diff --git a/api/wms_advertiser.h b/api/wms_advertiser.h
index d4091986..b5382b60 100644
--- a/api/wms_advertiser.h
+++ b/api/wms_advertiser.h
@@ -141,13 +141,9 @@ typedef void (*app_lib_advertiser_ackdatacb_f)
* APP_RES_INVALID_CONFIGURATION if device is not configured as
* @ref APP_LIB_SETTINGS_ROLE_ADVERTISER
*
- * Operation @ref app_lib_data_set_max_msg_queuing_time_f
- * "lib_data->setMaxMsgQueuingTime()" only allows setting the TTL value
- * in second precision. In CSMA-CA networks, the granularity of that service is
- * not enough. By using this service, advertiser can set the higher-precision
+ * By using this service, advertiser can set the higher-precision
* TTL and when advertiser sends data to CSMA-CA device, this TTL is also
- * checked (in addition to normal, second-granularity TTL set by @ref
- * app_lib_data_set_max_msg_queuing_time_f "lib_data->setMaxMsgQueuingTime()").
+ * checked.
* For time-slotted mode networks, this value has no impact due to nature of the
* time-slotted mode transmission. Neither this service has impact if device is
* not advertiser.
diff --git a/api/wms_data.h b/api/wms_data.h
index b088ed7b..bb992bb4 100644
--- a/api/wms_data.h
+++ b/api/wms_data.h
@@ -29,7 +29,7 @@
#define APP_LIB_DATA_NAME 0x0003f161 //!< "DATA"
/** \brief Maximum supported library version */
-#define APP_LIB_DATA_VERSION 0x20B
+#define APP_LIB_DATA_VERSION 0x20D
/**
* @brief Type of tracking ID for data packets
@@ -336,10 +336,6 @@ typedef struct
size_t num_bytes;
/** Destination address of packet */
app_addr_t dest_address;
- /** Initial end-to-end transmission delay, in 1 / 128 seconds. This could
- * be used, for example, to represent actual measurement time if done
- * earlier but generated for transmission on later time moment. */
- uint32_t delay;
/**
* Packet tracking ID
*/
@@ -691,56 +687,6 @@ typedef size_t
(*app_lib_data_get_app_config_num_bytes_f)(void);
-/**
- * \brief Set maximum queuing time for messages
- * \param priority
- * Message priority which queuing time to be set
- * \param time
- * Queuing time in seconds. Accepted range: 2 - 65534s.
- * Select queuing time carefully, too short value might cause
- * unnecessary message drops and too big value filling up message
- * queues. For consistent performance it is recommended to use the
- * same queuing time in the whole network.
- *
- * \note Minimum queuing time shall be bigger than access cycle
- * interval in time-slotted mode networks. It is recommended to use
- * multiples of access cycle interval (+ extra) to give time for
- * message repetitions, higher priority messages taking over the access
- * slot etc. Access cycle is not limiting the minimum value in
- * CSMA-CA networks.
- * \return Result code, @ref APP_RES_OK if successful
- * @ref APP_RES_INVALID_VALUE if unsupported message priority or time
- *
- * Example:
- * @code
- * // Set queueing time for low priority to 5 seconds
- * lib_data->setMaxMsgQueuingTime(APP_LIB_DATA_QOS_NORMAL, 5);
- * @endcode
- */
-typedef app_res_e
- (*app_lib_data_set_max_msg_queuing_time_f)(app_lib_data_qos_e priority,
- uint16_t time);
-
-/**
- * \brief Get maximum queuing time of messages
- * \param priority
- * Message priority which queuing time to be read
- * \param time_p
- * Pointer where to store maximum queuing time
- * \return Result code, @ref APP_RES_OK if ok,
- * @ref APP_RES_INVALID_VALUE if unsupported message priority,
- * @ref APP_RES_INVALID_NULL_POINTER if @p time_p is null
- *
- * Example:
- * @code
- * uint16_t qos_normal_qt;
- * lib_data->getMaxMsgQueuingTime(APP_LIB_DATA_QOS_NORMAL, &qos_normal_qt);
- * @endcode
- */
-typedef app_res_e
- (*app_lib_data_get_max_msg_queuing_time_f)(app_lib_data_qos_e priority,
- uint16_t * time_p);
-
/**
* \brief Write @ref appconfig "app config DATA"
* \param bytes
@@ -858,8 +804,6 @@ typedef struct
app_lib_data_allow_reception_f allowReception;
app_lib_data_read_app_config_f readAppConfig;
app_lib_data_get_app_config_num_bytes_f getAppConfigNumBytes;
- app_lib_data_set_max_msg_queuing_time_f setMaxMsgQueuingTime;
- app_lib_data_get_max_msg_queuing_time_f getMaxMsgQueuingTime;
app_lib_data_write_app_config_data_f writeAppConfigData;
app_lib_data_write_diagnostic_interval_f writeDiagnosticInterval;
app_lib_data_set_local_mc_f setLocalMulticastInfo;
diff --git a/api/wms_otap.h b/api/wms_otap.h
index d9dc9453..0a977d2a 100644
--- a/api/wms_otap.h
+++ b/api/wms_otap.h
@@ -30,7 +30,7 @@
#define APP_LIB_OTAP_NAME 0x000f2338 //!< "OTAP"
/** @brief Maximum supported library version */
-#define APP_LIB_OTAP_VERSION 0x201
+#define APP_LIB_OTAP_VERSION 0x202
/**
* @brief Different scratchpad type
@@ -109,9 +109,6 @@ typedef enum
* the given delay. Delay starts when node receive the information and the
* scratchpad is valid. */
APP_LIB_OTAP_ACTION_PROPAGATE_AND_PROCESS_WITH_DELAY = 3,
- /** Exchange and processing of scratchpad is managed the old way
- * (sequence comparison). */
- APP_LIB_OTAP_ACTION_LEGACY = 4,
} app_lib_otap_action_e;
/**
diff --git a/api/wms_radio_config.h b/api/wms_radio_config.h
index ad1b82cf..0f2b6a7d 100644
--- a/api/wms_radio_config.h
+++ b/api/wms_radio_config.h
@@ -32,6 +32,19 @@
/** @brief Maximum amount of configurable power levels */
#define APP_LIB_RADIO_CFG_POWER_MAX_CNT 10
+/** @brief Minimum configured radio current (10 x mA) */
+#define APP_LIB_RADIO_CFG_CURRENT_MIN 1
+
+/**
+ * @brief Maximum configured radio current (10 x mA)
+ *
+ * FCC allow maximum power for 2.4GHz to be roughly 600mA, so to be sure that
+ * we don't block the users from doing what they want, but also have some
+ * reasonable limit to root out obviously invalid values, we set the upper
+ * limit for current to be 10A.
+ */
+#define APP_LIB_RADIO_CFG_CURRENT_MAX 1000
+
/**
* @brief FEM control command from firmware to application
*
@@ -186,7 +199,7 @@ typedef struct
/** RX state current, unit [mA x 10] */
uint16_t rx_current;
/** RX LNA gain or 0 [dB] */
- int8_t rx_gain_dbm;
+ int8_t rx_gain_db;
/** Amount of power levels configured */
uint8_t power_count;
/** TX power level configuration / table.
diff --git a/api/wms_settings.h b/api/wms_settings.h
index bf17bc4a..a649d3a2 100644
--- a/api/wms_settings.h
+++ b/api/wms_settings.h
@@ -53,12 +53,16 @@
typedef uint32_t app_lib_settings_net_addr_t;
/**
- * @brief Network channel type definition.
- *
- * All nodes on the network must have the same network channel.
+ * @brief Channel type definition.
*/
typedef uint8_t app_lib_settings_net_channel_t;
+/**
+ * @brief Reserved value for definition of 'no channel' for @ref
+ * app_lib_settings_net_channel_t
+ */
+#define CHANNEL_NO_CHANNEL 0
+
typedef enum {
/** Sink in Low Energy mode */
APP_LIB_SETTINGS_ROLE_SINK_LE = 0x00,
@@ -541,10 +545,10 @@ typedef app_res_e
uint16_t * max_value_p);
/**
- * @brief Get access cycle range
+ * @brief Get access cycle range limits
*
- * Return the minimum and maximum access cycle value, in milliseconds, that can
- * be used when setting the access cycle range with the @ref
+ * Return the minimum and maximum for valid access cycle range, in milliseconds,
+ * that can be used when setting the access cycle range with the @ref
* app_lib_settings_set_ac_range_f "lib_settings->setAcRange"() function.
*
* @param min_value_p
diff --git a/api/wms_state.h b/api/wms_state.h
index 82f1058b..8e2cfb63 100644
--- a/api/wms_state.h
+++ b/api/wms_state.h
@@ -27,7 +27,7 @@
#define APP_LIB_STATE_NAME 0x02f9c165 //!< "STATE"
/** @brief Maximum supported library version */
-#define APP_LIB_STATE_VERSION 0x20D
+#define APP_LIB_STATE_VERSION 0x20E
/**
* @brief Macro for cost indicating "no route". Used in @ref
@@ -125,7 +125,7 @@ typedef struct
* is unknown for this neighbor. */
uint8_t cost;
/** Radio channel used by the neighbor */
- uint8_t channel;
+ app_lib_settings_net_channel_t channel;
/** Type of the neighbor. @ref app_lib_state_nbor_type_e */
uint8_t type;
/**
@@ -605,6 +605,13 @@ typedef app_res_e (*app_lib_state_scan_stop_f)(void);
typedef app_res_e (*app_lib_state_get_install_quality_f)
(app_lib_state_install_quality_t * qual_out);
+/**
+ * @brief Query cluster channel (i.e. operating channel) currently in use
+ * @return Cluster channel in use
+ */
+typedef app_lib_settings_net_channel_t (*app_lib_state_get_cluster_channel_t)
+ (void);
+
/**
* @brief List of library functions
*/
@@ -623,6 +630,7 @@ typedef struct
app_lib_state_scan_stop_f stopScanNbors;
app_lib_state_get_install_quality_f getInstallQual;
app_lib_state_set_stack_event_cb_f setOnStackEventCb;
+ app_lib_state_get_cluster_channel_t getClusterChannel;
} app_lib_state_t;
#endif /* APP_LIB_STATE_H_ */
diff --git a/board/bgm220-ek4314a/board.h b/board/bgm220-ek4314a/board.h
deleted file mode 100644
index b9f47f53..00000000
--- a/board/bgm220-ek4314a/board.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* Copyright 2020 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-/**
- * @file
- *
- * Board definition for a Silabs' board named as "Explorer Kit BGM220 Module"
- * Part number BGM220-EK4314A
- */
-#ifndef BOARD_BGM220_EK4314A_BOARD_H_
-#define BOARD_BGM220_EK4314A_BOARD_H_
-
-// Waps usart defines
-#define BOARD_USART_ID 0
-
-#define BOARD_USART_GPIO_PORT GPIO_PORTA
-#define BOARD_USART_TX_PIN 5
-#define BOARD_USART_RX_PIN 6
-
-// List of GPIO ports and pins for the LEDs on the board:
-#define BOARD_LED_PIN_LIST {{GPIO_PORTA, 4}}
-
-// Active high polarity for LEDs
-#define BOARD_LED_ACTIVE_LOW false
-
-// List of ext. ints, GPIO ports and pins for buttons on the board:
-// NOTE! EFR32xG22 can wake up from deep sleep (EM2) using GPIO input trigger
-// only from A or B ports. Having the button in port C prevents button
-// to be used for waking up from deep sleep.
-#define BOARD_BUTTON_PIN_LIST {{4, GPIO_PORTC, 7}}
-
-// Active low polarity for buttons
-#define BOARD_BUTTON_ACTIVE_LOW true
-
-// Board has external pull-up for buttons
-#define BOARD_BUTTON_INTERNAL_PULL false
-
-// Buttons use even external interrupts
-#define BOARD_BUTTON_USE_EVEN_INT true
-
-// Buttons use even external interrupts
-//#define BOARD_BUTTON_USE_EVEN_INT true
-
-#endif /* BOARD_BGM220_EK4314A_BOARD_H_ */
diff --git a/board/bgm220-ek4314a/config.mk b/board/bgm220-ek4314a/config.mk
deleted file mode 100644
index af400f43..00000000
--- a/board/bgm220-ek4314a/config.mk
+++ /dev/null
@@ -1,19 +0,0 @@
-# Mcu of the board
-MCU_FAMILY=efr
-MCU=efr32
-MCU_SUB=xg22
-MCU_MEM_VAR=xxxxf512
-
-# Radio of the module on the board
-radio=bgm220pc22hna
-
-# Hardware capabilities of the board
-## Is 32kHz crystal mounted on the board.
-board_hw_crystal_32k=yes
-## Is DCDC used on this board (must be yes for efr32xg22).
-board_hw_dcdc=yes
-## HFXO crystal characteristics
-board_hw_hfxo_ctune=120
-## LFXO crystal characteristics
-board_hw_lfxo_ctune=37
-board_hw_lfxo_gain=1
diff --git a/board/efr32_template/board.h b/board/efr32_template/board.h
deleted file mode 100644
index 86f29d11..00000000
--- a/board/efr32_template/board.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/* Copyright 2018 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-/**
- * @file
- *
- * Template to be used for EFR32 board definitions
- */
-
-#ifndef _BOARD_EFR32_TEMPLATE_BOARD_H_
-#define _BOARD_EFR32_TEMPLATE_BOARD_H_
-
-/**
- * @brief USART ID
- *
- * Valid values: 0, 1, ... (to match BOARD_USART)
- *
- * @note in order for application to use USART, see @ref
- * source_makefile_hal_uart "here".
- *
- */
-#define BOARD_USART_ID 0
-
-/**
- * @brief GPIO port used
- *
- * Valid values: GPIOA, GPIOB, ...
- */
-#define BOARD_USART_GPIO_PORT GPIOA
-/**
- * @brief RX routeloc definition
- *
- * Valid values: USART_ROUTELOC0_RXLOC_LOC0, USART_ROUTELOC0_RXLOC_LOC1,
- * ...
- */
-#define BOARD_USART_ROUTELOC_RXLOC USART_ROUTELOC0_RXLOC_LOC0
-/**
- * @brief TX routeloc definition
- *
- * Valid values: USART_ROUTELOC0_TXLOC_LOC0, USART_ROUTELOC0_TXLOC_LOC1,
- * ...
- */
-#define BOARD_USART_ROUTELOC_TXLOC USART_ROUTELOC0_TXLOC_LOC0
-
-/**
- * @brief Transmission pin number
- */
-#define BOARD_USART_TX_PIN 0
-/**
- * @brief Reception pin number
- */
-#define BOARD_USART_RX_PIN 1
-
-/**
- * @brief Interrupt pin for dual mcu app, unread indication
- *
- * This only used in @ref source/dualmcu_app.c "dualmcu_app" application to
- * announce with GPIO pin that there is incoming indication to be read from
- * device.
- *
- * It is optional definition. If not present, no irq pin is present
- */
-#define BOARD_UART_INT_PIN 8
-#define BOARD_UART_INT_PORT GPIOD
-
-/**
- * @brief LED definitions
- *
- * If board contains LEDs, they are defined here. If not defined, a dummy
- * LED driver is compiled, so that applications can use the LED driver
- * unconditionally.
- *
- * For Silabs EFR32 family, the list contains GPIO port/pin number pairs.
- *
- * @note in order for application to use LEDs, see @ref source_makefile_hal_led
- * "here".
- */
-#define BOARD_LED_PIN_LIST {{GPIOF, 4}, {GPIOF, 5}}
-
-/**
- * @brief LED GPIO polarity
- *
- * If LEDs turn on when the GPIO pin is driven low, this setting is true. Many
- * EFR32 boards, such as the Thunderboard Sense 2 and the BRD4001 Evaluation
- * Board have active high LEDs, so this setting should remain false.
- */
-#define BOARD_LED_ACTIVE_LOW false
-
-/**
- * @brief Button definitions
- *
- * Any buttons present on the board are defined here. If not defined, a dummy
- * button driver is compiled, so that applications can use the button driver
- * unconditionally.
- *
- * For Silabs EFR32 family, the list contains GPIO external interrupt numbers,
- * GPIO ports and pins. See \ref BOARD_BUTTON_USE_EVEN_INT below for extra
- * considerations when selecting external interrupt numbers.
- *
- * @note in order for application to use buttons, see @ref
- * source_makefile_hal_button "here".
- */
-#define BOARD_BUTTON_PIN_LIST {{4, GPIOF, 6}, {6, GPIOF, 7}}
-
-/**
- * @brief Button GPIO polarity
- *
- * If a button press pulls the GPIO pin low, this setting is true. This is the
- * case for many EFR32 boards, such as the Thunderboard Sense 2 and the BRD4001
- * Evaluation Board. Otherwise, if a button press pulls the GPIO pin high, this
- * setting should be set to false.
- */
-#define BOARD_BUTTON_ACTIVE_LOW true
-
-/**
- * @brief Button GPIO internal pull up/down
- *
- * Some buttons don't have any pull-up or pull-down resistor installed on the
- * board. They need it to be setup in software. Set
- * \ref BOARD_BUTTON_INTERNAL_PULL to true to enable internal pull-up(down).
- * Pull-up(down) is enabled when \ref BOARD_BUTTON_ACTIVE_LOW is true(false).
- */
-#define BOARD_BUTTON_INTERNAL_PULL true
-
-/**
- * @brief Button GPIO interrupt even/odd selection
- *
- * The EFR32 GPIO block has 16 configurable external interrupt sources. Even
- * and odd numbered interrupt sources are routed to separate interrupt vectors
- * in the processor. If this setting is true, the button interrupts use the
- * even interrupt vector GPIO_EVEN_IRQn, otherwise GPIO_ODD_IRQn.
- *
- * Not all GPIO pins can be mapped to all even or odd external interrupt
- * sources. Please see the GPIO_EXTIPINSELL and GPIO_EXTIPINSELH register
- * documentation in the EFR32xG12 Wireless Gecko Reference Manual.
- *
- * The external interrupt source in \ref BOARD_BUTTON_PIN_LIST above should
- * match this definition, otherwise the buttons won't work.
- */
-#define BOARD_BUTTON_USE_EVEN_INT true
-
-#endif /* _BOARD_EFR32_TEMPLATE_BOARD_H_ */
diff --git a/board/efr32_template/config.mk b/board/efr32_template/config.mk
deleted file mode 100644
index 602748ec..00000000
--- a/board/efr32_template/config.mk
+++ /dev/null
@@ -1,38 +0,0 @@
-# This definition describes mcu family.
-MCU_FAMILY=efr
-
-# This definition describes processor architecture.
-# Valid value: efr32 for EFR32 based boards
-MCU=efr32
-
-# This describes the sub-architecture of the processor. Allowed values are
-# following: xg12,xg21,xg22
-MCU_SUB=xg12
-
-# This definitions describes the processor memory variant. It is only used when
-# @ref config_mk_mcu "MCU" is efr32.
-# Valid values are following:
-# - pxxxf512 For 512 kB flash memory variant (xg12)
-# - xxxxf512 For 512 kB flash memory variant (xg22)
-# - pxxxf1024 For 1024 kB flash memory variant (xg12)
-# - xxxxf1024 For 1024 kB flash memory variant (xg21)
-MCU_MEM_VAR=pxxxf1024
-
-# Which radio version to use (different stack binary)
-# Must be set only for xg21 and xg22 only
-# Allowed values are following for xg21: efr32xg21, bgm210pa22jia
-# Allowed values are following for xg22: efr32xg22, bgm220pc22hna
-# radio=
-
-# This describes the hardware capabilities of the board
-# (this is used to customize the hardware service of the bootloader).
-## Is 32kHz crystal mounted on the board? default:yes, possible values:yes, no
-board_hw_crystal_32k=yes
-## Is DCDC to be enabled on the board? default:yes, possible values:yes, no
-## (it replaces MCU_NO_DCDC define in ./board/bootlaoder/early_init_efr32.c)
-board_hw_dcdc=yes
-## HFXO crystal characteristics
-board_hw_hfxo_ctune=322
-## LFXO crystal characteristics
-board_hw_lfxo_ctune=68
-board_hw_lfxo_gain=2
diff --git a/board/makefile b/board/makefile
index a84573bb..a6731cb5 100644
--- a/board/makefile
+++ b/board/makefile
@@ -37,3 +37,8 @@ endif
ifdef board_hw_lfxo_gain
CFLAGS += -DBOARD_HW_LFXO_GAIN=$(board_hw_lfxo_gain)
endif
+
+# FTDI enabled for serial communication
+ifeq ("$(board_use_ftdi)","yes")
+ CFLAGS += -DUSE_FTDI
+endif
diff --git a/board/mdbt50q_rx/board.h b/board/mdbt50q_rx/board.h
deleted file mode 100644
index a7eb2ef3..00000000
--- a/board/mdbt50q_rx/board.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* Copyright 2018 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-/**
- * @file
- *
- * Board definition for the
- * Raytac MDBT50Q-RX dongle
- */
-#ifndef BOARD_MDBT50Q_RX_H_
-#define BOARD_MDBT50Q_RX_H_
-
-
-// Serial port
-// There is no serial port but a USB connection
-
-
-// List of GPIO pins for the LEDs on the board: LED 1 P1.13 to LED 2 P1.11
-#define BOARD_LED_PIN_LIST {45, 43}
-
-// Active low polarity for LEDs
-#define BOARD_LED_ACTIVE_LOW true
-
-// List of GPIO pins for buttons on the board: Button 1 to Button 4
-#define BOARD_BUTTON_PIN_LIST {15}
-
-// Active low polarity for buttons
-#define BOARD_BUTTON_ACTIVE_LOW true
-
-// Active internal pull-up for buttons
-#define BOARD_BUTTON_INTERNAL_PULL true
-
-// The board supports DCDC (#define BOARD_SUPPORT_DCDC)
-// Since SDK v1.2 (stack v5.1.x) this option has been move to
-// board//config.mk. Set board_hw_dcdc to yes to enable DCDC.
-#ifdef BOARD_SUPPORT_DCDC
-#error This option has been moved to board//config.mk
-#endif
-
-#endif /* BOARD_MDBT50Q_RX_H_ */
diff --git a/board/mdbt50q_rx/config.mk b/board/mdbt50q_rx/config.mk
deleted file mode 100644
index f68ad8be..00000000
--- a/board/mdbt50q_rx/config.mk
+++ /dev/null
@@ -1,24 +0,0 @@
-# Mcu of the board
-MCU_FAMILY=nrf
-MCU=nrf52
-MCU_SUB=840
-
-# Hardware capabilities of the board
-## Is 32kHz crystal mounted on the board.
-board_hw_crystal_32k=yes
-## Is DCDC used on this board.
-board_hw_dcdc=yes
-
-uart_use_usb=yes
-
-# To be changed
-usb_vid=0xf00d
-usb_manufacturer_str="Raytac Wirepas"
-usb_product_str="Raytac Wirepas Dongle"
-
-# Uncomment, and set path to custom power table here, if set, the custom power
-# table will be set during application startup, and the stack will use that
-# instead of the default
-# For convenience, an example of a +4dBm power table is provided, uncomment the
-# line below to use that instead of the default +8dBm power table
-#RADIO_CUSTOM_POWER_TABLE=mcu/nrf/nrf52/hal/radio/radio_power_table_nrf52840_4dBm.h
diff --git a/board/nrf52832_mdk_v2/board.h b/board/nrf52832_mdk_v2/board.h
deleted file mode 100644
index 4110ce49..00000000
--- a/board/nrf52832_mdk_v2/board.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* Copyright 2020 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-/**
- * @file
- *
- * Board definition for the
- * nrf52832-MDK V2 kit
- */
-
-#ifndef _BOARD_NRF52832_MDK_V2_BOARD_H_
-#define _BOARD_NRF52832_MDK_V2_BOARD_H_
-
-// Serial port pins
-#define BOARD_USART_TX_PIN 20
-#define BOARD_USART_RX_PIN 19
-
-// List of GPIO pins for the LEDs on the board: LED R, G, B
-#define BOARD_LED_PIN_LIST {23, 22, 24}
-
-// Active low polarity for LEDs
-#define BOARD_LED_ACTIVE_LOW true
-
-// The board supports DCDC (#define BOARD_SUPPORT_DCDC)
-// Since SDK v1.2 (bootloader > v7) this option has been move to
-// board//config.mk.
-#ifdef BOARD_SUPPORT_DCDC
-#error This option has been moved to board//config.mk
-#endif
-
-#endif /* _BOARD_NRF52832_MDK_V2_BOARD_H_ */
diff --git a/board/nrf52832_mdk_v2/config.mk b/board/nrf52832_mdk_v2/config.mk
deleted file mode 100644
index a65764b1..00000000
--- a/board/nrf52832_mdk_v2/config.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-# Mcu of the board
-MCU_FAMILY=nrf
-MCU=nrf52
-MCU_SUB=832
-
-# Hardware capabilities of the board
-## Is 32kHz crystal mounted on the board.
-board_hw_crystal_32k=yes
-## Is DCDC used on this board.
-board_hw_dcdc=yes
\ No newline at end of file
diff --git a/board/nrf52_template/board.h b/board/nrf52_template/board.h
deleted file mode 100644
index 0ca5c91d..00000000
--- a/board/nrf52_template/board.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/* Copyright 2017 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-/**
- * @file
- *
- * Template to be used for nRF52 board definitions
- */
-
-#ifndef _BOARD_NRF52_TEMPLATE_BOARD_H_
-#define _BOARD_NRF52_TEMPLATE_BOARD_H_
-
-// Serial port pins
-/**
- * @brief Transmission pin number
- *
- * @note in order for application to use USART, see @ref
- * source_makefile_hal_uart "here".
- */
-#define BOARD_USART_TX_PIN 6
-/**
- * @brief Reception pin number
- */
-#define BOARD_USART_RX_PIN 8
-/**
- * @brief CTS pin number, for @ref USE_USART_HW_FLOW_CONTROL
- */
-#define BOARD_USART_CTS_PIN 7
-/**
- * @brief RTS pin number, for @ref USE_USART_HW_FLOW_CONTROL
- */
-#define BOARD_USART_RTS_PIN 5
-
-/**
- * @brief Interrupt pin for dual mcu app, unread indication
- *
- * This only used in @ref source/dualmcu_app.c "dualmcu_app" application to
- * announce with GPIO pin that there is incoming indication to be read from
- * device.
- *
- * It is optional definition. If not present, no irq pin is present
- */
-#define BOARD_UART_IRQ_PIN 11
-
-/**
- * @brief LED definitions
- *
- * If board contains LEDs, they are defined here. If not defined, a dummy
- * LED driver is compiled, so that applications can use the LED driver
- * unconditionally.
- *
- * For Nordic nRF52 family, LEDs are defined as list of GPIO pin numbers
- *
- * @note in order for application to use LEDs, see @ref source_makefile_hal_led
- * "here".
- */
-#define BOARD_LED_PIN_LIST {17, 18, 19, 20}
-
-/**
- * @brief LED GPIO polarity
- *
- * If LEDs turn on when the GPIO pin is driven low, this setting is true. This
- * is the case for many nRF52 boards, such as the PCA10040 and PCA10056.
- * Otherwise, if a LED is lit when the the GPIO pin is driven high, this
- * setting should be set to false.
- */
-#define BOARD_LED_ACTIVE_LOW true
-
-/**
- * @brief Button definitions
- *
- * Any buttons present on the board are defined here. If not defined, a dummy
- * button driver is compiled, so that applications can use the button driver
- * unconditionally.
-*
- * For Nordic nRF52 family, buttons are defined simply by the GPIO numbers.
- *
- * @note in order for application to use buttons, see @ref
- * source_makefile_hal_button "here".
- */
-#define BOARD_BUTTON_PIN_LIST {13, 14, 15, 16}
-
-/**
- * @brief Button GPIO polarity
- *
- * If a button press pulls the GPIO pin low, this setting is true. This is the
- * case for many nRF52 boards, such as the PCA10040 and PCA10056. Otherwise, if
- * a button press pulls the GPIO pin high, this setting should be set to false.
- */
-#define BOARD_BUTTON_ACTIVE_LOW true
-
-/**
- * @brief Button GPIO internal pull up/down
- *
- * Some buttons don't have any pull-up or pull-down resistor installed on the
- * board. They need it to be setup in software. Set
- * \ref BOARD_BUTTON_INTERNAL_PULL to true to enable internal pull-up(down).
- * Pull-up(down) is enabled when \ref BOARD_BUTTON_ACTIVE_LOW is true(false).
- */
-#define BOARD_BUTTON_INTERNAL_PULL true
-
-#endif /* _BOARD_NRF52_TEMPLATE_BOARD_H_ */
diff --git a/board/nrf52_template/config.mk b/board/nrf52_template/config.mk
deleted file mode 100644
index b538e8a8..00000000
--- a/board/nrf52_template/config.mk
+++ /dev/null
@@ -1,18 +0,0 @@
-# This definition describes mcu family.
-MCU_FAMILY=nrf
-
-# This definition describes processor architecture.
-# Valid value: nrf52 for nRF52 based boards
-MCU=nrf52
-
-# This describes the sub-architecture of the processor. Allowed values are
-# following: 832,840
-MCU_SUB=832
-
-# This describes the hardware capabilities of the board
-# (this is used to customize the hardware service of the bootloader).
-## Is 32kHz crystal mounted on the board? default:yes, possible values:yes, no
-board_hw_crystal_32k=yes
-## Is DCDC to be enabled on the board? default:yes, possible values:yes, no
-## (it replaces BOARD_SUPPORT_DCDC define in board.h)
-board_hw_dcdc=yes
diff --git a/board/pan1780/board.h b/board/pan1780/board.h
deleted file mode 100644
index ba8c2830..00000000
--- a/board/pan1780/board.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/* Copyright 2021 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-/**
- * @file
- *
- * Board definition for the
- * Panasonic PAN1780 evaluation board
- */
-#ifndef BOARD_PAN1780_BOARD_H_
-#define BOARD_PAN1780_BOARD_H_
-
-// NRF_GPIO is mapped to NRF_P0 , for pins P0.00 ... P0.31
-// Use NRF_P1 for pins P1.00 ... P1.15
-// With nrf_gpio.h, use SW_pin (logical pins, port-aware)
-
-/**
-NRF_P0 SW_pin PAN1780 Notes (recommended usage)
------------------------------------------------------------------
-P0.00 0 [XTAL 32k]
-P0.01 1 [XTAL 32k]
-P0.02 2 gpio/AIN0 (low freq)
-P0.03 3 gpio/AIN1 (low freq)
-P0.04 4 gpio/AIN2
-P0.05 5 UART_RTS
-P0.06 6 UART_TX
-P0.07 7 UART_CTS
-P0.08 8 UART_RX
-P0.09 9 gpio/NFC1 (low freq)
-P0.10 10 gpio/NFC2 (low freq)
-P0.11 11 nBUTTON1
-P0.12 12 nBUTTON2/SPI1 nSS
-P0.13 13 nLED1/SPI1 MOSI
-P0.14 14 nLED2/SPI1 MISO
-P0.15 15 nLED3/SPI1 SCK
-P0.16 16 nLED4
-P0.17 17 IRQ
-P0.18 18 RESET
-P0.19 19
-P0.20 20
-P0.21 21
-P0.22 22
-P0.23 23
-P0.24 24 nBUTTON3
-P0.25 25 nBUTTON4
-P0.26 26 I2C SDA
-P0.27 27 I2C SCL
-P0.28 28 gpio/AIN4 (low freq)
-P0.29 29 gpio/AIN5 (low freq)
-P0.30 30 gpio/AIN6 (low freq)
-P0.31 31 gpio/AIN7 (low freq)
-
-NRF_P1:
-P1.00 32 P1.00 (QSPI)
-P1.01 33 UART4 Tx (low freq)
-P1.02 34 UART4 Rx (low freq)
-P1.03 35 gpio (low freq)
-P1.04 36 gpio (low freq)
-P1.05 37 gpio (low freq)
-P1.06 38 gpio (low freq)
-P1.07 39 gpio (low freq)
-P1.08 40 gpio
-P1.09 41 gpio
-P1.10 42 gpio (low freq)
-P1.11 43 gpio (low freq)
-P1.12 44 gpio (low freq)
-P1.13 45 gpio (low freq)
-P1.14 46 gpio (low freq)
-P1.15 47 gpio (low freq)
-*/
-
-// Interrupt pin for dual mcu app, unread indication
-#define BOARD_UART_IRQ_PIN 17
-
-// Serial port pins
-#define BOARD_USART_TX_PIN 6
-#define BOARD_USART_RX_PIN 8
-#define BOARD_USART_CTS_PIN 7 /* For USE_USART_HW_FLOW_CONTROL */
-#define BOARD_USART_RTS_PIN 5 /* For USE_USART_HW_FLOW_CONTROL */
-
-// List of GPIO pins for the LEDs on the board: LED 1 to LED 4
-#define BOARD_LED_PIN_LIST {13, 14, 15, 16}
-
-// Active low polarity for LEDs
-#define BOARD_LED_ACTIVE_LOW true
-
-// List of GPIO pins for buttons on the board: Button 1 to Button 4
-#define BOARD_BUTTON_PIN_LIST {11, 12, 24, 25}
-
-// Active low polarity for buttons
-#define BOARD_BUTTON_ACTIVE_LOW true
-
-// Active internal pull-up for buttons
-#define BOARD_BUTTON_INTERNAL_PULL true
-
-
-#endif /* BOARD_PAN1780_BOARD_H_ */
diff --git a/board/pan1780/config.mk b/board/pan1780/config.mk
deleted file mode 100644
index 8a243c10..00000000
--- a/board/pan1780/config.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-# Mcu of the board
-MCU_FAMILY=nrf
-MCU=nrf52
-MCU_SUB=840
-
-# Hardware capabilities of the board
-## Is 32kHz crystal mounted on the board.
-board_hw_crystal_32k=yes
-## Is DCDC used on this board.
-board_hw_dcdc=yes
-
-# Uncomment, and set path to custom power table here, if set, the custom power
-# table will be set during application startup, and the stack will use that
-# instead of the default
-# For convenience, an example of a +4dBm power table is provided, uncomment the
-# line below to use that instead of the default +8dBm power table
-#RADIO_CUSTOM_POWER_TABLE=mcu/nrf/nrf52/hal/radio/radio_power_table_nrf52840_4dBm.h
diff --git a/board/pca10040/board.h b/board/pca10040/board.h
deleted file mode 100644
index 0b8a776c..00000000
--- a/board/pca10040/board.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* Copyright 2017 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-/**
- * @file
- *
- * Board definition for the
- * Nordic semiconductor PCA10040 evaluation board
- */
-#ifndef BOARD_PCA10040_BOARD_H_
-#define BOARD_PCA10040_BOARD_H_
-
-// Interrupt pin for dual mcu app, unread indication
-#define BOARD_UART_IRQ_PIN 11
-
-// Serial port pins
-#define BOARD_USART_TX_PIN 6
-#define BOARD_USART_RX_PIN 8
-#define BOARD_USART_CTS_PIN 7 /* For USE_USART_HW_FLOW_CONTROL */
-#define BOARD_USART_RTS_PIN 5 /* For USE_USART_HW_FLOW_CONTROL */
-
-// Pwm output for pwm_driver app
-#define BOARD_PWM_OUTPUT_GPIO 28
-
-// List of GPIO pins for the LEDs on the board: LED 1 to LED 4
-#define BOARD_LED_PIN_LIST {17, 18, 19, 20}
-
-// Active low polarity for LEDs
-#define BOARD_LED_ACTIVE_LOW true
-
-// List of GPIO pins for buttons on the board: Button 1 to Button 4
-#define BOARD_BUTTON_PIN_LIST {13, 14, 15, 16}
-
-// Active low polarity for buttons
-#define BOARD_BUTTON_ACTIVE_LOW true
-
-// Active internal pull-up for buttons
-#define BOARD_BUTTON_INTERNAL_PULL true
-
-// The board supports DCDC (#define BOARD_SUPPORT_DCDC)
-// Since SDK v1.2 (bootloader > v7) this option has been move to
-// board//config.mk. Set board_hw_dcdc to yes to enable DCDC.
-#ifdef BOARD_SUPPORT_DCDC
-#error This option has been moved to board//config.mk
-#endif
-
-
-
-#endif /* BOARD_PCA10040_BOARD_H_ */
diff --git a/board/pca10040/config.mk b/board/pca10040/config.mk
deleted file mode 100644
index a65764b1..00000000
--- a/board/pca10040/config.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-# Mcu of the board
-MCU_FAMILY=nrf
-MCU=nrf52
-MCU_SUB=832
-
-# Hardware capabilities of the board
-## Is 32kHz crystal mounted on the board.
-board_hw_crystal_32k=yes
-## Is DCDC used on this board.
-board_hw_dcdc=yes
\ No newline at end of file
diff --git a/board/pca10056/board.h b/board/pca10056/board.h
deleted file mode 100644
index 9e109c9d..00000000
--- a/board/pca10056/board.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/* Copyright 2018 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-/**
- * @file
- *
- * Board definition for the
- * Nordic semiconductor PCA10056 evaluation board
- */
-#ifndef BOARD_PCA10056_BOARD_H_
-#define BOARD_PCA10056_BOARD_H_
-
-// NRF_GPIO is mapped to NRF_P0 , for pins P0.00 ... P0.31
-// Use NRF_P1 for pins P1.00 ... P1.15
-// With nrf_gpio.h, use SW_pin (logical pins, port-aware)
-
-/**
-NRF_P0 SW_pin PCA10056 PCA10059 Notes (recommended usage)
-------------------------------------------------------------------------
-P0.00 0 [XTAL 32k] [XTAL 32k]
-P0.01 1 [XTAL 32k] [XTAL 32k]
-P0.02 2 gpio/AIN0 0.02 (low freq)
-P0.03 3 gpio/AIN1 - (low freq)
-P0.04 4 gpio/AIN2 0.04
-P0.05 5 UART_RTS -
-P0.06 6 UART_TX nLED1
-P0.07 7 UART_CTS -
-P0.08 8 UART_RX nLED2red
-P0.09 9 gpio/NFC1 0.09 (low freq)
-P0.10 10 gpio/NFC2 0.10 (low freq)
-P0.11 11 gpio/nBUTTON1 0.11
-P0.12 12 gpio/nBUTTON2 nLED2blue
-P0.13 13 gpio/nLED1 0.13
-P0.14 14 gpio/nLED2 0.14
-P0.15 15 gpio/nLED3 0.15
-P0.16 16 gpio/nLED4 -
-P0.17 17 gpio/FLASH 0.17
-P0.18 18 nRESET nRESET
-P0.19 19 gpio/FLASH nRESET (QSPI/SCK)
-P0.20 20 gpio/FLASH 0.20
-P0.21 21 gpio/FLASH nRESET (QSPI)
-P0.22 22 gpio/FLASH 0.22 (QSPI)
-P0.23 23 gpio/FLASH nRESET (QSPI)
-P0.24 24 gpio/nBUTTON3 0.24
-P0.25 25 gpio/nBUTTON4 nRESET
-P0.26 26 gpio 0.26
-P0.27 27 gpio -
-P0.28 28 gpio/AIN4 - (low freq)
-P0.29 29 gpio/AIN5 0.29 (low freq)
-P0.30 30 gpio/AIN6 - (low freq)
-P0.31 31 gpio/AIN7 0.31 (low freq)
-
-NRF_P1:
-P1.00 32 gpio/SWO 1.00 (QSPI)
-P1.01 33 gpio 1.01 (low freq)
-P1.02 34 gpio 1.02 (low freq)
-P1.03 35 gpio - (low freq)
-P1.04 36 gpio 1.04 (low freq)
-P1.05 37 gpio - (low freq)
-P1.06 38 gpio nSW1 (low freq)
-P1.07 39 gpio 1.07 (low freq)
-P1.08 40 gpio -
-P1.09 41 gpio nLED2green
-P1.10 42 gpio 1.10 (low freq)
-P1.11 43 gpio 1.11 (low freq)
-P1.12 44 gpio - (low freq)
-P1.13 45 gpio 1.13 (low freq)
-P1.14 46 gpio - (low freq)
-P1.15 47 gpio 1.15 (low freq)
-*/
-
-// Interrupt pin for dual mcu app, unread indication
-#define BOARD_UART_IRQ_PIN 11
-
-// Serial port pins
-#define BOARD_USART_TX_PIN 6
-#define BOARD_USART_RX_PIN 8
-#define BOARD_USART_CTS_PIN 7 /* For USE_USART_HW_FLOW_CONTROL */
-#define BOARD_USART_RTS_PIN 5 /* For USE_USART_HW_FLOW_CONTROL */
-
-// Pwm output for pwm_driver app
-#define BOARD_PWM_OUTPUT_GPIO 28
-
-// List of GPIO pins for the LEDs on the board: LED 1 to LED 4
-#define BOARD_LED_PIN_LIST {13, 14, 15, 16}
-
-// Active low polarity for LEDs
-#define BOARD_LED_ACTIVE_LOW true
-
-// List of GPIO pins for buttons on the board: Button 1 to Button 4
-#define BOARD_BUTTON_PIN_LIST {11, 12, 24, 25}
-
-// Active low polarity for buttons
-#define BOARD_BUTTON_ACTIVE_LOW true
-
-// Active internal pull-up for buttons
-#define BOARD_BUTTON_INTERNAL_PULL true
-
-// The board supports DCDC (#define BOARD_SUPPORT_DCDC)
-// Since SDK v1.2 (bootloader > v7) this option has been move to
-// board//config.mk. Set board_hw_dcdc to yes to enable DCDC.
-#ifdef BOARD_SUPPORT_DCDC
-#error This option has been moved to board//config.mk
-#endif
-
-
-#endif /* BOARD_PCA10056_BOARD_H_ */
diff --git a/board/pca10056/config.mk b/board/pca10056/config.mk
deleted file mode 100644
index 8a243c10..00000000
--- a/board/pca10056/config.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-# Mcu of the board
-MCU_FAMILY=nrf
-MCU=nrf52
-MCU_SUB=840
-
-# Hardware capabilities of the board
-## Is 32kHz crystal mounted on the board.
-board_hw_crystal_32k=yes
-## Is DCDC used on this board.
-board_hw_dcdc=yes
-
-# Uncomment, and set path to custom power table here, if set, the custom power
-# table will be set during application startup, and the stack will use that
-# instead of the default
-# For convenience, an example of a +4dBm power table is provided, uncomment the
-# line below to use that instead of the default +8dBm power table
-#RADIO_CUSTOM_POWER_TABLE=mcu/nrf/nrf52/hal/radio/radio_power_table_nrf52840_4dBm.h
diff --git a/board/pca10059/board.h b/board/pca10059/board.h
deleted file mode 100644
index 6a27fc36..00000000
--- a/board/pca10059/board.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/* Copyright 2018 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-/**
- * @file
- *
- * Board definition for the
- * Nordic semiconductor PCA10059 Dongle
- */
-#ifndef BOARD_PCA10059_BOARD_H_
-#define BOARD_PCA10059_BOARD_H_
-
-// PCA10059 nRF52840 USB Dongle
-// Note: This board is powered by USB +5V directly to MCU VDDH.
-// Do not try to use the new VDDH-related DCDC0 converter without understanding
-// the chip errata 197 and 202 (i.e. prefer to use REG0 in default LDO mode).
-// The default I/O voltage (VDD) is 1.8V in this configuration. To change that,
-// use first_boot() to set the correct I/O voltage (UICR->REGOUT0).
-// The old nrf52832-style DCDC can still be used.
-
-// NRF_GPIO is mapped to NRF_P0 , for pins P0.00 ... P0.31
-// Use NRF_P1 for pins P1.00 ... P1.15
-// With nrf_gpio.h, use SW_pin (logical pins, port-aware)
-
-/**
-NRF_P0 SW_pin PCA10056 PCA10059 Notes (recommended usage)
-------------------------------------------------------------------------
-P0.00 0 [XTAL 32k] [XTAL 32k]
-P0.01 1 [XTAL 32k] [XTAL 32k]
-P0.02 2 gpio/AIN0 0.02 (low freq)
-P0.03 3 gpio/AIN1 - (low freq)
-P0.04 4 gpio/AIN2 0.04
-P0.05 5 UART_RTS -
-P0.06 6 UART_TX nLED1
-P0.07 7 UART_CTS -
-P0.08 8 UART_RX nLED2red
-P0.09 9 gpio/NFC1 0.09 (low freq)
-P0.10 10 gpio/NFC2 0.10 (low freq)
-P0.11 11 gpio/nBUTTON1 0.11
-P0.12 12 gpio/nBUTTON2 nLED2blue
-P0.13 13 gpio/nLED1 0.13
-P0.14 14 gpio/nLED2 0.14
-P0.15 15 gpio/nLED3 0.15
-P0.16 16 gpio/nLED4 -
-P0.17 17 gpio/FLASH 0.17
-P0.18 18 nRESET nRESET
-P0.19 19 gpio/FLASH nRESET (QSPI/SCK)
-P0.20 20 gpio/FLASH 0.20
-P0.21 21 gpio/FLASH nRESET (QSPI)
-P0.22 22 gpio/FLASH 0.22 (QSPI)
-P0.23 23 gpio/FLASH nRESET (QSPI)
-P0.24 24 gpio/nBUTTON3 0.24
-P0.25 25 gpio/nBUTTON4 nRESET
-P0.26 26 gpio 0.26
-P0.27 27 gpio -
-P0.28 28 gpio/AIN4 - (low freq)
-P0.29 29 gpio/AIN5 0.29 (low freq)
-P0.30 30 gpio/AIN6 - (low freq)
-P0.31 31 gpio/AIN7 0.31 (low freq)
-
-NRF_P1:
-P1.00 32 gpio/SWO 1.00 (QSPI)
-P1.01 33 gpio 1.01 (low freq)
-P1.02 34 gpio 1.02 (low freq)
-P1.03 35 gpio - (low freq)
-P1.04 36 gpio 1.04 (low freq)
-P1.05 37 gpio - (low freq)
-P1.06 38 gpio nSW1 (low freq)
-P1.07 39 gpio 1.07 (low freq)
-P1.08 40 gpio -
-P1.09 41 gpio nLED2green
-P1.10 42 gpio 1.10 (low freq)
-P1.11 43 gpio 1.11 (low freq)
-P1.12 44 gpio - (low freq)
-P1.13 45 gpio 1.13 (low freq)
-P1.14 46 gpio - (low freq)
-P1.15 47 gpio 1.15 (low freq)
-*/
-
-// Serial port pins
-#define BOARD_USART_TX_PIN 29
-#define BOARD_USART_RX_PIN 31
-#define BOARD_USART_CTS_PIN 7 /* For USE_USART_HW_FLOW_CONTROL */
-#define BOARD_USART_RTS_PIN 5 /* For USE_USART_HW_FLOW_CONTROL */
-
-// Pwm output for pwm_driver app
-#define BOARD_PWM_OUTPUT_GPIO 4
-
-// List of GPIO pins for the LEDs on the board: LD1, LD2 R, G, B
-#define BOARD_LED_PIN_LIST {6, 8, 41, 12}
-
-// Active low polarity for LEDs
-#define BOARD_LED_ACTIVE_LOW true
-
-// List of GPIO pins for buttons on the board: SW1
-//#define BOARD_BUTTON_PIN_LIST {38}
-
-// Active low polarity for buttons
-#define BOARD_BUTTON_ACTIVE_LOW true
-
-// Active internal pull-up for buttons
-#define BOARD_BUTTON_INTERNAL_PULL true
-
-// The board supports DCDC (#define BOARD_SUPPORT_DCDC)
-// Since SDK v1.2 (bootloader > v7) this option has been move to
-// board//config.mk. Set board_hw_dcdc to yes to enable DCDC.
-#ifdef BOARD_SUPPORT_DCDC
-#error This option has been moved to board//config.mk
-#endif
-
-
-#endif /* BOARD_PCA10059_BOARD_H_ */
diff --git a/board/pca10059/board_custom_init.c b/board/pca10059/board_custom_init.c
deleted file mode 100644
index f3376efc..00000000
--- a/board/pca10059/board_custom_init.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* Copyright 2020 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-#include "api.h"
-
-void Board_custom_init()
-{
- // Mark two channels as reserved
- // In fact because of hardware issue, channels BLE #13 (2432 MHz)
- // and BLE #29 (2464 MHz) are unusable.
- // It corresponds to channel #14 and #30 in Wirepas space.
-
- // It doesn't prevent usage of those channels by other boards in the
- // network but at least this board will prevent the usage of those channels
- // for its own cluster channel.
- uint8_t res_chns[4];
-
- // Channel 1 is bit 0 of byte 0 :
- // - channel 14 is bit 5 (14 mod 8) of byte 1 (14 / 8)
- // - channel 30 is bit 5 (30 mod 8) of byte 3 (30 / 8)
-
- res_chns[0] = 0;
- res_chns[1] = 1 << 5;
- res_chns[2] = 0;
- res_chns[3] = 1 << 5;
-
- lib_settings->setReservedChannels(res_chns, sizeof(res_chns));
-}
-
diff --git a/board/pca10059/config.mk b/board/pca10059/config.mk
deleted file mode 100644
index 8a243c10..00000000
--- a/board/pca10059/config.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-# Mcu of the board
-MCU_FAMILY=nrf
-MCU=nrf52
-MCU_SUB=840
-
-# Hardware capabilities of the board
-## Is 32kHz crystal mounted on the board.
-board_hw_crystal_32k=yes
-## Is DCDC used on this board.
-board_hw_dcdc=yes
-
-# Uncomment, and set path to custom power table here, if set, the custom power
-# table will be set during application startup, and the stack will use that
-# instead of the default
-# For convenience, an example of a +4dBm power table is provided, uncomment the
-# line below to use that instead of the default +8dBm power table
-#RADIO_CUSTOM_POWER_TABLE=mcu/nrf/nrf52/hal/radio/radio_power_table_nrf52840_4dBm.h
diff --git a/board/pca10059/makefile_board.mk b/board/pca10059/makefile_board.mk
deleted file mode 100644
index 477a1112..00000000
--- a/board/pca10059/makefile_board.mk
+++ /dev/null
@@ -1,2 +0,0 @@
-# Add board specific sources here, if any
-SRCS += board/$(target_board)/board_custom_init.c
diff --git a/board/pca10100/board.h b/board/pca10100/board.h
deleted file mode 100644
index b4f6f923..00000000
--- a/board/pca10100/board.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* Copyright 2020 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-/**
- * @file
- *
- * Board definition for the
- * Nordic semiconductor PCA10100 evaluation board
- */
-#ifndef BOARD_PCA10100_BOARD_H_
-#define BOARD_PCA10100_BOARD_H_
-
-// NRF_GPIO is mapped to NRF_P0 , for pins P0.00 ... P0.31
-// Use NRF_P1 for pins P1.00 ... P1.09
-// With nrf_gpio.h, use SW_pin (logical pins, port-aware)
-
-/**
-NRF_P0 SW_pin PCA10056 Notes (recommended usage)
------------------------------------------------------------
-P0.00 0 [XTAL 32k]
-P0.01 1 [XTAL 32k]
-P0.02 2 gpio/AIN0 (low freq)
-P0.03 3 gpio/AIN1 (low freq)
-P0.04 4 gpio/AIN2
-P0.05 5 UART_RTS (gpio/AIN3)
-P0.06 6 UART_TX
-P0.07 7 UART_CTS (gpio/TRACECLK)
-P0.08 8 UART_RX
-P0.09 9 gpio/NFC1 (low freq)
-P0.10 10 gpio/NFC2 (low freq)
-P0.11 11 gpio/nBUTTON1
-P0.12 12 gpio/nBUTTON2
-P0.13 13 gpio/nLED1
-P0.14 14 gpio/nLED2
-P0.15 15 gpio/nLED3
-P0.16 16 gpio/nLED4
-P0.17 17 gpio
-P0.18 18 nRESET
-P0.19 19 gpio
-P0.20 20 gpio
-P0.21 21 gpio
-P0.22 22 gpio
-P0.23 23 gpio
-P0.24 24 gpio/nBUTTON3
-P0.25 25 gpio/nBUTTON4
-P0.26 26 gpio
-P0.27 27 gpio
-P0.28 28 gpio/AIN4 (low freq)
-P0.29 29 gpio/AIN5 (low freq)
-P0.30 30 gpio/AIN6 (low freq)
-P0.31 31 gpio/AIN7 (low freq)
-
-NRF_P1:
-P1.00 32 gpio/SWO
-P1.01 33 gpio (low freq)
-P1.02 34 gpio (low freq)
-P1.03 35 gpio (low freq)
-P1.04 36 gpio (low freq)
-P1.05 37 gpio (low freq)
-P1.06 38 gpio (low freq)
-P1.07 39 gpio (low freq)
-P1.08 40 gpio
-P1.09 41 gpio
-*/
-
-// Interrupt pin for dual mcu app, unread indication
-#define BOARD_UART_IRQ_PIN 11
-
-// Serial port pins
-#define BOARD_USART_TX_PIN 6
-#define BOARD_USART_RX_PIN 8
-#define BOARD_USART_CTS_PIN 7 /* For USE_USART_HW_FLOW_CONTROL */
-#define BOARD_USART_RTS_PIN 5 /* For USE_USART_HW_FLOW_CONTROL */
-
-// Pwm output for pwm_driver app
-#define BOARD_PWM_OUTPUT_GPIO 28
-
-// List of GPIO pins for the LEDs on the board: LED 1 to LED 4
-#define BOARD_LED_PIN_LIST {13, 14, 15, 16}
-
-// Active low polarity for LEDs
-#define BOARD_LED_ACTIVE_LOW true
-
-// List of GPIO pins for buttons on the board: Button 1 to Button 4
-#define BOARD_BUTTON_PIN_LIST {11, 12, 24, 25}
-
-// Active low polarity for buttons
-#define BOARD_BUTTON_ACTIVE_LOW true
-
-// Active internal pull-up for buttons
-#define BOARD_BUTTON_INTERNAL_PULL true
-
-// The board supports DCDC (#define BOARD_SUPPORT_DCDC)
-// Since SDK v1.2 (bootloader > v7) this option has been move to
-// board//config.mk. Set board_hw_dcdc to yes to enable DCDC.
-#ifdef BOARD_SUPPORT_DCDC
-#error This option has been moved to board//config.mk
-#endif
-
-
-#endif /* BOARD_PCA10100_BOARD_H_ */
diff --git a/board/pca10100/config.mk b/board/pca10100/config.mk
deleted file mode 100644
index 9bba9388..00000000
--- a/board/pca10100/config.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-# Mcu of the board
-MCU_FAMILY=nrf
-MCU=nrf52
-MCU_SUB=833
-
-# Hardware capabilities of the board
-## Is 32kHz crystal mounted on the board.
-board_hw_crystal_32k=yes
-## Is DCDC used on this board.
-board_hw_dcdc=yes
\ No newline at end of file
diff --git a/board/pca10112/board.h b/board/pca10112/board.h
deleted file mode 100644
index d8b87907..00000000
--- a/board/pca10112/board.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/* Copyright 2018 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-/**
- * @file
- *
- * Board definition for the
- * Nordic semiconductor PCA10112
- */
-#ifndef BOARD_PCA10112_BOARD_H_
-#define BOARD_PCA10112_BOARD_H_
-
-// PCA10112 nRF52840 SoC + nRF21540 FEM
-// NRF_GPIO is mapped to NRF_P0 , for pins P0.00 ... P0.31
-// Use NRF_P1 for pins P1.00 ... P1.15
-// With nrf_gpio.h, use SW_pin (logical pins, port-aware)
-
-/**
-NRF_P0 SW_pin PCA10112 Notes (recommended usage)
-------------------------------------------------------------------------
-P0.00 0 [XTAL 32k]
-P0.01 1 [XTAL 32k]
-P0.02 2 gpio/AIN0 (low freq)
-P0.03 3 gpio/AIN1 (low freq)
-P0.04 4 gpio/AIN2
-P0.05 5 UART_RTS
-P0.06 6 UART_TX
-P0.07 7 UART_CTS
-P0.08 8 UART_RX
-P0.09 9 gpio/NFC1 (low freq)
-P0.10 10 gpio/NFC2 (low freq)
-P0.11 11 gpio/nBUTTON1
-P0.12 12 gpio/nBUTTON2
-P0.13 13 gpio/nLED1
-P0.14 14 gpio/nLED2
-P0.15 15 gpio/nLED3
-P0.16 16 gpio/nLED4
-P0.17 17 gpio/FEM_MODE
-P0.18 18 nRESET
-P0.19 19 gpio/FEM_RXEN
-P0.20 20 gpio/FEM_ANTSEL
-P0.21 21 gpio/FEM_CS
-P0.22 22 gpio/FEM_TXEN
-P0.23 23 gpio/FEM_PDN
-P0.24 24 gpio/nBUTTON3
-P0.25 25 gpio/nBUTTON4
-P0.26 26 gpio
-P0.27 27 gpio
-P0.28 28 gpio/AIN4 (low freq)
-P0.29 29 gpio/AIN5 (low freq)
-P0.30 30 gpio/AIN6 (low freq)
-P0.31 31 gpio/AIN7 (low freq)
-
-NRF_P1:
-P1.00 32 gpio/SWO
-P1.01 33 gpio (low freq)
-P1.02 34 gpio (low freq)
-P1.03 35 gpio (low freq)
-P1.04 36 gpio (low freq)
-P1.05 37 gpio (low freq)
-P1.06 38 gpio (low freq)
-P1.07 39 gpio (low freq)
-P1.08 40 gpio
-P1.09 41 gpio
-P1.10 42 gpio (low freq)
-P1.11 43 gpio (low freq)
-P1.12 44 gpio (low freq)
-P1.13 45 FEM_MISO (low freq)
-P1.14 46 FEM_MOSI (low freq)
-P1.15 47 FEM_CLK (low freq)
-*/
-
-// Serial port pins
-#define BOARD_USART_TX_PIN 6
-#define BOARD_USART_RX_PIN 8
-#define BOARD_USART_CTS_PIN 7 /* For USE_USART_HW_FLOW_CONTROL */
-#define BOARD_USART_RTS_PIN 5 /* For USE_USART_HW_FLOW_CONTROL */
-
-// Pwm output for pwm_driver app
-#define BOARD_PWM_OUTPUT_GPIO 28
-
-// List of GPIO pins for the LEDs on the board: LED 1 to LED 4
-#define BOARD_LED_PIN_LIST {13, 14, 15, 16}
-
-// Active low polarity for LEDs
-#define BOARD_LED_ACTIVE_LOW true
-
-// List of GPIO pins for buttons on the board: Button 1 to Button 4
-#define BOARD_BUTTON_PIN_LIST {11, 12, 24, 25}
-
-// Active low polarity for buttons
-#define BOARD_BUTTON_ACTIVE_LOW true
-
-// The board supports DCDC (#define BOARD_SUPPORT_DCDC)
-// Since SDK v1.2 (bootloader > v7) this option has been move to
-// board//config.mk. Set board_hw_dcdc to yes to enable DCDC.
-#ifdef BOARD_SUPPORT_DCDC
-#error This option has been moved to board//config.mk
-#endif
-
-// FEM control
-#define BOARD_FEM_MODE_PIN 17 // P0.17
-#define BOARD_FEM_RXEN_PIN 19 // P0.19
-#define BOARD_FEM_ANTSEL_PIN 20 // P0.20
-#define BOARD_FEM_CS_PIN 21 // P0.21
-#define BOARD_FEM_TXEN_PIN 22 // P0.22
-#define BOARD_FEM_PDN_PIN 23 // P0.23
-
-// FEM SPI (not used for anything)
-#define BOARD_FEM_SPI_MOSI_PIN 45 // P1.13
-#define BOARD_FEM_SPI_MISO_PIN 46 // P1.14
-#define BOARD_FEM_SPI_CLK_PIN 47 // P1.15
-
-// Initialize FEM
-void Fem_init(void);
-
-
-#endif /* BOARD_PCA10112_BOARD_H_ */
diff --git a/board/pca10112/board_custom_init.c b/board/pca10112/board_custom_init.c
deleted file mode 100644
index 79237432..00000000
--- a/board/pca10112/board_custom_init.c
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2019 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-#include "mcu.h"
-#include "board.h"
-
-void Board_custom_init(void)
-{
- // This board requires FEM driver, as there is no bypass mode. The stack
- // _must_ control it for the RF to work.
- Fem_init();
-}
-
diff --git a/board/pca10112/config.mk b/board/pca10112/config.mk
deleted file mode 100644
index cf243d9f..00000000
--- a/board/pca10112/config.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-# Mcu of the board
-MCU_FAMILY=nrf
-MCU=nrf52
-MCU_SUB=840
-
-# Hardware capabilities of the board
-## Is 32kHz crystal mounted on the board.
-board_hw_crystal_32k=yes
-## Is DCDC used on this board.
-board_hw_dcdc=yes
diff --git a/board/pca10112/fem_driver_nrf21540.c b/board/pca10112/fem_driver_nrf21540.c
deleted file mode 100644
index 07cfd784..00000000
--- a/board/pca10112/fem_driver_nrf21540.c
+++ /dev/null
@@ -1,226 +0,0 @@
-/* Copyright 2019 Wirepas Ltd. All Rights Reserved.
- *
- * Reference FEM driver for nRF21540 FEM.
- *
- * radio FEM == Front End Module (aka AFE == Analog Front End).
- * Can be used as template for custom implementation.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-#include
-#include
-#include "mcu.h"
-#include "api.h"
-#include "board.h"
-
-// --------------- Radio configuration -----------------------------------------
-// This example sets up the FEM with +10dB PA gain, +13 dB LNA gain, for use
-// with the 2.4GHz ISM band in Europe and areas where +10dBm maximum output
-// power limit applies. The resulting maximum output power (ERP) is ~~ +10dBm
-// with this configuration
-// Note: The PA output power gain has a few dB of output power hysteresis, and
-// this configuration can result in an illegal output power level. See the
-// nRF21540 Product Specification v1.0, chapter 8.1.4 CONFREG3, which states
-// that the default TX gain of +10dB has an error margin of +/- 1.5dB.
-
-// For RADIO_TX_POWER_XXX
-#include "mcu/nrf/common/vendor/mdk/nrf52840_bitfields.h"
-
-// +10 dBm power table for nrf52840, with 7 power levels, PA gain +10dB
-// With +10dB gain power consumption increases by 38mA
-const app_lib_radio_cfg_power_t m_power_table =
-{
- .rx_current = 46 + 29, // 4.6 mA RX current (+2.9 mA LNA current)
- .rx_gain_dbm = 13, // 13 dBm RX gain (from LNA)
- .power_count = 7, // 7 power levels
- .powers =
- {
- {RADIO_TXPOWER_TXPOWER_Neg40dBm, -30, 1, 23 + 380},
- {RADIO_TXPOWER_TXPOWER_Neg20dBm, -10, 1, 27 + 380},
- {RADIO_TXPOWER_TXPOWER_Neg16dBm, -6, 1, 28 + 380},
- {RADIO_TXPOWER_TXPOWER_Neg12dBm, -2, 1, 30 + 380},
- {RADIO_TXPOWER_TXPOWER_Neg8dBm, 2, 1, 33 + 380},
- {RADIO_TXPOWER_TXPOWER_Neg4dBm, 6, 1, 37 + 380},
- {RADIO_TXPOWER_TXPOWER_0dBm, 10, 1, 48 + 380},
- },
-};
-
-// Maximum power level
-#define POWER_LEVEL_MAX (m_power_table.power_count - 1)
-
-//-----------------------------------------------------------------------------
-
-/** Latest asked TX power level from FW. Used as index to power tables.
- * NOTE: This example does not utilize this value for anything, as the FEM PA
- * gain does not change */
-static uint8_t m_tx_power_index;
-
-/** Current FEM state */
-static volatile uint32_t m_fem_state;
-
-// Code:
-
-/**
- * \brief Callback function to control FEM state.
- * This should be fast and not use other services.
- * In some cases may be called from interrupt context.
- * Customers are responsible for actual control strategy.
- * Can be empty function if nothing to do.
- * \param femcmd
- * Command to set FEM state.
- * For future compatibility, do nothing if command is not recognized.
- */
-static void fem_cmd_cb(app_lib_radio_cfg_femcmd_e femcmd)
-{
- if (m_fem_state == (uint32_t)femcmd)
- {
- // State does not change
- return;
- }
-
- // Record new state
- m_fem_state = femcmd;
-
- switch (femcmd)
- {
- case APP_LIB_RADIO_CFG_FEM_STANDBY:
- // Keep the FEM in RX mode, when in "standby", see why this is done
- // below in case APP_LIB_RADIO_CFG_FEM_STANDBY:
- case APP_LIB_RADIO_CFG_FEM_RX_ON:
- // According to datasheet, CSN must be driven low in RX
- nrf_gpio_pin_clear(BOARD_FEM_CS_PIN);
- // go to rx state with LNA on:
- nrf_gpio_pin_clear(BOARD_FEM_TXEN_PIN);
- nrf_gpio_pin_set(BOARD_FEM_RXEN_PIN);
- break;
- case APP_LIB_RADIO_CFG_FEM_TX_ON:
- nrf_gpio_pin_clear(BOARD_FEM_CS_PIN);
- nrf_gpio_pin_clear(BOARD_FEM_RXEN_PIN);
- nrf_gpio_pin_set(BOARD_FEM_TXEN_PIN);
- break;
-#if 0 // Entering standby / PG mode messes up the TX/RX timings, might be a chip
- // or chip revision related issue
- case APP_LIB_RADIO_CFG_FEM_STANDBY:
- nrf_gpio_pin_set(BOARD_FEM_CS_PIN);
- // Remain in program state
- nrf_gpio_pin_clear(BOARD_FEM_RXEN_PIN);
- nrf_gpio_pin_clear(BOARD_FEM_TXEN_PIN);
- nrf_gpio_pin_set(BOARD_FEM_PDN_PIN);
- break;
-#endif
- case APP_LIB_RADIO_CFG_FEM_PWR_ON:
- nrf_gpio_pin_set(BOARD_FEM_CS_PIN);
- // Remain in program state
- nrf_gpio_pin_clear(BOARD_FEM_RXEN_PIN);
- nrf_gpio_pin_clear(BOARD_FEM_TXEN_PIN);
- nrf_gpio_pin_set(BOARD_FEM_PDN_PIN);
- break;
- case APP_LIB_RADIO_CFG_FEM_PWR_OFF:
- nrf_gpio_pin_set(BOARD_FEM_CS_PIN);
- nrf_gpio_pin_clear(BOARD_FEM_RXEN_PIN);
- nrf_gpio_pin_clear(BOARD_FEM_TXEN_PIN);
- nrf_gpio_pin_clear(BOARD_FEM_PDN_PIN);
- break;
- default:
- // Do nothing if command not identified:
- break;
- }
-}
-
-/**
- * \brief Callback function to set radio TX power.
- * This is called by firmware to tell the next TX power level.
- * Never called when the TX is already active.
- * Must not activate TX state.
- * Sets power level of FEM PA (immediately or when TX actually starts).
- * Can be empty function if nothing to do (no PA or fixed PA).
- * \note Firmware sets the radio power level. Rationale: In some systems it
- * would be impossible to access the internal radio from here.
- *
- * \param Power level 0...POWER_LEVEL_MAX.
- * Used as index for power configuration structures.
- */
-static void fem_set_power_cb(uint8_t power)
-{
- if (power > POWER_LEVEL_MAX)
- {
- power = POWER_LEVEL_MAX;
- }
-
- // Store for later use (see APP_LIB_RADIO_CFG_FEM_TX_ON).
- m_tx_power_index = power;
-}
-
-/**
- * \brief Public interface. Initialize and register FEM driver.
- * Call exactly once, from App_init().
- */
-void Fem_init(void)
-{
- m_tx_power_index = 0; // (index 0 is the lowest possible power value)
- m_fem_state = APP_LIB_RADIO_CFG_FEM_PWR_OFF;
-
- // Initialize FEM control pins (nrf21540).
- // Safe initial state:
- nrf_gpio_cfg_output(BOARD_FEM_PDN_PIN);
- nrf_gpio_pin_clear(BOARD_FEM_PDN_PIN); // FEM disabled
-
- nrf_gpio_cfg_output(BOARD_FEM_RXEN_PIN);
- nrf_gpio_pin_clear(BOARD_FEM_RXEN_PIN); // RX off
-
- nrf_gpio_cfg_output(BOARD_FEM_TXEN_PIN);
- nrf_gpio_pin_clear(BOARD_FEM_TXEN_PIN); // TX off
-
- nrf_gpio_cfg_output(BOARD_FEM_ANTSEL_PIN);
- nrf_gpio_pin_clear(BOARD_FEM_ANTSEL_PIN); // Antenna 1
-
- // DO _NOT_ touch MODE pin afterwards, otherwise the FEM will load a
- // "default" value from POUTX_UICR or POUTX_UICR
- nrf_gpio_cfg_output(BOARD_FEM_MODE_PIN); // Load default value once
- nrf_gpio_pin_set(BOARD_FEM_MODE_PIN); // 0: +20dB 1: +10dB
-
- // Put all pins of spi to low values
- nrf_gpio_cfg_output(BOARD_FEM_SPI_MOSI_PIN);
- nrf_gpio_pin_clear(BOARD_FEM_SPI_MOSI_PIN);
- nrf_gpio_cfg_output(BOARD_FEM_SPI_CLK_PIN);
- nrf_gpio_pin_clear(BOARD_FEM_SPI_CLK_PIN);
- nrf_gpio_cfg_output(BOARD_FEM_SPI_MISO_PIN);
- nrf_gpio_pin_clear(BOARD_FEM_SPI_MISO_PIN);
- // Slave select has to be de-asserted
- nrf_gpio_cfg_output(BOARD_FEM_CS_PIN);
- nrf_gpio_pin_set(BOARD_FEM_CS_PIN);
-
- // Prepare the FEM configuration to the femcfg structure.
- // Set callbacks:
- app_lib_radio_cfg_fem_t femcfg =
- {
- .setPower = fem_set_power_cb,
- .femCmd = fem_cmd_cb,
- // Delays from nRF21540 PS1.0 Table 6
- .femTimings =
- {
- .pd_to_sby = 18, // 17.5
- .sby_to_tx = 11, // 10.5
- .sby_to_rx = 11, // 10.5
- .delay_values_set = true,
- },
- };
-
- app_res_e status = lib_radio_cfg->femSetup(&femcfg);
- if (status != APP_RES_OK)
- {
- // This will crash the SW but it is not possible to continue.
- while (1);
- }
-
- // Write radio configuration
- status = lib_radio_cfg->powerSetup(&m_power_table);
- if (status != APP_RES_OK)
- {
- // This will crash the SW but it is not possible to continue.
- while (1);
- }
-
- // Otherwise, we are done
-}
diff --git a/board/pca10112/makefile_board.mk b/board/pca10112/makefile_board.mk
deleted file mode 100644
index 8fb04b40..00000000
--- a/board/pca10112/makefile_board.mk
+++ /dev/null
@@ -1,4 +0,0 @@
-
-# Add board specific sources here, if any
-SRCS += board/$(target_board)/board_custom_init.c \
- board/$(target_board)/fem_driver_nrf21540.c
diff --git a/board/promistel_rpi_hat/board.h b/board/promistel_rpi_hat/board.h
deleted file mode 100644
index 05759724..00000000
--- a/board/promistel_rpi_hat/board.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* Copyright 2019 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-/**
- * @file
- *
- * Board definition for the
- * Promistel raspberry pi hat
- */
-#ifndef BOARD_PROMISTEL_RPI_HAT_BOARD_H_
-#define BOARD_PROMISTEL_RPI_HAT_BOARD_H_
-
-// Interrupt pin for dual mcu app, unread indication
-#define BOARD_UART_IRQ_PIN 23
-
-// Serial port pins
-#define BOARD_USART_TX_PIN 45 //P1.13
-#define BOARD_USART_RX_PIN 29
-#define BOARD_USART_CTS_PIN 7 /* For USE_USART_HW_FLOW_CONTROL */
-#define BOARD_USART_RTS_PIN 5 /* For USE_USART_HW_FLOW_CONTROL */
-
-// List of GPIO pins for the LEDs on the board: LED R, G, B
-#define BOARD_LED_PIN_LIST {15, 16, 24}
-
-// Active low polarity for LEDs
-#define BOARD_LED_ACTIVE_LOW true
-
-// List of GPIO pins for buttons on the board: User switch
-#define BOARD_BUTTON_PIN_LIST {14}
-
-// Active low polarity for buttons
-#define BOARD_BUTTON_ACTIVE_LOW true
-
-// Active internal pull-up for buttons
-#define BOARD_BUTTON_INTERNAL_PULL true
-
-// Define the SPI instance to use
-#define USE_SPI0
-
-// SPI Port pins
-#define BOARD_SPI_SCK_PIN 19
-#define BOARD_SPI_MOSI_PIN 20
-#define BOARD_SPI_MISO_PIN 21
-
-// SPI Chip Select pin
-#define BOARD_SPI_CS_PIN 17
-
-// The board supports DCDC (#define BOARD_SUPPORT_DCDC)
-// Since SDK v1.2 (bootloader > v7) this option has been move to
-// board//config.mk. Set board_hw_dcdc to yes to enable DCDC.
-#ifdef BOARD_SUPPORT_DCDC
-#error This option has been moved to board//config.mk
-#endif
-
-#endif /* BOARD_PROMISTEL_RPI_HAT_BOARD_H_ */
diff --git a/board/promistel_rpi_hat/config.mk b/board/promistel_rpi_hat/config.mk
deleted file mode 100644
index 55a31379..00000000
--- a/board/promistel_rpi_hat/config.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-# Mcu of the board
-MCU_FAMILY=nrf
-MCU=nrf52
-MCU_SUB=840
-
-# Hardware capabilities of the board
-## Is 32kHz crystal mounted on the board.
-board_hw_crystal_32k=yes
-## Is DCDC used on this board.
-board_hw_dcdc=yes
\ No newline at end of file
diff --git a/board/ruuvitag/board.h b/board/ruuvitag/board.h
deleted file mode 100644
index 51d9668c..00000000
--- a/board/ruuvitag/board.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* Copyright 2018 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-/**
- * @file
- *
- * Board definition for the
- * Ruuvitag device
- */
-#ifndef BOARD_RUUVITAG_H_
-#define BOARD_RUUVITAG_H_
-
-// Define the SPI instance to use
-#define USE_SPI0
-// SPI Port pins
-#define BOARD_SPI_SCK_PIN 29
-#define BOARD_SPI_MOSI_PIN 25
-#define BOARD_SPI_MISO_PIN 28
-
-// SPI Chip Select for various sensor
-#define BOARD_SPI_LIS2DH12_CS_PIN 8
-#define BOARD_SPI_BME280_CS_PIN 3
-
-// INT pins
-#define BOARD_LIS2DH12_INT1_PIN 2
-//#define BOARD_LIS2DH12_INT2_PIN 6
-
-
-
-// List of GPIO pins for the LEDs on the board: LED1, LED2
-#define BOARD_LED_PIN_LIST {17, 19}
-
-// Active low polarity for LEDs
-#define BOARD_LED_ACTIVE_LOW true
-
-// List of GPIO pins for buttons on the board: Button1
-#define BOARD_BUTTON_PIN_LIST {13}
-
-// Active low polarity for buttons
-#define BOARD_BUTTON_ACTIVE_LOW true
-
-// Active internal pull-up for buttons
-#define BOARD_BUTTON_INTERNAL_PULL true
-
-// The board supports DCDC (#define BOARD_SUPPORT_DCDC)
-// Since SDK v1.2 (bootloader > v7) this option has been move to
-// board//config.mk. Set board_hw_dcdc to yes to enable DCDC.
-#ifdef BOARD_SUPPORT_DCDC
-#error This option has been moved to board//config.mk
-#endif
-
-
-#endif /* BOARD_RUUVITAG_H_ */
diff --git a/board/ruuvitag/config.mk b/board/ruuvitag/config.mk
deleted file mode 100644
index a65764b1..00000000
--- a/board/ruuvitag/config.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-# Mcu of the board
-MCU_FAMILY=nrf
-MCU=nrf52
-MCU_SUB=832
-
-# Hardware capabilities of the board
-## Is 32kHz crystal mounted on the board.
-board_hw_crystal_32k=yes
-## Is DCDC used on this board.
-board_hw_dcdc=yes
\ No newline at end of file
diff --git a/board/silabs_brd2601b/board.h b/board/silabs_brd2601b/board.h
new file mode 100644
index 00000000..ef212bbf
--- /dev/null
+++ b/board/silabs_brd2601b/board.h
@@ -0,0 +1,101 @@
+/* Copyright 2023 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+
+/**
+ * @file
+ *
+ * Board definition for a board composed of a
+ *
+ *
+ */
+#ifndef BOARD_SILABS_BRD2610B_BOARD_H_
+#define BOARD_SILABS_BRD2610B_BOARD_H_
+
+// VCOM port only supports 115200 baudrate
+// This speed will be used independently of UART_BAUDRATE flag value
+#define BOARD_USART_FORCE_BAUDRATE 115200
+
+#define BOARD_SPI USART0
+#define BOARD_SPIROUTE GPIO->USARTROUTE[0]
+#define BOARD_SPI_MOSI_PORT GPIO_PORTC // SPI_COPI name in schema
+#define BOARD_SPI_MISO_PORT GPIO_PORTC // SPI_CIPO name in schema
+#define BOARD_SPI_SCKL_PORT GPIO_PORTC
+#define BOARD_SPI_MOSI_PIN 3
+#define BOARD_SPI_MISO_PIN 2
+#define BOARD_SPI_SCKL_PIN 1
+
+
+
+#define USE_I2C1
+#define BOARD_I2C_GPIO_PORT GPIOC
+#define BOARD_I2C_SDA_PIN 4
+#define BOARD_I2C_SCL_PIN 5
+#define BOARD_I2C_ROUTELOC_SDALOC I2C_ROUTELOC0_SDALOC_LOC17
+#define BOARD_I2C_ROUTELOC_SCLLOC I2C_ROUTELOC0_SCLLOC_LOC17
+
+
+
+// Serial port
+#define BOARD_USART_ID 0
+#define BOARD_USART_TX_PORT GPIO_PORTA
+#define BOARD_USART_TX_PIN 5 // UART_TX VCOM & Mini Simplicity
+#define BOARD_USART_RX_PORT GPIO_PORTA
+#define BOARD_USART_RX_PIN 6 // UART_RX VCOM & Mini Simplicity
+
+// List of GPIO pins
+#define BOARD_GPIO_PIN_LIST {{GPIO_PORTD, 2}, /* PD02 Red LED */ \
+ {GPIO_PORTA, 3}, /* PA04 Green LED */ \
+ {GPIO_PORTB, 0}, /* PB00 BLue LED */\
+ {GPIO_PORTB, 2}, /* PB01 Button0 */\
+ {GPIO_PORTB, 3}, /* PB01 Button1 */ \
+ {GPIO_PORTA, 7}, /* PA07. IMU CS, needs SENSOR_ENABLE to be set true to work */\
+ {GPIO_PORTA, 6}, /* PA06 USART wake-up */\
+ {GPIO_PORTC, 0}, /* PD04. SPI_FLASH_CS */ \
+ {GPIO_PORTC, 8}, /* PC08. I2C_MICS_ENABLE */ \
+ {GPIO_PORTD, 5}, /* PD05. I2C_WSE */ \
+ {GPIO_PORTC, 9}, /* PC09. SENSOR_ENABLE */ \
+ {GPIO_PORTA, 0}} /* PA00. ADC_VREF_ENABLE */ \
+
+
+
+
+// User friendly name for GPIOs (IDs mapped to the BOARD_GPIO_PIN_LIST table)
+#define BOARD_GPIO_ID_LED_RED 0 // mapped to pin PD02
+#define BOARD_GPIO_ID_LED_GREEN 1 // mapped to pin PA04
+#define BOARD_GPIO_ID_LED_BLUE 2 // mapped to pin PB00
+
+#define BOARD_GPIO_ID_BUTTON0 3 // mapped to pin PB02
+#define BOARD_GPIO_ID_BUTTON1 4 // mapped to pin PB03
+
+#define BOARD_SPI_CS_IMU 5 // mapped to pin PA07 NOTE! Needs SENSOR_ENABLE to be set also
+#define BOARD_GPIO_ID_USART_WAKEUP 6 // mapped to pin PA06
+#define BOARD_SPI_FLASH_CS 7 // mapped to pin PC00 32 MBit serial Flash
+
+#define BOARD_I2C_MICS_ENABLE 8 // mapped to pin PC08, both mics 1 = powered, 0 = not powered
+#define BOARD_I2C_WSE 9 // mapped to pin PD05, selects which mic is readed with i2c
+
+#define BOARD_SENSOR_ENABLE 10 // mapped to pin PC09, Enables next sensors to i2c bus:
+ // Temperature, Humidity, Hall effect, Ambient light, Barometric pressure.
+ // Signal enables 6-Axis Inertia sensor to SPI bus
+
+#define BOARD_ADC_VREF_ENABLE 11 // mapped to pin PA00, 1 = reference is enabled, 0 = reference is not enabled
+
+// List of LED IDs
+#define BOARD_LED_ID_LIST {BOARD_GPIO_ID_LED_RED, BOARD_GPIO_ID_LED_GREEN, BOARD_GPIO_ID_LED_BLUE}
+
+// Active high polarity for LEDs
+#define BOARD_LED_ACTIVE_LOW false
+
+// List of button IDs
+#define BOARD_BUTTON_ID_LIST {BOARD_GPIO_ID_BUTTON0, BOARD_GPIO_ID_BUTTON1}
+
+// Active button connects signal to ground
+#define BOARD_BUTTON_ACTIVE_LOW true
+
+// Board has external pull-up for buttons, internal pull-ups are not needed
+#define BOARD_BUTTON_INTERNAL_PULL false
+
+#endif /* BOARD_SILABS_BRD2610B_BOARD_H_ */
diff --git a/board/silabs_brd2601b/config.mk b/board/silabs_brd2601b/config.mk
new file mode 100644
index 00000000..48f20f93
--- /dev/null
+++ b/board/silabs_brd2601b/config.mk
@@ -0,0 +1,22 @@
+# Mcu of the board
+MCU_FAMILY=efr
+MCU=efr32
+MCU_SUB=xg24
+MCU_MEM_VAR=xxxxf1536
+MCU_RAM_VAR=256
+
+# Which radio to use
+radio=efr32xg24
+
+# Hardware capabilities of the board
+## Is 32kHz crystal mounted on the board.
+board_hw_crystal_32k=yes
+## Is DCDC used on this board.
+board_hw_dcdc=yes
+## HFXO crystal characteristics
+## https://github.com/SiliconLabs/gecko_sdk/blob/gsdk_4.2/hardware/board/config/brd2601a/sl_device_init_hfxo_config.h
+board_hw_hfxo_ctune=140
+## LFXO crystal characteristics
+## https://github.com/SiliconLabs/gecko_sdk/blob/gsdk_4.2/hardware/board/config/brd2601a/sl_device_init_lfxo_config.h
+board_hw_lfxo_ctune=63
+board_hw_lfxo_gain=1
diff --git a/board/silabs_brd2703a/board.h b/board/silabs_brd2703a/board.h
new file mode 100644
index 00000000..49721e7c
--- /dev/null
+++ b/board/silabs_brd2703a/board.h
@@ -0,0 +1,56 @@
+/* Copyright 2023 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+
+/**
+ * @file
+ *
+ * Board definition for
+ * xG24-EK2703A
+ */
+#ifndef BOARD_SILABS_BRD2703A_BOARD_H_
+#define BOARD_SILABS_BRD2703A_BOARD_H_
+
+// VCOM port only supports 115200 baudrate
+// This speed will be used independently of UART_BAUDRATE flag value
+#define BOARD_USART_FORCE_BAUDRATE 115200
+
+// Serial port
+#define BOARD_USART_ID 0
+#define BOARD_USART_TX_PORT GPIO_PORTA
+#define BOARD_USART_TX_PIN 5
+#define BOARD_USART_RX_PORT GPIO_PORTA
+#define BOARD_USART_RX_PIN 6
+
+// List of GPIO pins
+#define BOARD_GPIO_PIN_LIST {{GPIO_PORTA, 4}, /* PA04 */\
+ {GPIO_PORTA, 7}, /* PA07 */\
+ {GPIO_PORTB, 2}, /* PB02 */\
+ {GPIO_PORTB, 3}, /* PB03 */\
+ {GPIO_PORTA, 6}} /* PA06. required by the dual_mcu app. usart wakeup pin (= BOARD_USART_RX) */\
+
+// User friendly name for GPIOs (IDs mapped to the BOARD_GPIO_PIN_LIST table)
+#define BOARD_GPIO_ID_LED0 0 // mapped to pin PA04
+#define BOARD_GPIO_ID_LED1 1 // mapped to pin PA07
+#define BOARD_GPIO_ID_BUTTON0 2 // mapped to pin PB02
+#define BOARD_GPIO_ID_BUTTON1 3 // mapped to pin PB03
+#define BOARD_GPIO_ID_USART_WAKEUP 4 // mapped to pin PA06
+
+// List of LED IDs
+#define BOARD_LED_ID_LIST {BOARD_GPIO_ID_LED0, BOARD_GPIO_ID_LED1}
+
+// LED GPIO polarity
+#define BOARD_LED_ACTIVE_LOW false
+
+// List of button IDs
+#define BOARD_BUTTON_ID_LIST {BOARD_GPIO_ID_BUTTON0, BOARD_GPIO_ID_BUTTON1}
+
+// Button GPIO polarity
+#define BOARD_BUTTON_ACTIVE_LOW true
+
+// Button GPIO internal pull up/down
+#define BOARD_BUTTON_INTERNAL_PULL false
+
+#endif // BOARD_SILABS_BRD2703A_BOARD_H_
diff --git a/board/silabs_brd4184a/config.mk b/board/silabs_brd2703a/config.mk
similarity index 69%
rename from board/silabs_brd4184a/config.mk
rename to board/silabs_brd2703a/config.mk
index ed3f2fa1..f563acd2 100644
--- a/board/silabs_brd4184a/config.mk
+++ b/board/silabs_brd2703a/config.mk
@@ -1,19 +1,20 @@
# Mcu of the board
MCU_FAMILY=efr
MCU=efr32
-MCU_SUB=xg22
-MCU_MEM_VAR=xxxxf512
+MCU_SUB=xg24
+MCU_MEM_VAR=xxxxf1536
+MCU_RAM_VAR=256
# Which radio to use
-radio=efr32xg22
+radio=efr32xg24
# Hardware capabilities of the board
## Is 32kHz crystal mounted on the board.
board_hw_crystal_32k=yes
-## Is DCDC used on this board (must be yes for efr32xg22).
+## Is DCDC used on this board.
board_hw_dcdc=yes
## HFXO crystal characteristics
-board_hw_hfxo_ctune=120
+board_hw_hfxo_ctune=100
## LFXO crystal characteristics
board_hw_lfxo_ctune=37
board_hw_lfxo_gain=1
diff --git a/board/silabs_brd4180b/board.h b/board/silabs_brd4180b/board.h
deleted file mode 100644
index 2544f24c..00000000
--- a/board/silabs_brd4180b/board.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* Copyright 2020 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-/**
- * @file
- *
- * Board definition for a board composed of a
- * Silabs starter kit
- * and a brd4180b radio module
- */
-#ifndef BOARD_SILABS_BRD4180B_BOARD_H_
-#define BOARD_SILABS_BRD4180B_BOARD_H_
-
-// Waps usart defines
-#define BOARD_USART_ID 0
-
-#define BOARD_USART_GPIO_PORT GPIO_PORTA
-#define BOARD_USART_TX_PIN 5
-#define BOARD_USART_RX_PIN 6
-
-// Enadle vcom in silabs kit board
-#define BOARD_USART_VCOM_PORT GPIO_PORTD
-#define BOARD_USART_VCOM_PIN 4
-
-// List of GPIO ports and pins for the LEDs on the board: LED1, LED2
-//#define BOARD_LED_PIN_LIST {{GPIO_PORTB, 0}, {GPIO_PORTB, 1}} // brd4180a
-#define BOARD_LED_PIN_LIST {{GPIO_PORTD, 2}, {GPIO_PORTD, 3}} // brd4180b
-
-// Active high polarity for LEDs
-#define BOARD_LED_ACTIVE_LOW false
-
-// List of ext. ints, GPIO ports and pins for buttons on the board: BTN0
-//#define BOARD_BUTTON_PIN_LIST {{0, GPIO_PORTD, 2},{2, GPIO_PORTD, 3}} // brd4180a
-#define BOARD_BUTTON_PIN_LIST {{0, GPIO_PORTB, 0},{2, GPIO_PORTB, 1}} // brd4180b
-
-// Active low polarity for buttons
-#define BOARD_BUTTON_ACTIVE_LOW true
-
-// Board has external pull-up for buttons
-#define BOARD_BUTTON_INTERNAL_PULL false
-
-// Buttons use even external interrupts
-#define BOARD_BUTTON_USE_EVEN_INT true
-
-
-
-#endif /* BOARD_SILABS_BRD4180B_BOARD_H_ */
diff --git a/board/silabs_brd4180b/config.mk b/board/silabs_brd4180b/config.mk
deleted file mode 100644
index c4cea337..00000000
--- a/board/silabs_brd4180b/config.mk
+++ /dev/null
@@ -1,27 +0,0 @@
-# Mcu of the board
-MCU_FAMILY=efr
-MCU=efr32
-MCU_SUB=xg21
-MCU_MEM_VAR=xxxxf1024
-
-# Which radio to use
-radio=efr32xg21
-
-# Hardware capabilities of the board
-## Is 32kHz crystal mounted on the board.
-board_hw_crystal_32k=yes
-## Is DCDC used on this board. (must be no for efr32xg21).
-board_hw_dcdc=no
-## HFXO crystal characteristics
-board_hw_hfxo_ctune=129
-## LFXO crystal characteristics
-board_hw_lfxo_ctune=79
-board_hw_lfxo_gain=1
-
-# Uncomment, and set path to custom power table here, if set, the custom power
-# table will be set during application startup, and the stack will use that
-# instead of the default one.
-# For convenience, an example of a +20dBm power table is provided, uncomment the
-# line below to use that instead of the default +10dBm power table
-# NOTE! +20 dBm power level is usable only where US FCC regulation applies
-#RADIO_CUSTOM_POWER_TABLE=mcu/efr32/hal/radio/radio_power_table_efr32xg21_20dBm.h
diff --git a/board/silabs_brd4181b/board.h b/board/silabs_brd4181b/board.h
deleted file mode 100644
index 2babe5bc..00000000
--- a/board/silabs_brd4181b/board.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Copyright 2021 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-/**
- * @file
- *
- * Board definition for a board composed of a
- * Silabs starter kit
- * and a brd4181b radio module
- */
-#ifndef BOARD_SILABS_BRD4181B_BOARD_H_
-#define BOARD_SILABS_BRD4181B_BOARD_H_
-
-// Waps usart defines
-#define BOARD_USART_ID 0
-
-#define BOARD_USART_GPIO_PORT GPIO_PORTA
-#define BOARD_USART_TX_PIN 5
-#define BOARD_USART_RX_PIN 6
-
-// Enadle vcom in silabs kit board
-#define BOARD_USART_VCOM_PORT GPIO_PORTD
-#define BOARD_USART_VCOM_PIN 4
-
-// List of GPIO ports and pins for the LEDs on the board: LED1, LED2
-//#define BOARD_LED_PIN_LIST {{GPIO_PORTB, 0}, {GPIO_PORTB, 1}} // brd4181a
-#define BOARD_LED_PIN_LIST {{GPIO_PORTD, 2}, {GPIO_PORTD, 3}} // brd4181b
-
-// Active high polarity for LEDs
-#define BOARD_LED_ACTIVE_LOW false
-
-// List of ext. ints, GPIO ports and pins for buttons on the board: BTN0
-//#define BOARD_BUTTON_PIN_LIST {{0, GPIO_PORTD, 2},{2, GPIO_PORTD, 3}} // brd4181a
-#define BOARD_BUTTON_PIN_LIST {{0, GPIO_PORTB, 0},{2, GPIO_PORTB, 1}} // brd4181b
-
-// Active low polarity for buttons
-#define BOARD_BUTTON_ACTIVE_LOW true
-
-// Board has external pull-up for buttons
-#define BOARD_BUTTON_INTERNAL_PULL false
-
-// Buttons use even external interrupts
-#define BOARD_BUTTON_USE_EVEN_INT true
-
-#endif /* BOARD_SILABS_BRD4181B_BOARD_H_ */
diff --git a/board/silabs_brd4181b/config.mk b/board/silabs_brd4181b/config.mk
deleted file mode 100644
index d5c0899d..00000000
--- a/board/silabs_brd4181b/config.mk
+++ /dev/null
@@ -1,20 +0,0 @@
-# Mcu of the board
-MCU_FAMILY=efr
-MCU=efr32
-MCU_SUB=xg21
-MCU_MEM_VAR=xxxxf1024
-
-# Which radio to use
-radio=efr32xg21
-
-# Hardware capabilities of the board
-## Is 32kHz crystal mounted on the board.
-board_hw_crystal_32k=yes
-## Is DCDC used on this board. (must be no for efr32xg21).
-board_hw_dcdc=no
-
-## HFXO crystal characteristics
-board_hw_hfxo_ctune=133
-## LFXO crystal characteristics
-board_hw_lfxo_ctune=37
-board_hw_lfxo_gain=1
diff --git a/board/silabs_brd4184a/board.h b/board/silabs_brd4184a/board.h
deleted file mode 100644
index 2b32b32d..00000000
--- a/board/silabs_brd4184a/board.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* Copyright 2021 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-/**
- * @file
- *
- * Board definition for the
- * Silabs Thunderboard BG22
- */
-#ifndef BOARD_SILABSBRD4184A_BOARD_H_
-#define BOARD_SILABSBRD4184A_BOARD_H_
-
-#define BOARD_USART_ID 0
-#define BOARD_USART_GPIO_PORT GPIO_PORTA
-#define BOARD_USART_TX_PIN 5
-#define BOARD_USART_RX_PIN 6
-
-// VCOM port only supports 115200 baudrate
-// This speed will be used independently of UART_BAUDRATE flag value
-#define BOARD_USART_FORCE_BAUDRATE 115200
-
-// List of GPIO ports and pins for the LEDs on the board: yellow LED
-#define BOARD_LED_PIN_LIST {{GPIO_PORTB, 0}}
-
-// Active high polarity for LEDs
-#define BOARD_LED_ACTIVE_LOW false
-
-// List of ext. ints, GPIO ports and pins for buttons on the board: BTN0
-#define BOARD_BUTTON_PIN_LIST {{0, GPIO_PORTB, 1}}
-
-// Active low polarity for buttons
-#define BOARD_BUTTON_ACTIVE_LOW true
-
-// Board has external pull-up for buttons
-#define BOARD_BUTTON_INTERNAL_PULL false
-
-// Buttons use even external interrupts
-#define BOARD_BUTTON_USE_EVEN_INT true
-
-
-#endif /* BOARD_SILABSBRD4184A_BOARD_H_ */
diff --git a/board/silabs_brd4187c/board.h b/board/silabs_brd4187c/board.h
new file mode 100644
index 00000000..ec3b382c
--- /dev/null
+++ b/board/silabs_brd4187c/board.h
@@ -0,0 +1,41 @@
+/* Copyright 2023 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+
+/**
+ * @file
+ *
+ * Board definition for a board composed of a Wirepas Evaluation Kit mother board
+ * and a silabs brd4187c radio module schematic
+ */
+#ifndef BOARD_SILABS_BRD4187C_BOARD_H_
+#define BOARD_SILABS_BRD4187C_BOARD_H_
+
+// Serial port
+#define BOARD_USART_ID 0
+#define BOARD_USART_TX_PORT GPIO_PORTA
+#define BOARD_USART_TX_PIN 8
+#define BOARD_USART_RX_PORT GPIO_PORTA
+#define BOARD_USART_RX_PIN 9
+
+// List of GPIO pins
+#define BOARD_GPIO_PIN_LIST {{GPIO_PORTB, 2}, /* PB02 EZR_LED0 */ \
+ {GPIO_PORTB, 4}, /* PB04 EZR_LED1*/ \
+ {GPIO_PORTA, 9}, /* PA09. required by the dual_mcu app. usart wakeup pin (= BOARD_USART_RX) */ \
+ {GPIO_PORTB, 0}} /* PB00. usart vcom pin */
+
+// User friendly name for GPIOs (IDs mapped to the BOARD_GPIO_PIN_LIST table)
+#define BOARD_GPIO_ID_LED0 0 // mapped to pin PB02
+#define BOARD_GPIO_ID_LED1 1 // mapped to pin PB04
+#define BOARD_GPIO_ID_USART_WAKEUP 2 // mapped to pin PA09
+#define BOARD_GPIO_ID_VCOM_ENABLE 3 // mapped to pin PB00
+
+// List of LED IDs
+#define BOARD_LED_ID_LIST {BOARD_GPIO_ID_LED0, BOARD_GPIO_ID_LED1}
+
+// Active high polarity for LEDs
+#define BOARD_LED_ACTIVE_LOW false
+
+#endif /* BOARD_SILABS_BRD4187C_BOARD_H_ */
diff --git a/board/silabs_brd4187c/config.mk b/board/silabs_brd4187c/config.mk
new file mode 100644
index 00000000..5ba6dd79
--- /dev/null
+++ b/board/silabs_brd4187c/config.mk
@@ -0,0 +1,38 @@
+# Mcu of the board
+MCU_FAMILY=efr
+MCU=efr32
+MCU_SUB=xg24
+MCU_MEM_VAR=xxxxf1536
+MCU_RAM_VAR=256
+# Run internal tests with the minumum memory configuration
+MCU_MEM_VAR=xxxxf1024
+MCU_RAM_VAR=128
+# Which radio to use
+radio=efr32xg24
+
+# Hardware capabilities of the board
+## Is 32kHz crystal mounted on the board.
+board_hw_crystal_32k=yes
+## Is DCDC used on this board. Radio is powered using dcdc
+board_hw_dcdc=yes
+## HFXO crystal characteristics
+## https://github.com/SiliconLabs/gecko_sdk/blob/gsdk_4.2/hardware/board/config/brd4186c_brd4001a/sl_device_init_hfxo_config.h
+board_hw_hfxo_ctune=87
+
+## LFXO crystal characteristics
+## https://github.com/SiliconLabs/gecko_sdk/blob/gsdk_4.2/hardware/board/config/brd4186c_brd4001a/sl_device_init_lfxo_config.h
+board_hw_lfxo_ctune=36
+
+board_hw_lfxo_gain=1
+
+# Set path to custom power table here, if set, the custom power
+# table will be set during application startup, and the stack will use that
+# instead of the default one.
+# For convenience, an example of a +20dBm power table is provided, uncomment the
+# line below or use radio_power_table=20 setting as make argument to use that
+# instead of the default +8dBm power table.
+# NOTE! +20 dBm power level is usable only where US FCC regulation applies
+#RADIO_CUSTOM_POWER_TABLE=mcu/efr/efr32/hal/radio/radio_power_table_efr32xg24_20dBm.h
+ifneq ("$(radio_power_table)", "")
+ RADIO_CUSTOM_POWER_TABLE=mcu/efr/efr32/hal/radio/radio_power_table_efr32xg24_$(radio_power_table)dbm.h
+endif
diff --git a/board/silabs_brd4210a/board.h b/board/silabs_brd4210a/board.h
deleted file mode 100644
index 62eee18e..00000000
--- a/board/silabs_brd4210a/board.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* Copyright 2020 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-/**
- * @file
- *
- * Board definition for a board composed of a Wirepas Evaluation Kit mother board
- * and a silabs brd4210a radio module
- */
-#ifndef BOARD_WIREPAS_BRD4210A_BOARD_H_
-#define BOARD_WIREPAS_BRD4210A_BOARD_H_
-
-// Waps usart defines
-#define BOARD_USART_ID 0
-
-#define BOARD_USART_GPIO_PORT GPIO_PORTA
-#define BOARD_USART_TX_PIN 8
-#define BOARD_USART_RX_PIN 9
-
-// Enadle vcom in silabs kit board
-#define BOARD_USART_VCOM_PORT GPIO_PORTB
-#define BOARD_USART_VCOM_PIN 0
-
-// List of GPIO ports and pins for the LEDs on the board:
-#define BOARD_LED_PIN_LIST {{GPIO_PORTB, 2}, {GPIO_PORTD, 3}}
-
-// Active high polarity for LEDs
-#define BOARD_LED_ACTIVE_LOW false
-
-// List of ext. ints, GPIO ports and pins for buttons on the board: PB0, PB1
-#define BOARD_BUTTON_PIN_LIST {{0, GPIO_PORTB, 1},{2, GPIO_PORTB, 3}}
-
-// Active low polarity for buttons
-#define BOARD_BUTTON_ACTIVE_LOW true
-
-// Board has external pull-up for buttons
-#define BOARD_BUTTON_INTERNAL_PULL false
-
-// Buttons use even external interrupts
-#define BOARD_BUTTON_USE_EVEN_INT true
-
-#endif /* BOARD_WIREPAS_BRD4210A_BOARD_H_ */
diff --git a/board/silabs_brd4210a/config.mk b/board/silabs_brd4210a/config.mk
deleted file mode 100644
index 1dc665dc..00000000
--- a/board/silabs_brd4210a/config.mk
+++ /dev/null
@@ -1,36 +0,0 @@
-# Mcu of the board
-MCU_FAMILY=efr
-MCU=efr32
-MCU_SUB=xg23
-MCU_MEM_VAR=xxxxf512
-
-# Which radio to use
-radio=efr32xg23
-# Radio Configuration aus915 or india865
-#radio_config=aus915
-radio_config=india865
-mac_profile=subg
-
-# Hardware capabilities of the board
-## Is 32kHz crystal mounted on the board.
-board_hw_crystal_32k=no
-## Is DCDC used on this board.
-board_hw_dcdc=yes
-## HFXO crystal characteristics
-board_hw_hfxo_ctune=106
-## LFXO crystal characteristics
-board_hw_lfxo_ctune=63
-board_hw_lfxo_gain=2
-
-# Custom power table
-# if set, the custom power table will be set during application startup,
-# and the stack will use that instead of the default one.
-# For convenience, +13dBm, +16dBm and +20dBm power tables are provided as examples.
-# - mcu/efr/efr32/hal/radio/radio_power_table_efr32xg23_13dbm.h
-# - mcu/efr/efr32/hal/radio/radio_power_table_efr32xg23_16dbm.h
-# - mcu/efr/efr32/hal/radio/radio_power_table_efr32xg23_20dbm.h
-# If predefined custom power table shall be used,
-# provide radio_power_table=13/16/20 as build parameter.
-ifneq ("$(radio_power_table)", "")
- RADIO_CUSTOM_POWER_TABLE=mcu/efr/efr32/hal/radio/radio_power_table_efr32xg23_$(radio_power_table)dbm.h
-endif
diff --git a/board/silabs_brd4253a/board.h b/board/silabs_brd4253a/board.h
deleted file mode 100644
index e6f050be..00000000
--- a/board/silabs_brd4253a/board.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/* Copyright 2018 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-/**
- * @file
- *
- * Board definition for a board composed of a
- * Silabs starter kit
- * and a brd4253a radio module
- */
-#ifndef BOARD_SILABSEFR32KIT_BOARD_H_
-#define BOARD_SILABSEFR32KIT_BOARD_H_
-
-// NOTE! The VCOM on the kit board supports ONLY the standart baud rates
-// e.g. 125000 is not working.
-
-// Waps usart defines
-#define BOARD_USART_ID 0
-
-#define BOARD_USART_GPIO_PORT GPIOA
-#define BOARD_USART_TX_PIN 0
-#define BOARD_USART_RX_PIN 1
-// ROUTELOC are dependent on GPIO defined above and mapping
-// can be founded chip datasheet from Silabs
-#define BOARD_USART_ROUTELOC_RXLOC USART_ROUTELOC0_RXLOC_LOC0
-#define BOARD_USART_ROUTELOC_TXLOC USART_ROUTELOC0_TXLOC_LOC0
-
-// Interrupt pin for dual mcu app, unread indication
-#define BOARD_UART_INT_PIN 8
-#define BOARD_UART_INT_PORT GPIOD
-
-// Enadle vcom in silabs kit board
-// NOTE! To enable virtual com port (VCOM): When the target device drives the
-// VCOM_ENABLE (PA5) signal high, a communication line to the Board Controller
-// is enabled.
-#define BOARD_USART_VCOM_PORT GPIOA
-#define BOARD_USART_VCOM_PIN 5
-
-// For further information about Silicon Labs Kit board pin configuration see:
-// UG265: EFR32FG12 2400/868 MHz 10 dBm Wireless Starter Kit User's Guide
-
-// List of GPIO ports and pins for the LEDs on the board: LED0, LED1
-#define BOARD_LED_PIN_LIST {{GPIOF, 4}, {GPIOF, 5}}
-
-// Active high polarity for LEDs
-#define BOARD_LED_ACTIVE_LOW false
-
-// List of ext. ints, GPIO ports and pins for buttons on the board: PB0, PB1
-#define BOARD_BUTTON_PIN_LIST {{4, GPIOF, 6}, {6, GPIOF, 7}}
-
-// Active low polarity for buttons
-#define BOARD_BUTTON_ACTIVE_LOW true
-
-// Board has external pull-up for buttons
-#define BOARD_BUTTON_INTERNAL_PULL false
-
-// Buttons use even external interrupts
-#define BOARD_BUTTON_USE_EVEN_INT true
-
-
-#endif /* BOARD_SILABSEFR32KIT_BOARD_H_ */
diff --git a/board/silabs_brd4253a/config.mk b/board/silabs_brd4253a/config.mk
deleted file mode 100644
index 20b02cf9..00000000
--- a/board/silabs_brd4253a/config.mk
+++ /dev/null
@@ -1,24 +0,0 @@
-# Mcu of the board
-MCU_FAMILY=efr
-MCU=efr32
-MCU_SUB=xg12
-MCU_MEM_VAR=pxxxf1024
-
-# Hardware capabilities of the board
-## Is 32kHz crystal mounted on the board.
-board_hw_crystal_32k=yes
-## Is DCDC used on this board.
-board_hw_dcdc=yes
-## HFXO crystal characteristics
-board_hw_hfxo_ctune=322
-## LFXO crystal characteristics
-board_hw_lfxo_ctune=68
-board_hw_lfxo_gain=2
-
-# Uncomment, and set path to custom power table here, if set, the custom power
-# table will be set during application startup, and the stack will use that
-# instead of the default
-# For convenience, an example of a +19dBm power table is provided, uncomment the
-# line below to use that instead of the default +10dBm power table
-# NOTE! +19 dBm power level is usable only where US FCC regulation applies
-#RADIO_CUSTOM_POWER_TABLE=mcu/efr/efr32/hal/radio/radio_power_table_efr32xg12_19dBm.h
diff --git a/board/silabs_brd4254a/board.h b/board/silabs_brd4254a/board.h
deleted file mode 100644
index 5e888ed8..00000000
--- a/board/silabs_brd4254a/board.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/* Copyright 2018 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-/**
- * @file
- *
- * Board definition for a board composed of a
- * Silabs starter kit
- * and a brd4254a radio module
- */
-#ifndef BOARD_SILABSEFR32KIT_BOARD_H_
-#define BOARD_SILABSEFR32KIT_BOARD_H_
-
-// NOTE! The VCOM on the kit board supports ONLY the standart baud rates
-// e.g. 125000 is not working.
-
-// Waps usart defines
-#define BOARD_USART_ID 0
-
-#define BOARD_USART_GPIO_PORT GPIOA
-#define BOARD_USART_TX_PIN 0
-#define BOARD_USART_RX_PIN 1
-// ROUTELOC are dependent on GPIO defined above and mapping
-// can be founded chip datasheet from Silabs
-#define BOARD_USART_ROUTELOC_RXLOC USART_ROUTELOC0_RXLOC_LOC0
-#define BOARD_USART_ROUTELOC_TXLOC USART_ROUTELOC0_TXLOC_LOC0
-
-// Interrupt pin for dual mcu app, unread indication
-#define BOARD_UART_INT_PIN 8
-#define BOARD_UART_INT_PORT GPIOD
-
-// Enadle vcom in silabs kit board
-// NOTE! To enable virtual com port (VCOM): When the target device drives the
-// VCOM_ENABLE (PA5) signal high, a communication line to the Board Controller
-// is enabled.
-#define BOARD_USART_VCOM_PORT GPIOA
-#define BOARD_USART_VCOM_PIN 5
-
-// For further information about Silicon Labs Kit board pin configuration see:
-// UG265: EFR32FG12 2400/868 MHz 10 dBm Wireless Starter Kit User's Guide
-
-// List of GPIO ports and pins for the LEDs on the board: LED0, LED1
-#define BOARD_LED_PIN_LIST {{GPIOF, 4}, {GPIOF, 5}}
-
-// Active high polarity for LEDs
-#define BOARD_LED_ACTIVE_LOW false
-
-// List of ext. ints, GPIO ports and pins for buttons on the board: PB0, PB1
-#define BOARD_BUTTON_PIN_LIST {{4, GPIOF, 6}, {6, GPIOF, 7}}
-
-// Active low polarity for buttons
-#define BOARD_BUTTON_ACTIVE_LOW true
-
-// Board has external pull-up for buttons
-#define BOARD_BUTTON_INTERNAL_PULL false
-
-// Buttons use even external interrupts
-#define BOARD_BUTTON_USE_EVEN_INT true
-
-
-#endif /* BOARD_SILABSEFR32KIT_BOARD_H_ */
diff --git a/board/silabs_brd4254a/config.mk b/board/silabs_brd4254a/config.mk
deleted file mode 100644
index f35ae701..00000000
--- a/board/silabs_brd4254a/config.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-# Mcu of the board
-MCU_FAMILY=efr
-MCU=efr32
-MCU_SUB=xg12
-MCU_MEM_VAR=pxxxf1024
-
-# Hardware capabilities of the board
-## Is 32kHz crystal mounted on the board.
-board_hw_crystal_32k=yes
-## Is DCDC used on this board.
-board_hw_dcdc=yes
-## HFXO crystal characteristics
-board_hw_hfxo_ctune=322
-## LFXO crystal characteristics
-board_hw_lfxo_ctune=68
-board_hw_lfxo_gain=2
diff --git a/board/silabs_brd4312a/board.h b/board/silabs_brd4312a/board.h
deleted file mode 100644
index 92ae14fb..00000000
--- a/board/silabs_brd4312a/board.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* Copyright 2021 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-/**
- * @file
- *
- * Board definition for a board composed of a
- * Silabs starter kit
- * and a brd4312a radio module
- */
-#ifndef BOARD_SILABS_BRD4312A_BOARD_H_
-#define BOARD_SILABS_BRD4312A_BOARD_H_
-
-// Waps usart defines
-#define BOARD_USART_ID 0
-
-#define BOARD_USART_GPIO_PORT GPIO_PORTA
-#define BOARD_USART_TX_PIN 5
-#define BOARD_USART_RX_PIN 6
-
-// Enadle vcom in silabs kit board
-#define BOARD_USART_VCOM_PORT GPIO_PORTB
-#define BOARD_USART_VCOM_PIN 4
-
-// List of GPIO ports and pins for the LEDs on the board:
-#define BOARD_LED_PIN_LIST {{GPIO_PORTB, 0}} // Only LED0
-//If both LEDs are defined, buttons cannot be configured
-//#define BOARD_LED_PIN_LIST {{GPIO_PORTB, 0},{GPIO_PORTB, 1}} // Both LED0 and LED1
-
-// Active high polarity for LEDs
-#define BOARD_LED_ACTIVE_LOW true
-
-// List of ext. ints, GPIO ports and pins for buttons on the board:
-#define BOARD_BUTTON_PIN_LIST {{0, GPIO_PORTB, 1}} // Only button1
-//If both buttons are defined, LEDs cannot be configured
-//#define BOARD_BUTTON_PIN_LIST {{0, GPIO_PORTB, 0},{2, GPIO_PORTB, 1}} // Both button0 and button1
-
-// Active low polarity for buttons
-#define BOARD_BUTTON_ACTIVE_LOW true
-
-// Board has external pull-up for buttons
-#define BOARD_BUTTON_INTERNAL_PULL false
-
-// Buttons use even external interrupts
-#define BOARD_BUTTON_USE_EVEN_INT true
-
-#endif /* BOARD_SILABS_BRD4312A_BOARD_H_ */
diff --git a/board/silabs_brd4312a/config.mk b/board/silabs_brd4312a/config.mk
deleted file mode 100644
index e93e494a..00000000
--- a/board/silabs_brd4312a/config.mk
+++ /dev/null
@@ -1,19 +0,0 @@
-# Mcu of the board
-MCU_FAMILY=efr
-MCU=efr32
-MCU_SUB=xg22
-MCU_MEM_VAR=xxxxf512
-
-# Radio of the module on the board
-radio=bgm220sc22hna
-
-# Hardware capabilities of the board
-## Is 32kHz crystal mounted on the board.
-board_hw_crystal_32k=yes
-## Is DCDC used on this board (must be yes for efr32gx22).
-board_hw_dcdc=yes
-## HFXO crystal characteristics
-board_hw_hfxo_ctune=120
-## LFXO crystal characteristics
-board_hw_lfxo_ctune=37
-board_hw_lfxo_gain=1
diff --git a/board/tbsense2/board.h b/board/tbsense2/board.h
deleted file mode 100644
index 4b49ff0b..00000000
--- a/board/tbsense2/board.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* Copyright 2018 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-/**
- * @file
- *
- * Board definition for the
- * Silabs Thunderboard Sense 2
- */
-#ifndef BOARD_TBSENSE2_BOARD_H_
-#define BOARD_TBSENSE2_BOARD_H_
-
-// Waps usart defines
-#if defined USE_FTDI
-#define BOARD_USART_ID 1
-#define BOARD_USART_GPIO_PORT GPIOF
-#define BOARD_USART_TX_PIN 3
-#define BOARD_USART_RX_PIN 4
-// ROUTELOC are dependent on GPIO defined above and mapping
-// can be founded chip datasheet from Silabs
-#define BOARD_USART_ROUTELOC_RXLOC USART_ROUTELOC0_RXLOC_LOC27
-#define BOARD_USART_ROUTELOC_TXLOC USART_ROUTELOC0_TXLOC_LOC27
-
-#else
-#define BOARD_USART_ID 0
-#define BOARD_USART_GPIO_PORT GPIOA
-#define BOARD_USART_TX_PIN 0
-#define BOARD_USART_RX_PIN 1
-
-// VCOM port only supports 115200 baudrate
-// This speed will be used independently of UART_BAUDRATE flag value
-#define BOARD_USART_FORCE_BAUDRATE 115200
-
-// ROUTELOC are dependent on GPIO defined above and mapping
-// can be founded chip datasheet from Silabs
-#define BOARD_USART_ROUTELOC_RXLOC USART_ROUTELOC0_RXLOC_LOC0
-#define BOARD_USART_ROUTELOC_TXLOC USART_ROUTELOC0_TXLOC_LOC0
-#endif
-
-// Interrupt pin for dual mcu app, unread indication
-#define BOARD_UART_INT_PIN 6
-#define BOARD_UART_INT_PORT GPIOF
-
-// I2C configuration: SDA on PC4, SCL on PC5 (ENV_I2C on Thunderboard Sense 2)
-#define USE_I2C1
-#define BOARD_I2C_GPIO_PORT GPIOC
-#define BOARD_I2C_SDA_PIN 4
-#define BOARD_I2C_SCL_PIN 5
-#define BOARD_I2C_ROUTELOC_SDALOC I2C_ROUTELOC0_SDALOC_LOC17
-#define BOARD_I2C_ROUTELOC_SCLLOC I2C_ROUTELOC0_SCLLOC_LOC17
-
-// List of GPIO ports and pins for the LEDs on the board: red LED, green LED
-#define BOARD_LED_PIN_LIST {{GPIOD, 8}, {GPIOD, 9}}
-
-// Active high polarity for LEDs
-#define BOARD_LED_ACTIVE_LOW false
-
-// List of ext. ints, GPIO ports and pins for buttons on the board: BTN0, BTN1
-#define BOARD_BUTTON_PIN_LIST {{12, GPIOD, 14}, {14, GPIOD, 15}}
-
-// Active low polarity for buttons
-#define BOARD_BUTTON_ACTIVE_LOW true
-
-// Board has external pull-up for buttons
-#define BOARD_BUTTON_INTERNAL_PULL false
-
-// Buttons use even external interrupts
-#define BOARD_BUTTON_USE_EVEN_INT true
-
-
-#endif /* BOARD_TBSENSE2_BOARD_H_ */
diff --git a/board/tbsense2/config.mk b/board/tbsense2/config.mk
deleted file mode 100644
index f35ae701..00000000
--- a/board/tbsense2/config.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-# Mcu of the board
-MCU_FAMILY=efr
-MCU=efr32
-MCU_SUB=xg12
-MCU_MEM_VAR=pxxxf1024
-
-# Hardware capabilities of the board
-## Is 32kHz crystal mounted on the board.
-board_hw_crystal_32k=yes
-## Is DCDC used on this board.
-board_hw_dcdc=yes
-## HFXO crystal characteristics
-board_hw_hfxo_ctune=322
-## LFXO crystal characteristics
-board_hw_lfxo_ctune=68
-board_hw_lfxo_gain=2
diff --git a/board/ublox_b204/board.h b/board/ublox_b204/board.h
deleted file mode 100644
index dd892e75..00000000
--- a/board/ublox_b204/board.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Copyright 2019 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-/**
- * @file
- *
- * Board definition for the
- * Ublox b204 dongle
- */
-#ifndef BOARD_UBLOX_B204_H_
-#define BOARD_UBLOX_B204_H_
-
-// Serial port pins
-#define BOARD_USART_TX_PIN 6
-#define BOARD_USART_RX_PIN 5
-#define BOARD_USART_CTS_PIN 7 /* For USE_USART_HW_FLOW_CONTROL */
-#define BOARD_USART_RTS_PIN 31 /* For USE_USART_HW_FLOW_CONTROL */
-
-/* List of GPIO pins for the LEDs on the B204 board:
-LED B204 / nrf52832 pin
-GREEN: GPIO_7 / P0.16
-RED: GPIO_1 / P0.08
-BLUE: GPIO_8 / P0.18
-*/
-#define BOARD_LED_PIN_LIST {16, 8, 18}
-
-// The board supports DCDC (#define BOARD_SUPPORT_DCDC)
-// Since SDK v1.2 (bootloader > v7) this option has been move to
-// board//config.mk. Set board_hw_dcdc to yes to enable DCDC.
-#ifdef BOARD_SUPPORT_DCDC
-#error This option has been moved to board//config.mk
-#endif
-
-
-#endif /* BOARD_UBLOX_B204_H_ */
diff --git a/board/ublox_b204/config.mk b/board/ublox_b204/config.mk
deleted file mode 100644
index a65764b1..00000000
--- a/board/ublox_b204/config.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-# Mcu of the board
-MCU_FAMILY=nrf
-MCU=nrf52
-MCU_SUB=832
-
-# Hardware capabilities of the board
-## Is 32kHz crystal mounted on the board.
-board_hw_crystal_32k=yes
-## Is DCDC used on this board.
-board_hw_dcdc=yes
\ No newline at end of file
diff --git a/board/wuerth_261101102/board.h b/board/wuerth_261101102/board.h
deleted file mode 100644
index 3ef2f300..00000000
--- a/board/wuerth_261101102/board.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* Copyright 2021 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-/**
- * @file
- *
- * Board definition for the Wuerth Electronic eiSos radio module 261101102xxxx
- */
-#ifndef BOARD_WUERTH_261101102XXXX_BOARD_H_
-#define BOARD_WUERTH_261101102XXXX_BOARD_H_
-
-// NRF_GPIO is mapped to NRF_P0 , for pins P0.00 ... P0.31
-// Use NRF_P1 for pins P1.00 ... P1.15
-// With nrf_gpio.h, use SW_pin (logical pins, port-aware)
-
-/**
-NRF_P SW_pin Module pad function
----------------------------------------
-P0.00 0 11 [XTAL 32k]
-P0.01 1 12 [XTAL 32k]
-P0.02 2 7 gpio, DATA_IND
-P0.03 3 17 gpio
-P0.07 7 B6 gpio
-P0.09 9 B1 gpio
-P0.10 10 B2 gpio
-P0.11 11 15 UART_RTS
-P0.12 12 16 UART_CTS
-P0.18 18 6 nRESET
-P0.19 19 9 gpio, LED1
-P0.21 21 B5 gpio
-P0.22 22 10 gpio, LED2
-P0.23 23 B3 gpio
-P1.00 32 B4 gpio
-P1.08 40 13 UART_TX
-P1.09 41 14 UART_RX
-*/
-
-// Interrupt pin for dual mcu app, unread indication
-#define BOARD_UART_IRQ_PIN 2
-
-// Serial port pins
-#define BOARD_USART_TX_PIN 40
-#define BOARD_USART_RX_PIN 41
-#define BOARD_USART_CTS_PIN 12 /* For USE_USART_HW_FLOW_CONTROL */
-#define BOARD_USART_RTS_PIN 11 /* For USE_USART_HW_FLOW_CONTROL */
-
-// I2C pins
-#define BOARD_I2C_SDA_PIN BOARD_USART_CTS_PIN
-#define BOARD_I2C_SCL_PIN BOARD_USART_RTS_PIN
-
-// List of GPIO pins for the LEDs on the board: LED 1 to LED 2
-#define BOARD_LED_PIN_LIST {19, 22}
-
-// Active low polarity for LEDs
-#define BOARD_LED_ACTIVE_LOW false
-
-// List of GPIO pins for buttons on the board:
-// #define BOARD_BUTTON_PIN_LIST {}
-
-// Active low polarity for buttons
-#define BOARD_BUTTON_ACTIVE_LOW true
-
-
-#endif /* BOARD_WUERTH_261101102XXXX_BOARD_H_ */
\ No newline at end of file
diff --git a/board/wuerth_261101102/config.mk b/board/wuerth_261101102/config.mk
deleted file mode 100644
index 8a243c10..00000000
--- a/board/wuerth_261101102/config.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-# Mcu of the board
-MCU_FAMILY=nrf
-MCU=nrf52
-MCU_SUB=840
-
-# Hardware capabilities of the board
-## Is 32kHz crystal mounted on the board.
-board_hw_crystal_32k=yes
-## Is DCDC used on this board.
-board_hw_dcdc=yes
-
-# Uncomment, and set path to custom power table here, if set, the custom power
-# table will be set during application startup, and the stack will use that
-# instead of the default
-# For convenience, an example of a +4dBm power table is provided, uncomment the
-# line below to use that instead of the default +8dBm power table
-#RADIO_CUSTOM_POWER_TABLE=mcu/nrf/nrf52/hal/radio/radio_power_table_nrf52840_4dBm.h
diff --git a/bootloader/bl_hardware.c b/bootloader/bl_hardware.c
index 3fee6a5c..6ca03f67 100644
--- a/bootloader/bl_hardware.c
+++ b/bootloader/bl_hardware.c
@@ -9,9 +9,8 @@
#if defined(EFR32_PLATFORM)
#include "em_cmu.h"
-#endif
-#if defined(EFR32FG12) || defined(EFR32MG12) || defined(EFR32FG13)
+#if (_SILICON_LABS_32B_SERIES == 1)
static CMU_HFXOInit_TypeDef m_hfxoInit =
{
false, /* Low-noise mode for EFR32 */
@@ -38,9 +37,8 @@ static CMU_LFXOInit_TypeDef m_lfxoInit =
_CMU_LFXOCTRL_TIMEOUT_DEFAULT, /* Default start-up delay, 32 K cycles */
cmuOscMode_Crystal, /* Crystal oscillator */
};
-#endif
-#if defined(EFR32MG21) || defined(EFR32MG22)
+#elif (_SILICON_LABS_32B_SERIES == 2)
static CMU_HFXOInit_TypeDef m_hfxoInit =
{
cmuHfxoCbLsbTimeout_416us,
@@ -61,6 +59,9 @@ static CMU_HFXOInit_TypeDef m_hfxoInit =
false, /* forceXi2GndAna */
false, /* DisOndemand */
false, /* ForceEn */
+#if defined(HFXO_CTRL_EM23ONDEMAND)
+ false, /* Enable deep sleep */
+#endif // defined(HFXO_CTRL_EM23ONDEMAND)
false /* Lock registers */
};
@@ -78,50 +79,24 @@ static CMU_LFXOInit_TypeDef m_lfxoInit =
false, /* ForceEn */
false /* Lock registers */
};
-#endif
+#else
+#error "Unsupported EFR32 series"
+#endif // (_SILICON_LABS_32B_SERIES == 1)
-#if defined(EFR32FG23)
-static CMU_HFXOInit_TypeDef m_hfxoInit =
+static const platform_efr32_t m_platform_efr32 =
{
- cmuHfxoCbLsbTimeout_416us,
- cmuHfxoSteadyStateTimeout_833us, /* First lock */
- cmuHfxoSteadyStateTimeout_83us, /* Subsequent locks */
- 0U, /* ctuneXoStartup */
- 0U, /* ctuneXiStartup */
- 32U, /* coreBiasStartup */
- 32U, /* imCoreBiasStartup */
- cmuHfxoCoreDegen_None,
- cmuHfxoCtuneFixCap_Both,
- BOARD_HW_HFXO_CTUNE, /* ctuneXoAna */
- BOARD_HW_HFXO_CTUNE, /* ctuneXiAna */
- 60U, /* coreBiasAna */
- false, /* enXiDcBiasAna */
- cmuHfxoOscMode_Crystal,
- false, /* forceXo2GndAna */
- false, /* forceXi2GndAna */
- false, /* DisOndemand */
- false, /* ForceEn */
- false, /* Enable deep sleep */
- false /* Lock registers */
+ .hfxoInit = &m_hfxoInit,
+ .lfxoInit = &m_lfxoInit
};
-static CMU_LFXOInit_TypeDef m_lfxoInit =
+static const hardware_capabilities_t m_hw =
{
- BOARD_HW_LFXO_GAIN, /* gain */
- BOARD_HW_LFXO_CTUNE, /* capTune */
- cmuLfxoStartupDelay_4KCycles, /* timeout */
- cmuLfxoOscMode_Crystal, /* mode */
- false, /* highAmplitudeEn */
- true, /* agcEn */
- false, /* failDetEM4WUEn */
- false, /* failDetEn */
- false, /* DisOndemand */
- false, /* ForceEn */
- false /* Lock registers */
+ .crystal_32k = BOARD_HW_CRYSTAL_32K,
+ .dcdc = BOARD_HW_DCDC,
+ .platform.efr32 = &m_platform_efr32
};
-#endif
-#if defined(NRF52_PLATFORM)
+#elif defined(NRF52_PLATFORM)
static const hardware_capabilities_t m_hw =
{
@@ -131,32 +106,32 @@ static const hardware_capabilities_t m_hw =
};
#elif defined(NRF91_PLATFORM)
-static const hardware_capabilities_t m_hw =
-{
- .crystal_32k = BOARD_HW_CRYSTAL_32K,
- .dcdc = BOARD_HW_DCDC,
- .platform.nrf91 = NULL
-};
-#elif defined(EFR32_PLATFORM)
+#include "board.h"
-static const platform_efr32_t m_platform_efr32 =
+#if defined(BOARD_AT_COMMANDS)
+static const char board_at_commands[] = BOARD_AT_COMMANDS;
+#endif // defined(BOARD_AT_COMMANDS)
+
+static const platform_nrf91_t m_platform_nrf91 =
{
- .hfxoInit = &m_hfxoInit,
- .lfxoInit = &m_lfxoInit
+#if defined(BOARD_AT_COMMANDS)
+ .at_commands = board_at_commands
+#else // defined(BOARD_AT_COMMANDS)
+ .at_commands = NULL
+#endif
};
static const hardware_capabilities_t m_hw =
{
.crystal_32k = BOARD_HW_CRYSTAL_32K,
.dcdc = BOARD_HW_DCDC,
- .platform.efr32 = &m_platform_efr32
+ .platform.nrf91 = &m_platform_nrf91
};
-
#endif // defined(*_PLATFORM)
const hardware_capabilities_t * Hardware_getCapabilities(void)
{
-#if defined(EFR32MG21) || defined(EFR32MG22) || defined(EFR32FG23)
+#if defined(EFR32_PLATFORM) && (_SILICON_LABS_32B_SERIES == 2)
// If DevInfo.ModuleInfo contains valid calibration value for HFXO CTUNE,
// use it.
if ((DEVINFO->MODULEINFO & _DEVINFO_MODULEINFO_HFXOCALVAL_MASK) == 0) {
diff --git a/bootloader/bl_hardware.h b/bootloader/bl_hardware.h
index 743ce5a3..331c70b0 100644
--- a/bootloader/bl_hardware.h
+++ b/bootloader/bl_hardware.h
@@ -9,6 +9,19 @@
#include
+#if defined(NRF91_PLATFORM)
+/** \brief Platform specific descriptions for nRF91. */
+typedef struct
+{
+ /** Pointer to platform specific modem initialization AT commands.
+ * AT commands are separated from each other with null character ('\0'),
+ * the end of the list is indicated with double null characters ("\0\0").
+ * (introduced in bootloader v9).
+ */
+ const char * at_commands;
+} platform_nrf91_t;
+#endif
+
#if defined(EFR32_PLATFORM)
#include "em_cmu.h"
diff --git a/bootloader_test/api/bl_interface.h b/bootloader_test/api/bl_interface.h
index e50c8469..0be3659a 100644
--- a/bootloader_test/api/bl_interface.h
+++ b/bootloader_test/api/bl_interface.h
@@ -17,6 +17,10 @@
#include
#include
+#if defined(EFR32_PLATFORM)
+#include "em_cmu.h"
+#endif
+
/** \brief Bootloader interface operations result */
typedef enum
{
@@ -30,9 +34,6 @@ typedef enum
BL_RES_INVALID_STATE = 7, /** Write ongoing or scratchpad not valid */
} bl_interface_res_e;
-/** \brief Maximum number of memory areas */
-#define BL_MEMORY_AREA_MAX_AREAS 8
-
/** \brief Value of an area that doesn't exists */
#define BL_MEMORY_AREA_UNDEFINED 0xFFFFFFFF
@@ -47,7 +48,8 @@ typedef enum
BL_MEM_AREA_TYPE_APPLICATION = 2, /** Application area */
BL_MEM_AREA_TYPE_PERSISTENT = 3, /** Persistent memory area */
BL_MEM_AREA_TYPE_SCRATCHPAD = 4, /** Dedicated scratchpad area */
- BL_MEM_AREA_TYPE_USER = 5 /** User defined area */
+ BL_MEM_AREA_TYPE_USER = 5, /** User defined area */
+ BL_MEM_AREA_TYPE_MODEMFW = 6 /** Modem firmware area */
} bl_memory_area_type_e;
/** \brief Flash memory info definition */
@@ -97,7 +99,7 @@ typedef struct
bl_flash_info_t flash;
/** true if area is located in external flash */
bool external_flash;
- /** true if bl_info_header_t is stored at the beginning of area */
+ /** true if bl_area_info_header_t is stored at the beginning of area */
bool has_header;
/** Type of memory area */
bl_memory_area_type_e type;
@@ -181,13 +183,13 @@ typedef enum
/** \brief Scratchpad info definition */
typedef struct
{
- /** Maximum possible length for the scratchpad (including header) */
+ /** Maximum possible length for the scratchpad (including tag and header) */
uint32_t area_length;
/** theorical erase time of the whole scratchpad area */
uint32_t erase_time;
- /** Number of bytes (including header) */
+ /** Number of bytes (including tag and header) */
uint32_t length;
- /** CRC16-CCITT, not including any header bytes */
+ /** CRC16-CCITT, not including any tag or header bytes */
uint16_t crc;
/** Sequence number of data in scratchpad: \ref bl_scratchpad_seq_t,
* we don't want dependancies with the bootloader here.
@@ -199,23 +201,79 @@ typedef struct
uint8_t flags;
/** Scratchpad type information for bootloader: \ref bl_header_type_e */
uint32_t type;
- /** Status code from bootloader: \ref bl_header_status_e */
+ /** Status code from bootloader: \ref bl_scratchpad_status_e */
uint32_t status;
/** true if scratchpad has is own dedicated area */
bool dedicated;
+ /** Offset of modem firmware data in the scratchpad memory area,
+ * valid only when status is BL_SCRATCHPAD_STATUS_MODEM_FW_PENDING */
+ uint32_t modem_fw_data;
+ /** Length of modem firmware file in bytes,
+ * valid only when status is BL_SCRATCHPAD_STATUS_MODEM_FW_PENDING */
+ uint32_t modem_fw_length;
} bl_scrat_info_t;
+#if defined(NRF91_PLATFORM)
+typedef struct
+{
+ /** Pointer to platform specific modem initialization AT commands.
+ * AT commands are separated from each other with null character ('\0'),
+ * the end of the list is indicated with double null characters ("\0\0").
+ * (introduced in bootloader v9).
+ */
+ const char * at_commands;
+} bl_platform_nrf91_t;
+#elif defined(EFR32_PLATFORM)
+/** \brief Platform specific descriptions for EFR32. */
+typedef struct
+{
+ /** Pointer to platform specific HFXO crystal description
+ * (introduced in bootloader v8).
+ */
+ const CMU_HFXOInit_TypeDef * hfxoInit;
+ /** Pointer to platform specific LFXO crystal description
+ * (introduced in bootloader v8).
+ */
+ const CMU_LFXOInit_TypeDef * lfxoInit;
+} bl_platform_efr32_t;
+#endif
+
+/** \brief Platform specific descriptions. */
+typedef union
+{
+#if defined(NRF52_PLATFORM)
+ /** Platform specific descriptions for nRF52.
+ * (dummy, introduced in bootloader v8).
+ */
+ const void * nrf52;
+#elif defined(NRF91_PLATFORM)
+ /** Platform specific descriptions for nRF91.
+ * (dummy, introduced in bootloader v8).
+ */
+ const bl_platform_nrf91_t * nrf91;
+#elif defined(EFR32_PLATFORM)
+ /** Platform specific descriptions for EFR32.
+ * (introduced in bootloader v8).
+ */
+ const bl_platform_efr32_t * efr32;
+#endif
+} bl_platform_t;
+
/** \brief Hardware features that can be installed on a board. */
typedef struct
{
/** True if 32kHz crystal is present; default:true
- * (introduced in booloader v7).
+ * (introduced in bootloader v7).
*/
bool crystal_32k;
/** True if DCDC converter is enabled; default:true
- * (introduced in bootloader v7).
+ * (introduced in bootloader v7).
*/
bool dcdc;
+ /** Platform specific descriptions
+ * (introduced in bootloader v8).
+ */
+ bl_platform_t platform;
} bl_hardware_capabilities_t;
/**
@@ -340,6 +398,16 @@ typedef bl_interface_res_e
(*bl_memory_area_getAreaHeader_f)(bl_memory_area_id_t id,
bl_memory_area_header_t * header);
+/**
+ * \brief Return the total number of areas supported by the bootloader.
+ * \return Number of areas supported by the bootloader
+ * \note Bootloaders prior to version 10 do not have this function. Instead,
+ * a macro called BL_MEMORY_AREA_MAX_AREAS is defined, which has a
+ * value of 8.
+ */
+typedef uint8_t
+ (*bl_memory_area_getMaxNumAreas_f)(void);
+
/**
* \brief Check if the scratchpad contains valid data
* \note Valid data isn't necessarily a firmware image
@@ -429,12 +497,21 @@ typedef bl_interface_res_e
typedef bl_interface_res_e
(*bl_scrat_setBootable_f)(void);
+typedef bl_interface_res_e (*bl_scrat_setStatus_f)(uint32_t status);
+
/**
* \brief Returns board hardware capabilities.
- * \return Return a bit field \ref bl_hardware_capabilities_e with
+ * \return Return a structure \ref bl_hardware_capabilities_t with
* hardware features installed on the board.
*/
-typedef const bl_hardware_capabilities_t * (*bl_hardware_getCapabilities_f)(void);
+typedef const bl_hardware_capabilities_t *
+ (*bl_hardware_getCapabilities_f)(void);
+
+/**
+ * \brief Add flow debugging point.
+ */
+typedef void (*bl_debug_flow_f)(dflow_tag_e tag);
+
typedef struct
{
@@ -446,6 +523,7 @@ typedef struct
bl_memory_area_getAreaList_f getAreaList;
bl_memory_area_getIdfromType_f getIdfromType;
bl_memory_area_getAreaHeader_f getAreaHeader;
+ bl_memory_area_getMaxNumAreas_f getMaxNumAreas;
} memory_area_services_t;
typedef struct
@@ -457,6 +535,7 @@ typedef struct
bl_scrat_write_f write;
bl_scrat_getInfo_f getInfo;
bl_scrat_setBootable_f setBootable;
+ bl_scrat_setStatus_f setStatus;
} scratchpad_services_t;
typedef struct
@@ -464,6 +543,11 @@ typedef struct
bl_hardware_getCapabilities_f getCapabilities;
} hardware_services_t;
+typedef struct
+{
+ bl_debug_flow_f debug_flow;
+} dflow_services_t;
+
/**
* \brief Global interface entry point with a version id
*/
@@ -473,6 +557,7 @@ typedef struct
const memory_area_services_t * memory_area_services_p;
const scratchpad_services_t * scratchpad_services_p;
const hardware_services_t * hardware_services_p;
+ const dflow_services_t * dflow_services_p;
} bl_interface_t;
#endif /* BL_INTERFACE_H_ */
diff --git a/bootloader_test/drivers/efr32/usart.c b/bootloader_test/drivers/efr32/usart.c
index c34ee694..7c7d7dd4 100644
--- a/bootloader_test/drivers/efr32/usart.c
+++ b/bootloader_test/drivers/efr32/usart.c
@@ -76,10 +76,10 @@ void Usart_init(uint32_t baudrate)
CMU->HFBUSCLKEN0 |= CMU_HFBUSCLKEN0_GPIO;
/* Configure Uart Tx pin */
- hal_gpio_set_mode(BOARD_USART_GPIO_PORT,
+ hal_gpio_set_mode(BOARD_USART_TX_PORT,
BOARD_USART_TX_PIN,
GPIO_MODE_OUT_PP);
- hal_gpio_clear(BOARD_USART_GPIO_PORT, BOARD_USART_TX_PIN);
+ hal_gpio_clear(BOARD_USART_TX_PORT, BOARD_USART_TX_PIN);
/* Must enable clock for configuration period */
CMU->HFPERCLKEN0 |= BOARD_USART_CMU_BIT;
diff --git a/bootloader_test/drivers/nrf52/usart.c b/bootloader_test/drivers/nrf52/usart.c
index 9225113f..b03bc3dd 100644
--- a/bootloader_test/drivers/nrf52/usart.c
+++ b/bootloader_test/drivers/nrf52/usart.c
@@ -12,7 +12,7 @@
void Usart_init(uint32_t baudrate)
{
- /* Configure Uart Tx pin */
+ /* GPIO init */
nrf_gpio_cfg(BOARD_USART_TX_PIN,
NRF_GPIO_PIN_DIR_OUTPUT,
NRF_GPIO_PIN_INPUT_CONNECT,
@@ -20,8 +20,6 @@ void Usart_init(uint32_t baudrate)
NRF_GPIO_PIN_S0S1,
NRF_GPIO_PIN_NOSENSE);
-
- /* GPIO init */
NRF_UART0->PSELTXD = BOARD_USART_TX_PIN;
NRF_UART0->PSELRXD = BOARD_USART_RX_PIN;
NRF_UART0->TASKS_STOPTX = 1;
diff --git a/bootloader_test/tests/test.h b/bootloader_test/tests/test.h
index 3821e68d..51251403 100644
--- a/bootloader_test/tests/test.h
+++ b/bootloader_test/tests/test.h
@@ -9,6 +9,14 @@
#ifndef _TEST_H_
#define _TEST_H_
+/* Number of maximum supported memory areas in tests
+ *
+ * The bootloader used to only support eight memory areas, but that was later
+ * increased to 16. Remember to increase this, if the bootloader supports more
+ * areas in the future.
+ */
+#define MAX_TESTED_MEMORY_AREAS 16
+
/* Macro to print test startup */
#define START_TEST(_name_, _desc_) Print_printf("\nTEST [%s]: %s\n", \
#_name_, #_desc_);
diff --git a/bootloader_test/tests/test_info.c b/bootloader_test/tests/test_info.c
index a9eaa9c8..1d4ee6a9 100644
--- a/bootloader_test/tests/test_info.c
+++ b/bootloader_test/tests/test_info.c
@@ -18,8 +18,8 @@ static const char * type_lut[] = {"BOOTLOADER ",
bool info_areas(const memory_area_services_t * mem_area_services)
{
bl_interface_res_e bl_res;
- bl_memory_area_id_t areas[BL_MEMORY_AREA_MAX_AREAS];
- uint8_t num_areas = BL_MEMORY_AREA_MAX_AREAS;
+ bl_memory_area_id_t areas[MAX_TESTED_MEMORY_AREAS];
+ uint8_t num_areas = MAX_TESTED_MEMORY_AREAS;
bool res = true;
START_TEST(INFO, List all areas);
@@ -125,8 +125,8 @@ bool info_flash(const memory_area_services_t * mem_area_services)
bool res = true;
bl_interface_res_e bl_res;
bl_memory_area_info_t info;
- bl_memory_area_id_t areas[BL_MEMORY_AREA_MAX_AREAS];
- uint8_t num_areas = BL_MEMORY_AREA_MAX_AREAS;
+ bl_memory_area_id_t areas[MAX_TESTED_MEMORY_AREAS];
+ uint8_t num_areas = MAX_TESTED_MEMORY_AREAS;
bl_memory_area_id_t id;
//Internal flash info
diff --git a/bootloader_test/tests/test_memory_areas.c b/bootloader_test/tests/test_memory_areas.c
index 0fc45454..d4ef172d 100644
--- a/bootloader_test/tests/test_memory_areas.c
+++ b/bootloader_test/tests/test_memory_areas.c
@@ -241,8 +241,8 @@ bool Tests_areas(bl_interface_t * interface)
{
// Test areas one by one
bl_interface_res_e bl_res;
- bl_memory_area_id_t areas[BL_MEMORY_AREA_MAX_AREAS];
- uint8_t num_areas = BL_MEMORY_AREA_MAX_AREAS;
+ bl_memory_area_id_t areas[MAX_TESTED_MEMORY_AREAS];
+ uint8_t num_areas = MAX_TESTED_MEMORY_AREAS;
bool res = true;
/* Store the pointer globally. */
diff --git a/bootloader_test/tests/test_timings.c b/bootloader_test/tests/test_timings.c
index 5a31c355..ea758404 100644
--- a/bootloader_test/tests/test_timings.c
+++ b/bootloader_test/tests/test_timings.c
@@ -130,8 +130,8 @@ bool Tests_timings(bl_interface_t * interface)
bool res = true;
bl_interface_res_e bl_res;
bl_memory_area_info_t info;
- bl_memory_area_id_t areas[BL_MEMORY_AREA_MAX_AREAS];
- uint8_t num_areas = BL_MEMORY_AREA_MAX_AREAS;
+ bl_memory_area_id_t areas[MAX_TESTED_MEMORY_AREAS];
+ uint8_t num_areas = MAX_TESTED_MEMORY_AREAS;
bl_memory_area_id_t id;
/* Store the pointer globally. */
diff --git a/config.mk b/config.mk
index 22d7103c..3ee6ddf4 100644
--- a/config.mk
+++ b/config.mk
@@ -10,8 +10,8 @@ target_board=
# Version of the SDK
sdk_major=1
-sdk_minor=4
-sdk_maintenance=1
+sdk_minor=5
+sdk_maintenance=0
sdk_development=0
diff --git a/doc_src_doxy/a1_sdk_environment.h b/doc_src_doxy/a1_sdk_environment.h
index 6fceb1bb..a8cdf1b1 100644
--- a/doc_src_doxy/a1_sdk_environment.h
+++ b/doc_src_doxy/a1_sdk_environment.h
@@ -92,14 +92,13 @@ used by the application.
All the internal interrupt of cortex M are handled by the stack
directly (NMI, HardFault,...)
-@subsection peripherals_shared_between_the_stack_and_the_application Peripherals Shared between the stack and the application
+@subsection peripherals_shared_between_the_stack_and_the_application Peripherals shared between the stack and the application
Some peripherals are used by the stack but can also be accessed by the
application.
-Random Number Generator RNG (nRF52) and True Random Number Generator TRNG (EFR32)
-are available for application to use within App_init function.
-After App_init returns, these peripherals are reserved for Wirepas Mesh stack and
+Random Number Generator RNG is available for application to use within App_init function.
+After App_init returns, this peripheral is reserved for Wirepas Mesh stack and
all initializations done in App_init may be overwritten.
Application may also take the control of RNG/TRNG by initializing the peripheral in
scheduled task after App_init has returned and after Wirepas Mesh stack has started.
@@ -116,14 +115,14 @@ Following chip variants (at 2.4 GHz only) are supported:
- EFR32FG12P232F1024G L125/M48 [2.4 GHz only, 1024/128, BGA125/QFN48]
- EFR32FG12P432F1024G L125/M48 [2.4 GHz only, 1024/256, BGA125/QFN48]
-- EFR32FG12P433F1024G L125/M48 [2.4 GHz & SubGHz, 1024/256, BGA125/QFN48]
+- EFR32FG12P433F1024G L125/M48 [2.4 GHz, 1024/256, BGA125/QFN48]
- EFR32MG12P232F1024G L125/M48 [2.4 GHz only, 1024/128, BGA125/QFN48]
- EFR32MG12P332F1024G L125/M48 [2.4 GHz only, 1024/128, BGA125/QFN48]
- EFR32MG12P432F1024G L125/M48 [2.4 GHz only, 1024/256, BGA125/QFN48]
-- EFR32MG12P433F1024G L125/M48 [2.4 GHz & SubGHz, 1024/256, BGA125/QFN48]
+- EFR32MG12P433F1024G L125/M48 [2.4 GHz, 1024/256, BGA125/QFN48]
- EFR32BG12P232F1024G L125/M48 [2.4 GHz only, 1024/128, BGA125/QFN48]
- EFR32BG12P432F1024G L125/M48 [2.4 GHz only, 1024/256, BGA125/QFN48]
-- EFR32BG12P433F1024G L125/M48 [2.4 GHz & SubGHz, 1024/256, BGA125/QFN48]
+- EFR32BG12P433F1024G L125/M48 [2.4 GHz, 1024/256, BGA125/QFN48]
- EFR32BG21A010F1024IM32
- EFR32BG21A010F512IM32
- EFR32BG21A010F768IM32
@@ -137,6 +136,9 @@ Following chip variants (at 2.4 GHz only) are supported:
- EFR32BG22C224F512IM40
- BGM220PC22HNA
- BGM220SC22HNA
+- EFR32ZG23B020F512IM48
+- EFR32MG24B310F1536IM48-B
+- EFR32MG24B210F1536IM48
This page contains following sections:
- @subpage flash_memory_efr32
@@ -166,6 +168,10 @@ application, according to processor type is following:
efr32xg21xxxxf768
50kB
efr32xg21xxxxf1024
256kB
efr32xg22xxxxf512
50kB
+
efr32xg23xxxxf512
40kB
+
efr32xg24xxxxf1024
256kB
+
efr32xg24xxxxf1536_196
256kB
+
efr32xg24xxxxf1536_256
256kB
@@ -177,11 +183,14 @@ Allocated @ref ram_memory "RAM memory" for application, by the processor is
Processor
RAM memory
efr32xg12pxxxf1024
72kB
efr32xg12pxxxf512
8kB
-
efr32xg13pxxxf512
16kB
efr32xg21xxxxf512
12kB
efr32xg21xxxxf768
12kB
efr32xg21xxxxf1024
44kB
efr32xg22xxxxf512
4.5kB
+
efr32xg23xxxxf512
12kB
+
efr32xg24xxxxf1024
72kB
+
efr32xg22xxxxf1536_196
140kB
+
efr32xg22xxxxf1536_256
155kB
@subsection peripherals_accessible_by_stack_only2 Peripherals accessible by stack only
@@ -199,18 +208,13 @@ Some peripherals are used by the Wirepas Mesh stack and cannot be used by the ap
All the internal interrupt of cortex M are handled by the stack directly (NMI, HardFault,...)
-@subsection peripherals_shared_between_the_stack_and_the_application2 Peripherals Shared between the stack and the application
+@subsection peripherals_shared_between_the_stack_and_the_application2 Peripherals shared between the stack and the application
-Some peripherals are used by the stack but can also be accessed by the application.
-
-These peripherals must be reserved through the API before being used and the application must initialize them each time after reserving it. In fact, the stack may configure them differently.
-
-It is also important to avoid long reservation of theses peripherals to let the stack use them for its own purpose.
-
-
-
Peripheral
Reservation ID (from @ref app_lib_hardware_peripheral_e)
-
ADC0
@ref APP_LIB_HARDWARE_PERIPHERAL_ADC
-
+True Random Number Generator TRNG is available for application to use within App_init function.
+After App_init returns, this peripheral is reserved for Wirepas Mesh stack and all initializations done in App_init may be overwritten.
+Application may also take the control of RNG/TRNG by initializing the peripheral in scheduled task after App_init has returned and after
+Wirepas Mesh stack has started. Do note that initialization must not take place within interrupt context as interrupt could be served
+before this peripheral is released from Wirepas Mesh stack usage.
@subsection peripherals_available_for_the_application2 Peripherals available for the application
diff --git a/doc_src_doxy/a4_application_api.h b/doc_src_doxy/a4_application_api.h
index 562ad5dd..ecda0f69 100644
--- a/doc_src_doxy/a4_application_api.h
+++ b/doc_src_doxy/a4_application_api.h
@@ -273,7 +273,6 @@ are following:
Name (related to mcu/hal_api folder)
Description
-
@ref button.h "button.h"
Button functions
@ref ds.h "ds.h"
Deep sleep control module
@ref radio.h "radio.h"
Radio FEM (front-end module)
@@ -281,6 +280,8 @@ are following:
@ref hw_delay.h "hw_delay.h"
Hardware delay module
@ref i2c.h "i2c.h"
Simple minimal I2C master driver
+
@ref gpio.h "gpio.h"
GPIO functions
+
@ref button.h "button.h"
Button functions
@ref led.h "led.h"
LED functions
@ref power.h "power.h"
Enabling of DCDC converter
@ref spi.h "spi.h"
Simple minimal SPI master driver
diff --git a/doc_src_doxy/a5_application_examples.h b/doc_src_doxy/a5_application_examples.h
index fcd49935..e4fb0342 100644
--- a/doc_src_doxy/a5_application_examples.h
+++ b/doc_src_doxy/a5_application_examples.h
@@ -281,6 +281,7 @@ This page contains following sections:
- @subpage source_makefile_app_printing
- @subpage source_makefile_app_scheduler
- @subpage source_makefile_cflags
+- @subpage source_makefile_hal_gpio
- @subpage source_makefile_hal_button
- @subpage source_makefile_hal_hw_delay
- @subpage source_makefile_hal_i2c
@@ -338,6 +339,19 @@ CFLAGS += -DNETWORK_ADDRESS=$(default_network_address)
CFLAGS += -DNETWORK_CHANNEL=$(default_network_channel)
@endcode
+@subsection source_makefile_hal_gpio HAL_GPIO
+
+Using of @ref gpio.h "HAL for GPIOs" can be done by this flag.
+
+Example:
+@code
+# This application use HAL for GPIOs
+HAL_GPIO=yes
+@endcode
+
+@note: in order for application to be able to drive GPIOs, they must be
+defined in specific @ref board_folder "board".
+
@subsection source_makefile_hal_button HAL_BUTTON
Using of @ref button.h "HAL for buttons" can be done by this flag.
@@ -350,7 +364,6 @@ HAL_BUTTON=yes
@note: in order for application to be able to drive buttons, they must be
defined in specific @ref board_folder "board".
-@note This option is supported only on nRF52 architectures.
@subsection source_makefile_hal_hw_delay HAL_HW_DELAY
diff --git a/libraries/config.mk b/libraries/config.mk
index a8de3aa8..932257ec 100644
--- a/libraries/config.mk
+++ b/libraries/config.mk
@@ -27,7 +27,7 @@ app_config_filters=0
# shared_offline_modules+= + n
shared_offline_modules=0
-# Any library needing shared neighbors cllbacks must increment this variable
+# Any library needing shared neighbors callbacks must increment this variable
# this way:
# shared_neighbors_cbs+= + n
shared_neighbors_cbs=0
@@ -78,12 +78,20 @@ scheduler_tasks+= + 2
endif
ifeq ($(DUALMCU_LIB), yes)
-scheduler_tasks+= + 3
+HAL_GPIO=yes
+scheduler_tasks+= + 4
app_config_filters+= + 1
SHARED_DATA=yes
stack_state_cbs+= + 1
endif
+# RTC library
+ifeq ($(RTC), yes)
+scheduler_tasks+= + 1
+SHARED_DATA=yes
+APP_SCHEDULER=yes
+endif
+
#########
# Enabling libraries needed by other libs and check app input
#########
diff --git a/libraries/control_node/control_node.c b/libraries/control_node/control_node.c
index 2dea9aeb..7614b759 100644
--- a/libraries/control_node/control_node.c
+++ b/libraries/control_node/control_node.c
@@ -240,8 +240,6 @@ static uint32_t backup_route_task(void)
m_send_handle[1].sent = true;
m_data.dest_address = m_send_handle[1].address;
- /* Add eleasped time since first try to travel time. */
- m_data.delay = lib_time->getTimestampCoarse() - m_time_sent;
res = Shared_Data_sendData(&m_data, packet_sent_cb);
if (res != APP_LIB_DATA_SEND_RES_SUCCESS)
{
@@ -304,8 +302,6 @@ static void packet_sent_cb(const app_lib_data_sent_status_t * status)
{
app_lib_data_send_res_e res;
m_data.dest_address = m_send_handle[1].address;
- /* Add eleasped time since first try to travel time. */
- m_data.delay = lib_time->getTimestampCoarse() - m_time_sent;
res = Shared_Data_sendData(&m_data, packet_sent_cb);
m_send_handle[1].sent = true;
LOG(LVL_WARNING, "Sending to primary router failed, try backup");
@@ -400,7 +396,6 @@ static uint32_t diagnostic_task(void)
{
.bytes = (const uint8_t *)&diag,
.num_bytes = sizeof(control_diag_t),
- .delay = 0,
.tracking_id = APP_LIB_DATA_NO_TRACKING_ID,
.qos = APP_LIB_DATA_QOS_NORMAL,
.flags = APP_LIB_DATA_SEND_FLAG_NONE,
diff --git a/libraries/control_node/control_router.c b/libraries/control_node/control_router.c
index 14d6ffbb..81499847 100644
--- a/libraries/control_node/control_router.c
+++ b/libraries/control_node/control_router.c
@@ -67,7 +67,6 @@ app_lib_data_receive_res_e data_received (const shared_data_item_t * item,
{
.bytes = (const uint8_t *) &diag,
.num_bytes = sizeof(control_fwd_diag_t),
- .delay = 0,
.tracking_id = APP_LIB_DATA_NO_TRACKING_ID,
.qos = APP_LIB_DATA_QOS_NORMAL,
.flags = APP_LIB_DATA_SEND_FLAG_NONE,
diff --git a/libraries/dualmcu/api/DualMcuAPI.md b/libraries/dualmcu/api/DualMcuAPI.md
index da9d2f38..e3fbef36 100644
--- a/libraries/dualmcu/api/DualMcuAPI.md
+++ b/libraries/dualmcu/api/DualMcuAPI.md
@@ -348,10 +348,6 @@ the services. Table 3 list all the primitives and their primitive IDs.
| | MSAP-SCRATCHPAD_TARGET_READ.confirm| 0xA7 |
| | MSAP-SCRATCHPAD_BLOCK_READ.request | 0x28 |
| | MSAP-SCRATCHPAD_BLOCK_READ.confirm | 0xA8 |
-| | MSAP-MAX_QUEUE_TIME_WRITE.request | 0x4F |
-| | MSAP-MAX_QUEUE_TIME_WRITE.confirm | 0xCF |
-| | MSAP-MAX_QUEUE_TIME_READ.request | 0x50 |
-| | MSAP-MAX_QUEUE_TIME_READ.confirm | 0xD0 |
| CSAP | CSAP-ATTRIBUTE_WRITE.request | 0x0D |
| | CSAP-ATTRIBUTE_WRITE.confirm | 0x8D |
| | CSAP-ATTRIBUTE_READ.request | 0x0E |
@@ -503,7 +499,7 @@ value. Frame fields are described in the table below.
| *DestinationEndpoint* | 1 | 0 – 239 | See description in chapter [DSAP-DATA_TX.request](#DSAP-DATA_TX.request)
| *QoS* | 1 | 0 or 1 | See description in chapter [DSAP-DATA_TX.request](#DSAP-DATA_TX.request)
| *TXOptions* | 1 | 00xx xxxx (bitfield, where x can be 0 or 1) | See description in chapter [DSAP-DATA_TX.request](#DSAP-DATA_TX.request)
-| *BufferingDelay* | 4 | 0 – 4 294 967 295 | The time the PDU has been in the application buffers before it was transmitted over API. Expressed in units of 1/128th of a second.
+| *Reserved* | 4 | 0 | This value is reserved |
| *APDULength* | 1 | 1 – 102 | See description in chapter [DSAP-DATA_TX.request](#DSAP-DATA_TX.request)
| *APDU* | 1 – 102 | \- | See description in chapter [DSAP-DATA_TX.request](#DSAP-DATA_TX.request)
| *CRC* | 2 | \- | See section [General Frame Format](#General-Frame-Format)
@@ -530,7 +526,7 @@ Frame fields are described in the table below.
| *DestinationEndpoint* | 1 | 0 – 239 | See description in chapter [DSAP-DATA_TX.request](#DSAP-DATA_TX.request)
| *QoS* | 1 | 0 or 1 | See description in chapter [DSAP-DATA_TX.request](#DSAP-DATA_TX.request)
| *TXOptions* | 1 | 00xx xxxx (bitfield, where x can be 0 or 1) | See description in chapter [DSAP-DATA_TX.request](#DSAP-DATA_TX.request)
-| *BufferingDelay* | 4 | 0 – 4 294 967 295 | See description in chapter [DSAP-DATA_TX_TT.request](#DSAP-DATA_TX_TT.request)
+| *Reserved* | 4 | 0 | See description in chapter [DSAP-DATA_TX_TT.request](#DSAP-DATA_TX_TT.request)
| *FullPacketId* | 2 | 0 – 4095 | Id of the full message this fragment belongs. Only lowest twelve bits are meaningful.
| *FragmentOffset and flags* | 2 | see Description | - Bits 0..11:
Offset of this fragment inside the full packet (between 0 and 1499)
- Bits 12..14:
Reserved
- Bit 15:
Set if fragment is last one of full message
| *APDULength* | 1 | 1 – 102 | Size of this current fragment.
@@ -1365,8 +1361,8 @@ set the OTAP scratchpad target. It can only be set from a sink node.
| *Frame ID* | 1 | 0 – 255 | See section [General Frame Format](#General-Frame-Format)
| *Target sequence* | 1 | 1 – 254 | Target sequence for the scratchpad to handle (needed if action is 1, 2 or 3)
| *Target CRC* | 2 | 0 – 65535 | Target CRC for the scratchpad to handle (needed if action is 1, 2 or 3)
-| *Action* | 1 | 0 - 4 | Which action to apply to the target scratchpad. Actions are:
- 0 = No otap. There is no otap in the network (Target sequence and crc are not used in that case)
- 1 = Propagate only : target scratchpad is exchanged in network but not processed
- 2 = Propagate and process : target scratchpad is exchanged in network and processed by node immediatly upon reception
- 3 = Propagate and process with delay : target scratchpad is exchanged in network and processed by node after a given delay specified with param field. Delay starts when this info is received by nodes and when they receive the scratchpad too
- 4 = Legacy : Exchange and processing of scratchpad is managed the old way (sequence comparison for exchange and remote api command for processing)
-| *Param* | 1 | Depends on action| Only interpreted for action 3 to specify a delay. Delay is specified as followed:
- bits 7-6 are delay unit: 01 for minutes, 10 for hours and 11 for days (00 is invalid)
- bits 5..0 are the delay
As an example 0x4A is 10 minutes and 0x2d is 2 days
+| *Action* | 1 | 0 - 4 | Which action to apply to the target scratchpad. Actions are:
- 0 = No otap. There is no otap in the network (Target sequence and crc are not used in that case)
- 1 = Propagate only : target scratchpad is exchanged in network but not processed
- 2 = Propagate and process : target scratchpad is exchanged in network and processed by node immediatly upon reception
- 3 = Propagate and process with delay : target scratchpad is exchanged in network and processed by node after a given delay specified with param field. Delay starts when this info is received by nodes and when they receive the scratchpad too
+| *Param* | 1 | Depends on action| Only interpreted for action 3 to specify a delay. Delay is specified as followed:
- bits 7-6 are delay unit: 01 for minutes, 10 for hours and 11 for days (00 is invalid)
- bits 5..0 are the delay
As an example 0x4A is 10 minutes and 0xc2 is 2 days
| *CRC* | 2 | \- | See section [General Frame Format](#General-Frame-Format)
#### MSAP-SCRATCHPAD_TARGET_WRITE.confirm
@@ -1555,102 +1551,6 @@ MSAP-NRLS_GOTOSLEEP.request. Frame fields are described in the table below.
| LatestNRLS goto sleep time | 4 | 0 to 0x93A80 | Time in seconds which was used in previous NRLS sleep request starting from application NRLS sleep request until stack enters to NRLS sleep. Time is total time used including application callbacks during that period.
| *CRC* | 2 | \- | See section [General Frame Format](#General-Frame-Format)
-### MSAP-MAX_MESSAGE_QUEUING Service
-
-The maximum message queuing services are used to change or read the current
-value of the time for how long the message is hold in the node's queue before it
-is discarded. Queuing time can be changed to normal and high priority messages.
-Select queuing time carefully, too short value might cause unnecessary message
-drops and too big value filling up message queues. For consistent performance it
-is recommended to use the same queuing time in the whole network.
-Minimum queuing time shall be bigger than access cycle interval in TDMA
-networks. It is recommended to use multiples of access cycle interval (+ extra)
-to give time for message repetitions, higher priority messages taking over the
-access slot etc. Access cycle is not limiting the minimum value in CSMA-CA
-networks.
-Precision of the time when message is discarded depends on the checking interval
-of message's age. Interval is 1s in CSMA-CA and 15s for energy saving reasons in
-TDMA networks i.e. precision is 1s or 15s depending on used channel access
-method.
-The MSAP-MAX_MESSAGE_QUEUING service includes following primitives:
-
-- MSAP-MAX_QUEUE_TIME_WRITE.request
-
-- MSAP-MAX_QUEUE_TIME_WRITE.confirm
-
-- MSAP-MAX_QUEUE_TIME_READ.request
-
-- MSAP-MAX_QUEUE_TIME_READ.confirm
-
-#### MSAP-MAX_QUEUE_TIME_WRITE.request
-
-This request is issued by the application layer to change the maximum queuing
-time for messages.
-
-| **Primitive ID** | **Frame ID** | **Payload length** | **Priority** | **Time** | **CRC** |
-|------------------|--------------|--------------------|--------------|----------|----------|
-| 1 octet | 1 octet | 1 octet | 1 octet | 2 octets | 2 octets |
-
-Frame fields are described in the table below.
-
-| **Field Name** | **Size** | **Valid Values** | **Description**
-|----------------|----------|------------------|----------------
-| *Primitive ID* | 1 | 0x4F | Identifier of MSAP-MAX_QUEUE_TIME_WRITE.request primitive
-| *Frame ID* | 1 | 0 – 255 | See section [General Frame Format](#General-Frame-Format)
-| *Priority* | 1 | 0 - 1 | Message priority which queuing time to be set.
- 0 = User traffic class 0, i.e. normal priority
- 1 = User traffic class 1, i.e. high priority.
-| *Time* | 4 | 2 – 65534 | Maximum queuing time in seconds. Read instructions in chapter 2.3.15. Default time values after factory reset:
- Normal priority: 600s = 10 min.
- High priority: 300s = 5 min.
-| *CRC* | 2 | \- | See section [General Frame Format](#General-Frame-Format)
-
-#### MSAP-MAX_QUEUE_TIME_WRITE.confirm
-
-The MSAP-MAX_QUEUE_TIME_WRITE.confirm is issued in response to the
-MSAP-MAX_QUEUE_TIME_WRITE.request. Frame fields are described in the table
-below.
-
-| **Field Name** | **Size** | **Valid Values** | **Description**
-|----------------|----------|------------------|----------------
-| *Primitive ID* | 1 | 0xCF | Identifier of MSAP-MAX_QUEUE_TIME_WRITE.confirm primitive
-| *Frame ID* | 1 | 0 – 255 | See section [General Frame Format](#General-Frame-Format)
-| *Result* | 1 | 0, 3 | The return result of the corresponding MSAP-MAX_QUEUE_TIME_WRITE.request:
- 0 = Success
- 3 = Failure: Invalid priority or time
-| *CRC* | 2 | \- | See section [General Frame Format](#General-Frame-Format)
-
-#### MSAP-MAX_QUEUE_TIME_READ.request
-
-This request is issued by the application layer to read the current value of the
-maximum queuing time.
-
-| **Primitive ID** | **Frame ID** | **Payload length** | **Priority** | **CRC** |
-|------------------|--------------|--------------------|--------------|----------|
-| 1 octet | 1 octet | 1 octet | 1 octet | 2 octets |
-
-Frame fields are described in the table below.
-
-| **Field Name** | **Size** | **Valid Values** | **Description**
-|----------------|----------|------------------|----------------
-| *Primitive ID* | 1 | 0x50 | Identifier of MSAP-MAX_QUEUE_TIME_READ.request primitive
-| *Frame ID* | 1 | 0 – 255 | See section [General Frame Format](#General-Frame-Format)
-| *Priority* | 1 | 0 - 1 | Message priority which queuing time to be read.
- 0 = User traffic class 0, i.e. normal priority
- 1 = User traffic class 1, i.e. high priority
-| *CRC* | 2 | \- | See section [General Frame Format](#General-Frame-Format)
-
-#### MSAP-MAX_QUEUE_TIME_READ.confirm
-
-The MSAP-MAX_QUEUE_TIME_READ.confirm is issued in response to the
-MSAP-MAX_QUEUE_TIME_READ.request.
-
-| **Primitive ID** | **Frame ID** | **Payload length** | **Result** | **Time** | **CRC** |
-|------------------|--------------|--------------------|------------|----------|----------|
-| 1 octet | 1 octet | 1 octet | 1 octet | 2 octets | 2 octets |
-
-Frame fields are described in the table below.
-
-| **Field Name** | **Size** | **Valid Values** | **Description**
-|----------------|----------|------------------|----------------
-| *Primitive ID* | 1 | 0xD0 | Identifier of MSAP-MAX_QUEUE_TIME_READ.confirm primitive
-| *Frame ID* | 1 | 0 – 255 | See section [General Frame Format](#General-Frame-Format)
-| *Result* | 1 | 0, 3 | The return result of the corresponding MSAP-MAX_QUEUE_TIME_READ.request:
- 0 = Success
- 3 = Failure: Invalid priority
-| *Time* | 2 | 2 - 65534 | Read value of maximum queuing time in seconds
-| *CRC* | 2 | \- | See section [General Frame Format](#General-Frame-Format)
-
### MSAP Attributes
The MSAP attributes are specified in Table 45.
@@ -2002,7 +1902,6 @@ The CSAP attributes are specified in Table 50.
| [cHwMagic](#cHwMagic) | 17 | R | 2 |
| [cStackProfile](#cStackProfile) | 18 | R | 2 |
| [cOfflineScan](#cOfflineScan) | 20 | R/W | 2 |
-| [cChannelAllocMap](#cChannelAllocMap) | 21 | R/W | 4 |
| [cFeatureLockBits](#cFeatureLockBits) | 22 | R/W | 4 |
| [cFeatureLockKey](#cFeatureLockKey) | 23 | W | 16 |
@@ -2336,33 +2235,6 @@ value in seconds. When the device does not have a route to the sink, this
interval is used to find the route. The scanning interval is a tradeoff between
faster rejoin time to the network with the expense of power consumption.
-#### cChannelAllocMap
-
-| **Attribute ID** | **21** |
-|------------------|-------------------|
-| Type | Read and write |
-| Size | 4 octets |
-| Valid values | 0x00 – 0xFFFFFFFE |
-| Default value | 0x11111111 |
-
-Attribute cChannelAllocMap can be used to dedicate radio channels for devices
-that have CB-MAC role definition enabled or devices that do not .
-Each bit in the value represents one radio channel. LSB equals the first
-available channel. If bit is set, the radio channel is dedicated for devices
-that are configured to CB-MAC mode. If bit is not set, the radio channel is
-dedicated for devices that are not configured to CB-MAC mode. The default value
-equals 25% of channels to be dedicated for devices configured to CB-MAC mode.
-This attribute is mainly important in dense networks and by using this
-attribute, the amount of devices within radio range can be maximized. For
-example: if none of the devices are configured to CB-MAC mode, it is recommended
-to set this value as 0.
-**Note: This attribute must be the same throughout the network to operate
-correctly!**
-**Note: WM FW v3.6.0, v3.6.6, v3.6.7, v3.5.32, v3.5.36 releases and v4.0.xx
-release onwards cChannelAllocMap attribute does not exists anymore - writing
-this attribute will return an error code** (1 = Failure: Unsupported attribute
-ID).
-
#### cFeatureLockBits
| **Attribute ID** | **22** |
diff --git a/libraries/dualmcu/drivers/efr32/exti.c b/libraries/dualmcu/drivers/efr32/exti.c
deleted file mode 100644
index ea368f42..00000000
--- a/libraries/dualmcu/drivers/efr32/exti.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/* Copyright 2019 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-#include
-#include
-
-#include "hal_api.h"
-#include "io.h"
-#include "board.h"
-#include "api.h"
-#include "em_gpio.h"
-
-// Amount of channels per vector (IO port width / 2)
-#define IRQ_CHANNELS_PER_VECTOR 8
-
-// Callbacks
-static wakeup_cb_f m_even_callbacks[IRQ_CHANNELS_PER_VECTOR];
-static wakeup_cb_f m_odd_callbacks[IRQ_CHANNELS_PER_VECTOR];
-
-// Declare ISR
-void __attribute__((__interrupt__)) GPIO_EVEN_IRQHandler(void);
-void __attribute__((__interrupt__)) GPIO_ODD_IRQHandler(void);
-
-static inline void clear_interrupt(uint32_t pin)
-{
-#if defined(_SILICON_LABS_32B_SERIES_1)
- /** IFC is a latch register, safe to use without bit-band */
- GPIO->IFC = (1 << pin);
-#elif defined(_SILICON_LABS_32B_SERIES_2)
- GPIO->IF_CLR = (1 << pin);
-#else
-#error "Unknown EFR32 series and config"
-#endif
-}
-
-static void pin_config(uint32_t pin, uint32_t port)
-{
- // Code does not set GPIO->EXTIPINSELL or GPIO->EXTIPINSELH
- // thus direct mapping: pin x ==> EXTI x is used.
- if (pin < 8)
- {
- GPIO->EXTIPSELL = (GPIO->EXTIPSELL & ~(0xF << (4 * pin))) |
- (port << (4 * pin));
- }
-#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1)
- else
- {
- GPIO->EXTIPSELH = (GPIO->EXTIPSELH & ~(0xF << (4 * (pin - 8)))) |
- (port << (4 * (pin - 8)));
- }
-#endif
-}
-
-void Wakeup_pinInit(wakeup_cb_f cb)
-{
- /* Clear interrupt sources and flags */
- GPIO->IEN = _GPIO_IEN_RESETVALUE;
-#if defined(_SILICON_LABS_32B_SERIES_1)
- GPIO->IFC = _GPIO_IFC_MASK;
-#elif defined(_SILICON_LABS_32B_SERIES_2)
- GPIO->IF_CLR = _GPIO_IF_MASK;
-#else
-#error "Unknown EFR32 series and config"
-#endif
- uint32_t pin = BOARD_USART_RX_PIN;
- uint32_t index = pin;
- index >>= 1;
- if((pin % 2) == 0)
- {
- /* Even IRQ (only one pin per channel supported) */
- m_even_callbacks[index] = cb;
- }
- else
- {
- /* Odd IRQ (only one pin per channel supported) */
- m_odd_callbacks[index] = cb;
- }
-
- pin_config(BOARD_USART_RX_PIN, BOARD_USART_GPIO_PORT);
- /* Enable interrupt source for even pins */
- Sys_clearFastAppIrq(GPIO_EVEN_IRQn);
- Sys_enableFastAppIrq(GPIO_EVEN_IRQn,
- APP_LIB_SYSTEM_IRQ_PRIO_HI,
- GPIO_EVEN_IRQHandler);
- Sys_clearFastAppIrq(GPIO_ODD_IRQn);
- Sys_enableFastAppIrq(GPIO_ODD_IRQn,
- APP_LIB_SYSTEM_IRQ_PRIO_HI,
- GPIO_ODD_IRQHandler);
-}
-
-void Wakeup_off(void)
-{
- Sys_disableAppIrq(GPIO_EVEN_IRQn);
- Sys_clearFastAppIrq(GPIO_EVEN_IRQn);
- Sys_disableAppIrq(GPIO_ODD_IRQn);
- Sys_clearFastAppIrq(GPIO_ODD_IRQn);
-}
-
-void Wakeup_clearIrq(void)
-{
- clear_interrupt(BOARD_USART_RX_PIN);
-}
-
-void Wakeup_setEdgeIRQ(exti_irq_config_e edge, bool enable)
-{
- bool risingEdge, fallingEdge;
- edge & EXTI_IRQ_RISING_EDGE ? (risingEdge = true) : (risingEdge = false);
- edge & EXTI_IRQ_FALLING_EDGE ? (fallingEdge = true) : (fallingEdge = false);
- GPIO_IntConfig((GPIO_Port_TypeDef)BOARD_USART_GPIO_PORT, BOARD_USART_RX_PIN,
- risingEdge,
- fallingEdge,
- enable);
-}
-
-void __attribute__((__interrupt__)) GPIO_EVEN_IRQHandler(void)
-{
-#if defined(_SILICON_LABS_32B_SERIES_1)
- uint32_t epin = GPIO->IF & _GPIO_IF_EXT_MASK;
- epin &= GPIO->IEN & _GPIO_IEN_EXT_MASK;
-#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1)
- uint32_t epin = GPIO->IF & _GPIO_IF_EXT_MASK;
- epin &= GPIO->IEN & _GPIO_IEN_EXTIEN_MASK;
-#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3)
- uint32_t epin = GPIO->IF & 0x0FFF;
- epin &= GPIO->IEN & 0x0FFF;
-#else
-#error "Unknown EFR32 series and config"
-#endif
- uint32_t index;
- for(index = 0; index < IRQ_CHANNELS_PER_VECTOR; index++)
- {
- if((epin & 0x01) == 0x01)
- {
- clear_interrupt(2 * index);
- if(m_even_callbacks[index] != NULL)
- {
- m_even_callbacks[index]();
- }
- }
- epin >>= 2;
- }
-}
-
-void __attribute__((__interrupt__)) GPIO_ODD_IRQHandler(void)
-{
-#if defined(_SILICON_LABS_32B_SERIES_1)
- uint32_t opin = GPIO->IF & _GPIO_IF_EXT_MASK;
- opin &= GPIO->IEN & _GPIO_IEN_EXT_MASK;
-#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1)
- uint32_t opin = GPIO->IF & _GPIO_IF_EXT_MASK;
- opin &= GPIO->IEN & _GPIO_IEN_EXTIEN_MASK;
-#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3)
- uint32_t opin = GPIO->IF & 0x0FFF;
- opin &= GPIO->IEN & 0x0FFF;
-#else
-#error "Unknown EFR32 series and config"
-#endif
- opin >>= 1;
- uint32_t index;
- for(index = 0; index < IRQ_CHANNELS_PER_VECTOR; index++)
- {
- if((opin & 0x01) == 0x01)
- {
- clear_interrupt(2 * index + 1);
- if(m_odd_callbacks[index] != NULL)
- {
- m_odd_callbacks[index]();
- }
- }
- opin >>= 2;
- }
-}
-
diff --git a/libraries/dualmcu/drivers/efr32/io.c b/libraries/dualmcu/drivers/efr32/io.c
deleted file mode 100644
index c62241cb..00000000
--- a/libraries/dualmcu/drivers/efr32/io.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/* Copyright 2019 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-
-#include "hal_api.h"
-#include "io.h"
-#include "board.h"
-
-#if defined(BOARD_UART_INT_PIN) && defined(BOARD_UART_INT_PORT)
-
-void Io_init(void)
-{
-// /* Enable clocks */
- CMU->HFBUSCLKEN0 |= CMU_HFBUSCLKEN0_GPIO;
-
- hal_gpio_set_mode(BOARD_UART_INT_PORT,
- BOARD_UART_INT_PIN,
- GPIO_MODE_DISABLED);
- hal_gpio_clear(BOARD_UART_INT_PORT,
- BOARD_UART_INT_PIN);
-}
-
-void Io_enableUartIrq(void)
-{
-
- hal_gpio_set_mode(BOARD_UART_INT_PORT,
- BOARD_UART_INT_PIN,
- GPIO_MODE_OUT_PP);
-}
-
-void Io_setUartIrq(void)
-{
- // Active low IRQ pin
- hal_gpio_clear(BOARD_UART_INT_PORT,
- BOARD_UART_INT_PIN);
-}
-
-void Io_clearUartIrq(void)
-{
- // To clear we pull pin up
- hal_gpio_set(BOARD_UART_INT_PORT,
- BOARD_UART_INT_PIN);
-}
-
-void Io_setModeDisabled(void)
-{
- // Disable pin
- hal_gpio_set_mode(BOARD_UART_INT_PORT,
- BOARD_UART_INT_PIN,
- GPIO_MODE_DISABLED);
-}
-
-#else
-// IRQ pin not defined, no functionality
-void Io_init(void)
-{
-}
-
-void Io_enableUartIrq(void)
-{
-}
-
-void Io_setUartIrq(void)
-{
-}
-
-void Io_clearUartIrq(void)
-{
-}
-#endif
diff --git a/libraries/dualmcu/drivers/efr32/makefile b/libraries/dualmcu/drivers/efr32/makefile
deleted file mode 100644
index 292e78eb..00000000
--- a/libraries/dualmcu/drivers/efr32/makefile
+++ /dev/null
@@ -1,4 +0,0 @@
-EFR32_DRIVERS_PREFIX := $(DRIVERS_PREFIX)efr32/
-
-SRCS += $(EFR32_DRIVERS_PREFIX)exti.c \
- $(EFR32_DRIVERS_PREFIX)io.c
diff --git a/libraries/dualmcu/drivers/indication_signal.c b/libraries/dualmcu/drivers/indication_signal.c
new file mode 100644
index 00000000..462457b6
--- /dev/null
+++ b/libraries/dualmcu/drivers/indication_signal.c
@@ -0,0 +1,54 @@
+/* Copyright 2022 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+
+/**
+ * \file indication_signal.c
+ * \brief Used to generate the Interrupt ReQuest ("IRQ") signal to notify the application that it has one or more pending indications.
+ */
+
+#include "board.h"
+#include "gpio.h"
+
+#ifdef BOARD_GPIO_ID_UART_IRQ
+
+void IndicationSignal_enable(void)
+{
+ const gpio_out_cfg_t gpio_out_cfg =
+ {
+ .out_mode_cfg = GPIO_OUT_MODE_PUSH_PULL,
+ .level_default = GPIO_LEVEL_HIGH // Active low IRQ pin
+ };
+
+ Gpio_outputSetCfg(BOARD_GPIO_ID_UART_IRQ, &gpio_out_cfg);
+}
+
+void IndicationSignal_set(void)
+{
+ // Active low IRQ pin
+ Gpio_outputWrite(BOARD_GPIO_ID_UART_IRQ, GPIO_LEVEL_LOW);
+}
+
+void IndicationSignal_clear(void)
+{
+ // Active low IRQ pin
+ Gpio_outputWrite(BOARD_GPIO_ID_UART_IRQ, GPIO_LEVEL_HIGH);
+}
+
+#else // else if BOARD_GPIO_ID_UART_IRQ is undefined
+
+void IndicationSignal_enable(void)
+{
+}
+
+void IndicationSignal_set(void)
+{
+}
+
+void IndicationSignal_clear(void)
+{
+}
+
+#endif // BOARD_GPIO_ID_UART_IRQ
diff --git a/libraries/dualmcu/drivers/indication_signal.h b/libraries/dualmcu/drivers/indication_signal.h
new file mode 100644
index 00000000..a72e2c35
--- /dev/null
+++ b/libraries/dualmcu/drivers/indication_signal.h
@@ -0,0 +1,30 @@
+/* Copyright 2022 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+
+/**
+ * \file indication_signal.h
+ * \brief Used to generate the Interrupt ReQuest ("IRQ") signal to notify the application that it has one or more pending indications.
+ */
+
+#ifndef INDICATION_SIGNAL_
+#define INDICATION_SIGNAL_
+
+/**
+ * \brief Enables indication signal (UART IRQ) pin
+ */
+void IndicationSignal_enable(void);
+
+/**
+ * \brief Sets (asserts) indication signal (UART IRQ) pin
+ */
+void IndicationSignal_set(void);
+
+/**
+ * \brief Clears (de-asserts) indication signal (UART IRQ) pin
+ */
+void IndicationSignal_clear(void);
+
+#endif /* INDICATION_SIGNAL_ */
diff --git a/libraries/dualmcu/drivers/io.h b/libraries/dualmcu/drivers/io.h
deleted file mode 100644
index e6641d1a..00000000
--- a/libraries/dualmcu/drivers/io.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/* Copyright 2017 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-#ifndef EXTI_H_
-#define EXTI_H_
-
-#include "api.h"
-
-/**
- * \brief Initialize IO's to a known state
- *
- */
-void Io_init(void);
-
-/**
- * \brief Enables UART IRQ pin
- */
-void Io_enableUartIrq(void);
-
-/**
- * \brief Sets (asserts) UART IRQ pin
- */
-void Io_setUartIrq(void);
-
-/**
- * \brief Clears (de-asserts) UART IRQ pin
- */
-void Io_clearUartIrq(void);
-
-typedef enum
-{
- EXTI_IRQ_RISING_EDGE = 0x01,
- EXTI_IRQ_FALLING_EDGE = 0x10,
- EXTI_IRQ_STATE_CHANGE = EXTI_IRQ_RISING_EDGE | EXTI_IRQ_FALLING_EDGE
-}exti_irq_config_e;
-
-/**
- * \brief Mandatory callback for EXTI events
- */
-typedef void (*wakeup_cb_f)(void);
-
-/**
- * \brief Setup wake-up pin
- * \param cb
- * Mandatory callback that is invoked on event
- * \post Pin (EXTI channel) is fired and waiting for a falling edge trigger
- */
-void Wakeup_pinInit(wakeup_cb_f cb);
-
-/**
- * \brief Disable wake-up functionality.
- */
-void Wakeup_off(void);
-
-/**
- * \brief Clear interrupt source flag
- */
-void Wakeup_clearIrq(void);
-
-/**
- * \brief Change edge for wake-up pin
- * \param edge
- * Edge type to configure
- * \param enable
- * Enable pin interrrupt
- */
-void Wakeup_setEdgeIRQ(exti_irq_config_e edge, bool enable);
-#endif /* EXTI_H_ */
diff --git a/libraries/dualmcu/drivers/makefile b/libraries/dualmcu/drivers/makefile
index 88d7bd39..51a3ab51 100644
--- a/libraries/dualmcu/drivers/makefile
+++ b/libraries/dualmcu/drivers/makefile
@@ -3,10 +3,5 @@ DRIVERS_PREFIX := $(WP_LIB_PATH)dualmcu/drivers/
INCLUDES += -I$(DRIVERS_PREFIX)
-ifneq (,$(filter $(MCU), nrf52 nrf91))
- include $(DRIVERS_PREFIX)nrf/makefile
-else ifeq ($(MCU),efr32)
- include $(DRIVERS_PREFIX)efr32/makefile
-else
- $(error Cannot determine MCU for drivers)
-endif
+SRCS += $(DRIVERS_PREFIX)indication_signal.c
+SRCS += $(DRIVERS_PREFIX)uart_wakeup.c
diff --git a/libraries/dualmcu/drivers/nrf/exti.c b/libraries/dualmcu/drivers/nrf/exti.c
deleted file mode 100644
index 2163ba46..00000000
--- a/libraries/dualmcu/drivers/nrf/exti.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* Copyright 2017 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-#include
-#include
-
-#include "hal_api.h"
-#include "io.h"
-#include "api.h"
-#include "board.h"
-
-#ifndef UART_USE_USB
-// Callback for wake-up pin
-static wakeup_cb_f m_callback;
-
-// Declare the GPIOTE ISR
-void __attribute__((__interrupt__)) GPIOTE_IRQHandler(void);
-
-void Wakeup_pinInit(wakeup_cb_f cb)
-{
- // Clear interrupt sources and flags
- NRF_GPIOTE->INTENCLR = 0xFFFFFFFF;
- NRF_GPIOTE->EVENTS_PORT = 0;
- // Start with falling edge trigger
- nrf_gpio_cfg_sense_set(BOARD_USART_RX_PIN, NRF_GPIO_PIN_SENSE_LOW);
- m_callback = cb;
- Sys_clearFastAppIrq(GPIOTE_IRQn);
- Sys_enableFastAppIrq(GPIOTE_IRQn,
- APP_LIB_SYSTEM_IRQ_PRIO_HI,
- GPIOTE_IRQHandler);
-}
-
-void Wakeup_off(void)
-{
- Sys_disableAppIrq(GPIOTE_IRQn);
- Sys_clearFastAppIrq(GPIOTE_IRQn);
-}
-
-void Wakeup_clearIrq(void)
-{
- NRF_GPIOTE->EVENTS_PORT = 0;
-}
-
-void Wakeup_setEdgeIRQ(exti_irq_config_e edge, bool enable)
-{
- uint8_t mode = NRF_GPIO_PIN_NOSENSE;
- if(edge & EXTI_IRQ_RISING_EDGE)
- {
- mode = NRF_GPIO_PIN_SENSE_HIGH;
- }
- else if(edge & EXTI_IRQ_FALLING_EDGE)
- {
- mode = NRF_GPIO_PIN_SENSE_LOW;
- }
-
- /* Enable/disable the rising edge interrupt. */
- nrf_gpio_cfg_sense_set(BOARD_USART_RX_PIN, mode);
-
- /* Clear any pending interrupt. */
- Wakeup_clearIrq();
-
- /* Finally enable/disable interrupt. */
- if (enable)
- {
- NRF_GPIOTE->INTENSET = GPIOTE_INTENSET_PORT_Msk;
- }
- else
- {
- NRF_GPIOTE->INTENCLR = GPIOTE_INTENSET_PORT_Msk;
- }
-}
-
-void __attribute__((__interrupt__)) GPIOTE_IRQHandler(void)
-{
- if (NRF_GPIOTE->EVENTS_PORT != 0)
- {
- NRF_GPIOTE->EVENTS_PORT = 0;
- // read any event from peripheral to flush the write buffer:
- EVENT_READBACK = NRF_GPIOTE->EVENTS_PORT;
- if (m_callback)
- {
- m_callback();
- }
- }
-}
-#else
-// With USB connection, no wakeup mechanism (not needed)
-void Wakeup_pinInit(wakeup_cb_f cb)
-{
- (void) cb;
-}
-
-void Wakeup_off(void)
-{
-}
-
-void Wakeup_clearIrq(void)
-{
-}
-
-void Wakeup_setEdgeIRQ(exti_irq_config_e edge, bool enable)
-{
-}
-#endif
diff --git a/libraries/dualmcu/drivers/nrf/io.c b/libraries/dualmcu/drivers/nrf/io.c
deleted file mode 100644
index 8bb15a3f..00000000
--- a/libraries/dualmcu/drivers/nrf/io.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* Copyright 2017 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-
-#include "hal_api.h"
-#include "board.h"
-
-#ifdef BOARD_UART_IRQ_PIN
-
-void Io_init(void)
-{
- // Disconnect uart_irq_pin
- nrf_gpio_cfg_default(BOARD_UART_IRQ_PIN);
- // But set light pull-up
- nrf_gpio_pin_set(BOARD_UART_IRQ_PIN);
-}
-
-void Io_enableUartIrq(void)
-{
- nrf_gpio_cfg(BOARD_UART_IRQ_PIN,
- NRF_GPIO_PIN_DIR_OUTPUT,
- NRF_GPIO_PIN_INPUT_CONNECT,
- NRF_GPIO_PIN_NOPULL,
- NRF_GPIO_PIN_S0S1,
- NRF_GPIO_PIN_NOSENSE);
-}
-
-void Io_setUartIrq(void)
-{
- // Active low IRQ pin
- nrf_gpio_pin_clear(BOARD_UART_IRQ_PIN);
-}
-
-void Io_clearUartIrq(void)
-{
- // To clear we pull pin up
- nrf_gpio_pin_set(BOARD_UART_IRQ_PIN);
-}
-
-#else
-
-// IRQ pin not defined, no functionality
-void Io_init(void)
-{
-}
-
-void Io_enableUartIrq(void)
-{
-}
-
-void Io_setUartIrq(void)
-{
-}
-
-void Io_clearUartIrq(void)
-{
-}
-
-#endif
diff --git a/libraries/dualmcu/drivers/nrf/makefile b/libraries/dualmcu/drivers/nrf/makefile
deleted file mode 100644
index f5b1a12f..00000000
--- a/libraries/dualmcu/drivers/nrf/makefile
+++ /dev/null
@@ -1,4 +0,0 @@
-NRF_DRIVERS_PREFIX := $(DRIVERS_PREFIX)nrf/
-
-SRCS += $(NRF_DRIVERS_PREFIX)exti.c \
- $(NRF_DRIVERS_PREFIX)io.c \
diff --git a/libraries/dualmcu/drivers/uart_wakeup.c b/libraries/dualmcu/drivers/uart_wakeup.c
new file mode 100644
index 00000000..18c4c60a
--- /dev/null
+++ b/libraries/dualmcu/drivers/uart_wakeup.c
@@ -0,0 +1,53 @@
+/* Copyright 2022 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+
+/**
+ * \file uart_wakeup.c
+ * \brief Used to detect rising/falling edges on the UART RX GPIO in order to wake up the UART receiver.
+ */
+
+#include "gpio.h"
+#include "board.h"
+#include "hal_api.h"
+
+#ifndef UART_USE_USB
+
+void UartWakeup_enable(gpio_in_event_cb_f cb)
+{
+ const gpio_in_cfg_t gpio_in_cfg =
+ {
+ .event_cb = cb,
+ .event_cfg = GPIO_IN_EVENT_RISING_EDGE | GPIO_IN_EVENT_FALLING_EDGE,
+ .in_mode_cfg = GPIO_IN_PULL_NONE
+ };
+
+ Gpio_inputSetCfg(BOARD_GPIO_ID_USART_WAKEUP, &gpio_in_cfg);
+}
+
+void UartWakeup_disable(void)
+{
+ const gpio_in_cfg_t gpio_in_cfg =
+ {
+ .event_cb = NULL,
+ .event_cfg = GPIO_IN_EVENT_NONE,
+ .in_mode_cfg = GPIO_IN_PULL_NONE
+ };
+
+ Gpio_inputSetCfg(BOARD_GPIO_ID_USART_WAKEUP, &gpio_in_cfg);
+}
+
+#else // else if UART_USE_USB is defined
+// With USB connection, no wakeup mechanism (not needed)
+
+void UartWakeup_enable(gpio_in_event_cb_f cb)
+{
+}
+
+void UartWakeup_disable(void)
+{
+}
+
+#endif // UART_USE_USB
diff --git a/libraries/dualmcu/drivers/uart_wakeup.h b/libraries/dualmcu/drivers/uart_wakeup.h
new file mode 100644
index 00000000..ca84054e
--- /dev/null
+++ b/libraries/dualmcu/drivers/uart_wakeup.h
@@ -0,0 +1,29 @@
+/* Copyright 2022 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+
+/**
+ * \file uart_wakeup.c
+ * \brief Used to detect rising/falling edges on the UART RX GPIO in order to wake up the UART receiver.
+ */
+
+#ifndef UART_WAKEUP_
+#define UART_WAKEUP_
+
+#include "gpio.h"
+
+/**
+ * \brief Enable wake-up functionality.
+ * \param cb
+ * Callback that is invoked on GPIO edge transition
+ */
+void UartWakeup_enable(gpio_in_event_cb_f cb);
+
+/**
+ * \brief Disable wake-up functionality.
+ */
+void UartWakeup_disable(void);
+
+#endif /* UART_WAKEUP_ */
diff --git a/libraries/dualmcu/dualmcu_lib.c b/libraries/dualmcu/dualmcu_lib.c
index ce860320..4f97a33d 100644
--- a/libraries/dualmcu/dualmcu_lib.c
+++ b/libraries/dualmcu/dualmcu_lib.c
@@ -1,12 +1,8 @@
#include "dualmcu_lib.h"
-#include "io.h"
#include "waps.h"
dualmcu_lib_res_e Dualmcu_lib_init(uint32_t baudrate, bool flow_ctrl)
{
- // Initialize IO's (enable clock and initialize pins)
- Io_init();
-
// Initialize the Dual-MCU API protocol
if (Waps_init(baudrate, flow_ctrl))
{
diff --git a/libraries/dualmcu/waps/comm/uart/waps_uart.c b/libraries/dualmcu/waps/comm/uart/waps_uart.c
index c3affe81..5ae66daf 100644
--- a/libraries/dualmcu/waps/comm/uart/waps_uart.c
+++ b/libraries/dualmcu/waps/comm/uart/waps_uart.c
@@ -10,7 +10,7 @@
#include
#include
-#include "io.h"
+#include "indication_signal.h"
#include "usart.h"
#include "crc.h"
#include "waps/waps_buffer_sizes.h"
@@ -119,8 +119,8 @@ void Waps_uart_powerReset(void)
}
// Initialize UART IRQ pin
- Io_enableUartIrq();
- Io_clearUartIrq();
+ IndicationSignal_enable();
+ IndicationSignal_clear();
}
bool Waps_uart_send(const void * buffer, uint32_t size)
@@ -160,12 +160,12 @@ void Waps_uart_setIrq(bool state)
if(state)
{
// Assert IRQ pin
- Io_setUartIrq();
+ IndicationSignal_set();
}
else
{
// De-assert IRQ pin
- Io_clearUartIrq();
+ IndicationSignal_clear();
}
}
@@ -178,6 +178,7 @@ static void frame_completed(void)
{
uint32_t pld_size;
crc_t crc_1, crc_2;
+ uint8_t error = 0;
/* Step 1: see if frame makes any sense */
if(m_rx_buffer_idx >= sizeof(crc_t))
{
@@ -206,26 +207,41 @@ static void frame_completed(void)
(void)m_frame_cb((void *)m_rx_buffer, pld_size);
}
}
-#if defined WAPS_DIAGNOSTICS
else
{
+ error = 1;
+#if defined WAPS_DIAGNOSTICS
m_waps_diagnostics.crc_error++;
- }
#endif /* WAPS_DIAGNOSTICS */
+ }
}
-#if defined WAPS_DIAGNOSTICS
else
{
+ error = 2;
+#if defined WAPS_DIAGNOSTICS
m_waps_diagnostics.frame_size_out_of_bounds_error++;
- }
#endif /* WAPS_DIAGNOSTICS */
+ }
}
-#if defined WAPS_DIAGNOSTICS
else
{
+ error = 3;
+#if defined WAPS_DIAGNOSTICS
m_waps_diagnostics.way_too_short_frame_error++;
- }
#endif /* WAPS_DIAGNOSTICS */
+ }
+
+ if ( error != 0)
+ {
+ // Error in reception from host, so no answer will be provided.
+ // In order to avoid host waiting for timeout
+ // return back the error by generating ourself a dummy response
+ // containing a CRC error (CRC being 0xFFFF, it cannot be valid)
+ // (payload size must be at least 4)
+ /* Dummy message containing a CRC error (So host can interpret it as a propagated CRC error) */
+ uint8_t dummy_invalid_crc_message[] = {SLIP_END, error, m_rx_buffer_idx & 0xFF, (m_rx_buffer_idx >> 8) & 0xFF, 0xFF, 0xFF, SLIP_END};
+ Usart_sendBuffer(&dummy_invalid_crc_message, sizeof(dummy_invalid_crc_message));
+ }
reset_rx_buffer();
}
@@ -290,6 +306,10 @@ static void waps_uart_receive(uint8_t * chars, size_t n)
static bool is_autopower_in_use(void)
{
+#if BOARD_HW_CRYSTAL_32K == 0
+ // Auto power mechanism cannot be used without 32kHz crystal.
+ return false;
+#else
app_lib_settings_role_t node_role;
if (m_baudrate > MAX_BAUDRATE_FOR_AUTOPOWER)
{
@@ -325,6 +345,7 @@ static bool is_autopower_in_use(void)
// Enable it in all other cases
return true;
+#endif
}
__STATIC_INLINE void write_tx_buffer(uint8_t ch)
diff --git a/libraries/dualmcu/waps/comm/uart/waps_uart_power.c b/libraries/dualmcu/waps/comm/uart/waps_uart_power.c
index 3b91fb36..4ef87ff9 100644
--- a/libraries/dualmcu/waps/comm/uart/waps_uart_power.c
+++ b/libraries/dualmcu/waps/comm/uart/waps_uart_power.c
@@ -7,8 +7,8 @@
#include
#include "waps_private.h"
-
-#include "io.h"
+#include "uart_wakeup.h"
+#include "gpio.h"
#include "ds.h"
#include "usart.h"
@@ -23,17 +23,13 @@
* \file waps_usart_power.c
* The purpose of this file is to provide an automatic power on/off
* switch for the USART transceivers RX functionality.
- * This is done by level aware interrupt.
- * A low level on the line starts the power-up procedure, and triggers
- * a high level interrupt. When the high level is present, the UART +
- * receiver are turned on.
*/
/** USART power-up procedure states */
typedef enum
{
USART_POWER_OFF, /**< Power is completely off (IDLE state) */
- USART_POWER_UP, /**< Usart is powering up (between off and on) */
+ USART_POWER_UP, /**< Usart is powering up (between off and on), not used with EFR32 */
USART_POWER_ON /**< Usart is powered up */
}usart_power_state_e;
@@ -57,7 +53,7 @@ static volatile usart_power_state_e m_power_on = USART_POWER_OFF;
/**
* \brief Callback for RX pin state change
*/
-static void uart_gpio_isr(void);
+static void uart_gpio_isr(gpio_id_t gpio_id, gpio_in_event_e gpio_event);
/**
* \brief Turn receiver power off
@@ -73,9 +69,7 @@ void Waps_uart_AutoPowerOn(void)
{
Sys_enterCriticalSection();
m_power_on = USART_POWER_OFF;
- Wakeup_pinInit(uart_gpio_isr);
- // Expecting falling edge interrupt
- Wakeup_setEdgeIRQ(EXTI_IRQ_FALLING_EDGE, true);
+ UartWakeup_enable(uart_gpio_isr);
m_autopower_enabled = true;
Sys_exitCriticalSection();
}
@@ -84,9 +78,7 @@ void Waps_uart_AutoPowerOff(void)
{
Sys_enterCriticalSection();
m_power_on = USART_POWER_OFF;
- Wakeup_setEdgeIRQ(EXTI_IRQ_FALLING_EDGE, false);
- Wakeup_clearIrq();
- Wakeup_off();
+ UartWakeup_disable();
m_autopower_enabled = false;
Sys_exitCriticalSection();
}
@@ -126,22 +118,38 @@ void Waps_uart_powerOff(void)
USART_SHUTDOWN_EXEC_TIME_US);
}
-/** This function expects three preamble bytes, will not work otherwise */
-static void uart_gpio_isr(void)
+/** This function expects few preamble bytes, will not work otherwise */
+static void uart_gpio_isr(gpio_id_t gpio_id, gpio_in_event_e gpio_event)
{
+ // No need to check GPIO ID here.
+ (void)gpio_id;
+
+#if defined(EFR32_PLATFORM)
+ // Do not care is it rising or falling edge,
+ // any activity will wake up UART.
+ (void)gpio_event;
+
if(m_power_on == USART_POWER_OFF)
+ {
+ // MCU Wake-up
+ Sys_enterCriticalSection();
+ Usart_setEnabled(true);
+ Usart_receiverOn();
+ m_power_on = USART_POWER_ON;
+ Sys_exitCriticalSection();
+ UartWakeup_disable();
+ wakeup_task();
+ }
+#elif defined(NRF52_PLATFORM) || defined(NRF91_PLATFORM)
+ if((m_power_on == USART_POWER_OFF) && (gpio_event == GPIO_IN_EVENT_FALLING_EDGE))
{
/* MCU Wake-up (falling edge)! Start edge trigger VERY quickly */
Sys_enterCriticalSection();
- /* Change sense direction and enable rising edge trigger */
- Wakeup_setEdgeIRQ(EXTI_IRQ_RISING_EDGE, true);
m_power_on = USART_POWER_UP;
Sys_exitCriticalSection();
- // Rising edge comes very fast, may not be safe to enter deep sleep
- DS_Disable(DS_SOURCE_USART_POWER);
wakeup_task();
}
- else if(m_power_on == USART_POWER_UP)
+ else if((m_power_on == USART_POWER_UP) && (gpio_event == GPIO_IN_EVENT_RISING_EDGE))
{
/* Rising edge (receiver is on!) enable receiver and disable isr */
Sys_enterCriticalSection();
@@ -150,10 +158,11 @@ static void uart_gpio_isr(void)
Usart_receiverOn();
m_power_on = USART_POWER_ON;
Sys_exitCriticalSection();
- // Uart is now awake, safe to enable deep sleep
- DS_Enable(DS_SOURCE_USART_POWER);
- Wakeup_setEdgeIRQ(EXTI_IRQ_FALLING_EDGE, false);
+ UartWakeup_disable();
}
+#else
+#error "Unknown platform"
+#endif
}
static uint32_t shutdown_uart(void)
@@ -179,14 +188,9 @@ static void power_off(void)
Usart_setEnabled(false);
Waps_uart_clean();
}
- else if(m_power_on == USART_POWER_UP)
- {
- // Uart is in powering up state, clear deep sleep disable bit
- DS_Enable(DS_SOURCE_USART_POWER);
- }
/* Power is now off */
m_power_on = USART_POWER_OFF;
- /* Change edge to falling edge and enable power-up pin */
- Wakeup_setEdgeIRQ(EXTI_IRQ_FALLING_EDGE, true);
+ /* Enable detection of UART RX rising/falling edges, so that the UART receiver can be woken */
+ UartWakeup_enable(uart_gpio_isr);
}
diff --git a/libraries/dualmcu/waps/makefile b/libraries/dualmcu/waps/makefile
index e9801be1..41de4877 100644
--- a/libraries/dualmcu/waps/makefile
+++ b/libraries/dualmcu/waps/makefile
@@ -11,8 +11,12 @@ WAPS_PREFIX := $(WP_LIB_PATH)dualmcu/waps/
# 16 -> 17 (- Add support for fragmented packet (TX and RX))
# 17 -> 18 (- add scratchpad read primitive
# - add read-only MSAP attribute 14 for stored scratchpad size)
+# 18 -> 19 (- removed initial delay from WAPS_FUNC_DSAP_DATA_TX_TT_REQ &
+# WAPS_FUNC_DSAP_DATA_TX_FRAG_REQ
+# - Removed queueing time services
+# - Removed remote update services)
-CFLAGS += -DWAPS_VERSION=18
+CFLAGS += -DWAPS_VERSION=19
INCLUDES += -I$(WAPS_PREFIX)
diff --git a/libraries/dualmcu/waps/protocol/waps_protocol.c b/libraries/dualmcu/waps/protocol/waps_protocol.c
index 8874a660..547975d0 100644
--- a/libraries/dualmcu/waps/protocol/waps_protocol.c
+++ b/libraries/dualmcu/waps/protocol/waps_protocol.c
@@ -17,6 +17,7 @@
#include "sl_list.h"
#include "api.h"
+
/** Global access to lower level via function pointers */
waps_prot_t waps_prot;
diff --git a/libraries/dualmcu/waps/sap/csap.c b/libraries/dualmcu/waps/sap/csap.c
index 36c70a55..9cf9ad49 100644
--- a/libraries/dualmcu/waps/sap/csap.c
+++ b/libraries/dualmcu/waps/sap/csap.c
@@ -506,26 +506,6 @@ static attribute_result_e writeAttr(attr_t attr_id,
if (result == APP_RES_OK)
{
Waps_uart_powerReset();
-#ifdef OTAP_FORCE_LEGACY
- bool firstboot = false;
-
- Persistent_isFirstboot(&firstboot);
-
- // Check if first boot and a sink
- if ((app_role == APP_LIB_SETTINGS_ROLE_SINK_LE ||
- app_role == APP_LIB_SETTINGS_ROLE_SINK_LL) &&
- firstboot)
- {
- if (lib_otap->setTargetScratchpadAndAction(
- 0x00,
- 0x0000,
- APP_LIB_OTAP_ACTION_LEGACY,
- 0x00) == APP_RES_OK)
- {
- Persistent_setFirstboot(false);
- }
- }
-#endif // OTAP_FORCE_LEGACY
}
}
break;
diff --git a/libraries/dualmcu/waps/sap/dsap.c b/libraries/dualmcu/waps/sap/dsap.c
index 49e514d7..7d5f8ae7 100644
--- a/libraries/dualmcu/waps/sap/dsap.c
+++ b/libraries/dualmcu/waps/sap/dsap.c
@@ -92,7 +92,6 @@ bool Dsap_handleFrame(waps_item_t * item)
.num_bytes = req->apdu_len,
.bytes = req->apdu,
.tracking_id = req->apdu_id,
- .delay = lib_time->getTimestampCoarse() - item->time, // No initial travel time
.hop_limit = get_single_mcu_hop_limit_from_dualmcu_tx_option(req->tx_opts),
};
}
@@ -118,7 +117,6 @@ bool Dsap_handleFrame(waps_item_t * item)
.num_bytes = req->apdu_len,
.bytes = req->apdu,
.tracking_id = req->apdu_id,
- .delay = lib_time->getTimestampCoarse() + req->travel_time - item->time,
.hop_limit = get_single_mcu_hop_limit_from_dualmcu_tx_option(req->tx_opts),
};
}
@@ -149,7 +147,6 @@ bool Dsap_handleFrame(waps_item_t * item)
.num_bytes = req->apdu_len,
.bytes = req->apdu,
.tracking_id = req->apdu_id,
- .delay = lib_time->getTimestampCoarse() + req->travel_time - item->time,
.hop_limit = get_single_mcu_hop_limit_from_dualmcu_tx_option(req->tx_opts),
.fragment_info = {
.fragment_offset = fragment_offset,
@@ -297,7 +294,7 @@ static void update_packet_delay(waps_item_t * item)
{
item->frame.dsap.data_rx_ind.delay += local_delay;
}
- else if (item->frame.sfunc == WAPS_FUNC_DSAP_DATA_RX_IND)
+ else if (item->frame.sfunc == WAPS_FUNC_DSAP_DATA_RX_FRAG_IND)
{
item->frame.dsap.data_rx_frag_ind.delay += local_delay;
}
diff --git a/libraries/dualmcu/waps/sap/dsap_frames.h b/libraries/dualmcu/waps/sap/dsap_frames.h
index 4736daa4..edb7a397 100644
--- a/libraries/dualmcu/waps/sap/dsap_frames.h
+++ b/libraries/dualmcu/waps/sap/dsap_frames.h
@@ -79,7 +79,7 @@ typedef struct __attribute__ ((__packed__))
ep_t dst_endpoint;
uint8_t qos;
uint8_t tx_opts;
- uint32_t travel_time;
+ uint32_t reserved;
uint8_t apdu_len;
uint8_t apdu[APDU_MAX_SIZE];
} dsap_data_tx_tt_req_t;
@@ -95,7 +95,7 @@ typedef struct __attribute__ ((__packed__))
ep_t dst_endpoint;
uint8_t qos;
uint8_t tx_opts;
- uint32_t travel_time;
+ uint32_t reserved;
uint16_t full_packet_id : 12;
// Fragment offset + flag
uint16_t fragment_offset_flag;
diff --git a/libraries/dualmcu/waps/sap/function_codes.h b/libraries/dualmcu/waps/sap/function_codes.h
index ef1f732c..acc4d857 100644
--- a/libraries/dualmcu/waps/sap/function_codes.h
+++ b/libraries/dualmcu/waps/sap/function_codes.h
@@ -70,8 +70,8 @@ typedef enum
WAPS_FUNC_MSAP_REMOTE_STATUS_IND = 0x1D,
WAPS_FUNC_MSAP_REMOTE_STATUS_RSP = 0x9D,
/* MSAP-REMOTE_UPDATE_REQ */
- WAPS_FUNC_MSAP_REMOTE_UPDATE_REQ = 0x1E,
- WAPS_FUNC_MSAP_REMOTE_UPDATE_CNF = 0x9E,
+ DEPRECATED_WAPS_FUNC_MSAP_REMOTE_UPDATE_REQ = 0x1E,
+ DEPRECATED_WAPS_FUNC_MSAP_REMOTE_UPDATE_CNF = 0x9E,
/* DSAP-DATA_TX with non-zero initial travel time */
WAPS_FUNC_DSAP_DATA_TX_TT_REQ = 0x1F,
WAPS_FUNC_DSAP_DATA_TX_TT_CNF = 0x9F,
@@ -125,11 +125,11 @@ typedef enum
WAPS_FUNC_MSAP_STACK_SLEEP_GOTOSLEEPINFO_RSP = 0xCC,
/* MSAP-MAX_QUEUE_TIME_WRITE REQ */
- WAPS_FUNC_MSAP_MAX_MSG_QUEUEING_TIME_WRITE_REQ = 0x4F,
- WAPS_FUNC_MSAP_MAX_MSG_QUEUEING_TIME_WRITE_CNF = 0xCF,
+ DEPRECATED_WAPS_FUNC_MSAP_MAX_MSG_QUEUEING_TIME_WRITE_REQ = 0x4F,
+ DEPRECATED_WAPS_FUNC_MSAP_MAX_MSG_QUEUEING_TIME_WRITE_CNF = 0xCF,
/* MSAP-MAX_QUEUE_TIME_READ REQ */
- WAPS_FUNC_MSAP_MAX_MSG_QUEUEING_TIME_READ_REQ = 0x50,
- WAPS_FUNC_MSAP_MAX_MSG_QUEUEING_TIME_READ_CNF = 0xD0,
+ DEPRECATED_WAPS_FUNC_MSAP_MAX_MSG_QUEUEING_TIME_READ_REQ = 0x50,
+ DEPRECATED_WAPS_FUNC_MSAP_MAX_MSG_QUEUEING_TIME_READ_CNF = 0xD0,
/* Reserved request ids (only present in Remote API). */
WAPS_FUNC_RESERVED_REMOTE_API_1_REQ = 0x60,
@@ -165,7 +165,6 @@ typedef enum
WAPS_FUNC_MSAP_SCRATCHPAD_BOOTABLE_REQ, \
WAPS_FUNC_MSAP_SCRATCHPAD_CLEAR_REQ, \
WAPS_FUNC_MSAP_REMOTE_STATUS_REQ, \
- WAPS_FUNC_MSAP_REMOTE_UPDATE_REQ, \
WAPS_FUNC_MSAP_GET_NBORS_REQ, \
WAPS_FUNC_MSAP_SCAN_NBORS_REQ, \
WAPS_FUNC_MSAP_GET_INSTALL_QUALITY_REQ, \
@@ -177,8 +176,6 @@ typedef enum
WAPS_FUNC_MSAP_STACK_SLEEP_STOP_REQ, \
WAPS_FUNC_MSAP_STACK_SLEEP_STATE_GET_REQ, \
WAPS_FUNC_MSAP_STACK_SLEEP_GOTOSLEEPINFO_REQ, \
- WAPS_FUNC_MSAP_MAX_MSG_QUEUEING_TIME_WRITE_REQ, \
- WAPS_FUNC_MSAP_MAX_MSG_QUEUEING_TIME_READ_REQ, \
WAPS_FUNC_MSAP_SCRATCHPAD_TARGET_READ_REQ, \
WAPS_FUNC_MSAP_SCRATCHPAD_TARGET_WRITE_REQ, \
WAPS_FUNC_MSAP_SCRATCHPAD_BLOCK_READ_REQ \
@@ -216,14 +213,11 @@ typedef enum
WAPS_FUNC_MSAP_SCRATCHPAD_BOOTABLE_CNF, \
WAPS_FUNC_MSAP_SCRATCHPAD_CLEAR_CNF, \
WAPS_FUNC_MSAP_REMOTE_STATUS_CNF, \
- WAPS_FUNC_MSAP_REMOTE_UPDATE_CNF, \
WAPS_FUNC_DSAP_DATA_TX_TT_CNF, \
WAPS_FUNC_MSAP_APP_CONFIG_WRITE_CNF, \
WAPS_FUNC_MSAP_APP_CONFIG_READ_CNF, \
WAPS_FUNC_MSAP_STACK_SLEEP_REQ_CNF, \
WAPS_FUNC_MSAP_STACK_SLEEP_STOP_CNF, \
- WAPS_FUNC_MSAP_MAX_MSG_QUEUEING_TIME_WRITE_CNF, \
- WAPS_FUNC_MSAP_MAX_MSG_QUEUEING_TIME_READ_CNF, \
WAPS_FUNC_MSAP_SCRATCHPAD_TARGET_READ_CNF, \
WAPS_FUNC_MSAP_SCRATCHPAD_TARGET_WRITE_CNF, \
WAPS_FUNC_MSAP_SCRATCHPAD_BLOCK_READ_CNF, \
diff --git a/libraries/dualmcu/waps/sap/msap.c b/libraries/dualmcu/waps/sap/msap.c
index c11b2609..55609dc7 100644
--- a/libraries/dualmcu/waps/sap/msap.c
+++ b/libraries/dualmcu/waps/sap/msap.c
@@ -78,13 +78,10 @@ static bool scratchpadReadTarget(waps_item_t * item);
static bool allowScratchpadRead(void);
static bool scratchpadReadBlock(waps_item_t * item);
static bool remoteStatus(waps_item_t * item);
-static bool remoteUpdate(waps_item_t * item);
static bool sleep_request(waps_item_t * item);
static bool sleep_stop_request(waps_item_t * item);
static bool sleep_state_request(waps_item_t * item);
static bool sleep_gotosleepinfo_request(waps_item_t * item);
-static bool max_msg_queuing_time_write_req(waps_item_t * item);
-static bool max_msg_queuing_time_read_req(waps_item_t * item);
/* Map attr id to attr length */
static const uint8_t m_attr_size_lut[] =
@@ -325,8 +322,6 @@ bool Msap_handleFrame(waps_item_t * item)
return scratchpadReadBlock(item);
case WAPS_FUNC_MSAP_REMOTE_STATUS_REQ:
return remoteStatus(item);
- case WAPS_FUNC_MSAP_REMOTE_UPDATE_REQ:
- return remoteUpdate(item);
case WAPS_FUNC_MSAP_GET_NBORS_REQ:
return getNbors(item);
case WAPS_FUNC_MSAP_SCAN_NBORS_REQ:
@@ -345,10 +340,6 @@ bool Msap_handleFrame(waps_item_t * item)
return sleep_state_request(item);
case WAPS_FUNC_MSAP_STACK_SLEEP_GOTOSLEEPINFO_REQ:
return sleep_gotosleepinfo_request(item);
- case WAPS_FUNC_MSAP_MAX_MSG_QUEUEING_TIME_WRITE_REQ:
- return max_msg_queuing_time_write_req(item);
- case WAPS_FUNC_MSAP_MAX_MSG_QUEUEING_TIME_READ_REQ:
- return max_msg_queuing_time_read_req(item);
default:
return false;
}
@@ -1527,24 +1518,6 @@ static bool remoteStatus(waps_item_t * item)
return true;
}
-static bool remoteUpdate(waps_item_t * item)
-{
- // Remote status is not implemented by stack anymore
- // Return an existing error code to keep compatibility
- msap_remote_update_e result = MSAP_REMOTE_UPDATE_ACCESS_DENIED;
-
- if (item->frame.splen != sizeof(msap_remote_update_req_t))
- {
- return false;
- }
-
- Waps_item_init(item,
- WAPS_FUNC_MSAP_REMOTE_UPDATE_CNF,
- sizeof(simple_cnf_t));
- item->frame.simple_cnf.result = result;
- return true;
-}
-
static bool sleep_request(waps_item_t * item)
{
msap_sleep_update_e result = MSAP_SLEEP_SUCCESS;
@@ -1627,46 +1600,3 @@ static bool sleep_gotosleepinfo_request(waps_item_t * item)
return true;
}
-static bool max_msg_queuing_time_write_req(waps_item_t * item)
-{
- bool status = false;
- app_res_e result = APP_RES_INVALID_VALUE;
- waps_func_e conf = WAPS_FUNC_MSAP_MAX_MSG_QUEUEING_TIME_WRITE_CNF;
-
- if (item->frame.splen == sizeof (msap_max_msg_queuing_time_req_t))
- {
- app_lib_data_qos_e prio = item->
- frame.msap.max_msg_queuing_time_req.priority;
- uint16_t time = item->frame.msap.max_msg_queuing_time_req.time;
- result = lib_data->setMaxMsgQueuingTime(prio,time);
- status = true;
- }
- Waps_item_init(item, conf, sizeof(simple_cnf_t));
- item->frame.simple_cnf.result = result;
-
- return status;
-}
-
-static bool max_msg_queuing_time_read_req(waps_item_t * item)
-{
- bool status = false;
- app_res_e result = APP_RES_INVALID_VALUE;
- waps_func_e conf = WAPS_FUNC_MSAP_MAX_MSG_QUEUEING_TIME_READ_CNF;
- uint16_t time = 0;
-
- if (item->frame.splen == sizeof(item->
- frame.msap.max_msg_queuing_time_req.priority))
- {
- app_lib_data_qos_e prio = item->
- frame.msap.max_msg_queuing_time_req.priority;
-
- result = lib_data->getMaxMsgQueuingTime(prio,&time);
- status = true;
- }
- Waps_item_init(item, conf, sizeof(msap_max_msg_queuing_time_read_cnf_t));
- item->frame.msap.max_msg_queuing_time_read_cnf.time = time;
- item->frame.msap.max_msg_queuing_time_read_cnf.result = result;
- item->frame.splen = sizeof(item->frame.msap.max_msg_queuing_time_read_cnf);
-
- return status;
-}
diff --git a/libraries/dualmcu/waps/sap/msap_frames.h b/libraries/dualmcu/waps/sap/msap_frames.h
index b8d7a798..6c26cffb 100644
--- a/libraries/dualmcu/waps/sap/msap_frames.h
+++ b/libraries/dualmcu/waps/sap/msap_frames.h
@@ -349,26 +349,6 @@ typedef struct __attribute__ ((__packed__))
uint8_t scan_ready;
} msap_on_scanned_nbors_ind_t;
-/** MSAP-SCRATCHPAD_REMOTE_UPDATE request frame */
-typedef struct __attribute__ ((__packed__))
-{
- /** Unicast or broadcast targeting */
- w_addr_t target;
- /** Target scratchpad sequence to update */
- otap_seq_t seq;
- /** Reboot delay in seconds */
- uint16_t reboot_delay;
-} msap_remote_update_req_t;
-
-/** Result of MSAP-REMOTE_UPDATE request
- NB: ONLY one return code possible as feature is not
- implemented anymore and must be used through Remote API
-*/
-typedef enum
-{
- MSAP_REMOTE_UPDATE_ACCESS_DENIED = 6,
-} msap_remote_update_e;
-
/** MSAP-GET_NBORS */
typedef struct __attribute__ ((__packed__))
{
@@ -414,24 +394,6 @@ typedef struct __attribute__ ((__packed__))
} msap_sleep_latest_gotosleep_rsp_t;
-/** Maximum message queuing time request frame */
-typedef struct __attribute__ ((__packed__))
-{
- /** Message priority which queuing time to be set/get */
- app_lib_data_qos_e priority;
- /** Maximum queuing time to be set in seconds */
- uint16_t time;
-} msap_max_msg_queuing_time_req_t;
-
-/** Confirmation to maximum message queuing read request */
-typedef struct __attribute__ ((__packed__))
-{
- /** Read result */
- app_res_e result;
- /** Read value of maximum queuing time */
- uint16_t time;
-} msap_max_msg_queuing_time_read_cnf_t;
-
/** MSAP-GET_INSTALL_QUALITY */
typedef struct
{
@@ -555,13 +517,10 @@ typedef union
msap_scratchpad_status_cnf_t scratchpad_status_cnf;
msap_remote_status_req_t remote_status_req;
msap_remote_status_ind_t remote_status_ind;
- msap_remote_update_req_t remote_update_req;
msap_on_scanned_nbors_ind_t on_scanned_nbors;
msap_sleep_start_req_t sleep_start_req;
msap_sleep_state_rsp_t sleep_state_rsp;
msap_sleep_latest_gotosleep_rsp_t sleep_gotosleep_rsp_t;
- msap_max_msg_queuing_time_req_t max_msg_queuing_time_req;
- msap_max_msg_queuing_time_read_cnf_t max_msg_queuing_time_read_cnf;
msap_install_quality_cnf_t inst_qual_cnf;
msap_scratchpad_target_write_req_t scratchpad_target_write_req;
msap_scratchpad_target_read_cnf_t scratchpad_target_read_cnf;
diff --git a/libraries/dualmcu/waps/waps.c b/libraries/dualmcu/waps/waps.c
index d6919f3a..be900e74 100644
--- a/libraries/dualmcu/waps/waps.c
+++ b/libraries/dualmcu/waps/waps.c
@@ -17,6 +17,7 @@
#include "sap/function_codes.h"
#include "waps.h"
#include "waps_private.h"
+#include "protocol/waps_protocol_private.h" // To access prot_indication
#include "sap/persistent.h"
@@ -60,6 +61,12 @@
*/
#define WAPS_TASK_EXEC_TIME_FOR_REMOVE_DS_PREV_US 500
+/** Maximum time in ms to perform a gargbage collect on indication queued.
+ * Every period, the queued indication will be compared to the max
+ * TTL set in the node to removed if too old
+ */
+#define WAPS_GARBAGE_COLLECT_PERIOD_MS 5000
+
/**
* \brief Waps_exec is the core of WAPS
* Waps_exec must be allocated as much run time as possible to
@@ -112,6 +119,11 @@ static bool process_request(waps_item_t * item);
*/
static waps_item_t * find_indication(uint8_t id);
+/**
+ * \brief Delete indication that exceeded their max TTL
+ */
+static uint32_t garbage_collect_old_indication_task(void);
+
/** WAPS internal message queues */
sl_list_head_t waps_ind_queue;
sl_list_head_t waps_reply_queue;
@@ -231,6 +243,9 @@ bool Waps_init(uint32_t baudrate, bool flow_ctrl)
add_indication(Msap_getStackStatusIndication());
// Clear the signal here (can be set after Waps_prot_init())
m_signal = 0;
+
+ // Start a task to remove old indication (according to TTL)
+ App_Scheduler_addTask_execTime(garbage_collect_old_indication_task, WAPS_GARBAGE_COLLECT_PERIOD_MS, 100);
return true;
}
@@ -254,7 +269,8 @@ uint32_t Waps_exec(void)
// Request queued for too long time must not be executed
// In reality, it will only happen when a scratchpad is exchanged and app
// is not scheduled anymore for very long period > 10s
- if (lib_time->getTimestampCoarse() - item->time > WAPS_MAX_REQUEST_QUEUING_TIME_COARSE)
+ if (lib_time->getTimestampCoarse() - item->time >
+ WAPS_MAX_REQUEST_QUEUING_TIME_COARSE)
{
// Nothing to do except freeing memory, done just later
}
@@ -480,3 +496,89 @@ static waps_item_t * find_indication(uint8_t id)
}
return item;
}
+
+static bool is_indication_too_old(waps_item_t * item, uint16_t qos_qt_s[2])
+{
+ uint8_t qos;
+ uint32_t qt, travel_time;
+ uint32_t now = lib_time->getTimestampCoarse();
+
+ // Data RX Ind and DATA RX Frag Ind are handled independently
+ // even if struct are alligned, but more futur proof
+ if (item->frame.sfunc == WAPS_FUNC_DSAP_DATA_RX_IND)
+ {
+ qos = item->frame.dsap.data_rx_ind.info & RX_IND_INFO_QOS_MASK;
+ travel_time = item->frame.dsap.data_rx_ind.delay;
+ }
+ else if (item->frame.sfunc == WAPS_FUNC_DSAP_DATA_RX_FRAG_IND)
+ {
+ qos = item->frame.dsap.data_rx_frag_ind.info & RX_IND_INFO_QOS_MASK;
+ travel_time = item->frame.dsap.data_rx_frag_ind.delay;
+ }
+ else
+ {
+ return false;
+ }
+
+ // Queued time on dualmcu side
+ qt = now - item->time;
+
+ // Check travel_time + queued_time vs limit set
+ if (((travel_time + qt) / 128) > qos_qt_s[qos])
+ {
+ // Too long in transit, delete it
+ return true;
+ }
+
+ return false;
+}
+
+static uint32_t garbage_collect_old_indication_task(void)
+{
+ waps_item_t * item;
+
+ // Add a default value, in case it is not possible to read from stack (Not really possible)
+ uint16_t qos_qt_s[2] = {10 * 60, 5 * 60};
+
+ if (!queued_indications() && (prot_indication == NULL))
+ {
+ // Nothing to be done
+ // Return time could be optimize to min qos time.
+ // If no indication at the moment, next potential clean up will be in min quing time set
+ // but let's keep things simpler
+ return WAPS_GARBAGE_COLLECT_PERIOD_MS;
+ }
+
+ // Check the next indication that is already out of the queue
+ if (prot_indication != NULL)
+ {
+ if (is_indication_too_old(prot_indication, qos_qt_s))
+ {
+ Waps_itemFree(prot_indication);
+ prot_indication = NULL;
+ }
+ }
+
+ // Check all items from the queue one by one
+ item = (waps_item_t *) sl_list_begin(&waps_ind_queue);
+ while (item != NULL)
+ {
+ // Get next immediatelly in case we remove the item
+ waps_item_t * next = (waps_item_t *) sl_list_next((sl_list_t *) item);
+ if (is_indication_too_old(item, qos_qt_s))
+ {
+ // Unfortunately, there is no api in sl_list to remove without
+ // going through the list again, we could play with pointer here, but not
+ // good pattern to access internal sl_list struct.
+ // Anyway, list should never be very long
+ sl_list_remove(&waps_ind_queue, (sl_list_t *) item);
+ // Put back the item to free list and potentially re-enable the RX from stack
+ Waps_itemFree(item);
+ }
+
+ // move to next one
+ item = next;
+ }
+
+ return WAPS_GARBAGE_COLLECT_PERIOD_MS;
+}
diff --git a/libraries/libraries_init.c b/libraries/libraries_init.c
index 094d8d85..357b3ef9 100644
--- a/libraries/libraries_init.c
+++ b/libraries/libraries_init.c
@@ -41,6 +41,10 @@
#include "shared_offline.h"
#endif
+#if __has_include("rtc.h")
+#include "rtc.h"
+#endif
+
void Libraries_init(void)
{
#if __has_include("app_scheduler.h")
@@ -75,4 +79,8 @@ void Libraries_init(void)
Shared_Offline_init();
#endif
+#if __has_include("rtc.h")
+ RTC_init();
+#endif
+
}
diff --git a/libraries/local_provisioning/local_provisioning.c b/libraries/local_provisioning/local_provisioning.c
index 20c6d9a9..3780497a 100644
--- a/libraries/local_provisioning/local_provisioning.c
+++ b/libraries/local_provisioning/local_provisioning.c
@@ -292,7 +292,7 @@ static void enable_proxy(void)
// add filter for proxy asynchronously in case we are not started yet
// In fact if a sink, adding filter may trigger immediately cb and enabling
// joining beacon will work only after stack is really started (app_init has returned)
- App_Scheduler_addTask_execTime(add_filter_for_proxy, APP_SCHEDULER_SCHEDULE_ASAP, 50);
+ App_Scheduler_addTask_execTime(add_filter_for_proxy, APP_SCHEDULER_SCHEDULE_ASAP, 60);
}
/**
diff --git a/libraries/makefile b/libraries/makefile
index 715a5622..f4274a58 100644
--- a/libraries/makefile
+++ b/libraries/makefile
@@ -1,4 +1,10 @@
+ifeq ($(RTC), yes)
+SRCS += $(WP_LIB_PATH)rtc/rtc.c
+INCLUDES += -I$(WP_LIB_PATH)rtc
+CFLAGS += -DRTC_MAX_CB=$(RTC_CBS)
+endif
+
ifeq ($(SHARED_DATA), yes)
SRCS += $(WP_LIB_PATH)shared_data/shared_data.c
INCLUDES += -I$(WP_LIB_PATH)shared_data
@@ -7,7 +13,7 @@ endif
ifeq ($(SHARED_APP_CONFIG), yes)
SRCS += $(WP_LIB_PATH)shared_appconfig/shared_appconfig.c
INCLUDES += -I$(WP_LIB_PATH)shared_appconfig
-INCLUDES += -DSHARED_APP_CONFIG_MAX_FILTER=$(shell expr $(app_config_filters))
+CFLAGS += -DSHARED_APP_CONFIG_MAX_FILTER=$(shell expr $(app_config_filters))
endif
ifeq ($(LOCAL_PROVISIONING), yes)
@@ -40,7 +46,7 @@ endif
ifeq ($(SHARED_NEIGHBORS), yes)
SRCS += $(WP_LIB_PATH)shared_neighbors/shared_neighbors.c
INCLUDES += -I$(WP_LIB_PATH)shared_neighbors
-INCLUDES += -DSHARED_NEIGHBORS_MAX_CB=$(shell expr $(shared_neighbors_cbs))
+CFLAGS += -DSHARED_NEIGHBORS_MAX_CB=$(shell expr $(shared_neighbors_cbs))
endif
ifeq ($(SHARED_BEACON), yes)
@@ -70,20 +76,20 @@ endif
ifeq ($(SHARED_OFFLINE), yes)
SRCS += $(WP_LIB_PATH)shared_offline/shared_offline.c
INCLUDES += -I$(WP_LIB_PATH)shared_offline
-INCLUDES += -DSHARED_OFFLINE_MAX_MODULES=$(shell expr $(shared_offline_modules))
+CFLAGS += -DSHARED_OFFLINE_MAX_MODULES=$(shell expr $(shared_offline_modules))
endif
ifeq ($(STACK_STATE_LIB), yes)
SRCS += $(WP_LIB_PATH)stack_state/stack_state.c
INCLUDES += -I$(WP_LIB_PATH)stack_state
-INCLUDES += -DSTACK_STATE_CB=$(shell expr $(stack_state_cbs))
+CFLAGS += -DSTACK_STATE_CB=$(shell expr $(stack_state_cbs))
endif
ifeq ($(APP_SCHEDULER), yes)
SRCS += $(WP_LIB_PATH)scheduler/app_scheduler.c
INCLUDES += -I$(WP_LIB_PATH)scheduler
# Set number of Library tasks
-INCLUDES += -DAPP_SCHEDULER_ALL_TASKS=$(shell expr $(scheduler_tasks))
+CFLAGS += -DAPP_SCHEDULER_ALL_TASKS=$(shell expr $(scheduler_tasks))
endif
ifeq ($(DUALMCU_LIB), yes)
diff --git a/libraries/positioning/poslib/poslib_control.c b/libraries/positioning/poslib/poslib_control.c
index aa107083..f111e29d 100644
--- a/libraries/positioning/poslib/poslib_control.c
+++ b/libraries/positioning/poslib/poslib_control.c
@@ -92,7 +92,7 @@ static callback_state_t m_legacy_appcfg = {.reg = false, .id = SHARED_INVALID_ID
/** Buffer for appconfig */
-static uint8_t m_appcfg[APP_LIB_DATA_MAX_APP_CONFIG_NUM_BYTES];
+static uint8_t m_appcfg[APP_LIB_DATA_MAX_APP_CONFIG_NUM_BYTES];
static uint8_t m_appcfg_len = 0;
/** Control state variables */
@@ -102,7 +102,7 @@ static bool m_poslib_init = false;
static control_state_t m_ctrl;
/** Events private data */
-//ToDo: generalize event private data later
+//ToDo: generalize event private data later
static bool m_data_sent_success = false;
static poslib_internal_event_type_e m_timeout_event_type = POSLIB_CTRL_EVENT_NONE;
@@ -139,7 +139,7 @@ static void on_offline_cb(uint32_t delay_s)
*/
static void on_online_cb(uint32_t delay_from_deadline_s)
{
- LOG(LVL_DEBUG, "Online");
+ LOG(LVL_DEBUG, "Online");
PosLibEvent_add(POSLIB_CTRL_EVENT_ONLINE);
}
@@ -190,7 +190,7 @@ static void process_led_status(poslib_aux_settings_t * aux)
}
static void process_appcfg()
-{
+{
poslib_settings_t settings = m_pos_settings;
poslib_aux_settings_t aux = m_aux_settings;
@@ -226,7 +226,7 @@ static void appconfig_cb(uint16_t types, uint8_t length, uint8_t * bytes)
{
memcpy(&m_appcfg[0], bytes, length);
m_appcfg_len = length;
- PosLibEvent_add(POSLIB_CTRL_EVENT_APPCFG);
+ PosLibEvent_add(POSLIB_CTRL_EVENT_APPCFG);
}
else
{
@@ -239,8 +239,8 @@ static void appconfig_legacy_cb(uint16_t types, uint8_t length, uint8_t * bytes)
if (types == SHARED_APP_CONFIG_INCOMPATIBLE_FILTER)
{
/*Legacy AppCfg is not supported. We just need to inform that app cfg was received*/
- m_appcfg_len = 0;
- PosLibEvent_add(POSLIB_CTRL_EVENT_APPCFG);
+ m_appcfg_len = 0;
+ PosLibEvent_add(POSLIB_CTRL_EVENT_APPCFG);
}
else
{
@@ -363,16 +363,16 @@ static poslib_ret_e check_params(poslib_settings_t * settings)
return POS_RET_INVALID_PARAM;
}
- if (settings->update_period_dynamic_s > POSLIB_MAX_MEAS_RATE_S ||
- (settings->update_period_dynamic_s < POSLIB_MIN_MEAS_RATE_S &&
+ if (settings->update_period_dynamic_s > POSLIB_MAX_MEAS_RATE_S ||
+ (settings->update_period_dynamic_s < POSLIB_MIN_MEAS_RATE_S &&
settings->update_period_dynamic_s != 0))
{
LOG(LVL_ERROR, "Outside range dynamic period: %d", settings->update_period_static_s);
return POS_RET_INVALID_PARAM;
}
- if (settings->update_period_offline_s > POSLIB_MAX_MEAS_RATE_S ||
- (settings->update_period_offline_s < POSLIB_MIN_MEAS_RATE_S &&
+ if (settings->update_period_offline_s > POSLIB_MAX_MEAS_RATE_S ||
+ (settings->update_period_offline_s < POSLIB_MIN_MEAS_RATE_S &&
settings->update_period_offline_s != 0))
{
LOG(LVL_ERROR, "Outside range offline period: %d", settings->update_period_static_s);
@@ -409,7 +409,7 @@ static poslib_ret_e check_role(poslib_settings_t * settings)
if (!valid)
{
LOG(LVL_ERROR, "Anchor mode: %u but role: %u", poslib_mode, role);
- return POS_RET_INVALID_PARAM;
+ return POS_RET_INVALID_PARAM;
}
break;
}
@@ -467,7 +467,7 @@ static poslib_ret_e check_ble_params(poslib_settings_t * settings)
{
if (settings->ble.eddystone.tx_interval_ms >
APP_LIB_BEACON_TX_MAX_INTERVAL ||
- settings->ble.eddystone.tx_interval_ms <
+ settings->ble.eddystone.tx_interval_ms <
APP_LIB_BEACON_TX_MIN_INTERVAL ||
settings->ble.eddystone.channels >
APP_LIB_BEACON_TX_CHANNELS_ALL)
@@ -479,9 +479,9 @@ static poslib_ret_e check_ble_params(poslib_settings_t * settings)
if (ble_type == POSLIB_IBEACON || ble_type == POSLIB_BEACON_ALL)
{
- if (settings-> ble.ibeacon.tx_interval_ms >
+ if (settings-> ble.ibeacon.tx_interval_ms >
APP_LIB_BEACON_TX_MAX_INTERVAL ||
- settings-> ble.ibeacon.tx_interval_ms <
+ settings-> ble.ibeacon.tx_interval_ms <
APP_LIB_BEACON_TX_MIN_INTERVAL ||
settings->ble.ibeacon.channels >
APP_LIB_BEACON_TX_CHANNELS_ALL)
@@ -533,11 +533,11 @@ static bool shared_offline_register()
if (!m_shared_offline.reg)
{
-
+
uint8_t id; //FixME: all Shared libraries should use uint8_t, remove when change made
res = Shared_Offline_register(&id, m_shared_offline_cbs);
m_shared_offline.id = id;
-
+
if (res == SHARED_OFFLINE_RES_OK)
{
m_shared_offline.reg = true;
@@ -573,7 +573,7 @@ static bool shared_offline_unregister()
}
else
{
- LOG(LVL_ERROR, "Cannot unregister shared offline "); //FixMe:
+ LOG(LVL_ERROR, "Cannot unregister shared offline "); //FixMe:
}
}
@@ -591,7 +591,7 @@ static app_lib_state_route_state_e get_route_state(void)
#endif
static void control_init(void)
-{
+{
if (!m_poslib_init)
{
//m_ctrl init
@@ -615,13 +615,13 @@ poslib_ret_e PosLibCtrl_setConfig(poslib_settings_t * settings)
return ret;
}
- if (!m_poslib_configured ||
+ if (!m_poslib_configured ||
memcmp(&m_pos_settings , settings, sizeof(m_pos_settings)) != 0)
{
memcpy(&m_pos_settings , settings, sizeof(m_pos_settings));
config_change = true;
}
-
+
m_poslib_configured = true;
/* If started notify configuration change */
@@ -664,7 +664,7 @@ poslib_ret_e PosLibCtrl_startPeriodic(void)
m_ctrl.state = POSLIB_STATE_IDLE;
m_poslib_started = true;
App_Scheduler_addTask_execTime(delayed_start, 5000, 500); //FixME: this is needed to prevent a race condition in NRLS
-
+
PosLibBle_start(&m_pos_settings.ble);
if (m_pos_settings.node_mode == POSLIB_MODE_AUTOSCAN_ANCHOR ||
@@ -685,10 +685,10 @@ poslib_ret_e PosLibCtrl_startOneshot(void)
{
LOG(LVL_ERROR, "Start oneshot requested but PosLib not configured");
return POS_RET_NOT_CONFIGURED;
- }
+ }
control_init();
-
+
if (!register_callbacks())
{
LOG(LVL_ERROR, "Cannot register all required callbacks");
@@ -732,13 +732,13 @@ poslib_ret_e PosLibCtrl_motion(poslib_motion_mode_e mode)
{
return POS_RET_MOTION_NOT_ENABLED;
}
-
+
if(m_motion_mode != mode)
{
m_motion_mode = mode;
PosLibEvent_add(POSLIB_CTRL_EVENT_MOTION);
}
-
+
return POS_RET_OK;
}
@@ -781,13 +781,13 @@ poslib_measurements_e get_meas_type()
}
case POSLIB_MODE_AUTOSCAN_ANCHOR:
case POSLIB_MODE_OPPORTUNISTIC_ANCHOR:
- {
+ {
meas_type = DEFAULT_MEASUREMENT_TYPE_ANCHOR;
break;
}
default:
{
- LOG(LVL_WARNING, "Node mode %u unknown. Default to tag meas. type",
+ LOG(LVL_WARNING, "Node mode %u unknown. Default to tag meas. type",
m_pos_settings.node_mode);
meas_type = DEFAULT_MEASUREMENT_TYPE_TAG;
break;
@@ -804,7 +804,7 @@ static void get_node_info(poslib_meas_record_node_info_t * node_info)
node_info->node_mode = m_pos_settings.node_mode;
node_info->update_s = get_update_period();
- features = POSLIB_NODE_INFO_FEATURES_VERSION & POSLIB_NODE_INFO_MASK_VERSION;
+ features = POSLIB_NODE_INFO_FEATURES_VERSION & POSLIB_NODE_INFO_MASK_VERSION;
if (m_pos_settings.motion.enabled)
{
features |= POSLIB_NODE_INFO_FLAG_MOTION_EN;
@@ -823,16 +823,16 @@ static void get_node_info(poslib_meas_record_node_info_t * node_info)
}
if(m_pos_settings.da.routing_enabled)
{
- features |= POSLIB_NODE_INFO_FLAG_MBCN_ON;
+ features |= POSLIB_NODE_INFO_FLAG_MBCN_ON;
}
node_info->features = features;
- LOG(LVL_DEBUG, "Node info feature: %x en: %u", node_info->features, m_pos_settings.motion.enabled);
+ LOG(LVL_DEBUG, "Node info feature: %x en: %u", node_info->features, m_pos_settings.motion.enabled);
}
static uint8_t send_measurement_message()
-{
+{
#define MAX_PAYLOAD_LEN 102
size_t available_buffers;
@@ -862,7 +862,7 @@ static uint8_t send_measurement_message()
get_node_info(&node_info);
if (PosLibMeas_getPayload(bytes, sizeof(bytes), m_ctrl.sequence,
- get_meas_type(), add_voltage, &node_info,
+ get_meas_type(), add_voltage, &node_info,
&num_bytes, &num_meas))
{
/** add payload to be sent */
@@ -872,15 +872,14 @@ static uint8_t send_measurement_message()
payload.src_endpoint = POS_SOURCE_ENDPOINT;;
payload.dest_endpoint = POS_DESTINATION_ENDPOINT;
payload.qos = APP_LIB_DATA_QOS_NORMAL;
- payload.delay = 0;
payload.flags = APP_LIB_DATA_SEND_FLAG_TRACK;
payload.tracking_id = 0;
lib_settings->getNodeRole(&role);
- rc = (role == APP_LIB_SETTINGS_ROLE_ADVERTISER) ?
+ rc = (role == APP_LIB_SETTINGS_ROLE_ADVERTISER) ?
PosLibDa_sendData(&payload, data_send_cb) :
Shared_Data_sendData(&payload, data_send_cb);
-
+
if (rc == APP_LIB_DATA_SEND_RES_SUCCESS)
{
m_ctrl.events.data_sent = true;
@@ -899,8 +898,8 @@ static uint8_t send_measurement_message()
static uint32_t get_scan_duration()
{
uint32_t scan_duration_ms = 0;
-
- if (m_pos_settings.mbcn.enabled &&
+
+ if (m_pos_settings.mbcn.enabled &&
m_pos_settings.mbcn.tx_interval_ms < 1000)
{
scan_duration_ms = m_pos_settings.mbcn.tx_interval_ms;
@@ -918,15 +917,15 @@ static uint32_t trigger_update_task()
shared_offline_register(); //FixMe: handle registration
//Stack offline - wakeup stack
- if (Shared_Offline_get_status(&elapsed_s, &remaining_s) ==
+ if (Shared_Offline_get_status(&elapsed_s, &remaining_s) ==
SHARED_OFFLINE_STATUS_OFFLINE)
{
res = Shared_Offline_enter_online_state(m_shared_offline.id);
if ( res == SHARED_OFFLINE_RES_OK)
{
LOG(LVL_DEBUG, "Update triggered: stack wakeup");
- return APP_SCHEDULER_SCHEDULE_ASAP;
- }
+ return APP_SCHEDULER_SCHEDULE_ASAP;
+ }
else if (res == SHARED_OFFLINE_RES_ALREADY_ONLINE)
{
LOG(LVL_WARNING, "Update triggered: stack is online");
@@ -969,7 +968,7 @@ static void set_timeout(poslib_internal_event_type_e type, uint32_t timeout_ms)
static void clear_timeout(void)
{
- App_Scheduler_cancelTask(timeout_task);
+ App_Scheduler_cancelTask(timeout_task);
}
static void stop_tasks(void)
@@ -989,7 +988,7 @@ static bool update_autoscan(uint32_t delta_s)
LOG(LVL_ERROR, "Cannot add trigger_update task");
return false;
}
-
+
LOG(LVL_INFO, "Update scheduled in: %u sec", delta_s);
return true;
}
@@ -1011,15 +1010,15 @@ static bool update_nrls(uint32_t delta_s)
LOG(LVL_ERROR, "Failed to enter offline. res: %u:", res);
return false;
}
-
+
LOG(LVL_INFO, "Enter offline for %u sec stack %u", delta_s, lib_state->getStackState());
return true;
}
static uint32_t get_update_period()
{
-
- if (m_ctrl.outside_wm &&
+
+ if (m_ctrl.outside_wm &&
m_pos_settings.update_period_offline_s != 0)
{
return m_pos_settings.update_period_offline_s;
@@ -1031,7 +1030,7 @@ static uint32_t get_update_period()
{
return m_pos_settings.update_period_dynamic_s;
}
-
+
return m_pos_settings.update_period_static_s;
}
@@ -1039,7 +1038,7 @@ static void schedule_next(bool update_now)
{
uint32_t now_s = lib_time->getTimestampS();
uint32_t next_update_s = 0;
- uint32_t delta_s = 0;
+ uint32_t delta_s = 0;
uint32_t update_period_s = get_update_period();
bool scheduled = m_ctrl.scheduled;
@@ -1053,25 +1052,25 @@ static void schedule_next(bool update_now)
/* Determine the next update time */
if (update_now) // schedule imediatelly
{
- next_update_s = now_s;
+ next_update_s = now_s;
}
- else
+ else
{
delta_s = (now_s - m_ctrl.last_update_s) % update_period_s;
next_update_s = now_s + update_period_s - delta_s;
/* Keep the previous update time if already scheduled and is earlier */
- if (scheduled && (next_update_s > m_ctrl.next_update_s))
+ if (scheduled && (next_update_s > m_ctrl.next_update_s))
{
return;
}
}
- delta_s = next_update_s - now_s;
+ delta_s = next_update_s - now_s;
- if (scheduled)
+ if (scheduled)
{
- /* re-schedule if new update time; note that if in NRLS mode a
+ /* re-schedule if new update time; note that if in NRLS mode a
wakeup will be triggered */
if (next_update_s != m_ctrl.next_update_s)
{
@@ -1089,7 +1088,7 @@ static void schedule_next(bool update_now)
memset(&m_ctrl.events, 0, sizeof(control_events_t));
m_ctrl.next_update_s = next_update_s;
- m_ctrl.events.is_static = (m_motion_mode == POSLIB_MOTION_STATIC)
+ m_ctrl.events.is_static = (m_motion_mode == POSLIB_MOTION_STATIC)
&& m_pos_settings.motion.enabled;
switch (m_ctrl.mode)
@@ -1109,7 +1108,7 @@ static void schedule_next(bool update_now)
m_ctrl.sequence, MS_TIME_FROM(m_ctrl.update_start_hp));
PosLibMeas_opportunisticScan(false);
update_autoscan(delta_s); //FixMe: handle return
- break;
+ break;
}
case POSLIB_MODE_OPPORTUNISTIC_ANCHOR:
@@ -1125,7 +1124,7 @@ static void schedule_next(bool update_now)
}
}
- LOG(LVL_DEBUG," Schedule: last: %u next: %u now: %u delta: %u update: %u",
+ LOG(LVL_DEBUG," Schedule: last: %u next: %u now: %u delta: %u update: %u",
m_ctrl.last_update_s,
m_ctrl.next_update_s,
now_s,
@@ -1136,7 +1135,7 @@ static void schedule_next(bool update_now)
static void handle_stopped_state(poslib_internal_event_t * event)
{
if (!m_poslib_started && m_poslib_configured && event->type == POSLIB_CTRL_EVENT_ONESHOT)
- {
+ {
m_ctrl.events.oneshot = true;
schedule_next(true);
}
@@ -1149,14 +1148,14 @@ static void handle_idle_state(poslib_internal_event_t * event)
case POSLIB_CTRL_EVENT_SCAN_STARTED:
{
LOG(LVL_DEBUG, "Update started - scan");
- m_ctrl.update_start_hp = lib_time->getTimestampHp();
+ m_ctrl.update_start_hp = lib_time->getTimestampHp();
m_ctrl.state = POSLIB_STATE_UPDATE;
m_ctrl.events.scan_start = true;
set_timeout(POSLIB_CTRL_EVENT_SCAN_END, TIMEOUT_SCAN_MS);
break;
}
-
- case POSLIB_CTRL_EVENT_SCAN_END:
+
+ case POSLIB_CTRL_EVENT_SCAN_END:
{
if (m_ctrl.scheduled) //for opportunistic scan
{
@@ -1168,7 +1167,7 @@ static void handle_idle_state(poslib_internal_event_t * event)
else
{
LOG(LVL_ERROR, "Scan end received but no update scheduled");
- //FixMe: handle error
+ //FixMe: handle error
}
break;
}
@@ -1176,7 +1175,7 @@ static void handle_idle_state(poslib_internal_event_t * event)
case POSLIB_CTRL_EVENT_ONLINE:
{
LOG(LVL_DEBUG, " Update started - online");
- m_ctrl.update_start_hp = lib_time->getTimestampHp();
+ m_ctrl.update_start_hp = lib_time->getTimestampHp();
m_ctrl.state = POSLIB_STATE_UPDATE;
m_ctrl.events.online = true;
set_timeout(POSLIB_CTRL_EVENT_SCAN_END, TIMEOUT_SCAN_MS);
@@ -1191,7 +1190,7 @@ static void handle_idle_state(poslib_internal_event_t * event)
PosLibMeas_clearMeas();
}
LOG(LVL_DEBUG, " Update ended - online. seq: %u, time: %u",
- m_ctrl.sequence,
+ m_ctrl.sequence,
MS_TIME_FROM(m_ctrl.update_start_hp));
break;
}
@@ -1213,7 +1212,7 @@ static void handle_idle_state(poslib_internal_event_t * event)
{
LOG(LVL_ERROR, "Timeout occured in idle state: %u", lib_state->getStackState());
//FixMe: add recovery
- break;
+ break;
}
case POSLIB_CTRL_EVENT_ONESHOT:
{
@@ -1253,7 +1252,7 @@ static bool is_update_completed()
{
bool ret = m_ctrl.events.data_sent;
- /* Complete if: scan failed | timeout occured */
+ /* Complete if: scan failed | timeout occured */
if (m_ctrl.events.scan_fail || m_ctrl.events.timeout)
{
LOG(LVL_DEBUG, " Update completed: scan fail: %u,timeout: %u",
@@ -1264,7 +1263,7 @@ static bool is_update_completed()
if (m_ctrl.mode == POSLIB_MODE_NRLS_TAG)
{
/* In NRLS mode we wait for AppCfg and send complete */
- ret = ret && m_ctrl.events.app_cfg && m_ctrl.events.data_sent_complete;
+ ret = ret && m_ctrl.events.app_cfg && m_ctrl.events.data_sent_complete;
}
return ret;
}
@@ -1281,7 +1280,7 @@ static void update_outside_wm()
}
else if (bcn > 0 && m_ctrl.outside_wm)
{
- PosLibEvent_add(POSLIB_CTRL_EVENT_UNDER_WM);
+ PosLibEvent_add(POSLIB_CTRL_EVENT_UNDER_WM);
m_ctrl.outside_wm = false;
}
}
@@ -1295,12 +1294,12 @@ static void handle_update_state(poslib_internal_event_t * event)
{
switch (event->type)
{
- case POSLIB_CTRL_EVENT_SCAN_END:
+ case POSLIB_CTRL_EVENT_SCAN_END:
{
m_ctrl.events.scan_end = true;
clear_timeout();
update_outside_wm();
- LOG(LVL_INFO," Scan end. time: %u bcn: %u",
+ LOG(LVL_INFO," Scan end. time: %u bcn: %u",
MS_TIME_FROM(m_ctrl.update_start_hp), PosLibMeas_getBeaconNum());
if (is_scan_valid())
@@ -1329,8 +1328,8 @@ static void handle_update_state(poslib_internal_event_t * event)
{
m_ctrl.events.data_sent_complete = true;
m_ctrl.events.sent_success = m_data_sent_success;
- LOG(LVL_INFO," Measurement sent. success: %u time: %u ",
- m_ctrl.events.sent_success, MS_TIME_FROM(m_ctrl.update_start_hp));
+ LOG(LVL_INFO," Measurement sent. success: %u time: %u ",
+ m_ctrl.events.sent_success, MS_TIME_FROM(m_ctrl.update_start_hp));
break;
}
@@ -1349,7 +1348,7 @@ static void handle_update_state(poslib_internal_event_t * event)
app_lib_state_route_state_e route_state = get_route_state();
(void)route_state;
- LOG(LVL_INFO," Route change. state: %u time: %u", m_ctrl.events.sent_success,
+ LOG(LVL_INFO," Route change. state: %u time: %u", m_ctrl.events.sent_success,
MS_TIME_FROM(m_ctrl.update_start_hp));
@@ -1365,10 +1364,10 @@ static void handle_update_state(poslib_internal_event_t * event)
case POSLIB_CTRL_EVENT_TIMEOUT:
{
- LOG(LVL_ERROR, " Timeout occured - event: %u state %u time_ %u", m_timeout_event_type,
+ LOG(LVL_ERROR, " Timeout occured - event: %u state %u time_ %u", m_timeout_event_type,
lib_state->getStackState(), MS_TIME_FROM(m_ctrl.update_start_hp));
m_ctrl.events.timeout = true;
- break;
+ break;
}
default:
@@ -1380,7 +1379,7 @@ static void handle_update_state(poslib_internal_event_t * event)
if (is_update_completed())
{
- m_ctrl.scheduled = false;
+ m_ctrl.scheduled = false;
m_ctrl.last_update_s = m_ctrl.next_update_s;
PosLibEvent_add(POSLIB_CTRL_EVENT_UPDATE_END);
schedule_next(false);
@@ -1389,7 +1388,7 @@ static void handle_update_state(poslib_internal_event_t * event)
void PosLibCtrl_processEvent(poslib_internal_event_t * event)
{
-
+
if (m_ctrl.state == POSLIB_STATE_STOPPED)
{
handle_stopped_state(event);
@@ -1400,7 +1399,7 @@ static void handle_update_state(poslib_internal_event_t * event)
}
else if (m_ctrl.state == POSLIB_STATE_UPDATE)
{
- handle_update_state(event);
+ handle_update_state(event);
}
else
{
@@ -1416,11 +1415,11 @@ static void handle_update_state(poslib_internal_event_t * event)
void PosLibCtrl_setAppConfig(const uint8_t * cfg, uint8_t len)
{
-
+
if (len <= sizeof(m_appcfg))
{
memcpy(&m_appcfg, cfg, len);
m_appcfg_len = len;
}
- PosLibEvent_add(POSLIB_CTRL_EVENT_APPCFG);
- }
\ No newline at end of file
+ PosLibEvent_add(POSLIB_CTRL_EVENT_APPCFG);
+ }
diff --git a/libraries/positioning/poslib/poslib_da.c b/libraries/positioning/poslib/poslib_da.c
index 983e52d2..6724a457 100644
--- a/libraries/positioning/poslib/poslib_da.c
+++ b/libraries/positioning/poslib/poslib_da.c
@@ -28,7 +28,7 @@ static shared_data_item_t m_router_pos_item;
//received data filter used by tag to receive ACK data from router
static shared_data_item_t m_tag_ack_item;
-
+
static uint16_t m_sequence = 0; // the sequence of the rising packets
#define IS_DA_ROUTER(x) (x == APP_LIB_STATE_DIRADV_SUPPORTED)
@@ -36,7 +36,7 @@ static uint16_t m_sequence = 0; // the sequence of the rising packets
#define IS_NOT_DA_ROUTER(x) (x == APP_LIB_STATE_DIRADV_NOT_SUPPORTED)
#define ROUTER_COST_INVALID(x) (x == APP_LIB_STATE_INVALID_ROUTE_COST || x == APP_LIB_STATE_COST_UNKNOWN)
-#define MAX_NBORS 20
+#define MAX_NBORS 20
#define NBOR_LAST_SEEN_WINDOW 2
#define NO_ROUTE_FOUND_ADDRESS 0
@@ -50,8 +50,8 @@ app_lib_state_nbor_list_t m_nbors_list =
/**
* @brief Callback for router positioning data reception
- * @param[in] item pointer to shared data filter \ref shared_data_item_t
- * @param[in] data pointer to received data \ref app_lib_data_received_t
+ * @param[in] item pointer to shared data filter \ref shared_data_item_t
+ * @param[in] data pointer to received data \ref app_lib_data_received_t
* @return See \ref app_lib_data_receive_res_e
*/
static app_lib_data_receive_res_e router_pos_data_cb(const shared_data_item_t * item,
@@ -66,19 +66,18 @@ static app_lib_data_receive_res_e router_pos_data_cb(const shared_data_item_t *
.src_endpoint = POS_SOURCE_ENDPOINT,
.dest_endpoint = POS_DESTINATION_ENDPOINT,
.qos = APP_LIB_DATA_QOS_NORMAL,
- .delay = 0,
.flags = APP_LIB_DATA_SEND_FLAG_NONE,
.tracking_id = 0,
};
poslib_meas_message_header_t msg_header;
poslib_meas_record_da_t da;
app_lib_data_send_res_e res;
-
+
if (item->filter.src_endpoint != POSLIB_DA_SRC_EP &&
item->filter.dest_endpoint != POSLIB_DA_DEST_EP)
{
- LOG(LVL_ERROR, "Incorect EP: %u/%u",
+ LOG(LVL_ERROR, "Incorect EP: %u/%u",
item->filter.src_endpoint, item->filter.dest_endpoint);
return APP_LIB_DATA_RECEIVE_RES_HANDLED;
}
@@ -117,7 +116,6 @@ static app_lib_data_receive_res_e router_pos_data_cb(const shared_data_item_t *
// send data
payload.bytes = bytes;
payload.num_bytes = len;
- payload.delay = data->delay; // Inherits incoming packet delay
res = Shared_Data_sendData(&payload, NULL);
if (res == APP_LIB_DATA_SEND_RES_SUCCESS)
@@ -134,7 +132,7 @@ static app_lib_data_receive_res_e router_pos_data_cb(const shared_data_item_t *
static bool router_ack_cb(const ack_gen_input_t * in, ack_gen_output_t * out)
{
-
+
if (in->src_endpoint == POS_SOURCE_ENDPOINT &&
in->dest_endpoint == POS_DESTINATION_ENDPOINT)
{
@@ -150,7 +148,7 @@ static bool router_ack_cb(const ack_gen_input_t * in, ack_gen_output_t * out)
{
out->data = NULL;
out->length = 0;
- LOG(LVL_DEBUG, "DA ACK void addr: %u, src_ep: %u, dest_ep: %u app cfg: %u",
+ LOG(LVL_DEBUG, "DA ACK void addr: %u, src_ep: %u, dest_ep: %u app cfg: %u",
in->sender, in->src_endpoint, in->dest_endpoint);
}
return true;
@@ -172,14 +170,14 @@ bool start_router()
app_res_e res;
lib_settings->getNodeRole(&role);
-
+
// Activation posible only for LL headnode
if ( role != APP_LIB_SETTINGS_ROLE_HEADNODE_LL)
{
LOG(LVL_INFO, "Only LL router supported. Role: %u", role);
return false;
}
-
+
// FixME: replace with shared DA library when available
lib_advertiser->setRouterAckGenCb(router_ack_cb);
@@ -191,7 +189,7 @@ bool start_router()
LOG(LVL_ERROR, "Cannot register DA data reception");
return false;
}
-
+
LOG(LVL_INFO, "DA router started!");
return true;
}
@@ -227,15 +225,15 @@ static int compare_neighbours(const void * pa, const void *pb)
if ((IS_DA_ROUTER(a->diradv_support) && IS_DA_ROUTER(b->diradv_support)) ||
(IS_UNKNOWN_DA_ROUTER(a->diradv_support) && IS_UNKNOWN_DA_ROUTER(b->diradv_support)))
{
- dt = a->last_update - b->last_update;
+ dt = a->last_update - b->last_update;
if (abs(dt) > NBOR_LAST_SEEN_WINDOW)
{
// select latest updated
return dt;
}
// Select strongest RSSI
- return (b->norm_rssi - a->norm_rssi);
- }
+ return (b->norm_rssi - a->norm_rssi);
+ }
else if (IS_DA_ROUTER(a->diradv_support) ||
(IS_UNKNOWN_DA_ROUTER(a->diradv_support) && IS_NOT_DA_ROUTER(b->diradv_support)))
{
@@ -249,12 +247,12 @@ static int compare_neighbours(const void * pa, const void *pb)
return 1;
}
// A & B invalid -> equal
- return 0;
+ return 0;
}
/**
* \brief Updates neiggbours list stored in m_nbors_list
- * sorted based on criteria implemented in
+ * sorted based on criteria implemented in
* \return number of neigbours valid for DA communication
*/
static void update_neigbours()
@@ -262,13 +260,13 @@ static void update_neigbours()
m_nbors_list.number_nbors = MAX_NBORS;
lib_state->getNbors(&m_nbors_list);
- qsort(m_nbors_list.nbors, m_nbors_list.number_nbors,
+ qsort(m_nbors_list.nbors, m_nbors_list.number_nbors,
sizeof(m_nbors_list.nbors[0]), compare_neighbours);
for (uint8_t i = 0; i < m_nbors_list.number_nbors; i++)
{
- LOG(LVL_DEBUG,"neigh address: %u da: %u type: %u rssi: %i cost: %u last: %u", m_nbors[i].address,
- m_nbors[i].diradv_support, m_nbors[i].type, m_nbors[i].norm_rssi, m_nbors[i].cost, m_nbors[i].last_update);
+ LOG(LVL_DEBUG,"neigh address: %u da: %u type: %u rssi: %i cost: %u last: %u", m_nbors[i].address,
+ m_nbors[i].diradv_support, m_nbors[i].type, m_nbors[i].norm_rssi, m_nbors[i].cost, m_nbors[i].last_update);
}
}
@@ -286,7 +284,7 @@ static app_lib_data_receive_res_e tag_ack_cb(const shared_data_item_t * item,
}
else
{
- LOG(LVL_ERROR, "Incorect EP: %u/%u",
+ LOG(LVL_ERROR, "Incorect EP: %u/%u",
item->filter.src_endpoint, item->filter.dest_endpoint);
}
return APP_LIB_DATA_RECEIVE_RES_HANDLED;
@@ -306,7 +304,7 @@ static bool start_tag(poslib_da_settings_t * da_settings)
{
app_res_e res;
adv_option_t option;
- bool ret;
+ bool ret;
option.follow_network = da_settings->follow_network;
lib_advertiser->setOptions(&option);
@@ -317,7 +315,7 @@ static bool start_tag(poslib_da_settings_t * da_settings)
if (res == APP_RES_OK)
{
- LOG(LVL_DEBUG, "Registered tag DA ACK data EP: %u/%u",
+ LOG(LVL_DEBUG, "Registered tag DA ACK data EP: %u/%u",
m_tag_ack_item.filter.src_endpoint, m_tag_ack_item.filter.dest_endpoint);
}
else
@@ -333,7 +331,7 @@ static void stop_tag()
{
if (m_tag_ack_item.cb != NULL)
{
- Shared_Data_removeDataReceivedCb(&m_tag_ack_item);
+ Shared_Data_removeDataReceivedCb(&m_tag_ack_item);
}
}
@@ -346,7 +344,7 @@ void PosLibDa_stop()
bool PosLibDa_start(poslib_settings_t * settings)
{
bool ret = true;
-
+
switch(settings->node_mode)
{
case POSLIB_MODE_DA_TAG:
@@ -357,7 +355,7 @@ bool PosLibDa_start(poslib_settings_t * settings)
}
case POSLIB_MODE_AUTOSCAN_ANCHOR:
case POSLIB_MODE_OPPORTUNISTIC_ANCHOR:
- {
+ {
if (settings->da.routing_enabled)
{
stop_tag();
@@ -378,7 +376,7 @@ app_lib_data_send_res_e PosLibDa_sendData(app_lib_data_to_send_t * data,
app_lib_data_data_sent_cb_f sent_cb)
{
app_lib_settings_role_t role;
- app_lib_data_send_res_e res = APP_LIB_DATA_SEND_RES_INVALID_DEST_ADDRESS;
+ app_lib_data_send_res_e res = APP_LIB_DATA_SEND_RES_INVALID_DEST_ADDRESS;
lib_settings->getNodeRole(&role);
/** If: role is not DA or destination_address is a unicast send directly */
@@ -393,7 +391,7 @@ app_lib_data_send_res_e PosLibDa_sendData(app_lib_data_to_send_t * data,
for (uint8_t i = 0; i < m_nbors_list.number_nbors; i++)
{
-
+
if (ROUTER_COST_INVALID(m_nbors[i].cost))
{
continue;
@@ -408,4 +406,4 @@ app_lib_data_send_res_e PosLibDa_sendData(app_lib_data_to_send_t * data,
LOG(LVL_WARNING, "Fail DA data send. router: %u, res: %u", m_nbors[i].address, res);
}
return res;
-}
\ No newline at end of file
+}
diff --git a/libraries/positioning/poslib/poslib_mbcn.c b/libraries/positioning/poslib/poslib_mbcn.c
index eef2d98e..90f508d4 100644
--- a/libraries/positioning/poslib/poslib_mbcn.c
+++ b/libraries/positioning/poslib/poslib_mbcn.c
@@ -74,17 +74,17 @@ static uint8_t encode_mbcn(poslib_mbcn_config_t * settings, uint8_t * buf, uint8
{
record = &settings->records[i];
- if (record->type != POSLIB_MBCN_INVALID_TYPE &&
- record->type <= POSLIB_MBCN_MAX_TYPE &&
- record->length != 0 &&
+ if (record->type != POSLIB_MBCN_INVALID_TYPE &&
+ record->type <= POSLIB_MBCN_MAX_TYPE &&
+ record->length != 0 &&
record->length <= sizeof(record->value))
{
item.type = record->type;
item.length = record->length;
item.value = (uint8_t *) record->value;
PosLibTlv_Encode_addItem(&rcd, &item);
- LOG(LVL_DEBUG, "MBCN add record. type: %u, len: %u, buf: %u",
- record->type, record->length, rcd.index);
+ LOG(LVL_DEBUG, "MBCN add record. type: %u, len: %u, buf: %u",
+ record->type, record->length, rcd.index);
}
}
LOG(LVL_DEBUG, "MBCN records: %u", rcd.index);
@@ -95,7 +95,7 @@ void PosLibMbcn_stop()
{
App_Scheduler_cancelTask(mbcn_task);
m_started = false;
- LOG(LVL_ERROR, "Mini-beacon stopped");
+ LOG(LVL_ERROR, "Mini-beacon stopped");
}
bool PosLibMbcn_start(poslib_mbcn_config_t * settings)
@@ -109,7 +109,7 @@ bool PosLibMbcn_start(poslib_mbcn_config_t * settings)
m_started = false;
return false;
}
-
+
if (!m_started)
{
// Initialize constant values in mini-beacon data sent structure
@@ -118,15 +118,14 @@ bool PosLibMbcn_start(poslib_mbcn_config_t * settings)
m_mbcn.src_endpoint = POSLIB_MBCN_SRC_EP;
m_mbcn.dest_endpoint = POSLIB_MBCN_DEST_EP;
m_mbcn.qos = APP_LIB_DATA_QOS_NORMAL;
- m_mbcn.delay = 0;
m_mbcn.flags = APP_LIB_DATA_SEND_NW_CH_ONLY;
m_mbcn.tracking_id = 0;
m_mbcn.hop_limit = 1;
}
-
+
// Fill payload content
m_payload.seq = 0;
- m_mbcn.num_bytes = sizeof(m_payload.seq);
+ m_mbcn.num_bytes = sizeof(m_payload.seq);
m_mbcn.num_bytes += encode_mbcn(settings, m_payload.data, sizeof(m_payload.data));
//Add the task sending mini-beacons
@@ -163,7 +162,7 @@ bool PosLibMbcn_decode(uint8_t * buf, uint8_t length, poslib_mbcn_data_t * mbcn)
LOG(LVL_ERROR, "Incorrect input parameters!");
return false;
}
-
+
mbcn->seq = payload->seq;
rcd.buffer = payload->data;
rcd.length = length - sizeof(payload->seq);
@@ -174,7 +173,7 @@ bool PosLibMbcn_decode(uint8_t * buf, uint8_t length, poslib_mbcn_data_t * mbcn)
while (i < sizeof(mbcn->records))
{
- res = PosLibTlv_Decode_getNextItem(&rcd, &item);
+ res = PosLibTlv_Decode_getNextItem(&rcd, &item);
if (res == POSLIB_TLV_RES_OK)
{
@@ -195,7 +194,7 @@ bool PosLibMbcn_decode(uint8_t * buf, uint8_t length, poslib_mbcn_data_t * mbcn)
case POSLIB_MBCN_FEATURES:
{
-
+
if (item.length == sizeof(mbcn->features))
{
memcpy(&mbcn->features, item.value, item.length);
@@ -246,4 +245,4 @@ bool PosLibMbcn_decode(uint8_t * buf, uint8_t length, poslib_mbcn_data_t * mbcn)
}
}
return ret;
-}
\ No newline at end of file
+}
diff --git a/libraries/positioning/poslib/poslib_measurement.c b/libraries/positioning/poslib/poslib_measurement.c
index 1fde2d67..45e1489b 100644
--- a/libraries/positioning/poslib/poslib_measurement.c
+++ b/libraries/positioning/poslib/poslib_measurement.c
@@ -674,7 +674,7 @@ static bool add_voltage_record(poslib_meas_payload_buffer_t * buf)
return ret;
}
-bool PosLibMeas_getPayload(uint8_t * bytes, uint8_t max_len, uint8_t sequence,
+bool PosLibMeas_getPayload(uint8_t * bytes, uint8_t max_len, uint16_t sequence,
poslib_measurements_e meas_type, bool add_voltage,
poslib_meas_record_node_info_t * node_info,
uint8_t * num_bytes, uint8_t * num_meas)
diff --git a/libraries/positioning/poslib/poslib_measurement.h b/libraries/positioning/poslib/poslib_measurement.h
index 64562d87..96119e0c 100644
--- a/libraries/positioning/poslib/poslib_measurement.h
+++ b/libraries/positioning/poslib/poslib_measurement.h
@@ -151,7 +151,7 @@ uint8_t PosLibMeas_getBeaconNum(void);
*/
void PosLibMeas_stop(void);
-bool PosLibMeas_getPayload(uint8_t * bytes, uint8_t max_len, uint8_t sequence,
+bool PosLibMeas_getPayload(uint8_t * bytes, uint8_t max_len, uint16_t sequence,
poslib_measurements_e meas_type, bool add_voltage,
poslib_meas_record_node_info_t * node_info,
uint8_t * bytes_len, uint8_t * num_meas);
diff --git a/libraries/provisioning/provisioning.c b/libraries/provisioning/provisioning.c
index b8da2270..4d5aa819 100644
--- a/libraries/provisioning/provisioning.c
+++ b/libraries/provisioning/provisioning.c
@@ -215,7 +215,6 @@ static uint32_t send_ack_packet(void)
.bytes = (uint8_t *)&ack_data,
.num_bytes = sizeof(pdu_prov_data_ack_t),
.dest_address = get_dest_address(),
- .delay = 0,
.qos = APP_LIB_DATA_QOS_HIGH,
.flags = APP_LIB_DATA_SEND_FLAG_NONE,
.src_endpoint = PROV_UPLINK_EP,
@@ -291,7 +290,7 @@ provisioning_res_e process_data_packet(void)
}
}
- else if (m_conf.method == PROV_METHOD_SECURED)
+ else if (m_conf.method == PROV_METHOD_SECURED || m_conf.method == PROV_METHOD_EXTENDED_UID)
{
if (pdu->data.key_index == 1)
{
@@ -415,7 +414,7 @@ static uint32_t state_idle(void)
/* Generate IV for Secured method. The same IV will be used even
* for retries.
*/
- if (m_conf.method == PROV_METHOD_SECURED)
+ if (m_conf.method == PROV_METHOD_SECURED || m_conf.method == PROV_METHOD_EXTENDED_UID)
{
for(int i=0; i < AES_128_KEY_BLOCK_SIZE; i++)
{
@@ -499,7 +498,6 @@ static uint32_t state_start(void)
m_conf.uid_len +
AES_128_KEY_BLOCK_SIZE,
.dest_address = get_dest_address(),
- .delay = 0,
.qos = APP_LIB_DATA_QOS_HIGH,
.flags = APP_LIB_DATA_SEND_FLAG_NONE,
.src_endpoint = PROV_UPLINK_EP,
@@ -842,4 +840,4 @@ provisioning_ret_e Provisioning_stop(void)
m_conf.end_cb(PROV_RES_STOPPED);
return PROV_RET_OK;
-}
\ No newline at end of file
+}
diff --git a/libraries/provisioning/provisioning.h b/libraries/provisioning/provisioning.h
index 16e06475..df0ee271 100644
--- a/libraries/provisioning/provisioning.h
+++ b/libraries/provisioning/provisioning.h
@@ -44,6 +44,7 @@ typedef enum
{
PROV_METHOD_UNSECURED = 0, /**< Unsecured provisioning method. */
PROV_METHOD_SECURED = 1, /**< Secured provisioning method. */
+ PROV_METHOD_EXTENDED_UID = 3 /**< Extended UID provisioning method. */
} provisioning_method_e;
/**
diff --git a/libraries/provisioning/provisioning_int.h b/libraries/provisioning/provisioning_int.h
index 5c898446..2bbed881 100644
--- a/libraries/provisioning/provisioning_int.h
+++ b/libraries/provisioning/provisioning_int.h
@@ -43,10 +43,16 @@
#define PROV_DATA_MAX_USER_ID 255
/** Network address for sending and receiving joining beacons */
-#define JOINING_NETWORK_ADDRESS 0x89d3b8 // "JBTX"
+#define JOINING_NETWORK_ADDRESS 0x9E4ADC // "JBTX"
/** Network channel for sending and receiving joining beacons */
+// For Massive, joining network channel is 36
+#ifdef MAC_PROFILE_ISM24
+#define JOINING_NETWORK_CHANNEL 36
+// For other mac profile (SubGhz and 5G Mesh), channel 4 is used
+#else
#define JOINING_NETWORK_CHANNEL 4
+#endif
/** Time to scan for joining beacons, in milliseconds.
* \ref JOINING_RX_TIMEOUT and \ref JOINING_TX_INTERVAL needs to
diff --git a/libraries/provisioning/proxy.c b/libraries/provisioning/proxy.c
index 95344c0d..1ffab5bf 100644
--- a/libraries/provisioning/proxy.c
+++ b/libraries/provisioning/proxy.c
@@ -57,7 +57,6 @@ void send_nack(prov_nack_type_e type, const app_lib_data_received_t * data)
.bytes = (uint8_t *)&nack_pdu,
.num_bytes = sizeof(pdu_prov_nack_t),
.dest_address = data->src_address,
- .delay = 0,
.qos = APP_LIB_DATA_QOS_HIGH,
.flags = APP_LIB_DATA_SEND_FLAG_NONE,
.src_endpoint = PROV_DOWNLINK_EP,
@@ -243,7 +242,7 @@ static app_lib_data_receive_res_e pkt_received_cb(
LOG_BUFFER(LVL_DEBUG, data->bytes, data->num_bytes);
/* Check if it is a ACK packet. */
- if (pdu->pdu_header.type != PROV_PACKET_TYPE_START)
+ if (pdu->pdu_header.type == PROV_PACKET_TYPE_DATA_ACK)
{
LOG(LVL_INFO, "ACK received from %08X.", data->src_address);
return APP_LIB_DATA_RECEIVE_RES_HANDLED;
@@ -339,7 +338,6 @@ static app_lib_data_receive_res_e pkt_received_cb(
.bytes = data_buffer,
.num_bytes = PROV_DATA_OFFSET + data_len,
.dest_address = data->src_address,
- .delay = 0,
.qos = APP_LIB_DATA_QOS_HIGH,
.flags = APP_LIB_DATA_SEND_FLAG_NONE,
.src_endpoint = PROV_DOWNLINK_EP,
diff --git a/libraries/rtc/README.md b/libraries/rtc/README.md
new file mode 100644
index 00000000..f3413a54
--- /dev/null
+++ b/libraries/rtc/README.md
@@ -0,0 +1,97 @@
+# Wirepas Library RTC
+
+## Overview
+This library allows Wirepas devices to receive a real-time clock from a gateway without specific hardware.
+
+This service handles the RTC time reception messages and maintains the time locally to the node.
+
+
+## Functions
+
+| Function | Parameters | Description | Note |
+| ------------- | ---- | --- | --- |
+| RTC_init | void | Initialize the stack state library. | The function is called automatically when importing the library |
+| RTC_getUTCTime | rtc_timestamp_t * now | Store expected UTC RTC time in the variable now. | |
+| RTC_getLocalTime | rtc_timestamp_t * now | Store expected RTC time with the local timezone in the variable now | |
+| RTC_getTimezoneOffsetInSeconds | long * timezoneOffsetInSeconds | Get configured timezone offset of the node | The offset is provided by the gateway |
+| RTC_addInitializeCb | on_rtc_initialized callback | Add a new callback to be informed when RTC time is available from network | The callback will be called only once: at the initialization of the time references |
+| RTC_removeInitializedCb | on_rtc_initialized callback | Remove an event callback from the list. | |
+
+## How to use
+
+To import the library in an application, the line "RTC=yes" must be present in the makefile of the application and RTC_CBS variable must contain the number of callbacks to be launched at the first rtc message reception (can be 0 if information is not needed by application).
+
+
+## How does it work
+
+This service gets the global time in UTC timezone from a gateway.
+At the moment the time is received, the local clock and the rtc received are taken as references.
+RTC reference time is taken as rtc timestamp parameter in the payload and added to the travel time of the packet between the sink and the node.
+It is therefore, supposed to be the RTC time at the time where the message is received at the device.
+
+Each time an application needs the RTC time, the library returns sum of the last known RTC time (received from the network) and the elapsed time since the reception.
+
+
+## Messages format
+
+TLV encoding is used to allow extension in future.
+The messages are composed of:
+
+A version on 2 bytes to ensure the content will be well parsed by the RTC library.
+
+And the content is encoded with TLV with the following content:
+
+| Parameter | Type | Number of bytes | Description |
+| ------------- | ---- | --- | --- |
+| rtc timestamp | unsigned long long | 8 | Timestamp of the current rtc time in the UTC timezone |
+| timezone offset | long | 4 | Local timezone offset in seconds |
+
+
+### TLV encoding
+
+To encode messages with TLV, the type(id) of each parameter must be given as follow:
+
+RTC_ID_TIMESTAMP = 0,
+RTC_ID_TIMEZONE_OFFSET = 1
+
+Then the length of the value is coded in hexadecimal.
+And finally the value itself is encoded in hexadecimal.
+
+For example, a message containing:
+
+The RTC version equal to 1: 0x0001 which is not encoded.
+And the TLV encoded content with:
+
+| Parameter | Type | Number of bytes | Value |
+| ------------- | ---- | --- | --- |
+| rtc timestamp | 0 | 8 | 0x000001850aeb3964 |
+| timezone offset | 1 | 4 | 0x1c20 (7200s = 2h) |
+
+Each parameter is encoded with TLV as byte(type)(1 byte) - byte(length)(1 byte) - byte(value)(length bytes) individually and their bytes are concatenated.
+
+The message is therefore encoded with TLV in little-endian as:
+b'\x01\x00\x00\x08\x64\x39\xeb\x0a\x85\x01\x00\x00\x01\x04\x20\x1c\x00\x00'
+
+
+## Time precision
+
+Due to the multiple steps, the RTC time might lose some precision:
+
+Time is taken from a distant ntp server. The estimated latency may be inaccurate as it is calculated from the round-trip of the asymmetrical exchange. This is similar for all systems relying on NTP, but it must be acknowledged for better understanding of the time precision (around 10ms of precision).
+
+As devices use their own clock to stay synchronous,
+a drift might happen between the expected RTC time and the real one from the ntp server.
+It is empirically estimated to be a 1ms shift at the node level every 30s in a Low Latency mode.
+Furthermore, the time within the network is about 20ms beacause of the ntp precison and the delay caused by the gateway to the sink.
+
+For example, after 20 minutes having received RTC time, the difference between expected RTC from nodes and its real value is about 60ms (=10 + 10 + 20*60/30).
+A SDK RTC application example is providing a [backend script][Backend script] to calculate at a gateway level the time difference between the nodes expectations and the real value of the RTC and can be used validate the time precision.
+
+A latency may also occur when transferring the messages between nodes, but it hasn’t been tested yet.
+
+
+### Use conditions
+
+Nodes need to receive periodically the rtc time to stay synchronous.
+
+[Backend scripts]: ../../source/unitary_apps/rtc_app/backend_script/
diff --git a/libraries/rtc/rtc.c b/libraries/rtc/rtc.c
new file mode 100644
index 00000000..397da8ec
--- /dev/null
+++ b/libraries/rtc/rtc.c
@@ -0,0 +1,412 @@
+/* Copyright 2023 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+
+#define DEBUG_LOG_MODULE_NAME "RTC"
+#ifdef DEBUG_RTC_LOG_MAX_LEVEL
+#define DEBUG_LOG_MAX_LEVEL DEBUG_RTC_LOG_MAX_LEVEL
+#else
+#define DEBUG_LOG_MAX_LEVEL LVL_NOLOG
+#endif
+
+#include
+#include
+#include
+#include
+
+#include "api.h"
+#include "app_scheduler.h"
+#include "tlv.h"
+#include "debug_log.h"
+#include "shared_data.h"
+#include "rtc.h"
+
+/** Boolean asserting whether the library has been initialized (RTC_init). */
+static bool m_initialized = false;
+
+/** Endpoint to send and receive rtc data. */
+#define DATA_RTC_SRC_EP (78u) // TODO
+#define DATA_RTC_DEST_EP (79u) // TODO
+
+/** Period in milliseconds of update_time_references function. */
+#define UPDATE_TIME_REFERENCES_PERIOD_MS (1200000ul) // 20 minutes
+
+/** Offset between utc time to local timezone in seconds. */
+static long m_timezone_offset_s;
+/** Time of the last rtc update in high precision unit. */
+static uint32_t m_local_reference_time_hp;
+/** Time of the last received RTC in milliseconds. */
+static rtc_timestamp_t m_rtc_reference_time_ms;
+
+/** Boolean asserting whether the rtc has been received at least once. */
+static bool m_is_rtc_set;
+
+typedef struct
+{
+ on_rtc_initialized cb;
+} rtc_cb_t;
+
+/** List of callbacks to be called when first rtc is received. */
+static rtc_cb_t m_on_rtc_initialized_cbs[RTC_MAX_CB];
+
+
+/* RTC Received message type */
+typedef struct
+{
+ /** Timestamp of the rtc in utc time format in milliseconds. */
+ rtc_timestamp_t timestamp_ms;
+ /** Number of seconds to be added to the utc time to know local time. */
+ long timezone_offset;
+} rtc_recv_msg_t;
+
+
+static void handle_tlv_item(tlv_item_t * item, rtc_recv_msg_t * rtc_recv_msg)
+{
+ switch(item->type)
+ {
+ case RTC_ID_TIMESTAMP:
+ {
+ if(item->length == sizeof(rtc_timestamp_t))
+ {
+ memcpy(&rtc_recv_msg->timestamp_ms,
+ (rtc_timestamp_t *) item->value,
+ sizeof(rtc_recv_msg->timestamp_ms));
+ }
+ break;
+ }
+ case RTC_ID_TIMEZONE_OFFSET:
+ {
+ if(item->length == sizeof(int32_t))
+ {
+ memcpy(&rtc_recv_msg->timezone_offset,
+ (int32_t *) item->value,
+ sizeof(rtc_recv_msg->timezone_offset));
+ }
+ break;
+ }
+ default:
+ {
+ /* Let other ids not to be checked to be backward compatible. */
+ break;
+ }
+ }
+}
+
+/**
+ * @brief Initialize tlv decoder and buffer.
+ */
+static rtc_res_e parse_rtc_message(uint8_t * rtc_recv_buffer_p, int num_bytes, rtc_recv_msg_t * rtc_recv_msg)
+{
+ memset(rtc_recv_msg, 0, sizeof(*rtc_recv_msg));
+
+ tlv_record record;
+ Tlv_init(&record, rtc_recv_buffer_p, num_bytes);
+
+ tlv_item_t item;
+ tlv_res_e res = TLV_RES_OK; // result of TLV parsing
+ while(res == TLV_RES_OK)
+ {
+ res = Tlv_Decode_getNextItem(&record, &item);
+ handle_tlv_item(&item, rtc_recv_msg);
+ }
+ if(res != TLV_RES_END)
+ {
+ return RTC_INVALID_VALUE; // TLV Parsing returned an error
+ }
+ return RTC_RES_OK;
+}
+
+/**
+ * \brief Update local reference time
+ * \note As high precision timestamps are given with a 36 minutes loop
+ * for arithmetical uses, it is necessary to update the time references
+ * before it loops otherwise rtc time will be incorrect.
+*/
+static uint32_t update_time_references(void)
+{
+ LOG(LVL_DEBUG, "update_time_references - update time references");
+ uint32_t new_local_reference_time_hp = lib_time->getTimestampHp();
+ uint32_t time_spent_since_ref_us = lib_time->getTimeDiffUs(
+ new_local_reference_time_hp, m_local_reference_time_hp);
+
+ /* Updating time references. */
+ Sys_enterCriticalSection();
+ m_local_reference_time_hp = new_local_reference_time_hp;
+ // 1 ms precision is lost, but it can be neglected
+ // due to other time precision loses that are greater as,
+ // this function is called once every 20 minutes.
+ m_rtc_reference_time_ms += time_spent_since_ref_us/1000;
+ Sys_exitCriticalSection();
+
+ return UPDATE_TIME_REFERENCES_PERIOD_MS;
+}
+
+/**
+ * \brief Return the local time elapsed since the last rtc update.
+ */
+static uint32_t time_since_last_update_ms(void)
+{
+ return lib_time->getTimeDiffUs(
+ lib_time->getTimestampHp(), m_local_reference_time_hp)/1000;
+}
+
+/**
+ * \brief Reference locally the rtc time sent by the sink.
+ * \return Return code of the operation \ref rtc_res_e
+ */
+static rtc_res_e set_rtc(rtc_recv_msg_t rtc_recv_msg)
+{
+ Sys_enterCriticalSection();
+ /* Change time references for new ones */
+ m_timezone_offset_s = rtc_recv_msg.timezone_offset;
+ // End-to-end transmission delay has to be added to the time
+ // sent in the network for the time to be relevant
+ m_rtc_reference_time_ms = rtc_recv_msg.timestamp_ms;
+
+ /* Variables to calculate rtc at any time */
+ m_local_reference_time_hp = lib_time->getTimestampHp();
+ m_is_rtc_set = true;
+ Sys_exitCriticalSection();
+
+ LOG(LVL_INFO,
+ "received time is 0x%x%08x and time zone has a shift of %lis on utc",
+ (uint32_t) (m_rtc_reference_time_ms>>32),
+ (uint32_t) m_rtc_reference_time_ms,
+ m_timezone_offset_s);
+ return RTC_RES_OK;
+}
+
+rtc_res_e RTC_getUTCTime(rtc_timestamp_t * now)
+{
+ if (!m_is_rtc_set)
+ {
+ LOG(LVL_WARNING, "RTC_getUTCTime - Time has not been received yet");
+ return RTC_UNINITIALIZED;
+ }
+ /* The RTC time in UTC Timezone is basically the sum of rtc reference time
+ * and the time spent since the last rtc reference update. */
+ *now = m_rtc_reference_time_ms + time_since_last_update_ms();
+ return RTC_RES_OK;
+}
+
+rtc_res_e RTC_getLocalTime(rtc_timestamp_t * now)
+{
+ if (!m_is_rtc_set)
+ {
+ LOG(LVL_WARNING, "RTC_getLocalTime - Time has not been received yet");
+ return RTC_UNINITIALIZED;
+ }
+ long timezone_offset;
+ rtc_res_e res = RTC_getTimezoneOffsetInSeconds(&timezone_offset);
+ if (res != RTC_RES_OK)
+ {
+ LOG(LVL_WARNING, "RTC_getLocalTime - Timezone has not been set yet");
+ return res;
+ }
+ /* Local time is basically the sum of rtc reference time,
+ * the time spent since the last rtc reference update and
+ * the timezone offset. */
+ *now = m_rtc_reference_time_ms + time_since_last_update_ms() + timezone_offset*1000;
+ return res;
+}
+
+rtc_res_e RTC_getTimezoneOffsetInSeconds(long * timezoneOffsetInSeconds)
+{
+ if (!m_is_rtc_set)
+ {
+ LOG(LVL_WARNING, "RTC_getTimezoneOffsetInSeconds - Time has not been received yet");
+ return RTC_UNINITIALIZED;
+ }
+ *timezoneOffsetInSeconds = m_timezone_offset_s;
+ return RTC_RES_OK;
+}
+
+/**
+ * \brief Launch all callbacks present in the list m_on_rtc_initialized_cbs.
+ * \return Return code of the operation \ref rtc_res_e
+ */
+static rtc_res_e lauch_rtc_cbs(void)
+{
+ LOG(LVL_DEBUG, "Callbacks which need RTC time to be set are being called.");
+ for (uint8_t i = 0; i < RTC_MAX_CB; i++)
+ {
+ rtc_cb_t on_rtc_initialized_cb = m_on_rtc_initialized_cbs[i];
+ if(on_rtc_initialized_cb.cb != NULL)
+ {
+ on_rtc_initialized_cb.cb();
+ }
+ }
+ return RTC_RES_OK;
+}
+
+/**
+ * \brief Data reception callback
+ * \param data
+ * Received data, \ref app_lib_data_received_t
+ * \return Result code, \ref app_lib_data_receive_res_e
+ */
+static app_lib_data_receive_res_e rtc_received_cb(
+ const shared_data_item_t * item,
+ const app_lib_data_received_t * data)
+{
+ LOG(LVL_INFO, "rtc_received_cb - A RTC message has been received");
+ rtc_recv_msg_t rtc_recv_msg;
+ uint8_t * rtc_recv_buffer_p = (uint8_t *) data->bytes;
+ uint16_t * version = (uint16_t *) data->bytes;
+ uint64_t travel_time_hp = ((uint64_t) data->delay_hp);
+ bool rtc_already_set = m_is_rtc_set;
+
+ // Verify that the message contains more than just a version
+ if(data->num_bytes <= sizeof(uint16_t))
+ {
+ LOG(LVL_WARNING, "rtc_received_cb - RTC message received is too small");
+ return APP_LIB_DATA_RECEIVE_RES_HANDLED; // discard the message
+ }
+
+ // Verify the message version
+ if (*version != RTC_VERSION)
+ {
+ LOG(LVL_WARNING, "rtc_received_cb - RTC message has not the good version");
+ return APP_LIB_DATA_RECEIVE_RES_HANDLED; // discard the message
+ }
+
+ if(parse_rtc_message(rtc_recv_buffer_p+2, data->num_bytes-2, &rtc_recv_msg) != RTC_RES_OK)
+ {
+ LOG(LVL_WARNING, "rtc_received_cb - RTC message could not be parsed");
+ return APP_LIB_DATA_RECEIVE_RES_HANDLED; // discard the message
+ }
+
+ // Sets the new time reference of the rtc.
+ rtc_recv_msg.timestamp_ms += ((travel_time_hp * 1000) >> 10);
+ set_rtc(rtc_recv_msg);
+
+ // Updates the time references in 20 minutes.
+ App_Scheduler_addTask_execTime(&update_time_references,
+ UPDATE_TIME_REFERENCES_PERIOD_MS,
+ 50);
+
+ if(!rtc_already_set)
+ {
+ // Some callbacks must be launched the first time RTC time is set.
+ lauch_rtc_cbs();
+ }
+
+ // Data handled successfully
+ return APP_LIB_DATA_RECEIVE_RES_HANDLED;
+}
+
+/* Unicast messages filter */
+static shared_data_item_t alltype_packets_filter =
+{
+ .cb = rtc_received_cb,
+ .filter = {
+ .mode = SHARED_DATA_NET_MODE_ALL,
+ /* Filtering by source endpoint. */
+ .src_endpoint = DATA_RTC_SRC_EP,
+ /* Filtering by destination endpoint. */
+ .dest_endpoint = DATA_RTC_DEST_EP
+ }
+};
+
+rtc_res_e RTC_init(void)
+{
+ if (m_initialized)
+ {
+ LOG(LVL_DEBUG, "RTC_init: already initialized)");
+ return RTC_RES_OK;
+ }
+ m_is_rtc_set = false;
+
+ for (uint8_t i = 0; i < RTC_MAX_CB; i++)
+ {
+ m_on_rtc_initialized_cbs[i].cb = NULL;
+ }
+ m_initialized = true;
+ LOG(LVL_DEBUG, "RTC_init (%d)", RTC_MAX_CB);
+
+ /* Set unicast & broadcast received messages callback. */
+ Shared_Data_addDataReceivedCb(&alltype_packets_filter);
+
+ return RTC_RES_OK;
+}
+
+rtc_res_e RTC_addInitializeCb(on_rtc_initialized callback)
+{
+ if (!m_initialized)
+ {
+ return RTC_INVALID_VALUE;
+ }
+ rtc_res_e res = RTC_NO_MORE_CALLBACKS;
+ int free_slot = -1;
+
+ if (callback == NULL)
+ {
+ return RTC_INVALID_VALUE;
+ }
+
+ Sys_enterCriticalSection();
+ for (uint8_t i = 0; i < RTC_MAX_CB; i++)
+ {
+ if (m_on_rtc_initialized_cbs[i].cb == NULL)
+ {
+ /* One free room found */
+ free_slot = i;
+ continue;
+ }
+ else if (m_on_rtc_initialized_cbs[i].cb == callback)
+ {
+ /* Callback already present */
+ res = RTC_RES_OK;
+ break;
+ }
+ }
+
+ if (res != RTC_RES_OK && free_slot >= 0)
+ {
+ /* Callback was not already present and a free room was found */
+ m_on_rtc_initialized_cbs[free_slot].cb = callback;
+ res = RTC_RES_OK;
+ }
+ Sys_exitCriticalSection();
+
+ if (res == RTC_RES_OK)
+ {
+ LOG(LVL_DEBUG, "Add rtc cb (0x%x)", callback);
+ }
+ else
+ {
+ LOG(LVL_ERROR, "Cannot add rtc cb (0x%x)", callback);
+ }
+ return res;
+}
+
+rtc_res_e RTC_removeInitializedCb(on_rtc_initialized callback)
+{
+ if (!m_initialized)
+ {
+ return RTC_INVALID_VALUE;
+ }
+ rtc_res_e res = RTC_UNKNOWN_CALLBACK;
+
+ LOG(LVL_DEBUG, "Removing event cb (0x%x)", callback);
+
+ Sys_enterCriticalSection();
+ for (uint8_t i = 0; i < RTC_MAX_CB; i++)
+ {
+ if (m_on_rtc_initialized_cbs[i].cb == callback)
+ {
+ m_on_rtc_initialized_cbs[i].cb= NULL;
+ res = RTC_RES_OK;
+ }
+ }
+ Sys_exitCriticalSection();
+
+ if (res != RTC_RES_OK)
+ {
+ LOG(LVL_ERROR, "Cannot remove event cb (0x%x)", callback);
+ }
+
+ return res;
+}
diff --git a/libraries/rtc/rtc.h b/libraries/rtc/rtc.h
new file mode 100644
index 00000000..f59594af
--- /dev/null
+++ b/libraries/rtc/rtc.h
@@ -0,0 +1,102 @@
+/* Copyright 2023 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+
+#ifndef _RTC_H_
+#define _RTC_H_
+
+#include
+#include
+
+
+#define RTC_VERSION (uint16_t)(1)
+
+
+/**
+ * \brief List of return code
+ */
+typedef enum
+{
+ /** Operation is successful */
+ RTC_RES_OK = 0,
+ /** RTC is not yet available from network */
+ RTC_UNAVAILABLE_YET = 1,
+ /** Cannot register new callback*/
+ RTC_NO_MORE_CALLBACKS = 2,
+ /** Callback is not known */
+ RTC_UNKNOWN_CALLBACK = 3,
+ /** One or more parameter value is invalid */
+ RTC_INVALID_VALUE = 4,
+ /** The library has not been initialized. */
+ RTC_UNINITIALIZED = 5,
+} rtc_res_e;
+
+/** \brief List of Wirepas Ids for TLV encoded provisioning data. */
+typedef enum
+{
+ RTC_ID_TIMESTAMP = 0,
+ RTC_ID_TIMEZONE_OFFSET = 1
+} provisioning_data_ids_e;
+
+typedef uint64_t rtc_timestamp_t;
+
+/**
+ * \brief Callback called the first time RTC time is aquired from network
+ * \note It is up to registered module to call \ref RTC_getUTCTime() in the callback
+ */
+typedef void
+ (*on_rtc_initialized)(void);
+
+/**
+ * @brief Initialize the stack state library.
+ * @return Return code of operation
+ */
+rtc_res_e RTC_init(void);
+
+/**
+ * @brief Get current expected RTC time from node.
+ * @param now
+ * Current RTC time if return code is RTC_RES_OK
+ * @return Return code of the operation @ref rtc_res_e
+ * @note RTC time must have been received from network in the last 50 days.
+ */
+rtc_res_e RTC_getUTCTime(rtc_timestamp_t * now);
+
+/**
+ * @brief Get current expected RTC time with timezone from node.
+ * @param now
+ * Current local time if return code is RTC_RES_OK
+ * @return Return code of the operation @ref rtc_res_e
+ */
+rtc_res_e RTC_getLocalTime(rtc_timestamp_t * now);
+
+/**
+ * @brief Get configured timezone offset of the node
+ * @param timezoneOffsetInSeconds
+ * timezone offset of the local time if return code is RTC_RES_OK
+ * @return Return code of the operation @ref rtc_res_e
+ */
+rtc_res_e RTC_getTimezoneOffsetInSeconds(long * timezoneOffsetInSeconds);
+
+/**
+ * @brief Add a new callback to be informed when RTC time is available from network.
+ * @param callback
+ * New callback
+ * @return RTC_RES_OK if ok. See \ref rtc_res_e for
+ * other result codes.
+ */
+rtc_res_e RTC_addInitializeCb(on_rtc_initialized callback);
+
+/**
+ * @brief Remove an event callback from the list.
+ * Removed item fields are all set to 0.
+ * @param callback
+ * callback to remove.
+ * @return RTC_RES_OK if ok. See \ref app_res_e for
+ * other result codes.
+ */
+rtc_res_e RTC_removeInitializedCb(on_rtc_initialized callback);
+
+#endif //_RTC_H_
diff --git a/libraries/scheduler/app_scheduler.c b/libraries/scheduler/app_scheduler.c
index cd7a0cb4..81110746 100644
--- a/libraries/scheduler/app_scheduler.c
+++ b/libraries/scheduler/app_scheduler.c
@@ -19,8 +19,8 @@ static uint32_t m_max_time_ms;
*/
static bool m_initialized = false;
-/** Measured time on nrf52 (13us) */
-#define EXECUTION_TIME_NEEDED_FOR_SCHEDULING_US 20
+/** Measured time on nrf52 (13us) and nrf91 (32us) */
+#define EXECUTION_TIME_NEEDED_FOR_SCHEDULING_US 35
/** Maximum execution time application can request from stack (100ms) */
#define MAX_EXECUTION_TIME_ALLOWED_BY_STACK_US (100 * 1000)
@@ -419,7 +419,10 @@ void App_Scheduler_init()
}
// Maximum time to postpone the periodic work
- m_max_time_ms = lib_time->getMaxHpDelay() / 1000;
+ // Add some margin to avoid rounding issue. So take 80% of the max value
+ // In fact it is also used as the value to determine in which time domain
+ // tasks are scheduled (hp or coarse timestamp)
+ m_max_time_ms = lib_time->getMaxHpDelay() / 1000 * 8 / 10;
m_next_task_p = NULL;
m_force_reschedule = false;
diff --git a/libraries/shared_data/shared_data.c b/libraries/shared_data/shared_data.c
index b6a021bc..51e65ff7 100644
--- a/libraries/shared_data/shared_data.c
+++ b/libraries/shared_data/shared_data.c
@@ -9,6 +9,10 @@
#define DEBUG_LOG_MAX_LEVEL LVL_NOLOG
#include "debug_log.h"
+#ifdef WIRESHARK
+#include "wireshark.h"
+#endif
+
/** Some helpers macros for packet filtering. */
#define IS_UNICAST(mode) (mode == SHARED_DATA_NET_MODE_UNICAST)
#define IS_BROADCAST(mode) (mode == SHARED_DATA_NET_MODE_BROADCAST)
@@ -224,6 +228,21 @@ static app_lib_data_receive_res_e received_cb(
{
app_lib_data_receive_res_e res = APP_LIB_DATA_RECEIVE_RES_NOT_FOR_APP;
shared_data_item_t * item;
+
+#ifdef WIRESHARK
+ Wireshark_print(
+ data->src_address,
+ data->dest_address,
+ data->qos,
+ data->src_endpoint,
+ data->dest_endpoint,
+ data->rssi,
+ data->delay_hp,
+ data->bytes,
+ data->num_bytes
+ );
+#endif
+
sl_list_t * i = sl_list_begin((sl_list_t *)&m_shared_data_head);
LOG(LVL_DEBUG, "Rx (%u, %d -> %d)",
@@ -300,6 +319,11 @@ app_res_e Shared_Data_init(void)
return APP_RES_OK;
}
+#ifdef WIRESHARK
+ Wireshark_init();
+#endif
+
+
sl_list_init(&m_shared_data_head);
m_iterating_list = false;
@@ -478,6 +502,27 @@ app_lib_data_send_res_e Shared_Data_sendData(
/* Send the data packet. */
res = lib_data->sendData(data);
+ if (res == APP_LIB_DATA_SEND_RES_SUCCESS)
+ {
+ app_addr_t node_addr;
+ lib_settings->getNodeAddress(&node_addr);
+
+#ifdef WIRESHARK
+ Wireshark_print(
+ // no rssi nor delay so 0 for both
+ node_addr,
+ data->dest_address,
+ data->qos,
+ data->src_endpoint,
+ data->dest_endpoint,
+ 0,
+ 0,
+ data->bytes,
+ data->num_bytes
+ );
+#endif
+ }
+
/* Free resources if packet is tracked. */
if (res != APP_LIB_DATA_SEND_RES_SUCCESS && sent_cb != NULL)
{
diff --git a/makefile b/makefile
index 8fc75eab..734fb655 100644
--- a/makefile
+++ b/makefile
@@ -3,22 +3,42 @@
include makefile_common.mk
+# Version of GCC used for Wirepas testing
+GCC_TESTED_VERSION := 10.3.1
+
+# Check the toolchain version with GCC
+GCC_VERSION := $(shell $(CC) -dumpversion)
+ifneq ($(GCC_VERSION), $(findstring $(GCC_VERSION), $(GCC_TESTED_VERSION)))
+$(warning ***********************************************************************)
+$(warning "GCC version used is not the recommended and tested by Wirepas )
+$(warning "Recommended version is : $(GCC_TESTED_VERSION))
+$(warning ***********************************************************************)
+endif
+
#
# Targets
#
# Scratchpads for OTAP
+
FULL_SCRATCHPAD_NAME := $(APP_NAME)_$(FIRMWARE_NAME)
FULL_SCRATCHPAD_BIN := $(BUILDPREFIX_APP)$(FULL_SCRATCHPAD_NAME).otap
APP_SCRATCHPAD_NAME := $(APP_NAME)
APP_SCRATCHPAD_BIN := $(BUILDPREFIX_APP)$(APP_SCRATCHPAD_NAME).otap
STACK_SCRATCHPAD_NAME := $(FIRMWARE_NAME)
STACK_SCRATCHPAD_BIN := $(BUILDPREFIX_APP)$(STACK_SCRATCHPAD_NAME).otap
+ifneq ($(modemfw_area_id),)
+ifneq ($(radio),none)
+ifneq ($(modem_fw),)
+FULL_SCRATCHPAD_WITH_MODEMFW_NAME := $(APP_NAME)_$(FIRMWARE_NAME)_modem_fw
+FULL_SCRATCHPAD_WITH_MODEMFW_BIN := $(BUILDPREFIX_APP)$(FULL_SCRATCHPAD_WITH_MODEMFW_NAME).otap
+endif
+endif
+endif
-BOOTLOADER_CONFIG_INI := $(BUILDPREFIX_APP)bootloader_full_config.ini
PLATFORM_CONFIG_INI := $(MCU_PATH)$(MCU_FAMILY)/$(MCU)/ini_files/$(MCU)$(MCU_SUB)$(MCU_MEM_VAR)_platform.ini
-CLEAN += $(FULL_SCRATCHPAD_BIN) $(APP_SCRATCHPAD_BIN) $(STACK_SCRATCHPAD_BIN) $(BOOTLOADER_CONFIG_INI)
+CLEAN += $(FULL_SCRATCHPAD_BIN) $(APP_SCRATCHPAD_BIN) $(STACK_SCRATCHPAD_BIN) $(FULL_SCRATCHPAD_WITH_MODEMFW_BIN) $(BOOTLOADER_CONFIG_INI)
# Final image for programming
FINAL_IMAGE_NAME := final_image_$(APP_NAME)
@@ -69,6 +89,15 @@ updater_app_area_id=$(updater_app_specific_area_id)$(HW_VARIANT_ID)
#
# Functions
+define BUILD_FULL_SCRATCHPAD_WITH_MODEMFW
+ @echo " Creating Full Scratchpad with modem: $(2) + $(3) + $(4) -> $(1)"
+ $(SCRAT_GEN) --configfile=$(BOOTLOADER_CONFIG_INI) \
+ $(1) \
+ $(modemfw_area_id):$(2) \
+ $(patsubst %.hex,%.conf,$(3)):$(firmware_area_id):$(3) \
+ $(app_major).$(app_minor).$(app_maintenance).$(app_development):$(app_area_id):$(4)
+endef
+
define BUILD_FULL_SCRATCHPAD
@echo " Creating Full Scratchpad: $(2) + $(3) -> $(1)"
$(SCRAT_GEN) --configfile=$(BOOTLOADER_CONFIG_INI) \
@@ -116,7 +145,7 @@ all: $(TARGETS)
app_only: $(APP_HEX) $(APP_SCRATCHPAD_BIN)
-otap: $(FULL_SCRATCHPAD_BIN) $(APP_SCRATCHPAD_BIN) $(STACK_SCRATCHPAD_BIN)
+otap: $(FULL_SCRATCHPAD_BIN) $(APP_SCRATCHPAD_BIN) $(STACK_SCRATCHPAD_BIN) $(FULL_SCRATCHPAD_WITH_MODEMFW_BIN)
bootloader: $(BOOTLOADER_HEX)
@@ -165,7 +194,7 @@ $(APP_HEX):: initial_setup $(BUILDPREFIX_APP) need_board
# Add $(BOOTLOADER_HEX) to PHONY to always call bootloader makefile
.PHONY: $(BOOTLOADER_HEX)
-$(BOOTLOADER_HEX): initial_setup need_board
+$(BOOTLOADER_HEX): initial_setup need_board $(BOOTLOADER_CONFIG_INI)
@ # Call bootloader makefile to get the hex file of bootloader
+$(MAKE) -f makefile_bootloader.mk
@@ -183,6 +212,14 @@ $(APP_SCRATCHPAD_BIN): initial_setup $(APP_HEX) $(BOOTLOADER_CONFIG_INI)
$(FULL_SCRATCHPAD_BIN): initial_setup $(STACK_HEX) $(APP_HEX) $(BOOTLOADER_CONFIG_INI)
$(call BUILD_FULL_SCRATCHPAD,$(FULL_SCRATCHPAD_BIN),$(STACK_HEX),$(APP_HEX))
+ifneq ($(modemfw_area_id),)
+ifneq ($(radio),none)
+$(FULL_SCRATCHPAD_WITH_MODEMFW_BIN): initial_setup $(STACK_HEX) $(APP_HEX) $(BOOTLOADER_CONFIG_INI)
+ $(call BUILD_FULL_SCRATCHPAD_WITH_MODEMFW,$(FULL_SCRATCHPAD_WITH_MODEMFW_BIN),${modem_fw},$(STACK_HEX),$(APP_HEX))
+
+endif
+endif
+
$(FINAL_IMAGE_HEX): initial_setup $(STACK_HEX) $(APP_HEX) $(BOOTLOADER_HEX) $(BOOTLOADER_CONFIG_INI)
$(call BUILD_HEX,$(FINAL_IMAGE_HEX),$(BOOTLOADER_HEX),$(STACK_HEX),$(APP_HEX),$(EXTRA_HEX))
diff --git a/makefile_app.mk b/makefile_app.mk
index 2e17f3ee..5ea576ca 100644
--- a/makefile_app.mk
+++ b/makefile_app.mk
@@ -3,7 +3,12 @@ include makefile_common.mk
.DEFAULT_GOAL := all
# Linker script
+ifndef MCU_RAM_VAR
LDSCRIPT = $(MCU_PATH)$(MCU_FAMILY)/$(MCU)/linker/gcc_app_$(MCU)$(MCU_SUB)$(MCU_MEM_VAR).ld
+else
+LDSCRIPT = $(MCU_PATH)$(MCU_FAMILY)/$(MCU)/linker/gcc_app_$(MCU)$(MCU_SUB)$(MCU_MEM_VAR)_$(MCU_RAM_VAR).ld
+endif
+
LIBS :=
ifeq ($(filter $(TARGET_BOARDS),$(target_board)),)
@@ -37,6 +42,11 @@ endif
# And version numbers
CFLAGS += -DVER_MAJOR=$(app_major) -DVER_MINOR=$(app_minor) -DVER_MAINT=$(app_maintenance) -DVER_DEV=$(app_development)
+# Mac profile
+ifeq ("$(mac_profile)","ism_24_ghz")
+ CFLAGS += -DMAC_PROFILE_ISM24
+endif
+
# Include board init part
-include board/makefile
@@ -54,7 +64,10 @@ CFLAGS += -DVER_MAJOR=$(app_major) -DVER_MINOR=$(app_minor) -DVER_MAINT=$(app_ma
-include $(WP_LIB_PATH)makefile
INCLUDES += -I$(WP_LIB_PATH)
-# Include HAL drivers code
+# Include MCU config first
+-include $(MCU_PATH)config.mk
+
+# Include MCU HAL drivers code
-include $(HAL_API_PATH)makefile
# Include common MCU sources
@@ -107,4 +120,3 @@ clean:
$(RM) -rf $(CLEAN)
-include $(DEPS)
-
diff --git a/makefile_bootloader.mk b/makefile_bootloader.mk
index cfe07145..75957b5c 100644
--- a/makefile_bootloader.mk
+++ b/makefile_bootloader.mk
@@ -12,7 +12,12 @@ BOOTLOADER_SRC := $(BUILDPREFIX_BOOTLOADER)bootloader.a
BL_BUILDPREFIX := $(BUILDPREFIX_BOOTLOADER)
# Linker for the bootloader
-LDSCRIPT := $(MCU_PATH)$(MCU_FAMILY)/$(MCU)/linker/gcc_bl_$(MCU)$(MCU_SUB)$(MCU_MEM_VAR).ld
+ifndef MCU_RAM_VAR
+LDSCRIPT = $(MCU_PATH)$(MCU_FAMILY)/$(MCU)/linker/gcc_bl_$(MCU)$(MCU_SUB)$(MCU_MEM_VAR).ld
+else
+LDSCRIPT = $(MCU_PATH)$(MCU_FAMILY)/$(MCU)/linker/gcc_bl_$(MCU)$(MCU_SUB)$(MCU_MEM_VAR)_$(MCU_RAM_VAR).ld
+endif
+
BOOTLOADER_ELF := $(BL_BUILDPREFIX)bootloader.elf
@@ -35,11 +40,13 @@ CLEAN := $(OBJS) $(BOOTLOADER_ELF) $(BOOTLOADER_HEX)
$(BOOTLOADER_SRC): FORCE
# Get the right firmware from the image folder
$(MKDIR) $(@D)
+ $(eval key_type=$(shell $(BOOT_CONF) --in_file $(BOOTLOADER_CONFIG_INI) --get_key_type))
@$(FMW_SEL) --firmware_path=$(IMAGE_PATH)\
--firmware_type="wp_bootloader"\
--version=$(MIN_BOOTLOADER_VERSION)\
--output_path=$(@D)\
--output_name="bootloader"\
+ --key_type=$(key_type)\
--unlocked=$(unprotected)\
--mcu=$(MCU)\
--mcu_sub=$(MCU_SUB)\
diff --git a/makefile_common.mk b/makefile_common.mk
index 1d068085..e9a6d7ea 100644
--- a/makefile_common.mk
+++ b/makefile_common.mk
@@ -1,21 +1,21 @@
-# Version of GCC used for Wirepas testing
-GCC_TESTED_VERSION := 10.2.1
-
# Minimum binaries version required by this SDK version
MIN_BOOTLOADER_VERSION := 7
-MIN_STACK_VERSION := 5.3.0.0
+MIN_STACK_VERSION := 5.4.0.0
# SDK itself
SDK_PATH := .
INCLUDES := -I$(SDK_PATH)
+build_directory?= build/
+board_directory?= board/
+
# General SDK folder structure
API_PATH := api/
UTIL_PATH := util/
HAL_API_PATH := mcu/hal_api/
WP_LIB_PATH := libraries/
-GLOBAL_BUILD := build/
-BOARDS_PATH := board/
+GLOBAL_BUILD := $(build_directory)
+BOARDS_PATH := $(board_directory)
BOARDS_PATH_INTERNAL := board_internal/
MCU_PATH := mcu/
@@ -79,15 +79,6 @@ WIZARD := $(python) tools/sdk_wizard.py
HEX2ARRAY32 := $(python) tools/hextoarray32.py
MAKE := make
-# Check the toolchain version with GCC
-GCC_VERSION := $(shell $(CC) -dumpversion)
-ifneq ($(GCC_VERSION), $(findstring $(GCC_VERSION), $(GCC_TESTED_VERSION)))
-$(warning ***********************************************************************)
-$(warning "GCC version used is not the recommended and tested by Wirepas )
-$(warning "Recommended version is : $(GCC_TESTED_VERSION))
-$(warning ***********************************************************************)
-endif
-
# List of available boards found under board/
AVAILABLE_BOARDS := $(patsubst $(BOARDS_PATH)%/,%,$(sort $(dir $(wildcard $(BOARDS_PATH)*/.))))
@@ -131,6 +122,7 @@ INCLUDES += -I$(MCU_PATH)common/cmsis -I$(BOARD_FOLDER)
# Folder where the application sources are located (and config file)
# Can be in different folders, try them one by one
APP_POSSIBLE_FOLDER := source/*/$(app_name)/ source/$(app_name)/
+APP_POSSIBLE_FOLDER += $(app_extra_folder)/$(app_name)/
APP_SRCS_PATH := $(wildcard $(APP_POSSIBLE_FOLDER))
ifeq (,$(wildcard $(APP_SRCS_PATH)))
@@ -169,7 +161,10 @@ BOOTLOADER_HEX := $(BUILDPREFIX_BOOTLOADER)bootloader.hex
BOOTLOADER_TEST_HEX := $(BUILDPREFIX_APP)bootloader_test/bootloader_test.hex
BOOTLOADER_UPDATER_HEX := $(BUILDPREFIX)bootloader_updater/bootloader_updater.hex
BOOTLOADER_UPDATER_DATA_BIN := $(BUILDPREFIX)bootloader_updater/bootloader_updater_data.bin
+BOOTLOADER_CONFIG_INI := $(BUILDPREFIX_APP)bootloader_full_config.ini
STACK_HEX := $(BUILDPREFIX_STACK)$(FIRMWARE_NAME).hex
APP_HEX := $(BUILDPREFIX_APP)$(APP_NAME).hex
+
+mac_profile?=ism_24_ghz
diff --git a/makefile_stack.mk b/makefile_stack.mk
index b47ea5da..32fdba61 100644
--- a/makefile_stack.mk
+++ b/makefile_stack.mk
@@ -4,7 +4,7 @@ include makefile_common.mk
stack_mode?=normal
-mac_profile?=ism_24_ghz
+modemfw_name?=
$(STACK_HEX): FORCE
# Get the right stack from the image folder
@@ -19,6 +19,7 @@ $(STACK_HEX): FORCE
--mac_profile=$(mac_profile)\
--mac_profileid=$(mac_profileid)\
--mode=$(stack_mode)\
+ --modem_fw=$(modemfw_name)\
--radio=$(radio)\
--radio_config=$(radio_config)\
--version=$(MIN_STACK_VERSION)
diff --git a/mcu/common/button.c b/mcu/common/button.c
new file mode 100644
index 00000000..b25b2f3f
--- /dev/null
+++ b/mcu/common/button.c
@@ -0,0 +1,313 @@
+/* Copyright 2022 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+
+/*
+ * \file button.c
+ * \brief Board-independent button functions.
+ */
+
+#include "button.h"
+#include "gpio.h"
+#include "board.h"
+#include "api.h"
+
+
+#ifdef BOARD_BUTTON_ID_LIST
+
+/*
+ * The selected board has buttons
+ */
+
+#ifndef BOARD_DEBOUNCE_TIME_MS
+/** \brief Debounce time of button in ms. It can be overwritten from board.h */
+#define BOARD_DEBOUNCE_TIME_MS 100
+#endif
+
+#ifndef BOARD_BUTTON_ACTIVE_LOW
+/** \brief Is button active low. It can be overwritten from board.h */
+#define BOARD_BUTTON_ACTIVE_LOW true
+#endif
+
+#ifndef BOARD_BUTTON_INTERNAL_PULL
+/** \brief Does the driver needs to activate internal pull-up/down.
+ * If true; pull-up (down) is enabled if BOARD_BUTTON_ACTIVE_LOW is
+ * true (false). It can be overwritten from board.h
+ */
+#define BOARD_BUTTON_INTERNAL_PULL true
+#endif
+
+/** \brief Button id to GPIO id map (array index: button id ; array value: GPIO id) */
+static const uint8_t m_id_map[] = BOARD_BUTTON_ID_LIST;
+
+/** \brief Compute number of button on the board */
+#define BOARD_BUTTON_NUMBER (sizeof(m_id_map) / sizeof(m_id_map[0]))
+
+typedef struct
+{
+ // Callback when button pressed
+ on_button_event_cb on_pressed;
+ // Callback when button released
+ on_button_event_cb on_released;
+ // Used for debounce
+ app_lib_time_timestamp_hp_t last_button_event;
+} button_internal_t;
+
+/** \brief Button id to button conf map (array index: button id ; array value: button conf) */
+static button_internal_t m_button_conf[BOARD_BUTTON_NUMBER];
+
+/** \brief Has the button library been initialized */
+static bool m_initialized = false;
+
+static void button_event_handle(gpio_id_t gpio_id, gpio_in_event_e gpio_event);
+static bool get_button_id_from_gpio_id(gpio_id_t gpio_id, uint8_t *button_id);
+
+static inline gpio_in_cfg_t get_button_gpio_cfg(void)
+{
+ gpio_in_cfg_t gpio_in_cfg;
+
+ gpio_in_cfg.event_cb = NULL;
+ gpio_in_cfg.event_cfg = GPIO_IN_EVENT_NONE;
+#if BOARD_BUTTON_INTERNAL_PULL
+#if BOARD_BUTTON_ACTIVE_LOW
+ gpio_in_cfg.in_mode_cfg = GPIO_IN_PULL_UP;
+#else
+ gpio_in_cfg.in_mode_cfg = GPIO_IN_PULL_DOWN;
+#endif // BOARD_BUTTON_ACTIVE_LOW
+#else
+ gpio_in_cfg.in_mode_cfg = GPIO_IN_PULL_NONE;
+#endif // BOARD_BUTTON_INTERNAL_PULL
+
+ return gpio_in_cfg;
+}
+
+void Button_init(void)
+{
+ uint8_t button_id;
+ app_lib_time_timestamp_hp_t now = lib_time->getTimestampHp();
+ button_internal_t button_conf =
+ {
+ .on_pressed = NULL,
+ .on_released = NULL,
+ .last_button_event = now
+ };
+ gpio_id_t gpio_id;
+ gpio_in_cfg_t gpio_in_cfg;
+
+ if (m_initialized)
+ {
+ /* return if button initialization has already been performed */
+ return;
+ }
+
+ gpio_in_cfg = get_button_gpio_cfg();
+
+ for (button_id = 0; button_id < BOARD_BUTTON_NUMBER; button_id++)
+ {
+ gpio_id = m_id_map[button_id];
+ Gpio_inputSetCfg(gpio_id, &gpio_in_cfg);
+ m_button_conf[button_id] = button_conf;
+ }
+
+ m_initialized = true;
+}
+
+button_res_e Button_getState(uint8_t button_id, bool * state_p)
+{
+ gpio_level_e gpio_level = GPIO_LEVEL_LOW;
+ gpio_id_t gpio_id;
+
+ if (!m_initialized)
+ {
+ return BUTTON_RES_UNINITIALIZED;
+ }
+ if (button_id >= BOARD_BUTTON_NUMBER)
+ {
+ return BUTTON_RES_INVALID_ID;
+ }
+
+ gpio_id = m_id_map[button_id];
+ Gpio_inputRead(gpio_id, &gpio_level);
+
+ /*
+ * level | active_low | state |
+ * clear | 0 | 0 |
+ * set | 0 | 1 |
+ * clear | 1 | 1 |
+ * set | 1 | 0 |
+ */
+ *state_p = ((gpio_level != GPIO_LEVEL_LOW) != BOARD_BUTTON_ACTIVE_LOW);
+
+ return BUTTON_RES_OK;
+}
+
+button_res_e Button_register_for_event(uint8_t button_id,
+ button_event_e event,
+ on_button_event_cb cb)
+{
+ gpio_id_t gpio_id;
+ gpio_in_cfg_t gpio_in_cfg;
+
+ if (!m_initialized)
+ {
+ return BUTTON_RES_UNINITIALIZED;
+ }
+ if (button_id >= BOARD_BUTTON_NUMBER)
+ {
+ return BUTTON_RES_INVALID_ID;
+ }
+ if ((event != BUTTON_PRESSED && event != BUTTON_RELEASED) ||
+ (cb == NULL))
+ {
+ return BUTTON_RES_INVALID_PARAM;
+ }
+
+ gpio_in_cfg = get_button_gpio_cfg();
+
+ Sys_enterCriticalSection();
+
+ if (event == BUTTON_PRESSED)
+ {
+ m_button_conf[button_id].on_pressed = cb;
+ }
+ else
+ {
+ m_button_conf[button_id].on_released = cb;
+ }
+
+ /* if on both press and release */
+ if (m_button_conf[button_id].on_pressed &&
+ m_button_conf[button_id].on_released)
+ {
+ gpio_in_cfg.event_cfg = GPIO_IN_EVENT_RISING_EDGE | GPIO_IN_EVENT_FALLING_EDGE;
+ }
+ /* else if on press only or on release only */
+ else
+ {
+ /*
+ * button_event | active_low | gpio_event |
+ * on_pressed | 0 | on_rising_edge |
+ * on_released | 0 | on_falling_edge |
+ * on_pressed | 1 | on_falling_edge |
+ * on_released | 1 | on_rising_edge |
+ */
+ gpio_in_cfg.event_cfg = ((m_button_conf[button_id].on_pressed != NULL) != BOARD_BUTTON_ACTIVE_LOW) ?
+ GPIO_IN_EVENT_RISING_EDGE : GPIO_IN_EVENT_FALLING_EDGE;
+ }
+ gpio_in_cfg.event_cb = button_event_handle;
+
+ gpio_id = m_id_map[button_id];
+ Gpio_inputSetCfg(gpio_id, &gpio_in_cfg);
+
+ Sys_exitCriticalSection();
+
+ return BUTTON_RES_OK;
+}
+
+uint8_t Button_get_number(void)
+{
+ return BOARD_BUTTON_NUMBER;
+}
+
+static void button_event_handle(gpio_id_t gpio_id, gpio_in_event_e gpio_event)
+{
+ uint8_t button_id;
+ bool button_id_found;
+ app_lib_time_timestamp_hp_t now = lib_time->getTimestampHp();
+
+ if (gpio_id >= Gpio_getNumber())
+ {
+ return;
+ }
+
+ /* get button id from gpio id */
+ button_id_found = get_button_id_from_gpio_id(gpio_id, &button_id);
+ if (button_id_found == false)
+ {
+ return;
+ }
+
+ if (lib_time->getTimeDiffUs(now, m_button_conf[button_id].last_button_event)
+ > (BOARD_DEBOUNCE_TIME_MS * 1000))
+ {
+ m_button_conf[button_id].last_button_event = now;
+
+ if ((m_button_conf[button_id].on_pressed) &&
+ (((gpio_event == GPIO_IN_EVENT_RISING_EDGE) && !BOARD_BUTTON_ACTIVE_LOW) ||
+ ((gpio_event == GPIO_IN_EVENT_FALLING_EDGE) && BOARD_BUTTON_ACTIVE_LOW)))
+ {
+ m_button_conf[button_id].on_pressed(button_id, BUTTON_PRESSED);
+ }
+ else if ((m_button_conf[button_id].on_released) &&
+ (((gpio_event == GPIO_IN_EVENT_FALLING_EDGE) && !BOARD_BUTTON_ACTIVE_LOW) ||
+ ((gpio_event == GPIO_IN_EVENT_RISING_EDGE) && BOARD_BUTTON_ACTIVE_LOW)))
+ {
+ m_button_conf[button_id].on_released(button_id, BUTTON_RELEASED);
+ }
+ }
+}
+
+static bool get_button_id_from_gpio_id(gpio_id_t gpio_id, uint8_t *button_id)
+{
+ uint8_t button_id_tmp;
+
+ if (button_id == NULL)
+ {
+ return false;
+ }
+
+ /* browse the button IDs and find the one that is mapped to the given GPIO id */
+ for (button_id_tmp = 0; button_id_tmp < BOARD_BUTTON_NUMBER; button_id_tmp++)
+ {
+ if (m_id_map[button_id_tmp] == gpio_id)
+ {
+ *button_id = button_id_tmp;
+ return true;
+ }
+ }
+ return false;
+}
+
+#else // BOARD_BUTTON_ID_LIST
+/*
+ * The selected board has no buttons
+ *
+ * As some example apps support such boards but also provide extra features
+ * when a board has buttons, the button driver has this dummy implementation
+ * to simplify the build process.
+ */
+
+void Button_init(void)
+{
+ // Do nothing
+}
+
+button_res_e Button_getState(uint8_t button_id, bool * state_p)
+{
+ (void) button_id;
+ *state_p = false;
+
+ // Invalid button number
+ return BUTTON_RES_INVALID_ID;
+}
+
+uint8_t Button_get_number(void)
+{
+ return 0;
+}
+
+button_res_e Button_register_for_event(uint8_t button_id,
+ button_event_e event,
+ on_button_event_cb cb)
+{
+ (void) button_id;
+ (void) event;
+ (void) cb;
+
+ // Invalid button number
+ return BUTTON_RES_INVALID_ID;
+}
+
+#endif // BOARD_BUTTON_ID_LIST
diff --git a/mcu/efr/efr32/hal/ds.c b/mcu/common/ds.c
similarity index 88%
rename from mcu/efr/efr32/hal/ds.c
rename to mcu/common/ds.c
index a3a2e20b..f41aaa4c 100644
--- a/mcu/efr/efr32/hal/ds.c
+++ b/mcu/common/ds.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 Wirepas Ltd. All Rights Reserved.
+/* Copyright 2017 Wirepas Ltd. All Rights Reserved.
*
* See file LICENSE.txt for full license details.
*
@@ -6,7 +6,7 @@
#include
-#include "hal_api.h"
+#include "ds.h"
#include "api.h"
// Bitmask holding different sleep control bits
@@ -40,5 +40,6 @@ void DS_Disable(uint32_t source)
m_sleep_mask |= source;
// Disable deep sleep
Sys_disableDs(true);
+ // End of atomic operation
Sys_exitCriticalSection();
}
diff --git a/mcu/common/gpio_weak.c b/mcu/common/gpio_weak.c
new file mode 100644
index 00000000..1d4083b1
--- /dev/null
+++ b/mcu/common/gpio_weak.c
@@ -0,0 +1,87 @@
+/* Copyright 2022 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+
+/**
+ * \file gpio_weak.c
+ * \brief Definitions of gpio weak functions.
+ * \attention Should be compatible with the gpio.h interface.
+ */
+
+#include "gpio.h"
+
+gpio_res_e __attribute__((weak))
+ Gpio_init(void)
+{
+ return GPIO_RES_NOT_IMPLEMENTED;
+}
+
+gpio_res_e __attribute__((weak))
+ Gpio_inputSetCfg(gpio_id_t id, const gpio_in_cfg_t *in_cfg)
+{
+ (void) id;
+ (void) in_cfg;
+
+ return GPIO_RES_NOT_IMPLEMENTED;
+}
+
+gpio_res_e __attribute__((weak))
+ Gpio_inputRead(gpio_id_t id, gpio_level_e *level)
+{
+ (void) id;
+ (void) level;
+
+ return GPIO_RES_NOT_IMPLEMENTED;
+}
+
+gpio_res_e __attribute__((weak))
+ Gpio_outputSetCfg(gpio_id_t id, const gpio_out_cfg_t *out_cfg)
+{
+ (void) id;
+ (void) out_cfg;
+
+ return GPIO_RES_NOT_IMPLEMENTED;
+}
+
+gpio_res_e __attribute__((weak)) Gpio_outputWrite(gpio_id_t id, gpio_level_e level)
+{
+ (void) id;
+ (void) level;
+
+ return GPIO_RES_NOT_IMPLEMENTED;
+}
+
+gpio_res_e __attribute__((weak))
+ Gpio_outputToggle(gpio_id_t id)
+{
+ (void) id;
+
+ return GPIO_RES_NOT_IMPLEMENTED;
+}
+
+gpio_res_e __attribute__((weak))
+ Gpio_outputRead(gpio_id_t id, gpio_level_e *level)
+{
+ (void) id;
+ (void) level;
+
+ return GPIO_RES_NOT_IMPLEMENTED;
+}
+
+gpio_res_e __attribute__((weak))
+ Gpio_getPin(gpio_id_t id, gpio_port_t *port, gpio_pin_t *pin)
+{
+ (void) id;
+ (void) port;
+ (void) pin;
+
+ return GPIO_RES_NOT_IMPLEMENTED;
+}
+
+uint8_t __attribute__((weak))
+ Gpio_getNumber(void)
+{
+ return 0;
+}
diff --git a/mcu/common/led.c b/mcu/common/led.c
new file mode 100644
index 00000000..734ed75e
--- /dev/null
+++ b/mcu/common/led.c
@@ -0,0 +1,180 @@
+/* Copyright 2022 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+
+/*
+ * \file led.c
+ * \brief Board-independent led functions.
+ */
+
+#include "led.h"
+#include "gpio.h"
+#include "board.h"
+
+#ifdef BOARD_LED_ID_LIST
+
+/*
+ * The selected board has LEDs
+ */
+
+#ifndef BOARD_LED_ACTIVE_LOW
+/** \brief Are LEDs active low. It can be overwritten from board.h */
+#define BOARD_LED_ACTIVE_LOW true
+#endif
+
+/** \brief Button id to GPIO id map (array index: button id ; array value: GPIO id) */
+static const uint8_t m_id_map[] = BOARD_LED_ID_LIST;
+
+/** \brief Compute number of leds on the board */
+#define NUMBER_OF_LEDS (sizeof(m_id_map) / sizeof(m_id_map[0]))
+
+/** \brief Has the LED library been initialized */
+static bool m_initialized = false;
+
+void Led_init(void)
+{
+ gpio_id_t gpio_id;
+ uint8_t led_id;
+ gpio_out_cfg_t gpio_out_cfg = {
+ .out_mode_cfg = GPIO_OUT_MODE_PUSH_PULL,
+ .level_default = BOARD_LED_ACTIVE_LOW ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW
+ };
+
+ if (m_initialized)
+ {
+ /* return if Led initialization has already been performed */
+ return;
+ }
+
+ for (led_id = 0; led_id < NUMBER_OF_LEDS; led_id++)
+ {
+ gpio_id = m_id_map[led_id];
+ Gpio_outputSetCfg(gpio_id, &gpio_out_cfg);
+ }
+
+ m_initialized = true;
+}
+
+led_res_e Led_set(uint8_t led_id, bool state)
+{
+ gpio_id_t gpio_id;
+ gpio_level_e gpio_level;
+
+ if (!m_initialized)
+ {
+ return LED_RES_UNINITIALIZED;
+ }
+ if (led_id >= NUMBER_OF_LEDS)
+ {
+ return LED_RES_INVALID_ID;
+ }
+
+ /*
+ * state | active_low | level |
+ * 0 | 0 | clear |
+ * 1 | 0 | set |
+ * 0 | 1 | set |
+ * 1 | 1 | clear |
+ */
+ gpio_level = (state != BOARD_LED_ACTIVE_LOW) ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW;
+
+ gpio_id = m_id_map[led_id];
+ Gpio_outputWrite(gpio_id, gpio_level);
+
+ return LED_RES_OK;
+}
+
+bool Led_get(uint8_t led_id)
+{
+ gpio_level_e level;
+ gpio_id_t gpio_id;
+ bool state;
+
+ if (!m_initialized)
+ {
+ return LED_RES_UNINITIALIZED;
+ }
+ if (led_id >= NUMBER_OF_LEDS)
+ {
+ return LED_RES_INVALID_ID;
+ }
+
+ gpio_id = m_id_map[led_id];
+ Gpio_outputRead(gpio_id, &level);
+
+ /*
+ * level | active_low | state |
+ * clear | 0 | 0 |
+ * set | 0 | 1 |
+ * clear | 1 | 1 |
+ * set | 1 | 0 |
+ */
+ state = (level != GPIO_LEVEL_LOW) != BOARD_LED_ACTIVE_LOW;
+
+ return state;
+}
+
+led_res_e Led_toggle(uint8_t led_id)
+{
+ gpio_id_t gpio_id;
+
+ if (!m_initialized)
+ {
+ return LED_RES_UNINITIALIZED;
+ }
+ if (led_id >= NUMBER_OF_LEDS)
+ {
+ return LED_RES_INVALID_ID;
+ }
+
+ gpio_id = m_id_map[led_id];
+ Gpio_outputToggle(gpio_id);
+
+ return LED_RES_OK;
+}
+
+uint8_t Led_getNumber(void)
+{
+ return NUMBER_OF_LEDS;
+}
+
+#else // BOARD_LED_ID_LIST
+
+/*
+ * The selected board has no LEDs
+ *
+ * As some example apps support such boards but also provide extra status
+ * information when a board has LEDs, the LED driver has this dummy
+ * implementation to simplify the build process.
+ */
+
+void Led_init(void)
+{
+ // Do nothing
+}
+
+led_res_e Led_set(uint8_t led_id, bool state)
+{
+ (void) led_id;
+ (void) state;
+
+ // Invalid LED number
+ return LED_RES_INVALID_ID;
+}
+
+led_res_e Led_toggle(uint8_t led_id)
+{
+ (void) led_id;
+
+ // Invalid LED number
+ return LED_RES_INVALID_ID;
+}
+
+uint8_t Led_getNumber(void)
+{
+ return 0;
+}
+
+#endif // BOARD_LED_ID_LIST
diff --git a/mcu/common/makefile b/mcu/common/makefile
index be599bd5..77cd6560 100644
--- a/mcu/common/makefile
+++ b/mcu/common/makefile
@@ -1,7 +1,20 @@
MCU_COMMON_SRCS_PATH := $(MCU_PATH)common/
+include $(MCU_COMMON_SRCS_PATH)radio/makefile
+
ASM_SRCS += $(MCU_COMMON_SRCS_PATH)entrypoint.s
-SRCS += $(MCU_COMMON_SRCS_PATH)start.c
+SRCS += $(MCU_COMMON_SRCS_PATH)start.c \
+ $(MCU_COMMON_SRCS_PATH)ds.c
-include $(MCU_COMMON_SRCS_PATH)radio/makefile
+ifeq ($(HAL_BUTTON), yes)
+SRCS += $(MCU_COMMON_SRCS_PATH)button.c
+endif
+
+ifeq ($(HAL_LED), yes)
+SRCS += $(MCU_COMMON_SRCS_PATH)led.c
+endif
+
+ifeq ($(HAL_GPIO), yes)
+SRCS += $(MCU_COMMON_SRCS_PATH)gpio_weak.c
+endif
diff --git a/mcu/common/start.c b/mcu/common/start.c
index fdb3ee8e..7d261048 100644
--- a/mcu/common/start.c
+++ b/mcu/common/start.c
@@ -13,6 +13,7 @@
#include "api.h"
#include "board_init.h"
#include "libraries_init.h"
+#include "hal_init.h"
/** Addresses determined by the linker */
extern unsigned int __text_start__;
@@ -109,6 +110,9 @@ intptr_t _start(const app_global_functions_t * functions,
API_Open(functions);
+ /* Initialize HAL drivers */
+ Hal_init();
+
/* Call any board specific initialization */
Board_init();
diff --git a/mcu/config.mk b/mcu/config.mk
new file mode 100644
index 00000000..5a3b3489
--- /dev/null
+++ b/mcu/config.mk
@@ -0,0 +1,14 @@
+# Button lib requires the GPIO lib
+ifeq ($(HAL_BUTTON), yes)
+HAL_GPIO=yes
+endif
+
+# LED lib requires the GPIO lib
+ifeq ($(HAL_LED), yes)
+HAL_GPIO=yes
+endif
+
+# UART lib requires the GPIO lib
+ifeq ($(HAL_UART), yes)
+HAL_GPIO=yes
+endif
\ No newline at end of file
diff --git a/mcu/efr/common/mcu.h b/mcu/efr/common/mcu.h
index aa88e841..d32e4ac5 100644
--- a/mcu/efr/common/mcu.h
+++ b/mcu/efr/common/mcu.h
@@ -7,8 +7,6 @@
#include "em_emu.h"
#ifdef EFR32FG12
#include "efr32fg12/efr32_gpio.h"
-#elif defined EFR32FG13
-#include "efr32fg13/efr32_gpio.h"
#elif defined EFR32MG21
#include "efr32mg21/Include/efr32mg21_gpio.h"
#include "efr32mg21/efr32_gpio.h"
@@ -18,10 +16,13 @@
#elif defined EFR32FG23
#include "efr32fg23/Include/efr32fg23_gpio.h"
#include "efr32fg23/efr32_gpio.h"
+#elif defined EFR32MG24
+#include "efr32mg24/Include/efr32mg24_gpio.h"
+#include "efr32mg24/efr32_gpio.h"
#elif defined EFR32MG12
#else
-#error("EFR32FG12, EFR32MG12, EFR32FG13, EFR32MG21, EFR32MG22 or EFR32FG23 must be defined")
+#error("EFR32FG12, EFR32MG12, EFR32MG21, EFR32MG22, EFR32FG23 or EFR32MG24 must be defined")
#endif
#endif /* MCU_H_ */
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p231f1024gl125.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p231f1024gl125.h
similarity index 91%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p231f1024gl125.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p231f1024gl125.h
index 81954799..7c8587d6 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p231f1024gl125.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p231f1024gl125.h
@@ -1,35 +1,39 @@
-/**************************************************************************//**
- * @file efr32fg12p231f1024gl125.h
+/***************************************************************************//**
+ * @file
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
* for EFR32FG12P231F1024GL125
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
#ifndef EFR32FG12P231F1024GL125_H
#define EFR32FG12P231F1024GL125_H
@@ -38,111 +42,120 @@
extern "C" {
#endif
-/**************************************************************************//**
+/***************************************************************************//**
* @addtogroup Parts
* @{
- *****************************************************************************/
+ ******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFR32FG12P231F1024GL125 EFR32FG12P231F1024GL125
* @{
- *****************************************************************************/
+ ******************************************************************************/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
+typedef enum IRQn{
/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
- NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */
- HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */
- MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
/****** EFR32FG12P Peripheral Interrupt Numbers ********************************************/
- EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */
- WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */
- WDOG1_IRQn = 3, /*!< 3 EFR32 WDOG1 Interrupt */
- LDMA_IRQn = 9, /*!< 9 EFR32 LDMA Interrupt */
- GPIO_EVEN_IRQn = 10, /*!< 10 EFR32 GPIO_EVEN Interrupt */
- TIMER0_IRQn = 11, /*!< 11 EFR32 TIMER0 Interrupt */
- USART0_RX_IRQn = 12, /*!< 12 EFR32 USART0_RX Interrupt */
- USART0_TX_IRQn = 13, /*!< 13 EFR32 USART0_TX Interrupt */
- ACMP0_IRQn = 14, /*!< 14 EFR32 ACMP0 Interrupt */
- ADC0_IRQn = 15, /*!< 15 EFR32 ADC0 Interrupt */
- IDAC0_IRQn = 16, /*!< 16 EFR32 IDAC0 Interrupt */
- I2C0_IRQn = 17, /*!< 17 EFR32 I2C0 Interrupt */
- GPIO_ODD_IRQn = 18, /*!< 18 EFR32 GPIO_ODD Interrupt */
- TIMER1_IRQn = 19, /*!< 19 EFR32 TIMER1 Interrupt */
- USART1_RX_IRQn = 20, /*!< 20 EFR32 USART1_RX Interrupt */
- USART1_TX_IRQn = 21, /*!< 21 EFR32 USART1_TX Interrupt */
- LEUART0_IRQn = 22, /*!< 22 EFR32 LEUART0 Interrupt */
- PCNT0_IRQn = 23, /*!< 23 EFR32 PCNT0 Interrupt */
- CMU_IRQn = 24, /*!< 24 EFR32 CMU Interrupt */
- MSC_IRQn = 25, /*!< 25 EFR32 MSC Interrupt */
- CRYPTO0_IRQn = 26, /*!< 26 EFR32 CRYPTO0 Interrupt */
- LETIMER0_IRQn = 27, /*!< 27 EFR32 LETIMER0 Interrupt */
- RTCC_IRQn = 30, /*!< 30 EFR32 RTCC Interrupt */
- CRYOTIMER_IRQn = 32, /*!< 32 EFR32 CRYOTIMER Interrupt */
- FPUEH_IRQn = 34, /*!< 34 EFR32 FPUEH Interrupt */
- SMU_IRQn = 35, /*!< 35 EFR32 SMU Interrupt */
- WTIMER0_IRQn = 36, /*!< 36 EFR32 WTIMER0 Interrupt */
- WTIMER1_IRQn = 37, /*!< 37 EFR32 WTIMER1 Interrupt */
- PCNT1_IRQn = 38, /*!< 38 EFR32 PCNT1 Interrupt */
- PCNT2_IRQn = 39, /*!< 39 EFR32 PCNT2 Interrupt */
- USART2_RX_IRQn = 40, /*!< 40 EFR32 USART2_RX Interrupt */
- USART2_TX_IRQn = 41, /*!< 41 EFR32 USART2_TX Interrupt */
- I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */
- USART3_RX_IRQn = 43, /*!< 43 EFR32 USART3_RX Interrupt */
- USART3_TX_IRQn = 44, /*!< 44 EFR32 USART3_TX Interrupt */
- VDAC0_IRQn = 45, /*!< 45 EFR32 VDAC0 Interrupt */
- CSEN_IRQn = 46, /*!< 46 EFR32 CSEN Interrupt */
- LESENSE_IRQn = 47, /*!< 47 EFR32 LESENSE Interrupt */
- CRYPTO1_IRQn = 48, /*!< 48 EFR32 CRYPTO1 Interrupt */
- TRNG0_IRQn = 49, /*!< 49 EFR32 TRNG0 Interrupt */
+ EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
+ WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 3, /*!< 16+3 EFR32 WDOG1 Interrupt */
+ FRC_IRQn = 4, /*!< 16+4 EFR32 FRC Interrupt */
+ MODEM_IRQn = 5, /*!< 16+5 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 6, /*!< 16+6 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 7, /*!< 16+7 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 8, /*!< 16+8 EFR32 BUFC Interrupt */
+ LDMA_IRQn = 9, /*!< 16+9 EFR32 LDMA Interrupt */
+ GPIO_EVEN_IRQn = 10, /*!< 16+10 EFR32 GPIO_EVEN Interrupt */
+ TIMER0_IRQn = 11, /*!< 16+11 EFR32 TIMER0 Interrupt */
+ USART0_RX_IRQn = 12, /*!< 16+12 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 13, /*!< 16+13 EFR32 USART0_TX Interrupt */
+ ACMP0_IRQn = 14, /*!< 16+14 EFR32 ACMP0 Interrupt */
+ ADC0_IRQn = 15, /*!< 16+15 EFR32 ADC0 Interrupt */
+ IDAC0_IRQn = 16, /*!< 16+16 EFR32 IDAC0 Interrupt */
+ I2C0_IRQn = 17, /*!< 16+17 EFR32 I2C0 Interrupt */
+ GPIO_ODD_IRQn = 18, /*!< 16+18 EFR32 GPIO_ODD Interrupt */
+ TIMER1_IRQn = 19, /*!< 16+19 EFR32 TIMER1 Interrupt */
+ USART1_RX_IRQn = 20, /*!< 16+20 EFR32 USART1_RX Interrupt */
+ USART1_TX_IRQn = 21, /*!< 16+21 EFR32 USART1_TX Interrupt */
+ LEUART0_IRQn = 22, /*!< 16+22 EFR32 LEUART0 Interrupt */
+ PCNT0_IRQn = 23, /*!< 16+23 EFR32 PCNT0 Interrupt */
+ CMU_IRQn = 24, /*!< 16+24 EFR32 CMU Interrupt */
+ MSC_IRQn = 25, /*!< 16+25 EFR32 MSC Interrupt */
+ CRYPTO0_IRQn = 26, /*!< 16+26 EFR32 CRYPTO0 Interrupt */
+ LETIMER0_IRQn = 27, /*!< 16+27 EFR32 LETIMER0 Interrupt */
+ AGC_IRQn = 28, /*!< 16+28 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 29, /*!< 16+29 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 30, /*!< 16+30 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 31, /*!< 16+31 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 32, /*!< 16+32 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 33, /*!< 16+33 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 34, /*!< 16+34 EFR32 FPUEH Interrupt */
+ SMU_IRQn = 35, /*!< 16+35 EFR32 SMU Interrupt */
+ WTIMER0_IRQn = 36, /*!< 16+36 EFR32 WTIMER0 Interrupt */
+ WTIMER1_IRQn = 37, /*!< 16+37 EFR32 WTIMER1 Interrupt */
+ PCNT1_IRQn = 38, /*!< 16+38 EFR32 PCNT1 Interrupt */
+ PCNT2_IRQn = 39, /*!< 16+39 EFR32 PCNT2 Interrupt */
+ USART2_RX_IRQn = 40, /*!< 16+40 EFR32 USART2_RX Interrupt */
+ USART2_TX_IRQn = 41, /*!< 16+41 EFR32 USART2_TX Interrupt */
+ I2C1_IRQn = 42, /*!< 16+42 EFR32 I2C1 Interrupt */
+ USART3_RX_IRQn = 43, /*!< 16+43 EFR32 USART3_RX Interrupt */
+ USART3_TX_IRQn = 44, /*!< 16+44 EFR32 USART3_TX Interrupt */
+ VDAC0_IRQn = 45, /*!< 16+45 EFR32 VDAC0 Interrupt */
+ CSEN_IRQn = 46, /*!< 16+46 EFR32 CSEN Interrupt */
+ LESENSE_IRQn = 47, /*!< 16+47 EFR32 LESENSE Interrupt */
+ CRYPTO1_IRQn = 48, /*!< 16+48 EFR32 CRYPTO1 Interrupt */
+ TRNG0_IRQn = 49, /*!< 16+49 EFR32 TRNG0 Interrupt */
} IRQn_Type;
#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */
-/**************************************************************************//**
- * @defgroup EFR32FG12P231F1024GL125_Core EFR32FG12P231F1024GL125 Core
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F1024GL125_Core Core
* @{
* @brief Processor and Core Peripheral Section
- *****************************************************************************/
-#define __MPU_PRESENT 1 /**< Presence of MPU */
-#define __FPU_PRESENT 1 /**< Presence of FPU */
-#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
/** @} End of group EFR32FG12P231F1024GL125_Core */
-/**************************************************************************//**
-* @defgroup EFR32FG12P231F1024GL125_Part EFR32FG12P231F1024GL125 Part
-* @{
-******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F1024GL125_Part Part
+ * @{
+ ******************************************************************************/
/** Part family */
-#define _EFR32_FLEX_FAMILY 1 /**< FLEX Gecko RF SoC Family */
-#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
-#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
-#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */
-#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1
-#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2
-#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3
-#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ
-#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
-#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */
+#define _EFR32_FLEX_FAMILY 1 /**< FLEX Gecko RF SoC Family */
+#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
+#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /**< Radio type */
+#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */
/* If part number is not defined as compiler option, define it */
#if !defined(EFR32FG12P231F1024GL125)
@@ -153,179 +166,180 @@ typedef enum IRQn
#define PART_NUMBER "EFR32FG12P231F1024GL125" /**< Part Number */
/** Memory Base addresses and limits */
-#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */
-#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */
-#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */
-#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */
-#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */
-#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */
-#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */
-#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */
-#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */
-#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */
-#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */
-#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */
-#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */
-#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */
-#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
-#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
-#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */
-#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */
-#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */
-#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */
-#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */
-#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */
-#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */
-#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */
-#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */
-#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */
-#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */
-#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
-#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
-#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */
-#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */
-#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */
-#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */
-#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */
-#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
-#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
-#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
-#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
-#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
-#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */
-#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */
-#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */
-#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */
-#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */
-#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */
-#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */
-#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
-#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
-#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
-#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
-#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */
-#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */
-#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
-#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
-#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
-#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
-#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
-#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
-#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
-#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */
-#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */
-#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */
-#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */
-#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */
-#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */
-#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */
-#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */
-#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */
-#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */
-#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
-#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */
-#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */
-#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */
+#define CRYPTO1_BITCLR_MEM_BASE (0x440F0400UL) /**< CRYPTO1_BITCLR base address */
+#define CRYPTO1_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO1_BITCLR available address space */
+#define CRYPTO1_BITCLR_MEM_END (0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
+#define CRYPTO1_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
+#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */
+#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */
+#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */
+#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */
+#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */
+#define RAM2_MEM_SIZE (0x800UL) /**< RAM2 available address space */
+#define RAM2_MEM_END (0x200407FFUL) /**< RAM2 end address */
+#define RAM2_MEM_BITS (0x0000000BUL) /**< RAM2 used bits */
+#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */
+#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */
+#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
+#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
+#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
+#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
+#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
+#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
+#define CRYPTO1_MEM_BASE (0x400F0400UL) /**< CRYPTO1 base address */
+#define CRYPTO1_MEM_SIZE (0x400UL) /**< CRYPTO1 available address space */
+#define CRYPTO1_MEM_END (0x400F07FFUL) /**< CRYPTO1 end address */
+#define CRYPTO1_MEM_BITS (0x0000000AUL) /**< CRYPTO1 used bits */
+#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */
+#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */
+#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */
+#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
+#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
+#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
+#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
+#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */
+#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */
+#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */
+#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */
+#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */
+#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */
+#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */
+#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define CRYPTO1_BITSET_MEM_BASE (0x460F0400UL) /**< CRYPTO1_BITSET base address */
+#define CRYPTO1_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO1_BITSET available address space */
+#define CRYPTO1_BITSET_MEM_END (0x460F07FFUL) /**< CRYPTO1_BITSET end address */
+#define CRYPTO1_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITSET used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x20000UL) /**< RAM available address space */
+#define RAM_MEM_END (0x2001FFFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x00000011UL) /**< RAM used bits */
+#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */
+#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */
+#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */
+#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */
+#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
+#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
+#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
+#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xF0000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460EFFFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xF0000UL) /**< PER available address space */
+#define PER_MEM_END (0x400EFFFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */
+#define RAM2_CODE_MEM_SIZE (0x800UL) /**< RAM2_CODE available address space */
+#define RAM2_CODE_MEM_END (0x100407FFUL) /**< RAM2_CODE end address */
+#define RAM2_CODE_MEM_BITS (0x0000000BUL) /**< RAM2_CODE used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xF0000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440EFFFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
/** Bit banding area */
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
/** Flash and SRAM limits for EFR32FG12P231F1024GL125 */
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */
-#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size (interleaving off) */
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
-#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */
/** AF channels connect the different on-chip peripherals with the af-mux */
-#define AFCHAN_MAX 136
-#define AFCHANLOC_MAX 32
+#define AFCHAN_MAX 136U
+/** AF channel maximum location number */
+#define AFCHANLOC_MAX 32U
/** Analog AF channels */
-#define AFACHAN_MAX 125
+#define AFACHAN_MAX 125U
/* Part number capabilities */
-#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
-#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */
-#define TIMER_PRESENT /**< TIMER is available in this part */
-#define TIMER_COUNT 2 /**< 2 TIMERs available */
-#define WTIMER_PRESENT /**< WTIMER is available in this part */
-#define WTIMER_COUNT 2 /**< 2 WTIMERs available */
-#define USART_PRESENT /**< USART is available in this part */
-#define USART_COUNT 4 /**< 4 USARTs available */
-#define LEUART_PRESENT /**< LEUART is available in this part */
-#define LEUART_COUNT 1 /**< 1 LEUARTs available */
-#define LETIMER_PRESENT /**< LETIMER is available in this part */
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
-#define PCNT_PRESENT /**< PCNT is available in this part */
-#define PCNT_COUNT 3 /**< 3 PCNTs available */
-#define I2C_PRESENT /**< I2C is available in this part */
-#define I2C_COUNT 2 /**< 2 I2Cs available */
-#define ADC_PRESENT /**< ADC is available in this part */
-#define ADC_COUNT 1 /**< 1 ADCs available */
-#define ACMP_PRESENT /**< ACMP is available in this part */
-#define ACMP_COUNT 2 /**< 2 ACMPs available */
-#define IDAC_PRESENT /**< IDAC is available in this part */
-#define IDAC_COUNT 1 /**< 1 IDACs available */
-#define VDAC_PRESENT /**< VDAC is available in this part */
-#define VDAC_COUNT 1 /**< 1 VDACs available */
-#define WDOG_PRESENT /**< WDOG is available in this part */
-#define WDOG_COUNT 2 /**< 2 WDOGs available */
-#define TRNG_PRESENT /**< TRNG is available in this part */
-#define TRNG_COUNT 1 /**< 1 TRNGs available */
-#define SYSTICK_PRESENT
-#define SYSTICK_COUNT 1
-#define MSC_PRESENT
-#define MSC_COUNT 1
-#define EMU_PRESENT
-#define EMU_COUNT 1
-#define RMU_PRESENT
-#define RMU_COUNT 1
-#define CMU_PRESENT
-#define CMU_COUNT 1
-#define GPIO_PRESENT
-#define GPIO_COUNT 1
-#define PRS_PRESENT
-#define PRS_COUNT 1
-#define LDMA_PRESENT
-#define LDMA_COUNT 1
-#define FPUEH_PRESENT
-#define FPUEH_COUNT 1
-#define GPCRC_PRESENT
-#define GPCRC_COUNT 1
-#define CRYOTIMER_PRESENT
-#define CRYOTIMER_COUNT 1
-#define CSEN_PRESENT
-#define CSEN_COUNT 1
-#define LESENSE_PRESENT
-#define LESENSE_COUNT 1
-#define RTCC_PRESENT
-#define RTCC_COUNT 1
-#define ETM_PRESENT
-#define ETM_COUNT 1
-#define BOOTLOADER_PRESENT
-#define BOOTLOADER_COUNT 1
-#define SMU_PRESENT
-#define SMU_COUNT 1
-
-#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
-#include "system_efr32fg12p.h" /* System Header File */
+#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
+#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */
+#define TIMER_PRESENT /**< TIMER is available in this part */
+#define TIMER_COUNT 2 /**< 2 TIMERs available */
+#define WTIMER_PRESENT /**< WTIMER is available in this part */
+#define WTIMER_COUNT 2 /**< 2 WTIMERs available */
+#define USART_PRESENT /**< USART is available in this part */
+#define USART_COUNT 4 /**< 4 USARTs available */
+#define LEUART_PRESENT /**< LEUART is available in this part */
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */
+#define LETIMER_PRESENT /**< LETIMER is available in this part */
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
+#define PCNT_PRESENT /**< PCNT is available in this part */
+#define PCNT_COUNT 3 /**< 3 PCNTs available */
+#define I2C_PRESENT /**< I2C is available in this part */
+#define I2C_COUNT 2 /**< 2 I2Cs available */
+#define ADC_PRESENT /**< ADC is available in this part */
+#define ADC_COUNT 1 /**< 1 ADCs available */
+#define ACMP_PRESENT /**< ACMP is available in this part */
+#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
+#define VDAC_PRESENT /**< VDAC is available in this part */
+#define VDAC_COUNT 1 /**< 1 VDACs available */
+#define WDOG_PRESENT /**< WDOG is available in this part */
+#define WDOG_COUNT 2 /**< 2 WDOGs available */
+#define TRNG_PRESENT /**< TRNG is available in this part */
+#define TRNG_COUNT 1 /**< 1 TRNGs available */
+#define MSC_PRESENT /**< MSC is available in this part */
+#define MSC_COUNT 1 /**< 1 MSC available */
+#define EMU_PRESENT /**< EMU is available in this part */
+#define EMU_COUNT 1 /**< 1 EMU available */
+#define RMU_PRESENT /**< RMU is available in this part */
+#define RMU_COUNT 1 /**< 1 RMU available */
+#define CMU_PRESENT /**< CMU is available in this part */
+#define CMU_COUNT 1 /**< 1 CMU available */
+#define GPIO_PRESENT /**< GPIO is available in this part */
+#define GPIO_COUNT 1 /**< 1 GPIO available */
+#define PRS_PRESENT /**< PRS is available in this part */
+#define PRS_COUNT 1 /**< 1 PRS available */
+#define LDMA_PRESENT /**< LDMA is available in this part */
+#define LDMA_COUNT 1 /**< 1 LDMA available */
+#define FPUEH_PRESENT /**< FPUEH is available in this part */
+#define FPUEH_COUNT 1 /**< 1 FPUEH available */
+#define GPCRC_PRESENT /**< GPCRC is available in this part */
+#define GPCRC_COUNT 1 /**< 1 GPCRC available */
+#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
+#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
+#define CSEN_PRESENT /**< CSEN is available in this part */
+#define CSEN_COUNT 1 /**< 1 CSEN available */
+#define LESENSE_PRESENT /**< LESENSE is available in this part */
+#define LESENSE_COUNT 1 /**< 1 LESENSE available */
+#define RTCC_PRESENT /**< RTCC is available in this part */
+#define RTCC_COUNT 1 /**< 1 RTCC available */
+#define ETM_PRESENT /**< ETM is available in this part */
+#define ETM_COUNT 1 /**< 1 ETM available */
+#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
+#define SMU_PRESENT /**< SMU is available in this part */
+#define SMU_COUNT 1 /**< 1 SMU available */
+#define DCDC_PRESENT /**< DCDC is available in this part */
+#define DCDC_COUNT 1 /**< 1 DCDC available */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32fg12p.h" /* System Header File */
/** @} End of group EFR32FG12P231F1024GL125_Part */
-/**************************************************************************//**
- * @defgroup EFR32FG12P231F1024GL125_Peripheral_TypeDefs EFR32FG12P231F1024GL125 Peripheral TypeDefs
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F1024GL125_Peripheral_TypeDefs Peripheral TypeDefs
* @{
* @brief Device Specific Peripheral Register Structures
- *****************************************************************************/
+ ******************************************************************************/
#include "efr32fg12p_msc.h"
#include "efr32fg12p_emu.h"
@@ -372,10 +386,10 @@ typedef enum IRQn
/** @} End of group EFR32FG12P231F1024GL125_Peripheral_TypeDefs */
-/**************************************************************************//**
- * @defgroup EFR32FG12P231F1024GL125_Peripheral_Base EFR32FG12P231F1024GL125 Peripheral Memory Map
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F1024GL125_Peripheral_Base Peripheral Memory Map
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC_BASE (0x400E0000UL) /**< MSC base address */
#define EMU_BASE (0x400E3000UL) /**< EMU base address */
@@ -425,10 +439,10 @@ typedef enum IRQn
/** @} End of group EFR32FG12P231F1024GL125_Peripheral_Base */
-/**************************************************************************//**
- * @defgroup EFR32FG12P231F1024GL125_Peripheral_Declaration EFR32FG12P231F1024GL125 Peripheral Declarations
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F1024GL125_Peripheral_Declaration Peripheral Declarations
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
@@ -476,10 +490,10 @@ typedef enum IRQn
/** @} End of group EFR32FG12P231F1024GL125_Peripheral_Declaration */
-/**************************************************************************//**
- * @defgroup EFR32FG12P231F1024GL125_Peripheral_Offsets EFR32FG12P231F1024GL125 Peripheral Offsets
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F1024GL125_Peripheral_Offsets Peripheral Offsets
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */
#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
@@ -498,19 +512,20 @@ typedef enum IRQn
/** @} End of group EFR32FG12P231F1024GL125_Peripheral_Offsets */
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P231F1024GL125_BitFields EFR32FG12P231F1024GL125 Bit Fields
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F1024GL125_BitFields Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
#include "efr32fg12p_prs_signals.h"
#include "efr32fg12p_dmareq.h"
-/**************************************************************************//**
- * @defgroup EFR32FG12P231F1024GL125_WTIMER_BitFields EFR32FG12P231F1024GL125_WTIMER Bit Fields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P231F1024GL125_WTIMER
+ * @{
+ * @defgroup EFR32FG12P231F1024GL125_WTIMER_BitFields WTIMER Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for WTIMER CTRL */
#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */
@@ -626,7 +641,7 @@ typedef enum IRQn
#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */
#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */
+#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */
#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */
#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */
#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
@@ -1011,13 +1026,13 @@ typedef enum IRQn
#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */
-#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */
+#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */
-#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */
+#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */
@@ -1731,7 +1746,7 @@ typedef enum IRQn
#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */
#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */
+#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */
#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */
#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */
#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
@@ -1998,33 +2013,23 @@ typedef enum IRQn
#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */
-#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */
+#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */
-#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */
+#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */
+/** @} */
/** @} End of group EFR32FG12P231F1024GL125_WTIMER */
-
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P231F1024GL125_SYSTICK_BitFields EFR32FG12P231F1024GL125_SYSTICK Bit Fields
- * @{
- *****************************************************************************/
-
-/** @} End of group EFR32FG12P231F1024GL125_SYSTICK */
-
-
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P231F1024GL125_UNLOCK EFR32FG12P231F1024GL125 Unlock Codes
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F1024GL125_UNLOCK Unlock Codes
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
@@ -2037,16 +2042,9 @@ typedef enum IRQn
/** @} End of group EFR32FG12P231F1024GL125_BitFields */
-/**************************************************************************//**
- * @defgroup EFR32FG12P231F1024GL125_Alternate_Function EFR32FG12P231F1024GL125 Alternate Function
- * @{
- *****************************************************************************/
-
#include "efr32fg12p_af_ports.h"
#include "efr32fg12p_af_pins.h"
-/** @} End of group EFR32FG12P231F1024GL125_Alternate_Function */
-
/** @} End of group EFR32FG12P231F1024GL125 */
/** @} End of group Parts */
@@ -2054,4 +2052,5 @@ typedef enum IRQn
#ifdef __cplusplus
}
#endif
+
#endif /* EFR32FG12P231F1024GL125_H */
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p231f1024gm48.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p231f1024gm48.h
similarity index 91%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p231f1024gm48.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p231f1024gm48.h
index 0f3f7b6f..05d3ca2c 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p231f1024gm48.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p231f1024gm48.h
@@ -1,35 +1,39 @@
-/**************************************************************************//**
- * @file efr32fg12p231f1024gm48.h
+/***************************************************************************//**
+ * @file
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
* for EFR32FG12P231F1024GM48
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
#ifndef EFR32FG12P231F1024GM48_H
#define EFR32FG12P231F1024GM48_H
@@ -38,111 +42,120 @@
extern "C" {
#endif
-/**************************************************************************//**
+/***************************************************************************//**
* @addtogroup Parts
* @{
- *****************************************************************************/
+ ******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFR32FG12P231F1024GM48 EFR32FG12P231F1024GM48
* @{
- *****************************************************************************/
+ ******************************************************************************/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
+typedef enum IRQn{
/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
- NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */
- HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */
- MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
/****** EFR32FG12P Peripheral Interrupt Numbers ********************************************/
- EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */
- WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */
- WDOG1_IRQn = 3, /*!< 3 EFR32 WDOG1 Interrupt */
- LDMA_IRQn = 9, /*!< 9 EFR32 LDMA Interrupt */
- GPIO_EVEN_IRQn = 10, /*!< 10 EFR32 GPIO_EVEN Interrupt */
- TIMER0_IRQn = 11, /*!< 11 EFR32 TIMER0 Interrupt */
- USART0_RX_IRQn = 12, /*!< 12 EFR32 USART0_RX Interrupt */
- USART0_TX_IRQn = 13, /*!< 13 EFR32 USART0_TX Interrupt */
- ACMP0_IRQn = 14, /*!< 14 EFR32 ACMP0 Interrupt */
- ADC0_IRQn = 15, /*!< 15 EFR32 ADC0 Interrupt */
- IDAC0_IRQn = 16, /*!< 16 EFR32 IDAC0 Interrupt */
- I2C0_IRQn = 17, /*!< 17 EFR32 I2C0 Interrupt */
- GPIO_ODD_IRQn = 18, /*!< 18 EFR32 GPIO_ODD Interrupt */
- TIMER1_IRQn = 19, /*!< 19 EFR32 TIMER1 Interrupt */
- USART1_RX_IRQn = 20, /*!< 20 EFR32 USART1_RX Interrupt */
- USART1_TX_IRQn = 21, /*!< 21 EFR32 USART1_TX Interrupt */
- LEUART0_IRQn = 22, /*!< 22 EFR32 LEUART0 Interrupt */
- PCNT0_IRQn = 23, /*!< 23 EFR32 PCNT0 Interrupt */
- CMU_IRQn = 24, /*!< 24 EFR32 CMU Interrupt */
- MSC_IRQn = 25, /*!< 25 EFR32 MSC Interrupt */
- CRYPTO0_IRQn = 26, /*!< 26 EFR32 CRYPTO0 Interrupt */
- LETIMER0_IRQn = 27, /*!< 27 EFR32 LETIMER0 Interrupt */
- RTCC_IRQn = 30, /*!< 30 EFR32 RTCC Interrupt */
- CRYOTIMER_IRQn = 32, /*!< 32 EFR32 CRYOTIMER Interrupt */
- FPUEH_IRQn = 34, /*!< 34 EFR32 FPUEH Interrupt */
- SMU_IRQn = 35, /*!< 35 EFR32 SMU Interrupt */
- WTIMER0_IRQn = 36, /*!< 36 EFR32 WTIMER0 Interrupt */
- WTIMER1_IRQn = 37, /*!< 37 EFR32 WTIMER1 Interrupt */
- PCNT1_IRQn = 38, /*!< 38 EFR32 PCNT1 Interrupt */
- PCNT2_IRQn = 39, /*!< 39 EFR32 PCNT2 Interrupt */
- USART2_RX_IRQn = 40, /*!< 40 EFR32 USART2_RX Interrupt */
- USART2_TX_IRQn = 41, /*!< 41 EFR32 USART2_TX Interrupt */
- I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */
- USART3_RX_IRQn = 43, /*!< 43 EFR32 USART3_RX Interrupt */
- USART3_TX_IRQn = 44, /*!< 44 EFR32 USART3_TX Interrupt */
- VDAC0_IRQn = 45, /*!< 45 EFR32 VDAC0 Interrupt */
- CSEN_IRQn = 46, /*!< 46 EFR32 CSEN Interrupt */
- LESENSE_IRQn = 47, /*!< 47 EFR32 LESENSE Interrupt */
- CRYPTO1_IRQn = 48, /*!< 48 EFR32 CRYPTO1 Interrupt */
- TRNG0_IRQn = 49, /*!< 49 EFR32 TRNG0 Interrupt */
+ EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
+ WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 3, /*!< 16+3 EFR32 WDOG1 Interrupt */
+ FRC_IRQn = 4, /*!< 16+4 EFR32 FRC Interrupt */
+ MODEM_IRQn = 5, /*!< 16+5 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 6, /*!< 16+6 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 7, /*!< 16+7 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 8, /*!< 16+8 EFR32 BUFC Interrupt */
+ LDMA_IRQn = 9, /*!< 16+9 EFR32 LDMA Interrupt */
+ GPIO_EVEN_IRQn = 10, /*!< 16+10 EFR32 GPIO_EVEN Interrupt */
+ TIMER0_IRQn = 11, /*!< 16+11 EFR32 TIMER0 Interrupt */
+ USART0_RX_IRQn = 12, /*!< 16+12 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 13, /*!< 16+13 EFR32 USART0_TX Interrupt */
+ ACMP0_IRQn = 14, /*!< 16+14 EFR32 ACMP0 Interrupt */
+ ADC0_IRQn = 15, /*!< 16+15 EFR32 ADC0 Interrupt */
+ IDAC0_IRQn = 16, /*!< 16+16 EFR32 IDAC0 Interrupt */
+ I2C0_IRQn = 17, /*!< 16+17 EFR32 I2C0 Interrupt */
+ GPIO_ODD_IRQn = 18, /*!< 16+18 EFR32 GPIO_ODD Interrupt */
+ TIMER1_IRQn = 19, /*!< 16+19 EFR32 TIMER1 Interrupt */
+ USART1_RX_IRQn = 20, /*!< 16+20 EFR32 USART1_RX Interrupt */
+ USART1_TX_IRQn = 21, /*!< 16+21 EFR32 USART1_TX Interrupt */
+ LEUART0_IRQn = 22, /*!< 16+22 EFR32 LEUART0 Interrupt */
+ PCNT0_IRQn = 23, /*!< 16+23 EFR32 PCNT0 Interrupt */
+ CMU_IRQn = 24, /*!< 16+24 EFR32 CMU Interrupt */
+ MSC_IRQn = 25, /*!< 16+25 EFR32 MSC Interrupt */
+ CRYPTO0_IRQn = 26, /*!< 16+26 EFR32 CRYPTO0 Interrupt */
+ LETIMER0_IRQn = 27, /*!< 16+27 EFR32 LETIMER0 Interrupt */
+ AGC_IRQn = 28, /*!< 16+28 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 29, /*!< 16+29 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 30, /*!< 16+30 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 31, /*!< 16+31 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 32, /*!< 16+32 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 33, /*!< 16+33 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 34, /*!< 16+34 EFR32 FPUEH Interrupt */
+ SMU_IRQn = 35, /*!< 16+35 EFR32 SMU Interrupt */
+ WTIMER0_IRQn = 36, /*!< 16+36 EFR32 WTIMER0 Interrupt */
+ WTIMER1_IRQn = 37, /*!< 16+37 EFR32 WTIMER1 Interrupt */
+ PCNT1_IRQn = 38, /*!< 16+38 EFR32 PCNT1 Interrupt */
+ PCNT2_IRQn = 39, /*!< 16+39 EFR32 PCNT2 Interrupt */
+ USART2_RX_IRQn = 40, /*!< 16+40 EFR32 USART2_RX Interrupt */
+ USART2_TX_IRQn = 41, /*!< 16+41 EFR32 USART2_TX Interrupt */
+ I2C1_IRQn = 42, /*!< 16+42 EFR32 I2C1 Interrupt */
+ USART3_RX_IRQn = 43, /*!< 16+43 EFR32 USART3_RX Interrupt */
+ USART3_TX_IRQn = 44, /*!< 16+44 EFR32 USART3_TX Interrupt */
+ VDAC0_IRQn = 45, /*!< 16+45 EFR32 VDAC0 Interrupt */
+ CSEN_IRQn = 46, /*!< 16+46 EFR32 CSEN Interrupt */
+ LESENSE_IRQn = 47, /*!< 16+47 EFR32 LESENSE Interrupt */
+ CRYPTO1_IRQn = 48, /*!< 16+48 EFR32 CRYPTO1 Interrupt */
+ TRNG0_IRQn = 49, /*!< 16+49 EFR32 TRNG0 Interrupt */
} IRQn_Type;
#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */
-/**************************************************************************//**
- * @defgroup EFR32FG12P231F1024GM48_Core EFR32FG12P231F1024GM48 Core
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F1024GM48_Core Core
* @{
* @brief Processor and Core Peripheral Section
- *****************************************************************************/
-#define __MPU_PRESENT 1 /**< Presence of MPU */
-#define __FPU_PRESENT 1 /**< Presence of FPU */
-#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
/** @} End of group EFR32FG12P231F1024GM48_Core */
-/**************************************************************************//**
-* @defgroup EFR32FG12P231F1024GM48_Part EFR32FG12P231F1024GM48 Part
-* @{
-******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F1024GM48_Part Part
+ * @{
+ ******************************************************************************/
/** Part family */
-#define _EFR32_FLEX_FAMILY 1 /**< FLEX Gecko RF SoC Family */
-#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
-#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
-#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */
-#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1
-#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2
-#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3
-#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ
-#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
-#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */
+#define _EFR32_FLEX_FAMILY 1 /**< FLEX Gecko RF SoC Family */
+#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
+#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /**< Radio type */
+#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */
/* If part number is not defined as compiler option, define it */
#if !defined(EFR32FG12P231F1024GM48)
@@ -153,179 +166,180 @@ typedef enum IRQn
#define PART_NUMBER "EFR32FG12P231F1024GM48" /**< Part Number */
/** Memory Base addresses and limits */
-#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */
-#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */
-#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */
-#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */
-#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */
-#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */
-#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */
-#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */
-#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */
-#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */
-#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */
-#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */
-#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */
-#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */
-#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
-#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
-#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */
-#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */
-#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */
-#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */
-#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */
-#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */
-#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */
-#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */
-#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */
-#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */
-#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */
-#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
-#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
-#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */
-#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */
-#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */
-#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */
-#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */
-#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
-#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
-#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
-#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
-#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
-#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */
-#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */
-#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */
-#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */
-#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */
-#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */
-#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */
-#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
-#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
-#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
-#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
-#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */
-#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */
-#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
-#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
-#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
-#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
-#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
-#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
-#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
-#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */
-#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */
-#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */
-#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */
-#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */
-#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */
-#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */
-#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */
-#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */
-#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */
-#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
-#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */
-#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */
-#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */
+#define CRYPTO1_BITCLR_MEM_BASE (0x440F0400UL) /**< CRYPTO1_BITCLR base address */
+#define CRYPTO1_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO1_BITCLR available address space */
+#define CRYPTO1_BITCLR_MEM_END (0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
+#define CRYPTO1_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
+#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */
+#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */
+#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */
+#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */
+#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */
+#define RAM2_MEM_SIZE (0x800UL) /**< RAM2 available address space */
+#define RAM2_MEM_END (0x200407FFUL) /**< RAM2 end address */
+#define RAM2_MEM_BITS (0x0000000BUL) /**< RAM2 used bits */
+#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */
+#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */
+#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
+#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
+#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
+#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
+#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
+#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
+#define CRYPTO1_MEM_BASE (0x400F0400UL) /**< CRYPTO1 base address */
+#define CRYPTO1_MEM_SIZE (0x400UL) /**< CRYPTO1 available address space */
+#define CRYPTO1_MEM_END (0x400F07FFUL) /**< CRYPTO1 end address */
+#define CRYPTO1_MEM_BITS (0x0000000AUL) /**< CRYPTO1 used bits */
+#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */
+#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */
+#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */
+#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
+#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
+#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
+#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
+#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */
+#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */
+#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */
+#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */
+#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */
+#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */
+#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */
+#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define CRYPTO1_BITSET_MEM_BASE (0x460F0400UL) /**< CRYPTO1_BITSET base address */
+#define CRYPTO1_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO1_BITSET available address space */
+#define CRYPTO1_BITSET_MEM_END (0x460F07FFUL) /**< CRYPTO1_BITSET end address */
+#define CRYPTO1_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITSET used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x20000UL) /**< RAM available address space */
+#define RAM_MEM_END (0x2001FFFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x00000011UL) /**< RAM used bits */
+#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */
+#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */
+#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */
+#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */
+#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
+#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
+#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
+#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xF0000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460EFFFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xF0000UL) /**< PER available address space */
+#define PER_MEM_END (0x400EFFFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */
+#define RAM2_CODE_MEM_SIZE (0x800UL) /**< RAM2_CODE available address space */
+#define RAM2_CODE_MEM_END (0x100407FFUL) /**< RAM2_CODE end address */
+#define RAM2_CODE_MEM_BITS (0x0000000BUL) /**< RAM2_CODE used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xF0000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440EFFFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
/** Bit banding area */
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
/** Flash and SRAM limits for EFR32FG12P231F1024GM48 */
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */
-#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size (interleaving off) */
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
-#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */
/** AF channels connect the different on-chip peripherals with the af-mux */
-#define AFCHAN_MAX 136
-#define AFCHANLOC_MAX 32
+#define AFCHAN_MAX 136U
+/** AF channel maximum location number */
+#define AFCHANLOC_MAX 32U
/** Analog AF channels */
-#define AFACHAN_MAX 125
+#define AFACHAN_MAX 125U
/* Part number capabilities */
-#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
-#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */
-#define TIMER_PRESENT /**< TIMER is available in this part */
-#define TIMER_COUNT 2 /**< 2 TIMERs available */
-#define WTIMER_PRESENT /**< WTIMER is available in this part */
-#define WTIMER_COUNT 2 /**< 2 WTIMERs available */
-#define USART_PRESENT /**< USART is available in this part */
-#define USART_COUNT 4 /**< 4 USARTs available */
-#define LEUART_PRESENT /**< LEUART is available in this part */
-#define LEUART_COUNT 1 /**< 1 LEUARTs available */
-#define LETIMER_PRESENT /**< LETIMER is available in this part */
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
-#define PCNT_PRESENT /**< PCNT is available in this part */
-#define PCNT_COUNT 3 /**< 3 PCNTs available */
-#define I2C_PRESENT /**< I2C is available in this part */
-#define I2C_COUNT 2 /**< 2 I2Cs available */
-#define ADC_PRESENT /**< ADC is available in this part */
-#define ADC_COUNT 1 /**< 1 ADCs available */
-#define ACMP_PRESENT /**< ACMP is available in this part */
-#define ACMP_COUNT 2 /**< 2 ACMPs available */
-#define IDAC_PRESENT /**< IDAC is available in this part */
-#define IDAC_COUNT 1 /**< 1 IDACs available */
-#define VDAC_PRESENT /**< VDAC is available in this part */
-#define VDAC_COUNT 1 /**< 1 VDACs available */
-#define WDOG_PRESENT /**< WDOG is available in this part */
-#define WDOG_COUNT 2 /**< 2 WDOGs available */
-#define TRNG_PRESENT /**< TRNG is available in this part */
-#define TRNG_COUNT 1 /**< 1 TRNGs available */
-#define SYSTICK_PRESENT
-#define SYSTICK_COUNT 1
-#define MSC_PRESENT
-#define MSC_COUNT 1
-#define EMU_PRESENT
-#define EMU_COUNT 1
-#define RMU_PRESENT
-#define RMU_COUNT 1
-#define CMU_PRESENT
-#define CMU_COUNT 1
-#define GPIO_PRESENT
-#define GPIO_COUNT 1
-#define PRS_PRESENT
-#define PRS_COUNT 1
-#define LDMA_PRESENT
-#define LDMA_COUNT 1
-#define FPUEH_PRESENT
-#define FPUEH_COUNT 1
-#define GPCRC_PRESENT
-#define GPCRC_COUNT 1
-#define CRYOTIMER_PRESENT
-#define CRYOTIMER_COUNT 1
-#define CSEN_PRESENT
-#define CSEN_COUNT 1
-#define LESENSE_PRESENT
-#define LESENSE_COUNT 1
-#define RTCC_PRESENT
-#define RTCC_COUNT 1
-#define ETM_PRESENT
-#define ETM_COUNT 1
-#define BOOTLOADER_PRESENT
-#define BOOTLOADER_COUNT 1
-#define SMU_PRESENT
-#define SMU_COUNT 1
-
-#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
-#include "system_efr32fg12p.h" /* System Header File */
+#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
+#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */
+#define TIMER_PRESENT /**< TIMER is available in this part */
+#define TIMER_COUNT 2 /**< 2 TIMERs available */
+#define WTIMER_PRESENT /**< WTIMER is available in this part */
+#define WTIMER_COUNT 2 /**< 2 WTIMERs available */
+#define USART_PRESENT /**< USART is available in this part */
+#define USART_COUNT 4 /**< 4 USARTs available */
+#define LEUART_PRESENT /**< LEUART is available in this part */
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */
+#define LETIMER_PRESENT /**< LETIMER is available in this part */
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
+#define PCNT_PRESENT /**< PCNT is available in this part */
+#define PCNT_COUNT 3 /**< 3 PCNTs available */
+#define I2C_PRESENT /**< I2C is available in this part */
+#define I2C_COUNT 2 /**< 2 I2Cs available */
+#define ADC_PRESENT /**< ADC is available in this part */
+#define ADC_COUNT 1 /**< 1 ADCs available */
+#define ACMP_PRESENT /**< ACMP is available in this part */
+#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
+#define VDAC_PRESENT /**< VDAC is available in this part */
+#define VDAC_COUNT 1 /**< 1 VDACs available */
+#define WDOG_PRESENT /**< WDOG is available in this part */
+#define WDOG_COUNT 2 /**< 2 WDOGs available */
+#define TRNG_PRESENT /**< TRNG is available in this part */
+#define TRNG_COUNT 1 /**< 1 TRNGs available */
+#define MSC_PRESENT /**< MSC is available in this part */
+#define MSC_COUNT 1 /**< 1 MSC available */
+#define EMU_PRESENT /**< EMU is available in this part */
+#define EMU_COUNT 1 /**< 1 EMU available */
+#define RMU_PRESENT /**< RMU is available in this part */
+#define RMU_COUNT 1 /**< 1 RMU available */
+#define CMU_PRESENT /**< CMU is available in this part */
+#define CMU_COUNT 1 /**< 1 CMU available */
+#define GPIO_PRESENT /**< GPIO is available in this part */
+#define GPIO_COUNT 1 /**< 1 GPIO available */
+#define PRS_PRESENT /**< PRS is available in this part */
+#define PRS_COUNT 1 /**< 1 PRS available */
+#define LDMA_PRESENT /**< LDMA is available in this part */
+#define LDMA_COUNT 1 /**< 1 LDMA available */
+#define FPUEH_PRESENT /**< FPUEH is available in this part */
+#define FPUEH_COUNT 1 /**< 1 FPUEH available */
+#define GPCRC_PRESENT /**< GPCRC is available in this part */
+#define GPCRC_COUNT 1 /**< 1 GPCRC available */
+#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
+#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
+#define CSEN_PRESENT /**< CSEN is available in this part */
+#define CSEN_COUNT 1 /**< 1 CSEN available */
+#define LESENSE_PRESENT /**< LESENSE is available in this part */
+#define LESENSE_COUNT 1 /**< 1 LESENSE available */
+#define RTCC_PRESENT /**< RTCC is available in this part */
+#define RTCC_COUNT 1 /**< 1 RTCC available */
+#define ETM_PRESENT /**< ETM is available in this part */
+#define ETM_COUNT 1 /**< 1 ETM available */
+#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
+#define SMU_PRESENT /**< SMU is available in this part */
+#define SMU_COUNT 1 /**< 1 SMU available */
+#define DCDC_PRESENT /**< DCDC is available in this part */
+#define DCDC_COUNT 1 /**< 1 DCDC available */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32fg12p.h" /* System Header File */
/** @} End of group EFR32FG12P231F1024GM48_Part */
-/**************************************************************************//**
- * @defgroup EFR32FG12P231F1024GM48_Peripheral_TypeDefs EFR32FG12P231F1024GM48 Peripheral TypeDefs
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F1024GM48_Peripheral_TypeDefs Peripheral TypeDefs
* @{
* @brief Device Specific Peripheral Register Structures
- *****************************************************************************/
+ ******************************************************************************/
#include "efr32fg12p_msc.h"
#include "efr32fg12p_emu.h"
@@ -372,10 +386,10 @@ typedef enum IRQn
/** @} End of group EFR32FG12P231F1024GM48_Peripheral_TypeDefs */
-/**************************************************************************//**
- * @defgroup EFR32FG12P231F1024GM48_Peripheral_Base EFR32FG12P231F1024GM48 Peripheral Memory Map
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F1024GM48_Peripheral_Base Peripheral Memory Map
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC_BASE (0x400E0000UL) /**< MSC base address */
#define EMU_BASE (0x400E3000UL) /**< EMU base address */
@@ -425,10 +439,10 @@ typedef enum IRQn
/** @} End of group EFR32FG12P231F1024GM48_Peripheral_Base */
-/**************************************************************************//**
- * @defgroup EFR32FG12P231F1024GM48_Peripheral_Declaration EFR32FG12P231F1024GM48 Peripheral Declarations
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F1024GM48_Peripheral_Declaration Peripheral Declarations
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
@@ -476,10 +490,10 @@ typedef enum IRQn
/** @} End of group EFR32FG12P231F1024GM48_Peripheral_Declaration */
-/**************************************************************************//**
- * @defgroup EFR32FG12P231F1024GM48_Peripheral_Offsets EFR32FG12P231F1024GM48 Peripheral Offsets
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F1024GM48_Peripheral_Offsets Peripheral Offsets
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */
#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
@@ -498,19 +512,20 @@ typedef enum IRQn
/** @} End of group EFR32FG12P231F1024GM48_Peripheral_Offsets */
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P231F1024GM48_BitFields EFR32FG12P231F1024GM48 Bit Fields
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F1024GM48_BitFields Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
#include "efr32fg12p_prs_signals.h"
#include "efr32fg12p_dmareq.h"
-/**************************************************************************//**
- * @defgroup EFR32FG12P231F1024GM48_WTIMER_BitFields EFR32FG12P231F1024GM48_WTIMER Bit Fields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P231F1024GM48_WTIMER
+ * @{
+ * @defgroup EFR32FG12P231F1024GM48_WTIMER_BitFields WTIMER Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for WTIMER CTRL */
#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */
@@ -626,7 +641,7 @@ typedef enum IRQn
#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */
#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */
+#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */
#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */
#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */
#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
@@ -1011,13 +1026,13 @@ typedef enum IRQn
#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */
-#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */
+#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */
-#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */
+#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */
@@ -1731,7 +1746,7 @@ typedef enum IRQn
#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */
#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */
+#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */
#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */
#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */
#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
@@ -1998,33 +2013,23 @@ typedef enum IRQn
#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */
-#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */
+#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */
-#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */
+#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */
+/** @} */
/** @} End of group EFR32FG12P231F1024GM48_WTIMER */
-
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P231F1024GM48_SYSTICK_BitFields EFR32FG12P231F1024GM48_SYSTICK Bit Fields
- * @{
- *****************************************************************************/
-
-/** @} End of group EFR32FG12P231F1024GM48_SYSTICK */
-
-
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P231F1024GM48_UNLOCK EFR32FG12P231F1024GM48 Unlock Codes
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F1024GM48_UNLOCK Unlock Codes
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
@@ -2037,16 +2042,9 @@ typedef enum IRQn
/** @} End of group EFR32FG12P231F1024GM48_BitFields */
-/**************************************************************************//**
- * @defgroup EFR32FG12P231F1024GM48_Alternate_Function EFR32FG12P231F1024GM48 Alternate Function
- * @{
- *****************************************************************************/
-
#include "efr32fg12p_af_ports.h"
#include "efr32fg12p_af_pins.h"
-/** @} End of group EFR32FG12P231F1024GM48_Alternate_Function */
-
/** @} End of group EFR32FG12P231F1024GM48 */
/** @} End of group Parts */
@@ -2054,4 +2052,5 @@ typedef enum IRQn
#ifdef __cplusplus
}
#endif
+
#endif /* EFR32FG12P231F1024GM48_H */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p231f512im32.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p231f1024gm68.h
similarity index 92%
rename from mcu/efr/common/vendor/efr32fg13/efr32fg13p231f512im32.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p231f1024gm68.h
index a75f7918..c21b0632 100644
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p231f512im32.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p231f1024gm68.h
@@ -1,35 +1,33 @@
-/**************************************************************************//**
- * @file efr32fg13p231f512im32.h
+/***************************************************************************//**
+ * @file
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
- * for EFR32FG13P231F512IM32
- * @version 5.4.0
- ******************************************************************************
+ * for EFR32FG12P231F1024GM68
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#if defined(__ICCARM__)
#pragma system_include /* Treat file as system include file. */
@@ -37,22 +35,22 @@
#pragma clang system_header /* Treat file as system include file. */
#endif
-#ifndef EFR32FG13P231F512IM32_H
-#define EFR32FG13P231F512IM32_H
+#ifndef EFR32FG12P231F1024GM68_H
+#define EFR32FG12P231F1024GM68_H
#ifdef __cplusplus
extern "C" {
#endif
-/**************************************************************************//**
+/***************************************************************************//**
* @addtogroup Parts
* @{
- *****************************************************************************/
+ ******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512IM32 EFR32FG13P231F512IM32
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F1024GM68 EFR32FG12P231F1024GM68
* @{
- *****************************************************************************/
+ ******************************************************************************/
/** Interrupt Number Definition */
typedef enum IRQn{
@@ -67,11 +65,17 @@ typedef enum IRQn{
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
-/****** EFR32FG13P Peripheral Interrupt Numbers ********************************************/
+/****** EFR32FG12P Peripheral Interrupt Numbers ********************************************/
EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
WDOG1_IRQn = 3, /*!< 16+3 EFR32 WDOG1 Interrupt */
+ FRC_IRQn = 4, /*!< 16+4 EFR32 FRC Interrupt */
+ MODEM_IRQn = 5, /*!< 16+5 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 6, /*!< 16+6 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 7, /*!< 16+7 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 8, /*!< 16+8 EFR32 BUFC Interrupt */
LDMA_IRQn = 9, /*!< 16+9 EFR32 LDMA Interrupt */
GPIO_EVEN_IRQn = 10, /*!< 16+10 EFR32 GPIO_EVEN Interrupt */
TIMER0_IRQn = 11, /*!< 16+11 EFR32 TIMER0 Interrupt */
@@ -91,166 +95,175 @@ typedef enum IRQn{
MSC_IRQn = 25, /*!< 16+25 EFR32 MSC Interrupt */
CRYPTO0_IRQn = 26, /*!< 16+26 EFR32 CRYPTO0 Interrupt */
LETIMER0_IRQn = 27, /*!< 16+27 EFR32 LETIMER0 Interrupt */
- RTCC_IRQn = 31, /*!< 16+31 EFR32 RTCC Interrupt */
- CRYOTIMER_IRQn = 33, /*!< 16+33 EFR32 CRYOTIMER Interrupt */
- FPUEH_IRQn = 35, /*!< 16+35 EFR32 FPUEH Interrupt */
- SMU_IRQn = 36, /*!< 16+36 EFR32 SMU Interrupt */
- WTIMER0_IRQn = 37, /*!< 16+37 EFR32 WTIMER0 Interrupt */
- USART2_RX_IRQn = 38, /*!< 16+38 EFR32 USART2_RX Interrupt */
- USART2_TX_IRQn = 39, /*!< 16+39 EFR32 USART2_TX Interrupt */
- I2C1_IRQn = 40, /*!< 16+40 EFR32 I2C1 Interrupt */
- VDAC0_IRQn = 41, /*!< 16+41 EFR32 VDAC0 Interrupt */
- CSEN_IRQn = 42, /*!< 16+42 EFR32 CSEN Interrupt */
- LESENSE_IRQn = 43, /*!< 16+43 EFR32 LESENSE Interrupt */
- CRYPTO1_IRQn = 44, /*!< 16+44 EFR32 CRYPTO1 Interrupt */
- TRNG0_IRQn = 45, /*!< 16+45 EFR32 TRNG0 Interrupt */
+ AGC_IRQn = 28, /*!< 16+28 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 29, /*!< 16+29 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 30, /*!< 16+30 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 31, /*!< 16+31 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 32, /*!< 16+32 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 33, /*!< 16+33 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 34, /*!< 16+34 EFR32 FPUEH Interrupt */
+ SMU_IRQn = 35, /*!< 16+35 EFR32 SMU Interrupt */
+ WTIMER0_IRQn = 36, /*!< 16+36 EFR32 WTIMER0 Interrupt */
+ WTIMER1_IRQn = 37, /*!< 16+37 EFR32 WTIMER1 Interrupt */
+ PCNT1_IRQn = 38, /*!< 16+38 EFR32 PCNT1 Interrupt */
+ PCNT2_IRQn = 39, /*!< 16+39 EFR32 PCNT2 Interrupt */
+ USART2_RX_IRQn = 40, /*!< 16+40 EFR32 USART2_RX Interrupt */
+ USART2_TX_IRQn = 41, /*!< 16+41 EFR32 USART2_TX Interrupt */
+ I2C1_IRQn = 42, /*!< 16+42 EFR32 I2C1 Interrupt */
+ USART3_RX_IRQn = 43, /*!< 16+43 EFR32 USART3_RX Interrupt */
+ USART3_TX_IRQn = 44, /*!< 16+44 EFR32 USART3_TX Interrupt */
+ VDAC0_IRQn = 45, /*!< 16+45 EFR32 VDAC0 Interrupt */
+ CSEN_IRQn = 46, /*!< 16+46 EFR32 CSEN Interrupt */
+ LESENSE_IRQn = 47, /*!< 16+47 EFR32 LESENSE Interrupt */
+ CRYPTO1_IRQn = 48, /*!< 16+48 EFR32 CRYPTO1 Interrupt */
+ TRNG0_IRQn = 49, /*!< 16+49 EFR32 TRNG0 Interrupt */
} IRQn_Type;
#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512IM32_Core Core
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F1024GM68_Core Core
* @{
* @brief Processor and Core Peripheral Section
- *****************************************************************************/
-#define __MPU_PRESENT 1 /**< Presence of MPU */
-#define __FPU_PRESENT 1 /**< Presence of FPU */
-#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
-/** @} End of group EFR32FG13P231F512IM32_Core */
+/** @} End of group EFR32FG12P231F1024GM68_Core */
-/**************************************************************************//**
-* @defgroup EFR32FG13P231F512IM32_Part Part
-* @{
-******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F1024GM68_Part Part
+ * @{
+ ******************************************************************************/
/** Part family */
#define _EFR32_FLEX_FAMILY 1 /**< FLEX Gecko RF SoC Family */
#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG_3 /**< Series 1, Configuration 3 */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG 3 /**< Series 1, Configuration 3 */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID 89 /**< Silicon Labs internal use only, may change any time */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID_89 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /**< Silicon Labs internal use only, may change any time */
#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /**< Radio type */
#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN_3 /**< @deprecated Platform 2, generation 3 */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN 3 /**< @deprecated Platform 2, generation 3 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */
/* If part number is not defined as compiler option, define it */
-#if !defined(EFR32FG13P231F512IM32)
-#define EFR32FG13P231F512IM32 1 /**< FLEX Gecko Part */
+#if !defined(EFR32FG12P231F1024GM68)
+#define EFR32FG12P231F1024GM68 1 /**< FLEX Gecko Part */
#endif
/** Configure part number */
-#define PART_NUMBER "EFR32FG13P231F512IM32" /**< Part Number */
+#define PART_NUMBER "EFR32FG12P231F1024GM68" /**< Part Number */
/** Memory Base addresses and limits */
-#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */
-#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM0_CODE available address space */
-#define RAM0_CODE_MEM_END ((uint32_t) 0x10007FFFUL) /**< RAM0_CODE end address */
-#define RAM0_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM0_CODE used bits */
-#define RAM2_MEM_BASE ((uint32_t) 0x20010000UL) /**< RAM2 base address */
-#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */
-#define RAM2_MEM_END ((uint32_t) 0x200107FFUL) /**< RAM2 end address */
-#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */
-#define RAM1_MEM_BASE ((uint32_t) 0x20008000UL) /**< RAM1 base address */
-#define RAM1_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM1 available address space */
-#define RAM1_MEM_END ((uint32_t) 0x2000FFFFUL) /**< RAM1 end address */
-#define RAM1_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM1 used bits */
-#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */
-#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */
-#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
-#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
-#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */
-#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */
-#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */
-#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10008000UL) /**< RAM1_CODE base address */
-#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM1_CODE available address space */
-#define RAM1_CODE_MEM_END ((uint32_t) 0x1000FFFFUL) /**< RAM1_CODE end address */
-#define RAM1_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM1_CODE used bits */
-#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */
-#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */
-#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */
-#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */
-#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
-#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
-#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */
-#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */
-#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */
-#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */
-#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */
-#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
-#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
-#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
-#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
-#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
-#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */
-#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */
-#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */
-#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */
-#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */
-#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */
-#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */
-#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
-#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
-#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
-#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
-#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */
-#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */
-#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
-#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
-#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
-#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
-#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
-#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
-#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
-#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */
-#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */
-#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */
-#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */
-#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */
-#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */
-#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */
-#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10010000UL) /**< RAM2_CODE base address */
-#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */
-#define RAM2_CODE_MEM_END ((uint32_t) 0x100107FFUL) /**< RAM2_CODE end address */
-#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
-#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
-#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
-#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */
+#define CRYPTO1_BITCLR_MEM_BASE (0x440F0400UL) /**< CRYPTO1_BITCLR base address */
+#define CRYPTO1_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO1_BITCLR available address space */
+#define CRYPTO1_BITCLR_MEM_END (0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
+#define CRYPTO1_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
+#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */
+#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */
+#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */
+#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */
+#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */
+#define RAM2_MEM_SIZE (0x800UL) /**< RAM2 available address space */
+#define RAM2_MEM_END (0x200407FFUL) /**< RAM2 end address */
+#define RAM2_MEM_BITS (0x0000000BUL) /**< RAM2 used bits */
+#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */
+#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */
+#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
+#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
+#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
+#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
+#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
+#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
+#define CRYPTO1_MEM_BASE (0x400F0400UL) /**< CRYPTO1 base address */
+#define CRYPTO1_MEM_SIZE (0x400UL) /**< CRYPTO1 available address space */
+#define CRYPTO1_MEM_END (0x400F07FFUL) /**< CRYPTO1 end address */
+#define CRYPTO1_MEM_BITS (0x0000000AUL) /**< CRYPTO1 used bits */
+#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */
+#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */
+#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */
+#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
+#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
+#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
+#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
+#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */
+#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */
+#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */
+#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */
+#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */
+#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */
+#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */
+#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define CRYPTO1_BITSET_MEM_BASE (0x460F0400UL) /**< CRYPTO1_BITSET base address */
+#define CRYPTO1_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO1_BITSET available address space */
+#define CRYPTO1_BITSET_MEM_END (0x460F07FFUL) /**< CRYPTO1_BITSET end address */
+#define CRYPTO1_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITSET used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x20000UL) /**< RAM available address space */
+#define RAM_MEM_END (0x2001FFFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x00000011UL) /**< RAM used bits */
+#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */
+#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */
+#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */
+#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */
+#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
+#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
+#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
+#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xF0000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460EFFFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xF0000UL) /**< PER available address space */
+#define PER_MEM_END (0x400EFFFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */
+#define RAM2_CODE_MEM_SIZE (0x800UL) /**< RAM2_CODE available address space */
+#define RAM2_CODE_MEM_END (0x100407FFUL) /**< RAM2_CODE end address */
+#define RAM2_CODE_MEM_BITS (0x0000000BUL) /**< RAM2_CODE used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xF0000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440EFFFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
/** Bit banding area */
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
-/** Flash and SRAM limits for EFR32FG13P231F512IM32 */
+/** Flash and SRAM limits for EFR32FG12P231F1024GM68 */
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
-#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */
-#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
+#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size (interleaving off) */
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
-#define SRAM_SIZE (0x00010000UL) /**< Available SRAM Memory */
-#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
+#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
-#define EXT_IRQ_COUNT 47 /**< Number of External (NVIC) interrupts */
+#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */
/** AF channels connect the different on-chip peripherals with the af-mux */
-#define AFCHAN_MAX 118U
+#define AFCHAN_MAX 136U
/** AF channel maximum location number */
#define AFCHANLOC_MAX 32U
/** Analog AF channels */
-#define AFACHAN_MAX 118U
+#define AFACHAN_MAX 125U
/* Part number capabilities */
@@ -259,27 +272,27 @@ typedef enum IRQn{
#define TIMER_PRESENT /**< TIMER is available in this part */
#define TIMER_COUNT 2 /**< 2 TIMERs available */
#define WTIMER_PRESENT /**< WTIMER is available in this part */
-#define WTIMER_COUNT 1 /**< 1 WTIMERs available */
+#define WTIMER_COUNT 2 /**< 2 WTIMERs available */
#define USART_PRESENT /**< USART is available in this part */
-#define USART_COUNT 3 /**< 3 USARTs available */
+#define USART_COUNT 4 /**< 4 USARTs available */
#define LEUART_PRESENT /**< LEUART is available in this part */
#define LEUART_COUNT 1 /**< 1 LEUARTs available */
#define LETIMER_PRESENT /**< LETIMER is available in this part */
#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
#define PCNT_PRESENT /**< PCNT is available in this part */
-#define PCNT_COUNT 1 /**< 1 PCNTs available */
+#define PCNT_COUNT 3 /**< 3 PCNTs available */
#define I2C_PRESENT /**< I2C is available in this part */
#define I2C_COUNT 2 /**< 2 I2Cs available */
#define ADC_PRESENT /**< ADC is available in this part */
#define ADC_COUNT 1 /**< 1 ADCs available */
#define ACMP_PRESENT /**< ACMP is available in this part */
#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
#define VDAC_PRESENT /**< VDAC is available in this part */
#define VDAC_COUNT 1 /**< 1 VDACs available */
#define WDOG_PRESENT /**< WDOG is available in this part */
#define WDOG_COUNT 2 /**< 2 WDOGs available */
-#define IDAC_PRESENT /**< IDAC is available in this part */
-#define IDAC_COUNT 1 /**< 1 IDACs available */
#define TRNG_PRESENT /**< TRNG is available in this part */
#define TRNG_COUNT 1 /**< 1 TRNGs available */
#define MSC_PRESENT /**< MSC is available in this part */
@@ -317,66 +330,66 @@ typedef enum IRQn{
#define DCDC_PRESENT /**< DCDC is available in this part */
#define DCDC_COUNT 1 /**< 1 DCDC available */
-#include "../../../efr32/cmsis/core_cm4.h" /* Cortex-M4 processor and core peripherals */
-#include "../../../efr32/vendor/efr32fg13/system_efr32fg13p.h" /* System Header File */
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32fg12p.h" /* System Header File */
-/** @} End of group EFR32FG13P231F512IM32_Part */
+/** @} End of group EFR32FG12P231F1024GM68_Part */
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512IM32_Peripheral_TypeDefs Peripheral TypeDefs
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F1024GM68_Peripheral_TypeDefs Peripheral TypeDefs
* @{
* @brief Device Specific Peripheral Register Structures
- *****************************************************************************/
-
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_msc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_emu.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_rmu.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_cmu.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_crypto.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_gpio_p.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_gpio.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_prs_ch.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_prs.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_ldma_ch.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_ldma.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_fpueh.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_gpcrc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_timer_cc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_timer.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_usart.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_leuart.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_letimer.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_cryotimer.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_pcnt.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_i2c.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_adc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_acmp.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_vdac_opa.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_vdac.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_csen.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_lesense_st.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_lesense_buf.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_lesense_ch.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_lesense.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_rtcc_cc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_rtcc_ret.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_rtcc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_wdog_pch.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_wdog.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_etm.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_idac.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_smu.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_trng.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_dma_descriptor.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_devinfo.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_romtable.h"
-
-/** @} End of group EFR32FG13P231F512IM32_Peripheral_TypeDefs */
-
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512IM32_Peripheral_Base Peripheral Memory Map
+ ******************************************************************************/
+
+#include "efr32fg12p_msc.h"
+#include "efr32fg12p_emu.h"
+#include "efr32fg12p_rmu.h"
+#include "efr32fg12p_cmu.h"
+#include "efr32fg12p_crypto.h"
+#include "efr32fg12p_gpio_p.h"
+#include "efr32fg12p_gpio.h"
+#include "efr32fg12p_prs_ch.h"
+#include "efr32fg12p_prs.h"
+#include "efr32fg12p_ldma_ch.h"
+#include "efr32fg12p_ldma.h"
+#include "efr32fg12p_fpueh.h"
+#include "efr32fg12p_gpcrc.h"
+#include "efr32fg12p_timer_cc.h"
+#include "efr32fg12p_timer.h"
+#include "efr32fg12p_usart.h"
+#include "efr32fg12p_leuart.h"
+#include "efr32fg12p_letimer.h"
+#include "efr32fg12p_cryotimer.h"
+#include "efr32fg12p_pcnt.h"
+#include "efr32fg12p_i2c.h"
+#include "efr32fg12p_adc.h"
+#include "efr32fg12p_acmp.h"
+#include "efr32fg12p_idac.h"
+#include "efr32fg12p_vdac_opa.h"
+#include "efr32fg12p_vdac.h"
+#include "efr32fg12p_csen.h"
+#include "efr32fg12p_lesense_st.h"
+#include "efr32fg12p_lesense_buf.h"
+#include "efr32fg12p_lesense_ch.h"
+#include "efr32fg12p_lesense.h"
+#include "efr32fg12p_rtcc_cc.h"
+#include "efr32fg12p_rtcc_ret.h"
+#include "efr32fg12p_rtcc.h"
+#include "efr32fg12p_wdog_pch.h"
+#include "efr32fg12p_wdog.h"
+#include "efr32fg12p_etm.h"
+#include "efr32fg12p_smu.h"
+#include "efr32fg12p_trng.h"
+#include "efr32fg12p_dma_descriptor.h"
+#include "efr32fg12p_devinfo.h"
+#include "efr32fg12p_romtable.h"
+
+/** @} End of group EFR32FG12P231F1024GM68_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F1024GM68_Peripheral_Base Peripheral Memory Map
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC_BASE (0x400E0000UL) /**< MSC base address */
#define EMU_BASE (0x400E3000UL) /**< EMU base address */
@@ -393,18 +406,23 @@ typedef enum IRQn{
#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */
+#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */
#define USART0_BASE (0x40010000UL) /**< USART0 base address */
#define USART1_BASE (0x40010400UL) /**< USART1 base address */
#define USART2_BASE (0x40010800UL) /**< USART2 base address */
+#define USART3_BASE (0x40010C00UL) /**< USART3 base address */
#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
+#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */
+#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */
#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */
#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
+#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */
#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */
#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */
@@ -412,7 +430,6 @@ typedef enum IRQn{
#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */
#define ETM_BASE (0xE0041000UL) /**< ETM base address */
-#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
#define SMU_BASE (0x40022000UL) /**< SMU base address */
#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */
#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
@@ -420,12 +437,12 @@ typedef enum IRQn{
#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
-/** @} End of group EFR32FG13P231F512IM32_Peripheral_Base */
+/** @} End of group EFR32FG12P231F1024GM68_Peripheral_Base */
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512IM32_Peripheral_Declaration Peripheral Declarations
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F1024GM68_Peripheral_Declaration Peripheral Declarations
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
@@ -442,18 +459,23 @@ typedef enum IRQn{
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */
+#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
+#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
+#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
+#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
+#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */
#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */
#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
@@ -461,18 +483,17 @@ typedef enum IRQn{
#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */
#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
-#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */
#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
-/** @} End of group EFR32FG13P231F512IM32_Peripheral_Declaration */
+/** @} End of group EFR32FG12P231F1024GM68_Peripheral_Declaration */
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512IM32_Peripheral_Offsets Peripheral Offsets
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F1024GM68_Peripheral_Offsets Peripheral Offsets
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */
#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
@@ -484,31 +505,31 @@ typedef enum IRQn{
#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
+#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */
#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
-#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */
-/** @} End of group EFR32FG13P231F512IM32_Peripheral_Offsets */
+/** @} End of group EFR32FG12P231F1024GM68_Peripheral_Offsets */
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512IM32_BitFields Bit Fields
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F1024GM68_BitFields Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_prs_signals.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_dmareq.h"
+#include "efr32fg12p_prs_signals.h"
+#include "efr32fg12p_dmareq.h"
-/**************************************************************************//**
- * @addtogroup EFR32FG13P231F512IM32_WTIMER
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P231F1024GM68_WTIMER
* @{
- * @defgroup EFR32FG13P231F512IM32_WTIMER_BitFields WTIMER Bit Fields
+ * @defgroup EFR32FG12P231F1024GM68_WTIMER_BitFields WTIMER Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for WTIMER CTRL */
#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */
-#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */
+#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */
#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
@@ -579,11 +600,6 @@ typedef enum IRQn{
#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */
#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */
-#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */
-#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */
-#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */
#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */
#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */
#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
@@ -1010,13 +1026,13 @@ typedef enum IRQn{
#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */
-#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */
+#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */
-#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */
+#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */
@@ -1997,23 +2013,23 @@ typedef enum IRQn{
#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */
-#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */
+#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */
-#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */
+#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */
/** @} */
-/** @} End of group EFR32FG13P231F512IM32_WTIMER */
+/** @} End of group EFR32FG12P231F1024GM68_WTIMER */
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512IM32_UNLOCK Unlock Codes
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F1024GM68_UNLOCK Unlock Codes
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
@@ -2022,18 +2038,19 @@ typedef enum IRQn{
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
-/** @} End of group EFR32FG13P231F512IM32_UNLOCK */
+/** @} End of group EFR32FG12P231F1024GM68_UNLOCK */
-/** @} End of group EFR32FG13P231F512IM32_BitFields */
+/** @} End of group EFR32FG12P231F1024GM68_BitFields */
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_af_ports.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_af_pins.h"
+#include "efr32fg12p_af_ports.h"
+#include "efr32fg12p_af_pins.h"
-/** @} End of group EFR32FG13P231F512IM32 */
+/** @} End of group EFR32FG12P231F1024GM68 */
/** @} End of group Parts */
#ifdef __cplusplus
}
#endif
-#endif /* EFR32FG13P231F512IM32_H */
+
+#endif /* EFR32FG12P231F1024GM68_H */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p231f512gm48.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p231f512gm68.h
similarity index 92%
rename from mcu/efr/common/vendor/efr32fg13/efr32fg13p231f512gm48.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p231f512gm68.h
index 0217395b..acb707e5 100644
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p231f512gm48.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p231f512gm68.h
@@ -1,35 +1,33 @@
-/**************************************************************************//**
- * @file efr32fg13p231f512gm48.h
+/***************************************************************************//**
+ * @file
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
- * for EFR32FG13P231F512GM48
- * @version 5.4.0
- ******************************************************************************
+ * for EFR32FG12P231F512GM68
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#if defined(__ICCARM__)
#pragma system_include /* Treat file as system include file. */
@@ -37,22 +35,22 @@
#pragma clang system_header /* Treat file as system include file. */
#endif
-#ifndef EFR32FG13P231F512GM48_H
-#define EFR32FG13P231F512GM48_H
+#ifndef EFR32FG12P231F512GM68_H
+#define EFR32FG12P231F512GM68_H
#ifdef __cplusplus
extern "C" {
#endif
-/**************************************************************************//**
+/***************************************************************************//**
* @addtogroup Parts
* @{
- *****************************************************************************/
+ ******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512GM48 EFR32FG13P231F512GM48
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F512GM68 EFR32FG12P231F512GM68
* @{
- *****************************************************************************/
+ ******************************************************************************/
/** Interrupt Number Definition */
typedef enum IRQn{
@@ -67,11 +65,17 @@ typedef enum IRQn{
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
-/****** EFR32FG13P Peripheral Interrupt Numbers ********************************************/
+/****** EFR32FG12P Peripheral Interrupt Numbers ********************************************/
EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
WDOG1_IRQn = 3, /*!< 16+3 EFR32 WDOG1 Interrupt */
+ FRC_IRQn = 4, /*!< 16+4 EFR32 FRC Interrupt */
+ MODEM_IRQn = 5, /*!< 16+5 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 6, /*!< 16+6 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 7, /*!< 16+7 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 8, /*!< 16+8 EFR32 BUFC Interrupt */
LDMA_IRQn = 9, /*!< 16+9 EFR32 LDMA Interrupt */
GPIO_EVEN_IRQn = 10, /*!< 16+10 EFR32 GPIO_EVEN Interrupt */
TIMER0_IRQn = 11, /*!< 16+11 EFR32 TIMER0 Interrupt */
@@ -91,166 +95,175 @@ typedef enum IRQn{
MSC_IRQn = 25, /*!< 16+25 EFR32 MSC Interrupt */
CRYPTO0_IRQn = 26, /*!< 16+26 EFR32 CRYPTO0 Interrupt */
LETIMER0_IRQn = 27, /*!< 16+27 EFR32 LETIMER0 Interrupt */
- RTCC_IRQn = 31, /*!< 16+31 EFR32 RTCC Interrupt */
- CRYOTIMER_IRQn = 33, /*!< 16+33 EFR32 CRYOTIMER Interrupt */
- FPUEH_IRQn = 35, /*!< 16+35 EFR32 FPUEH Interrupt */
- SMU_IRQn = 36, /*!< 16+36 EFR32 SMU Interrupt */
- WTIMER0_IRQn = 37, /*!< 16+37 EFR32 WTIMER0 Interrupt */
- USART2_RX_IRQn = 38, /*!< 16+38 EFR32 USART2_RX Interrupt */
- USART2_TX_IRQn = 39, /*!< 16+39 EFR32 USART2_TX Interrupt */
- I2C1_IRQn = 40, /*!< 16+40 EFR32 I2C1 Interrupt */
- VDAC0_IRQn = 41, /*!< 16+41 EFR32 VDAC0 Interrupt */
- CSEN_IRQn = 42, /*!< 16+42 EFR32 CSEN Interrupt */
- LESENSE_IRQn = 43, /*!< 16+43 EFR32 LESENSE Interrupt */
- CRYPTO1_IRQn = 44, /*!< 16+44 EFR32 CRYPTO1 Interrupt */
- TRNG0_IRQn = 45, /*!< 16+45 EFR32 TRNG0 Interrupt */
+ AGC_IRQn = 28, /*!< 16+28 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 29, /*!< 16+29 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 30, /*!< 16+30 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 31, /*!< 16+31 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 32, /*!< 16+32 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 33, /*!< 16+33 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 34, /*!< 16+34 EFR32 FPUEH Interrupt */
+ SMU_IRQn = 35, /*!< 16+35 EFR32 SMU Interrupt */
+ WTIMER0_IRQn = 36, /*!< 16+36 EFR32 WTIMER0 Interrupt */
+ WTIMER1_IRQn = 37, /*!< 16+37 EFR32 WTIMER1 Interrupt */
+ PCNT1_IRQn = 38, /*!< 16+38 EFR32 PCNT1 Interrupt */
+ PCNT2_IRQn = 39, /*!< 16+39 EFR32 PCNT2 Interrupt */
+ USART2_RX_IRQn = 40, /*!< 16+40 EFR32 USART2_RX Interrupt */
+ USART2_TX_IRQn = 41, /*!< 16+41 EFR32 USART2_TX Interrupt */
+ I2C1_IRQn = 42, /*!< 16+42 EFR32 I2C1 Interrupt */
+ USART3_RX_IRQn = 43, /*!< 16+43 EFR32 USART3_RX Interrupt */
+ USART3_TX_IRQn = 44, /*!< 16+44 EFR32 USART3_TX Interrupt */
+ VDAC0_IRQn = 45, /*!< 16+45 EFR32 VDAC0 Interrupt */
+ CSEN_IRQn = 46, /*!< 16+46 EFR32 CSEN Interrupt */
+ LESENSE_IRQn = 47, /*!< 16+47 EFR32 LESENSE Interrupt */
+ CRYPTO1_IRQn = 48, /*!< 16+48 EFR32 CRYPTO1 Interrupt */
+ TRNG0_IRQn = 49, /*!< 16+49 EFR32 TRNG0 Interrupt */
} IRQn_Type;
#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512GM48_Core Core
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F512GM68_Core Core
* @{
* @brief Processor and Core Peripheral Section
- *****************************************************************************/
-#define __MPU_PRESENT 1 /**< Presence of MPU */
-#define __FPU_PRESENT 1 /**< Presence of FPU */
-#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
-/** @} End of group EFR32FG13P231F512GM48_Core */
+/** @} End of group EFR32FG12P231F512GM68_Core */
-/**************************************************************************//**
-* @defgroup EFR32FG13P231F512GM48_Part Part
-* @{
-******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F512GM68_Part Part
+ * @{
+ ******************************************************************************/
/** Part family */
#define _EFR32_FLEX_FAMILY 1 /**< FLEX Gecko RF SoC Family */
#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG_3 /**< Series 1, Configuration 3 */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG 3 /**< Series 1, Configuration 3 */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID 89 /**< Silicon Labs internal use only, may change any time */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID_89 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /**< Silicon Labs internal use only, may change any time */
#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /**< Radio type */
#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN_3 /**< @deprecated Platform 2, generation 3 */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN 3 /**< @deprecated Platform 2, generation 3 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */
/* If part number is not defined as compiler option, define it */
-#if !defined(EFR32FG13P231F512GM48)
-#define EFR32FG13P231F512GM48 1 /**< FLEX Gecko Part */
+#if !defined(EFR32FG12P231F512GM68)
+#define EFR32FG12P231F512GM68 1 /**< FLEX Gecko Part */
#endif
/** Configure part number */
-#define PART_NUMBER "EFR32FG13P231F512GM48" /**< Part Number */
+#define PART_NUMBER "EFR32FG12P231F512GM68" /**< Part Number */
/** Memory Base addresses and limits */
-#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */
-#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM0_CODE available address space */
-#define RAM0_CODE_MEM_END ((uint32_t) 0x10007FFFUL) /**< RAM0_CODE end address */
-#define RAM0_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM0_CODE used bits */
-#define RAM2_MEM_BASE ((uint32_t) 0x20010000UL) /**< RAM2 base address */
-#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */
-#define RAM2_MEM_END ((uint32_t) 0x200107FFUL) /**< RAM2 end address */
-#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */
-#define RAM1_MEM_BASE ((uint32_t) 0x20008000UL) /**< RAM1 base address */
-#define RAM1_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM1 available address space */
-#define RAM1_MEM_END ((uint32_t) 0x2000FFFFUL) /**< RAM1 end address */
-#define RAM1_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM1 used bits */
-#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */
-#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */
-#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
-#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
-#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */
-#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */
-#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */
-#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10008000UL) /**< RAM1_CODE base address */
-#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM1_CODE available address space */
-#define RAM1_CODE_MEM_END ((uint32_t) 0x1000FFFFUL) /**< RAM1_CODE end address */
-#define RAM1_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM1_CODE used bits */
-#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */
-#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */
-#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */
-#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */
-#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
-#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
-#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */
-#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */
-#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */
-#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */
-#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */
-#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
-#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
-#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
-#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
-#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
-#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */
-#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */
-#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */
-#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */
-#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */
-#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */
-#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */
-#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
-#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
-#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
-#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
-#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */
-#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */
-#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
-#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
-#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
-#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
-#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
-#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
-#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
-#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */
-#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */
-#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */
-#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */
-#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */
-#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */
-#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */
-#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10010000UL) /**< RAM2_CODE base address */
-#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */
-#define RAM2_CODE_MEM_END ((uint32_t) 0x100107FFUL) /**< RAM2_CODE end address */
-#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
-#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
-#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
-#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */
+#define CRYPTO1_BITCLR_MEM_BASE (0x440F0400UL) /**< CRYPTO1_BITCLR base address */
+#define CRYPTO1_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO1_BITCLR available address space */
+#define CRYPTO1_BITCLR_MEM_END (0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
+#define CRYPTO1_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
+#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */
+#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */
+#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */
+#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */
+#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */
+#define RAM2_MEM_SIZE (0x800UL) /**< RAM2 available address space */
+#define RAM2_MEM_END (0x200407FFUL) /**< RAM2 end address */
+#define RAM2_MEM_BITS (0x0000000BUL) /**< RAM2 used bits */
+#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */
+#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */
+#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
+#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
+#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
+#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
+#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
+#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
+#define CRYPTO1_MEM_BASE (0x400F0400UL) /**< CRYPTO1 base address */
+#define CRYPTO1_MEM_SIZE (0x400UL) /**< CRYPTO1 available address space */
+#define CRYPTO1_MEM_END (0x400F07FFUL) /**< CRYPTO1 end address */
+#define CRYPTO1_MEM_BITS (0x0000000AUL) /**< CRYPTO1 used bits */
+#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */
+#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */
+#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */
+#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
+#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
+#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
+#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
+#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */
+#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */
+#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */
+#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */
+#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */
+#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */
+#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */
+#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define CRYPTO1_BITSET_MEM_BASE (0x460F0400UL) /**< CRYPTO1_BITSET base address */
+#define CRYPTO1_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO1_BITSET available address space */
+#define CRYPTO1_BITSET_MEM_END (0x460F07FFUL) /**< CRYPTO1_BITSET end address */
+#define CRYPTO1_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITSET used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x20000UL) /**< RAM available address space */
+#define RAM_MEM_END (0x2001FFFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x00000011UL) /**< RAM used bits */
+#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */
+#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */
+#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */
+#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */
+#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
+#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
+#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
+#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xF0000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460EFFFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xF0000UL) /**< PER available address space */
+#define PER_MEM_END (0x400EFFFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */
+#define RAM2_CODE_MEM_SIZE (0x800UL) /**< RAM2_CODE available address space */
+#define RAM2_CODE_MEM_END (0x100407FFUL) /**< RAM2_CODE end address */
+#define RAM2_CODE_MEM_BITS (0x0000000BUL) /**< RAM2_CODE used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xF0000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440EFFFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
/** Bit banding area */
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
-/** Flash and SRAM limits for EFR32FG13P231F512GM48 */
+/** Flash and SRAM limits for EFR32FG12P231F512GM68 */
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */
-#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size (interleaving off) */
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
#define SRAM_SIZE (0x00010000UL) /**< Available SRAM Memory */
-#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
-#define EXT_IRQ_COUNT 47 /**< Number of External (NVIC) interrupts */
+#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */
/** AF channels connect the different on-chip peripherals with the af-mux */
-#define AFCHAN_MAX 118U
+#define AFCHAN_MAX 136U
/** AF channel maximum location number */
#define AFCHANLOC_MAX 32U
/** Analog AF channels */
-#define AFACHAN_MAX 118U
+#define AFACHAN_MAX 125U
/* Part number capabilities */
@@ -259,27 +272,27 @@ typedef enum IRQn{
#define TIMER_PRESENT /**< TIMER is available in this part */
#define TIMER_COUNT 2 /**< 2 TIMERs available */
#define WTIMER_PRESENT /**< WTIMER is available in this part */
-#define WTIMER_COUNT 1 /**< 1 WTIMERs available */
+#define WTIMER_COUNT 2 /**< 2 WTIMERs available */
#define USART_PRESENT /**< USART is available in this part */
-#define USART_COUNT 3 /**< 3 USARTs available */
+#define USART_COUNT 4 /**< 4 USARTs available */
#define LEUART_PRESENT /**< LEUART is available in this part */
#define LEUART_COUNT 1 /**< 1 LEUARTs available */
#define LETIMER_PRESENT /**< LETIMER is available in this part */
#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
#define PCNT_PRESENT /**< PCNT is available in this part */
-#define PCNT_COUNT 1 /**< 1 PCNTs available */
+#define PCNT_COUNT 3 /**< 3 PCNTs available */
#define I2C_PRESENT /**< I2C is available in this part */
#define I2C_COUNT 2 /**< 2 I2Cs available */
#define ADC_PRESENT /**< ADC is available in this part */
#define ADC_COUNT 1 /**< 1 ADCs available */
#define ACMP_PRESENT /**< ACMP is available in this part */
#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
#define VDAC_PRESENT /**< VDAC is available in this part */
#define VDAC_COUNT 1 /**< 1 VDACs available */
#define WDOG_PRESENT /**< WDOG is available in this part */
#define WDOG_COUNT 2 /**< 2 WDOGs available */
-#define IDAC_PRESENT /**< IDAC is available in this part */
-#define IDAC_COUNT 1 /**< 1 IDACs available */
#define TRNG_PRESENT /**< TRNG is available in this part */
#define TRNG_COUNT 1 /**< 1 TRNGs available */
#define MSC_PRESENT /**< MSC is available in this part */
@@ -317,66 +330,66 @@ typedef enum IRQn{
#define DCDC_PRESENT /**< DCDC is available in this part */
#define DCDC_COUNT 1 /**< 1 DCDC available */
-#include "../../../efr32/cmsis/core_cm4.h" /* Cortex-M4 processor and core peripherals */
-#include "../../../efr32/vendor/efr32fg13/system_efr32fg13p.h" /* System Header File */
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32fg12p.h" /* System Header File */
-/** @} End of group EFR32FG13P231F512GM48_Part */
+/** @} End of group EFR32FG12P231F512GM68_Part */
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512GM48_Peripheral_TypeDefs Peripheral TypeDefs
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F512GM68_Peripheral_TypeDefs Peripheral TypeDefs
* @{
* @brief Device Specific Peripheral Register Structures
- *****************************************************************************/
-
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_msc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_emu.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_rmu.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_cmu.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_crypto.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_gpio_p.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_gpio.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_prs_ch.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_prs.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_ldma_ch.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_ldma.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_fpueh.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_gpcrc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_timer_cc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_timer.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_usart.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_leuart.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_letimer.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_cryotimer.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_pcnt.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_i2c.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_adc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_acmp.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_vdac_opa.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_vdac.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_csen.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_lesense_st.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_lesense_buf.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_lesense_ch.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_lesense.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_rtcc_cc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_rtcc_ret.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_rtcc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_wdog_pch.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_wdog.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_etm.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_idac.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_smu.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_trng.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_dma_descriptor.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_devinfo.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_romtable.h"
-
-/** @} End of group EFR32FG13P231F512GM48_Peripheral_TypeDefs */
-
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512GM48_Peripheral_Base Peripheral Memory Map
+ ******************************************************************************/
+
+#include "efr32fg12p_msc.h"
+#include "efr32fg12p_emu.h"
+#include "efr32fg12p_rmu.h"
+#include "efr32fg12p_cmu.h"
+#include "efr32fg12p_crypto.h"
+#include "efr32fg12p_gpio_p.h"
+#include "efr32fg12p_gpio.h"
+#include "efr32fg12p_prs_ch.h"
+#include "efr32fg12p_prs.h"
+#include "efr32fg12p_ldma_ch.h"
+#include "efr32fg12p_ldma.h"
+#include "efr32fg12p_fpueh.h"
+#include "efr32fg12p_gpcrc.h"
+#include "efr32fg12p_timer_cc.h"
+#include "efr32fg12p_timer.h"
+#include "efr32fg12p_usart.h"
+#include "efr32fg12p_leuart.h"
+#include "efr32fg12p_letimer.h"
+#include "efr32fg12p_cryotimer.h"
+#include "efr32fg12p_pcnt.h"
+#include "efr32fg12p_i2c.h"
+#include "efr32fg12p_adc.h"
+#include "efr32fg12p_acmp.h"
+#include "efr32fg12p_idac.h"
+#include "efr32fg12p_vdac_opa.h"
+#include "efr32fg12p_vdac.h"
+#include "efr32fg12p_csen.h"
+#include "efr32fg12p_lesense_st.h"
+#include "efr32fg12p_lesense_buf.h"
+#include "efr32fg12p_lesense_ch.h"
+#include "efr32fg12p_lesense.h"
+#include "efr32fg12p_rtcc_cc.h"
+#include "efr32fg12p_rtcc_ret.h"
+#include "efr32fg12p_rtcc.h"
+#include "efr32fg12p_wdog_pch.h"
+#include "efr32fg12p_wdog.h"
+#include "efr32fg12p_etm.h"
+#include "efr32fg12p_smu.h"
+#include "efr32fg12p_trng.h"
+#include "efr32fg12p_dma_descriptor.h"
+#include "efr32fg12p_devinfo.h"
+#include "efr32fg12p_romtable.h"
+
+/** @} End of group EFR32FG12P231F512GM68_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F512GM68_Peripheral_Base Peripheral Memory Map
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC_BASE (0x400E0000UL) /**< MSC base address */
#define EMU_BASE (0x400E3000UL) /**< EMU base address */
@@ -393,18 +406,23 @@ typedef enum IRQn{
#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */
+#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */
#define USART0_BASE (0x40010000UL) /**< USART0 base address */
#define USART1_BASE (0x40010400UL) /**< USART1 base address */
#define USART2_BASE (0x40010800UL) /**< USART2 base address */
+#define USART3_BASE (0x40010C00UL) /**< USART3 base address */
#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
+#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */
+#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */
#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */
#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
+#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */
#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */
#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */
@@ -412,7 +430,6 @@ typedef enum IRQn{
#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */
#define ETM_BASE (0xE0041000UL) /**< ETM base address */
-#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
#define SMU_BASE (0x40022000UL) /**< SMU base address */
#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */
#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
@@ -420,12 +437,12 @@ typedef enum IRQn{
#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
-/** @} End of group EFR32FG13P231F512GM48_Peripheral_Base */
+/** @} End of group EFR32FG12P231F512GM68_Peripheral_Base */
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512GM48_Peripheral_Declaration Peripheral Declarations
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F512GM68_Peripheral_Declaration Peripheral Declarations
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
@@ -442,18 +459,23 @@ typedef enum IRQn{
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */
+#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
+#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
+#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
+#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
+#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */
#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */
#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
@@ -461,18 +483,17 @@ typedef enum IRQn{
#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */
#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
-#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */
#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
-/** @} End of group EFR32FG13P231F512GM48_Peripheral_Declaration */
+/** @} End of group EFR32FG12P231F512GM68_Peripheral_Declaration */
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512GM48_Peripheral_Offsets Peripheral Offsets
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F512GM68_Peripheral_Offsets Peripheral Offsets
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */
#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
@@ -484,31 +505,31 @@ typedef enum IRQn{
#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
+#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */
#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
-#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */
-/** @} End of group EFR32FG13P231F512GM48_Peripheral_Offsets */
+/** @} End of group EFR32FG12P231F512GM68_Peripheral_Offsets */
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512GM48_BitFields Bit Fields
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F512GM68_BitFields Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_prs_signals.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_dmareq.h"
+#include "efr32fg12p_prs_signals.h"
+#include "efr32fg12p_dmareq.h"
-/**************************************************************************//**
- * @addtogroup EFR32FG13P231F512GM48_WTIMER
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P231F512GM68_WTIMER
* @{
- * @defgroup EFR32FG13P231F512GM48_WTIMER_BitFields WTIMER Bit Fields
+ * @defgroup EFR32FG12P231F512GM68_WTIMER_BitFields WTIMER Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for WTIMER CTRL */
#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */
-#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */
+#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */
#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
@@ -579,11 +600,6 @@ typedef enum IRQn{
#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */
#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */
-#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */
-#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */
-#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */
#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */
#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */
#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
@@ -1010,13 +1026,13 @@ typedef enum IRQn{
#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */
-#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */
+#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */
-#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */
+#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */
@@ -1997,23 +2013,23 @@ typedef enum IRQn{
#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */
-#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */
+#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */
-#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */
+#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */
/** @} */
-/** @} End of group EFR32FG13P231F512GM48_WTIMER */
+/** @} End of group EFR32FG12P231F512GM68_WTIMER */
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512GM48_UNLOCK Unlock Codes
+/***************************************************************************//**
+ * @defgroup EFR32FG12P231F512GM68_UNLOCK Unlock Codes
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
@@ -2022,18 +2038,19 @@ typedef enum IRQn{
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
-/** @} End of group EFR32FG13P231F512GM48_UNLOCK */
+/** @} End of group EFR32FG12P231F512GM68_UNLOCK */
-/** @} End of group EFR32FG13P231F512GM48_BitFields */
+/** @} End of group EFR32FG12P231F512GM68_BitFields */
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_af_ports.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_af_pins.h"
+#include "efr32fg12p_af_ports.h"
+#include "efr32fg12p_af_pins.h"
-/** @} End of group EFR32FG13P231F512GM48 */
+/** @} End of group EFR32FG12P231F512GM68 */
/** @} End of group Parts */
#ifdef __cplusplus
}
#endif
-#endif /* EFR32FG13P231F512GM48_H */
+
+#endif /* EFR32FG12P231F512GM68_H */
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p232f1024gl125.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p232f1024gl125.h
similarity index 91%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p232f1024gl125.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p232f1024gl125.h
index 53353049..c20689a9 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p232f1024gl125.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p232f1024gl125.h
@@ -1,35 +1,39 @@
-/**************************************************************************//**
- * @file efr32fg12p232f1024gl125.h
+/***************************************************************************//**
+ * @file
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
* for EFR32FG12P232F1024GL125
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
#ifndef EFR32FG12P232F1024GL125_H
#define EFR32FG12P232F1024GL125_H
@@ -38,111 +42,120 @@
extern "C" {
#endif
-/**************************************************************************//**
+/***************************************************************************//**
* @addtogroup Parts
* @{
- *****************************************************************************/
+ ******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFR32FG12P232F1024GL125 EFR32FG12P232F1024GL125
* @{
- *****************************************************************************/
+ ******************************************************************************/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
+typedef enum IRQn{
/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
- NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */
- HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */
- MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
/****** EFR32FG12P Peripheral Interrupt Numbers ********************************************/
- EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */
- WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */
- WDOG1_IRQn = 3, /*!< 3 EFR32 WDOG1 Interrupt */
- LDMA_IRQn = 9, /*!< 9 EFR32 LDMA Interrupt */
- GPIO_EVEN_IRQn = 10, /*!< 10 EFR32 GPIO_EVEN Interrupt */
- TIMER0_IRQn = 11, /*!< 11 EFR32 TIMER0 Interrupt */
- USART0_RX_IRQn = 12, /*!< 12 EFR32 USART0_RX Interrupt */
- USART0_TX_IRQn = 13, /*!< 13 EFR32 USART0_TX Interrupt */
- ACMP0_IRQn = 14, /*!< 14 EFR32 ACMP0 Interrupt */
- ADC0_IRQn = 15, /*!< 15 EFR32 ADC0 Interrupt */
- IDAC0_IRQn = 16, /*!< 16 EFR32 IDAC0 Interrupt */
- I2C0_IRQn = 17, /*!< 17 EFR32 I2C0 Interrupt */
- GPIO_ODD_IRQn = 18, /*!< 18 EFR32 GPIO_ODD Interrupt */
- TIMER1_IRQn = 19, /*!< 19 EFR32 TIMER1 Interrupt */
- USART1_RX_IRQn = 20, /*!< 20 EFR32 USART1_RX Interrupt */
- USART1_TX_IRQn = 21, /*!< 21 EFR32 USART1_TX Interrupt */
- LEUART0_IRQn = 22, /*!< 22 EFR32 LEUART0 Interrupt */
- PCNT0_IRQn = 23, /*!< 23 EFR32 PCNT0 Interrupt */
- CMU_IRQn = 24, /*!< 24 EFR32 CMU Interrupt */
- MSC_IRQn = 25, /*!< 25 EFR32 MSC Interrupt */
- CRYPTO0_IRQn = 26, /*!< 26 EFR32 CRYPTO0 Interrupt */
- LETIMER0_IRQn = 27, /*!< 27 EFR32 LETIMER0 Interrupt */
- RTCC_IRQn = 30, /*!< 30 EFR32 RTCC Interrupt */
- CRYOTIMER_IRQn = 32, /*!< 32 EFR32 CRYOTIMER Interrupt */
- FPUEH_IRQn = 34, /*!< 34 EFR32 FPUEH Interrupt */
- SMU_IRQn = 35, /*!< 35 EFR32 SMU Interrupt */
- WTIMER0_IRQn = 36, /*!< 36 EFR32 WTIMER0 Interrupt */
- WTIMER1_IRQn = 37, /*!< 37 EFR32 WTIMER1 Interrupt */
- PCNT1_IRQn = 38, /*!< 38 EFR32 PCNT1 Interrupt */
- PCNT2_IRQn = 39, /*!< 39 EFR32 PCNT2 Interrupt */
- USART2_RX_IRQn = 40, /*!< 40 EFR32 USART2_RX Interrupt */
- USART2_TX_IRQn = 41, /*!< 41 EFR32 USART2_TX Interrupt */
- I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */
- USART3_RX_IRQn = 43, /*!< 43 EFR32 USART3_RX Interrupt */
- USART3_TX_IRQn = 44, /*!< 44 EFR32 USART3_TX Interrupt */
- VDAC0_IRQn = 45, /*!< 45 EFR32 VDAC0 Interrupt */
- CSEN_IRQn = 46, /*!< 46 EFR32 CSEN Interrupt */
- LESENSE_IRQn = 47, /*!< 47 EFR32 LESENSE Interrupt */
- CRYPTO1_IRQn = 48, /*!< 48 EFR32 CRYPTO1 Interrupt */
- TRNG0_IRQn = 49, /*!< 49 EFR32 TRNG0 Interrupt */
+ EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
+ WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 3, /*!< 16+3 EFR32 WDOG1 Interrupt */
+ FRC_IRQn = 4, /*!< 16+4 EFR32 FRC Interrupt */
+ MODEM_IRQn = 5, /*!< 16+5 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 6, /*!< 16+6 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 7, /*!< 16+7 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 8, /*!< 16+8 EFR32 BUFC Interrupt */
+ LDMA_IRQn = 9, /*!< 16+9 EFR32 LDMA Interrupt */
+ GPIO_EVEN_IRQn = 10, /*!< 16+10 EFR32 GPIO_EVEN Interrupt */
+ TIMER0_IRQn = 11, /*!< 16+11 EFR32 TIMER0 Interrupt */
+ USART0_RX_IRQn = 12, /*!< 16+12 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 13, /*!< 16+13 EFR32 USART0_TX Interrupt */
+ ACMP0_IRQn = 14, /*!< 16+14 EFR32 ACMP0 Interrupt */
+ ADC0_IRQn = 15, /*!< 16+15 EFR32 ADC0 Interrupt */
+ IDAC0_IRQn = 16, /*!< 16+16 EFR32 IDAC0 Interrupt */
+ I2C0_IRQn = 17, /*!< 16+17 EFR32 I2C0 Interrupt */
+ GPIO_ODD_IRQn = 18, /*!< 16+18 EFR32 GPIO_ODD Interrupt */
+ TIMER1_IRQn = 19, /*!< 16+19 EFR32 TIMER1 Interrupt */
+ USART1_RX_IRQn = 20, /*!< 16+20 EFR32 USART1_RX Interrupt */
+ USART1_TX_IRQn = 21, /*!< 16+21 EFR32 USART1_TX Interrupt */
+ LEUART0_IRQn = 22, /*!< 16+22 EFR32 LEUART0 Interrupt */
+ PCNT0_IRQn = 23, /*!< 16+23 EFR32 PCNT0 Interrupt */
+ CMU_IRQn = 24, /*!< 16+24 EFR32 CMU Interrupt */
+ MSC_IRQn = 25, /*!< 16+25 EFR32 MSC Interrupt */
+ CRYPTO0_IRQn = 26, /*!< 16+26 EFR32 CRYPTO0 Interrupt */
+ LETIMER0_IRQn = 27, /*!< 16+27 EFR32 LETIMER0 Interrupt */
+ AGC_IRQn = 28, /*!< 16+28 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 29, /*!< 16+29 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 30, /*!< 16+30 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 31, /*!< 16+31 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 32, /*!< 16+32 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 33, /*!< 16+33 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 34, /*!< 16+34 EFR32 FPUEH Interrupt */
+ SMU_IRQn = 35, /*!< 16+35 EFR32 SMU Interrupt */
+ WTIMER0_IRQn = 36, /*!< 16+36 EFR32 WTIMER0 Interrupt */
+ WTIMER1_IRQn = 37, /*!< 16+37 EFR32 WTIMER1 Interrupt */
+ PCNT1_IRQn = 38, /*!< 16+38 EFR32 PCNT1 Interrupt */
+ PCNT2_IRQn = 39, /*!< 16+39 EFR32 PCNT2 Interrupt */
+ USART2_RX_IRQn = 40, /*!< 16+40 EFR32 USART2_RX Interrupt */
+ USART2_TX_IRQn = 41, /*!< 16+41 EFR32 USART2_TX Interrupt */
+ I2C1_IRQn = 42, /*!< 16+42 EFR32 I2C1 Interrupt */
+ USART3_RX_IRQn = 43, /*!< 16+43 EFR32 USART3_RX Interrupt */
+ USART3_TX_IRQn = 44, /*!< 16+44 EFR32 USART3_TX Interrupt */
+ VDAC0_IRQn = 45, /*!< 16+45 EFR32 VDAC0 Interrupt */
+ CSEN_IRQn = 46, /*!< 16+46 EFR32 CSEN Interrupt */
+ LESENSE_IRQn = 47, /*!< 16+47 EFR32 LESENSE Interrupt */
+ CRYPTO1_IRQn = 48, /*!< 16+48 EFR32 CRYPTO1 Interrupt */
+ TRNG0_IRQn = 49, /*!< 16+49 EFR32 TRNG0 Interrupt */
} IRQn_Type;
#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */
-/**************************************************************************//**
- * @defgroup EFR32FG12P232F1024GL125_Core EFR32FG12P232F1024GL125 Core
+/***************************************************************************//**
+ * @defgroup EFR32FG12P232F1024GL125_Core Core
* @{
* @brief Processor and Core Peripheral Section
- *****************************************************************************/
-#define __MPU_PRESENT 1 /**< Presence of MPU */
-#define __FPU_PRESENT 1 /**< Presence of FPU */
-#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
/** @} End of group EFR32FG12P232F1024GL125_Core */
-/**************************************************************************//**
-* @defgroup EFR32FG12P232F1024GL125_Part EFR32FG12P232F1024GL125 Part
-* @{
-******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P232F1024GL125_Part Part
+ * @{
+ ******************************************************************************/
/** Part family */
-#define _EFR32_FLEX_FAMILY 1 /**< FLEX Gecko RF SoC Family */
-#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
-#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
-#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */
-#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1
-#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2
-#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3
-#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ
-#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
-#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */
+#define _EFR32_FLEX_FAMILY 1 /**< FLEX Gecko RF SoC Family */
+#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
+#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /**< Radio type */
+#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */
/* If part number is not defined as compiler option, define it */
#if !defined(EFR32FG12P232F1024GL125)
@@ -153,179 +166,180 @@ typedef enum IRQn
#define PART_NUMBER "EFR32FG12P232F1024GL125" /**< Part Number */
/** Memory Base addresses and limits */
-#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */
-#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */
-#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */
-#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */
-#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */
-#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */
-#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */
-#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */
-#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */
-#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */
-#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */
-#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */
-#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */
-#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */
-#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
-#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
-#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */
-#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */
-#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */
-#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */
-#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */
-#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */
-#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */
-#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */
-#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */
-#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */
-#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */
-#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
-#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
-#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */
-#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */
-#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */
-#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */
-#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */
-#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
-#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
-#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
-#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
-#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
-#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */
-#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */
-#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */
-#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */
-#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */
-#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */
-#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */
-#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
-#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
-#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
-#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
-#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */
-#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */
-#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
-#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
-#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
-#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
-#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
-#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
-#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
-#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */
-#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */
-#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */
-#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */
-#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */
-#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */
-#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */
-#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */
-#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */
-#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */
-#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
-#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */
-#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */
-#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */
+#define CRYPTO1_BITCLR_MEM_BASE (0x440F0400UL) /**< CRYPTO1_BITCLR base address */
+#define CRYPTO1_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO1_BITCLR available address space */
+#define CRYPTO1_BITCLR_MEM_END (0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
+#define CRYPTO1_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
+#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */
+#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */
+#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */
+#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */
+#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */
+#define RAM2_MEM_SIZE (0x800UL) /**< RAM2 available address space */
+#define RAM2_MEM_END (0x200407FFUL) /**< RAM2 end address */
+#define RAM2_MEM_BITS (0x0000000BUL) /**< RAM2 used bits */
+#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */
+#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */
+#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
+#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
+#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
+#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
+#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
+#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
+#define CRYPTO1_MEM_BASE (0x400F0400UL) /**< CRYPTO1 base address */
+#define CRYPTO1_MEM_SIZE (0x400UL) /**< CRYPTO1 available address space */
+#define CRYPTO1_MEM_END (0x400F07FFUL) /**< CRYPTO1 end address */
+#define CRYPTO1_MEM_BITS (0x0000000AUL) /**< CRYPTO1 used bits */
+#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */
+#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */
+#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */
+#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
+#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
+#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
+#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
+#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */
+#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */
+#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */
+#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */
+#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */
+#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */
+#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */
+#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define CRYPTO1_BITSET_MEM_BASE (0x460F0400UL) /**< CRYPTO1_BITSET base address */
+#define CRYPTO1_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO1_BITSET available address space */
+#define CRYPTO1_BITSET_MEM_END (0x460F07FFUL) /**< CRYPTO1_BITSET end address */
+#define CRYPTO1_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITSET used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x20000UL) /**< RAM available address space */
+#define RAM_MEM_END (0x2001FFFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x00000011UL) /**< RAM used bits */
+#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */
+#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */
+#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */
+#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */
+#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
+#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
+#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
+#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xF0000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460EFFFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xF0000UL) /**< PER available address space */
+#define PER_MEM_END (0x400EFFFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */
+#define RAM2_CODE_MEM_SIZE (0x800UL) /**< RAM2_CODE available address space */
+#define RAM2_CODE_MEM_END (0x100407FFUL) /**< RAM2_CODE end address */
+#define RAM2_CODE_MEM_BITS (0x0000000BUL) /**< RAM2_CODE used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xF0000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440EFFFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
/** Bit banding area */
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
/** Flash and SRAM limits for EFR32FG12P232F1024GL125 */
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */
-#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size (interleaving off) */
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
-#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */
/** AF channels connect the different on-chip peripherals with the af-mux */
-#define AFCHAN_MAX 136
-#define AFCHANLOC_MAX 32
+#define AFCHAN_MAX 136U
+/** AF channel maximum location number */
+#define AFCHANLOC_MAX 32U
/** Analog AF channels */
-#define AFACHAN_MAX 125
+#define AFACHAN_MAX 125U
/* Part number capabilities */
-#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
-#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */
-#define TIMER_PRESENT /**< TIMER is available in this part */
-#define TIMER_COUNT 2 /**< 2 TIMERs available */
-#define WTIMER_PRESENT /**< WTIMER is available in this part */
-#define WTIMER_COUNT 2 /**< 2 WTIMERs available */
-#define USART_PRESENT /**< USART is available in this part */
-#define USART_COUNT 4 /**< 4 USARTs available */
-#define LEUART_PRESENT /**< LEUART is available in this part */
-#define LEUART_COUNT 1 /**< 1 LEUARTs available */
-#define LETIMER_PRESENT /**< LETIMER is available in this part */
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
-#define PCNT_PRESENT /**< PCNT is available in this part */
-#define PCNT_COUNT 3 /**< 3 PCNTs available */
-#define I2C_PRESENT /**< I2C is available in this part */
-#define I2C_COUNT 2 /**< 2 I2Cs available */
-#define ADC_PRESENT /**< ADC is available in this part */
-#define ADC_COUNT 1 /**< 1 ADCs available */
-#define ACMP_PRESENT /**< ACMP is available in this part */
-#define ACMP_COUNT 2 /**< 2 ACMPs available */
-#define IDAC_PRESENT /**< IDAC is available in this part */
-#define IDAC_COUNT 1 /**< 1 IDACs available */
-#define VDAC_PRESENT /**< VDAC is available in this part */
-#define VDAC_COUNT 1 /**< 1 VDACs available */
-#define WDOG_PRESENT /**< WDOG is available in this part */
-#define WDOG_COUNT 2 /**< 2 WDOGs available */
-#define TRNG_PRESENT /**< TRNG is available in this part */
-#define TRNG_COUNT 1 /**< 1 TRNGs available */
-#define SYSTICK_PRESENT
-#define SYSTICK_COUNT 1
-#define MSC_PRESENT
-#define MSC_COUNT 1
-#define EMU_PRESENT
-#define EMU_COUNT 1
-#define RMU_PRESENT
-#define RMU_COUNT 1
-#define CMU_PRESENT
-#define CMU_COUNT 1
-#define GPIO_PRESENT
-#define GPIO_COUNT 1
-#define PRS_PRESENT
-#define PRS_COUNT 1
-#define LDMA_PRESENT
-#define LDMA_COUNT 1
-#define FPUEH_PRESENT
-#define FPUEH_COUNT 1
-#define GPCRC_PRESENT
-#define GPCRC_COUNT 1
-#define CRYOTIMER_PRESENT
-#define CRYOTIMER_COUNT 1
-#define CSEN_PRESENT
-#define CSEN_COUNT 1
-#define LESENSE_PRESENT
-#define LESENSE_COUNT 1
-#define RTCC_PRESENT
-#define RTCC_COUNT 1
-#define ETM_PRESENT
-#define ETM_COUNT 1
-#define BOOTLOADER_PRESENT
-#define BOOTLOADER_COUNT 1
-#define SMU_PRESENT
-#define SMU_COUNT 1
-
-#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
-#include "system_efr32fg12p.h" /* System Header File */
+#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
+#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */
+#define TIMER_PRESENT /**< TIMER is available in this part */
+#define TIMER_COUNT 2 /**< 2 TIMERs available */
+#define WTIMER_PRESENT /**< WTIMER is available in this part */
+#define WTIMER_COUNT 2 /**< 2 WTIMERs available */
+#define USART_PRESENT /**< USART is available in this part */
+#define USART_COUNT 4 /**< 4 USARTs available */
+#define LEUART_PRESENT /**< LEUART is available in this part */
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */
+#define LETIMER_PRESENT /**< LETIMER is available in this part */
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
+#define PCNT_PRESENT /**< PCNT is available in this part */
+#define PCNT_COUNT 3 /**< 3 PCNTs available */
+#define I2C_PRESENT /**< I2C is available in this part */
+#define I2C_COUNT 2 /**< 2 I2Cs available */
+#define ADC_PRESENT /**< ADC is available in this part */
+#define ADC_COUNT 1 /**< 1 ADCs available */
+#define ACMP_PRESENT /**< ACMP is available in this part */
+#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
+#define VDAC_PRESENT /**< VDAC is available in this part */
+#define VDAC_COUNT 1 /**< 1 VDACs available */
+#define WDOG_PRESENT /**< WDOG is available in this part */
+#define WDOG_COUNT 2 /**< 2 WDOGs available */
+#define TRNG_PRESENT /**< TRNG is available in this part */
+#define TRNG_COUNT 1 /**< 1 TRNGs available */
+#define MSC_PRESENT /**< MSC is available in this part */
+#define MSC_COUNT 1 /**< 1 MSC available */
+#define EMU_PRESENT /**< EMU is available in this part */
+#define EMU_COUNT 1 /**< 1 EMU available */
+#define RMU_PRESENT /**< RMU is available in this part */
+#define RMU_COUNT 1 /**< 1 RMU available */
+#define CMU_PRESENT /**< CMU is available in this part */
+#define CMU_COUNT 1 /**< 1 CMU available */
+#define GPIO_PRESENT /**< GPIO is available in this part */
+#define GPIO_COUNT 1 /**< 1 GPIO available */
+#define PRS_PRESENT /**< PRS is available in this part */
+#define PRS_COUNT 1 /**< 1 PRS available */
+#define LDMA_PRESENT /**< LDMA is available in this part */
+#define LDMA_COUNT 1 /**< 1 LDMA available */
+#define FPUEH_PRESENT /**< FPUEH is available in this part */
+#define FPUEH_COUNT 1 /**< 1 FPUEH available */
+#define GPCRC_PRESENT /**< GPCRC is available in this part */
+#define GPCRC_COUNT 1 /**< 1 GPCRC available */
+#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
+#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
+#define CSEN_PRESENT /**< CSEN is available in this part */
+#define CSEN_COUNT 1 /**< 1 CSEN available */
+#define LESENSE_PRESENT /**< LESENSE is available in this part */
+#define LESENSE_COUNT 1 /**< 1 LESENSE available */
+#define RTCC_PRESENT /**< RTCC is available in this part */
+#define RTCC_COUNT 1 /**< 1 RTCC available */
+#define ETM_PRESENT /**< ETM is available in this part */
+#define ETM_COUNT 1 /**< 1 ETM available */
+#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
+#define SMU_PRESENT /**< SMU is available in this part */
+#define SMU_COUNT 1 /**< 1 SMU available */
+#define DCDC_PRESENT /**< DCDC is available in this part */
+#define DCDC_COUNT 1 /**< 1 DCDC available */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32fg12p.h" /* System Header File */
/** @} End of group EFR32FG12P232F1024GL125_Part */
-/**************************************************************************//**
- * @defgroup EFR32FG12P232F1024GL125_Peripheral_TypeDefs EFR32FG12P232F1024GL125 Peripheral TypeDefs
+/***************************************************************************//**
+ * @defgroup EFR32FG12P232F1024GL125_Peripheral_TypeDefs Peripheral TypeDefs
* @{
* @brief Device Specific Peripheral Register Structures
- *****************************************************************************/
+ ******************************************************************************/
#include "efr32fg12p_msc.h"
#include "efr32fg12p_emu.h"
@@ -372,10 +386,10 @@ typedef enum IRQn
/** @} End of group EFR32FG12P232F1024GL125_Peripheral_TypeDefs */
-/**************************************************************************//**
- * @defgroup EFR32FG12P232F1024GL125_Peripheral_Base EFR32FG12P232F1024GL125 Peripheral Memory Map
+/***************************************************************************//**
+ * @defgroup EFR32FG12P232F1024GL125_Peripheral_Base Peripheral Memory Map
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC_BASE (0x400E0000UL) /**< MSC base address */
#define EMU_BASE (0x400E3000UL) /**< EMU base address */
@@ -425,10 +439,10 @@ typedef enum IRQn
/** @} End of group EFR32FG12P232F1024GL125_Peripheral_Base */
-/**************************************************************************//**
- * @defgroup EFR32FG12P232F1024GL125_Peripheral_Declaration EFR32FG12P232F1024GL125 Peripheral Declarations
+/***************************************************************************//**
+ * @defgroup EFR32FG12P232F1024GL125_Peripheral_Declaration Peripheral Declarations
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
@@ -476,10 +490,10 @@ typedef enum IRQn
/** @} End of group EFR32FG12P232F1024GL125_Peripheral_Declaration */
-/**************************************************************************//**
- * @defgroup EFR32FG12P232F1024GL125_Peripheral_Offsets EFR32FG12P232F1024GL125 Peripheral Offsets
+/***************************************************************************//**
+ * @defgroup EFR32FG12P232F1024GL125_Peripheral_Offsets Peripheral Offsets
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */
#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
@@ -498,19 +512,20 @@ typedef enum IRQn
/** @} End of group EFR32FG12P232F1024GL125_Peripheral_Offsets */
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P232F1024GL125_BitFields EFR32FG12P232F1024GL125 Bit Fields
+/***************************************************************************//**
+ * @defgroup EFR32FG12P232F1024GL125_BitFields Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
#include "efr32fg12p_prs_signals.h"
#include "efr32fg12p_dmareq.h"
-/**************************************************************************//**
- * @defgroup EFR32FG12P232F1024GL125_WTIMER_BitFields EFR32FG12P232F1024GL125_WTIMER Bit Fields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P232F1024GL125_WTIMER
+ * @{
+ * @defgroup EFR32FG12P232F1024GL125_WTIMER_BitFields WTIMER Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for WTIMER CTRL */
#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */
@@ -626,7 +641,7 @@ typedef enum IRQn
#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */
#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */
+#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */
#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */
#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */
#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
@@ -1011,13 +1026,13 @@ typedef enum IRQn
#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */
-#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */
+#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */
-#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */
+#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */
@@ -1731,7 +1746,7 @@ typedef enum IRQn
#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */
#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */
+#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */
#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */
#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */
#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
@@ -1998,33 +2013,23 @@ typedef enum IRQn
#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */
-#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */
+#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */
-#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */
+#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */
+/** @} */
/** @} End of group EFR32FG12P232F1024GL125_WTIMER */
-
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P232F1024GL125_SYSTICK_BitFields EFR32FG12P232F1024GL125_SYSTICK Bit Fields
- * @{
- *****************************************************************************/
-
-/** @} End of group EFR32FG12P232F1024GL125_SYSTICK */
-
-
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P232F1024GL125_UNLOCK EFR32FG12P232F1024GL125 Unlock Codes
+/***************************************************************************//**
+ * @defgroup EFR32FG12P232F1024GL125_UNLOCK Unlock Codes
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
@@ -2037,16 +2042,9 @@ typedef enum IRQn
/** @} End of group EFR32FG12P232F1024GL125_BitFields */
-/**************************************************************************//**
- * @defgroup EFR32FG12P232F1024GL125_Alternate_Function EFR32FG12P232F1024GL125 Alternate Function
- * @{
- *****************************************************************************/
-
#include "efr32fg12p_af_ports.h"
#include "efr32fg12p_af_pins.h"
-/** @} End of group EFR32FG12P232F1024GL125_Alternate_Function */
-
/** @} End of group EFR32FG12P232F1024GL125 */
/** @} End of group Parts */
@@ -2054,4 +2052,5 @@ typedef enum IRQn
#ifdef __cplusplus
}
#endif
+
#endif /* EFR32FG12P232F1024GL125_H */
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p232f1024gm48.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p232f1024gm48.h
similarity index 91%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p232f1024gm48.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p232f1024gm48.h
index 0123ce5d..d45479b6 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p232f1024gm48.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p232f1024gm48.h
@@ -1,35 +1,39 @@
-/**************************************************************************//**
- * @file efr32fg12p232f1024gm48.h
+/***************************************************************************//**
+ * @file
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
* for EFR32FG12P232F1024GM48
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
#ifndef EFR32FG12P232F1024GM48_H
#define EFR32FG12P232F1024GM48_H
@@ -38,111 +42,120 @@
extern "C" {
#endif
-/**************************************************************************//**
+/***************************************************************************//**
* @addtogroup Parts
* @{
- *****************************************************************************/
+ ******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFR32FG12P232F1024GM48 EFR32FG12P232F1024GM48
* @{
- *****************************************************************************/
+ ******************************************************************************/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
+typedef enum IRQn{
/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
- NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */
- HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */
- MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
/****** EFR32FG12P Peripheral Interrupt Numbers ********************************************/
- EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */
- WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */
- WDOG1_IRQn = 3, /*!< 3 EFR32 WDOG1 Interrupt */
- LDMA_IRQn = 9, /*!< 9 EFR32 LDMA Interrupt */
- GPIO_EVEN_IRQn = 10, /*!< 10 EFR32 GPIO_EVEN Interrupt */
- TIMER0_IRQn = 11, /*!< 11 EFR32 TIMER0 Interrupt */
- USART0_RX_IRQn = 12, /*!< 12 EFR32 USART0_RX Interrupt */
- USART0_TX_IRQn = 13, /*!< 13 EFR32 USART0_TX Interrupt */
- ACMP0_IRQn = 14, /*!< 14 EFR32 ACMP0 Interrupt */
- ADC0_IRQn = 15, /*!< 15 EFR32 ADC0 Interrupt */
- IDAC0_IRQn = 16, /*!< 16 EFR32 IDAC0 Interrupt */
- I2C0_IRQn = 17, /*!< 17 EFR32 I2C0 Interrupt */
- GPIO_ODD_IRQn = 18, /*!< 18 EFR32 GPIO_ODD Interrupt */
- TIMER1_IRQn = 19, /*!< 19 EFR32 TIMER1 Interrupt */
- USART1_RX_IRQn = 20, /*!< 20 EFR32 USART1_RX Interrupt */
- USART1_TX_IRQn = 21, /*!< 21 EFR32 USART1_TX Interrupt */
- LEUART0_IRQn = 22, /*!< 22 EFR32 LEUART0 Interrupt */
- PCNT0_IRQn = 23, /*!< 23 EFR32 PCNT0 Interrupt */
- CMU_IRQn = 24, /*!< 24 EFR32 CMU Interrupt */
- MSC_IRQn = 25, /*!< 25 EFR32 MSC Interrupt */
- CRYPTO0_IRQn = 26, /*!< 26 EFR32 CRYPTO0 Interrupt */
- LETIMER0_IRQn = 27, /*!< 27 EFR32 LETIMER0 Interrupt */
- RTCC_IRQn = 30, /*!< 30 EFR32 RTCC Interrupt */
- CRYOTIMER_IRQn = 32, /*!< 32 EFR32 CRYOTIMER Interrupt */
- FPUEH_IRQn = 34, /*!< 34 EFR32 FPUEH Interrupt */
- SMU_IRQn = 35, /*!< 35 EFR32 SMU Interrupt */
- WTIMER0_IRQn = 36, /*!< 36 EFR32 WTIMER0 Interrupt */
- WTIMER1_IRQn = 37, /*!< 37 EFR32 WTIMER1 Interrupt */
- PCNT1_IRQn = 38, /*!< 38 EFR32 PCNT1 Interrupt */
- PCNT2_IRQn = 39, /*!< 39 EFR32 PCNT2 Interrupt */
- USART2_RX_IRQn = 40, /*!< 40 EFR32 USART2_RX Interrupt */
- USART2_TX_IRQn = 41, /*!< 41 EFR32 USART2_TX Interrupt */
- I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */
- USART3_RX_IRQn = 43, /*!< 43 EFR32 USART3_RX Interrupt */
- USART3_TX_IRQn = 44, /*!< 44 EFR32 USART3_TX Interrupt */
- VDAC0_IRQn = 45, /*!< 45 EFR32 VDAC0 Interrupt */
- CSEN_IRQn = 46, /*!< 46 EFR32 CSEN Interrupt */
- LESENSE_IRQn = 47, /*!< 47 EFR32 LESENSE Interrupt */
- CRYPTO1_IRQn = 48, /*!< 48 EFR32 CRYPTO1 Interrupt */
- TRNG0_IRQn = 49, /*!< 49 EFR32 TRNG0 Interrupt */
+ EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
+ WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 3, /*!< 16+3 EFR32 WDOG1 Interrupt */
+ FRC_IRQn = 4, /*!< 16+4 EFR32 FRC Interrupt */
+ MODEM_IRQn = 5, /*!< 16+5 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 6, /*!< 16+6 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 7, /*!< 16+7 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 8, /*!< 16+8 EFR32 BUFC Interrupt */
+ LDMA_IRQn = 9, /*!< 16+9 EFR32 LDMA Interrupt */
+ GPIO_EVEN_IRQn = 10, /*!< 16+10 EFR32 GPIO_EVEN Interrupt */
+ TIMER0_IRQn = 11, /*!< 16+11 EFR32 TIMER0 Interrupt */
+ USART0_RX_IRQn = 12, /*!< 16+12 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 13, /*!< 16+13 EFR32 USART0_TX Interrupt */
+ ACMP0_IRQn = 14, /*!< 16+14 EFR32 ACMP0 Interrupt */
+ ADC0_IRQn = 15, /*!< 16+15 EFR32 ADC0 Interrupt */
+ IDAC0_IRQn = 16, /*!< 16+16 EFR32 IDAC0 Interrupt */
+ I2C0_IRQn = 17, /*!< 16+17 EFR32 I2C0 Interrupt */
+ GPIO_ODD_IRQn = 18, /*!< 16+18 EFR32 GPIO_ODD Interrupt */
+ TIMER1_IRQn = 19, /*!< 16+19 EFR32 TIMER1 Interrupt */
+ USART1_RX_IRQn = 20, /*!< 16+20 EFR32 USART1_RX Interrupt */
+ USART1_TX_IRQn = 21, /*!< 16+21 EFR32 USART1_TX Interrupt */
+ LEUART0_IRQn = 22, /*!< 16+22 EFR32 LEUART0 Interrupt */
+ PCNT0_IRQn = 23, /*!< 16+23 EFR32 PCNT0 Interrupt */
+ CMU_IRQn = 24, /*!< 16+24 EFR32 CMU Interrupt */
+ MSC_IRQn = 25, /*!< 16+25 EFR32 MSC Interrupt */
+ CRYPTO0_IRQn = 26, /*!< 16+26 EFR32 CRYPTO0 Interrupt */
+ LETIMER0_IRQn = 27, /*!< 16+27 EFR32 LETIMER0 Interrupt */
+ AGC_IRQn = 28, /*!< 16+28 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 29, /*!< 16+29 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 30, /*!< 16+30 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 31, /*!< 16+31 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 32, /*!< 16+32 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 33, /*!< 16+33 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 34, /*!< 16+34 EFR32 FPUEH Interrupt */
+ SMU_IRQn = 35, /*!< 16+35 EFR32 SMU Interrupt */
+ WTIMER0_IRQn = 36, /*!< 16+36 EFR32 WTIMER0 Interrupt */
+ WTIMER1_IRQn = 37, /*!< 16+37 EFR32 WTIMER1 Interrupt */
+ PCNT1_IRQn = 38, /*!< 16+38 EFR32 PCNT1 Interrupt */
+ PCNT2_IRQn = 39, /*!< 16+39 EFR32 PCNT2 Interrupt */
+ USART2_RX_IRQn = 40, /*!< 16+40 EFR32 USART2_RX Interrupt */
+ USART2_TX_IRQn = 41, /*!< 16+41 EFR32 USART2_TX Interrupt */
+ I2C1_IRQn = 42, /*!< 16+42 EFR32 I2C1 Interrupt */
+ USART3_RX_IRQn = 43, /*!< 16+43 EFR32 USART3_RX Interrupt */
+ USART3_TX_IRQn = 44, /*!< 16+44 EFR32 USART3_TX Interrupt */
+ VDAC0_IRQn = 45, /*!< 16+45 EFR32 VDAC0 Interrupt */
+ CSEN_IRQn = 46, /*!< 16+46 EFR32 CSEN Interrupt */
+ LESENSE_IRQn = 47, /*!< 16+47 EFR32 LESENSE Interrupt */
+ CRYPTO1_IRQn = 48, /*!< 16+48 EFR32 CRYPTO1 Interrupt */
+ TRNG0_IRQn = 49, /*!< 16+49 EFR32 TRNG0 Interrupt */
} IRQn_Type;
#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */
-/**************************************************************************//**
- * @defgroup EFR32FG12P232F1024GM48_Core EFR32FG12P232F1024GM48 Core
+/***************************************************************************//**
+ * @defgroup EFR32FG12P232F1024GM48_Core Core
* @{
* @brief Processor and Core Peripheral Section
- *****************************************************************************/
-#define __MPU_PRESENT 1 /**< Presence of MPU */
-#define __FPU_PRESENT 1 /**< Presence of FPU */
-#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
/** @} End of group EFR32FG12P232F1024GM48_Core */
-/**************************************************************************//**
-* @defgroup EFR32FG12P232F1024GM48_Part EFR32FG12P232F1024GM48 Part
-* @{
-******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P232F1024GM48_Part Part
+ * @{
+ ******************************************************************************/
/** Part family */
-#define _EFR32_FLEX_FAMILY 1 /**< FLEX Gecko RF SoC Family */
-#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
-#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
-#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */
-#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1
-#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2
-#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3
-#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ
-#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
-#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */
+#define _EFR32_FLEX_FAMILY 1 /**< FLEX Gecko RF SoC Family */
+#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
+#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /**< Radio type */
+#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */
/* If part number is not defined as compiler option, define it */
#if !defined(EFR32FG12P232F1024GM48)
@@ -153,179 +166,180 @@ typedef enum IRQn
#define PART_NUMBER "EFR32FG12P232F1024GM48" /**< Part Number */
/** Memory Base addresses and limits */
-#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */
-#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */
-#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */
-#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */
-#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */
-#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */
-#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */
-#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */
-#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */
-#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */
-#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */
-#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */
-#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */
-#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */
-#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
-#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
-#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */
-#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */
-#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */
-#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */
-#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */
-#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */
-#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */
-#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */
-#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */
-#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */
-#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */
-#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
-#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
-#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */
-#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */
-#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */
-#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */
-#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */
-#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
-#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
-#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
-#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
-#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
-#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */
-#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */
-#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */
-#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */
-#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */
-#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */
-#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */
-#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
-#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
-#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
-#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
-#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */
-#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */
-#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
-#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
-#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
-#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
-#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
-#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
-#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
-#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */
-#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */
-#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */
-#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */
-#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */
-#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */
-#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */
-#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */
-#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */
-#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */
-#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
-#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */
-#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */
-#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */
+#define CRYPTO1_BITCLR_MEM_BASE (0x440F0400UL) /**< CRYPTO1_BITCLR base address */
+#define CRYPTO1_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO1_BITCLR available address space */
+#define CRYPTO1_BITCLR_MEM_END (0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
+#define CRYPTO1_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
+#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */
+#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */
+#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */
+#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */
+#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */
+#define RAM2_MEM_SIZE (0x800UL) /**< RAM2 available address space */
+#define RAM2_MEM_END (0x200407FFUL) /**< RAM2 end address */
+#define RAM2_MEM_BITS (0x0000000BUL) /**< RAM2 used bits */
+#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */
+#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */
+#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
+#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
+#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
+#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
+#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
+#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
+#define CRYPTO1_MEM_BASE (0x400F0400UL) /**< CRYPTO1 base address */
+#define CRYPTO1_MEM_SIZE (0x400UL) /**< CRYPTO1 available address space */
+#define CRYPTO1_MEM_END (0x400F07FFUL) /**< CRYPTO1 end address */
+#define CRYPTO1_MEM_BITS (0x0000000AUL) /**< CRYPTO1 used bits */
+#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */
+#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */
+#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */
+#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
+#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
+#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
+#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
+#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */
+#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */
+#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */
+#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */
+#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */
+#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */
+#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */
+#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define CRYPTO1_BITSET_MEM_BASE (0x460F0400UL) /**< CRYPTO1_BITSET base address */
+#define CRYPTO1_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO1_BITSET available address space */
+#define CRYPTO1_BITSET_MEM_END (0x460F07FFUL) /**< CRYPTO1_BITSET end address */
+#define CRYPTO1_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITSET used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x20000UL) /**< RAM available address space */
+#define RAM_MEM_END (0x2001FFFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x00000011UL) /**< RAM used bits */
+#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */
+#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */
+#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */
+#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */
+#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
+#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
+#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
+#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xF0000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460EFFFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xF0000UL) /**< PER available address space */
+#define PER_MEM_END (0x400EFFFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */
+#define RAM2_CODE_MEM_SIZE (0x800UL) /**< RAM2_CODE available address space */
+#define RAM2_CODE_MEM_END (0x100407FFUL) /**< RAM2_CODE end address */
+#define RAM2_CODE_MEM_BITS (0x0000000BUL) /**< RAM2_CODE used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xF0000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440EFFFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
/** Bit banding area */
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
/** Flash and SRAM limits for EFR32FG12P232F1024GM48 */
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */
-#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size (interleaving off) */
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
-#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */
/** AF channels connect the different on-chip peripherals with the af-mux */
-#define AFCHAN_MAX 136
-#define AFCHANLOC_MAX 32
+#define AFCHAN_MAX 136U
+/** AF channel maximum location number */
+#define AFCHANLOC_MAX 32U
/** Analog AF channels */
-#define AFACHAN_MAX 125
+#define AFACHAN_MAX 125U
/* Part number capabilities */
-#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
-#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */
-#define TIMER_PRESENT /**< TIMER is available in this part */
-#define TIMER_COUNT 2 /**< 2 TIMERs available */
-#define WTIMER_PRESENT /**< WTIMER is available in this part */
-#define WTIMER_COUNT 2 /**< 2 WTIMERs available */
-#define USART_PRESENT /**< USART is available in this part */
-#define USART_COUNT 4 /**< 4 USARTs available */
-#define LEUART_PRESENT /**< LEUART is available in this part */
-#define LEUART_COUNT 1 /**< 1 LEUARTs available */
-#define LETIMER_PRESENT /**< LETIMER is available in this part */
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
-#define PCNT_PRESENT /**< PCNT is available in this part */
-#define PCNT_COUNT 3 /**< 3 PCNTs available */
-#define I2C_PRESENT /**< I2C is available in this part */
-#define I2C_COUNT 2 /**< 2 I2Cs available */
-#define ADC_PRESENT /**< ADC is available in this part */
-#define ADC_COUNT 1 /**< 1 ADCs available */
-#define ACMP_PRESENT /**< ACMP is available in this part */
-#define ACMP_COUNT 2 /**< 2 ACMPs available */
-#define IDAC_PRESENT /**< IDAC is available in this part */
-#define IDAC_COUNT 1 /**< 1 IDACs available */
-#define VDAC_PRESENT /**< VDAC is available in this part */
-#define VDAC_COUNT 1 /**< 1 VDACs available */
-#define WDOG_PRESENT /**< WDOG is available in this part */
-#define WDOG_COUNT 2 /**< 2 WDOGs available */
-#define TRNG_PRESENT /**< TRNG is available in this part */
-#define TRNG_COUNT 1 /**< 1 TRNGs available */
-#define SYSTICK_PRESENT
-#define SYSTICK_COUNT 1
-#define MSC_PRESENT
-#define MSC_COUNT 1
-#define EMU_PRESENT
-#define EMU_COUNT 1
-#define RMU_PRESENT
-#define RMU_COUNT 1
-#define CMU_PRESENT
-#define CMU_COUNT 1
-#define GPIO_PRESENT
-#define GPIO_COUNT 1
-#define PRS_PRESENT
-#define PRS_COUNT 1
-#define LDMA_PRESENT
-#define LDMA_COUNT 1
-#define FPUEH_PRESENT
-#define FPUEH_COUNT 1
-#define GPCRC_PRESENT
-#define GPCRC_COUNT 1
-#define CRYOTIMER_PRESENT
-#define CRYOTIMER_COUNT 1
-#define CSEN_PRESENT
-#define CSEN_COUNT 1
-#define LESENSE_PRESENT
-#define LESENSE_COUNT 1
-#define RTCC_PRESENT
-#define RTCC_COUNT 1
-#define ETM_PRESENT
-#define ETM_COUNT 1
-#define BOOTLOADER_PRESENT
-#define BOOTLOADER_COUNT 1
-#define SMU_PRESENT
-#define SMU_COUNT 1
-
-#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
-#include "system_efr32fg12p.h" /* System Header File */
+#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
+#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */
+#define TIMER_PRESENT /**< TIMER is available in this part */
+#define TIMER_COUNT 2 /**< 2 TIMERs available */
+#define WTIMER_PRESENT /**< WTIMER is available in this part */
+#define WTIMER_COUNT 2 /**< 2 WTIMERs available */
+#define USART_PRESENT /**< USART is available in this part */
+#define USART_COUNT 4 /**< 4 USARTs available */
+#define LEUART_PRESENT /**< LEUART is available in this part */
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */
+#define LETIMER_PRESENT /**< LETIMER is available in this part */
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
+#define PCNT_PRESENT /**< PCNT is available in this part */
+#define PCNT_COUNT 3 /**< 3 PCNTs available */
+#define I2C_PRESENT /**< I2C is available in this part */
+#define I2C_COUNT 2 /**< 2 I2Cs available */
+#define ADC_PRESENT /**< ADC is available in this part */
+#define ADC_COUNT 1 /**< 1 ADCs available */
+#define ACMP_PRESENT /**< ACMP is available in this part */
+#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
+#define VDAC_PRESENT /**< VDAC is available in this part */
+#define VDAC_COUNT 1 /**< 1 VDACs available */
+#define WDOG_PRESENT /**< WDOG is available in this part */
+#define WDOG_COUNT 2 /**< 2 WDOGs available */
+#define TRNG_PRESENT /**< TRNG is available in this part */
+#define TRNG_COUNT 1 /**< 1 TRNGs available */
+#define MSC_PRESENT /**< MSC is available in this part */
+#define MSC_COUNT 1 /**< 1 MSC available */
+#define EMU_PRESENT /**< EMU is available in this part */
+#define EMU_COUNT 1 /**< 1 EMU available */
+#define RMU_PRESENT /**< RMU is available in this part */
+#define RMU_COUNT 1 /**< 1 RMU available */
+#define CMU_PRESENT /**< CMU is available in this part */
+#define CMU_COUNT 1 /**< 1 CMU available */
+#define GPIO_PRESENT /**< GPIO is available in this part */
+#define GPIO_COUNT 1 /**< 1 GPIO available */
+#define PRS_PRESENT /**< PRS is available in this part */
+#define PRS_COUNT 1 /**< 1 PRS available */
+#define LDMA_PRESENT /**< LDMA is available in this part */
+#define LDMA_COUNT 1 /**< 1 LDMA available */
+#define FPUEH_PRESENT /**< FPUEH is available in this part */
+#define FPUEH_COUNT 1 /**< 1 FPUEH available */
+#define GPCRC_PRESENT /**< GPCRC is available in this part */
+#define GPCRC_COUNT 1 /**< 1 GPCRC available */
+#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
+#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
+#define CSEN_PRESENT /**< CSEN is available in this part */
+#define CSEN_COUNT 1 /**< 1 CSEN available */
+#define LESENSE_PRESENT /**< LESENSE is available in this part */
+#define LESENSE_COUNT 1 /**< 1 LESENSE available */
+#define RTCC_PRESENT /**< RTCC is available in this part */
+#define RTCC_COUNT 1 /**< 1 RTCC available */
+#define ETM_PRESENT /**< ETM is available in this part */
+#define ETM_COUNT 1 /**< 1 ETM available */
+#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
+#define SMU_PRESENT /**< SMU is available in this part */
+#define SMU_COUNT 1 /**< 1 SMU available */
+#define DCDC_PRESENT /**< DCDC is available in this part */
+#define DCDC_COUNT 1 /**< 1 DCDC available */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32fg12p.h" /* System Header File */
/** @} End of group EFR32FG12P232F1024GM48_Part */
-/**************************************************************************//**
- * @defgroup EFR32FG12P232F1024GM48_Peripheral_TypeDefs EFR32FG12P232F1024GM48 Peripheral TypeDefs
+/***************************************************************************//**
+ * @defgroup EFR32FG12P232F1024GM48_Peripheral_TypeDefs Peripheral TypeDefs
* @{
* @brief Device Specific Peripheral Register Structures
- *****************************************************************************/
+ ******************************************************************************/
#include "efr32fg12p_msc.h"
#include "efr32fg12p_emu.h"
@@ -372,10 +386,10 @@ typedef enum IRQn
/** @} End of group EFR32FG12P232F1024GM48_Peripheral_TypeDefs */
-/**************************************************************************//**
- * @defgroup EFR32FG12P232F1024GM48_Peripheral_Base EFR32FG12P232F1024GM48 Peripheral Memory Map
+/***************************************************************************//**
+ * @defgroup EFR32FG12P232F1024GM48_Peripheral_Base Peripheral Memory Map
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC_BASE (0x400E0000UL) /**< MSC base address */
#define EMU_BASE (0x400E3000UL) /**< EMU base address */
@@ -425,10 +439,10 @@ typedef enum IRQn
/** @} End of group EFR32FG12P232F1024GM48_Peripheral_Base */
-/**************************************************************************//**
- * @defgroup EFR32FG12P232F1024GM48_Peripheral_Declaration EFR32FG12P232F1024GM48 Peripheral Declarations
+/***************************************************************************//**
+ * @defgroup EFR32FG12P232F1024GM48_Peripheral_Declaration Peripheral Declarations
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
@@ -476,10 +490,10 @@ typedef enum IRQn
/** @} End of group EFR32FG12P232F1024GM48_Peripheral_Declaration */
-/**************************************************************************//**
- * @defgroup EFR32FG12P232F1024GM48_Peripheral_Offsets EFR32FG12P232F1024GM48 Peripheral Offsets
+/***************************************************************************//**
+ * @defgroup EFR32FG12P232F1024GM48_Peripheral_Offsets Peripheral Offsets
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */
#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
@@ -498,19 +512,20 @@ typedef enum IRQn
/** @} End of group EFR32FG12P232F1024GM48_Peripheral_Offsets */
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P232F1024GM48_BitFields EFR32FG12P232F1024GM48 Bit Fields
+/***************************************************************************//**
+ * @defgroup EFR32FG12P232F1024GM48_BitFields Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
#include "efr32fg12p_prs_signals.h"
#include "efr32fg12p_dmareq.h"
-/**************************************************************************//**
- * @defgroup EFR32FG12P232F1024GM48_WTIMER_BitFields EFR32FG12P232F1024GM48_WTIMER Bit Fields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P232F1024GM48_WTIMER
+ * @{
+ * @defgroup EFR32FG12P232F1024GM48_WTIMER_BitFields WTIMER Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for WTIMER CTRL */
#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */
@@ -626,7 +641,7 @@ typedef enum IRQn
#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */
#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */
+#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */
#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */
#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */
#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
@@ -1011,13 +1026,13 @@ typedef enum IRQn
#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */
-#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */
+#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */
-#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */
+#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */
@@ -1731,7 +1746,7 @@ typedef enum IRQn
#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */
#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */
+#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */
#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */
#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */
#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
@@ -1998,33 +2013,23 @@ typedef enum IRQn
#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */
-#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */
+#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */
-#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */
+#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */
+/** @} */
/** @} End of group EFR32FG12P232F1024GM48_WTIMER */
-
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P232F1024GM48_SYSTICK_BitFields EFR32FG12P232F1024GM48_SYSTICK Bit Fields
- * @{
- *****************************************************************************/
-
-/** @} End of group EFR32FG12P232F1024GM48_SYSTICK */
-
-
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P232F1024GM48_UNLOCK EFR32FG12P232F1024GM48 Unlock Codes
+/***************************************************************************//**
+ * @defgroup EFR32FG12P232F1024GM48_UNLOCK Unlock Codes
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
@@ -2037,16 +2042,9 @@ typedef enum IRQn
/** @} End of group EFR32FG12P232F1024GM48_BitFields */
-/**************************************************************************//**
- * @defgroup EFR32FG12P232F1024GM48_Alternate_Function EFR32FG12P232F1024GM48 Alternate Function
- * @{
- *****************************************************************************/
-
#include "efr32fg12p_af_ports.h"
#include "efr32fg12p_af_pins.h"
-/** @} End of group EFR32FG12P232F1024GM48_Alternate_Function */
-
/** @} End of group EFR32FG12P232F1024GM48 */
/** @} End of group Parts */
@@ -2054,4 +2052,5 @@ typedef enum IRQn
#ifdef __cplusplus
}
#endif
+
#endif /* EFR32FG12P232F1024GM48_H */
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p431f1024gl125.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p431f1024gl125.h
similarity index 91%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p431f1024gl125.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p431f1024gl125.h
index 0863fa84..dd19b13c 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p431f1024gl125.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p431f1024gl125.h
@@ -1,35 +1,39 @@
-/**************************************************************************//**
- * @file efr32fg12p431f1024gl125.h
+/***************************************************************************//**
+ * @file
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
* for EFR32FG12P431F1024GL125
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
#ifndef EFR32FG12P431F1024GL125_H
#define EFR32FG12P431F1024GL125_H
@@ -38,111 +42,120 @@
extern "C" {
#endif
-/**************************************************************************//**
+/***************************************************************************//**
* @addtogroup Parts
* @{
- *****************************************************************************/
+ ******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFR32FG12P431F1024GL125 EFR32FG12P431F1024GL125
* @{
- *****************************************************************************/
+ ******************************************************************************/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
+typedef enum IRQn{
/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
- NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */
- HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */
- MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
/****** EFR32FG12P Peripheral Interrupt Numbers ********************************************/
- EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */
- WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */
- WDOG1_IRQn = 3, /*!< 3 EFR32 WDOG1 Interrupt */
- LDMA_IRQn = 9, /*!< 9 EFR32 LDMA Interrupt */
- GPIO_EVEN_IRQn = 10, /*!< 10 EFR32 GPIO_EVEN Interrupt */
- TIMER0_IRQn = 11, /*!< 11 EFR32 TIMER0 Interrupt */
- USART0_RX_IRQn = 12, /*!< 12 EFR32 USART0_RX Interrupt */
- USART0_TX_IRQn = 13, /*!< 13 EFR32 USART0_TX Interrupt */
- ACMP0_IRQn = 14, /*!< 14 EFR32 ACMP0 Interrupt */
- ADC0_IRQn = 15, /*!< 15 EFR32 ADC0 Interrupt */
- IDAC0_IRQn = 16, /*!< 16 EFR32 IDAC0 Interrupt */
- I2C0_IRQn = 17, /*!< 17 EFR32 I2C0 Interrupt */
- GPIO_ODD_IRQn = 18, /*!< 18 EFR32 GPIO_ODD Interrupt */
- TIMER1_IRQn = 19, /*!< 19 EFR32 TIMER1 Interrupt */
- USART1_RX_IRQn = 20, /*!< 20 EFR32 USART1_RX Interrupt */
- USART1_TX_IRQn = 21, /*!< 21 EFR32 USART1_TX Interrupt */
- LEUART0_IRQn = 22, /*!< 22 EFR32 LEUART0 Interrupt */
- PCNT0_IRQn = 23, /*!< 23 EFR32 PCNT0 Interrupt */
- CMU_IRQn = 24, /*!< 24 EFR32 CMU Interrupt */
- MSC_IRQn = 25, /*!< 25 EFR32 MSC Interrupt */
- CRYPTO0_IRQn = 26, /*!< 26 EFR32 CRYPTO0 Interrupt */
- LETIMER0_IRQn = 27, /*!< 27 EFR32 LETIMER0 Interrupt */
- RTCC_IRQn = 30, /*!< 30 EFR32 RTCC Interrupt */
- CRYOTIMER_IRQn = 32, /*!< 32 EFR32 CRYOTIMER Interrupt */
- FPUEH_IRQn = 34, /*!< 34 EFR32 FPUEH Interrupt */
- SMU_IRQn = 35, /*!< 35 EFR32 SMU Interrupt */
- WTIMER0_IRQn = 36, /*!< 36 EFR32 WTIMER0 Interrupt */
- WTIMER1_IRQn = 37, /*!< 37 EFR32 WTIMER1 Interrupt */
- PCNT1_IRQn = 38, /*!< 38 EFR32 PCNT1 Interrupt */
- PCNT2_IRQn = 39, /*!< 39 EFR32 PCNT2 Interrupt */
- USART2_RX_IRQn = 40, /*!< 40 EFR32 USART2_RX Interrupt */
- USART2_TX_IRQn = 41, /*!< 41 EFR32 USART2_TX Interrupt */
- I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */
- USART3_RX_IRQn = 43, /*!< 43 EFR32 USART3_RX Interrupt */
- USART3_TX_IRQn = 44, /*!< 44 EFR32 USART3_TX Interrupt */
- VDAC0_IRQn = 45, /*!< 45 EFR32 VDAC0 Interrupt */
- CSEN_IRQn = 46, /*!< 46 EFR32 CSEN Interrupt */
- LESENSE_IRQn = 47, /*!< 47 EFR32 LESENSE Interrupt */
- CRYPTO1_IRQn = 48, /*!< 48 EFR32 CRYPTO1 Interrupt */
- TRNG0_IRQn = 49, /*!< 49 EFR32 TRNG0 Interrupt */
+ EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
+ WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 3, /*!< 16+3 EFR32 WDOG1 Interrupt */
+ FRC_IRQn = 4, /*!< 16+4 EFR32 FRC Interrupt */
+ MODEM_IRQn = 5, /*!< 16+5 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 6, /*!< 16+6 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 7, /*!< 16+7 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 8, /*!< 16+8 EFR32 BUFC Interrupt */
+ LDMA_IRQn = 9, /*!< 16+9 EFR32 LDMA Interrupt */
+ GPIO_EVEN_IRQn = 10, /*!< 16+10 EFR32 GPIO_EVEN Interrupt */
+ TIMER0_IRQn = 11, /*!< 16+11 EFR32 TIMER0 Interrupt */
+ USART0_RX_IRQn = 12, /*!< 16+12 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 13, /*!< 16+13 EFR32 USART0_TX Interrupt */
+ ACMP0_IRQn = 14, /*!< 16+14 EFR32 ACMP0 Interrupt */
+ ADC0_IRQn = 15, /*!< 16+15 EFR32 ADC0 Interrupt */
+ IDAC0_IRQn = 16, /*!< 16+16 EFR32 IDAC0 Interrupt */
+ I2C0_IRQn = 17, /*!< 16+17 EFR32 I2C0 Interrupt */
+ GPIO_ODD_IRQn = 18, /*!< 16+18 EFR32 GPIO_ODD Interrupt */
+ TIMER1_IRQn = 19, /*!< 16+19 EFR32 TIMER1 Interrupt */
+ USART1_RX_IRQn = 20, /*!< 16+20 EFR32 USART1_RX Interrupt */
+ USART1_TX_IRQn = 21, /*!< 16+21 EFR32 USART1_TX Interrupt */
+ LEUART0_IRQn = 22, /*!< 16+22 EFR32 LEUART0 Interrupt */
+ PCNT0_IRQn = 23, /*!< 16+23 EFR32 PCNT0 Interrupt */
+ CMU_IRQn = 24, /*!< 16+24 EFR32 CMU Interrupt */
+ MSC_IRQn = 25, /*!< 16+25 EFR32 MSC Interrupt */
+ CRYPTO0_IRQn = 26, /*!< 16+26 EFR32 CRYPTO0 Interrupt */
+ LETIMER0_IRQn = 27, /*!< 16+27 EFR32 LETIMER0 Interrupt */
+ AGC_IRQn = 28, /*!< 16+28 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 29, /*!< 16+29 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 30, /*!< 16+30 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 31, /*!< 16+31 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 32, /*!< 16+32 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 33, /*!< 16+33 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 34, /*!< 16+34 EFR32 FPUEH Interrupt */
+ SMU_IRQn = 35, /*!< 16+35 EFR32 SMU Interrupt */
+ WTIMER0_IRQn = 36, /*!< 16+36 EFR32 WTIMER0 Interrupt */
+ WTIMER1_IRQn = 37, /*!< 16+37 EFR32 WTIMER1 Interrupt */
+ PCNT1_IRQn = 38, /*!< 16+38 EFR32 PCNT1 Interrupt */
+ PCNT2_IRQn = 39, /*!< 16+39 EFR32 PCNT2 Interrupt */
+ USART2_RX_IRQn = 40, /*!< 16+40 EFR32 USART2_RX Interrupt */
+ USART2_TX_IRQn = 41, /*!< 16+41 EFR32 USART2_TX Interrupt */
+ I2C1_IRQn = 42, /*!< 16+42 EFR32 I2C1 Interrupt */
+ USART3_RX_IRQn = 43, /*!< 16+43 EFR32 USART3_RX Interrupt */
+ USART3_TX_IRQn = 44, /*!< 16+44 EFR32 USART3_TX Interrupt */
+ VDAC0_IRQn = 45, /*!< 16+45 EFR32 VDAC0 Interrupt */
+ CSEN_IRQn = 46, /*!< 16+46 EFR32 CSEN Interrupt */
+ LESENSE_IRQn = 47, /*!< 16+47 EFR32 LESENSE Interrupt */
+ CRYPTO1_IRQn = 48, /*!< 16+48 EFR32 CRYPTO1 Interrupt */
+ TRNG0_IRQn = 49, /*!< 16+49 EFR32 TRNG0 Interrupt */
} IRQn_Type;
#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */
-/**************************************************************************//**
- * @defgroup EFR32FG12P431F1024GL125_Core EFR32FG12P431F1024GL125 Core
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024GL125_Core Core
* @{
* @brief Processor and Core Peripheral Section
- *****************************************************************************/
-#define __MPU_PRESENT 1 /**< Presence of MPU */
-#define __FPU_PRESENT 1 /**< Presence of FPU */
-#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
/** @} End of group EFR32FG12P431F1024GL125_Core */
-/**************************************************************************//**
-* @defgroup EFR32FG12P431F1024GL125_Part EFR32FG12P431F1024GL125 Part
-* @{
-******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024GL125_Part Part
+ * @{
+ ******************************************************************************/
/** Part family */
-#define _EFR32_FLEX_FAMILY 1 /**< FLEX Gecko RF SoC Family */
-#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
-#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
-#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */
-#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1
-#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2
-#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3
-#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ
-#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
-#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */
+#define _EFR32_FLEX_FAMILY 1 /**< FLEX Gecko RF SoC Family */
+#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
+#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /**< Radio type */
+#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */
/* If part number is not defined as compiler option, define it */
#if !defined(EFR32FG12P431F1024GL125)
@@ -153,179 +166,180 @@ typedef enum IRQn
#define PART_NUMBER "EFR32FG12P431F1024GL125" /**< Part Number */
/** Memory Base addresses and limits */
-#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */
-#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */
-#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */
-#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */
-#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */
-#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */
-#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */
-#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */
-#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */
-#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */
-#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */
-#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */
-#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */
-#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */
-#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
-#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
-#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */
-#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */
-#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */
-#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */
-#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */
-#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */
-#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */
-#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */
-#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */
-#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */
-#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */
-#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
-#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
-#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */
-#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */
-#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */
-#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */
-#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */
-#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
-#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
-#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
-#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
-#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
-#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */
-#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */
-#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */
-#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */
-#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */
-#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */
-#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */
-#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
-#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
-#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
-#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
-#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */
-#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */
-#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
-#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
-#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
-#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
-#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
-#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
-#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
-#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */
-#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */
-#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */
-#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */
-#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */
-#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */
-#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */
-#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */
-#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */
-#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */
-#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
-#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */
-#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */
-#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */
+#define CRYPTO1_BITCLR_MEM_BASE (0x440F0400UL) /**< CRYPTO1_BITCLR base address */
+#define CRYPTO1_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO1_BITCLR available address space */
+#define CRYPTO1_BITCLR_MEM_END (0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
+#define CRYPTO1_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
+#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */
+#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */
+#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */
+#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */
+#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */
+#define RAM2_MEM_SIZE (0x800UL) /**< RAM2 available address space */
+#define RAM2_MEM_END (0x200407FFUL) /**< RAM2 end address */
+#define RAM2_MEM_BITS (0x0000000BUL) /**< RAM2 used bits */
+#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */
+#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */
+#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
+#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
+#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
+#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
+#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
+#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
+#define CRYPTO1_MEM_BASE (0x400F0400UL) /**< CRYPTO1 base address */
+#define CRYPTO1_MEM_SIZE (0x400UL) /**< CRYPTO1 available address space */
+#define CRYPTO1_MEM_END (0x400F07FFUL) /**< CRYPTO1 end address */
+#define CRYPTO1_MEM_BITS (0x0000000AUL) /**< CRYPTO1 used bits */
+#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */
+#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */
+#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */
+#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
+#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
+#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
+#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
+#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */
+#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */
+#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */
+#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */
+#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */
+#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */
+#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */
+#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define CRYPTO1_BITSET_MEM_BASE (0x460F0400UL) /**< CRYPTO1_BITSET base address */
+#define CRYPTO1_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO1_BITSET available address space */
+#define CRYPTO1_BITSET_MEM_END (0x460F07FFUL) /**< CRYPTO1_BITSET end address */
+#define CRYPTO1_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITSET used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x20000UL) /**< RAM available address space */
+#define RAM_MEM_END (0x2001FFFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x00000011UL) /**< RAM used bits */
+#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */
+#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */
+#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */
+#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */
+#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
+#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
+#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
+#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xF0000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460EFFFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xF0000UL) /**< PER available address space */
+#define PER_MEM_END (0x400EFFFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */
+#define RAM2_CODE_MEM_SIZE (0x800UL) /**< RAM2_CODE available address space */
+#define RAM2_CODE_MEM_END (0x100407FFUL) /**< RAM2_CODE end address */
+#define RAM2_CODE_MEM_BITS (0x0000000BUL) /**< RAM2_CODE used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xF0000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440EFFFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
/** Bit banding area */
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
/** Flash and SRAM limits for EFR32FG12P431F1024GL125 */
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */
-#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size (interleaving off) */
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
-#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */
/** AF channels connect the different on-chip peripherals with the af-mux */
-#define AFCHAN_MAX 136
-#define AFCHANLOC_MAX 32
+#define AFCHAN_MAX 136U
+/** AF channel maximum location number */
+#define AFCHANLOC_MAX 32U
/** Analog AF channels */
-#define AFACHAN_MAX 125
+#define AFACHAN_MAX 125U
/* Part number capabilities */
-#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
-#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */
-#define TIMER_PRESENT /**< TIMER is available in this part */
-#define TIMER_COUNT 2 /**< 2 TIMERs available */
-#define WTIMER_PRESENT /**< WTIMER is available in this part */
-#define WTIMER_COUNT 2 /**< 2 WTIMERs available */
-#define USART_PRESENT /**< USART is available in this part */
-#define USART_COUNT 4 /**< 4 USARTs available */
-#define LEUART_PRESENT /**< LEUART is available in this part */
-#define LEUART_COUNT 1 /**< 1 LEUARTs available */
-#define LETIMER_PRESENT /**< LETIMER is available in this part */
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
-#define PCNT_PRESENT /**< PCNT is available in this part */
-#define PCNT_COUNT 3 /**< 3 PCNTs available */
-#define I2C_PRESENT /**< I2C is available in this part */
-#define I2C_COUNT 2 /**< 2 I2Cs available */
-#define ADC_PRESENT /**< ADC is available in this part */
-#define ADC_COUNT 1 /**< 1 ADCs available */
-#define ACMP_PRESENT /**< ACMP is available in this part */
-#define ACMP_COUNT 2 /**< 2 ACMPs available */
-#define IDAC_PRESENT /**< IDAC is available in this part */
-#define IDAC_COUNT 1 /**< 1 IDACs available */
-#define VDAC_PRESENT /**< VDAC is available in this part */
-#define VDAC_COUNT 1 /**< 1 VDACs available */
-#define WDOG_PRESENT /**< WDOG is available in this part */
-#define WDOG_COUNT 2 /**< 2 WDOGs available */
-#define TRNG_PRESENT /**< TRNG is available in this part */
-#define TRNG_COUNT 1 /**< 1 TRNGs available */
-#define SYSTICK_PRESENT
-#define SYSTICK_COUNT 1
-#define MSC_PRESENT
-#define MSC_COUNT 1
-#define EMU_PRESENT
-#define EMU_COUNT 1
-#define RMU_PRESENT
-#define RMU_COUNT 1
-#define CMU_PRESENT
-#define CMU_COUNT 1
-#define GPIO_PRESENT
-#define GPIO_COUNT 1
-#define PRS_PRESENT
-#define PRS_COUNT 1
-#define LDMA_PRESENT
-#define LDMA_COUNT 1
-#define FPUEH_PRESENT
-#define FPUEH_COUNT 1
-#define GPCRC_PRESENT
-#define GPCRC_COUNT 1
-#define CRYOTIMER_PRESENT
-#define CRYOTIMER_COUNT 1
-#define CSEN_PRESENT
-#define CSEN_COUNT 1
-#define LESENSE_PRESENT
-#define LESENSE_COUNT 1
-#define RTCC_PRESENT
-#define RTCC_COUNT 1
-#define ETM_PRESENT
-#define ETM_COUNT 1
-#define BOOTLOADER_PRESENT
-#define BOOTLOADER_COUNT 1
-#define SMU_PRESENT
-#define SMU_COUNT 1
-
-#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
-#include "system_efr32fg12p.h" /* System Header File */
+#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
+#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */
+#define TIMER_PRESENT /**< TIMER is available in this part */
+#define TIMER_COUNT 2 /**< 2 TIMERs available */
+#define WTIMER_PRESENT /**< WTIMER is available in this part */
+#define WTIMER_COUNT 2 /**< 2 WTIMERs available */
+#define USART_PRESENT /**< USART is available in this part */
+#define USART_COUNT 4 /**< 4 USARTs available */
+#define LEUART_PRESENT /**< LEUART is available in this part */
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */
+#define LETIMER_PRESENT /**< LETIMER is available in this part */
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
+#define PCNT_PRESENT /**< PCNT is available in this part */
+#define PCNT_COUNT 3 /**< 3 PCNTs available */
+#define I2C_PRESENT /**< I2C is available in this part */
+#define I2C_COUNT 2 /**< 2 I2Cs available */
+#define ADC_PRESENT /**< ADC is available in this part */
+#define ADC_COUNT 1 /**< 1 ADCs available */
+#define ACMP_PRESENT /**< ACMP is available in this part */
+#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
+#define VDAC_PRESENT /**< VDAC is available in this part */
+#define VDAC_COUNT 1 /**< 1 VDACs available */
+#define WDOG_PRESENT /**< WDOG is available in this part */
+#define WDOG_COUNT 2 /**< 2 WDOGs available */
+#define TRNG_PRESENT /**< TRNG is available in this part */
+#define TRNG_COUNT 1 /**< 1 TRNGs available */
+#define MSC_PRESENT /**< MSC is available in this part */
+#define MSC_COUNT 1 /**< 1 MSC available */
+#define EMU_PRESENT /**< EMU is available in this part */
+#define EMU_COUNT 1 /**< 1 EMU available */
+#define RMU_PRESENT /**< RMU is available in this part */
+#define RMU_COUNT 1 /**< 1 RMU available */
+#define CMU_PRESENT /**< CMU is available in this part */
+#define CMU_COUNT 1 /**< 1 CMU available */
+#define GPIO_PRESENT /**< GPIO is available in this part */
+#define GPIO_COUNT 1 /**< 1 GPIO available */
+#define PRS_PRESENT /**< PRS is available in this part */
+#define PRS_COUNT 1 /**< 1 PRS available */
+#define LDMA_PRESENT /**< LDMA is available in this part */
+#define LDMA_COUNT 1 /**< 1 LDMA available */
+#define FPUEH_PRESENT /**< FPUEH is available in this part */
+#define FPUEH_COUNT 1 /**< 1 FPUEH available */
+#define GPCRC_PRESENT /**< GPCRC is available in this part */
+#define GPCRC_COUNT 1 /**< 1 GPCRC available */
+#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
+#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
+#define CSEN_PRESENT /**< CSEN is available in this part */
+#define CSEN_COUNT 1 /**< 1 CSEN available */
+#define LESENSE_PRESENT /**< LESENSE is available in this part */
+#define LESENSE_COUNT 1 /**< 1 LESENSE available */
+#define RTCC_PRESENT /**< RTCC is available in this part */
+#define RTCC_COUNT 1 /**< 1 RTCC available */
+#define ETM_PRESENT /**< ETM is available in this part */
+#define ETM_COUNT 1 /**< 1 ETM available */
+#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
+#define SMU_PRESENT /**< SMU is available in this part */
+#define SMU_COUNT 1 /**< 1 SMU available */
+#define DCDC_PRESENT /**< DCDC is available in this part */
+#define DCDC_COUNT 1 /**< 1 DCDC available */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32fg12p.h" /* System Header File */
/** @} End of group EFR32FG12P431F1024GL125_Part */
-/**************************************************************************//**
- * @defgroup EFR32FG12P431F1024GL125_Peripheral_TypeDefs EFR32FG12P431F1024GL125 Peripheral TypeDefs
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024GL125_Peripheral_TypeDefs Peripheral TypeDefs
* @{
* @brief Device Specific Peripheral Register Structures
- *****************************************************************************/
+ ******************************************************************************/
#include "efr32fg12p_msc.h"
#include "efr32fg12p_emu.h"
@@ -372,10 +386,10 @@ typedef enum IRQn
/** @} End of group EFR32FG12P431F1024GL125_Peripheral_TypeDefs */
-/**************************************************************************//**
- * @defgroup EFR32FG12P431F1024GL125_Peripheral_Base EFR32FG12P431F1024GL125 Peripheral Memory Map
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024GL125_Peripheral_Base Peripheral Memory Map
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC_BASE (0x400E0000UL) /**< MSC base address */
#define EMU_BASE (0x400E3000UL) /**< EMU base address */
@@ -425,10 +439,10 @@ typedef enum IRQn
/** @} End of group EFR32FG12P431F1024GL125_Peripheral_Base */
-/**************************************************************************//**
- * @defgroup EFR32FG12P431F1024GL125_Peripheral_Declaration EFR32FG12P431F1024GL125 Peripheral Declarations
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024GL125_Peripheral_Declaration Peripheral Declarations
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
@@ -476,10 +490,10 @@ typedef enum IRQn
/** @} End of group EFR32FG12P431F1024GL125_Peripheral_Declaration */
-/**************************************************************************//**
- * @defgroup EFR32FG12P431F1024GL125_Peripheral_Offsets EFR32FG12P431F1024GL125 Peripheral Offsets
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024GL125_Peripheral_Offsets Peripheral Offsets
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */
#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
@@ -498,19 +512,20 @@ typedef enum IRQn
/** @} End of group EFR32FG12P431F1024GL125_Peripheral_Offsets */
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P431F1024GL125_BitFields EFR32FG12P431F1024GL125 Bit Fields
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024GL125_BitFields Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
#include "efr32fg12p_prs_signals.h"
#include "efr32fg12p_dmareq.h"
-/**************************************************************************//**
- * @defgroup EFR32FG12P431F1024GL125_WTIMER_BitFields EFR32FG12P431F1024GL125_WTIMER Bit Fields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P431F1024GL125_WTIMER
+ * @{
+ * @defgroup EFR32FG12P431F1024GL125_WTIMER_BitFields WTIMER Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for WTIMER CTRL */
#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */
@@ -626,7 +641,7 @@ typedef enum IRQn
#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */
#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */
+#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */
#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */
#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */
#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
@@ -1011,13 +1026,13 @@ typedef enum IRQn
#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */
-#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */
+#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */
-#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */
+#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */
@@ -1731,7 +1746,7 @@ typedef enum IRQn
#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */
#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */
+#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */
#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */
#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */
#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
@@ -1998,33 +2013,23 @@ typedef enum IRQn
#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */
-#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */
+#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */
-#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */
+#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */
+/** @} */
/** @} End of group EFR32FG12P431F1024GL125_WTIMER */
-
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P431F1024GL125_SYSTICK_BitFields EFR32FG12P431F1024GL125_SYSTICK Bit Fields
- * @{
- *****************************************************************************/
-
-/** @} End of group EFR32FG12P431F1024GL125_SYSTICK */
-
-
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P431F1024GL125_UNLOCK EFR32FG12P431F1024GL125 Unlock Codes
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024GL125_UNLOCK Unlock Codes
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
@@ -2037,16 +2042,9 @@ typedef enum IRQn
/** @} End of group EFR32FG12P431F1024GL125_BitFields */
-/**************************************************************************//**
- * @defgroup EFR32FG12P431F1024GL125_Alternate_Function EFR32FG12P431F1024GL125 Alternate Function
- * @{
- *****************************************************************************/
-
#include "efr32fg12p_af_ports.h"
#include "efr32fg12p_af_pins.h"
-/** @} End of group EFR32FG12P431F1024GL125_Alternate_Function */
-
/** @} End of group EFR32FG12P431F1024GL125 */
/** @} End of group Parts */
@@ -2054,4 +2052,5 @@ typedef enum IRQn
#ifdef __cplusplus
}
#endif
+
#endif /* EFR32FG12P431F1024GL125_H */
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p431f1024gm48.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p431f1024gm48.h
similarity index 91%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p431f1024gm48.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p431f1024gm48.h
index 5a24ee6a..10d4b804 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p431f1024gm48.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p431f1024gm48.h
@@ -1,35 +1,39 @@
-/**************************************************************************//**
- * @file efr32fg12p431f1024gm48.h
+/***************************************************************************//**
+ * @file
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
* for EFR32FG12P431F1024GM48
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
#ifndef EFR32FG12P431F1024GM48_H
#define EFR32FG12P431F1024GM48_H
@@ -38,111 +42,120 @@
extern "C" {
#endif
-/**************************************************************************//**
+/***************************************************************************//**
* @addtogroup Parts
* @{
- *****************************************************************************/
+ ******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFR32FG12P431F1024GM48 EFR32FG12P431F1024GM48
* @{
- *****************************************************************************/
+ ******************************************************************************/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
+typedef enum IRQn{
/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
- NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */
- HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */
- MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
/****** EFR32FG12P Peripheral Interrupt Numbers ********************************************/
- EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */
- WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */
- WDOG1_IRQn = 3, /*!< 3 EFR32 WDOG1 Interrupt */
- LDMA_IRQn = 9, /*!< 9 EFR32 LDMA Interrupt */
- GPIO_EVEN_IRQn = 10, /*!< 10 EFR32 GPIO_EVEN Interrupt */
- TIMER0_IRQn = 11, /*!< 11 EFR32 TIMER0 Interrupt */
- USART0_RX_IRQn = 12, /*!< 12 EFR32 USART0_RX Interrupt */
- USART0_TX_IRQn = 13, /*!< 13 EFR32 USART0_TX Interrupt */
- ACMP0_IRQn = 14, /*!< 14 EFR32 ACMP0 Interrupt */
- ADC0_IRQn = 15, /*!< 15 EFR32 ADC0 Interrupt */
- IDAC0_IRQn = 16, /*!< 16 EFR32 IDAC0 Interrupt */
- I2C0_IRQn = 17, /*!< 17 EFR32 I2C0 Interrupt */
- GPIO_ODD_IRQn = 18, /*!< 18 EFR32 GPIO_ODD Interrupt */
- TIMER1_IRQn = 19, /*!< 19 EFR32 TIMER1 Interrupt */
- USART1_RX_IRQn = 20, /*!< 20 EFR32 USART1_RX Interrupt */
- USART1_TX_IRQn = 21, /*!< 21 EFR32 USART1_TX Interrupt */
- LEUART0_IRQn = 22, /*!< 22 EFR32 LEUART0 Interrupt */
- PCNT0_IRQn = 23, /*!< 23 EFR32 PCNT0 Interrupt */
- CMU_IRQn = 24, /*!< 24 EFR32 CMU Interrupt */
- MSC_IRQn = 25, /*!< 25 EFR32 MSC Interrupt */
- CRYPTO0_IRQn = 26, /*!< 26 EFR32 CRYPTO0 Interrupt */
- LETIMER0_IRQn = 27, /*!< 27 EFR32 LETIMER0 Interrupt */
- RTCC_IRQn = 30, /*!< 30 EFR32 RTCC Interrupt */
- CRYOTIMER_IRQn = 32, /*!< 32 EFR32 CRYOTIMER Interrupt */
- FPUEH_IRQn = 34, /*!< 34 EFR32 FPUEH Interrupt */
- SMU_IRQn = 35, /*!< 35 EFR32 SMU Interrupt */
- WTIMER0_IRQn = 36, /*!< 36 EFR32 WTIMER0 Interrupt */
- WTIMER1_IRQn = 37, /*!< 37 EFR32 WTIMER1 Interrupt */
- PCNT1_IRQn = 38, /*!< 38 EFR32 PCNT1 Interrupt */
- PCNT2_IRQn = 39, /*!< 39 EFR32 PCNT2 Interrupt */
- USART2_RX_IRQn = 40, /*!< 40 EFR32 USART2_RX Interrupt */
- USART2_TX_IRQn = 41, /*!< 41 EFR32 USART2_TX Interrupt */
- I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */
- USART3_RX_IRQn = 43, /*!< 43 EFR32 USART3_RX Interrupt */
- USART3_TX_IRQn = 44, /*!< 44 EFR32 USART3_TX Interrupt */
- VDAC0_IRQn = 45, /*!< 45 EFR32 VDAC0 Interrupt */
- CSEN_IRQn = 46, /*!< 46 EFR32 CSEN Interrupt */
- LESENSE_IRQn = 47, /*!< 47 EFR32 LESENSE Interrupt */
- CRYPTO1_IRQn = 48, /*!< 48 EFR32 CRYPTO1 Interrupt */
- TRNG0_IRQn = 49, /*!< 49 EFR32 TRNG0 Interrupt */
+ EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
+ WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 3, /*!< 16+3 EFR32 WDOG1 Interrupt */
+ FRC_IRQn = 4, /*!< 16+4 EFR32 FRC Interrupt */
+ MODEM_IRQn = 5, /*!< 16+5 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 6, /*!< 16+6 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 7, /*!< 16+7 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 8, /*!< 16+8 EFR32 BUFC Interrupt */
+ LDMA_IRQn = 9, /*!< 16+9 EFR32 LDMA Interrupt */
+ GPIO_EVEN_IRQn = 10, /*!< 16+10 EFR32 GPIO_EVEN Interrupt */
+ TIMER0_IRQn = 11, /*!< 16+11 EFR32 TIMER0 Interrupt */
+ USART0_RX_IRQn = 12, /*!< 16+12 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 13, /*!< 16+13 EFR32 USART0_TX Interrupt */
+ ACMP0_IRQn = 14, /*!< 16+14 EFR32 ACMP0 Interrupt */
+ ADC0_IRQn = 15, /*!< 16+15 EFR32 ADC0 Interrupt */
+ IDAC0_IRQn = 16, /*!< 16+16 EFR32 IDAC0 Interrupt */
+ I2C0_IRQn = 17, /*!< 16+17 EFR32 I2C0 Interrupt */
+ GPIO_ODD_IRQn = 18, /*!< 16+18 EFR32 GPIO_ODD Interrupt */
+ TIMER1_IRQn = 19, /*!< 16+19 EFR32 TIMER1 Interrupt */
+ USART1_RX_IRQn = 20, /*!< 16+20 EFR32 USART1_RX Interrupt */
+ USART1_TX_IRQn = 21, /*!< 16+21 EFR32 USART1_TX Interrupt */
+ LEUART0_IRQn = 22, /*!< 16+22 EFR32 LEUART0 Interrupt */
+ PCNT0_IRQn = 23, /*!< 16+23 EFR32 PCNT0 Interrupt */
+ CMU_IRQn = 24, /*!< 16+24 EFR32 CMU Interrupt */
+ MSC_IRQn = 25, /*!< 16+25 EFR32 MSC Interrupt */
+ CRYPTO0_IRQn = 26, /*!< 16+26 EFR32 CRYPTO0 Interrupt */
+ LETIMER0_IRQn = 27, /*!< 16+27 EFR32 LETIMER0 Interrupt */
+ AGC_IRQn = 28, /*!< 16+28 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 29, /*!< 16+29 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 30, /*!< 16+30 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 31, /*!< 16+31 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 32, /*!< 16+32 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 33, /*!< 16+33 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 34, /*!< 16+34 EFR32 FPUEH Interrupt */
+ SMU_IRQn = 35, /*!< 16+35 EFR32 SMU Interrupt */
+ WTIMER0_IRQn = 36, /*!< 16+36 EFR32 WTIMER0 Interrupt */
+ WTIMER1_IRQn = 37, /*!< 16+37 EFR32 WTIMER1 Interrupt */
+ PCNT1_IRQn = 38, /*!< 16+38 EFR32 PCNT1 Interrupt */
+ PCNT2_IRQn = 39, /*!< 16+39 EFR32 PCNT2 Interrupt */
+ USART2_RX_IRQn = 40, /*!< 16+40 EFR32 USART2_RX Interrupt */
+ USART2_TX_IRQn = 41, /*!< 16+41 EFR32 USART2_TX Interrupt */
+ I2C1_IRQn = 42, /*!< 16+42 EFR32 I2C1 Interrupt */
+ USART3_RX_IRQn = 43, /*!< 16+43 EFR32 USART3_RX Interrupt */
+ USART3_TX_IRQn = 44, /*!< 16+44 EFR32 USART3_TX Interrupt */
+ VDAC0_IRQn = 45, /*!< 16+45 EFR32 VDAC0 Interrupt */
+ CSEN_IRQn = 46, /*!< 16+46 EFR32 CSEN Interrupt */
+ LESENSE_IRQn = 47, /*!< 16+47 EFR32 LESENSE Interrupt */
+ CRYPTO1_IRQn = 48, /*!< 16+48 EFR32 CRYPTO1 Interrupt */
+ TRNG0_IRQn = 49, /*!< 16+49 EFR32 TRNG0 Interrupt */
} IRQn_Type;
#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */
-/**************************************************************************//**
- * @defgroup EFR32FG12P431F1024GM48_Core EFR32FG12P431F1024GM48 Core
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024GM48_Core Core
* @{
* @brief Processor and Core Peripheral Section
- *****************************************************************************/
-#define __MPU_PRESENT 1 /**< Presence of MPU */
-#define __FPU_PRESENT 1 /**< Presence of FPU */
-#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
/** @} End of group EFR32FG12P431F1024GM48_Core */
-/**************************************************************************//**
-* @defgroup EFR32FG12P431F1024GM48_Part EFR32FG12P431F1024GM48 Part
-* @{
-******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024GM48_Part Part
+ * @{
+ ******************************************************************************/
/** Part family */
-#define _EFR32_FLEX_FAMILY 1 /**< FLEX Gecko RF SoC Family */
-#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
-#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
-#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */
-#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1
-#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2
-#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3
-#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ
-#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
-#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */
+#define _EFR32_FLEX_FAMILY 1 /**< FLEX Gecko RF SoC Family */
+#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
+#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /**< Radio type */
+#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */
/* If part number is not defined as compiler option, define it */
#if !defined(EFR32FG12P431F1024GM48)
@@ -153,179 +166,180 @@ typedef enum IRQn
#define PART_NUMBER "EFR32FG12P431F1024GM48" /**< Part Number */
/** Memory Base addresses and limits */
-#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */
-#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */
-#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */
-#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */
-#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */
-#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */
-#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */
-#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */
-#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */
-#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */
-#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */
-#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */
-#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */
-#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */
-#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
-#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
-#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */
-#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */
-#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */
-#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */
-#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */
-#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */
-#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */
-#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */
-#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */
-#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */
-#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */
-#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
-#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
-#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */
-#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */
-#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */
-#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */
-#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */
-#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
-#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
-#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
-#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
-#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
-#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */
-#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */
-#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */
-#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */
-#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */
-#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */
-#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */
-#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
-#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
-#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
-#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
-#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */
-#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */
-#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
-#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
-#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
-#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
-#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
-#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
-#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
-#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */
-#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */
-#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */
-#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */
-#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */
-#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */
-#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */
-#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */
-#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */
-#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */
-#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
-#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */
-#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */
-#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */
+#define CRYPTO1_BITCLR_MEM_BASE (0x440F0400UL) /**< CRYPTO1_BITCLR base address */
+#define CRYPTO1_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO1_BITCLR available address space */
+#define CRYPTO1_BITCLR_MEM_END (0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
+#define CRYPTO1_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
+#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */
+#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */
+#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */
+#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */
+#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */
+#define RAM2_MEM_SIZE (0x800UL) /**< RAM2 available address space */
+#define RAM2_MEM_END (0x200407FFUL) /**< RAM2 end address */
+#define RAM2_MEM_BITS (0x0000000BUL) /**< RAM2 used bits */
+#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */
+#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */
+#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
+#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
+#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
+#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
+#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
+#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
+#define CRYPTO1_MEM_BASE (0x400F0400UL) /**< CRYPTO1 base address */
+#define CRYPTO1_MEM_SIZE (0x400UL) /**< CRYPTO1 available address space */
+#define CRYPTO1_MEM_END (0x400F07FFUL) /**< CRYPTO1 end address */
+#define CRYPTO1_MEM_BITS (0x0000000AUL) /**< CRYPTO1 used bits */
+#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */
+#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */
+#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */
+#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
+#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
+#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
+#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
+#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */
+#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */
+#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */
+#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */
+#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */
+#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */
+#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */
+#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define CRYPTO1_BITSET_MEM_BASE (0x460F0400UL) /**< CRYPTO1_BITSET base address */
+#define CRYPTO1_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO1_BITSET available address space */
+#define CRYPTO1_BITSET_MEM_END (0x460F07FFUL) /**< CRYPTO1_BITSET end address */
+#define CRYPTO1_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITSET used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x20000UL) /**< RAM available address space */
+#define RAM_MEM_END (0x2001FFFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x00000011UL) /**< RAM used bits */
+#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */
+#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */
+#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */
+#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */
+#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
+#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
+#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
+#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xF0000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460EFFFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xF0000UL) /**< PER available address space */
+#define PER_MEM_END (0x400EFFFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */
+#define RAM2_CODE_MEM_SIZE (0x800UL) /**< RAM2_CODE available address space */
+#define RAM2_CODE_MEM_END (0x100407FFUL) /**< RAM2_CODE end address */
+#define RAM2_CODE_MEM_BITS (0x0000000BUL) /**< RAM2_CODE used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xF0000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440EFFFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
/** Bit banding area */
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
/** Flash and SRAM limits for EFR32FG12P431F1024GM48 */
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */
-#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size (interleaving off) */
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
-#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */
/** AF channels connect the different on-chip peripherals with the af-mux */
-#define AFCHAN_MAX 136
-#define AFCHANLOC_MAX 32
+#define AFCHAN_MAX 136U
+/** AF channel maximum location number */
+#define AFCHANLOC_MAX 32U
/** Analog AF channels */
-#define AFACHAN_MAX 125
+#define AFACHAN_MAX 125U
/* Part number capabilities */
-#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
-#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */
-#define TIMER_PRESENT /**< TIMER is available in this part */
-#define TIMER_COUNT 2 /**< 2 TIMERs available */
-#define WTIMER_PRESENT /**< WTIMER is available in this part */
-#define WTIMER_COUNT 2 /**< 2 WTIMERs available */
-#define USART_PRESENT /**< USART is available in this part */
-#define USART_COUNT 4 /**< 4 USARTs available */
-#define LEUART_PRESENT /**< LEUART is available in this part */
-#define LEUART_COUNT 1 /**< 1 LEUARTs available */
-#define LETIMER_PRESENT /**< LETIMER is available in this part */
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
-#define PCNT_PRESENT /**< PCNT is available in this part */
-#define PCNT_COUNT 3 /**< 3 PCNTs available */
-#define I2C_PRESENT /**< I2C is available in this part */
-#define I2C_COUNT 2 /**< 2 I2Cs available */
-#define ADC_PRESENT /**< ADC is available in this part */
-#define ADC_COUNT 1 /**< 1 ADCs available */
-#define ACMP_PRESENT /**< ACMP is available in this part */
-#define ACMP_COUNT 2 /**< 2 ACMPs available */
-#define IDAC_PRESENT /**< IDAC is available in this part */
-#define IDAC_COUNT 1 /**< 1 IDACs available */
-#define VDAC_PRESENT /**< VDAC is available in this part */
-#define VDAC_COUNT 1 /**< 1 VDACs available */
-#define WDOG_PRESENT /**< WDOG is available in this part */
-#define WDOG_COUNT 2 /**< 2 WDOGs available */
-#define TRNG_PRESENT /**< TRNG is available in this part */
-#define TRNG_COUNT 1 /**< 1 TRNGs available */
-#define SYSTICK_PRESENT
-#define SYSTICK_COUNT 1
-#define MSC_PRESENT
-#define MSC_COUNT 1
-#define EMU_PRESENT
-#define EMU_COUNT 1
-#define RMU_PRESENT
-#define RMU_COUNT 1
-#define CMU_PRESENT
-#define CMU_COUNT 1
-#define GPIO_PRESENT
-#define GPIO_COUNT 1
-#define PRS_PRESENT
-#define PRS_COUNT 1
-#define LDMA_PRESENT
-#define LDMA_COUNT 1
-#define FPUEH_PRESENT
-#define FPUEH_COUNT 1
-#define GPCRC_PRESENT
-#define GPCRC_COUNT 1
-#define CRYOTIMER_PRESENT
-#define CRYOTIMER_COUNT 1
-#define CSEN_PRESENT
-#define CSEN_COUNT 1
-#define LESENSE_PRESENT
-#define LESENSE_COUNT 1
-#define RTCC_PRESENT
-#define RTCC_COUNT 1
-#define ETM_PRESENT
-#define ETM_COUNT 1
-#define BOOTLOADER_PRESENT
-#define BOOTLOADER_COUNT 1
-#define SMU_PRESENT
-#define SMU_COUNT 1
-
-#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
-#include "system_efr32fg12p.h" /* System Header File */
+#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
+#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */
+#define TIMER_PRESENT /**< TIMER is available in this part */
+#define TIMER_COUNT 2 /**< 2 TIMERs available */
+#define WTIMER_PRESENT /**< WTIMER is available in this part */
+#define WTIMER_COUNT 2 /**< 2 WTIMERs available */
+#define USART_PRESENT /**< USART is available in this part */
+#define USART_COUNT 4 /**< 4 USARTs available */
+#define LEUART_PRESENT /**< LEUART is available in this part */
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */
+#define LETIMER_PRESENT /**< LETIMER is available in this part */
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
+#define PCNT_PRESENT /**< PCNT is available in this part */
+#define PCNT_COUNT 3 /**< 3 PCNTs available */
+#define I2C_PRESENT /**< I2C is available in this part */
+#define I2C_COUNT 2 /**< 2 I2Cs available */
+#define ADC_PRESENT /**< ADC is available in this part */
+#define ADC_COUNT 1 /**< 1 ADCs available */
+#define ACMP_PRESENT /**< ACMP is available in this part */
+#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
+#define VDAC_PRESENT /**< VDAC is available in this part */
+#define VDAC_COUNT 1 /**< 1 VDACs available */
+#define WDOG_PRESENT /**< WDOG is available in this part */
+#define WDOG_COUNT 2 /**< 2 WDOGs available */
+#define TRNG_PRESENT /**< TRNG is available in this part */
+#define TRNG_COUNT 1 /**< 1 TRNGs available */
+#define MSC_PRESENT /**< MSC is available in this part */
+#define MSC_COUNT 1 /**< 1 MSC available */
+#define EMU_PRESENT /**< EMU is available in this part */
+#define EMU_COUNT 1 /**< 1 EMU available */
+#define RMU_PRESENT /**< RMU is available in this part */
+#define RMU_COUNT 1 /**< 1 RMU available */
+#define CMU_PRESENT /**< CMU is available in this part */
+#define CMU_COUNT 1 /**< 1 CMU available */
+#define GPIO_PRESENT /**< GPIO is available in this part */
+#define GPIO_COUNT 1 /**< 1 GPIO available */
+#define PRS_PRESENT /**< PRS is available in this part */
+#define PRS_COUNT 1 /**< 1 PRS available */
+#define LDMA_PRESENT /**< LDMA is available in this part */
+#define LDMA_COUNT 1 /**< 1 LDMA available */
+#define FPUEH_PRESENT /**< FPUEH is available in this part */
+#define FPUEH_COUNT 1 /**< 1 FPUEH available */
+#define GPCRC_PRESENT /**< GPCRC is available in this part */
+#define GPCRC_COUNT 1 /**< 1 GPCRC available */
+#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
+#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
+#define CSEN_PRESENT /**< CSEN is available in this part */
+#define CSEN_COUNT 1 /**< 1 CSEN available */
+#define LESENSE_PRESENT /**< LESENSE is available in this part */
+#define LESENSE_COUNT 1 /**< 1 LESENSE available */
+#define RTCC_PRESENT /**< RTCC is available in this part */
+#define RTCC_COUNT 1 /**< 1 RTCC available */
+#define ETM_PRESENT /**< ETM is available in this part */
+#define ETM_COUNT 1 /**< 1 ETM available */
+#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
+#define SMU_PRESENT /**< SMU is available in this part */
+#define SMU_COUNT 1 /**< 1 SMU available */
+#define DCDC_PRESENT /**< DCDC is available in this part */
+#define DCDC_COUNT 1 /**< 1 DCDC available */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32fg12p.h" /* System Header File */
/** @} End of group EFR32FG12P431F1024GM48_Part */
-/**************************************************************************//**
- * @defgroup EFR32FG12P431F1024GM48_Peripheral_TypeDefs EFR32FG12P431F1024GM48 Peripheral TypeDefs
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024GM48_Peripheral_TypeDefs Peripheral TypeDefs
* @{
* @brief Device Specific Peripheral Register Structures
- *****************************************************************************/
+ ******************************************************************************/
#include "efr32fg12p_msc.h"
#include "efr32fg12p_emu.h"
@@ -372,10 +386,10 @@ typedef enum IRQn
/** @} End of group EFR32FG12P431F1024GM48_Peripheral_TypeDefs */
-/**************************************************************************//**
- * @defgroup EFR32FG12P431F1024GM48_Peripheral_Base EFR32FG12P431F1024GM48 Peripheral Memory Map
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024GM48_Peripheral_Base Peripheral Memory Map
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC_BASE (0x400E0000UL) /**< MSC base address */
#define EMU_BASE (0x400E3000UL) /**< EMU base address */
@@ -425,10 +439,10 @@ typedef enum IRQn
/** @} End of group EFR32FG12P431F1024GM48_Peripheral_Base */
-/**************************************************************************//**
- * @defgroup EFR32FG12P431F1024GM48_Peripheral_Declaration EFR32FG12P431F1024GM48 Peripheral Declarations
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024GM48_Peripheral_Declaration Peripheral Declarations
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
@@ -476,10 +490,10 @@ typedef enum IRQn
/** @} End of group EFR32FG12P431F1024GM48_Peripheral_Declaration */
-/**************************************************************************//**
- * @defgroup EFR32FG12P431F1024GM48_Peripheral_Offsets EFR32FG12P431F1024GM48 Peripheral Offsets
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024GM48_Peripheral_Offsets Peripheral Offsets
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */
#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
@@ -498,19 +512,20 @@ typedef enum IRQn
/** @} End of group EFR32FG12P431F1024GM48_Peripheral_Offsets */
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P431F1024GM48_BitFields EFR32FG12P431F1024GM48 Bit Fields
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024GM48_BitFields Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
#include "efr32fg12p_prs_signals.h"
#include "efr32fg12p_dmareq.h"
-/**************************************************************************//**
- * @defgroup EFR32FG12P431F1024GM48_WTIMER_BitFields EFR32FG12P431F1024GM48_WTIMER Bit Fields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P431F1024GM48_WTIMER
+ * @{
+ * @defgroup EFR32FG12P431F1024GM48_WTIMER_BitFields WTIMER Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for WTIMER CTRL */
#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */
@@ -626,7 +641,7 @@ typedef enum IRQn
#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */
#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */
+#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */
#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */
#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */
#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
@@ -1011,13 +1026,13 @@ typedef enum IRQn
#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */
-#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */
+#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */
-#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */
+#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */
@@ -1731,7 +1746,7 @@ typedef enum IRQn
#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */
#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */
+#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */
#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */
#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */
#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
@@ -1998,33 +2013,23 @@ typedef enum IRQn
#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */
-#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */
+#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */
-#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */
+#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */
+/** @} */
/** @} End of group EFR32FG12P431F1024GM48_WTIMER */
-
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P431F1024GM48_SYSTICK_BitFields EFR32FG12P431F1024GM48_SYSTICK Bit Fields
- * @{
- *****************************************************************************/
-
-/** @} End of group EFR32FG12P431F1024GM48_SYSTICK */
-
-
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P431F1024GM48_UNLOCK EFR32FG12P431F1024GM48 Unlock Codes
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024GM48_UNLOCK Unlock Codes
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
@@ -2037,16 +2042,9 @@ typedef enum IRQn
/** @} End of group EFR32FG12P431F1024GM48_BitFields */
-/**************************************************************************//**
- * @defgroup EFR32FG12P431F1024GM48_Alternate_Function EFR32FG12P431F1024GM48 Alternate Function
- * @{
- *****************************************************************************/
-
#include "efr32fg12p_af_ports.h"
#include "efr32fg12p_af_pins.h"
-/** @} End of group EFR32FG12P431F1024GM48_Alternate_Function */
-
/** @} End of group EFR32FG12P431F1024GM48 */
/** @} End of group Parts */
@@ -2054,4 +2052,5 @@ typedef enum IRQn
#ifdef __cplusplus
}
#endif
+
#endif /* EFR32FG12P431F1024GM48_H */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p231f512im48.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p431f1024gm68.h
similarity index 92%
rename from mcu/efr/common/vendor/efr32fg13/efr32fg13p231f512im48.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p431f1024gm68.h
index 77f27f07..39e1f6a2 100644
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p231f512im48.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p431f1024gm68.h
@@ -1,35 +1,33 @@
-/**************************************************************************//**
- * @file efr32fg13p231f512im48.h
+/***************************************************************************//**
+ * @file
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
- * for EFR32FG13P231F512IM48
- * @version 5.4.0
- ******************************************************************************
+ * for EFR32FG12P431F1024GM68
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#if defined(__ICCARM__)
#pragma system_include /* Treat file as system include file. */
@@ -37,22 +35,22 @@
#pragma clang system_header /* Treat file as system include file. */
#endif
-#ifndef EFR32FG13P231F512IM48_H
-#define EFR32FG13P231F512IM48_H
+#ifndef EFR32FG12P431F1024GM68_H
+#define EFR32FG12P431F1024GM68_H
#ifdef __cplusplus
extern "C" {
#endif
-/**************************************************************************//**
+/***************************************************************************//**
* @addtogroup Parts
* @{
- *****************************************************************************/
+ ******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512IM48 EFR32FG13P231F512IM48
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024GM68 EFR32FG12P431F1024GM68
* @{
- *****************************************************************************/
+ ******************************************************************************/
/** Interrupt Number Definition */
typedef enum IRQn{
@@ -67,11 +65,17 @@ typedef enum IRQn{
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
-/****** EFR32FG13P Peripheral Interrupt Numbers ********************************************/
+/****** EFR32FG12P Peripheral Interrupt Numbers ********************************************/
EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
WDOG1_IRQn = 3, /*!< 16+3 EFR32 WDOG1 Interrupt */
+ FRC_IRQn = 4, /*!< 16+4 EFR32 FRC Interrupt */
+ MODEM_IRQn = 5, /*!< 16+5 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 6, /*!< 16+6 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 7, /*!< 16+7 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 8, /*!< 16+8 EFR32 BUFC Interrupt */
LDMA_IRQn = 9, /*!< 16+9 EFR32 LDMA Interrupt */
GPIO_EVEN_IRQn = 10, /*!< 16+10 EFR32 GPIO_EVEN Interrupt */
TIMER0_IRQn = 11, /*!< 16+11 EFR32 TIMER0 Interrupt */
@@ -91,166 +95,175 @@ typedef enum IRQn{
MSC_IRQn = 25, /*!< 16+25 EFR32 MSC Interrupt */
CRYPTO0_IRQn = 26, /*!< 16+26 EFR32 CRYPTO0 Interrupt */
LETIMER0_IRQn = 27, /*!< 16+27 EFR32 LETIMER0 Interrupt */
- RTCC_IRQn = 31, /*!< 16+31 EFR32 RTCC Interrupt */
- CRYOTIMER_IRQn = 33, /*!< 16+33 EFR32 CRYOTIMER Interrupt */
- FPUEH_IRQn = 35, /*!< 16+35 EFR32 FPUEH Interrupt */
- SMU_IRQn = 36, /*!< 16+36 EFR32 SMU Interrupt */
- WTIMER0_IRQn = 37, /*!< 16+37 EFR32 WTIMER0 Interrupt */
- USART2_RX_IRQn = 38, /*!< 16+38 EFR32 USART2_RX Interrupt */
- USART2_TX_IRQn = 39, /*!< 16+39 EFR32 USART2_TX Interrupt */
- I2C1_IRQn = 40, /*!< 16+40 EFR32 I2C1 Interrupt */
- VDAC0_IRQn = 41, /*!< 16+41 EFR32 VDAC0 Interrupt */
- CSEN_IRQn = 42, /*!< 16+42 EFR32 CSEN Interrupt */
- LESENSE_IRQn = 43, /*!< 16+43 EFR32 LESENSE Interrupt */
- CRYPTO1_IRQn = 44, /*!< 16+44 EFR32 CRYPTO1 Interrupt */
- TRNG0_IRQn = 45, /*!< 16+45 EFR32 TRNG0 Interrupt */
+ AGC_IRQn = 28, /*!< 16+28 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 29, /*!< 16+29 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 30, /*!< 16+30 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 31, /*!< 16+31 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 32, /*!< 16+32 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 33, /*!< 16+33 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 34, /*!< 16+34 EFR32 FPUEH Interrupt */
+ SMU_IRQn = 35, /*!< 16+35 EFR32 SMU Interrupt */
+ WTIMER0_IRQn = 36, /*!< 16+36 EFR32 WTIMER0 Interrupt */
+ WTIMER1_IRQn = 37, /*!< 16+37 EFR32 WTIMER1 Interrupt */
+ PCNT1_IRQn = 38, /*!< 16+38 EFR32 PCNT1 Interrupt */
+ PCNT2_IRQn = 39, /*!< 16+39 EFR32 PCNT2 Interrupt */
+ USART2_RX_IRQn = 40, /*!< 16+40 EFR32 USART2_RX Interrupt */
+ USART2_TX_IRQn = 41, /*!< 16+41 EFR32 USART2_TX Interrupt */
+ I2C1_IRQn = 42, /*!< 16+42 EFR32 I2C1 Interrupt */
+ USART3_RX_IRQn = 43, /*!< 16+43 EFR32 USART3_RX Interrupt */
+ USART3_TX_IRQn = 44, /*!< 16+44 EFR32 USART3_TX Interrupt */
+ VDAC0_IRQn = 45, /*!< 16+45 EFR32 VDAC0 Interrupt */
+ CSEN_IRQn = 46, /*!< 16+46 EFR32 CSEN Interrupt */
+ LESENSE_IRQn = 47, /*!< 16+47 EFR32 LESENSE Interrupt */
+ CRYPTO1_IRQn = 48, /*!< 16+48 EFR32 CRYPTO1 Interrupt */
+ TRNG0_IRQn = 49, /*!< 16+49 EFR32 TRNG0 Interrupt */
} IRQn_Type;
#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512IM48_Core Core
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024GM68_Core Core
* @{
* @brief Processor and Core Peripheral Section
- *****************************************************************************/
-#define __MPU_PRESENT 1 /**< Presence of MPU */
-#define __FPU_PRESENT 1 /**< Presence of FPU */
-#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
-/** @} End of group EFR32FG13P231F512IM48_Core */
+/** @} End of group EFR32FG12P431F1024GM68_Core */
-/**************************************************************************//**
-* @defgroup EFR32FG13P231F512IM48_Part Part
-* @{
-******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024GM68_Part Part
+ * @{
+ ******************************************************************************/
/** Part family */
#define _EFR32_FLEX_FAMILY 1 /**< FLEX Gecko RF SoC Family */
#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG_3 /**< Series 1, Configuration 3 */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG 3 /**< Series 1, Configuration 3 */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID 89 /**< Silicon Labs internal use only, may change any time */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID_89 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /**< Silicon Labs internal use only, may change any time */
#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /**< Radio type */
#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN_3 /**< @deprecated Platform 2, generation 3 */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN 3 /**< @deprecated Platform 2, generation 3 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */
/* If part number is not defined as compiler option, define it */
-#if !defined(EFR32FG13P231F512IM48)
-#define EFR32FG13P231F512IM48 1 /**< FLEX Gecko Part */
+#if !defined(EFR32FG12P431F1024GM68)
+#define EFR32FG12P431F1024GM68 1 /**< FLEX Gecko Part */
#endif
/** Configure part number */
-#define PART_NUMBER "EFR32FG13P231F512IM48" /**< Part Number */
+#define PART_NUMBER "EFR32FG12P431F1024GM68" /**< Part Number */
/** Memory Base addresses and limits */
-#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */
-#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM0_CODE available address space */
-#define RAM0_CODE_MEM_END ((uint32_t) 0x10007FFFUL) /**< RAM0_CODE end address */
-#define RAM0_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM0_CODE used bits */
-#define RAM2_MEM_BASE ((uint32_t) 0x20010000UL) /**< RAM2 base address */
-#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */
-#define RAM2_MEM_END ((uint32_t) 0x200107FFUL) /**< RAM2 end address */
-#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */
-#define RAM1_MEM_BASE ((uint32_t) 0x20008000UL) /**< RAM1 base address */
-#define RAM1_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM1 available address space */
-#define RAM1_MEM_END ((uint32_t) 0x2000FFFFUL) /**< RAM1 end address */
-#define RAM1_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM1 used bits */
-#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */
-#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */
-#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
-#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
-#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */
-#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */
-#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */
-#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10008000UL) /**< RAM1_CODE base address */
-#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM1_CODE available address space */
-#define RAM1_CODE_MEM_END ((uint32_t) 0x1000FFFFUL) /**< RAM1_CODE end address */
-#define RAM1_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM1_CODE used bits */
-#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */
-#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */
-#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */
-#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */
-#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
-#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
-#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */
-#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */
-#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */
-#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */
-#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */
-#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
-#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
-#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
-#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
-#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
-#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */
-#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */
-#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */
-#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */
-#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */
-#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */
-#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */
-#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
-#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
-#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
-#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
-#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */
-#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */
-#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
-#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
-#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
-#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
-#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
-#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
-#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
-#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */
-#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */
-#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */
-#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */
-#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */
-#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */
-#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */
-#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10010000UL) /**< RAM2_CODE base address */
-#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */
-#define RAM2_CODE_MEM_END ((uint32_t) 0x100107FFUL) /**< RAM2_CODE end address */
-#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
-#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
-#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
-#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */
+#define CRYPTO1_BITCLR_MEM_BASE (0x440F0400UL) /**< CRYPTO1_BITCLR base address */
+#define CRYPTO1_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO1_BITCLR available address space */
+#define CRYPTO1_BITCLR_MEM_END (0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
+#define CRYPTO1_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
+#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */
+#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */
+#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */
+#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */
+#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */
+#define RAM2_MEM_SIZE (0x800UL) /**< RAM2 available address space */
+#define RAM2_MEM_END (0x200407FFUL) /**< RAM2 end address */
+#define RAM2_MEM_BITS (0x0000000BUL) /**< RAM2 used bits */
+#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */
+#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */
+#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
+#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
+#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
+#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
+#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
+#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
+#define CRYPTO1_MEM_BASE (0x400F0400UL) /**< CRYPTO1 base address */
+#define CRYPTO1_MEM_SIZE (0x400UL) /**< CRYPTO1 available address space */
+#define CRYPTO1_MEM_END (0x400F07FFUL) /**< CRYPTO1 end address */
+#define CRYPTO1_MEM_BITS (0x0000000AUL) /**< CRYPTO1 used bits */
+#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */
+#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */
+#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */
+#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
+#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
+#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
+#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
+#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */
+#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */
+#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */
+#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */
+#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */
+#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */
+#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */
+#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define CRYPTO1_BITSET_MEM_BASE (0x460F0400UL) /**< CRYPTO1_BITSET base address */
+#define CRYPTO1_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO1_BITSET available address space */
+#define CRYPTO1_BITSET_MEM_END (0x460F07FFUL) /**< CRYPTO1_BITSET end address */
+#define CRYPTO1_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITSET used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x20000UL) /**< RAM available address space */
+#define RAM_MEM_END (0x2001FFFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x00000011UL) /**< RAM used bits */
+#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */
+#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */
+#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */
+#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */
+#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
+#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
+#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
+#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xF0000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460EFFFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xF0000UL) /**< PER available address space */
+#define PER_MEM_END (0x400EFFFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */
+#define RAM2_CODE_MEM_SIZE (0x800UL) /**< RAM2_CODE available address space */
+#define RAM2_CODE_MEM_END (0x100407FFUL) /**< RAM2_CODE end address */
+#define RAM2_CODE_MEM_BITS (0x0000000BUL) /**< RAM2_CODE used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xF0000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440EFFFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
/** Bit banding area */
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
-/** Flash and SRAM limits for EFR32FG13P231F512IM48 */
+/** Flash and SRAM limits for EFR32FG12P431F1024GM68 */
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
-#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */
-#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
+#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size (interleaving off) */
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
-#define SRAM_SIZE (0x00010000UL) /**< Available SRAM Memory */
-#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
+#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
-#define EXT_IRQ_COUNT 47 /**< Number of External (NVIC) interrupts */
+#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */
/** AF channels connect the different on-chip peripherals with the af-mux */
-#define AFCHAN_MAX 118U
+#define AFCHAN_MAX 136U
/** AF channel maximum location number */
#define AFCHANLOC_MAX 32U
/** Analog AF channels */
-#define AFACHAN_MAX 118U
+#define AFACHAN_MAX 125U
/* Part number capabilities */
@@ -259,27 +272,27 @@ typedef enum IRQn{
#define TIMER_PRESENT /**< TIMER is available in this part */
#define TIMER_COUNT 2 /**< 2 TIMERs available */
#define WTIMER_PRESENT /**< WTIMER is available in this part */
-#define WTIMER_COUNT 1 /**< 1 WTIMERs available */
+#define WTIMER_COUNT 2 /**< 2 WTIMERs available */
#define USART_PRESENT /**< USART is available in this part */
-#define USART_COUNT 3 /**< 3 USARTs available */
+#define USART_COUNT 4 /**< 4 USARTs available */
#define LEUART_PRESENT /**< LEUART is available in this part */
#define LEUART_COUNT 1 /**< 1 LEUARTs available */
#define LETIMER_PRESENT /**< LETIMER is available in this part */
#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
#define PCNT_PRESENT /**< PCNT is available in this part */
-#define PCNT_COUNT 1 /**< 1 PCNTs available */
+#define PCNT_COUNT 3 /**< 3 PCNTs available */
#define I2C_PRESENT /**< I2C is available in this part */
#define I2C_COUNT 2 /**< 2 I2Cs available */
#define ADC_PRESENT /**< ADC is available in this part */
#define ADC_COUNT 1 /**< 1 ADCs available */
#define ACMP_PRESENT /**< ACMP is available in this part */
#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
#define VDAC_PRESENT /**< VDAC is available in this part */
#define VDAC_COUNT 1 /**< 1 VDACs available */
#define WDOG_PRESENT /**< WDOG is available in this part */
#define WDOG_COUNT 2 /**< 2 WDOGs available */
-#define IDAC_PRESENT /**< IDAC is available in this part */
-#define IDAC_COUNT 1 /**< 1 IDACs available */
#define TRNG_PRESENT /**< TRNG is available in this part */
#define TRNG_COUNT 1 /**< 1 TRNGs available */
#define MSC_PRESENT /**< MSC is available in this part */
@@ -317,66 +330,66 @@ typedef enum IRQn{
#define DCDC_PRESENT /**< DCDC is available in this part */
#define DCDC_COUNT 1 /**< 1 DCDC available */
-#include "../../../efr32/cmsis/core_cm4.h" /* Cortex-M4 processor and core peripherals */
-#include "../../../efr32/vendor/efr32fg13/system_efr32fg13p.h" /* System Header File */
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32fg12p.h" /* System Header File */
-/** @} End of group EFR32FG13P231F512IM48_Part */
+/** @} End of group EFR32FG12P431F1024GM68_Part */
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512IM48_Peripheral_TypeDefs Peripheral TypeDefs
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024GM68_Peripheral_TypeDefs Peripheral TypeDefs
* @{
* @brief Device Specific Peripheral Register Structures
- *****************************************************************************/
-
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_msc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_emu.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_rmu.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_cmu.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_crypto.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_gpio_p.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_gpio.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_prs_ch.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_prs.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_ldma_ch.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_ldma.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_fpueh.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_gpcrc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_timer_cc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_timer.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_usart.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_leuart.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_letimer.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_cryotimer.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_pcnt.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_i2c.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_adc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_acmp.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_vdac_opa.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_vdac.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_csen.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_lesense_st.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_lesense_buf.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_lesense_ch.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_lesense.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_rtcc_cc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_rtcc_ret.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_rtcc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_wdog_pch.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_wdog.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_etm.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_idac.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_smu.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_trng.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_dma_descriptor.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_devinfo.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_romtable.h"
-
-/** @} End of group EFR32FG13P231F512IM48_Peripheral_TypeDefs */
-
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512IM48_Peripheral_Base Peripheral Memory Map
+ ******************************************************************************/
+
+#include "efr32fg12p_msc.h"
+#include "efr32fg12p_emu.h"
+#include "efr32fg12p_rmu.h"
+#include "efr32fg12p_cmu.h"
+#include "efr32fg12p_crypto.h"
+#include "efr32fg12p_gpio_p.h"
+#include "efr32fg12p_gpio.h"
+#include "efr32fg12p_prs_ch.h"
+#include "efr32fg12p_prs.h"
+#include "efr32fg12p_ldma_ch.h"
+#include "efr32fg12p_ldma.h"
+#include "efr32fg12p_fpueh.h"
+#include "efr32fg12p_gpcrc.h"
+#include "efr32fg12p_timer_cc.h"
+#include "efr32fg12p_timer.h"
+#include "efr32fg12p_usart.h"
+#include "efr32fg12p_leuart.h"
+#include "efr32fg12p_letimer.h"
+#include "efr32fg12p_cryotimer.h"
+#include "efr32fg12p_pcnt.h"
+#include "efr32fg12p_i2c.h"
+#include "efr32fg12p_adc.h"
+#include "efr32fg12p_acmp.h"
+#include "efr32fg12p_idac.h"
+#include "efr32fg12p_vdac_opa.h"
+#include "efr32fg12p_vdac.h"
+#include "efr32fg12p_csen.h"
+#include "efr32fg12p_lesense_st.h"
+#include "efr32fg12p_lesense_buf.h"
+#include "efr32fg12p_lesense_ch.h"
+#include "efr32fg12p_lesense.h"
+#include "efr32fg12p_rtcc_cc.h"
+#include "efr32fg12p_rtcc_ret.h"
+#include "efr32fg12p_rtcc.h"
+#include "efr32fg12p_wdog_pch.h"
+#include "efr32fg12p_wdog.h"
+#include "efr32fg12p_etm.h"
+#include "efr32fg12p_smu.h"
+#include "efr32fg12p_trng.h"
+#include "efr32fg12p_dma_descriptor.h"
+#include "efr32fg12p_devinfo.h"
+#include "efr32fg12p_romtable.h"
+
+/** @} End of group EFR32FG12P431F1024GM68_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024GM68_Peripheral_Base Peripheral Memory Map
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC_BASE (0x400E0000UL) /**< MSC base address */
#define EMU_BASE (0x400E3000UL) /**< EMU base address */
@@ -393,18 +406,23 @@ typedef enum IRQn{
#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */
+#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */
#define USART0_BASE (0x40010000UL) /**< USART0 base address */
#define USART1_BASE (0x40010400UL) /**< USART1 base address */
#define USART2_BASE (0x40010800UL) /**< USART2 base address */
+#define USART3_BASE (0x40010C00UL) /**< USART3 base address */
#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
+#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */
+#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */
#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */
#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
+#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */
#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */
#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */
@@ -412,7 +430,6 @@ typedef enum IRQn{
#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */
#define ETM_BASE (0xE0041000UL) /**< ETM base address */
-#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
#define SMU_BASE (0x40022000UL) /**< SMU base address */
#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */
#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
@@ -420,12 +437,12 @@ typedef enum IRQn{
#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
-/** @} End of group EFR32FG13P231F512IM48_Peripheral_Base */
+/** @} End of group EFR32FG12P431F1024GM68_Peripheral_Base */
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512IM48_Peripheral_Declaration Peripheral Declarations
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024GM68_Peripheral_Declaration Peripheral Declarations
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
@@ -442,18 +459,23 @@ typedef enum IRQn{
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */
+#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
+#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
+#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
+#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
+#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */
#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */
#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
@@ -461,18 +483,17 @@ typedef enum IRQn{
#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */
#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
-#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */
#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
-/** @} End of group EFR32FG13P231F512IM48_Peripheral_Declaration */
+/** @} End of group EFR32FG12P431F1024GM68_Peripheral_Declaration */
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512IM48_Peripheral_Offsets Peripheral Offsets
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024GM68_Peripheral_Offsets Peripheral Offsets
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */
#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
@@ -484,31 +505,31 @@ typedef enum IRQn{
#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
+#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */
#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
-#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */
-/** @} End of group EFR32FG13P231F512IM48_Peripheral_Offsets */
+/** @} End of group EFR32FG12P431F1024GM68_Peripheral_Offsets */
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512IM48_BitFields Bit Fields
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024GM68_BitFields Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_prs_signals.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_dmareq.h"
+#include "efr32fg12p_prs_signals.h"
+#include "efr32fg12p_dmareq.h"
-/**************************************************************************//**
- * @addtogroup EFR32FG13P231F512IM48_WTIMER
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P431F1024GM68_WTIMER
* @{
- * @defgroup EFR32FG13P231F512IM48_WTIMER_BitFields WTIMER Bit Fields
+ * @defgroup EFR32FG12P431F1024GM68_WTIMER_BitFields WTIMER Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for WTIMER CTRL */
#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */
-#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */
+#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */
#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
@@ -579,11 +600,6 @@ typedef enum IRQn{
#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */
#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */
-#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */
-#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */
-#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */
#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */
#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */
#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
@@ -1010,13 +1026,13 @@ typedef enum IRQn{
#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */
-#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */
+#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */
-#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */
+#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */
@@ -1997,23 +2013,23 @@ typedef enum IRQn{
#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */
-#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */
+#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */
-#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */
+#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */
/** @} */
-/** @} End of group EFR32FG13P231F512IM48_WTIMER */
+/** @} End of group EFR32FG12P431F1024GM68_WTIMER */
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512IM48_UNLOCK Unlock Codes
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024GM68_UNLOCK Unlock Codes
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
@@ -2022,18 +2038,19 @@ typedef enum IRQn{
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
-/** @} End of group EFR32FG13P231F512IM48_UNLOCK */
+/** @} End of group EFR32FG12P431F1024GM68_UNLOCK */
-/** @} End of group EFR32FG13P231F512IM48_BitFields */
+/** @} End of group EFR32FG12P431F1024GM68_BitFields */
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_af_ports.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_af_pins.h"
+#include "efr32fg12p_af_ports.h"
+#include "efr32fg12p_af_pins.h"
-/** @} End of group EFR32FG13P231F512IM48 */
+/** @} End of group EFR32FG12P431F1024GM68 */
/** @} End of group Parts */
#ifdef __cplusplus
}
#endif
-#endif /* EFR32FG13P231F512IM48_H */
+
+#endif /* EFR32FG12P431F1024GM68_H */
diff --git a/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p431f1024im48.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p431f1024im48.h
new file mode 100644
index 00000000..9acb4ede
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p431f1024im48.h
@@ -0,0 +1,2056 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32FG12P431F1024IM48
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+#ifndef EFR32FG12P431F1024IM48_H
+#define EFR32FG12P431F1024IM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024IM48 EFR32FG12P431F1024IM48
+ * @{
+ ******************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+
+/****** EFR32FG12P Peripheral Interrupt Numbers ********************************************/
+
+ EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
+ WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 3, /*!< 16+3 EFR32 WDOG1 Interrupt */
+ FRC_IRQn = 4, /*!< 16+4 EFR32 FRC Interrupt */
+ MODEM_IRQn = 5, /*!< 16+5 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 6, /*!< 16+6 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 7, /*!< 16+7 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 8, /*!< 16+8 EFR32 BUFC Interrupt */
+ LDMA_IRQn = 9, /*!< 16+9 EFR32 LDMA Interrupt */
+ GPIO_EVEN_IRQn = 10, /*!< 16+10 EFR32 GPIO_EVEN Interrupt */
+ TIMER0_IRQn = 11, /*!< 16+11 EFR32 TIMER0 Interrupt */
+ USART0_RX_IRQn = 12, /*!< 16+12 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 13, /*!< 16+13 EFR32 USART0_TX Interrupt */
+ ACMP0_IRQn = 14, /*!< 16+14 EFR32 ACMP0 Interrupt */
+ ADC0_IRQn = 15, /*!< 16+15 EFR32 ADC0 Interrupt */
+ IDAC0_IRQn = 16, /*!< 16+16 EFR32 IDAC0 Interrupt */
+ I2C0_IRQn = 17, /*!< 16+17 EFR32 I2C0 Interrupt */
+ GPIO_ODD_IRQn = 18, /*!< 16+18 EFR32 GPIO_ODD Interrupt */
+ TIMER1_IRQn = 19, /*!< 16+19 EFR32 TIMER1 Interrupt */
+ USART1_RX_IRQn = 20, /*!< 16+20 EFR32 USART1_RX Interrupt */
+ USART1_TX_IRQn = 21, /*!< 16+21 EFR32 USART1_TX Interrupt */
+ LEUART0_IRQn = 22, /*!< 16+22 EFR32 LEUART0 Interrupt */
+ PCNT0_IRQn = 23, /*!< 16+23 EFR32 PCNT0 Interrupt */
+ CMU_IRQn = 24, /*!< 16+24 EFR32 CMU Interrupt */
+ MSC_IRQn = 25, /*!< 16+25 EFR32 MSC Interrupt */
+ CRYPTO0_IRQn = 26, /*!< 16+26 EFR32 CRYPTO0 Interrupt */
+ LETIMER0_IRQn = 27, /*!< 16+27 EFR32 LETIMER0 Interrupt */
+ AGC_IRQn = 28, /*!< 16+28 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 29, /*!< 16+29 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 30, /*!< 16+30 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 31, /*!< 16+31 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 32, /*!< 16+32 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 33, /*!< 16+33 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 34, /*!< 16+34 EFR32 FPUEH Interrupt */
+ SMU_IRQn = 35, /*!< 16+35 EFR32 SMU Interrupt */
+ WTIMER0_IRQn = 36, /*!< 16+36 EFR32 WTIMER0 Interrupt */
+ WTIMER1_IRQn = 37, /*!< 16+37 EFR32 WTIMER1 Interrupt */
+ PCNT1_IRQn = 38, /*!< 16+38 EFR32 PCNT1 Interrupt */
+ PCNT2_IRQn = 39, /*!< 16+39 EFR32 PCNT2 Interrupt */
+ USART2_RX_IRQn = 40, /*!< 16+40 EFR32 USART2_RX Interrupt */
+ USART2_TX_IRQn = 41, /*!< 16+41 EFR32 USART2_TX Interrupt */
+ I2C1_IRQn = 42, /*!< 16+42 EFR32 I2C1 Interrupt */
+ USART3_RX_IRQn = 43, /*!< 16+43 EFR32 USART3_RX Interrupt */
+ USART3_TX_IRQn = 44, /*!< 16+44 EFR32 USART3_TX Interrupt */
+ VDAC0_IRQn = 45, /*!< 16+45 EFR32 VDAC0 Interrupt */
+ CSEN_IRQn = 46, /*!< 16+46 EFR32 CSEN Interrupt */
+ LESENSE_IRQn = 47, /*!< 16+47 EFR32 LESENSE Interrupt */
+ CRYPTO1_IRQn = 48, /*!< 16+48 EFR32 CRYPTO1 Interrupt */
+ TRNG0_IRQn = 49, /*!< 16+49 EFR32 TRNG0 Interrupt */
+} IRQn_Type;
+
+#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */
+
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024IM48_Core Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32FG12P431F1024IM48_Core */
+
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024IM48_Part Part
+ * @{
+ ******************************************************************************/
+
+/** Part family */
+#define _EFR32_FLEX_FAMILY 1 /**< FLEX Gecko RF SoC Family */
+#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
+#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /**< Radio type */
+#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32FG12P431F1024IM48)
+#define EFR32FG12P431F1024IM48 1 /**< FLEX Gecko Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32FG12P431F1024IM48" /**< Part Number */
+
+/** Memory Base addresses and limits */
+#define CRYPTO1_BITCLR_MEM_BASE (0x440F0400UL) /**< CRYPTO1_BITCLR base address */
+#define CRYPTO1_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO1_BITCLR available address space */
+#define CRYPTO1_BITCLR_MEM_END (0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
+#define CRYPTO1_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
+#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */
+#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */
+#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */
+#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */
+#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */
+#define RAM2_MEM_SIZE (0x800UL) /**< RAM2 available address space */
+#define RAM2_MEM_END (0x200407FFUL) /**< RAM2 end address */
+#define RAM2_MEM_BITS (0x0000000BUL) /**< RAM2 used bits */
+#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */
+#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */
+#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
+#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
+#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
+#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
+#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
+#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
+#define CRYPTO1_MEM_BASE (0x400F0400UL) /**< CRYPTO1 base address */
+#define CRYPTO1_MEM_SIZE (0x400UL) /**< CRYPTO1 available address space */
+#define CRYPTO1_MEM_END (0x400F07FFUL) /**< CRYPTO1 end address */
+#define CRYPTO1_MEM_BITS (0x0000000AUL) /**< CRYPTO1 used bits */
+#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */
+#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */
+#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */
+#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
+#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
+#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
+#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
+#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */
+#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */
+#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */
+#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */
+#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */
+#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */
+#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */
+#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define CRYPTO1_BITSET_MEM_BASE (0x460F0400UL) /**< CRYPTO1_BITSET base address */
+#define CRYPTO1_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO1_BITSET available address space */
+#define CRYPTO1_BITSET_MEM_END (0x460F07FFUL) /**< CRYPTO1_BITSET end address */
+#define CRYPTO1_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITSET used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x20000UL) /**< RAM available address space */
+#define RAM_MEM_END (0x2001FFFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x00000011UL) /**< RAM used bits */
+#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */
+#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */
+#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */
+#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */
+#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
+#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
+#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
+#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xF0000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460EFFFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xF0000UL) /**< PER available address space */
+#define PER_MEM_END (0x400EFFFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */
+#define RAM2_CODE_MEM_SIZE (0x800UL) /**< RAM2_CODE available address space */
+#define RAM2_CODE_MEM_END (0x100407FFUL) /**< RAM2_CODE end address */
+#define RAM2_CODE_MEM_BITS (0x0000000BUL) /**< RAM2_CODE used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xF0000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440EFFFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
+
+/** Bit banding area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
+
+/** Flash and SRAM limits for EFR32FG12P431F1024IM48 */
+#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size (interleaving off) */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
+#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
+#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */
+
+/** AF channels connect the different on-chip peripherals with the af-mux */
+#define AFCHAN_MAX 136U
+/** AF channel maximum location number */
+#define AFCHANLOC_MAX 32U
+/** Analog AF channels */
+#define AFACHAN_MAX 125U
+
+/* Part number capabilities */
+
+#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
+#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */
+#define TIMER_PRESENT /**< TIMER is available in this part */
+#define TIMER_COUNT 2 /**< 2 TIMERs available */
+#define WTIMER_PRESENT /**< WTIMER is available in this part */
+#define WTIMER_COUNT 2 /**< 2 WTIMERs available */
+#define USART_PRESENT /**< USART is available in this part */
+#define USART_COUNT 4 /**< 4 USARTs available */
+#define LEUART_PRESENT /**< LEUART is available in this part */
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */
+#define LETIMER_PRESENT /**< LETIMER is available in this part */
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
+#define PCNT_PRESENT /**< PCNT is available in this part */
+#define PCNT_COUNT 3 /**< 3 PCNTs available */
+#define I2C_PRESENT /**< I2C is available in this part */
+#define I2C_COUNT 2 /**< 2 I2Cs available */
+#define ADC_PRESENT /**< ADC is available in this part */
+#define ADC_COUNT 1 /**< 1 ADCs available */
+#define ACMP_PRESENT /**< ACMP is available in this part */
+#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
+#define VDAC_PRESENT /**< VDAC is available in this part */
+#define VDAC_COUNT 1 /**< 1 VDACs available */
+#define WDOG_PRESENT /**< WDOG is available in this part */
+#define WDOG_COUNT 2 /**< 2 WDOGs available */
+#define TRNG_PRESENT /**< TRNG is available in this part */
+#define TRNG_COUNT 1 /**< 1 TRNGs available */
+#define MSC_PRESENT /**< MSC is available in this part */
+#define MSC_COUNT 1 /**< 1 MSC available */
+#define EMU_PRESENT /**< EMU is available in this part */
+#define EMU_COUNT 1 /**< 1 EMU available */
+#define RMU_PRESENT /**< RMU is available in this part */
+#define RMU_COUNT 1 /**< 1 RMU available */
+#define CMU_PRESENT /**< CMU is available in this part */
+#define CMU_COUNT 1 /**< 1 CMU available */
+#define GPIO_PRESENT /**< GPIO is available in this part */
+#define GPIO_COUNT 1 /**< 1 GPIO available */
+#define PRS_PRESENT /**< PRS is available in this part */
+#define PRS_COUNT 1 /**< 1 PRS available */
+#define LDMA_PRESENT /**< LDMA is available in this part */
+#define LDMA_COUNT 1 /**< 1 LDMA available */
+#define FPUEH_PRESENT /**< FPUEH is available in this part */
+#define FPUEH_COUNT 1 /**< 1 FPUEH available */
+#define GPCRC_PRESENT /**< GPCRC is available in this part */
+#define GPCRC_COUNT 1 /**< 1 GPCRC available */
+#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
+#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
+#define CSEN_PRESENT /**< CSEN is available in this part */
+#define CSEN_COUNT 1 /**< 1 CSEN available */
+#define LESENSE_PRESENT /**< LESENSE is available in this part */
+#define LESENSE_COUNT 1 /**< 1 LESENSE available */
+#define RTCC_PRESENT /**< RTCC is available in this part */
+#define RTCC_COUNT 1 /**< 1 RTCC available */
+#define ETM_PRESENT /**< ETM is available in this part */
+#define ETM_COUNT 1 /**< 1 ETM available */
+#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
+#define SMU_PRESENT /**< SMU is available in this part */
+#define SMU_COUNT 1 /**< 1 SMU available */
+#define DCDC_PRESENT /**< DCDC is available in this part */
+#define DCDC_COUNT 1 /**< 1 DCDC available */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32fg12p.h" /* System Header File */
+
+/** @} End of group EFR32FG12P431F1024IM48_Part */
+
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024IM48_Peripheral_TypeDefs Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ ******************************************************************************/
+
+#include "efr32fg12p_msc.h"
+#include "efr32fg12p_emu.h"
+#include "efr32fg12p_rmu.h"
+#include "efr32fg12p_cmu.h"
+#include "efr32fg12p_crypto.h"
+#include "efr32fg12p_gpio_p.h"
+#include "efr32fg12p_gpio.h"
+#include "efr32fg12p_prs_ch.h"
+#include "efr32fg12p_prs.h"
+#include "efr32fg12p_ldma_ch.h"
+#include "efr32fg12p_ldma.h"
+#include "efr32fg12p_fpueh.h"
+#include "efr32fg12p_gpcrc.h"
+#include "efr32fg12p_timer_cc.h"
+#include "efr32fg12p_timer.h"
+#include "efr32fg12p_usart.h"
+#include "efr32fg12p_leuart.h"
+#include "efr32fg12p_letimer.h"
+#include "efr32fg12p_cryotimer.h"
+#include "efr32fg12p_pcnt.h"
+#include "efr32fg12p_i2c.h"
+#include "efr32fg12p_adc.h"
+#include "efr32fg12p_acmp.h"
+#include "efr32fg12p_idac.h"
+#include "efr32fg12p_vdac_opa.h"
+#include "efr32fg12p_vdac.h"
+#include "efr32fg12p_csen.h"
+#include "efr32fg12p_lesense_st.h"
+#include "efr32fg12p_lesense_buf.h"
+#include "efr32fg12p_lesense_ch.h"
+#include "efr32fg12p_lesense.h"
+#include "efr32fg12p_rtcc_cc.h"
+#include "efr32fg12p_rtcc_ret.h"
+#include "efr32fg12p_rtcc.h"
+#include "efr32fg12p_wdog_pch.h"
+#include "efr32fg12p_wdog.h"
+#include "efr32fg12p_etm.h"
+#include "efr32fg12p_smu.h"
+#include "efr32fg12p_trng.h"
+#include "efr32fg12p_dma_descriptor.h"
+#include "efr32fg12p_devinfo.h"
+#include "efr32fg12p_romtable.h"
+
+/** @} End of group EFR32FG12P431F1024IM48_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024IM48_Peripheral_Base Peripheral Memory Map
+ * @{
+ ******************************************************************************/
+
+#define MSC_BASE (0x400E0000UL) /**< MSC base address */
+#define EMU_BASE (0x400E3000UL) /**< EMU base address */
+#define RMU_BASE (0x400E5000UL) /**< RMU base address */
+#define CMU_BASE (0x400E4000UL) /**< CMU base address */
+#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */
+#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */
+#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */
+#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */
+#define PRS_BASE (0x400E6000UL) /**< PRS base address */
+#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */
+#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */
+#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */
+#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
+#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
+#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */
+#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */
+#define USART0_BASE (0x40010000UL) /**< USART0 base address */
+#define USART1_BASE (0x40010400UL) /**< USART1 base address */
+#define USART2_BASE (0x40010800UL) /**< USART2 base address */
+#define USART3_BASE (0x40010C00UL) /**< USART3 base address */
+#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
+#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
+#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
+#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
+#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */
+#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */
+#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
+#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */
+#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
+#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
+#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
+#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
+#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */
+#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */
+#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */
+#define RTCC_BASE (0x40042000UL) /**< RTCC base address */
+#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
+#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */
+#define ETM_BASE (0xE0041000UL) /**< ETM base address */
+#define SMU_BASE (0x40022000UL) /**< SMU base address */
+#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */
+#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
+#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
+#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
+#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
+
+/** @} End of group EFR32FG12P431F1024IM48_Peripheral_Base */
+
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024IM48_Peripheral_Declaration Peripheral Declarations
+ * @{
+ ******************************************************************************/
+
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
+#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
+#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */
+#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */
+#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */
+#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
+#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */
+#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
+#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
+#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
+#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */
+#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
+#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
+#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
+#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
+#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
+#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */
+#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */
+#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
+#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */
+#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */
+#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
+
+/** @} End of group EFR32FG12P431F1024IM48_Peripheral_Declaration */
+
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024IM48_Peripheral_Offsets Peripheral Offsets
+ * @{
+ ******************************************************************************/
+
+#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */
+#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
+#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */
+#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
+#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */
+#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */
+#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */
+#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
+#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
+#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
+#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
+#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */
+#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
+#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */
+
+/** @} End of group EFR32FG12P431F1024IM48_Peripheral_Offsets */
+
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024IM48_BitFields Bit Fields
+ * @{
+ ******************************************************************************/
+
+#include "efr32fg12p_prs_signals.h"
+#include "efr32fg12p_dmareq.h"
+
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P431F1024IM48_WTIMER
+ * @{
+ * @defgroup EFR32FG12P431F1024IM48_WTIMER_BitFields WTIMER Bit Fields
+ * @{
+ ******************************************************************************/
+
+/* Bit fields for WTIMER CTRL */
+#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */
+#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */
+#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
+#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
+#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
+#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */
+#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */
+#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */
+#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */
+#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */
+#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */
+#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */
+#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */
+#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */
+#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */
+#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */
+#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */
+#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
+#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */
+#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */
+#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */
+#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */
+#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
+#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */
+#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */
+#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */
+#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */
+#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
+#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */
+#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */
+#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */
+#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */
+#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */
+#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */
+#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */
+#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */
+#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
+#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */
+#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */
+#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */
+#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */
+#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
+#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */
+#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */
+#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */
+#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
+#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */
+#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */
+#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */
+#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */
+#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */
+#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */
+#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */
+#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */
+#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */
+#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */
+#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */
+#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
+#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */
+#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */
+#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */
+#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */
+#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */
+#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */
+#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */
+#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */
+#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */
+#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */
+#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */
+#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */
+#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
+#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */
+#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */
+#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */
+#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
+#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */
+#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */
+#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */
+#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */
+#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */
+#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */
+#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */
+#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */
+#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */
+#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
+#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */
+#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */
+#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */
+#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */
+#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */
+#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */
+#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */
+#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */
+#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */
+#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */
+#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */
+#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */
+#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */
+#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */
+#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */
+#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */
+#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */
+#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */
+#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */
+#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */
+#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */
+#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */
+#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */
+#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */
+#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */
+#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */
+#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
+#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */
+#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */
+#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */
+#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */
+#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
+#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */
+
+/* Bit fields for WTIMER CMD */
+#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */
+#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */
+#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */
+#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */
+#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */
+#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */
+#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */
+#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */
+#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */
+#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */
+#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */
+#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */
+
+/* Bit fields for WTIMER STATUS */
+#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */
+#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */
+#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */
+#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */
+#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */
+#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
+#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */
+#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */
+#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */
+#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */
+#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
+#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */
+#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */
+#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */
+#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */
+#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */
+#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */
+#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */
+#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */
+#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
+#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */
+#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */
+#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */
+#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */
+#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
+#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */
+#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */
+#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */
+#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */
+#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
+#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */
+#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */
+#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */
+#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */
+#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
+#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */
+#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */
+#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */
+#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */
+#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
+#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */
+#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */
+#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */
+#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */
+#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
+#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */
+#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */
+#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */
+#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */
+#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
+#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */
+#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */
+#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */
+#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */
+#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
+#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */
+#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */
+#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */
+#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */
+#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
+#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */
+#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */
+#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */
+#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */
+#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
+#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */
+#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */
+#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */
+#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */
+#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */
+#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */
+#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */
+#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */
+#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
+#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */
+#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */
+#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */
+#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */
+#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */
+#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */
+#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */
+#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */
+#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
+#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */
+#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */
+#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */
+#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */
+#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */
+#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */
+#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */
+#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */
+#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
+#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */
+#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */
+#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */
+#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */
+#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */
+
+/* Bit fields for WTIMER IF */
+#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */
+#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */
+#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */
+#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */
+#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
+#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
+#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */
+#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */
+#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */
+#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
+#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
+#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */
+#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */
+#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
+#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
+#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
+#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */
+#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */
+#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
+#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
+#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
+#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */
+#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */
+#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
+#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
+#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
+#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */
+#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */
+#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
+#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
+#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
+#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */
+#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */
+#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
+#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
+#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
+#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */
+#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */
+#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
+#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
+#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
+#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */
+#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */
+#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
+#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
+#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
+#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */
+#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */
+#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
+#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
+#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
+#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */
+#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */
+#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
+#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
+#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
+#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */
+
+/* Bit fields for WTIMER IFS */
+#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */
+#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */
+#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */
+#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */
+#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
+#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
+#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */
+#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */
+#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */
+#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
+#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
+#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */
+#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */
+#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
+#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
+#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
+#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */
+#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */
+#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
+#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
+#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
+#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */
+#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */
+#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
+#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
+#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
+#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */
+#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */
+#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
+#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
+#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
+#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */
+#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */
+#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
+#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
+#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
+#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */
+#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */
+#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
+#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
+#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
+#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */
+#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */
+#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
+#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
+#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
+#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */
+#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */
+#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
+#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
+#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
+#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */
+#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */
+#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
+#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
+#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
+#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */
+
+/* Bit fields for WTIMER IFC */
+#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */
+#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */
+#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */
+#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */
+#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
+#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
+#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */
+#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */
+#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */
+#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
+#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
+#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */
+#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */
+#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
+#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
+#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
+#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */
+#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */
+#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
+#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
+#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
+#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */
+#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */
+#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
+#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
+#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
+#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */
+#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */
+#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
+#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
+#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
+#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */
+#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */
+#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
+#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
+#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
+#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */
+#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */
+#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
+#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
+#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
+#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */
+#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */
+#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
+#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
+#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
+#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */
+#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */
+#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
+#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
+#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
+#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */
+#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */
+#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
+#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
+#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
+#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */
+
+/* Bit fields for WTIMER IEN */
+#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */
+#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */
+#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */
+#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */
+#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
+#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
+#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */
+#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */
+#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */
+#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
+#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
+#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */
+#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */
+#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
+#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
+#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
+#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */
+#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */
+#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
+#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
+#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
+#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */
+#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */
+#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
+#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
+#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
+#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */
+#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */
+#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
+#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
+#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
+#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */
+#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */
+#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
+#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
+#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
+#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */
+#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */
+#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
+#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
+#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
+#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */
+#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */
+#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
+#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
+#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
+#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */
+#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */
+#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
+#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
+#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
+#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */
+#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */
+#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
+#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
+#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
+#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */
+
+/* Bit fields for WTIMER TOP */
+#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */
+#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */
+#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */
+#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */
+#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */
+#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */
+
+/* Bit fields for WTIMER TOPB */
+#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */
+#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */
+#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */
+#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */
+#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */
+#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */
+
+/* Bit fields for WTIMER CNT */
+#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */
+#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */
+#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */
+#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */
+#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */
+#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */
+
+/* Bit fields for WTIMER LOCK */
+#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */
+#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */
+#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */
+#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */
+#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */
+#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */
+#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
+#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */
+#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */
+#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */
+#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */
+#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
+#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */
+#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */
+
+/* Bit fields for WTIMER ROUTEPEN */
+#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */
+#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */
+#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */
+#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */
+#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */
+#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
+#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
+#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */
+#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */
+#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */
+#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
+#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
+#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */
+#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */
+#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */
+#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
+#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
+#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */
+#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */
+#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */
+#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
+#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
+#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */
+#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */
+#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */
+#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
+#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
+#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */
+#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */
+#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */
+#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
+#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
+#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */
+#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */
+#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */
+#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
+#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
+
+/* Bit fields for WTIMER ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */
+#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */
+#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */
+#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */
+#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */
+#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */
+#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */
+
+/* Bit fields for WTIMER ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */
+#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */
+#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */
+
+/* Bit fields for WTIMER CC_CTRL */
+#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
+#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
+#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */
+#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */
+#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */
+#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */
+#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */
+#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */
+#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */
+#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */
+#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */
+#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */
+#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */
+#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */
+#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */
+#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */
+#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */
+#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */
+#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */
+#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */
+#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */
+#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */
+#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */
+#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */
+#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */
+#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */
+#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */
+#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */
+#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */
+#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */
+#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */
+#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */
+
+/* Bit fields for WTIMER CC_CCV */
+#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */
+#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */
+#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */
+#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */
+#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */
+#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */
+
+/* Bit fields for WTIMER CC_CCVP */
+#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */
+#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */
+#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */
+#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */
+#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */
+#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */
+
+/* Bit fields for WTIMER CC_CCVB */
+#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */
+#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */
+#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */
+#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */
+#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */
+#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */
+
+/* Bit fields for WTIMER DTCTRL */
+#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */
+#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */
+#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */
+#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */
+#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */
+#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
+#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
+#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */
+#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */
+#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */
+#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
+#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */
+#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */
+#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
+#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */
+#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */
+#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */
+#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */
+#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */
+#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
+#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
+#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */
+#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */
+#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */
+#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
+#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
+#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */
+#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */
+#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
+#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */
+#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */
+#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */
+#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */
+#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */
+#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */
+#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */
+#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */
+#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */
+#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */
+#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */
+#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */
+#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
+#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */
+#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */
+#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */
+#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */
+#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */
+#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */
+#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */
+#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */
+#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */
+#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */
+#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */
+#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */
+#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */
+#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */
+#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */
+#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
+#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
+#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */
+#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */
+#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */
+#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
+#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
+#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */
+#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */
+#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */
+#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
+#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
+
+/* Bit fields for WTIMER DTTIME */
+#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */
+#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */
+#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */
+#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */
+#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */
+#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */
+#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */
+#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */
+#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */
+#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */
+#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */
+#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */
+#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */
+#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */
+#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */
+#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */
+#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */
+#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */
+#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */
+#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */
+#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */
+#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */
+#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */
+#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */
+#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */
+#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */
+#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */
+#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */
+#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */
+#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */
+#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */
+#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */
+#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */
+#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */
+#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */
+#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */
+
+/* Bit fields for WTIMER DTFC */
+#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */
+#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */
+#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */
+#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */
+#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
+#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */
+#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */
+#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */
+#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */
+#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */
+#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */
+#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */
+#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */
+#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */
+#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */
+#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */
+#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */
+#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */
+#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */
+#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */
+#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */
+#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */
+#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */
+#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */
+#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */
+#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */
+#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */
+#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */
+#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */
+#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */
+#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */
+#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */
+#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
+#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */
+#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */
+#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */
+#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */
+#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */
+#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */
+#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */
+#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */
+#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */
+#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */
+#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */
+#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */
+#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */
+#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */
+#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */
+#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */
+#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */
+#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */
+#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */
+#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */
+#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */
+#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */
+#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */
+#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */
+#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */
+#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */
+#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */
+#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
+#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */
+#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */
+#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */
+#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */
+#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */
+#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */
+#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */
+#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */
+#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */
+#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */
+#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */
+#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */
+#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
+#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */
+#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */
+#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */
+#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */
+#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
+#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */
+#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */
+#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */
+#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */
+#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
+#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */
+#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */
+#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */
+#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */
+#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
+#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */
+
+/* Bit fields for WTIMER DTOGEN */
+#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */
+#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */
+#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */
+#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */
+#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */
+#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
+#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
+#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */
+#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */
+#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */
+#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
+#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
+#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */
+#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */
+#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */
+#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
+#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
+#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */
+#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */
+#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */
+#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
+#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
+#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */
+#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */
+#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */
+#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
+#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
+#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */
+#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */
+#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */
+#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
+#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
+
+/* Bit fields for WTIMER DTFAULT */
+#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */
+#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */
+#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */
+#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */
+#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */
+#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */
+#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */
+#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */
+#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */
+#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */
+#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */
+#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */
+#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */
+#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */
+#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */
+#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */
+#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */
+#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */
+#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */
+#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */
+#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */
+#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */
+
+/* Bit fields for WTIMER DTFAULTC */
+#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */
+#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */
+#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */
+#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */
+#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */
+#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */
+#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */
+#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */
+#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */
+#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */
+#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */
+#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */
+#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */
+#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */
+#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */
+#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */
+#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */
+#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */
+#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */
+#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */
+#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */
+#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */
+
+/* Bit fields for WTIMER DTLOCK */
+#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */
+#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */
+#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
+#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
+#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */
+#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */
+#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
+#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */
+#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */
+#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */
+#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */
+#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
+#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */
+#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */
+
+/** @} */
+/** @} End of group EFR32FG12P431F1024IM48_WTIMER */
+
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F1024IM48_UNLOCK Unlock Codes
+ * @{
+ ******************************************************************************/
+#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
+#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
+#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
+#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
+#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
+#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
+#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
+
+/** @} End of group EFR32FG12P431F1024IM48_UNLOCK */
+
+/** @} End of group EFR32FG12P431F1024IM48_BitFields */
+
+#include "efr32fg12p_af_ports.h"
+#include "efr32fg12p_af_pins.h"
+
+/** @} End of group EFR32FG12P431F1024IM48 */
+
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* EFR32FG12P431F1024IM48_H */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p231f512gm32.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p431f512gm68.h
similarity index 92%
rename from mcu/efr/common/vendor/efr32fg13/efr32fg13p231f512gm32.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p431f512gm68.h
index c506fd84..6d60355a 100644
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p231f512gm32.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p431f512gm68.h
@@ -1,35 +1,33 @@
-/**************************************************************************//**
- * @file efr32fg13p231f512gm32.h
+/***************************************************************************//**
+ * @file
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
- * for EFR32FG13P231F512GM32
- * @version 5.4.0
- ******************************************************************************
+ * for EFR32FG12P431F512GM68
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#if defined(__ICCARM__)
#pragma system_include /* Treat file as system include file. */
@@ -37,22 +35,22 @@
#pragma clang system_header /* Treat file as system include file. */
#endif
-#ifndef EFR32FG13P231F512GM32_H
-#define EFR32FG13P231F512GM32_H
+#ifndef EFR32FG12P431F512GM68_H
+#define EFR32FG12P431F512GM68_H
#ifdef __cplusplus
extern "C" {
#endif
-/**************************************************************************//**
+/***************************************************************************//**
* @addtogroup Parts
* @{
- *****************************************************************************/
+ ******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512GM32 EFR32FG13P231F512GM32
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F512GM68 EFR32FG12P431F512GM68
* @{
- *****************************************************************************/
+ ******************************************************************************/
/** Interrupt Number Definition */
typedef enum IRQn{
@@ -67,11 +65,17 @@ typedef enum IRQn{
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
-/****** EFR32FG13P Peripheral Interrupt Numbers ********************************************/
+/****** EFR32FG12P Peripheral Interrupt Numbers ********************************************/
EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
WDOG1_IRQn = 3, /*!< 16+3 EFR32 WDOG1 Interrupt */
+ FRC_IRQn = 4, /*!< 16+4 EFR32 FRC Interrupt */
+ MODEM_IRQn = 5, /*!< 16+5 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 6, /*!< 16+6 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 7, /*!< 16+7 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 8, /*!< 16+8 EFR32 BUFC Interrupt */
LDMA_IRQn = 9, /*!< 16+9 EFR32 LDMA Interrupt */
GPIO_EVEN_IRQn = 10, /*!< 16+10 EFR32 GPIO_EVEN Interrupt */
TIMER0_IRQn = 11, /*!< 16+11 EFR32 TIMER0 Interrupt */
@@ -91,166 +95,175 @@ typedef enum IRQn{
MSC_IRQn = 25, /*!< 16+25 EFR32 MSC Interrupt */
CRYPTO0_IRQn = 26, /*!< 16+26 EFR32 CRYPTO0 Interrupt */
LETIMER0_IRQn = 27, /*!< 16+27 EFR32 LETIMER0 Interrupt */
- RTCC_IRQn = 31, /*!< 16+31 EFR32 RTCC Interrupt */
- CRYOTIMER_IRQn = 33, /*!< 16+33 EFR32 CRYOTIMER Interrupt */
- FPUEH_IRQn = 35, /*!< 16+35 EFR32 FPUEH Interrupt */
- SMU_IRQn = 36, /*!< 16+36 EFR32 SMU Interrupt */
- WTIMER0_IRQn = 37, /*!< 16+37 EFR32 WTIMER0 Interrupt */
- USART2_RX_IRQn = 38, /*!< 16+38 EFR32 USART2_RX Interrupt */
- USART2_TX_IRQn = 39, /*!< 16+39 EFR32 USART2_TX Interrupt */
- I2C1_IRQn = 40, /*!< 16+40 EFR32 I2C1 Interrupt */
- VDAC0_IRQn = 41, /*!< 16+41 EFR32 VDAC0 Interrupt */
- CSEN_IRQn = 42, /*!< 16+42 EFR32 CSEN Interrupt */
- LESENSE_IRQn = 43, /*!< 16+43 EFR32 LESENSE Interrupt */
- CRYPTO1_IRQn = 44, /*!< 16+44 EFR32 CRYPTO1 Interrupt */
- TRNG0_IRQn = 45, /*!< 16+45 EFR32 TRNG0 Interrupt */
+ AGC_IRQn = 28, /*!< 16+28 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 29, /*!< 16+29 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 30, /*!< 16+30 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 31, /*!< 16+31 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 32, /*!< 16+32 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 33, /*!< 16+33 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 34, /*!< 16+34 EFR32 FPUEH Interrupt */
+ SMU_IRQn = 35, /*!< 16+35 EFR32 SMU Interrupt */
+ WTIMER0_IRQn = 36, /*!< 16+36 EFR32 WTIMER0 Interrupt */
+ WTIMER1_IRQn = 37, /*!< 16+37 EFR32 WTIMER1 Interrupt */
+ PCNT1_IRQn = 38, /*!< 16+38 EFR32 PCNT1 Interrupt */
+ PCNT2_IRQn = 39, /*!< 16+39 EFR32 PCNT2 Interrupt */
+ USART2_RX_IRQn = 40, /*!< 16+40 EFR32 USART2_RX Interrupt */
+ USART2_TX_IRQn = 41, /*!< 16+41 EFR32 USART2_TX Interrupt */
+ I2C1_IRQn = 42, /*!< 16+42 EFR32 I2C1 Interrupt */
+ USART3_RX_IRQn = 43, /*!< 16+43 EFR32 USART3_RX Interrupt */
+ USART3_TX_IRQn = 44, /*!< 16+44 EFR32 USART3_TX Interrupt */
+ VDAC0_IRQn = 45, /*!< 16+45 EFR32 VDAC0 Interrupt */
+ CSEN_IRQn = 46, /*!< 16+46 EFR32 CSEN Interrupt */
+ LESENSE_IRQn = 47, /*!< 16+47 EFR32 LESENSE Interrupt */
+ CRYPTO1_IRQn = 48, /*!< 16+48 EFR32 CRYPTO1 Interrupt */
+ TRNG0_IRQn = 49, /*!< 16+49 EFR32 TRNG0 Interrupt */
} IRQn_Type;
#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512GM32_Core Core
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F512GM68_Core Core
* @{
* @brief Processor and Core Peripheral Section
- *****************************************************************************/
-#define __MPU_PRESENT 1 /**< Presence of MPU */
-#define __FPU_PRESENT 1 /**< Presence of FPU */
-#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
-/** @} End of group EFR32FG13P231F512GM32_Core */
+/** @} End of group EFR32FG12P431F512GM68_Core */
-/**************************************************************************//**
-* @defgroup EFR32FG13P231F512GM32_Part Part
-* @{
-******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F512GM68_Part Part
+ * @{
+ ******************************************************************************/
/** Part family */
#define _EFR32_FLEX_FAMILY 1 /**< FLEX Gecko RF SoC Family */
#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG_3 /**< Series 1, Configuration 3 */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG 3 /**< Series 1, Configuration 3 */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID 89 /**< Silicon Labs internal use only, may change any time */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID_89 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /**< Silicon Labs internal use only, may change any time */
#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /**< Radio type */
#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN_3 /**< @deprecated Platform 2, generation 3 */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN 3 /**< @deprecated Platform 2, generation 3 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */
/* If part number is not defined as compiler option, define it */
-#if !defined(EFR32FG13P231F512GM32)
-#define EFR32FG13P231F512GM32 1 /**< FLEX Gecko Part */
+#if !defined(EFR32FG12P431F512GM68)
+#define EFR32FG12P431F512GM68 1 /**< FLEX Gecko Part */
#endif
/** Configure part number */
-#define PART_NUMBER "EFR32FG13P231F512GM32" /**< Part Number */
+#define PART_NUMBER "EFR32FG12P431F512GM68" /**< Part Number */
/** Memory Base addresses and limits */
-#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */
-#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM0_CODE available address space */
-#define RAM0_CODE_MEM_END ((uint32_t) 0x10007FFFUL) /**< RAM0_CODE end address */
-#define RAM0_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM0_CODE used bits */
-#define RAM2_MEM_BASE ((uint32_t) 0x20010000UL) /**< RAM2 base address */
-#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */
-#define RAM2_MEM_END ((uint32_t) 0x200107FFUL) /**< RAM2 end address */
-#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */
-#define RAM1_MEM_BASE ((uint32_t) 0x20008000UL) /**< RAM1 base address */
-#define RAM1_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM1 available address space */
-#define RAM1_MEM_END ((uint32_t) 0x2000FFFFUL) /**< RAM1 end address */
-#define RAM1_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM1 used bits */
-#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */
-#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */
-#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
-#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
-#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */
-#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */
-#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */
-#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10008000UL) /**< RAM1_CODE base address */
-#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM1_CODE available address space */
-#define RAM1_CODE_MEM_END ((uint32_t) 0x1000FFFFUL) /**< RAM1_CODE end address */
-#define RAM1_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM1_CODE used bits */
-#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */
-#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */
-#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */
-#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */
-#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
-#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
-#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */
-#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */
-#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */
-#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */
-#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */
-#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
-#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
-#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
-#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
-#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
-#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */
-#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */
-#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */
-#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */
-#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */
-#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */
-#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */
-#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
-#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
-#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
-#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
-#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */
-#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */
-#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
-#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
-#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
-#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
-#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
-#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
-#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
-#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */
-#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */
-#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */
-#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */
-#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */
-#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */
-#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */
-#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10010000UL) /**< RAM2_CODE base address */
-#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */
-#define RAM2_CODE_MEM_END ((uint32_t) 0x100107FFUL) /**< RAM2_CODE end address */
-#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
-#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
-#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
-#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */
+#define CRYPTO1_BITCLR_MEM_BASE (0x440F0400UL) /**< CRYPTO1_BITCLR base address */
+#define CRYPTO1_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO1_BITCLR available address space */
+#define CRYPTO1_BITCLR_MEM_END (0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
+#define CRYPTO1_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
+#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */
+#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */
+#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */
+#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */
+#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */
+#define RAM2_MEM_SIZE (0x800UL) /**< RAM2 available address space */
+#define RAM2_MEM_END (0x200407FFUL) /**< RAM2 end address */
+#define RAM2_MEM_BITS (0x0000000BUL) /**< RAM2 used bits */
+#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */
+#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */
+#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
+#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
+#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
+#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
+#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
+#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
+#define CRYPTO1_MEM_BASE (0x400F0400UL) /**< CRYPTO1 base address */
+#define CRYPTO1_MEM_SIZE (0x400UL) /**< CRYPTO1 available address space */
+#define CRYPTO1_MEM_END (0x400F07FFUL) /**< CRYPTO1 end address */
+#define CRYPTO1_MEM_BITS (0x0000000AUL) /**< CRYPTO1 used bits */
+#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */
+#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */
+#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */
+#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
+#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
+#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
+#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
+#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */
+#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */
+#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */
+#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */
+#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */
+#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */
+#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */
+#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define CRYPTO1_BITSET_MEM_BASE (0x460F0400UL) /**< CRYPTO1_BITSET base address */
+#define CRYPTO1_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO1_BITSET available address space */
+#define CRYPTO1_BITSET_MEM_END (0x460F07FFUL) /**< CRYPTO1_BITSET end address */
+#define CRYPTO1_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITSET used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x20000UL) /**< RAM available address space */
+#define RAM_MEM_END (0x2001FFFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x00000011UL) /**< RAM used bits */
+#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */
+#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */
+#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */
+#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */
+#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
+#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
+#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
+#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xF0000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460EFFFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xF0000UL) /**< PER available address space */
+#define PER_MEM_END (0x400EFFFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */
+#define RAM2_CODE_MEM_SIZE (0x800UL) /**< RAM2_CODE available address space */
+#define RAM2_CODE_MEM_END (0x100407FFUL) /**< RAM2_CODE end address */
+#define RAM2_CODE_MEM_BITS (0x0000000BUL) /**< RAM2_CODE used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xF0000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440EFFFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
/** Bit banding area */
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
-/** Flash and SRAM limits for EFR32FG13P231F512GM32 */
+/** Flash and SRAM limits for EFR32FG12P431F512GM68 */
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */
-#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size (interleaving off) */
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
-#define SRAM_SIZE (0x00010000UL) /**< Available SRAM Memory */
-#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
+#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
-#define EXT_IRQ_COUNT 47 /**< Number of External (NVIC) interrupts */
+#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */
/** AF channels connect the different on-chip peripherals with the af-mux */
-#define AFCHAN_MAX 118U
+#define AFCHAN_MAX 136U
/** AF channel maximum location number */
#define AFCHANLOC_MAX 32U
/** Analog AF channels */
-#define AFACHAN_MAX 118U
+#define AFACHAN_MAX 125U
/* Part number capabilities */
@@ -259,27 +272,27 @@ typedef enum IRQn{
#define TIMER_PRESENT /**< TIMER is available in this part */
#define TIMER_COUNT 2 /**< 2 TIMERs available */
#define WTIMER_PRESENT /**< WTIMER is available in this part */
-#define WTIMER_COUNT 1 /**< 1 WTIMERs available */
+#define WTIMER_COUNT 2 /**< 2 WTIMERs available */
#define USART_PRESENT /**< USART is available in this part */
-#define USART_COUNT 3 /**< 3 USARTs available */
+#define USART_COUNT 4 /**< 4 USARTs available */
#define LEUART_PRESENT /**< LEUART is available in this part */
#define LEUART_COUNT 1 /**< 1 LEUARTs available */
#define LETIMER_PRESENT /**< LETIMER is available in this part */
#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
#define PCNT_PRESENT /**< PCNT is available in this part */
-#define PCNT_COUNT 1 /**< 1 PCNTs available */
+#define PCNT_COUNT 3 /**< 3 PCNTs available */
#define I2C_PRESENT /**< I2C is available in this part */
#define I2C_COUNT 2 /**< 2 I2Cs available */
#define ADC_PRESENT /**< ADC is available in this part */
#define ADC_COUNT 1 /**< 1 ADCs available */
#define ACMP_PRESENT /**< ACMP is available in this part */
#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
#define VDAC_PRESENT /**< VDAC is available in this part */
#define VDAC_COUNT 1 /**< 1 VDACs available */
#define WDOG_PRESENT /**< WDOG is available in this part */
#define WDOG_COUNT 2 /**< 2 WDOGs available */
-#define IDAC_PRESENT /**< IDAC is available in this part */
-#define IDAC_COUNT 1 /**< 1 IDACs available */
#define TRNG_PRESENT /**< TRNG is available in this part */
#define TRNG_COUNT 1 /**< 1 TRNGs available */
#define MSC_PRESENT /**< MSC is available in this part */
@@ -317,66 +330,66 @@ typedef enum IRQn{
#define DCDC_PRESENT /**< DCDC is available in this part */
#define DCDC_COUNT 1 /**< 1 DCDC available */
-#include "../../../efr32/cmsis/core_cm4.h" /* Cortex-M4 processor and core peripherals */
-#include "../../../efr32/vendor/efr32fg13/system_efr32fg13p.h" /* System Header File */
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32fg12p.h" /* System Header File */
-/** @} End of group EFR32FG13P231F512GM32_Part */
+/** @} End of group EFR32FG12P431F512GM68_Part */
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512GM32_Peripheral_TypeDefs Peripheral TypeDefs
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F512GM68_Peripheral_TypeDefs Peripheral TypeDefs
* @{
* @brief Device Specific Peripheral Register Structures
- *****************************************************************************/
-
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_msc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_emu.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_rmu.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_cmu.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_crypto.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_gpio_p.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_gpio.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_prs_ch.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_prs.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_ldma_ch.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_ldma.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_fpueh.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_gpcrc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_timer_cc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_timer.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_usart.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_leuart.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_letimer.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_cryotimer.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_pcnt.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_i2c.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_adc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_acmp.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_vdac_opa.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_vdac.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_csen.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_lesense_st.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_lesense_buf.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_lesense_ch.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_lesense.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_rtcc_cc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_rtcc_ret.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_rtcc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_wdog_pch.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_wdog.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_etm.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_idac.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_smu.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_trng.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_dma_descriptor.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_devinfo.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_romtable.h"
-
-/** @} End of group EFR32FG13P231F512GM32_Peripheral_TypeDefs */
-
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512GM32_Peripheral_Base Peripheral Memory Map
+ ******************************************************************************/
+
+#include "efr32fg12p_msc.h"
+#include "efr32fg12p_emu.h"
+#include "efr32fg12p_rmu.h"
+#include "efr32fg12p_cmu.h"
+#include "efr32fg12p_crypto.h"
+#include "efr32fg12p_gpio_p.h"
+#include "efr32fg12p_gpio.h"
+#include "efr32fg12p_prs_ch.h"
+#include "efr32fg12p_prs.h"
+#include "efr32fg12p_ldma_ch.h"
+#include "efr32fg12p_ldma.h"
+#include "efr32fg12p_fpueh.h"
+#include "efr32fg12p_gpcrc.h"
+#include "efr32fg12p_timer_cc.h"
+#include "efr32fg12p_timer.h"
+#include "efr32fg12p_usart.h"
+#include "efr32fg12p_leuart.h"
+#include "efr32fg12p_letimer.h"
+#include "efr32fg12p_cryotimer.h"
+#include "efr32fg12p_pcnt.h"
+#include "efr32fg12p_i2c.h"
+#include "efr32fg12p_adc.h"
+#include "efr32fg12p_acmp.h"
+#include "efr32fg12p_idac.h"
+#include "efr32fg12p_vdac_opa.h"
+#include "efr32fg12p_vdac.h"
+#include "efr32fg12p_csen.h"
+#include "efr32fg12p_lesense_st.h"
+#include "efr32fg12p_lesense_buf.h"
+#include "efr32fg12p_lesense_ch.h"
+#include "efr32fg12p_lesense.h"
+#include "efr32fg12p_rtcc_cc.h"
+#include "efr32fg12p_rtcc_ret.h"
+#include "efr32fg12p_rtcc.h"
+#include "efr32fg12p_wdog_pch.h"
+#include "efr32fg12p_wdog.h"
+#include "efr32fg12p_etm.h"
+#include "efr32fg12p_smu.h"
+#include "efr32fg12p_trng.h"
+#include "efr32fg12p_dma_descriptor.h"
+#include "efr32fg12p_devinfo.h"
+#include "efr32fg12p_romtable.h"
+
+/** @} End of group EFR32FG12P431F512GM68_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F512GM68_Peripheral_Base Peripheral Memory Map
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC_BASE (0x400E0000UL) /**< MSC base address */
#define EMU_BASE (0x400E3000UL) /**< EMU base address */
@@ -393,18 +406,23 @@ typedef enum IRQn{
#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */
+#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */
#define USART0_BASE (0x40010000UL) /**< USART0 base address */
#define USART1_BASE (0x40010400UL) /**< USART1 base address */
#define USART2_BASE (0x40010800UL) /**< USART2 base address */
+#define USART3_BASE (0x40010C00UL) /**< USART3 base address */
#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
+#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */
+#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */
#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */
#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
+#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */
#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */
#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */
@@ -412,7 +430,6 @@ typedef enum IRQn{
#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */
#define ETM_BASE (0xE0041000UL) /**< ETM base address */
-#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
#define SMU_BASE (0x40022000UL) /**< SMU base address */
#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */
#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
@@ -420,12 +437,12 @@ typedef enum IRQn{
#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
-/** @} End of group EFR32FG13P231F512GM32_Peripheral_Base */
+/** @} End of group EFR32FG12P431F512GM68_Peripheral_Base */
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512GM32_Peripheral_Declaration Peripheral Declarations
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F512GM68_Peripheral_Declaration Peripheral Declarations
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
@@ -442,18 +459,23 @@ typedef enum IRQn{
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */
+#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
+#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
+#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
+#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
+#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */
#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */
#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
@@ -461,18 +483,17 @@ typedef enum IRQn{
#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */
#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
-#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */
#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
-/** @} End of group EFR32FG13P231F512GM32_Peripheral_Declaration */
+/** @} End of group EFR32FG12P431F512GM68_Peripheral_Declaration */
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512GM32_Peripheral_Offsets Peripheral Offsets
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F512GM68_Peripheral_Offsets Peripheral Offsets
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */
#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
@@ -484,31 +505,31 @@ typedef enum IRQn{
#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
+#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */
#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
-#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */
-/** @} End of group EFR32FG13P231F512GM32_Peripheral_Offsets */
+/** @} End of group EFR32FG12P431F512GM68_Peripheral_Offsets */
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512GM32_BitFields Bit Fields
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F512GM68_BitFields Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_prs_signals.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_dmareq.h"
+#include "efr32fg12p_prs_signals.h"
+#include "efr32fg12p_dmareq.h"
-/**************************************************************************//**
- * @addtogroup EFR32FG13P231F512GM32_WTIMER
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P431F512GM68_WTIMER
* @{
- * @defgroup EFR32FG13P231F512GM32_WTIMER_BitFields WTIMER Bit Fields
+ * @defgroup EFR32FG12P431F512GM68_WTIMER_BitFields WTIMER Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for WTIMER CTRL */
#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */
-#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */
+#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */
#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
@@ -579,11 +600,6 @@ typedef enum IRQn{
#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */
#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */
-#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */
-#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */
-#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */
#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */
#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */
#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
@@ -1010,13 +1026,13 @@ typedef enum IRQn{
#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */
-#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */
+#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */
-#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */
+#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */
@@ -1997,23 +2013,23 @@ typedef enum IRQn{
#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */
-#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */
+#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */
-#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */
+#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */
/** @} */
-/** @} End of group EFR32FG13P231F512GM32_WTIMER */
+/** @} End of group EFR32FG12P431F512GM68_WTIMER */
-/**************************************************************************//**
- * @defgroup EFR32FG13P231F512GM32_UNLOCK Unlock Codes
+/***************************************************************************//**
+ * @defgroup EFR32FG12P431F512GM68_UNLOCK Unlock Codes
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
@@ -2022,18 +2038,19 @@ typedef enum IRQn{
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
-/** @} End of group EFR32FG13P231F512GM32_UNLOCK */
+/** @} End of group EFR32FG12P431F512GM68_UNLOCK */
-/** @} End of group EFR32FG13P231F512GM32_BitFields */
+/** @} End of group EFR32FG12P431F512GM68_BitFields */
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_af_ports.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_af_pins.h"
+#include "efr32fg12p_af_ports.h"
+#include "efr32fg12p_af_pins.h"
-/** @} End of group EFR32FG13P231F512GM32 */
+/** @} End of group EFR32FG12P431F512GM68 */
/** @} End of group Parts */
#ifdef __cplusplus
}
#endif
-#endif /* EFR32FG13P231F512GM32_H */
+
+#endif /* EFR32FG12P431F512GM68_H */
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p432f1024gl125.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p432f1024gl125.h
similarity index 91%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p432f1024gl125.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p432f1024gl125.h
index fe952569..31168e5d 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p432f1024gl125.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p432f1024gl125.h
@@ -1,35 +1,39 @@
-/**************************************************************************//**
- * @file efr32fg12p432f1024gl125.h
+/***************************************************************************//**
+ * @file
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
* for EFR32FG12P432F1024GL125
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
#ifndef EFR32FG12P432F1024GL125_H
#define EFR32FG12P432F1024GL125_H
@@ -38,111 +42,120 @@
extern "C" {
#endif
-/**************************************************************************//**
+/***************************************************************************//**
* @addtogroup Parts
* @{
- *****************************************************************************/
+ ******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFR32FG12P432F1024GL125 EFR32FG12P432F1024GL125
* @{
- *****************************************************************************/
+ ******************************************************************************/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
+typedef enum IRQn{
/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
- NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */
- HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */
- MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
/****** EFR32FG12P Peripheral Interrupt Numbers ********************************************/
- EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */
- WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */
- WDOG1_IRQn = 3, /*!< 3 EFR32 WDOG1 Interrupt */
- LDMA_IRQn = 9, /*!< 9 EFR32 LDMA Interrupt */
- GPIO_EVEN_IRQn = 10, /*!< 10 EFR32 GPIO_EVEN Interrupt */
- TIMER0_IRQn = 11, /*!< 11 EFR32 TIMER0 Interrupt */
- USART0_RX_IRQn = 12, /*!< 12 EFR32 USART0_RX Interrupt */
- USART0_TX_IRQn = 13, /*!< 13 EFR32 USART0_TX Interrupt */
- ACMP0_IRQn = 14, /*!< 14 EFR32 ACMP0 Interrupt */
- ADC0_IRQn = 15, /*!< 15 EFR32 ADC0 Interrupt */
- IDAC0_IRQn = 16, /*!< 16 EFR32 IDAC0 Interrupt */
- I2C0_IRQn = 17, /*!< 17 EFR32 I2C0 Interrupt */
- GPIO_ODD_IRQn = 18, /*!< 18 EFR32 GPIO_ODD Interrupt */
- TIMER1_IRQn = 19, /*!< 19 EFR32 TIMER1 Interrupt */
- USART1_RX_IRQn = 20, /*!< 20 EFR32 USART1_RX Interrupt */
- USART1_TX_IRQn = 21, /*!< 21 EFR32 USART1_TX Interrupt */
- LEUART0_IRQn = 22, /*!< 22 EFR32 LEUART0 Interrupt */
- PCNT0_IRQn = 23, /*!< 23 EFR32 PCNT0 Interrupt */
- CMU_IRQn = 24, /*!< 24 EFR32 CMU Interrupt */
- MSC_IRQn = 25, /*!< 25 EFR32 MSC Interrupt */
- CRYPTO0_IRQn = 26, /*!< 26 EFR32 CRYPTO0 Interrupt */
- LETIMER0_IRQn = 27, /*!< 27 EFR32 LETIMER0 Interrupt */
- RTCC_IRQn = 30, /*!< 30 EFR32 RTCC Interrupt */
- CRYOTIMER_IRQn = 32, /*!< 32 EFR32 CRYOTIMER Interrupt */
- FPUEH_IRQn = 34, /*!< 34 EFR32 FPUEH Interrupt */
- SMU_IRQn = 35, /*!< 35 EFR32 SMU Interrupt */
- WTIMER0_IRQn = 36, /*!< 36 EFR32 WTIMER0 Interrupt */
- WTIMER1_IRQn = 37, /*!< 37 EFR32 WTIMER1 Interrupt */
- PCNT1_IRQn = 38, /*!< 38 EFR32 PCNT1 Interrupt */
- PCNT2_IRQn = 39, /*!< 39 EFR32 PCNT2 Interrupt */
- USART2_RX_IRQn = 40, /*!< 40 EFR32 USART2_RX Interrupt */
- USART2_TX_IRQn = 41, /*!< 41 EFR32 USART2_TX Interrupt */
- I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */
- USART3_RX_IRQn = 43, /*!< 43 EFR32 USART3_RX Interrupt */
- USART3_TX_IRQn = 44, /*!< 44 EFR32 USART3_TX Interrupt */
- VDAC0_IRQn = 45, /*!< 45 EFR32 VDAC0 Interrupt */
- CSEN_IRQn = 46, /*!< 46 EFR32 CSEN Interrupt */
- LESENSE_IRQn = 47, /*!< 47 EFR32 LESENSE Interrupt */
- CRYPTO1_IRQn = 48, /*!< 48 EFR32 CRYPTO1 Interrupt */
- TRNG0_IRQn = 49, /*!< 49 EFR32 TRNG0 Interrupt */
+ EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
+ WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 3, /*!< 16+3 EFR32 WDOG1 Interrupt */
+ FRC_IRQn = 4, /*!< 16+4 EFR32 FRC Interrupt */
+ MODEM_IRQn = 5, /*!< 16+5 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 6, /*!< 16+6 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 7, /*!< 16+7 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 8, /*!< 16+8 EFR32 BUFC Interrupt */
+ LDMA_IRQn = 9, /*!< 16+9 EFR32 LDMA Interrupt */
+ GPIO_EVEN_IRQn = 10, /*!< 16+10 EFR32 GPIO_EVEN Interrupt */
+ TIMER0_IRQn = 11, /*!< 16+11 EFR32 TIMER0 Interrupt */
+ USART0_RX_IRQn = 12, /*!< 16+12 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 13, /*!< 16+13 EFR32 USART0_TX Interrupt */
+ ACMP0_IRQn = 14, /*!< 16+14 EFR32 ACMP0 Interrupt */
+ ADC0_IRQn = 15, /*!< 16+15 EFR32 ADC0 Interrupt */
+ IDAC0_IRQn = 16, /*!< 16+16 EFR32 IDAC0 Interrupt */
+ I2C0_IRQn = 17, /*!< 16+17 EFR32 I2C0 Interrupt */
+ GPIO_ODD_IRQn = 18, /*!< 16+18 EFR32 GPIO_ODD Interrupt */
+ TIMER1_IRQn = 19, /*!< 16+19 EFR32 TIMER1 Interrupt */
+ USART1_RX_IRQn = 20, /*!< 16+20 EFR32 USART1_RX Interrupt */
+ USART1_TX_IRQn = 21, /*!< 16+21 EFR32 USART1_TX Interrupt */
+ LEUART0_IRQn = 22, /*!< 16+22 EFR32 LEUART0 Interrupt */
+ PCNT0_IRQn = 23, /*!< 16+23 EFR32 PCNT0 Interrupt */
+ CMU_IRQn = 24, /*!< 16+24 EFR32 CMU Interrupt */
+ MSC_IRQn = 25, /*!< 16+25 EFR32 MSC Interrupt */
+ CRYPTO0_IRQn = 26, /*!< 16+26 EFR32 CRYPTO0 Interrupt */
+ LETIMER0_IRQn = 27, /*!< 16+27 EFR32 LETIMER0 Interrupt */
+ AGC_IRQn = 28, /*!< 16+28 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 29, /*!< 16+29 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 30, /*!< 16+30 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 31, /*!< 16+31 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 32, /*!< 16+32 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 33, /*!< 16+33 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 34, /*!< 16+34 EFR32 FPUEH Interrupt */
+ SMU_IRQn = 35, /*!< 16+35 EFR32 SMU Interrupt */
+ WTIMER0_IRQn = 36, /*!< 16+36 EFR32 WTIMER0 Interrupt */
+ WTIMER1_IRQn = 37, /*!< 16+37 EFR32 WTIMER1 Interrupt */
+ PCNT1_IRQn = 38, /*!< 16+38 EFR32 PCNT1 Interrupt */
+ PCNT2_IRQn = 39, /*!< 16+39 EFR32 PCNT2 Interrupt */
+ USART2_RX_IRQn = 40, /*!< 16+40 EFR32 USART2_RX Interrupt */
+ USART2_TX_IRQn = 41, /*!< 16+41 EFR32 USART2_TX Interrupt */
+ I2C1_IRQn = 42, /*!< 16+42 EFR32 I2C1 Interrupt */
+ USART3_RX_IRQn = 43, /*!< 16+43 EFR32 USART3_RX Interrupt */
+ USART3_TX_IRQn = 44, /*!< 16+44 EFR32 USART3_TX Interrupt */
+ VDAC0_IRQn = 45, /*!< 16+45 EFR32 VDAC0 Interrupt */
+ CSEN_IRQn = 46, /*!< 16+46 EFR32 CSEN Interrupt */
+ LESENSE_IRQn = 47, /*!< 16+47 EFR32 LESENSE Interrupt */
+ CRYPTO1_IRQn = 48, /*!< 16+48 EFR32 CRYPTO1 Interrupt */
+ TRNG0_IRQn = 49, /*!< 16+49 EFR32 TRNG0 Interrupt */
} IRQn_Type;
#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */
-/**************************************************************************//**
- * @defgroup EFR32FG12P432F1024GL125_Core EFR32FG12P432F1024GL125 Core
+/***************************************************************************//**
+ * @defgroup EFR32FG12P432F1024GL125_Core Core
* @{
* @brief Processor and Core Peripheral Section
- *****************************************************************************/
-#define __MPU_PRESENT 1 /**< Presence of MPU */
-#define __FPU_PRESENT 1 /**< Presence of FPU */
-#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
/** @} End of group EFR32FG12P432F1024GL125_Core */
-/**************************************************************************//**
-* @defgroup EFR32FG12P432F1024GL125_Part EFR32FG12P432F1024GL125 Part
-* @{
-******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P432F1024GL125_Part Part
+ * @{
+ ******************************************************************************/
/** Part family */
-#define _EFR32_FLEX_FAMILY 1 /**< FLEX Gecko RF SoC Family */
-#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
-#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
-#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */
-#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1
-#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2
-#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3
-#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ
-#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
-#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */
+#define _EFR32_FLEX_FAMILY 1 /**< FLEX Gecko RF SoC Family */
+#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
+#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /**< Radio type */
+#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */
/* If part number is not defined as compiler option, define it */
#if !defined(EFR32FG12P432F1024GL125)
@@ -153,179 +166,180 @@ typedef enum IRQn
#define PART_NUMBER "EFR32FG12P432F1024GL125" /**< Part Number */
/** Memory Base addresses and limits */
-#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */
-#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */
-#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */
-#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */
-#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */
-#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */
-#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */
-#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */
-#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */
-#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */
-#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */
-#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */
-#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */
-#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */
-#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
-#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
-#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */
-#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */
-#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */
-#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */
-#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */
-#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */
-#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */
-#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */
-#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */
-#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */
-#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */
-#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
-#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
-#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */
-#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */
-#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */
-#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */
-#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */
-#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
-#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
-#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
-#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
-#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
-#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */
-#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */
-#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */
-#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */
-#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */
-#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */
-#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */
-#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
-#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
-#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
-#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
-#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */
-#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */
-#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
-#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
-#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
-#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
-#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
-#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
-#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
-#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */
-#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */
-#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */
-#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */
-#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */
-#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */
-#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */
-#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */
-#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */
-#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */
-#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
-#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */
-#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */
-#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */
+#define CRYPTO1_BITCLR_MEM_BASE (0x440F0400UL) /**< CRYPTO1_BITCLR base address */
+#define CRYPTO1_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO1_BITCLR available address space */
+#define CRYPTO1_BITCLR_MEM_END (0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
+#define CRYPTO1_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
+#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */
+#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */
+#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */
+#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */
+#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */
+#define RAM2_MEM_SIZE (0x800UL) /**< RAM2 available address space */
+#define RAM2_MEM_END (0x200407FFUL) /**< RAM2 end address */
+#define RAM2_MEM_BITS (0x0000000BUL) /**< RAM2 used bits */
+#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */
+#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */
+#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
+#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
+#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
+#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
+#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
+#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
+#define CRYPTO1_MEM_BASE (0x400F0400UL) /**< CRYPTO1 base address */
+#define CRYPTO1_MEM_SIZE (0x400UL) /**< CRYPTO1 available address space */
+#define CRYPTO1_MEM_END (0x400F07FFUL) /**< CRYPTO1 end address */
+#define CRYPTO1_MEM_BITS (0x0000000AUL) /**< CRYPTO1 used bits */
+#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */
+#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */
+#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */
+#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
+#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
+#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
+#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
+#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */
+#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */
+#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */
+#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */
+#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */
+#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */
+#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */
+#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define CRYPTO1_BITSET_MEM_BASE (0x460F0400UL) /**< CRYPTO1_BITSET base address */
+#define CRYPTO1_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO1_BITSET available address space */
+#define CRYPTO1_BITSET_MEM_END (0x460F07FFUL) /**< CRYPTO1_BITSET end address */
+#define CRYPTO1_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITSET used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x20000UL) /**< RAM available address space */
+#define RAM_MEM_END (0x2001FFFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x00000011UL) /**< RAM used bits */
+#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */
+#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */
+#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */
+#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */
+#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
+#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
+#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
+#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xF0000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460EFFFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xF0000UL) /**< PER available address space */
+#define PER_MEM_END (0x400EFFFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */
+#define RAM2_CODE_MEM_SIZE (0x800UL) /**< RAM2_CODE available address space */
+#define RAM2_CODE_MEM_END (0x100407FFUL) /**< RAM2_CODE end address */
+#define RAM2_CODE_MEM_BITS (0x0000000BUL) /**< RAM2_CODE used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xF0000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440EFFFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
/** Bit banding area */
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
/** Flash and SRAM limits for EFR32FG12P432F1024GL125 */
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */
-#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size (interleaving off) */
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
-#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */
/** AF channels connect the different on-chip peripherals with the af-mux */
-#define AFCHAN_MAX 136
-#define AFCHANLOC_MAX 32
+#define AFCHAN_MAX 136U
+/** AF channel maximum location number */
+#define AFCHANLOC_MAX 32U
/** Analog AF channels */
-#define AFACHAN_MAX 125
+#define AFACHAN_MAX 125U
/* Part number capabilities */
-#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
-#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */
-#define TIMER_PRESENT /**< TIMER is available in this part */
-#define TIMER_COUNT 2 /**< 2 TIMERs available */
-#define WTIMER_PRESENT /**< WTIMER is available in this part */
-#define WTIMER_COUNT 2 /**< 2 WTIMERs available */
-#define USART_PRESENT /**< USART is available in this part */
-#define USART_COUNT 4 /**< 4 USARTs available */
-#define LEUART_PRESENT /**< LEUART is available in this part */
-#define LEUART_COUNT 1 /**< 1 LEUARTs available */
-#define LETIMER_PRESENT /**< LETIMER is available in this part */
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
-#define PCNT_PRESENT /**< PCNT is available in this part */
-#define PCNT_COUNT 3 /**< 3 PCNTs available */
-#define I2C_PRESENT /**< I2C is available in this part */
-#define I2C_COUNT 2 /**< 2 I2Cs available */
-#define ADC_PRESENT /**< ADC is available in this part */
-#define ADC_COUNT 1 /**< 1 ADCs available */
-#define ACMP_PRESENT /**< ACMP is available in this part */
-#define ACMP_COUNT 2 /**< 2 ACMPs available */
-#define IDAC_PRESENT /**< IDAC is available in this part */
-#define IDAC_COUNT 1 /**< 1 IDACs available */
-#define VDAC_PRESENT /**< VDAC is available in this part */
-#define VDAC_COUNT 1 /**< 1 VDACs available */
-#define WDOG_PRESENT /**< WDOG is available in this part */
-#define WDOG_COUNT 2 /**< 2 WDOGs available */
-#define TRNG_PRESENT /**< TRNG is available in this part */
-#define TRNG_COUNT 1 /**< 1 TRNGs available */
-#define SYSTICK_PRESENT
-#define SYSTICK_COUNT 1
-#define MSC_PRESENT
-#define MSC_COUNT 1
-#define EMU_PRESENT
-#define EMU_COUNT 1
-#define RMU_PRESENT
-#define RMU_COUNT 1
-#define CMU_PRESENT
-#define CMU_COUNT 1
-#define GPIO_PRESENT
-#define GPIO_COUNT 1
-#define PRS_PRESENT
-#define PRS_COUNT 1
-#define LDMA_PRESENT
-#define LDMA_COUNT 1
-#define FPUEH_PRESENT
-#define FPUEH_COUNT 1
-#define GPCRC_PRESENT
-#define GPCRC_COUNT 1
-#define CRYOTIMER_PRESENT
-#define CRYOTIMER_COUNT 1
-#define CSEN_PRESENT
-#define CSEN_COUNT 1
-#define LESENSE_PRESENT
-#define LESENSE_COUNT 1
-#define RTCC_PRESENT
-#define RTCC_COUNT 1
-#define ETM_PRESENT
-#define ETM_COUNT 1
-#define BOOTLOADER_PRESENT
-#define BOOTLOADER_COUNT 1
-#define SMU_PRESENT
-#define SMU_COUNT 1
-
-#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
-#include "system_efr32fg12p.h" /* System Header File */
+#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
+#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */
+#define TIMER_PRESENT /**< TIMER is available in this part */
+#define TIMER_COUNT 2 /**< 2 TIMERs available */
+#define WTIMER_PRESENT /**< WTIMER is available in this part */
+#define WTIMER_COUNT 2 /**< 2 WTIMERs available */
+#define USART_PRESENT /**< USART is available in this part */
+#define USART_COUNT 4 /**< 4 USARTs available */
+#define LEUART_PRESENT /**< LEUART is available in this part */
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */
+#define LETIMER_PRESENT /**< LETIMER is available in this part */
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
+#define PCNT_PRESENT /**< PCNT is available in this part */
+#define PCNT_COUNT 3 /**< 3 PCNTs available */
+#define I2C_PRESENT /**< I2C is available in this part */
+#define I2C_COUNT 2 /**< 2 I2Cs available */
+#define ADC_PRESENT /**< ADC is available in this part */
+#define ADC_COUNT 1 /**< 1 ADCs available */
+#define ACMP_PRESENT /**< ACMP is available in this part */
+#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
+#define VDAC_PRESENT /**< VDAC is available in this part */
+#define VDAC_COUNT 1 /**< 1 VDACs available */
+#define WDOG_PRESENT /**< WDOG is available in this part */
+#define WDOG_COUNT 2 /**< 2 WDOGs available */
+#define TRNG_PRESENT /**< TRNG is available in this part */
+#define TRNG_COUNT 1 /**< 1 TRNGs available */
+#define MSC_PRESENT /**< MSC is available in this part */
+#define MSC_COUNT 1 /**< 1 MSC available */
+#define EMU_PRESENT /**< EMU is available in this part */
+#define EMU_COUNT 1 /**< 1 EMU available */
+#define RMU_PRESENT /**< RMU is available in this part */
+#define RMU_COUNT 1 /**< 1 RMU available */
+#define CMU_PRESENT /**< CMU is available in this part */
+#define CMU_COUNT 1 /**< 1 CMU available */
+#define GPIO_PRESENT /**< GPIO is available in this part */
+#define GPIO_COUNT 1 /**< 1 GPIO available */
+#define PRS_PRESENT /**< PRS is available in this part */
+#define PRS_COUNT 1 /**< 1 PRS available */
+#define LDMA_PRESENT /**< LDMA is available in this part */
+#define LDMA_COUNT 1 /**< 1 LDMA available */
+#define FPUEH_PRESENT /**< FPUEH is available in this part */
+#define FPUEH_COUNT 1 /**< 1 FPUEH available */
+#define GPCRC_PRESENT /**< GPCRC is available in this part */
+#define GPCRC_COUNT 1 /**< 1 GPCRC available */
+#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
+#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
+#define CSEN_PRESENT /**< CSEN is available in this part */
+#define CSEN_COUNT 1 /**< 1 CSEN available */
+#define LESENSE_PRESENT /**< LESENSE is available in this part */
+#define LESENSE_COUNT 1 /**< 1 LESENSE available */
+#define RTCC_PRESENT /**< RTCC is available in this part */
+#define RTCC_COUNT 1 /**< 1 RTCC available */
+#define ETM_PRESENT /**< ETM is available in this part */
+#define ETM_COUNT 1 /**< 1 ETM available */
+#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
+#define SMU_PRESENT /**< SMU is available in this part */
+#define SMU_COUNT 1 /**< 1 SMU available */
+#define DCDC_PRESENT /**< DCDC is available in this part */
+#define DCDC_COUNT 1 /**< 1 DCDC available */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32fg12p.h" /* System Header File */
/** @} End of group EFR32FG12P432F1024GL125_Part */
-/**************************************************************************//**
- * @defgroup EFR32FG12P432F1024GL125_Peripheral_TypeDefs EFR32FG12P432F1024GL125 Peripheral TypeDefs
+/***************************************************************************//**
+ * @defgroup EFR32FG12P432F1024GL125_Peripheral_TypeDefs Peripheral TypeDefs
* @{
* @brief Device Specific Peripheral Register Structures
- *****************************************************************************/
+ ******************************************************************************/
#include "efr32fg12p_msc.h"
#include "efr32fg12p_emu.h"
@@ -372,10 +386,10 @@ typedef enum IRQn
/** @} End of group EFR32FG12P432F1024GL125_Peripheral_TypeDefs */
-/**************************************************************************//**
- * @defgroup EFR32FG12P432F1024GL125_Peripheral_Base EFR32FG12P432F1024GL125 Peripheral Memory Map
+/***************************************************************************//**
+ * @defgroup EFR32FG12P432F1024GL125_Peripheral_Base Peripheral Memory Map
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC_BASE (0x400E0000UL) /**< MSC base address */
#define EMU_BASE (0x400E3000UL) /**< EMU base address */
@@ -425,10 +439,10 @@ typedef enum IRQn
/** @} End of group EFR32FG12P432F1024GL125_Peripheral_Base */
-/**************************************************************************//**
- * @defgroup EFR32FG12P432F1024GL125_Peripheral_Declaration EFR32FG12P432F1024GL125 Peripheral Declarations
+/***************************************************************************//**
+ * @defgroup EFR32FG12P432F1024GL125_Peripheral_Declaration Peripheral Declarations
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
@@ -476,10 +490,10 @@ typedef enum IRQn
/** @} End of group EFR32FG12P432F1024GL125_Peripheral_Declaration */
-/**************************************************************************//**
- * @defgroup EFR32FG12P432F1024GL125_Peripheral_Offsets EFR32FG12P432F1024GL125 Peripheral Offsets
+/***************************************************************************//**
+ * @defgroup EFR32FG12P432F1024GL125_Peripheral_Offsets Peripheral Offsets
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */
#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
@@ -498,19 +512,20 @@ typedef enum IRQn
/** @} End of group EFR32FG12P432F1024GL125_Peripheral_Offsets */
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P432F1024GL125_BitFields EFR32FG12P432F1024GL125 Bit Fields
+/***************************************************************************//**
+ * @defgroup EFR32FG12P432F1024GL125_BitFields Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
#include "efr32fg12p_prs_signals.h"
#include "efr32fg12p_dmareq.h"
-/**************************************************************************//**
- * @defgroup EFR32FG12P432F1024GL125_WTIMER_BitFields EFR32FG12P432F1024GL125_WTIMER Bit Fields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P432F1024GL125_WTIMER
+ * @{
+ * @defgroup EFR32FG12P432F1024GL125_WTIMER_BitFields WTIMER Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for WTIMER CTRL */
#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */
@@ -626,7 +641,7 @@ typedef enum IRQn
#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */
#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */
+#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */
#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */
#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */
#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
@@ -1011,13 +1026,13 @@ typedef enum IRQn
#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */
-#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */
+#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */
-#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */
+#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */
@@ -1731,7 +1746,7 @@ typedef enum IRQn
#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */
#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */
+#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */
#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */
#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */
#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
@@ -1998,33 +2013,23 @@ typedef enum IRQn
#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */
-#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */
+#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */
-#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */
+#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */
+/** @} */
/** @} End of group EFR32FG12P432F1024GL125_WTIMER */
-
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P432F1024GL125_SYSTICK_BitFields EFR32FG12P432F1024GL125_SYSTICK Bit Fields
- * @{
- *****************************************************************************/
-
-/** @} End of group EFR32FG12P432F1024GL125_SYSTICK */
-
-
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P432F1024GL125_UNLOCK EFR32FG12P432F1024GL125 Unlock Codes
+/***************************************************************************//**
+ * @defgroup EFR32FG12P432F1024GL125_UNLOCK Unlock Codes
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
@@ -2037,16 +2042,9 @@ typedef enum IRQn
/** @} End of group EFR32FG12P432F1024GL125_BitFields */
-/**************************************************************************//**
- * @defgroup EFR32FG12P432F1024GL125_Alternate_Function EFR32FG12P432F1024GL125 Alternate Function
- * @{
- *****************************************************************************/
-
#include "efr32fg12p_af_ports.h"
#include "efr32fg12p_af_pins.h"
-/** @} End of group EFR32FG12P432F1024GL125_Alternate_Function */
-
/** @} End of group EFR32FG12P432F1024GL125 */
/** @} End of group Parts */
@@ -2054,4 +2052,5 @@ typedef enum IRQn
#ifdef __cplusplus
}
#endif
+
#endif /* EFR32FG12P432F1024GL125_H */
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p432f1024gm48.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p432f1024gm48.h
similarity index 91%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p432f1024gm48.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p432f1024gm48.h
index ae13d279..ce442c40 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p432f1024gm48.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p432f1024gm48.h
@@ -1,35 +1,39 @@
-/**************************************************************************//**
- * @file efr32fg12p432f1024gm48.h
+/***************************************************************************//**
+ * @file
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
* for EFR32FG12P432F1024GM48
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
#ifndef EFR32FG12P432F1024GM48_H
#define EFR32FG12P432F1024GM48_H
@@ -38,111 +42,120 @@
extern "C" {
#endif
-/**************************************************************************//**
+/***************************************************************************//**
* @addtogroup Parts
* @{
- *****************************************************************************/
+ ******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFR32FG12P432F1024GM48 EFR32FG12P432F1024GM48
* @{
- *****************************************************************************/
+ ******************************************************************************/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
+typedef enum IRQn{
/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
- NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */
- HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */
- MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
/****** EFR32FG12P Peripheral Interrupt Numbers ********************************************/
- EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */
- WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */
- WDOG1_IRQn = 3, /*!< 3 EFR32 WDOG1 Interrupt */
- LDMA_IRQn = 9, /*!< 9 EFR32 LDMA Interrupt */
- GPIO_EVEN_IRQn = 10, /*!< 10 EFR32 GPIO_EVEN Interrupt */
- TIMER0_IRQn = 11, /*!< 11 EFR32 TIMER0 Interrupt */
- USART0_RX_IRQn = 12, /*!< 12 EFR32 USART0_RX Interrupt */
- USART0_TX_IRQn = 13, /*!< 13 EFR32 USART0_TX Interrupt */
- ACMP0_IRQn = 14, /*!< 14 EFR32 ACMP0 Interrupt */
- ADC0_IRQn = 15, /*!< 15 EFR32 ADC0 Interrupt */
- IDAC0_IRQn = 16, /*!< 16 EFR32 IDAC0 Interrupt */
- I2C0_IRQn = 17, /*!< 17 EFR32 I2C0 Interrupt */
- GPIO_ODD_IRQn = 18, /*!< 18 EFR32 GPIO_ODD Interrupt */
- TIMER1_IRQn = 19, /*!< 19 EFR32 TIMER1 Interrupt */
- USART1_RX_IRQn = 20, /*!< 20 EFR32 USART1_RX Interrupt */
- USART1_TX_IRQn = 21, /*!< 21 EFR32 USART1_TX Interrupt */
- LEUART0_IRQn = 22, /*!< 22 EFR32 LEUART0 Interrupt */
- PCNT0_IRQn = 23, /*!< 23 EFR32 PCNT0 Interrupt */
- CMU_IRQn = 24, /*!< 24 EFR32 CMU Interrupt */
- MSC_IRQn = 25, /*!< 25 EFR32 MSC Interrupt */
- CRYPTO0_IRQn = 26, /*!< 26 EFR32 CRYPTO0 Interrupt */
- LETIMER0_IRQn = 27, /*!< 27 EFR32 LETIMER0 Interrupt */
- RTCC_IRQn = 30, /*!< 30 EFR32 RTCC Interrupt */
- CRYOTIMER_IRQn = 32, /*!< 32 EFR32 CRYOTIMER Interrupt */
- FPUEH_IRQn = 34, /*!< 34 EFR32 FPUEH Interrupt */
- SMU_IRQn = 35, /*!< 35 EFR32 SMU Interrupt */
- WTIMER0_IRQn = 36, /*!< 36 EFR32 WTIMER0 Interrupt */
- WTIMER1_IRQn = 37, /*!< 37 EFR32 WTIMER1 Interrupt */
- PCNT1_IRQn = 38, /*!< 38 EFR32 PCNT1 Interrupt */
- PCNT2_IRQn = 39, /*!< 39 EFR32 PCNT2 Interrupt */
- USART2_RX_IRQn = 40, /*!< 40 EFR32 USART2_RX Interrupt */
- USART2_TX_IRQn = 41, /*!< 41 EFR32 USART2_TX Interrupt */
- I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */
- USART3_RX_IRQn = 43, /*!< 43 EFR32 USART3_RX Interrupt */
- USART3_TX_IRQn = 44, /*!< 44 EFR32 USART3_TX Interrupt */
- VDAC0_IRQn = 45, /*!< 45 EFR32 VDAC0 Interrupt */
- CSEN_IRQn = 46, /*!< 46 EFR32 CSEN Interrupt */
- LESENSE_IRQn = 47, /*!< 47 EFR32 LESENSE Interrupt */
- CRYPTO1_IRQn = 48, /*!< 48 EFR32 CRYPTO1 Interrupt */
- TRNG0_IRQn = 49, /*!< 49 EFR32 TRNG0 Interrupt */
+ EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
+ WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 3, /*!< 16+3 EFR32 WDOG1 Interrupt */
+ FRC_IRQn = 4, /*!< 16+4 EFR32 FRC Interrupt */
+ MODEM_IRQn = 5, /*!< 16+5 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 6, /*!< 16+6 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 7, /*!< 16+7 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 8, /*!< 16+8 EFR32 BUFC Interrupt */
+ LDMA_IRQn = 9, /*!< 16+9 EFR32 LDMA Interrupt */
+ GPIO_EVEN_IRQn = 10, /*!< 16+10 EFR32 GPIO_EVEN Interrupt */
+ TIMER0_IRQn = 11, /*!< 16+11 EFR32 TIMER0 Interrupt */
+ USART0_RX_IRQn = 12, /*!< 16+12 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 13, /*!< 16+13 EFR32 USART0_TX Interrupt */
+ ACMP0_IRQn = 14, /*!< 16+14 EFR32 ACMP0 Interrupt */
+ ADC0_IRQn = 15, /*!< 16+15 EFR32 ADC0 Interrupt */
+ IDAC0_IRQn = 16, /*!< 16+16 EFR32 IDAC0 Interrupt */
+ I2C0_IRQn = 17, /*!< 16+17 EFR32 I2C0 Interrupt */
+ GPIO_ODD_IRQn = 18, /*!< 16+18 EFR32 GPIO_ODD Interrupt */
+ TIMER1_IRQn = 19, /*!< 16+19 EFR32 TIMER1 Interrupt */
+ USART1_RX_IRQn = 20, /*!< 16+20 EFR32 USART1_RX Interrupt */
+ USART1_TX_IRQn = 21, /*!< 16+21 EFR32 USART1_TX Interrupt */
+ LEUART0_IRQn = 22, /*!< 16+22 EFR32 LEUART0 Interrupt */
+ PCNT0_IRQn = 23, /*!< 16+23 EFR32 PCNT0 Interrupt */
+ CMU_IRQn = 24, /*!< 16+24 EFR32 CMU Interrupt */
+ MSC_IRQn = 25, /*!< 16+25 EFR32 MSC Interrupt */
+ CRYPTO0_IRQn = 26, /*!< 16+26 EFR32 CRYPTO0 Interrupt */
+ LETIMER0_IRQn = 27, /*!< 16+27 EFR32 LETIMER0 Interrupt */
+ AGC_IRQn = 28, /*!< 16+28 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 29, /*!< 16+29 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 30, /*!< 16+30 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 31, /*!< 16+31 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 32, /*!< 16+32 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 33, /*!< 16+33 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 34, /*!< 16+34 EFR32 FPUEH Interrupt */
+ SMU_IRQn = 35, /*!< 16+35 EFR32 SMU Interrupt */
+ WTIMER0_IRQn = 36, /*!< 16+36 EFR32 WTIMER0 Interrupt */
+ WTIMER1_IRQn = 37, /*!< 16+37 EFR32 WTIMER1 Interrupt */
+ PCNT1_IRQn = 38, /*!< 16+38 EFR32 PCNT1 Interrupt */
+ PCNT2_IRQn = 39, /*!< 16+39 EFR32 PCNT2 Interrupt */
+ USART2_RX_IRQn = 40, /*!< 16+40 EFR32 USART2_RX Interrupt */
+ USART2_TX_IRQn = 41, /*!< 16+41 EFR32 USART2_TX Interrupt */
+ I2C1_IRQn = 42, /*!< 16+42 EFR32 I2C1 Interrupt */
+ USART3_RX_IRQn = 43, /*!< 16+43 EFR32 USART3_RX Interrupt */
+ USART3_TX_IRQn = 44, /*!< 16+44 EFR32 USART3_TX Interrupt */
+ VDAC0_IRQn = 45, /*!< 16+45 EFR32 VDAC0 Interrupt */
+ CSEN_IRQn = 46, /*!< 16+46 EFR32 CSEN Interrupt */
+ LESENSE_IRQn = 47, /*!< 16+47 EFR32 LESENSE Interrupt */
+ CRYPTO1_IRQn = 48, /*!< 16+48 EFR32 CRYPTO1 Interrupt */
+ TRNG0_IRQn = 49, /*!< 16+49 EFR32 TRNG0 Interrupt */
} IRQn_Type;
#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */
-/**************************************************************************//**
- * @defgroup EFR32FG12P432F1024GM48_Core EFR32FG12P432F1024GM48 Core
+/***************************************************************************//**
+ * @defgroup EFR32FG12P432F1024GM48_Core Core
* @{
* @brief Processor and Core Peripheral Section
- *****************************************************************************/
-#define __MPU_PRESENT 1 /**< Presence of MPU */
-#define __FPU_PRESENT 1 /**< Presence of FPU */
-#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
/** @} End of group EFR32FG12P432F1024GM48_Core */
-/**************************************************************************//**
-* @defgroup EFR32FG12P432F1024GM48_Part EFR32FG12P432F1024GM48 Part
-* @{
-******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P432F1024GM48_Part Part
+ * @{
+ ******************************************************************************/
/** Part family */
-#define _EFR32_FLEX_FAMILY 1 /**< FLEX Gecko RF SoC Family */
-#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
-#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
-#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */
-#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1
-#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2
-#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3
-#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ
-#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
-#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */
+#define _EFR32_FLEX_FAMILY 1 /**< FLEX Gecko RF SoC Family */
+#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
+#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /**< Radio type */
+#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */
/* If part number is not defined as compiler option, define it */
#if !defined(EFR32FG12P432F1024GM48)
@@ -153,179 +166,180 @@ typedef enum IRQn
#define PART_NUMBER "EFR32FG12P432F1024GM48" /**< Part Number */
/** Memory Base addresses and limits */
-#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */
-#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */
-#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */
-#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */
-#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */
-#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */
-#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */
-#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */
-#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */
-#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */
-#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */
-#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */
-#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */
-#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */
-#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
-#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
-#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */
-#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */
-#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */
-#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */
-#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */
-#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */
-#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */
-#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */
-#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */
-#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */
-#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */
-#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
-#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
-#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */
-#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */
-#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */
-#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */
-#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */
-#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
-#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
-#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
-#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
-#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
-#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */
-#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */
-#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */
-#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */
-#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */
-#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */
-#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */
-#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
-#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
-#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
-#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
-#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */
-#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */
-#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
-#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
-#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
-#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
-#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
-#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
-#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
-#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */
-#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */
-#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */
-#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */
-#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */
-#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */
-#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */
-#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */
-#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */
-#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */
-#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
-#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */
-#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */
-#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */
+#define CRYPTO1_BITCLR_MEM_BASE (0x440F0400UL) /**< CRYPTO1_BITCLR base address */
+#define CRYPTO1_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO1_BITCLR available address space */
+#define CRYPTO1_BITCLR_MEM_END (0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
+#define CRYPTO1_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
+#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */
+#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */
+#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */
+#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */
+#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */
+#define RAM2_MEM_SIZE (0x800UL) /**< RAM2 available address space */
+#define RAM2_MEM_END (0x200407FFUL) /**< RAM2 end address */
+#define RAM2_MEM_BITS (0x0000000BUL) /**< RAM2 used bits */
+#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */
+#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */
+#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
+#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
+#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
+#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
+#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
+#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
+#define CRYPTO1_MEM_BASE (0x400F0400UL) /**< CRYPTO1 base address */
+#define CRYPTO1_MEM_SIZE (0x400UL) /**< CRYPTO1 available address space */
+#define CRYPTO1_MEM_END (0x400F07FFUL) /**< CRYPTO1 end address */
+#define CRYPTO1_MEM_BITS (0x0000000AUL) /**< CRYPTO1 used bits */
+#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */
+#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */
+#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */
+#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
+#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
+#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
+#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
+#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */
+#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */
+#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */
+#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */
+#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */
+#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */
+#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */
+#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define CRYPTO1_BITSET_MEM_BASE (0x460F0400UL) /**< CRYPTO1_BITSET base address */
+#define CRYPTO1_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO1_BITSET available address space */
+#define CRYPTO1_BITSET_MEM_END (0x460F07FFUL) /**< CRYPTO1_BITSET end address */
+#define CRYPTO1_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITSET used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x20000UL) /**< RAM available address space */
+#define RAM_MEM_END (0x2001FFFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x00000011UL) /**< RAM used bits */
+#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */
+#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */
+#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */
+#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */
+#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
+#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
+#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
+#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xF0000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460EFFFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xF0000UL) /**< PER available address space */
+#define PER_MEM_END (0x400EFFFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */
+#define RAM2_CODE_MEM_SIZE (0x800UL) /**< RAM2_CODE available address space */
+#define RAM2_CODE_MEM_END (0x100407FFUL) /**< RAM2_CODE end address */
+#define RAM2_CODE_MEM_BITS (0x0000000BUL) /**< RAM2_CODE used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xF0000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440EFFFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
/** Bit banding area */
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
/** Flash and SRAM limits for EFR32FG12P432F1024GM48 */
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */
-#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size (interleaving off) */
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
-#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */
/** AF channels connect the different on-chip peripherals with the af-mux */
-#define AFCHAN_MAX 136
-#define AFCHANLOC_MAX 32
+#define AFCHAN_MAX 136U
+/** AF channel maximum location number */
+#define AFCHANLOC_MAX 32U
/** Analog AF channels */
-#define AFACHAN_MAX 125
+#define AFACHAN_MAX 125U
/* Part number capabilities */
-#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
-#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */
-#define TIMER_PRESENT /**< TIMER is available in this part */
-#define TIMER_COUNT 2 /**< 2 TIMERs available */
-#define WTIMER_PRESENT /**< WTIMER is available in this part */
-#define WTIMER_COUNT 2 /**< 2 WTIMERs available */
-#define USART_PRESENT /**< USART is available in this part */
-#define USART_COUNT 4 /**< 4 USARTs available */
-#define LEUART_PRESENT /**< LEUART is available in this part */
-#define LEUART_COUNT 1 /**< 1 LEUARTs available */
-#define LETIMER_PRESENT /**< LETIMER is available in this part */
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
-#define PCNT_PRESENT /**< PCNT is available in this part */
-#define PCNT_COUNT 3 /**< 3 PCNTs available */
-#define I2C_PRESENT /**< I2C is available in this part */
-#define I2C_COUNT 2 /**< 2 I2Cs available */
-#define ADC_PRESENT /**< ADC is available in this part */
-#define ADC_COUNT 1 /**< 1 ADCs available */
-#define ACMP_PRESENT /**< ACMP is available in this part */
-#define ACMP_COUNT 2 /**< 2 ACMPs available */
-#define IDAC_PRESENT /**< IDAC is available in this part */
-#define IDAC_COUNT 1 /**< 1 IDACs available */
-#define VDAC_PRESENT /**< VDAC is available in this part */
-#define VDAC_COUNT 1 /**< 1 VDACs available */
-#define WDOG_PRESENT /**< WDOG is available in this part */
-#define WDOG_COUNT 2 /**< 2 WDOGs available */
-#define TRNG_PRESENT /**< TRNG is available in this part */
-#define TRNG_COUNT 1 /**< 1 TRNGs available */
-#define SYSTICK_PRESENT
-#define SYSTICK_COUNT 1
-#define MSC_PRESENT
-#define MSC_COUNT 1
-#define EMU_PRESENT
-#define EMU_COUNT 1
-#define RMU_PRESENT
-#define RMU_COUNT 1
-#define CMU_PRESENT
-#define CMU_COUNT 1
-#define GPIO_PRESENT
-#define GPIO_COUNT 1
-#define PRS_PRESENT
-#define PRS_COUNT 1
-#define LDMA_PRESENT
-#define LDMA_COUNT 1
-#define FPUEH_PRESENT
-#define FPUEH_COUNT 1
-#define GPCRC_PRESENT
-#define GPCRC_COUNT 1
-#define CRYOTIMER_PRESENT
-#define CRYOTIMER_COUNT 1
-#define CSEN_PRESENT
-#define CSEN_COUNT 1
-#define LESENSE_PRESENT
-#define LESENSE_COUNT 1
-#define RTCC_PRESENT
-#define RTCC_COUNT 1
-#define ETM_PRESENT
-#define ETM_COUNT 1
-#define BOOTLOADER_PRESENT
-#define BOOTLOADER_COUNT 1
-#define SMU_PRESENT
-#define SMU_COUNT 1
-
-#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
-#include "system_efr32fg12p.h" /* System Header File */
+#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
+#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */
+#define TIMER_PRESENT /**< TIMER is available in this part */
+#define TIMER_COUNT 2 /**< 2 TIMERs available */
+#define WTIMER_PRESENT /**< WTIMER is available in this part */
+#define WTIMER_COUNT 2 /**< 2 WTIMERs available */
+#define USART_PRESENT /**< USART is available in this part */
+#define USART_COUNT 4 /**< 4 USARTs available */
+#define LEUART_PRESENT /**< LEUART is available in this part */
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */
+#define LETIMER_PRESENT /**< LETIMER is available in this part */
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
+#define PCNT_PRESENT /**< PCNT is available in this part */
+#define PCNT_COUNT 3 /**< 3 PCNTs available */
+#define I2C_PRESENT /**< I2C is available in this part */
+#define I2C_COUNT 2 /**< 2 I2Cs available */
+#define ADC_PRESENT /**< ADC is available in this part */
+#define ADC_COUNT 1 /**< 1 ADCs available */
+#define ACMP_PRESENT /**< ACMP is available in this part */
+#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
+#define VDAC_PRESENT /**< VDAC is available in this part */
+#define VDAC_COUNT 1 /**< 1 VDACs available */
+#define WDOG_PRESENT /**< WDOG is available in this part */
+#define WDOG_COUNT 2 /**< 2 WDOGs available */
+#define TRNG_PRESENT /**< TRNG is available in this part */
+#define TRNG_COUNT 1 /**< 1 TRNGs available */
+#define MSC_PRESENT /**< MSC is available in this part */
+#define MSC_COUNT 1 /**< 1 MSC available */
+#define EMU_PRESENT /**< EMU is available in this part */
+#define EMU_COUNT 1 /**< 1 EMU available */
+#define RMU_PRESENT /**< RMU is available in this part */
+#define RMU_COUNT 1 /**< 1 RMU available */
+#define CMU_PRESENT /**< CMU is available in this part */
+#define CMU_COUNT 1 /**< 1 CMU available */
+#define GPIO_PRESENT /**< GPIO is available in this part */
+#define GPIO_COUNT 1 /**< 1 GPIO available */
+#define PRS_PRESENT /**< PRS is available in this part */
+#define PRS_COUNT 1 /**< 1 PRS available */
+#define LDMA_PRESENT /**< LDMA is available in this part */
+#define LDMA_COUNT 1 /**< 1 LDMA available */
+#define FPUEH_PRESENT /**< FPUEH is available in this part */
+#define FPUEH_COUNT 1 /**< 1 FPUEH available */
+#define GPCRC_PRESENT /**< GPCRC is available in this part */
+#define GPCRC_COUNT 1 /**< 1 GPCRC available */
+#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
+#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
+#define CSEN_PRESENT /**< CSEN is available in this part */
+#define CSEN_COUNT 1 /**< 1 CSEN available */
+#define LESENSE_PRESENT /**< LESENSE is available in this part */
+#define LESENSE_COUNT 1 /**< 1 LESENSE available */
+#define RTCC_PRESENT /**< RTCC is available in this part */
+#define RTCC_COUNT 1 /**< 1 RTCC available */
+#define ETM_PRESENT /**< ETM is available in this part */
+#define ETM_COUNT 1 /**< 1 ETM available */
+#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
+#define SMU_PRESENT /**< SMU is available in this part */
+#define SMU_COUNT 1 /**< 1 SMU available */
+#define DCDC_PRESENT /**< DCDC is available in this part */
+#define DCDC_COUNT 1 /**< 1 DCDC available */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32fg12p.h" /* System Header File */
/** @} End of group EFR32FG12P432F1024GM48_Part */
-/**************************************************************************//**
- * @defgroup EFR32FG12P432F1024GM48_Peripheral_TypeDefs EFR32FG12P432F1024GM48 Peripheral TypeDefs
+/***************************************************************************//**
+ * @defgroup EFR32FG12P432F1024GM48_Peripheral_TypeDefs Peripheral TypeDefs
* @{
* @brief Device Specific Peripheral Register Structures
- *****************************************************************************/
+ ******************************************************************************/
#include "efr32fg12p_msc.h"
#include "efr32fg12p_emu.h"
@@ -372,10 +386,10 @@ typedef enum IRQn
/** @} End of group EFR32FG12P432F1024GM48_Peripheral_TypeDefs */
-/**************************************************************************//**
- * @defgroup EFR32FG12P432F1024GM48_Peripheral_Base EFR32FG12P432F1024GM48 Peripheral Memory Map
+/***************************************************************************//**
+ * @defgroup EFR32FG12P432F1024GM48_Peripheral_Base Peripheral Memory Map
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC_BASE (0x400E0000UL) /**< MSC base address */
#define EMU_BASE (0x400E3000UL) /**< EMU base address */
@@ -425,10 +439,10 @@ typedef enum IRQn
/** @} End of group EFR32FG12P432F1024GM48_Peripheral_Base */
-/**************************************************************************//**
- * @defgroup EFR32FG12P432F1024GM48_Peripheral_Declaration EFR32FG12P432F1024GM48 Peripheral Declarations
+/***************************************************************************//**
+ * @defgroup EFR32FG12P432F1024GM48_Peripheral_Declaration Peripheral Declarations
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
@@ -476,10 +490,10 @@ typedef enum IRQn
/** @} End of group EFR32FG12P432F1024GM48_Peripheral_Declaration */
-/**************************************************************************//**
- * @defgroup EFR32FG12P432F1024GM48_Peripheral_Offsets EFR32FG12P432F1024GM48 Peripheral Offsets
+/***************************************************************************//**
+ * @defgroup EFR32FG12P432F1024GM48_Peripheral_Offsets Peripheral Offsets
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */
#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
@@ -498,19 +512,20 @@ typedef enum IRQn
/** @} End of group EFR32FG12P432F1024GM48_Peripheral_Offsets */
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P432F1024GM48_BitFields EFR32FG12P432F1024GM48 Bit Fields
+/***************************************************************************//**
+ * @defgroup EFR32FG12P432F1024GM48_BitFields Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
#include "efr32fg12p_prs_signals.h"
#include "efr32fg12p_dmareq.h"
-/**************************************************************************//**
- * @defgroup EFR32FG12P432F1024GM48_WTIMER_BitFields EFR32FG12P432F1024GM48_WTIMER Bit Fields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P432F1024GM48_WTIMER
+ * @{
+ * @defgroup EFR32FG12P432F1024GM48_WTIMER_BitFields WTIMER Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for WTIMER CTRL */
#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */
@@ -626,7 +641,7 @@ typedef enum IRQn
#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */
#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */
+#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */
#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */
#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */
#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
@@ -1011,13 +1026,13 @@ typedef enum IRQn
#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */
-#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */
+#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */
-#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */
+#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */
@@ -1731,7 +1746,7 @@ typedef enum IRQn
#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */
#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */
+#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */
#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */
#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */
#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
@@ -1998,33 +2013,23 @@ typedef enum IRQn
#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */
-#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */
+#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */
-#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */
+#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */
+/** @} */
/** @} End of group EFR32FG12P432F1024GM48_WTIMER */
-
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P432F1024GM48_SYSTICK_BitFields EFR32FG12P432F1024GM48_SYSTICK Bit Fields
- * @{
- *****************************************************************************/
-
-/** @} End of group EFR32FG12P432F1024GM48_SYSTICK */
-
-
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P432F1024GM48_UNLOCK EFR32FG12P432F1024GM48 Unlock Codes
+/***************************************************************************//**
+ * @defgroup EFR32FG12P432F1024GM48_UNLOCK Unlock Codes
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
@@ -2037,16 +2042,9 @@ typedef enum IRQn
/** @} End of group EFR32FG12P432F1024GM48_BitFields */
-/**************************************************************************//**
- * @defgroup EFR32FG12P432F1024GM48_Alternate_Function EFR32FG12P432F1024GM48 Alternate Function
- * @{
- *****************************************************************************/
-
#include "efr32fg12p_af_ports.h"
#include "efr32fg12p_af_pins.h"
-/** @} End of group EFR32FG12P432F1024GM48_Alternate_Function */
-
/** @} End of group EFR32FG12P432F1024GM48 */
/** @} End of group Parts */
@@ -2054,4 +2052,5 @@ typedef enum IRQn
#ifdef __cplusplus
}
#endif
+
#endif /* EFR32FG12P432F1024GM48_H */
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p433f1024gl125.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p433f1024gl125.h
similarity index 91%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p433f1024gl125.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p433f1024gl125.h
index e746b991..9115ee4e 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p433f1024gl125.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p433f1024gl125.h
@@ -1,35 +1,39 @@
-/**************************************************************************//**
- * @file efr32fg12p433f1024gl125.h
+/***************************************************************************//**
+ * @file
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
* for EFR32FG12P433F1024GL125
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
#ifndef EFR32FG12P433F1024GL125_H
#define EFR32FG12P433F1024GL125_H
@@ -38,111 +42,120 @@
extern "C" {
#endif
-/**************************************************************************//**
+/***************************************************************************//**
* @addtogroup Parts
* @{
- *****************************************************************************/
+ ******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFR32FG12P433F1024GL125 EFR32FG12P433F1024GL125
* @{
- *****************************************************************************/
+ ******************************************************************************/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
+typedef enum IRQn{
/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
- NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */
- HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */
- MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
/****** EFR32FG12P Peripheral Interrupt Numbers ********************************************/
- EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */
- WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */
- WDOG1_IRQn = 3, /*!< 3 EFR32 WDOG1 Interrupt */
- LDMA_IRQn = 9, /*!< 9 EFR32 LDMA Interrupt */
- GPIO_EVEN_IRQn = 10, /*!< 10 EFR32 GPIO_EVEN Interrupt */
- TIMER0_IRQn = 11, /*!< 11 EFR32 TIMER0 Interrupt */
- USART0_RX_IRQn = 12, /*!< 12 EFR32 USART0_RX Interrupt */
- USART0_TX_IRQn = 13, /*!< 13 EFR32 USART0_TX Interrupt */
- ACMP0_IRQn = 14, /*!< 14 EFR32 ACMP0 Interrupt */
- ADC0_IRQn = 15, /*!< 15 EFR32 ADC0 Interrupt */
- IDAC0_IRQn = 16, /*!< 16 EFR32 IDAC0 Interrupt */
- I2C0_IRQn = 17, /*!< 17 EFR32 I2C0 Interrupt */
- GPIO_ODD_IRQn = 18, /*!< 18 EFR32 GPIO_ODD Interrupt */
- TIMER1_IRQn = 19, /*!< 19 EFR32 TIMER1 Interrupt */
- USART1_RX_IRQn = 20, /*!< 20 EFR32 USART1_RX Interrupt */
- USART1_TX_IRQn = 21, /*!< 21 EFR32 USART1_TX Interrupt */
- LEUART0_IRQn = 22, /*!< 22 EFR32 LEUART0 Interrupt */
- PCNT0_IRQn = 23, /*!< 23 EFR32 PCNT0 Interrupt */
- CMU_IRQn = 24, /*!< 24 EFR32 CMU Interrupt */
- MSC_IRQn = 25, /*!< 25 EFR32 MSC Interrupt */
- CRYPTO0_IRQn = 26, /*!< 26 EFR32 CRYPTO0 Interrupt */
- LETIMER0_IRQn = 27, /*!< 27 EFR32 LETIMER0 Interrupt */
- RTCC_IRQn = 30, /*!< 30 EFR32 RTCC Interrupt */
- CRYOTIMER_IRQn = 32, /*!< 32 EFR32 CRYOTIMER Interrupt */
- FPUEH_IRQn = 34, /*!< 34 EFR32 FPUEH Interrupt */
- SMU_IRQn = 35, /*!< 35 EFR32 SMU Interrupt */
- WTIMER0_IRQn = 36, /*!< 36 EFR32 WTIMER0 Interrupt */
- WTIMER1_IRQn = 37, /*!< 37 EFR32 WTIMER1 Interrupt */
- PCNT1_IRQn = 38, /*!< 38 EFR32 PCNT1 Interrupt */
- PCNT2_IRQn = 39, /*!< 39 EFR32 PCNT2 Interrupt */
- USART2_RX_IRQn = 40, /*!< 40 EFR32 USART2_RX Interrupt */
- USART2_TX_IRQn = 41, /*!< 41 EFR32 USART2_TX Interrupt */
- I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */
- USART3_RX_IRQn = 43, /*!< 43 EFR32 USART3_RX Interrupt */
- USART3_TX_IRQn = 44, /*!< 44 EFR32 USART3_TX Interrupt */
- VDAC0_IRQn = 45, /*!< 45 EFR32 VDAC0 Interrupt */
- CSEN_IRQn = 46, /*!< 46 EFR32 CSEN Interrupt */
- LESENSE_IRQn = 47, /*!< 47 EFR32 LESENSE Interrupt */
- CRYPTO1_IRQn = 48, /*!< 48 EFR32 CRYPTO1 Interrupt */
- TRNG0_IRQn = 49, /*!< 49 EFR32 TRNG0 Interrupt */
+ EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
+ WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 3, /*!< 16+3 EFR32 WDOG1 Interrupt */
+ FRC_IRQn = 4, /*!< 16+4 EFR32 FRC Interrupt */
+ MODEM_IRQn = 5, /*!< 16+5 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 6, /*!< 16+6 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 7, /*!< 16+7 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 8, /*!< 16+8 EFR32 BUFC Interrupt */
+ LDMA_IRQn = 9, /*!< 16+9 EFR32 LDMA Interrupt */
+ GPIO_EVEN_IRQn = 10, /*!< 16+10 EFR32 GPIO_EVEN Interrupt */
+ TIMER0_IRQn = 11, /*!< 16+11 EFR32 TIMER0 Interrupt */
+ USART0_RX_IRQn = 12, /*!< 16+12 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 13, /*!< 16+13 EFR32 USART0_TX Interrupt */
+ ACMP0_IRQn = 14, /*!< 16+14 EFR32 ACMP0 Interrupt */
+ ADC0_IRQn = 15, /*!< 16+15 EFR32 ADC0 Interrupt */
+ IDAC0_IRQn = 16, /*!< 16+16 EFR32 IDAC0 Interrupt */
+ I2C0_IRQn = 17, /*!< 16+17 EFR32 I2C0 Interrupt */
+ GPIO_ODD_IRQn = 18, /*!< 16+18 EFR32 GPIO_ODD Interrupt */
+ TIMER1_IRQn = 19, /*!< 16+19 EFR32 TIMER1 Interrupt */
+ USART1_RX_IRQn = 20, /*!< 16+20 EFR32 USART1_RX Interrupt */
+ USART1_TX_IRQn = 21, /*!< 16+21 EFR32 USART1_TX Interrupt */
+ LEUART0_IRQn = 22, /*!< 16+22 EFR32 LEUART0 Interrupt */
+ PCNT0_IRQn = 23, /*!< 16+23 EFR32 PCNT0 Interrupt */
+ CMU_IRQn = 24, /*!< 16+24 EFR32 CMU Interrupt */
+ MSC_IRQn = 25, /*!< 16+25 EFR32 MSC Interrupt */
+ CRYPTO0_IRQn = 26, /*!< 16+26 EFR32 CRYPTO0 Interrupt */
+ LETIMER0_IRQn = 27, /*!< 16+27 EFR32 LETIMER0 Interrupt */
+ AGC_IRQn = 28, /*!< 16+28 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 29, /*!< 16+29 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 30, /*!< 16+30 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 31, /*!< 16+31 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 32, /*!< 16+32 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 33, /*!< 16+33 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 34, /*!< 16+34 EFR32 FPUEH Interrupt */
+ SMU_IRQn = 35, /*!< 16+35 EFR32 SMU Interrupt */
+ WTIMER0_IRQn = 36, /*!< 16+36 EFR32 WTIMER0 Interrupt */
+ WTIMER1_IRQn = 37, /*!< 16+37 EFR32 WTIMER1 Interrupt */
+ PCNT1_IRQn = 38, /*!< 16+38 EFR32 PCNT1 Interrupt */
+ PCNT2_IRQn = 39, /*!< 16+39 EFR32 PCNT2 Interrupt */
+ USART2_RX_IRQn = 40, /*!< 16+40 EFR32 USART2_RX Interrupt */
+ USART2_TX_IRQn = 41, /*!< 16+41 EFR32 USART2_TX Interrupt */
+ I2C1_IRQn = 42, /*!< 16+42 EFR32 I2C1 Interrupt */
+ USART3_RX_IRQn = 43, /*!< 16+43 EFR32 USART3_RX Interrupt */
+ USART3_TX_IRQn = 44, /*!< 16+44 EFR32 USART3_TX Interrupt */
+ VDAC0_IRQn = 45, /*!< 16+45 EFR32 VDAC0 Interrupt */
+ CSEN_IRQn = 46, /*!< 16+46 EFR32 CSEN Interrupt */
+ LESENSE_IRQn = 47, /*!< 16+47 EFR32 LESENSE Interrupt */
+ CRYPTO1_IRQn = 48, /*!< 16+48 EFR32 CRYPTO1 Interrupt */
+ TRNG0_IRQn = 49, /*!< 16+49 EFR32 TRNG0 Interrupt */
} IRQn_Type;
#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */
-/**************************************************************************//**
- * @defgroup EFR32FG12P433F1024GL125_Core EFR32FG12P433F1024GL125 Core
+/***************************************************************************//**
+ * @defgroup EFR32FG12P433F1024GL125_Core Core
* @{
* @brief Processor and Core Peripheral Section
- *****************************************************************************/
-#define __MPU_PRESENT 1 /**< Presence of MPU */
-#define __FPU_PRESENT 1 /**< Presence of FPU */
-#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
/** @} End of group EFR32FG12P433F1024GL125_Core */
-/**************************************************************************//**
-* @defgroup EFR32FG12P433F1024GL125_Part EFR32FG12P433F1024GL125 Part
-* @{
-******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P433F1024GL125_Part Part
+ * @{
+ ******************************************************************************/
/** Part family */
-#define _EFR32_FLEX_FAMILY 1 /**< FLEX Gecko RF SoC Family */
-#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
-#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
-#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */
-#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1
-#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2
-#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3
-#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_DUALBAND
-#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
-#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */
+#define _EFR32_FLEX_FAMILY 1 /**< FLEX Gecko RF SoC Family */
+#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
+#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_DUALBAND /**< Radio type */
+#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */
/* If part number is not defined as compiler option, define it */
#if !defined(EFR32FG12P433F1024GL125)
@@ -153,179 +166,180 @@ typedef enum IRQn
#define PART_NUMBER "EFR32FG12P433F1024GL125" /**< Part Number */
/** Memory Base addresses and limits */
-#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */
-#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */
-#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */
-#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */
-#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */
-#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */
-#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */
-#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */
-#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */
-#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */
-#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */
-#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */
-#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */
-#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */
-#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
-#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
-#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */
-#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */
-#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */
-#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */
-#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */
-#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */
-#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */
-#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */
-#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */
-#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */
-#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */
-#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
-#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
-#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */
-#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */
-#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */
-#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */
-#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */
-#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
-#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
-#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
-#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
-#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
-#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */
-#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */
-#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */
-#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */
-#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */
-#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */
-#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */
-#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
-#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
-#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
-#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
-#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */
-#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */
-#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
-#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
-#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
-#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
-#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
-#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
-#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
-#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */
-#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */
-#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */
-#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */
-#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */
-#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */
-#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */
-#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */
-#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */
-#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */
-#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
-#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */
-#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */
-#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */
+#define CRYPTO1_BITCLR_MEM_BASE (0x440F0400UL) /**< CRYPTO1_BITCLR base address */
+#define CRYPTO1_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO1_BITCLR available address space */
+#define CRYPTO1_BITCLR_MEM_END (0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
+#define CRYPTO1_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
+#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */
+#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */
+#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */
+#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */
+#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */
+#define RAM2_MEM_SIZE (0x800UL) /**< RAM2 available address space */
+#define RAM2_MEM_END (0x200407FFUL) /**< RAM2 end address */
+#define RAM2_MEM_BITS (0x0000000BUL) /**< RAM2 used bits */
+#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */
+#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */
+#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
+#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
+#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
+#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
+#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
+#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
+#define CRYPTO1_MEM_BASE (0x400F0400UL) /**< CRYPTO1 base address */
+#define CRYPTO1_MEM_SIZE (0x400UL) /**< CRYPTO1 available address space */
+#define CRYPTO1_MEM_END (0x400F07FFUL) /**< CRYPTO1 end address */
+#define CRYPTO1_MEM_BITS (0x0000000AUL) /**< CRYPTO1 used bits */
+#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */
+#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */
+#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */
+#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
+#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
+#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
+#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
+#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */
+#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */
+#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */
+#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */
+#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */
+#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */
+#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */
+#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define CRYPTO1_BITSET_MEM_BASE (0x460F0400UL) /**< CRYPTO1_BITSET base address */
+#define CRYPTO1_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO1_BITSET available address space */
+#define CRYPTO1_BITSET_MEM_END (0x460F07FFUL) /**< CRYPTO1_BITSET end address */
+#define CRYPTO1_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITSET used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x20000UL) /**< RAM available address space */
+#define RAM_MEM_END (0x2001FFFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x00000011UL) /**< RAM used bits */
+#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */
+#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */
+#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */
+#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */
+#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
+#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
+#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
+#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xF0000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460EFFFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xF0000UL) /**< PER available address space */
+#define PER_MEM_END (0x400EFFFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */
+#define RAM2_CODE_MEM_SIZE (0x800UL) /**< RAM2_CODE available address space */
+#define RAM2_CODE_MEM_END (0x100407FFUL) /**< RAM2_CODE end address */
+#define RAM2_CODE_MEM_BITS (0x0000000BUL) /**< RAM2_CODE used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xF0000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440EFFFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
/** Bit banding area */
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
/** Flash and SRAM limits for EFR32FG12P433F1024GL125 */
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */
-#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size (interleaving off) */
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
-#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */
/** AF channels connect the different on-chip peripherals with the af-mux */
-#define AFCHAN_MAX 136
-#define AFCHANLOC_MAX 32
+#define AFCHAN_MAX 136U
+/** AF channel maximum location number */
+#define AFCHANLOC_MAX 32U
/** Analog AF channels */
-#define AFACHAN_MAX 125
+#define AFACHAN_MAX 125U
/* Part number capabilities */
-#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
-#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */
-#define TIMER_PRESENT /**< TIMER is available in this part */
-#define TIMER_COUNT 2 /**< 2 TIMERs available */
-#define WTIMER_PRESENT /**< WTIMER is available in this part */
-#define WTIMER_COUNT 2 /**< 2 WTIMERs available */
-#define USART_PRESENT /**< USART is available in this part */
-#define USART_COUNT 4 /**< 4 USARTs available */
-#define LEUART_PRESENT /**< LEUART is available in this part */
-#define LEUART_COUNT 1 /**< 1 LEUARTs available */
-#define LETIMER_PRESENT /**< LETIMER is available in this part */
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
-#define PCNT_PRESENT /**< PCNT is available in this part */
-#define PCNT_COUNT 3 /**< 3 PCNTs available */
-#define I2C_PRESENT /**< I2C is available in this part */
-#define I2C_COUNT 2 /**< 2 I2Cs available */
-#define ADC_PRESENT /**< ADC is available in this part */
-#define ADC_COUNT 1 /**< 1 ADCs available */
-#define ACMP_PRESENT /**< ACMP is available in this part */
-#define ACMP_COUNT 2 /**< 2 ACMPs available */
-#define IDAC_PRESENT /**< IDAC is available in this part */
-#define IDAC_COUNT 1 /**< 1 IDACs available */
-#define VDAC_PRESENT /**< VDAC is available in this part */
-#define VDAC_COUNT 1 /**< 1 VDACs available */
-#define WDOG_PRESENT /**< WDOG is available in this part */
-#define WDOG_COUNT 2 /**< 2 WDOGs available */
-#define TRNG_PRESENT /**< TRNG is available in this part */
-#define TRNG_COUNT 1 /**< 1 TRNGs available */
-#define SYSTICK_PRESENT
-#define SYSTICK_COUNT 1
-#define MSC_PRESENT
-#define MSC_COUNT 1
-#define EMU_PRESENT
-#define EMU_COUNT 1
-#define RMU_PRESENT
-#define RMU_COUNT 1
-#define CMU_PRESENT
-#define CMU_COUNT 1
-#define GPIO_PRESENT
-#define GPIO_COUNT 1
-#define PRS_PRESENT
-#define PRS_COUNT 1
-#define LDMA_PRESENT
-#define LDMA_COUNT 1
-#define FPUEH_PRESENT
-#define FPUEH_COUNT 1
-#define GPCRC_PRESENT
-#define GPCRC_COUNT 1
-#define CRYOTIMER_PRESENT
-#define CRYOTIMER_COUNT 1
-#define CSEN_PRESENT
-#define CSEN_COUNT 1
-#define LESENSE_PRESENT
-#define LESENSE_COUNT 1
-#define RTCC_PRESENT
-#define RTCC_COUNT 1
-#define ETM_PRESENT
-#define ETM_COUNT 1
-#define BOOTLOADER_PRESENT
-#define BOOTLOADER_COUNT 1
-#define SMU_PRESENT
-#define SMU_COUNT 1
-
-#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
-#include "system_efr32fg12p.h" /* System Header File */
+#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
+#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */
+#define TIMER_PRESENT /**< TIMER is available in this part */
+#define TIMER_COUNT 2 /**< 2 TIMERs available */
+#define WTIMER_PRESENT /**< WTIMER is available in this part */
+#define WTIMER_COUNT 2 /**< 2 WTIMERs available */
+#define USART_PRESENT /**< USART is available in this part */
+#define USART_COUNT 4 /**< 4 USARTs available */
+#define LEUART_PRESENT /**< LEUART is available in this part */
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */
+#define LETIMER_PRESENT /**< LETIMER is available in this part */
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
+#define PCNT_PRESENT /**< PCNT is available in this part */
+#define PCNT_COUNT 3 /**< 3 PCNTs available */
+#define I2C_PRESENT /**< I2C is available in this part */
+#define I2C_COUNT 2 /**< 2 I2Cs available */
+#define ADC_PRESENT /**< ADC is available in this part */
+#define ADC_COUNT 1 /**< 1 ADCs available */
+#define ACMP_PRESENT /**< ACMP is available in this part */
+#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
+#define VDAC_PRESENT /**< VDAC is available in this part */
+#define VDAC_COUNT 1 /**< 1 VDACs available */
+#define WDOG_PRESENT /**< WDOG is available in this part */
+#define WDOG_COUNT 2 /**< 2 WDOGs available */
+#define TRNG_PRESENT /**< TRNG is available in this part */
+#define TRNG_COUNT 1 /**< 1 TRNGs available */
+#define MSC_PRESENT /**< MSC is available in this part */
+#define MSC_COUNT 1 /**< 1 MSC available */
+#define EMU_PRESENT /**< EMU is available in this part */
+#define EMU_COUNT 1 /**< 1 EMU available */
+#define RMU_PRESENT /**< RMU is available in this part */
+#define RMU_COUNT 1 /**< 1 RMU available */
+#define CMU_PRESENT /**< CMU is available in this part */
+#define CMU_COUNT 1 /**< 1 CMU available */
+#define GPIO_PRESENT /**< GPIO is available in this part */
+#define GPIO_COUNT 1 /**< 1 GPIO available */
+#define PRS_PRESENT /**< PRS is available in this part */
+#define PRS_COUNT 1 /**< 1 PRS available */
+#define LDMA_PRESENT /**< LDMA is available in this part */
+#define LDMA_COUNT 1 /**< 1 LDMA available */
+#define FPUEH_PRESENT /**< FPUEH is available in this part */
+#define FPUEH_COUNT 1 /**< 1 FPUEH available */
+#define GPCRC_PRESENT /**< GPCRC is available in this part */
+#define GPCRC_COUNT 1 /**< 1 GPCRC available */
+#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
+#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
+#define CSEN_PRESENT /**< CSEN is available in this part */
+#define CSEN_COUNT 1 /**< 1 CSEN available */
+#define LESENSE_PRESENT /**< LESENSE is available in this part */
+#define LESENSE_COUNT 1 /**< 1 LESENSE available */
+#define RTCC_PRESENT /**< RTCC is available in this part */
+#define RTCC_COUNT 1 /**< 1 RTCC available */
+#define ETM_PRESENT /**< ETM is available in this part */
+#define ETM_COUNT 1 /**< 1 ETM available */
+#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
+#define SMU_PRESENT /**< SMU is available in this part */
+#define SMU_COUNT 1 /**< 1 SMU available */
+#define DCDC_PRESENT /**< DCDC is available in this part */
+#define DCDC_COUNT 1 /**< 1 DCDC available */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32fg12p.h" /* System Header File */
/** @} End of group EFR32FG12P433F1024GL125_Part */
-/**************************************************************************//**
- * @defgroup EFR32FG12P433F1024GL125_Peripheral_TypeDefs EFR32FG12P433F1024GL125 Peripheral TypeDefs
+/***************************************************************************//**
+ * @defgroup EFR32FG12P433F1024GL125_Peripheral_TypeDefs Peripheral TypeDefs
* @{
* @brief Device Specific Peripheral Register Structures
- *****************************************************************************/
+ ******************************************************************************/
#include "efr32fg12p_msc.h"
#include "efr32fg12p_emu.h"
@@ -372,10 +386,10 @@ typedef enum IRQn
/** @} End of group EFR32FG12P433F1024GL125_Peripheral_TypeDefs */
-/**************************************************************************//**
- * @defgroup EFR32FG12P433F1024GL125_Peripheral_Base EFR32FG12P433F1024GL125 Peripheral Memory Map
+/***************************************************************************//**
+ * @defgroup EFR32FG12P433F1024GL125_Peripheral_Base Peripheral Memory Map
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC_BASE (0x400E0000UL) /**< MSC base address */
#define EMU_BASE (0x400E3000UL) /**< EMU base address */
@@ -425,10 +439,10 @@ typedef enum IRQn
/** @} End of group EFR32FG12P433F1024GL125_Peripheral_Base */
-/**************************************************************************//**
- * @defgroup EFR32FG12P433F1024GL125_Peripheral_Declaration EFR32FG12P433F1024GL125 Peripheral Declarations
+/***************************************************************************//**
+ * @defgroup EFR32FG12P433F1024GL125_Peripheral_Declaration Peripheral Declarations
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
@@ -476,10 +490,10 @@ typedef enum IRQn
/** @} End of group EFR32FG12P433F1024GL125_Peripheral_Declaration */
-/**************************************************************************//**
- * @defgroup EFR32FG12P433F1024GL125_Peripheral_Offsets EFR32FG12P433F1024GL125 Peripheral Offsets
+/***************************************************************************//**
+ * @defgroup EFR32FG12P433F1024GL125_Peripheral_Offsets Peripheral Offsets
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */
#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
@@ -498,19 +512,20 @@ typedef enum IRQn
/** @} End of group EFR32FG12P433F1024GL125_Peripheral_Offsets */
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P433F1024GL125_BitFields EFR32FG12P433F1024GL125 Bit Fields
+/***************************************************************************//**
+ * @defgroup EFR32FG12P433F1024GL125_BitFields Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
#include "efr32fg12p_prs_signals.h"
#include "efr32fg12p_dmareq.h"
-/**************************************************************************//**
- * @defgroup EFR32FG12P433F1024GL125_WTIMER_BitFields EFR32FG12P433F1024GL125_WTIMER Bit Fields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P433F1024GL125_WTIMER
+ * @{
+ * @defgroup EFR32FG12P433F1024GL125_WTIMER_BitFields WTIMER Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for WTIMER CTRL */
#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */
@@ -626,7 +641,7 @@ typedef enum IRQn
#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */
#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */
+#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */
#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */
#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */
#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
@@ -1011,13 +1026,13 @@ typedef enum IRQn
#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */
-#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */
+#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */
-#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */
+#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */
@@ -1731,7 +1746,7 @@ typedef enum IRQn
#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */
#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */
+#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */
#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */
#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */
#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
@@ -1998,33 +2013,23 @@ typedef enum IRQn
#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */
-#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */
+#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */
-#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */
+#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */
+/** @} */
/** @} End of group EFR32FG12P433F1024GL125_WTIMER */
-
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P433F1024GL125_SYSTICK_BitFields EFR32FG12P433F1024GL125_SYSTICK Bit Fields
- * @{
- *****************************************************************************/
-
-/** @} End of group EFR32FG12P433F1024GL125_SYSTICK */
-
-
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P433F1024GL125_UNLOCK EFR32FG12P433F1024GL125 Unlock Codes
+/***************************************************************************//**
+ * @defgroup EFR32FG12P433F1024GL125_UNLOCK Unlock Codes
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
@@ -2037,16 +2042,9 @@ typedef enum IRQn
/** @} End of group EFR32FG12P433F1024GL125_BitFields */
-/**************************************************************************//**
- * @defgroup EFR32FG12P433F1024GL125_Alternate_Function EFR32FG12P433F1024GL125 Alternate Function
- * @{
- *****************************************************************************/
-
#include "efr32fg12p_af_ports.h"
#include "efr32fg12p_af_pins.h"
-/** @} End of group EFR32FG12P433F1024GL125_Alternate_Function */
-
/** @} End of group EFR32FG12P433F1024GL125 */
/** @} End of group Parts */
@@ -2054,4 +2052,5 @@ typedef enum IRQn
#ifdef __cplusplus
}
#endif
+
#endif /* EFR32FG12P433F1024GL125_H */
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p433f1024gm48.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p433f1024gm48.h
similarity index 91%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p433f1024gm48.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p433f1024gm48.h
index a21ce6cc..caecd77c 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p433f1024gm48.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p433f1024gm48.h
@@ -1,35 +1,39 @@
-/**************************************************************************//**
- * @file efr32fg12p433f1024gm48.h
+/***************************************************************************//**
+ * @file
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
* for EFR32FG12P433F1024GM48
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
#ifndef EFR32FG12P433F1024GM48_H
#define EFR32FG12P433F1024GM48_H
@@ -38,111 +42,120 @@
extern "C" {
#endif
-/**************************************************************************//**
+/***************************************************************************//**
* @addtogroup Parts
* @{
- *****************************************************************************/
+ ******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
* @defgroup EFR32FG12P433F1024GM48 EFR32FG12P433F1024GM48
* @{
- *****************************************************************************/
+ ******************************************************************************/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
+typedef enum IRQn{
/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
- NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */
- HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */
- MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
/****** EFR32FG12P Peripheral Interrupt Numbers ********************************************/
- EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */
- WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */
- WDOG1_IRQn = 3, /*!< 3 EFR32 WDOG1 Interrupt */
- LDMA_IRQn = 9, /*!< 9 EFR32 LDMA Interrupt */
- GPIO_EVEN_IRQn = 10, /*!< 10 EFR32 GPIO_EVEN Interrupt */
- TIMER0_IRQn = 11, /*!< 11 EFR32 TIMER0 Interrupt */
- USART0_RX_IRQn = 12, /*!< 12 EFR32 USART0_RX Interrupt */
- USART0_TX_IRQn = 13, /*!< 13 EFR32 USART0_TX Interrupt */
- ACMP0_IRQn = 14, /*!< 14 EFR32 ACMP0 Interrupt */
- ADC0_IRQn = 15, /*!< 15 EFR32 ADC0 Interrupt */
- IDAC0_IRQn = 16, /*!< 16 EFR32 IDAC0 Interrupt */
- I2C0_IRQn = 17, /*!< 17 EFR32 I2C0 Interrupt */
- GPIO_ODD_IRQn = 18, /*!< 18 EFR32 GPIO_ODD Interrupt */
- TIMER1_IRQn = 19, /*!< 19 EFR32 TIMER1 Interrupt */
- USART1_RX_IRQn = 20, /*!< 20 EFR32 USART1_RX Interrupt */
- USART1_TX_IRQn = 21, /*!< 21 EFR32 USART1_TX Interrupt */
- LEUART0_IRQn = 22, /*!< 22 EFR32 LEUART0 Interrupt */
- PCNT0_IRQn = 23, /*!< 23 EFR32 PCNT0 Interrupt */
- CMU_IRQn = 24, /*!< 24 EFR32 CMU Interrupt */
- MSC_IRQn = 25, /*!< 25 EFR32 MSC Interrupt */
- CRYPTO0_IRQn = 26, /*!< 26 EFR32 CRYPTO0 Interrupt */
- LETIMER0_IRQn = 27, /*!< 27 EFR32 LETIMER0 Interrupt */
- RTCC_IRQn = 30, /*!< 30 EFR32 RTCC Interrupt */
- CRYOTIMER_IRQn = 32, /*!< 32 EFR32 CRYOTIMER Interrupt */
- FPUEH_IRQn = 34, /*!< 34 EFR32 FPUEH Interrupt */
- SMU_IRQn = 35, /*!< 35 EFR32 SMU Interrupt */
- WTIMER0_IRQn = 36, /*!< 36 EFR32 WTIMER0 Interrupt */
- WTIMER1_IRQn = 37, /*!< 37 EFR32 WTIMER1 Interrupt */
- PCNT1_IRQn = 38, /*!< 38 EFR32 PCNT1 Interrupt */
- PCNT2_IRQn = 39, /*!< 39 EFR32 PCNT2 Interrupt */
- USART2_RX_IRQn = 40, /*!< 40 EFR32 USART2_RX Interrupt */
- USART2_TX_IRQn = 41, /*!< 41 EFR32 USART2_TX Interrupt */
- I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */
- USART3_RX_IRQn = 43, /*!< 43 EFR32 USART3_RX Interrupt */
- USART3_TX_IRQn = 44, /*!< 44 EFR32 USART3_TX Interrupt */
- VDAC0_IRQn = 45, /*!< 45 EFR32 VDAC0 Interrupt */
- CSEN_IRQn = 46, /*!< 46 EFR32 CSEN Interrupt */
- LESENSE_IRQn = 47, /*!< 47 EFR32 LESENSE Interrupt */
- CRYPTO1_IRQn = 48, /*!< 48 EFR32 CRYPTO1 Interrupt */
- TRNG0_IRQn = 49, /*!< 49 EFR32 TRNG0 Interrupt */
+ EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
+ WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 3, /*!< 16+3 EFR32 WDOG1 Interrupt */
+ FRC_IRQn = 4, /*!< 16+4 EFR32 FRC Interrupt */
+ MODEM_IRQn = 5, /*!< 16+5 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 6, /*!< 16+6 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 7, /*!< 16+7 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 8, /*!< 16+8 EFR32 BUFC Interrupt */
+ LDMA_IRQn = 9, /*!< 16+9 EFR32 LDMA Interrupt */
+ GPIO_EVEN_IRQn = 10, /*!< 16+10 EFR32 GPIO_EVEN Interrupt */
+ TIMER0_IRQn = 11, /*!< 16+11 EFR32 TIMER0 Interrupt */
+ USART0_RX_IRQn = 12, /*!< 16+12 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 13, /*!< 16+13 EFR32 USART0_TX Interrupt */
+ ACMP0_IRQn = 14, /*!< 16+14 EFR32 ACMP0 Interrupt */
+ ADC0_IRQn = 15, /*!< 16+15 EFR32 ADC0 Interrupt */
+ IDAC0_IRQn = 16, /*!< 16+16 EFR32 IDAC0 Interrupt */
+ I2C0_IRQn = 17, /*!< 16+17 EFR32 I2C0 Interrupt */
+ GPIO_ODD_IRQn = 18, /*!< 16+18 EFR32 GPIO_ODD Interrupt */
+ TIMER1_IRQn = 19, /*!< 16+19 EFR32 TIMER1 Interrupt */
+ USART1_RX_IRQn = 20, /*!< 16+20 EFR32 USART1_RX Interrupt */
+ USART1_TX_IRQn = 21, /*!< 16+21 EFR32 USART1_TX Interrupt */
+ LEUART0_IRQn = 22, /*!< 16+22 EFR32 LEUART0 Interrupt */
+ PCNT0_IRQn = 23, /*!< 16+23 EFR32 PCNT0 Interrupt */
+ CMU_IRQn = 24, /*!< 16+24 EFR32 CMU Interrupt */
+ MSC_IRQn = 25, /*!< 16+25 EFR32 MSC Interrupt */
+ CRYPTO0_IRQn = 26, /*!< 16+26 EFR32 CRYPTO0 Interrupt */
+ LETIMER0_IRQn = 27, /*!< 16+27 EFR32 LETIMER0 Interrupt */
+ AGC_IRQn = 28, /*!< 16+28 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 29, /*!< 16+29 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 30, /*!< 16+30 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 31, /*!< 16+31 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 32, /*!< 16+32 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 33, /*!< 16+33 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 34, /*!< 16+34 EFR32 FPUEH Interrupt */
+ SMU_IRQn = 35, /*!< 16+35 EFR32 SMU Interrupt */
+ WTIMER0_IRQn = 36, /*!< 16+36 EFR32 WTIMER0 Interrupt */
+ WTIMER1_IRQn = 37, /*!< 16+37 EFR32 WTIMER1 Interrupt */
+ PCNT1_IRQn = 38, /*!< 16+38 EFR32 PCNT1 Interrupt */
+ PCNT2_IRQn = 39, /*!< 16+39 EFR32 PCNT2 Interrupt */
+ USART2_RX_IRQn = 40, /*!< 16+40 EFR32 USART2_RX Interrupt */
+ USART2_TX_IRQn = 41, /*!< 16+41 EFR32 USART2_TX Interrupt */
+ I2C1_IRQn = 42, /*!< 16+42 EFR32 I2C1 Interrupt */
+ USART3_RX_IRQn = 43, /*!< 16+43 EFR32 USART3_RX Interrupt */
+ USART3_TX_IRQn = 44, /*!< 16+44 EFR32 USART3_TX Interrupt */
+ VDAC0_IRQn = 45, /*!< 16+45 EFR32 VDAC0 Interrupt */
+ CSEN_IRQn = 46, /*!< 16+46 EFR32 CSEN Interrupt */
+ LESENSE_IRQn = 47, /*!< 16+47 EFR32 LESENSE Interrupt */
+ CRYPTO1_IRQn = 48, /*!< 16+48 EFR32 CRYPTO1 Interrupt */
+ TRNG0_IRQn = 49, /*!< 16+49 EFR32 TRNG0 Interrupt */
} IRQn_Type;
#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */
-/**************************************************************************//**
- * @defgroup EFR32FG12P433F1024GM48_Core EFR32FG12P433F1024GM48 Core
+/***************************************************************************//**
+ * @defgroup EFR32FG12P433F1024GM48_Core Core
* @{
* @brief Processor and Core Peripheral Section
- *****************************************************************************/
-#define __MPU_PRESENT 1 /**< Presence of MPU */
-#define __FPU_PRESENT 1 /**< Presence of FPU */
-#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
/** @} End of group EFR32FG12P433F1024GM48_Core */
-/**************************************************************************//**
-* @defgroup EFR32FG12P433F1024GM48_Part EFR32FG12P433F1024GM48 Part
-* @{
-******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P433F1024GM48_Part Part
+ * @{
+ ******************************************************************************/
/** Part family */
-#define _EFR32_FLEX_FAMILY 1 /**< FLEX Gecko RF SoC Family */
-#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
-#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
-#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */
-#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1
-#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2
-#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3
-#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_DUALBAND
-#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
-#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */
+#define _EFR32_FLEX_FAMILY 1 /**< FLEX Gecko RF SoC Family */
+#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
+#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_DUALBAND /**< Radio type */
+#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */
/* If part number is not defined as compiler option, define it */
#if !defined(EFR32FG12P433F1024GM48)
@@ -153,179 +166,180 @@ typedef enum IRQn
#define PART_NUMBER "EFR32FG12P433F1024GM48" /**< Part Number */
/** Memory Base addresses and limits */
-#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */
-#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */
-#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */
-#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */
-#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */
-#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */
-#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */
-#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */
-#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */
-#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */
-#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */
-#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */
-#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */
-#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */
-#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
-#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
-#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */
-#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */
-#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */
-#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */
-#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */
-#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */
-#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */
-#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */
-#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */
-#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */
-#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */
-#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
-#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
-#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */
-#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */
-#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */
-#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */
-#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */
-#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
-#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
-#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
-#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
-#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
-#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */
-#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */
-#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */
-#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */
-#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */
-#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */
-#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */
-#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
-#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
-#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
-#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
-#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */
-#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */
-#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
-#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
-#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
-#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
-#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
-#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
-#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
-#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */
-#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */
-#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */
-#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */
-#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */
-#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */
-#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */
-#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */
-#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */
-#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */
-#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
-#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */
-#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */
-#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */
+#define CRYPTO1_BITCLR_MEM_BASE (0x440F0400UL) /**< CRYPTO1_BITCLR base address */
+#define CRYPTO1_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO1_BITCLR available address space */
+#define CRYPTO1_BITCLR_MEM_END (0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
+#define CRYPTO1_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
+#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */
+#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */
+#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */
+#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */
+#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */
+#define RAM2_MEM_SIZE (0x800UL) /**< RAM2 available address space */
+#define RAM2_MEM_END (0x200407FFUL) /**< RAM2 end address */
+#define RAM2_MEM_BITS (0x0000000BUL) /**< RAM2 used bits */
+#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */
+#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */
+#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
+#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
+#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
+#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
+#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
+#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
+#define CRYPTO1_MEM_BASE (0x400F0400UL) /**< CRYPTO1 base address */
+#define CRYPTO1_MEM_SIZE (0x400UL) /**< CRYPTO1 available address space */
+#define CRYPTO1_MEM_END (0x400F07FFUL) /**< CRYPTO1 end address */
+#define CRYPTO1_MEM_BITS (0x0000000AUL) /**< CRYPTO1 used bits */
+#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */
+#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */
+#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */
+#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
+#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
+#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
+#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
+#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */
+#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */
+#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */
+#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */
+#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */
+#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */
+#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */
+#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define CRYPTO1_BITSET_MEM_BASE (0x460F0400UL) /**< CRYPTO1_BITSET base address */
+#define CRYPTO1_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO1_BITSET available address space */
+#define CRYPTO1_BITSET_MEM_END (0x460F07FFUL) /**< CRYPTO1_BITSET end address */
+#define CRYPTO1_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITSET used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x20000UL) /**< RAM available address space */
+#define RAM_MEM_END (0x2001FFFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x00000011UL) /**< RAM used bits */
+#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */
+#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */
+#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */
+#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */
+#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
+#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
+#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
+#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xF0000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460EFFFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xF0000UL) /**< PER available address space */
+#define PER_MEM_END (0x400EFFFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */
+#define RAM2_CODE_MEM_SIZE (0x800UL) /**< RAM2_CODE available address space */
+#define RAM2_CODE_MEM_END (0x100407FFUL) /**< RAM2_CODE end address */
+#define RAM2_CODE_MEM_BITS (0x0000000BUL) /**< RAM2_CODE used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xF0000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440EFFFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
/** Bit banding area */
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
/** Flash and SRAM limits for EFR32FG12P433F1024GM48 */
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */
-#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size (interleaving off) */
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
-#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */
/** AF channels connect the different on-chip peripherals with the af-mux */
-#define AFCHAN_MAX 136
-#define AFCHANLOC_MAX 32
+#define AFCHAN_MAX 136U
+/** AF channel maximum location number */
+#define AFCHANLOC_MAX 32U
/** Analog AF channels */
-#define AFACHAN_MAX 125
+#define AFACHAN_MAX 125U
/* Part number capabilities */
-#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
-#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */
-#define TIMER_PRESENT /**< TIMER is available in this part */
-#define TIMER_COUNT 2 /**< 2 TIMERs available */
-#define WTIMER_PRESENT /**< WTIMER is available in this part */
-#define WTIMER_COUNT 2 /**< 2 WTIMERs available */
-#define USART_PRESENT /**< USART is available in this part */
-#define USART_COUNT 4 /**< 4 USARTs available */
-#define LEUART_PRESENT /**< LEUART is available in this part */
-#define LEUART_COUNT 1 /**< 1 LEUARTs available */
-#define LETIMER_PRESENT /**< LETIMER is available in this part */
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
-#define PCNT_PRESENT /**< PCNT is available in this part */
-#define PCNT_COUNT 3 /**< 3 PCNTs available */
-#define I2C_PRESENT /**< I2C is available in this part */
-#define I2C_COUNT 2 /**< 2 I2Cs available */
-#define ADC_PRESENT /**< ADC is available in this part */
-#define ADC_COUNT 1 /**< 1 ADCs available */
-#define ACMP_PRESENT /**< ACMP is available in this part */
-#define ACMP_COUNT 2 /**< 2 ACMPs available */
-#define IDAC_PRESENT /**< IDAC is available in this part */
-#define IDAC_COUNT 1 /**< 1 IDACs available */
-#define VDAC_PRESENT /**< VDAC is available in this part */
-#define VDAC_COUNT 1 /**< 1 VDACs available */
-#define WDOG_PRESENT /**< WDOG is available in this part */
-#define WDOG_COUNT 2 /**< 2 WDOGs available */
-#define TRNG_PRESENT /**< TRNG is available in this part */
-#define TRNG_COUNT 1 /**< 1 TRNGs available */
-#define SYSTICK_PRESENT
-#define SYSTICK_COUNT 1
-#define MSC_PRESENT
-#define MSC_COUNT 1
-#define EMU_PRESENT
-#define EMU_COUNT 1
-#define RMU_PRESENT
-#define RMU_COUNT 1
-#define CMU_PRESENT
-#define CMU_COUNT 1
-#define GPIO_PRESENT
-#define GPIO_COUNT 1
-#define PRS_PRESENT
-#define PRS_COUNT 1
-#define LDMA_PRESENT
-#define LDMA_COUNT 1
-#define FPUEH_PRESENT
-#define FPUEH_COUNT 1
-#define GPCRC_PRESENT
-#define GPCRC_COUNT 1
-#define CRYOTIMER_PRESENT
-#define CRYOTIMER_COUNT 1
-#define CSEN_PRESENT
-#define CSEN_COUNT 1
-#define LESENSE_PRESENT
-#define LESENSE_COUNT 1
-#define RTCC_PRESENT
-#define RTCC_COUNT 1
-#define ETM_PRESENT
-#define ETM_COUNT 1
-#define BOOTLOADER_PRESENT
-#define BOOTLOADER_COUNT 1
-#define SMU_PRESENT
-#define SMU_COUNT 1
-
-#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
-#include "system_efr32fg12p.h" /* System Header File */
+#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
+#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */
+#define TIMER_PRESENT /**< TIMER is available in this part */
+#define TIMER_COUNT 2 /**< 2 TIMERs available */
+#define WTIMER_PRESENT /**< WTIMER is available in this part */
+#define WTIMER_COUNT 2 /**< 2 WTIMERs available */
+#define USART_PRESENT /**< USART is available in this part */
+#define USART_COUNT 4 /**< 4 USARTs available */
+#define LEUART_PRESENT /**< LEUART is available in this part */
+#define LEUART_COUNT 1 /**< 1 LEUARTs available */
+#define LETIMER_PRESENT /**< LETIMER is available in this part */
+#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
+#define PCNT_PRESENT /**< PCNT is available in this part */
+#define PCNT_COUNT 3 /**< 3 PCNTs available */
+#define I2C_PRESENT /**< I2C is available in this part */
+#define I2C_COUNT 2 /**< 2 I2Cs available */
+#define ADC_PRESENT /**< ADC is available in this part */
+#define ADC_COUNT 1 /**< 1 ADCs available */
+#define ACMP_PRESENT /**< ACMP is available in this part */
+#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
+#define VDAC_PRESENT /**< VDAC is available in this part */
+#define VDAC_COUNT 1 /**< 1 VDACs available */
+#define WDOG_PRESENT /**< WDOG is available in this part */
+#define WDOG_COUNT 2 /**< 2 WDOGs available */
+#define TRNG_PRESENT /**< TRNG is available in this part */
+#define TRNG_COUNT 1 /**< 1 TRNGs available */
+#define MSC_PRESENT /**< MSC is available in this part */
+#define MSC_COUNT 1 /**< 1 MSC available */
+#define EMU_PRESENT /**< EMU is available in this part */
+#define EMU_COUNT 1 /**< 1 EMU available */
+#define RMU_PRESENT /**< RMU is available in this part */
+#define RMU_COUNT 1 /**< 1 RMU available */
+#define CMU_PRESENT /**< CMU is available in this part */
+#define CMU_COUNT 1 /**< 1 CMU available */
+#define GPIO_PRESENT /**< GPIO is available in this part */
+#define GPIO_COUNT 1 /**< 1 GPIO available */
+#define PRS_PRESENT /**< PRS is available in this part */
+#define PRS_COUNT 1 /**< 1 PRS available */
+#define LDMA_PRESENT /**< LDMA is available in this part */
+#define LDMA_COUNT 1 /**< 1 LDMA available */
+#define FPUEH_PRESENT /**< FPUEH is available in this part */
+#define FPUEH_COUNT 1 /**< 1 FPUEH available */
+#define GPCRC_PRESENT /**< GPCRC is available in this part */
+#define GPCRC_COUNT 1 /**< 1 GPCRC available */
+#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
+#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
+#define CSEN_PRESENT /**< CSEN is available in this part */
+#define CSEN_COUNT 1 /**< 1 CSEN available */
+#define LESENSE_PRESENT /**< LESENSE is available in this part */
+#define LESENSE_COUNT 1 /**< 1 LESENSE available */
+#define RTCC_PRESENT /**< RTCC is available in this part */
+#define RTCC_COUNT 1 /**< 1 RTCC available */
+#define ETM_PRESENT /**< ETM is available in this part */
+#define ETM_COUNT 1 /**< 1 ETM available */
+#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
+#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
+#define SMU_PRESENT /**< SMU is available in this part */
+#define SMU_COUNT 1 /**< 1 SMU available */
+#define DCDC_PRESENT /**< DCDC is available in this part */
+#define DCDC_COUNT 1 /**< 1 DCDC available */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32fg12p.h" /* System Header File */
/** @} End of group EFR32FG12P433F1024GM48_Part */
-/**************************************************************************//**
- * @defgroup EFR32FG12P433F1024GM48_Peripheral_TypeDefs EFR32FG12P433F1024GM48 Peripheral TypeDefs
+/***************************************************************************//**
+ * @defgroup EFR32FG12P433F1024GM48_Peripheral_TypeDefs Peripheral TypeDefs
* @{
* @brief Device Specific Peripheral Register Structures
- *****************************************************************************/
+ ******************************************************************************/
#include "efr32fg12p_msc.h"
#include "efr32fg12p_emu.h"
@@ -372,10 +386,10 @@ typedef enum IRQn
/** @} End of group EFR32FG12P433F1024GM48_Peripheral_TypeDefs */
-/**************************************************************************//**
- * @defgroup EFR32FG12P433F1024GM48_Peripheral_Base EFR32FG12P433F1024GM48 Peripheral Memory Map
+/***************************************************************************//**
+ * @defgroup EFR32FG12P433F1024GM48_Peripheral_Base Peripheral Memory Map
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC_BASE (0x400E0000UL) /**< MSC base address */
#define EMU_BASE (0x400E3000UL) /**< EMU base address */
@@ -425,10 +439,10 @@ typedef enum IRQn
/** @} End of group EFR32FG12P433F1024GM48_Peripheral_Base */
-/**************************************************************************//**
- * @defgroup EFR32FG12P433F1024GM48_Peripheral_Declaration EFR32FG12P433F1024GM48 Peripheral Declarations
+/***************************************************************************//**
+ * @defgroup EFR32FG12P433F1024GM48_Peripheral_Declaration Peripheral Declarations
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
@@ -476,10 +490,10 @@ typedef enum IRQn
/** @} End of group EFR32FG12P433F1024GM48_Peripheral_Declaration */
-/**************************************************************************//**
- * @defgroup EFR32FG12P433F1024GM48_Peripheral_Offsets EFR32FG12P433F1024GM48 Peripheral Offsets
+/***************************************************************************//**
+ * @defgroup EFR32FG12P433F1024GM48_Peripheral_Offsets Peripheral Offsets
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */
#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
@@ -498,19 +512,20 @@ typedef enum IRQn
/** @} End of group EFR32FG12P433F1024GM48_Peripheral_Offsets */
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P433F1024GM48_BitFields EFR32FG12P433F1024GM48 Bit Fields
+/***************************************************************************//**
+ * @defgroup EFR32FG12P433F1024GM48_BitFields Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
#include "efr32fg12p_prs_signals.h"
#include "efr32fg12p_dmareq.h"
-/**************************************************************************//**
- * @defgroup EFR32FG12P433F1024GM48_WTIMER_BitFields EFR32FG12P433F1024GM48_WTIMER Bit Fields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P433F1024GM48_WTIMER
+ * @{
+ * @defgroup EFR32FG12P433F1024GM48_WTIMER_BitFields WTIMER Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for WTIMER CTRL */
#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */
@@ -626,7 +641,7 @@ typedef enum IRQn
#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */
#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */
+#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */
#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */
#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */
#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
@@ -1011,13 +1026,13 @@ typedef enum IRQn
#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */
-#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */
+#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */
-#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */
+#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */
@@ -1731,7 +1746,7 @@ typedef enum IRQn
#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */
#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */
+#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */
#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */
#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */
#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
@@ -1998,33 +2013,23 @@ typedef enum IRQn
#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */
-#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */
+#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */
-#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */
+#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */
+/** @} */
/** @} End of group EFR32FG12P433F1024GM48_WTIMER */
-
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P433F1024GM48_SYSTICK_BitFields EFR32FG12P433F1024GM48_SYSTICK Bit Fields
- * @{
- *****************************************************************************/
-
-/** @} End of group EFR32FG12P433F1024GM48_SYSTICK */
-
-
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P433F1024GM48_UNLOCK EFR32FG12P433F1024GM48 Unlock Codes
+/***************************************************************************//**
+ * @defgroup EFR32FG12P433F1024GM48_UNLOCK Unlock Codes
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
@@ -2037,16 +2042,9 @@ typedef enum IRQn
/** @} End of group EFR32FG12P433F1024GM48_BitFields */
-/**************************************************************************//**
- * @defgroup EFR32FG12P433F1024GM48_Alternate_Function EFR32FG12P433F1024GM48 Alternate Function
- * @{
- *****************************************************************************/
-
#include "efr32fg12p_af_ports.h"
#include "efr32fg12p_af_pins.h"
-/** @} End of group EFR32FG12P433F1024GM48_Alternate_Function */
-
/** @} End of group EFR32FG12P433F1024GM48 */
/** @} End of group Parts */
@@ -2054,4 +2052,5 @@ typedef enum IRQn
#ifdef __cplusplus
}
#endif
+
#endif /* EFR32FG12P433F1024GM48_H */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p233f512gm48.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p433f1024gm68.h
similarity index 92%
rename from mcu/efr/common/vendor/efr32fg13/efr32fg13p233f512gm48.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p433f1024gm68.h
index 25f10a4b..1cb95ad6 100644
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p233f512gm48.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p433f1024gm68.h
@@ -1,35 +1,33 @@
-/**************************************************************************//**
- * @file efr32fg13p233f512gm48.h
+/***************************************************************************//**
+ * @file
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
- * for EFR32FG13P233F512GM48
- * @version 5.4.0
- ******************************************************************************
+ * for EFR32FG12P433F1024GM68
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#if defined(__ICCARM__)
#pragma system_include /* Treat file as system include file. */
@@ -37,22 +35,22 @@
#pragma clang system_header /* Treat file as system include file. */
#endif
-#ifndef EFR32FG13P233F512GM48_H
-#define EFR32FG13P233F512GM48_H
+#ifndef EFR32FG12P433F1024GM68_H
+#define EFR32FG12P433F1024GM68_H
#ifdef __cplusplus
extern "C" {
#endif
-/**************************************************************************//**
+/***************************************************************************//**
* @addtogroup Parts
* @{
- *****************************************************************************/
+ ******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P233F512GM48 EFR32FG13P233F512GM48
+/***************************************************************************//**
+ * @defgroup EFR32FG12P433F1024GM68 EFR32FG12P433F1024GM68
* @{
- *****************************************************************************/
+ ******************************************************************************/
/** Interrupt Number Definition */
typedef enum IRQn{
@@ -67,11 +65,17 @@ typedef enum IRQn{
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
-/****** EFR32FG13P Peripheral Interrupt Numbers ********************************************/
+/****** EFR32FG12P Peripheral Interrupt Numbers ********************************************/
EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
+ FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */
WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
WDOG1_IRQn = 3, /*!< 16+3 EFR32 WDOG1 Interrupt */
+ FRC_IRQn = 4, /*!< 16+4 EFR32 FRC Interrupt */
+ MODEM_IRQn = 5, /*!< 16+5 EFR32 MODEM Interrupt */
+ RAC_SEQ_IRQn = 6, /*!< 16+6 EFR32 RAC_SEQ Interrupt */
+ RAC_RSM_IRQn = 7, /*!< 16+7 EFR32 RAC_RSM Interrupt */
+ BUFC_IRQn = 8, /*!< 16+8 EFR32 BUFC Interrupt */
LDMA_IRQn = 9, /*!< 16+9 EFR32 LDMA Interrupt */
GPIO_EVEN_IRQn = 10, /*!< 16+10 EFR32 GPIO_EVEN Interrupt */
TIMER0_IRQn = 11, /*!< 16+11 EFR32 TIMER0 Interrupt */
@@ -91,166 +95,175 @@ typedef enum IRQn{
MSC_IRQn = 25, /*!< 16+25 EFR32 MSC Interrupt */
CRYPTO0_IRQn = 26, /*!< 16+26 EFR32 CRYPTO0 Interrupt */
LETIMER0_IRQn = 27, /*!< 16+27 EFR32 LETIMER0 Interrupt */
- RTCC_IRQn = 31, /*!< 16+31 EFR32 RTCC Interrupt */
- CRYOTIMER_IRQn = 33, /*!< 16+33 EFR32 CRYOTIMER Interrupt */
- FPUEH_IRQn = 35, /*!< 16+35 EFR32 FPUEH Interrupt */
- SMU_IRQn = 36, /*!< 16+36 EFR32 SMU Interrupt */
- WTIMER0_IRQn = 37, /*!< 16+37 EFR32 WTIMER0 Interrupt */
- USART2_RX_IRQn = 38, /*!< 16+38 EFR32 USART2_RX Interrupt */
- USART2_TX_IRQn = 39, /*!< 16+39 EFR32 USART2_TX Interrupt */
- I2C1_IRQn = 40, /*!< 16+40 EFR32 I2C1 Interrupt */
- VDAC0_IRQn = 41, /*!< 16+41 EFR32 VDAC0 Interrupt */
- CSEN_IRQn = 42, /*!< 16+42 EFR32 CSEN Interrupt */
- LESENSE_IRQn = 43, /*!< 16+43 EFR32 LESENSE Interrupt */
- CRYPTO1_IRQn = 44, /*!< 16+44 EFR32 CRYPTO1 Interrupt */
- TRNG0_IRQn = 45, /*!< 16+45 EFR32 TRNG0 Interrupt */
+ AGC_IRQn = 28, /*!< 16+28 EFR32 AGC Interrupt */
+ PROTIMER_IRQn = 29, /*!< 16+29 EFR32 PROTIMER Interrupt */
+ RTCC_IRQn = 30, /*!< 16+30 EFR32 RTCC Interrupt */
+ SYNTH_IRQn = 31, /*!< 16+31 EFR32 SYNTH Interrupt */
+ CRYOTIMER_IRQn = 32, /*!< 16+32 EFR32 CRYOTIMER Interrupt */
+ RFSENSE_IRQn = 33, /*!< 16+33 EFR32 RFSENSE Interrupt */
+ FPUEH_IRQn = 34, /*!< 16+34 EFR32 FPUEH Interrupt */
+ SMU_IRQn = 35, /*!< 16+35 EFR32 SMU Interrupt */
+ WTIMER0_IRQn = 36, /*!< 16+36 EFR32 WTIMER0 Interrupt */
+ WTIMER1_IRQn = 37, /*!< 16+37 EFR32 WTIMER1 Interrupt */
+ PCNT1_IRQn = 38, /*!< 16+38 EFR32 PCNT1 Interrupt */
+ PCNT2_IRQn = 39, /*!< 16+39 EFR32 PCNT2 Interrupt */
+ USART2_RX_IRQn = 40, /*!< 16+40 EFR32 USART2_RX Interrupt */
+ USART2_TX_IRQn = 41, /*!< 16+41 EFR32 USART2_TX Interrupt */
+ I2C1_IRQn = 42, /*!< 16+42 EFR32 I2C1 Interrupt */
+ USART3_RX_IRQn = 43, /*!< 16+43 EFR32 USART3_RX Interrupt */
+ USART3_TX_IRQn = 44, /*!< 16+44 EFR32 USART3_TX Interrupt */
+ VDAC0_IRQn = 45, /*!< 16+45 EFR32 VDAC0 Interrupt */
+ CSEN_IRQn = 46, /*!< 16+46 EFR32 CSEN Interrupt */
+ LESENSE_IRQn = 47, /*!< 16+47 EFR32 LESENSE Interrupt */
+ CRYPTO1_IRQn = 48, /*!< 16+48 EFR32 CRYPTO1 Interrupt */
+ TRNG0_IRQn = 49, /*!< 16+49 EFR32 TRNG0 Interrupt */
} IRQn_Type;
#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */
-/**************************************************************************//**
- * @defgroup EFR32FG13P233F512GM48_Core Core
+/***************************************************************************//**
+ * @defgroup EFR32FG12P433F1024GM68_Core Core
* @{
* @brief Processor and Core Peripheral Section
- *****************************************************************************/
-#define __MPU_PRESENT 1 /**< Presence of MPU */
-#define __FPU_PRESENT 1 /**< Presence of FPU */
-#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
+ ******************************************************************************/
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
-/** @} End of group EFR32FG13P233F512GM48_Core */
+/** @} End of group EFR32FG12P433F1024GM68_Core */
-/**************************************************************************//**
-* @defgroup EFR32FG13P233F512GM48_Part Part
-* @{
-******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P433F1024GM68_Part Part
+ * @{
+ ******************************************************************************/
/** Part family */
#define _EFR32_FLEX_FAMILY 1 /**< FLEX Gecko RF SoC Family */
#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG_3 /**< Series 1, Configuration 3 */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG 3 /**< Series 1, Configuration 3 */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID 89 /**< Silicon Labs internal use only, may change any time */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID_89 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /**< Silicon Labs internal use only, may change any time */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /**< Silicon Labs internal use only, may change any time */
#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_DUALBAND /**< Radio type */
#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN_3 /**< @deprecated Platform 2, generation 3 */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN 3 /**< @deprecated Platform 2, generation 3 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */
+#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */
/* If part number is not defined as compiler option, define it */
-#if !defined(EFR32FG13P233F512GM48)
-#define EFR32FG13P233F512GM48 1 /**< FLEX Gecko Part */
+#if !defined(EFR32FG12P433F1024GM68)
+#define EFR32FG12P433F1024GM68 1 /**< FLEX Gecko Part */
#endif
/** Configure part number */
-#define PART_NUMBER "EFR32FG13P233F512GM48" /**< Part Number */
+#define PART_NUMBER "EFR32FG12P433F1024GM68" /**< Part Number */
/** Memory Base addresses and limits */
-#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */
-#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM0_CODE available address space */
-#define RAM0_CODE_MEM_END ((uint32_t) 0x10007FFFUL) /**< RAM0_CODE end address */
-#define RAM0_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM0_CODE used bits */
-#define RAM2_MEM_BASE ((uint32_t) 0x20010000UL) /**< RAM2 base address */
-#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */
-#define RAM2_MEM_END ((uint32_t) 0x200107FFUL) /**< RAM2 end address */
-#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */
-#define RAM1_MEM_BASE ((uint32_t) 0x20008000UL) /**< RAM1 base address */
-#define RAM1_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM1 available address space */
-#define RAM1_MEM_END ((uint32_t) 0x2000FFFFUL) /**< RAM1 end address */
-#define RAM1_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM1 used bits */
-#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */
-#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */
-#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
-#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
-#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */
-#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */
-#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */
-#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10008000UL) /**< RAM1_CODE base address */
-#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM1_CODE available address space */
-#define RAM1_CODE_MEM_END ((uint32_t) 0x1000FFFFUL) /**< RAM1_CODE end address */
-#define RAM1_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM1_CODE used bits */
-#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */
-#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */
-#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */
-#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */
-#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
-#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
-#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */
-#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */
-#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */
-#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */
-#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */
-#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
-#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
-#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
-#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
-#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
-#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */
-#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */
-#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */
-#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */
-#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */
-#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */
-#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */
-#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
-#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
-#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
-#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
-#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */
-#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */
-#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
-#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
-#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
-#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
-#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
-#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
-#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
-#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */
-#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */
-#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */
-#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */
-#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */
-#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */
-#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */
-#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10010000UL) /**< RAM2_CODE base address */
-#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */
-#define RAM2_CODE_MEM_END ((uint32_t) 0x100107FFUL) /**< RAM2_CODE end address */
-#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
-#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
-#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
-#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */
+#define CRYPTO1_BITCLR_MEM_BASE (0x440F0400UL) /**< CRYPTO1_BITCLR base address */
+#define CRYPTO1_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO1_BITCLR available address space */
+#define CRYPTO1_BITCLR_MEM_END (0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
+#define CRYPTO1_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
+#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */
+#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */
+#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */
+#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */
+#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */
+#define RAM2_MEM_SIZE (0x800UL) /**< RAM2 available address space */
+#define RAM2_MEM_END (0x200407FFUL) /**< RAM2 end address */
+#define RAM2_MEM_BITS (0x0000000BUL) /**< RAM2 used bits */
+#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */
+#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */
+#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
+#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
+#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
+#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
+#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
+#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
+#define CRYPTO1_MEM_BASE (0x400F0400UL) /**< CRYPTO1 base address */
+#define CRYPTO1_MEM_SIZE (0x400UL) /**< CRYPTO1 available address space */
+#define CRYPTO1_MEM_END (0x400F07FFUL) /**< CRYPTO1 end address */
+#define CRYPTO1_MEM_BITS (0x0000000AUL) /**< CRYPTO1 used bits */
+#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */
+#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */
+#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */
+#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */
+#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
+#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
+#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
+#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
+#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */
+#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */
+#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */
+#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */
+#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */
+#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */
+#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */
+#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */
+#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */
+#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */
+#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */
+#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */
+#define CRYPTO1_BITSET_MEM_BASE (0x460F0400UL) /**< CRYPTO1_BITSET base address */
+#define CRYPTO1_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO1_BITSET available address space */
+#define CRYPTO1_BITSET_MEM_END (0x460F07FFUL) /**< CRYPTO1_BITSET end address */
+#define CRYPTO1_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITSET used bits */
+#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */
+#define RAM_MEM_SIZE (0x20000UL) /**< RAM available address space */
+#define RAM_MEM_END (0x2001FFFFUL) /**< RAM end address */
+#define RAM_MEM_BITS (0x00000011UL) /**< RAM used bits */
+#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */
+#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */
+#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */
+#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */
+#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
+#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
+#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
+#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
+#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */
+#define PER_BITSET_MEM_SIZE (0xF0000UL) /**< PER_BITSET available address space */
+#define PER_BITSET_MEM_END (0x460EFFFFUL) /**< PER_BITSET end address */
+#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */
+#define PER_MEM_BASE (0x40000000UL) /**< PER base address */
+#define PER_MEM_SIZE (0xF0000UL) /**< PER available address space */
+#define PER_MEM_END (0x400EFFFFUL) /**< PER end address */
+#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */
+#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */
+#define RAM2_CODE_MEM_SIZE (0x800UL) /**< RAM2_CODE available address space */
+#define RAM2_CODE_MEM_END (0x100407FFUL) /**< RAM2_CODE end address */
+#define RAM2_CODE_MEM_BITS (0x0000000BUL) /**< RAM2_CODE used bits */
+#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */
+#define PER_BITCLR_MEM_SIZE (0xF0000UL) /**< PER_BITCLR available address space */
+#define PER_BITCLR_MEM_END (0x440EFFFFUL) /**< PER_BITCLR end address */
+#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */
/** Bit banding area */
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
+#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */
-/** Flash and SRAM limits for EFR32FG13P233F512GM48 */
+/** Flash and SRAM limits for EFR32FG12P433F1024GM68 */
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
-#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */
-#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
+#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size (interleaving off) */
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
-#define SRAM_SIZE (0x00010000UL) /**< Available SRAM Memory */
-#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
+#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
+#define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
-#define EXT_IRQ_COUNT 47 /**< Number of External (NVIC) interrupts */
+#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */
/** AF channels connect the different on-chip peripherals with the af-mux */
-#define AFCHAN_MAX 118U
+#define AFCHAN_MAX 136U
/** AF channel maximum location number */
#define AFCHANLOC_MAX 32U
/** Analog AF channels */
-#define AFACHAN_MAX 118U
+#define AFACHAN_MAX 125U
/* Part number capabilities */
@@ -259,27 +272,27 @@ typedef enum IRQn{
#define TIMER_PRESENT /**< TIMER is available in this part */
#define TIMER_COUNT 2 /**< 2 TIMERs available */
#define WTIMER_PRESENT /**< WTIMER is available in this part */
-#define WTIMER_COUNT 1 /**< 1 WTIMERs available */
+#define WTIMER_COUNT 2 /**< 2 WTIMERs available */
#define USART_PRESENT /**< USART is available in this part */
-#define USART_COUNT 3 /**< 3 USARTs available */
+#define USART_COUNT 4 /**< 4 USARTs available */
#define LEUART_PRESENT /**< LEUART is available in this part */
#define LEUART_COUNT 1 /**< 1 LEUARTs available */
#define LETIMER_PRESENT /**< LETIMER is available in this part */
#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
#define PCNT_PRESENT /**< PCNT is available in this part */
-#define PCNT_COUNT 1 /**< 1 PCNTs available */
+#define PCNT_COUNT 3 /**< 3 PCNTs available */
#define I2C_PRESENT /**< I2C is available in this part */
#define I2C_COUNT 2 /**< 2 I2Cs available */
#define ADC_PRESENT /**< ADC is available in this part */
#define ADC_COUNT 1 /**< 1 ADCs available */
#define ACMP_PRESENT /**< ACMP is available in this part */
#define ACMP_COUNT 2 /**< 2 ACMPs available */
+#define IDAC_PRESENT /**< IDAC is available in this part */
+#define IDAC_COUNT 1 /**< 1 IDACs available */
#define VDAC_PRESENT /**< VDAC is available in this part */
#define VDAC_COUNT 1 /**< 1 VDACs available */
#define WDOG_PRESENT /**< WDOG is available in this part */
#define WDOG_COUNT 2 /**< 2 WDOGs available */
-#define IDAC_PRESENT /**< IDAC is available in this part */
-#define IDAC_COUNT 1 /**< 1 IDACs available */
#define TRNG_PRESENT /**< TRNG is available in this part */
#define TRNG_COUNT 1 /**< 1 TRNGs available */
#define MSC_PRESENT /**< MSC is available in this part */
@@ -317,66 +330,66 @@ typedef enum IRQn{
#define DCDC_PRESENT /**< DCDC is available in this part */
#define DCDC_COUNT 1 /**< 1 DCDC available */
-#include "../../../efr32/cmsis/core_cm4.h" /* Cortex-M4 processor and core peripherals */
-#include "../../../efr32/vendor/efr32fg13/system_efr32fg13p.h" /* System Header File */
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_efr32fg12p.h" /* System Header File */
-/** @} End of group EFR32FG13P233F512GM48_Part */
+/** @} End of group EFR32FG12P433F1024GM68_Part */
-/**************************************************************************//**
- * @defgroup EFR32FG13P233F512GM48_Peripheral_TypeDefs Peripheral TypeDefs
+/***************************************************************************//**
+ * @defgroup EFR32FG12P433F1024GM68_Peripheral_TypeDefs Peripheral TypeDefs
* @{
* @brief Device Specific Peripheral Register Structures
- *****************************************************************************/
-
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_msc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_emu.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_rmu.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_cmu.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_crypto.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_gpio_p.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_gpio.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_prs_ch.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_prs.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_ldma_ch.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_ldma.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_fpueh.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_gpcrc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_timer_cc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_timer.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_usart.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_leuart.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_letimer.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_cryotimer.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_pcnt.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_i2c.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_adc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_acmp.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_vdac_opa.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_vdac.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_csen.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_lesense_st.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_lesense_buf.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_lesense_ch.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_lesense.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_rtcc_cc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_rtcc_ret.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_rtcc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_wdog_pch.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_wdog.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_etm.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_idac.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_smu.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_trng.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_dma_descriptor.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_devinfo.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_romtable.h"
-
-/** @} End of group EFR32FG13P233F512GM48_Peripheral_TypeDefs */
-
-/**************************************************************************//**
- * @defgroup EFR32FG13P233F512GM48_Peripheral_Base Peripheral Memory Map
+ ******************************************************************************/
+
+#include "efr32fg12p_msc.h"
+#include "efr32fg12p_emu.h"
+#include "efr32fg12p_rmu.h"
+#include "efr32fg12p_cmu.h"
+#include "efr32fg12p_crypto.h"
+#include "efr32fg12p_gpio_p.h"
+#include "efr32fg12p_gpio.h"
+#include "efr32fg12p_prs_ch.h"
+#include "efr32fg12p_prs.h"
+#include "efr32fg12p_ldma_ch.h"
+#include "efr32fg12p_ldma.h"
+#include "efr32fg12p_fpueh.h"
+#include "efr32fg12p_gpcrc.h"
+#include "efr32fg12p_timer_cc.h"
+#include "efr32fg12p_timer.h"
+#include "efr32fg12p_usart.h"
+#include "efr32fg12p_leuart.h"
+#include "efr32fg12p_letimer.h"
+#include "efr32fg12p_cryotimer.h"
+#include "efr32fg12p_pcnt.h"
+#include "efr32fg12p_i2c.h"
+#include "efr32fg12p_adc.h"
+#include "efr32fg12p_acmp.h"
+#include "efr32fg12p_idac.h"
+#include "efr32fg12p_vdac_opa.h"
+#include "efr32fg12p_vdac.h"
+#include "efr32fg12p_csen.h"
+#include "efr32fg12p_lesense_st.h"
+#include "efr32fg12p_lesense_buf.h"
+#include "efr32fg12p_lesense_ch.h"
+#include "efr32fg12p_lesense.h"
+#include "efr32fg12p_rtcc_cc.h"
+#include "efr32fg12p_rtcc_ret.h"
+#include "efr32fg12p_rtcc.h"
+#include "efr32fg12p_wdog_pch.h"
+#include "efr32fg12p_wdog.h"
+#include "efr32fg12p_etm.h"
+#include "efr32fg12p_smu.h"
+#include "efr32fg12p_trng.h"
+#include "efr32fg12p_dma_descriptor.h"
+#include "efr32fg12p_devinfo.h"
+#include "efr32fg12p_romtable.h"
+
+/** @} End of group EFR32FG12P433F1024GM68_Peripheral_TypeDefs */
+
+/***************************************************************************//**
+ * @defgroup EFR32FG12P433F1024GM68_Peripheral_Base Peripheral Memory Map
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC_BASE (0x400E0000UL) /**< MSC base address */
#define EMU_BASE (0x400E3000UL) /**< EMU base address */
@@ -393,18 +406,23 @@ typedef enum IRQn{
#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */
+#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */
#define USART0_BASE (0x40010000UL) /**< USART0 base address */
#define USART1_BASE (0x40010400UL) /**< USART1 base address */
#define USART2_BASE (0x40010800UL) /**< USART2 base address */
+#define USART3_BASE (0x40010C00UL) /**< USART3 base address */
#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
+#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */
+#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */
#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */
#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
+#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */
#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */
#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */
@@ -412,7 +430,6 @@ typedef enum IRQn{
#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */
#define ETM_BASE (0xE0041000UL) /**< ETM base address */
-#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
#define SMU_BASE (0x40022000UL) /**< SMU base address */
#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */
#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
@@ -420,12 +437,12 @@ typedef enum IRQn{
#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
-/** @} End of group EFR32FG13P233F512GM48_Peripheral_Base */
+/** @} End of group EFR32FG12P433F1024GM68_Peripheral_Base */
-/**************************************************************************//**
- * @defgroup EFR32FG13P233F512GM48_Peripheral_Declaration Peripheral Declarations
+/***************************************************************************//**
+ * @defgroup EFR32FG12P433F1024GM68_Peripheral_Declaration Peripheral Declarations
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
@@ -442,18 +459,23 @@ typedef enum IRQn{
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */
+#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
+#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
+#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
+#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
+#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */
#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */
#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
@@ -461,18 +483,17 @@ typedef enum IRQn{
#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */
#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
-#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */
#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
-/** @} End of group EFR32FG13P233F512GM48_Peripheral_Declaration */
+/** @} End of group EFR32FG12P433F1024GM68_Peripheral_Declaration */
-/**************************************************************************//**
- * @defgroup EFR32FG13P233F512GM48_Peripheral_Offsets Peripheral Offsets
+/***************************************************************************//**
+ * @defgroup EFR32FG12P433F1024GM68_Peripheral_Offsets Peripheral Offsets
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */
#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
@@ -484,31 +505,31 @@ typedef enum IRQn{
#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
+#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */
#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
-#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */
-/** @} End of group EFR32FG13P233F512GM48_Peripheral_Offsets */
+/** @} End of group EFR32FG12P433F1024GM68_Peripheral_Offsets */
-/**************************************************************************//**
- * @defgroup EFR32FG13P233F512GM48_BitFields Bit Fields
+/***************************************************************************//**
+ * @defgroup EFR32FG12P433F1024GM68_BitFields Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_prs_signals.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_dmareq.h"
+#include "efr32fg12p_prs_signals.h"
+#include "efr32fg12p_dmareq.h"
-/**************************************************************************//**
- * @addtogroup EFR32FG13P233F512GM48_WTIMER
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P433F1024GM68_WTIMER
* @{
- * @defgroup EFR32FG13P233F512GM48_WTIMER_BitFields WTIMER Bit Fields
+ * @defgroup EFR32FG12P433F1024GM68_WTIMER_BitFields WTIMER Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for WTIMER CTRL */
#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */
-#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */
+#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */
#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
@@ -579,11 +600,6 @@ typedef enum IRQn{
#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */
#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */
-#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */
-#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */
-#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */
#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */
#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */
#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
@@ -1010,13 +1026,13 @@ typedef enum IRQn{
#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */
#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */
-#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */
+#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */
#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */
-#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */
+#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */
#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */
@@ -1997,23 +2013,23 @@ typedef enum IRQn{
#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */
-#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */
+#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */
#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */
-#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */
+#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */
#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */
/** @} */
-/** @} End of group EFR32FG13P233F512GM48_WTIMER */
+/** @} End of group EFR32FG12P433F1024GM68_WTIMER */
-/**************************************************************************//**
- * @defgroup EFR32FG13P233F512GM48_UNLOCK Unlock Codes
+/***************************************************************************//**
+ * @defgroup EFR32FG12P433F1024GM68_UNLOCK Unlock Codes
* @{
- *****************************************************************************/
+ ******************************************************************************/
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
@@ -2022,18 +2038,19 @@ typedef enum IRQn{
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
-/** @} End of group EFR32FG13P233F512GM48_UNLOCK */
+/** @} End of group EFR32FG12P433F1024GM68_UNLOCK */
-/** @} End of group EFR32FG13P233F512GM48_BitFields */
+/** @} End of group EFR32FG12P433F1024GM68_BitFields */
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_af_ports.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_af_pins.h"
+#include "efr32fg12p_af_ports.h"
+#include "efr32fg12p_af_pins.h"
-/** @} End of group EFR32FG13P233F512GM48 */
+/** @} End of group EFR32FG12P433F1024GM68 */
/** @} End of group Parts */
#ifdef __cplusplus
}
#endif
-#endif /* EFR32FG13P233F512GM48_H */
+
+#endif /* EFR32FG12P433F1024GM68_H */
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_acmp.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_acmp.h
similarity index 97%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_acmp.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_acmp.h
index bfda8eee..73186ea0 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_acmp.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_acmp.h
@@ -1,45 +1,50 @@
-/**************************************************************************//**
- * @file efr32fg12p_acmp.h
+/***************************************************************************//**
+ * @file
* @brief EFR32FG12P_ACMP register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_ACMP
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P_ACMP ACMP
* @{
* @brief EFR32FG12P_ACMP Register Declaration
- *****************************************************************************/
-typedef struct
-{
+ ******************************************************************************/
+/** ACMP Register Declaration */
+typedef struct {
__IOM uint32_t CTRL; /**< Control Register */
__IOM uint32_t INPUTSEL; /**< Input Selection Register */
__IM uint32_t STATUS; /**< Status Register */
@@ -47,22 +52,24 @@ typedef struct
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
__IOM uint32_t IEN; /**< Interrupt Enable Register */
- uint32_t RESERVED0[1]; /**< Reserved for future use **/
+ uint32_t RESERVED0[1U]; /**< Reserved for future use **/
__IM uint32_t APORTREQ; /**< APORT Request Status Register */
__IM uint32_t APORTCONFLICT; /**< APORT Conflict Status Register */
__IOM uint32_t HYSTERESIS0; /**< Hysteresis 0 Register */
__IOM uint32_t HYSTERESIS1; /**< Hysteresis 1 Register */
- uint32_t RESERVED1[4]; /**< Reserved for future use **/
+ uint32_t RESERVED1[4U]; /**< Reserved for future use **/
__IOM uint32_t ROUTEPEN; /**< I/O Routing Pine Enable Register */
__IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
- __IOM uint32_t EXTIFCTRL; /**< External override interface control */
+ __IOM uint32_t EXTIFCTRL; /**< External Override Interface Control */
} ACMP_TypeDef; /** @} */
-/**************************************************************************//**
- * @defgroup EFR32FG12P_ACMP_BitFields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_ACMP
+ * @{
+ * @defgroup EFR32FG12P_ACMP_BitFields ACMP Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for ACMP CTRL */
#define _ACMP_CTRL_RESETVALUE 0x07000000UL /**< Default value for ACMP_CTRL */
@@ -100,7 +107,7 @@ typedef struct
#define _ACMP_CTRL_APORTYMASTERDIS_MASK 0x200UL /**< Bit mask for ACMP_APORTYMASTERDIS */
#define _ACMP_CTRL_APORTYMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_APORTYMASTERDIS_DEFAULT (_ACMP_CTRL_APORTYMASTERDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for ACMP_CTRL */
-#define ACMP_CTRL_APORTVMASTERDIS (0x1UL << 10) /**< APORT Bus Master Disable for Bus selected by VASEL */
+#define ACMP_CTRL_APORTVMASTERDIS (0x1UL << 10) /**< APORT Bus Master Disable for Bus Selected By VASEL */
#define _ACMP_CTRL_APORTVMASTERDIS_SHIFT 10 /**< Shift value for ACMP_APORTVMASTERDIS */
#define _ACMP_CTRL_APORTVMASTERDIS_MASK 0x400UL /**< Bit mask for ACMP_APORTVMASTERDIS */
#define _ACMP_CTRL_APORTVMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
@@ -109,15 +116,15 @@ typedef struct
#define _ACMP_CTRL_PWRSEL_MASK 0x7000UL /**< Bit mask for ACMP_PWRSEL */
#define _ACMP_CTRL_PWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
#define _ACMP_CTRL_PWRSEL_AVDD 0x00000000UL /**< Mode AVDD for ACMP_CTRL */
-#define _ACMP_CTRL_PWRSEL_VREGVDD 0x00000001UL /**< Mode VREGVDD for ACMP_CTRL */
+#define _ACMP_CTRL_PWRSEL_DVDD 0x00000001UL /**< Mode DVDD for ACMP_CTRL */
#define _ACMP_CTRL_PWRSEL_IOVDD0 0x00000002UL /**< Mode IOVDD0 for ACMP_CTRL */
#define _ACMP_CTRL_PWRSEL_IOVDD1 0x00000004UL /**< Mode IOVDD1 for ACMP_CTRL */
#define ACMP_CTRL_PWRSEL_DEFAULT (_ACMP_CTRL_PWRSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_PWRSEL_AVDD (_ACMP_CTRL_PWRSEL_AVDD << 12) /**< Shifted mode AVDD for ACMP_CTRL */
-#define ACMP_CTRL_PWRSEL_VREGVDD (_ACMP_CTRL_PWRSEL_VREGVDD << 12) /**< Shifted mode VREGVDD for ACMP_CTRL */
+#define ACMP_CTRL_PWRSEL_DVDD (_ACMP_CTRL_PWRSEL_DVDD << 12) /**< Shifted mode DVDD for ACMP_CTRL */
#define ACMP_CTRL_PWRSEL_IOVDD0 (_ACMP_CTRL_PWRSEL_IOVDD0 << 12) /**< Shifted mode IOVDD0 for ACMP_CTRL */
#define ACMP_CTRL_PWRSEL_IOVDD1 (_ACMP_CTRL_PWRSEL_IOVDD1 << 12) /**< Shifted mode IOVDD1 for ACMP_CTRL */
-#define ACMP_CTRL_ACCURACY (0x1UL << 15) /**< ACMP accuracy mode */
+#define ACMP_CTRL_ACCURACY (0x1UL << 15) /**< ACMP Accuracy Mode */
#define _ACMP_CTRL_ACCURACY_SHIFT 15 /**< Shift value for ACMP_ACCURACY */
#define _ACMP_CTRL_ACCURACY_MASK 0x8000UL /**< Bit mask for ACMP_ACCURACY */
#define _ACMP_CTRL_ACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
@@ -312,6 +319,8 @@ typedef struct
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_POSSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ACMP_INPUTSEL */
@@ -327,8 +336,6 @@ typedef struct
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_DACOUT0 0x000000F2UL /**< Mode DACOUT0 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_DACOUT1 0x000000F3UL /**< Mode DACOUT1 for ACMP_INPUTSEL */
@@ -480,6 +487,8 @@ typedef struct
#define ACMP_INPUTSEL_POSSEL_APORT4XCH11 (_ACMP_INPUTSEL_POSSEL_APORT4XCH11 << 0) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4YCH12 (_ACMP_INPUTSEL_POSSEL_APORT4YCH12 << 0) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4XCH13 (_ACMP_INPUTSEL_POSSEL_APORT4XCH13 << 0) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4YCH14 (_ACMP_INPUTSEL_POSSEL_APORT4YCH14 << 0) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_POSSEL_APORT4XCH15 (_ACMP_INPUTSEL_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4YCH16 (_ACMP_INPUTSEL_POSSEL_APORT4YCH16 << 0) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4XCH17 (_ACMP_INPUTSEL_POSSEL_APORT4XCH17 << 0) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4YCH18 (_ACMP_INPUTSEL_POSSEL_APORT4YCH18 << 0) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */
@@ -495,8 +504,6 @@ typedef struct
#define ACMP_INPUTSEL_POSSEL_APORT4YCH28 (_ACMP_INPUTSEL_POSSEL_APORT4YCH28 << 0) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4XCH29 (_ACMP_INPUTSEL_POSSEL_APORT4XCH29 << 0) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4YCH30 (_ACMP_INPUTSEL_POSSEL_APORT4YCH30 << 0) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4YCH14 (_ACMP_INPUTSEL_POSSEL_APORT4YCH14 << 0) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4XCH15 (_ACMP_INPUTSEL_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_APORT4XCH31 (_ACMP_INPUTSEL_POSSEL_APORT4XCH31 << 0) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_DACOUT0 (_ACMP_INPUTSEL_POSSEL_DACOUT0 << 0) /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_DACOUT1 (_ACMP_INPUTSEL_POSSEL_DACOUT1 << 0) /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */
@@ -650,6 +657,8 @@ typedef struct
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */
+#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ACMP_INPUTSEL */
@@ -665,8 +674,6 @@ typedef struct
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_DACOUT0 0x000000F2UL /**< Mode DACOUT0 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_DACOUT1 0x000000F3UL /**< Mode DACOUT1 for ACMP_INPUTSEL */
@@ -818,6 +825,8 @@ typedef struct
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH11 << 8) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH13 << 8) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */
+#define ACMP_INPUTSEL_NEGSEL_APORT4XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH16 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH17 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH17 << 8) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH18 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */
@@ -833,8 +842,6 @@ typedef struct
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH28 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH29 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH29 << 8) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4YCH30 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_APORT4XCH31 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_DACOUT0 (_ACMP_INPUTSEL_NEGSEL_DACOUT0 << 8) /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_DACOUT1 (_ACMP_INPUTSEL_NEGSEL_DACOUT1 << 8) /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */
@@ -1007,7 +1014,7 @@ typedef struct
#define _ACMP_STATUS_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */
#define _ACMP_STATUS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */
#define ACMP_STATUS_APORTCONFLICT_DEFAULT (_ACMP_STATUS_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_STATUS */
-#define ACMP_STATUS_EXTIFACT (0x1UL << 3) /**< External override interface active. */
+#define ACMP_STATUS_EXTIFACT (0x1UL << 3) /**< External Override Interface Active */
#define _ACMP_STATUS_EXTIFACT_SHIFT 3 /**< Shift value for ACMP_EXTIFACT */
#define _ACMP_STATUS_EXTIFACT_MASK 0x8UL /**< Bit mask for ACMP_EXTIFACT */
#define _ACMP_STATUS_EXTIFACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */
@@ -1092,52 +1099,52 @@ typedef struct
/* Bit fields for ACMP APORTREQ */
#define _ACMP_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for ACMP_APORTREQ */
#define _ACMP_APORTREQ_MASK 0x000003FFUL /**< Mask for ACMP_APORTREQ */
-#define ACMP_APORTREQ_APORT0XREQ (0x1UL << 0) /**< 1 if the bus connected to APORT0X is requested */
+#define ACMP_APORTREQ_APORT0XREQ (0x1UL << 0) /**< 1 If the Bus Connected to APORT0X is Requested */
#define _ACMP_APORTREQ_APORT0XREQ_SHIFT 0 /**< Shift value for ACMP_APORT0XREQ */
#define _ACMP_APORTREQ_APORT0XREQ_MASK 0x1UL /**< Bit mask for ACMP_APORT0XREQ */
#define _ACMP_APORTREQ_APORT0XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
#define ACMP_APORTREQ_APORT0XREQ_DEFAULT (_ACMP_APORTREQ_APORT0XREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
-#define ACMP_APORTREQ_APORT0YREQ (0x1UL << 1) /**< 1 if the bus connected to APORT0Y is requested */
+#define ACMP_APORTREQ_APORT0YREQ (0x1UL << 1) /**< 1 If the Bus Connected to APORT0Y is Requested */
#define _ACMP_APORTREQ_APORT0YREQ_SHIFT 1 /**< Shift value for ACMP_APORT0YREQ */
#define _ACMP_APORTREQ_APORT0YREQ_MASK 0x2UL /**< Bit mask for ACMP_APORT0YREQ */
#define _ACMP_APORTREQ_APORT0YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
#define ACMP_APORTREQ_APORT0YREQ_DEFAULT (_ACMP_APORTREQ_APORT0YREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
-#define ACMP_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the bus connected to APORT2X is requested */
+#define ACMP_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 If the Bus Connected to APORT2X is Requested */
#define _ACMP_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for ACMP_APORT1XREQ */
#define _ACMP_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for ACMP_APORT1XREQ */
#define _ACMP_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
#define ACMP_APORTREQ_APORT1XREQ_DEFAULT (_ACMP_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
-#define ACMP_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1X is requested */
+#define ACMP_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 If the Bus Connected to APORT1X is Requested */
#define _ACMP_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for ACMP_APORT1YREQ */
#define _ACMP_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for ACMP_APORT1YREQ */
#define _ACMP_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
#define ACMP_APORTREQ_APORT1YREQ_DEFAULT (_ACMP_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
-#define ACMP_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 if the bus connected to APORT2X is requested */
+#define ACMP_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is Requested */
#define _ACMP_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for ACMP_APORT2XREQ */
#define _ACMP_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for ACMP_APORT2XREQ */
#define _ACMP_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
#define ACMP_APORTREQ_APORT2XREQ_DEFAULT (_ACMP_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
-#define ACMP_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is requested */
+#define ACMP_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is Requested */
#define _ACMP_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for ACMP_APORT2YREQ */
#define _ACMP_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for ACMP_APORT2YREQ */
#define _ACMP_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
#define ACMP_APORTREQ_APORT2YREQ_DEFAULT (_ACMP_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
-#define ACMP_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 if the bus connected to APORT3X is requested */
+#define ACMP_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is Requested */
#define _ACMP_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for ACMP_APORT3XREQ */
#define _ACMP_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for ACMP_APORT3XREQ */
#define _ACMP_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
#define ACMP_APORTREQ_APORT3XREQ_DEFAULT (_ACMP_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
-#define ACMP_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is requested */
+#define ACMP_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is Requested */
#define _ACMP_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for ACMP_APORT3YREQ */
#define _ACMP_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for ACMP_APORT3YREQ */
#define _ACMP_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
#define ACMP_APORTREQ_APORT3YREQ_DEFAULT (_ACMP_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
-#define ACMP_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 if the bus connected to APORT4X is requested */
+#define ACMP_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is Requested */
#define _ACMP_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for ACMP_APORT4XREQ */
#define _ACMP_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for ACMP_APORT4XREQ */
#define _ACMP_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
#define ACMP_APORTREQ_APORT4XREQ_DEFAULT (_ACMP_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
-#define ACMP_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is requested */
+#define ACMP_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is Requested */
#define _ACMP_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for ACMP_APORT4YREQ */
#define _ACMP_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for ACMP_APORT4YREQ */
#define _ACMP_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
@@ -1146,52 +1153,52 @@ typedef struct
/* Bit fields for ACMP APORTCONFLICT */
#define _ACMP_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for ACMP_APORTCONFLICT */
#define _ACMP_APORTCONFLICT_MASK 0x000003FFUL /**< Mask for ACMP_APORTCONFLICT */
-#define ACMP_APORTCONFLICT_APORT0XCONFLICT (0x1UL << 0) /**< 1 if the bus connected to APORT0X is in conflict with another peripheral */
+#define ACMP_APORTCONFLICT_APORT0XCONFLICT (0x1UL << 0) /**< 1 If the Bus Connected to APORT0X is in Conflict With Another Peripheral */
#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_SHIFT 0 /**< Shift value for ACMP_APORT0XCONFLICT */
#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_MASK 0x1UL /**< Bit mask for ACMP_APORT0XCONFLICT */
#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
#define ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
-#define ACMP_APORTCONFLICT_APORT0YCONFLICT (0x1UL << 1) /**< 1 if the bus connected to APORT0Y is in conflict with another peripheral */
+#define ACMP_APORTCONFLICT_APORT0YCONFLICT (0x1UL << 1) /**< 1 If the Bus Connected to APORT0Y is in Conflict With Another Peripheral */
#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_SHIFT 1 /**< Shift value for ACMP_APORT0YCONFLICT */
#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_MASK 0x2UL /**< Bit mask for ACMP_APORT0YCONFLICT */
#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
#define ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
-#define ACMP_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */
+#define ACMP_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */
#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORT1XCONFLICT */
#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORT1XCONFLICT */
#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
#define ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
-#define ACMP_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */
+#define ACMP_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */
#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for ACMP_APORT1YCONFLICT */
#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_APORT1YCONFLICT */
#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
#define ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
-#define ACMP_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 if the bus connected to APORT2X is in conflict with another peripheral */
+#define ACMP_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is in Conflict With Another Peripheral */
#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for ACMP_APORT2XCONFLICT */
#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for ACMP_APORT2XCONFLICT */
#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
#define ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
-#define ACMP_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is in conflict with another peripheral */
+#define ACMP_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is in Conflict With Another Peripheral */
#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for ACMP_APORT2YCONFLICT */
#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for ACMP_APORT2YCONFLICT */
#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
#define ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
-#define ACMP_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 if the bus connected to APORT3X is in conflict with another peripheral */
+#define ACMP_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is in Conflict With Another Peripheral */
#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for ACMP_APORT3XCONFLICT */
#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for ACMP_APORT3XCONFLICT */
#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
#define ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
-#define ACMP_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is in conflict with another peripheral */
+#define ACMP_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is in Conflict With Another Peripheral */
#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for ACMP_APORT3YCONFLICT */
#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for ACMP_APORT3YCONFLICT */
#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
#define ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
-#define ACMP_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 if the bus connected to APORT4X is in conflict with another peripheral */
+#define ACMP_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is in Conflict With Another Peripheral */
#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for ACMP_APORT4XCONFLICT */
#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for ACMP_APORT4XCONFLICT */
#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
#define ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
-#define ACMP_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is in conflict with another peripheral */
+#define ACMP_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is in Conflict With Another Peripheral */
#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for ACMP_APORT4YCONFLICT */
#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for ACMP_APORT4YCONFLICT */
#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
@@ -1377,7 +1384,7 @@ typedef struct
/* Bit fields for ACMP EXTIFCTRL */
#define _ACMP_EXTIFCTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_EXTIFCTRL */
#define _ACMP_EXTIFCTRL_MASK 0x000000F1UL /**< Mask for ACMP_EXTIFCTRL */
-#define ACMP_EXTIFCTRL_EN (0x1UL << 0) /**< Enable external interface. */
+#define ACMP_EXTIFCTRL_EN (0x1UL << 0) /**< Enable External Interface */
#define _ACMP_EXTIFCTRL_EN_SHIFT 0 /**< Shift value for ACMP_EN */
#define _ACMP_EXTIFCTRL_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */
#define _ACMP_EXTIFCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EXTIFCTRL */
@@ -1415,6 +1422,6 @@ typedef struct
#define ACMP_EXTIFCTRL_APORTSEL_APORT4Y (_ACMP_EXTIFCTRL_APORTSEL_APORT4Y << 4) /**< Shifted mode APORT4Y for ACMP_EXTIFCTRL */
#define ACMP_EXTIFCTRL_APORTSEL_APORT4YX (_ACMP_EXTIFCTRL_APORTSEL_APORT4YX << 4) /**< Shifted mode APORT4YX for ACMP_EXTIFCTRL */
+/** @} */
/** @} End of group EFR32FG12P_ACMP */
/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_adc.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_adc.h
similarity index 98%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_adc.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_adc.h
index 8f6dc3bb..d7c7b301 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_adc.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_adc.h
@@ -1,58 +1,63 @@
-/**************************************************************************//**
- * @file efr32fg12p_adc.h
+/***************************************************************************//**
+ * @file
* @brief EFR32FG12P_ADC register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_ADC
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P_ADC ADC
* @{
* @brief EFR32FG12P_ADC Register Declaration
- *****************************************************************************/
-typedef struct
-{
+ ******************************************************************************/
+/** ADC Register Declaration */
+typedef struct {
__IOM uint32_t CTRL; /**< Control Register */
- uint32_t RESERVED0[1]; /**< Reserved for future use **/
+ uint32_t RESERVED0[1U]; /**< Reserved for future use **/
__IOM uint32_t CMD; /**< Command Register */
__IM uint32_t STATUS; /**< Status Register */
__IOM uint32_t SINGLECTRL; /**< Single Channel Control Register */
- __IOM uint32_t SINGLECTRLX; /**< Single Channel Control Register continued */
+ __IOM uint32_t SINGLECTRLX; /**< Single Channel Control Register Continued */
__IOM uint32_t SCANCTRL; /**< Scan Control Register */
- __IOM uint32_t SCANCTRLX; /**< Scan Control Register continued */
+ __IOM uint32_t SCANCTRLX; /**< Scan Control Register Continued */
__IOM uint32_t SCANMASK; /**< Scan Sequence Input Mask Register */
- __IOM uint32_t SCANINPUTSEL; /**< Input Selection register for Scan mode */
- __IOM uint32_t SCANNEGSEL; /**< Negative Input select register for Scan */
+ __IOM uint32_t SCANINPUTSEL; /**< Input Selection Register for Scan Mode */
+ __IOM uint32_t SCANNEGSEL; /**< Negative Input Select Register for Scan */
__IOM uint32_t CMPTHR; /**< Compare Threshold Register */
- __IOM uint32_t BIASPROG; /**< Bias Programming Register for various analog blocks used in ADC operation. */
+ __IOM uint32_t BIASPROG; /**< Bias Programming Register for Various Analog Blocks Used in ADC Operation */
__IOM uint32_t CAL; /**< Calibration Register */
__IM uint32_t IF; /**< Interrupt Flag Register */
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
@@ -62,11 +67,11 @@ typedef struct
__IM uint32_t SCANDATA; /**< Scan Conversion Result Data */
__IM uint32_t SINGLEDATAP; /**< Single Conversion Result Data Peek Register */
__IM uint32_t SCANDATAP; /**< Scan Sequence Result Data Peek Register */
- uint32_t RESERVED1[4]; /**< Reserved for future use **/
+ uint32_t RESERVED1[4U]; /**< Reserved for future use **/
__IM uint32_t SCANDATAX; /**< Scan Sequence Result Data + Data Source Register */
__IM uint32_t SCANDATAXP; /**< Scan Sequence Result Data + Data Source Peek Register */
- uint32_t RESERVED2[3]; /**< Reserved for future use **/
+ uint32_t RESERVED2[3U]; /**< Reserved for future use **/
__IM uint32_t APORTREQ; /**< APORT Request Status Register */
__IM uint32_t APORTCONFLICT; /**< APORT Conflict Status Register */
__IM uint32_t SINGLEFIFOCOUNT; /**< Single FIFO Count Register */
@@ -76,10 +81,12 @@ typedef struct
__IOM uint32_t APORTMASTERDIS; /**< APORT Bus Master Disable Register */
} ADC_TypeDef; /** @} */
-/**************************************************************************//**
- * @defgroup EFR32FG12P_ADC_BitFields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_ADC
+ * @{
+ * @defgroup EFR32FG12P_ADC_BitFields ADC Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for ADC CTRL */
#define _ADC_CTRL_RESETVALUE 0x001F0000UL /**< Default value for ADC_CTRL */
@@ -111,7 +118,7 @@ typedef struct
#define _ADC_CTRL_TAILGATE_MASK 0x10UL /**< Bit mask for ADC_TAILGATE */
#define _ADC_CTRL_TAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
#define ADC_CTRL_TAILGATE_DEFAULT (_ADC_CTRL_TAILGATE_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_CTRL */
-#define ADC_CTRL_ASYNCCLKEN (0x1UL << 6) /**< Selects ASYNC CLK enable mode when ADCCLKMODE=1 */
+#define ADC_CTRL_ASYNCCLKEN (0x1UL << 6) /**< Selects ASYNC CLK Enable Mode When ADCCLKMODE=1 */
#define _ADC_CTRL_ASYNCCLKEN_SHIFT 6 /**< Shift value for ADC_ASYNCCLKEN */
#define _ADC_CTRL_ASYNCCLKEN_MASK 0x40UL /**< Bit mask for ADC_ASYNCCLKEN */
#define _ADC_CTRL_ASYNCCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
@@ -485,17 +492,17 @@ typedef struct
#define _ADC_SINGLECTRL_POSSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_POSSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_POSSEL_AVDD 0x000000E0UL /**< Mode AVDD for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_BU 0x000000E1UL /**< Mode BU for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_AREG 0x000000E2UL /**< Mode AREG for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_VREGOUTPA 0x000000E3UL /**< Mode VREGOUTPA for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_PDBU 0x000000E4UL /**< Mode PDBU for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_IO0 0x000000E5UL /**< Mode IO0 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_IO1 0x000000E6UL /**< Mode IO1 for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_BUVDD 0x000000E1UL /**< Mode BUVDD for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_DVDD 0x000000E2UL /**< Mode DVDD for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_PAVDD 0x000000E3UL /**< Mode PAVDD for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_DECOUPLE 0x000000E4UL /**< Mode DECOUPLE for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_IOVDD 0x000000E5UL /**< Mode IOVDD for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_IOVDD1 0x000000E6UL /**< Mode IOVDD1 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_POSSEL_VSP 0x000000E7UL /**< Mode VSP for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_POSSEL_OPA2 0x000000F2UL /**< Mode OPA2 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_POSSEL_TEMP 0x000000F3UL /**< Mode TEMP for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_POSSEL_DAC0OUT0 0x000000F4UL /**< Mode DAC0OUT0 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_TESTP 0x000000F5UL /**< Mode TESTP for ADC_SINGLECTRL */
+#define _ADC_SINGLECTRL_POSSEL_R5VOUT 0x000000F5UL /**< Mode R5VOUT for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_POSSEL_SP1 0x000000F6UL /**< Mode SP1 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_POSSEL_SP2 0x000000F7UL /**< Mode SP2 for ADC_SINGLECTRL */
#define _ADC_SINGLECTRL_POSSEL_DAC0OUT1 0x000000F8UL /**< Mode DAC0OUT1 for ADC_SINGLECTRL */
@@ -664,17 +671,17 @@ typedef struct
#define ADC_SINGLECTRL_POSSEL_APORT4YCH30 (_ADC_SINGLECTRL_POSSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_POSSEL_APORT4XCH31 (_ADC_SINGLECTRL_POSSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_POSSEL_AVDD (_ADC_SINGLECTRL_POSSEL_AVDD << 8) /**< Shifted mode AVDD for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_BU (_ADC_SINGLECTRL_POSSEL_BU << 8) /**< Shifted mode BU for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_AREG (_ADC_SINGLECTRL_POSSEL_AREG << 8) /**< Shifted mode AREG for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_VREGOUTPA (_ADC_SINGLECTRL_POSSEL_VREGOUTPA << 8) /**< Shifted mode VREGOUTPA for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_PDBU (_ADC_SINGLECTRL_POSSEL_PDBU << 8) /**< Shifted mode PDBU for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_IO0 (_ADC_SINGLECTRL_POSSEL_IO0 << 8) /**< Shifted mode IO0 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_IO1 (_ADC_SINGLECTRL_POSSEL_IO1 << 8) /**< Shifted mode IO1 for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_BUVDD (_ADC_SINGLECTRL_POSSEL_BUVDD << 8) /**< Shifted mode BUVDD for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_DVDD (_ADC_SINGLECTRL_POSSEL_DVDD << 8) /**< Shifted mode DVDD for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_PAVDD (_ADC_SINGLECTRL_POSSEL_PAVDD << 8) /**< Shifted mode PAVDD for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_DECOUPLE (_ADC_SINGLECTRL_POSSEL_DECOUPLE << 8) /**< Shifted mode DECOUPLE for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_IOVDD (_ADC_SINGLECTRL_POSSEL_IOVDD << 8) /**< Shifted mode IOVDD for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_IOVDD1 (_ADC_SINGLECTRL_POSSEL_IOVDD1 << 8) /**< Shifted mode IOVDD1 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_POSSEL_VSP (_ADC_SINGLECTRL_POSSEL_VSP << 8) /**< Shifted mode VSP for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_POSSEL_OPA2 (_ADC_SINGLECTRL_POSSEL_OPA2 << 8) /**< Shifted mode OPA2 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_POSSEL_TEMP (_ADC_SINGLECTRL_POSSEL_TEMP << 8) /**< Shifted mode TEMP for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_POSSEL_DAC0OUT0 (_ADC_SINGLECTRL_POSSEL_DAC0OUT0 << 8) /**< Shifted mode DAC0OUT0 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_TESTP (_ADC_SINGLECTRL_POSSEL_TESTP << 8) /**< Shifted mode TESTP for ADC_SINGLECTRL */
+#define ADC_SINGLECTRL_POSSEL_R5VOUT (_ADC_SINGLECTRL_POSSEL_R5VOUT << 8) /**< Shifted mode R5VOUT for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_POSSEL_SP1 (_ADC_SINGLECTRL_POSSEL_SP1 << 8) /**< Shifted mode SP1 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_POSSEL_SP2 (_ADC_SINGLECTRL_POSSEL_SP2 << 8) /**< Shifted mode SP2 for ADC_SINGLECTRL */
#define ADC_SINGLECTRL_POSSEL_DAC0OUT1 (_ADC_SINGLECTRL_POSSEL_DAC0OUT1 << 8) /**< Shifted mode DAC0OUT1 for ADC_SINGLECTRL */
@@ -1068,7 +1075,7 @@ typedef struct
#define ADC_SINGLECTRLX_VREFSEL_VREFPNWATT (_ADC_SINGLECTRLX_VREFSEL_VREFPNWATT << 0) /**< Shifted mode VREFPNWATT for ADC_SINGLECTRLX */
#define ADC_SINGLECTRLX_VREFSEL_VREFPN (_ADC_SINGLECTRLX_VREFSEL_VREFPN << 0) /**< Shifted mode VREFPN for ADC_SINGLECTRLX */
#define ADC_SINGLECTRLX_VREFSEL_VBGRLOW (_ADC_SINGLECTRLX_VREFSEL_VBGRLOW << 0) /**< Shifted mode VBGRLOW for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_VREFATTFIX (0x1UL << 3) /**< Enable fixed scaling on VREF */
+#define ADC_SINGLECTRLX_VREFATTFIX (0x1UL << 3) /**< Enable Fixed Scaling on VREF */
#define _ADC_SINGLECTRLX_VREFATTFIX_SHIFT 3 /**< Shift value for ADC_VREFATTFIX */
#define _ADC_SINGLECTRLX_VREFATTFIX_MASK 0x8UL /**< Bit mask for ADC_VREFATTFIX */
#define _ADC_SINGLECTRLX_VREFATTFIX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
@@ -1135,7 +1142,7 @@ typedef struct
#define _ADC_SINGLECTRLX_CONVSTARTDELAY_MASK 0x7C00000UL /**< Bit mask for ADC_CONVSTARTDELAY */
#define _ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
#define ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT (_ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT << 22) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_CONVSTARTDELAYEN (0x1UL << 27) /**< Enable delaying next conversion start */
+#define ADC_SINGLECTRLX_CONVSTARTDELAYEN (0x1UL << 27) /**< Enable Delaying Next Conversion Start */
#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_SHIFT 27 /**< Shift value for ADC_CONVSTARTDELAYEN */
#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_MASK 0x8000000UL /**< Bit mask for ADC_CONVSTARTDELAYEN */
#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
@@ -1271,7 +1278,7 @@ typedef struct
#define ADC_SCANCTRLX_VREFSEL_VREFPNWATT (_ADC_SCANCTRLX_VREFSEL_VREFPNWATT << 0) /**< Shifted mode VREFPNWATT for ADC_SCANCTRLX */
#define ADC_SCANCTRLX_VREFSEL_VREFPN (_ADC_SCANCTRLX_VREFSEL_VREFPN << 0) /**< Shifted mode VREFPN for ADC_SCANCTRLX */
#define ADC_SCANCTRLX_VREFSEL_VBGRLOW (_ADC_SCANCTRLX_VREFSEL_VBGRLOW << 0) /**< Shifted mode VBGRLOW for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_VREFATTFIX (0x1UL << 3) /**< Enable fixed scaling on VREF */
+#define ADC_SCANCTRLX_VREFATTFIX (0x1UL << 3) /**< Enable Fixed Scaling on VREF */
#define _ADC_SCANCTRLX_VREFATTFIX_SHIFT 3 /**< Shift value for ADC_VREFATTFIX */
#define _ADC_SCANCTRLX_VREFATTFIX_MASK 0x8UL /**< Bit mask for ADC_VREFATTFIX */
#define _ADC_SCANCTRLX_VREFATTFIX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
@@ -1338,7 +1345,7 @@ typedef struct
#define _ADC_SCANCTRLX_CONVSTARTDELAY_MASK 0x7C00000UL /**< Bit mask for ADC_CONVSTARTDELAY */
#define _ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
#define ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT (_ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT << 22) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_CONVSTARTDELAYEN (0x1UL << 27) /**< Enable delaying next conversion start */
+#define ADC_SCANCTRLX_CONVSTARTDELAYEN (0x1UL << 27) /**< Enable Delaying Next Conversion Start */
#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_SHIFT 27 /**< Shift value for ADC_CONVSTARTDELAYEN */
#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_MASK 0x8000000UL /**< Bit mask for ADC_CONVSTARTDELAYEN */
#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
@@ -1370,133 +1377,133 @@ typedef struct
#define _ADC_SCANMASK_SCANINPUTEN_SHIFT 0 /**< Shift value for ADC_SCANINPUTEN */
#define _ADC_SCANMASK_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_SCANINPUTEN */
#define _ADC_SCANMASK_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL 0x00000001UL /**< Mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT0 0x00000001UL /**< Mode INPUT0 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT1 0x00000002UL /**< Mode INPUT1 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL 0x00000001UL /**< Mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 0x00000002UL /**< Mode INPUT1INPUT2 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT1 0x00000002UL /**< Mode INPUT1 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT2 0x00000004UL /**< Mode INPUT2 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL 0x00000004UL /**< Mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT3 0x00000008UL /**< Mode INPUT3 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 0x00000008UL /**< Mode INPUT3INPUT4 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT4 0x00000010UL /**< Mode INPUT4 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT3 0x00000008UL /**< Mode INPUT3 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL 0x00000010UL /**< Mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT4 0x00000010UL /**< Mode INPUT4 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 0x00000020UL /**< Mode INPUT5INPUT6 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT5 0x00000020UL /**< Mode INPUT5 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL 0x00000040UL /**< Mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT6 0x00000040UL /**< Mode INPUT6 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT7 0x00000080UL /**< Mode INPUT7 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL 0x00000040UL /**< Mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 0x00000080UL /**< Mode INPUT7INPUT0 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 0x00000100UL /**< Mode INPUT8INPUT9 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT7 0x00000080UL /**< Mode INPUT7 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT8 0x00000100UL /**< Mode INPUT8 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT9 0x00000200UL /**< Mode INPUT9 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 0x00000100UL /**< Mode INPUT8INPUT9 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL 0x00000200UL /**< Mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 0x00000400UL /**< Mode INPUT10INPUT11 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT9 0x00000200UL /**< Mode INPUT9 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT10 0x00000400UL /**< Mode INPUT10 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL 0x00000800UL /**< Mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 0x00000400UL /**< Mode INPUT10INPUT11 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT11 0x00000800UL /**< Mode INPUT11 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 0x00001000UL /**< Mode INPUT12INPUT13 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL 0x00000800UL /**< Mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT12 0x00001000UL /**< Mode INPUT12 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL 0x00002000UL /**< Mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 0x00001000UL /**< Mode INPUT12INPUT13 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT13 0x00002000UL /**< Mode INPUT13 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 0x00004000UL /**< Mode INPUT14INPUT15 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL 0x00002000UL /**< Mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT14 0x00004000UL /**< Mode INPUT14 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL 0x00008000UL /**< Mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 0x00004000UL /**< Mode INPUT14INPUT15 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT15 0x00008000UL /**< Mode INPUT15 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 0x00010000UL /**< Mode INPUT16INPUT17 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL 0x00008000UL /**< Mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT16 0x00010000UL /**< Mode INPUT16 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 0x00020000UL /**< Mode INPUT17INPUT18 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 0x00010000UL /**< Mode INPUT16INPUT17 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT17 0x00020000UL /**< Mode INPUT17 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 0x00020000UL /**< Mode INPUT17INPUT18 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 0x00040000UL /**< Mode INPUT18INPUT19 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT18 0x00040000UL /**< Mode INPUT18 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT19 0x00080000UL /**< Mode INPUT19 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 0x00080000UL /**< Mode INPUT19INPUT20 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 0x00100000UL /**< Mode INPUT20INPUT21 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT20 0x00100000UL /**< Mode INPUT20 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT21 0x00200000UL /**< Mode INPUT21 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 0x00200000UL /**< Mode INPUT21INPUT22 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT21 0x00200000UL /**< Mode INPUT21 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 0x00400000UL /**< Mode INPUT22INPUT23 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT22 0x00400000UL /**< Mode INPUT22 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 0x00800000UL /**< Mode INPUT23INPUT16 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT23 0x00800000UL /**< Mode INPUT23 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT24 0x01000000UL /**< Mode INPUT24 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 0x00800000UL /**< Mode INPUT23INPUT16 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 0x01000000UL /**< Mode INPUT24INPUT25 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 0x02000000UL /**< Mode INPUT25INPUT26 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT24 0x01000000UL /**< Mode INPUT24 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT25 0x02000000UL /**< Mode INPUT25 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT26 0x04000000UL /**< Mode INPUT26 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 0x02000000UL /**< Mode INPUT25INPUT26 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 0x04000000UL /**< Mode INPUT26INPUT27 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 0x08000000UL /**< Mode INPUT27INPUT28 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT26 0x04000000UL /**< Mode INPUT26 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT27 0x08000000UL /**< Mode INPUT27 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 0x10000000UL /**< Mode INPUT28INPUT29 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 0x08000000UL /**< Mode INPUT27INPUT28 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT28 0x10000000UL /**< Mode INPUT28 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 0x10000000UL /**< Mode INPUT28INPUT29 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT29 0x20000000UL /**< Mode INPUT29 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 0x20000000UL /**< Mode INPUT29INPUT30 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT30 0x40000000UL /**< Mode INPUT30 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 0x40000000UL /**< Mode INPUT30INPUT31 for ADC_SCANMASK */
+#define _ADC_SCANMASK_SCANINPUTEN_INPUT30 0x40000000UL /**< Mode INPUT30 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 0x80000000UL /**< Mode INPUT31INPUT24 for ADC_SCANMASK */
#define _ADC_SCANMASK_SCANINPUTEN_INPUT31 0x80000000UL /**< Mode INPUT31 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_DEFAULT (_ADC_SCANMASK_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL << 0) /**< Shifted mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT0 (_ADC_SCANMASK_SCANINPUTEN_INPUT0 << 0) /**< Shifted mode INPUT0 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT1 (_ADC_SCANMASK_SCANINPUTEN_INPUT1 << 0) /**< Shifted mode INPUT1 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL << 0) /**< Shifted mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 (_ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 << 0) /**< Shifted mode INPUT1INPUT2 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT1 (_ADC_SCANMASK_SCANINPUTEN_INPUT1 << 0) /**< Shifted mode INPUT1 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT2 (_ADC_SCANMASK_SCANINPUTEN_INPUT2 << 0) /**< Shifted mode INPUT2 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL << 0) /**< Shifted mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT3 (_ADC_SCANMASK_SCANINPUTEN_INPUT3 << 0) /**< Shifted mode INPUT3 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 << 0) /**< Shifted mode INPUT3INPUT4 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT4 << 0) /**< Shifted mode INPUT4 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT3 (_ADC_SCANMASK_SCANINPUTEN_INPUT3 << 0) /**< Shifted mode INPUT3 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL << 0) /**< Shifted mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT4 << 0) /**< Shifted mode INPUT4 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 (_ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 << 0) /**< Shifted mode INPUT5INPUT6 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT5 (_ADC_SCANMASK_SCANINPUTEN_INPUT5 << 0) /**< Shifted mode INPUT5 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL << 0) /**< Shifted mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT6 (_ADC_SCANMASK_SCANINPUTEN_INPUT6 << 0) /**< Shifted mode INPUT6 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT7 (_ADC_SCANMASK_SCANINPUTEN_INPUT7 << 0) /**< Shifted mode INPUT7 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL << 0) /**< Shifted mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 (_ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 << 0) /**< Shifted mode INPUT7INPUT0 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 << 0) /**< Shifted mode INPUT8INPUT9 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT7 (_ADC_SCANMASK_SCANINPUTEN_INPUT7 << 0) /**< Shifted mode INPUT7 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT8 (_ADC_SCANMASK_SCANINPUTEN_INPUT8 << 0) /**< Shifted mode INPUT8 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT9 << 0) /**< Shifted mode INPUT9 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 << 0) /**< Shifted mode INPUT8INPUT9 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL << 0) /**< Shifted mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 << 0) /**< Shifted mode INPUT10INPUT11 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT9 << 0) /**< Shifted mode INPUT9 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT10 (_ADC_SCANMASK_SCANINPUTEN_INPUT10 << 0) /**< Shifted mode INPUT10 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL << 0) /**< Shifted mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 << 0) /**< Shifted mode INPUT10INPUT11 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT11 << 0) /**< Shifted mode INPUT11 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 << 0) /**< Shifted mode INPUT12INPUT13 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL << 0) /**< Shifted mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT12 (_ADC_SCANMASK_SCANINPUTEN_INPUT12 << 0) /**< Shifted mode INPUT12 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL << 0) /**< Shifted mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 << 0) /**< Shifted mode INPUT12INPUT13 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT13 << 0) /**< Shifted mode INPUT13 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 << 0) /**< Shifted mode INPUT14INPUT15 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL << 0) /**< Shifted mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT14 (_ADC_SCANMASK_SCANINPUTEN_INPUT14 << 0) /**< Shifted mode INPUT14 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL << 0) /**< Shifted mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 << 0) /**< Shifted mode INPUT14INPUT15 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT15 << 0) /**< Shifted mode INPUT15 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 << 0) /**< Shifted mode INPUT16INPUT17 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL << 0) /**< Shifted mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT16 << 0) /**< Shifted mode INPUT16 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 << 0) /**< Shifted mode INPUT17INPUT18 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 << 0) /**< Shifted mode INPUT16INPUT17 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT17 << 0) /**< Shifted mode INPUT17 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 << 0) /**< Shifted mode INPUT17INPUT18 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 (_ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 << 0) /**< Shifted mode INPUT18INPUT19 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT18 << 0) /**< Shifted mode INPUT18 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT19 (_ADC_SCANMASK_SCANINPUTEN_INPUT19 << 0) /**< Shifted mode INPUT19 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 (_ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 << 0) /**< Shifted mode INPUT19INPUT20 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 << 0) /**< Shifted mode INPUT20INPUT21 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT20 (_ADC_SCANMASK_SCANINPUTEN_INPUT20 << 0) /**< Shifted mode INPUT20 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT21 << 0) /**< Shifted mode INPUT21 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 (_ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 << 0) /**< Shifted mode INPUT21INPUT22 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT21 << 0) /**< Shifted mode INPUT21 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 (_ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 << 0) /**< Shifted mode INPUT22INPUT23 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT22 (_ADC_SCANMASK_SCANINPUTEN_INPUT22 << 0) /**< Shifted mode INPUT22 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 << 0) /**< Shifted mode INPUT23INPUT16 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT23 (_ADC_SCANMASK_SCANINPUTEN_INPUT23 << 0) /**< Shifted mode INPUT23 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT24 << 0) /**< Shifted mode INPUT24 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 << 0) /**< Shifted mode INPUT23INPUT16 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 (_ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 << 0) /**< Shifted mode INPUT24INPUT25 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 << 0) /**< Shifted mode INPUT25INPUT26 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT24 << 0) /**< Shifted mode INPUT24 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT25 (_ADC_SCANMASK_SCANINPUTEN_INPUT25 << 0) /**< Shifted mode INPUT25 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT26 << 0) /**< Shifted mode INPUT26 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 << 0) /**< Shifted mode INPUT25INPUT26 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 (_ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 << 0) /**< Shifted mode INPUT26INPUT27 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 << 0) /**< Shifted mode INPUT27INPUT28 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT26 << 0) /**< Shifted mode INPUT26 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT27 (_ADC_SCANMASK_SCANINPUTEN_INPUT27 << 0) /**< Shifted mode INPUT27 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 << 0) /**< Shifted mode INPUT28INPUT29 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 << 0) /**< Shifted mode INPUT27INPUT28 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT28 << 0) /**< Shifted mode INPUT28 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 << 0) /**< Shifted mode INPUT28INPUT29 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT29 << 0) /**< Shifted mode INPUT29 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 << 0) /**< Shifted mode INPUT29INPUT30 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT30 << 0) /**< Shifted mode INPUT30 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 (_ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 << 0) /**< Shifted mode INPUT30INPUT31 for ADC_SCANMASK */
+#define ADC_SCANMASK_SCANINPUTEN_INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT30 << 0) /**< Shifted mode INPUT30 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 << 0) /**< Shifted mode INPUT31INPUT24 for ADC_SCANMASK */
#define ADC_SCANMASK_SCANINPUTEN_INPUT31 (_ADC_SCANMASK_SCANINPUTEN_INPUT31 << 0) /**< Shifted mode INPUT31 for ADC_SCANMASK */
@@ -1795,12 +1802,12 @@ typedef struct
#define ADC_BIASPROG_ADCBIASPROG_SCALE8 (_ADC_BIASPROG_ADCBIASPROG_SCALE8 << 0) /**< Shifted mode SCALE8 for ADC_BIASPROG */
#define ADC_BIASPROG_ADCBIASPROG_SCALE16 (_ADC_BIASPROG_ADCBIASPROG_SCALE16 << 0) /**< Shifted mode SCALE16 for ADC_BIASPROG */
#define ADC_BIASPROG_ADCBIASPROG_SCALE32 (_ADC_BIASPROG_ADCBIASPROG_SCALE32 << 0) /**< Shifted mode SCALE32 for ADC_BIASPROG */
-#define ADC_BIASPROG_VFAULTCLR (0x1UL << 12) /**< Clear VREFOF flag */
+#define ADC_BIASPROG_VFAULTCLR (0x1UL << 12) /**< Clear VREFOF Flag */
#define _ADC_BIASPROG_VFAULTCLR_SHIFT 12 /**< Shift value for ADC_VFAULTCLR */
#define _ADC_BIASPROG_VFAULTCLR_MASK 0x1000UL /**< Bit mask for ADC_VFAULTCLR */
#define _ADC_BIASPROG_VFAULTCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */
#define ADC_BIASPROG_VFAULTCLR_DEFAULT (_ADC_BIASPROG_VFAULTCLR_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_BIASPROG */
-#define ADC_BIASPROG_GPBIASACC (0x1UL << 16) /**< Accuracy setting for the system bias during ADC operation */
+#define ADC_BIASPROG_GPBIASACC (0x1UL << 16) /**< Accuracy Setting for the System Bias During ADC Operation */
#define _ADC_BIASPROG_GPBIASACC_SHIFT 16 /**< Shift value for ADC_GPBIASACC */
#define _ADC_BIASPROG_GPBIASACC_MASK 0x10000UL /**< Bit mask for ADC_GPBIASACC */
#define _ADC_BIASPROG_GPBIASACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */
@@ -1825,7 +1832,7 @@ typedef struct
#define _ADC_CAL_SINGLEGAIN_MASK 0x7F00UL /**< Bit mask for ADC_SINGLEGAIN */
#define _ADC_CAL_SINGLEGAIN_DEFAULT 0x00000040UL /**< Mode DEFAULT for ADC_CAL */
#define ADC_CAL_SINGLEGAIN_DEFAULT (_ADC_CAL_SINGLEGAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CAL */
-#define ADC_CAL_OFFSETINVMODE (0x1UL << 15) /**< Negative single-ended offset calibration is enabled */
+#define ADC_CAL_OFFSETINVMODE (0x1UL << 15) /**< Negative Single-ended Offset Calibration is Enabled */
#define _ADC_CAL_OFFSETINVMODE_SHIFT 15 /**< Shift value for ADC_OFFSETINVMODE */
#define _ADC_CAL_OFFSETINVMODE_MASK 0x8000UL /**< Bit mask for ADC_OFFSETINVMODE */
#define _ADC_CAL_OFFSETINVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */
@@ -1842,7 +1849,7 @@ typedef struct
#define _ADC_CAL_SCANGAIN_MASK 0x7F000000UL /**< Bit mask for ADC_SCANGAIN */
#define _ADC_CAL_SCANGAIN_DEFAULT 0x00000040UL /**< Mode DEFAULT for ADC_CAL */
#define ADC_CAL_SCANGAIN_DEFAULT (_ADC_CAL_SCANGAIN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CAL */
-#define ADC_CAL_CALEN (0x1UL << 31) /**< Calibration mode is enabled */
+#define ADC_CAL_CALEN (0x1UL << 31) /**< Calibration Mode is Enabled */
#define _ADC_CAL_CALEN_SHIFT 31 /**< Shift value for ADC_CALEN */
#define _ADC_CAL_CALEN_MASK 0x80000000UL /**< Bit mask for ADC_CALEN */
#define _ADC_CAL_CALEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */
@@ -2183,52 +2190,52 @@ typedef struct
/* Bit fields for ADC APORTREQ */
#define _ADC_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTREQ */
#define _ADC_APORTREQ_MASK 0x000003FFUL /**< Mask for ADC_APORTREQ */
-#define ADC_APORTREQ_APORT0XREQ (0x1UL << 0) /**< 1 if the bus connected to APORT0X is requested */
+#define ADC_APORTREQ_APORT0XREQ (0x1UL << 0) /**< 1 If the Bus Connected to APORT0X is Requested */
#define _ADC_APORTREQ_APORT0XREQ_SHIFT 0 /**< Shift value for ADC_APORT0XREQ */
#define _ADC_APORTREQ_APORT0XREQ_MASK 0x1UL /**< Bit mask for ADC_APORT0XREQ */
#define _ADC_APORTREQ_APORT0XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
#define ADC_APORTREQ_APORT0XREQ_DEFAULT (_ADC_APORTREQ_APORT0XREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_APORTREQ */
-#define ADC_APORTREQ_APORT0YREQ (0x1UL << 1) /**< 1 if the bus connected to APORT0Y is requested */
+#define ADC_APORTREQ_APORT0YREQ (0x1UL << 1) /**< 1 If the Bus Connected to APORT0Y is Requested */
#define _ADC_APORTREQ_APORT0YREQ_SHIFT 1 /**< Shift value for ADC_APORT0YREQ */
#define _ADC_APORTREQ_APORT0YREQ_MASK 0x2UL /**< Bit mask for ADC_APORT0YREQ */
#define _ADC_APORTREQ_APORT0YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
#define ADC_APORTREQ_APORT0YREQ_DEFAULT (_ADC_APORTREQ_APORT0YREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_APORTREQ */
-#define ADC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the bus connected to APORT1X is requested */
+#define ADC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is Requested */
#define _ADC_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for ADC_APORT1XREQ */
#define _ADC_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for ADC_APORT1XREQ */
#define _ADC_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
#define ADC_APORTREQ_APORT1XREQ_DEFAULT (_ADC_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTREQ */
-#define ADC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is requested */
+#define ADC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is Requested */
#define _ADC_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for ADC_APORT1YREQ */
#define _ADC_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for ADC_APORT1YREQ */
#define _ADC_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
#define ADC_APORTREQ_APORT1YREQ_DEFAULT (_ADC_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTREQ */
-#define ADC_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 if the bus connected to APORT2X is requested */
+#define ADC_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is Requested */
#define _ADC_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for ADC_APORT2XREQ */
#define _ADC_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for ADC_APORT2XREQ */
#define _ADC_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
#define ADC_APORTREQ_APORT2XREQ_DEFAULT (_ADC_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTREQ */
-#define ADC_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is requested */
+#define ADC_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is Requested */
#define _ADC_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for ADC_APORT2YREQ */
#define _ADC_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for ADC_APORT2YREQ */
#define _ADC_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
#define ADC_APORTREQ_APORT2YREQ_DEFAULT (_ADC_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTREQ */
-#define ADC_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 if the bus connected to APORT3X is requested */
+#define ADC_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is Requested */
#define _ADC_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for ADC_APORT3XREQ */
#define _ADC_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for ADC_APORT3XREQ */
#define _ADC_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
#define ADC_APORTREQ_APORT3XREQ_DEFAULT (_ADC_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTREQ */
-#define ADC_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is requested */
+#define ADC_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is Requested */
#define _ADC_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for ADC_APORT3YREQ */
#define _ADC_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for ADC_APORT3YREQ */
#define _ADC_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
#define ADC_APORTREQ_APORT3YREQ_DEFAULT (_ADC_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTREQ */
-#define ADC_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 if the bus connected to APORT4X is requested */
+#define ADC_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is Requested */
#define _ADC_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for ADC_APORT4XREQ */
#define _ADC_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for ADC_APORT4XREQ */
#define _ADC_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
#define ADC_APORTREQ_APORT4XREQ_DEFAULT (_ADC_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTREQ */
-#define ADC_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is requested */
+#define ADC_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is Requested */
#define _ADC_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for ADC_APORT4YREQ */
#define _ADC_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for ADC_APORT4YREQ */
#define _ADC_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
@@ -2237,52 +2244,52 @@ typedef struct
/* Bit fields for ADC APORTCONFLICT */
#define _ADC_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTCONFLICT */
#define _ADC_APORTCONFLICT_MASK 0x000003FFUL /**< Mask for ADC_APORTCONFLICT */
-#define ADC_APORTCONFLICT_APORT0XCONFLICT (0x1UL << 0) /**< 1 if the bus connected to APORT0X is in conflict with another peripheral */
+#define ADC_APORTCONFLICT_APORT0XCONFLICT (0x1UL << 0) /**< 1 If the Bus Connected to APORT0X is in Conflict With Another Peripheral */
#define _ADC_APORTCONFLICT_APORT0XCONFLICT_SHIFT 0 /**< Shift value for ADC_APORT0XCONFLICT */
#define _ADC_APORTCONFLICT_APORT0XCONFLICT_MASK 0x1UL /**< Bit mask for ADC_APORT0XCONFLICT */
#define _ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
#define ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
-#define ADC_APORTCONFLICT_APORT0YCONFLICT (0x1UL << 1) /**< 1 if the bus connected to APORT0Y is in conflict with another peripheral */
+#define ADC_APORTCONFLICT_APORT0YCONFLICT (0x1UL << 1) /**< 1 If the Bus Connected to APORT0Y is in Conflict With Another Peripheral */
#define _ADC_APORTCONFLICT_APORT0YCONFLICT_SHIFT 1 /**< Shift value for ADC_APORT0YCONFLICT */
#define _ADC_APORTCONFLICT_APORT0YCONFLICT_MASK 0x2UL /**< Bit mask for ADC_APORT0YCONFLICT */
#define _ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
#define ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
-#define ADC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */
+#define ADC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */
#define _ADC_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for ADC_APORT1XCONFLICT */
#define _ADC_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for ADC_APORT1XCONFLICT */
#define _ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
#define ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
-#define ADC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is in conflict with another peripheral */
+#define ADC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is in Conflict With Another Peripheral */
#define _ADC_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for ADC_APORT1YCONFLICT */
#define _ADC_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for ADC_APORT1YCONFLICT */
#define _ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
#define ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
-#define ADC_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 if the bus connected to APORT2X is in conflict with another peripheral */
+#define ADC_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is in Conflict With Another Peripheral */
#define _ADC_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for ADC_APORT2XCONFLICT */
#define _ADC_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for ADC_APORT2XCONFLICT */
#define _ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
#define ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
-#define ADC_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is in conflict with another peripheral */
+#define ADC_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is in Conflict With Another Peripheral */
#define _ADC_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for ADC_APORT2YCONFLICT */
#define _ADC_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for ADC_APORT2YCONFLICT */
#define _ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
#define ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
-#define ADC_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 if the bus connected to APORT3X is in conflict with another peripheral */
+#define ADC_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is in Conflict With Another Peripheral */
#define _ADC_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for ADC_APORT3XCONFLICT */
#define _ADC_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for ADC_APORT3XCONFLICT */
#define _ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
#define ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
-#define ADC_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is in conflict with another peripheral */
+#define ADC_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is in Conflict With Another Peripheral */
#define _ADC_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for ADC_APORT3YCONFLICT */
#define _ADC_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for ADC_APORT3YCONFLICT */
#define _ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
#define ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
-#define ADC_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 if the bus connected to APORT4X is in conflict with another peripheral */
+#define ADC_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is in Conflict With Another Peripheral */
#define _ADC_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for ADC_APORT4XCONFLICT */
#define _ADC_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for ADC_APORT4XCONFLICT */
#define _ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
#define ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
-#define ADC_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is in conflict with another peripheral */
+#define ADC_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is in Conflict With Another Peripheral */
#define _ADC_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for ADC_APORT4YCONFLICT */
#define _ADC_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for ADC_APORT4YCONFLICT */
#define _ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
@@ -2307,7 +2314,7 @@ typedef struct
/* Bit fields for ADC SINGLEFIFOCLEAR */
#define _ADC_SINGLEFIFOCLEAR_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEFIFOCLEAR */
#define _ADC_SINGLEFIFOCLEAR_MASK 0x00000001UL /**< Mask for ADC_SINGLEFIFOCLEAR */
-#define ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR (0x1UL << 0) /**< Clear Single FIFO content */
+#define ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR (0x1UL << 0) /**< Clear Single FIFO Content */
#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_SHIFT 0 /**< Shift value for ADC_SINGLEFIFOCLEAR */
#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_MASK 0x1UL /**< Bit mask for ADC_SINGLEFIFOCLEAR */
#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEFIFOCLEAR */
@@ -2316,7 +2323,7 @@ typedef struct
/* Bit fields for ADC SCANFIFOCLEAR */
#define _ADC_SCANFIFOCLEAR_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANFIFOCLEAR */
#define _ADC_SCANFIFOCLEAR_MASK 0x00000001UL /**< Mask for ADC_SCANFIFOCLEAR */
-#define ADC_SCANFIFOCLEAR_SCANFIFOCLEAR (0x1UL << 0) /**< Clear Scan FIFO content */
+#define ADC_SCANFIFOCLEAR_SCANFIFOCLEAR (0x1UL << 0) /**< Clear Scan FIFO Content */
#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_SHIFT 0 /**< Shift value for ADC_SCANFIFOCLEAR */
#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_MASK 0x1UL /**< Bit mask for ADC_SCANFIFOCLEAR */
#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANFIFOCLEAR */
@@ -2366,6 +2373,6 @@ typedef struct
#define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */
#define ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
+/** @} */
/** @} End of group EFR32FG12P_ADC */
/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_af_pins.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_af_pins.h
similarity index 62%
rename from mcu/efr/common/vendor/efr32fg13/efr32fg13p_af_pins.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_af_pins.h
index f1ed4fbc..46bb1d28 100644
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_af_pins.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_af_pins.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efr32fg13p_af_pins.h
- * @brief EFR32FG13P_AF_PINS register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+/***************************************************************************//**
+ * @file
+ * @brief EFR32FG12P_AF_PINS register and bit field definitions
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#if defined(__ICCARM__)
#pragma system_include /* Treat file as system include file. */
@@ -36,121 +34,139 @@
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_Alternate_Function Alternate Function
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_Alternate_Function Alternate Function
* @{
- * @defgroup EFR32FG13P_AF_Pins Alternate Function Pins
+ * @defgroup EFR32FG12P_AF_Pins Alternate Function Pins
* @{
- *****************************************************************************/
+ ******************************************************************************/
-#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 15 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 7 : -1) /**< Pin number for AF_CMU_CLK0 location number i */
-#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 14 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 10 : (i) == 5 ? 15 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_CMU_CLK1 location number i */
-#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? -1 : (i) == 4 ? 5 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */
-#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : -1) /**< Pin number for AF_PRS_CH0 location number i */
-#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 0 : -1) /**< Pin number for AF_PRS_CH1 location number i */
-#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Pin number for AF_PRS_CH2 location number i */
-#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 11 : (i) == 11 ? 12 : (i) == 12 ? 13 : (i) == 13 ? 14 : (i) == 14 ? 15 : -1) /**< Pin number for AF_PRS_CH3 location number i */
-#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : -1) /**< Pin number for AF_PRS_CH4 location number i */
-#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 9 : -1) /**< Pin number for AF_PRS_CH5 location number i */
-#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 12 : (i) == 15 ? 13 : (i) == 16 ? 14 : (i) == 17 ? 15 : -1) /**< Pin number for AF_PRS_CH6 location number i */
-#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 0 : -1) /**< Pin number for AF_PRS_CH7 location number i */
-#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 0 : (i) == 10 ? 1 : -1) /**< Pin number for AF_PRS_CH8 location number i */
-#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 0 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : -1) /**< Pin number for AF_PRS_CH9 location number i */
-#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 10 : (i) == 5 ? 11 : -1) /**< Pin number for AF_PRS_CH10 location number i */
-#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 6 : -1) /**< Pin number for AF_PRS_CH11 location number i */
-#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */
-#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */
-#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */
-#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */
-#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */
-#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */
-#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */
-#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */
-#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */
-#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */
-#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */
-#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */
-#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */
-#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */
-#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */
-#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */
-#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? -1 : (i) == 7 ? -1 : (i) == 8 ? -1 : (i) == 9 ? -1 : (i) == 10 ? -1 : (i) == 11 ? -1 : (i) == 12 ? -1 : (i) == 13 ? -1 : (i) == 14 ? -1 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? -1 : (i) == 21 ? -1 : (i) == 22 ? -1 : (i) == 23 ? -1 : (i) == 24 ? -1 : (i) == 25 ? -1 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */
-#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? -1 : (i) == 5 ? -1 : (i) == 6 ? -1 : (i) == 7 ? -1 : (i) == 8 ? -1 : (i) == 9 ? -1 : (i) == 10 ? -1 : (i) == 11 ? -1 : (i) == 12 ? -1 : (i) == 13 ? 11 : (i) == 14 ? 12 : (i) == 15 ? 13 : (i) == 16 ? 14 : (i) == 17 ? 15 : (i) == 18 ? -1 : (i) == 19 ? -1 : (i) == 20 ? -1 : (i) == 21 ? -1 : (i) == 22 ? -1 : (i) == 23 ? -1 : (i) == 24 ? 6 : (i) == 25 ? 7 : (i) == 26 ? 8 : (i) == 27 ? 9 : (i) == 28 ? 10 : (i) == 29 ? 11 : (i) == 30 ? -1 : (i) == 31 ? 9 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */
-#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? -1 : (i) == 5 ? -1 : (i) == 6 ? -1 : (i) == 7 ? -1 : (i) == 8 ? -1 : (i) == 9 ? -1 : (i) == 10 ? -1 : (i) == 11 ? 11 : (i) == 12 ? 12 : (i) == 13 ? 13 : (i) == 14 ? 14 : (i) == 15 ? 15 : (i) == 16 ? -1 : (i) == 17 ? -1 : (i) == 18 ? -1 : (i) == 19 ? -1 : (i) == 20 ? -1 : (i) == 21 ? -1 : (i) == 22 ? 6 : (i) == 23 ? 7 : (i) == 24 ? 8 : (i) == 25 ? 9 : (i) == 26 ? 10 : (i) == 27 ? 11 : (i) == 28 ? -1 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */
-#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */
-#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? -1 : (i) == 1 ? -1 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? -1 : (i) == 5 ? -1 : (i) == 6 ? -1 : (i) == 7 ? 11 : (i) == 8 ? 12 : (i) == 9 ? 13 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? -1 : (i) == 13 ? -1 : (i) == 14 ? -1 : (i) == 15 ? -1 : (i) == 16 ? -1 : (i) == 17 ? -1 : (i) == 18 ? 6 : (i) == 19 ? 7 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? -1 : (i) == 25 ? 9 : (i) == 26 ? 10 : (i) == 27 ? 11 : (i) == 28 ? 12 : (i) == 29 ? 13 : (i) == 30 ? 14 : (i) == 31 ? 15 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */
-#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? -1 : (i) == 1 ? -1 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? -1 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? -1 : (i) == 11 ? -1 : (i) == 12 ? -1 : (i) == 13 ? -1 : (i) == 14 ? -1 : (i) == 15 ? -1 : (i) == 16 ? 6 : (i) == 17 ? 7 : (i) == 18 ? 8 : (i) == 19 ? 9 : (i) == 20 ? 10 : (i) == 21 ? 11 : (i) == 22 ? -1 : (i) == 23 ? 9 : (i) == 24 ? 10 : (i) == 25 ? 11 : (i) == 26 ? 12 : (i) == 27 ? 13 : (i) == 28 ? 14 : (i) == 29 ? 15 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */
-#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? -1 : (i) == 1 ? -1 : (i) == 2 ? -1 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? -1 : (i) == 9 ? -1 : (i) == 10 ? -1 : (i) == 11 ? -1 : (i) == 12 ? -1 : (i) == 13 ? -1 : (i) == 14 ? 6 : (i) == 15 ? 7 : (i) == 16 ? 8 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? -1 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */
-#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */
-#define AF_USART0_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_USART0_TX location number i */
-#define AF_USART0_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_USART0_RX location number i */
-#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) /**< Pin number for AF_USART0_CLK location number i */
-#define AF_USART0_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) /**< Pin number for AF_USART0_CS location number i */
-#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) /**< Pin number for AF_USART0_CTS location number i */
-#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1) /**< Pin number for AF_USART0_RTS location number i */
-#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_USART1_TX location number i */
-#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_USART1_RX location number i */
-#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) /**< Pin number for AF_USART1_CLK location number i */
-#define AF_USART1_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */
-#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) /**< Pin number for AF_USART1_CTS location number i */
-#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1) /**< Pin number for AF_USART1_RTS location number i */
-#define AF_USART2_TX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? -1 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? -1 : (i) == 5 ? -1 : (i) == 6 ? -1 : (i) == 7 ? -1 : (i) == 8 ? -1 : (i) == 9 ? -1 : (i) == 10 ? -1 : (i) == 11 ? -1 : (i) == 12 ? -1 : (i) == 13 ? -1 : (i) == 14 ? 0 : (i) == 15 ? 1 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 6 : (i) == 20 ? 7 : (i) == 21 ? -1 : (i) == 22 ? -1 : (i) == 23 ? -1 : (i) == 24 ? -1 : (i) == 25 ? -1 : (i) == 26 ? -1 : (i) == 27 ? -1 : (i) == 28 ? -1 : (i) == 29 ? -1 : (i) == 30 ? -1 : (i) == 31 ? -1 : -1) /**< Pin number for AF_USART2_TX location number i */
-#define AF_USART2_RX_PIN(i) ((i) == 0 ? -1 : (i) == 1 ? -1 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? -1 : (i) == 5 ? -1 : (i) == 6 ? -1 : (i) == 7 ? -1 : (i) == 8 ? -1 : (i) == 9 ? -1 : (i) == 10 ? -1 : (i) == 11 ? -1 : (i) == 12 ? -1 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 6 : (i) == 19 ? 7 : (i) == 20 ? -1 : (i) == 21 ? -1 : (i) == 22 ? -1 : (i) == 23 ? -1 : (i) == 24 ? -1 : (i) == 25 ? -1 : (i) == 26 ? -1 : (i) == 27 ? -1 : (i) == 28 ? -1 : (i) == 29 ? -1 : (i) == 30 ? -1 : (i) == 31 ? 5 : -1) /**< Pin number for AF_USART2_RX location number i */
-#define AF_USART2_CLK_PIN(i) ((i) == 0 ? -1 : (i) == 1 ? -1 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? -1 : (i) == 5 ? -1 : (i) == 6 ? -1 : (i) == 7 ? -1 : (i) == 8 ? -1 : (i) == 9 ? -1 : (i) == 10 ? -1 : (i) == 11 ? -1 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 3 : (i) == 15 ? 4 : (i) == 16 ? 5 : (i) == 17 ? 6 : (i) == 18 ? 7 : (i) == 19 ? -1 : (i) == 20 ? -1 : (i) == 21 ? -1 : (i) == 22 ? -1 : (i) == 23 ? -1 : (i) == 24 ? -1 : (i) == 25 ? -1 : (i) == 26 ? -1 : (i) == 27 ? -1 : (i) == 28 ? -1 : (i) == 29 ? -1 : (i) == 30 ? 5 : (i) == 31 ? -1 : -1) /**< Pin number for AF_USART2_CLK location number i */
-#define AF_USART2_CS_PIN(i) ((i) == 0 ? -1 : (i) == 1 ? -1 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? -1 : (i) == 5 ? -1 : (i) == 6 ? -1 : (i) == 7 ? -1 : (i) == 8 ? -1 : (i) == 9 ? -1 : (i) == 10 ? -1 : (i) == 11 ? 0 : (i) == 12 ? 1 : (i) == 13 ? 3 : (i) == 14 ? 4 : (i) == 15 ? 5 : (i) == 16 ? 6 : (i) == 17 ? 7 : (i) == 18 ? -1 : (i) == 19 ? -1 : (i) == 20 ? -1 : (i) == 21 ? -1 : (i) == 22 ? -1 : (i) == 23 ? -1 : (i) == 24 ? -1 : (i) == 25 ? -1 : (i) == 26 ? -1 : (i) == 27 ? -1 : (i) == 28 ? -1 : (i) == 29 ? 5 : (i) == 30 ? -1 : (i) == 31 ? -1 : -1) /**< Pin number for AF_USART2_CS location number i */
-#define AF_USART2_CTS_PIN(i) ((i) == 0 ? -1 : (i) == 1 ? -1 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? -1 : (i) == 5 ? -1 : (i) == 6 ? -1 : (i) == 7 ? -1 : (i) == 8 ? -1 : (i) == 9 ? -1 : (i) == 10 ? 0 : (i) == 11 ? 1 : (i) == 12 ? 3 : (i) == 13 ? 4 : (i) == 14 ? 5 : (i) == 15 ? 6 : (i) == 16 ? 7 : (i) == 17 ? -1 : (i) == 18 ? -1 : (i) == 19 ? -1 : (i) == 20 ? -1 : (i) == 21 ? -1 : (i) == 22 ? -1 : (i) == 23 ? -1 : (i) == 24 ? -1 : (i) == 25 ? -1 : (i) == 26 ? -1 : (i) == 27 ? -1 : (i) == 28 ? 5 : (i) == 29 ? -1 : (i) == 30 ? -1 : (i) == 31 ? -1 : -1) /**< Pin number for AF_USART2_CTS location number i */
-#define AF_USART2_RTS_PIN(i) ((i) == 0 ? -1 : (i) == 1 ? -1 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? -1 : (i) == 5 ? -1 : (i) == 6 ? -1 : (i) == 7 ? -1 : (i) == 8 ? -1 : (i) == 9 ? 0 : (i) == 10 ? 1 : (i) == 11 ? 3 : (i) == 12 ? 4 : (i) == 13 ? 5 : (i) == 14 ? 6 : (i) == 15 ? 7 : (i) == 16 ? -1 : (i) == 17 ? -1 : (i) == 18 ? -1 : (i) == 19 ? -1 : (i) == 20 ? -1 : (i) == 21 ? -1 : (i) == 22 ? -1 : (i) == 23 ? -1 : (i) == 24 ? -1 : (i) == 25 ? -1 : (i) == 26 ? -1 : (i) == 27 ? 5 : (i) == 28 ? -1 : (i) == 29 ? -1 : (i) == 30 ? -1 : (i) == 31 ? -1 : -1) /**< Pin number for AF_USART2_RTS location number i */
-#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_LEUART0_TX location number i */
-#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_LEUART0_RX location number i */
-#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */
-#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */
-#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */
-#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */
-#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_I2C0_SDA location number i */
-#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_I2C0_SCL location number i */
-#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? -1 : (i) == 1 ? -1 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? -1 : (i) == 5 ? -1 : (i) == 6 ? -1 : (i) == 7 ? -1 : (i) == 8 ? -1 : (i) == 9 ? -1 : (i) == 10 ? -1 : (i) == 11 ? -1 : (i) == 12 ? -1 : (i) == 13 ? -1 : (i) == 14 ? -1 : (i) == 15 ? -1 : (i) == 16 ? -1 : (i) == 17 ? -1 : (i) == 18 ? -1 : (i) == 19 ? 10 : (i) == 20 ? 11 : (i) == 21 ? -1 : (i) == 22 ? -1 : (i) == 23 ? -1 : (i) == 24 ? -1 : (i) == 25 ? -1 : (i) == 26 ? -1 : (i) == 27 ? -1 : (i) == 28 ? -1 : (i) == 29 ? -1 : (i) == 30 ? -1 : (i) == 31 ? -1 : -1) /**< Pin number for AF_I2C1_SDA location number i */
-#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? -1 : (i) == 1 ? -1 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? -1 : (i) == 5 ? -1 : (i) == 6 ? -1 : (i) == 7 ? -1 : (i) == 8 ? -1 : (i) == 9 ? -1 : (i) == 10 ? -1 : (i) == 11 ? -1 : (i) == 12 ? -1 : (i) == 13 ? -1 : (i) == 14 ? -1 : (i) == 15 ? -1 : (i) == 16 ? -1 : (i) == 17 ? -1 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? -1 : (i) == 21 ? -1 : (i) == 22 ? -1 : (i) == 23 ? -1 : (i) == 24 ? -1 : (i) == 25 ? -1 : (i) == 26 ? -1 : (i) == 27 ? -1 : (i) == 28 ? -1 : (i) == 29 ? -1 : (i) == 30 ? -1 : (i) == 31 ? -1 : -1) /**< Pin number for AF_I2C1_SCL location number i */
-#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_ACMP0_OUT location number i */
-#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_ACMP1_OUT location number i */
-#define AF_LESENSE_CH0_PIN(i) (-1) /**< Pin number for AF_LESENSE_CH0 location number i */
-#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */
-#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */
-#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */
-#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */
-#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */
-#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */
-#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */
-#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */
-#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */
-#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */
-#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */
-#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */
-#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */
-#define AF_LESENSE_CH14_PIN(i) (-1) /**< Pin number for AF_LESENSE_CH14 location number i */
-#define AF_LESENSE_CH15_PIN(i) (-1) /**< Pin number for AF_LESENSE_CH15 location number i */
-#define AF_LESENSE_ALTEX0_PIN(i) (-1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */
-#define AF_LESENSE_ALTEX1_PIN(i) (-1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */
-#define AF_LESENSE_ALTEX2_PIN(i) (-1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */
-#define AF_LESENSE_ALTEX3_PIN(i) (-1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */
-#define AF_LESENSE_ALTEX4_PIN(i) (-1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */
-#define AF_LESENSE_ALTEX5_PIN(i) (-1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */
-#define AF_LESENSE_ALTEX6_PIN(i) (-1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */
-#define AF_LESENSE_ALTEX7_PIN(i) (-1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */
-#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_DBG_TDI location number i */
-#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */
-#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 11 : -1) /**< Pin number for AF_DBG_SWV location number i */
-#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */
-#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */
-#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? -1 : (i) == 1 ? 5 : (i) == 2 ? -1 : (i) == 3 ? 6 : -1) /**< Pin number for AF_ETM_TCLK location number i */
-#define AF_ETM_TD0_PIN(i) ((i) == 0 ? -1 : (i) == 1 ? -1 : (i) == 2 ? -1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_ETM_TD0 location number i */
-#define AF_ETM_TD1_PIN(i) ((i) == 0 ? -1 : (i) == 1 ? -1 : (i) == 2 ? -1 : (i) == 3 ? 8 : -1) /**< Pin number for AF_ETM_TD1 location number i */
-#define AF_ETM_TD2_PIN(i) ((i) == 0 ? -1 : (i) == 1 ? -1 : (i) == 2 ? -1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_ETM_TD2 location number i */
-#define AF_ETM_TD3_PIN(i) ((i) == 0 ? -1 : (i) == 1 ? -1 : (i) == 2 ? -1 : (i) == 3 ? 10 : -1) /**< Pin number for AF_ETM_TD3 location number i */
+#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 15 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 7 : -1) /**< Pin number for AF_CMU_CLK0 location number i */
+#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 14 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 10 : (i) == 5 ? 15 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_CMU_CLK1 location number i */
+#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */
+#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : -1) /**< Pin number for AF_PRS_CH0 location number i */
+#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 0 : -1) /**< Pin number for AF_PRS_CH1 location number i */
+#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Pin number for AF_PRS_CH2 location number i */
+#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 11 : (i) == 11 ? 12 : (i) == 12 ? 13 : (i) == 13 ? 14 : (i) == 14 ? 15 : -1) /**< Pin number for AF_PRS_CH3 location number i */
+#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : -1) /**< Pin number for AF_PRS_CH4 location number i */
+#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 9 : -1) /**< Pin number for AF_PRS_CH5 location number i */
+#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 12 : (i) == 15 ? 13 : (i) == 16 ? 14 : (i) == 17 ? 15 : -1) /**< Pin number for AF_PRS_CH6 location number i */
+#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 0 : -1) /**< Pin number for AF_PRS_CH7 location number i */
+#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 0 : (i) == 10 ? 1 : -1) /**< Pin number for AF_PRS_CH8 location number i */
+#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 0 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : -1) /**< Pin number for AF_PRS_CH9 location number i */
+#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 10 : (i) == 5 ? 11 : -1) /**< Pin number for AF_PRS_CH10 location number i */
+#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 6 : -1) /**< Pin number for AF_PRS_CH11 location number i */
+#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */
+#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */
+#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */
+#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */
+#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */
+#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */
+#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */
+#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */
+#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */
+#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */
+#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */
+#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */
+#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */
+#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */
+#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */
+#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */
+#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */
+#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 9 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 12 : (i) == 15 ? 13 : (i) == 16 ? 14 : (i) == 17 ? 15 : (i) == 18 ? 0 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 3 : (i) == 22 ? 4 : (i) == 23 ? 5 : (i) == 24 ? 6 : (i) == 25 ? 7 : (i) == 26 ? 8 : (i) == 27 ? 9 : (i) == 28 ? 10 : (i) == 29 ? 11 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */
+#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 8 : (i) == 5 ? 9 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 12 : (i) == 13 ? 13 : (i) == 14 ? 14 : (i) == 15 ? 15 : (i) == 16 ? 0 : (i) == 17 ? 1 : (i) == 18 ? 2 : (i) == 19 ? 3 : (i) == 20 ? 4 : (i) == 21 ? 5 : (i) == 22 ? 6 : (i) == 23 ? 7 : (i) == 24 ? 8 : (i) == 25 ? 9 : (i) == 26 ? 10 : (i) == 27 ? 11 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */
+#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */
+#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 8 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 11 : (i) == 8 ? 12 : (i) == 9 ? 13 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 6 : (i) == 19 ? 7 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 8 : (i) == 25 ? 9 : (i) == 26 ? 10 : (i) == 27 ? 11 : (i) == 28 ? 12 : (i) == 29 ? 13 : (i) == 30 ? 14 : (i) == 31 ? 15 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */
+#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 10 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 0 : (i) == 11 ? 1 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 4 : (i) == 15 ? 5 : (i) == 16 ? 6 : (i) == 17 ? 7 : (i) == 18 ? 8 : (i) == 19 ? 9 : (i) == 20 ? 10 : (i) == 21 ? 11 : (i) == 22 ? 8 : (i) == 23 ? 9 : (i) == 24 ? 10 : (i) == 25 ? 11 : (i) == 26 ? 12 : (i) == 27 ? 13 : (i) == 28 ? 14 : (i) == 29 ? 15 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */
+#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 0 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 3 : (i) == 12 ? 4 : (i) == 13 ? 5 : (i) == 14 ? 6 : (i) == 15 ? 7 : (i) == 16 ? 8 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */
+#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */
+#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 3 : (i) == 8 ? 4 : (i) == 9 ? 5 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 8 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */
+#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 5 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 8 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */
+#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */
+#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 9 : (i) == 8 ? 10 : (i) == 9 ? 11 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 12 : (i) == 15 ? 13 : (i) == 16 ? 14 : (i) == 17 ? 15 : (i) == 18 ? 0 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 3 : (i) == 22 ? 4 : (i) == 23 ? 5 : (i) == 24 ? 6 : (i) == 25 ? 7 : (i) == 26 ? 8 : (i) == 27 ? 9 : (i) == 28 ? 10 : (i) == 29 ? 11 : (i) == 30 ? 12 : (i) == 31 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */
+#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */
+#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */
+#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */
+#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */
+#define AF_USART0_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_USART0_TX location number i */
+#define AF_USART0_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_USART0_RX location number i */
+#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) /**< Pin number for AF_USART0_CLK location number i */
+#define AF_USART0_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) /**< Pin number for AF_USART0_CS location number i */
+#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) /**< Pin number for AF_USART0_CTS location number i */
+#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1) /**< Pin number for AF_USART0_RTS location number i */
+#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_USART1_TX location number i */
+#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_USART1_RX location number i */
+#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) /**< Pin number for AF_USART1_CLK location number i */
+#define AF_USART1_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */
+#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) /**< Pin number for AF_USART1_CTS location number i */
+#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1) /**< Pin number for AF_USART1_RTS location number i */
+#define AF_USART2_TX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 9 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 3 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 0 : (i) == 15 ? 1 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 6 : (i) == 20 ? 7 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) /**< Pin number for AF_USART2_TX location number i */
+#define AF_USART2_RX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 3 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 6 : (i) == 19 ? 7 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 5 : -1) /**< Pin number for AF_USART2_RX location number i */
+#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 3 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 3 : (i) == 15 ? 4 : (i) == 16 ? 5 : (i) == 17 ? 6 : (i) == 18 ? 7 : (i) == 19 ? 8 : (i) == 20 ? 9 : (i) == 21 ? 10 : (i) == 22 ? 11 : (i) == 23 ? 12 : (i) == 24 ? 13 : (i) == 25 ? 14 : (i) == 26 ? 15 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 5 : (i) == 31 ? 6 : -1) /**< Pin number for AF_USART2_CLK location number i */
+#define AF_USART2_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 0 : (i) == 12 ? 1 : (i) == 13 ? 3 : (i) == 14 ? 4 : (i) == 15 ? 5 : (i) == 16 ? 6 : (i) == 17 ? 7 : (i) == 18 ? 8 : (i) == 19 ? 9 : (i) == 20 ? 10 : (i) == 21 ? 11 : (i) == 22 ? 12 : (i) == 23 ? 13 : (i) == 24 ? 14 : (i) == 25 ? 15 : (i) == 26 ? 0 : (i) == 27 ? 1 : (i) == 28 ? 2 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_USART2_CS location number i */
+#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 0 : (i) == 11 ? 1 : (i) == 12 ? 3 : (i) == 13 ? 4 : (i) == 14 ? 5 : (i) == 15 ? 6 : (i) == 16 ? 7 : (i) == 17 ? 8 : (i) == 18 ? 9 : (i) == 19 ? 10 : (i) == 20 ? 11 : (i) == 21 ? 12 : (i) == 22 ? 13 : (i) == 23 ? 14 : (i) == 24 ? 15 : (i) == 25 ? 0 : (i) == 26 ? 1 : (i) == 27 ? 2 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 8 : -1) /**< Pin number for AF_USART2_CTS location number i */
+#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 9 : (i) == 8 ? 10 : (i) == 9 ? 0 : (i) == 10 ? 1 : (i) == 11 ? 3 : (i) == 12 ? 4 : (i) == 13 ? 5 : (i) == 14 ? 6 : (i) == 15 ? 7 : (i) == 16 ? 8 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1) /**< Pin number for AF_USART2_RTS location number i */
+#define AF_USART3_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 2 : (i) == 9 ? 3 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 14 : (i) == 17 ? 15 : (i) == 18 ? 0 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 3 : (i) == 22 ? 4 : (i) == 23 ? 5 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) /**< Pin number for AF_USART3_TX location number i */
+#define AF_USART3_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 2 : (i) == 8 ? 3 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 14 : (i) == 16 ? 15 : (i) == 17 ? 0 : (i) == 18 ? 1 : (i) == 19 ? 2 : (i) == 20 ? 3 : (i) == 21 ? 4 : (i) == 22 ? 5 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 8 : -1) /**< Pin number for AF_USART3_RX location number i */
+#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 2 : (i) == 7 ? 3 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 14 : (i) == 15 ? 15 : (i) == 16 ? 0 : (i) == 17 ? 1 : (i) == 18 ? 2 : (i) == 19 ? 3 : (i) == 20 ? 4 : (i) == 21 ? 5 : (i) == 22 ? 11 : (i) == 23 ? 12 : (i) == 24 ? 13 : (i) == 25 ? 14 : (i) == 26 ? 15 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1) /**< Pin number for AF_USART3_CLK location number i */
+#define AF_USART3_CS_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 13 : (i) == 3 ? 14 : (i) == 4 ? 15 : (i) == 5 ? 2 : (i) == 6 ? 3 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 14 : (i) == 14 ? 15 : (i) == 15 ? 0 : (i) == 16 ? 1 : (i) == 17 ? 2 : (i) == 18 ? 3 : (i) == 19 ? 4 : (i) == 20 ? 5 : (i) == 21 ? 11 : (i) == 22 ? 12 : (i) == 23 ? 13 : (i) == 24 ? 14 : (i) == 25 ? 15 : (i) == 26 ? 0 : (i) == 27 ? 1 : (i) == 28 ? 2 : (i) == 29 ? 8 : (i) == 30 ? 9 : (i) == 31 ? 10 : -1) /**< Pin number for AF_USART3_CS location number i */
+#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 14 : (i) == 13 ? 15 : (i) == 14 ? 0 : (i) == 15 ? 1 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 4 : (i) == 19 ? 5 : (i) == 20 ? 11 : (i) == 21 ? 12 : (i) == 22 ? 13 : (i) == 23 ? 14 : (i) == 24 ? 15 : (i) == 25 ? 0 : (i) == 26 ? 1 : (i) == 27 ? 2 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1) /**< Pin number for AF_USART3_CTS location number i */
+#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 11 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 8 : (i) == 28 ? 9 : (i) == 29 ? 10 : (i) == 30 ? 11 : (i) == 31 ? 12 : -1) /**< Pin number for AF_USART3_RTS location number i */
+#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_LEUART0_TX location number i */
+#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_LEUART0_RX location number i */
+#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */
+#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */
+#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */
+#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */
+#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 6 : (i) == 20 ? 7 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */
+#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 6 : (i) == 19 ? 7 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 6 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */
+#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 10 : (i) == 20 ? 11 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */
+#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 6 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */
+#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_I2C0_SDA location number i */
+#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) /**< Pin number for AF_I2C0_SCL location number i */
+#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 10 : (i) == 20 ? 11 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */
+#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 6 : -1) /**< Pin number for AF_I2C1_SCL location number i */
+#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_ACMP0_OUT location number i */
+#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) /**< Pin number for AF_ACMP1_OUT location number i */
+#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */
+#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */
+#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */
+#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */
+#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */
+#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */
+#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */
+#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */
+#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */
+#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */
+#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */
+#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */
+#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */
+#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */
+#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */
+#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */
+#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */
+#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */
+#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */
+#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */
+#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */
+#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */
+#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */
+#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */
+#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_DBG_TDI location number i */
+#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */
+#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 11 : -1) /**< Pin number for AF_DBG_SWV location number i */
+#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */
+#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */
+#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 6 : -1) /**< Pin number for AF_ETM_TCLK location number i */
+#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 7 : -1) /**< Pin number for AF_ETM_TD0 location number i */
+#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 8 : -1) /**< Pin number for AF_ETM_TD1 location number i */
+#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 9 : -1) /**< Pin number for AF_ETM_TD2 location number i */
+#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 8 : (i) == 3 ? 10 : -1) /**< Pin number for AF_ETM_TD3 location number i */
/** @} */
-/** @} End of group EFR32FG13P_AF_Pins */
+/** @} End of group EFR32FG12P_AF_Pins */
/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_af_ports.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_af_ports.h
similarity index 60%
rename from mcu/efr/common/vendor/efr32fg13/efr32fg13p_af_ports.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_af_ports.h
index a6394bd5..61ae2340 100644
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_af_ports.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_af_ports.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efr32fg13p_af_ports.h
- * @brief EFR32FG13P_AF_PORTS register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+/***************************************************************************//**
+ * @file
+ * @brief EFR32FG12P_AF_PORTS register and bit field definitions
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#if defined(__ICCARM__)
#pragma system_include /* Treat file as system include file. */
@@ -36,121 +34,139 @@
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_Alternate_Function Alternate Function
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_Alternate_Function Alternate Function
* @{
- * @defgroup EFR32FG13P_AF_Ports Alternate Function Ports
+ * @defgroup EFR32FG12P_AF_Ports Alternate Function Ports
* @{
- *****************************************************************************/
+ ******************************************************************************/
-#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_CMU_CLK0 location number i */
-#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_CMU_CLK1 location number i */
-#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? -1 : (i) == 4 ? 0 : -1) /**< Port number for AF_CMU_CLKI0 location number i */
-#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : -1) /**< Port number for AF_PRS_CH0 location number i */
-#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_PRS_CH1 location number i */
-#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_PRS_CH2 location number i */
-#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : (i) == 8 ? 3 : (i) == 9 ? 3 : (i) == 10 ? 3 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : -1) /**< Port number for AF_PRS_CH3 location number i */
-#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : -1) /**< Port number for AF_PRS_CH4 location number i */
-#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */
-#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : -1) /**< Port number for AF_PRS_CH6 location number i */
-#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 0 : -1) /**< Port number for AF_PRS_CH7 location number i */
-#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 0 : (i) == 10 ? 0 : -1) /**< Port number for AF_PRS_CH8 location number i */
-#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 0 : (i) == 9 ? 0 : (i) == 10 ? 0 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : -1) /**< Port number for AF_PRS_CH9 location number i */
-#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_PRS_CH10 location number i */
-#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_PRS_CH11 location number i */
-#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_TIMER0_CC0 location number i */
-#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */
-#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */
-#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */
-#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */
-#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */
-#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */
-#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */
-#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_TIMER1_CC0 location number i */
-#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER1_CC1 location number i */
-#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER1_CC2 location number i */
-#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER1_CC3 location number i */
-#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */
-#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */
-#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */
-#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */
-#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? -1 : (i) == 7 ? -1 : (i) == 8 ? -1 : (i) == 9 ? -1 : (i) == 10 ? -1 : (i) == 11 ? -1 : (i) == 12 ? -1 : (i) == 13 ? -1 : (i) == 14 ? -1 : (i) == 15 ? 1 : (i) == 16 ? 1 : (i) == 17 ? 1 : (i) == 18 ? 1 : (i) == 19 ? 1 : (i) == 20 ? -1 : (i) == 21 ? -1 : (i) == 22 ? -1 : (i) == 23 ? -1 : (i) == 24 ? -1 : (i) == 25 ? -1 : (i) == 26 ? 2 : (i) == 27 ? 2 : (i) == 28 ? 2 : (i) == 29 ? 2 : (i) == 30 ? 2 : (i) == 31 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */
-#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? -1 : (i) == 5 ? -1 : (i) == 6 ? -1 : (i) == 7 ? -1 : (i) == 8 ? -1 : (i) == 9 ? -1 : (i) == 10 ? -1 : (i) == 11 ? -1 : (i) == 12 ? -1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 1 : (i) == 17 ? 1 : (i) == 18 ? -1 : (i) == 19 ? -1 : (i) == 20 ? -1 : (i) == 21 ? -1 : (i) == 22 ? -1 : (i) == 23 ? -1 : (i) == 24 ? 2 : (i) == 25 ? 2 : (i) == 26 ? 2 : (i) == 27 ? 2 : (i) == 28 ? 2 : (i) == 29 ? 2 : (i) == 30 ? -1 : (i) == 31 ? 3 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */
-#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? -1 : (i) == 5 ? -1 : (i) == 6 ? -1 : (i) == 7 ? -1 : (i) == 8 ? -1 : (i) == 9 ? -1 : (i) == 10 ? -1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? -1 : (i) == 17 ? -1 : (i) == 18 ? -1 : (i) == 19 ? -1 : (i) == 20 ? -1 : (i) == 21 ? -1 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 2 : (i) == 25 ? 2 : (i) == 26 ? 2 : (i) == 27 ? 2 : (i) == 28 ? -1 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */
-#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */
-#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? -1 : (i) == 1 ? -1 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? -1 : (i) == 5 ? -1 : (i) == 6 ? -1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? -1 : (i) == 13 ? -1 : (i) == 14 ? -1 : (i) == 15 ? -1 : (i) == 16 ? -1 : (i) == 17 ? -1 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? -1 : (i) == 25 ? 3 : (i) == 26 ? 3 : (i) == 27 ? 3 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */
-#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? -1 : (i) == 1 ? -1 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? -1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? -1 : (i) == 11 ? -1 : (i) == 12 ? -1 : (i) == 13 ? -1 : (i) == 14 ? -1 : (i) == 15 ? -1 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? -1 : (i) == 23 ? 3 : (i) == 24 ? 3 : (i) == 25 ? 3 : (i) == 26 ? 3 : (i) == 27 ? 3 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */
-#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? -1 : (i) == 1 ? -1 : (i) == 2 ? -1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? -1 : (i) == 9 ? -1 : (i) == 10 ? -1 : (i) == 11 ? -1 : (i) == 12 ? -1 : (i) == 13 ? -1 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? -1 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 3 : (i) == 25 ? 3 : (i) == 26 ? 3 : (i) == 27 ? 3 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */
-#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */
-#define AF_USART0_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_USART0_TX location number i */
-#define AF_USART0_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART0_RX location number i */
-#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART0_CLK location number i */
-#define AF_USART0_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART0_CS location number i */
-#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART0_CTS location number i */
-#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART0_RTS location number i */
-#define AF_USART1_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_USART1_TX location number i */
-#define AF_USART1_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */
-#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART1_CLK location number i */
-#define AF_USART1_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART1_CS location number i */
-#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART1_CTS location number i */
-#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART1_RTS location number i */
-#define AF_USART2_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? -1 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? -1 : (i) == 5 ? -1 : (i) == 6 ? -1 : (i) == 7 ? -1 : (i) == 8 ? -1 : (i) == 9 ? -1 : (i) == 10 ? -1 : (i) == 11 ? -1 : (i) == 12 ? -1 : (i) == 13 ? -1 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? -1 : (i) == 22 ? -1 : (i) == 23 ? -1 : (i) == 24 ? -1 : (i) == 25 ? -1 : (i) == 26 ? -1 : (i) == 27 ? -1 : (i) == 28 ? -1 : (i) == 29 ? -1 : (i) == 30 ? -1 : (i) == 31 ? -1 : -1) /**< Port number for AF_USART2_TX location number i */
-#define AF_USART2_RX_PORT(i) ((i) == 0 ? -1 : (i) == 1 ? -1 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? -1 : (i) == 5 ? -1 : (i) == 6 ? -1 : (i) == 7 ? -1 : (i) == 8 ? -1 : (i) == 9 ? -1 : (i) == 10 ? -1 : (i) == 11 ? -1 : (i) == 12 ? -1 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? -1 : (i) == 21 ? -1 : (i) == 22 ? -1 : (i) == 23 ? -1 : (i) == 24 ? -1 : (i) == 25 ? -1 : (i) == 26 ? -1 : (i) == 27 ? -1 : (i) == 28 ? -1 : (i) == 29 ? -1 : (i) == 30 ? -1 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART2_RX location number i */
-#define AF_USART2_CLK_PORT(i) ((i) == 0 ? -1 : (i) == 1 ? -1 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? -1 : (i) == 5 ? -1 : (i) == 6 ? -1 : (i) == 7 ? -1 : (i) == 8 ? -1 : (i) == 9 ? -1 : (i) == 10 ? -1 : (i) == 11 ? -1 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? -1 : (i) == 20 ? -1 : (i) == 21 ? -1 : (i) == 22 ? -1 : (i) == 23 ? -1 : (i) == 24 ? -1 : (i) == 25 ? -1 : (i) == 26 ? -1 : (i) == 27 ? -1 : (i) == 28 ? -1 : (i) == 29 ? -1 : (i) == 30 ? 0 : (i) == 31 ? -1 : -1) /**< Port number for AF_USART2_CLK location number i */
-#define AF_USART2_CS_PORT(i) ((i) == 0 ? -1 : (i) == 1 ? -1 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? -1 : (i) == 5 ? -1 : (i) == 6 ? -1 : (i) == 7 ? -1 : (i) == 8 ? -1 : (i) == 9 ? -1 : (i) == 10 ? -1 : (i) == 11 ? 5 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? -1 : (i) == 19 ? -1 : (i) == 20 ? -1 : (i) == 21 ? -1 : (i) == 22 ? -1 : (i) == 23 ? -1 : (i) == 24 ? -1 : (i) == 25 ? -1 : (i) == 26 ? -1 : (i) == 27 ? -1 : (i) == 28 ? -1 : (i) == 29 ? 0 : (i) == 30 ? -1 : (i) == 31 ? -1 : -1) /**< Port number for AF_USART2_CS location number i */
-#define AF_USART2_CTS_PORT(i) ((i) == 0 ? -1 : (i) == 1 ? -1 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? -1 : (i) == 5 ? -1 : (i) == 6 ? -1 : (i) == 7 ? -1 : (i) == 8 ? -1 : (i) == 9 ? -1 : (i) == 10 ? 5 : (i) == 11 ? 5 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? -1 : (i) == 18 ? -1 : (i) == 19 ? -1 : (i) == 20 ? -1 : (i) == 21 ? -1 : (i) == 22 ? -1 : (i) == 23 ? -1 : (i) == 24 ? -1 : (i) == 25 ? -1 : (i) == 26 ? -1 : (i) == 27 ? -1 : (i) == 28 ? 0 : (i) == 29 ? -1 : (i) == 30 ? -1 : (i) == 31 ? -1 : -1) /**< Port number for AF_USART2_CTS location number i */
-#define AF_USART2_RTS_PORT(i) ((i) == 0 ? -1 : (i) == 1 ? -1 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? -1 : (i) == 5 ? -1 : (i) == 6 ? -1 : (i) == 7 ? -1 : (i) == 8 ? -1 : (i) == 9 ? 5 : (i) == 10 ? 5 : (i) == 11 ? 5 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? -1 : (i) == 17 ? -1 : (i) == 18 ? -1 : (i) == 19 ? -1 : (i) == 20 ? -1 : (i) == 21 ? -1 : (i) == 22 ? -1 : (i) == 23 ? -1 : (i) == 24 ? -1 : (i) == 25 ? -1 : (i) == 26 ? -1 : (i) == 27 ? 0 : (i) == 28 ? -1 : (i) == 29 ? -1 : (i) == 30 ? -1 : (i) == 31 ? -1 : -1) /**< Port number for AF_USART2_RTS location number i */
-#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_LEUART0_TX location number i */
-#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_LEUART0_RX location number i */
-#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */
-#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */
-#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_PCNT0_S0IN location number i */
-#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_PCNT0_S1IN location number i */
-#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_I2C0_SDA location number i */
-#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_I2C0_SCL location number i */
-#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? -1 : (i) == 1 ? -1 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? -1 : (i) == 5 ? -1 : (i) == 6 ? -1 : (i) == 7 ? -1 : (i) == 8 ? -1 : (i) == 9 ? -1 : (i) == 10 ? -1 : (i) == 11 ? -1 : (i) == 12 ? -1 : (i) == 13 ? -1 : (i) == 14 ? -1 : (i) == 15 ? -1 : (i) == 16 ? -1 : (i) == 17 ? -1 : (i) == 18 ? -1 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? -1 : (i) == 22 ? -1 : (i) == 23 ? -1 : (i) == 24 ? -1 : (i) == 25 ? -1 : (i) == 26 ? -1 : (i) == 27 ? -1 : (i) == 28 ? -1 : (i) == 29 ? -1 : (i) == 30 ? -1 : (i) == 31 ? -1 : -1) /**< Port number for AF_I2C1_SDA location number i */
-#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? -1 : (i) == 1 ? -1 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? -1 : (i) == 5 ? -1 : (i) == 6 ? -1 : (i) == 7 ? -1 : (i) == 8 ? -1 : (i) == 9 ? -1 : (i) == 10 ? -1 : (i) == 11 ? -1 : (i) == 12 ? -1 : (i) == 13 ? -1 : (i) == 14 ? -1 : (i) == 15 ? -1 : (i) == 16 ? -1 : (i) == 17 ? -1 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? -1 : (i) == 21 ? -1 : (i) == 22 ? -1 : (i) == 23 ? -1 : (i) == 24 ? -1 : (i) == 25 ? -1 : (i) == 26 ? -1 : (i) == 27 ? -1 : (i) == 28 ? -1 : (i) == 29 ? -1 : (i) == 30 ? -1 : (i) == 31 ? -1 : -1) /**< Port number for AF_I2C1_SCL location number i */
-#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_ACMP0_OUT location number i */
-#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_ACMP1_OUT location number i */
-#define AF_LESENSE_CH0_PORT(i) (-1) /**< Port number for AF_LESENSE_CH0 location number i */
-#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_CH1 location number i */
-#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_CH2 location number i */
-#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_CH3 location number i */
-#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_CH4 location number i */
-#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_CH5 location number i */
-#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_CH6 location number i */
-#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_CH7 location number i */
-#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_CH8 location number i */
-#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_CH9 location number i */
-#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_CH10 location number i */
-#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_CH11 location number i */
-#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_CH12 location number i */
-#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_CH13 location number i */
-#define AF_LESENSE_CH14_PORT(i) (-1) /**< Port number for AF_LESENSE_CH14 location number i */
-#define AF_LESENSE_CH15_PORT(i) (-1) /**< Port number for AF_LESENSE_CH15 location number i */
-#define AF_LESENSE_ALTEX0_PORT(i) (-1) /**< Port number for AF_LESENSE_ALTEX0 location number i */
-#define AF_LESENSE_ALTEX1_PORT(i) (-1) /**< Port number for AF_LESENSE_ALTEX1 location number i */
-#define AF_LESENSE_ALTEX2_PORT(i) (-1) /**< Port number for AF_LESENSE_ALTEX2 location number i */
-#define AF_LESENSE_ALTEX3_PORT(i) (-1) /**< Port number for AF_LESENSE_ALTEX3 location number i */
-#define AF_LESENSE_ALTEX4_PORT(i) (-1) /**< Port number for AF_LESENSE_ALTEX4 location number i */
-#define AF_LESENSE_ALTEX5_PORT(i) (-1) /**< Port number for AF_LESENSE_ALTEX5 location number i */
-#define AF_LESENSE_ALTEX6_PORT(i) (-1) /**< Port number for AF_LESENSE_ALTEX6 location number i */
-#define AF_LESENSE_ALTEX7_PORT(i) (-1) /**< Port number for AF_LESENSE_ALTEX7 location number i */
-#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */
-#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */
-#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : -1) /**< Port number for AF_DBG_SWV location number i */
-#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */
-#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */
-#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? -1 : (i) == 1 ? 0 : (i) == 2 ? -1 : (i) == 3 ? 2 : -1) /**< Port number for AF_ETM_TCLK location number i */
-#define AF_ETM_TD0_PORT(i) ((i) == 0 ? -1 : (i) == 1 ? -1 : (i) == 2 ? -1 : (i) == 3 ? 2 : -1) /**< Port number for AF_ETM_TD0 location number i */
-#define AF_ETM_TD1_PORT(i) ((i) == 0 ? -1 : (i) == 1 ? -1 : (i) == 2 ? -1 : (i) == 3 ? 2 : -1) /**< Port number for AF_ETM_TD1 location number i */
-#define AF_ETM_TD2_PORT(i) ((i) == 0 ? -1 : (i) == 1 ? -1 : (i) == 2 ? -1 : (i) == 3 ? 2 : -1) /**< Port number for AF_ETM_TD2 location number i */
-#define AF_ETM_TD3_PORT(i) ((i) == 0 ? -1 : (i) == 1 ? -1 : (i) == 2 ? -1 : (i) == 3 ? 2 : -1) /**< Port number for AF_ETM_TD3 location number i */
+#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_CMU_CLK0 location number i */
+#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_CMU_CLK1 location number i */
+#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 0 : -1) /**< Port number for AF_CMU_CLKI0 location number i */
+#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : -1) /**< Port number for AF_PRS_CH0 location number i */
+#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_PRS_CH1 location number i */
+#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_PRS_CH2 location number i */
+#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : (i) == 8 ? 3 : (i) == 9 ? 3 : (i) == 10 ? 3 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : -1) /**< Port number for AF_PRS_CH3 location number i */
+#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : -1) /**< Port number for AF_PRS_CH4 location number i */
+#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */
+#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : -1) /**< Port number for AF_PRS_CH6 location number i */
+#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 0 : -1) /**< Port number for AF_PRS_CH7 location number i */
+#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 0 : (i) == 10 ? 0 : -1) /**< Port number for AF_PRS_CH8 location number i */
+#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 0 : (i) == 9 ? 0 : (i) == 10 ? 0 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : -1) /**< Port number for AF_PRS_CH9 location number i */
+#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_PRS_CH10 location number i */
+#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_PRS_CH11 location number i */
+#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_TIMER0_CC0 location number i */
+#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */
+#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */
+#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */
+#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */
+#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */
+#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */
+#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */
+#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_TIMER1_CC0 location number i */
+#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER1_CC1 location number i */
+#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER1_CC2 location number i */
+#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_TIMER1_CC3 location number i */
+#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */
+#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */
+#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */
+#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */
+#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : (i) == 8 ? 0 : (i) == 9 ? 0 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 1 : (i) == 17 ? 1 : (i) == 18 ? 1 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 2 : (i) == 25 ? 2 : (i) == 26 ? 2 : (i) == 27 ? 2 : (i) == 28 ? 2 : (i) == 29 ? 2 : (i) == 30 ? 2 : (i) == 31 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */
+#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 1 : (i) == 17 ? 1 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 2 : (i) == 25 ? 2 : (i) == 26 ? 2 : (i) == 27 ? 2 : (i) == 28 ? 2 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */
+#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 2 : (i) == 25 ? 2 : (i) == 26 ? 2 : (i) == 27 ? 2 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */
+#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */
+#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 3 : (i) == 26 ? 3 : (i) == 27 ? 3 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */
+#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 3 : (i) == 25 ? 3 : (i) == 26 ? 3 : (i) == 27 ? 3 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */
+#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 3 : (i) == 25 ? 3 : (i) == 26 ? 3 : (i) == 27 ? 3 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */
+#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */
+#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */
+#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */
+#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */
+#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 3 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */
+#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */
+#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */
+#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */
+#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */
+#define AF_USART0_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_USART0_TX location number i */
+#define AF_USART0_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART0_RX location number i */
+#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART0_CLK location number i */
+#define AF_USART0_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART0_CS location number i */
+#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART0_CTS location number i */
+#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART0_RTS location number i */
+#define AF_USART1_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_USART1_TX location number i */
+#define AF_USART1_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */
+#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART1_CLK location number i */
+#define AF_USART1_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART1_CS location number i */
+#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART1_CTS location number i */
+#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART1_RTS location number i */
+#define AF_USART2_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 8 : (i) == 8 ? 8 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1) /**< Port number for AF_USART2_TX location number i */
+#define AF_USART2_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 8 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART2_RX location number i */
+#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART2_CLK location number i */
+#define AF_USART2_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 5 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART2_CS location number i */
+#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 5 : (i) == 11 ? 5 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART2_CTS location number i */
+#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 8 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 5 : (i) == 10 ? 5 : (i) == 11 ? 5 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 10 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) /**< Port number for AF_USART2_RTS location number i */
+#define AF_USART3_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : (i) == 8 ? 8 : (i) == 9 ? 8 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 9 : (i) == 17 ? 9 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1) /**< Port number for AF_USART3_TX location number i */
+#define AF_USART3_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 8 : (i) == 8 ? 8 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 9 : (i) == 16 ? 9 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 3 : -1) /**< Port number for AF_USART3_RX location number i */
+#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 8 : (i) == 7 ? 8 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 9 : (i) == 15 ? 9 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) /**< Port number for AF_USART3_CLK location number i */
+#define AF_USART3_CS_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 9 : (i) == 14 ? 9 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) /**< Port number for AF_USART3_CS location number i */
+#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 9 : (i) == 13 ? 9 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) /**< Port number for AF_USART3_CTS location number i */
+#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 10 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 3 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) /**< Port number for AF_USART3_RTS location number i */
+#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_LEUART0_TX location number i */
+#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_LEUART0_RX location number i */
+#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */
+#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */
+#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_PCNT0_S0IN location number i */
+#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_PCNT0_S1IN location number i */
+#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1) /**< Port number for AF_PCNT1_S0IN location number i */
+#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 9 : (i) == 11 ? 9 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1) /**< Port number for AF_PCNT1_S1IN location number i */
+#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1) /**< Port number for AF_PCNT2_S0IN location number i */
+#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 9 : (i) == 11 ? 9 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1) /**< Port number for AF_PCNT2_S1IN location number i */
+#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_I2C0_SDA location number i */
+#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) /**< Port number for AF_I2C0_SCL location number i */
+#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1) /**< Port number for AF_I2C1_SDA location number i */
+#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 9 : (i) == 11 ? 9 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1) /**< Port number for AF_I2C1_SCL location number i */
+#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_ACMP0_OUT location number i */
+#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) /**< Port number for AF_ACMP1_OUT location number i */
+#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_CH0 location number i */
+#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_CH1 location number i */
+#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_CH2 location number i */
+#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_CH3 location number i */
+#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_CH4 location number i */
+#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_CH5 location number i */
+#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_CH6 location number i */
+#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_CH7 location number i */
+#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_CH8 location number i */
+#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_CH9 location number i */
+#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_CH10 location number i */
+#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_CH11 location number i */
+#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_CH12 location number i */
+#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_CH13 location number i */
+#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_CH14 location number i */
+#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_CH15 location number i */
+#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */
+#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */
+#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 9 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */
+#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 9 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */
+#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 8 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */
+#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 8 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */
+#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 8 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */
+#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 8 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */
+#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */
+#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */
+#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : -1) /**< Port number for AF_DBG_SWV location number i */
+#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */
+#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */
+#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 8 : (i) == 3 ? 2 : -1) /**< Port number for AF_ETM_TCLK location number i */
+#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 8 : (i) == 3 ? 2 : -1) /**< Port number for AF_ETM_TD0 location number i */
+#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Port number for AF_ETM_TD1 location number i */
+#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Port number for AF_ETM_TD2 location number i */
+#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Port number for AF_ETM_TD3 location number i */
/** @} */
-/** @} End of group EFR32FG13P_AF_Ports */
+/** @} End of group EFR32FG12P_AF_Ports */
/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_cmu.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_cmu.h
similarity index 98%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_cmu.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_cmu.h
index 8eeccf0d..7a8c206b 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_cmu.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_cmu.h
@@ -1,84 +1,89 @@
-/**************************************************************************//**
- * @file efr32fg12p_cmu.h
+/***************************************************************************//**
+ * @file
* @brief EFR32FG12P_CMU register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_CMU
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P_CMU CMU
* @{
* @brief EFR32FG12P_CMU Register Declaration
- *****************************************************************************/
-typedef struct
-{
+ ******************************************************************************/
+/** CMU Register Declaration */
+typedef struct {
__IOM uint32_t CTRL; /**< CMU Control Register */
- uint32_t RESERVED0[3]; /**< Reserved for future use **/
+ uint32_t RESERVED0[3U]; /**< Reserved for future use **/
__IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */
- uint32_t RESERVED1[1]; /**< Reserved for future use **/
+ uint32_t RESERVED1[1U]; /**< Reserved for future use **/
__IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */
- uint32_t RESERVED2[1]; /**< Reserved for future use **/
+ uint32_t RESERVED2[1U]; /**< Reserved for future use **/
__IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */
__IOM uint32_t HFXOCTRL; /**< HFXO Control Register */
- uint32_t RESERVED3[1]; /**< Reserved for future use **/
+ uint32_t RESERVED3[1U]; /**< Reserved for future use **/
__IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */
- __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State control */
+ __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */
__IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */
__IOM uint32_t LFXOCTRL; /**< LFXO Control Register */
- uint32_t RESERVED4[1]; /**< Reserved for future use **/
+ uint32_t RESERVED4[1U]; /**< Reserved for future use **/
__IOM uint32_t DPLLCTRL; /**< DPLL Control Register */
__IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */
- uint32_t RESERVED5[2]; /**< Reserved for future use **/
+ uint32_t RESERVED5[2U]; /**< Reserved for future use **/
__IOM uint32_t CALCTRL; /**< Calibration Control Register */
__IOM uint32_t CALCNT; /**< Calibration Counter Register */
- uint32_t RESERVED6[2]; /**< Reserved for future use **/
+ uint32_t RESERVED6[2U]; /**< Reserved for future use **/
__IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */
__IOM uint32_t CMD; /**< Command Register */
- uint32_t RESERVED7[2]; /**< Reserved for future use **/
+ uint32_t RESERVED7[2U]; /**< Reserved for future use **/
__IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */
__IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */
- uint32_t RESERVED8[2]; /**< Reserved for future use **/
+ uint32_t RESERVED8[2U]; /**< Reserved for future use **/
__IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */
__IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */
__IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */
- uint32_t RESERVED9[1]; /**< Reserved for future use **/
+ uint32_t RESERVED9[1U]; /**< Reserved for future use **/
__IM uint32_t STATUS; /**< Status Register */
__IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */
- uint32_t RESERVED10[1]; /**< Reserved for future use **/
+ uint32_t RESERVED10[1U]; /**< Reserved for future use **/
__IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */
__IM uint32_t IF; /**< Interrupt Flag Register */
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
@@ -86,55 +91,57 @@ typedef struct
__IOM uint32_t IEN; /**< Interrupt Enable Register */
__IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */
- uint32_t RESERVED11[3]; /**< Reserved for future use **/
+ uint32_t RESERVED11[3U]; /**< Reserved for future use **/
__IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */
- uint32_t RESERVED12[7]; /**< Reserved for future use **/
- __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */
- uint32_t RESERVED13[1]; /**< Reserved for future use **/
+ uint32_t RESERVED12[7U]; /**< Reserved for future use **/
+ __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */
+ uint32_t RESERVED13[1U]; /**< Reserved for future use **/
__IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */
- uint32_t RESERVED14[1]; /**< Reserved for future use **/
+ uint32_t RESERVED14[1U]; /**< Reserved for future use **/
__IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */
- uint32_t RESERVED15[3]; /**< Reserved for future use **/
+ uint32_t RESERVED15[3U]; /**< Reserved for future use **/
__IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */
- uint32_t RESERVED16[1]; /**< Reserved for future use **/
+ uint32_t RESERVED16[1U]; /**< Reserved for future use **/
__IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */
__IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */
- uint32_t RESERVED17[1]; /**< Reserved for future use **/
+ uint32_t RESERVED17[1U]; /**< Reserved for future use **/
__IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */
- uint32_t RESERVED18[2]; /**< Reserved for future use **/
- __IOM uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */
- uint32_t RESERVED19[1]; /**< Reserved for future use **/
+ uint32_t RESERVED18[2U]; /**< Reserved for future use **/
+ __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */
+ uint32_t RESERVED19[1U]; /**< Reserved for future use **/
__IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */
- uint32_t RESERVED20[1]; /**< Reserved for future use **/
- __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg). When waking up from EM4 make sure EM4UNLATCH in EMU_CMD is set for this to take effect */
+ uint32_t RESERVED20[1U]; /**< Reserved for future use **/
+ __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */
- uint32_t RESERVED21[3]; /**< Reserved for future use **/
+ uint32_t RESERVED21[3U]; /**< Reserved for future use **/
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
__IOM uint32_t FREEZE; /**< Freeze Register */
- uint32_t RESERVED22[2]; /**< Reserved for future use **/
+ uint32_t RESERVED22[2U]; /**< Reserved for future use **/
__IOM uint32_t PCNTCTRL; /**< PCNT Control Register */
- uint32_t RESERVED23[2]; /**< Reserved for future use **/
+ uint32_t RESERVED23[2U]; /**< Reserved for future use **/
__IOM uint32_t ADCCTRL; /**< ADC Control Register */
- uint32_t RESERVED24[4]; /**< Reserved for future use **/
+ uint32_t RESERVED24[4U]; /**< Reserved for future use **/
__IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
__IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
__IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */
- uint32_t RESERVED25[1]; /**< Reserved for future use **/
+ uint32_t RESERVED25[1U]; /**< Reserved for future use **/
__IOM uint32_t LOCK; /**< Configuration Lock Register */
__IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */
} CMU_TypeDef; /** @} */
-/**************************************************************************//**
- * @defgroup EFR32FG12P_CMU_BitFields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_CMU
+ * @{
+ * @defgroup EFR32FG12P_CMU_BitFields CMU Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for CMU CTRL */
#define _CMU_CTRL_RESETVALUE 0x00300000UL /**< Default value for CMU_CTRL */
@@ -244,7 +251,7 @@ typedef struct
#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */
#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */
#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */
-#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable reference for fine tuning */
+#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */
#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */
#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */
#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
@@ -288,7 +295,7 @@ typedef struct
#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */
#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */
#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */
-#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable reference for fine tuning */
+#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */
#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */
#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */
#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
@@ -305,17 +312,17 @@ typedef struct
#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */
#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
-#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable duty cycling of vref */
+#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */
#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */
#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */
#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
-#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable comparator chopping */
+#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */
#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */
#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */
#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
-#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable dynamic element matching */
+#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */
#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */
#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */
#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
@@ -369,17 +376,17 @@ typedef struct
#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */
#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */
#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_LOWPOWER (0x1UL << 8) /**< Low power mode control. PSR performance is reduced to enable low current consumption. */
+#define CMU_HFXOCTRL_LOWPOWER (0x1UL << 8) /**< Low Power Mode Control */
#define _CMU_HFXOCTRL_LOWPOWER_SHIFT 8 /**< Shift value for CMU_LOWPOWER */
#define _CMU_HFXOCTRL_LOWPOWER_MASK 0x100UL /**< Bit mask for CMU_LOWPOWER */
#define _CMU_HFXOCTRL_LOWPOWER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
#define CMU_HFXOCTRL_LOWPOWER_DEFAULT (_CMU_HFXOCTRL_LOWPOWER_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_XTI2GND (0x1UL << 9) /**< Clamp HFXTAL_N pin to ground when HFXO oscillator is off. */
+#define CMU_HFXOCTRL_XTI2GND (0x1UL << 9) /**< Clamp HFXTAL_N Pin to Ground When HFXO Oscillator is Off */
#define _CMU_HFXOCTRL_XTI2GND_SHIFT 9 /**< Shift value for CMU_XTI2GND */
#define _CMU_HFXOCTRL_XTI2GND_MASK 0x200UL /**< Bit mask for CMU_XTI2GND */
#define _CMU_HFXOCTRL_XTI2GND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
#define CMU_HFXOCTRL_XTI2GND_DEFAULT (_CMU_HFXOCTRL_XTI2GND_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_XTO2GND (0x1UL << 10) /**< Clamp HFXTAL_P pin to ground when HFXO oscillator is off. */
+#define CMU_HFXOCTRL_XTO2GND (0x1UL << 10) /**< Clamp HFXTAL_P Pin to Ground When HFXO Oscillator is Off */
#define _CMU_HFXOCTRL_XTO2GND_SHIFT 10 /**< Shift value for CMU_XTO2GND */
#define _CMU_HFXOCTRL_XTO2GND_MASK 0x400UL /**< Bit mask for CMU_XTO2GND */
#define _CMU_HFXOCTRL_XTO2GND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
@@ -404,12 +411,12 @@ typedef struct
#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */
#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */
#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically start of HFXO upon EM0/EM1 entry from EM2/EM3 */
+#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */
#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */
#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */
#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically start and select of HFXO upon EM0/EM1 entry from EM2/EM3 */
+#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */
#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */
#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */
#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
@@ -446,7 +453,7 @@ typedef struct
#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_MASK 0x3000000UL /**< Bit mask for CMU_REGSELILOW */
#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
#define CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
-#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables oscillator peak detectors */
+#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */
#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */
#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */
#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
@@ -646,7 +653,7 @@ typedef struct
#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */
#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */
#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */
-#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< automatic recovery ctrl */
+#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */
#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */
#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */
#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */
@@ -1019,7 +1026,7 @@ typedef struct
#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */
#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFXOREQ (0x1UL << 21) /**< HFXO is Required by Hardware (e.g. RAC) */
+#define CMU_STATUS_HFXOREQ (0x1UL << 21) /**< HFXO is Required By Hardware */
#define _CMU_STATUS_HFXOREQ_SHIFT 21 /**< Shift value for CMU_HFXOREQ */
#define _CMU_STATUS_HFXOREQ_MASK 0x200000UL /**< Bit mask for CMU_HFXOREQ */
#define _CMU_STATUS_HFXOREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
@@ -1029,22 +1036,22 @@ typedef struct
#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */
#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFXOSHUNTOPTRDY (0x1UL << 23) /**< HFXO Shunt Current Optimization ready */
+#define CMU_STATUS_HFXOSHUNTOPTRDY (0x1UL << 23) /**< HFXO Shunt Current Optimization Ready */
#define _CMU_STATUS_HFXOSHUNTOPTRDY_SHIFT 23 /**< Shift value for CMU_HFXOSHUNTOPTRDY */
#define _CMU_STATUS_HFXOSHUNTOPTRDY_MASK 0x800000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */
#define _CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
#define CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT (_CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFXOAMPHIGH (0x1UL << 24) /**< HFXO oscillation amplitude is too high */
+#define CMU_STATUS_HFXOAMPHIGH (0x1UL << 24) /**< HFXO Oscillation Amplitude is Too High */
#define _CMU_STATUS_HFXOAMPHIGH_SHIFT 24 /**< Shift value for CMU_HFXOAMPHIGH */
#define _CMU_STATUS_HFXOAMPHIGH_MASK 0x1000000UL /**< Bit mask for CMU_HFXOAMPHIGH */
#define _CMU_STATUS_HFXOAMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
#define CMU_STATUS_HFXOAMPHIGH_DEFAULT (_CMU_STATUS_HFXOAMPHIGH_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO amplitude tuning value too low */
+#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */
#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */
#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */
#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFXOREGILOW (0x1UL << 26) /**< HFXO regulator shunt current too low */
+#define CMU_STATUS_HFXOREGILOW (0x1UL << 26) /**< HFXO Regulator Shunt Current Too Low */
#define _CMU_STATUS_HFXOREGILOW_SHIFT 26 /**< Shift value for CMU_HFXOREGILOW */
#define _CMU_STATUS_HFXOREGILOW_MASK 0x4000000UL /**< Bit mask for CMU_HFXOREGILOW */
#define _CMU_STATUS_HFXOREGILOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
@@ -1565,7 +1572,7 @@ typedef struct
#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x800UL /**< Bit mask for CMU_ACMP1 */
#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 12) /**< CryoTimer Clock Enable */
+#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 12) /**< CRYOTIMER Clock Enable */
#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 12 /**< Shift value for CMU_CRYOTIMER */
#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x1000UL /**< Bit mask for CMU_CRYOTIMER */
#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
@@ -1777,12 +1784,12 @@ typedef struct
/* Bit fields for CMU SYNCBUSY */
#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */
#define _CMU_SYNCBUSY_MASK 0x3F050055UL /**< Mask for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */
+#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */
#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */
#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */
#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */
+#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */
#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */
#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */
#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
@@ -1912,7 +1919,7 @@ typedef struct
#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */
#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */
#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */
-#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert clock selected by ADC0CLKSEL */
+#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */
#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */
#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */
#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */
@@ -2005,13 +2012,13 @@ typedef struct
#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */
#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */
#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */
#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */
+#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */
#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */
#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */
+#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */
#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */
@@ -2027,6 +2034,6 @@ typedef struct
#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */
#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */
+/** @} */
/** @} End of group EFR32FG12P_CMU */
/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_cryotimer.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_cryotimer.h
similarity index 90%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_cryotimer.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_cryotimer.h
index 63550358..a00f3870 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_cryotimer.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_cryotimer.h
@@ -1,45 +1,50 @@
-/**************************************************************************//**
- * @file efr32fg12p_cryotimer.h
+/***************************************************************************//**
+ * @file
* @brief EFR32FG12P_CRYOTIMER register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_CRYOTIMER
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P_CRYOTIMER CRYOTIMER
* @{
* @brief EFR32FG12P_CRYOTIMER Register Declaration
- *****************************************************************************/
-typedef struct
-{
+ ******************************************************************************/
+/** CRYOTIMER Register Declaration */
+typedef struct {
__IOM uint32_t CTRL; /**< Control Register */
__IOM uint32_t PERIODSEL; /**< Interrupt Duration */
__IM uint32_t CNT; /**< Counter Value */
@@ -50,10 +55,12 @@ typedef struct
__IOM uint32_t IEN; /**< Interrupt Enable Register */
} CRYOTIMER_TypeDef; /** @} */
-/**************************************************************************//**
- * @defgroup EFR32FG12P_CRYOTIMER_BitFields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_CRYOTIMER
* @{
- *****************************************************************************/
+ * @defgroup EFR32FG12P_CRYOTIMER_BitFields CRYOTIMER Bit Fields
+ * @{
+ ******************************************************************************/
/* Bit fields for CRYOTIMER CTRL */
#define _CRYOTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_CTRL */
@@ -120,7 +127,7 @@ typedef struct
/* Bit fields for CRYOTIMER EM4WUEN */
#define _CRYOTIMER_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_EM4WUEN */
#define _CRYOTIMER_EM4WUEN_MASK 0x00000001UL /**< Mask for CRYOTIMER_EM4WUEN */
-#define CRYOTIMER_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up enable */
+#define CRYOTIMER_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up Enable */
#define _CRYOTIMER_EM4WUEN_EM4WU_SHIFT 0 /**< Shift value for CRYOTIMER_EM4WU */
#define _CRYOTIMER_EM4WUEN_EM4WU_MASK 0x1UL /**< Bit mask for CRYOTIMER_EM4WU */
#define _CRYOTIMER_EM4WUEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_EM4WUEN */
@@ -129,7 +136,7 @@ typedef struct
/* Bit fields for CRYOTIMER IF */
#define _CRYOTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IF */
#define _CRYOTIMER_IF_MASK 0x00000001UL /**< Mask for CRYOTIMER_IF */
-#define CRYOTIMER_IF_PERIOD (0x1UL << 0) /**< Wakeup event/Interrupt */
+#define CRYOTIMER_IF_PERIOD (0x1UL << 0) /**< Wakeup Event/Interrupt */
#define _CRYOTIMER_IF_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */
#define _CRYOTIMER_IF_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */
#define _CRYOTIMER_IF_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IF */
@@ -162,6 +169,6 @@ typedef struct
#define _CRYOTIMER_IEN_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IEN */
#define CRYOTIMER_IEN_PERIOD_DEFAULT (_CRYOTIMER_IEN_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IEN */
+/** @} */
/** @} End of group EFR32FG12P_CRYOTIMER */
/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_crypto.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_crypto.h
similarity index 96%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_crypto.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_crypto.h
index e1ecfb38..8582024a 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_crypto.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_crypto.h
@@ -1,110 +1,117 @@
-/**************************************************************************//**
- * @file efr32fg12p_crypto.h
+/***************************************************************************//**
+ * @file
* @brief EFR32FG12P_CRYPTO register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_CRYPTO
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P_CRYPTO CRYPTO
* @{
* @brief EFR32FG12P_CRYPTO Register Declaration
- *****************************************************************************/
-typedef struct
-{
- __IOM uint32_t CTRL; /**< Control Register */
- __IOM uint32_t WAC; /**< Wide Arithmetic Configuration */
- __IOM uint32_t CMD; /**< Command Register */
- uint32_t RESERVED0[1]; /**< Reserved for future use **/
- __IM uint32_t STATUS; /**< Status Register */
- __IM uint32_t DSTATUS; /**< Data Status Register */
- __IM uint32_t CSTATUS; /**< Control Status Register */
- uint32_t RESERVED1[1]; /**< Reserved for future use **/
- __IOM uint32_t KEY; /**< KEY Register Access */
- __IOM uint32_t KEYBUF; /**< KEY Buffer Register Access */
- uint32_t RESERVED2[2]; /**< Reserved for future use **/
- __IOM uint32_t SEQCTRL; /**< Sequence Control */
- __IOM uint32_t SEQCTRLB; /**< Sequence Control B */
- uint32_t RESERVED3[2]; /**< Reserved for future use **/
- __IM uint32_t IF; /**< AES Interrupt Flags */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- __IOM uint32_t SEQ0; /**< Sequence register 0 */
- __IOM uint32_t SEQ1; /**< Sequence Register 1 */
- __IOM uint32_t SEQ2; /**< Sequence Register 2 */
- __IOM uint32_t SEQ3; /**< Sequence Register 3 */
- __IOM uint32_t SEQ4; /**< Sequence Register 4 */
- uint32_t RESERVED4[7]; /**< Reserved for future use **/
- __IOM uint32_t DATA0; /**< DATA0 Register Access */
- __IOM uint32_t DATA1; /**< DATA1 Register Access */
- __IOM uint32_t DATA2; /**< DATA2 Register Access */
- __IOM uint32_t DATA3; /**< DATA3 Register Access */
- uint32_t RESERVED5[4]; /**< Reserved for future use **/
- __IOM uint32_t DATA0XOR; /**< DATA0XOR Register Access */
- uint32_t RESERVED6[3]; /**< Reserved for future use **/
- __IOM uint32_t DATA0BYTE; /**< DATA0 Register Byte Access */
- __IOM uint32_t DATA1BYTE; /**< DATA1 Register Byte Access */
- uint32_t RESERVED7[1]; /**< Reserved for future use **/
- __IOM uint32_t DATA0XORBYTE; /**< DATA0 Register Byte XOR Access */
- __IOM uint32_t DATA0BYTE12; /**< DATA0 Register Byte 12 Access */
- __IOM uint32_t DATA0BYTE13; /**< DATA0 Register Byte 13 Access */
- __IOM uint32_t DATA0BYTE14; /**< DATA0 Register Byte 14 Access */
- __IOM uint32_t DATA0BYTE15; /**< DATA0 Register Byte 15 Access */
- uint32_t RESERVED8[12]; /**< Reserved for future use **/
- __IOM uint32_t DDATA0; /**< DDATA0 Register Access */
- __IOM uint32_t DDATA1; /**< DDATA1 Register Access */
- __IOM uint32_t DDATA2; /**< DDATA2 Register Access */
- __IOM uint32_t DDATA3; /**< DDATA3 Register Access */
- __IOM uint32_t DDATA4; /**< DDATA4 Register Access */
- uint32_t RESERVED9[7]; /**< Reserved for future use **/
- __IOM uint32_t DDATA0BIG; /**< DDATA0 Register Big Endian Access */
- uint32_t RESERVED10[3]; /**< Reserved for future use **/
- __IOM uint32_t DDATA0BYTE; /**< DDATA0 Register Byte Access */
- __IOM uint32_t DDATA1BYTE; /**< DDATA1 Register Byte Access */
- __IOM uint32_t DDATA0BYTE32; /**< DDATA0 Register Byte 32 access. */
- uint32_t RESERVED11[13]; /**< Reserved for future use **/
- __IOM uint32_t QDATA0; /**< QDATA0 Register Access */
- __IOM uint32_t QDATA1; /**< QDATA1 Register Access */
- uint32_t RESERVED12[7]; /**< Reserved for future use **/
- __IOM uint32_t QDATA1BIG; /**< QDATA1 Register Big Endian Access */
- uint32_t RESERVED13[6]; /**< Reserved for future use **/
- __IOM uint32_t QDATA0BYTE; /**< QDATA0 Register Byte Access */
- __IOM uint32_t QDATA1BYTE; /**< QDATA1 Register Byte Access */
-} CRYPTO_TypeDef; /** @} */
+ ******************************************************************************/
+/** CRYPTO Register Declaration */
+typedef struct {
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t WAC; /**< Wide Arithmetic Configuration */
+ __IOM uint32_t CMD; /**< Command Register */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use **/
+ __IM uint32_t STATUS; /**< Status Register */
+ __IM uint32_t DSTATUS; /**< Data Status Register */
+ __IM uint32_t CSTATUS; /**< Control Status Register */
+ uint32_t RESERVED1[1U]; /**< Reserved for future use **/
+ __IOM uint32_t KEY; /**< KEY Register Access */
+ __IOM uint32_t KEYBUF; /**< KEY Buffer Register Access */
+ uint32_t RESERVED2[2U]; /**< Reserved for future use **/
+ __IOM uint32_t SEQCTRL; /**< Sequence Control */
+ __IOM uint32_t SEQCTRLB; /**< Sequence Control B */
+ uint32_t RESERVED3[2U]; /**< Reserved for future use **/
+ __IM uint32_t IF; /**< AES Interrupt Flags */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IOM uint32_t SEQ0; /**< Sequence Register 0 */
+ __IOM uint32_t SEQ1; /**< Sequence Register 1 */
+ __IOM uint32_t SEQ2; /**< Sequence Register 2 */
+ __IOM uint32_t SEQ3; /**< Sequence Register 3 */
+ __IOM uint32_t SEQ4; /**< Sequence Register 4 */
+ uint32_t RESERVED4[7U]; /**< Reserved for future use **/
+ __IOM uint32_t DATA0; /**< DATA0 Register Access */
+ __IOM uint32_t DATA1; /**< DATA1 Register Access */
+ __IOM uint32_t DATA2; /**< DATA2 Register Access */
+ __IOM uint32_t DATA3; /**< DATA3 Register Access */
+ uint32_t RESERVED5[4U]; /**< Reserved for future use **/
+ __IOM uint32_t DATA0XOR; /**< DATA0XOR Register Access */
+ uint32_t RESERVED6[3U]; /**< Reserved for future use **/
+ __IOM uint32_t DATA0BYTE; /**< DATA0 Register Byte Access */
+ __IOM uint32_t DATA1BYTE; /**< DATA1 Register Byte Access */
+ uint32_t RESERVED7[1U]; /**< Reserved for future use **/
+ __IOM uint32_t DATA0XORBYTE; /**< DATA0 Register Byte XOR Access */
+ __IOM uint32_t DATA0BYTE12; /**< DATA0 Register Byte 12 Access */
+ __IOM uint32_t DATA0BYTE13; /**< DATA0 Register Byte 13 Access */
+ __IOM uint32_t DATA0BYTE14; /**< DATA0 Register Byte 14 Access */
+ __IOM uint32_t DATA0BYTE15; /**< DATA0 Register Byte 15 Access */
+ uint32_t RESERVED8[12U]; /**< Reserved for future use **/
+ __IOM uint32_t DDATA0; /**< DDATA0 Register Access */
+ __IOM uint32_t DDATA1; /**< DDATA1 Register Access */
+ __IOM uint32_t DDATA2; /**< DDATA2 Register Access */
+ __IOM uint32_t DDATA3; /**< DDATA3 Register Access */
+ __IOM uint32_t DDATA4; /**< DDATA4 Register Access */
+ uint32_t RESERVED9[7U]; /**< Reserved for future use **/
+ __IOM uint32_t DDATA0BIG; /**< DDATA0 Register Big Endian Access */
+ uint32_t RESERVED10[3U]; /**< Reserved for future use **/
+ __IOM uint32_t DDATA0BYTE; /**< DDATA0 Register Byte Access */
+ __IOM uint32_t DDATA1BYTE; /**< DDATA1 Register Byte Access */
+ __IOM uint32_t DDATA0BYTE32; /**< DDATA0 Register Byte 32 Access */
+ uint32_t RESERVED11[13U]; /**< Reserved for future use **/
+ __IOM uint32_t QDATA0; /**< QDATA0 Register Access */
+ __IOM uint32_t QDATA1; /**< QDATA1 Register Access */
+ uint32_t RESERVED12[7U]; /**< Reserved for future use **/
+ __IOM uint32_t QDATA1BIG; /**< QDATA1 Register Big Endian Access */
+ uint32_t RESERVED13[6U]; /**< Reserved for future use **/
+ __IOM uint32_t QDATA0BYTE; /**< QDATA0 Register Byte Access */
+ __IOM uint32_t QDATA1BYTE; /**< QDATA1 Register Byte Access */
+} CRYPTO_TypeDef; /** @} */
-/**************************************************************************//**
- * @defgroup EFR32FG12P_CRYPTO_BitFields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_CRYPTO
* @{
- *****************************************************************************/
+ * @defgroup EFR32FG12P_CRYPTO_BitFields CRYPTO Bit Fields
+ * @{
+ ******************************************************************************/
/* Bit fields for CRYPTO CTRL */
#define _CRYPTO_CTRL_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_CTRL */
@@ -665,12 +672,12 @@ typedef struct
#define _CRYPTO_STATUS_SEQRUNNING_MASK 0x1UL /**< Bit mask for CRYPTO_SEQRUNNING */
#define _CRYPTO_STATUS_SEQRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */
#define CRYPTO_STATUS_SEQRUNNING_DEFAULT (_CRYPTO_STATUS_SEQRUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_STATUS */
-#define CRYPTO_STATUS_INSTRRUNNING (0x1UL << 1) /**< Action is active */
+#define CRYPTO_STATUS_INSTRRUNNING (0x1UL << 1) /**< Action is Active */
#define _CRYPTO_STATUS_INSTRRUNNING_SHIFT 1 /**< Shift value for CRYPTO_INSTRRUNNING */
#define _CRYPTO_STATUS_INSTRRUNNING_MASK 0x2UL /**< Bit mask for CRYPTO_INSTRRUNNING */
#define _CRYPTO_STATUS_INSTRRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */
#define CRYPTO_STATUS_INSTRRUNNING_DEFAULT (_CRYPTO_STATUS_INSTRRUNNING_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_STATUS */
-#define CRYPTO_STATUS_DMAACTIVE (0x1UL << 2) /**< DMA Action is active */
+#define CRYPTO_STATUS_DMAACTIVE (0x1UL << 2) /**< DMA Action is Active */
#define _CRYPTO_STATUS_DMAACTIVE_SHIFT 2 /**< Shift value for CRYPTO_DMAACTIVE */
#define _CRYPTO_STATUS_DMAACTIVE_MASK 0x4UL /**< Bit mask for CRYPTO_DMAACTIVE */
#define _CRYPTO_STATUS_DMAACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */
@@ -813,12 +820,12 @@ typedef struct
#define _CRYPTO_SEQCTRL_DMA1SKIP_MASK 0xC000000UL /**< Bit mask for CRYPTO_DMA1SKIP */
#define _CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */
#define CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT (_CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT << 26) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */
-#define CRYPTO_SEQCTRL_DMA0PRESA (0x1UL << 28) /**< DMA0 Preserve A */
+#define CRYPTO_SEQCTRL_DMA0PRESA (0x1UL << 28) /**< DMA0 Preserve a */
#define _CRYPTO_SEQCTRL_DMA0PRESA_SHIFT 28 /**< Shift value for CRYPTO_DMA0PRESA */
#define _CRYPTO_SEQCTRL_DMA0PRESA_MASK 0x10000000UL /**< Bit mask for CRYPTO_DMA0PRESA */
#define _CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */
#define CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT (_CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */
-#define CRYPTO_SEQCTRL_DMA1PRESA (0x1UL << 29) /**< DMA1 Preserve A */
+#define CRYPTO_SEQCTRL_DMA1PRESA (0x1UL << 29) /**< DMA1 Preserve a */
#define _CRYPTO_SEQCTRL_DMA1PRESA_SHIFT 29 /**< Shift value for CRYPTO_DMA1PRESA */
#define _CRYPTO_SEQCTRL_DMA1PRESA_MASK 0x20000000UL /**< Bit mask for CRYPTO_DMA1PRESA */
#define _CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */
@@ -850,7 +857,7 @@ typedef struct
/* Bit fields for CRYPTO IF */
#define _CRYPTO_IF_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IF */
#define _CRYPTO_IF_MASK 0x00000003UL /**< Mask for CRYPTO_IF */
-#define CRYPTO_IF_INSTRDONE (0x1UL << 0) /**< Instruction done */
+#define CRYPTO_IF_INSTRDONE (0x1UL << 0) /**< Instruction Done */
#define _CRYPTO_IF_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */
#define _CRYPTO_IF_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */
#define _CRYPTO_IF_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IF */
@@ -1211,6 +1218,6 @@ typedef struct
#define _CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA1BYTE */
#define CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT (_CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1BYTE */
+/** @} */
/** @} End of group EFR32FG12P_CRYPTO */
/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_csen.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_csen.h
similarity index 91%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_csen.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_csen.h
index f722ee15..3c6b03a5 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_csen.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_csen.h
@@ -1,76 +1,83 @@
-/**************************************************************************//**
- * @file efr32fg12p_csen.h
+/***************************************************************************//**
+ * @file
* @brief EFR32FG12P_CSEN register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_CSEN
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P_CSEN CSEN
* @{
* @brief EFR32FG12P_CSEN Register Declaration
- *****************************************************************************/
-typedef struct
-{
- __IOM uint32_t CTRL; /**< Control Register */
- __IOM uint32_t TIMCTRL; /**< Timing Control Register */
- __IOM uint32_t CMD; /**< Command Register */
- __IM uint32_t STATUS; /**< Status Register */
- __IOM uint32_t PRSSEL; /**< Control Register */
- __IOM uint32_t DATA; /**< Control Register */
- __IOM uint32_t SCANMASK0; /**< CSEN Channel Scan Mask */
- __IOM uint32_t SCANINPUTSEL0; /**< Input Channel Configuration register for Scan mode */
- __IOM uint32_t SCANMASK1; /**< CSEN Channel Scan Mask */
- __IOM uint32_t SCANINPUTSEL1; /**< Input Channel Configuration register for Scan mode */
- __IM uint32_t APORTREQ; /**< APORT Request Status Register */
- __IM uint32_t APORTCONFLICT; /**< APORT Request Status Register */
- __IOM uint32_t CMPTHR; /**< CSEN Comparator Threshold */
+ ******************************************************************************/
+/** CSEN Register Declaration */
+typedef struct {
+ __IOM uint32_t CTRL; /**< Control */
+ __IOM uint32_t TIMCTRL; /**< Timing Control */
+ __IOM uint32_t CMD; /**< Command */
+ __IM uint32_t STATUS; /**< Status */
+ __IOM uint32_t PRSSEL; /**< PRS Select */
+ __IOM uint32_t DATA; /**< Output Data */
+ __IOM uint32_t SCANMASK0; /**< Scan Channel Mask 0 */
+ __IOM uint32_t SCANINPUTSEL0; /**< Scan Input Selection 0 */
+ __IOM uint32_t SCANMASK1; /**< Scan Channel Mask 1 */
+ __IOM uint32_t SCANINPUTSEL1; /**< Scan Input Selection 1 */
+ __IM uint32_t APORTREQ; /**< APORT Request Status */
+ __IM uint32_t APORTCONFLICT; /**< APORT Request Conflict */
+ __IOM uint32_t CMPTHR; /**< Comparator Threshold */
__IOM uint32_t EMA; /**< Exponential Moving Average */
- __IOM uint32_t EMACTRL; /**< Exponential Moving Average */
- __IOM uint32_t SINGLECTRL; /**< CSEN Single Conversion Control Register */
- __IOM uint32_t DMBASELINE; /**< Control Register */
- __IOM uint32_t DMCFG; /**< Control Register */
- __IOM uint32_t ANACTRL; /**< Analog Control Register */
+ __IOM uint32_t EMACTRL; /**< Exponential Moving Average Control */
+ __IOM uint32_t SINGLECTRL; /**< Single Conversion Control */
+ __IOM uint32_t DMBASELINE; /**< Delta Modulation Baseline */
+ __IOM uint32_t DMCFG; /**< Delta Modulation Configuration */
+ __IOM uint32_t ANACTRL; /**< Analog Control */
- uint32_t RESERVED0[2]; /**< Reserved for future use **/
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ uint32_t RESERVED0[2U]; /**< Reserved for future use **/
+ __IM uint32_t IF; /**< Interrupt Flag */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear */
+ __IOM uint32_t IEN; /**< Interrupt Enable */
} CSEN_TypeDef; /** @} */
-/**************************************************************************//**
- * @defgroup EFR32FG12P_CSEN_BitFields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_CSEN
* @{
- *****************************************************************************/
+ * @defgroup EFR32FG12P_CSEN_BitFields CSEN Bit Fields
+ * @{
+ ******************************************************************************/
/* Bit fields for CSEN CTRL */
#define _CSEN_CTRL_RESETVALUE 0x00030000UL /**< Default value for CSEN_CTRL */
@@ -135,7 +142,7 @@ typedef struct
#define CSEN_CTRL_ACU_ACC16 (_CSEN_CTRL_ACU_ACC16 << 12) /**< Shifted mode ACC16 for CSEN_CTRL */
#define CSEN_CTRL_ACU_ACC32 (_CSEN_CTRL_ACU_ACC32 << 12) /**< Shifted mode ACC32 for CSEN_CTRL */
#define CSEN_CTRL_ACU_ACC64 (_CSEN_CTRL_ACU_ACC64 << 12) /**< Shifted mode ACC64 for CSEN_CTRL */
-#define CSEN_CTRL_MCEN (0x1UL << 15) /**< CSEN Multiple Channel Enable. */
+#define CSEN_CTRL_MCEN (0x1UL << 15) /**< CSEN Multiple Channel Enable */
#define _CSEN_CTRL_MCEN_SHIFT 15 /**< Shift value for CSEN_MCEN */
#define _CSEN_CTRL_MCEN_MASK 0x8000UL /**< Bit mask for CSEN_MCEN */
#define _CSEN_CTRL_MCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
@@ -156,7 +163,7 @@ typedef struct
#define CSEN_CTRL_STM_START (_CSEN_CTRL_STM_START << 16) /**< Shifted mode START for CSEN_CTRL */
#define CSEN_CTRL_STM_DEFAULT (_CSEN_CTRL_STM_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_CTRL */
#define CSEN_CTRL_STM_DEFAULT (_CSEN_CTRL_STM_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_CTRL */
-#define CSEN_CTRL_CMPEN (0x1UL << 18) /**< CSEN Digital Comparator Enable Bit. */
+#define CSEN_CTRL_CMPEN (0x1UL << 18) /**< CSEN Digital Comparator Enable */
#define _CSEN_CTRL_CMPEN_SHIFT 18 /**< Shift value for CSEN_CMPEN */
#define _CSEN_CTRL_CMPEN_MASK 0x40000UL /**< Bit mask for CSEN_CMPEN */
#define _CSEN_CTRL_CMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
@@ -165,7 +172,7 @@ typedef struct
#define CSEN_CTRL_CMPEN_DEFAULT (_CSEN_CTRL_CMPEN_DEFAULT << 18) /**< Shifted mode DEFAULT for CSEN_CTRL */
#define CSEN_CTRL_CMPEN_DISABLE (_CSEN_CTRL_CMPEN_DISABLE << 18) /**< Shifted mode DISABLE for CSEN_CTRL */
#define CSEN_CTRL_CMPEN_ENABLE (_CSEN_CTRL_CMPEN_ENABLE << 18) /**< Shifted mode ENABLE for CSEN_CTRL */
-#define CSEN_CTRL_DRSF (0x1UL << 19) /**< CSEN Disable Right-Shift. */
+#define CSEN_CTRL_DRSF (0x1UL << 19) /**< CSEN Disable Right-Shift */
#define _CSEN_CTRL_DRSF_SHIFT 19 /**< Shift value for CSEN_DRSF */
#define _CSEN_CTRL_DRSF_MASK 0x80000UL /**< Bit mask for CSEN_DRSF */
#define _CSEN_CTRL_DRSF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
@@ -174,7 +181,7 @@ typedef struct
#define CSEN_CTRL_DRSF_DEFAULT (_CSEN_CTRL_DRSF_DEFAULT << 19) /**< Shifted mode DEFAULT for CSEN_CTRL */
#define CSEN_CTRL_DRSF_DISABLE (_CSEN_CTRL_DRSF_DISABLE << 19) /**< Shifted mode DISABLE for CSEN_CTRL */
#define CSEN_CTRL_DRSF_ENABLE (_CSEN_CTRL_DRSF_ENABLE << 19) /**< Shifted mode ENABLE for CSEN_CTRL */
-#define CSEN_CTRL_DMAEN (0x1UL << 20) /**< CSEN DMA Enable Bit. */
+#define CSEN_CTRL_DMAEN (0x1UL << 20) /**< CSEN DMA Enable Bit */
#define _CSEN_CTRL_DMAEN_SHIFT 20 /**< Shift value for CSEN_DMAEN */
#define _CSEN_CTRL_DMAEN_MASK 0x100000UL /**< Bit mask for CSEN_DMAEN */
#define _CSEN_CTRL_DMAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
@@ -201,7 +208,7 @@ typedef struct
#define CSEN_CTRL_CHOPEN_DEFAULT (_CSEN_CTRL_CHOPEN_DEFAULT << 22) /**< Shifted mode DEFAULT for CSEN_CTRL */
#define CSEN_CTRL_CHOPEN_DISABLE (_CSEN_CTRL_CHOPEN_DISABLE << 22) /**< Shifted mode DISABLE for CSEN_CTRL */
#define CSEN_CTRL_CHOPEN_ENABLE (_CSEN_CTRL_CHOPEN_ENABLE << 22) /**< Shifted mode ENABLE for CSEN_CTRL */
-#define CSEN_CTRL_AUTOGND (0x1UL << 23) /**< CSEN auto ground enable */
+#define CSEN_CTRL_AUTOGND (0x1UL << 23) /**< CSEN Automatic Ground Enable */
#define _CSEN_CTRL_AUTOGND_SHIFT 23 /**< Shift value for CSEN_AUTOGND */
#define _CSEN_CTRL_AUTOGND_MASK 0x800000UL /**< Bit mask for CSEN_AUTOGND */
#define _CSEN_CTRL_AUTOGND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
@@ -210,7 +217,7 @@ typedef struct
#define CSEN_CTRL_AUTOGND_DEFAULT (_CSEN_CTRL_AUTOGND_DEFAULT << 23) /**< Shifted mode DEFAULT for CSEN_CTRL */
#define CSEN_CTRL_AUTOGND_DISABLE (_CSEN_CTRL_AUTOGND_DISABLE << 23) /**< Shifted mode DISABLE for CSEN_CTRL */
#define CSEN_CTRL_AUTOGND_ENABLE (_CSEN_CTRL_AUTOGND_ENABLE << 23) /**< Shifted mode ENABLE for CSEN_CTRL */
-#define CSEN_CTRL_MXUC (0x1UL << 24) /**< CSEN Mux Disconnect. */
+#define CSEN_CTRL_MXUC (0x1UL << 24) /**< CSEN Mux Disconnect */
#define _CSEN_CTRL_MXUC_SHIFT 24 /**< Shift value for CSEN_MXUC */
#define _CSEN_CTRL_MXUC_MASK 0x1000000UL /**< Bit mask for CSEN_MXUC */
#define _CSEN_CTRL_MXUC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
@@ -219,12 +226,12 @@ typedef struct
#define CSEN_CTRL_MXUC_DEFAULT (_CSEN_CTRL_MXUC_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_CTRL */
#define CSEN_CTRL_MXUC_CONN (_CSEN_CTRL_MXUC_CONN << 24) /**< Shifted mode CONN for CSEN_CTRL */
#define CSEN_CTRL_MXUC_UNC (_CSEN_CTRL_MXUC_UNC << 24) /**< Shifted mode UNC for CSEN_CTRL */
-#define CSEN_CTRL_EMACMPEN (0x1UL << 25) /**< Greater and less than comparison using the exponential moving average (EMA) is enabled. */
+#define CSEN_CTRL_EMACMPEN (0x1UL << 25) /**< Greater and Less Than Comparison Using the Exponential Moving Average (EMA) is Enabled */
#define _CSEN_CTRL_EMACMPEN_SHIFT 25 /**< Shift value for CSEN_EMACMPEN */
#define _CSEN_CTRL_EMACMPEN_MASK 0x2000000UL /**< Bit mask for CSEN_EMACMPEN */
#define _CSEN_CTRL_EMACMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
#define CSEN_CTRL_EMACMPEN_DEFAULT (_CSEN_CTRL_EMACMPEN_DEFAULT << 25) /**< Shifted mode DEFAULT for CSEN_CTRL */
-#define CSEN_CTRL_WARMUPMODE (0x1UL << 26) /**< Select Warmup mode for CSEN */
+#define CSEN_CTRL_WARMUPMODE (0x1UL << 26) /**< Select Warmup Mode for CSEN */
#define _CSEN_CTRL_WARMUPMODE_SHIFT 26 /**< Shift value for CSEN_WARMUPMODE */
#define _CSEN_CTRL_WARMUPMODE_MASK 0x4000000UL /**< Bit mask for CSEN_WARMUPMODE */
#define _CSEN_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
@@ -233,12 +240,12 @@ typedef struct
#define CSEN_CTRL_WARMUPMODE_DEFAULT (_CSEN_CTRL_WARMUPMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for CSEN_CTRL */
#define CSEN_CTRL_WARMUPMODE_NORMAL (_CSEN_CTRL_WARMUPMODE_NORMAL << 26) /**< Shifted mode NORMAL for CSEN_CTRL */
#define CSEN_CTRL_WARMUPMODE_KEEPCSENWARM (_CSEN_CTRL_WARMUPMODE_KEEPCSENWARM << 26) /**< Shifted mode KEEPCSENWARM for CSEN_CTRL */
-#define CSEN_CTRL_LOCALSENS (0x1UL << 27) /**< Sense local cap connection instead of the external kelvin connection. */
+#define CSEN_CTRL_LOCALSENS (0x1UL << 27) /**< Local Sensing Enable */
#define _CSEN_CTRL_LOCALSENS_SHIFT 27 /**< Shift value for CSEN_LOCALSENS */
#define _CSEN_CTRL_LOCALSENS_MASK 0x8000000UL /**< Bit mask for CSEN_LOCALSENS */
#define _CSEN_CTRL_LOCALSENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
#define CSEN_CTRL_LOCALSENS_DEFAULT (_CSEN_CTRL_LOCALSENS_DEFAULT << 27) /**< Shifted mode DEFAULT for CSEN_CTRL */
-#define CSEN_CTRL_CPACCURACY (0x1UL << 28) /**< Sets the accuracy of the charge pump. */
+#define CSEN_CTRL_CPACCURACY (0x1UL << 28) /**< Charge Pump Accuracy */
#define _CSEN_CTRL_CPACCURACY_SHIFT 28 /**< Shift value for CSEN_CPACCURACY */
#define _CSEN_CTRL_CPACCURACY_MASK 0x10000000UL /**< Bit mask for CSEN_CPACCURACY */
#define _CSEN_CTRL_CPACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
@@ -283,7 +290,7 @@ typedef struct
/* Bit fields for CSEN CMD */
#define _CSEN_CMD_RESETVALUE 0x00000000UL /**< Default value for CSEN_CMD */
#define _CSEN_CMD_MASK 0x00000001UL /**< Mask for CSEN_CMD */
-#define CSEN_CMD_START (0x1UL << 0) /**< Start a CSEN conversion. */
+#define CSEN_CMD_START (0x1UL << 0) /**< Start Software-Triggered Conversions */
#define _CSEN_CMD_START_SHIFT 0 /**< Shift value for CSEN_START */
#define _CSEN_CMD_START_MASK 0x1UL /**< Bit mask for CSEN_START */
#define _CSEN_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CMD */
@@ -292,7 +299,7 @@ typedef struct
/* Bit fields for CSEN STATUS */
#define _CSEN_STATUS_RESETVALUE 0x00000000UL /**< Default value for CSEN_STATUS */
#define _CSEN_STATUS_MASK 0x00000001UL /**< Mask for CSEN_STATUS */
-#define CSEN_STATUS_CSENBUSY (0x1UL << 0) /**< CSEN Busy */
+#define CSEN_STATUS_CSENBUSY (0x1UL << 0) /**< Busy Flag */
#define _CSEN_STATUS_CSENBUSY_SHIFT 0 /**< Shift value for CSEN_CSENBUSY */
#define _CSEN_STATUS_CSENBUSY_MASK 0x1UL /**< Bit mask for CSEN_CSENBUSY */
#define _CSEN_STATUS_CSENBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_STATUS */
@@ -529,42 +536,42 @@ typedef struct
/* Bit fields for CSEN APORTREQ */
#define _CSEN_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for CSEN_APORTREQ */
#define _CSEN_APORTREQ_MASK 0x000003FCUL /**< Mask for CSEN_APORTREQ */
-#define CSEN_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the bus connected to APORT2X is requested */
+#define CSEN_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 If the Bus Connected to APORT2X is Requested */
#define _CSEN_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for CSEN_APORT1XREQ */
#define _CSEN_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for CSEN_APORT1XREQ */
#define _CSEN_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */
#define CSEN_APORTREQ_APORT1XREQ_DEFAULT (_CSEN_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
-#define CSEN_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1X is requested */
+#define CSEN_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 If the Bus Connected to APORT1X is Requested */
#define _CSEN_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for CSEN_APORT1YREQ */
#define _CSEN_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for CSEN_APORT1YREQ */
#define _CSEN_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */
#define CSEN_APORTREQ_APORT1YREQ_DEFAULT (_CSEN_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
-#define CSEN_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 if the bus connected to APORT2X is requested */
+#define CSEN_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is Requested */
#define _CSEN_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for CSEN_APORT2XREQ */
#define _CSEN_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for CSEN_APORT2XREQ */
#define _CSEN_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */
#define CSEN_APORTREQ_APORT2XREQ_DEFAULT (_CSEN_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
-#define CSEN_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is requested */
+#define CSEN_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is Requested */
#define _CSEN_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for CSEN_APORT2YREQ */
#define _CSEN_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for CSEN_APORT2YREQ */
#define _CSEN_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */
#define CSEN_APORTREQ_APORT2YREQ_DEFAULT (_CSEN_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
-#define CSEN_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 if the bus connected to APORT3X is requested */
+#define CSEN_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is Requested */
#define _CSEN_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for CSEN_APORT3XREQ */
#define _CSEN_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for CSEN_APORT3XREQ */
#define _CSEN_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */
#define CSEN_APORTREQ_APORT3XREQ_DEFAULT (_CSEN_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
-#define CSEN_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is requested */
+#define CSEN_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is Requested */
#define _CSEN_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for CSEN_APORT3YREQ */
#define _CSEN_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for CSEN_APORT3YREQ */
#define _CSEN_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */
#define CSEN_APORTREQ_APORT3YREQ_DEFAULT (_CSEN_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
-#define CSEN_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 if the bus connected to APORT4X is requested */
+#define CSEN_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is Requested */
#define _CSEN_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for CSEN_APORT4XREQ */
#define _CSEN_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for CSEN_APORT4XREQ */
#define _CSEN_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */
#define CSEN_APORTREQ_APORT4XREQ_DEFAULT (_CSEN_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
-#define CSEN_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is requested */
+#define CSEN_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is Requested */
#define _CSEN_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for CSEN_APORT4YREQ */
#define _CSEN_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for CSEN_APORT4YREQ */
#define _CSEN_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */
@@ -573,42 +580,42 @@ typedef struct
/* Bit fields for CSEN APORTCONFLICT */
#define _CSEN_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for CSEN_APORTCONFLICT */
#define _CSEN_APORTCONFLICT_MASK 0x000003FCUL /**< Mask for CSEN_APORTCONFLICT */
-#define CSEN_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */
+#define CSEN_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */
#define _CSEN_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for CSEN_APORT1XCONFLICT */
#define _CSEN_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for CSEN_APORT1XCONFLICT */
#define _CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */
#define CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
-#define CSEN_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is in conflict with another peripheral */
+#define CSEN_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is in Conflict With Another Peripheral */
#define _CSEN_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for CSEN_APORT1YCONFLICT */
#define _CSEN_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for CSEN_APORT1YCONFLICT */
#define _CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */
#define CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
-#define CSEN_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 if the bus connected to APORT2X is in conflict with another peripheral */
+#define CSEN_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is in Conflict With Another Peripheral */
#define _CSEN_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORT2XCONFLICT */
#define _CSEN_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORT2XCONFLICT */
#define _CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */
#define CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
-#define CSEN_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is in conflict with another peripheral */
+#define CSEN_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is in Conflict With Another Peripheral */
#define _CSEN_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for CSEN_APORT2YCONFLICT */
#define _CSEN_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for CSEN_APORT2YCONFLICT */
#define _CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */
#define CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
-#define CSEN_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 if the bus connected to APORT3X is in conflict with another peripheral */
+#define CSEN_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is in Conflict With Another Peripheral */
#define _CSEN_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for CSEN_APORT3XCONFLICT */
#define _CSEN_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for CSEN_APORT3XCONFLICT */
#define _CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */
#define CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
-#define CSEN_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is in conflict with another peripheral */
+#define CSEN_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is in Conflict With Another Peripheral */
#define _CSEN_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for CSEN_APORT3YCONFLICT */
#define _CSEN_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for CSEN_APORT3YCONFLICT */
#define _CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */
#define CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
-#define CSEN_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 if the bus connected to APORT4X is in conflict with another peripheral */
+#define CSEN_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is in Conflict With Another Peripheral */
#define _CSEN_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for CSEN_APORT4XCONFLICT */
#define _CSEN_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for CSEN_APORT4XCONFLICT */
#define _CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */
#define CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
-#define CSEN_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is in conflict with another peripheral */
+#define CSEN_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is in Conflict With Another Peripheral */
#define _CSEN_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for CSEN_APORT4YCONFLICT */
#define _CSEN_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for CSEN_APORT4YCONFLICT */
#define _CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */
@@ -827,80 +834,47 @@ typedef struct
#define CSEN_DMCFG_CRMODE_DM12 (_CSEN_DMCFG_CRMODE_DM12 << 20) /**< Shifted mode DM12 for CSEN_DMCFG */
#define CSEN_DMCFG_CRMODE_DM14 (_CSEN_DMCFG_CRMODE_DM14 << 20) /**< Shifted mode DM14 for CSEN_DMCFG */
#define CSEN_DMCFG_CRMODE_DM16 (_CSEN_DMCFG_CRMODE_DM16 << 20) /**< Shifted mode DM16 for CSEN_DMCFG */
-#define CSEN_DMCFG_DMGRDIS (0x1UL << 28) /**< Disable delta modulator gain reduction. */
+#define CSEN_DMCFG_DMGRDIS (0x1UL << 28) /**< Delta Modulation Gain Step Reduction Disable */
#define _CSEN_DMCFG_DMGRDIS_SHIFT 28 /**< Shift value for CSEN_DMGRDIS */
#define _CSEN_DMCFG_DMGRDIS_MASK 0x10000000UL /**< Bit mask for CSEN_DMGRDIS */
#define _CSEN_DMCFG_DMGRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */
#define CSEN_DMCFG_DMGRDIS_DEFAULT (_CSEN_DMCFG_DMGRDIS_DEFAULT << 28) /**< Shifted mode DEFAULT for CSEN_DMCFG */
/* Bit fields for CSEN ANACTRL */
-#define _CSEN_ANACTRL_RESETVALUE 0x00000070UL /**< Default value for CSEN_ANACTRL */
-#define _CSEN_ANACTRL_MASK 0x03730771UL /**< Mask for CSEN_ANACTRL */
-#define CSEN_ANACTRL_CREFHALF (0x1UL << 0) /**< Reference capacitor divide by half. */
-#define _CSEN_ANACTRL_CREFHALF_SHIFT 0 /**< Shift value for CSEN_CREFHALF */
-#define _CSEN_ANACTRL_CREFHALF_MASK 0x1UL /**< Bit mask for CSEN_CREFHALF */
-#define _CSEN_ANACTRL_CREFHALF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */
-#define _CSEN_ANACTRL_CREFHALF_FULL 0x00000000UL /**< Mode FULL for CSEN_ANACTRL */
-#define _CSEN_ANACTRL_CREFHALF_HALF 0x00000001UL /**< Mode HALF for CSEN_ANACTRL */
-#define CSEN_ANACTRL_CREFHALF_DEFAULT (_CSEN_ANACTRL_CREFHALF_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_ANACTRL */
-#define CSEN_ANACTRL_CREFHALF_FULL (_CSEN_ANACTRL_CREFHALF_FULL << 0) /**< Shifted mode FULL for CSEN_ANACTRL */
-#define CSEN_ANACTRL_CREFHALF_HALF (_CSEN_ANACTRL_CREFHALF_HALF << 0) /**< Shifted mode HALF for CSEN_ANACTRL */
-#define _CSEN_ANACTRL_IREFPROG_SHIFT 4 /**< Shift value for CSEN_IREFPROG */
-#define _CSEN_ANACTRL_IREFPROG_MASK 0x70UL /**< Bit mask for CSEN_IREFPROG */
-#define _CSEN_ANACTRL_IREFPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for CSEN_ANACTRL */
-#define CSEN_ANACTRL_IREFPROG_DEFAULT (_CSEN_ANACTRL_IREFPROG_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_ANACTRL */
-#define _CSEN_ANACTRL_IDACIREFS_SHIFT 8 /**< Shift value for CSEN_IDACIREFS */
-#define _CSEN_ANACTRL_IDACIREFS_MASK 0x700UL /**< Bit mask for CSEN_IDACIREFS */
-#define _CSEN_ANACTRL_IDACIREFS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */
-#define CSEN_ANACTRL_IDACIREFS_DEFAULT (_CSEN_ANACTRL_IDACIREFS_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_ANACTRL */
-#define _CSEN_ANACTRL_DUTYSCALE_SHIFT 16 /**< Shift value for CSEN_DUTYSCALE */
-#define _CSEN_ANACTRL_DUTYSCALE_MASK 0x30000UL /**< Bit mask for CSEN_DUTYSCALE */
-#define _CSEN_ANACTRL_DUTYSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */
-#define _CSEN_ANACTRL_DUTYSCALE_DIV1 0x00000000UL /**< Mode DIV1 for CSEN_ANACTRL */
-#define _CSEN_ANACTRL_DUTYSCALE_DIV2 0x00000001UL /**< Mode DIV2 for CSEN_ANACTRL */
-#define _CSEN_ANACTRL_DUTYSCALE_DIV4 0x00000002UL /**< Mode DIV4 for CSEN_ANACTRL */
-#define _CSEN_ANACTRL_DUTYSCALE_DIV8 0x00000003UL /**< Mode DIV8 for CSEN_ANACTRL */
-#define CSEN_ANACTRL_DUTYSCALE_DEFAULT (_CSEN_ANACTRL_DUTYSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_ANACTRL */
-#define CSEN_ANACTRL_DUTYSCALE_DIV1 (_CSEN_ANACTRL_DUTYSCALE_DIV1 << 16) /**< Shifted mode DIV1 for CSEN_ANACTRL */
-#define CSEN_ANACTRL_DUTYSCALE_DIV2 (_CSEN_ANACTRL_DUTYSCALE_DIV2 << 16) /**< Shifted mode DIV2 for CSEN_ANACTRL */
-#define CSEN_ANACTRL_DUTYSCALE_DIV4 (_CSEN_ANACTRL_DUTYSCALE_DIV4 << 16) /**< Shifted mode DIV4 for CSEN_ANACTRL */
-#define CSEN_ANACTRL_DUTYSCALE_DIV8 (_CSEN_ANACTRL_DUTYSCALE_DIV8 << 16) /**< Shifted mode DIV8 for CSEN_ANACTRL */
-#define _CSEN_ANACTRL_TRSTPROG_SHIFT 20 /**< Shift value for CSEN_TRSTPROG */
-#define _CSEN_ANACTRL_TRSTPROG_MASK 0x700000UL /**< Bit mask for CSEN_TRSTPROG */
-#define _CSEN_ANACTRL_TRSTPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */
-#define CSEN_ANACTRL_TRSTPROG_DEFAULT (_CSEN_ANACTRL_TRSTPROG_DEFAULT << 20) /**< Shifted mode DEFAULT for CSEN_ANACTRL */
-#define _CSEN_ANACTRL_BIASPROG_SHIFT 24 /**< Shift value for CSEN_BIASPROG */
-#define _CSEN_ANACTRL_BIASPROG_MASK 0x3000000UL /**< Bit mask for CSEN_BIASPROG */
-#define _CSEN_ANACTRL_BIASPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */
-#define _CSEN_ANACTRL_BIASPROG_ONEX 0x00000000UL /**< Mode ONEX for CSEN_ANACTRL */
-#define _CSEN_ANACTRL_BIASPROG_TWOX 0x00000001UL /**< Mode TWOX for CSEN_ANACTRL */
-#define _CSEN_ANACTRL_BIASPROG_ONETENTH 0x00000002UL /**< Mode ONETENTH for CSEN_ANACTRL */
-#define _CSEN_ANACTRL_BIASPROG_HALF 0x00000003UL /**< Mode HALF for CSEN_ANACTRL */
-#define CSEN_ANACTRL_BIASPROG_DEFAULT (_CSEN_ANACTRL_BIASPROG_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_ANACTRL */
-#define CSEN_ANACTRL_BIASPROG_ONEX (_CSEN_ANACTRL_BIASPROG_ONEX << 24) /**< Shifted mode ONEX for CSEN_ANACTRL */
-#define CSEN_ANACTRL_BIASPROG_TWOX (_CSEN_ANACTRL_BIASPROG_TWOX << 24) /**< Shifted mode TWOX for CSEN_ANACTRL */
-#define CSEN_ANACTRL_BIASPROG_ONETENTH (_CSEN_ANACTRL_BIASPROG_ONETENTH << 24) /**< Shifted mode ONETENTH for CSEN_ANACTRL */
-#define CSEN_ANACTRL_BIASPROG_HALF (_CSEN_ANACTRL_BIASPROG_HALF << 24) /**< Shifted mode HALF for CSEN_ANACTRL */
+#define _CSEN_ANACTRL_RESETVALUE 0x00000070UL /**< Default value for CSEN_ANACTRL */
+#define _CSEN_ANACTRL_MASK 0x00700770UL /**< Mask for CSEN_ANACTRL */
+#define _CSEN_ANACTRL_IREFPROG_SHIFT 4 /**< Shift value for CSEN_IREFPROG */
+#define _CSEN_ANACTRL_IREFPROG_MASK 0x70UL /**< Bit mask for CSEN_IREFPROG */
+#define _CSEN_ANACTRL_IREFPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for CSEN_ANACTRL */
+#define CSEN_ANACTRL_IREFPROG_DEFAULT (_CSEN_ANACTRL_IREFPROG_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_ANACTRL */
+#define _CSEN_ANACTRL_IDACIREFS_SHIFT 8 /**< Shift value for CSEN_IDACIREFS */
+#define _CSEN_ANACTRL_IDACIREFS_MASK 0x700UL /**< Bit mask for CSEN_IDACIREFS */
+#define _CSEN_ANACTRL_IDACIREFS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */
+#define CSEN_ANACTRL_IDACIREFS_DEFAULT (_CSEN_ANACTRL_IDACIREFS_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_ANACTRL */
+#define _CSEN_ANACTRL_TRSTPROG_SHIFT 20 /**< Shift value for CSEN_TRSTPROG */
+#define _CSEN_ANACTRL_TRSTPROG_MASK 0x700000UL /**< Bit mask for CSEN_TRSTPROG */
+#define _CSEN_ANACTRL_TRSTPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */
+#define CSEN_ANACTRL_TRSTPROG_DEFAULT (_CSEN_ANACTRL_TRSTPROG_DEFAULT << 20) /**< Shifted mode DEFAULT for CSEN_ANACTRL */
/* Bit fields for CSEN IF */
#define _CSEN_IF_RESETVALUE 0x00000000UL /**< Default value for CSEN_IF */
#define _CSEN_IF_MASK 0x0000001FUL /**< Mask for CSEN_IF */
-#define CSEN_IF_CMP (0x1UL << 0) /**< CSEN Digital Comparator Interrupt Flag */
+#define CSEN_IF_CMP (0x1UL << 0) /**< Digital Comparator Interrupt Flag */
#define _CSEN_IF_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */
#define _CSEN_IF_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */
#define _CSEN_IF_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */
#define CSEN_IF_CMP_DEFAULT (_CSEN_IF_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IF */
-#define CSEN_IF_CONV (0x1UL << 1) /**< CSEN Conversion Done Interrupt Flag */
+#define CSEN_IF_CONV (0x1UL << 1) /**< Conversion Done Interrupt Flag */
#define _CSEN_IF_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */
#define _CSEN_IF_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */
#define _CSEN_IF_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */
#define CSEN_IF_CONV_DEFAULT (_CSEN_IF_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IF */
-#define CSEN_IF_EOS (0x1UL << 2) /**< CSEN End of Scan Interrupt Flag. */
+#define CSEN_IF_EOS (0x1UL << 2) /**< End of Scan Interrupt Flag. */
#define _CSEN_IF_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */
#define _CSEN_IF_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */
#define _CSEN_IF_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */
#define CSEN_IF_EOS_DEFAULT (_CSEN_IF_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IF */
-#define CSEN_IF_DMAOF (0x1UL << 3) /**< CSEN DMA Overflow Interrupt Flag. */
+#define CSEN_IF_DMAOF (0x1UL << 3) /**< DMA Overflow Interrupt Flag. */
#define _CSEN_IF_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */
#define _CSEN_IF_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */
#define _CSEN_IF_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */
@@ -998,6 +972,6 @@ typedef struct
#define _CSEN_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */
#define CSEN_IEN_APORTCONFLICT_DEFAULT (_CSEN_IEN_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IEN */
+/** @} */
/** @} End of group EFR32FG12P_CSEN */
/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_devinfo.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_devinfo.h
similarity index 89%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_devinfo.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_devinfo.h
index a3bce92e..2f6708b7 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_devinfo.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_devinfo.h
@@ -1,97 +1,104 @@
-/**************************************************************************//**
- * @file efr32fg12p_devinfo.h
+/***************************************************************************//**
+ * @file
* @brief EFR32FG12P_DEVINFO register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_DEVINFO
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P_DEVINFO Device Information and Calibration
* @{
- *****************************************************************************/
+ ******************************************************************************/
-typedef struct
-{
+/** DEVINFO Register Declaration */
+typedef struct {
__IM uint32_t CAL; /**< CRC of DI-page and calibration temperature */
- uint32_t RESERVED0[7]; /**< Reserved for future use **/
+ __IM uint32_t MODULEINFO; /**< Module trace information */
+ __IM uint32_t MODXOCAL; /**< Module Crystal Oscillator Calibration */
+ uint32_t RESERVED0[5U]; /**< Reserved for future use **/
__IM uint32_t EXTINFO; /**< External Component description */
- uint32_t RESERVED1[1]; /**< Reserved for future use **/
+ uint32_t RESERVED1[1U]; /**< Reserved for future use **/
__IM uint32_t EUI48L; /**< EUI48 OUI and Unique identifier */
__IM uint32_t EUI48H; /**< OUI */
__IM uint32_t CUSTOMINFO; /**< Custom information */
__IM uint32_t MEMINFO; /**< Flash page size and misc. chip information */
- uint32_t RESERVED2[2]; /**< Reserved for future use **/
+ uint32_t RESERVED2[2U]; /**< Reserved for future use **/
__IM uint32_t UNIQUEL; /**< Low 32 bits of device unique number */
__IM uint32_t UNIQUEH; /**< High 32 bits of device unique number */
__IM uint32_t MSIZE; /**< Flash and SRAM Memory size in kB */
__IM uint32_t PART; /**< Part description */
__IM uint32_t DEVINFOREV; /**< Device information page revision */
__IM uint32_t EMUTEMP; /**< EMU Temperature Calibration Information */
- uint32_t RESERVED3[2]; /**< Reserved for future use **/
+ uint32_t RESERVED3[2U]; /**< Reserved for future use **/
__IM uint32_t ADC0CAL0; /**< ADC0 calibration register 0 */
__IM uint32_t ADC0CAL1; /**< ADC0 calibration register 1 */
__IM uint32_t ADC0CAL2; /**< ADC0 calibration register 2 */
__IM uint32_t ADC0CAL3; /**< ADC0 calibration register 3 */
- uint32_t RESERVED4[4]; /**< Reserved for future use **/
+ uint32_t RESERVED4[4U]; /**< Reserved for future use **/
__IM uint32_t HFRCOCAL0; /**< HFRCO Calibration Register (4 MHz) */
- uint32_t RESERVED5[2]; /**< Reserved for future use **/
+ uint32_t RESERVED5[2U]; /**< Reserved for future use **/
__IM uint32_t HFRCOCAL3; /**< HFRCO Calibration Register (7 MHz) */
- uint32_t RESERVED6[2]; /**< Reserved for future use **/
+ uint32_t RESERVED6[2U]; /**< Reserved for future use **/
__IM uint32_t HFRCOCAL6; /**< HFRCO Calibration Register (13 MHz) */
__IM uint32_t HFRCOCAL7; /**< HFRCO Calibration Register (16 MHz) */
__IM uint32_t HFRCOCAL8; /**< HFRCO Calibration Register (19 MHz) */
- uint32_t RESERVED7[1]; /**< Reserved for future use **/
+ uint32_t RESERVED7[1U]; /**< Reserved for future use **/
__IM uint32_t HFRCOCAL10; /**< HFRCO Calibration Register (26 MHz) */
__IM uint32_t HFRCOCAL11; /**< HFRCO Calibration Register (32 MHz) */
__IM uint32_t HFRCOCAL12; /**< HFRCO Calibration Register (38 MHz) */
- uint32_t RESERVED8[11]; /**< Reserved for future use **/
+ uint32_t RESERVED8[11U]; /**< Reserved for future use **/
__IM uint32_t AUXHFRCOCAL0; /**< AUXHFRCO Calibration Register (4 MHz) */
- uint32_t RESERVED9[2]; /**< Reserved for future use **/
+ uint32_t RESERVED9[2U]; /**< Reserved for future use **/
__IM uint32_t AUXHFRCOCAL3; /**< AUXHFRCO Calibration Register (7 MHz) */
- uint32_t RESERVED10[2]; /**< Reserved for future use **/
+ uint32_t RESERVED10[2U]; /**< Reserved for future use **/
__IM uint32_t AUXHFRCOCAL6; /**< AUXHFRCO Calibration Register (13 MHz) */
__IM uint32_t AUXHFRCOCAL7; /**< AUXHFRCO Calibration Register (16 MHz) */
__IM uint32_t AUXHFRCOCAL8; /**< AUXHFRCO Calibration Register (19 MHz) */
- uint32_t RESERVED11[1]; /**< Reserved for future use **/
+ uint32_t RESERVED11[1U]; /**< Reserved for future use **/
__IM uint32_t AUXHFRCOCAL10; /**< AUXHFRCO Calibration Register (26 MHz) */
__IM uint32_t AUXHFRCOCAL11; /**< AUXHFRCO Calibration Register (32 MHz) */
__IM uint32_t AUXHFRCOCAL12; /**< AUXHFRCO Calibration Register (38 MHz) */
- uint32_t RESERVED12[11]; /**< Reserved for future use **/
+ uint32_t RESERVED12[11U]; /**< Reserved for future use **/
__IM uint32_t VMONCAL0; /**< VMON Calibration Register 0 */
__IM uint32_t VMONCAL1; /**< VMON Calibration Register 1 */
__IM uint32_t VMONCAL2; /**< VMON Calibration Register 2 */
- uint32_t RESERVED13[3]; /**< Reserved for future use **/
+ uint32_t RESERVED13[3U]; /**< Reserved for future use **/
__IM uint32_t IDAC0CAL0; /**< IDAC0 Calibration Register 0 */
__IM uint32_t IDAC0CAL1; /**< IDAC0 Calibration Register 1 */
- uint32_t RESERVED14[2]; /**< Reserved for future use **/
+ uint32_t RESERVED14[2U]; /**< Reserved for future use **/
__IM uint32_t DCDCLNVCTRL0; /**< DCDC Low-noise VREF Trim Register 0 */
__IM uint32_t DCDCLPVCTRL0; /**< DCDC Low-power VREF Trim Register 0 */
__IM uint32_t DCDCLPVCTRL1; /**< DCDC Low-power VREF Trim Register 1 */
@@ -115,7 +122,7 @@ typedef struct
__IM uint32_t OPA2CAL2; /**< OPA2 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */
__IM uint32_t OPA2CAL3; /**< OPA2 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */
__IM uint32_t CSENGAINCAL; /**< Cap Sense Gain Adjustment */
- uint32_t RESERVED15[3]; /**< Reserved for future use **/
+ uint32_t RESERVED15[3U]; /**< Reserved for future use **/
__IM uint32_t OPA0CAL4; /**< OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */
__IM uint32_t OPA0CAL5; /**< OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */
__IM uint32_t OPA0CAL6; /**< OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */
@@ -130,10 +137,12 @@ typedef struct
__IM uint32_t OPA2CAL7; /**< OPA2 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */
} DEVINFO_TypeDef; /** @} */
-/**************************************************************************//**
- * @defgroup EFR32FG12P_DEVINFO_BitFields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_DEVINFO
+ * @{
+ * @defgroup EFR32FG12P_DEVINFO_BitFields DEVINFO Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for DEVINFO CAL */
#define _DEVINFO_CAL_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_CAL */
@@ -142,21 +151,79 @@ typedef struct
#define _DEVINFO_CAL_TEMP_SHIFT 16 /**< Shift value for TEMP */
#define _DEVINFO_CAL_TEMP_MASK 0xFF0000UL /**< Bit mask for TEMP */
+/* Bit fields for DEVINFO MODULEINFO */
+#define _DEVINFO_MODULEINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_HWREV_SHIFT 0 /**< Shift value for HWREV */
+#define _DEVINFO_MODULEINFO_HWREV_MASK 0x1FUL /**< Bit mask for HWREV */
+#define _DEVINFO_MODULEINFO_ANTENNA_SHIFT 5 /**< Shift value for ANTENNA */
+#define _DEVINFO_MODULEINFO_ANTENNA_MASK 0xE0UL /**< Bit mask for ANTENNA */
+#define _DEVINFO_MODULEINFO_ANTENNA_BUILTIN 0x00000000UL /**< Mode BUILTIN for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_ANTENNA_CONNECTOR 0x00000001UL /**< Mode CONNECTOR for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_ANTENNA_RFPAD 0x00000002UL /**< Mode RFPAD for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_ANTENNA_BUILTIN (_DEVINFO_MODULEINFO_ANTENNA_BUILTIN << 5) /**< Shifted mode BUILTIN for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_ANTENNA_CONNECTOR (_DEVINFO_MODULEINFO_ANTENNA_CONNECTOR << 5) /**< Shifted mode CONNECTOR for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_ANTENNA_RFPAD (_DEVINFO_MODULEINFO_ANTENNA_RFPAD << 5) /**< Shifted mode RFPAD for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_MODNUMBER_SHIFT 8 /**< Shift value for MODNUMBER */
+#define _DEVINFO_MODULEINFO_MODNUMBER_MASK 0x7F00UL /**< Bit mask for MODNUMBER */
+#define _DEVINFO_MODULEINFO_TYPE_SHIFT 15 /**< Shift value for TYPE */
+#define _DEVINFO_MODULEINFO_TYPE_MASK 0x8000UL /**< Bit mask for TYPE */
+#define _DEVINFO_MODULEINFO_TYPE_PCB 0x00000000UL /**< Mode PCB for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_TYPE_SIP 0x00000001UL /**< Mode SIP for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_TYPE_PCB (_DEVINFO_MODULEINFO_TYPE_PCB << 15) /**< Shifted mode PCB for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_TYPE_SIP (_DEVINFO_MODULEINFO_TYPE_SIP << 15) /**< Shifted mode SIP for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_LFXO_SHIFT 16 /**< Shift value for LFXO */
+#define _DEVINFO_MODULEINFO_LFXO_MASK 0x10000UL /**< Bit mask for LFXO */
+#define _DEVINFO_MODULEINFO_LFXO_NONE 0x00000000UL /**< Mode NONE for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_LFXO_PRESENT 0x00000001UL /**< Mode PRESENT for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_LFXO_NONE (_DEVINFO_MODULEINFO_LFXO_NONE << 16) /**< Shifted mode NONE for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_LFXO_PRESENT (_DEVINFO_MODULEINFO_LFXO_PRESENT << 16) /**< Shifted mode PRESENT for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_EXPRESS_SHIFT 17 /**< Shift value for EXPRESS */
+#define _DEVINFO_MODULEINFO_EXPRESS_MASK 0x20000UL /**< Bit mask for EXPRESS */
+#define _DEVINFO_MODULEINFO_EXPRESS_SUPPORTED 0x00000000UL /**< Mode SUPPORTED for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_EXPRESS_NONE 0x00000001UL /**< Mode NONE for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_EXPRESS_SUPPORTED (_DEVINFO_MODULEINFO_EXPRESS_SUPPORTED << 17) /**< Shifted mode SUPPORTED for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_EXPRESS_NONE (_DEVINFO_MODULEINFO_EXPRESS_NONE << 17) /**< Shifted mode NONE for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_LFXOCALVAL_SHIFT 18 /**< Shift value for LFXOCALVAL */
+#define _DEVINFO_MODULEINFO_LFXOCALVAL_MASK 0x40000UL /**< Bit mask for LFXOCALVAL */
+#define _DEVINFO_MODULEINFO_LFXOCALVAL_VALID 0x00000000UL /**< Mode VALID for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID 0x00000001UL /**< Mode NOTVALID for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_LFXOCALVAL_VALID (_DEVINFO_MODULEINFO_LFXOCALVAL_VALID << 18) /**< Shifted mode VALID for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID (_DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID << 18) /**< Shifted mode NOTVALID for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_HFXOCALVAL_SHIFT 19 /**< Shift value for HFXOCALVAL */
+#define _DEVINFO_MODULEINFO_HFXOCALVAL_MASK 0x80000UL /**< Bit mask for HFXOCALVAL */
+#define _DEVINFO_MODULEINFO_HFXOCALVAL_VALID 0x00000000UL /**< Mode VALID for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID 0x00000001UL /**< Mode NOTVALID for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_HFXOCALVAL_VALID (_DEVINFO_MODULEINFO_HFXOCALVAL_VALID << 19) /**< Shifted mode VALID for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID (_DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID << 19) /**< Shifted mode NOTVALID for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_RESERVED1_SHIFT 20 /**< Shift value for RESERVED1 */
+#define _DEVINFO_MODULEINFO_RESERVED1_MASK 0xFFF00000UL /**< Bit mask for RESERVED1 */
+
+/* Bit fields for DEVINFO MODXOCAL */
+#define _DEVINFO_MODXOCAL_MASK 0x0000FFFFUL /**< Mask for DEVINFO_MODXOCAL */
+#define _DEVINFO_MODXOCAL_HFXOCTUNE_SHIFT 0 /**< Shift value for HFXOCTUNE */
+#define _DEVINFO_MODXOCAL_HFXOCTUNE_MASK 0x1FFUL /**< Bit mask for HFXOCTUNE */
+#define _DEVINFO_MODXOCAL_LFXOTUNING_SHIFT 9 /**< Shift value for LFXOTUNING */
+#define _DEVINFO_MODXOCAL_LFXOTUNING_MASK 0xFE00UL /**< Bit mask for LFXOTUNING */
+
/* Bit fields for DEVINFO EXTINFO */
#define _DEVINFO_EXTINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_EXTINFO */
#define _DEVINFO_EXTINFO_TYPE_SHIFT 0 /**< Shift value for TYPE */
#define _DEVINFO_EXTINFO_TYPE_MASK 0xFFUL /**< Bit mask for TYPE */
#define _DEVINFO_EXTINFO_TYPE_IS25LQ040B 0x00000001UL /**< Mode IS25LQ040B for DEVINFO_EXTINFO */
#define _DEVINFO_EXTINFO_TYPE_AT25S041 0x00000002UL /**< Mode AT25S041 for DEVINFO_EXTINFO */
+#define _DEVINFO_EXTINFO_TYPE_WF200 0x00000003UL /**< Mode WF200 for DEVINFO_EXTINFO */
#define _DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */
#define DEVINFO_EXTINFO_TYPE_IS25LQ040B (_DEVINFO_EXTINFO_TYPE_IS25LQ040B << 0) /**< Shifted mode IS25LQ040B for DEVINFO_EXTINFO */
#define DEVINFO_EXTINFO_TYPE_AT25S041 (_DEVINFO_EXTINFO_TYPE_AT25S041 << 0) /**< Shifted mode AT25S041 for DEVINFO_EXTINFO */
+#define DEVINFO_EXTINFO_TYPE_WF200 (_DEVINFO_EXTINFO_TYPE_WF200 << 0) /**< Shifted mode WF200 for DEVINFO_EXTINFO */
#define DEVINFO_EXTINFO_TYPE_NONE (_DEVINFO_EXTINFO_TYPE_NONE << 0) /**< Shifted mode NONE for DEVINFO_EXTINFO */
#define _DEVINFO_EXTINFO_CONNECTION_SHIFT 8 /**< Shift value for CONNECTION */
#define _DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL /**< Bit mask for CONNECTION */
#define _DEVINFO_EXTINFO_CONNECTION_SPI 0x00000001UL /**< Mode SPI for DEVINFO_EXTINFO */
+#define _DEVINFO_EXTINFO_CONNECTION_SDIO 0x00000002UL /**< Mode SDIO for DEVINFO_EXTINFO */
#define _DEVINFO_EXTINFO_CONNECTION_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */
#define DEVINFO_EXTINFO_CONNECTION_SPI (_DEVINFO_EXTINFO_CONNECTION_SPI << 8) /**< Shifted mode SPI for DEVINFO_EXTINFO */
+#define DEVINFO_EXTINFO_CONNECTION_SDIO (_DEVINFO_EXTINFO_CONNECTION_SDIO << 8) /**< Shifted mode SDIO for DEVINFO_EXTINFO */
#define DEVINFO_EXTINFO_CONNECTION_NONE (_DEVINFO_EXTINFO_CONNECTION_NONE << 8) /**< Shifted mode NONE for DEVINFO_EXTINFO */
#define _DEVINFO_EXTINFO_REV_SHIFT 16 /**< Shift value for REV */
#define _DEVINFO_EXTINFO_REV_MASK 0xFF0000UL /**< Bit mask for REV */
@@ -242,7 +309,6 @@ typedef struct
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B 0x0000001AUL /**< Mode EFR32FG1B for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V 0x0000001BUL /**< Mode EFR32FG1V for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P 0x0000001CUL /**< Mode EFR32MG12P for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P 0x0000001CUL /**< Mode EFR32MG2P for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B 0x0000001DUL /**< Mode EFR32MG12B for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V 0x0000001EUL /**< Mode EFR32MG12V for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P 0x0000001FUL /**< Mode EFR32BG12P for DEVINFO_PART */
@@ -257,29 +323,43 @@ typedef struct
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P 0x0000002BUL /**< Mode EFR32BG13P for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B 0x0000002CUL /**< Mode EFR32BG13B for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V 0x0000002DUL /**< Mode EFR32BG13V for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P 0x0000002EUL /**< Mode EFR32ZG13P for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L 0x0000002FUL /**< Mode EFR32ZG13L for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S 0x00000030UL /**< Mode EFR32ZG13S for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P 0x00000031UL /**< Mode EFR32FG13P for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B 0x00000032UL /**< Mode EFR32FG13B for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V 0x00000033UL /**< Mode EFR32FG13V for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P 0x00000034UL /**< Mode EFR32MG14P for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B 0x00000035UL /**< Mode EFR32MG14B for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V 0x00000036UL /**< Mode EFR32MG14V for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P 0x00000037UL /**< Mode EFR32BG14P for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B 0x00000038UL /**< Mode EFR32BG14B for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V 0x00000039UL /**< Mode EFR32BG14V for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P 0x0000003AUL /**< Mode EFR32ZG14P for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P 0x0000003DUL /**< Mode EFR32FG14P for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B 0x0000003EUL /**< Mode EFR32FG14B for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V 0x0000003FUL /**< Mode EFR32FG14V for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 0x00000047UL /**< Mode EFM32G for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_G 0x00000047UL /**< Mode G for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_GG 0x00000048UL /**< Mode GG for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL /**< Mode TG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 0x00000049UL /**< Mode EFM32TG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL /**< Mode TG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 0x0000004AUL /**< Mode EFM32LG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_LG 0x0000004AUL /**< Mode LG for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_WG 0x0000004BUL /**< Mode WG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_ZG 0x0000004CUL /**< Mode ZG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 0x0000004CUL /**< Mode EFM32ZG for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL /**< Mode HG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 0x0000004DUL /**< Mode EFM32HG for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL /**< Mode HG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B 0x00000051UL /**< Mode EFM32PG1B for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B 0x00000055UL /**< Mode EFM32PG12B for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B 0x00000057UL /**< Mode EFM32JG12B for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B 0x00000059UL /**< Mode EFM32PG13B for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B 0x0000005BUL /**< Mode EFM32JG13B for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B 0x00000064UL /**< Mode EFM32GG11B for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B 0x00000067UL /**< Mode EFM32TG11B for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B 0x0000006AUL /**< Mode EFM32GG12B for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 0x00000078UL /**< Mode EZR32LG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 0x00000079UL /**< Mode EZR32WG for DEVINFO_PART */
#define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 0x0000007AUL /**< Mode EZR32HG for DEVINFO_PART */
@@ -293,7 +373,6 @@ typedef struct
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B << 16) /**< Shifted mode EFR32FG1B for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V << 16) /**< Shifted mode EFR32FG1V for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P << 16) /**< Shifted mode EFR32MG12P for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P << 16) /**< Shifted mode EFR32MG2P for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B << 16) /**< Shifted mode EFR32MG12B for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V << 16) /**< Shifted mode EFR32MG12V for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P << 16) /**< Shifted mode EFR32BG12P for DEVINFO_PART */
@@ -308,29 +387,43 @@ typedef struct
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P << 16) /**< Shifted mode EFR32BG13P for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B << 16) /**< Shifted mode EFR32BG13B for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V << 16) /**< Shifted mode EFR32BG13V for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P << 16) /**< Shifted mode EFR32ZG13P for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L << 16) /**< Shifted mode EFR32ZG13L for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S << 16) /**< Shifted mode EFR32ZG13S for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P << 16) /**< Shifted mode EFR32FG13P for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B << 16) /**< Shifted mode EFR32FG13B for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V << 16) /**< Shifted mode EFR32FG13V for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P << 16) /**< Shifted mode EFR32MG14P for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B << 16) /**< Shifted mode EFR32MG14B for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V << 16) /**< Shifted mode EFR32MG14V for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P << 16) /**< Shifted mode EFR32BG14P for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B << 16) /**< Shifted mode EFR32BG14B for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V << 16) /**< Shifted mode EFR32BG14V for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P (_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P << 16) /**< Shifted mode EFR32ZG14P for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P << 16) /**< Shifted mode EFR32FG14P for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B << 16) /**< Shifted mode EFR32FG14B for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V << 16) /**< Shifted mode EFR32FG14V for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32G (_DEVINFO_PART_DEVICE_FAMILY_EFM32G << 16) /**< Shifted mode EFM32G for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_G (_DEVINFO_PART_DEVICE_FAMILY_G << 16) /**< Shifted mode G for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32GG (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_GG (_DEVINFO_PART_DEVICE_FAMILY_GG << 16) /**< Shifted mode GG for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_TG (_DEVINFO_PART_DEVICE_FAMILY_TG << 16) /**< Shifted mode TG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32TG (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG << 16) /**< Shifted mode EFM32TG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_TG (_DEVINFO_PART_DEVICE_FAMILY_TG << 16) /**< Shifted mode TG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32LG (_DEVINFO_PART_DEVICE_FAMILY_EFM32LG << 16) /**< Shifted mode EFM32LG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_LG (_DEVINFO_PART_DEVICE_FAMILY_LG << 16) /**< Shifted mode LG for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFM32WG (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_WG (_DEVINFO_PART_DEVICE_FAMILY_WG << 16) /**< Shifted mode WG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32WG (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_ZG (_DEVINFO_PART_DEVICE_FAMILY_ZG << 16) /**< Shifted mode ZG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32ZG (_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG << 16) /**< Shifted mode EFM32ZG for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_HG (_DEVINFO_PART_DEVICE_FAMILY_HG << 16) /**< Shifted mode HG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32HG (_DEVINFO_PART_DEVICE_FAMILY_EFM32HG << 16) /**< Shifted mode EFM32HG for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_HG (_DEVINFO_PART_DEVICE_FAMILY_HG << 16) /**< Shifted mode HG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B << 16) /**< Shifted mode EFM32PG12B for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B << 16) /**< Shifted mode EFM32JG12B for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B << 16) /**< Shifted mode EFM32PG13B for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B << 16) /**< Shifted mode EFM32JG13B for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B << 16) /**< Shifted mode EFM32GG11B for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B << 16) /**< Shifted mode EFM32TG11B for DEVINFO_PART */
+#define DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B << 16) /**< Shifted mode EFM32GG12B for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EZR32LG (_DEVINFO_PART_DEVICE_FAMILY_EZR32LG << 16) /**< Shifted mode EZR32LG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EZR32WG (_DEVINFO_PART_DEVICE_FAMILY_EZR32WG << 16) /**< Shifted mode EZR32WG for DEVINFO_PART */
#define DEVINFO_PART_DEVICE_FAMILY_EZR32HG (_DEVINFO_PART_DEVICE_FAMILY_EZR32HG << 16) /**< Shifted mode EZR32HG for DEVINFO_PART */
@@ -1293,6 +1386,6 @@ typedef struct
#define _DEVINFO_OPA2CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
#define _DEVINFO_OPA2CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
+/** @} */
/** @} End of group EFR32FG12P_DEVINFO */
/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_dma_descriptor.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_dma_descriptor.h
similarity index 54%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_dma_descriptor.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_dma_descriptor.h
index fe88679f..551211d2 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_dma_descriptor.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_dma_descriptor.h
@@ -1,44 +1,49 @@
-/**************************************************************************//**
- * @file efr32fg12p_dma_descriptor.h
+/***************************************************************************//**
+ * @file
* @brief EFR32FG12P_DMA_DESCRIPTOR register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_DMA_DESCRIPTOR
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P_DMA_DESCRIPTOR DMA Descriptor
* @{
- *****************************************************************************/
-typedef struct
-{
+ ******************************************************************************/
+/** DMA_DESCRIPTOR Register Declaration */
+typedef struct {
/* Note! Use of double __IOM (volatile) qualifier to ensure that both */
/* pointer and referenced memory are declared volatile. */
__IOM uint32_t CTRL; /**< DMA control register */
@@ -48,5 +53,3 @@ typedef struct
} DMA_DESCRIPTOR_TypeDef; /**< @} */
/** @} End of group Parts */
-
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_dmareq.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_dmareq.h
similarity index 87%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_dmareq.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_dmareq.h
index cc12aba9..e030f104 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_dmareq.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_dmareq.h
@@ -1,43 +1,50 @@
-/**************************************************************************//**
- * @file efr32fg12p_dmareq.h
+/***************************************************************************//**
+ * @file
* @brief EFR32FG12P_DMAREQ register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
+ ******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_DMAREQ_BitFields
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_DMAREQ DMAREQ
* @{
- *****************************************************************************/
+ * @defgroup EFR32FG12P_DMAREQ_BitFields DMAREQ Bit Fields
+ * @{
+ ******************************************************************************/
#define DMAREQ_PRS_REQ0 ((1 << 16) + 0) /**< DMA channel select for PRS_REQ0 */
#define DMAREQ_PRS_REQ1 ((1 << 16) + 1) /**< DMA channel select for PRS_REQ1 */
#define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /**< DMA channel select for ADC0_SINGLE */
@@ -105,6 +112,6 @@
#define DMAREQ_CRYPTO1_DATA1WR ((52 << 16) + 3) /**< DMA channel select for CRYPTO1_DATA1WR */
#define DMAREQ_CRYPTO1_DATA1RD ((52 << 16) + 4) /**< DMA channel select for CRYPTO1_DATA1RD */
+/** @} */
/** @} End of group EFR32FG12P_DMAREQ */
/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_emu.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_emu.h
similarity index 95%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_emu.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_emu.h
index 844135ca..8a33c205 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_emu.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_emu.h
@@ -1,104 +1,111 @@
-/**************************************************************************//**
- * @file efr32fg12p_emu.h
+/***************************************************************************//**
+ * @file
* @brief EFR32FG12P_EMU register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_EMU
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P_EMU EMU
* @{
* @brief EFR32FG12P_EMU Register Declaration
- *****************************************************************************/
-typedef struct
-{
+ ******************************************************************************/
+/** EMU Register Declaration */
+typedef struct {
__IOM uint32_t CTRL; /**< Control Register */
__IM uint32_t STATUS; /**< Status Register */
__IOM uint32_t LOCK; /**< Configuration Lock Register */
__IOM uint32_t RAM0CTRL; /**< Memory Control Register */
__IOM uint32_t CMD; /**< Command Register */
- uint32_t RESERVED0[1]; /**< Reserved for future use **/
+ uint32_t RESERVED0[1U]; /**< Reserved for future use **/
__IOM uint32_t EM4CTRL; /**< EM4 Control Register */
- __IOM uint32_t TEMPLIMITS; /**< Temperature limits for interrupt generation */
- __IM uint32_t TEMP; /**< Value of last temperature measurement */
+ __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */
+ __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */
__IM uint32_t IF; /**< Interrupt Flag Register */
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
__IOM uint32_t IEN; /**< Interrupt Enable Register */
__IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */
__IOM uint32_t PWRCFG; /**< Power Configuration Register */
- __IOM uint32_t PWRCTRL; /**< Power Control Register. */
+ __IOM uint32_t PWRCTRL; /**< Power Control Register */
__IOM uint32_t DCDCCTRL; /**< DCDC Control */
- uint32_t RESERVED1[2]; /**< Reserved for future use **/
+ uint32_t RESERVED1[2U]; /**< Reserved for future use **/
__IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */
__IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */
__IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */
__IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */
__IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */
- uint32_t RESERVED2[1]; /**< Reserved for future use **/
+ uint32_t RESERVED2[1U]; /**< Reserved for future use **/
__IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */
- uint32_t RESERVED3[1]; /**< Reserved for future use **/
+ uint32_t RESERVED3[1U]; /**< Reserved for future use **/
__IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */
__IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */
- uint32_t RESERVED4[1]; /**< Reserved for future use **/
+ uint32_t RESERVED4[1U]; /**< Reserved for future use **/
__IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */
- uint32_t RESERVED5[5]; /**< Reserved for future use **/
+ uint32_t RESERVED5[5U]; /**< Reserved for future use **/
__IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */
__IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */
__IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */
__IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */
- uint32_t RESERVED6[5]; /**< Reserved for future use **/
+ uint32_t RESERVED6[5U]; /**< Reserved for future use **/
__IOM uint32_t RAM1CTRL; /**< Memory Control Register */
__IOM uint32_t RAM2CTRL; /**< Memory Control Register */
- uint32_t RESERVED7[12]; /**< Reserved for future use **/
- __IOM uint32_t DCDCLPEM01CFG; /**< Configuration bits for low power mode to be applied during EM01, this field is only relevant if LP mode is used in EM01. */
+ uint32_t RESERVED7[12U]; /**< Reserved for future use **/
+ __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */
- uint32_t RESERVED8[4]; /**< Reserved for future use **/
- __IOM uint32_t EM23PERNORETAINCMD; /**< Clears corresponding bits in EM23PERNORETAINSTATUS unlocking access to peripheral */
- __IM uint32_t EM23PERNORETAINSTATUS; /**< Status indicating if peripherals were powered down in EM23, subsequently locking access to it. */
- __IOM uint32_t EM23PERNORETAINCTRL; /**< When set corresponding peripherals may get powered down in EM23 */
+ uint32_t RESERVED8[4U]; /**< Reserved for future use **/
+ __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */
+ __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */
+ __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */
} EMU_TypeDef; /** @} */
-/**************************************************************************//**
- * @defgroup EFR32FG12P_EMU_BitFields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_EMU
+ * @{
+ * @defgroup EFR32FG12P_EMU_BitFields EMU Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for EMU CTRL */
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
@@ -118,7 +125,7 @@ typedef struct
#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */
#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */
-#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically configures Flash, Ram and Frequency to wakeup from EM2 or EM3 at low voltage */
+#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */
#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */
#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */
#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
@@ -147,32 +154,32 @@ typedef struct
/* Bit fields for EMU STATUS */
#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */
#define _EMU_STATUS_MASK 0x0417011FUL /**< Mask for EMU_STATUS */
-#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON ready */
+#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */
#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */
#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */
#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */
-#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel. */
+#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */
#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */
#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */
#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */
-#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel. */
+#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */
#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */
#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */
#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */
-#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel. */
+#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */
#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */
#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */
#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */
-#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel. */
+#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */
#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */
#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */
#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */
-#define EMU_STATUS_VMONFVDD (0x1UL << 8) /**< VMON VDDFLASH Channel. */
+#define EMU_STATUS_VMONFVDD (0x1UL << 8) /**< VMON VDDFLASH Channel */
#define _EMU_STATUS_VMONFVDD_SHIFT 8 /**< Shift value for EMU_VMONFVDD */
#define _EMU_STATUS_VMONFVDD_MASK 0x100UL /**< Bit mask for EMU_VMONFVDD */
#define _EMU_STATUS_VMONFVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
@@ -187,7 +194,7 @@ typedef struct
#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */
#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */
#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */
-#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is busy Scaling Voltage */
+#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */
#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */
#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */
#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
@@ -213,13 +220,13 @@ typedef struct
#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */
-#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */
+#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */
-#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */
+#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */
@@ -249,12 +256,12 @@ typedef struct
#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */
#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */
#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */
-#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to scale to Voltage Scale Level 0 */
+#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */
#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */
#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */
#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */
#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */
-#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to scale to Voltage Scale Level 2 */
+#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */
#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */
#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */
#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */
@@ -272,17 +279,17 @@ typedef struct
#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */
#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */
-#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain during EM4 */
+#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */
#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */
#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */
#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
-#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain during EM4 */
+#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */
#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */
#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */
#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
-#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain during EM4S */
+#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */
#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */
#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */
#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
@@ -313,7 +320,7 @@ typedef struct
#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */
#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */
#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */
-#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup due to low/high temperature */
+#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */
#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */
#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */
#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */
@@ -380,32 +387,32 @@ typedef struct
#define _EMU_IF_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */
#define _EMU_IF_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
#define EMU_IF_VMONFVDDRISE_DEFAULT (_EMU_IF_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IF */
-#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET current limit hit */
+#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */
#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */
-#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET current limit hit */
+#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */
#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */
-#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP mode is running */
+#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */
#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */
#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */
#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */
-#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN mode is running */
+#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */
#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */
#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */
#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */
-#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in bypass */
+#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */
#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */
#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */
#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */
-#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ from EM2 and EM3 */
+#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */
#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */
#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */
#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
@@ -749,13 +756,13 @@ typedef struct
#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */
-#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */
#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */
+#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */
#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */
#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */
#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */
-#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */
#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */
+#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */
#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */
#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */
@@ -783,7 +790,7 @@ typedef struct
#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */
#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */
#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */
-#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This field selects the input for the regulator. */
+#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */
#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */
#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */
#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */
@@ -835,22 +842,22 @@ typedef struct
/* Bit fields for EMU DCDCMISCCTRL */
#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */
#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */
-#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC into CCM mode in low noise operation */
+#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */
#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */
#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */
#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
-#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP mode hysteresis in the state machine control */
+#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */
#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */
#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */
#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
-#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator threshold on the high side */
+#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */
#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */
#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */
#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
-#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC into CCM mode immediately, based on LNFORCECCM */
+#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */
#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */
#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */
#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
@@ -961,7 +968,7 @@ typedef struct
/* Bit fields for EMU DCDCLPVCTRL */
#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */
#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */
-#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low power feedback attenuation */
+#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */
#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */
#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */
#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */
@@ -982,7 +989,7 @@ typedef struct
#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */
#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */
#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */
-#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP mode duty cycling enable */
+#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */
#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */
#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */
#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */
@@ -1007,7 +1014,7 @@ typedef struct
/* Bit fields for EMU DCDCSYNC */
#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */
#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */
-#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy. */
+#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */
#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */
#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */
#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */
@@ -1120,7 +1127,7 @@ typedef struct
#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */
#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
-#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention disable */
+#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */
#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */
#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */
#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
@@ -1183,82 +1190,82 @@ typedef struct
/* Bit fields for EMU EM23PERNORETAINCMD */
#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */
#define _EMU_EM23PERNORETAINCMD_MASK 0x0000FFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears status bit of ACMP0 and unlocks access to it */
+#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */
#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */
#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */
#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears status bit of ACMP1 and unlocks access to it */
+#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */
#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */
#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */
#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears status bit of PCNT0 and unlocks access to it */
+#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */
#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */
#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */
#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears status bit of PCNT1 and unlocks access to it */
+#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */
#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */
#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */
#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears status bit of PCNT2 and unlocks access to it */
+#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */
#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */
#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */
#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears status bit of I2C0 and unlocks access to it */
+#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */
#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */
#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */
#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears status bit of I2C1 and unlocks access to it */
+#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */
#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */
#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */
#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears status bit of DAC0 and unlocks access to it */
+#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */
#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */
#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */
#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears status bit of IDAC0 and unlocks access to it */
+#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */
#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */
#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */
#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears status bit of ADC0 and unlocks access to it */
+#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */
#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */
#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */
#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears status bit of LETIMER0 and unlocks access to it */
+#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */
#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */
#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */
#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears status bit of WDOG0 and unlocks access to it */
+#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */
#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */
#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */
#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears status bit of WDOG1 and unlocks access to it */
+#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */
#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */
#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */
#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears status bit of LESENSE0 and unlocks access to it */
+#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */
#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */
#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */
#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears status bit of CSEN and unlocks access to it */
+#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */
#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */
#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */
#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears status bit of LEUART0 and unlocks access to it */
+#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */
#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */
#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */
#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
@@ -1267,82 +1274,82 @@ typedef struct
/* Bit fields for EMU EM23PERNORETAINSTATUS */
#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */
#define _EMU_EM23PERNORETAINSTATUS_MASK 0x0000FFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates if ACMP0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
+#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */
#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */
#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */
#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates if ACMP1 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
+#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */
#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */
#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */
#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates if PCNT0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
+#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */
#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */
#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */
#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates if PCNT1 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
+#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */
#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */
#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */
#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates if PCNT2 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
+#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */
#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */
#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */
#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates if I2C0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
+#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */
#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */
#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */
#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates if I2C1 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
+#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */
#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */
#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */
#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates if DAC0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
+#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */
#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */
#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */
#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates if IDAC0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
+#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */
#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */
#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */
#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates if ADC0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
+#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */
#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */
#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */
#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates if LETIMER0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
+#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */
#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */
#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */
#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates if WDOG0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
+#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */
#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */
#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */
#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates if WDOG1 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
+#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */
#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */
#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */
#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates if LESENSE0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
+#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */
#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */
#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */
#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates if CSEN powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
+#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */
#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */
#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */
#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates if LEUART0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
+#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */
#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */
#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */
#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
@@ -1351,87 +1358,87 @@ typedef struct
/* Bit fields for EMU EM23PERNORETAINCTRL */
#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */
#define _EMU_EM23PERNORETAINCTRL_MASK 0x0000FFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow power down of ACMP0 during EM23 */
+#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */
#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */
#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */
#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow power down of ACMP1 during EM23 */
+#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */
#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */
#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */
#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow power down of PCNT0 during EM23 */
+#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */
#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */
#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */
#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow power down of PCNT1 during EM23 */
+#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */
#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */
#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */
#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow power down of PCNT2 during EM23 */
+#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */
#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */
#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */
#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow power down of I2C0 during EM23 */
+#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */
#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */
#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */
#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow power down of I2C1 during EM23 */
+#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */
#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */
#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */
#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_DAC0DIS (0x1UL << 7) /**< Allow power down of DAC0 during EM23 */
-#define _EMU_EM23PERNORETAINCTRL_DAC0DIS_SHIFT 7 /**< Shift value for EMU_DAC0DIS */
-#define _EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK 0x80UL /**< Bit mask for EMU_DAC0DIS */
-#define _EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow power down of IDAC0 during EM23 */
+#define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */
+#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */
+#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */
+#define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
+#define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
+#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */
#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */
#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */
#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow power down of ADC0 during EM23 */
+#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */
#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */
#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */
#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow power down of LETIMER0 during EM23 */
+#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */
#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */
#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */
#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow power down of WDOG0 during EM23 */
+#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */
#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */
#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */
#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow power down of WDOG1 during EM23 */
+#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */
#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */
#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */
#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow power down of LESENSE0 during EM23 */
+#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */
#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */
#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */
#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow power down of CSEN during EM23 */
+#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */
#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */
#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */
#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow power down of LEUART0 during EM23 */
+#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */
#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */
#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */
#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
+/** @} */
/** @} End of group EFR32FG12P_EMU */
/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_etm.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_etm.h
similarity index 93%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_etm.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_etm.h
index 50ee81fd..1e8b2534 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_etm.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_etm.h
@@ -1,109 +1,116 @@
-/**************************************************************************//**
- * @file efr32fg12p_etm.h
+/***************************************************************************//**
+ * @file
* @brief EFR32FG12P_ETM register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_ETM
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P_ETM ETM
* @{
* @brief EFR32FG12P_ETM Register Declaration
- *****************************************************************************/
-typedef struct
-{
- __IOM uint32_t ETMCR; /**< Main Control Register */
- __IM uint32_t ETMCCR; /**< Configuration Code Register */
- __IOM uint32_t ETMTRIGGER; /**< ETM Trigger Event Register */
- uint32_t RESERVED0[1]; /**< Reserved for future use **/
- __IOM uint32_t ETMSR; /**< ETM Status Register */
- __IM uint32_t ETMSCR; /**< ETM System Configuration Register */
- uint32_t RESERVED1[2]; /**< Reserved for future use **/
- __IOM uint32_t ETMTEEVR; /**< ETM TraceEnable Event Register */
- __IOM uint32_t ETMTECR1; /**< ETM Trace control Register */
- uint32_t RESERVED2[1]; /**< Reserved for future use **/
- __IOM uint32_t ETMFFLR; /**< ETM Fifo Full Level Register */
- uint32_t RESERVED3[68]; /**< Reserved for future use **/
- __IOM uint32_t ETMCNTRLDVR1; /**< Counter Reload Value */
- uint32_t RESERVED4[39]; /**< Reserved for future use **/
- __IOM uint32_t ETMSYNCFR; /**< Synchronisation Frequency Register */
- __IM uint32_t ETMIDR; /**< ID Register */
- __IM uint32_t ETMCCER; /**< Configuration Code Extension Register */
- uint32_t RESERVED5[1]; /**< Reserved for future use **/
- __IOM uint32_t ETMTESSEICR; /**< TraceEnable Start/Stop EmbeddedICE Control Register */
- uint32_t RESERVED6[1]; /**< Reserved for future use **/
- __IOM uint32_t ETMTSEVR; /**< Timestamp Event Register */
- uint32_t RESERVED7[1]; /**< Reserved for future use **/
- __IOM uint32_t ETMTRACEIDR; /**< CoreSight Trace ID Register */
- uint32_t RESERVED8[1]; /**< Reserved for future use **/
- __IM uint32_t ETMIDR2; /**< ETM ID Register 2 */
- uint32_t RESERVED9[66]; /**< Reserved for future use **/
- __IM uint32_t ETMPDSR; /**< Device Power-down Status Register */
- uint32_t RESERVED10[754]; /**< Reserved for future use **/
- __IOM uint32_t ETMISCIN; /**< Integration Test Miscellaneous Inputs Register */
- uint32_t RESERVED11[1]; /**< Reserved for future use **/
- __IOM uint32_t ITTRIGOUT; /**< Integration Test Trigger Out Register */
- uint32_t RESERVED12[1]; /**< Reserved for future use **/
- __IM uint32_t ETMITATBCTR2; /**< ETM Integration Test ATB Control 2 Register */
- uint32_t RESERVED13[1]; /**< Reserved for future use **/
- __IOM uint32_t ETMITATBCTR0; /**< ETM Integration Test ATB Control 0 Register */
- uint32_t RESERVED14[1]; /**< Reserved for future use **/
- __IOM uint32_t ETMITCTRL; /**< ETM Integration Control Register */
- uint32_t RESERVED15[39]; /**< Reserved for future use **/
- __IOM uint32_t ETMCLAIMSET; /**< ETM Claim Tag Set Register */
- __IOM uint32_t ETMCLAIMCLR; /**< ETM Claim Tag Clear Register */
- uint32_t RESERVED16[2]; /**< Reserved for future use **/
- __IOM uint32_t ETMLAR; /**< ETM Lock Access Register */
- __IM uint32_t ETMLSR; /**< Lock Status Register */
- __IM uint32_t ETMAUTHSTATUS; /**< ETM Authentication Status Register */
- uint32_t RESERVED17[4]; /**< Reserved for future use **/
- __IM uint32_t ETMDEVTYPE; /**< CoreSight Device Type Register */
- __IM uint32_t ETMPIDR4; /**< Peripheral ID4 Register */
- __OM uint32_t ETMPIDR5; /**< Peripheral ID5 Register */
- __OM uint32_t ETMPIDR6; /**< Peripheral ID6 Register */
- __OM uint32_t ETMPIDR7; /**< Peripheral ID7 Register */
- __IM uint32_t ETMPIDR0; /**< Peripheral ID0 Register */
- __IM uint32_t ETMPIDR1; /**< Peripheral ID1 Register */
- __IM uint32_t ETMPIDR2; /**< Peripheral ID2 Register */
- __IM uint32_t ETMPIDR3; /**< Peripheral ID3 Register */
- __IM uint32_t ETMCIDR0; /**< Component ID0 Register */
- __IM uint32_t ETMCIDR1; /**< Component ID1 Register */
- __IM uint32_t ETMCIDR2; /**< Component ID2 Register */
- __IM uint32_t ETMCIDR3; /**< Component ID3 Register */
-} ETM_TypeDef; /** @} */
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P_ETM_BitFields
+ ******************************************************************************/
+/** ETM Register Declaration */
+typedef struct {
+ __IOM uint32_t ETMCR; /**< Main Control Register */
+ __IM uint32_t ETMCCR; /**< Configuration Code Register */
+ __IOM uint32_t ETMTRIGGER; /**< ETM Trigger Event Register */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use **/
+ __IOM uint32_t ETMSR; /**< ETM Status Register */
+ __IM uint32_t ETMSCR; /**< ETM System Configuration Register */
+ uint32_t RESERVED1[2U]; /**< Reserved for future use **/
+ __IOM uint32_t ETMTEEVR; /**< ETM TraceEnable Event Register */
+ __IOM uint32_t ETMTECR1; /**< ETM Trace control Register */
+ uint32_t RESERVED2[1U]; /**< Reserved for future use **/
+ __IOM uint32_t ETMFFLR; /**< ETM Fifo Full Level Register */
+ uint32_t RESERVED3[68U]; /**< Reserved for future use **/
+ __IOM uint32_t ETMCNTRLDVR1; /**< Counter Reload Value */
+ uint32_t RESERVED4[39U]; /**< Reserved for future use **/
+ __IOM uint32_t ETMSYNCFR; /**< Synchronisation Frequency Register */
+ __IM uint32_t ETMIDR; /**< ID Register */
+ __IM uint32_t ETMCCER; /**< Configuration Code Extension Register */
+ uint32_t RESERVED5[1U]; /**< Reserved for future use **/
+ __IOM uint32_t ETMTESSEICR; /**< TraceEnable Start/Stop EmbeddedICE Control Register */
+ uint32_t RESERVED6[1U]; /**< Reserved for future use **/
+ __IOM uint32_t ETMTSEVR; /**< Timestamp Event Register */
+ uint32_t RESERVED7[1U]; /**< Reserved for future use **/
+ __IOM uint32_t ETMTRACEIDR; /**< CoreSight Trace ID Register */
+ uint32_t RESERVED8[1U]; /**< Reserved for future use **/
+ __IM uint32_t ETMIDR2; /**< ETM ID Register 2 */
+ uint32_t RESERVED9[66U]; /**< Reserved for future use **/
+ __IM uint32_t ETMPDSR; /**< Device Power-down Status Register */
+ uint32_t RESERVED10[754U]; /**< Reserved for future use **/
+ __IOM uint32_t ETMISCIN; /**< Integration Test Miscellaneous Inputs Register */
+ uint32_t RESERVED11[1U]; /**< Reserved for future use **/
+ __IOM uint32_t ITTRIGOUT; /**< Integration Test Trigger Out Register */
+ uint32_t RESERVED12[1U]; /**< Reserved for future use **/
+ __IM uint32_t ETMITATBCTR2; /**< ETM Integration Test ATB Control 2 Register */
+ uint32_t RESERVED13[1U]; /**< Reserved for future use **/
+ __IOM uint32_t ETMITATBCTR0; /**< ETM Integration Test ATB Control 0 Register */
+ uint32_t RESERVED14[1U]; /**< Reserved for future use **/
+ __IOM uint32_t ETMITCTRL; /**< ETM Integration Control Register */
+ uint32_t RESERVED15[39U]; /**< Reserved for future use **/
+ __IOM uint32_t ETMCLAIMSET; /**< ETM Claim Tag Set Register */
+ __IOM uint32_t ETMCLAIMCLR; /**< ETM Claim Tag Clear Register */
+ uint32_t RESERVED16[2U]; /**< Reserved for future use **/
+ __IOM uint32_t ETMLAR; /**< ETM Lock Access Register */
+ __IM uint32_t ETMLSR; /**< Lock Status Register */
+ __IM uint32_t ETMAUTHSTATUS; /**< ETM Authentication Status Register */
+ uint32_t RESERVED17[4U]; /**< Reserved for future use **/
+ __IM uint32_t ETMDEVTYPE; /**< CoreSight Device Type Register */
+ __IM uint32_t ETMPIDR4; /**< Peripheral ID4 Register */
+ __OM uint32_t ETMPIDR5; /**< Peripheral ID5 Register */
+ __OM uint32_t ETMPIDR6; /**< Peripheral ID6 Register */
+ __OM uint32_t ETMPIDR7; /**< Peripheral ID7 Register */
+ __IM uint32_t ETMPIDR0; /**< Peripheral ID0 Register */
+ __IM uint32_t ETMPIDR1; /**< Peripheral ID1 Register */
+ __IM uint32_t ETMPIDR2; /**< Peripheral ID2 Register */
+ __IM uint32_t ETMPIDR3; /**< Peripheral ID3 Register */
+ __IM uint32_t ETMCIDR0; /**< Component ID0 Register */
+ __IM uint32_t ETMCIDR1; /**< Component ID1 Register */
+ __IM uint32_t ETMCIDR2; /**< Component ID2 Register */
+ __IM uint32_t ETMCIDR3; /**< Component ID3 Register */
+} ETM_TypeDef; /** @} */
+
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_ETM
* @{
- *****************************************************************************/
+ * @defgroup EFR32FG12P_ETM_BitFields ETM Bit Fields
+ * @{
+ ******************************************************************************/
/* Bit fields for ETM ETMCR */
#define _ETM_ETMCR_RESETVALUE 0x00000411UL /**< Default value for ETM_ETMCR */
@@ -776,6 +783,6 @@ typedef struct
#define _ETM_ETMCIDR3_PREAMB_DEFAULT 0x000000B1UL /**< Mode DEFAULT for ETM_ETMCIDR3 */
#define ETM_ETMCIDR3_PREAMB_DEFAULT (_ETM_ETMCIDR3_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR3 */
+/** @} */
/** @} End of group EFR32FG12P_ETM */
/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_fpueh.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_fpueh.h
similarity index 91%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_fpueh.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_fpueh.h
index 396b186c..a00e98dc 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_fpueh.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_fpueh.h
@@ -1,55 +1,62 @@
-/**************************************************************************//**
- * @file efr32fg12p_fpueh.h
+/***************************************************************************//**
+ * @file
* @brief EFR32FG12P_FPUEH register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_FPUEH
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P_FPUEH FPUEH
* @{
* @brief EFR32FG12P_FPUEH Register Declaration
- *****************************************************************************/
-typedef struct
-{
+ ******************************************************************************/
+/** FPUEH Register Declaration */
+typedef struct {
__IM uint32_t IF; /**< Interrupt Flag Register */
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
__IOM uint32_t IEN; /**< Interrupt Enable Register */
} FPUEH_TypeDef; /** @} */
-/**************************************************************************//**
- * @defgroup EFR32FG12P_FPUEH_BitFields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_FPUEH
* @{
- *****************************************************************************/
+ * @defgroup EFR32FG12P_FPUEH_BitFields FPUEH Bit Fields
+ * @{
+ ******************************************************************************/
/* Bit fields for FPUEH IF */
#define _FPUEH_IF_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IF */
@@ -187,6 +194,6 @@ typedef struct
#define _FPUEH_IEN_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
#define FPUEH_IEN_FPIXC_DEFAULT (_FPUEH_IEN_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IEN */
+/** @} */
/** @} End of group EFR32FG12P_FPUEH */
/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_gpcrc.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_gpcrc.h
similarity index 92%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_gpcrc.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_gpcrc.h
index a58d0da9..bc25135d 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_gpcrc.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_gpcrc.h
@@ -1,45 +1,50 @@
-/**************************************************************************//**
- * @file efr32fg12p_gpcrc.h
+/***************************************************************************//**
+ * @file
* @brief EFR32FG12P_GPCRC register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_GPCRC
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P_GPCRC GPCRC
* @{
* @brief EFR32FG12P_GPCRC Register Declaration
- *****************************************************************************/
-typedef struct
-{
+ ******************************************************************************/
+/** GPCRC Register Declaration */
+typedef struct {
__IOM uint32_t CTRL; /**< Control Register */
__IOM uint32_t CMD; /**< Command Register */
__IOM uint32_t INIT; /**< CRC Init Value */
@@ -52,10 +57,12 @@ typedef struct
__IM uint32_t DATABYTEREV; /**< CRC Data Byte Reverse Register */
} GPCRC_TypeDef; /** @} */
-/**************************************************************************//**
- * @defgroup EFR32FG12P_GPCRC_BitFields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_GPCRC
* @{
- *****************************************************************************/
+ * @defgroup EFR32FG12P_GPCRC_BitFields GPCRC Bit Fields
+ * @{
+ ******************************************************************************/
/* Bit fields for GPCRC CTRL */
#define _GPCRC_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CTRL */
@@ -180,6 +187,6 @@ typedef struct
#define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATABYTEREV */
#define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */
+/** @} */
/** @} End of group EFR32FG12P_GPCRC */
/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_gpio.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_gpio.h
similarity index 98%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_gpio.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_gpio.h
index 5c0588f7..65fa87f6 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_gpio.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_gpio.h
@@ -1,80 +1,87 @@
-/**************************************************************************//**
- * @file efr32fg12p_gpio.h
+/***************************************************************************//**
+ * @file
* @brief EFR32FG12P_GPIO register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_GPIO
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P_GPIO GPIO
* @{
* @brief EFR32FG12P_GPIO Register Declaration
- *****************************************************************************/
-typedef struct
-{
- GPIO_P_TypeDef P[12]; /**< Port configuration bits */
+ ******************************************************************************/
+/** GPIO Register Declaration */
+typedef struct {
+ GPIO_P_TypeDef P[12U]; /**< Port configuration bits */
- uint32_t RESERVED0[112]; /**< Reserved for future use **/
- __IOM uint32_t EXTIPSELL; /**< External Interrupt Port Select Low Register */
- __IOM uint32_t EXTIPSELH; /**< External Interrupt Port Select High Register */
- __IOM uint32_t EXTIPINSELL; /**< External Interrupt Pin Select Low Register */
- __IOM uint32_t EXTIPINSELH; /**< External Interrupt Pin Select High Register */
- __IOM uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger Register */
- __IOM uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger Register */
- __IOM uint32_t EXTILEVEL; /**< External Interrupt Level Register */
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- __IOM uint32_t EM4WUEN; /**< EM4 wake up Enable Register */
+ uint32_t RESERVED0[112U]; /**< Reserved for future use **/
+ __IOM uint32_t EXTIPSELL; /**< External Interrupt Port Select Low Register */
+ __IOM uint32_t EXTIPSELH; /**< External Interrupt Port Select High Register */
+ __IOM uint32_t EXTIPINSELL; /**< External Interrupt Pin Select Low Register */
+ __IOM uint32_t EXTIPINSELH; /**< External Interrupt Pin Select High Register */
+ __IOM uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger Register */
+ __IOM uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger Register */
+ __IOM uint32_t EXTILEVEL; /**< External Interrupt Level Register */
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IOM uint32_t EM4WUEN; /**< EM4 Wake Up Enable Register */
- uint32_t RESERVED1[4]; /**< Reserved for future use **/
- __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
- __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
- __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register 1 */
+ uint32_t RESERVED1[4U]; /**< Reserved for future use **/
+ __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
+ __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
+ __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register 1 */
- uint32_t RESERVED2[1]; /**< Reserved for future use **/
- __IOM uint32_t INSENSE; /**< Input Sense Register */
- __IOM uint32_t LOCK; /**< Configuration Lock Register */
-} GPIO_TypeDef; /** @} */
+ uint32_t RESERVED2[1U]; /**< Reserved for future use **/
+ __IOM uint32_t INSENSE; /**< Input Sense Register */
+ __IOM uint32_t LOCK; /**< Configuration Lock Register */
+} GPIO_TypeDef; /** @} */
-/**************************************************************************//**
- * @defgroup EFR32FG12P_GPIO_BitFields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_GPIO
+ * @{
+ * @defgroup EFR32FG12P_GPIO_BitFields GPIO Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for GPIO P_CTRL */
#define _GPIO_P_CTRL_RESETVALUE 0x00500050UL /**< Default value for GPIO_P_CTRL */
#define _GPIO_P_CTRL_MASK 0x10711071UL /**< Mask for GPIO_P_CTRL */
-#define GPIO_P_CTRL_DRIVESTRENGTH (0x1UL << 0) /**< Drive strength for port */
+#define GPIO_P_CTRL_DRIVESTRENGTH (0x1UL << 0) /**< Drive Strength for Port */
#define _GPIO_P_CTRL_DRIVESTRENGTH_SHIFT 0 /**< Shift value for GPIO_DRIVESTRENGTH */
#define _GPIO_P_CTRL_DRIVESTRENGTH_MASK 0x1UL /**< Bit mask for GPIO_DRIVESTRENGTH */
#define _GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */
@@ -87,12 +94,12 @@ typedef struct
#define _GPIO_P_CTRL_SLEWRATE_MASK 0x70UL /**< Bit mask for GPIO_SLEWRATE */
#define _GPIO_P_CTRL_SLEWRATE_DEFAULT 0x00000005UL /**< Mode DEFAULT for GPIO_P_CTRL */
#define GPIO_P_CTRL_SLEWRATE_DEFAULT (_GPIO_P_CTRL_SLEWRATE_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_CTRL */
-#define GPIO_P_CTRL_DINDIS (0x1UL << 12) /**< Data In Disable */
+#define GPIO_P_CTRL_DINDIS (0x1UL << 12) /**< Data in Disable */
#define _GPIO_P_CTRL_DINDIS_SHIFT 12 /**< Shift value for GPIO_DINDIS */
#define _GPIO_P_CTRL_DINDIS_MASK 0x1000UL /**< Bit mask for GPIO_DINDIS */
#define _GPIO_P_CTRL_DINDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */
#define GPIO_P_CTRL_DINDIS_DEFAULT (_GPIO_P_CTRL_DINDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_CTRL */
-#define GPIO_P_CTRL_DRIVESTRENGTHALT (0x1UL << 16) /**< Alternate drive strength for port */
+#define GPIO_P_CTRL_DRIVESTRENGTHALT (0x1UL << 16) /**< Alternate Drive Strength for Port */
#define _GPIO_P_CTRL_DRIVESTRENGTHALT_SHIFT 16 /**< Shift value for GPIO_DRIVESTRENGTHALT */
#define _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK 0x10000UL /**< Bit mask for GPIO_DRIVESTRENGTHALT */
#define _GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */
@@ -105,7 +112,7 @@ typedef struct
#define _GPIO_P_CTRL_SLEWRATEALT_MASK 0x700000UL /**< Bit mask for GPIO_SLEWRATEALT */
#define _GPIO_P_CTRL_SLEWRATEALT_DEFAULT 0x00000005UL /**< Mode DEFAULT for GPIO_P_CTRL */
#define GPIO_P_CTRL_SLEWRATEALT_DEFAULT (_GPIO_P_CTRL_SLEWRATEALT_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_CTRL */
-#define GPIO_P_CTRL_DINDISALT (0x1UL << 28) /**< Alternate Data In Disable */
+#define GPIO_P_CTRL_DINDISALT (0x1UL << 28) /**< Alternate Data in Disable */
#define _GPIO_P_CTRL_DINDISALT_SHIFT 28 /**< Shift value for GPIO_DINDISALT */
#define _GPIO_P_CTRL_DINDISALT_MASK 0x10000000UL /**< Bit mask for GPIO_DINDISALT */
#define _GPIO_P_CTRL_DINDISALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */
@@ -1523,16 +1530,16 @@ typedef struct
#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */
#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */
#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LOCK */
-#define _GPIO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for GPIO_LOCK */
#define _GPIO_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_LOCK */
+#define _GPIO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for GPIO_LOCK */
#define _GPIO_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_LOCK */
#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */
-#define GPIO_LOCK_LOCKKEY_LOCK (_GPIO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_UNLOCKED (_GPIO_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_LOCK */
+#define GPIO_LOCK_LOCKKEY_LOCK (_GPIO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_LOCKED (_GPIO_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_LOCK */
#define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */
+/** @} */
/** @} End of group EFR32FG12P_GPIO */
/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_gpio_p.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_gpio_p.h
new file mode 100644
index 00000000..69d50955
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_gpio_p.h
@@ -0,0 +1,59 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32FG12P_GPIO_P register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @brief GPIO_P GPIO P Register
+ * @ingroup EFR32FG12P_GPIO
+ ******************************************************************************/
+typedef struct {
+ __IOM uint32_t CTRL; /**< Port Control Register */
+ __IOM uint32_t MODEL; /**< Port Pin Mode Low Register */
+ __IOM uint32_t MODEH; /**< Port Pin Mode High Register */
+ __IOM uint32_t DOUT; /**< Port Data Out Register */
+ uint32_t RESERVED0[2U]; /**< Reserved for future use **/
+ __IOM uint32_t DOUTTGL; /**< Port Data Out Toggle Register */
+ __IM uint32_t DIN; /**< Port Data in Register */
+ __IOM uint32_t PINLOCKN; /**< Port Unlocked Pins Register */
+ uint32_t RESERVED1[1U]; /**< Reserved for future use **/
+ __IOM uint32_t OVTDIS; /**< Over Voltage Disable for All Modes */
+ uint32_t RESERVED2[1U]; /**< Reserved future */
+} GPIO_P_TypeDef;
+
+/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_i2c.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_i2c.h
similarity index 98%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_i2c.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_i2c.h
index fab2f8dd..e4bc8017 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_i2c.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_i2c.h
@@ -1,45 +1,50 @@
-/**************************************************************************//**
- * @file efr32fg12p_i2c.h
+/***************************************************************************//**
+ * @file
* @brief EFR32FG12P_I2C register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_I2C
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P_I2C I2C
* @{
* @brief EFR32FG12P_I2C Register Declaration
- *****************************************************************************/
-typedef struct
-{
+ ******************************************************************************/
+/** I2C Register Declaration */
+typedef struct {
__IOM uint32_t CTRL; /**< Control Register */
__IOM uint32_t CMD; /**< Command Register */
__IM uint32_t STATE; /**< State Register */
@@ -61,10 +66,12 @@ typedef struct
__IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
} I2C_TypeDef; /** @} */
-/**************************************************************************//**
- * @defgroup EFR32FG12P_I2C_BitFields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_I2C
* @{
- *****************************************************************************/
+ * @defgroup EFR32FG12P_I2C_BitFields I2C Bit Fields
+ * @{
+ ******************************************************************************/
/* Bit fields for I2C CTRL */
#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */
@@ -84,7 +91,7 @@ typedef struct
#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */
#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */
-#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */
+#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP When Empty */
#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */
#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */
#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
@@ -135,7 +142,7 @@ typedef struct
#define I2C_CTRL_BITO_40PCC (_I2C_CTRL_BITO_40PCC << 12) /**< Shifted mode 40PCC for I2C_CTRL */
#define I2C_CTRL_BITO_80PCC (_I2C_CTRL_BITO_80PCC << 12) /**< Shifted mode 80PCC for I2C_CTRL */
#define I2C_CTRL_BITO_160PCC (_I2C_CTRL_BITO_160PCC << 12) /**< Shifted mode 160PCC for I2C_CTRL */
-#define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */
+#define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */
#define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */
#define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */
#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
@@ -160,12 +167,12 @@ typedef struct
/* Bit fields for I2C CMD */
#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */
#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */
-#define I2C_CMD_START (0x1UL << 0) /**< Send start condition */
+#define I2C_CMD_START (0x1UL << 0) /**< Send Start Condition */
#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */
#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */
#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
#define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */
-#define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */
+#define I2C_CMD_STOP (0x1UL << 1) /**< Send Stop Condition */
#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */
#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */
#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
@@ -180,12 +187,12 @@ typedef struct
#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */
#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
#define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */
-#define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */
+#define I2C_CMD_CONT (0x1UL << 4) /**< Continue Transmission */
#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */
#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */
#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
#define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */
-#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */
+#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort Transmission */
#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */
#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */
#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
@@ -271,12 +278,12 @@ typedef struct
#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */
#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */
-#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */
+#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending Continue */
#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */
#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */
#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */
-#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */
+#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending Abort */
#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */
#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */
#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
@@ -389,12 +396,12 @@ typedef struct
/* Bit fields for I2C IF */
#define _I2C_IF_RESETVALUE 0x00000010UL /**< Default value for I2C_IF */
#define _I2C_IF_MASK 0x0007FFFFUL /**< Mask for I2C_IF */
-#define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */
+#define I2C_IF_START (0x1UL << 0) /**< START Condition Interrupt Flag */
#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */
#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */
#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */
-#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */
+#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START Condition Interrupt Flag */
#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
@@ -412,7 +419,7 @@ typedef struct
#define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */
#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
-#define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define _I2C_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */
#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
@@ -469,7 +476,7 @@ typedef struct
#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */
-#define I2C_IF_SSTOP (0x1UL << 16) /**< Slave STOP condition Interrupt Flag */
+#define I2C_IF_SSTOP (0x1UL << 16) /**< Slave STOP Condition Interrupt Flag */
#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
@@ -916,6 +923,6 @@ typedef struct
#define I2C_ROUTELOC0_SCLLOC_LOC30 (_I2C_ROUTELOC0_SCLLOC_LOC30 << 8) /**< Shifted mode LOC30 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC31 (_I2C_ROUTELOC0_SCLLOC_LOC31 << 8) /**< Shifted mode LOC31 for I2C_ROUTELOC0 */
+/** @} */
/** @} End of group EFR32FG12P_I2C */
/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_idac.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_idac.h
similarity index 94%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_idac.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_idac.h
index 20b68824..6ffc720e 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_idac.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_idac.h
@@ -1,66 +1,73 @@
-/**************************************************************************//**
- * @file efr32fg12p_idac.h
+/***************************************************************************//**
+ * @file
* @brief EFR32FG12P_IDAC register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_IDAC
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P_IDAC IDAC
* @{
* @brief EFR32FG12P_IDAC Register Declaration
- *****************************************************************************/
-typedef struct
-{
+ ******************************************************************************/
+/** IDAC Register Declaration */
+typedef struct {
__IOM uint32_t CTRL; /**< Control Register */
__IOM uint32_t CURPROG; /**< Current Programming Register */
- uint32_t RESERVED0[1]; /**< Reserved for future use **/
+ uint32_t RESERVED0[1U]; /**< Reserved for future use **/
__IOM uint32_t DUTYCONFIG; /**< Duty Cycle Configuration Register */
- uint32_t RESERVED1[2]; /**< Reserved for future use **/
+ uint32_t RESERVED1[2U]; /**< Reserved for future use **/
__IM uint32_t STATUS; /**< Status Register */
- uint32_t RESERVED2[1]; /**< Reserved for future use **/
+ uint32_t RESERVED2[1U]; /**< Reserved for future use **/
__IM uint32_t IF; /**< Interrupt Flag Register */
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
__IOM uint32_t IEN; /**< Interrupt Enable Register */
- uint32_t RESERVED3[1]; /**< Reserved for future use **/
+ uint32_t RESERVED3[1U]; /**< Reserved for future use **/
__IM uint32_t APORTREQ; /**< APORT Request Status Register */
__IM uint32_t APORTCONFLICT; /**< APORT Request Status Register */
} IDAC_TypeDef; /** @} */
-/**************************************************************************//**
- * @defgroup EFR32FG12P_IDAC_BitFields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_IDAC
* @{
- *****************************************************************************/
+ * @defgroup EFR32FG12P_IDAC_BitFields IDAC Bit Fields
+ * @{
+ ******************************************************************************/
/* Bit fields for IDAC CTRL */
#define _IDAC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IDAC_CTRL */
@@ -243,7 +250,7 @@ typedef struct
/* Bit fields for IDAC DUTYCONFIG */
#define _IDAC_DUTYCONFIG_RESETVALUE 0x00000000UL /**< Default value for IDAC_DUTYCONFIG */
#define _IDAC_DUTYCONFIG_MASK 0x00000002UL /**< Mask for IDAC_DUTYCONFIG */
-#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS (0x1UL << 1) /**< Duty Cycle Enable. */
+#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS (0x1UL << 1) /**< Duty Cycle Enable */
#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_SHIFT 1 /**< Shift value for IDAC_EM2DUTYCYCLEDIS */
#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_MASK 0x2UL /**< Bit mask for IDAC_EM2DUTYCYCLEDIS */
#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_DUTYCONFIG */
@@ -322,12 +329,12 @@ typedef struct
/* Bit fields for IDAC APORTREQ */
#define _IDAC_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTREQ */
#define _IDAC_APORTREQ_MASK 0x0000000CUL /**< Mask for IDAC_APORTREQ */
-#define IDAC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the APORT bus connected to APORT1X is requested */
+#define IDAC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 If the APORT Bus Connected to APORT1X is Requested */
#define _IDAC_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for IDAC_APORT1XREQ */
#define _IDAC_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for IDAC_APORT1XREQ */
#define _IDAC_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */
#define IDAC_APORTREQ_APORT1XREQ_DEFAULT (_IDAC_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTREQ */
-#define IDAC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is requested */
+#define IDAC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is Requested */
#define _IDAC_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for IDAC_APORT1YREQ */
#define _IDAC_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for IDAC_APORT1YREQ */
#define _IDAC_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */
@@ -336,17 +343,17 @@ typedef struct
/* Bit fields for IDAC APORTCONFLICT */
#define _IDAC_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTCONFLICT */
#define _IDAC_APORTCONFLICT_MASK 0x0000000CUL /**< Mask for IDAC_APORTCONFLICT */
-#define IDAC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */
+#define IDAC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */
#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for IDAC_APORT1XCONFLICT */
#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for IDAC_APORT1XCONFLICT */
#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */
#define IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */
-#define IDAC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is in conflict with another peripheral */
+#define IDAC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is in Conflict With Another Peripheral */
#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for IDAC_APORT1YCONFLICT */
#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for IDAC_APORT1YCONFLICT */
#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */
#define IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */
+/** @} */
/** @} End of group EFR32FG12P_IDAC */
/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_ldma.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_ldma.h
similarity index 96%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_ldma.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_ldma.h
index 467aeb74..f6b64dfa 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_ldma.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_ldma.h
@@ -1,72 +1,79 @@
-/**************************************************************************//**
- * @file efr32fg12p_ldma.h
+/***************************************************************************//**
+ * @file
* @brief EFR32FG12P_LDMA register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_LDMA
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P_LDMA LDMA
* @{
* @brief EFR32FG12P_LDMA Register Declaration
- *****************************************************************************/
-typedef struct
-{
- __IOM uint32_t CTRL; /**< DMA Control Register */
- __IM uint32_t STATUS; /**< DMA Status Register */
- __IOM uint32_t SYNC; /**< DMA Synchronization Trigger Register (Single-Cycle RMW) */
- uint32_t RESERVED0[5]; /**< Reserved for future use **/
- __IOM uint32_t CHEN; /**< DMA Channel Enable Register (Single-Cycle RMW) */
- __IM uint32_t CHBUSY; /**< DMA Channel Busy Register */
- __IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register (Single-Cycle RMW) */
- __IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */
- __IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request Register */
- __IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */
- __IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */
- __IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */
- __IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */
- uint32_t RESERVED1[7]; /**< Reserved for future use **/
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable register */
+ ******************************************************************************/
+/** LDMA Register Declaration */
+typedef struct {
+ __IOM uint32_t CTRL; /**< DMA Control Register */
+ __IM uint32_t STATUS; /**< DMA Status Register */
+ __IOM uint32_t SYNC; /**< DMA Synchronization Trigger Register (Single-Cycle RMW) */
+ uint32_t RESERVED0[5U]; /**< Reserved for future use **/
+ __IOM uint32_t CHEN; /**< DMA Channel Enable Register (Single-Cycle RMW) */
+ __IM uint32_t CHBUSY; /**< DMA Channel Busy Register */
+ __IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register (Single-Cycle RMW) */
+ __IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */
+ __IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request Register */
+ __IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */
+ __IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */
+ __IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */
+ __IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */
+ uint32_t RESERVED1[7U]; /**< Reserved for future use **/
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
- uint32_t RESERVED2[4]; /**< Reserved registers */
- LDMA_CH_TypeDef CH[8]; /**< DMA Channel Registers */
-} LDMA_TypeDef; /** @} */
+ uint32_t RESERVED2[4U]; /**< Reserved registers */
+ LDMA_CH_TypeDef CH[8U]; /**< DMA Channel Registers */
+} LDMA_TypeDef; /** @} */
-/**************************************************************************//**
- * @defgroup EFR32FG12P_LDMA_BitFields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_LDMA
* @{
- *****************************************************************************/
+ * @defgroup EFR32FG12P_LDMA_BitFields LDMA Bit Fields
+ * @{
+ ******************************************************************************/
/* Bit fields for LDMA CTRL */
#define _LDMA_CTRL_RESETVALUE 0x07000000UL /**< Default value for LDMA_CTRL */
@@ -638,6 +645,6 @@ typedef struct
#define _LDMA_CH_LINK_LINKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */
#define LDMA_CH_LINK_LINKADDR_DEFAULT (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CH_LINK */
+/** @} */
/** @} End of group EFR32FG12P_LDMA */
/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_ldma_ch.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_ldma_ch.h
new file mode 100644
index 00000000..c6547291
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_ldma_ch.h
@@ -0,0 +1,56 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32FG12P_LDMA_CH register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @brief LDMA_CH LDMA CH Register
+ * @ingroup EFR32FG12P_LDMA
+ ******************************************************************************/
+typedef struct {
+ __IOM uint32_t REQSEL; /**< Channel Peripheral Request Select Register */
+ __IOM uint32_t CFG; /**< Channel Configuration Register */
+ __IOM uint32_t LOOP; /**< Channel Loop Counter Register */
+ __IOM uint32_t CTRL; /**< Channel Descriptor Control Word Register */
+ __IOM uint32_t SRC; /**< Channel Descriptor Source Data Address Register */
+ __IOM uint32_t DST; /**< Channel Descriptor Destination Data Address Register */
+ __IOM uint32_t LINK; /**< Channel Descriptor Link Structure Address Register */
+ uint32_t RESERVED0[5U]; /**< Reserved future */
+} LDMA_CH_TypeDef;
+
+/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_lesense.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_lesense.h
similarity index 96%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_lesense.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_lesense.h
index 26c5af91..3a08440d 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_lesense.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_lesense.h
@@ -1,83 +1,90 @@
-/**************************************************************************//**
- * @file efr32fg12p_lesense.h
+/***************************************************************************//**
+ * @file
* @brief EFR32FG12P_LESENSE register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_LESENSE
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P_LESENSE LESENSE
* @{
* @brief EFR32FG12P_LESENSE Register Declaration
- *****************************************************************************/
-typedef struct
-{
- __IOM uint32_t CTRL; /**< Control Register */
- __IOM uint32_t TIMCTRL; /**< Timing Control Register */
- __IOM uint32_t PERCTRL; /**< Peripheral Control Register */
- __IOM uint32_t DECCTRL; /**< Decoder control Register */
- __IOM uint32_t BIASCTRL; /**< Bias Control Register */
- __IOM uint32_t EVALCTRL; /**< LESENSE evaluation control */
- __IOM uint32_t PRSCTRL; /**< PRS control register */
- __IOM uint32_t CMD; /**< Command Register */
- __IOM uint32_t CHEN; /**< Channel enable Register */
- __IOM uint32_t SCANRES; /**< Scan result register */
- __IM uint32_t STATUS; /**< Status Register */
- __IM uint32_t PTR; /**< Result buffer pointers */
- __IM uint32_t BUFDATA; /**< Result buffer data register */
- __IM uint32_t CURCH; /**< Current channel index */
- __IOM uint32_t DECSTATE; /**< Current decoder state */
- __IOM uint32_t SENSORSTATE; /**< Decoder input register */
- __IOM uint32_t IDLECONF; /**< GPIO Idle phase configuration */
- __IOM uint32_t ALTEXCONF; /**< Alternative excite pin configuration */
- uint32_t RESERVED0[2]; /**< Reserved for future use **/
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
- __IOM uint32_t ROUTEPEN; /**< I/O Routing Register */
+ ******************************************************************************/
+/** LESENSE Register Declaration */
+typedef struct {
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t TIMCTRL; /**< Timing Control Register */
+ __IOM uint32_t PERCTRL; /**< Peripheral Control Register */
+ __IOM uint32_t DECCTRL; /**< Decoder Control Register */
+ __IOM uint32_t BIASCTRL; /**< Bias Control Register */
+ __IOM uint32_t EVALCTRL; /**< LESENSE Evaluation Control */
+ __IOM uint32_t PRSCTRL; /**< PRS Control Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IOM uint32_t CHEN; /**< Channel Enable Register */
+ __IOM uint32_t SCANRES; /**< Scan Result Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IM uint32_t PTR; /**< Result Buffer Pointers */
+ __IM uint32_t BUFDATA; /**< Result Buffer Data Register */
+ __IM uint32_t CURCH; /**< Current Channel Index */
+ __IOM uint32_t DECSTATE; /**< Current Decoder State */
+ __IOM uint32_t SENSORSTATE; /**< Decoder Input Register */
+ __IOM uint32_t IDLECONF; /**< GPIO Idle Phase Configuration */
+ __IOM uint32_t ALTEXCONF; /**< Alternative Excite Pin Configuration */
+ uint32_t RESERVED0[2U]; /**< Reserved for future use **/
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
+ __IOM uint32_t ROUTEPEN; /**< I/O Routing Register */
- uint32_t RESERVED1[38]; /**< Reserved registers */
- LESENSE_ST_TypeDef ST[32]; /**< Decoding states */
+ uint32_t RESERVED1[38U]; /**< Reserved registers */
+ LESENSE_ST_TypeDef ST[32U]; /**< Decoding states */
- LESENSE_BUF_TypeDef BUF[16]; /**< Scanresult */
+ LESENSE_BUF_TypeDef BUF[16U]; /**< Scanresult */
- LESENSE_CH_TypeDef CH[16]; /**< Scanconfig */
-} LESENSE_TypeDef; /** @} */
+ LESENSE_CH_TypeDef CH[16U]; /**< Scanconfig */
+} LESENSE_TypeDef; /** @} */
-/**************************************************************************//**
- * @defgroup EFR32FG12P_LESENSE_BitFields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_LESENSE
+ * @{
+ * @defgroup EFR32FG12P_LESENSE_BitFields LESENSE Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for LESENSE CTRL */
#define _LESENSE_CTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CTRL */
@@ -132,7 +139,7 @@ typedef struct
#define LESENSE_CTRL_SCANCONF_INVMAP (_LESENSE_CTRL_SCANCONF_INVMAP << 7) /**< Shifted mode INVMAP for LESENSE_CTRL */
#define LESENSE_CTRL_SCANCONF_TOGGLE (_LESENSE_CTRL_SCANCONF_TOGGLE << 7) /**< Shifted mode TOGGLE for LESENSE_CTRL */
#define LESENSE_CTRL_SCANCONF_DECDEF (_LESENSE_CTRL_SCANCONF_DECDEF << 7) /**< Shifted mode DECDEF for LESENSE_CTRL */
-#define LESENSE_CTRL_ALTEXMAP (0x1UL << 11) /**< Alternative excitation map */
+#define LESENSE_CTRL_ALTEXMAP (0x1UL << 11) /**< Alternative Excitation Map */
#define _LESENSE_CTRL_ALTEXMAP_SHIFT 11 /**< Shift value for LESENSE_ALTEXMAP */
#define _LESENSE_CTRL_ALTEXMAP_MASK 0x800UL /**< Bit mask for LESENSE_ALTEXMAP */
#define _LESENSE_CTRL_ALTEXMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */
@@ -141,22 +148,22 @@ typedef struct
#define LESENSE_CTRL_ALTEXMAP_DEFAULT (_LESENSE_CTRL_ALTEXMAP_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_CTRL */
#define LESENSE_CTRL_ALTEXMAP_ALTEX (_LESENSE_CTRL_ALTEXMAP_ALTEX << 11) /**< Shifted mode ALTEX for LESENSE_CTRL */
#define LESENSE_CTRL_ALTEXMAP_CH (_LESENSE_CTRL_ALTEXMAP_CH << 11) /**< Shifted mode CH for LESENSE_CTRL */
-#define LESENSE_CTRL_DUALSAMPLE (0x1UL << 13) /**< Enable dual sample mode */
+#define LESENSE_CTRL_DUALSAMPLE (0x1UL << 13) /**< Enable Dual Sample Mode */
#define _LESENSE_CTRL_DUALSAMPLE_SHIFT 13 /**< Shift value for LESENSE_DUALSAMPLE */
#define _LESENSE_CTRL_DUALSAMPLE_MASK 0x2000UL /**< Bit mask for LESENSE_DUALSAMPLE */
#define _LESENSE_CTRL_DUALSAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */
#define LESENSE_CTRL_DUALSAMPLE_DEFAULT (_LESENSE_CTRL_DUALSAMPLE_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_CTRL */
-#define LESENSE_CTRL_BUFOW (0x1UL << 16) /**< Result buffer overwrite */
+#define LESENSE_CTRL_BUFOW (0x1UL << 16) /**< Result Buffer Overwrite */
#define _LESENSE_CTRL_BUFOW_SHIFT 16 /**< Shift value for LESENSE_BUFOW */
#define _LESENSE_CTRL_BUFOW_MASK 0x10000UL /**< Bit mask for LESENSE_BUFOW */
#define _LESENSE_CTRL_BUFOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */
#define LESENSE_CTRL_BUFOW_DEFAULT (_LESENSE_CTRL_BUFOW_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_CTRL */
-#define LESENSE_CTRL_STRSCANRES (0x1UL << 17) /**< Enable storing of SCANRES */
+#define LESENSE_CTRL_STRSCANRES (0x1UL << 17) /**< Enable Storing of SCANRES */
#define _LESENSE_CTRL_STRSCANRES_SHIFT 17 /**< Shift value for LESENSE_STRSCANRES */
#define _LESENSE_CTRL_STRSCANRES_MASK 0x20000UL /**< Bit mask for LESENSE_STRSCANRES */
#define _LESENSE_CTRL_STRSCANRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */
#define LESENSE_CTRL_STRSCANRES_DEFAULT (_LESENSE_CTRL_STRSCANRES_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_CTRL */
-#define LESENSE_CTRL_BUFIDL (0x1UL << 19) /**< Result buffer interrupt and DMA trigger level */
+#define LESENSE_CTRL_BUFIDL (0x1UL << 19) /**< Result Buffer Interrupt and DMA Trigger Level */
#define _LESENSE_CTRL_BUFIDL_SHIFT 19 /**< Shift value for LESENSE_BUFIDL */
#define _LESENSE_CTRL_BUFIDL_MASK 0x80000UL /**< Bit mask for LESENSE_BUFIDL */
#define _LESENSE_CTRL_BUFIDL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */
@@ -244,7 +251,7 @@ typedef struct
#define _LESENSE_TIMCTRL_STARTDLY_MASK 0xC00000UL /**< Bit mask for LESENSE_STARTDLY */
#define _LESENSE_TIMCTRL_STARTDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */
#define LESENSE_TIMCTRL_STARTDLY_DEFAULT (_LESENSE_TIMCTRL_STARTDLY_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */
-#define LESENSE_TIMCTRL_AUXSTARTUP (0x1UL << 28) /**< AUXHFRCO startup configuration */
+#define LESENSE_TIMCTRL_AUXSTARTUP (0x1UL << 28) /**< AUXHFRCO Startup Configuration */
#define _LESENSE_TIMCTRL_AUXSTARTUP_SHIFT 28 /**< Shift value for LESENSE_AUXSTARTUP */
#define _LESENSE_TIMCTRL_AUXSTARTUP_MASK 0x10000000UL /**< Bit mask for LESENSE_AUXSTARTUP */
#define _LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */
@@ -257,17 +264,17 @@ typedef struct
/* Bit fields for LESENSE PERCTRL */
#define _LESENSE_PERCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PERCTRL */
#define _LESENSE_PERCTRL_MASK 0x3FF0014FUL /**< Mask for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_DACCH0EN (0x1UL << 0) /**< VDAC CH0 enable. */
+#define LESENSE_PERCTRL_DACCH0EN (0x1UL << 0) /**< VDAC CH0 Enable */
#define _LESENSE_PERCTRL_DACCH0EN_SHIFT 0 /**< Shift value for LESENSE_DACCH0EN */
#define _LESENSE_PERCTRL_DACCH0EN_MASK 0x1UL /**< Bit mask for LESENSE_DACCH0EN */
#define _LESENSE_PERCTRL_DACCH0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */
#define LESENSE_PERCTRL_DACCH0EN_DEFAULT (_LESENSE_PERCTRL_DACCH0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_DACCH1EN (0x1UL << 1) /**< VDAC CH1 enable. */
+#define LESENSE_PERCTRL_DACCH1EN (0x1UL << 1) /**< VDAC CH1 Enable */
#define _LESENSE_PERCTRL_DACCH1EN_SHIFT 1 /**< Shift value for LESENSE_DACCH1EN */
#define _LESENSE_PERCTRL_DACCH1EN_MASK 0x2UL /**< Bit mask for LESENSE_DACCH1EN */
#define _LESENSE_PERCTRL_DACCH1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */
#define LESENSE_PERCTRL_DACCH1EN_DEFAULT (_LESENSE_PERCTRL_DACCH1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_DACCH0DATA (0x1UL << 2) /**< VDAC CH0 data selection. */
+#define LESENSE_PERCTRL_DACCH0DATA (0x1UL << 2) /**< VDAC CH0 Data Selection */
#define _LESENSE_PERCTRL_DACCH0DATA_SHIFT 2 /**< Shift value for LESENSE_DACCH0DATA */
#define _LESENSE_PERCTRL_DACCH0DATA_MASK 0x4UL /**< Bit mask for LESENSE_DACCH0DATA */
#define _LESENSE_PERCTRL_DACCH0DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */
@@ -276,7 +283,7 @@ typedef struct
#define LESENSE_PERCTRL_DACCH0DATA_DEFAULT (_LESENSE_PERCTRL_DACCH0DATA_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */
#define LESENSE_PERCTRL_DACCH0DATA_DACDATA (_LESENSE_PERCTRL_DACCH0DATA_DACDATA << 2) /**< Shifted mode DACDATA for LESENSE_PERCTRL */
#define LESENSE_PERCTRL_DACCH0DATA_THRES (_LESENSE_PERCTRL_DACCH0DATA_THRES << 2) /**< Shifted mode THRES for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_DACCH1DATA (0x1UL << 3) /**< VDAC CH1 data selection. */
+#define LESENSE_PERCTRL_DACCH1DATA (0x1UL << 3) /**< VDAC CH1 Data Selection */
#define _LESENSE_PERCTRL_DACCH1DATA_SHIFT 3 /**< Shift value for LESENSE_DACCH1DATA */
#define _LESENSE_PERCTRL_DACCH1DATA_MASK 0x8UL /**< Bit mask for LESENSE_DACCH1DATA */
#define _LESENSE_PERCTRL_DACCH1DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */
@@ -285,7 +292,7 @@ typedef struct
#define LESENSE_PERCTRL_DACCH1DATA_DEFAULT (_LESENSE_PERCTRL_DACCH1DATA_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */
#define LESENSE_PERCTRL_DACCH1DATA_DACDATA (_LESENSE_PERCTRL_DACCH1DATA_DACDATA << 3) /**< Shifted mode DACDATA for LESENSE_PERCTRL */
#define LESENSE_PERCTRL_DACCH1DATA_THRES (_LESENSE_PERCTRL_DACCH1DATA_THRES << 3) /**< Shifted mode THRES for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_DACSTARTUP (0x1UL << 6) /**< VDAC startup configuration */
+#define LESENSE_PERCTRL_DACSTARTUP (0x1UL << 6) /**< VDAC Startup Configuration */
#define _LESENSE_PERCTRL_DACSTARTUP_SHIFT 6 /**< Shift value for LESENSE_DACSTARTUP */
#define _LESENSE_PERCTRL_DACSTARTUP_MASK 0x40UL /**< Bit mask for LESENSE_DACSTARTUP */
#define _LESENSE_PERCTRL_DACSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */
@@ -294,7 +301,7 @@ typedef struct
#define LESENSE_PERCTRL_DACSTARTUP_DEFAULT (_LESENSE_PERCTRL_DACSTARTUP_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */
#define LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE (_LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE << 6) /**< Shifted mode FULLCYCLE for LESENSE_PERCTRL */
#define LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE (_LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE << 6) /**< Shifted mode HALFCYCLE for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_DACCONVTRIG (0x1UL << 8) /**< VDAC conversion trigger configuration */
+#define LESENSE_PERCTRL_DACCONVTRIG (0x1UL << 8) /**< VDAC Conversion Trigger Configuration */
#define _LESENSE_PERCTRL_DACCONVTRIG_SHIFT 8 /**< Shift value for LESENSE_DACCONVTRIG */
#define _LESENSE_PERCTRL_DACCONVTRIG_MASK 0x100UL /**< Bit mask for LESENSE_DACCONVTRIG */
#define _LESENSE_PERCTRL_DACCONVTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */
@@ -323,22 +330,22 @@ typedef struct
#define LESENSE_PERCTRL_ACMP1MODE_DISABLE (_LESENSE_PERCTRL_ACMP1MODE_DISABLE << 22) /**< Shifted mode DISABLE for LESENSE_PERCTRL */
#define LESENSE_PERCTRL_ACMP1MODE_MUX (_LESENSE_PERCTRL_ACMP1MODE_MUX << 22) /**< Shifted mode MUX for LESENSE_PERCTRL */
#define LESENSE_PERCTRL_ACMP1MODE_MUXTHRES (_LESENSE_PERCTRL_ACMP1MODE_MUXTHRES << 22) /**< Shifted mode MUXTHRES for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_ACMP0INV (0x1UL << 24) /**< Invert analog comparator 0 output */
+#define LESENSE_PERCTRL_ACMP0INV (0x1UL << 24) /**< Invert Analog Comparator 0 Output */
#define _LESENSE_PERCTRL_ACMP0INV_SHIFT 24 /**< Shift value for LESENSE_ACMP0INV */
#define _LESENSE_PERCTRL_ACMP0INV_MASK 0x1000000UL /**< Bit mask for LESENSE_ACMP0INV */
#define _LESENSE_PERCTRL_ACMP0INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */
#define LESENSE_PERCTRL_ACMP0INV_DEFAULT (_LESENSE_PERCTRL_ACMP0INV_DEFAULT << 24) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_ACMP1INV (0x1UL << 25) /**< Invert analog comparator 1 output */
+#define LESENSE_PERCTRL_ACMP1INV (0x1UL << 25) /**< Invert Analog Comparator 1 Output */
#define _LESENSE_PERCTRL_ACMP1INV_SHIFT 25 /**< Shift value for LESENSE_ACMP1INV */
#define _LESENSE_PERCTRL_ACMP1INV_MASK 0x2000000UL /**< Bit mask for LESENSE_ACMP1INV */
#define _LESENSE_PERCTRL_ACMP1INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */
#define LESENSE_PERCTRL_ACMP1INV_DEFAULT (_LESENSE_PERCTRL_ACMP1INV_DEFAULT << 25) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_ACMP0HYSTEN (0x1UL << 26) /**< ACMP0 hysteresis enable */
+#define LESENSE_PERCTRL_ACMP0HYSTEN (0x1UL << 26) /**< ACMP0 Hysteresis Enable */
#define _LESENSE_PERCTRL_ACMP0HYSTEN_SHIFT 26 /**< Shift value for LESENSE_ACMP0HYSTEN */
#define _LESENSE_PERCTRL_ACMP0HYSTEN_MASK 0x4000000UL /**< Bit mask for LESENSE_ACMP0HYSTEN */
#define _LESENSE_PERCTRL_ACMP0HYSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */
#define LESENSE_PERCTRL_ACMP0HYSTEN_DEFAULT (_LESENSE_PERCTRL_ACMP0HYSTEN_DEFAULT << 26) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_ACMP1HYSTEN (0x1UL << 27) /**< ACMP1 hysteresis enable */
+#define LESENSE_PERCTRL_ACMP1HYSTEN (0x1UL << 27) /**< ACMP1 Hysteresis Enable */
#define _LESENSE_PERCTRL_ACMP1HYSTEN_SHIFT 27 /**< Shift value for LESENSE_ACMP1HYSTEN */
#define _LESENSE_PERCTRL_ACMP1HYSTEN_MASK 0x8000000UL /**< Bit mask for LESENSE_ACMP1HYSTEN */
#define _LESENSE_PERCTRL_ACMP1HYSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */
@@ -359,47 +366,47 @@ typedef struct
/* Bit fields for LESENSE DECCTRL */
#define _LESENSE_DECCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_DECCTRL */
#define _LESENSE_DECCTRL_MASK 0x1EF7BDFFUL /**< Mask for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_DISABLE (0x1UL << 0) /**< Disable the decoder */
+#define LESENSE_DECCTRL_DISABLE (0x1UL << 0) /**< Disable the Decoder */
#define _LESENSE_DECCTRL_DISABLE_SHIFT 0 /**< Shift value for LESENSE_DISABLE */
#define _LESENSE_DECCTRL_DISABLE_MASK 0x1UL /**< Bit mask for LESENSE_DISABLE */
#define _LESENSE_DECCTRL_DISABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */
#define LESENSE_DECCTRL_DISABLE_DEFAULT (_LESENSE_DECCTRL_DISABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_ERRCHK (0x1UL << 1) /**< Enable check of current state */
+#define LESENSE_DECCTRL_ERRCHK (0x1UL << 1) /**< Enable Check of Current State */
#define _LESENSE_DECCTRL_ERRCHK_SHIFT 1 /**< Shift value for LESENSE_ERRCHK */
#define _LESENSE_DECCTRL_ERRCHK_MASK 0x2UL /**< Bit mask for LESENSE_ERRCHK */
#define _LESENSE_DECCTRL_ERRCHK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */
#define LESENSE_DECCTRL_ERRCHK_DEFAULT (_LESENSE_DECCTRL_ERRCHK_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_INTMAP (0x1UL << 2) /**< Enable decoder to channel interrupt mapping */
+#define LESENSE_DECCTRL_INTMAP (0x1UL << 2) /**< Enable Decoder to Channel Interrupt Mapping */
#define _LESENSE_DECCTRL_INTMAP_SHIFT 2 /**< Shift value for LESENSE_INTMAP */
#define _LESENSE_DECCTRL_INTMAP_MASK 0x4UL /**< Bit mask for LESENSE_INTMAP */
#define _LESENSE_DECCTRL_INTMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */
#define LESENSE_DECCTRL_INTMAP_DEFAULT (_LESENSE_DECCTRL_INTMAP_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_HYSTPRS0 (0x1UL << 3) /**< Enable decoder hysteresis on PRS0 output */
+#define LESENSE_DECCTRL_HYSTPRS0 (0x1UL << 3) /**< Enable Decoder Hysteresis on PRS0 Output */
#define _LESENSE_DECCTRL_HYSTPRS0_SHIFT 3 /**< Shift value for LESENSE_HYSTPRS0 */
#define _LESENSE_DECCTRL_HYSTPRS0_MASK 0x8UL /**< Bit mask for LESENSE_HYSTPRS0 */
#define _LESENSE_DECCTRL_HYSTPRS0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */
#define LESENSE_DECCTRL_HYSTPRS0_DEFAULT (_LESENSE_DECCTRL_HYSTPRS0_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_HYSTPRS1 (0x1UL << 4) /**< Enable decoder hysteresis on PRS1 output */
+#define LESENSE_DECCTRL_HYSTPRS1 (0x1UL << 4) /**< Enable Decoder Hysteresis on PRS1 Output */
#define _LESENSE_DECCTRL_HYSTPRS1_SHIFT 4 /**< Shift value for LESENSE_HYSTPRS1 */
#define _LESENSE_DECCTRL_HYSTPRS1_MASK 0x10UL /**< Bit mask for LESENSE_HYSTPRS1 */
#define _LESENSE_DECCTRL_HYSTPRS1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */
#define LESENSE_DECCTRL_HYSTPRS1_DEFAULT (_LESENSE_DECCTRL_HYSTPRS1_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_HYSTPRS2 (0x1UL << 5) /**< Enable decoder hysteresis on PRS2 output */
+#define LESENSE_DECCTRL_HYSTPRS2 (0x1UL << 5) /**< Enable Decoder Hysteresis on PRS2 Output */
#define _LESENSE_DECCTRL_HYSTPRS2_SHIFT 5 /**< Shift value for LESENSE_HYSTPRS2 */
#define _LESENSE_DECCTRL_HYSTPRS2_MASK 0x20UL /**< Bit mask for LESENSE_HYSTPRS2 */
#define _LESENSE_DECCTRL_HYSTPRS2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */
#define LESENSE_DECCTRL_HYSTPRS2_DEFAULT (_LESENSE_DECCTRL_HYSTPRS2_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_HYSTIRQ (0x1UL << 6) /**< Enable decoder hysteresis on interrupt requests */
+#define LESENSE_DECCTRL_HYSTIRQ (0x1UL << 6) /**< Enable Decoder Hysteresis on Interrupt Requests */
#define _LESENSE_DECCTRL_HYSTIRQ_SHIFT 6 /**< Shift value for LESENSE_HYSTIRQ */
#define _LESENSE_DECCTRL_HYSTIRQ_MASK 0x40UL /**< Bit mask for LESENSE_HYSTIRQ */
#define _LESENSE_DECCTRL_HYSTIRQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */
#define LESENSE_DECCTRL_HYSTIRQ_DEFAULT (_LESENSE_DECCTRL_HYSTIRQ_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSCNT (0x1UL << 7) /**< Enable count mode on decoder PRS channels 0 and 1 */
+#define LESENSE_DECCTRL_PRSCNT (0x1UL << 7) /**< Enable Count Mode on Decoder PRS Channels 0 and 1 */
#define _LESENSE_DECCTRL_PRSCNT_SHIFT 7 /**< Shift value for LESENSE_PRSCNT */
#define _LESENSE_DECCTRL_PRSCNT_MASK 0x80UL /**< Bit mask for LESENSE_PRSCNT */
#define _LESENSE_DECCTRL_PRSCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */
#define LESENSE_DECCTRL_PRSCNT_DEFAULT (_LESENSE_DECCTRL_PRSCNT_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_INPUT (0x1UL << 8) /**< LESENSE decoder input configuration */
+#define LESENSE_DECCTRL_INPUT (0x1UL << 8) /**< LESENSE Decoder Input Configuration */
#define _LESENSE_DECCTRL_INPUT_SHIFT 8 /**< Shift value for LESENSE_INPUT */
#define _LESENSE_DECCTRL_INPUT_MASK 0x100UL /**< Bit mask for LESENSE_INPUT */
#define _LESENSE_DECCTRL_INPUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */
@@ -554,7 +561,7 @@ typedef struct
#define _LESENSE_PRSCTRL_DECCMPMASK_MASK 0x1F00UL /**< Bit mask for LESENSE_DECCMPMASK */
#define _LESENSE_PRSCTRL_DECCMPMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */
#define LESENSE_PRSCTRL_DECCMPMASK_DEFAULT (_LESENSE_PRSCTRL_DECCMPMASK_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */
-#define LESENSE_PRSCTRL_DECCMPEN (0x1UL << 16) /**< Enable PRS output DECCMP */
+#define LESENSE_PRSCTRL_DECCMPEN (0x1UL << 16) /**< Enable PRS Output DECCMP */
#define _LESENSE_PRSCTRL_DECCMPEN_SHIFT 16 /**< Shift value for LESENSE_DECCMPEN */
#define _LESENSE_PRSCTRL_DECCMPEN_MASK 0x10000UL /**< Bit mask for LESENSE_DECCMPEN */
#define _LESENSE_PRSCTRL_DECCMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */
@@ -563,22 +570,22 @@ typedef struct
/* Bit fields for LESENSE CMD */
#define _LESENSE_CMD_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CMD */
#define _LESENSE_CMD_MASK 0x0000000FUL /**< Mask for LESENSE_CMD */
-#define LESENSE_CMD_START (0x1UL << 0) /**< Start scanning of sensors. */
+#define LESENSE_CMD_START (0x1UL << 0) /**< Start Scanning of Sensors */
#define _LESENSE_CMD_START_SHIFT 0 /**< Shift value for LESENSE_START */
#define _LESENSE_CMD_START_MASK 0x1UL /**< Bit mask for LESENSE_START */
#define _LESENSE_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */
#define LESENSE_CMD_START_DEFAULT (_LESENSE_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CMD */
-#define LESENSE_CMD_STOP (0x1UL << 1) /**< Stop scanning of sensors */
+#define LESENSE_CMD_STOP (0x1UL << 1) /**< Stop Scanning of Sensors */
#define _LESENSE_CMD_STOP_SHIFT 1 /**< Shift value for LESENSE_STOP */
#define _LESENSE_CMD_STOP_MASK 0x2UL /**< Bit mask for LESENSE_STOP */
#define _LESENSE_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */
#define LESENSE_CMD_STOP_DEFAULT (_LESENSE_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_CMD */
-#define LESENSE_CMD_DECODE (0x1UL << 2) /**< Start decoder */
+#define LESENSE_CMD_DECODE (0x1UL << 2) /**< Start Decoder */
#define _LESENSE_CMD_DECODE_SHIFT 2 /**< Shift value for LESENSE_DECODE */
#define _LESENSE_CMD_DECODE_MASK 0x4UL /**< Bit mask for LESENSE_DECODE */
#define _LESENSE_CMD_DECODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */
#define LESENSE_CMD_DECODE_DEFAULT (_LESENSE_CMD_DECODE_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_CMD */
-#define LESENSE_CMD_CLEARBUF (0x1UL << 3) /**< Clear result buffer */
+#define LESENSE_CMD_CLEARBUF (0x1UL << 3) /**< Clear Result Buffer */
#define _LESENSE_CMD_CLEARBUF_SHIFT 3 /**< Shift value for LESENSE_CLEARBUF */
#define _LESENSE_CMD_CLEARBUF_MASK 0x8UL /**< Bit mask for LESENSE_CLEARBUF */
#define _LESENSE_CMD_CLEARBUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */
@@ -607,32 +614,32 @@ typedef struct
/* Bit fields for LESENSE STATUS */
#define _LESENSE_STATUS_RESETVALUE 0x00000000UL /**< Default value for LESENSE_STATUS */
#define _LESENSE_STATUS_MASK 0x0000003FUL /**< Mask for LESENSE_STATUS */
-#define LESENSE_STATUS_BUFDATAV (0x1UL << 0) /**< Result data valid */
+#define LESENSE_STATUS_BUFDATAV (0x1UL << 0) /**< Result Data Valid */
#define _LESENSE_STATUS_BUFDATAV_SHIFT 0 /**< Shift value for LESENSE_BUFDATAV */
#define _LESENSE_STATUS_BUFDATAV_MASK 0x1UL /**< Bit mask for LESENSE_BUFDATAV */
#define _LESENSE_STATUS_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */
#define LESENSE_STATUS_BUFDATAV_DEFAULT (_LESENSE_STATUS_BUFDATAV_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_STATUS */
-#define LESENSE_STATUS_BUFHALFFULL (0x1UL << 1) /**< Result buffer half full */
+#define LESENSE_STATUS_BUFHALFFULL (0x1UL << 1) /**< Result Buffer Half Full */
#define _LESENSE_STATUS_BUFHALFFULL_SHIFT 1 /**< Shift value for LESENSE_BUFHALFFULL */
#define _LESENSE_STATUS_BUFHALFFULL_MASK 0x2UL /**< Bit mask for LESENSE_BUFHALFFULL */
#define _LESENSE_STATUS_BUFHALFFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */
#define LESENSE_STATUS_BUFHALFFULL_DEFAULT (_LESENSE_STATUS_BUFHALFFULL_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_STATUS */
-#define LESENSE_STATUS_BUFFULL (0x1UL << 2) /**< Result buffer full */
+#define LESENSE_STATUS_BUFFULL (0x1UL << 2) /**< Result Buffer Full */
#define _LESENSE_STATUS_BUFFULL_SHIFT 2 /**< Shift value for LESENSE_BUFFULL */
#define _LESENSE_STATUS_BUFFULL_MASK 0x4UL /**< Bit mask for LESENSE_BUFFULL */
#define _LESENSE_STATUS_BUFFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */
#define LESENSE_STATUS_BUFFULL_DEFAULT (_LESENSE_STATUS_BUFFULL_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_STATUS */
-#define LESENSE_STATUS_RUNNING (0x1UL << 3) /**< LESENSE periodic counter running */
+#define LESENSE_STATUS_RUNNING (0x1UL << 3) /**< LESENSE Periodic Counter Running */
#define _LESENSE_STATUS_RUNNING_SHIFT 3 /**< Shift value for LESENSE_RUNNING */
#define _LESENSE_STATUS_RUNNING_MASK 0x8UL /**< Bit mask for LESENSE_RUNNING */
#define _LESENSE_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */
#define LESENSE_STATUS_RUNNING_DEFAULT (_LESENSE_STATUS_RUNNING_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_STATUS */
-#define LESENSE_STATUS_SCANACTIVE (0x1UL << 4) /**< LESENSE scan active */
+#define LESENSE_STATUS_SCANACTIVE (0x1UL << 4) /**< LESENSE Scan Active */
#define _LESENSE_STATUS_SCANACTIVE_SHIFT 4 /**< Shift value for LESENSE_SCANACTIVE */
#define _LESENSE_STATUS_SCANACTIVE_MASK 0x10UL /**< Bit mask for LESENSE_SCANACTIVE */
#define _LESENSE_STATUS_SCANACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */
#define LESENSE_STATUS_SCANACTIVE_DEFAULT (_LESENSE_STATUS_SCANACTIVE_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_STATUS */
-#define LESENSE_STATUS_DACACTIVE (0x1UL << 5) /**< LESENSE VDAC interface is active */
+#define LESENSE_STATUS_DACACTIVE (0x1UL << 5) /**< LESENSE VDAC Interface is Active */
#define _LESENSE_STATUS_DACACTIVE_SHIFT 5 /**< Shift value for LESENSE_DACACTIVE */
#define _LESENSE_STATUS_DACACTIVE_MASK 0x20UL /**< Bit mask for LESENSE_DACACTIVE */
#define _LESENSE_STATUS_DACACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */
@@ -965,42 +972,42 @@ typedef struct
#define LESENSE_ALTEXCONF_IDLECONF7_DISABLE (_LESENSE_ALTEXCONF_IDLECONF7_DISABLE << 14) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */
#define LESENSE_ALTEXCONF_IDLECONF7_HIGH (_LESENSE_ALTEXCONF_IDLECONF7_HIGH << 14) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */
#define LESENSE_ALTEXCONF_IDLECONF7_LOW (_LESENSE_ALTEXCONF_IDLECONF7_LOW << 14) /**< Shifted mode LOW for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_AEX0 (0x1UL << 16) /**< ALTEX0 always excite enable */
+#define LESENSE_ALTEXCONF_AEX0 (0x1UL << 16) /**< ALTEX0 Always Excite Enable */
#define _LESENSE_ALTEXCONF_AEX0_SHIFT 16 /**< Shift value for LESENSE_AEX0 */
#define _LESENSE_ALTEXCONF_AEX0_MASK 0x10000UL /**< Bit mask for LESENSE_AEX0 */
#define _LESENSE_ALTEXCONF_AEX0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */
#define LESENSE_ALTEXCONF_AEX0_DEFAULT (_LESENSE_ALTEXCONF_AEX0_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_AEX1 (0x1UL << 17) /**< ALTEX1 always excite enable */
+#define LESENSE_ALTEXCONF_AEX1 (0x1UL << 17) /**< ALTEX1 Always Excite Enable */
#define _LESENSE_ALTEXCONF_AEX1_SHIFT 17 /**< Shift value for LESENSE_AEX1 */
#define _LESENSE_ALTEXCONF_AEX1_MASK 0x20000UL /**< Bit mask for LESENSE_AEX1 */
#define _LESENSE_ALTEXCONF_AEX1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */
#define LESENSE_ALTEXCONF_AEX1_DEFAULT (_LESENSE_ALTEXCONF_AEX1_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_AEX2 (0x1UL << 18) /**< ALTEX2 always excite enable */
+#define LESENSE_ALTEXCONF_AEX2 (0x1UL << 18) /**< ALTEX2 Always Excite Enable */
#define _LESENSE_ALTEXCONF_AEX2_SHIFT 18 /**< Shift value for LESENSE_AEX2 */
#define _LESENSE_ALTEXCONF_AEX2_MASK 0x40000UL /**< Bit mask for LESENSE_AEX2 */
#define _LESENSE_ALTEXCONF_AEX2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */
#define LESENSE_ALTEXCONF_AEX2_DEFAULT (_LESENSE_ALTEXCONF_AEX2_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_AEX3 (0x1UL << 19) /**< ALTEX3 always excite enable */
+#define LESENSE_ALTEXCONF_AEX3 (0x1UL << 19) /**< ALTEX3 Always Excite Enable */
#define _LESENSE_ALTEXCONF_AEX3_SHIFT 19 /**< Shift value for LESENSE_AEX3 */
#define _LESENSE_ALTEXCONF_AEX3_MASK 0x80000UL /**< Bit mask for LESENSE_AEX3 */
#define _LESENSE_ALTEXCONF_AEX3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */
#define LESENSE_ALTEXCONF_AEX3_DEFAULT (_LESENSE_ALTEXCONF_AEX3_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_AEX4 (0x1UL << 20) /**< ALTEX4 always excite enable */
+#define LESENSE_ALTEXCONF_AEX4 (0x1UL << 20) /**< ALTEX4 Always Excite Enable */
#define _LESENSE_ALTEXCONF_AEX4_SHIFT 20 /**< Shift value for LESENSE_AEX4 */
#define _LESENSE_ALTEXCONF_AEX4_MASK 0x100000UL /**< Bit mask for LESENSE_AEX4 */
#define _LESENSE_ALTEXCONF_AEX4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */
#define LESENSE_ALTEXCONF_AEX4_DEFAULT (_LESENSE_ALTEXCONF_AEX4_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_AEX5 (0x1UL << 21) /**< ALTEX5 always excite enable */
+#define LESENSE_ALTEXCONF_AEX5 (0x1UL << 21) /**< ALTEX5 Always Excite Enable */
#define _LESENSE_ALTEXCONF_AEX5_SHIFT 21 /**< Shift value for LESENSE_AEX5 */
#define _LESENSE_ALTEXCONF_AEX5_MASK 0x200000UL /**< Bit mask for LESENSE_AEX5 */
#define _LESENSE_ALTEXCONF_AEX5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */
#define LESENSE_ALTEXCONF_AEX5_DEFAULT (_LESENSE_ALTEXCONF_AEX5_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_AEX6 (0x1UL << 22) /**< ALTEX6 always excite enable */
+#define LESENSE_ALTEXCONF_AEX6 (0x1UL << 22) /**< ALTEX6 Always Excite Enable */
#define _LESENSE_ALTEXCONF_AEX6_SHIFT 22 /**< Shift value for LESENSE_AEX6 */
#define _LESENSE_ALTEXCONF_AEX6_MASK 0x400000UL /**< Bit mask for LESENSE_AEX6 */
#define _LESENSE_ALTEXCONF_AEX6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */
#define LESENSE_ALTEXCONF_AEX6_DEFAULT (_LESENSE_ALTEXCONF_AEX6_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_AEX7 (0x1UL << 23) /**< ALTEX7 always excite enable */
+#define LESENSE_ALTEXCONF_AEX7 (0x1UL << 23) /**< ALTEX7 Always Excite Enable */
#define _LESENSE_ALTEXCONF_AEX7_SHIFT 23 /**< Shift value for LESENSE_AEX7 */
#define _LESENSE_ALTEXCONF_AEX7_MASK 0x800000UL /**< Bit mask for LESENSE_AEX7 */
#define _LESENSE_ALTEXCONF_AEX7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */
@@ -1009,117 +1016,117 @@ typedef struct
/* Bit fields for LESENSE IF */
#define _LESENSE_IF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IF */
#define _LESENSE_IF_MASK 0x007FFFFFUL /**< Mask for LESENSE_IF */
-#define LESENSE_IF_CH0 (0x1UL << 0) /**< CH0 interrupt flag */
+#define LESENSE_IF_CH0 (0x1UL << 0) /**< CH0 Interrupt Flag */
#define _LESENSE_IF_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */
#define _LESENSE_IF_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */
#define _LESENSE_IF_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
#define LESENSE_IF_CH0_DEFAULT (_LESENSE_IF_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH1 (0x1UL << 1) /**< CH1 interrupt flag */
+#define LESENSE_IF_CH1 (0x1UL << 1) /**< CH1 Interrupt Flag */
#define _LESENSE_IF_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */
#define _LESENSE_IF_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */
#define _LESENSE_IF_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
#define LESENSE_IF_CH1_DEFAULT (_LESENSE_IF_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH2 (0x1UL << 2) /**< CH2 interrupt flag */
+#define LESENSE_IF_CH2 (0x1UL << 2) /**< CH2 Interrupt Flag */
#define _LESENSE_IF_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */
#define _LESENSE_IF_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */
#define _LESENSE_IF_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
#define LESENSE_IF_CH2_DEFAULT (_LESENSE_IF_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH3 (0x1UL << 3) /**< CH3 interrupt flag */
+#define LESENSE_IF_CH3 (0x1UL << 3) /**< CH3 Interrupt Flag */
#define _LESENSE_IF_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */
#define _LESENSE_IF_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */
#define _LESENSE_IF_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
#define LESENSE_IF_CH3_DEFAULT (_LESENSE_IF_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH4 (0x1UL << 4) /**< CH4 interrupt flag */
+#define LESENSE_IF_CH4 (0x1UL << 4) /**< CH4 Interrupt Flag */
#define _LESENSE_IF_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */
#define _LESENSE_IF_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */
#define _LESENSE_IF_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
#define LESENSE_IF_CH4_DEFAULT (_LESENSE_IF_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH5 (0x1UL << 5) /**< CH5 interrupt flag */
+#define LESENSE_IF_CH5 (0x1UL << 5) /**< CH5 Interrupt Flag */
#define _LESENSE_IF_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */
#define _LESENSE_IF_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */
#define _LESENSE_IF_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
#define LESENSE_IF_CH5_DEFAULT (_LESENSE_IF_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH6 (0x1UL << 6) /**< CH6 interrupt flag */
+#define LESENSE_IF_CH6 (0x1UL << 6) /**< CH6 Interrupt Flag */
#define _LESENSE_IF_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */
#define _LESENSE_IF_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */
#define _LESENSE_IF_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
#define LESENSE_IF_CH6_DEFAULT (_LESENSE_IF_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH7 (0x1UL << 7) /**< CH7 interrupt flag */
+#define LESENSE_IF_CH7 (0x1UL << 7) /**< CH7 Interrupt Flag */
#define _LESENSE_IF_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */
#define _LESENSE_IF_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */
#define _LESENSE_IF_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
#define LESENSE_IF_CH7_DEFAULT (_LESENSE_IF_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH8 (0x1UL << 8) /**< CH8 interrupt flag */
+#define LESENSE_IF_CH8 (0x1UL << 8) /**< CH8 Interrupt Flag */
#define _LESENSE_IF_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */
#define _LESENSE_IF_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */
#define _LESENSE_IF_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
#define LESENSE_IF_CH8_DEFAULT (_LESENSE_IF_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH9 (0x1UL << 9) /**< CH9 interrupt flag */
+#define LESENSE_IF_CH9 (0x1UL << 9) /**< CH9 Interrupt Flag */
#define _LESENSE_IF_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */
#define _LESENSE_IF_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */
#define _LESENSE_IF_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
#define LESENSE_IF_CH9_DEFAULT (_LESENSE_IF_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH10 (0x1UL << 10) /**< CH10 interrupt flag */
+#define LESENSE_IF_CH10 (0x1UL << 10) /**< CH10 Interrupt Flag */
#define _LESENSE_IF_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */
#define _LESENSE_IF_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */
#define _LESENSE_IF_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
#define LESENSE_IF_CH10_DEFAULT (_LESENSE_IF_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH11 (0x1UL << 11) /**< CH11 interrupt flag */
+#define LESENSE_IF_CH11 (0x1UL << 11) /**< CH11 Interrupt Flag */
#define _LESENSE_IF_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */
#define _LESENSE_IF_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */
#define _LESENSE_IF_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
#define LESENSE_IF_CH11_DEFAULT (_LESENSE_IF_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH12 (0x1UL << 12) /**< CH12 interrupt flag */
+#define LESENSE_IF_CH12 (0x1UL << 12) /**< CH12 Interrupt Flag */
#define _LESENSE_IF_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */
#define _LESENSE_IF_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */
#define _LESENSE_IF_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
#define LESENSE_IF_CH12_DEFAULT (_LESENSE_IF_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH13 (0x1UL << 13) /**< CH13 interrupt flag */
+#define LESENSE_IF_CH13 (0x1UL << 13) /**< CH13 Interrupt Flag */
#define _LESENSE_IF_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */
#define _LESENSE_IF_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */
#define _LESENSE_IF_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
#define LESENSE_IF_CH13_DEFAULT (_LESENSE_IF_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH14 (0x1UL << 14) /**< CH14 interrupt flag */
+#define LESENSE_IF_CH14 (0x1UL << 14) /**< CH14 Interrupt Flag */
#define _LESENSE_IF_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */
#define _LESENSE_IF_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */
#define _LESENSE_IF_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
#define LESENSE_IF_CH14_DEFAULT (_LESENSE_IF_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH15 (0x1UL << 15) /**< CH15 interrupt flag */
+#define LESENSE_IF_CH15 (0x1UL << 15) /**< CH15 Interrupt Flag */
#define _LESENSE_IF_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */
#define _LESENSE_IF_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */
#define _LESENSE_IF_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
#define LESENSE_IF_CH15_DEFAULT (_LESENSE_IF_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_SCANCOMPLETE (0x1UL << 16) /**< SCANCOMPLETE interrupt flag */
+#define LESENSE_IF_SCANCOMPLETE (0x1UL << 16) /**< SCANCOMPLETE Interrupt Flag */
#define _LESENSE_IF_SCANCOMPLETE_SHIFT 16 /**< Shift value for LESENSE_SCANCOMPLETE */
#define _LESENSE_IF_SCANCOMPLETE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANCOMPLETE */
#define _LESENSE_IF_SCANCOMPLETE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
#define LESENSE_IF_SCANCOMPLETE_DEFAULT (_LESENSE_IF_SCANCOMPLETE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_DEC (0x1UL << 17) /**< DEC interrupt flag */
+#define LESENSE_IF_DEC (0x1UL << 17) /**< DEC Interrupt Flag */
#define _LESENSE_IF_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */
#define _LESENSE_IF_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */
#define _LESENSE_IF_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
#define LESENSE_IF_DEC_DEFAULT (_LESENSE_IF_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_DECERR (0x1UL << 18) /**< DECERR interrupt flag */
+#define LESENSE_IF_DECERR (0x1UL << 18) /**< DECERR Interrupt Flag */
#define _LESENSE_IF_DECERR_SHIFT 18 /**< Shift value for LESENSE_DECERR */
#define _LESENSE_IF_DECERR_MASK 0x40000UL /**< Bit mask for LESENSE_DECERR */
#define _LESENSE_IF_DECERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
#define LESENSE_IF_DECERR_DEFAULT (_LESENSE_IF_DECERR_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_BUFDATAV (0x1UL << 19) /**< BUFDATAV interrupt flag */
+#define LESENSE_IF_BUFDATAV (0x1UL << 19) /**< BUFDATAV Interrupt Flag */
#define _LESENSE_IF_BUFDATAV_SHIFT 19 /**< Shift value for LESENSE_BUFDATAV */
#define _LESENSE_IF_BUFDATAV_MASK 0x80000UL /**< Bit mask for LESENSE_BUFDATAV */
#define _LESENSE_IF_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
#define LESENSE_IF_BUFDATAV_DEFAULT (_LESENSE_IF_BUFDATAV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_BUFLEVEL (0x1UL << 20) /**< BUFLEVEL interrupt flag */
+#define LESENSE_IF_BUFLEVEL (0x1UL << 20) /**< BUFLEVEL Interrupt Flag */
#define _LESENSE_IF_BUFLEVEL_SHIFT 20 /**< Shift value for LESENSE_BUFLEVEL */
#define _LESENSE_IF_BUFLEVEL_MASK 0x100000UL /**< Bit mask for LESENSE_BUFLEVEL */
#define _LESENSE_IF_BUFLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
#define LESENSE_IF_BUFLEVEL_DEFAULT (_LESENSE_IF_BUFLEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_BUFOF (0x1UL << 21) /**< BUFOF interrupt flag */
+#define LESENSE_IF_BUFOF (0x1UL << 21) /**< BUFOF Interrupt Flag */
#define _LESENSE_IF_BUFOF_SHIFT 21 /**< Shift value for LESENSE_BUFOF */
#define _LESENSE_IF_BUFOF_MASK 0x200000UL /**< Bit mask for LESENSE_BUFOF */
#define _LESENSE_IF_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
#define LESENSE_IF_BUFOF_DEFAULT (_LESENSE_IF_BUFOF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CNTOF (0x1UL << 22) /**< CNTOF interrupt flag */
+#define LESENSE_IF_CNTOF (0x1UL << 22) /**< CNTOF Interrupt Flag */
#define _LESENSE_IF_CNTOF_SHIFT 22 /**< Shift value for LESENSE_CNTOF */
#define _LESENSE_IF_CNTOF_MASK 0x400000UL /**< Bit mask for LESENSE_CNTOF */
#define _LESENSE_IF_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
@@ -1499,7 +1506,7 @@ typedef struct
#define _LESENSE_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for LESENSE_CH0PEN */
#define _LESENSE_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */
#define LESENSE_ROUTEPEN_CH0PEN_DEFAULT (_LESENSE_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH0 Pin Enable */
+#define LESENSE_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */
#define _LESENSE_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for LESENSE_CH1PEN */
#define _LESENSE_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for LESENSE_CH1PEN */
#define _LESENSE_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */
@@ -1630,12 +1637,12 @@ typedef struct
#define _LESENSE_ST_TCONFA_NEXTSTATE_MASK 0x1F00UL /**< Bit mask for LESENSE_NEXTSTATE */
#define _LESENSE_ST_TCONFA_NEXTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_NEXTSTATE_DEFAULT (_LESENSE_ST_TCONFA_NEXTSTATE_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_CHAIN (0x1UL << 14) /**< Enable state descriptor chaining */
+#define LESENSE_ST_TCONFA_CHAIN (0x1UL << 14) /**< Enable State Descriptor Chaining */
#define _LESENSE_ST_TCONFA_CHAIN_SHIFT 14 /**< Shift value for LESENSE_CHAIN */
#define _LESENSE_ST_TCONFA_CHAIN_MASK 0x4000UL /**< Bit mask for LESENSE_CHAIN */
#define _LESENSE_ST_TCONFA_CHAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_CHAIN_DEFAULT (_LESENSE_ST_TCONFA_CHAIN_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_SETIF (0x1UL << 15) /**< Set interrupt flag enable */
+#define LESENSE_ST_TCONFA_SETIF (0x1UL << 15) /**< Set Interrupt Flag Enable */
#define _LESENSE_ST_TCONFA_SETIF_SHIFT 15 /**< Shift value for LESENSE_SETIF */
#define _LESENSE_ST_TCONFA_SETIF_MASK 0x8000UL /**< Bit mask for LESENSE_SETIF */
#define _LESENSE_ST_TCONFA_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */
@@ -1644,27 +1651,27 @@ typedef struct
#define _LESENSE_ST_TCONFA_PRSACT_MASK 0x70000UL /**< Bit mask for LESENSE_PRSACT */
#define _LESENSE_ST_TCONFA_PRSACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_NONE 0x00000000UL /**< Mode NONE for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_PRS0 0x00000001UL /**< Mode PRS0 for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFA */
+#define _LESENSE_ST_TCONFA_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_DOWN 0x00000002UL /**< Mode DOWN for LESENSE_ST_TCONFA */
+#define _LESENSE_ST_TCONFA_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_PRS01 0x00000003UL /**< Mode PRS01 for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_PRS2 0x00000004UL /**< Mode PRS2 for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 0x00000005UL /**< Mode UPANDPRS2 for LESENSE_ST_TCONFA */
+#define _LESENSE_ST_TCONFA_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_PRS12 0x00000006UL /**< Mode PRS12 for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 0x00000006UL /**< Mode DOWNANDPRS2 for LESENSE_ST_TCONFA */
#define _LESENSE_ST_TCONFA_PRSACT_PRS012 0x00000007UL /**< Mode PRS012 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_DEFAULT (_LESENSE_ST_TCONFA_PRSACT_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_NONE (_LESENSE_ST_TCONFA_PRSACT_NONE << 16) /**< Shifted mode NONE for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_PRSACT_UP (_LESENSE_ST_TCONFA_PRSACT_UP << 16) /**< Shifted mode UP for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_PRS0 (_LESENSE_ST_TCONFA_PRSACT_PRS0 << 16) /**< Shifted mode PRS0 for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_PRSACT_PRS1 (_LESENSE_ST_TCONFA_PRSACT_PRS1 << 16) /**< Shifted mode PRS1 for LESENSE_ST_TCONFA */
+#define LESENSE_ST_TCONFA_PRSACT_UP (_LESENSE_ST_TCONFA_PRSACT_UP << 16) /**< Shifted mode UP for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_DOWN (_LESENSE_ST_TCONFA_PRSACT_DOWN << 16) /**< Shifted mode DOWN for LESENSE_ST_TCONFA */
+#define LESENSE_ST_TCONFA_PRSACT_PRS1 (_LESENSE_ST_TCONFA_PRSACT_PRS1 << 16) /**< Shifted mode PRS1 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_PRS01 (_LESENSE_ST_TCONFA_PRSACT_PRS01 << 16) /**< Shifted mode PRS01 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_PRS2 (_LESENSE_ST_TCONFA_PRSACT_PRS2 << 16) /**< Shifted mode PRS2 for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_PRSACT_PRS02 (_LESENSE_ST_TCONFA_PRSACT_PRS02 << 16) /**< Shifted mode PRS02 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 (_LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 << 16) /**< Shifted mode UPANDPRS2 for LESENSE_ST_TCONFA */
+#define LESENSE_ST_TCONFA_PRSACT_PRS02 (_LESENSE_ST_TCONFA_PRSACT_PRS02 << 16) /**< Shifted mode PRS02 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_PRS12 (_LESENSE_ST_TCONFA_PRSACT_PRS12 << 16) /**< Shifted mode PRS12 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 (_LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 << 16) /**< Shifted mode DOWNANDPRS2 for LESENSE_ST_TCONFA */
#define LESENSE_ST_TCONFA_PRSACT_PRS012 (_LESENSE_ST_TCONFA_PRSACT_PRS012 << 16) /**< Shifted mode PRS012 for LESENSE_ST_TCONFA */
@@ -1684,7 +1691,7 @@ typedef struct
#define _LESENSE_ST_TCONFB_NEXTSTATE_MASK 0x1F00UL /**< Bit mask for LESENSE_NEXTSTATE */
#define _LESENSE_ST_TCONFB_NEXTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_NEXTSTATE_DEFAULT (_LESENSE_ST_TCONFB_NEXTSTATE_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_SETIF (0x1UL << 15) /**< Set interrupt flag */
+#define LESENSE_ST_TCONFB_SETIF (0x1UL << 15) /**< Set Interrupt Flag */
#define _LESENSE_ST_TCONFB_SETIF_SHIFT 15 /**< Shift value for LESENSE_SETIF */
#define _LESENSE_ST_TCONFB_SETIF_MASK 0x8000UL /**< Bit mask for LESENSE_SETIF */
#define _LESENSE_ST_TCONFB_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */
@@ -1693,27 +1700,27 @@ typedef struct
#define _LESENSE_ST_TCONFB_PRSACT_MASK 0x70000UL /**< Bit mask for LESENSE_PRSACT */
#define _LESENSE_ST_TCONFB_PRSACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_NONE 0x00000000UL /**< Mode NONE for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_PRS0 0x00000001UL /**< Mode PRS0 for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFB */
+#define _LESENSE_ST_TCONFB_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_DOWN 0x00000002UL /**< Mode DOWN for LESENSE_ST_TCONFB */
+#define _LESENSE_ST_TCONFB_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_PRS01 0x00000003UL /**< Mode PRS01 for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_PRS2 0x00000004UL /**< Mode PRS2 for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 0x00000005UL /**< Mode UPANDPRS2 for LESENSE_ST_TCONFB */
+#define _LESENSE_ST_TCONFB_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_PRS12 0x00000006UL /**< Mode PRS12 for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 0x00000006UL /**< Mode DOWNANDPRS2 for LESENSE_ST_TCONFB */
#define _LESENSE_ST_TCONFB_PRSACT_PRS012 0x00000007UL /**< Mode PRS012 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_DEFAULT (_LESENSE_ST_TCONFB_PRSACT_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_NONE (_LESENSE_ST_TCONFB_PRSACT_NONE << 16) /**< Shifted mode NONE for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_PRSACT_UP (_LESENSE_ST_TCONFB_PRSACT_UP << 16) /**< Shifted mode UP for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_PRS0 (_LESENSE_ST_TCONFB_PRSACT_PRS0 << 16) /**< Shifted mode PRS0 for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_PRSACT_PRS1 (_LESENSE_ST_TCONFB_PRSACT_PRS1 << 16) /**< Shifted mode PRS1 for LESENSE_ST_TCONFB */
+#define LESENSE_ST_TCONFB_PRSACT_UP (_LESENSE_ST_TCONFB_PRSACT_UP << 16) /**< Shifted mode UP for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_DOWN (_LESENSE_ST_TCONFB_PRSACT_DOWN << 16) /**< Shifted mode DOWN for LESENSE_ST_TCONFB */
+#define LESENSE_ST_TCONFB_PRSACT_PRS1 (_LESENSE_ST_TCONFB_PRSACT_PRS1 << 16) /**< Shifted mode PRS1 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_PRS01 (_LESENSE_ST_TCONFB_PRSACT_PRS01 << 16) /**< Shifted mode PRS01 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_PRS2 (_LESENSE_ST_TCONFB_PRSACT_PRS2 << 16) /**< Shifted mode PRS2 for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_PRSACT_PRS02 (_LESENSE_ST_TCONFB_PRSACT_PRS02 << 16) /**< Shifted mode PRS02 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 (_LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 << 16) /**< Shifted mode UPANDPRS2 for LESENSE_ST_TCONFB */
+#define LESENSE_ST_TCONFB_PRSACT_PRS02 (_LESENSE_ST_TCONFB_PRSACT_PRS02 << 16) /**< Shifted mode PRS02 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_PRS12 (_LESENSE_ST_TCONFB_PRSACT_PRS12 << 16) /**< Shifted mode PRS12 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 (_LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 << 16) /**< Shifted mode DOWNANDPRS2 for LESENSE_ST_TCONFB */
#define LESENSE_ST_TCONFB_PRSACT_PRS012 (_LESENSE_ST_TCONFB_PRSACT_PRS012 << 16) /**< Shifted mode PRS012 for LESENSE_ST_TCONFB */
@@ -1791,7 +1798,7 @@ typedef struct
#define LESENSE_CH_INTERACT_EXMODE_HIGH (_LESENSE_CH_INTERACT_EXMODE_HIGH << 17) /**< Shifted mode HIGH for LESENSE_CH_INTERACT */
#define LESENSE_CH_INTERACT_EXMODE_LOW (_LESENSE_CH_INTERACT_EXMODE_LOW << 17) /**< Shifted mode LOW for LESENSE_CH_INTERACT */
#define LESENSE_CH_INTERACT_EXMODE_DACOUT (_LESENSE_CH_INTERACT_EXMODE_DACOUT << 17) /**< Shifted mode DACOUT for LESENSE_CH_INTERACT */
-#define LESENSE_CH_INTERACT_EXCLK (0x1UL << 19) /**< Select clock used for excitation timing */
+#define LESENSE_CH_INTERACT_EXCLK (0x1UL << 19) /**< Select Clock Used for Excitation Timing */
#define _LESENSE_CH_INTERACT_EXCLK_SHIFT 19 /**< Shift value for LESENSE_EXCLK */
#define _LESENSE_CH_INTERACT_EXCLK_MASK 0x80000UL /**< Bit mask for LESENSE_EXCLK */
#define _LESENSE_CH_INTERACT_EXCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */
@@ -1800,7 +1807,7 @@ typedef struct
#define LESENSE_CH_INTERACT_EXCLK_DEFAULT (_LESENSE_CH_INTERACT_EXCLK_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */
#define LESENSE_CH_INTERACT_EXCLK_LFACLK (_LESENSE_CH_INTERACT_EXCLK_LFACLK << 19) /**< Shifted mode LFACLK for LESENSE_CH_INTERACT */
#define LESENSE_CH_INTERACT_EXCLK_AUXHFRCO (_LESENSE_CH_INTERACT_EXCLK_AUXHFRCO << 19) /**< Shifted mode AUXHFRCO for LESENSE_CH_INTERACT */
-#define LESENSE_CH_INTERACT_SAMPLECLK (0x1UL << 20) /**< Select clock used for timing of sample delay */
+#define LESENSE_CH_INTERACT_SAMPLECLK (0x1UL << 20) /**< Select Clock Used for Timing of Sample Delay */
#define _LESENSE_CH_INTERACT_SAMPLECLK_SHIFT 20 /**< Shift value for LESENSE_SAMPLECLK */
#define _LESENSE_CH_INTERACT_SAMPLECLK_MASK 0x100000UL /**< Bit mask for LESENSE_SAMPLECLK */
#define _LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */
@@ -1809,7 +1816,7 @@ typedef struct
#define LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT (_LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */
#define LESENSE_CH_INTERACT_SAMPLECLK_LFACLK (_LESENSE_CH_INTERACT_SAMPLECLK_LFACLK << 20) /**< Shifted mode LFACLK for LESENSE_CH_INTERACT */
#define LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO (_LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for LESENSE_CH_INTERACT */
-#define LESENSE_CH_INTERACT_ALTEX (0x1UL << 21) /**< Use alternative excite pin */
+#define LESENSE_CH_INTERACT_ALTEX (0x1UL << 21) /**< Use Alternative Excite Pin */
#define _LESENSE_CH_INTERACT_ALTEX_SHIFT 21 /**< Shift value for LESENSE_ALTEX */
#define _LESENSE_CH_INTERACT_ALTEX_MASK 0x200000UL /**< Bit mask for LESENSE_ALTEX */
#define _LESENSE_CH_INTERACT_ALTEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */
@@ -1822,7 +1829,7 @@ typedef struct
#define _LESENSE_CH_EVAL_COMPTHRES_MASK 0xFFFFUL /**< Bit mask for LESENSE_COMPTHRES */
#define _LESENSE_CH_EVAL_COMPTHRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */
#define LESENSE_CH_EVAL_COMPTHRES_DEFAULT (_LESENSE_CH_EVAL_COMPTHRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */
-#define LESENSE_CH_EVAL_COMP (0x1UL << 16) /**< Select mode for threshold comparison */
+#define LESENSE_CH_EVAL_COMP (0x1UL << 16) /**< Select Mode for Threshold Comparison */
#define _LESENSE_CH_EVAL_COMP_SHIFT 16 /**< Shift value for LESENSE_COMP */
#define _LESENSE_CH_EVAL_COMP_MASK 0x10000UL /**< Bit mask for LESENSE_COMP */
#define _LESENSE_CH_EVAL_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */
@@ -1831,7 +1838,7 @@ typedef struct
#define LESENSE_CH_EVAL_COMP_DEFAULT (_LESENSE_CH_EVAL_COMP_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */
#define LESENSE_CH_EVAL_COMP_LESS (_LESENSE_CH_EVAL_COMP_LESS << 16) /**< Shifted mode LESS for LESENSE_CH_EVAL */
#define LESENSE_CH_EVAL_COMP_GE (_LESENSE_CH_EVAL_COMP_GE << 16) /**< Shifted mode GE for LESENSE_CH_EVAL */
-#define LESENSE_CH_EVAL_DECODE (0x1UL << 17) /**< Send result to decoder */
+#define LESENSE_CH_EVAL_DECODE (0x1UL << 17) /**< Send Result to Decoder */
#define _LESENSE_CH_EVAL_DECODE_SHIFT 17 /**< Shift value for LESENSE_DECODE */
#define _LESENSE_CH_EVAL_DECODE_MASK 0x20000UL /**< Bit mask for LESENSE_DECODE */
#define _LESENSE_CH_EVAL_DECODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */
@@ -1846,7 +1853,7 @@ typedef struct
#define LESENSE_CH_EVAL_STRSAMPLE_DISABLE (_LESENSE_CH_EVAL_STRSAMPLE_DISABLE << 18) /**< Shifted mode DISABLE for LESENSE_CH_EVAL */
#define LESENSE_CH_EVAL_STRSAMPLE_DATA (_LESENSE_CH_EVAL_STRSAMPLE_DATA << 18) /**< Shifted mode DATA for LESENSE_CH_EVAL */
#define LESENSE_CH_EVAL_STRSAMPLE_DATASRC (_LESENSE_CH_EVAL_STRSAMPLE_DATASRC << 18) /**< Shifted mode DATASRC for LESENSE_CH_EVAL */
-#define LESENSE_CH_EVAL_SCANRESINV (0x1UL << 20) /**< Enable inversion of result */
+#define LESENSE_CH_EVAL_SCANRESINV (0x1UL << 20) /**< Enable Inversion of Result */
#define _LESENSE_CH_EVAL_SCANRESINV_SHIFT 20 /**< Shift value for LESENSE_SCANRESINV */
#define _LESENSE_CH_EVAL_SCANRESINV_MASK 0x100000UL /**< Bit mask for LESENSE_SCANRESINV */
#define _LESENSE_CH_EVAL_SCANRESINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */
@@ -1862,6 +1869,6 @@ typedef struct
#define LESENSE_CH_EVAL_MODE_SLIDINGWIN (_LESENSE_CH_EVAL_MODE_SLIDINGWIN << 21) /**< Shifted mode SLIDINGWIN for LESENSE_CH_EVAL */
#define LESENSE_CH_EVAL_MODE_STEPDET (_LESENSE_CH_EVAL_MODE_STEPDET << 21) /**< Shifted mode STEPDET for LESENSE_CH_EVAL */
+/** @} */
/** @} End of group EFR32FG12P_LESENSE */
/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_lesense_buf.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_lesense_buf.h
similarity index 52%
rename from mcu/efr/common/vendor/efr32fg13/efr32fg13p_lesense_buf.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_lesense_buf.h
index 39b728df..7bf5e997 100644
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_lesense_buf.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_lesense_buf.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efr32fg13p_lesense_buf.h
- * @brief EFR32FG13P_LESENSE_BUF register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+/***************************************************************************//**
+ * @file
+ * @brief EFR32FG12P_LESENSE_BUF register and bit field definitions
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#if defined(__ICCARM__)
#pragma system_include /* Treat file as system include file. */
@@ -36,14 +34,14 @@
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @brief LESENSE_BUF LESENSE BUF Register
- * @ingroup EFR32FG13P_LESENSE
- *****************************************************************************/
+ * @ingroup EFR32FG12P_LESENSE
+ ******************************************************************************/
typedef struct {
__IOM uint32_t DATA; /**< Scan Results */
} LESENSE_BUF_TypeDef;
diff --git a/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_lesense_ch.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_lesense_ch.h
new file mode 100644
index 00000000..19378030
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_lesense_ch.h
@@ -0,0 +1,52 @@
+/***************************************************************************//**
+ * @file
+ * @brief EFR32FG12P_LESENSE_CH register and bit field definitions
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @brief LESENSE_CH LESENSE CH Register
+ * @ingroup EFR32FG12P_LESENSE
+ ******************************************************************************/
+typedef struct {
+ __IOM uint32_t TIMING; /**< Scan Configuration */
+ __IOM uint32_t INTERACT; /**< Scan Configuration */
+ __IOM uint32_t EVAL; /**< Scan Configuration */
+ uint32_t RESERVED0[1U]; /**< Reserved future */
+} LESENSE_CH_TypeDef;
+
+/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_lesense_st.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_lesense_st.h
similarity index 53%
rename from mcu/efr/common/vendor/efr32fg13/efr32fg13p_lesense_st.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_lesense_st.h
index 4f7401a6..5ffc2958 100644
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_lesense_st.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_lesense_st.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efr32fg13p_lesense_st.h
- * @brief EFR32FG13P_LESENSE_ST register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+/***************************************************************************//**
+ * @file
+ * @brief EFR32FG12P_LESENSE_ST register and bit field definitions
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#if defined(__ICCARM__)
#pragma system_include /* Treat file as system include file. */
@@ -36,14 +34,14 @@
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @brief LESENSE_ST LESENSE ST Register
- * @ingroup EFR32FG13P_LESENSE
- *****************************************************************************/
+ * @ingroup EFR32FG12P_LESENSE
+ ******************************************************************************/
typedef struct {
__IOM uint32_t TCONFA; /**< State Transition Configuration a */
__IOM uint32_t TCONFB; /**< State Transition Configuration B */
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_letimer.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_letimer.h
similarity index 96%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_letimer.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_letimer.h
index 06ad7192..7b94d2e2 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_letimer.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_letimer.h
@@ -1,73 +1,80 @@
-/**************************************************************************//**
- * @file efr32fg12p_letimer.h
+/***************************************************************************//**
+ * @file
* @brief EFR32FG12P_LETIMER register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_LETIMER
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P_LETIMER LETIMER
* @{
* @brief EFR32FG12P_LETIMER Register Declaration
- *****************************************************************************/
-typedef struct
-{
- __IOM uint32_t CTRL; /**< Control Register */
- __IOM uint32_t CMD; /**< Command Register */
- __IM uint32_t STATUS; /**< Status Register */
- __IOM uint32_t CNT; /**< Counter Value Register */
- __IOM uint32_t COMP0; /**< Compare Value Register 0 */
- __IOM uint32_t COMP1; /**< Compare Value Register 1 */
- __IOM uint32_t REP0; /**< Repeat Counter Register 0 */
- __IOM uint32_t REP1; /**< Repeat Counter Register 1 */
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ ******************************************************************************/
+/** LETIMER Register Declaration */
+typedef struct {
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IOM uint32_t CNT; /**< Counter Value Register */
+ __IOM uint32_t COMP0; /**< Compare Value Register 0 */
+ __IOM uint32_t COMP1; /**< Compare Value Register 1 */
+ __IOM uint32_t REP0; /**< Repeat Counter Register 0 */
+ __IOM uint32_t REP1; /**< Repeat Counter Register 1 */
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
- uint32_t RESERVED0[1]; /**< Reserved for future use **/
- __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use **/
+ __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
- uint32_t RESERVED1[2]; /**< Reserved for future use **/
- __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
- __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
+ uint32_t RESERVED1[2U]; /**< Reserved for future use **/
+ __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
+ __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
- uint32_t RESERVED2[2]; /**< Reserved for future use **/
- __IOM uint32_t PRSSEL; /**< PRS Input Select Register */
-} LETIMER_TypeDef; /** @} */
+ uint32_t RESERVED2[2U]; /**< Reserved for future use **/
+ __IOM uint32_t PRSSEL; /**< PRS Input Select Register */
+} LETIMER_TypeDef; /** @} */
-/**************************************************************************//**
- * @defgroup EFR32FG12P_LETIMER_BitFields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_LETIMER
* @{
- *****************************************************************************/
+ * @defgroup EFR32FG12P_LETIMER_BitFields LETIMER Bit Fields
+ * @{
+ ******************************************************************************/
/* Bit fields for LETIMER CTRL */
#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */
@@ -123,7 +130,7 @@ typedef struct
#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */
#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */
-#define LETIMER_CTRL_COMP0TOP (0x1UL << 9) /**< Compare Value 0 Is Top Value */
+#define LETIMER_CTRL_COMP0TOP (0x1UL << 9) /**< Compare Value 0 is Top Value */
#define _LETIMER_CTRL_COMP0TOP_SHIFT 9 /**< Shift value for LETIMER_COMP0TOP */
#define _LETIMER_CTRL_COMP0TOP_MASK 0x200UL /**< Bit mask for LETIMER_COMP0TOP */
#define _LETIMER_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
@@ -615,6 +622,6 @@ typedef struct
#define LETIMER_PRSSEL_PRSCLEARMODE_FALLING (_LETIMER_PRSSEL_PRSCLEARMODE_FALLING << 26) /**< Shifted mode FALLING for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSCLEARMODE_BOTH (_LETIMER_PRSSEL_PRSCLEARMODE_BOTH << 26) /**< Shifted mode BOTH for LETIMER_PRSSEL */
+/** @} */
/** @} End of group EFR32FG12P_LETIMER */
/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_leuart.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_leuart.h
similarity index 96%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_leuart.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_leuart.h
index a385fdc9..2839f4ca 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_leuart.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_leuart.h
@@ -1,76 +1,83 @@
-/**************************************************************************//**
- * @file efr32fg12p_leuart.h
+/***************************************************************************//**
+ * @file
* @brief EFR32FG12P_LEUART register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_LEUART
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P_LEUART LEUART
* @{
* @brief EFR32FG12P_LEUART Register Declaration
- *****************************************************************************/
-typedef struct
-{
- __IOM uint32_t CTRL; /**< Control Register */
- __IOM uint32_t CMD; /**< Command Register */
- __IM uint32_t STATUS; /**< Status Register */
- __IOM uint32_t CLKDIV; /**< Clock Control Register */
- __IOM uint32_t STARTFRAME; /**< Start Frame Register */
- __IOM uint32_t SIGFRAME; /**< Signal Frame Register */
- __IM uint32_t RXDATAX; /**< Receive Buffer Data Extended Register */
- __IM uint32_t RXDATA; /**< Receive Buffer Data Register */
- __IM uint32_t RXDATAXP; /**< Receive Buffer Data Extended Peek Register */
- __IOM uint32_t TXDATAX; /**< Transmit Buffer Data Extended Register */
- __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- __IOM uint32_t PULSECTRL; /**< Pulse Control Register */
+ ******************************************************************************/
+/** LEUART Register Declaration */
+typedef struct {
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IOM uint32_t CLKDIV; /**< Clock Control Register */
+ __IOM uint32_t STARTFRAME; /**< Start Frame Register */
+ __IOM uint32_t SIGFRAME; /**< Signal Frame Register */
+ __IM uint32_t RXDATAX; /**< Receive Buffer Data Extended Register */
+ __IM uint32_t RXDATA; /**< Receive Buffer Data Register */
+ __IM uint32_t RXDATAXP; /**< Receive Buffer Data Extended Peek Register */
+ __IOM uint32_t TXDATAX; /**< Transmit Buffer Data Extended Register */
+ __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IOM uint32_t PULSECTRL; /**< Pulse Control Register */
- __IOM uint32_t FREEZE; /**< Freeze Register */
- __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
+ __IOM uint32_t FREEZE; /**< Freeze Register */
+ __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
- uint32_t RESERVED0[3]; /**< Reserved for future use **/
- __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
- __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
- uint32_t RESERVED1[2]; /**< Reserved for future use **/
- __IOM uint32_t INPUT; /**< LEUART Input Register */
-} LEUART_TypeDef; /** @} */
+ uint32_t RESERVED0[3U]; /**< Reserved for future use **/
+ __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
+ __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
+ uint32_t RESERVED1[2U]; /**< Reserved for future use **/
+ __IOM uint32_t INPUT; /**< LEUART Input Register */
+} LEUART_TypeDef; /** @} */
-/**************************************************************************//**
- * @defgroup EFR32FG12P_LEUART_BitFields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_LEUART
* @{
- *****************************************************************************/
+ * @defgroup EFR32FG12P_LEUART_BitFields LEUART Bit Fields
+ * @{
+ ******************************************************************************/
/* Bit fields for LEUART CTRL */
#define _LEUART_CTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_CTRL */
@@ -108,12 +115,12 @@ typedef struct
#define LEUART_CTRL_STOPBITS_DEFAULT (_LEUART_CTRL_STOPBITS_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_STOPBITS_ONE (_LEUART_CTRL_STOPBITS_ONE << 4) /**< Shifted mode ONE for LEUART_CTRL */
#define LEUART_CTRL_STOPBITS_TWO (_LEUART_CTRL_STOPBITS_TWO << 4) /**< Shifted mode TWO for LEUART_CTRL */
-#define LEUART_CTRL_INV (0x1UL << 5) /**< Invert Input And Output */
+#define LEUART_CTRL_INV (0x1UL << 5) /**< Invert Input and Output */
#define _LEUART_CTRL_INV_SHIFT 5 /**< Shift value for LEUART_INV */
#define _LEUART_CTRL_INV_MASK 0x20UL /**< Bit mask for LEUART_INV */
#define _LEUART_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_INV_DEFAULT (_LEUART_CTRL_INV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CTRL */
-#define LEUART_CTRL_ERRSDMA (0x1UL << 6) /**< Clear RX DMA On Error */
+#define LEUART_CTRL_ERRSDMA (0x1UL << 6) /**< Clear RX DMA on Error */
#define _LEUART_CTRL_ERRSDMA_SHIFT 6 /**< Shift value for LEUART_ERRSDMA */
#define _LEUART_CTRL_ERRSDMA_MASK 0x40UL /**< Bit mask for LEUART_ERRSDMA */
#define _LEUART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
@@ -324,7 +331,7 @@ typedef struct
#define _LEUART_TXDATAX_TXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_TXDATA */
#define _LEUART_TXDATAX_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
#define LEUART_TXDATAX_TXDATA_DEFAULT (_LEUART_TXDATAX_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
-#define LEUART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */
+#define LEUART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data as Break */
#define _LEUART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for LEUART_TXBREAK */
#define _LEUART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for LEUART_TXBREAK */
#define _LEUART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
@@ -830,6 +837,6 @@ typedef struct
#define _LEUART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */
#define LEUART_INPUT_RXPRS_DEFAULT (_LEUART_INPUT_RXPRS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_INPUT */
+/** @} */
/** @} End of group EFR32FG12P_LEUART */
/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_msc.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_msc.h
similarity index 93%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_msc.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_msc.h
index f200f94f..d733386f 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_msc.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_msc.h
@@ -1,55 +1,60 @@
-/**************************************************************************//**
- * @file efr32fg12p_msc.h
+/***************************************************************************//**
+ * @file
* @brief EFR32FG12P_MSC register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_MSC
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P_MSC MSC
* @{
* @brief EFR32FG12P_MSC Register Declaration
- *****************************************************************************/
-typedef struct
-{
+ ******************************************************************************/
+/** MSC Register Declaration */
+typedef struct {
__IOM uint32_t CTRL; /**< Memory System Control Register */
__IOM uint32_t READCTRL; /**< Read Control Register */
__IOM uint32_t WRITECTRL; /**< Write Control Register */
__IOM uint32_t WRITECMD; /**< Write Command Register */
__IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */
- uint32_t RESERVED0[1]; /**< Reserved for future use **/
+ uint32_t RESERVED0[1U]; /**< Reserved for future use **/
__IOM uint32_t WDATA; /**< Write Data Register */
__IM uint32_t STATUS; /**< Status Register */
- uint32_t RESERVED1[4]; /**< Reserved for future use **/
+ uint32_t RESERVED1[4U]; /**< Reserved for future use **/
__IM uint32_t IF; /**< Interrupt Flag Register */
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
@@ -59,29 +64,31 @@ typedef struct
__IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */
__IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */
- uint32_t RESERVED2[1]; /**< Reserved for future use **/
+ uint32_t RESERVED2[1U]; /**< Reserved for future use **/
__IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */
- uint32_t RESERVED3[1]; /**< Reserved for future use **/
+ uint32_t RESERVED3[1U]; /**< Reserved for future use **/
__IOM uint32_t STARTUP; /**< Startup Control */
- uint32_t RESERVED4[4]; /**< Reserved for future use **/
+ uint32_t RESERVED4[4U]; /**< Reserved for future use **/
__IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */
__IOM uint32_t CMD; /**< Command Register */
- uint32_t RESERVED5[6]; /**< Reserved for future use **/
- __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader read and write enable, write once register */
+ uint32_t RESERVED5[6U]; /**< Reserved for future use **/
+ __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */
__IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */
__IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */
- uint32_t RESERVED6[25]; /**< Reserved for future use **/
- __IOM uint32_t RAMCTRL; /**< RAM Control enable Register */
+ uint32_t RESERVED6[25U]; /**< Reserved for future use **/
+ __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */
} MSC_TypeDef; /** @} */
-/**************************************************************************//**
- * @defgroup EFR32FG12P_MSC_BitFields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_MSC
+ * @{
+ * @defgroup EFR32FG12P_MSC_BitFields MSC Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for MSC CTRL */
#define _MSC_CTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_CTRL */
@@ -96,7 +103,7 @@ typedef struct
#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */
#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */
#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */
-#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up On Demand During Wake Up */
+#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */
#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */
#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */
#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */
@@ -161,7 +168,7 @@ typedef struct
/* Bit fields for MSC WRITECTRL */
#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */
#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */
-#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */
+#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */
#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */
#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */
#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
@@ -180,7 +187,7 @@ typedef struct
/* Bit fields for MSC WRITECMD */
#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */
#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */
-#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB into ADDR */
+#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */
#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */
#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */
#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
@@ -205,22 +212,22 @@ typedef struct
#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */
#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */
-#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */
+#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */
#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */
#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */
#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */
-#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */
+#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */
#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */
#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */
#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */
-#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass erase region 1 */
+#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */
#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */
#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */
#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */
-#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */
+#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */
#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */
#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */
#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
@@ -322,12 +329,12 @@ typedef struct
#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */
#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */
-#define MSC_IF_ICACHERR (0x1UL << 5) /**< iCache RAM Parity Error Flag */
+#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */
#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */
#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */
#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */
-#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash controller write buffer overflow */
+#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */
#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */
#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */
#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
@@ -476,13 +483,13 @@ typedef struct
#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */
-#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */
+#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */
-#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */
+#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */
@@ -526,13 +533,13 @@ typedef struct
#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
-#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */
+#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */
-#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */
+#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */
@@ -573,13 +580,13 @@ typedef struct
#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */
-#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */
+#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */
-#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */
#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */
+#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */
#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */
#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */
#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */
@@ -601,12 +608,12 @@ typedef struct
/* Bit fields for MSC BOOTLOADERCTRL */
#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */
#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */
-#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Enable */
+#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */
#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */
#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */
#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */
#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */
-#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Eanble */
+#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */
#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */
#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */
#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */
@@ -615,7 +622,7 @@ typedef struct
/* Bit fields for MSC AAPUNLOCKCMD */
#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */
#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */
-#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software unlock AAP command */
+#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */
#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */
#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */
#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */
@@ -636,29 +643,19 @@ typedef struct
#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */
/* Bit fields for MSC RAMCTRL */
-#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */
-#define _MSC_RAMCTRL_MASK 0x00090101UL /**< Mask for MSC_RAMCTRL */
-#define MSC_RAMCTRL_RAMCACHEEN (0x1UL << 0) /**< RAM CACHE Enable */
-#define _MSC_RAMCTRL_RAMCACHEEN_SHIFT 0 /**< Shift value for MSC_RAMCACHEEN */
-#define _MSC_RAMCTRL_RAMCACHEEN_MASK 0x1UL /**< Bit mask for MSC_RAMCACHEEN */
-#define _MSC_RAMCTRL_RAMCACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */
-#define MSC_RAMCTRL_RAMCACHEEN_DEFAULT (_MSC_RAMCTRL_RAMCACHEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMCTRL */
-#define MSC_RAMCTRL_RAM1CACHEEN (0x1UL << 8) /**< RAM1 CACHE Enable */
-#define _MSC_RAMCTRL_RAM1CACHEEN_SHIFT 8 /**< Shift value for MSC_RAM1CACHEEN */
-#define _MSC_RAMCTRL_RAM1CACHEEN_MASK 0x100UL /**< Bit mask for MSC_RAM1CACHEEN */
-#define _MSC_RAMCTRL_RAM1CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */
-#define MSC_RAMCTRL_RAM1CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM1CACHEEN_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_RAMCTRL */
-#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */
-#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */
-#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */
-#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */
-#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */
-#define MSC_RAMCTRL_RAMSEQCACHEEN (0x1UL << 19) /**< RAMSEQ CACHE Enable */
-#define _MSC_RAMCTRL_RAMSEQCACHEEN_SHIFT 19 /**< Shift value for MSC_RAMSEQCACHEEN */
-#define _MSC_RAMCTRL_RAMSEQCACHEEN_MASK 0x80000UL /**< Bit mask for MSC_RAMSEQCACHEEN */
-#define _MSC_RAMCTRL_RAMSEQCACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */
-#define MSC_RAMCTRL_RAMSEQCACHEEN_DEFAULT (_MSC_RAMCTRL_RAMSEQCACHEEN_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_RAMCTRL */
-
+#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */
+#define _MSC_RAMCTRL_MASK 0x00000101UL /**< Mask for MSC_RAMCTRL */
+#define MSC_RAMCTRL_RAMCACHEEN (0x1UL << 0) /**< RAM CACHE Enable */
+#define _MSC_RAMCTRL_RAMCACHEEN_SHIFT 0 /**< Shift value for MSC_RAMCACHEEN */
+#define _MSC_RAMCTRL_RAMCACHEEN_MASK 0x1UL /**< Bit mask for MSC_RAMCACHEEN */
+#define _MSC_RAMCTRL_RAMCACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */
+#define MSC_RAMCTRL_RAMCACHEEN_DEFAULT (_MSC_RAMCTRL_RAMCACHEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMCTRL */
+#define MSC_RAMCTRL_RAM1CACHEEN (0x1UL << 8) /**< RAM1 CACHE Enable */
+#define _MSC_RAMCTRL_RAM1CACHEEN_SHIFT 8 /**< Shift value for MSC_RAM1CACHEEN */
+#define _MSC_RAMCTRL_RAM1CACHEEN_MASK 0x100UL /**< Bit mask for MSC_RAM1CACHEEN */
+#define _MSC_RAMCTRL_RAM1CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */
+#define MSC_RAMCTRL_RAM1CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM1CACHEEN_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_RAMCTRL */
+
+/** @} */
/** @} End of group EFR32FG12P_MSC */
/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_pcnt.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_pcnt.h
similarity index 96%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_pcnt.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_pcnt.h
index 16e6b629..963c4441 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_pcnt.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_pcnt.h
@@ -1,72 +1,79 @@
-/**************************************************************************//**
- * @file efr32fg12p_pcnt.h
+/***************************************************************************//**
+ * @file
* @brief EFR32FG12P_PCNT register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_PCNT
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P_PCNT PCNT
* @{
* @brief EFR32FG12P_PCNT Register Declaration
- *****************************************************************************/
-typedef struct
-{
- __IOM uint32_t CTRL; /**< Control Register */
- __IOM uint32_t CMD; /**< Command Register */
- __IM uint32_t STATUS; /**< Status Register */
- __IM uint32_t CNT; /**< Counter Value Register */
- __IM uint32_t TOP; /**< Top Value Register */
- __IOM uint32_t TOPB; /**< Top Value Buffer Register */
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- uint32_t RESERVED0[1]; /**< Reserved for future use **/
- __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
+ ******************************************************************************/
+/** PCNT Register Declaration */
+typedef struct {
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IM uint32_t CNT; /**< Counter Value Register */
+ __IM uint32_t TOP; /**< Top Value Register */
+ __IOM uint32_t TOPB; /**< Top Value Buffer Register */
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use **/
+ __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
- uint32_t RESERVED1[4]; /**< Reserved for future use **/
- __IOM uint32_t FREEZE; /**< Freeze Register */
- __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
+ uint32_t RESERVED1[4U]; /**< Reserved for future use **/
+ __IOM uint32_t FREEZE; /**< Freeze Register */
+ __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
- uint32_t RESERVED2[7]; /**< Reserved for future use **/
- __IM uint32_t AUXCNT; /**< Auxiliary Counter Value Register */
- __IOM uint32_t INPUT; /**< PCNT Input Register */
- __IOM uint32_t OVSCFG; /**< Oversampling Config Register */
-} PCNT_TypeDef; /** @} */
+ uint32_t RESERVED2[7U]; /**< Reserved for future use **/
+ __IM uint32_t AUXCNT; /**< Auxiliary Counter Value Register */
+ __IOM uint32_t INPUT; /**< PCNT Input Register */
+ __IOM uint32_t OVSCFG; /**< Oversampling Config Register */
+} PCNT_TypeDef; /** @} */
-/**************************************************************************//**
- * @defgroup EFR32FG12P_PCNT_BitFields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_PCNT
* @{
- *****************************************************************************/
+ * @defgroup EFR32FG12P_PCNT_BitFields PCNT Bit Fields
+ * @{
+ ******************************************************************************/
/* Bit fields for PCNT CTRL */
#define _PCNT_CTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_CTRL */
@@ -119,7 +126,7 @@ typedef struct
#define _PCNT_CTRL_HYST_MASK 0x100UL /**< Bit mask for PCNT_HYST */
#define _PCNT_CTRL_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_HYST_DEFAULT (_PCNT_CTRL_HYST_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_CTRL */
-#define PCNT_CTRL_S1CDIR (0x1UL << 9) /**< Count direction determined by S1 */
+#define PCNT_CTRL_S1CDIR (0x1UL << 9) /**< Count Direction Determined By S1 */
#define _PCNT_CTRL_S1CDIR_SHIFT 9 /**< Shift value for PCNT_S1CDIR */
#define _PCNT_CTRL_S1CDIR_MASK 0x200UL /**< Bit mask for PCNT_S1CDIR */
#define _PCNT_CTRL_S1CDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
@@ -198,12 +205,12 @@ typedef struct
#define PCNT_CTRL_TCCCOMP_LTOE (_PCNT_CTRL_TCCCOMP_LTOE << 22) /**< Shifted mode LTOE for PCNT_CTRL */
#define PCNT_CTRL_TCCCOMP_GTOE (_PCNT_CTRL_TCCCOMP_GTOE << 22) /**< Shifted mode GTOE for PCNT_CTRL */
#define PCNT_CTRL_TCCCOMP_RANGE (_PCNT_CTRL_TCCCOMP_RANGE << 22) /**< Shifted mode RANGE for PCNT_CTRL */
-#define PCNT_CTRL_PRSGATEEN (0x1UL << 24) /**< PRS gate enable */
+#define PCNT_CTRL_PRSGATEEN (0x1UL << 24) /**< PRS Gate Enable */
#define _PCNT_CTRL_PRSGATEEN_SHIFT 24 /**< Shift value for PCNT_PRSGATEEN */
#define _PCNT_CTRL_PRSGATEEN_MASK 0x1000000UL /**< Bit mask for PCNT_PRSGATEEN */
#define _PCNT_CTRL_PRSGATEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_PRSGATEEN_DEFAULT (_PCNT_CTRL_PRSGATEEN_DEFAULT << 24) /**< Shifted mode DEFAULT for PCNT_CTRL */
-#define PCNT_CTRL_TCCPRSPOL (0x1UL << 25) /**< TCC PRS polarity select */
+#define PCNT_CTRL_TCCPRSPOL (0x1UL << 25) /**< TCC PRS Polarity Select */
#define _PCNT_CTRL_TCCPRSPOL_SHIFT 25 /**< Shift value for PCNT_TCCPRSPOL */
#define _PCNT_CTRL_TCCPRSPOL_MASK 0x2000000UL /**< Bit mask for PCNT_TCCPRSPOL */
#define _PCNT_CTRL_TCCPRSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
@@ -240,7 +247,7 @@ typedef struct
#define PCNT_CTRL_TCCPRSSEL_PRSCH9 (_PCNT_CTRL_TCCPRSSEL_PRSCH9 << 26) /**< Shifted mode PRSCH9 for PCNT_CTRL */
#define PCNT_CTRL_TCCPRSSEL_PRSCH10 (_PCNT_CTRL_TCCPRSSEL_PRSCH10 << 26) /**< Shifted mode PRSCH10 for PCNT_CTRL */
#define PCNT_CTRL_TCCPRSSEL_PRSCH11 (_PCNT_CTRL_TCCPRSSEL_PRSCH11 << 26) /**< Shifted mode PRSCH11 for PCNT_CTRL */
-#define PCNT_CTRL_TOPBHFSEL (0x1UL << 31) /**< TOPB High frequency value select */
+#define PCNT_CTRL_TOPBHFSEL (0x1UL << 31) /**< TOPB High Frequency Value Select */
#define _PCNT_CTRL_TOPBHFSEL_SHIFT 31 /**< Shift value for PCNT_TOPBHFSEL */
#define _PCNT_CTRL_TOPBHFSEL_MASK 0x80000000UL /**< Bit mask for PCNT_TOPBHFSEL */
#define _PCNT_CTRL_TOPBHFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
@@ -320,7 +327,7 @@ typedef struct
#define _PCNT_IF_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */
#define _PCNT_IF_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
#define PCNT_IF_AUXOF_DEFAULT (_PCNT_IF_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IF */
-#define PCNT_IF_TCC (0x1UL << 4) /**< Triggered compare Interrupt Read Flag */
+#define PCNT_IF_TCC (0x1UL << 4) /**< Triggered Compare Interrupt Read Flag */
#define _PCNT_IF_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */
#define _PCNT_IF_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */
#define _PCNT_IF_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
@@ -701,6 +708,6 @@ typedef struct
#define _PCNT_OVSCFG_FLUTTERRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCFG */
#define PCNT_OVSCFG_FLUTTERRM_DEFAULT (_PCNT_OVSCFG_FLUTTERRM_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_OVSCFG */
+/** @} */
/** @} End of group EFR32FG12P_PCNT */
/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_prs.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_prs.h
similarity index 100%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_prs.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_prs.h
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_prs_ch.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_prs_ch.h
similarity index 100%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_prs_ch.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_prs_ch.h
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_prs_signals.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_prs_signals.h
similarity index 100%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_prs_signals.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_prs_signals.h
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_rmu.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_rmu.h
similarity index 92%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_rmu.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_rmu.h
index 47ede088..979f7d68 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_rmu.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_rmu.h
@@ -1,45 +1,50 @@
-/**************************************************************************//**
- * @file efr32fg12p_rmu.h
+/***************************************************************************//**
+ * @file
* @brief EFR32FG12P_RMU register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_RMU
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P_RMU RMU
* @{
* @brief EFR32FG12P_RMU Register Declaration
- *****************************************************************************/
-typedef struct
-{
+ ******************************************************************************/
+/** RMU Register Declaration */
+typedef struct {
__IOM uint32_t CTRL; /**< Control Register */
__IM uint32_t RSTCAUSE; /**< Reset Cause Register */
__IOM uint32_t CMD; /**< Command Register */
@@ -47,10 +52,12 @@ typedef struct
__IOM uint32_t LOCK; /**< Configuration Lock Register */
} RMU_TypeDef; /** @} */
-/**************************************************************************//**
- * @defgroup EFR32FG12P_RMU_BitFields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_RMU
+ * @{
+ * @defgroup EFR32FG12P_RMU_BitFields RMU Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for RMU CTRL */
#define _RMU_CTRL_RESETVALUE 0x00004204UL /**< Default value for RMU_CTRL */
@@ -111,7 +118,7 @@ typedef struct
/* Bit fields for RMU RSTCAUSE */
#define _RMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for RMU_RSTCAUSE */
#define _RMU_RSTCAUSE_MASK 0x00010F1DUL /**< Mask for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_PORST (0x1UL << 0) /**< Power On Reset */
+#define RMU_RSTCAUSE_PORST (0x1UL << 0) /**< Power on Reset */
#define _RMU_RSTCAUSE_PORST_SHIFT 0 /**< Shift value for RMU_PORST */
#define _RMU_RSTCAUSE_PORST_MASK 0x1UL /**< Bit mask for RMU_PORST */
#define _RMU_RSTCAUSE_PORST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
@@ -176,16 +183,16 @@ typedef struct
#define _RMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RMU_LOCKKEY */
#define _RMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RMU_LOCKKEY */
#define _RMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_LOCK */
-#define _RMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RMU_LOCK */
#define _RMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RMU_LOCK */
+#define _RMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RMU_LOCK */
#define _RMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RMU_LOCK */
#define _RMU_LOCK_LOCKKEY_UNLOCK 0x0000E084UL /**< Mode UNLOCK for RMU_LOCK */
#define RMU_LOCK_LOCKKEY_DEFAULT (_RMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_LOCK */
-#define RMU_LOCK_LOCKKEY_LOCK (_RMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RMU_LOCK */
#define RMU_LOCK_LOCKKEY_UNLOCKED (_RMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RMU_LOCK */
+#define RMU_LOCK_LOCKKEY_LOCK (_RMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RMU_LOCK */
#define RMU_LOCK_LOCKKEY_LOCKED (_RMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RMU_LOCK */
#define RMU_LOCK_LOCKKEY_UNLOCK (_RMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RMU_LOCK */
+/** @} */
/** @} End of group EFR32FG12P_RMU */
/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_romtable.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_romtable.h
similarity index 68%
rename from mcu/efr/common/vendor/efr32fg13/efr32fg13p_romtable.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_romtable.h
index ff1fc9fe..24c45806 100644
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_romtable.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_romtable.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efr32fg13p_romtable.h
- * @brief EFR32FG13P_ROMTABLE register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+/***************************************************************************//**
+ * @file
+ * @brief EFR32FG12P_ROMTABLE register and bit field definitions
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#if defined(__ICCARM__)
#pragma system_include /* Treat file as system include file. */
@@ -36,15 +34,15 @@
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P_ROMTABLE ROM Table, Chip Revision Information
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P_ROMTABLE ROM Table, Chip Revision Information
* @{
* @brief Chip Information, Revision numbers
- *****************************************************************************/
+ ******************************************************************************/
/** ROMTABLE Register Declaration */
typedef struct {
__IM uint32_t PID4; /**< JEP_106_BANK */
@@ -58,13 +56,13 @@ typedef struct {
__IM uint32_t CID0; /**< Unused */
} ROMTABLE_TypeDef; /** @} */
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_ROMTABLE
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_ROMTABLE
* @{
- * @defgroup EFR32FG13P_ROMTABLE_BitFields ROM Table Bit Field definitions
+ * @defgroup EFR32FG12P_ROMTABLE_BitFields ROM Table Bit Field definitions
* @{
- *****************************************************************************/
-/* Bit fields for EFR32FG13P_ROMTABLE */
+ ******************************************************************************/
+/* Bit fields for EFR32FG12P_ROMTABLE */
#define _ROMTABLE_PID0_FAMILYLSB_MASK 0x000000C0UL /**< Least Significant Bits [1:0] of CHIP FAMILY, mask */
#define _ROMTABLE_PID0_FAMILYLSB_SHIFT 6 /**< Least Significant Bits [1:0] of CHIP FAMILY, shift */
#define _ROMTABLE_PID0_REVMAJOR_MASK 0x0000003FUL /**< CHIP MAJOR Revison, mask */
@@ -77,5 +75,5 @@ typedef struct {
#define _ROMTABLE_PID3_REVMINORLSB_SHIFT 4 /**< Least Significant Bits [3:0] of CHIP MINOR revision, shift */
/** @} */
-/** @} End of group EFR32FG13P_ROMTABLE */
+/** @} End of group EFR32FG12P_ROMTABLE */
/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_rtcc.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_rtcc.h
similarity index 95%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_rtcc.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_rtcc.h
index 1ea224a1..94858e23 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_rtcc.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_rtcc.h
@@ -1,72 +1,79 @@
-/**************************************************************************//**
- * @file efr32fg12p_rtcc.h
+/***************************************************************************//**
+ * @file
* @brief EFR32FG12P_RTCC register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_RTCC
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P_RTCC RTCC
* @{
* @brief EFR32FG12P_RTCC Register Declaration
- *****************************************************************************/
-typedef struct
-{
- __IOM uint32_t CTRL; /**< Control Register */
- __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */
- __IOM uint32_t CNT; /**< Counter Value Register */
- __IM uint32_t COMBCNT; /**< Combined Pre-Counter and Counter Value Register */
- __IOM uint32_t TIME; /**< Time of day register */
- __IOM uint32_t DATE; /**< Date register */
- __IM uint32_t IF; /**< RTCC Interrupt Flags */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- __IM uint32_t STATUS; /**< Status register */
- __IOM uint32_t CMD; /**< Command Register */
- __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
- __IOM uint32_t POWERDOWN; /**< Retention RAM power-down register */
- __IOM uint32_t LOCK; /**< Configuration Lock Register */
- __IOM uint32_t EM4WUEN; /**< Wake Up Enable */
+ ******************************************************************************/
+/** RTCC Register Declaration */
+typedef struct {
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */
+ __IOM uint32_t CNT; /**< Counter Value Register */
+ __IM uint32_t COMBCNT; /**< Combined Pre-Counter and Counter Value Register */
+ __IOM uint32_t TIME; /**< Time of Day Register */
+ __IOM uint32_t DATE; /**< Date Register */
+ __IM uint32_t IF; /**< RTCC Interrupt Flags */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
+ __IOM uint32_t POWERDOWN; /**< Retention RAM Power-down Register */
+ __IOM uint32_t LOCK; /**< Configuration Lock Register */
+ __IOM uint32_t EM4WUEN; /**< Wake Up Enable */
- RTCC_CC_TypeDef CC[3]; /**< Capture/Compare Channel */
+ RTCC_CC_TypeDef CC[3U]; /**< Capture/Compare Channel */
- uint32_t RESERVED0[37]; /**< Reserved registers */
- RTCC_RET_TypeDef RET[32]; /**< RetentionReg */
-} RTCC_TypeDef; /** @} */
+ uint32_t RESERVED0[37U]; /**< Reserved registers */
+ RTCC_RET_TypeDef RET[32U]; /**< RetentionReg */
+} RTCC_TypeDef; /** @} */
-/**************************************************************************//**
- * @defgroup EFR32FG12P_RTCC_BitFields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_RTCC
+ * @{
+ * @defgroup EFR32FG12P_RTCC_BitFields RTCC Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for RTCC CTRL */
#define _RTCC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CTRL */
@@ -81,12 +88,12 @@ typedef struct
#define _RTCC_CTRL_DEBUGRUN_MASK 0x4UL /**< Bit mask for RTCC_DEBUGRUN */
#define _RTCC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
#define RTCC_CTRL_DEBUGRUN_DEFAULT (_RTCC_CTRL_DEBUGRUN_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CTRL */
-#define RTCC_CTRL_PRECCV0TOP (0x1UL << 4) /**< Pre-counter CCV0 top value enable. */
+#define RTCC_CTRL_PRECCV0TOP (0x1UL << 4) /**< Pre-counter CCV0 Top Value Enable */
#define _RTCC_CTRL_PRECCV0TOP_SHIFT 4 /**< Shift value for RTCC_PRECCV0TOP */
#define _RTCC_CTRL_PRECCV0TOP_MASK 0x10UL /**< Bit mask for RTCC_PRECCV0TOP */
#define _RTCC_CTRL_PRECCV0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
#define RTCC_CTRL_PRECCV0TOP_DEFAULT (_RTCC_CTRL_PRECCV0TOP_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CTRL */
-#define RTCC_CTRL_CCV1TOP (0x1UL << 5) /**< CCV1 top value enable */
+#define RTCC_CTRL_CCV1TOP (0x1UL << 5) /**< CCV1 Top Value Enable */
#define _RTCC_CTRL_CCV1TOP_SHIFT 5 /**< Shift value for RTCC_CCV1TOP */
#define _RTCC_CTRL_CCV1TOP_MASK 0x20UL /**< Bit mask for RTCC_CCV1TOP */
#define _RTCC_CTRL_CCV1TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
@@ -127,7 +134,7 @@ typedef struct
#define RTCC_CTRL_CNTPRESC_DIV8192 (_RTCC_CTRL_CNTPRESC_DIV8192 << 8) /**< Shifted mode DIV8192 for RTCC_CTRL */
#define RTCC_CTRL_CNTPRESC_DIV16384 (_RTCC_CTRL_CNTPRESC_DIV16384 << 8) /**< Shifted mode DIV16384 for RTCC_CTRL */
#define RTCC_CTRL_CNTPRESC_DIV32768 (_RTCC_CTRL_CNTPRESC_DIV32768 << 8) /**< Shifted mode DIV32768 for RTCC_CTRL */
-#define RTCC_CTRL_CNTTICK (0x1UL << 12) /**< Counter prescaler mode. */
+#define RTCC_CTRL_CNTTICK (0x1UL << 12) /**< Counter Prescaler Mode */
#define _RTCC_CTRL_CNTTICK_SHIFT 12 /**< Shift value for RTCC_CNTTICK */
#define _RTCC_CTRL_CNTTICK_MASK 0x1000UL /**< Bit mask for RTCC_CNTTICK */
#define _RTCC_CTRL_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
@@ -136,12 +143,12 @@ typedef struct
#define RTCC_CTRL_CNTTICK_DEFAULT (_RTCC_CTRL_CNTTICK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CTRL */
#define RTCC_CTRL_CNTTICK_PRESC (_RTCC_CTRL_CNTTICK_PRESC << 12) /**< Shifted mode PRESC for RTCC_CTRL */
#define RTCC_CTRL_CNTTICK_CCV0MATCH (_RTCC_CTRL_CNTTICK_CCV0MATCH << 12) /**< Shifted mode CCV0MATCH for RTCC_CTRL */
-#define RTCC_CTRL_OSCFDETEN (0x1UL << 15) /**< Oscillator failure detection enable */
+#define RTCC_CTRL_OSCFDETEN (0x1UL << 15) /**< Oscillator Failure Detection Enable */
#define _RTCC_CTRL_OSCFDETEN_SHIFT 15 /**< Shift value for RTCC_OSCFDETEN */
#define _RTCC_CTRL_OSCFDETEN_MASK 0x8000UL /**< Bit mask for RTCC_OSCFDETEN */
#define _RTCC_CTRL_OSCFDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
#define RTCC_CTRL_OSCFDETEN_DEFAULT (_RTCC_CTRL_OSCFDETEN_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_CTRL */
-#define RTCC_CTRL_CNTMODE (0x1UL << 16) /**< Main counter mode */
+#define RTCC_CTRL_CNTMODE (0x1UL << 16) /**< Main Counter Mode */
#define _RTCC_CTRL_CNTMODE_SHIFT 16 /**< Shift value for RTCC_CNTMODE */
#define _RTCC_CTRL_CNTMODE_MASK 0x10000UL /**< Bit mask for RTCC_CNTMODE */
#define _RTCC_CTRL_CNTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
@@ -150,7 +157,7 @@ typedef struct
#define RTCC_CTRL_CNTMODE_DEFAULT (_RTCC_CTRL_CNTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_CTRL */
#define RTCC_CTRL_CNTMODE_NORMAL (_RTCC_CTRL_CNTMODE_NORMAL << 16) /**< Shifted mode NORMAL for RTCC_CTRL */
#define RTCC_CTRL_CNTMODE_CALENDAR (_RTCC_CTRL_CNTMODE_CALENDAR << 16) /**< Shifted mode CALENDAR for RTCC_CTRL */
-#define RTCC_CTRL_LYEARCORRDIS (0x1UL << 17) /**< Leap year correction disabled. */
+#define RTCC_CTRL_LYEARCORRDIS (0x1UL << 17) /**< Leap Year Correction Disabled */
#define _RTCC_CTRL_LYEARCORRDIS_SHIFT 17 /**< Shift value for RTCC_LYEARCORRDIS */
#define _RTCC_CTRL_LYEARCORRDIS_MASK 0x20000UL /**< Bit mask for RTCC_LYEARCORRDIS */
#define _RTCC_CTRL_LYEARCORRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
@@ -227,7 +234,7 @@ typedef struct
#define _RTCC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for RTCC_MONTHU */
#define _RTCC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
#define RTCC_DATE_MONTHU_DEFAULT (_RTCC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_DATE */
-#define RTCC_DATE_MONTHT (0x1UL << 12) /**< Month, tens. */
+#define RTCC_DATE_MONTHT (0x1UL << 12) /**< Month, Tens */
#define _RTCC_DATE_MONTHT_SHIFT 12 /**< Shift value for RTCC_MONTHT */
#define _RTCC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for RTCC_MONTHT */
#define _RTCC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
@@ -268,37 +275,37 @@ typedef struct
#define _RTCC_IF_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */
#define _RTCC_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
#define RTCC_IF_CC2_DEFAULT (_RTCC_IF_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IF */
-#define RTCC_IF_OSCFAIL (0x1UL << 4) /**< Oscillator failure Interrupt Flag */
+#define RTCC_IF_OSCFAIL (0x1UL << 4) /**< Oscillator Failure Interrupt Flag */
#define _RTCC_IF_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */
#define _RTCC_IF_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */
#define _RTCC_IF_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
#define RTCC_IF_OSCFAIL_DEFAULT (_RTCC_IF_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IF */
-#define RTCC_IF_CNTTICK (0x1UL << 5) /**< Main counter tick */
+#define RTCC_IF_CNTTICK (0x1UL << 5) /**< Main Counter Tick */
#define _RTCC_IF_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */
#define _RTCC_IF_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */
#define _RTCC_IF_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
#define RTCC_IF_CNTTICK_DEFAULT (_RTCC_IF_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IF */
-#define RTCC_IF_MINTICK (0x1UL << 6) /**< Minute tick */
+#define RTCC_IF_MINTICK (0x1UL << 6) /**< Minute Tick */
#define _RTCC_IF_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */
#define _RTCC_IF_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */
#define _RTCC_IF_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
#define RTCC_IF_MINTICK_DEFAULT (_RTCC_IF_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IF */
-#define RTCC_IF_HOURTICK (0x1UL << 7) /**< Hour tick */
+#define RTCC_IF_HOURTICK (0x1UL << 7) /**< Hour Tick */
#define _RTCC_IF_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */
#define _RTCC_IF_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */
#define _RTCC_IF_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
#define RTCC_IF_HOURTICK_DEFAULT (_RTCC_IF_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IF */
-#define RTCC_IF_DAYTICK (0x1UL << 8) /**< Day tick */
+#define RTCC_IF_DAYTICK (0x1UL << 8) /**< Day Tick */
#define _RTCC_IF_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */
#define _RTCC_IF_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */
#define _RTCC_IF_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
#define RTCC_IF_DAYTICK_DEFAULT (_RTCC_IF_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IF */
-#define RTCC_IF_DAYOWOF (0x1UL << 9) /**< Day of week overflow */
+#define RTCC_IF_DAYOWOF (0x1UL << 9) /**< Day of Week Overflow */
#define _RTCC_IF_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */
#define _RTCC_IF_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */
#define _RTCC_IF_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
#define RTCC_IF_DAYOWOF_DEFAULT (_RTCC_IF_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IF */
-#define RTCC_IF_MONTHTICK (0x1UL << 10) /**< Month tick */
+#define RTCC_IF_MONTHTICK (0x1UL << 10) /**< Month Tick */
#define _RTCC_IF_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */
#define _RTCC_IF_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */
#define _RTCC_IF_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
@@ -488,7 +495,7 @@ typedef struct
/* Bit fields for RTCC CMD */
#define _RTCC_CMD_RESETVALUE 0x00000000UL /**< Default value for RTCC_CMD */
#define _RTCC_CMD_MASK 0x00000001UL /**< Mask for RTCC_CMD */
-#define RTCC_CMD_CLRSTATUS (0x1UL << 0) /**< Clear RTCC_STATUS register. */
+#define RTCC_CMD_CLRSTATUS (0x1UL << 0) /**< Clear RTCC_STATUS Register */
#define _RTCC_CMD_CLRSTATUS_SHIFT 0 /**< Shift value for RTCC_CLRSTATUS */
#define _RTCC_CMD_CLRSTATUS_MASK 0x1UL /**< Bit mask for RTCC_CLRSTATUS */
#define _RTCC_CMD_CLRSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CMD */
@@ -506,7 +513,7 @@ typedef struct
/* Bit fields for RTCC POWERDOWN */
#define _RTCC_POWERDOWN_RESETVALUE 0x00000000UL /**< Default value for RTCC_POWERDOWN */
#define _RTCC_POWERDOWN_MASK 0x00000001UL /**< Mask for RTCC_POWERDOWN */
-#define RTCC_POWERDOWN_RAM (0x1UL << 0) /**< Retention RAM power-down */
+#define RTCC_POWERDOWN_RAM (0x1UL << 0) /**< Retention RAM Power-down */
#define _RTCC_POWERDOWN_RAM_SHIFT 0 /**< Shift value for RTCC_RAM */
#define _RTCC_POWERDOWN_RAM_MASK 0x1UL /**< Bit mask for RTCC_RAM */
#define _RTCC_POWERDOWN_RAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_POWERDOWN */
@@ -518,20 +525,20 @@ typedef struct
#define _RTCC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RTCC_LOCKKEY */
#define _RTCC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RTCC_LOCKKEY */
#define _RTCC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_LOCK */
-#define _RTCC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RTCC_LOCK */
#define _RTCC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RTCC_LOCK */
+#define _RTCC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RTCC_LOCK */
#define _RTCC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RTCC_LOCK */
#define _RTCC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for RTCC_LOCK */
#define RTCC_LOCK_LOCKKEY_DEFAULT (_RTCC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_LOCK */
-#define RTCC_LOCK_LOCKKEY_LOCK (_RTCC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RTCC_LOCK */
#define RTCC_LOCK_LOCKKEY_UNLOCKED (_RTCC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RTCC_LOCK */
+#define RTCC_LOCK_LOCKKEY_LOCK (_RTCC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RTCC_LOCK */
#define RTCC_LOCK_LOCKKEY_LOCKED (_RTCC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RTCC_LOCK */
#define RTCC_LOCK_LOCKKEY_UNLOCK (_RTCC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RTCC_LOCK */
/* Bit fields for RTCC EM4WUEN */
#define _RTCC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_EM4WUEN */
#define _RTCC_EM4WUEN_MASK 0x00000001UL /**< Mask for RTCC_EM4WUEN */
-#define RTCC_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up enable */
+#define RTCC_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up Enable */
#define _RTCC_EM4WUEN_EM4WU_SHIFT 0 /**< Shift value for RTCC_EM4WU */
#define _RTCC_EM4WUEN_EM4WU_MASK 0x1UL /**< Bit mask for RTCC_EM4WU */
#define _RTCC_EM4WUEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_EM4WUEN */
@@ -602,7 +609,7 @@ typedef struct
#define RTCC_CC_CTRL_PRSSEL_PRSCH9 (_RTCC_CC_CTRL_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_PRSSEL_PRSCH10 (_RTCC_CC_CTRL_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_PRSSEL_PRSCH11 (_RTCC_CC_CTRL_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_COMPBASE (0x1UL << 11) /**< Capture compare channel comparison base. */
+#define RTCC_CC_CTRL_COMPBASE (0x1UL << 11) /**< Capture Compare Channel Comparison Base */
#define _RTCC_CC_CTRL_COMPBASE_SHIFT 11 /**< Shift value for CC_COMPBASE */
#define _RTCC_CC_CTRL_COMPBASE_MASK 0x800UL /**< Bit mask for CC_COMPBASE */
#define _RTCC_CC_CTRL_COMPBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
@@ -615,7 +622,7 @@ typedef struct
#define _RTCC_CC_CTRL_COMPMASK_MASK 0x1F000UL /**< Bit mask for CC_COMPMASK */
#define _RTCC_CC_CTRL_COMPMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_COMPMASK_DEFAULT (_RTCC_CC_CTRL_COMPMASK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_DAYCC (0x1UL << 17) /**< Day Capture/Compare selection */
+#define RTCC_CC_CTRL_DAYCC (0x1UL << 17) /**< Day Capture/Compare Selection */
#define _RTCC_CC_CTRL_DAYCC_SHIFT 17 /**< Shift value for CC_DAYCC */
#define _RTCC_CC_CTRL_DAYCC_MASK 0x20000UL /**< Bit mask for CC_DAYCC */
#define _RTCC_CC_CTRL_DAYCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
@@ -676,7 +683,7 @@ typedef struct
#define _RTCC_CC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for CC_MONTHU */
#define _RTCC_CC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */
#define RTCC_CC_DATE_MONTHU_DEFAULT (_RTCC_CC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CC_DATE */
-#define RTCC_CC_DATE_MONTHT (0x1UL << 12) /**< Month, tens. */
+#define RTCC_CC_DATE_MONTHT (0x1UL << 12) /**< Month, Tens */
#define _RTCC_CC_DATE_MONTHT_SHIFT 12 /**< Shift value for CC_MONTHT */
#define _RTCC_CC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for CC_MONTHT */
#define _RTCC_CC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */
@@ -690,6 +697,6 @@ typedef struct
#define _RTCC_RET_REG_REG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_RET_REG */
#define RTCC_RET_REG_REG_DEFAULT (_RTCC_RET_REG_REG_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_RET_REG */
+/** @} */
/** @} End of group EFR32FG12P_RTCC */
/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_rtcc_cc.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_rtcc_cc.h
similarity index 55%
rename from mcu/efr/common/vendor/efr32fg13/efr32fg13p_rtcc_cc.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_rtcc_cc.h
index 1792a31a..00a4aad8 100644
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_rtcc_cc.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_rtcc_cc.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efr32fg13p_rtcc_cc.h
- * @brief EFR32FG13P_RTCC_CC register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+/***************************************************************************//**
+ * @file
+ * @brief EFR32FG12P_RTCC_CC register and bit field definitions
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#if defined(__ICCARM__)
#pragma system_include /* Treat file as system include file. */
@@ -36,14 +34,14 @@
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @brief RTCC_CC RTCC CC Register
- * @ingroup EFR32FG13P_RTCC
- *****************************************************************************/
+ * @ingroup EFR32FG12P_RTCC
+ ******************************************************************************/
typedef struct {
__IOM uint32_t CTRL; /**< CC Channel Control Register */
__IOM uint32_t CCV; /**< Capture/Compare Value Register */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_rtcc_ret.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_rtcc_ret.h
similarity index 52%
rename from mcu/efr/common/vendor/efr32fg13/efr32fg13p_rtcc_ret.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_rtcc_ret.h
index 1c12371d..f7634633 100644
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_rtcc_ret.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_rtcc_ret.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efr32fg13p_rtcc_ret.h
- * @brief EFR32FG13P_RTCC_RET register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+/***************************************************************************//**
+ * @file
+ * @brief EFR32FG12P_RTCC_RET register and bit field definitions
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#if defined(__ICCARM__)
#pragma system_include /* Treat file as system include file. */
@@ -36,14 +34,14 @@
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @brief RTCC_RET RTCC RET Register
- * @ingroup EFR32FG13P_RTCC
- *****************************************************************************/
+ * @ingroup EFR32FG12P_RTCC
+ ******************************************************************************/
typedef struct {
__IOM uint32_t REG; /**< Retention Register */
} RTCC_RET_TypeDef;
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_smu.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_smu.h
similarity index 94%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_smu.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_smu.h
index 60d674c8..b1597d05 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_smu.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_smu.h
@@ -1,65 +1,72 @@
-/**************************************************************************//**
- * @file efr32fg12p_smu.h
+/***************************************************************************//**
+ * @file
* @brief EFR32FG12P_SMU register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_SMU
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P_SMU SMU
* @{
* @brief EFR32FG12P_SMU Register Declaration
- *****************************************************************************/
-typedef struct
-{
- uint32_t RESERVED0[3]; /**< Reserved for future use **/
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ ******************************************************************************/
+/** SMU Register Declaration */
+typedef struct {
+ uint32_t RESERVED0[3U]; /**< Reserved for future use **/
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
- uint32_t RESERVED1[9]; /**< Reserved for future use **/
- __IOM uint32_t PPUCTRL; /**< PPU Control Register */
- uint32_t RESERVED2[3]; /**< Reserved for future use **/
- __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */
- __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */
+ uint32_t RESERVED1[9U]; /**< Reserved for future use **/
+ __IOM uint32_t PPUCTRL; /**< PPU Control Register */
+ uint32_t RESERVED2[3U]; /**< Reserved for future use **/
+ __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */
+ __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */
- uint32_t RESERVED3[14]; /**< Reserved for future use **/
- __IM uint32_t PPUFS; /**< PPU Fault Status */
-} SMU_TypeDef; /** @} */
+ uint32_t RESERVED3[14U]; /**< Reserved for future use **/
+ __IM uint32_t PPUFS; /**< PPU Fault Status */
+} SMU_TypeDef; /** @} */
-/**************************************************************************//**
- * @defgroup EFR32FG12P_SMU_BitFields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_SMU
* @{
- *****************************************************************************/
+ * @defgroup EFR32FG12P_SMU_BitFields SMU Bit Fields
+ * @{
+ ******************************************************************************/
/* Bit fields for SMU IF */
#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */
@@ -129,7 +136,7 @@ typedef struct
#define _SMU_PPUPATD0_CMU_MASK 0x20UL /**< Bit mask for SMU_CMU */
#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 7) /**< CryoTimer access control bit */
+#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 7) /**< CRYOTIMER access control bit */
#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 7 /**< Shift value for SMU_CRYOTIMER */
#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x80UL /**< Bit mask for SMU_CRYOTIMER */
#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
@@ -395,6 +402,6 @@ typedef struct
#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */
+/** @} */
/** @} End of group EFR32FG12P_SMU */
/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_timer.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_timer.h
similarity index 98%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_timer.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_timer.h
index 105d9a72..6ba8cfbb 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_timer.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_timer.h
@@ -1,78 +1,85 @@
-/**************************************************************************//**
- * @file efr32fg12p_timer.h
+/***************************************************************************//**
+ * @file
* @brief EFR32FG12P_TIMER register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_TIMER
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P_TIMER TIMER
* @{
* @brief EFR32FG12P_TIMER Register Declaration
- *****************************************************************************/
-typedef struct
-{
- __IOM uint32_t CTRL; /**< Control Register */
- __IOM uint32_t CMD; /**< Command Register */
- __IM uint32_t STATUS; /**< Status Register */
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- __IOM uint32_t TOP; /**< Counter Top Value Register */
- __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */
- __IOM uint32_t CNT; /**< Counter Value Register */
- uint32_t RESERVED0[1]; /**< Reserved for future use **/
- __IOM uint32_t LOCK; /**< TIMER Configuration Lock Register */
- __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
- __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
- uint32_t RESERVED1[1]; /**< Reserved for future use **/
- __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */
+ ******************************************************************************/
+/** TIMER Register Declaration */
+typedef struct {
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IOM uint32_t TOP; /**< Counter Top Value Register */
+ __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */
+ __IOM uint32_t CNT; /**< Counter Value Register */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use **/
+ __IOM uint32_t LOCK; /**< TIMER Configuration Lock Register */
+ __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
+ __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
+ uint32_t RESERVED1[1U]; /**< Reserved for future use **/
+ __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */
- uint32_t RESERVED2[8]; /**< Reserved registers */
- TIMER_CC_TypeDef CC[4]; /**< Compare/Capture Channel */
+ uint32_t RESERVED2[8U]; /**< Reserved registers */
+ TIMER_CC_TypeDef CC[4U]; /**< Compare/Capture Channel */
- __IOM uint32_t DTCTRL; /**< DTI Control Register */
- __IOM uint32_t DTTIME; /**< DTI Time Control Register */
- __IOM uint32_t DTFC; /**< DTI Fault Configuration Register */
- __IOM uint32_t DTOGEN; /**< DTI Output Generation Enable Register */
- __IM uint32_t DTFAULT; /**< DTI Fault Register */
- __IOM uint32_t DTFAULTC; /**< DTI Fault Clear Register */
- __IOM uint32_t DTLOCK; /**< DTI Configuration Lock Register */
-} TIMER_TypeDef; /** @} */
+ __IOM uint32_t DTCTRL; /**< DTI Control Register */
+ __IOM uint32_t DTTIME; /**< DTI Time Control Register */
+ __IOM uint32_t DTFC; /**< DTI Fault Configuration Register */
+ __IOM uint32_t DTOGEN; /**< DTI Output Generation Enable Register */
+ __IM uint32_t DTFAULT; /**< DTI Fault Register */
+ __IOM uint32_t DTFAULTC; /**< DTI Fault Clear Register */
+ __IOM uint32_t DTLOCK; /**< DTI Configuration Lock Register */
+} TIMER_TypeDef; /** @} */
-/**************************************************************************//**
- * @defgroup EFR32FG12P_TIMER_BitFields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_TIMER
+ * @{
+ * @defgroup EFR32FG12P_TIMER_BitFields TIMER Bit Fields
* @{
- *****************************************************************************/
+ ******************************************************************************/
/* Bit fields for TIMER CTRL */
#define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */
@@ -188,7 +195,7 @@ typedef struct
#define _TIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */
#define _TIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
#define TIMER_CTRL_ATI_DEFAULT (_TIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_CTRL */
-#define TIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */
+#define TIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */
#define _TIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */
#define _TIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */
#define _TIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
@@ -573,13 +580,13 @@ typedef struct
#define _TIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */
#define _TIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */
#define _TIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_LOCK */
-#define _TIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_LOCK */
#define _TIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_LOCK */
+#define _TIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_LOCK */
#define _TIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_LOCK */
#define _TIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_LOCK */
#define TIMER_LOCK_TIMERLOCKKEY_DEFAULT (_TIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_LOCK */
-#define TIMER_LOCK_TIMERLOCKKEY_LOCK (_TIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_LOCK */
#define TIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_TIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_LOCK */
+#define TIMER_LOCK_TIMERLOCKKEY_LOCK (_TIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_LOCK */
#define TIMER_LOCK_TIMERLOCKKEY_LOCKED (_TIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_LOCK */
#define TIMER_LOCK_TIMERLOCKKEY_UNLOCK (_TIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_LOCK */
@@ -1293,7 +1300,7 @@ typedef struct
#define _TIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */
#define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
#define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
-#define TIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */
+#define TIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */
#define _TIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */
#define _TIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */
#define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
@@ -1560,16 +1567,16 @@ typedef struct
#define _TIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
#define _TIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
#define _TIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */
-#define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_DTLOCK */
+#define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_DTLOCK */
#define _TIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_DEFAULT (_TIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */
-#define TIMER_DTLOCK_LOCKKEY_LOCK (_TIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_UNLOCKED (_TIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_DTLOCK */
+#define TIMER_DTLOCK_LOCKKEY_LOCK (_TIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_LOCKED (_TIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_DTLOCK */
#define TIMER_DTLOCK_LOCKKEY_UNLOCK (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */
+/** @} */
/** @} End of group EFR32FG12P_TIMER */
/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_timer_cc.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_timer_cc.h
similarity index 55%
rename from mcu/efr/common/vendor/efr32fg13/efr32fg13p_timer_cc.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_timer_cc.h
index 3bb75d0f..5b4a099d 100644
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_timer_cc.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_timer_cc.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efr32fg13p_timer_cc.h
- * @brief EFR32FG13P_TIMER_CC register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+/***************************************************************************//**
+ * @file
+ * @brief EFR32FG12P_TIMER_CC register and bit field definitions
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#if defined(__ICCARM__)
#pragma system_include /* Treat file as system include file. */
@@ -36,14 +34,14 @@
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @brief TIMER_CC TIMER CC Register
- * @ingroup EFR32FG13P_TIMER
- *****************************************************************************/
+ * @ingroup EFR32FG12P_TIMER
+ ******************************************************************************/
typedef struct {
__IOM uint32_t CTRL; /**< CC Channel Control Register */
__IOM uint32_t CCV; /**< CC Channel Value Register */
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_trng.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_trng.h
similarity index 90%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_trng.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_trng.h
index 1e170b5c..61125ca0 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_trng.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_trng.h
@@ -1,66 +1,73 @@
-/**************************************************************************//**
- * @file efr32fg12p_trng.h
+/***************************************************************************//**
+ * @file
* @brief EFR32FG12P_TRNG register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_TRNG
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P_TRNG TRNG
* @{
* @brief EFR32FG12P_TRNG Register Declaration
- *****************************************************************************/
-typedef struct
-{
- __IOM uint32_t CONTROL; /**< Main Control Register */
- __IM uint32_t FIFOLEVEL; /**< FIFO Level Register */
- uint32_t RESERVED0[1]; /**< Reserved for future use **/
- __IM uint32_t FIFODEPTH; /**< FIFO Depth Register */
- __IOM uint32_t KEY0; /**< Key Register 0 */
- __IOM uint32_t KEY1; /**< Key Register 1 */
- __IOM uint32_t KEY2; /**< Key Register 2 */
- __IOM uint32_t KEY3; /**< Key Register 3 */
- __IOM uint32_t TESTDATA; /**< Test Data Register */
+ ******************************************************************************/
+/** TRNG Register Declaration */
+typedef struct {
+ __IOM uint32_t CONTROL; /**< Main Control Register */
+ __IM uint32_t FIFOLEVEL; /**< FIFO Level Register */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use **/
+ __IM uint32_t FIFODEPTH; /**< FIFO Depth Register */
+ __IOM uint32_t KEY0; /**< Key Register 0 */
+ __IOM uint32_t KEY1; /**< Key Register 1 */
+ __IOM uint32_t KEY2; /**< Key Register 2 */
+ __IOM uint32_t KEY3; /**< Key Register 3 */
+ __IOM uint32_t TESTDATA; /**< Test Data Register */
- uint32_t RESERVED1[3]; /**< Reserved for future use **/
- __IOM uint32_t STATUS; /**< Status Register */
- __IOM uint32_t INITWAITVAL; /**< Initial Wait Counter */
- uint32_t RESERVED2[50]; /**< Reserved for future use **/
- __IM uint32_t FIFO; /**< FIFO Data */
-} TRNG_TypeDef; /** @} */
+ uint32_t RESERVED1[3U]; /**< Reserved for future use **/
+ __IOM uint32_t STATUS; /**< Status Register */
+ __IOM uint32_t INITWAITVAL; /**< Initial Wait Counter */
+ uint32_t RESERVED2[50U]; /**< Reserved for future use **/
+ __IM uint32_t FIFO; /**< FIFO Data */
+} TRNG_TypeDef; /** @} */
-/**************************************************************************//**
- * @defgroup EFR32FG12P_TRNG_BitFields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_TRNG
* @{
- *****************************************************************************/
+ * @defgroup EFR32FG12P_TRNG_BitFields TRNG Bit Fields
+ * @{
+ ******************************************************************************/
/* Bit fields for TRNG CONTROL */
#define _TRNG_CONTROL_RESETVALUE 0x00000000UL /**< Default value for TRNG_CONTROL */
@@ -92,22 +99,22 @@ typedef struct
#define TRNG_CONTROL_CONDBYPASS_DEFAULT (_TRNG_CONTROL_CONDBYPASS_DEFAULT << 3) /**< Shifted mode DEFAULT for TRNG_CONTROL */
#define TRNG_CONTROL_CONDBYPASS_NORMAL (_TRNG_CONTROL_CONDBYPASS_NORMAL << 3) /**< Shifted mode NORMAL for TRNG_CONTROL */
#define TRNG_CONTROL_CONDBYPASS_BYPASS (_TRNG_CONTROL_CONDBYPASS_BYPASS << 3) /**< Shifted mode BYPASS for TRNG_CONTROL */
-#define TRNG_CONTROL_REPCOUNTIEN (0x1UL << 4) /**< Interrupt enable for Repetition Count Test failure */
+#define TRNG_CONTROL_REPCOUNTIEN (0x1UL << 4) /**< Interrupt Enable for Repetition Count Test Failure */
#define _TRNG_CONTROL_REPCOUNTIEN_SHIFT 4 /**< Shift value for TRNG_REPCOUNTIEN */
#define _TRNG_CONTROL_REPCOUNTIEN_MASK 0x10UL /**< Bit mask for TRNG_REPCOUNTIEN */
#define _TRNG_CONTROL_REPCOUNTIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
#define TRNG_CONTROL_REPCOUNTIEN_DEFAULT (_TRNG_CONTROL_REPCOUNTIEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TRNG_CONTROL */
-#define TRNG_CONTROL_APT64IEN (0x1UL << 5) /**< Interrupt enable for Adaptive Proportion Test failure (64-sample window) */
+#define TRNG_CONTROL_APT64IEN (0x1UL << 5) /**< Interrupt Enable for Adaptive Proportion Test Failure (64-sample Window) */
#define _TRNG_CONTROL_APT64IEN_SHIFT 5 /**< Shift value for TRNG_APT64IEN */
#define _TRNG_CONTROL_APT64IEN_MASK 0x20UL /**< Bit mask for TRNG_APT64IEN */
#define _TRNG_CONTROL_APT64IEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
#define TRNG_CONTROL_APT64IEN_DEFAULT (_TRNG_CONTROL_APT64IEN_DEFAULT << 5) /**< Shifted mode DEFAULT for TRNG_CONTROL */
-#define TRNG_CONTROL_APT4096IEN (0x1UL << 6) /**< Interrupt enable for Adaptive Proportion Test failure (4096-sample window) */
+#define TRNG_CONTROL_APT4096IEN (0x1UL << 6) /**< Interrupt Enable for Adaptive Proportion Test Failure (4096-sample Window) */
#define _TRNG_CONTROL_APT4096IEN_SHIFT 6 /**< Shift value for TRNG_APT4096IEN */
#define _TRNG_CONTROL_APT4096IEN_MASK 0x40UL /**< Bit mask for TRNG_APT4096IEN */
#define _TRNG_CONTROL_APT4096IEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
#define TRNG_CONTROL_APT4096IEN_DEFAULT (_TRNG_CONTROL_APT4096IEN_DEFAULT << 6) /**< Shifted mode DEFAULT for TRNG_CONTROL */
-#define TRNG_CONTROL_FULLIEN (0x1UL << 7) /**< Interrupt enable for FIFO full */
+#define TRNG_CONTROL_FULLIEN (0x1UL << 7) /**< Interrupt Enable for FIFO Full */
#define _TRNG_CONTROL_FULLIEN_SHIFT 7 /**< Shift value for TRNG_FULLIEN */
#define _TRNG_CONTROL_FULLIEN_MASK 0x80UL /**< Bit mask for TRNG_FULLIEN */
#define _TRNG_CONTROL_FULLIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
@@ -227,7 +234,7 @@ typedef struct
#define TRNG_STATUS_TESTDATABUSY_DEFAULT (_TRNG_STATUS_TESTDATABUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_STATUS */
#define TRNG_STATUS_TESTDATABUSY_IDLE (_TRNG_STATUS_TESTDATABUSY_IDLE << 0) /**< Shifted mode IDLE for TRNG_STATUS */
#define TRNG_STATUS_TESTDATABUSY_BUSY (_TRNG_STATUS_TESTDATABUSY_BUSY << 0) /**< Shifted mode BUSY for TRNG_STATUS */
-#define TRNG_STATUS_REPCOUNTIF (0x1UL << 4) /**< Repetition Count Test interrupt status */
+#define TRNG_STATUS_REPCOUNTIF (0x1UL << 4) /**< Repetition Count Test Interrupt Status */
#define _TRNG_STATUS_REPCOUNTIF_SHIFT 4 /**< Shift value for TRNG_REPCOUNTIF */
#define _TRNG_STATUS_REPCOUNTIF_MASK 0x10UL /**< Bit mask for TRNG_REPCOUNTIF */
#define _TRNG_STATUS_REPCOUNTIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */
@@ -242,7 +249,7 @@ typedef struct
#define _TRNG_STATUS_APT4096IF_MASK 0x40UL /**< Bit mask for TRNG_APT4096IF */
#define _TRNG_STATUS_APT4096IF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */
#define TRNG_STATUS_APT4096IF_DEFAULT (_TRNG_STATUS_APT4096IF_DEFAULT << 6) /**< Shifted mode DEFAULT for TRNG_STATUS */
-#define TRNG_STATUS_FULLIF (0x1UL << 7) /**< FIFO full interrupt status */
+#define TRNG_STATUS_FULLIF (0x1UL << 7) /**< FIFO Full Interrupt Status */
#define _TRNG_STATUS_FULLIF_SHIFT 7 /**< Shift value for TRNG_FULLIF */
#define _TRNG_STATUS_FULLIF_MASK 0x80UL /**< Bit mask for TRNG_FULLIF */
#define _TRNG_STATUS_FULLIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */
@@ -274,6 +281,6 @@ typedef struct
#define _TRNG_FIFO_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_FIFO */
#define TRNG_FIFO_VALUE_DEFAULT (_TRNG_FIFO_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFO */
+/** @} */
/** @} End of group EFR32FG12P_TRNG */
/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_usart.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_usart.h
similarity index 97%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_usart.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_usart.h
index 5442a3fe..659af874 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_usart.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_usart.h
@@ -1,83 +1,90 @@
-/**************************************************************************//**
- * @file efr32fg12p_usart.h
+/***************************************************************************//**
+ * @file
* @brief EFR32FG12P_USART register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_USART
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P_USART USART
* @{
* @brief EFR32FG12P_USART Register Declaration
- *****************************************************************************/
-typedef struct
-{
- __IOM uint32_t CTRL; /**< Control Register */
- __IOM uint32_t FRAME; /**< USART Frame Format Register */
- __IOM uint32_t TRIGCTRL; /**< USART Trigger Control register */
- __IOM uint32_t CMD; /**< Command Register */
- __IM uint32_t STATUS; /**< USART Status Register */
- __IOM uint32_t CLKDIV; /**< Clock Control Register */
- __IM uint32_t RXDATAX; /**< RX Buffer Data Extended Register */
- __IM uint32_t RXDATA; /**< RX Buffer Data Register */
- __IM uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */
- __IM uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */
- __IM uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */
- __IM uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek Register */
- __IOM uint32_t TXDATAX; /**< TX Buffer Data Extended Register */
- __IOM uint32_t TXDATA; /**< TX Buffer Data Register */
- __IOM uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */
- __IOM uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- __IOM uint32_t IRCTRL; /**< IrDA Control Register */
- uint32_t RESERVED0[1]; /**< Reserved for future use **/
- __IOM uint32_t INPUT; /**< USART Input Register */
- __IOM uint32_t I2SCTRL; /**< I2S Control Register */
- __IOM uint32_t TIMING; /**< Timing Register */
- __IOM uint32_t CTRLX; /**< Control Register Extended */
- __IOM uint32_t TIMECMP0; /**< Used to generate interrupts and various delays */
- __IOM uint32_t TIMECMP1; /**< Used to generate interrupts and various delays */
- __IOM uint32_t TIMECMP2; /**< Used to generate interrupts and various delays */
- __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
- __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
- __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */
-} USART_TypeDef; /** @} */
+ ******************************************************************************/
+/** USART Register Declaration */
+typedef struct {
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t FRAME; /**< USART Frame Format Register */
+ __IOM uint32_t TRIGCTRL; /**< USART Trigger Control Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IM uint32_t STATUS; /**< USART Status Register */
+ __IOM uint32_t CLKDIV; /**< Clock Control Register */
+ __IM uint32_t RXDATAX; /**< RX Buffer Data Extended Register */
+ __IM uint32_t RXDATA; /**< RX Buffer Data Register */
+ __IM uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */
+ __IM uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */
+ __IM uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */
+ __IM uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek Register */
+ __IOM uint32_t TXDATAX; /**< TX Buffer Data Extended Register */
+ __IOM uint32_t TXDATA; /**< TX Buffer Data Register */
+ __IOM uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */
+ __IOM uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IOM uint32_t IRCTRL; /**< IrDA Control Register */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use **/
+ __IOM uint32_t INPUT; /**< USART Input Register */
+ __IOM uint32_t I2SCTRL; /**< I2S Control Register */
+ __IOM uint32_t TIMING; /**< Timing Register */
+ __IOM uint32_t CTRLX; /**< Control Register Extended */
+ __IOM uint32_t TIMECMP0; /**< Used to Generate Interrupts and Various Delays */
+ __IOM uint32_t TIMECMP1; /**< Used to Generate Interrupts and Various Delays */
+ __IOM uint32_t TIMECMP2; /**< Used to Generate Interrupts and Various Delays */
+ __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
+ __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
+ __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */
+} USART_TypeDef; /** @} */
-/**************************************************************************//**
- * @defgroup EFR32FG12P_USART_BitFields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_USART
* @{
- *****************************************************************************/
+ * @defgroup EFR32FG12P_USART_BitFields USART Bit Fields
+ * @{
+ ******************************************************************************/
/* Bit fields for USART CTRL */
#define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */
@@ -128,7 +135,7 @@ typedef struct
#define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */
#define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */
#define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */
-#define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */
+#define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge for Setup/Sample */
#define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */
#define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */
#define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
@@ -142,7 +149,7 @@ typedef struct
#define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */
#define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
#define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_CSMA (0x1UL << 11) /**< Action On Slave-Select In Master Mode */
+#define USART_CTRL_CSMA (0x1UL << 11) /**< Action on Slave-Select in Master Mode */
#define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */
#define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */
#define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
@@ -165,7 +172,7 @@ typedef struct
#define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */
#define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
#define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */
+#define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter Output Invert */
#define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */
#define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */
#define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
@@ -205,17 +212,17 @@ typedef struct
#define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */
#define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
#define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */
+#define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA on Error */
#define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */
#define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */
#define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
#define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */
+#define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX on Error */
#define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */
#define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */
#define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
#define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */
+#define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX on Error */
#define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */
#define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */
#define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
@@ -225,7 +232,7 @@ typedef struct
#define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */
#define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
#define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */
+#define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap in Double Accesses */
#define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */
#define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */
#define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
@@ -320,32 +327,32 @@ typedef struct
#define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */
#define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
#define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
-#define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger after RX End of Frame plus TCMP0VAL */
+#define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger After RX End of Frame Plus TCMP0VAL */
#define _USART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */
#define _USART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */
#define _USART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
#define USART_TRIGCTRL_TXARX0EN_DEFAULT (_USART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
-#define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger after RX End of Frame plus TCMP1VAL */
+#define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger After RX End of Frame Plus TCMP1VAL */
#define _USART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */
#define _USART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */
#define _USART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
#define USART_TRIGCTRL_TXARX1EN_DEFAULT (_USART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
-#define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger after RX End of Frame plus TCMP2VAL */
+#define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger After RX End of Frame Plus TCMP2VAL */
#define _USART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */
#define _USART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */
#define _USART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
#define USART_TRIGCTRL_TXARX2EN_DEFAULT (_USART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
-#define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL0 baud-times */
+#define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger After TX End of Frame Plus TCMPVAL0 Baud-times */
#define _USART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */
#define _USART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */
#define _USART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
#define USART_TRIGCTRL_RXATX0EN_DEFAULT (_USART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
-#define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL1 baud-times */
+#define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger After TX End of Frame Plus TCMPVAL1 Baud-times */
#define _USART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */
#define _USART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */
#define _USART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
#define USART_TRIGCTRL_RXATX1EN_DEFAULT (_USART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
-#define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL2 baud-times */
+#define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger After TX End of Frame Plus TCMPVAL2 Baud-times */
#define _USART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */
#define _USART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */
#define _USART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
@@ -516,7 +523,7 @@ typedef struct
#define _USART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
#define _USART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */
#define USART_STATUS_TXIDLE_DEFAULT (_USART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_STATUS */
-#define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer restarted itself */
+#define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer Restarted Itself */
#define _USART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */
#define _USART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */
#define _USART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
@@ -533,7 +540,7 @@ typedef struct
#define _USART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */
#define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */
#define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CLKDIV */
-#define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */
+#define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD Detection Enable */
#define _USART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */
#define _USART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */
#define _USART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */
@@ -676,7 +683,7 @@ typedef struct
#define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */
#define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
#define USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */
-#define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */
+#define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data as Break */
#define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */
#define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */
#define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
@@ -717,7 +724,7 @@ typedef struct
#define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */
#define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
#define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
-#define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */
+#define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data as Break */
#define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */
#define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */
#define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
@@ -746,7 +753,7 @@ typedef struct
#define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */
#define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
#define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
-#define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */
+#define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data as Break */
#define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */
#define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */
#define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
@@ -832,7 +839,7 @@ typedef struct
#define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
#define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
#define USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IF */
-#define USART_IF_SSM (0x1UL << 11) /**< Slave-Select In Master Mode Interrupt Flag */
+#define USART_IF_SSM (0x1UL << 11) /**< Slave-Select in Master Mode Interrupt Flag */
#define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */
#define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
#define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
@@ -847,17 +854,17 @@ typedef struct
#define _USART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
#define _USART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
#define USART_IF_TXIDLE_DEFAULT (_USART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IF */
-#define USART_IF_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Flag */
+#define USART_IF_TCMP0 (0x1UL << 14) /**< Timer Comparator 0 Interrupt Flag */
#define _USART_IF_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */
#define _USART_IF_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */
#define _USART_IF_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
#define USART_IF_TCMP0_DEFAULT (_USART_IF_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IF */
-#define USART_IF_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Flag */
+#define USART_IF_TCMP1 (0x1UL << 15) /**< Timer Comparator 1 Interrupt Flag */
#define _USART_IF_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */
#define _USART_IF_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */
#define _USART_IF_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
#define USART_IF_TCMP1_DEFAULT (_USART_IF_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IF */
-#define USART_IF_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Flag */
+#define USART_IF_TCMP2 (0x1UL << 16) /**< Timer Comparator 2 Interrupt Flag */
#define _USART_IF_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */
#define _USART_IF_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */
#define _USART_IF_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
@@ -1261,12 +1268,12 @@ typedef struct
#define USART_I2SCTRL_JUSTIFY_DEFAULT (_USART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_I2SCTRL */
#define USART_I2SCTRL_JUSTIFY_LEFT (_USART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for USART_I2SCTRL */
#define USART_I2SCTRL_JUSTIFY_RIGHT (_USART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for USART_I2SCTRL */
-#define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request For Left/Right Data */
+#define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request for Left/Right Data */
#define _USART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */
#define _USART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */
#define _USART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
#define USART_I2SCTRL_DMASPLIT_DEFAULT (_USART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_I2SCTRL */
-#define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S data */
+#define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S Data */
#define _USART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */
#define _USART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */
#define _USART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
@@ -1379,7 +1386,7 @@ typedef struct
/* Bit fields for USART CTRLX */
#define _USART_CTRLX_RESETVALUE 0x00000000UL /**< Default value for USART_CTRLX */
#define _USART_CTRLX_MASK 0x0000000FUL /**< Mask for USART_CTRLX */
-#define USART_CTRLX_DBGHALT (0x1UL << 0) /**< Debug halt */
+#define USART_CTRLX_DBGHALT (0x1UL << 0) /**< Debug Halt */
#define _USART_CTRLX_DBGHALT_SHIFT 0 /**< Shift value for USART_DBGHALT */
#define _USART_CTRLX_DBGHALT_MASK 0x1UL /**< Bit mask for USART_DBGHALT */
#define _USART_CTRLX_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
@@ -1389,7 +1396,7 @@ typedef struct
#define _USART_CTRLX_CTSINV_MASK 0x2UL /**< Bit mask for USART_CTSINV */
#define _USART_CTRLX_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
#define USART_CTRLX_CTSINV_DEFAULT (_USART_CTRLX_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRLX */
-#define USART_CTRLX_CTSEN (0x1UL << 2) /**< CTS Function enabled */
+#define USART_CTRLX_CTSEN (0x1UL << 2) /**< CTS Function Enabled */
#define _USART_CTRLX_CTSEN_SHIFT 2 /**< Shift value for USART_CTSEN */
#define _USART_CTRLX_CTSEN_MASK 0x4UL /**< Bit mask for USART_CTSEN */
#define _USART_CTRLX_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
@@ -1967,6 +1974,6 @@ typedef struct
#define USART_ROUTELOC1_RTSLOC_LOC30 (_USART_ROUTELOC1_RTSLOC_LOC30 << 8) /**< Shifted mode LOC30 for USART_ROUTELOC1 */
#define USART_ROUTELOC1_RTSLOC_LOC31 (_USART_ROUTELOC1_RTSLOC_LOC31 << 8) /**< Shifted mode LOC31 for USART_ROUTELOC1 */
+/** @} */
/** @} End of group EFR32FG12P_USART */
/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_vdac.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_vdac.h
similarity index 97%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_vdac.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_vdac.h
index 00b70158..abd9f859 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_vdac.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_vdac.h
@@ -1,67 +1,74 @@
-/**************************************************************************//**
- * @file efr32fg12p_vdac.h
+/***************************************************************************//**
+ * @file
* @brief EFR32FG12P_VDAC register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_VDAC
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P_VDAC VDAC
* @{
* @brief EFR32FG12P_VDAC Register Declaration
- *****************************************************************************/
-typedef struct
-{
- __IOM uint32_t CTRL; /**< Control Register */
- __IM uint32_t STATUS; /**< Status Register */
- __IOM uint32_t CH0CTRL; /**< Channel 0 Control Register */
- __IOM uint32_t CH1CTRL; /**< Channel 1 Control Register */
- __IOM uint32_t CMD; /**< Command Register */
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- __IOM uint32_t CH0DATA; /**< Channel 0 Data Register */
- __IOM uint32_t CH1DATA; /**< Channel 1 Data Register */
- __IOM uint32_t COMBDATA; /**< Combined Data Register */
- __IOM uint32_t CAL; /**< Calibration Register */
+ ******************************************************************************/
+/** VDAC Register Declaration */
+typedef struct {
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IOM uint32_t CH0CTRL; /**< Channel 0 Control Register */
+ __IOM uint32_t CH1CTRL; /**< Channel 1 Control Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IOM uint32_t CH0DATA; /**< Channel 0 Data Register */
+ __IOM uint32_t CH1DATA; /**< Channel 1 Data Register */
+ __IOM uint32_t COMBDATA; /**< Combined Data Register */
+ __IOM uint32_t CAL; /**< Calibration Register */
- uint32_t RESERVED0[27]; /**< Reserved registers */
- VDAC_OPA_TypeDef OPA[3]; /**< OPA Registers */
-} VDAC_TypeDef; /** @} */
+ uint32_t RESERVED0[27U]; /**< Reserved registers */
+ VDAC_OPA_TypeDef OPA[3U]; /**< OPA Registers */
+} VDAC_TypeDef; /** @} */
-/**************************************************************************//**
- * @defgroup EFR32FG12P_VDAC_BitFields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_VDAC
* @{
- *****************************************************************************/
+ * @defgroup EFR32FG12P_VDAC_BitFields VDAC Bit Fields
+ * @{
+ ******************************************************************************/
/* Bit fields for VDAC CTRL */
#define _VDAC_CTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_CTRL */
@@ -814,42 +821,42 @@ typedef struct
/* Bit fields for VDAC OPA_APORTREQ */
#define _VDAC_OPA_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for VDAC_OPA_APORTREQ */
#define _VDAC_OPA_APORTREQ_MASK 0x000003FCUL /**< Mask for VDAC_OPA_APORTREQ */
-#define VDAC_OPA_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the bus connected to APORT2X is requested */
+#define VDAC_OPA_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 If the Bus Connected to APORT2X is Requested */
#define _VDAC_OPA_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for VDAC_OPAAPORT1XREQ */
#define _VDAC_OPA_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for VDAC_OPAAPORT1XREQ */
#define _VDAC_OPA_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */
#define VDAC_OPA_APORTREQ_APORT1XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */
-#define VDAC_OPA_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1X is requested */
+#define VDAC_OPA_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 If the Bus Connected to APORT1X is Requested */
#define _VDAC_OPA_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for VDAC_OPAAPORT1YREQ */
#define _VDAC_OPA_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for VDAC_OPAAPORT1YREQ */
#define _VDAC_OPA_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */
#define VDAC_OPA_APORTREQ_APORT1YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */
-#define VDAC_OPA_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 if the bus connected to APORT2X is requested */
+#define VDAC_OPA_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is Requested */
#define _VDAC_OPA_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for VDAC_OPAAPORT2XREQ */
#define _VDAC_OPA_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for VDAC_OPAAPORT2XREQ */
#define _VDAC_OPA_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */
#define VDAC_OPA_APORTREQ_APORT2XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */
-#define VDAC_OPA_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is requested */
+#define VDAC_OPA_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is Requested */
#define _VDAC_OPA_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for VDAC_OPAAPORT2YREQ */
#define _VDAC_OPA_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for VDAC_OPAAPORT2YREQ */
#define _VDAC_OPA_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */
#define VDAC_OPA_APORTREQ_APORT2YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */
-#define VDAC_OPA_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 if the bus connected to APORT3X is requested */
+#define VDAC_OPA_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is Requested */
#define _VDAC_OPA_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for VDAC_OPAAPORT3XREQ */
#define _VDAC_OPA_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for VDAC_OPAAPORT3XREQ */
#define _VDAC_OPA_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */
#define VDAC_OPA_APORTREQ_APORT3XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */
-#define VDAC_OPA_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is requested */
+#define VDAC_OPA_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is Requested */
#define _VDAC_OPA_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for VDAC_OPAAPORT3YREQ */
#define _VDAC_OPA_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for VDAC_OPAAPORT3YREQ */
#define _VDAC_OPA_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */
#define VDAC_OPA_APORTREQ_APORT3YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */
-#define VDAC_OPA_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 if the bus connected to APORT4X is requested */
+#define VDAC_OPA_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is Requested */
#define _VDAC_OPA_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for VDAC_OPAAPORT4XREQ */
#define _VDAC_OPA_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for VDAC_OPAAPORT4XREQ */
#define _VDAC_OPA_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */
#define VDAC_OPA_APORTREQ_APORT4XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */
-#define VDAC_OPA_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is requested */
+#define VDAC_OPA_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is Requested */
#define _VDAC_OPA_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for VDAC_OPAAPORT4YREQ */
#define _VDAC_OPA_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for VDAC_OPAAPORT4YREQ */
#define _VDAC_OPA_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */
@@ -858,42 +865,42 @@ typedef struct
/* Bit fields for VDAC OPA_APORTCONFLICT */
#define _VDAC_OPA_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for VDAC_OPA_APORTCONFLICT */
#define _VDAC_OPA_APORTCONFLICT_MASK 0x000003FCUL /**< Mask for VDAC_OPA_APORTCONFLICT */
-#define VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */
+#define VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */
#define _VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for VDAC_OPAAPORT1XCONFLICT */
#define _VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for VDAC_OPAAPORT1XCONFLICT */
#define _VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */
#define VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */
-#define VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */
+#define VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */
#define _VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for VDAC_OPAAPORT1YCONFLICT */
#define _VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for VDAC_OPAAPORT1YCONFLICT */
#define _VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */
#define VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */
-#define VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 if the bus connected to APORT2X is in conflict with another peripheral */
+#define VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is in Conflict With Another Peripheral */
#define _VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for VDAC_OPAAPORT2XCONFLICT */
#define _VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for VDAC_OPAAPORT2XCONFLICT */
#define _VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */
#define VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */
-#define VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is in conflict with another peripheral */
+#define VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is in Conflict With Another Peripheral */
#define _VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for VDAC_OPAAPORT2YCONFLICT */
#define _VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for VDAC_OPAAPORT2YCONFLICT */
#define _VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */
#define VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */
-#define VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 if the bus connected to APORT3X is in conflict with another peripheral */
+#define VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is in Conflict With Another Peripheral */
#define _VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for VDAC_OPAAPORT3XCONFLICT */
#define _VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for VDAC_OPAAPORT3XCONFLICT */
#define _VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */
#define VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */
-#define VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is in conflict with another peripheral */
+#define VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is in Conflict With Another Peripheral */
#define _VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for VDAC_OPAAPORT3YCONFLICT */
#define _VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for VDAC_OPAAPORT3YCONFLICT */
#define _VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */
#define VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */
-#define VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 if the bus connected to APORT4X is in conflict with another peripheral */
+#define VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is in Conflict With Another Peripheral */
#define _VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for VDAC_OPAAPORT4XCONFLICT */
#define _VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for VDAC_OPAAPORT4XCONFLICT */
#define _VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */
#define VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */
-#define VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is in conflict with another peripheral */
+#define VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is in Conflict With Another Peripheral */
#define _VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for VDAC_OPAAPORT4YCONFLICT */
#define _VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for VDAC_OPAAPORT4YCONFLICT */
#define _VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */
@@ -906,17 +913,17 @@ typedef struct
#define _VDAC_OPA_CTRL_DRIVESTRENGTH_MASK 0x3UL /**< Bit mask for VDAC_OPADRIVESTRENGTH */
#define _VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT 0x00000002UL /**< Mode DEFAULT for VDAC_OPA_CTRL */
#define VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT (_VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_INCBW (0x1UL << 2) /**< OPAx unity gain bandwidth scale. */
+#define VDAC_OPA_CTRL_INCBW (0x1UL << 2) /**< OPAx Unity Gain Bandwidth Scale */
#define _VDAC_OPA_CTRL_INCBW_SHIFT 2 /**< Shift value for VDAC_OPAINCBW */
#define _VDAC_OPA_CTRL_INCBW_MASK 0x4UL /**< Bit mask for VDAC_OPAINCBW */
#define _VDAC_OPA_CTRL_INCBW_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_CTRL */
#define VDAC_OPA_CTRL_INCBW_DEFAULT (_VDAC_OPA_CTRL_INCBW_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_HCMDIS (0x1UL << 3) /**< High Common Mode Disable. */
+#define VDAC_OPA_CTRL_HCMDIS (0x1UL << 3) /**< High Common Mode Disable */
#define _VDAC_OPA_CTRL_HCMDIS_SHIFT 3 /**< Shift value for VDAC_OPAHCMDIS */
#define _VDAC_OPA_CTRL_HCMDIS_MASK 0x8UL /**< Bit mask for VDAC_OPAHCMDIS */
#define _VDAC_OPA_CTRL_HCMDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_CTRL */
#define VDAC_OPA_CTRL_HCMDIS_DEFAULT (_VDAC_OPA_CTRL_HCMDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_OUTSCALE (0x1UL << 4) /**< Scale OPAx output driving strength. */
+#define VDAC_OPA_CTRL_OUTSCALE (0x1UL << 4) /**< Scale OPAx Output Driving Strength */
#define _VDAC_OPA_CTRL_OUTSCALE_SHIFT 4 /**< Shift value for VDAC_OPAOUTSCALE */
#define _VDAC_OPA_CTRL_OUTSCALE_MASK 0x10UL /**< Bit mask for VDAC_OPAOUTSCALE */
#define _VDAC_OPA_CTRL_OUTSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */
@@ -967,7 +974,7 @@ typedef struct
#define VDAC_OPA_CTRL_PRSSEL_PRSCH9 (_VDAC_OPA_CTRL_PRSSEL_PRSCH9 << 10) /**< Shifted mode PRSCH9 for VDAC_OPA_CTRL */
#define VDAC_OPA_CTRL_PRSSEL_PRSCH10 (_VDAC_OPA_CTRL_PRSSEL_PRSCH10 << 10) /**< Shifted mode PRSCH10 for VDAC_OPA_CTRL */
#define VDAC_OPA_CTRL_PRSSEL_PRSCH11 (_VDAC_OPA_CTRL_PRSSEL_PRSCH11 << 10) /**< Shifted mode PRSCH11 for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_PRSOUTMODE (0x1UL << 16) /**< OPAx PRS Output Select. */
+#define VDAC_OPA_CTRL_PRSOUTMODE (0x1UL << 16) /**< OPAx PRS Output Select */
#define _VDAC_OPA_CTRL_PRSOUTMODE_SHIFT 16 /**< Shift value for VDAC_OPAPRSOUTMODE */
#define _VDAC_OPA_CTRL_PRSOUTMODE_MASK 0x10000UL /**< Bit mask for VDAC_OPAPRSOUTMODE */
#define _VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */
@@ -1306,7 +1313,7 @@ typedef struct
#define VDAC_OPA_MUX_RESINMUX_CENTER (_VDAC_OPA_MUX_RESINMUX_CENTER << 16) /**< Shifted mode CENTER for VDAC_OPA_MUX */
#define VDAC_OPA_MUX_RESINMUX_DEFAULT (_VDAC_OPA_MUX_RESINMUX_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */
#define VDAC_OPA_MUX_RESINMUX_VSS (_VDAC_OPA_MUX_RESINMUX_VSS << 16) /**< Shifted mode VSS for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_GAIN3X (0x1UL << 20) /**< OPAx Dedicated 3x gain resistor ladder. */
+#define VDAC_OPA_MUX_GAIN3X (0x1UL << 20) /**< OPAx Dedicated 3x Gain Resistor Ladder */
#define _VDAC_OPA_MUX_GAIN3X_SHIFT 20 /**< Shift value for VDAC_OPAGAIN3X */
#define _VDAC_OPA_MUX_GAIN3X_MASK 0x100000UL /**< Bit mask for VDAC_OPAGAIN3X */
#define _VDAC_OPA_MUX_GAIN3X_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_MUX */
@@ -1534,6 +1541,6 @@ typedef struct
#define _VDAC_OPA_CAL_OFFSETN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */
#define VDAC_OPA_CAL_OFFSETN_DEFAULT (_VDAC_OPA_CAL_OFFSETN_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */
+/** @} */
/** @} End of group EFR32FG12P_VDAC */
/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_vdac_opa.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_vdac_opa.h
similarity index 60%
rename from mcu/efr/common/vendor/efr32fg13/efr32fg13p_vdac_opa.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_vdac_opa.h
index fa0d592f..779567c2 100644
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_vdac_opa.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_vdac_opa.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efr32fg13p_vdac_opa.h
- * @brief EFR32FG13P_VDAC_OPA register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+/***************************************************************************//**
+ * @file
+ * @brief EFR32FG12P_VDAC_OPA register and bit field definitions
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#if defined(__ICCARM__)
#pragma system_include /* Treat file as system include file. */
@@ -36,14 +34,14 @@
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @brief VDAC_OPA VDAC OPA Register
- * @ingroup EFR32FG13P_VDAC
- *****************************************************************************/
+ * @ingroup EFR32FG12P_VDAC
+ ******************************************************************************/
typedef struct {
__IM uint32_t APORTREQ; /**< Operational Amplifier APORT Request Status Register */
__IM uint32_t APORTCONFLICT; /**< Operational Amplifier APORT Conflict Status Register */
@@ -52,7 +50,7 @@ typedef struct {
__IOM uint32_t MUX; /**< Operational Amplifier Mux Configuration Register */
__IOM uint32_t OUT; /**< Operational Amplifier Output Configuration Register */
__IOM uint32_t CAL; /**< Operational Amplifier Calibration Register */
- uint32_t RESERVED0[1]; /**< Reserved future */
+ uint32_t RESERVED0[1U]; /**< Reserved future */
} VDAC_OPA_TypeDef;
/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_wdog.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_wdog.h
similarity index 94%
rename from mcu/efr/common/vendor/efr32fg12/efr32fg12p_wdog.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_wdog.h
index 65dfb7df..9120fb99 100644
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_wdog.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_wdog.h
@@ -1,63 +1,70 @@
-/**************************************************************************//**
- * @file efr32fg12p_wdog.h
+/***************************************************************************//**
+ * @file
* @brief EFR32FG12P_WDOG register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_WDOG
+ ******************************************************************************/
+
+#if defined(__ICCARM__)
+#pragma system_include /* Treat file as system include file. */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* Treat file as system include file. */
+#endif
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @defgroup EFR32FG12P_WDOG WDOG
* @{
* @brief EFR32FG12P_WDOG Register Declaration
- *****************************************************************************/
-typedef struct
-{
- __IOM uint32_t CTRL; /**< Control Register */
- __IOM uint32_t CMD; /**< Command Register */
+ ******************************************************************************/
+/** WDOG Register Declaration */
+typedef struct {
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t CMD; /**< Command Register */
- __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
+ __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
- WDOG_PCH_TypeDef PCH[2]; /**< PCH */
+ WDOG_PCH_TypeDef PCH[2U]; /**< PCH */
- uint32_t RESERVED0[2]; /**< Reserved for future use **/
- __IM uint32_t IF; /**< Watchdog Interrupt Flags */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
-} WDOG_TypeDef; /** @} */
+ uint32_t RESERVED0[2U]; /**< Reserved for future use **/
+ __IM uint32_t IF; /**< Watchdog Interrupt Flags */
+ __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
+ __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+} WDOG_TypeDef; /** @} */
-/**************************************************************************//**
- * @defgroup EFR32FG12P_WDOG_BitFields
+/***************************************************************************//**
+ * @addtogroup EFR32FG12P_WDOG
* @{
- *****************************************************************************/
+ * @defgroup EFR32FG12P_WDOG_BitFields WDOG Bit Fields
+ * @{
+ ******************************************************************************/
/* Bit fields for WDOG CTRL */
#define _WDOG_CTRL_RESETVALUE 0x00000F00UL /**< Default value for WDOG_CTRL */
@@ -82,7 +89,7 @@ typedef struct
#define _WDOG_CTRL_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */
#define _WDOG_CTRL_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_EM3RUN_DEFAULT (_WDOG_CTRL_EM3RUN_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CTRL */
-#define WDOG_CTRL_LOCK (0x1UL << 4) /**< Configuration lock */
+#define WDOG_CTRL_LOCK (0x1UL << 4) /**< Configuration Lock */
#define _WDOG_CTRL_LOCK_SHIFT 4 /**< Shift value for WDOG_LOCK */
#define _WDOG_CTRL_LOCK_MASK 0x10UL /**< Bit mask for WDOG_LOCK */
#define _WDOG_CTRL_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
@@ -208,7 +215,7 @@ typedef struct
#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WDOG_PCH_PRSCTRL */
#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WDOG_PCH_PRSCTRL */
#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WDOG_PCH_PRSCTRL */
-#define WDOG_PCH_PRSCTRL_PRSMISSRSTEN (0x1UL << 8) /**< PRS missing event will trigger a watchdog reset */
+#define WDOG_PCH_PRSCTRL_PRSMISSRSTEN (0x1UL << 8) /**< PRS Missing Event Will Trigger a Watchdog Reset */
#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_SHIFT 8 /**< Shift value for WDOG_PRSMISSRSTEN */
#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_MASK 0x100UL /**< Bit mask for WDOG_PRSMISSRSTEN */
#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */
@@ -330,6 +337,6 @@ typedef struct
#define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
#define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */
+/** @} */
/** @} End of group EFR32FG12P_WDOG */
/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_wdog_pch.h b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_wdog_pch.h
similarity index 52%
rename from mcu/efr/common/vendor/efr32fg13/efr32fg13p_wdog_pch.h
rename to mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_wdog_pch.h
index d41f3641..538f1cf0 100644
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_wdog_pch.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/efr32fg12p_wdog_pch.h
@@ -1,34 +1,32 @@
-/**************************************************************************//**
- * @file efr32fg13p_wdog_pch.h
- * @brief EFR32FG13P_WDOG_PCH register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
+/***************************************************************************//**
+ * @file
+ * @brief EFR32FG12P_WDOG_PCH register and bit field definitions
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#if defined(__ICCARM__)
#pragma system_include /* Treat file as system include file. */
@@ -36,14 +34,14 @@
#pragma clang system_header /* Treat file as system include file. */
#endif
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
* @brief WDOG_PCH WDOG PCH Register
- * @ingroup EFR32FG13P_WDOG
- *****************************************************************************/
+ * @ingroup EFR32FG12P_WDOG
+ ******************************************************************************/
typedef struct {
__IOM uint32_t PRSCTRL; /**< PRS Control Register */
} WDOG_PCH_TypeDef;
diff --git a/mcu/efr/common/vendor/efr32fg12/em_device_fg12.h b/mcu/efr/common/vendor/efr32fg12/Include/em_device.h
similarity index 62%
rename from mcu/efr/common/vendor/efr32fg12/em_device_fg12.h
rename to mcu/efr/common/vendor/efr32fg12/Include/em_device.h
index 58b8f75a..eeab6e48 100644
--- a/mcu/efr/common/vendor/efr32fg12/em_device_fg12.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/em_device.h
@@ -1,5 +1,5 @@
-/**************************************************************************//**
- * @file em_device.h
+/***************************************************************************//**
+ * @file
* @brief CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories
* microcontroller devices
*
@@ -9,40 +9,37 @@
* @verbatim
* Example: Add "-DEFM32G890F128" to your build options, to define part
* Add "#include "em_device.h" to your source files
+ * @endverbatim
*
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
*
- * @endverbatim
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
-#ifndef EM_DEVICE_FG12_H
-#define EM_DEVICE_FG12_H
+#ifndef EM_DEVICE_H
+#define EM_DEVICE_H
#if defined(EFR32FG12P231F1024GL125)
#include "efr32fg12p231f1024gl125.h"
@@ -50,6 +47,12 @@
#elif defined(EFR32FG12P231F1024GM48)
#include "efr32fg12p231f1024gm48.h"
+#elif defined(EFR32FG12P231F1024GM68)
+#include "efr32fg12p231f1024gm68.h"
+
+#elif defined(EFR32FG12P231F512GM68)
+#include "efr32fg12p231f512gm68.h"
+
#elif defined(EFR32FG12P232F1024GL125)
#include "efr32fg12p232f1024gl125.h"
@@ -62,6 +65,15 @@
#elif defined(EFR32FG12P431F1024GM48)
#include "efr32fg12p431f1024gm48.h"
+#elif defined(EFR32FG12P431F1024GM68)
+#include "efr32fg12p431f1024gm68.h"
+
+#elif defined(EFR32FG12P431F1024IM48)
+#include "efr32fg12p431f1024im48.h"
+
+#elif defined(EFR32FG12P431F512GM68)
+#include "efr32fg12p431f512gm68.h"
+
#elif defined(EFR32FG12P432F1024GL125)
#include "efr32fg12p432f1024gl125.h"
@@ -74,7 +86,11 @@
#elif defined(EFR32FG12P433F1024GM48)
#include "efr32fg12p433f1024gm48.h"
+#elif defined(EFR32FG12P433F1024GM68)
+#include "efr32fg12p433f1024gm68.h"
+
#else
#error "em_device.h: PART NUMBER undefined"
#endif
-#endif /* EM_DEVICE_FG12_H */
+
+#endif /* EM_DEVICE_H */
diff --git a/mcu/efr/common/vendor/efr32fg13/system_efr32fg13p.h b/mcu/efr/common/vendor/efr32fg12/Include/system_efr32fg12p.h
similarity index 78%
rename from mcu/efr/common/vendor/efr32fg13/system_efr32fg13p.h
rename to mcu/efr/common/vendor/efr32fg12/Include/system_efr32fg12p.h
index 66ca9e76..6ffa631c 100644
--- a/mcu/efr/common/vendor/efr32fg13/system_efr32fg13p.h
+++ b/mcu/efr/common/vendor/efr32fg12/Include/system_efr32fg12p.h
@@ -1,34 +1,32 @@
/***************************************************************************//**
- * @file system_efr32fg13p.h
+ * @file
* @brief CMSIS Cortex-M3/M4 System Layer for EFR32 devices.
- * @version 5.4.0
- ******************************************************************************
+ *******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#ifndef SYSTEM_EFR32_H
#define SYSTEM_EFR32_H
@@ -39,21 +37,38 @@ extern "C" {
#include
-/**************************************************************************//**
+/***************************************************************************//**
* @addtogroup Parts
* @{
- *****************************************************************************/
-/**************************************************************************//**
+ ******************************************************************************/
+/***************************************************************************//**
* @addtogroup EFR32 EFR32
* @{
- *****************************************************************************/
+ ******************************************************************************/
+
+/*******************************************************************************
+ ****************************** TYPEDEFS ***********************************
+ ******************************************************************************/
+
+/* Interrupt vectortable entry */
+typedef union {
+ void (*pFunc)(void);
+ void *topOfStack;
+} tVectorEntry;
/*******************************************************************************
************************** GLOBAL VARIABLES *******************************
******************************************************************************/
-extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */
-extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */
+extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */
+extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */
+
+#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+#if defined(__ICCARM__) /* IAR requires the __vector_table symbol */
+#define __Vectors __vector_table
+#endif
+extern const tVectorEntry __Vectors[];
+#endif
/*******************************************************************************
***************************** PROTOTYPES **********************************
@@ -100,7 +115,6 @@ void CRYPTO0_IRQHandler(void); /**< CRYPTO IRQ Handler */
void LETIMER0_IRQHandler(void); /**< LETIMER0 IRQ Handler */
void AGC_IRQHandler(void); /**< AGC IRQ Handler */
void PROTIMER_IRQHandler(void); /**< PROTIMER IRQ Handler */
-void PRORTC_IRQHandler(void); /**< PRORTC IRQ Handler */
void RTCC_IRQHandler(void); /**< RTCC IRQ Handler */
void SYNTH_IRQHandler(void); /**< SYNTH IRQ Handler */
void CRYOTIMER_IRQHandler(void); /**< CRYOTIMER IRQ Handler */
@@ -108,9 +122,14 @@ void RFSENSE_IRQHandler(void); /**< RFSENSE IRQ Handler */
void FPUEH_IRQHandler(void); /**< FPUEH IRQ Handler */
void SMU_IRQHandler(void); /**< SMU IRQ Handler */
void WTIMER0_IRQHandler(void); /**< WTIMER0 IRQ Handler */
+void WTIMER1_IRQHandler(void); /**< WTIMER1 IRQ Handler */
+void PCNT1_IRQHandler(void); /**< PCNT1 IRQ Handler */
+void PCNT2_IRQHandler(void); /**< PCNT2 IRQ Handler */
void USART2_RX_IRQHandler(void); /**< USART2_RX IRQ Handler */
void USART2_TX_IRQHandler(void); /**< USART2_TX IRQ Handler */
void I2C1_IRQHandler(void); /**< I2C1 IRQ Handler */
+void USART3_RX_IRQHandler(void); /**< USART3_RX IRQ Handler */
+void USART3_TX_IRQHandler(void); /**< USART3_TX IRQ Handler */
void VDAC0_IRQHandler(void); /**< VDAC0 IRQ Handler */
void CSEN_IRQHandler(void); /**< CSEN IRQ Handler */
void LESENSE_IRQHandler(void); /**< LESENSE IRQ Handler */
@@ -120,7 +139,7 @@ void SYSCFG_IRQHandler(void); /**< SYSCFG IRQ Handler */
uint32_t SystemCoreClockGet(void);
-/**************************************************************************//**
+/***************************************************************************//**
* @brief
* Update CMSIS SystemCoreClock variable.
*
@@ -133,7 +152,7 @@ uint32_t SystemCoreClockGet(void);
* API, this variable will be kept updated. This function is only provided
* for CMSIS compliance and if a user modifies the the core clock outside
* the CMU API.
- *****************************************************************************/
+ ******************************************************************************/
static __INLINE void SystemCoreClockUpdate(void)
{
(void)SystemCoreClockGet();
diff --git a/mcu/efr/common/vendor/efr32fg12/Source/ARM/startup_efr32fg12p.s b/mcu/efr/common/vendor/efr32fg12/Source/ARM/startup_efr32fg12p.s
new file mode 100644
index 00000000..f758c92a
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32fg12/Source/ARM/startup_efr32fg12p.s
@@ -0,0 +1,349 @@
+;/**************************************************************************//**
+; * @file
+; * @brief CMSIS Core Device Startup File for
+; * Silicon Labs EFR32FG12P Device Series
+; ******************************************************************************
+; * # License
+; *
+; * The licensor of this software is Silicon Laboratories Inc. Your use of this
+; * software is governed by the terms of Silicon Labs Master Software License
+; * Agreement (MSLA) available at
+; * www.silabs.com/about-us/legal/master-software-license-agreement. This
+; * software is Third Party Software licensed by Silicon Labs from a third party
+; * and is governed by the sections of the MSLA applicable to Third Party
+; * Software and the additional terms set forth below.
+; *
+; *****************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+ IF :DEF: __STACK_SIZE
+Stack_Size EQU __STACK_SIZE
+ ELSE
+Stack_Size EQU 0x00000400
+ ENDIF
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+ IF :DEF: __HEAP_SIZE
+Heap_Size EQU __HEAP_SIZE
+ ELSE
+Heap_Size EQU 0x00000C00
+ ENDIF
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY, ALIGN=9
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD sl_app_properties ; Application properties
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+
+ DCD EMU_IRQHandler ; 0: EMU Interrupt
+ DCD FRC_PRI_IRQHandler ; 1: FRC_PRI Interrupt
+ DCD WDOG0_IRQHandler ; 2: WDOG0 Interrupt
+ DCD WDOG1_IRQHandler ; 3: WDOG1 Interrupt
+ DCD FRC_IRQHandler ; 4: FRC Interrupt
+ DCD MODEM_IRQHandler ; 5: MODEM Interrupt
+ DCD RAC_SEQ_IRQHandler ; 6: RAC_SEQ Interrupt
+ DCD RAC_RSM_IRQHandler ; 7: RAC_RSM Interrupt
+ DCD BUFC_IRQHandler ; 8: BUFC Interrupt
+ DCD LDMA_IRQHandler ; 9: LDMA Interrupt
+ DCD GPIO_EVEN_IRQHandler ; 10: GPIO_EVEN Interrupt
+ DCD TIMER0_IRQHandler ; 11: TIMER0 Interrupt
+ DCD USART0_RX_IRQHandler ; 12: USART0_RX Interrupt
+ DCD USART0_TX_IRQHandler ; 13: USART0_TX Interrupt
+ DCD ACMP0_IRQHandler ; 14: ACMP0 Interrupt
+ DCD ADC0_IRQHandler ; 15: ADC0 Interrupt
+ DCD IDAC0_IRQHandler ; 16: IDAC0 Interrupt
+ DCD I2C0_IRQHandler ; 17: I2C0 Interrupt
+ DCD GPIO_ODD_IRQHandler ; 18: GPIO_ODD Interrupt
+ DCD TIMER1_IRQHandler ; 19: TIMER1 Interrupt
+ DCD USART1_RX_IRQHandler ; 20: USART1_RX Interrupt
+ DCD USART1_TX_IRQHandler ; 21: USART1_TX Interrupt
+ DCD LEUART0_IRQHandler ; 22: LEUART0 Interrupt
+ DCD PCNT0_IRQHandler ; 23: PCNT0 Interrupt
+ DCD CMU_IRQHandler ; 24: CMU Interrupt
+ DCD MSC_IRQHandler ; 25: MSC Interrupt
+ DCD CRYPTO0_IRQHandler ; 26: CRYPTO0 Interrupt
+ DCD LETIMER0_IRQHandler ; 27: LETIMER0 Interrupt
+ DCD AGC_IRQHandler ; 28: AGC Interrupt
+ DCD PROTIMER_IRQHandler ; 29: PROTIMER Interrupt
+ DCD RTCC_IRQHandler ; 30: RTCC Interrupt
+ DCD SYNTH_IRQHandler ; 31: SYNTH Interrupt
+ DCD CRYOTIMER_IRQHandler ; 32: CRYOTIMER Interrupt
+ DCD RFSENSE_IRQHandler ; 33: RFSENSE Interrupt
+ DCD FPUEH_IRQHandler ; 34: FPUEH Interrupt
+ DCD SMU_IRQHandler ; 35: SMU Interrupt
+ DCD WTIMER0_IRQHandler ; 36: WTIMER0 Interrupt
+ DCD WTIMER1_IRQHandler ; 37: WTIMER1 Interrupt
+ DCD PCNT1_IRQHandler ; 38: PCNT1 Interrupt
+ DCD PCNT2_IRQHandler ; 39: PCNT2 Interrupt
+ DCD USART2_RX_IRQHandler ; 40: USART2_RX Interrupt
+ DCD USART2_TX_IRQHandler ; 41: USART2_TX Interrupt
+ DCD I2C1_IRQHandler ; 42: I2C1 Interrupt
+ DCD USART3_RX_IRQHandler ; 43: USART3_RX Interrupt
+ DCD USART3_TX_IRQHandler ; 44: USART3_TX Interrupt
+ DCD VDAC0_IRQHandler ; 45: VDAC0 Interrupt
+ DCD CSEN_IRQHandler ; 46: CSEN Interrupt
+ DCD LESENSE_IRQHandler ; 47: LESENSE Interrupt
+ DCD CRYPTO1_IRQHandler ; 48: CRYPTO1 Interrupt
+ DCD TRNG0_IRQHandler ; 49: TRNG0 Interrupt
+ DCD 0 ; 50: Reserved
+
+__Vectors_End
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ EXPORT sl_app_properties [WEAK]
+sl_app_properties ; Provide a dummy value for the sl_app_properties symbol.
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT EMU_IRQHandler [WEAK]
+ EXPORT FRC_PRI_IRQHandler [WEAK]
+ EXPORT WDOG0_IRQHandler [WEAK]
+ EXPORT WDOG1_IRQHandler [WEAK]
+ EXPORT FRC_IRQHandler [WEAK]
+ EXPORT MODEM_IRQHandler [WEAK]
+ EXPORT RAC_SEQ_IRQHandler [WEAK]
+ EXPORT RAC_RSM_IRQHandler [WEAK]
+ EXPORT BUFC_IRQHandler [WEAK]
+ EXPORT LDMA_IRQHandler [WEAK]
+ EXPORT GPIO_EVEN_IRQHandler [WEAK]
+ EXPORT TIMER0_IRQHandler [WEAK]
+ EXPORT USART0_RX_IRQHandler [WEAK]
+ EXPORT USART0_TX_IRQHandler [WEAK]
+ EXPORT ACMP0_IRQHandler [WEAK]
+ EXPORT ADC0_IRQHandler [WEAK]
+ EXPORT IDAC0_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT GPIO_ODD_IRQHandler [WEAK]
+ EXPORT TIMER1_IRQHandler [WEAK]
+ EXPORT USART1_RX_IRQHandler [WEAK]
+ EXPORT USART1_TX_IRQHandler [WEAK]
+ EXPORT LEUART0_IRQHandler [WEAK]
+ EXPORT PCNT0_IRQHandler [WEAK]
+ EXPORT CMU_IRQHandler [WEAK]
+ EXPORT MSC_IRQHandler [WEAK]
+ EXPORT CRYPTO0_IRQHandler [WEAK]
+ EXPORT LETIMER0_IRQHandler [WEAK]
+ EXPORT AGC_IRQHandler [WEAK]
+ EXPORT PROTIMER_IRQHandler [WEAK]
+ EXPORT RTCC_IRQHandler [WEAK]
+ EXPORT SYNTH_IRQHandler [WEAK]
+ EXPORT CRYOTIMER_IRQHandler [WEAK]
+ EXPORT RFSENSE_IRQHandler [WEAK]
+ EXPORT FPUEH_IRQHandler [WEAK]
+ EXPORT SMU_IRQHandler [WEAK]
+ EXPORT WTIMER0_IRQHandler [WEAK]
+ EXPORT WTIMER1_IRQHandler [WEAK]
+ EXPORT PCNT1_IRQHandler [WEAK]
+ EXPORT PCNT2_IRQHandler [WEAK]
+ EXPORT USART2_RX_IRQHandler [WEAK]
+ EXPORT USART2_TX_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT USART3_RX_IRQHandler [WEAK]
+ EXPORT USART3_TX_IRQHandler [WEAK]
+ EXPORT VDAC0_IRQHandler [WEAK]
+ EXPORT CSEN_IRQHandler [WEAK]
+ EXPORT LESENSE_IRQHandler [WEAK]
+ EXPORT CRYPTO1_IRQHandler [WEAK]
+ EXPORT TRNG0_IRQHandler [WEAK]
+
+
+EMU_IRQHandler
+FRC_PRI_IRQHandler
+WDOG0_IRQHandler
+WDOG1_IRQHandler
+FRC_IRQHandler
+MODEM_IRQHandler
+RAC_SEQ_IRQHandler
+RAC_RSM_IRQHandler
+BUFC_IRQHandler
+LDMA_IRQHandler
+GPIO_EVEN_IRQHandler
+TIMER0_IRQHandler
+USART0_RX_IRQHandler
+USART0_TX_IRQHandler
+ACMP0_IRQHandler
+ADC0_IRQHandler
+IDAC0_IRQHandler
+I2C0_IRQHandler
+GPIO_ODD_IRQHandler
+TIMER1_IRQHandler
+USART1_RX_IRQHandler
+USART1_TX_IRQHandler
+LEUART0_IRQHandler
+PCNT0_IRQHandler
+CMU_IRQHandler
+MSC_IRQHandler
+CRYPTO0_IRQHandler
+LETIMER0_IRQHandler
+AGC_IRQHandler
+PROTIMER_IRQHandler
+RTCC_IRQHandler
+SYNTH_IRQHandler
+CRYOTIMER_IRQHandler
+RFSENSE_IRQHandler
+FPUEH_IRQHandler
+SMU_IRQHandler
+WTIMER0_IRQHandler
+WTIMER1_IRQHandler
+PCNT1_IRQHandler
+PCNT2_IRQHandler
+USART2_RX_IRQHandler
+USART2_TX_IRQHandler
+I2C1_IRQHandler
+USART3_RX_IRQHandler
+USART3_TX_IRQHandler
+VDAC0_IRQHandler
+CSEN_IRQHandler
+LESENSE_IRQHandler
+CRYPTO1_IRQHandler
+TRNG0_IRQHandler
+ B .
+ ENDP
+
+ ALIGN
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+ END
diff --git a/mcu/efr/common/vendor/efr32fg12/Source/GCC/efr32fg12p.ld b/mcu/efr/common/vendor/efr32fg12/Source/GCC/efr32fg12p.ld
new file mode 100644
index 00000000..ed292e4b
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32fg12/Source/GCC/efr32fg12p.ld
@@ -0,0 +1,229 @@
+/***************************************************************************//**
+ * Linker script for Silicon Labs EFR32FG12P devices
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 1048576
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 262144
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapBase
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.vectors))
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG (__data2_end__ - __data2_start__)
+ __copy_table_end__ = .;
+ } > FLASH
+ */
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (__bss2_start__)
+ LONG (__bss2_end__ - __bss2_start__)
+ __zero_table_end__ = .;
+ } > FLASH
+ */
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+ . = ALIGN (4);
+ PROVIDE (__ram_func_section_start = .);
+ *(.ram)
+ PROVIDE (__ram_func_section_end = .);
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __HeapBase = .;
+ __end__ = .;
+ end = __end__;
+ _end = __end__;
+ KEEP(*(.heap*))
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ KEEP(*(.stack*))
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+ /* Check if FLASH usage exceeds FLASH size */
+ ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), "FLASH memory overflowed !")
+}
diff --git a/mcu/efr/common/vendor/efr32fg12/Source/GCC/startup_efr32fg12p.S b/mcu/efr/common/vendor/efr32fg12/Source/GCC/startup_efr32fg12p.S
new file mode 100644
index 00000000..f5864c1c
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32fg12/Source/GCC/startup_efr32fg12p.S
@@ -0,0 +1,365 @@
+/***************************************************************************//**
+ * @file
+ * @brief startup file for Silicon Labs EFR32FG12P devices.
+ * For use with GCC for ARM Embedded Processors
+ *******************************************************************************
+ * # License
+ *
+ * The licensor of this software is Silicon Laboratories Inc. Your use of this
+ * software is governed by the terms of Silicon Labs Master Software License
+ * Agreement (MSLA) available at
+ * www.silabs.com/about-us/legal/master-software-license-agreement. This
+ * software is Third Party Software licensed by Silicon Labs from a third party
+ * and is governed by the sections of the MSLA applicable to Third Party
+ * Software and the additional terms set forth below.
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ .syntax unified
+ .arch armv7-m
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x00000400
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x00000C00
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .vectors
+ .align 9
+ .globl __Vectors
+__Vectors:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long Default_Handler /* Reserved */
+ .long Default_Handler /* Reserved */
+ .long Default_Handler /* Reserved */
+ .long Default_Handler /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long sl_app_properties /* Application properties */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long EMU_IRQHandler /* 0 - EMU */
+ .long FRC_PRI_IRQHandler /* 1 - FRC_PRI */
+ .long WDOG0_IRQHandler /* 2 - WDOG0 */
+ .long WDOG1_IRQHandler /* 3 - WDOG1 */
+ .long FRC_IRQHandler /* 4 - FRC */
+ .long MODEM_IRQHandler /* 5 - MODEM */
+ .long RAC_SEQ_IRQHandler /* 6 - RAC_SEQ */
+ .long RAC_RSM_IRQHandler /* 7 - RAC_RSM */
+ .long BUFC_IRQHandler /* 8 - BUFC */
+ .long LDMA_IRQHandler /* 9 - LDMA */
+ .long GPIO_EVEN_IRQHandler /* 10 - GPIO_EVEN */
+ .long TIMER0_IRQHandler /* 11 - TIMER0 */
+ .long USART0_RX_IRQHandler /* 12 - USART0_RX */
+ .long USART0_TX_IRQHandler /* 13 - USART0_TX */
+ .long ACMP0_IRQHandler /* 14 - ACMP0 */
+ .long ADC0_IRQHandler /* 15 - ADC0 */
+ .long IDAC0_IRQHandler /* 16 - IDAC0 */
+ .long I2C0_IRQHandler /* 17 - I2C0 */
+ .long GPIO_ODD_IRQHandler /* 18 - GPIO_ODD */
+ .long TIMER1_IRQHandler /* 19 - TIMER1 */
+ .long USART1_RX_IRQHandler /* 20 - USART1_RX */
+ .long USART1_TX_IRQHandler /* 21 - USART1_TX */
+ .long LEUART0_IRQHandler /* 22 - LEUART0 */
+ .long PCNT0_IRQHandler /* 23 - PCNT0 */
+ .long CMU_IRQHandler /* 24 - CMU */
+ .long MSC_IRQHandler /* 25 - MSC */
+ .long CRYPTO0_IRQHandler /* 26 - CRYPTO0 */
+ .long LETIMER0_IRQHandler /* 27 - LETIMER0 */
+ .long AGC_IRQHandler /* 28 - AGC */
+ .long PROTIMER_IRQHandler /* 29 - PROTIMER */
+ .long RTCC_IRQHandler /* 30 - RTCC */
+ .long SYNTH_IRQHandler /* 31 - SYNTH */
+ .long CRYOTIMER_IRQHandler /* 32 - CRYOTIMER */
+ .long RFSENSE_IRQHandler /* 33 - RFSENSE */
+ .long FPUEH_IRQHandler /* 34 - FPUEH */
+ .long SMU_IRQHandler /* 35 - SMU */
+ .long WTIMER0_IRQHandler /* 36 - WTIMER0 */
+ .long WTIMER1_IRQHandler /* 37 - WTIMER1 */
+ .long PCNT1_IRQHandler /* 38 - PCNT1 */
+ .long PCNT2_IRQHandler /* 39 - PCNT2 */
+ .long USART2_RX_IRQHandler /* 40 - USART2_RX */
+ .long USART2_TX_IRQHandler /* 41 - USART2_TX */
+ .long I2C1_IRQHandler /* 42 - I2C1 */
+ .long USART3_RX_IRQHandler /* 43 - USART3_RX */
+ .long USART3_TX_IRQHandler /* 44 - USART3_TX */
+ .long VDAC0_IRQHandler /* 45 - VDAC0 */
+ .long CSEN_IRQHandler /* 46 - CSEN */
+ .long LESENSE_IRQHandler /* 47 - LESENSE */
+ .long CRYPTO1_IRQHandler /* 48 - CRYPTO1 */
+ .long TRNG0_IRQHandler /* 49 - TRNG0 */
+ .long Default_Handler /* 50 - Reserved */
+
+
+ .size __Vectors, . - __Vectors
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+#ifndef __NO_SYSTEM_INIT
+ ldr r0, =SystemInit
+ blx r0
+#endif
+
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+#endif /* __STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __zero_table_start__ and __zero_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak Default_Handler
+ .type Default_Handler, %function
+ .weak sl_app_properties
+ .type sl_app_properties, %common
+Default_Handler:
+sl_app_properties: /* Provide a dummy value for the sl_app_properties symbol. */
+ b .
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers.
+ */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler MemManage_Handler
+ def_irq_handler BusFault_Handler
+ def_irq_handler UsageFault_Handler
+ def_irq_handler SVC_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+
+ def_irq_handler EMU_IRQHandler
+ def_irq_handler FRC_PRI_IRQHandler
+ def_irq_handler WDOG0_IRQHandler
+ def_irq_handler WDOG1_IRQHandler
+ def_irq_handler FRC_IRQHandler
+ def_irq_handler MODEM_IRQHandler
+ def_irq_handler RAC_SEQ_IRQHandler
+ def_irq_handler RAC_RSM_IRQHandler
+ def_irq_handler BUFC_IRQHandler
+ def_irq_handler LDMA_IRQHandler
+ def_irq_handler GPIO_EVEN_IRQHandler
+ def_irq_handler TIMER0_IRQHandler
+ def_irq_handler USART0_RX_IRQHandler
+ def_irq_handler USART0_TX_IRQHandler
+ def_irq_handler ACMP0_IRQHandler
+ def_irq_handler ADC0_IRQHandler
+ def_irq_handler IDAC0_IRQHandler
+ def_irq_handler I2C0_IRQHandler
+ def_irq_handler GPIO_ODD_IRQHandler
+ def_irq_handler TIMER1_IRQHandler
+ def_irq_handler USART1_RX_IRQHandler
+ def_irq_handler USART1_TX_IRQHandler
+ def_irq_handler LEUART0_IRQHandler
+ def_irq_handler PCNT0_IRQHandler
+ def_irq_handler CMU_IRQHandler
+ def_irq_handler MSC_IRQHandler
+ def_irq_handler CRYPTO0_IRQHandler
+ def_irq_handler LETIMER0_IRQHandler
+ def_irq_handler AGC_IRQHandler
+ def_irq_handler PROTIMER_IRQHandler
+ def_irq_handler RTCC_IRQHandler
+ def_irq_handler SYNTH_IRQHandler
+ def_irq_handler CRYOTIMER_IRQHandler
+ def_irq_handler RFSENSE_IRQHandler
+ def_irq_handler FPUEH_IRQHandler
+ def_irq_handler SMU_IRQHandler
+ def_irq_handler WTIMER0_IRQHandler
+ def_irq_handler WTIMER1_IRQHandler
+ def_irq_handler PCNT1_IRQHandler
+ def_irq_handler PCNT2_IRQHandler
+ def_irq_handler USART2_RX_IRQHandler
+ def_irq_handler USART2_TX_IRQHandler
+ def_irq_handler I2C1_IRQHandler
+ def_irq_handler USART3_RX_IRQHandler
+ def_irq_handler USART3_TX_IRQHandler
+ def_irq_handler VDAC0_IRQHandler
+ def_irq_handler CSEN_IRQHandler
+ def_irq_handler LESENSE_IRQHandler
+ def_irq_handler CRYPTO1_IRQHandler
+ def_irq_handler TRNG0_IRQHandler
+
+ .end
diff --git a/mcu/efr/common/vendor/efr32fg12/Source/GCC/startup_efr32fg12p.c b/mcu/efr/common/vendor/efr32fg12/Source/GCC/startup_efr32fg12p.c
new file mode 100644
index 00000000..9d610d3e
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32fg12/Source/GCC/startup_efr32fg12p.c
@@ -0,0 +1,381 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Compatible EFR32FG12P startup file in C.
+ * Should be used with GCC 'GNU Tools ARM Embedded'
+ *******************************************************************************
+ * # License
+ *
+ * The licensor of this software is Silicon Laboratories Inc. Your use of this
+ * software is governed by the terms of Silicon Labs Master Software License
+ * Agreement (MSLA) available at
+ * www.silabs.com/about-us/legal/master-software-license-agreement. This
+ * software is Third Party Software licensed by Silicon Labs from a third party
+ * and is governed by the sections of the MSLA applicable to Third Party
+ * Software and the additional terms set forth below.
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include
+#include "em_device.h" /* The correct device header file. */
+
+#ifdef BOOTLOADER_ENABLE
+#include "api/btl_interface.h"
+
+#endif
+
+/*----------------------------------------------------------------------------
+ * Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t __etext;
+extern uint32_t __data_start__;
+extern uint32_t __data_end__;
+extern uint32_t __copy_table_start__;
+extern uint32_t __copy_table_end__;
+extern uint32_t __zero_table_start__;
+extern uint32_t __zero_table_end__;
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+extern uint32_t __StackTop;
+
+#ifdef BOOTLOADER_ENABLE
+extern MainBootloaderTable_t mainStageTable;
+
+extern void SystemInit2(void);
+
+/*----------------------------------------------------------------------------
+ * Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void (*pFunc)(void);
+#endif
+
+/*----------------------------------------------------------------------------
+ * External References
+ *----------------------------------------------------------------------------*/
+#ifndef __START
+extern void _start(void) __attribute__((noreturn)); /* Pre Main (C library entry point) */
+#else
+extern int __START(void) __attribute__((noreturn)); /* main entry point */
+#endif
+
+#ifndef __NO_SYSTEM_INIT
+extern void SystemInit(void); /* CMSIS System Initialization */
+#endif
+
+/*----------------------------------------------------------------------------
+ * Internal References
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void); /* Default empty handler */
+void Reset_Handler(void); /* Reset Handler */
+
+/*----------------------------------------------------------------------------
+ * User Initial Stack & Heap
+ *----------------------------------------------------------------------------*/
+#ifndef __STACK_SIZE
+#define __STACK_SIZE 0x00000400
+#endif
+static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
+
+#ifndef __HEAP_SIZE
+#define __HEAP_SIZE 0x00000C00
+#endif
+#if __HEAP_SIZE > 0
+static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap")));
+#endif
+
+/*----------------------------------------------------------------------------
+ * Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Cortex-M Processor Exceptions */
+void NMI_Handler(void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler(void) __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler(void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler(void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler(void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler(void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler(void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler(void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler(void) __attribute__ ((weak, alias("Default_Handler")));
+/* Provide a dummy value for the sl_app_properties symbol. */
+void sl_app_properties(void); /* Prototype to please MISRA checkers. */
+void sl_app_properties(void) __attribute__ ((weak, alias("Default_Handler")));
+
+/* Part Specific Interrupts */
+
+void EMU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void FRC_PRI_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void WDOG0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void WDOG1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void FRC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void MODEM_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void RAC_SEQ_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void RAC_RSM_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void BUFC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void LDMA_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void GPIO_EVEN_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void TIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void USART0_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void USART0_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void ACMP0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void ADC0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void IDAC0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void I2C0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void GPIO_ODD_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void TIMER1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void USART1_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void USART1_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void LEUART0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void PCNT0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void CMU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void MSC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void CRYPTO0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void LETIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void AGC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void PROTIMER_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void RTCC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void SYNTH_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void CRYOTIMER_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void RFSENSE_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void FPUEH_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void SMU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void WTIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void WTIMER1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void PCNT1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void PCNT2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void USART2_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void USART2_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void I2C1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void USART3_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void USART3_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void VDAC0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void CSEN_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void LESENSE_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void CRYPTO1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void TRNG0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+ * Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+extern const tVectorEntry __Vectors[];
+const tVectorEntry __Vectors[] __attribute__ ((aligned(512))) __attribute__ ((section(".vectors"))) = {
+ /* Cortex-M Exception Handlers */
+ { .topOfStack = &__StackTop }, /* Initial Stack Pointer */
+ { Reset_Handler }, /* Reset Handler */
+ { NMI_Handler }, /* NMI Handler */
+ { HardFault_Handler }, /* Hard Fault Handler */
+ { MemManage_Handler }, /* MPU Fault Handler */
+ { BusFault_Handler }, /* Bus Fault Handler */
+ { UsageFault_Handler }, /* Usage Fault Handler */
+ { Default_Handler }, /* Reserved */
+ { Default_Handler }, /* Reserved */
+ { Default_Handler }, /* Reserved */
+#ifdef BOOTLOADER_ENABLE
+ { (pFunc) & mainStageTable },
+#else
+ { Default_Handler }, /* Reserved */
+#endif
+ { SVC_Handler }, /* SVCall Handler */
+ { DebugMon_Handler }, /* Debug Monitor Handler */
+ { sl_app_properties }, /* Application properties*/
+ { PendSV_Handler }, /* PendSV Handler */
+ { SysTick_Handler }, /* SysTick Handler */
+
+ /* External interrupts */
+
+ { EMU_IRQHandler }, /* 0 */
+ { FRC_PRI_IRQHandler }, /* 1 */
+ { WDOG0_IRQHandler }, /* 2 */
+ { WDOG1_IRQHandler }, /* 3 */
+ { FRC_IRQHandler }, /* 4 */
+ { MODEM_IRQHandler }, /* 5 */
+ { RAC_SEQ_IRQHandler }, /* 6 */
+ { RAC_RSM_IRQHandler }, /* 7 */
+ { BUFC_IRQHandler }, /* 8 */
+ { LDMA_IRQHandler }, /* 9 */
+ { GPIO_EVEN_IRQHandler }, /* 10 */
+ { TIMER0_IRQHandler }, /* 11 */
+ { USART0_RX_IRQHandler }, /* 12 */
+ { USART0_TX_IRQHandler }, /* 13 */
+ { ACMP0_IRQHandler }, /* 14 */
+ { ADC0_IRQHandler }, /* 15 */
+ { IDAC0_IRQHandler }, /* 16 */
+ { I2C0_IRQHandler }, /* 17 */
+ { GPIO_ODD_IRQHandler }, /* 18 */
+ { TIMER1_IRQHandler }, /* 19 */
+ { USART1_RX_IRQHandler }, /* 20 */
+ { USART1_TX_IRQHandler }, /* 21 */
+ { LEUART0_IRQHandler }, /* 22 */
+ { PCNT0_IRQHandler }, /* 23 */
+ { CMU_IRQHandler }, /* 24 */
+ { MSC_IRQHandler }, /* 25 */
+ { CRYPTO0_IRQHandler }, /* 26 */
+ { LETIMER0_IRQHandler }, /* 27 */
+ { AGC_IRQHandler }, /* 28 */
+ { PROTIMER_IRQHandler }, /* 29 */
+ { RTCC_IRQHandler }, /* 30 */
+ { SYNTH_IRQHandler }, /* 31 */
+ { CRYOTIMER_IRQHandler }, /* 32 */
+ { RFSENSE_IRQHandler }, /* 33 */
+ { FPUEH_IRQHandler }, /* 34 */
+ { SMU_IRQHandler }, /* 35 */
+ { WTIMER0_IRQHandler }, /* 36 */
+ { WTIMER1_IRQHandler }, /* 37 */
+ { PCNT1_IRQHandler }, /* 38 */
+ { PCNT2_IRQHandler }, /* 39 */
+ { USART2_RX_IRQHandler }, /* 40 */
+ { USART2_TX_IRQHandler }, /* 41 */
+ { I2C1_IRQHandler }, /* 42 */
+ { USART3_RX_IRQHandler }, /* 43 */
+ { USART3_TX_IRQHandler }, /* 44 */
+ { VDAC0_IRQHandler }, /* 45 */
+ { CSEN_IRQHandler }, /* 46 */
+ { LESENSE_IRQHandler }, /* 47 */
+ { CRYPTO1_IRQHandler }, /* 48 */
+ { TRNG0_IRQHandler }, /* 49 */
+ { Default_Handler }, /* 50 - Reserved */
+};
+
+/*----------------------------------------------------------------------------
+ * Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+ uint32_t *pSrc, *pDest;
+ uint32_t start, end;
+ uint32_t tableStart __attribute__((unused));
+ uint32_t tableEnd __attribute__((unused));
+
+#ifndef __NO_SYSTEM_INIT
+ SystemInit();
+#endif
+
+#ifdef BOOTLOADER_ENABLE
+ SystemInit2();
+#endif
+
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ tableStart = (uint32_t) &__copy_table_start__;
+ tableEnd = (uint32_t) &__copy_table_end__;
+
+ for (; tableStart < tableEnd; tableStart += 12U) {
+ pSrc = (uint32_t *) (*(uint32_t *) tableStart);
+ start = *(uint32_t *) (tableStart + 4U);
+ end = *(uint32_t *) (tableStart + 8U) + start;
+ pDest = (uint32_t *) start;
+ for (; start < end; start += 4U) {
+ *pDest++ = *pSrc++;
+ }
+ }
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ pSrc = &__etext;
+ pDest = &__data_start__;
+ start = (uint32_t) &__data_start__;
+ end = (uint32_t) &__data_end__;
+
+ for (; start < end; start += 4U) {
+ *pDest++ = *pSrc++;
+ }
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __zero_table_start__ and __zero_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ tableStart = (uint32_t) &__zero_table_start__;
+ tableEnd = (uint32_t) &__zero_table_end__;
+
+ for (; tableStart < tableEnd; tableStart += 8U) {
+ start = *(uint32_t *) tableStart;
+ end = *(uint32_t *) (tableStart + 4U) + start;
+ pDest = (uint32_t *) start;
+ for (; start < end; start += 4U) {
+ *pDest++ = 0UL;
+ }
+ }
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ pDest = &__bss_start__;
+ start = (uint32_t) &__bss_start__;
+ end = (uint32_t) &__bss_end__;
+
+ for (; start < end; start += 4U) {
+ *pDest++ = 0UL;
+ }
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __START
+#define __START _start
+#endif
+ __START();
+}
+
+/*----------------------------------------------------------------------------
+ * Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+ while (true) {
+ }
+}
diff --git a/mcu/efr/common/vendor/efr32fg12/system_efr32fg12p.c b/mcu/efr/common/vendor/efr32fg12/Source/system_efr32fg12p.c
similarity index 80%
rename from mcu/efr/common/vendor/efr32fg12/system_efr32fg12p.c
rename to mcu/efr/common/vendor/efr32fg12/Source/system_efr32fg12p.c
index e30ff9b3..d6222820 100644
--- a/mcu/efr/common/vendor/efr32fg12/system_efr32fg12p.c
+++ b/mcu/efr/common/vendor/efr32fg12/Source/system_efr32fg12p.c
@@ -1,37 +1,35 @@
/***************************************************************************//**
- * @file system_efr32fg12p.c
+ * @file
* @brief CMSIS Cortex-M3/M4 System Layer for EFR32 devices.
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
+ ******************************************************************************/
#include
-#include "em_device_fg12.h"
+#include "em_device.h"
/*******************************************************************************
****************************** DEFINES ************************************
@@ -39,6 +37,7 @@
/** LFRCO frequency, tuned to below frequency during manufacturing. */
#define EFR32_LFRCO_FREQ (32768UL)
+/** ULFRCO frequency */
#define EFR32_ULFRCO_FREQ (1000UL)
/*******************************************************************************
@@ -48,26 +47,28 @@
/* System oscillator frequencies. These frequencies are normally constant */
/* for a target, but they are made configurable in order to allow run-time */
/* handling of different boards. The crystal oscillator clocks can be set */
-/* compile time to a non-default value by defining respective EFR_nFXO_FREQ */
-/* values according to board design. By defining the EFR_nFXO_FREQ to 0, */
+/* compile time to a non-default value by defining respective EFR32_nFXO_FREQ */
+/* values according to board design. By defining the EFR32_nFXO_FREQ to 0, */
/* one indicates that the oscillator is not present, in order to save some */
/* SW footprint. */
#ifndef EFR32_HFRCO_MAX_FREQ
+/** Maximum HFRCO frequency */
#define EFR32_HFRCO_MAX_FREQ (38000000UL)
#endif
#ifndef EFR32_HFXO_FREQ
+/** HFXO frequency */
#define EFR32_HFXO_FREQ (38400000UL)
#endif
#ifndef EFR32_HFRCO_STARTUP_FREQ
+/** HFRCO startup frequency */
#define EFR32_HFRCO_STARTUP_FREQ (19000000UL)
#endif
-
/* Do not define variable if HF crystal oscillator not present */
-#if (EFR32_HFXO_FREQ > 0UL)
+#if (EFR32_HFXO_FREQ > 0U)
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** System HFXO clock. */
static uint32_t SystemHFXOClock = EFR32_HFXO_FREQ;
@@ -75,17 +76,17 @@ static uint32_t SystemHFXOClock = EFR32_HFXO_FREQ;
#endif
#ifndef EFR32_LFXO_FREQ
+/** LFXO frequency */
#define EFR32_LFXO_FREQ (EFR32_LFRCO_FREQ)
#endif
/* Do not define variable if LF crystal oscillator not present */
-#if (EFR32_LFXO_FREQ > 0UL)
+#if (EFR32_LFXO_FREQ > 0U)
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** System LFXO clock. */
-static uint32_t SystemLFXOClock = 32768UL;
+static uint32_t SystemLFXOClock = EFR32_LFXO_FREQ;
/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
#endif
-
/*******************************************************************************
************************** GLOBAL VARIABLES *******************************
******************************************************************************/
@@ -97,8 +98,7 @@ static uint32_t SystemLFXOClock = 32768UL;
* @details
* Required CMSIS global variable that must be kept up-to-date.
*/
-uint32_t SystemCoreClock;
-
+uint32_t SystemCoreClock = EFR32_HFRCO_STARTUP_FREQ;
/**
* @brief
@@ -112,7 +112,6 @@ uint32_t SystemCoreClock;
*/
uint32_t SystemHfrcoFreq = EFR32_HFRCO_STARTUP_FREQ;
-
/*******************************************************************************
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
@@ -140,9 +139,9 @@ uint32_t SystemCoreClockGet(void)
uint32_t presc;
ret = SystemHFClockGet();
- presc = (CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK) >>
- _CMU_HFCOREPRESC_PRESC_SHIFT;
- ret /= (presc + 1);
+ presc = (CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK)
+ >> _CMU_HFCOREPRESC_PRESC_SHIFT;
+ ret /= presc + 1U;
/* Keep CMSIS system clock variable up-to-date */
SystemCoreClock = ret;
@@ -150,7 +149,6 @@ uint32_t SystemCoreClockGet(void)
return ret;
}
-
/***************************************************************************//**
* @brief
* Get the maximum core clock frequency.
@@ -163,11 +161,13 @@ uint32_t SystemCoreClockGet(void)
******************************************************************************/
uint32_t SystemMaxCoreClockGet(void)
{
- return (EFR32_HFRCO_MAX_FREQ > EFR32_HFXO_FREQ ? \
- EFR32_HFRCO_MAX_FREQ : EFR32_HFXO_FREQ);
+#if (EFR32_HFRCO_MAX_FREQ > EFR32_HFXO_FREQ)
+ return EFR32_HFRCO_MAX_FREQ;
+#else
+ return EFR32_HFXO_FREQ;
+#endif
}
-
/***************************************************************************//**
* @brief
* Get the current HFCLK frequency.
@@ -182,15 +182,14 @@ uint32_t SystemHFClockGet(void)
{
uint32_t ret;
- switch (CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK)
- {
+ switch (CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) {
case CMU_HFCLKSTATUS_SELECTED_LFXO:
-#if (EFR32_LFXO_FREQ > 0)
+#if (EFR32_LFXO_FREQ > 0U)
ret = SystemLFXOClock;
#else
/* We should not get here, since core should not be clocked. May */
/* be caused by a misconfiguration though. */
- ret = 0;
+ ret = 0U;
#endif
break;
@@ -199,15 +198,19 @@ uint32_t SystemHFClockGet(void)
break;
case CMU_HFCLKSTATUS_SELECTED_HFXO:
-#if (EFR32_HFXO_FREQ > 0)
+#if (EFR32_HFXO_FREQ > 0U)
ret = SystemHFXOClock;
#else
/* We should not get here, since core should not be clocked. May */
/* be caused by a misconfiguration though. */
- ret = 0;
+ ret = 0U;
#endif
break;
+ case CMU_HFCLKSTATUS_SELECTED_HFRCODIV2:
+ ret = SystemHfrcoFreq / 2;
+ break;
+
default: /* CMU_HFCLKSTATUS_SELECTED_HFRCO */
ret = SystemHfrcoFreq;
break;
@@ -217,8 +220,7 @@ uint32_t SystemHFClockGet(void)
>> _CMU_HFPRESC_PRESC_SHIFT));
}
-
-/**************************************************************************//**
+/***************************************************************************//**
* @brief
* Get high frequency crystal oscillator clock frequency for target system.
*
@@ -227,19 +229,18 @@ uint32_t SystemHFClockGet(void)
*
* @return
* HFXO frequency in Hz.
- *****************************************************************************/
+ ******************************************************************************/
uint32_t SystemHFXOClockGet(void)
{
/* External crystal oscillator present? */
-#if (EFR32_HFXO_FREQ > 0)
+#if (EFR32_HFXO_FREQ > 0U)
return SystemHFXOClock;
#else
- return 0;
+ return 0U;
#endif
}
-
-/**************************************************************************//**
+/***************************************************************************//**
* @brief
* Set high frequency crystal oscillator clock frequency for target system.
*
@@ -253,26 +254,25 @@ uint32_t SystemHFXOClockGet(void)
*
* @param[in] freq
* HFXO frequency in Hz used for target.
- *****************************************************************************/
+ ******************************************************************************/
void SystemHFXOClockSet(uint32_t freq)
{
/* External crystal oscillator present? */
-#if (EFR32_HFXO_FREQ > 0)
+#if (EFR32_HFXO_FREQ > 0U)
SystemHFXOClock = freq;
/* Update core clock frequency if HFXO is used to clock core */
- if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) == CMU_HFCLKSTATUS_SELECTED_HFXO)
- {
+ if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK)
+ == CMU_HFCLKSTATUS_SELECTED_HFXO) {
/* The function will update the global variable */
- SystemCoreClockGet();
+ (void)SystemCoreClockGet();
}
#else
(void)freq; /* Unused parameter */
#endif
}
-
-/**************************************************************************//**
+/***************************************************************************//**
* @brief
* Initialize the system.
*
@@ -283,18 +283,25 @@ void SystemHFXOClockSet(uint32_t freq)
* This function is invoked during system init, before the main() routine
* and any data has been initialized. For this reason, it cannot do any
* initialization of variables etc.
- *****************************************************************************/
+ ******************************************************************************/
void SystemInit(void)
{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t)&__Vectors;
+#endif
+
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
/* Set floating point coprosessor access mode. */
- SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
- (3UL << 11*2) ); /* set CP11 Full Access */
+ SCB->CPACR |= ((3UL << 10 * 2) /* set CP10 Full Access */
+ | (3UL << 11 * 2)); /* set CP11 Full Access */
#endif
-}
+#if defined(UNALIGNED_SUPPORT_DISABLE)
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+}
-/**************************************************************************//**
+/***************************************************************************//**
* @brief
* Get low frequency RC oscillator clock frequency for target system.
*
@@ -303,7 +310,7 @@ void SystemInit(void)
*
* @return
* LFRCO frequency in Hz.
- *****************************************************************************/
+ ******************************************************************************/
uint32_t SystemLFRCOClockGet(void)
{
/* Currently we assume that this frequency is properly tuned during */
@@ -312,8 +319,7 @@ uint32_t SystemLFRCOClockGet(void)
return EFR32_LFRCO_FREQ;
}
-
-/**************************************************************************//**
+/***************************************************************************//**
* @brief
* Get ultra low frequency RC oscillator clock frequency for target system.
*
@@ -322,15 +328,14 @@ uint32_t SystemLFRCOClockGet(void)
*
* @return
* ULFRCO frequency in Hz.
- *****************************************************************************/
+ ******************************************************************************/
uint32_t SystemULFRCOClockGet(void)
{
/* The ULFRCO frequency is not tuned, and can be very inaccurate */
return EFR32_ULFRCO_FREQ;
}
-
-/**************************************************************************//**
+/***************************************************************************//**
* @brief
* Get low frequency crystal oscillator clock frequency for target system.
*
@@ -339,19 +344,18 @@ uint32_t SystemULFRCOClockGet(void)
*
* @return
* LFXO frequency in Hz.
- *****************************************************************************/
+ ******************************************************************************/
uint32_t SystemLFXOClockGet(void)
{
/* External crystal oscillator present? */
-#if (EFR32_LFXO_FREQ > 0)
+#if (EFR32_LFXO_FREQ > 0U)
return SystemLFXOClock;
#else
- return 0;
+ return 0U;
#endif
}
-
-/**************************************************************************//**
+/***************************************************************************//**
* @brief
* Set low frequency crystal oscillator clock frequency for target system.
*
@@ -365,18 +369,18 @@ uint32_t SystemLFXOClockGet(void)
*
* @param[in] freq
* LFXO frequency in Hz used for target.
- *****************************************************************************/
+ ******************************************************************************/
void SystemLFXOClockSet(uint32_t freq)
{
/* External crystal oscillator present? */
-#if (EFR_LFXO_FREQ > 0)
+#if (EFR32_LFXO_FREQ > 0U)
SystemLFXOClock = freq;
/* Update core clock frequency if LFXO is used to clock core */
- if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) == CMU_HFCLKSTATUS_SELECTED_LFXO)
- {
+ if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK)
+ == CMU_HFCLKSTATUS_SELECTED_LFXO) {
/* The function will update the global variable */
- SystemCoreClockGet();
+ (void)SystemCoreClockGet();
}
#else
(void)freq; /* Unused parameter */
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_af_pins.h b/mcu/efr/common/vendor/efr32fg12/efr32fg12p_af_pins.h
deleted file mode 100644
index 11bfd111..00000000
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_af_pins.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg12p_af_pins.h
- * @brief EFR32FG12P_AF_PINS register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_AF_Pins
- * @{
- *****************************************************************************/
-
-/** AF pin number for location number i */
-#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 15 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 7 : -1)
-#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 14 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 10 : (i) == 5 ? 15 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1)
-#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : -1)
-#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : -1)
-#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 0 : -1)
-#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1)
-#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 11 : (i) == 11 ? 12 : (i) == 12 ? 13 : (i) == 13 ? 14 : (i) == 14 ? 15 : -1)
-#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : -1)
-#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 9 : -1)
-#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 12 : (i) == 15 ? 13 : (i) == 16 ? 14 : (i) == 17 ? 15 : -1)
-#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 0 : -1)
-#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 0 : (i) == 10 ? 1 : -1)
-#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 0 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : -1)
-#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 10 : (i) == 5 ? 11 : -1)
-#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 6 : -1)
-#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
-#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)
-#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1)
-#define AF_TIMER0_CC3_PIN(i) (-1)
-#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1)
-#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1)
-#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1)
-#define AF_TIMER0_CDTI3_PIN(i) (-1)
-#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
-#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)
-#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1)
-#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1)
-#define AF_TIMER1_CDTI0_PIN(i) (-1)
-#define AF_TIMER1_CDTI1_PIN(i) (-1)
-#define AF_TIMER1_CDTI2_PIN(i) (-1)
-#define AF_TIMER1_CDTI3_PIN(i) (-1)
-#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1)
-#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 9 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 12 : (i) == 15 ? 13 : (i) == 16 ? 14 : (i) == 17 ? 15 : (i) == 18 ? 0 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 3 : (i) == 22 ? 4 : (i) == 23 ? 5 : (i) == 24 ? 6 : (i) == 25 ? 7 : (i) == 26 ? 8 : (i) == 27 ? 9 : (i) == 28 ? 10 : (i) == 29 ? 11 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1)
-#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 8 : (i) == 5 ? 9 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 12 : (i) == 13 ? 13 : (i) == 14 ? 14 : (i) == 15 ? 15 : (i) == 16 ? 0 : (i) == 17 ? 1 : (i) == 18 ? 2 : (i) == 19 ? 3 : (i) == 20 ? 4 : (i) == 21 ? 5 : (i) == 22 ? 6 : (i) == 23 ? 7 : (i) == 24 ? 8 : (i) == 25 ? 9 : (i) == 26 ? 10 : (i) == 27 ? 11 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1)
-#define AF_WTIMER0_CC3_PIN(i) (-1)
-#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 8 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 11 : (i) == 8 ? 12 : (i) == 9 ? 13 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 6 : (i) == 19 ? 7 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 8 : (i) == 25 ? 9 : (i) == 26 ? 10 : (i) == 27 ? 11 : (i) == 28 ? 12 : (i) == 29 ? 13 : (i) == 30 ? 14 : (i) == 31 ? 15 : -1)
-#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 10 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 0 : (i) == 11 ? 1 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 4 : (i) == 15 ? 5 : (i) == 16 ? 6 : (i) == 17 ? 7 : (i) == 18 ? 8 : (i) == 19 ? 9 : (i) == 20 ? 10 : (i) == 21 ? 11 : (i) == 22 ? 8 : (i) == 23 ? 9 : (i) == 24 ? 10 : (i) == 25 ? 11 : (i) == 26 ? 12 : (i) == 27 ? 13 : (i) == 28 ? 14 : (i) == 29 ? 15 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1)
-#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 0 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 3 : (i) == 12 ? 4 : (i) == 13 ? 5 : (i) == 14 ? 6 : (i) == 15 ? 7 : (i) == 16 ? 8 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1)
-#define AF_WTIMER0_CDTI3_PIN(i) (-1)
-#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 3 : (i) == 8 ? 4 : (i) == 9 ? 5 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 8 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
-#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 5 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 8 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1)
-#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1)
-#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 9 : (i) == 8 ? 10 : (i) == 9 ? 11 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 12 : (i) == 15 ? 13 : (i) == 16 ? 14 : (i) == 17 ? 15 : (i) == 18 ? 0 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 3 : (i) == 22 ? 4 : (i) == 23 ? 5 : (i) == 24 ? 6 : (i) == 25 ? 7 : (i) == 26 ? 8 : (i) == 27 ? 9 : (i) == 28 ? 10 : (i) == 29 ? 11 : (i) == 30 ? 12 : (i) == 31 ? 13 : -1)
-#define AF_WTIMER1_CDTI0_PIN(i) (-1)
-#define AF_WTIMER1_CDTI1_PIN(i) (-1)
-#define AF_WTIMER1_CDTI2_PIN(i) (-1)
-#define AF_WTIMER1_CDTI3_PIN(i) (-1)
-#define AF_USART0_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
-#define AF_USART0_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)
-#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1)
-#define AF_USART0_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1)
-#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1)
-#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1)
-#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
-#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)
-#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1)
-#define AF_USART1_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1)
-#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1)
-#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1)
-#define AF_USART2_TX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 9 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 3 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 0 : (i) == 15 ? 1 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 6 : (i) == 20 ? 7 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1)
-#define AF_USART2_RX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 3 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 6 : (i) == 19 ? 7 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 5 : -1)
-#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 3 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 3 : (i) == 15 ? 4 : (i) == 16 ? 5 : (i) == 17 ? 6 : (i) == 18 ? 7 : (i) == 19 ? 8 : (i) == 20 ? 9 : (i) == 21 ? 10 : (i) == 22 ? 11 : (i) == 23 ? 12 : (i) == 24 ? 13 : (i) == 25 ? 14 : (i) == 26 ? 15 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 5 : (i) == 31 ? 6 : -1)
-#define AF_USART2_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 0 : (i) == 12 ? 1 : (i) == 13 ? 3 : (i) == 14 ? 4 : (i) == 15 ? 5 : (i) == 16 ? 6 : (i) == 17 ? 7 : (i) == 18 ? 8 : (i) == 19 ? 9 : (i) == 20 ? 10 : (i) == 21 ? 11 : (i) == 22 ? 12 : (i) == 23 ? 13 : (i) == 24 ? 14 : (i) == 25 ? 15 : (i) == 26 ? 0 : (i) == 27 ? 1 : (i) == 28 ? 2 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
-#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 0 : (i) == 11 ? 1 : (i) == 12 ? 3 : (i) == 13 ? 4 : (i) == 14 ? 5 : (i) == 15 ? 6 : (i) == 16 ? 7 : (i) == 17 ? 8 : (i) == 18 ? 9 : (i) == 19 ? 10 : (i) == 20 ? 11 : (i) == 21 ? 12 : (i) == 22 ? 13 : (i) == 23 ? 14 : (i) == 24 ? 15 : (i) == 25 ? 0 : (i) == 26 ? 1 : (i) == 27 ? 2 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 8 : -1)
-#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 9 : (i) == 8 ? 10 : (i) == 9 ? 0 : (i) == 10 ? 1 : (i) == 11 ? 3 : (i) == 12 ? 4 : (i) == 13 ? 5 : (i) == 14 ? 6 : (i) == 15 ? 7 : (i) == 16 ? 8 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1)
-#define AF_USART3_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 2 : (i) == 9 ? 3 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 14 : (i) == 17 ? 15 : (i) == 18 ? 0 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 3 : (i) == 22 ? 4 : (i) == 23 ? 5 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1)
-#define AF_USART3_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 2 : (i) == 8 ? 3 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 14 : (i) == 16 ? 15 : (i) == 17 ? 0 : (i) == 18 ? 1 : (i) == 19 ? 2 : (i) == 20 ? 3 : (i) == 21 ? 4 : (i) == 22 ? 5 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 8 : -1)
-#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 2 : (i) == 7 ? 3 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 14 : (i) == 15 ? 15 : (i) == 16 ? 0 : (i) == 17 ? 1 : (i) == 18 ? 2 : (i) == 19 ? 3 : (i) == 20 ? 4 : (i) == 21 ? 5 : (i) == 22 ? 11 : (i) == 23 ? 12 : (i) == 24 ? 13 : (i) == 25 ? 14 : (i) == 26 ? 15 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1)
-#define AF_USART3_CS_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 13 : (i) == 3 ? 14 : (i) == 4 ? 15 : (i) == 5 ? 2 : (i) == 6 ? 3 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 14 : (i) == 14 ? 15 : (i) == 15 ? 0 : (i) == 16 ? 1 : (i) == 17 ? 2 : (i) == 18 ? 3 : (i) == 19 ? 4 : (i) == 20 ? 5 : (i) == 21 ? 11 : (i) == 22 ? 12 : (i) == 23 ? 13 : (i) == 24 ? 14 : (i) == 25 ? 15 : (i) == 26 ? 0 : (i) == 27 ? 1 : (i) == 28 ? 2 : (i) == 29 ? 8 : (i) == 30 ? 9 : (i) == 31 ? 10 : -1)
-#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 14 : (i) == 13 ? 15 : (i) == 14 ? 0 : (i) == 15 ? 1 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 4 : (i) == 19 ? 5 : (i) == 20 ? 11 : (i) == 21 ? 12 : (i) == 22 ? 13 : (i) == 23 ? 14 : (i) == 24 ? 15 : (i) == 25 ? 0 : (i) == 26 ? 1 : (i) == 27 ? 2 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1)
-#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 11 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 8 : (i) == 28 ? 9 : (i) == 29 ? 10 : (i) == 30 ? 11 : (i) == 31 ? 12 : -1)
-#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
-#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)
-#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
-#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)
-#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
-#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)
-#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 6 : (i) == 20 ? 7 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1)
-#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 6 : (i) == 19 ? 7 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 6 : -1)
-#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 10 : (i) == 20 ? 11 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1)
-#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 6 : -1)
-#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
-#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)
-#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 10 : (i) == 20 ? 11 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1)
-#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 6 : -1)
-#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
-#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
-#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 8 : -1)
-#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 9 : -1)
-#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 10 : -1)
-#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 11 : -1)
-#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 12 : -1)
-#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 13 : -1)
-#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 14 : -1)
-#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 15 : -1)
-#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 0 : -1)
-#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 1 : -1)
-#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 2 : -1)
-#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 3 : -1)
-#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 4 : -1)
-#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 5 : -1)
-#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 6 : -1)
-#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 7 : -1)
-#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 8 : -1)
-#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 9 : -1)
-#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 14 : -1)
-#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 15 : -1)
-#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 0 : -1)
-#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 1 : -1)
-#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 2 : -1)
-#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 3 : -1)
-#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 3 : -1)
-#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1)
-#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 11 : -1)
-#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1)
-#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1)
-#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 6 : -1)
-#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 7 : -1)
-#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 8 : -1)
-#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 9 : -1)
-#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 8 : (i) == 3 ? 10 : -1)
-
-/** @} End of group EFR32FG12P_AF_Pins */
-/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_af_ports.h b/mcu/efr/common/vendor/efr32fg12/efr32fg12p_af_ports.h
deleted file mode 100644
index a78c72c5..00000000
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_af_ports.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg12p_af_ports.h
- * @brief EFR32FG12P_AF_PORTS register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_AF_Ports
- * @{
- *****************************************************************************/
-
-/** AF port number for location number i */
-#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1)
-#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1)
-#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 0 : -1)
-#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : -1)
-#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1)
-#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1)
-#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : (i) == 8 ? 3 : (i) == 9 ? 3 : (i) == 10 ? 3 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : -1)
-#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : -1)
-#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : -1)
-#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : -1)
-#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 0 : -1)
-#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 0 : (i) == 10 ? 0 : -1)
-#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 0 : (i) == 9 ? 0 : (i) == 10 ? 0 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : -1)
-#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1)
-#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1)
-#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
-#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)
-#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
-#define AF_TIMER0_CC3_PORT(i) (-1)
-#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
-#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
-#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
-#define AF_TIMER0_CDTI3_PORT(i) (-1)
-#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
-#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)
-#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
-#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
-#define AF_TIMER1_CDTI0_PORT(i) (-1)
-#define AF_TIMER1_CDTI1_PORT(i) (-1)
-#define AF_TIMER1_CDTI2_PORT(i) (-1)
-#define AF_TIMER1_CDTI3_PORT(i) (-1)
-#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : (i) == 8 ? 0 : (i) == 9 ? 0 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 1 : (i) == 17 ? 1 : (i) == 18 ? 1 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 2 : (i) == 25 ? 2 : (i) == 26 ? 2 : (i) == 27 ? 2 : (i) == 28 ? 2 : (i) == 29 ? 2 : (i) == 30 ? 2 : (i) == 31 ? 2 : -1)
-#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 1 : (i) == 17 ? 1 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 2 : (i) == 25 ? 2 : (i) == 26 ? 2 : (i) == 27 ? 2 : (i) == 28 ? 2 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1)
-#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 2 : (i) == 25 ? 2 : (i) == 26 ? 2 : (i) == 27 ? 2 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1)
-#define AF_WTIMER0_CC3_PORT(i) (-1)
-#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 3 : (i) == 26 ? 3 : (i) == 27 ? 3 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1)
-#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 3 : (i) == 25 ? 3 : (i) == 26 ? 3 : (i) == 27 ? 3 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
-#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 3 : (i) == 25 ? 3 : (i) == 26 ? 3 : (i) == 27 ? 3 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
-#define AF_WTIMER0_CDTI3_PORT(i) (-1)
-#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
-#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
-#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
-#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 3 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
-#define AF_WTIMER1_CDTI0_PORT(i) (-1)
-#define AF_WTIMER1_CDTI1_PORT(i) (-1)
-#define AF_WTIMER1_CDTI2_PORT(i) (-1)
-#define AF_WTIMER1_CDTI3_PORT(i) (-1)
-#define AF_USART0_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
-#define AF_USART0_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)
-#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
-#define AF_USART0_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
-#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
-#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
-#define AF_USART1_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
-#define AF_USART1_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)
-#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
-#define AF_USART1_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
-#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
-#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
-#define AF_USART2_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 8 : (i) == 8 ? 8 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1)
-#define AF_USART2_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 8 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1)
-#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
-#define AF_USART2_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 5 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
-#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 5 : (i) == 11 ? 5 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
-#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 8 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 5 : (i) == 10 ? 5 : (i) == 11 ? 5 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 10 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
-#define AF_USART3_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : (i) == 8 ? 8 : (i) == 9 ? 8 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 9 : (i) == 17 ? 9 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1)
-#define AF_USART3_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 8 : (i) == 8 ? 8 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 9 : (i) == 16 ? 9 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 3 : -1)
-#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 8 : (i) == 7 ? 8 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 9 : (i) == 15 ? 9 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1)
-#define AF_USART3_CS_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 9 : (i) == 14 ? 9 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1)
-#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 9 : (i) == 13 ? 9 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1)
-#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 10 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 3 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1)
-#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
-#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)
-#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
-#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)
-#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
-#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)
-#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1)
-#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 9 : (i) == 11 ? 9 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1)
-#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1)
-#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 9 : (i) == 11 ? 9 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1)
-#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
-#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)
-#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1)
-#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 9 : (i) == 11 ? 9 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1)
-#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
-#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
-#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 3 : -1)
-#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 3 : -1)
-#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 3 : -1)
-#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 3 : -1)
-#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 3 : -1)
-#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 3 : -1)
-#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 3 : -1)
-#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 3 : -1)
-#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 0 : -1)
-#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 0 : -1)
-#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 0 : -1)
-#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 0 : -1)
-#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 0 : -1)
-#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 0 : -1)
-#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 0 : -1)
-#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 0 : -1)
-#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 0 : -1)
-#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 0 : -1)
-#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 9 : -1)
-#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 9 : -1)
-#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 8 : -1)
-#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 8 : -1)
-#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 8 : -1)
-#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 8 : -1)
-#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1)
-#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1)
-#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : -1)
-#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1)
-#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1)
-#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 8 : (i) == 3 ? 2 : -1)
-#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 8 : (i) == 3 ? 2 : -1)
-#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1)
-#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1)
-#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1)
-
-/** @} End of group EFR32FG12P_AF_Ports */
-/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_gpio_p.h b/mcu/efr/common/vendor/efr32fg12/efr32fg12p_gpio_p.h
deleted file mode 100644
index 930454b8..00000000
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_gpio_p.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg12p_gpio_p.h
- * @brief EFR32FG12P_GPIO_P register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @brief GPIO_P EFR32FG12P GPIO P
- *****************************************************************************/
-typedef struct
-{
- __IOM uint32_t CTRL; /**< Port Control Register */
- __IOM uint32_t MODEL; /**< Port Pin Mode Low Register */
- __IOM uint32_t MODEH; /**< Port Pin Mode High Register */
- __IOM uint32_t DOUT; /**< Port Data Out Register */
- uint32_t RESERVED0[2]; /**< Reserved for future use **/
- __IOM uint32_t DOUTTGL; /**< Port Data Out Toggle Register */
- __IM uint32_t DIN; /**< Port Data In Register */
- __IOM uint32_t PINLOCKN; /**< Port Unlocked Pins Register */
- uint32_t RESERVED1[1]; /**< Reserved for future use **/
- __IOM uint32_t OVTDIS; /**< Over Voltage Disable for all modes */
- uint32_t RESERVED2[1]; /**< Reserved future */
-} GPIO_P_TypeDef;
-
-/** @} End of group Parts */
-
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_ldma_ch.h b/mcu/efr/common/vendor/efr32fg12/efr32fg12p_ldma_ch.h
deleted file mode 100644
index ddf030c3..00000000
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_ldma_ch.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg12p_ldma_ch.h
- * @brief EFR32FG12P_LDMA_CH register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @brief LDMA_CH EFR32FG12P LDMA CH
- *****************************************************************************/
-typedef struct
-{
- __IOM uint32_t REQSEL; /**< Channel Peripheral Request Select Register */
- __IOM uint32_t CFG; /**< Channel Configuration Register */
- __IOM uint32_t LOOP; /**< Channel Loop Counter Register */
- __IOM uint32_t CTRL; /**< Channel Descriptor Control Word Register */
- __IOM uint32_t SRC; /**< Channel Descriptor Source Data Address Register */
- __IOM uint32_t DST; /**< Channel Descriptor Destination Data Address Register */
- __IOM uint32_t LINK; /**< Channel Descriptor Link Structure Address Register */
- uint32_t RESERVED0[5]; /**< Reserved future */
-} LDMA_CH_TypeDef;
-
-/** @} End of group Parts */
-
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_lesense_buf.h b/mcu/efr/common/vendor/efr32fg12/efr32fg12p_lesense_buf.h
deleted file mode 100644
index d47a874d..00000000
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_lesense_buf.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg12p_lesense_buf.h
- * @brief EFR32FG12P_LESENSE_BUF register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @brief LESENSE_BUF EFR32FG12P LESENSE BUF
- *****************************************************************************/
-typedef struct
-{
- __IOM uint32_t DATA; /**< Scan results */
-} LESENSE_BUF_TypeDef;
-
-/** @} End of group Parts */
-
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_lesense_ch.h b/mcu/efr/common/vendor/efr32fg12/efr32fg12p_lesense_ch.h
deleted file mode 100644
index 068c8aa3..00000000
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_lesense_ch.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg12p_lesense_ch.h
- * @brief EFR32FG12P_LESENSE_CH register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @brief LESENSE_CH EFR32FG12P LESENSE CH
- *****************************************************************************/
-typedef struct
-{
- __IOM uint32_t TIMING; /**< Scan configuration */
- __IOM uint32_t INTERACT; /**< Scan configuration */
- __IOM uint32_t EVAL; /**< Scan configuration */
- uint32_t RESERVED0[1]; /**< Reserved future */
-} LESENSE_CH_TypeDef;
-
-/** @} End of group Parts */
-
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_lesense_st.h b/mcu/efr/common/vendor/efr32fg12/efr32fg12p_lesense_st.h
deleted file mode 100644
index e87bc680..00000000
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_lesense_st.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg12p_lesense_st.h
- * @brief EFR32FG12P_LESENSE_ST register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @brief LESENSE_ST EFR32FG12P LESENSE ST
- *****************************************************************************/
-typedef struct
-{
- __IOM uint32_t TCONFA; /**< State transition configuration A */
- __IOM uint32_t TCONFB; /**< State transition configuration B */
-} LESENSE_ST_TypeDef;
-
-/** @} End of group Parts */
-
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_romtable.h b/mcu/efr/common/vendor/efr32fg12/efr32fg12p_romtable.h
deleted file mode 100644
index fc53cdcf..00000000
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_romtable.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg12p_romtable.h
- * @brief EFR32FG12P_ROMTABLE register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG12P_ROMTABLE
- * @{
- * @brief Chip Information, Revision numbers
- *****************************************************************************/
-typedef struct
-{
- __IM uint32_t PID4; /**< JEP_106_BANK */
- __IM uint32_t PID5; /**< Unused */
- __IM uint32_t PID6; /**< Unused */
- __IM uint32_t PID7; /**< Unused */
- __IM uint32_t PID0; /**< Chip family LSB, chip major revision */
- __IM uint32_t PID1; /**< JEP_106_NO, Chip family MSB */
- __IM uint32_t PID2; /**< Chip minor rev MSB, JEP_106_PRESENT, JEP_106_NO */
- __IM uint32_t PID3; /**< Chip minor rev LSB */
- __IM uint32_t CID0; /**< Unused */
-} ROMTABLE_TypeDef; /** @} */
-
-/**************************************************************************//**
- * @defgroup EFR32FG12P_ROMTABLE_BitFields
- * @{
- *****************************************************************************/
-/* Bit fields for EFR32FG12P_ROMTABLE */
-#define _ROMTABLE_PID0_FAMILYLSB_MASK 0x000000C0UL /**< Least Significant Bits [1:0] of CHIP FAMILY, mask */
-#define _ROMTABLE_PID0_FAMILYLSB_SHIFT 6 /**< Least Significant Bits [1:0] of CHIP FAMILY, shift */
-#define _ROMTABLE_PID0_REVMAJOR_MASK 0x0000003FUL /**< CHIP MAJOR Revison, mask */
-#define _ROMTABLE_PID0_REVMAJOR_SHIFT 0 /**< CHIP MAJOR Revison, shift */
-#define _ROMTABLE_PID1_FAMILYMSB_MASK 0x0000000FUL /**< Most Significant Bits [5:2] of CHIP FAMILY, mask */
-#define _ROMTABLE_PID1_FAMILYMSB_SHIFT 0 /**< Most Significant Bits [5:2] of CHIP FAMILY, shift */
-#define _ROMTABLE_PID2_REVMINORMSB_MASK 0x000000F0UL /**< Most Significant Bits [7:4] of CHIP MINOR revision, mask */
-#define _ROMTABLE_PID2_REVMINORMSB_SHIFT 4 /**< Most Significant Bits [7:4] of CHIP MINOR revision, mask */
-#define _ROMTABLE_PID3_REVMINORLSB_MASK 0x000000F0UL /**< Least Significant Bits [3:0] of CHIP MINOR revision, mask */
-#define _ROMTABLE_PID3_REVMINORLSB_SHIFT 4 /**< Least Significant Bits [3:0] of CHIP MINOR revision, shift */
-
-/** @} End of group EFR32FG12P_ROMTABLE */
-/** @} End of group Parts */
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_rtcc_cc.h b/mcu/efr/common/vendor/efr32fg12/efr32fg12p_rtcc_cc.h
deleted file mode 100644
index 594efaa4..00000000
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_rtcc_cc.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg12p_rtcc_cc.h
- * @brief EFR32FG12P_RTCC_CC register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @brief RTCC_CC EFR32FG12P RTCC CC
- *****************************************************************************/
-typedef struct
-{
- __IOM uint32_t CTRL; /**< CC Channel Control Register */
- __IOM uint32_t CCV; /**< Capture/Compare Value Register */
- __IOM uint32_t TIME; /**< Capture/Compare Time Register */
- __IOM uint32_t DATE; /**< Capture/Compare Date Register */
-} RTCC_CC_TypeDef;
-
-/** @} End of group Parts */
-
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_rtcc_ret.h b/mcu/efr/common/vendor/efr32fg12/efr32fg12p_rtcc_ret.h
deleted file mode 100644
index c80063c9..00000000
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_rtcc_ret.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg12p_rtcc_ret.h
- * @brief EFR32FG12P_RTCC_RET register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @brief RTCC_RET EFR32FG12P RTCC RET
- *****************************************************************************/
-typedef struct
-{
- __IOM uint32_t REG; /**< Retention register */
-} RTCC_RET_TypeDef;
-
-/** @} End of group Parts */
-
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_timer_cc.h b/mcu/efr/common/vendor/efr32fg12/efr32fg12p_timer_cc.h
deleted file mode 100644
index 6747b794..00000000
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_timer_cc.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg12p_timer_cc.h
- * @brief EFR32FG12P_TIMER_CC register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @brief TIMER_CC EFR32FG12P TIMER CC
- *****************************************************************************/
-typedef struct
-{
- __IOM uint32_t CTRL; /**< CC Channel Control Register */
- __IOM uint32_t CCV; /**< CC Channel Value Register */
- __IM uint32_t CCVP; /**< CC Channel Value Peek Register */
- __IOM uint32_t CCVB; /**< CC Channel Buffer Register */
-} TIMER_CC_TypeDef;
-
-/** @} End of group Parts */
-
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_vdac_opa.h b/mcu/efr/common/vendor/efr32fg12/efr32fg12p_vdac_opa.h
deleted file mode 100644
index 8e243dae..00000000
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_vdac_opa.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg12p_vdac_opa.h
- * @brief EFR32FG12P_VDAC_OPA register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @brief VDAC_OPA EFR32FG12P VDAC OPA
- *****************************************************************************/
-typedef struct
-{
- __IM uint32_t APORTREQ; /**< Operational Amplifier APORT Request Status Register */
- __IM uint32_t APORTCONFLICT; /**< Operational Amplifier APORT Conflict Status Register */
- __IOM uint32_t CTRL; /**< Operational Amplifier Control Register */
- __IOM uint32_t TIMER; /**< Operational Amplifier Timer Control Register */
- __IOM uint32_t MUX; /**< Operational Amplifier Mux Configuration Register */
- __IOM uint32_t OUT; /**< Operational Amplifier Output Configuration Register */
- __IOM uint32_t CAL; /**< Operational Amplifier Calibration Register */
- uint32_t RESERVED0[1]; /**< Reserved future */
-} VDAC_OPA_TypeDef;
-
-/** @} End of group Parts */
-
-
diff --git a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_wdog_pch.h b/mcu/efr/common/vendor/efr32fg12/efr32fg12p_wdog_pch.h
deleted file mode 100644
index 563fd4fe..00000000
--- a/mcu/efr/common/vendor/efr32fg12/efr32fg12p_wdog_pch.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg12p_wdog_pch.h
- * @brief EFR32FG12P_WDOG_PCH register and bit field definitions
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @brief WDOG_PCH EFR32FG12P WDOG PCH
- *****************************************************************************/
-typedef struct
-{
- __IOM uint32_t PRSCTRL; /**< PRS Control Register */
-} WDOG_PCH_TypeDef;
-
-/** @} End of group Parts */
-
-
diff --git a/mcu/efr/common/vendor/efr32fg12/system_efr32fg12p.h b/mcu/efr/common/vendor/efr32fg12/system_efr32fg12p.h
deleted file mode 100644
index ad7ea518..00000000
--- a/mcu/efr/common/vendor/efr32fg12/system_efr32fg12p.h
+++ /dev/null
@@ -1,154 +0,0 @@
-/***************************************************************************//**
- * @file system_efr32fg12p.h
- * @brief CMSIS Cortex-M3/M4 System Layer for EFR32 devices.
- * @version 5.1.3
- ******************************************************************************
- * @section License
- * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#ifndef SYSTEM_EFR32_H
-#define SYSTEM_EFR32_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include
-
-/*******************************************************************************
- ************************** GLOBAL VARIABLES *******************************
- ******************************************************************************/
-
-extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */
-extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */
-
-/*******************************************************************************
- ***************************** PROTOTYPES **********************************
- ******************************************************************************/
-
-void Reset_Handler(void);
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-void EMU_IRQHandler(void);
-void FRC_PRI_IRQHandler(void);
-void WDOG0_IRQHandler(void);
-void WDOG1_IRQHandler(void);
-void FRC_IRQHandler(void);
-void MODEM_IRQHandler(void);
-void RAC_SEQ_IRQHandler(void);
-void RAC_RSM_IRQHandler(void);
-void BUFC_IRQHandler(void);
-void LDMA_IRQHandler(void);
-void GPIO_EVEN_IRQHandler(void);
-void TIMER0_IRQHandler(void);
-void USART0_RX_IRQHandler(void);
-void USART0_TX_IRQHandler(void);
-void ACMP0_IRQHandler(void);
-void ADC0_IRQHandler(void);
-void IDAC0_IRQHandler(void);
-void I2C0_IRQHandler(void);
-void GPIO_ODD_IRQHandler(void);
-void TIMER1_IRQHandler(void);
-void USART1_RX_IRQHandler(void);
-void USART1_TX_IRQHandler(void);
-void LEUART0_IRQHandler(void);
-void PCNT0_IRQHandler(void);
-void CMU_IRQHandler(void);
-void MSC_IRQHandler(void);
-void CRYPTO0_IRQHandler(void);
-void LETIMER0_IRQHandler(void);
-void AGC_IRQHandler(void);
-void PROTIMER_IRQHandler(void);
-void RTCC_IRQHandler(void);
-void SYNTH_IRQHandler(void);
-void CRYOTIMER_IRQHandler(void);
-void RFSENSE_IRQHandler(void);
-void FPUEH_IRQHandler(void);
-void SMU_IRQHandler(void);
-void WTIMER0_IRQHandler(void);
-void WTIMER1_IRQHandler(void);
-void PCNT1_IRQHandler(void);
-void PCNT2_IRQHandler(void);
-void USART2_RX_IRQHandler(void);
-void USART2_TX_IRQHandler(void);
-void I2C1_IRQHandler(void);
-void USART3_RX_IRQHandler(void);
-void USART3_TX_IRQHandler(void);
-void VDAC0_IRQHandler(void);
-void CSEN_IRQHandler(void);
-void LESENSE_IRQHandler(void);
-void CRYPTO1_IRQHandler(void);
-void TRNG0_IRQHandler(void);
-void SYSCFG_IRQHandler(void);
-
-uint32_t SystemCoreClockGet(void);
-
-/**************************************************************************//**
- * @brief
- * Update CMSIS SystemCoreClock variable.
- *
- * @details
- * CMSIS defines a global variable SystemCoreClock that shall hold the
- * core frequency in Hz. If the core frequency is dynamically changed, the
- * variable must be kept updated in order to be CMSIS compliant.
- *
- * Notice that only if changing the core clock frequency through the EFR CMU
- * API, this variable will be kept updated. This function is only provided
- * for CMSIS compliance and if a user modifies the the core clock outside
- * the CMU API.
- *****************************************************************************/
-static __INLINE void SystemCoreClockUpdate(void)
-{
- SystemCoreClockGet();
-}
-
-uint32_t SystemMaxCoreClockGet(void);
-
-void SystemInit(void);
-uint32_t SystemHFClockGet(void);
-
-uint32_t SystemHFXOClockGet(void);
-void SystemHFXOClockSet(uint32_t freq);
-
-uint32_t SystemLFRCOClockGet(void);
-uint32_t SystemULFRCOClockGet(void);
-
-uint32_t SystemLFXOClockGet(void);
-void SystemLFXOClockSet(uint32_t freq);
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* SYSTEM_EFR32_H */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p232f512gm32.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p232f512gm32.h
deleted file mode 100644
index 672906ae..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p232f512gm32.h
+++ /dev/null
@@ -1,2039 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p232f512gm32.h
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File
- * for EFR32FG13P232F512GM32
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-#ifndef EFR32FG13P232F512GM32_H
-#define EFR32FG13P232F512GM32_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**************************************************************************//**
- * @addtogroup Parts
- * @{
- *****************************************************************************/
-
-/**************************************************************************//**
- * @defgroup EFR32FG13P232F512GM32 EFR32FG13P232F512GM32
- * @{
- *****************************************************************************/
-
-/** Interrupt Number Definition */
-typedef enum IRQn{
-/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
- HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
-
-/****** EFR32FG13P Peripheral Interrupt Numbers ********************************************/
-
- EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
- WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
- WDOG1_IRQn = 3, /*!< 16+3 EFR32 WDOG1 Interrupt */
- LDMA_IRQn = 9, /*!< 16+9 EFR32 LDMA Interrupt */
- GPIO_EVEN_IRQn = 10, /*!< 16+10 EFR32 GPIO_EVEN Interrupt */
- TIMER0_IRQn = 11, /*!< 16+11 EFR32 TIMER0 Interrupt */
- USART0_RX_IRQn = 12, /*!< 16+12 EFR32 USART0_RX Interrupt */
- USART0_TX_IRQn = 13, /*!< 16+13 EFR32 USART0_TX Interrupt */
- ACMP0_IRQn = 14, /*!< 16+14 EFR32 ACMP0 Interrupt */
- ADC0_IRQn = 15, /*!< 16+15 EFR32 ADC0 Interrupt */
- IDAC0_IRQn = 16, /*!< 16+16 EFR32 IDAC0 Interrupt */
- I2C0_IRQn = 17, /*!< 16+17 EFR32 I2C0 Interrupt */
- GPIO_ODD_IRQn = 18, /*!< 16+18 EFR32 GPIO_ODD Interrupt */
- TIMER1_IRQn = 19, /*!< 16+19 EFR32 TIMER1 Interrupt */
- USART1_RX_IRQn = 20, /*!< 16+20 EFR32 USART1_RX Interrupt */
- USART1_TX_IRQn = 21, /*!< 16+21 EFR32 USART1_TX Interrupt */
- LEUART0_IRQn = 22, /*!< 16+22 EFR32 LEUART0 Interrupt */
- PCNT0_IRQn = 23, /*!< 16+23 EFR32 PCNT0 Interrupt */
- CMU_IRQn = 24, /*!< 16+24 EFR32 CMU Interrupt */
- MSC_IRQn = 25, /*!< 16+25 EFR32 MSC Interrupt */
- CRYPTO0_IRQn = 26, /*!< 16+26 EFR32 CRYPTO0 Interrupt */
- LETIMER0_IRQn = 27, /*!< 16+27 EFR32 LETIMER0 Interrupt */
- RTCC_IRQn = 31, /*!< 16+31 EFR32 RTCC Interrupt */
- CRYOTIMER_IRQn = 33, /*!< 16+33 EFR32 CRYOTIMER Interrupt */
- FPUEH_IRQn = 35, /*!< 16+35 EFR32 FPUEH Interrupt */
- SMU_IRQn = 36, /*!< 16+36 EFR32 SMU Interrupt */
- WTIMER0_IRQn = 37, /*!< 16+37 EFR32 WTIMER0 Interrupt */
- USART2_RX_IRQn = 38, /*!< 16+38 EFR32 USART2_RX Interrupt */
- USART2_TX_IRQn = 39, /*!< 16+39 EFR32 USART2_TX Interrupt */
- I2C1_IRQn = 40, /*!< 16+40 EFR32 I2C1 Interrupt */
- VDAC0_IRQn = 41, /*!< 16+41 EFR32 VDAC0 Interrupt */
- CSEN_IRQn = 42, /*!< 16+42 EFR32 CSEN Interrupt */
- LESENSE_IRQn = 43, /*!< 16+43 EFR32 LESENSE Interrupt */
- CRYPTO1_IRQn = 44, /*!< 16+44 EFR32 CRYPTO1 Interrupt */
- TRNG0_IRQn = 45, /*!< 16+45 EFR32 TRNG0 Interrupt */
-} IRQn_Type;
-
-#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */
-
-/**************************************************************************//**
- * @defgroup EFR32FG13P232F512GM32_Core Core
- * @{
- * @brief Processor and Core Peripheral Section
- *****************************************************************************/
-#define __MPU_PRESENT 1 /**< Presence of MPU */
-#define __FPU_PRESENT 1 /**< Presence of FPU */
-#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
-
-/** @} End of group EFR32FG13P232F512GM32_Core */
-
-/**************************************************************************//**
-* @defgroup EFR32FG13P232F512GM32_Part Part
-* @{
-******************************************************************************/
-
-/** Part family */
-#define _EFR32_FLEX_FAMILY 1 /**< FLEX Gecko RF SoC Family */
-#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
-#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
-#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG_3 /**< Series 1, Configuration 3 */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG 3 /**< Series 1, Configuration 3 */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID 89 /**< Silicon Labs internal use only, may change any time */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID_89 /**< Silicon Labs internal use only, may change any time */
-#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
-#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
-#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
-#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /**< Radio type */
-#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
-#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN_3 /**< @deprecated Platform 2, generation 3 */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN 3 /**< @deprecated Platform 2, generation 3 */
-
-/* If part number is not defined as compiler option, define it */
-#if !defined(EFR32FG13P232F512GM32)
-#define EFR32FG13P232F512GM32 1 /**< FLEX Gecko Part */
-#endif
-
-/** Configure part number */
-#define PART_NUMBER "EFR32FG13P232F512GM32" /**< Part Number */
-
-/** Memory Base addresses and limits */
-#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */
-#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM0_CODE available address space */
-#define RAM0_CODE_MEM_END ((uint32_t) 0x10007FFFUL) /**< RAM0_CODE end address */
-#define RAM0_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM0_CODE used bits */
-#define RAM2_MEM_BASE ((uint32_t) 0x20010000UL) /**< RAM2 base address */
-#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */
-#define RAM2_MEM_END ((uint32_t) 0x200107FFUL) /**< RAM2 end address */
-#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */
-#define RAM1_MEM_BASE ((uint32_t) 0x20008000UL) /**< RAM1 base address */
-#define RAM1_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM1 available address space */
-#define RAM1_MEM_END ((uint32_t) 0x2000FFFFUL) /**< RAM1 end address */
-#define RAM1_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM1 used bits */
-#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */
-#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */
-#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
-#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
-#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */
-#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */
-#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */
-#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10008000UL) /**< RAM1_CODE base address */
-#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM1_CODE available address space */
-#define RAM1_CODE_MEM_END ((uint32_t) 0x1000FFFFUL) /**< RAM1_CODE end address */
-#define RAM1_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM1_CODE used bits */
-#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */
-#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */
-#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */
-#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */
-#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
-#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
-#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */
-#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */
-#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */
-#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */
-#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */
-#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
-#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
-#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
-#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
-#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
-#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */
-#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */
-#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */
-#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */
-#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */
-#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */
-#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */
-#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
-#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
-#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
-#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
-#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */
-#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */
-#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
-#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
-#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
-#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
-#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
-#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
-#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
-#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */
-#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */
-#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */
-#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */
-#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */
-#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */
-#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */
-#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10010000UL) /**< RAM2_CODE base address */
-#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */
-#define RAM2_CODE_MEM_END ((uint32_t) 0x100107FFUL) /**< RAM2_CODE end address */
-#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
-#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
-#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
-#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */
-
-/** Bit banding area */
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
-
-/** Flash and SRAM limits for EFR32FG13P232F512GM32 */
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
-#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */
-#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
-#define SRAM_SIZE (0x00010000UL) /**< Available SRAM Memory */
-#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
-#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
-#define EXT_IRQ_COUNT 47 /**< Number of External (NVIC) interrupts */
-
-/** AF channels connect the different on-chip peripherals with the af-mux */
-#define AFCHAN_MAX 118U
-/** AF channel maximum location number */
-#define AFCHANLOC_MAX 32U
-/** Analog AF channels */
-#define AFACHAN_MAX 118U
-
-/* Part number capabilities */
-
-#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
-#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */
-#define TIMER_PRESENT /**< TIMER is available in this part */
-#define TIMER_COUNT 2 /**< 2 TIMERs available */
-#define WTIMER_PRESENT /**< WTIMER is available in this part */
-#define WTIMER_COUNT 1 /**< 1 WTIMERs available */
-#define USART_PRESENT /**< USART is available in this part */
-#define USART_COUNT 3 /**< 3 USARTs available */
-#define LEUART_PRESENT /**< LEUART is available in this part */
-#define LEUART_COUNT 1 /**< 1 LEUARTs available */
-#define LETIMER_PRESENT /**< LETIMER is available in this part */
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
-#define PCNT_PRESENT /**< PCNT is available in this part */
-#define PCNT_COUNT 1 /**< 1 PCNTs available */
-#define I2C_PRESENT /**< I2C is available in this part */
-#define I2C_COUNT 2 /**< 2 I2Cs available */
-#define ADC_PRESENT /**< ADC is available in this part */
-#define ADC_COUNT 1 /**< 1 ADCs available */
-#define ACMP_PRESENT /**< ACMP is available in this part */
-#define ACMP_COUNT 2 /**< 2 ACMPs available */
-#define VDAC_PRESENT /**< VDAC is available in this part */
-#define VDAC_COUNT 1 /**< 1 VDACs available */
-#define WDOG_PRESENT /**< WDOG is available in this part */
-#define WDOG_COUNT 2 /**< 2 WDOGs available */
-#define IDAC_PRESENT /**< IDAC is available in this part */
-#define IDAC_COUNT 1 /**< 1 IDACs available */
-#define TRNG_PRESENT /**< TRNG is available in this part */
-#define TRNG_COUNT 1 /**< 1 TRNGs available */
-#define MSC_PRESENT /**< MSC is available in this part */
-#define MSC_COUNT 1 /**< 1 MSC available */
-#define EMU_PRESENT /**< EMU is available in this part */
-#define EMU_COUNT 1 /**< 1 EMU available */
-#define RMU_PRESENT /**< RMU is available in this part */
-#define RMU_COUNT 1 /**< 1 RMU available */
-#define CMU_PRESENT /**< CMU is available in this part */
-#define CMU_COUNT 1 /**< 1 CMU available */
-#define GPIO_PRESENT /**< GPIO is available in this part */
-#define GPIO_COUNT 1 /**< 1 GPIO available */
-#define PRS_PRESENT /**< PRS is available in this part */
-#define PRS_COUNT 1 /**< 1 PRS available */
-#define LDMA_PRESENT /**< LDMA is available in this part */
-#define LDMA_COUNT 1 /**< 1 LDMA available */
-#define FPUEH_PRESENT /**< FPUEH is available in this part */
-#define FPUEH_COUNT 1 /**< 1 FPUEH available */
-#define GPCRC_PRESENT /**< GPCRC is available in this part */
-#define GPCRC_COUNT 1 /**< 1 GPCRC available */
-#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
-#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
-#define CSEN_PRESENT /**< CSEN is available in this part */
-#define CSEN_COUNT 1 /**< 1 CSEN available */
-#define LESENSE_PRESENT /**< LESENSE is available in this part */
-#define LESENSE_COUNT 1 /**< 1 LESENSE available */
-#define RTCC_PRESENT /**< RTCC is available in this part */
-#define RTCC_COUNT 1 /**< 1 RTCC available */
-#define ETM_PRESENT /**< ETM is available in this part */
-#define ETM_COUNT 1 /**< 1 ETM available */
-#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
-#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
-#define SMU_PRESENT /**< SMU is available in this part */
-#define SMU_COUNT 1 /**< 1 SMU available */
-#define DCDC_PRESENT /**< DCDC is available in this part */
-#define DCDC_COUNT 1 /**< 1 DCDC available */
-
-#include "../../../efr32/cmsis/core_cm4.h" /* Cortex-M4 processor and core peripherals */
-#include "../../../efr32/vendor/efr32fg13/system_efr32fg13p.h" /* System Header File */
-
-/** @} End of group EFR32FG13P232F512GM32_Part */
-
-/**************************************************************************//**
- * @defgroup EFR32FG13P232F512GM32_Peripheral_TypeDefs Peripheral TypeDefs
- * @{
- * @brief Device Specific Peripheral Register Structures
- *****************************************************************************/
-
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_msc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_emu.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_rmu.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_cmu.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_crypto.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_gpio_p.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_gpio.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_prs_ch.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_prs.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_ldma_ch.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_ldma.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_fpueh.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_gpcrc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_timer_cc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_timer.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_usart.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_leuart.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_letimer.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_cryotimer.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_pcnt.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_i2c.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_adc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_acmp.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_vdac_opa.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_vdac.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_csen.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_lesense_st.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_lesense_buf.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_lesense_ch.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_lesense.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_rtcc_cc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_rtcc_ret.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_rtcc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_wdog_pch.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_wdog.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_etm.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_idac.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_smu.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_trng.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_dma_descriptor.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_devinfo.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_romtable.h"
-
-/** @} End of group EFR32FG13P232F512GM32_Peripheral_TypeDefs */
-
-/**************************************************************************//**
- * @defgroup EFR32FG13P232F512GM32_Peripheral_Base Peripheral Memory Map
- * @{
- *****************************************************************************/
-
-#define MSC_BASE (0x400E0000UL) /**< MSC base address */
-#define EMU_BASE (0x400E3000UL) /**< EMU base address */
-#define RMU_BASE (0x400E5000UL) /**< RMU base address */
-#define CMU_BASE (0x400E4000UL) /**< CMU base address */
-#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */
-#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */
-#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */
-#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */
-#define PRS_BASE (0x400E6000UL) /**< PRS base address */
-#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */
-#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */
-#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */
-#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
-#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
-#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */
-#define USART0_BASE (0x40010000UL) /**< USART0 base address */
-#define USART1_BASE (0x40010400UL) /**< USART1 base address */
-#define USART2_BASE (0x40010800UL) /**< USART2 base address */
-#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
-#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
-#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
-#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
-#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
-#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
-#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
-#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
-#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */
-#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */
-#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */
-#define RTCC_BASE (0x40042000UL) /**< RTCC base address */
-#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
-#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */
-#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
-#define SMU_BASE (0x40022000UL) /**< SMU base address */
-#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
-
-/** @} End of group EFR32FG13P232F512GM32_Peripheral_Base */
-
-/**************************************************************************//**
- * @defgroup EFR32FG13P232F512GM32_Peripheral_Declaration Peripheral Declarations
- * @{
- *****************************************************************************/
-
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
-#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */
-#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */
-#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
-#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */
-#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
-#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
-#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
-#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
-#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */
-#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
-#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */
-#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
-#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
-#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
-#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */
-#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
-
-/** @} End of group EFR32FG13P232F512GM32_Peripheral_Declaration */
-
-/**************************************************************************//**
- * @defgroup EFR32FG13P232F512GM32_Peripheral_Offsets Peripheral Offsets
- * @{
- *****************************************************************************/
-
-#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */
-#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
-#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */
-#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
-#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */
-#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */
-#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */
-#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
-#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
-#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
-#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */
-#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
-#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
-#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */
-
-/** @} End of group EFR32FG13P232F512GM32_Peripheral_Offsets */
-
-/**************************************************************************//**
- * @defgroup EFR32FG13P232F512GM32_BitFields Bit Fields
- * @{
- *****************************************************************************/
-
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_prs_signals.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_dmareq.h"
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P232F512GM32_WTIMER
- * @{
- * @defgroup EFR32FG13P232F512GM32_WTIMER_BitFields WTIMER Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for WTIMER CTRL */
-#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */
-#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */
-#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
-#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
-#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */
-#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */
-#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */
-#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */
-#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */
-#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */
-#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */
-#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */
-#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */
-#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */
-#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */
-#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */
-#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */
-#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */
-#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */
-#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */
-#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */
-#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */
-#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */
-#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */
-#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */
-#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */
-#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */
-#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */
-#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */
-#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */
-#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */
-#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */
-#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */
-#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */
-#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */
-#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */
-#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */
-#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */
-#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */
-#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */
-#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */
-#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */
-#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */
-#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */
-#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */
-#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */
-#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */
-#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */
-#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */
-#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */
-#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */
-#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */
-#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */
-#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */
-#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */
-#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */
-#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */
-#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */
-#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */
-#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */
-#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */
-#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */
-#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */
-#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */
-#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */
-#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */
-#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */
-#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */
-#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */
-#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */
-#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */
-#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */
-#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */
-#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */
-#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */
-#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */
-#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */
-#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */
-#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */
-#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */
-#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */
-#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */
-#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */
-#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */
-#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */
-#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */
-#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */
-#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */
-#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */
-#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */
-#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */
-#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */
-#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */
-#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */
-#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */
-#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-
-/* Bit fields for WTIMER CMD */
-#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */
-#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */
-#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */
-#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */
-#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */
-#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */
-#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */
-#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */
-#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */
-#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */
-#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */
-#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */
-
-/* Bit fields for WTIMER STATUS */
-#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */
-#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */
-#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */
-#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */
-#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */
-#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */
-#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */
-#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */
-#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
-#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */
-#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */
-#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */
-#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */
-#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */
-#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */
-#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */
-#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */
-#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */
-#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */
-#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */
-#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */
-#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */
-#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */
-#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */
-#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */
-#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */
-#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */
-#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */
-#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */
-#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */
-#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */
-#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */
-#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */
-#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */
-#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */
-#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */
-#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */
-#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */
-#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */
-#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */
-#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */
-#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */
-#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */
-#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
-#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */
-#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */
-#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */
-#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */
-#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
-#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */
-#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */
-#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */
-#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */
-#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
-#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */
-#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */
-#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */
-#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */
-#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
-#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */
-#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */
-
-/* Bit fields for WTIMER IF */
-#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */
-#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */
-#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */
-#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */
-#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
-#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */
-#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */
-#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
-#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */
-#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
-#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
-#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */
-#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
-#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
-#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */
-#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
-#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
-#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */
-#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
-#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
-#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */
-#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
-#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
-#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */
-#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
-#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
-#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */
-#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
-#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
-#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */
-#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
-#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
-#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */
-#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
-#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
-#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */
-
-/* Bit fields for WTIMER IFS */
-#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */
-#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */
-#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */
-#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */
-#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
-#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */
-#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */
-#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
-#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */
-#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
-#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
-#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */
-#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
-#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
-#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */
-#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
-#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
-#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */
-#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
-#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
-#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */
-#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
-#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
-#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */
-#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
-#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
-#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */
-#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
-#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
-#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */
-#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
-#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
-#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */
-#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
-#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
-#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */
-
-/* Bit fields for WTIMER IFC */
-#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */
-#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */
-#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */
-#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */
-#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
-#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */
-#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */
-#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
-#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */
-#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
-#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
-#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */
-#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
-#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
-#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */
-#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
-#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
-#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */
-#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
-#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
-#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */
-#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
-#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
-#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */
-#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
-#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
-#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */
-#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
-#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
-#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */
-#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
-#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
-#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */
-#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
-#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
-#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */
-
-/* Bit fields for WTIMER IEN */
-#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */
-#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */
-#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */
-#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */
-#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
-#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */
-#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */
-#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
-#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */
-#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
-#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
-#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */
-#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
-#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
-#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */
-#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
-#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
-#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */
-#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
-#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
-#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */
-#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
-#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
-#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */
-#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
-#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
-#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */
-#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
-#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
-#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */
-#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
-#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
-#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */
-#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
-#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
-#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */
-
-/* Bit fields for WTIMER TOP */
-#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */
-#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */
-#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */
-#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */
-#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */
-#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */
-
-/* Bit fields for WTIMER TOPB */
-#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */
-#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */
-#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */
-#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */
-#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */
-#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */
-
-/* Bit fields for WTIMER CNT */
-#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */
-#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */
-#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */
-#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */
-#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */
-#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */
-
-/* Bit fields for WTIMER LOCK */
-#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */
-#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */
-#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */
-#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */
-#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */
-#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
-#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */
-#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */
-#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */
-#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */
-#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
-#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */
-#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */
-#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */
-
-/* Bit fields for WTIMER ROUTEPEN */
-#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */
-#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */
-#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */
-#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */
-#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */
-#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
-#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
-#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */
-#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */
-#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */
-#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
-#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
-#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */
-#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */
-#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */
-#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
-#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
-#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */
-#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */
-#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */
-#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
-#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
-#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */
-#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */
-#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */
-#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
-#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
-#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */
-#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */
-#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */
-#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
-#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
-#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */
-#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */
-#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */
-#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
-#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
-
-/* Bit fields for WTIMER ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */
-#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */
-#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */
-#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */
-#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */
-
-/* Bit fields for WTIMER ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */
-
-/* Bit fields for WTIMER CC_CTRL */
-#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
-#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
-#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */
-#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */
-#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */
-#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */
-#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */
-#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */
-#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */
-#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */
-#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */
-#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */
-#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */
-#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */
-#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */
-#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */
-#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */
-#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */
-#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */
-#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */
-#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */
-#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */
-#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */
-#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */
-#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */
-#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */
-#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */
-#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */
-#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */
-#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */
-
-/* Bit fields for WTIMER CC_CCV */
-#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */
-#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */
-#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */
-#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */
-#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */
-#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */
-
-/* Bit fields for WTIMER CC_CCVP */
-#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */
-#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */
-#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */
-#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */
-#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */
-#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */
-
-/* Bit fields for WTIMER CC_CCVB */
-#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */
-#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */
-#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */
-#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */
-#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */
-#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */
-
-/* Bit fields for WTIMER DTCTRL */
-#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */
-#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */
-#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */
-#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */
-#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */
-#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */
-#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */
-#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */
-#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */
-#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */
-#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */
-#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */
-#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */
-#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */
-#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */
-#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */
-#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */
-#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */
-#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */
-#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */
-#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */
-#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */
-#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */
-#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
-
-/* Bit fields for WTIMER DTTIME */
-#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */
-#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */
-#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */
-#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */
-#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */
-#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */
-#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */
-#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */
-#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */
-#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */
-#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */
-#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */
-#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */
-#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */
-#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */
-#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */
-#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */
-#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */
-#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */
-#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */
-#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */
-#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */
-#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */
-#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */
-#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */
-#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */
-#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */
-#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */
-#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */
-#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */
-#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */
-#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */
-#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */
-#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */
-#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */
-#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */
-
-/* Bit fields for WTIMER DTFC */
-#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */
-#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */
-#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */
-#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */
-#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */
-#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */
-#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */
-#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */
-#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */
-#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */
-#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */
-#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */
-#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */
-#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */
-#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */
-#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */
-#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */
-#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */
-#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */
-#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */
-#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */
-#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */
-#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
-#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */
-#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */
-#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */
-#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */
-#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
-#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */
-
-/* Bit fields for WTIMER DTOGEN */
-#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */
-#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */
-#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */
-#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */
-#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */
-#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
-#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
-#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */
-#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */
-#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */
-#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
-#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
-#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */
-#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */
-#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */
-#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
-#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
-#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */
-#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */
-#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */
-#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
-#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
-#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */
-#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */
-#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */
-#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
-#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
-#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */
-#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */
-#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */
-#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
-#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
-
-/* Bit fields for WTIMER DTFAULT */
-#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */
-#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */
-#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */
-#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */
-#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */
-#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */
-#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */
-#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */
-#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */
-#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */
-#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */
-#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */
-#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */
-#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */
-#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */
-#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */
-#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */
-#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */
-#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */
-#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */
-#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */
-#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */
-
-/* Bit fields for WTIMER DTFAULTC */
-#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */
-#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */
-#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */
-#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */
-#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */
-#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */
-#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */
-#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */
-#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */
-#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */
-#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */
-#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */
-#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */
-#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */
-#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */
-#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */
-#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */
-#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */
-#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */
-#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */
-#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */
-#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */
-
-/* Bit fields for WTIMER DTLOCK */
-#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */
-#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */
-#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
-#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
-#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */
-#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
-#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */
-#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */
-#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */
-#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */
-#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
-#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */
-#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */
-#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */
-
-/** @} */
-/** @} End of group EFR32FG13P232F512GM32_WTIMER */
-
-/**************************************************************************//**
- * @defgroup EFR32FG13P232F512GM32_UNLOCK Unlock Codes
- * @{
- *****************************************************************************/
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
-#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
-#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
-
-/** @} End of group EFR32FG13P232F512GM32_UNLOCK */
-
-/** @} End of group EFR32FG13P232F512GM32_BitFields */
-
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_af_ports.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_af_pins.h"
-
-/** @} End of group EFR32FG13P232F512GM32 */
-
-/** @} End of group Parts */
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* EFR32FG13P232F512GM32_H */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p232f512gm48.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p232f512gm48.h
deleted file mode 100644
index 720cd309..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p232f512gm48.h
+++ /dev/null
@@ -1,2039 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p232f512gm48.h
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File
- * for EFR32FG13P232F512GM48
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-#ifndef EFR32FG13P232F512GM48_H
-#define EFR32FG13P232F512GM48_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**************************************************************************//**
- * @addtogroup Parts
- * @{
- *****************************************************************************/
-
-/**************************************************************************//**
- * @defgroup EFR32FG13P232F512GM48 EFR32FG13P232F512GM48
- * @{
- *****************************************************************************/
-
-/** Interrupt Number Definition */
-typedef enum IRQn{
-/****** Cortex-M4 Processor Exceptions Numbers ********************************************/
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
- HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
-
-/****** EFR32FG13P Peripheral Interrupt Numbers ********************************************/
-
- EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */
- WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */
- WDOG1_IRQn = 3, /*!< 16+3 EFR32 WDOG1 Interrupt */
- LDMA_IRQn = 9, /*!< 16+9 EFR32 LDMA Interrupt */
- GPIO_EVEN_IRQn = 10, /*!< 16+10 EFR32 GPIO_EVEN Interrupt */
- TIMER0_IRQn = 11, /*!< 16+11 EFR32 TIMER0 Interrupt */
- USART0_RX_IRQn = 12, /*!< 16+12 EFR32 USART0_RX Interrupt */
- USART0_TX_IRQn = 13, /*!< 16+13 EFR32 USART0_TX Interrupt */
- ACMP0_IRQn = 14, /*!< 16+14 EFR32 ACMP0 Interrupt */
- ADC0_IRQn = 15, /*!< 16+15 EFR32 ADC0 Interrupt */
- IDAC0_IRQn = 16, /*!< 16+16 EFR32 IDAC0 Interrupt */
- I2C0_IRQn = 17, /*!< 16+17 EFR32 I2C0 Interrupt */
- GPIO_ODD_IRQn = 18, /*!< 16+18 EFR32 GPIO_ODD Interrupt */
- TIMER1_IRQn = 19, /*!< 16+19 EFR32 TIMER1 Interrupt */
- USART1_RX_IRQn = 20, /*!< 16+20 EFR32 USART1_RX Interrupt */
- USART1_TX_IRQn = 21, /*!< 16+21 EFR32 USART1_TX Interrupt */
- LEUART0_IRQn = 22, /*!< 16+22 EFR32 LEUART0 Interrupt */
- PCNT0_IRQn = 23, /*!< 16+23 EFR32 PCNT0 Interrupt */
- CMU_IRQn = 24, /*!< 16+24 EFR32 CMU Interrupt */
- MSC_IRQn = 25, /*!< 16+25 EFR32 MSC Interrupt */
- CRYPTO0_IRQn = 26, /*!< 16+26 EFR32 CRYPTO0 Interrupt */
- LETIMER0_IRQn = 27, /*!< 16+27 EFR32 LETIMER0 Interrupt */
- RTCC_IRQn = 31, /*!< 16+31 EFR32 RTCC Interrupt */
- CRYOTIMER_IRQn = 33, /*!< 16+33 EFR32 CRYOTIMER Interrupt */
- FPUEH_IRQn = 35, /*!< 16+35 EFR32 FPUEH Interrupt */
- SMU_IRQn = 36, /*!< 16+36 EFR32 SMU Interrupt */
- WTIMER0_IRQn = 37, /*!< 16+37 EFR32 WTIMER0 Interrupt */
- USART2_RX_IRQn = 38, /*!< 16+38 EFR32 USART2_RX Interrupt */
- USART2_TX_IRQn = 39, /*!< 16+39 EFR32 USART2_TX Interrupt */
- I2C1_IRQn = 40, /*!< 16+40 EFR32 I2C1 Interrupt */
- VDAC0_IRQn = 41, /*!< 16+41 EFR32 VDAC0 Interrupt */
- CSEN_IRQn = 42, /*!< 16+42 EFR32 CSEN Interrupt */
- LESENSE_IRQn = 43, /*!< 16+43 EFR32 LESENSE Interrupt */
- CRYPTO1_IRQn = 44, /*!< 16+44 EFR32 CRYPTO1 Interrupt */
- TRNG0_IRQn = 45, /*!< 16+45 EFR32 TRNG0 Interrupt */
-} IRQn_Type;
-
-#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */
-
-/**************************************************************************//**
- * @defgroup EFR32FG13P232F512GM48_Core Core
- * @{
- * @brief Processor and Core Peripheral Section
- *****************************************************************************/
-#define __MPU_PRESENT 1 /**< Presence of MPU */
-#define __FPU_PRESENT 1 /**< Presence of FPU */
-#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
-
-/** @} End of group EFR32FG13P232F512GM48_Core */
-
-/**************************************************************************//**
-* @defgroup EFR32FG13P232F512GM48_Part Part
-* @{
-******************************************************************************/
-
-/** Part family */
-#define _EFR32_FLEX_FAMILY 1 /**< FLEX Gecko RF SoC Family */
-#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */
-#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
-#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG_3 /**< Series 1, Configuration 3 */
-#define _SILICON_LABS_32B_SERIES_1_CONFIG 3 /**< Series 1, Configuration 3 */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID 89 /**< Silicon Labs internal use only, may change any time */
-#define _SILICON_LABS_GECKO_INTERNAL_SDID_89 /**< Silicon Labs internal use only, may change any time */
-#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */
-#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */
-#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */
-#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /**< Radio type */
-#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
-#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN_3 /**< @deprecated Platform 2, generation 3 */
-#define _SILICON_LABS_32B_PLATFORM_2_GEN 3 /**< @deprecated Platform 2, generation 3 */
-
-/* If part number is not defined as compiler option, define it */
-#if !defined(EFR32FG13P232F512GM48)
-#define EFR32FG13P232F512GM48 1 /**< FLEX Gecko Part */
-#endif
-
-/** Configure part number */
-#define PART_NUMBER "EFR32FG13P232F512GM48" /**< Part Number */
-
-/** Memory Base addresses and limits */
-#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */
-#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM0_CODE available address space */
-#define RAM0_CODE_MEM_END ((uint32_t) 0x10007FFFUL) /**< RAM0_CODE end address */
-#define RAM0_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM0_CODE used bits */
-#define RAM2_MEM_BASE ((uint32_t) 0x20010000UL) /**< RAM2 base address */
-#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */
-#define RAM2_MEM_END ((uint32_t) 0x200107FFUL) /**< RAM2 end address */
-#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */
-#define RAM1_MEM_BASE ((uint32_t) 0x20008000UL) /**< RAM1 base address */
-#define RAM1_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM1 available address space */
-#define RAM1_MEM_END ((uint32_t) 0x2000FFFFUL) /**< RAM1 end address */
-#define RAM1_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM1 used bits */
-#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */
-#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */
-#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */
-#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
-#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */
-#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */
-#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */
-#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10008000UL) /**< RAM1_CODE base address */
-#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM1_CODE available address space */
-#define RAM1_CODE_MEM_END ((uint32_t) 0x1000FFFFUL) /**< RAM1_CODE end address */
-#define RAM1_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM1_CODE used bits */
-#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */
-#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */
-#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */
-#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */
-#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
-#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */
-#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */
-#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */
-#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */
-#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */
-#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */
-#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */
-#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */
-#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */
-#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */
-#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
-#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */
-#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */
-#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */
-#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */
-#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */
-#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */
-#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */
-#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */
-#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */
-#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */
-#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */
-#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */
-#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */
-#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
-#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
-#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */
-#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */
-#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */
-#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */
-#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
-#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */
-#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */
-#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */
-#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */
-#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */
-#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */
-#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */
-#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10010000UL) /**< RAM2_CODE base address */
-#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */
-#define RAM2_CODE_MEM_END ((uint32_t) 0x100107FFUL) /**< RAM2_CODE end address */
-#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
-#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
-#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
-#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */
-
-/** Bit banding area */
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
-
-/** Flash and SRAM limits for EFR32FG13P232F512GM48 */
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
-#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */
-#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
-#define SRAM_SIZE (0x00010000UL) /**< Available SRAM Memory */
-#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
-#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
-#define EXT_IRQ_COUNT 47 /**< Number of External (NVIC) interrupts */
-
-/** AF channels connect the different on-chip peripherals with the af-mux */
-#define AFCHAN_MAX 118U
-/** AF channel maximum location number */
-#define AFCHANLOC_MAX 32U
-/** Analog AF channels */
-#define AFACHAN_MAX 118U
-
-/* Part number capabilities */
-
-#define CRYPTO_PRESENT /**< CRYPTO is available in this part */
-#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */
-#define TIMER_PRESENT /**< TIMER is available in this part */
-#define TIMER_COUNT 2 /**< 2 TIMERs available */
-#define WTIMER_PRESENT /**< WTIMER is available in this part */
-#define WTIMER_COUNT 1 /**< 1 WTIMERs available */
-#define USART_PRESENT /**< USART is available in this part */
-#define USART_COUNT 3 /**< 3 USARTs available */
-#define LEUART_PRESENT /**< LEUART is available in this part */
-#define LEUART_COUNT 1 /**< 1 LEUARTs available */
-#define LETIMER_PRESENT /**< LETIMER is available in this part */
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
-#define PCNT_PRESENT /**< PCNT is available in this part */
-#define PCNT_COUNT 1 /**< 1 PCNTs available */
-#define I2C_PRESENT /**< I2C is available in this part */
-#define I2C_COUNT 2 /**< 2 I2Cs available */
-#define ADC_PRESENT /**< ADC is available in this part */
-#define ADC_COUNT 1 /**< 1 ADCs available */
-#define ACMP_PRESENT /**< ACMP is available in this part */
-#define ACMP_COUNT 2 /**< 2 ACMPs available */
-#define VDAC_PRESENT /**< VDAC is available in this part */
-#define VDAC_COUNT 1 /**< 1 VDACs available */
-#define WDOG_PRESENT /**< WDOG is available in this part */
-#define WDOG_COUNT 2 /**< 2 WDOGs available */
-#define IDAC_PRESENT /**< IDAC is available in this part */
-#define IDAC_COUNT 1 /**< 1 IDACs available */
-#define TRNG_PRESENT /**< TRNG is available in this part */
-#define TRNG_COUNT 1 /**< 1 TRNGs available */
-#define MSC_PRESENT /**< MSC is available in this part */
-#define MSC_COUNT 1 /**< 1 MSC available */
-#define EMU_PRESENT /**< EMU is available in this part */
-#define EMU_COUNT 1 /**< 1 EMU available */
-#define RMU_PRESENT /**< RMU is available in this part */
-#define RMU_COUNT 1 /**< 1 RMU available */
-#define CMU_PRESENT /**< CMU is available in this part */
-#define CMU_COUNT 1 /**< 1 CMU available */
-#define GPIO_PRESENT /**< GPIO is available in this part */
-#define GPIO_COUNT 1 /**< 1 GPIO available */
-#define PRS_PRESENT /**< PRS is available in this part */
-#define PRS_COUNT 1 /**< 1 PRS available */
-#define LDMA_PRESENT /**< LDMA is available in this part */
-#define LDMA_COUNT 1 /**< 1 LDMA available */
-#define FPUEH_PRESENT /**< FPUEH is available in this part */
-#define FPUEH_COUNT 1 /**< 1 FPUEH available */
-#define GPCRC_PRESENT /**< GPCRC is available in this part */
-#define GPCRC_COUNT 1 /**< 1 GPCRC available */
-#define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
-#define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
-#define CSEN_PRESENT /**< CSEN is available in this part */
-#define CSEN_COUNT 1 /**< 1 CSEN available */
-#define LESENSE_PRESENT /**< LESENSE is available in this part */
-#define LESENSE_COUNT 1 /**< 1 LESENSE available */
-#define RTCC_PRESENT /**< RTCC is available in this part */
-#define RTCC_COUNT 1 /**< 1 RTCC available */
-#define ETM_PRESENT /**< ETM is available in this part */
-#define ETM_COUNT 1 /**< 1 ETM available */
-#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
-#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
-#define SMU_PRESENT /**< SMU is available in this part */
-#define SMU_COUNT 1 /**< 1 SMU available */
-#define DCDC_PRESENT /**< DCDC is available in this part */
-#define DCDC_COUNT 1 /**< 1 DCDC available */
-
-#include "../../../efr32/cmsis/core_cm4.h" /* Cortex-M4 processor and core peripherals */
-#include "../../../efr32/vendor/efr32fg13/system_efr32fg13p.h" /* System Header File */
-
-/** @} End of group EFR32FG13P232F512GM48_Part */
-
-/**************************************************************************//**
- * @defgroup EFR32FG13P232F512GM48_Peripheral_TypeDefs Peripheral TypeDefs
- * @{
- * @brief Device Specific Peripheral Register Structures
- *****************************************************************************/
-
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_msc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_emu.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_rmu.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_cmu.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_crypto.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_gpio_p.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_gpio.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_prs_ch.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_prs.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_ldma_ch.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_ldma.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_fpueh.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_gpcrc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_timer_cc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_timer.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_usart.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_leuart.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_letimer.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_cryotimer.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_pcnt.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_i2c.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_adc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_acmp.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_vdac_opa.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_vdac.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_csen.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_lesense_st.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_lesense_buf.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_lesense_ch.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_lesense.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_rtcc_cc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_rtcc_ret.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_rtcc.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_wdog_pch.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_wdog.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_etm.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_idac.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_smu.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_trng.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_dma_descriptor.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_devinfo.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_romtable.h"
-
-/** @} End of group EFR32FG13P232F512GM48_Peripheral_TypeDefs */
-
-/**************************************************************************//**
- * @defgroup EFR32FG13P232F512GM48_Peripheral_Base Peripheral Memory Map
- * @{
- *****************************************************************************/
-
-#define MSC_BASE (0x400E0000UL) /**< MSC base address */
-#define EMU_BASE (0x400E3000UL) /**< EMU base address */
-#define RMU_BASE (0x400E5000UL) /**< RMU base address */
-#define CMU_BASE (0x400E4000UL) /**< CMU base address */
-#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */
-#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */
-#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */
-#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */
-#define PRS_BASE (0x400E6000UL) /**< PRS base address */
-#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */
-#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */
-#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */
-#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
-#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
-#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */
-#define USART0_BASE (0x40010000UL) /**< USART0 base address */
-#define USART1_BASE (0x40010400UL) /**< USART1 base address */
-#define USART2_BASE (0x40010800UL) /**< USART2 base address */
-#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */
-#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */
-#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */
-#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */
-#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */
-#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
-#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */
-#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */
-#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */
-#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */
-#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */
-#define RTCC_BASE (0x40042000UL) /**< RTCC base address */
-#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
-#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */
-#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */
-#define SMU_BASE (0x40022000UL) /**< SMU base address */
-#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
-
-/** @} End of group EFR32FG13P232F512GM48_Peripheral_Base */
-
-/**************************************************************************//**
- * @defgroup EFR32FG13P232F512GM48_Peripheral_Declaration Peripheral Declarations
- * @{
- *****************************************************************************/
-
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
-#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */
-#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */
-#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
-#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */
-#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
-#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
-#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
-#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
-#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */
-#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
-#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */
-#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
-#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
-#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
-#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */
-#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
-
-/** @} End of group EFR32FG13P232F512GM48_Peripheral_Declaration */
-
-/**************************************************************************//**
- * @defgroup EFR32FG13P232F512GM48_Peripheral_Offsets Peripheral Offsets
- * @{
- *****************************************************************************/
-
-#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */
-#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
-#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */
-#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
-#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */
-#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */
-#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */
-#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
-#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
-#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
-#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */
-#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
-#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
-#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */
-
-/** @} End of group EFR32FG13P232F512GM48_Peripheral_Offsets */
-
-/**************************************************************************//**
- * @defgroup EFR32FG13P232F512GM48_BitFields Bit Fields
- * @{
- *****************************************************************************/
-
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_prs_signals.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_dmareq.h"
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P232F512GM48_WTIMER
- * @{
- * @defgroup EFR32FG13P232F512GM48_WTIMER_BitFields WTIMER Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for WTIMER CTRL */
-#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */
-#define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */
-#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
-#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
-#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */
-#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */
-#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */
-#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */
-#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */
-#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */
-#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */
-#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */
-#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */
-#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */
-#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */
-#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */
-#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */
-#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */
-#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */
-#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */
-#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */
-#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */
-#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */
-#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */
-#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */
-#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */
-#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */
-#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */
-#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */
-#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */
-#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */
-#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */
-#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */
-#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */
-#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */
-#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */
-#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */
-#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */
-#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */
-#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */
-#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */
-#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */
-#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */
-#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */
-#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */
-#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */
-#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */
-#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */
-#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */
-#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */
-#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */
-#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */
-#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */
-#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */
-#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */
-#define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */
-#define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */
-#define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */
-#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */
-#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */
-#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */
-#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */
-#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */
-#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */
-#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */
-#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */
-#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */
-#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */
-#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */
-#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */
-#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */
-#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */
-#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */
-#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */
-#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */
-#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */
-#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */
-#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */
-#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */
-#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */
-#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */
-#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */
-#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */
-#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */
-#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */
-#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */
-#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */
-#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */
-#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */
-#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */
-#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */
-#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */
-#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */
-#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */
-#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */
-#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
-#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */
-
-/* Bit fields for WTIMER CMD */
-#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */
-#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */
-#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */
-#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */
-#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */
-#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */
-#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */
-#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */
-#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */
-#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */
-#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */
-#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */
-
-/* Bit fields for WTIMER STATUS */
-#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */
-#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */
-#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */
-#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */
-#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */
-#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */
-#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */
-#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */
-#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
-#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */
-#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */
-#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */
-#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */
-#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */
-#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */
-#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */
-#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */
-#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */
-#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */
-#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */
-#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */
-#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */
-#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */
-#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */
-#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */
-#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */
-#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */
-#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */
-#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */
-#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */
-#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */
-#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */
-#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */
-#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */
-#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */
-#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */
-#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */
-#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */
-#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */
-#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */
-#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */
-#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */
-#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */
-#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
-#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */
-#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */
-#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */
-#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */
-#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
-#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */
-#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */
-#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */
-#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */
-#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
-#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */
-#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */
-#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */
-#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */
-#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
-#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */
-#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */
-#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */
-
-/* Bit fields for WTIMER IF */
-#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */
-#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */
-#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */
-#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */
-#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
-#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */
-#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */
-#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
-#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */
-#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
-#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
-#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */
-#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
-#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
-#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */
-#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
-#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
-#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */
-#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
-#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
-#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */
-#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
-#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
-#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */
-#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
-#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
-#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */
-#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
-#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
-#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */
-#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
-#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
-#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */
-#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
-#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
-#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
-#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */
-
-/* Bit fields for WTIMER IFS */
-#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */
-#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */
-#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */
-#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */
-#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
-#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */
-#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */
-#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
-#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */
-#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
-#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
-#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */
-#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
-#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
-#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */
-#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
-#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
-#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */
-#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
-#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
-#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */
-#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
-#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
-#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */
-#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
-#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
-#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */
-#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
-#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
-#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */
-#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
-#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
-#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */
-#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
-#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
-#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
-#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */
-
-/* Bit fields for WTIMER IFC */
-#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */
-#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */
-#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */
-#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */
-#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
-#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */
-#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */
-#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
-#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */
-#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
-#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
-#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */
-#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
-#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
-#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */
-#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
-#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
-#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */
-#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
-#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
-#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */
-#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
-#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
-#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */
-#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
-#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
-#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */
-#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
-#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
-#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */
-#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
-#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
-#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */
-#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
-#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
-#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
-#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */
-
-/* Bit fields for WTIMER IEN */
-#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */
-#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */
-#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */
-#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */
-#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
-#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */
-#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */
-#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
-#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */
-#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
-#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
-#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */
-#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
-#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
-#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */
-#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
-#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
-#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */
-#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
-#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
-#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */
-#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
-#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
-#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */
-#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
-#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
-#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */
-#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
-#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
-#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */
-#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
-#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
-#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */
-#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
-#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
-#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
-#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */
-
-/* Bit fields for WTIMER TOP */
-#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */
-#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */
-#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */
-#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */
-#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */
-#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */
-
-/* Bit fields for WTIMER TOPB */
-#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */
-#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */
-#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */
-#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */
-#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */
-#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */
-
-/* Bit fields for WTIMER CNT */
-#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */
-#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */
-#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */
-#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */
-#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */
-#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */
-
-/* Bit fields for WTIMER LOCK */
-#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */
-#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */
-#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */
-#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */
-#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */
-#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
-#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */
-#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */
-#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */
-#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */
-#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
-#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */
-#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */
-#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */
-
-/* Bit fields for WTIMER ROUTEPEN */
-#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */
-#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */
-#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */
-#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */
-#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */
-#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
-#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
-#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */
-#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */
-#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */
-#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
-#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
-#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */
-#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */
-#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */
-#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
-#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
-#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */
-#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */
-#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */
-#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
-#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
-#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */
-#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */
-#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */
-#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
-#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
-#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */
-#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */
-#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */
-#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
-#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
-#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */
-#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */
-#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */
-#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
-#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
-
-/* Bit fields for WTIMER ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */
-#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */
-#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */
-#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */
-#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */
-#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */
-#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */
-
-/* Bit fields for WTIMER ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */
-#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */
-#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */
-
-/* Bit fields for WTIMER CC_CTRL */
-#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
-#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
-#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */
-#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */
-#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */
-#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */
-#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */
-#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */
-#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */
-#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */
-#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */
-#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */
-#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */
-#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */
-#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */
-#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */
-#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */
-#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */
-#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */
-#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */
-#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */
-#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */
-#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */
-#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */
-#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */
-#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */
-#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */
-#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */
-#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */
-#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */
-#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */
-#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */
-
-/* Bit fields for WTIMER CC_CCV */
-#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */
-#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */
-#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */
-#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */
-#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */
-#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */
-
-/* Bit fields for WTIMER CC_CCVP */
-#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */
-#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */
-#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */
-#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */
-#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */
-#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */
-
-/* Bit fields for WTIMER CC_CCVB */
-#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */
-#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */
-#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */
-#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */
-#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */
-#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */
-
-/* Bit fields for WTIMER DTCTRL */
-#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */
-#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */
-#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */
-#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */
-#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */
-#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */
-#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */
-#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */
-#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */
-#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */
-#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */
-#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */
-#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */
-#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */
-#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */
-#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */
-#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */
-#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */
-#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */
-#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */
-#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */
-#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */
-#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */
-#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */
-#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
-#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
-
-/* Bit fields for WTIMER DTTIME */
-#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */
-#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */
-#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */
-#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */
-#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */
-#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */
-#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */
-#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */
-#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */
-#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */
-#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */
-#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */
-#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */
-#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */
-#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */
-#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */
-#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */
-#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */
-#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */
-#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */
-#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */
-#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */
-#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */
-#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */
-#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */
-#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */
-#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */
-#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */
-#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */
-#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */
-#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */
-#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */
-#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */
-#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */
-#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */
-#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */
-
-/* Bit fields for WTIMER DTFC */
-#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */
-#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */
-#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */
-#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */
-#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */
-#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */
-#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */
-#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */
-#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */
-#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */
-#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */
-#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */
-#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */
-#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */
-#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */
-#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */
-#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */
-#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */
-#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */
-#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
-#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */
-#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */
-#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */
-#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */
-#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
-#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */
-#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */
-#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */
-#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */
-#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
-#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */
-
-/* Bit fields for WTIMER DTOGEN */
-#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */
-#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */
-#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */
-#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */
-#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */
-#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
-#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
-#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */
-#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */
-#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */
-#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
-#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
-#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */
-#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */
-#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */
-#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
-#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
-#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */
-#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */
-#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */
-#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
-#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
-#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */
-#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */
-#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */
-#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
-#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
-#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */
-#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */
-#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */
-#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
-#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
-
-/* Bit fields for WTIMER DTFAULT */
-#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */
-#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */
-#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */
-#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */
-#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */
-#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */
-#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */
-#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */
-#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */
-#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */
-#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */
-#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */
-#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */
-#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */
-#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */
-#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */
-#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */
-#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */
-#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */
-#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */
-#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */
-#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */
-
-/* Bit fields for WTIMER DTFAULTC */
-#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */
-#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */
-#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */
-#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */
-#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */
-#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */
-#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */
-#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */
-#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */
-#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */
-#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */
-#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */
-#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */
-#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */
-#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */
-#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */
-#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */
-#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */
-#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */
-#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */
-#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */
-#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */
-
-/* Bit fields for WTIMER DTLOCK */
-#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */
-#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */
-#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
-#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
-#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */
-#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
-#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */
-#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */
-#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */
-#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */
-#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
-#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */
-#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */
-#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */
-
-/** @} */
-/** @} End of group EFR32FG13P232F512GM48_WTIMER */
-
-/**************************************************************************//**
- * @defgroup EFR32FG13P232F512GM48_UNLOCK Unlock Codes
- * @{
- *****************************************************************************/
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
-#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
-#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
-
-/** @} End of group EFR32FG13P232F512GM48_UNLOCK */
-
-/** @} End of group EFR32FG13P232F512GM48_BitFields */
-
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_af_ports.h"
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p_af_pins.h"
-
-/** @} End of group EFR32FG13P232F512GM48 */
-
-/** @} End of group Parts */
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* EFR32FG13P232F512GM48_H */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_acmp.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_acmp.h
deleted file mode 100644
index 0d8853ed..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_acmp.h
+++ /dev/null
@@ -1,1429 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_acmp.h
- * @brief EFR32FG13P_ACMP register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P_ACMP ACMP
- * @{
- * @brief EFR32FG13P_ACMP Register Declaration
- *****************************************************************************/
-/** ACMP Register Declaration */
-typedef struct {
- __IOM uint32_t CTRL; /**< Control Register */
- __IOM uint32_t INPUTSEL; /**< Input Selection Register */
- __IM uint32_t STATUS; /**< Status Register */
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- uint32_t RESERVED0[1]; /**< Reserved for future use **/
- __IM uint32_t APORTREQ; /**< APORT Request Status Register */
- __IM uint32_t APORTCONFLICT; /**< APORT Conflict Status Register */
- __IOM uint32_t HYSTERESIS0; /**< Hysteresis 0 Register */
- __IOM uint32_t HYSTERESIS1; /**< Hysteresis 1 Register */
-
- uint32_t RESERVED1[4]; /**< Reserved for future use **/
- __IOM uint32_t ROUTEPEN; /**< I/O Routing Pine Enable Register */
- __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
- __IOM uint32_t EXTIFCTRL; /**< External Override Interface Control */
-} ACMP_TypeDef; /** @} */
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_ACMP
- * @{
- * @defgroup EFR32FG13P_ACMP_BitFields ACMP Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for ACMP CTRL */
-#define _ACMP_CTRL_RESETVALUE 0x07000000UL /**< Default value for ACMP_CTRL */
-#define _ACMP_CTRL_MASK 0xBF3CF70DUL /**< Mask for ACMP_CTRL */
-#define ACMP_CTRL_EN (0x1UL << 0) /**< Analog Comparator Enable */
-#define _ACMP_CTRL_EN_SHIFT 0 /**< Shift value for ACMP_EN */
-#define _ACMP_CTRL_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */
-#define _ACMP_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
-#define ACMP_CTRL_EN_DEFAULT (_ACMP_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CTRL */
-#define ACMP_CTRL_INACTVAL (0x1UL << 2) /**< Inactive Value */
-#define _ACMP_CTRL_INACTVAL_SHIFT 2 /**< Shift value for ACMP_INACTVAL */
-#define _ACMP_CTRL_INACTVAL_MASK 0x4UL /**< Bit mask for ACMP_INACTVAL */
-#define _ACMP_CTRL_INACTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
-#define _ACMP_CTRL_INACTVAL_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */
-#define _ACMP_CTRL_INACTVAL_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */
-#define ACMP_CTRL_INACTVAL_DEFAULT (_ACMP_CTRL_INACTVAL_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_CTRL */
-#define ACMP_CTRL_INACTVAL_LOW (_ACMP_CTRL_INACTVAL_LOW << 2) /**< Shifted mode LOW for ACMP_CTRL */
-#define ACMP_CTRL_INACTVAL_HIGH (_ACMP_CTRL_INACTVAL_HIGH << 2) /**< Shifted mode HIGH for ACMP_CTRL */
-#define ACMP_CTRL_GPIOINV (0x1UL << 3) /**< Comparator GPIO Output Invert */
-#define _ACMP_CTRL_GPIOINV_SHIFT 3 /**< Shift value for ACMP_GPIOINV */
-#define _ACMP_CTRL_GPIOINV_MASK 0x8UL /**< Bit mask for ACMP_GPIOINV */
-#define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
-#define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL /**< Mode NOTINV for ACMP_CTRL */
-#define _ACMP_CTRL_GPIOINV_INV 0x00000001UL /**< Mode INV for ACMP_CTRL */
-#define ACMP_CTRL_GPIOINV_DEFAULT (_ACMP_CTRL_GPIOINV_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_CTRL */
-#define ACMP_CTRL_GPIOINV_NOTINV (_ACMP_CTRL_GPIOINV_NOTINV << 3) /**< Shifted mode NOTINV for ACMP_CTRL */
-#define ACMP_CTRL_GPIOINV_INV (_ACMP_CTRL_GPIOINV_INV << 3) /**< Shifted mode INV for ACMP_CTRL */
-#define ACMP_CTRL_APORTXMASTERDIS (0x1UL << 8) /**< APORT Bus X Master Disable */
-#define _ACMP_CTRL_APORTXMASTERDIS_SHIFT 8 /**< Shift value for ACMP_APORTXMASTERDIS */
-#define _ACMP_CTRL_APORTXMASTERDIS_MASK 0x100UL /**< Bit mask for ACMP_APORTXMASTERDIS */
-#define _ACMP_CTRL_APORTXMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
-#define ACMP_CTRL_APORTXMASTERDIS_DEFAULT (_ACMP_CTRL_APORTXMASTERDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_CTRL */
-#define ACMP_CTRL_APORTYMASTERDIS (0x1UL << 9) /**< APORT Bus Y Master Disable */
-#define _ACMP_CTRL_APORTYMASTERDIS_SHIFT 9 /**< Shift value for ACMP_APORTYMASTERDIS */
-#define _ACMP_CTRL_APORTYMASTERDIS_MASK 0x200UL /**< Bit mask for ACMP_APORTYMASTERDIS */
-#define _ACMP_CTRL_APORTYMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
-#define ACMP_CTRL_APORTYMASTERDIS_DEFAULT (_ACMP_CTRL_APORTYMASTERDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for ACMP_CTRL */
-#define ACMP_CTRL_APORTVMASTERDIS (0x1UL << 10) /**< APORT Bus Master Disable for Bus Selected By VASEL */
-#define _ACMP_CTRL_APORTVMASTERDIS_SHIFT 10 /**< Shift value for ACMP_APORTVMASTERDIS */
-#define _ACMP_CTRL_APORTVMASTERDIS_MASK 0x400UL /**< Bit mask for ACMP_APORTVMASTERDIS */
-#define _ACMP_CTRL_APORTVMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
-#define ACMP_CTRL_APORTVMASTERDIS_DEFAULT (_ACMP_CTRL_APORTVMASTERDIS_DEFAULT << 10) /**< Shifted mode DEFAULT for ACMP_CTRL */
-#define _ACMP_CTRL_PWRSEL_SHIFT 12 /**< Shift value for ACMP_PWRSEL */
-#define _ACMP_CTRL_PWRSEL_MASK 0x7000UL /**< Bit mask for ACMP_PWRSEL */
-#define _ACMP_CTRL_PWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
-#define _ACMP_CTRL_PWRSEL_AVDD 0x00000000UL /**< Mode AVDD for ACMP_CTRL */
-#define _ACMP_CTRL_PWRSEL_DVDD 0x00000001UL /**< Mode DVDD for ACMP_CTRL */
-#define _ACMP_CTRL_PWRSEL_IOVDD0 0x00000002UL /**< Mode IOVDD0 for ACMP_CTRL */
-#define _ACMP_CTRL_PWRSEL_IOVDD1 0x00000004UL /**< Mode IOVDD1 for ACMP_CTRL */
-#define ACMP_CTRL_PWRSEL_DEFAULT (_ACMP_CTRL_PWRSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for ACMP_CTRL */
-#define ACMP_CTRL_PWRSEL_AVDD (_ACMP_CTRL_PWRSEL_AVDD << 12) /**< Shifted mode AVDD for ACMP_CTRL */
-#define ACMP_CTRL_PWRSEL_DVDD (_ACMP_CTRL_PWRSEL_DVDD << 12) /**< Shifted mode DVDD for ACMP_CTRL */
-#define ACMP_CTRL_PWRSEL_IOVDD0 (_ACMP_CTRL_PWRSEL_IOVDD0 << 12) /**< Shifted mode IOVDD0 for ACMP_CTRL */
-#define ACMP_CTRL_PWRSEL_IOVDD1 (_ACMP_CTRL_PWRSEL_IOVDD1 << 12) /**< Shifted mode IOVDD1 for ACMP_CTRL */
-#define ACMP_CTRL_ACCURACY (0x1UL << 15) /**< ACMP Accuracy Mode */
-#define _ACMP_CTRL_ACCURACY_SHIFT 15 /**< Shift value for ACMP_ACCURACY */
-#define _ACMP_CTRL_ACCURACY_MASK 0x8000UL /**< Bit mask for ACMP_ACCURACY */
-#define _ACMP_CTRL_ACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
-#define _ACMP_CTRL_ACCURACY_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */
-#define _ACMP_CTRL_ACCURACY_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */
-#define ACMP_CTRL_ACCURACY_DEFAULT (_ACMP_CTRL_ACCURACY_DEFAULT << 15) /**< Shifted mode DEFAULT for ACMP_CTRL */
-#define ACMP_CTRL_ACCURACY_LOW (_ACMP_CTRL_ACCURACY_LOW << 15) /**< Shifted mode LOW for ACMP_CTRL */
-#define ACMP_CTRL_ACCURACY_HIGH (_ACMP_CTRL_ACCURACY_HIGH << 15) /**< Shifted mode HIGH for ACMP_CTRL */
-#define _ACMP_CTRL_INPUTRANGE_SHIFT 18 /**< Shift value for ACMP_INPUTRANGE */
-#define _ACMP_CTRL_INPUTRANGE_MASK 0xC0000UL /**< Bit mask for ACMP_INPUTRANGE */
-#define _ACMP_CTRL_INPUTRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
-#define _ACMP_CTRL_INPUTRANGE_FULL 0x00000000UL /**< Mode FULL for ACMP_CTRL */
-#define _ACMP_CTRL_INPUTRANGE_GTVDDDIV2 0x00000001UL /**< Mode GTVDDDIV2 for ACMP_CTRL */
-#define _ACMP_CTRL_INPUTRANGE_LTVDDDIV2 0x00000002UL /**< Mode LTVDDDIV2 for ACMP_CTRL */
-#define ACMP_CTRL_INPUTRANGE_DEFAULT (_ACMP_CTRL_INPUTRANGE_DEFAULT << 18) /**< Shifted mode DEFAULT for ACMP_CTRL */
-#define ACMP_CTRL_INPUTRANGE_FULL (_ACMP_CTRL_INPUTRANGE_FULL << 18) /**< Shifted mode FULL for ACMP_CTRL */
-#define ACMP_CTRL_INPUTRANGE_GTVDDDIV2 (_ACMP_CTRL_INPUTRANGE_GTVDDDIV2 << 18) /**< Shifted mode GTVDDDIV2 for ACMP_CTRL */
-#define ACMP_CTRL_INPUTRANGE_LTVDDDIV2 (_ACMP_CTRL_INPUTRANGE_LTVDDDIV2 << 18) /**< Shifted mode LTVDDDIV2 for ACMP_CTRL */
-#define ACMP_CTRL_IRISE (0x1UL << 20) /**< Rising Edge Interrupt Sense */
-#define _ACMP_CTRL_IRISE_SHIFT 20 /**< Shift value for ACMP_IRISE */
-#define _ACMP_CTRL_IRISE_MASK 0x100000UL /**< Bit mask for ACMP_IRISE */
-#define _ACMP_CTRL_IRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
-#define _ACMP_CTRL_IRISE_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */
-#define _ACMP_CTRL_IRISE_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */
-#define ACMP_CTRL_IRISE_DEFAULT (_ACMP_CTRL_IRISE_DEFAULT << 20) /**< Shifted mode DEFAULT for ACMP_CTRL */
-#define ACMP_CTRL_IRISE_DISABLED (_ACMP_CTRL_IRISE_DISABLED << 20) /**< Shifted mode DISABLED for ACMP_CTRL */
-#define ACMP_CTRL_IRISE_ENABLED (_ACMP_CTRL_IRISE_ENABLED << 20) /**< Shifted mode ENABLED for ACMP_CTRL */
-#define ACMP_CTRL_IFALL (0x1UL << 21) /**< Falling Edge Interrupt Sense */
-#define _ACMP_CTRL_IFALL_SHIFT 21 /**< Shift value for ACMP_IFALL */
-#define _ACMP_CTRL_IFALL_MASK 0x200000UL /**< Bit mask for ACMP_IFALL */
-#define _ACMP_CTRL_IFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
-#define _ACMP_CTRL_IFALL_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */
-#define _ACMP_CTRL_IFALL_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */
-#define ACMP_CTRL_IFALL_DEFAULT (_ACMP_CTRL_IFALL_DEFAULT << 21) /**< Shifted mode DEFAULT for ACMP_CTRL */
-#define ACMP_CTRL_IFALL_DISABLED (_ACMP_CTRL_IFALL_DISABLED << 21) /**< Shifted mode DISABLED for ACMP_CTRL */
-#define ACMP_CTRL_IFALL_ENABLED (_ACMP_CTRL_IFALL_ENABLED << 21) /**< Shifted mode ENABLED for ACMP_CTRL */
-#define _ACMP_CTRL_BIASPROG_SHIFT 24 /**< Shift value for ACMP_BIASPROG */
-#define _ACMP_CTRL_BIASPROG_MASK 0x3F000000UL /**< Bit mask for ACMP_BIASPROG */
-#define _ACMP_CTRL_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for ACMP_CTRL */
-#define ACMP_CTRL_BIASPROG_DEFAULT (_ACMP_CTRL_BIASPROG_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_CTRL */
-#define ACMP_CTRL_FULLBIAS (0x1UL << 31) /**< Full Bias Current */
-#define _ACMP_CTRL_FULLBIAS_SHIFT 31 /**< Shift value for ACMP_FULLBIAS */
-#define _ACMP_CTRL_FULLBIAS_MASK 0x80000000UL /**< Bit mask for ACMP_FULLBIAS */
-#define _ACMP_CTRL_FULLBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
-#define ACMP_CTRL_FULLBIAS_DEFAULT (_ACMP_CTRL_FULLBIAS_DEFAULT << 31) /**< Shifted mode DEFAULT for ACMP_CTRL */
-
-/* Bit fields for ACMP INPUTSEL */
-#define _ACMP_INPUTSEL_RESETVALUE 0x00000000UL /**< Default value for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_MASK 0x757FFFFFUL /**< Mask for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_SHIFT 0 /**< Shift value for ACMP_POSSEL */
-#define _ACMP_INPUTSEL_POSSEL_MASK 0xFFUL /**< Bit mask for ACMP_POSSEL */
-#define _ACMP_INPUTSEL_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_DACOUT0 0x000000F2UL /**< Mode DACOUT0 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_DACOUT1 0x000000F3UL /**< Mode DACOUT1 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_VADIV 0x000000FDUL /**< Mode VADIV for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_VDD 0x000000FEUL /**< Mode VDD for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_POSSEL_VSS 0x000000FFUL /**< Mode VSS for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_DEFAULT (_ACMP_INPUTSEL_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0XCH0 (_ACMP_INPUTSEL_POSSEL_APORT0XCH0 << 0) /**< Shifted mode APORT0XCH0 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0XCH1 (_ACMP_INPUTSEL_POSSEL_APORT0XCH1 << 0) /**< Shifted mode APORT0XCH1 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0XCH2 (_ACMP_INPUTSEL_POSSEL_APORT0XCH2 << 0) /**< Shifted mode APORT0XCH2 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0XCH3 (_ACMP_INPUTSEL_POSSEL_APORT0XCH3 << 0) /**< Shifted mode APORT0XCH3 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0XCH4 (_ACMP_INPUTSEL_POSSEL_APORT0XCH4 << 0) /**< Shifted mode APORT0XCH4 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0XCH5 (_ACMP_INPUTSEL_POSSEL_APORT0XCH5 << 0) /**< Shifted mode APORT0XCH5 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0XCH6 (_ACMP_INPUTSEL_POSSEL_APORT0XCH6 << 0) /**< Shifted mode APORT0XCH6 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0XCH7 (_ACMP_INPUTSEL_POSSEL_APORT0XCH7 << 0) /**< Shifted mode APORT0XCH7 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0XCH8 (_ACMP_INPUTSEL_POSSEL_APORT0XCH8 << 0) /**< Shifted mode APORT0XCH8 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0XCH9 (_ACMP_INPUTSEL_POSSEL_APORT0XCH9 << 0) /**< Shifted mode APORT0XCH9 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0XCH10 (_ACMP_INPUTSEL_POSSEL_APORT0XCH10 << 0) /**< Shifted mode APORT0XCH10 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0XCH11 (_ACMP_INPUTSEL_POSSEL_APORT0XCH11 << 0) /**< Shifted mode APORT0XCH11 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0XCH12 (_ACMP_INPUTSEL_POSSEL_APORT0XCH12 << 0) /**< Shifted mode APORT0XCH12 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0XCH13 (_ACMP_INPUTSEL_POSSEL_APORT0XCH13 << 0) /**< Shifted mode APORT0XCH13 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0XCH14 (_ACMP_INPUTSEL_POSSEL_APORT0XCH14 << 0) /**< Shifted mode APORT0XCH14 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0XCH15 (_ACMP_INPUTSEL_POSSEL_APORT0XCH15 << 0) /**< Shifted mode APORT0XCH15 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0YCH0 (_ACMP_INPUTSEL_POSSEL_APORT0YCH0 << 0) /**< Shifted mode APORT0YCH0 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0YCH1 (_ACMP_INPUTSEL_POSSEL_APORT0YCH1 << 0) /**< Shifted mode APORT0YCH1 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0YCH2 (_ACMP_INPUTSEL_POSSEL_APORT0YCH2 << 0) /**< Shifted mode APORT0YCH2 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0YCH3 (_ACMP_INPUTSEL_POSSEL_APORT0YCH3 << 0) /**< Shifted mode APORT0YCH3 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0YCH4 (_ACMP_INPUTSEL_POSSEL_APORT0YCH4 << 0) /**< Shifted mode APORT0YCH4 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0YCH5 (_ACMP_INPUTSEL_POSSEL_APORT0YCH5 << 0) /**< Shifted mode APORT0YCH5 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0YCH6 (_ACMP_INPUTSEL_POSSEL_APORT0YCH6 << 0) /**< Shifted mode APORT0YCH6 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0YCH7 (_ACMP_INPUTSEL_POSSEL_APORT0YCH7 << 0) /**< Shifted mode APORT0YCH7 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0YCH8 (_ACMP_INPUTSEL_POSSEL_APORT0YCH8 << 0) /**< Shifted mode APORT0YCH8 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0YCH9 (_ACMP_INPUTSEL_POSSEL_APORT0YCH9 << 0) /**< Shifted mode APORT0YCH9 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0YCH10 (_ACMP_INPUTSEL_POSSEL_APORT0YCH10 << 0) /**< Shifted mode APORT0YCH10 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0YCH11 (_ACMP_INPUTSEL_POSSEL_APORT0YCH11 << 0) /**< Shifted mode APORT0YCH11 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0YCH12 (_ACMP_INPUTSEL_POSSEL_APORT0YCH12 << 0) /**< Shifted mode APORT0YCH12 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0YCH13 (_ACMP_INPUTSEL_POSSEL_APORT0YCH13 << 0) /**< Shifted mode APORT0YCH13 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0YCH14 (_ACMP_INPUTSEL_POSSEL_APORT0YCH14 << 0) /**< Shifted mode APORT0YCH14 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT0YCH15 (_ACMP_INPUTSEL_POSSEL_APORT0YCH15 << 0) /**< Shifted mode APORT0YCH15 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1XCH0 (_ACMP_INPUTSEL_POSSEL_APORT1XCH0 << 0) /**< Shifted mode APORT1XCH0 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1YCH1 (_ACMP_INPUTSEL_POSSEL_APORT1YCH1 << 0) /**< Shifted mode APORT1YCH1 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1XCH2 (_ACMP_INPUTSEL_POSSEL_APORT1XCH2 << 0) /**< Shifted mode APORT1XCH2 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1YCH3 (_ACMP_INPUTSEL_POSSEL_APORT1YCH3 << 0) /**< Shifted mode APORT1YCH3 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1XCH4 (_ACMP_INPUTSEL_POSSEL_APORT1XCH4 << 0) /**< Shifted mode APORT1XCH4 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1YCH5 (_ACMP_INPUTSEL_POSSEL_APORT1YCH5 << 0) /**< Shifted mode APORT1YCH5 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1XCH6 (_ACMP_INPUTSEL_POSSEL_APORT1XCH6 << 0) /**< Shifted mode APORT1XCH6 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1YCH7 (_ACMP_INPUTSEL_POSSEL_APORT1YCH7 << 0) /**< Shifted mode APORT1YCH7 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1XCH8 (_ACMP_INPUTSEL_POSSEL_APORT1XCH8 << 0) /**< Shifted mode APORT1XCH8 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1YCH9 (_ACMP_INPUTSEL_POSSEL_APORT1YCH9 << 0) /**< Shifted mode APORT1YCH9 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1XCH10 (_ACMP_INPUTSEL_POSSEL_APORT1XCH10 << 0) /**< Shifted mode APORT1XCH10 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1YCH11 (_ACMP_INPUTSEL_POSSEL_APORT1YCH11 << 0) /**< Shifted mode APORT1YCH11 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1XCH12 (_ACMP_INPUTSEL_POSSEL_APORT1XCH12 << 0) /**< Shifted mode APORT1XCH12 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1YCH13 (_ACMP_INPUTSEL_POSSEL_APORT1YCH13 << 0) /**< Shifted mode APORT1YCH13 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1XCH14 (_ACMP_INPUTSEL_POSSEL_APORT1XCH14 << 0) /**< Shifted mode APORT1XCH14 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1YCH15 (_ACMP_INPUTSEL_POSSEL_APORT1YCH15 << 0) /**< Shifted mode APORT1YCH15 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1XCH16 (_ACMP_INPUTSEL_POSSEL_APORT1XCH16 << 0) /**< Shifted mode APORT1XCH16 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1YCH17 (_ACMP_INPUTSEL_POSSEL_APORT1YCH17 << 0) /**< Shifted mode APORT1YCH17 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1XCH18 (_ACMP_INPUTSEL_POSSEL_APORT1XCH18 << 0) /**< Shifted mode APORT1XCH18 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1YCH19 (_ACMP_INPUTSEL_POSSEL_APORT1YCH19 << 0) /**< Shifted mode APORT1YCH19 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1XCH20 (_ACMP_INPUTSEL_POSSEL_APORT1XCH20 << 0) /**< Shifted mode APORT1XCH20 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1YCH21 (_ACMP_INPUTSEL_POSSEL_APORT1YCH21 << 0) /**< Shifted mode APORT1YCH21 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1XCH22 (_ACMP_INPUTSEL_POSSEL_APORT1XCH22 << 0) /**< Shifted mode APORT1XCH22 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1YCH23 (_ACMP_INPUTSEL_POSSEL_APORT1YCH23 << 0) /**< Shifted mode APORT1YCH23 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1XCH24 (_ACMP_INPUTSEL_POSSEL_APORT1XCH24 << 0) /**< Shifted mode APORT1XCH24 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1YCH25 (_ACMP_INPUTSEL_POSSEL_APORT1YCH25 << 0) /**< Shifted mode APORT1YCH25 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1XCH26 (_ACMP_INPUTSEL_POSSEL_APORT1XCH26 << 0) /**< Shifted mode APORT1XCH26 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1YCH27 (_ACMP_INPUTSEL_POSSEL_APORT1YCH27 << 0) /**< Shifted mode APORT1YCH27 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1XCH28 (_ACMP_INPUTSEL_POSSEL_APORT1XCH28 << 0) /**< Shifted mode APORT1XCH28 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1YCH29 (_ACMP_INPUTSEL_POSSEL_APORT1YCH29 << 0) /**< Shifted mode APORT1YCH29 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1XCH30 (_ACMP_INPUTSEL_POSSEL_APORT1XCH30 << 0) /**< Shifted mode APORT1XCH30 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT1YCH31 (_ACMP_INPUTSEL_POSSEL_APORT1YCH31 << 0) /**< Shifted mode APORT1YCH31 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2YCH0 (_ACMP_INPUTSEL_POSSEL_APORT2YCH0 << 0) /**< Shifted mode APORT2YCH0 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2XCH1 (_ACMP_INPUTSEL_POSSEL_APORT2XCH1 << 0) /**< Shifted mode APORT2XCH1 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2YCH2 (_ACMP_INPUTSEL_POSSEL_APORT2YCH2 << 0) /**< Shifted mode APORT2YCH2 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2XCH3 (_ACMP_INPUTSEL_POSSEL_APORT2XCH3 << 0) /**< Shifted mode APORT2XCH3 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2YCH4 (_ACMP_INPUTSEL_POSSEL_APORT2YCH4 << 0) /**< Shifted mode APORT2YCH4 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2XCH5 (_ACMP_INPUTSEL_POSSEL_APORT2XCH5 << 0) /**< Shifted mode APORT2XCH5 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2YCH6 (_ACMP_INPUTSEL_POSSEL_APORT2YCH6 << 0) /**< Shifted mode APORT2YCH6 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2XCH7 (_ACMP_INPUTSEL_POSSEL_APORT2XCH7 << 0) /**< Shifted mode APORT2XCH7 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2YCH8 (_ACMP_INPUTSEL_POSSEL_APORT2YCH8 << 0) /**< Shifted mode APORT2YCH8 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2XCH9 (_ACMP_INPUTSEL_POSSEL_APORT2XCH9 << 0) /**< Shifted mode APORT2XCH9 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2YCH10 (_ACMP_INPUTSEL_POSSEL_APORT2YCH10 << 0) /**< Shifted mode APORT2YCH10 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2XCH11 (_ACMP_INPUTSEL_POSSEL_APORT2XCH11 << 0) /**< Shifted mode APORT2XCH11 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2YCH12 (_ACMP_INPUTSEL_POSSEL_APORT2YCH12 << 0) /**< Shifted mode APORT2YCH12 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2XCH13 (_ACMP_INPUTSEL_POSSEL_APORT2XCH13 << 0) /**< Shifted mode APORT2XCH13 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2YCH14 (_ACMP_INPUTSEL_POSSEL_APORT2YCH14 << 0) /**< Shifted mode APORT2YCH14 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2XCH15 (_ACMP_INPUTSEL_POSSEL_APORT2XCH15 << 0) /**< Shifted mode APORT2XCH15 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2YCH16 (_ACMP_INPUTSEL_POSSEL_APORT2YCH16 << 0) /**< Shifted mode APORT2YCH16 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2XCH17 (_ACMP_INPUTSEL_POSSEL_APORT2XCH17 << 0) /**< Shifted mode APORT2XCH17 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2YCH18 (_ACMP_INPUTSEL_POSSEL_APORT2YCH18 << 0) /**< Shifted mode APORT2YCH18 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2XCH19 (_ACMP_INPUTSEL_POSSEL_APORT2XCH19 << 0) /**< Shifted mode APORT2XCH19 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2YCH20 (_ACMP_INPUTSEL_POSSEL_APORT2YCH20 << 0) /**< Shifted mode APORT2YCH20 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2XCH21 (_ACMP_INPUTSEL_POSSEL_APORT2XCH21 << 0) /**< Shifted mode APORT2XCH21 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2YCH22 (_ACMP_INPUTSEL_POSSEL_APORT2YCH22 << 0) /**< Shifted mode APORT2YCH22 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2XCH23 (_ACMP_INPUTSEL_POSSEL_APORT2XCH23 << 0) /**< Shifted mode APORT2XCH23 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2YCH24 (_ACMP_INPUTSEL_POSSEL_APORT2YCH24 << 0) /**< Shifted mode APORT2YCH24 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2XCH25 (_ACMP_INPUTSEL_POSSEL_APORT2XCH25 << 0) /**< Shifted mode APORT2XCH25 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2YCH26 (_ACMP_INPUTSEL_POSSEL_APORT2YCH26 << 0) /**< Shifted mode APORT2YCH26 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2XCH27 (_ACMP_INPUTSEL_POSSEL_APORT2XCH27 << 0) /**< Shifted mode APORT2XCH27 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2YCH28 (_ACMP_INPUTSEL_POSSEL_APORT2YCH28 << 0) /**< Shifted mode APORT2YCH28 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2XCH29 (_ACMP_INPUTSEL_POSSEL_APORT2XCH29 << 0) /**< Shifted mode APORT2XCH29 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2YCH30 (_ACMP_INPUTSEL_POSSEL_APORT2YCH30 << 0) /**< Shifted mode APORT2YCH30 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT2XCH31 (_ACMP_INPUTSEL_POSSEL_APORT2XCH31 << 0) /**< Shifted mode APORT2XCH31 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3XCH0 (_ACMP_INPUTSEL_POSSEL_APORT3XCH0 << 0) /**< Shifted mode APORT3XCH0 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3YCH1 (_ACMP_INPUTSEL_POSSEL_APORT3YCH1 << 0) /**< Shifted mode APORT3YCH1 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3XCH2 (_ACMP_INPUTSEL_POSSEL_APORT3XCH2 << 0) /**< Shifted mode APORT3XCH2 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3YCH3 (_ACMP_INPUTSEL_POSSEL_APORT3YCH3 << 0) /**< Shifted mode APORT3YCH3 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3XCH4 (_ACMP_INPUTSEL_POSSEL_APORT3XCH4 << 0) /**< Shifted mode APORT3XCH4 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3YCH5 (_ACMP_INPUTSEL_POSSEL_APORT3YCH5 << 0) /**< Shifted mode APORT3YCH5 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3XCH6 (_ACMP_INPUTSEL_POSSEL_APORT3XCH6 << 0) /**< Shifted mode APORT3XCH6 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3YCH7 (_ACMP_INPUTSEL_POSSEL_APORT3YCH7 << 0) /**< Shifted mode APORT3YCH7 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3XCH8 (_ACMP_INPUTSEL_POSSEL_APORT3XCH8 << 0) /**< Shifted mode APORT3XCH8 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3YCH9 (_ACMP_INPUTSEL_POSSEL_APORT3YCH9 << 0) /**< Shifted mode APORT3YCH9 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3XCH10 (_ACMP_INPUTSEL_POSSEL_APORT3XCH10 << 0) /**< Shifted mode APORT3XCH10 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3YCH11 (_ACMP_INPUTSEL_POSSEL_APORT3YCH11 << 0) /**< Shifted mode APORT3YCH11 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3XCH12 (_ACMP_INPUTSEL_POSSEL_APORT3XCH12 << 0) /**< Shifted mode APORT3XCH12 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3YCH13 (_ACMP_INPUTSEL_POSSEL_APORT3YCH13 << 0) /**< Shifted mode APORT3YCH13 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3XCH14 (_ACMP_INPUTSEL_POSSEL_APORT3XCH14 << 0) /**< Shifted mode APORT3XCH14 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3YCH15 (_ACMP_INPUTSEL_POSSEL_APORT3YCH15 << 0) /**< Shifted mode APORT3YCH15 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3XCH16 (_ACMP_INPUTSEL_POSSEL_APORT3XCH16 << 0) /**< Shifted mode APORT3XCH16 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3YCH17 (_ACMP_INPUTSEL_POSSEL_APORT3YCH17 << 0) /**< Shifted mode APORT3YCH17 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3XCH18 (_ACMP_INPUTSEL_POSSEL_APORT3XCH18 << 0) /**< Shifted mode APORT3XCH18 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3YCH19 (_ACMP_INPUTSEL_POSSEL_APORT3YCH19 << 0) /**< Shifted mode APORT3YCH19 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3XCH20 (_ACMP_INPUTSEL_POSSEL_APORT3XCH20 << 0) /**< Shifted mode APORT3XCH20 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3YCH21 (_ACMP_INPUTSEL_POSSEL_APORT3YCH21 << 0) /**< Shifted mode APORT3YCH21 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3XCH22 (_ACMP_INPUTSEL_POSSEL_APORT3XCH22 << 0) /**< Shifted mode APORT3XCH22 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3YCH23 (_ACMP_INPUTSEL_POSSEL_APORT3YCH23 << 0) /**< Shifted mode APORT3YCH23 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3XCH24 (_ACMP_INPUTSEL_POSSEL_APORT3XCH24 << 0) /**< Shifted mode APORT3XCH24 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3YCH25 (_ACMP_INPUTSEL_POSSEL_APORT3YCH25 << 0) /**< Shifted mode APORT3YCH25 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3XCH26 (_ACMP_INPUTSEL_POSSEL_APORT3XCH26 << 0) /**< Shifted mode APORT3XCH26 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3YCH27 (_ACMP_INPUTSEL_POSSEL_APORT3YCH27 << 0) /**< Shifted mode APORT3YCH27 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3XCH28 (_ACMP_INPUTSEL_POSSEL_APORT3XCH28 << 0) /**< Shifted mode APORT3XCH28 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3YCH29 (_ACMP_INPUTSEL_POSSEL_APORT3YCH29 << 0) /**< Shifted mode APORT3YCH29 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3XCH30 (_ACMP_INPUTSEL_POSSEL_APORT3XCH30 << 0) /**< Shifted mode APORT3XCH30 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT3YCH31 (_ACMP_INPUTSEL_POSSEL_APORT3YCH31 << 0) /**< Shifted mode APORT3YCH31 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4YCH0 (_ACMP_INPUTSEL_POSSEL_APORT4YCH0 << 0) /**< Shifted mode APORT4YCH0 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4XCH1 (_ACMP_INPUTSEL_POSSEL_APORT4XCH1 << 0) /**< Shifted mode APORT4XCH1 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4YCH2 (_ACMP_INPUTSEL_POSSEL_APORT4YCH2 << 0) /**< Shifted mode APORT4YCH2 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4XCH3 (_ACMP_INPUTSEL_POSSEL_APORT4XCH3 << 0) /**< Shifted mode APORT4XCH3 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4YCH4 (_ACMP_INPUTSEL_POSSEL_APORT4YCH4 << 0) /**< Shifted mode APORT4YCH4 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4XCH5 (_ACMP_INPUTSEL_POSSEL_APORT4XCH5 << 0) /**< Shifted mode APORT4XCH5 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4YCH6 (_ACMP_INPUTSEL_POSSEL_APORT4YCH6 << 0) /**< Shifted mode APORT4YCH6 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4XCH7 (_ACMP_INPUTSEL_POSSEL_APORT4XCH7 << 0) /**< Shifted mode APORT4XCH7 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4YCH8 (_ACMP_INPUTSEL_POSSEL_APORT4YCH8 << 0) /**< Shifted mode APORT4YCH8 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4XCH9 (_ACMP_INPUTSEL_POSSEL_APORT4XCH9 << 0) /**< Shifted mode APORT4XCH9 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4YCH10 (_ACMP_INPUTSEL_POSSEL_APORT4YCH10 << 0) /**< Shifted mode APORT4YCH10 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4XCH11 (_ACMP_INPUTSEL_POSSEL_APORT4XCH11 << 0) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4YCH12 (_ACMP_INPUTSEL_POSSEL_APORT4YCH12 << 0) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4XCH13 (_ACMP_INPUTSEL_POSSEL_APORT4XCH13 << 0) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4YCH16 (_ACMP_INPUTSEL_POSSEL_APORT4YCH16 << 0) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4XCH17 (_ACMP_INPUTSEL_POSSEL_APORT4XCH17 << 0) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4YCH18 (_ACMP_INPUTSEL_POSSEL_APORT4YCH18 << 0) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4XCH19 (_ACMP_INPUTSEL_POSSEL_APORT4XCH19 << 0) /**< Shifted mode APORT4XCH19 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4YCH20 (_ACMP_INPUTSEL_POSSEL_APORT4YCH20 << 0) /**< Shifted mode APORT4YCH20 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4XCH21 (_ACMP_INPUTSEL_POSSEL_APORT4XCH21 << 0) /**< Shifted mode APORT4XCH21 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4YCH22 (_ACMP_INPUTSEL_POSSEL_APORT4YCH22 << 0) /**< Shifted mode APORT4YCH22 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4XCH23 (_ACMP_INPUTSEL_POSSEL_APORT4XCH23 << 0) /**< Shifted mode APORT4XCH23 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4YCH24 (_ACMP_INPUTSEL_POSSEL_APORT4YCH24 << 0) /**< Shifted mode APORT4YCH24 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4XCH25 (_ACMP_INPUTSEL_POSSEL_APORT4XCH25 << 0) /**< Shifted mode APORT4XCH25 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4YCH26 (_ACMP_INPUTSEL_POSSEL_APORT4YCH26 << 0) /**< Shifted mode APORT4YCH26 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4XCH27 (_ACMP_INPUTSEL_POSSEL_APORT4XCH27 << 0) /**< Shifted mode APORT4XCH27 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4YCH28 (_ACMP_INPUTSEL_POSSEL_APORT4YCH28 << 0) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4XCH29 (_ACMP_INPUTSEL_POSSEL_APORT4XCH29 << 0) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4YCH30 (_ACMP_INPUTSEL_POSSEL_APORT4YCH30 << 0) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4YCH14 (_ACMP_INPUTSEL_POSSEL_APORT4YCH14 << 0) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4XCH15 (_ACMP_INPUTSEL_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_APORT4XCH31 (_ACMP_INPUTSEL_POSSEL_APORT4XCH31 << 0) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_DACOUT0 (_ACMP_INPUTSEL_POSSEL_DACOUT0 << 0) /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_DACOUT1 (_ACMP_INPUTSEL_POSSEL_DACOUT1 << 0) /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_VLP (_ACMP_INPUTSEL_POSSEL_VLP << 0) /**< Shifted mode VLP for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_VBDIV (_ACMP_INPUTSEL_POSSEL_VBDIV << 0) /**< Shifted mode VBDIV for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_VADIV (_ACMP_INPUTSEL_POSSEL_VADIV << 0) /**< Shifted mode VADIV for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_VDD (_ACMP_INPUTSEL_POSSEL_VDD << 0) /**< Shifted mode VDD for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_POSSEL_VSS (_ACMP_INPUTSEL_POSSEL_VSS << 0) /**< Shifted mode VSS for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_SHIFT 8 /**< Shift value for ACMP_NEGSEL */
-#define _ACMP_INPUTSEL_NEGSEL_MASK 0xFF00UL /**< Bit mask for ACMP_NEGSEL */
-#define _ACMP_INPUTSEL_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_DACOUT0 0x000000F2UL /**< Mode DACOUT0 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_DACOUT1 0x000000F3UL /**< Mode DACOUT1 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_VADIV 0x000000FDUL /**< Mode VADIV for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_VDD 0x000000FEUL /**< Mode VDD for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_NEGSEL_VSS 0x000000FFUL /**< Mode VSS for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_DEFAULT (_ACMP_INPUTSEL_NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0XCH0 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH0 << 8) /**< Shifted mode APORT0XCH0 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0XCH1 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH1 << 8) /**< Shifted mode APORT0XCH1 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0XCH2 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH2 << 8) /**< Shifted mode APORT0XCH2 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0XCH3 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH3 << 8) /**< Shifted mode APORT0XCH3 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0XCH4 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH4 << 8) /**< Shifted mode APORT0XCH4 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0XCH5 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH5 << 8) /**< Shifted mode APORT0XCH5 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0XCH6 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH6 << 8) /**< Shifted mode APORT0XCH6 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0XCH7 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH7 << 8) /**< Shifted mode APORT0XCH7 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0XCH8 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH8 << 8) /**< Shifted mode APORT0XCH8 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0XCH9 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH9 << 8) /**< Shifted mode APORT0XCH9 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0XCH10 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH10 << 8) /**< Shifted mode APORT0XCH10 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH11 << 8) /**< Shifted mode APORT0XCH11 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0XCH12 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH12 << 8) /**< Shifted mode APORT0XCH12 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH13 << 8) /**< Shifted mode APORT0XCH13 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0XCH14 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH14 << 8) /**< Shifted mode APORT0XCH14 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH15 << 8) /**< Shifted mode APORT0XCH15 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0YCH0 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH0 << 8) /**< Shifted mode APORT0YCH0 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0YCH1 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH1 << 8) /**< Shifted mode APORT0YCH1 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0YCH2 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH2 << 8) /**< Shifted mode APORT0YCH2 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0YCH3 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH3 << 8) /**< Shifted mode APORT0YCH3 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0YCH4 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH4 << 8) /**< Shifted mode APORT0YCH4 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0YCH5 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH5 << 8) /**< Shifted mode APORT0YCH5 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0YCH6 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH6 << 8) /**< Shifted mode APORT0YCH6 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0YCH7 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH7 << 8) /**< Shifted mode APORT0YCH7 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0YCH8 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH8 << 8) /**< Shifted mode APORT0YCH8 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0YCH9 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH9 << 8) /**< Shifted mode APORT0YCH9 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0YCH10 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH10 << 8) /**< Shifted mode APORT0YCH10 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0YCH11 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH11 << 8) /**< Shifted mode APORT0YCH11 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH12 << 8) /**< Shifted mode APORT0YCH12 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0YCH13 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH13 << 8) /**< Shifted mode APORT0YCH13 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH14 << 8) /**< Shifted mode APORT0YCH14 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT0YCH15 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH15 << 8) /**< Shifted mode APORT0YCH15 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1XCH0 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH0 << 8) /**< Shifted mode APORT1XCH0 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1YCH1 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH1 << 8) /**< Shifted mode APORT1YCH1 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1XCH2 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH2 << 8) /**< Shifted mode APORT1XCH2 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1YCH3 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH3 << 8) /**< Shifted mode APORT1YCH3 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1XCH4 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH4 << 8) /**< Shifted mode APORT1XCH4 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1YCH5 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH5 << 8) /**< Shifted mode APORT1YCH5 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1XCH6 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH6 << 8) /**< Shifted mode APORT1XCH6 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1YCH7 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH7 << 8) /**< Shifted mode APORT1YCH7 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1XCH8 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH8 << 8) /**< Shifted mode APORT1XCH8 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1YCH9 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH9 << 8) /**< Shifted mode APORT1YCH9 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1XCH10 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH10 << 8) /**< Shifted mode APORT1XCH10 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1YCH11 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH11 << 8) /**< Shifted mode APORT1YCH11 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1XCH12 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH12 << 8) /**< Shifted mode APORT1XCH12 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1YCH13 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH13 << 8) /**< Shifted mode APORT1YCH13 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1XCH14 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH14 << 8) /**< Shifted mode APORT1XCH14 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1YCH15 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH15 << 8) /**< Shifted mode APORT1YCH15 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1XCH16 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH16 << 8) /**< Shifted mode APORT1XCH16 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1YCH17 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH17 << 8) /**< Shifted mode APORT1YCH17 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1XCH18 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH18 << 8) /**< Shifted mode APORT1XCH18 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1YCH19 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH19 << 8) /**< Shifted mode APORT1YCH19 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1XCH20 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH20 << 8) /**< Shifted mode APORT1XCH20 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1YCH21 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH21 << 8) /**< Shifted mode APORT1YCH21 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1XCH22 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH22 << 8) /**< Shifted mode APORT1XCH22 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1YCH23 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH23 << 8) /**< Shifted mode APORT1YCH23 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1XCH24 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH24 << 8) /**< Shifted mode APORT1XCH24 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1YCH25 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH25 << 8) /**< Shifted mode APORT1YCH25 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1XCH26 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH26 << 8) /**< Shifted mode APORT1XCH26 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1YCH27 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH27 << 8) /**< Shifted mode APORT1YCH27 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1XCH28 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH28 << 8) /**< Shifted mode APORT1XCH28 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1YCH29 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH29 << 8) /**< Shifted mode APORT1YCH29 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1XCH30 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH30 << 8) /**< Shifted mode APORT1XCH30 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT1YCH31 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH31 << 8) /**< Shifted mode APORT1YCH31 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2YCH0 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH0 << 8) /**< Shifted mode APORT2YCH0 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2XCH1 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH1 << 8) /**< Shifted mode APORT2XCH1 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2YCH2 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH2 << 8) /**< Shifted mode APORT2YCH2 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2XCH3 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH3 << 8) /**< Shifted mode APORT2XCH3 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2YCH4 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH4 << 8) /**< Shifted mode APORT2YCH4 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2XCH5 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH5 << 8) /**< Shifted mode APORT2XCH5 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2YCH6 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH6 << 8) /**< Shifted mode APORT2YCH6 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2XCH7 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH7 << 8) /**< Shifted mode APORT2XCH7 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2YCH8 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH8 << 8) /**< Shifted mode APORT2YCH8 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2XCH9 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH9 << 8) /**< Shifted mode APORT2XCH9 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2YCH10 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH10 << 8) /**< Shifted mode APORT2YCH10 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH11 << 8) /**< Shifted mode APORT2XCH11 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH12 << 8) /**< Shifted mode APORT2YCH12 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH13 << 8) /**< Shifted mode APORT2XCH13 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH14 << 8) /**< Shifted mode APORT2YCH14 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH15 << 8) /**< Shifted mode APORT2XCH15 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2YCH16 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH16 << 8) /**< Shifted mode APORT2YCH16 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2XCH17 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH17 << 8) /**< Shifted mode APORT2XCH17 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2YCH18 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH18 << 8) /**< Shifted mode APORT2YCH18 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2XCH19 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH19 << 8) /**< Shifted mode APORT2XCH19 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2YCH20 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH20 << 8) /**< Shifted mode APORT2YCH20 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2XCH21 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH21 << 8) /**< Shifted mode APORT2XCH21 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2YCH22 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH22 << 8) /**< Shifted mode APORT2YCH22 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2XCH23 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH23 << 8) /**< Shifted mode APORT2XCH23 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2YCH24 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH24 << 8) /**< Shifted mode APORT2YCH24 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2XCH25 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH25 << 8) /**< Shifted mode APORT2XCH25 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2YCH26 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH26 << 8) /**< Shifted mode APORT2YCH26 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2XCH27 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH27 << 8) /**< Shifted mode APORT2XCH27 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2YCH28 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH28 << 8) /**< Shifted mode APORT2YCH28 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2XCH29 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH29 << 8) /**< Shifted mode APORT2XCH29 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2YCH30 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH30 << 8) /**< Shifted mode APORT2YCH30 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT2XCH31 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH31 << 8) /**< Shifted mode APORT2XCH31 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3XCH0 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH0 << 8) /**< Shifted mode APORT3XCH0 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3YCH1 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH1 << 8) /**< Shifted mode APORT3YCH1 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3XCH2 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH2 << 8) /**< Shifted mode APORT3XCH2 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3YCH3 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH3 << 8) /**< Shifted mode APORT3YCH3 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3XCH4 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH4 << 8) /**< Shifted mode APORT3XCH4 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3YCH5 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH5 << 8) /**< Shifted mode APORT3YCH5 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3XCH6 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH6 << 8) /**< Shifted mode APORT3XCH6 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3YCH7 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH7 << 8) /**< Shifted mode APORT3YCH7 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3XCH8 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH8 << 8) /**< Shifted mode APORT3XCH8 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3YCH9 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH9 << 8) /**< Shifted mode APORT3YCH9 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3XCH10 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH10 << 8) /**< Shifted mode APORT3XCH10 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3YCH11 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH11 << 8) /**< Shifted mode APORT3YCH11 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3XCH12 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH12 << 8) /**< Shifted mode APORT3XCH12 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3YCH13 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH13 << 8) /**< Shifted mode APORT3YCH13 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3XCH14 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH14 << 8) /**< Shifted mode APORT3XCH14 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3YCH15 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH15 << 8) /**< Shifted mode APORT3YCH15 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3XCH16 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH16 << 8) /**< Shifted mode APORT3XCH16 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3YCH17 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH17 << 8) /**< Shifted mode APORT3YCH17 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3XCH18 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH18 << 8) /**< Shifted mode APORT3XCH18 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3YCH19 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH19 << 8) /**< Shifted mode APORT3YCH19 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3XCH20 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH20 << 8) /**< Shifted mode APORT3XCH20 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3YCH21 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH21 << 8) /**< Shifted mode APORT3YCH21 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3XCH22 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH22 << 8) /**< Shifted mode APORT3XCH22 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3YCH23 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH23 << 8) /**< Shifted mode APORT3YCH23 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3XCH24 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH24 << 8) /**< Shifted mode APORT3XCH24 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3YCH25 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH25 << 8) /**< Shifted mode APORT3YCH25 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3XCH26 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH26 << 8) /**< Shifted mode APORT3XCH26 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3YCH27 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH27 << 8) /**< Shifted mode APORT3YCH27 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3XCH28 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH28 << 8) /**< Shifted mode APORT3XCH28 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3YCH29 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH29 << 8) /**< Shifted mode APORT3YCH29 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3XCH30 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH30 << 8) /**< Shifted mode APORT3XCH30 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT3YCH31 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH31 << 8) /**< Shifted mode APORT3YCH31 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4YCH0 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH0 << 8) /**< Shifted mode APORT4YCH0 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4XCH1 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH1 << 8) /**< Shifted mode APORT4XCH1 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4YCH2 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH2 << 8) /**< Shifted mode APORT4YCH2 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4XCH3 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH3 << 8) /**< Shifted mode APORT4XCH3 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4YCH4 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH4 << 8) /**< Shifted mode APORT4YCH4 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4XCH5 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH5 << 8) /**< Shifted mode APORT4XCH5 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4YCH6 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH6 << 8) /**< Shifted mode APORT4YCH6 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4XCH7 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH7 << 8) /**< Shifted mode APORT4XCH7 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4YCH8 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH8 << 8) /**< Shifted mode APORT4YCH8 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4XCH9 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH9 << 8) /**< Shifted mode APORT4XCH9 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4YCH10 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH10 << 8) /**< Shifted mode APORT4YCH10 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH11 << 8) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH13 << 8) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4YCH16 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4XCH17 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH17 << 8) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4YCH18 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4XCH19 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH19 << 8) /**< Shifted mode APORT4XCH19 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4YCH20 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH20 << 8) /**< Shifted mode APORT4YCH20 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4XCH21 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH21 << 8) /**< Shifted mode APORT4XCH21 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4YCH22 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH22 << 8) /**< Shifted mode APORT4YCH22 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4XCH23 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH23 << 8) /**< Shifted mode APORT4XCH23 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4YCH24 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH24 << 8) /**< Shifted mode APORT4YCH24 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4XCH25 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH25 << 8) /**< Shifted mode APORT4XCH25 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4YCH26 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH26 << 8) /**< Shifted mode APORT4YCH26 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4XCH27 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH27 << 8) /**< Shifted mode APORT4XCH27 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4YCH28 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4XCH29 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH29 << 8) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4YCH30 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_APORT4XCH31 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_DACOUT0 (_ACMP_INPUTSEL_NEGSEL_DACOUT0 << 8) /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_DACOUT1 (_ACMP_INPUTSEL_NEGSEL_DACOUT1 << 8) /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_VLP (_ACMP_INPUTSEL_NEGSEL_VLP << 8) /**< Shifted mode VLP for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_VBDIV (_ACMP_INPUTSEL_NEGSEL_VBDIV << 8) /**< Shifted mode VBDIV for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_VADIV (_ACMP_INPUTSEL_NEGSEL_VADIV << 8) /**< Shifted mode VADIV for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_VDD (_ACMP_INPUTSEL_NEGSEL_VDD << 8) /**< Shifted mode VDD for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_NEGSEL_VSS (_ACMP_INPUTSEL_NEGSEL_VSS << 8) /**< Shifted mode VSS for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_SHIFT 16 /**< Shift value for ACMP_VASEL */
-#define _ACMP_INPUTSEL_VASEL_MASK 0x3F0000UL /**< Bit mask for ACMP_VASEL */
-#define _ACMP_INPUTSEL_VASEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_VDD 0x00000000UL /**< Mode VDD for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT2YCH0 0x00000001UL /**< Mode APORT2YCH0 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT2YCH2 0x00000003UL /**< Mode APORT2YCH2 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT2YCH4 0x00000005UL /**< Mode APORT2YCH4 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT2YCH6 0x00000007UL /**< Mode APORT2YCH6 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT2YCH8 0x00000009UL /**< Mode APORT2YCH8 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT2YCH10 0x0000000BUL /**< Mode APORT2YCH10 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT2YCH12 0x0000000DUL /**< Mode APORT2YCH12 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT2YCH14 0x0000000FUL /**< Mode APORT2YCH14 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT2YCH16 0x00000011UL /**< Mode APORT2YCH16 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT2YCH18 0x00000013UL /**< Mode APORT2YCH18 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT2YCH20 0x00000015UL /**< Mode APORT2YCH20 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT2YCH22 0x00000017UL /**< Mode APORT2YCH22 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT2YCH24 0x00000019UL /**< Mode APORT2YCH24 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT2YCH26 0x0000001BUL /**< Mode APORT2YCH26 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT2YCH28 0x0000001DUL /**< Mode APORT2YCH28 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT2YCH30 0x0000001FUL /**< Mode APORT2YCH30 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VASEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_DEFAULT (_ACMP_INPUTSEL_VASEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_VDD (_ACMP_INPUTSEL_VASEL_VDD << 16) /**< Shifted mode VDD for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT2YCH0 (_ACMP_INPUTSEL_VASEL_APORT2YCH0 << 16) /**< Shifted mode APORT2YCH0 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT2YCH2 (_ACMP_INPUTSEL_VASEL_APORT2YCH2 << 16) /**< Shifted mode APORT2YCH2 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT2YCH4 (_ACMP_INPUTSEL_VASEL_APORT2YCH4 << 16) /**< Shifted mode APORT2YCH4 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT2YCH6 (_ACMP_INPUTSEL_VASEL_APORT2YCH6 << 16) /**< Shifted mode APORT2YCH6 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT2YCH8 (_ACMP_INPUTSEL_VASEL_APORT2YCH8 << 16) /**< Shifted mode APORT2YCH8 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT2YCH10 (_ACMP_INPUTSEL_VASEL_APORT2YCH10 << 16) /**< Shifted mode APORT2YCH10 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT2YCH12 (_ACMP_INPUTSEL_VASEL_APORT2YCH12 << 16) /**< Shifted mode APORT2YCH12 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT2YCH14 (_ACMP_INPUTSEL_VASEL_APORT2YCH14 << 16) /**< Shifted mode APORT2YCH14 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT2YCH16 (_ACMP_INPUTSEL_VASEL_APORT2YCH16 << 16) /**< Shifted mode APORT2YCH16 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT2YCH18 (_ACMP_INPUTSEL_VASEL_APORT2YCH18 << 16) /**< Shifted mode APORT2YCH18 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT2YCH20 (_ACMP_INPUTSEL_VASEL_APORT2YCH20 << 16) /**< Shifted mode APORT2YCH20 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT2YCH22 (_ACMP_INPUTSEL_VASEL_APORT2YCH22 << 16) /**< Shifted mode APORT2YCH22 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT2YCH24 (_ACMP_INPUTSEL_VASEL_APORT2YCH24 << 16) /**< Shifted mode APORT2YCH24 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT2YCH26 (_ACMP_INPUTSEL_VASEL_APORT2YCH26 << 16) /**< Shifted mode APORT2YCH26 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT2YCH28 (_ACMP_INPUTSEL_VASEL_APORT2YCH28 << 16) /**< Shifted mode APORT2YCH28 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT2YCH30 (_ACMP_INPUTSEL_VASEL_APORT2YCH30 << 16) /**< Shifted mode APORT2YCH30 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1XCH0 (_ACMP_INPUTSEL_VASEL_APORT1XCH0 << 16) /**< Shifted mode APORT1XCH0 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1YCH1 (_ACMP_INPUTSEL_VASEL_APORT1YCH1 << 16) /**< Shifted mode APORT1YCH1 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1XCH2 (_ACMP_INPUTSEL_VASEL_APORT1XCH2 << 16) /**< Shifted mode APORT1XCH2 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1YCH3 (_ACMP_INPUTSEL_VASEL_APORT1YCH3 << 16) /**< Shifted mode APORT1YCH3 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1XCH4 (_ACMP_INPUTSEL_VASEL_APORT1XCH4 << 16) /**< Shifted mode APORT1XCH4 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1YCH5 (_ACMP_INPUTSEL_VASEL_APORT1YCH5 << 16) /**< Shifted mode APORT1YCH5 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1XCH6 (_ACMP_INPUTSEL_VASEL_APORT1XCH6 << 16) /**< Shifted mode APORT1XCH6 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1YCH7 (_ACMP_INPUTSEL_VASEL_APORT1YCH7 << 16) /**< Shifted mode APORT1YCH7 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1XCH8 (_ACMP_INPUTSEL_VASEL_APORT1XCH8 << 16) /**< Shifted mode APORT1XCH8 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1YCH9 (_ACMP_INPUTSEL_VASEL_APORT1YCH9 << 16) /**< Shifted mode APORT1YCH9 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1XCH10 (_ACMP_INPUTSEL_VASEL_APORT1XCH10 << 16) /**< Shifted mode APORT1XCH10 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1YCH11 (_ACMP_INPUTSEL_VASEL_APORT1YCH11 << 16) /**< Shifted mode APORT1YCH11 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1XCH12 (_ACMP_INPUTSEL_VASEL_APORT1XCH12 << 16) /**< Shifted mode APORT1XCH12 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1YCH13 (_ACMP_INPUTSEL_VASEL_APORT1YCH13 << 16) /**< Shifted mode APORT1YCH13 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1XCH14 (_ACMP_INPUTSEL_VASEL_APORT1XCH14 << 16) /**< Shifted mode APORT1XCH14 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1YCH15 (_ACMP_INPUTSEL_VASEL_APORT1YCH15 << 16) /**< Shifted mode APORT1YCH15 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1XCH16 (_ACMP_INPUTSEL_VASEL_APORT1XCH16 << 16) /**< Shifted mode APORT1XCH16 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1YCH17 (_ACMP_INPUTSEL_VASEL_APORT1YCH17 << 16) /**< Shifted mode APORT1YCH17 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1XCH18 (_ACMP_INPUTSEL_VASEL_APORT1XCH18 << 16) /**< Shifted mode APORT1XCH18 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1YCH19 (_ACMP_INPUTSEL_VASEL_APORT1YCH19 << 16) /**< Shifted mode APORT1YCH19 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1XCH20 (_ACMP_INPUTSEL_VASEL_APORT1XCH20 << 16) /**< Shifted mode APORT1XCH20 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1YCH21 (_ACMP_INPUTSEL_VASEL_APORT1YCH21 << 16) /**< Shifted mode APORT1YCH21 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1XCH22 (_ACMP_INPUTSEL_VASEL_APORT1XCH22 << 16) /**< Shifted mode APORT1XCH22 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1YCH23 (_ACMP_INPUTSEL_VASEL_APORT1YCH23 << 16) /**< Shifted mode APORT1YCH23 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1XCH24 (_ACMP_INPUTSEL_VASEL_APORT1XCH24 << 16) /**< Shifted mode APORT1XCH24 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1YCH25 (_ACMP_INPUTSEL_VASEL_APORT1YCH25 << 16) /**< Shifted mode APORT1YCH25 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1XCH26 (_ACMP_INPUTSEL_VASEL_APORT1XCH26 << 16) /**< Shifted mode APORT1XCH26 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1YCH27 (_ACMP_INPUTSEL_VASEL_APORT1YCH27 << 16) /**< Shifted mode APORT1YCH27 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1XCH28 (_ACMP_INPUTSEL_VASEL_APORT1XCH28 << 16) /**< Shifted mode APORT1XCH28 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1YCH29 (_ACMP_INPUTSEL_VASEL_APORT1YCH29 << 16) /**< Shifted mode APORT1YCH29 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1XCH30 (_ACMP_INPUTSEL_VASEL_APORT1XCH30 << 16) /**< Shifted mode APORT1XCH30 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VASEL_APORT1YCH31 (_ACMP_INPUTSEL_VASEL_APORT1YCH31 << 16) /**< Shifted mode APORT1YCH31 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VBSEL (0x1UL << 22) /**< VB Selection */
-#define _ACMP_INPUTSEL_VBSEL_SHIFT 22 /**< Shift value for ACMP_VBSEL */
-#define _ACMP_INPUTSEL_VBSEL_MASK 0x400000UL /**< Bit mask for ACMP_VBSEL */
-#define _ACMP_INPUTSEL_VBSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VBSEL_1V25 0x00000000UL /**< Mode 1V25 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VBSEL_2V5 0x00000001UL /**< Mode 2V5 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VBSEL_DEFAULT (_ACMP_INPUTSEL_VBSEL_DEFAULT << 22) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VBSEL_1V25 (_ACMP_INPUTSEL_VBSEL_1V25 << 22) /**< Shifted mode 1V25 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VBSEL_2V5 (_ACMP_INPUTSEL_VBSEL_2V5 << 22) /**< Shifted mode 2V5 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VLPSEL (0x1UL << 24) /**< Low-Power Sampled Voltage Selection */
-#define _ACMP_INPUTSEL_VLPSEL_SHIFT 24 /**< Shift value for ACMP_VLPSEL */
-#define _ACMP_INPUTSEL_VLPSEL_MASK 0x1000000UL /**< Bit mask for ACMP_VLPSEL */
-#define _ACMP_INPUTSEL_VLPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VLPSEL_VADIV 0x00000000UL /**< Mode VADIV for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_VLPSEL_VBDIV 0x00000001UL /**< Mode VBDIV for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VLPSEL_DEFAULT (_ACMP_INPUTSEL_VLPSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VLPSEL_VADIV (_ACMP_INPUTSEL_VLPSEL_VADIV << 24) /**< Shifted mode VADIV for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_VLPSEL_VBDIV (_ACMP_INPUTSEL_VLPSEL_VBDIV << 24) /**< Shifted mode VBDIV for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_CSRESEN (0x1UL << 26) /**< Capacitive Sense Mode Internal Resistor Enable */
-#define _ACMP_INPUTSEL_CSRESEN_SHIFT 26 /**< Shift value for ACMP_CSRESEN */
-#define _ACMP_INPUTSEL_CSRESEN_MASK 0x4000000UL /**< Bit mask for ACMP_CSRESEN */
-#define _ACMP_INPUTSEL_CSRESEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_CSRESEN_DEFAULT (_ACMP_INPUTSEL_CSRESEN_DEFAULT << 26) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_CSRESSEL_SHIFT 28 /**< Shift value for ACMP_CSRESSEL */
-#define _ACMP_INPUTSEL_CSRESSEL_MASK 0x70000000UL /**< Bit mask for ACMP_CSRESSEL */
-#define _ACMP_INPUTSEL_CSRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_CSRESSEL_RES0 0x00000000UL /**< Mode RES0 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_CSRESSEL_RES1 0x00000001UL /**< Mode RES1 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_CSRESSEL_RES2 0x00000002UL /**< Mode RES2 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_CSRESSEL_RES3 0x00000003UL /**< Mode RES3 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_CSRESSEL_RES4 0x00000004UL /**< Mode RES4 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_CSRESSEL_RES5 0x00000005UL /**< Mode RES5 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_CSRESSEL_RES6 0x00000006UL /**< Mode RES6 for ACMP_INPUTSEL */
-#define _ACMP_INPUTSEL_CSRESSEL_RES7 0x00000007UL /**< Mode RES7 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_CSRESSEL_DEFAULT (_ACMP_INPUTSEL_CSRESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_CSRESSEL_RES0 (_ACMP_INPUTSEL_CSRESSEL_RES0 << 28) /**< Shifted mode RES0 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_CSRESSEL_RES1 (_ACMP_INPUTSEL_CSRESSEL_RES1 << 28) /**< Shifted mode RES1 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_CSRESSEL_RES2 (_ACMP_INPUTSEL_CSRESSEL_RES2 << 28) /**< Shifted mode RES2 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_CSRESSEL_RES3 (_ACMP_INPUTSEL_CSRESSEL_RES3 << 28) /**< Shifted mode RES3 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_CSRESSEL_RES4 (_ACMP_INPUTSEL_CSRESSEL_RES4 << 28) /**< Shifted mode RES4 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_CSRESSEL_RES5 (_ACMP_INPUTSEL_CSRESSEL_RES5 << 28) /**< Shifted mode RES5 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_CSRESSEL_RES6 (_ACMP_INPUTSEL_CSRESSEL_RES6 << 28) /**< Shifted mode RES6 for ACMP_INPUTSEL */
-#define ACMP_INPUTSEL_CSRESSEL_RES7 (_ACMP_INPUTSEL_CSRESSEL_RES7 << 28) /**< Shifted mode RES7 for ACMP_INPUTSEL */
-
-/* Bit fields for ACMP STATUS */
-#define _ACMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for ACMP_STATUS */
-#define _ACMP_STATUS_MASK 0x0000000FUL /**< Mask for ACMP_STATUS */
-#define ACMP_STATUS_ACMPACT (0x1UL << 0) /**< Analog Comparator Active */
-#define _ACMP_STATUS_ACMPACT_SHIFT 0 /**< Shift value for ACMP_ACMPACT */
-#define _ACMP_STATUS_ACMPACT_MASK 0x1UL /**< Bit mask for ACMP_ACMPACT */
-#define _ACMP_STATUS_ACMPACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */
-#define ACMP_STATUS_ACMPACT_DEFAULT (_ACMP_STATUS_ACMPACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_STATUS */
-#define ACMP_STATUS_ACMPOUT (0x1UL << 1) /**< Analog Comparator Output */
-#define _ACMP_STATUS_ACMPOUT_SHIFT 1 /**< Shift value for ACMP_ACMPOUT */
-#define _ACMP_STATUS_ACMPOUT_MASK 0x2UL /**< Bit mask for ACMP_ACMPOUT */
-#define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */
-#define ACMP_STATUS_ACMPOUT_DEFAULT (_ACMP_STATUS_ACMPOUT_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_STATUS */
-#define ACMP_STATUS_APORTCONFLICT (0x1UL << 2) /**< APORT Conflict Output */
-#define _ACMP_STATUS_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */
-#define _ACMP_STATUS_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */
-#define _ACMP_STATUS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */
-#define ACMP_STATUS_APORTCONFLICT_DEFAULT (_ACMP_STATUS_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_STATUS */
-#define ACMP_STATUS_EXTIFACT (0x1UL << 3) /**< External Override Interface Active */
-#define _ACMP_STATUS_EXTIFACT_SHIFT 3 /**< Shift value for ACMP_EXTIFACT */
-#define _ACMP_STATUS_EXTIFACT_MASK 0x8UL /**< Bit mask for ACMP_EXTIFACT */
-#define _ACMP_STATUS_EXTIFACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */
-#define ACMP_STATUS_EXTIFACT_DEFAULT (_ACMP_STATUS_EXTIFACT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_STATUS */
-
-/* Bit fields for ACMP IF */
-#define _ACMP_IF_RESETVALUE 0x00000000UL /**< Default value for ACMP_IF */
-#define _ACMP_IF_MASK 0x00000007UL /**< Mask for ACMP_IF */
-#define ACMP_IF_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag */
-#define _ACMP_IF_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */
-#define _ACMP_IF_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */
-#define _ACMP_IF_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */
-#define ACMP_IF_EDGE_DEFAULT (_ACMP_IF_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IF */
-#define ACMP_IF_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag */
-#define _ACMP_IF_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */
-#define _ACMP_IF_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */
-#define _ACMP_IF_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */
-#define ACMP_IF_WARMUP_DEFAULT (_ACMP_IF_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IF */
-#define ACMP_IF_APORTCONFLICT (0x1UL << 2) /**< APORT Conflict Interrupt Flag */
-#define _ACMP_IF_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */
-#define _ACMP_IF_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */
-#define _ACMP_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */
-#define ACMP_IF_APORTCONFLICT_DEFAULT (_ACMP_IF_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IF */
-
-/* Bit fields for ACMP IFS */
-#define _ACMP_IFS_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFS */
-#define _ACMP_IFS_MASK 0x00000007UL /**< Mask for ACMP_IFS */
-#define ACMP_IFS_EDGE (0x1UL << 0) /**< Set EDGE Interrupt Flag */
-#define _ACMP_IFS_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */
-#define _ACMP_IFS_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */
-#define _ACMP_IFS_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */
-#define ACMP_IFS_EDGE_DEFAULT (_ACMP_IFS_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IFS */
-#define ACMP_IFS_WARMUP (0x1UL << 1) /**< Set WARMUP Interrupt Flag */
-#define _ACMP_IFS_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */
-#define _ACMP_IFS_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */
-#define _ACMP_IFS_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */
-#define ACMP_IFS_WARMUP_DEFAULT (_ACMP_IFS_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IFS */
-#define ACMP_IFS_APORTCONFLICT (0x1UL << 2) /**< Set APORTCONFLICT Interrupt Flag */
-#define _ACMP_IFS_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */
-#define _ACMP_IFS_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */
-#define _ACMP_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */
-#define ACMP_IFS_APORTCONFLICT_DEFAULT (_ACMP_IFS_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IFS */
-
-/* Bit fields for ACMP IFC */
-#define _ACMP_IFC_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFC */
-#define _ACMP_IFC_MASK 0x00000007UL /**< Mask for ACMP_IFC */
-#define ACMP_IFC_EDGE (0x1UL << 0) /**< Clear EDGE Interrupt Flag */
-#define _ACMP_IFC_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */
-#define _ACMP_IFC_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */
-#define _ACMP_IFC_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */
-#define ACMP_IFC_EDGE_DEFAULT (_ACMP_IFC_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IFC */
-#define ACMP_IFC_WARMUP (0x1UL << 1) /**< Clear WARMUP Interrupt Flag */
-#define _ACMP_IFC_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */
-#define _ACMP_IFC_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */
-#define _ACMP_IFC_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */
-#define ACMP_IFC_WARMUP_DEFAULT (_ACMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IFC */
-#define ACMP_IFC_APORTCONFLICT (0x1UL << 2) /**< Clear APORTCONFLICT Interrupt Flag */
-#define _ACMP_IFC_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */
-#define _ACMP_IFC_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */
-#define _ACMP_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */
-#define ACMP_IFC_APORTCONFLICT_DEFAULT (_ACMP_IFC_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IFC */
-
-/* Bit fields for ACMP IEN */
-#define _ACMP_IEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_IEN */
-#define _ACMP_IEN_MASK 0x00000007UL /**< Mask for ACMP_IEN */
-#define ACMP_IEN_EDGE (0x1UL << 0) /**< EDGE Interrupt Enable */
-#define _ACMP_IEN_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */
-#define _ACMP_IEN_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */
-#define _ACMP_IEN_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */
-#define ACMP_IEN_EDGE_DEFAULT (_ACMP_IEN_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IEN */
-#define ACMP_IEN_WARMUP (0x1UL << 1) /**< WARMUP Interrupt Enable */
-#define _ACMP_IEN_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */
-#define _ACMP_IEN_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */
-#define _ACMP_IEN_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */
-#define ACMP_IEN_WARMUP_DEFAULT (_ACMP_IEN_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IEN */
-#define ACMP_IEN_APORTCONFLICT (0x1UL << 2) /**< APORTCONFLICT Interrupt Enable */
-#define _ACMP_IEN_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */
-#define _ACMP_IEN_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */
-#define _ACMP_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */
-#define ACMP_IEN_APORTCONFLICT_DEFAULT (_ACMP_IEN_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IEN */
-
-/* Bit fields for ACMP APORTREQ */
-#define _ACMP_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for ACMP_APORTREQ */
-#define _ACMP_APORTREQ_MASK 0x000003FFUL /**< Mask for ACMP_APORTREQ */
-#define ACMP_APORTREQ_APORT0XREQ (0x1UL << 0) /**< 1 If the Bus Connected to APORT0X is Requested */
-#define _ACMP_APORTREQ_APORT0XREQ_SHIFT 0 /**< Shift value for ACMP_APORT0XREQ */
-#define _ACMP_APORTREQ_APORT0XREQ_MASK 0x1UL /**< Bit mask for ACMP_APORT0XREQ */
-#define _ACMP_APORTREQ_APORT0XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
-#define ACMP_APORTREQ_APORT0XREQ_DEFAULT (_ACMP_APORTREQ_APORT0XREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
-#define ACMP_APORTREQ_APORT0YREQ (0x1UL << 1) /**< 1 If the Bus Connected to APORT0Y is Requested */
-#define _ACMP_APORTREQ_APORT0YREQ_SHIFT 1 /**< Shift value for ACMP_APORT0YREQ */
-#define _ACMP_APORTREQ_APORT0YREQ_MASK 0x2UL /**< Bit mask for ACMP_APORT0YREQ */
-#define _ACMP_APORTREQ_APORT0YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
-#define ACMP_APORTREQ_APORT0YREQ_DEFAULT (_ACMP_APORTREQ_APORT0YREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
-#define ACMP_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 If the Bus Connected to APORT2X is Requested */
-#define _ACMP_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for ACMP_APORT1XREQ */
-#define _ACMP_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for ACMP_APORT1XREQ */
-#define _ACMP_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
-#define ACMP_APORTREQ_APORT1XREQ_DEFAULT (_ACMP_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
-#define ACMP_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 If the Bus Connected to APORT1X is Requested */
-#define _ACMP_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for ACMP_APORT1YREQ */
-#define _ACMP_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for ACMP_APORT1YREQ */
-#define _ACMP_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
-#define ACMP_APORTREQ_APORT1YREQ_DEFAULT (_ACMP_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
-#define ACMP_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is Requested */
-#define _ACMP_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for ACMP_APORT2XREQ */
-#define _ACMP_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for ACMP_APORT2XREQ */
-#define _ACMP_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
-#define ACMP_APORTREQ_APORT2XREQ_DEFAULT (_ACMP_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
-#define ACMP_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is Requested */
-#define _ACMP_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for ACMP_APORT2YREQ */
-#define _ACMP_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for ACMP_APORT2YREQ */
-#define _ACMP_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
-#define ACMP_APORTREQ_APORT2YREQ_DEFAULT (_ACMP_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
-#define ACMP_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is Requested */
-#define _ACMP_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for ACMP_APORT3XREQ */
-#define _ACMP_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for ACMP_APORT3XREQ */
-#define _ACMP_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
-#define ACMP_APORTREQ_APORT3XREQ_DEFAULT (_ACMP_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
-#define ACMP_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is Requested */
-#define _ACMP_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for ACMP_APORT3YREQ */
-#define _ACMP_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for ACMP_APORT3YREQ */
-#define _ACMP_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
-#define ACMP_APORTREQ_APORT3YREQ_DEFAULT (_ACMP_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
-#define ACMP_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is Requested */
-#define _ACMP_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for ACMP_APORT4XREQ */
-#define _ACMP_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for ACMP_APORT4XREQ */
-#define _ACMP_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
-#define ACMP_APORTREQ_APORT4XREQ_DEFAULT (_ACMP_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
-#define ACMP_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is Requested */
-#define _ACMP_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for ACMP_APORT4YREQ */
-#define _ACMP_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for ACMP_APORT4YREQ */
-#define _ACMP_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */
-#define ACMP_APORTREQ_APORT4YREQ_DEFAULT (_ACMP_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for ACMP_APORTREQ */
-
-/* Bit fields for ACMP APORTCONFLICT */
-#define _ACMP_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for ACMP_APORTCONFLICT */
-#define _ACMP_APORTCONFLICT_MASK 0x000003FFUL /**< Mask for ACMP_APORTCONFLICT */
-#define ACMP_APORTCONFLICT_APORT0XCONFLICT (0x1UL << 0) /**< 1 If the Bus Connected to APORT0X is in Conflict With Another Peripheral */
-#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_SHIFT 0 /**< Shift value for ACMP_APORT0XCONFLICT */
-#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_MASK 0x1UL /**< Bit mask for ACMP_APORT0XCONFLICT */
-#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
-#define ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
-#define ACMP_APORTCONFLICT_APORT0YCONFLICT (0x1UL << 1) /**< 1 If the Bus Connected to APORT0Y is in Conflict With Another Peripheral */
-#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_SHIFT 1 /**< Shift value for ACMP_APORT0YCONFLICT */
-#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_MASK 0x2UL /**< Bit mask for ACMP_APORT0YCONFLICT */
-#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
-#define ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
-#define ACMP_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */
-#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORT1XCONFLICT */
-#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORT1XCONFLICT */
-#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
-#define ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
-#define ACMP_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */
-#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for ACMP_APORT1YCONFLICT */
-#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_APORT1YCONFLICT */
-#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
-#define ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
-#define ACMP_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is in Conflict With Another Peripheral */
-#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for ACMP_APORT2XCONFLICT */
-#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for ACMP_APORT2XCONFLICT */
-#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
-#define ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
-#define ACMP_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is in Conflict With Another Peripheral */
-#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for ACMP_APORT2YCONFLICT */
-#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for ACMP_APORT2YCONFLICT */
-#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
-#define ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
-#define ACMP_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is in Conflict With Another Peripheral */
-#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for ACMP_APORT3XCONFLICT */
-#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for ACMP_APORT3XCONFLICT */
-#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
-#define ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
-#define ACMP_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is in Conflict With Another Peripheral */
-#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for ACMP_APORT3YCONFLICT */
-#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for ACMP_APORT3YCONFLICT */
-#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
-#define ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
-#define ACMP_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is in Conflict With Another Peripheral */
-#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for ACMP_APORT4XCONFLICT */
-#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for ACMP_APORT4XCONFLICT */
-#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
-#define ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
-#define ACMP_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is in Conflict With Another Peripheral */
-#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for ACMP_APORT4YCONFLICT */
-#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for ACMP_APORT4YCONFLICT */
-#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */
-#define ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */
-
-/* Bit fields for ACMP HYSTERESIS0 */
-#define _ACMP_HYSTERESIS0_RESETVALUE 0x00000000UL /**< Default value for ACMP_HYSTERESIS0 */
-#define _ACMP_HYSTERESIS0_MASK 0x3F3F000FUL /**< Mask for ACMP_HYSTERESIS0 */
-#define _ACMP_HYSTERESIS0_HYST_SHIFT 0 /**< Shift value for ACMP_HYST */
-#define _ACMP_HYSTERESIS0_HYST_MASK 0xFUL /**< Bit mask for ACMP_HYST */
-#define _ACMP_HYSTERESIS0_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS0 */
-#define _ACMP_HYSTERESIS0_HYST_HYST0 0x00000000UL /**< Mode HYST0 for ACMP_HYSTERESIS0 */
-#define _ACMP_HYSTERESIS0_HYST_HYST1 0x00000001UL /**< Mode HYST1 for ACMP_HYSTERESIS0 */
-#define _ACMP_HYSTERESIS0_HYST_HYST2 0x00000002UL /**< Mode HYST2 for ACMP_HYSTERESIS0 */
-#define _ACMP_HYSTERESIS0_HYST_HYST3 0x00000003UL /**< Mode HYST3 for ACMP_HYSTERESIS0 */
-#define _ACMP_HYSTERESIS0_HYST_HYST4 0x00000004UL /**< Mode HYST4 for ACMP_HYSTERESIS0 */
-#define _ACMP_HYSTERESIS0_HYST_HYST5 0x00000005UL /**< Mode HYST5 for ACMP_HYSTERESIS0 */
-#define _ACMP_HYSTERESIS0_HYST_HYST6 0x00000006UL /**< Mode HYST6 for ACMP_HYSTERESIS0 */
-#define _ACMP_HYSTERESIS0_HYST_HYST7 0x00000007UL /**< Mode HYST7 for ACMP_HYSTERESIS0 */
-#define _ACMP_HYSTERESIS0_HYST_HYST8 0x00000008UL /**< Mode HYST8 for ACMP_HYSTERESIS0 */
-#define _ACMP_HYSTERESIS0_HYST_HYST9 0x00000009UL /**< Mode HYST9 for ACMP_HYSTERESIS0 */
-#define _ACMP_HYSTERESIS0_HYST_HYST10 0x0000000AUL /**< Mode HYST10 for ACMP_HYSTERESIS0 */
-#define _ACMP_HYSTERESIS0_HYST_HYST11 0x0000000BUL /**< Mode HYST11 for ACMP_HYSTERESIS0 */
-#define _ACMP_HYSTERESIS0_HYST_HYST12 0x0000000CUL /**< Mode HYST12 for ACMP_HYSTERESIS0 */
-#define _ACMP_HYSTERESIS0_HYST_HYST13 0x0000000DUL /**< Mode HYST13 for ACMP_HYSTERESIS0 */
-#define _ACMP_HYSTERESIS0_HYST_HYST14 0x0000000EUL /**< Mode HYST14 for ACMP_HYSTERESIS0 */
-#define _ACMP_HYSTERESIS0_HYST_HYST15 0x0000000FUL /**< Mode HYST15 for ACMP_HYSTERESIS0 */
-#define ACMP_HYSTERESIS0_HYST_DEFAULT (_ACMP_HYSTERESIS0_HYST_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS0 */
-#define ACMP_HYSTERESIS0_HYST_HYST0 (_ACMP_HYSTERESIS0_HYST_HYST0 << 0) /**< Shifted mode HYST0 for ACMP_HYSTERESIS0 */
-#define ACMP_HYSTERESIS0_HYST_HYST1 (_ACMP_HYSTERESIS0_HYST_HYST1 << 0) /**< Shifted mode HYST1 for ACMP_HYSTERESIS0 */
-#define ACMP_HYSTERESIS0_HYST_HYST2 (_ACMP_HYSTERESIS0_HYST_HYST2 << 0) /**< Shifted mode HYST2 for ACMP_HYSTERESIS0 */
-#define ACMP_HYSTERESIS0_HYST_HYST3 (_ACMP_HYSTERESIS0_HYST_HYST3 << 0) /**< Shifted mode HYST3 for ACMP_HYSTERESIS0 */
-#define ACMP_HYSTERESIS0_HYST_HYST4 (_ACMP_HYSTERESIS0_HYST_HYST4 << 0) /**< Shifted mode HYST4 for ACMP_HYSTERESIS0 */
-#define ACMP_HYSTERESIS0_HYST_HYST5 (_ACMP_HYSTERESIS0_HYST_HYST5 << 0) /**< Shifted mode HYST5 for ACMP_HYSTERESIS0 */
-#define ACMP_HYSTERESIS0_HYST_HYST6 (_ACMP_HYSTERESIS0_HYST_HYST6 << 0) /**< Shifted mode HYST6 for ACMP_HYSTERESIS0 */
-#define ACMP_HYSTERESIS0_HYST_HYST7 (_ACMP_HYSTERESIS0_HYST_HYST7 << 0) /**< Shifted mode HYST7 for ACMP_HYSTERESIS0 */
-#define ACMP_HYSTERESIS0_HYST_HYST8 (_ACMP_HYSTERESIS0_HYST_HYST8 << 0) /**< Shifted mode HYST8 for ACMP_HYSTERESIS0 */
-#define ACMP_HYSTERESIS0_HYST_HYST9 (_ACMP_HYSTERESIS0_HYST_HYST9 << 0) /**< Shifted mode HYST9 for ACMP_HYSTERESIS0 */
-#define ACMP_HYSTERESIS0_HYST_HYST10 (_ACMP_HYSTERESIS0_HYST_HYST10 << 0) /**< Shifted mode HYST10 for ACMP_HYSTERESIS0 */
-#define ACMP_HYSTERESIS0_HYST_HYST11 (_ACMP_HYSTERESIS0_HYST_HYST11 << 0) /**< Shifted mode HYST11 for ACMP_HYSTERESIS0 */
-#define ACMP_HYSTERESIS0_HYST_HYST12 (_ACMP_HYSTERESIS0_HYST_HYST12 << 0) /**< Shifted mode HYST12 for ACMP_HYSTERESIS0 */
-#define ACMP_HYSTERESIS0_HYST_HYST13 (_ACMP_HYSTERESIS0_HYST_HYST13 << 0) /**< Shifted mode HYST13 for ACMP_HYSTERESIS0 */
-#define ACMP_HYSTERESIS0_HYST_HYST14 (_ACMP_HYSTERESIS0_HYST_HYST14 << 0) /**< Shifted mode HYST14 for ACMP_HYSTERESIS0 */
-#define ACMP_HYSTERESIS0_HYST_HYST15 (_ACMP_HYSTERESIS0_HYST_HYST15 << 0) /**< Shifted mode HYST15 for ACMP_HYSTERESIS0 */
-#define _ACMP_HYSTERESIS0_DIVVA_SHIFT 16 /**< Shift value for ACMP_DIVVA */
-#define _ACMP_HYSTERESIS0_DIVVA_MASK 0x3F0000UL /**< Bit mask for ACMP_DIVVA */
-#define _ACMP_HYSTERESIS0_DIVVA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS0 */
-#define ACMP_HYSTERESIS0_DIVVA_DEFAULT (_ACMP_HYSTERESIS0_DIVVA_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS0 */
-#define _ACMP_HYSTERESIS0_DIVVB_SHIFT 24 /**< Shift value for ACMP_DIVVB */
-#define _ACMP_HYSTERESIS0_DIVVB_MASK 0x3F000000UL /**< Bit mask for ACMP_DIVVB */
-#define _ACMP_HYSTERESIS0_DIVVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS0 */
-#define ACMP_HYSTERESIS0_DIVVB_DEFAULT (_ACMP_HYSTERESIS0_DIVVB_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS0 */
-
-/* Bit fields for ACMP HYSTERESIS1 */
-#define _ACMP_HYSTERESIS1_RESETVALUE 0x00000000UL /**< Default value for ACMP_HYSTERESIS1 */
-#define _ACMP_HYSTERESIS1_MASK 0x3F3F000FUL /**< Mask for ACMP_HYSTERESIS1 */
-#define _ACMP_HYSTERESIS1_HYST_SHIFT 0 /**< Shift value for ACMP_HYST */
-#define _ACMP_HYSTERESIS1_HYST_MASK 0xFUL /**< Bit mask for ACMP_HYST */
-#define _ACMP_HYSTERESIS1_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS1 */
-#define _ACMP_HYSTERESIS1_HYST_HYST0 0x00000000UL /**< Mode HYST0 for ACMP_HYSTERESIS1 */
-#define _ACMP_HYSTERESIS1_HYST_HYST1 0x00000001UL /**< Mode HYST1 for ACMP_HYSTERESIS1 */
-#define _ACMP_HYSTERESIS1_HYST_HYST2 0x00000002UL /**< Mode HYST2 for ACMP_HYSTERESIS1 */
-#define _ACMP_HYSTERESIS1_HYST_HYST3 0x00000003UL /**< Mode HYST3 for ACMP_HYSTERESIS1 */
-#define _ACMP_HYSTERESIS1_HYST_HYST4 0x00000004UL /**< Mode HYST4 for ACMP_HYSTERESIS1 */
-#define _ACMP_HYSTERESIS1_HYST_HYST5 0x00000005UL /**< Mode HYST5 for ACMP_HYSTERESIS1 */
-#define _ACMP_HYSTERESIS1_HYST_HYST6 0x00000006UL /**< Mode HYST6 for ACMP_HYSTERESIS1 */
-#define _ACMP_HYSTERESIS1_HYST_HYST7 0x00000007UL /**< Mode HYST7 for ACMP_HYSTERESIS1 */
-#define _ACMP_HYSTERESIS1_HYST_HYST8 0x00000008UL /**< Mode HYST8 for ACMP_HYSTERESIS1 */
-#define _ACMP_HYSTERESIS1_HYST_HYST9 0x00000009UL /**< Mode HYST9 for ACMP_HYSTERESIS1 */
-#define _ACMP_HYSTERESIS1_HYST_HYST10 0x0000000AUL /**< Mode HYST10 for ACMP_HYSTERESIS1 */
-#define _ACMP_HYSTERESIS1_HYST_HYST11 0x0000000BUL /**< Mode HYST11 for ACMP_HYSTERESIS1 */
-#define _ACMP_HYSTERESIS1_HYST_HYST12 0x0000000CUL /**< Mode HYST12 for ACMP_HYSTERESIS1 */
-#define _ACMP_HYSTERESIS1_HYST_HYST13 0x0000000DUL /**< Mode HYST13 for ACMP_HYSTERESIS1 */
-#define _ACMP_HYSTERESIS1_HYST_HYST14 0x0000000EUL /**< Mode HYST14 for ACMP_HYSTERESIS1 */
-#define _ACMP_HYSTERESIS1_HYST_HYST15 0x0000000FUL /**< Mode HYST15 for ACMP_HYSTERESIS1 */
-#define ACMP_HYSTERESIS1_HYST_DEFAULT (_ACMP_HYSTERESIS1_HYST_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS1 */
-#define ACMP_HYSTERESIS1_HYST_HYST0 (_ACMP_HYSTERESIS1_HYST_HYST0 << 0) /**< Shifted mode HYST0 for ACMP_HYSTERESIS1 */
-#define ACMP_HYSTERESIS1_HYST_HYST1 (_ACMP_HYSTERESIS1_HYST_HYST1 << 0) /**< Shifted mode HYST1 for ACMP_HYSTERESIS1 */
-#define ACMP_HYSTERESIS1_HYST_HYST2 (_ACMP_HYSTERESIS1_HYST_HYST2 << 0) /**< Shifted mode HYST2 for ACMP_HYSTERESIS1 */
-#define ACMP_HYSTERESIS1_HYST_HYST3 (_ACMP_HYSTERESIS1_HYST_HYST3 << 0) /**< Shifted mode HYST3 for ACMP_HYSTERESIS1 */
-#define ACMP_HYSTERESIS1_HYST_HYST4 (_ACMP_HYSTERESIS1_HYST_HYST4 << 0) /**< Shifted mode HYST4 for ACMP_HYSTERESIS1 */
-#define ACMP_HYSTERESIS1_HYST_HYST5 (_ACMP_HYSTERESIS1_HYST_HYST5 << 0) /**< Shifted mode HYST5 for ACMP_HYSTERESIS1 */
-#define ACMP_HYSTERESIS1_HYST_HYST6 (_ACMP_HYSTERESIS1_HYST_HYST6 << 0) /**< Shifted mode HYST6 for ACMP_HYSTERESIS1 */
-#define ACMP_HYSTERESIS1_HYST_HYST7 (_ACMP_HYSTERESIS1_HYST_HYST7 << 0) /**< Shifted mode HYST7 for ACMP_HYSTERESIS1 */
-#define ACMP_HYSTERESIS1_HYST_HYST8 (_ACMP_HYSTERESIS1_HYST_HYST8 << 0) /**< Shifted mode HYST8 for ACMP_HYSTERESIS1 */
-#define ACMP_HYSTERESIS1_HYST_HYST9 (_ACMP_HYSTERESIS1_HYST_HYST9 << 0) /**< Shifted mode HYST9 for ACMP_HYSTERESIS1 */
-#define ACMP_HYSTERESIS1_HYST_HYST10 (_ACMP_HYSTERESIS1_HYST_HYST10 << 0) /**< Shifted mode HYST10 for ACMP_HYSTERESIS1 */
-#define ACMP_HYSTERESIS1_HYST_HYST11 (_ACMP_HYSTERESIS1_HYST_HYST11 << 0) /**< Shifted mode HYST11 for ACMP_HYSTERESIS1 */
-#define ACMP_HYSTERESIS1_HYST_HYST12 (_ACMP_HYSTERESIS1_HYST_HYST12 << 0) /**< Shifted mode HYST12 for ACMP_HYSTERESIS1 */
-#define ACMP_HYSTERESIS1_HYST_HYST13 (_ACMP_HYSTERESIS1_HYST_HYST13 << 0) /**< Shifted mode HYST13 for ACMP_HYSTERESIS1 */
-#define ACMP_HYSTERESIS1_HYST_HYST14 (_ACMP_HYSTERESIS1_HYST_HYST14 << 0) /**< Shifted mode HYST14 for ACMP_HYSTERESIS1 */
-#define ACMP_HYSTERESIS1_HYST_HYST15 (_ACMP_HYSTERESIS1_HYST_HYST15 << 0) /**< Shifted mode HYST15 for ACMP_HYSTERESIS1 */
-#define _ACMP_HYSTERESIS1_DIVVA_SHIFT 16 /**< Shift value for ACMP_DIVVA */
-#define _ACMP_HYSTERESIS1_DIVVA_MASK 0x3F0000UL /**< Bit mask for ACMP_DIVVA */
-#define _ACMP_HYSTERESIS1_DIVVA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS1 */
-#define ACMP_HYSTERESIS1_DIVVA_DEFAULT (_ACMP_HYSTERESIS1_DIVVA_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS1 */
-#define _ACMP_HYSTERESIS1_DIVVB_SHIFT 24 /**< Shift value for ACMP_DIVVB */
-#define _ACMP_HYSTERESIS1_DIVVB_MASK 0x3F000000UL /**< Bit mask for ACMP_DIVVB */
-#define _ACMP_HYSTERESIS1_DIVVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS1 */
-#define ACMP_HYSTERESIS1_DIVVB_DEFAULT (_ACMP_HYSTERESIS1_DIVVB_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS1 */
-
-/* Bit fields for ACMP ROUTEPEN */
-#define _ACMP_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_ROUTEPEN */
-#define _ACMP_ROUTEPEN_MASK 0x00000001UL /**< Mask for ACMP_ROUTEPEN */
-#define ACMP_ROUTEPEN_OUTPEN (0x1UL << 0) /**< ACMP Output Pin Enable */
-#define _ACMP_ROUTEPEN_OUTPEN_SHIFT 0 /**< Shift value for ACMP_OUTPEN */
-#define _ACMP_ROUTEPEN_OUTPEN_MASK 0x1UL /**< Bit mask for ACMP_OUTPEN */
-#define _ACMP_ROUTEPEN_OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTEPEN */
-#define ACMP_ROUTEPEN_OUTPEN_DEFAULT (_ACMP_ROUTEPEN_OUTPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_ROUTEPEN */
-
-/* Bit fields for ACMP ROUTELOC0 */
-#define _ACMP_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_MASK 0x0000001FUL /**< Mask for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_SHIFT 0 /**< Shift value for ACMP_OUTLOC */
-#define _ACMP_ROUTELOC0_OUTLOC_MASK 0x1FUL /**< Bit mask for ACMP_OUTLOC */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC0 0x00000000UL /**< Mode LOC0 for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC1 0x00000001UL /**< Mode LOC1 for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC2 0x00000002UL /**< Mode LOC2 for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC3 0x00000003UL /**< Mode LOC3 for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC4 0x00000004UL /**< Mode LOC4 for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC5 0x00000005UL /**< Mode LOC5 for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC6 0x00000006UL /**< Mode LOC6 for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC7 0x00000007UL /**< Mode LOC7 for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC8 0x00000008UL /**< Mode LOC8 for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC9 0x00000009UL /**< Mode LOC9 for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC10 0x0000000AUL /**< Mode LOC10 for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC11 0x0000000BUL /**< Mode LOC11 for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC12 0x0000000CUL /**< Mode LOC12 for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC13 0x0000000DUL /**< Mode LOC13 for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC14 0x0000000EUL /**< Mode LOC14 for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC15 0x0000000FUL /**< Mode LOC15 for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC16 0x00000010UL /**< Mode LOC16 for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC17 0x00000011UL /**< Mode LOC17 for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC18 0x00000012UL /**< Mode LOC18 for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC19 0x00000013UL /**< Mode LOC19 for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC20 0x00000014UL /**< Mode LOC20 for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC21 0x00000015UL /**< Mode LOC21 for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC22 0x00000016UL /**< Mode LOC22 for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC23 0x00000017UL /**< Mode LOC23 for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC24 0x00000018UL /**< Mode LOC24 for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC25 0x00000019UL /**< Mode LOC25 for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC26 0x0000001AUL /**< Mode LOC26 for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC27 0x0000001BUL /**< Mode LOC27 for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC28 0x0000001CUL /**< Mode LOC28 for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC29 0x0000001DUL /**< Mode LOC29 for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC30 0x0000001EUL /**< Mode LOC30 for ACMP_ROUTELOC0 */
-#define _ACMP_ROUTELOC0_OUTLOC_LOC31 0x0000001FUL /**< Mode LOC31 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC0 (_ACMP_ROUTELOC0_OUTLOC_LOC0 << 0) /**< Shifted mode LOC0 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_DEFAULT (_ACMP_ROUTELOC0_OUTLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC1 (_ACMP_ROUTELOC0_OUTLOC_LOC1 << 0) /**< Shifted mode LOC1 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC2 (_ACMP_ROUTELOC0_OUTLOC_LOC2 << 0) /**< Shifted mode LOC2 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC3 (_ACMP_ROUTELOC0_OUTLOC_LOC3 << 0) /**< Shifted mode LOC3 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC4 (_ACMP_ROUTELOC0_OUTLOC_LOC4 << 0) /**< Shifted mode LOC4 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC5 (_ACMP_ROUTELOC0_OUTLOC_LOC5 << 0) /**< Shifted mode LOC5 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC6 (_ACMP_ROUTELOC0_OUTLOC_LOC6 << 0) /**< Shifted mode LOC6 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC7 (_ACMP_ROUTELOC0_OUTLOC_LOC7 << 0) /**< Shifted mode LOC7 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC8 (_ACMP_ROUTELOC0_OUTLOC_LOC8 << 0) /**< Shifted mode LOC8 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC9 (_ACMP_ROUTELOC0_OUTLOC_LOC9 << 0) /**< Shifted mode LOC9 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC10 (_ACMP_ROUTELOC0_OUTLOC_LOC10 << 0) /**< Shifted mode LOC10 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC11 (_ACMP_ROUTELOC0_OUTLOC_LOC11 << 0) /**< Shifted mode LOC11 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC12 (_ACMP_ROUTELOC0_OUTLOC_LOC12 << 0) /**< Shifted mode LOC12 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC13 (_ACMP_ROUTELOC0_OUTLOC_LOC13 << 0) /**< Shifted mode LOC13 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC14 (_ACMP_ROUTELOC0_OUTLOC_LOC14 << 0) /**< Shifted mode LOC14 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC15 (_ACMP_ROUTELOC0_OUTLOC_LOC15 << 0) /**< Shifted mode LOC15 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC16 (_ACMP_ROUTELOC0_OUTLOC_LOC16 << 0) /**< Shifted mode LOC16 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC17 (_ACMP_ROUTELOC0_OUTLOC_LOC17 << 0) /**< Shifted mode LOC17 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC18 (_ACMP_ROUTELOC0_OUTLOC_LOC18 << 0) /**< Shifted mode LOC18 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC19 (_ACMP_ROUTELOC0_OUTLOC_LOC19 << 0) /**< Shifted mode LOC19 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC20 (_ACMP_ROUTELOC0_OUTLOC_LOC20 << 0) /**< Shifted mode LOC20 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC21 (_ACMP_ROUTELOC0_OUTLOC_LOC21 << 0) /**< Shifted mode LOC21 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC22 (_ACMP_ROUTELOC0_OUTLOC_LOC22 << 0) /**< Shifted mode LOC22 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC23 (_ACMP_ROUTELOC0_OUTLOC_LOC23 << 0) /**< Shifted mode LOC23 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC24 (_ACMP_ROUTELOC0_OUTLOC_LOC24 << 0) /**< Shifted mode LOC24 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC25 (_ACMP_ROUTELOC0_OUTLOC_LOC25 << 0) /**< Shifted mode LOC25 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC26 (_ACMP_ROUTELOC0_OUTLOC_LOC26 << 0) /**< Shifted mode LOC26 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC27 (_ACMP_ROUTELOC0_OUTLOC_LOC27 << 0) /**< Shifted mode LOC27 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC28 (_ACMP_ROUTELOC0_OUTLOC_LOC28 << 0) /**< Shifted mode LOC28 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC29 (_ACMP_ROUTELOC0_OUTLOC_LOC29 << 0) /**< Shifted mode LOC29 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC30 (_ACMP_ROUTELOC0_OUTLOC_LOC30 << 0) /**< Shifted mode LOC30 for ACMP_ROUTELOC0 */
-#define ACMP_ROUTELOC0_OUTLOC_LOC31 (_ACMP_ROUTELOC0_OUTLOC_LOC31 << 0) /**< Shifted mode LOC31 for ACMP_ROUTELOC0 */
-
-/* Bit fields for ACMP EXTIFCTRL */
-#define _ACMP_EXTIFCTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_EXTIFCTRL */
-#define _ACMP_EXTIFCTRL_MASK 0x000000F1UL /**< Mask for ACMP_EXTIFCTRL */
-#define ACMP_EXTIFCTRL_EN (0x1UL << 0) /**< Enable External Interface */
-#define _ACMP_EXTIFCTRL_EN_SHIFT 0 /**< Shift value for ACMP_EN */
-#define _ACMP_EXTIFCTRL_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */
-#define _ACMP_EXTIFCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EXTIFCTRL */
-#define ACMP_EXTIFCTRL_EN_DEFAULT (_ACMP_EXTIFCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_EXTIFCTRL */
-#define _ACMP_EXTIFCTRL_APORTSEL_SHIFT 4 /**< Shift value for ACMP_APORTSEL */
-#define _ACMP_EXTIFCTRL_APORTSEL_MASK 0xF0UL /**< Bit mask for ACMP_APORTSEL */
-#define _ACMP_EXTIFCTRL_APORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EXTIFCTRL */
-#define _ACMP_EXTIFCTRL_APORTSEL_APORT0X 0x00000000UL /**< Mode APORT0X for ACMP_EXTIFCTRL */
-#define _ACMP_EXTIFCTRL_APORTSEL_APORT0Y 0x00000001UL /**< Mode APORT0Y for ACMP_EXTIFCTRL */
-#define _ACMP_EXTIFCTRL_APORTSEL_APORT1X 0x00000002UL /**< Mode APORT1X for ACMP_EXTIFCTRL */
-#define _ACMP_EXTIFCTRL_APORTSEL_APORT1Y 0x00000003UL /**< Mode APORT1Y for ACMP_EXTIFCTRL */
-#define _ACMP_EXTIFCTRL_APORTSEL_APORT1XY 0x00000004UL /**< Mode APORT1XY for ACMP_EXTIFCTRL */
-#define _ACMP_EXTIFCTRL_APORTSEL_APORT2X 0x00000005UL /**< Mode APORT2X for ACMP_EXTIFCTRL */
-#define _ACMP_EXTIFCTRL_APORTSEL_APORT2Y 0x00000006UL /**< Mode APORT2Y for ACMP_EXTIFCTRL */
-#define _ACMP_EXTIFCTRL_APORTSEL_APORT2YX 0x00000007UL /**< Mode APORT2YX for ACMP_EXTIFCTRL */
-#define _ACMP_EXTIFCTRL_APORTSEL_APORT3X 0x00000008UL /**< Mode APORT3X for ACMP_EXTIFCTRL */
-#define _ACMP_EXTIFCTRL_APORTSEL_APORT3Y 0x00000009UL /**< Mode APORT3Y for ACMP_EXTIFCTRL */
-#define _ACMP_EXTIFCTRL_APORTSEL_APORT3XY 0x0000000AUL /**< Mode APORT3XY for ACMP_EXTIFCTRL */
-#define _ACMP_EXTIFCTRL_APORTSEL_APORT4X 0x0000000BUL /**< Mode APORT4X for ACMP_EXTIFCTRL */
-#define _ACMP_EXTIFCTRL_APORTSEL_APORT4Y 0x0000000CUL /**< Mode APORT4Y for ACMP_EXTIFCTRL */
-#define _ACMP_EXTIFCTRL_APORTSEL_APORT4YX 0x0000000DUL /**< Mode APORT4YX for ACMP_EXTIFCTRL */
-#define ACMP_EXTIFCTRL_APORTSEL_DEFAULT (_ACMP_EXTIFCTRL_APORTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_EXTIFCTRL */
-#define ACMP_EXTIFCTRL_APORTSEL_APORT0X (_ACMP_EXTIFCTRL_APORTSEL_APORT0X << 4) /**< Shifted mode APORT0X for ACMP_EXTIFCTRL */
-#define ACMP_EXTIFCTRL_APORTSEL_APORT0Y (_ACMP_EXTIFCTRL_APORTSEL_APORT0Y << 4) /**< Shifted mode APORT0Y for ACMP_EXTIFCTRL */
-#define ACMP_EXTIFCTRL_APORTSEL_APORT1X (_ACMP_EXTIFCTRL_APORTSEL_APORT1X << 4) /**< Shifted mode APORT1X for ACMP_EXTIFCTRL */
-#define ACMP_EXTIFCTRL_APORTSEL_APORT1Y (_ACMP_EXTIFCTRL_APORTSEL_APORT1Y << 4) /**< Shifted mode APORT1Y for ACMP_EXTIFCTRL */
-#define ACMP_EXTIFCTRL_APORTSEL_APORT1XY (_ACMP_EXTIFCTRL_APORTSEL_APORT1XY << 4) /**< Shifted mode APORT1XY for ACMP_EXTIFCTRL */
-#define ACMP_EXTIFCTRL_APORTSEL_APORT2X (_ACMP_EXTIFCTRL_APORTSEL_APORT2X << 4) /**< Shifted mode APORT2X for ACMP_EXTIFCTRL */
-#define ACMP_EXTIFCTRL_APORTSEL_APORT2Y (_ACMP_EXTIFCTRL_APORTSEL_APORT2Y << 4) /**< Shifted mode APORT2Y for ACMP_EXTIFCTRL */
-#define ACMP_EXTIFCTRL_APORTSEL_APORT2YX (_ACMP_EXTIFCTRL_APORTSEL_APORT2YX << 4) /**< Shifted mode APORT2YX for ACMP_EXTIFCTRL */
-#define ACMP_EXTIFCTRL_APORTSEL_APORT3X (_ACMP_EXTIFCTRL_APORTSEL_APORT3X << 4) /**< Shifted mode APORT3X for ACMP_EXTIFCTRL */
-#define ACMP_EXTIFCTRL_APORTSEL_APORT3Y (_ACMP_EXTIFCTRL_APORTSEL_APORT3Y << 4) /**< Shifted mode APORT3Y for ACMP_EXTIFCTRL */
-#define ACMP_EXTIFCTRL_APORTSEL_APORT3XY (_ACMP_EXTIFCTRL_APORTSEL_APORT3XY << 4) /**< Shifted mode APORT3XY for ACMP_EXTIFCTRL */
-#define ACMP_EXTIFCTRL_APORTSEL_APORT4X (_ACMP_EXTIFCTRL_APORTSEL_APORT4X << 4) /**< Shifted mode APORT4X for ACMP_EXTIFCTRL */
-#define ACMP_EXTIFCTRL_APORTSEL_APORT4Y (_ACMP_EXTIFCTRL_APORTSEL_APORT4Y << 4) /**< Shifted mode APORT4Y for ACMP_EXTIFCTRL */
-#define ACMP_EXTIFCTRL_APORTSEL_APORT4YX (_ACMP_EXTIFCTRL_APORTSEL_APORT4YX << 4) /**< Shifted mode APORT4YX for ACMP_EXTIFCTRL */
-
-/** @} */
-/** @} End of group EFR32FG13P_ACMP */
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_adc.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_adc.h
deleted file mode 100644
index 71dea68c..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_adc.h
+++ /dev/null
@@ -1,2380 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_adc.h
- * @brief EFR32FG13P_ADC register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P_ADC ADC
- * @{
- * @brief EFR32FG13P_ADC Register Declaration
- *****************************************************************************/
-/** ADC Register Declaration */
-typedef struct {
- __IOM uint32_t CTRL; /**< Control Register */
- uint32_t RESERVED0[1]; /**< Reserved for future use **/
- __IOM uint32_t CMD; /**< Command Register */
- __IM uint32_t STATUS; /**< Status Register */
- __IOM uint32_t SINGLECTRL; /**< Single Channel Control Register */
- __IOM uint32_t SINGLECTRLX; /**< Single Channel Control Register Continued */
- __IOM uint32_t SCANCTRL; /**< Scan Control Register */
- __IOM uint32_t SCANCTRLX; /**< Scan Control Register Continued */
- __IOM uint32_t SCANMASK; /**< Scan Sequence Input Mask Register */
- __IOM uint32_t SCANINPUTSEL; /**< Input Selection Register for Scan Mode */
- __IOM uint32_t SCANNEGSEL; /**< Negative Input Select Register for Scan */
- __IOM uint32_t CMPTHR; /**< Compare Threshold Register */
- __IOM uint32_t BIASPROG; /**< Bias Programming Register for Various Analog Blocks Used in ADC Operation */
- __IOM uint32_t CAL; /**< Calibration Register */
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- __IM uint32_t SINGLEDATA; /**< Single Conversion Result Data */
- __IM uint32_t SCANDATA; /**< Scan Conversion Result Data */
- __IM uint32_t SINGLEDATAP; /**< Single Conversion Result Data Peek Register */
- __IM uint32_t SCANDATAP; /**< Scan Sequence Result Data Peek Register */
- uint32_t RESERVED1[4]; /**< Reserved for future use **/
- __IM uint32_t SCANDATAX; /**< Scan Sequence Result Data + Data Source Register */
- __IM uint32_t SCANDATAXP; /**< Scan Sequence Result Data + Data Source Peek Register */
-
- uint32_t RESERVED2[3]; /**< Reserved for future use **/
- __IM uint32_t APORTREQ; /**< APORT Request Status Register */
- __IM uint32_t APORTCONFLICT; /**< APORT Conflict Status Register */
- __IM uint32_t SINGLEFIFOCOUNT; /**< Single FIFO Count Register */
- __IM uint32_t SCANFIFOCOUNT; /**< Scan FIFO Count Register */
- __IOM uint32_t SINGLEFIFOCLEAR; /**< Single FIFO Clear Register */
- __IOM uint32_t SCANFIFOCLEAR; /**< Scan FIFO Clear Register */
- __IOM uint32_t APORTMASTERDIS; /**< APORT Bus Master Disable Register */
-} ADC_TypeDef; /** @} */
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_ADC
- * @{
- * @defgroup EFR32FG13P_ADC_BitFields ADC Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for ADC CTRL */
-#define _ADC_CTRL_RESETVALUE 0x001F0000UL /**< Default value for ADC_CTRL */
-#define _ADC_CTRL_MASK 0xFF7F7FDFUL /**< Mask for ADC_CTRL */
-#define _ADC_CTRL_WARMUPMODE_SHIFT 0 /**< Shift value for ADC_WARMUPMODE */
-#define _ADC_CTRL_WARMUPMODE_MASK 0x3UL /**< Bit mask for ADC_WARMUPMODE */
-#define _ADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
-#define _ADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for ADC_CTRL */
-#define _ADC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for ADC_CTRL */
-#define _ADC_CTRL_WARMUPMODE_KEEPINSLOWACC 0x00000002UL /**< Mode KEEPINSLOWACC for ADC_CTRL */
-#define _ADC_CTRL_WARMUPMODE_KEEPADCWARM 0x00000003UL /**< Mode KEEPADCWARM for ADC_CTRL */
-#define ADC_CTRL_WARMUPMODE_DEFAULT (_ADC_CTRL_WARMUPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CTRL */
-#define ADC_CTRL_WARMUPMODE_NORMAL (_ADC_CTRL_WARMUPMODE_NORMAL << 0) /**< Shifted mode NORMAL for ADC_CTRL */
-#define ADC_CTRL_WARMUPMODE_KEEPINSTANDBY (_ADC_CTRL_WARMUPMODE_KEEPINSTANDBY << 0) /**< Shifted mode KEEPINSTANDBY for ADC_CTRL */
-#define ADC_CTRL_WARMUPMODE_KEEPINSLOWACC (_ADC_CTRL_WARMUPMODE_KEEPINSLOWACC << 0) /**< Shifted mode KEEPINSLOWACC for ADC_CTRL */
-#define ADC_CTRL_WARMUPMODE_KEEPADCWARM (_ADC_CTRL_WARMUPMODE_KEEPADCWARM << 0) /**< Shifted mode KEEPADCWARM for ADC_CTRL */
-#define ADC_CTRL_SINGLEDMAWU (0x1UL << 2) /**< SINGLEFIFO DMA Wakeup */
-#define _ADC_CTRL_SINGLEDMAWU_SHIFT 2 /**< Shift value for ADC_SINGLEDMAWU */
-#define _ADC_CTRL_SINGLEDMAWU_MASK 0x4UL /**< Bit mask for ADC_SINGLEDMAWU */
-#define _ADC_CTRL_SINGLEDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
-#define ADC_CTRL_SINGLEDMAWU_DEFAULT (_ADC_CTRL_SINGLEDMAWU_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_CTRL */
-#define ADC_CTRL_SCANDMAWU (0x1UL << 3) /**< SCANFIFO DMA Wakeup */
-#define _ADC_CTRL_SCANDMAWU_SHIFT 3 /**< Shift value for ADC_SCANDMAWU */
-#define _ADC_CTRL_SCANDMAWU_MASK 0x8UL /**< Bit mask for ADC_SCANDMAWU */
-#define _ADC_CTRL_SCANDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
-#define ADC_CTRL_SCANDMAWU_DEFAULT (_ADC_CTRL_SCANDMAWU_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CTRL */
-#define ADC_CTRL_TAILGATE (0x1UL << 4) /**< Conversion Tailgating */
-#define _ADC_CTRL_TAILGATE_SHIFT 4 /**< Shift value for ADC_TAILGATE */
-#define _ADC_CTRL_TAILGATE_MASK 0x10UL /**< Bit mask for ADC_TAILGATE */
-#define _ADC_CTRL_TAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
-#define ADC_CTRL_TAILGATE_DEFAULT (_ADC_CTRL_TAILGATE_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_CTRL */
-#define ADC_CTRL_ASYNCCLKEN (0x1UL << 6) /**< Selects ASYNC CLK Enable Mode When ADCCLKMODE=1 */
-#define _ADC_CTRL_ASYNCCLKEN_SHIFT 6 /**< Shift value for ADC_ASYNCCLKEN */
-#define _ADC_CTRL_ASYNCCLKEN_MASK 0x40UL /**< Bit mask for ADC_ASYNCCLKEN */
-#define _ADC_CTRL_ASYNCCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
-#define _ADC_CTRL_ASYNCCLKEN_ASNEEDED 0x00000000UL /**< Mode ASNEEDED for ADC_CTRL */
-#define _ADC_CTRL_ASYNCCLKEN_ALWAYSON 0x00000001UL /**< Mode ALWAYSON for ADC_CTRL */
-#define ADC_CTRL_ASYNCCLKEN_DEFAULT (_ADC_CTRL_ASYNCCLKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_CTRL */
-#define ADC_CTRL_ASYNCCLKEN_ASNEEDED (_ADC_CTRL_ASYNCCLKEN_ASNEEDED << 6) /**< Shifted mode ASNEEDED for ADC_CTRL */
-#define ADC_CTRL_ASYNCCLKEN_ALWAYSON (_ADC_CTRL_ASYNCCLKEN_ALWAYSON << 6) /**< Shifted mode ALWAYSON for ADC_CTRL */
-#define ADC_CTRL_ADCCLKMODE (0x1UL << 7) /**< ADC Clock Mode */
-#define _ADC_CTRL_ADCCLKMODE_SHIFT 7 /**< Shift value for ADC_ADCCLKMODE */
-#define _ADC_CTRL_ADCCLKMODE_MASK 0x80UL /**< Bit mask for ADC_ADCCLKMODE */
-#define _ADC_CTRL_ADCCLKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
-#define _ADC_CTRL_ADCCLKMODE_SYNC 0x00000000UL /**< Mode SYNC for ADC_CTRL */
-#define _ADC_CTRL_ADCCLKMODE_ASYNC 0x00000001UL /**< Mode ASYNC for ADC_CTRL */
-#define ADC_CTRL_ADCCLKMODE_DEFAULT (_ADC_CTRL_ADCCLKMODE_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_CTRL */
-#define ADC_CTRL_ADCCLKMODE_SYNC (_ADC_CTRL_ADCCLKMODE_SYNC << 7) /**< Shifted mode SYNC for ADC_CTRL */
-#define ADC_CTRL_ADCCLKMODE_ASYNC (_ADC_CTRL_ADCCLKMODE_ASYNC << 7) /**< Shifted mode ASYNC for ADC_CTRL */
-#define _ADC_CTRL_PRESC_SHIFT 8 /**< Shift value for ADC_PRESC */
-#define _ADC_CTRL_PRESC_MASK 0x7F00UL /**< Bit mask for ADC_PRESC */
-#define _ADC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
-#define _ADC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for ADC_CTRL */
-#define ADC_CTRL_PRESC_DEFAULT (_ADC_CTRL_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CTRL */
-#define ADC_CTRL_PRESC_NODIVISION (_ADC_CTRL_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for ADC_CTRL */
-#define _ADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for ADC_TIMEBASE */
-#define _ADC_CTRL_TIMEBASE_MASK 0x7F0000UL /**< Bit mask for ADC_TIMEBASE */
-#define _ADC_CTRL_TIMEBASE_DEFAULT 0x0000001FUL /**< Mode DEFAULT for ADC_CTRL */
-#define ADC_CTRL_TIMEBASE_DEFAULT (_ADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CTRL */
-#define _ADC_CTRL_OVSRSEL_SHIFT 24 /**< Shift value for ADC_OVSRSEL */
-#define _ADC_CTRL_OVSRSEL_MASK 0xF000000UL /**< Bit mask for ADC_OVSRSEL */
-#define _ADC_CTRL_OVSRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
-#define _ADC_CTRL_OVSRSEL_X2 0x00000000UL /**< Mode X2 for ADC_CTRL */
-#define _ADC_CTRL_OVSRSEL_X4 0x00000001UL /**< Mode X4 for ADC_CTRL */
-#define _ADC_CTRL_OVSRSEL_X8 0x00000002UL /**< Mode X8 for ADC_CTRL */
-#define _ADC_CTRL_OVSRSEL_X16 0x00000003UL /**< Mode X16 for ADC_CTRL */
-#define _ADC_CTRL_OVSRSEL_X32 0x00000004UL /**< Mode X32 for ADC_CTRL */
-#define _ADC_CTRL_OVSRSEL_X64 0x00000005UL /**< Mode X64 for ADC_CTRL */
-#define _ADC_CTRL_OVSRSEL_X128 0x00000006UL /**< Mode X128 for ADC_CTRL */
-#define _ADC_CTRL_OVSRSEL_X256 0x00000007UL /**< Mode X256 for ADC_CTRL */
-#define _ADC_CTRL_OVSRSEL_X512 0x00000008UL /**< Mode X512 for ADC_CTRL */
-#define _ADC_CTRL_OVSRSEL_X1024 0x00000009UL /**< Mode X1024 for ADC_CTRL */
-#define _ADC_CTRL_OVSRSEL_X2048 0x0000000AUL /**< Mode X2048 for ADC_CTRL */
-#define _ADC_CTRL_OVSRSEL_X4096 0x0000000BUL /**< Mode X4096 for ADC_CTRL */
-#define ADC_CTRL_OVSRSEL_DEFAULT (_ADC_CTRL_OVSRSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CTRL */
-#define ADC_CTRL_OVSRSEL_X2 (_ADC_CTRL_OVSRSEL_X2 << 24) /**< Shifted mode X2 for ADC_CTRL */
-#define ADC_CTRL_OVSRSEL_X4 (_ADC_CTRL_OVSRSEL_X4 << 24) /**< Shifted mode X4 for ADC_CTRL */
-#define ADC_CTRL_OVSRSEL_X8 (_ADC_CTRL_OVSRSEL_X8 << 24) /**< Shifted mode X8 for ADC_CTRL */
-#define ADC_CTRL_OVSRSEL_X16 (_ADC_CTRL_OVSRSEL_X16 << 24) /**< Shifted mode X16 for ADC_CTRL */
-#define ADC_CTRL_OVSRSEL_X32 (_ADC_CTRL_OVSRSEL_X32 << 24) /**< Shifted mode X32 for ADC_CTRL */
-#define ADC_CTRL_OVSRSEL_X64 (_ADC_CTRL_OVSRSEL_X64 << 24) /**< Shifted mode X64 for ADC_CTRL */
-#define ADC_CTRL_OVSRSEL_X128 (_ADC_CTRL_OVSRSEL_X128 << 24) /**< Shifted mode X128 for ADC_CTRL */
-#define ADC_CTRL_OVSRSEL_X256 (_ADC_CTRL_OVSRSEL_X256 << 24) /**< Shifted mode X256 for ADC_CTRL */
-#define ADC_CTRL_OVSRSEL_X512 (_ADC_CTRL_OVSRSEL_X512 << 24) /**< Shifted mode X512 for ADC_CTRL */
-#define ADC_CTRL_OVSRSEL_X1024 (_ADC_CTRL_OVSRSEL_X1024 << 24) /**< Shifted mode X1024 for ADC_CTRL */
-#define ADC_CTRL_OVSRSEL_X2048 (_ADC_CTRL_OVSRSEL_X2048 << 24) /**< Shifted mode X2048 for ADC_CTRL */
-#define ADC_CTRL_OVSRSEL_X4096 (_ADC_CTRL_OVSRSEL_X4096 << 24) /**< Shifted mode X4096 for ADC_CTRL */
-#define ADC_CTRL_DBGHALT (0x1UL << 28) /**< Debug Mode Halt Enable */
-#define _ADC_CTRL_DBGHALT_SHIFT 28 /**< Shift value for ADC_DBGHALT */
-#define _ADC_CTRL_DBGHALT_MASK 0x10000000UL /**< Bit mask for ADC_DBGHALT */
-#define _ADC_CTRL_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
-#define ADC_CTRL_DBGHALT_DEFAULT (_ADC_CTRL_DBGHALT_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_CTRL */
-#define ADC_CTRL_CHCONMODE (0x1UL << 29) /**< Channel Connect */
-#define _ADC_CTRL_CHCONMODE_SHIFT 29 /**< Shift value for ADC_CHCONMODE */
-#define _ADC_CTRL_CHCONMODE_MASK 0x20000000UL /**< Bit mask for ADC_CHCONMODE */
-#define _ADC_CTRL_CHCONMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
-#define _ADC_CTRL_CHCONMODE_MAXSETTLE 0x00000000UL /**< Mode MAXSETTLE for ADC_CTRL */
-#define _ADC_CTRL_CHCONMODE_MAXRESP 0x00000001UL /**< Mode MAXRESP for ADC_CTRL */
-#define ADC_CTRL_CHCONMODE_DEFAULT (_ADC_CTRL_CHCONMODE_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_CTRL */
-#define ADC_CTRL_CHCONMODE_MAXSETTLE (_ADC_CTRL_CHCONMODE_MAXSETTLE << 29) /**< Shifted mode MAXSETTLE for ADC_CTRL */
-#define ADC_CTRL_CHCONMODE_MAXRESP (_ADC_CTRL_CHCONMODE_MAXRESP << 29) /**< Shifted mode MAXRESP for ADC_CTRL */
-#define _ADC_CTRL_CHCONREFWARMIDLE_SHIFT 30 /**< Shift value for ADC_CHCONREFWARMIDLE */
-#define _ADC_CTRL_CHCONREFWARMIDLE_MASK 0xC0000000UL /**< Bit mask for ADC_CHCONREFWARMIDLE */
-#define _ADC_CTRL_CHCONREFWARMIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
-#define _ADC_CTRL_CHCONREFWARMIDLE_PREFSCAN 0x00000000UL /**< Mode PREFSCAN for ADC_CTRL */
-#define _ADC_CTRL_CHCONREFWARMIDLE_PREFSINGLE 0x00000001UL /**< Mode PREFSINGLE for ADC_CTRL */
-#define _ADC_CTRL_CHCONREFWARMIDLE_KEEPPREV 0x00000002UL /**< Mode KEEPPREV for ADC_CTRL */
-#define ADC_CTRL_CHCONREFWARMIDLE_DEFAULT (_ADC_CTRL_CHCONREFWARMIDLE_DEFAULT << 30) /**< Shifted mode DEFAULT for ADC_CTRL */
-#define ADC_CTRL_CHCONREFWARMIDLE_PREFSCAN (_ADC_CTRL_CHCONREFWARMIDLE_PREFSCAN << 30) /**< Shifted mode PREFSCAN for ADC_CTRL */
-#define ADC_CTRL_CHCONREFWARMIDLE_PREFSINGLE (_ADC_CTRL_CHCONREFWARMIDLE_PREFSINGLE << 30) /**< Shifted mode PREFSINGLE for ADC_CTRL */
-#define ADC_CTRL_CHCONREFWARMIDLE_KEEPPREV (_ADC_CTRL_CHCONREFWARMIDLE_KEEPPREV << 30) /**< Shifted mode KEEPPREV for ADC_CTRL */
-
-/* Bit fields for ADC CMD */
-#define _ADC_CMD_RESETVALUE 0x00000000UL /**< Default value for ADC_CMD */
-#define _ADC_CMD_MASK 0x0000000FUL /**< Mask for ADC_CMD */
-#define ADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Channel Conversion Start */
-#define _ADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for ADC_SINGLESTART */
-#define _ADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for ADC_SINGLESTART */
-#define _ADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
-#define ADC_CMD_SINGLESTART_DEFAULT (_ADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CMD */
-#define ADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Channel Conversion Stop */
-#define _ADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for ADC_SINGLESTOP */
-#define _ADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for ADC_SINGLESTOP */
-#define _ADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
-#define ADC_CMD_SINGLESTOP_DEFAULT (_ADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_CMD */
-#define ADC_CMD_SCANSTART (0x1UL << 2) /**< Scan Sequence Start */
-#define _ADC_CMD_SCANSTART_SHIFT 2 /**< Shift value for ADC_SCANSTART */
-#define _ADC_CMD_SCANSTART_MASK 0x4UL /**< Bit mask for ADC_SCANSTART */
-#define _ADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
-#define ADC_CMD_SCANSTART_DEFAULT (_ADC_CMD_SCANSTART_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_CMD */
-#define ADC_CMD_SCANSTOP (0x1UL << 3) /**< Scan Sequence Stop */
-#define _ADC_CMD_SCANSTOP_SHIFT 3 /**< Shift value for ADC_SCANSTOP */
-#define _ADC_CMD_SCANSTOP_MASK 0x8UL /**< Bit mask for ADC_SCANSTOP */
-#define _ADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
-#define ADC_CMD_SCANSTOP_DEFAULT (_ADC_CMD_SCANSTOP_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CMD */
-
-/* Bit fields for ADC STATUS */
-#define _ADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for ADC_STATUS */
-#define _ADC_STATUS_MASK 0x00031F07UL /**< Mask for ADC_STATUS */
-#define ADC_STATUS_SINGLEACT (0x1UL << 0) /**< Single Channel Conversion Active */
-#define _ADC_STATUS_SINGLEACT_SHIFT 0 /**< Shift value for ADC_SINGLEACT */
-#define _ADC_STATUS_SINGLEACT_MASK 0x1UL /**< Bit mask for ADC_SINGLEACT */
-#define _ADC_STATUS_SINGLEACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
-#define ADC_STATUS_SINGLEACT_DEFAULT (_ADC_STATUS_SINGLEACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_STATUS */
-#define ADC_STATUS_SCANACT (0x1UL << 1) /**< Scan Conversion Active */
-#define _ADC_STATUS_SCANACT_SHIFT 1 /**< Shift value for ADC_SCANACT */
-#define _ADC_STATUS_SCANACT_MASK 0x2UL /**< Bit mask for ADC_SCANACT */
-#define _ADC_STATUS_SCANACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
-#define ADC_STATUS_SCANACT_DEFAULT (_ADC_STATUS_SCANACT_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_STATUS */
-#define ADC_STATUS_SCANPENDING (0x1UL << 2) /**< Scan Conversion Pending */
-#define _ADC_STATUS_SCANPENDING_SHIFT 2 /**< Shift value for ADC_SCANPENDING */
-#define _ADC_STATUS_SCANPENDING_MASK 0x4UL /**< Bit mask for ADC_SCANPENDING */
-#define _ADC_STATUS_SCANPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
-#define ADC_STATUS_SCANPENDING_DEFAULT (_ADC_STATUS_SCANPENDING_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_STATUS */
-#define ADC_STATUS_SINGLEREFWARM (0x1UL << 8) /**< Single Channel Reference Warmed Up */
-#define _ADC_STATUS_SINGLEREFWARM_SHIFT 8 /**< Shift value for ADC_SINGLEREFWARM */
-#define _ADC_STATUS_SINGLEREFWARM_MASK 0x100UL /**< Bit mask for ADC_SINGLEREFWARM */
-#define _ADC_STATUS_SINGLEREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
-#define ADC_STATUS_SINGLEREFWARM_DEFAULT (_ADC_STATUS_SINGLEREFWARM_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_STATUS */
-#define ADC_STATUS_SCANREFWARM (0x1UL << 9) /**< Scan Reference Warmed Up */
-#define _ADC_STATUS_SCANREFWARM_SHIFT 9 /**< Shift value for ADC_SCANREFWARM */
-#define _ADC_STATUS_SCANREFWARM_MASK 0x200UL /**< Bit mask for ADC_SCANREFWARM */
-#define _ADC_STATUS_SCANREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
-#define ADC_STATUS_SCANREFWARM_DEFAULT (_ADC_STATUS_SCANREFWARM_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_STATUS */
-#define _ADC_STATUS_PROGERR_SHIFT 10 /**< Shift value for ADC_PROGERR */
-#define _ADC_STATUS_PROGERR_MASK 0xC00UL /**< Bit mask for ADC_PROGERR */
-#define _ADC_STATUS_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
-#define _ADC_STATUS_PROGERR_BUSCONF 0x00000001UL /**< Mode BUSCONF for ADC_STATUS */
-#define _ADC_STATUS_PROGERR_NEGSELCONF 0x00000002UL /**< Mode NEGSELCONF for ADC_STATUS */
-#define ADC_STATUS_PROGERR_DEFAULT (_ADC_STATUS_PROGERR_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_STATUS */
-#define ADC_STATUS_PROGERR_BUSCONF (_ADC_STATUS_PROGERR_BUSCONF << 10) /**< Shifted mode BUSCONF for ADC_STATUS */
-#define ADC_STATUS_PROGERR_NEGSELCONF (_ADC_STATUS_PROGERR_NEGSELCONF << 10) /**< Shifted mode NEGSELCONF for ADC_STATUS */
-#define ADC_STATUS_WARM (0x1UL << 12) /**< ADC Warmed Up */
-#define _ADC_STATUS_WARM_SHIFT 12 /**< Shift value for ADC_WARM */
-#define _ADC_STATUS_WARM_MASK 0x1000UL /**< Bit mask for ADC_WARM */
-#define _ADC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
-#define ADC_STATUS_WARM_DEFAULT (_ADC_STATUS_WARM_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_STATUS */
-#define ADC_STATUS_SINGLEDV (0x1UL << 16) /**< Single Channel Data Valid */
-#define _ADC_STATUS_SINGLEDV_SHIFT 16 /**< Shift value for ADC_SINGLEDV */
-#define _ADC_STATUS_SINGLEDV_MASK 0x10000UL /**< Bit mask for ADC_SINGLEDV */
-#define _ADC_STATUS_SINGLEDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
-#define ADC_STATUS_SINGLEDV_DEFAULT (_ADC_STATUS_SINGLEDV_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_STATUS */
-#define ADC_STATUS_SCANDV (0x1UL << 17) /**< Scan Data Valid */
-#define _ADC_STATUS_SCANDV_SHIFT 17 /**< Shift value for ADC_SCANDV */
-#define _ADC_STATUS_SCANDV_MASK 0x20000UL /**< Bit mask for ADC_SCANDV */
-#define _ADC_STATUS_SCANDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
-#define ADC_STATUS_SCANDV_DEFAULT (_ADC_STATUS_SCANDV_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_STATUS */
-
-/* Bit fields for ADC SINGLECTRL */
-#define _ADC_SINGLECTRL_RESETVALUE 0x00FFFF00UL /**< Default value for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_MASK 0xAFFFFFFFUL /**< Mask for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_REP (0x1UL << 0) /**< Single Channel Repetitive Mode */
-#define _ADC_SINGLECTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */
-#define _ADC_SINGLECTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */
-#define _ADC_SINGLECTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_REP_DEFAULT (_ADC_SINGLECTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_DIFF (0x1UL << 1) /**< Single Channel Differential Mode */
-#define _ADC_SINGLECTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */
-#define _ADC_SINGLECTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */
-#define _ADC_SINGLECTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_DIFF_DEFAULT (_ADC_SINGLECTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_ADJ (0x1UL << 2) /**< Single Channel Result Adjustment */
-#define _ADC_SINGLECTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */
-#define _ADC_SINGLECTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */
-#define _ADC_SINGLECTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_ADJ_DEFAULT (_ADC_SINGLECTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_ADJ_RIGHT (_ADC_SINGLECTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_ADJ_LEFT (_ADC_SINGLECTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_RES_SHIFT 3 /**< Shift value for ADC_RES */
-#define _ADC_SINGLECTRL_RES_MASK 0x18UL /**< Bit mask for ADC_RES */
-#define _ADC_SINGLECTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_RES_DEFAULT (_ADC_SINGLECTRL_RES_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_RES_12BIT (_ADC_SINGLECTRL_RES_12BIT << 3) /**< Shifted mode 12BIT for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_RES_8BIT (_ADC_SINGLECTRL_RES_8BIT << 3) /**< Shifted mode 8BIT for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_RES_6BIT (_ADC_SINGLECTRL_RES_6BIT << 3) /**< Shifted mode 6BIT for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_RES_OVS (_ADC_SINGLECTRL_RES_OVS << 3) /**< Shifted mode OVS for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_REF_SHIFT 5 /**< Shift value for ADC_REF */
-#define _ADC_SINGLECTRL_REF_MASK 0xE0UL /**< Bit mask for ADC_REF */
-#define _ADC_SINGLECTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_REF_5V 0x00000003UL /**< Mode 5V for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_REF_CONF 0x00000007UL /**< Mode CONF for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_REF_DEFAULT (_ADC_SINGLECTRL_REF_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_REF_1V25 (_ADC_SINGLECTRL_REF_1V25 << 5) /**< Shifted mode 1V25 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_REF_2V5 (_ADC_SINGLECTRL_REF_2V5 << 5) /**< Shifted mode 2V5 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_REF_VDD (_ADC_SINGLECTRL_REF_VDD << 5) /**< Shifted mode VDD for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_REF_5V (_ADC_SINGLECTRL_REF_5V << 5) /**< Shifted mode 5V for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_REF_EXTSINGLE (_ADC_SINGLECTRL_REF_EXTSINGLE << 5) /**< Shifted mode EXTSINGLE for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_REF_2XEXTDIFF (_ADC_SINGLECTRL_REF_2XEXTDIFF << 5) /**< Shifted mode 2XEXTDIFF for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_REF_2XVDD (_ADC_SINGLECTRL_REF_2XVDD << 5) /**< Shifted mode 2XVDD for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_REF_CONF (_ADC_SINGLECTRL_REF_CONF << 5) /**< Shifted mode CONF for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_SHIFT 8 /**< Shift value for ADC_POSSEL */
-#define _ADC_SINGLECTRL_POSSEL_MASK 0xFF00UL /**< Bit mask for ADC_POSSEL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_AVDD 0x000000E0UL /**< Mode AVDD for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_BU 0x000000E1UL /**< Mode BU for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_AREG 0x000000E2UL /**< Mode AREG for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_VREGOUTPA 0x000000E3UL /**< Mode VREGOUTPA for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_PDBU 0x000000E4UL /**< Mode PDBU for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_IO0 0x000000E5UL /**< Mode IO0 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_IO1 0x000000E6UL /**< Mode IO1 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_VSP 0x000000E7UL /**< Mode VSP for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_OPA2 0x000000F2UL /**< Mode OPA2 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_TEMP 0x000000F3UL /**< Mode TEMP for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_DAC0OUT0 0x000000F4UL /**< Mode DAC0OUT0 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_R5VOUT 0x000000F5UL /**< Mode R5VOUT for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_SP1 0x000000F6UL /**< Mode SP1 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_SP2 0x000000F7UL /**< Mode SP2 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_DAC0OUT1 0x000000F8UL /**< Mode DAC0OUT1 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_SUBLSB 0x000000F9UL /**< Mode SUBLSB for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_OPA3 0x000000FAUL /**< Mode OPA3 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_DEFAULT 0x000000FFUL /**< Mode DEFAULT for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_POSSEL_VSS 0x000000FFUL /**< Mode VSS for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0XCH0 (_ADC_SINGLECTRL_POSSEL_APORT0XCH0 << 8) /**< Shifted mode APORT0XCH0 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0XCH1 (_ADC_SINGLECTRL_POSSEL_APORT0XCH1 << 8) /**< Shifted mode APORT0XCH1 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0XCH2 (_ADC_SINGLECTRL_POSSEL_APORT0XCH2 << 8) /**< Shifted mode APORT0XCH2 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0XCH3 (_ADC_SINGLECTRL_POSSEL_APORT0XCH3 << 8) /**< Shifted mode APORT0XCH3 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0XCH4 (_ADC_SINGLECTRL_POSSEL_APORT0XCH4 << 8) /**< Shifted mode APORT0XCH4 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0XCH5 (_ADC_SINGLECTRL_POSSEL_APORT0XCH5 << 8) /**< Shifted mode APORT0XCH5 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0XCH6 (_ADC_SINGLECTRL_POSSEL_APORT0XCH6 << 8) /**< Shifted mode APORT0XCH6 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0XCH7 (_ADC_SINGLECTRL_POSSEL_APORT0XCH7 << 8) /**< Shifted mode APORT0XCH7 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0XCH8 (_ADC_SINGLECTRL_POSSEL_APORT0XCH8 << 8) /**< Shifted mode APORT0XCH8 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0XCH9 (_ADC_SINGLECTRL_POSSEL_APORT0XCH9 << 8) /**< Shifted mode APORT0XCH9 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0XCH10 (_ADC_SINGLECTRL_POSSEL_APORT0XCH10 << 8) /**< Shifted mode APORT0XCH10 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0XCH11 (_ADC_SINGLECTRL_POSSEL_APORT0XCH11 << 8) /**< Shifted mode APORT0XCH11 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0XCH12 (_ADC_SINGLECTRL_POSSEL_APORT0XCH12 << 8) /**< Shifted mode APORT0XCH12 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0XCH13 (_ADC_SINGLECTRL_POSSEL_APORT0XCH13 << 8) /**< Shifted mode APORT0XCH13 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0XCH14 (_ADC_SINGLECTRL_POSSEL_APORT0XCH14 << 8) /**< Shifted mode APORT0XCH14 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0XCH15 (_ADC_SINGLECTRL_POSSEL_APORT0XCH15 << 8) /**< Shifted mode APORT0XCH15 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0YCH0 (_ADC_SINGLECTRL_POSSEL_APORT0YCH0 << 8) /**< Shifted mode APORT0YCH0 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0YCH1 (_ADC_SINGLECTRL_POSSEL_APORT0YCH1 << 8) /**< Shifted mode APORT0YCH1 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0YCH2 (_ADC_SINGLECTRL_POSSEL_APORT0YCH2 << 8) /**< Shifted mode APORT0YCH2 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0YCH3 (_ADC_SINGLECTRL_POSSEL_APORT0YCH3 << 8) /**< Shifted mode APORT0YCH3 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0YCH4 (_ADC_SINGLECTRL_POSSEL_APORT0YCH4 << 8) /**< Shifted mode APORT0YCH4 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0YCH5 (_ADC_SINGLECTRL_POSSEL_APORT0YCH5 << 8) /**< Shifted mode APORT0YCH5 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0YCH6 (_ADC_SINGLECTRL_POSSEL_APORT0YCH6 << 8) /**< Shifted mode APORT0YCH6 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0YCH7 (_ADC_SINGLECTRL_POSSEL_APORT0YCH7 << 8) /**< Shifted mode APORT0YCH7 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0YCH8 (_ADC_SINGLECTRL_POSSEL_APORT0YCH8 << 8) /**< Shifted mode APORT0YCH8 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0YCH9 (_ADC_SINGLECTRL_POSSEL_APORT0YCH9 << 8) /**< Shifted mode APORT0YCH9 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0YCH10 (_ADC_SINGLECTRL_POSSEL_APORT0YCH10 << 8) /**< Shifted mode APORT0YCH10 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0YCH11 (_ADC_SINGLECTRL_POSSEL_APORT0YCH11 << 8) /**< Shifted mode APORT0YCH11 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0YCH12 (_ADC_SINGLECTRL_POSSEL_APORT0YCH12 << 8) /**< Shifted mode APORT0YCH12 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0YCH13 (_ADC_SINGLECTRL_POSSEL_APORT0YCH13 << 8) /**< Shifted mode APORT0YCH13 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0YCH14 (_ADC_SINGLECTRL_POSSEL_APORT0YCH14 << 8) /**< Shifted mode APORT0YCH14 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT0YCH15 (_ADC_SINGLECTRL_POSSEL_APORT0YCH15 << 8) /**< Shifted mode APORT0YCH15 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1XCH0 (_ADC_SINGLECTRL_POSSEL_APORT1XCH0 << 8) /**< Shifted mode APORT1XCH0 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1YCH1 (_ADC_SINGLECTRL_POSSEL_APORT1YCH1 << 8) /**< Shifted mode APORT1YCH1 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1XCH2 (_ADC_SINGLECTRL_POSSEL_APORT1XCH2 << 8) /**< Shifted mode APORT1XCH2 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1YCH3 (_ADC_SINGLECTRL_POSSEL_APORT1YCH3 << 8) /**< Shifted mode APORT1YCH3 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1XCH4 (_ADC_SINGLECTRL_POSSEL_APORT1XCH4 << 8) /**< Shifted mode APORT1XCH4 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1YCH5 (_ADC_SINGLECTRL_POSSEL_APORT1YCH5 << 8) /**< Shifted mode APORT1YCH5 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1XCH6 (_ADC_SINGLECTRL_POSSEL_APORT1XCH6 << 8) /**< Shifted mode APORT1XCH6 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1YCH7 (_ADC_SINGLECTRL_POSSEL_APORT1YCH7 << 8) /**< Shifted mode APORT1YCH7 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1XCH8 (_ADC_SINGLECTRL_POSSEL_APORT1XCH8 << 8) /**< Shifted mode APORT1XCH8 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1YCH9 (_ADC_SINGLECTRL_POSSEL_APORT1YCH9 << 8) /**< Shifted mode APORT1YCH9 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1XCH10 (_ADC_SINGLECTRL_POSSEL_APORT1XCH10 << 8) /**< Shifted mode APORT1XCH10 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1YCH11 (_ADC_SINGLECTRL_POSSEL_APORT1YCH11 << 8) /**< Shifted mode APORT1YCH11 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1XCH12 (_ADC_SINGLECTRL_POSSEL_APORT1XCH12 << 8) /**< Shifted mode APORT1XCH12 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1YCH13 (_ADC_SINGLECTRL_POSSEL_APORT1YCH13 << 8) /**< Shifted mode APORT1YCH13 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1XCH14 (_ADC_SINGLECTRL_POSSEL_APORT1XCH14 << 8) /**< Shifted mode APORT1XCH14 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1YCH15 (_ADC_SINGLECTRL_POSSEL_APORT1YCH15 << 8) /**< Shifted mode APORT1YCH15 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1XCH16 (_ADC_SINGLECTRL_POSSEL_APORT1XCH16 << 8) /**< Shifted mode APORT1XCH16 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1YCH17 (_ADC_SINGLECTRL_POSSEL_APORT1YCH17 << 8) /**< Shifted mode APORT1YCH17 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1XCH18 (_ADC_SINGLECTRL_POSSEL_APORT1XCH18 << 8) /**< Shifted mode APORT1XCH18 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1YCH19 (_ADC_SINGLECTRL_POSSEL_APORT1YCH19 << 8) /**< Shifted mode APORT1YCH19 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1XCH20 (_ADC_SINGLECTRL_POSSEL_APORT1XCH20 << 8) /**< Shifted mode APORT1XCH20 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1YCH21 (_ADC_SINGLECTRL_POSSEL_APORT1YCH21 << 8) /**< Shifted mode APORT1YCH21 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1XCH22 (_ADC_SINGLECTRL_POSSEL_APORT1XCH22 << 8) /**< Shifted mode APORT1XCH22 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1YCH23 (_ADC_SINGLECTRL_POSSEL_APORT1YCH23 << 8) /**< Shifted mode APORT1YCH23 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1XCH24 (_ADC_SINGLECTRL_POSSEL_APORT1XCH24 << 8) /**< Shifted mode APORT1XCH24 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1YCH25 (_ADC_SINGLECTRL_POSSEL_APORT1YCH25 << 8) /**< Shifted mode APORT1YCH25 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1XCH26 (_ADC_SINGLECTRL_POSSEL_APORT1XCH26 << 8) /**< Shifted mode APORT1XCH26 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1YCH27 (_ADC_SINGLECTRL_POSSEL_APORT1YCH27 << 8) /**< Shifted mode APORT1YCH27 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1XCH28 (_ADC_SINGLECTRL_POSSEL_APORT1XCH28 << 8) /**< Shifted mode APORT1XCH28 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1YCH29 (_ADC_SINGLECTRL_POSSEL_APORT1YCH29 << 8) /**< Shifted mode APORT1YCH29 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1XCH30 (_ADC_SINGLECTRL_POSSEL_APORT1XCH30 << 8) /**< Shifted mode APORT1XCH30 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT1YCH31 (_ADC_SINGLECTRL_POSSEL_APORT1YCH31 << 8) /**< Shifted mode APORT1YCH31 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2YCH0 (_ADC_SINGLECTRL_POSSEL_APORT2YCH0 << 8) /**< Shifted mode APORT2YCH0 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2XCH1 (_ADC_SINGLECTRL_POSSEL_APORT2XCH1 << 8) /**< Shifted mode APORT2XCH1 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2YCH2 (_ADC_SINGLECTRL_POSSEL_APORT2YCH2 << 8) /**< Shifted mode APORT2YCH2 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2XCH3 (_ADC_SINGLECTRL_POSSEL_APORT2XCH3 << 8) /**< Shifted mode APORT2XCH3 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2YCH4 (_ADC_SINGLECTRL_POSSEL_APORT2YCH4 << 8) /**< Shifted mode APORT2YCH4 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2XCH5 (_ADC_SINGLECTRL_POSSEL_APORT2XCH5 << 8) /**< Shifted mode APORT2XCH5 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2YCH6 (_ADC_SINGLECTRL_POSSEL_APORT2YCH6 << 8) /**< Shifted mode APORT2YCH6 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2XCH7 (_ADC_SINGLECTRL_POSSEL_APORT2XCH7 << 8) /**< Shifted mode APORT2XCH7 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2YCH8 (_ADC_SINGLECTRL_POSSEL_APORT2YCH8 << 8) /**< Shifted mode APORT2YCH8 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2XCH9 (_ADC_SINGLECTRL_POSSEL_APORT2XCH9 << 8) /**< Shifted mode APORT2XCH9 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2YCH10 (_ADC_SINGLECTRL_POSSEL_APORT2YCH10 << 8) /**< Shifted mode APORT2YCH10 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2XCH11 (_ADC_SINGLECTRL_POSSEL_APORT2XCH11 << 8) /**< Shifted mode APORT2XCH11 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2YCH12 (_ADC_SINGLECTRL_POSSEL_APORT2YCH12 << 8) /**< Shifted mode APORT2YCH12 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2XCH13 (_ADC_SINGLECTRL_POSSEL_APORT2XCH13 << 8) /**< Shifted mode APORT2XCH13 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2YCH14 (_ADC_SINGLECTRL_POSSEL_APORT2YCH14 << 8) /**< Shifted mode APORT2YCH14 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2XCH15 (_ADC_SINGLECTRL_POSSEL_APORT2XCH15 << 8) /**< Shifted mode APORT2XCH15 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2YCH16 (_ADC_SINGLECTRL_POSSEL_APORT2YCH16 << 8) /**< Shifted mode APORT2YCH16 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2XCH17 (_ADC_SINGLECTRL_POSSEL_APORT2XCH17 << 8) /**< Shifted mode APORT2XCH17 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2YCH18 (_ADC_SINGLECTRL_POSSEL_APORT2YCH18 << 8) /**< Shifted mode APORT2YCH18 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2XCH19 (_ADC_SINGLECTRL_POSSEL_APORT2XCH19 << 8) /**< Shifted mode APORT2XCH19 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2YCH20 (_ADC_SINGLECTRL_POSSEL_APORT2YCH20 << 8) /**< Shifted mode APORT2YCH20 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2XCH21 (_ADC_SINGLECTRL_POSSEL_APORT2XCH21 << 8) /**< Shifted mode APORT2XCH21 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2YCH22 (_ADC_SINGLECTRL_POSSEL_APORT2YCH22 << 8) /**< Shifted mode APORT2YCH22 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2XCH23 (_ADC_SINGLECTRL_POSSEL_APORT2XCH23 << 8) /**< Shifted mode APORT2XCH23 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2YCH24 (_ADC_SINGLECTRL_POSSEL_APORT2YCH24 << 8) /**< Shifted mode APORT2YCH24 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2XCH25 (_ADC_SINGLECTRL_POSSEL_APORT2XCH25 << 8) /**< Shifted mode APORT2XCH25 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2YCH26 (_ADC_SINGLECTRL_POSSEL_APORT2YCH26 << 8) /**< Shifted mode APORT2YCH26 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2XCH27 (_ADC_SINGLECTRL_POSSEL_APORT2XCH27 << 8) /**< Shifted mode APORT2XCH27 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2YCH28 (_ADC_SINGLECTRL_POSSEL_APORT2YCH28 << 8) /**< Shifted mode APORT2YCH28 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2XCH29 (_ADC_SINGLECTRL_POSSEL_APORT2XCH29 << 8) /**< Shifted mode APORT2XCH29 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2YCH30 (_ADC_SINGLECTRL_POSSEL_APORT2YCH30 << 8) /**< Shifted mode APORT2YCH30 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT2XCH31 (_ADC_SINGLECTRL_POSSEL_APORT2XCH31 << 8) /**< Shifted mode APORT2XCH31 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3XCH0 (_ADC_SINGLECTRL_POSSEL_APORT3XCH0 << 8) /**< Shifted mode APORT3XCH0 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3YCH1 (_ADC_SINGLECTRL_POSSEL_APORT3YCH1 << 8) /**< Shifted mode APORT3YCH1 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3XCH2 (_ADC_SINGLECTRL_POSSEL_APORT3XCH2 << 8) /**< Shifted mode APORT3XCH2 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3YCH3 (_ADC_SINGLECTRL_POSSEL_APORT3YCH3 << 8) /**< Shifted mode APORT3YCH3 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3XCH4 (_ADC_SINGLECTRL_POSSEL_APORT3XCH4 << 8) /**< Shifted mode APORT3XCH4 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3YCH5 (_ADC_SINGLECTRL_POSSEL_APORT3YCH5 << 8) /**< Shifted mode APORT3YCH5 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3XCH6 (_ADC_SINGLECTRL_POSSEL_APORT3XCH6 << 8) /**< Shifted mode APORT3XCH6 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3YCH7 (_ADC_SINGLECTRL_POSSEL_APORT3YCH7 << 8) /**< Shifted mode APORT3YCH7 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3XCH8 (_ADC_SINGLECTRL_POSSEL_APORT3XCH8 << 8) /**< Shifted mode APORT3XCH8 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3YCH9 (_ADC_SINGLECTRL_POSSEL_APORT3YCH9 << 8) /**< Shifted mode APORT3YCH9 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3XCH10 (_ADC_SINGLECTRL_POSSEL_APORT3XCH10 << 8) /**< Shifted mode APORT3XCH10 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3YCH11 (_ADC_SINGLECTRL_POSSEL_APORT3YCH11 << 8) /**< Shifted mode APORT3YCH11 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3XCH12 (_ADC_SINGLECTRL_POSSEL_APORT3XCH12 << 8) /**< Shifted mode APORT3XCH12 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3YCH13 (_ADC_SINGLECTRL_POSSEL_APORT3YCH13 << 8) /**< Shifted mode APORT3YCH13 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3XCH14 (_ADC_SINGLECTRL_POSSEL_APORT3XCH14 << 8) /**< Shifted mode APORT3XCH14 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3YCH15 (_ADC_SINGLECTRL_POSSEL_APORT3YCH15 << 8) /**< Shifted mode APORT3YCH15 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3XCH16 (_ADC_SINGLECTRL_POSSEL_APORT3XCH16 << 8) /**< Shifted mode APORT3XCH16 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3YCH17 (_ADC_SINGLECTRL_POSSEL_APORT3YCH17 << 8) /**< Shifted mode APORT3YCH17 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3XCH18 (_ADC_SINGLECTRL_POSSEL_APORT3XCH18 << 8) /**< Shifted mode APORT3XCH18 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3YCH19 (_ADC_SINGLECTRL_POSSEL_APORT3YCH19 << 8) /**< Shifted mode APORT3YCH19 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3XCH20 (_ADC_SINGLECTRL_POSSEL_APORT3XCH20 << 8) /**< Shifted mode APORT3XCH20 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3YCH21 (_ADC_SINGLECTRL_POSSEL_APORT3YCH21 << 8) /**< Shifted mode APORT3YCH21 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3XCH22 (_ADC_SINGLECTRL_POSSEL_APORT3XCH22 << 8) /**< Shifted mode APORT3XCH22 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3YCH23 (_ADC_SINGLECTRL_POSSEL_APORT3YCH23 << 8) /**< Shifted mode APORT3YCH23 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3XCH24 (_ADC_SINGLECTRL_POSSEL_APORT3XCH24 << 8) /**< Shifted mode APORT3XCH24 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3YCH25 (_ADC_SINGLECTRL_POSSEL_APORT3YCH25 << 8) /**< Shifted mode APORT3YCH25 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3XCH26 (_ADC_SINGLECTRL_POSSEL_APORT3XCH26 << 8) /**< Shifted mode APORT3XCH26 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3YCH27 (_ADC_SINGLECTRL_POSSEL_APORT3YCH27 << 8) /**< Shifted mode APORT3YCH27 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3XCH28 (_ADC_SINGLECTRL_POSSEL_APORT3XCH28 << 8) /**< Shifted mode APORT3XCH28 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3YCH29 (_ADC_SINGLECTRL_POSSEL_APORT3YCH29 << 8) /**< Shifted mode APORT3YCH29 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3XCH30 (_ADC_SINGLECTRL_POSSEL_APORT3XCH30 << 8) /**< Shifted mode APORT3XCH30 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT3YCH31 (_ADC_SINGLECTRL_POSSEL_APORT3YCH31 << 8) /**< Shifted mode APORT3YCH31 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4YCH0 (_ADC_SINGLECTRL_POSSEL_APORT4YCH0 << 8) /**< Shifted mode APORT4YCH0 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4XCH1 (_ADC_SINGLECTRL_POSSEL_APORT4XCH1 << 8) /**< Shifted mode APORT4XCH1 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4YCH2 (_ADC_SINGLECTRL_POSSEL_APORT4YCH2 << 8) /**< Shifted mode APORT4YCH2 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4XCH3 (_ADC_SINGLECTRL_POSSEL_APORT4XCH3 << 8) /**< Shifted mode APORT4XCH3 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4YCH4 (_ADC_SINGLECTRL_POSSEL_APORT4YCH4 << 8) /**< Shifted mode APORT4YCH4 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4XCH5 (_ADC_SINGLECTRL_POSSEL_APORT4XCH5 << 8) /**< Shifted mode APORT4XCH5 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4YCH6 (_ADC_SINGLECTRL_POSSEL_APORT4YCH6 << 8) /**< Shifted mode APORT4YCH6 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4XCH7 (_ADC_SINGLECTRL_POSSEL_APORT4XCH7 << 8) /**< Shifted mode APORT4XCH7 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4YCH8 (_ADC_SINGLECTRL_POSSEL_APORT4YCH8 << 8) /**< Shifted mode APORT4YCH8 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4XCH9 (_ADC_SINGLECTRL_POSSEL_APORT4XCH9 << 8) /**< Shifted mode APORT4XCH9 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4YCH10 (_ADC_SINGLECTRL_POSSEL_APORT4YCH10 << 8) /**< Shifted mode APORT4YCH10 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4XCH11 (_ADC_SINGLECTRL_POSSEL_APORT4XCH11 << 8) /**< Shifted mode APORT4XCH11 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4YCH12 (_ADC_SINGLECTRL_POSSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4XCH13 (_ADC_SINGLECTRL_POSSEL_APORT4XCH13 << 8) /**< Shifted mode APORT4XCH13 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4YCH14 (_ADC_SINGLECTRL_POSSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4XCH15 (_ADC_SINGLECTRL_POSSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4YCH16 (_ADC_SINGLECTRL_POSSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4XCH17 (_ADC_SINGLECTRL_POSSEL_APORT4XCH17 << 8) /**< Shifted mode APORT4XCH17 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4YCH18 (_ADC_SINGLECTRL_POSSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4XCH19 (_ADC_SINGLECTRL_POSSEL_APORT4XCH19 << 8) /**< Shifted mode APORT4XCH19 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4YCH20 (_ADC_SINGLECTRL_POSSEL_APORT4YCH20 << 8) /**< Shifted mode APORT4YCH20 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4XCH21 (_ADC_SINGLECTRL_POSSEL_APORT4XCH21 << 8) /**< Shifted mode APORT4XCH21 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4YCH22 (_ADC_SINGLECTRL_POSSEL_APORT4YCH22 << 8) /**< Shifted mode APORT4YCH22 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4XCH23 (_ADC_SINGLECTRL_POSSEL_APORT4XCH23 << 8) /**< Shifted mode APORT4XCH23 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4YCH24 (_ADC_SINGLECTRL_POSSEL_APORT4YCH24 << 8) /**< Shifted mode APORT4YCH24 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4XCH25 (_ADC_SINGLECTRL_POSSEL_APORT4XCH25 << 8) /**< Shifted mode APORT4XCH25 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4YCH26 (_ADC_SINGLECTRL_POSSEL_APORT4YCH26 << 8) /**< Shifted mode APORT4YCH26 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4XCH27 (_ADC_SINGLECTRL_POSSEL_APORT4XCH27 << 8) /**< Shifted mode APORT4XCH27 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4YCH28 (_ADC_SINGLECTRL_POSSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4XCH29 (_ADC_SINGLECTRL_POSSEL_APORT4XCH29 << 8) /**< Shifted mode APORT4XCH29 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4YCH30 (_ADC_SINGLECTRL_POSSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_APORT4XCH31 (_ADC_SINGLECTRL_POSSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_AVDD (_ADC_SINGLECTRL_POSSEL_AVDD << 8) /**< Shifted mode AVDD for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_BU (_ADC_SINGLECTRL_POSSEL_BU << 8) /**< Shifted mode BU for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_AREG (_ADC_SINGLECTRL_POSSEL_AREG << 8) /**< Shifted mode AREG for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_VREGOUTPA (_ADC_SINGLECTRL_POSSEL_VREGOUTPA << 8) /**< Shifted mode VREGOUTPA for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_PDBU (_ADC_SINGLECTRL_POSSEL_PDBU << 8) /**< Shifted mode PDBU for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_IO0 (_ADC_SINGLECTRL_POSSEL_IO0 << 8) /**< Shifted mode IO0 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_IO1 (_ADC_SINGLECTRL_POSSEL_IO1 << 8) /**< Shifted mode IO1 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_VSP (_ADC_SINGLECTRL_POSSEL_VSP << 8) /**< Shifted mode VSP for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_OPA2 (_ADC_SINGLECTRL_POSSEL_OPA2 << 8) /**< Shifted mode OPA2 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_TEMP (_ADC_SINGLECTRL_POSSEL_TEMP << 8) /**< Shifted mode TEMP for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_DAC0OUT0 (_ADC_SINGLECTRL_POSSEL_DAC0OUT0 << 8) /**< Shifted mode DAC0OUT0 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_R5VOUT (_ADC_SINGLECTRL_POSSEL_R5VOUT << 8) /**< Shifted mode R5VOUT for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_SP1 (_ADC_SINGLECTRL_POSSEL_SP1 << 8) /**< Shifted mode SP1 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_SP2 (_ADC_SINGLECTRL_POSSEL_SP2 << 8) /**< Shifted mode SP2 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_DAC0OUT1 (_ADC_SINGLECTRL_POSSEL_DAC0OUT1 << 8) /**< Shifted mode DAC0OUT1 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_SUBLSB (_ADC_SINGLECTRL_POSSEL_SUBLSB << 8) /**< Shifted mode SUBLSB for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_OPA3 (_ADC_SINGLECTRL_POSSEL_OPA3 << 8) /**< Shifted mode OPA3 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_DEFAULT (_ADC_SINGLECTRL_POSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_POSSEL_VSS (_ADC_SINGLECTRL_POSSEL_VSS << 8) /**< Shifted mode VSS for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_SHIFT 16 /**< Shift value for ADC_NEGSEL */
-#define _ADC_SINGLECTRL_NEGSEL_MASK 0xFF0000UL /**< Bit mask for ADC_NEGSEL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_TESTN 0x000000F5UL /**< Mode TESTN for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_DEFAULT 0x000000FFUL /**< Mode DEFAULT for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_NEGSEL_VSS 0x000000FFUL /**< Mode VSS for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0XCH0 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH0 << 16) /**< Shifted mode APORT0XCH0 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0XCH1 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH1 << 16) /**< Shifted mode APORT0XCH1 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0XCH2 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH2 << 16) /**< Shifted mode APORT0XCH2 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0XCH3 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH3 << 16) /**< Shifted mode APORT0XCH3 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0XCH4 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH4 << 16) /**< Shifted mode APORT0XCH4 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0XCH5 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH5 << 16) /**< Shifted mode APORT0XCH5 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0XCH6 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH6 << 16) /**< Shifted mode APORT0XCH6 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0XCH7 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH7 << 16) /**< Shifted mode APORT0XCH7 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0XCH8 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH8 << 16) /**< Shifted mode APORT0XCH8 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0XCH9 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH9 << 16) /**< Shifted mode APORT0XCH9 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0XCH10 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH10 << 16) /**< Shifted mode APORT0XCH10 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0XCH11 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH11 << 16) /**< Shifted mode APORT0XCH11 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0XCH12 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH12 << 16) /**< Shifted mode APORT0XCH12 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0XCH13 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH13 << 16) /**< Shifted mode APORT0XCH13 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0XCH14 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH14 << 16) /**< Shifted mode APORT0XCH14 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0XCH15 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH15 << 16) /**< Shifted mode APORT0XCH15 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0YCH0 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH0 << 16) /**< Shifted mode APORT0YCH0 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0YCH1 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH1 << 16) /**< Shifted mode APORT0YCH1 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0YCH2 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH2 << 16) /**< Shifted mode APORT0YCH2 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0YCH3 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH3 << 16) /**< Shifted mode APORT0YCH3 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0YCH4 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH4 << 16) /**< Shifted mode APORT0YCH4 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0YCH5 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH5 << 16) /**< Shifted mode APORT0YCH5 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0YCH6 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH6 << 16) /**< Shifted mode APORT0YCH6 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0YCH7 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH7 << 16) /**< Shifted mode APORT0YCH7 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0YCH8 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH8 << 16) /**< Shifted mode APORT0YCH8 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0YCH9 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH9 << 16) /**< Shifted mode APORT0YCH9 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0YCH10 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH10 << 16) /**< Shifted mode APORT0YCH10 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0YCH11 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH11 << 16) /**< Shifted mode APORT0YCH11 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0YCH12 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH12 << 16) /**< Shifted mode APORT0YCH12 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0YCH13 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH13 << 16) /**< Shifted mode APORT0YCH13 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0YCH14 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH14 << 16) /**< Shifted mode APORT0YCH14 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT0YCH15 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH15 << 16) /**< Shifted mode APORT0YCH15 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1XCH0 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH0 << 16) /**< Shifted mode APORT1XCH0 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1YCH1 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH1 << 16) /**< Shifted mode APORT1YCH1 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1XCH2 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH2 << 16) /**< Shifted mode APORT1XCH2 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1YCH3 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH3 << 16) /**< Shifted mode APORT1YCH3 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1XCH4 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH4 << 16) /**< Shifted mode APORT1XCH4 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1YCH5 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH5 << 16) /**< Shifted mode APORT1YCH5 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1XCH6 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH6 << 16) /**< Shifted mode APORT1XCH6 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1YCH7 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH7 << 16) /**< Shifted mode APORT1YCH7 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1XCH8 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH8 << 16) /**< Shifted mode APORT1XCH8 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1YCH9 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH9 << 16) /**< Shifted mode APORT1YCH9 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1XCH10 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH10 << 16) /**< Shifted mode APORT1XCH10 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1YCH11 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH11 << 16) /**< Shifted mode APORT1YCH11 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1XCH12 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH12 << 16) /**< Shifted mode APORT1XCH12 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1YCH13 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH13 << 16) /**< Shifted mode APORT1YCH13 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1XCH14 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH14 << 16) /**< Shifted mode APORT1XCH14 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1YCH15 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH15 << 16) /**< Shifted mode APORT1YCH15 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1XCH16 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH16 << 16) /**< Shifted mode APORT1XCH16 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1YCH17 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH17 << 16) /**< Shifted mode APORT1YCH17 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1XCH18 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH18 << 16) /**< Shifted mode APORT1XCH18 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1YCH19 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH19 << 16) /**< Shifted mode APORT1YCH19 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1XCH20 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH20 << 16) /**< Shifted mode APORT1XCH20 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1YCH21 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH21 << 16) /**< Shifted mode APORT1YCH21 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1XCH22 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH22 << 16) /**< Shifted mode APORT1XCH22 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1YCH23 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH23 << 16) /**< Shifted mode APORT1YCH23 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1XCH24 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH24 << 16) /**< Shifted mode APORT1XCH24 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1YCH25 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH25 << 16) /**< Shifted mode APORT1YCH25 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1XCH26 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH26 << 16) /**< Shifted mode APORT1XCH26 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1YCH27 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH27 << 16) /**< Shifted mode APORT1YCH27 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1XCH28 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH28 << 16) /**< Shifted mode APORT1XCH28 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1YCH29 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH29 << 16) /**< Shifted mode APORT1YCH29 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1XCH30 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH30 << 16) /**< Shifted mode APORT1XCH30 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT1YCH31 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH31 << 16) /**< Shifted mode APORT1YCH31 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2YCH0 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH0 << 16) /**< Shifted mode APORT2YCH0 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2XCH1 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH1 << 16) /**< Shifted mode APORT2XCH1 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2YCH2 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH2 << 16) /**< Shifted mode APORT2YCH2 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2XCH3 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH3 << 16) /**< Shifted mode APORT2XCH3 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2YCH4 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH4 << 16) /**< Shifted mode APORT2YCH4 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2XCH5 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH5 << 16) /**< Shifted mode APORT2XCH5 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2YCH6 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH6 << 16) /**< Shifted mode APORT2YCH6 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2XCH7 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH7 << 16) /**< Shifted mode APORT2XCH7 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2YCH8 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH8 << 16) /**< Shifted mode APORT2YCH8 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2XCH9 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH9 << 16) /**< Shifted mode APORT2XCH9 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2YCH10 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH10 << 16) /**< Shifted mode APORT2YCH10 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2XCH11 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH11 << 16) /**< Shifted mode APORT2XCH11 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2YCH12 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH12 << 16) /**< Shifted mode APORT2YCH12 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2XCH13 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH13 << 16) /**< Shifted mode APORT2XCH13 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2YCH14 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH14 << 16) /**< Shifted mode APORT2YCH14 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2XCH15 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH15 << 16) /**< Shifted mode APORT2XCH15 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2YCH16 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH16 << 16) /**< Shifted mode APORT2YCH16 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2XCH17 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH17 << 16) /**< Shifted mode APORT2XCH17 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2YCH18 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH18 << 16) /**< Shifted mode APORT2YCH18 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2XCH19 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH19 << 16) /**< Shifted mode APORT2XCH19 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2YCH20 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH20 << 16) /**< Shifted mode APORT2YCH20 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2XCH21 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH21 << 16) /**< Shifted mode APORT2XCH21 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2YCH22 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH22 << 16) /**< Shifted mode APORT2YCH22 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2XCH23 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH23 << 16) /**< Shifted mode APORT2XCH23 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2YCH24 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH24 << 16) /**< Shifted mode APORT2YCH24 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2XCH25 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH25 << 16) /**< Shifted mode APORT2XCH25 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2YCH26 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH26 << 16) /**< Shifted mode APORT2YCH26 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2XCH27 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH27 << 16) /**< Shifted mode APORT2XCH27 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2YCH28 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH28 << 16) /**< Shifted mode APORT2YCH28 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2XCH29 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH29 << 16) /**< Shifted mode APORT2XCH29 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2YCH30 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH30 << 16) /**< Shifted mode APORT2YCH30 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT2XCH31 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH31 << 16) /**< Shifted mode APORT2XCH31 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3XCH0 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH0 << 16) /**< Shifted mode APORT3XCH0 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3YCH1 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH1 << 16) /**< Shifted mode APORT3YCH1 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3XCH2 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH2 << 16) /**< Shifted mode APORT3XCH2 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3YCH3 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH3 << 16) /**< Shifted mode APORT3YCH3 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3XCH4 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH4 << 16) /**< Shifted mode APORT3XCH4 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3YCH5 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH5 << 16) /**< Shifted mode APORT3YCH5 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3XCH6 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH6 << 16) /**< Shifted mode APORT3XCH6 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3YCH7 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH7 << 16) /**< Shifted mode APORT3YCH7 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3XCH8 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH8 << 16) /**< Shifted mode APORT3XCH8 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3YCH9 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH9 << 16) /**< Shifted mode APORT3YCH9 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3XCH10 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH10 << 16) /**< Shifted mode APORT3XCH10 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3YCH11 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH11 << 16) /**< Shifted mode APORT3YCH11 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3XCH12 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH12 << 16) /**< Shifted mode APORT3XCH12 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3YCH13 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH13 << 16) /**< Shifted mode APORT3YCH13 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3XCH14 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH14 << 16) /**< Shifted mode APORT3XCH14 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3YCH15 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH15 << 16) /**< Shifted mode APORT3YCH15 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3XCH16 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH16 << 16) /**< Shifted mode APORT3XCH16 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3YCH17 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH17 << 16) /**< Shifted mode APORT3YCH17 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3XCH18 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH18 << 16) /**< Shifted mode APORT3XCH18 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3YCH19 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH19 << 16) /**< Shifted mode APORT3YCH19 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3XCH20 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH20 << 16) /**< Shifted mode APORT3XCH20 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3YCH21 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH21 << 16) /**< Shifted mode APORT3YCH21 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3XCH22 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH22 << 16) /**< Shifted mode APORT3XCH22 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3YCH23 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH23 << 16) /**< Shifted mode APORT3YCH23 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3XCH24 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH24 << 16) /**< Shifted mode APORT3XCH24 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3YCH25 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH25 << 16) /**< Shifted mode APORT3YCH25 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3XCH26 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH26 << 16) /**< Shifted mode APORT3XCH26 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3YCH27 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH27 << 16) /**< Shifted mode APORT3YCH27 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3XCH28 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH28 << 16) /**< Shifted mode APORT3XCH28 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3YCH29 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH29 << 16) /**< Shifted mode APORT3YCH29 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3XCH30 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH30 << 16) /**< Shifted mode APORT3XCH30 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT3YCH31 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH31 << 16) /**< Shifted mode APORT3YCH31 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4YCH0 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH0 << 16) /**< Shifted mode APORT4YCH0 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4XCH1 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH1 << 16) /**< Shifted mode APORT4XCH1 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4YCH2 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH2 << 16) /**< Shifted mode APORT4YCH2 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4XCH3 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH3 << 16) /**< Shifted mode APORT4XCH3 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4YCH4 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH4 << 16) /**< Shifted mode APORT4YCH4 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4XCH5 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH5 << 16) /**< Shifted mode APORT4XCH5 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4YCH6 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH6 << 16) /**< Shifted mode APORT4YCH6 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4XCH7 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH7 << 16) /**< Shifted mode APORT4XCH7 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4YCH8 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH8 << 16) /**< Shifted mode APORT4YCH8 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4XCH9 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH9 << 16) /**< Shifted mode APORT4XCH9 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4YCH10 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH10 << 16) /**< Shifted mode APORT4YCH10 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4XCH11 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH11 << 16) /**< Shifted mode APORT4XCH11 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4YCH12 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH12 << 16) /**< Shifted mode APORT4YCH12 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4XCH13 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH13 << 16) /**< Shifted mode APORT4XCH13 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4YCH14 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH14 << 16) /**< Shifted mode APORT4YCH14 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4XCH15 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH15 << 16) /**< Shifted mode APORT4XCH15 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4YCH16 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH16 << 16) /**< Shifted mode APORT4YCH16 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4XCH17 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH17 << 16) /**< Shifted mode APORT4XCH17 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4YCH18 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH18 << 16) /**< Shifted mode APORT4YCH18 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4XCH19 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH19 << 16) /**< Shifted mode APORT4XCH19 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4YCH20 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH20 << 16) /**< Shifted mode APORT4YCH20 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4XCH21 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH21 << 16) /**< Shifted mode APORT4XCH21 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4YCH22 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH22 << 16) /**< Shifted mode APORT4YCH22 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4XCH23 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH23 << 16) /**< Shifted mode APORT4XCH23 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4YCH24 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH24 << 16) /**< Shifted mode APORT4YCH24 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4XCH25 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH25 << 16) /**< Shifted mode APORT4XCH25 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4YCH26 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH26 << 16) /**< Shifted mode APORT4YCH26 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4XCH27 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH27 << 16) /**< Shifted mode APORT4XCH27 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4YCH28 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH28 << 16) /**< Shifted mode APORT4YCH28 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4XCH29 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH29 << 16) /**< Shifted mode APORT4XCH29 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4YCH30 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH30 << 16) /**< Shifted mode APORT4YCH30 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_APORT4XCH31 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH31 << 16) /**< Shifted mode APORT4XCH31 for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_TESTN (_ADC_SINGLECTRL_NEGSEL_TESTN << 16) /**< Shifted mode TESTN for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_DEFAULT (_ADC_SINGLECTRL_NEGSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_NEGSEL_VSS (_ADC_SINGLECTRL_NEGSEL_VSS << 16) /**< Shifted mode VSS for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_AT_SHIFT 24 /**< Shift value for ADC_AT */
-#define _ADC_SINGLECTRL_AT_MASK 0xF000000UL /**< Bit mask for ADC_AT */
-#define _ADC_SINGLECTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_AT_3CYCLES 0x00000002UL /**< Mode 3CYCLES for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_AT_4CYCLES 0x00000003UL /**< Mode 4CYCLES for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_AT_8CYCLES 0x00000004UL /**< Mode 8CYCLES for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_AT_16CYCLES 0x00000005UL /**< Mode 16CYCLES for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_AT_32CYCLES 0x00000006UL /**< Mode 32CYCLES for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_AT_64CYCLES 0x00000007UL /**< Mode 64CYCLES for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_AT_128CYCLES 0x00000008UL /**< Mode 128CYCLES for ADC_SINGLECTRL */
-#define _ADC_SINGLECTRL_AT_256CYCLES 0x00000009UL /**< Mode 256CYCLES for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_AT_DEFAULT (_ADC_SINGLECTRL_AT_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_AT_1CYCLE (_ADC_SINGLECTRL_AT_1CYCLE << 24) /**< Shifted mode 1CYCLE for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_AT_2CYCLES (_ADC_SINGLECTRL_AT_2CYCLES << 24) /**< Shifted mode 2CYCLES for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_AT_3CYCLES (_ADC_SINGLECTRL_AT_3CYCLES << 24) /**< Shifted mode 3CYCLES for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_AT_4CYCLES (_ADC_SINGLECTRL_AT_4CYCLES << 24) /**< Shifted mode 4CYCLES for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_AT_8CYCLES (_ADC_SINGLECTRL_AT_8CYCLES << 24) /**< Shifted mode 8CYCLES for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_AT_16CYCLES (_ADC_SINGLECTRL_AT_16CYCLES << 24) /**< Shifted mode 16CYCLES for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_AT_32CYCLES (_ADC_SINGLECTRL_AT_32CYCLES << 24) /**< Shifted mode 32CYCLES for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_AT_64CYCLES (_ADC_SINGLECTRL_AT_64CYCLES << 24) /**< Shifted mode 64CYCLES for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_AT_128CYCLES (_ADC_SINGLECTRL_AT_128CYCLES << 24) /**< Shifted mode 128CYCLES for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_AT_256CYCLES (_ADC_SINGLECTRL_AT_256CYCLES << 24) /**< Shifted mode 256CYCLES for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_PRSEN (0x1UL << 29) /**< Single Channel PRS Trigger Enable */
-#define _ADC_SINGLECTRL_PRSEN_SHIFT 29 /**< Shift value for ADC_PRSEN */
-#define _ADC_SINGLECTRL_PRSEN_MASK 0x20000000UL /**< Bit mask for ADC_PRSEN */
-#define _ADC_SINGLECTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_PRSEN_DEFAULT (_ADC_SINGLECTRL_PRSEN_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_CMPEN (0x1UL << 31) /**< Compare Logic Enable for Single Channel */
-#define _ADC_SINGLECTRL_CMPEN_SHIFT 31 /**< Shift value for ADC_CMPEN */
-#define _ADC_SINGLECTRL_CMPEN_MASK 0x80000000UL /**< Bit mask for ADC_CMPEN */
-#define _ADC_SINGLECTRL_CMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
-#define ADC_SINGLECTRL_CMPEN_DEFAULT (_ADC_SINGLECTRL_CMPEN_DEFAULT << 31) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
-
-/* Bit fields for ADC SINGLECTRLX */
-#define _ADC_SINGLECTRLX_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_MASK 0xEFDF7FFFUL /**< Mask for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_VREFSEL_SHIFT 0 /**< Shift value for ADC_VREFSEL */
-#define _ADC_SINGLECTRLX_VREFSEL_MASK 0x7UL /**< Bit mask for ADC_VREFSEL */
-#define _ADC_SINGLECTRLX_VREFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_VREFSEL_VBGR 0x00000000UL /**< Mode VBGR for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_VREFSEL_VDDXWATT 0x00000001UL /**< Mode VDDXWATT for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_VREFSEL_VREFPWATT 0x00000002UL /**< Mode VREFPWATT for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_VREFSEL_VREFP 0x00000003UL /**< Mode VREFP for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_VREFSEL_VENTROPY 0x00000004UL /**< Mode VENTROPY for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_VREFSEL_VREFPNWATT 0x00000005UL /**< Mode VREFPNWATT for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_VREFSEL_VREFPN 0x00000006UL /**< Mode VREFPN for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_VREFSEL_VBGRLOW 0x00000007UL /**< Mode VBGRLOW for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_VREFSEL_DEFAULT (_ADC_SINGLECTRLX_VREFSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_VREFSEL_VBGR (_ADC_SINGLECTRLX_VREFSEL_VBGR << 0) /**< Shifted mode VBGR for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_VREFSEL_VDDXWATT (_ADC_SINGLECTRLX_VREFSEL_VDDXWATT << 0) /**< Shifted mode VDDXWATT for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_VREFSEL_VREFPWATT (_ADC_SINGLECTRLX_VREFSEL_VREFPWATT << 0) /**< Shifted mode VREFPWATT for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_VREFSEL_VREFP (_ADC_SINGLECTRLX_VREFSEL_VREFP << 0) /**< Shifted mode VREFP for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_VREFSEL_VENTROPY (_ADC_SINGLECTRLX_VREFSEL_VENTROPY << 0) /**< Shifted mode VENTROPY for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_VREFSEL_VREFPNWATT (_ADC_SINGLECTRLX_VREFSEL_VREFPNWATT << 0) /**< Shifted mode VREFPNWATT for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_VREFSEL_VREFPN (_ADC_SINGLECTRLX_VREFSEL_VREFPN << 0) /**< Shifted mode VREFPN for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_VREFSEL_VBGRLOW (_ADC_SINGLECTRLX_VREFSEL_VBGRLOW << 0) /**< Shifted mode VBGRLOW for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_VREFATTFIX (0x1UL << 3) /**< Enable Fixed Scaling on VREF */
-#define _ADC_SINGLECTRLX_VREFATTFIX_SHIFT 3 /**< Shift value for ADC_VREFATTFIX */
-#define _ADC_SINGLECTRLX_VREFATTFIX_MASK 0x8UL /**< Bit mask for ADC_VREFATTFIX */
-#define _ADC_SINGLECTRLX_VREFATTFIX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_VREFATTFIX_DEFAULT (_ADC_SINGLECTRLX_VREFATTFIX_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_VREFATT_SHIFT 4 /**< Shift value for ADC_VREFATT */
-#define _ADC_SINGLECTRLX_VREFATT_MASK 0xF0UL /**< Bit mask for ADC_VREFATT */
-#define _ADC_SINGLECTRLX_VREFATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_VREFATT_DEFAULT (_ADC_SINGLECTRLX_VREFATT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_VINATT_SHIFT 8 /**< Shift value for ADC_VINATT */
-#define _ADC_SINGLECTRLX_VINATT_MASK 0xF00UL /**< Bit mask for ADC_VINATT */
-#define _ADC_SINGLECTRLX_VINATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_VINATT_DEFAULT (_ADC_SINGLECTRLX_VINATT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_DVL_SHIFT 12 /**< Shift value for ADC_DVL */
-#define _ADC_SINGLECTRLX_DVL_MASK 0x3000UL /**< Bit mask for ADC_DVL */
-#define _ADC_SINGLECTRLX_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_DVL_DEFAULT (_ADC_SINGLECTRLX_DVL_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_FIFOOFACT (0x1UL << 14) /**< Single Channel FIFO Overflow Action */
-#define _ADC_SINGLECTRLX_FIFOOFACT_SHIFT 14 /**< Shift value for ADC_FIFOOFACT */
-#define _ADC_SINGLECTRLX_FIFOOFACT_MASK 0x4000UL /**< Bit mask for ADC_FIFOOFACT */
-#define _ADC_SINGLECTRLX_FIFOOFACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_FIFOOFACT_DISCARD 0x00000000UL /**< Mode DISCARD for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE 0x00000001UL /**< Mode OVERWRITE for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_FIFOOFACT_DEFAULT (_ADC_SINGLECTRLX_FIFOOFACT_DEFAULT << 14) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_FIFOOFACT_DISCARD (_ADC_SINGLECTRLX_FIFOOFACT_DISCARD << 14) /**< Shifted mode DISCARD for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE (_ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE << 14) /**< Shifted mode OVERWRITE for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_PRSMODE (0x1UL << 16) /**< Single Channel PRS Trigger Mode */
-#define _ADC_SINGLECTRLX_PRSMODE_SHIFT 16 /**< Shift value for ADC_PRSMODE */
-#define _ADC_SINGLECTRLX_PRSMODE_MASK 0x10000UL /**< Bit mask for ADC_PRSMODE */
-#define _ADC_SINGLECTRLX_PRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_PRSMODE_PULSED 0x00000000UL /**< Mode PULSED for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_PRSMODE_TIMED 0x00000001UL /**< Mode TIMED for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_PRSMODE_DEFAULT (_ADC_SINGLECTRLX_PRSMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_PRSMODE_PULSED (_ADC_SINGLECTRLX_PRSMODE_PULSED << 16) /**< Shifted mode PULSED for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_PRSMODE_TIMED (_ADC_SINGLECTRLX_PRSMODE_TIMED << 16) /**< Shifted mode TIMED for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_PRSSEL_SHIFT 17 /**< Shift value for ADC_PRSSEL */
-#define _ADC_SINGLECTRLX_PRSSEL_MASK 0x1E0000UL /**< Bit mask for ADC_PRSSEL */
-#define _ADC_SINGLECTRLX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_PRSSEL_DEFAULT (_ADC_SINGLECTRLX_PRSSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_PRSSEL_PRSCH0 (_ADC_SINGLECTRLX_PRSSEL_PRSCH0 << 17) /**< Shifted mode PRSCH0 for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_PRSSEL_PRSCH1 (_ADC_SINGLECTRLX_PRSSEL_PRSCH1 << 17) /**< Shifted mode PRSCH1 for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_PRSSEL_PRSCH2 (_ADC_SINGLECTRLX_PRSSEL_PRSCH2 << 17) /**< Shifted mode PRSCH2 for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_PRSSEL_PRSCH3 (_ADC_SINGLECTRLX_PRSSEL_PRSCH3 << 17) /**< Shifted mode PRSCH3 for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_PRSSEL_PRSCH4 (_ADC_SINGLECTRLX_PRSSEL_PRSCH4 << 17) /**< Shifted mode PRSCH4 for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_PRSSEL_PRSCH5 (_ADC_SINGLECTRLX_PRSSEL_PRSCH5 << 17) /**< Shifted mode PRSCH5 for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_PRSSEL_PRSCH6 (_ADC_SINGLECTRLX_PRSSEL_PRSCH6 << 17) /**< Shifted mode PRSCH6 for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_PRSSEL_PRSCH7 (_ADC_SINGLECTRLX_PRSSEL_PRSCH7 << 17) /**< Shifted mode PRSCH7 for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_PRSSEL_PRSCH8 (_ADC_SINGLECTRLX_PRSSEL_PRSCH8 << 17) /**< Shifted mode PRSCH8 for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_PRSSEL_PRSCH9 (_ADC_SINGLECTRLX_PRSSEL_PRSCH9 << 17) /**< Shifted mode PRSCH9 for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_PRSSEL_PRSCH10 (_ADC_SINGLECTRLX_PRSSEL_PRSCH10 << 17) /**< Shifted mode PRSCH10 for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_PRSSEL_PRSCH11 (_ADC_SINGLECTRLX_PRSSEL_PRSCH11 << 17) /**< Shifted mode PRSCH11 for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_CONVSTARTDELAY_SHIFT 22 /**< Shift value for ADC_CONVSTARTDELAY */
-#define _ADC_SINGLECTRLX_CONVSTARTDELAY_MASK 0x7C00000UL /**< Bit mask for ADC_CONVSTARTDELAY */
-#define _ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT (_ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT << 22) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_CONVSTARTDELAYEN (0x1UL << 27) /**< Enable Delaying Next Conversion Start */
-#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_SHIFT 27 /**< Shift value for ADC_CONVSTARTDELAYEN */
-#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_MASK 0x8000000UL /**< Bit mask for ADC_CONVSTARTDELAYEN */
-#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT (_ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_REPDELAY_SHIFT 29 /**< Shift value for ADC_REPDELAY */
-#define _ADC_SINGLECTRLX_REPDELAY_MASK 0xE0000000UL /**< Bit mask for ADC_REPDELAY */
-#define _ADC_SINGLECTRLX_REPDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_REPDELAY_NODELAY 0x00000000UL /**< Mode NODELAY for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_REPDELAY_4CYCLES 0x00000001UL /**< Mode 4CYCLES for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_REPDELAY_8CYCLES 0x00000002UL /**< Mode 8CYCLES for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_REPDELAY_16CYCLES 0x00000003UL /**< Mode 16CYCLES for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_REPDELAY_32CYCLES 0x00000004UL /**< Mode 32CYCLES for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_REPDELAY_64CYCLES 0x00000005UL /**< Mode 64CYCLES for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_REPDELAY_128CYCLES 0x00000006UL /**< Mode 128CYCLES for ADC_SINGLECTRLX */
-#define _ADC_SINGLECTRLX_REPDELAY_256CYCLES 0x00000007UL /**< Mode 256CYCLES for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_REPDELAY_DEFAULT (_ADC_SINGLECTRLX_REPDELAY_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_REPDELAY_NODELAY (_ADC_SINGLECTRLX_REPDELAY_NODELAY << 29) /**< Shifted mode NODELAY for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_REPDELAY_4CYCLES (_ADC_SINGLECTRLX_REPDELAY_4CYCLES << 29) /**< Shifted mode 4CYCLES for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_REPDELAY_8CYCLES (_ADC_SINGLECTRLX_REPDELAY_8CYCLES << 29) /**< Shifted mode 8CYCLES for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_REPDELAY_16CYCLES (_ADC_SINGLECTRLX_REPDELAY_16CYCLES << 29) /**< Shifted mode 16CYCLES for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_REPDELAY_32CYCLES (_ADC_SINGLECTRLX_REPDELAY_32CYCLES << 29) /**< Shifted mode 32CYCLES for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_REPDELAY_64CYCLES (_ADC_SINGLECTRLX_REPDELAY_64CYCLES << 29) /**< Shifted mode 64CYCLES for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_REPDELAY_128CYCLES (_ADC_SINGLECTRLX_REPDELAY_128CYCLES << 29) /**< Shifted mode 128CYCLES for ADC_SINGLECTRLX */
-#define ADC_SINGLECTRLX_REPDELAY_256CYCLES (_ADC_SINGLECTRLX_REPDELAY_256CYCLES << 29) /**< Shifted mode 256CYCLES for ADC_SINGLECTRLX */
-
-/* Bit fields for ADC SCANCTRL */
-#define _ADC_SCANCTRL_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_MASK 0xAF0000FFUL /**< Mask for ADC_SCANCTRL */
-#define ADC_SCANCTRL_REP (0x1UL << 0) /**< Scan Sequence Repetitive Mode */
-#define _ADC_SCANCTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */
-#define _ADC_SCANCTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */
-#define _ADC_SCANCTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
-#define ADC_SCANCTRL_REP_DEFAULT (_ADC_SCANCTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
-#define ADC_SCANCTRL_DIFF (0x1UL << 1) /**< Scan Sequence Differential Mode */
-#define _ADC_SCANCTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */
-#define _ADC_SCANCTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */
-#define _ADC_SCANCTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
-#define ADC_SCANCTRL_DIFF_DEFAULT (_ADC_SCANCTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
-#define ADC_SCANCTRL_ADJ (0x1UL << 2) /**< Scan Sequence Result Adjustment */
-#define _ADC_SCANCTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */
-#define _ADC_SCANCTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */
-#define _ADC_SCANCTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SCANCTRL */
-#define ADC_SCANCTRL_ADJ_DEFAULT (_ADC_SCANCTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
-#define ADC_SCANCTRL_ADJ_RIGHT (_ADC_SCANCTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SCANCTRL */
-#define ADC_SCANCTRL_ADJ_LEFT (_ADC_SCANCTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_RES_SHIFT 3 /**< Shift value for ADC_RES */
-#define _ADC_SCANCTRL_RES_MASK 0x18UL /**< Bit mask for ADC_RES */
-#define _ADC_SCANCTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SCANCTRL */
-#define ADC_SCANCTRL_RES_DEFAULT (_ADC_SCANCTRL_RES_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
-#define ADC_SCANCTRL_RES_12BIT (_ADC_SCANCTRL_RES_12BIT << 3) /**< Shifted mode 12BIT for ADC_SCANCTRL */
-#define ADC_SCANCTRL_RES_8BIT (_ADC_SCANCTRL_RES_8BIT << 3) /**< Shifted mode 8BIT for ADC_SCANCTRL */
-#define ADC_SCANCTRL_RES_6BIT (_ADC_SCANCTRL_RES_6BIT << 3) /**< Shifted mode 6BIT for ADC_SCANCTRL */
-#define ADC_SCANCTRL_RES_OVS (_ADC_SCANCTRL_RES_OVS << 3) /**< Shifted mode OVS for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_REF_SHIFT 5 /**< Shift value for ADC_REF */
-#define _ADC_SCANCTRL_REF_MASK 0xE0UL /**< Bit mask for ADC_REF */
-#define _ADC_SCANCTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_REF_5V 0x00000003UL /**< Mode 5V for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_REF_CONF 0x00000007UL /**< Mode CONF for ADC_SCANCTRL */
-#define ADC_SCANCTRL_REF_DEFAULT (_ADC_SCANCTRL_REF_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
-#define ADC_SCANCTRL_REF_1V25 (_ADC_SCANCTRL_REF_1V25 << 5) /**< Shifted mode 1V25 for ADC_SCANCTRL */
-#define ADC_SCANCTRL_REF_2V5 (_ADC_SCANCTRL_REF_2V5 << 5) /**< Shifted mode 2V5 for ADC_SCANCTRL */
-#define ADC_SCANCTRL_REF_VDD (_ADC_SCANCTRL_REF_VDD << 5) /**< Shifted mode VDD for ADC_SCANCTRL */
-#define ADC_SCANCTRL_REF_5V (_ADC_SCANCTRL_REF_5V << 5) /**< Shifted mode 5V for ADC_SCANCTRL */
-#define ADC_SCANCTRL_REF_EXTSINGLE (_ADC_SCANCTRL_REF_EXTSINGLE << 5) /**< Shifted mode EXTSINGLE for ADC_SCANCTRL */
-#define ADC_SCANCTRL_REF_2XEXTDIFF (_ADC_SCANCTRL_REF_2XEXTDIFF << 5) /**< Shifted mode 2XEXTDIFF for ADC_SCANCTRL */
-#define ADC_SCANCTRL_REF_2XVDD (_ADC_SCANCTRL_REF_2XVDD << 5) /**< Shifted mode 2XVDD for ADC_SCANCTRL */
-#define ADC_SCANCTRL_REF_CONF (_ADC_SCANCTRL_REF_CONF << 5) /**< Shifted mode CONF for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_AT_SHIFT 24 /**< Shift value for ADC_AT */
-#define _ADC_SCANCTRL_AT_MASK 0xF000000UL /**< Bit mask for ADC_AT */
-#define _ADC_SCANCTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_AT_3CYCLES 0x00000002UL /**< Mode 3CYCLES for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_AT_4CYCLES 0x00000003UL /**< Mode 4CYCLES for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_AT_8CYCLES 0x00000004UL /**< Mode 8CYCLES for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_AT_16CYCLES 0x00000005UL /**< Mode 16CYCLES for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_AT_32CYCLES 0x00000006UL /**< Mode 32CYCLES for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_AT_64CYCLES 0x00000007UL /**< Mode 64CYCLES for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_AT_128CYCLES 0x00000008UL /**< Mode 128CYCLES for ADC_SCANCTRL */
-#define _ADC_SCANCTRL_AT_256CYCLES 0x00000009UL /**< Mode 256CYCLES for ADC_SCANCTRL */
-#define ADC_SCANCTRL_AT_DEFAULT (_ADC_SCANCTRL_AT_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
-#define ADC_SCANCTRL_AT_1CYCLE (_ADC_SCANCTRL_AT_1CYCLE << 24) /**< Shifted mode 1CYCLE for ADC_SCANCTRL */
-#define ADC_SCANCTRL_AT_2CYCLES (_ADC_SCANCTRL_AT_2CYCLES << 24) /**< Shifted mode 2CYCLES for ADC_SCANCTRL */
-#define ADC_SCANCTRL_AT_3CYCLES (_ADC_SCANCTRL_AT_3CYCLES << 24) /**< Shifted mode 3CYCLES for ADC_SCANCTRL */
-#define ADC_SCANCTRL_AT_4CYCLES (_ADC_SCANCTRL_AT_4CYCLES << 24) /**< Shifted mode 4CYCLES for ADC_SCANCTRL */
-#define ADC_SCANCTRL_AT_8CYCLES (_ADC_SCANCTRL_AT_8CYCLES << 24) /**< Shifted mode 8CYCLES for ADC_SCANCTRL */
-#define ADC_SCANCTRL_AT_16CYCLES (_ADC_SCANCTRL_AT_16CYCLES << 24) /**< Shifted mode 16CYCLES for ADC_SCANCTRL */
-#define ADC_SCANCTRL_AT_32CYCLES (_ADC_SCANCTRL_AT_32CYCLES << 24) /**< Shifted mode 32CYCLES for ADC_SCANCTRL */
-#define ADC_SCANCTRL_AT_64CYCLES (_ADC_SCANCTRL_AT_64CYCLES << 24) /**< Shifted mode 64CYCLES for ADC_SCANCTRL */
-#define ADC_SCANCTRL_AT_128CYCLES (_ADC_SCANCTRL_AT_128CYCLES << 24) /**< Shifted mode 128CYCLES for ADC_SCANCTRL */
-#define ADC_SCANCTRL_AT_256CYCLES (_ADC_SCANCTRL_AT_256CYCLES << 24) /**< Shifted mode 256CYCLES for ADC_SCANCTRL */
-#define ADC_SCANCTRL_PRSEN (0x1UL << 29) /**< Scan Sequence PRS Trigger Enable */
-#define _ADC_SCANCTRL_PRSEN_SHIFT 29 /**< Shift value for ADC_PRSEN */
-#define _ADC_SCANCTRL_PRSEN_MASK 0x20000000UL /**< Bit mask for ADC_PRSEN */
-#define _ADC_SCANCTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
-#define ADC_SCANCTRL_PRSEN_DEFAULT (_ADC_SCANCTRL_PRSEN_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
-#define ADC_SCANCTRL_CMPEN (0x1UL << 31) /**< Compare Logic Enable for Scan */
-#define _ADC_SCANCTRL_CMPEN_SHIFT 31 /**< Shift value for ADC_CMPEN */
-#define _ADC_SCANCTRL_CMPEN_MASK 0x80000000UL /**< Bit mask for ADC_CMPEN */
-#define _ADC_SCANCTRL_CMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
-#define ADC_SCANCTRL_CMPEN_DEFAULT (_ADC_SCANCTRL_CMPEN_DEFAULT << 31) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
-
-/* Bit fields for ADC SCANCTRLX */
-#define _ADC_SCANCTRLX_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_MASK 0xEFDF7FFFUL /**< Mask for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_VREFSEL_SHIFT 0 /**< Shift value for ADC_VREFSEL */
-#define _ADC_SCANCTRLX_VREFSEL_MASK 0x7UL /**< Bit mask for ADC_VREFSEL */
-#define _ADC_SCANCTRLX_VREFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_VREFSEL_VBGR 0x00000000UL /**< Mode VBGR for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_VREFSEL_VDDXWATT 0x00000001UL /**< Mode VDDXWATT for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_VREFSEL_VREFPWATT 0x00000002UL /**< Mode VREFPWATT for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_VREFSEL_VREFP 0x00000003UL /**< Mode VREFP for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_VREFSEL_VREFPNWATT 0x00000005UL /**< Mode VREFPNWATT for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_VREFSEL_VREFPN 0x00000006UL /**< Mode VREFPN for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_VREFSEL_VBGRLOW 0x00000007UL /**< Mode VBGRLOW for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_VREFSEL_DEFAULT (_ADC_SCANCTRLX_VREFSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_VREFSEL_VBGR (_ADC_SCANCTRLX_VREFSEL_VBGR << 0) /**< Shifted mode VBGR for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_VREFSEL_VDDXWATT (_ADC_SCANCTRLX_VREFSEL_VDDXWATT << 0) /**< Shifted mode VDDXWATT for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_VREFSEL_VREFPWATT (_ADC_SCANCTRLX_VREFSEL_VREFPWATT << 0) /**< Shifted mode VREFPWATT for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_VREFSEL_VREFP (_ADC_SCANCTRLX_VREFSEL_VREFP << 0) /**< Shifted mode VREFP for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_VREFSEL_VREFPNWATT (_ADC_SCANCTRLX_VREFSEL_VREFPNWATT << 0) /**< Shifted mode VREFPNWATT for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_VREFSEL_VREFPN (_ADC_SCANCTRLX_VREFSEL_VREFPN << 0) /**< Shifted mode VREFPN for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_VREFSEL_VBGRLOW (_ADC_SCANCTRLX_VREFSEL_VBGRLOW << 0) /**< Shifted mode VBGRLOW for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_VREFATTFIX (0x1UL << 3) /**< Enable Fixed Scaling on VREF */
-#define _ADC_SCANCTRLX_VREFATTFIX_SHIFT 3 /**< Shift value for ADC_VREFATTFIX */
-#define _ADC_SCANCTRLX_VREFATTFIX_MASK 0x8UL /**< Bit mask for ADC_VREFATTFIX */
-#define _ADC_SCANCTRLX_VREFATTFIX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_VREFATTFIX_DEFAULT (_ADC_SCANCTRLX_VREFATTFIX_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_VREFATT_SHIFT 4 /**< Shift value for ADC_VREFATT */
-#define _ADC_SCANCTRLX_VREFATT_MASK 0xF0UL /**< Bit mask for ADC_VREFATT */
-#define _ADC_SCANCTRLX_VREFATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_VREFATT_DEFAULT (_ADC_SCANCTRLX_VREFATT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_VINATT_SHIFT 8 /**< Shift value for ADC_VINATT */
-#define _ADC_SCANCTRLX_VINATT_MASK 0xF00UL /**< Bit mask for ADC_VINATT */
-#define _ADC_SCANCTRLX_VINATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_VINATT_DEFAULT (_ADC_SCANCTRLX_VINATT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_DVL_SHIFT 12 /**< Shift value for ADC_DVL */
-#define _ADC_SCANCTRLX_DVL_MASK 0x3000UL /**< Bit mask for ADC_DVL */
-#define _ADC_SCANCTRLX_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_DVL_DEFAULT (_ADC_SCANCTRLX_DVL_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_FIFOOFACT (0x1UL << 14) /**< Scan FIFO Overflow Action */
-#define _ADC_SCANCTRLX_FIFOOFACT_SHIFT 14 /**< Shift value for ADC_FIFOOFACT */
-#define _ADC_SCANCTRLX_FIFOOFACT_MASK 0x4000UL /**< Bit mask for ADC_FIFOOFACT */
-#define _ADC_SCANCTRLX_FIFOOFACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_FIFOOFACT_DISCARD 0x00000000UL /**< Mode DISCARD for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_FIFOOFACT_OVERWRITE 0x00000001UL /**< Mode OVERWRITE for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_FIFOOFACT_DEFAULT (_ADC_SCANCTRLX_FIFOOFACT_DEFAULT << 14) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_FIFOOFACT_DISCARD (_ADC_SCANCTRLX_FIFOOFACT_DISCARD << 14) /**< Shifted mode DISCARD for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_FIFOOFACT_OVERWRITE (_ADC_SCANCTRLX_FIFOOFACT_OVERWRITE << 14) /**< Shifted mode OVERWRITE for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_PRSMODE (0x1UL << 16) /**< Scan PRS Trigger Mode */
-#define _ADC_SCANCTRLX_PRSMODE_SHIFT 16 /**< Shift value for ADC_PRSMODE */
-#define _ADC_SCANCTRLX_PRSMODE_MASK 0x10000UL /**< Bit mask for ADC_PRSMODE */
-#define _ADC_SCANCTRLX_PRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_PRSMODE_PULSED 0x00000000UL /**< Mode PULSED for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_PRSMODE_TIMED 0x00000001UL /**< Mode TIMED for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_PRSMODE_DEFAULT (_ADC_SCANCTRLX_PRSMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_PRSMODE_PULSED (_ADC_SCANCTRLX_PRSMODE_PULSED << 16) /**< Shifted mode PULSED for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_PRSMODE_TIMED (_ADC_SCANCTRLX_PRSMODE_TIMED << 16) /**< Shifted mode TIMED for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_PRSSEL_SHIFT 17 /**< Shift value for ADC_PRSSEL */
-#define _ADC_SCANCTRLX_PRSSEL_MASK 0x1E0000UL /**< Bit mask for ADC_PRSSEL */
-#define _ADC_SCANCTRLX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_PRSSEL_DEFAULT (_ADC_SCANCTRLX_PRSSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_PRSSEL_PRSCH0 (_ADC_SCANCTRLX_PRSSEL_PRSCH0 << 17) /**< Shifted mode PRSCH0 for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_PRSSEL_PRSCH1 (_ADC_SCANCTRLX_PRSSEL_PRSCH1 << 17) /**< Shifted mode PRSCH1 for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_PRSSEL_PRSCH2 (_ADC_SCANCTRLX_PRSSEL_PRSCH2 << 17) /**< Shifted mode PRSCH2 for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_PRSSEL_PRSCH3 (_ADC_SCANCTRLX_PRSSEL_PRSCH3 << 17) /**< Shifted mode PRSCH3 for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_PRSSEL_PRSCH4 (_ADC_SCANCTRLX_PRSSEL_PRSCH4 << 17) /**< Shifted mode PRSCH4 for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_PRSSEL_PRSCH5 (_ADC_SCANCTRLX_PRSSEL_PRSCH5 << 17) /**< Shifted mode PRSCH5 for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_PRSSEL_PRSCH6 (_ADC_SCANCTRLX_PRSSEL_PRSCH6 << 17) /**< Shifted mode PRSCH6 for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_PRSSEL_PRSCH7 (_ADC_SCANCTRLX_PRSSEL_PRSCH7 << 17) /**< Shifted mode PRSCH7 for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_PRSSEL_PRSCH8 (_ADC_SCANCTRLX_PRSSEL_PRSCH8 << 17) /**< Shifted mode PRSCH8 for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_PRSSEL_PRSCH9 (_ADC_SCANCTRLX_PRSSEL_PRSCH9 << 17) /**< Shifted mode PRSCH9 for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_PRSSEL_PRSCH10 (_ADC_SCANCTRLX_PRSSEL_PRSCH10 << 17) /**< Shifted mode PRSCH10 for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_PRSSEL_PRSCH11 (_ADC_SCANCTRLX_PRSSEL_PRSCH11 << 17) /**< Shifted mode PRSCH11 for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_CONVSTARTDELAY_SHIFT 22 /**< Shift value for ADC_CONVSTARTDELAY */
-#define _ADC_SCANCTRLX_CONVSTARTDELAY_MASK 0x7C00000UL /**< Bit mask for ADC_CONVSTARTDELAY */
-#define _ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT (_ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT << 22) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_CONVSTARTDELAYEN (0x1UL << 27) /**< Enable Delaying Next Conversion Start */
-#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_SHIFT 27 /**< Shift value for ADC_CONVSTARTDELAYEN */
-#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_MASK 0x8000000UL /**< Bit mask for ADC_CONVSTARTDELAYEN */
-#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT (_ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_REPDELAY_SHIFT 29 /**< Shift value for ADC_REPDELAY */
-#define _ADC_SCANCTRLX_REPDELAY_MASK 0xE0000000UL /**< Bit mask for ADC_REPDELAY */
-#define _ADC_SCANCTRLX_REPDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_REPDELAY_NODELAY 0x00000000UL /**< Mode NODELAY for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_REPDELAY_4CYCLES 0x00000001UL /**< Mode 4CYCLES for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_REPDELAY_8CYCLES 0x00000002UL /**< Mode 8CYCLES for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_REPDELAY_16CYCLES 0x00000003UL /**< Mode 16CYCLES for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_REPDELAY_32CYCLES 0x00000004UL /**< Mode 32CYCLES for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_REPDELAY_64CYCLES 0x00000005UL /**< Mode 64CYCLES for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_REPDELAY_128CYCLES 0x00000006UL /**< Mode 128CYCLES for ADC_SCANCTRLX */
-#define _ADC_SCANCTRLX_REPDELAY_256CYCLES 0x00000007UL /**< Mode 256CYCLES for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_REPDELAY_DEFAULT (_ADC_SCANCTRLX_REPDELAY_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_REPDELAY_NODELAY (_ADC_SCANCTRLX_REPDELAY_NODELAY << 29) /**< Shifted mode NODELAY for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_REPDELAY_4CYCLES (_ADC_SCANCTRLX_REPDELAY_4CYCLES << 29) /**< Shifted mode 4CYCLES for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_REPDELAY_8CYCLES (_ADC_SCANCTRLX_REPDELAY_8CYCLES << 29) /**< Shifted mode 8CYCLES for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_REPDELAY_16CYCLES (_ADC_SCANCTRLX_REPDELAY_16CYCLES << 29) /**< Shifted mode 16CYCLES for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_REPDELAY_32CYCLES (_ADC_SCANCTRLX_REPDELAY_32CYCLES << 29) /**< Shifted mode 32CYCLES for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_REPDELAY_64CYCLES (_ADC_SCANCTRLX_REPDELAY_64CYCLES << 29) /**< Shifted mode 64CYCLES for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_REPDELAY_128CYCLES (_ADC_SCANCTRLX_REPDELAY_128CYCLES << 29) /**< Shifted mode 128CYCLES for ADC_SCANCTRLX */
-#define ADC_SCANCTRLX_REPDELAY_256CYCLES (_ADC_SCANCTRLX_REPDELAY_256CYCLES << 29) /**< Shifted mode 256CYCLES for ADC_SCANCTRLX */
-
-/* Bit fields for ADC SCANMASK */
-#define _ADC_SCANMASK_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANMASK */
-#define _ADC_SCANMASK_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_SHIFT 0 /**< Shift value for ADC_SCANINPUTEN */
-#define _ADC_SCANMASK_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_SCANINPUTEN */
-#define _ADC_SCANMASK_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL 0x00000001UL /**< Mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT0 0x00000001UL /**< Mode INPUT0 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT1 0x00000002UL /**< Mode INPUT1 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 0x00000002UL /**< Mode INPUT1INPUT2 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT2 0x00000004UL /**< Mode INPUT2 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL 0x00000004UL /**< Mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT3 0x00000008UL /**< Mode INPUT3 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 0x00000008UL /**< Mode INPUT3INPUT4 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT4 0x00000010UL /**< Mode INPUT4 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL 0x00000010UL /**< Mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 0x00000020UL /**< Mode INPUT5INPUT6 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT5 0x00000020UL /**< Mode INPUT5 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL 0x00000040UL /**< Mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT6 0x00000040UL /**< Mode INPUT6 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT7 0x00000080UL /**< Mode INPUT7 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 0x00000080UL /**< Mode INPUT7INPUT0 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 0x00000100UL /**< Mode INPUT8INPUT9 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT8 0x00000100UL /**< Mode INPUT8 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT9 0x00000200UL /**< Mode INPUT9 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL 0x00000200UL /**< Mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 0x00000400UL /**< Mode INPUT10INPUT11 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT10 0x00000400UL /**< Mode INPUT10 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL 0x00000800UL /**< Mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT11 0x00000800UL /**< Mode INPUT11 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 0x00001000UL /**< Mode INPUT12INPUT13 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT12 0x00001000UL /**< Mode INPUT12 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL 0x00002000UL /**< Mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT13 0x00002000UL /**< Mode INPUT13 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 0x00004000UL /**< Mode INPUT14INPUT15 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT14 0x00004000UL /**< Mode INPUT14 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL 0x00008000UL /**< Mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT15 0x00008000UL /**< Mode INPUT15 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 0x00010000UL /**< Mode INPUT16INPUT17 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT16 0x00010000UL /**< Mode INPUT16 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 0x00020000UL /**< Mode INPUT17INPUT18 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT17 0x00020000UL /**< Mode INPUT17 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 0x00040000UL /**< Mode INPUT18INPUT19 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT18 0x00040000UL /**< Mode INPUT18 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT19 0x00080000UL /**< Mode INPUT19 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 0x00080000UL /**< Mode INPUT19INPUT20 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 0x00100000UL /**< Mode INPUT20INPUT21 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT20 0x00100000UL /**< Mode INPUT20 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT21 0x00200000UL /**< Mode INPUT21 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 0x00200000UL /**< Mode INPUT21INPUT22 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 0x00400000UL /**< Mode INPUT22INPUT23 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT22 0x00400000UL /**< Mode INPUT22 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 0x00800000UL /**< Mode INPUT23INPUT16 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT23 0x00800000UL /**< Mode INPUT23 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT24 0x01000000UL /**< Mode INPUT24 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 0x01000000UL /**< Mode INPUT24INPUT25 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 0x02000000UL /**< Mode INPUT25INPUT26 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT25 0x02000000UL /**< Mode INPUT25 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT26 0x04000000UL /**< Mode INPUT26 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 0x04000000UL /**< Mode INPUT26INPUT27 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 0x08000000UL /**< Mode INPUT27INPUT28 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT27 0x08000000UL /**< Mode INPUT27 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 0x10000000UL /**< Mode INPUT28INPUT29 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT28 0x10000000UL /**< Mode INPUT28 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT29 0x20000000UL /**< Mode INPUT29 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 0x20000000UL /**< Mode INPUT29INPUT30 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT30 0x40000000UL /**< Mode INPUT30 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 0x40000000UL /**< Mode INPUT30INPUT31 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 0x80000000UL /**< Mode INPUT31INPUT24 for ADC_SCANMASK */
-#define _ADC_SCANMASK_SCANINPUTEN_INPUT31 0x80000000UL /**< Mode INPUT31 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_DEFAULT (_ADC_SCANMASK_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL << 0) /**< Shifted mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT0 (_ADC_SCANMASK_SCANINPUTEN_INPUT0 << 0) /**< Shifted mode INPUT0 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT1 (_ADC_SCANMASK_SCANINPUTEN_INPUT1 << 0) /**< Shifted mode INPUT1 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 (_ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 << 0) /**< Shifted mode INPUT1INPUT2 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT2 (_ADC_SCANMASK_SCANINPUTEN_INPUT2 << 0) /**< Shifted mode INPUT2 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL << 0) /**< Shifted mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT3 (_ADC_SCANMASK_SCANINPUTEN_INPUT3 << 0) /**< Shifted mode INPUT3 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 << 0) /**< Shifted mode INPUT3INPUT4 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT4 << 0) /**< Shifted mode INPUT4 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL << 0) /**< Shifted mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 (_ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 << 0) /**< Shifted mode INPUT5INPUT6 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT5 (_ADC_SCANMASK_SCANINPUTEN_INPUT5 << 0) /**< Shifted mode INPUT5 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL << 0) /**< Shifted mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT6 (_ADC_SCANMASK_SCANINPUTEN_INPUT6 << 0) /**< Shifted mode INPUT6 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT7 (_ADC_SCANMASK_SCANINPUTEN_INPUT7 << 0) /**< Shifted mode INPUT7 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 (_ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 << 0) /**< Shifted mode INPUT7INPUT0 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 << 0) /**< Shifted mode INPUT8INPUT9 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT8 (_ADC_SCANMASK_SCANINPUTEN_INPUT8 << 0) /**< Shifted mode INPUT8 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT9 << 0) /**< Shifted mode INPUT9 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL << 0) /**< Shifted mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 << 0) /**< Shifted mode INPUT10INPUT11 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT10 (_ADC_SCANMASK_SCANINPUTEN_INPUT10 << 0) /**< Shifted mode INPUT10 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL << 0) /**< Shifted mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT11 << 0) /**< Shifted mode INPUT11 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 << 0) /**< Shifted mode INPUT12INPUT13 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT12 (_ADC_SCANMASK_SCANINPUTEN_INPUT12 << 0) /**< Shifted mode INPUT12 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL << 0) /**< Shifted mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT13 << 0) /**< Shifted mode INPUT13 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 << 0) /**< Shifted mode INPUT14INPUT15 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT14 (_ADC_SCANMASK_SCANINPUTEN_INPUT14 << 0) /**< Shifted mode INPUT14 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL << 0) /**< Shifted mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT15 << 0) /**< Shifted mode INPUT15 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 << 0) /**< Shifted mode INPUT16INPUT17 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT16 << 0) /**< Shifted mode INPUT16 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 << 0) /**< Shifted mode INPUT17INPUT18 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT17 << 0) /**< Shifted mode INPUT17 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 (_ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 << 0) /**< Shifted mode INPUT18INPUT19 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT18 << 0) /**< Shifted mode INPUT18 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT19 (_ADC_SCANMASK_SCANINPUTEN_INPUT19 << 0) /**< Shifted mode INPUT19 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 (_ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 << 0) /**< Shifted mode INPUT19INPUT20 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 << 0) /**< Shifted mode INPUT20INPUT21 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT20 (_ADC_SCANMASK_SCANINPUTEN_INPUT20 << 0) /**< Shifted mode INPUT20 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT21 << 0) /**< Shifted mode INPUT21 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 (_ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 << 0) /**< Shifted mode INPUT21INPUT22 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 (_ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 << 0) /**< Shifted mode INPUT22INPUT23 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT22 (_ADC_SCANMASK_SCANINPUTEN_INPUT22 << 0) /**< Shifted mode INPUT22 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 << 0) /**< Shifted mode INPUT23INPUT16 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT23 (_ADC_SCANMASK_SCANINPUTEN_INPUT23 << 0) /**< Shifted mode INPUT23 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT24 << 0) /**< Shifted mode INPUT24 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 (_ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 << 0) /**< Shifted mode INPUT24INPUT25 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 << 0) /**< Shifted mode INPUT25INPUT26 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT25 (_ADC_SCANMASK_SCANINPUTEN_INPUT25 << 0) /**< Shifted mode INPUT25 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT26 << 0) /**< Shifted mode INPUT26 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 (_ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 << 0) /**< Shifted mode INPUT26INPUT27 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 << 0) /**< Shifted mode INPUT27INPUT28 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT27 (_ADC_SCANMASK_SCANINPUTEN_INPUT27 << 0) /**< Shifted mode INPUT27 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 << 0) /**< Shifted mode INPUT28INPUT29 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT28 << 0) /**< Shifted mode INPUT28 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT29 << 0) /**< Shifted mode INPUT29 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 << 0) /**< Shifted mode INPUT29INPUT30 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT30 << 0) /**< Shifted mode INPUT30 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 (_ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 << 0) /**< Shifted mode INPUT30INPUT31 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 << 0) /**< Shifted mode INPUT31INPUT24 for ADC_SCANMASK */
-#define ADC_SCANMASK_SCANINPUTEN_INPUT31 (_ADC_SCANMASK_SCANINPUTEN_INPUT31 << 0) /**< Shifted mode INPUT31 for ADC_SCANMASK */
-
-/* Bit fields for ADC SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_MASK 0x1F1F1F1FUL /**< Mask for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_SHIFT 0 /**< Shift value for ADC_INPUT0TO7SEL */
-#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_MASK 0x1FUL /**< Bit mask for ADC_INPUT0TO7SEL */
-#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7 << 0) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15 << 0) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7 << 0) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15 << 0) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23 << 0) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31 << 0) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7 << 0) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15 << 0) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23 << 0) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31 << 0) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7 << 0) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15 << 0) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23 << 0) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31 << 0) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7 << 0) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15 << 0) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23 << 0) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31 << 0) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_SHIFT 8 /**< Shift value for ADC_INPUT8TO15SEL */
-#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_MASK 0x1F00UL /**< Bit mask for ADC_INPUT8TO15SEL */
-#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7 << 8) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15 << 8) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7 << 8) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15 << 8) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23 << 8) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31 << 8) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7 << 8) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15 << 8) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23 << 8) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31 << 8) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7 << 8) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15 << 8) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23 << 8) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31 << 8) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7 << 8) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15 << 8) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23 << 8) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31 << 8) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_SHIFT 16 /**< Shift value for ADC_INPUT16TO23SEL */
-#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_MASK 0x1F0000UL /**< Bit mask for ADC_INPUT16TO23SEL */
-#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7 << 16) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15 << 16) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7 << 16) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15 << 16) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7 << 16) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15 << 16) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23 << 16) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31 << 16) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7 << 16) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15 << 16) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7 << 16) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15 << 16) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23 << 16) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31 << 16) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_SHIFT 24 /**< Shift value for ADC_INPUT24TO31SEL */
-#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_MASK 0x1F000000UL /**< Bit mask for ADC_INPUT24TO31SEL */
-#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
-#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7 << 24) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15 << 24) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7 << 24) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15 << 24) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7 << 24) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15 << 24) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23 << 24) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31 << 24) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7 << 24) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15 << 24) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7 << 24) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15 << 24) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23 << 24) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
-#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31 << 24) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
-
-/* Bit fields for ADC SCANNEGSEL */
-#define _ADC_SCANNEGSEL_RESETVALUE 0x000039E4UL /**< Default value for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_MASK 0x0000FFFFUL /**< Mask for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT0NEGSEL_SHIFT 0 /**< Shift value for ADC_INPUT0NEGSEL */
-#define _ADC_SCANNEGSEL_INPUT0NEGSEL_MASK 0x3UL /**< Bit mask for ADC_INPUT0NEGSEL */
-#define _ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1 << 0) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3 << 0) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5 << 0) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7 << 0) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT2NEGSEL_SHIFT 2 /**< Shift value for ADC_INPUT2NEGSEL */
-#define _ADC_SCANNEGSEL_INPUT2NEGSEL_MASK 0xCUL /**< Bit mask for ADC_INPUT2NEGSEL */
-#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1 << 2) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3 << 2) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5 << 2) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7 << 2) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT4NEGSEL_SHIFT 4 /**< Shift value for ADC_INPUT4NEGSEL */
-#define _ADC_SCANNEGSEL_INPUT4NEGSEL_MASK 0x30UL /**< Bit mask for ADC_INPUT4NEGSEL */
-#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1 << 4) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3 << 4) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5 << 4) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7 << 4) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT6NEGSEL_SHIFT 6 /**< Shift value for ADC_INPUT6NEGSEL */
-#define _ADC_SCANNEGSEL_INPUT6NEGSEL_MASK 0xC0UL /**< Bit mask for ADC_INPUT6NEGSEL */
-#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1 << 6) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3 << 6) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5 << 6) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7 << 6) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT9NEGSEL_SHIFT 8 /**< Shift value for ADC_INPUT9NEGSEL */
-#define _ADC_SCANNEGSEL_INPUT9NEGSEL_MASK 0x300UL /**< Bit mask for ADC_INPUT9NEGSEL */
-#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8 << 8) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10 << 8) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12 << 8) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14 << 8) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT11NEGSEL_SHIFT 10 /**< Shift value for ADC_INPUT11NEGSEL */
-#define _ADC_SCANNEGSEL_INPUT11NEGSEL_MASK 0xC00UL /**< Bit mask for ADC_INPUT11NEGSEL */
-#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8 << 10) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10 << 10) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12 << 10) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14 << 10) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT13NEGSEL_SHIFT 12 /**< Shift value for ADC_INPUT13NEGSEL */
-#define _ADC_SCANNEGSEL_INPUT13NEGSEL_MASK 0x3000UL /**< Bit mask for ADC_INPUT13NEGSEL */
-#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8 << 12) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10 << 12) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12 << 12) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14 << 12) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT15NEGSEL_SHIFT 14 /**< Shift value for ADC_INPUT15NEGSEL */
-#define _ADC_SCANNEGSEL_INPUT15NEGSEL_MASK 0xC000UL /**< Bit mask for ADC_INPUT15NEGSEL */
-#define _ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */
-#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT << 14) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8 << 14) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10 << 14) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12 << 14) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */
-#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14 << 14) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */
-
-/* Bit fields for ADC CMPTHR */
-#define _ADC_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for ADC_CMPTHR */
-#define _ADC_CMPTHR_MASK 0xFFFFFFFFUL /**< Mask for ADC_CMPTHR */
-#define _ADC_CMPTHR_ADLT_SHIFT 0 /**< Shift value for ADC_ADLT */
-#define _ADC_CMPTHR_ADLT_MASK 0xFFFFUL /**< Bit mask for ADC_ADLT */
-#define _ADC_CMPTHR_ADLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMPTHR */
-#define ADC_CMPTHR_ADLT_DEFAULT (_ADC_CMPTHR_ADLT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CMPTHR */
-#define _ADC_CMPTHR_ADGT_SHIFT 16 /**< Shift value for ADC_ADGT */
-#define _ADC_CMPTHR_ADGT_MASK 0xFFFF0000UL /**< Bit mask for ADC_ADGT */
-#define _ADC_CMPTHR_ADGT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMPTHR */
-#define ADC_CMPTHR_ADGT_DEFAULT (_ADC_CMPTHR_ADGT_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CMPTHR */
-
-/* Bit fields for ADC BIASPROG */
-#define _ADC_BIASPROG_RESETVALUE 0x00000000UL /**< Default value for ADC_BIASPROG */
-#define _ADC_BIASPROG_MASK 0x0001100FUL /**< Mask for ADC_BIASPROG */
-#define _ADC_BIASPROG_ADCBIASPROG_SHIFT 0 /**< Shift value for ADC_ADCBIASPROG */
-#define _ADC_BIASPROG_ADCBIASPROG_MASK 0xFUL /**< Bit mask for ADC_ADCBIASPROG */
-#define _ADC_BIASPROG_ADCBIASPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */
-#define _ADC_BIASPROG_ADCBIASPROG_NORMAL 0x00000000UL /**< Mode NORMAL for ADC_BIASPROG */
-#define _ADC_BIASPROG_ADCBIASPROG_SCALE2 0x00000004UL /**< Mode SCALE2 for ADC_BIASPROG */
-#define _ADC_BIASPROG_ADCBIASPROG_SCALE4 0x00000008UL /**< Mode SCALE4 for ADC_BIASPROG */
-#define _ADC_BIASPROG_ADCBIASPROG_SCALE8 0x0000000CUL /**< Mode SCALE8 for ADC_BIASPROG */
-#define _ADC_BIASPROG_ADCBIASPROG_SCALE16 0x0000000EUL /**< Mode SCALE16 for ADC_BIASPROG */
-#define _ADC_BIASPROG_ADCBIASPROG_SCALE32 0x0000000FUL /**< Mode SCALE32 for ADC_BIASPROG */
-#define ADC_BIASPROG_ADCBIASPROG_DEFAULT (_ADC_BIASPROG_ADCBIASPROG_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_BIASPROG */
-#define ADC_BIASPROG_ADCBIASPROG_NORMAL (_ADC_BIASPROG_ADCBIASPROG_NORMAL << 0) /**< Shifted mode NORMAL for ADC_BIASPROG */
-#define ADC_BIASPROG_ADCBIASPROG_SCALE2 (_ADC_BIASPROG_ADCBIASPROG_SCALE2 << 0) /**< Shifted mode SCALE2 for ADC_BIASPROG */
-#define ADC_BIASPROG_ADCBIASPROG_SCALE4 (_ADC_BIASPROG_ADCBIASPROG_SCALE4 << 0) /**< Shifted mode SCALE4 for ADC_BIASPROG */
-#define ADC_BIASPROG_ADCBIASPROG_SCALE8 (_ADC_BIASPROG_ADCBIASPROG_SCALE8 << 0) /**< Shifted mode SCALE8 for ADC_BIASPROG */
-#define ADC_BIASPROG_ADCBIASPROG_SCALE16 (_ADC_BIASPROG_ADCBIASPROG_SCALE16 << 0) /**< Shifted mode SCALE16 for ADC_BIASPROG */
-#define ADC_BIASPROG_ADCBIASPROG_SCALE32 (_ADC_BIASPROG_ADCBIASPROG_SCALE32 << 0) /**< Shifted mode SCALE32 for ADC_BIASPROG */
-#define ADC_BIASPROG_VFAULTCLR (0x1UL << 12) /**< Clear VREFOF Flag */
-#define _ADC_BIASPROG_VFAULTCLR_SHIFT 12 /**< Shift value for ADC_VFAULTCLR */
-#define _ADC_BIASPROG_VFAULTCLR_MASK 0x1000UL /**< Bit mask for ADC_VFAULTCLR */
-#define _ADC_BIASPROG_VFAULTCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */
-#define ADC_BIASPROG_VFAULTCLR_DEFAULT (_ADC_BIASPROG_VFAULTCLR_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_BIASPROG */
-#define ADC_BIASPROG_GPBIASACC (0x1UL << 16) /**< Accuracy Setting for the System Bias During ADC Operation */
-#define _ADC_BIASPROG_GPBIASACC_SHIFT 16 /**< Shift value for ADC_GPBIASACC */
-#define _ADC_BIASPROG_GPBIASACC_MASK 0x10000UL /**< Bit mask for ADC_GPBIASACC */
-#define _ADC_BIASPROG_GPBIASACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */
-#define _ADC_BIASPROG_GPBIASACC_HIGHACC 0x00000000UL /**< Mode HIGHACC for ADC_BIASPROG */
-#define _ADC_BIASPROG_GPBIASACC_LOWACC 0x00000001UL /**< Mode LOWACC for ADC_BIASPROG */
-#define ADC_BIASPROG_GPBIASACC_DEFAULT (_ADC_BIASPROG_GPBIASACC_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_BIASPROG */
-#define ADC_BIASPROG_GPBIASACC_HIGHACC (_ADC_BIASPROG_GPBIASACC_HIGHACC << 16) /**< Shifted mode HIGHACC for ADC_BIASPROG */
-#define ADC_BIASPROG_GPBIASACC_LOWACC (_ADC_BIASPROG_GPBIASACC_LOWACC << 16) /**< Shifted mode LOWACC for ADC_BIASPROG */
-
-/* Bit fields for ADC CAL */
-#define _ADC_CAL_RESETVALUE 0x40784078UL /**< Default value for ADC_CAL */
-#define _ADC_CAL_MASK 0xFFFFFFFFUL /**< Mask for ADC_CAL */
-#define _ADC_CAL_SINGLEOFFSET_SHIFT 0 /**< Shift value for ADC_SINGLEOFFSET */
-#define _ADC_CAL_SINGLEOFFSET_MASK 0xFUL /**< Bit mask for ADC_SINGLEOFFSET */
-#define _ADC_CAL_SINGLEOFFSET_DEFAULT 0x00000008UL /**< Mode DEFAULT for ADC_CAL */
-#define ADC_CAL_SINGLEOFFSET_DEFAULT (_ADC_CAL_SINGLEOFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CAL */
-#define _ADC_CAL_SINGLEOFFSETINV_SHIFT 4 /**< Shift value for ADC_SINGLEOFFSETINV */
-#define _ADC_CAL_SINGLEOFFSETINV_MASK 0xF0UL /**< Bit mask for ADC_SINGLEOFFSETINV */
-#define _ADC_CAL_SINGLEOFFSETINV_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_CAL */
-#define ADC_CAL_SINGLEOFFSETINV_DEFAULT (_ADC_CAL_SINGLEOFFSETINV_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_CAL */
-#define _ADC_CAL_SINGLEGAIN_SHIFT 8 /**< Shift value for ADC_SINGLEGAIN */
-#define _ADC_CAL_SINGLEGAIN_MASK 0x7F00UL /**< Bit mask for ADC_SINGLEGAIN */
-#define _ADC_CAL_SINGLEGAIN_DEFAULT 0x00000040UL /**< Mode DEFAULT for ADC_CAL */
-#define ADC_CAL_SINGLEGAIN_DEFAULT (_ADC_CAL_SINGLEGAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CAL */
-#define ADC_CAL_OFFSETINVMODE (0x1UL << 15) /**< Negative Single-ended Offset Calibration is Enabled */
-#define _ADC_CAL_OFFSETINVMODE_SHIFT 15 /**< Shift value for ADC_OFFSETINVMODE */
-#define _ADC_CAL_OFFSETINVMODE_MASK 0x8000UL /**< Bit mask for ADC_OFFSETINVMODE */
-#define _ADC_CAL_OFFSETINVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */
-#define ADC_CAL_OFFSETINVMODE_DEFAULT (_ADC_CAL_OFFSETINVMODE_DEFAULT << 15) /**< Shifted mode DEFAULT for ADC_CAL */
-#define _ADC_CAL_SCANOFFSET_SHIFT 16 /**< Shift value for ADC_SCANOFFSET */
-#define _ADC_CAL_SCANOFFSET_MASK 0xF0000UL /**< Bit mask for ADC_SCANOFFSET */
-#define _ADC_CAL_SCANOFFSET_DEFAULT 0x00000008UL /**< Mode DEFAULT for ADC_CAL */
-#define ADC_CAL_SCANOFFSET_DEFAULT (_ADC_CAL_SCANOFFSET_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CAL */
-#define _ADC_CAL_SCANOFFSETINV_SHIFT 20 /**< Shift value for ADC_SCANOFFSETINV */
-#define _ADC_CAL_SCANOFFSETINV_MASK 0xF00000UL /**< Bit mask for ADC_SCANOFFSETINV */
-#define _ADC_CAL_SCANOFFSETINV_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_CAL */
-#define ADC_CAL_SCANOFFSETINV_DEFAULT (_ADC_CAL_SCANOFFSETINV_DEFAULT << 20) /**< Shifted mode DEFAULT for ADC_CAL */
-#define _ADC_CAL_SCANGAIN_SHIFT 24 /**< Shift value for ADC_SCANGAIN */
-#define _ADC_CAL_SCANGAIN_MASK 0x7F000000UL /**< Bit mask for ADC_SCANGAIN */
-#define _ADC_CAL_SCANGAIN_DEFAULT 0x00000040UL /**< Mode DEFAULT for ADC_CAL */
-#define ADC_CAL_SCANGAIN_DEFAULT (_ADC_CAL_SCANGAIN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CAL */
-#define ADC_CAL_CALEN (0x1UL << 31) /**< Calibration Mode is Enabled */
-#define _ADC_CAL_CALEN_SHIFT 31 /**< Shift value for ADC_CALEN */
-#define _ADC_CAL_CALEN_MASK 0x80000000UL /**< Bit mask for ADC_CALEN */
-#define _ADC_CAL_CALEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */
-#define ADC_CAL_CALEN_DEFAULT (_ADC_CAL_CALEN_DEFAULT << 31) /**< Shifted mode DEFAULT for ADC_CAL */
-
-/* Bit fields for ADC IF */
-#define _ADC_IF_RESETVALUE 0x00000000UL /**< Default value for ADC_IF */
-#define _ADC_IF_MASK 0x3F030F03UL /**< Mask for ADC_IF */
-#define ADC_IF_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Flag */
-#define _ADC_IF_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */
-#define _ADC_IF_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */
-#define _ADC_IF_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
-#define ADC_IF_SINGLE_DEFAULT (_ADC_IF_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IF */
-#define ADC_IF_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Flag */
-#define _ADC_IF_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */
-#define _ADC_IF_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */
-#define _ADC_IF_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
-#define ADC_IF_SCAN_DEFAULT (_ADC_IF_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IF */
-#define ADC_IF_SINGLEOF (0x1UL << 8) /**< Single FIFO Overflow Interrupt Flag */
-#define _ADC_IF_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
-#define _ADC_IF_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
-#define _ADC_IF_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
-#define ADC_IF_SINGLEOF_DEFAULT (_ADC_IF_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IF */
-#define ADC_IF_SCANOF (0x1UL << 9) /**< Scan FIFO Overflow Interrupt Flag */
-#define _ADC_IF_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
-#define _ADC_IF_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
-#define _ADC_IF_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
-#define ADC_IF_SCANOF_DEFAULT (_ADC_IF_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IF */
-#define ADC_IF_SINGLEUF (0x1UL << 10) /**< Single FIFO Underflow Interrupt Flag */
-#define _ADC_IF_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */
-#define _ADC_IF_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */
-#define _ADC_IF_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
-#define ADC_IF_SINGLEUF_DEFAULT (_ADC_IF_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IF */
-#define ADC_IF_SCANUF (0x1UL << 11) /**< Scan FIFO Underflow Interrupt Flag */
-#define _ADC_IF_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */
-#define _ADC_IF_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */
-#define _ADC_IF_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
-#define ADC_IF_SCANUF_DEFAULT (_ADC_IF_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IF */
-#define ADC_IF_SINGLECMP (0x1UL << 16) /**< Single Result Compare Match Interrupt Flag */
-#define _ADC_IF_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */
-#define _ADC_IF_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */
-#define _ADC_IF_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
-#define ADC_IF_SINGLECMP_DEFAULT (_ADC_IF_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IF */
-#define ADC_IF_SCANCMP (0x1UL << 17) /**< Scan Result Compare Match Interrupt Flag */
-#define _ADC_IF_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */
-#define _ADC_IF_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */
-#define _ADC_IF_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
-#define ADC_IF_SCANCMP_DEFAULT (_ADC_IF_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IF */
-#define ADC_IF_VREFOV (0x1UL << 24) /**< VREF Over Voltage Interrupt Flag */
-#define _ADC_IF_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */
-#define _ADC_IF_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */
-#define _ADC_IF_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
-#define ADC_IF_VREFOV_DEFAULT (_ADC_IF_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IF */
-#define ADC_IF_PROGERR (0x1UL << 25) /**< Programming Error Interrupt Flag */
-#define _ADC_IF_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */
-#define _ADC_IF_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */
-#define _ADC_IF_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
-#define ADC_IF_PROGERR_DEFAULT (_ADC_IF_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IF */
-#define ADC_IF_SCANEXTPEND (0x1UL << 26) /**< External Scan Trigger Pending Flag */
-#define _ADC_IF_SCANEXTPEND_SHIFT 26 /**< Shift value for ADC_SCANEXTPEND */
-#define _ADC_IF_SCANEXTPEND_MASK 0x4000000UL /**< Bit mask for ADC_SCANEXTPEND */
-#define _ADC_IF_SCANEXTPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
-#define ADC_IF_SCANEXTPEND_DEFAULT (_ADC_IF_SCANEXTPEND_DEFAULT << 26) /**< Shifted mode DEFAULT for ADC_IF */
-#define ADC_IF_SCANPEND (0x1UL << 27) /**< Scan Trigger Pending Flag */
-#define _ADC_IF_SCANPEND_SHIFT 27 /**< Shift value for ADC_SCANPEND */
-#define _ADC_IF_SCANPEND_MASK 0x8000000UL /**< Bit mask for ADC_SCANPEND */
-#define _ADC_IF_SCANPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
-#define ADC_IF_SCANPEND_DEFAULT (_ADC_IF_SCANPEND_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_IF */
-#define ADC_IF_PRSTIMEDERR (0x1UL << 28) /**< PRS Timed Mode Error Flag */
-#define _ADC_IF_PRSTIMEDERR_SHIFT 28 /**< Shift value for ADC_PRSTIMEDERR */
-#define _ADC_IF_PRSTIMEDERR_MASK 0x10000000UL /**< Bit mask for ADC_PRSTIMEDERR */
-#define _ADC_IF_PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
-#define ADC_IF_PRSTIMEDERR_DEFAULT (_ADC_IF_PRSTIMEDERR_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_IF */
-#define ADC_IF_EM23ERR (0x1UL << 29) /**< EM23 Entry Error Flag */
-#define _ADC_IF_EM23ERR_SHIFT 29 /**< Shift value for ADC_EM23ERR */
-#define _ADC_IF_EM23ERR_MASK 0x20000000UL /**< Bit mask for ADC_EM23ERR */
-#define _ADC_IF_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
-#define ADC_IF_EM23ERR_DEFAULT (_ADC_IF_EM23ERR_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_IF */
-
-/* Bit fields for ADC IFS */
-#define _ADC_IFS_RESETVALUE 0x00000000UL /**< Default value for ADC_IFS */
-#define _ADC_IFS_MASK 0x3F030F00UL /**< Mask for ADC_IFS */
-#define ADC_IFS_SINGLEOF (0x1UL << 8) /**< Set SINGLEOF Interrupt Flag */
-#define _ADC_IFS_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
-#define _ADC_IFS_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
-#define _ADC_IFS_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
-#define ADC_IFS_SINGLEOF_DEFAULT (_ADC_IFS_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFS */
-#define ADC_IFS_SCANOF (0x1UL << 9) /**< Set SCANOF Interrupt Flag */
-#define _ADC_IFS_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
-#define _ADC_IFS_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
-#define _ADC_IFS_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
-#define ADC_IFS_SCANOF_DEFAULT (_ADC_IFS_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFS */
-#define ADC_IFS_SINGLEUF (0x1UL << 10) /**< Set SINGLEUF Interrupt Flag */
-#define _ADC_IFS_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */
-#define _ADC_IFS_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */
-#define _ADC_IFS_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
-#define ADC_IFS_SINGLEUF_DEFAULT (_ADC_IFS_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IFS */
-#define ADC_IFS_SCANUF (0x1UL << 11) /**< Set SCANUF Interrupt Flag */
-#define _ADC_IFS_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */
-#define _ADC_IFS_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */
-#define _ADC_IFS_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
-#define ADC_IFS_SCANUF_DEFAULT (_ADC_IFS_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IFS */
-#define ADC_IFS_SINGLECMP (0x1UL << 16) /**< Set SINGLECMP Interrupt Flag */
-#define _ADC_IFS_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */
-#define _ADC_IFS_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */
-#define _ADC_IFS_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
-#define ADC_IFS_SINGLECMP_DEFAULT (_ADC_IFS_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IFS */
-#define ADC_IFS_SCANCMP (0x1UL << 17) /**< Set SCANCMP Interrupt Flag */
-#define _ADC_IFS_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */
-#define _ADC_IFS_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */
-#define _ADC_IFS_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
-#define ADC_IFS_SCANCMP_DEFAULT (_ADC_IFS_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IFS */
-#define ADC_IFS_VREFOV (0x1UL << 24) /**< Set VREFOV Interrupt Flag */
-#define _ADC_IFS_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */
-#define _ADC_IFS_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */
-#define _ADC_IFS_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
-#define ADC_IFS_VREFOV_DEFAULT (_ADC_IFS_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IFS */
-#define ADC_IFS_PROGERR (0x1UL << 25) /**< Set PROGERR Interrupt Flag */
-#define _ADC_IFS_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */
-#define _ADC_IFS_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */
-#define _ADC_IFS_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
-#define ADC_IFS_PROGERR_DEFAULT (_ADC_IFS_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IFS */
-#define ADC_IFS_SCANEXTPEND (0x1UL << 26) /**< Set SCANEXTPEND Interrupt Flag */
-#define _ADC_IFS_SCANEXTPEND_SHIFT 26 /**< Shift value for ADC_SCANEXTPEND */
-#define _ADC_IFS_SCANEXTPEND_MASK 0x4000000UL /**< Bit mask for ADC_SCANEXTPEND */
-#define _ADC_IFS_SCANEXTPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
-#define ADC_IFS_SCANEXTPEND_DEFAULT (_ADC_IFS_SCANEXTPEND_DEFAULT << 26) /**< Shifted mode DEFAULT for ADC_IFS */
-#define ADC_IFS_SCANPEND (0x1UL << 27) /**< Set SCANPEND Interrupt Flag */
-#define _ADC_IFS_SCANPEND_SHIFT 27 /**< Shift value for ADC_SCANPEND */
-#define _ADC_IFS_SCANPEND_MASK 0x8000000UL /**< Bit mask for ADC_SCANPEND */
-#define _ADC_IFS_SCANPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
-#define ADC_IFS_SCANPEND_DEFAULT (_ADC_IFS_SCANPEND_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_IFS */
-#define ADC_IFS_PRSTIMEDERR (0x1UL << 28) /**< Set PRSTIMEDERR Interrupt Flag */
-#define _ADC_IFS_PRSTIMEDERR_SHIFT 28 /**< Shift value for ADC_PRSTIMEDERR */
-#define _ADC_IFS_PRSTIMEDERR_MASK 0x10000000UL /**< Bit mask for ADC_PRSTIMEDERR */
-#define _ADC_IFS_PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
-#define ADC_IFS_PRSTIMEDERR_DEFAULT (_ADC_IFS_PRSTIMEDERR_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_IFS */
-#define ADC_IFS_EM23ERR (0x1UL << 29) /**< Set EM23ERR Interrupt Flag */
-#define _ADC_IFS_EM23ERR_SHIFT 29 /**< Shift value for ADC_EM23ERR */
-#define _ADC_IFS_EM23ERR_MASK 0x20000000UL /**< Bit mask for ADC_EM23ERR */
-#define _ADC_IFS_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
-#define ADC_IFS_EM23ERR_DEFAULT (_ADC_IFS_EM23ERR_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_IFS */
-
-/* Bit fields for ADC IFC */
-#define _ADC_IFC_RESETVALUE 0x00000000UL /**< Default value for ADC_IFC */
-#define _ADC_IFC_MASK 0x3F030F00UL /**< Mask for ADC_IFC */
-#define ADC_IFC_SINGLEOF (0x1UL << 8) /**< Clear SINGLEOF Interrupt Flag */
-#define _ADC_IFC_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
-#define _ADC_IFC_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
-#define _ADC_IFC_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
-#define ADC_IFC_SINGLEOF_DEFAULT (_ADC_IFC_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFC */
-#define ADC_IFC_SCANOF (0x1UL << 9) /**< Clear SCANOF Interrupt Flag */
-#define _ADC_IFC_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
-#define _ADC_IFC_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
-#define _ADC_IFC_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
-#define ADC_IFC_SCANOF_DEFAULT (_ADC_IFC_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFC */
-#define ADC_IFC_SINGLEUF (0x1UL << 10) /**< Clear SINGLEUF Interrupt Flag */
-#define _ADC_IFC_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */
-#define _ADC_IFC_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */
-#define _ADC_IFC_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
-#define ADC_IFC_SINGLEUF_DEFAULT (_ADC_IFC_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IFC */
-#define ADC_IFC_SCANUF (0x1UL << 11) /**< Clear SCANUF Interrupt Flag */
-#define _ADC_IFC_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */
-#define _ADC_IFC_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */
-#define _ADC_IFC_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
-#define ADC_IFC_SCANUF_DEFAULT (_ADC_IFC_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IFC */
-#define ADC_IFC_SINGLECMP (0x1UL << 16) /**< Clear SINGLECMP Interrupt Flag */
-#define _ADC_IFC_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */
-#define _ADC_IFC_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */
-#define _ADC_IFC_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
-#define ADC_IFC_SINGLECMP_DEFAULT (_ADC_IFC_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IFC */
-#define ADC_IFC_SCANCMP (0x1UL << 17) /**< Clear SCANCMP Interrupt Flag */
-#define _ADC_IFC_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */
-#define _ADC_IFC_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */
-#define _ADC_IFC_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
-#define ADC_IFC_SCANCMP_DEFAULT (_ADC_IFC_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IFC */
-#define ADC_IFC_VREFOV (0x1UL << 24) /**< Clear VREFOV Interrupt Flag */
-#define _ADC_IFC_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */
-#define _ADC_IFC_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */
-#define _ADC_IFC_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
-#define ADC_IFC_VREFOV_DEFAULT (_ADC_IFC_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IFC */
-#define ADC_IFC_PROGERR (0x1UL << 25) /**< Clear PROGERR Interrupt Flag */
-#define _ADC_IFC_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */
-#define _ADC_IFC_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */
-#define _ADC_IFC_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
-#define ADC_IFC_PROGERR_DEFAULT (_ADC_IFC_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IFC */
-#define ADC_IFC_SCANEXTPEND (0x1UL << 26) /**< Clear SCANEXTPEND Interrupt Flag */
-#define _ADC_IFC_SCANEXTPEND_SHIFT 26 /**< Shift value for ADC_SCANEXTPEND */
-#define _ADC_IFC_SCANEXTPEND_MASK 0x4000000UL /**< Bit mask for ADC_SCANEXTPEND */
-#define _ADC_IFC_SCANEXTPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
-#define ADC_IFC_SCANEXTPEND_DEFAULT (_ADC_IFC_SCANEXTPEND_DEFAULT << 26) /**< Shifted mode DEFAULT for ADC_IFC */
-#define ADC_IFC_SCANPEND (0x1UL << 27) /**< Clear SCANPEND Interrupt Flag */
-#define _ADC_IFC_SCANPEND_SHIFT 27 /**< Shift value for ADC_SCANPEND */
-#define _ADC_IFC_SCANPEND_MASK 0x8000000UL /**< Bit mask for ADC_SCANPEND */
-#define _ADC_IFC_SCANPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
-#define ADC_IFC_SCANPEND_DEFAULT (_ADC_IFC_SCANPEND_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_IFC */
-#define ADC_IFC_PRSTIMEDERR (0x1UL << 28) /**< Clear PRSTIMEDERR Interrupt Flag */
-#define _ADC_IFC_PRSTIMEDERR_SHIFT 28 /**< Shift value for ADC_PRSTIMEDERR */
-#define _ADC_IFC_PRSTIMEDERR_MASK 0x10000000UL /**< Bit mask for ADC_PRSTIMEDERR */
-#define _ADC_IFC_PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
-#define ADC_IFC_PRSTIMEDERR_DEFAULT (_ADC_IFC_PRSTIMEDERR_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_IFC */
-#define ADC_IFC_EM23ERR (0x1UL << 29) /**< Clear EM23ERR Interrupt Flag */
-#define _ADC_IFC_EM23ERR_SHIFT 29 /**< Shift value for ADC_EM23ERR */
-#define _ADC_IFC_EM23ERR_MASK 0x20000000UL /**< Bit mask for ADC_EM23ERR */
-#define _ADC_IFC_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
-#define ADC_IFC_EM23ERR_DEFAULT (_ADC_IFC_EM23ERR_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_IFC */
-
-/* Bit fields for ADC IEN */
-#define _ADC_IEN_RESETVALUE 0x00000000UL /**< Default value for ADC_IEN */
-#define _ADC_IEN_MASK 0x3F030F03UL /**< Mask for ADC_IEN */
-#define ADC_IEN_SINGLE (0x1UL << 0) /**< SINGLE Interrupt Enable */
-#define _ADC_IEN_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */
-#define _ADC_IEN_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */
-#define _ADC_IEN_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
-#define ADC_IEN_SINGLE_DEFAULT (_ADC_IEN_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IEN */
-#define ADC_IEN_SCAN (0x1UL << 1) /**< SCAN Interrupt Enable */
-#define _ADC_IEN_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */
-#define _ADC_IEN_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */
-#define _ADC_IEN_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
-#define ADC_IEN_SCAN_DEFAULT (_ADC_IEN_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IEN */
-#define ADC_IEN_SINGLEOF (0x1UL << 8) /**< SINGLEOF Interrupt Enable */
-#define _ADC_IEN_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
-#define _ADC_IEN_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
-#define _ADC_IEN_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
-#define ADC_IEN_SINGLEOF_DEFAULT (_ADC_IEN_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IEN */
-#define ADC_IEN_SCANOF (0x1UL << 9) /**< SCANOF Interrupt Enable */
-#define _ADC_IEN_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
-#define _ADC_IEN_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
-#define _ADC_IEN_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
-#define ADC_IEN_SCANOF_DEFAULT (_ADC_IEN_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IEN */
-#define ADC_IEN_SINGLEUF (0x1UL << 10) /**< SINGLEUF Interrupt Enable */
-#define _ADC_IEN_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */
-#define _ADC_IEN_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */
-#define _ADC_IEN_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
-#define ADC_IEN_SINGLEUF_DEFAULT (_ADC_IEN_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IEN */
-#define ADC_IEN_SCANUF (0x1UL << 11) /**< SCANUF Interrupt Enable */
-#define _ADC_IEN_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */
-#define _ADC_IEN_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */
-#define _ADC_IEN_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
-#define ADC_IEN_SCANUF_DEFAULT (_ADC_IEN_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IEN */
-#define ADC_IEN_SINGLECMP (0x1UL << 16) /**< SINGLECMP Interrupt Enable */
-#define _ADC_IEN_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */
-#define _ADC_IEN_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */
-#define _ADC_IEN_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
-#define ADC_IEN_SINGLECMP_DEFAULT (_ADC_IEN_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IEN */
-#define ADC_IEN_SCANCMP (0x1UL << 17) /**< SCANCMP Interrupt Enable */
-#define _ADC_IEN_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */
-#define _ADC_IEN_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */
-#define _ADC_IEN_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
-#define ADC_IEN_SCANCMP_DEFAULT (_ADC_IEN_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IEN */
-#define ADC_IEN_VREFOV (0x1UL << 24) /**< VREFOV Interrupt Enable */
-#define _ADC_IEN_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */
-#define _ADC_IEN_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */
-#define _ADC_IEN_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
-#define ADC_IEN_VREFOV_DEFAULT (_ADC_IEN_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IEN */
-#define ADC_IEN_PROGERR (0x1UL << 25) /**< PROGERR Interrupt Enable */
-#define _ADC_IEN_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */
-#define _ADC_IEN_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */
-#define _ADC_IEN_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
-#define ADC_IEN_PROGERR_DEFAULT (_ADC_IEN_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IEN */
-#define ADC_IEN_SCANEXTPEND (0x1UL << 26) /**< SCANEXTPEND Interrupt Enable */
-#define _ADC_IEN_SCANEXTPEND_SHIFT 26 /**< Shift value for ADC_SCANEXTPEND */
-#define _ADC_IEN_SCANEXTPEND_MASK 0x4000000UL /**< Bit mask for ADC_SCANEXTPEND */
-#define _ADC_IEN_SCANEXTPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
-#define ADC_IEN_SCANEXTPEND_DEFAULT (_ADC_IEN_SCANEXTPEND_DEFAULT << 26) /**< Shifted mode DEFAULT for ADC_IEN */
-#define ADC_IEN_SCANPEND (0x1UL << 27) /**< SCANPEND Interrupt Enable */
-#define _ADC_IEN_SCANPEND_SHIFT 27 /**< Shift value for ADC_SCANPEND */
-#define _ADC_IEN_SCANPEND_MASK 0x8000000UL /**< Bit mask for ADC_SCANPEND */
-#define _ADC_IEN_SCANPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
-#define ADC_IEN_SCANPEND_DEFAULT (_ADC_IEN_SCANPEND_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_IEN */
-#define ADC_IEN_PRSTIMEDERR (0x1UL << 28) /**< PRSTIMEDERR Interrupt Enable */
-#define _ADC_IEN_PRSTIMEDERR_SHIFT 28 /**< Shift value for ADC_PRSTIMEDERR */
-#define _ADC_IEN_PRSTIMEDERR_MASK 0x10000000UL /**< Bit mask for ADC_PRSTIMEDERR */
-#define _ADC_IEN_PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
-#define ADC_IEN_PRSTIMEDERR_DEFAULT (_ADC_IEN_PRSTIMEDERR_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_IEN */
-#define ADC_IEN_EM23ERR (0x1UL << 29) /**< EM23ERR Interrupt Enable */
-#define _ADC_IEN_EM23ERR_SHIFT 29 /**< Shift value for ADC_EM23ERR */
-#define _ADC_IEN_EM23ERR_MASK 0x20000000UL /**< Bit mask for ADC_EM23ERR */
-#define _ADC_IEN_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
-#define ADC_IEN_EM23ERR_DEFAULT (_ADC_IEN_EM23ERR_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_IEN */
-
-/* Bit fields for ADC SINGLEDATA */
-#define _ADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATA */
-#define _ADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATA */
-#define _ADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */
-#define _ADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */
-#define _ADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATA */
-#define ADC_SINGLEDATA_DATA_DEFAULT (_ADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATA */
-
-/* Bit fields for ADC SCANDATA */
-#define _ADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATA */
-#define _ADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATA */
-#define _ADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */
-#define _ADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */
-#define _ADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATA */
-#define ADC_SCANDATA_DATA_DEFAULT (_ADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATA */
-
-/* Bit fields for ADC SINGLEDATAP */
-#define _ADC_SINGLEDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATAP */
-#define _ADC_SINGLEDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATAP */
-#define _ADC_SINGLEDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */
-#define _ADC_SINGLEDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */
-#define _ADC_SINGLEDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATAP */
-#define ADC_SINGLEDATAP_DATAP_DEFAULT (_ADC_SINGLEDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATAP */
-
-/* Bit fields for ADC SCANDATAP */
-#define _ADC_SCANDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAP */
-#define _ADC_SCANDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATAP */
-#define _ADC_SCANDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */
-#define _ADC_SCANDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */
-#define _ADC_SCANDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAP */
-#define ADC_SCANDATAP_DATAP_DEFAULT (_ADC_SCANDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAP */
-
-/* Bit fields for ADC SCANDATAX */
-#define _ADC_SCANDATAX_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAX */
-#define _ADC_SCANDATAX_MASK 0x001FFFFFUL /**< Mask for ADC_SCANDATAX */
-#define _ADC_SCANDATAX_DATA_SHIFT 0 /**< Shift value for ADC_DATA */
-#define _ADC_SCANDATAX_DATA_MASK 0xFFFFUL /**< Bit mask for ADC_DATA */
-#define _ADC_SCANDATAX_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAX */
-#define ADC_SCANDATAX_DATA_DEFAULT (_ADC_SCANDATAX_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAX */
-#define _ADC_SCANDATAX_SCANINPUTID_SHIFT 16 /**< Shift value for ADC_SCANINPUTID */
-#define _ADC_SCANDATAX_SCANINPUTID_MASK 0x1F0000UL /**< Bit mask for ADC_SCANINPUTID */
-#define _ADC_SCANDATAX_SCANINPUTID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAX */
-#define ADC_SCANDATAX_SCANINPUTID_DEFAULT (_ADC_SCANDATAX_SCANINPUTID_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANDATAX */
-
-/* Bit fields for ADC SCANDATAXP */
-#define _ADC_SCANDATAXP_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAXP */
-#define _ADC_SCANDATAXP_MASK 0x001FFFFFUL /**< Mask for ADC_SCANDATAXP */
-#define _ADC_SCANDATAXP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */
-#define _ADC_SCANDATAXP_DATAP_MASK 0xFFFFUL /**< Bit mask for ADC_DATAP */
-#define _ADC_SCANDATAXP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAXP */
-#define ADC_SCANDATAXP_DATAP_DEFAULT (_ADC_SCANDATAXP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAXP */
-#define _ADC_SCANDATAXP_SCANINPUTIDPEEK_SHIFT 16 /**< Shift value for ADC_SCANINPUTIDPEEK */
-#define _ADC_SCANDATAXP_SCANINPUTIDPEEK_MASK 0x1F0000UL /**< Bit mask for ADC_SCANINPUTIDPEEK */
-#define _ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAXP */
-#define ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT (_ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANDATAXP */
-
-/* Bit fields for ADC APORTREQ */
-#define _ADC_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTREQ */
-#define _ADC_APORTREQ_MASK 0x000003FFUL /**< Mask for ADC_APORTREQ */
-#define ADC_APORTREQ_APORT0XREQ (0x1UL << 0) /**< 1 If the Bus Connected to APORT0X is Requested */
-#define _ADC_APORTREQ_APORT0XREQ_SHIFT 0 /**< Shift value for ADC_APORT0XREQ */
-#define _ADC_APORTREQ_APORT0XREQ_MASK 0x1UL /**< Bit mask for ADC_APORT0XREQ */
-#define _ADC_APORTREQ_APORT0XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
-#define ADC_APORTREQ_APORT0XREQ_DEFAULT (_ADC_APORTREQ_APORT0XREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_APORTREQ */
-#define ADC_APORTREQ_APORT0YREQ (0x1UL << 1) /**< 1 If the Bus Connected to APORT0Y is Requested */
-#define _ADC_APORTREQ_APORT0YREQ_SHIFT 1 /**< Shift value for ADC_APORT0YREQ */
-#define _ADC_APORTREQ_APORT0YREQ_MASK 0x2UL /**< Bit mask for ADC_APORT0YREQ */
-#define _ADC_APORTREQ_APORT0YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
-#define ADC_APORTREQ_APORT0YREQ_DEFAULT (_ADC_APORTREQ_APORT0YREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_APORTREQ */
-#define ADC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is Requested */
-#define _ADC_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for ADC_APORT1XREQ */
-#define _ADC_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for ADC_APORT1XREQ */
-#define _ADC_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
-#define ADC_APORTREQ_APORT1XREQ_DEFAULT (_ADC_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTREQ */
-#define ADC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is Requested */
-#define _ADC_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for ADC_APORT1YREQ */
-#define _ADC_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for ADC_APORT1YREQ */
-#define _ADC_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
-#define ADC_APORTREQ_APORT1YREQ_DEFAULT (_ADC_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTREQ */
-#define ADC_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is Requested */
-#define _ADC_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for ADC_APORT2XREQ */
-#define _ADC_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for ADC_APORT2XREQ */
-#define _ADC_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
-#define ADC_APORTREQ_APORT2XREQ_DEFAULT (_ADC_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTREQ */
-#define ADC_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is Requested */
-#define _ADC_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for ADC_APORT2YREQ */
-#define _ADC_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for ADC_APORT2YREQ */
-#define _ADC_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
-#define ADC_APORTREQ_APORT2YREQ_DEFAULT (_ADC_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTREQ */
-#define ADC_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is Requested */
-#define _ADC_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for ADC_APORT3XREQ */
-#define _ADC_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for ADC_APORT3XREQ */
-#define _ADC_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
-#define ADC_APORTREQ_APORT3XREQ_DEFAULT (_ADC_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTREQ */
-#define ADC_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is Requested */
-#define _ADC_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for ADC_APORT3YREQ */
-#define _ADC_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for ADC_APORT3YREQ */
-#define _ADC_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
-#define ADC_APORTREQ_APORT3YREQ_DEFAULT (_ADC_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTREQ */
-#define ADC_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is Requested */
-#define _ADC_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for ADC_APORT4XREQ */
-#define _ADC_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for ADC_APORT4XREQ */
-#define _ADC_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
-#define ADC_APORTREQ_APORT4XREQ_DEFAULT (_ADC_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTREQ */
-#define ADC_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is Requested */
-#define _ADC_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for ADC_APORT4YREQ */
-#define _ADC_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for ADC_APORT4YREQ */
-#define _ADC_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
-#define ADC_APORTREQ_APORT4YREQ_DEFAULT (_ADC_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTREQ */
-
-/* Bit fields for ADC APORTCONFLICT */
-#define _ADC_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTCONFLICT */
-#define _ADC_APORTCONFLICT_MASK 0x000003FFUL /**< Mask for ADC_APORTCONFLICT */
-#define ADC_APORTCONFLICT_APORT0XCONFLICT (0x1UL << 0) /**< 1 If the Bus Connected to APORT0X is in Conflict With Another Peripheral */
-#define _ADC_APORTCONFLICT_APORT0XCONFLICT_SHIFT 0 /**< Shift value for ADC_APORT0XCONFLICT */
-#define _ADC_APORTCONFLICT_APORT0XCONFLICT_MASK 0x1UL /**< Bit mask for ADC_APORT0XCONFLICT */
-#define _ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
-#define ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
-#define ADC_APORTCONFLICT_APORT0YCONFLICT (0x1UL << 1) /**< 1 If the Bus Connected to APORT0Y is in Conflict With Another Peripheral */
-#define _ADC_APORTCONFLICT_APORT0YCONFLICT_SHIFT 1 /**< Shift value for ADC_APORT0YCONFLICT */
-#define _ADC_APORTCONFLICT_APORT0YCONFLICT_MASK 0x2UL /**< Bit mask for ADC_APORT0YCONFLICT */
-#define _ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
-#define ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
-#define ADC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */
-#define _ADC_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for ADC_APORT1XCONFLICT */
-#define _ADC_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for ADC_APORT1XCONFLICT */
-#define _ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
-#define ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
-#define ADC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is in Conflict With Another Peripheral */
-#define _ADC_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for ADC_APORT1YCONFLICT */
-#define _ADC_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for ADC_APORT1YCONFLICT */
-#define _ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
-#define ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
-#define ADC_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is in Conflict With Another Peripheral */
-#define _ADC_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for ADC_APORT2XCONFLICT */
-#define _ADC_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for ADC_APORT2XCONFLICT */
-#define _ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
-#define ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
-#define ADC_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is in Conflict With Another Peripheral */
-#define _ADC_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for ADC_APORT2YCONFLICT */
-#define _ADC_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for ADC_APORT2YCONFLICT */
-#define _ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
-#define ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
-#define ADC_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is in Conflict With Another Peripheral */
-#define _ADC_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for ADC_APORT3XCONFLICT */
-#define _ADC_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for ADC_APORT3XCONFLICT */
-#define _ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
-#define ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
-#define ADC_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is in Conflict With Another Peripheral */
-#define _ADC_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for ADC_APORT3YCONFLICT */
-#define _ADC_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for ADC_APORT3YCONFLICT */
-#define _ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
-#define ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
-#define ADC_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is in Conflict With Another Peripheral */
-#define _ADC_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for ADC_APORT4XCONFLICT */
-#define _ADC_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for ADC_APORT4XCONFLICT */
-#define _ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
-#define ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
-#define ADC_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is in Conflict With Another Peripheral */
-#define _ADC_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for ADC_APORT4YCONFLICT */
-#define _ADC_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for ADC_APORT4YCONFLICT */
-#define _ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
-#define ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
-
-/* Bit fields for ADC SINGLEFIFOCOUNT */
-#define _ADC_SINGLEFIFOCOUNT_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEFIFOCOUNT */
-#define _ADC_SINGLEFIFOCOUNT_MASK 0x00000007UL /**< Mask for ADC_SINGLEFIFOCOUNT */
-#define _ADC_SINGLEFIFOCOUNT_SINGLEDC_SHIFT 0 /**< Shift value for ADC_SINGLEDC */
-#define _ADC_SINGLEFIFOCOUNT_SINGLEDC_MASK 0x7UL /**< Bit mask for ADC_SINGLEDC */
-#define _ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEFIFOCOUNT */
-#define ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT (_ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEFIFOCOUNT */
-
-/* Bit fields for ADC SCANFIFOCOUNT */
-#define _ADC_SCANFIFOCOUNT_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANFIFOCOUNT */
-#define _ADC_SCANFIFOCOUNT_MASK 0x00000007UL /**< Mask for ADC_SCANFIFOCOUNT */
-#define _ADC_SCANFIFOCOUNT_SCANDC_SHIFT 0 /**< Shift value for ADC_SCANDC */
-#define _ADC_SCANFIFOCOUNT_SCANDC_MASK 0x7UL /**< Bit mask for ADC_SCANDC */
-#define _ADC_SCANFIFOCOUNT_SCANDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANFIFOCOUNT */
-#define ADC_SCANFIFOCOUNT_SCANDC_DEFAULT (_ADC_SCANFIFOCOUNT_SCANDC_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANFIFOCOUNT */
-
-/* Bit fields for ADC SINGLEFIFOCLEAR */
-#define _ADC_SINGLEFIFOCLEAR_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEFIFOCLEAR */
-#define _ADC_SINGLEFIFOCLEAR_MASK 0x00000001UL /**< Mask for ADC_SINGLEFIFOCLEAR */
-#define ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR (0x1UL << 0) /**< Clear Single FIFO Content */
-#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_SHIFT 0 /**< Shift value for ADC_SINGLEFIFOCLEAR */
-#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_MASK 0x1UL /**< Bit mask for ADC_SINGLEFIFOCLEAR */
-#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEFIFOCLEAR */
-#define ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT (_ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEFIFOCLEAR */
-
-/* Bit fields for ADC SCANFIFOCLEAR */
-#define _ADC_SCANFIFOCLEAR_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANFIFOCLEAR */
-#define _ADC_SCANFIFOCLEAR_MASK 0x00000001UL /**< Mask for ADC_SCANFIFOCLEAR */
-#define ADC_SCANFIFOCLEAR_SCANFIFOCLEAR (0x1UL << 0) /**< Clear Scan FIFO Content */
-#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_SHIFT 0 /**< Shift value for ADC_SCANFIFOCLEAR */
-#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_MASK 0x1UL /**< Bit mask for ADC_SCANFIFOCLEAR */
-#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANFIFOCLEAR */
-#define ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT (_ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANFIFOCLEAR */
-
-/* Bit fields for ADC APORTMASTERDIS */
-#define _ADC_APORTMASTERDIS_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTMASTERDIS */
-#define _ADC_APORTMASTERDIS_MASK 0x000003FCUL /**< Mask for ADC_APORTMASTERDIS */
-#define ADC_APORTMASTERDIS_APORT1XMASTERDIS (0x1UL << 2) /**< APORT1X Master Disable */
-#define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_SHIFT 2 /**< Shift value for ADC_APORT1XMASTERDIS */
-#define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_MASK 0x4UL /**< Bit mask for ADC_APORT1XMASTERDIS */
-#define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */
-#define ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
-#define ADC_APORTMASTERDIS_APORT1YMASTERDIS (0x1UL << 3) /**< APORT1Y Master Disable */
-#define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_SHIFT 3 /**< Shift value for ADC_APORT1YMASTERDIS */
-#define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_MASK 0x8UL /**< Bit mask for ADC_APORT1YMASTERDIS */
-#define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */
-#define ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
-#define ADC_APORTMASTERDIS_APORT2XMASTERDIS (0x1UL << 4) /**< APORT2X Master Disable */
-#define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_SHIFT 4 /**< Shift value for ADC_APORT2XMASTERDIS */
-#define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_MASK 0x10UL /**< Bit mask for ADC_APORT2XMASTERDIS */
-#define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */
-#define ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
-#define ADC_APORTMASTERDIS_APORT2YMASTERDIS (0x1UL << 5) /**< APORT2Y Master Disable */
-#define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_SHIFT 5 /**< Shift value for ADC_APORT2YMASTERDIS */
-#define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_MASK 0x20UL /**< Bit mask for ADC_APORT2YMASTERDIS */
-#define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */
-#define ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
-#define ADC_APORTMASTERDIS_APORT3XMASTERDIS (0x1UL << 6) /**< APORT3X Master Disable */
-#define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_SHIFT 6 /**< Shift value for ADC_APORT3XMASTERDIS */
-#define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_MASK 0x40UL /**< Bit mask for ADC_APORT3XMASTERDIS */
-#define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */
-#define ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
-#define ADC_APORTMASTERDIS_APORT3YMASTERDIS (0x1UL << 7) /**< APORT3Y Master Disable */
-#define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_SHIFT 7 /**< Shift value for ADC_APORT3YMASTERDIS */
-#define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_MASK 0x80UL /**< Bit mask for ADC_APORT3YMASTERDIS */
-#define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */
-#define ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
-#define ADC_APORTMASTERDIS_APORT4XMASTERDIS (0x1UL << 8) /**< APORT4X Master Disable */
-#define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_SHIFT 8 /**< Shift value for ADC_APORT4XMASTERDIS */
-#define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_MASK 0x100UL /**< Bit mask for ADC_APORT4XMASTERDIS */
-#define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */
-#define ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
-#define ADC_APORTMASTERDIS_APORT4YMASTERDIS (0x1UL << 9) /**< APORT4Y Master Disable */
-#define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_SHIFT 9 /**< Shift value for ADC_APORT4YMASTERDIS */
-#define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_MASK 0x200UL /**< Bit mask for ADC_APORT4YMASTERDIS */
-#define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */
-#define ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
-
-/** @} */
-/** @} End of group EFR32FG13P_ADC */
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_cmu.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_cmu.h
deleted file mode 100644
index 43926c89..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_cmu.h
+++ /dev/null
@@ -1,2078 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_cmu.h
- * @brief EFR32FG13P_CMU register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P_CMU CMU
- * @{
- * @brief EFR32FG13P_CMU Register Declaration
- *****************************************************************************/
-/** CMU Register Declaration */
-typedef struct {
- __IOM uint32_t CTRL; /**< CMU Control Register */
-
- uint32_t RESERVED0[3]; /**< Reserved for future use **/
- __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */
-
- uint32_t RESERVED1[1]; /**< Reserved for future use **/
- __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */
-
- uint32_t RESERVED2[1]; /**< Reserved for future use **/
- __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */
- __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */
-
- uint32_t RESERVED3[1]; /**< Reserved for future use **/
- __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */
- __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */
- __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */
- __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */
-
- uint32_t RESERVED4[1]; /**< Reserved for future use **/
- __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */
- __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */
- uint32_t RESERVED5[2]; /**< Reserved for future use **/
- __IOM uint32_t CALCTRL; /**< Calibration Control Register */
- __IOM uint32_t CALCNT; /**< Calibration Counter Register */
- uint32_t RESERVED6[2]; /**< Reserved for future use **/
- __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */
- __IOM uint32_t CMD; /**< Command Register */
- uint32_t RESERVED7[2]; /**< Reserved for future use **/
- __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */
- __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */
- uint32_t RESERVED8[2]; /**< Reserved for future use **/
- __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */
- __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */
- __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */
-
- uint32_t RESERVED9[1]; /**< Reserved for future use **/
- __IM uint32_t STATUS; /**< Status Register */
- __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */
- uint32_t RESERVED10[1]; /**< Reserved for future use **/
- __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */
-
- uint32_t RESERVED11[3]; /**< Reserved for future use **/
- __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */
-
- uint32_t RESERVED12[7]; /**< Reserved for future use **/
- __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */
- uint32_t RESERVED13[1]; /**< Reserved for future use **/
- __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */
-
- uint32_t RESERVED14[1]; /**< Reserved for future use **/
- __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */
- uint32_t RESERVED15[3]; /**< Reserved for future use **/
- __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */
-
- uint32_t RESERVED16[1]; /**< Reserved for future use **/
- __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */
- __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */
-
- uint32_t RESERVED17[1]; /**< Reserved for future use **/
- __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */
-
- uint32_t RESERVED18[2]; /**< Reserved for future use **/
- __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */
- uint32_t RESERVED19[1]; /**< Reserved for future use **/
- __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */
- uint32_t RESERVED20[1]; /**< Reserved for future use **/
- __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */
-
- uint32_t RESERVED21[3]; /**< Reserved for future use **/
- __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
- __IOM uint32_t FREEZE; /**< Freeze Register */
- uint32_t RESERVED22[2]; /**< Reserved for future use **/
- __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */
-
- uint32_t RESERVED23[2]; /**< Reserved for future use **/
- __IOM uint32_t ADCCTRL; /**< ADC Control Register */
-
- uint32_t RESERVED24[4]; /**< Reserved for future use **/
- __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
- __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
- __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */
- uint32_t RESERVED25[1]; /**< Reserved for future use **/
- __IOM uint32_t LOCK; /**< Configuration Lock Register */
- __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */
-} CMU_TypeDef; /** @} */
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_CMU
- * @{
- * @defgroup EFR32FG13P_CMU_BitFields CMU Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for CMU CTRL */
-#define _CMU_CTRL_RESETVALUE 0x00300000UL /**< Default value for CMU_CTRL */
-#define _CMU_CTRL_MASK 0x001103FFUL /**< Mask for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */
-#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */
-#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */
-#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */
-#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */
-#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */
-#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
-#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */
-#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */
-#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */
-#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */
-#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */
-#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */
-
-/* Bit fields for CMU HFRCOCTRL */
-#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */
-#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
-#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
-#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */
-#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */
-#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */
-#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
-#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */
-#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */
-#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
-#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
-#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */
-#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */
-#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
-#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
-#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */
-#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */
-#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */
-#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
-#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
-#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */
-#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */
-#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
-#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */
-#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */
-#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */
-#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
-#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */
-#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */
-#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */
-#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */
-#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */
-#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */
-#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
-#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
-#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */
-#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */
-#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */
-#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
-
-/* Bit fields for CMU AUXHFRCOCTRL */
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */
-#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
-#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */
-#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */
-#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
-#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
-#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */
-#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */
-#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
-#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
-#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */
-#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */
-#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
-#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
-#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */
-#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */
-#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */
-#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
-#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
-#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */
-#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */
-#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
-#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */
-#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */
-#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */
-#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
-#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */
-#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */
-#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */
-#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */
-#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */
-#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */
-#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
-#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
-#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */
-#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */
-#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
-#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
-
-/* Bit fields for CMU LFRCOCTRL */
-#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */
-#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
-#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */
-#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */
-#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */
-#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
-#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
-#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */
-#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */
-#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */
-#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
-#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
-#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */
-#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */
-#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */
-#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
-#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
-#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */
-#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */
-#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
-#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */
-#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */
-#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */
-#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */
-#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
-#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */
-#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */
-#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */
-#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */
-#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */
-#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */
-#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */
-#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
-#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */
-#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */
-#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */
-#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
-#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */
-#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */
-#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */
-#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */
-#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
-#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
-
-/* Bit fields for CMU HFXOCTRL */
-#define _CMU_HFXOCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOCTRL */
-#define _CMU_HFXOCTRL_MASK 0x37000731UL /**< Mask for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_MODE (0x1UL << 0) /**< HFXO Mode */
-#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */
-#define _CMU_HFXOCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */
-#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
-#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */
-#define _CMU_HFXOCTRL_MODE_EXTCLK 0x00000001UL /**< Mode EXTCLK for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_MODE_EXTCLK (_CMU_HFXOCTRL_MODE_EXTCLK << 0) /**< Shifted mode EXTCLK for CMU_HFXOCTRL */
-#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETSHUNTOPTMODE */
-#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETSHUNTOPTMODE */
-#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
-#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD 0x00000000UL /**< Mode AUTOCMD for CMU_HFXOCTRL */
-#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD 0x00000001UL /**< Mode CMD for CMU_HFXOCTRL */
-#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL 0x00000002UL /**< Mode MANUAL for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_LOWPOWER (0x1UL << 8) /**< Low Power Mode Control */
-#define _CMU_HFXOCTRL_LOWPOWER_SHIFT 8 /**< Shift value for CMU_LOWPOWER */
-#define _CMU_HFXOCTRL_LOWPOWER_MASK 0x100UL /**< Bit mask for CMU_LOWPOWER */
-#define _CMU_HFXOCTRL_LOWPOWER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_LOWPOWER_DEFAULT (_CMU_HFXOCTRL_LOWPOWER_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_XTI2GND (0x1UL << 9) /**< Clamp HFXTAL_N Pin to Ground When HFXO Oscillator is Off */
-#define _CMU_HFXOCTRL_XTI2GND_SHIFT 9 /**< Shift value for CMU_XTI2GND */
-#define _CMU_HFXOCTRL_XTI2GND_MASK 0x200UL /**< Bit mask for CMU_XTI2GND */
-#define _CMU_HFXOCTRL_XTI2GND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_XTI2GND_DEFAULT (_CMU_HFXOCTRL_XTI2GND_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_XTO2GND (0x1UL << 10) /**< Clamp HFXTAL_P Pin to Ground When HFXO Oscillator is Off */
-#define _CMU_HFXOCTRL_XTO2GND_SHIFT 10 /**< Shift value for CMU_XTO2GND */
-#define _CMU_HFXOCTRL_XTO2GND_MASK 0x400UL /**< Bit mask for CMU_XTO2GND */
-#define _CMU_HFXOCTRL_XTO2GND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_XTO2GND_DEFAULT (_CMU_HFXOCTRL_XTO2GND_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
-#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */
-#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */
-#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
-#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */
-#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */
-#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */
-#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */
-#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */
-#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */
-#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */
-#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */
-#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */
-#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */
-#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */
-#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */
-#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */
-#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */
-#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
-
-/* Bit fields for CMU HFXOSTARTUPCTRL */
-#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00050020UL /**< Default value for CMU_HFXOSTARTUPCTRL */
-#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FF87FUL /**< Mask for CMU_HFXOSTARTUPCTRL */
-#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */
-#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */
-#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000020UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */
-#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */
-#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */
-#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */
-#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x000000A0UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */
-#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */
-
-/* Bit fields for CMU HFXOSTEADYSTATECTRL */
-#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0xA30B4507UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */
-#define _CMU_HFXOSTEADYSTATECTRL_MASK 0xF70FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */
-#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */
-#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */
-#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
-#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
-#define _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT 7 /**< Shift value for CMU_REGISH */
-#define _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK 0x780UL /**< Bit mask for CMU_REGISH */
-#define _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
-#define CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
-#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */
-#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */
-#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000168UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
-#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
-#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_SHIFT 24 /**< Shift value for CMU_REGSELILOW */
-#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_MASK 0x3000000UL /**< Bit mask for CMU_REGSELILOW */
-#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
-#define CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
-#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */
-#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */
-#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */
-#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
-#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
-#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT 28 /**< Shift value for CMU_REGISHUPPER */
-#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK 0xF0000000UL /**< Bit mask for CMU_REGISHUPPER */
-#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
-#define CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
-
-/* Bit fields for CMU HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0002A067UL /**< Default value for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_MASK 0x000FF0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */
-#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */
-#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */
-#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */
-#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000006UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */
-#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */
-#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT 16 /**< Shift value for CMU_SHUNTOPTTIMEOUT */
-#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_MASK 0xF0000UL /**< Bit mask for CMU_SHUNTOPTTIMEOUT */
-#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES << 16) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES << 16) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES << 16) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES << 16) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES << 16) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES << 16) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES << 16) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES << 16) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES << 16) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES << 16) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
-#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES << 16) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
-
-/* Bit fields for CMU LFXOCTRL */
-#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */
-#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */
-#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
-#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */
-#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */
-#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
-#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */
-#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */
-#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */
-#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */
-#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */
-#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */
-#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
-#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */
-#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */
-#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */
-#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */
-#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */
-#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */
-#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
-#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */
-#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */
-#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */
-#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */
-#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
-#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */
-#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */
-#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */
-#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */
-#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
-#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */
-#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */
-#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */
-#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
-#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */
-#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */
-#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */
-#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */
-#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
-#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */
-#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */
-#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */
-#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */
-#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */
-#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */
-#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */
-#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */
-#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */
-#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */
-#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */
-#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */
-#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */
-#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */
-#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */
-#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */
-#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */
-#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */
-#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
-#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */
-
-/* Bit fields for CMU DPLLCTRL */
-#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */
-#define _CMU_DPLLCTRL_MASK 0x0000001FUL /**< Mask for CMU_DPLLCTRL */
-#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */
-#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */
-#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */
-#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */
-#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */
-#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */
-#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */
-#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */
-#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */
-#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */
-#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */
-#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */
-#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */
-#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */
-#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */
-#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */
-#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */
-#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */
-#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */
-#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */
-#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */
-#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */
-#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */
-#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */
-#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */
-#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */
-#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */
-#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */
-#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */
-#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */
-#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */
-#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */
-#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */
-
-/* Bit fields for CMU DPLLCTRL1 */
-#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */
-#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */
-#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */
-#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */
-#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */
-#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */
-#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */
-#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */
-#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */
-#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */
-
-/* Bit fields for CMU CALCTRL */
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */
-#define _CMU_CALCTRL_MASK 0x0F0F01FFUL /**< Mask for CMU_CALCTRL */
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */
-#define _CMU_CALCTRL_UPSEL_MASK 0xFUL /**< Bit mask for CMU_UPSEL */
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */
-#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
-#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */
-#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */
-#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
-#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */
-#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */
-#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */
-#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */
-#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */
-#define _CMU_CALCTRL_PRSUPSEL_MASK 0xF0000UL /**< Bit mask for CMU_PRSUPSEL */
-#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
-#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */
-#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */
-#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */
-#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */
-#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */
-#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */
-#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */
-#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */
-#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */
-#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */
-#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */
-#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */
-#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */
-#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */
-#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */
-#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */
-#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */
-#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */
-#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */
-#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */
-#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */
-#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */
-#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */
-#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */
-#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */
-#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */
-#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0xF000000UL /**< Bit mask for CMU_PRSDOWNSEL */
-#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
-#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */
-#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */
-#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */
-#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */
-#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */
-#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */
-#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */
-#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */
-#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */
-#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */
-#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */
-#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */
-#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */
-#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */
-#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */
-#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */
-#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */
-#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */
-#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */
-#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */
-#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */
-#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */
-#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */
-#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */
-#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */
-
-/* Bit fields for CMU CALCNT */
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */
-
-/* Bit fields for CMU OSCENCMD */
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */
-#define _CMU_OSCENCMD_MASK 0x000033FFUL /**< Mask for CMU_OSCENCMD */
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */
-#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */
-#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */
-#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */
-#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */
-#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */
-#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
-#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
-
-/* Bit fields for CMU CMD */
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */
-#define _CMU_CMD_MASK 0x00000033UL /**< Mask for CMU_CMD */
-#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */
-#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */
-#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */
-#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */
-#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */
-#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */
-#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */
-#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */
-#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */
-#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
-#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */
-#define CMU_CMD_HFXOSHUNTOPTSTART (0x1UL << 5) /**< HFXO Shunt Current Optimization Start */
-#define _CMU_CMD_HFXOSHUNTOPTSTART_SHIFT 5 /**< Shift value for CMU_HFXOSHUNTOPTSTART */
-#define _CMU_CMD_HFXOSHUNTOPTSTART_MASK 0x20UL /**< Bit mask for CMU_HFXOSHUNTOPTSTART */
-#define _CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
-#define CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT (_CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */
-
-/* Bit fields for CMU DBGCLKSEL */
-#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */
-#define _CMU_DBGCLKSEL_MASK 0x00000001UL /**< Mask for CMU_DBGCLKSEL */
-#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */
-#define _CMU_DBGCLKSEL_DBG_MASK 0x1UL /**< Bit mask for CMU_DBG */
-#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */
-#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */
-#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */
-#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */
-#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */
-#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */
-
-/* Bit fields for CMU HFCLKSEL */
-#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */
-#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */
-#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */
-#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */
-#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */
-#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */
-#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */
-#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */
-#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */
-#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */
-#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */
-#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */
-#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */
-#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */
-#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */
-#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */
-#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */
-#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */
-
-/* Bit fields for CMU LFACLKSEL */
-#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */
-#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */
-#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */
-#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */
-#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */
-#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */
-#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */
-#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */
-#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */
-#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */
-#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */
-#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */
-#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */
-#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */
-
-/* Bit fields for CMU LFBCLKSEL */
-#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */
-#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */
-#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */
-#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */
-#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */
-#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */
-#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */
-#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */
-#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */
-#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */
-#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */
-#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */
-#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */
-#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */
-#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */
-#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */
-
-/* Bit fields for CMU LFECLKSEL */
-#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */
-#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */
-#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */
-#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */
-#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */
-#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */
-#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */
-#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */
-#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */
-#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */
-#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */
-#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */
-#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */
-#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */
-
-/* Bit fields for CMU STATUS */
-#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */
-#define _CMU_STATUS_MASK 0x3FE133FFUL /**< Mask for CMU_STATUS */
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */
-#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */
-#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */
-#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */
-#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */
-#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */
-#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */
-#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */
-#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */
-#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFXOREQ (0x1UL << 21) /**< HFXO is Required By Hardware */
-#define _CMU_STATUS_HFXOREQ_SHIFT 21 /**< Shift value for CMU_HFXOREQ */
-#define _CMU_STATUS_HFXOREQ_MASK 0x200000UL /**< Bit mask for CMU_HFXOREQ */
-#define _CMU_STATUS_HFXOREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFXOREQ_DEFAULT (_CMU_STATUS_HFXOREQ_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */
-#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */
-#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */
-#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFXOSHUNTOPTRDY (0x1UL << 23) /**< HFXO Shunt Current Optimization Ready */
-#define _CMU_STATUS_HFXOSHUNTOPTRDY_SHIFT 23 /**< Shift value for CMU_HFXOSHUNTOPTRDY */
-#define _CMU_STATUS_HFXOSHUNTOPTRDY_MASK 0x800000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */
-#define _CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT (_CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFXOAMPHIGH (0x1UL << 24) /**< HFXO Oscillation Amplitude is Too High */
-#define _CMU_STATUS_HFXOAMPHIGH_SHIFT 24 /**< Shift value for CMU_HFXOAMPHIGH */
-#define _CMU_STATUS_HFXOAMPHIGH_MASK 0x1000000UL /**< Bit mask for CMU_HFXOAMPHIGH */
-#define _CMU_STATUS_HFXOAMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFXOAMPHIGH_DEFAULT (_CMU_STATUS_HFXOAMPHIGH_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */
-#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */
-#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */
-#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFXOREGILOW (0x1UL << 26) /**< HFXO Regulator Shunt Current Too Low */
-#define _CMU_STATUS_HFXOREGILOW_SHIFT 26 /**< Shift value for CMU_HFXOREGILOW */
-#define _CMU_STATUS_HFXOREGILOW_MASK 0x4000000UL /**< Bit mask for CMU_HFXOREGILOW */
-#define _CMU_STATUS_HFXOREGILOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_HFXOREGILOW_DEFAULT (_CMU_STATUS_HFXOREGILOW_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */
-#define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */
-#define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */
-#define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */
-#define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */
-#define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */
-#define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */
-#define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */
-#define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */
-#define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
-#define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */
-
-/* Bit fields for CMU HFCLKSTATUS */
-#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */
-#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */
-#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */
-#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */
-#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */
-#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */
-#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */
-#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */
-#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */
-#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */
-#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */
-#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */
-#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */
-#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */
-#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */
-#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */
-#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */
-#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */
-
-/* Bit fields for CMU HFXOTRIMSTATUS */
-#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000500UL /**< Default value for CMU_HFXOTRIMSTATUS */
-#define _CMU_HFXOTRIMSTATUS_MASK 0x000007FFUL /**< Mask for CMU_HFXOTRIMSTATUS */
-#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */
-#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */
-#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */
-#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */
-#define _CMU_HFXOTRIMSTATUS_REGISH_SHIFT 7 /**< Shift value for CMU_REGISH */
-#define _CMU_HFXOTRIMSTATUS_REGISH_MASK 0x780UL /**< Bit mask for CMU_REGISH */
-#define _CMU_HFXOTRIMSTATUS_REGISH_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */
-#define CMU_HFXOTRIMSTATUS_REGISH_DEFAULT (_CMU_HFXOTRIMSTATUS_REGISH_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */
-
-/* Bit fields for CMU IF */
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */
-#define _CMU_IF_MASK 0xB803FF7FUL /**< Mask for CMU_IF */
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */
-#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */
-#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */
-#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */
-#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
-#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */
-#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */
-#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */
-#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */
-#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
-#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */
-#define CMU_IF_HFXOPEAKDETERR (0x1UL << 10) /**< HFXO Automatic Peak Detection Error Interrupt Flag */
-#define _CMU_IF_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */
-#define _CMU_IF_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */
-#define _CMU_IF_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
-#define CMU_IF_HFXOPEAKDETERR_DEFAULT (_CMU_IF_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IF */
-#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */
-#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */
-#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */
-#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
-#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */
-#define CMU_IF_HFXOSHUNTOPTRDY (0x1UL << 12) /**< HFXO Automatic Shunt Current Optimization Ready Interrupt Flag */
-#define _CMU_IF_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */
-#define _CMU_IF_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */
-#define _CMU_IF_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
-#define CMU_IF_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IF_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IF */
-#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */
-#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */
-#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */
-#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
-#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */
-#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */
-#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */
-#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */
-#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
-#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */
-#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */
-#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */
-#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */
-#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
-#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */
-#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */
-#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */
-#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */
-#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
-#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */
-#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */
-#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */
-#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */
-#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
-#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */
-#define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */
-#define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */
-#define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */
-#define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
-#define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */
-#define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */
-#define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */
-#define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */
-#define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
-#define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */
-#define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */
-#define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */
-#define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */
-#define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
-#define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */
-#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */
-#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */
-#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */
-#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
-#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */
-
-/* Bit fields for CMU IFS */
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */
-#define _CMU_IFS_MASK 0xB803FF7FUL /**< Mask for CMU_IFS */
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */
-#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */
-#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */
-#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */
-#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
-#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */
-#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */
-#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */
-#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */
-#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
-#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */
-#define CMU_IFS_HFXOPEAKDETERR (0x1UL << 10) /**< Set HFXOPEAKDETERR Interrupt Flag */
-#define _CMU_IFS_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */
-#define _CMU_IFS_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */
-#define _CMU_IFS_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
-#define CMU_IFS_HFXOPEAKDETERR_DEFAULT (_CMU_IFS_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IFS */
-#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */
-#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */
-#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */
-#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
-#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */
-#define CMU_IFS_HFXOSHUNTOPTRDY (0x1UL << 12) /**< Set HFXOSHUNTOPTRDY Interrupt Flag */
-#define _CMU_IFS_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */
-#define _CMU_IFS_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */
-#define _CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
-#define CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IFS */
-#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */
-#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */
-#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */
-#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
-#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */
-#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */
-#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */
-#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */
-#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
-#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */
-#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */
-#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */
-#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */
-#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
-#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */
-#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */
-#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */
-#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */
-#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
-#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */
-#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */
-#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */
-#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */
-#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
-#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */
-#define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */
-#define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */
-#define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */
-#define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
-#define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */
-#define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */
-#define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */
-#define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */
-#define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
-#define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */
-#define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */
-#define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */
-#define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */
-#define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
-#define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */
-#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */
-#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */
-#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */
-#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
-#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */
-
-/* Bit fields for CMU IFC */
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */
-#define _CMU_IFC_MASK 0xB803FF7FUL /**< Mask for CMU_IFC */
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */
-#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */
-#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */
-#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */
-#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
-#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */
-#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */
-#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */
-#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */
-#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
-#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */
-#define CMU_IFC_HFXOPEAKDETERR (0x1UL << 10) /**< Clear HFXOPEAKDETERR Interrupt Flag */
-#define _CMU_IFC_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */
-#define _CMU_IFC_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */
-#define _CMU_IFC_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
-#define CMU_IFC_HFXOPEAKDETERR_DEFAULT (_CMU_IFC_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IFC */
-#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */
-#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */
-#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */
-#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
-#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */
-#define CMU_IFC_HFXOSHUNTOPTRDY (0x1UL << 12) /**< Clear HFXOSHUNTOPTRDY Interrupt Flag */
-#define _CMU_IFC_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */
-#define _CMU_IFC_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */
-#define _CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
-#define CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IFC */
-#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */
-#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */
-#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */
-#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
-#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */
-#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */
-#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */
-#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */
-#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
-#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */
-#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */
-#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */
-#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */
-#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
-#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */
-#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */
-#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */
-#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */
-#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
-#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */
-#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */
-#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */
-#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */
-#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
-#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */
-#define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */
-#define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */
-#define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */
-#define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
-#define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */
-#define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */
-#define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */
-#define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */
-#define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
-#define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */
-#define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */
-#define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */
-#define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */
-#define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
-#define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */
-#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */
-#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */
-#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */
-#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
-#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */
-
-/* Bit fields for CMU IEN */
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */
-#define _CMU_IEN_MASK 0xB803FF7FUL /**< Mask for CMU_IEN */
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */
-#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */
-#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */
-#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */
-#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */
-#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
-#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */
-#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */
-#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */
-#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */
-#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
-#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */
-#define CMU_IEN_HFXOPEAKDETERR (0x1UL << 10) /**< HFXOPEAKDETERR Interrupt Enable */
-#define _CMU_IEN_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */
-#define _CMU_IEN_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */
-#define _CMU_IEN_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
-#define CMU_IEN_HFXOPEAKDETERR_DEFAULT (_CMU_IEN_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IEN */
-#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */
-#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */
-#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */
-#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
-#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */
-#define CMU_IEN_HFXOSHUNTOPTRDY (0x1UL << 12) /**< HFXOSHUNTOPTRDY Interrupt Enable */
-#define _CMU_IEN_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */
-#define _CMU_IEN_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */
-#define _CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
-#define CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IEN */
-#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */
-#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */
-#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */
-#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
-#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */
-#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */
-#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */
-#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */
-#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
-#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */
-#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */
-#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */
-#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */
-#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
-#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */
-#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */
-#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */
-#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */
-#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
-#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */
-#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */
-#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */
-#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */
-#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
-#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */
-#define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */
-#define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */
-#define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */
-#define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
-#define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */
-#define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */
-#define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */
-#define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */
-#define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
-#define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */
-#define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */
-#define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */
-#define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */
-#define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
-#define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */
-#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */
-#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */
-#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */
-#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
-#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */
-
-/* Bit fields for CMU HFBUSCLKEN0 */
-#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */
-#define _CMU_HFBUSCLKEN0_MASK 0x0000007FUL /**< Mask for CMU_HFBUSCLKEN0 */
-#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 0) /**< Advanced Encryption Standard Accelerator 0 Clock Enable */
-#define CMU_HFBUSCLKEN0_CRYPTO CMU_HFBUSCLKEN0_CRYPTO0 /**< Alias for CRYPTO0 */
-#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 0 /**< Shift value for CMU_CRYPTO0 */
-#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x1UL /**< Bit mask for CMU_CRYPTO0 */
-#define _CMU_HFBUSCLKEN0_CRYPTO_SHIFT _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT /**< Alias for CMU_CRYPTO0 */
-#define _CMU_HFBUSCLKEN0_CRYPTO_MASK _CMU_HFBUSCLKEN0_CRYPTO0_MASK /**< Alias for CMU_CRYPTO0 */
-#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
-#define _CMU_HFBUSCLKEN0_CRYPTO_DEFAULT _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT /**< Alias for CRYPTO0 mode DEFAULT */
-#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
-#define CMU_HFBUSCLKEN0_CRYPTO_DEFAULT CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT /**< Alias for CRYPTO0 mode DEFAULT*/
-#define CMU_HFBUSCLKEN0_CRYPTO1 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator 1 Clock Enable */
-#define _CMU_HFBUSCLKEN0_CRYPTO1_SHIFT 1 /**< Shift value for CMU_CRYPTO1 */
-#define _CMU_HFBUSCLKEN0_CRYPTO1_MASK 0x2UL /**< Bit mask for CMU_CRYPTO1 */
-#define _CMU_HFBUSCLKEN0_CRYPTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
-#define CMU_HFBUSCLKEN0_CRYPTO1_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
-#define CMU_HFBUSCLKEN0_LE (0x1UL << 2) /**< Low Energy Peripheral Interface Clock Enable */
-#define _CMU_HFBUSCLKEN0_LE_SHIFT 2 /**< Shift value for CMU_LE */
-#define _CMU_HFBUSCLKEN0_LE_MASK 0x4UL /**< Bit mask for CMU_LE */
-#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
-#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
-#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 3) /**< General purpose Input/Output Clock Enable */
-#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 3 /**< Shift value for CMU_GPIO */
-#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x8UL /**< Bit mask for CMU_GPIO */
-#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
-#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
-#define CMU_HFBUSCLKEN0_PRS (0x1UL << 4) /**< Peripheral Reflex System Clock Enable */
-#define _CMU_HFBUSCLKEN0_PRS_SHIFT 4 /**< Shift value for CMU_PRS */
-#define _CMU_HFBUSCLKEN0_PRS_MASK 0x10UL /**< Bit mask for CMU_PRS */
-#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
-#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
-#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 5) /**< Linked Direct Memory Access Controller Clock Enable */
-#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 5 /**< Shift value for CMU_LDMA */
-#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x20UL /**< Bit mask for CMU_LDMA */
-#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
-#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
-#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 6) /**< General Purpose CRC Clock Enable */
-#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 6 /**< Shift value for CMU_GPCRC */
-#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x40UL /**< Bit mask for CMU_GPCRC */
-#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
-#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
-
-/* Bit fields for CMU HFPERCLKEN0 */
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */
-#define _CMU_HFPERCLKEN0_MASK 0x0000FFFFUL /**< Mask for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_WTIMER0 (0x1UL << 2) /**< Wide Timer 0 Clock Enable */
-#define _CMU_HFPERCLKEN0_WTIMER0_SHIFT 2 /**< Shift value for CMU_WTIMER0 */
-#define _CMU_HFPERCLKEN0_WTIMER0_MASK 0x4UL /**< Bit mask for CMU_WTIMER0 */
-#define _CMU_HFPERCLKEN0_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_WTIMER0_DEFAULT (_CMU_HFPERCLKEN0_WTIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 3) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 3 /**< Shift value for CMU_USART0 */
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x8UL /**< Bit mask for CMU_USART0 */
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 4) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 4 /**< Shift value for CMU_USART1 */
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x10UL /**< Bit mask for CMU_USART1 */
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 5) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 5 /**< Shift value for CMU_USART2 */
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x20UL /**< Bit mask for CMU_USART2 */
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 6) /**< I2C 0 Clock Enable */
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 6 /**< Shift value for CMU_I2C0 */
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x40UL /**< Bit mask for CMU_I2C0 */
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 7) /**< I2C 1 Clock Enable */
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 7 /**< Shift value for CMU_I2C1 */
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x80UL /**< Bit mask for CMU_I2C1 */
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 8) /**< Analog Comparator 0 Clock Enable */
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 8 /**< Shift value for CMU_ACMP0 */
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x100UL /**< Bit mask for CMU_ACMP0 */
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 9) /**< Analog Comparator 1 Clock Enable */
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 9 /**< Shift value for CMU_ACMP1 */
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x200UL /**< Bit mask for CMU_ACMP1 */
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 10) /**< CryoTimer Clock Enable */
-#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 10 /**< Shift value for CMU_CRYOTIMER */
-#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400UL /**< Bit mask for CMU_CRYOTIMER */
-#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 11) /**< Analog to Digital Converter 0 Clock Enable */
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 11 /**< Shift value for CMU_ADC0 */
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x800UL /**< Bit mask for CMU_ADC0 */
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 Clock Enable */
-#define _CMU_HFPERCLKEN0_VDAC0_SHIFT 12 /**< Shift value for CMU_VDAC0 */
-#define _CMU_HFPERCLKEN0_VDAC0_MASK 0x1000UL /**< Bit mask for CMU_VDAC0 */
-#define _CMU_HFPERCLKEN0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_VDAC0_DEFAULT (_CMU_HFPERCLKEN0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_CSEN (0x1UL << 13) /**< Capacitive touch sense module Clock Enable */
-#define _CMU_HFPERCLKEN0_CSEN_SHIFT 13 /**< Shift value for CMU_CSEN */
-#define _CMU_HFPERCLKEN0_CSEN_MASK 0x2000UL /**< Bit mask for CMU_CSEN */
-#define _CMU_HFPERCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_CSEN_DEFAULT (_CMU_HFPERCLKEN0_CSEN_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 14) /**< Current Digital to Analog Converter 0 Clock Enable */
-#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 14 /**< Shift value for CMU_IDAC0 */
-#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x4000UL /**< Bit mask for CMU_IDAC0 */
-#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 15) /**< True Random Number Generator 0 Clock Enable */
-#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 15 /**< Shift value for CMU_TRNG0 */
-#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x8000UL /**< Bit mask for CMU_TRNG0 */
-#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
-#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
-
-/* Bit fields for CMU LFACLKEN0 */
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */
-#define _CMU_LFACLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFACLKEN0 */
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 1) /**< Low Energy Sensor Interface Clock Enable */
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 1 /**< Shift value for CMU_LESENSE */
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x2UL /**< Bit mask for CMU_LESENSE */
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
-
-/* Bit fields for CMU LFBCLKEN0 */
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */
-#define _CMU_LFBCLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFBCLKEN0 */
-#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 0) /**< Clock Enable */
-#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 0 /**< Shift value for CMU_SYSTICK */
-#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x1UL /**< Bit mask for CMU_SYSTICK */
-#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */
-#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 1) /**< Low Energy UART 0 Clock Enable */
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 1 /**< Shift value for CMU_LEUART0 */
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x2UL /**< Bit mask for CMU_LEUART0 */
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */
-#define CMU_LFBCLKEN0_CSEN (0x1UL << 2) /**< Capacitive touch sense module Clock Enable */
-#define _CMU_LFBCLKEN0_CSEN_SHIFT 2 /**< Shift value for CMU_CSEN */
-#define _CMU_LFBCLKEN0_CSEN_MASK 0x4UL /**< Bit mask for CMU_CSEN */
-#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */
-#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */
-
-/* Bit fields for CMU LFECLKEN0 */
-#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */
-#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */
-#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */
-#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */
-#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */
-#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */
-#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */
-
-/* Bit fields for CMU HFPRESC */
-#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */
-#define _CMU_HFPRESC_MASK 0x01001F00UL /**< Mask for CMU_HFPRESC */
-#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */
-#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */
-#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */
-#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */
-#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */
-#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */
-#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */
-#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x1000000UL /**< Bit mask for CMU_HFCLKLEPRESC */
-#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */
-#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */
-#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */
-#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */
-#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */
-#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */
-
-/* Bit fields for CMU HFCOREPRESC */
-#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */
-#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */
-#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */
-#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */
-#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */
-#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */
-#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */
-#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */
-
-/* Bit fields for CMU HFPERPRESC */
-#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */
-#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */
-#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */
-#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */
-#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */
-#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */
-#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */
-#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */
-
-/* Bit fields for CMU HFEXPPRESC */
-#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */
-#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */
-#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */
-#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */
-#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */
-#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */
-#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */
-#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */
-
-/* Bit fields for CMU LFAPRESC0 */
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_MASK 0x0000003FUL /**< Mask for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 4 /**< Shift value for CMU_LESENSE */
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x30UL /**< Bit mask for CMU_LESENSE */
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
-
-/* Bit fields for CMU LFBPRESC0 */
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */
-#define _CMU_LFBPRESC0_MASK 0x0000033FUL /**< Mask for CMU_LFBPRESC0 */
-#define _CMU_LFBPRESC0_SYSTICK_SHIFT 0 /**< Shift value for CMU_SYSTICK */
-#define _CMU_LFBPRESC0_SYSTICK_MASK 0xFUL /**< Bit mask for CMU_SYSTICK */
-#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */
-#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 4 /**< Shift value for CMU_LEUART0 */
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x30UL /**< Bit mask for CMU_LEUART0 */
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */
-#define _CMU_LFBPRESC0_CSEN_SHIFT 8 /**< Shift value for CMU_CSEN */
-#define _CMU_LFBPRESC0_CSEN_MASK 0x300UL /**< Bit mask for CMU_CSEN */
-#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */
-#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */
-#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */
-#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */
-#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */
-#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */
-#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */
-#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */
-
-/* Bit fields for CMU LFEPRESC0 */
-#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */
-#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */
-#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */
-#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */
-#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */
-#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */
-#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */
-#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */
-#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */
-#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */
-
-/* Bit fields for CMU SYNCBUSY */
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */
-#define _CMU_SYNCBUSY_MASK 0x3F050055UL /**< Mask for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */
-#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */
-#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */
-#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */
-#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */
-#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */
-#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */
-#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */
-#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */
-#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */
-#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */
-#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */
-#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */
-#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */
-#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */
-#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */
-#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */
-#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */
-#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */
-#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */
-#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */
-#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */
-#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */
-#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */
-#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
-#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
-
-/* Bit fields for CMU FREEZE */
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */
-
-/* Bit fields for CMU PCNTCTRL */
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */
-#define _CMU_PCNTCTRL_MASK 0x00000003UL /**< Mask for CMU_PCNTCTRL */
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */
-
-/* Bit fields for CMU ADCCTRL */
-#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */
-#define _CMU_ADCCTRL_MASK 0x00000130UL /**< Mask for CMU_ADCCTRL */
-#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */
-#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */
-#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */
-#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */
-#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */
-#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */
-#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */
-#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */
-#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */
-#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */
-#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */
-#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */
-#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */
-#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */
-#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */
-#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */
-#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */
-
-/* Bit fields for CMU ROUTEPEN */
-#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */
-#define _CMU_ROUTEPEN_MASK 0x10000003UL /**< Mask for CMU_ROUTEPEN */
-#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */
-#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */
-#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */
-#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */
-#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */
-#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */
-#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */
-#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */
-#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */
-#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */
-#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */
-#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */
-#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */
-#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */
-#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */
-
-/* Bit fields for CMU ROUTELOC0 */
-#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */
-#define _CMU_ROUTELOC0_MASK 0x00000707UL /**< Mask for CMU_ROUTELOC0 */
-#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */
-#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */
-#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */
-#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */
-#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */
-#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */
-#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */
-#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */
-#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */
-#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC0 */
-#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC0 */
-#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */
-#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */
-#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */
-#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */
-#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */
-#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */
-#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */
-#define CMU_ROUTELOC0_CLKOUT0LOC_LOC6 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC0 */
-#define CMU_ROUTELOC0_CLKOUT0LOC_LOC7 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC0 */
-#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */
-#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */
-#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */
-#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */
-#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */
-#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */
-#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */
-#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */
-#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */
-#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC0 */
-#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC0 */
-#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */
-#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */
-#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */
-#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */
-#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */
-#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */
-#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */
-#define CMU_ROUTELOC0_CLKOUT1LOC_LOC6 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC6 << 8) /**< Shifted mode LOC6 for CMU_ROUTELOC0 */
-#define CMU_ROUTELOC0_CLKOUT1LOC_LOC7 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC7 << 8) /**< Shifted mode LOC7 for CMU_ROUTELOC0 */
-
-/* Bit fields for CMU ROUTELOC1 */
-#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */
-#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */
-#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */
-#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */
-#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */
-#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */
-#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */
-#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */
-#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */
-#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */
-#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */
-#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */
-#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */
-#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */
-#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */
-#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */
-
-/* Bit fields for CMU LOCK */
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */
-
-/* Bit fields for CMU HFRCOSS */
-#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */
-#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */
-#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */
-#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */
-#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */
-#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */
-#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */
-#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */
-#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */
-#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */
-
-/** @} */
-/** @} End of group EFR32FG13P_CMU */
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_cryotimer.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_cryotimer.h
deleted file mode 100644
index c334b53c..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_cryotimer.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_cryotimer.h
- * @brief EFR32FG13P_CRYOTIMER register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P_CRYOTIMER CRYOTIMER
- * @{
- * @brief EFR32FG13P_CRYOTIMER Register Declaration
- *****************************************************************************/
-/** CRYOTIMER Register Declaration */
-typedef struct {
- __IOM uint32_t CTRL; /**< Control Register */
- __IOM uint32_t PERIODSEL; /**< Interrupt Duration */
- __IM uint32_t CNT; /**< Counter Value */
- __IOM uint32_t EM4WUEN; /**< Wake Up Enable */
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
-} CRYOTIMER_TypeDef; /** @} */
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_CRYOTIMER
- * @{
- * @defgroup EFR32FG13P_CRYOTIMER_BitFields CRYOTIMER Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for CRYOTIMER CTRL */
-#define _CRYOTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_CTRL */
-#define _CRYOTIMER_CTRL_MASK 0x000000FFUL /**< Mask for CRYOTIMER_CTRL */
-#define CRYOTIMER_CTRL_EN (0x1UL << 0) /**< Enable CRYOTIMER */
-#define _CRYOTIMER_CTRL_EN_SHIFT 0 /**< Shift value for CRYOTIMER_EN */
-#define _CRYOTIMER_CTRL_EN_MASK 0x1UL /**< Bit mask for CRYOTIMER_EN */
-#define _CRYOTIMER_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */
-#define CRYOTIMER_CTRL_EN_DEFAULT (_CRYOTIMER_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
-#define CRYOTIMER_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */
-#define _CRYOTIMER_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for CRYOTIMER_DEBUGRUN */
-#define _CRYOTIMER_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for CRYOTIMER_DEBUGRUN */
-#define _CRYOTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */
-#define CRYOTIMER_CTRL_DEBUGRUN_DEFAULT (_CRYOTIMER_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
-#define _CRYOTIMER_CTRL_OSCSEL_SHIFT 2 /**< Shift value for CRYOTIMER_OSCSEL */
-#define _CRYOTIMER_CTRL_OSCSEL_MASK 0x1CUL /**< Bit mask for CRYOTIMER_OSCSEL */
-#define _CRYOTIMER_CTRL_OSCSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */
-#define _CRYOTIMER_CTRL_OSCSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CRYOTIMER_CTRL */
-#define _CRYOTIMER_CTRL_OSCSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CRYOTIMER_CTRL */
-#define _CRYOTIMER_CTRL_OSCSEL_LFXO 0x00000002UL /**< Mode LFXO for CRYOTIMER_CTRL */
-#define _CRYOTIMER_CTRL_OSCSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CRYOTIMER_CTRL */
-#define CRYOTIMER_CTRL_OSCSEL_DEFAULT (_CRYOTIMER_CTRL_OSCSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
-#define CRYOTIMER_CTRL_OSCSEL_DISABLED (_CRYOTIMER_CTRL_OSCSEL_DISABLED << 2) /**< Shifted mode DISABLED for CRYOTIMER_CTRL */
-#define CRYOTIMER_CTRL_OSCSEL_LFRCO (_CRYOTIMER_CTRL_OSCSEL_LFRCO << 2) /**< Shifted mode LFRCO for CRYOTIMER_CTRL */
-#define CRYOTIMER_CTRL_OSCSEL_LFXO (_CRYOTIMER_CTRL_OSCSEL_LFXO << 2) /**< Shifted mode LFXO for CRYOTIMER_CTRL */
-#define CRYOTIMER_CTRL_OSCSEL_ULFRCO (_CRYOTIMER_CTRL_OSCSEL_ULFRCO << 2) /**< Shifted mode ULFRCO for CRYOTIMER_CTRL */
-#define _CRYOTIMER_CTRL_PRESC_SHIFT 5 /**< Shift value for CRYOTIMER_PRESC */
-#define _CRYOTIMER_CTRL_PRESC_MASK 0xE0UL /**< Bit mask for CRYOTIMER_PRESC */
-#define _CRYOTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */
-#define _CRYOTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for CRYOTIMER_CTRL */
-#define _CRYOTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for CRYOTIMER_CTRL */
-#define _CRYOTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for CRYOTIMER_CTRL */
-#define _CRYOTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for CRYOTIMER_CTRL */
-#define _CRYOTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for CRYOTIMER_CTRL */
-#define _CRYOTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for CRYOTIMER_CTRL */
-#define _CRYOTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for CRYOTIMER_CTRL */
-#define _CRYOTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for CRYOTIMER_CTRL */
-#define CRYOTIMER_CTRL_PRESC_DEFAULT (_CRYOTIMER_CTRL_PRESC_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
-#define CRYOTIMER_CTRL_PRESC_DIV1 (_CRYOTIMER_CTRL_PRESC_DIV1 << 5) /**< Shifted mode DIV1 for CRYOTIMER_CTRL */
-#define CRYOTIMER_CTRL_PRESC_DIV2 (_CRYOTIMER_CTRL_PRESC_DIV2 << 5) /**< Shifted mode DIV2 for CRYOTIMER_CTRL */
-#define CRYOTIMER_CTRL_PRESC_DIV4 (_CRYOTIMER_CTRL_PRESC_DIV4 << 5) /**< Shifted mode DIV4 for CRYOTIMER_CTRL */
-#define CRYOTIMER_CTRL_PRESC_DIV8 (_CRYOTIMER_CTRL_PRESC_DIV8 << 5) /**< Shifted mode DIV8 for CRYOTIMER_CTRL */
-#define CRYOTIMER_CTRL_PRESC_DIV16 (_CRYOTIMER_CTRL_PRESC_DIV16 << 5) /**< Shifted mode DIV16 for CRYOTIMER_CTRL */
-#define CRYOTIMER_CTRL_PRESC_DIV32 (_CRYOTIMER_CTRL_PRESC_DIV32 << 5) /**< Shifted mode DIV32 for CRYOTIMER_CTRL */
-#define CRYOTIMER_CTRL_PRESC_DIV64 (_CRYOTIMER_CTRL_PRESC_DIV64 << 5) /**< Shifted mode DIV64 for CRYOTIMER_CTRL */
-#define CRYOTIMER_CTRL_PRESC_DIV128 (_CRYOTIMER_CTRL_PRESC_DIV128 << 5) /**< Shifted mode DIV128 for CRYOTIMER_CTRL */
-
-/* Bit fields for CRYOTIMER PERIODSEL */
-#define _CRYOTIMER_PERIODSEL_RESETVALUE 0x00000020UL /**< Default value for CRYOTIMER_PERIODSEL */
-#define _CRYOTIMER_PERIODSEL_MASK 0x0000003FUL /**< Mask for CRYOTIMER_PERIODSEL */
-#define _CRYOTIMER_PERIODSEL_PERIODSEL_SHIFT 0 /**< Shift value for CRYOTIMER_PERIODSEL */
-#define _CRYOTIMER_PERIODSEL_PERIODSEL_MASK 0x3FUL /**< Bit mask for CRYOTIMER_PERIODSEL */
-#define _CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT 0x00000020UL /**< Mode DEFAULT for CRYOTIMER_PERIODSEL */
-#define CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT (_CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_PERIODSEL */
-
-/* Bit fields for CRYOTIMER CNT */
-#define _CRYOTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_CNT */
-#define _CRYOTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for CRYOTIMER_CNT */
-#define _CRYOTIMER_CNT_CNT_SHIFT 0 /**< Shift value for CRYOTIMER_CNT */
-#define _CRYOTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for CRYOTIMER_CNT */
-#define _CRYOTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CNT */
-#define CRYOTIMER_CNT_CNT_DEFAULT (_CRYOTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_CNT */
-
-/* Bit fields for CRYOTIMER EM4WUEN */
-#define _CRYOTIMER_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_EM4WUEN */
-#define _CRYOTIMER_EM4WUEN_MASK 0x00000001UL /**< Mask for CRYOTIMER_EM4WUEN */
-#define CRYOTIMER_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up Enable */
-#define _CRYOTIMER_EM4WUEN_EM4WU_SHIFT 0 /**< Shift value for CRYOTIMER_EM4WU */
-#define _CRYOTIMER_EM4WUEN_EM4WU_MASK 0x1UL /**< Bit mask for CRYOTIMER_EM4WU */
-#define _CRYOTIMER_EM4WUEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_EM4WUEN */
-#define CRYOTIMER_EM4WUEN_EM4WU_DEFAULT (_CRYOTIMER_EM4WUEN_EM4WU_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_EM4WUEN */
-
-/* Bit fields for CRYOTIMER IF */
-#define _CRYOTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IF */
-#define _CRYOTIMER_IF_MASK 0x00000001UL /**< Mask for CRYOTIMER_IF */
-#define CRYOTIMER_IF_PERIOD (0x1UL << 0) /**< Wakeup Event/Interrupt */
-#define _CRYOTIMER_IF_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */
-#define _CRYOTIMER_IF_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */
-#define _CRYOTIMER_IF_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IF */
-#define CRYOTIMER_IF_PERIOD_DEFAULT (_CRYOTIMER_IF_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IF */
-
-/* Bit fields for CRYOTIMER IFS */
-#define _CRYOTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IFS */
-#define _CRYOTIMER_IFS_MASK 0x00000001UL /**< Mask for CRYOTIMER_IFS */
-#define CRYOTIMER_IFS_PERIOD (0x1UL << 0) /**< Set PERIOD Interrupt Flag */
-#define _CRYOTIMER_IFS_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */
-#define _CRYOTIMER_IFS_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */
-#define _CRYOTIMER_IFS_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IFS */
-#define CRYOTIMER_IFS_PERIOD_DEFAULT (_CRYOTIMER_IFS_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IFS */
-
-/* Bit fields for CRYOTIMER IFC */
-#define _CRYOTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IFC */
-#define _CRYOTIMER_IFC_MASK 0x00000001UL /**< Mask for CRYOTIMER_IFC */
-#define CRYOTIMER_IFC_PERIOD (0x1UL << 0) /**< Clear PERIOD Interrupt Flag */
-#define _CRYOTIMER_IFC_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */
-#define _CRYOTIMER_IFC_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */
-#define _CRYOTIMER_IFC_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IFC */
-#define CRYOTIMER_IFC_PERIOD_DEFAULT (_CRYOTIMER_IFC_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IFC */
-
-/* Bit fields for CRYOTIMER IEN */
-#define _CRYOTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IEN */
-#define _CRYOTIMER_IEN_MASK 0x00000001UL /**< Mask for CRYOTIMER_IEN */
-#define CRYOTIMER_IEN_PERIOD (0x1UL << 0) /**< PERIOD Interrupt Enable */
-#define _CRYOTIMER_IEN_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */
-#define _CRYOTIMER_IEN_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */
-#define _CRYOTIMER_IEN_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IEN */
-#define CRYOTIMER_IEN_PERIOD_DEFAULT (_CRYOTIMER_IEN_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IEN */
-
-/** @} */
-/** @} End of group EFR32FG13P_CRYOTIMER */
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_crypto.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_crypto.h
deleted file mode 100644
index 15309382..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_crypto.h
+++ /dev/null
@@ -1,1205 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_crypto.h
- * @brief EFR32FG13P_CRYPTO register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P_CRYPTO CRYPTO
- * @{
- * @brief EFR32FG13P_CRYPTO Register Declaration
- *****************************************************************************/
-/** CRYPTO Register Declaration */
-typedef struct {
- __IOM uint32_t CTRL; /**< Control Register */
- __IOM uint32_t WAC; /**< Wide Arithmetic Configuration */
- __IOM uint32_t CMD; /**< Command Register */
- uint32_t RESERVED0[1]; /**< Reserved for future use **/
- __IM uint32_t STATUS; /**< Status Register */
- __IM uint32_t DSTATUS; /**< Data Status Register */
- __IM uint32_t CSTATUS; /**< Control Status Register */
- uint32_t RESERVED1[1]; /**< Reserved for future use **/
- __IOM uint32_t KEY; /**< KEY Register Access */
- __IOM uint32_t KEYBUF; /**< KEY Buffer Register Access */
- uint32_t RESERVED2[2]; /**< Reserved for future use **/
- __IOM uint32_t SEQCTRL; /**< Sequence Control */
- __IOM uint32_t SEQCTRLB; /**< Sequence Control B */
- uint32_t RESERVED3[2]; /**< Reserved for future use **/
- __IM uint32_t IF; /**< AES Interrupt Flags */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- __IOM uint32_t SEQ0; /**< Sequence Register 0 */
- __IOM uint32_t SEQ1; /**< Sequence Register 1 */
- __IOM uint32_t SEQ2; /**< Sequence Register 2 */
- __IOM uint32_t SEQ3; /**< Sequence Register 3 */
- __IOM uint32_t SEQ4; /**< Sequence Register 4 */
- uint32_t RESERVED4[7]; /**< Reserved for future use **/
- __IOM uint32_t DATA0; /**< DATA0 Register Access */
- __IOM uint32_t DATA1; /**< DATA1 Register Access */
- __IOM uint32_t DATA2; /**< DATA2 Register Access */
- __IOM uint32_t DATA3; /**< DATA3 Register Access */
- uint32_t RESERVED5[4]; /**< Reserved for future use **/
- __IOM uint32_t DATA0XOR; /**< DATA0XOR Register Access */
- uint32_t RESERVED6[3]; /**< Reserved for future use **/
- __IOM uint32_t DATA0BYTE; /**< DATA0 Register Byte Access */
- __IOM uint32_t DATA1BYTE; /**< DATA1 Register Byte Access */
- uint32_t RESERVED7[1]; /**< Reserved for future use **/
- __IOM uint32_t DATA0XORBYTE; /**< DATA0 Register Byte XOR Access */
- __IOM uint32_t DATA0BYTE12; /**< DATA0 Register Byte 12 Access */
- __IOM uint32_t DATA0BYTE13; /**< DATA0 Register Byte 13 Access */
- __IOM uint32_t DATA0BYTE14; /**< DATA0 Register Byte 14 Access */
- __IOM uint32_t DATA0BYTE15; /**< DATA0 Register Byte 15 Access */
- uint32_t RESERVED8[12]; /**< Reserved for future use **/
- __IOM uint32_t DDATA0; /**< DDATA0 Register Access */
- __IOM uint32_t DDATA1; /**< DDATA1 Register Access */
- __IOM uint32_t DDATA2; /**< DDATA2 Register Access */
- __IOM uint32_t DDATA3; /**< DDATA3 Register Access */
- __IOM uint32_t DDATA4; /**< DDATA4 Register Access */
- uint32_t RESERVED9[7]; /**< Reserved for future use **/
- __IOM uint32_t DDATA0BIG; /**< DDATA0 Register Big Endian Access */
- uint32_t RESERVED10[3]; /**< Reserved for future use **/
- __IOM uint32_t DDATA0BYTE; /**< DDATA0 Register Byte Access */
- __IOM uint32_t DDATA1BYTE; /**< DDATA1 Register Byte Access */
- __IOM uint32_t DDATA0BYTE32; /**< DDATA0 Register Byte 32 Access */
- uint32_t RESERVED11[13]; /**< Reserved for future use **/
- __IOM uint32_t QDATA0; /**< QDATA0 Register Access */
- __IOM uint32_t QDATA1; /**< QDATA1 Register Access */
- uint32_t RESERVED12[7]; /**< Reserved for future use **/
- __IOM uint32_t QDATA1BIG; /**< QDATA1 Register Big Endian Access */
- uint32_t RESERVED13[6]; /**< Reserved for future use **/
- __IOM uint32_t QDATA0BYTE; /**< QDATA0 Register Byte Access */
- __IOM uint32_t QDATA1BYTE; /**< QDATA1 Register Byte Access */
-} CRYPTO_TypeDef; /** @} */
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_CRYPTO
- * @{
- * @defgroup EFR32FG13P_CRYPTO_BitFields CRYPTO Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for CRYPTO CTRL */
-#define _CRYPTO_CTRL_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_CTRL */
-#define _CRYPTO_CTRL_MASK 0xB333C407UL /**< Mask for CRYPTO_CTRL */
-#define CRYPTO_CTRL_AES (0x1UL << 0) /**< AES Mode */
-#define _CRYPTO_CTRL_AES_SHIFT 0 /**< Shift value for CRYPTO_AES */
-#define _CRYPTO_CTRL_AES_MASK 0x1UL /**< Bit mask for CRYPTO_AES */
-#define _CRYPTO_CTRL_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */
-#define _CRYPTO_CTRL_AES_AES128 0x00000000UL /**< Mode AES128 for CRYPTO_CTRL */
-#define _CRYPTO_CTRL_AES_AES256 0x00000001UL /**< Mode AES256 for CRYPTO_CTRL */
-#define CRYPTO_CTRL_AES_DEFAULT (_CRYPTO_CTRL_AES_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_CTRL */
-#define CRYPTO_CTRL_AES_AES128 (_CRYPTO_CTRL_AES_AES128 << 0) /**< Shifted mode AES128 for CRYPTO_CTRL */
-#define CRYPTO_CTRL_AES_AES256 (_CRYPTO_CTRL_AES_AES256 << 0) /**< Shifted mode AES256 for CRYPTO_CTRL */
-#define CRYPTO_CTRL_KEYBUFDIS (0x1UL << 1) /**< Key Buffer Disable */
-#define _CRYPTO_CTRL_KEYBUFDIS_SHIFT 1 /**< Shift value for CRYPTO_KEYBUFDIS */
-#define _CRYPTO_CTRL_KEYBUFDIS_MASK 0x2UL /**< Bit mask for CRYPTO_KEYBUFDIS */
-#define _CRYPTO_CTRL_KEYBUFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */
-#define CRYPTO_CTRL_KEYBUFDIS_DEFAULT (_CRYPTO_CTRL_KEYBUFDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_CTRL */
-#define CRYPTO_CTRL_SHA (0x1UL << 2) /**< SHA Mode */
-#define _CRYPTO_CTRL_SHA_SHIFT 2 /**< Shift value for CRYPTO_SHA */
-#define _CRYPTO_CTRL_SHA_MASK 0x4UL /**< Bit mask for CRYPTO_SHA */
-#define _CRYPTO_CTRL_SHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */
-#define _CRYPTO_CTRL_SHA_SHA1 0x00000000UL /**< Mode SHA1 for CRYPTO_CTRL */
-#define _CRYPTO_CTRL_SHA_SHA2 0x00000001UL /**< Mode SHA2 for CRYPTO_CTRL */
-#define CRYPTO_CTRL_SHA_DEFAULT (_CRYPTO_CTRL_SHA_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_CTRL */
-#define CRYPTO_CTRL_SHA_SHA1 (_CRYPTO_CTRL_SHA_SHA1 << 2) /**< Shifted mode SHA1 for CRYPTO_CTRL */
-#define CRYPTO_CTRL_SHA_SHA2 (_CRYPTO_CTRL_SHA_SHA2 << 2) /**< Shifted mode SHA2 for CRYPTO_CTRL */
-#define CRYPTO_CTRL_NOBUSYSTALL (0x1UL << 10) /**< No Stalling of Bus When Busy */
-#define _CRYPTO_CTRL_NOBUSYSTALL_SHIFT 10 /**< Shift value for CRYPTO_NOBUSYSTALL */
-#define _CRYPTO_CTRL_NOBUSYSTALL_MASK 0x400UL /**< Bit mask for CRYPTO_NOBUSYSTALL */
-#define _CRYPTO_CTRL_NOBUSYSTALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */
-#define CRYPTO_CTRL_NOBUSYSTALL_DEFAULT (_CRYPTO_CTRL_NOBUSYSTALL_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTO_CTRL */
-#define _CRYPTO_CTRL_INCWIDTH_SHIFT 14 /**< Shift value for CRYPTO_INCWIDTH */
-#define _CRYPTO_CTRL_INCWIDTH_MASK 0xC000UL /**< Bit mask for CRYPTO_INCWIDTH */
-#define _CRYPTO_CTRL_INCWIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */
-#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH1 0x00000000UL /**< Mode INCWIDTH1 for CRYPTO_CTRL */
-#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH2 0x00000001UL /**< Mode INCWIDTH2 for CRYPTO_CTRL */
-#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH3 0x00000002UL /**< Mode INCWIDTH3 for CRYPTO_CTRL */
-#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH4 0x00000003UL /**< Mode INCWIDTH4 for CRYPTO_CTRL */
-#define CRYPTO_CTRL_INCWIDTH_DEFAULT (_CRYPTO_CTRL_INCWIDTH_DEFAULT << 14) /**< Shifted mode DEFAULT for CRYPTO_CTRL */
-#define CRYPTO_CTRL_INCWIDTH_INCWIDTH1 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH1 << 14) /**< Shifted mode INCWIDTH1 for CRYPTO_CTRL */
-#define CRYPTO_CTRL_INCWIDTH_INCWIDTH2 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH2 << 14) /**< Shifted mode INCWIDTH2 for CRYPTO_CTRL */
-#define CRYPTO_CTRL_INCWIDTH_INCWIDTH3 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH3 << 14) /**< Shifted mode INCWIDTH3 for CRYPTO_CTRL */
-#define CRYPTO_CTRL_INCWIDTH_INCWIDTH4 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH4 << 14) /**< Shifted mode INCWIDTH4 for CRYPTO_CTRL */
-#define _CRYPTO_CTRL_DMA0MODE_SHIFT 16 /**< Shift value for CRYPTO_DMA0MODE */
-#define _CRYPTO_CTRL_DMA0MODE_MASK 0x30000UL /**< Bit mask for CRYPTO_DMA0MODE */
-#define _CRYPTO_CTRL_DMA0MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */
-#define _CRYPTO_CTRL_DMA0MODE_FULL 0x00000000UL /**< Mode FULL for CRYPTO_CTRL */
-#define _CRYPTO_CTRL_DMA0MODE_LENLIMIT 0x00000001UL /**< Mode LENLIMIT for CRYPTO_CTRL */
-#define _CRYPTO_CTRL_DMA0MODE_FULLBYTE 0x00000002UL /**< Mode FULLBYTE for CRYPTO_CTRL */
-#define _CRYPTO_CTRL_DMA0MODE_LENLIMITBYTE 0x00000003UL /**< Mode LENLIMITBYTE for CRYPTO_CTRL */
-#define CRYPTO_CTRL_DMA0MODE_DEFAULT (_CRYPTO_CTRL_DMA0MODE_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_CTRL */
-#define CRYPTO_CTRL_DMA0MODE_FULL (_CRYPTO_CTRL_DMA0MODE_FULL << 16) /**< Shifted mode FULL for CRYPTO_CTRL */
-#define CRYPTO_CTRL_DMA0MODE_LENLIMIT (_CRYPTO_CTRL_DMA0MODE_LENLIMIT << 16) /**< Shifted mode LENLIMIT for CRYPTO_CTRL */
-#define CRYPTO_CTRL_DMA0MODE_FULLBYTE (_CRYPTO_CTRL_DMA0MODE_FULLBYTE << 16) /**< Shifted mode FULLBYTE for CRYPTO_CTRL */
-#define CRYPTO_CTRL_DMA0MODE_LENLIMITBYTE (_CRYPTO_CTRL_DMA0MODE_LENLIMITBYTE << 16) /**< Shifted mode LENLIMITBYTE for CRYPTO_CTRL */
-#define _CRYPTO_CTRL_DMA0RSEL_SHIFT 20 /**< Shift value for CRYPTO_DMA0RSEL */
-#define _CRYPTO_CTRL_DMA0RSEL_MASK 0x300000UL /**< Bit mask for CRYPTO_DMA0RSEL */
-#define _CRYPTO_CTRL_DMA0RSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */
-#define _CRYPTO_CTRL_DMA0RSEL_DATA0 0x00000000UL /**< Mode DATA0 for CRYPTO_CTRL */
-#define _CRYPTO_CTRL_DMA0RSEL_DDATA0 0x00000001UL /**< Mode DDATA0 for CRYPTO_CTRL */
-#define _CRYPTO_CTRL_DMA0RSEL_DDATA0BIG 0x00000002UL /**< Mode DDATA0BIG for CRYPTO_CTRL */
-#define _CRYPTO_CTRL_DMA0RSEL_QDATA0 0x00000003UL /**< Mode QDATA0 for CRYPTO_CTRL */
-#define CRYPTO_CTRL_DMA0RSEL_DEFAULT (_CRYPTO_CTRL_DMA0RSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_CTRL */
-#define CRYPTO_CTRL_DMA0RSEL_DATA0 (_CRYPTO_CTRL_DMA0RSEL_DATA0 << 20) /**< Shifted mode DATA0 for CRYPTO_CTRL */
-#define CRYPTO_CTRL_DMA0RSEL_DDATA0 (_CRYPTO_CTRL_DMA0RSEL_DDATA0 << 20) /**< Shifted mode DDATA0 for CRYPTO_CTRL */
-#define CRYPTO_CTRL_DMA0RSEL_DDATA0BIG (_CRYPTO_CTRL_DMA0RSEL_DDATA0BIG << 20) /**< Shifted mode DDATA0BIG for CRYPTO_CTRL */
-#define CRYPTO_CTRL_DMA0RSEL_QDATA0 (_CRYPTO_CTRL_DMA0RSEL_QDATA0 << 20) /**< Shifted mode QDATA0 for CRYPTO_CTRL */
-#define _CRYPTO_CTRL_DMA1MODE_SHIFT 24 /**< Shift value for CRYPTO_DMA1MODE */
-#define _CRYPTO_CTRL_DMA1MODE_MASK 0x3000000UL /**< Bit mask for CRYPTO_DMA1MODE */
-#define _CRYPTO_CTRL_DMA1MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */
-#define _CRYPTO_CTRL_DMA1MODE_FULL 0x00000000UL /**< Mode FULL for CRYPTO_CTRL */
-#define _CRYPTO_CTRL_DMA1MODE_LENLIMIT 0x00000001UL /**< Mode LENLIMIT for CRYPTO_CTRL */
-#define _CRYPTO_CTRL_DMA1MODE_FULLBYTE 0x00000002UL /**< Mode FULLBYTE for CRYPTO_CTRL */
-#define _CRYPTO_CTRL_DMA1MODE_LENLIMITBYTE 0x00000003UL /**< Mode LENLIMITBYTE for CRYPTO_CTRL */
-#define CRYPTO_CTRL_DMA1MODE_DEFAULT (_CRYPTO_CTRL_DMA1MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_CTRL */
-#define CRYPTO_CTRL_DMA1MODE_FULL (_CRYPTO_CTRL_DMA1MODE_FULL << 24) /**< Shifted mode FULL for CRYPTO_CTRL */
-#define CRYPTO_CTRL_DMA1MODE_LENLIMIT (_CRYPTO_CTRL_DMA1MODE_LENLIMIT << 24) /**< Shifted mode LENLIMIT for CRYPTO_CTRL */
-#define CRYPTO_CTRL_DMA1MODE_FULLBYTE (_CRYPTO_CTRL_DMA1MODE_FULLBYTE << 24) /**< Shifted mode FULLBYTE for CRYPTO_CTRL */
-#define CRYPTO_CTRL_DMA1MODE_LENLIMITBYTE (_CRYPTO_CTRL_DMA1MODE_LENLIMITBYTE << 24) /**< Shifted mode LENLIMITBYTE for CRYPTO_CTRL */
-#define _CRYPTO_CTRL_DMA1RSEL_SHIFT 28 /**< Shift value for CRYPTO_DMA1RSEL */
-#define _CRYPTO_CTRL_DMA1RSEL_MASK 0x30000000UL /**< Bit mask for CRYPTO_DMA1RSEL */
-#define _CRYPTO_CTRL_DMA1RSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */
-#define _CRYPTO_CTRL_DMA1RSEL_DATA1 0x00000000UL /**< Mode DATA1 for CRYPTO_CTRL */
-#define _CRYPTO_CTRL_DMA1RSEL_DDATA1 0x00000001UL /**< Mode DDATA1 for CRYPTO_CTRL */
-#define _CRYPTO_CTRL_DMA1RSEL_QDATA1 0x00000002UL /**< Mode QDATA1 for CRYPTO_CTRL */
-#define _CRYPTO_CTRL_DMA1RSEL_QDATA1BIG 0x00000003UL /**< Mode QDATA1BIG for CRYPTO_CTRL */
-#define CRYPTO_CTRL_DMA1RSEL_DEFAULT (_CRYPTO_CTRL_DMA1RSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTO_CTRL */
-#define CRYPTO_CTRL_DMA1RSEL_DATA1 (_CRYPTO_CTRL_DMA1RSEL_DATA1 << 28) /**< Shifted mode DATA1 for CRYPTO_CTRL */
-#define CRYPTO_CTRL_DMA1RSEL_DDATA1 (_CRYPTO_CTRL_DMA1RSEL_DDATA1 << 28) /**< Shifted mode DDATA1 for CRYPTO_CTRL */
-#define CRYPTO_CTRL_DMA1RSEL_QDATA1 (_CRYPTO_CTRL_DMA1RSEL_QDATA1 << 28) /**< Shifted mode QDATA1 for CRYPTO_CTRL */
-#define CRYPTO_CTRL_DMA1RSEL_QDATA1BIG (_CRYPTO_CTRL_DMA1RSEL_QDATA1BIG << 28) /**< Shifted mode QDATA1BIG for CRYPTO_CTRL */
-#define CRYPTO_CTRL_COMBDMA0WEREQ (0x1UL << 31) /**< Combined Data0 Write DMA Request */
-#define _CRYPTO_CTRL_COMBDMA0WEREQ_SHIFT 31 /**< Shift value for CRYPTO_COMBDMA0WEREQ */
-#define _CRYPTO_CTRL_COMBDMA0WEREQ_MASK 0x80000000UL /**< Bit mask for CRYPTO_COMBDMA0WEREQ */
-#define _CRYPTO_CTRL_COMBDMA0WEREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */
-#define CRYPTO_CTRL_COMBDMA0WEREQ_DEFAULT (_CRYPTO_CTRL_COMBDMA0WEREQ_DEFAULT << 31) /**< Shifted mode DEFAULT for CRYPTO_CTRL */
-
-/* Bit fields for CRYPTO WAC */
-#define _CRYPTO_WAC_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_WAC */
-#define _CRYPTO_WAC_MASK 0x00000F1FUL /**< Mask for CRYPTO_WAC */
-#define _CRYPTO_WAC_MODULUS_SHIFT 0 /**< Shift value for CRYPTO_MODULUS */
-#define _CRYPTO_WAC_MODULUS_MASK 0xFUL /**< Bit mask for CRYPTO_MODULUS */
-#define _CRYPTO_WAC_MODULUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */
-#define _CRYPTO_WAC_MODULUS_BIN256 0x00000000UL /**< Mode BIN256 for CRYPTO_WAC */
-#define _CRYPTO_WAC_MODULUS_BIN128 0x00000001UL /**< Mode BIN128 for CRYPTO_WAC */
-#define _CRYPTO_WAC_MODULUS_ECCBIN233P 0x00000002UL /**< Mode ECCBIN233P for CRYPTO_WAC */
-#define _CRYPTO_WAC_MODULUS_ECCBIN163P 0x00000003UL /**< Mode ECCBIN163P for CRYPTO_WAC */
-#define _CRYPTO_WAC_MODULUS_GCMBIN128 0x00000004UL /**< Mode GCMBIN128 for CRYPTO_WAC */
-#define _CRYPTO_WAC_MODULUS_ECCPRIME256P 0x00000005UL /**< Mode ECCPRIME256P for CRYPTO_WAC */
-#define _CRYPTO_WAC_MODULUS_ECCPRIME224P 0x00000006UL /**< Mode ECCPRIME224P for CRYPTO_WAC */
-#define _CRYPTO_WAC_MODULUS_ECCPRIME192P 0x00000007UL /**< Mode ECCPRIME192P for CRYPTO_WAC */
-#define _CRYPTO_WAC_MODULUS_ECCBIN233N 0x00000008UL /**< Mode ECCBIN233N for CRYPTO_WAC */
-#define _CRYPTO_WAC_MODULUS_ECCBIN233KN 0x00000009UL /**< Mode ECCBIN233KN for CRYPTO_WAC */
-#define _CRYPTO_WAC_MODULUS_ECCBIN163N 0x0000000AUL /**< Mode ECCBIN163N for CRYPTO_WAC */
-#define _CRYPTO_WAC_MODULUS_ECCBIN163KN 0x0000000BUL /**< Mode ECCBIN163KN for CRYPTO_WAC */
-#define _CRYPTO_WAC_MODULUS_ECCPRIME256N 0x0000000CUL /**< Mode ECCPRIME256N for CRYPTO_WAC */
-#define _CRYPTO_WAC_MODULUS_ECCPRIME224N 0x0000000DUL /**< Mode ECCPRIME224N for CRYPTO_WAC */
-#define _CRYPTO_WAC_MODULUS_ECCPRIME192N 0x0000000EUL /**< Mode ECCPRIME192N for CRYPTO_WAC */
-#define CRYPTO_WAC_MODULUS_DEFAULT (_CRYPTO_WAC_MODULUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_WAC */
-#define CRYPTO_WAC_MODULUS_BIN256 (_CRYPTO_WAC_MODULUS_BIN256 << 0) /**< Shifted mode BIN256 for CRYPTO_WAC */
-#define CRYPTO_WAC_MODULUS_BIN128 (_CRYPTO_WAC_MODULUS_BIN128 << 0) /**< Shifted mode BIN128 for CRYPTO_WAC */
-#define CRYPTO_WAC_MODULUS_ECCBIN233P (_CRYPTO_WAC_MODULUS_ECCBIN233P << 0) /**< Shifted mode ECCBIN233P for CRYPTO_WAC */
-#define CRYPTO_WAC_MODULUS_ECCBIN163P (_CRYPTO_WAC_MODULUS_ECCBIN163P << 0) /**< Shifted mode ECCBIN163P for CRYPTO_WAC */
-#define CRYPTO_WAC_MODULUS_GCMBIN128 (_CRYPTO_WAC_MODULUS_GCMBIN128 << 0) /**< Shifted mode GCMBIN128 for CRYPTO_WAC */
-#define CRYPTO_WAC_MODULUS_ECCPRIME256P (_CRYPTO_WAC_MODULUS_ECCPRIME256P << 0) /**< Shifted mode ECCPRIME256P for CRYPTO_WAC */
-#define CRYPTO_WAC_MODULUS_ECCPRIME224P (_CRYPTO_WAC_MODULUS_ECCPRIME224P << 0) /**< Shifted mode ECCPRIME224P for CRYPTO_WAC */
-#define CRYPTO_WAC_MODULUS_ECCPRIME192P (_CRYPTO_WAC_MODULUS_ECCPRIME192P << 0) /**< Shifted mode ECCPRIME192P for CRYPTO_WAC */
-#define CRYPTO_WAC_MODULUS_ECCBIN233N (_CRYPTO_WAC_MODULUS_ECCBIN233N << 0) /**< Shifted mode ECCBIN233N for CRYPTO_WAC */
-#define CRYPTO_WAC_MODULUS_ECCBIN233KN (_CRYPTO_WAC_MODULUS_ECCBIN233KN << 0) /**< Shifted mode ECCBIN233KN for CRYPTO_WAC */
-#define CRYPTO_WAC_MODULUS_ECCBIN163N (_CRYPTO_WAC_MODULUS_ECCBIN163N << 0) /**< Shifted mode ECCBIN163N for CRYPTO_WAC */
-#define CRYPTO_WAC_MODULUS_ECCBIN163KN (_CRYPTO_WAC_MODULUS_ECCBIN163KN << 0) /**< Shifted mode ECCBIN163KN for CRYPTO_WAC */
-#define CRYPTO_WAC_MODULUS_ECCPRIME256N (_CRYPTO_WAC_MODULUS_ECCPRIME256N << 0) /**< Shifted mode ECCPRIME256N for CRYPTO_WAC */
-#define CRYPTO_WAC_MODULUS_ECCPRIME224N (_CRYPTO_WAC_MODULUS_ECCPRIME224N << 0) /**< Shifted mode ECCPRIME224N for CRYPTO_WAC */
-#define CRYPTO_WAC_MODULUS_ECCPRIME192N (_CRYPTO_WAC_MODULUS_ECCPRIME192N << 0) /**< Shifted mode ECCPRIME192N for CRYPTO_WAC */
-#define CRYPTO_WAC_MODOP (0x1UL << 4) /**< Modular Operation Field Type */
-#define _CRYPTO_WAC_MODOP_SHIFT 4 /**< Shift value for CRYPTO_MODOP */
-#define _CRYPTO_WAC_MODOP_MASK 0x10UL /**< Bit mask for CRYPTO_MODOP */
-#define _CRYPTO_WAC_MODOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */
-#define _CRYPTO_WAC_MODOP_BINARY 0x00000000UL /**< Mode BINARY for CRYPTO_WAC */
-#define _CRYPTO_WAC_MODOP_REGULAR 0x00000001UL /**< Mode REGULAR for CRYPTO_WAC */
-#define CRYPTO_WAC_MODOP_DEFAULT (_CRYPTO_WAC_MODOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTO_WAC */
-#define CRYPTO_WAC_MODOP_BINARY (_CRYPTO_WAC_MODOP_BINARY << 4) /**< Shifted mode BINARY for CRYPTO_WAC */
-#define CRYPTO_WAC_MODOP_REGULAR (_CRYPTO_WAC_MODOP_REGULAR << 4) /**< Shifted mode REGULAR for CRYPTO_WAC */
-#define _CRYPTO_WAC_MULWIDTH_SHIFT 8 /**< Shift value for CRYPTO_MULWIDTH */
-#define _CRYPTO_WAC_MULWIDTH_MASK 0x300UL /**< Bit mask for CRYPTO_MULWIDTH */
-#define _CRYPTO_WAC_MULWIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */
-#define _CRYPTO_WAC_MULWIDTH_MUL256 0x00000000UL /**< Mode MUL256 for CRYPTO_WAC */
-#define _CRYPTO_WAC_MULWIDTH_MUL128 0x00000001UL /**< Mode MUL128 for CRYPTO_WAC */
-#define _CRYPTO_WAC_MULWIDTH_MULMOD 0x00000002UL /**< Mode MULMOD for CRYPTO_WAC */
-#define CRYPTO_WAC_MULWIDTH_DEFAULT (_CRYPTO_WAC_MULWIDTH_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_WAC */
-#define CRYPTO_WAC_MULWIDTH_MUL256 (_CRYPTO_WAC_MULWIDTH_MUL256 << 8) /**< Shifted mode MUL256 for CRYPTO_WAC */
-#define CRYPTO_WAC_MULWIDTH_MUL128 (_CRYPTO_WAC_MULWIDTH_MUL128 << 8) /**< Shifted mode MUL128 for CRYPTO_WAC */
-#define CRYPTO_WAC_MULWIDTH_MULMOD (_CRYPTO_WAC_MULWIDTH_MULMOD << 8) /**< Shifted mode MULMOD for CRYPTO_WAC */
-#define _CRYPTO_WAC_RESULTWIDTH_SHIFT 10 /**< Shift value for CRYPTO_RESULTWIDTH */
-#define _CRYPTO_WAC_RESULTWIDTH_MASK 0xC00UL /**< Bit mask for CRYPTO_RESULTWIDTH */
-#define _CRYPTO_WAC_RESULTWIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */
-#define _CRYPTO_WAC_RESULTWIDTH_256BIT 0x00000000UL /**< Mode 256BIT for CRYPTO_WAC */
-#define _CRYPTO_WAC_RESULTWIDTH_128BIT 0x00000001UL /**< Mode 128BIT for CRYPTO_WAC */
-#define _CRYPTO_WAC_RESULTWIDTH_260BIT 0x00000002UL /**< Mode 260BIT for CRYPTO_WAC */
-#define CRYPTO_WAC_RESULTWIDTH_DEFAULT (_CRYPTO_WAC_RESULTWIDTH_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTO_WAC */
-#define CRYPTO_WAC_RESULTWIDTH_256BIT (_CRYPTO_WAC_RESULTWIDTH_256BIT << 10) /**< Shifted mode 256BIT for CRYPTO_WAC */
-#define CRYPTO_WAC_RESULTWIDTH_128BIT (_CRYPTO_WAC_RESULTWIDTH_128BIT << 10) /**< Shifted mode 128BIT for CRYPTO_WAC */
-#define CRYPTO_WAC_RESULTWIDTH_260BIT (_CRYPTO_WAC_RESULTWIDTH_260BIT << 10) /**< Shifted mode 260BIT for CRYPTO_WAC */
-
-/* Bit fields for CRYPTO CMD */
-#define _CRYPTO_CMD_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_CMD */
-#define _CRYPTO_CMD_MASK 0x00000EFFUL /**< Mask for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SHIFT 0 /**< Shift value for CRYPTO_INSTR */
-#define _CRYPTO_CMD_INSTR_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR */
-#define _CRYPTO_CMD_INSTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_END 0x00000000UL /**< Mode END for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_EXEC 0x00000001UL /**< Mode EXEC for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA1INC 0x00000003UL /**< Mode DATA1INC for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA1INCCLR 0x00000004UL /**< Mode DATA1INCCLR for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_AESENC 0x00000005UL /**< Mode AESENC for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_AESDEC 0x00000006UL /**< Mode AESDEC for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SHA 0x00000007UL /**< Mode SHA for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_ADD 0x00000008UL /**< Mode ADD for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_ADDC 0x00000009UL /**< Mode ADDC for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_MADD 0x0000000CUL /**< Mode MADD for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_MADD32 0x0000000DUL /**< Mode MADD32 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SUB 0x00000010UL /**< Mode SUB for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SUBC 0x00000011UL /**< Mode SUBC for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_MSUB 0x00000014UL /**< Mode MSUB for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_MUL 0x00000018UL /**< Mode MUL for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_MULC 0x00000019UL /**< Mode MULC for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_MMUL 0x0000001CUL /**< Mode MMUL for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_MULO 0x0000001DUL /**< Mode MULO for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SHL 0x00000020UL /**< Mode SHL for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SHLC 0x00000021UL /**< Mode SHLC for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SHLB 0x00000022UL /**< Mode SHLB for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SHL1 0x00000023UL /**< Mode SHL1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SHR 0x00000024UL /**< Mode SHR for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SHRC 0x00000025UL /**< Mode SHRC for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SHRB 0x00000026UL /**< Mode SHRB for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SHR1 0x00000027UL /**< Mode SHR1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_ADDO 0x00000028UL /**< Mode ADDO for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_ADDIC 0x00000029UL /**< Mode ADDIC for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_CLR 0x00000030UL /**< Mode CLR for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_XOR 0x00000031UL /**< Mode XOR for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_INV 0x00000032UL /**< Mode INV for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_CSET 0x00000034UL /**< Mode CSET for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_CCLR 0x00000035UL /**< Mode CCLR for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_BBSWAP128 0x00000036UL /**< Mode BBSWAP128 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_INC 0x00000038UL /**< Mode INC for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DEC 0x00000039UL /**< Mode DEC for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SHRA 0x0000003EUL /**< Mode SHRA for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA0TODATA0 0x00000040UL /**< Mode DATA0TODATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA0TODATA0XOR 0x00000041UL /**< Mode DATA0TODATA0XOR for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA0TODATA0XORLEN 0x00000042UL /**< Mode DATA0TODATA0XORLEN for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA0TODATA1 0x00000044UL /**< Mode DATA0TODATA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA0TODATA2 0x00000045UL /**< Mode DATA0TODATA2 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA0TODATA3 0x00000046UL /**< Mode DATA0TODATA3 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA1TODATA0 0x00000048UL /**< Mode DATA1TODATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA1TODATA0XOR 0x00000049UL /**< Mode DATA1TODATA0XOR for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA1TODATA0XORLEN 0x0000004AUL /**< Mode DATA1TODATA0XORLEN for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA1TODATA2 0x0000004DUL /**< Mode DATA1TODATA2 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA1TODATA3 0x0000004EUL /**< Mode DATA1TODATA3 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA2TODATA0 0x00000050UL /**< Mode DATA2TODATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA2TODATA0XOR 0x00000051UL /**< Mode DATA2TODATA0XOR for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA2TODATA0XORLEN 0x00000052UL /**< Mode DATA2TODATA0XORLEN for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA2TODATA1 0x00000054UL /**< Mode DATA2TODATA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA2TODATA3 0x00000056UL /**< Mode DATA2TODATA3 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA3TODATA0 0x00000058UL /**< Mode DATA3TODATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA3TODATA0XOR 0x00000059UL /**< Mode DATA3TODATA0XOR for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA3TODATA0XORLEN 0x0000005AUL /**< Mode DATA3TODATA0XORLEN for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA3TODATA1 0x0000005CUL /**< Mode DATA3TODATA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA3TODATA2 0x0000005DUL /**< Mode DATA3TODATA2 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATATODMA0 0x00000063UL /**< Mode DATATODMA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA0TOBUF 0x00000064UL /**< Mode DATA0TOBUF for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA0TOBUFXOR 0x00000065UL /**< Mode DATA0TOBUFXOR for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATATODMA1 0x0000006BUL /**< Mode DATATODMA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA1TOBUF 0x0000006CUL /**< Mode DATA1TOBUF for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA1TOBUFXOR 0x0000006DUL /**< Mode DATA1TOBUFXOR for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DMA0TODATA 0x00000070UL /**< Mode DMA0TODATA for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DMA0TODATAXOR 0x00000071UL /**< Mode DMA0TODATAXOR for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DMA1TODATA 0x00000072UL /**< Mode DMA1TODATA for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_BUFTODATA0 0x00000078UL /**< Mode BUFTODATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_BUFTODATA0XOR 0x00000079UL /**< Mode BUFTODATA0XOR for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_BUFTODATA1 0x0000007AUL /**< Mode BUFTODATA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA0TODDATA1 0x00000081UL /**< Mode DDATA0TODDATA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA0TODDATA2 0x00000082UL /**< Mode DDATA0TODDATA2 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA0TODDATA3 0x00000083UL /**< Mode DDATA0TODDATA3 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA0TODDATA4 0x00000084UL /**< Mode DDATA0TODDATA4 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA0LTODATA0 0x00000085UL /**< Mode DDATA0LTODATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA0HTODATA1 0x00000086UL /**< Mode DDATA0HTODATA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA0LTODATA2 0x00000087UL /**< Mode DDATA0LTODATA2 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA1TODDATA0 0x00000088UL /**< Mode DDATA1TODDATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA1TODDATA2 0x0000008AUL /**< Mode DDATA1TODDATA2 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA1TODDATA3 0x0000008BUL /**< Mode DDATA1TODDATA3 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA1TODDATA4 0x0000008CUL /**< Mode DDATA1TODDATA4 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA1LTODATA0 0x0000008DUL /**< Mode DDATA1LTODATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA1HTODATA1 0x0000008EUL /**< Mode DDATA1HTODATA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA1LTODATA2 0x0000008FUL /**< Mode DDATA1LTODATA2 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA2TODDATA0 0x00000090UL /**< Mode DDATA2TODDATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA2TODDATA1 0x00000091UL /**< Mode DDATA2TODDATA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA2TODDATA3 0x00000093UL /**< Mode DDATA2TODDATA3 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA2TODDATA4 0x00000094UL /**< Mode DDATA2TODDATA4 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA2LTODATA2 0x00000097UL /**< Mode DDATA2LTODATA2 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA3TODDATA0 0x00000098UL /**< Mode DDATA3TODDATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA3TODDATA1 0x00000099UL /**< Mode DDATA3TODDATA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA3TODDATA2 0x0000009AUL /**< Mode DDATA3TODDATA2 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA3TODDATA4 0x0000009CUL /**< Mode DDATA3TODDATA4 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA3LTODATA0 0x0000009DUL /**< Mode DDATA3LTODATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA3HTODATA1 0x0000009EUL /**< Mode DDATA3HTODATA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA4TODDATA0 0x000000A0UL /**< Mode DDATA4TODDATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA4TODDATA1 0x000000A1UL /**< Mode DDATA4TODDATA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA4TODDATA2 0x000000A2UL /**< Mode DDATA4TODDATA2 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA4TODDATA3 0x000000A3UL /**< Mode DDATA4TODDATA3 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA4LTODATA0 0x000000A5UL /**< Mode DDATA4LTODATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA4HTODATA1 0x000000A6UL /**< Mode DDATA4HTODATA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DDATA4LTODATA2 0x000000A7UL /**< Mode DDATA4LTODATA2 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA0TODDATA0 0x000000A8UL /**< Mode DATA0TODDATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA0TODDATA1 0x000000A9UL /**< Mode DATA0TODDATA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA1TODDATA0 0x000000B0UL /**< Mode DATA1TODDATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA1TODDATA1 0x000000B1UL /**< Mode DATA1TODDATA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA2TODDATA0 0x000000B8UL /**< Mode DATA2TODDATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA2TODDATA1 0x000000B9UL /**< Mode DATA2TODDATA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_DATA2TODDATA2 0x000000BAUL /**< Mode DATA2TODDATA2 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA0 0x000000C0UL /**< Mode SELDDATA0DDATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA0 0x000000C1UL /**< Mode SELDDATA1DDATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA0 0x000000C2UL /**< Mode SELDDATA2DDATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA0 0x000000C3UL /**< Mode SELDDATA3DDATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA0 0x000000C4UL /**< Mode SELDDATA4DDATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDATA0DDATA0 0x000000C5UL /**< Mode SELDATA0DDATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDATA1DDATA0 0x000000C6UL /**< Mode SELDATA1DDATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDATA2DDATA0 0x000000C7UL /**< Mode SELDATA2DDATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA1 0x000000C8UL /**< Mode SELDDATA0DDATA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA1 0x000000C9UL /**< Mode SELDDATA1DDATA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA1 0x000000CAUL /**< Mode SELDDATA2DDATA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA1 0x000000CBUL /**< Mode SELDDATA3DDATA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA1 0x000000CCUL /**< Mode SELDDATA4DDATA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDATA0DDATA1 0x000000CDUL /**< Mode SELDATA0DDATA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDATA1DDATA1 0x000000CEUL /**< Mode SELDATA1DDATA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDATA2DDATA1 0x000000CFUL /**< Mode SELDATA2DDATA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA2 0x000000D0UL /**< Mode SELDDATA0DDATA2 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA2 0x000000D1UL /**< Mode SELDDATA1DDATA2 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA2 0x000000D2UL /**< Mode SELDDATA2DDATA2 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA2 0x000000D3UL /**< Mode SELDDATA3DDATA2 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA2 0x000000D4UL /**< Mode SELDDATA4DDATA2 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDATA0DDATA2 0x000000D5UL /**< Mode SELDATA0DDATA2 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDATA1DDATA2 0x000000D6UL /**< Mode SELDATA1DDATA2 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDATA2DDATA2 0x000000D7UL /**< Mode SELDATA2DDATA2 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA3 0x000000D8UL /**< Mode SELDDATA0DDATA3 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA3 0x000000D9UL /**< Mode SELDDATA1DDATA3 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA3 0x000000DAUL /**< Mode SELDDATA2DDATA3 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA3 0x000000DBUL /**< Mode SELDDATA3DDATA3 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA3 0x000000DCUL /**< Mode SELDDATA4DDATA3 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDATA0DDATA3 0x000000DDUL /**< Mode SELDATA0DDATA3 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDATA1DDATA3 0x000000DEUL /**< Mode SELDATA1DDATA3 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDATA2DDATA3 0x000000DFUL /**< Mode SELDATA2DDATA3 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA4 0x000000E0UL /**< Mode SELDDATA0DDATA4 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA4 0x000000E1UL /**< Mode SELDDATA1DDATA4 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA4 0x000000E2UL /**< Mode SELDDATA2DDATA4 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA4 0x000000E3UL /**< Mode SELDDATA3DDATA4 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA4 0x000000E4UL /**< Mode SELDDATA4DDATA4 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDATA0DDATA4 0x000000E5UL /**< Mode SELDATA0DDATA4 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDATA1DDATA4 0x000000E6UL /**< Mode SELDATA1DDATA4 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDATA2DDATA4 0x000000E7UL /**< Mode SELDATA2DDATA4 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA0DATA0 0x000000E8UL /**< Mode SELDDATA0DATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA1DATA0 0x000000E9UL /**< Mode SELDDATA1DATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA2DATA0 0x000000EAUL /**< Mode SELDDATA2DATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA3DATA0 0x000000EBUL /**< Mode SELDDATA3DATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA4DATA0 0x000000ECUL /**< Mode SELDDATA4DATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDATA0DATA0 0x000000EDUL /**< Mode SELDATA0DATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDATA1DATA0 0x000000EEUL /**< Mode SELDATA1DATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDATA2DATA0 0x000000EFUL /**< Mode SELDATA2DATA0 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA0DATA1 0x000000F0UL /**< Mode SELDDATA0DATA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA1DATA1 0x000000F1UL /**< Mode SELDDATA1DATA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA2DATA1 0x000000F2UL /**< Mode SELDDATA2DATA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA3DATA1 0x000000F3UL /**< Mode SELDDATA3DATA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDDATA4DATA1 0x000000F4UL /**< Mode SELDDATA4DATA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDATA0DATA1 0x000000F5UL /**< Mode SELDATA0DATA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDATA1DATA1 0x000000F6UL /**< Mode SELDATA1DATA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_SELDATA2DATA1 0x000000F7UL /**< Mode SELDATA2DATA1 for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_EXECIFA 0x000000F8UL /**< Mode EXECIFA for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_EXECIFB 0x000000F9UL /**< Mode EXECIFB for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_EXECIFNLAST 0x000000FAUL /**< Mode EXECIFNLAST for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_EXECIFLAST 0x000000FBUL /**< Mode EXECIFLAST for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_EXECIFCARRY 0x000000FCUL /**< Mode EXECIFCARRY for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_EXECIFNCARRY 0x000000FDUL /**< Mode EXECIFNCARRY for CRYPTO_CMD */
-#define _CRYPTO_CMD_INSTR_EXECALWAYS 0x000000FEUL /**< Mode EXECALWAYS for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DEFAULT (_CRYPTO_CMD_INSTR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_END (_CRYPTO_CMD_INSTR_END << 0) /**< Shifted mode END for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_EXEC (_CRYPTO_CMD_INSTR_EXEC << 0) /**< Shifted mode EXEC for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA1INC (_CRYPTO_CMD_INSTR_DATA1INC << 0) /**< Shifted mode DATA1INC for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA1INCCLR (_CRYPTO_CMD_INSTR_DATA1INCCLR << 0) /**< Shifted mode DATA1INCCLR for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_AESENC (_CRYPTO_CMD_INSTR_AESENC << 0) /**< Shifted mode AESENC for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_AESDEC (_CRYPTO_CMD_INSTR_AESDEC << 0) /**< Shifted mode AESDEC for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SHA (_CRYPTO_CMD_INSTR_SHA << 0) /**< Shifted mode SHA for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_ADD (_CRYPTO_CMD_INSTR_ADD << 0) /**< Shifted mode ADD for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_ADDC (_CRYPTO_CMD_INSTR_ADDC << 0) /**< Shifted mode ADDC for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_MADD (_CRYPTO_CMD_INSTR_MADD << 0) /**< Shifted mode MADD for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_MADD32 (_CRYPTO_CMD_INSTR_MADD32 << 0) /**< Shifted mode MADD32 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SUB (_CRYPTO_CMD_INSTR_SUB << 0) /**< Shifted mode SUB for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SUBC (_CRYPTO_CMD_INSTR_SUBC << 0) /**< Shifted mode SUBC for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_MSUB (_CRYPTO_CMD_INSTR_MSUB << 0) /**< Shifted mode MSUB for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_MUL (_CRYPTO_CMD_INSTR_MUL << 0) /**< Shifted mode MUL for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_MULC (_CRYPTO_CMD_INSTR_MULC << 0) /**< Shifted mode MULC for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_MMUL (_CRYPTO_CMD_INSTR_MMUL << 0) /**< Shifted mode MMUL for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_MULO (_CRYPTO_CMD_INSTR_MULO << 0) /**< Shifted mode MULO for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SHL (_CRYPTO_CMD_INSTR_SHL << 0) /**< Shifted mode SHL for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SHLC (_CRYPTO_CMD_INSTR_SHLC << 0) /**< Shifted mode SHLC for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SHLB (_CRYPTO_CMD_INSTR_SHLB << 0) /**< Shifted mode SHLB for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SHL1 (_CRYPTO_CMD_INSTR_SHL1 << 0) /**< Shifted mode SHL1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SHR (_CRYPTO_CMD_INSTR_SHR << 0) /**< Shifted mode SHR for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SHRC (_CRYPTO_CMD_INSTR_SHRC << 0) /**< Shifted mode SHRC for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SHRB (_CRYPTO_CMD_INSTR_SHRB << 0) /**< Shifted mode SHRB for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SHR1 (_CRYPTO_CMD_INSTR_SHR1 << 0) /**< Shifted mode SHR1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_ADDO (_CRYPTO_CMD_INSTR_ADDO << 0) /**< Shifted mode ADDO for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_ADDIC (_CRYPTO_CMD_INSTR_ADDIC << 0) /**< Shifted mode ADDIC for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_CLR (_CRYPTO_CMD_INSTR_CLR << 0) /**< Shifted mode CLR for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_XOR (_CRYPTO_CMD_INSTR_XOR << 0) /**< Shifted mode XOR for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_INV (_CRYPTO_CMD_INSTR_INV << 0) /**< Shifted mode INV for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_CSET (_CRYPTO_CMD_INSTR_CSET << 0) /**< Shifted mode CSET for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_CCLR (_CRYPTO_CMD_INSTR_CCLR << 0) /**< Shifted mode CCLR for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_BBSWAP128 (_CRYPTO_CMD_INSTR_BBSWAP128 << 0) /**< Shifted mode BBSWAP128 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_INC (_CRYPTO_CMD_INSTR_INC << 0) /**< Shifted mode INC for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DEC (_CRYPTO_CMD_INSTR_DEC << 0) /**< Shifted mode DEC for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SHRA (_CRYPTO_CMD_INSTR_SHRA << 0) /**< Shifted mode SHRA for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA0TODATA0 (_CRYPTO_CMD_INSTR_DATA0TODATA0 << 0) /**< Shifted mode DATA0TODATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA0TODATA0XOR (_CRYPTO_CMD_INSTR_DATA0TODATA0XOR << 0) /**< Shifted mode DATA0TODATA0XOR for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA0TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA0TODATA0XORLEN << 0) /**< Shifted mode DATA0TODATA0XORLEN for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA0TODATA1 (_CRYPTO_CMD_INSTR_DATA0TODATA1 << 0) /**< Shifted mode DATA0TODATA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA0TODATA2 (_CRYPTO_CMD_INSTR_DATA0TODATA2 << 0) /**< Shifted mode DATA0TODATA2 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA0TODATA3 (_CRYPTO_CMD_INSTR_DATA0TODATA3 << 0) /**< Shifted mode DATA0TODATA3 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA1TODATA0 (_CRYPTO_CMD_INSTR_DATA1TODATA0 << 0) /**< Shifted mode DATA1TODATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA1TODATA0XOR (_CRYPTO_CMD_INSTR_DATA1TODATA0XOR << 0) /**< Shifted mode DATA1TODATA0XOR for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA1TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA1TODATA0XORLEN << 0) /**< Shifted mode DATA1TODATA0XORLEN for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA1TODATA2 (_CRYPTO_CMD_INSTR_DATA1TODATA2 << 0) /**< Shifted mode DATA1TODATA2 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA1TODATA3 (_CRYPTO_CMD_INSTR_DATA1TODATA3 << 0) /**< Shifted mode DATA1TODATA3 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA2TODATA0 (_CRYPTO_CMD_INSTR_DATA2TODATA0 << 0) /**< Shifted mode DATA2TODATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA2TODATA0XOR (_CRYPTO_CMD_INSTR_DATA2TODATA0XOR << 0) /**< Shifted mode DATA2TODATA0XOR for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA2TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA2TODATA0XORLEN << 0) /**< Shifted mode DATA2TODATA0XORLEN for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA2TODATA1 (_CRYPTO_CMD_INSTR_DATA2TODATA1 << 0) /**< Shifted mode DATA2TODATA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA2TODATA3 (_CRYPTO_CMD_INSTR_DATA2TODATA3 << 0) /**< Shifted mode DATA2TODATA3 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA3TODATA0 (_CRYPTO_CMD_INSTR_DATA3TODATA0 << 0) /**< Shifted mode DATA3TODATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA3TODATA0XOR (_CRYPTO_CMD_INSTR_DATA3TODATA0XOR << 0) /**< Shifted mode DATA3TODATA0XOR for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA3TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA3TODATA0XORLEN << 0) /**< Shifted mode DATA3TODATA0XORLEN for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA3TODATA1 (_CRYPTO_CMD_INSTR_DATA3TODATA1 << 0) /**< Shifted mode DATA3TODATA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA3TODATA2 (_CRYPTO_CMD_INSTR_DATA3TODATA2 << 0) /**< Shifted mode DATA3TODATA2 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATATODMA0 (_CRYPTO_CMD_INSTR_DATATODMA0 << 0) /**< Shifted mode DATATODMA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA0TOBUF (_CRYPTO_CMD_INSTR_DATA0TOBUF << 0) /**< Shifted mode DATA0TOBUF for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA0TOBUFXOR (_CRYPTO_CMD_INSTR_DATA0TOBUFXOR << 0) /**< Shifted mode DATA0TOBUFXOR for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATATODMA1 (_CRYPTO_CMD_INSTR_DATATODMA1 << 0) /**< Shifted mode DATATODMA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA1TOBUF (_CRYPTO_CMD_INSTR_DATA1TOBUF << 0) /**< Shifted mode DATA1TOBUF for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA1TOBUFXOR (_CRYPTO_CMD_INSTR_DATA1TOBUFXOR << 0) /**< Shifted mode DATA1TOBUFXOR for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DMA0TODATA (_CRYPTO_CMD_INSTR_DMA0TODATA << 0) /**< Shifted mode DMA0TODATA for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DMA0TODATAXOR (_CRYPTO_CMD_INSTR_DMA0TODATAXOR << 0) /**< Shifted mode DMA0TODATAXOR for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DMA1TODATA (_CRYPTO_CMD_INSTR_DMA1TODATA << 0) /**< Shifted mode DMA1TODATA for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_BUFTODATA0 (_CRYPTO_CMD_INSTR_BUFTODATA0 << 0) /**< Shifted mode BUFTODATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_BUFTODATA0XOR (_CRYPTO_CMD_INSTR_BUFTODATA0XOR << 0) /**< Shifted mode BUFTODATA0XOR for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_BUFTODATA1 (_CRYPTO_CMD_INSTR_BUFTODATA1 << 0) /**< Shifted mode BUFTODATA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA0TODDATA1 (_CRYPTO_CMD_INSTR_DDATA0TODDATA1 << 0) /**< Shifted mode DDATA0TODDATA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA0TODDATA2 (_CRYPTO_CMD_INSTR_DDATA0TODDATA2 << 0) /**< Shifted mode DDATA0TODDATA2 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA0TODDATA3 (_CRYPTO_CMD_INSTR_DDATA0TODDATA3 << 0) /**< Shifted mode DDATA0TODDATA3 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA0TODDATA4 (_CRYPTO_CMD_INSTR_DDATA0TODDATA4 << 0) /**< Shifted mode DDATA0TODDATA4 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA0LTODATA0 (_CRYPTO_CMD_INSTR_DDATA0LTODATA0 << 0) /**< Shifted mode DDATA0LTODATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA0HTODATA1 (_CRYPTO_CMD_INSTR_DDATA0HTODATA1 << 0) /**< Shifted mode DDATA0HTODATA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA0LTODATA2 (_CRYPTO_CMD_INSTR_DDATA0LTODATA2 << 0) /**< Shifted mode DDATA0LTODATA2 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA1TODDATA0 (_CRYPTO_CMD_INSTR_DDATA1TODDATA0 << 0) /**< Shifted mode DDATA1TODDATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA1TODDATA2 (_CRYPTO_CMD_INSTR_DDATA1TODDATA2 << 0) /**< Shifted mode DDATA1TODDATA2 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA1TODDATA3 (_CRYPTO_CMD_INSTR_DDATA1TODDATA3 << 0) /**< Shifted mode DDATA1TODDATA3 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA1TODDATA4 (_CRYPTO_CMD_INSTR_DDATA1TODDATA4 << 0) /**< Shifted mode DDATA1TODDATA4 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA1LTODATA0 (_CRYPTO_CMD_INSTR_DDATA1LTODATA0 << 0) /**< Shifted mode DDATA1LTODATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA1HTODATA1 (_CRYPTO_CMD_INSTR_DDATA1HTODATA1 << 0) /**< Shifted mode DDATA1HTODATA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA1LTODATA2 (_CRYPTO_CMD_INSTR_DDATA1LTODATA2 << 0) /**< Shifted mode DDATA1LTODATA2 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA2TODDATA0 (_CRYPTO_CMD_INSTR_DDATA2TODDATA0 << 0) /**< Shifted mode DDATA2TODDATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA2TODDATA1 (_CRYPTO_CMD_INSTR_DDATA2TODDATA1 << 0) /**< Shifted mode DDATA2TODDATA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA2TODDATA3 (_CRYPTO_CMD_INSTR_DDATA2TODDATA3 << 0) /**< Shifted mode DDATA2TODDATA3 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA2TODDATA4 (_CRYPTO_CMD_INSTR_DDATA2TODDATA4 << 0) /**< Shifted mode DDATA2TODDATA4 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA2LTODATA2 (_CRYPTO_CMD_INSTR_DDATA2LTODATA2 << 0) /**< Shifted mode DDATA2LTODATA2 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA3TODDATA0 (_CRYPTO_CMD_INSTR_DDATA3TODDATA0 << 0) /**< Shifted mode DDATA3TODDATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA3TODDATA1 (_CRYPTO_CMD_INSTR_DDATA3TODDATA1 << 0) /**< Shifted mode DDATA3TODDATA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA3TODDATA2 (_CRYPTO_CMD_INSTR_DDATA3TODDATA2 << 0) /**< Shifted mode DDATA3TODDATA2 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA3TODDATA4 (_CRYPTO_CMD_INSTR_DDATA3TODDATA4 << 0) /**< Shifted mode DDATA3TODDATA4 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA3LTODATA0 (_CRYPTO_CMD_INSTR_DDATA3LTODATA0 << 0) /**< Shifted mode DDATA3LTODATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA3HTODATA1 (_CRYPTO_CMD_INSTR_DDATA3HTODATA1 << 0) /**< Shifted mode DDATA3HTODATA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA4TODDATA0 (_CRYPTO_CMD_INSTR_DDATA4TODDATA0 << 0) /**< Shifted mode DDATA4TODDATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA4TODDATA1 (_CRYPTO_CMD_INSTR_DDATA4TODDATA1 << 0) /**< Shifted mode DDATA4TODDATA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA4TODDATA2 (_CRYPTO_CMD_INSTR_DDATA4TODDATA2 << 0) /**< Shifted mode DDATA4TODDATA2 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA4TODDATA3 (_CRYPTO_CMD_INSTR_DDATA4TODDATA3 << 0) /**< Shifted mode DDATA4TODDATA3 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA4LTODATA0 (_CRYPTO_CMD_INSTR_DDATA4LTODATA0 << 0) /**< Shifted mode DDATA4LTODATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA4HTODATA1 (_CRYPTO_CMD_INSTR_DDATA4HTODATA1 << 0) /**< Shifted mode DDATA4HTODATA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DDATA4LTODATA2 (_CRYPTO_CMD_INSTR_DDATA4LTODATA2 << 0) /**< Shifted mode DDATA4LTODATA2 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA0TODDATA0 (_CRYPTO_CMD_INSTR_DATA0TODDATA0 << 0) /**< Shifted mode DATA0TODDATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA0TODDATA1 (_CRYPTO_CMD_INSTR_DATA0TODDATA1 << 0) /**< Shifted mode DATA0TODDATA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA1TODDATA0 (_CRYPTO_CMD_INSTR_DATA1TODDATA0 << 0) /**< Shifted mode DATA1TODDATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA1TODDATA1 (_CRYPTO_CMD_INSTR_DATA1TODDATA1 << 0) /**< Shifted mode DATA1TODDATA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA2TODDATA0 (_CRYPTO_CMD_INSTR_DATA2TODDATA0 << 0) /**< Shifted mode DATA2TODDATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA2TODDATA1 (_CRYPTO_CMD_INSTR_DATA2TODDATA1 << 0) /**< Shifted mode DATA2TODDATA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_DATA2TODDATA2 (_CRYPTO_CMD_INSTR_DATA2TODDATA2 << 0) /**< Shifted mode DATA2TODDATA2 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA0DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA0 << 0) /**< Shifted mode SELDDATA0DDATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA1DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA0 << 0) /**< Shifted mode SELDDATA1DDATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA2DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA0 << 0) /**< Shifted mode SELDDATA2DDATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA3DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA0 << 0) /**< Shifted mode SELDDATA3DDATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA4DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA0 << 0) /**< Shifted mode SELDDATA4DDATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDATA0DDATA0 (_CRYPTO_CMD_INSTR_SELDATA0DDATA0 << 0) /**< Shifted mode SELDATA0DDATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDATA1DDATA0 (_CRYPTO_CMD_INSTR_SELDATA1DDATA0 << 0) /**< Shifted mode SELDATA1DDATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDATA2DDATA0 (_CRYPTO_CMD_INSTR_SELDATA2DDATA0 << 0) /**< Shifted mode SELDATA2DDATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA0DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA1 << 0) /**< Shifted mode SELDDATA0DDATA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA1DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA1 << 0) /**< Shifted mode SELDDATA1DDATA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA2DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA1 << 0) /**< Shifted mode SELDDATA2DDATA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA3DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA1 << 0) /**< Shifted mode SELDDATA3DDATA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA4DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA1 << 0) /**< Shifted mode SELDDATA4DDATA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDATA0DDATA1 (_CRYPTO_CMD_INSTR_SELDATA0DDATA1 << 0) /**< Shifted mode SELDATA0DDATA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDATA1DDATA1 (_CRYPTO_CMD_INSTR_SELDATA1DDATA1 << 0) /**< Shifted mode SELDATA1DDATA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDATA2DDATA1 (_CRYPTO_CMD_INSTR_SELDATA2DDATA1 << 0) /**< Shifted mode SELDATA2DDATA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA0DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA2 << 0) /**< Shifted mode SELDDATA0DDATA2 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA1DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA2 << 0) /**< Shifted mode SELDDATA1DDATA2 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA2DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA2 << 0) /**< Shifted mode SELDDATA2DDATA2 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA3DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA2 << 0) /**< Shifted mode SELDDATA3DDATA2 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA4DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA2 << 0) /**< Shifted mode SELDDATA4DDATA2 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDATA0DDATA2 (_CRYPTO_CMD_INSTR_SELDATA0DDATA2 << 0) /**< Shifted mode SELDATA0DDATA2 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDATA1DDATA2 (_CRYPTO_CMD_INSTR_SELDATA1DDATA2 << 0) /**< Shifted mode SELDATA1DDATA2 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDATA2DDATA2 (_CRYPTO_CMD_INSTR_SELDATA2DDATA2 << 0) /**< Shifted mode SELDATA2DDATA2 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA0DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA3 << 0) /**< Shifted mode SELDDATA0DDATA3 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA1DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA3 << 0) /**< Shifted mode SELDDATA1DDATA3 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA2DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA3 << 0) /**< Shifted mode SELDDATA2DDATA3 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA3DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA3 << 0) /**< Shifted mode SELDDATA3DDATA3 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA4DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA3 << 0) /**< Shifted mode SELDDATA4DDATA3 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDATA0DDATA3 (_CRYPTO_CMD_INSTR_SELDATA0DDATA3 << 0) /**< Shifted mode SELDATA0DDATA3 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDATA1DDATA3 (_CRYPTO_CMD_INSTR_SELDATA1DDATA3 << 0) /**< Shifted mode SELDATA1DDATA3 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDATA2DDATA3 (_CRYPTO_CMD_INSTR_SELDATA2DDATA3 << 0) /**< Shifted mode SELDATA2DDATA3 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA0DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA4 << 0) /**< Shifted mode SELDDATA0DDATA4 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA1DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA4 << 0) /**< Shifted mode SELDDATA1DDATA4 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA2DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA4 << 0) /**< Shifted mode SELDDATA2DDATA4 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA3DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA4 << 0) /**< Shifted mode SELDDATA3DDATA4 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA4DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA4 << 0) /**< Shifted mode SELDDATA4DDATA4 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDATA0DDATA4 (_CRYPTO_CMD_INSTR_SELDATA0DDATA4 << 0) /**< Shifted mode SELDATA0DDATA4 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDATA1DDATA4 (_CRYPTO_CMD_INSTR_SELDATA1DDATA4 << 0) /**< Shifted mode SELDATA1DDATA4 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDATA2DDATA4 (_CRYPTO_CMD_INSTR_SELDATA2DDATA4 << 0) /**< Shifted mode SELDATA2DDATA4 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA0DATA0 (_CRYPTO_CMD_INSTR_SELDDATA0DATA0 << 0) /**< Shifted mode SELDDATA0DATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA1DATA0 (_CRYPTO_CMD_INSTR_SELDDATA1DATA0 << 0) /**< Shifted mode SELDDATA1DATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA2DATA0 (_CRYPTO_CMD_INSTR_SELDDATA2DATA0 << 0) /**< Shifted mode SELDDATA2DATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA3DATA0 (_CRYPTO_CMD_INSTR_SELDDATA3DATA0 << 0) /**< Shifted mode SELDDATA3DATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA4DATA0 (_CRYPTO_CMD_INSTR_SELDDATA4DATA0 << 0) /**< Shifted mode SELDDATA4DATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDATA0DATA0 (_CRYPTO_CMD_INSTR_SELDATA0DATA0 << 0) /**< Shifted mode SELDATA0DATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDATA1DATA0 (_CRYPTO_CMD_INSTR_SELDATA1DATA0 << 0) /**< Shifted mode SELDATA1DATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDATA2DATA0 (_CRYPTO_CMD_INSTR_SELDATA2DATA0 << 0) /**< Shifted mode SELDATA2DATA0 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA0DATA1 (_CRYPTO_CMD_INSTR_SELDDATA0DATA1 << 0) /**< Shifted mode SELDDATA0DATA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA1DATA1 (_CRYPTO_CMD_INSTR_SELDDATA1DATA1 << 0) /**< Shifted mode SELDDATA1DATA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA2DATA1 (_CRYPTO_CMD_INSTR_SELDDATA2DATA1 << 0) /**< Shifted mode SELDDATA2DATA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA3DATA1 (_CRYPTO_CMD_INSTR_SELDDATA3DATA1 << 0) /**< Shifted mode SELDDATA3DATA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDDATA4DATA1 (_CRYPTO_CMD_INSTR_SELDDATA4DATA1 << 0) /**< Shifted mode SELDDATA4DATA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDATA0DATA1 (_CRYPTO_CMD_INSTR_SELDATA0DATA1 << 0) /**< Shifted mode SELDATA0DATA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDATA1DATA1 (_CRYPTO_CMD_INSTR_SELDATA1DATA1 << 0) /**< Shifted mode SELDATA1DATA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_SELDATA2DATA1 (_CRYPTO_CMD_INSTR_SELDATA2DATA1 << 0) /**< Shifted mode SELDATA2DATA1 for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_EXECIFA (_CRYPTO_CMD_INSTR_EXECIFA << 0) /**< Shifted mode EXECIFA for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_EXECIFB (_CRYPTO_CMD_INSTR_EXECIFB << 0) /**< Shifted mode EXECIFB for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_EXECIFNLAST (_CRYPTO_CMD_INSTR_EXECIFNLAST << 0) /**< Shifted mode EXECIFNLAST for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_EXECIFLAST (_CRYPTO_CMD_INSTR_EXECIFLAST << 0) /**< Shifted mode EXECIFLAST for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_EXECIFCARRY (_CRYPTO_CMD_INSTR_EXECIFCARRY << 0) /**< Shifted mode EXECIFCARRY for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_EXECIFNCARRY (_CRYPTO_CMD_INSTR_EXECIFNCARRY << 0) /**< Shifted mode EXECIFNCARRY for CRYPTO_CMD */
-#define CRYPTO_CMD_INSTR_EXECALWAYS (_CRYPTO_CMD_INSTR_EXECALWAYS << 0) /**< Shifted mode EXECALWAYS for CRYPTO_CMD */
-#define CRYPTO_CMD_SEQSTART (0x1UL << 9) /**< Encryption/Decryption SEQUENCE Start */
-#define _CRYPTO_CMD_SEQSTART_SHIFT 9 /**< Shift value for CRYPTO_SEQSTART */
-#define _CRYPTO_CMD_SEQSTART_MASK 0x200UL /**< Bit mask for CRYPTO_SEQSTART */
-#define _CRYPTO_CMD_SEQSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */
-#define CRYPTO_CMD_SEQSTART_DEFAULT (_CRYPTO_CMD_SEQSTART_DEFAULT << 9) /**< Shifted mode DEFAULT for CRYPTO_CMD */
-#define CRYPTO_CMD_SEQSTOP (0x1UL << 10) /**< Sequence Stop */
-#define _CRYPTO_CMD_SEQSTOP_SHIFT 10 /**< Shift value for CRYPTO_SEQSTOP */
-#define _CRYPTO_CMD_SEQSTOP_MASK 0x400UL /**< Bit mask for CRYPTO_SEQSTOP */
-#define _CRYPTO_CMD_SEQSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */
-#define CRYPTO_CMD_SEQSTOP_DEFAULT (_CRYPTO_CMD_SEQSTOP_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTO_CMD */
-#define CRYPTO_CMD_SEQSTEP (0x1UL << 11) /**< Sequence Step */
-#define _CRYPTO_CMD_SEQSTEP_SHIFT 11 /**< Shift value for CRYPTO_SEQSTEP */
-#define _CRYPTO_CMD_SEQSTEP_MASK 0x800UL /**< Bit mask for CRYPTO_SEQSTEP */
-#define _CRYPTO_CMD_SEQSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */
-#define CRYPTO_CMD_SEQSTEP_DEFAULT (_CRYPTO_CMD_SEQSTEP_DEFAULT << 11) /**< Shifted mode DEFAULT for CRYPTO_CMD */
-
-/* Bit fields for CRYPTO STATUS */
-#define _CRYPTO_STATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_STATUS */
-#define _CRYPTO_STATUS_MASK 0x00000007UL /**< Mask for CRYPTO_STATUS */
-#define CRYPTO_STATUS_SEQRUNNING (0x1UL << 0) /**< AES SEQUENCE Running */
-#define _CRYPTO_STATUS_SEQRUNNING_SHIFT 0 /**< Shift value for CRYPTO_SEQRUNNING */
-#define _CRYPTO_STATUS_SEQRUNNING_MASK 0x1UL /**< Bit mask for CRYPTO_SEQRUNNING */
-#define _CRYPTO_STATUS_SEQRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */
-#define CRYPTO_STATUS_SEQRUNNING_DEFAULT (_CRYPTO_STATUS_SEQRUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_STATUS */
-#define CRYPTO_STATUS_INSTRRUNNING (0x1UL << 1) /**< Action is Active */
-#define _CRYPTO_STATUS_INSTRRUNNING_SHIFT 1 /**< Shift value for CRYPTO_INSTRRUNNING */
-#define _CRYPTO_STATUS_INSTRRUNNING_MASK 0x2UL /**< Bit mask for CRYPTO_INSTRRUNNING */
-#define _CRYPTO_STATUS_INSTRRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */
-#define CRYPTO_STATUS_INSTRRUNNING_DEFAULT (_CRYPTO_STATUS_INSTRRUNNING_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_STATUS */
-#define CRYPTO_STATUS_DMAACTIVE (0x1UL << 2) /**< DMA Action is Active */
-#define _CRYPTO_STATUS_DMAACTIVE_SHIFT 2 /**< Shift value for CRYPTO_DMAACTIVE */
-#define _CRYPTO_STATUS_DMAACTIVE_MASK 0x4UL /**< Bit mask for CRYPTO_DMAACTIVE */
-#define _CRYPTO_STATUS_DMAACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */
-#define CRYPTO_STATUS_DMAACTIVE_DEFAULT (_CRYPTO_STATUS_DMAACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_STATUS */
-
-/* Bit fields for CRYPTO DSTATUS */
-#define _CRYPTO_DSTATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DSTATUS */
-#define _CRYPTO_DSTATUS_MASK 0x011F0F0FUL /**< Mask for CRYPTO_DSTATUS */
-#define _CRYPTO_DSTATUS_DATA0ZERO_SHIFT 0 /**< Shift value for CRYPTO_DATA0ZERO */
-#define _CRYPTO_DSTATUS_DATA0ZERO_MASK 0xFUL /**< Bit mask for CRYPTO_DATA0ZERO */
-#define _CRYPTO_DSTATUS_DATA0ZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */
-#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO0TO31 0x00000001UL /**< Mode ZERO0TO31 for CRYPTO_DSTATUS */
-#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO32TO63 0x00000002UL /**< Mode ZERO32TO63 for CRYPTO_DSTATUS */
-#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO64TO95 0x00000004UL /**< Mode ZERO64TO95 for CRYPTO_DSTATUS */
-#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO96TO127 0x00000008UL /**< Mode ZERO96TO127 for CRYPTO_DSTATUS */
-#define CRYPTO_DSTATUS_DATA0ZERO_DEFAULT (_CRYPTO_DSTATUS_DATA0ZERO_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */
-#define CRYPTO_DSTATUS_DATA0ZERO_ZERO0TO31 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO0TO31 << 0) /**< Shifted mode ZERO0TO31 for CRYPTO_DSTATUS */
-#define CRYPTO_DSTATUS_DATA0ZERO_ZERO32TO63 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO32TO63 << 0) /**< Shifted mode ZERO32TO63 for CRYPTO_DSTATUS */
-#define CRYPTO_DSTATUS_DATA0ZERO_ZERO64TO95 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO64TO95 << 0) /**< Shifted mode ZERO64TO95 for CRYPTO_DSTATUS */
-#define CRYPTO_DSTATUS_DATA0ZERO_ZERO96TO127 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO96TO127 << 0) /**< Shifted mode ZERO96TO127 for CRYPTO_DSTATUS */
-#define _CRYPTO_DSTATUS_DDATA0LSBS_SHIFT 8 /**< Shift value for CRYPTO_DDATA0LSBS */
-#define _CRYPTO_DSTATUS_DDATA0LSBS_MASK 0xF00UL /**< Bit mask for CRYPTO_DDATA0LSBS */
-#define _CRYPTO_DSTATUS_DDATA0LSBS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */
-#define CRYPTO_DSTATUS_DDATA0LSBS_DEFAULT (_CRYPTO_DSTATUS_DDATA0LSBS_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */
-#define _CRYPTO_DSTATUS_DDATA0MSBS_SHIFT 16 /**< Shift value for CRYPTO_DDATA0MSBS */
-#define _CRYPTO_DSTATUS_DDATA0MSBS_MASK 0xF0000UL /**< Bit mask for CRYPTO_DDATA0MSBS */
-#define _CRYPTO_DSTATUS_DDATA0MSBS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */
-#define CRYPTO_DSTATUS_DDATA0MSBS_DEFAULT (_CRYPTO_DSTATUS_DDATA0MSBS_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */
-#define CRYPTO_DSTATUS_DDATA1MSB (0x1UL << 20) /**< MSB in DDATA1 */
-#define _CRYPTO_DSTATUS_DDATA1MSB_SHIFT 20 /**< Shift value for CRYPTO_DDATA1MSB */
-#define _CRYPTO_DSTATUS_DDATA1MSB_MASK 0x100000UL /**< Bit mask for CRYPTO_DDATA1MSB */
-#define _CRYPTO_DSTATUS_DDATA1MSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */
-#define CRYPTO_DSTATUS_DDATA1MSB_DEFAULT (_CRYPTO_DSTATUS_DDATA1MSB_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */
-#define CRYPTO_DSTATUS_CARRY (0x1UL << 24) /**< Carry From Arithmetic Operation */
-#define _CRYPTO_DSTATUS_CARRY_SHIFT 24 /**< Shift value for CRYPTO_CARRY */
-#define _CRYPTO_DSTATUS_CARRY_MASK 0x1000000UL /**< Bit mask for CRYPTO_CARRY */
-#define _CRYPTO_DSTATUS_CARRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */
-#define CRYPTO_DSTATUS_CARRY_DEFAULT (_CRYPTO_DSTATUS_CARRY_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */
-
-/* Bit fields for CRYPTO CSTATUS */
-#define _CRYPTO_CSTATUS_RESETVALUE 0x00000201UL /**< Default value for CRYPTO_CSTATUS */
-#define _CRYPTO_CSTATUS_MASK 0x01F30707UL /**< Mask for CRYPTO_CSTATUS */
-#define _CRYPTO_CSTATUS_V0_SHIFT 0 /**< Shift value for CRYPTO_V0 */
-#define _CRYPTO_CSTATUS_V0_MASK 0x7UL /**< Bit mask for CRYPTO_V0 */
-#define _CRYPTO_CSTATUS_V0_DDATA0 0x00000000UL /**< Mode DDATA0 for CRYPTO_CSTATUS */
-#define _CRYPTO_CSTATUS_V0_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTO_CSTATUS */
-#define _CRYPTO_CSTATUS_V0_DDATA1 0x00000001UL /**< Mode DDATA1 for CRYPTO_CSTATUS */
-#define _CRYPTO_CSTATUS_V0_DDATA2 0x00000002UL /**< Mode DDATA2 for CRYPTO_CSTATUS */
-#define _CRYPTO_CSTATUS_V0_DDATA3 0x00000003UL /**< Mode DDATA3 for CRYPTO_CSTATUS */
-#define _CRYPTO_CSTATUS_V0_DDATA4 0x00000004UL /**< Mode DDATA4 for CRYPTO_CSTATUS */
-#define _CRYPTO_CSTATUS_V0_DATA0 0x00000005UL /**< Mode DATA0 for CRYPTO_CSTATUS */
-#define _CRYPTO_CSTATUS_V0_DATA1 0x00000006UL /**< Mode DATA1 for CRYPTO_CSTATUS */
-#define _CRYPTO_CSTATUS_V0_DATA2 0x00000007UL /**< Mode DATA2 for CRYPTO_CSTATUS */
-#define CRYPTO_CSTATUS_V0_DDATA0 (_CRYPTO_CSTATUS_V0_DDATA0 << 0) /**< Shifted mode DDATA0 for CRYPTO_CSTATUS */
-#define CRYPTO_CSTATUS_V0_DEFAULT (_CRYPTO_CSTATUS_V0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */
-#define CRYPTO_CSTATUS_V0_DDATA1 (_CRYPTO_CSTATUS_V0_DDATA1 << 0) /**< Shifted mode DDATA1 for CRYPTO_CSTATUS */
-#define CRYPTO_CSTATUS_V0_DDATA2 (_CRYPTO_CSTATUS_V0_DDATA2 << 0) /**< Shifted mode DDATA2 for CRYPTO_CSTATUS */
-#define CRYPTO_CSTATUS_V0_DDATA3 (_CRYPTO_CSTATUS_V0_DDATA3 << 0) /**< Shifted mode DDATA3 for CRYPTO_CSTATUS */
-#define CRYPTO_CSTATUS_V0_DDATA4 (_CRYPTO_CSTATUS_V0_DDATA4 << 0) /**< Shifted mode DDATA4 for CRYPTO_CSTATUS */
-#define CRYPTO_CSTATUS_V0_DATA0 (_CRYPTO_CSTATUS_V0_DATA0 << 0) /**< Shifted mode DATA0 for CRYPTO_CSTATUS */
-#define CRYPTO_CSTATUS_V0_DATA1 (_CRYPTO_CSTATUS_V0_DATA1 << 0) /**< Shifted mode DATA1 for CRYPTO_CSTATUS */
-#define CRYPTO_CSTATUS_V0_DATA2 (_CRYPTO_CSTATUS_V0_DATA2 << 0) /**< Shifted mode DATA2 for CRYPTO_CSTATUS */
-#define _CRYPTO_CSTATUS_V1_SHIFT 8 /**< Shift value for CRYPTO_V1 */
-#define _CRYPTO_CSTATUS_V1_MASK 0x700UL /**< Bit mask for CRYPTO_V1 */
-#define _CRYPTO_CSTATUS_V1_DDATA0 0x00000000UL /**< Mode DDATA0 for CRYPTO_CSTATUS */
-#define _CRYPTO_CSTATUS_V1_DDATA1 0x00000001UL /**< Mode DDATA1 for CRYPTO_CSTATUS */
-#define _CRYPTO_CSTATUS_V1_DEFAULT 0x00000002UL /**< Mode DEFAULT for CRYPTO_CSTATUS */
-#define _CRYPTO_CSTATUS_V1_DDATA2 0x00000002UL /**< Mode DDATA2 for CRYPTO_CSTATUS */
-#define _CRYPTO_CSTATUS_V1_DDATA3 0x00000003UL /**< Mode DDATA3 for CRYPTO_CSTATUS */
-#define _CRYPTO_CSTATUS_V1_DDATA4 0x00000004UL /**< Mode DDATA4 for CRYPTO_CSTATUS */
-#define _CRYPTO_CSTATUS_V1_DATA0 0x00000005UL /**< Mode DATA0 for CRYPTO_CSTATUS */
-#define _CRYPTO_CSTATUS_V1_DATA1 0x00000006UL /**< Mode DATA1 for CRYPTO_CSTATUS */
-#define _CRYPTO_CSTATUS_V1_DATA2 0x00000007UL /**< Mode DATA2 for CRYPTO_CSTATUS */
-#define CRYPTO_CSTATUS_V1_DDATA0 (_CRYPTO_CSTATUS_V1_DDATA0 << 8) /**< Shifted mode DDATA0 for CRYPTO_CSTATUS */
-#define CRYPTO_CSTATUS_V1_DDATA1 (_CRYPTO_CSTATUS_V1_DDATA1 << 8) /**< Shifted mode DDATA1 for CRYPTO_CSTATUS */
-#define CRYPTO_CSTATUS_V1_DEFAULT (_CRYPTO_CSTATUS_V1_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */
-#define CRYPTO_CSTATUS_V1_DDATA2 (_CRYPTO_CSTATUS_V1_DDATA2 << 8) /**< Shifted mode DDATA2 for CRYPTO_CSTATUS */
-#define CRYPTO_CSTATUS_V1_DDATA3 (_CRYPTO_CSTATUS_V1_DDATA3 << 8) /**< Shifted mode DDATA3 for CRYPTO_CSTATUS */
-#define CRYPTO_CSTATUS_V1_DDATA4 (_CRYPTO_CSTATUS_V1_DDATA4 << 8) /**< Shifted mode DDATA4 for CRYPTO_CSTATUS */
-#define CRYPTO_CSTATUS_V1_DATA0 (_CRYPTO_CSTATUS_V1_DATA0 << 8) /**< Shifted mode DATA0 for CRYPTO_CSTATUS */
-#define CRYPTO_CSTATUS_V1_DATA1 (_CRYPTO_CSTATUS_V1_DATA1 << 8) /**< Shifted mode DATA1 for CRYPTO_CSTATUS */
-#define CRYPTO_CSTATUS_V1_DATA2 (_CRYPTO_CSTATUS_V1_DATA2 << 8) /**< Shifted mode DATA2 for CRYPTO_CSTATUS */
-#define CRYPTO_CSTATUS_SEQPART (0x1UL << 16) /**< Sequence Part */
-#define _CRYPTO_CSTATUS_SEQPART_SHIFT 16 /**< Shift value for CRYPTO_SEQPART */
-#define _CRYPTO_CSTATUS_SEQPART_MASK 0x10000UL /**< Bit mask for CRYPTO_SEQPART */
-#define _CRYPTO_CSTATUS_SEQPART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CSTATUS */
-#define _CRYPTO_CSTATUS_SEQPART_SEQA 0x00000000UL /**< Mode SEQA for CRYPTO_CSTATUS */
-#define _CRYPTO_CSTATUS_SEQPART_SEQB 0x00000001UL /**< Mode SEQB for CRYPTO_CSTATUS */
-#define CRYPTO_CSTATUS_SEQPART_DEFAULT (_CRYPTO_CSTATUS_SEQPART_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */
-#define CRYPTO_CSTATUS_SEQPART_SEQA (_CRYPTO_CSTATUS_SEQPART_SEQA << 16) /**< Shifted mode SEQA for CRYPTO_CSTATUS */
-#define CRYPTO_CSTATUS_SEQPART_SEQB (_CRYPTO_CSTATUS_SEQPART_SEQB << 16) /**< Shifted mode SEQB for CRYPTO_CSTATUS */
-#define CRYPTO_CSTATUS_SEQSKIP (0x1UL << 17) /**< Sequence Skip Next Instruction */
-#define _CRYPTO_CSTATUS_SEQSKIP_SHIFT 17 /**< Shift value for CRYPTO_SEQSKIP */
-#define _CRYPTO_CSTATUS_SEQSKIP_MASK 0x20000UL /**< Bit mask for CRYPTO_SEQSKIP */
-#define _CRYPTO_CSTATUS_SEQSKIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CSTATUS */
-#define CRYPTO_CSTATUS_SEQSKIP_DEFAULT (_CRYPTO_CSTATUS_SEQSKIP_DEFAULT << 17) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */
-#define _CRYPTO_CSTATUS_SEQIP_SHIFT 20 /**< Shift value for CRYPTO_SEQIP */
-#define _CRYPTO_CSTATUS_SEQIP_MASK 0x1F00000UL /**< Bit mask for CRYPTO_SEQIP */
-#define _CRYPTO_CSTATUS_SEQIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CSTATUS */
-#define CRYPTO_CSTATUS_SEQIP_DEFAULT (_CRYPTO_CSTATUS_SEQIP_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */
-
-/* Bit fields for CRYPTO KEY */
-#define _CRYPTO_KEY_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_KEY */
-#define _CRYPTO_KEY_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_KEY */
-#define _CRYPTO_KEY_KEY_SHIFT 0 /**< Shift value for CRYPTO_KEY */
-#define _CRYPTO_KEY_KEY_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_KEY */
-#define _CRYPTO_KEY_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_KEY */
-#define CRYPTO_KEY_KEY_DEFAULT (_CRYPTO_KEY_KEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_KEY */
-
-/* Bit fields for CRYPTO KEYBUF */
-#define _CRYPTO_KEYBUF_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_KEYBUF */
-#define _CRYPTO_KEYBUF_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_KEYBUF */
-#define _CRYPTO_KEYBUF_KEYBUF_SHIFT 0 /**< Shift value for CRYPTO_KEYBUF */
-#define _CRYPTO_KEYBUF_KEYBUF_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_KEYBUF */
-#define _CRYPTO_KEYBUF_KEYBUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_KEYBUF */
-#define CRYPTO_KEYBUF_KEYBUF_DEFAULT (_CRYPTO_KEYBUF_KEYBUF_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_KEYBUF */
-
-/* Bit fields for CRYPTO SEQCTRL */
-#define _CRYPTO_SEQCTRL_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQCTRL */
-#define _CRYPTO_SEQCTRL_MASK 0xBF303FFFUL /**< Mask for CRYPTO_SEQCTRL */
-#define _CRYPTO_SEQCTRL_LENGTHA_SHIFT 0 /**< Shift value for CRYPTO_LENGTHA */
-#define _CRYPTO_SEQCTRL_LENGTHA_MASK 0x3FFFUL /**< Bit mask for CRYPTO_LENGTHA */
-#define _CRYPTO_SEQCTRL_LENGTHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */
-#define CRYPTO_SEQCTRL_LENGTHA_DEFAULT (_CRYPTO_SEQCTRL_LENGTHA_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */
-#define _CRYPTO_SEQCTRL_BLOCKSIZE_SHIFT 20 /**< Shift value for CRYPTO_BLOCKSIZE */
-#define _CRYPTO_SEQCTRL_BLOCKSIZE_MASK 0x300000UL /**< Bit mask for CRYPTO_BLOCKSIZE */
-#define _CRYPTO_SEQCTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */
-#define _CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES 0x00000000UL /**< Mode 16BYTES for CRYPTO_SEQCTRL */
-#define _CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES 0x00000001UL /**< Mode 32BYTES for CRYPTO_SEQCTRL */
-#define _CRYPTO_SEQCTRL_BLOCKSIZE_64BYTES 0x00000002UL /**< Mode 64BYTES for CRYPTO_SEQCTRL */
-#define CRYPTO_SEQCTRL_BLOCKSIZE_DEFAULT (_CRYPTO_SEQCTRL_BLOCKSIZE_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */
-#define CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES (_CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES << 20) /**< Shifted mode 16BYTES for CRYPTO_SEQCTRL */
-#define CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES (_CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES << 20) /**< Shifted mode 32BYTES for CRYPTO_SEQCTRL */
-#define CRYPTO_SEQCTRL_BLOCKSIZE_64BYTES (_CRYPTO_SEQCTRL_BLOCKSIZE_64BYTES << 20) /**< Shifted mode 64BYTES for CRYPTO_SEQCTRL */
-#define _CRYPTO_SEQCTRL_DMA0SKIP_SHIFT 24 /**< Shift value for CRYPTO_DMA0SKIP */
-#define _CRYPTO_SEQCTRL_DMA0SKIP_MASK 0x3000000UL /**< Bit mask for CRYPTO_DMA0SKIP */
-#define _CRYPTO_SEQCTRL_DMA0SKIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */
-#define CRYPTO_SEQCTRL_DMA0SKIP_DEFAULT (_CRYPTO_SEQCTRL_DMA0SKIP_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */
-#define _CRYPTO_SEQCTRL_DMA1SKIP_SHIFT 26 /**< Shift value for CRYPTO_DMA1SKIP */
-#define _CRYPTO_SEQCTRL_DMA1SKIP_MASK 0xC000000UL /**< Bit mask for CRYPTO_DMA1SKIP */
-#define _CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */
-#define CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT (_CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT << 26) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */
-#define CRYPTO_SEQCTRL_DMA0PRESA (0x1UL << 28) /**< DMA0 Preserve a */
-#define _CRYPTO_SEQCTRL_DMA0PRESA_SHIFT 28 /**< Shift value for CRYPTO_DMA0PRESA */
-#define _CRYPTO_SEQCTRL_DMA0PRESA_MASK 0x10000000UL /**< Bit mask for CRYPTO_DMA0PRESA */
-#define _CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */
-#define CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT (_CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */
-#define CRYPTO_SEQCTRL_DMA1PRESA (0x1UL << 29) /**< DMA1 Preserve a */
-#define _CRYPTO_SEQCTRL_DMA1PRESA_SHIFT 29 /**< Shift value for CRYPTO_DMA1PRESA */
-#define _CRYPTO_SEQCTRL_DMA1PRESA_MASK 0x20000000UL /**< Bit mask for CRYPTO_DMA1PRESA */
-#define _CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */
-#define CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT (_CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */
-#define CRYPTO_SEQCTRL_HALT (0x1UL << 31) /**< Halt Sequence */
-#define _CRYPTO_SEQCTRL_HALT_SHIFT 31 /**< Shift value for CRYPTO_HALT */
-#define _CRYPTO_SEQCTRL_HALT_MASK 0x80000000UL /**< Bit mask for CRYPTO_HALT */
-#define _CRYPTO_SEQCTRL_HALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */
-#define CRYPTO_SEQCTRL_HALT_DEFAULT (_CRYPTO_SEQCTRL_HALT_DEFAULT << 31) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */
-
-/* Bit fields for CRYPTO SEQCTRLB */
-#define _CRYPTO_SEQCTRLB_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQCTRLB */
-#define _CRYPTO_SEQCTRLB_MASK 0x30003FFFUL /**< Mask for CRYPTO_SEQCTRLB */
-#define _CRYPTO_SEQCTRLB_LENGTHB_SHIFT 0 /**< Shift value for CRYPTO_LENGTHB */
-#define _CRYPTO_SEQCTRLB_LENGTHB_MASK 0x3FFFUL /**< Bit mask for CRYPTO_LENGTHB */
-#define _CRYPTO_SEQCTRLB_LENGTHB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRLB */
-#define CRYPTO_SEQCTRLB_LENGTHB_DEFAULT (_CRYPTO_SEQCTRLB_LENGTHB_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRLB */
-#define CRYPTO_SEQCTRLB_DMA0PRESB (0x1UL << 28) /**< DMA0 Preserve B */
-#define _CRYPTO_SEQCTRLB_DMA0PRESB_SHIFT 28 /**< Shift value for CRYPTO_DMA0PRESB */
-#define _CRYPTO_SEQCTRLB_DMA0PRESB_MASK 0x10000000UL /**< Bit mask for CRYPTO_DMA0PRESB */
-#define _CRYPTO_SEQCTRLB_DMA0PRESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRLB */
-#define CRYPTO_SEQCTRLB_DMA0PRESB_DEFAULT (_CRYPTO_SEQCTRLB_DMA0PRESB_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRLB */
-#define CRYPTO_SEQCTRLB_DMA1PRESB (0x1UL << 29) /**< DMA1 Preserve B */
-#define _CRYPTO_SEQCTRLB_DMA1PRESB_SHIFT 29 /**< Shift value for CRYPTO_DMA1PRESB */
-#define _CRYPTO_SEQCTRLB_DMA1PRESB_MASK 0x20000000UL /**< Bit mask for CRYPTO_DMA1PRESB */
-#define _CRYPTO_SEQCTRLB_DMA1PRESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRLB */
-#define CRYPTO_SEQCTRLB_DMA1PRESB_DEFAULT (_CRYPTO_SEQCTRLB_DMA1PRESB_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRLB */
-
-/* Bit fields for CRYPTO IF */
-#define _CRYPTO_IF_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IF */
-#define _CRYPTO_IF_MASK 0x00000003UL /**< Mask for CRYPTO_IF */
-#define CRYPTO_IF_INSTRDONE (0x1UL << 0) /**< Instruction Done */
-#define _CRYPTO_IF_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */
-#define _CRYPTO_IF_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */
-#define _CRYPTO_IF_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IF */
-#define CRYPTO_IF_INSTRDONE_DEFAULT (_CRYPTO_IF_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IF */
-#define CRYPTO_IF_SEQDONE (0x1UL << 1) /**< Sequence Done */
-#define _CRYPTO_IF_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */
-#define _CRYPTO_IF_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */
-#define _CRYPTO_IF_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IF */
-#define CRYPTO_IF_SEQDONE_DEFAULT (_CRYPTO_IF_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IF */
-
-/* Bit fields for CRYPTO IFS */
-#define _CRYPTO_IFS_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IFS */
-#define _CRYPTO_IFS_MASK 0x00000003UL /**< Mask for CRYPTO_IFS */
-#define CRYPTO_IFS_INSTRDONE (0x1UL << 0) /**< Set INSTRDONE Interrupt Flag */
-#define _CRYPTO_IFS_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */
-#define _CRYPTO_IFS_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */
-#define _CRYPTO_IFS_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */
-#define CRYPTO_IFS_INSTRDONE_DEFAULT (_CRYPTO_IFS_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IFS */
-#define CRYPTO_IFS_SEQDONE (0x1UL << 1) /**< Set SEQDONE Interrupt Flag */
-#define _CRYPTO_IFS_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */
-#define _CRYPTO_IFS_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */
-#define _CRYPTO_IFS_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */
-#define CRYPTO_IFS_SEQDONE_DEFAULT (_CRYPTO_IFS_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IFS */
-
-/* Bit fields for CRYPTO IFC */
-#define _CRYPTO_IFC_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IFC */
-#define _CRYPTO_IFC_MASK 0x00000003UL /**< Mask for CRYPTO_IFC */
-#define CRYPTO_IFC_INSTRDONE (0x1UL << 0) /**< Clear INSTRDONE Interrupt Flag */
-#define _CRYPTO_IFC_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */
-#define _CRYPTO_IFC_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */
-#define _CRYPTO_IFC_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */
-#define CRYPTO_IFC_INSTRDONE_DEFAULT (_CRYPTO_IFC_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IFC */
-#define CRYPTO_IFC_SEQDONE (0x1UL << 1) /**< Clear SEQDONE Interrupt Flag */
-#define _CRYPTO_IFC_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */
-#define _CRYPTO_IFC_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */
-#define _CRYPTO_IFC_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */
-#define CRYPTO_IFC_SEQDONE_DEFAULT (_CRYPTO_IFC_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IFC */
-
-/* Bit fields for CRYPTO IEN */
-#define _CRYPTO_IEN_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IEN */
-#define _CRYPTO_IEN_MASK 0x00000003UL /**< Mask for CRYPTO_IEN */
-#define CRYPTO_IEN_INSTRDONE (0x1UL << 0) /**< INSTRDONE Interrupt Enable */
-#define _CRYPTO_IEN_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */
-#define _CRYPTO_IEN_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */
-#define _CRYPTO_IEN_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */
-#define CRYPTO_IEN_INSTRDONE_DEFAULT (_CRYPTO_IEN_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IEN */
-#define CRYPTO_IEN_SEQDONE (0x1UL << 1) /**< SEQDONE Interrupt Enable */
-#define _CRYPTO_IEN_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */
-#define _CRYPTO_IEN_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */
-#define _CRYPTO_IEN_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */
-#define CRYPTO_IEN_SEQDONE_DEFAULT (_CRYPTO_IEN_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IEN */
-
-/* Bit fields for CRYPTO SEQ0 */
-#define _CRYPTO_SEQ0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ0 */
-#define _CRYPTO_SEQ0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ0 */
-#define _CRYPTO_SEQ0_INSTR0_SHIFT 0 /**< Shift value for CRYPTO_INSTR0 */
-#define _CRYPTO_SEQ0_INSTR0_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR0 */
-#define _CRYPTO_SEQ0_INSTR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */
-#define CRYPTO_SEQ0_INSTR0_DEFAULT (_CRYPTO_SEQ0_INSTR0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */
-#define _CRYPTO_SEQ0_INSTR1_SHIFT 8 /**< Shift value for CRYPTO_INSTR1 */
-#define _CRYPTO_SEQ0_INSTR1_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR1 */
-#define _CRYPTO_SEQ0_INSTR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */
-#define CRYPTO_SEQ0_INSTR1_DEFAULT (_CRYPTO_SEQ0_INSTR1_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */
-#define _CRYPTO_SEQ0_INSTR2_SHIFT 16 /**< Shift value for CRYPTO_INSTR2 */
-#define _CRYPTO_SEQ0_INSTR2_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR2 */
-#define _CRYPTO_SEQ0_INSTR2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */
-#define CRYPTO_SEQ0_INSTR2_DEFAULT (_CRYPTO_SEQ0_INSTR2_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */
-#define _CRYPTO_SEQ0_INSTR3_SHIFT 24 /**< Shift value for CRYPTO_INSTR3 */
-#define _CRYPTO_SEQ0_INSTR3_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR3 */
-#define _CRYPTO_SEQ0_INSTR3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */
-#define CRYPTO_SEQ0_INSTR3_DEFAULT (_CRYPTO_SEQ0_INSTR3_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */
-
-/* Bit fields for CRYPTO SEQ1 */
-#define _CRYPTO_SEQ1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ1 */
-#define _CRYPTO_SEQ1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ1 */
-#define _CRYPTO_SEQ1_INSTR4_SHIFT 0 /**< Shift value for CRYPTO_INSTR4 */
-#define _CRYPTO_SEQ1_INSTR4_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR4 */
-#define _CRYPTO_SEQ1_INSTR4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */
-#define CRYPTO_SEQ1_INSTR4_DEFAULT (_CRYPTO_SEQ1_INSTR4_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */
-#define _CRYPTO_SEQ1_INSTR5_SHIFT 8 /**< Shift value for CRYPTO_INSTR5 */
-#define _CRYPTO_SEQ1_INSTR5_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR5 */
-#define _CRYPTO_SEQ1_INSTR5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */
-#define CRYPTO_SEQ1_INSTR5_DEFAULT (_CRYPTO_SEQ1_INSTR5_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */
-#define _CRYPTO_SEQ1_INSTR6_SHIFT 16 /**< Shift value for CRYPTO_INSTR6 */
-#define _CRYPTO_SEQ1_INSTR6_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR6 */
-#define _CRYPTO_SEQ1_INSTR6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */
-#define CRYPTO_SEQ1_INSTR6_DEFAULT (_CRYPTO_SEQ1_INSTR6_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */
-#define _CRYPTO_SEQ1_INSTR7_SHIFT 24 /**< Shift value for CRYPTO_INSTR7 */
-#define _CRYPTO_SEQ1_INSTR7_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR7 */
-#define _CRYPTO_SEQ1_INSTR7_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */
-#define CRYPTO_SEQ1_INSTR7_DEFAULT (_CRYPTO_SEQ1_INSTR7_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */
-
-/* Bit fields for CRYPTO SEQ2 */
-#define _CRYPTO_SEQ2_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ2 */
-#define _CRYPTO_SEQ2_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ2 */
-#define _CRYPTO_SEQ2_INSTR8_SHIFT 0 /**< Shift value for CRYPTO_INSTR8 */
-#define _CRYPTO_SEQ2_INSTR8_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR8 */
-#define _CRYPTO_SEQ2_INSTR8_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */
-#define CRYPTO_SEQ2_INSTR8_DEFAULT (_CRYPTO_SEQ2_INSTR8_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */
-#define _CRYPTO_SEQ2_INSTR9_SHIFT 8 /**< Shift value for CRYPTO_INSTR9 */
-#define _CRYPTO_SEQ2_INSTR9_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR9 */
-#define _CRYPTO_SEQ2_INSTR9_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */
-#define CRYPTO_SEQ2_INSTR9_DEFAULT (_CRYPTO_SEQ2_INSTR9_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */
-#define _CRYPTO_SEQ2_INSTR10_SHIFT 16 /**< Shift value for CRYPTO_INSTR10 */
-#define _CRYPTO_SEQ2_INSTR10_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR10 */
-#define _CRYPTO_SEQ2_INSTR10_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */
-#define CRYPTO_SEQ2_INSTR10_DEFAULT (_CRYPTO_SEQ2_INSTR10_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */
-#define _CRYPTO_SEQ2_INSTR11_SHIFT 24 /**< Shift value for CRYPTO_INSTR11 */
-#define _CRYPTO_SEQ2_INSTR11_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR11 */
-#define _CRYPTO_SEQ2_INSTR11_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */
-#define CRYPTO_SEQ2_INSTR11_DEFAULT (_CRYPTO_SEQ2_INSTR11_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */
-
-/* Bit fields for CRYPTO SEQ3 */
-#define _CRYPTO_SEQ3_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ3 */
-#define _CRYPTO_SEQ3_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ3 */
-#define _CRYPTO_SEQ3_INSTR12_SHIFT 0 /**< Shift value for CRYPTO_INSTR12 */
-#define _CRYPTO_SEQ3_INSTR12_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR12 */
-#define _CRYPTO_SEQ3_INSTR12_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */
-#define CRYPTO_SEQ3_INSTR12_DEFAULT (_CRYPTO_SEQ3_INSTR12_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */
-#define _CRYPTO_SEQ3_INSTR13_SHIFT 8 /**< Shift value for CRYPTO_INSTR13 */
-#define _CRYPTO_SEQ3_INSTR13_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR13 */
-#define _CRYPTO_SEQ3_INSTR13_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */
-#define CRYPTO_SEQ3_INSTR13_DEFAULT (_CRYPTO_SEQ3_INSTR13_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */
-#define _CRYPTO_SEQ3_INSTR14_SHIFT 16 /**< Shift value for CRYPTO_INSTR14 */
-#define _CRYPTO_SEQ3_INSTR14_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR14 */
-#define _CRYPTO_SEQ3_INSTR14_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */
-#define CRYPTO_SEQ3_INSTR14_DEFAULT (_CRYPTO_SEQ3_INSTR14_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */
-#define _CRYPTO_SEQ3_INSTR15_SHIFT 24 /**< Shift value for CRYPTO_INSTR15 */
-#define _CRYPTO_SEQ3_INSTR15_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR15 */
-#define _CRYPTO_SEQ3_INSTR15_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */
-#define CRYPTO_SEQ3_INSTR15_DEFAULT (_CRYPTO_SEQ3_INSTR15_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */
-
-/* Bit fields for CRYPTO SEQ4 */
-#define _CRYPTO_SEQ4_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ4 */
-#define _CRYPTO_SEQ4_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ4 */
-#define _CRYPTO_SEQ4_INSTR16_SHIFT 0 /**< Shift value for CRYPTO_INSTR16 */
-#define _CRYPTO_SEQ4_INSTR16_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR16 */
-#define _CRYPTO_SEQ4_INSTR16_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */
-#define CRYPTO_SEQ4_INSTR16_DEFAULT (_CRYPTO_SEQ4_INSTR16_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */
-#define _CRYPTO_SEQ4_INSTR17_SHIFT 8 /**< Shift value for CRYPTO_INSTR17 */
-#define _CRYPTO_SEQ4_INSTR17_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR17 */
-#define _CRYPTO_SEQ4_INSTR17_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */
-#define CRYPTO_SEQ4_INSTR17_DEFAULT (_CRYPTO_SEQ4_INSTR17_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */
-#define _CRYPTO_SEQ4_INSTR18_SHIFT 16 /**< Shift value for CRYPTO_INSTR18 */
-#define _CRYPTO_SEQ4_INSTR18_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR18 */
-#define _CRYPTO_SEQ4_INSTR18_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */
-#define CRYPTO_SEQ4_INSTR18_DEFAULT (_CRYPTO_SEQ4_INSTR18_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */
-#define _CRYPTO_SEQ4_INSTR19_SHIFT 24 /**< Shift value for CRYPTO_INSTR19 */
-#define _CRYPTO_SEQ4_INSTR19_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR19 */
-#define _CRYPTO_SEQ4_INSTR19_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */
-#define CRYPTO_SEQ4_INSTR19_DEFAULT (_CRYPTO_SEQ4_INSTR19_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */
-
-/* Bit fields for CRYPTO DATA0 */
-#define _CRYPTO_DATA0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0 */
-#define _CRYPTO_DATA0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA0 */
-#define _CRYPTO_DATA0_DATA0_SHIFT 0 /**< Shift value for CRYPTO_DATA0 */
-#define _CRYPTO_DATA0_DATA0_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA0 */
-#define _CRYPTO_DATA0_DATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0 */
-#define CRYPTO_DATA0_DATA0_DEFAULT (_CRYPTO_DATA0_DATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0 */
-
-/* Bit fields for CRYPTO DATA1 */
-#define _CRYPTO_DATA1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA1 */
-#define _CRYPTO_DATA1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA1 */
-#define _CRYPTO_DATA1_DATA1_SHIFT 0 /**< Shift value for CRYPTO_DATA1 */
-#define _CRYPTO_DATA1_DATA1_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA1 */
-#define _CRYPTO_DATA1_DATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA1 */
-#define CRYPTO_DATA1_DATA1_DEFAULT (_CRYPTO_DATA1_DATA1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA1 */
-
-/* Bit fields for CRYPTO DATA2 */
-#define _CRYPTO_DATA2_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA2 */
-#define _CRYPTO_DATA2_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA2 */
-#define _CRYPTO_DATA2_DATA2_SHIFT 0 /**< Shift value for CRYPTO_DATA2 */
-#define _CRYPTO_DATA2_DATA2_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA2 */
-#define _CRYPTO_DATA2_DATA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA2 */
-#define CRYPTO_DATA2_DATA2_DEFAULT (_CRYPTO_DATA2_DATA2_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA2 */
-
-/* Bit fields for CRYPTO DATA3 */
-#define _CRYPTO_DATA3_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA3 */
-#define _CRYPTO_DATA3_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA3 */
-#define _CRYPTO_DATA3_DATA3_SHIFT 0 /**< Shift value for CRYPTO_DATA3 */
-#define _CRYPTO_DATA3_DATA3_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA3 */
-#define _CRYPTO_DATA3_DATA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA3 */
-#define CRYPTO_DATA3_DATA3_DEFAULT (_CRYPTO_DATA3_DATA3_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA3 */
-
-/* Bit fields for CRYPTO DATA0XOR */
-#define _CRYPTO_DATA0XOR_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0XOR */
-#define _CRYPTO_DATA0XOR_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA0XOR */
-#define _CRYPTO_DATA0XOR_DATA0XOR_SHIFT 0 /**< Shift value for CRYPTO_DATA0XOR */
-#define _CRYPTO_DATA0XOR_DATA0XOR_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA0XOR */
-#define _CRYPTO_DATA0XOR_DATA0XOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0XOR */
-#define CRYPTO_DATA0XOR_DATA0XOR_DEFAULT (_CRYPTO_DATA0XOR_DATA0XOR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0XOR */
-
-/* Bit fields for CRYPTO DATA0BYTE */
-#define _CRYPTO_DATA0BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE */
-#define _CRYPTO_DATA0BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE */
-#define _CRYPTO_DATA0BYTE_DATA0BYTE_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE */
-#define _CRYPTO_DATA0BYTE_DATA0BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE */
-#define _CRYPTO_DATA0BYTE_DATA0BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE */
-#define CRYPTO_DATA0BYTE_DATA0BYTE_DEFAULT (_CRYPTO_DATA0BYTE_DATA0BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE */
-
-/* Bit fields for CRYPTO DATA1BYTE */
-#define _CRYPTO_DATA1BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA1BYTE */
-#define _CRYPTO_DATA1BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA1BYTE */
-#define _CRYPTO_DATA1BYTE_DATA1BYTE_SHIFT 0 /**< Shift value for CRYPTO_DATA1BYTE */
-#define _CRYPTO_DATA1BYTE_DATA1BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA1BYTE */
-#define _CRYPTO_DATA1BYTE_DATA1BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA1BYTE */
-#define CRYPTO_DATA1BYTE_DATA1BYTE_DEFAULT (_CRYPTO_DATA1BYTE_DATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA1BYTE */
-
-/* Bit fields for CRYPTO DATA0XORBYTE */
-#define _CRYPTO_DATA0XORBYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0XORBYTE */
-#define _CRYPTO_DATA0XORBYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0XORBYTE */
-#define _CRYPTO_DATA0XORBYTE_DATA0XORBYTE_SHIFT 0 /**< Shift value for CRYPTO_DATA0XORBYTE */
-#define _CRYPTO_DATA0XORBYTE_DATA0XORBYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0XORBYTE */
-#define _CRYPTO_DATA0XORBYTE_DATA0XORBYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0XORBYTE */
-#define CRYPTO_DATA0XORBYTE_DATA0XORBYTE_DEFAULT (_CRYPTO_DATA0XORBYTE_DATA0XORBYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0XORBYTE */
-
-/* Bit fields for CRYPTO DATA0BYTE12 */
-#define _CRYPTO_DATA0BYTE12_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE12 */
-#define _CRYPTO_DATA0BYTE12_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE12 */
-#define _CRYPTO_DATA0BYTE12_DATA0BYTE12_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE12 */
-#define _CRYPTO_DATA0BYTE12_DATA0BYTE12_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE12 */
-#define _CRYPTO_DATA0BYTE12_DATA0BYTE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE12 */
-#define CRYPTO_DATA0BYTE12_DATA0BYTE12_DEFAULT (_CRYPTO_DATA0BYTE12_DATA0BYTE12_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE12 */
-
-/* Bit fields for CRYPTO DATA0BYTE13 */
-#define _CRYPTO_DATA0BYTE13_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE13 */
-#define _CRYPTO_DATA0BYTE13_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE13 */
-#define _CRYPTO_DATA0BYTE13_DATA0BYTE13_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE13 */
-#define _CRYPTO_DATA0BYTE13_DATA0BYTE13_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE13 */
-#define _CRYPTO_DATA0BYTE13_DATA0BYTE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE13 */
-#define CRYPTO_DATA0BYTE13_DATA0BYTE13_DEFAULT (_CRYPTO_DATA0BYTE13_DATA0BYTE13_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE13 */
-
-/* Bit fields for CRYPTO DATA0BYTE14 */
-#define _CRYPTO_DATA0BYTE14_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE14 */
-#define _CRYPTO_DATA0BYTE14_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE14 */
-#define _CRYPTO_DATA0BYTE14_DATA0BYTE14_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE14 */
-#define _CRYPTO_DATA0BYTE14_DATA0BYTE14_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE14 */
-#define _CRYPTO_DATA0BYTE14_DATA0BYTE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE14 */
-#define CRYPTO_DATA0BYTE14_DATA0BYTE14_DEFAULT (_CRYPTO_DATA0BYTE14_DATA0BYTE14_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE14 */
-
-/* Bit fields for CRYPTO DATA0BYTE15 */
-#define _CRYPTO_DATA0BYTE15_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE15 */
-#define _CRYPTO_DATA0BYTE15_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE15 */
-#define _CRYPTO_DATA0BYTE15_DATA0BYTE15_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE15 */
-#define _CRYPTO_DATA0BYTE15_DATA0BYTE15_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE15 */
-#define _CRYPTO_DATA0BYTE15_DATA0BYTE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE15 */
-#define CRYPTO_DATA0BYTE15_DATA0BYTE15_DEFAULT (_CRYPTO_DATA0BYTE15_DATA0BYTE15_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE15 */
-
-/* Bit fields for CRYPTO DDATA0 */
-#define _CRYPTO_DDATA0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0 */
-#define _CRYPTO_DDATA0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA0 */
-#define _CRYPTO_DDATA0_DDATA0_SHIFT 0 /**< Shift value for CRYPTO_DDATA0 */
-#define _CRYPTO_DDATA0_DDATA0_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA0 */
-#define _CRYPTO_DDATA0_DDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0 */
-#define CRYPTO_DDATA0_DDATA0_DEFAULT (_CRYPTO_DDATA0_DDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0 */
-
-/* Bit fields for CRYPTO DDATA1 */
-#define _CRYPTO_DDATA1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA1 */
-#define _CRYPTO_DDATA1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA1 */
-#define _CRYPTO_DDATA1_DDATA1_SHIFT 0 /**< Shift value for CRYPTO_DDATA1 */
-#define _CRYPTO_DDATA1_DDATA1_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA1 */
-#define _CRYPTO_DDATA1_DDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA1 */
-#define CRYPTO_DDATA1_DDATA1_DEFAULT (_CRYPTO_DDATA1_DDATA1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA1 */
-
-/* Bit fields for CRYPTO DDATA2 */
-#define _CRYPTO_DDATA2_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA2 */
-#define _CRYPTO_DDATA2_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA2 */
-#define _CRYPTO_DDATA2_DDATA2_SHIFT 0 /**< Shift value for CRYPTO_DDATA2 */
-#define _CRYPTO_DDATA2_DDATA2_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA2 */
-#define _CRYPTO_DDATA2_DDATA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA2 */
-#define CRYPTO_DDATA2_DDATA2_DEFAULT (_CRYPTO_DDATA2_DDATA2_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA2 */
-
-/* Bit fields for CRYPTO DDATA3 */
-#define _CRYPTO_DDATA3_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA3 */
-#define _CRYPTO_DDATA3_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA3 */
-#define _CRYPTO_DDATA3_DDATA3_SHIFT 0 /**< Shift value for CRYPTO_DDATA3 */
-#define _CRYPTO_DDATA3_DDATA3_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA3 */
-#define _CRYPTO_DDATA3_DDATA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA3 */
-#define CRYPTO_DDATA3_DDATA3_DEFAULT (_CRYPTO_DDATA3_DDATA3_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA3 */
-
-/* Bit fields for CRYPTO DDATA4 */
-#define _CRYPTO_DDATA4_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA4 */
-#define _CRYPTO_DDATA4_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA4 */
-#define _CRYPTO_DDATA4_DDATA4_SHIFT 0 /**< Shift value for CRYPTO_DDATA4 */
-#define _CRYPTO_DDATA4_DDATA4_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA4 */
-#define _CRYPTO_DDATA4_DDATA4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA4 */
-#define CRYPTO_DDATA4_DDATA4_DEFAULT (_CRYPTO_DDATA4_DDATA4_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA4 */
-
-/* Bit fields for CRYPTO DDATA0BIG */
-#define _CRYPTO_DDATA0BIG_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0BIG */
-#define _CRYPTO_DDATA0BIG_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA0BIG */
-#define _CRYPTO_DDATA0BIG_DDATA0BIG_SHIFT 0 /**< Shift value for CRYPTO_DDATA0BIG */
-#define _CRYPTO_DDATA0BIG_DDATA0BIG_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA0BIG */
-#define _CRYPTO_DDATA0BIG_DDATA0BIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0BIG */
-#define CRYPTO_DDATA0BIG_DDATA0BIG_DEFAULT (_CRYPTO_DDATA0BIG_DDATA0BIG_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0BIG */
-
-/* Bit fields for CRYPTO DDATA0BYTE */
-#define _CRYPTO_DDATA0BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0BYTE */
-#define _CRYPTO_DDATA0BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DDATA0BYTE */
-#define _CRYPTO_DDATA0BYTE_DDATA0BYTE_SHIFT 0 /**< Shift value for CRYPTO_DDATA0BYTE */
-#define _CRYPTO_DDATA0BYTE_DDATA0BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DDATA0BYTE */
-#define _CRYPTO_DDATA0BYTE_DDATA0BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0BYTE */
-#define CRYPTO_DDATA0BYTE_DDATA0BYTE_DEFAULT (_CRYPTO_DDATA0BYTE_DDATA0BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0BYTE */
-
-/* Bit fields for CRYPTO DDATA1BYTE */
-#define _CRYPTO_DDATA1BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA1BYTE */
-#define _CRYPTO_DDATA1BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DDATA1BYTE */
-#define _CRYPTO_DDATA1BYTE_DDATA1BYTE_SHIFT 0 /**< Shift value for CRYPTO_DDATA1BYTE */
-#define _CRYPTO_DDATA1BYTE_DDATA1BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DDATA1BYTE */
-#define _CRYPTO_DDATA1BYTE_DDATA1BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA1BYTE */
-#define CRYPTO_DDATA1BYTE_DDATA1BYTE_DEFAULT (_CRYPTO_DDATA1BYTE_DDATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA1BYTE */
-
-/* Bit fields for CRYPTO DDATA0BYTE32 */
-#define _CRYPTO_DDATA0BYTE32_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0BYTE32 */
-#define _CRYPTO_DDATA0BYTE32_MASK 0x0000000FUL /**< Mask for CRYPTO_DDATA0BYTE32 */
-#define _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_SHIFT 0 /**< Shift value for CRYPTO_DDATA0BYTE32 */
-#define _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_MASK 0xFUL /**< Bit mask for CRYPTO_DDATA0BYTE32 */
-#define _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0BYTE32 */
-#define CRYPTO_DDATA0BYTE32_DDATA0BYTE32_DEFAULT (_CRYPTO_DDATA0BYTE32_DDATA0BYTE32_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0BYTE32 */
-
-/* Bit fields for CRYPTO QDATA0 */
-#define _CRYPTO_QDATA0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA0 */
-#define _CRYPTO_QDATA0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_QDATA0 */
-#define _CRYPTO_QDATA0_QDATA0_SHIFT 0 /**< Shift value for CRYPTO_QDATA0 */
-#define _CRYPTO_QDATA0_QDATA0_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_QDATA0 */
-#define _CRYPTO_QDATA0_QDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA0 */
-#define CRYPTO_QDATA0_QDATA0_DEFAULT (_CRYPTO_QDATA0_QDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA0 */
-
-/* Bit fields for CRYPTO QDATA1 */
-#define _CRYPTO_QDATA1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA1 */
-#define _CRYPTO_QDATA1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_QDATA1 */
-#define _CRYPTO_QDATA1_QDATA1_SHIFT 0 /**< Shift value for CRYPTO_QDATA1 */
-#define _CRYPTO_QDATA1_QDATA1_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_QDATA1 */
-#define _CRYPTO_QDATA1_QDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA1 */
-#define CRYPTO_QDATA1_QDATA1_DEFAULT (_CRYPTO_QDATA1_QDATA1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1 */
-
-/* Bit fields for CRYPTO QDATA1BIG */
-#define _CRYPTO_QDATA1BIG_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA1BIG */
-#define _CRYPTO_QDATA1BIG_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_QDATA1BIG */
-#define _CRYPTO_QDATA1BIG_QDATA1BIG_SHIFT 0 /**< Shift value for CRYPTO_QDATA1BIG */
-#define _CRYPTO_QDATA1BIG_QDATA1BIG_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_QDATA1BIG */
-#define _CRYPTO_QDATA1BIG_QDATA1BIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA1BIG */
-#define CRYPTO_QDATA1BIG_QDATA1BIG_DEFAULT (_CRYPTO_QDATA1BIG_QDATA1BIG_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1BIG */
-
-/* Bit fields for CRYPTO QDATA0BYTE */
-#define _CRYPTO_QDATA0BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA0BYTE */
-#define _CRYPTO_QDATA0BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_QDATA0BYTE */
-#define _CRYPTO_QDATA0BYTE_QDATA0BYTE_SHIFT 0 /**< Shift value for CRYPTO_QDATA0BYTE */
-#define _CRYPTO_QDATA0BYTE_QDATA0BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_QDATA0BYTE */
-#define _CRYPTO_QDATA0BYTE_QDATA0BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA0BYTE */
-#define CRYPTO_QDATA0BYTE_QDATA0BYTE_DEFAULT (_CRYPTO_QDATA0BYTE_QDATA0BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA0BYTE */
-
-/* Bit fields for CRYPTO QDATA1BYTE */
-#define _CRYPTO_QDATA1BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA1BYTE */
-#define _CRYPTO_QDATA1BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_QDATA1BYTE */
-#define _CRYPTO_QDATA1BYTE_QDATA1BYTE_SHIFT 0 /**< Shift value for CRYPTO_QDATA1BYTE */
-#define _CRYPTO_QDATA1BYTE_QDATA1BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_QDATA1BYTE */
-#define _CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA1BYTE */
-#define CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT (_CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1BYTE */
-
-/** @} */
-/** @} End of group EFR32FG13P_CRYPTO */
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_csen.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_csen.h
deleted file mode 100644
index d4bf9cd2..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_csen.h
+++ /dev/null
@@ -1,979 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_csen.h
- * @brief EFR32FG13P_CSEN register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P_CSEN CSEN
- * @{
- * @brief EFR32FG13P_CSEN Register Declaration
- *****************************************************************************/
-/** CSEN Register Declaration */
-typedef struct {
- __IOM uint32_t CTRL; /**< Control */
- __IOM uint32_t TIMCTRL; /**< Timing Control */
- __IOM uint32_t CMD; /**< Command */
- __IM uint32_t STATUS; /**< Status */
- __IOM uint32_t PRSSEL; /**< PRS Select */
- __IOM uint32_t DATA; /**< Output Data */
- __IOM uint32_t SCANMASK0; /**< Scan Channel Mask 0 */
- __IOM uint32_t SCANINPUTSEL0; /**< Scan Input Selection 0 */
- __IOM uint32_t SCANMASK1; /**< Scan Channel Mask 1 */
- __IOM uint32_t SCANINPUTSEL1; /**< Scan Input Selection 1 */
- __IM uint32_t APORTREQ; /**< APORT Request Status */
- __IM uint32_t APORTCONFLICT; /**< APORT Request Conflict */
- __IOM uint32_t CMPTHR; /**< Comparator Threshold */
- __IOM uint32_t EMA; /**< Exponential Moving Average */
- __IOM uint32_t EMACTRL; /**< Exponential Moving Average Control */
- __IOM uint32_t SINGLECTRL; /**< Single Conversion Control */
- __IOM uint32_t DMBASELINE; /**< Delta Modulation Baseline */
- __IOM uint32_t DMCFG; /**< Delta Modulation Configuration */
- __IOM uint32_t ANACTRL; /**< Analog Control */
-
- uint32_t RESERVED0[2]; /**< Reserved for future use **/
- __IM uint32_t IF; /**< Interrupt Flag */
- __IOM uint32_t IFS; /**< Interrupt Flag Set */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear */
- __IOM uint32_t IEN; /**< Interrupt Enable */
-} CSEN_TypeDef; /** @} */
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_CSEN
- * @{
- * @defgroup EFR32FG13P_CSEN_BitFields CSEN Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for CSEN CTRL */
-#define _CSEN_CTRL_RESETVALUE 0x00030000UL /**< Default value for CSEN_CTRL */
-#define _CSEN_CTRL_MASK 0x1FFFF336UL /**< Mask for CSEN_CTRL */
-#define CSEN_CTRL_EN (0x1UL << 1) /**< CSEN Enable */
-#define _CSEN_CTRL_EN_SHIFT 1 /**< Shift value for CSEN_EN */
-#define _CSEN_CTRL_EN_MASK 0x2UL /**< Bit mask for CSEN_EN */
-#define _CSEN_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
-#define _CSEN_CTRL_EN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */
-#define _CSEN_CTRL_EN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */
-#define CSEN_CTRL_EN_DEFAULT (_CSEN_CTRL_EN_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_CTRL */
-#define CSEN_CTRL_EN_DISABLE (_CSEN_CTRL_EN_DISABLE << 1) /**< Shifted mode DISABLE for CSEN_CTRL */
-#define CSEN_CTRL_EN_ENABLE (_CSEN_CTRL_EN_ENABLE << 1) /**< Shifted mode ENABLE for CSEN_CTRL */
-#define CSEN_CTRL_CMPPOL (0x1UL << 2) /**< CSEN Digital Comparator Polarity Select */
-#define _CSEN_CTRL_CMPPOL_SHIFT 2 /**< Shift value for CSEN_CMPPOL */
-#define _CSEN_CTRL_CMPPOL_MASK 0x4UL /**< Bit mask for CSEN_CMPPOL */
-#define _CSEN_CTRL_CMPPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
-#define _CSEN_CTRL_CMPPOL_GT 0x00000000UL /**< Mode GT for CSEN_CTRL */
-#define _CSEN_CTRL_CMPPOL_LTE 0x00000001UL /**< Mode LTE for CSEN_CTRL */
-#define CSEN_CTRL_CMPPOL_DEFAULT (_CSEN_CTRL_CMPPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_CTRL */
-#define CSEN_CTRL_CMPPOL_GT (_CSEN_CTRL_CMPPOL_GT << 2) /**< Shifted mode GT for CSEN_CTRL */
-#define CSEN_CTRL_CMPPOL_LTE (_CSEN_CTRL_CMPPOL_LTE << 2) /**< Shifted mode LTE for CSEN_CTRL */
-#define _CSEN_CTRL_CM_SHIFT 4 /**< Shift value for CSEN_CM */
-#define _CSEN_CTRL_CM_MASK 0x30UL /**< Bit mask for CSEN_CM */
-#define _CSEN_CTRL_CM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
-#define _CSEN_CTRL_CM_SGL 0x00000000UL /**< Mode SGL for CSEN_CTRL */
-#define _CSEN_CTRL_CM_SCAN 0x00000001UL /**< Mode SCAN for CSEN_CTRL */
-#define _CSEN_CTRL_CM_CONTSGL 0x00000002UL /**< Mode CONTSGL for CSEN_CTRL */
-#define _CSEN_CTRL_CM_CONTSCAN 0x00000003UL /**< Mode CONTSCAN for CSEN_CTRL */
-#define CSEN_CTRL_CM_DEFAULT (_CSEN_CTRL_CM_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_CTRL */
-#define CSEN_CTRL_CM_SGL (_CSEN_CTRL_CM_SGL << 4) /**< Shifted mode SGL for CSEN_CTRL */
-#define CSEN_CTRL_CM_SCAN (_CSEN_CTRL_CM_SCAN << 4) /**< Shifted mode SCAN for CSEN_CTRL */
-#define CSEN_CTRL_CM_CONTSGL (_CSEN_CTRL_CM_CONTSGL << 4) /**< Shifted mode CONTSGL for CSEN_CTRL */
-#define CSEN_CTRL_CM_CONTSCAN (_CSEN_CTRL_CM_CONTSCAN << 4) /**< Shifted mode CONTSCAN for CSEN_CTRL */
-#define _CSEN_CTRL_SARCR_SHIFT 8 /**< Shift value for CSEN_SARCR */
-#define _CSEN_CTRL_SARCR_MASK 0x300UL /**< Bit mask for CSEN_SARCR */
-#define _CSEN_CTRL_SARCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
-#define _CSEN_CTRL_SARCR_CLK10 0x00000000UL /**< Mode CLK10 for CSEN_CTRL */
-#define _CSEN_CTRL_SARCR_CLK12 0x00000001UL /**< Mode CLK12 for CSEN_CTRL */
-#define _CSEN_CTRL_SARCR_CLK14 0x00000002UL /**< Mode CLK14 for CSEN_CTRL */
-#define _CSEN_CTRL_SARCR_CLK16 0x00000003UL /**< Mode CLK16 for CSEN_CTRL */
-#define CSEN_CTRL_SARCR_DEFAULT (_CSEN_CTRL_SARCR_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_CTRL */
-#define CSEN_CTRL_SARCR_CLK10 (_CSEN_CTRL_SARCR_CLK10 << 8) /**< Shifted mode CLK10 for CSEN_CTRL */
-#define CSEN_CTRL_SARCR_CLK12 (_CSEN_CTRL_SARCR_CLK12 << 8) /**< Shifted mode CLK12 for CSEN_CTRL */
-#define CSEN_CTRL_SARCR_CLK14 (_CSEN_CTRL_SARCR_CLK14 << 8) /**< Shifted mode CLK14 for CSEN_CTRL */
-#define CSEN_CTRL_SARCR_CLK16 (_CSEN_CTRL_SARCR_CLK16 << 8) /**< Shifted mode CLK16 for CSEN_CTRL */
-#define _CSEN_CTRL_ACU_SHIFT 12 /**< Shift value for CSEN_ACU */
-#define _CSEN_CTRL_ACU_MASK 0x7000UL /**< Bit mask for CSEN_ACU */
-#define _CSEN_CTRL_ACU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
-#define _CSEN_CTRL_ACU_ACC1 0x00000000UL /**< Mode ACC1 for CSEN_CTRL */
-#define _CSEN_CTRL_ACU_ACC2 0x00000001UL /**< Mode ACC2 for CSEN_CTRL */
-#define _CSEN_CTRL_ACU_ACC4 0x00000002UL /**< Mode ACC4 for CSEN_CTRL */
-#define _CSEN_CTRL_ACU_ACC8 0x00000003UL /**< Mode ACC8 for CSEN_CTRL */
-#define _CSEN_CTRL_ACU_ACC16 0x00000004UL /**< Mode ACC16 for CSEN_CTRL */
-#define _CSEN_CTRL_ACU_ACC32 0x00000005UL /**< Mode ACC32 for CSEN_CTRL */
-#define _CSEN_CTRL_ACU_ACC64 0x00000006UL /**< Mode ACC64 for CSEN_CTRL */
-#define CSEN_CTRL_ACU_DEFAULT (_CSEN_CTRL_ACU_DEFAULT << 12) /**< Shifted mode DEFAULT for CSEN_CTRL */
-#define CSEN_CTRL_ACU_ACC1 (_CSEN_CTRL_ACU_ACC1 << 12) /**< Shifted mode ACC1 for CSEN_CTRL */
-#define CSEN_CTRL_ACU_ACC2 (_CSEN_CTRL_ACU_ACC2 << 12) /**< Shifted mode ACC2 for CSEN_CTRL */
-#define CSEN_CTRL_ACU_ACC4 (_CSEN_CTRL_ACU_ACC4 << 12) /**< Shifted mode ACC4 for CSEN_CTRL */
-#define CSEN_CTRL_ACU_ACC8 (_CSEN_CTRL_ACU_ACC8 << 12) /**< Shifted mode ACC8 for CSEN_CTRL */
-#define CSEN_CTRL_ACU_ACC16 (_CSEN_CTRL_ACU_ACC16 << 12) /**< Shifted mode ACC16 for CSEN_CTRL */
-#define CSEN_CTRL_ACU_ACC32 (_CSEN_CTRL_ACU_ACC32 << 12) /**< Shifted mode ACC32 for CSEN_CTRL */
-#define CSEN_CTRL_ACU_ACC64 (_CSEN_CTRL_ACU_ACC64 << 12) /**< Shifted mode ACC64 for CSEN_CTRL */
-#define CSEN_CTRL_MCEN (0x1UL << 15) /**< CSEN Multiple Channel Enable */
-#define _CSEN_CTRL_MCEN_SHIFT 15 /**< Shift value for CSEN_MCEN */
-#define _CSEN_CTRL_MCEN_MASK 0x8000UL /**< Bit mask for CSEN_MCEN */
-#define _CSEN_CTRL_MCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
-#define _CSEN_CTRL_MCEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */
-#define _CSEN_CTRL_MCEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */
-#define CSEN_CTRL_MCEN_DEFAULT (_CSEN_CTRL_MCEN_DEFAULT << 15) /**< Shifted mode DEFAULT for CSEN_CTRL */
-#define CSEN_CTRL_MCEN_DISABLE (_CSEN_CTRL_MCEN_DISABLE << 15) /**< Shifted mode DISABLE for CSEN_CTRL */
-#define CSEN_CTRL_MCEN_ENABLE (_CSEN_CTRL_MCEN_ENABLE << 15) /**< Shifted mode ENABLE for CSEN_CTRL */
-#define _CSEN_CTRL_STM_SHIFT 16 /**< Shift value for CSEN_STM */
-#define _CSEN_CTRL_STM_MASK 0x30000UL /**< Bit mask for CSEN_STM */
-#define _CSEN_CTRL_STM_PRS 0x00000000UL /**< Mode PRS for CSEN_CTRL */
-#define _CSEN_CTRL_STM_TIMER 0x00000001UL /**< Mode TIMER for CSEN_CTRL */
-#define _CSEN_CTRL_STM_START 0x00000002UL /**< Mode START for CSEN_CTRL */
-#define _CSEN_CTRL_STM_DEFAULT 0x00000003UL /**< Mode DEFAULT for CSEN_CTRL */
-#define _CSEN_CTRL_STM_DEFAULT 0x00000003UL /**< Mode DEFAULT for CSEN_CTRL */
-#define CSEN_CTRL_STM_PRS (_CSEN_CTRL_STM_PRS << 16) /**< Shifted mode PRS for CSEN_CTRL */
-#define CSEN_CTRL_STM_TIMER (_CSEN_CTRL_STM_TIMER << 16) /**< Shifted mode TIMER for CSEN_CTRL */
-#define CSEN_CTRL_STM_START (_CSEN_CTRL_STM_START << 16) /**< Shifted mode START for CSEN_CTRL */
-#define CSEN_CTRL_STM_DEFAULT (_CSEN_CTRL_STM_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_CTRL */
-#define CSEN_CTRL_STM_DEFAULT (_CSEN_CTRL_STM_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_CTRL */
-#define CSEN_CTRL_CMPEN (0x1UL << 18) /**< CSEN Digital Comparator Enable */
-#define _CSEN_CTRL_CMPEN_SHIFT 18 /**< Shift value for CSEN_CMPEN */
-#define _CSEN_CTRL_CMPEN_MASK 0x40000UL /**< Bit mask for CSEN_CMPEN */
-#define _CSEN_CTRL_CMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
-#define _CSEN_CTRL_CMPEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */
-#define _CSEN_CTRL_CMPEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */
-#define CSEN_CTRL_CMPEN_DEFAULT (_CSEN_CTRL_CMPEN_DEFAULT << 18) /**< Shifted mode DEFAULT for CSEN_CTRL */
-#define CSEN_CTRL_CMPEN_DISABLE (_CSEN_CTRL_CMPEN_DISABLE << 18) /**< Shifted mode DISABLE for CSEN_CTRL */
-#define CSEN_CTRL_CMPEN_ENABLE (_CSEN_CTRL_CMPEN_ENABLE << 18) /**< Shifted mode ENABLE for CSEN_CTRL */
-#define CSEN_CTRL_DRSF (0x1UL << 19) /**< CSEN Disable Right-Shift */
-#define _CSEN_CTRL_DRSF_SHIFT 19 /**< Shift value for CSEN_DRSF */
-#define _CSEN_CTRL_DRSF_MASK 0x80000UL /**< Bit mask for CSEN_DRSF */
-#define _CSEN_CTRL_DRSF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
-#define _CSEN_CTRL_DRSF_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */
-#define _CSEN_CTRL_DRSF_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */
-#define CSEN_CTRL_DRSF_DEFAULT (_CSEN_CTRL_DRSF_DEFAULT << 19) /**< Shifted mode DEFAULT for CSEN_CTRL */
-#define CSEN_CTRL_DRSF_DISABLE (_CSEN_CTRL_DRSF_DISABLE << 19) /**< Shifted mode DISABLE for CSEN_CTRL */
-#define CSEN_CTRL_DRSF_ENABLE (_CSEN_CTRL_DRSF_ENABLE << 19) /**< Shifted mode ENABLE for CSEN_CTRL */
-#define CSEN_CTRL_DMAEN (0x1UL << 20) /**< CSEN DMA Enable Bit */
-#define _CSEN_CTRL_DMAEN_SHIFT 20 /**< Shift value for CSEN_DMAEN */
-#define _CSEN_CTRL_DMAEN_MASK 0x100000UL /**< Bit mask for CSEN_DMAEN */
-#define _CSEN_CTRL_DMAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
-#define _CSEN_CTRL_DMAEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */
-#define _CSEN_CTRL_DMAEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */
-#define CSEN_CTRL_DMAEN_DEFAULT (_CSEN_CTRL_DMAEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CSEN_CTRL */
-#define CSEN_CTRL_DMAEN_DISABLE (_CSEN_CTRL_DMAEN_DISABLE << 20) /**< Shifted mode DISABLE for CSEN_CTRL */
-#define CSEN_CTRL_DMAEN_ENABLE (_CSEN_CTRL_DMAEN_ENABLE << 20) /**< Shifted mode ENABLE for CSEN_CTRL */
-#define CSEN_CTRL_CONVSEL (0x1UL << 21) /**< CSEN Converter Select */
-#define _CSEN_CTRL_CONVSEL_SHIFT 21 /**< Shift value for CSEN_CONVSEL */
-#define _CSEN_CTRL_CONVSEL_MASK 0x200000UL /**< Bit mask for CSEN_CONVSEL */
-#define _CSEN_CTRL_CONVSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
-#define _CSEN_CTRL_CONVSEL_SAR 0x00000000UL /**< Mode SAR for CSEN_CTRL */
-#define _CSEN_CTRL_CONVSEL_DM 0x00000001UL /**< Mode DM for CSEN_CTRL */
-#define CSEN_CTRL_CONVSEL_DEFAULT (_CSEN_CTRL_CONVSEL_DEFAULT << 21) /**< Shifted mode DEFAULT for CSEN_CTRL */
-#define CSEN_CTRL_CONVSEL_SAR (_CSEN_CTRL_CONVSEL_SAR << 21) /**< Shifted mode SAR for CSEN_CTRL */
-#define CSEN_CTRL_CONVSEL_DM (_CSEN_CTRL_CONVSEL_DM << 21) /**< Shifted mode DM for CSEN_CTRL */
-#define CSEN_CTRL_CHOPEN (0x1UL << 22) /**< CSEN Chop Enable */
-#define _CSEN_CTRL_CHOPEN_SHIFT 22 /**< Shift value for CSEN_CHOPEN */
-#define _CSEN_CTRL_CHOPEN_MASK 0x400000UL /**< Bit mask for CSEN_CHOPEN */
-#define _CSEN_CTRL_CHOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
-#define _CSEN_CTRL_CHOPEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */
-#define _CSEN_CTRL_CHOPEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */
-#define CSEN_CTRL_CHOPEN_DEFAULT (_CSEN_CTRL_CHOPEN_DEFAULT << 22) /**< Shifted mode DEFAULT for CSEN_CTRL */
-#define CSEN_CTRL_CHOPEN_DISABLE (_CSEN_CTRL_CHOPEN_DISABLE << 22) /**< Shifted mode DISABLE for CSEN_CTRL */
-#define CSEN_CTRL_CHOPEN_ENABLE (_CSEN_CTRL_CHOPEN_ENABLE << 22) /**< Shifted mode ENABLE for CSEN_CTRL */
-#define CSEN_CTRL_AUTOGND (0x1UL << 23) /**< CSEN Automatic Ground Enable */
-#define _CSEN_CTRL_AUTOGND_SHIFT 23 /**< Shift value for CSEN_AUTOGND */
-#define _CSEN_CTRL_AUTOGND_MASK 0x800000UL /**< Bit mask for CSEN_AUTOGND */
-#define _CSEN_CTRL_AUTOGND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
-#define _CSEN_CTRL_AUTOGND_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */
-#define _CSEN_CTRL_AUTOGND_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */
-#define CSEN_CTRL_AUTOGND_DEFAULT (_CSEN_CTRL_AUTOGND_DEFAULT << 23) /**< Shifted mode DEFAULT for CSEN_CTRL */
-#define CSEN_CTRL_AUTOGND_DISABLE (_CSEN_CTRL_AUTOGND_DISABLE << 23) /**< Shifted mode DISABLE for CSEN_CTRL */
-#define CSEN_CTRL_AUTOGND_ENABLE (_CSEN_CTRL_AUTOGND_ENABLE << 23) /**< Shifted mode ENABLE for CSEN_CTRL */
-#define CSEN_CTRL_MXUC (0x1UL << 24) /**< CSEN Mux Disconnect */
-#define _CSEN_CTRL_MXUC_SHIFT 24 /**< Shift value for CSEN_MXUC */
-#define _CSEN_CTRL_MXUC_MASK 0x1000000UL /**< Bit mask for CSEN_MXUC */
-#define _CSEN_CTRL_MXUC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
-#define _CSEN_CTRL_MXUC_CONN 0x00000000UL /**< Mode CONN for CSEN_CTRL */
-#define _CSEN_CTRL_MXUC_UNC 0x00000001UL /**< Mode UNC for CSEN_CTRL */
-#define CSEN_CTRL_MXUC_DEFAULT (_CSEN_CTRL_MXUC_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_CTRL */
-#define CSEN_CTRL_MXUC_CONN (_CSEN_CTRL_MXUC_CONN << 24) /**< Shifted mode CONN for CSEN_CTRL */
-#define CSEN_CTRL_MXUC_UNC (_CSEN_CTRL_MXUC_UNC << 24) /**< Shifted mode UNC for CSEN_CTRL */
-#define CSEN_CTRL_EMACMPEN (0x1UL << 25) /**< Greater and Less Than Comparison Using the Exponential Moving Average (EMA) is Enabled */
-#define _CSEN_CTRL_EMACMPEN_SHIFT 25 /**< Shift value for CSEN_EMACMPEN */
-#define _CSEN_CTRL_EMACMPEN_MASK 0x2000000UL /**< Bit mask for CSEN_EMACMPEN */
-#define _CSEN_CTRL_EMACMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
-#define CSEN_CTRL_EMACMPEN_DEFAULT (_CSEN_CTRL_EMACMPEN_DEFAULT << 25) /**< Shifted mode DEFAULT for CSEN_CTRL */
-#define CSEN_CTRL_WARMUPMODE (0x1UL << 26) /**< Select Warmup Mode for CSEN */
-#define _CSEN_CTRL_WARMUPMODE_SHIFT 26 /**< Shift value for CSEN_WARMUPMODE */
-#define _CSEN_CTRL_WARMUPMODE_MASK 0x4000000UL /**< Bit mask for CSEN_WARMUPMODE */
-#define _CSEN_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
-#define _CSEN_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for CSEN_CTRL */
-#define _CSEN_CTRL_WARMUPMODE_KEEPCSENWARM 0x00000001UL /**< Mode KEEPCSENWARM for CSEN_CTRL */
-#define CSEN_CTRL_WARMUPMODE_DEFAULT (_CSEN_CTRL_WARMUPMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for CSEN_CTRL */
-#define CSEN_CTRL_WARMUPMODE_NORMAL (_CSEN_CTRL_WARMUPMODE_NORMAL << 26) /**< Shifted mode NORMAL for CSEN_CTRL */
-#define CSEN_CTRL_WARMUPMODE_KEEPCSENWARM (_CSEN_CTRL_WARMUPMODE_KEEPCSENWARM << 26) /**< Shifted mode KEEPCSENWARM for CSEN_CTRL */
-#define CSEN_CTRL_LOCALSENS (0x1UL << 27) /**< Local Sensing Enable */
-#define _CSEN_CTRL_LOCALSENS_SHIFT 27 /**< Shift value for CSEN_LOCALSENS */
-#define _CSEN_CTRL_LOCALSENS_MASK 0x8000000UL /**< Bit mask for CSEN_LOCALSENS */
-#define _CSEN_CTRL_LOCALSENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
-#define CSEN_CTRL_LOCALSENS_DEFAULT (_CSEN_CTRL_LOCALSENS_DEFAULT << 27) /**< Shifted mode DEFAULT for CSEN_CTRL */
-#define CSEN_CTRL_CPACCURACY (0x1UL << 28) /**< Charge Pump Accuracy */
-#define _CSEN_CTRL_CPACCURACY_SHIFT 28 /**< Shift value for CSEN_CPACCURACY */
-#define _CSEN_CTRL_CPACCURACY_MASK 0x10000000UL /**< Bit mask for CSEN_CPACCURACY */
-#define _CSEN_CTRL_CPACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */
-#define _CSEN_CTRL_CPACCURACY_LO 0x00000000UL /**< Mode LO for CSEN_CTRL */
-#define _CSEN_CTRL_CPACCURACY_HI 0x00000001UL /**< Mode HI for CSEN_CTRL */
-#define CSEN_CTRL_CPACCURACY_DEFAULT (_CSEN_CTRL_CPACCURACY_DEFAULT << 28) /**< Shifted mode DEFAULT for CSEN_CTRL */
-#define CSEN_CTRL_CPACCURACY_LO (_CSEN_CTRL_CPACCURACY_LO << 28) /**< Shifted mode LO for CSEN_CTRL */
-#define CSEN_CTRL_CPACCURACY_HI (_CSEN_CTRL_CPACCURACY_HI << 28) /**< Shifted mode HI for CSEN_CTRL */
-
-/* Bit fields for CSEN TIMCTRL */
-#define _CSEN_TIMCTRL_RESETVALUE 0x00000000UL /**< Default value for CSEN_TIMCTRL */
-#define _CSEN_TIMCTRL_MASK 0x0003FF07UL /**< Mask for CSEN_TIMCTRL */
-#define _CSEN_TIMCTRL_PCPRESC_SHIFT 0 /**< Shift value for CSEN_PCPRESC */
-#define _CSEN_TIMCTRL_PCPRESC_MASK 0x7UL /**< Bit mask for CSEN_PCPRESC */
-#define _CSEN_TIMCTRL_PCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_TIMCTRL */
-#define _CSEN_TIMCTRL_PCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CSEN_TIMCTRL */
-#define _CSEN_TIMCTRL_PCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CSEN_TIMCTRL */
-#define _CSEN_TIMCTRL_PCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for CSEN_TIMCTRL */
-#define _CSEN_TIMCTRL_PCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for CSEN_TIMCTRL */
-#define _CSEN_TIMCTRL_PCPRESC_DIV16 0x00000004UL /**< Mode DIV16 for CSEN_TIMCTRL */
-#define _CSEN_TIMCTRL_PCPRESC_DIV32 0x00000005UL /**< Mode DIV32 for CSEN_TIMCTRL */
-#define _CSEN_TIMCTRL_PCPRESC_DIV64 0x00000006UL /**< Mode DIV64 for CSEN_TIMCTRL */
-#define _CSEN_TIMCTRL_PCPRESC_DIV128 0x00000007UL /**< Mode DIV128 for CSEN_TIMCTRL */
-#define CSEN_TIMCTRL_PCPRESC_DEFAULT (_CSEN_TIMCTRL_PCPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_TIMCTRL */
-#define CSEN_TIMCTRL_PCPRESC_DIV1 (_CSEN_TIMCTRL_PCPRESC_DIV1 << 0) /**< Shifted mode DIV1 for CSEN_TIMCTRL */
-#define CSEN_TIMCTRL_PCPRESC_DIV2 (_CSEN_TIMCTRL_PCPRESC_DIV2 << 0) /**< Shifted mode DIV2 for CSEN_TIMCTRL */
-#define CSEN_TIMCTRL_PCPRESC_DIV4 (_CSEN_TIMCTRL_PCPRESC_DIV4 << 0) /**< Shifted mode DIV4 for CSEN_TIMCTRL */
-#define CSEN_TIMCTRL_PCPRESC_DIV8 (_CSEN_TIMCTRL_PCPRESC_DIV8 << 0) /**< Shifted mode DIV8 for CSEN_TIMCTRL */
-#define CSEN_TIMCTRL_PCPRESC_DIV16 (_CSEN_TIMCTRL_PCPRESC_DIV16 << 0) /**< Shifted mode DIV16 for CSEN_TIMCTRL */
-#define CSEN_TIMCTRL_PCPRESC_DIV32 (_CSEN_TIMCTRL_PCPRESC_DIV32 << 0) /**< Shifted mode DIV32 for CSEN_TIMCTRL */
-#define CSEN_TIMCTRL_PCPRESC_DIV64 (_CSEN_TIMCTRL_PCPRESC_DIV64 << 0) /**< Shifted mode DIV64 for CSEN_TIMCTRL */
-#define CSEN_TIMCTRL_PCPRESC_DIV128 (_CSEN_TIMCTRL_PCPRESC_DIV128 << 0) /**< Shifted mode DIV128 for CSEN_TIMCTRL */
-#define _CSEN_TIMCTRL_PCTOP_SHIFT 8 /**< Shift value for CSEN_PCTOP */
-#define _CSEN_TIMCTRL_PCTOP_MASK 0xFF00UL /**< Bit mask for CSEN_PCTOP */
-#define _CSEN_TIMCTRL_PCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_TIMCTRL */
-#define CSEN_TIMCTRL_PCTOP_DEFAULT (_CSEN_TIMCTRL_PCTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_TIMCTRL */
-#define _CSEN_TIMCTRL_WARMUPCNT_SHIFT 16 /**< Shift value for CSEN_WARMUPCNT */
-#define _CSEN_TIMCTRL_WARMUPCNT_MASK 0x30000UL /**< Bit mask for CSEN_WARMUPCNT */
-#define _CSEN_TIMCTRL_WARMUPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_TIMCTRL */
-#define CSEN_TIMCTRL_WARMUPCNT_DEFAULT (_CSEN_TIMCTRL_WARMUPCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_TIMCTRL */
-
-/* Bit fields for CSEN CMD */
-#define _CSEN_CMD_RESETVALUE 0x00000000UL /**< Default value for CSEN_CMD */
-#define _CSEN_CMD_MASK 0x00000001UL /**< Mask for CSEN_CMD */
-#define CSEN_CMD_START (0x1UL << 0) /**< Start Software-Triggered Conversions */
-#define _CSEN_CMD_START_SHIFT 0 /**< Shift value for CSEN_START */
-#define _CSEN_CMD_START_MASK 0x1UL /**< Bit mask for CSEN_START */
-#define _CSEN_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CMD */
-#define CSEN_CMD_START_DEFAULT (_CSEN_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_CMD */
-
-/* Bit fields for CSEN STATUS */
-#define _CSEN_STATUS_RESETVALUE 0x00000000UL /**< Default value for CSEN_STATUS */
-#define _CSEN_STATUS_MASK 0x00000001UL /**< Mask for CSEN_STATUS */
-#define CSEN_STATUS_CSENBUSY (0x1UL << 0) /**< Busy Flag */
-#define _CSEN_STATUS_CSENBUSY_SHIFT 0 /**< Shift value for CSEN_CSENBUSY */
-#define _CSEN_STATUS_CSENBUSY_MASK 0x1UL /**< Bit mask for CSEN_CSENBUSY */
-#define _CSEN_STATUS_CSENBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_STATUS */
-#define _CSEN_STATUS_CSENBUSY_IDLE 0x00000000UL /**< Mode IDLE for CSEN_STATUS */
-#define _CSEN_STATUS_CSENBUSY_BUSY 0x00000001UL /**< Mode BUSY for CSEN_STATUS */
-#define CSEN_STATUS_CSENBUSY_DEFAULT (_CSEN_STATUS_CSENBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_STATUS */
-#define CSEN_STATUS_CSENBUSY_IDLE (_CSEN_STATUS_CSENBUSY_IDLE << 0) /**< Shifted mode IDLE for CSEN_STATUS */
-#define CSEN_STATUS_CSENBUSY_BUSY (_CSEN_STATUS_CSENBUSY_BUSY << 0) /**< Shifted mode BUSY for CSEN_STATUS */
-
-/* Bit fields for CSEN PRSSEL */
-#define _CSEN_PRSSEL_RESETVALUE 0x00000000UL /**< Default value for CSEN_PRSSEL */
-#define _CSEN_PRSSEL_MASK 0x0000000FUL /**< Mask for CSEN_PRSSEL */
-#define _CSEN_PRSSEL_PRSSEL_SHIFT 0 /**< Shift value for CSEN_PRSSEL */
-#define _CSEN_PRSSEL_PRSSEL_MASK 0xFUL /**< Bit mask for CSEN_PRSSEL */
-#define _CSEN_PRSSEL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_PRSSEL */
-#define _CSEN_PRSSEL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CSEN_PRSSEL */
-#define _CSEN_PRSSEL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CSEN_PRSSEL */
-#define _CSEN_PRSSEL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CSEN_PRSSEL */
-#define _CSEN_PRSSEL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CSEN_PRSSEL */
-#define _CSEN_PRSSEL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CSEN_PRSSEL */
-#define _CSEN_PRSSEL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CSEN_PRSSEL */
-#define _CSEN_PRSSEL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CSEN_PRSSEL */
-#define _CSEN_PRSSEL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CSEN_PRSSEL */
-#define _CSEN_PRSSEL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CSEN_PRSSEL */
-#define _CSEN_PRSSEL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CSEN_PRSSEL */
-#define _CSEN_PRSSEL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CSEN_PRSSEL */
-#define _CSEN_PRSSEL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CSEN_PRSSEL */
-#define CSEN_PRSSEL_PRSSEL_DEFAULT (_CSEN_PRSSEL_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_PRSSEL */
-#define CSEN_PRSSEL_PRSSEL_PRSCH0 (_CSEN_PRSSEL_PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for CSEN_PRSSEL */
-#define CSEN_PRSSEL_PRSSEL_PRSCH1 (_CSEN_PRSSEL_PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for CSEN_PRSSEL */
-#define CSEN_PRSSEL_PRSSEL_PRSCH2 (_CSEN_PRSSEL_PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for CSEN_PRSSEL */
-#define CSEN_PRSSEL_PRSSEL_PRSCH3 (_CSEN_PRSSEL_PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for CSEN_PRSSEL */
-#define CSEN_PRSSEL_PRSSEL_PRSCH4 (_CSEN_PRSSEL_PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for CSEN_PRSSEL */
-#define CSEN_PRSSEL_PRSSEL_PRSCH5 (_CSEN_PRSSEL_PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for CSEN_PRSSEL */
-#define CSEN_PRSSEL_PRSSEL_PRSCH6 (_CSEN_PRSSEL_PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for CSEN_PRSSEL */
-#define CSEN_PRSSEL_PRSSEL_PRSCH7 (_CSEN_PRSSEL_PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for CSEN_PRSSEL */
-#define CSEN_PRSSEL_PRSSEL_PRSCH8 (_CSEN_PRSSEL_PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for CSEN_PRSSEL */
-#define CSEN_PRSSEL_PRSSEL_PRSCH9 (_CSEN_PRSSEL_PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for CSEN_PRSSEL */
-#define CSEN_PRSSEL_PRSSEL_PRSCH10 (_CSEN_PRSSEL_PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for CSEN_PRSSEL */
-#define CSEN_PRSSEL_PRSSEL_PRSCH11 (_CSEN_PRSSEL_PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for CSEN_PRSSEL */
-
-/* Bit fields for CSEN DATA */
-#define _CSEN_DATA_RESETVALUE 0x00000000UL /**< Default value for CSEN_DATA */
-#define _CSEN_DATA_MASK 0xFFFFFFFFUL /**< Mask for CSEN_DATA */
-#define _CSEN_DATA_DATA_SHIFT 0 /**< Shift value for CSEN_DATA */
-#define _CSEN_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for CSEN_DATA */
-#define _CSEN_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DATA */
-#define CSEN_DATA_DATA_DEFAULT (_CSEN_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_DATA */
-
-/* Bit fields for CSEN SCANMASK0 */
-#define _CSEN_SCANMASK0_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANMASK0 */
-#define _CSEN_SCANMASK0_MASK 0xFFFFFFFFUL /**< Mask for CSEN_SCANMASK0 */
-#define _CSEN_SCANMASK0_SCANINPUTEN_SHIFT 0 /**< Shift value for CSEN_SCANINPUTEN */
-#define _CSEN_SCANMASK0_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for CSEN_SCANINPUTEN */
-#define _CSEN_SCANMASK0_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANMASK0 */
-#define CSEN_SCANMASK0_SCANINPUTEN_DEFAULT (_CSEN_SCANMASK0_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANMASK0 */
-
-/* Bit fields for CSEN SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_MASK 0x0F0F0F0FUL /**< Mask for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_SHIFT 0 /**< Shift value for CSEN_INPUT0TO7SEL */
-#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_MASK 0xFUL /**< Bit mask for CSEN_INPUT0TO7SEL */
-#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7 << 0) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15 << 0) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23 << 0) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31 << 0) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7 << 0) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15 << 0) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23 << 0) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31 << 0) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_SHIFT 8 /**< Shift value for CSEN_INPUT8TO15SEL */
-#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_MASK 0xF00UL /**< Bit mask for CSEN_INPUT8TO15SEL */
-#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7 << 8) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15 << 8) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23 << 8) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31 << 8) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7 << 8) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15 << 8) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23 << 8) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31 << 8) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_SHIFT 16 /**< Shift value for CSEN_INPUT16TO23SEL */
-#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_MASK 0xF0000UL /**< Bit mask for CSEN_INPUT16TO23SEL */
-#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7 << 16) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15 << 16) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7 << 16) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15 << 16) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_SHIFT 24 /**< Shift value for CSEN_INPUT24TO31SEL */
-#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_MASK 0xF000000UL /**< Bit mask for CSEN_INPUT24TO31SEL */
-#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
-#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7 << 24) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15 << 24) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7 << 24) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15 << 24) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */
-#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */
-
-/* Bit fields for CSEN SCANMASK1 */
-#define _CSEN_SCANMASK1_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANMASK1 */
-#define _CSEN_SCANMASK1_MASK 0xFFFFFFFFUL /**< Mask for CSEN_SCANMASK1 */
-#define _CSEN_SCANMASK1_SCANINPUTEN_SHIFT 0 /**< Shift value for CSEN_SCANINPUTEN */
-#define _CSEN_SCANMASK1_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for CSEN_SCANINPUTEN */
-#define _CSEN_SCANMASK1_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANMASK1 */
-#define CSEN_SCANMASK1_SCANINPUTEN_DEFAULT (_CSEN_SCANMASK1_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANMASK1 */
-
-/* Bit fields for CSEN SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_MASK 0x0F0F0F0FUL /**< Mask for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_SHIFT 0 /**< Shift value for CSEN_INPUT32TO39SEL */
-#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_MASK 0xFUL /**< Bit mask for CSEN_INPUT32TO39SEL */
-#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7 << 0) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15 << 0) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23 << 0) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31 << 0) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7 << 0) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15 << 0) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23 << 0) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31 << 0) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_SHIFT 8 /**< Shift value for CSEN_INPUT40TO47SEL */
-#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_MASK 0xF00UL /**< Bit mask for CSEN_INPUT40TO47SEL */
-#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7 << 8) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15 << 8) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23 << 8) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31 << 8) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7 << 8) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15 << 8) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23 << 8) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31 << 8) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_SHIFT 16 /**< Shift value for CSEN_INPUT48TO55SEL */
-#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_MASK 0xF0000UL /**< Bit mask for CSEN_INPUT48TO55SEL */
-#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7 << 16) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15 << 16) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7 << 16) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15 << 16) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_SHIFT 24 /**< Shift value for CSEN_INPUT56TO63SEL */
-#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_MASK 0xF000000UL /**< Bit mask for CSEN_INPUT56TO63SEL */
-#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
-#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7 << 24) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15 << 24) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7 << 24) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15 << 24) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */
-#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */
-
-/* Bit fields for CSEN APORTREQ */
-#define _CSEN_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for CSEN_APORTREQ */
-#define _CSEN_APORTREQ_MASK 0x000003FCUL /**< Mask for CSEN_APORTREQ */
-#define CSEN_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 If the Bus Connected to APORT2X is Requested */
-#define _CSEN_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for CSEN_APORT1XREQ */
-#define _CSEN_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for CSEN_APORT1XREQ */
-#define _CSEN_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */
-#define CSEN_APORTREQ_APORT1XREQ_DEFAULT (_CSEN_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
-#define CSEN_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 If the Bus Connected to APORT1X is Requested */
-#define _CSEN_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for CSEN_APORT1YREQ */
-#define _CSEN_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for CSEN_APORT1YREQ */
-#define _CSEN_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */
-#define CSEN_APORTREQ_APORT1YREQ_DEFAULT (_CSEN_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
-#define CSEN_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is Requested */
-#define _CSEN_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for CSEN_APORT2XREQ */
-#define _CSEN_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for CSEN_APORT2XREQ */
-#define _CSEN_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */
-#define CSEN_APORTREQ_APORT2XREQ_DEFAULT (_CSEN_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
-#define CSEN_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is Requested */
-#define _CSEN_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for CSEN_APORT2YREQ */
-#define _CSEN_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for CSEN_APORT2YREQ */
-#define _CSEN_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */
-#define CSEN_APORTREQ_APORT2YREQ_DEFAULT (_CSEN_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
-#define CSEN_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is Requested */
-#define _CSEN_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for CSEN_APORT3XREQ */
-#define _CSEN_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for CSEN_APORT3XREQ */
-#define _CSEN_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */
-#define CSEN_APORTREQ_APORT3XREQ_DEFAULT (_CSEN_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
-#define CSEN_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is Requested */
-#define _CSEN_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for CSEN_APORT3YREQ */
-#define _CSEN_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for CSEN_APORT3YREQ */
-#define _CSEN_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */
-#define CSEN_APORTREQ_APORT3YREQ_DEFAULT (_CSEN_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
-#define CSEN_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is Requested */
-#define _CSEN_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for CSEN_APORT4XREQ */
-#define _CSEN_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for CSEN_APORT4XREQ */
-#define _CSEN_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */
-#define CSEN_APORTREQ_APORT4XREQ_DEFAULT (_CSEN_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
-#define CSEN_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is Requested */
-#define _CSEN_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for CSEN_APORT4YREQ */
-#define _CSEN_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for CSEN_APORT4YREQ */
-#define _CSEN_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */
-#define CSEN_APORTREQ_APORT4YREQ_DEFAULT (_CSEN_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for CSEN_APORTREQ */
-
-/* Bit fields for CSEN APORTCONFLICT */
-#define _CSEN_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for CSEN_APORTCONFLICT */
-#define _CSEN_APORTCONFLICT_MASK 0x000003FCUL /**< Mask for CSEN_APORTCONFLICT */
-#define CSEN_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */
-#define _CSEN_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for CSEN_APORT1XCONFLICT */
-#define _CSEN_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for CSEN_APORT1XCONFLICT */
-#define _CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */
-#define CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
-#define CSEN_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is in Conflict With Another Peripheral */
-#define _CSEN_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for CSEN_APORT1YCONFLICT */
-#define _CSEN_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for CSEN_APORT1YCONFLICT */
-#define _CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */
-#define CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
-#define CSEN_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is in Conflict With Another Peripheral */
-#define _CSEN_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORT2XCONFLICT */
-#define _CSEN_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORT2XCONFLICT */
-#define _CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */
-#define CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
-#define CSEN_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is in Conflict With Another Peripheral */
-#define _CSEN_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for CSEN_APORT2YCONFLICT */
-#define _CSEN_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for CSEN_APORT2YCONFLICT */
-#define _CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */
-#define CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
-#define CSEN_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is in Conflict With Another Peripheral */
-#define _CSEN_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for CSEN_APORT3XCONFLICT */
-#define _CSEN_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for CSEN_APORT3XCONFLICT */
-#define _CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */
-#define CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
-#define CSEN_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is in Conflict With Another Peripheral */
-#define _CSEN_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for CSEN_APORT3YCONFLICT */
-#define _CSEN_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for CSEN_APORT3YCONFLICT */
-#define _CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */
-#define CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
-#define CSEN_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is in Conflict With Another Peripheral */
-#define _CSEN_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for CSEN_APORT4XCONFLICT */
-#define _CSEN_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for CSEN_APORT4XCONFLICT */
-#define _CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */
-#define CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
-#define CSEN_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is in Conflict With Another Peripheral */
-#define _CSEN_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for CSEN_APORT4YCONFLICT */
-#define _CSEN_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for CSEN_APORT4YCONFLICT */
-#define _CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */
-#define CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */
-
-/* Bit fields for CSEN CMPTHR */
-#define _CSEN_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for CSEN_CMPTHR */
-#define _CSEN_CMPTHR_MASK 0x0000FFFFUL /**< Mask for CSEN_CMPTHR */
-#define _CSEN_CMPTHR_CMPTHR_SHIFT 0 /**< Shift value for CSEN_CMPTHR */
-#define _CSEN_CMPTHR_CMPTHR_MASK 0xFFFFUL /**< Bit mask for CSEN_CMPTHR */
-#define _CSEN_CMPTHR_CMPTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CMPTHR */
-#define CSEN_CMPTHR_CMPTHR_DEFAULT (_CSEN_CMPTHR_CMPTHR_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_CMPTHR */
-
-/* Bit fields for CSEN EMA */
-#define _CSEN_EMA_RESETVALUE 0x00000000UL /**< Default value for CSEN_EMA */
-#define _CSEN_EMA_MASK 0x003FFFFFUL /**< Mask for CSEN_EMA */
-#define _CSEN_EMA_EMA_SHIFT 0 /**< Shift value for CSEN_EMA */
-#define _CSEN_EMA_EMA_MASK 0x3FFFFFUL /**< Bit mask for CSEN_EMA */
-#define _CSEN_EMA_EMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_EMA */
-#define CSEN_EMA_EMA_DEFAULT (_CSEN_EMA_EMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_EMA */
-
-/* Bit fields for CSEN EMACTRL */
-#define _CSEN_EMACTRL_RESETVALUE 0x00000000UL /**< Default value for CSEN_EMACTRL */
-#define _CSEN_EMACTRL_MASK 0x00000007UL /**< Mask for CSEN_EMACTRL */
-#define _CSEN_EMACTRL_EMASAMPLE_SHIFT 0 /**< Shift value for CSEN_EMASAMPLE */
-#define _CSEN_EMACTRL_EMASAMPLE_MASK 0x7UL /**< Bit mask for CSEN_EMASAMPLE */
-#define _CSEN_EMACTRL_EMASAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_EMACTRL */
-#define _CSEN_EMACTRL_EMASAMPLE_W1 0x00000000UL /**< Mode W1 for CSEN_EMACTRL */
-#define _CSEN_EMACTRL_EMASAMPLE_W2 0x00000001UL /**< Mode W2 for CSEN_EMACTRL */
-#define _CSEN_EMACTRL_EMASAMPLE_W4 0x00000002UL /**< Mode W4 for CSEN_EMACTRL */
-#define _CSEN_EMACTRL_EMASAMPLE_W8 0x00000003UL /**< Mode W8 for CSEN_EMACTRL */
-#define _CSEN_EMACTRL_EMASAMPLE_W16 0x00000004UL /**< Mode W16 for CSEN_EMACTRL */
-#define _CSEN_EMACTRL_EMASAMPLE_W32 0x00000005UL /**< Mode W32 for CSEN_EMACTRL */
-#define _CSEN_EMACTRL_EMASAMPLE_W64 0x00000006UL /**< Mode W64 for CSEN_EMACTRL */
-#define CSEN_EMACTRL_EMASAMPLE_DEFAULT (_CSEN_EMACTRL_EMASAMPLE_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_EMACTRL */
-#define CSEN_EMACTRL_EMASAMPLE_W1 (_CSEN_EMACTRL_EMASAMPLE_W1 << 0) /**< Shifted mode W1 for CSEN_EMACTRL */
-#define CSEN_EMACTRL_EMASAMPLE_W2 (_CSEN_EMACTRL_EMASAMPLE_W2 << 0) /**< Shifted mode W2 for CSEN_EMACTRL */
-#define CSEN_EMACTRL_EMASAMPLE_W4 (_CSEN_EMACTRL_EMASAMPLE_W4 << 0) /**< Shifted mode W4 for CSEN_EMACTRL */
-#define CSEN_EMACTRL_EMASAMPLE_W8 (_CSEN_EMACTRL_EMASAMPLE_W8 << 0) /**< Shifted mode W8 for CSEN_EMACTRL */
-#define CSEN_EMACTRL_EMASAMPLE_W16 (_CSEN_EMACTRL_EMASAMPLE_W16 << 0) /**< Shifted mode W16 for CSEN_EMACTRL */
-#define CSEN_EMACTRL_EMASAMPLE_W32 (_CSEN_EMACTRL_EMASAMPLE_W32 << 0) /**< Shifted mode W32 for CSEN_EMACTRL */
-#define CSEN_EMACTRL_EMASAMPLE_W64 (_CSEN_EMACTRL_EMASAMPLE_W64 << 0) /**< Shifted mode W64 for CSEN_EMACTRL */
-
-/* Bit fields for CSEN SINGLECTRL */
-#define _CSEN_SINGLECTRL_RESETVALUE 0x00000000UL /**< Default value for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_MASK 0x000007F0UL /**< Mask for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_SHIFT 4 /**< Shift value for CSEN_SINGLESEL */
-#define _CSEN_SINGLECTRL_SINGLESEL_MASK 0x7F0UL /**< Bit mask for CSEN_SINGLESEL */
-#define _CSEN_SINGLECTRL_SINGLESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for CSEN_SINGLECTRL */
-#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_DEFAULT (_CSEN_SINGLECTRL_SINGLESEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0 << 4) /**< Shifted mode APORT1XCH0 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1 << 4) /**< Shifted mode APORT1YCH1 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2 << 4) /**< Shifted mode APORT1XCH2 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3 << 4) /**< Shifted mode APORT1YCH3 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4 << 4) /**< Shifted mode APORT1XCH4 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5 << 4) /**< Shifted mode APORT1YCH5 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6 << 4) /**< Shifted mode APORT1XCH6 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7 << 4) /**< Shifted mode APORT1YCH7 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8 << 4) /**< Shifted mode APORT1XCH8 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9 << 4) /**< Shifted mode APORT1YCH9 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10 << 4) /**< Shifted mode APORT1XCH10 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11 << 4) /**< Shifted mode APORT1YCH11 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12 << 4) /**< Shifted mode APORT1XCH12 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13 << 4) /**< Shifted mode APORT1YCH13 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14 << 4) /**< Shifted mode APORT1XCH14 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15 << 4) /**< Shifted mode APORT1YCH15 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16 << 4) /**< Shifted mode APORT1XCH16 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17 << 4) /**< Shifted mode APORT1YCH17 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18 << 4) /**< Shifted mode APORT1XCH18 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19 << 4) /**< Shifted mode APORT1YCH19 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20 << 4) /**< Shifted mode APORT1XCH20 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21 << 4) /**< Shifted mode APORT1YCH21 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22 << 4) /**< Shifted mode APORT1XCH22 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23 << 4) /**< Shifted mode APORT1YCH23 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24 << 4) /**< Shifted mode APORT1XCH24 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25 << 4) /**< Shifted mode APORT1YCH25 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26 << 4) /**< Shifted mode APORT1XCH26 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27 << 4) /**< Shifted mode APORT1YCH27 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28 << 4) /**< Shifted mode APORT1XCH28 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29 << 4) /**< Shifted mode APORT1YCH29 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30 << 4) /**< Shifted mode APORT1XCH30 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31 << 4) /**< Shifted mode APORT1YCH31 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0 << 4) /**< Shifted mode APORT3XCH0 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1 << 4) /**< Shifted mode APORT3YCH1 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2 << 4) /**< Shifted mode APORT3XCH2 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3 << 4) /**< Shifted mode APORT3YCH3 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4 << 4) /**< Shifted mode APORT3XCH4 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5 << 4) /**< Shifted mode APORT3YCH5 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6 << 4) /**< Shifted mode APORT3XCH6 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7 << 4) /**< Shifted mode APORT3YCH7 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8 << 4) /**< Shifted mode APORT3XCH8 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9 << 4) /**< Shifted mode APORT3YCH9 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10 << 4) /**< Shifted mode APORT3XCH10 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11 << 4) /**< Shifted mode APORT3YCH11 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12 << 4) /**< Shifted mode APORT3XCH12 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13 << 4) /**< Shifted mode APORT3YCH13 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14 << 4) /**< Shifted mode APORT3XCH14 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15 << 4) /**< Shifted mode APORT3YCH15 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16 << 4) /**< Shifted mode APORT3XCH16 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17 << 4) /**< Shifted mode APORT3YCH17 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18 << 4) /**< Shifted mode APORT3XCH18 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19 << 4) /**< Shifted mode APORT3YCH19 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20 << 4) /**< Shifted mode APORT3XCH20 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21 << 4) /**< Shifted mode APORT3YCH21 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22 << 4) /**< Shifted mode APORT3XCH22 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23 << 4) /**< Shifted mode APORT3YCH23 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24 << 4) /**< Shifted mode APORT3XCH24 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25 << 4) /**< Shifted mode APORT3YCH25 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26 << 4) /**< Shifted mode APORT3XCH26 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27 << 4) /**< Shifted mode APORT3YCH27 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28 << 4) /**< Shifted mode APORT3XCH28 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29 << 4) /**< Shifted mode APORT3YCH29 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30 << 4) /**< Shifted mode APORT3XCH30 for CSEN_SINGLECTRL */
-#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31 << 4) /**< Shifted mode APORT3YCH31 for CSEN_SINGLECTRL */
-
-/* Bit fields for CSEN DMBASELINE */
-#define _CSEN_DMBASELINE_RESETVALUE 0x00000000UL /**< Default value for CSEN_DMBASELINE */
-#define _CSEN_DMBASELINE_MASK 0xFFFFFFFFUL /**< Mask for CSEN_DMBASELINE */
-#define _CSEN_DMBASELINE_BASELINEUP_SHIFT 0 /**< Shift value for CSEN_BASELINEUP */
-#define _CSEN_DMBASELINE_BASELINEUP_MASK 0xFFFFUL /**< Bit mask for CSEN_BASELINEUP */
-#define _CSEN_DMBASELINE_BASELINEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMBASELINE */
-#define CSEN_DMBASELINE_BASELINEUP_DEFAULT (_CSEN_DMBASELINE_BASELINEUP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_DMBASELINE */
-#define _CSEN_DMBASELINE_BASELINEDN_SHIFT 16 /**< Shift value for CSEN_BASELINEDN */
-#define _CSEN_DMBASELINE_BASELINEDN_MASK 0xFFFF0000UL /**< Bit mask for CSEN_BASELINEDN */
-#define _CSEN_DMBASELINE_BASELINEDN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMBASELINE */
-#define CSEN_DMBASELINE_BASELINEDN_DEFAULT (_CSEN_DMBASELINE_BASELINEDN_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_DMBASELINE */
-
-/* Bit fields for CSEN DMCFG */
-#define _CSEN_DMCFG_RESETVALUE 0x00000000UL /**< Default value for CSEN_DMCFG */
-#define _CSEN_DMCFG_MASK 0x103F0FFFUL /**< Mask for CSEN_DMCFG */
-#define _CSEN_DMCFG_DMG_SHIFT 0 /**< Shift value for CSEN_DMG */
-#define _CSEN_DMCFG_DMG_MASK 0xFFUL /**< Bit mask for CSEN_DMG */
-#define _CSEN_DMCFG_DMG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */
-#define CSEN_DMCFG_DMG_DEFAULT (_CSEN_DMCFG_DMG_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_DMCFG */
-#define _CSEN_DMCFG_DMR_SHIFT 8 /**< Shift value for CSEN_DMR */
-#define _CSEN_DMCFG_DMR_MASK 0xF00UL /**< Bit mask for CSEN_DMR */
-#define _CSEN_DMCFG_DMR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */
-#define CSEN_DMCFG_DMR_DEFAULT (_CSEN_DMCFG_DMR_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_DMCFG */
-#define _CSEN_DMCFG_DMCR_SHIFT 16 /**< Shift value for CSEN_DMCR */
-#define _CSEN_DMCFG_DMCR_MASK 0xF0000UL /**< Bit mask for CSEN_DMCR */
-#define _CSEN_DMCFG_DMCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */
-#define CSEN_DMCFG_DMCR_DEFAULT (_CSEN_DMCFG_DMCR_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_DMCFG */
-#define _CSEN_DMCFG_CRMODE_SHIFT 20 /**< Shift value for CSEN_CRMODE */
-#define _CSEN_DMCFG_CRMODE_MASK 0x300000UL /**< Bit mask for CSEN_CRMODE */
-#define _CSEN_DMCFG_CRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */
-#define _CSEN_DMCFG_CRMODE_DM10 0x00000000UL /**< Mode DM10 for CSEN_DMCFG */
-#define _CSEN_DMCFG_CRMODE_DM12 0x00000001UL /**< Mode DM12 for CSEN_DMCFG */
-#define _CSEN_DMCFG_CRMODE_DM14 0x00000002UL /**< Mode DM14 for CSEN_DMCFG */
-#define _CSEN_DMCFG_CRMODE_DM16 0x00000003UL /**< Mode DM16 for CSEN_DMCFG */
-#define CSEN_DMCFG_CRMODE_DEFAULT (_CSEN_DMCFG_CRMODE_DEFAULT << 20) /**< Shifted mode DEFAULT for CSEN_DMCFG */
-#define CSEN_DMCFG_CRMODE_DM10 (_CSEN_DMCFG_CRMODE_DM10 << 20) /**< Shifted mode DM10 for CSEN_DMCFG */
-#define CSEN_DMCFG_CRMODE_DM12 (_CSEN_DMCFG_CRMODE_DM12 << 20) /**< Shifted mode DM12 for CSEN_DMCFG */
-#define CSEN_DMCFG_CRMODE_DM14 (_CSEN_DMCFG_CRMODE_DM14 << 20) /**< Shifted mode DM14 for CSEN_DMCFG */
-#define CSEN_DMCFG_CRMODE_DM16 (_CSEN_DMCFG_CRMODE_DM16 << 20) /**< Shifted mode DM16 for CSEN_DMCFG */
-#define CSEN_DMCFG_DMGRDIS (0x1UL << 28) /**< Delta Modulation Gain Step Reduction Disable */
-#define _CSEN_DMCFG_DMGRDIS_SHIFT 28 /**< Shift value for CSEN_DMGRDIS */
-#define _CSEN_DMCFG_DMGRDIS_MASK 0x10000000UL /**< Bit mask for CSEN_DMGRDIS */
-#define _CSEN_DMCFG_DMGRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */
-#define CSEN_DMCFG_DMGRDIS_DEFAULT (_CSEN_DMCFG_DMGRDIS_DEFAULT << 28) /**< Shifted mode DEFAULT for CSEN_DMCFG */
-
-/* Bit fields for CSEN ANACTRL */
-#define _CSEN_ANACTRL_RESETVALUE 0x00000070UL /**< Default value for CSEN_ANACTRL */
-#define _CSEN_ANACTRL_MASK 0x00700770UL /**< Mask for CSEN_ANACTRL */
-#define _CSEN_ANACTRL_IREFPROG_SHIFT 4 /**< Shift value for CSEN_IREFPROG */
-#define _CSEN_ANACTRL_IREFPROG_MASK 0x70UL /**< Bit mask for CSEN_IREFPROG */
-#define _CSEN_ANACTRL_IREFPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for CSEN_ANACTRL */
-#define CSEN_ANACTRL_IREFPROG_DEFAULT (_CSEN_ANACTRL_IREFPROG_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_ANACTRL */
-#define _CSEN_ANACTRL_IDACIREFS_SHIFT 8 /**< Shift value for CSEN_IDACIREFS */
-#define _CSEN_ANACTRL_IDACIREFS_MASK 0x700UL /**< Bit mask for CSEN_IDACIREFS */
-#define _CSEN_ANACTRL_IDACIREFS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */
-#define CSEN_ANACTRL_IDACIREFS_DEFAULT (_CSEN_ANACTRL_IDACIREFS_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_ANACTRL */
-#define _CSEN_ANACTRL_TRSTPROG_SHIFT 20 /**< Shift value for CSEN_TRSTPROG */
-#define _CSEN_ANACTRL_TRSTPROG_MASK 0x700000UL /**< Bit mask for CSEN_TRSTPROG */
-#define _CSEN_ANACTRL_TRSTPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */
-#define CSEN_ANACTRL_TRSTPROG_DEFAULT (_CSEN_ANACTRL_TRSTPROG_DEFAULT << 20) /**< Shifted mode DEFAULT for CSEN_ANACTRL */
-
-/* Bit fields for CSEN IF */
-#define _CSEN_IF_RESETVALUE 0x00000000UL /**< Default value for CSEN_IF */
-#define _CSEN_IF_MASK 0x0000001FUL /**< Mask for CSEN_IF */
-#define CSEN_IF_CMP (0x1UL << 0) /**< Digital Comparator Interrupt Flag */
-#define _CSEN_IF_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */
-#define _CSEN_IF_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */
-#define _CSEN_IF_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */
-#define CSEN_IF_CMP_DEFAULT (_CSEN_IF_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IF */
-#define CSEN_IF_CONV (0x1UL << 1) /**< Conversion Done Interrupt Flag */
-#define _CSEN_IF_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */
-#define _CSEN_IF_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */
-#define _CSEN_IF_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */
-#define CSEN_IF_CONV_DEFAULT (_CSEN_IF_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IF */
-#define CSEN_IF_EOS (0x1UL << 2) /**< End of Scan Interrupt Flag. */
-#define _CSEN_IF_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */
-#define _CSEN_IF_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */
-#define _CSEN_IF_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */
-#define CSEN_IF_EOS_DEFAULT (_CSEN_IF_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IF */
-#define CSEN_IF_DMAOF (0x1UL << 3) /**< DMA Overflow Interrupt Flag. */
-#define _CSEN_IF_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */
-#define _CSEN_IF_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */
-#define _CSEN_IF_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */
-#define CSEN_IF_DMAOF_DEFAULT (_CSEN_IF_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IF */
-#define CSEN_IF_APORTCONFLICT (0x1UL << 4) /**< APORT Conflict Interrupt Flag */
-#define _CSEN_IF_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */
-#define _CSEN_IF_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */
-#define _CSEN_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */
-#define CSEN_IF_APORTCONFLICT_DEFAULT (_CSEN_IF_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IF */
-
-/* Bit fields for CSEN IFS */
-#define _CSEN_IFS_RESETVALUE 0x00000000UL /**< Default value for CSEN_IFS */
-#define _CSEN_IFS_MASK 0x0000001FUL /**< Mask for CSEN_IFS */
-#define CSEN_IFS_CMP (0x1UL << 0) /**< Set CMP Interrupt Flag */
-#define _CSEN_IFS_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */
-#define _CSEN_IFS_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */
-#define _CSEN_IFS_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */
-#define CSEN_IFS_CMP_DEFAULT (_CSEN_IFS_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IFS */
-#define CSEN_IFS_CONV (0x1UL << 1) /**< Set CONV Interrupt Flag */
-#define _CSEN_IFS_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */
-#define _CSEN_IFS_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */
-#define _CSEN_IFS_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */
-#define CSEN_IFS_CONV_DEFAULT (_CSEN_IFS_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IFS */
-#define CSEN_IFS_EOS (0x1UL << 2) /**< Set EOS Interrupt Flag */
-#define _CSEN_IFS_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */
-#define _CSEN_IFS_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */
-#define _CSEN_IFS_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */
-#define CSEN_IFS_EOS_DEFAULT (_CSEN_IFS_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IFS */
-#define CSEN_IFS_DMAOF (0x1UL << 3) /**< Set DMAOF Interrupt Flag */
-#define _CSEN_IFS_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */
-#define _CSEN_IFS_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */
-#define _CSEN_IFS_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */
-#define CSEN_IFS_DMAOF_DEFAULT (_CSEN_IFS_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IFS */
-#define CSEN_IFS_APORTCONFLICT (0x1UL << 4) /**< Set APORTCONFLICT Interrupt Flag */
-#define _CSEN_IFS_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */
-#define _CSEN_IFS_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */
-#define _CSEN_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */
-#define CSEN_IFS_APORTCONFLICT_DEFAULT (_CSEN_IFS_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IFS */
-
-/* Bit fields for CSEN IFC */
-#define _CSEN_IFC_RESETVALUE 0x00000000UL /**< Default value for CSEN_IFC */
-#define _CSEN_IFC_MASK 0x0000001FUL /**< Mask for CSEN_IFC */
-#define CSEN_IFC_CMP (0x1UL << 0) /**< Clear CMP Interrupt Flag */
-#define _CSEN_IFC_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */
-#define _CSEN_IFC_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */
-#define _CSEN_IFC_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */
-#define CSEN_IFC_CMP_DEFAULT (_CSEN_IFC_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IFC */
-#define CSEN_IFC_CONV (0x1UL << 1) /**< Clear CONV Interrupt Flag */
-#define _CSEN_IFC_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */
-#define _CSEN_IFC_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */
-#define _CSEN_IFC_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */
-#define CSEN_IFC_CONV_DEFAULT (_CSEN_IFC_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IFC */
-#define CSEN_IFC_EOS (0x1UL << 2) /**< Clear EOS Interrupt Flag */
-#define _CSEN_IFC_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */
-#define _CSEN_IFC_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */
-#define _CSEN_IFC_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */
-#define CSEN_IFC_EOS_DEFAULT (_CSEN_IFC_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IFC */
-#define CSEN_IFC_DMAOF (0x1UL << 3) /**< Clear DMAOF Interrupt Flag */
-#define _CSEN_IFC_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */
-#define _CSEN_IFC_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */
-#define _CSEN_IFC_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */
-#define CSEN_IFC_DMAOF_DEFAULT (_CSEN_IFC_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IFC */
-#define CSEN_IFC_APORTCONFLICT (0x1UL << 4) /**< Clear APORTCONFLICT Interrupt Flag */
-#define _CSEN_IFC_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */
-#define _CSEN_IFC_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */
-#define _CSEN_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */
-#define CSEN_IFC_APORTCONFLICT_DEFAULT (_CSEN_IFC_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IFC */
-
-/* Bit fields for CSEN IEN */
-#define _CSEN_IEN_RESETVALUE 0x00000000UL /**< Default value for CSEN_IEN */
-#define _CSEN_IEN_MASK 0x0000001FUL /**< Mask for CSEN_IEN */
-#define CSEN_IEN_CMP (0x1UL << 0) /**< CMP Interrupt Enable */
-#define _CSEN_IEN_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */
-#define _CSEN_IEN_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */
-#define _CSEN_IEN_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */
-#define CSEN_IEN_CMP_DEFAULT (_CSEN_IEN_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IEN */
-#define CSEN_IEN_CONV (0x1UL << 1) /**< CONV Interrupt Enable */
-#define _CSEN_IEN_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */
-#define _CSEN_IEN_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */
-#define _CSEN_IEN_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */
-#define CSEN_IEN_CONV_DEFAULT (_CSEN_IEN_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IEN */
-#define CSEN_IEN_EOS (0x1UL << 2) /**< EOS Interrupt Enable */
-#define _CSEN_IEN_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */
-#define _CSEN_IEN_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */
-#define _CSEN_IEN_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */
-#define CSEN_IEN_EOS_DEFAULT (_CSEN_IEN_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IEN */
-#define CSEN_IEN_DMAOF (0x1UL << 3) /**< DMAOF Interrupt Enable */
-#define _CSEN_IEN_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */
-#define _CSEN_IEN_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */
-#define _CSEN_IEN_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */
-#define CSEN_IEN_DMAOF_DEFAULT (_CSEN_IEN_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IEN */
-#define CSEN_IEN_APORTCONFLICT (0x1UL << 4) /**< APORTCONFLICT Interrupt Enable */
-#define _CSEN_IEN_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */
-#define _CSEN_IEN_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */
-#define _CSEN_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */
-#define CSEN_IEN_APORTCONFLICT_DEFAULT (_CSEN_IEN_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IEN */
-
-/** @} */
-/** @} End of group EFR32FG13P_CSEN */
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_devinfo.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_devinfo.h
deleted file mode 100644
index 736aa7c2..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_devinfo.h
+++ /dev/null
@@ -1,1323 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_devinfo.h
- * @brief EFR32FG13P_DEVINFO register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P_DEVINFO Device Information and Calibration
- * @{
- *****************************************************************************/
-
-/** DEVINFO Register Declaration */
-typedef struct {
- __IM uint32_t CAL; /**< CRC of DI-page and calibration temperature */
- uint32_t RESERVED0[7]; /**< Reserved for future use **/
- __IM uint32_t EXTINFO; /**< External Component description */
- uint32_t RESERVED1[1]; /**< Reserved for future use **/
- __IM uint32_t EUI48L; /**< EUI48 OUI and Unique identifier */
- __IM uint32_t EUI48H; /**< OUI */
- __IM uint32_t CUSTOMINFO; /**< Custom information */
- __IM uint32_t MEMINFO; /**< Flash page size and misc. chip information */
- uint32_t RESERVED2[2]; /**< Reserved for future use **/
- __IM uint32_t UNIQUEL; /**< Low 32 bits of device unique number */
- __IM uint32_t UNIQUEH; /**< High 32 bits of device unique number */
- __IM uint32_t MSIZE; /**< Flash and SRAM Memory size in kB */
- __IM uint32_t PART; /**< Part description */
- __IM uint32_t DEVINFOREV; /**< Device information page revision */
- __IM uint32_t EMUTEMP; /**< EMU Temperature Calibration Information */
- uint32_t RESERVED3[2]; /**< Reserved for future use **/
- __IM uint32_t ADC0CAL0; /**< ADC0 calibration register 0 */
- __IM uint32_t ADC0CAL1; /**< ADC0 calibration register 1 */
- __IM uint32_t ADC0CAL2; /**< ADC0 calibration register 2 */
- __IM uint32_t ADC0CAL3; /**< ADC0 calibration register 3 */
- uint32_t RESERVED4[4]; /**< Reserved for future use **/
- __IM uint32_t HFRCOCAL0; /**< HFRCO Calibration Register (4 MHz) */
- uint32_t RESERVED5[2]; /**< Reserved for future use **/
- __IM uint32_t HFRCOCAL3; /**< HFRCO Calibration Register (7 MHz) */
- uint32_t RESERVED6[2]; /**< Reserved for future use **/
- __IM uint32_t HFRCOCAL6; /**< HFRCO Calibration Register (13 MHz) */
- __IM uint32_t HFRCOCAL7; /**< HFRCO Calibration Register (16 MHz) */
- __IM uint32_t HFRCOCAL8; /**< HFRCO Calibration Register (19 MHz) */
- uint32_t RESERVED7[1]; /**< Reserved for future use **/
- __IM uint32_t HFRCOCAL10; /**< HFRCO Calibration Register (26 MHz) */
- __IM uint32_t HFRCOCAL11; /**< HFRCO Calibration Register (32 MHz) */
- __IM uint32_t HFRCOCAL12; /**< HFRCO Calibration Register (38 MHz) */
- uint32_t RESERVED8[11]; /**< Reserved for future use **/
- __IM uint32_t AUXHFRCOCAL0; /**< AUXHFRCO Calibration Register (4 MHz) */
- uint32_t RESERVED9[2]; /**< Reserved for future use **/
- __IM uint32_t AUXHFRCOCAL3; /**< AUXHFRCO Calibration Register (7 MHz) */
- uint32_t RESERVED10[2]; /**< Reserved for future use **/
- __IM uint32_t AUXHFRCOCAL6; /**< AUXHFRCO Calibration Register (13 MHz) */
- __IM uint32_t AUXHFRCOCAL7; /**< AUXHFRCO Calibration Register (16 MHz) */
- __IM uint32_t AUXHFRCOCAL8; /**< AUXHFRCO Calibration Register (19 MHz) */
- uint32_t RESERVED11[1]; /**< Reserved for future use **/
- __IM uint32_t AUXHFRCOCAL10; /**< AUXHFRCO Calibration Register (26 MHz) */
- __IM uint32_t AUXHFRCOCAL11; /**< AUXHFRCO Calibration Register (32 MHz) */
- __IM uint32_t AUXHFRCOCAL12; /**< AUXHFRCO Calibration Register (38 MHz) */
- uint32_t RESERVED12[11]; /**< Reserved for future use **/
- __IM uint32_t VMONCAL0; /**< VMON Calibration Register 0 */
- __IM uint32_t VMONCAL1; /**< VMON Calibration Register 1 */
- __IM uint32_t VMONCAL2; /**< VMON Calibration Register 2 */
- uint32_t RESERVED13[3]; /**< Reserved for future use **/
- __IM uint32_t IDAC0CAL0; /**< IDAC0 Calibration Register 0 */
- __IM uint32_t IDAC0CAL1; /**< IDAC0 Calibration Register 1 */
- uint32_t RESERVED14[2]; /**< Reserved for future use **/
- __IM uint32_t DCDCLNVCTRL0; /**< DCDC Low-noise VREF Trim Register 0 */
- __IM uint32_t DCDCLPVCTRL0; /**< DCDC Low-power VREF Trim Register 0 */
- __IM uint32_t DCDCLPVCTRL1; /**< DCDC Low-power VREF Trim Register 1 */
- __IM uint32_t DCDCLPVCTRL2; /**< DCDC Low-power VREF Trim Register 2 */
- __IM uint32_t DCDCLPVCTRL3; /**< DCDC Low-power VREF Trim Register 3 */
- __IM uint32_t DCDCLPCMPHYSSEL0; /**< DCDC LPCMPHYSSEL Trim Register 0 */
- __IM uint32_t DCDCLPCMPHYSSEL1; /**< DCDC LPCMPHYSSEL Trim Register 1 */
- __IM uint32_t VDAC0MAINCAL; /**< VDAC0 Cals for Main Path */
- __IM uint32_t VDAC0ALTCAL; /**< VDAC0 Cals for Alternate Path */
- __IM uint32_t VDAC0CH1CAL; /**< VDAC0 CH1 Error Cal */
- __IM uint32_t OPA0CAL0; /**< OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */
- __IM uint32_t OPA0CAL1; /**< OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */
- __IM uint32_t OPA0CAL2; /**< OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */
- __IM uint32_t OPA0CAL3; /**< OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */
- __IM uint32_t OPA1CAL0; /**< OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */
- __IM uint32_t OPA1CAL1; /**< OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */
- __IM uint32_t OPA1CAL2; /**< OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */
- __IM uint32_t OPA1CAL3; /**< OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */
- __IM uint32_t OPA2CAL0; /**< OPA2 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */
- __IM uint32_t OPA2CAL1; /**< OPA2 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */
- __IM uint32_t OPA2CAL2; /**< OPA2 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */
- __IM uint32_t OPA2CAL3; /**< OPA2 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */
- __IM uint32_t CSENGAINCAL; /**< Cap Sense Gain Adjustment */
- uint32_t RESERVED15[3]; /**< Reserved for future use **/
- __IM uint32_t OPA0CAL4; /**< OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */
- __IM uint32_t OPA0CAL5; /**< OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */
- __IM uint32_t OPA0CAL6; /**< OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */
- __IM uint32_t OPA0CAL7; /**< OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */
- __IM uint32_t OPA1CAL4; /**< OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */
- __IM uint32_t OPA1CAL5; /**< OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */
- __IM uint32_t OPA1CAL6; /**< OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */
- __IM uint32_t OPA1CAL7; /**< OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */
- __IM uint32_t OPA2CAL4; /**< OPA2 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */
- __IM uint32_t OPA2CAL5; /**< OPA2 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */
- __IM uint32_t OPA2CAL6; /**< OPA2 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */
- __IM uint32_t OPA2CAL7; /**< OPA2 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */
-} DEVINFO_TypeDef; /** @} */
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_DEVINFO
- * @{
- * @defgroup EFR32FG13P_DEVINFO_BitFields DEVINFO Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for DEVINFO CAL */
-#define _DEVINFO_CAL_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_CAL */
-#define _DEVINFO_CAL_CRC_SHIFT 0 /**< Shift value for CRC */
-#define _DEVINFO_CAL_CRC_MASK 0xFFFFUL /**< Bit mask for CRC */
-#define _DEVINFO_CAL_TEMP_SHIFT 16 /**< Shift value for TEMP */
-#define _DEVINFO_CAL_TEMP_MASK 0xFF0000UL /**< Bit mask for TEMP */
-
-/* Bit fields for DEVINFO EXTINFO */
-#define _DEVINFO_EXTINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_EXTINFO */
-#define _DEVINFO_EXTINFO_TYPE_SHIFT 0 /**< Shift value for TYPE */
-#define _DEVINFO_EXTINFO_TYPE_MASK 0xFFUL /**< Bit mask for TYPE */
-#define _DEVINFO_EXTINFO_TYPE_IS25LQ040B 0x00000001UL /**< Mode IS25LQ040B for DEVINFO_EXTINFO */
-#define _DEVINFO_EXTINFO_TYPE_AT25S041 0x00000002UL /**< Mode AT25S041 for DEVINFO_EXTINFO */
-#define _DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */
-#define DEVINFO_EXTINFO_TYPE_IS25LQ040B (_DEVINFO_EXTINFO_TYPE_IS25LQ040B << 0) /**< Shifted mode IS25LQ040B for DEVINFO_EXTINFO */
-#define DEVINFO_EXTINFO_TYPE_AT25S041 (_DEVINFO_EXTINFO_TYPE_AT25S041 << 0) /**< Shifted mode AT25S041 for DEVINFO_EXTINFO */
-#define DEVINFO_EXTINFO_TYPE_NONE (_DEVINFO_EXTINFO_TYPE_NONE << 0) /**< Shifted mode NONE for DEVINFO_EXTINFO */
-#define _DEVINFO_EXTINFO_CONNECTION_SHIFT 8 /**< Shift value for CONNECTION */
-#define _DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL /**< Bit mask for CONNECTION */
-#define _DEVINFO_EXTINFO_CONNECTION_SPI 0x00000001UL /**< Mode SPI for DEVINFO_EXTINFO */
-#define _DEVINFO_EXTINFO_CONNECTION_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */
-#define DEVINFO_EXTINFO_CONNECTION_SPI (_DEVINFO_EXTINFO_CONNECTION_SPI << 8) /**< Shifted mode SPI for DEVINFO_EXTINFO */
-#define DEVINFO_EXTINFO_CONNECTION_NONE (_DEVINFO_EXTINFO_CONNECTION_NONE << 8) /**< Shifted mode NONE for DEVINFO_EXTINFO */
-#define _DEVINFO_EXTINFO_REV_SHIFT 16 /**< Shift value for REV */
-#define _DEVINFO_EXTINFO_REV_MASK 0xFF0000UL /**< Bit mask for REV */
-#define _DEVINFO_EXTINFO_REV_REV1 0x00000001UL /**< Mode REV1 for DEVINFO_EXTINFO */
-#define _DEVINFO_EXTINFO_REV_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */
-#define DEVINFO_EXTINFO_REV_REV1 (_DEVINFO_EXTINFO_REV_REV1 << 16) /**< Shifted mode REV1 for DEVINFO_EXTINFO */
-#define DEVINFO_EXTINFO_REV_NONE (_DEVINFO_EXTINFO_REV_NONE << 16) /**< Shifted mode NONE for DEVINFO_EXTINFO */
-
-/* Bit fields for DEVINFO EUI48L */
-#define _DEVINFO_EUI48L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48L */
-#define _DEVINFO_EUI48L_UNIQUEID_SHIFT 0 /**< Shift value for UNIQUEID */
-#define _DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL /**< Bit mask for UNIQUEID */
-#define _DEVINFO_EUI48L_OUI48L_SHIFT 24 /**< Shift value for OUI48L */
-#define _DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL /**< Bit mask for OUI48L */
-
-/* Bit fields for DEVINFO EUI48H */
-#define _DEVINFO_EUI48H_MASK 0x0000FFFFUL /**< Mask for DEVINFO_EUI48H */
-#define _DEVINFO_EUI48H_OUI48H_SHIFT 0 /**< Shift value for OUI48H */
-#define _DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL /**< Bit mask for OUI48H */
-
-/* Bit fields for DEVINFO CUSTOMINFO */
-#define _DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL /**< Mask for DEVINFO_CUSTOMINFO */
-#define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16 /**< Shift value for PARTNO */
-#define _DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL /**< Bit mask for PARTNO */
-
-/* Bit fields for DEVINFO MEMINFO */
-#define _DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MEMINFO */
-#define _DEVINFO_MEMINFO_TEMPGRADE_SHIFT 0 /**< Shift value for TEMPGRADE */
-#define _DEVINFO_MEMINFO_TEMPGRADE_MASK 0xFFUL /**< Bit mask for TEMPGRADE */
-#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO85 0x00000000UL /**< Mode N40TO85 for DEVINFO_MEMINFO */
-#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO125 0x00000001UL /**< Mode N40TO125 for DEVINFO_MEMINFO */
-#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO105 0x00000002UL /**< Mode N40TO105 for DEVINFO_MEMINFO */
-#define _DEVINFO_MEMINFO_TEMPGRADE_N0TO70 0x00000003UL /**< Mode N0TO70 for DEVINFO_MEMINFO */
-#define DEVINFO_MEMINFO_TEMPGRADE_N40TO85 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO85 << 0) /**< Shifted mode N40TO85 for DEVINFO_MEMINFO */
-#define DEVINFO_MEMINFO_TEMPGRADE_N40TO125 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO125 << 0) /**< Shifted mode N40TO125 for DEVINFO_MEMINFO */
-#define DEVINFO_MEMINFO_TEMPGRADE_N40TO105 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO105 << 0) /**< Shifted mode N40TO105 for DEVINFO_MEMINFO */
-#define DEVINFO_MEMINFO_TEMPGRADE_N0TO70 (_DEVINFO_MEMINFO_TEMPGRADE_N0TO70 << 0) /**< Shifted mode N0TO70 for DEVINFO_MEMINFO */
-#define _DEVINFO_MEMINFO_PKGTYPE_SHIFT 8 /**< Shift value for PKGTYPE */
-#define _DEVINFO_MEMINFO_PKGTYPE_MASK 0xFF00UL /**< Bit mask for PKGTYPE */
-#define _DEVINFO_MEMINFO_PKGTYPE_WLCSP 0x0000004AUL /**< Mode WLCSP for DEVINFO_MEMINFO */
-#define _DEVINFO_MEMINFO_PKGTYPE_BGA 0x0000004CUL /**< Mode BGA for DEVINFO_MEMINFO */
-#define _DEVINFO_MEMINFO_PKGTYPE_QFN 0x0000004DUL /**< Mode QFN for DEVINFO_MEMINFO */
-#define _DEVINFO_MEMINFO_PKGTYPE_QFP 0x00000051UL /**< Mode QFP for DEVINFO_MEMINFO */
-#define DEVINFO_MEMINFO_PKGTYPE_WLCSP (_DEVINFO_MEMINFO_PKGTYPE_WLCSP << 8) /**< Shifted mode WLCSP for DEVINFO_MEMINFO */
-#define DEVINFO_MEMINFO_PKGTYPE_BGA (_DEVINFO_MEMINFO_PKGTYPE_BGA << 8) /**< Shifted mode BGA for DEVINFO_MEMINFO */
-#define DEVINFO_MEMINFO_PKGTYPE_QFN (_DEVINFO_MEMINFO_PKGTYPE_QFN << 8) /**< Shifted mode QFN for DEVINFO_MEMINFO */
-#define DEVINFO_MEMINFO_PKGTYPE_QFP (_DEVINFO_MEMINFO_PKGTYPE_QFP << 8) /**< Shifted mode QFP for DEVINFO_MEMINFO */
-#define _DEVINFO_MEMINFO_PINCOUNT_SHIFT 16 /**< Shift value for PINCOUNT */
-#define _DEVINFO_MEMINFO_PINCOUNT_MASK 0xFF0000UL /**< Bit mask for PINCOUNT */
-#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24 /**< Shift value for FLASH_PAGE_SIZE */
-#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL /**< Bit mask for FLASH_PAGE_SIZE */
-
-/* Bit fields for DEVINFO UNIQUEL */
-#define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEL */
-#define _DEVINFO_UNIQUEL_UNIQUEL_SHIFT 0 /**< Shift value for UNIQUEL */
-#define _DEVINFO_UNIQUEL_UNIQUEL_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEL */
-
-/* Bit fields for DEVINFO UNIQUEH */
-#define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEH */
-#define _DEVINFO_UNIQUEH_UNIQUEH_SHIFT 0 /**< Shift value for UNIQUEH */
-#define _DEVINFO_UNIQUEH_UNIQUEH_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEH */
-
-/* Bit fields for DEVINFO MSIZE */
-#define _DEVINFO_MSIZE_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MSIZE */
-#define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Shift value for FLASH */
-#define _DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL /**< Bit mask for FLASH */
-#define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Shift value for SRAM */
-#define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL /**< Bit mask for SRAM */
-
-/* Bit fields for DEVINFO PART */
-#define _DEVINFO_PART_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /**< Shift value for DEVICE_NUMBER */
-#define _DEVINFO_PART_DEVICE_NUMBER_MASK 0xFFFFUL /**< Bit mask for DEVICE_NUMBER */
-#define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16 /**< Shift value for DEVICE_FAMILY */
-#define _DEVINFO_PART_DEVICE_FAMILY_MASK 0xFF0000UL /**< Bit mask for DEVICE_FAMILY */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P 0x00000010UL /**< Mode EFR32MG1P for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B 0x00000011UL /**< Mode EFR32MG1B for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V 0x00000012UL /**< Mode EFR32MG1V for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P 0x00000013UL /**< Mode EFR32BG1P for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B 0x00000014UL /**< Mode EFR32BG1B for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V 0x00000015UL /**< Mode EFR32BG1V for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P 0x00000019UL /**< Mode EFR32FG1P for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B 0x0000001AUL /**< Mode EFR32FG1B for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V 0x0000001BUL /**< Mode EFR32FG1V for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P 0x0000001CUL /**< Mode EFR32MG12P for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B 0x0000001DUL /**< Mode EFR32MG12B for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V 0x0000001EUL /**< Mode EFR32MG12V for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P 0x0000001FUL /**< Mode EFR32BG12P for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B 0x00000020UL /**< Mode EFR32BG12B for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V 0x00000021UL /**< Mode EFR32BG12V for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P 0x00000025UL /**< Mode EFR32FG12P for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B 0x00000026UL /**< Mode EFR32FG12B for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V 0x00000027UL /**< Mode EFR32FG12V for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P 0x00000028UL /**< Mode EFR32MG13P for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B 0x00000029UL /**< Mode EFR32MG13B for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V 0x0000002AUL /**< Mode EFR32MG13V for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P 0x0000002BUL /**< Mode EFR32BG13P for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B 0x0000002CUL /**< Mode EFR32BG13B for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V 0x0000002DUL /**< Mode EFR32BG13V for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P 0x00000031UL /**< Mode EFR32FG13P for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B 0x00000032UL /**< Mode EFR32FG13B for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V 0x00000033UL /**< Mode EFR32FG13V for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P 0x00000034UL /**< Mode EFR32MG14P for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B 0x00000035UL /**< Mode EFR32MG14B for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V 0x00000036UL /**< Mode EFR32MG14V for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P 0x00000037UL /**< Mode EFR32BG14P for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B 0x00000038UL /**< Mode EFR32BG14B for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V 0x00000039UL /**< Mode EFR32BG14V for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P 0x0000003DUL /**< Mode EFR32FG14P for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B 0x0000003EUL /**< Mode EFR32FG14B for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V 0x0000003FUL /**< Mode EFR32FG14V for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 0x00000047UL /**< Mode EFM32G for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_G 0x00000047UL /**< Mode G for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_GG 0x00000048UL /**< Mode GG for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL /**< Mode TG for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 0x00000049UL /**< Mode EFM32TG for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 0x0000004AUL /**< Mode EFM32LG for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_LG 0x0000004AUL /**< Mode LG for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_WG 0x0000004BUL /**< Mode WG for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_ZG 0x0000004CUL /**< Mode ZG for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 0x0000004CUL /**< Mode EFM32ZG for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL /**< Mode HG for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 0x0000004DUL /**< Mode EFM32HG for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B 0x00000051UL /**< Mode EFM32PG1B for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B 0x00000055UL /**< Mode EFM32PG12B for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B 0x00000057UL /**< Mode EFM32JG12B for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B 0x00000064UL /**< Mode EFM32GG11B for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B 0x00000067UL /**< Mode EFM32TG11B for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 0x00000078UL /**< Mode EZR32LG for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 0x00000079UL /**< Mode EZR32WG for DEVINFO_PART */
-#define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 0x0000007AUL /**< Mode EZR32HG for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P << 16) /**< Shifted mode EFR32MG1P for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B << 16) /**< Shifted mode EFR32MG1B for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V << 16) /**< Shifted mode EFR32MG1V for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P << 16) /**< Shifted mode EFR32BG1P for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B << 16) /**< Shifted mode EFR32BG1B for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V << 16) /**< Shifted mode EFR32BG1V for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P << 16) /**< Shifted mode EFR32FG1P for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B << 16) /**< Shifted mode EFR32FG1B for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V << 16) /**< Shifted mode EFR32FG1V for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P << 16) /**< Shifted mode EFR32MG12P for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B << 16) /**< Shifted mode EFR32MG12B for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V << 16) /**< Shifted mode EFR32MG12V for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P << 16) /**< Shifted mode EFR32BG12P for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B << 16) /**< Shifted mode EFR32BG12B for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V << 16) /**< Shifted mode EFR32BG12V for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P << 16) /**< Shifted mode EFR32FG12P for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B << 16) /**< Shifted mode EFR32FG12B for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V << 16) /**< Shifted mode EFR32FG12V for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P << 16) /**< Shifted mode EFR32MG13P for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B << 16) /**< Shifted mode EFR32MG13B for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V << 16) /**< Shifted mode EFR32MG13V for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P << 16) /**< Shifted mode EFR32BG13P for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B << 16) /**< Shifted mode EFR32BG13B for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V << 16) /**< Shifted mode EFR32BG13V for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P << 16) /**< Shifted mode EFR32FG13P for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B << 16) /**< Shifted mode EFR32FG13B for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V << 16) /**< Shifted mode EFR32FG13V for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P << 16) /**< Shifted mode EFR32MG14P for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B << 16) /**< Shifted mode EFR32MG14B for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V << 16) /**< Shifted mode EFR32MG14V for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P << 16) /**< Shifted mode EFR32BG14P for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B << 16) /**< Shifted mode EFR32BG14B for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V << 16) /**< Shifted mode EFR32BG14V for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P << 16) /**< Shifted mode EFR32FG14P for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B << 16) /**< Shifted mode EFR32FG14B for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V << 16) /**< Shifted mode EFR32FG14V for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFM32G (_DEVINFO_PART_DEVICE_FAMILY_EFM32G << 16) /**< Shifted mode EFM32G for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_G (_DEVINFO_PART_DEVICE_FAMILY_G << 16) /**< Shifted mode G for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFM32GG (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_GG (_DEVINFO_PART_DEVICE_FAMILY_GG << 16) /**< Shifted mode GG for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_TG (_DEVINFO_PART_DEVICE_FAMILY_TG << 16) /**< Shifted mode TG for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFM32TG (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG << 16) /**< Shifted mode EFM32TG for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFM32LG (_DEVINFO_PART_DEVICE_FAMILY_EFM32LG << 16) /**< Shifted mode EFM32LG for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_LG (_DEVINFO_PART_DEVICE_FAMILY_LG << 16) /**< Shifted mode LG for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFM32WG (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_WG (_DEVINFO_PART_DEVICE_FAMILY_WG << 16) /**< Shifted mode WG for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_ZG (_DEVINFO_PART_DEVICE_FAMILY_ZG << 16) /**< Shifted mode ZG for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFM32ZG (_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG << 16) /**< Shifted mode EFM32ZG for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_HG (_DEVINFO_PART_DEVICE_FAMILY_HG << 16) /**< Shifted mode HG for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFM32HG (_DEVINFO_PART_DEVICE_FAMILY_EFM32HG << 16) /**< Shifted mode EFM32HG for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B << 16) /**< Shifted mode EFM32PG12B for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B << 16) /**< Shifted mode EFM32JG12B for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B << 16) /**< Shifted mode EFM32GG11B for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B << 16) /**< Shifted mode EFM32TG11B for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EZR32LG (_DEVINFO_PART_DEVICE_FAMILY_EZR32LG << 16) /**< Shifted mode EZR32LG for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EZR32WG (_DEVINFO_PART_DEVICE_FAMILY_EZR32WG << 16) /**< Shifted mode EZR32WG for DEVINFO_PART */
-#define DEVINFO_PART_DEVICE_FAMILY_EZR32HG (_DEVINFO_PART_DEVICE_FAMILY_EZR32HG << 16) /**< Shifted mode EZR32HG for DEVINFO_PART */
-#define _DEVINFO_PART_PROD_REV_SHIFT 24 /**< Shift value for PROD_REV */
-#define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL /**< Bit mask for PROD_REV */
-
-/* Bit fields for DEVINFO DEVINFOREV */
-#define _DEVINFO_DEVINFOREV_MASK 0x000000FFUL /**< Mask for DEVINFO_DEVINFOREV */
-#define _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT 0 /**< Shift value for DEVINFOREV */
-#define _DEVINFO_DEVINFOREV_DEVINFOREV_MASK 0xFFUL /**< Bit mask for DEVINFOREV */
-
-/* Bit fields for DEVINFO EMUTEMP */
-#define _DEVINFO_EMUTEMP_MASK 0x000000FFUL /**< Mask for DEVINFO_EMUTEMP */
-#define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 0 /**< Shift value for EMUTEMPROOM */
-#define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0xFFUL /**< Bit mask for EMUTEMPROOM */
-
-/* Bit fields for DEVINFO ADC0CAL0 */
-#define _DEVINFO_ADC0CAL0_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL0 */
-#define _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT 0 /**< Shift value for OFFSET1V25 */
-#define _DEVINFO_ADC0CAL0_OFFSET1V25_MASK 0xFUL /**< Bit mask for OFFSET1V25 */
-#define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT 4 /**< Shift value for NEGSEOFFSET1V25 */
-#define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET1V25 */
-#define _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT 8 /**< Shift value for GAIN1V25 */
-#define _DEVINFO_ADC0CAL0_GAIN1V25_MASK 0x7F00UL /**< Bit mask for GAIN1V25 */
-#define _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT 16 /**< Shift value for OFFSET2V5 */
-#define _DEVINFO_ADC0CAL0_OFFSET2V5_MASK 0xF0000UL /**< Bit mask for OFFSET2V5 */
-#define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT 20 /**< Shift value for NEGSEOFFSET2V5 */
-#define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET2V5 */
-#define _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT 24 /**< Shift value for GAIN2V5 */
-#define _DEVINFO_ADC0CAL0_GAIN2V5_MASK 0x7F000000UL /**< Bit mask for GAIN2V5 */
-
-/* Bit fields for DEVINFO ADC0CAL1 */
-#define _DEVINFO_ADC0CAL1_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL1 */
-#define _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT 0 /**< Shift value for OFFSETVDD */
-#define _DEVINFO_ADC0CAL1_OFFSETVDD_MASK 0xFUL /**< Bit mask for OFFSETVDD */
-#define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT 4 /**< Shift value for NEGSEOFFSETVDD */
-#define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSETVDD */
-#define _DEVINFO_ADC0CAL1_GAINVDD_SHIFT 8 /**< Shift value for GAINVDD */
-#define _DEVINFO_ADC0CAL1_GAINVDD_MASK 0x7F00UL /**< Bit mask for GAINVDD */
-#define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT 16 /**< Shift value for OFFSET5VDIFF */
-#define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK 0xF0000UL /**< Bit mask for OFFSET5VDIFF */
-#define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT 20 /**< Shift value for NEGSEOFFSET5VDIFF */
-#define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET5VDIFF */
-#define _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT 24 /**< Shift value for GAIN5VDIFF */
-#define _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK 0x7F000000UL /**< Bit mask for GAIN5VDIFF */
-
-/* Bit fields for DEVINFO ADC0CAL2 */
-#define _DEVINFO_ADC0CAL2_MASK 0x000000FFUL /**< Mask for DEVINFO_ADC0CAL2 */
-#define _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT 0 /**< Shift value for OFFSET2XVDD */
-#define _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK 0xFUL /**< Bit mask for OFFSET2XVDD */
-#define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT 4 /**< Shift value for NEGSEOFFSET2XVDD */
-#define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET2XVDD */
-
-/* Bit fields for DEVINFO ADC0CAL3 */
-#define _DEVINFO_ADC0CAL3_MASK 0x0000FFF0UL /**< Mask for DEVINFO_ADC0CAL3 */
-#define _DEVINFO_ADC0CAL3_TEMPREAD1V25_SHIFT 4 /**< Shift value for TEMPREAD1V25 */
-#define _DEVINFO_ADC0CAL3_TEMPREAD1V25_MASK 0xFFF0UL /**< Bit mask for TEMPREAD1V25 */
-
-/* Bit fields for DEVINFO HFRCOCAL0 */
-#define _DEVINFO_HFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL0 */
-#define _DEVINFO_HFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */
-#define _DEVINFO_HFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
-#define _DEVINFO_HFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
-#define _DEVINFO_HFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
-#define _DEVINFO_HFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
-#define _DEVINFO_HFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
-#define _DEVINFO_HFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
-#define _DEVINFO_HFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
-#define _DEVINFO_HFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
-#define _DEVINFO_HFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
-#define _DEVINFO_HFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
-#define _DEVINFO_HFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
-#define _DEVINFO_HFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
-#define _DEVINFO_HFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
-#define _DEVINFO_HFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
-#define _DEVINFO_HFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
-
-/* Bit fields for DEVINFO HFRCOCAL3 */
-#define _DEVINFO_HFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL3 */
-#define _DEVINFO_HFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */
-#define _DEVINFO_HFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
-#define _DEVINFO_HFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
-#define _DEVINFO_HFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
-#define _DEVINFO_HFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
-#define _DEVINFO_HFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
-#define _DEVINFO_HFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
-#define _DEVINFO_HFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
-#define _DEVINFO_HFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
-#define _DEVINFO_HFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
-#define _DEVINFO_HFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
-#define _DEVINFO_HFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
-#define _DEVINFO_HFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
-#define _DEVINFO_HFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
-#define _DEVINFO_HFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
-#define _DEVINFO_HFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
-
-/* Bit fields for DEVINFO HFRCOCAL6 */
-#define _DEVINFO_HFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL6 */
-#define _DEVINFO_HFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */
-#define _DEVINFO_HFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
-#define _DEVINFO_HFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
-#define _DEVINFO_HFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
-#define _DEVINFO_HFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
-#define _DEVINFO_HFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
-#define _DEVINFO_HFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
-#define _DEVINFO_HFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
-#define _DEVINFO_HFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
-#define _DEVINFO_HFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
-#define _DEVINFO_HFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
-#define _DEVINFO_HFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
-#define _DEVINFO_HFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
-#define _DEVINFO_HFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
-#define _DEVINFO_HFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
-#define _DEVINFO_HFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
-
-/* Bit fields for DEVINFO HFRCOCAL7 */
-#define _DEVINFO_HFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL7 */
-#define _DEVINFO_HFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */
-#define _DEVINFO_HFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
-#define _DEVINFO_HFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
-#define _DEVINFO_HFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
-#define _DEVINFO_HFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
-#define _DEVINFO_HFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
-#define _DEVINFO_HFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
-#define _DEVINFO_HFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
-#define _DEVINFO_HFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
-#define _DEVINFO_HFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
-#define _DEVINFO_HFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
-#define _DEVINFO_HFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
-#define _DEVINFO_HFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
-#define _DEVINFO_HFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
-#define _DEVINFO_HFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
-#define _DEVINFO_HFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
-
-/* Bit fields for DEVINFO HFRCOCAL8 */
-#define _DEVINFO_HFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL8 */
-#define _DEVINFO_HFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */
-#define _DEVINFO_HFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
-#define _DEVINFO_HFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
-#define _DEVINFO_HFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
-#define _DEVINFO_HFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
-#define _DEVINFO_HFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
-#define _DEVINFO_HFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
-#define _DEVINFO_HFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
-#define _DEVINFO_HFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
-#define _DEVINFO_HFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
-#define _DEVINFO_HFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
-#define _DEVINFO_HFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
-#define _DEVINFO_HFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
-#define _DEVINFO_HFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
-#define _DEVINFO_HFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
-#define _DEVINFO_HFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
-
-/* Bit fields for DEVINFO HFRCOCAL10 */
-#define _DEVINFO_HFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL10 */
-#define _DEVINFO_HFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */
-#define _DEVINFO_HFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
-#define _DEVINFO_HFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
-#define _DEVINFO_HFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
-#define _DEVINFO_HFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
-#define _DEVINFO_HFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
-#define _DEVINFO_HFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
-#define _DEVINFO_HFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
-#define _DEVINFO_HFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
-#define _DEVINFO_HFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
-#define _DEVINFO_HFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
-#define _DEVINFO_HFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
-#define _DEVINFO_HFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
-#define _DEVINFO_HFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
-#define _DEVINFO_HFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
-#define _DEVINFO_HFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
-
-/* Bit fields for DEVINFO HFRCOCAL11 */
-#define _DEVINFO_HFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL11 */
-#define _DEVINFO_HFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */
-#define _DEVINFO_HFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
-#define _DEVINFO_HFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
-#define _DEVINFO_HFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
-#define _DEVINFO_HFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
-#define _DEVINFO_HFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
-#define _DEVINFO_HFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
-#define _DEVINFO_HFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
-#define _DEVINFO_HFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
-#define _DEVINFO_HFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
-#define _DEVINFO_HFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
-#define _DEVINFO_HFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
-#define _DEVINFO_HFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
-#define _DEVINFO_HFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
-#define _DEVINFO_HFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
-#define _DEVINFO_HFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
-
-/* Bit fields for DEVINFO HFRCOCAL12 */
-#define _DEVINFO_HFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL12 */
-#define _DEVINFO_HFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */
-#define _DEVINFO_HFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
-#define _DEVINFO_HFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
-#define _DEVINFO_HFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
-#define _DEVINFO_HFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
-#define _DEVINFO_HFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
-#define _DEVINFO_HFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
-#define _DEVINFO_HFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
-#define _DEVINFO_HFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
-#define _DEVINFO_HFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
-#define _DEVINFO_HFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
-#define _DEVINFO_HFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
-#define _DEVINFO_HFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
-#define _DEVINFO_HFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
-#define _DEVINFO_HFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
-#define _DEVINFO_HFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
-
-/* Bit fields for DEVINFO AUXHFRCOCAL0 */
-#define _DEVINFO_AUXHFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL0 */
-#define _DEVINFO_AUXHFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */
-#define _DEVINFO_AUXHFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
-#define _DEVINFO_AUXHFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
-#define _DEVINFO_AUXHFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
-#define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
-#define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
-#define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
-#define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
-#define _DEVINFO_AUXHFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
-#define _DEVINFO_AUXHFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
-#define _DEVINFO_AUXHFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
-#define _DEVINFO_AUXHFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
-#define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
-#define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
-#define _DEVINFO_AUXHFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
-#define _DEVINFO_AUXHFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
-
-/* Bit fields for DEVINFO AUXHFRCOCAL3 */
-#define _DEVINFO_AUXHFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL3 */
-#define _DEVINFO_AUXHFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */
-#define _DEVINFO_AUXHFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
-#define _DEVINFO_AUXHFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
-#define _DEVINFO_AUXHFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
-#define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
-#define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
-#define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
-#define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
-#define _DEVINFO_AUXHFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
-#define _DEVINFO_AUXHFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
-#define _DEVINFO_AUXHFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
-#define _DEVINFO_AUXHFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
-#define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
-#define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
-#define _DEVINFO_AUXHFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
-#define _DEVINFO_AUXHFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
-
-/* Bit fields for DEVINFO AUXHFRCOCAL6 */
-#define _DEVINFO_AUXHFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL6 */
-#define _DEVINFO_AUXHFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */
-#define _DEVINFO_AUXHFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
-#define _DEVINFO_AUXHFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
-#define _DEVINFO_AUXHFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
-#define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
-#define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
-#define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
-#define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
-#define _DEVINFO_AUXHFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
-#define _DEVINFO_AUXHFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
-#define _DEVINFO_AUXHFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
-#define _DEVINFO_AUXHFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
-#define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
-#define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
-#define _DEVINFO_AUXHFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
-#define _DEVINFO_AUXHFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
-
-/* Bit fields for DEVINFO AUXHFRCOCAL7 */
-#define _DEVINFO_AUXHFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL7 */
-#define _DEVINFO_AUXHFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */
-#define _DEVINFO_AUXHFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
-#define _DEVINFO_AUXHFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
-#define _DEVINFO_AUXHFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
-#define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
-#define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
-#define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
-#define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
-#define _DEVINFO_AUXHFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
-#define _DEVINFO_AUXHFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
-#define _DEVINFO_AUXHFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
-#define _DEVINFO_AUXHFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
-#define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
-#define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
-#define _DEVINFO_AUXHFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
-#define _DEVINFO_AUXHFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
-
-/* Bit fields for DEVINFO AUXHFRCOCAL8 */
-#define _DEVINFO_AUXHFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL8 */
-#define _DEVINFO_AUXHFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */
-#define _DEVINFO_AUXHFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
-#define _DEVINFO_AUXHFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
-#define _DEVINFO_AUXHFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
-#define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
-#define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
-#define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
-#define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
-#define _DEVINFO_AUXHFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
-#define _DEVINFO_AUXHFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
-#define _DEVINFO_AUXHFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
-#define _DEVINFO_AUXHFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
-#define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
-#define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
-#define _DEVINFO_AUXHFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
-#define _DEVINFO_AUXHFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
-
-/* Bit fields for DEVINFO AUXHFRCOCAL10 */
-#define _DEVINFO_AUXHFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL10 */
-#define _DEVINFO_AUXHFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */
-#define _DEVINFO_AUXHFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
-#define _DEVINFO_AUXHFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
-#define _DEVINFO_AUXHFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
-#define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
-#define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
-#define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
-#define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
-#define _DEVINFO_AUXHFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
-#define _DEVINFO_AUXHFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
-#define _DEVINFO_AUXHFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
-#define _DEVINFO_AUXHFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
-#define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
-#define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
-#define _DEVINFO_AUXHFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
-#define _DEVINFO_AUXHFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
-
-/* Bit fields for DEVINFO AUXHFRCOCAL11 */
-#define _DEVINFO_AUXHFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL11 */
-#define _DEVINFO_AUXHFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */
-#define _DEVINFO_AUXHFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
-#define _DEVINFO_AUXHFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
-#define _DEVINFO_AUXHFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
-#define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
-#define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
-#define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
-#define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
-#define _DEVINFO_AUXHFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
-#define _DEVINFO_AUXHFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
-#define _DEVINFO_AUXHFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
-#define _DEVINFO_AUXHFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
-#define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
-#define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
-#define _DEVINFO_AUXHFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
-#define _DEVINFO_AUXHFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
-
-/* Bit fields for DEVINFO AUXHFRCOCAL12 */
-#define _DEVINFO_AUXHFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL12 */
-#define _DEVINFO_AUXHFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */
-#define _DEVINFO_AUXHFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
-#define _DEVINFO_AUXHFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
-#define _DEVINFO_AUXHFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
-#define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
-#define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
-#define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
-#define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
-#define _DEVINFO_AUXHFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
-#define _DEVINFO_AUXHFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
-#define _DEVINFO_AUXHFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
-#define _DEVINFO_AUXHFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
-#define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
-#define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
-#define _DEVINFO_AUXHFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
-#define _DEVINFO_AUXHFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
-
-/* Bit fields for DEVINFO VMONCAL0 */
-#define _DEVINFO_VMONCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL0 */
-#define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT 0 /**< Shift value for AVDD1V86THRESFINE */
-#define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for AVDD1V86THRESFINE */
-#define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for AVDD1V86THRESCOARSE */
-#define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for AVDD1V86THRESCOARSE */
-#define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT 8 /**< Shift value for AVDD2V98THRESFINE */
-#define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for AVDD2V98THRESFINE */
-#define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for AVDD2V98THRESCOARSE */
-#define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for AVDD2V98THRESCOARSE */
-#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT 16 /**< Shift value for ALTAVDD1V86THRESFINE */
-#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK 0xF0000UL /**< Bit mask for ALTAVDD1V86THRESFINE */
-#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT 20 /**< Shift value for ALTAVDD1V86THRESCOARSE */
-#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for ALTAVDD1V86THRESCOARSE */
-#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT 24 /**< Shift value for ALTAVDD2V98THRESFINE */
-#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK 0xF000000UL /**< Bit mask for ALTAVDD2V98THRESFINE */
-#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT 28 /**< Shift value for ALTAVDD2V98THRESCOARSE */
-#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for ALTAVDD2V98THRESCOARSE */
-
-/* Bit fields for DEVINFO VMONCAL1 */
-#define _DEVINFO_VMONCAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL1 */
-#define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT 0 /**< Shift value for DVDD1V86THRESFINE */
-#define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for DVDD1V86THRESFINE */
-#define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for DVDD1V86THRESCOARSE */
-#define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for DVDD1V86THRESCOARSE */
-#define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT 8 /**< Shift value for DVDD2V98THRESFINE */
-#define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for DVDD2V98THRESFINE */
-#define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for DVDD2V98THRESCOARSE */
-#define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for DVDD2V98THRESCOARSE */
-#define _DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT 16 /**< Shift value for IO01V86THRESFINE */
-#define _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK 0xF0000UL /**< Bit mask for IO01V86THRESFINE */
-#define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT 20 /**< Shift value for IO01V86THRESCOARSE */
-#define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for IO01V86THRESCOARSE */
-#define _DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT 24 /**< Shift value for IO02V98THRESFINE */
-#define _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK 0xF000000UL /**< Bit mask for IO02V98THRESFINE */
-#define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT 28 /**< Shift value for IO02V98THRESCOARSE */
-#define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for IO02V98THRESCOARSE */
-
-/* Bit fields for DEVINFO VMONCAL2 */
-#define _DEVINFO_VMONCAL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL2 */
-#define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_SHIFT 0 /**< Shift value for PAVDD1V86THRESFINE */
-#define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for PAVDD1V86THRESFINE */
-#define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for PAVDD1V86THRESCOARSE */
-#define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for PAVDD1V86THRESCOARSE */
-#define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_SHIFT 8 /**< Shift value for PAVDD2V98THRESFINE */
-#define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for PAVDD2V98THRESFINE */
-#define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for PAVDD2V98THRESCOARSE */
-#define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for PAVDD2V98THRESCOARSE */
-#define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_SHIFT 16 /**< Shift value for FVDD1V86THRESFINE */
-#define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_MASK 0xF0000UL /**< Bit mask for FVDD1V86THRESFINE */
-#define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_SHIFT 20 /**< Shift value for FVDD1V86THRESCOARSE */
-#define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for FVDD1V86THRESCOARSE */
-#define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_SHIFT 24 /**< Shift value for FVDD2V98THRESFINE */
-#define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_MASK 0xF000000UL /**< Bit mask for FVDD2V98THRESFINE */
-#define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_SHIFT 28 /**< Shift value for FVDD2V98THRESCOARSE */
-#define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for FVDD2V98THRESCOARSE */
-
-/* Bit fields for DEVINFO IDAC0CAL0 */
-#define _DEVINFO_IDAC0CAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL0 */
-#define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT 0 /**< Shift value for SOURCERANGE0TUNING */
-#define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK 0xFFUL /**< Bit mask for SOURCERANGE0TUNING */
-#define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_SHIFT 8 /**< Shift value for SOURCERANGE1TUNING */
-#define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SOURCERANGE1TUNING */
-#define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_SHIFT 16 /**< Shift value for SOURCERANGE2TUNING */
-#define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SOURCERANGE2TUNING */
-#define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_SHIFT 24 /**< Shift value for SOURCERANGE3TUNING */
-#define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SOURCERANGE3TUNING */
-
-/* Bit fields for DEVINFO IDAC0CAL1 */
-#define _DEVINFO_IDAC0CAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL1 */
-#define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT 0 /**< Shift value for SINKRANGE0TUNING */
-#define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK 0xFFUL /**< Bit mask for SINKRANGE0TUNING */
-#define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_SHIFT 8 /**< Shift value for SINKRANGE1TUNING */
-#define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SINKRANGE1TUNING */
-#define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_SHIFT 16 /**< Shift value for SINKRANGE2TUNING */
-#define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SINKRANGE2TUNING */
-#define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_SHIFT 24 /**< Shift value for SINKRANGE3TUNING */
-#define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SINKRANGE3TUNING */
-
-/* Bit fields for DEVINFO DCDCLNVCTRL0 */
-#define _DEVINFO_DCDCLNVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLNVCTRL0 */
-#define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT 0 /**< Shift value for 1V2LNATT0 */
-#define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK 0xFFUL /**< Bit mask for 1V2LNATT0 */
-#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT 8 /**< Shift value for 1V8LNATT0 */
-#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK 0xFF00UL /**< Bit mask for 1V8LNATT0 */
-#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT 16 /**< Shift value for 1V8LNATT1 */
-#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK 0xFF0000UL /**< Bit mask for 1V8LNATT1 */
-#define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT 24 /**< Shift value for 3V0LNATT1 */
-#define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK 0xFF000000UL /**< Bit mask for 3V0LNATT1 */
-
-/* Bit fields for DEVINFO DCDCLPVCTRL0 */
-#define _DEVINFO_DCDCLPVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL0 */
-#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS0 */
-#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS0 */
-#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS0 */
-#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS0 */
-#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS1 */
-#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS1 */
-#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS1 */
-#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS1 */
-
-/* Bit fields for DEVINFO DCDCLPVCTRL1 */
-#define _DEVINFO_DCDCLPVCTRL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL1 */
-#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS2 */
-#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS2 */
-#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS2 */
-#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS2 */
-#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS3 */
-#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS3 */
-#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS3 */
-#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS3 */
-
-/* Bit fields for DEVINFO DCDCLPVCTRL2 */
-#define _DEVINFO_DCDCLPVCTRL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL2 */
-#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS0 */
-#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS0 */
-#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS0 */
-#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS0 */
-#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS1 */
-#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS1 */
-#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS1 */
-#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS1 */
-
-/* Bit fields for DEVINFO DCDCLPVCTRL3 */
-#define _DEVINFO_DCDCLPVCTRL3_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL3 */
-#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS2 */
-#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS2 */
-#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS2 */
-#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS2 */
-#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS3 */
-#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS3 */
-#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS3 */
-#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS3 */
-
-/* Bit fields for DEVINFO DCDCLPCMPHYSSEL0 */
-#define _DEVINFO_DCDCLPCMPHYSSEL0_MASK 0x0000FFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL0 */
-#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPATT0 */
-#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPATT0 */
-#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPATT1 */
-#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPATT1 */
-
-/* Bit fields for DEVINFO DCDCLPCMPHYSSEL1 */
-#define _DEVINFO_DCDCLPCMPHYSSEL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL1 */
-#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPCMPBIAS0 */
-#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPCMPBIAS0 */
-#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPCMPBIAS1 */
-#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS1 */
-#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT 16 /**< Shift value for LPCMPHYSSELLPCMPBIAS2 */
-#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK 0xFF0000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS2 */
-#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT 24 /**< Shift value for LPCMPHYSSELLPCMPBIAS3 */
-#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS3 */
-
-/* Bit fields for DEVINFO VDAC0MAINCAL */
-#define _DEVINFO_VDAC0MAINCAL_MASK 0x3FFFFFFFUL /**< Mask for DEVINFO_VDAC0MAINCAL */
-#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_SHIFT 0 /**< Shift value for GAINERRTRIM1V25LN */
-#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_MASK 0x3FUL /**< Bit mask for GAINERRTRIM1V25LN */
-#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_SHIFT 6 /**< Shift value for GAINERRTRIM2V5LN */
-#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_MASK 0xFC0UL /**< Bit mask for GAINERRTRIM2V5LN */
-#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_SHIFT 12 /**< Shift value for GAINERRTRIM1V25 */
-#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_MASK 0x3F000UL /**< Bit mask for GAINERRTRIM1V25 */
-#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_SHIFT 18 /**< Shift value for GAINERRTRIM2V5 */
-#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_MASK 0xFC0000UL /**< Bit mask for GAINERRTRIM2V5 */
-#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_SHIFT 24 /**< Shift value for GAINERRTRIMVDDANAEXTPIN */
-#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_MASK 0x3F000000UL /**< Bit mask for GAINERRTRIMVDDANAEXTPIN */
-
-/* Bit fields for DEVINFO VDAC0ALTCAL */
-#define _DEVINFO_VDAC0ALTCAL_MASK 0x3FFFFFFFUL /**< Mask for DEVINFO_VDAC0ALTCAL */
-#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25LNALT_SHIFT 0 /**< Shift value for GAINERRTRIM1V25LNALT */
-#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25LNALT_MASK 0x3FUL /**< Bit mask for GAINERRTRIM1V25LNALT */
-#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5LNALT_SHIFT 6 /**< Shift value for GAINERRTRIM2V5LNALT */
-#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5LNALT_MASK 0xFC0UL /**< Bit mask for GAINERRTRIM2V5LNALT */
-#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25ALT_SHIFT 12 /**< Shift value for GAINERRTRIM1V25ALT */
-#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25ALT_MASK 0x3F000UL /**< Bit mask for GAINERRTRIM1V25ALT */
-#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5ALT_SHIFT 18 /**< Shift value for GAINERRTRIM2V5ALT */
-#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5ALT_MASK 0xFC0000UL /**< Bit mask for GAINERRTRIM2V5ALT */
-#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIMVDDANAEXTPINALT_SHIFT 24 /**< Shift value for GAINERRTRIMVDDANAEXTPINALT */
-#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIMVDDANAEXTPINALT_MASK 0x3F000000UL /**< Bit mask for GAINERRTRIMVDDANAEXTPINALT */
-
-/* Bit fields for DEVINFO VDAC0CH1CAL */
-#define _DEVINFO_VDAC0CH1CAL_MASK 0x00000FF7UL /**< Mask for DEVINFO_VDAC0CH1CAL */
-#define _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_SHIFT 0 /**< Shift value for OFFSETTRIM */
-#define _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_MASK 0x7UL /**< Bit mask for OFFSETTRIM */
-#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_SHIFT 4 /**< Shift value for GAINERRTRIMCH1A */
-#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_MASK 0xF0UL /**< Bit mask for GAINERRTRIMCH1A */
-#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_SHIFT 8 /**< Shift value for GAINERRTRIMCH1B */
-#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_MASK 0xF00UL /**< Bit mask for GAINERRTRIMCH1B */
-
-/* Bit fields for DEVINFO OPA0CAL0 */
-#define _DEVINFO_OPA0CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL0 */
-#define _DEVINFO_OPA0CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */
-#define _DEVINFO_OPA0CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */
-#define _DEVINFO_OPA0CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */
-#define _DEVINFO_OPA0CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
-#define _DEVINFO_OPA0CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */
-#define _DEVINFO_OPA0CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
-#define _DEVINFO_OPA0CAL0_GM_SHIFT 13 /**< Shift value for GM */
-#define _DEVINFO_OPA0CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */
-#define _DEVINFO_OPA0CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */
-#define _DEVINFO_OPA0CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
-#define _DEVINFO_OPA0CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
-#define _DEVINFO_OPA0CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
-#define _DEVINFO_OPA0CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
-#define _DEVINFO_OPA0CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
-
-/* Bit fields for DEVINFO OPA0CAL1 */
-#define _DEVINFO_OPA0CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL1 */
-#define _DEVINFO_OPA0CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */
-#define _DEVINFO_OPA0CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */
-#define _DEVINFO_OPA0CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */
-#define _DEVINFO_OPA0CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
-#define _DEVINFO_OPA0CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */
-#define _DEVINFO_OPA0CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
-#define _DEVINFO_OPA0CAL1_GM_SHIFT 13 /**< Shift value for GM */
-#define _DEVINFO_OPA0CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */
-#define _DEVINFO_OPA0CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */
-#define _DEVINFO_OPA0CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
-#define _DEVINFO_OPA0CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
-#define _DEVINFO_OPA0CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
-#define _DEVINFO_OPA0CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
-#define _DEVINFO_OPA0CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
-
-/* Bit fields for DEVINFO OPA0CAL2 */
-#define _DEVINFO_OPA0CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL2 */
-#define _DEVINFO_OPA0CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */
-#define _DEVINFO_OPA0CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */
-#define _DEVINFO_OPA0CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */
-#define _DEVINFO_OPA0CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
-#define _DEVINFO_OPA0CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */
-#define _DEVINFO_OPA0CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
-#define _DEVINFO_OPA0CAL2_GM_SHIFT 13 /**< Shift value for GM */
-#define _DEVINFO_OPA0CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */
-#define _DEVINFO_OPA0CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */
-#define _DEVINFO_OPA0CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
-#define _DEVINFO_OPA0CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
-#define _DEVINFO_OPA0CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
-#define _DEVINFO_OPA0CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
-#define _DEVINFO_OPA0CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
-
-/* Bit fields for DEVINFO OPA0CAL3 */
-#define _DEVINFO_OPA0CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL3 */
-#define _DEVINFO_OPA0CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */
-#define _DEVINFO_OPA0CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */
-#define _DEVINFO_OPA0CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */
-#define _DEVINFO_OPA0CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
-#define _DEVINFO_OPA0CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */
-#define _DEVINFO_OPA0CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
-#define _DEVINFO_OPA0CAL3_GM_SHIFT 13 /**< Shift value for GM */
-#define _DEVINFO_OPA0CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */
-#define _DEVINFO_OPA0CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */
-#define _DEVINFO_OPA0CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
-#define _DEVINFO_OPA0CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
-#define _DEVINFO_OPA0CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
-#define _DEVINFO_OPA0CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
-#define _DEVINFO_OPA0CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
-
-/* Bit fields for DEVINFO OPA1CAL0 */
-#define _DEVINFO_OPA1CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL0 */
-#define _DEVINFO_OPA1CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */
-#define _DEVINFO_OPA1CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */
-#define _DEVINFO_OPA1CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */
-#define _DEVINFO_OPA1CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
-#define _DEVINFO_OPA1CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */
-#define _DEVINFO_OPA1CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
-#define _DEVINFO_OPA1CAL0_GM_SHIFT 13 /**< Shift value for GM */
-#define _DEVINFO_OPA1CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */
-#define _DEVINFO_OPA1CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */
-#define _DEVINFO_OPA1CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
-#define _DEVINFO_OPA1CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
-#define _DEVINFO_OPA1CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
-#define _DEVINFO_OPA1CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
-#define _DEVINFO_OPA1CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
-
-/* Bit fields for DEVINFO OPA1CAL1 */
-#define _DEVINFO_OPA1CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL1 */
-#define _DEVINFO_OPA1CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */
-#define _DEVINFO_OPA1CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */
-#define _DEVINFO_OPA1CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */
-#define _DEVINFO_OPA1CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
-#define _DEVINFO_OPA1CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */
-#define _DEVINFO_OPA1CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
-#define _DEVINFO_OPA1CAL1_GM_SHIFT 13 /**< Shift value for GM */
-#define _DEVINFO_OPA1CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */
-#define _DEVINFO_OPA1CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */
-#define _DEVINFO_OPA1CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
-#define _DEVINFO_OPA1CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
-#define _DEVINFO_OPA1CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
-#define _DEVINFO_OPA1CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
-#define _DEVINFO_OPA1CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
-
-/* Bit fields for DEVINFO OPA1CAL2 */
-#define _DEVINFO_OPA1CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL2 */
-#define _DEVINFO_OPA1CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */
-#define _DEVINFO_OPA1CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */
-#define _DEVINFO_OPA1CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */
-#define _DEVINFO_OPA1CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
-#define _DEVINFO_OPA1CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */
-#define _DEVINFO_OPA1CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
-#define _DEVINFO_OPA1CAL2_GM_SHIFT 13 /**< Shift value for GM */
-#define _DEVINFO_OPA1CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */
-#define _DEVINFO_OPA1CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */
-#define _DEVINFO_OPA1CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
-#define _DEVINFO_OPA1CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
-#define _DEVINFO_OPA1CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
-#define _DEVINFO_OPA1CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
-#define _DEVINFO_OPA1CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
-
-/* Bit fields for DEVINFO OPA1CAL3 */
-#define _DEVINFO_OPA1CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL3 */
-#define _DEVINFO_OPA1CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */
-#define _DEVINFO_OPA1CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */
-#define _DEVINFO_OPA1CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */
-#define _DEVINFO_OPA1CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
-#define _DEVINFO_OPA1CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */
-#define _DEVINFO_OPA1CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
-#define _DEVINFO_OPA1CAL3_GM_SHIFT 13 /**< Shift value for GM */
-#define _DEVINFO_OPA1CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */
-#define _DEVINFO_OPA1CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */
-#define _DEVINFO_OPA1CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
-#define _DEVINFO_OPA1CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
-#define _DEVINFO_OPA1CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
-#define _DEVINFO_OPA1CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
-#define _DEVINFO_OPA1CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
-
-/* Bit fields for DEVINFO OPA2CAL0 */
-#define _DEVINFO_OPA2CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL0 */
-#define _DEVINFO_OPA2CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */
-#define _DEVINFO_OPA2CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */
-#define _DEVINFO_OPA2CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */
-#define _DEVINFO_OPA2CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
-#define _DEVINFO_OPA2CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */
-#define _DEVINFO_OPA2CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
-#define _DEVINFO_OPA2CAL0_GM_SHIFT 13 /**< Shift value for GM */
-#define _DEVINFO_OPA2CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */
-#define _DEVINFO_OPA2CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */
-#define _DEVINFO_OPA2CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
-#define _DEVINFO_OPA2CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
-#define _DEVINFO_OPA2CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
-#define _DEVINFO_OPA2CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
-#define _DEVINFO_OPA2CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
-
-/* Bit fields for DEVINFO OPA2CAL1 */
-#define _DEVINFO_OPA2CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL1 */
-#define _DEVINFO_OPA2CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */
-#define _DEVINFO_OPA2CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */
-#define _DEVINFO_OPA2CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */
-#define _DEVINFO_OPA2CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
-#define _DEVINFO_OPA2CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */
-#define _DEVINFO_OPA2CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
-#define _DEVINFO_OPA2CAL1_GM_SHIFT 13 /**< Shift value for GM */
-#define _DEVINFO_OPA2CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */
-#define _DEVINFO_OPA2CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */
-#define _DEVINFO_OPA2CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
-#define _DEVINFO_OPA2CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
-#define _DEVINFO_OPA2CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
-#define _DEVINFO_OPA2CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
-#define _DEVINFO_OPA2CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
-
-/* Bit fields for DEVINFO OPA2CAL2 */
-#define _DEVINFO_OPA2CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL2 */
-#define _DEVINFO_OPA2CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */
-#define _DEVINFO_OPA2CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */
-#define _DEVINFO_OPA2CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */
-#define _DEVINFO_OPA2CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
-#define _DEVINFO_OPA2CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */
-#define _DEVINFO_OPA2CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
-#define _DEVINFO_OPA2CAL2_GM_SHIFT 13 /**< Shift value for GM */
-#define _DEVINFO_OPA2CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */
-#define _DEVINFO_OPA2CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */
-#define _DEVINFO_OPA2CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
-#define _DEVINFO_OPA2CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
-#define _DEVINFO_OPA2CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
-#define _DEVINFO_OPA2CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
-#define _DEVINFO_OPA2CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
-
-/* Bit fields for DEVINFO OPA2CAL3 */
-#define _DEVINFO_OPA2CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL3 */
-#define _DEVINFO_OPA2CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */
-#define _DEVINFO_OPA2CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */
-#define _DEVINFO_OPA2CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */
-#define _DEVINFO_OPA2CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
-#define _DEVINFO_OPA2CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */
-#define _DEVINFO_OPA2CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
-#define _DEVINFO_OPA2CAL3_GM_SHIFT 13 /**< Shift value for GM */
-#define _DEVINFO_OPA2CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */
-#define _DEVINFO_OPA2CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */
-#define _DEVINFO_OPA2CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
-#define _DEVINFO_OPA2CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
-#define _DEVINFO_OPA2CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
-#define _DEVINFO_OPA2CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
-#define _DEVINFO_OPA2CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
-
-/* Bit fields for DEVINFO CSENGAINCAL */
-#define _DEVINFO_CSENGAINCAL_MASK 0x000000FFUL /**< Mask for DEVINFO_CSENGAINCAL */
-#define _DEVINFO_CSENGAINCAL_GAINCAL_SHIFT 0 /**< Shift value for GAINCAL */
-#define _DEVINFO_CSENGAINCAL_GAINCAL_MASK 0xFFUL /**< Bit mask for GAINCAL */
-
-/* Bit fields for DEVINFO OPA0CAL4 */
-#define _DEVINFO_OPA0CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL4 */
-#define _DEVINFO_OPA0CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */
-#define _DEVINFO_OPA0CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */
-#define _DEVINFO_OPA0CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */
-#define _DEVINFO_OPA0CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
-#define _DEVINFO_OPA0CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */
-#define _DEVINFO_OPA0CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
-#define _DEVINFO_OPA0CAL4_GM_SHIFT 13 /**< Shift value for GM */
-#define _DEVINFO_OPA0CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */
-#define _DEVINFO_OPA0CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */
-#define _DEVINFO_OPA0CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
-#define _DEVINFO_OPA0CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
-#define _DEVINFO_OPA0CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
-#define _DEVINFO_OPA0CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
-#define _DEVINFO_OPA0CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
-
-/* Bit fields for DEVINFO OPA0CAL5 */
-#define _DEVINFO_OPA0CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL5 */
-#define _DEVINFO_OPA0CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */
-#define _DEVINFO_OPA0CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */
-#define _DEVINFO_OPA0CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */
-#define _DEVINFO_OPA0CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
-#define _DEVINFO_OPA0CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */
-#define _DEVINFO_OPA0CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
-#define _DEVINFO_OPA0CAL5_GM_SHIFT 13 /**< Shift value for GM */
-#define _DEVINFO_OPA0CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */
-#define _DEVINFO_OPA0CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */
-#define _DEVINFO_OPA0CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
-#define _DEVINFO_OPA0CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
-#define _DEVINFO_OPA0CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
-#define _DEVINFO_OPA0CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
-#define _DEVINFO_OPA0CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
-
-/* Bit fields for DEVINFO OPA0CAL6 */
-#define _DEVINFO_OPA0CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL6 */
-#define _DEVINFO_OPA0CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */
-#define _DEVINFO_OPA0CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */
-#define _DEVINFO_OPA0CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */
-#define _DEVINFO_OPA0CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
-#define _DEVINFO_OPA0CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */
-#define _DEVINFO_OPA0CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
-#define _DEVINFO_OPA0CAL6_GM_SHIFT 13 /**< Shift value for GM */
-#define _DEVINFO_OPA0CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */
-#define _DEVINFO_OPA0CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */
-#define _DEVINFO_OPA0CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
-#define _DEVINFO_OPA0CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
-#define _DEVINFO_OPA0CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
-#define _DEVINFO_OPA0CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
-#define _DEVINFO_OPA0CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
-
-/* Bit fields for DEVINFO OPA0CAL7 */
-#define _DEVINFO_OPA0CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL7 */
-#define _DEVINFO_OPA0CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */
-#define _DEVINFO_OPA0CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */
-#define _DEVINFO_OPA0CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */
-#define _DEVINFO_OPA0CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
-#define _DEVINFO_OPA0CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */
-#define _DEVINFO_OPA0CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
-#define _DEVINFO_OPA0CAL7_GM_SHIFT 13 /**< Shift value for GM */
-#define _DEVINFO_OPA0CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */
-#define _DEVINFO_OPA0CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */
-#define _DEVINFO_OPA0CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
-#define _DEVINFO_OPA0CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
-#define _DEVINFO_OPA0CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
-#define _DEVINFO_OPA0CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
-#define _DEVINFO_OPA0CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
-
-/* Bit fields for DEVINFO OPA1CAL4 */
-#define _DEVINFO_OPA1CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL4 */
-#define _DEVINFO_OPA1CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */
-#define _DEVINFO_OPA1CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */
-#define _DEVINFO_OPA1CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */
-#define _DEVINFO_OPA1CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
-#define _DEVINFO_OPA1CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */
-#define _DEVINFO_OPA1CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
-#define _DEVINFO_OPA1CAL4_GM_SHIFT 13 /**< Shift value for GM */
-#define _DEVINFO_OPA1CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */
-#define _DEVINFO_OPA1CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */
-#define _DEVINFO_OPA1CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
-#define _DEVINFO_OPA1CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
-#define _DEVINFO_OPA1CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
-#define _DEVINFO_OPA1CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
-#define _DEVINFO_OPA1CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
-
-/* Bit fields for DEVINFO OPA1CAL5 */
-#define _DEVINFO_OPA1CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL5 */
-#define _DEVINFO_OPA1CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */
-#define _DEVINFO_OPA1CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */
-#define _DEVINFO_OPA1CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */
-#define _DEVINFO_OPA1CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
-#define _DEVINFO_OPA1CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */
-#define _DEVINFO_OPA1CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
-#define _DEVINFO_OPA1CAL5_GM_SHIFT 13 /**< Shift value for GM */
-#define _DEVINFO_OPA1CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */
-#define _DEVINFO_OPA1CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */
-#define _DEVINFO_OPA1CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
-#define _DEVINFO_OPA1CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
-#define _DEVINFO_OPA1CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
-#define _DEVINFO_OPA1CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
-#define _DEVINFO_OPA1CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
-
-/* Bit fields for DEVINFO OPA1CAL6 */
-#define _DEVINFO_OPA1CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL6 */
-#define _DEVINFO_OPA1CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */
-#define _DEVINFO_OPA1CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */
-#define _DEVINFO_OPA1CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */
-#define _DEVINFO_OPA1CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
-#define _DEVINFO_OPA1CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */
-#define _DEVINFO_OPA1CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
-#define _DEVINFO_OPA1CAL6_GM_SHIFT 13 /**< Shift value for GM */
-#define _DEVINFO_OPA1CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */
-#define _DEVINFO_OPA1CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */
-#define _DEVINFO_OPA1CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
-#define _DEVINFO_OPA1CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
-#define _DEVINFO_OPA1CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
-#define _DEVINFO_OPA1CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
-#define _DEVINFO_OPA1CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
-
-/* Bit fields for DEVINFO OPA1CAL7 */
-#define _DEVINFO_OPA1CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL7 */
-#define _DEVINFO_OPA1CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */
-#define _DEVINFO_OPA1CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */
-#define _DEVINFO_OPA1CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */
-#define _DEVINFO_OPA1CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
-#define _DEVINFO_OPA1CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */
-#define _DEVINFO_OPA1CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
-#define _DEVINFO_OPA1CAL7_GM_SHIFT 13 /**< Shift value for GM */
-#define _DEVINFO_OPA1CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */
-#define _DEVINFO_OPA1CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */
-#define _DEVINFO_OPA1CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
-#define _DEVINFO_OPA1CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
-#define _DEVINFO_OPA1CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
-#define _DEVINFO_OPA1CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
-#define _DEVINFO_OPA1CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
-
-/* Bit fields for DEVINFO OPA2CAL4 */
-#define _DEVINFO_OPA2CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL4 */
-#define _DEVINFO_OPA2CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */
-#define _DEVINFO_OPA2CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */
-#define _DEVINFO_OPA2CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */
-#define _DEVINFO_OPA2CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
-#define _DEVINFO_OPA2CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */
-#define _DEVINFO_OPA2CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
-#define _DEVINFO_OPA2CAL4_GM_SHIFT 13 /**< Shift value for GM */
-#define _DEVINFO_OPA2CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */
-#define _DEVINFO_OPA2CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */
-#define _DEVINFO_OPA2CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
-#define _DEVINFO_OPA2CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
-#define _DEVINFO_OPA2CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
-#define _DEVINFO_OPA2CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
-#define _DEVINFO_OPA2CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
-
-/* Bit fields for DEVINFO OPA2CAL5 */
-#define _DEVINFO_OPA2CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL5 */
-#define _DEVINFO_OPA2CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */
-#define _DEVINFO_OPA2CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */
-#define _DEVINFO_OPA2CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */
-#define _DEVINFO_OPA2CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
-#define _DEVINFO_OPA2CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */
-#define _DEVINFO_OPA2CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
-#define _DEVINFO_OPA2CAL5_GM_SHIFT 13 /**< Shift value for GM */
-#define _DEVINFO_OPA2CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */
-#define _DEVINFO_OPA2CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */
-#define _DEVINFO_OPA2CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
-#define _DEVINFO_OPA2CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
-#define _DEVINFO_OPA2CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
-#define _DEVINFO_OPA2CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
-#define _DEVINFO_OPA2CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
-
-/* Bit fields for DEVINFO OPA2CAL6 */
-#define _DEVINFO_OPA2CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL6 */
-#define _DEVINFO_OPA2CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */
-#define _DEVINFO_OPA2CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */
-#define _DEVINFO_OPA2CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */
-#define _DEVINFO_OPA2CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
-#define _DEVINFO_OPA2CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */
-#define _DEVINFO_OPA2CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
-#define _DEVINFO_OPA2CAL6_GM_SHIFT 13 /**< Shift value for GM */
-#define _DEVINFO_OPA2CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */
-#define _DEVINFO_OPA2CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */
-#define _DEVINFO_OPA2CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
-#define _DEVINFO_OPA2CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
-#define _DEVINFO_OPA2CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
-#define _DEVINFO_OPA2CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
-#define _DEVINFO_OPA2CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
-
-/* Bit fields for DEVINFO OPA2CAL7 */
-#define _DEVINFO_OPA2CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL7 */
-#define _DEVINFO_OPA2CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */
-#define _DEVINFO_OPA2CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */
-#define _DEVINFO_OPA2CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */
-#define _DEVINFO_OPA2CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
-#define _DEVINFO_OPA2CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */
-#define _DEVINFO_OPA2CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
-#define _DEVINFO_OPA2CAL7_GM_SHIFT 13 /**< Shift value for GM */
-#define _DEVINFO_OPA2CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */
-#define _DEVINFO_OPA2CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */
-#define _DEVINFO_OPA2CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
-#define _DEVINFO_OPA2CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
-#define _DEVINFO_OPA2CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
-#define _DEVINFO_OPA2CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
-#define _DEVINFO_OPA2CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
-
-/** @} */
-/** @} End of group EFR32FG13P_DEVINFO */
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_dmareq.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_dmareq.h
deleted file mode 100644
index 1897a000..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_dmareq.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_dmareq.h
- * @brief EFR32FG13P_DMAREQ register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_DMAREQ DMAREQ
- * @{
- * @defgroup EFR32FG13P_DMAREQ_BitFields DMAREQ Bit Fields
- * @{
- *****************************************************************************/
-#define DMAREQ_PRS_REQ0 ((1 << 16) + 0) /**< DMA channel select for PRS_REQ0 */
-#define DMAREQ_PRS_REQ1 ((1 << 16) + 1) /**< DMA channel select for PRS_REQ1 */
-#define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /**< DMA channel select for ADC0_SINGLE */
-#define DMAREQ_ADC0_SCAN ((8 << 16) + 1) /**< DMA channel select for ADC0_SCAN */
-#define DMAREQ_VDAC0_CH0 ((10 << 16) + 0) /**< DMA channel select for VDAC0_CH0 */
-#define DMAREQ_VDAC0_CH1 ((10 << 16) + 1) /**< DMA channel select for VDAC0_CH1 */
-#define DMAREQ_USART0_RXDATAV ((12 << 16) + 0) /**< DMA channel select for USART0_RXDATAV */
-#define DMAREQ_USART0_TXBL ((12 << 16) + 1) /**< DMA channel select for USART0_TXBL */
-#define DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) /**< DMA channel select for USART0_TXEMPTY */
-#define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) /**< DMA channel select for USART1_RXDATAV */
-#define DMAREQ_USART1_TXBL ((13 << 16) + 1) /**< DMA channel select for USART1_TXBL */
-#define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) /**< DMA channel select for USART1_TXEMPTY */
-#define DMAREQ_USART1_RXDATAVRIGHT ((13 << 16) + 3) /**< DMA channel select for USART1_RXDATAVRIGHT */
-#define DMAREQ_USART1_TXBLRIGHT ((13 << 16) + 4) /**< DMA channel select for USART1_TXBLRIGHT */
-#define DMAREQ_USART2_RXDATAV ((14 << 16) + 0) /**< DMA channel select for USART2_RXDATAV */
-#define DMAREQ_USART2_TXBL ((14 << 16) + 1) /**< DMA channel select for USART2_TXBL */
-#define DMAREQ_USART2_TXEMPTY ((14 << 16) + 2) /**< DMA channel select for USART2_TXEMPTY */
-#define DMAREQ_LEUART0_RXDATAV ((16 << 16) + 0) /**< DMA channel select for LEUART0_RXDATAV */
-#define DMAREQ_LEUART0_TXBL ((16 << 16) + 1) /**< DMA channel select for LEUART0_TXBL */
-#define DMAREQ_LEUART0_TXEMPTY ((16 << 16) + 2) /**< DMA channel select for LEUART0_TXEMPTY */
-#define DMAREQ_I2C0_RXDATAV ((20 << 16) + 0) /**< DMA channel select for I2C0_RXDATAV */
-#define DMAREQ_I2C0_TXBL ((20 << 16) + 1) /**< DMA channel select for I2C0_TXBL */
-#define DMAREQ_I2C1_RXDATAV ((21 << 16) + 0) /**< DMA channel select for I2C1_RXDATAV */
-#define DMAREQ_I2C1_TXBL ((21 << 16) + 1) /**< DMA channel select for I2C1_TXBL */
-#define DMAREQ_TIMER0_UFOF ((24 << 16) + 0) /**< DMA channel select for TIMER0_UFOF */
-#define DMAREQ_TIMER0_CC0 ((24 << 16) + 1) /**< DMA channel select for TIMER0_CC0 */
-#define DMAREQ_TIMER0_CC1 ((24 << 16) + 2) /**< DMA channel select for TIMER0_CC1 */
-#define DMAREQ_TIMER0_CC2 ((24 << 16) + 3) /**< DMA channel select for TIMER0_CC2 */
-#define DMAREQ_TIMER1_UFOF ((25 << 16) + 0) /**< DMA channel select for TIMER1_UFOF */
-#define DMAREQ_TIMER1_CC0 ((25 << 16) + 1) /**< DMA channel select for TIMER1_CC0 */
-#define DMAREQ_TIMER1_CC1 ((25 << 16) + 2) /**< DMA channel select for TIMER1_CC1 */
-#define DMAREQ_TIMER1_CC2 ((25 << 16) + 3) /**< DMA channel select for TIMER1_CC2 */
-#define DMAREQ_TIMER1_CC3 ((25 << 16) + 4) /**< DMA channel select for TIMER1_CC3 */
-#define DMAREQ_WTIMER0_UFOF ((26 << 16) + 0) /**< DMA channel select for WTIMER0_UFOF */
-#define DMAREQ_WTIMER0_CC0 ((26 << 16) + 1) /**< DMA channel select for WTIMER0_CC0 */
-#define DMAREQ_WTIMER0_CC1 ((26 << 16) + 2) /**< DMA channel select for WTIMER0_CC1 */
-#define DMAREQ_WTIMER0_CC2 ((26 << 16) + 3) /**< DMA channel select for WTIMER0_CC2 */
-#define DMAREQ_MSC_WDATA ((48 << 16) + 0) /**< DMA channel select for MSC_WDATA */
-#define DMAREQ_CRYPTO0_DATA0WR ((49 << 16) + 0) /**< DMA channel select for CRYPTO0_DATA0WR */
-#define DMAREQ_CRYPTO_DATA0WR DMAREQ_CRYPTO0_DATA0WR /**< Alias for DMAREQ_CRYPTO0_DATA0WR */
-#define DMAREQ_CRYPTO0_DATA0XWR ((49 << 16) + 1) /**< DMA channel select for CRYPTO0_DATA0XWR */
-#define DMAREQ_CRYPTO_DATA0XWR DMAREQ_CRYPTO0_DATA0XWR /**< Alias for DMAREQ_CRYPTO0_DATA0XWR */
-#define DMAREQ_CRYPTO0_DATA0RD ((49 << 16) + 2) /**< DMA channel select for CRYPTO0_DATA0RD */
-#define DMAREQ_CRYPTO_DATA0RD DMAREQ_CRYPTO0_DATA0RD /**< Alias for DMAREQ_CRYPTO0_DATA0RD */
-#define DMAREQ_CRYPTO0_DATA1WR ((49 << 16) + 3) /**< DMA channel select for CRYPTO0_DATA1WR */
-#define DMAREQ_CRYPTO_DATA1WR DMAREQ_CRYPTO0_DATA1WR /**< Alias for DMAREQ_CRYPTO0_DATA1WR */
-#define DMAREQ_CRYPTO0_DATA1RD ((49 << 16) + 4) /**< DMA channel select for CRYPTO0_DATA1RD */
-#define DMAREQ_CRYPTO_DATA1RD DMAREQ_CRYPTO0_DATA1RD /**< Alias for DMAREQ_CRYPTO0_DATA1RD */
-#define DMAREQ_CSEN_DATA ((50 << 16) + 0) /**< DMA channel select for CSEN_DATA */
-#define DMAREQ_CSEN_BSLN ((50 << 16) + 1) /**< DMA channel select for CSEN_BSLN */
-#define DMAREQ_LESENSE_BUFDATAV ((51 << 16) + 0) /**< DMA channel select for LESENSE_BUFDATAV */
-#define DMAREQ_CRYPTO1_DATA0WR ((52 << 16) + 0) /**< DMA channel select for CRYPTO1_DATA0WR */
-#define DMAREQ_CRYPTO1_DATA0XWR ((52 << 16) + 1) /**< DMA channel select for CRYPTO1_DATA0XWR */
-#define DMAREQ_CRYPTO1_DATA0RD ((52 << 16) + 2) /**< DMA channel select for CRYPTO1_DATA0RD */
-#define DMAREQ_CRYPTO1_DATA1WR ((52 << 16) + 3) /**< DMA channel select for CRYPTO1_DATA1WR */
-#define DMAREQ_CRYPTO1_DATA1RD ((52 << 16) + 4) /**< DMA channel select for CRYPTO1_DATA1RD */
-
-/** @} */
-/** @} End of group EFR32FG13P_DMAREQ */
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_emu.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_emu.h
deleted file mode 100644
index bf463c5f..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_emu.h
+++ /dev/null
@@ -1,1399 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_emu.h
- * @brief EFR32FG13P_EMU register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P_EMU EMU
- * @{
- * @brief EFR32FG13P_EMU Register Declaration
- *****************************************************************************/
-/** EMU Register Declaration */
-typedef struct {
- __IOM uint32_t CTRL; /**< Control Register */
- __IM uint32_t STATUS; /**< Status Register */
- __IOM uint32_t LOCK; /**< Configuration Lock Register */
- __IOM uint32_t RAM0CTRL; /**< Memory Control Register */
- __IOM uint32_t CMD; /**< Command Register */
-
- uint32_t RESERVED0[1]; /**< Reserved for future use **/
- __IOM uint32_t EM4CTRL; /**< EM4 Control Register */
- __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */
- __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */
-
- uint32_t RESERVED1[1]; /**< Reserved for future use **/
- __IOM uint32_t PWRCTRL; /**< Power Control Register */
- __IOM uint32_t DCDCCTRL; /**< DCDC Control */
-
- uint32_t RESERVED2[2]; /**< Reserved for future use **/
- __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */
- __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */
- __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */
- __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */
- __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */
-
- uint32_t RESERVED3[1]; /**< Reserved for future use **/
- __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */
-
- uint32_t RESERVED4[1]; /**< Reserved for future use **/
- __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */
- __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */
-
- uint32_t RESERVED5[1]; /**< Reserved for future use **/
- __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */
-
- uint32_t RESERVED6[5]; /**< Reserved for future use **/
- __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */
- __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */
- __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */
- __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */
-
- uint32_t RESERVED7[4]; /**< Reserved for future use **/
- __IOM uint32_t RAM1CTRL; /**< Memory Control Register */
- __IOM uint32_t RAM2CTRL; /**< Memory Control Register */
-
- uint32_t RESERVED8[10]; /**< Reserved for future use **/
- __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */
-
- uint32_t RESERVED9[4]; /**< Reserved for future use **/
- __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */
- __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */
- __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */
-} EMU_TypeDef; /** @} */
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_EMU
- * @{
- * @defgroup EFR32FG13P_EMU_BitFields EMU Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for EMU CTRL */
-#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
-#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */
-#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */
-#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */
-#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */
-#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
-#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */
-#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */
-#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */
-#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */
-#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
-#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */
-#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */
-#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */
-#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */
-#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
-#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */
-#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash, Ram and Frequency to Wakeup From EM2 or EM3 at Low Voltage */
-#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */
-#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */
-#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
-#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */
-#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */
-#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */
-#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
-#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */
-#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */
-#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */
-#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */
-#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */
-#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */
-#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */
-#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */
-#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */
-#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
-#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */
-#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */
-#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */
-#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */
-#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */
-#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */
-#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */
-
-/* Bit fields for EMU STATUS */
-#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */
-#define _EMU_STATUS_MASK 0x0417011FUL /**< Mask for EMU_STATUS */
-#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */
-#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */
-#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */
-#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
-#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */
-#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */
-#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */
-#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */
-#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
-#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */
-#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */
-#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */
-#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */
-#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
-#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */
-#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */
-#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */
-#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */
-#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
-#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */
-#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */
-#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */
-#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */
-#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
-#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */
-#define EMU_STATUS_VMONFVDD (0x1UL << 8) /**< VMON VDDFLASH Channel */
-#define _EMU_STATUS_VMONFVDD_SHIFT 8 /**< Shift value for EMU_VMONFVDD */
-#define _EMU_STATUS_VMONFVDD_MASK 0x100UL /**< Bit mask for EMU_VMONFVDD */
-#define _EMU_STATUS_VMONFVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
-#define EMU_STATUS_VMONFVDD_DEFAULT (_EMU_STATUS_VMONFVDD_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_STATUS */
-#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */
-#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */
-#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
-#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */
-#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */
-#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */
-#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */
-#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */
-#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */
-#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */
-#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */
-#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */
-#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */
-#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
-#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */
-#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */
-#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */
-#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */
-#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
-#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */
-#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */
-#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */
-#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */
-#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */
-#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */
-#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */
-#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */
-#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
-#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */
-
-/* Bit fields for EMU LOCK */
-#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */
-#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */
-#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
-#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
-#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */
-#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */
-#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */
-#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */
-#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */
-#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */
-#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */
-#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */
-#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */
-#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */
-
-/* Bit fields for EMU RAM0CTRL */
-#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */
-#define _EMU_RAM0CTRL_MASK 0x00000001UL /**< Mask for EMU_RAM0CTRL */
-#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */
-#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x1UL /**< Bit mask for EMU_RAMPOWERDOWN */
-#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */
-#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */
-#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1 0x00000001UL /**< Mode BLK1 for EMU_RAM0CTRL */
-#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */
-#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */
-#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1 << 0) /**< Shifted mode BLK1 for EMU_RAM0CTRL */
-
-/* Bit fields for EMU CMD */
-#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */
-#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */
-#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */
-#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */
-#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */
-#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */
-#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */
-#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */
-#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */
-#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */
-#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */
-#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */
-#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */
-#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */
-#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */
-#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */
-#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */
-
-/* Bit fields for EMU EM4CTRL */
-#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */
-#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */
-#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */
-#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */
-#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */
-#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
-#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */
-#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */
-#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
-#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */
-#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */
-#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */
-#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */
-#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */
-#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
-#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
-#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */
-#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */
-#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */
-#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
-#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
-#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */
-#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */
-#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */
-#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
-#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
-#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */
-#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */
-#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
-#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */
-#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */
-#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */
-#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
-#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */
-#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */
-#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */
-#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */
-#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */
-#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
-#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
-
-/* Bit fields for EMU TEMPLIMITS */
-#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */
-#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */
-#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */
-#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */
-#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */
-#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */
-#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */
-#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */
-#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */
-#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */
-#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */
-#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */
-#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */
-#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */
-#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */
-
-/* Bit fields for EMU TEMP */
-#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */
-#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */
-#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */
-#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */
-#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */
-#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */
-
-/* Bit fields for EMU IF */
-#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */
-#define _EMU_IF_MASK 0xE31FC0FFUL /**< Mask for EMU_IF */
-#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */
-#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */
-#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */
-#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
-#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */
-#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */
-#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */
-#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */
-#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
-#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */
-#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */
-#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */
-#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */
-#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
-#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */
-#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */
-#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */
-#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */
-#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
-#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */
-#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */
-#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */
-#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */
-#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
-#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */
-#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */
-#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */
-#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */
-#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
-#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */
-#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */
-#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */
-#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */
-#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
-#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */
-#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */
-#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */
-#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */
-#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
-#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */
-#define EMU_IF_VMONFVDDFALL (0x1UL << 14) /**< VMON VDDFLASH Channel Fall */
-#define _EMU_IF_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */
-#define _EMU_IF_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */
-#define _EMU_IF_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
-#define EMU_IF_VMONFVDDFALL_DEFAULT (_EMU_IF_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IF */
-#define EMU_IF_VMONFVDDRISE (0x1UL << 15) /**< VMON VDDFLASH Channel Rise */
-#define _EMU_IF_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */
-#define _EMU_IF_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */
-#define _EMU_IF_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
-#define EMU_IF_VMONFVDDRISE_DEFAULT (_EMU_IF_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IF */
-#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */
-#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
-#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
-#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
-#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */
-#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */
-#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
-#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
-#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
-#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */
-#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */
-#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */
-#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */
-#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
-#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */
-#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */
-#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */
-#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */
-#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
-#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */
-#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */
-#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */
-#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */
-#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
-#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */
-#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */
-#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */
-#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */
-#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
-#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */
-#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */
-#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */
-#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */
-#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
-#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */
-#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */
-#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */
-#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */
-#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
-#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */
-#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */
-#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */
-#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */
-#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
-#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */
-#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */
-#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */
-#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */
-#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
-#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */
-
-/* Bit fields for EMU IFS */
-#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */
-#define _EMU_IFS_MASK 0xE31FC0FFUL /**< Mask for EMU_IFS */
-#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */
-#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */
-#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */
-#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
-#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */
-#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */
-#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */
-#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */
-#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
-#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */
-#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */
-#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */
-#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */
-#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
-#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */
-#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */
-#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */
-#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */
-#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
-#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */
-#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */
-#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */
-#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */
-#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
-#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */
-#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */
-#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */
-#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */
-#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
-#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */
-#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */
-#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */
-#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */
-#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
-#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */
-#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */
-#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */
-#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */
-#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
-#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */
-#define EMU_IFS_VMONFVDDFALL (0x1UL << 14) /**< Set VMONFVDDFALL Interrupt Flag */
-#define _EMU_IFS_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */
-#define _EMU_IFS_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */
-#define _EMU_IFS_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
-#define EMU_IFS_VMONFVDDFALL_DEFAULT (_EMU_IFS_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IFS */
-#define EMU_IFS_VMONFVDDRISE (0x1UL << 15) /**< Set VMONFVDDRISE Interrupt Flag */
-#define _EMU_IFS_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */
-#define _EMU_IFS_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */
-#define _EMU_IFS_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
-#define EMU_IFS_VMONFVDDRISE_DEFAULT (_EMU_IFS_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IFS */
-#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */
-#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
-#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
-#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
-#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */
-#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */
-#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
-#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
-#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
-#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */
-#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */
-#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */
-#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */
-#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
-#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */
-#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */
-#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */
-#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */
-#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
-#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */
-#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */
-#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */
-#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */
-#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
-#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */
-#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */
-#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */
-#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */
-#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
-#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */
-#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */
-#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */
-#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */
-#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
-#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */
-#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */
-#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */
-#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */
-#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
-#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */
-#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */
-#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */
-#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */
-#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
-#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */
-#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */
-#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */
-#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */
-#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
-#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */
-
-/* Bit fields for EMU IFC */
-#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */
-#define _EMU_IFC_MASK 0xE31FC0FFUL /**< Mask for EMU_IFC */
-#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */
-#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */
-#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */
-#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
-#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */
-#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */
-#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */
-#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */
-#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
-#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */
-#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */
-#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */
-#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */
-#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
-#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */
-#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */
-#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */
-#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */
-#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
-#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */
-#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */
-#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */
-#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */
-#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
-#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */
-#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */
-#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */
-#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */
-#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
-#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */
-#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */
-#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */
-#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */
-#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
-#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */
-#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */
-#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */
-#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */
-#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
-#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */
-#define EMU_IFC_VMONFVDDFALL (0x1UL << 14) /**< Clear VMONFVDDFALL Interrupt Flag */
-#define _EMU_IFC_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */
-#define _EMU_IFC_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */
-#define _EMU_IFC_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
-#define EMU_IFC_VMONFVDDFALL_DEFAULT (_EMU_IFC_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IFC */
-#define EMU_IFC_VMONFVDDRISE (0x1UL << 15) /**< Clear VMONFVDDRISE Interrupt Flag */
-#define _EMU_IFC_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */
-#define _EMU_IFC_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */
-#define _EMU_IFC_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
-#define EMU_IFC_VMONFVDDRISE_DEFAULT (_EMU_IFC_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IFC */
-#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */
-#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
-#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
-#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
-#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */
-#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */
-#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
-#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
-#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
-#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */
-#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */
-#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */
-#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */
-#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
-#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */
-#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */
-#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */
-#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */
-#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
-#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */
-#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */
-#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */
-#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */
-#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
-#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */
-#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */
-#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */
-#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */
-#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
-#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */
-#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */
-#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */
-#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */
-#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
-#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */
-#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */
-#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */
-#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */
-#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
-#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */
-#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */
-#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */
-#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */
-#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
-#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */
-#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */
-#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */
-#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */
-#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
-#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */
-
-/* Bit fields for EMU IEN */
-#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */
-#define _EMU_IEN_MASK 0xE31FC0FFUL /**< Mask for EMU_IEN */
-#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */
-#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */
-#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */
-#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
-#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */
-#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */
-#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */
-#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */
-#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
-#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */
-#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */
-#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */
-#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */
-#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
-#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */
-#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */
-#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */
-#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */
-#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
-#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */
-#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */
-#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */
-#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */
-#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
-#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */
-#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */
-#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */
-#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */
-#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
-#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */
-#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */
-#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */
-#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */
-#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
-#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */
-#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */
-#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */
-#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */
-#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
-#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */
-#define EMU_IEN_VMONFVDDFALL (0x1UL << 14) /**< VMONFVDDFALL Interrupt Enable */
-#define _EMU_IEN_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */
-#define _EMU_IEN_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */
-#define _EMU_IEN_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
-#define EMU_IEN_VMONFVDDFALL_DEFAULT (_EMU_IEN_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IEN */
-#define EMU_IEN_VMONFVDDRISE (0x1UL << 15) /**< VMONFVDDRISE Interrupt Enable */
-#define _EMU_IEN_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */
-#define _EMU_IEN_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */
-#define _EMU_IEN_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
-#define EMU_IEN_VMONFVDDRISE_DEFAULT (_EMU_IEN_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IEN */
-#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */
-#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
-#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
-#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
-#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */
-#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */
-#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
-#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
-#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
-#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */
-#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */
-#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */
-#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */
-#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
-#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */
-#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */
-#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */
-#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */
-#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
-#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */
-#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */
-#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */
-#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */
-#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
-#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */
-#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */
-#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */
-#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */
-#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
-#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */
-#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */
-#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */
-#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */
-#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
-#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */
-#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */
-#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */
-#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */
-#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
-#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */
-#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */
-#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */
-#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */
-#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
-#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */
-#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */
-#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */
-#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */
-#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
-#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */
-
-/* Bit fields for EMU PWRLOCK */
-#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */
-#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */
-#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
-#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
-#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */
-#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */
-#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */
-#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */
-#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */
-#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */
-#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */
-#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */
-#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */
-#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */
-
-/* Bit fields for EMU PWRCTRL */
-#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */
-#define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */
-#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */
-#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */
-#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */
-#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */
-#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */
-#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */
-#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */
-#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */
-#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */
-#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */
-#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */
-#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */
-#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */
-#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */
-#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */
-#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */
-#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */
-#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */
-#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */
-#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */
-#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */
-#define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */
-#define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */
-
-/* Bit fields for EMU DCDCCTRL */
-#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */
-#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */
-#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */
-#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */
-#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */
-#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */
-#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */
-#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */
-#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */
-#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */
-#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */
-#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */
-#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */
-#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */
-#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */
-#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */
-#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */
-#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */
-#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */
-#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */
-#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */
-#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */
-#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */
-#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */
-#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */
-#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */
-#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */
-#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */
-#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */
-#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */
-#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */
-#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */
-
-/* Bit fields for EMU DCDCMISCCTRL */
-#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */
-#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */
-#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */
-#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */
-#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */
-#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
-#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
-#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */
-#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */
-#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */
-#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
-#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
-#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */
-#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */
-#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */
-#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
-#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
-#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */
-#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */
-#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */
-#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
-#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
-#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */
-#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */
-#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
-#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
-#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */
-#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */
-#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
-#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
-#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */
-#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */
-#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
-#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
-#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */
-#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */
-#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
-#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
-#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */
-#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */
-#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
-#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
-#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */
-#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */
-#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
-#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */
-#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */
-#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */
-#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */
-#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
-#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */
-#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */
-#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */
-#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */
-
-/* Bit fields for EMU DCDCZDETCTRL */
-#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */
-#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */
-#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */
-#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */
-#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */
-#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */
-#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */
-#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */
-#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */
-#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */
-
-/* Bit fields for EMU DCDCCLIMCTRL */
-#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */
-#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */
-#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */
-#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */
-#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */
-#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */
-#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */
-#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */
-#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */
-#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */
-#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */
-
-/* Bit fields for EMU DCDCLNCOMPCTRL */
-#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */
-#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */
-#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */
-#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */
-#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
-#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
-#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */
-#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */
-#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
-#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
-#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */
-#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */
-#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
-#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
-#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */
-#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */
-#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
-#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
-#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */
-#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */
-#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
-#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
-#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */
-#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */
-#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
-#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
-
-/* Bit fields for EMU DCDCLNVCTRL */
-#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */
-#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */
-#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */
-#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */
-#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */
-#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */
-#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */
-#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */
-#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */
-#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */
-#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */
-#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */
-#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */
-#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */
-#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */
-
-/* Bit fields for EMU DCDCLPVCTRL */
-#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */
-#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */
-#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */
-#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */
-#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */
-#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */
-#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */
-#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */
-#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */
-#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */
-#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */
-#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */
-#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */
-#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */
-#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */
-
-/* Bit fields for EMU DCDCLPCTRL */
-#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */
-#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */
-#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */
-#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */
-#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */
-#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */
-#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */
-#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */
-#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */
-#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */
-#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */
-#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */
-#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */
-#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */
-#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */
-
-/* Bit fields for EMU DCDCLNFREQCTRL */
-#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */
-#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */
-#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */
-#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */
-#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */
-#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */
-#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */
-#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */
-#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */
-#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */
-
-/* Bit fields for EMU DCDCSYNC */
-#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */
-#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */
-#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */
-#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */
-#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */
-#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */
-#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */
-
-/* Bit fields for EMU VMONAVDDCTRL */
-#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */
-#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */
-#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */
-#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */
-#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */
-#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
-#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
-#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */
-#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */
-#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */
-#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
-#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
-#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */
-#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */
-#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */
-#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
-#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
-#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */
-#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */
-#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
-#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
-#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */
-#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */
-#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
-#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
-#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */
-#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */
-#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
-#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
-#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */
-#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */
-#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
-#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
-
-/* Bit fields for EMU VMONALTAVDDCTRL */
-#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */
-#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */
-#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */
-#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */
-#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */
-#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
-#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
-#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */
-#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */
-#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */
-#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
-#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
-#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */
-#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */
-#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */
-#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
-#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
-#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */
-#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */
-#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
-#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
-#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */
-#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */
-#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
-#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
-
-/* Bit fields for EMU VMONDVDDCTRL */
-#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */
-#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */
-#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */
-#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */
-#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */
-#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
-#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
-#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */
-#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */
-#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */
-#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
-#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
-#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */
-#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */
-#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */
-#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
-#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
-#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */
-#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */
-#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
-#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
-#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */
-#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */
-#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
-#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
-
-/* Bit fields for EMU VMONIO0CTRL */
-#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */
-#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */
-#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */
-#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */
-#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */
-#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
-#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
-#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */
-#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */
-#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */
-#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
-#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
-#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */
-#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */
-#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */
-#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
-#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
-#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */
-#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */
-#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */
-#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
-#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
-#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */
-#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */
-#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
-#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
-#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */
-#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */
-#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
-#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
-
-/* Bit fields for EMU RAM1CTRL */
-#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */
-#define _EMU_RAM1CTRL_MASK 0x00000003UL /**< Mask for EMU_RAM1CTRL */
-#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */
-#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0x3UL /**< Bit mask for EMU_RAMPOWERDOWN */
-#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */
-#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */
-#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1 0x00000002UL /**< Mode BLK1 for EMU_RAM1CTRL */
-#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO1 0x00000003UL /**< Mode BLK0TO1 for EMU_RAM1CTRL */
-#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */
-#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */
-#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1 << 0) /**< Shifted mode BLK1 for EMU_RAM1CTRL */
-#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO1 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO1 << 0) /**< Shifted mode BLK0TO1 for EMU_RAM1CTRL */
-
-/* Bit fields for EMU RAM2CTRL */
-#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */
-#define _EMU_RAM2CTRL_MASK 0x00000001UL /**< Mask for EMU_RAM2CTRL */
-#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */
-#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0x1UL /**< Bit mask for EMU_RAMPOWERDOWN */
-#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */
-#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */
-#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK 0x00000001UL /**< Mode BLK for EMU_RAM2CTRL */
-#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */
-#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */
-#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK << 0) /**< Shifted mode BLK for EMU_RAM2CTRL */
-
-/* Bit fields for EMU DCDCLPEM01CFG */
-#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */
-#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */
-#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */
-#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */
-#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */
-#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */
-#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */
-#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */
-#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */
-#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */
-#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */
-#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */
-#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */
-#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */
-#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */
-#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */
-#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */
-#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */
-
-/* Bit fields for EMU EM23PERNORETAINCMD */
-#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */
-#define _EMU_EM23PERNORETAINCMD_MASK 0x0000FFE7UL /**< Mask for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */
-#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */
-#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */
-#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */
-#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */
-#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */
-#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */
-#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */
-#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */
-#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */
-#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */
-#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */
-#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */
-#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */
-#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */
-#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */
-#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */
-#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */
-#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */
-#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */
-#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */
-#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */
-#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */
-#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */
-#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */
-#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */
-#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */
-#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */
-#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */
-#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */
-#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */
-#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */
-#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */
-#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */
-#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */
-#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */
-#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */
-#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */
-#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */
-#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */
-#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */
-#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */
-#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
-#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
-
-/* Bit fields for EMU EM23PERNORETAINSTATUS */
-#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */
-#define _EMU_EM23PERNORETAINSTATUS_MASK 0x0000FFE7UL /**< Mask for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */
-#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */
-#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */
-#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */
-#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */
-#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */
-#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */
-#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */
-#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */
-#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */
-#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */
-#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */
-#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */
-#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */
-#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */
-#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */
-#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */
-#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */
-#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */
-#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */
-#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */
-#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */
-#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */
-#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */
-#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */
-#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */
-#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */
-#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */
-#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */
-#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */
-#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */
-#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */
-#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */
-#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */
-#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */
-#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */
-#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */
-#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */
-#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */
-#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */
-#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */
-#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */
-#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
-
-/* Bit fields for EMU EM23PERNORETAINCTRL */
-#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */
-#define _EMU_EM23PERNORETAINCTRL_MASK 0x0000FFE7UL /**< Mask for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */
-#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */
-#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */
-#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */
-#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */
-#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */
-#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */
-#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */
-#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */
-#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */
-#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */
-#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */
-#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */
-#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */
-#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */
-#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_DAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */
-#define _EMU_EM23PERNORETAINCTRL_DAC0DIS_SHIFT 7 /**< Shift value for EMU_DAC0DIS */
-#define _EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK 0x80UL /**< Bit mask for EMU_DAC0DIS */
-#define _EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */
-#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */
-#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */
-#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */
-#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */
-#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */
-#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */
-#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */
-#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */
-#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */
-#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */
-#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */
-#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */
-#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */
-#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */
-#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */
-#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */
-#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */
-#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */
-#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */
-#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */
-#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */
-#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */
-#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */
-#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
-
-/** @} */
-/** @} End of group EFR32FG13P_EMU */
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_etm.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_etm.h
deleted file mode 100644
index 01f718c0..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_etm.h
+++ /dev/null
@@ -1,790 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_etm.h
- * @brief EFR32FG13P_ETM register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P_ETM ETM
- * @{
- * @brief EFR32FG13P_ETM Register Declaration
- *****************************************************************************/
-/** ETM Register Declaration */
-typedef struct {
- __IOM uint32_t ETMCR; /**< Main Control Register */
- __IM uint32_t ETMCCR; /**< Configuration Code Register */
- __IOM uint32_t ETMTRIGGER; /**< ETM Trigger Event Register */
- uint32_t RESERVED0[1]; /**< Reserved for future use **/
- __IOM uint32_t ETMSR; /**< ETM Status Register */
- __IM uint32_t ETMSCR; /**< ETM System Configuration Register */
- uint32_t RESERVED1[2]; /**< Reserved for future use **/
- __IOM uint32_t ETMTEEVR; /**< ETM TraceEnable Event Register */
- __IOM uint32_t ETMTECR1; /**< ETM Trace control Register */
- uint32_t RESERVED2[1]; /**< Reserved for future use **/
- __IOM uint32_t ETMFFLR; /**< ETM Fifo Full Level Register */
- uint32_t RESERVED3[68]; /**< Reserved for future use **/
- __IOM uint32_t ETMCNTRLDVR1; /**< Counter Reload Value */
- uint32_t RESERVED4[39]; /**< Reserved for future use **/
- __IOM uint32_t ETMSYNCFR; /**< Synchronisation Frequency Register */
- __IM uint32_t ETMIDR; /**< ID Register */
- __IM uint32_t ETMCCER; /**< Configuration Code Extension Register */
- uint32_t RESERVED5[1]; /**< Reserved for future use **/
- __IOM uint32_t ETMTESSEICR; /**< TraceEnable Start/Stop EmbeddedICE Control Register */
- uint32_t RESERVED6[1]; /**< Reserved for future use **/
- __IOM uint32_t ETMTSEVR; /**< Timestamp Event Register */
- uint32_t RESERVED7[1]; /**< Reserved for future use **/
- __IOM uint32_t ETMTRACEIDR; /**< CoreSight Trace ID Register */
- uint32_t RESERVED8[1]; /**< Reserved for future use **/
- __IM uint32_t ETMIDR2; /**< ETM ID Register 2 */
- uint32_t RESERVED9[66]; /**< Reserved for future use **/
- __IM uint32_t ETMPDSR; /**< Device Power-down Status Register */
- uint32_t RESERVED10[754]; /**< Reserved for future use **/
- __IOM uint32_t ETMISCIN; /**< Integration Test Miscellaneous Inputs Register */
- uint32_t RESERVED11[1]; /**< Reserved for future use **/
- __IOM uint32_t ITTRIGOUT; /**< Integration Test Trigger Out Register */
- uint32_t RESERVED12[1]; /**< Reserved for future use **/
- __IM uint32_t ETMITATBCTR2; /**< ETM Integration Test ATB Control 2 Register */
- uint32_t RESERVED13[1]; /**< Reserved for future use **/
- __IOM uint32_t ETMITATBCTR0; /**< ETM Integration Test ATB Control 0 Register */
- uint32_t RESERVED14[1]; /**< Reserved for future use **/
- __IOM uint32_t ETMITCTRL; /**< ETM Integration Control Register */
- uint32_t RESERVED15[39]; /**< Reserved for future use **/
- __IOM uint32_t ETMCLAIMSET; /**< ETM Claim Tag Set Register */
- __IOM uint32_t ETMCLAIMCLR; /**< ETM Claim Tag Clear Register */
- uint32_t RESERVED16[2]; /**< Reserved for future use **/
- __IOM uint32_t ETMLAR; /**< ETM Lock Access Register */
- __IM uint32_t ETMLSR; /**< Lock Status Register */
- __IM uint32_t ETMAUTHSTATUS; /**< ETM Authentication Status Register */
- uint32_t RESERVED17[4]; /**< Reserved for future use **/
- __IM uint32_t ETMDEVTYPE; /**< CoreSight Device Type Register */
- __IM uint32_t ETMPIDR4; /**< Peripheral ID4 Register */
- __OM uint32_t ETMPIDR5; /**< Peripheral ID5 Register */
- __OM uint32_t ETMPIDR6; /**< Peripheral ID6 Register */
- __OM uint32_t ETMPIDR7; /**< Peripheral ID7 Register */
- __IM uint32_t ETMPIDR0; /**< Peripheral ID0 Register */
- __IM uint32_t ETMPIDR1; /**< Peripheral ID1 Register */
- __IM uint32_t ETMPIDR2; /**< Peripheral ID2 Register */
- __IM uint32_t ETMPIDR3; /**< Peripheral ID3 Register */
- __IM uint32_t ETMCIDR0; /**< Component ID0 Register */
- __IM uint32_t ETMCIDR1; /**< Component ID1 Register */
- __IM uint32_t ETMCIDR2; /**< Component ID2 Register */
- __IM uint32_t ETMCIDR3; /**< Component ID3 Register */
-} ETM_TypeDef; /** @} */
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_ETM
- * @{
- * @defgroup EFR32FG13P_ETM_BitFields ETM Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for ETM ETMCR */
-#define _ETM_ETMCR_RESETVALUE 0x00000411UL /**< Default value for ETM_ETMCR */
-#define _ETM_ETMCR_MASK 0x10632FF1UL /**< Mask for ETM_ETMCR */
-#define ETM_ETMCR_POWERDWN (0x1UL << 0) /**< ETM Control in low power mode */
-#define _ETM_ETMCR_POWERDWN_SHIFT 0 /**< Shift value for ETM_POWERDWN */
-#define _ETM_ETMCR_POWERDWN_MASK 0x1UL /**< Bit mask for ETM_POWERDWN */
-#define _ETM_ETMCR_POWERDWN_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */
-#define ETM_ETMCR_POWERDWN_DEFAULT (_ETM_ETMCR_POWERDWN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCR */
-#define _ETM_ETMCR_PORTSIZE_SHIFT 4 /**< Shift value for ETM_PORTSIZE */
-#define _ETM_ETMCR_PORTSIZE_MASK 0x70UL /**< Bit mask for ETM_PORTSIZE */
-#define _ETM_ETMCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */
-#define ETM_ETMCR_PORTSIZE_DEFAULT (_ETM_ETMCR_PORTSIZE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCR */
-#define ETM_ETMCR_STALL (0x1UL << 7) /**< Stall Processor */
-#define _ETM_ETMCR_STALL_SHIFT 7 /**< Shift value for ETM_STALL */
-#define _ETM_ETMCR_STALL_MASK 0x80UL /**< Bit mask for ETM_STALL */
-#define _ETM_ETMCR_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
-#define ETM_ETMCR_STALL_DEFAULT (_ETM_ETMCR_STALL_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMCR */
-#define ETM_ETMCR_BRANCHOUTPUT (0x1UL << 8) /**< Branch Output */
-#define _ETM_ETMCR_BRANCHOUTPUT_SHIFT 8 /**< Shift value for ETM_BRANCHOUTPUT */
-#define _ETM_ETMCR_BRANCHOUTPUT_MASK 0x100UL /**< Bit mask for ETM_BRANCHOUTPUT */
-#define _ETM_ETMCR_BRANCHOUTPUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
-#define ETM_ETMCR_BRANCHOUTPUT_DEFAULT (_ETM_ETMCR_BRANCHOUTPUT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCR */
-#define ETM_ETMCR_DBGREQCTRL (0x1UL << 9) /**< Debug Request Control */
-#define _ETM_ETMCR_DBGREQCTRL_SHIFT 9 /**< Shift value for ETM_DBGREQCTRL */
-#define _ETM_ETMCR_DBGREQCTRL_MASK 0x200UL /**< Bit mask for ETM_DBGREQCTRL */
-#define _ETM_ETMCR_DBGREQCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
-#define ETM_ETMCR_DBGREQCTRL_DEFAULT (_ETM_ETMCR_DBGREQCTRL_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMCR */
-#define ETM_ETMCR_ETMPROG (0x1UL << 10) /**< ETM Programming */
-#define _ETM_ETMCR_ETMPROG_SHIFT 10 /**< Shift value for ETM_ETMPROG */
-#define _ETM_ETMCR_ETMPROG_MASK 0x400UL /**< Bit mask for ETM_ETMPROG */
-#define _ETM_ETMCR_ETMPROG_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */
-#define ETM_ETMCR_ETMPROG_DEFAULT (_ETM_ETMCR_ETMPROG_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMCR */
-#define ETM_ETMCR_ETMPORTSEL (0x1UL << 11) /**< ETM Port Selection */
-#define _ETM_ETMCR_ETMPORTSEL_SHIFT 11 /**< Shift value for ETM_ETMPORTSEL */
-#define _ETM_ETMCR_ETMPORTSEL_MASK 0x800UL /**< Bit mask for ETM_ETMPORTSEL */
-#define _ETM_ETMCR_ETMPORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
-#define _ETM_ETMCR_ETMPORTSEL_ETMLOW 0x00000000UL /**< Mode ETMLOW for ETM_ETMCR */
-#define _ETM_ETMCR_ETMPORTSEL_ETMHIGH 0x00000001UL /**< Mode ETMHIGH for ETM_ETMCR */
-#define ETM_ETMCR_ETMPORTSEL_DEFAULT (_ETM_ETMCR_ETMPORTSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCR */
-#define ETM_ETMCR_ETMPORTSEL_ETMLOW (_ETM_ETMCR_ETMPORTSEL_ETMLOW << 11) /**< Shifted mode ETMLOW for ETM_ETMCR */
-#define ETM_ETMCR_ETMPORTSEL_ETMHIGH (_ETM_ETMCR_ETMPORTSEL_ETMHIGH << 11) /**< Shifted mode ETMHIGH for ETM_ETMCR */
-#define ETM_ETMCR_PORTMODE2 (0x1UL << 13) /**< Port Mode[2] */
-#define _ETM_ETMCR_PORTMODE2_SHIFT 13 /**< Shift value for ETM_PORTMODE2 */
-#define _ETM_ETMCR_PORTMODE2_MASK 0x2000UL /**< Bit mask for ETM_PORTMODE2 */
-#define _ETM_ETMCR_PORTMODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
-#define ETM_ETMCR_PORTMODE2_DEFAULT (_ETM_ETMCR_PORTMODE2_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCR */
-#define _ETM_ETMCR_PORTMODE_SHIFT 16 /**< Shift value for ETM_PORTMODE */
-#define _ETM_ETMCR_PORTMODE_MASK 0x30000UL /**< Bit mask for ETM_PORTMODE */
-#define _ETM_ETMCR_PORTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
-#define ETM_ETMCR_PORTMODE_DEFAULT (_ETM_ETMCR_PORTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCR */
-#define _ETM_ETMCR_EPORTSIZE_SHIFT 21 /**< Shift value for ETM_EPORTSIZE */
-#define _ETM_ETMCR_EPORTSIZE_MASK 0x600000UL /**< Bit mask for ETM_EPORTSIZE */
-#define _ETM_ETMCR_EPORTSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
-#define ETM_ETMCR_EPORTSIZE_DEFAULT (_ETM_ETMCR_EPORTSIZE_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCR */
-#define ETM_ETMCR_TSTAMPEN (0x1UL << 28) /**< Time Stamp Enable */
-#define _ETM_ETMCR_TSTAMPEN_SHIFT 28 /**< Shift value for ETM_TSTAMPEN */
-#define _ETM_ETMCR_TSTAMPEN_MASK 0x10000000UL /**< Bit mask for ETM_TSTAMPEN */
-#define _ETM_ETMCR_TSTAMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
-#define ETM_ETMCR_TSTAMPEN_DEFAULT (_ETM_ETMCR_TSTAMPEN_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCR */
-
-/* Bit fields for ETM ETMCCR */
-#define _ETM_ETMCCR_RESETVALUE 0x8C802000UL /**< Default value for ETM_ETMCCR */
-#define _ETM_ETMCCR_MASK 0x8FFFFFFFUL /**< Mask for ETM_ETMCCR */
-#define _ETM_ETMCCR_ADRCMPPAIR_SHIFT 0 /**< Shift value for ETM_ADRCMPPAIR */
-#define _ETM_ETMCCR_ADRCMPPAIR_MASK 0xFUL /**< Bit mask for ETM_ADRCMPPAIR */
-#define _ETM_ETMCCR_ADRCMPPAIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
-#define ETM_ETMCCR_ADRCMPPAIR_DEFAULT (_ETM_ETMCCR_ADRCMPPAIR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCR */
-#define _ETM_ETMCCR_DATACMPNUM_SHIFT 4 /**< Shift value for ETM_DATACMPNUM */
-#define _ETM_ETMCCR_DATACMPNUM_MASK 0xF0UL /**< Bit mask for ETM_DATACMPNUM */
-#define _ETM_ETMCCR_DATACMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
-#define ETM_ETMCCR_DATACMPNUM_DEFAULT (_ETM_ETMCCR_DATACMPNUM_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCCR */
-#define _ETM_ETMCCR_MMDECCNT_SHIFT 8 /**< Shift value for ETM_MMDECCNT */
-#define _ETM_ETMCCR_MMDECCNT_MASK 0x1F00UL /**< Bit mask for ETM_MMDECCNT */
-#define _ETM_ETMCCR_MMDECCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
-#define ETM_ETMCCR_MMDECCNT_DEFAULT (_ETM_ETMCCR_MMDECCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCCR */
-#define _ETM_ETMCCR_COUNTNUM_SHIFT 13 /**< Shift value for ETM_COUNTNUM */
-#define _ETM_ETMCCR_COUNTNUM_MASK 0xE000UL /**< Bit mask for ETM_COUNTNUM */
-#define _ETM_ETMCCR_COUNTNUM_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
-#define ETM_ETMCCR_COUNTNUM_DEFAULT (_ETM_ETMCCR_COUNTNUM_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCR */
-#define ETM_ETMCCR_SEQPRES (0x1UL << 16) /**< Sequencer Present */
-#define _ETM_ETMCCR_SEQPRES_SHIFT 16 /**< Shift value for ETM_SEQPRES */
-#define _ETM_ETMCCR_SEQPRES_MASK 0x10000UL /**< Bit mask for ETM_SEQPRES */
-#define _ETM_ETMCCR_SEQPRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
-#define ETM_ETMCCR_SEQPRES_DEFAULT (_ETM_ETMCCR_SEQPRES_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCR */
-#define _ETM_ETMCCR_EXTINPNUM_SHIFT 17 /**< Shift value for ETM_EXTINPNUM */
-#define _ETM_ETMCCR_EXTINPNUM_MASK 0xE0000UL /**< Bit mask for ETM_EXTINPNUM */
-#define _ETM_ETMCCR_EXTINPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
-#define _ETM_ETMCCR_EXTINPNUM_ZERO 0x00000000UL /**< Mode ZERO for ETM_ETMCCR */
-#define _ETM_ETMCCR_EXTINPNUM_ONE 0x00000001UL /**< Mode ONE for ETM_ETMCCR */
-#define _ETM_ETMCCR_EXTINPNUM_TWO 0x00000002UL /**< Mode TWO for ETM_ETMCCR */
-#define ETM_ETMCCR_EXTINPNUM_DEFAULT (_ETM_ETMCCR_EXTINPNUM_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMCCR */
-#define ETM_ETMCCR_EXTINPNUM_ZERO (_ETM_ETMCCR_EXTINPNUM_ZERO << 17) /**< Shifted mode ZERO for ETM_ETMCCR */
-#define ETM_ETMCCR_EXTINPNUM_ONE (_ETM_ETMCCR_EXTINPNUM_ONE << 17) /**< Shifted mode ONE for ETM_ETMCCR */
-#define ETM_ETMCCR_EXTINPNUM_TWO (_ETM_ETMCCR_EXTINPNUM_TWO << 17) /**< Shifted mode TWO for ETM_ETMCCR */
-#define _ETM_ETMCCR_EXTOUTNUM_SHIFT 20 /**< Shift value for ETM_EXTOUTNUM */
-#define _ETM_ETMCCR_EXTOUTNUM_MASK 0x700000UL /**< Bit mask for ETM_EXTOUTNUM */
-#define _ETM_ETMCCR_EXTOUTNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
-#define ETM_ETMCCR_EXTOUTNUM_DEFAULT (_ETM_ETMCCR_EXTOUTNUM_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCR */
-#define ETM_ETMCCR_FIFOFULLPRES (0x1UL << 23) /**< FIFIO FULL present */
-#define _ETM_ETMCCR_FIFOFULLPRES_SHIFT 23 /**< Shift value for ETM_FIFOFULLPRES */
-#define _ETM_ETMCCR_FIFOFULLPRES_MASK 0x800000UL /**< Bit mask for ETM_FIFOFULLPRES */
-#define _ETM_ETMCCR_FIFOFULLPRES_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
-#define ETM_ETMCCR_FIFOFULLPRES_DEFAULT (_ETM_ETMCCR_FIFOFULLPRES_DEFAULT << 23) /**< Shifted mode DEFAULT for ETM_ETMCCR */
-#define _ETM_ETMCCR_IDCOMPNUM_SHIFT 24 /**< Shift value for ETM_IDCOMPNUM */
-#define _ETM_ETMCCR_IDCOMPNUM_MASK 0x3000000UL /**< Bit mask for ETM_IDCOMPNUM */
-#define _ETM_ETMCCR_IDCOMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
-#define ETM_ETMCCR_IDCOMPNUM_DEFAULT (_ETM_ETMCCR_IDCOMPNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMCCR */
-#define ETM_ETMCCR_TRACESS (0x1UL << 26) /**< Trace Start/Stop Block Present */
-#define _ETM_ETMCCR_TRACESS_SHIFT 26 /**< Shift value for ETM_TRACESS */
-#define _ETM_ETMCCR_TRACESS_MASK 0x4000000UL /**< Bit mask for ETM_TRACESS */
-#define _ETM_ETMCCR_TRACESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
-#define ETM_ETMCCR_TRACESS_DEFAULT (_ETM_ETMCCR_TRACESS_DEFAULT << 26) /**< Shifted mode DEFAULT for ETM_ETMCCR */
-#define ETM_ETMCCR_MMACCESS (0x1UL << 27) /**< Coprocessor and Memeory Access */
-#define _ETM_ETMCCR_MMACCESS_SHIFT 27 /**< Shift value for ETM_MMACCESS */
-#define _ETM_ETMCCR_MMACCESS_MASK 0x8000000UL /**< Bit mask for ETM_MMACCESS */
-#define _ETM_ETMCCR_MMACCESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
-#define ETM_ETMCCR_MMACCESS_DEFAULT (_ETM_ETMCCR_MMACCESS_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCR */
-#define ETM_ETMCCR_ETMID (0x1UL << 31) /**< ETM ID Register Present */
-#define _ETM_ETMCCR_ETMID_SHIFT 31 /**< Shift value for ETM_ETMID */
-#define _ETM_ETMCCR_ETMID_MASK 0x80000000UL /**< Bit mask for ETM_ETMID */
-#define _ETM_ETMCCR_ETMID_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
-#define ETM_ETMCCR_ETMID_DEFAULT (_ETM_ETMCCR_ETMID_DEFAULT << 31) /**< Shifted mode DEFAULT for ETM_ETMCCR */
-
-/* Bit fields for ETM ETMTRIGGER */
-#define _ETM_ETMTRIGGER_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRIGGER */
-#define _ETM_ETMTRIGGER_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTRIGGER */
-#define _ETM_ETMTRIGGER_RESA_SHIFT 0 /**< Shift value for ETM_RESA */
-#define _ETM_ETMTRIGGER_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */
-#define _ETM_ETMTRIGGER_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */
-#define ETM_ETMTRIGGER_RESA_DEFAULT (_ETM_ETMTRIGGER_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */
-#define _ETM_ETMTRIGGER_RESB_SHIFT 7 /**< Shift value for ETM_RESB */
-#define _ETM_ETMTRIGGER_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */
-#define _ETM_ETMTRIGGER_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */
-#define ETM_ETMTRIGGER_RESB_DEFAULT (_ETM_ETMTRIGGER_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */
-#define _ETM_ETMTRIGGER_ETMFCN_SHIFT 14 /**< Shift value for ETM_ETMFCN */
-#define _ETM_ETMTRIGGER_ETMFCN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCN */
-#define _ETM_ETMTRIGGER_ETMFCN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */
-#define ETM_ETMTRIGGER_ETMFCN_DEFAULT (_ETM_ETMTRIGGER_ETMFCN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */
-
-/* Bit fields for ETM ETMSR */
-#define _ETM_ETMSR_RESETVALUE 0x00000002UL /**< Default value for ETM_ETMSR */
-#define _ETM_ETMSR_MASK 0x0000000FUL /**< Mask for ETM_ETMSR */
-#define ETM_ETMSR_ETHOF (0x1UL << 0) /**< ETM Overflow */
-#define _ETM_ETMSR_ETHOF_SHIFT 0 /**< Shift value for ETM_ETHOF */
-#define _ETM_ETMSR_ETHOF_MASK 0x1UL /**< Bit mask for ETM_ETHOF */
-#define _ETM_ETMSR_ETHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */
-#define ETM_ETMSR_ETHOF_DEFAULT (_ETM_ETMSR_ETHOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSR */
-#define ETM_ETMSR_ETMPROGBIT (0x1UL << 1) /**< ETM Programming Bit Status */
-#define _ETM_ETMSR_ETMPROGBIT_SHIFT 1 /**< Shift value for ETM_ETMPROGBIT */
-#define _ETM_ETMSR_ETMPROGBIT_MASK 0x2UL /**< Bit mask for ETM_ETMPROGBIT */
-#define _ETM_ETMSR_ETMPROGBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSR */
-#define ETM_ETMSR_ETMPROGBIT_DEFAULT (_ETM_ETMSR_ETMPROGBIT_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMSR */
-#define ETM_ETMSR_TRACESTAT (0x1UL << 2) /**< Trace Start/Stop Status */
-#define _ETM_ETMSR_TRACESTAT_SHIFT 2 /**< Shift value for ETM_TRACESTAT */
-#define _ETM_ETMSR_TRACESTAT_MASK 0x4UL /**< Bit mask for ETM_TRACESTAT */
-#define _ETM_ETMSR_TRACESTAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */
-#define ETM_ETMSR_TRACESTAT_DEFAULT (_ETM_ETMSR_TRACESTAT_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMSR */
-#define ETM_ETMSR_TRIGBIT (0x1UL << 3) /**< Trigger Bit */
-#define _ETM_ETMSR_TRIGBIT_SHIFT 3 /**< Shift value for ETM_TRIGBIT */
-#define _ETM_ETMSR_TRIGBIT_MASK 0x8UL /**< Bit mask for ETM_TRIGBIT */
-#define _ETM_ETMSR_TRIGBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */
-#define ETM_ETMSR_TRIGBIT_DEFAULT (_ETM_ETMSR_TRIGBIT_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMSR */
-
-/* Bit fields for ETM ETMSCR */
-#define _ETM_ETMSCR_RESETVALUE 0x00020D09UL /**< Default value for ETM_ETMSCR */
-#define _ETM_ETMSCR_MASK 0x00027F0FUL /**< Mask for ETM_ETMSCR */
-#define _ETM_ETMSCR_MAXPORTSIZE_SHIFT 0 /**< Shift value for ETM_MAXPORTSIZE */
-#define _ETM_ETMSCR_MAXPORTSIZE_MASK 0x7UL /**< Bit mask for ETM_MAXPORTSIZE */
-#define _ETM_ETMSCR_MAXPORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
-#define ETM_ETMSCR_MAXPORTSIZE_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSCR */
-#define ETM_ETMSCR_FIFOFULL (0x1UL << 8) /**< FIFO FULL Supported */
-#define _ETM_ETMSCR_FIFOFULL_SHIFT 8 /**< Shift value for ETM_FIFOFULL */
-#define _ETM_ETMSCR_FIFOFULL_MASK 0x100UL /**< Bit mask for ETM_FIFOFULL */
-#define _ETM_ETMSCR_FIFOFULL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
-#define ETM_ETMSCR_FIFOFULL_DEFAULT (_ETM_ETMSCR_FIFOFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMSCR */
-#define ETM_ETMSCR_MAXPORTSIZE3 (0x1UL << 9) /**< Max Port Size[3] */
-#define _ETM_ETMSCR_MAXPORTSIZE3_SHIFT 9 /**< Shift value for ETM_MAXPORTSIZE3 */
-#define _ETM_ETMSCR_MAXPORTSIZE3_MASK 0x200UL /**< Bit mask for ETM_MAXPORTSIZE3 */
-#define _ETM_ETMSCR_MAXPORTSIZE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */
-#define ETM_ETMSCR_MAXPORTSIZE3_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE3_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMSCR */
-#define ETM_ETMSCR_PORTSIZE (0x1UL << 10) /**< Port Size Supported */
-#define _ETM_ETMSCR_PORTSIZE_SHIFT 10 /**< Shift value for ETM_PORTSIZE */
-#define _ETM_ETMSCR_PORTSIZE_MASK 0x400UL /**< Bit mask for ETM_PORTSIZE */
-#define _ETM_ETMSCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
-#define ETM_ETMSCR_PORTSIZE_DEFAULT (_ETM_ETMSCR_PORTSIZE_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMSCR */
-#define ETM_ETMSCR_PORTMODE (0x1UL << 11) /**< Port Mode Supported */
-#define _ETM_ETMSCR_PORTMODE_SHIFT 11 /**< Shift value for ETM_PORTMODE */
-#define _ETM_ETMSCR_PORTMODE_MASK 0x800UL /**< Bit mask for ETM_PORTMODE */
-#define _ETM_ETMSCR_PORTMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
-#define ETM_ETMSCR_PORTMODE_DEFAULT (_ETM_ETMSCR_PORTMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMSCR */
-#define _ETM_ETMSCR_PROCNUM_SHIFT 12 /**< Shift value for ETM_PROCNUM */
-#define _ETM_ETMSCR_PROCNUM_MASK 0x7000UL /**< Bit mask for ETM_PROCNUM */
-#define _ETM_ETMSCR_PROCNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */
-#define ETM_ETMSCR_PROCNUM_DEFAULT (_ETM_ETMSCR_PROCNUM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMSCR */
-#define ETM_ETMSCR_NOFETCHCOMP (0x1UL << 17) /**< No Fetch Comparison */
-#define _ETM_ETMSCR_NOFETCHCOMP_SHIFT 17 /**< Shift value for ETM_NOFETCHCOMP */
-#define _ETM_ETMSCR_NOFETCHCOMP_MASK 0x20000UL /**< Bit mask for ETM_NOFETCHCOMP */
-#define _ETM_ETMSCR_NOFETCHCOMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
-#define ETM_ETMSCR_NOFETCHCOMP_DEFAULT (_ETM_ETMSCR_NOFETCHCOMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMSCR */
-
-/* Bit fields for ETM ETMTEEVR */
-#define _ETM_ETMTEEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTEEVR */
-#define _ETM_ETMTEEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTEEVR */
-#define _ETM_ETMTEEVR_RESA_SHIFT 0 /**< Shift value for ETM_RESA */
-#define _ETM_ETMTEEVR_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */
-#define _ETM_ETMTEEVR_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */
-#define ETM_ETMTEEVR_RESA_DEFAULT (_ETM_ETMTEEVR_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */
-#define _ETM_ETMTEEVR_RESB_SHIFT 7 /**< Shift value for ETM_RESB */
-#define _ETM_ETMTEEVR_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */
-#define _ETM_ETMTEEVR_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */
-#define ETM_ETMTEEVR_RESB_DEFAULT (_ETM_ETMTEEVR_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */
-#define _ETM_ETMTEEVR_ETMFCNEN_SHIFT 14 /**< Shift value for ETM_ETMFCNEN */
-#define _ETM_ETMTEEVR_ETMFCNEN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEN */
-#define _ETM_ETMTEEVR_ETMFCNEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */
-#define ETM_ETMTEEVR_ETMFCNEN_DEFAULT (_ETM_ETMTEEVR_ETMFCNEN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */
-
-/* Bit fields for ETM ETMTECR1 */
-#define _ETM_ETMTECR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTECR1 */
-#define _ETM_ETMTECR1_MASK 0x03FFFFFFUL /**< Mask for ETM_ETMTECR1 */
-#define _ETM_ETMTECR1_ADRCMP_SHIFT 0 /**< Shift value for ETM_ADRCMP */
-#define _ETM_ETMTECR1_ADRCMP_MASK 0xFFUL /**< Bit mask for ETM_ADRCMP */
-#define _ETM_ETMTECR1_ADRCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
-#define ETM_ETMTECR1_ADRCMP_DEFAULT (_ETM_ETMTECR1_ADRCMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
-#define _ETM_ETMTECR1_MEMMAP_SHIFT 8 /**< Shift value for ETM_MEMMAP */
-#define _ETM_ETMTECR1_MEMMAP_MASK 0xFFFF00UL /**< Bit mask for ETM_MEMMAP */
-#define _ETM_ETMTECR1_MEMMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
-#define ETM_ETMTECR1_MEMMAP_DEFAULT (_ETM_ETMTECR1_MEMMAP_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
-#define ETM_ETMTECR1_INCEXCTL (0x1UL << 24) /**< Trace Include/Exclude Flag */
-#define _ETM_ETMTECR1_INCEXCTL_SHIFT 24 /**< Shift value for ETM_INCEXCTL */
-#define _ETM_ETMTECR1_INCEXCTL_MASK 0x1000000UL /**< Bit mask for ETM_INCEXCTL */
-#define _ETM_ETMTECR1_INCEXCTL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
-#define _ETM_ETMTECR1_INCEXCTL_INC 0x00000000UL /**< Mode INC for ETM_ETMTECR1 */
-#define _ETM_ETMTECR1_INCEXCTL_EXC 0x00000001UL /**< Mode EXC for ETM_ETMTECR1 */
-#define ETM_ETMTECR1_INCEXCTL_DEFAULT (_ETM_ETMTECR1_INCEXCTL_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
-#define ETM_ETMTECR1_INCEXCTL_INC (_ETM_ETMTECR1_INCEXCTL_INC << 24) /**< Shifted mode INC for ETM_ETMTECR1 */
-#define ETM_ETMTECR1_INCEXCTL_EXC (_ETM_ETMTECR1_INCEXCTL_EXC << 24) /**< Shifted mode EXC for ETM_ETMTECR1 */
-#define ETM_ETMTECR1_TCE (0x1UL << 25) /**< Trace Control Enable */
-#define _ETM_ETMTECR1_TCE_SHIFT 25 /**< Shift value for ETM_TCE */
-#define _ETM_ETMTECR1_TCE_MASK 0x2000000UL /**< Bit mask for ETM_TCE */
-#define _ETM_ETMTECR1_TCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
-#define _ETM_ETMTECR1_TCE_EN 0x00000000UL /**< Mode EN for ETM_ETMTECR1 */
-#define _ETM_ETMTECR1_TCE_DIS 0x00000001UL /**< Mode DIS for ETM_ETMTECR1 */
-#define ETM_ETMTECR1_TCE_DEFAULT (_ETM_ETMTECR1_TCE_DEFAULT << 25) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
-#define ETM_ETMTECR1_TCE_EN (_ETM_ETMTECR1_TCE_EN << 25) /**< Shifted mode EN for ETM_ETMTECR1 */
-#define ETM_ETMTECR1_TCE_DIS (_ETM_ETMTECR1_TCE_DIS << 25) /**< Shifted mode DIS for ETM_ETMTECR1 */
-
-/* Bit fields for ETM ETMFFLR */
-#define _ETM_ETMFFLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMFFLR */
-#define _ETM_ETMFFLR_MASK 0x000000FFUL /**< Mask for ETM_ETMFFLR */
-#define _ETM_ETMFFLR_BYTENUM_SHIFT 0 /**< Shift value for ETM_BYTENUM */
-#define _ETM_ETMFFLR_BYTENUM_MASK 0xFFUL /**< Bit mask for ETM_BYTENUM */
-#define _ETM_ETMFFLR_BYTENUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMFFLR */
-#define ETM_ETMFFLR_BYTENUM_DEFAULT (_ETM_ETMFFLR_BYTENUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMFFLR */
-
-/* Bit fields for ETM ETMCNTRLDVR1 */
-#define _ETM_ETMCNTRLDVR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCNTRLDVR1 */
-#define _ETM_ETMCNTRLDVR1_MASK 0x0000FFFFUL /**< Mask for ETM_ETMCNTRLDVR1 */
-#define _ETM_ETMCNTRLDVR1_COUNT_SHIFT 0 /**< Shift value for ETM_COUNT */
-#define _ETM_ETMCNTRLDVR1_COUNT_MASK 0xFFFFUL /**< Bit mask for ETM_COUNT */
-#define _ETM_ETMCNTRLDVR1_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCNTRLDVR1 */
-#define ETM_ETMCNTRLDVR1_COUNT_DEFAULT (_ETM_ETMCNTRLDVR1_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCNTRLDVR1 */
-
-/* Bit fields for ETM ETMSYNCFR */
-#define _ETM_ETMSYNCFR_RESETVALUE 0x00000400UL /**< Default value for ETM_ETMSYNCFR */
-#define _ETM_ETMSYNCFR_MASK 0x00000FFFUL /**< Mask for ETM_ETMSYNCFR */
-#define _ETM_ETMSYNCFR_FREQ_SHIFT 0 /**< Shift value for ETM_FREQ */
-#define _ETM_ETMSYNCFR_FREQ_MASK 0xFFFUL /**< Bit mask for ETM_FREQ */
-#define _ETM_ETMSYNCFR_FREQ_DEFAULT 0x00000400UL /**< Mode DEFAULT for ETM_ETMSYNCFR */
-#define ETM_ETMSYNCFR_FREQ_DEFAULT (_ETM_ETMSYNCFR_FREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSYNCFR */
-
-/* Bit fields for ETM ETMIDR */
-#define _ETM_ETMIDR_RESETVALUE 0x4114F253UL /**< Default value for ETM_ETMIDR */
-#define _ETM_ETMIDR_MASK 0xFF1DFFFFUL /**< Mask for ETM_ETMIDR */
-#define _ETM_ETMIDR_IMPVER_SHIFT 0 /**< Shift value for ETM_IMPVER */
-#define _ETM_ETMIDR_IMPVER_MASK 0xFUL /**< Bit mask for ETM_IMPVER */
-#define _ETM_ETMIDR_IMPVER_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMIDR */
-#define ETM_ETMIDR_IMPVER_DEFAULT (_ETM_ETMIDR_IMPVER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR */
-#define _ETM_ETMIDR_ETMMINVER_SHIFT 4 /**< Shift value for ETM_ETMMINVER */
-#define _ETM_ETMIDR_ETMMINVER_MASK 0xF0UL /**< Bit mask for ETM_ETMMINVER */
-#define _ETM_ETMIDR_ETMMINVER_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMIDR */
-#define ETM_ETMIDR_ETMMINVER_DEFAULT (_ETM_ETMIDR_ETMMINVER_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMIDR */
-#define _ETM_ETMIDR_ETMMAJVER_SHIFT 8 /**< Shift value for ETM_ETMMAJVER */
-#define _ETM_ETMIDR_ETMMAJVER_MASK 0xF00UL /**< Bit mask for ETM_ETMMAJVER */
-#define _ETM_ETMIDR_ETMMAJVER_DEFAULT 0x00000002UL /**< Mode DEFAULT for ETM_ETMIDR */
-#define ETM_ETMIDR_ETMMAJVER_DEFAULT (_ETM_ETMIDR_ETMMAJVER_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMIDR */
-#define _ETM_ETMIDR_PROCFAM_SHIFT 12 /**< Shift value for ETM_PROCFAM */
-#define _ETM_ETMIDR_PROCFAM_MASK 0xF000UL /**< Bit mask for ETM_PROCFAM */
-#define _ETM_ETMIDR_PROCFAM_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMIDR */
-#define ETM_ETMIDR_PROCFAM_DEFAULT (_ETM_ETMIDR_PROCFAM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMIDR */
-#define ETM_ETMIDR_LPCF (0x1UL << 16) /**< Load PC First */
-#define _ETM_ETMIDR_LPCF_SHIFT 16 /**< Shift value for ETM_LPCF */
-#define _ETM_ETMIDR_LPCF_MASK 0x10000UL /**< Bit mask for ETM_LPCF */
-#define _ETM_ETMIDR_LPCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */
-#define ETM_ETMIDR_LPCF_DEFAULT (_ETM_ETMIDR_LPCF_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMIDR */
-#define ETM_ETMIDR_THUMBT (0x1UL << 18) /**< 32-bit Thumb Instruction Tracing */
-#define _ETM_ETMIDR_THUMBT_SHIFT 18 /**< Shift value for ETM_THUMBT */
-#define _ETM_ETMIDR_THUMBT_MASK 0x40000UL /**< Bit mask for ETM_THUMBT */
-#define _ETM_ETMIDR_THUMBT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */
-#define ETM_ETMIDR_THUMBT_DEFAULT (_ETM_ETMIDR_THUMBT_DEFAULT << 18) /**< Shifted mode DEFAULT for ETM_ETMIDR */
-#define ETM_ETMIDR_SECEXT (0x1UL << 19) /**< Security Extension Support */
-#define _ETM_ETMIDR_SECEXT_SHIFT 19 /**< Shift value for ETM_SECEXT */
-#define _ETM_ETMIDR_SECEXT_MASK 0x80000UL /**< Bit mask for ETM_SECEXT */
-#define _ETM_ETMIDR_SECEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */
-#define ETM_ETMIDR_SECEXT_DEFAULT (_ETM_ETMIDR_SECEXT_DEFAULT << 19) /**< Shifted mode DEFAULT for ETM_ETMIDR */
-#define ETM_ETMIDR_BPE (0x1UL << 20) /**< Branch Packet Encoding */
-#define _ETM_ETMIDR_BPE_SHIFT 20 /**< Shift value for ETM_BPE */
-#define _ETM_ETMIDR_BPE_MASK 0x100000UL /**< Bit mask for ETM_BPE */
-#define _ETM_ETMIDR_BPE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */
-#define ETM_ETMIDR_BPE_DEFAULT (_ETM_ETMIDR_BPE_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMIDR */
-#define _ETM_ETMIDR_IMPCODE_SHIFT 24 /**< Shift value for ETM_IMPCODE */
-#define _ETM_ETMIDR_IMPCODE_MASK 0xFF000000UL /**< Bit mask for ETM_IMPCODE */
-#define _ETM_ETMIDR_IMPCODE_DEFAULT 0x00000041UL /**< Mode DEFAULT for ETM_ETMIDR */
-#define ETM_ETMIDR_IMPCODE_DEFAULT (_ETM_ETMIDR_IMPCODE_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMIDR */
-
-/* Bit fields for ETM ETMCCER */
-#define _ETM_ETMCCER_RESETVALUE 0x18541800UL /**< Default value for ETM_ETMCCER */
-#define _ETM_ETMCCER_MASK 0x387FFFFBUL /**< Mask for ETM_ETMCCER */
-#define _ETM_ETMCCER_EXTINPSEL_SHIFT 0 /**< Shift value for ETM_EXTINPSEL */
-#define _ETM_ETMCCER_EXTINPSEL_MASK 0x3UL /**< Bit mask for ETM_EXTINPSEL */
-#define _ETM_ETMCCER_EXTINPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
-#define ETM_ETMCCER_EXTINPSEL_DEFAULT (_ETM_ETMCCER_EXTINPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCER */
-#define _ETM_ETMCCER_EXTINPBUS_SHIFT 3 /**< Shift value for ETM_EXTINPBUS */
-#define _ETM_ETMCCER_EXTINPBUS_MASK 0x7F8UL /**< Bit mask for ETM_EXTINPBUS */
-#define _ETM_ETMCCER_EXTINPBUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
-#define ETM_ETMCCER_EXTINPBUS_DEFAULT (_ETM_ETMCCER_EXTINPBUS_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMCCER */
-#define ETM_ETMCCER_READREGS (0x1UL << 11) /**< Readable Registers */
-#define _ETM_ETMCCER_READREGS_SHIFT 11 /**< Shift value for ETM_READREGS */
-#define _ETM_ETMCCER_READREGS_MASK 0x800UL /**< Bit mask for ETM_READREGS */
-#define _ETM_ETMCCER_READREGS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
-#define ETM_ETMCCER_READREGS_DEFAULT (_ETM_ETMCCER_READREGS_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCCER */
-#define ETM_ETMCCER_DADDRCMP (0x1UL << 12) /**< Data Address comparisons */
-#define _ETM_ETMCCER_DADDRCMP_SHIFT 12 /**< Shift value for ETM_DADDRCMP */
-#define _ETM_ETMCCER_DADDRCMP_MASK 0x1000UL /**< Bit mask for ETM_DADDRCMP */
-#define _ETM_ETMCCER_DADDRCMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
-#define ETM_ETMCCER_DADDRCMP_DEFAULT (_ETM_ETMCCER_DADDRCMP_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMCCER */
-#define _ETM_ETMCCER_INSTRES_SHIFT 13 /**< Shift value for ETM_INSTRES */
-#define _ETM_ETMCCER_INSTRES_MASK 0xE000UL /**< Bit mask for ETM_INSTRES */
-#define _ETM_ETMCCER_INSTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
-#define ETM_ETMCCER_INSTRES_DEFAULT (_ETM_ETMCCER_INSTRES_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCER */
-#define _ETM_ETMCCER_EICEWPNT_SHIFT 16 /**< Shift value for ETM_EICEWPNT */
-#define _ETM_ETMCCER_EICEWPNT_MASK 0xF0000UL /**< Bit mask for ETM_EICEWPNT */
-#define _ETM_ETMCCER_EICEWPNT_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMCCER */
-#define ETM_ETMCCER_EICEWPNT_DEFAULT (_ETM_ETMCCER_EICEWPNT_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCER */
-#define ETM_ETMCCER_TEICEWPNT (0x1UL << 20) /**< Trace Sart/Stop Block Uses EmbeddedICE watchpoint inputs */
-#define _ETM_ETMCCER_TEICEWPNT_SHIFT 20 /**< Shift value for ETM_TEICEWPNT */
-#define _ETM_ETMCCER_TEICEWPNT_MASK 0x100000UL /**< Bit mask for ETM_TEICEWPNT */
-#define _ETM_ETMCCER_TEICEWPNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
-#define ETM_ETMCCER_TEICEWPNT_DEFAULT (_ETM_ETMCCER_TEICEWPNT_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCER */
-#define ETM_ETMCCER_EICEIMP (0x1UL << 21) /**< EmbeddedICE Behavior control Implemented */
-#define _ETM_ETMCCER_EICEIMP_SHIFT 21 /**< Shift value for ETM_EICEIMP */
-#define _ETM_ETMCCER_EICEIMP_MASK 0x200000UL /**< Bit mask for ETM_EICEIMP */
-#define _ETM_ETMCCER_EICEIMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
-#define ETM_ETMCCER_EICEIMP_DEFAULT (_ETM_ETMCCER_EICEIMP_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCCER */
-#define ETM_ETMCCER_TIMP (0x1UL << 22) /**< Timestamping Implemented */
-#define _ETM_ETMCCER_TIMP_SHIFT 22 /**< Shift value for ETM_TIMP */
-#define _ETM_ETMCCER_TIMP_MASK 0x400000UL /**< Bit mask for ETM_TIMP */
-#define _ETM_ETMCCER_TIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
-#define ETM_ETMCCER_TIMP_DEFAULT (_ETM_ETMCCER_TIMP_DEFAULT << 22) /**< Shifted mode DEFAULT for ETM_ETMCCER */
-#define ETM_ETMCCER_RFCNT (0x1UL << 27) /**< Reduced Function Counter */
-#define _ETM_ETMCCER_RFCNT_SHIFT 27 /**< Shift value for ETM_RFCNT */
-#define _ETM_ETMCCER_RFCNT_MASK 0x8000000UL /**< Bit mask for ETM_RFCNT */
-#define _ETM_ETMCCER_RFCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
-#define ETM_ETMCCER_RFCNT_DEFAULT (_ETM_ETMCCER_RFCNT_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCER */
-#define ETM_ETMCCER_TENC (0x1UL << 28) /**< Timestamp Encoding */
-#define _ETM_ETMCCER_TENC_SHIFT 28 /**< Shift value for ETM_TENC */
-#define _ETM_ETMCCER_TENC_MASK 0x10000000UL /**< Bit mask for ETM_TENC */
-#define _ETM_ETMCCER_TENC_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
-#define ETM_ETMCCER_TENC_DEFAULT (_ETM_ETMCCER_TENC_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCCER */
-#define ETM_ETMCCER_TSIZE (0x1UL << 29) /**< Timestamp Size */
-#define _ETM_ETMCCER_TSIZE_SHIFT 29 /**< Shift value for ETM_TSIZE */
-#define _ETM_ETMCCER_TSIZE_MASK 0x20000000UL /**< Bit mask for ETM_TSIZE */
-#define _ETM_ETMCCER_TSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
-#define ETM_ETMCCER_TSIZE_DEFAULT (_ETM_ETMCCER_TSIZE_DEFAULT << 29) /**< Shifted mode DEFAULT for ETM_ETMCCER */
-
-/* Bit fields for ETM ETMTESSEICR */
-#define _ETM_ETMTESSEICR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTESSEICR */
-#define _ETM_ETMTESSEICR_MASK 0x000F000FUL /**< Mask for ETM_ETMTESSEICR */
-#define _ETM_ETMTESSEICR_STARTRSEL_SHIFT 0 /**< Shift value for ETM_STARTRSEL */
-#define _ETM_ETMTESSEICR_STARTRSEL_MASK 0xFUL /**< Bit mask for ETM_STARTRSEL */
-#define _ETM_ETMTESSEICR_STARTRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */
-#define ETM_ETMTESSEICR_STARTRSEL_DEFAULT (_ETM_ETMTESSEICR_STARTRSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */
-#define _ETM_ETMTESSEICR_STOPRSEL_SHIFT 16 /**< Shift value for ETM_STOPRSEL */
-#define _ETM_ETMTESSEICR_STOPRSEL_MASK 0xF0000UL /**< Bit mask for ETM_STOPRSEL */
-#define _ETM_ETMTESSEICR_STOPRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */
-#define ETM_ETMTESSEICR_STOPRSEL_DEFAULT (_ETM_ETMTESSEICR_STOPRSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */
-
-/* Bit fields for ETM ETMTSEVR */
-#define _ETM_ETMTSEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTSEVR */
-#define _ETM_ETMTSEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTSEVR */
-#define _ETM_ETMTSEVR_RESAEVT_SHIFT 0 /**< Shift value for ETM_RESAEVT */
-#define _ETM_ETMTSEVR_RESAEVT_MASK 0x7FUL /**< Bit mask for ETM_RESAEVT */
-#define _ETM_ETMTSEVR_RESAEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */
-#define ETM_ETMTSEVR_RESAEVT_DEFAULT (_ETM_ETMTSEVR_RESAEVT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */
-#define _ETM_ETMTSEVR_RESBEVT_SHIFT 7 /**< Shift value for ETM_RESBEVT */
-#define _ETM_ETMTSEVR_RESBEVT_MASK 0x3F80UL /**< Bit mask for ETM_RESBEVT */
-#define _ETM_ETMTSEVR_RESBEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */
-#define ETM_ETMTSEVR_RESBEVT_DEFAULT (_ETM_ETMTSEVR_RESBEVT_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */
-#define _ETM_ETMTSEVR_ETMFCNEVT_SHIFT 14 /**< Shift value for ETM_ETMFCNEVT */
-#define _ETM_ETMTSEVR_ETMFCNEVT_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEVT */
-#define _ETM_ETMTSEVR_ETMFCNEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */
-#define ETM_ETMTSEVR_ETMFCNEVT_DEFAULT (_ETM_ETMTSEVR_ETMFCNEVT_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */
-
-/* Bit fields for ETM ETMTRACEIDR */
-#define _ETM_ETMTRACEIDR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRACEIDR */
-#define _ETM_ETMTRACEIDR_MASK 0x0000007FUL /**< Mask for ETM_ETMTRACEIDR */
-#define _ETM_ETMTRACEIDR_TRACEID_SHIFT 0 /**< Shift value for ETM_TRACEID */
-#define _ETM_ETMTRACEIDR_TRACEID_MASK 0x7FUL /**< Bit mask for ETM_TRACEID */
-#define _ETM_ETMTRACEIDR_TRACEID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRACEIDR */
-#define ETM_ETMTRACEIDR_TRACEID_DEFAULT (_ETM_ETMTRACEIDR_TRACEID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRACEIDR */
-
-/* Bit fields for ETM ETMIDR2 */
-#define _ETM_ETMIDR2_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMIDR2 */
-#define _ETM_ETMIDR2_MASK 0x00000003UL /**< Mask for ETM_ETMIDR2 */
-#define ETM_ETMIDR2_RFE (0x1UL << 0) /**< RFE Transfer Order */
-#define _ETM_ETMIDR2_RFE_SHIFT 0 /**< Shift value for ETM_RFE */
-#define _ETM_ETMIDR2_RFE_MASK 0x1UL /**< Bit mask for ETM_RFE */
-#define _ETM_ETMIDR2_RFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */
-#define _ETM_ETMIDR2_RFE_PC 0x00000000UL /**< Mode PC for ETM_ETMIDR2 */
-#define _ETM_ETMIDR2_RFE_CPSR 0x00000001UL /**< Mode CPSR for ETM_ETMIDR2 */
-#define ETM_ETMIDR2_RFE_DEFAULT (_ETM_ETMIDR2_RFE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */
-#define ETM_ETMIDR2_RFE_PC (_ETM_ETMIDR2_RFE_PC << 0) /**< Shifted mode PC for ETM_ETMIDR2 */
-#define ETM_ETMIDR2_RFE_CPSR (_ETM_ETMIDR2_RFE_CPSR << 0) /**< Shifted mode CPSR for ETM_ETMIDR2 */
-#define ETM_ETMIDR2_SWP (0x1UL << 1) /**< SWP Transfer Order */
-#define _ETM_ETMIDR2_SWP_SHIFT 1 /**< Shift value for ETM_SWP */
-#define _ETM_ETMIDR2_SWP_MASK 0x2UL /**< Bit mask for ETM_SWP */
-#define _ETM_ETMIDR2_SWP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */
-#define _ETM_ETMIDR2_SWP_LOAD 0x00000000UL /**< Mode LOAD for ETM_ETMIDR2 */
-#define _ETM_ETMIDR2_SWP_STORE 0x00000001UL /**< Mode STORE for ETM_ETMIDR2 */
-#define ETM_ETMIDR2_SWP_DEFAULT (_ETM_ETMIDR2_SWP_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */
-#define ETM_ETMIDR2_SWP_LOAD (_ETM_ETMIDR2_SWP_LOAD << 1) /**< Shifted mode LOAD for ETM_ETMIDR2 */
-#define ETM_ETMIDR2_SWP_STORE (_ETM_ETMIDR2_SWP_STORE << 1) /**< Shifted mode STORE for ETM_ETMIDR2 */
-
-/* Bit fields for ETM ETMPDSR */
-#define _ETM_ETMPDSR_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMPDSR */
-#define _ETM_ETMPDSR_MASK 0x00000001UL /**< Mask for ETM_ETMPDSR */
-#define ETM_ETMPDSR_ETMUP (0x1UL << 0) /**< ETM Powered Up */
-#define _ETM_ETMPDSR_ETMUP_SHIFT 0 /**< Shift value for ETM_ETMUP */
-#define _ETM_ETMPDSR_ETMUP_MASK 0x1UL /**< Bit mask for ETM_ETMUP */
-#define _ETM_ETMPDSR_ETMUP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPDSR */
-#define ETM_ETMPDSR_ETMUP_DEFAULT (_ETM_ETMPDSR_ETMUP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPDSR */
-
-/* Bit fields for ETM ETMISCIN */
-#define _ETM_ETMISCIN_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMISCIN */
-#define _ETM_ETMISCIN_MASK 0x00000013UL /**< Mask for ETM_ETMISCIN */
-#define _ETM_ETMISCIN_EXTIN_SHIFT 0 /**< Shift value for ETM_EXTIN */
-#define _ETM_ETMISCIN_EXTIN_MASK 0x3UL /**< Bit mask for ETM_EXTIN */
-#define _ETM_ETMISCIN_EXTIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */
-#define ETM_ETMISCIN_EXTIN_DEFAULT (_ETM_ETMISCIN_EXTIN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMISCIN */
-#define ETM_ETMISCIN_COREHALT (0x1UL << 4) /**< Core Halt */
-#define _ETM_ETMISCIN_COREHALT_SHIFT 4 /**< Shift value for ETM_COREHALT */
-#define _ETM_ETMISCIN_COREHALT_MASK 0x10UL /**< Bit mask for ETM_COREHALT */
-#define _ETM_ETMISCIN_COREHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */
-#define ETM_ETMISCIN_COREHALT_DEFAULT (_ETM_ETMISCIN_COREHALT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMISCIN */
-
-/* Bit fields for ETM ITTRIGOUT */
-#define _ETM_ITTRIGOUT_RESETVALUE 0x00000000UL /**< Default value for ETM_ITTRIGOUT */
-#define _ETM_ITTRIGOUT_MASK 0x00000001UL /**< Mask for ETM_ITTRIGOUT */
-#define ETM_ITTRIGOUT_TRIGGEROUT (0x1UL << 0) /**< Trigger output value */
-#define _ETM_ITTRIGOUT_TRIGGEROUT_SHIFT 0 /**< Shift value for ETM_TRIGGEROUT */
-#define _ETM_ITTRIGOUT_TRIGGEROUT_MASK 0x1UL /**< Bit mask for ETM_TRIGGEROUT */
-#define _ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ITTRIGOUT */
-#define ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT (_ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ITTRIGOUT */
-
-/* Bit fields for ETM ETMITATBCTR2 */
-#define _ETM_ETMITATBCTR2_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMITATBCTR2 */
-#define _ETM_ETMITATBCTR2_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR2 */
-#define ETM_ETMITATBCTR2_ATREADY (0x1UL << 0) /**< ATREADY Input Value */
-#define _ETM_ETMITATBCTR2_ATREADY_SHIFT 0 /**< Shift value for ETM_ATREADY */
-#define _ETM_ETMITATBCTR2_ATREADY_MASK 0x1UL /**< Bit mask for ETM_ATREADY */
-#define _ETM_ETMITATBCTR2_ATREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMITATBCTR2 */
-#define ETM_ETMITATBCTR2_ATREADY_DEFAULT (_ETM_ETMITATBCTR2_ATREADY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR2 */
-
-/* Bit fields for ETM ETMITATBCTR0 */
-#define _ETM_ETMITATBCTR0_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITATBCTR0 */
-#define _ETM_ETMITATBCTR0_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR0 */
-#define ETM_ETMITATBCTR0_ATVALID (0x1UL << 0) /**< ATVALID Output Value */
-#define _ETM_ETMITATBCTR0_ATVALID_SHIFT 0 /**< Shift value for ETM_ATVALID */
-#define _ETM_ETMITATBCTR0_ATVALID_MASK 0x1UL /**< Bit mask for ETM_ATVALID */
-#define _ETM_ETMITATBCTR0_ATVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITATBCTR0 */
-#define ETM_ETMITATBCTR0_ATVALID_DEFAULT (_ETM_ETMITATBCTR0_ATVALID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR0 */
-
-/* Bit fields for ETM ETMITCTRL */
-#define _ETM_ETMITCTRL_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITCTRL */
-#define _ETM_ETMITCTRL_MASK 0x00000001UL /**< Mask for ETM_ETMITCTRL */
-#define ETM_ETMITCTRL_ITEN (0x1UL << 0) /**< Integration Mode Enable */
-#define _ETM_ETMITCTRL_ITEN_SHIFT 0 /**< Shift value for ETM_ITEN */
-#define _ETM_ETMITCTRL_ITEN_MASK 0x1UL /**< Bit mask for ETM_ITEN */
-#define _ETM_ETMITCTRL_ITEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITCTRL */
-#define ETM_ETMITCTRL_ITEN_DEFAULT (_ETM_ETMITCTRL_ITEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITCTRL */
-
-/* Bit fields for ETM ETMCLAIMSET */
-#define _ETM_ETMCLAIMSET_RESETVALUE 0x0000000FUL /**< Default value for ETM_ETMCLAIMSET */
-#define _ETM_ETMCLAIMSET_MASK 0x000000FFUL /**< Mask for ETM_ETMCLAIMSET */
-#define _ETM_ETMCLAIMSET_SETTAG_SHIFT 0 /**< Shift value for ETM_SETTAG */
-#define _ETM_ETMCLAIMSET_SETTAG_MASK 0xFFUL /**< Bit mask for ETM_SETTAG */
-#define _ETM_ETMCLAIMSET_SETTAG_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMCLAIMSET */
-#define ETM_ETMCLAIMSET_SETTAG_DEFAULT (_ETM_ETMCLAIMSET_SETTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMSET */
-
-/* Bit fields for ETM ETMCLAIMCLR */
-#define _ETM_ETMCLAIMCLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCLAIMCLR */
-#define _ETM_ETMCLAIMCLR_MASK 0x00000001UL /**< Mask for ETM_ETMCLAIMCLR */
-#define ETM_ETMCLAIMCLR_CLRTAG (0x1UL << 0) /**< Tag Bits */
-#define _ETM_ETMCLAIMCLR_CLRTAG_SHIFT 0 /**< Shift value for ETM_CLRTAG */
-#define _ETM_ETMCLAIMCLR_CLRTAG_MASK 0x1UL /**< Bit mask for ETM_CLRTAG */
-#define _ETM_ETMCLAIMCLR_CLRTAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCLAIMCLR */
-#define ETM_ETMCLAIMCLR_CLRTAG_DEFAULT (_ETM_ETMCLAIMCLR_CLRTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMCLR */
-
-/* Bit fields for ETM ETMLAR */
-#define _ETM_ETMLAR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMLAR */
-#define _ETM_ETMLAR_MASK 0x00000001UL /**< Mask for ETM_ETMLAR */
-#define ETM_ETMLAR_KEY (0x1UL << 0) /**< Key Value */
-#define _ETM_ETMLAR_KEY_SHIFT 0 /**< Shift value for ETM_KEY */
-#define _ETM_ETMLAR_KEY_MASK 0x1UL /**< Bit mask for ETM_KEY */
-#define _ETM_ETMLAR_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMLAR */
-#define ETM_ETMLAR_KEY_DEFAULT (_ETM_ETMLAR_KEY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLAR */
-
-/* Bit fields for ETM ETMLSR */
-#define _ETM_ETMLSR_RESETVALUE 0x00000003UL /**< Default value for ETM_ETMLSR */
-#define _ETM_ETMLSR_MASK 0x00000003UL /**< Mask for ETM_ETMLSR */
-#define ETM_ETMLSR_LOCKIMP (0x1UL << 0) /**< ETM Locking Implemented */
-#define _ETM_ETMLSR_LOCKIMP_SHIFT 0 /**< Shift value for ETM_LOCKIMP */
-#define _ETM_ETMLSR_LOCKIMP_MASK 0x1UL /**< Bit mask for ETM_LOCKIMP */
-#define _ETM_ETMLSR_LOCKIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */
-#define ETM_ETMLSR_LOCKIMP_DEFAULT (_ETM_ETMLSR_LOCKIMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLSR */
-#define ETM_ETMLSR_LOCKED (0x1UL << 1) /**< ETM locked */
-#define _ETM_ETMLSR_LOCKED_SHIFT 1 /**< Shift value for ETM_LOCKED */
-#define _ETM_ETMLSR_LOCKED_MASK 0x2UL /**< Bit mask for ETM_LOCKED */
-#define _ETM_ETMLSR_LOCKED_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */
-#define ETM_ETMLSR_LOCKED_DEFAULT (_ETM_ETMLSR_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMLSR */
-
-/* Bit fields for ETM ETMAUTHSTATUS */
-#define _ETM_ETMAUTHSTATUS_RESETVALUE 0x000000C0UL /**< Default value for ETM_ETMAUTHSTATUS */
-#define _ETM_ETMAUTHSTATUS_MASK 0x000000FFUL /**< Mask for ETM_ETMAUTHSTATUS */
-#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_SHIFT 0 /**< Shift value for ETM_NONSECINVDBG */
-#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_MASK 0x3UL /**< Bit mask for ETM_NONSECINVDBG */
-#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
-#define ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
-#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_SHIFT 2 /**< Shift value for ETM_NONSECNONINVDBG */
-#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_MASK 0xCUL /**< Bit mask for ETM_NONSECNONINVDBG */
-#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
-#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE 0x00000002UL /**< Mode DISABLE for ETM_ETMAUTHSTATUS */
-#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE 0x00000003UL /**< Mode ENABLE for ETM_ETMAUTHSTATUS */
-#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
-#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE << 2) /**< Shifted mode DISABLE for ETM_ETMAUTHSTATUS */
-#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE << 2) /**< Shifted mode ENABLE for ETM_ETMAUTHSTATUS */
-#define _ETM_ETMAUTHSTATUS_SECINVDBG_SHIFT 4 /**< Shift value for ETM_SECINVDBG */
-#define _ETM_ETMAUTHSTATUS_SECINVDBG_MASK 0x30UL /**< Bit mask for ETM_SECINVDBG */
-#define _ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
-#define ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
-#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_SHIFT 6 /**< Shift value for ETM_SECNONINVDBG */
-#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_MASK 0xC0UL /**< Bit mask for ETM_SECNONINVDBG */
-#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
-#define ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT << 6) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
-
-/* Bit fields for ETM ETMDEVTYPE */
-#define _ETM_ETMDEVTYPE_RESETVALUE 0x00000013UL /**< Default value for ETM_ETMDEVTYPE */
-#define _ETM_ETMDEVTYPE_MASK 0x000000FFUL /**< Mask for ETM_ETMDEVTYPE */
-#define _ETM_ETMDEVTYPE_TRACESRC_SHIFT 0 /**< Shift value for ETM_TRACESRC */
-#define _ETM_ETMDEVTYPE_TRACESRC_MASK 0xFUL /**< Bit mask for ETM_TRACESRC */
-#define _ETM_ETMDEVTYPE_TRACESRC_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */
-#define ETM_ETMDEVTYPE_TRACESRC_DEFAULT (_ETM_ETMDEVTYPE_TRACESRC_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */
-#define _ETM_ETMDEVTYPE_PROCTRACE_SHIFT 4 /**< Shift value for ETM_PROCTRACE */
-#define _ETM_ETMDEVTYPE_PROCTRACE_MASK 0xF0UL /**< Bit mask for ETM_PROCTRACE */
-#define _ETM_ETMDEVTYPE_PROCTRACE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */
-#define ETM_ETMDEVTYPE_PROCTRACE_DEFAULT (_ETM_ETMDEVTYPE_PROCTRACE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */
-
-/* Bit fields for ETM ETMPIDR4 */
-#define _ETM_ETMPIDR4_RESETVALUE 0x00000004UL /**< Default value for ETM_ETMPIDR4 */
-#define _ETM_ETMPIDR4_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR4 */
-#define _ETM_ETMPIDR4_CONTCODE_SHIFT 0 /**< Shift value for ETM_CONTCODE */
-#define _ETM_ETMPIDR4_CONTCODE_MASK 0xFUL /**< Bit mask for ETM_CONTCODE */
-#define _ETM_ETMPIDR4_CONTCODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMPIDR4 */
-#define ETM_ETMPIDR4_CONTCODE_DEFAULT (_ETM_ETMPIDR4_CONTCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */
-#define _ETM_ETMPIDR4_COUNT_SHIFT 4 /**< Shift value for ETM_COUNT */
-#define _ETM_ETMPIDR4_COUNT_MASK 0xF0UL /**< Bit mask for ETM_COUNT */
-#define _ETM_ETMPIDR4_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR4 */
-#define ETM_ETMPIDR4_COUNT_DEFAULT (_ETM_ETMPIDR4_COUNT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */
-
-/* Bit fields for ETM ETMPIDR5 */
-#define _ETM_ETMPIDR5_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR5 */
-#define _ETM_ETMPIDR5_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR5 */
-
-/* Bit fields for ETM ETMPIDR6 */
-#define _ETM_ETMPIDR6_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR6 */
-#define _ETM_ETMPIDR6_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR6 */
-
-/* Bit fields for ETM ETMPIDR7 */
-#define _ETM_ETMPIDR7_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR7 */
-#define _ETM_ETMPIDR7_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR7 */
-
-/* Bit fields for ETM ETMPIDR0 */
-#define _ETM_ETMPIDR0_RESETVALUE 0x00000025UL /**< Default value for ETM_ETMPIDR0 */
-#define _ETM_ETMPIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR0 */
-#define _ETM_ETMPIDR0_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */
-#define _ETM_ETMPIDR0_PARTNUM_MASK 0xFFUL /**< Bit mask for ETM_PARTNUM */
-#define _ETM_ETMPIDR0_PARTNUM_DEFAULT 0x00000025UL /**< Mode DEFAULT for ETM_ETMPIDR0 */
-#define ETM_ETMPIDR0_PARTNUM_DEFAULT (_ETM_ETMPIDR0_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR0 */
-
-/* Bit fields for ETM ETMPIDR1 */
-#define _ETM_ETMPIDR1_RESETVALUE 0x000000B9UL /**< Default value for ETM_ETMPIDR1 */
-#define _ETM_ETMPIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR1 */
-#define _ETM_ETMPIDR1_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */
-#define _ETM_ETMPIDR1_PARTNUM_MASK 0xFUL /**< Bit mask for ETM_PARTNUM */
-#define _ETM_ETMPIDR1_PARTNUM_DEFAULT 0x00000009UL /**< Mode DEFAULT for ETM_ETMPIDR1 */
-#define ETM_ETMPIDR1_PARTNUM_DEFAULT (_ETM_ETMPIDR1_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */
-#define _ETM_ETMPIDR1_IDCODE_SHIFT 4 /**< Shift value for ETM_IDCODE */
-#define _ETM_ETMPIDR1_IDCODE_MASK 0xF0UL /**< Bit mask for ETM_IDCODE */
-#define _ETM_ETMPIDR1_IDCODE_DEFAULT 0x0000000BUL /**< Mode DEFAULT for ETM_ETMPIDR1 */
-#define ETM_ETMPIDR1_IDCODE_DEFAULT (_ETM_ETMPIDR1_IDCODE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */
-
-/* Bit fields for ETM ETMPIDR2 */
-#define _ETM_ETMPIDR2_RESETVALUE 0x0000000BUL /**< Default value for ETM_ETMPIDR2 */
-#define _ETM_ETMPIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR2 */
-#define _ETM_ETMPIDR2_IDCODE_SHIFT 0 /**< Shift value for ETM_IDCODE */
-#define _ETM_ETMPIDR2_IDCODE_MASK 0x7UL /**< Bit mask for ETM_IDCODE */
-#define _ETM_ETMPIDR2_IDCODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMPIDR2 */
-#define ETM_ETMPIDR2_IDCODE_DEFAULT (_ETM_ETMPIDR2_IDCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */
-#define ETM_ETMPIDR2_ALWAYS1 (0x1UL << 3) /**< Always 1 */
-#define _ETM_ETMPIDR2_ALWAYS1_SHIFT 3 /**< Shift value for ETM_ALWAYS1 */
-#define _ETM_ETMPIDR2_ALWAYS1_MASK 0x8UL /**< Bit mask for ETM_ALWAYS1 */
-#define _ETM_ETMPIDR2_ALWAYS1_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPIDR2 */
-#define ETM_ETMPIDR2_ALWAYS1_DEFAULT (_ETM_ETMPIDR2_ALWAYS1_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */
-#define _ETM_ETMPIDR2_REV_SHIFT 4 /**< Shift value for ETM_REV */
-#define _ETM_ETMPIDR2_REV_MASK 0xF0UL /**< Bit mask for ETM_REV */
-#define _ETM_ETMPIDR2_REV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR2 */
-#define ETM_ETMPIDR2_REV_DEFAULT (_ETM_ETMPIDR2_REV_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */
-
-/* Bit fields for ETM ETMPIDR3 */
-#define _ETM_ETMPIDR3_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR3 */
-#define _ETM_ETMPIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR3 */
-#define _ETM_ETMPIDR3_CUSTMOD_SHIFT 0 /**< Shift value for ETM_CUSTMOD */
-#define _ETM_ETMPIDR3_CUSTMOD_MASK 0xFUL /**< Bit mask for ETM_CUSTMOD */
-#define _ETM_ETMPIDR3_CUSTMOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */
-#define ETM_ETMPIDR3_CUSTMOD_DEFAULT (_ETM_ETMPIDR3_CUSTMOD_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */
-#define _ETM_ETMPIDR3_REVAND_SHIFT 4 /**< Shift value for ETM_REVAND */
-#define _ETM_ETMPIDR3_REVAND_MASK 0xF0UL /**< Bit mask for ETM_REVAND */
-#define _ETM_ETMPIDR3_REVAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */
-#define ETM_ETMPIDR3_REVAND_DEFAULT (_ETM_ETMPIDR3_REVAND_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */
-
-/* Bit fields for ETM ETMCIDR0 */
-#define _ETM_ETMCIDR0_RESETVALUE 0x0000000DUL /**< Default value for ETM_ETMCIDR0 */
-#define _ETM_ETMCIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR0 */
-#define _ETM_ETMCIDR0_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
-#define _ETM_ETMCIDR0_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
-#define _ETM_ETMCIDR0_PREAMB_DEFAULT 0x0000000DUL /**< Mode DEFAULT for ETM_ETMCIDR0 */
-#define ETM_ETMCIDR0_PREAMB_DEFAULT (_ETM_ETMCIDR0_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR0 */
-
-/* Bit fields for ETM ETMCIDR1 */
-#define _ETM_ETMCIDR1_RESETVALUE 0x00000090UL /**< Default value for ETM_ETMCIDR1 */
-#define _ETM_ETMCIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR1 */
-#define _ETM_ETMCIDR1_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
-#define _ETM_ETMCIDR1_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
-#define _ETM_ETMCIDR1_PREAMB_DEFAULT 0x00000090UL /**< Mode DEFAULT for ETM_ETMCIDR1 */
-#define ETM_ETMCIDR1_PREAMB_DEFAULT (_ETM_ETMCIDR1_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR1 */
-
-/* Bit fields for ETM ETMCIDR2 */
-#define _ETM_ETMCIDR2_RESETVALUE 0x00000005UL /**< Default value for ETM_ETMCIDR2 */
-#define _ETM_ETMCIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR2 */
-#define _ETM_ETMCIDR2_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
-#define _ETM_ETMCIDR2_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
-#define _ETM_ETMCIDR2_PREAMB_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMCIDR2 */
-#define ETM_ETMCIDR2_PREAMB_DEFAULT (_ETM_ETMCIDR2_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR2 */
-
-/* Bit fields for ETM ETMCIDR3 */
-#define _ETM_ETMCIDR3_RESETVALUE 0x000000B1UL /**< Default value for ETM_ETMCIDR3 */
-#define _ETM_ETMCIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR3 */
-#define _ETM_ETMCIDR3_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
-#define _ETM_ETMCIDR3_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
-#define _ETM_ETMCIDR3_PREAMB_DEFAULT 0x000000B1UL /**< Mode DEFAULT for ETM_ETMCIDR3 */
-#define ETM_ETMCIDR3_PREAMB_DEFAULT (_ETM_ETMCIDR3_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR3 */
-
-/** @} */
-/** @} End of group EFR32FG13P_ETM */
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_fpueh.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_fpueh.h
deleted file mode 100644
index 2c0ce4f2..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_fpueh.h
+++ /dev/null
@@ -1,201 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_fpueh.h
- * @brief EFR32FG13P_FPUEH register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P_FPUEH FPUEH
- * @{
- * @brief EFR32FG13P_FPUEH Register Declaration
- *****************************************************************************/
-/** FPUEH Register Declaration */
-typedef struct {
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
-} FPUEH_TypeDef; /** @} */
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_FPUEH
- * @{
- * @defgroup EFR32FG13P_FPUEH_BitFields FPUEH Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for FPUEH IF */
-#define _FPUEH_IF_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IF */
-#define _FPUEH_IF_MASK 0x0000003FUL /**< Mask for FPUEH_IF */
-#define FPUEH_IF_FPIOC (0x1UL << 0) /**< FPU invalid operation */
-#define _FPUEH_IF_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
-#define _FPUEH_IF_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
-#define _FPUEH_IF_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
-#define FPUEH_IF_FPIOC_DEFAULT (_FPUEH_IF_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IF */
-#define FPUEH_IF_FPDZC (0x1UL << 1) /**< FPU divide-by-zero exception */
-#define _FPUEH_IF_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
-#define _FPUEH_IF_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
-#define _FPUEH_IF_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
-#define FPUEH_IF_FPDZC_DEFAULT (_FPUEH_IF_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IF */
-#define FPUEH_IF_FPUFC (0x1UL << 2) /**< FPU underflow exception */
-#define _FPUEH_IF_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
-#define _FPUEH_IF_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
-#define _FPUEH_IF_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
-#define FPUEH_IF_FPUFC_DEFAULT (_FPUEH_IF_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IF */
-#define FPUEH_IF_FPOFC (0x1UL << 3) /**< FPU overflow exception */
-#define _FPUEH_IF_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
-#define _FPUEH_IF_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
-#define _FPUEH_IF_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
-#define FPUEH_IF_FPOFC_DEFAULT (_FPUEH_IF_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IF */
-#define FPUEH_IF_FPIDC (0x1UL << 4) /**< FPU input denormal exception */
-#define _FPUEH_IF_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
-#define _FPUEH_IF_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
-#define _FPUEH_IF_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
-#define FPUEH_IF_FPIDC_DEFAULT (_FPUEH_IF_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IF */
-#define FPUEH_IF_FPIXC (0x1UL << 5) /**< FPU inexact exception */
-#define _FPUEH_IF_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
-#define _FPUEH_IF_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
-#define _FPUEH_IF_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
-#define FPUEH_IF_FPIXC_DEFAULT (_FPUEH_IF_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IF */
-
-/* Bit fields for FPUEH IFS */
-#define _FPUEH_IFS_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFS */
-#define _FPUEH_IFS_MASK 0x0000003FUL /**< Mask for FPUEH_IFS */
-#define FPUEH_IFS_FPIOC (0x1UL << 0) /**< Set FPIOC Interrupt Flag */
-#define _FPUEH_IFS_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
-#define _FPUEH_IFS_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
-#define _FPUEH_IFS_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
-#define FPUEH_IFS_FPIOC_DEFAULT (_FPUEH_IFS_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFS */
-#define FPUEH_IFS_FPDZC (0x1UL << 1) /**< Set FPDZC Interrupt Flag */
-#define _FPUEH_IFS_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
-#define _FPUEH_IFS_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
-#define _FPUEH_IFS_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
-#define FPUEH_IFS_FPDZC_DEFAULT (_FPUEH_IFS_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFS */
-#define FPUEH_IFS_FPUFC (0x1UL << 2) /**< Set FPUFC Interrupt Flag */
-#define _FPUEH_IFS_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
-#define _FPUEH_IFS_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
-#define _FPUEH_IFS_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
-#define FPUEH_IFS_FPUFC_DEFAULT (_FPUEH_IFS_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFS */
-#define FPUEH_IFS_FPOFC (0x1UL << 3) /**< Set FPOFC Interrupt Flag */
-#define _FPUEH_IFS_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
-#define _FPUEH_IFS_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
-#define _FPUEH_IFS_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
-#define FPUEH_IFS_FPOFC_DEFAULT (_FPUEH_IFS_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFS */
-#define FPUEH_IFS_FPIDC (0x1UL << 4) /**< Set FPIDC Interrupt Flag */
-#define _FPUEH_IFS_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
-#define _FPUEH_IFS_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
-#define _FPUEH_IFS_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
-#define FPUEH_IFS_FPIDC_DEFAULT (_FPUEH_IFS_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFS */
-#define FPUEH_IFS_FPIXC (0x1UL << 5) /**< Set FPIXC Interrupt Flag */
-#define _FPUEH_IFS_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
-#define _FPUEH_IFS_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
-#define _FPUEH_IFS_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
-#define FPUEH_IFS_FPIXC_DEFAULT (_FPUEH_IFS_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFS */
-
-/* Bit fields for FPUEH IFC */
-#define _FPUEH_IFC_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFC */
-#define _FPUEH_IFC_MASK 0x0000003FUL /**< Mask for FPUEH_IFC */
-#define FPUEH_IFC_FPIOC (0x1UL << 0) /**< Clear FPIOC Interrupt Flag */
-#define _FPUEH_IFC_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
-#define _FPUEH_IFC_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
-#define _FPUEH_IFC_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
-#define FPUEH_IFC_FPIOC_DEFAULT (_FPUEH_IFC_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFC */
-#define FPUEH_IFC_FPDZC (0x1UL << 1) /**< Clear FPDZC Interrupt Flag */
-#define _FPUEH_IFC_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
-#define _FPUEH_IFC_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
-#define _FPUEH_IFC_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
-#define FPUEH_IFC_FPDZC_DEFAULT (_FPUEH_IFC_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFC */
-#define FPUEH_IFC_FPUFC (0x1UL << 2) /**< Clear FPUFC Interrupt Flag */
-#define _FPUEH_IFC_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
-#define _FPUEH_IFC_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
-#define _FPUEH_IFC_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
-#define FPUEH_IFC_FPUFC_DEFAULT (_FPUEH_IFC_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFC */
-#define FPUEH_IFC_FPOFC (0x1UL << 3) /**< Clear FPOFC Interrupt Flag */
-#define _FPUEH_IFC_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
-#define _FPUEH_IFC_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
-#define _FPUEH_IFC_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
-#define FPUEH_IFC_FPOFC_DEFAULT (_FPUEH_IFC_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFC */
-#define FPUEH_IFC_FPIDC (0x1UL << 4) /**< Clear FPIDC Interrupt Flag */
-#define _FPUEH_IFC_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
-#define _FPUEH_IFC_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
-#define _FPUEH_IFC_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
-#define FPUEH_IFC_FPIDC_DEFAULT (_FPUEH_IFC_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFC */
-#define FPUEH_IFC_FPIXC (0x1UL << 5) /**< Clear FPIXC Interrupt Flag */
-#define _FPUEH_IFC_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
-#define _FPUEH_IFC_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
-#define _FPUEH_IFC_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
-#define FPUEH_IFC_FPIXC_DEFAULT (_FPUEH_IFC_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFC */
-
-/* Bit fields for FPUEH IEN */
-#define _FPUEH_IEN_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IEN */
-#define _FPUEH_IEN_MASK 0x0000003FUL /**< Mask for FPUEH_IEN */
-#define FPUEH_IEN_FPIOC (0x1UL << 0) /**< FPIOC Interrupt Enable */
-#define _FPUEH_IEN_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
-#define _FPUEH_IEN_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
-#define _FPUEH_IEN_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
-#define FPUEH_IEN_FPIOC_DEFAULT (_FPUEH_IEN_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IEN */
-#define FPUEH_IEN_FPDZC (0x1UL << 1) /**< FPDZC Interrupt Enable */
-#define _FPUEH_IEN_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
-#define _FPUEH_IEN_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
-#define _FPUEH_IEN_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
-#define FPUEH_IEN_FPDZC_DEFAULT (_FPUEH_IEN_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IEN */
-#define FPUEH_IEN_FPUFC (0x1UL << 2) /**< FPUFC Interrupt Enable */
-#define _FPUEH_IEN_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
-#define _FPUEH_IEN_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
-#define _FPUEH_IEN_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
-#define FPUEH_IEN_FPUFC_DEFAULT (_FPUEH_IEN_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IEN */
-#define FPUEH_IEN_FPOFC (0x1UL << 3) /**< FPOFC Interrupt Enable */
-#define _FPUEH_IEN_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
-#define _FPUEH_IEN_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
-#define _FPUEH_IEN_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
-#define FPUEH_IEN_FPOFC_DEFAULT (_FPUEH_IEN_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IEN */
-#define FPUEH_IEN_FPIDC (0x1UL << 4) /**< FPIDC Interrupt Enable */
-#define _FPUEH_IEN_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
-#define _FPUEH_IEN_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
-#define _FPUEH_IEN_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
-#define FPUEH_IEN_FPIDC_DEFAULT (_FPUEH_IEN_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IEN */
-#define FPUEH_IEN_FPIXC (0x1UL << 5) /**< FPIXC Interrupt Enable */
-#define _FPUEH_IEN_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
-#define _FPUEH_IEN_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
-#define _FPUEH_IEN_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
-#define FPUEH_IEN_FPIXC_DEFAULT (_FPUEH_IEN_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IEN */
-
-/** @} */
-/** @} End of group EFR32FG13P_FPUEH */
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_gpcrc.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_gpcrc.h
deleted file mode 100644
index f03bee42..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_gpcrc.h
+++ /dev/null
@@ -1,194 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_gpcrc.h
- * @brief EFR32FG13P_GPCRC register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P_GPCRC GPCRC
- * @{
- * @brief EFR32FG13P_GPCRC Register Declaration
- *****************************************************************************/
-/** GPCRC Register Declaration */
-typedef struct {
- __IOM uint32_t CTRL; /**< Control Register */
- __IOM uint32_t CMD; /**< Command Register */
- __IOM uint32_t INIT; /**< CRC Init Value */
- __IOM uint32_t POLY; /**< CRC Polynomial Value */
- __IOM uint32_t INPUTDATA; /**< Input 32-bit Data Register */
- __IOM uint32_t INPUTDATAHWORD; /**< Input 16-bit Data Register */
- __IOM uint32_t INPUTDATABYTE; /**< Input 8-bit Data Register */
- __IM uint32_t DATA; /**< CRC Data Register */
- __IM uint32_t DATAREV; /**< CRC Data Reverse Register */
- __IM uint32_t DATABYTEREV; /**< CRC Data Byte Reverse Register */
-} GPCRC_TypeDef; /** @} */
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_GPCRC
- * @{
- * @defgroup EFR32FG13P_GPCRC_BitFields GPCRC Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for GPCRC CTRL */
-#define _GPCRC_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CTRL */
-#define _GPCRC_CTRL_MASK 0x00002711UL /**< Mask for GPCRC_CTRL */
-#define GPCRC_CTRL_EN (0x1UL << 0) /**< CRC Functionality Enable */
-#define _GPCRC_CTRL_EN_SHIFT 0 /**< Shift value for GPCRC_EN */
-#define _GPCRC_CTRL_EN_MASK 0x1UL /**< Bit mask for GPCRC_EN */
-#define _GPCRC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
-#define _GPCRC_CTRL_EN_DISABLE 0x00000000UL /**< Mode DISABLE for GPCRC_CTRL */
-#define _GPCRC_CTRL_EN_ENABLE 0x00000001UL /**< Mode ENABLE for GPCRC_CTRL */
-#define GPCRC_CTRL_EN_DEFAULT (_GPCRC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CTRL */
-#define GPCRC_CTRL_EN_DISABLE (_GPCRC_CTRL_EN_DISABLE << 0) /**< Shifted mode DISABLE for GPCRC_CTRL */
-#define GPCRC_CTRL_EN_ENABLE (_GPCRC_CTRL_EN_ENABLE << 0) /**< Shifted mode ENABLE for GPCRC_CTRL */
-#define GPCRC_CTRL_POLYSEL (0x1UL << 4) /**< Polynomial Select */
-#define _GPCRC_CTRL_POLYSEL_SHIFT 4 /**< Shift value for GPCRC_POLYSEL */
-#define _GPCRC_CTRL_POLYSEL_MASK 0x10UL /**< Bit mask for GPCRC_POLYSEL */
-#define _GPCRC_CTRL_POLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
-#define _GPCRC_CTRL_POLYSEL_CRC32 0x00000000UL /**< Mode CRC32 for GPCRC_CTRL */
-#define _GPCRC_CTRL_POLYSEL_16 0x00000001UL /**< Mode 16 for GPCRC_CTRL */
-#define GPCRC_CTRL_POLYSEL_DEFAULT (_GPCRC_CTRL_POLYSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for GPCRC_CTRL */
-#define GPCRC_CTRL_POLYSEL_CRC32 (_GPCRC_CTRL_POLYSEL_CRC32 << 4) /**< Shifted mode CRC32 for GPCRC_CTRL */
-#define GPCRC_CTRL_POLYSEL_16 (_GPCRC_CTRL_POLYSEL_16 << 4) /**< Shifted mode 16 for GPCRC_CTRL */
-#define GPCRC_CTRL_BYTEMODE (0x1UL << 8) /**< Byte Mode Enable */
-#define _GPCRC_CTRL_BYTEMODE_SHIFT 8 /**< Shift value for GPCRC_BYTEMODE */
-#define _GPCRC_CTRL_BYTEMODE_MASK 0x100UL /**< Bit mask for GPCRC_BYTEMODE */
-#define _GPCRC_CTRL_BYTEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
-#define GPCRC_CTRL_BYTEMODE_DEFAULT (_GPCRC_CTRL_BYTEMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for GPCRC_CTRL */
-#define GPCRC_CTRL_BITREVERSE (0x1UL << 9) /**< Byte-level Bit Reverse Enable */
-#define _GPCRC_CTRL_BITREVERSE_SHIFT 9 /**< Shift value for GPCRC_BITREVERSE */
-#define _GPCRC_CTRL_BITREVERSE_MASK 0x200UL /**< Bit mask for GPCRC_BITREVERSE */
-#define _GPCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
-#define _GPCRC_CTRL_BITREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */
-#define _GPCRC_CTRL_BITREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */
-#define GPCRC_CTRL_BITREVERSE_DEFAULT (_GPCRC_CTRL_BITREVERSE_DEFAULT << 9) /**< Shifted mode DEFAULT for GPCRC_CTRL */
-#define GPCRC_CTRL_BITREVERSE_NORMAL (_GPCRC_CTRL_BITREVERSE_NORMAL << 9) /**< Shifted mode NORMAL for GPCRC_CTRL */
-#define GPCRC_CTRL_BITREVERSE_REVERSED (_GPCRC_CTRL_BITREVERSE_REVERSED << 9) /**< Shifted mode REVERSED for GPCRC_CTRL */
-#define GPCRC_CTRL_BYTEREVERSE (0x1UL << 10) /**< Byte Reverse Mode */
-#define _GPCRC_CTRL_BYTEREVERSE_SHIFT 10 /**< Shift value for GPCRC_BYTEREVERSE */
-#define _GPCRC_CTRL_BYTEREVERSE_MASK 0x400UL /**< Bit mask for GPCRC_BYTEREVERSE */
-#define _GPCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
-#define _GPCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */
-#define _GPCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */
-#define GPCRC_CTRL_BYTEREVERSE_DEFAULT (_GPCRC_CTRL_BYTEREVERSE_DEFAULT << 10) /**< Shifted mode DEFAULT for GPCRC_CTRL */
-#define GPCRC_CTRL_BYTEREVERSE_NORMAL (_GPCRC_CTRL_BYTEREVERSE_NORMAL << 10) /**< Shifted mode NORMAL for GPCRC_CTRL */
-#define GPCRC_CTRL_BYTEREVERSE_REVERSED (_GPCRC_CTRL_BYTEREVERSE_REVERSED << 10) /**< Shifted mode REVERSED for GPCRC_CTRL */
-#define GPCRC_CTRL_AUTOINIT (0x1UL << 13) /**< Auto Init Enable */
-#define _GPCRC_CTRL_AUTOINIT_SHIFT 13 /**< Shift value for GPCRC_AUTOINIT */
-#define _GPCRC_CTRL_AUTOINIT_MASK 0x2000UL /**< Bit mask for GPCRC_AUTOINIT */
-#define _GPCRC_CTRL_AUTOINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
-#define GPCRC_CTRL_AUTOINIT_DEFAULT (_GPCRC_CTRL_AUTOINIT_DEFAULT << 13) /**< Shifted mode DEFAULT for GPCRC_CTRL */
-
-/* Bit fields for GPCRC CMD */
-#define _GPCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CMD */
-#define _GPCRC_CMD_MASK 0x00000001UL /**< Mask for GPCRC_CMD */
-#define GPCRC_CMD_INIT (0x1UL << 0) /**< Initialization Enable */
-#define _GPCRC_CMD_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */
-#define _GPCRC_CMD_INIT_MASK 0x1UL /**< Bit mask for GPCRC_INIT */
-#define _GPCRC_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CMD */
-#define GPCRC_CMD_INIT_DEFAULT (_GPCRC_CMD_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CMD */
-
-/* Bit fields for GPCRC INIT */
-#define _GPCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INIT */
-#define _GPCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INIT */
-#define _GPCRC_INIT_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */
-#define _GPCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INIT */
-#define _GPCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INIT */
-#define GPCRC_INIT_INIT_DEFAULT (_GPCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INIT */
-
-/* Bit fields for GPCRC POLY */
-#define _GPCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for GPCRC_POLY */
-#define _GPCRC_POLY_MASK 0x0000FFFFUL /**< Mask for GPCRC_POLY */
-#define _GPCRC_POLY_POLY_SHIFT 0 /**< Shift value for GPCRC_POLY */
-#define _GPCRC_POLY_POLY_MASK 0xFFFFUL /**< Bit mask for GPCRC_POLY */
-#define _GPCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_POLY */
-#define GPCRC_POLY_POLY_DEFAULT (_GPCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_POLY */
-
-/* Bit fields for GPCRC INPUTDATA */
-#define _GPCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATA */
-#define _GPCRC_INPUTDATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INPUTDATA */
-#define _GPCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for GPCRC_INPUTDATA */
-#define _GPCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INPUTDATA */
-#define _GPCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATA */
-#define GPCRC_INPUTDATA_INPUTDATA_DEFAULT (_GPCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATA */
-
-/* Bit fields for GPCRC INPUTDATAHWORD */
-#define _GPCRC_INPUTDATAHWORD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATAHWORD */
-#define _GPCRC_INPUTDATAHWORD_MASK 0x0000FFFFUL /**< Mask for GPCRC_INPUTDATAHWORD */
-#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_SHIFT 0 /**< Shift value for GPCRC_INPUTDATAHWORD */
-#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_MASK 0xFFFFUL /**< Bit mask for GPCRC_INPUTDATAHWORD */
-#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATAHWORD */
-#define GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT (_GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATAHWORD */
-
-/* Bit fields for GPCRC INPUTDATABYTE */
-#define _GPCRC_INPUTDATABYTE_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATABYTE */
-#define _GPCRC_INPUTDATABYTE_MASK 0x000000FFUL /**< Mask for GPCRC_INPUTDATABYTE */
-#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_SHIFT 0 /**< Shift value for GPCRC_INPUTDATABYTE */
-#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_MASK 0xFFUL /**< Bit mask for GPCRC_INPUTDATABYTE */
-#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATABYTE */
-#define GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT (_GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATABYTE */
-
-/* Bit fields for GPCRC DATA */
-#define _GPCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATA */
-#define _GPCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATA */
-#define _GPCRC_DATA_DATA_SHIFT 0 /**< Shift value for GPCRC_DATA */
-#define _GPCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATA */
-#define _GPCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATA */
-#define GPCRC_DATA_DATA_DEFAULT (_GPCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATA */
-
-/* Bit fields for GPCRC DATAREV */
-#define _GPCRC_DATAREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATAREV */
-#define _GPCRC_DATAREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATAREV */
-#define _GPCRC_DATAREV_DATAREV_SHIFT 0 /**< Shift value for GPCRC_DATAREV */
-#define _GPCRC_DATAREV_DATAREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATAREV */
-#define _GPCRC_DATAREV_DATAREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATAREV */
-#define GPCRC_DATAREV_DATAREV_DEFAULT (_GPCRC_DATAREV_DATAREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATAREV */
-
-/* Bit fields for GPCRC DATABYTEREV */
-#define _GPCRC_DATABYTEREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATABYTEREV */
-#define _GPCRC_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATABYTEREV */
-#define _GPCRC_DATABYTEREV_DATABYTEREV_SHIFT 0 /**< Shift value for GPCRC_DATABYTEREV */
-#define _GPCRC_DATABYTEREV_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATABYTEREV */
-#define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATABYTEREV */
-#define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */
-
-/** @} */
-/** @} End of group EFR32FG13P_GPCRC */
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_gpio.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_gpio.h
deleted file mode 100644
index 9d9c50e3..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_gpio.h
+++ /dev/null
@@ -1,1451 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_gpio.h
- * @brief EFR32FG13P_GPIO register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P_GPIO GPIO
- * @{
- * @brief EFR32FG13P_GPIO Register Declaration
- *****************************************************************************/
-/** GPIO Register Declaration */
-typedef struct {
- GPIO_P_TypeDef P[12]; /**< Port configuration bits */
-
- uint32_t RESERVED0[112]; /**< Reserved for future use **/
- __IOM uint32_t EXTIPSELL; /**< External Interrupt Port Select Low Register */
- __IOM uint32_t EXTIPSELH; /**< External Interrupt Port Select High Register */
- __IOM uint32_t EXTIPINSELL; /**< External Interrupt Pin Select Low Register */
- __IOM uint32_t EXTIPINSELH; /**< External Interrupt Pin Select High Register */
- __IOM uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger Register */
- __IOM uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger Register */
- __IOM uint32_t EXTILEVEL; /**< External Interrupt Level Register */
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- __IOM uint32_t EM4WUEN; /**< EM4 Wake Up Enable Register */
-
- uint32_t RESERVED1[4]; /**< Reserved for future use **/
- __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
- __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
- __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register 1 */
-
- uint32_t RESERVED2[1]; /**< Reserved for future use **/
- __IOM uint32_t INSENSE; /**< Input Sense Register */
- __IOM uint32_t LOCK; /**< Configuration Lock Register */
-} GPIO_TypeDef; /** @} */
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_GPIO
- * @{
- * @defgroup EFR32FG13P_GPIO_BitFields GPIO Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for GPIO P_CTRL */
-#define _GPIO_P_CTRL_RESETVALUE 0x00500050UL /**< Default value for GPIO_P_CTRL */
-#define _GPIO_P_CTRL_MASK 0x10711071UL /**< Mask for GPIO_P_CTRL */
-#define GPIO_P_CTRL_DRIVESTRENGTH (0x1UL << 0) /**< Drive Strength for Port */
-#define _GPIO_P_CTRL_DRIVESTRENGTH_SHIFT 0 /**< Shift value for GPIO_DRIVESTRENGTH */
-#define _GPIO_P_CTRL_DRIVESTRENGTH_MASK 0x1UL /**< Bit mask for GPIO_DRIVESTRENGTH */
-#define _GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */
-#define _GPIO_P_CTRL_DRIVESTRENGTH_STRONG 0x00000000UL /**< Mode STRONG for GPIO_P_CTRL */
-#define _GPIO_P_CTRL_DRIVESTRENGTH_WEAK 0x00000001UL /**< Mode WEAK for GPIO_P_CTRL */
-#define GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT (_GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_CTRL */
-#define GPIO_P_CTRL_DRIVESTRENGTH_STRONG (_GPIO_P_CTRL_DRIVESTRENGTH_STRONG << 0) /**< Shifted mode STRONG for GPIO_P_CTRL */
-#define GPIO_P_CTRL_DRIVESTRENGTH_WEAK (_GPIO_P_CTRL_DRIVESTRENGTH_WEAK << 0) /**< Shifted mode WEAK for GPIO_P_CTRL */
-#define _GPIO_P_CTRL_SLEWRATE_SHIFT 4 /**< Shift value for GPIO_SLEWRATE */
-#define _GPIO_P_CTRL_SLEWRATE_MASK 0x70UL /**< Bit mask for GPIO_SLEWRATE */
-#define _GPIO_P_CTRL_SLEWRATE_DEFAULT 0x00000005UL /**< Mode DEFAULT for GPIO_P_CTRL */
-#define GPIO_P_CTRL_SLEWRATE_DEFAULT (_GPIO_P_CTRL_SLEWRATE_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_CTRL */
-#define GPIO_P_CTRL_DINDIS (0x1UL << 12) /**< Data in Disable */
-#define _GPIO_P_CTRL_DINDIS_SHIFT 12 /**< Shift value for GPIO_DINDIS */
-#define _GPIO_P_CTRL_DINDIS_MASK 0x1000UL /**< Bit mask for GPIO_DINDIS */
-#define _GPIO_P_CTRL_DINDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */
-#define GPIO_P_CTRL_DINDIS_DEFAULT (_GPIO_P_CTRL_DINDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_CTRL */
-#define GPIO_P_CTRL_DRIVESTRENGTHALT (0x1UL << 16) /**< Alternate Drive Strength for Port */
-#define _GPIO_P_CTRL_DRIVESTRENGTHALT_SHIFT 16 /**< Shift value for GPIO_DRIVESTRENGTHALT */
-#define _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK 0x10000UL /**< Bit mask for GPIO_DRIVESTRENGTHALT */
-#define _GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */
-#define _GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG 0x00000000UL /**< Mode STRONG for GPIO_P_CTRL */
-#define _GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK 0x00000001UL /**< Mode WEAK for GPIO_P_CTRL */
-#define GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT (_GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_CTRL */
-#define GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG (_GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG << 16) /**< Shifted mode STRONG for GPIO_P_CTRL */
-#define GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK (_GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK << 16) /**< Shifted mode WEAK for GPIO_P_CTRL */
-#define _GPIO_P_CTRL_SLEWRATEALT_SHIFT 20 /**< Shift value for GPIO_SLEWRATEALT */
-#define _GPIO_P_CTRL_SLEWRATEALT_MASK 0x700000UL /**< Bit mask for GPIO_SLEWRATEALT */
-#define _GPIO_P_CTRL_SLEWRATEALT_DEFAULT 0x00000005UL /**< Mode DEFAULT for GPIO_P_CTRL */
-#define GPIO_P_CTRL_SLEWRATEALT_DEFAULT (_GPIO_P_CTRL_SLEWRATEALT_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_CTRL */
-#define GPIO_P_CTRL_DINDISALT (0x1UL << 28) /**< Alternate Data in Disable */
-#define _GPIO_P_CTRL_DINDISALT_SHIFT 28 /**< Shift value for GPIO_DINDISALT */
-#define _GPIO_P_CTRL_DINDISALT_MASK 0x10000000UL /**< Bit mask for GPIO_DINDISALT */
-#define _GPIO_P_CTRL_DINDISALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */
-#define GPIO_P_CTRL_DINDISALT_DEFAULT (_GPIO_P_CTRL_DINDISALT_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_CTRL */
-
-/* Bit fields for GPIO P_MODEL */
-#define _GPIO_P_MODEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */
-#define _GPIO_P_MODEL_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */
-#define _GPIO_P_MODEL_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE0_DEFAULT (_GPIO_P_MODEL_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE0_DISABLED (_GPIO_P_MODEL_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE0_INPUT (_GPIO_P_MODEL_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE0_INPUTPULL (_GPIO_P_MODEL_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE0_INPUTPULLFILTER (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE0_PUSHPULL (_GPIO_P_MODEL_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE0_PUSHPULLALT (_GPIO_P_MODEL_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE0_WIREDOR (_GPIO_P_MODEL_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE0_WIREDAND (_GPIO_P_MODEL_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE0_WIREDANDFILTER (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE0_WIREDANDPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE0_WIREDANDALT (_GPIO_P_MODEL_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */
-#define _GPIO_P_MODEL_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */
-#define _GPIO_P_MODEL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE1_DEFAULT (_GPIO_P_MODEL_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE1_DISABLED (_GPIO_P_MODEL_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE1_INPUT (_GPIO_P_MODEL_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE1_INPUTPULL (_GPIO_P_MODEL_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE1_INPUTPULLFILTER (_GPIO_P_MODEL_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE1_PUSHPULL (_GPIO_P_MODEL_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE1_PUSHPULLALT (_GPIO_P_MODEL_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE1_WIREDOR (_GPIO_P_MODEL_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE1_WIREDAND (_GPIO_P_MODEL_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE1_WIREDANDFILTER (_GPIO_P_MODEL_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE1_WIREDANDPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE1_WIREDANDALT (_GPIO_P_MODEL_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */
-#define _GPIO_P_MODEL_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */
-#define _GPIO_P_MODEL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE2_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE2_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE2_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE2_DEFAULT (_GPIO_P_MODEL_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE2_DISABLED (_GPIO_P_MODEL_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE2_INPUT (_GPIO_P_MODEL_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE2_INPUTPULL (_GPIO_P_MODEL_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE2_INPUTPULLFILTER (_GPIO_P_MODEL_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE2_PUSHPULL (_GPIO_P_MODEL_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE2_PUSHPULLALT (_GPIO_P_MODEL_MODE2_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE2_WIREDOR (_GPIO_P_MODEL_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE2_WIREDAND (_GPIO_P_MODEL_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE2_WIREDANDFILTER (_GPIO_P_MODEL_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE2_WIREDANDPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE2_WIREDANDALT (_GPIO_P_MODEL_MODE2_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE2_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE3_SHIFT 12 /**< Shift value for GPIO_MODE3 */
-#define _GPIO_P_MODEL_MODE3_MASK 0xF000UL /**< Bit mask for GPIO_MODE3 */
-#define _GPIO_P_MODEL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE3_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE3_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE3_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE3_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE3_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE3_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE3_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE3_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE3_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE3_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE3_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE3_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE3_DEFAULT (_GPIO_P_MODEL_MODE3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE3_DISABLED (_GPIO_P_MODEL_MODE3_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE3_INPUT (_GPIO_P_MODEL_MODE3_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE3_INPUTPULL (_GPIO_P_MODEL_MODE3_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE3_INPUTPULLFILTER (_GPIO_P_MODEL_MODE3_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE3_PUSHPULL (_GPIO_P_MODEL_MODE3_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE3_PUSHPULLALT (_GPIO_P_MODEL_MODE3_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE3_WIREDOR (_GPIO_P_MODEL_MODE3_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE3_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE3_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE3_WIREDAND (_GPIO_P_MODEL_MODE3_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE3_WIREDANDFILTER (_GPIO_P_MODEL_MODE3_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE3_WIREDANDPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE3_WIREDANDALT (_GPIO_P_MODEL_MODE3_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE3_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE4_SHIFT 16 /**< Shift value for GPIO_MODE4 */
-#define _GPIO_P_MODEL_MODE4_MASK 0xF0000UL /**< Bit mask for GPIO_MODE4 */
-#define _GPIO_P_MODEL_MODE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE4_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE4_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE4_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE4_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE4_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE4_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE4_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE4_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE4_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE4_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE4_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE4_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE4_DEFAULT (_GPIO_P_MODEL_MODE4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE4_DISABLED (_GPIO_P_MODEL_MODE4_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE4_INPUT (_GPIO_P_MODEL_MODE4_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE4_INPUTPULL (_GPIO_P_MODEL_MODE4_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE4_INPUTPULLFILTER (_GPIO_P_MODEL_MODE4_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE4_PUSHPULL (_GPIO_P_MODEL_MODE4_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE4_PUSHPULLALT (_GPIO_P_MODEL_MODE4_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE4_WIREDOR (_GPIO_P_MODEL_MODE4_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE4_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE4_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE4_WIREDAND (_GPIO_P_MODEL_MODE4_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE4_WIREDANDFILTER (_GPIO_P_MODEL_MODE4_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE4_WIREDANDPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE4_WIREDANDALT (_GPIO_P_MODEL_MODE4_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE4_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE5_SHIFT 20 /**< Shift value for GPIO_MODE5 */
-#define _GPIO_P_MODEL_MODE5_MASK 0xF00000UL /**< Bit mask for GPIO_MODE5 */
-#define _GPIO_P_MODEL_MODE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE5_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE5_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE5_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE5_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE5_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE5_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE5_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE5_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE5_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE5_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE5_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE5_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE5_DEFAULT (_GPIO_P_MODEL_MODE5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE5_DISABLED (_GPIO_P_MODEL_MODE5_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE5_INPUT (_GPIO_P_MODEL_MODE5_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE5_INPUTPULL (_GPIO_P_MODEL_MODE5_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE5_INPUTPULLFILTER (_GPIO_P_MODEL_MODE5_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE5_PUSHPULL (_GPIO_P_MODEL_MODE5_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE5_PUSHPULLALT (_GPIO_P_MODEL_MODE5_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE5_WIREDOR (_GPIO_P_MODEL_MODE5_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE5_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE5_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE5_WIREDAND (_GPIO_P_MODEL_MODE5_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE5_WIREDANDFILTER (_GPIO_P_MODEL_MODE5_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE5_WIREDANDPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE5_WIREDANDALT (_GPIO_P_MODEL_MODE5_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE5_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE6_SHIFT 24 /**< Shift value for GPIO_MODE6 */
-#define _GPIO_P_MODEL_MODE6_MASK 0xF000000UL /**< Bit mask for GPIO_MODE6 */
-#define _GPIO_P_MODEL_MODE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE6_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE6_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE6_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE6_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE6_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE6_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE6_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE6_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE6_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE6_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE6_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE6_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE6_DEFAULT (_GPIO_P_MODEL_MODE6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE6_DISABLED (_GPIO_P_MODEL_MODE6_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE6_INPUT (_GPIO_P_MODEL_MODE6_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE6_INPUTPULL (_GPIO_P_MODEL_MODE6_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE6_INPUTPULLFILTER (_GPIO_P_MODEL_MODE6_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE6_PUSHPULL (_GPIO_P_MODEL_MODE6_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE6_PUSHPULLALT (_GPIO_P_MODEL_MODE6_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE6_WIREDOR (_GPIO_P_MODEL_MODE6_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE6_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE6_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE6_WIREDAND (_GPIO_P_MODEL_MODE6_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE6_WIREDANDFILTER (_GPIO_P_MODEL_MODE6_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE6_WIREDANDPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE6_WIREDANDALT (_GPIO_P_MODEL_MODE6_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE6_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE7_SHIFT 28 /**< Shift value for GPIO_MODE7 */
-#define _GPIO_P_MODEL_MODE7_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE7 */
-#define _GPIO_P_MODEL_MODE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE7_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE7_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE7_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE7_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE7_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE7_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE7_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE7_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE7_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE7_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE7_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE7_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
-#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE7_DEFAULT (_GPIO_P_MODEL_MODE7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE7_DISABLED (_GPIO_P_MODEL_MODE7_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE7_INPUT (_GPIO_P_MODEL_MODE7_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE7_INPUTPULL (_GPIO_P_MODEL_MODE7_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE7_INPUTPULLFILTER (_GPIO_P_MODEL_MODE7_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE7_PUSHPULL (_GPIO_P_MODEL_MODE7_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE7_PUSHPULLALT (_GPIO_P_MODEL_MODE7_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE7_WIREDOR (_GPIO_P_MODEL_MODE7_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE7_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE7_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE7_WIREDAND (_GPIO_P_MODEL_MODE7_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE7_WIREDANDFILTER (_GPIO_P_MODEL_MODE7_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE7_WIREDANDPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE7_WIREDANDALT (_GPIO_P_MODEL_MODE7_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE7_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */
-#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */
-
-/* Bit fields for GPIO P_MODEH */
-#define _GPIO_P_MODEH_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE8_SHIFT 0 /**< Shift value for GPIO_MODE8 */
-#define _GPIO_P_MODEH_MODE8_MASK 0xFUL /**< Bit mask for GPIO_MODE8 */
-#define _GPIO_P_MODEH_MODE8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE8_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE8_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE8_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE8_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE8_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE8_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE8_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE8_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE8_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE8_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE8_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE8_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE8_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE8_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE8_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE8_DEFAULT (_GPIO_P_MODEH_MODE8_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE8_DISABLED (_GPIO_P_MODEH_MODE8_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE8_INPUT (_GPIO_P_MODEH_MODE8_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE8_INPUTPULL (_GPIO_P_MODEH_MODE8_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE8_INPUTPULLFILTER (_GPIO_P_MODEH_MODE8_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE8_PUSHPULL (_GPIO_P_MODEH_MODE8_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE8_PUSHPULLALT (_GPIO_P_MODEH_MODE8_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE8_WIREDOR (_GPIO_P_MODEH_MODE8_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE8_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE8_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE8_WIREDAND (_GPIO_P_MODEH_MODE8_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE8_WIREDANDFILTER (_GPIO_P_MODEH_MODE8_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE8_WIREDANDPULLUP (_GPIO_P_MODEH_MODE8_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE8_WIREDANDALT (_GPIO_P_MODEH_MODE8_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE8_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE8_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE8_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE8_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE8_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE8_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE9_SHIFT 4 /**< Shift value for GPIO_MODE9 */
-#define _GPIO_P_MODEH_MODE9_MASK 0xF0UL /**< Bit mask for GPIO_MODE9 */
-#define _GPIO_P_MODEH_MODE9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE9_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE9_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE9_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE9_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE9_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE9_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE9_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE9_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE9_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE9_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE9_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE9_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE9_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE9_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE9_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE9_DEFAULT (_GPIO_P_MODEH_MODE9_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE9_DISABLED (_GPIO_P_MODEH_MODE9_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE9_INPUT (_GPIO_P_MODEH_MODE9_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE9_INPUTPULL (_GPIO_P_MODEH_MODE9_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE9_INPUTPULLFILTER (_GPIO_P_MODEH_MODE9_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE9_PUSHPULL (_GPIO_P_MODEH_MODE9_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE9_PUSHPULLALT (_GPIO_P_MODEH_MODE9_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE9_WIREDOR (_GPIO_P_MODEH_MODE9_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE9_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE9_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE9_WIREDAND (_GPIO_P_MODEH_MODE9_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE9_WIREDANDFILTER (_GPIO_P_MODEH_MODE9_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE9_WIREDANDPULLUP (_GPIO_P_MODEH_MODE9_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE9_WIREDANDALT (_GPIO_P_MODEH_MODE9_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE9_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE9_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE9_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE9_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE9_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE9_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE10_SHIFT 8 /**< Shift value for GPIO_MODE10 */
-#define _GPIO_P_MODEH_MODE10_MASK 0xF00UL /**< Bit mask for GPIO_MODE10 */
-#define _GPIO_P_MODEH_MODE10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE10_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE10_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE10_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE10_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE10_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE10_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE10_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE10_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE10_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE10_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE10_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE10_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE10_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE10_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE10_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE10_DEFAULT (_GPIO_P_MODEH_MODE10_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE10_DISABLED (_GPIO_P_MODEH_MODE10_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE10_INPUT (_GPIO_P_MODEH_MODE10_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE10_INPUTPULL (_GPIO_P_MODEH_MODE10_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE10_INPUTPULLFILTER (_GPIO_P_MODEH_MODE10_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE10_PUSHPULL (_GPIO_P_MODEH_MODE10_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE10_PUSHPULLALT (_GPIO_P_MODEH_MODE10_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE10_WIREDOR (_GPIO_P_MODEH_MODE10_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE10_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE10_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE10_WIREDAND (_GPIO_P_MODEH_MODE10_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE10_WIREDANDFILTER (_GPIO_P_MODEH_MODE10_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE10_WIREDANDPULLUP (_GPIO_P_MODEH_MODE10_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE10_WIREDANDALT (_GPIO_P_MODEH_MODE10_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE10_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE10_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE10_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE10_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE10_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE10_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE11_SHIFT 12 /**< Shift value for GPIO_MODE11 */
-#define _GPIO_P_MODEH_MODE11_MASK 0xF000UL /**< Bit mask for GPIO_MODE11 */
-#define _GPIO_P_MODEH_MODE11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE11_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE11_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE11_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE11_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE11_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE11_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE11_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE11_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE11_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE11_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE11_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE11_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE11_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE11_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE11_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE11_DEFAULT (_GPIO_P_MODEH_MODE11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE11_DISABLED (_GPIO_P_MODEH_MODE11_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE11_INPUT (_GPIO_P_MODEH_MODE11_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE11_INPUTPULL (_GPIO_P_MODEH_MODE11_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE11_INPUTPULLFILTER (_GPIO_P_MODEH_MODE11_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE11_PUSHPULL (_GPIO_P_MODEH_MODE11_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE11_PUSHPULLALT (_GPIO_P_MODEH_MODE11_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE11_WIREDOR (_GPIO_P_MODEH_MODE11_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE11_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE11_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE11_WIREDAND (_GPIO_P_MODEH_MODE11_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE11_WIREDANDFILTER (_GPIO_P_MODEH_MODE11_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE11_WIREDANDPULLUP (_GPIO_P_MODEH_MODE11_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE11_WIREDANDALT (_GPIO_P_MODEH_MODE11_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE11_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE11_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE11_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE11_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE11_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE11_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE12_SHIFT 16 /**< Shift value for GPIO_MODE12 */
-#define _GPIO_P_MODEH_MODE12_MASK 0xF0000UL /**< Bit mask for GPIO_MODE12 */
-#define _GPIO_P_MODEH_MODE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE12_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE12_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE12_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE12_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE12_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE12_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE12_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE12_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE12_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE12_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE12_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE12_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE12_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE12_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE12_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE12_DEFAULT (_GPIO_P_MODEH_MODE12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE12_DISABLED (_GPIO_P_MODEH_MODE12_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE12_INPUT (_GPIO_P_MODEH_MODE12_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE12_INPUTPULL (_GPIO_P_MODEH_MODE12_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE12_INPUTPULLFILTER (_GPIO_P_MODEH_MODE12_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE12_PUSHPULL (_GPIO_P_MODEH_MODE12_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE12_PUSHPULLALT (_GPIO_P_MODEH_MODE12_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE12_WIREDOR (_GPIO_P_MODEH_MODE12_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE12_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE12_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE12_WIREDAND (_GPIO_P_MODEH_MODE12_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE12_WIREDANDFILTER (_GPIO_P_MODEH_MODE12_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE12_WIREDANDPULLUP (_GPIO_P_MODEH_MODE12_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE12_WIREDANDALT (_GPIO_P_MODEH_MODE12_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE12_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE12_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE12_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE12_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE12_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE12_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE13_SHIFT 20 /**< Shift value for GPIO_MODE13 */
-#define _GPIO_P_MODEH_MODE13_MASK 0xF00000UL /**< Bit mask for GPIO_MODE13 */
-#define _GPIO_P_MODEH_MODE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE13_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE13_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE13_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE13_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE13_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE13_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE13_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE13_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE13_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE13_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE13_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE13_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE13_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE13_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE13_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE13_DEFAULT (_GPIO_P_MODEH_MODE13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE13_DISABLED (_GPIO_P_MODEH_MODE13_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE13_INPUT (_GPIO_P_MODEH_MODE13_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE13_INPUTPULL (_GPIO_P_MODEH_MODE13_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE13_INPUTPULLFILTER (_GPIO_P_MODEH_MODE13_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE13_PUSHPULL (_GPIO_P_MODEH_MODE13_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE13_PUSHPULLALT (_GPIO_P_MODEH_MODE13_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE13_WIREDOR (_GPIO_P_MODEH_MODE13_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE13_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE13_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE13_WIREDAND (_GPIO_P_MODEH_MODE13_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE13_WIREDANDFILTER (_GPIO_P_MODEH_MODE13_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE13_WIREDANDPULLUP (_GPIO_P_MODEH_MODE13_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE13_WIREDANDALT (_GPIO_P_MODEH_MODE13_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE13_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE13_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE13_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE13_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE13_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE13_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE14_SHIFT 24 /**< Shift value for GPIO_MODE14 */
-#define _GPIO_P_MODEH_MODE14_MASK 0xF000000UL /**< Bit mask for GPIO_MODE14 */
-#define _GPIO_P_MODEH_MODE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE14_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE14_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE14_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE14_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE14_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE14_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE14_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE14_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE14_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE14_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE14_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE14_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE14_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE14_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE14_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE14_DEFAULT (_GPIO_P_MODEH_MODE14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE14_DISABLED (_GPIO_P_MODEH_MODE14_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE14_INPUT (_GPIO_P_MODEH_MODE14_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE14_INPUTPULL (_GPIO_P_MODEH_MODE14_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE14_INPUTPULLFILTER (_GPIO_P_MODEH_MODE14_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE14_PUSHPULL (_GPIO_P_MODEH_MODE14_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE14_PUSHPULLALT (_GPIO_P_MODEH_MODE14_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE14_WIREDOR (_GPIO_P_MODEH_MODE14_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE14_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE14_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE14_WIREDAND (_GPIO_P_MODEH_MODE14_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE14_WIREDANDFILTER (_GPIO_P_MODEH_MODE14_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE14_WIREDANDPULLUP (_GPIO_P_MODEH_MODE14_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE14_WIREDANDALT (_GPIO_P_MODEH_MODE14_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE14_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE14_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE14_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE14_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE14_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE14_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE15_SHIFT 28 /**< Shift value for GPIO_MODE15 */
-#define _GPIO_P_MODEH_MODE15_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE15 */
-#define _GPIO_P_MODEH_MODE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE15_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE15_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE15_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE15_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE15_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE15_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE15_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE15_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE15_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE15_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE15_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE15_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE15_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE15_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */
-#define _GPIO_P_MODEH_MODE15_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE15_DEFAULT (_GPIO_P_MODEH_MODE15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE15_DISABLED (_GPIO_P_MODEH_MODE15_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE15_INPUT (_GPIO_P_MODEH_MODE15_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE15_INPUTPULL (_GPIO_P_MODEH_MODE15_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE15_INPUTPULLFILTER (_GPIO_P_MODEH_MODE15_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE15_PUSHPULL (_GPIO_P_MODEH_MODE15_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE15_PUSHPULLALT (_GPIO_P_MODEH_MODE15_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE15_WIREDOR (_GPIO_P_MODEH_MODE15_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE15_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE15_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE15_WIREDAND (_GPIO_P_MODEH_MODE15_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE15_WIREDANDFILTER (_GPIO_P_MODEH_MODE15_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE15_WIREDANDPULLUP (_GPIO_P_MODEH_MODE15_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE15_WIREDANDALT (_GPIO_P_MODEH_MODE15_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE15_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE15_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE15_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE15_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */
-#define GPIO_P_MODEH_MODE15_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE15_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */
-
-/* Bit fields for GPIO P_DOUT */
-#define _GPIO_P_DOUT_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUT */
-#define _GPIO_P_DOUT_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUT */
-#define _GPIO_P_DOUT_DOUT_SHIFT 0 /**< Shift value for GPIO_DOUT */
-#define _GPIO_P_DOUT_DOUT_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUT */
-#define _GPIO_P_DOUT_DOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUT */
-#define GPIO_P_DOUT_DOUT_DEFAULT (_GPIO_P_DOUT_DOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUT */
-
-/* Bit fields for GPIO P_DOUTTGL */
-#define _GPIO_P_DOUTTGL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUTTGL */
-#define _GPIO_P_DOUTTGL_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUTTGL */
-#define _GPIO_P_DOUTTGL_DOUTTGL_SHIFT 0 /**< Shift value for GPIO_DOUTTGL */
-#define _GPIO_P_DOUTTGL_DOUTTGL_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUTTGL */
-#define _GPIO_P_DOUTTGL_DOUTTGL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUTTGL */
-#define GPIO_P_DOUTTGL_DOUTTGL_DEFAULT (_GPIO_P_DOUTTGL_DOUTTGL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUTTGL */
-
-/* Bit fields for GPIO P_DIN */
-#define _GPIO_P_DIN_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DIN */
-#define _GPIO_P_DIN_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DIN */
-#define _GPIO_P_DIN_DIN_SHIFT 0 /**< Shift value for GPIO_DIN */
-#define _GPIO_P_DIN_DIN_MASK 0xFFFFUL /**< Bit mask for GPIO_DIN */
-#define _GPIO_P_DIN_DIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DIN */
-#define GPIO_P_DIN_DIN_DEFAULT (_GPIO_P_DIN_DIN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DIN */
-
-/* Bit fields for GPIO P_PINLOCKN */
-#define _GPIO_P_PINLOCKN_RESETVALUE 0x0000FFFFUL /**< Default value for GPIO_P_PINLOCKN */
-#define _GPIO_P_PINLOCKN_MASK 0x0000FFFFUL /**< Mask for GPIO_P_PINLOCKN */
-#define _GPIO_P_PINLOCKN_PINLOCKN_SHIFT 0 /**< Shift value for GPIO_PINLOCKN */
-#define _GPIO_P_PINLOCKN_PINLOCKN_MASK 0xFFFFUL /**< Bit mask for GPIO_PINLOCKN */
-#define _GPIO_P_PINLOCKN_PINLOCKN_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for GPIO_P_PINLOCKN */
-#define GPIO_P_PINLOCKN_PINLOCKN_DEFAULT (_GPIO_P_PINLOCKN_PINLOCKN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_PINLOCKN */
-
-/* Bit fields for GPIO P_OVTDIS */
-#define _GPIO_P_OVTDIS_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_OVTDIS */
-#define _GPIO_P_OVTDIS_MASK 0x0000FFFFUL /**< Mask for GPIO_P_OVTDIS */
-#define _GPIO_P_OVTDIS_OVTDIS_SHIFT 0 /**< Shift value for GPIO_OVTDIS */
-#define _GPIO_P_OVTDIS_OVTDIS_MASK 0xFFFFUL /**< Bit mask for GPIO_OVTDIS */
-#define _GPIO_P_OVTDIS_OVTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_OVTDIS */
-#define GPIO_P_OVTDIS_OVTDIS_DEFAULT (_GPIO_P_OVTDIS_OVTDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_OVTDIS */
-
-/* Bit fields for GPIO EXTIPSELL */
-#define _GPIO_EXTIPSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */
-#define _GPIO_EXTIPSELL_EXTIPSEL0_MASK 0xFUL /**< Bit mask for GPIO_EXTIPSEL0 */
-#define _GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL0_PORTA (_GPIO_EXTIPSELL_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL0_PORTB (_GPIO_EXTIPSELL_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL0_PORTC (_GPIO_EXTIPSELL_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL0_PORTD (_GPIO_EXTIPSELL_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL0_PORTF (_GPIO_EXTIPSELL_EXTIPSEL0_PORTF << 0) /**< Shifted mode PORTF for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */
-#define _GPIO_EXTIPSELL_EXTIPSEL1_MASK 0xF0UL /**< Bit mask for GPIO_EXTIPSEL1 */
-#define _GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL1_PORTA (_GPIO_EXTIPSELL_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL1_PORTB (_GPIO_EXTIPSELL_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL1_PORTC (_GPIO_EXTIPSELL_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL1_PORTD (_GPIO_EXTIPSELL_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL1_PORTF (_GPIO_EXTIPSELL_EXTIPSEL1_PORTF << 4) /**< Shifted mode PORTF for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */
-#define _GPIO_EXTIPSELL_EXTIPSEL2_MASK 0xF00UL /**< Bit mask for GPIO_EXTIPSEL2 */
-#define _GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL2_PORTA (_GPIO_EXTIPSELL_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL2_PORTB (_GPIO_EXTIPSELL_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL2_PORTC (_GPIO_EXTIPSELL_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL2_PORTD (_GPIO_EXTIPSELL_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL2_PORTF (_GPIO_EXTIPSELL_EXTIPSEL2_PORTF << 8) /**< Shifted mode PORTF for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */
-#define _GPIO_EXTIPSELL_EXTIPSEL3_MASK 0xF000UL /**< Bit mask for GPIO_EXTIPSEL3 */
-#define _GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL3_PORTA (_GPIO_EXTIPSELL_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL3_PORTB (_GPIO_EXTIPSELL_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL3_PORTC (_GPIO_EXTIPSELL_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL3_PORTD (_GPIO_EXTIPSELL_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL3_PORTF (_GPIO_EXTIPSELL_EXTIPSEL3_PORTF << 12) /**< Shifted mode PORTF for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL4 */
-#define _GPIO_EXTIPSELL_EXTIPSEL4_MASK 0xF0000UL /**< Bit mask for GPIO_EXTIPSEL4 */
-#define _GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL4_PORTA (_GPIO_EXTIPSELL_EXTIPSEL4_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL4_PORTB (_GPIO_EXTIPSELL_EXTIPSEL4_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL4_PORTC (_GPIO_EXTIPSELL_EXTIPSEL4_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL4_PORTD (_GPIO_EXTIPSELL_EXTIPSEL4_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL4_PORTF (_GPIO_EXTIPSELL_EXTIPSEL4_PORTF << 16) /**< Shifted mode PORTF for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL5 */
-#define _GPIO_EXTIPSELL_EXTIPSEL5_MASK 0xF00000UL /**< Bit mask for GPIO_EXTIPSEL5 */
-#define _GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL5_PORTA (_GPIO_EXTIPSELL_EXTIPSEL5_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL5_PORTB (_GPIO_EXTIPSELL_EXTIPSEL5_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL5_PORTC (_GPIO_EXTIPSELL_EXTIPSEL5_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL5_PORTD (_GPIO_EXTIPSELL_EXTIPSEL5_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL5_PORTF (_GPIO_EXTIPSELL_EXTIPSEL5_PORTF << 20) /**< Shifted mode PORTF for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL6 */
-#define _GPIO_EXTIPSELL_EXTIPSEL6_MASK 0xF000000UL /**< Bit mask for GPIO_EXTIPSEL6 */
-#define _GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL6_PORTA (_GPIO_EXTIPSELL_EXTIPSEL6_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL6_PORTB (_GPIO_EXTIPSELL_EXTIPSEL6_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL6_PORTC (_GPIO_EXTIPSELL_EXTIPSEL6_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL6_PORTD (_GPIO_EXTIPSELL_EXTIPSEL6_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL6_PORTF (_GPIO_EXTIPSELL_EXTIPSEL6_PORTF << 24) /**< Shifted mode PORTF for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL7 */
-#define _GPIO_EXTIPSELL_EXTIPSEL7_MASK 0xF0000000UL /**< Bit mask for GPIO_EXTIPSEL7 */
-#define _GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
-#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL7_PORTA (_GPIO_EXTIPSELL_EXTIPSEL7_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL7_PORTB (_GPIO_EXTIPSELL_EXTIPSEL7_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL7_PORTC (_GPIO_EXTIPSELL_EXTIPSEL7_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL7_PORTD (_GPIO_EXTIPSELL_EXTIPSEL7_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
-#define GPIO_EXTIPSELL_EXTIPSEL7_PORTF (_GPIO_EXTIPSELL_EXTIPSEL7_PORTF << 28) /**< Shifted mode PORTF for GPIO_EXTIPSELL */
-
-/* Bit fields for GPIO EXTIPSELH */
-#define _GPIO_EXTIPSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_MASK 0xFFFFFFFFUL /**< Mask for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL8_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL8 */
-#define _GPIO_EXTIPSELH_EXTIPSEL8_MASK 0xFUL /**< Bit mask for GPIO_EXTIPSEL8 */
-#define _GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL8_PORTA (_GPIO_EXTIPSELH_EXTIPSEL8_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL8_PORTB (_GPIO_EXTIPSELH_EXTIPSEL8_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL8_PORTC (_GPIO_EXTIPSELH_EXTIPSEL8_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL8_PORTD (_GPIO_EXTIPSELH_EXTIPSEL8_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL8_PORTF (_GPIO_EXTIPSELH_EXTIPSEL8_PORTF << 0) /**< Shifted mode PORTF for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL9_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL9 */
-#define _GPIO_EXTIPSELH_EXTIPSEL9_MASK 0xF0UL /**< Bit mask for GPIO_EXTIPSEL9 */
-#define _GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL9_PORTA (_GPIO_EXTIPSELH_EXTIPSEL9_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL9_PORTB (_GPIO_EXTIPSELH_EXTIPSEL9_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL9_PORTC (_GPIO_EXTIPSELH_EXTIPSEL9_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL9_PORTD (_GPIO_EXTIPSELH_EXTIPSEL9_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL9_PORTF (_GPIO_EXTIPSELH_EXTIPSEL9_PORTF << 4) /**< Shifted mode PORTF for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL10_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL10 */
-#define _GPIO_EXTIPSELH_EXTIPSEL10_MASK 0xF00UL /**< Bit mask for GPIO_EXTIPSEL10 */
-#define _GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL10_PORTA (_GPIO_EXTIPSELH_EXTIPSEL10_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL10_PORTB (_GPIO_EXTIPSELH_EXTIPSEL10_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL10_PORTC (_GPIO_EXTIPSELH_EXTIPSEL10_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL10_PORTD (_GPIO_EXTIPSELH_EXTIPSEL10_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL10_PORTF (_GPIO_EXTIPSELH_EXTIPSEL10_PORTF << 8) /**< Shifted mode PORTF for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL11_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL11 */
-#define _GPIO_EXTIPSELH_EXTIPSEL11_MASK 0xF000UL /**< Bit mask for GPIO_EXTIPSEL11 */
-#define _GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL11_PORTA (_GPIO_EXTIPSELH_EXTIPSEL11_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL11_PORTB (_GPIO_EXTIPSELH_EXTIPSEL11_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL11_PORTC (_GPIO_EXTIPSELH_EXTIPSEL11_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL11_PORTD (_GPIO_EXTIPSELH_EXTIPSEL11_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL11_PORTF (_GPIO_EXTIPSELH_EXTIPSEL11_PORTF << 12) /**< Shifted mode PORTF for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL12_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL12 */
-#define _GPIO_EXTIPSELH_EXTIPSEL12_MASK 0xF0000UL /**< Bit mask for GPIO_EXTIPSEL12 */
-#define _GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL12_PORTA (_GPIO_EXTIPSELH_EXTIPSEL12_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL12_PORTB (_GPIO_EXTIPSELH_EXTIPSEL12_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL12_PORTC (_GPIO_EXTIPSELH_EXTIPSEL12_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL12_PORTD (_GPIO_EXTIPSELH_EXTIPSEL12_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL12_PORTF (_GPIO_EXTIPSELH_EXTIPSEL12_PORTF << 16) /**< Shifted mode PORTF for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL13_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL13 */
-#define _GPIO_EXTIPSELH_EXTIPSEL13_MASK 0xF00000UL /**< Bit mask for GPIO_EXTIPSEL13 */
-#define _GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL13_PORTA (_GPIO_EXTIPSELH_EXTIPSEL13_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL13_PORTB (_GPIO_EXTIPSELH_EXTIPSEL13_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL13_PORTC (_GPIO_EXTIPSELH_EXTIPSEL13_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL13_PORTD (_GPIO_EXTIPSELH_EXTIPSEL13_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL13_PORTF (_GPIO_EXTIPSELH_EXTIPSEL13_PORTF << 20) /**< Shifted mode PORTF for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL14_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL14 */
-#define _GPIO_EXTIPSELH_EXTIPSEL14_MASK 0xF000000UL /**< Bit mask for GPIO_EXTIPSEL14 */
-#define _GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL14_PORTA (_GPIO_EXTIPSELH_EXTIPSEL14_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL14_PORTB (_GPIO_EXTIPSELH_EXTIPSEL14_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL14_PORTC (_GPIO_EXTIPSELH_EXTIPSEL14_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL14_PORTD (_GPIO_EXTIPSELH_EXTIPSEL14_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL14_PORTF (_GPIO_EXTIPSELH_EXTIPSEL14_PORTF << 24) /**< Shifted mode PORTF for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL15_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL15 */
-#define _GPIO_EXTIPSELH_EXTIPSEL15_MASK 0xF0000000UL /**< Bit mask for GPIO_EXTIPSEL15 */
-#define _GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */
-#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL15_PORTA (_GPIO_EXTIPSELH_EXTIPSEL15_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL15_PORTB (_GPIO_EXTIPSELH_EXTIPSEL15_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL15_PORTC (_GPIO_EXTIPSELH_EXTIPSEL15_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL15_PORTD (_GPIO_EXTIPSELH_EXTIPSEL15_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELH */
-#define GPIO_EXTIPSELH_EXTIPSEL15_PORTF (_GPIO_EXTIPSELH_EXTIPSEL15_PORTF << 28) /**< Shifted mode PORTF for GPIO_EXTIPSELH */
-
-/* Bit fields for GPIO EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_RESETVALUE 0x32103210UL /**< Default value for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 << 0) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 << 0) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 << 0) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 << 0) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 << 4) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 << 4) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 << 4) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 << 4) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 << 8) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 << 8) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 << 8) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 << 8) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 << 12) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 << 12) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 << 12) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 << 12) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL4 */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL4 */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN4 << 16) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN5 << 16) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6 << 16) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN7 << 16) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL5 */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL5 */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN4 << 20) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN5 << 20) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN6 << 20) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7 << 20) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL6 */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL6 */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4 << 24) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN5 << 24) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN6 << 24) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN7 << 24) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL7 */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL7 */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */
-#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN4 << 28) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN5 << 28) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN6 << 28) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
-#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7 << 28) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */
-
-/* Bit fields for GPIO EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_RESETVALUE 0x32103210UL /**< Default value for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL8_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL8 */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL8_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL8 */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL8_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL8_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8 << 0) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN9 << 0) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN10 << 0) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN11 << 0) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL9_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL9 */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL9_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL9 */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL9_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN8 << 4) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL9_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL9_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9 << 4) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN10 << 4) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN11 << 4) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL10_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL10 */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL10_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL10 */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL10_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN8 << 8) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN9 << 8) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL10_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL10_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN10 << 8) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11 << 8) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL11_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL11 */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL11_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL11 */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL11_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8 << 12) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN9 << 12) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN10 << 12) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL11_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN11 << 12) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL12_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL12 */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL12_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL12 */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL12_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN12 << 16) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13 << 16) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN14 << 16) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN15 << 16) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL13_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL13 */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL13_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL13 */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL13_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN12 << 20) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL13_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN13 << 20) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN14 << 20) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15 << 20) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL14_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL14 */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL14_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL14 */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL14_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12 << 24) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN13 << 24) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL14_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN14 << 24) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN15 << 24) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL15_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL15 */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL15_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL15 */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL15_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */
-#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12 << 28) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN13 << 28) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN14 << 28) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL15_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */
-#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN15 << 28) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */
-
-/* Bit fields for GPIO EXTIRISE */
-#define _GPIO_EXTIRISE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIRISE */
-#define _GPIO_EXTIRISE_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIRISE */
-#define _GPIO_EXTIRISE_EXTIRISE_SHIFT 0 /**< Shift value for GPIO_EXTIRISE */
-#define _GPIO_EXTIRISE_EXTIRISE_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIRISE */
-#define _GPIO_EXTIRISE_EXTIRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIRISE */
-#define GPIO_EXTIRISE_EXTIRISE_DEFAULT (_GPIO_EXTIRISE_EXTIRISE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIRISE */
-
-/* Bit fields for GPIO EXTIFALL */
-#define _GPIO_EXTIFALL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIFALL */
-#define _GPIO_EXTIFALL_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIFALL */
-#define _GPIO_EXTIFALL_EXTIFALL_SHIFT 0 /**< Shift value for GPIO_EXTIFALL */
-#define _GPIO_EXTIFALL_EXTIFALL_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIFALL */
-#define _GPIO_EXTIFALL_EXTIFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIFALL */
-#define GPIO_EXTIFALL_EXTIFALL_DEFAULT (_GPIO_EXTIFALL_EXTIFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIFALL */
-
-/* Bit fields for GPIO EXTILEVEL */
-#define _GPIO_EXTILEVEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTILEVEL */
-#define _GPIO_EXTILEVEL_MASK 0x13130000UL /**< Mask for GPIO_EXTILEVEL */
-#define GPIO_EXTILEVEL_EM4WU0 (0x1UL << 16) /**< EM4 Wake Up Level for EM4WU0 Pin */
-#define _GPIO_EXTILEVEL_EM4WU0_SHIFT 16 /**< Shift value for GPIO_EM4WU0 */
-#define _GPIO_EXTILEVEL_EM4WU0_MASK 0x10000UL /**< Bit mask for GPIO_EM4WU0 */
-#define _GPIO_EXTILEVEL_EM4WU0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */
-#define GPIO_EXTILEVEL_EM4WU0_DEFAULT (_GPIO_EXTILEVEL_EM4WU0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */
-#define GPIO_EXTILEVEL_EM4WU1 (0x1UL << 17) /**< EM4 Wake Up Level for EM4WU1 Pin */
-#define _GPIO_EXTILEVEL_EM4WU1_SHIFT 17 /**< Shift value for GPIO_EM4WU1 */
-#define _GPIO_EXTILEVEL_EM4WU1_MASK 0x20000UL /**< Bit mask for GPIO_EM4WU1 */
-#define _GPIO_EXTILEVEL_EM4WU1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */
-#define GPIO_EXTILEVEL_EM4WU1_DEFAULT (_GPIO_EXTILEVEL_EM4WU1_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */
-#define GPIO_EXTILEVEL_EM4WU4 (0x1UL << 20) /**< EM4 Wake Up Level for EM4WU4 Pin */
-#define _GPIO_EXTILEVEL_EM4WU4_SHIFT 20 /**< Shift value for GPIO_EM4WU4 */
-#define _GPIO_EXTILEVEL_EM4WU4_MASK 0x100000UL /**< Bit mask for GPIO_EM4WU4 */
-#define _GPIO_EXTILEVEL_EM4WU4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */
-#define GPIO_EXTILEVEL_EM4WU4_DEFAULT (_GPIO_EXTILEVEL_EM4WU4_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */
-#define GPIO_EXTILEVEL_EM4WU8 (0x1UL << 24) /**< EM4 Wake Up Level for EM4WU8 Pin */
-#define _GPIO_EXTILEVEL_EM4WU8_SHIFT 24 /**< Shift value for GPIO_EM4WU8 */
-#define _GPIO_EXTILEVEL_EM4WU8_MASK 0x1000000UL /**< Bit mask for GPIO_EM4WU8 */
-#define _GPIO_EXTILEVEL_EM4WU8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */
-#define GPIO_EXTILEVEL_EM4WU8_DEFAULT (_GPIO_EXTILEVEL_EM4WU8_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */
-#define GPIO_EXTILEVEL_EM4WU9 (0x1UL << 25) /**< EM4 Wake Up Level for EM4WU9 Pin */
-#define _GPIO_EXTILEVEL_EM4WU9_SHIFT 25 /**< Shift value for GPIO_EM4WU9 */
-#define _GPIO_EXTILEVEL_EM4WU9_MASK 0x2000000UL /**< Bit mask for GPIO_EM4WU9 */
-#define _GPIO_EXTILEVEL_EM4WU9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */
-#define GPIO_EXTILEVEL_EM4WU9_DEFAULT (_GPIO_EXTILEVEL_EM4WU9_DEFAULT << 25) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */
-#define GPIO_EXTILEVEL_EM4WU12 (0x1UL << 28) /**< EM4 Wake Up Level for EM4WU12 Pin */
-#define _GPIO_EXTILEVEL_EM4WU12_SHIFT 28 /**< Shift value for GPIO_EM4WU12 */
-#define _GPIO_EXTILEVEL_EM4WU12_MASK 0x10000000UL /**< Bit mask for GPIO_EM4WU12 */
-#define _GPIO_EXTILEVEL_EM4WU12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */
-#define GPIO_EXTILEVEL_EM4WU12_DEFAULT (_GPIO_EXTILEVEL_EM4WU12_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */
-
-/* Bit fields for GPIO IF */
-#define _GPIO_IF_RESETVALUE 0x00000000UL /**< Default value for GPIO_IF */
-#define _GPIO_IF_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IF */
-#define _GPIO_IF_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */
-#define _GPIO_IF_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */
-#define _GPIO_IF_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */
-#define GPIO_IF_EXT_DEFAULT (_GPIO_IF_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IF */
-#define _GPIO_IF_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */
-#define _GPIO_IF_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */
-#define _GPIO_IF_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */
-#define GPIO_IF_EM4WU_DEFAULT (_GPIO_IF_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IF */
-
-/* Bit fields for GPIO IFS */
-#define _GPIO_IFS_RESETVALUE 0x00000000UL /**< Default value for GPIO_IFS */
-#define _GPIO_IFS_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IFS */
-#define _GPIO_IFS_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */
-#define _GPIO_IFS_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */
-#define _GPIO_IFS_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFS */
-#define GPIO_IFS_EXT_DEFAULT (_GPIO_IFS_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IFS */
-#define _GPIO_IFS_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */
-#define _GPIO_IFS_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */
-#define _GPIO_IFS_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFS */
-#define GPIO_IFS_EM4WU_DEFAULT (_GPIO_IFS_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IFS */
-
-/* Bit fields for GPIO IFC */
-#define _GPIO_IFC_RESETVALUE 0x00000000UL /**< Default value for GPIO_IFC */
-#define _GPIO_IFC_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IFC */
-#define _GPIO_IFC_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */
-#define _GPIO_IFC_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */
-#define _GPIO_IFC_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFC */
-#define GPIO_IFC_EXT_DEFAULT (_GPIO_IFC_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IFC */
-#define _GPIO_IFC_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */
-#define _GPIO_IFC_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */
-#define _GPIO_IFC_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFC */
-#define GPIO_IFC_EM4WU_DEFAULT (_GPIO_IFC_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IFC */
-
-/* Bit fields for GPIO IEN */
-#define _GPIO_IEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_IEN */
-#define _GPIO_IEN_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IEN */
-#define _GPIO_IEN_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */
-#define _GPIO_IEN_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */
-#define _GPIO_IEN_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */
-#define GPIO_IEN_EXT_DEFAULT (_GPIO_IEN_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IEN */
-#define _GPIO_IEN_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */
-#define _GPIO_IEN_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */
-#define _GPIO_IEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */
-#define GPIO_IEN_EM4WU_DEFAULT (_GPIO_IEN_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IEN */
-
-/* Bit fields for GPIO EM4WUEN */
-#define _GPIO_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUEN */
-#define _GPIO_EM4WUEN_MASK 0xFFFF0000UL /**< Mask for GPIO_EM4WUEN */
-#define _GPIO_EM4WUEN_EM4WUEN_SHIFT 16 /**< Shift value for GPIO_EM4WUEN */
-#define _GPIO_EM4WUEN_EM4WUEN_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WUEN */
-#define _GPIO_EM4WUEN_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUEN */
-#define GPIO_EM4WUEN_EM4WUEN_DEFAULT (_GPIO_EM4WUEN_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUEN */
-
-/* Bit fields for GPIO ROUTEPEN */
-#define _GPIO_ROUTEPEN_RESETVALUE 0x0000000FUL /**< Default value for GPIO_ROUTEPEN */
-#define _GPIO_ROUTEPEN_MASK 0x001F001FUL /**< Mask for GPIO_ROUTEPEN */
-#define GPIO_ROUTEPEN_SWCLKTCKPEN (0x1UL << 0) /**< Serial Wire Clock and JTAG Test Clock Pin Enable */
-#define _GPIO_ROUTEPEN_SWCLKTCKPEN_SHIFT 0 /**< Shift value for GPIO_SWCLKTCKPEN */
-#define _GPIO_ROUTEPEN_SWCLKTCKPEN_MASK 0x1UL /**< Bit mask for GPIO_SWCLKTCKPEN */
-#define _GPIO_ROUTEPEN_SWCLKTCKPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */
-#define GPIO_ROUTEPEN_SWCLKTCKPEN_DEFAULT (_GPIO_ROUTEPEN_SWCLKTCKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */
-#define GPIO_ROUTEPEN_SWDIOTMSPEN (0x1UL << 1) /**< Serial Wire Data and JTAG Test Mode Select Pin Enable */
-#define _GPIO_ROUTEPEN_SWDIOTMSPEN_SHIFT 1 /**< Shift value for GPIO_SWDIOTMSPEN */
-#define _GPIO_ROUTEPEN_SWDIOTMSPEN_MASK 0x2UL /**< Bit mask for GPIO_SWDIOTMSPEN */
-#define _GPIO_ROUTEPEN_SWDIOTMSPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */
-#define GPIO_ROUTEPEN_SWDIOTMSPEN_DEFAULT (_GPIO_ROUTEPEN_SWDIOTMSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */
-#define GPIO_ROUTEPEN_TDOPEN (0x1UL << 2) /**< JTAG Test Debug Output Pin Enable */
-#define _GPIO_ROUTEPEN_TDOPEN_SHIFT 2 /**< Shift value for GPIO_TDOPEN */
-#define _GPIO_ROUTEPEN_TDOPEN_MASK 0x4UL /**< Bit mask for GPIO_TDOPEN */
-#define _GPIO_ROUTEPEN_TDOPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */
-#define GPIO_ROUTEPEN_TDOPEN_DEFAULT (_GPIO_ROUTEPEN_TDOPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */
-#define GPIO_ROUTEPEN_TDIPEN (0x1UL << 3) /**< JTAG Test Debug Input Pin Enable */
-#define _GPIO_ROUTEPEN_TDIPEN_SHIFT 3 /**< Shift value for GPIO_TDIPEN */
-#define _GPIO_ROUTEPEN_TDIPEN_MASK 0x8UL /**< Bit mask for GPIO_TDIPEN */
-#define _GPIO_ROUTEPEN_TDIPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */
-#define GPIO_ROUTEPEN_TDIPEN_DEFAULT (_GPIO_ROUTEPEN_TDIPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */
-#define GPIO_ROUTEPEN_SWVPEN (0x1UL << 4) /**< Serial Wire Viewer Output Pin Enable */
-#define _GPIO_ROUTEPEN_SWVPEN_SHIFT 4 /**< Shift value for GPIO_SWVPEN */
-#define _GPIO_ROUTEPEN_SWVPEN_MASK 0x10UL /**< Bit mask for GPIO_SWVPEN */
-#define _GPIO_ROUTEPEN_SWVPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */
-#define GPIO_ROUTEPEN_SWVPEN_DEFAULT (_GPIO_ROUTEPEN_SWVPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */
-#define GPIO_ROUTEPEN_ETMTCLKPEN (0x1UL << 16) /**< ETM Trace Clock Pin Enable */
-#define _GPIO_ROUTEPEN_ETMTCLKPEN_SHIFT 16 /**< Shift value for GPIO_ETMTCLKPEN */
-#define _GPIO_ROUTEPEN_ETMTCLKPEN_MASK 0x10000UL /**< Bit mask for GPIO_ETMTCLKPEN */
-#define _GPIO_ROUTEPEN_ETMTCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */
-#define GPIO_ROUTEPEN_ETMTCLKPEN_DEFAULT (_GPIO_ROUTEPEN_ETMTCLKPEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */
-#define GPIO_ROUTEPEN_ETMTD0PEN (0x1UL << 17) /**< ETM Trace Data Pin Enable */
-#define _GPIO_ROUTEPEN_ETMTD0PEN_SHIFT 17 /**< Shift value for GPIO_ETMTD0PEN */
-#define _GPIO_ROUTEPEN_ETMTD0PEN_MASK 0x20000UL /**< Bit mask for GPIO_ETMTD0PEN */
-#define _GPIO_ROUTEPEN_ETMTD0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */
-#define GPIO_ROUTEPEN_ETMTD0PEN_DEFAULT (_GPIO_ROUTEPEN_ETMTD0PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */
-#define GPIO_ROUTEPEN_ETMTD1PEN (0x1UL << 18) /**< ETM Trace Data Pin Enable */
-#define _GPIO_ROUTEPEN_ETMTD1PEN_SHIFT 18 /**< Shift value for GPIO_ETMTD1PEN */
-#define _GPIO_ROUTEPEN_ETMTD1PEN_MASK 0x40000UL /**< Bit mask for GPIO_ETMTD1PEN */
-#define _GPIO_ROUTEPEN_ETMTD1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */
-#define GPIO_ROUTEPEN_ETMTD1PEN_DEFAULT (_GPIO_ROUTEPEN_ETMTD1PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */
-#define GPIO_ROUTEPEN_ETMTD2PEN (0x1UL << 19) /**< ETM Trace Data Pin Enable */
-#define _GPIO_ROUTEPEN_ETMTD2PEN_SHIFT 19 /**< Shift value for GPIO_ETMTD2PEN */
-#define _GPIO_ROUTEPEN_ETMTD2PEN_MASK 0x80000UL /**< Bit mask for GPIO_ETMTD2PEN */
-#define _GPIO_ROUTEPEN_ETMTD2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */
-#define GPIO_ROUTEPEN_ETMTD2PEN_DEFAULT (_GPIO_ROUTEPEN_ETMTD2PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */
-#define GPIO_ROUTEPEN_ETMTD3PEN (0x1UL << 20) /**< ETM Trace Data Pin Enable */
-#define _GPIO_ROUTEPEN_ETMTD3PEN_SHIFT 20 /**< Shift value for GPIO_ETMTD3PEN */
-#define _GPIO_ROUTEPEN_ETMTD3PEN_MASK 0x100000UL /**< Bit mask for GPIO_ETMTD3PEN */
-#define _GPIO_ROUTEPEN_ETMTD3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */
-#define GPIO_ROUTEPEN_ETMTD3PEN_DEFAULT (_GPIO_ROUTEPEN_ETMTD3PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */
-
-/* Bit fields for GPIO ROUTELOC0 */
-#define _GPIO_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for GPIO_ROUTELOC0 */
-#define _GPIO_ROUTELOC0_MASK 0x00000003UL /**< Mask for GPIO_ROUTELOC0 */
-#define _GPIO_ROUTELOC0_SWVLOC_SHIFT 0 /**< Shift value for GPIO_SWVLOC */
-#define _GPIO_ROUTELOC0_SWVLOC_MASK 0x3UL /**< Bit mask for GPIO_SWVLOC */
-#define _GPIO_ROUTELOC0_SWVLOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC0 */
-#define _GPIO_ROUTELOC0_SWVLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC0 */
-#define _GPIO_ROUTELOC0_SWVLOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC0 */
-#define _GPIO_ROUTELOC0_SWVLOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC0 */
-#define _GPIO_ROUTELOC0_SWVLOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC0 */
-#define GPIO_ROUTELOC0_SWVLOC_LOC0 (_GPIO_ROUTELOC0_SWVLOC_LOC0 << 0) /**< Shifted mode LOC0 for GPIO_ROUTELOC0 */
-#define GPIO_ROUTELOC0_SWVLOC_DEFAULT (_GPIO_ROUTELOC0_SWVLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ROUTELOC0 */
-#define GPIO_ROUTELOC0_SWVLOC_LOC1 (_GPIO_ROUTELOC0_SWVLOC_LOC1 << 0) /**< Shifted mode LOC1 for GPIO_ROUTELOC0 */
-#define GPIO_ROUTELOC0_SWVLOC_LOC2 (_GPIO_ROUTELOC0_SWVLOC_LOC2 << 0) /**< Shifted mode LOC2 for GPIO_ROUTELOC0 */
-#define GPIO_ROUTELOC0_SWVLOC_LOC3 (_GPIO_ROUTELOC0_SWVLOC_LOC3 << 0) /**< Shifted mode LOC3 for GPIO_ROUTELOC0 */
-
-/* Bit fields for GPIO ROUTELOC1 */
-#define _GPIO_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for GPIO_ROUTELOC1 */
-#define _GPIO_ROUTELOC1_MASK 0x0C30C303UL /**< Mask for GPIO_ROUTELOC1 */
-#define _GPIO_ROUTELOC1_ETMTCLKLOC_SHIFT 0 /**< Shift value for GPIO_ETMTCLKLOC */
-#define _GPIO_ROUTELOC1_ETMTCLKLOC_MASK 0x3UL /**< Bit mask for GPIO_ETMTCLKLOC */
-#define _GPIO_ROUTELOC1_ETMTCLKLOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC1 */
-#define _GPIO_ROUTELOC1_ETMTCLKLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC1 */
-#define _GPIO_ROUTELOC1_ETMTCLKLOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC1 */
-#define _GPIO_ROUTELOC1_ETMTCLKLOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC1 */
-#define _GPIO_ROUTELOC1_ETMTCLKLOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC1 */
-#define GPIO_ROUTELOC1_ETMTCLKLOC_LOC0 (_GPIO_ROUTELOC1_ETMTCLKLOC_LOC0 << 0) /**< Shifted mode LOC0 for GPIO_ROUTELOC1 */
-#define GPIO_ROUTELOC1_ETMTCLKLOC_DEFAULT (_GPIO_ROUTELOC1_ETMTCLKLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ROUTELOC1 */
-#define GPIO_ROUTELOC1_ETMTCLKLOC_LOC1 (_GPIO_ROUTELOC1_ETMTCLKLOC_LOC1 << 0) /**< Shifted mode LOC1 for GPIO_ROUTELOC1 */
-#define GPIO_ROUTELOC1_ETMTCLKLOC_LOC2 (_GPIO_ROUTELOC1_ETMTCLKLOC_LOC2 << 0) /**< Shifted mode LOC2 for GPIO_ROUTELOC1 */
-#define GPIO_ROUTELOC1_ETMTCLKLOC_LOC3 (_GPIO_ROUTELOC1_ETMTCLKLOC_LOC3 << 0) /**< Shifted mode LOC3 for GPIO_ROUTELOC1 */
-#define _GPIO_ROUTELOC1_ETMTD0LOC_SHIFT 8 /**< Shift value for GPIO_ETMTD0LOC */
-#define _GPIO_ROUTELOC1_ETMTD0LOC_MASK 0x300UL /**< Bit mask for GPIO_ETMTD0LOC */
-#define _GPIO_ROUTELOC1_ETMTD0LOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC1 */
-#define _GPIO_ROUTELOC1_ETMTD0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC1 */
-#define _GPIO_ROUTELOC1_ETMTD0LOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC1 */
-#define _GPIO_ROUTELOC1_ETMTD0LOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC1 */
-#define _GPIO_ROUTELOC1_ETMTD0LOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC1 */
-#define GPIO_ROUTELOC1_ETMTD0LOC_LOC0 (_GPIO_ROUTELOC1_ETMTD0LOC_LOC0 << 8) /**< Shifted mode LOC0 for GPIO_ROUTELOC1 */
-#define GPIO_ROUTELOC1_ETMTD0LOC_DEFAULT (_GPIO_ROUTELOC1_ETMTD0LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_ROUTELOC1 */
-#define GPIO_ROUTELOC1_ETMTD0LOC_LOC1 (_GPIO_ROUTELOC1_ETMTD0LOC_LOC1 << 8) /**< Shifted mode LOC1 for GPIO_ROUTELOC1 */
-#define GPIO_ROUTELOC1_ETMTD0LOC_LOC2 (_GPIO_ROUTELOC1_ETMTD0LOC_LOC2 << 8) /**< Shifted mode LOC2 for GPIO_ROUTELOC1 */
-#define GPIO_ROUTELOC1_ETMTD0LOC_LOC3 (_GPIO_ROUTELOC1_ETMTD0LOC_LOC3 << 8) /**< Shifted mode LOC3 for GPIO_ROUTELOC1 */
-#define _GPIO_ROUTELOC1_ETMTD1LOC_SHIFT 14 /**< Shift value for GPIO_ETMTD1LOC */
-#define _GPIO_ROUTELOC1_ETMTD1LOC_MASK 0xC000UL /**< Bit mask for GPIO_ETMTD1LOC */
-#define _GPIO_ROUTELOC1_ETMTD1LOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC1 */
-#define _GPIO_ROUTELOC1_ETMTD1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC1 */
-#define _GPIO_ROUTELOC1_ETMTD1LOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC1 */
-#define _GPIO_ROUTELOC1_ETMTD1LOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC1 */
-#define _GPIO_ROUTELOC1_ETMTD1LOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC1 */
-#define GPIO_ROUTELOC1_ETMTD1LOC_LOC0 (_GPIO_ROUTELOC1_ETMTD1LOC_LOC0 << 14) /**< Shifted mode LOC0 for GPIO_ROUTELOC1 */
-#define GPIO_ROUTELOC1_ETMTD1LOC_DEFAULT (_GPIO_ROUTELOC1_ETMTD1LOC_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_ROUTELOC1 */
-#define GPIO_ROUTELOC1_ETMTD1LOC_LOC1 (_GPIO_ROUTELOC1_ETMTD1LOC_LOC1 << 14) /**< Shifted mode LOC1 for GPIO_ROUTELOC1 */
-#define GPIO_ROUTELOC1_ETMTD1LOC_LOC2 (_GPIO_ROUTELOC1_ETMTD1LOC_LOC2 << 14) /**< Shifted mode LOC2 for GPIO_ROUTELOC1 */
-#define GPIO_ROUTELOC1_ETMTD1LOC_LOC3 (_GPIO_ROUTELOC1_ETMTD1LOC_LOC3 << 14) /**< Shifted mode LOC3 for GPIO_ROUTELOC1 */
-#define _GPIO_ROUTELOC1_ETMTD2LOC_SHIFT 20 /**< Shift value for GPIO_ETMTD2LOC */
-#define _GPIO_ROUTELOC1_ETMTD2LOC_MASK 0x300000UL /**< Bit mask for GPIO_ETMTD2LOC */
-#define _GPIO_ROUTELOC1_ETMTD2LOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC1 */
-#define _GPIO_ROUTELOC1_ETMTD2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC1 */
-#define _GPIO_ROUTELOC1_ETMTD2LOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC1 */
-#define _GPIO_ROUTELOC1_ETMTD2LOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC1 */
-#define _GPIO_ROUTELOC1_ETMTD2LOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC1 */
-#define GPIO_ROUTELOC1_ETMTD2LOC_LOC0 (_GPIO_ROUTELOC1_ETMTD2LOC_LOC0 << 20) /**< Shifted mode LOC0 for GPIO_ROUTELOC1 */
-#define GPIO_ROUTELOC1_ETMTD2LOC_DEFAULT (_GPIO_ROUTELOC1_ETMTD2LOC_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_ROUTELOC1 */
-#define GPIO_ROUTELOC1_ETMTD2LOC_LOC1 (_GPIO_ROUTELOC1_ETMTD2LOC_LOC1 << 20) /**< Shifted mode LOC1 for GPIO_ROUTELOC1 */
-#define GPIO_ROUTELOC1_ETMTD2LOC_LOC2 (_GPIO_ROUTELOC1_ETMTD2LOC_LOC2 << 20) /**< Shifted mode LOC2 for GPIO_ROUTELOC1 */
-#define GPIO_ROUTELOC1_ETMTD2LOC_LOC3 (_GPIO_ROUTELOC1_ETMTD2LOC_LOC3 << 20) /**< Shifted mode LOC3 for GPIO_ROUTELOC1 */
-#define _GPIO_ROUTELOC1_ETMTD3LOC_SHIFT 26 /**< Shift value for GPIO_ETMTD3LOC */
-#define _GPIO_ROUTELOC1_ETMTD3LOC_MASK 0xC000000UL /**< Bit mask for GPIO_ETMTD3LOC */
-#define _GPIO_ROUTELOC1_ETMTD3LOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC1 */
-#define _GPIO_ROUTELOC1_ETMTD3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC1 */
-#define _GPIO_ROUTELOC1_ETMTD3LOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC1 */
-#define _GPIO_ROUTELOC1_ETMTD3LOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC1 */
-#define _GPIO_ROUTELOC1_ETMTD3LOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC1 */
-#define GPIO_ROUTELOC1_ETMTD3LOC_LOC0 (_GPIO_ROUTELOC1_ETMTD3LOC_LOC0 << 26) /**< Shifted mode LOC0 for GPIO_ROUTELOC1 */
-#define GPIO_ROUTELOC1_ETMTD3LOC_DEFAULT (_GPIO_ROUTELOC1_ETMTD3LOC_DEFAULT << 26) /**< Shifted mode DEFAULT for GPIO_ROUTELOC1 */
-#define GPIO_ROUTELOC1_ETMTD3LOC_LOC1 (_GPIO_ROUTELOC1_ETMTD3LOC_LOC1 << 26) /**< Shifted mode LOC1 for GPIO_ROUTELOC1 */
-#define GPIO_ROUTELOC1_ETMTD3LOC_LOC2 (_GPIO_ROUTELOC1_ETMTD3LOC_LOC2 << 26) /**< Shifted mode LOC2 for GPIO_ROUTELOC1 */
-#define GPIO_ROUTELOC1_ETMTD3LOC_LOC3 (_GPIO_ROUTELOC1_ETMTD3LOC_LOC3 << 26) /**< Shifted mode LOC3 for GPIO_ROUTELOC1 */
-
-/* Bit fields for GPIO INSENSE */
-#define _GPIO_INSENSE_RESETVALUE 0x00000003UL /**< Default value for GPIO_INSENSE */
-#define _GPIO_INSENSE_MASK 0x00000003UL /**< Mask for GPIO_INSENSE */
-#define GPIO_INSENSE_INT (0x1UL << 0) /**< Interrupt Sense Enable */
-#define _GPIO_INSENSE_INT_SHIFT 0 /**< Shift value for GPIO_INT */
-#define _GPIO_INSENSE_INT_MASK 0x1UL /**< Bit mask for GPIO_INT */
-#define _GPIO_INSENSE_INT_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_INSENSE */
-#define GPIO_INSENSE_INT_DEFAULT (_GPIO_INSENSE_INT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_INSENSE */
-#define GPIO_INSENSE_EM4WU (0x1UL << 1) /**< EM4WU Interrupt Sense Enable */
-#define _GPIO_INSENSE_EM4WU_SHIFT 1 /**< Shift value for GPIO_EM4WU */
-#define _GPIO_INSENSE_EM4WU_MASK 0x2UL /**< Bit mask for GPIO_EM4WU */
-#define _GPIO_INSENSE_EM4WU_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_INSENSE */
-#define GPIO_INSENSE_EM4WU_DEFAULT (_GPIO_INSENSE_EM4WU_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_INSENSE */
-
-/* Bit fields for GPIO LOCK */
-#define _GPIO_LOCK_RESETVALUE 0x00000000UL /**< Default value for GPIO_LOCK */
-#define _GPIO_LOCK_MASK 0x0000FFFFUL /**< Mask for GPIO_LOCK */
-#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */
-#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */
-#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LOCK */
-#define _GPIO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for GPIO_LOCK */
-#define _GPIO_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_LOCK */
-#define _GPIO_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_LOCK */
-#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */
-#define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */
-#define GPIO_LOCK_LOCKKEY_LOCK (_GPIO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for GPIO_LOCK */
-#define GPIO_LOCK_LOCKKEY_UNLOCKED (_GPIO_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_LOCK */
-#define GPIO_LOCK_LOCKKEY_LOCKED (_GPIO_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_LOCK */
-#define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */
-
-/** @} */
-/** @} End of group EFR32FG13P_GPIO */
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_gpio_p.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_gpio_p.h
deleted file mode 100644
index ce11dfe0..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_gpio_p.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_gpio_p.h
- * @brief EFR32FG13P_GPIO_P register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @brief GPIO_P GPIO P Register
- * @ingroup EFR32FG13P_GPIO
- *****************************************************************************/
-typedef struct {
- __IOM uint32_t CTRL; /**< Port Control Register */
- __IOM uint32_t MODEL; /**< Port Pin Mode Low Register */
- __IOM uint32_t MODEH; /**< Port Pin Mode High Register */
- __IOM uint32_t DOUT; /**< Port Data Out Register */
- uint32_t RESERVED0[2]; /**< Reserved for future use **/
- __IOM uint32_t DOUTTGL; /**< Port Data Out Toggle Register */
- __IM uint32_t DIN; /**< Port Data in Register */
- __IOM uint32_t PINLOCKN; /**< Port Unlocked Pins Register */
- uint32_t RESERVED1[1]; /**< Reserved for future use **/
- __IOM uint32_t OVTDIS; /**< Over Voltage Disable for All Modes */
- uint32_t RESERVED2[1]; /**< Reserved future */
-} GPIO_P_TypeDef;
-
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_i2c.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_i2c.h
deleted file mode 100644
index 7051983e..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_i2c.h
+++ /dev/null
@@ -1,930 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_i2c.h
- * @brief EFR32FG13P_I2C register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P_I2C I2C
- * @{
- * @brief EFR32FG13P_I2C Register Declaration
- *****************************************************************************/
-/** I2C Register Declaration */
-typedef struct {
- __IOM uint32_t CTRL; /**< Control Register */
- __IOM uint32_t CMD; /**< Command Register */
- __IM uint32_t STATE; /**< State Register */
- __IM uint32_t STATUS; /**< Status Register */
- __IOM uint32_t CLKDIV; /**< Clock Division Register */
- __IOM uint32_t SADDR; /**< Slave Address Register */
- __IOM uint32_t SADDRMASK; /**< Slave Address Mask Register */
- __IM uint32_t RXDATA; /**< Receive Buffer Data Register */
- __IM uint32_t RXDOUBLE; /**< Receive Buffer Double Data Register */
- __IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */
- __IM uint32_t RXDOUBLEP; /**< Receive Buffer Double Data Peek Register */
- __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */
- __IOM uint32_t TXDOUBLE; /**< Transmit Buffer Double Data Register */
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
- __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
-} I2C_TypeDef; /** @} */
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_I2C
- * @{
- * @defgroup EFR32FG13P_I2C_BitFields I2C Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for I2C CTRL */
-#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */
-#define _I2C_CTRL_MASK 0x0007B3FFUL /**< Mask for I2C_CTRL */
-#define I2C_CTRL_EN (0x1UL << 0) /**< I2C Enable */
-#define _I2C_CTRL_EN_SHIFT 0 /**< Shift value for I2C_EN */
-#define _I2C_CTRL_EN_MASK 0x1UL /**< Bit mask for I2C_EN */
-#define _I2C_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
-#define I2C_CTRL_EN_DEFAULT (_I2C_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */
-#define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Slave */
-#define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */
-#define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */
-#define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
-#define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */
-#define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */
-#define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */
-#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */
-#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
-#define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */
-#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP When Empty */
-#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */
-#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */
-#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
-#define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */
-#define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */
-#define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */
-#define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */
-#define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
-#define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */
-#define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */
-#define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */
-#define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */
-#define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
-#define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */
-#define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */
-#define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */
-#define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */
-#define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
-#define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */
-#define I2C_CTRL_TXBIL (0x1UL << 7) /**< TX Buffer Interrupt Level */
-#define _I2C_CTRL_TXBIL_SHIFT 7 /**< Shift value for I2C_TXBIL */
-#define _I2C_CTRL_TXBIL_MASK 0x80UL /**< Bit mask for I2C_TXBIL */
-#define _I2C_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
-#define _I2C_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for I2C_CTRL */
-#define _I2C_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for I2C_CTRL */
-#define I2C_CTRL_TXBIL_DEFAULT (_I2C_CTRL_TXBIL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CTRL */
-#define I2C_CTRL_TXBIL_EMPTY (_I2C_CTRL_TXBIL_EMPTY << 7) /**< Shifted mode EMPTY for I2C_CTRL */
-#define I2C_CTRL_TXBIL_HALFFULL (_I2C_CTRL_TXBIL_HALFFULL << 7) /**< Shifted mode HALFFULL for I2C_CTRL */
-#define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */
-#define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */
-#define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
-#define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */
-#define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */
-#define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */
-#define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */
-#define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */
-#define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */
-#define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */
-#define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */
-#define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */
-#define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
-#define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */
-#define _I2C_CTRL_BITO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */
-#define _I2C_CTRL_BITO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */
-#define _I2C_CTRL_BITO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */
-#define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */
-#define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */
-#define I2C_CTRL_BITO_40PCC (_I2C_CTRL_BITO_40PCC << 12) /**< Shifted mode 40PCC for I2C_CTRL */
-#define I2C_CTRL_BITO_80PCC (_I2C_CTRL_BITO_80PCC << 12) /**< Shifted mode 80PCC for I2C_CTRL */
-#define I2C_CTRL_BITO_160PCC (_I2C_CTRL_BITO_160PCC << 12) /**< Shifted mode 160PCC for I2C_CTRL */
-#define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */
-#define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */
-#define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */
-#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
-#define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */
-#define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */
-#define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */
-#define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
-#define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */
-#define _I2C_CTRL_CLTO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */
-#define _I2C_CTRL_CLTO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */
-#define _I2C_CTRL_CLTO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */
-#define _I2C_CTRL_CLTO_320PCC 0x00000004UL /**< Mode 320PCC for I2C_CTRL */
-#define _I2C_CTRL_CLTO_1024PCC 0x00000005UL /**< Mode 1024PCC for I2C_CTRL */
-#define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */
-#define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */
-#define I2C_CTRL_CLTO_40PCC (_I2C_CTRL_CLTO_40PCC << 16) /**< Shifted mode 40PCC for I2C_CTRL */
-#define I2C_CTRL_CLTO_80PCC (_I2C_CTRL_CLTO_80PCC << 16) /**< Shifted mode 80PCC for I2C_CTRL */
-#define I2C_CTRL_CLTO_160PCC (_I2C_CTRL_CLTO_160PCC << 16) /**< Shifted mode 160PCC for I2C_CTRL */
-#define I2C_CTRL_CLTO_320PCC (_I2C_CTRL_CLTO_320PCC << 16) /**< Shifted mode 320PCC for I2C_CTRL */
-#define I2C_CTRL_CLTO_1024PCC (_I2C_CTRL_CLTO_1024PCC << 16) /**< Shifted mode 1024PCC for I2C_CTRL */
-
-/* Bit fields for I2C CMD */
-#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */
-#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */
-#define I2C_CMD_START (0x1UL << 0) /**< Send Start Condition */
-#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */
-#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */
-#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
-#define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */
-#define I2C_CMD_STOP (0x1UL << 1) /**< Send Stop Condition */
-#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */
-#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */
-#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
-#define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */
-#define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */
-#define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */
-#define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */
-#define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
-#define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */
-#define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */
-#define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */
-#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */
-#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
-#define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */
-#define I2C_CMD_CONT (0x1UL << 4) /**< Continue Transmission */
-#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */
-#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */
-#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
-#define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */
-#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort Transmission */
-#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */
-#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */
-#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
-#define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */
-#define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */
-#define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */
-#define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */
-#define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
-#define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */
-#define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */
-#define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */
-#define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */
-#define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
-#define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */
-
-/* Bit fields for I2C STATE */
-#define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */
-#define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */
-#define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */
-#define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */
-#define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */
-#define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */
-#define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */
-#define I2C_STATE_MASTER (0x1UL << 1) /**< Master */
-#define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */
-#define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */
-#define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
-#define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */
-#define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */
-#define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */
-#define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */
-#define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
-#define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */
-#define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */
-#define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */
-#define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */
-#define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
-#define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */
-#define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */
-#define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */
-#define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */
-#define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
-#define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */
-#define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */
-#define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */
-#define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
-#define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */
-#define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */
-#define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */
-#define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */
-#define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */
-#define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */
-#define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */
-#define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */
-#define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */
-#define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */
-#define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */
-#define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */
-#define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */
-#define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */
-#define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */
-
-/* Bit fields for I2C STATUS */
-#define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */
-#define _I2C_STATUS_MASK 0x000003FFUL /**< Mask for I2C_STATUS */
-#define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */
-#define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */
-#define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */
-#define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
-#define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */
-#define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */
-#define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */
-#define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */
-#define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
-#define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */
-#define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */
-#define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */
-#define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */
-#define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
-#define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */
-#define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */
-#define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */
-#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */
-#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
-#define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */
-#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending Continue */
-#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */
-#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */
-#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
-#define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */
-#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending Abort */
-#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */
-#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */
-#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
-#define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */
-#define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */
-#define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */
-#define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */
-#define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
-#define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */
-#define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */
-#define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */
-#define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */
-#define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */
-#define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */
-#define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */
-#define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */
-#define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */
-#define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
-#define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */
-#define I2C_STATUS_RXFULL (0x1UL << 9) /**< RX FIFO Full */
-#define _I2C_STATUS_RXFULL_SHIFT 9 /**< Shift value for I2C_RXFULL */
-#define _I2C_STATUS_RXFULL_MASK 0x200UL /**< Bit mask for I2C_RXFULL */
-#define _I2C_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
-#define I2C_STATUS_RXFULL_DEFAULT (_I2C_STATUS_RXFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_STATUS */
-
-/* Bit fields for I2C CLKDIV */
-#define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */
-#define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */
-#define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */
-#define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */
-#define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */
-#define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */
-
-/* Bit fields for I2C SADDR */
-#define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */
-#define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */
-#define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */
-#define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */
-#define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */
-#define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */
-
-/* Bit fields for I2C SADDRMASK */
-#define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */
-#define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */
-#define _I2C_SADDRMASK_MASK_SHIFT 1 /**< Shift value for I2C_MASK */
-#define _I2C_SADDRMASK_MASK_MASK 0xFEUL /**< Bit mask for I2C_MASK */
-#define _I2C_SADDRMASK_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */
-#define I2C_SADDRMASK_MASK_DEFAULT (_I2C_SADDRMASK_MASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */
-
-/* Bit fields for I2C RXDATA */
-#define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */
-#define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */
-#define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */
-#define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */
-#define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */
-#define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */
-
-/* Bit fields for I2C RXDOUBLE */
-#define _I2C_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLE */
-#define _I2C_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLE */
-#define _I2C_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for I2C_RXDATA0 */
-#define _I2C_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for I2C_RXDATA0 */
-#define _I2C_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */
-#define I2C_RXDOUBLE_RXDATA0_DEFAULT (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */
-#define _I2C_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for I2C_RXDATA1 */
-#define _I2C_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATA1 */
-#define _I2C_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */
-#define I2C_RXDOUBLE_RXDATA1_DEFAULT (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */
-
-/* Bit fields for I2C RXDATAP */
-#define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */
-#define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */
-#define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */
-#define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */
-#define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */
-#define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */
-
-/* Bit fields for I2C RXDOUBLEP */
-#define _I2C_RXDOUBLEP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLEP */
-#define _I2C_RXDOUBLEP_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLEP */
-#define _I2C_RXDOUBLEP_RXDATAP0_SHIFT 0 /**< Shift value for I2C_RXDATAP0 */
-#define _I2C_RXDOUBLEP_RXDATAP0_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP0 */
-#define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */
-#define I2C_RXDOUBLEP_RXDATAP0_DEFAULT (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */
-#define _I2C_RXDOUBLEP_RXDATAP1_SHIFT 8 /**< Shift value for I2C_RXDATAP1 */
-#define _I2C_RXDOUBLEP_RXDATAP1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATAP1 */
-#define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */
-#define I2C_RXDOUBLEP_RXDATAP1_DEFAULT (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */
-
-/* Bit fields for I2C TXDATA */
-#define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */
-#define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */
-#define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */
-#define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */
-#define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */
-#define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */
-
-/* Bit fields for I2C TXDOUBLE */
-#define _I2C_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDOUBLE */
-#define _I2C_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_TXDOUBLE */
-#define _I2C_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for I2C_TXDATA0 */
-#define _I2C_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for I2C_TXDATA0 */
-#define _I2C_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */
-#define I2C_TXDOUBLE_TXDATA0_DEFAULT (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */
-#define _I2C_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for I2C_TXDATA1 */
-#define _I2C_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_TXDATA1 */
-#define _I2C_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */
-#define I2C_TXDOUBLE_TXDATA1_DEFAULT (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */
-
-/* Bit fields for I2C IF */
-#define _I2C_IF_RESETVALUE 0x00000010UL /**< Default value for I2C_IF */
-#define _I2C_IF_MASK 0x0007FFFFUL /**< Mask for I2C_IF */
-#define I2C_IF_START (0x1UL << 0) /**< START Condition Interrupt Flag */
-#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */
-#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */
-#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
-#define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */
-#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START Condition Interrupt Flag */
-#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
-#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
-#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
-#define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */
-#define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */
-#define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
-#define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
-#define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
-#define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */
-#define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */
-#define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
-#define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
-#define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
-#define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */
-#define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */
-#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
-#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
-#define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
-#define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */
-#define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */
-#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
-#define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */
-#define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
-#define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */
-#define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */
-#define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
-#define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
-#define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
-#define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */
-#define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */
-#define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
-#define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
-#define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
-#define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */
-#define I2C_IF_MSTOP (0x1UL << 8) /**< Master STOP Condition Interrupt Flag */
-#define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
-#define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
-#define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
-#define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */
-#define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */
-#define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
-#define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
-#define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
-#define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */
-#define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */
-#define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
-#define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
-#define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
-#define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */
-#define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */
-#define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
-#define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
-#define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
-#define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */
-#define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */
-#define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
-#define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
-#define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
-#define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */
-#define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */
-#define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
-#define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
-#define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
-#define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */
-#define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */
-#define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
-#define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
-#define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
-#define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */
-#define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */
-#define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
-#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
-#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
-#define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */
-#define I2C_IF_SSTOP (0x1UL << 16) /**< Slave STOP Condition Interrupt Flag */
-#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
-#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
-#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
-#define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */
-#define I2C_IF_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */
-#define _I2C_IF_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
-#define _I2C_IF_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
-#define _I2C_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
-#define I2C_IF_RXFULL_DEFAULT (_I2C_IF_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IF */
-#define I2C_IF_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */
-#define _I2C_IF_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
-#define _I2C_IF_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
-#define _I2C_IF_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
-#define I2C_IF_CLERR_DEFAULT (_I2C_IF_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IF */
-
-/* Bit fields for I2C IFS */
-#define _I2C_IFS_RESETVALUE 0x00000000UL /**< Default value for I2C_IFS */
-#define _I2C_IFS_MASK 0x0007FFCFUL /**< Mask for I2C_IFS */
-#define I2C_IFS_START (0x1UL << 0) /**< Set START Interrupt Flag */
-#define _I2C_IFS_START_SHIFT 0 /**< Shift value for I2C_START */
-#define _I2C_IFS_START_MASK 0x1UL /**< Bit mask for I2C_START */
-#define _I2C_IFS_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
-#define I2C_IFS_START_DEFAULT (_I2C_IFS_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFS */
-#define I2C_IFS_RSTART (0x1UL << 1) /**< Set RSTART Interrupt Flag */
-#define _I2C_IFS_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
-#define _I2C_IFS_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
-#define _I2C_IFS_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
-#define I2C_IFS_RSTART_DEFAULT (_I2C_IFS_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFS */
-#define I2C_IFS_ADDR (0x1UL << 2) /**< Set ADDR Interrupt Flag */
-#define _I2C_IFS_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
-#define _I2C_IFS_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
-#define _I2C_IFS_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
-#define I2C_IFS_ADDR_DEFAULT (_I2C_IFS_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFS */
-#define I2C_IFS_TXC (0x1UL << 3) /**< Set TXC Interrupt Flag */
-#define _I2C_IFS_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
-#define _I2C_IFS_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
-#define _I2C_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
-#define I2C_IFS_TXC_DEFAULT (_I2C_IFS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFS */
-#define I2C_IFS_ACK (0x1UL << 6) /**< Set ACK Interrupt Flag */
-#define _I2C_IFS_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
-#define _I2C_IFS_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
-#define _I2C_IFS_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
-#define I2C_IFS_ACK_DEFAULT (_I2C_IFS_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFS */
-#define I2C_IFS_NACK (0x1UL << 7) /**< Set NACK Interrupt Flag */
-#define _I2C_IFS_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
-#define _I2C_IFS_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
-#define _I2C_IFS_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
-#define I2C_IFS_NACK_DEFAULT (_I2C_IFS_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFS */
-#define I2C_IFS_MSTOP (0x1UL << 8) /**< Set MSTOP Interrupt Flag */
-#define _I2C_IFS_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
-#define _I2C_IFS_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
-#define _I2C_IFS_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
-#define I2C_IFS_MSTOP_DEFAULT (_I2C_IFS_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFS */
-#define I2C_IFS_ARBLOST (0x1UL << 9) /**< Set ARBLOST Interrupt Flag */
-#define _I2C_IFS_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
-#define _I2C_IFS_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
-#define _I2C_IFS_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
-#define I2C_IFS_ARBLOST_DEFAULT (_I2C_IFS_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFS */
-#define I2C_IFS_BUSERR (0x1UL << 10) /**< Set BUSERR Interrupt Flag */
-#define _I2C_IFS_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
-#define _I2C_IFS_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
-#define _I2C_IFS_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
-#define I2C_IFS_BUSERR_DEFAULT (_I2C_IFS_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFS */
-#define I2C_IFS_BUSHOLD (0x1UL << 11) /**< Set BUSHOLD Interrupt Flag */
-#define _I2C_IFS_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
-#define _I2C_IFS_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
-#define _I2C_IFS_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
-#define I2C_IFS_BUSHOLD_DEFAULT (_I2C_IFS_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFS */
-#define I2C_IFS_TXOF (0x1UL << 12) /**< Set TXOF Interrupt Flag */
-#define _I2C_IFS_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
-#define _I2C_IFS_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
-#define _I2C_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
-#define I2C_IFS_TXOF_DEFAULT (_I2C_IFS_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFS */
-#define I2C_IFS_RXUF (0x1UL << 13) /**< Set RXUF Interrupt Flag */
-#define _I2C_IFS_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
-#define _I2C_IFS_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
-#define _I2C_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
-#define I2C_IFS_RXUF_DEFAULT (_I2C_IFS_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFS */
-#define I2C_IFS_BITO (0x1UL << 14) /**< Set BITO Interrupt Flag */
-#define _I2C_IFS_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
-#define _I2C_IFS_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
-#define _I2C_IFS_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
-#define I2C_IFS_BITO_DEFAULT (_I2C_IFS_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFS */
-#define I2C_IFS_CLTO (0x1UL << 15) /**< Set CLTO Interrupt Flag */
-#define _I2C_IFS_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
-#define _I2C_IFS_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
-#define _I2C_IFS_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
-#define I2C_IFS_CLTO_DEFAULT (_I2C_IFS_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFS */
-#define I2C_IFS_SSTOP (0x1UL << 16) /**< Set SSTOP Interrupt Flag */
-#define _I2C_IFS_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
-#define _I2C_IFS_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
-#define _I2C_IFS_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
-#define I2C_IFS_SSTOP_DEFAULT (_I2C_IFS_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFS */
-#define I2C_IFS_RXFULL (0x1UL << 17) /**< Set RXFULL Interrupt Flag */
-#define _I2C_IFS_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
-#define _I2C_IFS_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
-#define _I2C_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
-#define I2C_IFS_RXFULL_DEFAULT (_I2C_IFS_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IFS */
-#define I2C_IFS_CLERR (0x1UL << 18) /**< Set CLERR Interrupt Flag */
-#define _I2C_IFS_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
-#define _I2C_IFS_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
-#define _I2C_IFS_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
-#define I2C_IFS_CLERR_DEFAULT (_I2C_IFS_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IFS */
-
-/* Bit fields for I2C IFC */
-#define _I2C_IFC_RESETVALUE 0x00000000UL /**< Default value for I2C_IFC */
-#define _I2C_IFC_MASK 0x0007FFCFUL /**< Mask for I2C_IFC */
-#define I2C_IFC_START (0x1UL << 0) /**< Clear START Interrupt Flag */
-#define _I2C_IFC_START_SHIFT 0 /**< Shift value for I2C_START */
-#define _I2C_IFC_START_MASK 0x1UL /**< Bit mask for I2C_START */
-#define _I2C_IFC_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
-#define I2C_IFC_START_DEFAULT (_I2C_IFC_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFC */
-#define I2C_IFC_RSTART (0x1UL << 1) /**< Clear RSTART Interrupt Flag */
-#define _I2C_IFC_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
-#define _I2C_IFC_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
-#define _I2C_IFC_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
-#define I2C_IFC_RSTART_DEFAULT (_I2C_IFC_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFC */
-#define I2C_IFC_ADDR (0x1UL << 2) /**< Clear ADDR Interrupt Flag */
-#define _I2C_IFC_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
-#define _I2C_IFC_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
-#define _I2C_IFC_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
-#define I2C_IFC_ADDR_DEFAULT (_I2C_IFC_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFC */
-#define I2C_IFC_TXC (0x1UL << 3) /**< Clear TXC Interrupt Flag */
-#define _I2C_IFC_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
-#define _I2C_IFC_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
-#define _I2C_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
-#define I2C_IFC_TXC_DEFAULT (_I2C_IFC_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFC */
-#define I2C_IFC_ACK (0x1UL << 6) /**< Clear ACK Interrupt Flag */
-#define _I2C_IFC_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
-#define _I2C_IFC_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
-#define _I2C_IFC_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
-#define I2C_IFC_ACK_DEFAULT (_I2C_IFC_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFC */
-#define I2C_IFC_NACK (0x1UL << 7) /**< Clear NACK Interrupt Flag */
-#define _I2C_IFC_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
-#define _I2C_IFC_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
-#define _I2C_IFC_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
-#define I2C_IFC_NACK_DEFAULT (_I2C_IFC_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFC */
-#define I2C_IFC_MSTOP (0x1UL << 8) /**< Clear MSTOP Interrupt Flag */
-#define _I2C_IFC_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
-#define _I2C_IFC_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
-#define _I2C_IFC_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
-#define I2C_IFC_MSTOP_DEFAULT (_I2C_IFC_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFC */
-#define I2C_IFC_ARBLOST (0x1UL << 9) /**< Clear ARBLOST Interrupt Flag */
-#define _I2C_IFC_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
-#define _I2C_IFC_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
-#define _I2C_IFC_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
-#define I2C_IFC_ARBLOST_DEFAULT (_I2C_IFC_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFC */
-#define I2C_IFC_BUSERR (0x1UL << 10) /**< Clear BUSERR Interrupt Flag */
-#define _I2C_IFC_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
-#define _I2C_IFC_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
-#define _I2C_IFC_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
-#define I2C_IFC_BUSERR_DEFAULT (_I2C_IFC_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFC */
-#define I2C_IFC_BUSHOLD (0x1UL << 11) /**< Clear BUSHOLD Interrupt Flag */
-#define _I2C_IFC_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
-#define _I2C_IFC_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
-#define _I2C_IFC_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
-#define I2C_IFC_BUSHOLD_DEFAULT (_I2C_IFC_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFC */
-#define I2C_IFC_TXOF (0x1UL << 12) /**< Clear TXOF Interrupt Flag */
-#define _I2C_IFC_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
-#define _I2C_IFC_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
-#define _I2C_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
-#define I2C_IFC_TXOF_DEFAULT (_I2C_IFC_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFC */
-#define I2C_IFC_RXUF (0x1UL << 13) /**< Clear RXUF Interrupt Flag */
-#define _I2C_IFC_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
-#define _I2C_IFC_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
-#define _I2C_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
-#define I2C_IFC_RXUF_DEFAULT (_I2C_IFC_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFC */
-#define I2C_IFC_BITO (0x1UL << 14) /**< Clear BITO Interrupt Flag */
-#define _I2C_IFC_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
-#define _I2C_IFC_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
-#define _I2C_IFC_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
-#define I2C_IFC_BITO_DEFAULT (_I2C_IFC_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFC */
-#define I2C_IFC_CLTO (0x1UL << 15) /**< Clear CLTO Interrupt Flag */
-#define _I2C_IFC_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
-#define _I2C_IFC_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
-#define _I2C_IFC_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
-#define I2C_IFC_CLTO_DEFAULT (_I2C_IFC_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFC */
-#define I2C_IFC_SSTOP (0x1UL << 16) /**< Clear SSTOP Interrupt Flag */
-#define _I2C_IFC_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
-#define _I2C_IFC_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
-#define _I2C_IFC_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
-#define I2C_IFC_SSTOP_DEFAULT (_I2C_IFC_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFC */
-#define I2C_IFC_RXFULL (0x1UL << 17) /**< Clear RXFULL Interrupt Flag */
-#define _I2C_IFC_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
-#define _I2C_IFC_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
-#define _I2C_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
-#define I2C_IFC_RXFULL_DEFAULT (_I2C_IFC_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IFC */
-#define I2C_IFC_CLERR (0x1UL << 18) /**< Clear CLERR Interrupt Flag */
-#define _I2C_IFC_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
-#define _I2C_IFC_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
-#define _I2C_IFC_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
-#define I2C_IFC_CLERR_DEFAULT (_I2C_IFC_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IFC */
-
-/* Bit fields for I2C IEN */
-#define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */
-#define _I2C_IEN_MASK 0x0007FFFFUL /**< Mask for I2C_IEN */
-#define I2C_IEN_START (0x1UL << 0) /**< START Interrupt Enable */
-#define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */
-#define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */
-#define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
-#define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */
-#define I2C_IEN_RSTART (0x1UL << 1) /**< RSTART Interrupt Enable */
-#define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
-#define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
-#define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
-#define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */
-#define I2C_IEN_ADDR (0x1UL << 2) /**< ADDR Interrupt Enable */
-#define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
-#define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
-#define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
-#define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */
-#define I2C_IEN_TXC (0x1UL << 3) /**< TXC Interrupt Enable */
-#define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
-#define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
-#define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
-#define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */
-#define I2C_IEN_TXBL (0x1UL << 4) /**< TXBL Interrupt Enable */
-#define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
-#define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
-#define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
-#define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */
-#define I2C_IEN_RXDATAV (0x1UL << 5) /**< RXDATAV Interrupt Enable */
-#define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
-#define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */
-#define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
-#define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */
-#define I2C_IEN_ACK (0x1UL << 6) /**< ACK Interrupt Enable */
-#define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
-#define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
-#define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
-#define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */
-#define I2C_IEN_NACK (0x1UL << 7) /**< NACK Interrupt Enable */
-#define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
-#define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
-#define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
-#define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */
-#define I2C_IEN_MSTOP (0x1UL << 8) /**< MSTOP Interrupt Enable */
-#define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
-#define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
-#define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
-#define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */
-#define I2C_IEN_ARBLOST (0x1UL << 9) /**< ARBLOST Interrupt Enable */
-#define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
-#define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
-#define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
-#define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */
-#define I2C_IEN_BUSERR (0x1UL << 10) /**< BUSERR Interrupt Enable */
-#define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
-#define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
-#define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
-#define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */
-#define I2C_IEN_BUSHOLD (0x1UL << 11) /**< BUSHOLD Interrupt Enable */
-#define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
-#define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
-#define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
-#define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */
-#define I2C_IEN_TXOF (0x1UL << 12) /**< TXOF Interrupt Enable */
-#define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
-#define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
-#define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
-#define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */
-#define I2C_IEN_RXUF (0x1UL << 13) /**< RXUF Interrupt Enable */
-#define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
-#define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
-#define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
-#define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */
-#define I2C_IEN_BITO (0x1UL << 14) /**< BITO Interrupt Enable */
-#define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
-#define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
-#define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
-#define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */
-#define I2C_IEN_CLTO (0x1UL << 15) /**< CLTO Interrupt Enable */
-#define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
-#define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
-#define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
-#define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */
-#define I2C_IEN_SSTOP (0x1UL << 16) /**< SSTOP Interrupt Enable */
-#define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
-#define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
-#define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
-#define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */
-#define I2C_IEN_RXFULL (0x1UL << 17) /**< RXFULL Interrupt Enable */
-#define _I2C_IEN_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
-#define _I2C_IEN_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
-#define _I2C_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
-#define I2C_IEN_RXFULL_DEFAULT (_I2C_IEN_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IEN */
-#define I2C_IEN_CLERR (0x1UL << 18) /**< CLERR Interrupt Enable */
-#define _I2C_IEN_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
-#define _I2C_IEN_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
-#define _I2C_IEN_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
-#define I2C_IEN_CLERR_DEFAULT (_I2C_IEN_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IEN */
-
-/* Bit fields for I2C ROUTEPEN */
-#define _I2C_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTEPEN */
-#define _I2C_ROUTEPEN_MASK 0x00000003UL /**< Mask for I2C_ROUTEPEN */
-#define I2C_ROUTEPEN_SDAPEN (0x1UL << 0) /**< SDA Pin Enable */
-#define _I2C_ROUTEPEN_SDAPEN_SHIFT 0 /**< Shift value for I2C_SDAPEN */
-#define _I2C_ROUTEPEN_SDAPEN_MASK 0x1UL /**< Bit mask for I2C_SDAPEN */
-#define _I2C_ROUTEPEN_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTEPEN */
-#define I2C_ROUTEPEN_SDAPEN_DEFAULT (_I2C_ROUTEPEN_SDAPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */
-#define I2C_ROUTEPEN_SCLPEN (0x1UL << 1) /**< SCL Pin Enable */
-#define _I2C_ROUTEPEN_SCLPEN_SHIFT 1 /**< Shift value for I2C_SCLPEN */
-#define _I2C_ROUTEPEN_SCLPEN_MASK 0x2UL /**< Bit mask for I2C_SCLPEN */
-#define _I2C_ROUTEPEN_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTEPEN */
-#define I2C_ROUTEPEN_SCLPEN_DEFAULT (_I2C_ROUTEPEN_SCLPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */
-
-/* Bit fields for I2C ROUTELOC0 */
-#define _I2C_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_SHIFT 0 /**< Shift value for I2C_SDALOC */
-#define _I2C_ROUTELOC0_SDALOC_MASK 0x1FUL /**< Bit mask for I2C_SDALOC */
-#define _I2C_ROUTELOC0_SDALOC_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_LOC7 0x00000007UL /**< Mode LOC7 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_LOC8 0x00000008UL /**< Mode LOC8 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_LOC9 0x00000009UL /**< Mode LOC9 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_LOC10 0x0000000AUL /**< Mode LOC10 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_LOC11 0x0000000BUL /**< Mode LOC11 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_LOC12 0x0000000CUL /**< Mode LOC12 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_LOC13 0x0000000DUL /**< Mode LOC13 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_LOC14 0x0000000EUL /**< Mode LOC14 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_LOC15 0x0000000FUL /**< Mode LOC15 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_LOC16 0x00000010UL /**< Mode LOC16 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_LOC17 0x00000011UL /**< Mode LOC17 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_LOC18 0x00000012UL /**< Mode LOC18 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_LOC19 0x00000013UL /**< Mode LOC19 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_LOC20 0x00000014UL /**< Mode LOC20 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_LOC21 0x00000015UL /**< Mode LOC21 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_LOC22 0x00000016UL /**< Mode LOC22 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_LOC23 0x00000017UL /**< Mode LOC23 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_LOC24 0x00000018UL /**< Mode LOC24 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_LOC25 0x00000019UL /**< Mode LOC25 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_LOC26 0x0000001AUL /**< Mode LOC26 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_LOC27 0x0000001BUL /**< Mode LOC27 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_LOC28 0x0000001CUL /**< Mode LOC28 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_LOC29 0x0000001DUL /**< Mode LOC29 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_LOC30 0x0000001EUL /**< Mode LOC30 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SDALOC_LOC31 0x0000001FUL /**< Mode LOC31 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC0 (_I2C_ROUTELOC0_SDALOC_LOC0 << 0) /**< Shifted mode LOC0 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_DEFAULT (_I2C_ROUTELOC0_SDALOC_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC1 (_I2C_ROUTELOC0_SDALOC_LOC1 << 0) /**< Shifted mode LOC1 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC2 (_I2C_ROUTELOC0_SDALOC_LOC2 << 0) /**< Shifted mode LOC2 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC3 (_I2C_ROUTELOC0_SDALOC_LOC3 << 0) /**< Shifted mode LOC3 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC4 (_I2C_ROUTELOC0_SDALOC_LOC4 << 0) /**< Shifted mode LOC4 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC5 (_I2C_ROUTELOC0_SDALOC_LOC5 << 0) /**< Shifted mode LOC5 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC6 (_I2C_ROUTELOC0_SDALOC_LOC6 << 0) /**< Shifted mode LOC6 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC7 (_I2C_ROUTELOC0_SDALOC_LOC7 << 0) /**< Shifted mode LOC7 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC8 (_I2C_ROUTELOC0_SDALOC_LOC8 << 0) /**< Shifted mode LOC8 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC9 (_I2C_ROUTELOC0_SDALOC_LOC9 << 0) /**< Shifted mode LOC9 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC10 (_I2C_ROUTELOC0_SDALOC_LOC10 << 0) /**< Shifted mode LOC10 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC11 (_I2C_ROUTELOC0_SDALOC_LOC11 << 0) /**< Shifted mode LOC11 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC12 (_I2C_ROUTELOC0_SDALOC_LOC12 << 0) /**< Shifted mode LOC12 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC13 (_I2C_ROUTELOC0_SDALOC_LOC13 << 0) /**< Shifted mode LOC13 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC14 (_I2C_ROUTELOC0_SDALOC_LOC14 << 0) /**< Shifted mode LOC14 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC15 (_I2C_ROUTELOC0_SDALOC_LOC15 << 0) /**< Shifted mode LOC15 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC16 (_I2C_ROUTELOC0_SDALOC_LOC16 << 0) /**< Shifted mode LOC16 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC17 (_I2C_ROUTELOC0_SDALOC_LOC17 << 0) /**< Shifted mode LOC17 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC18 (_I2C_ROUTELOC0_SDALOC_LOC18 << 0) /**< Shifted mode LOC18 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC19 (_I2C_ROUTELOC0_SDALOC_LOC19 << 0) /**< Shifted mode LOC19 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC20 (_I2C_ROUTELOC0_SDALOC_LOC20 << 0) /**< Shifted mode LOC20 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC21 (_I2C_ROUTELOC0_SDALOC_LOC21 << 0) /**< Shifted mode LOC21 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC22 (_I2C_ROUTELOC0_SDALOC_LOC22 << 0) /**< Shifted mode LOC22 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC23 (_I2C_ROUTELOC0_SDALOC_LOC23 << 0) /**< Shifted mode LOC23 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC24 (_I2C_ROUTELOC0_SDALOC_LOC24 << 0) /**< Shifted mode LOC24 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC25 (_I2C_ROUTELOC0_SDALOC_LOC25 << 0) /**< Shifted mode LOC25 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC26 (_I2C_ROUTELOC0_SDALOC_LOC26 << 0) /**< Shifted mode LOC26 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC27 (_I2C_ROUTELOC0_SDALOC_LOC27 << 0) /**< Shifted mode LOC27 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC28 (_I2C_ROUTELOC0_SDALOC_LOC28 << 0) /**< Shifted mode LOC28 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC29 (_I2C_ROUTELOC0_SDALOC_LOC29 << 0) /**< Shifted mode LOC29 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC30 (_I2C_ROUTELOC0_SDALOC_LOC30 << 0) /**< Shifted mode LOC30 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SDALOC_LOC31 (_I2C_ROUTELOC0_SDALOC_LOC31 << 0) /**< Shifted mode LOC31 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_SHIFT 8 /**< Shift value for I2C_SCLLOC */
-#define _I2C_ROUTELOC0_SCLLOC_MASK 0x1F00UL /**< Bit mask for I2C_SCLLOC */
-#define _I2C_ROUTELOC0_SCLLOC_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_LOC7 0x00000007UL /**< Mode LOC7 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_LOC8 0x00000008UL /**< Mode LOC8 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_LOC9 0x00000009UL /**< Mode LOC9 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_LOC10 0x0000000AUL /**< Mode LOC10 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_LOC11 0x0000000BUL /**< Mode LOC11 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_LOC12 0x0000000CUL /**< Mode LOC12 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_LOC13 0x0000000DUL /**< Mode LOC13 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_LOC14 0x0000000EUL /**< Mode LOC14 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_LOC15 0x0000000FUL /**< Mode LOC15 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_LOC16 0x00000010UL /**< Mode LOC16 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_LOC17 0x00000011UL /**< Mode LOC17 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_LOC18 0x00000012UL /**< Mode LOC18 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_LOC19 0x00000013UL /**< Mode LOC19 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_LOC20 0x00000014UL /**< Mode LOC20 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_LOC21 0x00000015UL /**< Mode LOC21 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_LOC22 0x00000016UL /**< Mode LOC22 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_LOC23 0x00000017UL /**< Mode LOC23 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_LOC24 0x00000018UL /**< Mode LOC24 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_LOC25 0x00000019UL /**< Mode LOC25 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_LOC26 0x0000001AUL /**< Mode LOC26 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_LOC27 0x0000001BUL /**< Mode LOC27 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_LOC28 0x0000001CUL /**< Mode LOC28 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_LOC29 0x0000001DUL /**< Mode LOC29 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_LOC30 0x0000001EUL /**< Mode LOC30 for I2C_ROUTELOC0 */
-#define _I2C_ROUTELOC0_SCLLOC_LOC31 0x0000001FUL /**< Mode LOC31 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC0 (_I2C_ROUTELOC0_SCLLOC_LOC0 << 8) /**< Shifted mode LOC0 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_DEFAULT (_I2C_ROUTELOC0_SCLLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC1 (_I2C_ROUTELOC0_SCLLOC_LOC1 << 8) /**< Shifted mode LOC1 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC2 (_I2C_ROUTELOC0_SCLLOC_LOC2 << 8) /**< Shifted mode LOC2 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC3 (_I2C_ROUTELOC0_SCLLOC_LOC3 << 8) /**< Shifted mode LOC3 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC4 (_I2C_ROUTELOC0_SCLLOC_LOC4 << 8) /**< Shifted mode LOC4 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC5 (_I2C_ROUTELOC0_SCLLOC_LOC5 << 8) /**< Shifted mode LOC5 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC6 (_I2C_ROUTELOC0_SCLLOC_LOC6 << 8) /**< Shifted mode LOC6 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC7 (_I2C_ROUTELOC0_SCLLOC_LOC7 << 8) /**< Shifted mode LOC7 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC8 (_I2C_ROUTELOC0_SCLLOC_LOC8 << 8) /**< Shifted mode LOC8 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC9 (_I2C_ROUTELOC0_SCLLOC_LOC9 << 8) /**< Shifted mode LOC9 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC10 (_I2C_ROUTELOC0_SCLLOC_LOC10 << 8) /**< Shifted mode LOC10 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC11 (_I2C_ROUTELOC0_SCLLOC_LOC11 << 8) /**< Shifted mode LOC11 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC12 (_I2C_ROUTELOC0_SCLLOC_LOC12 << 8) /**< Shifted mode LOC12 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC13 (_I2C_ROUTELOC0_SCLLOC_LOC13 << 8) /**< Shifted mode LOC13 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC14 (_I2C_ROUTELOC0_SCLLOC_LOC14 << 8) /**< Shifted mode LOC14 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC15 (_I2C_ROUTELOC0_SCLLOC_LOC15 << 8) /**< Shifted mode LOC15 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC16 (_I2C_ROUTELOC0_SCLLOC_LOC16 << 8) /**< Shifted mode LOC16 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC17 (_I2C_ROUTELOC0_SCLLOC_LOC17 << 8) /**< Shifted mode LOC17 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC18 (_I2C_ROUTELOC0_SCLLOC_LOC18 << 8) /**< Shifted mode LOC18 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC19 (_I2C_ROUTELOC0_SCLLOC_LOC19 << 8) /**< Shifted mode LOC19 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC20 (_I2C_ROUTELOC0_SCLLOC_LOC20 << 8) /**< Shifted mode LOC20 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC21 (_I2C_ROUTELOC0_SCLLOC_LOC21 << 8) /**< Shifted mode LOC21 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC22 (_I2C_ROUTELOC0_SCLLOC_LOC22 << 8) /**< Shifted mode LOC22 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC23 (_I2C_ROUTELOC0_SCLLOC_LOC23 << 8) /**< Shifted mode LOC23 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC24 (_I2C_ROUTELOC0_SCLLOC_LOC24 << 8) /**< Shifted mode LOC24 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC25 (_I2C_ROUTELOC0_SCLLOC_LOC25 << 8) /**< Shifted mode LOC25 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC26 (_I2C_ROUTELOC0_SCLLOC_LOC26 << 8) /**< Shifted mode LOC26 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC27 (_I2C_ROUTELOC0_SCLLOC_LOC27 << 8) /**< Shifted mode LOC27 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC28 (_I2C_ROUTELOC0_SCLLOC_LOC28 << 8) /**< Shifted mode LOC28 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC29 (_I2C_ROUTELOC0_SCLLOC_LOC29 << 8) /**< Shifted mode LOC29 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC30 (_I2C_ROUTELOC0_SCLLOC_LOC30 << 8) /**< Shifted mode LOC30 for I2C_ROUTELOC0 */
-#define I2C_ROUTELOC0_SCLLOC_LOC31 (_I2C_ROUTELOC0_SCLLOC_LOC31 << 8) /**< Shifted mode LOC31 for I2C_ROUTELOC0 */
-
-/** @} */
-/** @} End of group EFR32FG13P_I2C */
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_idac.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_idac.h
deleted file mode 100644
index 484ea772..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_idac.h
+++ /dev/null
@@ -1,336 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_idac.h
- * @brief EFR32FG13P_IDAC register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P_IDAC IDAC
- * @{
- * @brief EFR32FG13P_IDAC Register Declaration
- *****************************************************************************/
-/** IDAC Register Declaration */
-typedef struct {
- __IOM uint32_t CTRL; /**< Control Register */
- __IOM uint32_t CURPROG; /**< Current Programming Register */
- uint32_t RESERVED0[1]; /**< Reserved for future use **/
- __IOM uint32_t DUTYCONFIG; /**< Duty Cycle Configuration Register */
-
- uint32_t RESERVED1[2]; /**< Reserved for future use **/
- __IM uint32_t STATUS; /**< Status Register */
- uint32_t RESERVED2[1]; /**< Reserved for future use **/
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- uint32_t RESERVED3[1]; /**< Reserved for future use **/
- __IM uint32_t APORTREQ; /**< APORT Request Status Register */
- __IM uint32_t APORTCONFLICT; /**< APORT Request Status Register */
-} IDAC_TypeDef; /** @} */
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_IDAC
- * @{
- * @defgroup EFR32FG13P_IDAC_BitFields IDAC Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for IDAC CTRL */
-#define _IDAC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IDAC_CTRL */
-#define _IDAC_CTRL_MASK 0x00FD7FFFUL /**< Mask for IDAC_CTRL */
-#define IDAC_CTRL_EN (0x1UL << 0) /**< Current DAC Enable */
-#define _IDAC_CTRL_EN_SHIFT 0 /**< Shift value for IDAC_EN */
-#define _IDAC_CTRL_EN_MASK 0x1UL /**< Bit mask for IDAC_EN */
-#define _IDAC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
-#define IDAC_CTRL_EN_DEFAULT (_IDAC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CTRL */
-#define IDAC_CTRL_CURSINK (0x1UL << 1) /**< Current Sink Enable */
-#define _IDAC_CTRL_CURSINK_SHIFT 1 /**< Shift value for IDAC_CURSINK */
-#define _IDAC_CTRL_CURSINK_MASK 0x2UL /**< Bit mask for IDAC_CURSINK */
-#define _IDAC_CTRL_CURSINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
-#define IDAC_CTRL_CURSINK_DEFAULT (_IDAC_CTRL_CURSINK_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_CTRL */
-#define IDAC_CTRL_MINOUTTRANS (0x1UL << 2) /**< Minimum Output Transition Enable */
-#define _IDAC_CTRL_MINOUTTRANS_SHIFT 2 /**< Shift value for IDAC_MINOUTTRANS */
-#define _IDAC_CTRL_MINOUTTRANS_MASK 0x4UL /**< Bit mask for IDAC_MINOUTTRANS */
-#define _IDAC_CTRL_MINOUTTRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
-#define IDAC_CTRL_MINOUTTRANS_DEFAULT (_IDAC_CTRL_MINOUTTRANS_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTEN (0x1UL << 3) /**< APORT Output Enable */
-#define _IDAC_CTRL_APORTOUTEN_SHIFT 3 /**< Shift value for IDAC_APORTOUTEN */
-#define _IDAC_CTRL_APORTOUTEN_MASK 0x8UL /**< Bit mask for IDAC_APORTOUTEN */
-#define _IDAC_CTRL_APORTOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTEN_DEFAULT (_IDAC_CTRL_APORTOUTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_SHIFT 4 /**< Shift value for IDAC_APORTOUTSEL */
-#define _IDAC_CTRL_APORTOUTSEL_MASK 0xFF0UL /**< Bit mask for IDAC_APORTOUTSEL */
-#define _IDAC_CTRL_APORTOUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for IDAC_CTRL */
-#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_DEFAULT (_IDAC_CTRL_APORTOUTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1XCH0 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH0 << 4) /**< Shifted mode APORT1XCH0 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1YCH1 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH1 << 4) /**< Shifted mode APORT1YCH1 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1XCH2 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH2 << 4) /**< Shifted mode APORT1XCH2 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1YCH3 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH3 << 4) /**< Shifted mode APORT1YCH3 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1XCH4 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH4 << 4) /**< Shifted mode APORT1XCH4 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1YCH5 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH5 << 4) /**< Shifted mode APORT1YCH5 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1XCH6 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH6 << 4) /**< Shifted mode APORT1XCH6 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1YCH7 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH7 << 4) /**< Shifted mode APORT1YCH7 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1XCH8 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH8 << 4) /**< Shifted mode APORT1XCH8 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1YCH9 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH9 << 4) /**< Shifted mode APORT1YCH9 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1XCH10 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH10 << 4) /**< Shifted mode APORT1XCH10 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1YCH11 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH11 << 4) /**< Shifted mode APORT1YCH11 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1XCH12 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH12 << 4) /**< Shifted mode APORT1XCH12 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1YCH13 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH13 << 4) /**< Shifted mode APORT1YCH13 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1XCH14 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH14 << 4) /**< Shifted mode APORT1XCH14 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1YCH15 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH15 << 4) /**< Shifted mode APORT1YCH15 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1XCH16 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH16 << 4) /**< Shifted mode APORT1XCH16 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1YCH17 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH17 << 4) /**< Shifted mode APORT1YCH17 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1XCH18 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH18 << 4) /**< Shifted mode APORT1XCH18 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1YCH19 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH19 << 4) /**< Shifted mode APORT1YCH19 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1XCH20 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH20 << 4) /**< Shifted mode APORT1XCH20 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1YCH21 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH21 << 4) /**< Shifted mode APORT1YCH21 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1XCH22 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH22 << 4) /**< Shifted mode APORT1XCH22 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1YCH23 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH23 << 4) /**< Shifted mode APORT1YCH23 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1XCH24 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH24 << 4) /**< Shifted mode APORT1XCH24 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1YCH25 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH25 << 4) /**< Shifted mode APORT1YCH25 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1XCH26 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH26 << 4) /**< Shifted mode APORT1XCH26 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1YCH27 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH27 << 4) /**< Shifted mode APORT1YCH27 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1XCH28 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH28 << 4) /**< Shifted mode APORT1XCH28 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1YCH29 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH29 << 4) /**< Shifted mode APORT1YCH29 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1XCH30 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH30 << 4) /**< Shifted mode APORT1XCH30 for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTSEL_APORT1YCH31 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH31 << 4) /**< Shifted mode APORT1YCH31 for IDAC_CTRL */
-#define IDAC_CTRL_PWRSEL (0x1UL << 12) /**< Power Select */
-#define _IDAC_CTRL_PWRSEL_SHIFT 12 /**< Shift value for IDAC_PWRSEL */
-#define _IDAC_CTRL_PWRSEL_MASK 0x1000UL /**< Bit mask for IDAC_PWRSEL */
-#define _IDAC_CTRL_PWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
-#define _IDAC_CTRL_PWRSEL_ANA 0x00000000UL /**< Mode ANA for IDAC_CTRL */
-#define _IDAC_CTRL_PWRSEL_IO 0x00000001UL /**< Mode IO for IDAC_CTRL */
-#define IDAC_CTRL_PWRSEL_DEFAULT (_IDAC_CTRL_PWRSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for IDAC_CTRL */
-#define IDAC_CTRL_PWRSEL_ANA (_IDAC_CTRL_PWRSEL_ANA << 12) /**< Shifted mode ANA for IDAC_CTRL */
-#define IDAC_CTRL_PWRSEL_IO (_IDAC_CTRL_PWRSEL_IO << 12) /**< Shifted mode IO for IDAC_CTRL */
-#define IDAC_CTRL_EM2DELAY (0x1UL << 13) /**< EM2 Delay */
-#define _IDAC_CTRL_EM2DELAY_SHIFT 13 /**< Shift value for IDAC_EM2DELAY */
-#define _IDAC_CTRL_EM2DELAY_MASK 0x2000UL /**< Bit mask for IDAC_EM2DELAY */
-#define _IDAC_CTRL_EM2DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
-#define IDAC_CTRL_EM2DELAY_DEFAULT (_IDAC_CTRL_EM2DELAY_DEFAULT << 13) /**< Shifted mode DEFAULT for IDAC_CTRL */
-#define IDAC_CTRL_APORTMASTERDIS (0x1UL << 14) /**< APORT Bus Master Disable */
-#define _IDAC_CTRL_APORTMASTERDIS_SHIFT 14 /**< Shift value for IDAC_APORTMASTERDIS */
-#define _IDAC_CTRL_APORTMASTERDIS_MASK 0x4000UL /**< Bit mask for IDAC_APORTMASTERDIS */
-#define _IDAC_CTRL_APORTMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
-#define IDAC_CTRL_APORTMASTERDIS_DEFAULT (_IDAC_CTRL_APORTMASTERDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTENPRS (0x1UL << 16) /**< PRS Controlled APORT Output Enable */
-#define _IDAC_CTRL_APORTOUTENPRS_SHIFT 16 /**< Shift value for IDAC_APORTOUTENPRS */
-#define _IDAC_CTRL_APORTOUTENPRS_MASK 0x10000UL /**< Bit mask for IDAC_APORTOUTENPRS */
-#define _IDAC_CTRL_APORTOUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
-#define IDAC_CTRL_APORTOUTENPRS_DEFAULT (_IDAC_CTRL_APORTOUTENPRS_DEFAULT << 16) /**< Shifted mode DEFAULT for IDAC_CTRL */
-#define IDAC_CTRL_MAINOUTEN (0x1UL << 18) /**< Output Enable */
-#define _IDAC_CTRL_MAINOUTEN_SHIFT 18 /**< Shift value for IDAC_MAINOUTEN */
-#define _IDAC_CTRL_MAINOUTEN_MASK 0x40000UL /**< Bit mask for IDAC_MAINOUTEN */
-#define _IDAC_CTRL_MAINOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
-#define IDAC_CTRL_MAINOUTEN_DEFAULT (_IDAC_CTRL_MAINOUTEN_DEFAULT << 18) /**< Shifted mode DEFAULT for IDAC_CTRL */
-#define IDAC_CTRL_MAINOUTENPRS (0x1UL << 19) /**< PRS Controlled Main Pad Output Enable */
-#define _IDAC_CTRL_MAINOUTENPRS_SHIFT 19 /**< Shift value for IDAC_MAINOUTENPRS */
-#define _IDAC_CTRL_MAINOUTENPRS_MASK 0x80000UL /**< Bit mask for IDAC_MAINOUTENPRS */
-#define _IDAC_CTRL_MAINOUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
-#define IDAC_CTRL_MAINOUTENPRS_DEFAULT (_IDAC_CTRL_MAINOUTENPRS_DEFAULT << 19) /**< Shifted mode DEFAULT for IDAC_CTRL */
-#define _IDAC_CTRL_PRSSEL_SHIFT 20 /**< Shift value for IDAC_PRSSEL */
-#define _IDAC_CTRL_PRSSEL_MASK 0xF00000UL /**< Bit mask for IDAC_PRSSEL */
-#define _IDAC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
-#define _IDAC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for IDAC_CTRL */
-#define _IDAC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for IDAC_CTRL */
-#define _IDAC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for IDAC_CTRL */
-#define _IDAC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for IDAC_CTRL */
-#define _IDAC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for IDAC_CTRL */
-#define _IDAC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for IDAC_CTRL */
-#define _IDAC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for IDAC_CTRL */
-#define _IDAC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for IDAC_CTRL */
-#define _IDAC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for IDAC_CTRL */
-#define _IDAC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for IDAC_CTRL */
-#define _IDAC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for IDAC_CTRL */
-#define _IDAC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for IDAC_CTRL */
-#define IDAC_CTRL_PRSSEL_DEFAULT (_IDAC_CTRL_PRSSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for IDAC_CTRL */
-#define IDAC_CTRL_PRSSEL_PRSCH0 (_IDAC_CTRL_PRSSEL_PRSCH0 << 20) /**< Shifted mode PRSCH0 for IDAC_CTRL */
-#define IDAC_CTRL_PRSSEL_PRSCH1 (_IDAC_CTRL_PRSSEL_PRSCH1 << 20) /**< Shifted mode PRSCH1 for IDAC_CTRL */
-#define IDAC_CTRL_PRSSEL_PRSCH2 (_IDAC_CTRL_PRSSEL_PRSCH2 << 20) /**< Shifted mode PRSCH2 for IDAC_CTRL */
-#define IDAC_CTRL_PRSSEL_PRSCH3 (_IDAC_CTRL_PRSSEL_PRSCH3 << 20) /**< Shifted mode PRSCH3 for IDAC_CTRL */
-#define IDAC_CTRL_PRSSEL_PRSCH4 (_IDAC_CTRL_PRSSEL_PRSCH4 << 20) /**< Shifted mode PRSCH4 for IDAC_CTRL */
-#define IDAC_CTRL_PRSSEL_PRSCH5 (_IDAC_CTRL_PRSSEL_PRSCH5 << 20) /**< Shifted mode PRSCH5 for IDAC_CTRL */
-#define IDAC_CTRL_PRSSEL_PRSCH6 (_IDAC_CTRL_PRSSEL_PRSCH6 << 20) /**< Shifted mode PRSCH6 for IDAC_CTRL */
-#define IDAC_CTRL_PRSSEL_PRSCH7 (_IDAC_CTRL_PRSSEL_PRSCH7 << 20) /**< Shifted mode PRSCH7 for IDAC_CTRL */
-#define IDAC_CTRL_PRSSEL_PRSCH8 (_IDAC_CTRL_PRSSEL_PRSCH8 << 20) /**< Shifted mode PRSCH8 for IDAC_CTRL */
-#define IDAC_CTRL_PRSSEL_PRSCH9 (_IDAC_CTRL_PRSSEL_PRSCH9 << 20) /**< Shifted mode PRSCH9 for IDAC_CTRL */
-#define IDAC_CTRL_PRSSEL_PRSCH10 (_IDAC_CTRL_PRSSEL_PRSCH10 << 20) /**< Shifted mode PRSCH10 for IDAC_CTRL */
-#define IDAC_CTRL_PRSSEL_PRSCH11 (_IDAC_CTRL_PRSSEL_PRSCH11 << 20) /**< Shifted mode PRSCH11 for IDAC_CTRL */
-
-/* Bit fields for IDAC CURPROG */
-#define _IDAC_CURPROG_RESETVALUE 0x009B0000UL /**< Default value for IDAC_CURPROG */
-#define _IDAC_CURPROG_MASK 0x00FF1F03UL /**< Mask for IDAC_CURPROG */
-#define _IDAC_CURPROG_RANGESEL_SHIFT 0 /**< Shift value for IDAC_RANGESEL */
-#define _IDAC_CURPROG_RANGESEL_MASK 0x3UL /**< Bit mask for IDAC_RANGESEL */
-#define _IDAC_CURPROG_RANGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */
-#define _IDAC_CURPROG_RANGESEL_RANGE0 0x00000000UL /**< Mode RANGE0 for IDAC_CURPROG */
-#define _IDAC_CURPROG_RANGESEL_RANGE1 0x00000001UL /**< Mode RANGE1 for IDAC_CURPROG */
-#define _IDAC_CURPROG_RANGESEL_RANGE2 0x00000002UL /**< Mode RANGE2 for IDAC_CURPROG */
-#define _IDAC_CURPROG_RANGESEL_RANGE3 0x00000003UL /**< Mode RANGE3 for IDAC_CURPROG */
-#define IDAC_CURPROG_RANGESEL_DEFAULT (_IDAC_CURPROG_RANGESEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CURPROG */
-#define IDAC_CURPROG_RANGESEL_RANGE0 (_IDAC_CURPROG_RANGESEL_RANGE0 << 0) /**< Shifted mode RANGE0 for IDAC_CURPROG */
-#define IDAC_CURPROG_RANGESEL_RANGE1 (_IDAC_CURPROG_RANGESEL_RANGE1 << 0) /**< Shifted mode RANGE1 for IDAC_CURPROG */
-#define IDAC_CURPROG_RANGESEL_RANGE2 (_IDAC_CURPROG_RANGESEL_RANGE2 << 0) /**< Shifted mode RANGE2 for IDAC_CURPROG */
-#define IDAC_CURPROG_RANGESEL_RANGE3 (_IDAC_CURPROG_RANGESEL_RANGE3 << 0) /**< Shifted mode RANGE3 for IDAC_CURPROG */
-#define _IDAC_CURPROG_STEPSEL_SHIFT 8 /**< Shift value for IDAC_STEPSEL */
-#define _IDAC_CURPROG_STEPSEL_MASK 0x1F00UL /**< Bit mask for IDAC_STEPSEL */
-#define _IDAC_CURPROG_STEPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */
-#define IDAC_CURPROG_STEPSEL_DEFAULT (_IDAC_CURPROG_STEPSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for IDAC_CURPROG */
-#define _IDAC_CURPROG_TUNING_SHIFT 16 /**< Shift value for IDAC_TUNING */
-#define _IDAC_CURPROG_TUNING_MASK 0xFF0000UL /**< Bit mask for IDAC_TUNING */
-#define _IDAC_CURPROG_TUNING_DEFAULT 0x0000009BUL /**< Mode DEFAULT for IDAC_CURPROG */
-#define IDAC_CURPROG_TUNING_DEFAULT (_IDAC_CURPROG_TUNING_DEFAULT << 16) /**< Shifted mode DEFAULT for IDAC_CURPROG */
-
-/* Bit fields for IDAC DUTYCONFIG */
-#define _IDAC_DUTYCONFIG_RESETVALUE 0x00000000UL /**< Default value for IDAC_DUTYCONFIG */
-#define _IDAC_DUTYCONFIG_MASK 0x00000002UL /**< Mask for IDAC_DUTYCONFIG */
-#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS (0x1UL << 1) /**< Duty Cycle Enable */
-#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_SHIFT 1 /**< Shift value for IDAC_EM2DUTYCYCLEDIS */
-#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_MASK 0x2UL /**< Bit mask for IDAC_EM2DUTYCYCLEDIS */
-#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_DUTYCONFIG */
-#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT (_IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_DUTYCONFIG */
-
-/* Bit fields for IDAC STATUS */
-#define _IDAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for IDAC_STATUS */
-#define _IDAC_STATUS_MASK 0x00000002UL /**< Mask for IDAC_STATUS */
-#define IDAC_STATUS_APORTCONFLICT (0x1UL << 1) /**< APORT Conflict Output */
-#define _IDAC_STATUS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */
-#define _IDAC_STATUS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */
-#define _IDAC_STATUS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_STATUS */
-#define IDAC_STATUS_APORTCONFLICT_DEFAULT (_IDAC_STATUS_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_STATUS */
-
-/* Bit fields for IDAC IF */
-#define _IDAC_IF_RESETVALUE 0x00000000UL /**< Default value for IDAC_IF */
-#define _IDAC_IF_MASK 0x00000002UL /**< Mask for IDAC_IF */
-#define IDAC_IF_APORTCONFLICT (0x1UL << 1) /**< APORT Conflict Interrupt Flag */
-#define _IDAC_IF_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */
-#define _IDAC_IF_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */
-#define _IDAC_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IF */
-#define IDAC_IF_APORTCONFLICT_DEFAULT (_IDAC_IF_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IF */
-
-/* Bit fields for IDAC IFS */
-#define _IDAC_IFS_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFS */
-#define _IDAC_IFS_MASK 0x00000002UL /**< Mask for IDAC_IFS */
-#define IDAC_IFS_APORTCONFLICT (0x1UL << 1) /**< Set APORTCONFLICT Interrupt Flag */
-#define _IDAC_IFS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */
-#define _IDAC_IFS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */
-#define _IDAC_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFS */
-#define IDAC_IFS_APORTCONFLICT_DEFAULT (_IDAC_IFS_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IFS */
-
-/* Bit fields for IDAC IFC */
-#define _IDAC_IFC_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFC */
-#define _IDAC_IFC_MASK 0x00000002UL /**< Mask for IDAC_IFC */
-#define IDAC_IFC_APORTCONFLICT (0x1UL << 1) /**< Clear APORTCONFLICT Interrupt Flag */
-#define _IDAC_IFC_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */
-#define _IDAC_IFC_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */
-#define _IDAC_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFC */
-#define IDAC_IFC_APORTCONFLICT_DEFAULT (_IDAC_IFC_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IFC */
-
-/* Bit fields for IDAC IEN */
-#define _IDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for IDAC_IEN */
-#define _IDAC_IEN_MASK 0x00000002UL /**< Mask for IDAC_IEN */
-#define IDAC_IEN_APORTCONFLICT (0x1UL << 1) /**< APORTCONFLICT Interrupt Enable */
-#define _IDAC_IEN_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */
-#define _IDAC_IEN_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */
-#define _IDAC_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IEN */
-#define IDAC_IEN_APORTCONFLICT_DEFAULT (_IDAC_IEN_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IEN */
-
-/* Bit fields for IDAC APORTREQ */
-#define _IDAC_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTREQ */
-#define _IDAC_APORTREQ_MASK 0x0000000CUL /**< Mask for IDAC_APORTREQ */
-#define IDAC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 If the APORT Bus Connected to APORT1X is Requested */
-#define _IDAC_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for IDAC_APORT1XREQ */
-#define _IDAC_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for IDAC_APORT1XREQ */
-#define _IDAC_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */
-#define IDAC_APORTREQ_APORT1XREQ_DEFAULT (_IDAC_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTREQ */
-#define IDAC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is Requested */
-#define _IDAC_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for IDAC_APORT1YREQ */
-#define _IDAC_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for IDAC_APORT1YREQ */
-#define _IDAC_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */
-#define IDAC_APORTREQ_APORT1YREQ_DEFAULT (_IDAC_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTREQ */
-
-/* Bit fields for IDAC APORTCONFLICT */
-#define _IDAC_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTCONFLICT */
-#define _IDAC_APORTCONFLICT_MASK 0x0000000CUL /**< Mask for IDAC_APORTCONFLICT */
-#define IDAC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */
-#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for IDAC_APORT1XCONFLICT */
-#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for IDAC_APORT1XCONFLICT */
-#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */
-#define IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */
-#define IDAC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is in Conflict With Another Peripheral */
-#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for IDAC_APORT1YCONFLICT */
-#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for IDAC_APORT1YCONFLICT */
-#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */
-#define IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */
-
-/** @} */
-/** @} End of group EFR32FG13P_IDAC */
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_ldma.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_ldma.h
deleted file mode 100644
index aa28ed99..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_ldma.h
+++ /dev/null
@@ -1,628 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_ldma.h
- * @brief EFR32FG13P_LDMA register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P_LDMA LDMA
- * @{
- * @brief EFR32FG13P_LDMA Register Declaration
- *****************************************************************************/
-/** LDMA Register Declaration */
-typedef struct {
- __IOM uint32_t CTRL; /**< DMA Control Register */
- __IM uint32_t STATUS; /**< DMA Status Register */
- __IOM uint32_t SYNC; /**< DMA Synchronization Trigger Register (Single-Cycle RMW) */
- uint32_t RESERVED0[5]; /**< Reserved for future use **/
- __IOM uint32_t CHEN; /**< DMA Channel Enable Register (Single-Cycle RMW) */
- __IM uint32_t CHBUSY; /**< DMA Channel Busy Register */
- __IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register (Single-Cycle RMW) */
- __IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */
- __IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request Register */
- __IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */
- __IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */
- __IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */
- __IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */
- uint32_t RESERVED1[7]; /**< Reserved for future use **/
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
-
- uint32_t RESERVED2[4]; /**< Reserved registers */
- LDMA_CH_TypeDef CH[8]; /**< DMA Channel Registers */
-} LDMA_TypeDef; /** @} */
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_LDMA
- * @{
- * @defgroup EFR32FG13P_LDMA_BitFields LDMA Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for LDMA CTRL */
-#define _LDMA_CTRL_RESETVALUE 0x07000000UL /**< Default value for LDMA_CTRL */
-#define _LDMA_CTRL_MASK 0x0700FFFFUL /**< Mask for LDMA_CTRL */
-#define _LDMA_CTRL_SYNCPRSSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCPRSSETEN */
-#define _LDMA_CTRL_SYNCPRSSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCPRSSETEN */
-#define _LDMA_CTRL_SYNCPRSSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */
-#define LDMA_CTRL_SYNCPRSSETEN_DEFAULT (_LDMA_CTRL_SYNCPRSSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CTRL */
-#define _LDMA_CTRL_SYNCPRSCLREN_SHIFT 8 /**< Shift value for LDMA_SYNCPRSCLREN */
-#define _LDMA_CTRL_SYNCPRSCLREN_MASK 0xFF00UL /**< Bit mask for LDMA_SYNCPRSCLREN */
-#define _LDMA_CTRL_SYNCPRSCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */
-#define LDMA_CTRL_SYNCPRSCLREN_DEFAULT (_LDMA_CTRL_SYNCPRSCLREN_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_CTRL */
-#define _LDMA_CTRL_NUMFIXED_SHIFT 24 /**< Shift value for LDMA_NUMFIXED */
-#define _LDMA_CTRL_NUMFIXED_MASK 0x7000000UL /**< Bit mask for LDMA_NUMFIXED */
-#define _LDMA_CTRL_NUMFIXED_DEFAULT 0x00000007UL /**< Mode DEFAULT for LDMA_CTRL */
-#define LDMA_CTRL_NUMFIXED_DEFAULT (_LDMA_CTRL_NUMFIXED_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CTRL */
-
-/* Bit fields for LDMA STATUS */
-#define _LDMA_STATUS_RESETVALUE 0x08100000UL /**< Default value for LDMA_STATUS */
-#define _LDMA_STATUS_MASK 0x1F1F073BUL /**< Mask for LDMA_STATUS */
-#define LDMA_STATUS_ANYBUSY (0x1UL << 0) /**< Any DMA Channel Busy */
-#define _LDMA_STATUS_ANYBUSY_SHIFT 0 /**< Shift value for LDMA_ANYBUSY */
-#define _LDMA_STATUS_ANYBUSY_MASK 0x1UL /**< Bit mask for LDMA_ANYBUSY */
-#define _LDMA_STATUS_ANYBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
-#define LDMA_STATUS_ANYBUSY_DEFAULT (_LDMA_STATUS_ANYBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_STATUS */
-#define LDMA_STATUS_ANYREQ (0x1UL << 1) /**< Any DMA Channel Request Pending */
-#define _LDMA_STATUS_ANYREQ_SHIFT 1 /**< Shift value for LDMA_ANYREQ */
-#define _LDMA_STATUS_ANYREQ_MASK 0x2UL /**< Bit mask for LDMA_ANYREQ */
-#define _LDMA_STATUS_ANYREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
-#define LDMA_STATUS_ANYREQ_DEFAULT (_LDMA_STATUS_ANYREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_STATUS */
-#define _LDMA_STATUS_CHGRANT_SHIFT 3 /**< Shift value for LDMA_CHGRANT */
-#define _LDMA_STATUS_CHGRANT_MASK 0x38UL /**< Bit mask for LDMA_CHGRANT */
-#define _LDMA_STATUS_CHGRANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
-#define LDMA_STATUS_CHGRANT_DEFAULT (_LDMA_STATUS_CHGRANT_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_STATUS */
-#define _LDMA_STATUS_CHERROR_SHIFT 8 /**< Shift value for LDMA_CHERROR */
-#define _LDMA_STATUS_CHERROR_MASK 0x700UL /**< Bit mask for LDMA_CHERROR */
-#define _LDMA_STATUS_CHERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
-#define LDMA_STATUS_CHERROR_DEFAULT (_LDMA_STATUS_CHERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_STATUS */
-#define _LDMA_STATUS_FIFOLEVEL_SHIFT 16 /**< Shift value for LDMA_FIFOLEVEL */
-#define _LDMA_STATUS_FIFOLEVEL_MASK 0x1F0000UL /**< Bit mask for LDMA_FIFOLEVEL */
-#define _LDMA_STATUS_FIFOLEVEL_DEFAULT 0x00000010UL /**< Mode DEFAULT for LDMA_STATUS */
-#define LDMA_STATUS_FIFOLEVEL_DEFAULT (_LDMA_STATUS_FIFOLEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_STATUS */
-#define _LDMA_STATUS_CHNUM_SHIFT 24 /**< Shift value for LDMA_CHNUM */
-#define _LDMA_STATUS_CHNUM_MASK 0x1F000000UL /**< Bit mask for LDMA_CHNUM */
-#define _LDMA_STATUS_CHNUM_DEFAULT 0x00000008UL /**< Mode DEFAULT for LDMA_STATUS */
-#define LDMA_STATUS_CHNUM_DEFAULT (_LDMA_STATUS_CHNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_STATUS */
-
-/* Bit fields for LDMA SYNC */
-#define _LDMA_SYNC_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNC */
-#define _LDMA_SYNC_MASK 0x000000FFUL /**< Mask for LDMA_SYNC */
-#define _LDMA_SYNC_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */
-#define _LDMA_SYNC_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */
-#define _LDMA_SYNC_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNC */
-#define LDMA_SYNC_SYNCTRIG_DEFAULT (_LDMA_SYNC_SYNCTRIG_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNC */
-
-/* Bit fields for LDMA CHEN */
-#define _LDMA_CHEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHEN */
-#define _LDMA_CHEN_MASK 0x000000FFUL /**< Mask for LDMA_CHEN */
-#define _LDMA_CHEN_CHEN_SHIFT 0 /**< Shift value for LDMA_CHEN */
-#define _LDMA_CHEN_CHEN_MASK 0xFFUL /**< Bit mask for LDMA_CHEN */
-#define _LDMA_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHEN */
-#define LDMA_CHEN_CHEN_DEFAULT (_LDMA_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHEN */
-
-/* Bit fields for LDMA CHBUSY */
-#define _LDMA_CHBUSY_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHBUSY */
-#define _LDMA_CHBUSY_MASK 0x000000FFUL /**< Mask for LDMA_CHBUSY */
-#define _LDMA_CHBUSY_BUSY_SHIFT 0 /**< Shift value for LDMA_BUSY */
-#define _LDMA_CHBUSY_BUSY_MASK 0xFFUL /**< Bit mask for LDMA_BUSY */
-#define _LDMA_CHBUSY_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHBUSY */
-#define LDMA_CHBUSY_BUSY_DEFAULT (_LDMA_CHBUSY_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHBUSY */
-
-/* Bit fields for LDMA CHDONE */
-#define _LDMA_CHDONE_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDONE */
-#define _LDMA_CHDONE_MASK 0x000000FFUL /**< Mask for LDMA_CHDONE */
-#define _LDMA_CHDONE_CHDONE_SHIFT 0 /**< Shift value for LDMA_CHDONE */
-#define _LDMA_CHDONE_CHDONE_MASK 0xFFUL /**< Bit mask for LDMA_CHDONE */
-#define _LDMA_CHDONE_CHDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */
-#define LDMA_CHDONE_CHDONE_DEFAULT (_LDMA_CHDONE_CHDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDONE */
-
-/* Bit fields for LDMA DBGHALT */
-#define _LDMA_DBGHALT_RESETVALUE 0x00000000UL /**< Default value for LDMA_DBGHALT */
-#define _LDMA_DBGHALT_MASK 0x000000FFUL /**< Mask for LDMA_DBGHALT */
-#define _LDMA_DBGHALT_DBGHALT_SHIFT 0 /**< Shift value for LDMA_DBGHALT */
-#define _LDMA_DBGHALT_DBGHALT_MASK 0xFFUL /**< Bit mask for LDMA_DBGHALT */
-#define _LDMA_DBGHALT_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_DBGHALT */
-#define LDMA_DBGHALT_DBGHALT_DEFAULT (_LDMA_DBGHALT_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_DBGHALT */
-
-/* Bit fields for LDMA SWREQ */
-#define _LDMA_SWREQ_RESETVALUE 0x00000000UL /**< Default value for LDMA_SWREQ */
-#define _LDMA_SWREQ_MASK 0x000000FFUL /**< Mask for LDMA_SWREQ */
-#define _LDMA_SWREQ_SWREQ_SHIFT 0 /**< Shift value for LDMA_SWREQ */
-#define _LDMA_SWREQ_SWREQ_MASK 0xFFUL /**< Bit mask for LDMA_SWREQ */
-#define _LDMA_SWREQ_SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SWREQ */
-#define LDMA_SWREQ_SWREQ_DEFAULT (_LDMA_SWREQ_SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SWREQ */
-
-/* Bit fields for LDMA REQDIS */
-#define _LDMA_REQDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQDIS */
-#define _LDMA_REQDIS_MASK 0x000000FFUL /**< Mask for LDMA_REQDIS */
-#define _LDMA_REQDIS_REQDIS_SHIFT 0 /**< Shift value for LDMA_REQDIS */
-#define _LDMA_REQDIS_REQDIS_MASK 0xFFUL /**< Bit mask for LDMA_REQDIS */
-#define _LDMA_REQDIS_REQDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQDIS */
-#define LDMA_REQDIS_REQDIS_DEFAULT (_LDMA_REQDIS_REQDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQDIS */
-
-/* Bit fields for LDMA REQPEND */
-#define _LDMA_REQPEND_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQPEND */
-#define _LDMA_REQPEND_MASK 0x000000FFUL /**< Mask for LDMA_REQPEND */
-#define _LDMA_REQPEND_REQPEND_SHIFT 0 /**< Shift value for LDMA_REQPEND */
-#define _LDMA_REQPEND_REQPEND_MASK 0xFFUL /**< Bit mask for LDMA_REQPEND */
-#define _LDMA_REQPEND_REQPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQPEND */
-#define LDMA_REQPEND_REQPEND_DEFAULT (_LDMA_REQPEND_REQPEND_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQPEND */
-
-/* Bit fields for LDMA LINKLOAD */
-#define _LDMA_LINKLOAD_RESETVALUE 0x00000000UL /**< Default value for LDMA_LINKLOAD */
-#define _LDMA_LINKLOAD_MASK 0x000000FFUL /**< Mask for LDMA_LINKLOAD */
-#define _LDMA_LINKLOAD_LINKLOAD_SHIFT 0 /**< Shift value for LDMA_LINKLOAD */
-#define _LDMA_LINKLOAD_LINKLOAD_MASK 0xFFUL /**< Bit mask for LDMA_LINKLOAD */
-#define _LDMA_LINKLOAD_LINKLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_LINKLOAD */
-#define LDMA_LINKLOAD_LINKLOAD_DEFAULT (_LDMA_LINKLOAD_LINKLOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_LINKLOAD */
-
-/* Bit fields for LDMA REQCLEAR */
-#define _LDMA_REQCLEAR_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQCLEAR */
-#define _LDMA_REQCLEAR_MASK 0x000000FFUL /**< Mask for LDMA_REQCLEAR */
-#define _LDMA_REQCLEAR_REQCLEAR_SHIFT 0 /**< Shift value for LDMA_REQCLEAR */
-#define _LDMA_REQCLEAR_REQCLEAR_MASK 0xFFUL /**< Bit mask for LDMA_REQCLEAR */
-#define _LDMA_REQCLEAR_REQCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQCLEAR */
-#define LDMA_REQCLEAR_REQCLEAR_DEFAULT (_LDMA_REQCLEAR_REQCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQCLEAR */
-
-/* Bit fields for LDMA IF */
-#define _LDMA_IF_RESETVALUE 0x00000000UL /**< Default value for LDMA_IF */
-#define _LDMA_IF_MASK 0x800000FFUL /**< Mask for LDMA_IF */
-#define _LDMA_IF_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */
-#define _LDMA_IF_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */
-#define _LDMA_IF_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
-#define LDMA_IF_DONE_DEFAULT (_LDMA_IF_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IF */
-#define LDMA_IF_ERROR (0x1UL << 31) /**< Transfer Error Interrupt Flag */
-#define _LDMA_IF_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
-#define _LDMA_IF_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
-#define _LDMA_IF_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
-#define LDMA_IF_ERROR_DEFAULT (_LDMA_IF_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IF */
-
-/* Bit fields for LDMA IFS */
-#define _LDMA_IFS_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFS */
-#define _LDMA_IFS_MASK 0x800000FFUL /**< Mask for LDMA_IFS */
-#define _LDMA_IFS_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */
-#define _LDMA_IFS_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */
-#define _LDMA_IFS_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */
-#define LDMA_IFS_DONE_DEFAULT (_LDMA_IFS_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFS */
-#define LDMA_IFS_ERROR (0x1UL << 31) /**< Set ERROR Interrupt Flag */
-#define _LDMA_IFS_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
-#define _LDMA_IFS_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
-#define _LDMA_IFS_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */
-#define LDMA_IFS_ERROR_DEFAULT (_LDMA_IFS_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFS */
-
-/* Bit fields for LDMA IFC */
-#define _LDMA_IFC_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFC */
-#define _LDMA_IFC_MASK 0x800000FFUL /**< Mask for LDMA_IFC */
-#define _LDMA_IFC_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */
-#define _LDMA_IFC_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */
-#define _LDMA_IFC_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */
-#define LDMA_IFC_DONE_DEFAULT (_LDMA_IFC_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFC */
-#define LDMA_IFC_ERROR (0x1UL << 31) /**< Clear ERROR Interrupt Flag */
-#define _LDMA_IFC_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
-#define _LDMA_IFC_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
-#define _LDMA_IFC_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */
-#define LDMA_IFC_ERROR_DEFAULT (_LDMA_IFC_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFC */
-
-/* Bit fields for LDMA IEN */
-#define _LDMA_IEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_IEN */
-#define _LDMA_IEN_MASK 0x800000FFUL /**< Mask for LDMA_IEN */
-#define _LDMA_IEN_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */
-#define _LDMA_IEN_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */
-#define _LDMA_IEN_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */
-#define LDMA_IEN_DONE_DEFAULT (_LDMA_IEN_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IEN */
-#define LDMA_IEN_ERROR (0x1UL << 31) /**< ERROR Interrupt Enable */
-#define _LDMA_IEN_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
-#define _LDMA_IEN_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
-#define _LDMA_IEN_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */
-#define LDMA_IEN_ERROR_DEFAULT (_LDMA_IEN_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IEN */
-
-/* Bit fields for LDMA CH_REQSEL */
-#define _LDMA_CH_REQSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_MASK 0x003F000FUL /**< Mask for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_SHIFT 0 /**< Shift value for LDMA_SIGSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_MASK 0xFUL /**< Bit mask for LDMA_SIGSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_PRSREQ0 0x00000000UL /**< Mode PRSREQ0 for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF 0x00000000UL /**< Mode WTIMER0UFOF for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR 0x00000000UL /**< Mode CRYPTO0DATA0WR for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR /**< Alias for mode CRYPTO0DATA0WR */
-#define _LDMA_CH_REQSEL_SIGSEL_CSENDATA 0x00000000UL /**< Mode CSENDATA for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR 0x00000000UL /**< Mode CRYPTO1DATA0WR for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_PRSREQ1 0x00000001UL /**< Mode PRSREQ1 for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 0x00000001UL /**< Mode WTIMER0CC0 for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR 0x00000001UL /**< Mode CRYPTO0DATA0XWR for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR /**< Alias for mode CRYPTO0DATA0XWR */
-#define _LDMA_CH_REQSEL_SIGSEL_CSENBSLN 0x00000001UL /**< Mode CSENBSLN for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR 0x00000001UL /**< Mode CRYPTO1DATA0XWR for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 0x00000002UL /**< Mode WTIMER0CC1 for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD 0x00000002UL /**< Mode CRYPTO0DATA0RD for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD /**< Alias for mode CRYPTO0DATA0RD */
-#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD 0x00000002UL /**< Mode CRYPTO1DATA0RD for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 0x00000003UL /**< Mode WTIMER0CC2 for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR 0x00000003UL /**< Mode CRYPTO0DATA1WR for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR /**< Alias for mode CRYPTO0DATA1WR */
-#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR 0x00000003UL /**< Mode CRYPTO1DATA1WR for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 0x00000004UL /**< Mode TIMER1CC3 for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD 0x00000004UL /**< Mode CRYPTO0DATA1RD for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD /**< Alias for mode CRYPTO0DATA1RD */
-#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD 0x00000004UL /**< Mode CRYPTO1DATA1RD for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_PRSREQ0 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ0 << 0) /**< Shifted mode PRSREQ0 for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE (_LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 (_LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF << 0) /**< Shifted mode WTIMER0UFOF for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_MSCWDATA (_LDMA_CH_REQSEL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR << 0) /**< Shifted mode CRYPTO0DATA0WR for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_CSENDATA (_LDMA_CH_REQSEL_SIGSEL_CSENDATA << 0) /**< Shifted mode CSENDATA for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV (_LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR << 0) /**< Shifted mode CRYPTO1DATA0WR for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_PRSREQ1 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ1 << 0) /**< Shifted mode PRSREQ1 for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_ADC0SCAN (_LDMA_CH_REQSEL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 (_LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_USART0TXBL (_LDMA_CH_REQSEL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_USART1TXBL (_LDMA_CH_REQSEL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_USART2TXBL (_LDMA_CH_REQSEL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_I2C0TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_I2C1TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR << 0) /**< Shifted mode CRYPTO0DATA0XWR for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_CSENBSLN (_LDMA_CH_REQSEL_SIGSEL_CSENBSLN << 0) /**< Shifted mode CSENBSLN for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR << 0) /**< Shifted mode CRYPTO1DATA0XWR for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD << 0) /**< Shifted mode CRYPTO0DATA0RD for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD << 0) /**< Shifted mode CRYPTO1DATA0RD for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR << 0) /**< Shifted mode CRYPTO0DATA1WR for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR << 0) /**< Shifted mode CRYPTO1DATA1WR for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD << 0) /**< Shifted mode CRYPTO0DATA1RD for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD << 0) /**< Shifted mode CRYPTO1DATA1RD for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SOURCESEL_SHIFT 16 /**< Shift value for LDMA_SOURCESEL */
-#define _LDMA_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for LDMA_SOURCESEL */
-#define _LDMA_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SOURCESEL_PRS 0x00000001UL /**< Mode PRS for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SOURCESEL_VDAC0 0x0000000AUL /**< Mode VDAC0 for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SOURCESEL_I2C1 0x00000015UL /**< Mode I2C1 for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SOURCESEL_WTIMER0 0x0000001AUL /**< Mode WTIMER0 for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 0x00000031UL /**< Mode CRYPTO0 for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO _LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 /**< Alias for mode CRYPTO0 */
-#define _LDMA_CH_REQSEL_SOURCESEL_CSEN 0x00000032UL /**< Mode CSEN for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SOURCESEL_LESENSE 0x00000033UL /**< Mode LESENSE for LDMA_CH_REQSEL */
-#define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO1 0x00000034UL /**< Mode CRYPTO1 for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SOURCESEL_NONE (_LDMA_CH_REQSEL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SOURCESEL_PRS (_LDMA_CH_REQSEL_SOURCESEL_PRS << 16) /**< Shifted mode PRS for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SOURCESEL_ADC0 (_LDMA_CH_REQSEL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SOURCESEL_VDAC0 (_LDMA_CH_REQSEL_SOURCESEL_VDAC0 << 16) /**< Shifted mode VDAC0 for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SOURCESEL_USART0 (_LDMA_CH_REQSEL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SOURCESEL_USART1 (_LDMA_CH_REQSEL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SOURCESEL_USART2 (_LDMA_CH_REQSEL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SOURCESEL_LEUART0 (_LDMA_CH_REQSEL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SOURCESEL_I2C0 (_LDMA_CH_REQSEL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SOURCESEL_I2C1 (_LDMA_CH_REQSEL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SOURCESEL_TIMER0 (_LDMA_CH_REQSEL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SOURCESEL_TIMER1 (_LDMA_CH_REQSEL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SOURCESEL_WTIMER0 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER0 << 16) /**< Shifted mode WTIMER0 for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SOURCESEL_MSC (_LDMA_CH_REQSEL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 (_LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 << 16) /**< Shifted mode CRYPTO0 for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SOURCESEL_CSEN (_LDMA_CH_REQSEL_SOURCESEL_CSEN << 16) /**< Shifted mode CSEN for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SOURCESEL_LESENSE (_LDMA_CH_REQSEL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for LDMA_CH_REQSEL */
-#define LDMA_CH_REQSEL_SOURCESEL_CRYPTO1 (_LDMA_CH_REQSEL_SOURCESEL_CRYPTO1 << 16) /**< Shifted mode CRYPTO1 for LDMA_CH_REQSEL */
-
-/* Bit fields for LDMA CH_CFG */
-#define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */
-#define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */
-#define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */
-#define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */
-#define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */
-#define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */
-#define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */
-#define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */
-#define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */
-#define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */
-#define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */
-#define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */
-#define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */
-#define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */
-#define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */
-#define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */
-#define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */
-#define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */
-#define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */
-#define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */
-#define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */
-#define LDMA_CH_CFG_SRCINCSIGN_POSITIVE (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20) /**< Shifted mode POSITIVE for LDMA_CH_CFG */
-#define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */
-#define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */
-#define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */
-#define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */
-#define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */
-#define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */
-#define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */
-#define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */
-#define LDMA_CH_CFG_DSTINCSIGN_POSITIVE (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21) /**< Shifted mode POSITIVE for LDMA_CH_CFG */
-#define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */
-
-/* Bit fields for LDMA CH_LOOP */
-#define _LDMA_CH_LOOP_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LOOP */
-#define _LDMA_CH_LOOP_MASK 0x000000FFUL /**< Mask for LDMA_CH_LOOP */
-#define _LDMA_CH_LOOP_LOOPCNT_SHIFT 0 /**< Shift value for LDMA_LOOPCNT */
-#define _LDMA_CH_LOOP_LOOPCNT_MASK 0xFFUL /**< Bit mask for LDMA_LOOPCNT */
-#define _LDMA_CH_LOOP_LOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LOOP */
-#define LDMA_CH_LOOP_LOOPCNT_DEFAULT (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LOOP */
-
-/* Bit fields for LDMA CH_CTRL */
-#define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */
-#define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */
-#define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0) /**< Shifted mode SYNCHRONIZE for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */
-#define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */
-#define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */
-#define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */
-#define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */
-#define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */
-#define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */
-#define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */
-#define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */
-#define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */
-#define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_DONEIFSEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set Enable */
-#define _LDMA_CH_CTRL_DONEIFSEN_SHIFT 20 /**< Shift value for LDMA_DONEIFSEN */
-#define _LDMA_CH_CTRL_DONEIFSEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIFSEN */
-#define _LDMA_CH_CTRL_DONEIFSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_DONEIFSEN_DEFAULT (_LDMA_CH_CTRL_DONEIFSEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */
-#define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */
-#define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */
-#define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */
-#define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */
-#define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */
-#define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */
-#define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */
-#define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */
-#define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */
-#define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */
-#define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */
-#define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */
-#define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */
-#define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */
-#define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */
-#define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */
-#define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */
-#define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */
-#define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */
-#define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */
-#define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */
-#define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */
-#define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */
-
-/* Bit fields for LDMA CH_SRC */
-#define _LDMA_CH_SRC_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_SRC */
-#define _LDMA_CH_SRC_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_SRC */
-#define _LDMA_CH_SRC_SRCADDR_SHIFT 0 /**< Shift value for LDMA_SRCADDR */
-#define _LDMA_CH_SRC_SRCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_SRCADDR */
-#define _LDMA_CH_SRC_SRCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_SRC */
-#define LDMA_CH_SRC_SRCADDR_DEFAULT (_LDMA_CH_SRC_SRCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_SRC */
-
-/* Bit fields for LDMA CH_DST */
-#define _LDMA_CH_DST_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_DST */
-#define _LDMA_CH_DST_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_DST */
-#define _LDMA_CH_DST_DSTADDR_SHIFT 0 /**< Shift value for LDMA_DSTADDR */
-#define _LDMA_CH_DST_DSTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_DSTADDR */
-#define _LDMA_CH_DST_DSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_DST */
-#define LDMA_CH_DST_DSTADDR_DEFAULT (_LDMA_CH_DST_DSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_DST */
-
-/* Bit fields for LDMA CH_LINK */
-#define _LDMA_CH_LINK_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LINK */
-#define _LDMA_CH_LINK_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_LINK */
-#define LDMA_CH_LINK_LINKMODE (0x1UL << 0) /**< Link Structure Addressing Mode */
-#define _LDMA_CH_LINK_LINKMODE_SHIFT 0 /**< Shift value for LDMA_LINKMODE */
-#define _LDMA_CH_LINK_LINKMODE_MASK 0x1UL /**< Bit mask for LDMA_LINKMODE */
-#define _LDMA_CH_LINK_LINKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */
-#define _LDMA_CH_LINK_LINKMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_LINK */
-#define _LDMA_CH_LINK_LINKMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_LINK */
-#define LDMA_CH_LINK_LINKMODE_DEFAULT (_LDMA_CH_LINK_LINKMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LINK */
-#define LDMA_CH_LINK_LINKMODE_ABSOLUTE (_LDMA_CH_LINK_LINKMODE_ABSOLUTE << 0) /**< Shifted mode ABSOLUTE for LDMA_CH_LINK */
-#define LDMA_CH_LINK_LINKMODE_RELATIVE (_LDMA_CH_LINK_LINKMODE_RELATIVE << 0) /**< Shifted mode RELATIVE for LDMA_CH_LINK */
-#define LDMA_CH_LINK_LINK (0x1UL << 1) /**< Link Next Structure */
-#define _LDMA_CH_LINK_LINK_SHIFT 1 /**< Shift value for LDMA_LINK */
-#define _LDMA_CH_LINK_LINK_MASK 0x2UL /**< Bit mask for LDMA_LINK */
-#define _LDMA_CH_LINK_LINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */
-#define LDMA_CH_LINK_LINK_DEFAULT (_LDMA_CH_LINK_LINK_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CH_LINK */
-#define _LDMA_CH_LINK_LINKADDR_SHIFT 2 /**< Shift value for LDMA_LINKADDR */
-#define _LDMA_CH_LINK_LINKADDR_MASK 0xFFFFFFFCUL /**< Bit mask for LDMA_LINKADDR */
-#define _LDMA_CH_LINK_LINKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */
-#define LDMA_CH_LINK_LINKADDR_DEFAULT (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CH_LINK */
-
-/** @} */
-/** @} End of group EFR32FG13P_LDMA */
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_ldma_ch.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_ldma_ch.h
deleted file mode 100644
index 8a7a1bb3..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_ldma_ch.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_ldma_ch.h
- * @brief EFR32FG13P_LDMA_CH register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @brief LDMA_CH LDMA CH Register
- * @ingroup EFR32FG13P_LDMA
- *****************************************************************************/
-typedef struct {
- __IOM uint32_t REQSEL; /**< Channel Peripheral Request Select Register */
- __IOM uint32_t CFG; /**< Channel Configuration Register */
- __IOM uint32_t LOOP; /**< Channel Loop Counter Register */
- __IOM uint32_t CTRL; /**< Channel Descriptor Control Word Register */
- __IOM uint32_t SRC; /**< Channel Descriptor Source Data Address Register */
- __IOM uint32_t DST; /**< Channel Descriptor Destination Data Address Register */
- __IOM uint32_t LINK; /**< Channel Descriptor Link Structure Address Register */
- uint32_t RESERVED0[5]; /**< Reserved future */
-} LDMA_CH_TypeDef;
-
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_lesense.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_lesense.h
deleted file mode 100644
index 73ba04aa..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_lesense.h
+++ /dev/null
@@ -1,1876 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_lesense.h
- * @brief EFR32FG13P_LESENSE register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P_LESENSE LESENSE
- * @{
- * @brief EFR32FG13P_LESENSE Register Declaration
- *****************************************************************************/
-/** LESENSE Register Declaration */
-typedef struct {
- __IOM uint32_t CTRL; /**< Control Register */
- __IOM uint32_t TIMCTRL; /**< Timing Control Register */
- __IOM uint32_t PERCTRL; /**< Peripheral Control Register */
- __IOM uint32_t DECCTRL; /**< Decoder Control Register */
- __IOM uint32_t BIASCTRL; /**< Bias Control Register */
- __IOM uint32_t EVALCTRL; /**< LESENSE Evaluation Control */
- __IOM uint32_t PRSCTRL; /**< PRS Control Register */
- __IOM uint32_t CMD; /**< Command Register */
- __IOM uint32_t CHEN; /**< Channel Enable Register */
- __IOM uint32_t SCANRES; /**< Scan Result Register */
- __IM uint32_t STATUS; /**< Status Register */
- __IM uint32_t PTR; /**< Result Buffer Pointers */
- __IM uint32_t BUFDATA; /**< Result Buffer Data Register */
- __IM uint32_t CURCH; /**< Current Channel Index */
- __IOM uint32_t DECSTATE; /**< Current Decoder State */
- __IOM uint32_t SENSORSTATE; /**< Decoder Input Register */
- __IOM uint32_t IDLECONF; /**< GPIO Idle Phase Configuration */
- __IOM uint32_t ALTEXCONF; /**< Alternative Excite Pin Configuration */
- uint32_t RESERVED0[2]; /**< Reserved for future use **/
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
- __IOM uint32_t ROUTEPEN; /**< I/O Routing Register */
-
- uint32_t RESERVED1[38]; /**< Reserved registers */
- LESENSE_ST_TypeDef ST[32]; /**< Decoding states */
-
- LESENSE_BUF_TypeDef BUF[16]; /**< Scanresult */
-
- LESENSE_CH_TypeDef CH[16]; /**< Scanconfig */
-} LESENSE_TypeDef; /** @} */
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_LESENSE
- * @{
- * @defgroup EFR32FG13P_LESENSE_BitFields LESENSE Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for LESENSE CTRL */
-#define _LESENSE_CTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CTRL */
-#define _LESENSE_CTRL_MASK 0x007B29BFUL /**< Mask for LESENSE_CTRL */
-#define _LESENSE_CTRL_SCANMODE_SHIFT 0 /**< Shift value for LESENSE_SCANMODE */
-#define _LESENSE_CTRL_SCANMODE_MASK 0x3UL /**< Bit mask for LESENSE_SCANMODE */
-#define _LESENSE_CTRL_SCANMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */
-#define _LESENSE_CTRL_SCANMODE_PERIODIC 0x00000000UL /**< Mode PERIODIC for LESENSE_CTRL */
-#define _LESENSE_CTRL_SCANMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LESENSE_CTRL */
-#define _LESENSE_CTRL_SCANMODE_PRS 0x00000002UL /**< Mode PRS for LESENSE_CTRL */
-#define LESENSE_CTRL_SCANMODE_DEFAULT (_LESENSE_CTRL_SCANMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CTRL */
-#define LESENSE_CTRL_SCANMODE_PERIODIC (_LESENSE_CTRL_SCANMODE_PERIODIC << 0) /**< Shifted mode PERIODIC for LESENSE_CTRL */
-#define LESENSE_CTRL_SCANMODE_ONESHOT (_LESENSE_CTRL_SCANMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LESENSE_CTRL */
-#define LESENSE_CTRL_SCANMODE_PRS (_LESENSE_CTRL_SCANMODE_PRS << 0) /**< Shifted mode PRS for LESENSE_CTRL */
-#define _LESENSE_CTRL_PRSSEL_SHIFT 2 /**< Shift value for LESENSE_PRSSEL */
-#define _LESENSE_CTRL_PRSSEL_MASK 0x3CUL /**< Bit mask for LESENSE_PRSSEL */
-#define _LESENSE_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */
-#define _LESENSE_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_CTRL */
-#define _LESENSE_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_CTRL */
-#define _LESENSE_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_CTRL */
-#define _LESENSE_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_CTRL */
-#define _LESENSE_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_CTRL */
-#define _LESENSE_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_CTRL */
-#define _LESENSE_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_CTRL */
-#define _LESENSE_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_CTRL */
-#define _LESENSE_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_CTRL */
-#define _LESENSE_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_CTRL */
-#define _LESENSE_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_CTRL */
-#define _LESENSE_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_CTRL */
-#define LESENSE_CTRL_PRSSEL_DEFAULT (_LESENSE_CTRL_PRSSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_CTRL */
-#define LESENSE_CTRL_PRSSEL_PRSCH0 (_LESENSE_CTRL_PRSSEL_PRSCH0 << 2) /**< Shifted mode PRSCH0 for LESENSE_CTRL */
-#define LESENSE_CTRL_PRSSEL_PRSCH1 (_LESENSE_CTRL_PRSSEL_PRSCH1 << 2) /**< Shifted mode PRSCH1 for LESENSE_CTRL */
-#define LESENSE_CTRL_PRSSEL_PRSCH2 (_LESENSE_CTRL_PRSSEL_PRSCH2 << 2) /**< Shifted mode PRSCH2 for LESENSE_CTRL */
-#define LESENSE_CTRL_PRSSEL_PRSCH3 (_LESENSE_CTRL_PRSSEL_PRSCH3 << 2) /**< Shifted mode PRSCH3 for LESENSE_CTRL */
-#define LESENSE_CTRL_PRSSEL_PRSCH4 (_LESENSE_CTRL_PRSSEL_PRSCH4 << 2) /**< Shifted mode PRSCH4 for LESENSE_CTRL */
-#define LESENSE_CTRL_PRSSEL_PRSCH5 (_LESENSE_CTRL_PRSSEL_PRSCH5 << 2) /**< Shifted mode PRSCH5 for LESENSE_CTRL */
-#define LESENSE_CTRL_PRSSEL_PRSCH6 (_LESENSE_CTRL_PRSSEL_PRSCH6 << 2) /**< Shifted mode PRSCH6 for LESENSE_CTRL */
-#define LESENSE_CTRL_PRSSEL_PRSCH7 (_LESENSE_CTRL_PRSSEL_PRSCH7 << 2) /**< Shifted mode PRSCH7 for LESENSE_CTRL */
-#define LESENSE_CTRL_PRSSEL_PRSCH8 (_LESENSE_CTRL_PRSSEL_PRSCH8 << 2) /**< Shifted mode PRSCH8 for LESENSE_CTRL */
-#define LESENSE_CTRL_PRSSEL_PRSCH9 (_LESENSE_CTRL_PRSSEL_PRSCH9 << 2) /**< Shifted mode PRSCH9 for LESENSE_CTRL */
-#define LESENSE_CTRL_PRSSEL_PRSCH10 (_LESENSE_CTRL_PRSSEL_PRSCH10 << 2) /**< Shifted mode PRSCH10 for LESENSE_CTRL */
-#define LESENSE_CTRL_PRSSEL_PRSCH11 (_LESENSE_CTRL_PRSSEL_PRSCH11 << 2) /**< Shifted mode PRSCH11 for LESENSE_CTRL */
-#define _LESENSE_CTRL_SCANCONF_SHIFT 7 /**< Shift value for LESENSE_SCANCONF */
-#define _LESENSE_CTRL_SCANCONF_MASK 0x180UL /**< Bit mask for LESENSE_SCANCONF */
-#define _LESENSE_CTRL_SCANCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */
-#define _LESENSE_CTRL_SCANCONF_DIRMAP 0x00000000UL /**< Mode DIRMAP for LESENSE_CTRL */
-#define _LESENSE_CTRL_SCANCONF_INVMAP 0x00000001UL /**< Mode INVMAP for LESENSE_CTRL */
-#define _LESENSE_CTRL_SCANCONF_TOGGLE 0x00000002UL /**< Mode TOGGLE for LESENSE_CTRL */
-#define _LESENSE_CTRL_SCANCONF_DECDEF 0x00000003UL /**< Mode DECDEF for LESENSE_CTRL */
-#define LESENSE_CTRL_SCANCONF_DEFAULT (_LESENSE_CTRL_SCANCONF_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_CTRL */
-#define LESENSE_CTRL_SCANCONF_DIRMAP (_LESENSE_CTRL_SCANCONF_DIRMAP << 7) /**< Shifted mode DIRMAP for LESENSE_CTRL */
-#define LESENSE_CTRL_SCANCONF_INVMAP (_LESENSE_CTRL_SCANCONF_INVMAP << 7) /**< Shifted mode INVMAP for LESENSE_CTRL */
-#define LESENSE_CTRL_SCANCONF_TOGGLE (_LESENSE_CTRL_SCANCONF_TOGGLE << 7) /**< Shifted mode TOGGLE for LESENSE_CTRL */
-#define LESENSE_CTRL_SCANCONF_DECDEF (_LESENSE_CTRL_SCANCONF_DECDEF << 7) /**< Shifted mode DECDEF for LESENSE_CTRL */
-#define LESENSE_CTRL_ALTEXMAP (0x1UL << 11) /**< Alternative Excitation Map */
-#define _LESENSE_CTRL_ALTEXMAP_SHIFT 11 /**< Shift value for LESENSE_ALTEXMAP */
-#define _LESENSE_CTRL_ALTEXMAP_MASK 0x800UL /**< Bit mask for LESENSE_ALTEXMAP */
-#define _LESENSE_CTRL_ALTEXMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */
-#define _LESENSE_CTRL_ALTEXMAP_ALTEX 0x00000000UL /**< Mode ALTEX for LESENSE_CTRL */
-#define _LESENSE_CTRL_ALTEXMAP_CH 0x00000001UL /**< Mode CH for LESENSE_CTRL */
-#define LESENSE_CTRL_ALTEXMAP_DEFAULT (_LESENSE_CTRL_ALTEXMAP_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_CTRL */
-#define LESENSE_CTRL_ALTEXMAP_ALTEX (_LESENSE_CTRL_ALTEXMAP_ALTEX << 11) /**< Shifted mode ALTEX for LESENSE_CTRL */
-#define LESENSE_CTRL_ALTEXMAP_CH (_LESENSE_CTRL_ALTEXMAP_CH << 11) /**< Shifted mode CH for LESENSE_CTRL */
-#define LESENSE_CTRL_DUALSAMPLE (0x1UL << 13) /**< Enable Dual Sample Mode */
-#define _LESENSE_CTRL_DUALSAMPLE_SHIFT 13 /**< Shift value for LESENSE_DUALSAMPLE */
-#define _LESENSE_CTRL_DUALSAMPLE_MASK 0x2000UL /**< Bit mask for LESENSE_DUALSAMPLE */
-#define _LESENSE_CTRL_DUALSAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */
-#define LESENSE_CTRL_DUALSAMPLE_DEFAULT (_LESENSE_CTRL_DUALSAMPLE_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_CTRL */
-#define LESENSE_CTRL_BUFOW (0x1UL << 16) /**< Result Buffer Overwrite */
-#define _LESENSE_CTRL_BUFOW_SHIFT 16 /**< Shift value for LESENSE_BUFOW */
-#define _LESENSE_CTRL_BUFOW_MASK 0x10000UL /**< Bit mask for LESENSE_BUFOW */
-#define _LESENSE_CTRL_BUFOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */
-#define LESENSE_CTRL_BUFOW_DEFAULT (_LESENSE_CTRL_BUFOW_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_CTRL */
-#define LESENSE_CTRL_STRSCANRES (0x1UL << 17) /**< Enable Storing of SCANRES */
-#define _LESENSE_CTRL_STRSCANRES_SHIFT 17 /**< Shift value for LESENSE_STRSCANRES */
-#define _LESENSE_CTRL_STRSCANRES_MASK 0x20000UL /**< Bit mask for LESENSE_STRSCANRES */
-#define _LESENSE_CTRL_STRSCANRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */
-#define LESENSE_CTRL_STRSCANRES_DEFAULT (_LESENSE_CTRL_STRSCANRES_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_CTRL */
-#define LESENSE_CTRL_BUFIDL (0x1UL << 19) /**< Result Buffer Interrupt and DMA Trigger Level */
-#define _LESENSE_CTRL_BUFIDL_SHIFT 19 /**< Shift value for LESENSE_BUFIDL */
-#define _LESENSE_CTRL_BUFIDL_MASK 0x80000UL /**< Bit mask for LESENSE_BUFIDL */
-#define _LESENSE_CTRL_BUFIDL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */
-#define _LESENSE_CTRL_BUFIDL_HALFFULL 0x00000000UL /**< Mode HALFFULL for LESENSE_CTRL */
-#define _LESENSE_CTRL_BUFIDL_FULL 0x00000001UL /**< Mode FULL for LESENSE_CTRL */
-#define LESENSE_CTRL_BUFIDL_DEFAULT (_LESENSE_CTRL_BUFIDL_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_CTRL */
-#define LESENSE_CTRL_BUFIDL_HALFFULL (_LESENSE_CTRL_BUFIDL_HALFFULL << 19) /**< Shifted mode HALFFULL for LESENSE_CTRL */
-#define LESENSE_CTRL_BUFIDL_FULL (_LESENSE_CTRL_BUFIDL_FULL << 19) /**< Shifted mode FULL for LESENSE_CTRL */
-#define _LESENSE_CTRL_DMAWU_SHIFT 20 /**< Shift value for LESENSE_DMAWU */
-#define _LESENSE_CTRL_DMAWU_MASK 0x300000UL /**< Bit mask for LESENSE_DMAWU */
-#define _LESENSE_CTRL_DMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */
-#define _LESENSE_CTRL_DMAWU_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CTRL */
-#define _LESENSE_CTRL_DMAWU_BUFDATAV 0x00000001UL /**< Mode BUFDATAV for LESENSE_CTRL */
-#define _LESENSE_CTRL_DMAWU_BUFLEVEL 0x00000002UL /**< Mode BUFLEVEL for LESENSE_CTRL */
-#define LESENSE_CTRL_DMAWU_DEFAULT (_LESENSE_CTRL_DMAWU_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_CTRL */
-#define LESENSE_CTRL_DMAWU_DISABLE (_LESENSE_CTRL_DMAWU_DISABLE << 20) /**< Shifted mode DISABLE for LESENSE_CTRL */
-#define LESENSE_CTRL_DMAWU_BUFDATAV (_LESENSE_CTRL_DMAWU_BUFDATAV << 20) /**< Shifted mode BUFDATAV for LESENSE_CTRL */
-#define LESENSE_CTRL_DMAWU_BUFLEVEL (_LESENSE_CTRL_DMAWU_BUFLEVEL << 20) /**< Shifted mode BUFLEVEL for LESENSE_CTRL */
-#define LESENSE_CTRL_DEBUGRUN (0x1UL << 22) /**< Debug Mode Run Enable */
-#define _LESENSE_CTRL_DEBUGRUN_SHIFT 22 /**< Shift value for LESENSE_DEBUGRUN */
-#define _LESENSE_CTRL_DEBUGRUN_MASK 0x400000UL /**< Bit mask for LESENSE_DEBUGRUN */
-#define _LESENSE_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */
-#define LESENSE_CTRL_DEBUGRUN_DEFAULT (_LESENSE_CTRL_DEBUGRUN_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_CTRL */
-
-/* Bit fields for LESENSE TIMCTRL */
-#define _LESENSE_TIMCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_TIMCTRL */
-#define _LESENSE_TIMCTRL_MASK 0x10CFF773UL /**< Mask for LESENSE_TIMCTRL */
-#define _LESENSE_TIMCTRL_AUXPRESC_SHIFT 0 /**< Shift value for LESENSE_AUXPRESC */
-#define _LESENSE_TIMCTRL_AUXPRESC_MASK 0x3UL /**< Bit mask for LESENSE_AUXPRESC */
-#define _LESENSE_TIMCTRL_AUXPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */
-#define _LESENSE_TIMCTRL_AUXPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */
-#define _LESENSE_TIMCTRL_AUXPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */
-#define _LESENSE_TIMCTRL_AUXPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */
-#define _LESENSE_TIMCTRL_AUXPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */
-#define LESENSE_TIMCTRL_AUXPRESC_DEFAULT (_LESENSE_TIMCTRL_AUXPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */
-#define LESENSE_TIMCTRL_AUXPRESC_DIV1 (_LESENSE_TIMCTRL_AUXPRESC_DIV1 << 0) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */
-#define LESENSE_TIMCTRL_AUXPRESC_DIV2 (_LESENSE_TIMCTRL_AUXPRESC_DIV2 << 0) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */
-#define LESENSE_TIMCTRL_AUXPRESC_DIV4 (_LESENSE_TIMCTRL_AUXPRESC_DIV4 << 0) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */
-#define LESENSE_TIMCTRL_AUXPRESC_DIV8 (_LESENSE_TIMCTRL_AUXPRESC_DIV8 << 0) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */
-#define _LESENSE_TIMCTRL_LFPRESC_SHIFT 4 /**< Shift value for LESENSE_LFPRESC */
-#define _LESENSE_TIMCTRL_LFPRESC_MASK 0x70UL /**< Bit mask for LESENSE_LFPRESC */
-#define _LESENSE_TIMCTRL_LFPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */
-#define _LESENSE_TIMCTRL_LFPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */
-#define _LESENSE_TIMCTRL_LFPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */
-#define _LESENSE_TIMCTRL_LFPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */
-#define _LESENSE_TIMCTRL_LFPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */
-#define _LESENSE_TIMCTRL_LFPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LESENSE_TIMCTRL */
-#define _LESENSE_TIMCTRL_LFPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LESENSE_TIMCTRL */
-#define _LESENSE_TIMCTRL_LFPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LESENSE_TIMCTRL */
-#define _LESENSE_TIMCTRL_LFPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LESENSE_TIMCTRL */
-#define LESENSE_TIMCTRL_LFPRESC_DEFAULT (_LESENSE_TIMCTRL_LFPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */
-#define LESENSE_TIMCTRL_LFPRESC_DIV1 (_LESENSE_TIMCTRL_LFPRESC_DIV1 << 4) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */
-#define LESENSE_TIMCTRL_LFPRESC_DIV2 (_LESENSE_TIMCTRL_LFPRESC_DIV2 << 4) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */
-#define LESENSE_TIMCTRL_LFPRESC_DIV4 (_LESENSE_TIMCTRL_LFPRESC_DIV4 << 4) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */
-#define LESENSE_TIMCTRL_LFPRESC_DIV8 (_LESENSE_TIMCTRL_LFPRESC_DIV8 << 4) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */
-#define LESENSE_TIMCTRL_LFPRESC_DIV16 (_LESENSE_TIMCTRL_LFPRESC_DIV16 << 4) /**< Shifted mode DIV16 for LESENSE_TIMCTRL */
-#define LESENSE_TIMCTRL_LFPRESC_DIV32 (_LESENSE_TIMCTRL_LFPRESC_DIV32 << 4) /**< Shifted mode DIV32 for LESENSE_TIMCTRL */
-#define LESENSE_TIMCTRL_LFPRESC_DIV64 (_LESENSE_TIMCTRL_LFPRESC_DIV64 << 4) /**< Shifted mode DIV64 for LESENSE_TIMCTRL */
-#define LESENSE_TIMCTRL_LFPRESC_DIV128 (_LESENSE_TIMCTRL_LFPRESC_DIV128 << 4) /**< Shifted mode DIV128 for LESENSE_TIMCTRL */
-#define _LESENSE_TIMCTRL_PCPRESC_SHIFT 8 /**< Shift value for LESENSE_PCPRESC */
-#define _LESENSE_TIMCTRL_PCPRESC_MASK 0x700UL /**< Bit mask for LESENSE_PCPRESC */
-#define _LESENSE_TIMCTRL_PCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */
-#define _LESENSE_TIMCTRL_PCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */
-#define _LESENSE_TIMCTRL_PCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */
-#define _LESENSE_TIMCTRL_PCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */
-#define _LESENSE_TIMCTRL_PCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */
-#define _LESENSE_TIMCTRL_PCPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LESENSE_TIMCTRL */
-#define _LESENSE_TIMCTRL_PCPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LESENSE_TIMCTRL */
-#define _LESENSE_TIMCTRL_PCPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LESENSE_TIMCTRL */
-#define _LESENSE_TIMCTRL_PCPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LESENSE_TIMCTRL */
-#define LESENSE_TIMCTRL_PCPRESC_DEFAULT (_LESENSE_TIMCTRL_PCPRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */
-#define LESENSE_TIMCTRL_PCPRESC_DIV1 (_LESENSE_TIMCTRL_PCPRESC_DIV1 << 8) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */
-#define LESENSE_TIMCTRL_PCPRESC_DIV2 (_LESENSE_TIMCTRL_PCPRESC_DIV2 << 8) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */
-#define LESENSE_TIMCTRL_PCPRESC_DIV4 (_LESENSE_TIMCTRL_PCPRESC_DIV4 << 8) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */
-#define LESENSE_TIMCTRL_PCPRESC_DIV8 (_LESENSE_TIMCTRL_PCPRESC_DIV8 << 8) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */
-#define LESENSE_TIMCTRL_PCPRESC_DIV16 (_LESENSE_TIMCTRL_PCPRESC_DIV16 << 8) /**< Shifted mode DIV16 for LESENSE_TIMCTRL */
-#define LESENSE_TIMCTRL_PCPRESC_DIV32 (_LESENSE_TIMCTRL_PCPRESC_DIV32 << 8) /**< Shifted mode DIV32 for LESENSE_TIMCTRL */
-#define LESENSE_TIMCTRL_PCPRESC_DIV64 (_LESENSE_TIMCTRL_PCPRESC_DIV64 << 8) /**< Shifted mode DIV64 for LESENSE_TIMCTRL */
-#define LESENSE_TIMCTRL_PCPRESC_DIV128 (_LESENSE_TIMCTRL_PCPRESC_DIV128 << 8) /**< Shifted mode DIV128 for LESENSE_TIMCTRL */
-#define _LESENSE_TIMCTRL_PCTOP_SHIFT 12 /**< Shift value for LESENSE_PCTOP */
-#define _LESENSE_TIMCTRL_PCTOP_MASK 0xFF000UL /**< Bit mask for LESENSE_PCTOP */
-#define _LESENSE_TIMCTRL_PCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */
-#define LESENSE_TIMCTRL_PCTOP_DEFAULT (_LESENSE_TIMCTRL_PCTOP_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */
-#define _LESENSE_TIMCTRL_STARTDLY_SHIFT 22 /**< Shift value for LESENSE_STARTDLY */
-#define _LESENSE_TIMCTRL_STARTDLY_MASK 0xC00000UL /**< Bit mask for LESENSE_STARTDLY */
-#define _LESENSE_TIMCTRL_STARTDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */
-#define LESENSE_TIMCTRL_STARTDLY_DEFAULT (_LESENSE_TIMCTRL_STARTDLY_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */
-#define LESENSE_TIMCTRL_AUXSTARTUP (0x1UL << 28) /**< AUXHFRCO Startup Configuration */
-#define _LESENSE_TIMCTRL_AUXSTARTUP_SHIFT 28 /**< Shift value for LESENSE_AUXSTARTUP */
-#define _LESENSE_TIMCTRL_AUXSTARTUP_MASK 0x10000000UL /**< Bit mask for LESENSE_AUXSTARTUP */
-#define _LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */
-#define _LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND 0x00000000UL /**< Mode PREDEMAND for LESENSE_TIMCTRL */
-#define _LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND 0x00000001UL /**< Mode ONDEMAND for LESENSE_TIMCTRL */
-#define LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT (_LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */
-#define LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND (_LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND << 28) /**< Shifted mode PREDEMAND for LESENSE_TIMCTRL */
-#define LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND (_LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND << 28) /**< Shifted mode ONDEMAND for LESENSE_TIMCTRL */
-
-/* Bit fields for LESENSE PERCTRL */
-#define _LESENSE_PERCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PERCTRL */
-#define _LESENSE_PERCTRL_MASK 0x3FF0014FUL /**< Mask for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_DACCH0EN (0x1UL << 0) /**< VDAC CH0 Enable */
-#define _LESENSE_PERCTRL_DACCH0EN_SHIFT 0 /**< Shift value for LESENSE_DACCH0EN */
-#define _LESENSE_PERCTRL_DACCH0EN_MASK 0x1UL /**< Bit mask for LESENSE_DACCH0EN */
-#define _LESENSE_PERCTRL_DACCH0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_DACCH0EN_DEFAULT (_LESENSE_PERCTRL_DACCH0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_DACCH1EN (0x1UL << 1) /**< VDAC CH1 Enable */
-#define _LESENSE_PERCTRL_DACCH1EN_SHIFT 1 /**< Shift value for LESENSE_DACCH1EN */
-#define _LESENSE_PERCTRL_DACCH1EN_MASK 0x2UL /**< Bit mask for LESENSE_DACCH1EN */
-#define _LESENSE_PERCTRL_DACCH1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_DACCH1EN_DEFAULT (_LESENSE_PERCTRL_DACCH1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_DACCH0DATA (0x1UL << 2) /**< VDAC CH0 Data Selection */
-#define _LESENSE_PERCTRL_DACCH0DATA_SHIFT 2 /**< Shift value for LESENSE_DACCH0DATA */
-#define _LESENSE_PERCTRL_DACCH0DATA_MASK 0x4UL /**< Bit mask for LESENSE_DACCH0DATA */
-#define _LESENSE_PERCTRL_DACCH0DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */
-#define _LESENSE_PERCTRL_DACCH0DATA_DACDATA 0x00000000UL /**< Mode DACDATA for LESENSE_PERCTRL */
-#define _LESENSE_PERCTRL_DACCH0DATA_THRES 0x00000001UL /**< Mode THRES for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_DACCH0DATA_DEFAULT (_LESENSE_PERCTRL_DACCH0DATA_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_DACCH0DATA_DACDATA (_LESENSE_PERCTRL_DACCH0DATA_DACDATA << 2) /**< Shifted mode DACDATA for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_DACCH0DATA_THRES (_LESENSE_PERCTRL_DACCH0DATA_THRES << 2) /**< Shifted mode THRES for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_DACCH1DATA (0x1UL << 3) /**< VDAC CH1 Data Selection */
-#define _LESENSE_PERCTRL_DACCH1DATA_SHIFT 3 /**< Shift value for LESENSE_DACCH1DATA */
-#define _LESENSE_PERCTRL_DACCH1DATA_MASK 0x8UL /**< Bit mask for LESENSE_DACCH1DATA */
-#define _LESENSE_PERCTRL_DACCH1DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */
-#define _LESENSE_PERCTRL_DACCH1DATA_DACDATA 0x00000000UL /**< Mode DACDATA for LESENSE_PERCTRL */
-#define _LESENSE_PERCTRL_DACCH1DATA_THRES 0x00000001UL /**< Mode THRES for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_DACCH1DATA_DEFAULT (_LESENSE_PERCTRL_DACCH1DATA_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_DACCH1DATA_DACDATA (_LESENSE_PERCTRL_DACCH1DATA_DACDATA << 3) /**< Shifted mode DACDATA for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_DACCH1DATA_THRES (_LESENSE_PERCTRL_DACCH1DATA_THRES << 3) /**< Shifted mode THRES for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_DACSTARTUP (0x1UL << 6) /**< VDAC Startup Configuration */
-#define _LESENSE_PERCTRL_DACSTARTUP_SHIFT 6 /**< Shift value for LESENSE_DACSTARTUP */
-#define _LESENSE_PERCTRL_DACSTARTUP_MASK 0x40UL /**< Bit mask for LESENSE_DACSTARTUP */
-#define _LESENSE_PERCTRL_DACSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */
-#define _LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE 0x00000000UL /**< Mode FULLCYCLE for LESENSE_PERCTRL */
-#define _LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE 0x00000001UL /**< Mode HALFCYCLE for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_DACSTARTUP_DEFAULT (_LESENSE_PERCTRL_DACSTARTUP_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE (_LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE << 6) /**< Shifted mode FULLCYCLE for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE (_LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE << 6) /**< Shifted mode HALFCYCLE for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_DACCONVTRIG (0x1UL << 8) /**< VDAC Conversion Trigger Configuration */
-#define _LESENSE_PERCTRL_DACCONVTRIG_SHIFT 8 /**< Shift value for LESENSE_DACCONVTRIG */
-#define _LESENSE_PERCTRL_DACCONVTRIG_MASK 0x100UL /**< Bit mask for LESENSE_DACCONVTRIG */
-#define _LESENSE_PERCTRL_DACCONVTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */
-#define _LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART 0x00000000UL /**< Mode CHANNELSTART for LESENSE_PERCTRL */
-#define _LESENSE_PERCTRL_DACCONVTRIG_SCANSTART 0x00000001UL /**< Mode SCANSTART for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_DACCONVTRIG_DEFAULT (_LESENSE_PERCTRL_DACCONVTRIG_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART (_LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART << 8) /**< Shifted mode CHANNELSTART for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_DACCONVTRIG_SCANSTART (_LESENSE_PERCTRL_DACCONVTRIG_SCANSTART << 8) /**< Shifted mode SCANSTART for LESENSE_PERCTRL */
-#define _LESENSE_PERCTRL_ACMP0MODE_SHIFT 20 /**< Shift value for LESENSE_ACMP0MODE */
-#define _LESENSE_PERCTRL_ACMP0MODE_MASK 0x300000UL /**< Bit mask for LESENSE_ACMP0MODE */
-#define _LESENSE_PERCTRL_ACMP0MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */
-#define _LESENSE_PERCTRL_ACMP0MODE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_PERCTRL */
-#define _LESENSE_PERCTRL_ACMP0MODE_MUX 0x00000001UL /**< Mode MUX for LESENSE_PERCTRL */
-#define _LESENSE_PERCTRL_ACMP0MODE_MUXTHRES 0x00000002UL /**< Mode MUXTHRES for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_ACMP0MODE_DEFAULT (_LESENSE_PERCTRL_ACMP0MODE_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_ACMP0MODE_DISABLE (_LESENSE_PERCTRL_ACMP0MODE_DISABLE << 20) /**< Shifted mode DISABLE for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_ACMP0MODE_MUX (_LESENSE_PERCTRL_ACMP0MODE_MUX << 20) /**< Shifted mode MUX for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_ACMP0MODE_MUXTHRES (_LESENSE_PERCTRL_ACMP0MODE_MUXTHRES << 20) /**< Shifted mode MUXTHRES for LESENSE_PERCTRL */
-#define _LESENSE_PERCTRL_ACMP1MODE_SHIFT 22 /**< Shift value for LESENSE_ACMP1MODE */
-#define _LESENSE_PERCTRL_ACMP1MODE_MASK 0xC00000UL /**< Bit mask for LESENSE_ACMP1MODE */
-#define _LESENSE_PERCTRL_ACMP1MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */
-#define _LESENSE_PERCTRL_ACMP1MODE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_PERCTRL */
-#define _LESENSE_PERCTRL_ACMP1MODE_MUX 0x00000001UL /**< Mode MUX for LESENSE_PERCTRL */
-#define _LESENSE_PERCTRL_ACMP1MODE_MUXTHRES 0x00000002UL /**< Mode MUXTHRES for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_ACMP1MODE_DEFAULT (_LESENSE_PERCTRL_ACMP1MODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_ACMP1MODE_DISABLE (_LESENSE_PERCTRL_ACMP1MODE_DISABLE << 22) /**< Shifted mode DISABLE for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_ACMP1MODE_MUX (_LESENSE_PERCTRL_ACMP1MODE_MUX << 22) /**< Shifted mode MUX for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_ACMP1MODE_MUXTHRES (_LESENSE_PERCTRL_ACMP1MODE_MUXTHRES << 22) /**< Shifted mode MUXTHRES for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_ACMP0INV (0x1UL << 24) /**< Invert Analog Comparator 0 Output */
-#define _LESENSE_PERCTRL_ACMP0INV_SHIFT 24 /**< Shift value for LESENSE_ACMP0INV */
-#define _LESENSE_PERCTRL_ACMP0INV_MASK 0x1000000UL /**< Bit mask for LESENSE_ACMP0INV */
-#define _LESENSE_PERCTRL_ACMP0INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_ACMP0INV_DEFAULT (_LESENSE_PERCTRL_ACMP0INV_DEFAULT << 24) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_ACMP1INV (0x1UL << 25) /**< Invert Analog Comparator 1 Output */
-#define _LESENSE_PERCTRL_ACMP1INV_SHIFT 25 /**< Shift value for LESENSE_ACMP1INV */
-#define _LESENSE_PERCTRL_ACMP1INV_MASK 0x2000000UL /**< Bit mask for LESENSE_ACMP1INV */
-#define _LESENSE_PERCTRL_ACMP1INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_ACMP1INV_DEFAULT (_LESENSE_PERCTRL_ACMP1INV_DEFAULT << 25) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_ACMP0HYSTEN (0x1UL << 26) /**< ACMP0 Hysteresis Enable */
-#define _LESENSE_PERCTRL_ACMP0HYSTEN_SHIFT 26 /**< Shift value for LESENSE_ACMP0HYSTEN */
-#define _LESENSE_PERCTRL_ACMP0HYSTEN_MASK 0x4000000UL /**< Bit mask for LESENSE_ACMP0HYSTEN */
-#define _LESENSE_PERCTRL_ACMP0HYSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_ACMP0HYSTEN_DEFAULT (_LESENSE_PERCTRL_ACMP0HYSTEN_DEFAULT << 26) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_ACMP1HYSTEN (0x1UL << 27) /**< ACMP1 Hysteresis Enable */
-#define _LESENSE_PERCTRL_ACMP1HYSTEN_SHIFT 27 /**< Shift value for LESENSE_ACMP1HYSTEN */
-#define _LESENSE_PERCTRL_ACMP1HYSTEN_MASK 0x8000000UL /**< Bit mask for LESENSE_ACMP1HYSTEN */
-#define _LESENSE_PERCTRL_ACMP1HYSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_ACMP1HYSTEN_DEFAULT (_LESENSE_PERCTRL_ACMP1HYSTEN_DEFAULT << 27) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */
-#define _LESENSE_PERCTRL_WARMUPMODE_SHIFT 28 /**< Shift value for LESENSE_WARMUPMODE */
-#define _LESENSE_PERCTRL_WARMUPMODE_MASK 0x30000000UL /**< Bit mask for LESENSE_WARMUPMODE */
-#define _LESENSE_PERCTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */
-#define _LESENSE_PERCTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for LESENSE_PERCTRL */
-#define _LESENSE_PERCTRL_WARMUPMODE_KEEPACMPWARM 0x00000001UL /**< Mode KEEPACMPWARM for LESENSE_PERCTRL */
-#define _LESENSE_PERCTRL_WARMUPMODE_KEEPDACWARM 0x00000002UL /**< Mode KEEPDACWARM for LESENSE_PERCTRL */
-#define _LESENSE_PERCTRL_WARMUPMODE_KEEPACMPDACWARM 0x00000003UL /**< Mode KEEPACMPDACWARM for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_WARMUPMODE_DEFAULT (_LESENSE_PERCTRL_WARMUPMODE_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_WARMUPMODE_NORMAL (_LESENSE_PERCTRL_WARMUPMODE_NORMAL << 28) /**< Shifted mode NORMAL for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_WARMUPMODE_KEEPACMPWARM (_LESENSE_PERCTRL_WARMUPMODE_KEEPACMPWARM << 28) /**< Shifted mode KEEPACMPWARM for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_WARMUPMODE_KEEPDACWARM (_LESENSE_PERCTRL_WARMUPMODE_KEEPDACWARM << 28) /**< Shifted mode KEEPDACWARM for LESENSE_PERCTRL */
-#define LESENSE_PERCTRL_WARMUPMODE_KEEPACMPDACWARM (_LESENSE_PERCTRL_WARMUPMODE_KEEPACMPDACWARM << 28) /**< Shifted mode KEEPACMPDACWARM for LESENSE_PERCTRL */
-
-/* Bit fields for LESENSE DECCTRL */
-#define _LESENSE_DECCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_MASK 0x1EF7BDFFUL /**< Mask for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_DISABLE (0x1UL << 0) /**< Disable the Decoder */
-#define _LESENSE_DECCTRL_DISABLE_SHIFT 0 /**< Shift value for LESENSE_DISABLE */
-#define _LESENSE_DECCTRL_DISABLE_MASK 0x1UL /**< Bit mask for LESENSE_DISABLE */
-#define _LESENSE_DECCTRL_DISABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_DISABLE_DEFAULT (_LESENSE_DECCTRL_DISABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_ERRCHK (0x1UL << 1) /**< Enable Check of Current State */
-#define _LESENSE_DECCTRL_ERRCHK_SHIFT 1 /**< Shift value for LESENSE_ERRCHK */
-#define _LESENSE_DECCTRL_ERRCHK_MASK 0x2UL /**< Bit mask for LESENSE_ERRCHK */
-#define _LESENSE_DECCTRL_ERRCHK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_ERRCHK_DEFAULT (_LESENSE_DECCTRL_ERRCHK_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_INTMAP (0x1UL << 2) /**< Enable Decoder to Channel Interrupt Mapping */
-#define _LESENSE_DECCTRL_INTMAP_SHIFT 2 /**< Shift value for LESENSE_INTMAP */
-#define _LESENSE_DECCTRL_INTMAP_MASK 0x4UL /**< Bit mask for LESENSE_INTMAP */
-#define _LESENSE_DECCTRL_INTMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_INTMAP_DEFAULT (_LESENSE_DECCTRL_INTMAP_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_HYSTPRS0 (0x1UL << 3) /**< Enable Decoder Hysteresis on PRS0 Output */
-#define _LESENSE_DECCTRL_HYSTPRS0_SHIFT 3 /**< Shift value for LESENSE_HYSTPRS0 */
-#define _LESENSE_DECCTRL_HYSTPRS0_MASK 0x8UL /**< Bit mask for LESENSE_HYSTPRS0 */
-#define _LESENSE_DECCTRL_HYSTPRS0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_HYSTPRS0_DEFAULT (_LESENSE_DECCTRL_HYSTPRS0_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_HYSTPRS1 (0x1UL << 4) /**< Enable Decoder Hysteresis on PRS1 Output */
-#define _LESENSE_DECCTRL_HYSTPRS1_SHIFT 4 /**< Shift value for LESENSE_HYSTPRS1 */
-#define _LESENSE_DECCTRL_HYSTPRS1_MASK 0x10UL /**< Bit mask for LESENSE_HYSTPRS1 */
-#define _LESENSE_DECCTRL_HYSTPRS1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_HYSTPRS1_DEFAULT (_LESENSE_DECCTRL_HYSTPRS1_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_HYSTPRS2 (0x1UL << 5) /**< Enable Decoder Hysteresis on PRS2 Output */
-#define _LESENSE_DECCTRL_HYSTPRS2_SHIFT 5 /**< Shift value for LESENSE_HYSTPRS2 */
-#define _LESENSE_DECCTRL_HYSTPRS2_MASK 0x20UL /**< Bit mask for LESENSE_HYSTPRS2 */
-#define _LESENSE_DECCTRL_HYSTPRS2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_HYSTPRS2_DEFAULT (_LESENSE_DECCTRL_HYSTPRS2_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_HYSTIRQ (0x1UL << 6) /**< Enable Decoder Hysteresis on Interrupt Requests */
-#define _LESENSE_DECCTRL_HYSTIRQ_SHIFT 6 /**< Shift value for LESENSE_HYSTIRQ */
-#define _LESENSE_DECCTRL_HYSTIRQ_MASK 0x40UL /**< Bit mask for LESENSE_HYSTIRQ */
-#define _LESENSE_DECCTRL_HYSTIRQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_HYSTIRQ_DEFAULT (_LESENSE_DECCTRL_HYSTIRQ_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSCNT (0x1UL << 7) /**< Enable Count Mode on Decoder PRS Channels 0 and 1 */
-#define _LESENSE_DECCTRL_PRSCNT_SHIFT 7 /**< Shift value for LESENSE_PRSCNT */
-#define _LESENSE_DECCTRL_PRSCNT_MASK 0x80UL /**< Bit mask for LESENSE_PRSCNT */
-#define _LESENSE_DECCTRL_PRSCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSCNT_DEFAULT (_LESENSE_DECCTRL_PRSCNT_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_INPUT (0x1UL << 8) /**< LESENSE Decoder Input Configuration */
-#define _LESENSE_DECCTRL_INPUT_SHIFT 8 /**< Shift value for LESENSE_INPUT */
-#define _LESENSE_DECCTRL_INPUT_MASK 0x100UL /**< Bit mask for LESENSE_INPUT */
-#define _LESENSE_DECCTRL_INPUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_INPUT_SENSORSTATE 0x00000000UL /**< Mode SENSORSTATE for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_INPUT_PRS 0x00000001UL /**< Mode PRS for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_INPUT_DEFAULT (_LESENSE_DECCTRL_INPUT_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_INPUT_SENSORSTATE (_LESENSE_DECCTRL_INPUT_SENSORSTATE << 8) /**< Shifted mode SENSORSTATE for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_INPUT_PRS (_LESENSE_DECCTRL_INPUT_PRS << 8) /**< Shifted mode PRS for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL0_SHIFT 10 /**< Shift value for LESENSE_PRSSEL0 */
-#define _LESENSE_DECCTRL_PRSSEL0_MASK 0x3C00UL /**< Bit mask for LESENSE_PRSSEL0 */
-#define _LESENSE_DECCTRL_PRSSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL0_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL0_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL0_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL0_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL0_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL0_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL0_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL0_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL0_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL0_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL0_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL0_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL0_DEFAULT (_LESENSE_DECCTRL_PRSSEL0_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL0_PRSCH0 (_LESENSE_DECCTRL_PRSSEL0_PRSCH0 << 10) /**< Shifted mode PRSCH0 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL0_PRSCH1 (_LESENSE_DECCTRL_PRSSEL0_PRSCH1 << 10) /**< Shifted mode PRSCH1 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL0_PRSCH2 (_LESENSE_DECCTRL_PRSSEL0_PRSCH2 << 10) /**< Shifted mode PRSCH2 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL0_PRSCH3 (_LESENSE_DECCTRL_PRSSEL0_PRSCH3 << 10) /**< Shifted mode PRSCH3 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL0_PRSCH4 (_LESENSE_DECCTRL_PRSSEL0_PRSCH4 << 10) /**< Shifted mode PRSCH4 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL0_PRSCH5 (_LESENSE_DECCTRL_PRSSEL0_PRSCH5 << 10) /**< Shifted mode PRSCH5 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL0_PRSCH6 (_LESENSE_DECCTRL_PRSSEL0_PRSCH6 << 10) /**< Shifted mode PRSCH6 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL0_PRSCH7 (_LESENSE_DECCTRL_PRSSEL0_PRSCH7 << 10) /**< Shifted mode PRSCH7 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL0_PRSCH8 (_LESENSE_DECCTRL_PRSSEL0_PRSCH8 << 10) /**< Shifted mode PRSCH8 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL0_PRSCH9 (_LESENSE_DECCTRL_PRSSEL0_PRSCH9 << 10) /**< Shifted mode PRSCH9 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL0_PRSCH10 (_LESENSE_DECCTRL_PRSSEL0_PRSCH10 << 10) /**< Shifted mode PRSCH10 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL0_PRSCH11 (_LESENSE_DECCTRL_PRSSEL0_PRSCH11 << 10) /**< Shifted mode PRSCH11 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL1_SHIFT 15 /**< Shift value for LESENSE_PRSSEL1 */
-#define _LESENSE_DECCTRL_PRSSEL1_MASK 0x78000UL /**< Bit mask for LESENSE_PRSSEL1 */
-#define _LESENSE_DECCTRL_PRSSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL1_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL1_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL1_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL1_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL1_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL1_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL1_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL1_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL1_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL1_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL1_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL1_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL1_DEFAULT (_LESENSE_DECCTRL_PRSSEL1_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL1_PRSCH0 (_LESENSE_DECCTRL_PRSSEL1_PRSCH0 << 15) /**< Shifted mode PRSCH0 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL1_PRSCH1 (_LESENSE_DECCTRL_PRSSEL1_PRSCH1 << 15) /**< Shifted mode PRSCH1 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL1_PRSCH2 (_LESENSE_DECCTRL_PRSSEL1_PRSCH2 << 15) /**< Shifted mode PRSCH2 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL1_PRSCH3 (_LESENSE_DECCTRL_PRSSEL1_PRSCH3 << 15) /**< Shifted mode PRSCH3 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL1_PRSCH4 (_LESENSE_DECCTRL_PRSSEL1_PRSCH4 << 15) /**< Shifted mode PRSCH4 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL1_PRSCH5 (_LESENSE_DECCTRL_PRSSEL1_PRSCH5 << 15) /**< Shifted mode PRSCH5 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL1_PRSCH6 (_LESENSE_DECCTRL_PRSSEL1_PRSCH6 << 15) /**< Shifted mode PRSCH6 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL1_PRSCH7 (_LESENSE_DECCTRL_PRSSEL1_PRSCH7 << 15) /**< Shifted mode PRSCH7 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL1_PRSCH8 (_LESENSE_DECCTRL_PRSSEL1_PRSCH8 << 15) /**< Shifted mode PRSCH8 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL1_PRSCH9 (_LESENSE_DECCTRL_PRSSEL1_PRSCH9 << 15) /**< Shifted mode PRSCH9 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL1_PRSCH10 (_LESENSE_DECCTRL_PRSSEL1_PRSCH10 << 15) /**< Shifted mode PRSCH10 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL1_PRSCH11 (_LESENSE_DECCTRL_PRSSEL1_PRSCH11 << 15) /**< Shifted mode PRSCH11 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL2_SHIFT 20 /**< Shift value for LESENSE_PRSSEL2 */
-#define _LESENSE_DECCTRL_PRSSEL2_MASK 0xF00000UL /**< Bit mask for LESENSE_PRSSEL2 */
-#define _LESENSE_DECCTRL_PRSSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL2_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL2_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL2_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL2_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL2_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL2_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL2_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL2_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL2_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL2_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL2_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL2_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL2_DEFAULT (_LESENSE_DECCTRL_PRSSEL2_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL2_PRSCH0 (_LESENSE_DECCTRL_PRSSEL2_PRSCH0 << 20) /**< Shifted mode PRSCH0 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL2_PRSCH1 (_LESENSE_DECCTRL_PRSSEL2_PRSCH1 << 20) /**< Shifted mode PRSCH1 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL2_PRSCH2 (_LESENSE_DECCTRL_PRSSEL2_PRSCH2 << 20) /**< Shifted mode PRSCH2 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL2_PRSCH3 (_LESENSE_DECCTRL_PRSSEL2_PRSCH3 << 20) /**< Shifted mode PRSCH3 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL2_PRSCH4 (_LESENSE_DECCTRL_PRSSEL2_PRSCH4 << 20) /**< Shifted mode PRSCH4 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL2_PRSCH5 (_LESENSE_DECCTRL_PRSSEL2_PRSCH5 << 20) /**< Shifted mode PRSCH5 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL2_PRSCH6 (_LESENSE_DECCTRL_PRSSEL2_PRSCH6 << 20) /**< Shifted mode PRSCH6 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL2_PRSCH7 (_LESENSE_DECCTRL_PRSSEL2_PRSCH7 << 20) /**< Shifted mode PRSCH7 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL2_PRSCH8 (_LESENSE_DECCTRL_PRSSEL2_PRSCH8 << 20) /**< Shifted mode PRSCH8 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL2_PRSCH9 (_LESENSE_DECCTRL_PRSSEL2_PRSCH9 << 20) /**< Shifted mode PRSCH9 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL2_PRSCH10 (_LESENSE_DECCTRL_PRSSEL2_PRSCH10 << 20) /**< Shifted mode PRSCH10 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL2_PRSCH11 (_LESENSE_DECCTRL_PRSSEL2_PRSCH11 << 20) /**< Shifted mode PRSCH11 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL3_SHIFT 25 /**< Shift value for LESENSE_PRSSEL3 */
-#define _LESENSE_DECCTRL_PRSSEL3_MASK 0x1E000000UL /**< Bit mask for LESENSE_PRSSEL3 */
-#define _LESENSE_DECCTRL_PRSSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL3_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL3_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL3_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL3_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL3_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL3_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL3_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL3_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL3_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL3_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL3_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_DECCTRL */
-#define _LESENSE_DECCTRL_PRSSEL3_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL3_DEFAULT (_LESENSE_DECCTRL_PRSSEL3_DEFAULT << 25) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL3_PRSCH0 (_LESENSE_DECCTRL_PRSSEL3_PRSCH0 << 25) /**< Shifted mode PRSCH0 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL3_PRSCH1 (_LESENSE_DECCTRL_PRSSEL3_PRSCH1 << 25) /**< Shifted mode PRSCH1 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL3_PRSCH2 (_LESENSE_DECCTRL_PRSSEL3_PRSCH2 << 25) /**< Shifted mode PRSCH2 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL3_PRSCH3 (_LESENSE_DECCTRL_PRSSEL3_PRSCH3 << 25) /**< Shifted mode PRSCH3 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL3_PRSCH4 (_LESENSE_DECCTRL_PRSSEL3_PRSCH4 << 25) /**< Shifted mode PRSCH4 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL3_PRSCH5 (_LESENSE_DECCTRL_PRSSEL3_PRSCH5 << 25) /**< Shifted mode PRSCH5 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL3_PRSCH6 (_LESENSE_DECCTRL_PRSSEL3_PRSCH6 << 25) /**< Shifted mode PRSCH6 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL3_PRSCH7 (_LESENSE_DECCTRL_PRSSEL3_PRSCH7 << 25) /**< Shifted mode PRSCH7 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL3_PRSCH8 (_LESENSE_DECCTRL_PRSSEL3_PRSCH8 << 25) /**< Shifted mode PRSCH8 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL3_PRSCH9 (_LESENSE_DECCTRL_PRSSEL3_PRSCH9 << 25) /**< Shifted mode PRSCH9 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL3_PRSCH10 (_LESENSE_DECCTRL_PRSSEL3_PRSCH10 << 25) /**< Shifted mode PRSCH10 for LESENSE_DECCTRL */
-#define LESENSE_DECCTRL_PRSSEL3_PRSCH11 (_LESENSE_DECCTRL_PRSSEL3_PRSCH11 << 25) /**< Shifted mode PRSCH11 for LESENSE_DECCTRL */
-
-/* Bit fields for LESENSE BIASCTRL */
-#define _LESENSE_BIASCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_BIASCTRL */
-#define _LESENSE_BIASCTRL_MASK 0x00000003UL /**< Mask for LESENSE_BIASCTRL */
-#define _LESENSE_BIASCTRL_BIASMODE_SHIFT 0 /**< Shift value for LESENSE_BIASMODE */
-#define _LESENSE_BIASCTRL_BIASMODE_MASK 0x3UL /**< Bit mask for LESENSE_BIASMODE */
-#define _LESENSE_BIASCTRL_BIASMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BIASCTRL */
-#define _LESENSE_BIASCTRL_BIASMODE_DONTTOUCH 0x00000000UL /**< Mode DONTTOUCH for LESENSE_BIASCTRL */
-#define _LESENSE_BIASCTRL_BIASMODE_DUTYCYCLE 0x00000001UL /**< Mode DUTYCYCLE for LESENSE_BIASCTRL */
-#define _LESENSE_BIASCTRL_BIASMODE_HIGHACC 0x00000002UL /**< Mode HIGHACC for LESENSE_BIASCTRL */
-#define LESENSE_BIASCTRL_BIASMODE_DEFAULT (_LESENSE_BIASCTRL_BIASMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_BIASCTRL */
-#define LESENSE_BIASCTRL_BIASMODE_DONTTOUCH (_LESENSE_BIASCTRL_BIASMODE_DONTTOUCH << 0) /**< Shifted mode DONTTOUCH for LESENSE_BIASCTRL */
-#define LESENSE_BIASCTRL_BIASMODE_DUTYCYCLE (_LESENSE_BIASCTRL_BIASMODE_DUTYCYCLE << 0) /**< Shifted mode DUTYCYCLE for LESENSE_BIASCTRL */
-#define LESENSE_BIASCTRL_BIASMODE_HIGHACC (_LESENSE_BIASCTRL_BIASMODE_HIGHACC << 0) /**< Shifted mode HIGHACC for LESENSE_BIASCTRL */
-
-/* Bit fields for LESENSE EVALCTRL */
-#define _LESENSE_EVALCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_EVALCTRL */
-#define _LESENSE_EVALCTRL_MASK 0x0000FFFFUL /**< Mask for LESENSE_EVALCTRL */
-#define _LESENSE_EVALCTRL_WINSIZE_SHIFT 0 /**< Shift value for LESENSE_WINSIZE */
-#define _LESENSE_EVALCTRL_WINSIZE_MASK 0xFFFFUL /**< Bit mask for LESENSE_WINSIZE */
-#define _LESENSE_EVALCTRL_WINSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_EVALCTRL */
-#define LESENSE_EVALCTRL_WINSIZE_DEFAULT (_LESENSE_EVALCTRL_WINSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_EVALCTRL */
-
-/* Bit fields for LESENSE PRSCTRL */
-#define _LESENSE_PRSCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PRSCTRL */
-#define _LESENSE_PRSCTRL_MASK 0x00011F1FUL /**< Mask for LESENSE_PRSCTRL */
-#define _LESENSE_PRSCTRL_DECCMPVAL_SHIFT 0 /**< Shift value for LESENSE_DECCMPVAL */
-#define _LESENSE_PRSCTRL_DECCMPVAL_MASK 0x1FUL /**< Bit mask for LESENSE_DECCMPVAL */
-#define _LESENSE_PRSCTRL_DECCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */
-#define LESENSE_PRSCTRL_DECCMPVAL_DEFAULT (_LESENSE_PRSCTRL_DECCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */
-#define _LESENSE_PRSCTRL_DECCMPMASK_SHIFT 8 /**< Shift value for LESENSE_DECCMPMASK */
-#define _LESENSE_PRSCTRL_DECCMPMASK_MASK 0x1F00UL /**< Bit mask for LESENSE_DECCMPMASK */
-#define _LESENSE_PRSCTRL_DECCMPMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */
-#define LESENSE_PRSCTRL_DECCMPMASK_DEFAULT (_LESENSE_PRSCTRL_DECCMPMASK_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */
-#define LESENSE_PRSCTRL_DECCMPEN (0x1UL << 16) /**< Enable PRS Output DECCMP */
-#define _LESENSE_PRSCTRL_DECCMPEN_SHIFT 16 /**< Shift value for LESENSE_DECCMPEN */
-#define _LESENSE_PRSCTRL_DECCMPEN_MASK 0x10000UL /**< Bit mask for LESENSE_DECCMPEN */
-#define _LESENSE_PRSCTRL_DECCMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */
-#define LESENSE_PRSCTRL_DECCMPEN_DEFAULT (_LESENSE_PRSCTRL_DECCMPEN_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */
-
-/* Bit fields for LESENSE CMD */
-#define _LESENSE_CMD_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CMD */
-#define _LESENSE_CMD_MASK 0x0000000FUL /**< Mask for LESENSE_CMD */
-#define LESENSE_CMD_START (0x1UL << 0) /**< Start Scanning of Sensors */
-#define _LESENSE_CMD_START_SHIFT 0 /**< Shift value for LESENSE_START */
-#define _LESENSE_CMD_START_MASK 0x1UL /**< Bit mask for LESENSE_START */
-#define _LESENSE_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */
-#define LESENSE_CMD_START_DEFAULT (_LESENSE_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CMD */
-#define LESENSE_CMD_STOP (0x1UL << 1) /**< Stop Scanning of Sensors */
-#define _LESENSE_CMD_STOP_SHIFT 1 /**< Shift value for LESENSE_STOP */
-#define _LESENSE_CMD_STOP_MASK 0x2UL /**< Bit mask for LESENSE_STOP */
-#define _LESENSE_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */
-#define LESENSE_CMD_STOP_DEFAULT (_LESENSE_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_CMD */
-#define LESENSE_CMD_DECODE (0x1UL << 2) /**< Start Decoder */
-#define _LESENSE_CMD_DECODE_SHIFT 2 /**< Shift value for LESENSE_DECODE */
-#define _LESENSE_CMD_DECODE_MASK 0x4UL /**< Bit mask for LESENSE_DECODE */
-#define _LESENSE_CMD_DECODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */
-#define LESENSE_CMD_DECODE_DEFAULT (_LESENSE_CMD_DECODE_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_CMD */
-#define LESENSE_CMD_CLEARBUF (0x1UL << 3) /**< Clear Result Buffer */
-#define _LESENSE_CMD_CLEARBUF_SHIFT 3 /**< Shift value for LESENSE_CLEARBUF */
-#define _LESENSE_CMD_CLEARBUF_MASK 0x8UL /**< Bit mask for LESENSE_CLEARBUF */
-#define _LESENSE_CMD_CLEARBUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */
-#define LESENSE_CMD_CLEARBUF_DEFAULT (_LESENSE_CMD_CLEARBUF_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_CMD */
-
-/* Bit fields for LESENSE CHEN */
-#define _LESENSE_CHEN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CHEN */
-#define _LESENSE_CHEN_MASK 0x0000FFFFUL /**< Mask for LESENSE_CHEN */
-#define _LESENSE_CHEN_CHEN_SHIFT 0 /**< Shift value for LESENSE_CHEN */
-#define _LESENSE_CHEN_CHEN_MASK 0xFFFFUL /**< Bit mask for LESENSE_CHEN */
-#define _LESENSE_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CHEN */
-#define LESENSE_CHEN_CHEN_DEFAULT (_LESENSE_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CHEN */
-
-/* Bit fields for LESENSE SCANRES */
-#define _LESENSE_SCANRES_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SCANRES */
-#define _LESENSE_SCANRES_MASK 0xFFFFFFFFUL /**< Mask for LESENSE_SCANRES */
-#define _LESENSE_SCANRES_SCANRES_SHIFT 0 /**< Shift value for LESENSE_SCANRES */
-#define _LESENSE_SCANRES_SCANRES_MASK 0xFFFFUL /**< Bit mask for LESENSE_SCANRES */
-#define _LESENSE_SCANRES_SCANRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SCANRES */
-#define LESENSE_SCANRES_SCANRES_DEFAULT (_LESENSE_SCANRES_SCANRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SCANRES */
-#define _LESENSE_SCANRES_STEPDIR_SHIFT 16 /**< Shift value for LESENSE_STEPDIR */
-#define _LESENSE_SCANRES_STEPDIR_MASK 0xFFFF0000UL /**< Bit mask for LESENSE_STEPDIR */
-#define _LESENSE_SCANRES_STEPDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SCANRES */
-#define LESENSE_SCANRES_STEPDIR_DEFAULT (_LESENSE_SCANRES_STEPDIR_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_SCANRES */
-
-/* Bit fields for LESENSE STATUS */
-#define _LESENSE_STATUS_RESETVALUE 0x00000000UL /**< Default value for LESENSE_STATUS */
-#define _LESENSE_STATUS_MASK 0x0000003FUL /**< Mask for LESENSE_STATUS */
-#define LESENSE_STATUS_BUFDATAV (0x1UL << 0) /**< Result Data Valid */
-#define _LESENSE_STATUS_BUFDATAV_SHIFT 0 /**< Shift value for LESENSE_BUFDATAV */
-#define _LESENSE_STATUS_BUFDATAV_MASK 0x1UL /**< Bit mask for LESENSE_BUFDATAV */
-#define _LESENSE_STATUS_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */
-#define LESENSE_STATUS_BUFDATAV_DEFAULT (_LESENSE_STATUS_BUFDATAV_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_STATUS */
-#define LESENSE_STATUS_BUFHALFFULL (0x1UL << 1) /**< Result Buffer Half Full */
-#define _LESENSE_STATUS_BUFHALFFULL_SHIFT 1 /**< Shift value for LESENSE_BUFHALFFULL */
-#define _LESENSE_STATUS_BUFHALFFULL_MASK 0x2UL /**< Bit mask for LESENSE_BUFHALFFULL */
-#define _LESENSE_STATUS_BUFHALFFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */
-#define LESENSE_STATUS_BUFHALFFULL_DEFAULT (_LESENSE_STATUS_BUFHALFFULL_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_STATUS */
-#define LESENSE_STATUS_BUFFULL (0x1UL << 2) /**< Result Buffer Full */
-#define _LESENSE_STATUS_BUFFULL_SHIFT 2 /**< Shift value for LESENSE_BUFFULL */
-#define _LESENSE_STATUS_BUFFULL_MASK 0x4UL /**< Bit mask for LESENSE_BUFFULL */
-#define _LESENSE_STATUS_BUFFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */
-#define LESENSE_STATUS_BUFFULL_DEFAULT (_LESENSE_STATUS_BUFFULL_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_STATUS */
-#define LESENSE_STATUS_RUNNING (0x1UL << 3) /**< LESENSE Periodic Counter Running */
-#define _LESENSE_STATUS_RUNNING_SHIFT 3 /**< Shift value for LESENSE_RUNNING */
-#define _LESENSE_STATUS_RUNNING_MASK 0x8UL /**< Bit mask for LESENSE_RUNNING */
-#define _LESENSE_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */
-#define LESENSE_STATUS_RUNNING_DEFAULT (_LESENSE_STATUS_RUNNING_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_STATUS */
-#define LESENSE_STATUS_SCANACTIVE (0x1UL << 4) /**< LESENSE Scan Active */
-#define _LESENSE_STATUS_SCANACTIVE_SHIFT 4 /**< Shift value for LESENSE_SCANACTIVE */
-#define _LESENSE_STATUS_SCANACTIVE_MASK 0x10UL /**< Bit mask for LESENSE_SCANACTIVE */
-#define _LESENSE_STATUS_SCANACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */
-#define LESENSE_STATUS_SCANACTIVE_DEFAULT (_LESENSE_STATUS_SCANACTIVE_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_STATUS */
-#define LESENSE_STATUS_DACACTIVE (0x1UL << 5) /**< LESENSE VDAC Interface is Active */
-#define _LESENSE_STATUS_DACACTIVE_SHIFT 5 /**< Shift value for LESENSE_DACACTIVE */
-#define _LESENSE_STATUS_DACACTIVE_MASK 0x20UL /**< Bit mask for LESENSE_DACACTIVE */
-#define _LESENSE_STATUS_DACACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */
-#define LESENSE_STATUS_DACACTIVE_DEFAULT (_LESENSE_STATUS_DACACTIVE_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_STATUS */
-
-/* Bit fields for LESENSE PTR */
-#define _LESENSE_PTR_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PTR */
-#define _LESENSE_PTR_MASK 0x000000FFUL /**< Mask for LESENSE_PTR */
-#define _LESENSE_PTR_RD_SHIFT 0 /**< Shift value for LESENSE_RD */
-#define _LESENSE_PTR_RD_MASK 0xFUL /**< Bit mask for LESENSE_RD */
-#define _LESENSE_PTR_RD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PTR */
-#define LESENSE_PTR_RD_DEFAULT (_LESENSE_PTR_RD_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_PTR */
-#define _LESENSE_PTR_WR_SHIFT 4 /**< Shift value for LESENSE_WR */
-#define _LESENSE_PTR_WR_MASK 0xF0UL /**< Bit mask for LESENSE_WR */
-#define _LESENSE_PTR_WR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PTR */
-#define LESENSE_PTR_WR_DEFAULT (_LESENSE_PTR_WR_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_PTR */
-
-/* Bit fields for LESENSE BUFDATA */
-#define _LESENSE_BUFDATA_RESETVALUE 0x00000000UL /**< Default value for LESENSE_BUFDATA */
-#define _LESENSE_BUFDATA_MASK 0x000FFFFFUL /**< Mask for LESENSE_BUFDATA */
-#define _LESENSE_BUFDATA_BUFDATA_SHIFT 0 /**< Shift value for LESENSE_BUFDATA */
-#define _LESENSE_BUFDATA_BUFDATA_MASK 0xFFFFUL /**< Bit mask for LESENSE_BUFDATA */
-#define _LESENSE_BUFDATA_BUFDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BUFDATA */
-#define LESENSE_BUFDATA_BUFDATA_DEFAULT (_LESENSE_BUFDATA_BUFDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_BUFDATA */
-#define _LESENSE_BUFDATA_BUFDATASRC_SHIFT 16 /**< Shift value for LESENSE_BUFDATASRC */
-#define _LESENSE_BUFDATA_BUFDATASRC_MASK 0xF0000UL /**< Bit mask for LESENSE_BUFDATASRC */
-#define _LESENSE_BUFDATA_BUFDATASRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BUFDATA */
-#define LESENSE_BUFDATA_BUFDATASRC_DEFAULT (_LESENSE_BUFDATA_BUFDATASRC_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_BUFDATA */
-
-/* Bit fields for LESENSE CURCH */
-#define _LESENSE_CURCH_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CURCH */
-#define _LESENSE_CURCH_MASK 0x0000000FUL /**< Mask for LESENSE_CURCH */
-#define _LESENSE_CURCH_CURCH_SHIFT 0 /**< Shift value for LESENSE_CURCH */
-#define _LESENSE_CURCH_CURCH_MASK 0xFUL /**< Bit mask for LESENSE_CURCH */
-#define _LESENSE_CURCH_CURCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CURCH */
-#define LESENSE_CURCH_CURCH_DEFAULT (_LESENSE_CURCH_CURCH_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CURCH */
-
-/* Bit fields for LESENSE DECSTATE */
-#define _LESENSE_DECSTATE_RESETVALUE 0x00000000UL /**< Default value for LESENSE_DECSTATE */
-#define _LESENSE_DECSTATE_MASK 0x0000001FUL /**< Mask for LESENSE_DECSTATE */
-#define _LESENSE_DECSTATE_DECSTATE_SHIFT 0 /**< Shift value for LESENSE_DECSTATE */
-#define _LESENSE_DECSTATE_DECSTATE_MASK 0x1FUL /**< Bit mask for LESENSE_DECSTATE */
-#define _LESENSE_DECSTATE_DECSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECSTATE */
-#define LESENSE_DECSTATE_DECSTATE_DEFAULT (_LESENSE_DECSTATE_DECSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_DECSTATE */
-
-/* Bit fields for LESENSE SENSORSTATE */
-#define _LESENSE_SENSORSTATE_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SENSORSTATE */
-#define _LESENSE_SENSORSTATE_MASK 0x0000000FUL /**< Mask for LESENSE_SENSORSTATE */
-#define _LESENSE_SENSORSTATE_SENSORSTATE_SHIFT 0 /**< Shift value for LESENSE_SENSORSTATE */
-#define _LESENSE_SENSORSTATE_SENSORSTATE_MASK 0xFUL /**< Bit mask for LESENSE_SENSORSTATE */
-#define _LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SENSORSTATE */
-#define LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT (_LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SENSORSTATE */
-
-/* Bit fields for LESENSE IDLECONF */
-#define _LESENSE_IDLECONF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_MASK 0xFFFFFFFFUL /**< Mask for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */
-#define _LESENSE_IDLECONF_CH0_MASK 0x3UL /**< Bit mask for LESENSE_CH0 */
-#define _LESENSE_IDLECONF_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH0_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH0_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH0_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH0_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH0_DEFAULT (_LESENSE_IDLECONF_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH0_DISABLE (_LESENSE_IDLECONF_CH0_DISABLE << 0) /**< Shifted mode DISABLE for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH0_HIGH (_LESENSE_IDLECONF_CH0_HIGH << 0) /**< Shifted mode HIGH for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH0_LOW (_LESENSE_IDLECONF_CH0_LOW << 0) /**< Shifted mode LOW for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH0_DAC (_LESENSE_IDLECONF_CH0_DAC << 0) /**< Shifted mode DAC for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH1_SHIFT 2 /**< Shift value for LESENSE_CH1 */
-#define _LESENSE_IDLECONF_CH1_MASK 0xCUL /**< Bit mask for LESENSE_CH1 */
-#define _LESENSE_IDLECONF_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH1_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH1_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH1_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH1_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH1_DEFAULT (_LESENSE_IDLECONF_CH1_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH1_DISABLE (_LESENSE_IDLECONF_CH1_DISABLE << 2) /**< Shifted mode DISABLE for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH1_HIGH (_LESENSE_IDLECONF_CH1_HIGH << 2) /**< Shifted mode HIGH for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH1_LOW (_LESENSE_IDLECONF_CH1_LOW << 2) /**< Shifted mode LOW for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH1_DAC (_LESENSE_IDLECONF_CH1_DAC << 2) /**< Shifted mode DAC for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH2_SHIFT 4 /**< Shift value for LESENSE_CH2 */
-#define _LESENSE_IDLECONF_CH2_MASK 0x30UL /**< Bit mask for LESENSE_CH2 */
-#define _LESENSE_IDLECONF_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH2_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH2_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH2_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH2_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH2_DEFAULT (_LESENSE_IDLECONF_CH2_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH2_DISABLE (_LESENSE_IDLECONF_CH2_DISABLE << 4) /**< Shifted mode DISABLE for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH2_HIGH (_LESENSE_IDLECONF_CH2_HIGH << 4) /**< Shifted mode HIGH for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH2_LOW (_LESENSE_IDLECONF_CH2_LOW << 4) /**< Shifted mode LOW for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH2_DAC (_LESENSE_IDLECONF_CH2_DAC << 4) /**< Shifted mode DAC for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH3_SHIFT 6 /**< Shift value for LESENSE_CH3 */
-#define _LESENSE_IDLECONF_CH3_MASK 0xC0UL /**< Bit mask for LESENSE_CH3 */
-#define _LESENSE_IDLECONF_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH3_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH3_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH3_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH3_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH3_DEFAULT (_LESENSE_IDLECONF_CH3_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH3_DISABLE (_LESENSE_IDLECONF_CH3_DISABLE << 6) /**< Shifted mode DISABLE for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH3_HIGH (_LESENSE_IDLECONF_CH3_HIGH << 6) /**< Shifted mode HIGH for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH3_LOW (_LESENSE_IDLECONF_CH3_LOW << 6) /**< Shifted mode LOW for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH3_DAC (_LESENSE_IDLECONF_CH3_DAC << 6) /**< Shifted mode DAC for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH4_SHIFT 8 /**< Shift value for LESENSE_CH4 */
-#define _LESENSE_IDLECONF_CH4_MASK 0x300UL /**< Bit mask for LESENSE_CH4 */
-#define _LESENSE_IDLECONF_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH4_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH4_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH4_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH4_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH4_DEFAULT (_LESENSE_IDLECONF_CH4_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH4_DISABLE (_LESENSE_IDLECONF_CH4_DISABLE << 8) /**< Shifted mode DISABLE for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH4_HIGH (_LESENSE_IDLECONF_CH4_HIGH << 8) /**< Shifted mode HIGH for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH4_LOW (_LESENSE_IDLECONF_CH4_LOW << 8) /**< Shifted mode LOW for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH4_DAC (_LESENSE_IDLECONF_CH4_DAC << 8) /**< Shifted mode DAC for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH5_SHIFT 10 /**< Shift value for LESENSE_CH5 */
-#define _LESENSE_IDLECONF_CH5_MASK 0xC00UL /**< Bit mask for LESENSE_CH5 */
-#define _LESENSE_IDLECONF_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH5_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH5_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH5_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH5_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH5_DEFAULT (_LESENSE_IDLECONF_CH5_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH5_DISABLE (_LESENSE_IDLECONF_CH5_DISABLE << 10) /**< Shifted mode DISABLE for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH5_HIGH (_LESENSE_IDLECONF_CH5_HIGH << 10) /**< Shifted mode HIGH for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH5_LOW (_LESENSE_IDLECONF_CH5_LOW << 10) /**< Shifted mode LOW for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH5_DAC (_LESENSE_IDLECONF_CH5_DAC << 10) /**< Shifted mode DAC for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH6_SHIFT 12 /**< Shift value for LESENSE_CH6 */
-#define _LESENSE_IDLECONF_CH6_MASK 0x3000UL /**< Bit mask for LESENSE_CH6 */
-#define _LESENSE_IDLECONF_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH6_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH6_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH6_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH6_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH6_DEFAULT (_LESENSE_IDLECONF_CH6_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH6_DISABLE (_LESENSE_IDLECONF_CH6_DISABLE << 12) /**< Shifted mode DISABLE for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH6_HIGH (_LESENSE_IDLECONF_CH6_HIGH << 12) /**< Shifted mode HIGH for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH6_LOW (_LESENSE_IDLECONF_CH6_LOW << 12) /**< Shifted mode LOW for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH6_DAC (_LESENSE_IDLECONF_CH6_DAC << 12) /**< Shifted mode DAC for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH7_SHIFT 14 /**< Shift value for LESENSE_CH7 */
-#define _LESENSE_IDLECONF_CH7_MASK 0xC000UL /**< Bit mask for LESENSE_CH7 */
-#define _LESENSE_IDLECONF_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH7_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH7_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH7_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH7_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH7_DEFAULT (_LESENSE_IDLECONF_CH7_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH7_DISABLE (_LESENSE_IDLECONF_CH7_DISABLE << 14) /**< Shifted mode DISABLE for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH7_HIGH (_LESENSE_IDLECONF_CH7_HIGH << 14) /**< Shifted mode HIGH for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH7_LOW (_LESENSE_IDLECONF_CH7_LOW << 14) /**< Shifted mode LOW for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH7_DAC (_LESENSE_IDLECONF_CH7_DAC << 14) /**< Shifted mode DAC for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH8_SHIFT 16 /**< Shift value for LESENSE_CH8 */
-#define _LESENSE_IDLECONF_CH8_MASK 0x30000UL /**< Bit mask for LESENSE_CH8 */
-#define _LESENSE_IDLECONF_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH8_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH8_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH8_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH8_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH8_DEFAULT (_LESENSE_IDLECONF_CH8_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH8_DISABLE (_LESENSE_IDLECONF_CH8_DISABLE << 16) /**< Shifted mode DISABLE for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH8_HIGH (_LESENSE_IDLECONF_CH8_HIGH << 16) /**< Shifted mode HIGH for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH8_LOW (_LESENSE_IDLECONF_CH8_LOW << 16) /**< Shifted mode LOW for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH8_DAC (_LESENSE_IDLECONF_CH8_DAC << 16) /**< Shifted mode DAC for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH9_SHIFT 18 /**< Shift value for LESENSE_CH9 */
-#define _LESENSE_IDLECONF_CH9_MASK 0xC0000UL /**< Bit mask for LESENSE_CH9 */
-#define _LESENSE_IDLECONF_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH9_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH9_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH9_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH9_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH9_DEFAULT (_LESENSE_IDLECONF_CH9_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH9_DISABLE (_LESENSE_IDLECONF_CH9_DISABLE << 18) /**< Shifted mode DISABLE for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH9_HIGH (_LESENSE_IDLECONF_CH9_HIGH << 18) /**< Shifted mode HIGH for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH9_LOW (_LESENSE_IDLECONF_CH9_LOW << 18) /**< Shifted mode LOW for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH9_DAC (_LESENSE_IDLECONF_CH9_DAC << 18) /**< Shifted mode DAC for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH10_SHIFT 20 /**< Shift value for LESENSE_CH10 */
-#define _LESENSE_IDLECONF_CH10_MASK 0x300000UL /**< Bit mask for LESENSE_CH10 */
-#define _LESENSE_IDLECONF_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH10_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH10_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH10_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH10_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH10_DEFAULT (_LESENSE_IDLECONF_CH10_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH10_DISABLE (_LESENSE_IDLECONF_CH10_DISABLE << 20) /**< Shifted mode DISABLE for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH10_HIGH (_LESENSE_IDLECONF_CH10_HIGH << 20) /**< Shifted mode HIGH for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH10_LOW (_LESENSE_IDLECONF_CH10_LOW << 20) /**< Shifted mode LOW for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH10_DAC (_LESENSE_IDLECONF_CH10_DAC << 20) /**< Shifted mode DAC for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH11_SHIFT 22 /**< Shift value for LESENSE_CH11 */
-#define _LESENSE_IDLECONF_CH11_MASK 0xC00000UL /**< Bit mask for LESENSE_CH11 */
-#define _LESENSE_IDLECONF_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH11_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH11_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH11_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH11_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH11_DEFAULT (_LESENSE_IDLECONF_CH11_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH11_DISABLE (_LESENSE_IDLECONF_CH11_DISABLE << 22) /**< Shifted mode DISABLE for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH11_HIGH (_LESENSE_IDLECONF_CH11_HIGH << 22) /**< Shifted mode HIGH for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH11_LOW (_LESENSE_IDLECONF_CH11_LOW << 22) /**< Shifted mode LOW for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH11_DAC (_LESENSE_IDLECONF_CH11_DAC << 22) /**< Shifted mode DAC for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH12_SHIFT 24 /**< Shift value for LESENSE_CH12 */
-#define _LESENSE_IDLECONF_CH12_MASK 0x3000000UL /**< Bit mask for LESENSE_CH12 */
-#define _LESENSE_IDLECONF_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH12_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH12_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH12_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH12_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH12_DEFAULT (_LESENSE_IDLECONF_CH12_DEFAULT << 24) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH12_DISABLE (_LESENSE_IDLECONF_CH12_DISABLE << 24) /**< Shifted mode DISABLE for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH12_HIGH (_LESENSE_IDLECONF_CH12_HIGH << 24) /**< Shifted mode HIGH for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH12_LOW (_LESENSE_IDLECONF_CH12_LOW << 24) /**< Shifted mode LOW for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH12_DAC (_LESENSE_IDLECONF_CH12_DAC << 24) /**< Shifted mode DAC for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH13_SHIFT 26 /**< Shift value for LESENSE_CH13 */
-#define _LESENSE_IDLECONF_CH13_MASK 0xC000000UL /**< Bit mask for LESENSE_CH13 */
-#define _LESENSE_IDLECONF_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH13_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH13_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH13_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH13_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH13_DEFAULT (_LESENSE_IDLECONF_CH13_DEFAULT << 26) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH13_DISABLE (_LESENSE_IDLECONF_CH13_DISABLE << 26) /**< Shifted mode DISABLE for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH13_HIGH (_LESENSE_IDLECONF_CH13_HIGH << 26) /**< Shifted mode HIGH for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH13_LOW (_LESENSE_IDLECONF_CH13_LOW << 26) /**< Shifted mode LOW for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH13_DAC (_LESENSE_IDLECONF_CH13_DAC << 26) /**< Shifted mode DAC for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH14_SHIFT 28 /**< Shift value for LESENSE_CH14 */
-#define _LESENSE_IDLECONF_CH14_MASK 0x30000000UL /**< Bit mask for LESENSE_CH14 */
-#define _LESENSE_IDLECONF_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH14_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH14_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH14_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH14_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH14_DEFAULT (_LESENSE_IDLECONF_CH14_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH14_DISABLE (_LESENSE_IDLECONF_CH14_DISABLE << 28) /**< Shifted mode DISABLE for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH14_HIGH (_LESENSE_IDLECONF_CH14_HIGH << 28) /**< Shifted mode HIGH for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH14_LOW (_LESENSE_IDLECONF_CH14_LOW << 28) /**< Shifted mode LOW for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH14_DAC (_LESENSE_IDLECONF_CH14_DAC << 28) /**< Shifted mode DAC for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH15_SHIFT 30 /**< Shift value for LESENSE_CH15 */
-#define _LESENSE_IDLECONF_CH15_MASK 0xC0000000UL /**< Bit mask for LESENSE_CH15 */
-#define _LESENSE_IDLECONF_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH15_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH15_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH15_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */
-#define _LESENSE_IDLECONF_CH15_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH15_DEFAULT (_LESENSE_IDLECONF_CH15_DEFAULT << 30) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH15_DISABLE (_LESENSE_IDLECONF_CH15_DISABLE << 30) /**< Shifted mode DISABLE for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH15_HIGH (_LESENSE_IDLECONF_CH15_HIGH << 30) /**< Shifted mode HIGH for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH15_LOW (_LESENSE_IDLECONF_CH15_LOW << 30) /**< Shifted mode LOW for LESENSE_IDLECONF */
-#define LESENSE_IDLECONF_CH15_DAC (_LESENSE_IDLECONF_CH15_DAC << 30) /**< Shifted mode DAC for LESENSE_IDLECONF */
-
-/* Bit fields for LESENSE ALTEXCONF */
-#define _LESENSE_ALTEXCONF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_MASK 0x00FFFFFFUL /**< Mask for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF0_SHIFT 0 /**< Shift value for LESENSE_IDLECONF0 */
-#define _LESENSE_ALTEXCONF_IDLECONF0_MASK 0x3UL /**< Bit mask for LESENSE_IDLECONF0 */
-#define _LESENSE_ALTEXCONF_IDLECONF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF0_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF0_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF0_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF0_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF0_DISABLE (_LESENSE_ALTEXCONF_IDLECONF0_DISABLE << 0) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF0_HIGH (_LESENSE_ALTEXCONF_IDLECONF0_HIGH << 0) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF0_LOW (_LESENSE_ALTEXCONF_IDLECONF0_LOW << 0) /**< Shifted mode LOW for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF1_SHIFT 2 /**< Shift value for LESENSE_IDLECONF1 */
-#define _LESENSE_ALTEXCONF_IDLECONF1_MASK 0xCUL /**< Bit mask for LESENSE_IDLECONF1 */
-#define _LESENSE_ALTEXCONF_IDLECONF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF1_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF1_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF1_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF1_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF1_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF1_DISABLE (_LESENSE_ALTEXCONF_IDLECONF1_DISABLE << 2) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF1_HIGH (_LESENSE_ALTEXCONF_IDLECONF1_HIGH << 2) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF1_LOW (_LESENSE_ALTEXCONF_IDLECONF1_LOW << 2) /**< Shifted mode LOW for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF2_SHIFT 4 /**< Shift value for LESENSE_IDLECONF2 */
-#define _LESENSE_ALTEXCONF_IDLECONF2_MASK 0x30UL /**< Bit mask for LESENSE_IDLECONF2 */
-#define _LESENSE_ALTEXCONF_IDLECONF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF2_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF2_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF2_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF2_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF2_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF2_DISABLE (_LESENSE_ALTEXCONF_IDLECONF2_DISABLE << 4) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF2_HIGH (_LESENSE_ALTEXCONF_IDLECONF2_HIGH << 4) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF2_LOW (_LESENSE_ALTEXCONF_IDLECONF2_LOW << 4) /**< Shifted mode LOW for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF3_SHIFT 6 /**< Shift value for LESENSE_IDLECONF3 */
-#define _LESENSE_ALTEXCONF_IDLECONF3_MASK 0xC0UL /**< Bit mask for LESENSE_IDLECONF3 */
-#define _LESENSE_ALTEXCONF_IDLECONF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF3_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF3_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF3_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF3_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF3_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF3_DISABLE (_LESENSE_ALTEXCONF_IDLECONF3_DISABLE << 6) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF3_HIGH (_LESENSE_ALTEXCONF_IDLECONF3_HIGH << 6) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF3_LOW (_LESENSE_ALTEXCONF_IDLECONF3_LOW << 6) /**< Shifted mode LOW for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF4_SHIFT 8 /**< Shift value for LESENSE_IDLECONF4 */
-#define _LESENSE_ALTEXCONF_IDLECONF4_MASK 0x300UL /**< Bit mask for LESENSE_IDLECONF4 */
-#define _LESENSE_ALTEXCONF_IDLECONF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF4_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF4_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF4_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF4_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF4_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF4_DISABLE (_LESENSE_ALTEXCONF_IDLECONF4_DISABLE << 8) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF4_HIGH (_LESENSE_ALTEXCONF_IDLECONF4_HIGH << 8) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF4_LOW (_LESENSE_ALTEXCONF_IDLECONF4_LOW << 8) /**< Shifted mode LOW for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF5_SHIFT 10 /**< Shift value for LESENSE_IDLECONF5 */
-#define _LESENSE_ALTEXCONF_IDLECONF5_MASK 0xC00UL /**< Bit mask for LESENSE_IDLECONF5 */
-#define _LESENSE_ALTEXCONF_IDLECONF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF5_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF5_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF5_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF5_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF5_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF5_DISABLE (_LESENSE_ALTEXCONF_IDLECONF5_DISABLE << 10) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF5_HIGH (_LESENSE_ALTEXCONF_IDLECONF5_HIGH << 10) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF5_LOW (_LESENSE_ALTEXCONF_IDLECONF5_LOW << 10) /**< Shifted mode LOW for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF6_SHIFT 12 /**< Shift value for LESENSE_IDLECONF6 */
-#define _LESENSE_ALTEXCONF_IDLECONF6_MASK 0x3000UL /**< Bit mask for LESENSE_IDLECONF6 */
-#define _LESENSE_ALTEXCONF_IDLECONF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF6_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF6_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF6_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF6_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF6_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF6_DISABLE (_LESENSE_ALTEXCONF_IDLECONF6_DISABLE << 12) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF6_HIGH (_LESENSE_ALTEXCONF_IDLECONF6_HIGH << 12) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF6_LOW (_LESENSE_ALTEXCONF_IDLECONF6_LOW << 12) /**< Shifted mode LOW for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF7_SHIFT 14 /**< Shift value for LESENSE_IDLECONF7 */
-#define _LESENSE_ALTEXCONF_IDLECONF7_MASK 0xC000UL /**< Bit mask for LESENSE_IDLECONF7 */
-#define _LESENSE_ALTEXCONF_IDLECONF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF7_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF7_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */
-#define _LESENSE_ALTEXCONF_IDLECONF7_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF7_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF7_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF7_DISABLE (_LESENSE_ALTEXCONF_IDLECONF7_DISABLE << 14) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF7_HIGH (_LESENSE_ALTEXCONF_IDLECONF7_HIGH << 14) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_IDLECONF7_LOW (_LESENSE_ALTEXCONF_IDLECONF7_LOW << 14) /**< Shifted mode LOW for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_AEX0 (0x1UL << 16) /**< ALTEX0 Always Excite Enable */
-#define _LESENSE_ALTEXCONF_AEX0_SHIFT 16 /**< Shift value for LESENSE_AEX0 */
-#define _LESENSE_ALTEXCONF_AEX0_MASK 0x10000UL /**< Bit mask for LESENSE_AEX0 */
-#define _LESENSE_ALTEXCONF_AEX0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_AEX0_DEFAULT (_LESENSE_ALTEXCONF_AEX0_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_AEX1 (0x1UL << 17) /**< ALTEX1 Always Excite Enable */
-#define _LESENSE_ALTEXCONF_AEX1_SHIFT 17 /**< Shift value for LESENSE_AEX1 */
-#define _LESENSE_ALTEXCONF_AEX1_MASK 0x20000UL /**< Bit mask for LESENSE_AEX1 */
-#define _LESENSE_ALTEXCONF_AEX1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_AEX1_DEFAULT (_LESENSE_ALTEXCONF_AEX1_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_AEX2 (0x1UL << 18) /**< ALTEX2 Always Excite Enable */
-#define _LESENSE_ALTEXCONF_AEX2_SHIFT 18 /**< Shift value for LESENSE_AEX2 */
-#define _LESENSE_ALTEXCONF_AEX2_MASK 0x40000UL /**< Bit mask for LESENSE_AEX2 */
-#define _LESENSE_ALTEXCONF_AEX2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_AEX2_DEFAULT (_LESENSE_ALTEXCONF_AEX2_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_AEX3 (0x1UL << 19) /**< ALTEX3 Always Excite Enable */
-#define _LESENSE_ALTEXCONF_AEX3_SHIFT 19 /**< Shift value for LESENSE_AEX3 */
-#define _LESENSE_ALTEXCONF_AEX3_MASK 0x80000UL /**< Bit mask for LESENSE_AEX3 */
-#define _LESENSE_ALTEXCONF_AEX3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_AEX3_DEFAULT (_LESENSE_ALTEXCONF_AEX3_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_AEX4 (0x1UL << 20) /**< ALTEX4 Always Excite Enable */
-#define _LESENSE_ALTEXCONF_AEX4_SHIFT 20 /**< Shift value for LESENSE_AEX4 */
-#define _LESENSE_ALTEXCONF_AEX4_MASK 0x100000UL /**< Bit mask for LESENSE_AEX4 */
-#define _LESENSE_ALTEXCONF_AEX4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_AEX4_DEFAULT (_LESENSE_ALTEXCONF_AEX4_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_AEX5 (0x1UL << 21) /**< ALTEX5 Always Excite Enable */
-#define _LESENSE_ALTEXCONF_AEX5_SHIFT 21 /**< Shift value for LESENSE_AEX5 */
-#define _LESENSE_ALTEXCONF_AEX5_MASK 0x200000UL /**< Bit mask for LESENSE_AEX5 */
-#define _LESENSE_ALTEXCONF_AEX5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_AEX5_DEFAULT (_LESENSE_ALTEXCONF_AEX5_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_AEX6 (0x1UL << 22) /**< ALTEX6 Always Excite Enable */
-#define _LESENSE_ALTEXCONF_AEX6_SHIFT 22 /**< Shift value for LESENSE_AEX6 */
-#define _LESENSE_ALTEXCONF_AEX6_MASK 0x400000UL /**< Bit mask for LESENSE_AEX6 */
-#define _LESENSE_ALTEXCONF_AEX6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_AEX6_DEFAULT (_LESENSE_ALTEXCONF_AEX6_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_AEX7 (0x1UL << 23) /**< ALTEX7 Always Excite Enable */
-#define _LESENSE_ALTEXCONF_AEX7_SHIFT 23 /**< Shift value for LESENSE_AEX7 */
-#define _LESENSE_ALTEXCONF_AEX7_MASK 0x800000UL /**< Bit mask for LESENSE_AEX7 */
-#define _LESENSE_ALTEXCONF_AEX7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */
-#define LESENSE_ALTEXCONF_AEX7_DEFAULT (_LESENSE_ALTEXCONF_AEX7_DEFAULT << 23) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */
-
-/* Bit fields for LESENSE IF */
-#define _LESENSE_IF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IF */
-#define _LESENSE_IF_MASK 0x007FFFFFUL /**< Mask for LESENSE_IF */
-#define LESENSE_IF_CH0 (0x1UL << 0) /**< CH0 Interrupt Flag */
-#define _LESENSE_IF_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */
-#define _LESENSE_IF_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */
-#define _LESENSE_IF_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH0_DEFAULT (_LESENSE_IF_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH1 (0x1UL << 1) /**< CH1 Interrupt Flag */
-#define _LESENSE_IF_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */
-#define _LESENSE_IF_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */
-#define _LESENSE_IF_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH1_DEFAULT (_LESENSE_IF_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH2 (0x1UL << 2) /**< CH2 Interrupt Flag */
-#define _LESENSE_IF_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */
-#define _LESENSE_IF_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */
-#define _LESENSE_IF_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH2_DEFAULT (_LESENSE_IF_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH3 (0x1UL << 3) /**< CH3 Interrupt Flag */
-#define _LESENSE_IF_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */
-#define _LESENSE_IF_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */
-#define _LESENSE_IF_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH3_DEFAULT (_LESENSE_IF_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH4 (0x1UL << 4) /**< CH4 Interrupt Flag */
-#define _LESENSE_IF_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */
-#define _LESENSE_IF_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */
-#define _LESENSE_IF_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH4_DEFAULT (_LESENSE_IF_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH5 (0x1UL << 5) /**< CH5 Interrupt Flag */
-#define _LESENSE_IF_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */
-#define _LESENSE_IF_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */
-#define _LESENSE_IF_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH5_DEFAULT (_LESENSE_IF_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH6 (0x1UL << 6) /**< CH6 Interrupt Flag */
-#define _LESENSE_IF_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */
-#define _LESENSE_IF_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */
-#define _LESENSE_IF_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH6_DEFAULT (_LESENSE_IF_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH7 (0x1UL << 7) /**< CH7 Interrupt Flag */
-#define _LESENSE_IF_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */
-#define _LESENSE_IF_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */
-#define _LESENSE_IF_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH7_DEFAULT (_LESENSE_IF_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH8 (0x1UL << 8) /**< CH8 Interrupt Flag */
-#define _LESENSE_IF_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */
-#define _LESENSE_IF_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */
-#define _LESENSE_IF_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH8_DEFAULT (_LESENSE_IF_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH9 (0x1UL << 9) /**< CH9 Interrupt Flag */
-#define _LESENSE_IF_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */
-#define _LESENSE_IF_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */
-#define _LESENSE_IF_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH9_DEFAULT (_LESENSE_IF_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH10 (0x1UL << 10) /**< CH10 Interrupt Flag */
-#define _LESENSE_IF_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */
-#define _LESENSE_IF_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */
-#define _LESENSE_IF_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH10_DEFAULT (_LESENSE_IF_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH11 (0x1UL << 11) /**< CH11 Interrupt Flag */
-#define _LESENSE_IF_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */
-#define _LESENSE_IF_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */
-#define _LESENSE_IF_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH11_DEFAULT (_LESENSE_IF_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH12 (0x1UL << 12) /**< CH12 Interrupt Flag */
-#define _LESENSE_IF_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */
-#define _LESENSE_IF_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */
-#define _LESENSE_IF_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH12_DEFAULT (_LESENSE_IF_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH13 (0x1UL << 13) /**< CH13 Interrupt Flag */
-#define _LESENSE_IF_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */
-#define _LESENSE_IF_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */
-#define _LESENSE_IF_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH13_DEFAULT (_LESENSE_IF_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH14 (0x1UL << 14) /**< CH14 Interrupt Flag */
-#define _LESENSE_IF_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */
-#define _LESENSE_IF_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */
-#define _LESENSE_IF_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH14_DEFAULT (_LESENSE_IF_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH15 (0x1UL << 15) /**< CH15 Interrupt Flag */
-#define _LESENSE_IF_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */
-#define _LESENSE_IF_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */
-#define _LESENSE_IF_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CH15_DEFAULT (_LESENSE_IF_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_SCANCOMPLETE (0x1UL << 16) /**< SCANCOMPLETE Interrupt Flag */
-#define _LESENSE_IF_SCANCOMPLETE_SHIFT 16 /**< Shift value for LESENSE_SCANCOMPLETE */
-#define _LESENSE_IF_SCANCOMPLETE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANCOMPLETE */
-#define _LESENSE_IF_SCANCOMPLETE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_SCANCOMPLETE_DEFAULT (_LESENSE_IF_SCANCOMPLETE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_DEC (0x1UL << 17) /**< DEC Interrupt Flag */
-#define _LESENSE_IF_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */
-#define _LESENSE_IF_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */
-#define _LESENSE_IF_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_DEC_DEFAULT (_LESENSE_IF_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_DECERR (0x1UL << 18) /**< DECERR Interrupt Flag */
-#define _LESENSE_IF_DECERR_SHIFT 18 /**< Shift value for LESENSE_DECERR */
-#define _LESENSE_IF_DECERR_MASK 0x40000UL /**< Bit mask for LESENSE_DECERR */
-#define _LESENSE_IF_DECERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_DECERR_DEFAULT (_LESENSE_IF_DECERR_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_BUFDATAV (0x1UL << 19) /**< BUFDATAV Interrupt Flag */
-#define _LESENSE_IF_BUFDATAV_SHIFT 19 /**< Shift value for LESENSE_BUFDATAV */
-#define _LESENSE_IF_BUFDATAV_MASK 0x80000UL /**< Bit mask for LESENSE_BUFDATAV */
-#define _LESENSE_IF_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_BUFDATAV_DEFAULT (_LESENSE_IF_BUFDATAV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_BUFLEVEL (0x1UL << 20) /**< BUFLEVEL Interrupt Flag */
-#define _LESENSE_IF_BUFLEVEL_SHIFT 20 /**< Shift value for LESENSE_BUFLEVEL */
-#define _LESENSE_IF_BUFLEVEL_MASK 0x100000UL /**< Bit mask for LESENSE_BUFLEVEL */
-#define _LESENSE_IF_BUFLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_BUFLEVEL_DEFAULT (_LESENSE_IF_BUFLEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_BUFOF (0x1UL << 21) /**< BUFOF Interrupt Flag */
-#define _LESENSE_IF_BUFOF_SHIFT 21 /**< Shift value for LESENSE_BUFOF */
-#define _LESENSE_IF_BUFOF_MASK 0x200000UL /**< Bit mask for LESENSE_BUFOF */
-#define _LESENSE_IF_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_BUFOF_DEFAULT (_LESENSE_IF_BUFOF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CNTOF (0x1UL << 22) /**< CNTOF Interrupt Flag */
-#define _LESENSE_IF_CNTOF_SHIFT 22 /**< Shift value for LESENSE_CNTOF */
-#define _LESENSE_IF_CNTOF_MASK 0x400000UL /**< Bit mask for LESENSE_CNTOF */
-#define _LESENSE_IF_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */
-#define LESENSE_IF_CNTOF_DEFAULT (_LESENSE_IF_CNTOF_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IF */
-
-/* Bit fields for LESENSE IFS */
-#define _LESENSE_IFS_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IFS */
-#define _LESENSE_IFS_MASK 0x007FFFFFUL /**< Mask for LESENSE_IFS */
-#define LESENSE_IFS_CH0 (0x1UL << 0) /**< Set CH0 Interrupt Flag */
-#define _LESENSE_IFS_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */
-#define _LESENSE_IFS_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */
-#define _LESENSE_IFS_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CH0_DEFAULT (_LESENSE_IFS_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CH1 (0x1UL << 1) /**< Set CH1 Interrupt Flag */
-#define _LESENSE_IFS_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */
-#define _LESENSE_IFS_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */
-#define _LESENSE_IFS_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CH1_DEFAULT (_LESENSE_IFS_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CH2 (0x1UL << 2) /**< Set CH2 Interrupt Flag */
-#define _LESENSE_IFS_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */
-#define _LESENSE_IFS_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */
-#define _LESENSE_IFS_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CH2_DEFAULT (_LESENSE_IFS_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CH3 (0x1UL << 3) /**< Set CH3 Interrupt Flag */
-#define _LESENSE_IFS_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */
-#define _LESENSE_IFS_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */
-#define _LESENSE_IFS_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CH3_DEFAULT (_LESENSE_IFS_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CH4 (0x1UL << 4) /**< Set CH4 Interrupt Flag */
-#define _LESENSE_IFS_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */
-#define _LESENSE_IFS_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */
-#define _LESENSE_IFS_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CH4_DEFAULT (_LESENSE_IFS_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CH5 (0x1UL << 5) /**< Set CH5 Interrupt Flag */
-#define _LESENSE_IFS_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */
-#define _LESENSE_IFS_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */
-#define _LESENSE_IFS_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CH5_DEFAULT (_LESENSE_IFS_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CH6 (0x1UL << 6) /**< Set CH6 Interrupt Flag */
-#define _LESENSE_IFS_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */
-#define _LESENSE_IFS_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */
-#define _LESENSE_IFS_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CH6_DEFAULT (_LESENSE_IFS_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CH7 (0x1UL << 7) /**< Set CH7 Interrupt Flag */
-#define _LESENSE_IFS_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */
-#define _LESENSE_IFS_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */
-#define _LESENSE_IFS_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CH7_DEFAULT (_LESENSE_IFS_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CH8 (0x1UL << 8) /**< Set CH8 Interrupt Flag */
-#define _LESENSE_IFS_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */
-#define _LESENSE_IFS_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */
-#define _LESENSE_IFS_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CH8_DEFAULT (_LESENSE_IFS_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CH9 (0x1UL << 9) /**< Set CH9 Interrupt Flag */
-#define _LESENSE_IFS_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */
-#define _LESENSE_IFS_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */
-#define _LESENSE_IFS_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CH9_DEFAULT (_LESENSE_IFS_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CH10 (0x1UL << 10) /**< Set CH10 Interrupt Flag */
-#define _LESENSE_IFS_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */
-#define _LESENSE_IFS_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */
-#define _LESENSE_IFS_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CH10_DEFAULT (_LESENSE_IFS_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CH11 (0x1UL << 11) /**< Set CH11 Interrupt Flag */
-#define _LESENSE_IFS_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */
-#define _LESENSE_IFS_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */
-#define _LESENSE_IFS_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CH11_DEFAULT (_LESENSE_IFS_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CH12 (0x1UL << 12) /**< Set CH12 Interrupt Flag */
-#define _LESENSE_IFS_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */
-#define _LESENSE_IFS_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */
-#define _LESENSE_IFS_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CH12_DEFAULT (_LESENSE_IFS_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CH13 (0x1UL << 13) /**< Set CH13 Interrupt Flag */
-#define _LESENSE_IFS_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */
-#define _LESENSE_IFS_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */
-#define _LESENSE_IFS_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CH13_DEFAULT (_LESENSE_IFS_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CH14 (0x1UL << 14) /**< Set CH14 Interrupt Flag */
-#define _LESENSE_IFS_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */
-#define _LESENSE_IFS_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */
-#define _LESENSE_IFS_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CH14_DEFAULT (_LESENSE_IFS_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CH15 (0x1UL << 15) /**< Set CH15 Interrupt Flag */
-#define _LESENSE_IFS_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */
-#define _LESENSE_IFS_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */
-#define _LESENSE_IFS_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CH15_DEFAULT (_LESENSE_IFS_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_SCANCOMPLETE (0x1UL << 16) /**< Set SCANCOMPLETE Interrupt Flag */
-#define _LESENSE_IFS_SCANCOMPLETE_SHIFT 16 /**< Shift value for LESENSE_SCANCOMPLETE */
-#define _LESENSE_IFS_SCANCOMPLETE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANCOMPLETE */
-#define _LESENSE_IFS_SCANCOMPLETE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_SCANCOMPLETE_DEFAULT (_LESENSE_IFS_SCANCOMPLETE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_DEC (0x1UL << 17) /**< Set DEC Interrupt Flag */
-#define _LESENSE_IFS_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */
-#define _LESENSE_IFS_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */
-#define _LESENSE_IFS_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_DEC_DEFAULT (_LESENSE_IFS_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_DECERR (0x1UL << 18) /**< Set DECERR Interrupt Flag */
-#define _LESENSE_IFS_DECERR_SHIFT 18 /**< Shift value for LESENSE_DECERR */
-#define _LESENSE_IFS_DECERR_MASK 0x40000UL /**< Bit mask for LESENSE_DECERR */
-#define _LESENSE_IFS_DECERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_DECERR_DEFAULT (_LESENSE_IFS_DECERR_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_BUFDATAV (0x1UL << 19) /**< Set BUFDATAV Interrupt Flag */
-#define _LESENSE_IFS_BUFDATAV_SHIFT 19 /**< Shift value for LESENSE_BUFDATAV */
-#define _LESENSE_IFS_BUFDATAV_MASK 0x80000UL /**< Bit mask for LESENSE_BUFDATAV */
-#define _LESENSE_IFS_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_BUFDATAV_DEFAULT (_LESENSE_IFS_BUFDATAV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_BUFLEVEL (0x1UL << 20) /**< Set BUFLEVEL Interrupt Flag */
-#define _LESENSE_IFS_BUFLEVEL_SHIFT 20 /**< Shift value for LESENSE_BUFLEVEL */
-#define _LESENSE_IFS_BUFLEVEL_MASK 0x100000UL /**< Bit mask for LESENSE_BUFLEVEL */
-#define _LESENSE_IFS_BUFLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_BUFLEVEL_DEFAULT (_LESENSE_IFS_BUFLEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_BUFOF (0x1UL << 21) /**< Set BUFOF Interrupt Flag */
-#define _LESENSE_IFS_BUFOF_SHIFT 21 /**< Shift value for LESENSE_BUFOF */
-#define _LESENSE_IFS_BUFOF_MASK 0x200000UL /**< Bit mask for LESENSE_BUFOF */
-#define _LESENSE_IFS_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_BUFOF_DEFAULT (_LESENSE_IFS_BUFOF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CNTOF (0x1UL << 22) /**< Set CNTOF Interrupt Flag */
-#define _LESENSE_IFS_CNTOF_SHIFT 22 /**< Shift value for LESENSE_CNTOF */
-#define _LESENSE_IFS_CNTOF_MASK 0x400000UL /**< Bit mask for LESENSE_CNTOF */
-#define _LESENSE_IFS_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */
-#define LESENSE_IFS_CNTOF_DEFAULT (_LESENSE_IFS_CNTOF_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IFS */
-
-/* Bit fields for LESENSE IFC */
-#define _LESENSE_IFC_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IFC */
-#define _LESENSE_IFC_MASK 0x007FFFFFUL /**< Mask for LESENSE_IFC */
-#define LESENSE_IFC_CH0 (0x1UL << 0) /**< Clear CH0 Interrupt Flag */
-#define _LESENSE_IFC_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */
-#define _LESENSE_IFC_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */
-#define _LESENSE_IFC_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CH0_DEFAULT (_LESENSE_IFC_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CH1 (0x1UL << 1) /**< Clear CH1 Interrupt Flag */
-#define _LESENSE_IFC_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */
-#define _LESENSE_IFC_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */
-#define _LESENSE_IFC_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CH1_DEFAULT (_LESENSE_IFC_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CH2 (0x1UL << 2) /**< Clear CH2 Interrupt Flag */
-#define _LESENSE_IFC_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */
-#define _LESENSE_IFC_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */
-#define _LESENSE_IFC_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CH2_DEFAULT (_LESENSE_IFC_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CH3 (0x1UL << 3) /**< Clear CH3 Interrupt Flag */
-#define _LESENSE_IFC_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */
-#define _LESENSE_IFC_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */
-#define _LESENSE_IFC_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CH3_DEFAULT (_LESENSE_IFC_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CH4 (0x1UL << 4) /**< Clear CH4 Interrupt Flag */
-#define _LESENSE_IFC_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */
-#define _LESENSE_IFC_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */
-#define _LESENSE_IFC_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CH4_DEFAULT (_LESENSE_IFC_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CH5 (0x1UL << 5) /**< Clear CH5 Interrupt Flag */
-#define _LESENSE_IFC_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */
-#define _LESENSE_IFC_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */
-#define _LESENSE_IFC_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CH5_DEFAULT (_LESENSE_IFC_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CH6 (0x1UL << 6) /**< Clear CH6 Interrupt Flag */
-#define _LESENSE_IFC_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */
-#define _LESENSE_IFC_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */
-#define _LESENSE_IFC_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CH6_DEFAULT (_LESENSE_IFC_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CH7 (0x1UL << 7) /**< Clear CH7 Interrupt Flag */
-#define _LESENSE_IFC_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */
-#define _LESENSE_IFC_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */
-#define _LESENSE_IFC_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CH7_DEFAULT (_LESENSE_IFC_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CH8 (0x1UL << 8) /**< Clear CH8 Interrupt Flag */
-#define _LESENSE_IFC_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */
-#define _LESENSE_IFC_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */
-#define _LESENSE_IFC_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CH8_DEFAULT (_LESENSE_IFC_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CH9 (0x1UL << 9) /**< Clear CH9 Interrupt Flag */
-#define _LESENSE_IFC_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */
-#define _LESENSE_IFC_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */
-#define _LESENSE_IFC_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CH9_DEFAULT (_LESENSE_IFC_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CH10 (0x1UL << 10) /**< Clear CH10 Interrupt Flag */
-#define _LESENSE_IFC_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */
-#define _LESENSE_IFC_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */
-#define _LESENSE_IFC_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CH10_DEFAULT (_LESENSE_IFC_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CH11 (0x1UL << 11) /**< Clear CH11 Interrupt Flag */
-#define _LESENSE_IFC_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */
-#define _LESENSE_IFC_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */
-#define _LESENSE_IFC_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CH11_DEFAULT (_LESENSE_IFC_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CH12 (0x1UL << 12) /**< Clear CH12 Interrupt Flag */
-#define _LESENSE_IFC_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */
-#define _LESENSE_IFC_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */
-#define _LESENSE_IFC_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CH12_DEFAULT (_LESENSE_IFC_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CH13 (0x1UL << 13) /**< Clear CH13 Interrupt Flag */
-#define _LESENSE_IFC_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */
-#define _LESENSE_IFC_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */
-#define _LESENSE_IFC_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CH13_DEFAULT (_LESENSE_IFC_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CH14 (0x1UL << 14) /**< Clear CH14 Interrupt Flag */
-#define _LESENSE_IFC_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */
-#define _LESENSE_IFC_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */
-#define _LESENSE_IFC_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CH14_DEFAULT (_LESENSE_IFC_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CH15 (0x1UL << 15) /**< Clear CH15 Interrupt Flag */
-#define _LESENSE_IFC_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */
-#define _LESENSE_IFC_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */
-#define _LESENSE_IFC_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CH15_DEFAULT (_LESENSE_IFC_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_SCANCOMPLETE (0x1UL << 16) /**< Clear SCANCOMPLETE Interrupt Flag */
-#define _LESENSE_IFC_SCANCOMPLETE_SHIFT 16 /**< Shift value for LESENSE_SCANCOMPLETE */
-#define _LESENSE_IFC_SCANCOMPLETE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANCOMPLETE */
-#define _LESENSE_IFC_SCANCOMPLETE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_SCANCOMPLETE_DEFAULT (_LESENSE_IFC_SCANCOMPLETE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_DEC (0x1UL << 17) /**< Clear DEC Interrupt Flag */
-#define _LESENSE_IFC_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */
-#define _LESENSE_IFC_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */
-#define _LESENSE_IFC_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_DEC_DEFAULT (_LESENSE_IFC_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_DECERR (0x1UL << 18) /**< Clear DECERR Interrupt Flag */
-#define _LESENSE_IFC_DECERR_SHIFT 18 /**< Shift value for LESENSE_DECERR */
-#define _LESENSE_IFC_DECERR_MASK 0x40000UL /**< Bit mask for LESENSE_DECERR */
-#define _LESENSE_IFC_DECERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_DECERR_DEFAULT (_LESENSE_IFC_DECERR_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_BUFDATAV (0x1UL << 19) /**< Clear BUFDATAV Interrupt Flag */
-#define _LESENSE_IFC_BUFDATAV_SHIFT 19 /**< Shift value for LESENSE_BUFDATAV */
-#define _LESENSE_IFC_BUFDATAV_MASK 0x80000UL /**< Bit mask for LESENSE_BUFDATAV */
-#define _LESENSE_IFC_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_BUFDATAV_DEFAULT (_LESENSE_IFC_BUFDATAV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_BUFLEVEL (0x1UL << 20) /**< Clear BUFLEVEL Interrupt Flag */
-#define _LESENSE_IFC_BUFLEVEL_SHIFT 20 /**< Shift value for LESENSE_BUFLEVEL */
-#define _LESENSE_IFC_BUFLEVEL_MASK 0x100000UL /**< Bit mask for LESENSE_BUFLEVEL */
-#define _LESENSE_IFC_BUFLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_BUFLEVEL_DEFAULT (_LESENSE_IFC_BUFLEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_BUFOF (0x1UL << 21) /**< Clear BUFOF Interrupt Flag */
-#define _LESENSE_IFC_BUFOF_SHIFT 21 /**< Shift value for LESENSE_BUFOF */
-#define _LESENSE_IFC_BUFOF_MASK 0x200000UL /**< Bit mask for LESENSE_BUFOF */
-#define _LESENSE_IFC_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_BUFOF_DEFAULT (_LESENSE_IFC_BUFOF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CNTOF (0x1UL << 22) /**< Clear CNTOF Interrupt Flag */
-#define _LESENSE_IFC_CNTOF_SHIFT 22 /**< Shift value for LESENSE_CNTOF */
-#define _LESENSE_IFC_CNTOF_MASK 0x400000UL /**< Bit mask for LESENSE_CNTOF */
-#define _LESENSE_IFC_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */
-#define LESENSE_IFC_CNTOF_DEFAULT (_LESENSE_IFC_CNTOF_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IFC */
-
-/* Bit fields for LESENSE IEN */
-#define _LESENSE_IEN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IEN */
-#define _LESENSE_IEN_MASK 0x007FFFFFUL /**< Mask for LESENSE_IEN */
-#define LESENSE_IEN_CH0 (0x1UL << 0) /**< CH0 Interrupt Enable */
-#define _LESENSE_IEN_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */
-#define _LESENSE_IEN_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */
-#define _LESENSE_IEN_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CH0_DEFAULT (_LESENSE_IEN_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CH1 (0x1UL << 1) /**< CH1 Interrupt Enable */
-#define _LESENSE_IEN_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */
-#define _LESENSE_IEN_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */
-#define _LESENSE_IEN_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CH1_DEFAULT (_LESENSE_IEN_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CH2 (0x1UL << 2) /**< CH2 Interrupt Enable */
-#define _LESENSE_IEN_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */
-#define _LESENSE_IEN_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */
-#define _LESENSE_IEN_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CH2_DEFAULT (_LESENSE_IEN_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CH3 (0x1UL << 3) /**< CH3 Interrupt Enable */
-#define _LESENSE_IEN_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */
-#define _LESENSE_IEN_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */
-#define _LESENSE_IEN_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CH3_DEFAULT (_LESENSE_IEN_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CH4 (0x1UL << 4) /**< CH4 Interrupt Enable */
-#define _LESENSE_IEN_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */
-#define _LESENSE_IEN_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */
-#define _LESENSE_IEN_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CH4_DEFAULT (_LESENSE_IEN_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CH5 (0x1UL << 5) /**< CH5 Interrupt Enable */
-#define _LESENSE_IEN_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */
-#define _LESENSE_IEN_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */
-#define _LESENSE_IEN_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CH5_DEFAULT (_LESENSE_IEN_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CH6 (0x1UL << 6) /**< CH6 Interrupt Enable */
-#define _LESENSE_IEN_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */
-#define _LESENSE_IEN_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */
-#define _LESENSE_IEN_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CH6_DEFAULT (_LESENSE_IEN_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CH7 (0x1UL << 7) /**< CH7 Interrupt Enable */
-#define _LESENSE_IEN_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */
-#define _LESENSE_IEN_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */
-#define _LESENSE_IEN_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CH7_DEFAULT (_LESENSE_IEN_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CH8 (0x1UL << 8) /**< CH8 Interrupt Enable */
-#define _LESENSE_IEN_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */
-#define _LESENSE_IEN_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */
-#define _LESENSE_IEN_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CH8_DEFAULT (_LESENSE_IEN_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CH9 (0x1UL << 9) /**< CH9 Interrupt Enable */
-#define _LESENSE_IEN_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */
-#define _LESENSE_IEN_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */
-#define _LESENSE_IEN_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CH9_DEFAULT (_LESENSE_IEN_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CH10 (0x1UL << 10) /**< CH10 Interrupt Enable */
-#define _LESENSE_IEN_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */
-#define _LESENSE_IEN_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */
-#define _LESENSE_IEN_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CH10_DEFAULT (_LESENSE_IEN_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CH11 (0x1UL << 11) /**< CH11 Interrupt Enable */
-#define _LESENSE_IEN_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */
-#define _LESENSE_IEN_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */
-#define _LESENSE_IEN_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CH11_DEFAULT (_LESENSE_IEN_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CH12 (0x1UL << 12) /**< CH12 Interrupt Enable */
-#define _LESENSE_IEN_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */
-#define _LESENSE_IEN_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */
-#define _LESENSE_IEN_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CH12_DEFAULT (_LESENSE_IEN_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CH13 (0x1UL << 13) /**< CH13 Interrupt Enable */
-#define _LESENSE_IEN_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */
-#define _LESENSE_IEN_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */
-#define _LESENSE_IEN_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CH13_DEFAULT (_LESENSE_IEN_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CH14 (0x1UL << 14) /**< CH14 Interrupt Enable */
-#define _LESENSE_IEN_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */
-#define _LESENSE_IEN_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */
-#define _LESENSE_IEN_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CH14_DEFAULT (_LESENSE_IEN_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CH15 (0x1UL << 15) /**< CH15 Interrupt Enable */
-#define _LESENSE_IEN_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */
-#define _LESENSE_IEN_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */
-#define _LESENSE_IEN_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CH15_DEFAULT (_LESENSE_IEN_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_SCANCOMPLETE (0x1UL << 16) /**< SCANCOMPLETE Interrupt Enable */
-#define _LESENSE_IEN_SCANCOMPLETE_SHIFT 16 /**< Shift value for LESENSE_SCANCOMPLETE */
-#define _LESENSE_IEN_SCANCOMPLETE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANCOMPLETE */
-#define _LESENSE_IEN_SCANCOMPLETE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_SCANCOMPLETE_DEFAULT (_LESENSE_IEN_SCANCOMPLETE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_DEC (0x1UL << 17) /**< DEC Interrupt Enable */
-#define _LESENSE_IEN_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */
-#define _LESENSE_IEN_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */
-#define _LESENSE_IEN_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_DEC_DEFAULT (_LESENSE_IEN_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_DECERR (0x1UL << 18) /**< DECERR Interrupt Enable */
-#define _LESENSE_IEN_DECERR_SHIFT 18 /**< Shift value for LESENSE_DECERR */
-#define _LESENSE_IEN_DECERR_MASK 0x40000UL /**< Bit mask for LESENSE_DECERR */
-#define _LESENSE_IEN_DECERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_DECERR_DEFAULT (_LESENSE_IEN_DECERR_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_BUFDATAV (0x1UL << 19) /**< BUFDATAV Interrupt Enable */
-#define _LESENSE_IEN_BUFDATAV_SHIFT 19 /**< Shift value for LESENSE_BUFDATAV */
-#define _LESENSE_IEN_BUFDATAV_MASK 0x80000UL /**< Bit mask for LESENSE_BUFDATAV */
-#define _LESENSE_IEN_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_BUFDATAV_DEFAULT (_LESENSE_IEN_BUFDATAV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_BUFLEVEL (0x1UL << 20) /**< BUFLEVEL Interrupt Enable */
-#define _LESENSE_IEN_BUFLEVEL_SHIFT 20 /**< Shift value for LESENSE_BUFLEVEL */
-#define _LESENSE_IEN_BUFLEVEL_MASK 0x100000UL /**< Bit mask for LESENSE_BUFLEVEL */
-#define _LESENSE_IEN_BUFLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_BUFLEVEL_DEFAULT (_LESENSE_IEN_BUFLEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_BUFOF (0x1UL << 21) /**< BUFOF Interrupt Enable */
-#define _LESENSE_IEN_BUFOF_SHIFT 21 /**< Shift value for LESENSE_BUFOF */
-#define _LESENSE_IEN_BUFOF_MASK 0x200000UL /**< Bit mask for LESENSE_BUFOF */
-#define _LESENSE_IEN_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_BUFOF_DEFAULT (_LESENSE_IEN_BUFOF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CNTOF (0x1UL << 22) /**< CNTOF Interrupt Enable */
-#define _LESENSE_IEN_CNTOF_SHIFT 22 /**< Shift value for LESENSE_CNTOF */
-#define _LESENSE_IEN_CNTOF_MASK 0x400000UL /**< Bit mask for LESENSE_CNTOF */
-#define _LESENSE_IEN_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */
-#define LESENSE_IEN_CNTOF_DEFAULT (_LESENSE_IEN_CNTOF_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IEN */
-
-/* Bit fields for LESENSE SYNCBUSY */
-#define _LESENSE_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SYNCBUSY */
-#define _LESENSE_SYNCBUSY_MASK 0x00000080UL /**< Mask for LESENSE_SYNCBUSY */
-#define LESENSE_SYNCBUSY_CMD (0x1UL << 7) /**< CMD Register Busy */
-#define _LESENSE_SYNCBUSY_CMD_SHIFT 7 /**< Shift value for LESENSE_CMD */
-#define _LESENSE_SYNCBUSY_CMD_MASK 0x80UL /**< Bit mask for LESENSE_CMD */
-#define _LESENSE_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SYNCBUSY */
-#define LESENSE_SYNCBUSY_CMD_DEFAULT (_LESENSE_SYNCBUSY_CMD_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_SYNCBUSY */
-
-/* Bit fields for LESENSE ROUTEPEN */
-#define _LESENSE_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ROUTEPEN */
-#define _LESENSE_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */
-#define _LESENSE_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for LESENSE_CH0PEN */
-#define _LESENSE_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for LESENSE_CH0PEN */
-#define _LESENSE_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH0PEN_DEFAULT (_LESENSE_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */
-#define _LESENSE_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for LESENSE_CH1PEN */
-#define _LESENSE_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for LESENSE_CH1PEN */
-#define _LESENSE_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH1PEN_DEFAULT (_LESENSE_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */
-#define _LESENSE_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for LESENSE_CH2PEN */
-#define _LESENSE_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for LESENSE_CH2PEN */
-#define _LESENSE_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH2PEN_DEFAULT (_LESENSE_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */
-#define _LESENSE_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for LESENSE_CH3PEN */
-#define _LESENSE_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for LESENSE_CH3PEN */
-#define _LESENSE_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH3PEN_DEFAULT (_LESENSE_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */
-#define _LESENSE_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for LESENSE_CH4PEN */
-#define _LESENSE_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for LESENSE_CH4PEN */
-#define _LESENSE_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH4PEN_DEFAULT (_LESENSE_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */
-#define _LESENSE_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for LESENSE_CH5PEN */
-#define _LESENSE_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for LESENSE_CH5PEN */
-#define _LESENSE_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH5PEN_DEFAULT (_LESENSE_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */
-#define _LESENSE_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for LESENSE_CH6PEN */
-#define _LESENSE_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for LESENSE_CH6PEN */
-#define _LESENSE_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH6PEN_DEFAULT (_LESENSE_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */
-#define _LESENSE_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for LESENSE_CH7PEN */
-#define _LESENSE_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for LESENSE_CH7PEN */
-#define _LESENSE_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH7PEN_DEFAULT (_LESENSE_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */
-#define _LESENSE_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for LESENSE_CH8PEN */
-#define _LESENSE_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for LESENSE_CH8PEN */
-#define _LESENSE_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH8PEN_DEFAULT (_LESENSE_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */
-#define _LESENSE_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for LESENSE_CH9PEN */
-#define _LESENSE_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for LESENSE_CH9PEN */
-#define _LESENSE_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH9PEN_DEFAULT (_LESENSE_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */
-#define _LESENSE_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for LESENSE_CH10PEN */
-#define _LESENSE_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for LESENSE_CH10PEN */
-#define _LESENSE_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH10PEN_DEFAULT (_LESENSE_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */
-#define _LESENSE_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for LESENSE_CH11PEN */
-#define _LESENSE_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for LESENSE_CH11PEN */
-#define _LESENSE_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH11PEN_DEFAULT (_LESENSE_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */
-#define _LESENSE_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for LESENSE_CH12PEN */
-#define _LESENSE_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for LESENSE_CH12PEN */
-#define _LESENSE_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH12PEN_DEFAULT (_LESENSE_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */
-#define _LESENSE_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for LESENSE_CH13PEN */
-#define _LESENSE_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for LESENSE_CH13PEN */
-#define _LESENSE_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH13PEN_DEFAULT (_LESENSE_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */
-#define _LESENSE_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for LESENSE_CH14PEN */
-#define _LESENSE_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for LESENSE_CH14PEN */
-#define _LESENSE_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH14PEN_DEFAULT (_LESENSE_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */
-#define _LESENSE_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for LESENSE_CH15PEN */
-#define _LESENSE_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for LESENSE_CH15PEN */
-#define _LESENSE_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_CH15PEN_DEFAULT (_LESENSE_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_ALTEX0PEN (0x1UL << 16) /**< ALTEX0 Pin Enable */
-#define _LESENSE_ROUTEPEN_ALTEX0PEN_SHIFT 16 /**< Shift value for LESENSE_ALTEX0PEN */
-#define _LESENSE_ROUTEPEN_ALTEX0PEN_MASK 0x10000UL /**< Bit mask for LESENSE_ALTEX0PEN */
-#define _LESENSE_ROUTEPEN_ALTEX0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_ALTEX0PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX0PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_ALTEX1PEN (0x1UL << 17) /**< ALTEX1 Pin Enable */
-#define _LESENSE_ROUTEPEN_ALTEX1PEN_SHIFT 17 /**< Shift value for LESENSE_ALTEX1PEN */
-#define _LESENSE_ROUTEPEN_ALTEX1PEN_MASK 0x20000UL /**< Bit mask for LESENSE_ALTEX1PEN */
-#define _LESENSE_ROUTEPEN_ALTEX1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_ALTEX1PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX1PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_ALTEX2PEN (0x1UL << 18) /**< ALTEX2 Pin Enable */
-#define _LESENSE_ROUTEPEN_ALTEX2PEN_SHIFT 18 /**< Shift value for LESENSE_ALTEX2PEN */
-#define _LESENSE_ROUTEPEN_ALTEX2PEN_MASK 0x40000UL /**< Bit mask for LESENSE_ALTEX2PEN */
-#define _LESENSE_ROUTEPEN_ALTEX2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_ALTEX2PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX2PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_ALTEX3PEN (0x1UL << 19) /**< ALTEX3 Pin Enable */
-#define _LESENSE_ROUTEPEN_ALTEX3PEN_SHIFT 19 /**< Shift value for LESENSE_ALTEX3PEN */
-#define _LESENSE_ROUTEPEN_ALTEX3PEN_MASK 0x80000UL /**< Bit mask for LESENSE_ALTEX3PEN */
-#define _LESENSE_ROUTEPEN_ALTEX3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_ALTEX3PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX3PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_ALTEX4PEN (0x1UL << 20) /**< ALTEX4 Pin Enable */
-#define _LESENSE_ROUTEPEN_ALTEX4PEN_SHIFT 20 /**< Shift value for LESENSE_ALTEX4PEN */
-#define _LESENSE_ROUTEPEN_ALTEX4PEN_MASK 0x100000UL /**< Bit mask for LESENSE_ALTEX4PEN */
-#define _LESENSE_ROUTEPEN_ALTEX4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_ALTEX4PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX4PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_ALTEX5PEN (0x1UL << 21) /**< ALTEX5 Pin Enable */
-#define _LESENSE_ROUTEPEN_ALTEX5PEN_SHIFT 21 /**< Shift value for LESENSE_ALTEX5PEN */
-#define _LESENSE_ROUTEPEN_ALTEX5PEN_MASK 0x200000UL /**< Bit mask for LESENSE_ALTEX5PEN */
-#define _LESENSE_ROUTEPEN_ALTEX5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_ALTEX5PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX5PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_ALTEX6PEN (0x1UL << 22) /**< ALTEX6 Pin Enable */
-#define _LESENSE_ROUTEPEN_ALTEX6PEN_SHIFT 22 /**< Shift value for LESENSE_ALTEX6PEN */
-#define _LESENSE_ROUTEPEN_ALTEX6PEN_MASK 0x400000UL /**< Bit mask for LESENSE_ALTEX6PEN */
-#define _LESENSE_ROUTEPEN_ALTEX6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_ALTEX6PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX6PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_ALTEX7PEN (0x1UL << 23) /**< ALTEX7 Pin Enable */
-#define _LESENSE_ROUTEPEN_ALTEX7PEN_SHIFT 23 /**< Shift value for LESENSE_ALTEX7PEN */
-#define _LESENSE_ROUTEPEN_ALTEX7PEN_MASK 0x800000UL /**< Bit mask for LESENSE_ALTEX7PEN */
-#define _LESENSE_ROUTEPEN_ALTEX7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */
-#define LESENSE_ROUTEPEN_ALTEX7PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX7PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */
-
-/* Bit fields for LESENSE ST_TCONFA */
-#define _LESENSE_ST_TCONFA_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_MASK 0x0007DFFFUL /**< Mask for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_COMP_SHIFT 0 /**< Shift value for LESENSE_COMP */
-#define _LESENSE_ST_TCONFA_COMP_MASK 0xFUL /**< Bit mask for LESENSE_COMP */
-#define _LESENSE_ST_TCONFA_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_COMP_DEFAULT (_LESENSE_ST_TCONFA_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_MASK_SHIFT 4 /**< Shift value for LESENSE_MASK */
-#define _LESENSE_ST_TCONFA_MASK_MASK 0xF0UL /**< Bit mask for LESENSE_MASK */
-#define _LESENSE_ST_TCONFA_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_MASK_DEFAULT (_LESENSE_ST_TCONFA_MASK_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_NEXTSTATE_SHIFT 8 /**< Shift value for LESENSE_NEXTSTATE */
-#define _LESENSE_ST_TCONFA_NEXTSTATE_MASK 0x1F00UL /**< Bit mask for LESENSE_NEXTSTATE */
-#define _LESENSE_ST_TCONFA_NEXTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_NEXTSTATE_DEFAULT (_LESENSE_ST_TCONFA_NEXTSTATE_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_CHAIN (0x1UL << 14) /**< Enable State Descriptor Chaining */
-#define _LESENSE_ST_TCONFA_CHAIN_SHIFT 14 /**< Shift value for LESENSE_CHAIN */
-#define _LESENSE_ST_TCONFA_CHAIN_MASK 0x4000UL /**< Bit mask for LESENSE_CHAIN */
-#define _LESENSE_ST_TCONFA_CHAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_CHAIN_DEFAULT (_LESENSE_ST_TCONFA_CHAIN_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_SETIF (0x1UL << 15) /**< Set Interrupt Flag Enable */
-#define _LESENSE_ST_TCONFA_SETIF_SHIFT 15 /**< Shift value for LESENSE_SETIF */
-#define _LESENSE_ST_TCONFA_SETIF_MASK 0x8000UL /**< Bit mask for LESENSE_SETIF */
-#define _LESENSE_ST_TCONFA_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_SETIF_DEFAULT (_LESENSE_ST_TCONFA_SETIF_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_PRSACT_SHIFT 16 /**< Shift value for LESENSE_PRSACT */
-#define _LESENSE_ST_TCONFA_PRSACT_MASK 0x70000UL /**< Bit mask for LESENSE_PRSACT */
-#define _LESENSE_ST_TCONFA_PRSACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_PRSACT_NONE 0x00000000UL /**< Mode NONE for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_PRSACT_PRS0 0x00000001UL /**< Mode PRS0 for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_PRSACT_DOWN 0x00000002UL /**< Mode DOWN for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_PRSACT_PRS01 0x00000003UL /**< Mode PRS01 for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_PRSACT_PRS2 0x00000004UL /**< Mode PRS2 for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 0x00000005UL /**< Mode UPANDPRS2 for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_PRSACT_PRS12 0x00000006UL /**< Mode PRS12 for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 0x00000006UL /**< Mode DOWNANDPRS2 for LESENSE_ST_TCONFA */
-#define _LESENSE_ST_TCONFA_PRSACT_PRS012 0x00000007UL /**< Mode PRS012 for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_PRSACT_DEFAULT (_LESENSE_ST_TCONFA_PRSACT_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_PRSACT_NONE (_LESENSE_ST_TCONFA_PRSACT_NONE << 16) /**< Shifted mode NONE for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_PRSACT_UP (_LESENSE_ST_TCONFA_PRSACT_UP << 16) /**< Shifted mode UP for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_PRSACT_PRS0 (_LESENSE_ST_TCONFA_PRSACT_PRS0 << 16) /**< Shifted mode PRS0 for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_PRSACT_PRS1 (_LESENSE_ST_TCONFA_PRSACT_PRS1 << 16) /**< Shifted mode PRS1 for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_PRSACT_DOWN (_LESENSE_ST_TCONFA_PRSACT_DOWN << 16) /**< Shifted mode DOWN for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_PRSACT_PRS01 (_LESENSE_ST_TCONFA_PRSACT_PRS01 << 16) /**< Shifted mode PRS01 for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_PRSACT_PRS2 (_LESENSE_ST_TCONFA_PRSACT_PRS2 << 16) /**< Shifted mode PRS2 for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_PRSACT_PRS02 (_LESENSE_ST_TCONFA_PRSACT_PRS02 << 16) /**< Shifted mode PRS02 for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 (_LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 << 16) /**< Shifted mode UPANDPRS2 for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_PRSACT_PRS12 (_LESENSE_ST_TCONFA_PRSACT_PRS12 << 16) /**< Shifted mode PRS12 for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 (_LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 << 16) /**< Shifted mode DOWNANDPRS2 for LESENSE_ST_TCONFA */
-#define LESENSE_ST_TCONFA_PRSACT_PRS012 (_LESENSE_ST_TCONFA_PRSACT_PRS012 << 16) /**< Shifted mode PRS012 for LESENSE_ST_TCONFA */
-
-/* Bit fields for LESENSE ST_TCONFB */
-#define _LESENSE_ST_TCONFB_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_MASK 0x00079FFFUL /**< Mask for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_COMP_SHIFT 0 /**< Shift value for LESENSE_COMP */
-#define _LESENSE_ST_TCONFB_COMP_MASK 0xFUL /**< Bit mask for LESENSE_COMP */
-#define _LESENSE_ST_TCONFB_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_COMP_DEFAULT (_LESENSE_ST_TCONFB_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_MASK_SHIFT 4 /**< Shift value for LESENSE_MASK */
-#define _LESENSE_ST_TCONFB_MASK_MASK 0xF0UL /**< Bit mask for LESENSE_MASK */
-#define _LESENSE_ST_TCONFB_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_MASK_DEFAULT (_LESENSE_ST_TCONFB_MASK_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_NEXTSTATE_SHIFT 8 /**< Shift value for LESENSE_NEXTSTATE */
-#define _LESENSE_ST_TCONFB_NEXTSTATE_MASK 0x1F00UL /**< Bit mask for LESENSE_NEXTSTATE */
-#define _LESENSE_ST_TCONFB_NEXTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_NEXTSTATE_DEFAULT (_LESENSE_ST_TCONFB_NEXTSTATE_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_SETIF (0x1UL << 15) /**< Set Interrupt Flag */
-#define _LESENSE_ST_TCONFB_SETIF_SHIFT 15 /**< Shift value for LESENSE_SETIF */
-#define _LESENSE_ST_TCONFB_SETIF_MASK 0x8000UL /**< Bit mask for LESENSE_SETIF */
-#define _LESENSE_ST_TCONFB_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_SETIF_DEFAULT (_LESENSE_ST_TCONFB_SETIF_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_PRSACT_SHIFT 16 /**< Shift value for LESENSE_PRSACT */
-#define _LESENSE_ST_TCONFB_PRSACT_MASK 0x70000UL /**< Bit mask for LESENSE_PRSACT */
-#define _LESENSE_ST_TCONFB_PRSACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_PRSACT_NONE 0x00000000UL /**< Mode NONE for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_PRSACT_PRS0 0x00000001UL /**< Mode PRS0 for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_PRSACT_DOWN 0x00000002UL /**< Mode DOWN for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_PRSACT_PRS01 0x00000003UL /**< Mode PRS01 for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_PRSACT_PRS2 0x00000004UL /**< Mode PRS2 for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 0x00000005UL /**< Mode UPANDPRS2 for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_PRSACT_PRS12 0x00000006UL /**< Mode PRS12 for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 0x00000006UL /**< Mode DOWNANDPRS2 for LESENSE_ST_TCONFB */
-#define _LESENSE_ST_TCONFB_PRSACT_PRS012 0x00000007UL /**< Mode PRS012 for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_PRSACT_DEFAULT (_LESENSE_ST_TCONFB_PRSACT_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_PRSACT_NONE (_LESENSE_ST_TCONFB_PRSACT_NONE << 16) /**< Shifted mode NONE for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_PRSACT_UP (_LESENSE_ST_TCONFB_PRSACT_UP << 16) /**< Shifted mode UP for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_PRSACT_PRS0 (_LESENSE_ST_TCONFB_PRSACT_PRS0 << 16) /**< Shifted mode PRS0 for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_PRSACT_PRS1 (_LESENSE_ST_TCONFB_PRSACT_PRS1 << 16) /**< Shifted mode PRS1 for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_PRSACT_DOWN (_LESENSE_ST_TCONFB_PRSACT_DOWN << 16) /**< Shifted mode DOWN for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_PRSACT_PRS01 (_LESENSE_ST_TCONFB_PRSACT_PRS01 << 16) /**< Shifted mode PRS01 for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_PRSACT_PRS2 (_LESENSE_ST_TCONFB_PRSACT_PRS2 << 16) /**< Shifted mode PRS2 for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_PRSACT_PRS02 (_LESENSE_ST_TCONFB_PRSACT_PRS02 << 16) /**< Shifted mode PRS02 for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 (_LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 << 16) /**< Shifted mode UPANDPRS2 for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_PRSACT_PRS12 (_LESENSE_ST_TCONFB_PRSACT_PRS12 << 16) /**< Shifted mode PRS12 for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 (_LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 << 16) /**< Shifted mode DOWNANDPRS2 for LESENSE_ST_TCONFB */
-#define LESENSE_ST_TCONFB_PRSACT_PRS012 (_LESENSE_ST_TCONFB_PRSACT_PRS012 << 16) /**< Shifted mode PRS012 for LESENSE_ST_TCONFB */
-
-/* Bit fields for LESENSE BUF_DATA */
-#define _LESENSE_BUF_DATA_RESETVALUE 0x00000000UL /**< Default value for LESENSE_BUF_DATA */
-#define _LESENSE_BUF_DATA_MASK 0x000FFFFFUL /**< Mask for LESENSE_BUF_DATA */
-#define _LESENSE_BUF_DATA_DATA_SHIFT 0 /**< Shift value for LESENSE_DATA */
-#define _LESENSE_BUF_DATA_DATA_MASK 0xFFFFUL /**< Bit mask for LESENSE_DATA */
-#define _LESENSE_BUF_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BUF_DATA */
-#define LESENSE_BUF_DATA_DATA_DEFAULT (_LESENSE_BUF_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_BUF_DATA */
-#define _LESENSE_BUF_DATA_DATASRC_SHIFT 16 /**< Shift value for LESENSE_DATASRC */
-#define _LESENSE_BUF_DATA_DATASRC_MASK 0xF0000UL /**< Bit mask for LESENSE_DATASRC */
-#define _LESENSE_BUF_DATA_DATASRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BUF_DATA */
-#define LESENSE_BUF_DATA_DATASRC_DEFAULT (_LESENSE_BUF_DATA_DATASRC_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_BUF_DATA */
-
-/* Bit fields for LESENSE CH_TIMING */
-#define _LESENSE_CH_TIMING_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_TIMING */
-#define _LESENSE_CH_TIMING_MASK 0x00FFFFFFUL /**< Mask for LESENSE_CH_TIMING */
-#define _LESENSE_CH_TIMING_EXTIME_SHIFT 0 /**< Shift value for LESENSE_EXTIME */
-#define _LESENSE_CH_TIMING_EXTIME_MASK 0x3FUL /**< Bit mask for LESENSE_EXTIME */
-#define _LESENSE_CH_TIMING_EXTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */
-#define LESENSE_CH_TIMING_EXTIME_DEFAULT (_LESENSE_CH_TIMING_EXTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */
-#define _LESENSE_CH_TIMING_SAMPLEDLY_SHIFT 6 /**< Shift value for LESENSE_SAMPLEDLY */
-#define _LESENSE_CH_TIMING_SAMPLEDLY_MASK 0x3FC0UL /**< Bit mask for LESENSE_SAMPLEDLY */
-#define _LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */
-#define LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT (_LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */
-#define _LESENSE_CH_TIMING_MEASUREDLY_SHIFT 14 /**< Shift value for LESENSE_MEASUREDLY */
-#define _LESENSE_CH_TIMING_MEASUREDLY_MASK 0xFFC000UL /**< Bit mask for LESENSE_MEASUREDLY */
-#define _LESENSE_CH_TIMING_MEASUREDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */
-#define LESENSE_CH_TIMING_MEASUREDLY_DEFAULT (_LESENSE_CH_TIMING_MEASUREDLY_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */
-
-/* Bit fields for LESENSE CH_INTERACT */
-#define _LESENSE_CH_INTERACT_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_INTERACT */
-#define _LESENSE_CH_INTERACT_MASK 0x003FFFFFUL /**< Mask for LESENSE_CH_INTERACT */
-#define _LESENSE_CH_INTERACT_THRES_SHIFT 0 /**< Shift value for LESENSE_THRES */
-#define _LESENSE_CH_INTERACT_THRES_MASK 0xFFFUL /**< Bit mask for LESENSE_THRES */
-#define _LESENSE_CH_INTERACT_THRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */
-#define LESENSE_CH_INTERACT_THRES_DEFAULT (_LESENSE_CH_INTERACT_THRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */
-#define _LESENSE_CH_INTERACT_SAMPLE_SHIFT 12 /**< Shift value for LESENSE_SAMPLE */
-#define _LESENSE_CH_INTERACT_SAMPLE_MASK 0x3000UL /**< Bit mask for LESENSE_SAMPLE */
-#define _LESENSE_CH_INTERACT_SAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */
-#define _LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT 0x00000000UL /**< Mode ACMPCOUNT for LESENSE_CH_INTERACT */
-#define _LESENSE_CH_INTERACT_SAMPLE_ACMP 0x00000001UL /**< Mode ACMP for LESENSE_CH_INTERACT */
-#define _LESENSE_CH_INTERACT_SAMPLE_ADC 0x00000002UL /**< Mode ADC for LESENSE_CH_INTERACT */
-#define _LESENSE_CH_INTERACT_SAMPLE_ADCDIFF 0x00000003UL /**< Mode ADCDIFF for LESENSE_CH_INTERACT */
-#define LESENSE_CH_INTERACT_SAMPLE_DEFAULT (_LESENSE_CH_INTERACT_SAMPLE_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */
-#define LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT (_LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT << 12) /**< Shifted mode ACMPCOUNT for LESENSE_CH_INTERACT */
-#define LESENSE_CH_INTERACT_SAMPLE_ACMP (_LESENSE_CH_INTERACT_SAMPLE_ACMP << 12) /**< Shifted mode ACMP for LESENSE_CH_INTERACT */
-#define LESENSE_CH_INTERACT_SAMPLE_ADC (_LESENSE_CH_INTERACT_SAMPLE_ADC << 12) /**< Shifted mode ADC for LESENSE_CH_INTERACT */
-#define LESENSE_CH_INTERACT_SAMPLE_ADCDIFF (_LESENSE_CH_INTERACT_SAMPLE_ADCDIFF << 12) /**< Shifted mode ADCDIFF for LESENSE_CH_INTERACT */
-#define _LESENSE_CH_INTERACT_SETIF_SHIFT 14 /**< Shift value for LESENSE_SETIF */
-#define _LESENSE_CH_INTERACT_SETIF_MASK 0x1C000UL /**< Bit mask for LESENSE_SETIF */
-#define _LESENSE_CH_INTERACT_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */
-#define _LESENSE_CH_INTERACT_SETIF_NONE 0x00000000UL /**< Mode NONE for LESENSE_CH_INTERACT */
-#define _LESENSE_CH_INTERACT_SETIF_LEVEL 0x00000001UL /**< Mode LEVEL for LESENSE_CH_INTERACT */
-#define _LESENSE_CH_INTERACT_SETIF_POSEDGE 0x00000002UL /**< Mode POSEDGE for LESENSE_CH_INTERACT */
-#define _LESENSE_CH_INTERACT_SETIF_NEGEDGE 0x00000003UL /**< Mode NEGEDGE for LESENSE_CH_INTERACT */
-#define _LESENSE_CH_INTERACT_SETIF_BOTHEDGES 0x00000004UL /**< Mode BOTHEDGES for LESENSE_CH_INTERACT */
-#define LESENSE_CH_INTERACT_SETIF_DEFAULT (_LESENSE_CH_INTERACT_SETIF_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */
-#define LESENSE_CH_INTERACT_SETIF_NONE (_LESENSE_CH_INTERACT_SETIF_NONE << 14) /**< Shifted mode NONE for LESENSE_CH_INTERACT */
-#define LESENSE_CH_INTERACT_SETIF_LEVEL (_LESENSE_CH_INTERACT_SETIF_LEVEL << 14) /**< Shifted mode LEVEL for LESENSE_CH_INTERACT */
-#define LESENSE_CH_INTERACT_SETIF_POSEDGE (_LESENSE_CH_INTERACT_SETIF_POSEDGE << 14) /**< Shifted mode POSEDGE for LESENSE_CH_INTERACT */
-#define LESENSE_CH_INTERACT_SETIF_NEGEDGE (_LESENSE_CH_INTERACT_SETIF_NEGEDGE << 14) /**< Shifted mode NEGEDGE for LESENSE_CH_INTERACT */
-#define LESENSE_CH_INTERACT_SETIF_BOTHEDGES (_LESENSE_CH_INTERACT_SETIF_BOTHEDGES << 14) /**< Shifted mode BOTHEDGES for LESENSE_CH_INTERACT */
-#define _LESENSE_CH_INTERACT_EXMODE_SHIFT 17 /**< Shift value for LESENSE_EXMODE */
-#define _LESENSE_CH_INTERACT_EXMODE_MASK 0x60000UL /**< Bit mask for LESENSE_EXMODE */
-#define _LESENSE_CH_INTERACT_EXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */
-#define _LESENSE_CH_INTERACT_EXMODE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CH_INTERACT */
-#define _LESENSE_CH_INTERACT_EXMODE_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_CH_INTERACT */
-#define _LESENSE_CH_INTERACT_EXMODE_LOW 0x00000002UL /**< Mode LOW for LESENSE_CH_INTERACT */
-#define _LESENSE_CH_INTERACT_EXMODE_DACOUT 0x00000003UL /**< Mode DACOUT for LESENSE_CH_INTERACT */
-#define LESENSE_CH_INTERACT_EXMODE_DEFAULT (_LESENSE_CH_INTERACT_EXMODE_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */
-#define LESENSE_CH_INTERACT_EXMODE_DISABLE (_LESENSE_CH_INTERACT_EXMODE_DISABLE << 17) /**< Shifted mode DISABLE for LESENSE_CH_INTERACT */
-#define LESENSE_CH_INTERACT_EXMODE_HIGH (_LESENSE_CH_INTERACT_EXMODE_HIGH << 17) /**< Shifted mode HIGH for LESENSE_CH_INTERACT */
-#define LESENSE_CH_INTERACT_EXMODE_LOW (_LESENSE_CH_INTERACT_EXMODE_LOW << 17) /**< Shifted mode LOW for LESENSE_CH_INTERACT */
-#define LESENSE_CH_INTERACT_EXMODE_DACOUT (_LESENSE_CH_INTERACT_EXMODE_DACOUT << 17) /**< Shifted mode DACOUT for LESENSE_CH_INTERACT */
-#define LESENSE_CH_INTERACT_EXCLK (0x1UL << 19) /**< Select Clock Used for Excitation Timing */
-#define _LESENSE_CH_INTERACT_EXCLK_SHIFT 19 /**< Shift value for LESENSE_EXCLK */
-#define _LESENSE_CH_INTERACT_EXCLK_MASK 0x80000UL /**< Bit mask for LESENSE_EXCLK */
-#define _LESENSE_CH_INTERACT_EXCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */
-#define _LESENSE_CH_INTERACT_EXCLK_LFACLK 0x00000000UL /**< Mode LFACLK for LESENSE_CH_INTERACT */
-#define _LESENSE_CH_INTERACT_EXCLK_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for LESENSE_CH_INTERACT */
-#define LESENSE_CH_INTERACT_EXCLK_DEFAULT (_LESENSE_CH_INTERACT_EXCLK_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */
-#define LESENSE_CH_INTERACT_EXCLK_LFACLK (_LESENSE_CH_INTERACT_EXCLK_LFACLK << 19) /**< Shifted mode LFACLK for LESENSE_CH_INTERACT */
-#define LESENSE_CH_INTERACT_EXCLK_AUXHFRCO (_LESENSE_CH_INTERACT_EXCLK_AUXHFRCO << 19) /**< Shifted mode AUXHFRCO for LESENSE_CH_INTERACT */
-#define LESENSE_CH_INTERACT_SAMPLECLK (0x1UL << 20) /**< Select Clock Used for Timing of Sample Delay */
-#define _LESENSE_CH_INTERACT_SAMPLECLK_SHIFT 20 /**< Shift value for LESENSE_SAMPLECLK */
-#define _LESENSE_CH_INTERACT_SAMPLECLK_MASK 0x100000UL /**< Bit mask for LESENSE_SAMPLECLK */
-#define _LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */
-#define _LESENSE_CH_INTERACT_SAMPLECLK_LFACLK 0x00000000UL /**< Mode LFACLK for LESENSE_CH_INTERACT */
-#define _LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for LESENSE_CH_INTERACT */
-#define LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT (_LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */
-#define LESENSE_CH_INTERACT_SAMPLECLK_LFACLK (_LESENSE_CH_INTERACT_SAMPLECLK_LFACLK << 20) /**< Shifted mode LFACLK for LESENSE_CH_INTERACT */
-#define LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO (_LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for LESENSE_CH_INTERACT */
-#define LESENSE_CH_INTERACT_ALTEX (0x1UL << 21) /**< Use Alternative Excite Pin */
-#define _LESENSE_CH_INTERACT_ALTEX_SHIFT 21 /**< Shift value for LESENSE_ALTEX */
-#define _LESENSE_CH_INTERACT_ALTEX_MASK 0x200000UL /**< Bit mask for LESENSE_ALTEX */
-#define _LESENSE_CH_INTERACT_ALTEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */
-#define LESENSE_CH_INTERACT_ALTEX_DEFAULT (_LESENSE_CH_INTERACT_ALTEX_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */
-
-/* Bit fields for LESENSE CH_EVAL */
-#define _LESENSE_CH_EVAL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_EVAL */
-#define _LESENSE_CH_EVAL_MASK 0x007FFFFFUL /**< Mask for LESENSE_CH_EVAL */
-#define _LESENSE_CH_EVAL_COMPTHRES_SHIFT 0 /**< Shift value for LESENSE_COMPTHRES */
-#define _LESENSE_CH_EVAL_COMPTHRES_MASK 0xFFFFUL /**< Bit mask for LESENSE_COMPTHRES */
-#define _LESENSE_CH_EVAL_COMPTHRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */
-#define LESENSE_CH_EVAL_COMPTHRES_DEFAULT (_LESENSE_CH_EVAL_COMPTHRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */
-#define LESENSE_CH_EVAL_COMP (0x1UL << 16) /**< Select Mode for Threshold Comparison */
-#define _LESENSE_CH_EVAL_COMP_SHIFT 16 /**< Shift value for LESENSE_COMP */
-#define _LESENSE_CH_EVAL_COMP_MASK 0x10000UL /**< Bit mask for LESENSE_COMP */
-#define _LESENSE_CH_EVAL_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */
-#define _LESENSE_CH_EVAL_COMP_LESS 0x00000000UL /**< Mode LESS for LESENSE_CH_EVAL */
-#define _LESENSE_CH_EVAL_COMP_GE 0x00000001UL /**< Mode GE for LESENSE_CH_EVAL */
-#define LESENSE_CH_EVAL_COMP_DEFAULT (_LESENSE_CH_EVAL_COMP_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */
-#define LESENSE_CH_EVAL_COMP_LESS (_LESENSE_CH_EVAL_COMP_LESS << 16) /**< Shifted mode LESS for LESENSE_CH_EVAL */
-#define LESENSE_CH_EVAL_COMP_GE (_LESENSE_CH_EVAL_COMP_GE << 16) /**< Shifted mode GE for LESENSE_CH_EVAL */
-#define LESENSE_CH_EVAL_DECODE (0x1UL << 17) /**< Send Result to Decoder */
-#define _LESENSE_CH_EVAL_DECODE_SHIFT 17 /**< Shift value for LESENSE_DECODE */
-#define _LESENSE_CH_EVAL_DECODE_MASK 0x20000UL /**< Bit mask for LESENSE_DECODE */
-#define _LESENSE_CH_EVAL_DECODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */
-#define LESENSE_CH_EVAL_DECODE_DEFAULT (_LESENSE_CH_EVAL_DECODE_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */
-#define _LESENSE_CH_EVAL_STRSAMPLE_SHIFT 18 /**< Shift value for LESENSE_STRSAMPLE */
-#define _LESENSE_CH_EVAL_STRSAMPLE_MASK 0xC0000UL /**< Bit mask for LESENSE_STRSAMPLE */
-#define _LESENSE_CH_EVAL_STRSAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */
-#define _LESENSE_CH_EVAL_STRSAMPLE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CH_EVAL */
-#define _LESENSE_CH_EVAL_STRSAMPLE_DATA 0x00000001UL /**< Mode DATA for LESENSE_CH_EVAL */
-#define _LESENSE_CH_EVAL_STRSAMPLE_DATASRC 0x00000002UL /**< Mode DATASRC for LESENSE_CH_EVAL */
-#define LESENSE_CH_EVAL_STRSAMPLE_DEFAULT (_LESENSE_CH_EVAL_STRSAMPLE_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */
-#define LESENSE_CH_EVAL_STRSAMPLE_DISABLE (_LESENSE_CH_EVAL_STRSAMPLE_DISABLE << 18) /**< Shifted mode DISABLE for LESENSE_CH_EVAL */
-#define LESENSE_CH_EVAL_STRSAMPLE_DATA (_LESENSE_CH_EVAL_STRSAMPLE_DATA << 18) /**< Shifted mode DATA for LESENSE_CH_EVAL */
-#define LESENSE_CH_EVAL_STRSAMPLE_DATASRC (_LESENSE_CH_EVAL_STRSAMPLE_DATASRC << 18) /**< Shifted mode DATASRC for LESENSE_CH_EVAL */
-#define LESENSE_CH_EVAL_SCANRESINV (0x1UL << 20) /**< Enable Inversion of Result */
-#define _LESENSE_CH_EVAL_SCANRESINV_SHIFT 20 /**< Shift value for LESENSE_SCANRESINV */
-#define _LESENSE_CH_EVAL_SCANRESINV_MASK 0x100000UL /**< Bit mask for LESENSE_SCANRESINV */
-#define _LESENSE_CH_EVAL_SCANRESINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */
-#define LESENSE_CH_EVAL_SCANRESINV_DEFAULT (_LESENSE_CH_EVAL_SCANRESINV_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */
-#define _LESENSE_CH_EVAL_MODE_SHIFT 21 /**< Shift value for LESENSE_MODE */
-#define _LESENSE_CH_EVAL_MODE_MASK 0x600000UL /**< Bit mask for LESENSE_MODE */
-#define _LESENSE_CH_EVAL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */
-#define _LESENSE_CH_EVAL_MODE_THRES 0x00000000UL /**< Mode THRES for LESENSE_CH_EVAL */
-#define _LESENSE_CH_EVAL_MODE_SLIDINGWIN 0x00000001UL /**< Mode SLIDINGWIN for LESENSE_CH_EVAL */
-#define _LESENSE_CH_EVAL_MODE_STEPDET 0x00000002UL /**< Mode STEPDET for LESENSE_CH_EVAL */
-#define LESENSE_CH_EVAL_MODE_DEFAULT (_LESENSE_CH_EVAL_MODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */
-#define LESENSE_CH_EVAL_MODE_THRES (_LESENSE_CH_EVAL_MODE_THRES << 21) /**< Shifted mode THRES for LESENSE_CH_EVAL */
-#define LESENSE_CH_EVAL_MODE_SLIDINGWIN (_LESENSE_CH_EVAL_MODE_SLIDINGWIN << 21) /**< Shifted mode SLIDINGWIN for LESENSE_CH_EVAL */
-#define LESENSE_CH_EVAL_MODE_STEPDET (_LESENSE_CH_EVAL_MODE_STEPDET << 21) /**< Shifted mode STEPDET for LESENSE_CH_EVAL */
-
-/** @} */
-/** @} End of group EFR32FG13P_LESENSE */
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_lesense_ch.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_lesense_ch.h
deleted file mode 100644
index e57d8ef4..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_lesense_ch.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_lesense_ch.h
- * @brief EFR32FG13P_LESENSE_CH register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @brief LESENSE_CH LESENSE CH Register
- * @ingroup EFR32FG13P_LESENSE
- *****************************************************************************/
-typedef struct {
- __IOM uint32_t TIMING; /**< Scan Configuration */
- __IOM uint32_t INTERACT; /**< Scan Configuration */
- __IOM uint32_t EVAL; /**< Scan Configuration */
- uint32_t RESERVED0[1]; /**< Reserved future */
-} LESENSE_CH_TypeDef;
-
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_letimer.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_letimer.h
deleted file mode 100644
index ea7e22b2..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_letimer.h
+++ /dev/null
@@ -1,629 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_letimer.h
- * @brief EFR32FG13P_LETIMER register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P_LETIMER LETIMER
- * @{
- * @brief EFR32FG13P_LETIMER Register Declaration
- *****************************************************************************/
-/** LETIMER Register Declaration */
-typedef struct {
- __IOM uint32_t CTRL; /**< Control Register */
- __IOM uint32_t CMD; /**< Command Register */
- __IM uint32_t STATUS; /**< Status Register */
- __IOM uint32_t CNT; /**< Counter Value Register */
- __IOM uint32_t COMP0; /**< Compare Value Register 0 */
- __IOM uint32_t COMP1; /**< Compare Value Register 1 */
- __IOM uint32_t REP0; /**< Repeat Counter Register 0 */
- __IOM uint32_t REP1; /**< Repeat Counter Register 1 */
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
-
- uint32_t RESERVED0[1]; /**< Reserved for future use **/
- __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
-
- uint32_t RESERVED1[2]; /**< Reserved for future use **/
- __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
- __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
-
- uint32_t RESERVED2[2]; /**< Reserved for future use **/
- __IOM uint32_t PRSSEL; /**< PRS Input Select Register */
-} LETIMER_TypeDef; /** @} */
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_LETIMER
- * @{
- * @defgroup EFR32FG13P_LETIMER_BitFields LETIMER Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for LETIMER CTRL */
-#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */
-#define _LETIMER_CTRL_MASK 0x000013FFUL /**< Mask for LETIMER_CTRL */
-#define _LETIMER_CTRL_REPMODE_SHIFT 0 /**< Shift value for LETIMER_REPMODE */
-#define _LETIMER_CTRL_REPMODE_MASK 0x3UL /**< Bit mask for LETIMER_REPMODE */
-#define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
-#define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /**< Mode FREE for LETIMER_CTRL */
-#define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LETIMER_CTRL */
-#define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /**< Mode BUFFERED for LETIMER_CTRL */
-#define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /**< Mode DOUBLE for LETIMER_CTRL */
-#define LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CTRL */
-#define LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0) /**< Shifted mode FREE for LETIMER_CTRL */
-#define LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LETIMER_CTRL */
-#define LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0) /**< Shifted mode BUFFERED for LETIMER_CTRL */
-#define LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0) /**< Shifted mode DOUBLE for LETIMER_CTRL */
-#define _LETIMER_CTRL_UFOA0_SHIFT 2 /**< Shift value for LETIMER_UFOA0 */
-#define _LETIMER_CTRL_UFOA0_MASK 0xCUL /**< Bit mask for LETIMER_UFOA0 */
-#define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
-#define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */
-#define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */
-#define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */
-#define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */
-#define LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CTRL */
-#define LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2) /**< Shifted mode NONE for LETIMER_CTRL */
-#define LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2) /**< Shifted mode TOGGLE for LETIMER_CTRL */
-#define LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2) /**< Shifted mode PULSE for LETIMER_CTRL */
-#define LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2) /**< Shifted mode PWM for LETIMER_CTRL */
-#define _LETIMER_CTRL_UFOA1_SHIFT 4 /**< Shift value for LETIMER_UFOA1 */
-#define _LETIMER_CTRL_UFOA1_MASK 0x30UL /**< Bit mask for LETIMER_UFOA1 */
-#define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
-#define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */
-#define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */
-#define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */
-#define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */
-#define LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CTRL */
-#define LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4) /**< Shifted mode NONE for LETIMER_CTRL */
-#define LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4) /**< Shifted mode TOGGLE for LETIMER_CTRL */
-#define LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4) /**< Shifted mode PULSE for LETIMER_CTRL */
-#define LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4) /**< Shifted mode PWM for LETIMER_CTRL */
-#define LETIMER_CTRL_OPOL0 (0x1UL << 6) /**< Output 0 Polarity */
-#define _LETIMER_CTRL_OPOL0_SHIFT 6 /**< Shift value for LETIMER_OPOL0 */
-#define _LETIMER_CTRL_OPOL0_MASK 0x40UL /**< Bit mask for LETIMER_OPOL0 */
-#define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
-#define LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_CTRL */
-#define LETIMER_CTRL_OPOL1 (0x1UL << 7) /**< Output 1 Polarity */
-#define _LETIMER_CTRL_OPOL1_SHIFT 7 /**< Shift value for LETIMER_OPOL1 */
-#define _LETIMER_CTRL_OPOL1_MASK 0x80UL /**< Bit mask for LETIMER_OPOL1 */
-#define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
-#define LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_CTRL */
-#define LETIMER_CTRL_BUFTOP (0x1UL << 8) /**< Buffered Top */
-#define _LETIMER_CTRL_BUFTOP_SHIFT 8 /**< Shift value for LETIMER_BUFTOP */
-#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */
-#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
-#define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */
-#define LETIMER_CTRL_COMP0TOP (0x1UL << 9) /**< Compare Value 0 is Top Value */
-#define _LETIMER_CTRL_COMP0TOP_SHIFT 9 /**< Shift value for LETIMER_COMP0TOP */
-#define _LETIMER_CTRL_COMP0TOP_MASK 0x200UL /**< Bit mask for LETIMER_COMP0TOP */
-#define _LETIMER_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
-#define LETIMER_CTRL_COMP0TOP_DEFAULT (_LETIMER_CTRL_COMP0TOP_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_CTRL */
-#define LETIMER_CTRL_DEBUGRUN (0x1UL << 12) /**< Debug Mode Run Enable */
-#define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /**< Shift value for LETIMER_DEBUGRUN */
-#define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /**< Bit mask for LETIMER_DEBUGRUN */
-#define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
-#define LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_CTRL */
-
-/* Bit fields for LETIMER CMD */
-#define _LETIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CMD */
-#define _LETIMER_CMD_MASK 0x0000001FUL /**< Mask for LETIMER_CMD */
-#define LETIMER_CMD_START (0x1UL << 0) /**< Start LETIMER */
-#define _LETIMER_CMD_START_SHIFT 0 /**< Shift value for LETIMER_START */
-#define _LETIMER_CMD_START_MASK 0x1UL /**< Bit mask for LETIMER_START */
-#define _LETIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
-#define LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CMD */
-#define LETIMER_CMD_STOP (0x1UL << 1) /**< Stop LETIMER */
-#define _LETIMER_CMD_STOP_SHIFT 1 /**< Shift value for LETIMER_STOP */
-#define _LETIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for LETIMER_STOP */
-#define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
-#define LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_CMD */
-#define LETIMER_CMD_CLEAR (0x1UL << 2) /**< Clear LETIMER */
-#define _LETIMER_CMD_CLEAR_SHIFT 2 /**< Shift value for LETIMER_CLEAR */
-#define _LETIMER_CMD_CLEAR_MASK 0x4UL /**< Bit mask for LETIMER_CLEAR */
-#define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
-#define LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CMD */
-#define LETIMER_CMD_CTO0 (0x1UL << 3) /**< Clear Toggle Output 0 */
-#define _LETIMER_CMD_CTO0_SHIFT 3 /**< Shift value for LETIMER_CTO0 */
-#define _LETIMER_CMD_CTO0_MASK 0x8UL /**< Bit mask for LETIMER_CTO0 */
-#define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
-#define LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_CMD */
-#define LETIMER_CMD_CTO1 (0x1UL << 4) /**< Clear Toggle Output 1 */
-#define _LETIMER_CMD_CTO1_SHIFT 4 /**< Shift value for LETIMER_CTO1 */
-#define _LETIMER_CMD_CTO1_MASK 0x10UL /**< Bit mask for LETIMER_CTO1 */
-#define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
-#define LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CMD */
-
-/* Bit fields for LETIMER STATUS */
-#define _LETIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_STATUS */
-#define _LETIMER_STATUS_MASK 0x00000001UL /**< Mask for LETIMER_STATUS */
-#define LETIMER_STATUS_RUNNING (0x1UL << 0) /**< LETIMER Running */
-#define _LETIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for LETIMER_RUNNING */
-#define _LETIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for LETIMER_RUNNING */
-#define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */
-#define LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_STATUS */
-
-/* Bit fields for LETIMER CNT */
-#define _LETIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CNT */
-#define _LETIMER_CNT_MASK 0x0000FFFFUL /**< Mask for LETIMER_CNT */
-#define _LETIMER_CNT_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */
-#define _LETIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for LETIMER_CNT */
-#define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CNT */
-#define LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CNT */
-
-/* Bit fields for LETIMER COMP0 */
-#define _LETIMER_COMP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP0 */
-#define _LETIMER_COMP0_MASK 0x0000FFFFUL /**< Mask for LETIMER_COMP0 */
-#define _LETIMER_COMP0_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
-#define _LETIMER_COMP0_COMP0_MASK 0xFFFFUL /**< Bit mask for LETIMER_COMP0 */
-#define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP0 */
-#define LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP0 */
-
-/* Bit fields for LETIMER COMP1 */
-#define _LETIMER_COMP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP1 */
-#define _LETIMER_COMP1_MASK 0x0000FFFFUL /**< Mask for LETIMER_COMP1 */
-#define _LETIMER_COMP1_COMP1_SHIFT 0 /**< Shift value for LETIMER_COMP1 */
-#define _LETIMER_COMP1_COMP1_MASK 0xFFFFUL /**< Bit mask for LETIMER_COMP1 */
-#define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP1 */
-#define LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP1 */
-
-/* Bit fields for LETIMER REP0 */
-#define _LETIMER_REP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP0 */
-#define _LETIMER_REP0_MASK 0x000000FFUL /**< Mask for LETIMER_REP0 */
-#define _LETIMER_REP0_REP0_SHIFT 0 /**< Shift value for LETIMER_REP0 */
-#define _LETIMER_REP0_REP0_MASK 0xFFUL /**< Bit mask for LETIMER_REP0 */
-#define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP0 */
-#define LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP0 */
-
-/* Bit fields for LETIMER REP1 */
-#define _LETIMER_REP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP1 */
-#define _LETIMER_REP1_MASK 0x000000FFUL /**< Mask for LETIMER_REP1 */
-#define _LETIMER_REP1_REP1_SHIFT 0 /**< Shift value for LETIMER_REP1 */
-#define _LETIMER_REP1_REP1_MASK 0xFFUL /**< Bit mask for LETIMER_REP1 */
-#define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP1 */
-#define LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP1 */
-
-/* Bit fields for LETIMER IF */
-#define _LETIMER_IF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IF */
-#define _LETIMER_IF_MASK 0x0000001FUL /**< Mask for LETIMER_IF */
-#define LETIMER_IF_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Flag */
-#define _LETIMER_IF_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
-#define _LETIMER_IF_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */
-#define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
-#define LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IF */
-#define LETIMER_IF_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Flag */
-#define _LETIMER_IF_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */
-#define _LETIMER_IF_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */
-#define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
-#define LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IF */
-#define LETIMER_IF_UF (0x1UL << 2) /**< Underflow Interrupt Flag */
-#define _LETIMER_IF_UF_SHIFT 2 /**< Shift value for LETIMER_UF */
-#define _LETIMER_IF_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */
-#define _LETIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
-#define LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IF */
-#define LETIMER_IF_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Flag */
-#define _LETIMER_IF_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */
-#define _LETIMER_IF_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */
-#define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
-#define LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IF */
-#define LETIMER_IF_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Flag */
-#define _LETIMER_IF_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */
-#define _LETIMER_IF_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */
-#define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
-#define LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IF */
-
-/* Bit fields for LETIMER IFS */
-#define _LETIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IFS */
-#define _LETIMER_IFS_MASK 0x0000001FUL /**< Mask for LETIMER_IFS */
-#define LETIMER_IFS_COMP0 (0x1UL << 0) /**< Set COMP0 Interrupt Flag */
-#define _LETIMER_IFS_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
-#define _LETIMER_IFS_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */
-#define _LETIMER_IFS_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */
-#define LETIMER_IFS_COMP0_DEFAULT (_LETIMER_IFS_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IFS */
-#define LETIMER_IFS_COMP1 (0x1UL << 1) /**< Set COMP1 Interrupt Flag */
-#define _LETIMER_IFS_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */
-#define _LETIMER_IFS_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */
-#define _LETIMER_IFS_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */
-#define LETIMER_IFS_COMP1_DEFAULT (_LETIMER_IFS_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IFS */
-#define LETIMER_IFS_UF (0x1UL << 2) /**< Set UF Interrupt Flag */
-#define _LETIMER_IFS_UF_SHIFT 2 /**< Shift value for LETIMER_UF */
-#define _LETIMER_IFS_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */
-#define _LETIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */
-#define LETIMER_IFS_UF_DEFAULT (_LETIMER_IFS_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IFS */
-#define LETIMER_IFS_REP0 (0x1UL << 3) /**< Set REP0 Interrupt Flag */
-#define _LETIMER_IFS_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */
-#define _LETIMER_IFS_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */
-#define _LETIMER_IFS_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */
-#define LETIMER_IFS_REP0_DEFAULT (_LETIMER_IFS_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IFS */
-#define LETIMER_IFS_REP1 (0x1UL << 4) /**< Set REP1 Interrupt Flag */
-#define _LETIMER_IFS_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */
-#define _LETIMER_IFS_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */
-#define _LETIMER_IFS_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */
-#define LETIMER_IFS_REP1_DEFAULT (_LETIMER_IFS_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IFS */
-
-/* Bit fields for LETIMER IFC */
-#define _LETIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IFC */
-#define _LETIMER_IFC_MASK 0x0000001FUL /**< Mask for LETIMER_IFC */
-#define LETIMER_IFC_COMP0 (0x1UL << 0) /**< Clear COMP0 Interrupt Flag */
-#define _LETIMER_IFC_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
-#define _LETIMER_IFC_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */
-#define _LETIMER_IFC_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */
-#define LETIMER_IFC_COMP0_DEFAULT (_LETIMER_IFC_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IFC */
-#define LETIMER_IFC_COMP1 (0x1UL << 1) /**< Clear COMP1 Interrupt Flag */
-#define _LETIMER_IFC_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */
-#define _LETIMER_IFC_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */
-#define _LETIMER_IFC_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */
-#define LETIMER_IFC_COMP1_DEFAULT (_LETIMER_IFC_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IFC */
-#define LETIMER_IFC_UF (0x1UL << 2) /**< Clear UF Interrupt Flag */
-#define _LETIMER_IFC_UF_SHIFT 2 /**< Shift value for LETIMER_UF */
-#define _LETIMER_IFC_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */
-#define _LETIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */
-#define LETIMER_IFC_UF_DEFAULT (_LETIMER_IFC_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IFC */
-#define LETIMER_IFC_REP0 (0x1UL << 3) /**< Clear REP0 Interrupt Flag */
-#define _LETIMER_IFC_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */
-#define _LETIMER_IFC_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */
-#define _LETIMER_IFC_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */
-#define LETIMER_IFC_REP0_DEFAULT (_LETIMER_IFC_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IFC */
-#define LETIMER_IFC_REP1 (0x1UL << 4) /**< Clear REP1 Interrupt Flag */
-#define _LETIMER_IFC_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */
-#define _LETIMER_IFC_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */
-#define _LETIMER_IFC_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */
-#define LETIMER_IFC_REP1_DEFAULT (_LETIMER_IFC_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IFC */
-
-/* Bit fields for LETIMER IEN */
-#define _LETIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IEN */
-#define _LETIMER_IEN_MASK 0x0000001FUL /**< Mask for LETIMER_IEN */
-#define LETIMER_IEN_COMP0 (0x1UL << 0) /**< COMP0 Interrupt Enable */
-#define _LETIMER_IEN_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
-#define _LETIMER_IEN_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */
-#define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
-#define LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IEN */
-#define LETIMER_IEN_COMP1 (0x1UL << 1) /**< COMP1 Interrupt Enable */
-#define _LETIMER_IEN_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */
-#define _LETIMER_IEN_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */
-#define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
-#define LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IEN */
-#define LETIMER_IEN_UF (0x1UL << 2) /**< UF Interrupt Enable */
-#define _LETIMER_IEN_UF_SHIFT 2 /**< Shift value for LETIMER_UF */
-#define _LETIMER_IEN_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */
-#define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
-#define LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IEN */
-#define LETIMER_IEN_REP0 (0x1UL << 3) /**< REP0 Interrupt Enable */
-#define _LETIMER_IEN_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */
-#define _LETIMER_IEN_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */
-#define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
-#define LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IEN */
-#define LETIMER_IEN_REP1 (0x1UL << 4) /**< REP1 Interrupt Enable */
-#define _LETIMER_IEN_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */
-#define _LETIMER_IEN_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */
-#define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
-#define LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IEN */
-
-/* Bit fields for LETIMER SYNCBUSY */
-#define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SYNCBUSY */
-#define _LETIMER_SYNCBUSY_MASK 0x00000002UL /**< Mask for LETIMER_SYNCBUSY */
-#define LETIMER_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */
-#define _LETIMER_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LETIMER_CMD */
-#define _LETIMER_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LETIMER_CMD */
-#define _LETIMER_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
-#define LETIMER_SYNCBUSY_CMD_DEFAULT (_LETIMER_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
-
-/* Bit fields for LETIMER ROUTEPEN */
-#define _LETIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_ROUTEPEN */
-#define _LETIMER_ROUTEPEN_MASK 0x00000003UL /**< Mask for LETIMER_ROUTEPEN */
-#define LETIMER_ROUTEPEN_OUT0PEN (0x1UL << 0) /**< Output 0 Pin Enable */
-#define _LETIMER_ROUTEPEN_OUT0PEN_SHIFT 0 /**< Shift value for LETIMER_OUT0PEN */
-#define _LETIMER_ROUTEPEN_OUT0PEN_MASK 0x1UL /**< Bit mask for LETIMER_OUT0PEN */
-#define _LETIMER_ROUTEPEN_OUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTEPEN */
-#define LETIMER_ROUTEPEN_OUT0PEN_DEFAULT (_LETIMER_ROUTEPEN_OUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_ROUTEPEN */
-#define LETIMER_ROUTEPEN_OUT1PEN (0x1UL << 1) /**< Output 1 Pin Enable */
-#define _LETIMER_ROUTEPEN_OUT1PEN_SHIFT 1 /**< Shift value for LETIMER_OUT1PEN */
-#define _LETIMER_ROUTEPEN_OUT1PEN_MASK 0x2UL /**< Bit mask for LETIMER_OUT1PEN */
-#define _LETIMER_ROUTEPEN_OUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTEPEN */
-#define LETIMER_ROUTEPEN_OUT1PEN_DEFAULT (_LETIMER_ROUTEPEN_OUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_ROUTEPEN */
-
-/* Bit fields for LETIMER ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_SHIFT 0 /**< Shift value for LETIMER_OUT0LOC */
-#define _LETIMER_ROUTELOC0_OUT0LOC_MASK 0x1FUL /**< Bit mask for LETIMER_OUT0LOC */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC6 0x00000006UL /**< Mode LOC6 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC7 0x00000007UL /**< Mode LOC7 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC8 0x00000008UL /**< Mode LOC8 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC9 0x00000009UL /**< Mode LOC9 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC16 0x00000010UL /**< Mode LOC16 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC17 0x00000011UL /**< Mode LOC17 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC18 0x00000012UL /**< Mode LOC18 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC19 0x00000013UL /**< Mode LOC19 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC20 0x00000014UL /**< Mode LOC20 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC21 0x00000015UL /**< Mode LOC21 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC22 0x00000016UL /**< Mode LOC22 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC23 0x00000017UL /**< Mode LOC23 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC24 0x00000018UL /**< Mode LOC24 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC25 0x00000019UL /**< Mode LOC25 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC0 (_LETIMER_ROUTELOC0_OUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_DEFAULT (_LETIMER_ROUTELOC0_OUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC1 (_LETIMER_ROUTELOC0_OUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC2 (_LETIMER_ROUTELOC0_OUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC3 (_LETIMER_ROUTELOC0_OUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC4 (_LETIMER_ROUTELOC0_OUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC5 (_LETIMER_ROUTELOC0_OUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC6 (_LETIMER_ROUTELOC0_OUT0LOC_LOC6 << 0) /**< Shifted mode LOC6 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC7 (_LETIMER_ROUTELOC0_OUT0LOC_LOC7 << 0) /**< Shifted mode LOC7 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC8 (_LETIMER_ROUTELOC0_OUT0LOC_LOC8 << 0) /**< Shifted mode LOC8 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC9 (_LETIMER_ROUTELOC0_OUT0LOC_LOC9 << 0) /**< Shifted mode LOC9 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC10 (_LETIMER_ROUTELOC0_OUT0LOC_LOC10 << 0) /**< Shifted mode LOC10 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC11 (_LETIMER_ROUTELOC0_OUT0LOC_LOC11 << 0) /**< Shifted mode LOC11 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC12 (_LETIMER_ROUTELOC0_OUT0LOC_LOC12 << 0) /**< Shifted mode LOC12 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC13 (_LETIMER_ROUTELOC0_OUT0LOC_LOC13 << 0) /**< Shifted mode LOC13 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC14 (_LETIMER_ROUTELOC0_OUT0LOC_LOC14 << 0) /**< Shifted mode LOC14 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC15 (_LETIMER_ROUTELOC0_OUT0LOC_LOC15 << 0) /**< Shifted mode LOC15 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC16 (_LETIMER_ROUTELOC0_OUT0LOC_LOC16 << 0) /**< Shifted mode LOC16 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC17 (_LETIMER_ROUTELOC0_OUT0LOC_LOC17 << 0) /**< Shifted mode LOC17 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC18 (_LETIMER_ROUTELOC0_OUT0LOC_LOC18 << 0) /**< Shifted mode LOC18 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC19 (_LETIMER_ROUTELOC0_OUT0LOC_LOC19 << 0) /**< Shifted mode LOC19 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC20 (_LETIMER_ROUTELOC0_OUT0LOC_LOC20 << 0) /**< Shifted mode LOC20 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC21 (_LETIMER_ROUTELOC0_OUT0LOC_LOC21 << 0) /**< Shifted mode LOC21 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC22 (_LETIMER_ROUTELOC0_OUT0LOC_LOC22 << 0) /**< Shifted mode LOC22 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC23 (_LETIMER_ROUTELOC0_OUT0LOC_LOC23 << 0) /**< Shifted mode LOC23 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC24 (_LETIMER_ROUTELOC0_OUT0LOC_LOC24 << 0) /**< Shifted mode LOC24 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC25 (_LETIMER_ROUTELOC0_OUT0LOC_LOC25 << 0) /**< Shifted mode LOC25 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC26 (_LETIMER_ROUTELOC0_OUT0LOC_LOC26 << 0) /**< Shifted mode LOC26 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC27 (_LETIMER_ROUTELOC0_OUT0LOC_LOC27 << 0) /**< Shifted mode LOC27 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC28 (_LETIMER_ROUTELOC0_OUT0LOC_LOC28 << 0) /**< Shifted mode LOC28 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC29 (_LETIMER_ROUTELOC0_OUT0LOC_LOC29 << 0) /**< Shifted mode LOC29 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC30 (_LETIMER_ROUTELOC0_OUT0LOC_LOC30 << 0) /**< Shifted mode LOC30 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT0LOC_LOC31 (_LETIMER_ROUTELOC0_OUT0LOC_LOC31 << 0) /**< Shifted mode LOC31 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_SHIFT 8 /**< Shift value for LETIMER_OUT1LOC */
-#define _LETIMER_ROUTELOC0_OUT1LOC_MASK 0x1F00UL /**< Bit mask for LETIMER_OUT1LOC */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC6 0x00000006UL /**< Mode LOC6 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC7 0x00000007UL /**< Mode LOC7 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC8 0x00000008UL /**< Mode LOC8 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC9 0x00000009UL /**< Mode LOC9 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC16 0x00000010UL /**< Mode LOC16 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC17 0x00000011UL /**< Mode LOC17 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC18 0x00000012UL /**< Mode LOC18 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC19 0x00000013UL /**< Mode LOC19 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC20 0x00000014UL /**< Mode LOC20 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC21 0x00000015UL /**< Mode LOC21 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC22 0x00000016UL /**< Mode LOC22 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC23 0x00000017UL /**< Mode LOC23 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC24 0x00000018UL /**< Mode LOC24 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC25 0x00000019UL /**< Mode LOC25 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for LETIMER_ROUTELOC0 */
-#define _LETIMER_ROUTELOC0_OUT1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC0 (_LETIMER_ROUTELOC0_OUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_DEFAULT (_LETIMER_ROUTELOC0_OUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC1 (_LETIMER_ROUTELOC0_OUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC2 (_LETIMER_ROUTELOC0_OUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC3 (_LETIMER_ROUTELOC0_OUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC4 (_LETIMER_ROUTELOC0_OUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC5 (_LETIMER_ROUTELOC0_OUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC6 (_LETIMER_ROUTELOC0_OUT1LOC_LOC6 << 8) /**< Shifted mode LOC6 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC7 (_LETIMER_ROUTELOC0_OUT1LOC_LOC7 << 8) /**< Shifted mode LOC7 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC8 (_LETIMER_ROUTELOC0_OUT1LOC_LOC8 << 8) /**< Shifted mode LOC8 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC9 (_LETIMER_ROUTELOC0_OUT1LOC_LOC9 << 8) /**< Shifted mode LOC9 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC10 (_LETIMER_ROUTELOC0_OUT1LOC_LOC10 << 8) /**< Shifted mode LOC10 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC11 (_LETIMER_ROUTELOC0_OUT1LOC_LOC11 << 8) /**< Shifted mode LOC11 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC12 (_LETIMER_ROUTELOC0_OUT1LOC_LOC12 << 8) /**< Shifted mode LOC12 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC13 (_LETIMER_ROUTELOC0_OUT1LOC_LOC13 << 8) /**< Shifted mode LOC13 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC14 (_LETIMER_ROUTELOC0_OUT1LOC_LOC14 << 8) /**< Shifted mode LOC14 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC15 (_LETIMER_ROUTELOC0_OUT1LOC_LOC15 << 8) /**< Shifted mode LOC15 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC16 (_LETIMER_ROUTELOC0_OUT1LOC_LOC16 << 8) /**< Shifted mode LOC16 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC17 (_LETIMER_ROUTELOC0_OUT1LOC_LOC17 << 8) /**< Shifted mode LOC17 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC18 (_LETIMER_ROUTELOC0_OUT1LOC_LOC18 << 8) /**< Shifted mode LOC18 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC19 (_LETIMER_ROUTELOC0_OUT1LOC_LOC19 << 8) /**< Shifted mode LOC19 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC20 (_LETIMER_ROUTELOC0_OUT1LOC_LOC20 << 8) /**< Shifted mode LOC20 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC21 (_LETIMER_ROUTELOC0_OUT1LOC_LOC21 << 8) /**< Shifted mode LOC21 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC22 (_LETIMER_ROUTELOC0_OUT1LOC_LOC22 << 8) /**< Shifted mode LOC22 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC23 (_LETIMER_ROUTELOC0_OUT1LOC_LOC23 << 8) /**< Shifted mode LOC23 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC24 (_LETIMER_ROUTELOC0_OUT1LOC_LOC24 << 8) /**< Shifted mode LOC24 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC25 (_LETIMER_ROUTELOC0_OUT1LOC_LOC25 << 8) /**< Shifted mode LOC25 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC26 (_LETIMER_ROUTELOC0_OUT1LOC_LOC26 << 8) /**< Shifted mode LOC26 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC27 (_LETIMER_ROUTELOC0_OUT1LOC_LOC27 << 8) /**< Shifted mode LOC27 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC28 (_LETIMER_ROUTELOC0_OUT1LOC_LOC28 << 8) /**< Shifted mode LOC28 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC29 (_LETIMER_ROUTELOC0_OUT1LOC_LOC29 << 8) /**< Shifted mode LOC29 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC30 (_LETIMER_ROUTELOC0_OUT1LOC_LOC30 << 8) /**< Shifted mode LOC30 for LETIMER_ROUTELOC0 */
-#define LETIMER_ROUTELOC0_OUT1LOC_LOC31 (_LETIMER_ROUTELOC0_OUT1LOC_LOC31 << 8) /**< Shifted mode LOC31 for LETIMER_ROUTELOC0 */
-
-/* Bit fields for LETIMER PRSSEL */
-#define _LETIMER_PRSSEL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_MASK 0x0CCCF3CFUL /**< Mask for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTARTSEL_SHIFT 0 /**< Shift value for LETIMER_PRSSTARTSEL */
-#define _LETIMER_PRSSEL_PRSSTARTSEL_MASK 0xFUL /**< Bit mask for LETIMER_PRSSTARTSEL */
-#define _LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT (_LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTOPSEL_SHIFT 6 /**< Shift value for LETIMER_PRSSTOPSEL */
-#define _LETIMER_PRSSEL_PRSSTOPSEL_MASK 0x3C0UL /**< Bit mask for LETIMER_PRSSTOPSEL */
-#define _LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT (_LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSCLEARSEL_SHIFT 12 /**< Shift value for LETIMER_PRSCLEARSEL */
-#define _LETIMER_PRSSEL_PRSCLEARSEL_MASK 0xF000UL /**< Bit mask for LETIMER_PRSCLEARSEL */
-#define _LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT (_LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 << 12) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 << 12) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 << 12) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 << 12) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 << 12) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 << 12) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 << 12) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 << 12) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 << 12) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 << 12) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 << 12) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 << 12) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTARTMODE_SHIFT 18 /**< Shift value for LETIMER_PRSSTARTMODE */
-#define _LETIMER_PRSSEL_PRSSTARTMODE_MASK 0xC0000UL /**< Bit mask for LETIMER_PRSSTARTMODE */
-#define _LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTARTMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTARTMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTARTMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTARTMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT (_LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTARTMODE_NONE (_LETIMER_PRSSEL_PRSSTARTMODE_NONE << 18) /**< Shifted mode NONE for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTARTMODE_RISING (_LETIMER_PRSSEL_PRSSTARTMODE_RISING << 18) /**< Shifted mode RISING for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTARTMODE_FALLING (_LETIMER_PRSSEL_PRSSTARTMODE_FALLING << 18) /**< Shifted mode FALLING for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTARTMODE_BOTH (_LETIMER_PRSSEL_PRSSTARTMODE_BOTH << 18) /**< Shifted mode BOTH for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTOPMODE_SHIFT 22 /**< Shift value for LETIMER_PRSSTOPMODE */
-#define _LETIMER_PRSSEL_PRSSTOPMODE_MASK 0xC00000UL /**< Bit mask for LETIMER_PRSSTOPMODE */
-#define _LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTOPMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTOPMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTOPMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSSTOPMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT (_LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTOPMODE_NONE (_LETIMER_PRSSEL_PRSSTOPMODE_NONE << 22) /**< Shifted mode NONE for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTOPMODE_RISING (_LETIMER_PRSSEL_PRSSTOPMODE_RISING << 22) /**< Shifted mode RISING for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTOPMODE_FALLING (_LETIMER_PRSSEL_PRSSTOPMODE_FALLING << 22) /**< Shifted mode FALLING for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSSTOPMODE_BOTH (_LETIMER_PRSSEL_PRSSTOPMODE_BOTH << 22) /**< Shifted mode BOTH for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSCLEARMODE_SHIFT 26 /**< Shift value for LETIMER_PRSCLEARMODE */
-#define _LETIMER_PRSSEL_PRSCLEARMODE_MASK 0xC000000UL /**< Bit mask for LETIMER_PRSCLEARMODE */
-#define _LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSCLEARMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSCLEARMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSCLEARMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */
-#define _LETIMER_PRSSEL_PRSCLEARMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT (_LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSCLEARMODE_NONE (_LETIMER_PRSSEL_PRSCLEARMODE_NONE << 26) /**< Shifted mode NONE for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSCLEARMODE_RISING (_LETIMER_PRSSEL_PRSCLEARMODE_RISING << 26) /**< Shifted mode RISING for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSCLEARMODE_FALLING (_LETIMER_PRSSEL_PRSCLEARMODE_FALLING << 26) /**< Shifted mode FALLING for LETIMER_PRSSEL */
-#define LETIMER_PRSSEL_PRSCLEARMODE_BOTH (_LETIMER_PRSSEL_PRSCLEARMODE_BOTH << 26) /**< Shifted mode BOTH for LETIMER_PRSSEL */
-
-/** @} */
-/** @} End of group EFR32FG13P_LETIMER */
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_leuart.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_leuart.h
deleted file mode 100644
index e2eb1805..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_leuart.h
+++ /dev/null
@@ -1,844 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_leuart.h
- * @brief EFR32FG13P_LEUART register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P_LEUART LEUART
- * @{
- * @brief EFR32FG13P_LEUART Register Declaration
- *****************************************************************************/
-/** LEUART Register Declaration */
-typedef struct {
- __IOM uint32_t CTRL; /**< Control Register */
- __IOM uint32_t CMD; /**< Command Register */
- __IM uint32_t STATUS; /**< Status Register */
- __IOM uint32_t CLKDIV; /**< Clock Control Register */
- __IOM uint32_t STARTFRAME; /**< Start Frame Register */
- __IOM uint32_t SIGFRAME; /**< Signal Frame Register */
- __IM uint32_t RXDATAX; /**< Receive Buffer Data Extended Register */
- __IM uint32_t RXDATA; /**< Receive Buffer Data Register */
- __IM uint32_t RXDATAXP; /**< Receive Buffer Data Extended Peek Register */
- __IOM uint32_t TXDATAX; /**< Transmit Buffer Data Extended Register */
- __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- __IOM uint32_t PULSECTRL; /**< Pulse Control Register */
-
- __IOM uint32_t FREEZE; /**< Freeze Register */
- __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
-
- uint32_t RESERVED0[3]; /**< Reserved for future use **/
- __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
- __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
- uint32_t RESERVED1[2]; /**< Reserved for future use **/
- __IOM uint32_t INPUT; /**< LEUART Input Register */
-} LEUART_TypeDef; /** @} */
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_LEUART
- * @{
- * @defgroup EFR32FG13P_LEUART_BitFields LEUART Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for LEUART CTRL */
-#define _LEUART_CTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_CTRL */
-#define _LEUART_CTRL_MASK 0x0000FFFFUL /**< Mask for LEUART_CTRL */
-#define LEUART_CTRL_AUTOTRI (0x1UL << 0) /**< Automatic Transmitter Tristate */
-#define _LEUART_CTRL_AUTOTRI_SHIFT 0 /**< Shift value for LEUART_AUTOTRI */
-#define _LEUART_CTRL_AUTOTRI_MASK 0x1UL /**< Bit mask for LEUART_AUTOTRI */
-#define _LEUART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
-#define LEUART_CTRL_AUTOTRI_DEFAULT (_LEUART_CTRL_AUTOTRI_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CTRL */
-#define LEUART_CTRL_DATABITS (0x1UL << 1) /**< Data-Bit Mode */
-#define _LEUART_CTRL_DATABITS_SHIFT 1 /**< Shift value for LEUART_DATABITS */
-#define _LEUART_CTRL_DATABITS_MASK 0x2UL /**< Bit mask for LEUART_DATABITS */
-#define _LEUART_CTRL_DATABITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
-#define _LEUART_CTRL_DATABITS_EIGHT 0x00000000UL /**< Mode EIGHT for LEUART_CTRL */
-#define _LEUART_CTRL_DATABITS_NINE 0x00000001UL /**< Mode NINE for LEUART_CTRL */
-#define LEUART_CTRL_DATABITS_DEFAULT (_LEUART_CTRL_DATABITS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CTRL */
-#define LEUART_CTRL_DATABITS_EIGHT (_LEUART_CTRL_DATABITS_EIGHT << 1) /**< Shifted mode EIGHT for LEUART_CTRL */
-#define LEUART_CTRL_DATABITS_NINE (_LEUART_CTRL_DATABITS_NINE << 1) /**< Shifted mode NINE for LEUART_CTRL */
-#define _LEUART_CTRL_PARITY_SHIFT 2 /**< Shift value for LEUART_PARITY */
-#define _LEUART_CTRL_PARITY_MASK 0xCUL /**< Bit mask for LEUART_PARITY */
-#define _LEUART_CTRL_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
-#define _LEUART_CTRL_PARITY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */
-#define _LEUART_CTRL_PARITY_EVEN 0x00000002UL /**< Mode EVEN for LEUART_CTRL */
-#define _LEUART_CTRL_PARITY_ODD 0x00000003UL /**< Mode ODD for LEUART_CTRL */
-#define LEUART_CTRL_PARITY_DEFAULT (_LEUART_CTRL_PARITY_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CTRL */
-#define LEUART_CTRL_PARITY_NONE (_LEUART_CTRL_PARITY_NONE << 2) /**< Shifted mode NONE for LEUART_CTRL */
-#define LEUART_CTRL_PARITY_EVEN (_LEUART_CTRL_PARITY_EVEN << 2) /**< Shifted mode EVEN for LEUART_CTRL */
-#define LEUART_CTRL_PARITY_ODD (_LEUART_CTRL_PARITY_ODD << 2) /**< Shifted mode ODD for LEUART_CTRL */
-#define LEUART_CTRL_STOPBITS (0x1UL << 4) /**< Stop-Bit Mode */
-#define _LEUART_CTRL_STOPBITS_SHIFT 4 /**< Shift value for LEUART_STOPBITS */
-#define _LEUART_CTRL_STOPBITS_MASK 0x10UL /**< Bit mask for LEUART_STOPBITS */
-#define _LEUART_CTRL_STOPBITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
-#define _LEUART_CTRL_STOPBITS_ONE 0x00000000UL /**< Mode ONE for LEUART_CTRL */
-#define _LEUART_CTRL_STOPBITS_TWO 0x00000001UL /**< Mode TWO for LEUART_CTRL */
-#define LEUART_CTRL_STOPBITS_DEFAULT (_LEUART_CTRL_STOPBITS_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CTRL */
-#define LEUART_CTRL_STOPBITS_ONE (_LEUART_CTRL_STOPBITS_ONE << 4) /**< Shifted mode ONE for LEUART_CTRL */
-#define LEUART_CTRL_STOPBITS_TWO (_LEUART_CTRL_STOPBITS_TWO << 4) /**< Shifted mode TWO for LEUART_CTRL */
-#define LEUART_CTRL_INV (0x1UL << 5) /**< Invert Input and Output */
-#define _LEUART_CTRL_INV_SHIFT 5 /**< Shift value for LEUART_INV */
-#define _LEUART_CTRL_INV_MASK 0x20UL /**< Bit mask for LEUART_INV */
-#define _LEUART_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
-#define LEUART_CTRL_INV_DEFAULT (_LEUART_CTRL_INV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CTRL */
-#define LEUART_CTRL_ERRSDMA (0x1UL << 6) /**< Clear RX DMA on Error */
-#define _LEUART_CTRL_ERRSDMA_SHIFT 6 /**< Shift value for LEUART_ERRSDMA */
-#define _LEUART_CTRL_ERRSDMA_MASK 0x40UL /**< Bit mask for LEUART_ERRSDMA */
-#define _LEUART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
-#define LEUART_CTRL_ERRSDMA_DEFAULT (_LEUART_CTRL_ERRSDMA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CTRL */
-#define LEUART_CTRL_LOOPBK (0x1UL << 7) /**< Loopback Enable */
-#define _LEUART_CTRL_LOOPBK_SHIFT 7 /**< Shift value for LEUART_LOOPBK */
-#define _LEUART_CTRL_LOOPBK_MASK 0x80UL /**< Bit mask for LEUART_LOOPBK */
-#define _LEUART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
-#define LEUART_CTRL_LOOPBK_DEFAULT (_LEUART_CTRL_LOOPBK_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CTRL */
-#define LEUART_CTRL_SFUBRX (0x1UL << 8) /**< Start-Frame UnBlock RX */
-#define _LEUART_CTRL_SFUBRX_SHIFT 8 /**< Shift value for LEUART_SFUBRX */
-#define _LEUART_CTRL_SFUBRX_MASK 0x100UL /**< Bit mask for LEUART_SFUBRX */
-#define _LEUART_CTRL_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
-#define LEUART_CTRL_SFUBRX_DEFAULT (_LEUART_CTRL_SFUBRX_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_CTRL */
-#define LEUART_CTRL_MPM (0x1UL << 9) /**< Multi-Processor Mode */
-#define _LEUART_CTRL_MPM_SHIFT 9 /**< Shift value for LEUART_MPM */
-#define _LEUART_CTRL_MPM_MASK 0x200UL /**< Bit mask for LEUART_MPM */
-#define _LEUART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
-#define LEUART_CTRL_MPM_DEFAULT (_LEUART_CTRL_MPM_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_CTRL */
-#define LEUART_CTRL_MPAB (0x1UL << 10) /**< Multi-Processor Address-Bit */
-#define _LEUART_CTRL_MPAB_SHIFT 10 /**< Shift value for LEUART_MPAB */
-#define _LEUART_CTRL_MPAB_MASK 0x400UL /**< Bit mask for LEUART_MPAB */
-#define _LEUART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
-#define LEUART_CTRL_MPAB_DEFAULT (_LEUART_CTRL_MPAB_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_CTRL */
-#define LEUART_CTRL_BIT8DV (0x1UL << 11) /**< Bit 8 Default Value */
-#define _LEUART_CTRL_BIT8DV_SHIFT 11 /**< Shift value for LEUART_BIT8DV */
-#define _LEUART_CTRL_BIT8DV_MASK 0x800UL /**< Bit mask for LEUART_BIT8DV */
-#define _LEUART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
-#define LEUART_CTRL_BIT8DV_DEFAULT (_LEUART_CTRL_BIT8DV_DEFAULT << 11) /**< Shifted mode DEFAULT for LEUART_CTRL */
-#define LEUART_CTRL_RXDMAWU (0x1UL << 12) /**< RX DMA Wakeup */
-#define _LEUART_CTRL_RXDMAWU_SHIFT 12 /**< Shift value for LEUART_RXDMAWU */
-#define _LEUART_CTRL_RXDMAWU_MASK 0x1000UL /**< Bit mask for LEUART_RXDMAWU */
-#define _LEUART_CTRL_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
-#define LEUART_CTRL_RXDMAWU_DEFAULT (_LEUART_CTRL_RXDMAWU_DEFAULT << 12) /**< Shifted mode DEFAULT for LEUART_CTRL */
-#define LEUART_CTRL_TXDMAWU (0x1UL << 13) /**< TX DMA Wakeup */
-#define _LEUART_CTRL_TXDMAWU_SHIFT 13 /**< Shift value for LEUART_TXDMAWU */
-#define _LEUART_CTRL_TXDMAWU_MASK 0x2000UL /**< Bit mask for LEUART_TXDMAWU */
-#define _LEUART_CTRL_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
-#define LEUART_CTRL_TXDMAWU_DEFAULT (_LEUART_CTRL_TXDMAWU_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_CTRL */
-#define _LEUART_CTRL_TXDELAY_SHIFT 14 /**< Shift value for LEUART_TXDELAY */
-#define _LEUART_CTRL_TXDELAY_MASK 0xC000UL /**< Bit mask for LEUART_TXDELAY */
-#define _LEUART_CTRL_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
-#define _LEUART_CTRL_TXDELAY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */
-#define _LEUART_CTRL_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for LEUART_CTRL */
-#define _LEUART_CTRL_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for LEUART_CTRL */
-#define _LEUART_CTRL_TXDELAY_TRIPLE 0x00000003UL /**< Mode TRIPLE for LEUART_CTRL */
-#define LEUART_CTRL_TXDELAY_DEFAULT (_LEUART_CTRL_TXDELAY_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_CTRL */
-#define LEUART_CTRL_TXDELAY_NONE (_LEUART_CTRL_TXDELAY_NONE << 14) /**< Shifted mode NONE for LEUART_CTRL */
-#define LEUART_CTRL_TXDELAY_SINGLE (_LEUART_CTRL_TXDELAY_SINGLE << 14) /**< Shifted mode SINGLE for LEUART_CTRL */
-#define LEUART_CTRL_TXDELAY_DOUBLE (_LEUART_CTRL_TXDELAY_DOUBLE << 14) /**< Shifted mode DOUBLE for LEUART_CTRL */
-#define LEUART_CTRL_TXDELAY_TRIPLE (_LEUART_CTRL_TXDELAY_TRIPLE << 14) /**< Shifted mode TRIPLE for LEUART_CTRL */
-
-/* Bit fields for LEUART CMD */
-#define _LEUART_CMD_RESETVALUE 0x00000000UL /**< Default value for LEUART_CMD */
-#define _LEUART_CMD_MASK 0x000000FFUL /**< Mask for LEUART_CMD */
-#define LEUART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */
-#define _LEUART_CMD_RXEN_SHIFT 0 /**< Shift value for LEUART_RXEN */
-#define _LEUART_CMD_RXEN_MASK 0x1UL /**< Bit mask for LEUART_RXEN */
-#define _LEUART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
-#define LEUART_CMD_RXEN_DEFAULT (_LEUART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CMD */
-#define LEUART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */
-#define _LEUART_CMD_RXDIS_SHIFT 1 /**< Shift value for LEUART_RXDIS */
-#define _LEUART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for LEUART_RXDIS */
-#define _LEUART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
-#define LEUART_CMD_RXDIS_DEFAULT (_LEUART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CMD */
-#define LEUART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */
-#define _LEUART_CMD_TXEN_SHIFT 2 /**< Shift value for LEUART_TXEN */
-#define _LEUART_CMD_TXEN_MASK 0x4UL /**< Bit mask for LEUART_TXEN */
-#define _LEUART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
-#define LEUART_CMD_TXEN_DEFAULT (_LEUART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CMD */
-#define LEUART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */
-#define _LEUART_CMD_TXDIS_SHIFT 3 /**< Shift value for LEUART_TXDIS */
-#define _LEUART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for LEUART_TXDIS */
-#define _LEUART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
-#define LEUART_CMD_TXDIS_DEFAULT (_LEUART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CMD */
-#define LEUART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */
-#define _LEUART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for LEUART_RXBLOCKEN */
-#define _LEUART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for LEUART_RXBLOCKEN */
-#define _LEUART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
-#define LEUART_CMD_RXBLOCKEN_DEFAULT (_LEUART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CMD */
-#define LEUART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */
-#define _LEUART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for LEUART_RXBLOCKDIS */
-#define _LEUART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for LEUART_RXBLOCKDIS */
-#define _LEUART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
-#define LEUART_CMD_RXBLOCKDIS_DEFAULT (_LEUART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CMD */
-#define LEUART_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */
-#define _LEUART_CMD_CLEARTX_SHIFT 6 /**< Shift value for LEUART_CLEARTX */
-#define _LEUART_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for LEUART_CLEARTX */
-#define _LEUART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
-#define LEUART_CMD_CLEARTX_DEFAULT (_LEUART_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CMD */
-#define LEUART_CMD_CLEARRX (0x1UL << 7) /**< Clear RX */
-#define _LEUART_CMD_CLEARRX_SHIFT 7 /**< Shift value for LEUART_CLEARRX */
-#define _LEUART_CMD_CLEARRX_MASK 0x80UL /**< Bit mask for LEUART_CLEARRX */
-#define _LEUART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
-#define LEUART_CMD_CLEARRX_DEFAULT (_LEUART_CMD_CLEARRX_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CMD */
-
-/* Bit fields for LEUART STATUS */
-#define _LEUART_STATUS_RESETVALUE 0x00000050UL /**< Default value for LEUART_STATUS */
-#define _LEUART_STATUS_MASK 0x0000007FUL /**< Mask for LEUART_STATUS */
-#define LEUART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */
-#define _LEUART_STATUS_RXENS_SHIFT 0 /**< Shift value for LEUART_RXENS */
-#define _LEUART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for LEUART_RXENS */
-#define _LEUART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
-#define LEUART_STATUS_RXENS_DEFAULT (_LEUART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STATUS */
-#define LEUART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */
-#define _LEUART_STATUS_TXENS_SHIFT 1 /**< Shift value for LEUART_TXENS */
-#define _LEUART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for LEUART_TXENS */
-#define _LEUART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
-#define LEUART_STATUS_TXENS_DEFAULT (_LEUART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_STATUS */
-#define LEUART_STATUS_RXBLOCK (0x1UL << 2) /**< Block Incoming Data */
-#define _LEUART_STATUS_RXBLOCK_SHIFT 2 /**< Shift value for LEUART_RXBLOCK */
-#define _LEUART_STATUS_RXBLOCK_MASK 0x4UL /**< Bit mask for LEUART_RXBLOCK */
-#define _LEUART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
-#define LEUART_STATUS_RXBLOCK_DEFAULT (_LEUART_STATUS_RXBLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_STATUS */
-#define LEUART_STATUS_TXC (0x1UL << 3) /**< TX Complete */
-#define _LEUART_STATUS_TXC_SHIFT 3 /**< Shift value for LEUART_TXC */
-#define _LEUART_STATUS_TXC_MASK 0x8UL /**< Bit mask for LEUART_TXC */
-#define _LEUART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
-#define LEUART_STATUS_TXC_DEFAULT (_LEUART_STATUS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_STATUS */
-#define LEUART_STATUS_TXBL (0x1UL << 4) /**< TX Buffer Level */
-#define _LEUART_STATUS_TXBL_SHIFT 4 /**< Shift value for LEUART_TXBL */
-#define _LEUART_STATUS_TXBL_MASK 0x10UL /**< Bit mask for LEUART_TXBL */
-#define _LEUART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */
-#define LEUART_STATUS_TXBL_DEFAULT (_LEUART_STATUS_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_STATUS */
-#define LEUART_STATUS_RXDATAV (0x1UL << 5) /**< RX Data Valid */
-#define _LEUART_STATUS_RXDATAV_SHIFT 5 /**< Shift value for LEUART_RXDATAV */
-#define _LEUART_STATUS_RXDATAV_MASK 0x20UL /**< Bit mask for LEUART_RXDATAV */
-#define _LEUART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
-#define LEUART_STATUS_RXDATAV_DEFAULT (_LEUART_STATUS_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_STATUS */
-#define LEUART_STATUS_TXIDLE (0x1UL << 6) /**< TX Idle */
-#define _LEUART_STATUS_TXIDLE_SHIFT 6 /**< Shift value for LEUART_TXIDLE */
-#define _LEUART_STATUS_TXIDLE_MASK 0x40UL /**< Bit mask for LEUART_TXIDLE */
-#define _LEUART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */
-#define LEUART_STATUS_TXIDLE_DEFAULT (_LEUART_STATUS_TXIDLE_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_STATUS */
-
-/* Bit fields for LEUART CLKDIV */
-#define _LEUART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for LEUART_CLKDIV */
-#define _LEUART_CLKDIV_MASK 0x0001FFF8UL /**< Mask for LEUART_CLKDIV */
-#define _LEUART_CLKDIV_DIV_SHIFT 3 /**< Shift value for LEUART_DIV */
-#define _LEUART_CLKDIV_DIV_MASK 0x1FFF8UL /**< Bit mask for LEUART_DIV */
-#define _LEUART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CLKDIV */
-#define LEUART_CLKDIV_DIV_DEFAULT (_LEUART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CLKDIV */
-
-/* Bit fields for LEUART STARTFRAME */
-#define _LEUART_STARTFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_STARTFRAME */
-#define _LEUART_STARTFRAME_MASK 0x000001FFUL /**< Mask for LEUART_STARTFRAME */
-#define _LEUART_STARTFRAME_STARTFRAME_SHIFT 0 /**< Shift value for LEUART_STARTFRAME */
-#define _LEUART_STARTFRAME_STARTFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_STARTFRAME */
-#define _LEUART_STARTFRAME_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STARTFRAME */
-#define LEUART_STARTFRAME_STARTFRAME_DEFAULT (_LEUART_STARTFRAME_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STARTFRAME */
-
-/* Bit fields for LEUART SIGFRAME */
-#define _LEUART_SIGFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_SIGFRAME */
-#define _LEUART_SIGFRAME_MASK 0x000001FFUL /**< Mask for LEUART_SIGFRAME */
-#define _LEUART_SIGFRAME_SIGFRAME_SHIFT 0 /**< Shift value for LEUART_SIGFRAME */
-#define _LEUART_SIGFRAME_SIGFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_SIGFRAME */
-#define _LEUART_SIGFRAME_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SIGFRAME */
-#define LEUART_SIGFRAME_SIGFRAME_DEFAULT (_LEUART_SIGFRAME_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SIGFRAME */
-
-/* Bit fields for LEUART RXDATAX */
-#define _LEUART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAX */
-#define _LEUART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAX */
-#define _LEUART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */
-#define _LEUART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATA */
-#define _LEUART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */
-#define LEUART_RXDATAX_RXDATA_DEFAULT (_LEUART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAX */
-#define LEUART_RXDATAX_PERR (0x1UL << 14) /**< Receive Data Parity Error */
-#define _LEUART_RXDATAX_PERR_SHIFT 14 /**< Shift value for LEUART_PERR */
-#define _LEUART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for LEUART_PERR */
-#define _LEUART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */
-#define LEUART_RXDATAX_PERR_DEFAULT (_LEUART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAX */
-#define LEUART_RXDATAX_FERR (0x1UL << 15) /**< Receive Data Framing Error */
-#define _LEUART_RXDATAX_FERR_SHIFT 15 /**< Shift value for LEUART_FERR */
-#define _LEUART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for LEUART_FERR */
-#define _LEUART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */
-#define LEUART_RXDATAX_FERR_DEFAULT (_LEUART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAX */
-
-/* Bit fields for LEUART RXDATA */
-#define _LEUART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATA */
-#define _LEUART_RXDATA_MASK 0x000000FFUL /**< Mask for LEUART_RXDATA */
-#define _LEUART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */
-#define _LEUART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for LEUART_RXDATA */
-#define _LEUART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATA */
-#define LEUART_RXDATA_RXDATA_DEFAULT (_LEUART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATA */
-
-/* Bit fields for LEUART RXDATAXP */
-#define _LEUART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAXP */
-#define _LEUART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAXP */
-#define _LEUART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for LEUART_RXDATAP */
-#define _LEUART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATAP */
-#define _LEUART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */
-#define LEUART_RXDATAXP_RXDATAP_DEFAULT (_LEUART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */
-#define LEUART_RXDATAXP_PERRP (0x1UL << 14) /**< Receive Data Parity Error Peek */
-#define _LEUART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for LEUART_PERRP */
-#define _LEUART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for LEUART_PERRP */
-#define _LEUART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */
-#define LEUART_RXDATAXP_PERRP_DEFAULT (_LEUART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */
-#define LEUART_RXDATAXP_FERRP (0x1UL << 15) /**< Receive Data Framing Error Peek */
-#define _LEUART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for LEUART_FERRP */
-#define _LEUART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for LEUART_FERRP */
-#define _LEUART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */
-#define LEUART_RXDATAXP_FERRP_DEFAULT (_LEUART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */
-
-/* Bit fields for LEUART TXDATAX */
-#define _LEUART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATAX */
-#define _LEUART_TXDATAX_MASK 0x0000E1FFUL /**< Mask for LEUART_TXDATAX */
-#define _LEUART_TXDATAX_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */
-#define _LEUART_TXDATAX_TXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_TXDATA */
-#define _LEUART_TXDATAX_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
-#define LEUART_TXDATAX_TXDATA_DEFAULT (_LEUART_TXDATAX_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
-#define LEUART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data as Break */
-#define _LEUART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for LEUART_TXBREAK */
-#define _LEUART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for LEUART_TXBREAK */
-#define _LEUART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
-#define LEUART_TXDATAX_TXBREAK_DEFAULT (_LEUART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
-#define LEUART_TXDATAX_TXDISAT (0x1UL << 14) /**< Disable TX After Transmission */
-#define _LEUART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for LEUART_TXDISAT */
-#define _LEUART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for LEUART_TXDISAT */
-#define _LEUART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
-#define LEUART_TXDATAX_TXDISAT_DEFAULT (_LEUART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
-#define LEUART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */
-#define _LEUART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for LEUART_RXENAT */
-#define _LEUART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for LEUART_RXENAT */
-#define _LEUART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
-#define LEUART_TXDATAX_RXENAT_DEFAULT (_LEUART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
-
-/* Bit fields for LEUART TXDATA */
-#define _LEUART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATA */
-#define _LEUART_TXDATA_MASK 0x000000FFUL /**< Mask for LEUART_TXDATA */
-#define _LEUART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */
-#define _LEUART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for LEUART_TXDATA */
-#define _LEUART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATA */
-#define LEUART_TXDATA_TXDATA_DEFAULT (_LEUART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATA */
-
-/* Bit fields for LEUART IF */
-#define _LEUART_IF_RESETVALUE 0x00000002UL /**< Default value for LEUART_IF */
-#define _LEUART_IF_MASK 0x000007FFUL /**< Mask for LEUART_IF */
-#define LEUART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */
-#define _LEUART_IF_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
-#define _LEUART_IF_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
-#define _LEUART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
-#define LEUART_IF_TXC_DEFAULT (_LEUART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IF */
-#define LEUART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */
-#define _LEUART_IF_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */
-#define _LEUART_IF_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */
-#define _LEUART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_IF */
-#define LEUART_IF_TXBL_DEFAULT (_LEUART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IF */
-#define LEUART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */
-#define _LEUART_IF_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */
-#define _LEUART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */
-#define _LEUART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
-#define LEUART_IF_RXDATAV_DEFAULT (_LEUART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IF */
-#define LEUART_IF_RXOF (0x1UL << 3) /**< RX Overflow Interrupt Flag */
-#define _LEUART_IF_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
-#define _LEUART_IF_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
-#define _LEUART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
-#define LEUART_IF_RXOF_DEFAULT (_LEUART_IF_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IF */
-#define LEUART_IF_RXUF (0x1UL << 4) /**< RX Underflow Interrupt Flag */
-#define _LEUART_IF_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
-#define _LEUART_IF_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
-#define _LEUART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
-#define LEUART_IF_RXUF_DEFAULT (_LEUART_IF_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IF */
-#define LEUART_IF_TXOF (0x1UL << 5) /**< TX Overflow Interrupt Flag */
-#define _LEUART_IF_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
-#define _LEUART_IF_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
-#define _LEUART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
-#define LEUART_IF_TXOF_DEFAULT (_LEUART_IF_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IF */
-#define LEUART_IF_PERR (0x1UL << 6) /**< Parity Error Interrupt Flag */
-#define _LEUART_IF_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
-#define _LEUART_IF_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
-#define _LEUART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
-#define LEUART_IF_PERR_DEFAULT (_LEUART_IF_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IF */
-#define LEUART_IF_FERR (0x1UL << 7) /**< Framing Error Interrupt Flag */
-#define _LEUART_IF_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
-#define _LEUART_IF_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
-#define _LEUART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
-#define LEUART_IF_FERR_DEFAULT (_LEUART_IF_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IF */
-#define LEUART_IF_MPAF (0x1UL << 8) /**< Multi-Processor Address Frame Interrupt Flag */
-#define _LEUART_IF_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
-#define _LEUART_IF_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
-#define _LEUART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
-#define LEUART_IF_MPAF_DEFAULT (_LEUART_IF_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IF */
-#define LEUART_IF_STARTF (0x1UL << 9) /**< Start Frame Interrupt Flag */
-#define _LEUART_IF_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
-#define _LEUART_IF_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
-#define _LEUART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
-#define LEUART_IF_STARTF_DEFAULT (_LEUART_IF_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IF */
-#define LEUART_IF_SIGF (0x1UL << 10) /**< Signal Frame Interrupt Flag */
-#define _LEUART_IF_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
-#define _LEUART_IF_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
-#define _LEUART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
-#define LEUART_IF_SIGF_DEFAULT (_LEUART_IF_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IF */
-
-/* Bit fields for LEUART IFS */
-#define _LEUART_IFS_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFS */
-#define _LEUART_IFS_MASK 0x000007F9UL /**< Mask for LEUART_IFS */
-#define LEUART_IFS_TXC (0x1UL << 0) /**< Set TXC Interrupt Flag */
-#define _LEUART_IFS_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
-#define _LEUART_IFS_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
-#define _LEUART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
-#define LEUART_IFS_TXC_DEFAULT (_LEUART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFS */
-#define LEUART_IFS_RXOF (0x1UL << 3) /**< Set RXOF Interrupt Flag */
-#define _LEUART_IFS_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
-#define _LEUART_IFS_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
-#define _LEUART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
-#define LEUART_IFS_RXOF_DEFAULT (_LEUART_IFS_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFS */
-#define LEUART_IFS_RXUF (0x1UL << 4) /**< Set RXUF Interrupt Flag */
-#define _LEUART_IFS_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
-#define _LEUART_IFS_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
-#define _LEUART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
-#define LEUART_IFS_RXUF_DEFAULT (_LEUART_IFS_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFS */
-#define LEUART_IFS_TXOF (0x1UL << 5) /**< Set TXOF Interrupt Flag */
-#define _LEUART_IFS_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
-#define _LEUART_IFS_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
-#define _LEUART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
-#define LEUART_IFS_TXOF_DEFAULT (_LEUART_IFS_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFS */
-#define LEUART_IFS_PERR (0x1UL << 6) /**< Set PERR Interrupt Flag */
-#define _LEUART_IFS_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
-#define _LEUART_IFS_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
-#define _LEUART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
-#define LEUART_IFS_PERR_DEFAULT (_LEUART_IFS_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFS */
-#define LEUART_IFS_FERR (0x1UL << 7) /**< Set FERR Interrupt Flag */
-#define _LEUART_IFS_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
-#define _LEUART_IFS_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
-#define _LEUART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
-#define LEUART_IFS_FERR_DEFAULT (_LEUART_IFS_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFS */
-#define LEUART_IFS_MPAF (0x1UL << 8) /**< Set MPAF Interrupt Flag */
-#define _LEUART_IFS_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
-#define _LEUART_IFS_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
-#define _LEUART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
-#define LEUART_IFS_MPAF_DEFAULT (_LEUART_IFS_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFS */
-#define LEUART_IFS_STARTF (0x1UL << 9) /**< Set STARTF Interrupt Flag */
-#define _LEUART_IFS_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
-#define _LEUART_IFS_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
-#define _LEUART_IFS_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
-#define LEUART_IFS_STARTF_DEFAULT (_LEUART_IFS_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFS */
-#define LEUART_IFS_SIGF (0x1UL << 10) /**< Set SIGF Interrupt Flag */
-#define _LEUART_IFS_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
-#define _LEUART_IFS_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
-#define _LEUART_IFS_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
-#define LEUART_IFS_SIGF_DEFAULT (_LEUART_IFS_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFS */
-
-/* Bit fields for LEUART IFC */
-#define _LEUART_IFC_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFC */
-#define _LEUART_IFC_MASK 0x000007F9UL /**< Mask for LEUART_IFC */
-#define LEUART_IFC_TXC (0x1UL << 0) /**< Clear TXC Interrupt Flag */
-#define _LEUART_IFC_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
-#define _LEUART_IFC_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
-#define _LEUART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
-#define LEUART_IFC_TXC_DEFAULT (_LEUART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFC */
-#define LEUART_IFC_RXOF (0x1UL << 3) /**< Clear RXOF Interrupt Flag */
-#define _LEUART_IFC_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
-#define _LEUART_IFC_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
-#define _LEUART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
-#define LEUART_IFC_RXOF_DEFAULT (_LEUART_IFC_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFC */
-#define LEUART_IFC_RXUF (0x1UL << 4) /**< Clear RXUF Interrupt Flag */
-#define _LEUART_IFC_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
-#define _LEUART_IFC_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
-#define _LEUART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
-#define LEUART_IFC_RXUF_DEFAULT (_LEUART_IFC_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFC */
-#define LEUART_IFC_TXOF (0x1UL << 5) /**< Clear TXOF Interrupt Flag */
-#define _LEUART_IFC_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
-#define _LEUART_IFC_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
-#define _LEUART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
-#define LEUART_IFC_TXOF_DEFAULT (_LEUART_IFC_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFC */
-#define LEUART_IFC_PERR (0x1UL << 6) /**< Clear PERR Interrupt Flag */
-#define _LEUART_IFC_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
-#define _LEUART_IFC_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
-#define _LEUART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
-#define LEUART_IFC_PERR_DEFAULT (_LEUART_IFC_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFC */
-#define LEUART_IFC_FERR (0x1UL << 7) /**< Clear FERR Interrupt Flag */
-#define _LEUART_IFC_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
-#define _LEUART_IFC_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
-#define _LEUART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
-#define LEUART_IFC_FERR_DEFAULT (_LEUART_IFC_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFC */
-#define LEUART_IFC_MPAF (0x1UL << 8) /**< Clear MPAF Interrupt Flag */
-#define _LEUART_IFC_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
-#define _LEUART_IFC_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
-#define _LEUART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
-#define LEUART_IFC_MPAF_DEFAULT (_LEUART_IFC_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFC */
-#define LEUART_IFC_STARTF (0x1UL << 9) /**< Clear STARTF Interrupt Flag */
-#define _LEUART_IFC_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
-#define _LEUART_IFC_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
-#define _LEUART_IFC_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
-#define LEUART_IFC_STARTF_DEFAULT (_LEUART_IFC_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFC */
-#define LEUART_IFC_SIGF (0x1UL << 10) /**< Clear SIGF Interrupt Flag */
-#define _LEUART_IFC_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
-#define _LEUART_IFC_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
-#define _LEUART_IFC_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
-#define LEUART_IFC_SIGF_DEFAULT (_LEUART_IFC_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFC */
-
-/* Bit fields for LEUART IEN */
-#define _LEUART_IEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_IEN */
-#define _LEUART_IEN_MASK 0x000007FFUL /**< Mask for LEUART_IEN */
-#define LEUART_IEN_TXC (0x1UL << 0) /**< TXC Interrupt Enable */
-#define _LEUART_IEN_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
-#define _LEUART_IEN_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
-#define _LEUART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
-#define LEUART_IEN_TXC_DEFAULT (_LEUART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IEN */
-#define LEUART_IEN_TXBL (0x1UL << 1) /**< TXBL Interrupt Enable */
-#define _LEUART_IEN_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */
-#define _LEUART_IEN_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */
-#define _LEUART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
-#define LEUART_IEN_TXBL_DEFAULT (_LEUART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IEN */
-#define LEUART_IEN_RXDATAV (0x1UL << 2) /**< RXDATAV Interrupt Enable */
-#define _LEUART_IEN_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */
-#define _LEUART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */
-#define _LEUART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
-#define LEUART_IEN_RXDATAV_DEFAULT (_LEUART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IEN */
-#define LEUART_IEN_RXOF (0x1UL << 3) /**< RXOF Interrupt Enable */
-#define _LEUART_IEN_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
-#define _LEUART_IEN_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
-#define _LEUART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
-#define LEUART_IEN_RXOF_DEFAULT (_LEUART_IEN_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IEN */
-#define LEUART_IEN_RXUF (0x1UL << 4) /**< RXUF Interrupt Enable */
-#define _LEUART_IEN_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
-#define _LEUART_IEN_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
-#define _LEUART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
-#define LEUART_IEN_RXUF_DEFAULT (_LEUART_IEN_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IEN */
-#define LEUART_IEN_TXOF (0x1UL << 5) /**< TXOF Interrupt Enable */
-#define _LEUART_IEN_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
-#define _LEUART_IEN_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
-#define _LEUART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
-#define LEUART_IEN_TXOF_DEFAULT (_LEUART_IEN_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IEN */
-#define LEUART_IEN_PERR (0x1UL << 6) /**< PERR Interrupt Enable */
-#define _LEUART_IEN_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
-#define _LEUART_IEN_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
-#define _LEUART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
-#define LEUART_IEN_PERR_DEFAULT (_LEUART_IEN_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IEN */
-#define LEUART_IEN_FERR (0x1UL << 7) /**< FERR Interrupt Enable */
-#define _LEUART_IEN_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
-#define _LEUART_IEN_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
-#define _LEUART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
-#define LEUART_IEN_FERR_DEFAULT (_LEUART_IEN_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IEN */
-#define LEUART_IEN_MPAF (0x1UL << 8) /**< MPAF Interrupt Enable */
-#define _LEUART_IEN_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
-#define _LEUART_IEN_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
-#define _LEUART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
-#define LEUART_IEN_MPAF_DEFAULT (_LEUART_IEN_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IEN */
-#define LEUART_IEN_STARTF (0x1UL << 9) /**< STARTF Interrupt Enable */
-#define _LEUART_IEN_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
-#define _LEUART_IEN_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
-#define _LEUART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
-#define LEUART_IEN_STARTF_DEFAULT (_LEUART_IEN_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IEN */
-#define LEUART_IEN_SIGF (0x1UL << 10) /**< SIGF Interrupt Enable */
-#define _LEUART_IEN_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
-#define _LEUART_IEN_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
-#define _LEUART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
-#define LEUART_IEN_SIGF_DEFAULT (_LEUART_IEN_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IEN */
-
-/* Bit fields for LEUART PULSECTRL */
-#define _LEUART_PULSECTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_PULSECTRL */
-#define _LEUART_PULSECTRL_MASK 0x0000003FUL /**< Mask for LEUART_PULSECTRL */
-#define _LEUART_PULSECTRL_PULSEW_SHIFT 0 /**< Shift value for LEUART_PULSEW */
-#define _LEUART_PULSECTRL_PULSEW_MASK 0xFUL /**< Bit mask for LEUART_PULSEW */
-#define _LEUART_PULSECTRL_PULSEW_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */
-#define LEUART_PULSECTRL_PULSEW_DEFAULT (_LEUART_PULSECTRL_PULSEW_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */
-#define LEUART_PULSECTRL_PULSEEN (0x1UL << 4) /**< Pulse Generator/Extender Enable */
-#define _LEUART_PULSECTRL_PULSEEN_SHIFT 4 /**< Shift value for LEUART_PULSEEN */
-#define _LEUART_PULSECTRL_PULSEEN_MASK 0x10UL /**< Bit mask for LEUART_PULSEEN */
-#define _LEUART_PULSECTRL_PULSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */
-#define LEUART_PULSECTRL_PULSEEN_DEFAULT (_LEUART_PULSECTRL_PULSEEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */
-#define LEUART_PULSECTRL_PULSEFILT (0x1UL << 5) /**< Pulse Filter */
-#define _LEUART_PULSECTRL_PULSEFILT_SHIFT 5 /**< Shift value for LEUART_PULSEFILT */
-#define _LEUART_PULSECTRL_PULSEFILT_MASK 0x20UL /**< Bit mask for LEUART_PULSEFILT */
-#define _LEUART_PULSECTRL_PULSEFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */
-#define LEUART_PULSECTRL_PULSEFILT_DEFAULT (_LEUART_PULSECTRL_PULSEFILT_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */
-
-/* Bit fields for LEUART FREEZE */
-#define _LEUART_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LEUART_FREEZE */
-#define _LEUART_FREEZE_MASK 0x00000001UL /**< Mask for LEUART_FREEZE */
-#define LEUART_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
-#define _LEUART_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LEUART_REGFREEZE */
-#define _LEUART_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LEUART_REGFREEZE */
-#define _LEUART_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_FREEZE */
-#define _LEUART_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LEUART_FREEZE */
-#define _LEUART_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LEUART_FREEZE */
-#define LEUART_FREEZE_REGFREEZE_DEFAULT (_LEUART_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_FREEZE */
-#define LEUART_FREEZE_REGFREEZE_UPDATE (_LEUART_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for LEUART_FREEZE */
-#define LEUART_FREEZE_REGFREEZE_FREEZE (_LEUART_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for LEUART_FREEZE */
-
-/* Bit fields for LEUART SYNCBUSY */
-#define _LEUART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LEUART_SYNCBUSY */
-#define _LEUART_SYNCBUSY_MASK 0x000000FFUL /**< Mask for LEUART_SYNCBUSY */
-#define LEUART_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
-#define _LEUART_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LEUART_CTRL */
-#define _LEUART_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LEUART_CTRL */
-#define _LEUART_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
-#define LEUART_SYNCBUSY_CTRL_DEFAULT (_LEUART_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
-#define LEUART_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */
-#define _LEUART_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LEUART_CMD */
-#define _LEUART_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LEUART_CMD */
-#define _LEUART_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
-#define LEUART_SYNCBUSY_CMD_DEFAULT (_LEUART_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
-#define LEUART_SYNCBUSY_CLKDIV (0x1UL << 2) /**< CLKDIV Register Busy */
-#define _LEUART_SYNCBUSY_CLKDIV_SHIFT 2 /**< Shift value for LEUART_CLKDIV */
-#define _LEUART_SYNCBUSY_CLKDIV_MASK 0x4UL /**< Bit mask for LEUART_CLKDIV */
-#define _LEUART_SYNCBUSY_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
-#define LEUART_SYNCBUSY_CLKDIV_DEFAULT (_LEUART_SYNCBUSY_CLKDIV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
-#define LEUART_SYNCBUSY_STARTFRAME (0x1UL << 3) /**< STARTFRAME Register Busy */
-#define _LEUART_SYNCBUSY_STARTFRAME_SHIFT 3 /**< Shift value for LEUART_STARTFRAME */
-#define _LEUART_SYNCBUSY_STARTFRAME_MASK 0x8UL /**< Bit mask for LEUART_STARTFRAME */
-#define _LEUART_SYNCBUSY_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
-#define LEUART_SYNCBUSY_STARTFRAME_DEFAULT (_LEUART_SYNCBUSY_STARTFRAME_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
-#define LEUART_SYNCBUSY_SIGFRAME (0x1UL << 4) /**< SIGFRAME Register Busy */
-#define _LEUART_SYNCBUSY_SIGFRAME_SHIFT 4 /**< Shift value for LEUART_SIGFRAME */
-#define _LEUART_SYNCBUSY_SIGFRAME_MASK 0x10UL /**< Bit mask for LEUART_SIGFRAME */
-#define _LEUART_SYNCBUSY_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
-#define LEUART_SYNCBUSY_SIGFRAME_DEFAULT (_LEUART_SYNCBUSY_SIGFRAME_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
-#define LEUART_SYNCBUSY_TXDATAX (0x1UL << 5) /**< TXDATAX Register Busy */
-#define _LEUART_SYNCBUSY_TXDATAX_SHIFT 5 /**< Shift value for LEUART_TXDATAX */
-#define _LEUART_SYNCBUSY_TXDATAX_MASK 0x20UL /**< Bit mask for LEUART_TXDATAX */
-#define _LEUART_SYNCBUSY_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
-#define LEUART_SYNCBUSY_TXDATAX_DEFAULT (_LEUART_SYNCBUSY_TXDATAX_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
-#define LEUART_SYNCBUSY_TXDATA (0x1UL << 6) /**< TXDATA Register Busy */
-#define _LEUART_SYNCBUSY_TXDATA_SHIFT 6 /**< Shift value for LEUART_TXDATA */
-#define _LEUART_SYNCBUSY_TXDATA_MASK 0x40UL /**< Bit mask for LEUART_TXDATA */
-#define _LEUART_SYNCBUSY_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
-#define LEUART_SYNCBUSY_TXDATA_DEFAULT (_LEUART_SYNCBUSY_TXDATA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
-#define LEUART_SYNCBUSY_PULSECTRL (0x1UL << 7) /**< PULSECTRL Register Busy */
-#define _LEUART_SYNCBUSY_PULSECTRL_SHIFT 7 /**< Shift value for LEUART_PULSECTRL */
-#define _LEUART_SYNCBUSY_PULSECTRL_MASK 0x80UL /**< Bit mask for LEUART_PULSECTRL */
-#define _LEUART_SYNCBUSY_PULSECTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
-#define LEUART_SYNCBUSY_PULSECTRL_DEFAULT (_LEUART_SYNCBUSY_PULSECTRL_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
-
-/* Bit fields for LEUART ROUTEPEN */
-#define _LEUART_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTEPEN */
-#define _LEUART_ROUTEPEN_MASK 0x00000003UL /**< Mask for LEUART_ROUTEPEN */
-#define LEUART_ROUTEPEN_RXPEN (0x1UL << 0) /**< RX Pin Enable */
-#define _LEUART_ROUTEPEN_RXPEN_SHIFT 0 /**< Shift value for LEUART_RXPEN */
-#define _LEUART_ROUTEPEN_RXPEN_MASK 0x1UL /**< Bit mask for LEUART_RXPEN */
-#define _LEUART_ROUTEPEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTEPEN */
-#define LEUART_ROUTEPEN_RXPEN_DEFAULT (_LEUART_ROUTEPEN_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTEPEN */
-#define LEUART_ROUTEPEN_TXPEN (0x1UL << 1) /**< TX Pin Enable */
-#define _LEUART_ROUTEPEN_TXPEN_SHIFT 1 /**< Shift value for LEUART_TXPEN */
-#define _LEUART_ROUTEPEN_TXPEN_MASK 0x2UL /**< Bit mask for LEUART_TXPEN */
-#define _LEUART_ROUTEPEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTEPEN */
-#define LEUART_ROUTEPEN_TXPEN_DEFAULT (_LEUART_ROUTEPEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_ROUTEPEN */
-
-/* Bit fields for LEUART ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_SHIFT 0 /**< Shift value for LEUART_RXLOC */
-#define _LEUART_ROUTELOC0_RXLOC_MASK 0x1FUL /**< Bit mask for LEUART_RXLOC */
-#define _LEUART_ROUTELOC0_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_LOC7 0x00000007UL /**< Mode LOC7 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_LOC8 0x00000008UL /**< Mode LOC8 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_LOC9 0x00000009UL /**< Mode LOC9 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_LOC16 0x00000010UL /**< Mode LOC16 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_LOC17 0x00000011UL /**< Mode LOC17 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_LOC18 0x00000012UL /**< Mode LOC18 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_LOC19 0x00000013UL /**< Mode LOC19 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_LOC20 0x00000014UL /**< Mode LOC20 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_LOC21 0x00000015UL /**< Mode LOC21 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_LOC22 0x00000016UL /**< Mode LOC22 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_LOC23 0x00000017UL /**< Mode LOC23 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_LOC24 0x00000018UL /**< Mode LOC24 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_LOC25 0x00000019UL /**< Mode LOC25 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_RXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC0 (_LEUART_ROUTELOC0_RXLOC_LOC0 << 0) /**< Shifted mode LOC0 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_DEFAULT (_LEUART_ROUTELOC0_RXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC1 (_LEUART_ROUTELOC0_RXLOC_LOC1 << 0) /**< Shifted mode LOC1 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC2 (_LEUART_ROUTELOC0_RXLOC_LOC2 << 0) /**< Shifted mode LOC2 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC3 (_LEUART_ROUTELOC0_RXLOC_LOC3 << 0) /**< Shifted mode LOC3 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC4 (_LEUART_ROUTELOC0_RXLOC_LOC4 << 0) /**< Shifted mode LOC4 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC5 (_LEUART_ROUTELOC0_RXLOC_LOC5 << 0) /**< Shifted mode LOC5 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC6 (_LEUART_ROUTELOC0_RXLOC_LOC6 << 0) /**< Shifted mode LOC6 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC7 (_LEUART_ROUTELOC0_RXLOC_LOC7 << 0) /**< Shifted mode LOC7 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC8 (_LEUART_ROUTELOC0_RXLOC_LOC8 << 0) /**< Shifted mode LOC8 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC9 (_LEUART_ROUTELOC0_RXLOC_LOC9 << 0) /**< Shifted mode LOC9 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC10 (_LEUART_ROUTELOC0_RXLOC_LOC10 << 0) /**< Shifted mode LOC10 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC11 (_LEUART_ROUTELOC0_RXLOC_LOC11 << 0) /**< Shifted mode LOC11 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC12 (_LEUART_ROUTELOC0_RXLOC_LOC12 << 0) /**< Shifted mode LOC12 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC13 (_LEUART_ROUTELOC0_RXLOC_LOC13 << 0) /**< Shifted mode LOC13 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC14 (_LEUART_ROUTELOC0_RXLOC_LOC14 << 0) /**< Shifted mode LOC14 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC15 (_LEUART_ROUTELOC0_RXLOC_LOC15 << 0) /**< Shifted mode LOC15 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC16 (_LEUART_ROUTELOC0_RXLOC_LOC16 << 0) /**< Shifted mode LOC16 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC17 (_LEUART_ROUTELOC0_RXLOC_LOC17 << 0) /**< Shifted mode LOC17 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC18 (_LEUART_ROUTELOC0_RXLOC_LOC18 << 0) /**< Shifted mode LOC18 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC19 (_LEUART_ROUTELOC0_RXLOC_LOC19 << 0) /**< Shifted mode LOC19 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC20 (_LEUART_ROUTELOC0_RXLOC_LOC20 << 0) /**< Shifted mode LOC20 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC21 (_LEUART_ROUTELOC0_RXLOC_LOC21 << 0) /**< Shifted mode LOC21 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC22 (_LEUART_ROUTELOC0_RXLOC_LOC22 << 0) /**< Shifted mode LOC22 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC23 (_LEUART_ROUTELOC0_RXLOC_LOC23 << 0) /**< Shifted mode LOC23 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC24 (_LEUART_ROUTELOC0_RXLOC_LOC24 << 0) /**< Shifted mode LOC24 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC25 (_LEUART_ROUTELOC0_RXLOC_LOC25 << 0) /**< Shifted mode LOC25 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC26 (_LEUART_ROUTELOC0_RXLOC_LOC26 << 0) /**< Shifted mode LOC26 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC27 (_LEUART_ROUTELOC0_RXLOC_LOC27 << 0) /**< Shifted mode LOC27 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC28 (_LEUART_ROUTELOC0_RXLOC_LOC28 << 0) /**< Shifted mode LOC28 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC29 (_LEUART_ROUTELOC0_RXLOC_LOC29 << 0) /**< Shifted mode LOC29 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC30 (_LEUART_ROUTELOC0_RXLOC_LOC30 << 0) /**< Shifted mode LOC30 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_RXLOC_LOC31 (_LEUART_ROUTELOC0_RXLOC_LOC31 << 0) /**< Shifted mode LOC31 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_SHIFT 8 /**< Shift value for LEUART_TXLOC */
-#define _LEUART_ROUTELOC0_TXLOC_MASK 0x1F00UL /**< Bit mask for LEUART_TXLOC */
-#define _LEUART_ROUTELOC0_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_LOC7 0x00000007UL /**< Mode LOC7 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_LOC8 0x00000008UL /**< Mode LOC8 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_LOC9 0x00000009UL /**< Mode LOC9 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_LOC16 0x00000010UL /**< Mode LOC16 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_LOC17 0x00000011UL /**< Mode LOC17 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_LOC18 0x00000012UL /**< Mode LOC18 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_LOC19 0x00000013UL /**< Mode LOC19 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_LOC20 0x00000014UL /**< Mode LOC20 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_LOC21 0x00000015UL /**< Mode LOC21 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_LOC22 0x00000016UL /**< Mode LOC22 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_LOC23 0x00000017UL /**< Mode LOC23 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_LOC24 0x00000018UL /**< Mode LOC24 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_LOC25 0x00000019UL /**< Mode LOC25 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for LEUART_ROUTELOC0 */
-#define _LEUART_ROUTELOC0_TXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC0 (_LEUART_ROUTELOC0_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_DEFAULT (_LEUART_ROUTELOC0_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC1 (_LEUART_ROUTELOC0_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC2 (_LEUART_ROUTELOC0_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC3 (_LEUART_ROUTELOC0_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC4 (_LEUART_ROUTELOC0_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC5 (_LEUART_ROUTELOC0_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC6 (_LEUART_ROUTELOC0_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC7 (_LEUART_ROUTELOC0_TXLOC_LOC7 << 8) /**< Shifted mode LOC7 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC8 (_LEUART_ROUTELOC0_TXLOC_LOC8 << 8) /**< Shifted mode LOC8 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC9 (_LEUART_ROUTELOC0_TXLOC_LOC9 << 8) /**< Shifted mode LOC9 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC10 (_LEUART_ROUTELOC0_TXLOC_LOC10 << 8) /**< Shifted mode LOC10 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC11 (_LEUART_ROUTELOC0_TXLOC_LOC11 << 8) /**< Shifted mode LOC11 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC12 (_LEUART_ROUTELOC0_TXLOC_LOC12 << 8) /**< Shifted mode LOC12 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC13 (_LEUART_ROUTELOC0_TXLOC_LOC13 << 8) /**< Shifted mode LOC13 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC14 (_LEUART_ROUTELOC0_TXLOC_LOC14 << 8) /**< Shifted mode LOC14 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC15 (_LEUART_ROUTELOC0_TXLOC_LOC15 << 8) /**< Shifted mode LOC15 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC16 (_LEUART_ROUTELOC0_TXLOC_LOC16 << 8) /**< Shifted mode LOC16 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC17 (_LEUART_ROUTELOC0_TXLOC_LOC17 << 8) /**< Shifted mode LOC17 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC18 (_LEUART_ROUTELOC0_TXLOC_LOC18 << 8) /**< Shifted mode LOC18 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC19 (_LEUART_ROUTELOC0_TXLOC_LOC19 << 8) /**< Shifted mode LOC19 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC20 (_LEUART_ROUTELOC0_TXLOC_LOC20 << 8) /**< Shifted mode LOC20 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC21 (_LEUART_ROUTELOC0_TXLOC_LOC21 << 8) /**< Shifted mode LOC21 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC22 (_LEUART_ROUTELOC0_TXLOC_LOC22 << 8) /**< Shifted mode LOC22 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC23 (_LEUART_ROUTELOC0_TXLOC_LOC23 << 8) /**< Shifted mode LOC23 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC24 (_LEUART_ROUTELOC0_TXLOC_LOC24 << 8) /**< Shifted mode LOC24 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC25 (_LEUART_ROUTELOC0_TXLOC_LOC25 << 8) /**< Shifted mode LOC25 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC26 (_LEUART_ROUTELOC0_TXLOC_LOC26 << 8) /**< Shifted mode LOC26 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC27 (_LEUART_ROUTELOC0_TXLOC_LOC27 << 8) /**< Shifted mode LOC27 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC28 (_LEUART_ROUTELOC0_TXLOC_LOC28 << 8) /**< Shifted mode LOC28 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC29 (_LEUART_ROUTELOC0_TXLOC_LOC29 << 8) /**< Shifted mode LOC29 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC30 (_LEUART_ROUTELOC0_TXLOC_LOC30 << 8) /**< Shifted mode LOC30 for LEUART_ROUTELOC0 */
-#define LEUART_ROUTELOC0_TXLOC_LOC31 (_LEUART_ROUTELOC0_TXLOC_LOC31 << 8) /**< Shifted mode LOC31 for LEUART_ROUTELOC0 */
-
-/* Bit fields for LEUART INPUT */
-#define _LEUART_INPUT_RESETVALUE 0x00000000UL /**< Default value for LEUART_INPUT */
-#define _LEUART_INPUT_MASK 0x0000002FUL /**< Mask for LEUART_INPUT */
-#define _LEUART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for LEUART_RXPRSSEL */
-#define _LEUART_INPUT_RXPRSSEL_MASK 0xFUL /**< Bit mask for LEUART_RXPRSSEL */
-#define _LEUART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */
-#define _LEUART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LEUART_INPUT */
-#define _LEUART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LEUART_INPUT */
-#define _LEUART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LEUART_INPUT */
-#define _LEUART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LEUART_INPUT */
-#define _LEUART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LEUART_INPUT */
-#define _LEUART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LEUART_INPUT */
-#define _LEUART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LEUART_INPUT */
-#define _LEUART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LEUART_INPUT */
-#define _LEUART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LEUART_INPUT */
-#define _LEUART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LEUART_INPUT */
-#define _LEUART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LEUART_INPUT */
-#define _LEUART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LEUART_INPUT */
-#define LEUART_INPUT_RXPRSSEL_DEFAULT (_LEUART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_INPUT */
-#define LEUART_INPUT_RXPRSSEL_PRSCH0 (_LEUART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for LEUART_INPUT */
-#define LEUART_INPUT_RXPRSSEL_PRSCH1 (_LEUART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for LEUART_INPUT */
-#define LEUART_INPUT_RXPRSSEL_PRSCH2 (_LEUART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for LEUART_INPUT */
-#define LEUART_INPUT_RXPRSSEL_PRSCH3 (_LEUART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for LEUART_INPUT */
-#define LEUART_INPUT_RXPRSSEL_PRSCH4 (_LEUART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for LEUART_INPUT */
-#define LEUART_INPUT_RXPRSSEL_PRSCH5 (_LEUART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for LEUART_INPUT */
-#define LEUART_INPUT_RXPRSSEL_PRSCH6 (_LEUART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for LEUART_INPUT */
-#define LEUART_INPUT_RXPRSSEL_PRSCH7 (_LEUART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for LEUART_INPUT */
-#define LEUART_INPUT_RXPRSSEL_PRSCH8 (_LEUART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for LEUART_INPUT */
-#define LEUART_INPUT_RXPRSSEL_PRSCH9 (_LEUART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for LEUART_INPUT */
-#define LEUART_INPUT_RXPRSSEL_PRSCH10 (_LEUART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for LEUART_INPUT */
-#define LEUART_INPUT_RXPRSSEL_PRSCH11 (_LEUART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for LEUART_INPUT */
-#define LEUART_INPUT_RXPRS (0x1UL << 5) /**< PRS RX Enable */
-#define _LEUART_INPUT_RXPRS_SHIFT 5 /**< Shift value for LEUART_RXPRS */
-#define _LEUART_INPUT_RXPRS_MASK 0x20UL /**< Bit mask for LEUART_RXPRS */
-#define _LEUART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */
-#define LEUART_INPUT_RXPRS_DEFAULT (_LEUART_INPUT_RXPRS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_INPUT */
-
-/** @} */
-/** @} End of group EFR32FG13P_LEUART */
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_msc.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_msc.h
deleted file mode 100644
index a7216223..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_msc.h
+++ /dev/null
@@ -1,609 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_msc.h
- * @brief EFR32FG13P_MSC register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P_MSC MSC
- * @{
- * @brief EFR32FG13P_MSC Register Declaration
- *****************************************************************************/
-/** MSC Register Declaration */
-typedef struct {
- __IOM uint32_t CTRL; /**< Memory System Control Register */
- __IOM uint32_t READCTRL; /**< Read Control Register */
- __IOM uint32_t WRITECTRL; /**< Write Control Register */
- __IOM uint32_t WRITECMD; /**< Write Command Register */
- __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */
- uint32_t RESERVED0[1]; /**< Reserved for future use **/
- __IOM uint32_t WDATA; /**< Write Data Register */
- __IM uint32_t STATUS; /**< Status Register */
-
- uint32_t RESERVED1[4]; /**< Reserved for future use **/
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- __IOM uint32_t LOCK; /**< Configuration Lock Register */
- __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */
- __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */
- __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */
-
- uint32_t RESERVED2[1]; /**< Reserved for future use **/
- __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */
-
- uint32_t RESERVED3[1]; /**< Reserved for future use **/
- __IOM uint32_t STARTUP; /**< Startup Control */
-
- uint32_t RESERVED4[5]; /**< Reserved for future use **/
- __IOM uint32_t CMD; /**< Command Register */
-
- uint32_t RESERVED5[6]; /**< Reserved for future use **/
- __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */
- __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */
- __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */
-} MSC_TypeDef; /** @} */
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_MSC
- * @{
- * @defgroup EFR32FG13P_MSC_BitFields MSC Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for MSC CTRL */
-#define _MSC_CTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_CTRL */
-#define _MSC_CTRL_MASK 0x0000001FUL /**< Mask for MSC_CTRL */
-#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */
-#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */
-#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */
-#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */
-#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */
-#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */
-#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */
-#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */
-#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */
-#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */
-#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */
-#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */
-#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */
-#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */
-#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */
-#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */
-#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */
-#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */
-#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */
-#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */
-#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */
-#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */
-#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */
-#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */
-#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */
-
-/* Bit fields for MSC READCTRL */
-#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */
-#define _MSC_READCTRL_MASK 0x13000338UL /**< Mask for MSC_READCTRL */
-#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */
-#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */
-#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */
-#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
-#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */
-#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */
-#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */
-#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */
-#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
-#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */
-#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */
-#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */
-#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */
-#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
-#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */
-#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */
-#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */
-#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */
-#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */
-#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */
-#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */
-#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */
-#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */
-#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
-#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */
-#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */
-#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */
-#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */
-#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */
-#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */
-#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */
-#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */
-#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */
-#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */
-#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */
-#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */
-#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */
-#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */
-#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */
-#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */
-#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
-#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */
-
-/* Bit fields for MSC WRITECTRL */
-#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */
-#define _MSC_WRITECTRL_MASK 0x00000003UL /**< Mask for MSC_WRITECTRL */
-#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */
-#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */
-#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */
-#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
-#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
-#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */
-#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */
-#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */
-#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
-#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
-
-/* Bit fields for MSC WRITECMD */
-#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */
-#define _MSC_WRITECMD_MASK 0x0000113FUL /**< Mask for MSC_WRITECMD */
-#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */
-#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */
-#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */
-#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
-#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */
-#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */
-#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */
-#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */
-#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
-#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */
-#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */
-#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */
-#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */
-#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
-#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */
-#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */
-#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */
-#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */
-#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
-#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */
-#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */
-#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */
-#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */
-#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
-#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */
-#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */
-#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */
-#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */
-#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
-#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */
-#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */
-#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */
-#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */
-#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
-#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */
-#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */
-#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */
-#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */
-#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
-#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */
-
-/* Bit fields for MSC ADDRB */
-#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */
-#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */
-#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */
-#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */
-#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */
-#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */
-
-/* Bit fields for MSC WDATA */
-#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */
-#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */
-#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */
-#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */
-#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */
-#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */
-
-/* Bit fields for MSC STATUS */
-#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */
-#define _MSC_STATUS_MASK 0xFF00007FUL /**< Mask for MSC_STATUS */
-#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */
-#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */
-#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */
-#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
-#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */
-#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */
-#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */
-#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */
-#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
-#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */
-#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */
-#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */
-#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */
-#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
-#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */
-#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */
-#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */
-#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */
-#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */
-#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */
-#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */
-#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */
-#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */
-#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
-#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */
-#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */
-#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */
-#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */
-#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
-#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */
-#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */
-#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */
-#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */
-#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
-#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */
-#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */
-#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */
-#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
-#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */
-#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */
-#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */
-#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
-#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */
-
-/* Bit fields for MSC IF */
-#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */
-#define _MSC_IF_MASK 0x0000017FUL /**< Mask for MSC_IF */
-#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */
-#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
-#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
-#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
-#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */
-#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */
-#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
-#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
-#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
-#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */
-#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */
-#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
-#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
-#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
-#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */
-#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */
-#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
-#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
-#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
-#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */
-#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */
-#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */
-#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */
-#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
-#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */
-#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */
-#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */
-#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */
-#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
-#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */
-#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */
-#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */
-#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */
-#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
-#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */
-#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */
-#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */
-#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */
-#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
-#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */
-
-/* Bit fields for MSC IFS */
-#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */
-#define _MSC_IFS_MASK 0x0000017FUL /**< Mask for MSC_IFS */
-#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */
-#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
-#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
-#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
-#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */
-#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */
-#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
-#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
-#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
-#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */
-#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */
-#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
-#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
-#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
-#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */
-#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */
-#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
-#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
-#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
-#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */
-#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */
-#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */
-#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */
-#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
-#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */
-#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */
-#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */
-#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */
-#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
-#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */
-#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */
-#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */
-#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */
-#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
-#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */
-#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */
-#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */
-#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */
-#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
-#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */
-
-/* Bit fields for MSC IFC */
-#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */
-#define _MSC_IFC_MASK 0x0000017FUL /**< Mask for MSC_IFC */
-#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */
-#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
-#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
-#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
-#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */
-#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */
-#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
-#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
-#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
-#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */
-#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */
-#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
-#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
-#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
-#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */
-#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */
-#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
-#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
-#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
-#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */
-#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */
-#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */
-#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */
-#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
-#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */
-#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */
-#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */
-#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */
-#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
-#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */
-#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */
-#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */
-#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */
-#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
-#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */
-#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */
-#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */
-#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */
-#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
-#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */
-
-/* Bit fields for MSC IEN */
-#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */
-#define _MSC_IEN_MASK 0x0000017FUL /**< Mask for MSC_IEN */
-#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */
-#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
-#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
-#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
-#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */
-#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */
-#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
-#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
-#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
-#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */
-#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */
-#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
-#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
-#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
-#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */
-#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */
-#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
-#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
-#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
-#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */
-#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */
-#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */
-#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */
-#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
-#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */
-#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */
-#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */
-#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */
-#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
-#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */
-#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */
-#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */
-#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */
-#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
-#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */
-#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */
-#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */
-#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */
-#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
-#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */
-
-/* Bit fields for MSC LOCK */
-#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */
-#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */
-#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
-#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
-#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */
-#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */
-#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */
-#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */
-#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */
-#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */
-#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */
-#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */
-#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */
-#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */
-
-/* Bit fields for MSC CACHECMD */
-#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */
-#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */
-#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */
-#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */
-#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */
-#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */
-#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */
-#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */
-#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */
-#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */
-#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */
-#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */
-#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */
-#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */
-#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */
-#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */
-#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */
-
-/* Bit fields for MSC CACHEHITS */
-#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */
-#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */
-#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */
-#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */
-#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */
-#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */
-
-/* Bit fields for MSC CACHEMISSES */
-#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */
-#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */
-#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */
-#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */
-#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */
-#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */
-
-/* Bit fields for MSC MASSLOCK */
-#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */
-#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */
-#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
-#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
-#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */
-#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */
-#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */
-#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */
-#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */
-#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */
-#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */
-#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */
-#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */
-#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */
-
-/* Bit fields for MSC STARTUP */
-#define _MSC_STARTUP_RESETVALUE 0x1300104DUL /**< Default value for MSC_STARTUP */
-#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */
-#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */
-#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */
-#define _MSC_STARTUP_STDLY0_DEFAULT 0x0000004DUL /**< Mode DEFAULT for MSC_STARTUP */
-#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */
-#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */
-#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */
-#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */
-#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */
-#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */
-#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */
-#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */
-#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */
-#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */
-#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */
-#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */
-#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */
-#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */
-#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */
-#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */
-#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */
-#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */
-#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */
-#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */
-#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */
-#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */
-#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */
-#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */
-
-/* Bit fields for MSC CMD */
-#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */
-#define _MSC_CMD_MASK 0x00000001UL /**< Mask for MSC_CMD */
-#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */
-#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */
-#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */
-#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */
-#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */
-
-/* Bit fields for MSC BOOTLOADERCTRL */
-#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */
-#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */
-#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */
-#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */
-#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */
-#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */
-#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */
-#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */
-#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */
-#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */
-#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */
-#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */
-
-/* Bit fields for MSC AAPUNLOCKCMD */
-#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */
-#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */
-#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */
-#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */
-#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */
-#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */
-#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */
-
-/* Bit fields for MSC CACHECONFIG0 */
-#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */
-#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */
-#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */
-#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */
-#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */
-#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */
-#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */
-#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */
-#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */
-#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */
-#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */
-#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */
-
-/** @} */
-/** @} End of group EFR32FG13P_MSC */
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_pcnt.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_pcnt.h
deleted file mode 100644
index 6b9d3d14..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_pcnt.h
+++ /dev/null
@@ -1,715 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_pcnt.h
- * @brief EFR32FG13P_PCNT register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P_PCNT PCNT
- * @{
- * @brief EFR32FG13P_PCNT Register Declaration
- *****************************************************************************/
-/** PCNT Register Declaration */
-typedef struct {
- __IOM uint32_t CTRL; /**< Control Register */
- __IOM uint32_t CMD; /**< Command Register */
- __IM uint32_t STATUS; /**< Status Register */
- __IM uint32_t CNT; /**< Counter Value Register */
- __IM uint32_t TOP; /**< Top Value Register */
- __IOM uint32_t TOPB; /**< Top Value Buffer Register */
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- uint32_t RESERVED0[1]; /**< Reserved for future use **/
- __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
-
- uint32_t RESERVED1[4]; /**< Reserved for future use **/
- __IOM uint32_t FREEZE; /**< Freeze Register */
- __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
-
- uint32_t RESERVED2[7]; /**< Reserved for future use **/
- __IM uint32_t AUXCNT; /**< Auxiliary Counter Value Register */
- __IOM uint32_t INPUT; /**< PCNT Input Register */
- __IOM uint32_t OVSCFG; /**< Oversampling Config Register */
-} PCNT_TypeDef; /** @} */
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_PCNT
- * @{
- * @defgroup EFR32FG13P_PCNT_BitFields PCNT Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for PCNT CTRL */
-#define _PCNT_CTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_CTRL */
-#define _PCNT_CTRL_MASK 0xBFDBFFFFUL /**< Mask for PCNT_CTRL */
-#define _PCNT_CTRL_MODE_SHIFT 0 /**< Shift value for PCNT_MODE */
-#define _PCNT_CTRL_MODE_MASK 0x7UL /**< Bit mask for PCNT_MODE */
-#define _PCNT_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
-#define _PCNT_CTRL_MODE_DISABLE 0x00000000UL /**< Mode DISABLE for PCNT_CTRL */
-#define _PCNT_CTRL_MODE_OVSSINGLE 0x00000001UL /**< Mode OVSSINGLE for PCNT_CTRL */
-#define _PCNT_CTRL_MODE_EXTCLKSINGLE 0x00000002UL /**< Mode EXTCLKSINGLE for PCNT_CTRL */
-#define _PCNT_CTRL_MODE_EXTCLKQUAD 0x00000003UL /**< Mode EXTCLKQUAD for PCNT_CTRL */
-#define _PCNT_CTRL_MODE_OVSQUAD1X 0x00000004UL /**< Mode OVSQUAD1X for PCNT_CTRL */
-#define _PCNT_CTRL_MODE_OVSQUAD2X 0x00000005UL /**< Mode OVSQUAD2X for PCNT_CTRL */
-#define _PCNT_CTRL_MODE_OVSQUAD4X 0x00000006UL /**< Mode OVSQUAD4X for PCNT_CTRL */
-#define PCNT_CTRL_MODE_DEFAULT (_PCNT_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CTRL */
-#define PCNT_CTRL_MODE_DISABLE (_PCNT_CTRL_MODE_DISABLE << 0) /**< Shifted mode DISABLE for PCNT_CTRL */
-#define PCNT_CTRL_MODE_OVSSINGLE (_PCNT_CTRL_MODE_OVSSINGLE << 0) /**< Shifted mode OVSSINGLE for PCNT_CTRL */
-#define PCNT_CTRL_MODE_EXTCLKSINGLE (_PCNT_CTRL_MODE_EXTCLKSINGLE << 0) /**< Shifted mode EXTCLKSINGLE for PCNT_CTRL */
-#define PCNT_CTRL_MODE_EXTCLKQUAD (_PCNT_CTRL_MODE_EXTCLKQUAD << 0) /**< Shifted mode EXTCLKQUAD for PCNT_CTRL */
-#define PCNT_CTRL_MODE_OVSQUAD1X (_PCNT_CTRL_MODE_OVSQUAD1X << 0) /**< Shifted mode OVSQUAD1X for PCNT_CTRL */
-#define PCNT_CTRL_MODE_OVSQUAD2X (_PCNT_CTRL_MODE_OVSQUAD2X << 0) /**< Shifted mode OVSQUAD2X for PCNT_CTRL */
-#define PCNT_CTRL_MODE_OVSQUAD4X (_PCNT_CTRL_MODE_OVSQUAD4X << 0) /**< Shifted mode OVSQUAD4X for PCNT_CTRL */
-#define PCNT_CTRL_FILT (0x1UL << 3) /**< Enable Digital Pulse Width Filter */
-#define _PCNT_CTRL_FILT_SHIFT 3 /**< Shift value for PCNT_FILT */
-#define _PCNT_CTRL_FILT_MASK 0x8UL /**< Bit mask for PCNT_FILT */
-#define _PCNT_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
-#define PCNT_CTRL_FILT_DEFAULT (_PCNT_CTRL_FILT_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_CTRL */
-#define PCNT_CTRL_RSTEN (0x1UL << 4) /**< Enable PCNT Clock Domain Reset */
-#define _PCNT_CTRL_RSTEN_SHIFT 4 /**< Shift value for PCNT_RSTEN */
-#define _PCNT_CTRL_RSTEN_MASK 0x10UL /**< Bit mask for PCNT_RSTEN */
-#define _PCNT_CTRL_RSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
-#define PCNT_CTRL_RSTEN_DEFAULT (_PCNT_CTRL_RSTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CTRL */
-#define PCNT_CTRL_CNTRSTEN (0x1UL << 5) /**< Enable CNT Reset */
-#define _PCNT_CTRL_CNTRSTEN_SHIFT 5 /**< Shift value for PCNT_CNTRSTEN */
-#define _PCNT_CTRL_CNTRSTEN_MASK 0x20UL /**< Bit mask for PCNT_CNTRSTEN */
-#define _PCNT_CTRL_CNTRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
-#define PCNT_CTRL_CNTRSTEN_DEFAULT (_PCNT_CTRL_CNTRSTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_CTRL */
-#define PCNT_CTRL_AUXCNTRSTEN (0x1UL << 6) /**< Enable AUXCNT Reset */
-#define _PCNT_CTRL_AUXCNTRSTEN_SHIFT 6 /**< Shift value for PCNT_AUXCNTRSTEN */
-#define _PCNT_CTRL_AUXCNTRSTEN_MASK 0x40UL /**< Bit mask for PCNT_AUXCNTRSTEN */
-#define _PCNT_CTRL_AUXCNTRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
-#define PCNT_CTRL_AUXCNTRSTEN_DEFAULT (_PCNT_CTRL_AUXCNTRSTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_CTRL */
-#define PCNT_CTRL_DEBUGHALT (0x1UL << 7) /**< Debug Mode Halt Enable */
-#define _PCNT_CTRL_DEBUGHALT_SHIFT 7 /**< Shift value for PCNT_DEBUGHALT */
-#define _PCNT_CTRL_DEBUGHALT_MASK 0x80UL /**< Bit mask for PCNT_DEBUGHALT */
-#define _PCNT_CTRL_DEBUGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
-#define PCNT_CTRL_DEBUGHALT_DEFAULT (_PCNT_CTRL_DEBUGHALT_DEFAULT << 7) /**< Shifted mode DEFAULT for PCNT_CTRL */
-#define PCNT_CTRL_HYST (0x1UL << 8) /**< Enable Hysteresis */
-#define _PCNT_CTRL_HYST_SHIFT 8 /**< Shift value for PCNT_HYST */
-#define _PCNT_CTRL_HYST_MASK 0x100UL /**< Bit mask for PCNT_HYST */
-#define _PCNT_CTRL_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
-#define PCNT_CTRL_HYST_DEFAULT (_PCNT_CTRL_HYST_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_CTRL */
-#define PCNT_CTRL_S1CDIR (0x1UL << 9) /**< Count Direction Determined By S1 */
-#define _PCNT_CTRL_S1CDIR_SHIFT 9 /**< Shift value for PCNT_S1CDIR */
-#define _PCNT_CTRL_S1CDIR_MASK 0x200UL /**< Bit mask for PCNT_S1CDIR */
-#define _PCNT_CTRL_S1CDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
-#define PCNT_CTRL_S1CDIR_DEFAULT (_PCNT_CTRL_S1CDIR_DEFAULT << 9) /**< Shifted mode DEFAULT for PCNT_CTRL */
-#define _PCNT_CTRL_CNTEV_SHIFT 10 /**< Shift value for PCNT_CNTEV */
-#define _PCNT_CTRL_CNTEV_MASK 0xC00UL /**< Bit mask for PCNT_CNTEV */
-#define _PCNT_CTRL_CNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
-#define _PCNT_CTRL_CNTEV_BOTH 0x00000000UL /**< Mode BOTH for PCNT_CTRL */
-#define _PCNT_CTRL_CNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */
-#define _PCNT_CTRL_CNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */
-#define _PCNT_CTRL_CNTEV_NONE 0x00000003UL /**< Mode NONE for PCNT_CTRL */
-#define PCNT_CTRL_CNTEV_DEFAULT (_PCNT_CTRL_CNTEV_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_CTRL */
-#define PCNT_CTRL_CNTEV_BOTH (_PCNT_CTRL_CNTEV_BOTH << 10) /**< Shifted mode BOTH for PCNT_CTRL */
-#define PCNT_CTRL_CNTEV_UP (_PCNT_CTRL_CNTEV_UP << 10) /**< Shifted mode UP for PCNT_CTRL */
-#define PCNT_CTRL_CNTEV_DOWN (_PCNT_CTRL_CNTEV_DOWN << 10) /**< Shifted mode DOWN for PCNT_CTRL */
-#define PCNT_CTRL_CNTEV_NONE (_PCNT_CTRL_CNTEV_NONE << 10) /**< Shifted mode NONE for PCNT_CTRL */
-#define _PCNT_CTRL_AUXCNTEV_SHIFT 12 /**< Shift value for PCNT_AUXCNTEV */
-#define _PCNT_CTRL_AUXCNTEV_MASK 0x3000UL /**< Bit mask for PCNT_AUXCNTEV */
-#define _PCNT_CTRL_AUXCNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
-#define _PCNT_CTRL_AUXCNTEV_NONE 0x00000000UL /**< Mode NONE for PCNT_CTRL */
-#define _PCNT_CTRL_AUXCNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */
-#define _PCNT_CTRL_AUXCNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */
-#define _PCNT_CTRL_AUXCNTEV_BOTH 0x00000003UL /**< Mode BOTH for PCNT_CTRL */
-#define PCNT_CTRL_AUXCNTEV_DEFAULT (_PCNT_CTRL_AUXCNTEV_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_CTRL */
-#define PCNT_CTRL_AUXCNTEV_NONE (_PCNT_CTRL_AUXCNTEV_NONE << 12) /**< Shifted mode NONE for PCNT_CTRL */
-#define PCNT_CTRL_AUXCNTEV_UP (_PCNT_CTRL_AUXCNTEV_UP << 12) /**< Shifted mode UP for PCNT_CTRL */
-#define PCNT_CTRL_AUXCNTEV_DOWN (_PCNT_CTRL_AUXCNTEV_DOWN << 12) /**< Shifted mode DOWN for PCNT_CTRL */
-#define PCNT_CTRL_AUXCNTEV_BOTH (_PCNT_CTRL_AUXCNTEV_BOTH << 12) /**< Shifted mode BOTH for PCNT_CTRL */
-#define PCNT_CTRL_CNTDIR (0x1UL << 14) /**< Non-Quadrature Mode Counter Direction Control */
-#define _PCNT_CTRL_CNTDIR_SHIFT 14 /**< Shift value for PCNT_CNTDIR */
-#define _PCNT_CTRL_CNTDIR_MASK 0x4000UL /**< Bit mask for PCNT_CNTDIR */
-#define _PCNT_CTRL_CNTDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
-#define _PCNT_CTRL_CNTDIR_UP 0x00000000UL /**< Mode UP for PCNT_CTRL */
-#define _PCNT_CTRL_CNTDIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_CTRL */
-#define PCNT_CTRL_CNTDIR_DEFAULT (_PCNT_CTRL_CNTDIR_DEFAULT << 14) /**< Shifted mode DEFAULT for PCNT_CTRL */
-#define PCNT_CTRL_CNTDIR_UP (_PCNT_CTRL_CNTDIR_UP << 14) /**< Shifted mode UP for PCNT_CTRL */
-#define PCNT_CTRL_CNTDIR_DOWN (_PCNT_CTRL_CNTDIR_DOWN << 14) /**< Shifted mode DOWN for PCNT_CTRL */
-#define PCNT_CTRL_EDGE (0x1UL << 15) /**< Edge Select */
-#define _PCNT_CTRL_EDGE_SHIFT 15 /**< Shift value for PCNT_EDGE */
-#define _PCNT_CTRL_EDGE_MASK 0x8000UL /**< Bit mask for PCNT_EDGE */
-#define _PCNT_CTRL_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
-#define _PCNT_CTRL_EDGE_POS 0x00000000UL /**< Mode POS for PCNT_CTRL */
-#define _PCNT_CTRL_EDGE_NEG 0x00000001UL /**< Mode NEG for PCNT_CTRL */
-#define PCNT_CTRL_EDGE_DEFAULT (_PCNT_CTRL_EDGE_DEFAULT << 15) /**< Shifted mode DEFAULT for PCNT_CTRL */
-#define PCNT_CTRL_EDGE_POS (_PCNT_CTRL_EDGE_POS << 15) /**< Shifted mode POS for PCNT_CTRL */
-#define PCNT_CTRL_EDGE_NEG (_PCNT_CTRL_EDGE_NEG << 15) /**< Shifted mode NEG for PCNT_CTRL */
-#define _PCNT_CTRL_TCCMODE_SHIFT 16 /**< Shift value for PCNT_TCCMODE */
-#define _PCNT_CTRL_TCCMODE_MASK 0x30000UL /**< Bit mask for PCNT_TCCMODE */
-#define _PCNT_CTRL_TCCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
-#define _PCNT_CTRL_TCCMODE_DISABLED 0x00000000UL /**< Mode DISABLED for PCNT_CTRL */
-#define _PCNT_CTRL_TCCMODE_LFA 0x00000001UL /**< Mode LFA for PCNT_CTRL */
-#define _PCNT_CTRL_TCCMODE_PRS 0x00000002UL /**< Mode PRS for PCNT_CTRL */
-#define PCNT_CTRL_TCCMODE_DEFAULT (_PCNT_CTRL_TCCMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for PCNT_CTRL */
-#define PCNT_CTRL_TCCMODE_DISABLED (_PCNT_CTRL_TCCMODE_DISABLED << 16) /**< Shifted mode DISABLED for PCNT_CTRL */
-#define PCNT_CTRL_TCCMODE_LFA (_PCNT_CTRL_TCCMODE_LFA << 16) /**< Shifted mode LFA for PCNT_CTRL */
-#define PCNT_CTRL_TCCMODE_PRS (_PCNT_CTRL_TCCMODE_PRS << 16) /**< Shifted mode PRS for PCNT_CTRL */
-#define _PCNT_CTRL_TCCPRESC_SHIFT 19 /**< Shift value for PCNT_TCCPRESC */
-#define _PCNT_CTRL_TCCPRESC_MASK 0x180000UL /**< Bit mask for PCNT_TCCPRESC */
-#define _PCNT_CTRL_TCCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
-#define _PCNT_CTRL_TCCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for PCNT_CTRL */
-#define _PCNT_CTRL_TCCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for PCNT_CTRL */
-#define _PCNT_CTRL_TCCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for PCNT_CTRL */
-#define _PCNT_CTRL_TCCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for PCNT_CTRL */
-#define PCNT_CTRL_TCCPRESC_DEFAULT (_PCNT_CTRL_TCCPRESC_DEFAULT << 19) /**< Shifted mode DEFAULT for PCNT_CTRL */
-#define PCNT_CTRL_TCCPRESC_DIV1 (_PCNT_CTRL_TCCPRESC_DIV1 << 19) /**< Shifted mode DIV1 for PCNT_CTRL */
-#define PCNT_CTRL_TCCPRESC_DIV2 (_PCNT_CTRL_TCCPRESC_DIV2 << 19) /**< Shifted mode DIV2 for PCNT_CTRL */
-#define PCNT_CTRL_TCCPRESC_DIV4 (_PCNT_CTRL_TCCPRESC_DIV4 << 19) /**< Shifted mode DIV4 for PCNT_CTRL */
-#define PCNT_CTRL_TCCPRESC_DIV8 (_PCNT_CTRL_TCCPRESC_DIV8 << 19) /**< Shifted mode DIV8 for PCNT_CTRL */
-#define _PCNT_CTRL_TCCCOMP_SHIFT 22 /**< Shift value for PCNT_TCCCOMP */
-#define _PCNT_CTRL_TCCCOMP_MASK 0xC00000UL /**< Bit mask for PCNT_TCCCOMP */
-#define _PCNT_CTRL_TCCCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
-#define _PCNT_CTRL_TCCCOMP_LTOE 0x00000000UL /**< Mode LTOE for PCNT_CTRL */
-#define _PCNT_CTRL_TCCCOMP_GTOE 0x00000001UL /**< Mode GTOE for PCNT_CTRL */
-#define _PCNT_CTRL_TCCCOMP_RANGE 0x00000002UL /**< Mode RANGE for PCNT_CTRL */
-#define PCNT_CTRL_TCCCOMP_DEFAULT (_PCNT_CTRL_TCCCOMP_DEFAULT << 22) /**< Shifted mode DEFAULT for PCNT_CTRL */
-#define PCNT_CTRL_TCCCOMP_LTOE (_PCNT_CTRL_TCCCOMP_LTOE << 22) /**< Shifted mode LTOE for PCNT_CTRL */
-#define PCNT_CTRL_TCCCOMP_GTOE (_PCNT_CTRL_TCCCOMP_GTOE << 22) /**< Shifted mode GTOE for PCNT_CTRL */
-#define PCNT_CTRL_TCCCOMP_RANGE (_PCNT_CTRL_TCCCOMP_RANGE << 22) /**< Shifted mode RANGE for PCNT_CTRL */
-#define PCNT_CTRL_PRSGATEEN (0x1UL << 24) /**< PRS Gate Enable */
-#define _PCNT_CTRL_PRSGATEEN_SHIFT 24 /**< Shift value for PCNT_PRSGATEEN */
-#define _PCNT_CTRL_PRSGATEEN_MASK 0x1000000UL /**< Bit mask for PCNT_PRSGATEEN */
-#define _PCNT_CTRL_PRSGATEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
-#define PCNT_CTRL_PRSGATEEN_DEFAULT (_PCNT_CTRL_PRSGATEEN_DEFAULT << 24) /**< Shifted mode DEFAULT for PCNT_CTRL */
-#define PCNT_CTRL_TCCPRSPOL (0x1UL << 25) /**< TCC PRS Polarity Select */
-#define _PCNT_CTRL_TCCPRSPOL_SHIFT 25 /**< Shift value for PCNT_TCCPRSPOL */
-#define _PCNT_CTRL_TCCPRSPOL_MASK 0x2000000UL /**< Bit mask for PCNT_TCCPRSPOL */
-#define _PCNT_CTRL_TCCPRSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
-#define _PCNT_CTRL_TCCPRSPOL_RISING 0x00000000UL /**< Mode RISING for PCNT_CTRL */
-#define _PCNT_CTRL_TCCPRSPOL_FALLING 0x00000001UL /**< Mode FALLING for PCNT_CTRL */
-#define PCNT_CTRL_TCCPRSPOL_DEFAULT (_PCNT_CTRL_TCCPRSPOL_DEFAULT << 25) /**< Shifted mode DEFAULT for PCNT_CTRL */
-#define PCNT_CTRL_TCCPRSPOL_RISING (_PCNT_CTRL_TCCPRSPOL_RISING << 25) /**< Shifted mode RISING for PCNT_CTRL */
-#define PCNT_CTRL_TCCPRSPOL_FALLING (_PCNT_CTRL_TCCPRSPOL_FALLING << 25) /**< Shifted mode FALLING for PCNT_CTRL */
-#define _PCNT_CTRL_TCCPRSSEL_SHIFT 26 /**< Shift value for PCNT_TCCPRSSEL */
-#define _PCNT_CTRL_TCCPRSSEL_MASK 0x3C000000UL /**< Bit mask for PCNT_TCCPRSSEL */
-#define _PCNT_CTRL_TCCPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
-#define _PCNT_CTRL_TCCPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_CTRL */
-#define _PCNT_CTRL_TCCPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_CTRL */
-#define _PCNT_CTRL_TCCPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_CTRL */
-#define _PCNT_CTRL_TCCPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_CTRL */
-#define _PCNT_CTRL_TCCPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_CTRL */
-#define _PCNT_CTRL_TCCPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_CTRL */
-#define _PCNT_CTRL_TCCPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_CTRL */
-#define _PCNT_CTRL_TCCPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_CTRL */
-#define _PCNT_CTRL_TCCPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_CTRL */
-#define _PCNT_CTRL_TCCPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_CTRL */
-#define _PCNT_CTRL_TCCPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_CTRL */
-#define _PCNT_CTRL_TCCPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_CTRL */
-#define PCNT_CTRL_TCCPRSSEL_DEFAULT (_PCNT_CTRL_TCCPRSSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for PCNT_CTRL */
-#define PCNT_CTRL_TCCPRSSEL_PRSCH0 (_PCNT_CTRL_TCCPRSSEL_PRSCH0 << 26) /**< Shifted mode PRSCH0 for PCNT_CTRL */
-#define PCNT_CTRL_TCCPRSSEL_PRSCH1 (_PCNT_CTRL_TCCPRSSEL_PRSCH1 << 26) /**< Shifted mode PRSCH1 for PCNT_CTRL */
-#define PCNT_CTRL_TCCPRSSEL_PRSCH2 (_PCNT_CTRL_TCCPRSSEL_PRSCH2 << 26) /**< Shifted mode PRSCH2 for PCNT_CTRL */
-#define PCNT_CTRL_TCCPRSSEL_PRSCH3 (_PCNT_CTRL_TCCPRSSEL_PRSCH3 << 26) /**< Shifted mode PRSCH3 for PCNT_CTRL */
-#define PCNT_CTRL_TCCPRSSEL_PRSCH4 (_PCNT_CTRL_TCCPRSSEL_PRSCH4 << 26) /**< Shifted mode PRSCH4 for PCNT_CTRL */
-#define PCNT_CTRL_TCCPRSSEL_PRSCH5 (_PCNT_CTRL_TCCPRSSEL_PRSCH5 << 26) /**< Shifted mode PRSCH5 for PCNT_CTRL */
-#define PCNT_CTRL_TCCPRSSEL_PRSCH6 (_PCNT_CTRL_TCCPRSSEL_PRSCH6 << 26) /**< Shifted mode PRSCH6 for PCNT_CTRL */
-#define PCNT_CTRL_TCCPRSSEL_PRSCH7 (_PCNT_CTRL_TCCPRSSEL_PRSCH7 << 26) /**< Shifted mode PRSCH7 for PCNT_CTRL */
-#define PCNT_CTRL_TCCPRSSEL_PRSCH8 (_PCNT_CTRL_TCCPRSSEL_PRSCH8 << 26) /**< Shifted mode PRSCH8 for PCNT_CTRL */
-#define PCNT_CTRL_TCCPRSSEL_PRSCH9 (_PCNT_CTRL_TCCPRSSEL_PRSCH9 << 26) /**< Shifted mode PRSCH9 for PCNT_CTRL */
-#define PCNT_CTRL_TCCPRSSEL_PRSCH10 (_PCNT_CTRL_TCCPRSSEL_PRSCH10 << 26) /**< Shifted mode PRSCH10 for PCNT_CTRL */
-#define PCNT_CTRL_TCCPRSSEL_PRSCH11 (_PCNT_CTRL_TCCPRSSEL_PRSCH11 << 26) /**< Shifted mode PRSCH11 for PCNT_CTRL */
-#define PCNT_CTRL_TOPBHFSEL (0x1UL << 31) /**< TOPB High Frequency Value Select */
-#define _PCNT_CTRL_TOPBHFSEL_SHIFT 31 /**< Shift value for PCNT_TOPBHFSEL */
-#define _PCNT_CTRL_TOPBHFSEL_MASK 0x80000000UL /**< Bit mask for PCNT_TOPBHFSEL */
-#define _PCNT_CTRL_TOPBHFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
-#define PCNT_CTRL_TOPBHFSEL_DEFAULT (_PCNT_CTRL_TOPBHFSEL_DEFAULT << 31) /**< Shifted mode DEFAULT for PCNT_CTRL */
-
-/* Bit fields for PCNT CMD */
-#define _PCNT_CMD_RESETVALUE 0x00000000UL /**< Default value for PCNT_CMD */
-#define _PCNT_CMD_MASK 0x00000003UL /**< Mask for PCNT_CMD */
-#define PCNT_CMD_LCNTIM (0x1UL << 0) /**< Load CNT Immediately */
-#define _PCNT_CMD_LCNTIM_SHIFT 0 /**< Shift value for PCNT_LCNTIM */
-#define _PCNT_CMD_LCNTIM_MASK 0x1UL /**< Bit mask for PCNT_LCNTIM */
-#define _PCNT_CMD_LCNTIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */
-#define PCNT_CMD_LCNTIM_DEFAULT (_PCNT_CMD_LCNTIM_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CMD */
-#define PCNT_CMD_LTOPBIM (0x1UL << 1) /**< Load TOPB Immediately */
-#define _PCNT_CMD_LTOPBIM_SHIFT 1 /**< Shift value for PCNT_LTOPBIM */
-#define _PCNT_CMD_LTOPBIM_MASK 0x2UL /**< Bit mask for PCNT_LTOPBIM */
-#define _PCNT_CMD_LTOPBIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */
-#define PCNT_CMD_LTOPBIM_DEFAULT (_PCNT_CMD_LTOPBIM_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CMD */
-
-/* Bit fields for PCNT STATUS */
-#define _PCNT_STATUS_RESETVALUE 0x00000000UL /**< Default value for PCNT_STATUS */
-#define _PCNT_STATUS_MASK 0x00000001UL /**< Mask for PCNT_STATUS */
-#define PCNT_STATUS_DIR (0x1UL << 0) /**< Current Counter Direction */
-#define _PCNT_STATUS_DIR_SHIFT 0 /**< Shift value for PCNT_DIR */
-#define _PCNT_STATUS_DIR_MASK 0x1UL /**< Bit mask for PCNT_DIR */
-#define _PCNT_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */
-#define _PCNT_STATUS_DIR_UP 0x00000000UL /**< Mode UP for PCNT_STATUS */
-#define _PCNT_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_STATUS */
-#define PCNT_STATUS_DIR_DEFAULT (_PCNT_STATUS_DIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_STATUS */
-#define PCNT_STATUS_DIR_UP (_PCNT_STATUS_DIR_UP << 0) /**< Shifted mode UP for PCNT_STATUS */
-#define PCNT_STATUS_DIR_DOWN (_PCNT_STATUS_DIR_DOWN << 0) /**< Shifted mode DOWN for PCNT_STATUS */
-
-/* Bit fields for PCNT CNT */
-#define _PCNT_CNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_CNT */
-#define _PCNT_CNT_MASK 0x0000FFFFUL /**< Mask for PCNT_CNT */
-#define _PCNT_CNT_CNT_SHIFT 0 /**< Shift value for PCNT_CNT */
-#define _PCNT_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for PCNT_CNT */
-#define _PCNT_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CNT */
-#define PCNT_CNT_CNT_DEFAULT (_PCNT_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CNT */
-
-/* Bit fields for PCNT TOP */
-#define _PCNT_TOP_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOP */
-#define _PCNT_TOP_MASK 0x0000FFFFUL /**< Mask for PCNT_TOP */
-#define _PCNT_TOP_TOP_SHIFT 0 /**< Shift value for PCNT_TOP */
-#define _PCNT_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for PCNT_TOP */
-#define _PCNT_TOP_TOP_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOP */
-#define PCNT_TOP_TOP_DEFAULT (_PCNT_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOP */
-
-/* Bit fields for PCNT TOPB */
-#define _PCNT_TOPB_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOPB */
-#define _PCNT_TOPB_MASK 0x0000FFFFUL /**< Mask for PCNT_TOPB */
-#define _PCNT_TOPB_TOPB_SHIFT 0 /**< Shift value for PCNT_TOPB */
-#define _PCNT_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for PCNT_TOPB */
-#define _PCNT_TOPB_TOPB_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOPB */
-#define PCNT_TOPB_TOPB_DEFAULT (_PCNT_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOPB */
-
-/* Bit fields for PCNT IF */
-#define _PCNT_IF_RESETVALUE 0x00000000UL /**< Default value for PCNT_IF */
-#define _PCNT_IF_MASK 0x0000003FUL /**< Mask for PCNT_IF */
-#define PCNT_IF_UF (0x1UL << 0) /**< Underflow Interrupt Read Flag */
-#define _PCNT_IF_UF_SHIFT 0 /**< Shift value for PCNT_UF */
-#define _PCNT_IF_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */
-#define _PCNT_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
-#define PCNT_IF_UF_DEFAULT (_PCNT_IF_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IF */
-#define PCNT_IF_OF (0x1UL << 1) /**< Overflow Interrupt Read Flag */
-#define _PCNT_IF_OF_SHIFT 1 /**< Shift value for PCNT_OF */
-#define _PCNT_IF_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */
-#define _PCNT_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
-#define PCNT_IF_OF_DEFAULT (_PCNT_IF_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IF */
-#define PCNT_IF_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */
-#define _PCNT_IF_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */
-#define _PCNT_IF_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */
-#define _PCNT_IF_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
-#define PCNT_IF_DIRCNG_DEFAULT (_PCNT_IF_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IF */
-#define PCNT_IF_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Read Flag */
-#define _PCNT_IF_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */
-#define _PCNT_IF_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */
-#define _PCNT_IF_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
-#define PCNT_IF_AUXOF_DEFAULT (_PCNT_IF_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IF */
-#define PCNT_IF_TCC (0x1UL << 4) /**< Triggered Compare Interrupt Read Flag */
-#define _PCNT_IF_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */
-#define _PCNT_IF_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */
-#define _PCNT_IF_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
-#define PCNT_IF_TCC_DEFAULT (_PCNT_IF_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IF */
-#define PCNT_IF_OQSTERR (0x1UL << 5) /**< Oversampling Quadrature State Error Interrupt */
-#define _PCNT_IF_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */
-#define _PCNT_IF_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */
-#define _PCNT_IF_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
-#define PCNT_IF_OQSTERR_DEFAULT (_PCNT_IF_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IF */
-
-/* Bit fields for PCNT IFS */
-#define _PCNT_IFS_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFS */
-#define _PCNT_IFS_MASK 0x0000003FUL /**< Mask for PCNT_IFS */
-#define PCNT_IFS_UF (0x1UL << 0) /**< Set UF Interrupt Flag */
-#define _PCNT_IFS_UF_SHIFT 0 /**< Shift value for PCNT_UF */
-#define _PCNT_IFS_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */
-#define _PCNT_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */
-#define PCNT_IFS_UF_DEFAULT (_PCNT_IFS_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IFS */
-#define PCNT_IFS_OF (0x1UL << 1) /**< Set OF Interrupt Flag */
-#define _PCNT_IFS_OF_SHIFT 1 /**< Shift value for PCNT_OF */
-#define _PCNT_IFS_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */
-#define _PCNT_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */
-#define PCNT_IFS_OF_DEFAULT (_PCNT_IFS_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IFS */
-#define PCNT_IFS_DIRCNG (0x1UL << 2) /**< Set DIRCNG Interrupt Flag */
-#define _PCNT_IFS_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */
-#define _PCNT_IFS_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */
-#define _PCNT_IFS_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */
-#define PCNT_IFS_DIRCNG_DEFAULT (_PCNT_IFS_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IFS */
-#define PCNT_IFS_AUXOF (0x1UL << 3) /**< Set AUXOF Interrupt Flag */
-#define _PCNT_IFS_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */
-#define _PCNT_IFS_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */
-#define _PCNT_IFS_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */
-#define PCNT_IFS_AUXOF_DEFAULT (_PCNT_IFS_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IFS */
-#define PCNT_IFS_TCC (0x1UL << 4) /**< Set TCC Interrupt Flag */
-#define _PCNT_IFS_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */
-#define _PCNT_IFS_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */
-#define _PCNT_IFS_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */
-#define PCNT_IFS_TCC_DEFAULT (_PCNT_IFS_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IFS */
-#define PCNT_IFS_OQSTERR (0x1UL << 5) /**< Set OQSTERR Interrupt Flag */
-#define _PCNT_IFS_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */
-#define _PCNT_IFS_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */
-#define _PCNT_IFS_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */
-#define PCNT_IFS_OQSTERR_DEFAULT (_PCNT_IFS_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IFS */
-
-/* Bit fields for PCNT IFC */
-#define _PCNT_IFC_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFC */
-#define _PCNT_IFC_MASK 0x0000003FUL /**< Mask for PCNT_IFC */
-#define PCNT_IFC_UF (0x1UL << 0) /**< Clear UF Interrupt Flag */
-#define _PCNT_IFC_UF_SHIFT 0 /**< Shift value for PCNT_UF */
-#define _PCNT_IFC_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */
-#define _PCNT_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */
-#define PCNT_IFC_UF_DEFAULT (_PCNT_IFC_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IFC */
-#define PCNT_IFC_OF (0x1UL << 1) /**< Clear OF Interrupt Flag */
-#define _PCNT_IFC_OF_SHIFT 1 /**< Shift value for PCNT_OF */
-#define _PCNT_IFC_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */
-#define _PCNT_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */
-#define PCNT_IFC_OF_DEFAULT (_PCNT_IFC_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IFC */
-#define PCNT_IFC_DIRCNG (0x1UL << 2) /**< Clear DIRCNG Interrupt Flag */
-#define _PCNT_IFC_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */
-#define _PCNT_IFC_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */
-#define _PCNT_IFC_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */
-#define PCNT_IFC_DIRCNG_DEFAULT (_PCNT_IFC_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IFC */
-#define PCNT_IFC_AUXOF (0x1UL << 3) /**< Clear AUXOF Interrupt Flag */
-#define _PCNT_IFC_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */
-#define _PCNT_IFC_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */
-#define _PCNT_IFC_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */
-#define PCNT_IFC_AUXOF_DEFAULT (_PCNT_IFC_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IFC */
-#define PCNT_IFC_TCC (0x1UL << 4) /**< Clear TCC Interrupt Flag */
-#define _PCNT_IFC_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */
-#define _PCNT_IFC_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */
-#define _PCNT_IFC_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */
-#define PCNT_IFC_TCC_DEFAULT (_PCNT_IFC_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IFC */
-#define PCNT_IFC_OQSTERR (0x1UL << 5) /**< Clear OQSTERR Interrupt Flag */
-#define _PCNT_IFC_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */
-#define _PCNT_IFC_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */
-#define _PCNT_IFC_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */
-#define PCNT_IFC_OQSTERR_DEFAULT (_PCNT_IFC_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IFC */
-
-/* Bit fields for PCNT IEN */
-#define _PCNT_IEN_RESETVALUE 0x00000000UL /**< Default value for PCNT_IEN */
-#define _PCNT_IEN_MASK 0x0000003FUL /**< Mask for PCNT_IEN */
-#define PCNT_IEN_UF (0x1UL << 0) /**< UF Interrupt Enable */
-#define _PCNT_IEN_UF_SHIFT 0 /**< Shift value for PCNT_UF */
-#define _PCNT_IEN_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */
-#define _PCNT_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
-#define PCNT_IEN_UF_DEFAULT (_PCNT_IEN_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IEN */
-#define PCNT_IEN_OF (0x1UL << 1) /**< OF Interrupt Enable */
-#define _PCNT_IEN_OF_SHIFT 1 /**< Shift value for PCNT_OF */
-#define _PCNT_IEN_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */
-#define _PCNT_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
-#define PCNT_IEN_OF_DEFAULT (_PCNT_IEN_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IEN */
-#define PCNT_IEN_DIRCNG (0x1UL << 2) /**< DIRCNG Interrupt Enable */
-#define _PCNT_IEN_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */
-#define _PCNT_IEN_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */
-#define _PCNT_IEN_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
-#define PCNT_IEN_DIRCNG_DEFAULT (_PCNT_IEN_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IEN */
-#define PCNT_IEN_AUXOF (0x1UL << 3) /**< AUXOF Interrupt Enable */
-#define _PCNT_IEN_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */
-#define _PCNT_IEN_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */
-#define _PCNT_IEN_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
-#define PCNT_IEN_AUXOF_DEFAULT (_PCNT_IEN_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IEN */
-#define PCNT_IEN_TCC (0x1UL << 4) /**< TCC Interrupt Enable */
-#define _PCNT_IEN_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */
-#define _PCNT_IEN_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */
-#define _PCNT_IEN_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
-#define PCNT_IEN_TCC_DEFAULT (_PCNT_IEN_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IEN */
-#define PCNT_IEN_OQSTERR (0x1UL << 5) /**< OQSTERR Interrupt Enable */
-#define _PCNT_IEN_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */
-#define _PCNT_IEN_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */
-#define _PCNT_IEN_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
-#define PCNT_IEN_OQSTERR_DEFAULT (_PCNT_IEN_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IEN */
-
-/* Bit fields for PCNT ROUTELOC0 */
-#define _PCNT_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_SHIFT 0 /**< Shift value for PCNT_S0INLOC */
-#define _PCNT_ROUTELOC0_S0INLOC_MASK 0x1FUL /**< Bit mask for PCNT_S0INLOC */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC0 0x00000000UL /**< Mode LOC0 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC1 0x00000001UL /**< Mode LOC1 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC2 0x00000002UL /**< Mode LOC2 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC3 0x00000003UL /**< Mode LOC3 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC4 0x00000004UL /**< Mode LOC4 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC5 0x00000005UL /**< Mode LOC5 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC6 0x00000006UL /**< Mode LOC6 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC7 0x00000007UL /**< Mode LOC7 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC8 0x00000008UL /**< Mode LOC8 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC9 0x00000009UL /**< Mode LOC9 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC10 0x0000000AUL /**< Mode LOC10 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC11 0x0000000BUL /**< Mode LOC11 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC12 0x0000000CUL /**< Mode LOC12 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC13 0x0000000DUL /**< Mode LOC13 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC14 0x0000000EUL /**< Mode LOC14 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC15 0x0000000FUL /**< Mode LOC15 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC16 0x00000010UL /**< Mode LOC16 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC17 0x00000011UL /**< Mode LOC17 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC18 0x00000012UL /**< Mode LOC18 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC19 0x00000013UL /**< Mode LOC19 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC20 0x00000014UL /**< Mode LOC20 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC21 0x00000015UL /**< Mode LOC21 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC22 0x00000016UL /**< Mode LOC22 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC23 0x00000017UL /**< Mode LOC23 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC24 0x00000018UL /**< Mode LOC24 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC25 0x00000019UL /**< Mode LOC25 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC26 0x0000001AUL /**< Mode LOC26 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC27 0x0000001BUL /**< Mode LOC27 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC28 0x0000001CUL /**< Mode LOC28 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC29 0x0000001DUL /**< Mode LOC29 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC30 0x0000001EUL /**< Mode LOC30 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S0INLOC_LOC31 0x0000001FUL /**< Mode LOC31 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC0 (_PCNT_ROUTELOC0_S0INLOC_LOC0 << 0) /**< Shifted mode LOC0 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_DEFAULT (_PCNT_ROUTELOC0_S0INLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC1 (_PCNT_ROUTELOC0_S0INLOC_LOC1 << 0) /**< Shifted mode LOC1 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC2 (_PCNT_ROUTELOC0_S0INLOC_LOC2 << 0) /**< Shifted mode LOC2 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC3 (_PCNT_ROUTELOC0_S0INLOC_LOC3 << 0) /**< Shifted mode LOC3 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC4 (_PCNT_ROUTELOC0_S0INLOC_LOC4 << 0) /**< Shifted mode LOC4 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC5 (_PCNT_ROUTELOC0_S0INLOC_LOC5 << 0) /**< Shifted mode LOC5 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC6 (_PCNT_ROUTELOC0_S0INLOC_LOC6 << 0) /**< Shifted mode LOC6 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC7 (_PCNT_ROUTELOC0_S0INLOC_LOC7 << 0) /**< Shifted mode LOC7 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC8 (_PCNT_ROUTELOC0_S0INLOC_LOC8 << 0) /**< Shifted mode LOC8 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC9 (_PCNT_ROUTELOC0_S0INLOC_LOC9 << 0) /**< Shifted mode LOC9 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC10 (_PCNT_ROUTELOC0_S0INLOC_LOC10 << 0) /**< Shifted mode LOC10 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC11 (_PCNT_ROUTELOC0_S0INLOC_LOC11 << 0) /**< Shifted mode LOC11 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC12 (_PCNT_ROUTELOC0_S0INLOC_LOC12 << 0) /**< Shifted mode LOC12 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC13 (_PCNT_ROUTELOC0_S0INLOC_LOC13 << 0) /**< Shifted mode LOC13 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC14 (_PCNT_ROUTELOC0_S0INLOC_LOC14 << 0) /**< Shifted mode LOC14 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC15 (_PCNT_ROUTELOC0_S0INLOC_LOC15 << 0) /**< Shifted mode LOC15 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC16 (_PCNT_ROUTELOC0_S0INLOC_LOC16 << 0) /**< Shifted mode LOC16 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC17 (_PCNT_ROUTELOC0_S0INLOC_LOC17 << 0) /**< Shifted mode LOC17 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC18 (_PCNT_ROUTELOC0_S0INLOC_LOC18 << 0) /**< Shifted mode LOC18 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC19 (_PCNT_ROUTELOC0_S0INLOC_LOC19 << 0) /**< Shifted mode LOC19 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC20 (_PCNT_ROUTELOC0_S0INLOC_LOC20 << 0) /**< Shifted mode LOC20 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC21 (_PCNT_ROUTELOC0_S0INLOC_LOC21 << 0) /**< Shifted mode LOC21 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC22 (_PCNT_ROUTELOC0_S0INLOC_LOC22 << 0) /**< Shifted mode LOC22 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC23 (_PCNT_ROUTELOC0_S0INLOC_LOC23 << 0) /**< Shifted mode LOC23 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC24 (_PCNT_ROUTELOC0_S0INLOC_LOC24 << 0) /**< Shifted mode LOC24 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC25 (_PCNT_ROUTELOC0_S0INLOC_LOC25 << 0) /**< Shifted mode LOC25 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC26 (_PCNT_ROUTELOC0_S0INLOC_LOC26 << 0) /**< Shifted mode LOC26 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC27 (_PCNT_ROUTELOC0_S0INLOC_LOC27 << 0) /**< Shifted mode LOC27 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC28 (_PCNT_ROUTELOC0_S0INLOC_LOC28 << 0) /**< Shifted mode LOC28 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC29 (_PCNT_ROUTELOC0_S0INLOC_LOC29 << 0) /**< Shifted mode LOC29 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC30 (_PCNT_ROUTELOC0_S0INLOC_LOC30 << 0) /**< Shifted mode LOC30 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S0INLOC_LOC31 (_PCNT_ROUTELOC0_S0INLOC_LOC31 << 0) /**< Shifted mode LOC31 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_SHIFT 8 /**< Shift value for PCNT_S1INLOC */
-#define _PCNT_ROUTELOC0_S1INLOC_MASK 0x1F00UL /**< Bit mask for PCNT_S1INLOC */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC0 0x00000000UL /**< Mode LOC0 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC1 0x00000001UL /**< Mode LOC1 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC2 0x00000002UL /**< Mode LOC2 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC3 0x00000003UL /**< Mode LOC3 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC4 0x00000004UL /**< Mode LOC4 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC5 0x00000005UL /**< Mode LOC5 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC6 0x00000006UL /**< Mode LOC6 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC7 0x00000007UL /**< Mode LOC7 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC8 0x00000008UL /**< Mode LOC8 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC9 0x00000009UL /**< Mode LOC9 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC10 0x0000000AUL /**< Mode LOC10 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC11 0x0000000BUL /**< Mode LOC11 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC12 0x0000000CUL /**< Mode LOC12 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC13 0x0000000DUL /**< Mode LOC13 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC14 0x0000000EUL /**< Mode LOC14 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC15 0x0000000FUL /**< Mode LOC15 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC16 0x00000010UL /**< Mode LOC16 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC17 0x00000011UL /**< Mode LOC17 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC18 0x00000012UL /**< Mode LOC18 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC19 0x00000013UL /**< Mode LOC19 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC20 0x00000014UL /**< Mode LOC20 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC21 0x00000015UL /**< Mode LOC21 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC22 0x00000016UL /**< Mode LOC22 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC23 0x00000017UL /**< Mode LOC23 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC24 0x00000018UL /**< Mode LOC24 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC25 0x00000019UL /**< Mode LOC25 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC26 0x0000001AUL /**< Mode LOC26 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC27 0x0000001BUL /**< Mode LOC27 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC28 0x0000001CUL /**< Mode LOC28 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC29 0x0000001DUL /**< Mode LOC29 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC30 0x0000001EUL /**< Mode LOC30 for PCNT_ROUTELOC0 */
-#define _PCNT_ROUTELOC0_S1INLOC_LOC31 0x0000001FUL /**< Mode LOC31 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC0 (_PCNT_ROUTELOC0_S1INLOC_LOC0 << 8) /**< Shifted mode LOC0 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_DEFAULT (_PCNT_ROUTELOC0_S1INLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC1 (_PCNT_ROUTELOC0_S1INLOC_LOC1 << 8) /**< Shifted mode LOC1 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC2 (_PCNT_ROUTELOC0_S1INLOC_LOC2 << 8) /**< Shifted mode LOC2 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC3 (_PCNT_ROUTELOC0_S1INLOC_LOC3 << 8) /**< Shifted mode LOC3 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC4 (_PCNT_ROUTELOC0_S1INLOC_LOC4 << 8) /**< Shifted mode LOC4 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC5 (_PCNT_ROUTELOC0_S1INLOC_LOC5 << 8) /**< Shifted mode LOC5 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC6 (_PCNT_ROUTELOC0_S1INLOC_LOC6 << 8) /**< Shifted mode LOC6 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC7 (_PCNT_ROUTELOC0_S1INLOC_LOC7 << 8) /**< Shifted mode LOC7 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC8 (_PCNT_ROUTELOC0_S1INLOC_LOC8 << 8) /**< Shifted mode LOC8 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC9 (_PCNT_ROUTELOC0_S1INLOC_LOC9 << 8) /**< Shifted mode LOC9 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC10 (_PCNT_ROUTELOC0_S1INLOC_LOC10 << 8) /**< Shifted mode LOC10 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC11 (_PCNT_ROUTELOC0_S1INLOC_LOC11 << 8) /**< Shifted mode LOC11 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC12 (_PCNT_ROUTELOC0_S1INLOC_LOC12 << 8) /**< Shifted mode LOC12 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC13 (_PCNT_ROUTELOC0_S1INLOC_LOC13 << 8) /**< Shifted mode LOC13 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC14 (_PCNT_ROUTELOC0_S1INLOC_LOC14 << 8) /**< Shifted mode LOC14 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC15 (_PCNT_ROUTELOC0_S1INLOC_LOC15 << 8) /**< Shifted mode LOC15 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC16 (_PCNT_ROUTELOC0_S1INLOC_LOC16 << 8) /**< Shifted mode LOC16 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC17 (_PCNT_ROUTELOC0_S1INLOC_LOC17 << 8) /**< Shifted mode LOC17 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC18 (_PCNT_ROUTELOC0_S1INLOC_LOC18 << 8) /**< Shifted mode LOC18 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC19 (_PCNT_ROUTELOC0_S1INLOC_LOC19 << 8) /**< Shifted mode LOC19 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC20 (_PCNT_ROUTELOC0_S1INLOC_LOC20 << 8) /**< Shifted mode LOC20 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC21 (_PCNT_ROUTELOC0_S1INLOC_LOC21 << 8) /**< Shifted mode LOC21 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC22 (_PCNT_ROUTELOC0_S1INLOC_LOC22 << 8) /**< Shifted mode LOC22 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC23 (_PCNT_ROUTELOC0_S1INLOC_LOC23 << 8) /**< Shifted mode LOC23 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC24 (_PCNT_ROUTELOC0_S1INLOC_LOC24 << 8) /**< Shifted mode LOC24 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC25 (_PCNT_ROUTELOC0_S1INLOC_LOC25 << 8) /**< Shifted mode LOC25 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC26 (_PCNT_ROUTELOC0_S1INLOC_LOC26 << 8) /**< Shifted mode LOC26 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC27 (_PCNT_ROUTELOC0_S1INLOC_LOC27 << 8) /**< Shifted mode LOC27 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC28 (_PCNT_ROUTELOC0_S1INLOC_LOC28 << 8) /**< Shifted mode LOC28 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC29 (_PCNT_ROUTELOC0_S1INLOC_LOC29 << 8) /**< Shifted mode LOC29 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC30 (_PCNT_ROUTELOC0_S1INLOC_LOC30 << 8) /**< Shifted mode LOC30 for PCNT_ROUTELOC0 */
-#define PCNT_ROUTELOC0_S1INLOC_LOC31 (_PCNT_ROUTELOC0_S1INLOC_LOC31 << 8) /**< Shifted mode LOC31 for PCNT_ROUTELOC0 */
-
-/* Bit fields for PCNT FREEZE */
-#define _PCNT_FREEZE_RESETVALUE 0x00000000UL /**< Default value for PCNT_FREEZE */
-#define _PCNT_FREEZE_MASK 0x00000001UL /**< Mask for PCNT_FREEZE */
-#define PCNT_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
-#define _PCNT_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for PCNT_REGFREEZE */
-#define _PCNT_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for PCNT_REGFREEZE */
-#define _PCNT_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_FREEZE */
-#define _PCNT_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for PCNT_FREEZE */
-#define _PCNT_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for PCNT_FREEZE */
-#define PCNT_FREEZE_REGFREEZE_DEFAULT (_PCNT_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_FREEZE */
-#define PCNT_FREEZE_REGFREEZE_UPDATE (_PCNT_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for PCNT_FREEZE */
-#define PCNT_FREEZE_REGFREEZE_FREEZE (_PCNT_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for PCNT_FREEZE */
-
-/* Bit fields for PCNT SYNCBUSY */
-#define _PCNT_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for PCNT_SYNCBUSY */
-#define _PCNT_SYNCBUSY_MASK 0x0000000FUL /**< Mask for PCNT_SYNCBUSY */
-#define PCNT_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
-#define _PCNT_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for PCNT_CTRL */
-#define _PCNT_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for PCNT_CTRL */
-#define _PCNT_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
-#define PCNT_SYNCBUSY_CTRL_DEFAULT (_PCNT_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
-#define PCNT_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */
-#define _PCNT_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for PCNT_CMD */
-#define _PCNT_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for PCNT_CMD */
-#define _PCNT_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
-#define PCNT_SYNCBUSY_CMD_DEFAULT (_PCNT_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
-#define PCNT_SYNCBUSY_TOPB (0x1UL << 2) /**< TOPB Register Busy */
-#define _PCNT_SYNCBUSY_TOPB_SHIFT 2 /**< Shift value for PCNT_TOPB */
-#define _PCNT_SYNCBUSY_TOPB_MASK 0x4UL /**< Bit mask for PCNT_TOPB */
-#define _PCNT_SYNCBUSY_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
-#define PCNT_SYNCBUSY_TOPB_DEFAULT (_PCNT_SYNCBUSY_TOPB_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
-#define PCNT_SYNCBUSY_OVSCFG (0x1UL << 3) /**< OVSCFG Register Busy */
-#define _PCNT_SYNCBUSY_OVSCFG_SHIFT 3 /**< Shift value for PCNT_OVSCFG */
-#define _PCNT_SYNCBUSY_OVSCFG_MASK 0x8UL /**< Bit mask for PCNT_OVSCFG */
-#define _PCNT_SYNCBUSY_OVSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
-#define PCNT_SYNCBUSY_OVSCFG_DEFAULT (_PCNT_SYNCBUSY_OVSCFG_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
-
-/* Bit fields for PCNT AUXCNT */
-#define _PCNT_AUXCNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_AUXCNT */
-#define _PCNT_AUXCNT_MASK 0x0000FFFFUL /**< Mask for PCNT_AUXCNT */
-#define _PCNT_AUXCNT_AUXCNT_SHIFT 0 /**< Shift value for PCNT_AUXCNT */
-#define _PCNT_AUXCNT_AUXCNT_MASK 0xFFFFUL /**< Bit mask for PCNT_AUXCNT */
-#define _PCNT_AUXCNT_AUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_AUXCNT */
-#define PCNT_AUXCNT_AUXCNT_DEFAULT (_PCNT_AUXCNT_AUXCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_AUXCNT */
-
-/* Bit fields for PCNT INPUT */
-#define _PCNT_INPUT_RESETVALUE 0x00000000UL /**< Default value for PCNT_INPUT */
-#define _PCNT_INPUT_MASK 0x00000BEFUL /**< Mask for PCNT_INPUT */
-#define _PCNT_INPUT_S0PRSSEL_SHIFT 0 /**< Shift value for PCNT_S0PRSSEL */
-#define _PCNT_INPUT_S0PRSSEL_MASK 0xFUL /**< Bit mask for PCNT_S0PRSSEL */
-#define _PCNT_INPUT_S0PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */
-#define _PCNT_INPUT_S0PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_INPUT */
-#define _PCNT_INPUT_S0PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_INPUT */
-#define _PCNT_INPUT_S0PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_INPUT */
-#define _PCNT_INPUT_S0PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_INPUT */
-#define _PCNT_INPUT_S0PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_INPUT */
-#define _PCNT_INPUT_S0PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_INPUT */
-#define _PCNT_INPUT_S0PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_INPUT */
-#define _PCNT_INPUT_S0PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_INPUT */
-#define _PCNT_INPUT_S0PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_INPUT */
-#define _PCNT_INPUT_S0PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_INPUT */
-#define _PCNT_INPUT_S0PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_INPUT */
-#define _PCNT_INPUT_S0PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_INPUT */
-#define PCNT_INPUT_S0PRSSEL_DEFAULT (_PCNT_INPUT_S0PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_INPUT */
-#define PCNT_INPUT_S0PRSSEL_PRSCH0 (_PCNT_INPUT_S0PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PCNT_INPUT */
-#define PCNT_INPUT_S0PRSSEL_PRSCH1 (_PCNT_INPUT_S0PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PCNT_INPUT */
-#define PCNT_INPUT_S0PRSSEL_PRSCH2 (_PCNT_INPUT_S0PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PCNT_INPUT */
-#define PCNT_INPUT_S0PRSSEL_PRSCH3 (_PCNT_INPUT_S0PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PCNT_INPUT */
-#define PCNT_INPUT_S0PRSSEL_PRSCH4 (_PCNT_INPUT_S0PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PCNT_INPUT */
-#define PCNT_INPUT_S0PRSSEL_PRSCH5 (_PCNT_INPUT_S0PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PCNT_INPUT */
-#define PCNT_INPUT_S0PRSSEL_PRSCH6 (_PCNT_INPUT_S0PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PCNT_INPUT */
-#define PCNT_INPUT_S0PRSSEL_PRSCH7 (_PCNT_INPUT_S0PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PCNT_INPUT */
-#define PCNT_INPUT_S0PRSSEL_PRSCH8 (_PCNT_INPUT_S0PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PCNT_INPUT */
-#define PCNT_INPUT_S0PRSSEL_PRSCH9 (_PCNT_INPUT_S0PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PCNT_INPUT */
-#define PCNT_INPUT_S0PRSSEL_PRSCH10 (_PCNT_INPUT_S0PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PCNT_INPUT */
-#define PCNT_INPUT_S0PRSSEL_PRSCH11 (_PCNT_INPUT_S0PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PCNT_INPUT */
-#define PCNT_INPUT_S0PRSEN (0x1UL << 5) /**< S0IN PRS Enable */
-#define _PCNT_INPUT_S0PRSEN_SHIFT 5 /**< Shift value for PCNT_S0PRSEN */
-#define _PCNT_INPUT_S0PRSEN_MASK 0x20UL /**< Bit mask for PCNT_S0PRSEN */
-#define _PCNT_INPUT_S0PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */
-#define PCNT_INPUT_S0PRSEN_DEFAULT (_PCNT_INPUT_S0PRSEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_INPUT */
-#define _PCNT_INPUT_S1PRSSEL_SHIFT 6 /**< Shift value for PCNT_S1PRSSEL */
-#define _PCNT_INPUT_S1PRSSEL_MASK 0x3C0UL /**< Bit mask for PCNT_S1PRSSEL */
-#define _PCNT_INPUT_S1PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */
-#define _PCNT_INPUT_S1PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_INPUT */
-#define _PCNT_INPUT_S1PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_INPUT */
-#define _PCNT_INPUT_S1PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_INPUT */
-#define _PCNT_INPUT_S1PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_INPUT */
-#define _PCNT_INPUT_S1PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_INPUT */
-#define _PCNT_INPUT_S1PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_INPUT */
-#define _PCNT_INPUT_S1PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_INPUT */
-#define _PCNT_INPUT_S1PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_INPUT */
-#define _PCNT_INPUT_S1PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_INPUT */
-#define _PCNT_INPUT_S1PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_INPUT */
-#define _PCNT_INPUT_S1PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_INPUT */
-#define _PCNT_INPUT_S1PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_INPUT */
-#define PCNT_INPUT_S1PRSSEL_DEFAULT (_PCNT_INPUT_S1PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_INPUT */
-#define PCNT_INPUT_S1PRSSEL_PRSCH0 (_PCNT_INPUT_S1PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PCNT_INPUT */
-#define PCNT_INPUT_S1PRSSEL_PRSCH1 (_PCNT_INPUT_S1PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PCNT_INPUT */
-#define PCNT_INPUT_S1PRSSEL_PRSCH2 (_PCNT_INPUT_S1PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PCNT_INPUT */
-#define PCNT_INPUT_S1PRSSEL_PRSCH3 (_PCNT_INPUT_S1PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PCNT_INPUT */
-#define PCNT_INPUT_S1PRSSEL_PRSCH4 (_PCNT_INPUT_S1PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PCNT_INPUT */
-#define PCNT_INPUT_S1PRSSEL_PRSCH5 (_PCNT_INPUT_S1PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PCNT_INPUT */
-#define PCNT_INPUT_S1PRSSEL_PRSCH6 (_PCNT_INPUT_S1PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PCNT_INPUT */
-#define PCNT_INPUT_S1PRSSEL_PRSCH7 (_PCNT_INPUT_S1PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PCNT_INPUT */
-#define PCNT_INPUT_S1PRSSEL_PRSCH8 (_PCNT_INPUT_S1PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PCNT_INPUT */
-#define PCNT_INPUT_S1PRSSEL_PRSCH9 (_PCNT_INPUT_S1PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PCNT_INPUT */
-#define PCNT_INPUT_S1PRSSEL_PRSCH10 (_PCNT_INPUT_S1PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PCNT_INPUT */
-#define PCNT_INPUT_S1PRSSEL_PRSCH11 (_PCNT_INPUT_S1PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PCNT_INPUT */
-#define PCNT_INPUT_S1PRSEN (0x1UL << 11) /**< S1IN PRS Enable */
-#define _PCNT_INPUT_S1PRSEN_SHIFT 11 /**< Shift value for PCNT_S1PRSEN */
-#define _PCNT_INPUT_S1PRSEN_MASK 0x800UL /**< Bit mask for PCNT_S1PRSEN */
-#define _PCNT_INPUT_S1PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */
-#define PCNT_INPUT_S1PRSEN_DEFAULT (_PCNT_INPUT_S1PRSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PCNT_INPUT */
-
-/* Bit fields for PCNT OVSCFG */
-#define _PCNT_OVSCFG_RESETVALUE 0x00000000UL /**< Default value for PCNT_OVSCFG */
-#define _PCNT_OVSCFG_MASK 0x000010FFUL /**< Mask for PCNT_OVSCFG */
-#define _PCNT_OVSCFG_FILTLEN_SHIFT 0 /**< Shift value for PCNT_FILTLEN */
-#define _PCNT_OVSCFG_FILTLEN_MASK 0xFFUL /**< Bit mask for PCNT_FILTLEN */
-#define _PCNT_OVSCFG_FILTLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCFG */
-#define PCNT_OVSCFG_FILTLEN_DEFAULT (_PCNT_OVSCFG_FILTLEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_OVSCFG */
-#define PCNT_OVSCFG_FLUTTERRM (0x1UL << 12) /**< Flutter Remove */
-#define _PCNT_OVSCFG_FLUTTERRM_SHIFT 12 /**< Shift value for PCNT_FLUTTERRM */
-#define _PCNT_OVSCFG_FLUTTERRM_MASK 0x1000UL /**< Bit mask for PCNT_FLUTTERRM */
-#define _PCNT_OVSCFG_FLUTTERRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCFG */
-#define PCNT_OVSCFG_FLUTTERRM_DEFAULT (_PCNT_OVSCFG_FLUTTERRM_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_OVSCFG */
-
-/** @} */
-/** @} End of group EFR32FG13P_PCNT */
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_prs.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_prs.h
deleted file mode 100644
index 43ccdb88..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_prs.h
+++ /dev/null
@@ -1,1056 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_prs.h
- * @brief EFR32FG13P_PRS register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P_PRS PRS
- * @{
- * @brief EFR32FG13P_PRS Register Declaration
- *****************************************************************************/
-/** PRS Register Declaration */
-typedef struct {
- __IOM uint32_t SWPULSE; /**< Software Pulse Register */
- __IOM uint32_t SWLEVEL; /**< Software Level Register */
- __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
- uint32_t RESERVED0[1]; /**< Reserved for future use **/
- __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
- __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */
- __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */
-
- uint32_t RESERVED1[5]; /**< Reserved for future use **/
- __IOM uint32_t CTRL; /**< Control Register */
- __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */
- __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */
- uint32_t RESERVED2[1]; /**< Reserved for future use **/
- __IM uint32_t PEEK; /**< PRS Channel Values */
-
- uint32_t RESERVED3[3]; /**< Reserved registers */
- PRS_CH_TypeDef CH[12]; /**< Channel registers */
-} PRS_TypeDef; /** @} */
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_PRS
- * @{
- * @defgroup EFR32FG13P_PRS_BitFields PRS Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for PRS SWPULSE */
-#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */
-#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */
-#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */
-#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */
-#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */
-#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
-#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */
-#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */
-#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */
-#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */
-#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
-#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */
-#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */
-#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */
-#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */
-#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
-#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */
-#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */
-#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */
-#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */
-#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
-#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */
-#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */
-#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */
-#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */
-#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
-#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */
-#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */
-#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */
-#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */
-#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
-#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */
-#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */
-#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */
-#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */
-#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
-#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */
-#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */
-#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */
-#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */
-#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
-#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */
-#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */
-#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */
-#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */
-#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
-#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */
-#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */
-#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */
-#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */
-#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
-#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */
-#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */
-#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */
-#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */
-#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
-#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */
-#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */
-#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */
-#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */
-#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
-#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */
-
-/* Bit fields for PRS SWLEVEL */
-#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */
-#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */
-#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */
-#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */
-#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */
-#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
-#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
-#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */
-#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */
-#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */
-#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
-#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
-#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */
-#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */
-#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */
-#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
-#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
-#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */
-#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */
-#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */
-#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
-#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
-#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */
-#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */
-#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */
-#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
-#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
-#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */
-#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */
-#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */
-#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
-#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
-#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */
-#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */
-#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */
-#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
-#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
-#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */
-#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */
-#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */
-#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
-#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
-#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */
-#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */
-#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */
-#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
-#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
-#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */
-#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */
-#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */
-#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
-#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
-#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */
-#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */
-#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */
-#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
-#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
-#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */
-#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */
-#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */
-#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
-#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
-
-/* Bit fields for PRS ROUTEPEN */
-#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */
-#define _PRS_ROUTEPEN_MASK 0x00000FFFUL /**< Mask for PRS_ROUTEPEN */
-#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */
-#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */
-#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */
-#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */
-#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
-#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */
-#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */
-#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */
-#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */
-#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
-#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */
-#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */
-#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */
-#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */
-#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
-#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */
-#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */
-#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */
-#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */
-#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
-#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */
-#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */
-#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */
-#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */
-#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
-#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */
-#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */
-#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */
-#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */
-#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
-#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */
-#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */
-#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */
-#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */
-#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
-#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */
-#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */
-#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */
-#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */
-#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
-#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */
-#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */
-#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */
-#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */
-#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
-#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */
-#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */
-#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */
-#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */
-#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
-#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */
-#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */
-#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */
-#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */
-#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
-#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */
-#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */
-#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */
-#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */
-#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
-
-/* Bit fields for PRS ROUTELOC0 */
-#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_MASK 0x0F07070FUL /**< Mask for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */
-#define _PRS_ROUTELOC0_CH0LOC_MASK 0xFUL /**< Bit mask for PRS_CH0LOC */
-#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH0LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH0LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH0LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH0LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH0LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH0LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH0LOC_LOC4 (_PRS_ROUTELOC0_CH0LOC_LOC4 << 0) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH0LOC_LOC5 (_PRS_ROUTELOC0_CH0LOC_LOC5 << 0) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH0LOC_LOC6 (_PRS_ROUTELOC0_CH0LOC_LOC6 << 0) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH0LOC_LOC7 (_PRS_ROUTELOC0_CH0LOC_LOC7 << 0) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH0LOC_LOC8 (_PRS_ROUTELOC0_CH0LOC_LOC8 << 0) /**< Shifted mode LOC8 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH0LOC_LOC9 (_PRS_ROUTELOC0_CH0LOC_LOC9 << 0) /**< Shifted mode LOC9 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH0LOC_LOC10 (_PRS_ROUTELOC0_CH0LOC_LOC10 << 0) /**< Shifted mode LOC10 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH0LOC_LOC11 (_PRS_ROUTELOC0_CH0LOC_LOC11 << 0) /**< Shifted mode LOC11 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH0LOC_LOC12 (_PRS_ROUTELOC0_CH0LOC_LOC12 << 0) /**< Shifted mode LOC12 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH0LOC_LOC13 (_PRS_ROUTELOC0_CH0LOC_LOC13 << 0) /**< Shifted mode LOC13 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */
-#define _PRS_ROUTELOC0_CH1LOC_MASK 0x700UL /**< Bit mask for PRS_CH1LOC */
-#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH1LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH1LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH1LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH1LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH1LOC_LOC4 (_PRS_ROUTELOC0_CH1LOC_LOC4 << 8) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH1LOC_LOC5 (_PRS_ROUTELOC0_CH1LOC_LOC5 << 8) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH1LOC_LOC6 (_PRS_ROUTELOC0_CH1LOC_LOC6 << 8) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH1LOC_LOC7 (_PRS_ROUTELOC0_CH1LOC_LOC7 << 8) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */
-#define _PRS_ROUTELOC0_CH2LOC_MASK 0x70000UL /**< Bit mask for PRS_CH2LOC */
-#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH2LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH2LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH2LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH2LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH2LOC_LOC4 (_PRS_ROUTELOC0_CH2LOC_LOC4 << 16) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH2LOC_LOC5 (_PRS_ROUTELOC0_CH2LOC_LOC5 << 16) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH2LOC_LOC6 (_PRS_ROUTELOC0_CH2LOC_LOC6 << 16) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH2LOC_LOC7 (_PRS_ROUTELOC0_CH2LOC_LOC7 << 16) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */
-#define _PRS_ROUTELOC0_CH3LOC_MASK 0xF000000UL /**< Bit mask for PRS_CH3LOC */
-#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH3LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH3LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH3LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH3LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH3LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH3LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC0 */
-#define _PRS_ROUTELOC0_CH3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH3LOC_LOC4 (_PRS_ROUTELOC0_CH3LOC_LOC4 << 24) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH3LOC_LOC5 (_PRS_ROUTELOC0_CH3LOC_LOC5 << 24) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH3LOC_LOC6 (_PRS_ROUTELOC0_CH3LOC_LOC6 << 24) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH3LOC_LOC7 (_PRS_ROUTELOC0_CH3LOC_LOC7 << 24) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH3LOC_LOC8 (_PRS_ROUTELOC0_CH3LOC_LOC8 << 24) /**< Shifted mode LOC8 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH3LOC_LOC9 (_PRS_ROUTELOC0_CH3LOC_LOC9 << 24) /**< Shifted mode LOC9 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH3LOC_LOC10 (_PRS_ROUTELOC0_CH3LOC_LOC10 << 24) /**< Shifted mode LOC10 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH3LOC_LOC11 (_PRS_ROUTELOC0_CH3LOC_LOC11 << 24) /**< Shifted mode LOC11 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH3LOC_LOC12 (_PRS_ROUTELOC0_CH3LOC_LOC12 << 24) /**< Shifted mode LOC12 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH3LOC_LOC13 (_PRS_ROUTELOC0_CH3LOC_LOC13 << 24) /**< Shifted mode LOC13 for PRS_ROUTELOC0 */
-#define PRS_ROUTELOC0_CH3LOC_LOC14 (_PRS_ROUTELOC0_CH3LOC_LOC14 << 24) /**< Shifted mode LOC14 for PRS_ROUTELOC0 */
-
-/* Bit fields for PRS ROUTELOC1 */
-#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_MASK 0x0F1F0707UL /**< Mask for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */
-#define _PRS_ROUTELOC1_CH4LOC_MASK 0x7UL /**< Bit mask for PRS_CH4LOC */
-#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH4LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH4LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH4LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH4LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH4LOC_LOC3 (_PRS_ROUTELOC1_CH4LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH4LOC_LOC4 (_PRS_ROUTELOC1_CH4LOC_LOC4 << 0) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH4LOC_LOC5 (_PRS_ROUTELOC1_CH4LOC_LOC5 << 0) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH4LOC_LOC6 (_PRS_ROUTELOC1_CH4LOC_LOC6 << 0) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */
-#define _PRS_ROUTELOC1_CH5LOC_MASK 0x700UL /**< Bit mask for PRS_CH5LOC */
-#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH5LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH5LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH5LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH5LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH5LOC_LOC3 (_PRS_ROUTELOC1_CH5LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH5LOC_LOC4 (_PRS_ROUTELOC1_CH5LOC_LOC4 << 8) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH5LOC_LOC5 (_PRS_ROUTELOC1_CH5LOC_LOC5 << 8) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH5LOC_LOC6 (_PRS_ROUTELOC1_CH5LOC_LOC6 << 8) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */
-#define _PRS_ROUTELOC1_CH6LOC_MASK 0x1F0000UL /**< Bit mask for PRS_CH6LOC */
-#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH6LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH6LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH6LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH6LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH6LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH6LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH6LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH6LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH6LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH6LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH6LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH6LOC_LOC14 0x0000000EUL /**< Mode LOC14 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH6LOC_LOC15 0x0000000FUL /**< Mode LOC15 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH6LOC_LOC16 0x00000010UL /**< Mode LOC16 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH6LOC_LOC17 0x00000011UL /**< Mode LOC17 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH6LOC_LOC3 (_PRS_ROUTELOC1_CH6LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH6LOC_LOC4 (_PRS_ROUTELOC1_CH6LOC_LOC4 << 16) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH6LOC_LOC5 (_PRS_ROUTELOC1_CH6LOC_LOC5 << 16) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH6LOC_LOC6 (_PRS_ROUTELOC1_CH6LOC_LOC6 << 16) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH6LOC_LOC7 (_PRS_ROUTELOC1_CH6LOC_LOC7 << 16) /**< Shifted mode LOC7 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH6LOC_LOC8 (_PRS_ROUTELOC1_CH6LOC_LOC8 << 16) /**< Shifted mode LOC8 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH6LOC_LOC9 (_PRS_ROUTELOC1_CH6LOC_LOC9 << 16) /**< Shifted mode LOC9 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH6LOC_LOC10 (_PRS_ROUTELOC1_CH6LOC_LOC10 << 16) /**< Shifted mode LOC10 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH6LOC_LOC11 (_PRS_ROUTELOC1_CH6LOC_LOC11 << 16) /**< Shifted mode LOC11 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH6LOC_LOC12 (_PRS_ROUTELOC1_CH6LOC_LOC12 << 16) /**< Shifted mode LOC12 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH6LOC_LOC13 (_PRS_ROUTELOC1_CH6LOC_LOC13 << 16) /**< Shifted mode LOC13 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH6LOC_LOC14 (_PRS_ROUTELOC1_CH6LOC_LOC14 << 16) /**< Shifted mode LOC14 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH6LOC_LOC15 (_PRS_ROUTELOC1_CH6LOC_LOC15 << 16) /**< Shifted mode LOC15 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH6LOC_LOC16 (_PRS_ROUTELOC1_CH6LOC_LOC16 << 16) /**< Shifted mode LOC16 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH6LOC_LOC17 (_PRS_ROUTELOC1_CH6LOC_LOC17 << 16) /**< Shifted mode LOC17 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */
-#define _PRS_ROUTELOC1_CH7LOC_MASK 0xF000000UL /**< Bit mask for PRS_CH7LOC */
-#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH7LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH7LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH7LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH7LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH7LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH7LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH7LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC1 */
-#define _PRS_ROUTELOC1_CH7LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH7LOC_LOC3 (_PRS_ROUTELOC1_CH7LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH7LOC_LOC4 (_PRS_ROUTELOC1_CH7LOC_LOC4 << 24) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH7LOC_LOC5 (_PRS_ROUTELOC1_CH7LOC_LOC5 << 24) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH7LOC_LOC6 (_PRS_ROUTELOC1_CH7LOC_LOC6 << 24) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH7LOC_LOC7 (_PRS_ROUTELOC1_CH7LOC_LOC7 << 24) /**< Shifted mode LOC7 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH7LOC_LOC8 (_PRS_ROUTELOC1_CH7LOC_LOC8 << 24) /**< Shifted mode LOC8 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH7LOC_LOC9 (_PRS_ROUTELOC1_CH7LOC_LOC9 << 24) /**< Shifted mode LOC9 for PRS_ROUTELOC1 */
-#define PRS_ROUTELOC1_CH7LOC_LOC10 (_PRS_ROUTELOC1_CH7LOC_LOC10 << 24) /**< Shifted mode LOC10 for PRS_ROUTELOC1 */
-
-/* Bit fields for PRS ROUTELOC2 */
-#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_MASK 0x07071F0FUL /**< Mask for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */
-#define _PRS_ROUTELOC2_CH8LOC_MASK 0xFUL /**< Bit mask for PRS_CH8LOC */
-#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH8LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH8LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH8LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH8LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH8LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH8LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH8LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH8LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH8LOC_LOC3 (_PRS_ROUTELOC2_CH8LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH8LOC_LOC4 (_PRS_ROUTELOC2_CH8LOC_LOC4 << 0) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH8LOC_LOC5 (_PRS_ROUTELOC2_CH8LOC_LOC5 << 0) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH8LOC_LOC6 (_PRS_ROUTELOC2_CH8LOC_LOC6 << 0) /**< Shifted mode LOC6 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH8LOC_LOC7 (_PRS_ROUTELOC2_CH8LOC_LOC7 << 0) /**< Shifted mode LOC7 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH8LOC_LOC8 (_PRS_ROUTELOC2_CH8LOC_LOC8 << 0) /**< Shifted mode LOC8 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH8LOC_LOC9 (_PRS_ROUTELOC2_CH8LOC_LOC9 << 0) /**< Shifted mode LOC9 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH8LOC_LOC10 (_PRS_ROUTELOC2_CH8LOC_LOC10 << 0) /**< Shifted mode LOC10 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */
-#define _PRS_ROUTELOC2_CH9LOC_MASK 0x1F00UL /**< Bit mask for PRS_CH9LOC */
-#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH9LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH9LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH9LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH9LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH9LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH9LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH9LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH9LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH9LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH9LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH9LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH9LOC_LOC14 0x0000000EUL /**< Mode LOC14 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH9LOC_LOC15 0x0000000FUL /**< Mode LOC15 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH9LOC_LOC16 0x00000010UL /**< Mode LOC16 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH9LOC_LOC3 (_PRS_ROUTELOC2_CH9LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH9LOC_LOC4 (_PRS_ROUTELOC2_CH9LOC_LOC4 << 8) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH9LOC_LOC5 (_PRS_ROUTELOC2_CH9LOC_LOC5 << 8) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH9LOC_LOC6 (_PRS_ROUTELOC2_CH9LOC_LOC6 << 8) /**< Shifted mode LOC6 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH9LOC_LOC7 (_PRS_ROUTELOC2_CH9LOC_LOC7 << 8) /**< Shifted mode LOC7 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH9LOC_LOC8 (_PRS_ROUTELOC2_CH9LOC_LOC8 << 8) /**< Shifted mode LOC8 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH9LOC_LOC9 (_PRS_ROUTELOC2_CH9LOC_LOC9 << 8) /**< Shifted mode LOC9 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH9LOC_LOC10 (_PRS_ROUTELOC2_CH9LOC_LOC10 << 8) /**< Shifted mode LOC10 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH9LOC_LOC11 (_PRS_ROUTELOC2_CH9LOC_LOC11 << 8) /**< Shifted mode LOC11 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH9LOC_LOC12 (_PRS_ROUTELOC2_CH9LOC_LOC12 << 8) /**< Shifted mode LOC12 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH9LOC_LOC13 (_PRS_ROUTELOC2_CH9LOC_LOC13 << 8) /**< Shifted mode LOC13 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH9LOC_LOC14 (_PRS_ROUTELOC2_CH9LOC_LOC14 << 8) /**< Shifted mode LOC14 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH9LOC_LOC15 (_PRS_ROUTELOC2_CH9LOC_LOC15 << 8) /**< Shifted mode LOC15 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH9LOC_LOC16 (_PRS_ROUTELOC2_CH9LOC_LOC16 << 8) /**< Shifted mode LOC16 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */
-#define _PRS_ROUTELOC2_CH10LOC_MASK 0x70000UL /**< Bit mask for PRS_CH10LOC */
-#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH10LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH10LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH10LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH10LOC_LOC3 (_PRS_ROUTELOC2_CH10LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH10LOC_LOC4 (_PRS_ROUTELOC2_CH10LOC_LOC4 << 16) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH10LOC_LOC5 (_PRS_ROUTELOC2_CH10LOC_LOC5 << 16) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */
-#define _PRS_ROUTELOC2_CH11LOC_MASK 0x7000000UL /**< Bit mask for PRS_CH11LOC */
-#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH11LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH11LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */
-#define _PRS_ROUTELOC2_CH11LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH11LOC_LOC3 (_PRS_ROUTELOC2_CH11LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH11LOC_LOC4 (_PRS_ROUTELOC2_CH11LOC_LOC4 << 24) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */
-#define PRS_ROUTELOC2_CH11LOC_LOC5 (_PRS_ROUTELOC2_CH11LOC_LOC5 << 24) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */
-
-/* Bit fields for PRS CTRL */
-#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */
-#define _PRS_CTRL_MASK 0x0000001FUL /**< Mask for PRS_CTRL */
-#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */
-#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */
-#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */
-#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */
-#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */
-#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */
-#define _PRS_CTRL_SEVONPRSSEL_MASK 0x1EUL /**< Bit mask for PRS_SEVONPRSSEL */
-#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */
-#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */
-#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */
-#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */
-#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */
-#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */
-#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */
-#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */
-#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */
-#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */
-#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */
-#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */
-#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */
-#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */
-#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */
-#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */
-#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */
-#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */
-#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */
-#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */
-#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */
-#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */
-#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */
-#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */
-#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */
-#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */
-
-/* Bit fields for PRS DMAREQ0 */
-#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */
-#define _PRS_DMAREQ0_MASK 0x000003C0UL /**< Mask for PRS_DMAREQ0 */
-#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */
-#define _PRS_DMAREQ0_PRSSEL_MASK 0x3C0UL /**< Bit mask for PRS_PRSSEL */
-#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */
-#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */
-#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */
-#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */
-#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */
-#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */
-#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */
-#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */
-#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */
-#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */
-#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */
-#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */
-#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */
-#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */
-#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */
-#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */
-#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */
-#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */
-#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */
-#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */
-#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */
-#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */
-#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */
-#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */
-#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */
-#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */
-
-/* Bit fields for PRS DMAREQ1 */
-#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */
-#define _PRS_DMAREQ1_MASK 0x000003C0UL /**< Mask for PRS_DMAREQ1 */
-#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */
-#define _PRS_DMAREQ1_PRSSEL_MASK 0x3C0UL /**< Bit mask for PRS_PRSSEL */
-#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */
-#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */
-#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */
-#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */
-#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */
-#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */
-#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */
-#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */
-#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */
-#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */
-#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */
-#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */
-#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */
-#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */
-#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */
-#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */
-#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */
-#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */
-#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */
-#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */
-#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */
-#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */
-#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */
-#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */
-#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */
-#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */
-
-/* Bit fields for PRS PEEK */
-#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */
-#define _PRS_PEEK_MASK 0x00000FFFUL /**< Mask for PRS_PEEK */
-#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */
-#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */
-#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */
-#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */
-#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */
-#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */
-#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */
-#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */
-#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */
-#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */
-#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */
-#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */
-#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */
-#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */
-#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */
-#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */
-#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */
-#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */
-#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */
-#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */
-#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */
-#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */
-#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */
-#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */
-#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */
-#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */
-#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */
-#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */
-#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */
-#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */
-#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */
-#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */
-#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */
-#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */
-#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */
-#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */
-#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */
-#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */
-#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */
-#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */
-#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */
-#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */
-#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */
-#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */
-#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */
-#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */
-#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */
-#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */
-#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */
-#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */
-#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */
-#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */
-#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */
-#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */
-#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */
-#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */
-#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */
-#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */
-#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */
-#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */
-
-/* Bit fields for PRS CH_CTRL */
-#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */
-#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */
-#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */
-#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */
-#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000002UL /**< Mode PRSH for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000003UL /**< Mode ACMP0 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000004UL /**< Mode ACMP1 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000005UL /**< Mode ADC0 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000007UL /**< Mode LESENSEL for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000008UL /**< Mode LESENSEH for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x00000009UL /**< Mode LESENSED for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000000AUL /**< Mode LESENSE for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x0000000BUL /**< Mode RTCC for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x0000000CUL /**< Mode GPIOL for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000DUL /**< Mode GPIOH for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000EUL /**< Mode LETIMER0 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000FUL /**< Mode PCNT0 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000012UL /**< Mode CMU for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000018UL /**< Mode VDAC0 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x0000001AUL /**< Mode CRYOTIMER for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x0000003EUL /**< Mode WTIMER0 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */
-#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */
-#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */
-#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */
-#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */
-#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
-#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */
-#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */
-#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */
-#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */
-#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */
-#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */
-#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */
-#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */
-#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
-#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */
-#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */
-#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */
-#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */
-#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
-#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */
-#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */
-#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */
-#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */
-#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
-#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */
-#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */
-#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */
-#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */
-#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
-#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */
-#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */
-#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */
-#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */
-#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
-
-/** @} */
-/** @} End of group EFR32FG13P_PRS */
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_prs_ch.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_prs_ch.h
deleted file mode 100644
index 64e1204d..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_prs_ch.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_prs_ch.h
- * @brief EFR32FG13P_PRS_CH register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @brief PRS_CH PRS CH Register
- * @ingroup EFR32FG13P_PRS
- *****************************************************************************/
-typedef struct {
- __IOM uint32_t CTRL; /**< Channel Control Register */
-} PRS_CH_TypeDef;
-
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_prs_signals.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_prs_signals.h
deleted file mode 100644
index 312c3af6..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_prs_signals.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_prs_signals.h
- * @brief EFR32FG13P_PRS_SIGNALS register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_PRS
- * @{
- * @addtogroup EFR32FG13P_PRS_Signals PRS Signals
- * @{
- * @brief PRS Signal names
- *****************************************************************************/
-#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */
-#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */
-#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */
-#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */
-#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */
-#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */
-#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */
-#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */
-#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */
-#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */
-#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */
-#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */
-#define PRS_ACMP0_OUT ((3 << 8) + 0) /**< PRS Analog comparator output */
-#define PRS_ACMP1_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */
-#define PRS_ADC0_SINGLE ((5 << 8) + 0) /**< PRS ADC single conversion done */
-#define PRS_ADC0_SCAN ((5 << 8) + 1) /**< PRS ADC scan conversion done */
-#define PRS_LESENSE_SCANRES0 ((7 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */
-#define PRS_LESENSE_SCANRES1 ((7 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */
-#define PRS_LESENSE_SCANRES2 ((7 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */
-#define PRS_LESENSE_SCANRES3 ((7 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */
-#define PRS_LESENSE_SCANRES4 ((7 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */
-#define PRS_LESENSE_SCANRES5 ((7 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */
-#define PRS_LESENSE_SCANRES6 ((7 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */
-#define PRS_LESENSE_SCANRES7 ((7 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */
-#define PRS_LESENSE_SCANRES8 ((8 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */
-#define PRS_LESENSE_SCANRES9 ((8 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */
-#define PRS_LESENSE_SCANRES10 ((8 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */
-#define PRS_LESENSE_SCANRES11 ((8 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */
-#define PRS_LESENSE_SCANRES12 ((8 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */
-#define PRS_LESENSE_SCANRES13 ((8 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */
-#define PRS_LESENSE_SCANRES14 ((8 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */
-#define PRS_LESENSE_SCANRES15 ((8 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */
-#define PRS_LESENSE_DEC0 ((9 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */
-#define PRS_LESENSE_DEC1 ((9 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */
-#define PRS_LESENSE_DEC2 ((9 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */
-#define PRS_LESENSE_DECCMP ((9 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */
-#define PRS_LESENSE_MEASACT ((10 << 8) + 0) /**< PRS LESENSE Measurement active */
-#define PRS_RTCC_CCV0 ((11 << 8) + 1) /**< PRS RTCC Compare 0 */
-#define PRS_RTCC_CCV1 ((11 << 8) + 2) /**< PRS RTCC Compare 1 */
-#define PRS_RTCC_CCV2 ((11 << 8) + 3) /**< PRS RTCC Compare 2 */
-#define PRS_GPIO_PIN0 ((12 << 8) + 0) /**< PRS GPIO pin 0 */
-#define PRS_GPIO_PIN1 ((12 << 8) + 1) /**< PRS GPIO pin 1 */
-#define PRS_GPIO_PIN2 ((12 << 8) + 2) /**< PRS GPIO pin 2 */
-#define PRS_GPIO_PIN3 ((12 << 8) + 3) /**< PRS GPIO pin 3 */
-#define PRS_GPIO_PIN4 ((12 << 8) + 4) /**< PRS GPIO pin 4 */
-#define PRS_GPIO_PIN5 ((12 << 8) + 5) /**< PRS GPIO pin 5 */
-#define PRS_GPIO_PIN6 ((12 << 8) + 6) /**< PRS GPIO pin 6 */
-#define PRS_GPIO_PIN7 ((12 << 8) + 7) /**< PRS GPIO pin 7 */
-#define PRS_GPIO_PIN8 ((13 << 8) + 0) /**< PRS GPIO pin 8 */
-#define PRS_GPIO_PIN9 ((13 << 8) + 1) /**< PRS GPIO pin 9 */
-#define PRS_GPIO_PIN10 ((13 << 8) + 2) /**< PRS GPIO pin 10 */
-#define PRS_GPIO_PIN11 ((13 << 8) + 3) /**< PRS GPIO pin 11 */
-#define PRS_GPIO_PIN12 ((13 << 8) + 4) /**< PRS GPIO pin 12 */
-#define PRS_GPIO_PIN13 ((13 << 8) + 5) /**< PRS GPIO pin 13 */
-#define PRS_GPIO_PIN14 ((13 << 8) + 6) /**< PRS GPIO pin 14 */
-#define PRS_GPIO_PIN15 ((13 << 8) + 7) /**< PRS GPIO pin 15 */
-#define PRS_LETIMER0_CH0 ((14 << 8) + 0) /**< PRS LETIMER CH0 Out */
-#define PRS_LETIMER0_CH1 ((14 << 8) + 1) /**< PRS LETIMER CH1 Out */
-#define PRS_PCNT0_TCC ((15 << 8) + 0) /**< PRS PCNT0 Triggered compare match */
-#define PRS_PCNT0_UFOF ((15 << 8) + 1) /**< PRS PCNT0 Counter overflow or underflow */
-#define PRS_PCNT0_DIR ((15 << 8) + 2) /**< PRS PCNT0 Counter direction */
-#define PRS_CMU_CLKOUT0 ((18 << 8) + 0) /**< PRS Clock Output 0 */
-#define PRS_CMU_CLKOUT1 ((18 << 8) + 1) /**< PRS Clock Output 1 */
-#define PRS_VDAC0_CH0 ((24 << 8) + 0) /**< PRS DAC ch0 conversion done */
-#define PRS_VDAC0_CH1 ((24 << 8) + 1) /**< PRS DAC ch1 conversion done */
-#define PRS_VDAC0_OPA0 ((24 << 8) + 2) /**< PRS OPA0 warmedup or outputvalid based on OPA0PRSOUTMODE mode in OPACTRL. */
-#define PRS_VDAC0_OPA1 ((24 << 8) + 3) /**< PRS OPA1 warmedup or outputvalid based on OPA1PRSOUTMODE mode in OPACTRL. */
-#define PRS_VDAC0_OPA2 ((24 << 8) + 4) /**< PRS OPA2 warmedup or outputvalid based on OPA2PRSOUTMODE mode in OPACTRL. */
-#define PRS_RFSENSE_WU ((25 << 8) + 0) /**< PRS RFSENSE Output */
-#define PRS_CRYOTIMER_PERIOD ((26 << 8) + 0) /**< PRS CRYOTIMER Output */
-#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS USART 0 IRDA out */
-#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS USART 0 TX complete */
-#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS USART 0 RX Data Valid */
-#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS USART 0 RTS */
-#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS USART 0 TX */
-#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS USART 0 CS */
-#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS USART 1 TX complete */
-#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS USART 1 RX Data Valid */
-#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS USART 1 RTS */
-#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS USART 1 TX */
-#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS USART 1 CS */
-#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */
-#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS USART 2 TX complete */
-#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS USART 2 RX Data Valid */
-#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS USART 2 RTS */
-#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS USART 2 TX */
-#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS USART 2 CS */
-#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS Timer 0 Underflow */
-#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS Timer 0 Overflow */
-#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS Timer 0 Compare/Capture 0 */
-#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS Timer 0 Compare/Capture 1 */
-#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS Timer 0 Compare/Capture 2 */
-#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS Timer 1 Underflow */
-#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS Timer 1 Overflow */
-#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS Timer 1 Compare/Capture 0 */
-#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS Timer 1 Compare/Capture 1 */
-#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS Timer 1 Compare/Capture 2 */
-#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS Timer 1 Compare/Capture 3 */
-#define PRS_WTIMER0_UF ((62 << 8) + 0) /**< PRS Timer 2 Underflow */
-#define PRS_WTIMER0_OF ((62 << 8) + 1) /**< PRS Timer 2 Overflow */
-#define PRS_WTIMER0_CC0 ((62 << 8) + 2) /**< PRS Timer 2 Compare/Capture 0 */
-#define PRS_WTIMER0_CC1 ((62 << 8) + 3) /**< PRS Timer 2 Compare/Capture 1 */
-#define PRS_WTIMER0_CC2 ((62 << 8) + 4) /**< PRS Timer 2 Compare/Capture 2 */
-#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */
-#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */
-#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */
-#define PRS_RAC_ACTIVE ((81 << 8) + 0) /**< PRS RAC is active */
-#define PRS_RAC_TX ((81 << 8) + 1) /**< PRS RAC is in TX */
-#define PRS_RAC_RX ((81 << 8) + 2) /**< PRS RAC is in RX */
-#define PRS_RAC_LNAEN ((81 << 8) + 3) /**< PRS LNA enable */
-#define PRS_RAC_PAEN ((81 << 8) + 4) /**< PRS PA enable */
-#define PRS_PROTIMER_LBTS ((84 << 8) + 5) /**< PRS Listen Before Talk Success */
-#define PRS_PROTIMER_LBTR ((84 << 8) + 6) /**< PRS Listen Before Talk Retry */
-#define PRS_PROTIMER_LBTF ((84 << 8) + 7) /**< PRS Listen Before Talk Failure */
-#define PRS_MODEM_FRAMEDET ((86 << 8) + 0) /**< PRS Frame detected */
-#define PRS_MODEM_PREDET ((86 << 8) + 1) /**< PRS Receive preamble detected */
-#define PRS_MODEM_TIMDET ((86 << 8) + 2) /**< PRS Receive timing detected */
-#define PRS_MODEM_FRAMESENT ((86 << 8) + 3) /**< PRS Entire frame transmitted */
-#define PRS_MODEM_SYNCSENT ((86 << 8) + 4) /**< PRS Syncword transmitted */
-#define PRS_MODEM_PRESENT ((86 << 8) + 5) /**< PRS Preamble transmitted */
-
-/** @} */
-/** @} End of group EFR32FG13P_PRS */
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_rmu.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_rmu.h
deleted file mode 100644
index 0f7b908b..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_rmu.h
+++ /dev/null
@@ -1,200 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_rmu.h
- * @brief EFR32FG13P_RMU register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P_RMU RMU
- * @{
- * @brief EFR32FG13P_RMU Register Declaration
- *****************************************************************************/
-/** RMU Register Declaration */
-typedef struct {
- __IOM uint32_t CTRL; /**< Control Register */
- __IM uint32_t RSTCAUSE; /**< Reset Cause Register */
- __IOM uint32_t CMD; /**< Command Register */
- __IOM uint32_t RST; /**< Reset Control Register */
- __IOM uint32_t LOCK; /**< Configuration Lock Register */
-} RMU_TypeDef; /** @} */
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_RMU
- * @{
- * @defgroup EFR32FG13P_RMU_BitFields RMU Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for RMU CTRL */
-#define _RMU_CTRL_RESETVALUE 0x00004204UL /**< Default value for RMU_CTRL */
-#define _RMU_CTRL_MASK 0x03007777UL /**< Mask for RMU_CTRL */
-#define _RMU_CTRL_WDOGRMODE_SHIFT 0 /**< Shift value for RMU_WDOGRMODE */
-#define _RMU_CTRL_WDOGRMODE_MASK 0x7UL /**< Bit mask for RMU_WDOGRMODE */
-#define _RMU_CTRL_WDOGRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */
-#define _RMU_CTRL_WDOGRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */
-#define _RMU_CTRL_WDOGRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */
-#define _RMU_CTRL_WDOGRMODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for RMU_CTRL */
-#define _RMU_CTRL_WDOGRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */
-#define RMU_CTRL_WDOGRMODE_DISABLED (_RMU_CTRL_WDOGRMODE_DISABLED << 0) /**< Shifted mode DISABLED for RMU_CTRL */
-#define RMU_CTRL_WDOGRMODE_LIMITED (_RMU_CTRL_WDOGRMODE_LIMITED << 0) /**< Shifted mode LIMITED for RMU_CTRL */
-#define RMU_CTRL_WDOGRMODE_EXTENDED (_RMU_CTRL_WDOGRMODE_EXTENDED << 0) /**< Shifted mode EXTENDED for RMU_CTRL */
-#define RMU_CTRL_WDOGRMODE_DEFAULT (_RMU_CTRL_WDOGRMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CTRL */
-#define RMU_CTRL_WDOGRMODE_FULL (_RMU_CTRL_WDOGRMODE_FULL << 0) /**< Shifted mode FULL for RMU_CTRL */
-#define _RMU_CTRL_LOCKUPRMODE_SHIFT 4 /**< Shift value for RMU_LOCKUPRMODE */
-#define _RMU_CTRL_LOCKUPRMODE_MASK 0x70UL /**< Bit mask for RMU_LOCKUPRMODE */
-#define _RMU_CTRL_LOCKUPRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */
-#define _RMU_CTRL_LOCKUPRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */
-#define _RMU_CTRL_LOCKUPRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */
-#define _RMU_CTRL_LOCKUPRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */
-#define _RMU_CTRL_LOCKUPRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */
-#define RMU_CTRL_LOCKUPRMODE_DEFAULT (_RMU_CTRL_LOCKUPRMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_CTRL */
-#define RMU_CTRL_LOCKUPRMODE_DISABLED (_RMU_CTRL_LOCKUPRMODE_DISABLED << 4) /**< Shifted mode DISABLED for RMU_CTRL */
-#define RMU_CTRL_LOCKUPRMODE_LIMITED (_RMU_CTRL_LOCKUPRMODE_LIMITED << 4) /**< Shifted mode LIMITED for RMU_CTRL */
-#define RMU_CTRL_LOCKUPRMODE_EXTENDED (_RMU_CTRL_LOCKUPRMODE_EXTENDED << 4) /**< Shifted mode EXTENDED for RMU_CTRL */
-#define RMU_CTRL_LOCKUPRMODE_FULL (_RMU_CTRL_LOCKUPRMODE_FULL << 4) /**< Shifted mode FULL for RMU_CTRL */
-#define _RMU_CTRL_SYSRMODE_SHIFT 8 /**< Shift value for RMU_SYSRMODE */
-#define _RMU_CTRL_SYSRMODE_MASK 0x700UL /**< Bit mask for RMU_SYSRMODE */
-#define _RMU_CTRL_SYSRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */
-#define _RMU_CTRL_SYSRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */
-#define _RMU_CTRL_SYSRMODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for RMU_CTRL */
-#define _RMU_CTRL_SYSRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */
-#define _RMU_CTRL_SYSRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */
-#define RMU_CTRL_SYSRMODE_DISABLED (_RMU_CTRL_SYSRMODE_DISABLED << 8) /**< Shifted mode DISABLED for RMU_CTRL */
-#define RMU_CTRL_SYSRMODE_LIMITED (_RMU_CTRL_SYSRMODE_LIMITED << 8) /**< Shifted mode LIMITED for RMU_CTRL */
-#define RMU_CTRL_SYSRMODE_DEFAULT (_RMU_CTRL_SYSRMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for RMU_CTRL */
-#define RMU_CTRL_SYSRMODE_EXTENDED (_RMU_CTRL_SYSRMODE_EXTENDED << 8) /**< Shifted mode EXTENDED for RMU_CTRL */
-#define RMU_CTRL_SYSRMODE_FULL (_RMU_CTRL_SYSRMODE_FULL << 8) /**< Shifted mode FULL for RMU_CTRL */
-#define _RMU_CTRL_PINRMODE_SHIFT 12 /**< Shift value for RMU_PINRMODE */
-#define _RMU_CTRL_PINRMODE_MASK 0x7000UL /**< Bit mask for RMU_PINRMODE */
-#define _RMU_CTRL_PINRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */
-#define _RMU_CTRL_PINRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */
-#define _RMU_CTRL_PINRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */
-#define _RMU_CTRL_PINRMODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for RMU_CTRL */
-#define _RMU_CTRL_PINRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */
-#define RMU_CTRL_PINRMODE_DISABLED (_RMU_CTRL_PINRMODE_DISABLED << 12) /**< Shifted mode DISABLED for RMU_CTRL */
-#define RMU_CTRL_PINRMODE_LIMITED (_RMU_CTRL_PINRMODE_LIMITED << 12) /**< Shifted mode LIMITED for RMU_CTRL */
-#define RMU_CTRL_PINRMODE_EXTENDED (_RMU_CTRL_PINRMODE_EXTENDED << 12) /**< Shifted mode EXTENDED for RMU_CTRL */
-#define RMU_CTRL_PINRMODE_DEFAULT (_RMU_CTRL_PINRMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for RMU_CTRL */
-#define RMU_CTRL_PINRMODE_FULL (_RMU_CTRL_PINRMODE_FULL << 12) /**< Shifted mode FULL for RMU_CTRL */
-#define _RMU_CTRL_RESETSTATE_SHIFT 24 /**< Shift value for RMU_RESETSTATE */
-#define _RMU_CTRL_RESETSTATE_MASK 0x3000000UL /**< Bit mask for RMU_RESETSTATE */
-#define _RMU_CTRL_RESETSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */
-#define RMU_CTRL_RESETSTATE_DEFAULT (_RMU_CTRL_RESETSTATE_DEFAULT << 24) /**< Shifted mode DEFAULT for RMU_CTRL */
-
-/* Bit fields for RMU RSTCAUSE */
-#define _RMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for RMU_RSTCAUSE */
-#define _RMU_RSTCAUSE_MASK 0x00010F1DUL /**< Mask for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_PORST (0x1UL << 0) /**< Power on Reset */
-#define _RMU_RSTCAUSE_PORST_SHIFT 0 /**< Shift value for RMU_PORST */
-#define _RMU_RSTCAUSE_PORST_MASK 0x1UL /**< Bit mask for RMU_PORST */
-#define _RMU_RSTCAUSE_PORST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_PORST_DEFAULT (_RMU_RSTCAUSE_PORST_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_AVDDBOD (0x1UL << 2) /**< Brown Out Detector AVDD Reset */
-#define _RMU_RSTCAUSE_AVDDBOD_SHIFT 2 /**< Shift value for RMU_AVDDBOD */
-#define _RMU_RSTCAUSE_AVDDBOD_MASK 0x4UL /**< Bit mask for RMU_AVDDBOD */
-#define _RMU_RSTCAUSE_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_AVDDBOD_DEFAULT (_RMU_RSTCAUSE_AVDDBOD_DEFAULT << 2) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_DVDDBOD (0x1UL << 3) /**< Brown Out Detector DVDD Reset */
-#define _RMU_RSTCAUSE_DVDDBOD_SHIFT 3 /**< Shift value for RMU_DVDDBOD */
-#define _RMU_RSTCAUSE_DVDDBOD_MASK 0x8UL /**< Bit mask for RMU_DVDDBOD */
-#define _RMU_RSTCAUSE_DVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_DVDDBOD_DEFAULT (_RMU_RSTCAUSE_DVDDBOD_DEFAULT << 3) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_DECBOD (0x1UL << 4) /**< Brown Out Detector Decouple Domain Reset */
-#define _RMU_RSTCAUSE_DECBOD_SHIFT 4 /**< Shift value for RMU_DECBOD */
-#define _RMU_RSTCAUSE_DECBOD_MASK 0x10UL /**< Bit mask for RMU_DECBOD */
-#define _RMU_RSTCAUSE_DECBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_DECBOD_DEFAULT (_RMU_RSTCAUSE_DECBOD_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_EXTRST (0x1UL << 8) /**< External Pin Reset */
-#define _RMU_RSTCAUSE_EXTRST_SHIFT 8 /**< Shift value for RMU_EXTRST */
-#define _RMU_RSTCAUSE_EXTRST_MASK 0x100UL /**< Bit mask for RMU_EXTRST */
-#define _RMU_RSTCAUSE_EXTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_EXTRST_DEFAULT (_RMU_RSTCAUSE_EXTRST_DEFAULT << 8) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_LOCKUPRST (0x1UL << 9) /**< LOCKUP Reset */
-#define _RMU_RSTCAUSE_LOCKUPRST_SHIFT 9 /**< Shift value for RMU_LOCKUPRST */
-#define _RMU_RSTCAUSE_LOCKUPRST_MASK 0x200UL /**< Bit mask for RMU_LOCKUPRST */
-#define _RMU_RSTCAUSE_LOCKUPRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_LOCKUPRST_DEFAULT (_RMU_RSTCAUSE_LOCKUPRST_DEFAULT << 9) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_SYSREQRST (0x1UL << 10) /**< System Request Reset */
-#define _RMU_RSTCAUSE_SYSREQRST_SHIFT 10 /**< Shift value for RMU_SYSREQRST */
-#define _RMU_RSTCAUSE_SYSREQRST_MASK 0x400UL /**< Bit mask for RMU_SYSREQRST */
-#define _RMU_RSTCAUSE_SYSREQRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_SYSREQRST_DEFAULT (_RMU_RSTCAUSE_SYSREQRST_DEFAULT << 10) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_WDOGRST (0x1UL << 11) /**< Watchdog Reset */
-#define _RMU_RSTCAUSE_WDOGRST_SHIFT 11 /**< Shift value for RMU_WDOGRST */
-#define _RMU_RSTCAUSE_WDOGRST_MASK 0x800UL /**< Bit mask for RMU_WDOGRST */
-#define _RMU_RSTCAUSE_WDOGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_WDOGRST_DEFAULT (_RMU_RSTCAUSE_WDOGRST_DEFAULT << 11) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_EM4RST (0x1UL << 16) /**< EM4 Reset */
-#define _RMU_RSTCAUSE_EM4RST_SHIFT 16 /**< Shift value for RMU_EM4RST */
-#define _RMU_RSTCAUSE_EM4RST_MASK 0x10000UL /**< Bit mask for RMU_EM4RST */
-#define _RMU_RSTCAUSE_EM4RST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
-#define RMU_RSTCAUSE_EM4RST_DEFAULT (_RMU_RSTCAUSE_EM4RST_DEFAULT << 16) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
-
-/* Bit fields for RMU CMD */
-#define _RMU_CMD_RESETVALUE 0x00000000UL /**< Default value for RMU_CMD */
-#define _RMU_CMD_MASK 0x00000001UL /**< Mask for RMU_CMD */
-#define RMU_CMD_RCCLR (0x1UL << 0) /**< Reset Cause Clear */
-#define _RMU_CMD_RCCLR_SHIFT 0 /**< Shift value for RMU_RCCLR */
-#define _RMU_CMD_RCCLR_MASK 0x1UL /**< Bit mask for RMU_RCCLR */
-#define _RMU_CMD_RCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CMD */
-#define RMU_CMD_RCCLR_DEFAULT (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */
-
-/* Bit fields for RMU RST */
-#define _RMU_RST_RESETVALUE 0x00000000UL /**< Default value for RMU_RST */
-#define _RMU_RST_MASK 0x00000000UL /**< Mask for RMU_RST */
-
-/* Bit fields for RMU LOCK */
-#define _RMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for RMU_LOCK */
-#define _RMU_LOCK_MASK 0x0000FFFFUL /**< Mask for RMU_LOCK */
-#define _RMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RMU_LOCKKEY */
-#define _RMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RMU_LOCKKEY */
-#define _RMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_LOCK */
-#define _RMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RMU_LOCK */
-#define _RMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RMU_LOCK */
-#define _RMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RMU_LOCK */
-#define _RMU_LOCK_LOCKKEY_UNLOCK 0x0000E084UL /**< Mode UNLOCK for RMU_LOCK */
-#define RMU_LOCK_LOCKKEY_DEFAULT (_RMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_LOCK */
-#define RMU_LOCK_LOCKKEY_LOCK (_RMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RMU_LOCK */
-#define RMU_LOCK_LOCKKEY_UNLOCKED (_RMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RMU_LOCK */
-#define RMU_LOCK_LOCKKEY_LOCKED (_RMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RMU_LOCK */
-#define RMU_LOCK_LOCKKEY_UNLOCK (_RMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RMU_LOCK */
-
-/** @} */
-/** @} End of group EFR32FG13P_RMU */
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_rtcc.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_rtcc.h
deleted file mode 100644
index f9edf4fe..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_rtcc.h
+++ /dev/null
@@ -1,704 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_rtcc.h
- * @brief EFR32FG13P_RTCC register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P_RTCC RTCC
- * @{
- * @brief EFR32FG13P_RTCC Register Declaration
- *****************************************************************************/
-/** RTCC Register Declaration */
-typedef struct {
- __IOM uint32_t CTRL; /**< Control Register */
- __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */
- __IOM uint32_t CNT; /**< Counter Value Register */
- __IM uint32_t COMBCNT; /**< Combined Pre-Counter and Counter Value Register */
- __IOM uint32_t TIME; /**< Time of Day Register */
- __IOM uint32_t DATE; /**< Date Register */
- __IM uint32_t IF; /**< RTCC Interrupt Flags */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- __IM uint32_t STATUS; /**< Status Register */
- __IOM uint32_t CMD; /**< Command Register */
- __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
- __IOM uint32_t POWERDOWN; /**< Retention RAM Power-down Register */
- __IOM uint32_t LOCK; /**< Configuration Lock Register */
- __IOM uint32_t EM4WUEN; /**< Wake Up Enable */
-
- RTCC_CC_TypeDef CC[3]; /**< Capture/Compare Channel */
-
- uint32_t RESERVED0[37]; /**< Reserved registers */
- RTCC_RET_TypeDef RET[32]; /**< RetentionReg */
-} RTCC_TypeDef; /** @} */
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_RTCC
- * @{
- * @defgroup EFR32FG13P_RTCC_BitFields RTCC Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for RTCC CTRL */
-#define _RTCC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CTRL */
-#define _RTCC_CTRL_MASK 0x00039F35UL /**< Mask for RTCC_CTRL */
-#define RTCC_CTRL_ENABLE (0x1UL << 0) /**< RTCC Enable */
-#define _RTCC_CTRL_ENABLE_SHIFT 0 /**< Shift value for RTCC_ENABLE */
-#define _RTCC_CTRL_ENABLE_MASK 0x1UL /**< Bit mask for RTCC_ENABLE */
-#define _RTCC_CTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
-#define RTCC_CTRL_ENABLE_DEFAULT (_RTCC_CTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CTRL */
-#define RTCC_CTRL_DEBUGRUN (0x1UL << 2) /**< Debug Mode Run Enable */
-#define _RTCC_CTRL_DEBUGRUN_SHIFT 2 /**< Shift value for RTCC_DEBUGRUN */
-#define _RTCC_CTRL_DEBUGRUN_MASK 0x4UL /**< Bit mask for RTCC_DEBUGRUN */
-#define _RTCC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
-#define RTCC_CTRL_DEBUGRUN_DEFAULT (_RTCC_CTRL_DEBUGRUN_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CTRL */
-#define RTCC_CTRL_PRECCV0TOP (0x1UL << 4) /**< Pre-counter CCV0 Top Value Enable */
-#define _RTCC_CTRL_PRECCV0TOP_SHIFT 4 /**< Shift value for RTCC_PRECCV0TOP */
-#define _RTCC_CTRL_PRECCV0TOP_MASK 0x10UL /**< Bit mask for RTCC_PRECCV0TOP */
-#define _RTCC_CTRL_PRECCV0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
-#define RTCC_CTRL_PRECCV0TOP_DEFAULT (_RTCC_CTRL_PRECCV0TOP_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CTRL */
-#define RTCC_CTRL_CCV1TOP (0x1UL << 5) /**< CCV1 Top Value Enable */
-#define _RTCC_CTRL_CCV1TOP_SHIFT 5 /**< Shift value for RTCC_CCV1TOP */
-#define _RTCC_CTRL_CCV1TOP_MASK 0x20UL /**< Bit mask for RTCC_CCV1TOP */
-#define _RTCC_CTRL_CCV1TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
-#define RTCC_CTRL_CCV1TOP_DEFAULT (_RTCC_CTRL_CCV1TOP_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_CTRL */
-#define _RTCC_CTRL_CNTPRESC_SHIFT 8 /**< Shift value for RTCC_CNTPRESC */
-#define _RTCC_CTRL_CNTPRESC_MASK 0xF00UL /**< Bit mask for RTCC_CNTPRESC */
-#define _RTCC_CTRL_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
-#define _RTCC_CTRL_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for RTCC_CTRL */
-#define _RTCC_CTRL_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for RTCC_CTRL */
-#define _RTCC_CTRL_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for RTCC_CTRL */
-#define _RTCC_CTRL_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for RTCC_CTRL */
-#define _RTCC_CTRL_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for RTCC_CTRL */
-#define _RTCC_CTRL_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for RTCC_CTRL */
-#define _RTCC_CTRL_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for RTCC_CTRL */
-#define _RTCC_CTRL_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for RTCC_CTRL */
-#define _RTCC_CTRL_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for RTCC_CTRL */
-#define _RTCC_CTRL_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for RTCC_CTRL */
-#define _RTCC_CTRL_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for RTCC_CTRL */
-#define _RTCC_CTRL_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for RTCC_CTRL */
-#define _RTCC_CTRL_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for RTCC_CTRL */
-#define _RTCC_CTRL_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for RTCC_CTRL */
-#define _RTCC_CTRL_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for RTCC_CTRL */
-#define _RTCC_CTRL_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for RTCC_CTRL */
-#define RTCC_CTRL_CNTPRESC_DEFAULT (_RTCC_CTRL_CNTPRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CTRL */
-#define RTCC_CTRL_CNTPRESC_DIV1 (_RTCC_CTRL_CNTPRESC_DIV1 << 8) /**< Shifted mode DIV1 for RTCC_CTRL */
-#define RTCC_CTRL_CNTPRESC_DIV2 (_RTCC_CTRL_CNTPRESC_DIV2 << 8) /**< Shifted mode DIV2 for RTCC_CTRL */
-#define RTCC_CTRL_CNTPRESC_DIV4 (_RTCC_CTRL_CNTPRESC_DIV4 << 8) /**< Shifted mode DIV4 for RTCC_CTRL */
-#define RTCC_CTRL_CNTPRESC_DIV8 (_RTCC_CTRL_CNTPRESC_DIV8 << 8) /**< Shifted mode DIV8 for RTCC_CTRL */
-#define RTCC_CTRL_CNTPRESC_DIV16 (_RTCC_CTRL_CNTPRESC_DIV16 << 8) /**< Shifted mode DIV16 for RTCC_CTRL */
-#define RTCC_CTRL_CNTPRESC_DIV32 (_RTCC_CTRL_CNTPRESC_DIV32 << 8) /**< Shifted mode DIV32 for RTCC_CTRL */
-#define RTCC_CTRL_CNTPRESC_DIV64 (_RTCC_CTRL_CNTPRESC_DIV64 << 8) /**< Shifted mode DIV64 for RTCC_CTRL */
-#define RTCC_CTRL_CNTPRESC_DIV128 (_RTCC_CTRL_CNTPRESC_DIV128 << 8) /**< Shifted mode DIV128 for RTCC_CTRL */
-#define RTCC_CTRL_CNTPRESC_DIV256 (_RTCC_CTRL_CNTPRESC_DIV256 << 8) /**< Shifted mode DIV256 for RTCC_CTRL */
-#define RTCC_CTRL_CNTPRESC_DIV512 (_RTCC_CTRL_CNTPRESC_DIV512 << 8) /**< Shifted mode DIV512 for RTCC_CTRL */
-#define RTCC_CTRL_CNTPRESC_DIV1024 (_RTCC_CTRL_CNTPRESC_DIV1024 << 8) /**< Shifted mode DIV1024 for RTCC_CTRL */
-#define RTCC_CTRL_CNTPRESC_DIV2048 (_RTCC_CTRL_CNTPRESC_DIV2048 << 8) /**< Shifted mode DIV2048 for RTCC_CTRL */
-#define RTCC_CTRL_CNTPRESC_DIV4096 (_RTCC_CTRL_CNTPRESC_DIV4096 << 8) /**< Shifted mode DIV4096 for RTCC_CTRL */
-#define RTCC_CTRL_CNTPRESC_DIV8192 (_RTCC_CTRL_CNTPRESC_DIV8192 << 8) /**< Shifted mode DIV8192 for RTCC_CTRL */
-#define RTCC_CTRL_CNTPRESC_DIV16384 (_RTCC_CTRL_CNTPRESC_DIV16384 << 8) /**< Shifted mode DIV16384 for RTCC_CTRL */
-#define RTCC_CTRL_CNTPRESC_DIV32768 (_RTCC_CTRL_CNTPRESC_DIV32768 << 8) /**< Shifted mode DIV32768 for RTCC_CTRL */
-#define RTCC_CTRL_CNTTICK (0x1UL << 12) /**< Counter Prescaler Mode */
-#define _RTCC_CTRL_CNTTICK_SHIFT 12 /**< Shift value for RTCC_CNTTICK */
-#define _RTCC_CTRL_CNTTICK_MASK 0x1000UL /**< Bit mask for RTCC_CNTTICK */
-#define _RTCC_CTRL_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
-#define _RTCC_CTRL_CNTTICK_PRESC 0x00000000UL /**< Mode PRESC for RTCC_CTRL */
-#define _RTCC_CTRL_CNTTICK_CCV0MATCH 0x00000001UL /**< Mode CCV0MATCH for RTCC_CTRL */
-#define RTCC_CTRL_CNTTICK_DEFAULT (_RTCC_CTRL_CNTTICK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CTRL */
-#define RTCC_CTRL_CNTTICK_PRESC (_RTCC_CTRL_CNTTICK_PRESC << 12) /**< Shifted mode PRESC for RTCC_CTRL */
-#define RTCC_CTRL_CNTTICK_CCV0MATCH (_RTCC_CTRL_CNTTICK_CCV0MATCH << 12) /**< Shifted mode CCV0MATCH for RTCC_CTRL */
-#define RTCC_CTRL_OSCFDETEN (0x1UL << 15) /**< Oscillator Failure Detection Enable */
-#define _RTCC_CTRL_OSCFDETEN_SHIFT 15 /**< Shift value for RTCC_OSCFDETEN */
-#define _RTCC_CTRL_OSCFDETEN_MASK 0x8000UL /**< Bit mask for RTCC_OSCFDETEN */
-#define _RTCC_CTRL_OSCFDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
-#define RTCC_CTRL_OSCFDETEN_DEFAULT (_RTCC_CTRL_OSCFDETEN_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_CTRL */
-#define RTCC_CTRL_CNTMODE (0x1UL << 16) /**< Main Counter Mode */
-#define _RTCC_CTRL_CNTMODE_SHIFT 16 /**< Shift value for RTCC_CNTMODE */
-#define _RTCC_CTRL_CNTMODE_MASK 0x10000UL /**< Bit mask for RTCC_CNTMODE */
-#define _RTCC_CTRL_CNTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
-#define _RTCC_CTRL_CNTMODE_NORMAL 0x00000000UL /**< Mode NORMAL for RTCC_CTRL */
-#define _RTCC_CTRL_CNTMODE_CALENDAR 0x00000001UL /**< Mode CALENDAR for RTCC_CTRL */
-#define RTCC_CTRL_CNTMODE_DEFAULT (_RTCC_CTRL_CNTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_CTRL */
-#define RTCC_CTRL_CNTMODE_NORMAL (_RTCC_CTRL_CNTMODE_NORMAL << 16) /**< Shifted mode NORMAL for RTCC_CTRL */
-#define RTCC_CTRL_CNTMODE_CALENDAR (_RTCC_CTRL_CNTMODE_CALENDAR << 16) /**< Shifted mode CALENDAR for RTCC_CTRL */
-#define RTCC_CTRL_LYEARCORRDIS (0x1UL << 17) /**< Leap Year Correction Disabled */
-#define _RTCC_CTRL_LYEARCORRDIS_SHIFT 17 /**< Shift value for RTCC_LYEARCORRDIS */
-#define _RTCC_CTRL_LYEARCORRDIS_MASK 0x20000UL /**< Bit mask for RTCC_LYEARCORRDIS */
-#define _RTCC_CTRL_LYEARCORRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
-#define RTCC_CTRL_LYEARCORRDIS_DEFAULT (_RTCC_CTRL_LYEARCORRDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for RTCC_CTRL */
-
-/* Bit fields for RTCC PRECNT */
-#define _RTCC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_PRECNT */
-#define _RTCC_PRECNT_MASK 0x00007FFFUL /**< Mask for RTCC_PRECNT */
-#define _RTCC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */
-#define _RTCC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */
-#define _RTCC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_PRECNT */
-#define RTCC_PRECNT_PRECNT_DEFAULT (_RTCC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_PRECNT */
-
-/* Bit fields for RTCC CNT */
-#define _RTCC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_CNT */
-#define _RTCC_CNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CNT */
-#define _RTCC_CNT_CNT_SHIFT 0 /**< Shift value for RTCC_CNT */
-#define _RTCC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_CNT */
-#define _RTCC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CNT */
-#define RTCC_CNT_CNT_DEFAULT (_RTCC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CNT */
-
-/* Bit fields for RTCC COMBCNT */
-#define _RTCC_COMBCNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_COMBCNT */
-#define _RTCC_COMBCNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_COMBCNT */
-#define _RTCC_COMBCNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */
-#define _RTCC_COMBCNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */
-#define _RTCC_COMBCNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */
-#define RTCC_COMBCNT_PRECNT_DEFAULT (_RTCC_COMBCNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_COMBCNT */
-#define _RTCC_COMBCNT_CNTLSB_SHIFT 15 /**< Shift value for RTCC_CNTLSB */
-#define _RTCC_COMBCNT_CNTLSB_MASK 0xFFFF8000UL /**< Bit mask for RTCC_CNTLSB */
-#define _RTCC_COMBCNT_CNTLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */
-#define RTCC_COMBCNT_CNTLSB_DEFAULT (_RTCC_COMBCNT_CNTLSB_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_COMBCNT */
-
-/* Bit fields for RTCC TIME */
-#define _RTCC_TIME_RESETVALUE 0x00000000UL /**< Default value for RTCC_TIME */
-#define _RTCC_TIME_MASK 0x003F7F7FUL /**< Mask for RTCC_TIME */
-#define _RTCC_TIME_SECU_SHIFT 0 /**< Shift value for RTCC_SECU */
-#define _RTCC_TIME_SECU_MASK 0xFUL /**< Bit mask for RTCC_SECU */
-#define _RTCC_TIME_SECU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */
-#define RTCC_TIME_SECU_DEFAULT (_RTCC_TIME_SECU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_TIME */
-#define _RTCC_TIME_SECT_SHIFT 4 /**< Shift value for RTCC_SECT */
-#define _RTCC_TIME_SECT_MASK 0x70UL /**< Bit mask for RTCC_SECT */
-#define _RTCC_TIME_SECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */
-#define RTCC_TIME_SECT_DEFAULT (_RTCC_TIME_SECT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_TIME */
-#define _RTCC_TIME_MINU_SHIFT 8 /**< Shift value for RTCC_MINU */
-#define _RTCC_TIME_MINU_MASK 0xF00UL /**< Bit mask for RTCC_MINU */
-#define _RTCC_TIME_MINU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */
-#define RTCC_TIME_MINU_DEFAULT (_RTCC_TIME_MINU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_TIME */
-#define _RTCC_TIME_MINT_SHIFT 12 /**< Shift value for RTCC_MINT */
-#define _RTCC_TIME_MINT_MASK 0x7000UL /**< Bit mask for RTCC_MINT */
-#define _RTCC_TIME_MINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */
-#define RTCC_TIME_MINT_DEFAULT (_RTCC_TIME_MINT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_TIME */
-#define _RTCC_TIME_HOURU_SHIFT 16 /**< Shift value for RTCC_HOURU */
-#define _RTCC_TIME_HOURU_MASK 0xF0000UL /**< Bit mask for RTCC_HOURU */
-#define _RTCC_TIME_HOURU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */
-#define RTCC_TIME_HOURU_DEFAULT (_RTCC_TIME_HOURU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_TIME */
-#define _RTCC_TIME_HOURT_SHIFT 20 /**< Shift value for RTCC_HOURT */
-#define _RTCC_TIME_HOURT_MASK 0x300000UL /**< Bit mask for RTCC_HOURT */
-#define _RTCC_TIME_HOURT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */
-#define RTCC_TIME_HOURT_DEFAULT (_RTCC_TIME_HOURT_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_TIME */
-
-/* Bit fields for RTCC DATE */
-#define _RTCC_DATE_RESETVALUE 0x00000000UL /**< Default value for RTCC_DATE */
-#define _RTCC_DATE_MASK 0x07FF1F3FUL /**< Mask for RTCC_DATE */
-#define _RTCC_DATE_DAYOMU_SHIFT 0 /**< Shift value for RTCC_DAYOMU */
-#define _RTCC_DATE_DAYOMU_MASK 0xFUL /**< Bit mask for RTCC_DAYOMU */
-#define _RTCC_DATE_DAYOMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
-#define RTCC_DATE_DAYOMU_DEFAULT (_RTCC_DATE_DAYOMU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_DATE */
-#define _RTCC_DATE_DAYOMT_SHIFT 4 /**< Shift value for RTCC_DAYOMT */
-#define _RTCC_DATE_DAYOMT_MASK 0x30UL /**< Bit mask for RTCC_DAYOMT */
-#define _RTCC_DATE_DAYOMT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
-#define RTCC_DATE_DAYOMT_DEFAULT (_RTCC_DATE_DAYOMT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_DATE */
-#define _RTCC_DATE_MONTHU_SHIFT 8 /**< Shift value for RTCC_MONTHU */
-#define _RTCC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for RTCC_MONTHU */
-#define _RTCC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
-#define RTCC_DATE_MONTHU_DEFAULT (_RTCC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_DATE */
-#define RTCC_DATE_MONTHT (0x1UL << 12) /**< Month, Tens */
-#define _RTCC_DATE_MONTHT_SHIFT 12 /**< Shift value for RTCC_MONTHT */
-#define _RTCC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for RTCC_MONTHT */
-#define _RTCC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
-#define RTCC_DATE_MONTHT_DEFAULT (_RTCC_DATE_MONTHT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_DATE */
-#define _RTCC_DATE_YEARU_SHIFT 16 /**< Shift value for RTCC_YEARU */
-#define _RTCC_DATE_YEARU_MASK 0xF0000UL /**< Bit mask for RTCC_YEARU */
-#define _RTCC_DATE_YEARU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
-#define RTCC_DATE_YEARU_DEFAULT (_RTCC_DATE_YEARU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_DATE */
-#define _RTCC_DATE_YEART_SHIFT 20 /**< Shift value for RTCC_YEART */
-#define _RTCC_DATE_YEART_MASK 0xF00000UL /**< Bit mask for RTCC_YEART */
-#define _RTCC_DATE_YEART_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
-#define RTCC_DATE_YEART_DEFAULT (_RTCC_DATE_YEART_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_DATE */
-#define _RTCC_DATE_DAYOW_SHIFT 24 /**< Shift value for RTCC_DAYOW */
-#define _RTCC_DATE_DAYOW_MASK 0x7000000UL /**< Bit mask for RTCC_DAYOW */
-#define _RTCC_DATE_DAYOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
-#define RTCC_DATE_DAYOW_DEFAULT (_RTCC_DATE_DAYOW_DEFAULT << 24) /**< Shifted mode DEFAULT for RTCC_DATE */
-
-/* Bit fields for RTCC IF */
-#define _RTCC_IF_RESETVALUE 0x00000000UL /**< Default value for RTCC_IF */
-#define _RTCC_IF_MASK 0x000007FFUL /**< Mask for RTCC_IF */
-#define RTCC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */
-#define _RTCC_IF_OF_SHIFT 0 /**< Shift value for RTCC_OF */
-#define _RTCC_IF_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */
-#define _RTCC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
-#define RTCC_IF_OF_DEFAULT (_RTCC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IF */
-#define RTCC_IF_CC0 (0x1UL << 1) /**< Channel 0 Interrupt Flag */
-#define _RTCC_IF_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */
-#define _RTCC_IF_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */
-#define _RTCC_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
-#define RTCC_IF_CC0_DEFAULT (_RTCC_IF_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IF */
-#define RTCC_IF_CC1 (0x1UL << 2) /**< Channel 1 Interrupt Flag */
-#define _RTCC_IF_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */
-#define _RTCC_IF_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */
-#define _RTCC_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
-#define RTCC_IF_CC1_DEFAULT (_RTCC_IF_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IF */
-#define RTCC_IF_CC2 (0x1UL << 3) /**< Channel 2 Interrupt Flag */
-#define _RTCC_IF_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */
-#define _RTCC_IF_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */
-#define _RTCC_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
-#define RTCC_IF_CC2_DEFAULT (_RTCC_IF_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IF */
-#define RTCC_IF_OSCFAIL (0x1UL << 4) /**< Oscillator Failure Interrupt Flag */
-#define _RTCC_IF_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */
-#define _RTCC_IF_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */
-#define _RTCC_IF_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
-#define RTCC_IF_OSCFAIL_DEFAULT (_RTCC_IF_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IF */
-#define RTCC_IF_CNTTICK (0x1UL << 5) /**< Main Counter Tick */
-#define _RTCC_IF_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */
-#define _RTCC_IF_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */
-#define _RTCC_IF_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
-#define RTCC_IF_CNTTICK_DEFAULT (_RTCC_IF_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IF */
-#define RTCC_IF_MINTICK (0x1UL << 6) /**< Minute Tick */
-#define _RTCC_IF_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */
-#define _RTCC_IF_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */
-#define _RTCC_IF_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
-#define RTCC_IF_MINTICK_DEFAULT (_RTCC_IF_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IF */
-#define RTCC_IF_HOURTICK (0x1UL << 7) /**< Hour Tick */
-#define _RTCC_IF_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */
-#define _RTCC_IF_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */
-#define _RTCC_IF_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
-#define RTCC_IF_HOURTICK_DEFAULT (_RTCC_IF_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IF */
-#define RTCC_IF_DAYTICK (0x1UL << 8) /**< Day Tick */
-#define _RTCC_IF_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */
-#define _RTCC_IF_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */
-#define _RTCC_IF_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
-#define RTCC_IF_DAYTICK_DEFAULT (_RTCC_IF_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IF */
-#define RTCC_IF_DAYOWOF (0x1UL << 9) /**< Day of Week Overflow */
-#define _RTCC_IF_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */
-#define _RTCC_IF_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */
-#define _RTCC_IF_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
-#define RTCC_IF_DAYOWOF_DEFAULT (_RTCC_IF_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IF */
-#define RTCC_IF_MONTHTICK (0x1UL << 10) /**< Month Tick */
-#define _RTCC_IF_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */
-#define _RTCC_IF_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */
-#define _RTCC_IF_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
-#define RTCC_IF_MONTHTICK_DEFAULT (_RTCC_IF_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IF */
-
-/* Bit fields for RTCC IFS */
-#define _RTCC_IFS_RESETVALUE 0x00000000UL /**< Default value for RTCC_IFS */
-#define _RTCC_IFS_MASK 0x000007FFUL /**< Mask for RTCC_IFS */
-#define RTCC_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */
-#define _RTCC_IFS_OF_SHIFT 0 /**< Shift value for RTCC_OF */
-#define _RTCC_IFS_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */
-#define _RTCC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
-#define RTCC_IFS_OF_DEFAULT (_RTCC_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IFS */
-#define RTCC_IFS_CC0 (0x1UL << 1) /**< Set CC0 Interrupt Flag */
-#define _RTCC_IFS_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */
-#define _RTCC_IFS_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */
-#define _RTCC_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
-#define RTCC_IFS_CC0_DEFAULT (_RTCC_IFS_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IFS */
-#define RTCC_IFS_CC1 (0x1UL << 2) /**< Set CC1 Interrupt Flag */
-#define _RTCC_IFS_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */
-#define _RTCC_IFS_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */
-#define _RTCC_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
-#define RTCC_IFS_CC1_DEFAULT (_RTCC_IFS_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IFS */
-#define RTCC_IFS_CC2 (0x1UL << 3) /**< Set CC2 Interrupt Flag */
-#define _RTCC_IFS_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */
-#define _RTCC_IFS_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */
-#define _RTCC_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
-#define RTCC_IFS_CC2_DEFAULT (_RTCC_IFS_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IFS */
-#define RTCC_IFS_OSCFAIL (0x1UL << 4) /**< Set OSCFAIL Interrupt Flag */
-#define _RTCC_IFS_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */
-#define _RTCC_IFS_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */
-#define _RTCC_IFS_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
-#define RTCC_IFS_OSCFAIL_DEFAULT (_RTCC_IFS_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IFS */
-#define RTCC_IFS_CNTTICK (0x1UL << 5) /**< Set CNTTICK Interrupt Flag */
-#define _RTCC_IFS_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */
-#define _RTCC_IFS_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */
-#define _RTCC_IFS_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
-#define RTCC_IFS_CNTTICK_DEFAULT (_RTCC_IFS_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IFS */
-#define RTCC_IFS_MINTICK (0x1UL << 6) /**< Set MINTICK Interrupt Flag */
-#define _RTCC_IFS_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */
-#define _RTCC_IFS_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */
-#define _RTCC_IFS_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
-#define RTCC_IFS_MINTICK_DEFAULT (_RTCC_IFS_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IFS */
-#define RTCC_IFS_HOURTICK (0x1UL << 7) /**< Set HOURTICK Interrupt Flag */
-#define _RTCC_IFS_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */
-#define _RTCC_IFS_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */
-#define _RTCC_IFS_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
-#define RTCC_IFS_HOURTICK_DEFAULT (_RTCC_IFS_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IFS */
-#define RTCC_IFS_DAYTICK (0x1UL << 8) /**< Set DAYTICK Interrupt Flag */
-#define _RTCC_IFS_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */
-#define _RTCC_IFS_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */
-#define _RTCC_IFS_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
-#define RTCC_IFS_DAYTICK_DEFAULT (_RTCC_IFS_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IFS */
-#define RTCC_IFS_DAYOWOF (0x1UL << 9) /**< Set DAYOWOF Interrupt Flag */
-#define _RTCC_IFS_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */
-#define _RTCC_IFS_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */
-#define _RTCC_IFS_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
-#define RTCC_IFS_DAYOWOF_DEFAULT (_RTCC_IFS_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IFS */
-#define RTCC_IFS_MONTHTICK (0x1UL << 10) /**< Set MONTHTICK Interrupt Flag */
-#define _RTCC_IFS_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */
-#define _RTCC_IFS_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */
-#define _RTCC_IFS_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
-#define RTCC_IFS_MONTHTICK_DEFAULT (_RTCC_IFS_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IFS */
-
-/* Bit fields for RTCC IFC */
-#define _RTCC_IFC_RESETVALUE 0x00000000UL /**< Default value for RTCC_IFC */
-#define _RTCC_IFC_MASK 0x000007FFUL /**< Mask for RTCC_IFC */
-#define RTCC_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */
-#define _RTCC_IFC_OF_SHIFT 0 /**< Shift value for RTCC_OF */
-#define _RTCC_IFC_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */
-#define _RTCC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
-#define RTCC_IFC_OF_DEFAULT (_RTCC_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IFC */
-#define RTCC_IFC_CC0 (0x1UL << 1) /**< Clear CC0 Interrupt Flag */
-#define _RTCC_IFC_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */
-#define _RTCC_IFC_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */
-#define _RTCC_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
-#define RTCC_IFC_CC0_DEFAULT (_RTCC_IFC_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IFC */
-#define RTCC_IFC_CC1 (0x1UL << 2) /**< Clear CC1 Interrupt Flag */
-#define _RTCC_IFC_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */
-#define _RTCC_IFC_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */
-#define _RTCC_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
-#define RTCC_IFC_CC1_DEFAULT (_RTCC_IFC_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IFC */
-#define RTCC_IFC_CC2 (0x1UL << 3) /**< Clear CC2 Interrupt Flag */
-#define _RTCC_IFC_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */
-#define _RTCC_IFC_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */
-#define _RTCC_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
-#define RTCC_IFC_CC2_DEFAULT (_RTCC_IFC_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IFC */
-#define RTCC_IFC_OSCFAIL (0x1UL << 4) /**< Clear OSCFAIL Interrupt Flag */
-#define _RTCC_IFC_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */
-#define _RTCC_IFC_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */
-#define _RTCC_IFC_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
-#define RTCC_IFC_OSCFAIL_DEFAULT (_RTCC_IFC_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IFC */
-#define RTCC_IFC_CNTTICK (0x1UL << 5) /**< Clear CNTTICK Interrupt Flag */
-#define _RTCC_IFC_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */
-#define _RTCC_IFC_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */
-#define _RTCC_IFC_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
-#define RTCC_IFC_CNTTICK_DEFAULT (_RTCC_IFC_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IFC */
-#define RTCC_IFC_MINTICK (0x1UL << 6) /**< Clear MINTICK Interrupt Flag */
-#define _RTCC_IFC_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */
-#define _RTCC_IFC_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */
-#define _RTCC_IFC_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
-#define RTCC_IFC_MINTICK_DEFAULT (_RTCC_IFC_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IFC */
-#define RTCC_IFC_HOURTICK (0x1UL << 7) /**< Clear HOURTICK Interrupt Flag */
-#define _RTCC_IFC_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */
-#define _RTCC_IFC_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */
-#define _RTCC_IFC_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
-#define RTCC_IFC_HOURTICK_DEFAULT (_RTCC_IFC_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IFC */
-#define RTCC_IFC_DAYTICK (0x1UL << 8) /**< Clear DAYTICK Interrupt Flag */
-#define _RTCC_IFC_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */
-#define _RTCC_IFC_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */
-#define _RTCC_IFC_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
-#define RTCC_IFC_DAYTICK_DEFAULT (_RTCC_IFC_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IFC */
-#define RTCC_IFC_DAYOWOF (0x1UL << 9) /**< Clear DAYOWOF Interrupt Flag */
-#define _RTCC_IFC_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */
-#define _RTCC_IFC_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */
-#define _RTCC_IFC_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
-#define RTCC_IFC_DAYOWOF_DEFAULT (_RTCC_IFC_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IFC */
-#define RTCC_IFC_MONTHTICK (0x1UL << 10) /**< Clear MONTHTICK Interrupt Flag */
-#define _RTCC_IFC_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */
-#define _RTCC_IFC_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */
-#define _RTCC_IFC_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
-#define RTCC_IFC_MONTHTICK_DEFAULT (_RTCC_IFC_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IFC */
-
-/* Bit fields for RTCC IEN */
-#define _RTCC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_IEN */
-#define _RTCC_IEN_MASK 0x000007FFUL /**< Mask for RTCC_IEN */
-#define RTCC_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */
-#define _RTCC_IEN_OF_SHIFT 0 /**< Shift value for RTCC_OF */
-#define _RTCC_IEN_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */
-#define _RTCC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
-#define RTCC_IEN_OF_DEFAULT (_RTCC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IEN */
-#define RTCC_IEN_CC0 (0x1UL << 1) /**< CC0 Interrupt Enable */
-#define _RTCC_IEN_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */
-#define _RTCC_IEN_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */
-#define _RTCC_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
-#define RTCC_IEN_CC0_DEFAULT (_RTCC_IEN_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IEN */
-#define RTCC_IEN_CC1 (0x1UL << 2) /**< CC1 Interrupt Enable */
-#define _RTCC_IEN_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */
-#define _RTCC_IEN_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */
-#define _RTCC_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
-#define RTCC_IEN_CC1_DEFAULT (_RTCC_IEN_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IEN */
-#define RTCC_IEN_CC2 (0x1UL << 3) /**< CC2 Interrupt Enable */
-#define _RTCC_IEN_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */
-#define _RTCC_IEN_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */
-#define _RTCC_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
-#define RTCC_IEN_CC2_DEFAULT (_RTCC_IEN_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IEN */
-#define RTCC_IEN_OSCFAIL (0x1UL << 4) /**< OSCFAIL Interrupt Enable */
-#define _RTCC_IEN_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */
-#define _RTCC_IEN_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */
-#define _RTCC_IEN_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
-#define RTCC_IEN_OSCFAIL_DEFAULT (_RTCC_IEN_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IEN */
-#define RTCC_IEN_CNTTICK (0x1UL << 5) /**< CNTTICK Interrupt Enable */
-#define _RTCC_IEN_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */
-#define _RTCC_IEN_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */
-#define _RTCC_IEN_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
-#define RTCC_IEN_CNTTICK_DEFAULT (_RTCC_IEN_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IEN */
-#define RTCC_IEN_MINTICK (0x1UL << 6) /**< MINTICK Interrupt Enable */
-#define _RTCC_IEN_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */
-#define _RTCC_IEN_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */
-#define _RTCC_IEN_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
-#define RTCC_IEN_MINTICK_DEFAULT (_RTCC_IEN_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IEN */
-#define RTCC_IEN_HOURTICK (0x1UL << 7) /**< HOURTICK Interrupt Enable */
-#define _RTCC_IEN_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */
-#define _RTCC_IEN_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */
-#define _RTCC_IEN_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
-#define RTCC_IEN_HOURTICK_DEFAULT (_RTCC_IEN_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IEN */
-#define RTCC_IEN_DAYTICK (0x1UL << 8) /**< DAYTICK Interrupt Enable */
-#define _RTCC_IEN_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */
-#define _RTCC_IEN_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */
-#define _RTCC_IEN_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
-#define RTCC_IEN_DAYTICK_DEFAULT (_RTCC_IEN_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IEN */
-#define RTCC_IEN_DAYOWOF (0x1UL << 9) /**< DAYOWOF Interrupt Enable */
-#define _RTCC_IEN_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */
-#define _RTCC_IEN_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */
-#define _RTCC_IEN_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
-#define RTCC_IEN_DAYOWOF_DEFAULT (_RTCC_IEN_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IEN */
-#define RTCC_IEN_MONTHTICK (0x1UL << 10) /**< MONTHTICK Interrupt Enable */
-#define _RTCC_IEN_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */
-#define _RTCC_IEN_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */
-#define _RTCC_IEN_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
-#define RTCC_IEN_MONTHTICK_DEFAULT (_RTCC_IEN_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IEN */
-
-/* Bit fields for RTCC STATUS */
-#define _RTCC_STATUS_RESETVALUE 0x00000000UL /**< Default value for RTCC_STATUS */
-#define _RTCC_STATUS_MASK 0x00000000UL /**< Mask for RTCC_STATUS */
-
-/* Bit fields for RTCC CMD */
-#define _RTCC_CMD_RESETVALUE 0x00000000UL /**< Default value for RTCC_CMD */
-#define _RTCC_CMD_MASK 0x00000001UL /**< Mask for RTCC_CMD */
-#define RTCC_CMD_CLRSTATUS (0x1UL << 0) /**< Clear RTCC_STATUS Register */
-#define _RTCC_CMD_CLRSTATUS_SHIFT 0 /**< Shift value for RTCC_CLRSTATUS */
-#define _RTCC_CMD_CLRSTATUS_MASK 0x1UL /**< Bit mask for RTCC_CLRSTATUS */
-#define _RTCC_CMD_CLRSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CMD */
-#define RTCC_CMD_CLRSTATUS_DEFAULT (_RTCC_CMD_CLRSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CMD */
-
-/* Bit fields for RTCC SYNCBUSY */
-#define _RTCC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for RTCC_SYNCBUSY */
-#define _RTCC_SYNCBUSY_MASK 0x00000020UL /**< Mask for RTCC_SYNCBUSY */
-#define RTCC_SYNCBUSY_CMD (0x1UL << 5) /**< CMD Register Busy */
-#define _RTCC_SYNCBUSY_CMD_SHIFT 5 /**< Shift value for RTCC_CMD */
-#define _RTCC_SYNCBUSY_CMD_MASK 0x20UL /**< Bit mask for RTCC_CMD */
-#define _RTCC_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */
-#define RTCC_SYNCBUSY_CMD_DEFAULT (_RTCC_SYNCBUSY_CMD_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */
-
-/* Bit fields for RTCC POWERDOWN */
-#define _RTCC_POWERDOWN_RESETVALUE 0x00000000UL /**< Default value for RTCC_POWERDOWN */
-#define _RTCC_POWERDOWN_MASK 0x00000001UL /**< Mask for RTCC_POWERDOWN */
-#define RTCC_POWERDOWN_RAM (0x1UL << 0) /**< Retention RAM Power-down */
-#define _RTCC_POWERDOWN_RAM_SHIFT 0 /**< Shift value for RTCC_RAM */
-#define _RTCC_POWERDOWN_RAM_MASK 0x1UL /**< Bit mask for RTCC_RAM */
-#define _RTCC_POWERDOWN_RAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_POWERDOWN */
-#define RTCC_POWERDOWN_RAM_DEFAULT (_RTCC_POWERDOWN_RAM_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_POWERDOWN */
-
-/* Bit fields for RTCC LOCK */
-#define _RTCC_LOCK_RESETVALUE 0x00000000UL /**< Default value for RTCC_LOCK */
-#define _RTCC_LOCK_MASK 0x0000FFFFUL /**< Mask for RTCC_LOCK */
-#define _RTCC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RTCC_LOCKKEY */
-#define _RTCC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RTCC_LOCKKEY */
-#define _RTCC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_LOCK */
-#define _RTCC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RTCC_LOCK */
-#define _RTCC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RTCC_LOCK */
-#define _RTCC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RTCC_LOCK */
-#define _RTCC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for RTCC_LOCK */
-#define RTCC_LOCK_LOCKKEY_DEFAULT (_RTCC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_LOCK */
-#define RTCC_LOCK_LOCKKEY_LOCK (_RTCC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RTCC_LOCK */
-#define RTCC_LOCK_LOCKKEY_UNLOCKED (_RTCC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RTCC_LOCK */
-#define RTCC_LOCK_LOCKKEY_LOCKED (_RTCC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RTCC_LOCK */
-#define RTCC_LOCK_LOCKKEY_UNLOCK (_RTCC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RTCC_LOCK */
-
-/* Bit fields for RTCC EM4WUEN */
-#define _RTCC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_EM4WUEN */
-#define _RTCC_EM4WUEN_MASK 0x00000001UL /**< Mask for RTCC_EM4WUEN */
-#define RTCC_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up Enable */
-#define _RTCC_EM4WUEN_EM4WU_SHIFT 0 /**< Shift value for RTCC_EM4WU */
-#define _RTCC_EM4WUEN_EM4WU_MASK 0x1UL /**< Bit mask for RTCC_EM4WU */
-#define _RTCC_EM4WUEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_EM4WUEN */
-#define RTCC_EM4WUEN_EM4WU_DEFAULT (_RTCC_EM4WUEN_EM4WU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_EM4WUEN */
-
-/* Bit fields for RTCC CC_CTRL */
-#define _RTCC_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_MASK 0x0003FBFFUL /**< Mask for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_MODE_SHIFT 0 /**< Shift value for CC_MODE */
-#define _RTCC_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for CC_MODE */
-#define _RTCC_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_MODE_DEFAULT (_RTCC_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_MODE_OFF (_RTCC_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_MODE_INPUTCAPTURE (_RTCC_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_MODE_OUTPUTCOMPARE (_RTCC_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_CMOA_SHIFT 2 /**< Shift value for CC_CMOA */
-#define _RTCC_CC_CTRL_CMOA_MASK 0xCUL /**< Bit mask for CC_CMOA */
-#define _RTCC_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_CMOA_PULSE 0x00000000UL /**< Mode PULSE for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_CMOA_DEFAULT (_RTCC_CC_CTRL_CMOA_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_CMOA_PULSE (_RTCC_CC_CTRL_CMOA_PULSE << 2) /**< Shifted mode PULSE for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_CMOA_TOGGLE (_RTCC_CC_CTRL_CMOA_TOGGLE << 2) /**< Shifted mode TOGGLE for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_CMOA_CLEAR (_RTCC_CC_CTRL_CMOA_CLEAR << 2) /**< Shifted mode CLEAR for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_CMOA_SET (_RTCC_CC_CTRL_CMOA_SET << 2) /**< Shifted mode SET for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_ICEDGE_SHIFT 4 /**< Shift value for CC_ICEDGE */
-#define _RTCC_CC_CTRL_ICEDGE_MASK 0x30UL /**< Bit mask for CC_ICEDGE */
-#define _RTCC_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_ICEDGE_DEFAULT (_RTCC_CC_CTRL_ICEDGE_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_ICEDGE_RISING (_RTCC_CC_CTRL_ICEDGE_RISING << 4) /**< Shifted mode RISING for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_ICEDGE_FALLING (_RTCC_CC_CTRL_ICEDGE_FALLING << 4) /**< Shifted mode FALLING for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_ICEDGE_BOTH (_RTCC_CC_CTRL_ICEDGE_BOTH << 4) /**< Shifted mode BOTH for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_ICEDGE_NONE (_RTCC_CC_CTRL_ICEDGE_NONE << 4) /**< Shifted mode NONE for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_PRSSEL_SHIFT 6 /**< Shift value for CC_PRSSEL */
-#define _RTCC_CC_CTRL_PRSSEL_MASK 0x3C0UL /**< Bit mask for CC_PRSSEL */
-#define _RTCC_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_PRSSEL_DEFAULT (_RTCC_CC_CTRL_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_PRSSEL_PRSCH0 (_RTCC_CC_CTRL_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_PRSSEL_PRSCH1 (_RTCC_CC_CTRL_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_PRSSEL_PRSCH2 (_RTCC_CC_CTRL_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_PRSSEL_PRSCH3 (_RTCC_CC_CTRL_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_PRSSEL_PRSCH4 (_RTCC_CC_CTRL_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_PRSSEL_PRSCH5 (_RTCC_CC_CTRL_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_PRSSEL_PRSCH6 (_RTCC_CC_CTRL_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_PRSSEL_PRSCH7 (_RTCC_CC_CTRL_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_PRSSEL_PRSCH8 (_RTCC_CC_CTRL_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_PRSSEL_PRSCH9 (_RTCC_CC_CTRL_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_PRSSEL_PRSCH10 (_RTCC_CC_CTRL_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_PRSSEL_PRSCH11 (_RTCC_CC_CTRL_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_COMPBASE (0x1UL << 11) /**< Capture Compare Channel Comparison Base */
-#define _RTCC_CC_CTRL_COMPBASE_SHIFT 11 /**< Shift value for CC_COMPBASE */
-#define _RTCC_CC_CTRL_COMPBASE_MASK 0x800UL /**< Bit mask for CC_COMPBASE */
-#define _RTCC_CC_CTRL_COMPBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_COMPBASE_CNT 0x00000000UL /**< Mode CNT for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_COMPBASE_PRECNT 0x00000001UL /**< Mode PRECNT for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_COMPBASE_DEFAULT (_RTCC_CC_CTRL_COMPBASE_DEFAULT << 11) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_COMPBASE_CNT (_RTCC_CC_CTRL_COMPBASE_CNT << 11) /**< Shifted mode CNT for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_COMPBASE_PRECNT (_RTCC_CC_CTRL_COMPBASE_PRECNT << 11) /**< Shifted mode PRECNT for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_COMPMASK_SHIFT 12 /**< Shift value for CC_COMPMASK */
-#define _RTCC_CC_CTRL_COMPMASK_MASK 0x1F000UL /**< Bit mask for CC_COMPMASK */
-#define _RTCC_CC_CTRL_COMPMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_COMPMASK_DEFAULT (_RTCC_CC_CTRL_COMPMASK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_DAYCC (0x1UL << 17) /**< Day Capture/Compare Selection */
-#define _RTCC_CC_CTRL_DAYCC_SHIFT 17 /**< Shift value for CC_DAYCC */
-#define _RTCC_CC_CTRL_DAYCC_MASK 0x20000UL /**< Bit mask for CC_DAYCC */
-#define _RTCC_CC_CTRL_DAYCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_DAYCC_MONTH 0x00000000UL /**< Mode MONTH for RTCC_CC_CTRL */
-#define _RTCC_CC_CTRL_DAYCC_WEEK 0x00000001UL /**< Mode WEEK for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_DAYCC_DEFAULT (_RTCC_CC_CTRL_DAYCC_DEFAULT << 17) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_DAYCC_MONTH (_RTCC_CC_CTRL_DAYCC_MONTH << 17) /**< Shifted mode MONTH for RTCC_CC_CTRL */
-#define RTCC_CC_CTRL_DAYCC_WEEK (_RTCC_CC_CTRL_DAYCC_WEEK << 17) /**< Shifted mode WEEK for RTCC_CC_CTRL */
-
-/* Bit fields for RTCC CC_CCV */
-#define _RTCC_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CCV */
-#define _RTCC_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CC_CCV */
-#define _RTCC_CC_CCV_CCV_SHIFT 0 /**< Shift value for CC_CCV */
-#define _RTCC_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for CC_CCV */
-#define _RTCC_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CCV */
-#define RTCC_CC_CCV_CCV_DEFAULT (_RTCC_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CCV */
-
-/* Bit fields for RTCC CC_TIME */
-#define _RTCC_CC_TIME_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_TIME */
-#define _RTCC_CC_TIME_MASK 0x003F7F7FUL /**< Mask for RTCC_CC_TIME */
-#define _RTCC_CC_TIME_SECU_SHIFT 0 /**< Shift value for CC_SECU */
-#define _RTCC_CC_TIME_SECU_MASK 0xFUL /**< Bit mask for CC_SECU */
-#define _RTCC_CC_TIME_SECU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */
-#define RTCC_CC_TIME_SECU_DEFAULT (_RTCC_CC_TIME_SECU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
-#define _RTCC_CC_TIME_SECT_SHIFT 4 /**< Shift value for CC_SECT */
-#define _RTCC_CC_TIME_SECT_MASK 0x70UL /**< Bit mask for CC_SECT */
-#define _RTCC_CC_TIME_SECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */
-#define RTCC_CC_TIME_SECT_DEFAULT (_RTCC_CC_TIME_SECT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
-#define _RTCC_CC_TIME_MINU_SHIFT 8 /**< Shift value for CC_MINU */
-#define _RTCC_CC_TIME_MINU_MASK 0xF00UL /**< Bit mask for CC_MINU */
-#define _RTCC_CC_TIME_MINU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */
-#define RTCC_CC_TIME_MINU_DEFAULT (_RTCC_CC_TIME_MINU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
-#define _RTCC_CC_TIME_MINT_SHIFT 12 /**< Shift value for CC_MINT */
-#define _RTCC_CC_TIME_MINT_MASK 0x7000UL /**< Bit mask for CC_MINT */
-#define _RTCC_CC_TIME_MINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */
-#define RTCC_CC_TIME_MINT_DEFAULT (_RTCC_CC_TIME_MINT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
-#define _RTCC_CC_TIME_HOURU_SHIFT 16 /**< Shift value for CC_HOURU */
-#define _RTCC_CC_TIME_HOURU_MASK 0xF0000UL /**< Bit mask for CC_HOURU */
-#define _RTCC_CC_TIME_HOURU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */
-#define RTCC_CC_TIME_HOURU_DEFAULT (_RTCC_CC_TIME_HOURU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
-#define _RTCC_CC_TIME_HOURT_SHIFT 20 /**< Shift value for CC_HOURT */
-#define _RTCC_CC_TIME_HOURT_MASK 0x300000UL /**< Bit mask for CC_HOURT */
-#define _RTCC_CC_TIME_HOURT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */
-#define RTCC_CC_TIME_HOURT_DEFAULT (_RTCC_CC_TIME_HOURT_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
-
-/* Bit fields for RTCC CC_DATE */
-#define _RTCC_CC_DATE_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_DATE */
-#define _RTCC_CC_DATE_MASK 0x00001F3FUL /**< Mask for RTCC_CC_DATE */
-#define _RTCC_CC_DATE_DAYU_SHIFT 0 /**< Shift value for CC_DAYU */
-#define _RTCC_CC_DATE_DAYU_MASK 0xFUL /**< Bit mask for CC_DAYU */
-#define _RTCC_CC_DATE_DAYU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */
-#define RTCC_CC_DATE_DAYU_DEFAULT (_RTCC_CC_DATE_DAYU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_DATE */
-#define _RTCC_CC_DATE_DAYT_SHIFT 4 /**< Shift value for CC_DAYT */
-#define _RTCC_CC_DATE_DAYT_MASK 0x30UL /**< Bit mask for CC_DAYT */
-#define _RTCC_CC_DATE_DAYT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */
-#define RTCC_CC_DATE_DAYT_DEFAULT (_RTCC_CC_DATE_DAYT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_DATE */
-#define _RTCC_CC_DATE_MONTHU_SHIFT 8 /**< Shift value for CC_MONTHU */
-#define _RTCC_CC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for CC_MONTHU */
-#define _RTCC_CC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */
-#define RTCC_CC_DATE_MONTHU_DEFAULT (_RTCC_CC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CC_DATE */
-#define RTCC_CC_DATE_MONTHT (0x1UL << 12) /**< Month, Tens */
-#define _RTCC_CC_DATE_MONTHT_SHIFT 12 /**< Shift value for CC_MONTHT */
-#define _RTCC_CC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for CC_MONTHT */
-#define _RTCC_CC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */
-#define RTCC_CC_DATE_MONTHT_DEFAULT (_RTCC_CC_DATE_MONTHT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_DATE */
-
-/* Bit fields for RTCC RET_REG */
-#define _RTCC_RET_REG_RESETVALUE 0x00000000UL /**< Default value for RTCC_RET_REG */
-#define _RTCC_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for RTCC_RET_REG */
-#define _RTCC_RET_REG_REG_SHIFT 0 /**< Shift value for RET_REG */
-#define _RTCC_RET_REG_REG_MASK 0xFFFFFFFFUL /**< Bit mask for RET_REG */
-#define _RTCC_RET_REG_REG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_RET_REG */
-#define RTCC_RET_REG_REG_DEFAULT (_RTCC_RET_REG_REG_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_RET_REG */
-
-/** @} */
-/** @} End of group EFR32FG13P_RTCC */
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_smu.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_smu.h
deleted file mode 100644
index cef08c52..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_smu.h
+++ /dev/null
@@ -1,381 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_smu.h
- * @brief EFR32FG13P_SMU register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P_SMU SMU
- * @{
- * @brief EFR32FG13P_SMU Register Declaration
- *****************************************************************************/
-/** SMU Register Declaration */
-typedef struct {
- uint32_t RESERVED0[3]; /**< Reserved for future use **/
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
-
- uint32_t RESERVED1[9]; /**< Reserved for future use **/
- __IOM uint32_t PPUCTRL; /**< PPU Control Register */
- uint32_t RESERVED2[3]; /**< Reserved for future use **/
- __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */
- __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */
-
- uint32_t RESERVED3[14]; /**< Reserved for future use **/
- __IM uint32_t PPUFS; /**< PPU Fault Status */
-} SMU_TypeDef; /** @} */
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_SMU
- * @{
- * @defgroup EFR32FG13P_SMU_BitFields SMU Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for SMU IF */
-#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */
-#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */
-#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */
-#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */
-#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */
-#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */
-#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */
-
-/* Bit fields for SMU IFS */
-#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */
-#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */
-#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */
-#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */
-#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */
-#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */
-#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */
-
-/* Bit fields for SMU IFC */
-#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */
-#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */
-#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */
-#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */
-#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */
-#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */
-#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */
-
-/* Bit fields for SMU IEN */
-#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */
-#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */
-#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */
-#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */
-#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */
-#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */
-#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */
-
-/* Bit fields for SMU PPUCTRL */
-#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */
-#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */
-#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */
-#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */
-#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */
-#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */
-#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */
-
-/* Bit fields for SMU PPUPATD0 */
-#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */
-#define _SMU_PPUPATD0_MASK 0x0BFF7FA7UL /**< Mask for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */
-#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */
-#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */
-#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */
-#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */
-#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */
-#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_ADC0 (0x1UL << 2) /**< Analog to Digital Converter 0 access control bit */
-#define _SMU_PPUPATD0_ADC0_SHIFT 2 /**< Shift value for SMU_ADC0 */
-#define _SMU_PPUPATD0_ADC0_MASK 0x4UL /**< Bit mask for SMU_ADC0 */
-#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_CMU (0x1UL << 5) /**< Clock Management Unit access control bit */
-#define _SMU_PPUPATD0_CMU_SHIFT 5 /**< Shift value for SMU_CMU */
-#define _SMU_PPUPATD0_CMU_MASK 0x20UL /**< Bit mask for SMU_CMU */
-#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 7) /**< CryoTimer access control bit */
-#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 7 /**< Shift value for SMU_CRYOTIMER */
-#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x80UL /**< Bit mask for SMU_CRYOTIMER */
-#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 8) /**< Advanced Encryption Standard Accelerator 0 access control bit */
-#define _SMU_PPUPATD0_CRYPTO0_SHIFT 8 /**< Shift value for SMU_CRYPTO0 */
-#define _SMU_PPUPATD0_CRYPTO0_MASK 0x100UL /**< Bit mask for SMU_CRYPTO0 */
-#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_CRYPTO1 (0x1UL << 9) /**< Advanced Encryption Standard Accelerator 1 access control bit */
-#define _SMU_PPUPATD0_CRYPTO1_SHIFT 9 /**< Shift value for SMU_CRYPTO1 */
-#define _SMU_PPUPATD0_CRYPTO1_MASK 0x200UL /**< Bit mask for SMU_CRYPTO1 */
-#define _SMU_PPUPATD0_CRYPTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_CRYPTO1_DEFAULT (_SMU_PPUPATD0_CRYPTO1_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_CSEN (0x1UL << 10) /**< Capacitive touch sense module access control bit */
-#define _SMU_PPUPATD0_CSEN_SHIFT 10 /**< Shift value for SMU_CSEN */
-#define _SMU_PPUPATD0_CSEN_MASK 0x400UL /**< Bit mask for SMU_CSEN */
-#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_VDAC0 (0x1UL << 11) /**< Digital to Analog Converter 0 access control bit */
-#define _SMU_PPUPATD0_VDAC0_SHIFT 11 /**< Shift value for SMU_VDAC0 */
-#define _SMU_PPUPATD0_VDAC0_MASK 0x800UL /**< Bit mask for SMU_VDAC0 */
-#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_PRS (0x1UL << 12) /**< Peripheral Reflex System access control bit */
-#define _SMU_PPUPATD0_PRS_SHIFT 12 /**< Shift value for SMU_PRS */
-#define _SMU_PPUPATD0_PRS_MASK 0x1000UL /**< Bit mask for SMU_PRS */
-#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_EMU (0x1UL << 13) /**< Energy Management Unit access control bit */
-#define _SMU_PPUPATD0_EMU_SHIFT 13 /**< Shift value for SMU_EMU */
-#define _SMU_PPUPATD0_EMU_MASK 0x2000UL /**< Bit mask for SMU_EMU */
-#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_FPUEH (0x1UL << 14) /**< FPU Exception Handler access control bit */
-#define _SMU_PPUPATD0_FPUEH_SHIFT 14 /**< Shift value for SMU_FPUEH */
-#define _SMU_PPUPATD0_FPUEH_MASK 0x4000UL /**< Bit mask for SMU_FPUEH */
-#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_GPCRC (0x1UL << 16) /**< General Purpose CRC access control bit */
-#define _SMU_PPUPATD0_GPCRC_SHIFT 16 /**< Shift value for SMU_GPCRC */
-#define _SMU_PPUPATD0_GPCRC_MASK 0x10000UL /**< Bit mask for SMU_GPCRC */
-#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_GPIO (0x1UL << 17) /**< General purpose Input/Output access control bit */
-#define _SMU_PPUPATD0_GPIO_SHIFT 17 /**< Shift value for SMU_GPIO */
-#define _SMU_PPUPATD0_GPIO_MASK 0x20000UL /**< Bit mask for SMU_GPIO */
-#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_I2C0 (0x1UL << 18) /**< I2C 0 access control bit */
-#define _SMU_PPUPATD0_I2C0_SHIFT 18 /**< Shift value for SMU_I2C0 */
-#define _SMU_PPUPATD0_I2C0_MASK 0x40000UL /**< Bit mask for SMU_I2C0 */
-#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_I2C1 (0x1UL << 19) /**< I2C 1 access control bit */
-#define _SMU_PPUPATD0_I2C1_SHIFT 19 /**< Shift value for SMU_I2C1 */
-#define _SMU_PPUPATD0_I2C1_MASK 0x80000UL /**< Bit mask for SMU_I2C1 */
-#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_IDAC0 (0x1UL << 20) /**< Current Digital to Analog Converter 0 access control bit */
-#define _SMU_PPUPATD0_IDAC0_SHIFT 20 /**< Shift value for SMU_IDAC0 */
-#define _SMU_PPUPATD0_IDAC0_MASK 0x100000UL /**< Bit mask for SMU_IDAC0 */
-#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_MSC (0x1UL << 21) /**< Memory System Controller access control bit */
-#define _SMU_PPUPATD0_MSC_SHIFT 21 /**< Shift value for SMU_MSC */
-#define _SMU_PPUPATD0_MSC_MASK 0x200000UL /**< Bit mask for SMU_MSC */
-#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_LDMA (0x1UL << 22) /**< Linked Direct Memory Access Controller access control bit */
-#define _SMU_PPUPATD0_LDMA_SHIFT 22 /**< Shift value for SMU_LDMA */
-#define _SMU_PPUPATD0_LDMA_MASK 0x400000UL /**< Bit mask for SMU_LDMA */
-#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_LESENSE (0x1UL << 23) /**< Low Energy Sensor Interface access control bit */
-#define _SMU_PPUPATD0_LESENSE_SHIFT 23 /**< Shift value for SMU_LESENSE */
-#define _SMU_PPUPATD0_LESENSE_MASK 0x800000UL /**< Bit mask for SMU_LESENSE */
-#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_LETIMER0 (0x1UL << 24) /**< Low Energy Timer 0 access control bit */
-#define _SMU_PPUPATD0_LETIMER0_SHIFT 24 /**< Shift value for SMU_LETIMER0 */
-#define _SMU_PPUPATD0_LETIMER0_MASK 0x1000000UL /**< Bit mask for SMU_LETIMER0 */
-#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_LEUART0 (0x1UL << 25) /**< Low Energy UART 0 access control bit */
-#define _SMU_PPUPATD0_LEUART0_SHIFT 25 /**< Shift value for SMU_LEUART0 */
-#define _SMU_PPUPATD0_LEUART0_MASK 0x2000000UL /**< Bit mask for SMU_LEUART0 */
-#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_PCNT0 (0x1UL << 27) /**< Pulse Counter 0 access control bit */
-#define _SMU_PPUPATD0_PCNT0_SHIFT 27 /**< Shift value for SMU_PCNT0 */
-#define _SMU_PPUPATD0_PCNT0_MASK 0x8000000UL /**< Bit mask for SMU_PCNT0 */
-#define _SMU_PPUPATD0_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
-#define SMU_PPUPATD0_PCNT0_DEFAULT (_SMU_PPUPATD0_PCNT0_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
-
-/* Bit fields for SMU PPUPATD1 */
-#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */
-#define _SMU_PPUPATD1_MASK 0x00001FF7UL /**< Mask for SMU_PPUPATD1 */
-#define SMU_PPUPATD1_RMU (0x1UL << 0) /**< Reset Management Unit access control bit */
-#define _SMU_PPUPATD1_RMU_SHIFT 0 /**< Shift value for SMU_RMU */
-#define _SMU_PPUPATD1_RMU_MASK 0x1UL /**< Bit mask for SMU_RMU */
-#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
-#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
-#define SMU_PPUPATD1_RTCC (0x1UL << 1) /**< Real-Time Counter and Calendar access control bit */
-#define _SMU_PPUPATD1_RTCC_SHIFT 1 /**< Shift value for SMU_RTCC */
-#define _SMU_PPUPATD1_RTCC_MASK 0x2UL /**< Bit mask for SMU_RTCC */
-#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
-#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
-#define SMU_PPUPATD1_SMU (0x1UL << 2) /**< Security Management Unit access control bit */
-#define _SMU_PPUPATD1_SMU_SHIFT 2 /**< Shift value for SMU_SMU */
-#define _SMU_PPUPATD1_SMU_MASK 0x4UL /**< Bit mask for SMU_SMU */
-#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
-#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
-#define SMU_PPUPATD1_TIMER0 (0x1UL << 4) /**< Timer 0 access control bit */
-#define _SMU_PPUPATD1_TIMER0_SHIFT 4 /**< Shift value for SMU_TIMER0 */
-#define _SMU_PPUPATD1_TIMER0_MASK 0x10UL /**< Bit mask for SMU_TIMER0 */
-#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
-#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
-#define SMU_PPUPATD1_TIMER1 (0x1UL << 5) /**< Timer 1 access control bit */
-#define _SMU_PPUPATD1_TIMER1_SHIFT 5 /**< Shift value for SMU_TIMER1 */
-#define _SMU_PPUPATD1_TIMER1_MASK 0x20UL /**< Bit mask for SMU_TIMER1 */
-#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
-#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
-#define SMU_PPUPATD1_TRNG0 (0x1UL << 6) /**< True Random Number Generator 0 access control bit */
-#define _SMU_PPUPATD1_TRNG0_SHIFT 6 /**< Shift value for SMU_TRNG0 */
-#define _SMU_PPUPATD1_TRNG0_MASK 0x40UL /**< Bit mask for SMU_TRNG0 */
-#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
-#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
-#define SMU_PPUPATD1_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */
-#define _SMU_PPUPATD1_USART0_SHIFT 7 /**< Shift value for SMU_USART0 */
-#define _SMU_PPUPATD1_USART0_MASK 0x80UL /**< Bit mask for SMU_USART0 */
-#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
-#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
-#define SMU_PPUPATD1_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */
-#define _SMU_PPUPATD1_USART1_SHIFT 8 /**< Shift value for SMU_USART1 */
-#define _SMU_PPUPATD1_USART1_MASK 0x100UL /**< Bit mask for SMU_USART1 */
-#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
-#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
-#define SMU_PPUPATD1_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */
-#define _SMU_PPUPATD1_USART2_SHIFT 9 /**< Shift value for SMU_USART2 */
-#define _SMU_PPUPATD1_USART2_MASK 0x200UL /**< Bit mask for SMU_USART2 */
-#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
-#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
-#define SMU_PPUPATD1_WDOG0 (0x1UL << 10) /**< Watchdog 0 access control bit */
-#define _SMU_PPUPATD1_WDOG0_SHIFT 10 /**< Shift value for SMU_WDOG0 */
-#define _SMU_PPUPATD1_WDOG0_MASK 0x400UL /**< Bit mask for SMU_WDOG0 */
-#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
-#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
-#define SMU_PPUPATD1_WDOG1 (0x1UL << 11) /**< Watchdog 1 access control bit */
-#define _SMU_PPUPATD1_WDOG1_SHIFT 11 /**< Shift value for SMU_WDOG1 */
-#define _SMU_PPUPATD1_WDOG1_MASK 0x800UL /**< Bit mask for SMU_WDOG1 */
-#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
-#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
-#define SMU_PPUPATD1_WTIMER0 (0x1UL << 12) /**< Wide Timer 0 access control bit */
-#define _SMU_PPUPATD1_WTIMER0_SHIFT 12 /**< Shift value for SMU_WTIMER0 */
-#define _SMU_PPUPATD1_WTIMER0_MASK 0x1000UL /**< Bit mask for SMU_WTIMER0 */
-#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
-#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
-
-/* Bit fields for SMU PPUFS */
-#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */
-#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */
-#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */
-#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_ADC0 0x00000002UL /**< Mode ADC0 for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_CMU 0x00000005UL /**< Mode CMU for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000007UL /**< Mode CRYOTIMER for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x00000008UL /**< Mode CRYPTO0 for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_CRYPTO1 0x00000009UL /**< Mode CRYPTO1 for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000AUL /**< Mode CSEN for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000BUL /**< Mode VDAC0 for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_PRS 0x0000000CUL /**< Mode PRS for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_EMU 0x0000000DUL /**< Mode EMU for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_FPUEH 0x0000000EUL /**< Mode FPUEH for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000010UL /**< Mode GPCRC for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_GPIO 0x00000011UL /**< Mode GPIO for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_I2C0 0x00000012UL /**< Mode I2C0 for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_I2C1 0x00000013UL /**< Mode I2C1 for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000014UL /**< Mode IDAC0 for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_MSC 0x00000015UL /**< Mode MSC for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_LDMA 0x00000016UL /**< Mode LDMA for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_LESENSE 0x00000017UL /**< Mode LESENSE for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_LETIMER0 0x00000018UL /**< Mode LETIMER0 for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_LEUART0 0x00000019UL /**< Mode LEUART0 for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_PCNT0 0x0000001BUL /**< Mode PCNT0 for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_RMU 0x00000020UL /**< Mode RMU for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_RTCC 0x00000021UL /**< Mode RTCC for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_SMU 0x00000022UL /**< Mode SMU for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000024UL /**< Mode TIMER0 for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_TIMER1 0x00000025UL /**< Mode TIMER1 for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000026UL /**< Mode TRNG0 for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_USART0 0x00000027UL /**< Mode USART0 for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_USART1 0x00000028UL /**< Mode USART1 for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_USART2 0x00000029UL /**< Mode USART2 for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000002AUL /**< Mode WDOG0 for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000002BUL /**< Mode WDOG1 for SMU_PPUFS */
-#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000002CUL /**< Mode WTIMER0 for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_CRYPTO1 (_SMU_PPUFS_PERIPHID_CRYPTO1 << 0) /**< Shifted mode CRYPTO1 for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */
-#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */
-
-/** @} */
-/** @} End of group EFR32FG13P_SMU */
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_timer.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_timer.h
deleted file mode 100644
index e30cf46c..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_timer.h
+++ /dev/null
@@ -1,1589 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_timer.h
- * @brief EFR32FG13P_TIMER register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P_TIMER TIMER
- * @{
- * @brief EFR32FG13P_TIMER Register Declaration
- *****************************************************************************/
-/** TIMER Register Declaration */
-typedef struct {
- __IOM uint32_t CTRL; /**< Control Register */
- __IOM uint32_t CMD; /**< Command Register */
- __IM uint32_t STATUS; /**< Status Register */
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- __IOM uint32_t TOP; /**< Counter Top Value Register */
- __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */
- __IOM uint32_t CNT; /**< Counter Value Register */
- uint32_t RESERVED0[1]; /**< Reserved for future use **/
- __IOM uint32_t LOCK; /**< TIMER Configuration Lock Register */
- __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
- __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
- uint32_t RESERVED1[1]; /**< Reserved for future use **/
- __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */
-
- uint32_t RESERVED2[8]; /**< Reserved registers */
- TIMER_CC_TypeDef CC[4]; /**< Compare/Capture Channel */
-
- __IOM uint32_t DTCTRL; /**< DTI Control Register */
- __IOM uint32_t DTTIME; /**< DTI Time Control Register */
- __IOM uint32_t DTFC; /**< DTI Fault Configuration Register */
- __IOM uint32_t DTOGEN; /**< DTI Output Generation Enable Register */
- __IM uint32_t DTFAULT; /**< DTI Fault Register */
- __IOM uint32_t DTFAULTC; /**< DTI Fault Clear Register */
- __IOM uint32_t DTLOCK; /**< DTI Configuration Lock Register */
-} TIMER_TypeDef; /** @} */
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_TIMER
- * @{
- * @defgroup EFR32FG13P_TIMER_BitFields TIMER Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for TIMER CTRL */
-#define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */
-#define _TIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for TIMER_CTRL */
-#define _TIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
-#define _TIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
-#define _TIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
-#define _TIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CTRL */
-#define _TIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CTRL */
-#define _TIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CTRL */
-#define _TIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CTRL */
-#define TIMER_CTRL_MODE_DEFAULT (_TIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */
-#define TIMER_CTRL_MODE_UP (_TIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for TIMER_CTRL */
-#define TIMER_CTRL_MODE_DOWN (_TIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for TIMER_CTRL */
-#define TIMER_CTRL_MODE_UPDOWN (_TIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for TIMER_CTRL */
-#define TIMER_CTRL_MODE_QDEC (_TIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for TIMER_CTRL */
-#define TIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */
-#define _TIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */
-#define _TIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */
-#define _TIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
-#define TIMER_CTRL_SYNC_DEFAULT (_TIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_CTRL */
-#define TIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */
-#define _TIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */
-#define _TIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */
-#define _TIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
-#define TIMER_CTRL_OSMEN_DEFAULT (_TIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */
-#define TIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */
-#define _TIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */
-#define _TIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */
-#define _TIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
-#define _TIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for TIMER_CTRL */
-#define _TIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for TIMER_CTRL */
-#define TIMER_CTRL_QDM_DEFAULT (_TIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_CTRL */
-#define TIMER_CTRL_QDM_X2 (_TIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for TIMER_CTRL */
-#define TIMER_CTRL_QDM_X4 (_TIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for TIMER_CTRL */
-#define TIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */
-#define _TIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */
-#define _TIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */
-#define _TIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
-#define TIMER_CTRL_DEBUGRUN_DEFAULT (_TIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_CTRL */
-#define TIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */
-#define _TIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */
-#define _TIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */
-#define _TIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
-#define TIMER_CTRL_DMACLRACT_DEFAULT (_TIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_CTRL */
-#define _TIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */
-#define _TIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */
-#define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
-#define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */
-#define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */
-#define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */
-#define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */
-#define TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CTRL */
-#define TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for TIMER_CTRL */
-#define TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for TIMER_CTRL */
-#define TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for TIMER_CTRL */
-#define TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for TIMER_CTRL */
-#define _TIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */
-#define _TIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */
-#define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
-#define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */
-#define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */
-#define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */
-#define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */
-#define TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CTRL */
-#define TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for TIMER_CTRL */
-#define TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for TIMER_CTRL */
-#define TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for TIMER_CTRL */
-#define TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for TIMER_CTRL */
-#define TIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */
-#define _TIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */
-#define _TIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */
-#define _TIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
-#define TIMER_CTRL_X2CNT_DEFAULT (_TIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for TIMER_CTRL */
-#define TIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */
-#define _TIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */
-#define _TIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */
-#define _TIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
-#define TIMER_CTRL_DISSYNCOUT_DEFAULT (_TIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for TIMER_CTRL */
-#define _TIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */
-#define _TIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */
-#define _TIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
-#define _TIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for TIMER_CTRL */
-#define _TIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CTRL */
-#define _TIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CTRL */
-#define TIMER_CTRL_CLKSEL_DEFAULT (_TIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CTRL */
-#define TIMER_CTRL_CLKSEL_PRESCHFPERCLK (_TIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for TIMER_CTRL */
-#define TIMER_CTRL_CLKSEL_CC1 (_TIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for TIMER_CTRL */
-#define TIMER_CTRL_CLKSEL_TIMEROUF (_TIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for TIMER_CTRL */
-#define _TIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */
-#define _TIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */
-#define _TIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
-#define _TIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CTRL */
-#define _TIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CTRL */
-#define _TIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_CTRL */
-#define _TIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_CTRL */
-#define _TIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_CTRL */
-#define _TIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_CTRL */
-#define _TIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_CTRL */
-#define _TIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_CTRL */
-#define _TIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_CTRL */
-#define _TIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_CTRL */
-#define _TIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_CTRL */
-#define TIMER_CTRL_PRESC_DEFAULT (_TIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CTRL */
-#define TIMER_CTRL_PRESC_DIV1 (_TIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for TIMER_CTRL */
-#define TIMER_CTRL_PRESC_DIV2 (_TIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for TIMER_CTRL */
-#define TIMER_CTRL_PRESC_DIV4 (_TIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for TIMER_CTRL */
-#define TIMER_CTRL_PRESC_DIV8 (_TIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for TIMER_CTRL */
-#define TIMER_CTRL_PRESC_DIV16 (_TIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for TIMER_CTRL */
-#define TIMER_CTRL_PRESC_DIV32 (_TIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for TIMER_CTRL */
-#define TIMER_CTRL_PRESC_DIV64 (_TIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for TIMER_CTRL */
-#define TIMER_CTRL_PRESC_DIV128 (_TIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for TIMER_CTRL */
-#define TIMER_CTRL_PRESC_DIV256 (_TIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for TIMER_CTRL */
-#define TIMER_CTRL_PRESC_DIV512 (_TIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for TIMER_CTRL */
-#define TIMER_CTRL_PRESC_DIV1024 (_TIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for TIMER_CTRL */
-#define TIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */
-#define _TIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */
-#define _TIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */
-#define _TIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
-#define TIMER_CTRL_ATI_DEFAULT (_TIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_CTRL */
-#define TIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */
-#define _TIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */
-#define _TIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */
-#define _TIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
-#define TIMER_CTRL_RSSCOIST_DEFAULT (_TIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for TIMER_CTRL */
-
-/* Bit fields for TIMER CMD */
-#define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */
-#define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */
-#define TIMER_CMD_START (0x1UL << 0) /**< Start Timer */
-#define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */
-#define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */
-#define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */
-#define TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CMD */
-#define TIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */
-#define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */
-#define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */
-#define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */
-#define TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_CMD */
-
-/* Bit fields for TIMER STATUS */
-#define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */
-#define _TIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for TIMER_STATUS */
-#define TIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */
-#define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */
-#define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */
-#define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
-#define TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */
-#define TIMER_STATUS_DIR (0x1UL << 1) /**< Direction */
-#define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */
-#define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */
-#define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
-#define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */
-#define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */
-#define TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */
-#define TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for TIMER_STATUS */
-#define TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for TIMER_STATUS */
-#define TIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */
-#define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */
-#define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */
-#define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
-#define TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */
-#define TIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */
-#define _TIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */
-#define _TIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */
-#define _TIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
-#define TIMER_STATUS_CCVBV0_DEFAULT (_TIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */
-#define TIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */
-#define _TIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */
-#define _TIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */
-#define _TIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
-#define TIMER_STATUS_CCVBV1_DEFAULT (_TIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */
-#define TIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */
-#define _TIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */
-#define _TIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */
-#define _TIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
-#define TIMER_STATUS_CCVBV2_DEFAULT (_TIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */
-#define TIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */
-#define _TIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */
-#define _TIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */
-#define _TIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
-#define TIMER_STATUS_CCVBV3_DEFAULT (_TIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_STATUS */
-#define TIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */
-#define _TIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */
-#define _TIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */
-#define _TIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
-#define TIMER_STATUS_ICV0_DEFAULT (_TIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */
-#define TIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */
-#define _TIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */
-#define _TIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */
-#define _TIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
-#define TIMER_STATUS_ICV1_DEFAULT (_TIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */
-#define TIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */
-#define _TIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */
-#define _TIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */
-#define _TIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
-#define TIMER_STATUS_ICV2_DEFAULT (_TIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */
-#define TIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */
-#define _TIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */
-#define _TIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */
-#define _TIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
-#define TIMER_STATUS_ICV3_DEFAULT (_TIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for TIMER_STATUS */
-#define TIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */
-#define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */
-#define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */
-#define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
-#define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */
-#define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */
-#define TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */
-#define TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */
-#define TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */
-#define TIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */
-#define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */
-#define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */
-#define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
-#define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */
-#define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */
-#define TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */
-#define TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */
-#define TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */
-#define TIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */
-#define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */
-#define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */
-#define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
-#define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */
-#define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */
-#define TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */
-#define TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */
-#define TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */
-#define TIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */
-#define _TIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */
-#define _TIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */
-#define _TIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
-#define _TIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */
-#define _TIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */
-#define TIMER_STATUS_CCPOL3_DEFAULT (_TIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_STATUS */
-#define TIMER_STATUS_CCPOL3_LOWRISE (_TIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for TIMER_STATUS */
-#define TIMER_STATUS_CCPOL3_HIGHFALL (_TIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for TIMER_STATUS */
-
-/* Bit fields for TIMER IF */
-#define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */
-#define _TIMER_IF_MASK 0x00000FF7UL /**< Mask for TIMER_IF */
-#define TIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */
-#define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */
-#define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
-#define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
-#define TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IF */
-#define TIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */
-#define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */
-#define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
-#define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
-#define TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IF */
-#define TIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */
-#define _TIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
-#define _TIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
-#define _TIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
-#define TIMER_IF_DIRCHG_DEFAULT (_TIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IF */
-#define TIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */
-#define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
-#define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
-#define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
-#define TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IF */
-#define TIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */
-#define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
-#define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
-#define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
-#define TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IF */
-#define TIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */
-#define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
-#define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
-#define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
-#define TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IF */
-#define TIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */
-#define _TIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
-#define _TIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
-#define _TIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
-#define TIMER_IF_CC3_DEFAULT (_TIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IF */
-#define TIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */
-#define _TIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
-#define _TIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
-#define _TIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
-#define TIMER_IF_ICBOF0_DEFAULT (_TIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IF */
-#define TIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */
-#define _TIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
-#define _TIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
-#define _TIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
-#define TIMER_IF_ICBOF1_DEFAULT (_TIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IF */
-#define TIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */
-#define _TIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
-#define _TIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
-#define _TIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
-#define TIMER_IF_ICBOF2_DEFAULT (_TIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IF */
-#define TIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */
-#define _TIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
-#define _TIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
-#define _TIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
-#define TIMER_IF_ICBOF3_DEFAULT (_TIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IF */
-
-/* Bit fields for TIMER IFS */
-#define _TIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFS */
-#define _TIMER_IFS_MASK 0x00000FF7UL /**< Mask for TIMER_IFS */
-#define TIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */
-#define _TIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */
-#define _TIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
-#define _TIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
-#define TIMER_IFS_OF_DEFAULT (_TIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IFS */
-#define TIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */
-#define _TIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */
-#define _TIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
-#define _TIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
-#define TIMER_IFS_UF_DEFAULT (_TIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IFS */
-#define TIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */
-#define _TIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
-#define _TIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
-#define _TIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
-#define TIMER_IFS_DIRCHG_DEFAULT (_TIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IFS */
-#define TIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */
-#define _TIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
-#define _TIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
-#define _TIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
-#define TIMER_IFS_CC0_DEFAULT (_TIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IFS */
-#define TIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */
-#define _TIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
-#define _TIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
-#define _TIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
-#define TIMER_IFS_CC1_DEFAULT (_TIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IFS */
-#define TIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */
-#define _TIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
-#define _TIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
-#define _TIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
-#define TIMER_IFS_CC2_DEFAULT (_TIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IFS */
-#define TIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */
-#define _TIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
-#define _TIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
-#define _TIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
-#define TIMER_IFS_CC3_DEFAULT (_TIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IFS */
-#define TIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */
-#define _TIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
-#define _TIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
-#define _TIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
-#define TIMER_IFS_ICBOF0_DEFAULT (_TIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IFS */
-#define TIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */
-#define _TIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
-#define _TIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
-#define _TIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
-#define TIMER_IFS_ICBOF1_DEFAULT (_TIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IFS */
-#define TIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */
-#define _TIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
-#define _TIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
-#define _TIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
-#define TIMER_IFS_ICBOF2_DEFAULT (_TIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFS */
-#define TIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */
-#define _TIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
-#define _TIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
-#define _TIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
-#define TIMER_IFS_ICBOF3_DEFAULT (_TIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IFS */
-
-/* Bit fields for TIMER IFC */
-#define _TIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFC */
-#define _TIMER_IFC_MASK 0x00000FF7UL /**< Mask for TIMER_IFC */
-#define TIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */
-#define _TIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */
-#define _TIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
-#define _TIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
-#define TIMER_IFC_OF_DEFAULT (_TIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IFC */
-#define TIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */
-#define _TIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */
-#define _TIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
-#define _TIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
-#define TIMER_IFC_UF_DEFAULT (_TIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IFC */
-#define TIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */
-#define _TIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
-#define _TIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
-#define _TIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
-#define TIMER_IFC_DIRCHG_DEFAULT (_TIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IFC */
-#define TIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */
-#define _TIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
-#define _TIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
-#define _TIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
-#define TIMER_IFC_CC0_DEFAULT (_TIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IFC */
-#define TIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */
-#define _TIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
-#define _TIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
-#define _TIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
-#define TIMER_IFC_CC1_DEFAULT (_TIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IFC */
-#define TIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */
-#define _TIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
-#define _TIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
-#define _TIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
-#define TIMER_IFC_CC2_DEFAULT (_TIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IFC */
-#define TIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */
-#define _TIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
-#define _TIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
-#define _TIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
-#define TIMER_IFC_CC3_DEFAULT (_TIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IFC */
-#define TIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */
-#define _TIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
-#define _TIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
-#define _TIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
-#define TIMER_IFC_ICBOF0_DEFAULT (_TIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IFC */
-#define TIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */
-#define _TIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
-#define _TIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
-#define _TIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
-#define TIMER_IFC_ICBOF1_DEFAULT (_TIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IFC */
-#define TIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */
-#define _TIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
-#define _TIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
-#define _TIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
-#define TIMER_IFC_ICBOF2_DEFAULT (_TIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFC */
-#define TIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */
-#define _TIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
-#define _TIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
-#define _TIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
-#define TIMER_IFC_ICBOF3_DEFAULT (_TIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IFC */
-
-/* Bit fields for TIMER IEN */
-#define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */
-#define _TIMER_IEN_MASK 0x00000FF7UL /**< Mask for TIMER_IEN */
-#define TIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */
-#define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */
-#define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
-#define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
-#define TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IEN */
-#define TIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */
-#define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */
-#define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
-#define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
-#define TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IEN */
-#define TIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */
-#define _TIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
-#define _TIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
-#define _TIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
-#define TIMER_IEN_DIRCHG_DEFAULT (_TIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IEN */
-#define TIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */
-#define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
-#define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
-#define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
-#define TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IEN */
-#define TIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */
-#define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
-#define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
-#define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
-#define TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IEN */
-#define TIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */
-#define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
-#define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
-#define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
-#define TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IEN */
-#define TIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */
-#define _TIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
-#define _TIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
-#define _TIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
-#define TIMER_IEN_CC3_DEFAULT (_TIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IEN */
-#define TIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */
-#define _TIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
-#define _TIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
-#define _TIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
-#define TIMER_IEN_ICBOF0_DEFAULT (_TIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IEN */
-#define TIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */
-#define _TIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
-#define _TIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
-#define _TIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
-#define TIMER_IEN_ICBOF1_DEFAULT (_TIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IEN */
-#define TIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */
-#define _TIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
-#define _TIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
-#define _TIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
-#define TIMER_IEN_ICBOF2_DEFAULT (_TIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IEN */
-#define TIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */
-#define _TIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
-#define _TIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
-#define _TIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
-#define TIMER_IEN_ICBOF3_DEFAULT (_TIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IEN */
-
-/* Bit fields for TIMER TOP */
-#define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */
-#define _TIMER_TOP_MASK 0x0000FFFFUL /**< Mask for TIMER_TOP */
-#define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */
-#define _TIMER_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for TIMER_TOP */
-#define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */
-#define TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOP */
-
-/* Bit fields for TIMER TOPB */
-#define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */
-#define _TIMER_TOPB_MASK 0x0000FFFFUL /**< Mask for TIMER_TOPB */
-#define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */
-#define _TIMER_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for TIMER_TOPB */
-#define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */
-#define TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */
-
-/* Bit fields for TIMER CNT */
-#define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */
-#define _TIMER_CNT_MASK 0x0000FFFFUL /**< Mask for TIMER_CNT */
-#define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */
-#define _TIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for TIMER_CNT */
-#define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */
-#define TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CNT */
-
-/* Bit fields for TIMER LOCK */
-#define _TIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_LOCK */
-#define _TIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_LOCK */
-#define _TIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */
-#define _TIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */
-#define _TIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_LOCK */
-#define _TIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_LOCK */
-#define _TIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_LOCK */
-#define _TIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_LOCK */
-#define _TIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_LOCK */
-#define TIMER_LOCK_TIMERLOCKKEY_DEFAULT (_TIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_LOCK */
-#define TIMER_LOCK_TIMERLOCKKEY_LOCK (_TIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_LOCK */
-#define TIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_TIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_LOCK */
-#define TIMER_LOCK_TIMERLOCKKEY_LOCKED (_TIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_LOCK */
-#define TIMER_LOCK_TIMERLOCKKEY_UNLOCK (_TIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_LOCK */
-
-/* Bit fields for TIMER ROUTEPEN */
-#define _TIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTEPEN */
-#define _TIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for TIMER_ROUTEPEN */
-#define TIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */
-#define _TIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */
-#define _TIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */
-#define _TIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */
-#define TIMER_ROUTEPEN_CC0PEN_DEFAULT (_TIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */
-#define TIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */
-#define _TIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */
-#define _TIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */
-#define _TIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */
-#define TIMER_ROUTEPEN_CC1PEN_DEFAULT (_TIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */
-#define TIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */
-#define _TIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */
-#define _TIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */
-#define _TIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */
-#define TIMER_ROUTEPEN_CC2PEN_DEFAULT (_TIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */
-#define TIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */
-#define _TIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */
-#define _TIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */
-#define _TIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */
-#define TIMER_ROUTEPEN_CC3PEN_DEFAULT (_TIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */
-#define TIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */
-#define _TIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */
-#define _TIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */
-#define _TIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */
-#define TIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_TIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */
-#define TIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */
-#define _TIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */
-#define _TIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */
-#define _TIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */
-#define TIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_TIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */
-#define TIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */
-#define _TIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */
-#define _TIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */
-#define _TIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */
-#define TIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_TIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */
-
-/* Bit fields for TIMER ROUTELOC0 */
-#define _TIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */
-#define _TIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC0 (_TIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_DEFAULT (_TIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC1 (_TIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC2 (_TIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC3 (_TIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC4 (_TIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC5 (_TIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC6 (_TIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC7 (_TIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC8 (_TIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC9 (_TIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC10 (_TIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC11 (_TIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC12 (_TIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC13 (_TIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC14 (_TIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC15 (_TIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC16 (_TIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC17 (_TIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC18 (_TIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC19 (_TIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC20 (_TIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC21 (_TIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC22 (_TIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC23 (_TIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC24 (_TIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC25 (_TIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC26 (_TIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC27 (_TIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC28 (_TIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC29 (_TIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC30 (_TIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC0LOC_LOC31 (_TIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */
-#define _TIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC0 (_TIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_DEFAULT (_TIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC1 (_TIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC2 (_TIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC3 (_TIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC4 (_TIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC5 (_TIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC6 (_TIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC7 (_TIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC8 (_TIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC9 (_TIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC10 (_TIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC11 (_TIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC12 (_TIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC13 (_TIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC14 (_TIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC15 (_TIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC16 (_TIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC17 (_TIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC18 (_TIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC19 (_TIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC20 (_TIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC21 (_TIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC22 (_TIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC23 (_TIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC24 (_TIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC25 (_TIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC26 (_TIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC27 (_TIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC28 (_TIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC29 (_TIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC30 (_TIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC1LOC_LOC31 (_TIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */
-#define _TIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC0 (_TIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_DEFAULT (_TIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC1 (_TIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC2 (_TIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC3 (_TIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC4 (_TIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC5 (_TIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC6 (_TIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC7 (_TIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC8 (_TIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC9 (_TIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC10 (_TIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC11 (_TIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC12 (_TIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC13 (_TIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC14 (_TIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC15 (_TIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC16 (_TIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC17 (_TIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC18 (_TIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC19 (_TIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC20 (_TIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC21 (_TIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC22 (_TIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC23 (_TIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC24 (_TIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC25 (_TIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC26 (_TIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC27 (_TIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC28 (_TIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC29 (_TIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC30 (_TIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC2LOC_LOC31 (_TIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */
-#define _TIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */
-#define _TIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC0 (_TIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_DEFAULT (_TIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC1 (_TIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC2 (_TIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC3 (_TIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC4 (_TIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC5 (_TIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC6 (_TIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC7 (_TIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC8 (_TIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC9 (_TIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC10 (_TIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC11 (_TIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC12 (_TIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC13 (_TIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC14 (_TIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC15 (_TIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC16 (_TIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC17 (_TIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC18 (_TIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC19 (_TIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC20 (_TIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC21 (_TIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC22 (_TIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC23 (_TIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC24 (_TIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC25 (_TIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC26 (_TIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC27 (_TIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC28 (_TIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC29 (_TIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC30 (_TIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */
-#define TIMER_ROUTELOC0_CC3LOC_LOC31 (_TIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */
-
-/* Bit fields for TIMER ROUTELOC2 */
-#define _TIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */
-#define _TIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC0 (_TIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_TIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC1 (_TIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC2 (_TIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC3 (_TIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC4 (_TIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC5 (_TIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC6 (_TIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC7 (_TIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC8 (_TIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC9 (_TIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC10 (_TIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC11 (_TIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC12 (_TIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC13 (_TIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC14 (_TIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC15 (_TIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC16 (_TIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC17 (_TIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC18 (_TIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC19 (_TIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC20 (_TIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC21 (_TIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC22 (_TIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC23 (_TIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC24 (_TIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC25 (_TIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC26 (_TIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC27 (_TIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC28 (_TIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC29 (_TIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC30 (_TIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI0LOC_LOC31 (_TIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */
-#define _TIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC0 (_TIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_TIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC1 (_TIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC2 (_TIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC3 (_TIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC4 (_TIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC5 (_TIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC6 (_TIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC7 (_TIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC8 (_TIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC9 (_TIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC10 (_TIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC11 (_TIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC12 (_TIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC13 (_TIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC14 (_TIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC15 (_TIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC16 (_TIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC17 (_TIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC18 (_TIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC19 (_TIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC20 (_TIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC21 (_TIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC22 (_TIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC23 (_TIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC24 (_TIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC25 (_TIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC26 (_TIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC27 (_TIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC28 (_TIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC29 (_TIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC30 (_TIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI1LOC_LOC31 (_TIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */
-#define _TIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC2 */
-#define _TIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC0 (_TIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_TIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC1 (_TIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC2 (_TIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC3 (_TIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC4 (_TIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC5 (_TIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC6 (_TIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC7 (_TIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC8 (_TIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC9 (_TIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC10 (_TIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC11 (_TIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC12 (_TIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC13 (_TIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC14 (_TIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC15 (_TIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC16 (_TIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC17 (_TIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC18 (_TIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC19 (_TIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC20 (_TIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC21 (_TIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC22 (_TIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC23 (_TIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC24 (_TIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC25 (_TIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC26 (_TIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC27 (_TIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC28 (_TIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC29 (_TIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC30 (_TIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for TIMER_ROUTELOC2 */
-#define TIMER_ROUTELOC2_CDTI2LOC_LOC31 (_TIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for TIMER_ROUTELOC2 */
-
-/* Bit fields for TIMER CC_CTRL */
-#define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
-#define _TIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
-#define _TIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_MODE_DEFAULT (_TIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_MODE_OFF (_TIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_MODE_INPUTCAPTURE (_TIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_TIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_MODE_PWM (_TIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */
-#define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */
-#define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */
-#define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */
-#define _TIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */
-#define _TIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */
-#define _TIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_COIST_DEFAULT (_TIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */
-#define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */
-#define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */
-#define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */
-#define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */
-#define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */
-#define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */
-#define _TIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */
-#define _TIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_PRSSEL_DEFAULT (_TIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_PRSSEL_PRSCH0 (_TIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_PRSSEL_PRSCH1 (_TIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_PRSSEL_PRSCH2 (_TIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_PRSSEL_PRSCH3 (_TIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_PRSSEL_PRSCH4 (_TIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_PRSSEL_PRSCH5 (_TIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_PRSSEL_PRSCH6 (_TIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_PRSSEL_PRSCH7 (_TIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_PRSSEL_PRSCH8 (_TIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_PRSSEL_PRSCH9 (_TIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_PRSSEL_PRSCH10 (_TIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_PRSSEL_PRSCH11 (_TIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */
-#define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */
-#define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */
-#define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */
-#define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */
-#define _TIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */
-#define _TIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */
-#define _TIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_PRSCONF_DEFAULT (_TIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_PRSCONF_PULSE (_TIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_PRSCONF_LEVEL (_TIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */
-#define _TIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */
-#define _TIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */
-#define _TIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_INSEL_DEFAULT (_TIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_INSEL_PIN (_TIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_INSEL_PRS (_TIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */
-#define _TIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */
-#define _TIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */
-#define _TIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CTRL */
-#define _TIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_FILT_DEFAULT (_TIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_FILT_DISABLE (_TIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for TIMER_CC_CTRL */
-#define TIMER_CC_CTRL_FILT_ENABLE (_TIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for TIMER_CC_CTRL */
-
-/* Bit fields for TIMER CC_CCV */
-#define _TIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCV */
-#define _TIMER_CC_CCV_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCV */
-#define _TIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */
-#define _TIMER_CC_CCV_CCV_MASK 0xFFFFUL /**< Bit mask for TIMER_CCV */
-#define _TIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCV */
-#define TIMER_CC_CCV_CCV_DEFAULT (_TIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCV */
-
-/* Bit fields for TIMER CC_CCVP */
-#define _TIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVP */
-#define _TIMER_CC_CCVP_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVP */
-#define _TIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */
-#define _TIMER_CC_CCVP_CCVP_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVP */
-#define _TIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVP */
-#define TIMER_CC_CCVP_CCVP_DEFAULT (_TIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVP */
-
-/* Bit fields for TIMER CC_CCVB */
-#define _TIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVB */
-#define _TIMER_CC_CCVB_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVB */
-#define _TIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */
-#define _TIMER_CC_CCVB_CCVB_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVB */
-#define _TIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVB */
-#define TIMER_CC_CCVB_CCVB_DEFAULT (_TIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVB */
-
-/* Bit fields for TIMER DTCTRL */
-#define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */
-#define _TIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for TIMER_DTCTRL */
-#define TIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */
-#define _TIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */
-#define _TIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */
-#define _TIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
-#define TIMER_DTCTRL_DTEN_DEFAULT (_TIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
-#define TIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */
-#define _TIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */
-#define _TIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */
-#define _TIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
-#define _TIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCTRL */
-#define _TIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCTRL */
-#define TIMER_DTCTRL_DTDAS_DEFAULT (_TIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
-#define TIMER_DTCTRL_DTDAS_NORESTART (_TIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for TIMER_DTCTRL */
-#define TIMER_DTCTRL_DTDAS_RESTART (_TIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for TIMER_DTCTRL */
-#define TIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */
-#define _TIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */
-#define _TIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */
-#define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
-#define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
-#define TIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */
-#define _TIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */
-#define _TIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */
-#define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
-#define TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
-#define _TIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */
-#define _TIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */
-#define _TIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
-#define _TIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTCTRL */
-#define _TIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTCTRL */
-#define _TIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTCTRL */
-#define _TIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTCTRL */
-#define _TIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTCTRL */
-#define _TIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTCTRL */
-#define _TIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTCTRL */
-#define _TIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTCTRL */
-#define _TIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTCTRL */
-#define _TIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTCTRL */
-#define _TIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTCTRL */
-#define _TIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTCTRL */
-#define TIMER_DTCTRL_DTPRSSEL_DEFAULT (_TIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
-#define TIMER_DTCTRL_DTPRSSEL_PRSCH0 (_TIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for TIMER_DTCTRL */
-#define TIMER_DTCTRL_DTPRSSEL_PRSCH1 (_TIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for TIMER_DTCTRL */
-#define TIMER_DTCTRL_DTPRSSEL_PRSCH2 (_TIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for TIMER_DTCTRL */
-#define TIMER_DTCTRL_DTPRSSEL_PRSCH3 (_TIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for TIMER_DTCTRL */
-#define TIMER_DTCTRL_DTPRSSEL_PRSCH4 (_TIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for TIMER_DTCTRL */
-#define TIMER_DTCTRL_DTPRSSEL_PRSCH5 (_TIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for TIMER_DTCTRL */
-#define TIMER_DTCTRL_DTPRSSEL_PRSCH6 (_TIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for TIMER_DTCTRL */
-#define TIMER_DTCTRL_DTPRSSEL_PRSCH7 (_TIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for TIMER_DTCTRL */
-#define TIMER_DTCTRL_DTPRSSEL_PRSCH8 (_TIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for TIMER_DTCTRL */
-#define TIMER_DTCTRL_DTPRSSEL_PRSCH9 (_TIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for TIMER_DTCTRL */
-#define TIMER_DTCTRL_DTPRSSEL_PRSCH10 (_TIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for TIMER_DTCTRL */
-#define TIMER_DTCTRL_DTPRSSEL_PRSCH11 (_TIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for TIMER_DTCTRL */
-#define TIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */
-#define _TIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */
-#define _TIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */
-#define _TIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
-#define TIMER_DTCTRL_DTAR_DEFAULT (_TIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
-#define TIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */
-#define _TIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */
-#define _TIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */
-#define _TIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
-#define TIMER_DTCTRL_DTFATS_DEFAULT (_TIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
-#define TIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */
-#define _TIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */
-#define _TIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */
-#define _TIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
-#define TIMER_DTCTRL_DTPRSEN_DEFAULT (_TIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
-
-/* Bit fields for TIMER DTTIME */
-#define _TIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIME */
-#define _TIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for TIMER_DTTIME */
-#define _TIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */
-#define _TIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */
-#define _TIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */
-#define _TIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_DTTIME */
-#define _TIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_DTTIME */
-#define _TIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_DTTIME */
-#define _TIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_DTTIME */
-#define _TIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_DTTIME */
-#define _TIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_DTTIME */
-#define _TIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_DTTIME */
-#define _TIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_DTTIME */
-#define _TIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_DTTIME */
-#define _TIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_DTTIME */
-#define _TIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_DTTIME */
-#define TIMER_DTTIME_DTPRESC_DEFAULT (_TIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTTIME */
-#define TIMER_DTTIME_DTPRESC_DIV1 (_TIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for TIMER_DTTIME */
-#define TIMER_DTTIME_DTPRESC_DIV2 (_TIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for TIMER_DTTIME */
-#define TIMER_DTTIME_DTPRESC_DIV4 (_TIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for TIMER_DTTIME */
-#define TIMER_DTTIME_DTPRESC_DIV8 (_TIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for TIMER_DTTIME */
-#define TIMER_DTTIME_DTPRESC_DIV16 (_TIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for TIMER_DTTIME */
-#define TIMER_DTTIME_DTPRESC_DIV32 (_TIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for TIMER_DTTIME */
-#define TIMER_DTTIME_DTPRESC_DIV64 (_TIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for TIMER_DTTIME */
-#define TIMER_DTTIME_DTPRESC_DIV128 (_TIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for TIMER_DTTIME */
-#define TIMER_DTTIME_DTPRESC_DIV256 (_TIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for TIMER_DTTIME */
-#define TIMER_DTTIME_DTPRESC_DIV512 (_TIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for TIMER_DTTIME */
-#define TIMER_DTTIME_DTPRESC_DIV1024 (_TIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for TIMER_DTTIME */
-#define _TIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */
-#define _TIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */
-#define _TIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */
-#define TIMER_DTTIME_DTRISET_DEFAULT (_TIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_DTTIME */
-#define _TIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */
-#define _TIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */
-#define _TIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */
-#define TIMER_DTTIME_DTFALLT_DEFAULT (_TIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTTIME */
-
-/* Bit fields for TIMER DTFC */
-#define _TIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFC */
-#define _TIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for TIMER_DTFC */
-#define _TIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */
-#define _TIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */
-#define _TIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
-#define _TIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */
-#define _TIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */
-#define _TIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */
-#define _TIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */
-#define _TIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */
-#define _TIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */
-#define _TIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */
-#define _TIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */
-#define _TIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTFC */
-#define _TIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTFC */
-#define _TIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTFC */
-#define _TIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTFC */
-#define TIMER_DTFC_DTPRS0FSEL_DEFAULT (_TIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFC */
-#define TIMER_DTFC_DTPRS0FSEL_PRSCH0 (_TIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for TIMER_DTFC */
-#define TIMER_DTFC_DTPRS0FSEL_PRSCH1 (_TIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for TIMER_DTFC */
-#define TIMER_DTFC_DTPRS0FSEL_PRSCH2 (_TIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for TIMER_DTFC */
-#define TIMER_DTFC_DTPRS0FSEL_PRSCH3 (_TIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for TIMER_DTFC */
-#define TIMER_DTFC_DTPRS0FSEL_PRSCH4 (_TIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for TIMER_DTFC */
-#define TIMER_DTFC_DTPRS0FSEL_PRSCH5 (_TIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for TIMER_DTFC */
-#define TIMER_DTFC_DTPRS0FSEL_PRSCH6 (_TIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for TIMER_DTFC */
-#define TIMER_DTFC_DTPRS0FSEL_PRSCH7 (_TIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for TIMER_DTFC */
-#define TIMER_DTFC_DTPRS0FSEL_PRSCH8 (_TIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for TIMER_DTFC */
-#define TIMER_DTFC_DTPRS0FSEL_PRSCH9 (_TIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for TIMER_DTFC */
-#define TIMER_DTFC_DTPRS0FSEL_PRSCH10 (_TIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for TIMER_DTFC */
-#define TIMER_DTFC_DTPRS0FSEL_PRSCH11 (_TIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for TIMER_DTFC */
-#define _TIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */
-#define _TIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */
-#define _TIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
-#define _TIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */
-#define _TIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */
-#define _TIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */
-#define _TIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */
-#define _TIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */
-#define _TIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */
-#define _TIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */
-#define _TIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */
-#define _TIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTFC */
-#define _TIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTFC */
-#define _TIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTFC */
-#define _TIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTFC */
-#define TIMER_DTFC_DTPRS1FSEL_DEFAULT (_TIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_DTFC */
-#define TIMER_DTFC_DTPRS1FSEL_PRSCH0 (_TIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for TIMER_DTFC */
-#define TIMER_DTFC_DTPRS1FSEL_PRSCH1 (_TIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for TIMER_DTFC */
-#define TIMER_DTFC_DTPRS1FSEL_PRSCH2 (_TIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for TIMER_DTFC */
-#define TIMER_DTFC_DTPRS1FSEL_PRSCH3 (_TIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for TIMER_DTFC */
-#define TIMER_DTFC_DTPRS1FSEL_PRSCH4 (_TIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for TIMER_DTFC */
-#define TIMER_DTFC_DTPRS1FSEL_PRSCH5 (_TIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for TIMER_DTFC */
-#define TIMER_DTFC_DTPRS1FSEL_PRSCH6 (_TIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for TIMER_DTFC */
-#define TIMER_DTFC_DTPRS1FSEL_PRSCH7 (_TIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for TIMER_DTFC */
-#define TIMER_DTFC_DTPRS1FSEL_PRSCH8 (_TIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for TIMER_DTFC */
-#define TIMER_DTFC_DTPRS1FSEL_PRSCH9 (_TIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for TIMER_DTFC */
-#define TIMER_DTFC_DTPRS1FSEL_PRSCH10 (_TIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for TIMER_DTFC */
-#define TIMER_DTFC_DTPRS1FSEL_PRSCH11 (_TIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for TIMER_DTFC */
-#define _TIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */
-#define _TIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */
-#define _TIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
-#define _TIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFC */
-#define _TIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFC */
-#define _TIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFC */
-#define _TIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFC */
-#define TIMER_DTFC_DTFA_DEFAULT (_TIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTFC */
-#define TIMER_DTFC_DTFA_NONE (_TIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for TIMER_DTFC */
-#define TIMER_DTFC_DTFA_INACTIVE (_TIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for TIMER_DTFC */
-#define TIMER_DTFC_DTFA_CLEAR (_TIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for TIMER_DTFC */
-#define TIMER_DTFC_DTFA_TRISTATE (_TIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for TIMER_DTFC */
-#define TIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */
-#define _TIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */
-#define _TIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */
-#define _TIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
-#define TIMER_DTFC_DTPRS0FEN_DEFAULT (_TIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTFC */
-#define TIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */
-#define _TIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */
-#define _TIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */
-#define _TIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
-#define TIMER_DTFC_DTPRS1FEN_DEFAULT (_TIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_DTFC */
-#define TIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */
-#define _TIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */
-#define _TIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */
-#define _TIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
-#define TIMER_DTFC_DTDBGFEN_DEFAULT (_TIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_DTFC */
-#define TIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */
-#define _TIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */
-#define _TIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */
-#define _TIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
-#define TIMER_DTFC_DTLOCKUPFEN_DEFAULT (_TIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_DTFC */
-
-/* Bit fields for TIMER DTOGEN */
-#define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */
-#define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */
-#define TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */
-#define _TIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */
-#define _TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */
-#define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
-#define TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
-#define TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */
-#define _TIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */
-#define _TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */
-#define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
-#define TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
-#define TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */
-#define _TIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */
-#define _TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */
-#define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
-#define TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
-#define TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */
-#define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */
-#define _TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */
-#define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
-#define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
-#define TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */
-#define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */
-#define _TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */
-#define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
-#define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
-#define TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */
-#define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */
-#define _TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */
-#define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
-#define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
-
-/* Bit fields for TIMER DTFAULT */
-#define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */
-#define _TIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULT */
-#define TIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */
-#define _TIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */
-#define _TIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */
-#define _TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */
-#define TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
-#define TIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */
-#define _TIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */
-#define _TIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */
-#define _TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */
-#define TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
-#define TIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */
-#define _TIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */
-#define _TIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */
-#define _TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */
-#define TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
-#define TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */
-#define _TIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */
-#define _TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */
-#define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */
-#define TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
-
-/* Bit fields for TIMER DTFAULTC */
-#define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */
-#define _TIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULTC */
-#define TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */
-#define _TIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */
-#define _TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */
-#define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */
-#define TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
-#define TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */
-#define _TIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */
-#define _TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */
-#define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */
-#define TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
-#define TIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */
-#define _TIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */
-#define _TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */
-#define _TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */
-#define TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
-#define TIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */
-#define _TIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */
-#define _TIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */
-#define _TIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */
-#define TIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
-
-/* Bit fields for TIMER DTLOCK */
-#define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */
-#define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */
-#define _TIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
-#define _TIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
-#define _TIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */
-#define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_DTLOCK */
-#define _TIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_DTLOCK */
-#define _TIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_DTLOCK */
-#define _TIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */
-#define TIMER_DTLOCK_LOCKKEY_DEFAULT (_TIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */
-#define TIMER_DTLOCK_LOCKKEY_LOCK (_TIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_DTLOCK */
-#define TIMER_DTLOCK_LOCKKEY_UNLOCKED (_TIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_DTLOCK */
-#define TIMER_DTLOCK_LOCKKEY_LOCKED (_TIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_DTLOCK */
-#define TIMER_DTLOCK_LOCKKEY_UNLOCK (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */
-
-/** @} */
-/** @} End of group EFR32FG13P_TIMER */
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_trng.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_trng.h
deleted file mode 100644
index ad2ee342..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_trng.h
+++ /dev/null
@@ -1,288 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_trng.h
- * @brief EFR32FG13P_TRNG register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P_TRNG TRNG
- * @{
- * @brief EFR32FG13P_TRNG Register Declaration
- *****************************************************************************/
-/** TRNG Register Declaration */
-typedef struct {
- __IOM uint32_t CONTROL; /**< Main Control Register */
- __IM uint32_t FIFOLEVEL; /**< FIFO Level Register */
- uint32_t RESERVED0[1]; /**< Reserved for future use **/
- __IM uint32_t FIFODEPTH; /**< FIFO Depth Register */
- __IOM uint32_t KEY0; /**< Key Register 0 */
- __IOM uint32_t KEY1; /**< Key Register 1 */
- __IOM uint32_t KEY2; /**< Key Register 2 */
- __IOM uint32_t KEY3; /**< Key Register 3 */
- __IOM uint32_t TESTDATA; /**< Test Data Register */
-
- uint32_t RESERVED1[3]; /**< Reserved for future use **/
- __IOM uint32_t STATUS; /**< Status Register */
- __IOM uint32_t INITWAITVAL; /**< Initial Wait Counter */
- uint32_t RESERVED2[50]; /**< Reserved for future use **/
- __IM uint32_t FIFO; /**< FIFO Data */
-} TRNG_TypeDef; /** @} */
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_TRNG
- * @{
- * @defgroup EFR32FG13P_TRNG_BitFields TRNG Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for TRNG CONTROL */
-#define _TRNG_CONTROL_RESETVALUE 0x00000000UL /**< Default value for TRNG_CONTROL */
-#define _TRNG_CONTROL_MASK 0x00003FFDUL /**< Mask for TRNG_CONTROL */
-#define TRNG_CONTROL_ENABLE (0x1UL << 0) /**< TRNG Module Enable */
-#define _TRNG_CONTROL_ENABLE_SHIFT 0 /**< Shift value for TRNG_ENABLE */
-#define _TRNG_CONTROL_ENABLE_MASK 0x1UL /**< Bit mask for TRNG_ENABLE */
-#define _TRNG_CONTROL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
-#define _TRNG_CONTROL_ENABLE_DISABLED 0x00000000UL /**< Mode DISABLED for TRNG_CONTROL */
-#define _TRNG_CONTROL_ENABLE_ENABLED 0x00000001UL /**< Mode ENABLED for TRNG_CONTROL */
-#define TRNG_CONTROL_ENABLE_DEFAULT (_TRNG_CONTROL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_CONTROL */
-#define TRNG_CONTROL_ENABLE_DISABLED (_TRNG_CONTROL_ENABLE_DISABLED << 0) /**< Shifted mode DISABLED for TRNG_CONTROL */
-#define TRNG_CONTROL_ENABLE_ENABLED (_TRNG_CONTROL_ENABLE_ENABLED << 0) /**< Shifted mode ENABLED for TRNG_CONTROL */
-#define TRNG_CONTROL_TESTEN (0x1UL << 2) /**< Test Enable */
-#define _TRNG_CONTROL_TESTEN_SHIFT 2 /**< Shift value for TRNG_TESTEN */
-#define _TRNG_CONTROL_TESTEN_MASK 0x4UL /**< Bit mask for TRNG_TESTEN */
-#define _TRNG_CONTROL_TESTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
-#define _TRNG_CONTROL_TESTEN_NOISE 0x00000000UL /**< Mode NOISE for TRNG_CONTROL */
-#define _TRNG_CONTROL_TESTEN_TESTDATA 0x00000001UL /**< Mode TESTDATA for TRNG_CONTROL */
-#define TRNG_CONTROL_TESTEN_DEFAULT (_TRNG_CONTROL_TESTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for TRNG_CONTROL */
-#define TRNG_CONTROL_TESTEN_NOISE (_TRNG_CONTROL_TESTEN_NOISE << 2) /**< Shifted mode NOISE for TRNG_CONTROL */
-#define TRNG_CONTROL_TESTEN_TESTDATA (_TRNG_CONTROL_TESTEN_TESTDATA << 2) /**< Shifted mode TESTDATA for TRNG_CONTROL */
-#define TRNG_CONTROL_CONDBYPASS (0x1UL << 3) /**< Conditioning Bypass */
-#define _TRNG_CONTROL_CONDBYPASS_SHIFT 3 /**< Shift value for TRNG_CONDBYPASS */
-#define _TRNG_CONTROL_CONDBYPASS_MASK 0x8UL /**< Bit mask for TRNG_CONDBYPASS */
-#define _TRNG_CONTROL_CONDBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
-#define _TRNG_CONTROL_CONDBYPASS_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */
-#define _TRNG_CONTROL_CONDBYPASS_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */
-#define TRNG_CONTROL_CONDBYPASS_DEFAULT (_TRNG_CONTROL_CONDBYPASS_DEFAULT << 3) /**< Shifted mode DEFAULT for TRNG_CONTROL */
-#define TRNG_CONTROL_CONDBYPASS_NORMAL (_TRNG_CONTROL_CONDBYPASS_NORMAL << 3) /**< Shifted mode NORMAL for TRNG_CONTROL */
-#define TRNG_CONTROL_CONDBYPASS_BYPASS (_TRNG_CONTROL_CONDBYPASS_BYPASS << 3) /**< Shifted mode BYPASS for TRNG_CONTROL */
-#define TRNG_CONTROL_REPCOUNTIEN (0x1UL << 4) /**< Interrupt Enable for Repetition Count Test Failure */
-#define _TRNG_CONTROL_REPCOUNTIEN_SHIFT 4 /**< Shift value for TRNG_REPCOUNTIEN */
-#define _TRNG_CONTROL_REPCOUNTIEN_MASK 0x10UL /**< Bit mask for TRNG_REPCOUNTIEN */
-#define _TRNG_CONTROL_REPCOUNTIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
-#define TRNG_CONTROL_REPCOUNTIEN_DEFAULT (_TRNG_CONTROL_REPCOUNTIEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TRNG_CONTROL */
-#define TRNG_CONTROL_APT64IEN (0x1UL << 5) /**< Interrupt Enable for Adaptive Proportion Test Failure (64-sample Window) */
-#define _TRNG_CONTROL_APT64IEN_SHIFT 5 /**< Shift value for TRNG_APT64IEN */
-#define _TRNG_CONTROL_APT64IEN_MASK 0x20UL /**< Bit mask for TRNG_APT64IEN */
-#define _TRNG_CONTROL_APT64IEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
-#define TRNG_CONTROL_APT64IEN_DEFAULT (_TRNG_CONTROL_APT64IEN_DEFAULT << 5) /**< Shifted mode DEFAULT for TRNG_CONTROL */
-#define TRNG_CONTROL_APT4096IEN (0x1UL << 6) /**< Interrupt Enable for Adaptive Proportion Test Failure (4096-sample Window) */
-#define _TRNG_CONTROL_APT4096IEN_SHIFT 6 /**< Shift value for TRNG_APT4096IEN */
-#define _TRNG_CONTROL_APT4096IEN_MASK 0x40UL /**< Bit mask for TRNG_APT4096IEN */
-#define _TRNG_CONTROL_APT4096IEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
-#define TRNG_CONTROL_APT4096IEN_DEFAULT (_TRNG_CONTROL_APT4096IEN_DEFAULT << 6) /**< Shifted mode DEFAULT for TRNG_CONTROL */
-#define TRNG_CONTROL_FULLIEN (0x1UL << 7) /**< Interrupt Enable for FIFO Full */
-#define _TRNG_CONTROL_FULLIEN_SHIFT 7 /**< Shift value for TRNG_FULLIEN */
-#define _TRNG_CONTROL_FULLIEN_MASK 0x80UL /**< Bit mask for TRNG_FULLIEN */
-#define _TRNG_CONTROL_FULLIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
-#define TRNG_CONTROL_FULLIEN_DEFAULT (_TRNG_CONTROL_FULLIEN_DEFAULT << 7) /**< Shifted mode DEFAULT for TRNG_CONTROL */
-#define TRNG_CONTROL_SOFTRESET (0x1UL << 8) /**< Software Reset */
-#define _TRNG_CONTROL_SOFTRESET_SHIFT 8 /**< Shift value for TRNG_SOFTRESET */
-#define _TRNG_CONTROL_SOFTRESET_MASK 0x100UL /**< Bit mask for TRNG_SOFTRESET */
-#define _TRNG_CONTROL_SOFTRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
-#define _TRNG_CONTROL_SOFTRESET_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */
-#define _TRNG_CONTROL_SOFTRESET_RESET 0x00000001UL /**< Mode RESET for TRNG_CONTROL */
-#define TRNG_CONTROL_SOFTRESET_DEFAULT (_TRNG_CONTROL_SOFTRESET_DEFAULT << 8) /**< Shifted mode DEFAULT for TRNG_CONTROL */
-#define TRNG_CONTROL_SOFTRESET_NORMAL (_TRNG_CONTROL_SOFTRESET_NORMAL << 8) /**< Shifted mode NORMAL for TRNG_CONTROL */
-#define TRNG_CONTROL_SOFTRESET_RESET (_TRNG_CONTROL_SOFTRESET_RESET << 8) /**< Shifted mode RESET for TRNG_CONTROL */
-#define TRNG_CONTROL_PREIEN (0x1UL << 9) /**< Interrupt enable for AIS31 preliminary noise alarm */
-#define _TRNG_CONTROL_PREIEN_SHIFT 9 /**< Shift value for TRNG_PREIEN */
-#define _TRNG_CONTROL_PREIEN_MASK 0x200UL /**< Bit mask for TRNG_PREIEN */
-#define _TRNG_CONTROL_PREIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
-#define TRNG_CONTROL_PREIEN_DEFAULT (_TRNG_CONTROL_PREIEN_DEFAULT << 9) /**< Shifted mode DEFAULT for TRNG_CONTROL */
-#define TRNG_CONTROL_ALMIEN (0x1UL << 10) /**< Interrupt enable for AIS31 noise alarm */
-#define _TRNG_CONTROL_ALMIEN_SHIFT 10 /**< Shift value for TRNG_ALMIEN */
-#define _TRNG_CONTROL_ALMIEN_MASK 0x400UL /**< Bit mask for TRNG_ALMIEN */
-#define _TRNG_CONTROL_ALMIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
-#define TRNG_CONTROL_ALMIEN_DEFAULT (_TRNG_CONTROL_ALMIEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TRNG_CONTROL */
-#define TRNG_CONTROL_FORCERUN (0x1UL << 11) /**< Oscillator Force Run */
-#define _TRNG_CONTROL_FORCERUN_SHIFT 11 /**< Shift value for TRNG_FORCERUN */
-#define _TRNG_CONTROL_FORCERUN_MASK 0x800UL /**< Bit mask for TRNG_FORCERUN */
-#define _TRNG_CONTROL_FORCERUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
-#define _TRNG_CONTROL_FORCERUN_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */
-#define _TRNG_CONTROL_FORCERUN_RUN 0x00000001UL /**< Mode RUN for TRNG_CONTROL */
-#define TRNG_CONTROL_FORCERUN_DEFAULT (_TRNG_CONTROL_FORCERUN_DEFAULT << 11) /**< Shifted mode DEFAULT for TRNG_CONTROL */
-#define TRNG_CONTROL_FORCERUN_NORMAL (_TRNG_CONTROL_FORCERUN_NORMAL << 11) /**< Shifted mode NORMAL for TRNG_CONTROL */
-#define TRNG_CONTROL_FORCERUN_RUN (_TRNG_CONTROL_FORCERUN_RUN << 11) /**< Shifted mode RUN for TRNG_CONTROL */
-#define TRNG_CONTROL_BYPNIST (0x1UL << 12) /**< NIST Start-up Test Bypass. */
-#define _TRNG_CONTROL_BYPNIST_SHIFT 12 /**< Shift value for TRNG_BYPNIST */
-#define _TRNG_CONTROL_BYPNIST_MASK 0x1000UL /**< Bit mask for TRNG_BYPNIST */
-#define _TRNG_CONTROL_BYPNIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
-#define _TRNG_CONTROL_BYPNIST_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */
-#define _TRNG_CONTROL_BYPNIST_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */
-#define TRNG_CONTROL_BYPNIST_DEFAULT (_TRNG_CONTROL_BYPNIST_DEFAULT << 12) /**< Shifted mode DEFAULT for TRNG_CONTROL */
-#define TRNG_CONTROL_BYPNIST_NORMAL (_TRNG_CONTROL_BYPNIST_NORMAL << 12) /**< Shifted mode NORMAL for TRNG_CONTROL */
-#define TRNG_CONTROL_BYPNIST_BYPASS (_TRNG_CONTROL_BYPNIST_BYPASS << 12) /**< Shifted mode BYPASS for TRNG_CONTROL */
-#define TRNG_CONTROL_BYPAIS31 (0x1UL << 13) /**< AIS31 Start-up Test Bypass. */
-#define _TRNG_CONTROL_BYPAIS31_SHIFT 13 /**< Shift value for TRNG_BYPAIS31 */
-#define _TRNG_CONTROL_BYPAIS31_MASK 0x2000UL /**< Bit mask for TRNG_BYPAIS31 */
-#define _TRNG_CONTROL_BYPAIS31_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
-#define _TRNG_CONTROL_BYPAIS31_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */
-#define _TRNG_CONTROL_BYPAIS31_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */
-#define TRNG_CONTROL_BYPAIS31_DEFAULT (_TRNG_CONTROL_BYPAIS31_DEFAULT << 13) /**< Shifted mode DEFAULT for TRNG_CONTROL */
-#define TRNG_CONTROL_BYPAIS31_NORMAL (_TRNG_CONTROL_BYPAIS31_NORMAL << 13) /**< Shifted mode NORMAL for TRNG_CONTROL */
-#define TRNG_CONTROL_BYPAIS31_BYPASS (_TRNG_CONTROL_BYPAIS31_BYPASS << 13) /**< Shifted mode BYPASS for TRNG_CONTROL */
-
-/* Bit fields for TRNG FIFOLEVEL */
-#define _TRNG_FIFOLEVEL_RESETVALUE 0x00000000UL /**< Default value for TRNG_FIFOLEVEL */
-#define _TRNG_FIFOLEVEL_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFOLEVEL */
-#define _TRNG_FIFOLEVEL_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
-#define _TRNG_FIFOLEVEL_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
-#define _TRNG_FIFOLEVEL_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_FIFOLEVEL */
-#define TRNG_FIFOLEVEL_VALUE_DEFAULT (_TRNG_FIFOLEVEL_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFOLEVEL */
-
-/* Bit fields for TRNG FIFODEPTH */
-#define _TRNG_FIFODEPTH_RESETVALUE 0x00000040UL /**< Default value for TRNG_FIFODEPTH */
-#define _TRNG_FIFODEPTH_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFODEPTH */
-#define _TRNG_FIFODEPTH_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
-#define _TRNG_FIFODEPTH_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
-#define _TRNG_FIFODEPTH_VALUE_DEFAULT 0x00000040UL /**< Mode DEFAULT for TRNG_FIFODEPTH */
-#define TRNG_FIFODEPTH_VALUE_DEFAULT (_TRNG_FIFODEPTH_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFODEPTH */
-
-/* Bit fields for TRNG KEY0 */
-#define _TRNG_KEY0_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY0 */
-#define _TRNG_KEY0_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY0 */
-#define _TRNG_KEY0_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
-#define _TRNG_KEY0_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
-#define _TRNG_KEY0_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY0 */
-#define TRNG_KEY0_VALUE_DEFAULT (_TRNG_KEY0_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY0 */
-
-/* Bit fields for TRNG KEY1 */
-#define _TRNG_KEY1_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY1 */
-#define _TRNG_KEY1_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY1 */
-#define _TRNG_KEY1_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
-#define _TRNG_KEY1_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
-#define _TRNG_KEY1_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY1 */
-#define TRNG_KEY1_VALUE_DEFAULT (_TRNG_KEY1_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY1 */
-
-/* Bit fields for TRNG KEY2 */
-#define _TRNG_KEY2_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY2 */
-#define _TRNG_KEY2_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY2 */
-#define _TRNG_KEY2_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
-#define _TRNG_KEY2_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
-#define _TRNG_KEY2_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY2 */
-#define TRNG_KEY2_VALUE_DEFAULT (_TRNG_KEY2_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY2 */
-
-/* Bit fields for TRNG KEY3 */
-#define _TRNG_KEY3_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY3 */
-#define _TRNG_KEY3_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY3 */
-#define _TRNG_KEY3_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
-#define _TRNG_KEY3_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
-#define _TRNG_KEY3_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY3 */
-#define TRNG_KEY3_VALUE_DEFAULT (_TRNG_KEY3_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY3 */
-
-/* Bit fields for TRNG TESTDATA */
-#define _TRNG_TESTDATA_RESETVALUE 0x00000000UL /**< Default value for TRNG_TESTDATA */
-#define _TRNG_TESTDATA_MASK 0xFFFFFFFFUL /**< Mask for TRNG_TESTDATA */
-#define _TRNG_TESTDATA_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
-#define _TRNG_TESTDATA_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
-#define _TRNG_TESTDATA_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_TESTDATA */
-#define TRNG_TESTDATA_VALUE_DEFAULT (_TRNG_TESTDATA_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_TESTDATA */
-
-/* Bit fields for TRNG STATUS */
-#define _TRNG_STATUS_RESETVALUE 0x00000000UL /**< Default value for TRNG_STATUS */
-#define _TRNG_STATUS_MASK 0x000003F1UL /**< Mask for TRNG_STATUS */
-#define TRNG_STATUS_TESTDATABUSY (0x1UL << 0) /**< Test Data Busy */
-#define _TRNG_STATUS_TESTDATABUSY_SHIFT 0 /**< Shift value for TRNG_TESTDATABUSY */
-#define _TRNG_STATUS_TESTDATABUSY_MASK 0x1UL /**< Bit mask for TRNG_TESTDATABUSY */
-#define _TRNG_STATUS_TESTDATABUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */
-#define _TRNG_STATUS_TESTDATABUSY_IDLE 0x00000000UL /**< Mode IDLE for TRNG_STATUS */
-#define _TRNG_STATUS_TESTDATABUSY_BUSY 0x00000001UL /**< Mode BUSY for TRNG_STATUS */
-#define TRNG_STATUS_TESTDATABUSY_DEFAULT (_TRNG_STATUS_TESTDATABUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_STATUS */
-#define TRNG_STATUS_TESTDATABUSY_IDLE (_TRNG_STATUS_TESTDATABUSY_IDLE << 0) /**< Shifted mode IDLE for TRNG_STATUS */
-#define TRNG_STATUS_TESTDATABUSY_BUSY (_TRNG_STATUS_TESTDATABUSY_BUSY << 0) /**< Shifted mode BUSY for TRNG_STATUS */
-#define TRNG_STATUS_REPCOUNTIF (0x1UL << 4) /**< Repetition Count Test Interrupt Status */
-#define _TRNG_STATUS_REPCOUNTIF_SHIFT 4 /**< Shift value for TRNG_REPCOUNTIF */
-#define _TRNG_STATUS_REPCOUNTIF_MASK 0x10UL /**< Bit mask for TRNG_REPCOUNTIF */
-#define _TRNG_STATUS_REPCOUNTIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */
-#define TRNG_STATUS_REPCOUNTIF_DEFAULT (_TRNG_STATUS_REPCOUNTIF_DEFAULT << 4) /**< Shifted mode DEFAULT for TRNG_STATUS */
-#define TRNG_STATUS_APT64IF (0x1UL << 5) /**< Adaptive Proportion test failure (64-sample window) interrupt status */
-#define _TRNG_STATUS_APT64IF_SHIFT 5 /**< Shift value for TRNG_APT64IF */
-#define _TRNG_STATUS_APT64IF_MASK 0x20UL /**< Bit mask for TRNG_APT64IF */
-#define _TRNG_STATUS_APT64IF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */
-#define TRNG_STATUS_APT64IF_DEFAULT (_TRNG_STATUS_APT64IF_DEFAULT << 5) /**< Shifted mode DEFAULT for TRNG_STATUS */
-#define TRNG_STATUS_APT4096IF (0x1UL << 6) /**< Adaptive Proportion test failure (4096-sample window) interrupt status */
-#define _TRNG_STATUS_APT4096IF_SHIFT 6 /**< Shift value for TRNG_APT4096IF */
-#define _TRNG_STATUS_APT4096IF_MASK 0x40UL /**< Bit mask for TRNG_APT4096IF */
-#define _TRNG_STATUS_APT4096IF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */
-#define TRNG_STATUS_APT4096IF_DEFAULT (_TRNG_STATUS_APT4096IF_DEFAULT << 6) /**< Shifted mode DEFAULT for TRNG_STATUS */
-#define TRNG_STATUS_FULLIF (0x1UL << 7) /**< FIFO Full Interrupt Status */
-#define _TRNG_STATUS_FULLIF_SHIFT 7 /**< Shift value for TRNG_FULLIF */
-#define _TRNG_STATUS_FULLIF_MASK 0x80UL /**< Bit mask for TRNG_FULLIF */
-#define _TRNG_STATUS_FULLIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */
-#define TRNG_STATUS_FULLIF_DEFAULT (_TRNG_STATUS_FULLIF_DEFAULT << 7) /**< Shifted mode DEFAULT for TRNG_STATUS */
-#define TRNG_STATUS_PREIF (0x1UL << 8) /**< AIS31 Preliminary Noise Alarm interrupt status */
-#define _TRNG_STATUS_PREIF_SHIFT 8 /**< Shift value for TRNG_PREIF */
-#define _TRNG_STATUS_PREIF_MASK 0x100UL /**< Bit mask for TRNG_PREIF */
-#define _TRNG_STATUS_PREIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */
-#define TRNG_STATUS_PREIF_DEFAULT (_TRNG_STATUS_PREIF_DEFAULT << 8) /**< Shifted mode DEFAULT for TRNG_STATUS */
-#define TRNG_STATUS_ALMIF (0x1UL << 9) /**< AIS31 Noise Alarm interrupt status */
-#define _TRNG_STATUS_ALMIF_SHIFT 9 /**< Shift value for TRNG_ALMIF */
-#define _TRNG_STATUS_ALMIF_MASK 0x200UL /**< Bit mask for TRNG_ALMIF */
-#define _TRNG_STATUS_ALMIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */
-#define TRNG_STATUS_ALMIF_DEFAULT (_TRNG_STATUS_ALMIF_DEFAULT << 9) /**< Shifted mode DEFAULT for TRNG_STATUS */
-
-/* Bit fields for TRNG INITWAITVAL */
-#define _TRNG_INITWAITVAL_RESETVALUE 0x000000FFUL /**< Default value for TRNG_INITWAITVAL */
-#define _TRNG_INITWAITVAL_MASK 0x000000FFUL /**< Mask for TRNG_INITWAITVAL */
-#define _TRNG_INITWAITVAL_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
-#define _TRNG_INITWAITVAL_VALUE_MASK 0xFFUL /**< Bit mask for TRNG_VALUE */
-#define _TRNG_INITWAITVAL_VALUE_DEFAULT 0x000000FFUL /**< Mode DEFAULT for TRNG_INITWAITVAL */
-#define TRNG_INITWAITVAL_VALUE_DEFAULT (_TRNG_INITWAITVAL_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_INITWAITVAL */
-
-/* Bit fields for TRNG FIFO */
-#define _TRNG_FIFO_RESETVALUE 0x00000000UL /**< Default value for TRNG_FIFO */
-#define _TRNG_FIFO_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFO */
-#define _TRNG_FIFO_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
-#define _TRNG_FIFO_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
-#define _TRNG_FIFO_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_FIFO */
-#define TRNG_FIFO_VALUE_DEFAULT (_TRNG_FIFO_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFO */
-
-/** @} */
-/** @} End of group EFR32FG13P_TRNG */
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_usart.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_usart.h
deleted file mode 100644
index 2b11553f..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_usart.h
+++ /dev/null
@@ -1,1981 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_usart.h
- * @brief EFR32FG13P_USART register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P_USART USART
- * @{
- * @brief EFR32FG13P_USART Register Declaration
- *****************************************************************************/
-/** USART Register Declaration */
-typedef struct {
- __IOM uint32_t CTRL; /**< Control Register */
- __IOM uint32_t FRAME; /**< USART Frame Format Register */
- __IOM uint32_t TRIGCTRL; /**< USART Trigger Control Register */
- __IOM uint32_t CMD; /**< Command Register */
- __IM uint32_t STATUS; /**< USART Status Register */
- __IOM uint32_t CLKDIV; /**< Clock Control Register */
- __IM uint32_t RXDATAX; /**< RX Buffer Data Extended Register */
- __IM uint32_t RXDATA; /**< RX Buffer Data Register */
- __IM uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */
- __IM uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */
- __IM uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */
- __IM uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek Register */
- __IOM uint32_t TXDATAX; /**< TX Buffer Data Extended Register */
- __IOM uint32_t TXDATA; /**< TX Buffer Data Register */
- __IOM uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */
- __IOM uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- __IOM uint32_t IRCTRL; /**< IrDA Control Register */
- uint32_t RESERVED0[1]; /**< Reserved for future use **/
- __IOM uint32_t INPUT; /**< USART Input Register */
- __IOM uint32_t I2SCTRL; /**< I2S Control Register */
- __IOM uint32_t TIMING; /**< Timing Register */
- __IOM uint32_t CTRLX; /**< Control Register Extended */
- __IOM uint32_t TIMECMP0; /**< Used to Generate Interrupts and Various Delays */
- __IOM uint32_t TIMECMP1; /**< Used to Generate Interrupts and Various Delays */
- __IOM uint32_t TIMECMP2; /**< Used to Generate Interrupts and Various Delays */
- __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
- __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
- __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */
-} USART_TypeDef; /** @} */
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_USART
- * @{
- * @defgroup EFR32FG13P_USART_BitFields USART Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for USART CTRL */
-#define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */
-#define _USART_CTRL_MASK 0xF3FFFF7FUL /**< Mask for USART_CTRL */
-#define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */
-#define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */
-#define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */
-#define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
-#define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */
-#define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */
-#define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */
-#define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
-#define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */
-#define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */
-#define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */
-#define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
-#define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */
-#define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */
-#define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */
-#define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
-#define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */
-#define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */
-#define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */
-#define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
-#define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */
-#define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */
-#define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */
-#define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
-#define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */
-#define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */
-#define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */
-#define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */
-#define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */
-#define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */
-#define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */
-#define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */
-#define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */
-#define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */
-#define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */
-#define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
-#define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */
-#define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */
-#define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */
-#define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */
-#define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge for Setup/Sample */
-#define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */
-#define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */
-#define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
-#define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */
-#define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */
-#define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */
-#define USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */
-#define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */
-#define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */
-#define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */
-#define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
-#define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_CSMA (0x1UL << 11) /**< Action on Slave-Select in Master Mode */
-#define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */
-#define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */
-#define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
-#define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */
-#define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */
-#define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */
-#define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */
-#define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */
-#define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */
-#define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */
-#define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
-#define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */
-#define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */
-#define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */
-#define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */
-#define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */
-#define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */
-#define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */
-#define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
-#define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter Output Invert */
-#define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */
-#define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */
-#define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
-#define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */
-#define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */
-#define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */
-#define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
-#define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */
-#define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */
-#define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */
-#define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
-#define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */
-#define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */
-#define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */
-#define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
-#define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */
-#define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */
-#define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */
-#define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
-#define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */
-#define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */
-#define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */
-#define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
-#define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */
-#define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */
-#define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */
-#define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
-#define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */
-#define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */
-#define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */
-#define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
-#define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA on Error */
-#define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */
-#define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */
-#define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
-#define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX on Error */
-#define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */
-#define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */
-#define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
-#define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX on Error */
-#define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */
-#define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */
-#define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
-#define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Slave Setup Early */
-#define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */
-#define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */
-#define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
-#define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap in Double Accesses */
-#define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */
-#define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */
-#define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
-#define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */
-#define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */
-#define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */
-#define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
-#define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */
-#define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */
-#define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */
-#define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
-#define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */
-#define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Master Sample Delay */
-#define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */
-#define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */
-#define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
-#define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */
-
-/* Bit fields for USART FRAME */
-#define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */
-#define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */
-#define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */
-#define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */
-#define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */
-#define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */
-#define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */
-#define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */
-#define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */
-#define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */
-#define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */
-#define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */
-#define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */
-#define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */
-#define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */
-#define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */
-#define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */
-#define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */
-#define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */
-#define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */
-#define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */
-#define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */
-#define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */
-#define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */
-#define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */
-#define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */
-#define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */
-#define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */
-#define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */
-#define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */
-#define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */
-#define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */
-#define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */
-#define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */
-#define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */
-#define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */
-#define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */
-#define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */
-#define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */
-#define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */
-#define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */
-#define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */
-#define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */
-#define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */
-#define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */
-#define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */
-#define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */
-#define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */
-#define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */
-#define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */
-#define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */
-#define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */
-#define USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */
-#define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */
-
-/* Bit fields for USART TRIGCTRL */
-#define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */
-#define _USART_TRIGCTRL_MASK 0x000F1FF0UL /**< Mask for USART_TRIGCTRL */
-#define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */
-#define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */
-#define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */
-#define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
-#define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
-#define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */
-#define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */
-#define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */
-#define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
-#define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
-#define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */
-#define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */
-#define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */
-#define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
-#define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
-#define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger After RX End of Frame Plus TCMP0VAL */
-#define _USART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */
-#define _USART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */
-#define _USART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
-#define USART_TRIGCTRL_TXARX0EN_DEFAULT (_USART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
-#define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger After RX End of Frame Plus TCMP1VAL */
-#define _USART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */
-#define _USART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */
-#define _USART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
-#define USART_TRIGCTRL_TXARX1EN_DEFAULT (_USART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
-#define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger After RX End of Frame Plus TCMP2VAL */
-#define _USART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */
-#define _USART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */
-#define _USART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
-#define USART_TRIGCTRL_TXARX2EN_DEFAULT (_USART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
-#define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger After TX End of Frame Plus TCMPVAL0 Baud-times */
-#define _USART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */
-#define _USART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */
-#define _USART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
-#define USART_TRIGCTRL_RXATX0EN_DEFAULT (_USART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
-#define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger After TX End of Frame Plus TCMPVAL1 Baud-times */
-#define _USART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */
-#define _USART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */
-#define _USART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
-#define USART_TRIGCTRL_RXATX1EN_DEFAULT (_USART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
-#define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger After TX End of Frame Plus TCMPVAL2 Baud-times */
-#define _USART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */
-#define _USART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */
-#define _USART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
-#define USART_TRIGCTRL_RXATX2EN_DEFAULT (_USART_TRIGCTRL_RXATX2EN_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
-#define _USART_TRIGCTRL_TSEL_SHIFT 16 /**< Shift value for USART_TSEL */
-#define _USART_TRIGCTRL_TSEL_MASK 0xF0000UL /**< Bit mask for USART_TSEL */
-#define _USART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
-#define _USART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_TRIGCTRL */
-#define _USART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_TRIGCTRL */
-#define _USART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_TRIGCTRL */
-#define _USART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_TRIGCTRL */
-#define _USART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_TRIGCTRL */
-#define _USART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_TRIGCTRL */
-#define _USART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_TRIGCTRL */
-#define _USART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_TRIGCTRL */
-#define _USART_TRIGCTRL_TSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_TRIGCTRL */
-#define _USART_TRIGCTRL_TSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_TRIGCTRL */
-#define _USART_TRIGCTRL_TSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_TRIGCTRL */
-#define _USART_TRIGCTRL_TSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_TRIGCTRL */
-#define USART_TRIGCTRL_TSEL_DEFAULT (_USART_TRIGCTRL_TSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
-#define USART_TRIGCTRL_TSEL_PRSCH0 (_USART_TRIGCTRL_TSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for USART_TRIGCTRL */
-#define USART_TRIGCTRL_TSEL_PRSCH1 (_USART_TRIGCTRL_TSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for USART_TRIGCTRL */
-#define USART_TRIGCTRL_TSEL_PRSCH2 (_USART_TRIGCTRL_TSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for USART_TRIGCTRL */
-#define USART_TRIGCTRL_TSEL_PRSCH3 (_USART_TRIGCTRL_TSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for USART_TRIGCTRL */
-#define USART_TRIGCTRL_TSEL_PRSCH4 (_USART_TRIGCTRL_TSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for USART_TRIGCTRL */
-#define USART_TRIGCTRL_TSEL_PRSCH5 (_USART_TRIGCTRL_TSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for USART_TRIGCTRL */
-#define USART_TRIGCTRL_TSEL_PRSCH6 (_USART_TRIGCTRL_TSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for USART_TRIGCTRL */
-#define USART_TRIGCTRL_TSEL_PRSCH7 (_USART_TRIGCTRL_TSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for USART_TRIGCTRL */
-#define USART_TRIGCTRL_TSEL_PRSCH8 (_USART_TRIGCTRL_TSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for USART_TRIGCTRL */
-#define USART_TRIGCTRL_TSEL_PRSCH9 (_USART_TRIGCTRL_TSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for USART_TRIGCTRL */
-#define USART_TRIGCTRL_TSEL_PRSCH10 (_USART_TRIGCTRL_TSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for USART_TRIGCTRL */
-#define USART_TRIGCTRL_TSEL_PRSCH11 (_USART_TRIGCTRL_TSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for USART_TRIGCTRL */
-
-/* Bit fields for USART CMD */
-#define _USART_CMD_RESETVALUE 0x00000000UL /**< Default value for USART_CMD */
-#define _USART_CMD_MASK 0x00000FFFUL /**< Mask for USART_CMD */
-#define USART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */
-#define _USART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */
-#define _USART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */
-#define _USART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
-#define USART_CMD_RXEN_DEFAULT (_USART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CMD */
-#define USART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */
-#define _USART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */
-#define _USART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */
-#define _USART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
-#define USART_CMD_RXDIS_DEFAULT (_USART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CMD */
-#define USART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */
-#define _USART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */
-#define _USART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */
-#define _USART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
-#define USART_CMD_TXEN_DEFAULT (_USART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CMD */
-#define USART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */
-#define _USART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */
-#define _USART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */
-#define _USART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
-#define USART_CMD_TXDIS_DEFAULT (_USART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CMD */
-#define USART_CMD_MASTEREN (0x1UL << 4) /**< Master Enable */
-#define _USART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */
-#define _USART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */
-#define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
-#define USART_CMD_MASTEREN_DEFAULT (_USART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CMD */
-#define USART_CMD_MASTERDIS (0x1UL << 5) /**< Master Disable */
-#define _USART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */
-#define _USART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */
-#define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
-#define USART_CMD_MASTERDIS_DEFAULT (_USART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CMD */
-#define USART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */
-#define _USART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */
-#define _USART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */
-#define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
-#define USART_CMD_RXBLOCKEN_DEFAULT (_USART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CMD */
-#define USART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */
-#define _USART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */
-#define _USART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */
-#define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
-#define USART_CMD_RXBLOCKDIS_DEFAULT (_USART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CMD */
-#define USART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */
-#define _USART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */
-#define _USART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */
-#define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
-#define USART_CMD_TXTRIEN_DEFAULT (_USART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CMD */
-#define USART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */
-#define _USART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */
-#define _USART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */
-#define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
-#define USART_CMD_TXTRIDIS_DEFAULT (_USART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CMD */
-#define USART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */
-#define _USART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */
-#define _USART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */
-#define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
-#define USART_CMD_CLEARTX_DEFAULT (_USART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CMD */
-#define USART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */
-#define _USART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */
-#define _USART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */
-#define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
-#define USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CMD */
-
-/* Bit fields for USART STATUS */
-#define _USART_STATUS_RESETVALUE 0x00002040UL /**< Default value for USART_STATUS */
-#define _USART_STATUS_MASK 0x00037FFFUL /**< Mask for USART_STATUS */
-#define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */
-#define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */
-#define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */
-#define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
-#define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */
-#define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */
-#define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */
-#define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */
-#define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
-#define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */
-#define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Master Mode */
-#define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */
-#define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */
-#define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
-#define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */
-#define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */
-#define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */
-#define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */
-#define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
-#define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */
-#define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */
-#define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */
-#define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */
-#define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
-#define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */
-#define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */
-#define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */
-#define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */
-#define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
-#define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */
-#define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */
-#define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */
-#define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */
-#define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */
-#define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */
-#define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */
-#define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */
-#define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */
-#define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
-#define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */
-#define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */
-#define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */
-#define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */
-#define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
-#define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */
-#define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */
-#define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */
-#define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */
-#define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
-#define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */
-#define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */
-#define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */
-#define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */
-#define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
-#define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */
-#define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */
-#define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */
-#define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */
-#define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
-#define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */
-#define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */
-#define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */
-#define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */
-#define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
-#define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */
-#define USART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */
-#define _USART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
-#define _USART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
-#define _USART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */
-#define USART_STATUS_TXIDLE_DEFAULT (_USART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_STATUS */
-#define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer Restarted Itself */
-#define _USART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */
-#define _USART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */
-#define _USART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
-#define USART_STATUS_TIMERRESTARTED_DEFAULT (_USART_STATUS_TIMERRESTARTED_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_STATUS */
-#define _USART_STATUS_TXBUFCNT_SHIFT 16 /**< Shift value for USART_TXBUFCNT */
-#define _USART_STATUS_TXBUFCNT_MASK 0x30000UL /**< Bit mask for USART_TXBUFCNT */
-#define _USART_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
-#define USART_STATUS_TXBUFCNT_DEFAULT (_USART_STATUS_TXBUFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_STATUS */
-
-/* Bit fields for USART CLKDIV */
-#define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */
-#define _USART_CLKDIV_MASK 0x807FFFF8UL /**< Mask for USART_CLKDIV */
-#define _USART_CLKDIV_DIV_SHIFT 3 /**< Shift value for USART_DIV */
-#define _USART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */
-#define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */
-#define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CLKDIV */
-#define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD Detection Enable */
-#define _USART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */
-#define _USART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */
-#define _USART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */
-#define USART_CLKDIV_AUTOBAUDEN_DEFAULT (_USART_CLKDIV_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CLKDIV */
-
-/* Bit fields for USART RXDATAX */
-#define _USART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAX */
-#define _USART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAX */
-#define _USART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */
-#define _USART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */
-#define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */
-#define USART_RXDATAX_RXDATA_DEFAULT (_USART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */
-#define USART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */
-#define _USART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */
-#define _USART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */
-#define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */
-#define USART_RXDATAX_PERR_DEFAULT (_USART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAX */
-#define USART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */
-#define _USART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */
-#define _USART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */
-#define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */
-#define USART_RXDATAX_FERR_DEFAULT (_USART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAX */
-
-/* Bit fields for USART RXDATA */
-#define _USART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATA */
-#define _USART_RXDATA_MASK 0x000000FFUL /**< Mask for USART_RXDATA */
-#define _USART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */
-#define _USART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */
-#define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATA */
-#define USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATA */
-
-/* Bit fields for USART RXDOUBLEX */
-#define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */
-#define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */
-#define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */
-#define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */
-#define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
-#define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
-#define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */
-#define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */
-#define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */
-#define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
-#define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
-#define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */
-#define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */
-#define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */
-#define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
-#define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
-#define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */
-#define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */
-#define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
-#define USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
-#define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */
-#define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */
-#define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */
-#define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
-#define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
-#define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */
-#define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */
-#define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */
-#define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
-#define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
-
-/* Bit fields for USART RXDOUBLE */
-#define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */
-#define _USART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_RXDOUBLE */
-#define _USART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */
-#define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */
-#define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */
-#define USART_RXDOUBLE_RXDATA0_DEFAULT (_USART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */
-#define _USART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */
-#define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */
-#define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */
-#define USART_RXDOUBLE_RXDATA1_DEFAULT (_USART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */
-
-/* Bit fields for USART RXDATAXP */
-#define _USART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAXP */
-#define _USART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAXP */
-#define _USART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */
-#define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */
-#define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */
-#define USART_RXDATAXP_RXDATAP_DEFAULT (_USART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */
-#define USART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */
-#define _USART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */
-#define _USART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */
-#define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */
-#define USART_RXDATAXP_PERRP_DEFAULT (_USART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAXP */
-#define USART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */
-#define _USART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */
-#define _USART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */
-#define _USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */
-#define USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */
-
-/* Bit fields for USART RXDOUBLEXP */
-#define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */
-#define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */
-#define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */
-#define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */
-#define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
-#define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
-#define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */
-#define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */
-#define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */
-#define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
-#define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
-#define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */
-#define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */
-#define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */
-#define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
-#define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
-#define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */
-#define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */
-#define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
-#define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
-#define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */
-#define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */
-#define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */
-#define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
-#define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
-#define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */
-#define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */
-#define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */
-#define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
-#define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
-
-/* Bit fields for USART TXDATAX */
-#define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */
-#define _USART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for USART_TXDATAX */
-#define _USART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */
-#define _USART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */
-#define _USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
-#define USART_TXDATAX_TXDATAX_DEFAULT (_USART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATAX */
-#define USART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */
-#define _USART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */
-#define _USART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */
-#define _USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
-#define USART_TXDATAX_UBRXAT_DEFAULT (_USART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDATAX */
-#define USART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */
-#define _USART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */
-#define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */
-#define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
-#define USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */
-#define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data as Break */
-#define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */
-#define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */
-#define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
-#define USART_TXDATAX_TXBREAK_DEFAULT (_USART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDATAX */
-#define USART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */
-#define _USART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */
-#define _USART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */
-#define _USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
-#define USART_TXDATAX_TXDISAT_DEFAULT (_USART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDATAX */
-#define USART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */
-#define _USART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */
-#define _USART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */
-#define _USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
-#define USART_TXDATAX_RXENAT_DEFAULT (_USART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDATAX */
-
-/* Bit fields for USART TXDATA */
-#define _USART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATA */
-#define _USART_TXDATA_MASK 0x000000FFUL /**< Mask for USART_TXDATA */
-#define _USART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */
-#define _USART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */
-#define _USART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATA */
-#define USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATA */
-
-/* Bit fields for USART TXDOUBLEX */
-#define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */
-#define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */
-#define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */
-#define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */
-#define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
-#define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
-#define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */
-#define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */
-#define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */
-#define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
-#define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
-#define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */
-#define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */
-#define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */
-#define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
-#define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
-#define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data as Break */
-#define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */
-#define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */
-#define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
-#define USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
-#define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */
-#define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */
-#define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */
-#define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
-#define USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
-#define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */
-#define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */
-#define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */
-#define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
-#define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
-#define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */
-#define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */
-#define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
-#define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
-#define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */
-#define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */
-#define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */
-#define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
-#define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
-#define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */
-#define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */
-#define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */
-#define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
-#define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
-#define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data as Break */
-#define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */
-#define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */
-#define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
-#define USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
-#define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */
-#define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */
-#define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */
-#define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
-#define USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
-#define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */
-#define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */
-#define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */
-#define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
-#define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
-
-/* Bit fields for USART TXDOUBLE */
-#define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */
-#define _USART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_TXDOUBLE */
-#define _USART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */
-#define _USART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */
-#define _USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */
-#define USART_TXDOUBLE_TXDATA0_DEFAULT (_USART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLE */
-#define _USART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */
-#define _USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */
-#define _USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */
-#define USART_TXDOUBLE_TXDATA1_DEFAULT (_USART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TXDOUBLE */
-
-/* Bit fields for USART IF */
-#define _USART_IF_RESETVALUE 0x00000002UL /**< Default value for USART_IF */
-#define _USART_IF_MASK 0x0001FFFFUL /**< Mask for USART_IF */
-#define USART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */
-#define _USART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */
-#define _USART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
-#define _USART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
-#define USART_IF_TXC_DEFAULT (_USART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IF */
-#define USART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */
-#define _USART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */
-#define _USART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */
-#define _USART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_IF */
-#define USART_IF_TXBL_DEFAULT (_USART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IF */
-#define USART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */
-#define _USART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */
-#define _USART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */
-#define _USART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
-#define USART_IF_RXDATAV_DEFAULT (_USART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IF */
-#define USART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */
-#define _USART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
-#define _USART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
-#define _USART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
-#define USART_IF_RXFULL_DEFAULT (_USART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IF */
-#define USART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */
-#define _USART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
-#define _USART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
-#define _USART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
-#define USART_IF_RXOF_DEFAULT (_USART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IF */
-#define USART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */
-#define _USART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
-#define _USART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
-#define _USART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
-#define USART_IF_RXUF_DEFAULT (_USART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IF */
-#define USART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */
-#define _USART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
-#define _USART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
-#define _USART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
-#define USART_IF_TXOF_DEFAULT (_USART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IF */
-#define USART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */
-#define _USART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
-#define _USART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
-#define _USART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
-#define USART_IF_TXUF_DEFAULT (_USART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IF */
-#define USART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */
-#define _USART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */
-#define _USART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
-#define _USART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
-#define USART_IF_PERR_DEFAULT (_USART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IF */
-#define USART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */
-#define _USART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */
-#define _USART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
-#define _USART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
-#define USART_IF_FERR_DEFAULT (_USART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IF */
-#define USART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt Flag */
-#define _USART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
-#define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
-#define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
-#define USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IF */
-#define USART_IF_SSM (0x1UL << 11) /**< Slave-Select in Master Mode Interrupt Flag */
-#define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */
-#define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
-#define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
-#define USART_IF_SSM_DEFAULT (_USART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IF */
-#define USART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */
-#define _USART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */
-#define _USART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
-#define _USART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
-#define USART_IF_CCF_DEFAULT (_USART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IF */
-#define USART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */
-#define _USART_IF_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
-#define _USART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
-#define _USART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
-#define USART_IF_TXIDLE_DEFAULT (_USART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IF */
-#define USART_IF_TCMP0 (0x1UL << 14) /**< Timer Comparator 0 Interrupt Flag */
-#define _USART_IF_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */
-#define _USART_IF_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */
-#define _USART_IF_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
-#define USART_IF_TCMP0_DEFAULT (_USART_IF_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IF */
-#define USART_IF_TCMP1 (0x1UL << 15) /**< Timer Comparator 1 Interrupt Flag */
-#define _USART_IF_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */
-#define _USART_IF_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */
-#define _USART_IF_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
-#define USART_IF_TCMP1_DEFAULT (_USART_IF_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IF */
-#define USART_IF_TCMP2 (0x1UL << 16) /**< Timer Comparator 2 Interrupt Flag */
-#define _USART_IF_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */
-#define _USART_IF_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */
-#define _USART_IF_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
-#define USART_IF_TCMP2_DEFAULT (_USART_IF_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IF */
-
-/* Bit fields for USART IFS */
-#define _USART_IFS_RESETVALUE 0x00000000UL /**< Default value for USART_IFS */
-#define _USART_IFS_MASK 0x0001FFF9UL /**< Mask for USART_IFS */
-#define USART_IFS_TXC (0x1UL << 0) /**< Set TXC Interrupt Flag */
-#define _USART_IFS_TXC_SHIFT 0 /**< Shift value for USART_TXC */
-#define _USART_IFS_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
-#define _USART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
-#define USART_IFS_TXC_DEFAULT (_USART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFS */
-#define USART_IFS_RXFULL (0x1UL << 3) /**< Set RXFULL Interrupt Flag */
-#define _USART_IFS_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
-#define _USART_IFS_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
-#define _USART_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
-#define USART_IFS_RXFULL_DEFAULT (_USART_IFS_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFS */
-#define USART_IFS_RXOF (0x1UL << 4) /**< Set RXOF Interrupt Flag */
-#define _USART_IFS_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
-#define _USART_IFS_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
-#define _USART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
-#define USART_IFS_RXOF_DEFAULT (_USART_IFS_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFS */
-#define USART_IFS_RXUF (0x1UL << 5) /**< Set RXUF Interrupt Flag */
-#define _USART_IFS_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
-#define _USART_IFS_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
-#define _USART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
-#define USART_IFS_RXUF_DEFAULT (_USART_IFS_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFS */
-#define USART_IFS_TXOF (0x1UL << 6) /**< Set TXOF Interrupt Flag */
-#define _USART_IFS_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
-#define _USART_IFS_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
-#define _USART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
-#define USART_IFS_TXOF_DEFAULT (_USART_IFS_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFS */
-#define USART_IFS_TXUF (0x1UL << 7) /**< Set TXUF Interrupt Flag */
-#define _USART_IFS_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
-#define _USART_IFS_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
-#define _USART_IFS_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
-#define USART_IFS_TXUF_DEFAULT (_USART_IFS_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFS */
-#define USART_IFS_PERR (0x1UL << 8) /**< Set PERR Interrupt Flag */
-#define _USART_IFS_PERR_SHIFT 8 /**< Shift value for USART_PERR */
-#define _USART_IFS_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
-#define _USART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
-#define USART_IFS_PERR_DEFAULT (_USART_IFS_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFS */
-#define USART_IFS_FERR (0x1UL << 9) /**< Set FERR Interrupt Flag */
-#define _USART_IFS_FERR_SHIFT 9 /**< Shift value for USART_FERR */
-#define _USART_IFS_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
-#define _USART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
-#define USART_IFS_FERR_DEFAULT (_USART_IFS_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFS */
-#define USART_IFS_MPAF (0x1UL << 10) /**< Set MPAF Interrupt Flag */
-#define _USART_IFS_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
-#define _USART_IFS_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
-#define _USART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
-#define USART_IFS_MPAF_DEFAULT (_USART_IFS_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFS */
-#define USART_IFS_SSM (0x1UL << 11) /**< Set SSM Interrupt Flag */
-#define _USART_IFS_SSM_SHIFT 11 /**< Shift value for USART_SSM */
-#define _USART_IFS_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
-#define _USART_IFS_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
-#define USART_IFS_SSM_DEFAULT (_USART_IFS_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFS */
-#define USART_IFS_CCF (0x1UL << 12) /**< Set CCF Interrupt Flag */
-#define _USART_IFS_CCF_SHIFT 12 /**< Shift value for USART_CCF */
-#define _USART_IFS_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
-#define _USART_IFS_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
-#define USART_IFS_CCF_DEFAULT (_USART_IFS_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFS */
-#define USART_IFS_TXIDLE (0x1UL << 13) /**< Set TXIDLE Interrupt Flag */
-#define _USART_IFS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
-#define _USART_IFS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
-#define _USART_IFS_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
-#define USART_IFS_TXIDLE_DEFAULT (_USART_IFS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IFS */
-#define USART_IFS_TCMP0 (0x1UL << 14) /**< Set TCMP0 Interrupt Flag */
-#define _USART_IFS_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */
-#define _USART_IFS_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */
-#define _USART_IFS_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
-#define USART_IFS_TCMP0_DEFAULT (_USART_IFS_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IFS */
-#define USART_IFS_TCMP1 (0x1UL << 15) /**< Set TCMP1 Interrupt Flag */
-#define _USART_IFS_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */
-#define _USART_IFS_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */
-#define _USART_IFS_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
-#define USART_IFS_TCMP1_DEFAULT (_USART_IFS_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IFS */
-#define USART_IFS_TCMP2 (0x1UL << 16) /**< Set TCMP2 Interrupt Flag */
-#define _USART_IFS_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */
-#define _USART_IFS_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */
-#define _USART_IFS_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
-#define USART_IFS_TCMP2_DEFAULT (_USART_IFS_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IFS */
-
-/* Bit fields for USART IFC */
-#define _USART_IFC_RESETVALUE 0x00000000UL /**< Default value for USART_IFC */
-#define _USART_IFC_MASK 0x0001FFF9UL /**< Mask for USART_IFC */
-#define USART_IFC_TXC (0x1UL << 0) /**< Clear TXC Interrupt Flag */
-#define _USART_IFC_TXC_SHIFT 0 /**< Shift value for USART_TXC */
-#define _USART_IFC_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
-#define _USART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
-#define USART_IFC_TXC_DEFAULT (_USART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFC */
-#define USART_IFC_RXFULL (0x1UL << 3) /**< Clear RXFULL Interrupt Flag */
-#define _USART_IFC_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
-#define _USART_IFC_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
-#define _USART_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
-#define USART_IFC_RXFULL_DEFAULT (_USART_IFC_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFC */
-#define USART_IFC_RXOF (0x1UL << 4) /**< Clear RXOF Interrupt Flag */
-#define _USART_IFC_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
-#define _USART_IFC_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
-#define _USART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
-#define USART_IFC_RXOF_DEFAULT (_USART_IFC_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFC */
-#define USART_IFC_RXUF (0x1UL << 5) /**< Clear RXUF Interrupt Flag */
-#define _USART_IFC_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
-#define _USART_IFC_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
-#define _USART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
-#define USART_IFC_RXUF_DEFAULT (_USART_IFC_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFC */
-#define USART_IFC_TXOF (0x1UL << 6) /**< Clear TXOF Interrupt Flag */
-#define _USART_IFC_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
-#define _USART_IFC_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
-#define _USART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
-#define USART_IFC_TXOF_DEFAULT (_USART_IFC_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFC */
-#define USART_IFC_TXUF (0x1UL << 7) /**< Clear TXUF Interrupt Flag */
-#define _USART_IFC_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
-#define _USART_IFC_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
-#define _USART_IFC_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
-#define USART_IFC_TXUF_DEFAULT (_USART_IFC_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFC */
-#define USART_IFC_PERR (0x1UL << 8) /**< Clear PERR Interrupt Flag */
-#define _USART_IFC_PERR_SHIFT 8 /**< Shift value for USART_PERR */
-#define _USART_IFC_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
-#define _USART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
-#define USART_IFC_PERR_DEFAULT (_USART_IFC_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFC */
-#define USART_IFC_FERR (0x1UL << 9) /**< Clear FERR Interrupt Flag */
-#define _USART_IFC_FERR_SHIFT 9 /**< Shift value for USART_FERR */
-#define _USART_IFC_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
-#define _USART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
-#define USART_IFC_FERR_DEFAULT (_USART_IFC_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFC */
-#define USART_IFC_MPAF (0x1UL << 10) /**< Clear MPAF Interrupt Flag */
-#define _USART_IFC_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
-#define _USART_IFC_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
-#define _USART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
-#define USART_IFC_MPAF_DEFAULT (_USART_IFC_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFC */
-#define USART_IFC_SSM (0x1UL << 11) /**< Clear SSM Interrupt Flag */
-#define _USART_IFC_SSM_SHIFT 11 /**< Shift value for USART_SSM */
-#define _USART_IFC_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
-#define _USART_IFC_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
-#define USART_IFC_SSM_DEFAULT (_USART_IFC_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFC */
-#define USART_IFC_CCF (0x1UL << 12) /**< Clear CCF Interrupt Flag */
-#define _USART_IFC_CCF_SHIFT 12 /**< Shift value for USART_CCF */
-#define _USART_IFC_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
-#define _USART_IFC_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
-#define USART_IFC_CCF_DEFAULT (_USART_IFC_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFC */
-#define USART_IFC_TXIDLE (0x1UL << 13) /**< Clear TXIDLE Interrupt Flag */
-#define _USART_IFC_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
-#define _USART_IFC_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
-#define _USART_IFC_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
-#define USART_IFC_TXIDLE_DEFAULT (_USART_IFC_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IFC */
-#define USART_IFC_TCMP0 (0x1UL << 14) /**< Clear TCMP0 Interrupt Flag */
-#define _USART_IFC_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */
-#define _USART_IFC_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */
-#define _USART_IFC_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
-#define USART_IFC_TCMP0_DEFAULT (_USART_IFC_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IFC */
-#define USART_IFC_TCMP1 (0x1UL << 15) /**< Clear TCMP1 Interrupt Flag */
-#define _USART_IFC_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */
-#define _USART_IFC_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */
-#define _USART_IFC_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
-#define USART_IFC_TCMP1_DEFAULT (_USART_IFC_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IFC */
-#define USART_IFC_TCMP2 (0x1UL << 16) /**< Clear TCMP2 Interrupt Flag */
-#define _USART_IFC_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */
-#define _USART_IFC_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */
-#define _USART_IFC_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
-#define USART_IFC_TCMP2_DEFAULT (_USART_IFC_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IFC */
-
-/* Bit fields for USART IEN */
-#define _USART_IEN_RESETVALUE 0x00000000UL /**< Default value for USART_IEN */
-#define _USART_IEN_MASK 0x0001FFFFUL /**< Mask for USART_IEN */
-#define USART_IEN_TXC (0x1UL << 0) /**< TXC Interrupt Enable */
-#define _USART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */
-#define _USART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
-#define _USART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
-#define USART_IEN_TXC_DEFAULT (_USART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IEN */
-#define USART_IEN_TXBL (0x1UL << 1) /**< TXBL Interrupt Enable */
-#define _USART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */
-#define _USART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */
-#define _USART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
-#define USART_IEN_TXBL_DEFAULT (_USART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IEN */
-#define USART_IEN_RXDATAV (0x1UL << 2) /**< RXDATAV Interrupt Enable */
-#define _USART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */
-#define _USART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */
-#define _USART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
-#define USART_IEN_RXDATAV_DEFAULT (_USART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IEN */
-#define USART_IEN_RXFULL (0x1UL << 3) /**< RXFULL Interrupt Enable */
-#define _USART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
-#define _USART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
-#define _USART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
-#define USART_IEN_RXFULL_DEFAULT (_USART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IEN */
-#define USART_IEN_RXOF (0x1UL << 4) /**< RXOF Interrupt Enable */
-#define _USART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
-#define _USART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
-#define _USART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
-#define USART_IEN_RXOF_DEFAULT (_USART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IEN */
-#define USART_IEN_RXUF (0x1UL << 5) /**< RXUF Interrupt Enable */
-#define _USART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
-#define _USART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
-#define _USART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
-#define USART_IEN_RXUF_DEFAULT (_USART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IEN */
-#define USART_IEN_TXOF (0x1UL << 6) /**< TXOF Interrupt Enable */
-#define _USART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
-#define _USART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
-#define _USART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
-#define USART_IEN_TXOF_DEFAULT (_USART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IEN */
-#define USART_IEN_TXUF (0x1UL << 7) /**< TXUF Interrupt Enable */
-#define _USART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
-#define _USART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
-#define _USART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
-#define USART_IEN_TXUF_DEFAULT (_USART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IEN */
-#define USART_IEN_PERR (0x1UL << 8) /**< PERR Interrupt Enable */
-#define _USART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */
-#define _USART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
-#define _USART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
-#define USART_IEN_PERR_DEFAULT (_USART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IEN */
-#define USART_IEN_FERR (0x1UL << 9) /**< FERR Interrupt Enable */
-#define _USART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */
-#define _USART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
-#define _USART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
-#define USART_IEN_FERR_DEFAULT (_USART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IEN */
-#define USART_IEN_MPAF (0x1UL << 10) /**< MPAF Interrupt Enable */
-#define _USART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
-#define _USART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
-#define _USART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
-#define USART_IEN_MPAF_DEFAULT (_USART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IEN */
-#define USART_IEN_SSM (0x1UL << 11) /**< SSM Interrupt Enable */
-#define _USART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */
-#define _USART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
-#define _USART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
-#define USART_IEN_SSM_DEFAULT (_USART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IEN */
-#define USART_IEN_CCF (0x1UL << 12) /**< CCF Interrupt Enable */
-#define _USART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */
-#define _USART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
-#define _USART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
-#define USART_IEN_CCF_DEFAULT (_USART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IEN */
-#define USART_IEN_TXIDLE (0x1UL << 13) /**< TXIDLE Interrupt Enable */
-#define _USART_IEN_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
-#define _USART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
-#define _USART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
-#define USART_IEN_TXIDLE_DEFAULT (_USART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IEN */
-#define USART_IEN_TCMP0 (0x1UL << 14) /**< TCMP0 Interrupt Enable */
-#define _USART_IEN_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */
-#define _USART_IEN_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */
-#define _USART_IEN_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
-#define USART_IEN_TCMP0_DEFAULT (_USART_IEN_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IEN */
-#define USART_IEN_TCMP1 (0x1UL << 15) /**< TCMP1 Interrupt Enable */
-#define _USART_IEN_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */
-#define _USART_IEN_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */
-#define _USART_IEN_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
-#define USART_IEN_TCMP1_DEFAULT (_USART_IEN_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IEN */
-#define USART_IEN_TCMP2 (0x1UL << 16) /**< TCMP2 Interrupt Enable */
-#define _USART_IEN_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */
-#define _USART_IEN_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */
-#define _USART_IEN_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
-#define USART_IEN_TCMP2_DEFAULT (_USART_IEN_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IEN */
-
-/* Bit fields for USART IRCTRL */
-#define _USART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_IRCTRL */
-#define _USART_IRCTRL_MASK 0x00000F8FUL /**< Mask for USART_IRCTRL */
-#define USART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */
-#define _USART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */
-#define _USART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */
-#define _USART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
-#define USART_IRCTRL_IREN_DEFAULT (_USART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IRCTRL */
-#define _USART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */
-#define _USART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */
-#define _USART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
-#define _USART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for USART_IRCTRL */
-#define _USART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for USART_IRCTRL */
-#define _USART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for USART_IRCTRL */
-#define _USART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for USART_IRCTRL */
-#define USART_IRCTRL_IRPW_DEFAULT (_USART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IRCTRL */
-#define USART_IRCTRL_IRPW_ONE (_USART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for USART_IRCTRL */
-#define USART_IRCTRL_IRPW_TWO (_USART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for USART_IRCTRL */
-#define USART_IRCTRL_IRPW_THREE (_USART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for USART_IRCTRL */
-#define USART_IRCTRL_IRPW_FOUR (_USART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for USART_IRCTRL */
-#define USART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */
-#define _USART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */
-#define _USART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */
-#define _USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
-#define USART_IRCTRL_IRFILT_DEFAULT (_USART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IRCTRL */
-#define USART_IRCTRL_IRPRSEN (0x1UL << 7) /**< IrDA PRS Channel Enable */
-#define _USART_IRCTRL_IRPRSEN_SHIFT 7 /**< Shift value for USART_IRPRSEN */
-#define _USART_IRCTRL_IRPRSEN_MASK 0x80UL /**< Bit mask for USART_IRPRSEN */
-#define _USART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
-#define USART_IRCTRL_IRPRSEN_DEFAULT (_USART_IRCTRL_IRPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IRCTRL */
-#define _USART_IRCTRL_IRPRSSEL_SHIFT 8 /**< Shift value for USART_IRPRSSEL */
-#define _USART_IRCTRL_IRPRSSEL_MASK 0xF00UL /**< Bit mask for USART_IRPRSSEL */
-#define _USART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
-#define _USART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_IRCTRL */
-#define _USART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_IRCTRL */
-#define _USART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_IRCTRL */
-#define _USART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_IRCTRL */
-#define _USART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_IRCTRL */
-#define _USART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_IRCTRL */
-#define _USART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_IRCTRL */
-#define _USART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_IRCTRL */
-#define _USART_IRCTRL_IRPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_IRCTRL */
-#define _USART_IRCTRL_IRPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_IRCTRL */
-#define _USART_IRCTRL_IRPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_IRCTRL */
-#define _USART_IRCTRL_IRPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_IRCTRL */
-#define USART_IRCTRL_IRPRSSEL_DEFAULT (_USART_IRCTRL_IRPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IRCTRL */
-#define USART_IRCTRL_IRPRSSEL_PRSCH0 (_USART_IRCTRL_IRPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for USART_IRCTRL */
-#define USART_IRCTRL_IRPRSSEL_PRSCH1 (_USART_IRCTRL_IRPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for USART_IRCTRL */
-#define USART_IRCTRL_IRPRSSEL_PRSCH2 (_USART_IRCTRL_IRPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for USART_IRCTRL */
-#define USART_IRCTRL_IRPRSSEL_PRSCH3 (_USART_IRCTRL_IRPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for USART_IRCTRL */
-#define USART_IRCTRL_IRPRSSEL_PRSCH4 (_USART_IRCTRL_IRPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for USART_IRCTRL */
-#define USART_IRCTRL_IRPRSSEL_PRSCH5 (_USART_IRCTRL_IRPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for USART_IRCTRL */
-#define USART_IRCTRL_IRPRSSEL_PRSCH6 (_USART_IRCTRL_IRPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for USART_IRCTRL */
-#define USART_IRCTRL_IRPRSSEL_PRSCH7 (_USART_IRCTRL_IRPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for USART_IRCTRL */
-#define USART_IRCTRL_IRPRSSEL_PRSCH8 (_USART_IRCTRL_IRPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for USART_IRCTRL */
-#define USART_IRCTRL_IRPRSSEL_PRSCH9 (_USART_IRCTRL_IRPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for USART_IRCTRL */
-#define USART_IRCTRL_IRPRSSEL_PRSCH10 (_USART_IRCTRL_IRPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for USART_IRCTRL */
-#define USART_IRCTRL_IRPRSSEL_PRSCH11 (_USART_IRCTRL_IRPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for USART_IRCTRL */
-
-/* Bit fields for USART INPUT */
-#define _USART_INPUT_RESETVALUE 0x00000000UL /**< Default value for USART_INPUT */
-#define _USART_INPUT_MASK 0x00008F8FUL /**< Mask for USART_INPUT */
-#define _USART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for USART_RXPRSSEL */
-#define _USART_INPUT_RXPRSSEL_MASK 0xFUL /**< Bit mask for USART_RXPRSSEL */
-#define _USART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */
-#define _USART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */
-#define _USART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */
-#define _USART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */
-#define _USART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */
-#define _USART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */
-#define _USART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */
-#define _USART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_INPUT */
-#define _USART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_INPUT */
-#define _USART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_INPUT */
-#define _USART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_INPUT */
-#define _USART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_INPUT */
-#define _USART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_INPUT */
-#define USART_INPUT_RXPRSSEL_DEFAULT (_USART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_INPUT */
-#define USART_INPUT_RXPRSSEL_PRSCH0 (_USART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for USART_INPUT */
-#define USART_INPUT_RXPRSSEL_PRSCH1 (_USART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for USART_INPUT */
-#define USART_INPUT_RXPRSSEL_PRSCH2 (_USART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for USART_INPUT */
-#define USART_INPUT_RXPRSSEL_PRSCH3 (_USART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for USART_INPUT */
-#define USART_INPUT_RXPRSSEL_PRSCH4 (_USART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for USART_INPUT */
-#define USART_INPUT_RXPRSSEL_PRSCH5 (_USART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for USART_INPUT */
-#define USART_INPUT_RXPRSSEL_PRSCH6 (_USART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for USART_INPUT */
-#define USART_INPUT_RXPRSSEL_PRSCH7 (_USART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for USART_INPUT */
-#define USART_INPUT_RXPRSSEL_PRSCH8 (_USART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for USART_INPUT */
-#define USART_INPUT_RXPRSSEL_PRSCH9 (_USART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for USART_INPUT */
-#define USART_INPUT_RXPRSSEL_PRSCH10 (_USART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for USART_INPUT */
-#define USART_INPUT_RXPRSSEL_PRSCH11 (_USART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for USART_INPUT */
-#define USART_INPUT_RXPRS (0x1UL << 7) /**< PRS RX Enable */
-#define _USART_INPUT_RXPRS_SHIFT 7 /**< Shift value for USART_RXPRS */
-#define _USART_INPUT_RXPRS_MASK 0x80UL /**< Bit mask for USART_RXPRS */
-#define _USART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */
-#define USART_INPUT_RXPRS_DEFAULT (_USART_INPUT_RXPRS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_INPUT */
-#define _USART_INPUT_CLKPRSSEL_SHIFT 8 /**< Shift value for USART_CLKPRSSEL */
-#define _USART_INPUT_CLKPRSSEL_MASK 0xF00UL /**< Bit mask for USART_CLKPRSSEL */
-#define _USART_INPUT_CLKPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */
-#define _USART_INPUT_CLKPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */
-#define _USART_INPUT_CLKPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */
-#define _USART_INPUT_CLKPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */
-#define _USART_INPUT_CLKPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */
-#define _USART_INPUT_CLKPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */
-#define _USART_INPUT_CLKPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */
-#define _USART_INPUT_CLKPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_INPUT */
-#define _USART_INPUT_CLKPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_INPUT */
-#define _USART_INPUT_CLKPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_INPUT */
-#define _USART_INPUT_CLKPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_INPUT */
-#define _USART_INPUT_CLKPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_INPUT */
-#define _USART_INPUT_CLKPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_INPUT */
-#define USART_INPUT_CLKPRSSEL_DEFAULT (_USART_INPUT_CLKPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_INPUT */
-#define USART_INPUT_CLKPRSSEL_PRSCH0 (_USART_INPUT_CLKPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for USART_INPUT */
-#define USART_INPUT_CLKPRSSEL_PRSCH1 (_USART_INPUT_CLKPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for USART_INPUT */
-#define USART_INPUT_CLKPRSSEL_PRSCH2 (_USART_INPUT_CLKPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for USART_INPUT */
-#define USART_INPUT_CLKPRSSEL_PRSCH3 (_USART_INPUT_CLKPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for USART_INPUT */
-#define USART_INPUT_CLKPRSSEL_PRSCH4 (_USART_INPUT_CLKPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for USART_INPUT */
-#define USART_INPUT_CLKPRSSEL_PRSCH5 (_USART_INPUT_CLKPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for USART_INPUT */
-#define USART_INPUT_CLKPRSSEL_PRSCH6 (_USART_INPUT_CLKPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for USART_INPUT */
-#define USART_INPUT_CLKPRSSEL_PRSCH7 (_USART_INPUT_CLKPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for USART_INPUT */
-#define USART_INPUT_CLKPRSSEL_PRSCH8 (_USART_INPUT_CLKPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for USART_INPUT */
-#define USART_INPUT_CLKPRSSEL_PRSCH9 (_USART_INPUT_CLKPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for USART_INPUT */
-#define USART_INPUT_CLKPRSSEL_PRSCH10 (_USART_INPUT_CLKPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for USART_INPUT */
-#define USART_INPUT_CLKPRSSEL_PRSCH11 (_USART_INPUT_CLKPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for USART_INPUT */
-#define USART_INPUT_CLKPRS (0x1UL << 15) /**< PRS CLK Enable */
-#define _USART_INPUT_CLKPRS_SHIFT 15 /**< Shift value for USART_CLKPRS */
-#define _USART_INPUT_CLKPRS_MASK 0x8000UL /**< Bit mask for USART_CLKPRS */
-#define _USART_INPUT_CLKPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */
-#define USART_INPUT_CLKPRS_DEFAULT (_USART_INPUT_CLKPRS_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_INPUT */
-
-/* Bit fields for USART I2SCTRL */
-#define _USART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_I2SCTRL */
-#define _USART_I2SCTRL_MASK 0x0000071FUL /**< Mask for USART_I2SCTRL */
-#define USART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */
-#define _USART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */
-#define _USART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */
-#define _USART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
-#define USART_I2SCTRL_EN_DEFAULT (_USART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_I2SCTRL */
-#define USART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */
-#define _USART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */
-#define _USART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */
-#define _USART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
-#define USART_I2SCTRL_MONO_DEFAULT (_USART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_I2SCTRL */
-#define USART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */
-#define _USART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */
-#define _USART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */
-#define _USART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
-#define _USART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for USART_I2SCTRL */
-#define _USART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for USART_I2SCTRL */
-#define USART_I2SCTRL_JUSTIFY_DEFAULT (_USART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_I2SCTRL */
-#define USART_I2SCTRL_JUSTIFY_LEFT (_USART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for USART_I2SCTRL */
-#define USART_I2SCTRL_JUSTIFY_RIGHT (_USART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for USART_I2SCTRL */
-#define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request for Left/Right Data */
-#define _USART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */
-#define _USART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */
-#define _USART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
-#define USART_I2SCTRL_DMASPLIT_DEFAULT (_USART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_I2SCTRL */
-#define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S Data */
-#define _USART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */
-#define _USART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */
-#define _USART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
-#define USART_I2SCTRL_DELAY_DEFAULT (_USART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_I2SCTRL */
-#define _USART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */
-#define _USART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */
-#define _USART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
-#define _USART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for USART_I2SCTRL */
-#define _USART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for USART_I2SCTRL */
-#define _USART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for USART_I2SCTRL */
-#define _USART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for USART_I2SCTRL */
-#define _USART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for USART_I2SCTRL */
-#define _USART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for USART_I2SCTRL */
-#define _USART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for USART_I2SCTRL */
-#define _USART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for USART_I2SCTRL */
-#define USART_I2SCTRL_FORMAT_DEFAULT (_USART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_I2SCTRL */
-#define USART_I2SCTRL_FORMAT_W32D32 (_USART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for USART_I2SCTRL */
-#define USART_I2SCTRL_FORMAT_W32D24M (_USART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for USART_I2SCTRL */
-#define USART_I2SCTRL_FORMAT_W32D24 (_USART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for USART_I2SCTRL */
-#define USART_I2SCTRL_FORMAT_W32D16 (_USART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for USART_I2SCTRL */
-#define USART_I2SCTRL_FORMAT_W32D8 (_USART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for USART_I2SCTRL */
-#define USART_I2SCTRL_FORMAT_W16D16 (_USART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for USART_I2SCTRL */
-#define USART_I2SCTRL_FORMAT_W16D8 (_USART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for USART_I2SCTRL */
-#define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */
-
-/* Bit fields for USART TIMING */
-#define _USART_TIMING_RESETVALUE 0x00000000UL /**< Default value for USART_TIMING */
-#define _USART_TIMING_MASK 0x77770000UL /**< Mask for USART_TIMING */
-#define _USART_TIMING_TXDELAY_SHIFT 16 /**< Shift value for USART_TXDELAY */
-#define _USART_TIMING_TXDELAY_MASK 0x70000UL /**< Bit mask for USART_TXDELAY */
-#define _USART_TIMING_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */
-#define _USART_TIMING_TXDELAY_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMING */
-#define _USART_TIMING_TXDELAY_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */
-#define _USART_TIMING_TXDELAY_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */
-#define _USART_TIMING_TXDELAY_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */
-#define _USART_TIMING_TXDELAY_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */
-#define _USART_TIMING_TXDELAY_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */
-#define _USART_TIMING_TXDELAY_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */
-#define _USART_TIMING_TXDELAY_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */
-#define USART_TIMING_TXDELAY_DEFAULT (_USART_TIMING_TXDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMING */
-#define USART_TIMING_TXDELAY_DISABLE (_USART_TIMING_TXDELAY_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMING */
-#define USART_TIMING_TXDELAY_ONE (_USART_TIMING_TXDELAY_ONE << 16) /**< Shifted mode ONE for USART_TIMING */
-#define USART_TIMING_TXDELAY_TWO (_USART_TIMING_TXDELAY_TWO << 16) /**< Shifted mode TWO for USART_TIMING */
-#define USART_TIMING_TXDELAY_THREE (_USART_TIMING_TXDELAY_THREE << 16) /**< Shifted mode THREE for USART_TIMING */
-#define USART_TIMING_TXDELAY_SEVEN (_USART_TIMING_TXDELAY_SEVEN << 16) /**< Shifted mode SEVEN for USART_TIMING */
-#define USART_TIMING_TXDELAY_TCMP0 (_USART_TIMING_TXDELAY_TCMP0 << 16) /**< Shifted mode TCMP0 for USART_TIMING */
-#define USART_TIMING_TXDELAY_TCMP1 (_USART_TIMING_TXDELAY_TCMP1 << 16) /**< Shifted mode TCMP1 for USART_TIMING */
-#define USART_TIMING_TXDELAY_TCMP2 (_USART_TIMING_TXDELAY_TCMP2 << 16) /**< Shifted mode TCMP2 for USART_TIMING */
-#define _USART_TIMING_CSSETUP_SHIFT 20 /**< Shift value for USART_CSSETUP */
-#define _USART_TIMING_CSSETUP_MASK 0x700000UL /**< Bit mask for USART_CSSETUP */
-#define _USART_TIMING_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */
-#define _USART_TIMING_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */
-#define _USART_TIMING_CSSETUP_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */
-#define _USART_TIMING_CSSETUP_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */
-#define _USART_TIMING_CSSETUP_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */
-#define _USART_TIMING_CSSETUP_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */
-#define _USART_TIMING_CSSETUP_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */
-#define _USART_TIMING_CSSETUP_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */
-#define _USART_TIMING_CSSETUP_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */
-#define USART_TIMING_CSSETUP_DEFAULT (_USART_TIMING_CSSETUP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMING */
-#define USART_TIMING_CSSETUP_ZERO (_USART_TIMING_CSSETUP_ZERO << 20) /**< Shifted mode ZERO for USART_TIMING */
-#define USART_TIMING_CSSETUP_ONE (_USART_TIMING_CSSETUP_ONE << 20) /**< Shifted mode ONE for USART_TIMING */
-#define USART_TIMING_CSSETUP_TWO (_USART_TIMING_CSSETUP_TWO << 20) /**< Shifted mode TWO for USART_TIMING */
-#define USART_TIMING_CSSETUP_THREE (_USART_TIMING_CSSETUP_THREE << 20) /**< Shifted mode THREE for USART_TIMING */
-#define USART_TIMING_CSSETUP_SEVEN (_USART_TIMING_CSSETUP_SEVEN << 20) /**< Shifted mode SEVEN for USART_TIMING */
-#define USART_TIMING_CSSETUP_TCMP0 (_USART_TIMING_CSSETUP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMING */
-#define USART_TIMING_CSSETUP_TCMP1 (_USART_TIMING_CSSETUP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMING */
-#define USART_TIMING_CSSETUP_TCMP2 (_USART_TIMING_CSSETUP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMING */
-#define _USART_TIMING_ICS_SHIFT 24 /**< Shift value for USART_ICS */
-#define _USART_TIMING_ICS_MASK 0x7000000UL /**< Bit mask for USART_ICS */
-#define _USART_TIMING_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */
-#define _USART_TIMING_ICS_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */
-#define _USART_TIMING_ICS_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */
-#define _USART_TIMING_ICS_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */
-#define _USART_TIMING_ICS_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */
-#define _USART_TIMING_ICS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */
-#define _USART_TIMING_ICS_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */
-#define _USART_TIMING_ICS_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */
-#define _USART_TIMING_ICS_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */
-#define USART_TIMING_ICS_DEFAULT (_USART_TIMING_ICS_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMING */
-#define USART_TIMING_ICS_ZERO (_USART_TIMING_ICS_ZERO << 24) /**< Shifted mode ZERO for USART_TIMING */
-#define USART_TIMING_ICS_ONE (_USART_TIMING_ICS_ONE << 24) /**< Shifted mode ONE for USART_TIMING */
-#define USART_TIMING_ICS_TWO (_USART_TIMING_ICS_TWO << 24) /**< Shifted mode TWO for USART_TIMING */
-#define USART_TIMING_ICS_THREE (_USART_TIMING_ICS_THREE << 24) /**< Shifted mode THREE for USART_TIMING */
-#define USART_TIMING_ICS_SEVEN (_USART_TIMING_ICS_SEVEN << 24) /**< Shifted mode SEVEN for USART_TIMING */
-#define USART_TIMING_ICS_TCMP0 (_USART_TIMING_ICS_TCMP0 << 24) /**< Shifted mode TCMP0 for USART_TIMING */
-#define USART_TIMING_ICS_TCMP1 (_USART_TIMING_ICS_TCMP1 << 24) /**< Shifted mode TCMP1 for USART_TIMING */
-#define USART_TIMING_ICS_TCMP2 (_USART_TIMING_ICS_TCMP2 << 24) /**< Shifted mode TCMP2 for USART_TIMING */
-#define _USART_TIMING_CSHOLD_SHIFT 28 /**< Shift value for USART_CSHOLD */
-#define _USART_TIMING_CSHOLD_MASK 0x70000000UL /**< Bit mask for USART_CSHOLD */
-#define _USART_TIMING_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */
-#define _USART_TIMING_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */
-#define _USART_TIMING_CSHOLD_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */
-#define _USART_TIMING_CSHOLD_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */
-#define _USART_TIMING_CSHOLD_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */
-#define _USART_TIMING_CSHOLD_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */
-#define _USART_TIMING_CSHOLD_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */
-#define _USART_TIMING_CSHOLD_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */
-#define _USART_TIMING_CSHOLD_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */
-#define USART_TIMING_CSHOLD_DEFAULT (_USART_TIMING_CSHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TIMING */
-#define USART_TIMING_CSHOLD_ZERO (_USART_TIMING_CSHOLD_ZERO << 28) /**< Shifted mode ZERO for USART_TIMING */
-#define USART_TIMING_CSHOLD_ONE (_USART_TIMING_CSHOLD_ONE << 28) /**< Shifted mode ONE for USART_TIMING */
-#define USART_TIMING_CSHOLD_TWO (_USART_TIMING_CSHOLD_TWO << 28) /**< Shifted mode TWO for USART_TIMING */
-#define USART_TIMING_CSHOLD_THREE (_USART_TIMING_CSHOLD_THREE << 28) /**< Shifted mode THREE for USART_TIMING */
-#define USART_TIMING_CSHOLD_SEVEN (_USART_TIMING_CSHOLD_SEVEN << 28) /**< Shifted mode SEVEN for USART_TIMING */
-#define USART_TIMING_CSHOLD_TCMP0 (_USART_TIMING_CSHOLD_TCMP0 << 28) /**< Shifted mode TCMP0 for USART_TIMING */
-#define USART_TIMING_CSHOLD_TCMP1 (_USART_TIMING_CSHOLD_TCMP1 << 28) /**< Shifted mode TCMP1 for USART_TIMING */
-#define USART_TIMING_CSHOLD_TCMP2 (_USART_TIMING_CSHOLD_TCMP2 << 28) /**< Shifted mode TCMP2 for USART_TIMING */
-
-/* Bit fields for USART CTRLX */
-#define _USART_CTRLX_RESETVALUE 0x00000000UL /**< Default value for USART_CTRLX */
-#define _USART_CTRLX_MASK 0x0000000FUL /**< Mask for USART_CTRLX */
-#define USART_CTRLX_DBGHALT (0x1UL << 0) /**< Debug Halt */
-#define _USART_CTRLX_DBGHALT_SHIFT 0 /**< Shift value for USART_DBGHALT */
-#define _USART_CTRLX_DBGHALT_MASK 0x1UL /**< Bit mask for USART_DBGHALT */
-#define _USART_CTRLX_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
-#define USART_CTRLX_DBGHALT_DEFAULT (_USART_CTRLX_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRLX */
-#define USART_CTRLX_CTSINV (0x1UL << 1) /**< CTS Pin Inversion */
-#define _USART_CTRLX_CTSINV_SHIFT 1 /**< Shift value for USART_CTSINV */
-#define _USART_CTRLX_CTSINV_MASK 0x2UL /**< Bit mask for USART_CTSINV */
-#define _USART_CTRLX_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
-#define USART_CTRLX_CTSINV_DEFAULT (_USART_CTRLX_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRLX */
-#define USART_CTRLX_CTSEN (0x1UL << 2) /**< CTS Function Enabled */
-#define _USART_CTRLX_CTSEN_SHIFT 2 /**< Shift value for USART_CTSEN */
-#define _USART_CTRLX_CTSEN_MASK 0x4UL /**< Bit mask for USART_CTSEN */
-#define _USART_CTRLX_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
-#define USART_CTRLX_CTSEN_DEFAULT (_USART_CTRLX_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRLX */
-#define USART_CTRLX_RTSINV (0x1UL << 3) /**< RTS Pin Inversion */
-#define _USART_CTRLX_RTSINV_SHIFT 3 /**< Shift value for USART_RTSINV */
-#define _USART_CTRLX_RTSINV_MASK 0x8UL /**< Bit mask for USART_RTSINV */
-#define _USART_CTRLX_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
-#define USART_CTRLX_RTSINV_DEFAULT (_USART_CTRLX_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRLX */
-
-/* Bit fields for USART TIMECMP0 */
-#define _USART_TIMECMP0_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP0 */
-#define _USART_TIMECMP0_MASK 0x017700FFUL /**< Mask for USART_TIMECMP0 */
-#define _USART_TIMECMP0_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */
-#define _USART_TIMECMP0_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */
-#define _USART_TIMECMP0_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */
-#define USART_TIMECMP0_TCMPVAL_DEFAULT (_USART_TIMECMP0_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP0 */
-#define _USART_TIMECMP0_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */
-#define _USART_TIMECMP0_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */
-#define _USART_TIMECMP0_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */
-#define _USART_TIMECMP0_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */
-#define _USART_TIMECMP0_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP0 */
-#define _USART_TIMECMP0_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP0 */
-#define _USART_TIMECMP0_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP0 */
-#define _USART_TIMECMP0_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP0 */
-#define USART_TIMECMP0_TSTART_DEFAULT (_USART_TIMECMP0_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP0 */
-#define USART_TIMECMP0_TSTART_DISABLE (_USART_TIMECMP0_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP0 */
-#define USART_TIMECMP0_TSTART_TXEOF (_USART_TIMECMP0_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP0 */
-#define USART_TIMECMP0_TSTART_TXC (_USART_TIMECMP0_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP0 */
-#define USART_TIMECMP0_TSTART_RXACT (_USART_TIMECMP0_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP0 */
-#define USART_TIMECMP0_TSTART_RXEOF (_USART_TIMECMP0_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP0 */
-#define _USART_TIMECMP0_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */
-#define _USART_TIMECMP0_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */
-#define _USART_TIMECMP0_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */
-#define _USART_TIMECMP0_TSTOP_TCMP0 0x00000000UL /**< Mode TCMP0 for USART_TIMECMP0 */
-#define _USART_TIMECMP0_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP0 */
-#define _USART_TIMECMP0_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP0 */
-#define _USART_TIMECMP0_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP0 */
-#define USART_TIMECMP0_TSTOP_DEFAULT (_USART_TIMECMP0_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP0 */
-#define USART_TIMECMP0_TSTOP_TCMP0 (_USART_TIMECMP0_TSTOP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMECMP0 */
-#define USART_TIMECMP0_TSTOP_TXST (_USART_TIMECMP0_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP0 */
-#define USART_TIMECMP0_TSTOP_RXACT (_USART_TIMECMP0_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP0 */
-#define USART_TIMECMP0_TSTOP_RXACTN (_USART_TIMECMP0_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP0 */
-#define USART_TIMECMP0_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP0 */
-#define _USART_TIMECMP0_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */
-#define _USART_TIMECMP0_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */
-#define _USART_TIMECMP0_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */
-#define USART_TIMECMP0_RESTARTEN_DEFAULT (_USART_TIMECMP0_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP0 */
-
-/* Bit fields for USART TIMECMP1 */
-#define _USART_TIMECMP1_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP1 */
-#define _USART_TIMECMP1_MASK 0x017700FFUL /**< Mask for USART_TIMECMP1 */
-#define _USART_TIMECMP1_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */
-#define _USART_TIMECMP1_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */
-#define _USART_TIMECMP1_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */
-#define USART_TIMECMP1_TCMPVAL_DEFAULT (_USART_TIMECMP1_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP1 */
-#define _USART_TIMECMP1_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */
-#define _USART_TIMECMP1_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */
-#define _USART_TIMECMP1_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */
-#define _USART_TIMECMP1_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */
-#define _USART_TIMECMP1_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP1 */
-#define _USART_TIMECMP1_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP1 */
-#define _USART_TIMECMP1_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP1 */
-#define _USART_TIMECMP1_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP1 */
-#define USART_TIMECMP1_TSTART_DEFAULT (_USART_TIMECMP1_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP1 */
-#define USART_TIMECMP1_TSTART_DISABLE (_USART_TIMECMP1_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP1 */
-#define USART_TIMECMP1_TSTART_TXEOF (_USART_TIMECMP1_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP1 */
-#define USART_TIMECMP1_TSTART_TXC (_USART_TIMECMP1_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP1 */
-#define USART_TIMECMP1_TSTART_RXACT (_USART_TIMECMP1_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP1 */
-#define USART_TIMECMP1_TSTART_RXEOF (_USART_TIMECMP1_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP1 */
-#define _USART_TIMECMP1_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */
-#define _USART_TIMECMP1_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */
-#define _USART_TIMECMP1_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */
-#define _USART_TIMECMP1_TSTOP_TCMP1 0x00000000UL /**< Mode TCMP1 for USART_TIMECMP1 */
-#define _USART_TIMECMP1_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP1 */
-#define _USART_TIMECMP1_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP1 */
-#define _USART_TIMECMP1_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP1 */
-#define USART_TIMECMP1_TSTOP_DEFAULT (_USART_TIMECMP1_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP1 */
-#define USART_TIMECMP1_TSTOP_TCMP1 (_USART_TIMECMP1_TSTOP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMECMP1 */
-#define USART_TIMECMP1_TSTOP_TXST (_USART_TIMECMP1_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP1 */
-#define USART_TIMECMP1_TSTOP_RXACT (_USART_TIMECMP1_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP1 */
-#define USART_TIMECMP1_TSTOP_RXACTN (_USART_TIMECMP1_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP1 */
-#define USART_TIMECMP1_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP1 */
-#define _USART_TIMECMP1_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */
-#define _USART_TIMECMP1_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */
-#define _USART_TIMECMP1_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */
-#define USART_TIMECMP1_RESTARTEN_DEFAULT (_USART_TIMECMP1_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP1 */
-
-/* Bit fields for USART TIMECMP2 */
-#define _USART_TIMECMP2_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP2 */
-#define _USART_TIMECMP2_MASK 0x017700FFUL /**< Mask for USART_TIMECMP2 */
-#define _USART_TIMECMP2_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */
-#define _USART_TIMECMP2_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */
-#define _USART_TIMECMP2_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */
-#define USART_TIMECMP2_TCMPVAL_DEFAULT (_USART_TIMECMP2_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP2 */
-#define _USART_TIMECMP2_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */
-#define _USART_TIMECMP2_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */
-#define _USART_TIMECMP2_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */
-#define _USART_TIMECMP2_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */
-#define _USART_TIMECMP2_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP2 */
-#define _USART_TIMECMP2_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP2 */
-#define _USART_TIMECMP2_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP2 */
-#define _USART_TIMECMP2_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP2 */
-#define USART_TIMECMP2_TSTART_DEFAULT (_USART_TIMECMP2_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP2 */
-#define USART_TIMECMP2_TSTART_DISABLE (_USART_TIMECMP2_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP2 */
-#define USART_TIMECMP2_TSTART_TXEOF (_USART_TIMECMP2_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP2 */
-#define USART_TIMECMP2_TSTART_TXC (_USART_TIMECMP2_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP2 */
-#define USART_TIMECMP2_TSTART_RXACT (_USART_TIMECMP2_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP2 */
-#define USART_TIMECMP2_TSTART_RXEOF (_USART_TIMECMP2_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP2 */
-#define _USART_TIMECMP2_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */
-#define _USART_TIMECMP2_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */
-#define _USART_TIMECMP2_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */
-#define _USART_TIMECMP2_TSTOP_TCMP2 0x00000000UL /**< Mode TCMP2 for USART_TIMECMP2 */
-#define _USART_TIMECMP2_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP2 */
-#define _USART_TIMECMP2_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP2 */
-#define _USART_TIMECMP2_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP2 */
-#define USART_TIMECMP2_TSTOP_DEFAULT (_USART_TIMECMP2_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP2 */
-#define USART_TIMECMP2_TSTOP_TCMP2 (_USART_TIMECMP2_TSTOP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMECMP2 */
-#define USART_TIMECMP2_TSTOP_TXST (_USART_TIMECMP2_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP2 */
-#define USART_TIMECMP2_TSTOP_RXACT (_USART_TIMECMP2_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP2 */
-#define USART_TIMECMP2_TSTOP_RXACTN (_USART_TIMECMP2_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP2 */
-#define USART_TIMECMP2_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP2 */
-#define _USART_TIMECMP2_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */
-#define _USART_TIMECMP2_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */
-#define _USART_TIMECMP2_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */
-#define USART_TIMECMP2_RESTARTEN_DEFAULT (_USART_TIMECMP2_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP2 */
-
-/* Bit fields for USART ROUTEPEN */
-#define _USART_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTEPEN */
-#define _USART_ROUTEPEN_MASK 0x0000003FUL /**< Mask for USART_ROUTEPEN */
-#define USART_ROUTEPEN_RXPEN (0x1UL << 0) /**< RX Pin Enable */
-#define _USART_ROUTEPEN_RXPEN_SHIFT 0 /**< Shift value for USART_RXPEN */
-#define _USART_ROUTEPEN_RXPEN_MASK 0x1UL /**< Bit mask for USART_RXPEN */
-#define _USART_ROUTEPEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */
-#define USART_ROUTEPEN_RXPEN_DEFAULT (_USART_ROUTEPEN_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
-#define USART_ROUTEPEN_TXPEN (0x1UL << 1) /**< TX Pin Enable */
-#define _USART_ROUTEPEN_TXPEN_SHIFT 1 /**< Shift value for USART_TXPEN */
-#define _USART_ROUTEPEN_TXPEN_MASK 0x2UL /**< Bit mask for USART_TXPEN */
-#define _USART_ROUTEPEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */
-#define USART_ROUTEPEN_TXPEN_DEFAULT (_USART_ROUTEPEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
-#define USART_ROUTEPEN_CSPEN (0x1UL << 2) /**< CS Pin Enable */
-#define _USART_ROUTEPEN_CSPEN_SHIFT 2 /**< Shift value for USART_CSPEN */
-#define _USART_ROUTEPEN_CSPEN_MASK 0x4UL /**< Bit mask for USART_CSPEN */
-#define _USART_ROUTEPEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */
-#define USART_ROUTEPEN_CSPEN_DEFAULT (_USART_ROUTEPEN_CSPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
-#define USART_ROUTEPEN_CLKPEN (0x1UL << 3) /**< CLK Pin Enable */
-#define _USART_ROUTEPEN_CLKPEN_SHIFT 3 /**< Shift value for USART_CLKPEN */
-#define _USART_ROUTEPEN_CLKPEN_MASK 0x8UL /**< Bit mask for USART_CLKPEN */
-#define _USART_ROUTEPEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */
-#define USART_ROUTEPEN_CLKPEN_DEFAULT (_USART_ROUTEPEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
-#define USART_ROUTEPEN_CTSPEN (0x1UL << 4) /**< CTS Pin Enable */
-#define _USART_ROUTEPEN_CTSPEN_SHIFT 4 /**< Shift value for USART_CTSPEN */
-#define _USART_ROUTEPEN_CTSPEN_MASK 0x10UL /**< Bit mask for USART_CTSPEN */
-#define _USART_ROUTEPEN_CTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */
-#define USART_ROUTEPEN_CTSPEN_DEFAULT (_USART_ROUTEPEN_CTSPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
-#define USART_ROUTEPEN_RTSPEN (0x1UL << 5) /**< RTS Pin Enable */
-#define _USART_ROUTEPEN_RTSPEN_SHIFT 5 /**< Shift value for USART_RTSPEN */
-#define _USART_ROUTEPEN_RTSPEN_MASK 0x20UL /**< Bit mask for USART_RTSPEN */
-#define _USART_ROUTEPEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */
-#define USART_ROUTEPEN_RTSPEN_DEFAULT (_USART_ROUTEPEN_RTSPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
-
-/* Bit fields for USART ROUTELOC0 */
-#define _USART_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_SHIFT 0 /**< Shift value for USART_RXLOC */
-#define _USART_ROUTELOC0_RXLOC_MASK 0x1FUL /**< Bit mask for USART_RXLOC */
-#define _USART_ROUTELOC0_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_RXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC0 (_USART_ROUTELOC0_RXLOC_LOC0 << 0) /**< Shifted mode LOC0 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_DEFAULT (_USART_ROUTELOC0_RXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC1 (_USART_ROUTELOC0_RXLOC_LOC1 << 0) /**< Shifted mode LOC1 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC2 (_USART_ROUTELOC0_RXLOC_LOC2 << 0) /**< Shifted mode LOC2 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC3 (_USART_ROUTELOC0_RXLOC_LOC3 << 0) /**< Shifted mode LOC3 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC4 (_USART_ROUTELOC0_RXLOC_LOC4 << 0) /**< Shifted mode LOC4 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC5 (_USART_ROUTELOC0_RXLOC_LOC5 << 0) /**< Shifted mode LOC5 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC6 (_USART_ROUTELOC0_RXLOC_LOC6 << 0) /**< Shifted mode LOC6 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC7 (_USART_ROUTELOC0_RXLOC_LOC7 << 0) /**< Shifted mode LOC7 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC8 (_USART_ROUTELOC0_RXLOC_LOC8 << 0) /**< Shifted mode LOC8 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC9 (_USART_ROUTELOC0_RXLOC_LOC9 << 0) /**< Shifted mode LOC9 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC10 (_USART_ROUTELOC0_RXLOC_LOC10 << 0) /**< Shifted mode LOC10 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC11 (_USART_ROUTELOC0_RXLOC_LOC11 << 0) /**< Shifted mode LOC11 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC12 (_USART_ROUTELOC0_RXLOC_LOC12 << 0) /**< Shifted mode LOC12 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC13 (_USART_ROUTELOC0_RXLOC_LOC13 << 0) /**< Shifted mode LOC13 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC14 (_USART_ROUTELOC0_RXLOC_LOC14 << 0) /**< Shifted mode LOC14 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC15 (_USART_ROUTELOC0_RXLOC_LOC15 << 0) /**< Shifted mode LOC15 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC16 (_USART_ROUTELOC0_RXLOC_LOC16 << 0) /**< Shifted mode LOC16 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC17 (_USART_ROUTELOC0_RXLOC_LOC17 << 0) /**< Shifted mode LOC17 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC18 (_USART_ROUTELOC0_RXLOC_LOC18 << 0) /**< Shifted mode LOC18 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC19 (_USART_ROUTELOC0_RXLOC_LOC19 << 0) /**< Shifted mode LOC19 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC20 (_USART_ROUTELOC0_RXLOC_LOC20 << 0) /**< Shifted mode LOC20 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC21 (_USART_ROUTELOC0_RXLOC_LOC21 << 0) /**< Shifted mode LOC21 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC22 (_USART_ROUTELOC0_RXLOC_LOC22 << 0) /**< Shifted mode LOC22 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC23 (_USART_ROUTELOC0_RXLOC_LOC23 << 0) /**< Shifted mode LOC23 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC24 (_USART_ROUTELOC0_RXLOC_LOC24 << 0) /**< Shifted mode LOC24 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC25 (_USART_ROUTELOC0_RXLOC_LOC25 << 0) /**< Shifted mode LOC25 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC26 (_USART_ROUTELOC0_RXLOC_LOC26 << 0) /**< Shifted mode LOC26 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC27 (_USART_ROUTELOC0_RXLOC_LOC27 << 0) /**< Shifted mode LOC27 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC28 (_USART_ROUTELOC0_RXLOC_LOC28 << 0) /**< Shifted mode LOC28 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC29 (_USART_ROUTELOC0_RXLOC_LOC29 << 0) /**< Shifted mode LOC29 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC30 (_USART_ROUTELOC0_RXLOC_LOC30 << 0) /**< Shifted mode LOC30 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_RXLOC_LOC31 (_USART_ROUTELOC0_RXLOC_LOC31 << 0) /**< Shifted mode LOC31 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_SHIFT 8 /**< Shift value for USART_TXLOC */
-#define _USART_ROUTELOC0_TXLOC_MASK 0x1F00UL /**< Bit mask for USART_TXLOC */
-#define _USART_ROUTELOC0_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_TXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC0 (_USART_ROUTELOC0_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_DEFAULT (_USART_ROUTELOC0_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC1 (_USART_ROUTELOC0_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC2 (_USART_ROUTELOC0_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC3 (_USART_ROUTELOC0_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC4 (_USART_ROUTELOC0_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC5 (_USART_ROUTELOC0_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC6 (_USART_ROUTELOC0_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC7 (_USART_ROUTELOC0_TXLOC_LOC7 << 8) /**< Shifted mode LOC7 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC8 (_USART_ROUTELOC0_TXLOC_LOC8 << 8) /**< Shifted mode LOC8 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC9 (_USART_ROUTELOC0_TXLOC_LOC9 << 8) /**< Shifted mode LOC9 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC10 (_USART_ROUTELOC0_TXLOC_LOC10 << 8) /**< Shifted mode LOC10 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC11 (_USART_ROUTELOC0_TXLOC_LOC11 << 8) /**< Shifted mode LOC11 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC12 (_USART_ROUTELOC0_TXLOC_LOC12 << 8) /**< Shifted mode LOC12 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC13 (_USART_ROUTELOC0_TXLOC_LOC13 << 8) /**< Shifted mode LOC13 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC14 (_USART_ROUTELOC0_TXLOC_LOC14 << 8) /**< Shifted mode LOC14 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC15 (_USART_ROUTELOC0_TXLOC_LOC15 << 8) /**< Shifted mode LOC15 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC16 (_USART_ROUTELOC0_TXLOC_LOC16 << 8) /**< Shifted mode LOC16 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC17 (_USART_ROUTELOC0_TXLOC_LOC17 << 8) /**< Shifted mode LOC17 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC18 (_USART_ROUTELOC0_TXLOC_LOC18 << 8) /**< Shifted mode LOC18 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC19 (_USART_ROUTELOC0_TXLOC_LOC19 << 8) /**< Shifted mode LOC19 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC20 (_USART_ROUTELOC0_TXLOC_LOC20 << 8) /**< Shifted mode LOC20 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC21 (_USART_ROUTELOC0_TXLOC_LOC21 << 8) /**< Shifted mode LOC21 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC22 (_USART_ROUTELOC0_TXLOC_LOC22 << 8) /**< Shifted mode LOC22 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC23 (_USART_ROUTELOC0_TXLOC_LOC23 << 8) /**< Shifted mode LOC23 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC24 (_USART_ROUTELOC0_TXLOC_LOC24 << 8) /**< Shifted mode LOC24 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC25 (_USART_ROUTELOC0_TXLOC_LOC25 << 8) /**< Shifted mode LOC25 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC26 (_USART_ROUTELOC0_TXLOC_LOC26 << 8) /**< Shifted mode LOC26 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC27 (_USART_ROUTELOC0_TXLOC_LOC27 << 8) /**< Shifted mode LOC27 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC28 (_USART_ROUTELOC0_TXLOC_LOC28 << 8) /**< Shifted mode LOC28 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC29 (_USART_ROUTELOC0_TXLOC_LOC29 << 8) /**< Shifted mode LOC29 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC30 (_USART_ROUTELOC0_TXLOC_LOC30 << 8) /**< Shifted mode LOC30 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_TXLOC_LOC31 (_USART_ROUTELOC0_TXLOC_LOC31 << 8) /**< Shifted mode LOC31 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_SHIFT 16 /**< Shift value for USART_CSLOC */
-#define _USART_ROUTELOC0_CSLOC_MASK 0x1F0000UL /**< Bit mask for USART_CSLOC */
-#define _USART_ROUTELOC0_CSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC0 (_USART_ROUTELOC0_CSLOC_LOC0 << 16) /**< Shifted mode LOC0 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_DEFAULT (_USART_ROUTELOC0_CSLOC_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC1 (_USART_ROUTELOC0_CSLOC_LOC1 << 16) /**< Shifted mode LOC1 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC2 (_USART_ROUTELOC0_CSLOC_LOC2 << 16) /**< Shifted mode LOC2 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC3 (_USART_ROUTELOC0_CSLOC_LOC3 << 16) /**< Shifted mode LOC3 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC4 (_USART_ROUTELOC0_CSLOC_LOC4 << 16) /**< Shifted mode LOC4 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC5 (_USART_ROUTELOC0_CSLOC_LOC5 << 16) /**< Shifted mode LOC5 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC6 (_USART_ROUTELOC0_CSLOC_LOC6 << 16) /**< Shifted mode LOC6 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC7 (_USART_ROUTELOC0_CSLOC_LOC7 << 16) /**< Shifted mode LOC7 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC8 (_USART_ROUTELOC0_CSLOC_LOC8 << 16) /**< Shifted mode LOC8 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC9 (_USART_ROUTELOC0_CSLOC_LOC9 << 16) /**< Shifted mode LOC9 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC10 (_USART_ROUTELOC0_CSLOC_LOC10 << 16) /**< Shifted mode LOC10 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC11 (_USART_ROUTELOC0_CSLOC_LOC11 << 16) /**< Shifted mode LOC11 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC12 (_USART_ROUTELOC0_CSLOC_LOC12 << 16) /**< Shifted mode LOC12 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC13 (_USART_ROUTELOC0_CSLOC_LOC13 << 16) /**< Shifted mode LOC13 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC14 (_USART_ROUTELOC0_CSLOC_LOC14 << 16) /**< Shifted mode LOC14 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC15 (_USART_ROUTELOC0_CSLOC_LOC15 << 16) /**< Shifted mode LOC15 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC16 (_USART_ROUTELOC0_CSLOC_LOC16 << 16) /**< Shifted mode LOC16 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC17 (_USART_ROUTELOC0_CSLOC_LOC17 << 16) /**< Shifted mode LOC17 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC18 (_USART_ROUTELOC0_CSLOC_LOC18 << 16) /**< Shifted mode LOC18 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC19 (_USART_ROUTELOC0_CSLOC_LOC19 << 16) /**< Shifted mode LOC19 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC20 (_USART_ROUTELOC0_CSLOC_LOC20 << 16) /**< Shifted mode LOC20 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC21 (_USART_ROUTELOC0_CSLOC_LOC21 << 16) /**< Shifted mode LOC21 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC22 (_USART_ROUTELOC0_CSLOC_LOC22 << 16) /**< Shifted mode LOC22 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC23 (_USART_ROUTELOC0_CSLOC_LOC23 << 16) /**< Shifted mode LOC23 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC24 (_USART_ROUTELOC0_CSLOC_LOC24 << 16) /**< Shifted mode LOC24 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC25 (_USART_ROUTELOC0_CSLOC_LOC25 << 16) /**< Shifted mode LOC25 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC26 (_USART_ROUTELOC0_CSLOC_LOC26 << 16) /**< Shifted mode LOC26 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC27 (_USART_ROUTELOC0_CSLOC_LOC27 << 16) /**< Shifted mode LOC27 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC28 (_USART_ROUTELOC0_CSLOC_LOC28 << 16) /**< Shifted mode LOC28 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC29 (_USART_ROUTELOC0_CSLOC_LOC29 << 16) /**< Shifted mode LOC29 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC30 (_USART_ROUTELOC0_CSLOC_LOC30 << 16) /**< Shifted mode LOC30 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CSLOC_LOC31 (_USART_ROUTELOC0_CSLOC_LOC31 << 16) /**< Shifted mode LOC31 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_SHIFT 24 /**< Shift value for USART_CLKLOC */
-#define _USART_ROUTELOC0_CLKLOC_MASK 0x1F000000UL /**< Bit mask for USART_CLKLOC */
-#define _USART_ROUTELOC0_CLKLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */
-#define _USART_ROUTELOC0_CLKLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC0 (_USART_ROUTELOC0_CLKLOC_LOC0 << 24) /**< Shifted mode LOC0 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_DEFAULT (_USART_ROUTELOC0_CLKLOC_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC1 (_USART_ROUTELOC0_CLKLOC_LOC1 << 24) /**< Shifted mode LOC1 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC2 (_USART_ROUTELOC0_CLKLOC_LOC2 << 24) /**< Shifted mode LOC2 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC3 (_USART_ROUTELOC0_CLKLOC_LOC3 << 24) /**< Shifted mode LOC3 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC4 (_USART_ROUTELOC0_CLKLOC_LOC4 << 24) /**< Shifted mode LOC4 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC5 (_USART_ROUTELOC0_CLKLOC_LOC5 << 24) /**< Shifted mode LOC5 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC6 (_USART_ROUTELOC0_CLKLOC_LOC6 << 24) /**< Shifted mode LOC6 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC7 (_USART_ROUTELOC0_CLKLOC_LOC7 << 24) /**< Shifted mode LOC7 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC8 (_USART_ROUTELOC0_CLKLOC_LOC8 << 24) /**< Shifted mode LOC8 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC9 (_USART_ROUTELOC0_CLKLOC_LOC9 << 24) /**< Shifted mode LOC9 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC10 (_USART_ROUTELOC0_CLKLOC_LOC10 << 24) /**< Shifted mode LOC10 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC11 (_USART_ROUTELOC0_CLKLOC_LOC11 << 24) /**< Shifted mode LOC11 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC12 (_USART_ROUTELOC0_CLKLOC_LOC12 << 24) /**< Shifted mode LOC12 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC13 (_USART_ROUTELOC0_CLKLOC_LOC13 << 24) /**< Shifted mode LOC13 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC14 (_USART_ROUTELOC0_CLKLOC_LOC14 << 24) /**< Shifted mode LOC14 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC15 (_USART_ROUTELOC0_CLKLOC_LOC15 << 24) /**< Shifted mode LOC15 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC16 (_USART_ROUTELOC0_CLKLOC_LOC16 << 24) /**< Shifted mode LOC16 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC17 (_USART_ROUTELOC0_CLKLOC_LOC17 << 24) /**< Shifted mode LOC17 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC18 (_USART_ROUTELOC0_CLKLOC_LOC18 << 24) /**< Shifted mode LOC18 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC19 (_USART_ROUTELOC0_CLKLOC_LOC19 << 24) /**< Shifted mode LOC19 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC20 (_USART_ROUTELOC0_CLKLOC_LOC20 << 24) /**< Shifted mode LOC20 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC21 (_USART_ROUTELOC0_CLKLOC_LOC21 << 24) /**< Shifted mode LOC21 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC22 (_USART_ROUTELOC0_CLKLOC_LOC22 << 24) /**< Shifted mode LOC22 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC23 (_USART_ROUTELOC0_CLKLOC_LOC23 << 24) /**< Shifted mode LOC23 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC24 (_USART_ROUTELOC0_CLKLOC_LOC24 << 24) /**< Shifted mode LOC24 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC25 (_USART_ROUTELOC0_CLKLOC_LOC25 << 24) /**< Shifted mode LOC25 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC26 (_USART_ROUTELOC0_CLKLOC_LOC26 << 24) /**< Shifted mode LOC26 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC27 (_USART_ROUTELOC0_CLKLOC_LOC27 << 24) /**< Shifted mode LOC27 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC28 (_USART_ROUTELOC0_CLKLOC_LOC28 << 24) /**< Shifted mode LOC28 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC29 (_USART_ROUTELOC0_CLKLOC_LOC29 << 24) /**< Shifted mode LOC29 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC30 (_USART_ROUTELOC0_CLKLOC_LOC30 << 24) /**< Shifted mode LOC30 for USART_ROUTELOC0 */
-#define USART_ROUTELOC0_CLKLOC_LOC31 (_USART_ROUTELOC0_CLKLOC_LOC31 << 24) /**< Shifted mode LOC31 for USART_ROUTELOC0 */
-
-/* Bit fields for USART ROUTELOC1 */
-#define _USART_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_MASK 0x00001F1FUL /**< Mask for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_SHIFT 0 /**< Shift value for USART_CTSLOC */
-#define _USART_ROUTELOC1_CTSLOC_MASK 0x1FUL /**< Bit mask for USART_CTSLOC */
-#define _USART_ROUTELOC1_CTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_CTSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC0 (_USART_ROUTELOC1_CTSLOC_LOC0 << 0) /**< Shifted mode LOC0 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_DEFAULT (_USART_ROUTELOC1_CTSLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC1 (_USART_ROUTELOC1_CTSLOC_LOC1 << 0) /**< Shifted mode LOC1 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC2 (_USART_ROUTELOC1_CTSLOC_LOC2 << 0) /**< Shifted mode LOC2 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC3 (_USART_ROUTELOC1_CTSLOC_LOC3 << 0) /**< Shifted mode LOC3 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC4 (_USART_ROUTELOC1_CTSLOC_LOC4 << 0) /**< Shifted mode LOC4 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC5 (_USART_ROUTELOC1_CTSLOC_LOC5 << 0) /**< Shifted mode LOC5 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC6 (_USART_ROUTELOC1_CTSLOC_LOC6 << 0) /**< Shifted mode LOC6 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC7 (_USART_ROUTELOC1_CTSLOC_LOC7 << 0) /**< Shifted mode LOC7 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC8 (_USART_ROUTELOC1_CTSLOC_LOC8 << 0) /**< Shifted mode LOC8 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC9 (_USART_ROUTELOC1_CTSLOC_LOC9 << 0) /**< Shifted mode LOC9 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC10 (_USART_ROUTELOC1_CTSLOC_LOC10 << 0) /**< Shifted mode LOC10 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC11 (_USART_ROUTELOC1_CTSLOC_LOC11 << 0) /**< Shifted mode LOC11 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC12 (_USART_ROUTELOC1_CTSLOC_LOC12 << 0) /**< Shifted mode LOC12 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC13 (_USART_ROUTELOC1_CTSLOC_LOC13 << 0) /**< Shifted mode LOC13 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC14 (_USART_ROUTELOC1_CTSLOC_LOC14 << 0) /**< Shifted mode LOC14 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC15 (_USART_ROUTELOC1_CTSLOC_LOC15 << 0) /**< Shifted mode LOC15 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC16 (_USART_ROUTELOC1_CTSLOC_LOC16 << 0) /**< Shifted mode LOC16 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC17 (_USART_ROUTELOC1_CTSLOC_LOC17 << 0) /**< Shifted mode LOC17 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC18 (_USART_ROUTELOC1_CTSLOC_LOC18 << 0) /**< Shifted mode LOC18 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC19 (_USART_ROUTELOC1_CTSLOC_LOC19 << 0) /**< Shifted mode LOC19 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC20 (_USART_ROUTELOC1_CTSLOC_LOC20 << 0) /**< Shifted mode LOC20 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC21 (_USART_ROUTELOC1_CTSLOC_LOC21 << 0) /**< Shifted mode LOC21 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC22 (_USART_ROUTELOC1_CTSLOC_LOC22 << 0) /**< Shifted mode LOC22 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC23 (_USART_ROUTELOC1_CTSLOC_LOC23 << 0) /**< Shifted mode LOC23 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC24 (_USART_ROUTELOC1_CTSLOC_LOC24 << 0) /**< Shifted mode LOC24 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC25 (_USART_ROUTELOC1_CTSLOC_LOC25 << 0) /**< Shifted mode LOC25 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC26 (_USART_ROUTELOC1_CTSLOC_LOC26 << 0) /**< Shifted mode LOC26 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC27 (_USART_ROUTELOC1_CTSLOC_LOC27 << 0) /**< Shifted mode LOC27 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC28 (_USART_ROUTELOC1_CTSLOC_LOC28 << 0) /**< Shifted mode LOC28 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC29 (_USART_ROUTELOC1_CTSLOC_LOC29 << 0) /**< Shifted mode LOC29 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC30 (_USART_ROUTELOC1_CTSLOC_LOC30 << 0) /**< Shifted mode LOC30 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_CTSLOC_LOC31 (_USART_ROUTELOC1_CTSLOC_LOC31 << 0) /**< Shifted mode LOC31 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_SHIFT 8 /**< Shift value for USART_RTSLOC */
-#define _USART_ROUTELOC1_RTSLOC_MASK 0x1F00UL /**< Bit mask for USART_RTSLOC */
-#define _USART_ROUTELOC1_RTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC1 */
-#define _USART_ROUTELOC1_RTSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC0 (_USART_ROUTELOC1_RTSLOC_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_DEFAULT (_USART_ROUTELOC1_RTSLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC1 (_USART_ROUTELOC1_RTSLOC_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC2 (_USART_ROUTELOC1_RTSLOC_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC3 (_USART_ROUTELOC1_RTSLOC_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC4 (_USART_ROUTELOC1_RTSLOC_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC5 (_USART_ROUTELOC1_RTSLOC_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC6 (_USART_ROUTELOC1_RTSLOC_LOC6 << 8) /**< Shifted mode LOC6 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC7 (_USART_ROUTELOC1_RTSLOC_LOC7 << 8) /**< Shifted mode LOC7 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC8 (_USART_ROUTELOC1_RTSLOC_LOC8 << 8) /**< Shifted mode LOC8 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC9 (_USART_ROUTELOC1_RTSLOC_LOC9 << 8) /**< Shifted mode LOC9 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC10 (_USART_ROUTELOC1_RTSLOC_LOC10 << 8) /**< Shifted mode LOC10 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC11 (_USART_ROUTELOC1_RTSLOC_LOC11 << 8) /**< Shifted mode LOC11 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC12 (_USART_ROUTELOC1_RTSLOC_LOC12 << 8) /**< Shifted mode LOC12 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC13 (_USART_ROUTELOC1_RTSLOC_LOC13 << 8) /**< Shifted mode LOC13 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC14 (_USART_ROUTELOC1_RTSLOC_LOC14 << 8) /**< Shifted mode LOC14 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC15 (_USART_ROUTELOC1_RTSLOC_LOC15 << 8) /**< Shifted mode LOC15 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC16 (_USART_ROUTELOC1_RTSLOC_LOC16 << 8) /**< Shifted mode LOC16 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC17 (_USART_ROUTELOC1_RTSLOC_LOC17 << 8) /**< Shifted mode LOC17 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC18 (_USART_ROUTELOC1_RTSLOC_LOC18 << 8) /**< Shifted mode LOC18 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC19 (_USART_ROUTELOC1_RTSLOC_LOC19 << 8) /**< Shifted mode LOC19 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC20 (_USART_ROUTELOC1_RTSLOC_LOC20 << 8) /**< Shifted mode LOC20 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC21 (_USART_ROUTELOC1_RTSLOC_LOC21 << 8) /**< Shifted mode LOC21 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC22 (_USART_ROUTELOC1_RTSLOC_LOC22 << 8) /**< Shifted mode LOC22 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC23 (_USART_ROUTELOC1_RTSLOC_LOC23 << 8) /**< Shifted mode LOC23 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC24 (_USART_ROUTELOC1_RTSLOC_LOC24 << 8) /**< Shifted mode LOC24 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC25 (_USART_ROUTELOC1_RTSLOC_LOC25 << 8) /**< Shifted mode LOC25 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC26 (_USART_ROUTELOC1_RTSLOC_LOC26 << 8) /**< Shifted mode LOC26 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC27 (_USART_ROUTELOC1_RTSLOC_LOC27 << 8) /**< Shifted mode LOC27 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC28 (_USART_ROUTELOC1_RTSLOC_LOC28 << 8) /**< Shifted mode LOC28 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC29 (_USART_ROUTELOC1_RTSLOC_LOC29 << 8) /**< Shifted mode LOC29 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC30 (_USART_ROUTELOC1_RTSLOC_LOC30 << 8) /**< Shifted mode LOC30 for USART_ROUTELOC1 */
-#define USART_ROUTELOC1_RTSLOC_LOC31 (_USART_ROUTELOC1_RTSLOC_LOC31 << 8) /**< Shifted mode LOC31 for USART_ROUTELOC1 */
-
-/** @} */
-/** @} End of group EFR32FG13P_USART */
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_vdac.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_vdac.h
deleted file mode 100644
index cb113581..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_vdac.h
+++ /dev/null
@@ -1,1548 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_vdac.h
- * @brief EFR32FG13P_VDAC register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P_VDAC VDAC
- * @{
- * @brief EFR32FG13P_VDAC Register Declaration
- *****************************************************************************/
-/** VDAC Register Declaration */
-typedef struct {
- __IOM uint32_t CTRL; /**< Control Register */
- __IM uint32_t STATUS; /**< Status Register */
- __IOM uint32_t CH0CTRL; /**< Channel 0 Control Register */
- __IOM uint32_t CH1CTRL; /**< Channel 1 Control Register */
- __IOM uint32_t CMD; /**< Command Register */
- __IM uint32_t IF; /**< Interrupt Flag Register */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
- __IOM uint32_t CH0DATA; /**< Channel 0 Data Register */
- __IOM uint32_t CH1DATA; /**< Channel 1 Data Register */
- __IOM uint32_t COMBDATA; /**< Combined Data Register */
- __IOM uint32_t CAL; /**< Calibration Register */
-
- uint32_t RESERVED0[27]; /**< Reserved registers */
- VDAC_OPA_TypeDef OPA[3]; /**< OPA Registers */
-} VDAC_TypeDef; /** @} */
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_VDAC
- * @{
- * @defgroup EFR32FG13P_VDAC_BitFields VDAC Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for VDAC CTRL */
-#define _VDAC_CTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_CTRL */
-#define _VDAC_CTRL_MASK 0x937F0771UL /**< Mask for VDAC_CTRL */
-#define VDAC_CTRL_DIFF (0x1UL << 0) /**< Differential Mode */
-#define _VDAC_CTRL_DIFF_SHIFT 0 /**< Shift value for VDAC_DIFF */
-#define _VDAC_CTRL_DIFF_MASK 0x1UL /**< Bit mask for VDAC_DIFF */
-#define _VDAC_CTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */
-#define VDAC_CTRL_DIFF_DEFAULT (_VDAC_CTRL_DIFF_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CTRL */
-#define VDAC_CTRL_SINEMODE (0x1UL << 4) /**< Sine Mode */
-#define _VDAC_CTRL_SINEMODE_SHIFT 4 /**< Shift value for VDAC_SINEMODE */
-#define _VDAC_CTRL_SINEMODE_MASK 0x10UL /**< Bit mask for VDAC_SINEMODE */
-#define _VDAC_CTRL_SINEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */
-#define VDAC_CTRL_SINEMODE_DEFAULT (_VDAC_CTRL_SINEMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CTRL */
-#define VDAC_CTRL_OUTENPRS (0x1UL << 5) /**< PRS Controlled Output Enable */
-#define _VDAC_CTRL_OUTENPRS_SHIFT 5 /**< Shift value for VDAC_OUTENPRS */
-#define _VDAC_CTRL_OUTENPRS_MASK 0x20UL /**< Bit mask for VDAC_OUTENPRS */
-#define _VDAC_CTRL_OUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */
-#define VDAC_CTRL_OUTENPRS_DEFAULT (_VDAC_CTRL_OUTENPRS_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_CTRL */
-#define VDAC_CTRL_CH0PRESCRST (0x1UL << 6) /**< Channel 0 Start Reset Prescaler */
-#define _VDAC_CTRL_CH0PRESCRST_SHIFT 6 /**< Shift value for VDAC_CH0PRESCRST */
-#define _VDAC_CTRL_CH0PRESCRST_MASK 0x40UL /**< Bit mask for VDAC_CH0PRESCRST */
-#define _VDAC_CTRL_CH0PRESCRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */
-#define VDAC_CTRL_CH0PRESCRST_DEFAULT (_VDAC_CTRL_CH0PRESCRST_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_CTRL */
-#define _VDAC_CTRL_REFSEL_SHIFT 8 /**< Shift value for VDAC_REFSEL */
-#define _VDAC_CTRL_REFSEL_MASK 0x700UL /**< Bit mask for VDAC_REFSEL */
-#define _VDAC_CTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */
-#define _VDAC_CTRL_REFSEL_1V25LN 0x00000000UL /**< Mode 1V25LN for VDAC_CTRL */
-#define _VDAC_CTRL_REFSEL_2V5LN 0x00000001UL /**< Mode 2V5LN for VDAC_CTRL */
-#define _VDAC_CTRL_REFSEL_1V25 0x00000002UL /**< Mode 1V25 for VDAC_CTRL */
-#define _VDAC_CTRL_REFSEL_2V5 0x00000003UL /**< Mode 2V5 for VDAC_CTRL */
-#define _VDAC_CTRL_REFSEL_VDD 0x00000004UL /**< Mode VDD for VDAC_CTRL */
-#define _VDAC_CTRL_REFSEL_EXT 0x00000006UL /**< Mode EXT for VDAC_CTRL */
-#define VDAC_CTRL_REFSEL_DEFAULT (_VDAC_CTRL_REFSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CTRL */
-#define VDAC_CTRL_REFSEL_1V25LN (_VDAC_CTRL_REFSEL_1V25LN << 8) /**< Shifted mode 1V25LN for VDAC_CTRL */
-#define VDAC_CTRL_REFSEL_2V5LN (_VDAC_CTRL_REFSEL_2V5LN << 8) /**< Shifted mode 2V5LN for VDAC_CTRL */
-#define VDAC_CTRL_REFSEL_1V25 (_VDAC_CTRL_REFSEL_1V25 << 8) /**< Shifted mode 1V25 for VDAC_CTRL */
-#define VDAC_CTRL_REFSEL_2V5 (_VDAC_CTRL_REFSEL_2V5 << 8) /**< Shifted mode 2V5 for VDAC_CTRL */
-#define VDAC_CTRL_REFSEL_VDD (_VDAC_CTRL_REFSEL_VDD << 8) /**< Shifted mode VDD for VDAC_CTRL */
-#define VDAC_CTRL_REFSEL_EXT (_VDAC_CTRL_REFSEL_EXT << 8) /**< Shifted mode EXT for VDAC_CTRL */
-#define _VDAC_CTRL_PRESC_SHIFT 16 /**< Shift value for VDAC_PRESC */
-#define _VDAC_CTRL_PRESC_MASK 0x7F0000UL /**< Bit mask for VDAC_PRESC */
-#define _VDAC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */
-#define _VDAC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for VDAC_CTRL */
-#define VDAC_CTRL_PRESC_DEFAULT (_VDAC_CTRL_PRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CTRL */
-#define VDAC_CTRL_PRESC_NODIVISION (_VDAC_CTRL_PRESC_NODIVISION << 16) /**< Shifted mode NODIVISION for VDAC_CTRL */
-#define _VDAC_CTRL_REFRESHPERIOD_SHIFT 24 /**< Shift value for VDAC_REFRESHPERIOD */
-#define _VDAC_CTRL_REFRESHPERIOD_MASK 0x3000000UL /**< Bit mask for VDAC_REFRESHPERIOD */
-#define _VDAC_CTRL_REFRESHPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */
-#define _VDAC_CTRL_REFRESHPERIOD_8CYCLES 0x00000000UL /**< Mode 8CYCLES for VDAC_CTRL */
-#define _VDAC_CTRL_REFRESHPERIOD_16CYCLES 0x00000001UL /**< Mode 16CYCLES for VDAC_CTRL */
-#define _VDAC_CTRL_REFRESHPERIOD_32CYCLES 0x00000002UL /**< Mode 32CYCLES for VDAC_CTRL */
-#define _VDAC_CTRL_REFRESHPERIOD_64CYCLES 0x00000003UL /**< Mode 64CYCLES for VDAC_CTRL */
-#define VDAC_CTRL_REFRESHPERIOD_DEFAULT (_VDAC_CTRL_REFRESHPERIOD_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_CTRL */
-#define VDAC_CTRL_REFRESHPERIOD_8CYCLES (_VDAC_CTRL_REFRESHPERIOD_8CYCLES << 24) /**< Shifted mode 8CYCLES for VDAC_CTRL */
-#define VDAC_CTRL_REFRESHPERIOD_16CYCLES (_VDAC_CTRL_REFRESHPERIOD_16CYCLES << 24) /**< Shifted mode 16CYCLES for VDAC_CTRL */
-#define VDAC_CTRL_REFRESHPERIOD_32CYCLES (_VDAC_CTRL_REFRESHPERIOD_32CYCLES << 24) /**< Shifted mode 32CYCLES for VDAC_CTRL */
-#define VDAC_CTRL_REFRESHPERIOD_64CYCLES (_VDAC_CTRL_REFRESHPERIOD_64CYCLES << 24) /**< Shifted mode 64CYCLES for VDAC_CTRL */
-#define VDAC_CTRL_WARMUPMODE (0x1UL << 28) /**< Warm-up Mode */
-#define _VDAC_CTRL_WARMUPMODE_SHIFT 28 /**< Shift value for VDAC_WARMUPMODE */
-#define _VDAC_CTRL_WARMUPMODE_MASK 0x10000000UL /**< Bit mask for VDAC_WARMUPMODE */
-#define _VDAC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */
-#define _VDAC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for VDAC_CTRL */
-#define _VDAC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for VDAC_CTRL */
-#define VDAC_CTRL_WARMUPMODE_DEFAULT (_VDAC_CTRL_WARMUPMODE_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_CTRL */
-#define VDAC_CTRL_WARMUPMODE_NORMAL (_VDAC_CTRL_WARMUPMODE_NORMAL << 28) /**< Shifted mode NORMAL for VDAC_CTRL */
-#define VDAC_CTRL_WARMUPMODE_KEEPINSTANDBY (_VDAC_CTRL_WARMUPMODE_KEEPINSTANDBY << 28) /**< Shifted mode KEEPINSTANDBY for VDAC_CTRL */
-#define VDAC_CTRL_DACCLKMODE (0x1UL << 31) /**< Clock Mode */
-#define _VDAC_CTRL_DACCLKMODE_SHIFT 31 /**< Shift value for VDAC_DACCLKMODE */
-#define _VDAC_CTRL_DACCLKMODE_MASK 0x80000000UL /**< Bit mask for VDAC_DACCLKMODE */
-#define _VDAC_CTRL_DACCLKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */
-#define _VDAC_CTRL_DACCLKMODE_SYNC 0x00000000UL /**< Mode SYNC for VDAC_CTRL */
-#define _VDAC_CTRL_DACCLKMODE_ASYNC 0x00000001UL /**< Mode ASYNC for VDAC_CTRL */
-#define VDAC_CTRL_DACCLKMODE_DEFAULT (_VDAC_CTRL_DACCLKMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for VDAC_CTRL */
-#define VDAC_CTRL_DACCLKMODE_SYNC (_VDAC_CTRL_DACCLKMODE_SYNC << 31) /**< Shifted mode SYNC for VDAC_CTRL */
-#define VDAC_CTRL_DACCLKMODE_ASYNC (_VDAC_CTRL_DACCLKMODE_ASYNC << 31) /**< Shifted mode ASYNC for VDAC_CTRL */
-
-/* Bit fields for VDAC STATUS */
-#define _VDAC_STATUS_RESETVALUE 0x0000000CUL /**< Default value for VDAC_STATUS */
-#define _VDAC_STATUS_MASK 0x7777003FUL /**< Mask for VDAC_STATUS */
-#define VDAC_STATUS_CH0ENS (0x1UL << 0) /**< Channel 0 Enabled Status */
-#define _VDAC_STATUS_CH0ENS_SHIFT 0 /**< Shift value for VDAC_CH0ENS */
-#define _VDAC_STATUS_CH0ENS_MASK 0x1UL /**< Bit mask for VDAC_CH0ENS */
-#define _VDAC_STATUS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_CH0ENS_DEFAULT (_VDAC_STATUS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_CH1ENS (0x1UL << 1) /**< Channel 1 Enabled Status */
-#define _VDAC_STATUS_CH1ENS_SHIFT 1 /**< Shift value for VDAC_CH1ENS */
-#define _VDAC_STATUS_CH1ENS_MASK 0x2UL /**< Bit mask for VDAC_CH1ENS */
-#define _VDAC_STATUS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_CH1ENS_DEFAULT (_VDAC_STATUS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_CH0BL (0x1UL << 2) /**< Channel 0 Buffer Level */
-#define _VDAC_STATUS_CH0BL_SHIFT 2 /**< Shift value for VDAC_CH0BL */
-#define _VDAC_STATUS_CH0BL_MASK 0x4UL /**< Bit mask for VDAC_CH0BL */
-#define _VDAC_STATUS_CH0BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_CH0BL_DEFAULT (_VDAC_STATUS_CH0BL_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_CH1BL (0x1UL << 3) /**< Channel 1 Buffer Level */
-#define _VDAC_STATUS_CH1BL_SHIFT 3 /**< Shift value for VDAC_CH1BL */
-#define _VDAC_STATUS_CH1BL_MASK 0x8UL /**< Bit mask for VDAC_CH1BL */
-#define _VDAC_STATUS_CH1BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_CH1BL_DEFAULT (_VDAC_STATUS_CH1BL_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_CH0WARM (0x1UL << 4) /**< Channel 0 Warm */
-#define _VDAC_STATUS_CH0WARM_SHIFT 4 /**< Shift value for VDAC_CH0WARM */
-#define _VDAC_STATUS_CH0WARM_MASK 0x10UL /**< Bit mask for VDAC_CH0WARM */
-#define _VDAC_STATUS_CH0WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_CH0WARM_DEFAULT (_VDAC_STATUS_CH0WARM_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_CH1WARM (0x1UL << 5) /**< Channel 1 Warm */
-#define _VDAC_STATUS_CH1WARM_SHIFT 5 /**< Shift value for VDAC_CH1WARM */
-#define _VDAC_STATUS_CH1WARM_MASK 0x20UL /**< Bit mask for VDAC_CH1WARM */
-#define _VDAC_STATUS_CH1WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_CH1WARM_DEFAULT (_VDAC_STATUS_CH1WARM_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_OPA0APORTCONFLICT (0x1UL << 16) /**< OPA0 Bus Conflict Output */
-#define _VDAC_STATUS_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */
-#define _VDAC_STATUS_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */
-#define _VDAC_STATUS_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_OPA0APORTCONFLICT_DEFAULT (_VDAC_STATUS_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_OPA1APORTCONFLICT (0x1UL << 17) /**< OPA1 Bus Conflict Output */
-#define _VDAC_STATUS_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */
-#define _VDAC_STATUS_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */
-#define _VDAC_STATUS_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_OPA1APORTCONFLICT_DEFAULT (_VDAC_STATUS_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_OPA2APORTCONFLICT (0x1UL << 18) /**< OPA2 Bus Conflict Output */
-#define _VDAC_STATUS_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */
-#define _VDAC_STATUS_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */
-#define _VDAC_STATUS_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_OPA2APORTCONFLICT_DEFAULT (_VDAC_STATUS_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_OPA0ENS (0x1UL << 20) /**< OPA0 Enabled Status */
-#define _VDAC_STATUS_OPA0ENS_SHIFT 20 /**< Shift value for VDAC_OPA0ENS */
-#define _VDAC_STATUS_OPA0ENS_MASK 0x100000UL /**< Bit mask for VDAC_OPA0ENS */
-#define _VDAC_STATUS_OPA0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_OPA0ENS_DEFAULT (_VDAC_STATUS_OPA0ENS_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_OPA1ENS (0x1UL << 21) /**< OPA1 Enabled Status */
-#define _VDAC_STATUS_OPA1ENS_SHIFT 21 /**< Shift value for VDAC_OPA1ENS */
-#define _VDAC_STATUS_OPA1ENS_MASK 0x200000UL /**< Bit mask for VDAC_OPA1ENS */
-#define _VDAC_STATUS_OPA1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_OPA1ENS_DEFAULT (_VDAC_STATUS_OPA1ENS_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_OPA2ENS (0x1UL << 22) /**< OPA2 Enabled Status */
-#define _VDAC_STATUS_OPA2ENS_SHIFT 22 /**< Shift value for VDAC_OPA2ENS */
-#define _VDAC_STATUS_OPA2ENS_MASK 0x400000UL /**< Bit mask for VDAC_OPA2ENS */
-#define _VDAC_STATUS_OPA2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_OPA2ENS_DEFAULT (_VDAC_STATUS_OPA2ENS_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_OPA0WARM (0x1UL << 24) /**< OPA0 Warm Status */
-#define _VDAC_STATUS_OPA0WARM_SHIFT 24 /**< Shift value for VDAC_OPA0WARM */
-#define _VDAC_STATUS_OPA0WARM_MASK 0x1000000UL /**< Bit mask for VDAC_OPA0WARM */
-#define _VDAC_STATUS_OPA0WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_OPA0WARM_DEFAULT (_VDAC_STATUS_OPA0WARM_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_OPA1WARM (0x1UL << 25) /**< OPA1 Warm Status */
-#define _VDAC_STATUS_OPA1WARM_SHIFT 25 /**< Shift value for VDAC_OPA1WARM */
-#define _VDAC_STATUS_OPA1WARM_MASK 0x2000000UL /**< Bit mask for VDAC_OPA1WARM */
-#define _VDAC_STATUS_OPA1WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_OPA1WARM_DEFAULT (_VDAC_STATUS_OPA1WARM_DEFAULT << 25) /**< Shifted mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_OPA2WARM (0x1UL << 26) /**< OPA2 Warm Status */
-#define _VDAC_STATUS_OPA2WARM_SHIFT 26 /**< Shift value for VDAC_OPA2WARM */
-#define _VDAC_STATUS_OPA2WARM_MASK 0x4000000UL /**< Bit mask for VDAC_OPA2WARM */
-#define _VDAC_STATUS_OPA2WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_OPA2WARM_DEFAULT (_VDAC_STATUS_OPA2WARM_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_OPA0OUTVALID (0x1UL << 28) /**< OPA0 Output Valid Status */
-#define _VDAC_STATUS_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */
-#define _VDAC_STATUS_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */
-#define _VDAC_STATUS_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_OPA0OUTVALID_DEFAULT (_VDAC_STATUS_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_OPA1OUTVALID (0x1UL << 29) /**< OPA1 Output Valid Status */
-#define _VDAC_STATUS_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */
-#define _VDAC_STATUS_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */
-#define _VDAC_STATUS_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_OPA1OUTVALID_DEFAULT (_VDAC_STATUS_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_OPA2OUTVALID (0x1UL << 30) /**< OPA2 Output Valid Status */
-#define _VDAC_STATUS_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */
-#define _VDAC_STATUS_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */
-#define _VDAC_STATUS_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
-#define VDAC_STATUS_OPA2OUTVALID_DEFAULT (_VDAC_STATUS_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_STATUS */
-
-/* Bit fields for VDAC CH0CTRL */
-#define _VDAC_CH0CTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH0CTRL */
-#define _VDAC_CH0CTRL_MASK 0x0000F171UL /**< Mask for VDAC_CH0CTRL */
-#define VDAC_CH0CTRL_CONVMODE (0x1UL << 0) /**< Conversion Mode */
-#define _VDAC_CH0CTRL_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */
-#define _VDAC_CH0CTRL_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */
-#define _VDAC_CH0CTRL_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */
-#define _VDAC_CH0CTRL_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH0CTRL */
-#define _VDAC_CH0CTRL_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH0CTRL */
-#define VDAC_CH0CTRL_CONVMODE_DEFAULT (_VDAC_CH0CTRL_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */
-#define VDAC_CH0CTRL_CONVMODE_CONTINUOUS (_VDAC_CH0CTRL_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH0CTRL */
-#define VDAC_CH0CTRL_CONVMODE_SAMPLEOFF (_VDAC_CH0CTRL_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH0CTRL */
-#define _VDAC_CH0CTRL_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */
-#define _VDAC_CH0CTRL_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */
-#define _VDAC_CH0CTRL_TRIGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */
-#define _VDAC_CH0CTRL_TRIGMODE_SW 0x00000000UL /**< Mode SW for VDAC_CH0CTRL */
-#define _VDAC_CH0CTRL_TRIGMODE_PRS 0x00000001UL /**< Mode PRS for VDAC_CH0CTRL */
-#define _VDAC_CH0CTRL_TRIGMODE_REFRESH 0x00000002UL /**< Mode REFRESH for VDAC_CH0CTRL */
-#define _VDAC_CH0CTRL_TRIGMODE_SWPRS 0x00000003UL /**< Mode SWPRS for VDAC_CH0CTRL */
-#define _VDAC_CH0CTRL_TRIGMODE_SWREFRESH 0x00000004UL /**< Mode SWREFRESH for VDAC_CH0CTRL */
-#define _VDAC_CH0CTRL_TRIGMODE_LESENSE 0x00000005UL /**< Mode LESENSE for VDAC_CH0CTRL */
-#define VDAC_CH0CTRL_TRIGMODE_DEFAULT (_VDAC_CH0CTRL_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */
-#define VDAC_CH0CTRL_TRIGMODE_SW (_VDAC_CH0CTRL_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH0CTRL */
-#define VDAC_CH0CTRL_TRIGMODE_PRS (_VDAC_CH0CTRL_TRIGMODE_PRS << 4) /**< Shifted mode PRS for VDAC_CH0CTRL */
-#define VDAC_CH0CTRL_TRIGMODE_REFRESH (_VDAC_CH0CTRL_TRIGMODE_REFRESH << 4) /**< Shifted mode REFRESH for VDAC_CH0CTRL */
-#define VDAC_CH0CTRL_TRIGMODE_SWPRS (_VDAC_CH0CTRL_TRIGMODE_SWPRS << 4) /**< Shifted mode SWPRS for VDAC_CH0CTRL */
-#define VDAC_CH0CTRL_TRIGMODE_SWREFRESH (_VDAC_CH0CTRL_TRIGMODE_SWREFRESH << 4) /**< Shifted mode SWREFRESH for VDAC_CH0CTRL */
-#define VDAC_CH0CTRL_TRIGMODE_LESENSE (_VDAC_CH0CTRL_TRIGMODE_LESENSE << 4) /**< Shifted mode LESENSE for VDAC_CH0CTRL */
-#define VDAC_CH0CTRL_PRSASYNC (0x1UL << 8) /**< Channel 0 PRS Asynchronous Enable */
-#define _VDAC_CH0CTRL_PRSASYNC_SHIFT 8 /**< Shift value for VDAC_PRSASYNC */
-#define _VDAC_CH0CTRL_PRSASYNC_MASK 0x100UL /**< Bit mask for VDAC_PRSASYNC */
-#define _VDAC_CH0CTRL_PRSASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */
-#define VDAC_CH0CTRL_PRSASYNC_DEFAULT (_VDAC_CH0CTRL_PRSASYNC_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */
-#define _VDAC_CH0CTRL_PRSSEL_SHIFT 12 /**< Shift value for VDAC_PRSSEL */
-#define _VDAC_CH0CTRL_PRSSEL_MASK 0xF000UL /**< Bit mask for VDAC_PRSSEL */
-#define _VDAC_CH0CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */
-#define _VDAC_CH0CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for VDAC_CH0CTRL */
-#define _VDAC_CH0CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for VDAC_CH0CTRL */
-#define _VDAC_CH0CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for VDAC_CH0CTRL */
-#define _VDAC_CH0CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for VDAC_CH0CTRL */
-#define _VDAC_CH0CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for VDAC_CH0CTRL */
-#define _VDAC_CH0CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for VDAC_CH0CTRL */
-#define _VDAC_CH0CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for VDAC_CH0CTRL */
-#define _VDAC_CH0CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for VDAC_CH0CTRL */
-#define _VDAC_CH0CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for VDAC_CH0CTRL */
-#define _VDAC_CH0CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for VDAC_CH0CTRL */
-#define _VDAC_CH0CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for VDAC_CH0CTRL */
-#define _VDAC_CH0CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for VDAC_CH0CTRL */
-#define VDAC_CH0CTRL_PRSSEL_DEFAULT (_VDAC_CH0CTRL_PRSSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */
-#define VDAC_CH0CTRL_PRSSEL_PRSCH0 (_VDAC_CH0CTRL_PRSSEL_PRSCH0 << 12) /**< Shifted mode PRSCH0 for VDAC_CH0CTRL */
-#define VDAC_CH0CTRL_PRSSEL_PRSCH1 (_VDAC_CH0CTRL_PRSSEL_PRSCH1 << 12) /**< Shifted mode PRSCH1 for VDAC_CH0CTRL */
-#define VDAC_CH0CTRL_PRSSEL_PRSCH2 (_VDAC_CH0CTRL_PRSSEL_PRSCH2 << 12) /**< Shifted mode PRSCH2 for VDAC_CH0CTRL */
-#define VDAC_CH0CTRL_PRSSEL_PRSCH3 (_VDAC_CH0CTRL_PRSSEL_PRSCH3 << 12) /**< Shifted mode PRSCH3 for VDAC_CH0CTRL */
-#define VDAC_CH0CTRL_PRSSEL_PRSCH4 (_VDAC_CH0CTRL_PRSSEL_PRSCH4 << 12) /**< Shifted mode PRSCH4 for VDAC_CH0CTRL */
-#define VDAC_CH0CTRL_PRSSEL_PRSCH5 (_VDAC_CH0CTRL_PRSSEL_PRSCH5 << 12) /**< Shifted mode PRSCH5 for VDAC_CH0CTRL */
-#define VDAC_CH0CTRL_PRSSEL_PRSCH6 (_VDAC_CH0CTRL_PRSSEL_PRSCH6 << 12) /**< Shifted mode PRSCH6 for VDAC_CH0CTRL */
-#define VDAC_CH0CTRL_PRSSEL_PRSCH7 (_VDAC_CH0CTRL_PRSSEL_PRSCH7 << 12) /**< Shifted mode PRSCH7 for VDAC_CH0CTRL */
-#define VDAC_CH0CTRL_PRSSEL_PRSCH8 (_VDAC_CH0CTRL_PRSSEL_PRSCH8 << 12) /**< Shifted mode PRSCH8 for VDAC_CH0CTRL */
-#define VDAC_CH0CTRL_PRSSEL_PRSCH9 (_VDAC_CH0CTRL_PRSSEL_PRSCH9 << 12) /**< Shifted mode PRSCH9 for VDAC_CH0CTRL */
-#define VDAC_CH0CTRL_PRSSEL_PRSCH10 (_VDAC_CH0CTRL_PRSSEL_PRSCH10 << 12) /**< Shifted mode PRSCH10 for VDAC_CH0CTRL */
-#define VDAC_CH0CTRL_PRSSEL_PRSCH11 (_VDAC_CH0CTRL_PRSSEL_PRSCH11 << 12) /**< Shifted mode PRSCH11 for VDAC_CH0CTRL */
-
-/* Bit fields for VDAC CH1CTRL */
-#define _VDAC_CH1CTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH1CTRL */
-#define _VDAC_CH1CTRL_MASK 0x0000F171UL /**< Mask for VDAC_CH1CTRL */
-#define VDAC_CH1CTRL_CONVMODE (0x1UL << 0) /**< Conversion Mode */
-#define _VDAC_CH1CTRL_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */
-#define _VDAC_CH1CTRL_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */
-#define _VDAC_CH1CTRL_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */
-#define _VDAC_CH1CTRL_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH1CTRL */
-#define _VDAC_CH1CTRL_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH1CTRL */
-#define VDAC_CH1CTRL_CONVMODE_DEFAULT (_VDAC_CH1CTRL_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */
-#define VDAC_CH1CTRL_CONVMODE_CONTINUOUS (_VDAC_CH1CTRL_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH1CTRL */
-#define VDAC_CH1CTRL_CONVMODE_SAMPLEOFF (_VDAC_CH1CTRL_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH1CTRL */
-#define _VDAC_CH1CTRL_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */
-#define _VDAC_CH1CTRL_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */
-#define _VDAC_CH1CTRL_TRIGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */
-#define _VDAC_CH1CTRL_TRIGMODE_SW 0x00000000UL /**< Mode SW for VDAC_CH1CTRL */
-#define _VDAC_CH1CTRL_TRIGMODE_PRS 0x00000001UL /**< Mode PRS for VDAC_CH1CTRL */
-#define _VDAC_CH1CTRL_TRIGMODE_REFRESH 0x00000002UL /**< Mode REFRESH for VDAC_CH1CTRL */
-#define _VDAC_CH1CTRL_TRIGMODE_SWPRS 0x00000003UL /**< Mode SWPRS for VDAC_CH1CTRL */
-#define _VDAC_CH1CTRL_TRIGMODE_SWREFRESH 0x00000004UL /**< Mode SWREFRESH for VDAC_CH1CTRL */
-#define _VDAC_CH1CTRL_TRIGMODE_LESENSE 0x00000005UL /**< Mode LESENSE for VDAC_CH1CTRL */
-#define VDAC_CH1CTRL_TRIGMODE_DEFAULT (_VDAC_CH1CTRL_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */
-#define VDAC_CH1CTRL_TRIGMODE_SW (_VDAC_CH1CTRL_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH1CTRL */
-#define VDAC_CH1CTRL_TRIGMODE_PRS (_VDAC_CH1CTRL_TRIGMODE_PRS << 4) /**< Shifted mode PRS for VDAC_CH1CTRL */
-#define VDAC_CH1CTRL_TRIGMODE_REFRESH (_VDAC_CH1CTRL_TRIGMODE_REFRESH << 4) /**< Shifted mode REFRESH for VDAC_CH1CTRL */
-#define VDAC_CH1CTRL_TRIGMODE_SWPRS (_VDAC_CH1CTRL_TRIGMODE_SWPRS << 4) /**< Shifted mode SWPRS for VDAC_CH1CTRL */
-#define VDAC_CH1CTRL_TRIGMODE_SWREFRESH (_VDAC_CH1CTRL_TRIGMODE_SWREFRESH << 4) /**< Shifted mode SWREFRESH for VDAC_CH1CTRL */
-#define VDAC_CH1CTRL_TRIGMODE_LESENSE (_VDAC_CH1CTRL_TRIGMODE_LESENSE << 4) /**< Shifted mode LESENSE for VDAC_CH1CTRL */
-#define VDAC_CH1CTRL_PRSASYNC (0x1UL << 8) /**< Channel 1 PRS Asynchronous Enable */
-#define _VDAC_CH1CTRL_PRSASYNC_SHIFT 8 /**< Shift value for VDAC_PRSASYNC */
-#define _VDAC_CH1CTRL_PRSASYNC_MASK 0x100UL /**< Bit mask for VDAC_PRSASYNC */
-#define _VDAC_CH1CTRL_PRSASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */
-#define VDAC_CH1CTRL_PRSASYNC_DEFAULT (_VDAC_CH1CTRL_PRSASYNC_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */
-#define _VDAC_CH1CTRL_PRSSEL_SHIFT 12 /**< Shift value for VDAC_PRSSEL */
-#define _VDAC_CH1CTRL_PRSSEL_MASK 0xF000UL /**< Bit mask for VDAC_PRSSEL */
-#define _VDAC_CH1CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */
-#define _VDAC_CH1CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for VDAC_CH1CTRL */
-#define _VDAC_CH1CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for VDAC_CH1CTRL */
-#define _VDAC_CH1CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for VDAC_CH1CTRL */
-#define _VDAC_CH1CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for VDAC_CH1CTRL */
-#define _VDAC_CH1CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for VDAC_CH1CTRL */
-#define _VDAC_CH1CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for VDAC_CH1CTRL */
-#define _VDAC_CH1CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for VDAC_CH1CTRL */
-#define _VDAC_CH1CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for VDAC_CH1CTRL */
-#define _VDAC_CH1CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for VDAC_CH1CTRL */
-#define _VDAC_CH1CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for VDAC_CH1CTRL */
-#define _VDAC_CH1CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for VDAC_CH1CTRL */
-#define _VDAC_CH1CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for VDAC_CH1CTRL */
-#define VDAC_CH1CTRL_PRSSEL_DEFAULT (_VDAC_CH1CTRL_PRSSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */
-#define VDAC_CH1CTRL_PRSSEL_PRSCH0 (_VDAC_CH1CTRL_PRSSEL_PRSCH0 << 12) /**< Shifted mode PRSCH0 for VDAC_CH1CTRL */
-#define VDAC_CH1CTRL_PRSSEL_PRSCH1 (_VDAC_CH1CTRL_PRSSEL_PRSCH1 << 12) /**< Shifted mode PRSCH1 for VDAC_CH1CTRL */
-#define VDAC_CH1CTRL_PRSSEL_PRSCH2 (_VDAC_CH1CTRL_PRSSEL_PRSCH2 << 12) /**< Shifted mode PRSCH2 for VDAC_CH1CTRL */
-#define VDAC_CH1CTRL_PRSSEL_PRSCH3 (_VDAC_CH1CTRL_PRSSEL_PRSCH3 << 12) /**< Shifted mode PRSCH3 for VDAC_CH1CTRL */
-#define VDAC_CH1CTRL_PRSSEL_PRSCH4 (_VDAC_CH1CTRL_PRSSEL_PRSCH4 << 12) /**< Shifted mode PRSCH4 for VDAC_CH1CTRL */
-#define VDAC_CH1CTRL_PRSSEL_PRSCH5 (_VDAC_CH1CTRL_PRSSEL_PRSCH5 << 12) /**< Shifted mode PRSCH5 for VDAC_CH1CTRL */
-#define VDAC_CH1CTRL_PRSSEL_PRSCH6 (_VDAC_CH1CTRL_PRSSEL_PRSCH6 << 12) /**< Shifted mode PRSCH6 for VDAC_CH1CTRL */
-#define VDAC_CH1CTRL_PRSSEL_PRSCH7 (_VDAC_CH1CTRL_PRSSEL_PRSCH7 << 12) /**< Shifted mode PRSCH7 for VDAC_CH1CTRL */
-#define VDAC_CH1CTRL_PRSSEL_PRSCH8 (_VDAC_CH1CTRL_PRSSEL_PRSCH8 << 12) /**< Shifted mode PRSCH8 for VDAC_CH1CTRL */
-#define VDAC_CH1CTRL_PRSSEL_PRSCH9 (_VDAC_CH1CTRL_PRSSEL_PRSCH9 << 12) /**< Shifted mode PRSCH9 for VDAC_CH1CTRL */
-#define VDAC_CH1CTRL_PRSSEL_PRSCH10 (_VDAC_CH1CTRL_PRSSEL_PRSCH10 << 12) /**< Shifted mode PRSCH10 for VDAC_CH1CTRL */
-#define VDAC_CH1CTRL_PRSSEL_PRSCH11 (_VDAC_CH1CTRL_PRSSEL_PRSCH11 << 12) /**< Shifted mode PRSCH11 for VDAC_CH1CTRL */
-
-/* Bit fields for VDAC CMD */
-#define _VDAC_CMD_RESETVALUE 0x00000000UL /**< Default value for VDAC_CMD */
-#define _VDAC_CMD_MASK 0x003F000FUL /**< Mask for VDAC_CMD */
-#define VDAC_CMD_CH0EN (0x1UL << 0) /**< DAC Channel 0 Enable */
-#define _VDAC_CMD_CH0EN_SHIFT 0 /**< Shift value for VDAC_CH0EN */
-#define _VDAC_CMD_CH0EN_MASK 0x1UL /**< Bit mask for VDAC_CH0EN */
-#define _VDAC_CMD_CH0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */
-#define VDAC_CMD_CH0EN_DEFAULT (_VDAC_CMD_CH0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CMD */
-#define VDAC_CMD_CH0DIS (0x1UL << 1) /**< DAC Channel 0 Disable */
-#define _VDAC_CMD_CH0DIS_SHIFT 1 /**< Shift value for VDAC_CH0DIS */
-#define _VDAC_CMD_CH0DIS_MASK 0x2UL /**< Bit mask for VDAC_CH0DIS */
-#define _VDAC_CMD_CH0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */
-#define VDAC_CMD_CH0DIS_DEFAULT (_VDAC_CMD_CH0DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_CMD */
-#define VDAC_CMD_CH1EN (0x1UL << 2) /**< DAC Channel 1 Enable */
-#define _VDAC_CMD_CH1EN_SHIFT 2 /**< Shift value for VDAC_CH1EN */
-#define _VDAC_CMD_CH1EN_MASK 0x4UL /**< Bit mask for VDAC_CH1EN */
-#define _VDAC_CMD_CH1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */
-#define VDAC_CMD_CH1EN_DEFAULT (_VDAC_CMD_CH1EN_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CMD */
-#define VDAC_CMD_CH1DIS (0x1UL << 3) /**< DAC Channel 1 Disable */
-#define _VDAC_CMD_CH1DIS_SHIFT 3 /**< Shift value for VDAC_CH1DIS */
-#define _VDAC_CMD_CH1DIS_MASK 0x8UL /**< Bit mask for VDAC_CH1DIS */
-#define _VDAC_CMD_CH1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */
-#define VDAC_CMD_CH1DIS_DEFAULT (_VDAC_CMD_CH1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_CMD */
-#define VDAC_CMD_OPA0EN (0x1UL << 16) /**< OPA0 Enable */
-#define _VDAC_CMD_OPA0EN_SHIFT 16 /**< Shift value for VDAC_OPA0EN */
-#define _VDAC_CMD_OPA0EN_MASK 0x10000UL /**< Bit mask for VDAC_OPA0EN */
-#define _VDAC_CMD_OPA0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */
-#define VDAC_CMD_OPA0EN_DEFAULT (_VDAC_CMD_OPA0EN_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CMD */
-#define VDAC_CMD_OPA0DIS (0x1UL << 17) /**< OPA0 Disable */
-#define _VDAC_CMD_OPA0DIS_SHIFT 17 /**< Shift value for VDAC_OPA0DIS */
-#define _VDAC_CMD_OPA0DIS_MASK 0x20000UL /**< Bit mask for VDAC_OPA0DIS */
-#define _VDAC_CMD_OPA0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */
-#define VDAC_CMD_OPA0DIS_DEFAULT (_VDAC_CMD_OPA0DIS_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_CMD */
-#define VDAC_CMD_OPA1EN (0x1UL << 18) /**< OPA1 Enable */
-#define _VDAC_CMD_OPA1EN_SHIFT 18 /**< Shift value for VDAC_OPA1EN */
-#define _VDAC_CMD_OPA1EN_MASK 0x40000UL /**< Bit mask for VDAC_OPA1EN */
-#define _VDAC_CMD_OPA1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */
-#define VDAC_CMD_OPA1EN_DEFAULT (_VDAC_CMD_OPA1EN_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_CMD */
-#define VDAC_CMD_OPA1DIS (0x1UL << 19) /**< OPA1 Disable */
-#define _VDAC_CMD_OPA1DIS_SHIFT 19 /**< Shift value for VDAC_OPA1DIS */
-#define _VDAC_CMD_OPA1DIS_MASK 0x80000UL /**< Bit mask for VDAC_OPA1DIS */
-#define _VDAC_CMD_OPA1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */
-#define VDAC_CMD_OPA1DIS_DEFAULT (_VDAC_CMD_OPA1DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for VDAC_CMD */
-#define VDAC_CMD_OPA2EN (0x1UL << 20) /**< OPA2 Enable */
-#define _VDAC_CMD_OPA2EN_SHIFT 20 /**< Shift value for VDAC_OPA2EN */
-#define _VDAC_CMD_OPA2EN_MASK 0x100000UL /**< Bit mask for VDAC_OPA2EN */
-#define _VDAC_CMD_OPA2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */
-#define VDAC_CMD_OPA2EN_DEFAULT (_VDAC_CMD_OPA2EN_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_CMD */
-#define VDAC_CMD_OPA2DIS (0x1UL << 21) /**< OPA2 Disable */
-#define _VDAC_CMD_OPA2DIS_SHIFT 21 /**< Shift value for VDAC_OPA2DIS */
-#define _VDAC_CMD_OPA2DIS_MASK 0x200000UL /**< Bit mask for VDAC_OPA2DIS */
-#define _VDAC_CMD_OPA2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */
-#define VDAC_CMD_OPA2DIS_DEFAULT (_VDAC_CMD_OPA2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_CMD */
-
-/* Bit fields for VDAC IF */
-#define _VDAC_IF_RESETVALUE 0x000000C0UL /**< Default value for VDAC_IF */
-#define _VDAC_IF_MASK 0x707780FFUL /**< Mask for VDAC_IF */
-#define VDAC_IF_CH0CD (0x1UL << 0) /**< Channel 0 Conversion Done Interrupt Flag */
-#define _VDAC_IF_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */
-#define _VDAC_IF_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */
-#define _VDAC_IF_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
-#define VDAC_IF_CH0CD_DEFAULT (_VDAC_IF_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IF */
-#define VDAC_IF_CH1CD (0x1UL << 1) /**< Channel 1 Conversion Done Interrupt Flag */
-#define _VDAC_IF_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */
-#define _VDAC_IF_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */
-#define _VDAC_IF_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
-#define VDAC_IF_CH1CD_DEFAULT (_VDAC_IF_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IF */
-#define VDAC_IF_CH0OF (0x1UL << 2) /**< Channel 0 Data Overflow Interrupt Flag */
-#define _VDAC_IF_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */
-#define _VDAC_IF_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */
-#define _VDAC_IF_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
-#define VDAC_IF_CH0OF_DEFAULT (_VDAC_IF_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IF */
-#define VDAC_IF_CH1OF (0x1UL << 3) /**< Channel 1 Data Overflow Interrupt Flag */
-#define _VDAC_IF_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */
-#define _VDAC_IF_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */
-#define _VDAC_IF_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
-#define VDAC_IF_CH1OF_DEFAULT (_VDAC_IF_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IF */
-#define VDAC_IF_CH0UF (0x1UL << 4) /**< Channel 0 Data Underflow Interrupt Flag */
-#define _VDAC_IF_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */
-#define _VDAC_IF_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */
-#define _VDAC_IF_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
-#define VDAC_IF_CH0UF_DEFAULT (_VDAC_IF_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IF */
-#define VDAC_IF_CH1UF (0x1UL << 5) /**< Channel 1 Data Underflow Interrupt Flag */
-#define _VDAC_IF_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */
-#define _VDAC_IF_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */
-#define _VDAC_IF_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
-#define VDAC_IF_CH1UF_DEFAULT (_VDAC_IF_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IF */
-#define VDAC_IF_CH0BL (0x1UL << 6) /**< Channel 0 Buffer Level Interrupt Flag */
-#define _VDAC_IF_CH0BL_SHIFT 6 /**< Shift value for VDAC_CH0BL */
-#define _VDAC_IF_CH0BL_MASK 0x40UL /**< Bit mask for VDAC_CH0BL */
-#define _VDAC_IF_CH0BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_IF */
-#define VDAC_IF_CH0BL_DEFAULT (_VDAC_IF_CH0BL_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_IF */
-#define VDAC_IF_CH1BL (0x1UL << 7) /**< Channel 1 Buffer Level Interrupt Flag */
-#define _VDAC_IF_CH1BL_SHIFT 7 /**< Shift value for VDAC_CH1BL */
-#define _VDAC_IF_CH1BL_MASK 0x80UL /**< Bit mask for VDAC_CH1BL */
-#define _VDAC_IF_CH1BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_IF */
-#define VDAC_IF_CH1BL_DEFAULT (_VDAC_IF_CH1BL_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_IF */
-#define VDAC_IF_EM23ERR (0x1UL << 15) /**< EM2/3 Entry Error Flag */
-#define _VDAC_IF_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */
-#define _VDAC_IF_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */
-#define _VDAC_IF_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
-#define VDAC_IF_EM23ERR_DEFAULT (_VDAC_IF_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IF */
-#define VDAC_IF_OPA0APORTCONFLICT (0x1UL << 16) /**< OPA0 Bus Conflict Output Interrupt Flag */
-#define _VDAC_IF_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */
-#define _VDAC_IF_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */
-#define _VDAC_IF_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
-#define VDAC_IF_OPA0APORTCONFLICT_DEFAULT (_VDAC_IF_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IF */
-#define VDAC_IF_OPA1APORTCONFLICT (0x1UL << 17) /**< OPA1 Bus Conflict Output Interrupt Flag */
-#define _VDAC_IF_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */
-#define _VDAC_IF_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */
-#define _VDAC_IF_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
-#define VDAC_IF_OPA1APORTCONFLICT_DEFAULT (_VDAC_IF_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IF */
-#define VDAC_IF_OPA2APORTCONFLICT (0x1UL << 18) /**< OPA2 Bus Conflict Output Interrupt Flag */
-#define _VDAC_IF_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */
-#define _VDAC_IF_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */
-#define _VDAC_IF_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
-#define VDAC_IF_OPA2APORTCONFLICT_DEFAULT (_VDAC_IF_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IF */
-#define VDAC_IF_OPA0PRSTIMEDERR (0x1UL << 20) /**< OPA0 PRS Trigger Mode Error Interrupt Flag */
-#define _VDAC_IF_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */
-#define _VDAC_IF_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */
-#define _VDAC_IF_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
-#define VDAC_IF_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IF_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IF */
-#define VDAC_IF_OPA1PRSTIMEDERR (0x1UL << 21) /**< OPA1 PRS Trigger Mode Error Interrupt Flag */
-#define _VDAC_IF_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */
-#define _VDAC_IF_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */
-#define _VDAC_IF_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
-#define VDAC_IF_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IF_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IF */
-#define VDAC_IF_OPA2PRSTIMEDERR (0x1UL << 22) /**< OPA2 PRS Trigger Mode Error Interrupt Flag */
-#define _VDAC_IF_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */
-#define _VDAC_IF_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */
-#define _VDAC_IF_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
-#define VDAC_IF_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IF_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IF */
-#define VDAC_IF_OPA0OUTVALID (0x1UL << 28) /**< OPA0 Output Valid Interrupt Flag */
-#define _VDAC_IF_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */
-#define _VDAC_IF_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */
-#define _VDAC_IF_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
-#define VDAC_IF_OPA0OUTVALID_DEFAULT (_VDAC_IF_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IF */
-#define VDAC_IF_OPA1OUTVALID (0x1UL << 29) /**< OPA1 Output Valid Interrupt Flag */
-#define _VDAC_IF_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */
-#define _VDAC_IF_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */
-#define _VDAC_IF_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
-#define VDAC_IF_OPA1OUTVALID_DEFAULT (_VDAC_IF_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IF */
-#define VDAC_IF_OPA2OUTVALID (0x1UL << 30) /**< OPA3 Output Valid Interrupt Flag */
-#define _VDAC_IF_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */
-#define _VDAC_IF_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */
-#define _VDAC_IF_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
-#define VDAC_IF_OPA2OUTVALID_DEFAULT (_VDAC_IF_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IF */
-
-/* Bit fields for VDAC IFS */
-#define _VDAC_IFS_RESETVALUE 0x00000000UL /**< Default value for VDAC_IFS */
-#define _VDAC_IFS_MASK 0x7077803FUL /**< Mask for VDAC_IFS */
-#define VDAC_IFS_CH0CD (0x1UL << 0) /**< Set CH0CD Interrupt Flag */
-#define _VDAC_IFS_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */
-#define _VDAC_IFS_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */
-#define _VDAC_IFS_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */
-#define VDAC_IFS_CH0CD_DEFAULT (_VDAC_IFS_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IFS */
-#define VDAC_IFS_CH1CD (0x1UL << 1) /**< Set CH1CD Interrupt Flag */
-#define _VDAC_IFS_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */
-#define _VDAC_IFS_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */
-#define _VDAC_IFS_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */
-#define VDAC_IFS_CH1CD_DEFAULT (_VDAC_IFS_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IFS */
-#define VDAC_IFS_CH0OF (0x1UL << 2) /**< Set CH0OF Interrupt Flag */
-#define _VDAC_IFS_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */
-#define _VDAC_IFS_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */
-#define _VDAC_IFS_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */
-#define VDAC_IFS_CH0OF_DEFAULT (_VDAC_IFS_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IFS */
-#define VDAC_IFS_CH1OF (0x1UL << 3) /**< Set CH1OF Interrupt Flag */
-#define _VDAC_IFS_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */
-#define _VDAC_IFS_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */
-#define _VDAC_IFS_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */
-#define VDAC_IFS_CH1OF_DEFAULT (_VDAC_IFS_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IFS */
-#define VDAC_IFS_CH0UF (0x1UL << 4) /**< Set CH0UF Interrupt Flag */
-#define _VDAC_IFS_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */
-#define _VDAC_IFS_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */
-#define _VDAC_IFS_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */
-#define VDAC_IFS_CH0UF_DEFAULT (_VDAC_IFS_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IFS */
-#define VDAC_IFS_CH1UF (0x1UL << 5) /**< Set CH1UF Interrupt Flag */
-#define _VDAC_IFS_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */
-#define _VDAC_IFS_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */
-#define _VDAC_IFS_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */
-#define VDAC_IFS_CH1UF_DEFAULT (_VDAC_IFS_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IFS */
-#define VDAC_IFS_EM23ERR (0x1UL << 15) /**< Set EM23ERR Interrupt Flag */
-#define _VDAC_IFS_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */
-#define _VDAC_IFS_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */
-#define _VDAC_IFS_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */
-#define VDAC_IFS_EM23ERR_DEFAULT (_VDAC_IFS_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IFS */
-#define VDAC_IFS_OPA0APORTCONFLICT (0x1UL << 16) /**< Set OPA0APORTCONFLICT Interrupt Flag */
-#define _VDAC_IFS_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */
-#define _VDAC_IFS_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */
-#define _VDAC_IFS_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */
-#define VDAC_IFS_OPA0APORTCONFLICT_DEFAULT (_VDAC_IFS_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IFS */
-#define VDAC_IFS_OPA1APORTCONFLICT (0x1UL << 17) /**< Set OPA1APORTCONFLICT Interrupt Flag */
-#define _VDAC_IFS_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */
-#define _VDAC_IFS_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */
-#define _VDAC_IFS_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */
-#define VDAC_IFS_OPA1APORTCONFLICT_DEFAULT (_VDAC_IFS_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IFS */
-#define VDAC_IFS_OPA2APORTCONFLICT (0x1UL << 18) /**< Set OPA2APORTCONFLICT Interrupt Flag */
-#define _VDAC_IFS_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */
-#define _VDAC_IFS_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */
-#define _VDAC_IFS_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */
-#define VDAC_IFS_OPA2APORTCONFLICT_DEFAULT (_VDAC_IFS_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IFS */
-#define VDAC_IFS_OPA0PRSTIMEDERR (0x1UL << 20) /**< Set OPA0PRSTIMEDERR Interrupt Flag */
-#define _VDAC_IFS_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */
-#define _VDAC_IFS_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */
-#define _VDAC_IFS_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */
-#define VDAC_IFS_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IFS_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IFS */
-#define VDAC_IFS_OPA1PRSTIMEDERR (0x1UL << 21) /**< Set OPA1PRSTIMEDERR Interrupt Flag */
-#define _VDAC_IFS_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */
-#define _VDAC_IFS_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */
-#define _VDAC_IFS_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */
-#define VDAC_IFS_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IFS_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IFS */
-#define VDAC_IFS_OPA2PRSTIMEDERR (0x1UL << 22) /**< Set OPA2PRSTIMEDERR Interrupt Flag */
-#define _VDAC_IFS_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */
-#define _VDAC_IFS_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */
-#define _VDAC_IFS_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */
-#define VDAC_IFS_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IFS_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IFS */
-#define VDAC_IFS_OPA0OUTVALID (0x1UL << 28) /**< Set OPA0OUTVALID Interrupt Flag */
-#define _VDAC_IFS_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */
-#define _VDAC_IFS_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */
-#define _VDAC_IFS_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */
-#define VDAC_IFS_OPA0OUTVALID_DEFAULT (_VDAC_IFS_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IFS */
-#define VDAC_IFS_OPA1OUTVALID (0x1UL << 29) /**< Set OPA1OUTVALID Interrupt Flag */
-#define _VDAC_IFS_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */
-#define _VDAC_IFS_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */
-#define _VDAC_IFS_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */
-#define VDAC_IFS_OPA1OUTVALID_DEFAULT (_VDAC_IFS_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IFS */
-#define VDAC_IFS_OPA2OUTVALID (0x1UL << 30) /**< Set OPA2OUTVALID Interrupt Flag */
-#define _VDAC_IFS_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */
-#define _VDAC_IFS_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */
-#define _VDAC_IFS_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */
-#define VDAC_IFS_OPA2OUTVALID_DEFAULT (_VDAC_IFS_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IFS */
-
-/* Bit fields for VDAC IFC */
-#define _VDAC_IFC_RESETVALUE 0x00000000UL /**< Default value for VDAC_IFC */
-#define _VDAC_IFC_MASK 0x7077803FUL /**< Mask for VDAC_IFC */
-#define VDAC_IFC_CH0CD (0x1UL << 0) /**< Clear CH0CD Interrupt Flag */
-#define _VDAC_IFC_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */
-#define _VDAC_IFC_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */
-#define _VDAC_IFC_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */
-#define VDAC_IFC_CH0CD_DEFAULT (_VDAC_IFC_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IFC */
-#define VDAC_IFC_CH1CD (0x1UL << 1) /**< Clear CH1CD Interrupt Flag */
-#define _VDAC_IFC_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */
-#define _VDAC_IFC_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */
-#define _VDAC_IFC_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */
-#define VDAC_IFC_CH1CD_DEFAULT (_VDAC_IFC_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IFC */
-#define VDAC_IFC_CH0OF (0x1UL << 2) /**< Clear CH0OF Interrupt Flag */
-#define _VDAC_IFC_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */
-#define _VDAC_IFC_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */
-#define _VDAC_IFC_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */
-#define VDAC_IFC_CH0OF_DEFAULT (_VDAC_IFC_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IFC */
-#define VDAC_IFC_CH1OF (0x1UL << 3) /**< Clear CH1OF Interrupt Flag */
-#define _VDAC_IFC_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */
-#define _VDAC_IFC_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */
-#define _VDAC_IFC_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */
-#define VDAC_IFC_CH1OF_DEFAULT (_VDAC_IFC_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IFC */
-#define VDAC_IFC_CH0UF (0x1UL << 4) /**< Clear CH0UF Interrupt Flag */
-#define _VDAC_IFC_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */
-#define _VDAC_IFC_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */
-#define _VDAC_IFC_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */
-#define VDAC_IFC_CH0UF_DEFAULT (_VDAC_IFC_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IFC */
-#define VDAC_IFC_CH1UF (0x1UL << 5) /**< Clear CH1UF Interrupt Flag */
-#define _VDAC_IFC_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */
-#define _VDAC_IFC_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */
-#define _VDAC_IFC_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */
-#define VDAC_IFC_CH1UF_DEFAULT (_VDAC_IFC_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IFC */
-#define VDAC_IFC_EM23ERR (0x1UL << 15) /**< Clear EM23ERR Interrupt Flag */
-#define _VDAC_IFC_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */
-#define _VDAC_IFC_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */
-#define _VDAC_IFC_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */
-#define VDAC_IFC_EM23ERR_DEFAULT (_VDAC_IFC_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IFC */
-#define VDAC_IFC_OPA0APORTCONFLICT (0x1UL << 16) /**< Clear OPA0APORTCONFLICT Interrupt Flag */
-#define _VDAC_IFC_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */
-#define _VDAC_IFC_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */
-#define _VDAC_IFC_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */
-#define VDAC_IFC_OPA0APORTCONFLICT_DEFAULT (_VDAC_IFC_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IFC */
-#define VDAC_IFC_OPA1APORTCONFLICT (0x1UL << 17) /**< Clear OPA1APORTCONFLICT Interrupt Flag */
-#define _VDAC_IFC_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */
-#define _VDAC_IFC_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */
-#define _VDAC_IFC_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */
-#define VDAC_IFC_OPA1APORTCONFLICT_DEFAULT (_VDAC_IFC_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IFC */
-#define VDAC_IFC_OPA2APORTCONFLICT (0x1UL << 18) /**< Clear OPA2APORTCONFLICT Interrupt Flag */
-#define _VDAC_IFC_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */
-#define _VDAC_IFC_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */
-#define _VDAC_IFC_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */
-#define VDAC_IFC_OPA2APORTCONFLICT_DEFAULT (_VDAC_IFC_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IFC */
-#define VDAC_IFC_OPA0PRSTIMEDERR (0x1UL << 20) /**< Clear OPA0PRSTIMEDERR Interrupt Flag */
-#define _VDAC_IFC_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */
-#define _VDAC_IFC_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */
-#define _VDAC_IFC_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */
-#define VDAC_IFC_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IFC_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IFC */
-#define VDAC_IFC_OPA1PRSTIMEDERR (0x1UL << 21) /**< Clear OPA1PRSTIMEDERR Interrupt Flag */
-#define _VDAC_IFC_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */
-#define _VDAC_IFC_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */
-#define _VDAC_IFC_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */
-#define VDAC_IFC_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IFC_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IFC */
-#define VDAC_IFC_OPA2PRSTIMEDERR (0x1UL << 22) /**< Clear OPA2PRSTIMEDERR Interrupt Flag */
-#define _VDAC_IFC_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */
-#define _VDAC_IFC_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */
-#define _VDAC_IFC_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */
-#define VDAC_IFC_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IFC_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IFC */
-#define VDAC_IFC_OPA0OUTVALID (0x1UL << 28) /**< Clear OPA0OUTVALID Interrupt Flag */
-#define _VDAC_IFC_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */
-#define _VDAC_IFC_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */
-#define _VDAC_IFC_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */
-#define VDAC_IFC_OPA0OUTVALID_DEFAULT (_VDAC_IFC_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IFC */
-#define VDAC_IFC_OPA1OUTVALID (0x1UL << 29) /**< Clear OPA1OUTVALID Interrupt Flag */
-#define _VDAC_IFC_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */
-#define _VDAC_IFC_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */
-#define _VDAC_IFC_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */
-#define VDAC_IFC_OPA1OUTVALID_DEFAULT (_VDAC_IFC_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IFC */
-#define VDAC_IFC_OPA2OUTVALID (0x1UL << 30) /**< Clear OPA2OUTVALID Interrupt Flag */
-#define _VDAC_IFC_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */
-#define _VDAC_IFC_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */
-#define _VDAC_IFC_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */
-#define VDAC_IFC_OPA2OUTVALID_DEFAULT (_VDAC_IFC_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IFC */
-
-/* Bit fields for VDAC IEN */
-#define _VDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for VDAC_IEN */
-#define _VDAC_IEN_MASK 0x707780FFUL /**< Mask for VDAC_IEN */
-#define VDAC_IEN_CH0CD (0x1UL << 0) /**< CH0CD Interrupt Enable */
-#define _VDAC_IEN_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */
-#define _VDAC_IEN_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */
-#define _VDAC_IEN_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_CH0CD_DEFAULT (_VDAC_IEN_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_CH1CD (0x1UL << 1) /**< CH1CD Interrupt Enable */
-#define _VDAC_IEN_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */
-#define _VDAC_IEN_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */
-#define _VDAC_IEN_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_CH1CD_DEFAULT (_VDAC_IEN_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_CH0OF (0x1UL << 2) /**< CH0OF Interrupt Enable */
-#define _VDAC_IEN_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */
-#define _VDAC_IEN_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */
-#define _VDAC_IEN_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_CH0OF_DEFAULT (_VDAC_IEN_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_CH1OF (0x1UL << 3) /**< CH1OF Interrupt Enable */
-#define _VDAC_IEN_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */
-#define _VDAC_IEN_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */
-#define _VDAC_IEN_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_CH1OF_DEFAULT (_VDAC_IEN_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_CH0UF (0x1UL << 4) /**< CH0UF Interrupt Enable */
-#define _VDAC_IEN_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */
-#define _VDAC_IEN_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */
-#define _VDAC_IEN_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_CH0UF_DEFAULT (_VDAC_IEN_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_CH1UF (0x1UL << 5) /**< CH1UF Interrupt Enable */
-#define _VDAC_IEN_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */
-#define _VDAC_IEN_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */
-#define _VDAC_IEN_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_CH1UF_DEFAULT (_VDAC_IEN_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_CH0BL (0x1UL << 6) /**< CH0BL Interrupt Enable */
-#define _VDAC_IEN_CH0BL_SHIFT 6 /**< Shift value for VDAC_CH0BL */
-#define _VDAC_IEN_CH0BL_MASK 0x40UL /**< Bit mask for VDAC_CH0BL */
-#define _VDAC_IEN_CH0BL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_CH0BL_DEFAULT (_VDAC_IEN_CH0BL_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_CH1BL (0x1UL << 7) /**< CH1BL Interrupt Enable */
-#define _VDAC_IEN_CH1BL_SHIFT 7 /**< Shift value for VDAC_CH1BL */
-#define _VDAC_IEN_CH1BL_MASK 0x80UL /**< Bit mask for VDAC_CH1BL */
-#define _VDAC_IEN_CH1BL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_CH1BL_DEFAULT (_VDAC_IEN_CH1BL_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_EM23ERR (0x1UL << 15) /**< EM23ERR Interrupt Enable */
-#define _VDAC_IEN_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */
-#define _VDAC_IEN_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */
-#define _VDAC_IEN_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_EM23ERR_DEFAULT (_VDAC_IEN_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_OPA0APORTCONFLICT (0x1UL << 16) /**< OPA0APORTCONFLICT Interrupt Enable */
-#define _VDAC_IEN_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */
-#define _VDAC_IEN_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */
-#define _VDAC_IEN_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_OPA0APORTCONFLICT_DEFAULT (_VDAC_IEN_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_OPA1APORTCONFLICT (0x1UL << 17) /**< OPA1APORTCONFLICT Interrupt Enable */
-#define _VDAC_IEN_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */
-#define _VDAC_IEN_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */
-#define _VDAC_IEN_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_OPA1APORTCONFLICT_DEFAULT (_VDAC_IEN_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_OPA2APORTCONFLICT (0x1UL << 18) /**< OPA2APORTCONFLICT Interrupt Enable */
-#define _VDAC_IEN_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */
-#define _VDAC_IEN_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */
-#define _VDAC_IEN_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_OPA2APORTCONFLICT_DEFAULT (_VDAC_IEN_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_OPA0PRSTIMEDERR (0x1UL << 20) /**< OPA0PRSTIMEDERR Interrupt Enable */
-#define _VDAC_IEN_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */
-#define _VDAC_IEN_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */
-#define _VDAC_IEN_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IEN_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_OPA1PRSTIMEDERR (0x1UL << 21) /**< OPA1PRSTIMEDERR Interrupt Enable */
-#define _VDAC_IEN_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */
-#define _VDAC_IEN_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */
-#define _VDAC_IEN_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IEN_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_OPA2PRSTIMEDERR (0x1UL << 22) /**< OPA2PRSTIMEDERR Interrupt Enable */
-#define _VDAC_IEN_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */
-#define _VDAC_IEN_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */
-#define _VDAC_IEN_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IEN_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_OPA0OUTVALID (0x1UL << 28) /**< OPA0OUTVALID Interrupt Enable */
-#define _VDAC_IEN_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */
-#define _VDAC_IEN_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */
-#define _VDAC_IEN_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_OPA0OUTVALID_DEFAULT (_VDAC_IEN_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_OPA1OUTVALID (0x1UL << 29) /**< OPA1OUTVALID Interrupt Enable */
-#define _VDAC_IEN_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */
-#define _VDAC_IEN_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */
-#define _VDAC_IEN_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_OPA1OUTVALID_DEFAULT (_VDAC_IEN_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_OPA2OUTVALID (0x1UL << 30) /**< OPA2OUTVALID Interrupt Enable */
-#define _VDAC_IEN_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */
-#define _VDAC_IEN_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */
-#define _VDAC_IEN_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
-#define VDAC_IEN_OPA2OUTVALID_DEFAULT (_VDAC_IEN_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IEN */
-
-/* Bit fields for VDAC CH0DATA */
-#define _VDAC_CH0DATA_RESETVALUE 0x00000800UL /**< Default value for VDAC_CH0DATA */
-#define _VDAC_CH0DATA_MASK 0x00000FFFUL /**< Mask for VDAC_CH0DATA */
-#define _VDAC_CH0DATA_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */
-#define _VDAC_CH0DATA_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */
-#define _VDAC_CH0DATA_DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_CH0DATA */
-#define VDAC_CH0DATA_DATA_DEFAULT (_VDAC_CH0DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0DATA */
-
-/* Bit fields for VDAC CH1DATA */
-#define _VDAC_CH1DATA_RESETVALUE 0x00000800UL /**< Default value for VDAC_CH1DATA */
-#define _VDAC_CH1DATA_MASK 0x00000FFFUL /**< Mask for VDAC_CH1DATA */
-#define _VDAC_CH1DATA_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */
-#define _VDAC_CH1DATA_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */
-#define _VDAC_CH1DATA_DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_CH1DATA */
-#define VDAC_CH1DATA_DATA_DEFAULT (_VDAC_CH1DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1DATA */
-
-/* Bit fields for VDAC COMBDATA */
-#define _VDAC_COMBDATA_RESETVALUE 0x08000800UL /**< Default value for VDAC_COMBDATA */
-#define _VDAC_COMBDATA_MASK 0x0FFF0FFFUL /**< Mask for VDAC_COMBDATA */
-#define _VDAC_COMBDATA_CH0DATA_SHIFT 0 /**< Shift value for VDAC_CH0DATA */
-#define _VDAC_COMBDATA_CH0DATA_MASK 0xFFFUL /**< Bit mask for VDAC_CH0DATA */
-#define _VDAC_COMBDATA_CH0DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_COMBDATA */
-#define VDAC_COMBDATA_CH0DATA_DEFAULT (_VDAC_COMBDATA_CH0DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_COMBDATA */
-#define _VDAC_COMBDATA_CH1DATA_SHIFT 16 /**< Shift value for VDAC_CH1DATA */
-#define _VDAC_COMBDATA_CH1DATA_MASK 0xFFF0000UL /**< Bit mask for VDAC_CH1DATA */
-#define _VDAC_COMBDATA_CH1DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_COMBDATA */
-#define VDAC_COMBDATA_CH1DATA_DEFAULT (_VDAC_COMBDATA_CH1DATA_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_COMBDATA */
-
-/* Bit fields for VDAC CAL */
-#define _VDAC_CAL_RESETVALUE 0x00082004UL /**< Default value for VDAC_CAL */
-#define _VDAC_CAL_MASK 0x000F3F07UL /**< Mask for VDAC_CAL */
-#define _VDAC_CAL_OFFSETTRIM_SHIFT 0 /**< Shift value for VDAC_OFFSETTRIM */
-#define _VDAC_CAL_OFFSETTRIM_MASK 0x7UL /**< Bit mask for VDAC_OFFSETTRIM */
-#define _VDAC_CAL_OFFSETTRIM_DEFAULT 0x00000004UL /**< Mode DEFAULT for VDAC_CAL */
-#define VDAC_CAL_OFFSETTRIM_DEFAULT (_VDAC_CAL_OFFSETTRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CAL */
-#define _VDAC_CAL_GAINERRTRIM_SHIFT 8 /**< Shift value for VDAC_GAINERRTRIM */
-#define _VDAC_CAL_GAINERRTRIM_MASK 0x3F00UL /**< Bit mask for VDAC_GAINERRTRIM */
-#define _VDAC_CAL_GAINERRTRIM_DEFAULT 0x00000020UL /**< Mode DEFAULT for VDAC_CAL */
-#define VDAC_CAL_GAINERRTRIM_DEFAULT (_VDAC_CAL_GAINERRTRIM_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CAL */
-#define _VDAC_CAL_GAINERRTRIMCH1_SHIFT 16 /**< Shift value for VDAC_GAINERRTRIMCH1 */
-#define _VDAC_CAL_GAINERRTRIMCH1_MASK 0xF0000UL /**< Bit mask for VDAC_GAINERRTRIMCH1 */
-#define _VDAC_CAL_GAINERRTRIMCH1_DEFAULT 0x00000008UL /**< Mode DEFAULT for VDAC_CAL */
-#define VDAC_CAL_GAINERRTRIMCH1_DEFAULT (_VDAC_CAL_GAINERRTRIMCH1_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CAL */
-
-/* Bit fields for VDAC OPA_APORTREQ */
-#define _VDAC_OPA_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for VDAC_OPA_APORTREQ */
-#define _VDAC_OPA_APORTREQ_MASK 0x000003FCUL /**< Mask for VDAC_OPA_APORTREQ */
-#define VDAC_OPA_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 If the Bus Connected to APORT2X is Requested */
-#define _VDAC_OPA_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for VDAC_OPAAPORT1XREQ */
-#define _VDAC_OPA_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for VDAC_OPAAPORT1XREQ */
-#define _VDAC_OPA_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */
-#define VDAC_OPA_APORTREQ_APORT1XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */
-#define VDAC_OPA_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 If the Bus Connected to APORT1X is Requested */
-#define _VDAC_OPA_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for VDAC_OPAAPORT1YREQ */
-#define _VDAC_OPA_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for VDAC_OPAAPORT1YREQ */
-#define _VDAC_OPA_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */
-#define VDAC_OPA_APORTREQ_APORT1YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */
-#define VDAC_OPA_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is Requested */
-#define _VDAC_OPA_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for VDAC_OPAAPORT2XREQ */
-#define _VDAC_OPA_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for VDAC_OPAAPORT2XREQ */
-#define _VDAC_OPA_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */
-#define VDAC_OPA_APORTREQ_APORT2XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */
-#define VDAC_OPA_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is Requested */
-#define _VDAC_OPA_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for VDAC_OPAAPORT2YREQ */
-#define _VDAC_OPA_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for VDAC_OPAAPORT2YREQ */
-#define _VDAC_OPA_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */
-#define VDAC_OPA_APORTREQ_APORT2YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */
-#define VDAC_OPA_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is Requested */
-#define _VDAC_OPA_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for VDAC_OPAAPORT3XREQ */
-#define _VDAC_OPA_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for VDAC_OPAAPORT3XREQ */
-#define _VDAC_OPA_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */
-#define VDAC_OPA_APORTREQ_APORT3XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */
-#define VDAC_OPA_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is Requested */
-#define _VDAC_OPA_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for VDAC_OPAAPORT3YREQ */
-#define _VDAC_OPA_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for VDAC_OPAAPORT3YREQ */
-#define _VDAC_OPA_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */
-#define VDAC_OPA_APORTREQ_APORT3YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */
-#define VDAC_OPA_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is Requested */
-#define _VDAC_OPA_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for VDAC_OPAAPORT4XREQ */
-#define _VDAC_OPA_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for VDAC_OPAAPORT4XREQ */
-#define _VDAC_OPA_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */
-#define VDAC_OPA_APORTREQ_APORT4XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */
-#define VDAC_OPA_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is Requested */
-#define _VDAC_OPA_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for VDAC_OPAAPORT4YREQ */
-#define _VDAC_OPA_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for VDAC_OPAAPORT4YREQ */
-#define _VDAC_OPA_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */
-#define VDAC_OPA_APORTREQ_APORT4YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */
-
-/* Bit fields for VDAC OPA_APORTCONFLICT */
-#define _VDAC_OPA_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for VDAC_OPA_APORTCONFLICT */
-#define _VDAC_OPA_APORTCONFLICT_MASK 0x000003FCUL /**< Mask for VDAC_OPA_APORTCONFLICT */
-#define VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */
-#define _VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for VDAC_OPAAPORT1XCONFLICT */
-#define _VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for VDAC_OPAAPORT1XCONFLICT */
-#define _VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */
-#define VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */
-#define VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */
-#define _VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for VDAC_OPAAPORT1YCONFLICT */
-#define _VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for VDAC_OPAAPORT1YCONFLICT */
-#define _VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */
-#define VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */
-#define VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 If the Bus Connected to APORT2X is in Conflict With Another Peripheral */
-#define _VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for VDAC_OPAAPORT2XCONFLICT */
-#define _VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for VDAC_OPAAPORT2XCONFLICT */
-#define _VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */
-#define VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */
-#define VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 If the Bus Connected to APORT2Y is in Conflict With Another Peripheral */
-#define _VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for VDAC_OPAAPORT2YCONFLICT */
-#define _VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for VDAC_OPAAPORT2YCONFLICT */
-#define _VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */
-#define VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */
-#define VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 If the Bus Connected to APORT3X is in Conflict With Another Peripheral */
-#define _VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for VDAC_OPAAPORT3XCONFLICT */
-#define _VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for VDAC_OPAAPORT3XCONFLICT */
-#define _VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */
-#define VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */
-#define VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 If the Bus Connected to APORT3Y is in Conflict With Another Peripheral */
-#define _VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for VDAC_OPAAPORT3YCONFLICT */
-#define _VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for VDAC_OPAAPORT3YCONFLICT */
-#define _VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */
-#define VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */
-#define VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 If the Bus Connected to APORT4X is in Conflict With Another Peripheral */
-#define _VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for VDAC_OPAAPORT4XCONFLICT */
-#define _VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for VDAC_OPAAPORT4XCONFLICT */
-#define _VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */
-#define VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */
-#define VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 If the Bus Connected to APORT4Y is in Conflict With Another Peripheral */
-#define _VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for VDAC_OPAAPORT4YCONFLICT */
-#define _VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for VDAC_OPAAPORT4YCONFLICT */
-#define _VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */
-#define VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */
-
-/* Bit fields for VDAC OPA_CTRL */
-#define _VDAC_OPA_CTRL_RESETVALUE 0x0000000EUL /**< Default value for VDAC_OPA_CTRL */
-#define _VDAC_OPA_CTRL_MASK 0x00313F1FUL /**< Mask for VDAC_OPA_CTRL */
-#define _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT 0 /**< Shift value for VDAC_OPADRIVESTRENGTH */
-#define _VDAC_OPA_CTRL_DRIVESTRENGTH_MASK 0x3UL /**< Bit mask for VDAC_OPADRIVESTRENGTH */
-#define _VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT 0x00000002UL /**< Mode DEFAULT for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT (_VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_INCBW (0x1UL << 2) /**< OPAx Unity Gain Bandwidth Scale */
-#define _VDAC_OPA_CTRL_INCBW_SHIFT 2 /**< Shift value for VDAC_OPAINCBW */
-#define _VDAC_OPA_CTRL_INCBW_MASK 0x4UL /**< Bit mask for VDAC_OPAINCBW */
-#define _VDAC_OPA_CTRL_INCBW_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_INCBW_DEFAULT (_VDAC_OPA_CTRL_INCBW_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_HCMDIS (0x1UL << 3) /**< High Common Mode Disable */
-#define _VDAC_OPA_CTRL_HCMDIS_SHIFT 3 /**< Shift value for VDAC_OPAHCMDIS */
-#define _VDAC_OPA_CTRL_HCMDIS_MASK 0x8UL /**< Bit mask for VDAC_OPAHCMDIS */
-#define _VDAC_OPA_CTRL_HCMDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_HCMDIS_DEFAULT (_VDAC_OPA_CTRL_HCMDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_OUTSCALE (0x1UL << 4) /**< Scale OPAx Output Driving Strength */
-#define _VDAC_OPA_CTRL_OUTSCALE_SHIFT 4 /**< Shift value for VDAC_OPAOUTSCALE */
-#define _VDAC_OPA_CTRL_OUTSCALE_MASK 0x10UL /**< Bit mask for VDAC_OPAOUTSCALE */
-#define _VDAC_OPA_CTRL_OUTSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */
-#define _VDAC_OPA_CTRL_OUTSCALE_FULL 0x00000000UL /**< Mode FULL for VDAC_OPA_CTRL */
-#define _VDAC_OPA_CTRL_OUTSCALE_HALF 0x00000001UL /**< Mode HALF for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_OUTSCALE_DEFAULT (_VDAC_OPA_CTRL_OUTSCALE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_OUTSCALE_FULL (_VDAC_OPA_CTRL_OUTSCALE_FULL << 4) /**< Shifted mode FULL for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_OUTSCALE_HALF (_VDAC_OPA_CTRL_OUTSCALE_HALF << 4) /**< Shifted mode HALF for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_PRSEN (0x1UL << 8) /**< OPAx PRS Trigger Enable */
-#define _VDAC_OPA_CTRL_PRSEN_SHIFT 8 /**< Shift value for VDAC_OPAPRSEN */
-#define _VDAC_OPA_CTRL_PRSEN_MASK 0x100UL /**< Bit mask for VDAC_OPAPRSEN */
-#define _VDAC_OPA_CTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_PRSEN_DEFAULT (_VDAC_OPA_CTRL_PRSEN_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_PRSMODE (0x1UL << 9) /**< OPAx PRS Trigger Mode */
-#define _VDAC_OPA_CTRL_PRSMODE_SHIFT 9 /**< Shift value for VDAC_OPAPRSMODE */
-#define _VDAC_OPA_CTRL_PRSMODE_MASK 0x200UL /**< Bit mask for VDAC_OPAPRSMODE */
-#define _VDAC_OPA_CTRL_PRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */
-#define _VDAC_OPA_CTRL_PRSMODE_PULSED 0x00000000UL /**< Mode PULSED for VDAC_OPA_CTRL */
-#define _VDAC_OPA_CTRL_PRSMODE_TIMED 0x00000001UL /**< Mode TIMED for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_PRSMODE_DEFAULT (_VDAC_OPA_CTRL_PRSMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_PRSMODE_PULSED (_VDAC_OPA_CTRL_PRSMODE_PULSED << 9) /**< Shifted mode PULSED for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_PRSMODE_TIMED (_VDAC_OPA_CTRL_PRSMODE_TIMED << 9) /**< Shifted mode TIMED for VDAC_OPA_CTRL */
-#define _VDAC_OPA_CTRL_PRSSEL_SHIFT 10 /**< Shift value for VDAC_OPAPRSSEL */
-#define _VDAC_OPA_CTRL_PRSSEL_MASK 0x3C00UL /**< Bit mask for VDAC_OPAPRSSEL */
-#define _VDAC_OPA_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */
-#define _VDAC_OPA_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for VDAC_OPA_CTRL */
-#define _VDAC_OPA_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for VDAC_OPA_CTRL */
-#define _VDAC_OPA_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for VDAC_OPA_CTRL */
-#define _VDAC_OPA_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for VDAC_OPA_CTRL */
-#define _VDAC_OPA_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for VDAC_OPA_CTRL */
-#define _VDAC_OPA_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for VDAC_OPA_CTRL */
-#define _VDAC_OPA_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for VDAC_OPA_CTRL */
-#define _VDAC_OPA_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for VDAC_OPA_CTRL */
-#define _VDAC_OPA_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for VDAC_OPA_CTRL */
-#define _VDAC_OPA_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for VDAC_OPA_CTRL */
-#define _VDAC_OPA_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for VDAC_OPA_CTRL */
-#define _VDAC_OPA_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_PRSSEL_DEFAULT (_VDAC_OPA_CTRL_PRSSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_PRSSEL_PRSCH0 (_VDAC_OPA_CTRL_PRSSEL_PRSCH0 << 10) /**< Shifted mode PRSCH0 for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_PRSSEL_PRSCH1 (_VDAC_OPA_CTRL_PRSSEL_PRSCH1 << 10) /**< Shifted mode PRSCH1 for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_PRSSEL_PRSCH2 (_VDAC_OPA_CTRL_PRSSEL_PRSCH2 << 10) /**< Shifted mode PRSCH2 for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_PRSSEL_PRSCH3 (_VDAC_OPA_CTRL_PRSSEL_PRSCH3 << 10) /**< Shifted mode PRSCH3 for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_PRSSEL_PRSCH4 (_VDAC_OPA_CTRL_PRSSEL_PRSCH4 << 10) /**< Shifted mode PRSCH4 for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_PRSSEL_PRSCH5 (_VDAC_OPA_CTRL_PRSSEL_PRSCH5 << 10) /**< Shifted mode PRSCH5 for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_PRSSEL_PRSCH6 (_VDAC_OPA_CTRL_PRSSEL_PRSCH6 << 10) /**< Shifted mode PRSCH6 for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_PRSSEL_PRSCH7 (_VDAC_OPA_CTRL_PRSSEL_PRSCH7 << 10) /**< Shifted mode PRSCH7 for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_PRSSEL_PRSCH8 (_VDAC_OPA_CTRL_PRSSEL_PRSCH8 << 10) /**< Shifted mode PRSCH8 for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_PRSSEL_PRSCH9 (_VDAC_OPA_CTRL_PRSSEL_PRSCH9 << 10) /**< Shifted mode PRSCH9 for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_PRSSEL_PRSCH10 (_VDAC_OPA_CTRL_PRSSEL_PRSCH10 << 10) /**< Shifted mode PRSCH10 for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_PRSSEL_PRSCH11 (_VDAC_OPA_CTRL_PRSSEL_PRSCH11 << 10) /**< Shifted mode PRSCH11 for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_PRSOUTMODE (0x1UL << 16) /**< OPAx PRS Output Select */
-#define _VDAC_OPA_CTRL_PRSOUTMODE_SHIFT 16 /**< Shift value for VDAC_OPAPRSOUTMODE */
-#define _VDAC_OPA_CTRL_PRSOUTMODE_MASK 0x10000UL /**< Bit mask for VDAC_OPAPRSOUTMODE */
-#define _VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */
-#define _VDAC_OPA_CTRL_PRSOUTMODE_WARM 0x00000000UL /**< Mode WARM for VDAC_OPA_CTRL */
-#define _VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID 0x00000001UL /**< Mode OUTVALID for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT (_VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_PRSOUTMODE_WARM (_VDAC_OPA_CTRL_PRSOUTMODE_WARM << 16) /**< Shifted mode WARM for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID (_VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID << 16) /**< Shifted mode OUTVALID for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_APORTXMASTERDIS (0x1UL << 20) /**< APORT Bus Master Disable */
-#define _VDAC_OPA_CTRL_APORTXMASTERDIS_SHIFT 20 /**< Shift value for VDAC_OPAAPORTXMASTERDIS */
-#define _VDAC_OPA_CTRL_APORTXMASTERDIS_MASK 0x100000UL /**< Bit mask for VDAC_OPAAPORTXMASTERDIS */
-#define _VDAC_OPA_CTRL_APORTXMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_APORTXMASTERDIS_DEFAULT (_VDAC_OPA_CTRL_APORTXMASTERDIS_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_APORTYMASTERDIS (0x1UL << 21) /**< APORT Bus Master Disable */
-#define _VDAC_OPA_CTRL_APORTYMASTERDIS_SHIFT 21 /**< Shift value for VDAC_OPAAPORTYMASTERDIS */
-#define _VDAC_OPA_CTRL_APORTYMASTERDIS_MASK 0x200000UL /**< Bit mask for VDAC_OPAAPORTYMASTERDIS */
-#define _VDAC_OPA_CTRL_APORTYMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */
-#define VDAC_OPA_CTRL_APORTYMASTERDIS_DEFAULT (_VDAC_OPA_CTRL_APORTYMASTERDIS_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */
-
-/* Bit fields for VDAC OPA_TIMER */
-#define _VDAC_OPA_TIMER_RESETVALUE 0x00010700UL /**< Default value for VDAC_OPA_TIMER */
-#define _VDAC_OPA_TIMER_MASK 0x03FF7F3FUL /**< Mask for VDAC_OPA_TIMER */
-#define _VDAC_OPA_TIMER_STARTUPDLY_SHIFT 0 /**< Shift value for VDAC_OPASTARTUPDLY */
-#define _VDAC_OPA_TIMER_STARTUPDLY_MASK 0x3FUL /**< Bit mask for VDAC_OPASTARTUPDLY */
-#define _VDAC_OPA_TIMER_STARTUPDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_TIMER */
-#define VDAC_OPA_TIMER_STARTUPDLY_DEFAULT (_VDAC_OPA_TIMER_STARTUPDLY_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_TIMER */
-#define _VDAC_OPA_TIMER_WARMUPTIME_SHIFT 8 /**< Shift value for VDAC_OPAWARMUPTIME */
-#define _VDAC_OPA_TIMER_WARMUPTIME_MASK 0x7F00UL /**< Bit mask for VDAC_OPAWARMUPTIME */
-#define _VDAC_OPA_TIMER_WARMUPTIME_DEFAULT 0x00000007UL /**< Mode DEFAULT for VDAC_OPA_TIMER */
-#define VDAC_OPA_TIMER_WARMUPTIME_DEFAULT (_VDAC_OPA_TIMER_WARMUPTIME_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_TIMER */
-#define _VDAC_OPA_TIMER_SETTLETIME_SHIFT 16 /**< Shift value for VDAC_OPASETTLETIME */
-#define _VDAC_OPA_TIMER_SETTLETIME_MASK 0x3FF0000UL /**< Bit mask for VDAC_OPASETTLETIME */
-#define _VDAC_OPA_TIMER_SETTLETIME_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_TIMER */
-#define VDAC_OPA_TIMER_SETTLETIME_DEFAULT (_VDAC_OPA_TIMER_SETTLETIME_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_TIMER */
-
-/* Bit fields for VDAC OPA_MUX */
-#define _VDAC_OPA_MUX_RESETVALUE 0x0016F2F1UL /**< Default value for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_MASK 0x0717FFFFUL /**< Mask for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_SHIFT 0 /**< Shift value for VDAC_OPAPOSSEL */
-#define _VDAC_OPA_MUX_POSSEL_MASK 0xFFUL /**< Bit mask for VDAC_OPAPOSSEL */
-#define _VDAC_OPA_MUX_POSSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT1XCH2 0x00000021UL /**< Mode APORT1XCH2 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT1XCH4 0x00000022UL /**< Mode APORT1XCH4 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT1XCH6 0x00000023UL /**< Mode APORT1XCH6 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT1XCH8 0x00000024UL /**< Mode APORT1XCH8 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT1XCH10 0x00000025UL /**< Mode APORT1XCH10 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT1XCH12 0x00000026UL /**< Mode APORT1XCH12 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT1XCH14 0x00000027UL /**< Mode APORT1XCH14 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT1XCH16 0x00000028UL /**< Mode APORT1XCH16 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT1XCH18 0x00000029UL /**< Mode APORT1XCH18 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT1XCH20 0x0000002AUL /**< Mode APORT1XCH20 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT1XCH22 0x0000002BUL /**< Mode APORT1XCH22 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT1XCH24 0x0000002CUL /**< Mode APORT1XCH24 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT1XCH26 0x0000002DUL /**< Mode APORT1XCH26 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT1XCH28 0x0000002EUL /**< Mode APORT1XCH28 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT1XCH30 0x0000002FUL /**< Mode APORT1XCH30 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT2XCH1 0x00000040UL /**< Mode APORT2XCH1 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT2XCH3 0x00000041UL /**< Mode APORT2XCH3 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT2XCH5 0x00000042UL /**< Mode APORT2XCH5 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT2XCH7 0x00000043UL /**< Mode APORT2XCH7 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT2XCH9 0x00000044UL /**< Mode APORT2XCH9 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT2XCH11 0x00000045UL /**< Mode APORT2XCH11 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT2XCH13 0x00000046UL /**< Mode APORT2XCH13 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT2XCH15 0x00000047UL /**< Mode APORT2XCH15 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT2XCH17 0x00000048UL /**< Mode APORT2XCH17 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT2XCH19 0x00000049UL /**< Mode APORT2XCH19 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT2XCH21 0x0000004AUL /**< Mode APORT2XCH21 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT2XCH23 0x0000004BUL /**< Mode APORT2XCH23 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT2XCH25 0x0000004CUL /**< Mode APORT2XCH25 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT2XCH27 0x0000004DUL /**< Mode APORT2XCH27 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT2XCH29 0x0000004EUL /**< Mode APORT2XCH29 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT2XCH31 0x0000004FUL /**< Mode APORT2XCH31 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT3XCH2 0x00000061UL /**< Mode APORT3XCH2 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT3XCH4 0x00000062UL /**< Mode APORT3XCH4 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT3XCH6 0x00000063UL /**< Mode APORT3XCH6 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT3XCH8 0x00000064UL /**< Mode APORT3XCH8 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT3XCH10 0x00000065UL /**< Mode APORT3XCH10 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT3XCH12 0x00000066UL /**< Mode APORT3XCH12 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT3XCH14 0x00000067UL /**< Mode APORT3XCH14 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT3XCH16 0x00000068UL /**< Mode APORT3XCH16 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT3XCH18 0x00000069UL /**< Mode APORT3XCH18 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT3XCH20 0x0000006AUL /**< Mode APORT3XCH20 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT3XCH22 0x0000006BUL /**< Mode APORT3XCH22 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT3XCH24 0x0000006CUL /**< Mode APORT3XCH24 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT3XCH26 0x0000006DUL /**< Mode APORT3XCH26 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT3XCH28 0x0000006EUL /**< Mode APORT3XCH28 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT3XCH30 0x0000006FUL /**< Mode APORT3XCH30 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT4XCH1 0x00000080UL /**< Mode APORT4XCH1 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT4XCH3 0x00000081UL /**< Mode APORT4XCH3 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT4XCH5 0x00000082UL /**< Mode APORT4XCH5 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT4XCH7 0x00000083UL /**< Mode APORT4XCH7 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT4XCH9 0x00000084UL /**< Mode APORT4XCH9 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT4XCH11 0x00000085UL /**< Mode APORT4XCH11 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT4XCH13 0x00000086UL /**< Mode APORT4XCH13 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT4XCH15 0x00000087UL /**< Mode APORT4XCH15 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT4XCH17 0x00000088UL /**< Mode APORT4XCH17 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT4XCH19 0x00000089UL /**< Mode APORT4XCH19 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT4XCH21 0x0000008AUL /**< Mode APORT4XCH21 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT4XCH23 0x0000008BUL /**< Mode APORT4XCH23 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT4XCH25 0x0000008CUL /**< Mode APORT4XCH25 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT4XCH27 0x0000008DUL /**< Mode APORT4XCH27 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT4XCH29 0x0000008EUL /**< Mode APORT4XCH29 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_APORT4XCH31 0x0000008FUL /**< Mode APORT4XCH31 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_DISABLE 0x000000F0UL /**< Mode DISABLE for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_DEFAULT 0x000000F1UL /**< Mode DEFAULT for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_DAC 0x000000F1UL /**< Mode DAC for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_POSPAD 0x000000F2UL /**< Mode POSPAD for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_OPANEXT 0x000000F3UL /**< Mode OPANEXT for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_POSSEL_OPATAP 0x000000F4UL /**< Mode OPATAP for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT1XCH0 (_VDAC_OPA_MUX_POSSEL_APORT1XCH0 << 0) /**< Shifted mode APORT1XCH0 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT1XCH2 (_VDAC_OPA_MUX_POSSEL_APORT1XCH2 << 0) /**< Shifted mode APORT1XCH2 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT1XCH4 (_VDAC_OPA_MUX_POSSEL_APORT1XCH4 << 0) /**< Shifted mode APORT1XCH4 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT1XCH6 (_VDAC_OPA_MUX_POSSEL_APORT1XCH6 << 0) /**< Shifted mode APORT1XCH6 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT1XCH8 (_VDAC_OPA_MUX_POSSEL_APORT1XCH8 << 0) /**< Shifted mode APORT1XCH8 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT1XCH10 (_VDAC_OPA_MUX_POSSEL_APORT1XCH10 << 0) /**< Shifted mode APORT1XCH10 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT1XCH12 (_VDAC_OPA_MUX_POSSEL_APORT1XCH12 << 0) /**< Shifted mode APORT1XCH12 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT1XCH14 (_VDAC_OPA_MUX_POSSEL_APORT1XCH14 << 0) /**< Shifted mode APORT1XCH14 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT1XCH16 (_VDAC_OPA_MUX_POSSEL_APORT1XCH16 << 0) /**< Shifted mode APORT1XCH16 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT1XCH18 (_VDAC_OPA_MUX_POSSEL_APORT1XCH18 << 0) /**< Shifted mode APORT1XCH18 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT1XCH20 (_VDAC_OPA_MUX_POSSEL_APORT1XCH20 << 0) /**< Shifted mode APORT1XCH20 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT1XCH22 (_VDAC_OPA_MUX_POSSEL_APORT1XCH22 << 0) /**< Shifted mode APORT1XCH22 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT1XCH24 (_VDAC_OPA_MUX_POSSEL_APORT1XCH24 << 0) /**< Shifted mode APORT1XCH24 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT1XCH26 (_VDAC_OPA_MUX_POSSEL_APORT1XCH26 << 0) /**< Shifted mode APORT1XCH26 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT1XCH28 (_VDAC_OPA_MUX_POSSEL_APORT1XCH28 << 0) /**< Shifted mode APORT1XCH28 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT1XCH30 (_VDAC_OPA_MUX_POSSEL_APORT1XCH30 << 0) /**< Shifted mode APORT1XCH30 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT2XCH1 (_VDAC_OPA_MUX_POSSEL_APORT2XCH1 << 0) /**< Shifted mode APORT2XCH1 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT2XCH3 (_VDAC_OPA_MUX_POSSEL_APORT2XCH3 << 0) /**< Shifted mode APORT2XCH3 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT2XCH5 (_VDAC_OPA_MUX_POSSEL_APORT2XCH5 << 0) /**< Shifted mode APORT2XCH5 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT2XCH7 (_VDAC_OPA_MUX_POSSEL_APORT2XCH7 << 0) /**< Shifted mode APORT2XCH7 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT2XCH9 (_VDAC_OPA_MUX_POSSEL_APORT2XCH9 << 0) /**< Shifted mode APORT2XCH9 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT2XCH11 (_VDAC_OPA_MUX_POSSEL_APORT2XCH11 << 0) /**< Shifted mode APORT2XCH11 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT2XCH13 (_VDAC_OPA_MUX_POSSEL_APORT2XCH13 << 0) /**< Shifted mode APORT2XCH13 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT2XCH15 (_VDAC_OPA_MUX_POSSEL_APORT2XCH15 << 0) /**< Shifted mode APORT2XCH15 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT2XCH17 (_VDAC_OPA_MUX_POSSEL_APORT2XCH17 << 0) /**< Shifted mode APORT2XCH17 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT2XCH19 (_VDAC_OPA_MUX_POSSEL_APORT2XCH19 << 0) /**< Shifted mode APORT2XCH19 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT2XCH21 (_VDAC_OPA_MUX_POSSEL_APORT2XCH21 << 0) /**< Shifted mode APORT2XCH21 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT2XCH23 (_VDAC_OPA_MUX_POSSEL_APORT2XCH23 << 0) /**< Shifted mode APORT2XCH23 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT2XCH25 (_VDAC_OPA_MUX_POSSEL_APORT2XCH25 << 0) /**< Shifted mode APORT2XCH25 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT2XCH27 (_VDAC_OPA_MUX_POSSEL_APORT2XCH27 << 0) /**< Shifted mode APORT2XCH27 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT2XCH29 (_VDAC_OPA_MUX_POSSEL_APORT2XCH29 << 0) /**< Shifted mode APORT2XCH29 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT2XCH31 (_VDAC_OPA_MUX_POSSEL_APORT2XCH31 << 0) /**< Shifted mode APORT2XCH31 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT3XCH0 (_VDAC_OPA_MUX_POSSEL_APORT3XCH0 << 0) /**< Shifted mode APORT3XCH0 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT3XCH2 (_VDAC_OPA_MUX_POSSEL_APORT3XCH2 << 0) /**< Shifted mode APORT3XCH2 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT3XCH4 (_VDAC_OPA_MUX_POSSEL_APORT3XCH4 << 0) /**< Shifted mode APORT3XCH4 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT3XCH6 (_VDAC_OPA_MUX_POSSEL_APORT3XCH6 << 0) /**< Shifted mode APORT3XCH6 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT3XCH8 (_VDAC_OPA_MUX_POSSEL_APORT3XCH8 << 0) /**< Shifted mode APORT3XCH8 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT3XCH10 (_VDAC_OPA_MUX_POSSEL_APORT3XCH10 << 0) /**< Shifted mode APORT3XCH10 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT3XCH12 (_VDAC_OPA_MUX_POSSEL_APORT3XCH12 << 0) /**< Shifted mode APORT3XCH12 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT3XCH14 (_VDAC_OPA_MUX_POSSEL_APORT3XCH14 << 0) /**< Shifted mode APORT3XCH14 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT3XCH16 (_VDAC_OPA_MUX_POSSEL_APORT3XCH16 << 0) /**< Shifted mode APORT3XCH16 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT3XCH18 (_VDAC_OPA_MUX_POSSEL_APORT3XCH18 << 0) /**< Shifted mode APORT3XCH18 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT3XCH20 (_VDAC_OPA_MUX_POSSEL_APORT3XCH20 << 0) /**< Shifted mode APORT3XCH20 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT3XCH22 (_VDAC_OPA_MUX_POSSEL_APORT3XCH22 << 0) /**< Shifted mode APORT3XCH22 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT3XCH24 (_VDAC_OPA_MUX_POSSEL_APORT3XCH24 << 0) /**< Shifted mode APORT3XCH24 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT3XCH26 (_VDAC_OPA_MUX_POSSEL_APORT3XCH26 << 0) /**< Shifted mode APORT3XCH26 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT3XCH28 (_VDAC_OPA_MUX_POSSEL_APORT3XCH28 << 0) /**< Shifted mode APORT3XCH28 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT3XCH30 (_VDAC_OPA_MUX_POSSEL_APORT3XCH30 << 0) /**< Shifted mode APORT3XCH30 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT4XCH1 (_VDAC_OPA_MUX_POSSEL_APORT4XCH1 << 0) /**< Shifted mode APORT4XCH1 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT4XCH3 (_VDAC_OPA_MUX_POSSEL_APORT4XCH3 << 0) /**< Shifted mode APORT4XCH3 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT4XCH5 (_VDAC_OPA_MUX_POSSEL_APORT4XCH5 << 0) /**< Shifted mode APORT4XCH5 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT4XCH7 (_VDAC_OPA_MUX_POSSEL_APORT4XCH7 << 0) /**< Shifted mode APORT4XCH7 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT4XCH9 (_VDAC_OPA_MUX_POSSEL_APORT4XCH9 << 0) /**< Shifted mode APORT4XCH9 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT4XCH11 (_VDAC_OPA_MUX_POSSEL_APORT4XCH11 << 0) /**< Shifted mode APORT4XCH11 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT4XCH13 (_VDAC_OPA_MUX_POSSEL_APORT4XCH13 << 0) /**< Shifted mode APORT4XCH13 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT4XCH15 (_VDAC_OPA_MUX_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT4XCH17 (_VDAC_OPA_MUX_POSSEL_APORT4XCH17 << 0) /**< Shifted mode APORT4XCH17 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT4XCH19 (_VDAC_OPA_MUX_POSSEL_APORT4XCH19 << 0) /**< Shifted mode APORT4XCH19 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT4XCH21 (_VDAC_OPA_MUX_POSSEL_APORT4XCH21 << 0) /**< Shifted mode APORT4XCH21 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT4XCH23 (_VDAC_OPA_MUX_POSSEL_APORT4XCH23 << 0) /**< Shifted mode APORT4XCH23 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT4XCH25 (_VDAC_OPA_MUX_POSSEL_APORT4XCH25 << 0) /**< Shifted mode APORT4XCH25 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT4XCH27 (_VDAC_OPA_MUX_POSSEL_APORT4XCH27 << 0) /**< Shifted mode APORT4XCH27 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT4XCH29 (_VDAC_OPA_MUX_POSSEL_APORT4XCH29 << 0) /**< Shifted mode APORT4XCH29 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_APORT4XCH31 (_VDAC_OPA_MUX_POSSEL_APORT4XCH31 << 0) /**< Shifted mode APORT4XCH31 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_DISABLE (_VDAC_OPA_MUX_POSSEL_DISABLE << 0) /**< Shifted mode DISABLE for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_DEFAULT (_VDAC_OPA_MUX_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_DAC (_VDAC_OPA_MUX_POSSEL_DAC << 0) /**< Shifted mode DAC for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_POSPAD (_VDAC_OPA_MUX_POSSEL_POSPAD << 0) /**< Shifted mode POSPAD for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_OPANEXT (_VDAC_OPA_MUX_POSSEL_OPANEXT << 0) /**< Shifted mode OPANEXT for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_POSSEL_OPATAP (_VDAC_OPA_MUX_POSSEL_OPATAP << 0) /**< Shifted mode OPATAP for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_SHIFT 8 /**< Shift value for VDAC_OPANEGSEL */
-#define _VDAC_OPA_MUX_NEGSEL_MASK 0xFF00UL /**< Bit mask for VDAC_OPANEGSEL */
-#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH1 0x00000030UL /**< Mode APORT1YCH1 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH3 0x00000031UL /**< Mode APORT1YCH3 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH5 0x00000032UL /**< Mode APORT1YCH5 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH7 0x00000033UL /**< Mode APORT1YCH7 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH9 0x00000034UL /**< Mode APORT1YCH9 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH11 0x00000035UL /**< Mode APORT1YCH11 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH13 0x00000036UL /**< Mode APORT1YCH13 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH15 0x00000037UL /**< Mode APORT1YCH15 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH17 0x00000038UL /**< Mode APORT1YCH17 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH19 0x00000039UL /**< Mode APORT1YCH19 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH21 0x0000003AUL /**< Mode APORT1YCH21 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH23 0x0000003BUL /**< Mode APORT1YCH23 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH25 0x0000003CUL /**< Mode APORT1YCH25 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH27 0x0000003DUL /**< Mode APORT1YCH27 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH29 0x0000003EUL /**< Mode APORT1YCH29 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH0 0x00000050UL /**< Mode APORT2YCH0 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH2 0x00000051UL /**< Mode APORT2YCH2 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH4 0x00000052UL /**< Mode APORT2YCH4 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH6 0x00000053UL /**< Mode APORT2YCH6 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH8 0x00000054UL /**< Mode APORT2YCH8 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH10 0x00000055UL /**< Mode APORT2YCH10 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH12 0x00000056UL /**< Mode APORT2YCH12 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH14 0x00000057UL /**< Mode APORT2YCH14 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH16 0x00000058UL /**< Mode APORT2YCH16 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH18 0x00000059UL /**< Mode APORT2YCH18 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH20 0x0000005AUL /**< Mode APORT2YCH20 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH22 0x0000005BUL /**< Mode APORT2YCH22 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH24 0x0000005CUL /**< Mode APORT2YCH24 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH26 0x0000005DUL /**< Mode APORT2YCH26 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH28 0x0000005EUL /**< Mode APORT2YCH28 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH30 0x0000005FUL /**< Mode APORT2YCH30 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH1 0x00000070UL /**< Mode APORT3YCH1 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH3 0x00000071UL /**< Mode APORT3YCH3 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH5 0x00000072UL /**< Mode APORT3YCH5 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH7 0x00000073UL /**< Mode APORT3YCH7 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH9 0x00000074UL /**< Mode APORT3YCH9 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH11 0x00000075UL /**< Mode APORT3YCH11 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH13 0x00000076UL /**< Mode APORT3YCH13 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH15 0x00000077UL /**< Mode APORT3YCH15 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH17 0x00000078UL /**< Mode APORT3YCH17 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH19 0x00000079UL /**< Mode APORT3YCH19 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH21 0x0000007AUL /**< Mode APORT3YCH21 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH23 0x0000007BUL /**< Mode APORT3YCH23 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH25 0x0000007CUL /**< Mode APORT3YCH25 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH27 0x0000007DUL /**< Mode APORT3YCH27 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH29 0x0000007EUL /**< Mode APORT3YCH29 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH0 0x00000090UL /**< Mode APORT4YCH0 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH2 0x00000091UL /**< Mode APORT4YCH2 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH4 0x00000092UL /**< Mode APORT4YCH4 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH6 0x00000093UL /**< Mode APORT4YCH6 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH8 0x00000094UL /**< Mode APORT4YCH8 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH10 0x00000095UL /**< Mode APORT4YCH10 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH12 0x00000096UL /**< Mode APORT4YCH12 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH14 0x00000097UL /**< Mode APORT4YCH14 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH16 0x00000098UL /**< Mode APORT4YCH16 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH18 0x00000099UL /**< Mode APORT4YCH18 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH20 0x0000009AUL /**< Mode APORT4YCH20 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH22 0x0000009BUL /**< Mode APORT4YCH22 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH24 0x0000009CUL /**< Mode APORT4YCH24 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH26 0x0000009DUL /**< Mode APORT4YCH26 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH28 0x0000009EUL /**< Mode APORT4YCH28 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH30 0x0000009FUL /**< Mode APORT4YCH30 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_DISABLE 0x000000F0UL /**< Mode DISABLE for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_UG 0x000000F1UL /**< Mode UG for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_DEFAULT 0x000000F2UL /**< Mode DEFAULT for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_OPATAP 0x000000F2UL /**< Mode OPATAP for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_NEGSEL_NEGPAD 0x000000F3UL /**< Mode NEGPAD for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT1YCH1 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH1 << 8) /**< Shifted mode APORT1YCH1 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT1YCH3 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH3 << 8) /**< Shifted mode APORT1YCH3 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT1YCH5 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH5 << 8) /**< Shifted mode APORT1YCH5 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT1YCH7 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH7 << 8) /**< Shifted mode APORT1YCH7 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT1YCH9 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH9 << 8) /**< Shifted mode APORT1YCH9 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT1YCH11 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH11 << 8) /**< Shifted mode APORT1YCH11 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT1YCH13 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH13 << 8) /**< Shifted mode APORT1YCH13 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT1YCH15 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH15 << 8) /**< Shifted mode APORT1YCH15 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT1YCH17 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH17 << 8) /**< Shifted mode APORT1YCH17 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT1YCH19 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH19 << 8) /**< Shifted mode APORT1YCH19 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT1YCH21 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH21 << 8) /**< Shifted mode APORT1YCH21 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT1YCH23 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH23 << 8) /**< Shifted mode APORT1YCH23 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT1YCH25 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH25 << 8) /**< Shifted mode APORT1YCH25 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT1YCH27 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH27 << 8) /**< Shifted mode APORT1YCH27 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT1YCH29 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH29 << 8) /**< Shifted mode APORT1YCH29 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT1YCH31 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH31 << 8) /**< Shifted mode APORT1YCH31 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT2YCH0 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH0 << 8) /**< Shifted mode APORT2YCH0 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT2YCH2 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH2 << 8) /**< Shifted mode APORT2YCH2 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT2YCH4 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH4 << 8) /**< Shifted mode APORT2YCH4 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT2YCH6 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH6 << 8) /**< Shifted mode APORT2YCH6 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT2YCH8 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH8 << 8) /**< Shifted mode APORT2YCH8 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT2YCH10 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH10 << 8) /**< Shifted mode APORT2YCH10 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT2YCH12 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH12 << 8) /**< Shifted mode APORT2YCH12 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT2YCH14 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH14 << 8) /**< Shifted mode APORT2YCH14 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT2YCH16 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH16 << 8) /**< Shifted mode APORT2YCH16 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT2YCH18 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH18 << 8) /**< Shifted mode APORT2YCH18 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT2YCH20 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH20 << 8) /**< Shifted mode APORT2YCH20 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT2YCH22 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH22 << 8) /**< Shifted mode APORT2YCH22 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT2YCH24 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH24 << 8) /**< Shifted mode APORT2YCH24 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT2YCH26 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH26 << 8) /**< Shifted mode APORT2YCH26 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT2YCH28 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH28 << 8) /**< Shifted mode APORT2YCH28 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT2YCH30 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH30 << 8) /**< Shifted mode APORT2YCH30 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT3YCH1 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH1 << 8) /**< Shifted mode APORT3YCH1 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT3YCH3 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH3 << 8) /**< Shifted mode APORT3YCH3 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT3YCH5 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH5 << 8) /**< Shifted mode APORT3YCH5 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT3YCH7 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH7 << 8) /**< Shifted mode APORT3YCH7 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT3YCH9 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH9 << 8) /**< Shifted mode APORT3YCH9 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT3YCH11 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH11 << 8) /**< Shifted mode APORT3YCH11 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT3YCH13 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH13 << 8) /**< Shifted mode APORT3YCH13 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT3YCH15 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH15 << 8) /**< Shifted mode APORT3YCH15 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT3YCH17 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH17 << 8) /**< Shifted mode APORT3YCH17 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT3YCH19 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH19 << 8) /**< Shifted mode APORT3YCH19 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT3YCH21 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH21 << 8) /**< Shifted mode APORT3YCH21 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT3YCH23 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH23 << 8) /**< Shifted mode APORT3YCH23 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT3YCH25 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH25 << 8) /**< Shifted mode APORT3YCH25 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT3YCH27 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH27 << 8) /**< Shifted mode APORT3YCH27 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT3YCH29 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH29 << 8) /**< Shifted mode APORT3YCH29 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT3YCH31 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH31 << 8) /**< Shifted mode APORT3YCH31 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT4YCH0 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH0 << 8) /**< Shifted mode APORT4YCH0 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT4YCH2 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH2 << 8) /**< Shifted mode APORT4YCH2 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT4YCH4 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH4 << 8) /**< Shifted mode APORT4YCH4 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT4YCH6 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH6 << 8) /**< Shifted mode APORT4YCH6 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT4YCH8 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH8 << 8) /**< Shifted mode APORT4YCH8 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT4YCH10 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH10 << 8) /**< Shifted mode APORT4YCH10 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT4YCH12 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT4YCH14 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT4YCH16 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT4YCH18 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT4YCH20 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH20 << 8) /**< Shifted mode APORT4YCH20 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT4YCH22 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH22 << 8) /**< Shifted mode APORT4YCH22 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT4YCH24 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH24 << 8) /**< Shifted mode APORT4YCH24 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT4YCH26 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH26 << 8) /**< Shifted mode APORT4YCH26 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT4YCH28 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_APORT4YCH30 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_DISABLE (_VDAC_OPA_MUX_NEGSEL_DISABLE << 8) /**< Shifted mode DISABLE for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_UG (_VDAC_OPA_MUX_NEGSEL_UG << 8) /**< Shifted mode UG for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_DEFAULT (_VDAC_OPA_MUX_NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_OPATAP (_VDAC_OPA_MUX_NEGSEL_OPATAP << 8) /**< Shifted mode OPATAP for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_NEGSEL_NEGPAD (_VDAC_OPA_MUX_NEGSEL_NEGPAD << 8) /**< Shifted mode NEGPAD for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_RESINMUX_SHIFT 16 /**< Shift value for VDAC_OPARESINMUX */
-#define _VDAC_OPA_MUX_RESINMUX_MASK 0x70000UL /**< Bit mask for VDAC_OPARESINMUX */
-#define _VDAC_OPA_MUX_RESINMUX_DISABLE 0x00000000UL /**< Mode DISABLE for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_RESINMUX_OPANEXT 0x00000001UL /**< Mode OPANEXT for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_RESINMUX_NEGPAD 0x00000002UL /**< Mode NEGPAD for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_RESINMUX_POSPAD 0x00000003UL /**< Mode POSPAD for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_RESINMUX_COMPAD 0x00000004UL /**< Mode COMPAD for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_RESINMUX_CENTER 0x00000005UL /**< Mode CENTER for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_RESINMUX_DEFAULT 0x00000006UL /**< Mode DEFAULT for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_RESINMUX_VSS 0x00000006UL /**< Mode VSS for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_RESINMUX_DISABLE (_VDAC_OPA_MUX_RESINMUX_DISABLE << 16) /**< Shifted mode DISABLE for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_RESINMUX_OPANEXT (_VDAC_OPA_MUX_RESINMUX_OPANEXT << 16) /**< Shifted mode OPANEXT for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_RESINMUX_NEGPAD (_VDAC_OPA_MUX_RESINMUX_NEGPAD << 16) /**< Shifted mode NEGPAD for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_RESINMUX_POSPAD (_VDAC_OPA_MUX_RESINMUX_POSPAD << 16) /**< Shifted mode POSPAD for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_RESINMUX_COMPAD (_VDAC_OPA_MUX_RESINMUX_COMPAD << 16) /**< Shifted mode COMPAD for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_RESINMUX_CENTER (_VDAC_OPA_MUX_RESINMUX_CENTER << 16) /**< Shifted mode CENTER for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_RESINMUX_DEFAULT (_VDAC_OPA_MUX_RESINMUX_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_RESINMUX_VSS (_VDAC_OPA_MUX_RESINMUX_VSS << 16) /**< Shifted mode VSS for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_GAIN3X (0x1UL << 20) /**< OPAx Dedicated 3x Gain Resistor Ladder */
-#define _VDAC_OPA_MUX_GAIN3X_SHIFT 20 /**< Shift value for VDAC_OPAGAIN3X */
-#define _VDAC_OPA_MUX_GAIN3X_MASK 0x100000UL /**< Bit mask for VDAC_OPAGAIN3X */
-#define _VDAC_OPA_MUX_GAIN3X_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_GAIN3X_DEFAULT (_VDAC_OPA_MUX_GAIN3X_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_RESSEL_SHIFT 24 /**< Shift value for VDAC_OPARESSEL */
-#define _VDAC_OPA_MUX_RESSEL_MASK 0x7000000UL /**< Bit mask for VDAC_OPARESSEL */
-#define _VDAC_OPA_MUX_RESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_RESSEL_RES0 0x00000000UL /**< Mode RES0 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_RESSEL_RES1 0x00000001UL /**< Mode RES1 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_RESSEL_RES2 0x00000002UL /**< Mode RES2 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_RESSEL_RES3 0x00000003UL /**< Mode RES3 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_RESSEL_RES4 0x00000004UL /**< Mode RES4 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_RESSEL_RES5 0x00000005UL /**< Mode RES5 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_RESSEL_RES6 0x00000006UL /**< Mode RES6 for VDAC_OPA_MUX */
-#define _VDAC_OPA_MUX_RESSEL_RES7 0x00000007UL /**< Mode RES7 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_RESSEL_DEFAULT (_VDAC_OPA_MUX_RESSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_RESSEL_RES0 (_VDAC_OPA_MUX_RESSEL_RES0 << 24) /**< Shifted mode RES0 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_RESSEL_RES1 (_VDAC_OPA_MUX_RESSEL_RES1 << 24) /**< Shifted mode RES1 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_RESSEL_RES2 (_VDAC_OPA_MUX_RESSEL_RES2 << 24) /**< Shifted mode RES2 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_RESSEL_RES3 (_VDAC_OPA_MUX_RESSEL_RES3 << 24) /**< Shifted mode RES3 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_RESSEL_RES4 (_VDAC_OPA_MUX_RESSEL_RES4 << 24) /**< Shifted mode RES4 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_RESSEL_RES5 (_VDAC_OPA_MUX_RESSEL_RES5 << 24) /**< Shifted mode RES5 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_RESSEL_RES6 (_VDAC_OPA_MUX_RESSEL_RES6 << 24) /**< Shifted mode RES6 for VDAC_OPA_MUX */
-#define VDAC_OPA_MUX_RESSEL_RES7 (_VDAC_OPA_MUX_RESSEL_RES7 << 24) /**< Shifted mode RES7 for VDAC_OPA_MUX */
-
-/* Bit fields for VDAC OPA_OUT */
-#define _VDAC_OPA_OUT_RESETVALUE 0x00000001UL /**< Default value for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_MASK 0x00FF01FFUL /**< Mask for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_MAINOUTEN (0x1UL << 0) /**< OPAx Main Output Enable */
-#define _VDAC_OPA_OUT_MAINOUTEN_SHIFT 0 /**< Shift value for VDAC_OPAMAINOUTEN */
-#define _VDAC_OPA_OUT_MAINOUTEN_MASK 0x1UL /**< Bit mask for VDAC_OPAMAINOUTEN */
-#define _VDAC_OPA_OUT_MAINOUTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_MAINOUTEN_DEFAULT (_VDAC_OPA_OUT_MAINOUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_ALTOUTEN (0x1UL << 1) /**< OPAx Alternative Output Enable */
-#define _VDAC_OPA_OUT_ALTOUTEN_SHIFT 1 /**< Shift value for VDAC_OPAALTOUTEN */
-#define _VDAC_OPA_OUT_ALTOUTEN_MASK 0x2UL /**< Bit mask for VDAC_OPAALTOUTEN */
-#define _VDAC_OPA_OUT_ALTOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_ALTOUTEN_DEFAULT (_VDAC_OPA_OUT_ALTOUTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTEN (0x1UL << 2) /**< OPAx Aport Output Enable */
-#define _VDAC_OPA_OUT_APORTOUTEN_SHIFT 2 /**< Shift value for VDAC_OPAAPORTOUTEN */
-#define _VDAC_OPA_OUT_APORTOUTEN_MASK 0x4UL /**< Bit mask for VDAC_OPAAPORTOUTEN */
-#define _VDAC_OPA_OUT_APORTOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTEN_DEFAULT (_VDAC_OPA_OUT_APORTOUTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_SHORT (0x1UL << 3) /**< OPAx Main and Alternative Output Short */
-#define _VDAC_OPA_OUT_SHORT_SHIFT 3 /**< Shift value for VDAC_OPASHORT */
-#define _VDAC_OPA_OUT_SHORT_MASK 0x8UL /**< Bit mask for VDAC_OPASHORT */
-#define _VDAC_OPA_OUT_SHORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_SHORT_DEFAULT (_VDAC_OPA_OUT_SHORT_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_ALTOUTPADEN_SHIFT 4 /**< Shift value for VDAC_OPAALTOUTPADEN */
-#define _VDAC_OPA_OUT_ALTOUTPADEN_MASK 0x1F0UL /**< Bit mask for VDAC_OPAALTOUTPADEN */
-#define _VDAC_OPA_OUT_ALTOUTPADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_ALTOUTPADEN_OUT0 0x00000001UL /**< Mode OUT0 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_ALTOUTPADEN_OUT1 0x00000002UL /**< Mode OUT1 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_ALTOUTPADEN_OUT2 0x00000004UL /**< Mode OUT2 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_ALTOUTPADEN_OUT3 0x00000008UL /**< Mode OUT3 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_ALTOUTPADEN_OUT4 0x00000010UL /**< Mode OUT4 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_ALTOUTPADEN_DEFAULT (_VDAC_OPA_OUT_ALTOUTPADEN_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_ALTOUTPADEN_OUT0 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT0 << 4) /**< Shifted mode OUT0 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_ALTOUTPADEN_OUT1 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT1 << 4) /**< Shifted mode OUT1 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_ALTOUTPADEN_OUT2 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT2 << 4) /**< Shifted mode OUT2 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_ALTOUTPADEN_OUT3 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT3 << 4) /**< Shifted mode OUT3 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_ALTOUTPADEN_OUT4 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT4 << 4) /**< Shifted mode OUT4 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_SHIFT 16 /**< Shift value for VDAC_OPAAPORTOUTSEL */
-#define _VDAC_OPA_OUT_APORTOUTSEL_MASK 0xFF0000UL /**< Bit mask for VDAC_OPAAPORTOUTSEL */
-#define _VDAC_OPA_OUT_APORTOUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1 0x00000030UL /**< Mode APORT1YCH1 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3 0x00000031UL /**< Mode APORT1YCH3 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5 0x00000032UL /**< Mode APORT1YCH5 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7 0x00000033UL /**< Mode APORT1YCH7 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9 0x00000034UL /**< Mode APORT1YCH9 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11 0x00000035UL /**< Mode APORT1YCH11 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13 0x00000036UL /**< Mode APORT1YCH13 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15 0x00000037UL /**< Mode APORT1YCH15 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17 0x00000038UL /**< Mode APORT1YCH17 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19 0x00000039UL /**< Mode APORT1YCH19 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21 0x0000003AUL /**< Mode APORT1YCH21 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23 0x0000003BUL /**< Mode APORT1YCH23 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25 0x0000003CUL /**< Mode APORT1YCH25 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27 0x0000003DUL /**< Mode APORT1YCH27 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29 0x0000003EUL /**< Mode APORT1YCH29 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0 0x00000050UL /**< Mode APORT2YCH0 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2 0x00000051UL /**< Mode APORT2YCH2 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4 0x00000052UL /**< Mode APORT2YCH4 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6 0x00000053UL /**< Mode APORT2YCH6 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8 0x00000054UL /**< Mode APORT2YCH8 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10 0x00000055UL /**< Mode APORT2YCH10 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12 0x00000056UL /**< Mode APORT2YCH12 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14 0x00000057UL /**< Mode APORT2YCH14 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16 0x00000058UL /**< Mode APORT2YCH16 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18 0x00000059UL /**< Mode APORT2YCH18 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20 0x0000005AUL /**< Mode APORT2YCH20 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22 0x0000005BUL /**< Mode APORT2YCH22 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24 0x0000005CUL /**< Mode APORT2YCH24 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26 0x0000005DUL /**< Mode APORT2YCH26 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28 0x0000005EUL /**< Mode APORT2YCH28 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30 0x0000005FUL /**< Mode APORT2YCH30 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1 0x00000070UL /**< Mode APORT3YCH1 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3 0x00000071UL /**< Mode APORT3YCH3 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5 0x00000072UL /**< Mode APORT3YCH5 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7 0x00000073UL /**< Mode APORT3YCH7 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9 0x00000074UL /**< Mode APORT3YCH9 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11 0x00000075UL /**< Mode APORT3YCH11 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13 0x00000076UL /**< Mode APORT3YCH13 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15 0x00000077UL /**< Mode APORT3YCH15 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17 0x00000078UL /**< Mode APORT3YCH17 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19 0x00000079UL /**< Mode APORT3YCH19 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21 0x0000007AUL /**< Mode APORT3YCH21 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23 0x0000007BUL /**< Mode APORT3YCH23 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25 0x0000007CUL /**< Mode APORT3YCH25 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27 0x0000007DUL /**< Mode APORT3YCH27 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29 0x0000007EUL /**< Mode APORT3YCH29 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0 0x00000090UL /**< Mode APORT4YCH0 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2 0x00000091UL /**< Mode APORT4YCH2 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4 0x00000092UL /**< Mode APORT4YCH4 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6 0x00000093UL /**< Mode APORT4YCH6 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8 0x00000094UL /**< Mode APORT4YCH8 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10 0x00000095UL /**< Mode APORT4YCH10 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12 0x00000096UL /**< Mode APORT4YCH12 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14 0x00000097UL /**< Mode APORT4YCH14 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16 0x00000098UL /**< Mode APORT4YCH16 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18 0x00000099UL /**< Mode APORT4YCH18 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20 0x0000009AUL /**< Mode APORT4YCH20 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22 0x0000009BUL /**< Mode APORT4YCH22 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24 0x0000009CUL /**< Mode APORT4YCH24 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26 0x0000009DUL /**< Mode APORT4YCH26 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28 0x0000009EUL /**< Mode APORT4YCH28 for VDAC_OPA_OUT */
-#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30 0x0000009FUL /**< Mode APORT4YCH30 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_DEFAULT (_VDAC_OPA_OUT_APORTOUTSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1 << 16) /**< Shifted mode APORT1YCH1 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3 << 16) /**< Shifted mode APORT1YCH3 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5 << 16) /**< Shifted mode APORT1YCH5 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7 << 16) /**< Shifted mode APORT1YCH7 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9 << 16) /**< Shifted mode APORT1YCH9 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11 << 16) /**< Shifted mode APORT1YCH11 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13 << 16) /**< Shifted mode APORT1YCH13 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15 << 16) /**< Shifted mode APORT1YCH15 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17 << 16) /**< Shifted mode APORT1YCH17 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19 << 16) /**< Shifted mode APORT1YCH19 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21 << 16) /**< Shifted mode APORT1YCH21 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23 << 16) /**< Shifted mode APORT1YCH23 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25 << 16) /**< Shifted mode APORT1YCH25 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27 << 16) /**< Shifted mode APORT1YCH27 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29 << 16) /**< Shifted mode APORT1YCH29 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31 << 16) /**< Shifted mode APORT1YCH31 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0 << 16) /**< Shifted mode APORT2YCH0 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2 << 16) /**< Shifted mode APORT2YCH2 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4 << 16) /**< Shifted mode APORT2YCH4 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6 << 16) /**< Shifted mode APORT2YCH6 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8 << 16) /**< Shifted mode APORT2YCH8 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10 << 16) /**< Shifted mode APORT2YCH10 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12 << 16) /**< Shifted mode APORT2YCH12 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14 << 16) /**< Shifted mode APORT2YCH14 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16 << 16) /**< Shifted mode APORT2YCH16 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18 << 16) /**< Shifted mode APORT2YCH18 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20 << 16) /**< Shifted mode APORT2YCH20 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22 << 16) /**< Shifted mode APORT2YCH22 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24 << 16) /**< Shifted mode APORT2YCH24 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26 << 16) /**< Shifted mode APORT2YCH26 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28 << 16) /**< Shifted mode APORT2YCH28 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30 << 16) /**< Shifted mode APORT2YCH30 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1 << 16) /**< Shifted mode APORT3YCH1 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3 << 16) /**< Shifted mode APORT3YCH3 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5 << 16) /**< Shifted mode APORT3YCH5 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7 << 16) /**< Shifted mode APORT3YCH7 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9 << 16) /**< Shifted mode APORT3YCH9 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11 << 16) /**< Shifted mode APORT3YCH11 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13 << 16) /**< Shifted mode APORT3YCH13 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15 << 16) /**< Shifted mode APORT3YCH15 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17 << 16) /**< Shifted mode APORT3YCH17 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19 << 16) /**< Shifted mode APORT3YCH19 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21 << 16) /**< Shifted mode APORT3YCH21 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23 << 16) /**< Shifted mode APORT3YCH23 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25 << 16) /**< Shifted mode APORT3YCH25 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27 << 16) /**< Shifted mode APORT3YCH27 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29 << 16) /**< Shifted mode APORT3YCH29 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31 << 16) /**< Shifted mode APORT3YCH31 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0 << 16) /**< Shifted mode APORT4YCH0 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2 << 16) /**< Shifted mode APORT4YCH2 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4 << 16) /**< Shifted mode APORT4YCH4 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6 << 16) /**< Shifted mode APORT4YCH6 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8 << 16) /**< Shifted mode APORT4YCH8 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10 << 16) /**< Shifted mode APORT4YCH10 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12 << 16) /**< Shifted mode APORT4YCH12 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14 << 16) /**< Shifted mode APORT4YCH14 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16 << 16) /**< Shifted mode APORT4YCH16 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18 << 16) /**< Shifted mode APORT4YCH18 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20 << 16) /**< Shifted mode APORT4YCH20 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22 << 16) /**< Shifted mode APORT4YCH22 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24 << 16) /**< Shifted mode APORT4YCH24 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26 << 16) /**< Shifted mode APORT4YCH26 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28 << 16) /**< Shifted mode APORT4YCH28 for VDAC_OPA_OUT */
-#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30 << 16) /**< Shifted mode APORT4YCH30 for VDAC_OPA_OUT */
-
-/* Bit fields for VDAC OPA_CAL */
-#define _VDAC_OPA_CAL_RESETVALUE 0x000080E7UL /**< Default value for VDAC_OPA_CAL */
-#define _VDAC_OPA_CAL_MASK 0x7DF6EDEFUL /**< Mask for VDAC_OPA_CAL */
-#define _VDAC_OPA_CAL_CM1_SHIFT 0 /**< Shift value for VDAC_OPACM1 */
-#define _VDAC_OPA_CAL_CM1_MASK 0xFUL /**< Bit mask for VDAC_OPACM1 */
-#define _VDAC_OPA_CAL_CM1_DEFAULT 0x00000007UL /**< Mode DEFAULT for VDAC_OPA_CAL */
-#define VDAC_OPA_CAL_CM1_DEFAULT (_VDAC_OPA_CAL_CM1_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */
-#define _VDAC_OPA_CAL_CM2_SHIFT 5 /**< Shift value for VDAC_OPACM2 */
-#define _VDAC_OPA_CAL_CM2_MASK 0x1E0UL /**< Bit mask for VDAC_OPACM2 */
-#define _VDAC_OPA_CAL_CM2_DEFAULT 0x00000007UL /**< Mode DEFAULT for VDAC_OPA_CAL */
-#define VDAC_OPA_CAL_CM2_DEFAULT (_VDAC_OPA_CAL_CM2_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */
-#define _VDAC_OPA_CAL_CM3_SHIFT 10 /**< Shift value for VDAC_OPACM3 */
-#define _VDAC_OPA_CAL_CM3_MASK 0xC00UL /**< Bit mask for VDAC_OPACM3 */
-#define _VDAC_OPA_CAL_CM3_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */
-#define VDAC_OPA_CAL_CM3_DEFAULT (_VDAC_OPA_CAL_CM3_DEFAULT << 10) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */
-#define _VDAC_OPA_CAL_GM_SHIFT 13 /**< Shift value for VDAC_OPAGM */
-#define _VDAC_OPA_CAL_GM_MASK 0xE000UL /**< Bit mask for VDAC_OPAGM */
-#define _VDAC_OPA_CAL_GM_DEFAULT 0x00000004UL /**< Mode DEFAULT for VDAC_OPA_CAL */
-#define VDAC_OPA_CAL_GM_DEFAULT (_VDAC_OPA_CAL_GM_DEFAULT << 13) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */
-#define _VDAC_OPA_CAL_GM3_SHIFT 17 /**< Shift value for VDAC_OPAGM3 */
-#define _VDAC_OPA_CAL_GM3_MASK 0x60000UL /**< Bit mask for VDAC_OPAGM3 */
-#define _VDAC_OPA_CAL_GM3_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */
-#define VDAC_OPA_CAL_GM3_DEFAULT (_VDAC_OPA_CAL_GM3_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */
-#define _VDAC_OPA_CAL_OFFSETP_SHIFT 20 /**< Shift value for VDAC_OPAOFFSETP */
-#define _VDAC_OPA_CAL_OFFSETP_MASK 0x1F00000UL /**< Bit mask for VDAC_OPAOFFSETP */
-#define _VDAC_OPA_CAL_OFFSETP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */
-#define VDAC_OPA_CAL_OFFSETP_DEFAULT (_VDAC_OPA_CAL_OFFSETP_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */
-#define _VDAC_OPA_CAL_OFFSETN_SHIFT 26 /**< Shift value for VDAC_OPAOFFSETN */
-#define _VDAC_OPA_CAL_OFFSETN_MASK 0x7C000000UL /**< Bit mask for VDAC_OPAOFFSETN */
-#define _VDAC_OPA_CAL_OFFSETN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */
-#define VDAC_OPA_CAL_OFFSETN_DEFAULT (_VDAC_OPA_CAL_OFFSETN_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */
-
-/** @} */
-/** @} End of group EFR32FG13P_VDAC */
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_wdog.h b/mcu/efr/common/vendor/efr32fg13/efr32fg13p_wdog.h
deleted file mode 100644
index b5fc475a..00000000
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_wdog.h
+++ /dev/null
@@ -1,344 +0,0 @@
-/**************************************************************************//**
- * @file efr32fg13p_wdog.h
- * @brief EFR32FG13P_WDOG register and bit field definitions
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#if defined(__ICCARM__)
-#pragma system_include /* Treat file as system include file. */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header /* Treat file as system include file. */
-#endif
-
-/**************************************************************************//**
-* @addtogroup Parts
-* @{
-******************************************************************************/
-/**************************************************************************//**
- * @defgroup EFR32FG13P_WDOG WDOG
- * @{
- * @brief EFR32FG13P_WDOG Register Declaration
- *****************************************************************************/
-/** WDOG Register Declaration */
-typedef struct {
- __IOM uint32_t CTRL; /**< Control Register */
- __IOM uint32_t CMD; /**< Command Register */
-
- __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
-
- WDOG_PCH_TypeDef PCH[2]; /**< PCH */
-
- uint32_t RESERVED0[2]; /**< Reserved for future use **/
- __IM uint32_t IF; /**< Watchdog Interrupt Flags */
- __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
- __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
- __IOM uint32_t IEN; /**< Interrupt Enable Register */
-} WDOG_TypeDef; /** @} */
-
-/**************************************************************************//**
- * @addtogroup EFR32FG13P_WDOG
- * @{
- * @defgroup EFR32FG13P_WDOG_BitFields WDOG Bit Fields
- * @{
- *****************************************************************************/
-
-/* Bit fields for WDOG CTRL */
-#define _WDOG_CTRL_RESETVALUE 0x00000F00UL /**< Default value for WDOG_CTRL */
-#define _WDOG_CTRL_MASK 0xC7033F7FUL /**< Mask for WDOG_CTRL */
-#define WDOG_CTRL_EN (0x1UL << 0) /**< Watchdog Timer Enable */
-#define _WDOG_CTRL_EN_SHIFT 0 /**< Shift value for WDOG_EN */
-#define _WDOG_CTRL_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */
-#define _WDOG_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
-#define WDOG_CTRL_EN_DEFAULT (_WDOG_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CTRL */
-#define WDOG_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */
-#define _WDOG_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for WDOG_DEBUGRUN */
-#define _WDOG_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for WDOG_DEBUGRUN */
-#define _WDOG_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
-#define WDOG_CTRL_DEBUGRUN_DEFAULT (_WDOG_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CTRL */
-#define WDOG_CTRL_EM2RUN (0x1UL << 2) /**< Energy Mode 2 Run Enable */
-#define _WDOG_CTRL_EM2RUN_SHIFT 2 /**< Shift value for WDOG_EM2RUN */
-#define _WDOG_CTRL_EM2RUN_MASK 0x4UL /**< Bit mask for WDOG_EM2RUN */
-#define _WDOG_CTRL_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
-#define WDOG_CTRL_EM2RUN_DEFAULT (_WDOG_CTRL_EM2RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CTRL */
-#define WDOG_CTRL_EM3RUN (0x1UL << 3) /**< Energy Mode 3 Run Enable */
-#define _WDOG_CTRL_EM3RUN_SHIFT 3 /**< Shift value for WDOG_EM3RUN */
-#define _WDOG_CTRL_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */
-#define _WDOG_CTRL_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
-#define WDOG_CTRL_EM3RUN_DEFAULT (_WDOG_CTRL_EM3RUN_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CTRL */
-#define WDOG_CTRL_LOCK (0x1UL << 4) /**< Configuration Lock */
-#define _WDOG_CTRL_LOCK_SHIFT 4 /**< Shift value for WDOG_LOCK */
-#define _WDOG_CTRL_LOCK_MASK 0x10UL /**< Bit mask for WDOG_LOCK */
-#define _WDOG_CTRL_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
-#define WDOG_CTRL_LOCK_DEFAULT (_WDOG_CTRL_LOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CTRL */
-#define WDOG_CTRL_EM4BLOCK (0x1UL << 5) /**< Energy Mode 4 Block */
-#define _WDOG_CTRL_EM4BLOCK_SHIFT 5 /**< Shift value for WDOG_EM4BLOCK */
-#define _WDOG_CTRL_EM4BLOCK_MASK 0x20UL /**< Bit mask for WDOG_EM4BLOCK */
-#define _WDOG_CTRL_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
-#define WDOG_CTRL_EM4BLOCK_DEFAULT (_WDOG_CTRL_EM4BLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for WDOG_CTRL */
-#define WDOG_CTRL_SWOSCBLOCK (0x1UL << 6) /**< Software Oscillator Disable Block */
-#define _WDOG_CTRL_SWOSCBLOCK_SHIFT 6 /**< Shift value for WDOG_SWOSCBLOCK */
-#define _WDOG_CTRL_SWOSCBLOCK_MASK 0x40UL /**< Bit mask for WDOG_SWOSCBLOCK */
-#define _WDOG_CTRL_SWOSCBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
-#define WDOG_CTRL_SWOSCBLOCK_DEFAULT (_WDOG_CTRL_SWOSCBLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for WDOG_CTRL */
-#define _WDOG_CTRL_PERSEL_SHIFT 8 /**< Shift value for WDOG_PERSEL */
-#define _WDOG_CTRL_PERSEL_MASK 0xF00UL /**< Bit mask for WDOG_PERSEL */
-#define _WDOG_CTRL_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CTRL */
-#define WDOG_CTRL_PERSEL_DEFAULT (_WDOG_CTRL_PERSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CTRL */
-#define _WDOG_CTRL_CLKSEL_SHIFT 12 /**< Shift value for WDOG_CLKSEL */
-#define _WDOG_CTRL_CLKSEL_MASK 0x3000UL /**< Bit mask for WDOG_CLKSEL */
-#define _WDOG_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
-#define _WDOG_CTRL_CLKSEL_ULFRCO 0x00000000UL /**< Mode ULFRCO for WDOG_CTRL */
-#define _WDOG_CTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for WDOG_CTRL */
-#define _WDOG_CTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for WDOG_CTRL */
-#define _WDOG_CTRL_CLKSEL_HFCORECLK 0x00000003UL /**< Mode HFCORECLK for WDOG_CTRL */
-#define WDOG_CTRL_CLKSEL_DEFAULT (_WDOG_CTRL_CLKSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for WDOG_CTRL */
-#define WDOG_CTRL_CLKSEL_ULFRCO (_WDOG_CTRL_CLKSEL_ULFRCO << 12) /**< Shifted mode ULFRCO for WDOG_CTRL */
-#define WDOG_CTRL_CLKSEL_LFRCO (_WDOG_CTRL_CLKSEL_LFRCO << 12) /**< Shifted mode LFRCO for WDOG_CTRL */
-#define WDOG_CTRL_CLKSEL_LFXO (_WDOG_CTRL_CLKSEL_LFXO << 12) /**< Shifted mode LFXO for WDOG_CTRL */
-#define WDOG_CTRL_CLKSEL_HFCORECLK (_WDOG_CTRL_CLKSEL_HFCORECLK << 12) /**< Shifted mode HFCORECLK for WDOG_CTRL */
-#define _WDOG_CTRL_WARNSEL_SHIFT 16 /**< Shift value for WDOG_WARNSEL */
-#define _WDOG_CTRL_WARNSEL_MASK 0x30000UL /**< Bit mask for WDOG_WARNSEL */
-#define _WDOG_CTRL_WARNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
-#define WDOG_CTRL_WARNSEL_DEFAULT (_WDOG_CTRL_WARNSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WDOG_CTRL */
-#define _WDOG_CTRL_WINSEL_SHIFT 24 /**< Shift value for WDOG_WINSEL */
-#define _WDOG_CTRL_WINSEL_MASK 0x7000000UL /**< Bit mask for WDOG_WINSEL */
-#define _WDOG_CTRL_WINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
-#define WDOG_CTRL_WINSEL_DEFAULT (_WDOG_CTRL_WINSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for WDOG_CTRL */
-#define WDOG_CTRL_CLRSRC (0x1UL << 30) /**< Watchdog Clear Source */
-#define _WDOG_CTRL_CLRSRC_SHIFT 30 /**< Shift value for WDOG_CLRSRC */
-#define _WDOG_CTRL_CLRSRC_MASK 0x40000000UL /**< Bit mask for WDOG_CLRSRC */
-#define _WDOG_CTRL_CLRSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
-#define _WDOG_CTRL_CLRSRC_SW 0x00000000UL /**< Mode SW for WDOG_CTRL */
-#define _WDOG_CTRL_CLRSRC_PCH0 0x00000001UL /**< Mode PCH0 for WDOG_CTRL */
-#define WDOG_CTRL_CLRSRC_DEFAULT (_WDOG_CTRL_CLRSRC_DEFAULT << 30) /**< Shifted mode DEFAULT for WDOG_CTRL */
-#define WDOG_CTRL_CLRSRC_SW (_WDOG_CTRL_CLRSRC_SW << 30) /**< Shifted mode SW for WDOG_CTRL */
-#define WDOG_CTRL_CLRSRC_PCH0 (_WDOG_CTRL_CLRSRC_PCH0 << 30) /**< Shifted mode PCH0 for WDOG_CTRL */
-#define WDOG_CTRL_WDOGRSTDIS (0x1UL << 31) /**< Watchdog Reset Disable */
-#define _WDOG_CTRL_WDOGRSTDIS_SHIFT 31 /**< Shift value for WDOG_WDOGRSTDIS */
-#define _WDOG_CTRL_WDOGRSTDIS_MASK 0x80000000UL /**< Bit mask for WDOG_WDOGRSTDIS */
-#define _WDOG_CTRL_WDOGRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
-#define _WDOG_CTRL_WDOGRSTDIS_EN 0x00000000UL /**< Mode EN for WDOG_CTRL */
-#define _WDOG_CTRL_WDOGRSTDIS_DIS 0x00000001UL /**< Mode DIS for WDOG_CTRL */
-#define WDOG_CTRL_WDOGRSTDIS_DEFAULT (_WDOG_CTRL_WDOGRSTDIS_DEFAULT << 31) /**< Shifted mode DEFAULT for WDOG_CTRL */
-#define WDOG_CTRL_WDOGRSTDIS_EN (_WDOG_CTRL_WDOGRSTDIS_EN << 31) /**< Shifted mode EN for WDOG_CTRL */
-#define WDOG_CTRL_WDOGRSTDIS_DIS (_WDOG_CTRL_WDOGRSTDIS_DIS << 31) /**< Shifted mode DIS for WDOG_CTRL */
-
-/* Bit fields for WDOG CMD */
-#define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */
-#define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */
-#define WDOG_CMD_CLEAR (0x1UL << 0) /**< Watchdog Timer Clear */
-#define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */
-#define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */
-#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */
-#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */
-#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */
-#define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */
-#define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */
-#define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */
-
-/* Bit fields for WDOG SYNCBUSY */
-#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */
-#define _WDOG_SYNCBUSY_MASK 0x0000000FUL /**< Mask for WDOG_SYNCBUSY */
-#define WDOG_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
-#define _WDOG_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for WDOG_CTRL */
-#define _WDOG_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for WDOG_CTRL */
-#define _WDOG_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */
-#define WDOG_SYNCBUSY_CTRL_DEFAULT (_WDOG_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
-#define WDOG_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */
-#define _WDOG_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for WDOG_CMD */
-#define _WDOG_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for WDOG_CMD */
-#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */
-#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
-#define WDOG_SYNCBUSY_PCH0_PRSCTRL (0x1UL << 2) /**< PCH0_PRSCTRL Register Busy */
-#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_SHIFT 2 /**< Shift value for WDOG_PCH0_PRSCTRL */
-#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_MASK 0x4UL /**< Bit mask for WDOG_PCH0_PRSCTRL */
-#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */
-#define WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT (_WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
-#define WDOG_SYNCBUSY_PCH1_PRSCTRL (0x1UL << 3) /**< PCH1_PRSCTRL Register Busy */
-#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_SHIFT 3 /**< Shift value for WDOG_PCH1_PRSCTRL */
-#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_MASK 0x8UL /**< Bit mask for WDOG_PCH1_PRSCTRL */
-#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */
-#define WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT (_WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
-
-/* Bit fields for WDOG PCH_PRSCTRL */
-#define _WDOG_PCH_PRSCTRL_RESETVALUE 0x00000000UL /**< Default value for WDOG_PCH_PRSCTRL */
-#define _WDOG_PCH_PRSCTRL_MASK 0x0000010FUL /**< Mask for WDOG_PCH_PRSCTRL */
-#define _WDOG_PCH_PRSCTRL_PRSSEL_SHIFT 0 /**< Shift value for WDOG_PRSSEL */
-#define _WDOG_PCH_PRSCTRL_PRSSEL_MASK 0xFUL /**< Bit mask for WDOG_PRSSEL */
-#define _WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */
-#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WDOG_PCH_PRSCTRL */
-#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WDOG_PCH_PRSCTRL */
-#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WDOG_PCH_PRSCTRL */
-#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WDOG_PCH_PRSCTRL */
-#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WDOG_PCH_PRSCTRL */
-#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WDOG_PCH_PRSCTRL */
-#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WDOG_PCH_PRSCTRL */
-#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WDOG_PCH_PRSCTRL */
-#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WDOG_PCH_PRSCTRL */
-#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WDOG_PCH_PRSCTRL */
-#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WDOG_PCH_PRSCTRL */
-#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WDOG_PCH_PRSCTRL */
-#define WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT (_WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_PCH_PRSCTRL */
-#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WDOG_PCH_PRSCTRL */
-#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WDOG_PCH_PRSCTRL */
-#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WDOG_PCH_PRSCTRL */
-#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WDOG_PCH_PRSCTRL */
-#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WDOG_PCH_PRSCTRL */
-#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WDOG_PCH_PRSCTRL */
-#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WDOG_PCH_PRSCTRL */
-#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WDOG_PCH_PRSCTRL */
-#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WDOG_PCH_PRSCTRL */
-#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WDOG_PCH_PRSCTRL */
-#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WDOG_PCH_PRSCTRL */
-#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WDOG_PCH_PRSCTRL */
-#define WDOG_PCH_PRSCTRL_PRSMISSRSTEN (0x1UL << 8) /**< PRS Missing Event Will Trigger a Watchdog Reset */
-#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_SHIFT 8 /**< Shift value for WDOG_PRSMISSRSTEN */
-#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_MASK 0x100UL /**< Bit mask for WDOG_PRSMISSRSTEN */
-#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */
-#define WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT (_WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_PCH_PRSCTRL */
-
-/* Bit fields for WDOG IF */
-#define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */
-#define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */
-#define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */
-#define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */
-#define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */
-#define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
-#define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */
-#define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */
-#define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */
-#define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */
-#define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
-#define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */
-#define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */
-#define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */
-#define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */
-#define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
-#define WDOG_IF_WIN_DEFAULT (_WDOG_IF_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IF */
-#define WDOG_IF_PEM0 (0x1UL << 3) /**< PRS Channel Zero Event Missing Interrupt Flag */
-#define _WDOG_IF_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */
-#define _WDOG_IF_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */
-#define _WDOG_IF_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
-#define WDOG_IF_PEM0_DEFAULT (_WDOG_IF_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IF */
-#define WDOG_IF_PEM1 (0x1UL << 4) /**< PRS Channel One Event Missing Interrupt Flag */
-#define _WDOG_IF_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */
-#define _WDOG_IF_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */
-#define _WDOG_IF_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
-#define WDOG_IF_PEM1_DEFAULT (_WDOG_IF_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IF */
-
-/* Bit fields for WDOG IFS */
-#define _WDOG_IFS_RESETVALUE 0x00000000UL /**< Default value for WDOG_IFS */
-#define _WDOG_IFS_MASK 0x0000001FUL /**< Mask for WDOG_IFS */
-#define WDOG_IFS_TOUT (0x1UL << 0) /**< Set TOUT Interrupt Flag */
-#define _WDOG_IFS_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */
-#define _WDOG_IFS_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */
-#define _WDOG_IFS_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */
-#define WDOG_IFS_TOUT_DEFAULT (_WDOG_IFS_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IFS */
-#define WDOG_IFS_WARN (0x1UL << 1) /**< Set WARN Interrupt Flag */
-#define _WDOG_IFS_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */
-#define _WDOG_IFS_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */
-#define _WDOG_IFS_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */
-#define WDOG_IFS_WARN_DEFAULT (_WDOG_IFS_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IFS */
-#define WDOG_IFS_WIN (0x1UL << 2) /**< Set WIN Interrupt Flag */
-#define _WDOG_IFS_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */
-#define _WDOG_IFS_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */
-#define _WDOG_IFS_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */
-#define WDOG_IFS_WIN_DEFAULT (_WDOG_IFS_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IFS */
-#define WDOG_IFS_PEM0 (0x1UL << 3) /**< Set PEM0 Interrupt Flag */
-#define _WDOG_IFS_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */
-#define _WDOG_IFS_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */
-#define _WDOG_IFS_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */
-#define WDOG_IFS_PEM0_DEFAULT (_WDOG_IFS_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IFS */
-#define WDOG_IFS_PEM1 (0x1UL << 4) /**< Set PEM1 Interrupt Flag */
-#define _WDOG_IFS_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */
-#define _WDOG_IFS_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */
-#define _WDOG_IFS_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */
-#define WDOG_IFS_PEM1_DEFAULT (_WDOG_IFS_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IFS */
-
-/* Bit fields for WDOG IFC */
-#define _WDOG_IFC_RESETVALUE 0x00000000UL /**< Default value for WDOG_IFC */
-#define _WDOG_IFC_MASK 0x0000001FUL /**< Mask for WDOG_IFC */
-#define WDOG_IFC_TOUT (0x1UL << 0) /**< Clear TOUT Interrupt Flag */
-#define _WDOG_IFC_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */
-#define _WDOG_IFC_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */
-#define _WDOG_IFC_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */
-#define WDOG_IFC_TOUT_DEFAULT (_WDOG_IFC_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IFC */
-#define WDOG_IFC_WARN (0x1UL << 1) /**< Clear WARN Interrupt Flag */
-#define _WDOG_IFC_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */
-#define _WDOG_IFC_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */
-#define _WDOG_IFC_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */
-#define WDOG_IFC_WARN_DEFAULT (_WDOG_IFC_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IFC */
-#define WDOG_IFC_WIN (0x1UL << 2) /**< Clear WIN Interrupt Flag */
-#define _WDOG_IFC_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */
-#define _WDOG_IFC_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */
-#define _WDOG_IFC_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */
-#define WDOG_IFC_WIN_DEFAULT (_WDOG_IFC_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IFC */
-#define WDOG_IFC_PEM0 (0x1UL << 3) /**< Clear PEM0 Interrupt Flag */
-#define _WDOG_IFC_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */
-#define _WDOG_IFC_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */
-#define _WDOG_IFC_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */
-#define WDOG_IFC_PEM0_DEFAULT (_WDOG_IFC_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IFC */
-#define WDOG_IFC_PEM1 (0x1UL << 4) /**< Clear PEM1 Interrupt Flag */
-#define _WDOG_IFC_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */
-#define _WDOG_IFC_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */
-#define _WDOG_IFC_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */
-#define WDOG_IFC_PEM1_DEFAULT (_WDOG_IFC_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IFC */
-
-/* Bit fields for WDOG IEN */
-#define _WDOG_IEN_RESETVALUE 0x00000000UL /**< Default value for WDOG_IEN */
-#define _WDOG_IEN_MASK 0x0000001FUL /**< Mask for WDOG_IEN */
-#define WDOG_IEN_TOUT (0x1UL << 0) /**< TOUT Interrupt Enable */
-#define _WDOG_IEN_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */
-#define _WDOG_IEN_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */
-#define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
-#define WDOG_IEN_TOUT_DEFAULT (_WDOG_IEN_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IEN */
-#define WDOG_IEN_WARN (0x1UL << 1) /**< WARN Interrupt Enable */
-#define _WDOG_IEN_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */
-#define _WDOG_IEN_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */
-#define _WDOG_IEN_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
-#define WDOG_IEN_WARN_DEFAULT (_WDOG_IEN_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IEN */
-#define WDOG_IEN_WIN (0x1UL << 2) /**< WIN Interrupt Enable */
-#define _WDOG_IEN_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */
-#define _WDOG_IEN_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */
-#define _WDOG_IEN_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
-#define WDOG_IEN_WIN_DEFAULT (_WDOG_IEN_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IEN */
-#define WDOG_IEN_PEM0 (0x1UL << 3) /**< PEM0 Interrupt Enable */
-#define _WDOG_IEN_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */
-#define _WDOG_IEN_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */
-#define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
-#define WDOG_IEN_PEM0_DEFAULT (_WDOG_IEN_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IEN */
-#define WDOG_IEN_PEM1 (0x1UL << 4) /**< PEM1 Interrupt Enable */
-#define _WDOG_IEN_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */
-#define _WDOG_IEN_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */
-#define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
-#define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */
-
-/** @} */
-/** @} End of group EFR32FG13P_WDOG */
-/** @} End of group Parts */
diff --git a/mcu/efr/common/vendor/efr32fg13/em_device_fg13.h b/mcu/efr/common/vendor/efr32fg13/em_device_fg13.h
deleted file mode 100644
index 88c0193a..00000000
--- a/mcu/efr/common/vendor/efr32fg13/em_device_fg13.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/**************************************************************************//**
- * @file em_device.h
- * @brief CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories
- * microcontroller devices
- *
- * This is a convenience header file for defining the part number on the
- * build command line, instead of specifying the part specific header file.
- *
- * @verbatim
- * Example: Add "-DEFM32G890F128" to your build options, to define part
- * Add "#include "em_device.h" to your source files
-
- *
- * @endverbatim
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#ifndef EM_DEVICE_FG13_H
-#define EM_DEVICE_FG13_H
-
-#if defined(EFR32FG13P231F512GM32)
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p231f512gm32.h"
-
-#elif defined(EFR32FG13P231F512GM48)
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p231f512gm48.h"
-
-#elif defined(EFR32FG13P231F512IM32)
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p231f512im32.h"
-
-#elif defined(EFR32FG13P231F512IM48)
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p231f512im48.h"
-
-#elif defined(EFR32FG13P232F512GM32)
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p232f512gm32.h"
-
-#elif defined(EFR32FG13P232F512GM48)
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p232f512gm48.h"
-
-#elif defined(EFR32FG13P233F512GM48)
-#include "../../../efr32/vendor/efr32fg13/efr32fg13p233f512gm48.h"
-
-#else
-#error "em_device.h: PART NUMBER undefined"
-#endif
-#endif /* EM_DEVICE_FG13_H */
diff --git a/mcu/efr/common/vendor/efr32fg13/system_efr32fg13p.c b/mcu/efr/common/vendor/efr32fg13/system_efr32fg13p.c
deleted file mode 100644
index 176d39ce..00000000
--- a/mcu/efr/common/vendor/efr32fg13/system_efr32fg13p.c
+++ /dev/null
@@ -1,379 +0,0 @@
-/***************************************************************************//**
- * @file system_efr32fg13p.c
- * @brief CMSIS Cortex-M3/M4 System Layer for EFR32 devices.
- * @version 5.4.0
- ******************************************************************************
- * # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
- ******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
- *****************************************************************************/
-
-#include
-
-#include "../../../efr32/vendor/efr32fg13/em_device_fg13.h"
-
-/*******************************************************************************
- ****************************** DEFINES ************************************
- ******************************************************************************/
-
-/** LFRCO frequency, tuned to below frequency during manufacturing. */
-#define EFR32_LFRCO_FREQ (32768UL)
-/** ULFRCO frequency */
-#define EFR32_ULFRCO_FREQ (1000UL)
-
-/*******************************************************************************
- ************************** LOCAL VARIABLES ********************************
- ******************************************************************************/
-
-/* System oscillator frequencies. These frequencies are normally constant */
-/* for a target, but they are made configurable in order to allow run-time */
-/* handling of different boards. The crystal oscillator clocks can be set */
-/* compile time to a non-default value by defining respective EFR32_nFXO_FREQ */
-/* values according to board design. By defining the EFR32_nFXO_FREQ to 0, */
-/* one indicates that the oscillator is not present, in order to save some */
-/* SW footprint. */
-
-#ifndef EFR32_HFRCO_MAX_FREQ
-/** Maximum HFRCO frequency */
-#define EFR32_HFRCO_MAX_FREQ (38000000UL)
-#endif
-
-#ifndef EFR32_HFXO_FREQ
-/** HFXO frequency */
-#define EFR32_HFXO_FREQ (38400000UL)
-#endif
-
-#ifndef EFR32_HFRCO_STARTUP_FREQ
-/** HFRCO startup frequency */
-#define EFR32_HFRCO_STARTUP_FREQ (19000000UL)
-#endif
-
-/* Do not define variable if HF crystal oscillator not present */
-#if (EFR32_HFXO_FREQ > 0UL)
-/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
-/** System HFXO clock. */
-static uint32_t SystemHFXOClock = EFR32_HFXO_FREQ;
-/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
-#endif
-
-#ifndef EFR32_LFXO_FREQ
-/** LFXO frequency */
-#define EFR32_LFXO_FREQ (EFR32_LFRCO_FREQ)
-#endif
-/* Do not define variable if LF crystal oscillator not present */
-#if (EFR32_LFXO_FREQ > 0UL)
-/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
-/** System LFXO clock. */
-static uint32_t SystemLFXOClock = EFR32_LFXO_FREQ;
-/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
-#endif
-
-/*******************************************************************************
- ************************** GLOBAL VARIABLES *******************************
- ******************************************************************************/
-
-/**
- * @brief
- * System System Clock Frequency (Core Clock).
- *
- * @details
- * Required CMSIS global variable that must be kept up-to-date.
- */
-uint32_t SystemCoreClock = EFR32_HFRCO_STARTUP_FREQ;
-
-/**
- * @brief
- * System HFRCO frequency
- *
- * @note
- * This is an EFR32 proprietary variable, not part of the CMSIS definition.
- *
- * @details
- * Frequency of the system HFRCO oscillator
- */
-uint32_t SystemHfrcoFreq = EFR32_HFRCO_STARTUP_FREQ;
-
-/*******************************************************************************
- ************************** GLOBAL FUNCTIONS *******************************
- ******************************************************************************/
-
-/***************************************************************************//**
- * @brief
- * Get the current core clock frequency.
- *
- * @details
- * Calculate and get the current core clock frequency based on the current
- * configuration. Assuming that the SystemCoreClock global variable is
- * maintained, the core clock frequency is stored in that variable as well.
- * This function will however calculate the core clock based on actual HW
- * configuration. It will also update the SystemCoreClock global variable.
- *
- * @note
- * This is an EFR32 proprietary function, not part of the CMSIS definition.
- *
- * @return
- * The current core clock frequency in Hz.
- ******************************************************************************/
-uint32_t SystemCoreClockGet(void)
-{
- uint32_t ret;
- uint32_t presc;
-
- ret = SystemHFClockGet();
- presc = (CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK)
- >> _CMU_HFCOREPRESC_PRESC_SHIFT;
- ret /= presc + 1U;
-
- /* Keep CMSIS system clock variable up-to-date */
- SystemCoreClock = ret;
-
- return ret;
-}
-
-/***************************************************************************//**
- * @brief
- * Get the maximum core clock frequency.
- *
- * @note
- * This is an EFR32 proprietary function, not part of the CMSIS definition.
- *
- * @return
- * The maximum core clock frequency in Hz.
- ******************************************************************************/
-uint32_t SystemMaxCoreClockGet(void)
-{
-#if (EFR32_HFRCO_MAX_FREQ > EFR32_HFXO_FREQ)
- return EFR32_HFRCO_MAX_FREQ;
-#else
- return EFR32_HFXO_FREQ;
-#endif
-}
-
-/***************************************************************************//**
- * @brief
- * Get the current HFCLK frequency.
- *
- * @note
- * This is an EFR proprietary function, not part of the CMSIS definition.
- *
- * @return
- * The current HFCLK frequency in Hz.
- ******************************************************************************/
-uint32_t SystemHFClockGet(void)
-{
- uint32_t ret;
-
- switch (CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) {
- case CMU_HFCLKSTATUS_SELECTED_LFXO:
-#if (EFR32_LFXO_FREQ > 0)
- ret = SystemLFXOClock;
-#else
- /* We should not get here, since core should not be clocked. May */
- /* be caused by a misconfiguration though. */
- ret = 0;
-#endif
- break;
-
- case CMU_HFCLKSTATUS_SELECTED_LFRCO:
- ret = EFR32_LFRCO_FREQ;
- break;
-
- case CMU_HFCLKSTATUS_SELECTED_HFXO:
-#if (EFR32_HFXO_FREQ > 0)
- ret = SystemHFXOClock;
-#else
- /* We should not get here, since core should not be clocked. May */
- /* be caused by a misconfiguration though. */
- ret = 0;
-#endif
- break;
-
- default: /* CMU_HFCLKSTATUS_SELECTED_HFRCO */
- ret = SystemHfrcoFreq;
- break;
- }
-
- return ret / (1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK)
- >> _CMU_HFPRESC_PRESC_SHIFT));
-}
-
-/**************************************************************************//**
- * @brief
- * Get high frequency crystal oscillator clock frequency for target system.
- *
- * @note
- * This is an EFR proprietary function, not part of the CMSIS definition.
- *
- * @return
- * HFXO frequency in Hz.
- *****************************************************************************/
-uint32_t SystemHFXOClockGet(void)
-{
- /* External crystal oscillator present? */
-#if (EFR32_HFXO_FREQ > 0)
- return SystemHFXOClock;
-#else
- return 0;
-#endif
-}
-
-/**************************************************************************//**
- * @brief
- * Set high frequency crystal oscillator clock frequency for target system.
- *
- * @note
- * This function is mainly provided for being able to handle target systems
- * with different HF crystal oscillator frequencies run-time. If used, it
- * should probably only be used once during system startup.
- *
- * @note
- * This is an EFR proprietary function, not part of the CMSIS definition.
- *
- * @param[in] freq
- * HFXO frequency in Hz used for target.
- *****************************************************************************/
-void SystemHFXOClockSet(uint32_t freq)
-{
- /* External crystal oscillator present? */
-#if (EFR32_HFXO_FREQ > 0)
- SystemHFXOClock = freq;
-
- /* Update core clock frequency if HFXO is used to clock core */
- if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK)
- == CMU_HFCLKSTATUS_SELECTED_HFXO) {
- /* The function will update the global variable */
- (void)SystemCoreClockGet();
- }
-#else
- (void)freq; /* Unused parameter */
-#endif
-}
-
-/**************************************************************************//**
- * @brief
- * Initialize the system.
- *
- * @details
- * Do required generic HW system init.
- *
- * @note
- * This function is invoked during system init, before the main() routine
- * and any data has been initialized. For this reason, it cannot do any
- * initialization of variables etc.
- *****************************************************************************/
-void SystemInit(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- /* Set floating point coprosessor access mode. */
- SCB->CPACR |= ((3UL << 10 * 2) /* set CP10 Full Access */
- | (3UL << 11 * 2)); /* set CP11 Full Access */
-#endif
-}
-
-/**************************************************************************//**
- * @brief
- * Get low frequency RC oscillator clock frequency for target system.
- *
- * @note
- * This is an EFR proprietary function, not part of the CMSIS definition.
- *
- * @return
- * LFRCO frequency in Hz.
- *****************************************************************************/
-uint32_t SystemLFRCOClockGet(void)
-{
- /* Currently we assume that this frequency is properly tuned during */
- /* manufacturing and is not changed after reset. If future requirements */
- /* for re-tuning by user, we can add support for that. */
- return EFR32_LFRCO_FREQ;
-}
-
-/**************************************************************************//**
- * @brief
- * Get ultra low frequency RC oscillator clock frequency for target system.
- *
- * @note
- * This is an EFR proprietary function, not part of the CMSIS definition.
- *
- * @return
- * ULFRCO frequency in Hz.
- *****************************************************************************/
-uint32_t SystemULFRCOClockGet(void)
-{
- /* The ULFRCO frequency is not tuned, and can be very inaccurate */
- return EFR32_ULFRCO_FREQ;
-}
-
-/**************************************************************************//**
- * @brief
- * Get low frequency crystal oscillator clock frequency for target system.
- *
- * @note
- * This is an EFR proprietary function, not part of the CMSIS definition.
- *
- * @return
- * LFXO frequency in Hz.
- *****************************************************************************/
-uint32_t SystemLFXOClockGet(void)
-{
- /* External crystal oscillator present? */
-#if (EFR32_LFXO_FREQ > 0)
- return SystemLFXOClock;
-#else
- return 0;
-#endif
-}
-
-/**************************************************************************//**
- * @brief
- * Set low frequency crystal oscillator clock frequency for target system.
- *
- * @note
- * This function is mainly provided for being able to handle target systems
- * with different HF crystal oscillator frequencies run-time. If used, it
- * should probably only be used once during system startup.
- *
- * @note
- * This is an EFR proprietary function, not part of the CMSIS definition.
- *
- * @param[in] freq
- * LFXO frequency in Hz used for target.
- *****************************************************************************/
-void SystemLFXOClockSet(uint32_t freq)
-{
- /* External crystal oscillator present? */
-#if (EFR32_LFXO_FREQ > 0)
- SystemLFXOClock = freq;
-
- /* Update core clock frequency if LFXO is used to clock core */
- if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK)
- == CMU_HFCLKSTATUS_SELECTED_LFXO) {
- /* The function will update the global variable */
- (void)SystemCoreClockGet();
- }
-#else
- (void)freq; /* Unused parameter */
-#endif
-}
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_acmp.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_acmp.h
new file mode 100644
index 00000000..6087c46d
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_acmp.h
@@ -0,0 +1,654 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 ACMP register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_ACMP_H
+#define EFR32MG24_ACMP_H
+#define ACMP_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_ACMP ACMP
+ * @{
+ * @brief EFR32MG24 ACMP Register Declaration.
+ *****************************************************************************/
+
+/** ACMP Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IP version ID */
+ __IOM uint32_t EN; /**< ACMP enable */
+ __IOM uint32_t SWRST; /**< Software reset */
+ __IOM uint32_t CFG; /**< Configuration register */
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t INPUTCTRL; /**< Input Control Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IOM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IM uint32_t SYNCBUSY; /**< Syncbusy */
+ uint32_t RESERVED0[1014U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP version ID */
+ __IOM uint32_t EN_SET; /**< ACMP enable */
+ __IOM uint32_t SWRST_SET; /**< Software reset */
+ __IOM uint32_t CFG_SET; /**< Configuration register */
+ __IOM uint32_t CTRL_SET; /**< Control Register */
+ __IOM uint32_t INPUTCTRL_SET; /**< Input Control Register */
+ __IM uint32_t STATUS_SET; /**< Status Register */
+ __IOM uint32_t IF_SET; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
+ __IM uint32_t SYNCBUSY_SET; /**< Syncbusy */
+ uint32_t RESERVED1[1014U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP version ID */
+ __IOM uint32_t EN_CLR; /**< ACMP enable */
+ __IOM uint32_t SWRST_CLR; /**< Software reset */
+ __IOM uint32_t CFG_CLR; /**< Configuration register */
+ __IOM uint32_t CTRL_CLR; /**< Control Register */
+ __IOM uint32_t INPUTCTRL_CLR; /**< Input Control Register */
+ __IM uint32_t STATUS_CLR; /**< Status Register */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
+ __IM uint32_t SYNCBUSY_CLR; /**< Syncbusy */
+ uint32_t RESERVED2[1014U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP version ID */
+ __IOM uint32_t EN_TGL; /**< ACMP enable */
+ __IOM uint32_t SWRST_TGL; /**< Software reset */
+ __IOM uint32_t CFG_TGL; /**< Configuration register */
+ __IOM uint32_t CTRL_TGL; /**< Control Register */
+ __IOM uint32_t INPUTCTRL_TGL; /**< Input Control Register */
+ __IM uint32_t STATUS_TGL; /**< Status Register */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
+ __IM uint32_t SYNCBUSY_TGL; /**< Syncbusy */
+} ACMP_TypeDef;
+/** @} End of group EFR32MG24_ACMP */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_ACMP
+ * @{
+ * @defgroup EFR32MG24_ACMP_BitFields ACMP Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for ACMP IPVERSION */
+#define _ACMP_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for ACMP_IPVERSION */
+#define _ACMP_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ACMP_IPVERSION */
+#define _ACMP_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ACMP_IPVERSION */
+#define _ACMP_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ACMP_IPVERSION */
+#define _ACMP_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for ACMP_IPVERSION */
+#define ACMP_IPVERSION_IPVERSION_DEFAULT (_ACMP_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IPVERSION */
+
+/* Bit fields for ACMP EN */
+#define _ACMP_EN_RESETVALUE 0x00000000UL /**< Default value for ACMP_EN */
+#define _ACMP_EN_MASK 0x00000003UL /**< Mask for ACMP_EN */
+#define ACMP_EN_EN (0x1UL << 0) /**< Module enable */
+#define _ACMP_EN_EN_SHIFT 0 /**< Shift value for ACMP_EN */
+#define _ACMP_EN_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */
+#define _ACMP_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EN */
+#define ACMP_EN_EN_DEFAULT (_ACMP_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_EN */
+#define ACMP_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */
+#define _ACMP_EN_DISABLING_SHIFT 1 /**< Shift value for ACMP_DISABLING */
+#define _ACMP_EN_DISABLING_MASK 0x2UL /**< Bit mask for ACMP_DISABLING */
+#define _ACMP_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EN */
+#define ACMP_EN_DISABLING_DEFAULT (_ACMP_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_EN */
+
+/* Bit fields for ACMP SWRST */
+#define _ACMP_SWRST_RESETVALUE 0x00000000UL /**< Default value for ACMP_SWRST */
+#define _ACMP_SWRST_MASK 0x00000003UL /**< Mask for ACMP_SWRST */
+#define ACMP_SWRST_SWRST (0x1UL << 0) /**< Software reset */
+#define _ACMP_SWRST_SWRST_SHIFT 0 /**< Shift value for ACMP_SWRST */
+#define _ACMP_SWRST_SWRST_MASK 0x1UL /**< Bit mask for ACMP_SWRST */
+#define _ACMP_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SWRST */
+#define ACMP_SWRST_SWRST_DEFAULT (_ACMP_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_SWRST */
+#define ACMP_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */
+#define _ACMP_SWRST_RESETTING_SHIFT 1 /**< Shift value for ACMP_RESETTING */
+#define _ACMP_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for ACMP_RESETTING */
+#define _ACMP_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SWRST */
+#define ACMP_SWRST_RESETTING_DEFAULT (_ACMP_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_SWRST */
+
+/* Bit fields for ACMP CFG */
+#define _ACMP_CFG_RESETVALUE 0x00000004UL /**< Default value for ACMP_CFG */
+#define _ACMP_CFG_MASK 0x00030F07UL /**< Mask for ACMP_CFG */
+#define _ACMP_CFG_BIAS_SHIFT 0 /**< Shift value for ACMP_BIAS */
+#define _ACMP_CFG_BIAS_MASK 0x7UL /**< Bit mask for ACMP_BIAS */
+#define _ACMP_CFG_BIAS_DEFAULT 0x00000004UL /**< Mode DEFAULT for ACMP_CFG */
+#define ACMP_CFG_BIAS_DEFAULT (_ACMP_CFG_BIAS_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CFG */
+#define _ACMP_CFG_HYST_SHIFT 8 /**< Shift value for ACMP_HYST */
+#define _ACMP_CFG_HYST_MASK 0xF00UL /**< Bit mask for ACMP_HYST */
+#define _ACMP_CFG_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */
+#define _ACMP_CFG_HYST_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CFG */
+#define _ACMP_CFG_HYST_SYM10MV 0x00000001UL /**< Mode SYM10MV for ACMP_CFG */
+#define _ACMP_CFG_HYST_SYM20MV 0x00000002UL /**< Mode SYM20MV for ACMP_CFG */
+#define _ACMP_CFG_HYST_SYM30MV 0x00000003UL /**< Mode SYM30MV for ACMP_CFG */
+#define _ACMP_CFG_HYST_POS10MV 0x00000004UL /**< Mode POS10MV for ACMP_CFG */
+#define _ACMP_CFG_HYST_POS20MV 0x00000005UL /**< Mode POS20MV for ACMP_CFG */
+#define _ACMP_CFG_HYST_POS30MV 0x00000006UL /**< Mode POS30MV for ACMP_CFG */
+#define _ACMP_CFG_HYST_NEG10MV 0x00000008UL /**< Mode NEG10MV for ACMP_CFG */
+#define _ACMP_CFG_HYST_NEG20MV 0x00000009UL /**< Mode NEG20MV for ACMP_CFG */
+#define _ACMP_CFG_HYST_NEG30MV 0x0000000AUL /**< Mode NEG30MV for ACMP_CFG */
+#define ACMP_CFG_HYST_DEFAULT (_ACMP_CFG_HYST_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_CFG */
+#define ACMP_CFG_HYST_DISABLED (_ACMP_CFG_HYST_DISABLED << 8) /**< Shifted mode DISABLED for ACMP_CFG */
+#define ACMP_CFG_HYST_SYM10MV (_ACMP_CFG_HYST_SYM10MV << 8) /**< Shifted mode SYM10MV for ACMP_CFG */
+#define ACMP_CFG_HYST_SYM20MV (_ACMP_CFG_HYST_SYM20MV << 8) /**< Shifted mode SYM20MV for ACMP_CFG */
+#define ACMP_CFG_HYST_SYM30MV (_ACMP_CFG_HYST_SYM30MV << 8) /**< Shifted mode SYM30MV for ACMP_CFG */
+#define ACMP_CFG_HYST_POS10MV (_ACMP_CFG_HYST_POS10MV << 8) /**< Shifted mode POS10MV for ACMP_CFG */
+#define ACMP_CFG_HYST_POS20MV (_ACMP_CFG_HYST_POS20MV << 8) /**< Shifted mode POS20MV for ACMP_CFG */
+#define ACMP_CFG_HYST_POS30MV (_ACMP_CFG_HYST_POS30MV << 8) /**< Shifted mode POS30MV for ACMP_CFG */
+#define ACMP_CFG_HYST_NEG10MV (_ACMP_CFG_HYST_NEG10MV << 8) /**< Shifted mode NEG10MV for ACMP_CFG */
+#define ACMP_CFG_HYST_NEG20MV (_ACMP_CFG_HYST_NEG20MV << 8) /**< Shifted mode NEG20MV for ACMP_CFG */
+#define ACMP_CFG_HYST_NEG30MV (_ACMP_CFG_HYST_NEG30MV << 8) /**< Shifted mode NEG30MV for ACMP_CFG */
+#define ACMP_CFG_INPUTRANGE (0x1UL << 16) /**< Input Range */
+#define _ACMP_CFG_INPUTRANGE_SHIFT 16 /**< Shift value for ACMP_INPUTRANGE */
+#define _ACMP_CFG_INPUTRANGE_MASK 0x10000UL /**< Bit mask for ACMP_INPUTRANGE */
+#define _ACMP_CFG_INPUTRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */
+#define _ACMP_CFG_INPUTRANGE_FULL 0x00000000UL /**< Mode FULL for ACMP_CFG */
+#define _ACMP_CFG_INPUTRANGE_REDUCED 0x00000001UL /**< Mode REDUCED for ACMP_CFG */
+#define ACMP_CFG_INPUTRANGE_DEFAULT (_ACMP_CFG_INPUTRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_CFG */
+#define ACMP_CFG_INPUTRANGE_FULL (_ACMP_CFG_INPUTRANGE_FULL << 16) /**< Shifted mode FULL for ACMP_CFG */
+#define ACMP_CFG_INPUTRANGE_REDUCED (_ACMP_CFG_INPUTRANGE_REDUCED << 16) /**< Shifted mode REDUCED for ACMP_CFG */
+#define ACMP_CFG_ACCURACY (0x1UL << 17) /**< ACMP accuracy mode */
+#define _ACMP_CFG_ACCURACY_SHIFT 17 /**< Shift value for ACMP_ACCURACY */
+#define _ACMP_CFG_ACCURACY_MASK 0x20000UL /**< Bit mask for ACMP_ACCURACY */
+#define _ACMP_CFG_ACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */
+#define _ACMP_CFG_ACCURACY_LOW 0x00000000UL /**< Mode LOW for ACMP_CFG */
+#define _ACMP_CFG_ACCURACY_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CFG */
+#define ACMP_CFG_ACCURACY_DEFAULT (_ACMP_CFG_ACCURACY_DEFAULT << 17) /**< Shifted mode DEFAULT for ACMP_CFG */
+#define ACMP_CFG_ACCURACY_LOW (_ACMP_CFG_ACCURACY_LOW << 17) /**< Shifted mode LOW for ACMP_CFG */
+#define ACMP_CFG_ACCURACY_HIGH (_ACMP_CFG_ACCURACY_HIGH << 17) /**< Shifted mode HIGH for ACMP_CFG */
+
+/* Bit fields for ACMP CTRL */
+#define _ACMP_CTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_CTRL */
+#define _ACMP_CTRL_MASK 0x00000003UL /**< Mask for ACMP_CTRL */
+#define ACMP_CTRL_NOTRDYVAL (0x1UL << 0) /**< Not Ready Value */
+#define _ACMP_CTRL_NOTRDYVAL_SHIFT 0 /**< Shift value for ACMP_NOTRDYVAL */
+#define _ACMP_CTRL_NOTRDYVAL_MASK 0x1UL /**< Bit mask for ACMP_NOTRDYVAL */
+#define _ACMP_CTRL_NOTRDYVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
+#define _ACMP_CTRL_NOTRDYVAL_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */
+#define _ACMP_CTRL_NOTRDYVAL_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */
+#define ACMP_CTRL_NOTRDYVAL_DEFAULT (_ACMP_CTRL_NOTRDYVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_NOTRDYVAL_LOW (_ACMP_CTRL_NOTRDYVAL_LOW << 0) /**< Shifted mode LOW for ACMP_CTRL */
+#define ACMP_CTRL_NOTRDYVAL_HIGH (_ACMP_CTRL_NOTRDYVAL_HIGH << 0) /**< Shifted mode HIGH for ACMP_CTRL */
+#define ACMP_CTRL_GPIOINV (0x1UL << 1) /**< Comparator GPIO Output Invert */
+#define _ACMP_CTRL_GPIOINV_SHIFT 1 /**< Shift value for ACMP_GPIOINV */
+#define _ACMP_CTRL_GPIOINV_MASK 0x2UL /**< Bit mask for ACMP_GPIOINV */
+#define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
+#define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL /**< Mode NOTINV for ACMP_CTRL */
+#define _ACMP_CTRL_GPIOINV_INV 0x00000001UL /**< Mode INV for ACMP_CTRL */
+#define ACMP_CTRL_GPIOINV_DEFAULT (_ACMP_CTRL_GPIOINV_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_CTRL */
+#define ACMP_CTRL_GPIOINV_NOTINV (_ACMP_CTRL_GPIOINV_NOTINV << 1) /**< Shifted mode NOTINV for ACMP_CTRL */
+#define ACMP_CTRL_GPIOINV_INV (_ACMP_CTRL_GPIOINV_INV << 1) /**< Shifted mode INV for ACMP_CTRL */
+
+/* Bit fields for ACMP INPUTCTRL */
+#define _ACMP_INPUTCTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_MASK 0x703FFFFFUL /**< Mask for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_SHIFT 0 /**< Shift value for ACMP_POSSEL */
+#define _ACMP_INPUTCTRL_POSSEL_MASK 0xFFUL /**< Bit mask for ACMP_POSSEL */
+#define _ACMP_INPUTCTRL_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_VSS 0x00000000UL /**< Mode VSS for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD 0x00000010UL /**< Mode VREFDIVAVDD for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP 0x00000011UL /**< Mode VREFDIVAVDDLP for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 0x00000012UL /**< Mode VREFDIV1V25 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP 0x00000013UL /**< Mode VREFDIV1V25LP for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 0x00000014UL /**< Mode VREFDIV2V5 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP 0x00000015UL /**< Mode VREFDIV2V5LP for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 0x00000020UL /**< Mode VSENSE01DIV4 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP 0x00000021UL /**< Mode VSENSE01DIV4LP for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 0x00000022UL /**< Mode VSENSE11DIV4 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP 0x00000023UL /**< Mode VSENSE11DIV4LP for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_VDAC0OUT1 0x00000041UL /**< Mode VDAC0OUT1 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_VDAC1OUT1 0x00000043UL /**< Mode VDAC1OUT1 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_EXTPA 0x00000050UL /**< Mode EXTPA for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_EXTPB 0x00000051UL /**< Mode EXTPB for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_EXTPC 0x00000052UL /**< Mode EXTPC for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_EXTPD 0x00000053UL /**< Mode EXTPD for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PA0 0x00000080UL /**< Mode PA0 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PA1 0x00000081UL /**< Mode PA1 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PA2 0x00000082UL /**< Mode PA2 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PA3 0x00000083UL /**< Mode PA3 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PA4 0x00000084UL /**< Mode PA4 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PA5 0x00000085UL /**< Mode PA5 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PA6 0x00000086UL /**< Mode PA6 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PA7 0x00000087UL /**< Mode PA7 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PA8 0x00000088UL /**< Mode PA8 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PA9 0x00000089UL /**< Mode PA9 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PA10 0x0000008AUL /**< Mode PA10 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PA11 0x0000008BUL /**< Mode PA11 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PA12 0x0000008CUL /**< Mode PA12 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PA13 0x0000008DUL /**< Mode PA13 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PA14 0x0000008EUL /**< Mode PA14 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PA15 0x0000008FUL /**< Mode PA15 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PB0 0x00000090UL /**< Mode PB0 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PB1 0x00000091UL /**< Mode PB1 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PB2 0x00000092UL /**< Mode PB2 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PB3 0x00000093UL /**< Mode PB3 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PB4 0x00000094UL /**< Mode PB4 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PB5 0x00000095UL /**< Mode PB5 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PB6 0x00000096UL /**< Mode PB6 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PB7 0x00000097UL /**< Mode PB7 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PB8 0x00000098UL /**< Mode PB8 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PB9 0x00000099UL /**< Mode PB9 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PB10 0x0000009AUL /**< Mode PB10 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PB11 0x0000009BUL /**< Mode PB11 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PB12 0x0000009CUL /**< Mode PB12 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PB13 0x0000009DUL /**< Mode PB13 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PB14 0x0000009EUL /**< Mode PB14 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PB15 0x0000009FUL /**< Mode PB15 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PC0 0x000000A0UL /**< Mode PC0 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PC1 0x000000A1UL /**< Mode PC1 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PC2 0x000000A2UL /**< Mode PC2 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PC3 0x000000A3UL /**< Mode PC3 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PC4 0x000000A4UL /**< Mode PC4 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PC5 0x000000A5UL /**< Mode PC5 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PC6 0x000000A6UL /**< Mode PC6 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PC7 0x000000A7UL /**< Mode PC7 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PC8 0x000000A8UL /**< Mode PC8 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PC9 0x000000A9UL /**< Mode PC9 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PC10 0x000000AAUL /**< Mode PC10 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PC11 0x000000ABUL /**< Mode PC11 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PC12 0x000000ACUL /**< Mode PC12 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PC13 0x000000ADUL /**< Mode PC13 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PC14 0x000000AEUL /**< Mode PC14 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PC15 0x000000AFUL /**< Mode PC15 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PD0 0x000000B0UL /**< Mode PD0 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PD1 0x000000B1UL /**< Mode PD1 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PD2 0x000000B2UL /**< Mode PD2 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PD3 0x000000B3UL /**< Mode PD3 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PD4 0x000000B4UL /**< Mode PD4 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PD5 0x000000B5UL /**< Mode PD5 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PD6 0x000000B6UL /**< Mode PD6 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PD7 0x000000B7UL /**< Mode PD7 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PD8 0x000000B8UL /**< Mode PD8 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PD9 0x000000B9UL /**< Mode PD9 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PD10 0x000000BAUL /**< Mode PD10 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PD11 0x000000BBUL /**< Mode PD11 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PD12 0x000000BCUL /**< Mode PD12 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PD13 0x000000BDUL /**< Mode PD13 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PD14 0x000000BEUL /**< Mode PD14 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_POSSEL_PD15 0x000000BFUL /**< Mode PD15 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_DEFAULT (_ACMP_INPUTCTRL_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_VSS (_ACMP_INPUTCTRL_POSSEL_VSS << 0) /**< Shifted mode VSS for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD (_ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD << 0) /**< Shifted mode VREFDIVAVDD for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP (_ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP << 0) /**< Shifted mode VREFDIVAVDDLP for ACMP_INPUTCTRL*/
+#define ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 (_ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 << 0) /**< Shifted mode VREFDIV1V25 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP (_ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP << 0) /**< Shifted mode VREFDIV1V25LP for ACMP_INPUTCTRL*/
+#define ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 (_ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 << 0) /**< Shifted mode VREFDIV2V5 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP (_ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP << 0) /**< Shifted mode VREFDIV2V5LP for ACMP_INPUTCTRL*/
+#define ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 (_ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 << 0) /**< Shifted mode VSENSE01DIV4 for ACMP_INPUTCTRL*/
+#define ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP (_ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP << 0) /**< Shifted mode VSENSE01DIV4LP for ACMP_INPUTCTRL*/
+#define ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 (_ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 << 0) /**< Shifted mode VSENSE11DIV4 for ACMP_INPUTCTRL*/
+#define ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP (_ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP << 0) /**< Shifted mode VSENSE11DIV4LP for ACMP_INPUTCTRL*/
+#define ACMP_INPUTCTRL_POSSEL_VDAC0OUT1 (_ACMP_INPUTCTRL_POSSEL_VDAC0OUT1 << 0) /**< Shifted mode VDAC0OUT1 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_VDAC1OUT1 (_ACMP_INPUTCTRL_POSSEL_VDAC1OUT1 << 0) /**< Shifted mode VDAC1OUT1 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_EXTPA (_ACMP_INPUTCTRL_POSSEL_EXTPA << 0) /**< Shifted mode EXTPA for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_EXTPB (_ACMP_INPUTCTRL_POSSEL_EXTPB << 0) /**< Shifted mode EXTPB for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_EXTPC (_ACMP_INPUTCTRL_POSSEL_EXTPC << 0) /**< Shifted mode EXTPC for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_EXTPD (_ACMP_INPUTCTRL_POSSEL_EXTPD << 0) /**< Shifted mode EXTPD for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PA0 (_ACMP_INPUTCTRL_POSSEL_PA0 << 0) /**< Shifted mode PA0 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PA1 (_ACMP_INPUTCTRL_POSSEL_PA1 << 0) /**< Shifted mode PA1 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PA2 (_ACMP_INPUTCTRL_POSSEL_PA2 << 0) /**< Shifted mode PA2 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PA3 (_ACMP_INPUTCTRL_POSSEL_PA3 << 0) /**< Shifted mode PA3 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PA4 (_ACMP_INPUTCTRL_POSSEL_PA4 << 0) /**< Shifted mode PA4 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PA5 (_ACMP_INPUTCTRL_POSSEL_PA5 << 0) /**< Shifted mode PA5 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PA6 (_ACMP_INPUTCTRL_POSSEL_PA6 << 0) /**< Shifted mode PA6 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PA7 (_ACMP_INPUTCTRL_POSSEL_PA7 << 0) /**< Shifted mode PA7 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PA8 (_ACMP_INPUTCTRL_POSSEL_PA8 << 0) /**< Shifted mode PA8 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PA9 (_ACMP_INPUTCTRL_POSSEL_PA9 << 0) /**< Shifted mode PA9 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PA10 (_ACMP_INPUTCTRL_POSSEL_PA10 << 0) /**< Shifted mode PA10 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PA11 (_ACMP_INPUTCTRL_POSSEL_PA11 << 0) /**< Shifted mode PA11 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PA12 (_ACMP_INPUTCTRL_POSSEL_PA12 << 0) /**< Shifted mode PA12 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PA13 (_ACMP_INPUTCTRL_POSSEL_PA13 << 0) /**< Shifted mode PA13 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PA14 (_ACMP_INPUTCTRL_POSSEL_PA14 << 0) /**< Shifted mode PA14 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PA15 (_ACMP_INPUTCTRL_POSSEL_PA15 << 0) /**< Shifted mode PA15 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PB0 (_ACMP_INPUTCTRL_POSSEL_PB0 << 0) /**< Shifted mode PB0 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PB1 (_ACMP_INPUTCTRL_POSSEL_PB1 << 0) /**< Shifted mode PB1 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PB2 (_ACMP_INPUTCTRL_POSSEL_PB2 << 0) /**< Shifted mode PB2 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PB3 (_ACMP_INPUTCTRL_POSSEL_PB3 << 0) /**< Shifted mode PB3 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PB4 (_ACMP_INPUTCTRL_POSSEL_PB4 << 0) /**< Shifted mode PB4 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PB5 (_ACMP_INPUTCTRL_POSSEL_PB5 << 0) /**< Shifted mode PB5 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PB6 (_ACMP_INPUTCTRL_POSSEL_PB6 << 0) /**< Shifted mode PB6 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PB7 (_ACMP_INPUTCTRL_POSSEL_PB7 << 0) /**< Shifted mode PB7 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PB8 (_ACMP_INPUTCTRL_POSSEL_PB8 << 0) /**< Shifted mode PB8 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PB9 (_ACMP_INPUTCTRL_POSSEL_PB9 << 0) /**< Shifted mode PB9 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PB10 (_ACMP_INPUTCTRL_POSSEL_PB10 << 0) /**< Shifted mode PB10 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PB11 (_ACMP_INPUTCTRL_POSSEL_PB11 << 0) /**< Shifted mode PB11 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PB12 (_ACMP_INPUTCTRL_POSSEL_PB12 << 0) /**< Shifted mode PB12 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PB13 (_ACMP_INPUTCTRL_POSSEL_PB13 << 0) /**< Shifted mode PB13 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PB14 (_ACMP_INPUTCTRL_POSSEL_PB14 << 0) /**< Shifted mode PB14 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PB15 (_ACMP_INPUTCTRL_POSSEL_PB15 << 0) /**< Shifted mode PB15 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PC0 (_ACMP_INPUTCTRL_POSSEL_PC0 << 0) /**< Shifted mode PC0 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PC1 (_ACMP_INPUTCTRL_POSSEL_PC1 << 0) /**< Shifted mode PC1 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PC2 (_ACMP_INPUTCTRL_POSSEL_PC2 << 0) /**< Shifted mode PC2 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PC3 (_ACMP_INPUTCTRL_POSSEL_PC3 << 0) /**< Shifted mode PC3 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PC4 (_ACMP_INPUTCTRL_POSSEL_PC4 << 0) /**< Shifted mode PC4 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PC5 (_ACMP_INPUTCTRL_POSSEL_PC5 << 0) /**< Shifted mode PC5 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PC6 (_ACMP_INPUTCTRL_POSSEL_PC6 << 0) /**< Shifted mode PC6 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PC7 (_ACMP_INPUTCTRL_POSSEL_PC7 << 0) /**< Shifted mode PC7 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PC8 (_ACMP_INPUTCTRL_POSSEL_PC8 << 0) /**< Shifted mode PC8 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PC9 (_ACMP_INPUTCTRL_POSSEL_PC9 << 0) /**< Shifted mode PC9 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PC10 (_ACMP_INPUTCTRL_POSSEL_PC10 << 0) /**< Shifted mode PC10 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PC11 (_ACMP_INPUTCTRL_POSSEL_PC11 << 0) /**< Shifted mode PC11 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PC12 (_ACMP_INPUTCTRL_POSSEL_PC12 << 0) /**< Shifted mode PC12 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PC13 (_ACMP_INPUTCTRL_POSSEL_PC13 << 0) /**< Shifted mode PC13 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PC14 (_ACMP_INPUTCTRL_POSSEL_PC14 << 0) /**< Shifted mode PC14 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PC15 (_ACMP_INPUTCTRL_POSSEL_PC15 << 0) /**< Shifted mode PC15 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PD0 (_ACMP_INPUTCTRL_POSSEL_PD0 << 0) /**< Shifted mode PD0 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PD1 (_ACMP_INPUTCTRL_POSSEL_PD1 << 0) /**< Shifted mode PD1 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PD2 (_ACMP_INPUTCTRL_POSSEL_PD2 << 0) /**< Shifted mode PD2 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PD3 (_ACMP_INPUTCTRL_POSSEL_PD3 << 0) /**< Shifted mode PD3 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PD4 (_ACMP_INPUTCTRL_POSSEL_PD4 << 0) /**< Shifted mode PD4 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PD5 (_ACMP_INPUTCTRL_POSSEL_PD5 << 0) /**< Shifted mode PD5 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PD6 (_ACMP_INPUTCTRL_POSSEL_PD6 << 0) /**< Shifted mode PD6 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PD7 (_ACMP_INPUTCTRL_POSSEL_PD7 << 0) /**< Shifted mode PD7 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PD8 (_ACMP_INPUTCTRL_POSSEL_PD8 << 0) /**< Shifted mode PD8 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PD9 (_ACMP_INPUTCTRL_POSSEL_PD9 << 0) /**< Shifted mode PD9 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PD10 (_ACMP_INPUTCTRL_POSSEL_PD10 << 0) /**< Shifted mode PD10 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PD11 (_ACMP_INPUTCTRL_POSSEL_PD11 << 0) /**< Shifted mode PD11 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PD12 (_ACMP_INPUTCTRL_POSSEL_PD12 << 0) /**< Shifted mode PD12 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PD13 (_ACMP_INPUTCTRL_POSSEL_PD13 << 0) /**< Shifted mode PD13 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PD14 (_ACMP_INPUTCTRL_POSSEL_PD14 << 0) /**< Shifted mode PD14 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_POSSEL_PD15 (_ACMP_INPUTCTRL_POSSEL_PD15 << 0) /**< Shifted mode PD15 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_SHIFT 8 /**< Shift value for ACMP_NEGSEL */
+#define _ACMP_INPUTCTRL_NEGSEL_MASK 0xFF00UL /**< Bit mask for ACMP_NEGSEL */
+#define _ACMP_INPUTCTRL_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_VSS 0x00000000UL /**< Mode VSS for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD 0x00000010UL /**< Mode VREFDIVAVDD for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP 0x00000011UL /**< Mode VREFDIVAVDDLP for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 0x00000012UL /**< Mode VREFDIV1V25 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP 0x00000013UL /**< Mode VREFDIV1V25LP for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 0x00000014UL /**< Mode VREFDIV2V5 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP 0x00000015UL /**< Mode VREFDIV2V5LP for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 0x00000020UL /**< Mode VSENSE01DIV4 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP 0x00000021UL /**< Mode VSENSE01DIV4LP for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 0x00000022UL /**< Mode VSENSE11DIV4 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP 0x00000023UL /**< Mode VSENSE11DIV4LP for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_CAPSENSE 0x00000030UL /**< Mode CAPSENSE for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_VDAC0OUT0 0x00000040UL /**< Mode VDAC0OUT0 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_VDAC1OUT0 0x00000042UL /**< Mode VDAC1OUT0 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PA0 0x00000080UL /**< Mode PA0 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PA1 0x00000081UL /**< Mode PA1 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PA2 0x00000082UL /**< Mode PA2 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PA3 0x00000083UL /**< Mode PA3 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PA4 0x00000084UL /**< Mode PA4 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PA5 0x00000085UL /**< Mode PA5 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PA6 0x00000086UL /**< Mode PA6 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PA7 0x00000087UL /**< Mode PA7 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PA8 0x00000088UL /**< Mode PA8 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PA9 0x00000089UL /**< Mode PA9 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PA10 0x0000008AUL /**< Mode PA10 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PA11 0x0000008BUL /**< Mode PA11 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PA12 0x0000008CUL /**< Mode PA12 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PA13 0x0000008DUL /**< Mode PA13 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PA14 0x0000008EUL /**< Mode PA14 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PA15 0x0000008FUL /**< Mode PA15 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PB0 0x00000090UL /**< Mode PB0 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PB1 0x00000091UL /**< Mode PB1 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PB2 0x00000092UL /**< Mode PB2 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PB3 0x00000093UL /**< Mode PB3 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PB4 0x00000094UL /**< Mode PB4 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PB5 0x00000095UL /**< Mode PB5 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PB6 0x00000096UL /**< Mode PB6 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PB7 0x00000097UL /**< Mode PB7 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PB8 0x00000098UL /**< Mode PB8 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PB9 0x00000099UL /**< Mode PB9 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PB10 0x0000009AUL /**< Mode PB10 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PB11 0x0000009BUL /**< Mode PB11 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PB12 0x0000009CUL /**< Mode PB12 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PB13 0x0000009DUL /**< Mode PB13 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PB14 0x0000009EUL /**< Mode PB14 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PB15 0x0000009FUL /**< Mode PB15 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PC0 0x000000A0UL /**< Mode PC0 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PC1 0x000000A1UL /**< Mode PC1 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PC2 0x000000A2UL /**< Mode PC2 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PC3 0x000000A3UL /**< Mode PC3 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PC4 0x000000A4UL /**< Mode PC4 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PC5 0x000000A5UL /**< Mode PC5 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PC6 0x000000A6UL /**< Mode PC6 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PC7 0x000000A7UL /**< Mode PC7 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PC8 0x000000A8UL /**< Mode PC8 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PC9 0x000000A9UL /**< Mode PC9 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PC10 0x000000AAUL /**< Mode PC10 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PC11 0x000000ABUL /**< Mode PC11 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PC12 0x000000ACUL /**< Mode PC12 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PC13 0x000000ADUL /**< Mode PC13 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PC14 0x000000AEUL /**< Mode PC14 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PC15 0x000000AFUL /**< Mode PC15 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PD0 0x000000B0UL /**< Mode PD0 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PD1 0x000000B1UL /**< Mode PD1 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PD2 0x000000B2UL /**< Mode PD2 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PD3 0x000000B3UL /**< Mode PD3 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PD4 0x000000B4UL /**< Mode PD4 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PD5 0x000000B5UL /**< Mode PD5 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PD6 0x000000B6UL /**< Mode PD6 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PD7 0x000000B7UL /**< Mode PD7 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PD8 0x000000B8UL /**< Mode PD8 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PD9 0x000000B9UL /**< Mode PD9 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PD10 0x000000BAUL /**< Mode PD10 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PD11 0x000000BBUL /**< Mode PD11 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PD12 0x000000BCUL /**< Mode PD12 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PD13 0x000000BDUL /**< Mode PD13 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PD14 0x000000BEUL /**< Mode PD14 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_NEGSEL_PD15 0x000000BFUL /**< Mode PD15 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_DEFAULT (_ACMP_INPUTCTRL_NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_VSS (_ACMP_INPUTCTRL_NEGSEL_VSS << 8) /**< Shifted mode VSS for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD (_ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD << 8) /**< Shifted mode VREFDIVAVDD for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP (_ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP << 8) /**< Shifted mode VREFDIVAVDDLP for ACMP_INPUTCTRL*/
+#define ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 (_ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 << 8) /**< Shifted mode VREFDIV1V25 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP (_ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP << 8) /**< Shifted mode VREFDIV1V25LP for ACMP_INPUTCTRL*/
+#define ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 (_ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 << 8) /**< Shifted mode VREFDIV2V5 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP (_ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP << 8) /**< Shifted mode VREFDIV2V5LP for ACMP_INPUTCTRL*/
+#define ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 (_ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 << 8) /**< Shifted mode VSENSE01DIV4 for ACMP_INPUTCTRL*/
+#define ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP (_ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP << 8) /**< Shifted mode VSENSE01DIV4LP for ACMP_INPUTCTRL*/
+#define ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 (_ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 << 8) /**< Shifted mode VSENSE11DIV4 for ACMP_INPUTCTRL*/
+#define ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP (_ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP << 8) /**< Shifted mode VSENSE11DIV4LP for ACMP_INPUTCTRL*/
+#define ACMP_INPUTCTRL_NEGSEL_CAPSENSE (_ACMP_INPUTCTRL_NEGSEL_CAPSENSE << 8) /**< Shifted mode CAPSENSE for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_VDAC0OUT0 (_ACMP_INPUTCTRL_NEGSEL_VDAC0OUT0 << 8) /**< Shifted mode VDAC0OUT0 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_VDAC1OUT0 (_ACMP_INPUTCTRL_NEGSEL_VDAC1OUT0 << 8) /**< Shifted mode VDAC1OUT0 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PA0 (_ACMP_INPUTCTRL_NEGSEL_PA0 << 8) /**< Shifted mode PA0 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PA1 (_ACMP_INPUTCTRL_NEGSEL_PA1 << 8) /**< Shifted mode PA1 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PA2 (_ACMP_INPUTCTRL_NEGSEL_PA2 << 8) /**< Shifted mode PA2 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PA3 (_ACMP_INPUTCTRL_NEGSEL_PA3 << 8) /**< Shifted mode PA3 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PA4 (_ACMP_INPUTCTRL_NEGSEL_PA4 << 8) /**< Shifted mode PA4 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PA5 (_ACMP_INPUTCTRL_NEGSEL_PA5 << 8) /**< Shifted mode PA5 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PA6 (_ACMP_INPUTCTRL_NEGSEL_PA6 << 8) /**< Shifted mode PA6 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PA7 (_ACMP_INPUTCTRL_NEGSEL_PA7 << 8) /**< Shifted mode PA7 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PA8 (_ACMP_INPUTCTRL_NEGSEL_PA8 << 8) /**< Shifted mode PA8 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PA9 (_ACMP_INPUTCTRL_NEGSEL_PA9 << 8) /**< Shifted mode PA9 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PA10 (_ACMP_INPUTCTRL_NEGSEL_PA10 << 8) /**< Shifted mode PA10 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PA11 (_ACMP_INPUTCTRL_NEGSEL_PA11 << 8) /**< Shifted mode PA11 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PA12 (_ACMP_INPUTCTRL_NEGSEL_PA12 << 8) /**< Shifted mode PA12 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PA13 (_ACMP_INPUTCTRL_NEGSEL_PA13 << 8) /**< Shifted mode PA13 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PA14 (_ACMP_INPUTCTRL_NEGSEL_PA14 << 8) /**< Shifted mode PA14 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PA15 (_ACMP_INPUTCTRL_NEGSEL_PA15 << 8) /**< Shifted mode PA15 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PB0 (_ACMP_INPUTCTRL_NEGSEL_PB0 << 8) /**< Shifted mode PB0 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PB1 (_ACMP_INPUTCTRL_NEGSEL_PB1 << 8) /**< Shifted mode PB1 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PB2 (_ACMP_INPUTCTRL_NEGSEL_PB2 << 8) /**< Shifted mode PB2 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PB3 (_ACMP_INPUTCTRL_NEGSEL_PB3 << 8) /**< Shifted mode PB3 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PB4 (_ACMP_INPUTCTRL_NEGSEL_PB4 << 8) /**< Shifted mode PB4 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PB5 (_ACMP_INPUTCTRL_NEGSEL_PB5 << 8) /**< Shifted mode PB5 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PB6 (_ACMP_INPUTCTRL_NEGSEL_PB6 << 8) /**< Shifted mode PB6 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PB7 (_ACMP_INPUTCTRL_NEGSEL_PB7 << 8) /**< Shifted mode PB7 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PB8 (_ACMP_INPUTCTRL_NEGSEL_PB8 << 8) /**< Shifted mode PB8 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PB9 (_ACMP_INPUTCTRL_NEGSEL_PB9 << 8) /**< Shifted mode PB9 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PB10 (_ACMP_INPUTCTRL_NEGSEL_PB10 << 8) /**< Shifted mode PB10 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PB11 (_ACMP_INPUTCTRL_NEGSEL_PB11 << 8) /**< Shifted mode PB11 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PB12 (_ACMP_INPUTCTRL_NEGSEL_PB12 << 8) /**< Shifted mode PB12 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PB13 (_ACMP_INPUTCTRL_NEGSEL_PB13 << 8) /**< Shifted mode PB13 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PB14 (_ACMP_INPUTCTRL_NEGSEL_PB14 << 8) /**< Shifted mode PB14 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PB15 (_ACMP_INPUTCTRL_NEGSEL_PB15 << 8) /**< Shifted mode PB15 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PC0 (_ACMP_INPUTCTRL_NEGSEL_PC0 << 8) /**< Shifted mode PC0 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PC1 (_ACMP_INPUTCTRL_NEGSEL_PC1 << 8) /**< Shifted mode PC1 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PC2 (_ACMP_INPUTCTRL_NEGSEL_PC2 << 8) /**< Shifted mode PC2 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PC3 (_ACMP_INPUTCTRL_NEGSEL_PC3 << 8) /**< Shifted mode PC3 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PC4 (_ACMP_INPUTCTRL_NEGSEL_PC4 << 8) /**< Shifted mode PC4 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PC5 (_ACMP_INPUTCTRL_NEGSEL_PC5 << 8) /**< Shifted mode PC5 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PC6 (_ACMP_INPUTCTRL_NEGSEL_PC6 << 8) /**< Shifted mode PC6 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PC7 (_ACMP_INPUTCTRL_NEGSEL_PC7 << 8) /**< Shifted mode PC7 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PC8 (_ACMP_INPUTCTRL_NEGSEL_PC8 << 8) /**< Shifted mode PC8 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PC9 (_ACMP_INPUTCTRL_NEGSEL_PC9 << 8) /**< Shifted mode PC9 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PC10 (_ACMP_INPUTCTRL_NEGSEL_PC10 << 8) /**< Shifted mode PC10 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PC11 (_ACMP_INPUTCTRL_NEGSEL_PC11 << 8) /**< Shifted mode PC11 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PC12 (_ACMP_INPUTCTRL_NEGSEL_PC12 << 8) /**< Shifted mode PC12 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PC13 (_ACMP_INPUTCTRL_NEGSEL_PC13 << 8) /**< Shifted mode PC13 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PC14 (_ACMP_INPUTCTRL_NEGSEL_PC14 << 8) /**< Shifted mode PC14 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PC15 (_ACMP_INPUTCTRL_NEGSEL_PC15 << 8) /**< Shifted mode PC15 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PD0 (_ACMP_INPUTCTRL_NEGSEL_PD0 << 8) /**< Shifted mode PD0 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PD1 (_ACMP_INPUTCTRL_NEGSEL_PD1 << 8) /**< Shifted mode PD1 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PD2 (_ACMP_INPUTCTRL_NEGSEL_PD2 << 8) /**< Shifted mode PD2 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PD3 (_ACMP_INPUTCTRL_NEGSEL_PD3 << 8) /**< Shifted mode PD3 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PD4 (_ACMP_INPUTCTRL_NEGSEL_PD4 << 8) /**< Shifted mode PD4 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PD5 (_ACMP_INPUTCTRL_NEGSEL_PD5 << 8) /**< Shifted mode PD5 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PD6 (_ACMP_INPUTCTRL_NEGSEL_PD6 << 8) /**< Shifted mode PD6 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PD7 (_ACMP_INPUTCTRL_NEGSEL_PD7 << 8) /**< Shifted mode PD7 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PD8 (_ACMP_INPUTCTRL_NEGSEL_PD8 << 8) /**< Shifted mode PD8 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PD9 (_ACMP_INPUTCTRL_NEGSEL_PD9 << 8) /**< Shifted mode PD9 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PD10 (_ACMP_INPUTCTRL_NEGSEL_PD10 << 8) /**< Shifted mode PD10 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PD11 (_ACMP_INPUTCTRL_NEGSEL_PD11 << 8) /**< Shifted mode PD11 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PD12 (_ACMP_INPUTCTRL_NEGSEL_PD12 << 8) /**< Shifted mode PD12 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PD13 (_ACMP_INPUTCTRL_NEGSEL_PD13 << 8) /**< Shifted mode PD13 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PD14 (_ACMP_INPUTCTRL_NEGSEL_PD14 << 8) /**< Shifted mode PD14 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_NEGSEL_PD15 (_ACMP_INPUTCTRL_NEGSEL_PD15 << 8) /**< Shifted mode PD15 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_VREFDIV_SHIFT 16 /**< Shift value for ACMP_VREFDIV */
+#define _ACMP_INPUTCTRL_VREFDIV_MASK 0x3F0000UL /**< Bit mask for ACMP_VREFDIV */
+#define _ACMP_INPUTCTRL_VREFDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_VREFDIV_DEFAULT (_ACMP_INPUTCTRL_VREFDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_CSRESSEL_SHIFT 28 /**< Shift value for ACMP_CSRESSEL */
+#define _ACMP_INPUTCTRL_CSRESSEL_MASK 0x70000000UL /**< Bit mask for ACMP_CSRESSEL */
+#define _ACMP_INPUTCTRL_CSRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_CSRESSEL_RES0 0x00000000UL /**< Mode RES0 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_CSRESSEL_RES1 0x00000001UL /**< Mode RES1 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_CSRESSEL_RES2 0x00000002UL /**< Mode RES2 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_CSRESSEL_RES3 0x00000003UL /**< Mode RES3 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_CSRESSEL_RES4 0x00000004UL /**< Mode RES4 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_CSRESSEL_RES5 0x00000005UL /**< Mode RES5 for ACMP_INPUTCTRL */
+#define _ACMP_INPUTCTRL_CSRESSEL_RES6 0x00000006UL /**< Mode RES6 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_CSRESSEL_DEFAULT (_ACMP_INPUTCTRL_CSRESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_CSRESSEL_RES0 (_ACMP_INPUTCTRL_CSRESSEL_RES0 << 28) /**< Shifted mode RES0 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_CSRESSEL_RES1 (_ACMP_INPUTCTRL_CSRESSEL_RES1 << 28) /**< Shifted mode RES1 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_CSRESSEL_RES2 (_ACMP_INPUTCTRL_CSRESSEL_RES2 << 28) /**< Shifted mode RES2 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_CSRESSEL_RES3 (_ACMP_INPUTCTRL_CSRESSEL_RES3 << 28) /**< Shifted mode RES3 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_CSRESSEL_RES4 (_ACMP_INPUTCTRL_CSRESSEL_RES4 << 28) /**< Shifted mode RES4 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_CSRESSEL_RES5 (_ACMP_INPUTCTRL_CSRESSEL_RES5 << 28) /**< Shifted mode RES5 for ACMP_INPUTCTRL */
+#define ACMP_INPUTCTRL_CSRESSEL_RES6 (_ACMP_INPUTCTRL_CSRESSEL_RES6 << 28) /**< Shifted mode RES6 for ACMP_INPUTCTRL */
+
+/* Bit fields for ACMP STATUS */
+#define _ACMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for ACMP_STATUS */
+#define _ACMP_STATUS_MASK 0x0000001DUL /**< Mask for ACMP_STATUS */
+#define ACMP_STATUS_ACMPOUT (0x1UL << 0) /**< Analog Comparator Output */
+#define _ACMP_STATUS_ACMPOUT_SHIFT 0 /**< Shift value for ACMP_ACMPOUT */
+#define _ACMP_STATUS_ACMPOUT_MASK 0x1UL /**< Bit mask for ACMP_ACMPOUT */
+#define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */
+#define ACMP_STATUS_ACMPOUT_DEFAULT (_ACMP_STATUS_ACMPOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_STATUS */
+#define ACMP_STATUS_ACMPRDY (0x1UL << 2) /**< Analog Comparator Ready */
+#define _ACMP_STATUS_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */
+#define _ACMP_STATUS_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */
+#define _ACMP_STATUS_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */
+#define ACMP_STATUS_ACMPRDY_DEFAULT (_ACMP_STATUS_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_STATUS */
+#define ACMP_STATUS_INPUTCONFLICT (0x1UL << 3) /**< INPUT conflict */
+#define _ACMP_STATUS_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */
+#define _ACMP_STATUS_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */
+#define _ACMP_STATUS_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */
+#define ACMP_STATUS_INPUTCONFLICT_DEFAULT (_ACMP_STATUS_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_STATUS */
+#define ACMP_STATUS_PORTALLOCERR (0x1UL << 4) /**< Port allocation error */
+#define _ACMP_STATUS_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */
+#define _ACMP_STATUS_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */
+#define _ACMP_STATUS_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */
+#define ACMP_STATUS_PORTALLOCERR_DEFAULT (_ACMP_STATUS_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_STATUS */
+
+/* Bit fields for ACMP IF */
+#define _ACMP_IF_RESETVALUE 0x00000000UL /**< Default value for ACMP_IF */
+#define _ACMP_IF_MASK 0x0000001FUL /**< Mask for ACMP_IF */
+#define ACMP_IF_RISE (0x1UL << 0) /**< Rising Edge Triggered Interrupt Flag */
+#define _ACMP_IF_RISE_SHIFT 0 /**< Shift value for ACMP_RISE */
+#define _ACMP_IF_RISE_MASK 0x1UL /**< Bit mask for ACMP_RISE */
+#define _ACMP_IF_RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */
+#define ACMP_IF_RISE_DEFAULT (_ACMP_IF_RISE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IF */
+#define ACMP_IF_FALL (0x1UL << 1) /**< Falling Edge Triggered Interrupt Flag */
+#define _ACMP_IF_FALL_SHIFT 1 /**< Shift value for ACMP_FALL */
+#define _ACMP_IF_FALL_MASK 0x2UL /**< Bit mask for ACMP_FALL */
+#define _ACMP_IF_FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */
+#define ACMP_IF_FALL_DEFAULT (_ACMP_IF_FALL_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IF */
+#define ACMP_IF_ACMPRDY (0x1UL << 2) /**< ACMP ready Interrupt flag */
+#define _ACMP_IF_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */
+#define _ACMP_IF_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */
+#define _ACMP_IF_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */
+#define ACMP_IF_ACMPRDY_DEFAULT (_ACMP_IF_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IF */
+#define ACMP_IF_INPUTCONFLICT (0x1UL << 3) /**< Input conflict */
+#define _ACMP_IF_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */
+#define _ACMP_IF_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */
+#define _ACMP_IF_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */
+#define ACMP_IF_INPUTCONFLICT_DEFAULT (_ACMP_IF_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_IF */
+#define ACMP_IF_PORTALLOCERR (0x1UL << 4) /**< Port allocation error */
+#define _ACMP_IF_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */
+#define _ACMP_IF_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */
+#define _ACMP_IF_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */
+#define ACMP_IF_PORTALLOCERR_DEFAULT (_ACMP_IF_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_IF */
+
+/* Bit fields for ACMP IEN */
+#define _ACMP_IEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_IEN */
+#define _ACMP_IEN_MASK 0x0000001FUL /**< Mask for ACMP_IEN */
+#define ACMP_IEN_RISE (0x1UL << 0) /**< Rising edge interrupt enable */
+#define _ACMP_IEN_RISE_SHIFT 0 /**< Shift value for ACMP_RISE */
+#define _ACMP_IEN_RISE_MASK 0x1UL /**< Bit mask for ACMP_RISE */
+#define _ACMP_IEN_RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */
+#define ACMP_IEN_RISE_DEFAULT (_ACMP_IEN_RISE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IEN */
+#define ACMP_IEN_FALL (0x1UL << 1) /**< Falling edge interrupt enable */
+#define _ACMP_IEN_FALL_SHIFT 1 /**< Shift value for ACMP_FALL */
+#define _ACMP_IEN_FALL_MASK 0x2UL /**< Bit mask for ACMP_FALL */
+#define _ACMP_IEN_FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */
+#define ACMP_IEN_FALL_DEFAULT (_ACMP_IEN_FALL_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IEN */
+#define ACMP_IEN_ACMPRDY (0x1UL << 2) /**< ACMP ready interrupt enable */
+#define _ACMP_IEN_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */
+#define _ACMP_IEN_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */
+#define _ACMP_IEN_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */
+#define ACMP_IEN_ACMPRDY_DEFAULT (_ACMP_IEN_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IEN */
+#define ACMP_IEN_INPUTCONFLICT (0x1UL << 3) /**< Input conflict interrupt enable */
+#define _ACMP_IEN_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */
+#define _ACMP_IEN_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */
+#define _ACMP_IEN_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */
+#define ACMP_IEN_INPUTCONFLICT_DEFAULT (_ACMP_IEN_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_IEN */
+#define ACMP_IEN_PORTALLOCERR (0x1UL << 4) /**< Port allocation error interrupt enable */
+#define _ACMP_IEN_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */
+#define _ACMP_IEN_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */
+#define _ACMP_IEN_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */
+#define ACMP_IEN_PORTALLOCERR_DEFAULT (_ACMP_IEN_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_IEN */
+
+/* Bit fields for ACMP SYNCBUSY */
+#define _ACMP_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for ACMP_SYNCBUSY */
+#define _ACMP_SYNCBUSY_MASK 0x00000001UL /**< Mask for ACMP_SYNCBUSY */
+#define ACMP_SYNCBUSY_INPUTCTRL (0x1UL << 0) /**< Syncbusy for INPUTCTRL */
+#define _ACMP_SYNCBUSY_INPUTCTRL_SHIFT 0 /**< Shift value for ACMP_INPUTCTRL */
+#define _ACMP_SYNCBUSY_INPUTCTRL_MASK 0x1UL /**< Bit mask for ACMP_INPUTCTRL */
+#define _ACMP_SYNCBUSY_INPUTCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SYNCBUSY */
+#define ACMP_SYNCBUSY_INPUTCTRL_DEFAULT (_ACMP_SYNCBUSY_INPUTCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_SYNCBUSY */
+
+/** @} End of group EFR32MG24_ACMP_BitFields */
+/** @} End of group EFR32MG24_ACMP */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_ACMP_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_aes.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_aes.h
new file mode 100644
index 00000000..4927b6df
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_aes.h
@@ -0,0 +1,453 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 AES register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_AES_H
+#define EFR32MG24_AES_H
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_AES AES
+ * @{
+ * @brief EFR32MG24 AES Register Declaration.
+ *****************************************************************************/
+
+/** AES Register Declaration. */
+typedef struct {
+ __IOM uint32_t FETCHADDR; /**< Fetcher Address */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+ __IOM uint32_t FETCHLEN; /**< Fetcher Length */
+ __IOM uint32_t FETCHTAG; /**< Fetcher Tag */
+ __IOM uint32_t PUSHADDR; /**< Pusher Address */
+ uint32_t RESERVED1[1U]; /**< Reserved for future use */
+ __IOM uint32_t PUSHLEN; /**< Pusher Length */
+ __IOM uint32_t IEN; /**< Interrupt Enable */
+ uint32_t RESERVED2[2U]; /**< Reserved for future use */
+ __IM uint32_t IF; /**< Interrupt Flags */
+ uint32_t RESERVED3[1U]; /**< Reserved for future use */
+ __IOM uint32_t IF_CLR; /**< Interrupt status clear */
+ __IOM uint32_t CTRL; /**< Control register */
+ __IOM uint32_t CMD; /**< Command register */
+ __IM uint32_t STATUS; /**< Status register */
+ uint32_t RESERVED4[240U]; /**< Reserved for future use */
+ __IM uint32_t INCL_IPS_HW_CFG; /**< INCL_IPS_HW_CFG */
+ __IM uint32_t BA411E_HW_CFG_1; /**< BA411E_HW_CFG_1 */
+ __IM uint32_t BA411E_HW_CFG_2; /**< BA411E_HW_CFG_2 */
+ __IM uint32_t BA413_HW_CFG; /**< BA413_HW_CFG */
+ __IM uint32_t BA418_HW_CFG; /**< BA418_HW_CFG */
+ __IM uint32_t BA419_HW_CFG; /**< BA419_HW_CFG */
+} AES_TypeDef;
+/** @} End of group EFR32MG24_AES */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_AES
+ * @{
+ * @defgroup EFR32MG24_AES_BitFields AES Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for AES FETCHADDR */
+#define _AES_FETCHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHADDR */
+#define _AES_FETCHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHADDR */
+#define _AES_FETCHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */
+#define _AES_FETCHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */
+#define _AES_FETCHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHADDR */
+#define AES_FETCHADDR_ADDR_DEFAULT (_AES_FETCHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHADDR */
+
+/* Bit fields for AES FETCHLEN */
+#define _AES_FETCHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHLEN */
+#define _AES_FETCHLEN_MASK 0x3FFFFFFFUL /**< Mask for AES_FETCHLEN */
+#define _AES_FETCHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */
+#define _AES_FETCHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */
+#define _AES_FETCHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */
+#define AES_FETCHLEN_LENGTH_DEFAULT (_AES_FETCHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHLEN */
+#define AES_FETCHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */
+#define _AES_FETCHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */
+#define _AES_FETCHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */
+#define _AES_FETCHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */
+#define AES_FETCHLEN_CONSTADDR_DEFAULT (_AES_FETCHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_FETCHLEN */
+#define AES_FETCHLEN_REALIGN (0x1UL << 29) /**< Realign lengh */
+#define _AES_FETCHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */
+#define _AES_FETCHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */
+#define _AES_FETCHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */
+#define AES_FETCHLEN_REALIGN_DEFAULT (_AES_FETCHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_FETCHLEN */
+
+/* Bit fields for AES FETCHTAG */
+#define _AES_FETCHTAG_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHTAG */
+#define _AES_FETCHTAG_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHTAG */
+#define _AES_FETCHTAG_TAG_SHIFT 0 /**< Shift value for AES_TAG */
+#define _AES_FETCHTAG_TAG_MASK 0xFFFFFFFFUL /**< Bit mask for AES_TAG */
+#define _AES_FETCHTAG_TAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHTAG */
+#define AES_FETCHTAG_TAG_DEFAULT (_AES_FETCHTAG_TAG_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHTAG */
+
+/* Bit fields for AES PUSHADDR */
+#define _AES_PUSHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHADDR */
+#define _AES_PUSHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_PUSHADDR */
+#define _AES_PUSHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */
+#define _AES_PUSHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */
+#define _AES_PUSHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHADDR */
+#define AES_PUSHADDR_ADDR_DEFAULT (_AES_PUSHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHADDR */
+
+/* Bit fields for AES PUSHLEN */
+#define _AES_PUSHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHLEN */
+#define _AES_PUSHLEN_MASK 0x7FFFFFFFUL /**< Mask for AES_PUSHLEN */
+#define _AES_PUSHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */
+#define _AES_PUSHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */
+#define _AES_PUSHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */
+#define AES_PUSHLEN_LENGTH_DEFAULT (_AES_PUSHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHLEN */
+#define AES_PUSHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */
+#define _AES_PUSHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */
+#define _AES_PUSHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */
+#define _AES_PUSHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */
+#define AES_PUSHLEN_CONSTADDR_DEFAULT (_AES_PUSHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_PUSHLEN */
+#define AES_PUSHLEN_REALIGN (0x1UL << 29) /**< Realign length */
+#define _AES_PUSHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */
+#define _AES_PUSHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */
+#define _AES_PUSHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */
+#define AES_PUSHLEN_REALIGN_DEFAULT (_AES_PUSHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_PUSHLEN */
+#define AES_PUSHLEN_DISCARD (0x1UL << 30) /**< Discard data */
+#define _AES_PUSHLEN_DISCARD_SHIFT 30 /**< Shift value for AES_DISCARD */
+#define _AES_PUSHLEN_DISCARD_MASK 0x40000000UL /**< Bit mask for AES_DISCARD */
+#define _AES_PUSHLEN_DISCARD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */
+#define AES_PUSHLEN_DISCARD_DEFAULT (_AES_PUSHLEN_DISCARD_DEFAULT << 30) /**< Shifted mode DEFAULT for AES_PUSHLEN */
+
+/* Bit fields for AES IEN */
+#define _AES_IEN_RESETVALUE 0x00000000UL /**< Default value for AES_IEN */
+#define _AES_IEN_MASK 0x0000003FUL /**< Mask for AES_IEN */
+#define AES_IEN_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt enable */
+#define _AES_IEN_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */
+#define _AES_IEN_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */
+#define _AES_IEN_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */
+#define AES_IEN_FETCHERENDOFBLOCK_DEFAULT (_AES_IEN_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IEN */
+#define AES_IEN_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt enable */
+#define _AES_IEN_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */
+#define _AES_IEN_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */
+#define _AES_IEN_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */
+#define AES_IEN_FETCHERSTOPPED_DEFAULT (_AES_IEN_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IEN */
+#define AES_IEN_FETCHERERROR (0x1UL << 2) /**< Error interrupt enable */
+#define _AES_IEN_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */
+#define _AES_IEN_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */
+#define _AES_IEN_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */
+#define AES_IEN_FETCHERERROR_DEFAULT (_AES_IEN_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IEN */
+#define AES_IEN_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt enable */
+#define _AES_IEN_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */
+#define _AES_IEN_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */
+#define _AES_IEN_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */
+#define AES_IEN_PUSHERENDOFBLOCK_DEFAULT (_AES_IEN_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IEN */
+#define AES_IEN_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt enable */
+#define _AES_IEN_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */
+#define _AES_IEN_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */
+#define _AES_IEN_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */
+#define AES_IEN_PUSHERSTOPPED_DEFAULT (_AES_IEN_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IEN */
+#define AES_IEN_PUSHERERROR (0x1UL << 5) /**< Error interrupt enable */
+#define _AES_IEN_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */
+#define _AES_IEN_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */
+#define _AES_IEN_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */
+#define AES_IEN_PUSHERERROR_DEFAULT (_AES_IEN_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IEN */
+
+/* Bit fields for AES IF */
+#define _AES_IF_RESETVALUE 0x00000000UL /**< Default value for AES_IF */
+#define _AES_IF_MASK 0x0000003FUL /**< Mask for AES_IF */
+#define AES_IF_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag */
+#define _AES_IF_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */
+#define _AES_IF_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */
+#define _AES_IF_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */
+#define AES_IF_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF */
+#define AES_IF_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag */
+#define _AES_IF_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */
+#define _AES_IF_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */
+#define _AES_IF_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */
+#define AES_IF_FETCHERSTOPPED_DEFAULT (_AES_IF_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF */
+#define AES_IF_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag */
+#define _AES_IF_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */
+#define _AES_IF_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */
+#define _AES_IF_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */
+#define AES_IF_FETCHERERROR_DEFAULT (_AES_IF_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF */
+#define AES_IF_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt flag */
+#define _AES_IF_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */
+#define _AES_IF_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */
+#define _AES_IF_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */
+#define AES_IF_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF */
+#define AES_IF_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt flag */
+#define _AES_IF_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */
+#define _AES_IF_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */
+#define _AES_IF_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */
+#define AES_IF_PUSHERSTOPPED_DEFAULT (_AES_IF_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF */
+#define AES_IF_PUSHERERROR (0x1UL << 5) /**< Error interrupt flag */
+#define _AES_IF_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */
+#define _AES_IF_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */
+#define _AES_IF_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */
+#define AES_IF_PUSHERERROR_DEFAULT (_AES_IF_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF */
+
+/* Bit fields for AES IF_CLR */
+#define _AES_IF_CLR_RESETVALUE 0x00000000UL /**< Default value for AES_IF_CLR */
+#define _AES_IF_CLR_MASK 0x0000003FUL /**< Mask for AES_IF_CLR */
+#define AES_IF_CLR_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag clear */
+#define _AES_IF_CLR_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */
+#define _AES_IF_CLR_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */
+#define _AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */
+#define AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF_CLR */
+#define AES_IF_CLR_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag clear */
+#define _AES_IF_CLR_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */
+#define _AES_IF_CLR_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */
+#define _AES_IF_CLR_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */
+#define AES_IF_CLR_FETCHERSTOPPED_DEFAULT (_AES_IF_CLR_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF_CLR */
+#define AES_IF_CLR_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag clear */
+#define _AES_IF_CLR_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */
+#define _AES_IF_CLR_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */
+#define _AES_IF_CLR_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */
+#define AES_IF_CLR_FETCHERERROR_DEFAULT (_AES_IF_CLR_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF_CLR */
+#define AES_IF_CLR_PUSHERENDOFBLOCK (0x1UL << 3) /**< FETCHERENDOFBLOCKIFC */
+#define _AES_IF_CLR_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */
+#define _AES_IF_CLR_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */
+#define _AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */
+#define AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF_CLR */
+#define AES_IF_CLR_PUSHERSTOPPED (0x1UL << 4) /**< FETCHERSTOPPEDIFC */
+#define _AES_IF_CLR_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */
+#define _AES_IF_CLR_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */
+#define _AES_IF_CLR_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */
+#define AES_IF_CLR_PUSHERSTOPPED_DEFAULT (_AES_IF_CLR_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF_CLR */
+#define AES_IF_CLR_PUSHERERROR (0x1UL << 5) /**< FETCHERERRORIFC */
+#define _AES_IF_CLR_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */
+#define _AES_IF_CLR_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */
+#define _AES_IF_CLR_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */
+#define AES_IF_CLR_PUSHERERROR_DEFAULT (_AES_IF_CLR_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF_CLR */
+
+/* Bit fields for AES CTRL */
+#define _AES_CTRL_RESETVALUE 0x00000000UL /**< Default value for AES_CTRL */
+#define _AES_CTRL_MASK 0x0000001FUL /**< Mask for AES_CTRL */
+#define AES_CTRL_FETCHERSCATTERGATHER (0x1UL << 0) /**< Fetcher scatter/gather */
+#define _AES_CTRL_FETCHERSCATTERGATHER_SHIFT 0 /**< Shift value for AES_FETCHERSCATTERGATHER */
+#define _AES_CTRL_FETCHERSCATTERGATHER_MASK 0x1UL /**< Bit mask for AES_FETCHERSCATTERGATHER */
+#define _AES_CTRL_FETCHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
+#define AES_CTRL_FETCHERSCATTERGATHER_DEFAULT (_AES_CTRL_FETCHERSCATTERGATHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CTRL */
+#define AES_CTRL_PUSHERSCATTERGATHER (0x1UL << 1) /**< Pusher scatter/gather */
+#define _AES_CTRL_PUSHERSCATTERGATHER_SHIFT 1 /**< Shift value for AES_PUSHERSCATTERGATHER */
+#define _AES_CTRL_PUSHERSCATTERGATHER_MASK 0x2UL /**< Bit mask for AES_PUSHERSCATTERGATHER */
+#define _AES_CTRL_PUSHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
+#define AES_CTRL_PUSHERSCATTERGATHER_DEFAULT (_AES_CTRL_PUSHERSCATTERGATHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CTRL */
+#define AES_CTRL_STOPFETCHER (0x1UL << 2) /**< Stop fetcher */
+#define _AES_CTRL_STOPFETCHER_SHIFT 2 /**< Shift value for AES_STOPFETCHER */
+#define _AES_CTRL_STOPFETCHER_MASK 0x4UL /**< Bit mask for AES_STOPFETCHER */
+#define _AES_CTRL_STOPFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
+#define AES_CTRL_STOPFETCHER_DEFAULT (_AES_CTRL_STOPFETCHER_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_CTRL */
+#define AES_CTRL_STOPPUSHER (0x1UL << 3) /**< Stop pusher */
+#define _AES_CTRL_STOPPUSHER_SHIFT 3 /**< Shift value for AES_STOPPUSHER */
+#define _AES_CTRL_STOPPUSHER_MASK 0x8UL /**< Bit mask for AES_STOPPUSHER */
+#define _AES_CTRL_STOPPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
+#define AES_CTRL_STOPPUSHER_DEFAULT (_AES_CTRL_STOPPUSHER_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_CTRL */
+#define AES_CTRL_SWRESET (0x1UL << 4) /**< Software reset */
+#define _AES_CTRL_SWRESET_SHIFT 4 /**< Shift value for AES_SWRESET */
+#define _AES_CTRL_SWRESET_MASK 0x10UL /**< Bit mask for AES_SWRESET */
+#define _AES_CTRL_SWRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
+#define AES_CTRL_SWRESET_DEFAULT (_AES_CTRL_SWRESET_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_CTRL */
+
+/* Bit fields for AES CMD */
+#define _AES_CMD_RESETVALUE 0x00000000UL /**< Default value for AES_CMD */
+#define _AES_CMD_MASK 0x00000003UL /**< Mask for AES_CMD */
+#define AES_CMD_STARTFETCHER (0x1UL << 0) /**< Start fetch */
+#define _AES_CMD_STARTFETCHER_SHIFT 0 /**< Shift value for AES_STARTFETCHER */
+#define _AES_CMD_STARTFETCHER_MASK 0x1UL /**< Bit mask for AES_STARTFETCHER */
+#define _AES_CMD_STARTFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */
+#define AES_CMD_STARTFETCHER_DEFAULT (_AES_CMD_STARTFETCHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CMD */
+#define AES_CMD_STARTPUSHER (0x1UL << 1) /**< Start push */
+#define _AES_CMD_STARTPUSHER_SHIFT 1 /**< Shift value for AES_STARTPUSHER */
+#define _AES_CMD_STARTPUSHER_MASK 0x2UL /**< Bit mask for AES_STARTPUSHER */
+#define _AES_CMD_STARTPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */
+#define AES_CMD_STARTPUSHER_DEFAULT (_AES_CMD_STARTPUSHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CMD */
+
+/* Bit fields for AES STATUS */
+#define _AES_STATUS_RESETVALUE 0x00000000UL /**< Default value for AES_STATUS */
+#define _AES_STATUS_MASK 0xFFFF0073UL /**< Mask for AES_STATUS */
+#define AES_STATUS_FETCHERBSY (0x1UL << 0) /**< Fetcher busy */
+#define _AES_STATUS_FETCHERBSY_SHIFT 0 /**< Shift value for AES_FETCHERBSY */
+#define _AES_STATUS_FETCHERBSY_MASK 0x1UL /**< Bit mask for AES_FETCHERBSY */
+#define _AES_STATUS_FETCHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */
+#define AES_STATUS_FETCHERBSY_DEFAULT (_AES_STATUS_FETCHERBSY_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_STATUS */
+#define AES_STATUS_PUSHERBSY (0x1UL << 1) /**< Pusher busy */
+#define _AES_STATUS_PUSHERBSY_SHIFT 1 /**< Shift value for AES_PUSHERBSY */
+#define _AES_STATUS_PUSHERBSY_MASK 0x2UL /**< Bit mask for AES_PUSHERBSY */
+#define _AES_STATUS_PUSHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */
+#define AES_STATUS_PUSHERBSY_DEFAULT (_AES_STATUS_PUSHERBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_STATUS */
+#define AES_STATUS_NOTEMPTY (0x1UL << 4) /**< Not empty flag from input FIFO (fetcher) */
+#define _AES_STATUS_NOTEMPTY_SHIFT 4 /**< Shift value for AES_NOTEMPTY */
+#define _AES_STATUS_NOTEMPTY_MASK 0x10UL /**< Bit mask for AES_NOTEMPTY */
+#define _AES_STATUS_NOTEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */
+#define AES_STATUS_NOTEMPTY_DEFAULT (_AES_STATUS_NOTEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_STATUS */
+#define AES_STATUS_WAITING (0x1UL << 5) /**< Pusher waiting for FIFO */
+#define _AES_STATUS_WAITING_SHIFT 5 /**< Shift value for AES_WAITING */
+#define _AES_STATUS_WAITING_MASK 0x20UL /**< Bit mask for AES_WAITING */
+#define _AES_STATUS_WAITING_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */
+#define AES_STATUS_WAITING_DEFAULT (_AES_STATUS_WAITING_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_STATUS */
+#define AES_STATUS_SOFTRSTBSY (0x1UL << 6) /**< Software reset busy */
+#define _AES_STATUS_SOFTRSTBSY_SHIFT 6 /**< Shift value for AES_SOFTRSTBSY */
+#define _AES_STATUS_SOFTRSTBSY_MASK 0x40UL /**< Bit mask for AES_SOFTRSTBSY */
+#define _AES_STATUS_SOFTRSTBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */
+#define AES_STATUS_SOFTRSTBSY_DEFAULT (_AES_STATUS_SOFTRSTBSY_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_STATUS */
+#define _AES_STATUS_FIFODATANUM_SHIFT 16 /**< Shift value for AES_FIFODATANUM */
+#define _AES_STATUS_FIFODATANUM_MASK 0xFFFF0000UL /**< Bit mask for AES_FIFODATANUM */
+#define _AES_STATUS_FIFODATANUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */
+#define AES_STATUS_FIFODATANUM_DEFAULT (_AES_STATUS_FIFODATANUM_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_STATUS */
+
+/* Bit fields for AES INCL_IPS_HW_CFG */
+#define _AES_INCL_IPS_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_INCL_IPS_HW_CFG */
+#define _AES_INCL_IPS_HW_CFG_MASK 0x000007FFUL /**< Mask for AES_INCL_IPS_HW_CFG */
+#define AES_INCL_IPS_HW_CFG_g_IncludeAES (0x1UL << 0) /**< Generic g_IncludeAES value */
+#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_SHIFT 0 /**< Shift value for AES_g_IncludeAES */
+#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_MASK 0x1UL /**< Bit mask for AES_g_IncludeAES */
+#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */
+#define AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/
+#define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM (0x1UL << 1) /**< Generic g_IncludeAESGCM value */
+#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_SHIFT 1 /**< Shift value for AES_g_IncludeAESGCM */
+#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_MASK 0x2UL /**< Bit mask for AES_g_IncludeAESGCM */
+#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */
+#define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/
+#define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS (0x1UL << 2) /**< Generic g_IncludeAESXTS value */
+#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_SHIFT 2 /**< Shift value for AES_g_IncludeAESXTS */
+#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_MASK 0x4UL /**< Bit mask for AES_g_IncludeAESXTS */
+#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */
+#define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/
+#define AES_INCL_IPS_HW_CFG_g_IncludeDES (0x1UL << 3) /**< Generic g_IncludeDES value */
+#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_SHIFT 3 /**< Shift value for AES_g_IncludeDES */
+#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_MASK 0x8UL /**< Bit mask for AES_g_IncludeDES */
+#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */
+#define AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/
+#define AES_INCL_IPS_HW_CFG_g_IncludeHASH (0x1UL << 4) /**< Generic g_IncludeHASH value */
+#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_SHIFT 4 /**< Shift value for AES_g_IncludeHASH */
+#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_MASK 0x10UL /**< Bit mask for AES_g_IncludeHASH */
+#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */
+#define AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/
+#define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly (0x1UL << 5) /**< Generic g_IncludeChachaPoly value */
+#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_SHIFT 5 /**< Shift value for AES_g_IncludeChachaPoly */
+#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_MASK 0x20UL /**< Bit mask for AES_g_IncludeChachaPoly */
+#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */
+#define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/
+#define AES_INCL_IPS_HW_CFG_g_IncludeSHA3 (0x1UL << 6) /**< Generic g_IncludeSHA3 value */
+#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_SHIFT 6 /**< Shift value for AES_g_IncludeSHA3 */
+#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_MASK 0x40UL /**< Bit mask for AES_g_IncludeSHA3 */
+#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */
+#define AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/
+#define AES_INCL_IPS_HW_CFG_g_IncludeZUC (0x1UL << 7) /**< Generic g_IncludeZUC value */
+#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_SHIFT 7 /**< Shift value for AES_g_IncludeZUC */
+#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_MASK 0x80UL /**< Bit mask for AES_g_IncludeZUC */
+#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */
+#define AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT << 7) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/
+#define AES_INCL_IPS_HW_CFG_g_IncludeSM4 (0x1UL << 8) /**< Generic g_IncludeSM4 value */
+#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_SHIFT 8 /**< Shift value for AES_g_IncludeSM4 */
+#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_MASK 0x100UL /**< Bit mask for AES_g_IncludeSM4 */
+#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */
+#define AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT << 8) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/
+#define AES_INCL_IPS_HW_CFG_g_IncludePKE (0x1UL << 9) /**< Generic g_IncludePKE value */
+#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_SHIFT 9 /**< Shift value for AES_g_IncludePKE */
+#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_MASK 0x200UL /**< Bit mask for AES_g_IncludePKE */
+#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */
+#define AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT << 9) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/
+#define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG (0x1UL << 10) /**< Generic g_IncludeNDRNG value */
+#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_SHIFT 10 /**< Shift value for AES_g_IncludeNDRNG */
+#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_MASK 0x400UL /**< Bit mask for AES_g_IncludeNDRNG */
+#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */
+#define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT << 10) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/
+
+/* Bit fields for AES BA411E_HW_CFG_1 */
+#define _AES_BA411E_HW_CFG_1_RESETVALUE 0x05010127UL /**< Default value for AES_BA411E_HW_CFG_1 */
+#define _AES_BA411E_HW_CFG_1_MASK 0x070301FFUL /**< Mask for AES_BA411E_HW_CFG_1 */
+#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_SHIFT 0 /**< Shift value for AES_g_AesModesPoss */
+#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_MASK 0x1FFUL /**< Bit mask for AES_g_AesModesPoss */
+#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT 0x00000127UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */
+#define AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT (_AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/
+#define AES_BA411E_HW_CFG_1_g_CS (0x1UL << 16) /**< Generic g_CS value */
+#define _AES_BA411E_HW_CFG_1_g_CS_SHIFT 16 /**< Shift value for AES_g_CS */
+#define _AES_BA411E_HW_CFG_1_g_CS_MASK 0x10000UL /**< Bit mask for AES_g_CS */
+#define _AES_BA411E_HW_CFG_1_g_CS_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */
+#define AES_BA411E_HW_CFG_1_g_CS_DEFAULT (_AES_BA411E_HW_CFG_1_g_CS_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/
+#define AES_BA411E_HW_CFG_1_g_UseMasking (0x1UL << 17) /**< Generic g_UseMasking value */
+#define _AES_BA411E_HW_CFG_1_g_UseMasking_SHIFT 17 /**< Shift value for AES_g_UseMasking */
+#define _AES_BA411E_HW_CFG_1_g_UseMasking_MASK 0x20000UL /**< Bit mask for AES_g_UseMasking */
+#define _AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */
+#define AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT (_AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/
+#define _AES_BA411E_HW_CFG_1_g_Keysize_SHIFT 24 /**< Shift value for AES_g_Keysize */
+#define _AES_BA411E_HW_CFG_1_g_Keysize_MASK 0x7000000UL /**< Bit mask for AES_g_Keysize */
+#define _AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT 0x00000005UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */
+#define AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT (_AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT << 24) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/
+
+/* Bit fields for AES BA411E_HW_CFG_2 */
+#define _AES_BA411E_HW_CFG_2_RESETVALUE 0x00000080UL /**< Default value for AES_BA411E_HW_CFG_2 */
+#define _AES_BA411E_HW_CFG_2_MASK 0x0000FFFFUL /**< Mask for AES_BA411E_HW_CFG_2 */
+#define _AES_BA411E_HW_CFG_2_g_CtrSize_SHIFT 0 /**< Shift value for AES_g_CtrSize */
+#define _AES_BA411E_HW_CFG_2_g_CtrSize_MASK 0xFFFFUL /**< Bit mask for AES_g_CtrSize */
+#define _AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT 0x00000080UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_2 */
+#define AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT (_AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_2*/
+
+/* Bit fields for AES BA413_HW_CFG */
+#define _AES_BA413_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA413_HW_CFG */
+#define _AES_BA413_HW_CFG_MASK 0x0007007FUL /**< Mask for AES_BA413_HW_CFG */
+#define _AES_BA413_HW_CFG_g_HashMaskFunc_SHIFT 0 /**< Shift value for AES_g_HashMaskFunc */
+#define _AES_BA413_HW_CFG_g_HashMaskFunc_MASK 0x7FUL /**< Bit mask for AES_g_HashMaskFunc */
+#define _AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */
+#define AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT (_AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */
+#define AES_BA413_HW_CFG_g_HashPadding (0x1UL << 16) /**< Generic g_HashPadding value */
+#define _AES_BA413_HW_CFG_g_HashPadding_SHIFT 16 /**< Shift value for AES_g_HashPadding */
+#define _AES_BA413_HW_CFG_g_HashPadding_MASK 0x10000UL /**< Bit mask for AES_g_HashPadding */
+#define _AES_BA413_HW_CFG_g_HashPadding_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */
+#define AES_BA413_HW_CFG_g_HashPadding_DEFAULT (_AES_BA413_HW_CFG_g_HashPadding_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */
+#define AES_BA413_HW_CFG_g_HMAC_enabled (0x1UL << 17) /**< Generic g_HMAC_enabled value */
+#define _AES_BA413_HW_CFG_g_HMAC_enabled_SHIFT 17 /**< Shift value for AES_g_HMAC_enabled */
+#define _AES_BA413_HW_CFG_g_HMAC_enabled_MASK 0x20000UL /**< Bit mask for AES_g_HMAC_enabled */
+#define _AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */
+#define AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT (_AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */
+#define AES_BA413_HW_CFG_g_HashVerifyDigest (0x1UL << 18) /**< Generic g_HashVerifyDigest value */
+#define _AES_BA413_HW_CFG_g_HashVerifyDigest_SHIFT 18 /**< Shift value for AES_g_HashVerifyDigest */
+#define _AES_BA413_HW_CFG_g_HashVerifyDigest_MASK 0x40000UL /**< Bit mask for AES_g_HashVerifyDigest */
+#define _AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */
+#define AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT (_AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT << 18) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */
+
+/* Bit fields for AES BA418_HW_CFG */
+#define _AES_BA418_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_BA418_HW_CFG */
+#define _AES_BA418_HW_CFG_MASK 0x00000001UL /**< Mask for AES_BA418_HW_CFG */
+#define AES_BA418_HW_CFG_g_Sha3CtxtEn (0x1UL << 0) /**< Generic g_Sha3CtxtEn value */
+#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_SHIFT 0 /**< Shift value for AES_g_Sha3CtxtEn */
+#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_MASK 0x1UL /**< Bit mask for AES_g_Sha3CtxtEn */
+#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA418_HW_CFG */
+#define AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT (_AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA418_HW_CFG */
+
+/* Bit fields for AES BA419_HW_CFG */
+#define _AES_BA419_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA419_HW_CFG */
+#define _AES_BA419_HW_CFG_MASK 0x0000007FUL /**< Mask for AES_BA419_HW_CFG */
+#define _AES_BA419_HW_CFG_g_SM4ModesPoss_SHIFT 0 /**< Shift value for AES_g_SM4ModesPoss */
+#define _AES_BA419_HW_CFG_g_SM4ModesPoss_MASK 0x7FUL /**< Bit mask for AES_g_SM4ModesPoss */
+#define _AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA419_HW_CFG */
+#define AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT (_AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA419_HW_CFG */
+
+/** @} End of group EFR32MG24_AES_BitFields */
+/** @} End of group EFR32MG24_AES */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_AES_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_agc.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_agc.h
new file mode 100644
index 00000000..d80fcf45
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_agc.h
@@ -0,0 +1,2976 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 AGC register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_AGC_H
+#define EFR32MG24_AGC_H
+#define AGC_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_AGC AGC
+ * @{
+ * @brief EFR32MG24 AGC Register Declaration.
+ *****************************************************************************/
+
+/** AGC Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IP Version */
+ __IOM uint32_t EN; /**< Enable peripheral clock to this module */
+ __IM uint32_t STATUS0; /**< Status register 0 */
+ __IM uint32_t STATUS1; /**< Status register 1 */
+ __IM uint32_t STATUS2; /**< Status register 2 */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+ __IM uint32_t RSSI; /**< Received Signal Strength Indicator */
+ __IM uint32_t FRAMERSSI; /**< FRAME RSSI value */
+ __IOM uint32_t CTRL0; /**< Control register 0 */
+ __IOM uint32_t CTRL1; /**< Control register 1 */
+ __IOM uint32_t CTRL2; /**< Control register 2 */
+ __IOM uint32_t CTRL3; /**< Control register 3 */
+ __IOM uint32_t CTRL4; /**< Control register 4 */
+ __IOM uint32_t CTRL5; /**< Control register 5 */
+ __IOM uint32_t CTRL6; /**< Control register 6 */
+ __IOM uint32_t CTRL7; /**< Control register 1 */
+ __IOM uint32_t RSSISTEPTHR; /**< RSSI step threshold */
+ uint32_t RESERVED1[1U]; /**< Reserved for future use */
+ __IOM uint32_t IF; /**< Interrupt Flags Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ uint32_t RESERVED2[1U]; /**< Reserved for future use */
+ __IOM uint32_t GAINRANGE; /**< Range of RX Gain to use in AGC */
+ __IOM uint32_t AGCPERIOD0; /**< AGC period */
+ __IOM uint32_t AGCPERIOD1; /**< AGC Period */
+ __IOM uint32_t HICNTREGION0; /**< Hi-counter region-0 */
+ __IOM uint32_t HICNTREGION1; /**< Hi-counter region-1 */
+ __IOM uint32_t STEPDWN; /**< Hi-counter region-2 */
+ __IOM uint32_t GAINSTEPLIM0; /**< Limits for Gain Steps */
+ __IOM uint32_t GAINSTEPLIM1; /**< Limits for Gain Steps */
+ __IOM uint32_t PNRFATT0; /**< PN RF attenuation code group 0 */
+ __IOM uint32_t PNRFATT1; /**< PN RF attenuation code group 1 */
+ __IOM uint32_t PNRFATT2; /**< PN RF attenuation code group 2 */
+ __IOM uint32_t PNRFATT3; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFATT4; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFATT5; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFATT6; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFATT7; /**< PN RF attenuation code group 3 */
+ uint32_t RESERVED3[4U]; /**< Reserved for future use */
+ __IOM uint32_t PNRFATTALT; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t LNAMIXCODE0; /**< LNA/MIX slice code group 0 */
+ __IOM uint32_t LNAMIXCODE1; /**< LNA/MIX slice code group 1 */
+ __IOM uint32_t PGACODE0; /**< PGA gain code group 0 */
+ __IOM uint32_t PGACODE1; /**< PGA gain code group 1 */
+ __IOM uint32_t LBT; /**< Configure AGC for (ETSI) LBT */
+ __IOM uint32_t MIRRORIF; /**< Mirror Interrupt Flags Register */
+ __IOM uint32_t SEQIF; /**< SEQ Interrupt Flags Register */
+ __IOM uint32_t SEQIEN; /**< SEQ Interrupt Enable Register */
+ __IOM uint32_t RSSIABSTHR; /**< RSSI absolute threshold */
+ __IOM uint32_t LNABOOST; /**< LNA boost control register */
+ __IOM uint32_t ANTDIV; /**< Antenna diversity AGC setting */
+ __IOM uint32_t DUALRFPKDTHD0; /**< Thresholds for dual rfpkd */
+ __IOM uint32_t DUALRFPKDTHD1; /**< Thresholds for dual rfpkd */
+ __IOM uint32_t SPARE; /**< Spare register for ECO */
+ __IOM uint32_t PNRFFILT0; /**< PN RF attenuation code group 0 */
+ __IOM uint32_t PNRFFILT1; /**< PN RF attenuation code group 1 */
+ __IOM uint32_t PNRFFILT2; /**< PN RF attenuation code group 2 */
+ __IOM uint32_t PNRFFILT3; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFFILT4; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFFILT5; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFFILT6; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFFILT7; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t FENOTCHATT0; /**< FE Notch attenuation code group 0 */
+ __IOM uint32_t FENOTCHATT1; /**< FE Notch attenuation code group 1 */
+ __IOM uint32_t FENOTCHATT2; /**< FE Notch attenuation code group 2 */
+ __IOM uint32_t FENOTCHATT3; /**< FE Notch attenuation code group 3 */
+ __IOM uint32_t FENOTCHATT4; /**< FE Notch attenuation code group 4 */
+ __IOM uint32_t FENOTCHATT5; /**< FE Notch attenuation code group 5 */
+ __IOM uint32_t FENOTCHATT6; /**< FE Notch attenuation code group 6 */
+ __IOM uint32_t FENOTCHATT7; /**< FE Notch attenuation code group 7 */
+ __IOM uint32_t FENOTCHATT8; /**< FE Notch attenuation code group 8 */
+ __IOM uint32_t FENOTCHATT9; /**< FE Notch attenuation code group 9 */
+ __IOM uint32_t FENOTCHATT10; /**< FE Notch attenuation code group 10 */
+ __IOM uint32_t FENOTCHATT11; /**< FE Notch attenuation code group 11 */
+ __IOM uint32_t FENOTCHFILT0; /**< FE Notch filter code group 0 */
+ __IOM uint32_t FENOTCHFILT1; /**< FE Notch filter code group 1 */
+ __IOM uint32_t FENOTCHFILT2; /**< FE Notch filter code group 2 */
+ __IOM uint32_t FENOTCHFILT3; /**< FE Notch filter code group 3 */
+ __IOM uint32_t FENOTCHFILT4; /**< FE Notch filter code group 4 */
+ __IOM uint32_t FENOTCHFILT5; /**< FE Notch filter code group 5 */
+ __IOM uint32_t FENOTCHFILT6; /**< FE Notch filter code group 6 */
+ __IOM uint32_t FENOTCHFILT7; /**< FE Notch filter code group 7 */
+ __IOM uint32_t FENOTCHFILT8; /**< FE Notch filter code group 8 */
+ __IOM uint32_t FENOTCHFILT9; /**< FE Notch filter code group 9 */
+ __IOM uint32_t FENOTCHFILT10; /**< FE Notch filter code group 10 */
+ __IOM uint32_t FENOTCHFILT11; /**< FE Notch filter code group 11 */
+ __IM uint32_t CCADEBUG; /**< CCA debug register */
+ uint32_t RESERVED4[935U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP Version */
+ __IOM uint32_t EN_SET; /**< Enable peripheral clock to this module */
+ __IM uint32_t STATUS0_SET; /**< Status register 0 */
+ __IM uint32_t STATUS1_SET; /**< Status register 1 */
+ __IM uint32_t STATUS2_SET; /**< Status register 2 */
+ uint32_t RESERVED5[1U]; /**< Reserved for future use */
+ __IM uint32_t RSSI_SET; /**< Received Signal Strength Indicator */
+ __IM uint32_t FRAMERSSI_SET; /**< FRAME RSSI value */
+ __IOM uint32_t CTRL0_SET; /**< Control register 0 */
+ __IOM uint32_t CTRL1_SET; /**< Control register 1 */
+ __IOM uint32_t CTRL2_SET; /**< Control register 2 */
+ __IOM uint32_t CTRL3_SET; /**< Control register 3 */
+ __IOM uint32_t CTRL4_SET; /**< Control register 4 */
+ __IOM uint32_t CTRL5_SET; /**< Control register 5 */
+ __IOM uint32_t CTRL6_SET; /**< Control register 6 */
+ __IOM uint32_t CTRL7_SET; /**< Control register 1 */
+ __IOM uint32_t RSSISTEPTHR_SET; /**< RSSI step threshold */
+ uint32_t RESERVED6[1U]; /**< Reserved for future use */
+ __IOM uint32_t IF_SET; /**< Interrupt Flags Register */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
+ uint32_t RESERVED7[1U]; /**< Reserved for future use */
+ __IOM uint32_t GAINRANGE_SET; /**< Range of RX Gain to use in AGC */
+ __IOM uint32_t AGCPERIOD0_SET; /**< AGC period */
+ __IOM uint32_t AGCPERIOD1_SET; /**< AGC Period */
+ __IOM uint32_t HICNTREGION0_SET; /**< Hi-counter region-0 */
+ __IOM uint32_t HICNTREGION1_SET; /**< Hi-counter region-1 */
+ __IOM uint32_t STEPDWN_SET; /**< Hi-counter region-2 */
+ __IOM uint32_t GAINSTEPLIM0_SET; /**< Limits for Gain Steps */
+ __IOM uint32_t GAINSTEPLIM1_SET; /**< Limits for Gain Steps */
+ __IOM uint32_t PNRFATT0_SET; /**< PN RF attenuation code group 0 */
+ __IOM uint32_t PNRFATT1_SET; /**< PN RF attenuation code group 1 */
+ __IOM uint32_t PNRFATT2_SET; /**< PN RF attenuation code group 2 */
+ __IOM uint32_t PNRFATT3_SET; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFATT4_SET; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFATT5_SET; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFATT6_SET; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFATT7_SET; /**< PN RF attenuation code group 3 */
+ uint32_t RESERVED8[4U]; /**< Reserved for future use */
+ __IOM uint32_t PNRFATTALT_SET; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t LNAMIXCODE0_SET; /**< LNA/MIX slice code group 0 */
+ __IOM uint32_t LNAMIXCODE1_SET; /**< LNA/MIX slice code group 1 */
+ __IOM uint32_t PGACODE0_SET; /**< PGA gain code group 0 */
+ __IOM uint32_t PGACODE1_SET; /**< PGA gain code group 1 */
+ __IOM uint32_t LBT_SET; /**< Configure AGC for (ETSI) LBT */
+ __IOM uint32_t MIRRORIF_SET; /**< Mirror Interrupt Flags Register */
+ __IOM uint32_t SEQIF_SET; /**< SEQ Interrupt Flags Register */
+ __IOM uint32_t SEQIEN_SET; /**< SEQ Interrupt Enable Register */
+ __IOM uint32_t RSSIABSTHR_SET; /**< RSSI absolute threshold */
+ __IOM uint32_t LNABOOST_SET; /**< LNA boost control register */
+ __IOM uint32_t ANTDIV_SET; /**< Antenna diversity AGC setting */
+ __IOM uint32_t DUALRFPKDTHD0_SET; /**< Thresholds for dual rfpkd */
+ __IOM uint32_t DUALRFPKDTHD1_SET; /**< Thresholds for dual rfpkd */
+ __IOM uint32_t SPARE_SET; /**< Spare register for ECO */
+ __IOM uint32_t PNRFFILT0_SET; /**< PN RF attenuation code group 0 */
+ __IOM uint32_t PNRFFILT1_SET; /**< PN RF attenuation code group 1 */
+ __IOM uint32_t PNRFFILT2_SET; /**< PN RF attenuation code group 2 */
+ __IOM uint32_t PNRFFILT3_SET; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFFILT4_SET; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFFILT5_SET; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFFILT6_SET; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFFILT7_SET; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t FENOTCHATT0_SET; /**< FE Notch attenuation code group 0 */
+ __IOM uint32_t FENOTCHATT1_SET; /**< FE Notch attenuation code group 1 */
+ __IOM uint32_t FENOTCHATT2_SET; /**< FE Notch attenuation code group 2 */
+ __IOM uint32_t FENOTCHATT3_SET; /**< FE Notch attenuation code group 3 */
+ __IOM uint32_t FENOTCHATT4_SET; /**< FE Notch attenuation code group 4 */
+ __IOM uint32_t FENOTCHATT5_SET; /**< FE Notch attenuation code group 5 */
+ __IOM uint32_t FENOTCHATT6_SET; /**< FE Notch attenuation code group 6 */
+ __IOM uint32_t FENOTCHATT7_SET; /**< FE Notch attenuation code group 7 */
+ __IOM uint32_t FENOTCHATT8_SET; /**< FE Notch attenuation code group 8 */
+ __IOM uint32_t FENOTCHATT9_SET; /**< FE Notch attenuation code group 9 */
+ __IOM uint32_t FENOTCHATT10_SET; /**< FE Notch attenuation code group 10 */
+ __IOM uint32_t FENOTCHATT11_SET; /**< FE Notch attenuation code group 11 */
+ __IOM uint32_t FENOTCHFILT0_SET; /**< FE Notch filter code group 0 */
+ __IOM uint32_t FENOTCHFILT1_SET; /**< FE Notch filter code group 1 */
+ __IOM uint32_t FENOTCHFILT2_SET; /**< FE Notch filter code group 2 */
+ __IOM uint32_t FENOTCHFILT3_SET; /**< FE Notch filter code group 3 */
+ __IOM uint32_t FENOTCHFILT4_SET; /**< FE Notch filter code group 4 */
+ __IOM uint32_t FENOTCHFILT5_SET; /**< FE Notch filter code group 5 */
+ __IOM uint32_t FENOTCHFILT6_SET; /**< FE Notch filter code group 6 */
+ __IOM uint32_t FENOTCHFILT7_SET; /**< FE Notch filter code group 7 */
+ __IOM uint32_t FENOTCHFILT8_SET; /**< FE Notch filter code group 8 */
+ __IOM uint32_t FENOTCHFILT9_SET; /**< FE Notch filter code group 9 */
+ __IOM uint32_t FENOTCHFILT10_SET; /**< FE Notch filter code group 10 */
+ __IOM uint32_t FENOTCHFILT11_SET; /**< FE Notch filter code group 11 */
+ __IM uint32_t CCADEBUG_SET; /**< CCA debug register */
+ uint32_t RESERVED9[935U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP Version */
+ __IOM uint32_t EN_CLR; /**< Enable peripheral clock to this module */
+ __IM uint32_t STATUS0_CLR; /**< Status register 0 */
+ __IM uint32_t STATUS1_CLR; /**< Status register 1 */
+ __IM uint32_t STATUS2_CLR; /**< Status register 2 */
+ uint32_t RESERVED10[1U]; /**< Reserved for future use */
+ __IM uint32_t RSSI_CLR; /**< Received Signal Strength Indicator */
+ __IM uint32_t FRAMERSSI_CLR; /**< FRAME RSSI value */
+ __IOM uint32_t CTRL0_CLR; /**< Control register 0 */
+ __IOM uint32_t CTRL1_CLR; /**< Control register 1 */
+ __IOM uint32_t CTRL2_CLR; /**< Control register 2 */
+ __IOM uint32_t CTRL3_CLR; /**< Control register 3 */
+ __IOM uint32_t CTRL4_CLR; /**< Control register 4 */
+ __IOM uint32_t CTRL5_CLR; /**< Control register 5 */
+ __IOM uint32_t CTRL6_CLR; /**< Control register 6 */
+ __IOM uint32_t CTRL7_CLR; /**< Control register 1 */
+ __IOM uint32_t RSSISTEPTHR_CLR; /**< RSSI step threshold */
+ uint32_t RESERVED11[1U]; /**< Reserved for future use */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flags Register */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
+ uint32_t RESERVED12[1U]; /**< Reserved for future use */
+ __IOM uint32_t GAINRANGE_CLR; /**< Range of RX Gain to use in AGC */
+ __IOM uint32_t AGCPERIOD0_CLR; /**< AGC period */
+ __IOM uint32_t AGCPERIOD1_CLR; /**< AGC Period */
+ __IOM uint32_t HICNTREGION0_CLR; /**< Hi-counter region-0 */
+ __IOM uint32_t HICNTREGION1_CLR; /**< Hi-counter region-1 */
+ __IOM uint32_t STEPDWN_CLR; /**< Hi-counter region-2 */
+ __IOM uint32_t GAINSTEPLIM0_CLR; /**< Limits for Gain Steps */
+ __IOM uint32_t GAINSTEPLIM1_CLR; /**< Limits for Gain Steps */
+ __IOM uint32_t PNRFATT0_CLR; /**< PN RF attenuation code group 0 */
+ __IOM uint32_t PNRFATT1_CLR; /**< PN RF attenuation code group 1 */
+ __IOM uint32_t PNRFATT2_CLR; /**< PN RF attenuation code group 2 */
+ __IOM uint32_t PNRFATT3_CLR; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFATT4_CLR; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFATT5_CLR; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFATT6_CLR; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFATT7_CLR; /**< PN RF attenuation code group 3 */
+ uint32_t RESERVED13[4U]; /**< Reserved for future use */
+ __IOM uint32_t PNRFATTALT_CLR; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t LNAMIXCODE0_CLR; /**< LNA/MIX slice code group 0 */
+ __IOM uint32_t LNAMIXCODE1_CLR; /**< LNA/MIX slice code group 1 */
+ __IOM uint32_t PGACODE0_CLR; /**< PGA gain code group 0 */
+ __IOM uint32_t PGACODE1_CLR; /**< PGA gain code group 1 */
+ __IOM uint32_t LBT_CLR; /**< Configure AGC for (ETSI) LBT */
+ __IOM uint32_t MIRRORIF_CLR; /**< Mirror Interrupt Flags Register */
+ __IOM uint32_t SEQIF_CLR; /**< SEQ Interrupt Flags Register */
+ __IOM uint32_t SEQIEN_CLR; /**< SEQ Interrupt Enable Register */
+ __IOM uint32_t RSSIABSTHR_CLR; /**< RSSI absolute threshold */
+ __IOM uint32_t LNABOOST_CLR; /**< LNA boost control register */
+ __IOM uint32_t ANTDIV_CLR; /**< Antenna diversity AGC setting */
+ __IOM uint32_t DUALRFPKDTHD0_CLR; /**< Thresholds for dual rfpkd */
+ __IOM uint32_t DUALRFPKDTHD1_CLR; /**< Thresholds for dual rfpkd */
+ __IOM uint32_t SPARE_CLR; /**< Spare register for ECO */
+ __IOM uint32_t PNRFFILT0_CLR; /**< PN RF attenuation code group 0 */
+ __IOM uint32_t PNRFFILT1_CLR; /**< PN RF attenuation code group 1 */
+ __IOM uint32_t PNRFFILT2_CLR; /**< PN RF attenuation code group 2 */
+ __IOM uint32_t PNRFFILT3_CLR; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFFILT4_CLR; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFFILT5_CLR; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFFILT6_CLR; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFFILT7_CLR; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t FENOTCHATT0_CLR; /**< FE Notch attenuation code group 0 */
+ __IOM uint32_t FENOTCHATT1_CLR; /**< FE Notch attenuation code group 1 */
+ __IOM uint32_t FENOTCHATT2_CLR; /**< FE Notch attenuation code group 2 */
+ __IOM uint32_t FENOTCHATT3_CLR; /**< FE Notch attenuation code group 3 */
+ __IOM uint32_t FENOTCHATT4_CLR; /**< FE Notch attenuation code group 4 */
+ __IOM uint32_t FENOTCHATT5_CLR; /**< FE Notch attenuation code group 5 */
+ __IOM uint32_t FENOTCHATT6_CLR; /**< FE Notch attenuation code group 6 */
+ __IOM uint32_t FENOTCHATT7_CLR; /**< FE Notch attenuation code group 7 */
+ __IOM uint32_t FENOTCHATT8_CLR; /**< FE Notch attenuation code group 8 */
+ __IOM uint32_t FENOTCHATT9_CLR; /**< FE Notch attenuation code group 9 */
+ __IOM uint32_t FENOTCHATT10_CLR; /**< FE Notch attenuation code group 10 */
+ __IOM uint32_t FENOTCHATT11_CLR; /**< FE Notch attenuation code group 11 */
+ __IOM uint32_t FENOTCHFILT0_CLR; /**< FE Notch filter code group 0 */
+ __IOM uint32_t FENOTCHFILT1_CLR; /**< FE Notch filter code group 1 */
+ __IOM uint32_t FENOTCHFILT2_CLR; /**< FE Notch filter code group 2 */
+ __IOM uint32_t FENOTCHFILT3_CLR; /**< FE Notch filter code group 3 */
+ __IOM uint32_t FENOTCHFILT4_CLR; /**< FE Notch filter code group 4 */
+ __IOM uint32_t FENOTCHFILT5_CLR; /**< FE Notch filter code group 5 */
+ __IOM uint32_t FENOTCHFILT6_CLR; /**< FE Notch filter code group 6 */
+ __IOM uint32_t FENOTCHFILT7_CLR; /**< FE Notch filter code group 7 */
+ __IOM uint32_t FENOTCHFILT8_CLR; /**< FE Notch filter code group 8 */
+ __IOM uint32_t FENOTCHFILT9_CLR; /**< FE Notch filter code group 9 */
+ __IOM uint32_t FENOTCHFILT10_CLR; /**< FE Notch filter code group 10 */
+ __IOM uint32_t FENOTCHFILT11_CLR; /**< FE Notch filter code group 11 */
+ __IM uint32_t CCADEBUG_CLR; /**< CCA debug register */
+ uint32_t RESERVED14[935U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP Version */
+ __IOM uint32_t EN_TGL; /**< Enable peripheral clock to this module */
+ __IM uint32_t STATUS0_TGL; /**< Status register 0 */
+ __IM uint32_t STATUS1_TGL; /**< Status register 1 */
+ __IM uint32_t STATUS2_TGL; /**< Status register 2 */
+ uint32_t RESERVED15[1U]; /**< Reserved for future use */
+ __IM uint32_t RSSI_TGL; /**< Received Signal Strength Indicator */
+ __IM uint32_t FRAMERSSI_TGL; /**< FRAME RSSI value */
+ __IOM uint32_t CTRL0_TGL; /**< Control register 0 */
+ __IOM uint32_t CTRL1_TGL; /**< Control register 1 */
+ __IOM uint32_t CTRL2_TGL; /**< Control register 2 */
+ __IOM uint32_t CTRL3_TGL; /**< Control register 3 */
+ __IOM uint32_t CTRL4_TGL; /**< Control register 4 */
+ __IOM uint32_t CTRL5_TGL; /**< Control register 5 */
+ __IOM uint32_t CTRL6_TGL; /**< Control register 6 */
+ __IOM uint32_t CTRL7_TGL; /**< Control register 1 */
+ __IOM uint32_t RSSISTEPTHR_TGL; /**< RSSI step threshold */
+ uint32_t RESERVED16[1U]; /**< Reserved for future use */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flags Register */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
+ uint32_t RESERVED17[1U]; /**< Reserved for future use */
+ __IOM uint32_t GAINRANGE_TGL; /**< Range of RX Gain to use in AGC */
+ __IOM uint32_t AGCPERIOD0_TGL; /**< AGC period */
+ __IOM uint32_t AGCPERIOD1_TGL; /**< AGC Period */
+ __IOM uint32_t HICNTREGION0_TGL; /**< Hi-counter region-0 */
+ __IOM uint32_t HICNTREGION1_TGL; /**< Hi-counter region-1 */
+ __IOM uint32_t STEPDWN_TGL; /**< Hi-counter region-2 */
+ __IOM uint32_t GAINSTEPLIM0_TGL; /**< Limits for Gain Steps */
+ __IOM uint32_t GAINSTEPLIM1_TGL; /**< Limits for Gain Steps */
+ __IOM uint32_t PNRFATT0_TGL; /**< PN RF attenuation code group 0 */
+ __IOM uint32_t PNRFATT1_TGL; /**< PN RF attenuation code group 1 */
+ __IOM uint32_t PNRFATT2_TGL; /**< PN RF attenuation code group 2 */
+ __IOM uint32_t PNRFATT3_TGL; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFATT4_TGL; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFATT5_TGL; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFATT6_TGL; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFATT7_TGL; /**< PN RF attenuation code group 3 */
+ uint32_t RESERVED18[4U]; /**< Reserved for future use */
+ __IOM uint32_t PNRFATTALT_TGL; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t LNAMIXCODE0_TGL; /**< LNA/MIX slice code group 0 */
+ __IOM uint32_t LNAMIXCODE1_TGL; /**< LNA/MIX slice code group 1 */
+ __IOM uint32_t PGACODE0_TGL; /**< PGA gain code group 0 */
+ __IOM uint32_t PGACODE1_TGL; /**< PGA gain code group 1 */
+ __IOM uint32_t LBT_TGL; /**< Configure AGC for (ETSI) LBT */
+ __IOM uint32_t MIRRORIF_TGL; /**< Mirror Interrupt Flags Register */
+ __IOM uint32_t SEQIF_TGL; /**< SEQ Interrupt Flags Register */
+ __IOM uint32_t SEQIEN_TGL; /**< SEQ Interrupt Enable Register */
+ __IOM uint32_t RSSIABSTHR_TGL; /**< RSSI absolute threshold */
+ __IOM uint32_t LNABOOST_TGL; /**< LNA boost control register */
+ __IOM uint32_t ANTDIV_TGL; /**< Antenna diversity AGC setting */
+ __IOM uint32_t DUALRFPKDTHD0_TGL; /**< Thresholds for dual rfpkd */
+ __IOM uint32_t DUALRFPKDTHD1_TGL; /**< Thresholds for dual rfpkd */
+ __IOM uint32_t SPARE_TGL; /**< Spare register for ECO */
+ __IOM uint32_t PNRFFILT0_TGL; /**< PN RF attenuation code group 0 */
+ __IOM uint32_t PNRFFILT1_TGL; /**< PN RF attenuation code group 1 */
+ __IOM uint32_t PNRFFILT2_TGL; /**< PN RF attenuation code group 2 */
+ __IOM uint32_t PNRFFILT3_TGL; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFFILT4_TGL; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFFILT5_TGL; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFFILT6_TGL; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t PNRFFILT7_TGL; /**< PN RF attenuation code group 3 */
+ __IOM uint32_t FENOTCHATT0_TGL; /**< FE Notch attenuation code group 0 */
+ __IOM uint32_t FENOTCHATT1_TGL; /**< FE Notch attenuation code group 1 */
+ __IOM uint32_t FENOTCHATT2_TGL; /**< FE Notch attenuation code group 2 */
+ __IOM uint32_t FENOTCHATT3_TGL; /**< FE Notch attenuation code group 3 */
+ __IOM uint32_t FENOTCHATT4_TGL; /**< FE Notch attenuation code group 4 */
+ __IOM uint32_t FENOTCHATT5_TGL; /**< FE Notch attenuation code group 5 */
+ __IOM uint32_t FENOTCHATT6_TGL; /**< FE Notch attenuation code group 6 */
+ __IOM uint32_t FENOTCHATT7_TGL; /**< FE Notch attenuation code group 7 */
+ __IOM uint32_t FENOTCHATT8_TGL; /**< FE Notch attenuation code group 8 */
+ __IOM uint32_t FENOTCHATT9_TGL; /**< FE Notch attenuation code group 9 */
+ __IOM uint32_t FENOTCHATT10_TGL; /**< FE Notch attenuation code group 10 */
+ __IOM uint32_t FENOTCHATT11_TGL; /**< FE Notch attenuation code group 11 */
+ __IOM uint32_t FENOTCHFILT0_TGL; /**< FE Notch filter code group 0 */
+ __IOM uint32_t FENOTCHFILT1_TGL; /**< FE Notch filter code group 1 */
+ __IOM uint32_t FENOTCHFILT2_TGL; /**< FE Notch filter code group 2 */
+ __IOM uint32_t FENOTCHFILT3_TGL; /**< FE Notch filter code group 3 */
+ __IOM uint32_t FENOTCHFILT4_TGL; /**< FE Notch filter code group 4 */
+ __IOM uint32_t FENOTCHFILT5_TGL; /**< FE Notch filter code group 5 */
+ __IOM uint32_t FENOTCHFILT6_TGL; /**< FE Notch filter code group 6 */
+ __IOM uint32_t FENOTCHFILT7_TGL; /**< FE Notch filter code group 7 */
+ __IOM uint32_t FENOTCHFILT8_TGL; /**< FE Notch filter code group 8 */
+ __IOM uint32_t FENOTCHFILT9_TGL; /**< FE Notch filter code group 9 */
+ __IOM uint32_t FENOTCHFILT10_TGL; /**< FE Notch filter code group 10 */
+ __IOM uint32_t FENOTCHFILT11_TGL; /**< FE Notch filter code group 11 */
+ __IM uint32_t CCADEBUG_TGL; /**< CCA debug register */
+} AGC_TypeDef;
+/** @} End of group EFR32MG24_AGC */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_AGC
+ * @{
+ * @defgroup EFR32MG24_AGC_BitFields AGC Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for AGC IPVERSION */
+#define _AGC_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for AGC_IPVERSION */
+#define _AGC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for AGC_IPVERSION */
+#define _AGC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for AGC_IPVERSION */
+#define _AGC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for AGC_IPVERSION */
+#define _AGC_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for AGC_IPVERSION */
+#define AGC_IPVERSION_IPVERSION_DEFAULT (_AGC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_IPVERSION */
+
+/* Bit fields for AGC EN */
+#define _AGC_EN_RESETVALUE 0x00000000UL /**< Default value for AGC_EN */
+#define _AGC_EN_MASK 0x00000001UL /**< Mask for AGC_EN */
+#define AGC_EN_EN (0x1UL << 0) /**< Enable peripheral clock to this module */
+#define _AGC_EN_EN_SHIFT 0 /**< Shift value for AGC_EN */
+#define _AGC_EN_EN_MASK 0x1UL /**< Bit mask for AGC_EN */
+#define _AGC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_EN */
+#define AGC_EN_EN_DEFAULT (_AGC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_EN */
+
+/* Bit fields for AGC STATUS0 */
+#define _AGC_STATUS0_RESETVALUE 0x00000000UL /**< Default value for AGC_STATUS0 */
+#define _AGC_STATUS0_MASK 0x07FFFFFFUL /**< Mask for AGC_STATUS0 */
+#define _AGC_STATUS0_GAININDEX_SHIFT 0 /**< Shift value for AGC_GAININDEX */
+#define _AGC_STATUS0_GAININDEX_MASK 0x3FUL /**< Bit mask for AGC_GAININDEX */
+#define _AGC_STATUS0_GAININDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_STATUS0 */
+#define AGC_STATUS0_GAININDEX_DEFAULT (_AGC_STATUS0_GAININDEX_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_STATUS0 */
+#define AGC_STATUS0_RFPKDLOWLAT (0x1UL << 6) /**< RFPKD low Latch */
+#define _AGC_STATUS0_RFPKDLOWLAT_SHIFT 6 /**< Shift value for AGC_RFPKDLOWLAT */
+#define _AGC_STATUS0_RFPKDLOWLAT_MASK 0x40UL /**< Bit mask for AGC_RFPKDLOWLAT */
+#define _AGC_STATUS0_RFPKDLOWLAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_STATUS0 */
+#define AGC_STATUS0_RFPKDLOWLAT_DEFAULT (_AGC_STATUS0_RFPKDLOWLAT_DEFAULT << 6) /**< Shifted mode DEFAULT for AGC_STATUS0 */
+#define AGC_STATUS0_RFPKDHILAT (0x1UL << 7) /**< RFPKD hi Latch */
+#define _AGC_STATUS0_RFPKDHILAT_SHIFT 7 /**< Shift value for AGC_RFPKDHILAT */
+#define _AGC_STATUS0_RFPKDHILAT_MASK 0x80UL /**< Bit mask for AGC_RFPKDHILAT */
+#define _AGC_STATUS0_RFPKDHILAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_STATUS0 */
+#define AGC_STATUS0_RFPKDHILAT_DEFAULT (_AGC_STATUS0_RFPKDHILAT_DEFAULT << 7) /**< Shifted mode DEFAULT for AGC_STATUS0 */
+#define AGC_STATUS0_IFPKDLOLAT (0x1UL << 8) /**< IFPKD Lo threshold pass Latch */
+#define _AGC_STATUS0_IFPKDLOLAT_SHIFT 8 /**< Shift value for AGC_IFPKDLOLAT */
+#define _AGC_STATUS0_IFPKDLOLAT_MASK 0x100UL /**< Bit mask for AGC_IFPKDLOLAT */
+#define _AGC_STATUS0_IFPKDLOLAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_STATUS0 */
+#define AGC_STATUS0_IFPKDLOLAT_DEFAULT (_AGC_STATUS0_IFPKDLOLAT_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_STATUS0 */
+#define AGC_STATUS0_IFPKDHILAT (0x1UL << 9) /**< IFPKD Hi threshold pass Latch */
+#define _AGC_STATUS0_IFPKDHILAT_SHIFT 9 /**< Shift value for AGC_IFPKDHILAT */
+#define _AGC_STATUS0_IFPKDHILAT_MASK 0x200UL /**< Bit mask for AGC_IFPKDHILAT */
+#define _AGC_STATUS0_IFPKDHILAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_STATUS0 */
+#define AGC_STATUS0_IFPKDHILAT_DEFAULT (_AGC_STATUS0_IFPKDHILAT_DEFAULT << 9) /**< Shifted mode DEFAULT for AGC_STATUS0 */
+#define AGC_STATUS0_CCA (0x1UL << 10) /**< Clear Channel Assessment */
+#define _AGC_STATUS0_CCA_SHIFT 10 /**< Shift value for AGC_CCA */
+#define _AGC_STATUS0_CCA_MASK 0x400UL /**< Bit mask for AGC_CCA */
+#define _AGC_STATUS0_CCA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_STATUS0 */
+#define AGC_STATUS0_CCA_DEFAULT (_AGC_STATUS0_CCA_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_STATUS0 */
+#define AGC_STATUS0_GAINOK (0x1UL << 11) /**< Gain OK */
+#define _AGC_STATUS0_GAINOK_SHIFT 11 /**< Shift value for AGC_GAINOK */
+#define _AGC_STATUS0_GAINOK_MASK 0x800UL /**< Bit mask for AGC_GAINOK */
+#define _AGC_STATUS0_GAINOK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_STATUS0 */
+#define AGC_STATUS0_GAINOK_DEFAULT (_AGC_STATUS0_GAINOK_DEFAULT << 11) /**< Shifted mode DEFAULT for AGC_STATUS0 */
+#define _AGC_STATUS0_PGAINDEX_SHIFT 12 /**< Shift value for AGC_PGAINDEX */
+#define _AGC_STATUS0_PGAINDEX_MASK 0xF000UL /**< Bit mask for AGC_PGAINDEX */
+#define _AGC_STATUS0_PGAINDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_STATUS0 */
+#define AGC_STATUS0_PGAINDEX_DEFAULT (_AGC_STATUS0_PGAINDEX_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_STATUS0 */
+#define _AGC_STATUS0_LNAINDEX_SHIFT 16 /**< Shift value for AGC_LNAINDEX */
+#define _AGC_STATUS0_LNAINDEX_MASK 0xF0000UL /**< Bit mask for AGC_LNAINDEX */
+#define _AGC_STATUS0_LNAINDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_STATUS0 */
+#define AGC_STATUS0_LNAINDEX_DEFAULT (_AGC_STATUS0_LNAINDEX_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_STATUS0 */
+#define _AGC_STATUS0_PNINDEX_SHIFT 20 /**< Shift value for AGC_PNINDEX */
+#define _AGC_STATUS0_PNINDEX_MASK 0x1F00000UL /**< Bit mask for AGC_PNINDEX */
+#define _AGC_STATUS0_PNINDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_STATUS0 */
+#define AGC_STATUS0_PNINDEX_DEFAULT (_AGC_STATUS0_PNINDEX_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_STATUS0 */
+#define _AGC_STATUS0_ADCINDEX_SHIFT 25 /**< Shift value for AGC_ADCINDEX */
+#define _AGC_STATUS0_ADCINDEX_MASK 0x6000000UL /**< Bit mask for AGC_ADCINDEX */
+#define _AGC_STATUS0_ADCINDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_STATUS0 */
+#define AGC_STATUS0_ADCINDEX_DEFAULT (_AGC_STATUS0_ADCINDEX_DEFAULT << 25) /**< Shifted mode DEFAULT for AGC_STATUS0 */
+
+/* Bit fields for AGC STATUS1 */
+#define _AGC_STATUS1_RESETVALUE 0x00000000UL /**< Default value for AGC_STATUS1 */
+#define _AGC_STATUS1_MASK 0x3FFFFEFFUL /**< Mask for AGC_STATUS1 */
+#define _AGC_STATUS1_RFPKDLOWLATCNT_SHIFT 18 /**< Shift value for AGC_RFPKDLOWLATCNT */
+#define _AGC_STATUS1_RFPKDLOWLATCNT_MASK 0x3FFC0000UL /**< Bit mask for AGC_RFPKDLOWLATCNT */
+#define _AGC_STATUS1_RFPKDLOWLATCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_STATUS1 */
+#define AGC_STATUS1_RFPKDLOWLATCNT_DEFAULT (_AGC_STATUS1_RFPKDLOWLATCNT_DEFAULT << 18) /**< Shifted mode DEFAULT for AGC_STATUS1 */
+
+/* Bit fields for AGC STATUS2 */
+#define _AGC_STATUS2_RESETVALUE 0x00000000UL /**< Default value for AGC_STATUS2 */
+#define _AGC_STATUS2_MASK 0xFFFF4FFFUL /**< Mask for AGC_STATUS2 */
+#define _AGC_STATUS2_RFPKDHILATCNT_SHIFT 0 /**< Shift value for AGC_RFPKDHILATCNT */
+#define _AGC_STATUS2_RFPKDHILATCNT_MASK 0xFFFUL /**< Bit mask for AGC_RFPKDHILATCNT */
+#define _AGC_STATUS2_RFPKDHILATCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_STATUS2 */
+#define AGC_STATUS2_RFPKDHILATCNT_DEFAULT (_AGC_STATUS2_RFPKDHILATCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_STATUS2 */
+#define AGC_STATUS2_PNDWNUP (0x1UL << 14) /**< Allow PN GAIN UP */
+#define _AGC_STATUS2_PNDWNUP_SHIFT 14 /**< Shift value for AGC_PNDWNUP */
+#define _AGC_STATUS2_PNDWNUP_MASK 0x4000UL /**< Bit mask for AGC_PNDWNUP */
+#define _AGC_STATUS2_PNDWNUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_STATUS2 */
+#define AGC_STATUS2_PNDWNUP_DEFAULT (_AGC_STATUS2_PNDWNUP_DEFAULT << 14) /**< Shifted mode DEFAULT for AGC_STATUS2 */
+#define _AGC_STATUS2_RFPKDPRDCNT_SHIFT 16 /**< Shift value for AGC_RFPKDPRDCNT */
+#define _AGC_STATUS2_RFPKDPRDCNT_MASK 0xFFFF0000UL /**< Bit mask for AGC_RFPKDPRDCNT */
+#define _AGC_STATUS2_RFPKDPRDCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_STATUS2 */
+#define AGC_STATUS2_RFPKDPRDCNT_DEFAULT (_AGC_STATUS2_RFPKDPRDCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_STATUS2 */
+
+/* Bit fields for AGC RSSI */
+#define _AGC_RSSI_RESETVALUE 0x00008000UL /**< Default value for AGC_RSSI */
+#define _AGC_RSSI_MASK 0x0000FFC0UL /**< Mask for AGC_RSSI */
+#define _AGC_RSSI_RSSIFRAC_SHIFT 6 /**< Shift value for AGC_RSSIFRAC */
+#define _AGC_RSSI_RSSIFRAC_MASK 0xC0UL /**< Bit mask for AGC_RSSIFRAC */
+#define _AGC_RSSI_RSSIFRAC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_RSSI */
+#define AGC_RSSI_RSSIFRAC_DEFAULT (_AGC_RSSI_RSSIFRAC_DEFAULT << 6) /**< Shifted mode DEFAULT for AGC_RSSI */
+#define _AGC_RSSI_RSSIINT_SHIFT 8 /**< Shift value for AGC_RSSIINT */
+#define _AGC_RSSI_RSSIINT_MASK 0xFF00UL /**< Bit mask for AGC_RSSIINT */
+#define _AGC_RSSI_RSSIINT_DEFAULT 0x00000080UL /**< Mode DEFAULT for AGC_RSSI */
+#define AGC_RSSI_RSSIINT_DEFAULT (_AGC_RSSI_RSSIINT_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_RSSI */
+
+/* Bit fields for AGC FRAMERSSI */
+#define _AGC_FRAMERSSI_RESETVALUE 0x00008000UL /**< Default value for AGC_FRAMERSSI */
+#define _AGC_FRAMERSSI_MASK 0x0000FFC0UL /**< Mask for AGC_FRAMERSSI */
+#define _AGC_FRAMERSSI_FRAMERSSIFRAC_SHIFT 6 /**< Shift value for AGC_FRAMERSSIFRAC */
+#define _AGC_FRAMERSSI_FRAMERSSIFRAC_MASK 0xC0UL /**< Bit mask for AGC_FRAMERSSIFRAC */
+#define _AGC_FRAMERSSI_FRAMERSSIFRAC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FRAMERSSI */
+#define AGC_FRAMERSSI_FRAMERSSIFRAC_DEFAULT (_AGC_FRAMERSSI_FRAMERSSIFRAC_DEFAULT << 6) /**< Shifted mode DEFAULT for AGC_FRAMERSSI */
+#define _AGC_FRAMERSSI_FRAMERSSIINT_SHIFT 8 /**< Shift value for AGC_FRAMERSSIINT */
+#define _AGC_FRAMERSSI_FRAMERSSIINT_MASK 0xFF00UL /**< Bit mask for AGC_FRAMERSSIINT */
+#define _AGC_FRAMERSSI_FRAMERSSIINT_DEFAULT 0x00000080UL /**< Mode DEFAULT for AGC_FRAMERSSI */
+#define AGC_FRAMERSSI_FRAMERSSIINT_DEFAULT (_AGC_FRAMERSSI_FRAMERSSIINT_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FRAMERSSI */
+
+/* Bit fields for AGC CTRL0 */
+#define _AGC_CTRL0_RESETVALUE 0x2132727FUL /**< Default value for AGC_CTRL0 */
+#define _AGC_CTRL0_MASK 0xFFFFFFFFUL /**< Mask for AGC_CTRL0 */
+#define _AGC_CTRL0_PWRTARGET_SHIFT 0 /**< Shift value for AGC_PWRTARGET */
+#define _AGC_CTRL0_PWRTARGET_MASK 0xFFUL /**< Bit mask for AGC_PWRTARGET */
+#define _AGC_CTRL0_PWRTARGET_DEFAULT 0x0000007FUL /**< Mode DEFAULT for AGC_CTRL0 */
+#define AGC_CTRL0_PWRTARGET_DEFAULT (_AGC_CTRL0_PWRTARGET_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_CTRL0 */
+#define _AGC_CTRL0_MODE_SHIFT 8 /**< Shift value for AGC_MODE */
+#define _AGC_CTRL0_MODE_MASK 0x700UL /**< Bit mask for AGC_MODE */
+#define _AGC_CTRL0_MODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for AGC_CTRL0 */
+#define _AGC_CTRL0_MODE_CONT 0x00000000UL /**< Mode CONT for AGC_CTRL0 */
+#define _AGC_CTRL0_MODE_LOCKPREDET 0x00000001UL /**< Mode LOCKPREDET for AGC_CTRL0 */
+#define _AGC_CTRL0_MODE_LOCKFRAMEDET 0x00000002UL /**< Mode LOCKFRAMEDET for AGC_CTRL0 */
+#define _AGC_CTRL0_MODE_LOCKDSA 0x00000003UL /**< Mode LOCKDSA for AGC_CTRL0 */
+#define AGC_CTRL0_MODE_DEFAULT (_AGC_CTRL0_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_CTRL0 */
+#define AGC_CTRL0_MODE_CONT (_AGC_CTRL0_MODE_CONT << 8) /**< Shifted mode CONT for AGC_CTRL0 */
+#define AGC_CTRL0_MODE_LOCKPREDET (_AGC_CTRL0_MODE_LOCKPREDET << 8) /**< Shifted mode LOCKPREDET for AGC_CTRL0 */
+#define AGC_CTRL0_MODE_LOCKFRAMEDET (_AGC_CTRL0_MODE_LOCKFRAMEDET << 8) /**< Shifted mode LOCKFRAMEDET for AGC_CTRL0 */
+#define AGC_CTRL0_MODE_LOCKDSA (_AGC_CTRL0_MODE_LOCKDSA << 8) /**< Shifted mode LOCKDSA for AGC_CTRL0 */
+#define _AGC_CTRL0_RSSISHIFT_SHIFT 11 /**< Shift value for AGC_RSSISHIFT */
+#define _AGC_CTRL0_RSSISHIFT_MASK 0x7F800UL /**< Bit mask for AGC_RSSISHIFT */
+#define _AGC_CTRL0_RSSISHIFT_DEFAULT 0x0000004EUL /**< Mode DEFAULT for AGC_CTRL0 */
+#define AGC_CTRL0_RSSISHIFT_DEFAULT (_AGC_CTRL0_RSSISHIFT_DEFAULT << 11) /**< Shifted mode DEFAULT for AGC_CTRL0 */
+#define AGC_CTRL0_DISCFLOOPADJ (0x1UL << 19) /**< Disable gain adjustment by CFLOOP */
+#define _AGC_CTRL0_DISCFLOOPADJ_SHIFT 19 /**< Shift value for AGC_DISCFLOOPADJ */
+#define _AGC_CTRL0_DISCFLOOPADJ_MASK 0x80000UL /**< Bit mask for AGC_DISCFLOOPADJ */
+#define _AGC_CTRL0_DISCFLOOPADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL0 */
+#define AGC_CTRL0_DISCFLOOPADJ_DEFAULT (_AGC_CTRL0_DISCFLOOPADJ_DEFAULT << 19) /**< Shifted mode DEFAULT for AGC_CTRL0 */
+#define AGC_CTRL0_CFLOOPNFADJ (0x1UL << 20) /**< Enable NF correction term in SL */
+#define _AGC_CTRL0_CFLOOPNFADJ_SHIFT 20 /**< Shift value for AGC_CFLOOPNFADJ */
+#define _AGC_CTRL0_CFLOOPNFADJ_MASK 0x100000UL /**< Bit mask for AGC_CFLOOPNFADJ */
+#define _AGC_CTRL0_CFLOOPNFADJ_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_CTRL0 */
+#define AGC_CTRL0_CFLOOPNFADJ_DEFAULT (_AGC_CTRL0_CFLOOPNFADJ_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_CTRL0 */
+#define AGC_CTRL0_CFLOOPNEWCALC (0x1UL << 21) /**< Enable new wanted gain calculation in SL */
+#define _AGC_CTRL0_CFLOOPNEWCALC_SHIFT 21 /**< Shift value for AGC_CFLOOPNEWCALC */
+#define _AGC_CTRL0_CFLOOPNEWCALC_MASK 0x200000UL /**< Bit mask for AGC_CFLOOPNEWCALC */
+#define _AGC_CTRL0_CFLOOPNEWCALC_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_CTRL0 */
+#define AGC_CTRL0_CFLOOPNEWCALC_DEFAULT (_AGC_CTRL0_CFLOOPNEWCALC_DEFAULT << 21) /**< Shifted mode DEFAULT for AGC_CTRL0 */
+#define AGC_CTRL0_DISRESETCHPWR (0x1UL << 22) /**< Disable Reset of CHPWR */
+#define _AGC_CTRL0_DISRESETCHPWR_SHIFT 22 /**< Shift value for AGC_DISRESETCHPWR */
+#define _AGC_CTRL0_DISRESETCHPWR_MASK 0x400000UL /**< Bit mask for AGC_DISRESETCHPWR */
+#define _AGC_CTRL0_DISRESETCHPWR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL0 */
+#define AGC_CTRL0_DISRESETCHPWR_DEFAULT (_AGC_CTRL0_DISRESETCHPWR_DEFAULT << 22) /**< Shifted mode DEFAULT for AGC_CTRL0 */
+#define AGC_CTRL0_ADCATTENMODE (0x1UL << 23) /**< ADC Attenuator mode */
+#define _AGC_CTRL0_ADCATTENMODE_SHIFT 23 /**< Shift value for AGC_ADCATTENMODE */
+#define _AGC_CTRL0_ADCATTENMODE_MASK 0x800000UL /**< Bit mask for AGC_ADCATTENMODE */
+#define _AGC_CTRL0_ADCATTENMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL0 */
+#define _AGC_CTRL0_ADCATTENMODE_DISABLE 0x00000000UL /**< Mode DISABLE for AGC_CTRL0 */
+#define _AGC_CTRL0_ADCATTENMODE_NOTMAXGAIN 0x00000001UL /**< Mode NOTMAXGAIN for AGC_CTRL0 */
+#define AGC_CTRL0_ADCATTENMODE_DEFAULT (_AGC_CTRL0_ADCATTENMODE_DEFAULT << 23) /**< Shifted mode DEFAULT for AGC_CTRL0 */
+#define AGC_CTRL0_ADCATTENMODE_DISABLE (_AGC_CTRL0_ADCATTENMODE_DISABLE << 23) /**< Shifted mode DISABLE for AGC_CTRL0 */
+#define AGC_CTRL0_ADCATTENMODE_NOTMAXGAIN (_AGC_CTRL0_ADCATTENMODE_NOTMAXGAIN << 23) /**< Shifted mode NOTMAXGAIN for AGC_CTRL0 */
+#define AGC_CTRL0_FENOTCHMODESEL (0x1UL << 24) /**< FE notch mode select */
+#define _AGC_CTRL0_FENOTCHMODESEL_SHIFT 24 /**< Shift value for AGC_FENOTCHMODESEL */
+#define _AGC_CTRL0_FENOTCHMODESEL_MASK 0x1000000UL /**< Bit mask for AGC_FENOTCHMODESEL */
+#define _AGC_CTRL0_FENOTCHMODESEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_CTRL0 */
+#define _AGC_CTRL0_FENOTCHMODESEL_FENOTCHFILT 0x00000000UL /**< Mode FENOTCHFILT for AGC_CTRL0 */
+#define _AGC_CTRL0_FENOTCHMODESEL_FENOTCHATTN 0x00000001UL /**< Mode FENOTCHATTN for AGC_CTRL0 */
+#define AGC_CTRL0_FENOTCHMODESEL_DEFAULT (_AGC_CTRL0_FENOTCHMODESEL_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_CTRL0 */
+#define AGC_CTRL0_FENOTCHMODESEL_FENOTCHFILT (_AGC_CTRL0_FENOTCHMODESEL_FENOTCHFILT << 24) /**< Shifted mode FENOTCHFILT for AGC_CTRL0 */
+#define AGC_CTRL0_FENOTCHMODESEL_FENOTCHATTN (_AGC_CTRL0_FENOTCHMODESEL_FENOTCHATTN << 24) /**< Shifted mode FENOTCHATTN for AGC_CTRL0 */
+#define _AGC_CTRL0_ADCATTENCODE_SHIFT 25 /**< Shift value for AGC_ADCATTENCODE */
+#define _AGC_CTRL0_ADCATTENCODE_MASK 0x6000000UL /**< Bit mask for AGC_ADCATTENCODE */
+#define _AGC_CTRL0_ADCATTENCODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL0 */
+#define AGC_CTRL0_ADCATTENCODE_DEFAULT (_AGC_CTRL0_ADCATTENCODE_DEFAULT << 25) /**< Shifted mode DEFAULT for AGC_CTRL0 */
+#define AGC_CTRL0_ENRSSIRESET (0x1UL << 27) /**< Enables reset of RSSI and CCA */
+#define _AGC_CTRL0_ENRSSIRESET_SHIFT 27 /**< Shift value for AGC_ENRSSIRESET */
+#define _AGC_CTRL0_ENRSSIRESET_MASK 0x8000000UL /**< Bit mask for AGC_ENRSSIRESET */
+#define _AGC_CTRL0_ENRSSIRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL0 */
+#define AGC_CTRL0_ENRSSIRESET_DEFAULT (_AGC_CTRL0_ENRSSIRESET_DEFAULT << 27) /**< Shifted mode DEFAULT for AGC_CTRL0 */
+#define AGC_CTRL0_DSADISCFLOOP (0x1UL << 28) /**< Disable channel filter loop */
+#define _AGC_CTRL0_DSADISCFLOOP_SHIFT 28 /**< Shift value for AGC_DSADISCFLOOP */
+#define _AGC_CTRL0_DSADISCFLOOP_MASK 0x10000000UL /**< Bit mask for AGC_DSADISCFLOOP */
+#define _AGC_CTRL0_DSADISCFLOOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL0 */
+#define AGC_CTRL0_DSADISCFLOOP_DEFAULT (_AGC_CTRL0_DSADISCFLOOP_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_CTRL0 */
+#define AGC_CTRL0_DISPNGAINUP (0x1UL << 29) /**< Disable PN gain increase */
+#define _AGC_CTRL0_DISPNGAINUP_SHIFT 29 /**< Shift value for AGC_DISPNGAINUP */
+#define _AGC_CTRL0_DISPNGAINUP_MASK 0x20000000UL /**< Bit mask for AGC_DISPNGAINUP */
+#define _AGC_CTRL0_DISPNGAINUP_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_CTRL0 */
+#define AGC_CTRL0_DISPNGAINUP_DEFAULT (_AGC_CTRL0_DISPNGAINUP_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_CTRL0 */
+#define AGC_CTRL0_DISPNDWNCOMP (0x1UL << 30) /**< Disable PN gain decrease compensation */
+#define _AGC_CTRL0_DISPNDWNCOMP_SHIFT 30 /**< Shift value for AGC_DISPNDWNCOMP */
+#define _AGC_CTRL0_DISPNDWNCOMP_MASK 0x40000000UL /**< Bit mask for AGC_DISPNDWNCOMP */
+#define _AGC_CTRL0_DISPNDWNCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL0 */
+#define AGC_CTRL0_DISPNDWNCOMP_DEFAULT (_AGC_CTRL0_DISPNDWNCOMP_DEFAULT << 30) /**< Shifted mode DEFAULT for AGC_CTRL0 */
+#define AGC_CTRL0_AGCRST (0x1UL << 31) /**< AGC reset */
+#define _AGC_CTRL0_AGCRST_SHIFT 31 /**< Shift value for AGC_AGCRST */
+#define _AGC_CTRL0_AGCRST_MASK 0x80000000UL /**< Bit mask for AGC_AGCRST */
+#define _AGC_CTRL0_AGCRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL0 */
+#define AGC_CTRL0_AGCRST_DEFAULT (_AGC_CTRL0_AGCRST_DEFAULT << 31) /**< Shifted mode DEFAULT for AGC_CTRL0 */
+
+/* Bit fields for AGC CTRL1 */
+#define _AGC_CTRL1_RESETVALUE 0x00001300UL /**< Default value for AGC_CTRL1 */
+#define _AGC_CTRL1_MASK 0x0007FFFFUL /**< Mask for AGC_CTRL1 */
+#define _AGC_CTRL1_CCATHRSH_SHIFT 0 /**< Shift value for AGC_CCATHRSH */
+#define _AGC_CTRL1_CCATHRSH_MASK 0xFFUL /**< Bit mask for AGC_CCATHRSH */
+#define _AGC_CTRL1_CCATHRSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL1 */
+#define AGC_CTRL1_CCATHRSH_DEFAULT (_AGC_CTRL1_CCATHRSH_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_CTRL1 */
+#define _AGC_CTRL1_RSSIPERIOD_SHIFT 8 /**< Shift value for AGC_RSSIPERIOD */
+#define _AGC_CTRL1_RSSIPERIOD_MASK 0xF00UL /**< Bit mask for AGC_RSSIPERIOD */
+#define _AGC_CTRL1_RSSIPERIOD_DEFAULT 0x00000003UL /**< Mode DEFAULT for AGC_CTRL1 */
+#define AGC_CTRL1_RSSIPERIOD_DEFAULT (_AGC_CTRL1_RSSIPERIOD_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_CTRL1 */
+#define _AGC_CTRL1_PWRPERIOD_SHIFT 12 /**< Shift value for AGC_PWRPERIOD */
+#define _AGC_CTRL1_PWRPERIOD_MASK 0x7000UL /**< Bit mask for AGC_PWRPERIOD */
+#define _AGC_CTRL1_PWRPERIOD_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_CTRL1 */
+#define AGC_CTRL1_PWRPERIOD_DEFAULT (_AGC_CTRL1_PWRPERIOD_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_CTRL1 */
+#define _AGC_CTRL1_CCAMODE_SHIFT 15 /**< Shift value for AGC_CCAMODE */
+#define _AGC_CTRL1_CCAMODE_MASK 0x18000UL /**< Bit mask for AGC_CCAMODE */
+#define _AGC_CTRL1_CCAMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL1 */
+#define _AGC_CTRL1_CCAMODE_MODE1 0x00000000UL /**< Mode MODE1 for AGC_CTRL1 */
+#define _AGC_CTRL1_CCAMODE_MODE2 0x00000001UL /**< Mode MODE2 for AGC_CTRL1 */
+#define _AGC_CTRL1_CCAMODE_MODE3 0x00000002UL /**< Mode MODE3 for AGC_CTRL1 */
+#define _AGC_CTRL1_CCAMODE_MODE4 0x00000003UL /**< Mode MODE4 for AGC_CTRL1 */
+#define AGC_CTRL1_CCAMODE_DEFAULT (_AGC_CTRL1_CCAMODE_DEFAULT << 15) /**< Shifted mode DEFAULT for AGC_CTRL1 */
+#define AGC_CTRL1_CCAMODE_MODE1 (_AGC_CTRL1_CCAMODE_MODE1 << 15) /**< Shifted mode MODE1 for AGC_CTRL1 */
+#define AGC_CTRL1_CCAMODE_MODE2 (_AGC_CTRL1_CCAMODE_MODE2 << 15) /**< Shifted mode MODE2 for AGC_CTRL1 */
+#define AGC_CTRL1_CCAMODE_MODE3 (_AGC_CTRL1_CCAMODE_MODE3 << 15) /**< Shifted mode MODE3 for AGC_CTRL1 */
+#define AGC_CTRL1_CCAMODE_MODE4 (_AGC_CTRL1_CCAMODE_MODE4 << 15) /**< Shifted mode MODE4 for AGC_CTRL1 */
+#define AGC_CTRL1_CCAMODE3LOGIC (0x1UL << 17) /**< Select mode3 logic */
+#define _AGC_CTRL1_CCAMODE3LOGIC_SHIFT 17 /**< Shift value for AGC_CCAMODE3LOGIC */
+#define _AGC_CTRL1_CCAMODE3LOGIC_MASK 0x20000UL /**< Bit mask for AGC_CCAMODE3LOGIC */
+#define _AGC_CTRL1_CCAMODE3LOGIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL1 */
+#define _AGC_CTRL1_CCAMODE3LOGIC_AND 0x00000000UL /**< Mode AND for AGC_CTRL1 */
+#define _AGC_CTRL1_CCAMODE3LOGIC_OR 0x00000001UL /**< Mode OR for AGC_CTRL1 */
+#define AGC_CTRL1_CCAMODE3LOGIC_DEFAULT (_AGC_CTRL1_CCAMODE3LOGIC_DEFAULT << 17) /**< Shifted mode DEFAULT for AGC_CTRL1 */
+#define AGC_CTRL1_CCAMODE3LOGIC_AND (_AGC_CTRL1_CCAMODE3LOGIC_AND << 17) /**< Shifted mode AND for AGC_CTRL1 */
+#define AGC_CTRL1_CCAMODE3LOGIC_OR (_AGC_CTRL1_CCAMODE3LOGIC_OR << 17) /**< Shifted mode OR for AGC_CTRL1 */
+#define AGC_CTRL1_CCASWCTRL (0x1UL << 18) /**< SW control over CCA */
+#define _AGC_CTRL1_CCASWCTRL_SHIFT 18 /**< Shift value for AGC_CCASWCTRL */
+#define _AGC_CTRL1_CCASWCTRL_MASK 0x40000UL /**< Bit mask for AGC_CCASWCTRL */
+#define _AGC_CTRL1_CCASWCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL1 */
+#define AGC_CTRL1_CCASWCTRL_DEFAULT (_AGC_CTRL1_CCASWCTRL_DEFAULT << 18) /**< Shifted mode DEFAULT for AGC_CTRL1 */
+
+/* Bit fields for AGC CTRL2 */
+#define _AGC_CTRL2_RESETVALUE 0x0000610AUL /**< Default value for AGC_CTRL2 */
+#define _AGC_CTRL2_MASK 0xFFFFFFFFUL /**< Mask for AGC_CTRL2 */
+#define AGC_CTRL2_DMASEL (0x1UL << 0) /**< DMA select */
+#define _AGC_CTRL2_DMASEL_SHIFT 0 /**< Shift value for AGC_DMASEL */
+#define _AGC_CTRL2_DMASEL_MASK 0x1UL /**< Bit mask for AGC_DMASEL */
+#define _AGC_CTRL2_DMASEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL2 */
+#define _AGC_CTRL2_DMASEL_RSSI 0x00000000UL /**< Mode RSSI for AGC_CTRL2 */
+#define _AGC_CTRL2_DMASEL_GAIN 0x00000001UL /**< Mode GAIN for AGC_CTRL2 */
+#define AGC_CTRL2_DMASEL_DEFAULT (_AGC_CTRL2_DMASEL_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_CTRL2 */
+#define AGC_CTRL2_DMASEL_RSSI (_AGC_CTRL2_DMASEL_RSSI << 0) /**< Shifted mode RSSI for AGC_CTRL2 */
+#define AGC_CTRL2_DMASEL_GAIN (_AGC_CTRL2_DMASEL_GAIN << 0) /**< Shifted mode GAIN for AGC_CTRL2 */
+#define AGC_CTRL2_SAFEMODE (0x1UL << 1) /**< AGC safe mode */
+#define _AGC_CTRL2_SAFEMODE_SHIFT 1 /**< Shift value for AGC_SAFEMODE */
+#define _AGC_CTRL2_SAFEMODE_MASK 0x2UL /**< Bit mask for AGC_SAFEMODE */
+#define _AGC_CTRL2_SAFEMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_CTRL2 */
+#define AGC_CTRL2_SAFEMODE_DEFAULT (_AGC_CTRL2_SAFEMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for AGC_CTRL2 */
+#define _AGC_CTRL2_SAFEMODETHD_SHIFT 2 /**< Shift value for AGC_SAFEMODETHD */
+#define _AGC_CTRL2_SAFEMODETHD_MASK 0x1CUL /**< Bit mask for AGC_SAFEMODETHD */
+#define _AGC_CTRL2_SAFEMODETHD_DEFAULT 0x00000002UL /**< Mode DEFAULT for AGC_CTRL2 */
+#define AGC_CTRL2_SAFEMODETHD_DEFAULT (_AGC_CTRL2_SAFEMODETHD_DEFAULT << 2) /**< Shifted mode DEFAULT for AGC_CTRL2 */
+#define _AGC_CTRL2_REHICNTTHD_SHIFT 5 /**< Shift value for AGC_REHICNTTHD */
+#define _AGC_CTRL2_REHICNTTHD_MASK 0x1FE0UL /**< Bit mask for AGC_REHICNTTHD */
+#define _AGC_CTRL2_REHICNTTHD_DEFAULT 0x00000008UL /**< Mode DEFAULT for AGC_CTRL2 */
+#define AGC_CTRL2_REHICNTTHD_DEFAULT (_AGC_CTRL2_REHICNTTHD_DEFAULT << 5) /**< Shifted mode DEFAULT for AGC_CTRL2 */
+#define _AGC_CTRL2_RELOTHD_SHIFT 13 /**< Shift value for AGC_RELOTHD */
+#define _AGC_CTRL2_RELOTHD_MASK 0xE000UL /**< Bit mask for AGC_RELOTHD */
+#define _AGC_CTRL2_RELOTHD_DEFAULT 0x00000003UL /**< Mode DEFAULT for AGC_CTRL2 */
+#define AGC_CTRL2_RELOTHD_DEFAULT (_AGC_CTRL2_RELOTHD_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_CTRL2 */
+#define _AGC_CTRL2_RELBYCHPWR_SHIFT 16 /**< Shift value for AGC_RELBYCHPWR */
+#define _AGC_CTRL2_RELBYCHPWR_MASK 0x30000UL /**< Bit mask for AGC_RELBYCHPWR */
+#define _AGC_CTRL2_RELBYCHPWR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL2 */
+#define _AGC_CTRL2_RELBYCHPWR_LO_CNT 0x00000000UL /**< Mode LO_CNT for AGC_CTRL2 */
+#define _AGC_CTRL2_RELBYCHPWR_PWR 0x00000001UL /**< Mode PWR for AGC_CTRL2 */
+#define _AGC_CTRL2_RELBYCHPWR_LO_CNT_PWR 0x00000002UL /**< Mode LO_CNT_PWR for AGC_CTRL2 */
+#define _AGC_CTRL2_RELBYCHPWR_LO_CNT_AND_PWR 0x00000003UL /**< Mode LO_CNT_AND_PWR for AGC_CTRL2 */
+#define AGC_CTRL2_RELBYCHPWR_DEFAULT (_AGC_CTRL2_RELBYCHPWR_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_CTRL2 */
+#define AGC_CTRL2_RELBYCHPWR_LO_CNT (_AGC_CTRL2_RELBYCHPWR_LO_CNT << 16) /**< Shifted mode LO_CNT for AGC_CTRL2 */
+#define AGC_CTRL2_RELBYCHPWR_PWR (_AGC_CTRL2_RELBYCHPWR_PWR << 16) /**< Shifted mode PWR for AGC_CTRL2 */
+#define AGC_CTRL2_RELBYCHPWR_LO_CNT_PWR (_AGC_CTRL2_RELBYCHPWR_LO_CNT_PWR << 16) /**< Shifted mode LO_CNT_PWR for AGC_CTRL2 */
+#define AGC_CTRL2_RELBYCHPWR_LO_CNT_AND_PWR (_AGC_CTRL2_RELBYCHPWR_LO_CNT_AND_PWR << 16) /**< Shifted mode LO_CNT_AND_PWR for AGC_CTRL2 */
+#define _AGC_CTRL2_RELTARGETPWR_SHIFT 18 /**< Shift value for AGC_RELTARGETPWR */
+#define _AGC_CTRL2_RELTARGETPWR_MASK 0x3FC0000UL /**< Bit mask for AGC_RELTARGETPWR */
+#define _AGC_CTRL2_RELTARGETPWR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL2 */
+#define AGC_CTRL2_RELTARGETPWR_DEFAULT (_AGC_CTRL2_RELTARGETPWR_DEFAULT << 18) /**< Shifted mode DEFAULT for AGC_CTRL2 */
+#define _AGC_CTRL2_RSSICCASUB_SHIFT 26 /**< Shift value for AGC_RSSICCASUB */
+#define _AGC_CTRL2_RSSICCASUB_MASK 0x1C000000UL /**< Bit mask for AGC_RSSICCASUB */
+#define _AGC_CTRL2_RSSICCASUB_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL2 */
+#define AGC_CTRL2_RSSICCASUB_DEFAULT (_AGC_CTRL2_RSSICCASUB_DEFAULT << 26) /**< Shifted mode DEFAULT for AGC_CTRL2 */
+#define AGC_CTRL2_DEBCNTRST (0x1UL << 29) /**< Debonce CNT Reset MODE */
+#define _AGC_CTRL2_DEBCNTRST_SHIFT 29 /**< Shift value for AGC_DEBCNTRST */
+#define _AGC_CTRL2_DEBCNTRST_MASK 0x20000000UL /**< Bit mask for AGC_DEBCNTRST */
+#define _AGC_CTRL2_DEBCNTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL2 */
+#define AGC_CTRL2_DEBCNTRST_DEFAULT (_AGC_CTRL2_DEBCNTRST_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_CTRL2 */
+#define AGC_CTRL2_PRSDEBUGEN (0x1UL << 30) /**< PRS Debug Enable */
+#define _AGC_CTRL2_PRSDEBUGEN_SHIFT 30 /**< Shift value for AGC_PRSDEBUGEN */
+#define _AGC_CTRL2_PRSDEBUGEN_MASK 0x40000000UL /**< Bit mask for AGC_PRSDEBUGEN */
+#define _AGC_CTRL2_PRSDEBUGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL2 */
+#define AGC_CTRL2_PRSDEBUGEN_DEFAULT (_AGC_CTRL2_PRSDEBUGEN_DEFAULT << 30) /**< Shifted mode DEFAULT for AGC_CTRL2 */
+#define AGC_CTRL2_DISRFPKD (0x1UL << 31) /**< Disable RF PEAKDET */
+#define _AGC_CTRL2_DISRFPKD_SHIFT 31 /**< Shift value for AGC_DISRFPKD */
+#define _AGC_CTRL2_DISRFPKD_MASK 0x80000000UL /**< Bit mask for AGC_DISRFPKD */
+#define _AGC_CTRL2_DISRFPKD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL2 */
+#define AGC_CTRL2_DISRFPKD_DEFAULT (_AGC_CTRL2_DISRFPKD_DEFAULT << 31) /**< Shifted mode DEFAULT for AGC_CTRL2 */
+
+/* Bit fields for AGC CTRL3 */
+#define _AGC_CTRL3_RESETVALUE 0x5140A800UL /**< Default value for AGC_CTRL3 */
+#define _AGC_CTRL3_MASK 0xFFFFFFFFUL /**< Mask for AGC_CTRL3 */
+#define AGC_CTRL3_IFPKDDEB (0x1UL << 0) /**< IF PEAKDET debounce mode enable */
+#define _AGC_CTRL3_IFPKDDEB_SHIFT 0 /**< Shift value for AGC_IFPKDDEB */
+#define _AGC_CTRL3_IFPKDDEB_MASK 0x1UL /**< Bit mask for AGC_IFPKDDEB */
+#define _AGC_CTRL3_IFPKDDEB_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL3 */
+#define AGC_CTRL3_IFPKDDEB_DEFAULT (_AGC_CTRL3_IFPKDDEB_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_CTRL3 */
+#define _AGC_CTRL3_IFPKDDEBTHD_SHIFT 1 /**< Shift value for AGC_IFPKDDEBTHD */
+#define _AGC_CTRL3_IFPKDDEBTHD_MASK 0x6UL /**< Bit mask for AGC_IFPKDDEBTHD */
+#define _AGC_CTRL3_IFPKDDEBTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL3 */
+#define AGC_CTRL3_IFPKDDEBTHD_DEFAULT (_AGC_CTRL3_IFPKDDEBTHD_DEFAULT << 1) /**< Shifted mode DEFAULT for AGC_CTRL3 */
+#define _AGC_CTRL3_IFPKDDEBPRD_SHIFT 3 /**< Shift value for AGC_IFPKDDEBPRD */
+#define _AGC_CTRL3_IFPKDDEBPRD_MASK 0x1F8UL /**< Bit mask for AGC_IFPKDDEBPRD */
+#define _AGC_CTRL3_IFPKDDEBPRD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL3 */
+#define AGC_CTRL3_IFPKDDEBPRD_DEFAULT (_AGC_CTRL3_IFPKDDEBPRD_DEFAULT << 3) /**< Shifted mode DEFAULT for AGC_CTRL3 */
+#define _AGC_CTRL3_IFPKDDEBRST_SHIFT 9 /**< Shift value for AGC_IFPKDDEBRST */
+#define _AGC_CTRL3_IFPKDDEBRST_MASK 0x1E00UL /**< Bit mask for AGC_IFPKDDEBRST */
+#define _AGC_CTRL3_IFPKDDEBRST_DEFAULT 0x00000004UL /**< Mode DEFAULT for AGC_CTRL3 */
+#define AGC_CTRL3_IFPKDDEBRST_DEFAULT (_AGC_CTRL3_IFPKDDEBRST_DEFAULT << 9) /**< Shifted mode DEFAULT for AGC_CTRL3 */
+#define AGC_CTRL3_RFPKDDEB (0x1UL << 13) /**< RF PEAKDET debounce mode enable */
+#define _AGC_CTRL3_RFPKDDEB_SHIFT 13 /**< Shift value for AGC_RFPKDDEB */
+#define _AGC_CTRL3_RFPKDDEB_MASK 0x2000UL /**< Bit mask for AGC_RFPKDDEB */
+#define _AGC_CTRL3_RFPKDDEB_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_CTRL3 */
+#define AGC_CTRL3_RFPKDDEB_DEFAULT (_AGC_CTRL3_RFPKDDEB_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_CTRL3 */
+#define _AGC_CTRL3_RFPKDDEBTHD_SHIFT 14 /**< Shift value for AGC_RFPKDDEBTHD */
+#define _AGC_CTRL3_RFPKDDEBTHD_MASK 0x7C000UL /**< Bit mask for AGC_RFPKDDEBTHD */
+#define _AGC_CTRL3_RFPKDDEBTHD_DEFAULT 0x00000002UL /**< Mode DEFAULT for AGC_CTRL3 */
+#define AGC_CTRL3_RFPKDDEBTHD_DEFAULT (_AGC_CTRL3_RFPKDDEBTHD_DEFAULT << 14) /**< Shifted mode DEFAULT for AGC_CTRL3 */
+#define _AGC_CTRL3_RFPKDDEBPRD_SHIFT 19 /**< Shift value for AGC_RFPKDDEBPRD */
+#define _AGC_CTRL3_RFPKDDEBPRD_MASK 0x7F80000UL /**< Bit mask for AGC_RFPKDDEBPRD */
+#define _AGC_CTRL3_RFPKDDEBPRD_DEFAULT 0x00000028UL /**< Mode DEFAULT for AGC_CTRL3 */
+#define AGC_CTRL3_RFPKDDEBPRD_DEFAULT (_AGC_CTRL3_RFPKDDEBPRD_DEFAULT << 19) /**< Shifted mode DEFAULT for AGC_CTRL3 */
+#define _AGC_CTRL3_RFPKDDEBRST_SHIFT 27 /**< Shift value for AGC_RFPKDDEBRST */
+#define _AGC_CTRL3_RFPKDDEBRST_MASK 0xF8000000UL /**< Bit mask for AGC_RFPKDDEBRST */
+#define _AGC_CTRL3_RFPKDDEBRST_DEFAULT 0x0000000AUL /**< Mode DEFAULT for AGC_CTRL3 */
+#define AGC_CTRL3_RFPKDDEBRST_DEFAULT (_AGC_CTRL3_RFPKDDEBRST_DEFAULT << 27) /**< Shifted mode DEFAULT for AGC_CTRL3 */
+
+/* Bit fields for AGC CTRL4 */
+#define _AGC_CTRL4_RESETVALUE 0x0000000EUL /**< Default value for AGC_CTRL4 */
+#define _AGC_CTRL4_MASK 0xFF80FFFFUL /**< Mask for AGC_CTRL4 */
+#define _AGC_CTRL4_PERIODRFPKD_SHIFT 0 /**< Shift value for AGC_PERIODRFPKD */
+#define _AGC_CTRL4_PERIODRFPKD_MASK 0xFFFFUL /**< Bit mask for AGC_PERIODRFPKD */
+#define _AGC_CTRL4_PERIODRFPKD_DEFAULT 0x0000000EUL /**< Mode DEFAULT for AGC_CTRL4 */
+#define AGC_CTRL4_PERIODRFPKD_DEFAULT (_AGC_CTRL4_PERIODRFPKD_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_CTRL4 */
+#define AGC_CTRL4_DISRFPKDCNTRST (0x1UL << 23) /**< Disable PGOCELOT-5333 fix */
+#define _AGC_CTRL4_DISRFPKDCNTRST_SHIFT 23 /**< Shift value for AGC_DISRFPKDCNTRST */
+#define _AGC_CTRL4_DISRFPKDCNTRST_MASK 0x800000UL /**< Bit mask for AGC_DISRFPKDCNTRST */
+#define _AGC_CTRL4_DISRFPKDCNTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL4 */
+#define AGC_CTRL4_DISRFPKDCNTRST_DEFAULT (_AGC_CTRL4_DISRFPKDCNTRST_DEFAULT << 23) /**< Shifted mode DEFAULT for AGC_CTRL4 */
+#define AGC_CTRL4_DISRSTCONDI (0x1UL << 24) /**< Disable PGOCELOT-5333 fix */
+#define _AGC_CTRL4_DISRSTCONDI_SHIFT 24 /**< Shift value for AGC_DISRSTCONDI */
+#define _AGC_CTRL4_DISRSTCONDI_MASK 0x1000000UL /**< Bit mask for AGC_DISRSTCONDI */
+#define _AGC_CTRL4_DISRSTCONDI_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL4 */
+#define AGC_CTRL4_DISRSTCONDI_DEFAULT (_AGC_CTRL4_DISRSTCONDI_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_CTRL4 */
+#define _AGC_CTRL4_RFPKDPRDGEAR_SHIFT 25 /**< Shift value for AGC_RFPKDPRDGEAR */
+#define _AGC_CTRL4_RFPKDPRDGEAR_MASK 0xE000000UL /**< Bit mask for AGC_RFPKDPRDGEAR */
+#define _AGC_CTRL4_RFPKDPRDGEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL4 */
+#define AGC_CTRL4_RFPKDPRDGEAR_DEFAULT (_AGC_CTRL4_RFPKDPRDGEAR_DEFAULT << 25) /**< Shifted mode DEFAULT for AGC_CTRL4 */
+#define AGC_CTRL4_RFPKDSYNCSEL (0x1UL << 28) /**< SYNC RF PKD OUTPUT SELECT */
+#define _AGC_CTRL4_RFPKDSYNCSEL_SHIFT 28 /**< Shift value for AGC_RFPKDSYNCSEL */
+#define _AGC_CTRL4_RFPKDSYNCSEL_MASK 0x10000000UL /**< Bit mask for AGC_RFPKDSYNCSEL */
+#define _AGC_CTRL4_RFPKDSYNCSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL4 */
+#define AGC_CTRL4_RFPKDSYNCSEL_DEFAULT (_AGC_CTRL4_RFPKDSYNCSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_CTRL4 */
+#define AGC_CTRL4_RFPKDSEL (0x1UL << 29) /**< RF PKD OUTPUT SELECT */
+#define _AGC_CTRL4_RFPKDSEL_SHIFT 29 /**< Shift value for AGC_RFPKDSEL */
+#define _AGC_CTRL4_RFPKDSEL_MASK 0x20000000UL /**< Bit mask for AGC_RFPKDSEL */
+#define _AGC_CTRL4_RFPKDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL4 */
+#define AGC_CTRL4_RFPKDSEL_DEFAULT (_AGC_CTRL4_RFPKDSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_CTRL4 */
+#define AGC_CTRL4_FRZPKDEN (0x1UL << 30) /**< PKD Freeze Enable */
+#define _AGC_CTRL4_FRZPKDEN_SHIFT 30 /**< Shift value for AGC_FRZPKDEN */
+#define _AGC_CTRL4_FRZPKDEN_MASK 0x40000000UL /**< Bit mask for AGC_FRZPKDEN */
+#define _AGC_CTRL4_FRZPKDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL4 */
+#define AGC_CTRL4_FRZPKDEN_DEFAULT (_AGC_CTRL4_FRZPKDEN_DEFAULT << 30) /**< Shifted mode DEFAULT for AGC_CTRL4 */
+#define AGC_CTRL4_RFPKDCNTEN (0x1UL << 31) /**< Counter-based RFPKD Enable */
+#define _AGC_CTRL4_RFPKDCNTEN_SHIFT 31 /**< Shift value for AGC_RFPKDCNTEN */
+#define _AGC_CTRL4_RFPKDCNTEN_MASK 0x80000000UL /**< Bit mask for AGC_RFPKDCNTEN */
+#define _AGC_CTRL4_RFPKDCNTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL4 */
+#define AGC_CTRL4_RFPKDCNTEN_DEFAULT (_AGC_CTRL4_RFPKDCNTEN_DEFAULT << 31) /**< Shifted mode DEFAULT for AGC_CTRL4 */
+
+/* Bit fields for AGC CTRL5 */
+#define _AGC_CTRL5_RESETVALUE 0x00000000UL /**< Default value for AGC_CTRL5 */
+#define _AGC_CTRL5_MASK 0xC0FFFFFFUL /**< Mask for AGC_CTRL5 */
+#define _AGC_CTRL5_PNUPDISTHD_SHIFT 0 /**< Shift value for AGC_PNUPDISTHD */
+#define _AGC_CTRL5_PNUPDISTHD_MASK 0xFFFUL /**< Bit mask for AGC_PNUPDISTHD */
+#define _AGC_CTRL5_PNUPDISTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL5 */
+#define AGC_CTRL5_PNUPDISTHD_DEFAULT (_AGC_CTRL5_PNUPDISTHD_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_CTRL5 */
+#define _AGC_CTRL5_PNUPRELTHD_SHIFT 12 /**< Shift value for AGC_PNUPRELTHD */
+#define _AGC_CTRL5_PNUPRELTHD_MASK 0xFFF000UL /**< Bit mask for AGC_PNUPRELTHD */
+#define _AGC_CTRL5_PNUPRELTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL5 */
+#define AGC_CTRL5_PNUPRELTHD_DEFAULT (_AGC_CTRL5_PNUPRELTHD_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_CTRL5 */
+#define AGC_CTRL5_SEQPNUPALLOW (0x1UL << 30) /**< SEQ Set PN GAIN UP ALLOW */
+#define _AGC_CTRL5_SEQPNUPALLOW_SHIFT 30 /**< Shift value for AGC_SEQPNUPALLOW */
+#define _AGC_CTRL5_SEQPNUPALLOW_MASK 0x40000000UL /**< Bit mask for AGC_SEQPNUPALLOW */
+#define _AGC_CTRL5_SEQPNUPALLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL5 */
+#define AGC_CTRL5_SEQPNUPALLOW_DEFAULT (_AGC_CTRL5_SEQPNUPALLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for AGC_CTRL5 */
+#define AGC_CTRL5_SEQRFPKDEN (0x1UL << 31) /**< SEQ-based RFPKD Enable */
+#define _AGC_CTRL5_SEQRFPKDEN_SHIFT 31 /**< Shift value for AGC_SEQRFPKDEN */
+#define _AGC_CTRL5_SEQRFPKDEN_MASK 0x80000000UL /**< Bit mask for AGC_SEQRFPKDEN */
+#define _AGC_CTRL5_SEQRFPKDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL5 */
+#define AGC_CTRL5_SEQRFPKDEN_DEFAULT (_AGC_CTRL5_SEQRFPKDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for AGC_CTRL5 */
+
+/* Bit fields for AGC CTRL6 */
+#define _AGC_CTRL6_RESETVALUE 0x0003AAA8UL /**< Default value for AGC_CTRL6 */
+#define _AGC_CTRL6_MASK 0x7FFFFFFFUL /**< Mask for AGC_CTRL6 */
+#define _AGC_CTRL6_DUALRFPKDDEC_SHIFT 0 /**< Shift value for AGC_DUALRFPKDDEC */
+#define _AGC_CTRL6_DUALRFPKDDEC_MASK 0x3FFFFUL /**< Bit mask for AGC_DUALRFPKDDEC */
+#define _AGC_CTRL6_DUALRFPKDDEC_DEFAULT 0x0003AAA8UL /**< Mode DEFAULT for AGC_CTRL6 */
+#define AGC_CTRL6_DUALRFPKDDEC_DEFAULT (_AGC_CTRL6_DUALRFPKDDEC_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_CTRL6 */
+#define AGC_CTRL6_ENDUALRFPKD (0x1UL << 18) /**< Enable dual RFPKD */
+#define _AGC_CTRL6_ENDUALRFPKD_SHIFT 18 /**< Shift value for AGC_ENDUALRFPKD */
+#define _AGC_CTRL6_ENDUALRFPKD_MASK 0x40000UL /**< Bit mask for AGC_ENDUALRFPKD */
+#define _AGC_CTRL6_ENDUALRFPKD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL6 */
+#define AGC_CTRL6_ENDUALRFPKD_DEFAULT (_AGC_CTRL6_ENDUALRFPKD_DEFAULT << 18) /**< Shifted mode DEFAULT for AGC_CTRL6 */
+#define _AGC_CTRL6_GAINDETTHD_SHIFT 19 /**< Shift value for AGC_GAINDETTHD */
+#define _AGC_CTRL6_GAINDETTHD_MASK 0x7FF80000UL /**< Bit mask for AGC_GAINDETTHD */
+#define _AGC_CTRL6_GAINDETTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL6 */
+#define AGC_CTRL6_GAINDETTHD_DEFAULT (_AGC_CTRL6_GAINDETTHD_DEFAULT << 19) /**< Shifted mode DEFAULT for AGC_CTRL6 */
+
+/* Bit fields for AGC CTRL7 */
+#define _AGC_CTRL7_RESETVALUE 0x00000000UL /**< Default value for AGC_CTRL7 */
+#define _AGC_CTRL7_MASK 0x01FFFFFFUL /**< Mask for AGC_CTRL7 */
+#define _AGC_CTRL7_SUBDEN_SHIFT 0 /**< Shift value for AGC_SUBDEN */
+#define _AGC_CTRL7_SUBDEN_MASK 0xFFUL /**< Bit mask for AGC_SUBDEN */
+#define _AGC_CTRL7_SUBDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL7 */
+#define AGC_CTRL7_SUBDEN_DEFAULT (_AGC_CTRL7_SUBDEN_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_CTRL7 */
+#define _AGC_CTRL7_SUBINT_SHIFT 8 /**< Shift value for AGC_SUBINT */
+#define _AGC_CTRL7_SUBINT_MASK 0xFF00UL /**< Bit mask for AGC_SUBINT */
+#define _AGC_CTRL7_SUBINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL7 */
+#define AGC_CTRL7_SUBINT_DEFAULT (_AGC_CTRL7_SUBINT_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_CTRL7 */
+#define _AGC_CTRL7_SUBNUM_SHIFT 16 /**< Shift value for AGC_SUBNUM */
+#define _AGC_CTRL7_SUBNUM_MASK 0xFF0000UL /**< Bit mask for AGC_SUBNUM */
+#define _AGC_CTRL7_SUBNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL7 */
+#define AGC_CTRL7_SUBNUM_DEFAULT (_AGC_CTRL7_SUBNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_CTRL7 */
+#define AGC_CTRL7_SUBPERIOD (0x1UL << 24) /**< Subperiod */
+#define _AGC_CTRL7_SUBPERIOD_SHIFT 24 /**< Shift value for AGC_SUBPERIOD */
+#define _AGC_CTRL7_SUBPERIOD_MASK 0x1000000UL /**< Bit mask for AGC_SUBPERIOD */
+#define _AGC_CTRL7_SUBPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CTRL7 */
+#define AGC_CTRL7_SUBPERIOD_DEFAULT (_AGC_CTRL7_SUBPERIOD_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_CTRL7 */
+
+/* Bit fields for AGC RSSISTEPTHR */
+#define _AGC_RSSISTEPTHR_RESETVALUE 0x00000000UL /**< Default value for AGC_RSSISTEPTHR */
+#define _AGC_RSSISTEPTHR_MASK 0x3FFFFFFFUL /**< Mask for AGC_RSSISTEPTHR */
+#define _AGC_RSSISTEPTHR_POSSTEPTHR_SHIFT 0 /**< Shift value for AGC_POSSTEPTHR */
+#define _AGC_RSSISTEPTHR_POSSTEPTHR_MASK 0xFFUL /**< Bit mask for AGC_POSSTEPTHR */
+#define _AGC_RSSISTEPTHR_POSSTEPTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_RSSISTEPTHR */
+#define AGC_RSSISTEPTHR_POSSTEPTHR_DEFAULT (_AGC_RSSISTEPTHR_POSSTEPTHR_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_RSSISTEPTHR */
+#define _AGC_RSSISTEPTHR_NEGSTEPTHR_SHIFT 8 /**< Shift value for AGC_NEGSTEPTHR */
+#define _AGC_RSSISTEPTHR_NEGSTEPTHR_MASK 0xFF00UL /**< Bit mask for AGC_NEGSTEPTHR */
+#define _AGC_RSSISTEPTHR_NEGSTEPTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_RSSISTEPTHR */
+#define AGC_RSSISTEPTHR_NEGSTEPTHR_DEFAULT (_AGC_RSSISTEPTHR_NEGSTEPTHR_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_RSSISTEPTHR */
+#define AGC_RSSISTEPTHR_STEPPER (0x1UL << 16) /**< Step Period */
+#define _AGC_RSSISTEPTHR_STEPPER_SHIFT 16 /**< Shift value for AGC_STEPPER */
+#define _AGC_RSSISTEPTHR_STEPPER_MASK 0x10000UL /**< Bit mask for AGC_STEPPER */
+#define _AGC_RSSISTEPTHR_STEPPER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_RSSISTEPTHR */
+#define AGC_RSSISTEPTHR_STEPPER_DEFAULT (_AGC_RSSISTEPTHR_STEPPER_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_RSSISTEPTHR */
+#define _AGC_RSSISTEPTHR_DEMODRESTARTPER_SHIFT 17 /**< Shift value for AGC_DEMODRESTARTPER */
+#define _AGC_RSSISTEPTHR_DEMODRESTARTPER_MASK 0x1E0000UL /**< Bit mask for AGC_DEMODRESTARTPER */
+#define _AGC_RSSISTEPTHR_DEMODRESTARTPER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_RSSISTEPTHR */
+#define AGC_RSSISTEPTHR_DEMODRESTARTPER_DEFAULT (_AGC_RSSISTEPTHR_DEMODRESTARTPER_DEFAULT << 17) /**< Shifted mode DEFAULT for AGC_RSSISTEPTHR */
+#define _AGC_RSSISTEPTHR_DEMODRESTARTTHR_SHIFT 21 /**< Shift value for AGC_DEMODRESTARTTHR */
+#define _AGC_RSSISTEPTHR_DEMODRESTARTTHR_MASK 0x1FE00000UL /**< Bit mask for AGC_DEMODRESTARTTHR */
+#define _AGC_RSSISTEPTHR_DEMODRESTARTTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_RSSISTEPTHR */
+#define AGC_RSSISTEPTHR_DEMODRESTARTTHR_DEFAULT (_AGC_RSSISTEPTHR_DEMODRESTARTTHR_DEFAULT << 21) /**< Shifted mode DEFAULT for AGC_RSSISTEPTHR */
+#define AGC_RSSISTEPTHR_RSSIFAST (0x1UL << 29) /**< RSSI fast startup */
+#define _AGC_RSSISTEPTHR_RSSIFAST_SHIFT 29 /**< Shift value for AGC_RSSIFAST */
+#define _AGC_RSSISTEPTHR_RSSIFAST_MASK 0x20000000UL /**< Bit mask for AGC_RSSIFAST */
+#define _AGC_RSSISTEPTHR_RSSIFAST_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_RSSISTEPTHR */
+#define AGC_RSSISTEPTHR_RSSIFAST_DEFAULT (_AGC_RSSISTEPTHR_RSSIFAST_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_RSSISTEPTHR */
+
+/* Bit fields for AGC IF */
+#define _AGC_IF_RESETVALUE 0x00000000UL /**< Default value for AGC_IF */
+#define _AGC_IF_MASK 0x00007F7DUL /**< Mask for AGC_IF */
+#define AGC_IF_RSSIVALID (0x1UL << 0) /**< RSSI Value is Valid */
+#define _AGC_IF_RSSIVALID_SHIFT 0 /**< Shift value for AGC_RSSIVALID */
+#define _AGC_IF_RSSIVALID_MASK 0x1UL /**< Bit mask for AGC_RSSIVALID */
+#define _AGC_IF_RSSIVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IF */
+#define AGC_IF_RSSIVALID_DEFAULT (_AGC_IF_RSSIVALID_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_IF */
+#define AGC_IF_CCA (0x1UL << 2) /**< Clear Channel Assessment */
+#define _AGC_IF_CCA_SHIFT 2 /**< Shift value for AGC_CCA */
+#define _AGC_IF_CCA_MASK 0x4UL /**< Bit mask for AGC_CCA */
+#define _AGC_IF_CCA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IF */
+#define AGC_IF_CCA_DEFAULT (_AGC_IF_CCA_DEFAULT << 2) /**< Shifted mode DEFAULT for AGC_IF */
+#define AGC_IF_RSSIPOSSTEP (0x1UL << 3) /**< Positive RSSI Step Detected */
+#define _AGC_IF_RSSIPOSSTEP_SHIFT 3 /**< Shift value for AGC_RSSIPOSSTEP */
+#define _AGC_IF_RSSIPOSSTEP_MASK 0x8UL /**< Bit mask for AGC_RSSIPOSSTEP */
+#define _AGC_IF_RSSIPOSSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IF */
+#define AGC_IF_RSSIPOSSTEP_DEFAULT (_AGC_IF_RSSIPOSSTEP_DEFAULT << 3) /**< Shifted mode DEFAULT for AGC_IF */
+#define AGC_IF_RSSINEGSTEP (0x1UL << 4) /**< Negative RSSI Step Detected */
+#define _AGC_IF_RSSINEGSTEP_SHIFT 4 /**< Shift value for AGC_RSSINEGSTEP */
+#define _AGC_IF_RSSINEGSTEP_MASK 0x10UL /**< Bit mask for AGC_RSSINEGSTEP */
+#define _AGC_IF_RSSINEGSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IF */
+#define AGC_IF_RSSINEGSTEP_DEFAULT (_AGC_IF_RSSINEGSTEP_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_IF */
+#define AGC_IF_SHORTRSSIPOSSTEP (0x1UL << 6) /**< Short-term Positive RSSI Step Detected */
+#define _AGC_IF_SHORTRSSIPOSSTEP_SHIFT 6 /**< Shift value for AGC_SHORTRSSIPOSSTEP */
+#define _AGC_IF_SHORTRSSIPOSSTEP_MASK 0x40UL /**< Bit mask for AGC_SHORTRSSIPOSSTEP */
+#define _AGC_IF_SHORTRSSIPOSSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IF */
+#define AGC_IF_SHORTRSSIPOSSTEP_DEFAULT (_AGC_IF_SHORTRSSIPOSSTEP_DEFAULT << 6) /**< Shifted mode DEFAULT for AGC_IF */
+#define AGC_IF_RFPKDPRDDONE (0x1UL << 8) /**< RF PKD PERIOD CNT TOMEOUT */
+#define _AGC_IF_RFPKDPRDDONE_SHIFT 8 /**< Shift value for AGC_RFPKDPRDDONE */
+#define _AGC_IF_RFPKDPRDDONE_MASK 0x100UL /**< Bit mask for AGC_RFPKDPRDDONE */
+#define _AGC_IF_RFPKDPRDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IF */
+#define AGC_IF_RFPKDPRDDONE_DEFAULT (_AGC_IF_RFPKDPRDDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_IF */
+#define AGC_IF_RFPKDCNTDONE (0x1UL << 9) /**< RF PKD pulse CNT TOMEOUT */
+#define _AGC_IF_RFPKDCNTDONE_SHIFT 9 /**< Shift value for AGC_RFPKDCNTDONE */
+#define _AGC_IF_RFPKDCNTDONE_MASK 0x200UL /**< Bit mask for AGC_RFPKDCNTDONE */
+#define _AGC_IF_RFPKDCNTDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IF */
+#define AGC_IF_RFPKDCNTDONE_DEFAULT (_AGC_IF_RFPKDCNTDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for AGC_IF */
+#define AGC_IF_RSSIHIGH (0x1UL << 10) /**< RSSI high detected */
+#define _AGC_IF_RSSIHIGH_SHIFT 10 /**< Shift value for AGC_RSSIHIGH */
+#define _AGC_IF_RSSIHIGH_MASK 0x400UL /**< Bit mask for AGC_RSSIHIGH */
+#define _AGC_IF_RSSIHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IF */
+#define AGC_IF_RSSIHIGH_DEFAULT (_AGC_IF_RSSIHIGH_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_IF */
+#define AGC_IF_RSSILOW (0x1UL << 11) /**< RSSI low detected */
+#define _AGC_IF_RSSILOW_SHIFT 11 /**< Shift value for AGC_RSSILOW */
+#define _AGC_IF_RSSILOW_MASK 0x800UL /**< Bit mask for AGC_RSSILOW */
+#define _AGC_IF_RSSILOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IF */
+#define AGC_IF_RSSILOW_DEFAULT (_AGC_IF_RSSILOW_DEFAULT << 11) /**< Shifted mode DEFAULT for AGC_IF */
+#define AGC_IF_CCANODET (0x1UL << 12) /**< CCA Not Detected */
+#define _AGC_IF_CCANODET_SHIFT 12 /**< Shift value for AGC_CCANODET */
+#define _AGC_IF_CCANODET_MASK 0x1000UL /**< Bit mask for AGC_CCANODET */
+#define _AGC_IF_CCANODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IF */
+#define AGC_IF_CCANODET_DEFAULT (_AGC_IF_CCANODET_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_IF */
+#define AGC_IF_GAINBELOWGAINTHD (0x1UL << 13) /**< agc gain above threshold int */
+#define _AGC_IF_GAINBELOWGAINTHD_SHIFT 13 /**< Shift value for AGC_GAINBELOWGAINTHD */
+#define _AGC_IF_GAINBELOWGAINTHD_MASK 0x2000UL /**< Bit mask for AGC_GAINBELOWGAINTHD */
+#define _AGC_IF_GAINBELOWGAINTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IF */
+#define AGC_IF_GAINBELOWGAINTHD_DEFAULT (_AGC_IF_GAINBELOWGAINTHD_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_IF */
+#define AGC_IF_GAINUPDATEFRZ (0x1UL << 14) /**< AGC gain update frozen int */
+#define _AGC_IF_GAINUPDATEFRZ_SHIFT 14 /**< Shift value for AGC_GAINUPDATEFRZ */
+#define _AGC_IF_GAINUPDATEFRZ_MASK 0x4000UL /**< Bit mask for AGC_GAINUPDATEFRZ */
+#define _AGC_IF_GAINUPDATEFRZ_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IF */
+#define AGC_IF_GAINUPDATEFRZ_DEFAULT (_AGC_IF_GAINUPDATEFRZ_DEFAULT << 14) /**< Shifted mode DEFAULT for AGC_IF */
+
+/* Bit fields for AGC IEN */
+#define _AGC_IEN_RESETVALUE 0x00000000UL /**< Default value for AGC_IEN */
+#define _AGC_IEN_MASK 0x00007F7DUL /**< Mask for AGC_IEN */
+#define AGC_IEN_RSSIVALID (0x1UL << 0) /**< RSSIVALID Interrupt Enable */
+#define _AGC_IEN_RSSIVALID_SHIFT 0 /**< Shift value for AGC_RSSIVALID */
+#define _AGC_IEN_RSSIVALID_MASK 0x1UL /**< Bit mask for AGC_RSSIVALID */
+#define _AGC_IEN_RSSIVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IEN */
+#define AGC_IEN_RSSIVALID_DEFAULT (_AGC_IEN_RSSIVALID_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_IEN */
+#define AGC_IEN_CCA (0x1UL << 2) /**< CCA Interrupt Enable */
+#define _AGC_IEN_CCA_SHIFT 2 /**< Shift value for AGC_CCA */
+#define _AGC_IEN_CCA_MASK 0x4UL /**< Bit mask for AGC_CCA */
+#define _AGC_IEN_CCA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IEN */
+#define AGC_IEN_CCA_DEFAULT (_AGC_IEN_CCA_DEFAULT << 2) /**< Shifted mode DEFAULT for AGC_IEN */
+#define AGC_IEN_RSSIPOSSTEP (0x1UL << 3) /**< RSSIPOSSTEP Interrupt Enable */
+#define _AGC_IEN_RSSIPOSSTEP_SHIFT 3 /**< Shift value for AGC_RSSIPOSSTEP */
+#define _AGC_IEN_RSSIPOSSTEP_MASK 0x8UL /**< Bit mask for AGC_RSSIPOSSTEP */
+#define _AGC_IEN_RSSIPOSSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IEN */
+#define AGC_IEN_RSSIPOSSTEP_DEFAULT (_AGC_IEN_RSSIPOSSTEP_DEFAULT << 3) /**< Shifted mode DEFAULT for AGC_IEN */
+#define AGC_IEN_RSSINEGSTEP (0x1UL << 4) /**< RSSINEGSTEP Interrupt Enable */
+#define _AGC_IEN_RSSINEGSTEP_SHIFT 4 /**< Shift value for AGC_RSSINEGSTEP */
+#define _AGC_IEN_RSSINEGSTEP_MASK 0x10UL /**< Bit mask for AGC_RSSINEGSTEP */
+#define _AGC_IEN_RSSINEGSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IEN */
+#define AGC_IEN_RSSINEGSTEP_DEFAULT (_AGC_IEN_RSSINEGSTEP_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_IEN */
+#define AGC_IEN_SHORTRSSIPOSSTEP (0x1UL << 6) /**< SHORTRSSIPOSSTEP Interrupt Enable */
+#define _AGC_IEN_SHORTRSSIPOSSTEP_SHIFT 6 /**< Shift value for AGC_SHORTRSSIPOSSTEP */
+#define _AGC_IEN_SHORTRSSIPOSSTEP_MASK 0x40UL /**< Bit mask for AGC_SHORTRSSIPOSSTEP */
+#define _AGC_IEN_SHORTRSSIPOSSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IEN */
+#define AGC_IEN_SHORTRSSIPOSSTEP_DEFAULT (_AGC_IEN_SHORTRSSIPOSSTEP_DEFAULT << 6) /**< Shifted mode DEFAULT for AGC_IEN */
+#define AGC_IEN_RFPKDPRDDONE (0x1UL << 8) /**< RF PKD PERIOD CNT Interrupt Enable */
+#define _AGC_IEN_RFPKDPRDDONE_SHIFT 8 /**< Shift value for AGC_RFPKDPRDDONE */
+#define _AGC_IEN_RFPKDPRDDONE_MASK 0x100UL /**< Bit mask for AGC_RFPKDPRDDONE */
+#define _AGC_IEN_RFPKDPRDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IEN */
+#define AGC_IEN_RFPKDPRDDONE_DEFAULT (_AGC_IEN_RFPKDPRDDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_IEN */
+#define AGC_IEN_RFPKDCNTDONE (0x1UL << 9) /**< RF PKD pulse CNT Interrupt Enable */
+#define _AGC_IEN_RFPKDCNTDONE_SHIFT 9 /**< Shift value for AGC_RFPKDCNTDONE */
+#define _AGC_IEN_RFPKDCNTDONE_MASK 0x200UL /**< Bit mask for AGC_RFPKDCNTDONE */
+#define _AGC_IEN_RFPKDCNTDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IEN */
+#define AGC_IEN_RFPKDCNTDONE_DEFAULT (_AGC_IEN_RFPKDCNTDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for AGC_IEN */
+#define AGC_IEN_RSSIHIGH (0x1UL << 10) /**< RSSIHIGH Interrupt Enable */
+#define _AGC_IEN_RSSIHIGH_SHIFT 10 /**< Shift value for AGC_RSSIHIGH */
+#define _AGC_IEN_RSSIHIGH_MASK 0x400UL /**< Bit mask for AGC_RSSIHIGH */
+#define _AGC_IEN_RSSIHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IEN */
+#define AGC_IEN_RSSIHIGH_DEFAULT (_AGC_IEN_RSSIHIGH_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_IEN */
+#define AGC_IEN_RSSILOW (0x1UL << 11) /**< RSSILOW Interrupt Enable */
+#define _AGC_IEN_RSSILOW_SHIFT 11 /**< Shift value for AGC_RSSILOW */
+#define _AGC_IEN_RSSILOW_MASK 0x800UL /**< Bit mask for AGC_RSSILOW */
+#define _AGC_IEN_RSSILOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IEN */
+#define AGC_IEN_RSSILOW_DEFAULT (_AGC_IEN_RSSILOW_DEFAULT << 11) /**< Shifted mode DEFAULT for AGC_IEN */
+#define AGC_IEN_CCANODET (0x1UL << 12) /**< CCANODET Interrupt Enable */
+#define _AGC_IEN_CCANODET_SHIFT 12 /**< Shift value for AGC_CCANODET */
+#define _AGC_IEN_CCANODET_MASK 0x1000UL /**< Bit mask for AGC_CCANODET */
+#define _AGC_IEN_CCANODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IEN */
+#define AGC_IEN_CCANODET_DEFAULT (_AGC_IEN_CCANODET_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_IEN */
+#define AGC_IEN_GAINBELOWGAINTHD (0x1UL << 13) /**< GAINBELOWGAINTHD Interrupt Enable */
+#define _AGC_IEN_GAINBELOWGAINTHD_SHIFT 13 /**< Shift value for AGC_GAINBELOWGAINTHD */
+#define _AGC_IEN_GAINBELOWGAINTHD_MASK 0x2000UL /**< Bit mask for AGC_GAINBELOWGAINTHD */
+#define _AGC_IEN_GAINBELOWGAINTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IEN */
+#define AGC_IEN_GAINBELOWGAINTHD_DEFAULT (_AGC_IEN_GAINBELOWGAINTHD_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_IEN */
+#define AGC_IEN_GAINUPDATEFRZ (0x1UL << 14) /**< AGC gain update frozen int Enable */
+#define _AGC_IEN_GAINUPDATEFRZ_SHIFT 14 /**< Shift value for AGC_GAINUPDATEFRZ */
+#define _AGC_IEN_GAINUPDATEFRZ_MASK 0x4000UL /**< Bit mask for AGC_GAINUPDATEFRZ */
+#define _AGC_IEN_GAINUPDATEFRZ_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_IEN */
+#define AGC_IEN_GAINUPDATEFRZ_DEFAULT (_AGC_IEN_GAINUPDATEFRZ_DEFAULT << 14) /**< Shifted mode DEFAULT for AGC_IEN */
+
+/* Bit fields for AGC GAINRANGE */
+#define _AGC_GAINRANGE_RESETVALUE 0x00813187UL /**< Default value for AGC_GAINRANGE */
+#define _AGC_GAINRANGE_MASK 0x03FFFFFFUL /**< Mask for AGC_GAINRANGE */
+#define _AGC_GAINRANGE_LNAINDEXBORDER_SHIFT 0 /**< Shift value for AGC_LNAINDEXBORDER */
+#define _AGC_GAINRANGE_LNAINDEXBORDER_MASK 0xFUL /**< Bit mask for AGC_LNAINDEXBORDER */
+#define _AGC_GAINRANGE_LNAINDEXBORDER_DEFAULT 0x00000007UL /**< Mode DEFAULT for AGC_GAINRANGE */
+#define AGC_GAINRANGE_LNAINDEXBORDER_DEFAULT (_AGC_GAINRANGE_LNAINDEXBORDER_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_GAINRANGE */
+#define _AGC_GAINRANGE_PGAINDEXBORDER_SHIFT 4 /**< Shift value for AGC_PGAINDEXBORDER */
+#define _AGC_GAINRANGE_PGAINDEXBORDER_MASK 0xF0UL /**< Bit mask for AGC_PGAINDEXBORDER */
+#define _AGC_GAINRANGE_PGAINDEXBORDER_DEFAULT 0x00000008UL /**< Mode DEFAULT for AGC_GAINRANGE */
+#define AGC_GAINRANGE_PGAINDEXBORDER_DEFAULT (_AGC_GAINRANGE_PGAINDEXBORDER_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_GAINRANGE */
+#define _AGC_GAINRANGE_GAININCSTEP_SHIFT 8 /**< Shift value for AGC_GAININCSTEP */
+#define _AGC_GAINRANGE_GAININCSTEP_MASK 0xF00UL /**< Bit mask for AGC_GAININCSTEP */
+#define _AGC_GAINRANGE_GAININCSTEP_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_GAINRANGE */
+#define AGC_GAINRANGE_GAININCSTEP_DEFAULT (_AGC_GAINRANGE_GAININCSTEP_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_GAINRANGE */
+#define _AGC_GAINRANGE_PNGAINSTEP_SHIFT 12 /**< Shift value for AGC_PNGAINSTEP */
+#define _AGC_GAINRANGE_PNGAINSTEP_MASK 0xF000UL /**< Bit mask for AGC_PNGAINSTEP */
+#define _AGC_GAINRANGE_PNGAINSTEP_DEFAULT 0x00000003UL /**< Mode DEFAULT for AGC_GAINRANGE */
+#define AGC_GAINRANGE_PNGAINSTEP_DEFAULT (_AGC_GAINRANGE_PNGAINSTEP_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_GAINRANGE */
+#define _AGC_GAINRANGE_LATCHEDHISTEP_SHIFT 16 /**< Shift value for AGC_LATCHEDHISTEP */
+#define _AGC_GAINRANGE_LATCHEDHISTEP_MASK 0xF0000UL /**< Bit mask for AGC_LATCHEDHISTEP */
+#define _AGC_GAINRANGE_LATCHEDHISTEP_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_GAINRANGE */
+#define AGC_GAINRANGE_LATCHEDHISTEP_DEFAULT (_AGC_GAINRANGE_LATCHEDHISTEP_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_GAINRANGE */
+#define _AGC_GAINRANGE_HIPWRTHD_SHIFT 20 /**< Shift value for AGC_HIPWRTHD */
+#define _AGC_GAINRANGE_HIPWRTHD_MASK 0x3F00000UL /**< Bit mask for AGC_HIPWRTHD */
+#define _AGC_GAINRANGE_HIPWRTHD_DEFAULT 0x00000008UL /**< Mode DEFAULT for AGC_GAINRANGE */
+#define AGC_GAINRANGE_HIPWRTHD_DEFAULT (_AGC_GAINRANGE_HIPWRTHD_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_GAINRANGE */
+
+/* Bit fields for AGC AGCPERIOD0 */
+#define _AGC_AGCPERIOD0_RESETVALUE 0xD607000EUL /**< Default value for AGC_AGCPERIOD0 */
+#define _AGC_AGCPERIOD0_MASK 0xFFFF01FFUL /**< Mask for AGC_AGCPERIOD0 */
+#define _AGC_AGCPERIOD0_PERIODHI_SHIFT 0 /**< Shift value for AGC_PERIODHI */
+#define _AGC_AGCPERIOD0_PERIODHI_MASK 0x1FFUL /**< Bit mask for AGC_PERIODHI */
+#define _AGC_AGCPERIOD0_PERIODHI_DEFAULT 0x0000000EUL /**< Mode DEFAULT for AGC_AGCPERIOD0 */
+#define AGC_AGCPERIOD0_PERIODHI_DEFAULT (_AGC_AGCPERIOD0_PERIODHI_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_AGCPERIOD0 */
+#define _AGC_AGCPERIOD0_MAXHICNTTHD_SHIFT 16 /**< Shift value for AGC_MAXHICNTTHD */
+#define _AGC_AGCPERIOD0_MAXHICNTTHD_MASK 0xFF0000UL /**< Bit mask for AGC_MAXHICNTTHD */
+#define _AGC_AGCPERIOD0_MAXHICNTTHD_DEFAULT 0x00000007UL /**< Mode DEFAULT for AGC_AGCPERIOD0 */
+#define AGC_AGCPERIOD0_MAXHICNTTHD_DEFAULT (_AGC_AGCPERIOD0_MAXHICNTTHD_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_AGCPERIOD0 */
+#define _AGC_AGCPERIOD0_SETTLETIMEIF_SHIFT 24 /**< Shift value for AGC_SETTLETIMEIF */
+#define _AGC_AGCPERIOD0_SETTLETIMEIF_MASK 0xF000000UL /**< Bit mask for AGC_SETTLETIMEIF */
+#define _AGC_AGCPERIOD0_SETTLETIMEIF_DEFAULT 0x00000006UL /**< Mode DEFAULT for AGC_AGCPERIOD0 */
+#define AGC_AGCPERIOD0_SETTLETIMEIF_DEFAULT (_AGC_AGCPERIOD0_SETTLETIMEIF_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_AGCPERIOD0 */
+#define _AGC_AGCPERIOD0_SETTLETIMERF_SHIFT 28 /**< Shift value for AGC_SETTLETIMERF */
+#define _AGC_AGCPERIOD0_SETTLETIMERF_MASK 0xF0000000UL /**< Bit mask for AGC_SETTLETIMERF */
+#define _AGC_AGCPERIOD0_SETTLETIMERF_DEFAULT 0x0000000DUL /**< Mode DEFAULT for AGC_AGCPERIOD0 */
+#define AGC_AGCPERIOD0_SETTLETIMERF_DEFAULT (_AGC_AGCPERIOD0_SETTLETIMERF_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_AGCPERIOD0 */
+
+/* Bit fields for AGC AGCPERIOD1 */
+#define _AGC_AGCPERIOD1_RESETVALUE 0x00000037UL /**< Default value for AGC_AGCPERIOD1 */
+#define _AGC_AGCPERIOD1_MASK 0xFFFFFFFFUL /**< Mask for AGC_AGCPERIOD1 */
+#define _AGC_AGCPERIOD1_PERIODLOW_SHIFT 0 /**< Shift value for AGC_PERIODLOW */
+#define _AGC_AGCPERIOD1_PERIODLOW_MASK 0xFFFFFFFFUL /**< Bit mask for AGC_PERIODLOW */
+#define _AGC_AGCPERIOD1_PERIODLOW_DEFAULT 0x00000037UL /**< Mode DEFAULT for AGC_AGCPERIOD1 */
+#define AGC_AGCPERIOD1_PERIODLOW_DEFAULT (_AGC_AGCPERIOD1_PERIODLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_AGCPERIOD1 */
+
+/* Bit fields for AGC HICNTREGION0 */
+#define _AGC_HICNTREGION0_RESETVALUE 0x06050403UL /**< Default value for AGC_HICNTREGION0 */
+#define _AGC_HICNTREGION0_MASK 0xFFFFFFFFUL /**< Mask for AGC_HICNTREGION0 */
+#define _AGC_HICNTREGION0_HICNTREGION0_SHIFT 0 /**< Shift value for AGC_HICNTREGION0 */
+#define _AGC_HICNTREGION0_HICNTREGION0_MASK 0xFFUL /**< Bit mask for AGC_HICNTREGION0 */
+#define _AGC_HICNTREGION0_HICNTREGION0_DEFAULT 0x00000003UL /**< Mode DEFAULT for AGC_HICNTREGION0 */
+#define AGC_HICNTREGION0_HICNTREGION0_DEFAULT (_AGC_HICNTREGION0_HICNTREGION0_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_HICNTREGION0 */
+#define _AGC_HICNTREGION0_HICNTREGION1_SHIFT 8 /**< Shift value for AGC_HICNTREGION1 */
+#define _AGC_HICNTREGION0_HICNTREGION1_MASK 0xFF00UL /**< Bit mask for AGC_HICNTREGION1 */
+#define _AGC_HICNTREGION0_HICNTREGION1_DEFAULT 0x00000004UL /**< Mode DEFAULT for AGC_HICNTREGION0 */
+#define AGC_HICNTREGION0_HICNTREGION1_DEFAULT (_AGC_HICNTREGION0_HICNTREGION1_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_HICNTREGION0 */
+#define _AGC_HICNTREGION0_HICNTREGION2_SHIFT 16 /**< Shift value for AGC_HICNTREGION2 */
+#define _AGC_HICNTREGION0_HICNTREGION2_MASK 0xFF0000UL /**< Bit mask for AGC_HICNTREGION2 */
+#define _AGC_HICNTREGION0_HICNTREGION2_DEFAULT 0x00000005UL /**< Mode DEFAULT for AGC_HICNTREGION0 */
+#define AGC_HICNTREGION0_HICNTREGION2_DEFAULT (_AGC_HICNTREGION0_HICNTREGION2_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_HICNTREGION0 */
+#define _AGC_HICNTREGION0_HICNTREGION3_SHIFT 24 /**< Shift value for AGC_HICNTREGION3 */
+#define _AGC_HICNTREGION0_HICNTREGION3_MASK 0xFF000000UL /**< Bit mask for AGC_HICNTREGION3 */
+#define _AGC_HICNTREGION0_HICNTREGION3_DEFAULT 0x00000006UL /**< Mode DEFAULT for AGC_HICNTREGION0 */
+#define AGC_HICNTREGION0_HICNTREGION3_DEFAULT (_AGC_HICNTREGION0_HICNTREGION3_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_HICNTREGION0 */
+
+/* Bit fields for AGC HICNTREGION1 */
+#define _AGC_HICNTREGION1_RESETVALUE 0x00000008UL /**< Default value for AGC_HICNTREGION1 */
+#define _AGC_HICNTREGION1_MASK 0x000000FFUL /**< Mask for AGC_HICNTREGION1 */
+#define _AGC_HICNTREGION1_HICNTREGION4_SHIFT 0 /**< Shift value for AGC_HICNTREGION4 */
+#define _AGC_HICNTREGION1_HICNTREGION4_MASK 0xFFUL /**< Bit mask for AGC_HICNTREGION4 */
+#define _AGC_HICNTREGION1_HICNTREGION4_DEFAULT 0x00000008UL /**< Mode DEFAULT for AGC_HICNTREGION1 */
+#define AGC_HICNTREGION1_HICNTREGION4_DEFAULT (_AGC_HICNTREGION1_HICNTREGION4_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_HICNTREGION1 */
+
+/* Bit fields for AGC STEPDWN */
+#define _AGC_STEPDWN_RESETVALUE 0x00036D11UL /**< Default value for AGC_STEPDWN */
+#define _AGC_STEPDWN_MASK 0x0003FFFFUL /**< Mask for AGC_STEPDWN */
+#define _AGC_STEPDWN_STEPDWN0_SHIFT 0 /**< Shift value for AGC_STEPDWN0 */
+#define _AGC_STEPDWN_STEPDWN0_MASK 0x7UL /**< Bit mask for AGC_STEPDWN0 */
+#define _AGC_STEPDWN_STEPDWN0_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_STEPDWN */
+#define AGC_STEPDWN_STEPDWN0_DEFAULT (_AGC_STEPDWN_STEPDWN0_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_STEPDWN */
+#define _AGC_STEPDWN_STEPDWN1_SHIFT 3 /**< Shift value for AGC_STEPDWN1 */
+#define _AGC_STEPDWN_STEPDWN1_MASK 0x38UL /**< Bit mask for AGC_STEPDWN1 */
+#define _AGC_STEPDWN_STEPDWN1_DEFAULT 0x00000002UL /**< Mode DEFAULT for AGC_STEPDWN */
+#define AGC_STEPDWN_STEPDWN1_DEFAULT (_AGC_STEPDWN_STEPDWN1_DEFAULT << 3) /**< Shifted mode DEFAULT for AGC_STEPDWN */
+#define _AGC_STEPDWN_STEPDWN2_SHIFT 6 /**< Shift value for AGC_STEPDWN2 */
+#define _AGC_STEPDWN_STEPDWN2_MASK 0x1C0UL /**< Bit mask for AGC_STEPDWN2 */
+#define _AGC_STEPDWN_STEPDWN2_DEFAULT 0x00000004UL /**< Mode DEFAULT for AGC_STEPDWN */
+#define AGC_STEPDWN_STEPDWN2_DEFAULT (_AGC_STEPDWN_STEPDWN2_DEFAULT << 6) /**< Shifted mode DEFAULT for AGC_STEPDWN */
+#define _AGC_STEPDWN_STEPDWN3_SHIFT 9 /**< Shift value for AGC_STEPDWN3 */
+#define _AGC_STEPDWN_STEPDWN3_MASK 0xE00UL /**< Bit mask for AGC_STEPDWN3 */
+#define _AGC_STEPDWN_STEPDWN3_DEFAULT 0x00000006UL /**< Mode DEFAULT for AGC_STEPDWN */
+#define AGC_STEPDWN_STEPDWN3_DEFAULT (_AGC_STEPDWN_STEPDWN3_DEFAULT << 9) /**< Shifted mode DEFAULT for AGC_STEPDWN */
+#define _AGC_STEPDWN_STEPDWN4_SHIFT 12 /**< Shift value for AGC_STEPDWN4 */
+#define _AGC_STEPDWN_STEPDWN4_MASK 0x7000UL /**< Bit mask for AGC_STEPDWN4 */
+#define _AGC_STEPDWN_STEPDWN4_DEFAULT 0x00000006UL /**< Mode DEFAULT for AGC_STEPDWN */
+#define AGC_STEPDWN_STEPDWN4_DEFAULT (_AGC_STEPDWN_STEPDWN4_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_STEPDWN */
+#define _AGC_STEPDWN_STEPDWN5_SHIFT 15 /**< Shift value for AGC_STEPDWN5 */
+#define _AGC_STEPDWN_STEPDWN5_MASK 0x38000UL /**< Bit mask for AGC_STEPDWN5 */
+#define _AGC_STEPDWN_STEPDWN5_DEFAULT 0x00000006UL /**< Mode DEFAULT for AGC_STEPDWN */
+#define AGC_STEPDWN_STEPDWN5_DEFAULT (_AGC_STEPDWN_STEPDWN5_DEFAULT << 15) /**< Shifted mode DEFAULT for AGC_STEPDWN */
+
+/* Bit fields for AGC GAINSTEPLIM0 */
+#define _AGC_GAINSTEPLIM0_RESETVALUE 0x00003144UL /**< Default value for AGC_GAINSTEPLIM0 */
+#define _AGC_GAINSTEPLIM0_MASK 0x01FFFFFFUL /**< Mask for AGC_GAINSTEPLIM0 */
+#define _AGC_GAINSTEPLIM0_CFLOOPSTEPMAX_SHIFT 0 /**< Shift value for AGC_CFLOOPSTEPMAX */
+#define _AGC_GAINSTEPLIM0_CFLOOPSTEPMAX_MASK 0x1FUL /**< Bit mask for AGC_CFLOOPSTEPMAX */
+#define _AGC_GAINSTEPLIM0_CFLOOPSTEPMAX_DEFAULT 0x00000004UL /**< Mode DEFAULT for AGC_GAINSTEPLIM0 */
+#define AGC_GAINSTEPLIM0_CFLOOPSTEPMAX_DEFAULT (_AGC_GAINSTEPLIM0_CFLOOPSTEPMAX_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_GAINSTEPLIM0 */
+#define _AGC_GAINSTEPLIM0_CFLOOPDEL_SHIFT 5 /**< Shift value for AGC_CFLOOPDEL */
+#define _AGC_GAINSTEPLIM0_CFLOOPDEL_MASK 0xFE0UL /**< Bit mask for AGC_CFLOOPDEL */
+#define _AGC_GAINSTEPLIM0_CFLOOPDEL_DEFAULT 0x0000000AUL /**< Mode DEFAULT for AGC_GAINSTEPLIM0 */
+#define AGC_GAINSTEPLIM0_CFLOOPDEL_DEFAULT (_AGC_GAINSTEPLIM0_CFLOOPDEL_DEFAULT << 5) /**< Shifted mode DEFAULT for AGC_GAINSTEPLIM0 */
+#define _AGC_GAINSTEPLIM0_HYST_SHIFT 12 /**< Shift value for AGC_HYST */
+#define _AGC_GAINSTEPLIM0_HYST_MASK 0xF000UL /**< Bit mask for AGC_HYST */
+#define _AGC_GAINSTEPLIM0_HYST_DEFAULT 0x00000003UL /**< Mode DEFAULT for AGC_GAINSTEPLIM0 */
+#define AGC_GAINSTEPLIM0_HYST_DEFAULT (_AGC_GAINSTEPLIM0_HYST_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_GAINSTEPLIM0 */
+#define _AGC_GAINSTEPLIM0_MAXPWRVAR_SHIFT 16 /**< Shift value for AGC_MAXPWRVAR */
+#define _AGC_GAINSTEPLIM0_MAXPWRVAR_MASK 0xFF0000UL /**< Bit mask for AGC_MAXPWRVAR */
+#define _AGC_GAINSTEPLIM0_MAXPWRVAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_GAINSTEPLIM0 */
+#define AGC_GAINSTEPLIM0_MAXPWRVAR_DEFAULT (_AGC_GAINSTEPLIM0_MAXPWRVAR_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_GAINSTEPLIM0 */
+#define AGC_GAINSTEPLIM0_TRANRSTAGC (0x1UL << 24) /**< power transient detector Reset AGC */
+#define _AGC_GAINSTEPLIM0_TRANRSTAGC_SHIFT 24 /**< Shift value for AGC_TRANRSTAGC */
+#define _AGC_GAINSTEPLIM0_TRANRSTAGC_MASK 0x1000000UL /**< Bit mask for AGC_TRANRSTAGC */
+#define _AGC_GAINSTEPLIM0_TRANRSTAGC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_GAINSTEPLIM0 */
+#define AGC_GAINSTEPLIM0_TRANRSTAGC_DEFAULT (_AGC_GAINSTEPLIM0_TRANRSTAGC_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_GAINSTEPLIM0 */
+
+/* Bit fields for AGC GAINSTEPLIM1 */
+#define _AGC_GAINSTEPLIM1_RESETVALUE 0x000011BAUL /**< Default value for AGC_GAINSTEPLIM1 */
+#define _AGC_GAINSTEPLIM1_MASK 0x00001FFFUL /**< Mask for AGC_GAINSTEPLIM1 */
+#define _AGC_GAINSTEPLIM1_LNAINDEXMAX_SHIFT 0 /**< Shift value for AGC_LNAINDEXMAX */
+#define _AGC_GAINSTEPLIM1_LNAINDEXMAX_MASK 0xFUL /**< Bit mask for AGC_LNAINDEXMAX */
+#define _AGC_GAINSTEPLIM1_LNAINDEXMAX_DEFAULT 0x0000000AUL /**< Mode DEFAULT for AGC_GAINSTEPLIM1 */
+#define AGC_GAINSTEPLIM1_LNAINDEXMAX_DEFAULT (_AGC_GAINSTEPLIM1_LNAINDEXMAX_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_GAINSTEPLIM1 */
+#define _AGC_GAINSTEPLIM1_PGAINDEXMAX_SHIFT 4 /**< Shift value for AGC_PGAINDEXMAX */
+#define _AGC_GAINSTEPLIM1_PGAINDEXMAX_MASK 0xF0UL /**< Bit mask for AGC_PGAINDEXMAX */
+#define _AGC_GAINSTEPLIM1_PGAINDEXMAX_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_GAINSTEPLIM1 */
+#define AGC_GAINSTEPLIM1_PGAINDEXMAX_DEFAULT (_AGC_GAINSTEPLIM1_PGAINDEXMAX_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_GAINSTEPLIM1 */
+#define _AGC_GAINSTEPLIM1_PNINDEXMAX_SHIFT 8 /**< Shift value for AGC_PNINDEXMAX */
+#define _AGC_GAINSTEPLIM1_PNINDEXMAX_MASK 0x1F00UL /**< Bit mask for AGC_PNINDEXMAX */
+#define _AGC_GAINSTEPLIM1_PNINDEXMAX_DEFAULT 0x00000011UL /**< Mode DEFAULT for AGC_GAINSTEPLIM1 */
+#define AGC_GAINSTEPLIM1_PNINDEXMAX_DEFAULT (_AGC_GAINSTEPLIM1_PNINDEXMAX_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_GAINSTEPLIM1 */
+
+/* Bit fields for AGC PNRFATT0 */
+#define _AGC_PNRFATT0_RESETVALUE 0x00200400UL /**< Default value for AGC_PNRFATT0 */
+#define _AGC_PNRFATT0_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFATT0 */
+#define _AGC_PNRFATT0_LNAMIXRFATT1_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT1 */
+#define _AGC_PNRFATT0_LNAMIXRFATT1_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT1 */
+#define _AGC_PNRFATT0_LNAMIXRFATT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_PNRFATT0 */
+#define AGC_PNRFATT0_LNAMIXRFATT1_DEFAULT (_AGC_PNRFATT0_LNAMIXRFATT1_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFATT0 */
+#define _AGC_PNRFATT0_LNAMIXRFATT2_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT2 */
+#define _AGC_PNRFATT0_LNAMIXRFATT2_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT2 */
+#define _AGC_PNRFATT0_LNAMIXRFATT2_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_PNRFATT0 */
+#define AGC_PNRFATT0_LNAMIXRFATT2_DEFAULT (_AGC_PNRFATT0_LNAMIXRFATT2_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFATT0 */
+#define _AGC_PNRFATT0_LNAMIXRFATT3_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT3 */
+#define _AGC_PNRFATT0_LNAMIXRFATT3_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT3 */
+#define _AGC_PNRFATT0_LNAMIXRFATT3_DEFAULT 0x00000002UL /**< Mode DEFAULT for AGC_PNRFATT0 */
+#define AGC_PNRFATT0_LNAMIXRFATT3_DEFAULT (_AGC_PNRFATT0_LNAMIXRFATT3_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFATT0 */
+
+/* Bit fields for AGC PNRFATT1 */
+#define _AGC_PNRFATT1_RESETVALUE 0x00801804UL /**< Default value for AGC_PNRFATT1 */
+#define _AGC_PNRFATT1_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFATT1 */
+#define _AGC_PNRFATT1_LNAMIXRFATT4_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT4 */
+#define _AGC_PNRFATT1_LNAMIXRFATT4_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT4 */
+#define _AGC_PNRFATT1_LNAMIXRFATT4_DEFAULT 0x00000004UL /**< Mode DEFAULT for AGC_PNRFATT1 */
+#define AGC_PNRFATT1_LNAMIXRFATT4_DEFAULT (_AGC_PNRFATT1_LNAMIXRFATT4_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFATT1 */
+#define _AGC_PNRFATT1_LNAMIXRFATT5_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT5 */
+#define _AGC_PNRFATT1_LNAMIXRFATT5_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT5 */
+#define _AGC_PNRFATT1_LNAMIXRFATT5_DEFAULT 0x00000006UL /**< Mode DEFAULT for AGC_PNRFATT1 */
+#define AGC_PNRFATT1_LNAMIXRFATT5_DEFAULT (_AGC_PNRFATT1_LNAMIXRFATT5_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFATT1 */
+#define _AGC_PNRFATT1_LNAMIXRFATT6_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT6 */
+#define _AGC_PNRFATT1_LNAMIXRFATT6_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT6 */
+#define _AGC_PNRFATT1_LNAMIXRFATT6_DEFAULT 0x00000008UL /**< Mode DEFAULT for AGC_PNRFATT1 */
+#define AGC_PNRFATT1_LNAMIXRFATT6_DEFAULT (_AGC_PNRFATT1_LNAMIXRFATT6_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFATT1 */
+
+/* Bit fields for AGC PNRFATT2 */
+#define _AGC_PNRFATT2_RESETVALUE 0x01203C0BUL /**< Default value for AGC_PNRFATT2 */
+#define _AGC_PNRFATT2_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFATT2 */
+#define _AGC_PNRFATT2_LNAMIXRFATT7_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT7 */
+#define _AGC_PNRFATT2_LNAMIXRFATT7_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT7 */
+#define _AGC_PNRFATT2_LNAMIXRFATT7_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_PNRFATT2 */
+#define AGC_PNRFATT2_LNAMIXRFATT7_DEFAULT (_AGC_PNRFATT2_LNAMIXRFATT7_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFATT2 */
+#define _AGC_PNRFATT2_LNAMIXRFATT8_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT8 */
+#define _AGC_PNRFATT2_LNAMIXRFATT8_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT8 */
+#define _AGC_PNRFATT2_LNAMIXRFATT8_DEFAULT 0x0000000FUL /**< Mode DEFAULT for AGC_PNRFATT2 */
+#define AGC_PNRFATT2_LNAMIXRFATT8_DEFAULT (_AGC_PNRFATT2_LNAMIXRFATT8_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFATT2 */
+#define _AGC_PNRFATT2_LNAMIXRFATT9_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT9 */
+#define _AGC_PNRFATT2_LNAMIXRFATT9_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT9 */
+#define _AGC_PNRFATT2_LNAMIXRFATT9_DEFAULT 0x00000012UL /**< Mode DEFAULT for AGC_PNRFATT2 */
+#define AGC_PNRFATT2_LNAMIXRFATT9_DEFAULT (_AGC_PNRFATT2_LNAMIXRFATT9_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFATT2 */
+
+/* Bit fields for AGC PNRFATT3 */
+#define _AGC_PNRFATT3_RESETVALUE 0x02107C18UL /**< Default value for AGC_PNRFATT3 */
+#define _AGC_PNRFATT3_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFATT3 */
+#define _AGC_PNRFATT3_LNAMIXRFATT10_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT10 */
+#define _AGC_PNRFATT3_LNAMIXRFATT10_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT10 */
+#define _AGC_PNRFATT3_LNAMIXRFATT10_DEFAULT 0x00000018UL /**< Mode DEFAULT for AGC_PNRFATT3 */
+#define AGC_PNRFATT3_LNAMIXRFATT10_DEFAULT (_AGC_PNRFATT3_LNAMIXRFATT10_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFATT3 */
+#define _AGC_PNRFATT3_LNAMIXRFATT11_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT11 */
+#define _AGC_PNRFATT3_LNAMIXRFATT11_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT11 */
+#define _AGC_PNRFATT3_LNAMIXRFATT11_DEFAULT 0x0000001FUL /**< Mode DEFAULT for AGC_PNRFATT3 */
+#define AGC_PNRFATT3_LNAMIXRFATT11_DEFAULT (_AGC_PNRFATT3_LNAMIXRFATT11_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFATT3 */
+#define _AGC_PNRFATT3_LNAMIXRFATT12_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT12 */
+#define _AGC_PNRFATT3_LNAMIXRFATT12_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT12 */
+#define _AGC_PNRFATT3_LNAMIXRFATT12_DEFAULT 0x00000021UL /**< Mode DEFAULT for AGC_PNRFATT3 */
+#define AGC_PNRFATT3_LNAMIXRFATT12_DEFAULT (_AGC_PNRFATT3_LNAMIXRFATT12_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFATT3 */
+
+/* Bit fields for AGC PNRFATT4 */
+#define _AGC_PNRFATT4_RESETVALUE 0x06E0FC2FUL /**< Default value for AGC_PNRFATT4 */
+#define _AGC_PNRFATT4_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFATT4 */
+#define _AGC_PNRFATT4_LNAMIXRFATT13_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT13 */
+#define _AGC_PNRFATT4_LNAMIXRFATT13_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT13 */
+#define _AGC_PNRFATT4_LNAMIXRFATT13_DEFAULT 0x0000002FUL /**< Mode DEFAULT for AGC_PNRFATT4 */
+#define AGC_PNRFATT4_LNAMIXRFATT13_DEFAULT (_AGC_PNRFATT4_LNAMIXRFATT13_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFATT4 */
+#define _AGC_PNRFATT4_LNAMIXRFATT14_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT14 */
+#define _AGC_PNRFATT4_LNAMIXRFATT14_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT14 */
+#define _AGC_PNRFATT4_LNAMIXRFATT14_DEFAULT 0x0000003FUL /**< Mode DEFAULT for AGC_PNRFATT4 */
+#define AGC_PNRFATT4_LNAMIXRFATT14_DEFAULT (_AGC_PNRFATT4_LNAMIXRFATT14_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFATT4 */
+#define _AGC_PNRFATT4_LNAMIXRFATT15_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT15 */
+#define _AGC_PNRFATT4_LNAMIXRFATT15_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT15 */
+#define _AGC_PNRFATT4_LNAMIXRFATT15_DEFAULT 0x0000006EUL /**< Mode DEFAULT for AGC_PNRFATT4 */
+#define AGC_PNRFATT4_LNAMIXRFATT15_DEFAULT (_AGC_PNRFATT4_LNAMIXRFATT15_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFATT4 */
+
+/* Bit fields for AGC PNRFATT5 */
+#define _AGC_PNRFATT5_RESETVALUE 0x0180480FUL /**< Default value for AGC_PNRFATT5 */
+#define _AGC_PNRFATT5_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFATT5 */
+#define _AGC_PNRFATT5_LNAMIXRFATT16_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT16 */
+#define _AGC_PNRFATT5_LNAMIXRFATT16_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT16 */
+#define _AGC_PNRFATT5_LNAMIXRFATT16_DEFAULT 0x0000000FUL /**< Mode DEFAULT for AGC_PNRFATT5 */
+#define AGC_PNRFATT5_LNAMIXRFATT16_DEFAULT (_AGC_PNRFATT5_LNAMIXRFATT16_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFATT5 */
+#define _AGC_PNRFATT5_LNAMIXRFATT17_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT17 */
+#define _AGC_PNRFATT5_LNAMIXRFATT17_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT17 */
+#define _AGC_PNRFATT5_LNAMIXRFATT17_DEFAULT 0x00000012UL /**< Mode DEFAULT for AGC_PNRFATT5 */
+#define AGC_PNRFATT5_LNAMIXRFATT17_DEFAULT (_AGC_PNRFATT5_LNAMIXRFATT17_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFATT5 */
+#define _AGC_PNRFATT5_LNAMIXRFATT18_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT18 */
+#define _AGC_PNRFATT5_LNAMIXRFATT18_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT18 */
+#define _AGC_PNRFATT5_LNAMIXRFATT18_DEFAULT 0x00000018UL /**< Mode DEFAULT for AGC_PNRFATT5 */
+#define AGC_PNRFATT5_LNAMIXRFATT18_DEFAULT (_AGC_PNRFATT5_LNAMIXRFATT18_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFATT5 */
+
+/* Bit fields for AGC PNRFATT6 */
+#define _AGC_PNRFATT6_RESETVALUE 0x02F0841FUL /**< Default value for AGC_PNRFATT6 */
+#define _AGC_PNRFATT6_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFATT6 */
+#define _AGC_PNRFATT6_LNAMIXRFATT19_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT19 */
+#define _AGC_PNRFATT6_LNAMIXRFATT19_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT19 */
+#define _AGC_PNRFATT6_LNAMIXRFATT19_DEFAULT 0x0000001FUL /**< Mode DEFAULT for AGC_PNRFATT6 */
+#define AGC_PNRFATT6_LNAMIXRFATT19_DEFAULT (_AGC_PNRFATT6_LNAMIXRFATT19_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFATT6 */
+#define _AGC_PNRFATT6_LNAMIXRFATT20_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT20 */
+#define _AGC_PNRFATT6_LNAMIXRFATT20_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT20 */
+#define _AGC_PNRFATT6_LNAMIXRFATT20_DEFAULT 0x00000021UL /**< Mode DEFAULT for AGC_PNRFATT6 */
+#define AGC_PNRFATT6_LNAMIXRFATT20_DEFAULT (_AGC_PNRFATT6_LNAMIXRFATT20_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFATT6 */
+#define _AGC_PNRFATT6_LNAMIXRFATT21_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT21 */
+#define _AGC_PNRFATT6_LNAMIXRFATT21_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT21 */
+#define _AGC_PNRFATT6_LNAMIXRFATT21_DEFAULT 0x0000002FUL /**< Mode DEFAULT for AGC_PNRFATT6 */
+#define AGC_PNRFATT6_LNAMIXRFATT21_DEFAULT (_AGC_PNRFATT6_LNAMIXRFATT21_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFATT6 */
+
+/* Bit fields for AGC PNRFATT7 */
+#define _AGC_PNRFATT7_RESETVALUE 0x07F1B83FUL /**< Default value for AGC_PNRFATT7 */
+#define _AGC_PNRFATT7_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFATT7 */
+#define _AGC_PNRFATT7_LNAMIXRFATT22_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT22 */
+#define _AGC_PNRFATT7_LNAMIXRFATT22_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT22 */
+#define _AGC_PNRFATT7_LNAMIXRFATT22_DEFAULT 0x0000003FUL /**< Mode DEFAULT for AGC_PNRFATT7 */
+#define AGC_PNRFATT7_LNAMIXRFATT22_DEFAULT (_AGC_PNRFATT7_LNAMIXRFATT22_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFATT7 */
+#define _AGC_PNRFATT7_LNAMIXRFATT23_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT23 */
+#define _AGC_PNRFATT7_LNAMIXRFATT23_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT23 */
+#define _AGC_PNRFATT7_LNAMIXRFATT23_DEFAULT 0x0000006EUL /**< Mode DEFAULT for AGC_PNRFATT7 */
+#define AGC_PNRFATT7_LNAMIXRFATT23_DEFAULT (_AGC_PNRFATT7_LNAMIXRFATT23_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFATT7 */
+#define _AGC_PNRFATT7_LNAMIXRFATT24_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT24 */
+#define _AGC_PNRFATT7_LNAMIXRFATT24_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT24 */
+#define _AGC_PNRFATT7_LNAMIXRFATT24_DEFAULT 0x0000007FUL /**< Mode DEFAULT for AGC_PNRFATT7 */
+#define AGC_PNRFATT7_LNAMIXRFATT24_DEFAULT (_AGC_PNRFATT7_LNAMIXRFATT24_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFATT7 */
+
+/* Bit fields for AGC PNRFATTALT */
+#define _AGC_PNRFATTALT_RESETVALUE 0x0000007FUL /**< Default value for AGC_PNRFATTALT */
+#define _AGC_PNRFATTALT_MASK 0x000003FFUL /**< Mask for AGC_PNRFATTALT */
+#define _AGC_PNRFATTALT_LNAMIXRFATTALT_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATTALT */
+#define _AGC_PNRFATTALT_LNAMIXRFATTALT_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATTALT */
+#define _AGC_PNRFATTALT_LNAMIXRFATTALT_DEFAULT 0x0000007FUL /**< Mode DEFAULT for AGC_PNRFATTALT */
+#define AGC_PNRFATTALT_LNAMIXRFATTALT_DEFAULT (_AGC_PNRFATTALT_LNAMIXRFATTALT_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFATTALT */
+
+/* Bit fields for AGC LNAMIXCODE0 */
+#define _AGC_LNAMIXCODE0_RESETVALUE 0x15724BBDUL /**< Default value for AGC_LNAMIXCODE0 */
+#define _AGC_LNAMIXCODE0_MASK 0x3FFFFFFFUL /**< Mask for AGC_LNAMIXCODE0 */
+#define _AGC_LNAMIXCODE0_LNAMIXSLICE1_SHIFT 0 /**< Shift value for AGC_LNAMIXSLICE1 */
+#define _AGC_LNAMIXCODE0_LNAMIXSLICE1_MASK 0x3FUL /**< Bit mask for AGC_LNAMIXSLICE1 */
+#define _AGC_LNAMIXCODE0_LNAMIXSLICE1_DEFAULT 0x0000003DUL /**< Mode DEFAULT for AGC_LNAMIXCODE0 */
+#define AGC_LNAMIXCODE0_LNAMIXSLICE1_DEFAULT (_AGC_LNAMIXCODE0_LNAMIXSLICE1_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_LNAMIXCODE0 */
+#define _AGC_LNAMIXCODE0_LNAMIXSLICE2_SHIFT 6 /**< Shift value for AGC_LNAMIXSLICE2 */
+#define _AGC_LNAMIXCODE0_LNAMIXSLICE2_MASK 0xFC0UL /**< Bit mask for AGC_LNAMIXSLICE2 */
+#define _AGC_LNAMIXCODE0_LNAMIXSLICE2_DEFAULT 0x0000002EUL /**< Mode DEFAULT for AGC_LNAMIXCODE0 */
+#define AGC_LNAMIXCODE0_LNAMIXSLICE2_DEFAULT (_AGC_LNAMIXCODE0_LNAMIXSLICE2_DEFAULT << 6) /**< Shifted mode DEFAULT for AGC_LNAMIXCODE0 */
+#define _AGC_LNAMIXCODE0_LNAMIXSLICE3_SHIFT 12 /**< Shift value for AGC_LNAMIXSLICE3 */
+#define _AGC_LNAMIXCODE0_LNAMIXSLICE3_MASK 0x3F000UL /**< Bit mask for AGC_LNAMIXSLICE3 */
+#define _AGC_LNAMIXCODE0_LNAMIXSLICE3_DEFAULT 0x00000024UL /**< Mode DEFAULT for AGC_LNAMIXCODE0 */
+#define AGC_LNAMIXCODE0_LNAMIXSLICE3_DEFAULT (_AGC_LNAMIXCODE0_LNAMIXSLICE3_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_LNAMIXCODE0 */
+#define _AGC_LNAMIXCODE0_LNAMIXSLICE4_SHIFT 18 /**< Shift value for AGC_LNAMIXSLICE4 */
+#define _AGC_LNAMIXCODE0_LNAMIXSLICE4_MASK 0xFC0000UL /**< Bit mask for AGC_LNAMIXSLICE4 */
+#define _AGC_LNAMIXCODE0_LNAMIXSLICE4_DEFAULT 0x0000001CUL /**< Mode DEFAULT for AGC_LNAMIXCODE0 */
+#define AGC_LNAMIXCODE0_LNAMIXSLICE4_DEFAULT (_AGC_LNAMIXCODE0_LNAMIXSLICE4_DEFAULT << 18) /**< Shifted mode DEFAULT for AGC_LNAMIXCODE0 */
+#define _AGC_LNAMIXCODE0_LNAMIXSLICE5_SHIFT 24 /**< Shift value for AGC_LNAMIXSLICE5 */
+#define _AGC_LNAMIXCODE0_LNAMIXSLICE5_MASK 0x3F000000UL /**< Bit mask for AGC_LNAMIXSLICE5 */
+#define _AGC_LNAMIXCODE0_LNAMIXSLICE5_DEFAULT 0x00000015UL /**< Mode DEFAULT for AGC_LNAMIXCODE0 */
+#define AGC_LNAMIXCODE0_LNAMIXSLICE5_DEFAULT (_AGC_LNAMIXCODE0_LNAMIXSLICE5_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_LNAMIXCODE0 */
+
+/* Bit fields for AGC LNAMIXCODE1 */
+#define _AGC_LNAMIXCODE1_RESETVALUE 0x0518A311UL /**< Default value for AGC_LNAMIXCODE1 */
+#define _AGC_LNAMIXCODE1_MASK 0x3FFFFFFFUL /**< Mask for AGC_LNAMIXCODE1 */
+#define _AGC_LNAMIXCODE1_LNAMIXSLICE6_SHIFT 0 /**< Shift value for AGC_LNAMIXSLICE6 */
+#define _AGC_LNAMIXCODE1_LNAMIXSLICE6_MASK 0x3FUL /**< Bit mask for AGC_LNAMIXSLICE6 */
+#define _AGC_LNAMIXCODE1_LNAMIXSLICE6_DEFAULT 0x00000011UL /**< Mode DEFAULT for AGC_LNAMIXCODE1 */
+#define AGC_LNAMIXCODE1_LNAMIXSLICE6_DEFAULT (_AGC_LNAMIXCODE1_LNAMIXSLICE6_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_LNAMIXCODE1 */
+#define _AGC_LNAMIXCODE1_LNAMIXSLICE7_SHIFT 6 /**< Shift value for AGC_LNAMIXSLICE7 */
+#define _AGC_LNAMIXCODE1_LNAMIXSLICE7_MASK 0xFC0UL /**< Bit mask for AGC_LNAMIXSLICE7 */
+#define _AGC_LNAMIXCODE1_LNAMIXSLICE7_DEFAULT 0x0000000CUL /**< Mode DEFAULT for AGC_LNAMIXCODE1 */
+#define AGC_LNAMIXCODE1_LNAMIXSLICE7_DEFAULT (_AGC_LNAMIXCODE1_LNAMIXSLICE7_DEFAULT << 6) /**< Shifted mode DEFAULT for AGC_LNAMIXCODE1 */
+#define _AGC_LNAMIXCODE1_LNAMIXSLICE8_SHIFT 12 /**< Shift value for AGC_LNAMIXSLICE8 */
+#define _AGC_LNAMIXCODE1_LNAMIXSLICE8_MASK 0x3F000UL /**< Bit mask for AGC_LNAMIXSLICE8 */
+#define _AGC_LNAMIXCODE1_LNAMIXSLICE8_DEFAULT 0x0000000AUL /**< Mode DEFAULT for AGC_LNAMIXCODE1 */
+#define AGC_LNAMIXCODE1_LNAMIXSLICE8_DEFAULT (_AGC_LNAMIXCODE1_LNAMIXSLICE8_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_LNAMIXCODE1 */
+#define _AGC_LNAMIXCODE1_LNAMIXSLICE9_SHIFT 18 /**< Shift value for AGC_LNAMIXSLICE9 */
+#define _AGC_LNAMIXCODE1_LNAMIXSLICE9_MASK 0xFC0000UL /**< Bit mask for AGC_LNAMIXSLICE9 */
+#define _AGC_LNAMIXCODE1_LNAMIXSLICE9_DEFAULT 0x00000006UL /**< Mode DEFAULT for AGC_LNAMIXCODE1 */
+#define AGC_LNAMIXCODE1_LNAMIXSLICE9_DEFAULT (_AGC_LNAMIXCODE1_LNAMIXSLICE9_DEFAULT << 18) /**< Shifted mode DEFAULT for AGC_LNAMIXCODE1 */
+#define _AGC_LNAMIXCODE1_LNAMIXSLICE10_SHIFT 24 /**< Shift value for AGC_LNAMIXSLICE10 */
+#define _AGC_LNAMIXCODE1_LNAMIXSLICE10_MASK 0x3F000000UL /**< Bit mask for AGC_LNAMIXSLICE10 */
+#define _AGC_LNAMIXCODE1_LNAMIXSLICE10_DEFAULT 0x00000005UL /**< Mode DEFAULT for AGC_LNAMIXCODE1 */
+#define AGC_LNAMIXCODE1_LNAMIXSLICE10_DEFAULT (_AGC_LNAMIXCODE1_LNAMIXSLICE10_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_LNAMIXCODE1 */
+
+/* Bit fields for AGC PGACODE0 */
+#define _AGC_PGACODE0_RESETVALUE 0x76543210UL /**< Default value for AGC_PGACODE0 */
+#define _AGC_PGACODE0_MASK 0xFFFFFFFFUL /**< Mask for AGC_PGACODE0 */
+#define _AGC_PGACODE0_PGAGAIN1_SHIFT 0 /**< Shift value for AGC_PGAGAIN1 */
+#define _AGC_PGACODE0_PGAGAIN1_MASK 0xFUL /**< Bit mask for AGC_PGAGAIN1 */
+#define _AGC_PGACODE0_PGAGAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_PGACODE0 */
+#define AGC_PGACODE0_PGAGAIN1_DEFAULT (_AGC_PGACODE0_PGAGAIN1_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PGACODE0 */
+#define _AGC_PGACODE0_PGAGAIN2_SHIFT 4 /**< Shift value for AGC_PGAGAIN2 */
+#define _AGC_PGACODE0_PGAGAIN2_MASK 0xF0UL /**< Bit mask for AGC_PGAGAIN2 */
+#define _AGC_PGACODE0_PGAGAIN2_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_PGACODE0 */
+#define AGC_PGACODE0_PGAGAIN2_DEFAULT (_AGC_PGACODE0_PGAGAIN2_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_PGACODE0 */
+#define _AGC_PGACODE0_PGAGAIN3_SHIFT 8 /**< Shift value for AGC_PGAGAIN3 */
+#define _AGC_PGACODE0_PGAGAIN3_MASK 0xF00UL /**< Bit mask for AGC_PGAGAIN3 */
+#define _AGC_PGACODE0_PGAGAIN3_DEFAULT 0x00000002UL /**< Mode DEFAULT for AGC_PGACODE0 */
+#define AGC_PGACODE0_PGAGAIN3_DEFAULT (_AGC_PGACODE0_PGAGAIN3_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_PGACODE0 */
+#define _AGC_PGACODE0_PGAGAIN4_SHIFT 12 /**< Shift value for AGC_PGAGAIN4 */
+#define _AGC_PGACODE0_PGAGAIN4_MASK 0xF000UL /**< Bit mask for AGC_PGAGAIN4 */
+#define _AGC_PGACODE0_PGAGAIN4_DEFAULT 0x00000003UL /**< Mode DEFAULT for AGC_PGACODE0 */
+#define AGC_PGACODE0_PGAGAIN4_DEFAULT (_AGC_PGACODE0_PGAGAIN4_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_PGACODE0 */
+#define _AGC_PGACODE0_PGAGAIN5_SHIFT 16 /**< Shift value for AGC_PGAGAIN5 */
+#define _AGC_PGACODE0_PGAGAIN5_MASK 0xF0000UL /**< Bit mask for AGC_PGAGAIN5 */
+#define _AGC_PGACODE0_PGAGAIN5_DEFAULT 0x00000004UL /**< Mode DEFAULT for AGC_PGACODE0 */
+#define AGC_PGACODE0_PGAGAIN5_DEFAULT (_AGC_PGACODE0_PGAGAIN5_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_PGACODE0 */
+#define _AGC_PGACODE0_PGAGAIN6_SHIFT 20 /**< Shift value for AGC_PGAGAIN6 */
+#define _AGC_PGACODE0_PGAGAIN6_MASK 0xF00000UL /**< Bit mask for AGC_PGAGAIN6 */
+#define _AGC_PGACODE0_PGAGAIN6_DEFAULT 0x00000005UL /**< Mode DEFAULT for AGC_PGACODE0 */
+#define AGC_PGACODE0_PGAGAIN6_DEFAULT (_AGC_PGACODE0_PGAGAIN6_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PGACODE0 */
+#define _AGC_PGACODE0_PGAGAIN7_SHIFT 24 /**< Shift value for AGC_PGAGAIN7 */
+#define _AGC_PGACODE0_PGAGAIN7_MASK 0xF000000UL /**< Bit mask for AGC_PGAGAIN7 */
+#define _AGC_PGACODE0_PGAGAIN7_DEFAULT 0x00000006UL /**< Mode DEFAULT for AGC_PGACODE0 */
+#define AGC_PGACODE0_PGAGAIN7_DEFAULT (_AGC_PGACODE0_PGAGAIN7_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_PGACODE0 */
+#define _AGC_PGACODE0_PGAGAIN8_SHIFT 28 /**< Shift value for AGC_PGAGAIN8 */
+#define _AGC_PGACODE0_PGAGAIN8_MASK 0xF0000000UL /**< Bit mask for AGC_PGAGAIN8 */
+#define _AGC_PGACODE0_PGAGAIN8_DEFAULT 0x00000007UL /**< Mode DEFAULT for AGC_PGACODE0 */
+#define AGC_PGACODE0_PGAGAIN8_DEFAULT (_AGC_PGACODE0_PGAGAIN8_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_PGACODE0 */
+
+/* Bit fields for AGC PGACODE1 */
+#define _AGC_PGACODE1_RESETVALUE 0x00000A98UL /**< Default value for AGC_PGACODE1 */
+#define _AGC_PGACODE1_MASK 0x00000FFFUL /**< Mask for AGC_PGACODE1 */
+#define _AGC_PGACODE1_PGAGAIN9_SHIFT 0 /**< Shift value for AGC_PGAGAIN9 */
+#define _AGC_PGACODE1_PGAGAIN9_MASK 0xFUL /**< Bit mask for AGC_PGAGAIN9 */
+#define _AGC_PGACODE1_PGAGAIN9_DEFAULT 0x00000008UL /**< Mode DEFAULT for AGC_PGACODE1 */
+#define AGC_PGACODE1_PGAGAIN9_DEFAULT (_AGC_PGACODE1_PGAGAIN9_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PGACODE1 */
+#define _AGC_PGACODE1_PGAGAIN10_SHIFT 4 /**< Shift value for AGC_PGAGAIN10 */
+#define _AGC_PGACODE1_PGAGAIN10_MASK 0xF0UL /**< Bit mask for AGC_PGAGAIN10 */
+#define _AGC_PGACODE1_PGAGAIN10_DEFAULT 0x00000009UL /**< Mode DEFAULT for AGC_PGACODE1 */
+#define AGC_PGACODE1_PGAGAIN10_DEFAULT (_AGC_PGACODE1_PGAGAIN10_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_PGACODE1 */
+#define _AGC_PGACODE1_PGAGAIN11_SHIFT 8 /**< Shift value for AGC_PGAGAIN11 */
+#define _AGC_PGACODE1_PGAGAIN11_MASK 0xF00UL /**< Bit mask for AGC_PGAGAIN11 */
+#define _AGC_PGACODE1_PGAGAIN11_DEFAULT 0x0000000AUL /**< Mode DEFAULT for AGC_PGACODE1 */
+#define AGC_PGACODE1_PGAGAIN11_DEFAULT (_AGC_PGACODE1_PGAGAIN11_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_PGACODE1 */
+
+/* Bit fields for AGC LBT */
+#define _AGC_LBT_RESETVALUE 0x00000000UL /**< Default value for AGC_LBT */
+#define _AGC_LBT_MASK 0x0000007FUL /**< Mask for AGC_LBT */
+#define _AGC_LBT_CCARSSIPERIOD_SHIFT 0 /**< Shift value for AGC_CCARSSIPERIOD */
+#define _AGC_LBT_CCARSSIPERIOD_MASK 0xFUL /**< Bit mask for AGC_CCARSSIPERIOD */
+#define _AGC_LBT_CCARSSIPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_LBT */
+#define AGC_LBT_CCARSSIPERIOD_DEFAULT (_AGC_LBT_CCARSSIPERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_LBT */
+#define AGC_LBT_ENCCARSSIPERIOD (0x1UL << 4) /**< RSSI PERIOD during CCA measurements */
+#define _AGC_LBT_ENCCARSSIPERIOD_SHIFT 4 /**< Shift value for AGC_ENCCARSSIPERIOD */
+#define _AGC_LBT_ENCCARSSIPERIOD_MASK 0x10UL /**< Bit mask for AGC_ENCCARSSIPERIOD */
+#define _AGC_LBT_ENCCARSSIPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_LBT */
+#define AGC_LBT_ENCCARSSIPERIOD_DEFAULT (_AGC_LBT_ENCCARSSIPERIOD_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_LBT */
+#define AGC_LBT_ENCCAGAINREDUCED (0x1UL << 5) /**< CCA gain reduced */
+#define _AGC_LBT_ENCCAGAINREDUCED_SHIFT 5 /**< Shift value for AGC_ENCCAGAINREDUCED */
+#define _AGC_LBT_ENCCAGAINREDUCED_MASK 0x20UL /**< Bit mask for AGC_ENCCAGAINREDUCED */
+#define _AGC_LBT_ENCCAGAINREDUCED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_LBT */
+#define AGC_LBT_ENCCAGAINREDUCED_DEFAULT (_AGC_LBT_ENCCAGAINREDUCED_DEFAULT << 5) /**< Shifted mode DEFAULT for AGC_LBT */
+#define AGC_LBT_ENCCARSSIMAX (0x1UL << 6) /**< Use RSSIMAX to indicate CCA */
+#define _AGC_LBT_ENCCARSSIMAX_SHIFT 6 /**< Shift value for AGC_ENCCARSSIMAX */
+#define _AGC_LBT_ENCCARSSIMAX_MASK 0x40UL /**< Bit mask for AGC_ENCCARSSIMAX */
+#define _AGC_LBT_ENCCARSSIMAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_LBT */
+#define AGC_LBT_ENCCARSSIMAX_DEFAULT (_AGC_LBT_ENCCARSSIMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for AGC_LBT */
+
+/* Bit fields for AGC MIRRORIF */
+#define _AGC_MIRRORIF_RESETVALUE 0x00000000UL /**< Default value for AGC_MIRRORIF */
+#define _AGC_MIRRORIF_MASK 0x0000000FUL /**< Mask for AGC_MIRRORIF */
+#define AGC_MIRRORIF_RSSIPOSSTEPM (0x1UL << 0) /**< Positive RSSI Step Detected */
+#define _AGC_MIRRORIF_RSSIPOSSTEPM_SHIFT 0 /**< Shift value for AGC_RSSIPOSSTEPM */
+#define _AGC_MIRRORIF_RSSIPOSSTEPM_MASK 0x1UL /**< Bit mask for AGC_RSSIPOSSTEPM */
+#define _AGC_MIRRORIF_RSSIPOSSTEPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_MIRRORIF */
+#define AGC_MIRRORIF_RSSIPOSSTEPM_DEFAULT (_AGC_MIRRORIF_RSSIPOSSTEPM_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_MIRRORIF */
+#define AGC_MIRRORIF_RSSINEGSTEPM (0x1UL << 1) /**< Negative RSSI Step Detected */
+#define _AGC_MIRRORIF_RSSINEGSTEPM_SHIFT 1 /**< Shift value for AGC_RSSINEGSTEPM */
+#define _AGC_MIRRORIF_RSSINEGSTEPM_MASK 0x2UL /**< Bit mask for AGC_RSSINEGSTEPM */
+#define _AGC_MIRRORIF_RSSINEGSTEPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_MIRRORIF */
+#define AGC_MIRRORIF_RSSINEGSTEPM_DEFAULT (_AGC_MIRRORIF_RSSINEGSTEPM_DEFAULT << 1) /**< Shifted mode DEFAULT for AGC_MIRRORIF */
+#define AGC_MIRRORIF_SHORTRSSIPOSSTEPM (0x1UL << 2) /**< Short-term Positive RSSI Step Detected */
+#define _AGC_MIRRORIF_SHORTRSSIPOSSTEPM_SHIFT 2 /**< Shift value for AGC_SHORTRSSIPOSSTEPM */
+#define _AGC_MIRRORIF_SHORTRSSIPOSSTEPM_MASK 0x4UL /**< Bit mask for AGC_SHORTRSSIPOSSTEPM */
+#define _AGC_MIRRORIF_SHORTRSSIPOSSTEPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_MIRRORIF */
+#define AGC_MIRRORIF_SHORTRSSIPOSSTEPM_DEFAULT (_AGC_MIRRORIF_SHORTRSSIPOSSTEPM_DEFAULT << 2) /**< Shifted mode DEFAULT for AGC_MIRRORIF */
+#define AGC_MIRRORIF_IFMIRRORCLEAR (0x1UL << 3) /**< Clear bit for the AGC IF MIRROR Register */
+#define _AGC_MIRRORIF_IFMIRRORCLEAR_SHIFT 3 /**< Shift value for AGC_IFMIRRORCLEAR */
+#define _AGC_MIRRORIF_IFMIRRORCLEAR_MASK 0x8UL /**< Bit mask for AGC_IFMIRRORCLEAR */
+#define _AGC_MIRRORIF_IFMIRRORCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_MIRRORIF */
+#define AGC_MIRRORIF_IFMIRRORCLEAR_DEFAULT (_AGC_MIRRORIF_IFMIRRORCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for AGC_MIRRORIF */
+
+/* Bit fields for AGC SEQIF */
+#define _AGC_SEQIF_RESETVALUE 0x00000000UL /**< Default value for AGC_SEQIF */
+#define _AGC_SEQIF_MASK 0x00007F7DUL /**< Mask for AGC_SEQIF */
+#define AGC_SEQIF_RSSIVALID (0x1UL << 0) /**< RSSI Value is Valid */
+#define _AGC_SEQIF_RSSIVALID_SHIFT 0 /**< Shift value for AGC_RSSIVALID */
+#define _AGC_SEQIF_RSSIVALID_MASK 0x1UL /**< Bit mask for AGC_RSSIVALID */
+#define _AGC_SEQIF_RSSIVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIF */
+#define AGC_SEQIF_RSSIVALID_DEFAULT (_AGC_SEQIF_RSSIVALID_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_SEQIF */
+#define AGC_SEQIF_CCA (0x1UL << 2) /**< Clear Channel Assessment */
+#define _AGC_SEQIF_CCA_SHIFT 2 /**< Shift value for AGC_CCA */
+#define _AGC_SEQIF_CCA_MASK 0x4UL /**< Bit mask for AGC_CCA */
+#define _AGC_SEQIF_CCA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIF */
+#define AGC_SEQIF_CCA_DEFAULT (_AGC_SEQIF_CCA_DEFAULT << 2) /**< Shifted mode DEFAULT for AGC_SEQIF */
+#define AGC_SEQIF_RSSIPOSSTEP (0x1UL << 3) /**< Positive RSSI Step Detected */
+#define _AGC_SEQIF_RSSIPOSSTEP_SHIFT 3 /**< Shift value for AGC_RSSIPOSSTEP */
+#define _AGC_SEQIF_RSSIPOSSTEP_MASK 0x8UL /**< Bit mask for AGC_RSSIPOSSTEP */
+#define _AGC_SEQIF_RSSIPOSSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIF */
+#define AGC_SEQIF_RSSIPOSSTEP_DEFAULT (_AGC_SEQIF_RSSIPOSSTEP_DEFAULT << 3) /**< Shifted mode DEFAULT for AGC_SEQIF */
+#define AGC_SEQIF_RSSINEGSTEP (0x1UL << 4) /**< Negative RSSI Step Detected */
+#define _AGC_SEQIF_RSSINEGSTEP_SHIFT 4 /**< Shift value for AGC_RSSINEGSTEP */
+#define _AGC_SEQIF_RSSINEGSTEP_MASK 0x10UL /**< Bit mask for AGC_RSSINEGSTEP */
+#define _AGC_SEQIF_RSSINEGSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIF */
+#define AGC_SEQIF_RSSINEGSTEP_DEFAULT (_AGC_SEQIF_RSSINEGSTEP_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_SEQIF */
+#define AGC_SEQIF_SHORTRSSIPOSSTEP (0x1UL << 6) /**< Short-term Positive RSSI Step Detected */
+#define _AGC_SEQIF_SHORTRSSIPOSSTEP_SHIFT 6 /**< Shift value for AGC_SHORTRSSIPOSSTEP */
+#define _AGC_SEQIF_SHORTRSSIPOSSTEP_MASK 0x40UL /**< Bit mask for AGC_SHORTRSSIPOSSTEP */
+#define _AGC_SEQIF_SHORTRSSIPOSSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIF */
+#define AGC_SEQIF_SHORTRSSIPOSSTEP_DEFAULT (_AGC_SEQIF_SHORTRSSIPOSSTEP_DEFAULT << 6) /**< Shifted mode DEFAULT for AGC_SEQIF */
+#define AGC_SEQIF_RFPKDPRDDONE (0x1UL << 8) /**< RF PKD PERIOD CNT TOMEOUT */
+#define _AGC_SEQIF_RFPKDPRDDONE_SHIFT 8 /**< Shift value for AGC_RFPKDPRDDONE */
+#define _AGC_SEQIF_RFPKDPRDDONE_MASK 0x100UL /**< Bit mask for AGC_RFPKDPRDDONE */
+#define _AGC_SEQIF_RFPKDPRDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIF */
+#define AGC_SEQIF_RFPKDPRDDONE_DEFAULT (_AGC_SEQIF_RFPKDPRDDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_SEQIF */
+#define AGC_SEQIF_RFPKDCNTDONE (0x1UL << 9) /**< RF PKD pulse CNT TOMEOUT */
+#define _AGC_SEQIF_RFPKDCNTDONE_SHIFT 9 /**< Shift value for AGC_RFPKDCNTDONE */
+#define _AGC_SEQIF_RFPKDCNTDONE_MASK 0x200UL /**< Bit mask for AGC_RFPKDCNTDONE */
+#define _AGC_SEQIF_RFPKDCNTDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIF */
+#define AGC_SEQIF_RFPKDCNTDONE_DEFAULT (_AGC_SEQIF_RFPKDCNTDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for AGC_SEQIF */
+#define AGC_SEQIF_RSSIHIGH (0x1UL << 10) /**< RSSI high detected */
+#define _AGC_SEQIF_RSSIHIGH_SHIFT 10 /**< Shift value for AGC_RSSIHIGH */
+#define _AGC_SEQIF_RSSIHIGH_MASK 0x400UL /**< Bit mask for AGC_RSSIHIGH */
+#define _AGC_SEQIF_RSSIHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIF */
+#define AGC_SEQIF_RSSIHIGH_DEFAULT (_AGC_SEQIF_RSSIHIGH_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_SEQIF */
+#define AGC_SEQIF_RSSILOW (0x1UL << 11) /**< RSSI low detected */
+#define _AGC_SEQIF_RSSILOW_SHIFT 11 /**< Shift value for AGC_RSSILOW */
+#define _AGC_SEQIF_RSSILOW_MASK 0x800UL /**< Bit mask for AGC_RSSILOW */
+#define _AGC_SEQIF_RSSILOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIF */
+#define AGC_SEQIF_RSSILOW_DEFAULT (_AGC_SEQIF_RSSILOW_DEFAULT << 11) /**< Shifted mode DEFAULT for AGC_SEQIF */
+#define AGC_SEQIF_CCANODET (0x1UL << 12) /**< CCA Not Detected */
+#define _AGC_SEQIF_CCANODET_SHIFT 12 /**< Shift value for AGC_CCANODET */
+#define _AGC_SEQIF_CCANODET_MASK 0x1000UL /**< Bit mask for AGC_CCANODET */
+#define _AGC_SEQIF_CCANODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIF */
+#define AGC_SEQIF_CCANODET_DEFAULT (_AGC_SEQIF_CCANODET_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_SEQIF */
+#define AGC_SEQIF_GAINBELOWGAINTHD (0x1UL << 13) /**< agc gain above threshold int */
+#define _AGC_SEQIF_GAINBELOWGAINTHD_SHIFT 13 /**< Shift value for AGC_GAINBELOWGAINTHD */
+#define _AGC_SEQIF_GAINBELOWGAINTHD_MASK 0x2000UL /**< Bit mask for AGC_GAINBELOWGAINTHD */
+#define _AGC_SEQIF_GAINBELOWGAINTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIF */
+#define AGC_SEQIF_GAINBELOWGAINTHD_DEFAULT (_AGC_SEQIF_GAINBELOWGAINTHD_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_SEQIF */
+#define AGC_SEQIF_GAINUPDATEFRZ (0x1UL << 14) /**< AGC gain update frozen int */
+#define _AGC_SEQIF_GAINUPDATEFRZ_SHIFT 14 /**< Shift value for AGC_GAINUPDATEFRZ */
+#define _AGC_SEQIF_GAINUPDATEFRZ_MASK 0x4000UL /**< Bit mask for AGC_GAINUPDATEFRZ */
+#define _AGC_SEQIF_GAINUPDATEFRZ_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIF */
+#define AGC_SEQIF_GAINUPDATEFRZ_DEFAULT (_AGC_SEQIF_GAINUPDATEFRZ_DEFAULT << 14) /**< Shifted mode DEFAULT for AGC_SEQIF */
+
+/* Bit fields for AGC SEQIEN */
+#define _AGC_SEQIEN_RESETVALUE 0x00000000UL /**< Default value for AGC_SEQIEN */
+#define _AGC_SEQIEN_MASK 0x00007F7DUL /**< Mask for AGC_SEQIEN */
+#define AGC_SEQIEN_RSSIVALID (0x1UL << 0) /**< RSSIVALID Interrupt Enable */
+#define _AGC_SEQIEN_RSSIVALID_SHIFT 0 /**< Shift value for AGC_RSSIVALID */
+#define _AGC_SEQIEN_RSSIVALID_MASK 0x1UL /**< Bit mask for AGC_RSSIVALID */
+#define _AGC_SEQIEN_RSSIVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIEN */
+#define AGC_SEQIEN_RSSIVALID_DEFAULT (_AGC_SEQIEN_RSSIVALID_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_SEQIEN */
+#define AGC_SEQIEN_CCA (0x1UL << 2) /**< CCA Interrupt Enable */
+#define _AGC_SEQIEN_CCA_SHIFT 2 /**< Shift value for AGC_CCA */
+#define _AGC_SEQIEN_CCA_MASK 0x4UL /**< Bit mask for AGC_CCA */
+#define _AGC_SEQIEN_CCA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIEN */
+#define AGC_SEQIEN_CCA_DEFAULT (_AGC_SEQIEN_CCA_DEFAULT << 2) /**< Shifted mode DEFAULT for AGC_SEQIEN */
+#define AGC_SEQIEN_RSSIPOSSTEP (0x1UL << 3) /**< RSSIPOSSTEP Interrupt Enable */
+#define _AGC_SEQIEN_RSSIPOSSTEP_SHIFT 3 /**< Shift value for AGC_RSSIPOSSTEP */
+#define _AGC_SEQIEN_RSSIPOSSTEP_MASK 0x8UL /**< Bit mask for AGC_RSSIPOSSTEP */
+#define _AGC_SEQIEN_RSSIPOSSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIEN */
+#define AGC_SEQIEN_RSSIPOSSTEP_DEFAULT (_AGC_SEQIEN_RSSIPOSSTEP_DEFAULT << 3) /**< Shifted mode DEFAULT for AGC_SEQIEN */
+#define AGC_SEQIEN_RSSINEGSTEP (0x1UL << 4) /**< RSSINEGSTEP Interrupt Enable */
+#define _AGC_SEQIEN_RSSINEGSTEP_SHIFT 4 /**< Shift value for AGC_RSSINEGSTEP */
+#define _AGC_SEQIEN_RSSINEGSTEP_MASK 0x10UL /**< Bit mask for AGC_RSSINEGSTEP */
+#define _AGC_SEQIEN_RSSINEGSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIEN */
+#define AGC_SEQIEN_RSSINEGSTEP_DEFAULT (_AGC_SEQIEN_RSSINEGSTEP_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_SEQIEN */
+#define AGC_SEQIEN_SHORTRSSIPOSSTEP (0x1UL << 6) /**< SHORTRSSIPOSSTEP Interrupt Enable */
+#define _AGC_SEQIEN_SHORTRSSIPOSSTEP_SHIFT 6 /**< Shift value for AGC_SHORTRSSIPOSSTEP */
+#define _AGC_SEQIEN_SHORTRSSIPOSSTEP_MASK 0x40UL /**< Bit mask for AGC_SHORTRSSIPOSSTEP */
+#define _AGC_SEQIEN_SHORTRSSIPOSSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIEN */
+#define AGC_SEQIEN_SHORTRSSIPOSSTEP_DEFAULT (_AGC_SEQIEN_SHORTRSSIPOSSTEP_DEFAULT << 6) /**< Shifted mode DEFAULT for AGC_SEQIEN */
+#define AGC_SEQIEN_RFPKDPRDDONE (0x1UL << 8) /**< RF PKD PERIOD CNT Interrupt Enable */
+#define _AGC_SEQIEN_RFPKDPRDDONE_SHIFT 8 /**< Shift value for AGC_RFPKDPRDDONE */
+#define _AGC_SEQIEN_RFPKDPRDDONE_MASK 0x100UL /**< Bit mask for AGC_RFPKDPRDDONE */
+#define _AGC_SEQIEN_RFPKDPRDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIEN */
+#define AGC_SEQIEN_RFPKDPRDDONE_DEFAULT (_AGC_SEQIEN_RFPKDPRDDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_SEQIEN */
+#define AGC_SEQIEN_RFPKDCNTDONE (0x1UL << 9) /**< RF PKD pulse CNT Interrupt Enable */
+#define _AGC_SEQIEN_RFPKDCNTDONE_SHIFT 9 /**< Shift value for AGC_RFPKDCNTDONE */
+#define _AGC_SEQIEN_RFPKDCNTDONE_MASK 0x200UL /**< Bit mask for AGC_RFPKDCNTDONE */
+#define _AGC_SEQIEN_RFPKDCNTDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIEN */
+#define AGC_SEQIEN_RFPKDCNTDONE_DEFAULT (_AGC_SEQIEN_RFPKDCNTDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for AGC_SEQIEN */
+#define AGC_SEQIEN_RSSIHIGH (0x1UL << 10) /**< RSSIHIGH Interrupt Enable */
+#define _AGC_SEQIEN_RSSIHIGH_SHIFT 10 /**< Shift value for AGC_RSSIHIGH */
+#define _AGC_SEQIEN_RSSIHIGH_MASK 0x400UL /**< Bit mask for AGC_RSSIHIGH */
+#define _AGC_SEQIEN_RSSIHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIEN */
+#define AGC_SEQIEN_RSSIHIGH_DEFAULT (_AGC_SEQIEN_RSSIHIGH_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_SEQIEN */
+#define AGC_SEQIEN_RSSILOW (0x1UL << 11) /**< RSSILOW Interrupt Enable */
+#define _AGC_SEQIEN_RSSILOW_SHIFT 11 /**< Shift value for AGC_RSSILOW */
+#define _AGC_SEQIEN_RSSILOW_MASK 0x800UL /**< Bit mask for AGC_RSSILOW */
+#define _AGC_SEQIEN_RSSILOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIEN */
+#define AGC_SEQIEN_RSSILOW_DEFAULT (_AGC_SEQIEN_RSSILOW_DEFAULT << 11) /**< Shifted mode DEFAULT for AGC_SEQIEN */
+#define AGC_SEQIEN_CCANODET (0x1UL << 12) /**< CCANODET Interrupt Enable */
+#define _AGC_SEQIEN_CCANODET_SHIFT 12 /**< Shift value for AGC_CCANODET */
+#define _AGC_SEQIEN_CCANODET_MASK 0x1000UL /**< Bit mask for AGC_CCANODET */
+#define _AGC_SEQIEN_CCANODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIEN */
+#define AGC_SEQIEN_CCANODET_DEFAULT (_AGC_SEQIEN_CCANODET_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_SEQIEN */
+#define AGC_SEQIEN_GAINBELOWGAINTHD (0x1UL << 13) /**< GAINBELOWGAINTHD Interrupt Enable */
+#define _AGC_SEQIEN_GAINBELOWGAINTHD_SHIFT 13 /**< Shift value for AGC_GAINBELOWGAINTHD */
+#define _AGC_SEQIEN_GAINBELOWGAINTHD_MASK 0x2000UL /**< Bit mask for AGC_GAINBELOWGAINTHD */
+#define _AGC_SEQIEN_GAINBELOWGAINTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIEN */
+#define AGC_SEQIEN_GAINBELOWGAINTHD_DEFAULT (_AGC_SEQIEN_GAINBELOWGAINTHD_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_SEQIEN */
+#define AGC_SEQIEN_GAINUPDATEFRZ (0x1UL << 14) /**< AGC gain update frozen int Enable */
+#define _AGC_SEQIEN_GAINUPDATEFRZ_SHIFT 14 /**< Shift value for AGC_GAINUPDATEFRZ */
+#define _AGC_SEQIEN_GAINUPDATEFRZ_MASK 0x4000UL /**< Bit mask for AGC_GAINUPDATEFRZ */
+#define _AGC_SEQIEN_GAINUPDATEFRZ_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SEQIEN */
+#define AGC_SEQIEN_GAINUPDATEFRZ_DEFAULT (_AGC_SEQIEN_GAINUPDATEFRZ_DEFAULT << 14) /**< Shifted mode DEFAULT for AGC_SEQIEN */
+
+/* Bit fields for AGC RSSIABSTHR */
+#define _AGC_RSSIABSTHR_RESETVALUE 0x00000000UL /**< Default value for AGC_RSSIABSTHR */
+#define _AGC_RSSIABSTHR_MASK 0xFFFFFFFFUL /**< Mask for AGC_RSSIABSTHR */
+#define _AGC_RSSIABSTHR_RSSIHIGHTHRSH_SHIFT 0 /**< Shift value for AGC_RSSIHIGHTHRSH */
+#define _AGC_RSSIABSTHR_RSSIHIGHTHRSH_MASK 0xFFUL /**< Bit mask for AGC_RSSIHIGHTHRSH */
+#define _AGC_RSSIABSTHR_RSSIHIGHTHRSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_RSSIABSTHR */
+#define AGC_RSSIABSTHR_RSSIHIGHTHRSH_DEFAULT (_AGC_RSSIABSTHR_RSSIHIGHTHRSH_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_RSSIABSTHR */
+#define _AGC_RSSIABSTHR_RSSILOWTHRSH_SHIFT 8 /**< Shift value for AGC_RSSILOWTHRSH */
+#define _AGC_RSSIABSTHR_RSSILOWTHRSH_MASK 0xFF00UL /**< Bit mask for AGC_RSSILOWTHRSH */
+#define _AGC_RSSIABSTHR_RSSILOWTHRSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_RSSIABSTHR */
+#define AGC_RSSIABSTHR_RSSILOWTHRSH_DEFAULT (_AGC_RSSIABSTHR_RSSILOWTHRSH_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_RSSIABSTHR */
+#define _AGC_RSSIABSTHR_SIRSSIHIGHTHR_SHIFT 16 /**< Shift value for AGC_SIRSSIHIGHTHR */
+#define _AGC_RSSIABSTHR_SIRSSIHIGHTHR_MASK 0xFF0000UL /**< Bit mask for AGC_SIRSSIHIGHTHR */
+#define _AGC_RSSIABSTHR_SIRSSIHIGHTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_RSSIABSTHR */
+#define AGC_RSSIABSTHR_SIRSSIHIGHTHR_DEFAULT (_AGC_RSSIABSTHR_SIRSSIHIGHTHR_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_RSSIABSTHR */
+#define _AGC_RSSIABSTHR_SIRSSINEGSTEPTHR_SHIFT 24 /**< Shift value for AGC_SIRSSINEGSTEPTHR */
+#define _AGC_RSSIABSTHR_SIRSSINEGSTEPTHR_MASK 0xFF000000UL /**< Bit mask for AGC_SIRSSINEGSTEPTHR */
+#define _AGC_RSSIABSTHR_SIRSSINEGSTEPTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_RSSIABSTHR */
+#define AGC_RSSIABSTHR_SIRSSINEGSTEPTHR_DEFAULT (_AGC_RSSIABSTHR_SIRSSINEGSTEPTHR_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_RSSIABSTHR */
+
+/* Bit fields for AGC LNABOOST */
+#define _AGC_LNABOOST_RESETVALUE 0x000001FEUL /**< Default value for AGC_LNABOOST */
+#define _AGC_LNABOOST_MASK 0x000001FFUL /**< Mask for AGC_LNABOOST */
+#define AGC_LNABOOST_BOOSTLNA (0x1UL << 0) /**< LNA GAIN BOOST mode */
+#define _AGC_LNABOOST_BOOSTLNA_SHIFT 0 /**< Shift value for AGC_BOOSTLNA */
+#define _AGC_LNABOOST_BOOSTLNA_MASK 0x1UL /**< Bit mask for AGC_BOOSTLNA */
+#define _AGC_LNABOOST_BOOSTLNA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_LNABOOST */
+#define AGC_LNABOOST_BOOSTLNA_DEFAULT (_AGC_LNABOOST_BOOSTLNA_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_LNABOOST */
+#define _AGC_LNABOOST_LNABWADJ_SHIFT 1 /**< Shift value for AGC_LNABWADJ */
+#define _AGC_LNABOOST_LNABWADJ_MASK 0x1EUL /**< Bit mask for AGC_LNABWADJ */
+#define _AGC_LNABOOST_LNABWADJ_DEFAULT 0x0000000FUL /**< Mode DEFAULT for AGC_LNABOOST */
+#define AGC_LNABOOST_LNABWADJ_DEFAULT (_AGC_LNABOOST_LNABWADJ_DEFAULT << 1) /**< Shifted mode DEFAULT for AGC_LNABOOST */
+#define _AGC_LNABOOST_LNABWADJBOOST_SHIFT 5 /**< Shift value for AGC_LNABWADJBOOST */
+#define _AGC_LNABOOST_LNABWADJBOOST_MASK 0x1E0UL /**< Bit mask for AGC_LNABWADJBOOST */
+#define _AGC_LNABOOST_LNABWADJBOOST_DEFAULT 0x0000000FUL /**< Mode DEFAULT for AGC_LNABOOST */
+#define AGC_LNABOOST_LNABWADJBOOST_DEFAULT (_AGC_LNABOOST_LNABWADJBOOST_DEFAULT << 5) /**< Shifted mode DEFAULT for AGC_LNABOOST */
+
+/* Bit fields for AGC ANTDIV */
+#define _AGC_ANTDIV_RESETVALUE 0x00000000UL /**< Default value for AGC_ANTDIV */
+#define _AGC_ANTDIV_MASK 0x000007FFUL /**< Mask for AGC_ANTDIV */
+#define _AGC_ANTDIV_GAINMODE_SHIFT 0 /**< Shift value for AGC_GAINMODE */
+#define _AGC_ANTDIV_GAINMODE_MASK 0x3UL /**< Bit mask for AGC_GAINMODE */
+#define _AGC_ANTDIV_GAINMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_ANTDIV */
+#define _AGC_ANTDIV_GAINMODE_DISABLE 0x00000000UL /**< Mode DISABLE for AGC_ANTDIV */
+#define _AGC_ANTDIV_GAINMODE_SINGLE_PACKET 0x00000001UL /**< Mode SINGLE_PACKET for AGC_ANTDIV */
+#define _AGC_ANTDIV_GAINMODE_ALWAYS 0x00000002UL /**< Mode ALWAYS for AGC_ANTDIV */
+#define AGC_ANTDIV_GAINMODE_DEFAULT (_AGC_ANTDIV_GAINMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_ANTDIV */
+#define AGC_ANTDIV_GAINMODE_DISABLE (_AGC_ANTDIV_GAINMODE_DISABLE << 0) /**< Shifted mode DISABLE for AGC_ANTDIV */
+#define AGC_ANTDIV_GAINMODE_SINGLE_PACKET (_AGC_ANTDIV_GAINMODE_SINGLE_PACKET << 0) /**< Shifted mode SINGLE_PACKET for AGC_ANTDIV */
+#define AGC_ANTDIV_GAINMODE_ALWAYS (_AGC_ANTDIV_GAINMODE_ALWAYS << 0) /**< Shifted mode ALWAYS for AGC_ANTDIV */
+#define _AGC_ANTDIV_DEBOUNCECNTTHD_SHIFT 2 /**< Shift value for AGC_DEBOUNCECNTTHD */
+#define _AGC_ANTDIV_DEBOUNCECNTTHD_MASK 0x1FCUL /**< Bit mask for AGC_DEBOUNCECNTTHD */
+#define _AGC_ANTDIV_DEBOUNCECNTTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_ANTDIV */
+#define AGC_ANTDIV_DEBOUNCECNTTHD_DEFAULT (_AGC_ANTDIV_DEBOUNCECNTTHD_DEFAULT << 2) /**< Shifted mode DEFAULT for AGC_ANTDIV */
+#define _AGC_ANTDIV_DISRSSIANTDIVFIX_SHIFT 9 /**< Shift value for AGC_DISRSSIANTDIVFIX */
+#define _AGC_ANTDIV_DISRSSIANTDIVFIX_MASK 0x600UL /**< Bit mask for AGC_DISRSSIANTDIVFIX */
+#define _AGC_ANTDIV_DISRSSIANTDIVFIX_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_ANTDIV */
+#define AGC_ANTDIV_DISRSSIANTDIVFIX_DEFAULT (_AGC_ANTDIV_DISRSSIANTDIVFIX_DEFAULT << 9) /**< Shifted mode DEFAULT for AGC_ANTDIV */
+
+/* Bit fields for AGC DUALRFPKDTHD0 */
+#define _AGC_DUALRFPKDTHD0_RESETVALUE 0x000A0001UL /**< Default value for AGC_DUALRFPKDTHD0 */
+#define _AGC_DUALRFPKDTHD0_MASK 0x0FFF0FFFUL /**< Mask for AGC_DUALRFPKDTHD0 */
+#define _AGC_DUALRFPKDTHD0_RFPKDLOWTHD0_SHIFT 0 /**< Shift value for AGC_RFPKDLOWTHD0 */
+#define _AGC_DUALRFPKDTHD0_RFPKDLOWTHD0_MASK 0xFFFUL /**< Bit mask for AGC_RFPKDLOWTHD0 */
+#define _AGC_DUALRFPKDTHD0_RFPKDLOWTHD0_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_DUALRFPKDTHD0 */
+#define AGC_DUALRFPKDTHD0_RFPKDLOWTHD0_DEFAULT (_AGC_DUALRFPKDTHD0_RFPKDLOWTHD0_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_DUALRFPKDTHD0 */
+#define _AGC_DUALRFPKDTHD0_RFPKDLOWTHD1_SHIFT 16 /**< Shift value for AGC_RFPKDLOWTHD1 */
+#define _AGC_DUALRFPKDTHD0_RFPKDLOWTHD1_MASK 0xFFF0000UL /**< Bit mask for AGC_RFPKDLOWTHD1 */
+#define _AGC_DUALRFPKDTHD0_RFPKDLOWTHD1_DEFAULT 0x0000000AUL /**< Mode DEFAULT for AGC_DUALRFPKDTHD0 */
+#define AGC_DUALRFPKDTHD0_RFPKDLOWTHD1_DEFAULT (_AGC_DUALRFPKDTHD0_RFPKDLOWTHD1_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_DUALRFPKDTHD0 */
+
+/* Bit fields for AGC DUALRFPKDTHD1 */
+#define _AGC_DUALRFPKDTHD1_RESETVALUE 0x00280001UL /**< Default value for AGC_DUALRFPKDTHD1 */
+#define _AGC_DUALRFPKDTHD1_MASK 0x0FFF0FFFUL /**< Mask for AGC_DUALRFPKDTHD1 */
+#define _AGC_DUALRFPKDTHD1_RFPKDHITHD0_SHIFT 0 /**< Shift value for AGC_RFPKDHITHD0 */
+#define _AGC_DUALRFPKDTHD1_RFPKDHITHD0_MASK 0xFFFUL /**< Bit mask for AGC_RFPKDHITHD0 */
+#define _AGC_DUALRFPKDTHD1_RFPKDHITHD0_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_DUALRFPKDTHD1 */
+#define AGC_DUALRFPKDTHD1_RFPKDHITHD0_DEFAULT (_AGC_DUALRFPKDTHD1_RFPKDHITHD0_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_DUALRFPKDTHD1 */
+#define _AGC_DUALRFPKDTHD1_RFPKDHITHD1_SHIFT 16 /**< Shift value for AGC_RFPKDHITHD1 */
+#define _AGC_DUALRFPKDTHD1_RFPKDHITHD1_MASK 0xFFF0000UL /**< Bit mask for AGC_RFPKDHITHD1 */
+#define _AGC_DUALRFPKDTHD1_RFPKDHITHD1_DEFAULT 0x00000028UL /**< Mode DEFAULT for AGC_DUALRFPKDTHD1 */
+#define AGC_DUALRFPKDTHD1_RFPKDHITHD1_DEFAULT (_AGC_DUALRFPKDTHD1_RFPKDHITHD1_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_DUALRFPKDTHD1 */
+
+/* Bit fields for AGC SPARE */
+#define _AGC_SPARE_RESETVALUE 0x00000000UL /**< Default value for AGC_SPARE */
+#define _AGC_SPARE_MASK 0x000000FFUL /**< Mask for AGC_SPARE */
+#define _AGC_SPARE_SPAREREG_SHIFT 0 /**< Shift value for AGC_SPAREREG */
+#define _AGC_SPARE_SPAREREG_MASK 0xFFUL /**< Bit mask for AGC_SPAREREG */
+#define _AGC_SPARE_SPAREREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_SPARE */
+#define AGC_SPARE_SPAREREG_DEFAULT (_AGC_SPARE_SPAREREG_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_SPARE */
+
+/* Bit fields for AGC PNRFFILT0 */
+#define _AGC_PNRFFILT0_RESETVALUE 0x00200400UL /**< Default value for AGC_PNRFFILT0 */
+#define _AGC_PNRFFILT0_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFFILT0 */
+#define _AGC_PNRFFILT0_LNAMIXRFATT1_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT1 */
+#define _AGC_PNRFFILT0_LNAMIXRFATT1_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT1 */
+#define _AGC_PNRFFILT0_LNAMIXRFATT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_PNRFFILT0 */
+#define AGC_PNRFFILT0_LNAMIXRFATT1_DEFAULT (_AGC_PNRFFILT0_LNAMIXRFATT1_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFFILT0 */
+#define _AGC_PNRFFILT0_LNAMIXRFATT2_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT2 */
+#define _AGC_PNRFFILT0_LNAMIXRFATT2_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT2 */
+#define _AGC_PNRFFILT0_LNAMIXRFATT2_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_PNRFFILT0 */
+#define AGC_PNRFFILT0_LNAMIXRFATT2_DEFAULT (_AGC_PNRFFILT0_LNAMIXRFATT2_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFFILT0 */
+#define _AGC_PNRFFILT0_LNAMIXRFATT3_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT3 */
+#define _AGC_PNRFFILT0_LNAMIXRFATT3_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT3 */
+#define _AGC_PNRFFILT0_LNAMIXRFATT3_DEFAULT 0x00000002UL /**< Mode DEFAULT for AGC_PNRFFILT0 */
+#define AGC_PNRFFILT0_LNAMIXRFATT3_DEFAULT (_AGC_PNRFFILT0_LNAMIXRFATT3_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFFILT0 */
+
+/* Bit fields for AGC PNRFFILT1 */
+#define _AGC_PNRFFILT1_RESETVALUE 0x00801804UL /**< Default value for AGC_PNRFFILT1 */
+#define _AGC_PNRFFILT1_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFFILT1 */
+#define _AGC_PNRFFILT1_LNAMIXRFATT4_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT4 */
+#define _AGC_PNRFFILT1_LNAMIXRFATT4_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT4 */
+#define _AGC_PNRFFILT1_LNAMIXRFATT4_DEFAULT 0x00000004UL /**< Mode DEFAULT for AGC_PNRFFILT1 */
+#define AGC_PNRFFILT1_LNAMIXRFATT4_DEFAULT (_AGC_PNRFFILT1_LNAMIXRFATT4_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFFILT1 */
+#define _AGC_PNRFFILT1_LNAMIXRFATT5_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT5 */
+#define _AGC_PNRFFILT1_LNAMIXRFATT5_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT5 */
+#define _AGC_PNRFFILT1_LNAMIXRFATT5_DEFAULT 0x00000006UL /**< Mode DEFAULT for AGC_PNRFFILT1 */
+#define AGC_PNRFFILT1_LNAMIXRFATT5_DEFAULT (_AGC_PNRFFILT1_LNAMIXRFATT5_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFFILT1 */
+#define _AGC_PNRFFILT1_LNAMIXRFATT6_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT6 */
+#define _AGC_PNRFFILT1_LNAMIXRFATT6_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT6 */
+#define _AGC_PNRFFILT1_LNAMIXRFATT6_DEFAULT 0x00000008UL /**< Mode DEFAULT for AGC_PNRFFILT1 */
+#define AGC_PNRFFILT1_LNAMIXRFATT6_DEFAULT (_AGC_PNRFFILT1_LNAMIXRFATT6_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFFILT1 */
+
+/* Bit fields for AGC PNRFFILT2 */
+#define _AGC_PNRFFILT2_RESETVALUE 0x01203C0BUL /**< Default value for AGC_PNRFFILT2 */
+#define _AGC_PNRFFILT2_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFFILT2 */
+#define _AGC_PNRFFILT2_LNAMIXRFATT7_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT7 */
+#define _AGC_PNRFFILT2_LNAMIXRFATT7_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT7 */
+#define _AGC_PNRFFILT2_LNAMIXRFATT7_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_PNRFFILT2 */
+#define AGC_PNRFFILT2_LNAMIXRFATT7_DEFAULT (_AGC_PNRFFILT2_LNAMIXRFATT7_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFFILT2 */
+#define _AGC_PNRFFILT2_LNAMIXRFATT8_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT8 */
+#define _AGC_PNRFFILT2_LNAMIXRFATT8_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT8 */
+#define _AGC_PNRFFILT2_LNAMIXRFATT8_DEFAULT 0x0000000FUL /**< Mode DEFAULT for AGC_PNRFFILT2 */
+#define AGC_PNRFFILT2_LNAMIXRFATT8_DEFAULT (_AGC_PNRFFILT2_LNAMIXRFATT8_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFFILT2 */
+#define _AGC_PNRFFILT2_LNAMIXRFATT9_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT9 */
+#define _AGC_PNRFFILT2_LNAMIXRFATT9_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT9 */
+#define _AGC_PNRFFILT2_LNAMIXRFATT9_DEFAULT 0x00000012UL /**< Mode DEFAULT for AGC_PNRFFILT2 */
+#define AGC_PNRFFILT2_LNAMIXRFATT9_DEFAULT (_AGC_PNRFFILT2_LNAMIXRFATT9_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFFILT2 */
+
+/* Bit fields for AGC PNRFFILT3 */
+#define _AGC_PNRFFILT3_RESETVALUE 0x02107C18UL /**< Default value for AGC_PNRFFILT3 */
+#define _AGC_PNRFFILT3_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFFILT3 */
+#define _AGC_PNRFFILT3_LNAMIXRFATT10_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT10 */
+#define _AGC_PNRFFILT3_LNAMIXRFATT10_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT10 */
+#define _AGC_PNRFFILT3_LNAMIXRFATT10_DEFAULT 0x00000018UL /**< Mode DEFAULT for AGC_PNRFFILT3 */
+#define AGC_PNRFFILT3_LNAMIXRFATT10_DEFAULT (_AGC_PNRFFILT3_LNAMIXRFATT10_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFFILT3 */
+#define _AGC_PNRFFILT3_LNAMIXRFATT11_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT11 */
+#define _AGC_PNRFFILT3_LNAMIXRFATT11_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT11 */
+#define _AGC_PNRFFILT3_LNAMIXRFATT11_DEFAULT 0x0000001FUL /**< Mode DEFAULT for AGC_PNRFFILT3 */
+#define AGC_PNRFFILT3_LNAMIXRFATT11_DEFAULT (_AGC_PNRFFILT3_LNAMIXRFATT11_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFFILT3 */
+#define _AGC_PNRFFILT3_LNAMIXRFATT12_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT12 */
+#define _AGC_PNRFFILT3_LNAMIXRFATT12_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT12 */
+#define _AGC_PNRFFILT3_LNAMIXRFATT12_DEFAULT 0x00000021UL /**< Mode DEFAULT for AGC_PNRFFILT3 */
+#define AGC_PNRFFILT3_LNAMIXRFATT12_DEFAULT (_AGC_PNRFFILT3_LNAMIXRFATT12_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFFILT3 */
+
+/* Bit fields for AGC PNRFFILT4 */
+#define _AGC_PNRFFILT4_RESETVALUE 0x06E0FC2FUL /**< Default value for AGC_PNRFFILT4 */
+#define _AGC_PNRFFILT4_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFFILT4 */
+#define _AGC_PNRFFILT4_LNAMIXRFATT13_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT13 */
+#define _AGC_PNRFFILT4_LNAMIXRFATT13_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT13 */
+#define _AGC_PNRFFILT4_LNAMIXRFATT13_DEFAULT 0x0000002FUL /**< Mode DEFAULT for AGC_PNRFFILT4 */
+#define AGC_PNRFFILT4_LNAMIXRFATT13_DEFAULT (_AGC_PNRFFILT4_LNAMIXRFATT13_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFFILT4 */
+#define _AGC_PNRFFILT4_LNAMIXRFATT14_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT14 */
+#define _AGC_PNRFFILT4_LNAMIXRFATT14_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT14 */
+#define _AGC_PNRFFILT4_LNAMIXRFATT14_DEFAULT 0x0000003FUL /**< Mode DEFAULT for AGC_PNRFFILT4 */
+#define AGC_PNRFFILT4_LNAMIXRFATT14_DEFAULT (_AGC_PNRFFILT4_LNAMIXRFATT14_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFFILT4 */
+#define _AGC_PNRFFILT4_LNAMIXRFATT15_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT15 */
+#define _AGC_PNRFFILT4_LNAMIXRFATT15_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT15 */
+#define _AGC_PNRFFILT4_LNAMIXRFATT15_DEFAULT 0x0000006EUL /**< Mode DEFAULT for AGC_PNRFFILT4 */
+#define AGC_PNRFFILT4_LNAMIXRFATT15_DEFAULT (_AGC_PNRFFILT4_LNAMIXRFATT15_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFFILT4 */
+
+/* Bit fields for AGC PNRFFILT5 */
+#define _AGC_PNRFFILT5_RESETVALUE 0x0180480FUL /**< Default value for AGC_PNRFFILT5 */
+#define _AGC_PNRFFILT5_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFFILT5 */
+#define _AGC_PNRFFILT5_LNAMIXRFATT16_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT16 */
+#define _AGC_PNRFFILT5_LNAMIXRFATT16_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT16 */
+#define _AGC_PNRFFILT5_LNAMIXRFATT16_DEFAULT 0x0000000FUL /**< Mode DEFAULT for AGC_PNRFFILT5 */
+#define AGC_PNRFFILT5_LNAMIXRFATT16_DEFAULT (_AGC_PNRFFILT5_LNAMIXRFATT16_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFFILT5 */
+#define _AGC_PNRFFILT5_LNAMIXRFATT17_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT17 */
+#define _AGC_PNRFFILT5_LNAMIXRFATT17_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT17 */
+#define _AGC_PNRFFILT5_LNAMIXRFATT17_DEFAULT 0x00000012UL /**< Mode DEFAULT for AGC_PNRFFILT5 */
+#define AGC_PNRFFILT5_LNAMIXRFATT17_DEFAULT (_AGC_PNRFFILT5_LNAMIXRFATT17_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFFILT5 */
+#define _AGC_PNRFFILT5_LNAMIXRFATT18_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT18 */
+#define _AGC_PNRFFILT5_LNAMIXRFATT18_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT18 */
+#define _AGC_PNRFFILT5_LNAMIXRFATT18_DEFAULT 0x00000018UL /**< Mode DEFAULT for AGC_PNRFFILT5 */
+#define AGC_PNRFFILT5_LNAMIXRFATT18_DEFAULT (_AGC_PNRFFILT5_LNAMIXRFATT18_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFFILT5 */
+
+/* Bit fields for AGC PNRFFILT6 */
+#define _AGC_PNRFFILT6_RESETVALUE 0x02F0841FUL /**< Default value for AGC_PNRFFILT6 */
+#define _AGC_PNRFFILT6_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFFILT6 */
+#define _AGC_PNRFFILT6_LNAMIXRFATT19_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT19 */
+#define _AGC_PNRFFILT6_LNAMIXRFATT19_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT19 */
+#define _AGC_PNRFFILT6_LNAMIXRFATT19_DEFAULT 0x0000001FUL /**< Mode DEFAULT for AGC_PNRFFILT6 */
+#define AGC_PNRFFILT6_LNAMIXRFATT19_DEFAULT (_AGC_PNRFFILT6_LNAMIXRFATT19_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFFILT6 */
+#define _AGC_PNRFFILT6_LNAMIXRFATT20_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT20 */
+#define _AGC_PNRFFILT6_LNAMIXRFATT20_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT20 */
+#define _AGC_PNRFFILT6_LNAMIXRFATT20_DEFAULT 0x00000021UL /**< Mode DEFAULT for AGC_PNRFFILT6 */
+#define AGC_PNRFFILT6_LNAMIXRFATT20_DEFAULT (_AGC_PNRFFILT6_LNAMIXRFATT20_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFFILT6 */
+#define _AGC_PNRFFILT6_LNAMIXRFATT21_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT21 */
+#define _AGC_PNRFFILT6_LNAMIXRFATT21_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT21 */
+#define _AGC_PNRFFILT6_LNAMIXRFATT21_DEFAULT 0x0000002FUL /**< Mode DEFAULT for AGC_PNRFFILT6 */
+#define AGC_PNRFFILT6_LNAMIXRFATT21_DEFAULT (_AGC_PNRFFILT6_LNAMIXRFATT21_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFFILT6 */
+
+/* Bit fields for AGC PNRFFILT7 */
+#define _AGC_PNRFFILT7_RESETVALUE 0x07F1B83FUL /**< Default value for AGC_PNRFFILT7 */
+#define _AGC_PNRFFILT7_MASK 0x3FFFFFFFUL /**< Mask for AGC_PNRFFILT7 */
+#define _AGC_PNRFFILT7_LNAMIXRFATT22_SHIFT 0 /**< Shift value for AGC_LNAMIXRFATT22 */
+#define _AGC_PNRFFILT7_LNAMIXRFATT22_MASK 0x3FFUL /**< Bit mask for AGC_LNAMIXRFATT22 */
+#define _AGC_PNRFFILT7_LNAMIXRFATT22_DEFAULT 0x0000003FUL /**< Mode DEFAULT for AGC_PNRFFILT7 */
+#define AGC_PNRFFILT7_LNAMIXRFATT22_DEFAULT (_AGC_PNRFFILT7_LNAMIXRFATT22_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_PNRFFILT7 */
+#define _AGC_PNRFFILT7_LNAMIXRFATT23_SHIFT 10 /**< Shift value for AGC_LNAMIXRFATT23 */
+#define _AGC_PNRFFILT7_LNAMIXRFATT23_MASK 0xFFC00UL /**< Bit mask for AGC_LNAMIXRFATT23 */
+#define _AGC_PNRFFILT7_LNAMIXRFATT23_DEFAULT 0x0000006EUL /**< Mode DEFAULT for AGC_PNRFFILT7 */
+#define AGC_PNRFFILT7_LNAMIXRFATT23_DEFAULT (_AGC_PNRFFILT7_LNAMIXRFATT23_DEFAULT << 10) /**< Shifted mode DEFAULT for AGC_PNRFFILT7 */
+#define _AGC_PNRFFILT7_LNAMIXRFATT24_SHIFT 20 /**< Shift value for AGC_LNAMIXRFATT24 */
+#define _AGC_PNRFFILT7_LNAMIXRFATT24_MASK 0x3FF00000UL /**< Bit mask for AGC_LNAMIXRFATT24 */
+#define _AGC_PNRFFILT7_LNAMIXRFATT24_DEFAULT 0x0000007FUL /**< Mode DEFAULT for AGC_PNRFFILT7 */
+#define AGC_PNRFFILT7_LNAMIXRFATT24_DEFAULT (_AGC_PNRFFILT7_LNAMIXRFATT24_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_PNRFFILT7 */
+
+/* Bit fields for AGC FENOTCHATT0 */
+#define _AGC_FENOTCHATT0_RESETVALUE 0x00000000UL /**< Default value for AGC_FENOTCHATT0 */
+#define _AGC_FENOTCHATT0_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHATT0 */
+#define _AGC_FENOTCHATT0_FENOTCHATTNSEL1_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL1 */
+#define _AGC_FENOTCHATT0_FENOTCHATTNSEL1_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL1 */
+#define _AGC_FENOTCHATT0_FENOTCHATTNSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT0 */
+#define AGC_FENOTCHATT0_FENOTCHATTNSEL1_DEFAULT (_AGC_FENOTCHATT0_FENOTCHATTNSEL1_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHATT0 */
+#define _AGC_FENOTCHATT0_FENOTCHCAPCRSE1_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE1 */
+#define _AGC_FENOTCHATT0_FENOTCHCAPCRSE1_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE1 */
+#define _AGC_FENOTCHATT0_FENOTCHCAPCRSE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT0 */
+#define AGC_FENOTCHATT0_FENOTCHCAPCRSE1_DEFAULT (_AGC_FENOTCHATT0_FENOTCHCAPCRSE1_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHATT0 */
+#define _AGC_FENOTCHATT0_FENOTCHCAPFINE1_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE1 */
+#define _AGC_FENOTCHATT0_FENOTCHCAPFINE1_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE1 */
+#define _AGC_FENOTCHATT0_FENOTCHCAPFINE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT0 */
+#define AGC_FENOTCHATT0_FENOTCHCAPFINE1_DEFAULT (_AGC_FENOTCHATT0_FENOTCHCAPFINE1_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHATT0 */
+#define AGC_FENOTCHATT0_FENOTCHRATTNEN1 (0x1UL << 12) /**< FE notch rattn enable for index 1 */
+#define _AGC_FENOTCHATT0_FENOTCHRATTNEN1_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN1 */
+#define _AGC_FENOTCHATT0_FENOTCHRATTNEN1_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN1 */
+#define _AGC_FENOTCHATT0_FENOTCHRATTNEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT0 */
+#define AGC_FENOTCHATT0_FENOTCHRATTNEN1_DEFAULT (_AGC_FENOTCHATT0_FENOTCHRATTNEN1_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHATT0 */
+#define AGC_FENOTCHATT0_FENOTCHEN1 (0x1UL << 13) /**< FE notch enable for index 1 */
+#define _AGC_FENOTCHATT0_FENOTCHEN1_SHIFT 13 /**< Shift value for AGC_FENOTCHEN1 */
+#define _AGC_FENOTCHATT0_FENOTCHEN1_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN1 */
+#define _AGC_FENOTCHATT0_FENOTCHEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT0 */
+#define AGC_FENOTCHATT0_FENOTCHEN1_DEFAULT (_AGC_FENOTCHATT0_FENOTCHEN1_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHATT0 */
+#define _AGC_FENOTCHATT0_FENOTCHATTNSEL2_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL2 */
+#define _AGC_FENOTCHATT0_FENOTCHATTNSEL2_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL2 */
+#define _AGC_FENOTCHATT0_FENOTCHATTNSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT0 */
+#define AGC_FENOTCHATT0_FENOTCHATTNSEL2_DEFAULT (_AGC_FENOTCHATT0_FENOTCHATTNSEL2_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHATT0 */
+#define _AGC_FENOTCHATT0_FENOTCHCAPCRSE2_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE2 */
+#define _AGC_FENOTCHATT0_FENOTCHCAPCRSE2_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE2 */
+#define _AGC_FENOTCHATT0_FENOTCHCAPCRSE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT0 */
+#define AGC_FENOTCHATT0_FENOTCHCAPCRSE2_DEFAULT (_AGC_FENOTCHATT0_FENOTCHCAPCRSE2_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHATT0 */
+#define _AGC_FENOTCHATT0_FENOTCHCAPFINE2_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE2 */
+#define _AGC_FENOTCHATT0_FENOTCHCAPFINE2_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE2 */
+#define _AGC_FENOTCHATT0_FENOTCHCAPFINE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT0 */
+#define AGC_FENOTCHATT0_FENOTCHCAPFINE2_DEFAULT (_AGC_FENOTCHATT0_FENOTCHCAPFINE2_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHATT0 */
+#define AGC_FENOTCHATT0_FENOTCHRATTNEN2 (0x1UL << 28) /**< FE notch rattn enable for index 2 */
+#define _AGC_FENOTCHATT0_FENOTCHRATTNEN2_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN2 */
+#define _AGC_FENOTCHATT0_FENOTCHRATTNEN2_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN2 */
+#define _AGC_FENOTCHATT0_FENOTCHRATTNEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT0 */
+#define AGC_FENOTCHATT0_FENOTCHRATTNEN2_DEFAULT (_AGC_FENOTCHATT0_FENOTCHRATTNEN2_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHATT0 */
+#define AGC_FENOTCHATT0_FENOTCHEN2 (0x1UL << 29) /**< FE notch enable for index 2 */
+#define _AGC_FENOTCHATT0_FENOTCHEN2_SHIFT 29 /**< Shift value for AGC_FENOTCHEN2 */
+#define _AGC_FENOTCHATT0_FENOTCHEN2_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN2 */
+#define _AGC_FENOTCHATT0_FENOTCHEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT0 */
+#define AGC_FENOTCHATT0_FENOTCHEN2_DEFAULT (_AGC_FENOTCHATT0_FENOTCHEN2_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHATT0 */
+
+/* Bit fields for AGC FENOTCHATT1 */
+#define _AGC_FENOTCHATT1_RESETVALUE 0x00000000UL /**< Default value for AGC_FENOTCHATT1 */
+#define _AGC_FENOTCHATT1_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHATT1 */
+#define _AGC_FENOTCHATT1_FENOTCHATTNSEL3_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL3 */
+#define _AGC_FENOTCHATT1_FENOTCHATTNSEL3_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL3 */
+#define _AGC_FENOTCHATT1_FENOTCHATTNSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT1 */
+#define AGC_FENOTCHATT1_FENOTCHATTNSEL3_DEFAULT (_AGC_FENOTCHATT1_FENOTCHATTNSEL3_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHATT1 */
+#define _AGC_FENOTCHATT1_FENOTCHCAPCRSE3_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE3 */
+#define _AGC_FENOTCHATT1_FENOTCHCAPCRSE3_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE3 */
+#define _AGC_FENOTCHATT1_FENOTCHCAPCRSE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT1 */
+#define AGC_FENOTCHATT1_FENOTCHCAPCRSE3_DEFAULT (_AGC_FENOTCHATT1_FENOTCHCAPCRSE3_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHATT1 */
+#define _AGC_FENOTCHATT1_FENOTCHCAPFINE3_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE3 */
+#define _AGC_FENOTCHATT1_FENOTCHCAPFINE3_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE3 */
+#define _AGC_FENOTCHATT1_FENOTCHCAPFINE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT1 */
+#define AGC_FENOTCHATT1_FENOTCHCAPFINE3_DEFAULT (_AGC_FENOTCHATT1_FENOTCHCAPFINE3_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHATT1 */
+#define AGC_FENOTCHATT1_FENOTCHRATTNEN3 (0x1UL << 12) /**< FE notch rattn enable for index 3 */
+#define _AGC_FENOTCHATT1_FENOTCHRATTNEN3_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN3 */
+#define _AGC_FENOTCHATT1_FENOTCHRATTNEN3_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN3 */
+#define _AGC_FENOTCHATT1_FENOTCHRATTNEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT1 */
+#define AGC_FENOTCHATT1_FENOTCHRATTNEN3_DEFAULT (_AGC_FENOTCHATT1_FENOTCHRATTNEN3_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHATT1 */
+#define AGC_FENOTCHATT1_FENOTCHEN3 (0x1UL << 13) /**< FE notch enable for index 3 */
+#define _AGC_FENOTCHATT1_FENOTCHEN3_SHIFT 13 /**< Shift value for AGC_FENOTCHEN3 */
+#define _AGC_FENOTCHATT1_FENOTCHEN3_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN3 */
+#define _AGC_FENOTCHATT1_FENOTCHEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT1 */
+#define AGC_FENOTCHATT1_FENOTCHEN3_DEFAULT (_AGC_FENOTCHATT1_FENOTCHEN3_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHATT1 */
+#define _AGC_FENOTCHATT1_FENOTCHATTNSEL4_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL4 */
+#define _AGC_FENOTCHATT1_FENOTCHATTNSEL4_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL4 */
+#define _AGC_FENOTCHATT1_FENOTCHATTNSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT1 */
+#define AGC_FENOTCHATT1_FENOTCHATTNSEL4_DEFAULT (_AGC_FENOTCHATT1_FENOTCHATTNSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHATT1 */
+#define _AGC_FENOTCHATT1_FENOTCHCAPCRSE4_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE4 */
+#define _AGC_FENOTCHATT1_FENOTCHCAPCRSE4_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE4 */
+#define _AGC_FENOTCHATT1_FENOTCHCAPCRSE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT1 */
+#define AGC_FENOTCHATT1_FENOTCHCAPCRSE4_DEFAULT (_AGC_FENOTCHATT1_FENOTCHCAPCRSE4_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHATT1 */
+#define _AGC_FENOTCHATT1_FENOTCHCAPFINE4_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE4 */
+#define _AGC_FENOTCHATT1_FENOTCHCAPFINE4_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE4 */
+#define _AGC_FENOTCHATT1_FENOTCHCAPFINE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT1 */
+#define AGC_FENOTCHATT1_FENOTCHCAPFINE4_DEFAULT (_AGC_FENOTCHATT1_FENOTCHCAPFINE4_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHATT1 */
+#define AGC_FENOTCHATT1_FENOTCHRATTNEN4 (0x1UL << 28) /**< FE notch rattn enable for index 4 */
+#define _AGC_FENOTCHATT1_FENOTCHRATTNEN4_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN4 */
+#define _AGC_FENOTCHATT1_FENOTCHRATTNEN4_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN4 */
+#define _AGC_FENOTCHATT1_FENOTCHRATTNEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT1 */
+#define AGC_FENOTCHATT1_FENOTCHRATTNEN4_DEFAULT (_AGC_FENOTCHATT1_FENOTCHRATTNEN4_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHATT1 */
+#define AGC_FENOTCHATT1_FENOTCHEN4 (0x1UL << 29) /**< FE notch enable for index 4 */
+#define _AGC_FENOTCHATT1_FENOTCHEN4_SHIFT 29 /**< Shift value for AGC_FENOTCHEN4 */
+#define _AGC_FENOTCHATT1_FENOTCHEN4_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN4 */
+#define _AGC_FENOTCHATT1_FENOTCHEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT1 */
+#define AGC_FENOTCHATT1_FENOTCHEN4_DEFAULT (_AGC_FENOTCHATT1_FENOTCHEN4_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHATT1 */
+
+/* Bit fields for AGC FENOTCHATT2 */
+#define _AGC_FENOTCHATT2_RESETVALUE 0x00000000UL /**< Default value for AGC_FENOTCHATT2 */
+#define _AGC_FENOTCHATT2_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHATT2 */
+#define _AGC_FENOTCHATT2_FENOTCHATTNSEL5_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL5 */
+#define _AGC_FENOTCHATT2_FENOTCHATTNSEL5_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL5 */
+#define _AGC_FENOTCHATT2_FENOTCHATTNSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT2 */
+#define AGC_FENOTCHATT2_FENOTCHATTNSEL5_DEFAULT (_AGC_FENOTCHATT2_FENOTCHATTNSEL5_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHATT2 */
+#define _AGC_FENOTCHATT2_FENOTCHCAPCRSE5_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE5 */
+#define _AGC_FENOTCHATT2_FENOTCHCAPCRSE5_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE5 */
+#define _AGC_FENOTCHATT2_FENOTCHCAPCRSE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT2 */
+#define AGC_FENOTCHATT2_FENOTCHCAPCRSE5_DEFAULT (_AGC_FENOTCHATT2_FENOTCHCAPCRSE5_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHATT2 */
+#define _AGC_FENOTCHATT2_FENOTCHCAPFINE5_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE5 */
+#define _AGC_FENOTCHATT2_FENOTCHCAPFINE5_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE5 */
+#define _AGC_FENOTCHATT2_FENOTCHCAPFINE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT2 */
+#define AGC_FENOTCHATT2_FENOTCHCAPFINE5_DEFAULT (_AGC_FENOTCHATT2_FENOTCHCAPFINE5_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHATT2 */
+#define AGC_FENOTCHATT2_FENOTCHRATTNEN5 (0x1UL << 12) /**< FE notch rattn enable for index 5 */
+#define _AGC_FENOTCHATT2_FENOTCHRATTNEN5_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN5 */
+#define _AGC_FENOTCHATT2_FENOTCHRATTNEN5_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN5 */
+#define _AGC_FENOTCHATT2_FENOTCHRATTNEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT2 */
+#define AGC_FENOTCHATT2_FENOTCHRATTNEN5_DEFAULT (_AGC_FENOTCHATT2_FENOTCHRATTNEN5_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHATT2 */
+#define AGC_FENOTCHATT2_FENOTCHEN5 (0x1UL << 13) /**< FE notch enable for index 5 */
+#define _AGC_FENOTCHATT2_FENOTCHEN5_SHIFT 13 /**< Shift value for AGC_FENOTCHEN5 */
+#define _AGC_FENOTCHATT2_FENOTCHEN5_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN5 */
+#define _AGC_FENOTCHATT2_FENOTCHEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT2 */
+#define AGC_FENOTCHATT2_FENOTCHEN5_DEFAULT (_AGC_FENOTCHATT2_FENOTCHEN5_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHATT2 */
+#define _AGC_FENOTCHATT2_FENOTCHATTNSEL6_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL6 */
+#define _AGC_FENOTCHATT2_FENOTCHATTNSEL6_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL6 */
+#define _AGC_FENOTCHATT2_FENOTCHATTNSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT2 */
+#define AGC_FENOTCHATT2_FENOTCHATTNSEL6_DEFAULT (_AGC_FENOTCHATT2_FENOTCHATTNSEL6_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHATT2 */
+#define _AGC_FENOTCHATT2_FENOTCHCAPCRSE6_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE6 */
+#define _AGC_FENOTCHATT2_FENOTCHCAPCRSE6_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE6 */
+#define _AGC_FENOTCHATT2_FENOTCHCAPCRSE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT2 */
+#define AGC_FENOTCHATT2_FENOTCHCAPCRSE6_DEFAULT (_AGC_FENOTCHATT2_FENOTCHCAPCRSE6_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHATT2 */
+#define _AGC_FENOTCHATT2_FENOTCHCAPFINE6_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE6 */
+#define _AGC_FENOTCHATT2_FENOTCHCAPFINE6_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE6 */
+#define _AGC_FENOTCHATT2_FENOTCHCAPFINE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT2 */
+#define AGC_FENOTCHATT2_FENOTCHCAPFINE6_DEFAULT (_AGC_FENOTCHATT2_FENOTCHCAPFINE6_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHATT2 */
+#define AGC_FENOTCHATT2_FENOTCHRATTNEN6 (0x1UL << 28) /**< FE notch rattn enable for index 6 */
+#define _AGC_FENOTCHATT2_FENOTCHRATTNEN6_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN6 */
+#define _AGC_FENOTCHATT2_FENOTCHRATTNEN6_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN6 */
+#define _AGC_FENOTCHATT2_FENOTCHRATTNEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT2 */
+#define AGC_FENOTCHATT2_FENOTCHRATTNEN6_DEFAULT (_AGC_FENOTCHATT2_FENOTCHRATTNEN6_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHATT2 */
+#define AGC_FENOTCHATT2_FENOTCHEN6 (0x1UL << 29) /**< FE notch enable for index 6 */
+#define _AGC_FENOTCHATT2_FENOTCHEN6_SHIFT 29 /**< Shift value for AGC_FENOTCHEN6 */
+#define _AGC_FENOTCHATT2_FENOTCHEN6_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN6 */
+#define _AGC_FENOTCHATT2_FENOTCHEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT2 */
+#define AGC_FENOTCHATT2_FENOTCHEN6_DEFAULT (_AGC_FENOTCHATT2_FENOTCHEN6_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHATT2 */
+
+/* Bit fields for AGC FENOTCHATT3 */
+#define _AGC_FENOTCHATT3_RESETVALUE 0x00000000UL /**< Default value for AGC_FENOTCHATT3 */
+#define _AGC_FENOTCHATT3_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHATT3 */
+#define _AGC_FENOTCHATT3_FENOTCHATTNSEL7_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL7 */
+#define _AGC_FENOTCHATT3_FENOTCHATTNSEL7_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL7 */
+#define _AGC_FENOTCHATT3_FENOTCHATTNSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT3 */
+#define AGC_FENOTCHATT3_FENOTCHATTNSEL7_DEFAULT (_AGC_FENOTCHATT3_FENOTCHATTNSEL7_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHATT3 */
+#define _AGC_FENOTCHATT3_FENOTCHCAPCRSE7_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE7 */
+#define _AGC_FENOTCHATT3_FENOTCHCAPCRSE7_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE7 */
+#define _AGC_FENOTCHATT3_FENOTCHCAPCRSE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT3 */
+#define AGC_FENOTCHATT3_FENOTCHCAPCRSE7_DEFAULT (_AGC_FENOTCHATT3_FENOTCHCAPCRSE7_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHATT3 */
+#define _AGC_FENOTCHATT3_FENOTCHCAPFINE7_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE7 */
+#define _AGC_FENOTCHATT3_FENOTCHCAPFINE7_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE7 */
+#define _AGC_FENOTCHATT3_FENOTCHCAPFINE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT3 */
+#define AGC_FENOTCHATT3_FENOTCHCAPFINE7_DEFAULT (_AGC_FENOTCHATT3_FENOTCHCAPFINE7_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHATT3 */
+#define AGC_FENOTCHATT3_FENOTCHRATTNEN7 (0x1UL << 12) /**< FE notch rattn enable for index 7 */
+#define _AGC_FENOTCHATT3_FENOTCHRATTNEN7_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN7 */
+#define _AGC_FENOTCHATT3_FENOTCHRATTNEN7_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN7 */
+#define _AGC_FENOTCHATT3_FENOTCHRATTNEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT3 */
+#define AGC_FENOTCHATT3_FENOTCHRATTNEN7_DEFAULT (_AGC_FENOTCHATT3_FENOTCHRATTNEN7_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHATT3 */
+#define AGC_FENOTCHATT3_FENOTCHEN7 (0x1UL << 13) /**< FE notch enable for index 7 */
+#define _AGC_FENOTCHATT3_FENOTCHEN7_SHIFT 13 /**< Shift value for AGC_FENOTCHEN7 */
+#define _AGC_FENOTCHATT3_FENOTCHEN7_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN7 */
+#define _AGC_FENOTCHATT3_FENOTCHEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT3 */
+#define AGC_FENOTCHATT3_FENOTCHEN7_DEFAULT (_AGC_FENOTCHATT3_FENOTCHEN7_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHATT3 */
+#define _AGC_FENOTCHATT3_FENOTCHATTNSEL8_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL8 */
+#define _AGC_FENOTCHATT3_FENOTCHATTNSEL8_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL8 */
+#define _AGC_FENOTCHATT3_FENOTCHATTNSEL8_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT3 */
+#define AGC_FENOTCHATT3_FENOTCHATTNSEL8_DEFAULT (_AGC_FENOTCHATT3_FENOTCHATTNSEL8_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHATT3 */
+#define _AGC_FENOTCHATT3_FENOTCHCAPCRSE8_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE8 */
+#define _AGC_FENOTCHATT3_FENOTCHCAPCRSE8_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE8 */
+#define _AGC_FENOTCHATT3_FENOTCHCAPCRSE8_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT3 */
+#define AGC_FENOTCHATT3_FENOTCHCAPCRSE8_DEFAULT (_AGC_FENOTCHATT3_FENOTCHCAPCRSE8_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHATT3 */
+#define _AGC_FENOTCHATT3_FENOTCHCAPFINE8_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE8 */
+#define _AGC_FENOTCHATT3_FENOTCHCAPFINE8_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE8 */
+#define _AGC_FENOTCHATT3_FENOTCHCAPFINE8_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT3 */
+#define AGC_FENOTCHATT3_FENOTCHCAPFINE8_DEFAULT (_AGC_FENOTCHATT3_FENOTCHCAPFINE8_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHATT3 */
+#define AGC_FENOTCHATT3_FENOTCHRATTNEN8 (0x1UL << 28) /**< FE notch rattn enable for index 8 */
+#define _AGC_FENOTCHATT3_FENOTCHRATTNEN8_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN8 */
+#define _AGC_FENOTCHATT3_FENOTCHRATTNEN8_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN8 */
+#define _AGC_FENOTCHATT3_FENOTCHRATTNEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT3 */
+#define AGC_FENOTCHATT3_FENOTCHRATTNEN8_DEFAULT (_AGC_FENOTCHATT3_FENOTCHRATTNEN8_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHATT3 */
+#define AGC_FENOTCHATT3_FENOTCHEN8 (0x1UL << 29) /**< FE notch enable for index 8 */
+#define _AGC_FENOTCHATT3_FENOTCHEN8_SHIFT 29 /**< Shift value for AGC_FENOTCHEN8 */
+#define _AGC_FENOTCHATT3_FENOTCHEN8_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN8 */
+#define _AGC_FENOTCHATT3_FENOTCHEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT3 */
+#define AGC_FENOTCHATT3_FENOTCHEN8_DEFAULT (_AGC_FENOTCHATT3_FENOTCHEN8_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHATT3 */
+
+/* Bit fields for AGC FENOTCHATT4 */
+#define _AGC_FENOTCHATT4_RESETVALUE 0x00000000UL /**< Default value for AGC_FENOTCHATT4 */
+#define _AGC_FENOTCHATT4_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHATT4 */
+#define _AGC_FENOTCHATT4_FENOTCHATTNSEL9_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL9 */
+#define _AGC_FENOTCHATT4_FENOTCHATTNSEL9_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL9 */
+#define _AGC_FENOTCHATT4_FENOTCHATTNSEL9_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT4 */
+#define AGC_FENOTCHATT4_FENOTCHATTNSEL9_DEFAULT (_AGC_FENOTCHATT4_FENOTCHATTNSEL9_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHATT4 */
+#define _AGC_FENOTCHATT4_FENOTCHCAPCRSE9_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE9 */
+#define _AGC_FENOTCHATT4_FENOTCHCAPCRSE9_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE9 */
+#define _AGC_FENOTCHATT4_FENOTCHCAPCRSE9_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT4 */
+#define AGC_FENOTCHATT4_FENOTCHCAPCRSE9_DEFAULT (_AGC_FENOTCHATT4_FENOTCHCAPCRSE9_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHATT4 */
+#define _AGC_FENOTCHATT4_FENOTCHCAPFINE9_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE9 */
+#define _AGC_FENOTCHATT4_FENOTCHCAPFINE9_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE9 */
+#define _AGC_FENOTCHATT4_FENOTCHCAPFINE9_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT4 */
+#define AGC_FENOTCHATT4_FENOTCHCAPFINE9_DEFAULT (_AGC_FENOTCHATT4_FENOTCHCAPFINE9_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHATT4 */
+#define AGC_FENOTCHATT4_FENOTCHRATTNEN9 (0x1UL << 12) /**< FE notch rattn enable for index 9 */
+#define _AGC_FENOTCHATT4_FENOTCHRATTNEN9_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN9 */
+#define _AGC_FENOTCHATT4_FENOTCHRATTNEN9_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN9 */
+#define _AGC_FENOTCHATT4_FENOTCHRATTNEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT4 */
+#define AGC_FENOTCHATT4_FENOTCHRATTNEN9_DEFAULT (_AGC_FENOTCHATT4_FENOTCHRATTNEN9_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHATT4 */
+#define AGC_FENOTCHATT4_FENOTCHEN9 (0x1UL << 13) /**< FE notch enable for index 9 */
+#define _AGC_FENOTCHATT4_FENOTCHEN9_SHIFT 13 /**< Shift value for AGC_FENOTCHEN9 */
+#define _AGC_FENOTCHATT4_FENOTCHEN9_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN9 */
+#define _AGC_FENOTCHATT4_FENOTCHEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT4 */
+#define AGC_FENOTCHATT4_FENOTCHEN9_DEFAULT (_AGC_FENOTCHATT4_FENOTCHEN9_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHATT4 */
+#define _AGC_FENOTCHATT4_FENOTCHATTNSEL10_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL10 */
+#define _AGC_FENOTCHATT4_FENOTCHATTNSEL10_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL10 */
+#define _AGC_FENOTCHATT4_FENOTCHATTNSEL10_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT4 */
+#define AGC_FENOTCHATT4_FENOTCHATTNSEL10_DEFAULT (_AGC_FENOTCHATT4_FENOTCHATTNSEL10_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHATT4 */
+#define _AGC_FENOTCHATT4_FENOTCHCAPCRSE10_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE10 */
+#define _AGC_FENOTCHATT4_FENOTCHCAPCRSE10_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE10 */
+#define _AGC_FENOTCHATT4_FENOTCHCAPCRSE10_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT4 */
+#define AGC_FENOTCHATT4_FENOTCHCAPCRSE10_DEFAULT (_AGC_FENOTCHATT4_FENOTCHCAPCRSE10_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHATT4 */
+#define _AGC_FENOTCHATT4_FENOTCHCAPFINE10_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE10 */
+#define _AGC_FENOTCHATT4_FENOTCHCAPFINE10_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE10 */
+#define _AGC_FENOTCHATT4_FENOTCHCAPFINE10_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT4 */
+#define AGC_FENOTCHATT4_FENOTCHCAPFINE10_DEFAULT (_AGC_FENOTCHATT4_FENOTCHCAPFINE10_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHATT4 */
+#define AGC_FENOTCHATT4_FENOTCHRATTNEN10 (0x1UL << 28) /**< FE notch rattn enable for index 10 */
+#define _AGC_FENOTCHATT4_FENOTCHRATTNEN10_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN10 */
+#define _AGC_FENOTCHATT4_FENOTCHRATTNEN10_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN10 */
+#define _AGC_FENOTCHATT4_FENOTCHRATTNEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT4 */
+#define AGC_FENOTCHATT4_FENOTCHRATTNEN10_DEFAULT (_AGC_FENOTCHATT4_FENOTCHRATTNEN10_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHATT4 */
+#define AGC_FENOTCHATT4_FENOTCHEN10 (0x1UL << 29) /**< FE notch enable for index 10 */
+#define _AGC_FENOTCHATT4_FENOTCHEN10_SHIFT 29 /**< Shift value for AGC_FENOTCHEN10 */
+#define _AGC_FENOTCHATT4_FENOTCHEN10_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN10 */
+#define _AGC_FENOTCHATT4_FENOTCHEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT4 */
+#define AGC_FENOTCHATT4_FENOTCHEN10_DEFAULT (_AGC_FENOTCHATT4_FENOTCHEN10_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHATT4 */
+
+/* Bit fields for AGC FENOTCHATT5 */
+#define _AGC_FENOTCHATT5_RESETVALUE 0x00000000UL /**< Default value for AGC_FENOTCHATT5 */
+#define _AGC_FENOTCHATT5_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHATT5 */
+#define _AGC_FENOTCHATT5_FENOTCHATTNSEL11_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL11 */
+#define _AGC_FENOTCHATT5_FENOTCHATTNSEL11_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL11 */
+#define _AGC_FENOTCHATT5_FENOTCHATTNSEL11_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT5 */
+#define AGC_FENOTCHATT5_FENOTCHATTNSEL11_DEFAULT (_AGC_FENOTCHATT5_FENOTCHATTNSEL11_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHATT5 */
+#define _AGC_FENOTCHATT5_FENOTCHCAPCRSE11_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE11 */
+#define _AGC_FENOTCHATT5_FENOTCHCAPCRSE11_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE11 */
+#define _AGC_FENOTCHATT5_FENOTCHCAPCRSE11_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT5 */
+#define AGC_FENOTCHATT5_FENOTCHCAPCRSE11_DEFAULT (_AGC_FENOTCHATT5_FENOTCHCAPCRSE11_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHATT5 */
+#define _AGC_FENOTCHATT5_FENOTCHCAPFINE11_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE11 */
+#define _AGC_FENOTCHATT5_FENOTCHCAPFINE11_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE11 */
+#define _AGC_FENOTCHATT5_FENOTCHCAPFINE11_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT5 */
+#define AGC_FENOTCHATT5_FENOTCHCAPFINE11_DEFAULT (_AGC_FENOTCHATT5_FENOTCHCAPFINE11_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHATT5 */
+#define AGC_FENOTCHATT5_FENOTCHRATTNEN11 (0x1UL << 12) /**< FE notch rattn enable for index 11 */
+#define _AGC_FENOTCHATT5_FENOTCHRATTNEN11_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN11 */
+#define _AGC_FENOTCHATT5_FENOTCHRATTNEN11_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN11 */
+#define _AGC_FENOTCHATT5_FENOTCHRATTNEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT5 */
+#define AGC_FENOTCHATT5_FENOTCHRATTNEN11_DEFAULT (_AGC_FENOTCHATT5_FENOTCHRATTNEN11_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHATT5 */
+#define AGC_FENOTCHATT5_FENOTCHEN11 (0x1UL << 13) /**< FE notch enable for index 11 */
+#define _AGC_FENOTCHATT5_FENOTCHEN11_SHIFT 13 /**< Shift value for AGC_FENOTCHEN11 */
+#define _AGC_FENOTCHATT5_FENOTCHEN11_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN11 */
+#define _AGC_FENOTCHATT5_FENOTCHEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT5 */
+#define AGC_FENOTCHATT5_FENOTCHEN11_DEFAULT (_AGC_FENOTCHATT5_FENOTCHEN11_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHATT5 */
+#define _AGC_FENOTCHATT5_FENOTCHATTNSEL12_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL12 */
+#define _AGC_FENOTCHATT5_FENOTCHATTNSEL12_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL12 */
+#define _AGC_FENOTCHATT5_FENOTCHATTNSEL12_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT5 */
+#define AGC_FENOTCHATT5_FENOTCHATTNSEL12_DEFAULT (_AGC_FENOTCHATT5_FENOTCHATTNSEL12_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHATT5 */
+#define _AGC_FENOTCHATT5_FENOTCHCAPCRSE12_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE12 */
+#define _AGC_FENOTCHATT5_FENOTCHCAPCRSE12_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE12 */
+#define _AGC_FENOTCHATT5_FENOTCHCAPCRSE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT5 */
+#define AGC_FENOTCHATT5_FENOTCHCAPCRSE12_DEFAULT (_AGC_FENOTCHATT5_FENOTCHCAPCRSE12_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHATT5 */
+#define _AGC_FENOTCHATT5_FENOTCHCAPFINE12_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE12 */
+#define _AGC_FENOTCHATT5_FENOTCHCAPFINE12_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE12 */
+#define _AGC_FENOTCHATT5_FENOTCHCAPFINE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT5 */
+#define AGC_FENOTCHATT5_FENOTCHCAPFINE12_DEFAULT (_AGC_FENOTCHATT5_FENOTCHCAPFINE12_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHATT5 */
+#define AGC_FENOTCHATT5_FENOTCHRATTNEN12 (0x1UL << 28) /**< FE notch rattn enable for index 12 */
+#define _AGC_FENOTCHATT5_FENOTCHRATTNEN12_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN12 */
+#define _AGC_FENOTCHATT5_FENOTCHRATTNEN12_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN12 */
+#define _AGC_FENOTCHATT5_FENOTCHRATTNEN12_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT5 */
+#define AGC_FENOTCHATT5_FENOTCHRATTNEN12_DEFAULT (_AGC_FENOTCHATT5_FENOTCHRATTNEN12_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHATT5 */
+#define AGC_FENOTCHATT5_FENOTCHEN12 (0x1UL << 29) /**< FE notch enable for index 12 */
+#define _AGC_FENOTCHATT5_FENOTCHEN12_SHIFT 29 /**< Shift value for AGC_FENOTCHEN12 */
+#define _AGC_FENOTCHATT5_FENOTCHEN12_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN12 */
+#define _AGC_FENOTCHATT5_FENOTCHEN12_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT5 */
+#define AGC_FENOTCHATT5_FENOTCHEN12_DEFAULT (_AGC_FENOTCHATT5_FENOTCHEN12_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHATT5 */
+
+/* Bit fields for AGC FENOTCHATT6 */
+#define _AGC_FENOTCHATT6_RESETVALUE 0x00000000UL /**< Default value for AGC_FENOTCHATT6 */
+#define _AGC_FENOTCHATT6_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHATT6 */
+#define _AGC_FENOTCHATT6_FENOTCHATTNSEL13_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL13 */
+#define _AGC_FENOTCHATT6_FENOTCHATTNSEL13_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL13 */
+#define _AGC_FENOTCHATT6_FENOTCHATTNSEL13_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT6 */
+#define AGC_FENOTCHATT6_FENOTCHATTNSEL13_DEFAULT (_AGC_FENOTCHATT6_FENOTCHATTNSEL13_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHATT6 */
+#define _AGC_FENOTCHATT6_FENOTCHCAPCRSE13_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE13 */
+#define _AGC_FENOTCHATT6_FENOTCHCAPCRSE13_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE13 */
+#define _AGC_FENOTCHATT6_FENOTCHCAPCRSE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT6 */
+#define AGC_FENOTCHATT6_FENOTCHCAPCRSE13_DEFAULT (_AGC_FENOTCHATT6_FENOTCHCAPCRSE13_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHATT6 */
+#define _AGC_FENOTCHATT6_FENOTCHCAPFINE13_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE13 */
+#define _AGC_FENOTCHATT6_FENOTCHCAPFINE13_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE13 */
+#define _AGC_FENOTCHATT6_FENOTCHCAPFINE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT6 */
+#define AGC_FENOTCHATT6_FENOTCHCAPFINE13_DEFAULT (_AGC_FENOTCHATT6_FENOTCHCAPFINE13_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHATT6 */
+#define AGC_FENOTCHATT6_FENOTCHRATTNEN13 (0x1UL << 12) /**< FE notch rattn enable for index 13 */
+#define _AGC_FENOTCHATT6_FENOTCHRATTNEN13_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN13 */
+#define _AGC_FENOTCHATT6_FENOTCHRATTNEN13_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN13 */
+#define _AGC_FENOTCHATT6_FENOTCHRATTNEN13_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT6 */
+#define AGC_FENOTCHATT6_FENOTCHRATTNEN13_DEFAULT (_AGC_FENOTCHATT6_FENOTCHRATTNEN13_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHATT6 */
+#define AGC_FENOTCHATT6_FENOTCHEN13 (0x1UL << 13) /**< FE notch enable for index 13 */
+#define _AGC_FENOTCHATT6_FENOTCHEN13_SHIFT 13 /**< Shift value for AGC_FENOTCHEN13 */
+#define _AGC_FENOTCHATT6_FENOTCHEN13_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN13 */
+#define _AGC_FENOTCHATT6_FENOTCHEN13_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT6 */
+#define AGC_FENOTCHATT6_FENOTCHEN13_DEFAULT (_AGC_FENOTCHATT6_FENOTCHEN13_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHATT6 */
+#define _AGC_FENOTCHATT6_FENOTCHATTNSEL14_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL14 */
+#define _AGC_FENOTCHATT6_FENOTCHATTNSEL14_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL14 */
+#define _AGC_FENOTCHATT6_FENOTCHATTNSEL14_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT6 */
+#define AGC_FENOTCHATT6_FENOTCHATTNSEL14_DEFAULT (_AGC_FENOTCHATT6_FENOTCHATTNSEL14_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHATT6 */
+#define _AGC_FENOTCHATT6_FENOTCHCAPCRSE14_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE14 */
+#define _AGC_FENOTCHATT6_FENOTCHCAPCRSE14_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE14 */
+#define _AGC_FENOTCHATT6_FENOTCHCAPCRSE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT6 */
+#define AGC_FENOTCHATT6_FENOTCHCAPCRSE14_DEFAULT (_AGC_FENOTCHATT6_FENOTCHCAPCRSE14_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHATT6 */
+#define _AGC_FENOTCHATT6_FENOTCHCAPFINE14_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE14 */
+#define _AGC_FENOTCHATT6_FENOTCHCAPFINE14_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE14 */
+#define _AGC_FENOTCHATT6_FENOTCHCAPFINE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT6 */
+#define AGC_FENOTCHATT6_FENOTCHCAPFINE14_DEFAULT (_AGC_FENOTCHATT6_FENOTCHCAPFINE14_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHATT6 */
+#define AGC_FENOTCHATT6_FENOTCHRATTNEN14 (0x1UL << 28) /**< FE notch rattn enable for index 14 */
+#define _AGC_FENOTCHATT6_FENOTCHRATTNEN14_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN14 */
+#define _AGC_FENOTCHATT6_FENOTCHRATTNEN14_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN14 */
+#define _AGC_FENOTCHATT6_FENOTCHRATTNEN14_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT6 */
+#define AGC_FENOTCHATT6_FENOTCHRATTNEN14_DEFAULT (_AGC_FENOTCHATT6_FENOTCHRATTNEN14_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHATT6 */
+#define AGC_FENOTCHATT6_FENOTCHEN14 (0x1UL << 29) /**< FE notch enable for index 14 */
+#define _AGC_FENOTCHATT6_FENOTCHEN14_SHIFT 29 /**< Shift value for AGC_FENOTCHEN14 */
+#define _AGC_FENOTCHATT6_FENOTCHEN14_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN14 */
+#define _AGC_FENOTCHATT6_FENOTCHEN14_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT6 */
+#define AGC_FENOTCHATT6_FENOTCHEN14_DEFAULT (_AGC_FENOTCHATT6_FENOTCHEN14_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHATT6 */
+
+/* Bit fields for AGC FENOTCHATT7 */
+#define _AGC_FENOTCHATT7_RESETVALUE 0x20080000UL /**< Default value for AGC_FENOTCHATT7 */
+#define _AGC_FENOTCHATT7_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHATT7 */
+#define _AGC_FENOTCHATT7_FENOTCHATTNSEL15_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL15 */
+#define _AGC_FENOTCHATT7_FENOTCHATTNSEL15_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL15 */
+#define _AGC_FENOTCHATT7_FENOTCHATTNSEL15_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT7 */
+#define AGC_FENOTCHATT7_FENOTCHATTNSEL15_DEFAULT (_AGC_FENOTCHATT7_FENOTCHATTNSEL15_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHATT7 */
+#define _AGC_FENOTCHATT7_FENOTCHCAPCRSE15_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE15 */
+#define _AGC_FENOTCHATT7_FENOTCHCAPCRSE15_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE15 */
+#define _AGC_FENOTCHATT7_FENOTCHCAPCRSE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT7 */
+#define AGC_FENOTCHATT7_FENOTCHCAPCRSE15_DEFAULT (_AGC_FENOTCHATT7_FENOTCHCAPCRSE15_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHATT7 */
+#define _AGC_FENOTCHATT7_FENOTCHCAPFINE15_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE15 */
+#define _AGC_FENOTCHATT7_FENOTCHCAPFINE15_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE15 */
+#define _AGC_FENOTCHATT7_FENOTCHCAPFINE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT7 */
+#define AGC_FENOTCHATT7_FENOTCHCAPFINE15_DEFAULT (_AGC_FENOTCHATT7_FENOTCHCAPFINE15_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHATT7 */
+#define AGC_FENOTCHATT7_FENOTCHRATTNEN15 (0x1UL << 12) /**< FE notch rattn enable for index 15 */
+#define _AGC_FENOTCHATT7_FENOTCHRATTNEN15_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN15 */
+#define _AGC_FENOTCHATT7_FENOTCHRATTNEN15_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN15 */
+#define _AGC_FENOTCHATT7_FENOTCHRATTNEN15_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT7 */
+#define AGC_FENOTCHATT7_FENOTCHRATTNEN15_DEFAULT (_AGC_FENOTCHATT7_FENOTCHRATTNEN15_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHATT7 */
+#define AGC_FENOTCHATT7_FENOTCHEN15 (0x1UL << 13) /**< FE notch enable for index 15 */
+#define _AGC_FENOTCHATT7_FENOTCHEN15_SHIFT 13 /**< Shift value for AGC_FENOTCHEN15 */
+#define _AGC_FENOTCHATT7_FENOTCHEN15_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN15 */
+#define _AGC_FENOTCHATT7_FENOTCHEN15_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT7 */
+#define AGC_FENOTCHATT7_FENOTCHEN15_DEFAULT (_AGC_FENOTCHATT7_FENOTCHEN15_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHATT7 */
+#define _AGC_FENOTCHATT7_FENOTCHATTNSEL16_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL16 */
+#define _AGC_FENOTCHATT7_FENOTCHATTNSEL16_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL16 */
+#define _AGC_FENOTCHATT7_FENOTCHATTNSEL16_DEFAULT 0x00000008UL /**< Mode DEFAULT for AGC_FENOTCHATT7 */
+#define AGC_FENOTCHATT7_FENOTCHATTNSEL16_DEFAULT (_AGC_FENOTCHATT7_FENOTCHATTNSEL16_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHATT7 */
+#define _AGC_FENOTCHATT7_FENOTCHCAPCRSE16_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE16 */
+#define _AGC_FENOTCHATT7_FENOTCHCAPCRSE16_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE16 */
+#define _AGC_FENOTCHATT7_FENOTCHCAPCRSE16_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT7 */
+#define AGC_FENOTCHATT7_FENOTCHCAPCRSE16_DEFAULT (_AGC_FENOTCHATT7_FENOTCHCAPCRSE16_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHATT7 */
+#define _AGC_FENOTCHATT7_FENOTCHCAPFINE16_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE16 */
+#define _AGC_FENOTCHATT7_FENOTCHCAPFINE16_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE16 */
+#define _AGC_FENOTCHATT7_FENOTCHCAPFINE16_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT7 */
+#define AGC_FENOTCHATT7_FENOTCHCAPFINE16_DEFAULT (_AGC_FENOTCHATT7_FENOTCHCAPFINE16_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHATT7 */
+#define AGC_FENOTCHATT7_FENOTCHRATTNEN16 (0x1UL << 28) /**< FE notch rattn enable for index 16 */
+#define _AGC_FENOTCHATT7_FENOTCHRATTNEN16_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN16 */
+#define _AGC_FENOTCHATT7_FENOTCHRATTNEN16_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN16 */
+#define _AGC_FENOTCHATT7_FENOTCHRATTNEN16_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT7 */
+#define AGC_FENOTCHATT7_FENOTCHRATTNEN16_DEFAULT (_AGC_FENOTCHATT7_FENOTCHRATTNEN16_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHATT7 */
+#define AGC_FENOTCHATT7_FENOTCHEN16 (0x1UL << 29) /**< FE notch enable for index 16 */
+#define _AGC_FENOTCHATT7_FENOTCHEN16_SHIFT 29 /**< Shift value for AGC_FENOTCHEN16 */
+#define _AGC_FENOTCHATT7_FENOTCHEN16_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN16 */
+#define _AGC_FENOTCHATT7_FENOTCHEN16_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHATT7 */
+#define AGC_FENOTCHATT7_FENOTCHEN16_DEFAULT (_AGC_FENOTCHATT7_FENOTCHEN16_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHATT7 */
+
+/* Bit fields for AGC FENOTCHATT8 */
+#define _AGC_FENOTCHATT8_RESETVALUE 0x200B200AUL /**< Default value for AGC_FENOTCHATT8 */
+#define _AGC_FENOTCHATT8_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHATT8 */
+#define _AGC_FENOTCHATT8_FENOTCHATTNSEL17_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL17 */
+#define _AGC_FENOTCHATT8_FENOTCHATTNSEL17_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL17 */
+#define _AGC_FENOTCHATT8_FENOTCHATTNSEL17_DEFAULT 0x0000000AUL /**< Mode DEFAULT for AGC_FENOTCHATT8 */
+#define AGC_FENOTCHATT8_FENOTCHATTNSEL17_DEFAULT (_AGC_FENOTCHATT8_FENOTCHATTNSEL17_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHATT8 */
+#define _AGC_FENOTCHATT8_FENOTCHCAPCRSE17_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE17 */
+#define _AGC_FENOTCHATT8_FENOTCHCAPCRSE17_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE17 */
+#define _AGC_FENOTCHATT8_FENOTCHCAPCRSE17_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT8 */
+#define AGC_FENOTCHATT8_FENOTCHCAPCRSE17_DEFAULT (_AGC_FENOTCHATT8_FENOTCHCAPCRSE17_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHATT8 */
+#define _AGC_FENOTCHATT8_FENOTCHCAPFINE17_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE17 */
+#define _AGC_FENOTCHATT8_FENOTCHCAPFINE17_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE17 */
+#define _AGC_FENOTCHATT8_FENOTCHCAPFINE17_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT8 */
+#define AGC_FENOTCHATT8_FENOTCHCAPFINE17_DEFAULT (_AGC_FENOTCHATT8_FENOTCHCAPFINE17_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHATT8 */
+#define AGC_FENOTCHATT8_FENOTCHRATTNEN17 (0x1UL << 12) /**< FE notch rattn enable for index 17 */
+#define _AGC_FENOTCHATT8_FENOTCHRATTNEN17_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN17 */
+#define _AGC_FENOTCHATT8_FENOTCHRATTNEN17_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN17 */
+#define _AGC_FENOTCHATT8_FENOTCHRATTNEN17_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT8 */
+#define AGC_FENOTCHATT8_FENOTCHRATTNEN17_DEFAULT (_AGC_FENOTCHATT8_FENOTCHRATTNEN17_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHATT8 */
+#define AGC_FENOTCHATT8_FENOTCHEN17 (0x1UL << 13) /**< FE notch enable for index 17 */
+#define _AGC_FENOTCHATT8_FENOTCHEN17_SHIFT 13 /**< Shift value for AGC_FENOTCHEN17 */
+#define _AGC_FENOTCHATT8_FENOTCHEN17_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN17 */
+#define _AGC_FENOTCHATT8_FENOTCHEN17_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHATT8 */
+#define AGC_FENOTCHATT8_FENOTCHEN17_DEFAULT (_AGC_FENOTCHATT8_FENOTCHEN17_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHATT8 */
+#define _AGC_FENOTCHATT8_FENOTCHATTNSEL18_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL18 */
+#define _AGC_FENOTCHATT8_FENOTCHATTNSEL18_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL18 */
+#define _AGC_FENOTCHATT8_FENOTCHATTNSEL18_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_FENOTCHATT8 */
+#define AGC_FENOTCHATT8_FENOTCHATTNSEL18_DEFAULT (_AGC_FENOTCHATT8_FENOTCHATTNSEL18_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHATT8 */
+#define _AGC_FENOTCHATT8_FENOTCHCAPCRSE18_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE18 */
+#define _AGC_FENOTCHATT8_FENOTCHCAPCRSE18_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE18 */
+#define _AGC_FENOTCHATT8_FENOTCHCAPCRSE18_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT8 */
+#define AGC_FENOTCHATT8_FENOTCHCAPCRSE18_DEFAULT (_AGC_FENOTCHATT8_FENOTCHCAPCRSE18_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHATT8 */
+#define _AGC_FENOTCHATT8_FENOTCHCAPFINE18_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE18 */
+#define _AGC_FENOTCHATT8_FENOTCHCAPFINE18_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE18 */
+#define _AGC_FENOTCHATT8_FENOTCHCAPFINE18_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT8 */
+#define AGC_FENOTCHATT8_FENOTCHCAPFINE18_DEFAULT (_AGC_FENOTCHATT8_FENOTCHCAPFINE18_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHATT8 */
+#define AGC_FENOTCHATT8_FENOTCHRATTNEN18 (0x1UL << 28) /**< FE notch rattn enable for index 18 */
+#define _AGC_FENOTCHATT8_FENOTCHRATTNEN18_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN18 */
+#define _AGC_FENOTCHATT8_FENOTCHRATTNEN18_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN18 */
+#define _AGC_FENOTCHATT8_FENOTCHRATTNEN18_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT8 */
+#define AGC_FENOTCHATT8_FENOTCHRATTNEN18_DEFAULT (_AGC_FENOTCHATT8_FENOTCHRATTNEN18_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHATT8 */
+#define AGC_FENOTCHATT8_FENOTCHEN18 (0x1UL << 29) /**< FE notch enable for index 18 */
+#define _AGC_FENOTCHATT8_FENOTCHEN18_SHIFT 29 /**< Shift value for AGC_FENOTCHEN18 */
+#define _AGC_FENOTCHATT8_FENOTCHEN18_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN18 */
+#define _AGC_FENOTCHATT8_FENOTCHEN18_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHATT8 */
+#define AGC_FENOTCHATT8_FENOTCHEN18_DEFAULT (_AGC_FENOTCHATT8_FENOTCHEN18_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHATT8 */
+
+/* Bit fields for AGC FENOTCHATT9 */
+#define _AGC_FENOTCHATT9_RESETVALUE 0x200B200BUL /**< Default value for AGC_FENOTCHATT9 */
+#define _AGC_FENOTCHATT9_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHATT9 */
+#define _AGC_FENOTCHATT9_FENOTCHATTNSEL19_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL19 */
+#define _AGC_FENOTCHATT9_FENOTCHATTNSEL19_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL19 */
+#define _AGC_FENOTCHATT9_FENOTCHATTNSEL19_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_FENOTCHATT9 */
+#define AGC_FENOTCHATT9_FENOTCHATTNSEL19_DEFAULT (_AGC_FENOTCHATT9_FENOTCHATTNSEL19_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHATT9 */
+#define _AGC_FENOTCHATT9_FENOTCHCAPCRSE19_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE19 */
+#define _AGC_FENOTCHATT9_FENOTCHCAPCRSE19_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE19 */
+#define _AGC_FENOTCHATT9_FENOTCHCAPCRSE19_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT9 */
+#define AGC_FENOTCHATT9_FENOTCHCAPCRSE19_DEFAULT (_AGC_FENOTCHATT9_FENOTCHCAPCRSE19_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHATT9 */
+#define _AGC_FENOTCHATT9_FENOTCHCAPFINE19_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE19 */
+#define _AGC_FENOTCHATT9_FENOTCHCAPFINE19_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE19 */
+#define _AGC_FENOTCHATT9_FENOTCHCAPFINE19_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT9 */
+#define AGC_FENOTCHATT9_FENOTCHCAPFINE19_DEFAULT (_AGC_FENOTCHATT9_FENOTCHCAPFINE19_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHATT9 */
+#define AGC_FENOTCHATT9_FENOTCHRATTNEN19 (0x1UL << 12) /**< FE notch rattn enable for index 19 */
+#define _AGC_FENOTCHATT9_FENOTCHRATTNEN19_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN19 */
+#define _AGC_FENOTCHATT9_FENOTCHRATTNEN19_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN19 */
+#define _AGC_FENOTCHATT9_FENOTCHRATTNEN19_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT9 */
+#define AGC_FENOTCHATT9_FENOTCHRATTNEN19_DEFAULT (_AGC_FENOTCHATT9_FENOTCHRATTNEN19_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHATT9 */
+#define AGC_FENOTCHATT9_FENOTCHEN19 (0x1UL << 13) /**< FE notch enable for index 19 */
+#define _AGC_FENOTCHATT9_FENOTCHEN19_SHIFT 13 /**< Shift value for AGC_FENOTCHEN19 */
+#define _AGC_FENOTCHATT9_FENOTCHEN19_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN19 */
+#define _AGC_FENOTCHATT9_FENOTCHEN19_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHATT9 */
+#define AGC_FENOTCHATT9_FENOTCHEN19_DEFAULT (_AGC_FENOTCHATT9_FENOTCHEN19_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHATT9 */
+#define _AGC_FENOTCHATT9_FENOTCHATTNSEL20_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL20 */
+#define _AGC_FENOTCHATT9_FENOTCHATTNSEL20_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL20 */
+#define _AGC_FENOTCHATT9_FENOTCHATTNSEL20_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_FENOTCHATT9 */
+#define AGC_FENOTCHATT9_FENOTCHATTNSEL20_DEFAULT (_AGC_FENOTCHATT9_FENOTCHATTNSEL20_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHATT9 */
+#define _AGC_FENOTCHATT9_FENOTCHCAPCRSE20_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE20 */
+#define _AGC_FENOTCHATT9_FENOTCHCAPCRSE20_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE20 */
+#define _AGC_FENOTCHATT9_FENOTCHCAPCRSE20_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT9 */
+#define AGC_FENOTCHATT9_FENOTCHCAPCRSE20_DEFAULT (_AGC_FENOTCHATT9_FENOTCHCAPCRSE20_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHATT9 */
+#define _AGC_FENOTCHATT9_FENOTCHCAPFINE20_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE20 */
+#define _AGC_FENOTCHATT9_FENOTCHCAPFINE20_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE20 */
+#define _AGC_FENOTCHATT9_FENOTCHCAPFINE20_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT9 */
+#define AGC_FENOTCHATT9_FENOTCHCAPFINE20_DEFAULT (_AGC_FENOTCHATT9_FENOTCHCAPFINE20_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHATT9 */
+#define AGC_FENOTCHATT9_FENOTCHRATTNEN20 (0x1UL << 28) /**< FE notch rattn enable for index 20 */
+#define _AGC_FENOTCHATT9_FENOTCHRATTNEN20_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN20 */
+#define _AGC_FENOTCHATT9_FENOTCHRATTNEN20_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN20 */
+#define _AGC_FENOTCHATT9_FENOTCHRATTNEN20_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT9 */
+#define AGC_FENOTCHATT9_FENOTCHRATTNEN20_DEFAULT (_AGC_FENOTCHATT9_FENOTCHRATTNEN20_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHATT9 */
+#define AGC_FENOTCHATT9_FENOTCHEN20 (0x1UL << 29) /**< FE notch enable for index 20 */
+#define _AGC_FENOTCHATT9_FENOTCHEN20_SHIFT 29 /**< Shift value for AGC_FENOTCHEN20 */
+#define _AGC_FENOTCHATT9_FENOTCHEN20_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN20 */
+#define _AGC_FENOTCHATT9_FENOTCHEN20_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHATT9 */
+#define AGC_FENOTCHATT9_FENOTCHEN20_DEFAULT (_AGC_FENOTCHATT9_FENOTCHEN20_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHATT9 */
+
+/* Bit fields for AGC FENOTCHATT10 */
+#define _AGC_FENOTCHATT10_RESETVALUE 0x200B200BUL /**< Default value for AGC_FENOTCHATT10 */
+#define _AGC_FENOTCHATT10_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHATT10 */
+#define _AGC_FENOTCHATT10_FENOTCHATTNSEL21_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL21 */
+#define _AGC_FENOTCHATT10_FENOTCHATTNSEL21_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL21 */
+#define _AGC_FENOTCHATT10_FENOTCHATTNSEL21_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_FENOTCHATT10 */
+#define AGC_FENOTCHATT10_FENOTCHATTNSEL21_DEFAULT (_AGC_FENOTCHATT10_FENOTCHATTNSEL21_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHATT10 */
+#define _AGC_FENOTCHATT10_FENOTCHCAPCRSE21_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE21 */
+#define _AGC_FENOTCHATT10_FENOTCHCAPCRSE21_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE21 */
+#define _AGC_FENOTCHATT10_FENOTCHCAPCRSE21_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT10 */
+#define AGC_FENOTCHATT10_FENOTCHCAPCRSE21_DEFAULT (_AGC_FENOTCHATT10_FENOTCHCAPCRSE21_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHATT10 */
+#define _AGC_FENOTCHATT10_FENOTCHCAPFINE21_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE21 */
+#define _AGC_FENOTCHATT10_FENOTCHCAPFINE21_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE21 */
+#define _AGC_FENOTCHATT10_FENOTCHCAPFINE21_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT10 */
+#define AGC_FENOTCHATT10_FENOTCHCAPFINE21_DEFAULT (_AGC_FENOTCHATT10_FENOTCHCAPFINE21_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHATT10 */
+#define AGC_FENOTCHATT10_FENOTCHRATTNEN21 (0x1UL << 12) /**< FE notch rattn enable for index 21 */
+#define _AGC_FENOTCHATT10_FENOTCHRATTNEN21_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN21 */
+#define _AGC_FENOTCHATT10_FENOTCHRATTNEN21_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN21 */
+#define _AGC_FENOTCHATT10_FENOTCHRATTNEN21_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT10 */
+#define AGC_FENOTCHATT10_FENOTCHRATTNEN21_DEFAULT (_AGC_FENOTCHATT10_FENOTCHRATTNEN21_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHATT10 */
+#define AGC_FENOTCHATT10_FENOTCHEN21 (0x1UL << 13) /**< FE notch enable for index 21 */
+#define _AGC_FENOTCHATT10_FENOTCHEN21_SHIFT 13 /**< Shift value for AGC_FENOTCHEN21 */
+#define _AGC_FENOTCHATT10_FENOTCHEN21_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN21 */
+#define _AGC_FENOTCHATT10_FENOTCHEN21_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHATT10 */
+#define AGC_FENOTCHATT10_FENOTCHEN21_DEFAULT (_AGC_FENOTCHATT10_FENOTCHEN21_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHATT10 */
+#define _AGC_FENOTCHATT10_FENOTCHATTNSEL22_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL22 */
+#define _AGC_FENOTCHATT10_FENOTCHATTNSEL22_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL22 */
+#define _AGC_FENOTCHATT10_FENOTCHATTNSEL22_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_FENOTCHATT10 */
+#define AGC_FENOTCHATT10_FENOTCHATTNSEL22_DEFAULT (_AGC_FENOTCHATT10_FENOTCHATTNSEL22_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHATT10 */
+#define _AGC_FENOTCHATT10_FENOTCHCAPCRSE22_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE22 */
+#define _AGC_FENOTCHATT10_FENOTCHCAPCRSE22_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE22 */
+#define _AGC_FENOTCHATT10_FENOTCHCAPCRSE22_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT10 */
+#define AGC_FENOTCHATT10_FENOTCHCAPCRSE22_DEFAULT (_AGC_FENOTCHATT10_FENOTCHCAPCRSE22_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHATT10 */
+#define _AGC_FENOTCHATT10_FENOTCHCAPFINE22_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE22 */
+#define _AGC_FENOTCHATT10_FENOTCHCAPFINE22_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE22 */
+#define _AGC_FENOTCHATT10_FENOTCHCAPFINE22_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT10 */
+#define AGC_FENOTCHATT10_FENOTCHCAPFINE22_DEFAULT (_AGC_FENOTCHATT10_FENOTCHCAPFINE22_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHATT10 */
+#define AGC_FENOTCHATT10_FENOTCHRATTNEN22 (0x1UL << 28) /**< FE notch rattn enable for index 22 */
+#define _AGC_FENOTCHATT10_FENOTCHRATTNEN22_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN22 */
+#define _AGC_FENOTCHATT10_FENOTCHRATTNEN22_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN22 */
+#define _AGC_FENOTCHATT10_FENOTCHRATTNEN22_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT10 */
+#define AGC_FENOTCHATT10_FENOTCHRATTNEN22_DEFAULT (_AGC_FENOTCHATT10_FENOTCHRATTNEN22_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHATT10 */
+#define AGC_FENOTCHATT10_FENOTCHEN22 (0x1UL << 29) /**< FE notch enable for index 22 */
+#define _AGC_FENOTCHATT10_FENOTCHEN22_SHIFT 29 /**< Shift value for AGC_FENOTCHEN22 */
+#define _AGC_FENOTCHATT10_FENOTCHEN22_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN22 */
+#define _AGC_FENOTCHATT10_FENOTCHEN22_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHATT10 */
+#define AGC_FENOTCHATT10_FENOTCHEN22_DEFAULT (_AGC_FENOTCHATT10_FENOTCHEN22_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHATT10 */
+
+/* Bit fields for AGC FENOTCHATT11 */
+#define _AGC_FENOTCHATT11_RESETVALUE 0x200B200BUL /**< Default value for AGC_FENOTCHATT11 */
+#define _AGC_FENOTCHATT11_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHATT11 */
+#define _AGC_FENOTCHATT11_FENOTCHATTNSEL23_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL23 */
+#define _AGC_FENOTCHATT11_FENOTCHATTNSEL23_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL23 */
+#define _AGC_FENOTCHATT11_FENOTCHATTNSEL23_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_FENOTCHATT11 */
+#define AGC_FENOTCHATT11_FENOTCHATTNSEL23_DEFAULT (_AGC_FENOTCHATT11_FENOTCHATTNSEL23_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHATT11 */
+#define _AGC_FENOTCHATT11_FENOTCHCAPCRSE23_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE23 */
+#define _AGC_FENOTCHATT11_FENOTCHCAPCRSE23_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE23 */
+#define _AGC_FENOTCHATT11_FENOTCHCAPCRSE23_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT11 */
+#define AGC_FENOTCHATT11_FENOTCHCAPCRSE23_DEFAULT (_AGC_FENOTCHATT11_FENOTCHCAPCRSE23_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHATT11 */
+#define _AGC_FENOTCHATT11_FENOTCHCAPFINE23_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE23 */
+#define _AGC_FENOTCHATT11_FENOTCHCAPFINE23_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE23 */
+#define _AGC_FENOTCHATT11_FENOTCHCAPFINE23_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT11 */
+#define AGC_FENOTCHATT11_FENOTCHCAPFINE23_DEFAULT (_AGC_FENOTCHATT11_FENOTCHCAPFINE23_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHATT11 */
+#define AGC_FENOTCHATT11_FENOTCHRATTNEN23 (0x1UL << 12) /**< FE notch rattn enable for index 23 */
+#define _AGC_FENOTCHATT11_FENOTCHRATTNEN23_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN23 */
+#define _AGC_FENOTCHATT11_FENOTCHRATTNEN23_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN23 */
+#define _AGC_FENOTCHATT11_FENOTCHRATTNEN23_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT11 */
+#define AGC_FENOTCHATT11_FENOTCHRATTNEN23_DEFAULT (_AGC_FENOTCHATT11_FENOTCHRATTNEN23_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHATT11 */
+#define AGC_FENOTCHATT11_FENOTCHEN23 (0x1UL << 13) /**< FE notch enable for index 23 */
+#define _AGC_FENOTCHATT11_FENOTCHEN23_SHIFT 13 /**< Shift value for AGC_FENOTCHEN23 */
+#define _AGC_FENOTCHATT11_FENOTCHEN23_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN23 */
+#define _AGC_FENOTCHATT11_FENOTCHEN23_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHATT11 */
+#define AGC_FENOTCHATT11_FENOTCHEN23_DEFAULT (_AGC_FENOTCHATT11_FENOTCHEN23_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHATT11 */
+#define _AGC_FENOTCHATT11_FENOTCHATTNSEL24_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL24 */
+#define _AGC_FENOTCHATT11_FENOTCHATTNSEL24_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL24 */
+#define _AGC_FENOTCHATT11_FENOTCHATTNSEL24_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_FENOTCHATT11 */
+#define AGC_FENOTCHATT11_FENOTCHATTNSEL24_DEFAULT (_AGC_FENOTCHATT11_FENOTCHATTNSEL24_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHATT11 */
+#define _AGC_FENOTCHATT11_FENOTCHCAPCRSE24_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE24 */
+#define _AGC_FENOTCHATT11_FENOTCHCAPCRSE24_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE24 */
+#define _AGC_FENOTCHATT11_FENOTCHCAPCRSE24_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT11 */
+#define AGC_FENOTCHATT11_FENOTCHCAPCRSE24_DEFAULT (_AGC_FENOTCHATT11_FENOTCHCAPCRSE24_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHATT11 */
+#define _AGC_FENOTCHATT11_FENOTCHCAPFINE24_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE24 */
+#define _AGC_FENOTCHATT11_FENOTCHCAPFINE24_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE24 */
+#define _AGC_FENOTCHATT11_FENOTCHCAPFINE24_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT11 */
+#define AGC_FENOTCHATT11_FENOTCHCAPFINE24_DEFAULT (_AGC_FENOTCHATT11_FENOTCHCAPFINE24_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHATT11 */
+#define AGC_FENOTCHATT11_FENOTCHRATTNEN24 (0x1UL << 28) /**< FE notch rattn enable for index 24 */
+#define _AGC_FENOTCHATT11_FENOTCHRATTNEN24_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN24 */
+#define _AGC_FENOTCHATT11_FENOTCHRATTNEN24_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN24 */
+#define _AGC_FENOTCHATT11_FENOTCHRATTNEN24_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHATT11 */
+#define AGC_FENOTCHATT11_FENOTCHRATTNEN24_DEFAULT (_AGC_FENOTCHATT11_FENOTCHRATTNEN24_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHATT11 */
+#define AGC_FENOTCHATT11_FENOTCHEN24 (0x1UL << 29) /**< FE notch enable for index 24 */
+#define _AGC_FENOTCHATT11_FENOTCHEN24_SHIFT 29 /**< Shift value for AGC_FENOTCHEN24 */
+#define _AGC_FENOTCHATT11_FENOTCHEN24_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN24 */
+#define _AGC_FENOTCHATT11_FENOTCHEN24_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHATT11 */
+#define AGC_FENOTCHATT11_FENOTCHEN24_DEFAULT (_AGC_FENOTCHATT11_FENOTCHEN24_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHATT11 */
+
+/* Bit fields for AGC FENOTCHFILT0 */
+#define _AGC_FENOTCHFILT0_RESETVALUE 0x00000000UL /**< Default value for AGC_FENOTCHFILT0 */
+#define _AGC_FENOTCHFILT0_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHFILT0 */
+#define _AGC_FENOTCHFILT0_FENOTCHATTNSEL1_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL1 */
+#define _AGC_FENOTCHFILT0_FENOTCHATTNSEL1_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL1 */
+#define _AGC_FENOTCHFILT0_FENOTCHATTNSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT0 */
+#define AGC_FENOTCHFILT0_FENOTCHATTNSEL1_DEFAULT (_AGC_FENOTCHFILT0_FENOTCHATTNSEL1_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT0 */
+#define _AGC_FENOTCHFILT0_FENOTCHCAPCRSE1_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE1 */
+#define _AGC_FENOTCHFILT0_FENOTCHCAPCRSE1_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE1 */
+#define _AGC_FENOTCHFILT0_FENOTCHCAPCRSE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT0 */
+#define AGC_FENOTCHFILT0_FENOTCHCAPCRSE1_DEFAULT (_AGC_FENOTCHFILT0_FENOTCHCAPCRSE1_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT0 */
+#define _AGC_FENOTCHFILT0_FENOTCHCAPFINE1_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE1 */
+#define _AGC_FENOTCHFILT0_FENOTCHCAPFINE1_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE1 */
+#define _AGC_FENOTCHFILT0_FENOTCHCAPFINE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT0 */
+#define AGC_FENOTCHFILT0_FENOTCHCAPFINE1_DEFAULT (_AGC_FENOTCHFILT0_FENOTCHCAPFINE1_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT0 */
+#define AGC_FENOTCHFILT0_FENOTCHRATTNEN1 (0x1UL << 12) /**< FE notch rattn enable for index 1 */
+#define _AGC_FENOTCHFILT0_FENOTCHRATTNEN1_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN1 */
+#define _AGC_FENOTCHFILT0_FENOTCHRATTNEN1_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN1 */
+#define _AGC_FENOTCHFILT0_FENOTCHRATTNEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT0 */
+#define AGC_FENOTCHFILT0_FENOTCHRATTNEN1_DEFAULT (_AGC_FENOTCHFILT0_FENOTCHRATTNEN1_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT0 */
+#define AGC_FENOTCHFILT0_FENOTCHEN1 (0x1UL << 13) /**< FE notch enable for index 1 */
+#define _AGC_FENOTCHFILT0_FENOTCHEN1_SHIFT 13 /**< Shift value for AGC_FENOTCHEN1 */
+#define _AGC_FENOTCHFILT0_FENOTCHEN1_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN1 */
+#define _AGC_FENOTCHFILT0_FENOTCHEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT0 */
+#define AGC_FENOTCHFILT0_FENOTCHEN1_DEFAULT (_AGC_FENOTCHFILT0_FENOTCHEN1_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT0 */
+#define _AGC_FENOTCHFILT0_FENOTCHATTNSEL2_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL2 */
+#define _AGC_FENOTCHFILT0_FENOTCHATTNSEL2_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL2 */
+#define _AGC_FENOTCHFILT0_FENOTCHATTNSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT0 */
+#define AGC_FENOTCHFILT0_FENOTCHATTNSEL2_DEFAULT (_AGC_FENOTCHFILT0_FENOTCHATTNSEL2_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT0 */
+#define _AGC_FENOTCHFILT0_FENOTCHCAPCRSE2_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE2 */
+#define _AGC_FENOTCHFILT0_FENOTCHCAPCRSE2_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE2 */
+#define _AGC_FENOTCHFILT0_FENOTCHCAPCRSE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT0 */
+#define AGC_FENOTCHFILT0_FENOTCHCAPCRSE2_DEFAULT (_AGC_FENOTCHFILT0_FENOTCHCAPCRSE2_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT0 */
+#define _AGC_FENOTCHFILT0_FENOTCHCAPFINE2_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE2 */
+#define _AGC_FENOTCHFILT0_FENOTCHCAPFINE2_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE2 */
+#define _AGC_FENOTCHFILT0_FENOTCHCAPFINE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT0 */
+#define AGC_FENOTCHFILT0_FENOTCHCAPFINE2_DEFAULT (_AGC_FENOTCHFILT0_FENOTCHCAPFINE2_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT0 */
+#define AGC_FENOTCHFILT0_FENOTCHRATTNEN2 (0x1UL << 28) /**< FE notch rattn enable for index 2 */
+#define _AGC_FENOTCHFILT0_FENOTCHRATTNEN2_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN2 */
+#define _AGC_FENOTCHFILT0_FENOTCHRATTNEN2_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN2 */
+#define _AGC_FENOTCHFILT0_FENOTCHRATTNEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT0 */
+#define AGC_FENOTCHFILT0_FENOTCHRATTNEN2_DEFAULT (_AGC_FENOTCHFILT0_FENOTCHRATTNEN2_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT0 */
+#define AGC_FENOTCHFILT0_FENOTCHEN2 (0x1UL << 29) /**< FE notch enable for index 2 */
+#define _AGC_FENOTCHFILT0_FENOTCHEN2_SHIFT 29 /**< Shift value for AGC_FENOTCHEN2 */
+#define _AGC_FENOTCHFILT0_FENOTCHEN2_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN2 */
+#define _AGC_FENOTCHFILT0_FENOTCHEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT0 */
+#define AGC_FENOTCHFILT0_FENOTCHEN2_DEFAULT (_AGC_FENOTCHFILT0_FENOTCHEN2_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT0 */
+
+/* Bit fields for AGC FENOTCHFILT1 */
+#define _AGC_FENOTCHFILT1_RESETVALUE 0x00000000UL /**< Default value for AGC_FENOTCHFILT1 */
+#define _AGC_FENOTCHFILT1_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHFILT1 */
+#define _AGC_FENOTCHFILT1_FENOTCHATTNSEL3_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL3 */
+#define _AGC_FENOTCHFILT1_FENOTCHATTNSEL3_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL3 */
+#define _AGC_FENOTCHFILT1_FENOTCHATTNSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT1 */
+#define AGC_FENOTCHFILT1_FENOTCHATTNSEL3_DEFAULT (_AGC_FENOTCHFILT1_FENOTCHATTNSEL3_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT1 */
+#define _AGC_FENOTCHFILT1_FENOTCHCAPCRSE3_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE3 */
+#define _AGC_FENOTCHFILT1_FENOTCHCAPCRSE3_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE3 */
+#define _AGC_FENOTCHFILT1_FENOTCHCAPCRSE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT1 */
+#define AGC_FENOTCHFILT1_FENOTCHCAPCRSE3_DEFAULT (_AGC_FENOTCHFILT1_FENOTCHCAPCRSE3_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT1 */
+#define _AGC_FENOTCHFILT1_FENOTCHCAPFINE3_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE3 */
+#define _AGC_FENOTCHFILT1_FENOTCHCAPFINE3_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE3 */
+#define _AGC_FENOTCHFILT1_FENOTCHCAPFINE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT1 */
+#define AGC_FENOTCHFILT1_FENOTCHCAPFINE3_DEFAULT (_AGC_FENOTCHFILT1_FENOTCHCAPFINE3_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT1 */
+#define AGC_FENOTCHFILT1_FENOTCHRATTNEN3 (0x1UL << 12) /**< FE notch rattn enable for index 3 */
+#define _AGC_FENOTCHFILT1_FENOTCHRATTNEN3_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN3 */
+#define _AGC_FENOTCHFILT1_FENOTCHRATTNEN3_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN3 */
+#define _AGC_FENOTCHFILT1_FENOTCHRATTNEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT1 */
+#define AGC_FENOTCHFILT1_FENOTCHRATTNEN3_DEFAULT (_AGC_FENOTCHFILT1_FENOTCHRATTNEN3_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT1 */
+#define AGC_FENOTCHFILT1_FENOTCHEN3 (0x1UL << 13) /**< FE notch enable for index 3 */
+#define _AGC_FENOTCHFILT1_FENOTCHEN3_SHIFT 13 /**< Shift value for AGC_FENOTCHEN3 */
+#define _AGC_FENOTCHFILT1_FENOTCHEN3_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN3 */
+#define _AGC_FENOTCHFILT1_FENOTCHEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT1 */
+#define AGC_FENOTCHFILT1_FENOTCHEN3_DEFAULT (_AGC_FENOTCHFILT1_FENOTCHEN3_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT1 */
+#define _AGC_FENOTCHFILT1_FENOTCHATTNSEL4_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL4 */
+#define _AGC_FENOTCHFILT1_FENOTCHATTNSEL4_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL4 */
+#define _AGC_FENOTCHFILT1_FENOTCHATTNSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT1 */
+#define AGC_FENOTCHFILT1_FENOTCHATTNSEL4_DEFAULT (_AGC_FENOTCHFILT1_FENOTCHATTNSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT1 */
+#define _AGC_FENOTCHFILT1_FENOTCHCAPCRSE4_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE4 */
+#define _AGC_FENOTCHFILT1_FENOTCHCAPCRSE4_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE4 */
+#define _AGC_FENOTCHFILT1_FENOTCHCAPCRSE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT1 */
+#define AGC_FENOTCHFILT1_FENOTCHCAPCRSE4_DEFAULT (_AGC_FENOTCHFILT1_FENOTCHCAPCRSE4_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT1 */
+#define _AGC_FENOTCHFILT1_FENOTCHCAPFINE4_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE4 */
+#define _AGC_FENOTCHFILT1_FENOTCHCAPFINE4_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE4 */
+#define _AGC_FENOTCHFILT1_FENOTCHCAPFINE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT1 */
+#define AGC_FENOTCHFILT1_FENOTCHCAPFINE4_DEFAULT (_AGC_FENOTCHFILT1_FENOTCHCAPFINE4_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT1 */
+#define AGC_FENOTCHFILT1_FENOTCHRATTNEN4 (0x1UL << 28) /**< FE notch rattn enable for index 4 */
+#define _AGC_FENOTCHFILT1_FENOTCHRATTNEN4_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN4 */
+#define _AGC_FENOTCHFILT1_FENOTCHRATTNEN4_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN4 */
+#define _AGC_FENOTCHFILT1_FENOTCHRATTNEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT1 */
+#define AGC_FENOTCHFILT1_FENOTCHRATTNEN4_DEFAULT (_AGC_FENOTCHFILT1_FENOTCHRATTNEN4_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT1 */
+#define AGC_FENOTCHFILT1_FENOTCHEN4 (0x1UL << 29) /**< FE notch enable for index 4 */
+#define _AGC_FENOTCHFILT1_FENOTCHEN4_SHIFT 29 /**< Shift value for AGC_FENOTCHEN4 */
+#define _AGC_FENOTCHFILT1_FENOTCHEN4_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN4 */
+#define _AGC_FENOTCHFILT1_FENOTCHEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT1 */
+#define AGC_FENOTCHFILT1_FENOTCHEN4_DEFAULT (_AGC_FENOTCHFILT1_FENOTCHEN4_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT1 */
+
+/* Bit fields for AGC FENOTCHFILT2 */
+#define _AGC_FENOTCHFILT2_RESETVALUE 0x00000000UL /**< Default value for AGC_FENOTCHFILT2 */
+#define _AGC_FENOTCHFILT2_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHFILT2 */
+#define _AGC_FENOTCHFILT2_FENOTCHATTNSEL5_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL5 */
+#define _AGC_FENOTCHFILT2_FENOTCHATTNSEL5_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL5 */
+#define _AGC_FENOTCHFILT2_FENOTCHATTNSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT2 */
+#define AGC_FENOTCHFILT2_FENOTCHATTNSEL5_DEFAULT (_AGC_FENOTCHFILT2_FENOTCHATTNSEL5_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT2 */
+#define _AGC_FENOTCHFILT2_FENOTCHCAPCRSE5_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE5 */
+#define _AGC_FENOTCHFILT2_FENOTCHCAPCRSE5_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE5 */
+#define _AGC_FENOTCHFILT2_FENOTCHCAPCRSE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT2 */
+#define AGC_FENOTCHFILT2_FENOTCHCAPCRSE5_DEFAULT (_AGC_FENOTCHFILT2_FENOTCHCAPCRSE5_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT2 */
+#define _AGC_FENOTCHFILT2_FENOTCHCAPFINE5_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE5 */
+#define _AGC_FENOTCHFILT2_FENOTCHCAPFINE5_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE5 */
+#define _AGC_FENOTCHFILT2_FENOTCHCAPFINE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT2 */
+#define AGC_FENOTCHFILT2_FENOTCHCAPFINE5_DEFAULT (_AGC_FENOTCHFILT2_FENOTCHCAPFINE5_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT2 */
+#define AGC_FENOTCHFILT2_FENOTCHRATTNEN5 (0x1UL << 12) /**< FE notch rattn enable for index 5 */
+#define _AGC_FENOTCHFILT2_FENOTCHRATTNEN5_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN5 */
+#define _AGC_FENOTCHFILT2_FENOTCHRATTNEN5_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN5 */
+#define _AGC_FENOTCHFILT2_FENOTCHRATTNEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT2 */
+#define AGC_FENOTCHFILT2_FENOTCHRATTNEN5_DEFAULT (_AGC_FENOTCHFILT2_FENOTCHRATTNEN5_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT2 */
+#define AGC_FENOTCHFILT2_FENOTCHEN5 (0x1UL << 13) /**< FE notch enable for index 5 */
+#define _AGC_FENOTCHFILT2_FENOTCHEN5_SHIFT 13 /**< Shift value for AGC_FENOTCHEN5 */
+#define _AGC_FENOTCHFILT2_FENOTCHEN5_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN5 */
+#define _AGC_FENOTCHFILT2_FENOTCHEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT2 */
+#define AGC_FENOTCHFILT2_FENOTCHEN5_DEFAULT (_AGC_FENOTCHFILT2_FENOTCHEN5_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT2 */
+#define _AGC_FENOTCHFILT2_FENOTCHATTNSEL6_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL6 */
+#define _AGC_FENOTCHFILT2_FENOTCHATTNSEL6_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL6 */
+#define _AGC_FENOTCHFILT2_FENOTCHATTNSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT2 */
+#define AGC_FENOTCHFILT2_FENOTCHATTNSEL6_DEFAULT (_AGC_FENOTCHFILT2_FENOTCHATTNSEL6_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT2 */
+#define _AGC_FENOTCHFILT2_FENOTCHCAPCRSE6_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE6 */
+#define _AGC_FENOTCHFILT2_FENOTCHCAPCRSE6_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE6 */
+#define _AGC_FENOTCHFILT2_FENOTCHCAPCRSE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT2 */
+#define AGC_FENOTCHFILT2_FENOTCHCAPCRSE6_DEFAULT (_AGC_FENOTCHFILT2_FENOTCHCAPCRSE6_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT2 */
+#define _AGC_FENOTCHFILT2_FENOTCHCAPFINE6_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE6 */
+#define _AGC_FENOTCHFILT2_FENOTCHCAPFINE6_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE6 */
+#define _AGC_FENOTCHFILT2_FENOTCHCAPFINE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT2 */
+#define AGC_FENOTCHFILT2_FENOTCHCAPFINE6_DEFAULT (_AGC_FENOTCHFILT2_FENOTCHCAPFINE6_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT2 */
+#define AGC_FENOTCHFILT2_FENOTCHRATTNEN6 (0x1UL << 28) /**< FE notch rattn enable for index 6 */
+#define _AGC_FENOTCHFILT2_FENOTCHRATTNEN6_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN6 */
+#define _AGC_FENOTCHFILT2_FENOTCHRATTNEN6_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN6 */
+#define _AGC_FENOTCHFILT2_FENOTCHRATTNEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT2 */
+#define AGC_FENOTCHFILT2_FENOTCHRATTNEN6_DEFAULT (_AGC_FENOTCHFILT2_FENOTCHRATTNEN6_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT2 */
+#define AGC_FENOTCHFILT2_FENOTCHEN6 (0x1UL << 29) /**< FE notch enable for index 6 */
+#define _AGC_FENOTCHFILT2_FENOTCHEN6_SHIFT 29 /**< Shift value for AGC_FENOTCHEN6 */
+#define _AGC_FENOTCHFILT2_FENOTCHEN6_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN6 */
+#define _AGC_FENOTCHFILT2_FENOTCHEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT2 */
+#define AGC_FENOTCHFILT2_FENOTCHEN6_DEFAULT (_AGC_FENOTCHFILT2_FENOTCHEN6_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT2 */
+
+/* Bit fields for AGC FENOTCHFILT3 */
+#define _AGC_FENOTCHFILT3_RESETVALUE 0x00000000UL /**< Default value for AGC_FENOTCHFILT3 */
+#define _AGC_FENOTCHFILT3_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHFILT3 */
+#define _AGC_FENOTCHFILT3_FENOTCHATTNSEL7_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL7 */
+#define _AGC_FENOTCHFILT3_FENOTCHATTNSEL7_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL7 */
+#define _AGC_FENOTCHFILT3_FENOTCHATTNSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT3 */
+#define AGC_FENOTCHFILT3_FENOTCHATTNSEL7_DEFAULT (_AGC_FENOTCHFILT3_FENOTCHATTNSEL7_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT3 */
+#define _AGC_FENOTCHFILT3_FENOTCHCAPCRSE7_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE7 */
+#define _AGC_FENOTCHFILT3_FENOTCHCAPCRSE7_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE7 */
+#define _AGC_FENOTCHFILT3_FENOTCHCAPCRSE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT3 */
+#define AGC_FENOTCHFILT3_FENOTCHCAPCRSE7_DEFAULT (_AGC_FENOTCHFILT3_FENOTCHCAPCRSE7_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT3 */
+#define _AGC_FENOTCHFILT3_FENOTCHCAPFINE7_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE7 */
+#define _AGC_FENOTCHFILT3_FENOTCHCAPFINE7_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE7 */
+#define _AGC_FENOTCHFILT3_FENOTCHCAPFINE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT3 */
+#define AGC_FENOTCHFILT3_FENOTCHCAPFINE7_DEFAULT (_AGC_FENOTCHFILT3_FENOTCHCAPFINE7_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT3 */
+#define AGC_FENOTCHFILT3_FENOTCHRATTNEN7 (0x1UL << 12) /**< FE notch rattn enable for index 7 */
+#define _AGC_FENOTCHFILT3_FENOTCHRATTNEN7_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN7 */
+#define _AGC_FENOTCHFILT3_FENOTCHRATTNEN7_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN7 */
+#define _AGC_FENOTCHFILT3_FENOTCHRATTNEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT3 */
+#define AGC_FENOTCHFILT3_FENOTCHRATTNEN7_DEFAULT (_AGC_FENOTCHFILT3_FENOTCHRATTNEN7_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT3 */
+#define AGC_FENOTCHFILT3_FENOTCHEN7 (0x1UL << 13) /**< FE notch enable for index 7 */
+#define _AGC_FENOTCHFILT3_FENOTCHEN7_SHIFT 13 /**< Shift value for AGC_FENOTCHEN7 */
+#define _AGC_FENOTCHFILT3_FENOTCHEN7_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN7 */
+#define _AGC_FENOTCHFILT3_FENOTCHEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT3 */
+#define AGC_FENOTCHFILT3_FENOTCHEN7_DEFAULT (_AGC_FENOTCHFILT3_FENOTCHEN7_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT3 */
+#define _AGC_FENOTCHFILT3_FENOTCHATTNSEL8_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL8 */
+#define _AGC_FENOTCHFILT3_FENOTCHATTNSEL8_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL8 */
+#define _AGC_FENOTCHFILT3_FENOTCHATTNSEL8_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT3 */
+#define AGC_FENOTCHFILT3_FENOTCHATTNSEL8_DEFAULT (_AGC_FENOTCHFILT3_FENOTCHATTNSEL8_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT3 */
+#define _AGC_FENOTCHFILT3_FENOTCHCAPCRSE8_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE8 */
+#define _AGC_FENOTCHFILT3_FENOTCHCAPCRSE8_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE8 */
+#define _AGC_FENOTCHFILT3_FENOTCHCAPCRSE8_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT3 */
+#define AGC_FENOTCHFILT3_FENOTCHCAPCRSE8_DEFAULT (_AGC_FENOTCHFILT3_FENOTCHCAPCRSE8_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT3 */
+#define _AGC_FENOTCHFILT3_FENOTCHCAPFINE8_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE8 */
+#define _AGC_FENOTCHFILT3_FENOTCHCAPFINE8_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE8 */
+#define _AGC_FENOTCHFILT3_FENOTCHCAPFINE8_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT3 */
+#define AGC_FENOTCHFILT3_FENOTCHCAPFINE8_DEFAULT (_AGC_FENOTCHFILT3_FENOTCHCAPFINE8_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT3 */
+#define AGC_FENOTCHFILT3_FENOTCHRATTNEN8 (0x1UL << 28) /**< FE notch rattn enable for index 8 */
+#define _AGC_FENOTCHFILT3_FENOTCHRATTNEN8_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN8 */
+#define _AGC_FENOTCHFILT3_FENOTCHRATTNEN8_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN8 */
+#define _AGC_FENOTCHFILT3_FENOTCHRATTNEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT3 */
+#define AGC_FENOTCHFILT3_FENOTCHRATTNEN8_DEFAULT (_AGC_FENOTCHFILT3_FENOTCHRATTNEN8_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT3 */
+#define AGC_FENOTCHFILT3_FENOTCHEN8 (0x1UL << 29) /**< FE notch enable for index 8 */
+#define _AGC_FENOTCHFILT3_FENOTCHEN8_SHIFT 29 /**< Shift value for AGC_FENOTCHEN8 */
+#define _AGC_FENOTCHFILT3_FENOTCHEN8_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN8 */
+#define _AGC_FENOTCHFILT3_FENOTCHEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT3 */
+#define AGC_FENOTCHFILT3_FENOTCHEN8_DEFAULT (_AGC_FENOTCHFILT3_FENOTCHEN8_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT3 */
+
+/* Bit fields for AGC FENOTCHFILT4 */
+#define _AGC_FENOTCHFILT4_RESETVALUE 0x00000000UL /**< Default value for AGC_FENOTCHFILT4 */
+#define _AGC_FENOTCHFILT4_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHFILT4 */
+#define _AGC_FENOTCHFILT4_FENOTCHATTNSEL9_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL9 */
+#define _AGC_FENOTCHFILT4_FENOTCHATTNSEL9_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL9 */
+#define _AGC_FENOTCHFILT4_FENOTCHATTNSEL9_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT4 */
+#define AGC_FENOTCHFILT4_FENOTCHATTNSEL9_DEFAULT (_AGC_FENOTCHFILT4_FENOTCHATTNSEL9_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT4 */
+#define _AGC_FENOTCHFILT4_FENOTCHCAPCRSE9_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE9 */
+#define _AGC_FENOTCHFILT4_FENOTCHCAPCRSE9_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE9 */
+#define _AGC_FENOTCHFILT4_FENOTCHCAPCRSE9_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT4 */
+#define AGC_FENOTCHFILT4_FENOTCHCAPCRSE9_DEFAULT (_AGC_FENOTCHFILT4_FENOTCHCAPCRSE9_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT4 */
+#define _AGC_FENOTCHFILT4_FENOTCHCAPFINE9_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE9 */
+#define _AGC_FENOTCHFILT4_FENOTCHCAPFINE9_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE9 */
+#define _AGC_FENOTCHFILT4_FENOTCHCAPFINE9_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT4 */
+#define AGC_FENOTCHFILT4_FENOTCHCAPFINE9_DEFAULT (_AGC_FENOTCHFILT4_FENOTCHCAPFINE9_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT4 */
+#define AGC_FENOTCHFILT4_FENOTCHRATTNEN9 (0x1UL << 12) /**< FE notch rattn enable for index 9 */
+#define _AGC_FENOTCHFILT4_FENOTCHRATTNEN9_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN9 */
+#define _AGC_FENOTCHFILT4_FENOTCHRATTNEN9_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN9 */
+#define _AGC_FENOTCHFILT4_FENOTCHRATTNEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT4 */
+#define AGC_FENOTCHFILT4_FENOTCHRATTNEN9_DEFAULT (_AGC_FENOTCHFILT4_FENOTCHRATTNEN9_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT4 */
+#define AGC_FENOTCHFILT4_FENOTCHEN9 (0x1UL << 13) /**< FE notch enable for index 9 */
+#define _AGC_FENOTCHFILT4_FENOTCHEN9_SHIFT 13 /**< Shift value for AGC_FENOTCHEN9 */
+#define _AGC_FENOTCHFILT4_FENOTCHEN9_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN9 */
+#define _AGC_FENOTCHFILT4_FENOTCHEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT4 */
+#define AGC_FENOTCHFILT4_FENOTCHEN9_DEFAULT (_AGC_FENOTCHFILT4_FENOTCHEN9_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT4 */
+#define _AGC_FENOTCHFILT4_FENOTCHATTNSEL10_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL10 */
+#define _AGC_FENOTCHFILT4_FENOTCHATTNSEL10_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL10 */
+#define _AGC_FENOTCHFILT4_FENOTCHATTNSEL10_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT4 */
+#define AGC_FENOTCHFILT4_FENOTCHATTNSEL10_DEFAULT (_AGC_FENOTCHFILT4_FENOTCHATTNSEL10_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT4 */
+#define _AGC_FENOTCHFILT4_FENOTCHCAPCRSE10_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE10 */
+#define _AGC_FENOTCHFILT4_FENOTCHCAPCRSE10_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE10 */
+#define _AGC_FENOTCHFILT4_FENOTCHCAPCRSE10_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT4 */
+#define AGC_FENOTCHFILT4_FENOTCHCAPCRSE10_DEFAULT (_AGC_FENOTCHFILT4_FENOTCHCAPCRSE10_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT4 */
+#define _AGC_FENOTCHFILT4_FENOTCHCAPFINE10_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE10 */
+#define _AGC_FENOTCHFILT4_FENOTCHCAPFINE10_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE10 */
+#define _AGC_FENOTCHFILT4_FENOTCHCAPFINE10_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT4 */
+#define AGC_FENOTCHFILT4_FENOTCHCAPFINE10_DEFAULT (_AGC_FENOTCHFILT4_FENOTCHCAPFINE10_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT4 */
+#define AGC_FENOTCHFILT4_FENOTCHRATTNEN10 (0x1UL << 28) /**< FE notch rattn enable for index 10 */
+#define _AGC_FENOTCHFILT4_FENOTCHRATTNEN10_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN10 */
+#define _AGC_FENOTCHFILT4_FENOTCHRATTNEN10_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN10 */
+#define _AGC_FENOTCHFILT4_FENOTCHRATTNEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT4 */
+#define AGC_FENOTCHFILT4_FENOTCHRATTNEN10_DEFAULT (_AGC_FENOTCHFILT4_FENOTCHRATTNEN10_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT4 */
+#define AGC_FENOTCHFILT4_FENOTCHEN10 (0x1UL << 29) /**< FE notch enable for index 10 */
+#define _AGC_FENOTCHFILT4_FENOTCHEN10_SHIFT 29 /**< Shift value for AGC_FENOTCHEN10 */
+#define _AGC_FENOTCHFILT4_FENOTCHEN10_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN10 */
+#define _AGC_FENOTCHFILT4_FENOTCHEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT4 */
+#define AGC_FENOTCHFILT4_FENOTCHEN10_DEFAULT (_AGC_FENOTCHFILT4_FENOTCHEN10_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT4 */
+
+/* Bit fields for AGC FENOTCHFILT5 */
+#define _AGC_FENOTCHFILT5_RESETVALUE 0x00000000UL /**< Default value for AGC_FENOTCHFILT5 */
+#define _AGC_FENOTCHFILT5_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHFILT5 */
+#define _AGC_FENOTCHFILT5_FENOTCHATTNSEL11_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL11 */
+#define _AGC_FENOTCHFILT5_FENOTCHATTNSEL11_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL11 */
+#define _AGC_FENOTCHFILT5_FENOTCHATTNSEL11_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT5 */
+#define AGC_FENOTCHFILT5_FENOTCHATTNSEL11_DEFAULT (_AGC_FENOTCHFILT5_FENOTCHATTNSEL11_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT5 */
+#define _AGC_FENOTCHFILT5_FENOTCHCAPCRSE11_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE11 */
+#define _AGC_FENOTCHFILT5_FENOTCHCAPCRSE11_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE11 */
+#define _AGC_FENOTCHFILT5_FENOTCHCAPCRSE11_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT5 */
+#define AGC_FENOTCHFILT5_FENOTCHCAPCRSE11_DEFAULT (_AGC_FENOTCHFILT5_FENOTCHCAPCRSE11_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT5 */
+#define _AGC_FENOTCHFILT5_FENOTCHCAPFINE11_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE11 */
+#define _AGC_FENOTCHFILT5_FENOTCHCAPFINE11_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE11 */
+#define _AGC_FENOTCHFILT5_FENOTCHCAPFINE11_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT5 */
+#define AGC_FENOTCHFILT5_FENOTCHCAPFINE11_DEFAULT (_AGC_FENOTCHFILT5_FENOTCHCAPFINE11_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT5 */
+#define AGC_FENOTCHFILT5_FENOTCHRATTNEN11 (0x1UL << 12) /**< FE notch rattn enable for index 11 */
+#define _AGC_FENOTCHFILT5_FENOTCHRATTNEN11_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN11 */
+#define _AGC_FENOTCHFILT5_FENOTCHRATTNEN11_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN11 */
+#define _AGC_FENOTCHFILT5_FENOTCHRATTNEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT5 */
+#define AGC_FENOTCHFILT5_FENOTCHRATTNEN11_DEFAULT (_AGC_FENOTCHFILT5_FENOTCHRATTNEN11_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT5 */
+#define AGC_FENOTCHFILT5_FENOTCHEN11 (0x1UL << 13) /**< FE notch enable for index 11 */
+#define _AGC_FENOTCHFILT5_FENOTCHEN11_SHIFT 13 /**< Shift value for AGC_FENOTCHEN11 */
+#define _AGC_FENOTCHFILT5_FENOTCHEN11_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN11 */
+#define _AGC_FENOTCHFILT5_FENOTCHEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT5 */
+#define AGC_FENOTCHFILT5_FENOTCHEN11_DEFAULT (_AGC_FENOTCHFILT5_FENOTCHEN11_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT5 */
+#define _AGC_FENOTCHFILT5_FENOTCHATTNSEL12_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL12 */
+#define _AGC_FENOTCHFILT5_FENOTCHATTNSEL12_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL12 */
+#define _AGC_FENOTCHFILT5_FENOTCHATTNSEL12_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT5 */
+#define AGC_FENOTCHFILT5_FENOTCHATTNSEL12_DEFAULT (_AGC_FENOTCHFILT5_FENOTCHATTNSEL12_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT5 */
+#define _AGC_FENOTCHFILT5_FENOTCHCAPCRSE12_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE12 */
+#define _AGC_FENOTCHFILT5_FENOTCHCAPCRSE12_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE12 */
+#define _AGC_FENOTCHFILT5_FENOTCHCAPCRSE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT5 */
+#define AGC_FENOTCHFILT5_FENOTCHCAPCRSE12_DEFAULT (_AGC_FENOTCHFILT5_FENOTCHCAPCRSE12_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT5 */
+#define _AGC_FENOTCHFILT5_FENOTCHCAPFINE12_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE12 */
+#define _AGC_FENOTCHFILT5_FENOTCHCAPFINE12_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE12 */
+#define _AGC_FENOTCHFILT5_FENOTCHCAPFINE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT5 */
+#define AGC_FENOTCHFILT5_FENOTCHCAPFINE12_DEFAULT (_AGC_FENOTCHFILT5_FENOTCHCAPFINE12_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT5 */
+#define AGC_FENOTCHFILT5_FENOTCHRATTNEN12 (0x1UL << 28) /**< FE notch rattn enable for index 12 */
+#define _AGC_FENOTCHFILT5_FENOTCHRATTNEN12_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN12 */
+#define _AGC_FENOTCHFILT5_FENOTCHRATTNEN12_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN12 */
+#define _AGC_FENOTCHFILT5_FENOTCHRATTNEN12_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT5 */
+#define AGC_FENOTCHFILT5_FENOTCHRATTNEN12_DEFAULT (_AGC_FENOTCHFILT5_FENOTCHRATTNEN12_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT5 */
+#define AGC_FENOTCHFILT5_FENOTCHEN12 (0x1UL << 29) /**< FE notch enable for index 12 */
+#define _AGC_FENOTCHFILT5_FENOTCHEN12_SHIFT 29 /**< Shift value for AGC_FENOTCHEN12 */
+#define _AGC_FENOTCHFILT5_FENOTCHEN12_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN12 */
+#define _AGC_FENOTCHFILT5_FENOTCHEN12_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT5 */
+#define AGC_FENOTCHFILT5_FENOTCHEN12_DEFAULT (_AGC_FENOTCHFILT5_FENOTCHEN12_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT5 */
+
+/* Bit fields for AGC FENOTCHFILT6 */
+#define _AGC_FENOTCHFILT6_RESETVALUE 0x00000000UL /**< Default value for AGC_FENOTCHFILT6 */
+#define _AGC_FENOTCHFILT6_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHFILT6 */
+#define _AGC_FENOTCHFILT6_FENOTCHATTNSEL13_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL13 */
+#define _AGC_FENOTCHFILT6_FENOTCHATTNSEL13_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL13 */
+#define _AGC_FENOTCHFILT6_FENOTCHATTNSEL13_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT6 */
+#define AGC_FENOTCHFILT6_FENOTCHATTNSEL13_DEFAULT (_AGC_FENOTCHFILT6_FENOTCHATTNSEL13_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT6 */
+#define _AGC_FENOTCHFILT6_FENOTCHCAPCRSE13_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE13 */
+#define _AGC_FENOTCHFILT6_FENOTCHCAPCRSE13_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE13 */
+#define _AGC_FENOTCHFILT6_FENOTCHCAPCRSE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT6 */
+#define AGC_FENOTCHFILT6_FENOTCHCAPCRSE13_DEFAULT (_AGC_FENOTCHFILT6_FENOTCHCAPCRSE13_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT6 */
+#define _AGC_FENOTCHFILT6_FENOTCHCAPFINE13_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE13 */
+#define _AGC_FENOTCHFILT6_FENOTCHCAPFINE13_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE13 */
+#define _AGC_FENOTCHFILT6_FENOTCHCAPFINE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT6 */
+#define AGC_FENOTCHFILT6_FENOTCHCAPFINE13_DEFAULT (_AGC_FENOTCHFILT6_FENOTCHCAPFINE13_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT6 */
+#define AGC_FENOTCHFILT6_FENOTCHRATTNEN13 (0x1UL << 12) /**< FE notch rattn enable for index 13 */
+#define _AGC_FENOTCHFILT6_FENOTCHRATTNEN13_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN13 */
+#define _AGC_FENOTCHFILT6_FENOTCHRATTNEN13_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN13 */
+#define _AGC_FENOTCHFILT6_FENOTCHRATTNEN13_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT6 */
+#define AGC_FENOTCHFILT6_FENOTCHRATTNEN13_DEFAULT (_AGC_FENOTCHFILT6_FENOTCHRATTNEN13_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT6 */
+#define AGC_FENOTCHFILT6_FENOTCHEN13 (0x1UL << 13) /**< FE notch enable for index 13 */
+#define _AGC_FENOTCHFILT6_FENOTCHEN13_SHIFT 13 /**< Shift value for AGC_FENOTCHEN13 */
+#define _AGC_FENOTCHFILT6_FENOTCHEN13_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN13 */
+#define _AGC_FENOTCHFILT6_FENOTCHEN13_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT6 */
+#define AGC_FENOTCHFILT6_FENOTCHEN13_DEFAULT (_AGC_FENOTCHFILT6_FENOTCHEN13_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT6 */
+#define _AGC_FENOTCHFILT6_FENOTCHATTNSEL14_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL14 */
+#define _AGC_FENOTCHFILT6_FENOTCHATTNSEL14_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL14 */
+#define _AGC_FENOTCHFILT6_FENOTCHATTNSEL14_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT6 */
+#define AGC_FENOTCHFILT6_FENOTCHATTNSEL14_DEFAULT (_AGC_FENOTCHFILT6_FENOTCHATTNSEL14_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT6 */
+#define _AGC_FENOTCHFILT6_FENOTCHCAPCRSE14_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE14 */
+#define _AGC_FENOTCHFILT6_FENOTCHCAPCRSE14_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE14 */
+#define _AGC_FENOTCHFILT6_FENOTCHCAPCRSE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT6 */
+#define AGC_FENOTCHFILT6_FENOTCHCAPCRSE14_DEFAULT (_AGC_FENOTCHFILT6_FENOTCHCAPCRSE14_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT6 */
+#define _AGC_FENOTCHFILT6_FENOTCHCAPFINE14_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE14 */
+#define _AGC_FENOTCHFILT6_FENOTCHCAPFINE14_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE14 */
+#define _AGC_FENOTCHFILT6_FENOTCHCAPFINE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT6 */
+#define AGC_FENOTCHFILT6_FENOTCHCAPFINE14_DEFAULT (_AGC_FENOTCHFILT6_FENOTCHCAPFINE14_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT6 */
+#define AGC_FENOTCHFILT6_FENOTCHRATTNEN14 (0x1UL << 28) /**< FE notch rattn enable for index 14 */
+#define _AGC_FENOTCHFILT6_FENOTCHRATTNEN14_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN14 */
+#define _AGC_FENOTCHFILT6_FENOTCHRATTNEN14_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN14 */
+#define _AGC_FENOTCHFILT6_FENOTCHRATTNEN14_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT6 */
+#define AGC_FENOTCHFILT6_FENOTCHRATTNEN14_DEFAULT (_AGC_FENOTCHFILT6_FENOTCHRATTNEN14_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT6 */
+#define AGC_FENOTCHFILT6_FENOTCHEN14 (0x1UL << 29) /**< FE notch enable for index 14 */
+#define _AGC_FENOTCHFILT6_FENOTCHEN14_SHIFT 29 /**< Shift value for AGC_FENOTCHEN14 */
+#define _AGC_FENOTCHFILT6_FENOTCHEN14_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN14 */
+#define _AGC_FENOTCHFILT6_FENOTCHEN14_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT6 */
+#define AGC_FENOTCHFILT6_FENOTCHEN14_DEFAULT (_AGC_FENOTCHFILT6_FENOTCHEN14_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT6 */
+
+/* Bit fields for AGC FENOTCHFILT7 */
+#define _AGC_FENOTCHFILT7_RESETVALUE 0x20080000UL /**< Default value for AGC_FENOTCHFILT7 */
+#define _AGC_FENOTCHFILT7_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHFILT7 */
+#define _AGC_FENOTCHFILT7_FENOTCHATTNSEL15_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL15 */
+#define _AGC_FENOTCHFILT7_FENOTCHATTNSEL15_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL15 */
+#define _AGC_FENOTCHFILT7_FENOTCHATTNSEL15_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT7 */
+#define AGC_FENOTCHFILT7_FENOTCHATTNSEL15_DEFAULT (_AGC_FENOTCHFILT7_FENOTCHATTNSEL15_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT7 */
+#define _AGC_FENOTCHFILT7_FENOTCHCAPCRSE15_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE15 */
+#define _AGC_FENOTCHFILT7_FENOTCHCAPCRSE15_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE15 */
+#define _AGC_FENOTCHFILT7_FENOTCHCAPCRSE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT7 */
+#define AGC_FENOTCHFILT7_FENOTCHCAPCRSE15_DEFAULT (_AGC_FENOTCHFILT7_FENOTCHCAPCRSE15_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT7 */
+#define _AGC_FENOTCHFILT7_FENOTCHCAPFINE15_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE15 */
+#define _AGC_FENOTCHFILT7_FENOTCHCAPFINE15_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE15 */
+#define _AGC_FENOTCHFILT7_FENOTCHCAPFINE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT7 */
+#define AGC_FENOTCHFILT7_FENOTCHCAPFINE15_DEFAULT (_AGC_FENOTCHFILT7_FENOTCHCAPFINE15_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT7 */
+#define AGC_FENOTCHFILT7_FENOTCHRATTNEN15 (0x1UL << 12) /**< FE notch rattn enable for index 15 */
+#define _AGC_FENOTCHFILT7_FENOTCHRATTNEN15_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN15 */
+#define _AGC_FENOTCHFILT7_FENOTCHRATTNEN15_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN15 */
+#define _AGC_FENOTCHFILT7_FENOTCHRATTNEN15_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT7 */
+#define AGC_FENOTCHFILT7_FENOTCHRATTNEN15_DEFAULT (_AGC_FENOTCHFILT7_FENOTCHRATTNEN15_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT7 */
+#define AGC_FENOTCHFILT7_FENOTCHEN15 (0x1UL << 13) /**< FE notch enable for index 15 */
+#define _AGC_FENOTCHFILT7_FENOTCHEN15_SHIFT 13 /**< Shift value for AGC_FENOTCHEN15 */
+#define _AGC_FENOTCHFILT7_FENOTCHEN15_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN15 */
+#define _AGC_FENOTCHFILT7_FENOTCHEN15_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT7 */
+#define AGC_FENOTCHFILT7_FENOTCHEN15_DEFAULT (_AGC_FENOTCHFILT7_FENOTCHEN15_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT7 */
+#define _AGC_FENOTCHFILT7_FENOTCHATTNSEL16_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL16 */
+#define _AGC_FENOTCHFILT7_FENOTCHATTNSEL16_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL16 */
+#define _AGC_FENOTCHFILT7_FENOTCHATTNSEL16_DEFAULT 0x00000008UL /**< Mode DEFAULT for AGC_FENOTCHFILT7 */
+#define AGC_FENOTCHFILT7_FENOTCHATTNSEL16_DEFAULT (_AGC_FENOTCHFILT7_FENOTCHATTNSEL16_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT7 */
+#define _AGC_FENOTCHFILT7_FENOTCHCAPCRSE16_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE16 */
+#define _AGC_FENOTCHFILT7_FENOTCHCAPCRSE16_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE16 */
+#define _AGC_FENOTCHFILT7_FENOTCHCAPCRSE16_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT7 */
+#define AGC_FENOTCHFILT7_FENOTCHCAPCRSE16_DEFAULT (_AGC_FENOTCHFILT7_FENOTCHCAPCRSE16_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT7 */
+#define _AGC_FENOTCHFILT7_FENOTCHCAPFINE16_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE16 */
+#define _AGC_FENOTCHFILT7_FENOTCHCAPFINE16_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE16 */
+#define _AGC_FENOTCHFILT7_FENOTCHCAPFINE16_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT7 */
+#define AGC_FENOTCHFILT7_FENOTCHCAPFINE16_DEFAULT (_AGC_FENOTCHFILT7_FENOTCHCAPFINE16_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT7 */
+#define AGC_FENOTCHFILT7_FENOTCHRATTNEN16 (0x1UL << 28) /**< FE notch rattn enable for index 16 */
+#define _AGC_FENOTCHFILT7_FENOTCHRATTNEN16_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN16 */
+#define _AGC_FENOTCHFILT7_FENOTCHRATTNEN16_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN16 */
+#define _AGC_FENOTCHFILT7_FENOTCHRATTNEN16_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT7 */
+#define AGC_FENOTCHFILT7_FENOTCHRATTNEN16_DEFAULT (_AGC_FENOTCHFILT7_FENOTCHRATTNEN16_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT7 */
+#define AGC_FENOTCHFILT7_FENOTCHEN16 (0x1UL << 29) /**< FE notch enable for index 16 */
+#define _AGC_FENOTCHFILT7_FENOTCHEN16_SHIFT 29 /**< Shift value for AGC_FENOTCHEN16 */
+#define _AGC_FENOTCHFILT7_FENOTCHEN16_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN16 */
+#define _AGC_FENOTCHFILT7_FENOTCHEN16_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHFILT7 */
+#define AGC_FENOTCHFILT7_FENOTCHEN16_DEFAULT (_AGC_FENOTCHFILT7_FENOTCHEN16_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT7 */
+
+/* Bit fields for AGC FENOTCHFILT8 */
+#define _AGC_FENOTCHFILT8_RESETVALUE 0x200B200AUL /**< Default value for AGC_FENOTCHFILT8 */
+#define _AGC_FENOTCHFILT8_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHFILT8 */
+#define _AGC_FENOTCHFILT8_FENOTCHATTNSEL17_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL17 */
+#define _AGC_FENOTCHFILT8_FENOTCHATTNSEL17_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL17 */
+#define _AGC_FENOTCHFILT8_FENOTCHATTNSEL17_DEFAULT 0x0000000AUL /**< Mode DEFAULT for AGC_FENOTCHFILT8 */
+#define AGC_FENOTCHFILT8_FENOTCHATTNSEL17_DEFAULT (_AGC_FENOTCHFILT8_FENOTCHATTNSEL17_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT8 */
+#define _AGC_FENOTCHFILT8_FENOTCHCAPCRSE17_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE17 */
+#define _AGC_FENOTCHFILT8_FENOTCHCAPCRSE17_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE17 */
+#define _AGC_FENOTCHFILT8_FENOTCHCAPCRSE17_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT8 */
+#define AGC_FENOTCHFILT8_FENOTCHCAPCRSE17_DEFAULT (_AGC_FENOTCHFILT8_FENOTCHCAPCRSE17_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT8 */
+#define _AGC_FENOTCHFILT8_FENOTCHCAPFINE17_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE17 */
+#define _AGC_FENOTCHFILT8_FENOTCHCAPFINE17_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE17 */
+#define _AGC_FENOTCHFILT8_FENOTCHCAPFINE17_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT8 */
+#define AGC_FENOTCHFILT8_FENOTCHCAPFINE17_DEFAULT (_AGC_FENOTCHFILT8_FENOTCHCAPFINE17_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT8 */
+#define AGC_FENOTCHFILT8_FENOTCHRATTNEN17 (0x1UL << 12) /**< FE notch rattn enable for index 17 */
+#define _AGC_FENOTCHFILT8_FENOTCHRATTNEN17_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN17 */
+#define _AGC_FENOTCHFILT8_FENOTCHRATTNEN17_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN17 */
+#define _AGC_FENOTCHFILT8_FENOTCHRATTNEN17_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT8 */
+#define AGC_FENOTCHFILT8_FENOTCHRATTNEN17_DEFAULT (_AGC_FENOTCHFILT8_FENOTCHRATTNEN17_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT8 */
+#define AGC_FENOTCHFILT8_FENOTCHEN17 (0x1UL << 13) /**< FE notch enable for index 17 */
+#define _AGC_FENOTCHFILT8_FENOTCHEN17_SHIFT 13 /**< Shift value for AGC_FENOTCHEN17 */
+#define _AGC_FENOTCHFILT8_FENOTCHEN17_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN17 */
+#define _AGC_FENOTCHFILT8_FENOTCHEN17_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHFILT8 */
+#define AGC_FENOTCHFILT8_FENOTCHEN17_DEFAULT (_AGC_FENOTCHFILT8_FENOTCHEN17_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT8 */
+#define _AGC_FENOTCHFILT8_FENOTCHATTNSEL18_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL18 */
+#define _AGC_FENOTCHFILT8_FENOTCHATTNSEL18_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL18 */
+#define _AGC_FENOTCHFILT8_FENOTCHATTNSEL18_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_FENOTCHFILT8 */
+#define AGC_FENOTCHFILT8_FENOTCHATTNSEL18_DEFAULT (_AGC_FENOTCHFILT8_FENOTCHATTNSEL18_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT8 */
+#define _AGC_FENOTCHFILT8_FENOTCHCAPCRSE18_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE18 */
+#define _AGC_FENOTCHFILT8_FENOTCHCAPCRSE18_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE18 */
+#define _AGC_FENOTCHFILT8_FENOTCHCAPCRSE18_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT8 */
+#define AGC_FENOTCHFILT8_FENOTCHCAPCRSE18_DEFAULT (_AGC_FENOTCHFILT8_FENOTCHCAPCRSE18_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT8 */
+#define _AGC_FENOTCHFILT8_FENOTCHCAPFINE18_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE18 */
+#define _AGC_FENOTCHFILT8_FENOTCHCAPFINE18_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE18 */
+#define _AGC_FENOTCHFILT8_FENOTCHCAPFINE18_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT8 */
+#define AGC_FENOTCHFILT8_FENOTCHCAPFINE18_DEFAULT (_AGC_FENOTCHFILT8_FENOTCHCAPFINE18_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT8 */
+#define AGC_FENOTCHFILT8_FENOTCHRATTNEN18 (0x1UL << 28) /**< FE notch rattn enable for index 18 */
+#define _AGC_FENOTCHFILT8_FENOTCHRATTNEN18_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN18 */
+#define _AGC_FENOTCHFILT8_FENOTCHRATTNEN18_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN18 */
+#define _AGC_FENOTCHFILT8_FENOTCHRATTNEN18_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT8 */
+#define AGC_FENOTCHFILT8_FENOTCHRATTNEN18_DEFAULT (_AGC_FENOTCHFILT8_FENOTCHRATTNEN18_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT8 */
+#define AGC_FENOTCHFILT8_FENOTCHEN18 (0x1UL << 29) /**< FE notch enable for index 18 */
+#define _AGC_FENOTCHFILT8_FENOTCHEN18_SHIFT 29 /**< Shift value for AGC_FENOTCHEN18 */
+#define _AGC_FENOTCHFILT8_FENOTCHEN18_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN18 */
+#define _AGC_FENOTCHFILT8_FENOTCHEN18_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHFILT8 */
+#define AGC_FENOTCHFILT8_FENOTCHEN18_DEFAULT (_AGC_FENOTCHFILT8_FENOTCHEN18_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT8 */
+
+/* Bit fields for AGC FENOTCHFILT9 */
+#define _AGC_FENOTCHFILT9_RESETVALUE 0x200B200BUL /**< Default value for AGC_FENOTCHFILT9 */
+#define _AGC_FENOTCHFILT9_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHFILT9 */
+#define _AGC_FENOTCHFILT9_FENOTCHATTNSEL19_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL19 */
+#define _AGC_FENOTCHFILT9_FENOTCHATTNSEL19_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL19 */
+#define _AGC_FENOTCHFILT9_FENOTCHATTNSEL19_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_FENOTCHFILT9 */
+#define AGC_FENOTCHFILT9_FENOTCHATTNSEL19_DEFAULT (_AGC_FENOTCHFILT9_FENOTCHATTNSEL19_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT9 */
+#define _AGC_FENOTCHFILT9_FENOTCHCAPCRSE19_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE19 */
+#define _AGC_FENOTCHFILT9_FENOTCHCAPCRSE19_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE19 */
+#define _AGC_FENOTCHFILT9_FENOTCHCAPCRSE19_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT9 */
+#define AGC_FENOTCHFILT9_FENOTCHCAPCRSE19_DEFAULT (_AGC_FENOTCHFILT9_FENOTCHCAPCRSE19_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT9 */
+#define _AGC_FENOTCHFILT9_FENOTCHCAPFINE19_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE19 */
+#define _AGC_FENOTCHFILT9_FENOTCHCAPFINE19_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE19 */
+#define _AGC_FENOTCHFILT9_FENOTCHCAPFINE19_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT9 */
+#define AGC_FENOTCHFILT9_FENOTCHCAPFINE19_DEFAULT (_AGC_FENOTCHFILT9_FENOTCHCAPFINE19_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT9 */
+#define AGC_FENOTCHFILT9_FENOTCHRATTNEN19 (0x1UL << 12) /**< FE notch rattn enable for index 19 */
+#define _AGC_FENOTCHFILT9_FENOTCHRATTNEN19_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN19 */
+#define _AGC_FENOTCHFILT9_FENOTCHRATTNEN19_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN19 */
+#define _AGC_FENOTCHFILT9_FENOTCHRATTNEN19_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT9 */
+#define AGC_FENOTCHFILT9_FENOTCHRATTNEN19_DEFAULT (_AGC_FENOTCHFILT9_FENOTCHRATTNEN19_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT9 */
+#define AGC_FENOTCHFILT9_FENOTCHEN19 (0x1UL << 13) /**< FE notch enable for index 19 */
+#define _AGC_FENOTCHFILT9_FENOTCHEN19_SHIFT 13 /**< Shift value for AGC_FENOTCHEN19 */
+#define _AGC_FENOTCHFILT9_FENOTCHEN19_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN19 */
+#define _AGC_FENOTCHFILT9_FENOTCHEN19_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHFILT9 */
+#define AGC_FENOTCHFILT9_FENOTCHEN19_DEFAULT (_AGC_FENOTCHFILT9_FENOTCHEN19_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT9 */
+#define _AGC_FENOTCHFILT9_FENOTCHATTNSEL20_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL20 */
+#define _AGC_FENOTCHFILT9_FENOTCHATTNSEL20_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL20 */
+#define _AGC_FENOTCHFILT9_FENOTCHATTNSEL20_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_FENOTCHFILT9 */
+#define AGC_FENOTCHFILT9_FENOTCHATTNSEL20_DEFAULT (_AGC_FENOTCHFILT9_FENOTCHATTNSEL20_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT9 */
+#define _AGC_FENOTCHFILT9_FENOTCHCAPCRSE20_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE20 */
+#define _AGC_FENOTCHFILT9_FENOTCHCAPCRSE20_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE20 */
+#define _AGC_FENOTCHFILT9_FENOTCHCAPCRSE20_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT9 */
+#define AGC_FENOTCHFILT9_FENOTCHCAPCRSE20_DEFAULT (_AGC_FENOTCHFILT9_FENOTCHCAPCRSE20_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT9 */
+#define _AGC_FENOTCHFILT9_FENOTCHCAPFINE20_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE20 */
+#define _AGC_FENOTCHFILT9_FENOTCHCAPFINE20_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE20 */
+#define _AGC_FENOTCHFILT9_FENOTCHCAPFINE20_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT9 */
+#define AGC_FENOTCHFILT9_FENOTCHCAPFINE20_DEFAULT (_AGC_FENOTCHFILT9_FENOTCHCAPFINE20_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT9 */
+#define AGC_FENOTCHFILT9_FENOTCHRATTNEN20 (0x1UL << 28) /**< FE notch rattn enable for index 20 */
+#define _AGC_FENOTCHFILT9_FENOTCHRATTNEN20_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN20 */
+#define _AGC_FENOTCHFILT9_FENOTCHRATTNEN20_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN20 */
+#define _AGC_FENOTCHFILT9_FENOTCHRATTNEN20_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT9 */
+#define AGC_FENOTCHFILT9_FENOTCHRATTNEN20_DEFAULT (_AGC_FENOTCHFILT9_FENOTCHRATTNEN20_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT9 */
+#define AGC_FENOTCHFILT9_FENOTCHEN20 (0x1UL << 29) /**< FE notch enable for index 20 */
+#define _AGC_FENOTCHFILT9_FENOTCHEN20_SHIFT 29 /**< Shift value for AGC_FENOTCHEN20 */
+#define _AGC_FENOTCHFILT9_FENOTCHEN20_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN20 */
+#define _AGC_FENOTCHFILT9_FENOTCHEN20_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHFILT9 */
+#define AGC_FENOTCHFILT9_FENOTCHEN20_DEFAULT (_AGC_FENOTCHFILT9_FENOTCHEN20_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT9 */
+
+/* Bit fields for AGC FENOTCHFILT10 */
+#define _AGC_FENOTCHFILT10_RESETVALUE 0x200B200BUL /**< Default value for AGC_FENOTCHFILT10 */
+#define _AGC_FENOTCHFILT10_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHFILT10 */
+#define _AGC_FENOTCHFILT10_FENOTCHATTNSEL21_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL21 */
+#define _AGC_FENOTCHFILT10_FENOTCHATTNSEL21_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL21 */
+#define _AGC_FENOTCHFILT10_FENOTCHATTNSEL21_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_FENOTCHFILT10 */
+#define AGC_FENOTCHFILT10_FENOTCHATTNSEL21_DEFAULT (_AGC_FENOTCHFILT10_FENOTCHATTNSEL21_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT10 */
+#define _AGC_FENOTCHFILT10_FENOTCHCAPCRSE21_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE21 */
+#define _AGC_FENOTCHFILT10_FENOTCHCAPCRSE21_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE21 */
+#define _AGC_FENOTCHFILT10_FENOTCHCAPCRSE21_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT10 */
+#define AGC_FENOTCHFILT10_FENOTCHCAPCRSE21_DEFAULT (_AGC_FENOTCHFILT10_FENOTCHCAPCRSE21_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT10 */
+#define _AGC_FENOTCHFILT10_FENOTCHCAPFINE21_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE21 */
+#define _AGC_FENOTCHFILT10_FENOTCHCAPFINE21_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE21 */
+#define _AGC_FENOTCHFILT10_FENOTCHCAPFINE21_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT10 */
+#define AGC_FENOTCHFILT10_FENOTCHCAPFINE21_DEFAULT (_AGC_FENOTCHFILT10_FENOTCHCAPFINE21_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT10 */
+#define AGC_FENOTCHFILT10_FENOTCHRATTNEN21 (0x1UL << 12) /**< FE notch rattn enable for index 21 */
+#define _AGC_FENOTCHFILT10_FENOTCHRATTNEN21_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN21 */
+#define _AGC_FENOTCHFILT10_FENOTCHRATTNEN21_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN21 */
+#define _AGC_FENOTCHFILT10_FENOTCHRATTNEN21_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT10 */
+#define AGC_FENOTCHFILT10_FENOTCHRATTNEN21_DEFAULT (_AGC_FENOTCHFILT10_FENOTCHRATTNEN21_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT10 */
+#define AGC_FENOTCHFILT10_FENOTCHEN21 (0x1UL << 13) /**< FE notch enable for index 21 */
+#define _AGC_FENOTCHFILT10_FENOTCHEN21_SHIFT 13 /**< Shift value for AGC_FENOTCHEN21 */
+#define _AGC_FENOTCHFILT10_FENOTCHEN21_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN21 */
+#define _AGC_FENOTCHFILT10_FENOTCHEN21_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHFILT10 */
+#define AGC_FENOTCHFILT10_FENOTCHEN21_DEFAULT (_AGC_FENOTCHFILT10_FENOTCHEN21_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT10 */
+#define _AGC_FENOTCHFILT10_FENOTCHATTNSEL22_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL22 */
+#define _AGC_FENOTCHFILT10_FENOTCHATTNSEL22_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL22 */
+#define _AGC_FENOTCHFILT10_FENOTCHATTNSEL22_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_FENOTCHFILT10 */
+#define AGC_FENOTCHFILT10_FENOTCHATTNSEL22_DEFAULT (_AGC_FENOTCHFILT10_FENOTCHATTNSEL22_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT10 */
+#define _AGC_FENOTCHFILT10_FENOTCHCAPCRSE22_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE22 */
+#define _AGC_FENOTCHFILT10_FENOTCHCAPCRSE22_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE22 */
+#define _AGC_FENOTCHFILT10_FENOTCHCAPCRSE22_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT10 */
+#define AGC_FENOTCHFILT10_FENOTCHCAPCRSE22_DEFAULT (_AGC_FENOTCHFILT10_FENOTCHCAPCRSE22_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT10 */
+#define _AGC_FENOTCHFILT10_FENOTCHCAPFINE22_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE22 */
+#define _AGC_FENOTCHFILT10_FENOTCHCAPFINE22_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE22 */
+#define _AGC_FENOTCHFILT10_FENOTCHCAPFINE22_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT10 */
+#define AGC_FENOTCHFILT10_FENOTCHCAPFINE22_DEFAULT (_AGC_FENOTCHFILT10_FENOTCHCAPFINE22_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT10 */
+#define AGC_FENOTCHFILT10_FENOTCHRATTNEN22 (0x1UL << 28) /**< FE notch rattn enable for index 22 */
+#define _AGC_FENOTCHFILT10_FENOTCHRATTNEN22_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN22 */
+#define _AGC_FENOTCHFILT10_FENOTCHRATTNEN22_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN22 */
+#define _AGC_FENOTCHFILT10_FENOTCHRATTNEN22_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT10 */
+#define AGC_FENOTCHFILT10_FENOTCHRATTNEN22_DEFAULT (_AGC_FENOTCHFILT10_FENOTCHRATTNEN22_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT10 */
+#define AGC_FENOTCHFILT10_FENOTCHEN22 (0x1UL << 29) /**< FE notch enable for index 22 */
+#define _AGC_FENOTCHFILT10_FENOTCHEN22_SHIFT 29 /**< Shift value for AGC_FENOTCHEN22 */
+#define _AGC_FENOTCHFILT10_FENOTCHEN22_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN22 */
+#define _AGC_FENOTCHFILT10_FENOTCHEN22_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHFILT10 */
+#define AGC_FENOTCHFILT10_FENOTCHEN22_DEFAULT (_AGC_FENOTCHFILT10_FENOTCHEN22_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT10 */
+
+/* Bit fields for AGC FENOTCHFILT11 */
+#define _AGC_FENOTCHFILT11_RESETVALUE 0x200B200BUL /**< Default value for AGC_FENOTCHFILT11 */
+#define _AGC_FENOTCHFILT11_MASK 0x3FFF3FFFUL /**< Mask for AGC_FENOTCHFILT11 */
+#define _AGC_FENOTCHFILT11_FENOTCHATTNSEL23_SHIFT 0 /**< Shift value for AGC_FENOTCHATTNSEL23 */
+#define _AGC_FENOTCHFILT11_FENOTCHATTNSEL23_MASK 0xFUL /**< Bit mask for AGC_FENOTCHATTNSEL23 */
+#define _AGC_FENOTCHFILT11_FENOTCHATTNSEL23_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_FENOTCHFILT11 */
+#define AGC_FENOTCHFILT11_FENOTCHATTNSEL23_DEFAULT (_AGC_FENOTCHFILT11_FENOTCHATTNSEL23_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT11 */
+#define _AGC_FENOTCHFILT11_FENOTCHCAPCRSE23_SHIFT 4 /**< Shift value for AGC_FENOTCHCAPCRSE23 */
+#define _AGC_FENOTCHFILT11_FENOTCHCAPCRSE23_MASK 0xF0UL /**< Bit mask for AGC_FENOTCHCAPCRSE23 */
+#define _AGC_FENOTCHFILT11_FENOTCHCAPCRSE23_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT11 */
+#define AGC_FENOTCHFILT11_FENOTCHCAPCRSE23_DEFAULT (_AGC_FENOTCHFILT11_FENOTCHCAPCRSE23_DEFAULT << 4) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT11 */
+#define _AGC_FENOTCHFILT11_FENOTCHCAPFINE23_SHIFT 8 /**< Shift value for AGC_FENOTCHCAPFINE23 */
+#define _AGC_FENOTCHFILT11_FENOTCHCAPFINE23_MASK 0xF00UL /**< Bit mask for AGC_FENOTCHCAPFINE23 */
+#define _AGC_FENOTCHFILT11_FENOTCHCAPFINE23_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT11 */
+#define AGC_FENOTCHFILT11_FENOTCHCAPFINE23_DEFAULT (_AGC_FENOTCHFILT11_FENOTCHCAPFINE23_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT11 */
+#define AGC_FENOTCHFILT11_FENOTCHRATTNEN23 (0x1UL << 12) /**< FE notch rattn enable for index 23 */
+#define _AGC_FENOTCHFILT11_FENOTCHRATTNEN23_SHIFT 12 /**< Shift value for AGC_FENOTCHRATTNEN23 */
+#define _AGC_FENOTCHFILT11_FENOTCHRATTNEN23_MASK 0x1000UL /**< Bit mask for AGC_FENOTCHRATTNEN23 */
+#define _AGC_FENOTCHFILT11_FENOTCHRATTNEN23_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT11 */
+#define AGC_FENOTCHFILT11_FENOTCHRATTNEN23_DEFAULT (_AGC_FENOTCHFILT11_FENOTCHRATTNEN23_DEFAULT << 12) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT11 */
+#define AGC_FENOTCHFILT11_FENOTCHEN23 (0x1UL << 13) /**< FE notch enable for index 23 */
+#define _AGC_FENOTCHFILT11_FENOTCHEN23_SHIFT 13 /**< Shift value for AGC_FENOTCHEN23 */
+#define _AGC_FENOTCHFILT11_FENOTCHEN23_MASK 0x2000UL /**< Bit mask for AGC_FENOTCHEN23 */
+#define _AGC_FENOTCHFILT11_FENOTCHEN23_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHFILT11 */
+#define AGC_FENOTCHFILT11_FENOTCHEN23_DEFAULT (_AGC_FENOTCHFILT11_FENOTCHEN23_DEFAULT << 13) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT11 */
+#define _AGC_FENOTCHFILT11_FENOTCHATTNSEL24_SHIFT 16 /**< Shift value for AGC_FENOTCHATTNSEL24 */
+#define _AGC_FENOTCHFILT11_FENOTCHATTNSEL24_MASK 0xF0000UL /**< Bit mask for AGC_FENOTCHATTNSEL24 */
+#define _AGC_FENOTCHFILT11_FENOTCHATTNSEL24_DEFAULT 0x0000000BUL /**< Mode DEFAULT for AGC_FENOTCHFILT11 */
+#define AGC_FENOTCHFILT11_FENOTCHATTNSEL24_DEFAULT (_AGC_FENOTCHFILT11_FENOTCHATTNSEL24_DEFAULT << 16) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT11 */
+#define _AGC_FENOTCHFILT11_FENOTCHCAPCRSE24_SHIFT 20 /**< Shift value for AGC_FENOTCHCAPCRSE24 */
+#define _AGC_FENOTCHFILT11_FENOTCHCAPCRSE24_MASK 0xF00000UL /**< Bit mask for AGC_FENOTCHCAPCRSE24 */
+#define _AGC_FENOTCHFILT11_FENOTCHCAPCRSE24_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT11 */
+#define AGC_FENOTCHFILT11_FENOTCHCAPCRSE24_DEFAULT (_AGC_FENOTCHFILT11_FENOTCHCAPCRSE24_DEFAULT << 20) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT11 */
+#define _AGC_FENOTCHFILT11_FENOTCHCAPFINE24_SHIFT 24 /**< Shift value for AGC_FENOTCHCAPFINE24 */
+#define _AGC_FENOTCHFILT11_FENOTCHCAPFINE24_MASK 0xF000000UL /**< Bit mask for AGC_FENOTCHCAPFINE24 */
+#define _AGC_FENOTCHFILT11_FENOTCHCAPFINE24_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT11 */
+#define AGC_FENOTCHFILT11_FENOTCHCAPFINE24_DEFAULT (_AGC_FENOTCHFILT11_FENOTCHCAPFINE24_DEFAULT << 24) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT11 */
+#define AGC_FENOTCHFILT11_FENOTCHRATTNEN24 (0x1UL << 28) /**< FE notch rattn enable for index 24 */
+#define _AGC_FENOTCHFILT11_FENOTCHRATTNEN24_SHIFT 28 /**< Shift value for AGC_FENOTCHRATTNEN24 */
+#define _AGC_FENOTCHFILT11_FENOTCHRATTNEN24_MASK 0x10000000UL /**< Bit mask for AGC_FENOTCHRATTNEN24 */
+#define _AGC_FENOTCHFILT11_FENOTCHRATTNEN24_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_FENOTCHFILT11 */
+#define AGC_FENOTCHFILT11_FENOTCHRATTNEN24_DEFAULT (_AGC_FENOTCHFILT11_FENOTCHRATTNEN24_DEFAULT << 28) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT11 */
+#define AGC_FENOTCHFILT11_FENOTCHEN24 (0x1UL << 29) /**< FE notch enable for index 24 */
+#define _AGC_FENOTCHFILT11_FENOTCHEN24_SHIFT 29 /**< Shift value for AGC_FENOTCHEN24 */
+#define _AGC_FENOTCHFILT11_FENOTCHEN24_MASK 0x20000000UL /**< Bit mask for AGC_FENOTCHEN24 */
+#define _AGC_FENOTCHFILT11_FENOTCHEN24_DEFAULT 0x00000001UL /**< Mode DEFAULT for AGC_FENOTCHFILT11 */
+#define AGC_FENOTCHFILT11_FENOTCHEN24_DEFAULT (_AGC_FENOTCHFILT11_FENOTCHEN24_DEFAULT << 29) /**< Shifted mode DEFAULT for AGC_FENOTCHFILT11 */
+
+/* Bit fields for AGC CCADEBUG */
+#define _AGC_CCADEBUG_RESETVALUE 0x00000000UL /**< Default value for AGC_CCADEBUG */
+#define _AGC_CCADEBUG_MASK 0x000003FFUL /**< Mask for AGC_CCADEBUG */
+#define _AGC_CCADEBUG_DEBUGCCARSSI_SHIFT 0 /**< Shift value for AGC_DEBUGCCARSSI */
+#define _AGC_CCADEBUG_DEBUGCCARSSI_MASK 0xFFUL /**< Bit mask for AGC_DEBUGCCARSSI */
+#define _AGC_CCADEBUG_DEBUGCCARSSI_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CCADEBUG */
+#define AGC_CCADEBUG_DEBUGCCARSSI_DEFAULT (_AGC_CCADEBUG_DEBUGCCARSSI_DEFAULT << 0) /**< Shifted mode DEFAULT for AGC_CCADEBUG */
+#define AGC_CCADEBUG_DEBUGCCAM1 (0x1UL << 8) /**< Mode 1 Clear Channel Assessment */
+#define _AGC_CCADEBUG_DEBUGCCAM1_SHIFT 8 /**< Shift value for AGC_DEBUGCCAM1 */
+#define _AGC_CCADEBUG_DEBUGCCAM1_MASK 0x100UL /**< Bit mask for AGC_DEBUGCCAM1 */
+#define _AGC_CCADEBUG_DEBUGCCAM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CCADEBUG */
+#define AGC_CCADEBUG_DEBUGCCAM1_DEFAULT (_AGC_CCADEBUG_DEBUGCCAM1_DEFAULT << 8) /**< Shifted mode DEFAULT for AGC_CCADEBUG */
+#define AGC_CCADEBUG_DEBUGCCASIGDET (0x1UL << 9) /**< Signal detector Clear Channel Assessment */
+#define _AGC_CCADEBUG_DEBUGCCASIGDET_SHIFT 9 /**< Shift value for AGC_DEBUGCCASIGDET */
+#define _AGC_CCADEBUG_DEBUGCCASIGDET_MASK 0x200UL /**< Bit mask for AGC_DEBUGCCASIGDET */
+#define _AGC_CCADEBUG_DEBUGCCASIGDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for AGC_CCADEBUG */
+#define AGC_CCADEBUG_DEBUGCCASIGDET_DEFAULT (_AGC_CCADEBUG_DEBUGCCASIGDET_DEFAULT << 9) /**< Shifted mode DEFAULT for AGC_CCADEBUG */
+
+/** @} End of group EFR32MG24_AGC_BitFields */
+/** @} End of group EFR32MG24_AGC */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_AGC_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_amuxcp.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_amuxcp.h
new file mode 100644
index 00000000..83709fe4
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_amuxcp.h
@@ -0,0 +1,261 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 AMUXCP register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_AMUXCP_H
+#define EFR32MG24_AMUXCP_H
+#define AMUXCP_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_AMUXCP AMUXCP
+ * @{
+ * @brief EFR32MG24 AMUXCP Register Declaration.
+ *****************************************************************************/
+
+/** AMUXCP Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IPVERSION */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+ __IOM uint32_t CTRL; /**< Control */
+ __IM uint32_t STATUS; /**< Status */
+ __IOM uint32_t TEST; /**< Test */
+ __IOM uint32_t TRIM; /**< Trim */
+ uint32_t RESERVED1[1018U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IPVERSION */
+ uint32_t RESERVED2[1U]; /**< Reserved for future use */
+ __IOM uint32_t CTRL_SET; /**< Control */
+ __IM uint32_t STATUS_SET; /**< Status */
+ __IOM uint32_t TEST_SET; /**< Test */
+ __IOM uint32_t TRIM_SET; /**< Trim */
+ uint32_t RESERVED3[1018U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IPVERSION */
+ uint32_t RESERVED4[1U]; /**< Reserved for future use */
+ __IOM uint32_t CTRL_CLR; /**< Control */
+ __IM uint32_t STATUS_CLR; /**< Status */
+ __IOM uint32_t TEST_CLR; /**< Test */
+ __IOM uint32_t TRIM_CLR; /**< Trim */
+ uint32_t RESERVED5[1018U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IPVERSION */
+ uint32_t RESERVED6[1U]; /**< Reserved for future use */
+ __IOM uint32_t CTRL_TGL; /**< Control */
+ __IM uint32_t STATUS_TGL; /**< Status */
+ __IOM uint32_t TEST_TGL; /**< Test */
+ __IOM uint32_t TRIM_TGL; /**< Trim */
+} AMUXCP_TypeDef;
+/** @} End of group EFR32MG24_AMUXCP */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_AMUXCP
+ * @{
+ * @defgroup EFR32MG24_AMUXCP_BitFields AMUXCP Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for AMUXCP IPVERSION */
+#define _AMUXCP_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for AMUXCP_IPVERSION */
+#define _AMUXCP_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for AMUXCP_IPVERSION */
+#define _AMUXCP_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for AMUXCP_IPVERSION */
+#define _AMUXCP_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for AMUXCP_IPVERSION */
+#define _AMUXCP_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for AMUXCP_IPVERSION */
+#define AMUXCP_IPVERSION_IPVERSION_DEFAULT (_AMUXCP_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for AMUXCP_IPVERSION */
+
+/* Bit fields for AMUXCP CTRL */
+#define _AMUXCP_CTRL_RESETVALUE 0x00000000UL /**< Default value for AMUXCP_CTRL */
+#define _AMUXCP_CTRL_MASK 0x00000033UL /**< Mask for AMUXCP_CTRL */
+#define AMUXCP_CTRL_FORCEHP (0x1UL << 0) /**< Force High Power */
+#define _AMUXCP_CTRL_FORCEHP_SHIFT 0 /**< Shift value for AMUXCP_FORCEHP */
+#define _AMUXCP_CTRL_FORCEHP_MASK 0x1UL /**< Bit mask for AMUXCP_FORCEHP */
+#define _AMUXCP_CTRL_FORCEHP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_CTRL */
+#define AMUXCP_CTRL_FORCEHP_DEFAULT (_AMUXCP_CTRL_FORCEHP_DEFAULT << 0) /**< Shifted mode DEFAULT for AMUXCP_CTRL */
+#define AMUXCP_CTRL_FORCELP (0x1UL << 1) /**< Force Low Power */
+#define _AMUXCP_CTRL_FORCELP_SHIFT 1 /**< Shift value for AMUXCP_FORCELP */
+#define _AMUXCP_CTRL_FORCELP_MASK 0x2UL /**< Bit mask for AMUXCP_FORCELP */
+#define _AMUXCP_CTRL_FORCELP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_CTRL */
+#define AMUXCP_CTRL_FORCELP_DEFAULT (_AMUXCP_CTRL_FORCELP_DEFAULT << 1) /**< Shifted mode DEFAULT for AMUXCP_CTRL */
+#define AMUXCP_CTRL_FORCERUN (0x1UL << 4) /**< Force run */
+#define _AMUXCP_CTRL_FORCERUN_SHIFT 4 /**< Shift value for AMUXCP_FORCERUN */
+#define _AMUXCP_CTRL_FORCERUN_MASK 0x10UL /**< Bit mask for AMUXCP_FORCERUN */
+#define _AMUXCP_CTRL_FORCERUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_CTRL */
+#define AMUXCP_CTRL_FORCERUN_DEFAULT (_AMUXCP_CTRL_FORCERUN_DEFAULT << 4) /**< Shifted mode DEFAULT for AMUXCP_CTRL */
+#define AMUXCP_CTRL_FORCESTOP (0x1UL << 5) /**< Force stop */
+#define _AMUXCP_CTRL_FORCESTOP_SHIFT 5 /**< Shift value for AMUXCP_FORCESTOP */
+#define _AMUXCP_CTRL_FORCESTOP_MASK 0x20UL /**< Bit mask for AMUXCP_FORCESTOP */
+#define _AMUXCP_CTRL_FORCESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_CTRL */
+#define AMUXCP_CTRL_FORCESTOP_DEFAULT (_AMUXCP_CTRL_FORCESTOP_DEFAULT << 5) /**< Shifted mode DEFAULT for AMUXCP_CTRL */
+
+/* Bit fields for AMUXCP STATUS */
+#define _AMUXCP_STATUS_RESETVALUE 0x00000000UL /**< Default value for AMUXCP_STATUS */
+#define _AMUXCP_STATUS_MASK 0x00000003UL /**< Mask for AMUXCP_STATUS */
+#define AMUXCP_STATUS_RUN (0x1UL << 0) /**< running */
+#define _AMUXCP_STATUS_RUN_SHIFT 0 /**< Shift value for AMUXCP_RUN */
+#define _AMUXCP_STATUS_RUN_MASK 0x1UL /**< Bit mask for AMUXCP_RUN */
+#define _AMUXCP_STATUS_RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_STATUS */
+#define AMUXCP_STATUS_RUN_DEFAULT (_AMUXCP_STATUS_RUN_DEFAULT << 0) /**< Shifted mode DEFAULT for AMUXCP_STATUS */
+#define AMUXCP_STATUS_HICAP (0x1UL << 1) /**< high cap */
+#define _AMUXCP_STATUS_HICAP_SHIFT 1 /**< Shift value for AMUXCP_HICAP */
+#define _AMUXCP_STATUS_HICAP_MASK 0x2UL /**< Bit mask for AMUXCP_HICAP */
+#define _AMUXCP_STATUS_HICAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_STATUS */
+#define AMUXCP_STATUS_HICAP_DEFAULT (_AMUXCP_STATUS_HICAP_DEFAULT << 1) /**< Shifted mode DEFAULT for AMUXCP_STATUS */
+
+/* Bit fields for AMUXCP TEST */
+#define _AMUXCP_TEST_RESETVALUE 0x00000000UL /**< Default value for AMUXCP_TEST */
+#define _AMUXCP_TEST_MASK 0x80003313UL /**< Mask for AMUXCP_TEST */
+#define AMUXCP_TEST_SYNCCLK (0x1UL << 0) /**< Sync Clock */
+#define _AMUXCP_TEST_SYNCCLK_SHIFT 0 /**< Shift value for AMUXCP_SYNCCLK */
+#define _AMUXCP_TEST_SYNCCLK_MASK 0x1UL /**< Bit mask for AMUXCP_SYNCCLK */
+#define _AMUXCP_TEST_SYNCCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */
+#define AMUXCP_TEST_SYNCCLK_DEFAULT (_AMUXCP_TEST_SYNCCLK_DEFAULT << 0) /**< Shifted mode DEFAULT for AMUXCP_TEST */
+#define AMUXCP_TEST_SYNCMODE (0x1UL << 1) /**< Sync Mode */
+#define _AMUXCP_TEST_SYNCMODE_SHIFT 1 /**< Shift value for AMUXCP_SYNCMODE */
+#define _AMUXCP_TEST_SYNCMODE_MASK 0x2UL /**< Bit mask for AMUXCP_SYNCMODE */
+#define _AMUXCP_TEST_SYNCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */
+#define AMUXCP_TEST_SYNCMODE_DEFAULT (_AMUXCP_TEST_SYNCMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for AMUXCP_TEST */
+#define AMUXCP_TEST_FORCEREQUEST (0x1UL << 4) /**< Force Request */
+#define _AMUXCP_TEST_FORCEREQUEST_SHIFT 4 /**< Shift value for AMUXCP_FORCEREQUEST */
+#define _AMUXCP_TEST_FORCEREQUEST_MASK 0x10UL /**< Bit mask for AMUXCP_FORCEREQUEST */
+#define _AMUXCP_TEST_FORCEREQUEST_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */
+#define AMUXCP_TEST_FORCEREQUEST_DEFAULT (_AMUXCP_TEST_FORCEREQUEST_DEFAULT << 4) /**< Shifted mode DEFAULT for AMUXCP_TEST */
+#define AMUXCP_TEST_FORCEHICAP (0x1UL << 8) /**< Force high capacitance driver */
+#define _AMUXCP_TEST_FORCEHICAP_SHIFT 8 /**< Shift value for AMUXCP_FORCEHICAP */
+#define _AMUXCP_TEST_FORCEHICAP_MASK 0x100UL /**< Bit mask for AMUXCP_FORCEHICAP */
+#define _AMUXCP_TEST_FORCEHICAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */
+#define AMUXCP_TEST_FORCEHICAP_DEFAULT (_AMUXCP_TEST_FORCEHICAP_DEFAULT << 8) /**< Shifted mode DEFAULT for AMUXCP_TEST */
+#define AMUXCP_TEST_FORCELOCAP (0x1UL << 9) /**< Force low capacitance driver */
+#define _AMUXCP_TEST_FORCELOCAP_SHIFT 9 /**< Shift value for AMUXCP_FORCELOCAP */
+#define _AMUXCP_TEST_FORCELOCAP_MASK 0x200UL /**< Bit mask for AMUXCP_FORCELOCAP */
+#define _AMUXCP_TEST_FORCELOCAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */
+#define AMUXCP_TEST_FORCELOCAP_DEFAULT (_AMUXCP_TEST_FORCELOCAP_DEFAULT << 9) /**< Shifted mode DEFAULT for AMUXCP_TEST */
+#define AMUXCP_TEST_FORCEBOOSTON (0x1UL << 12) /**< Force Boost On */
+#define _AMUXCP_TEST_FORCEBOOSTON_SHIFT 12 /**< Shift value for AMUXCP_FORCEBOOSTON */
+#define _AMUXCP_TEST_FORCEBOOSTON_MASK 0x1000UL /**< Bit mask for AMUXCP_FORCEBOOSTON */
+#define _AMUXCP_TEST_FORCEBOOSTON_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */
+#define AMUXCP_TEST_FORCEBOOSTON_DEFAULT (_AMUXCP_TEST_FORCEBOOSTON_DEFAULT << 12) /**< Shifted mode DEFAULT for AMUXCP_TEST */
+#define AMUXCP_TEST_FORCEBOOSTOFF (0x1UL << 13) /**< Force Boost Off */
+#define _AMUXCP_TEST_FORCEBOOSTOFF_SHIFT 13 /**< Shift value for AMUXCP_FORCEBOOSTOFF */
+#define _AMUXCP_TEST_FORCEBOOSTOFF_MASK 0x2000UL /**< Bit mask for AMUXCP_FORCEBOOSTOFF */
+#define _AMUXCP_TEST_FORCEBOOSTOFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */
+#define AMUXCP_TEST_FORCEBOOSTOFF_DEFAULT (_AMUXCP_TEST_FORCEBOOSTOFF_DEFAULT << 13) /**< Shifted mode DEFAULT for AMUXCP_TEST */
+#define AMUXCP_TEST_STATUSEN (0x1UL << 31) /**< Enable write to status bits */
+#define _AMUXCP_TEST_STATUSEN_SHIFT 31 /**< Shift value for AMUXCP_STATUSEN */
+#define _AMUXCP_TEST_STATUSEN_MASK 0x80000000UL /**< Bit mask for AMUXCP_STATUSEN */
+#define _AMUXCP_TEST_STATUSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TEST */
+#define AMUXCP_TEST_STATUSEN_DEFAULT (_AMUXCP_TEST_STATUSEN_DEFAULT << 31) /**< Shifted mode DEFAULT for AMUXCP_TEST */
+
+/* Bit fields for AMUXCP TRIM */
+#define _AMUXCP_TRIM_RESETVALUE 0x77E44AB1UL /**< Default value for AMUXCP_TRIM */
+#define _AMUXCP_TRIM_MASK 0x77FFEFFFUL /**< Mask for AMUXCP_TRIM */
+#define _AMUXCP_TRIM_WARMUPTIME_SHIFT 0 /**< Shift value for AMUXCP_WARMUPTIME */
+#define _AMUXCP_TRIM_WARMUPTIME_MASK 0x3UL /**< Bit mask for AMUXCP_WARMUPTIME */
+#define _AMUXCP_TRIM_WARMUPTIME_DEFAULT 0x00000001UL /**< Mode DEFAULT for AMUXCP_TRIM */
+#define _AMUXCP_TRIM_WARMUPTIME_WUCYCLES72 0x00000000UL /**< Mode WUCYCLES72 for AMUXCP_TRIM */
+#define _AMUXCP_TRIM_WARMUPTIME_WUCYCLES96 0x00000001UL /**< Mode WUCYCLES96 for AMUXCP_TRIM */
+#define _AMUXCP_TRIM_WARMUPTIME_WUCYCLES128 0x00000002UL /**< Mode WUCYCLES128 for AMUXCP_TRIM */
+#define _AMUXCP_TRIM_WARMUPTIME_WUCYCLES160 0x00000003UL /**< Mode WUCYCLES160 for AMUXCP_TRIM */
+#define AMUXCP_TRIM_WARMUPTIME_DEFAULT (_AMUXCP_TRIM_WARMUPTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
+#define AMUXCP_TRIM_WARMUPTIME_WUCYCLES72 (_AMUXCP_TRIM_WARMUPTIME_WUCYCLES72 << 0) /**< Shifted mode WUCYCLES72 for AMUXCP_TRIM */
+#define AMUXCP_TRIM_WARMUPTIME_WUCYCLES96 (_AMUXCP_TRIM_WARMUPTIME_WUCYCLES96 << 0) /**< Shifted mode WUCYCLES96 for AMUXCP_TRIM */
+#define AMUXCP_TRIM_WARMUPTIME_WUCYCLES128 (_AMUXCP_TRIM_WARMUPTIME_WUCYCLES128 << 0) /**< Shifted mode WUCYCLES128 for AMUXCP_TRIM */
+#define AMUXCP_TRIM_WARMUPTIME_WUCYCLES160 (_AMUXCP_TRIM_WARMUPTIME_WUCYCLES160 << 0) /**< Shifted mode WUCYCLES160 for AMUXCP_TRIM */
+#define AMUXCP_TRIM_FLOATVDDCPLO (0x1UL << 2) /**< Float VDDCP Low Power */
+#define _AMUXCP_TRIM_FLOATVDDCPLO_SHIFT 2 /**< Shift value for AMUXCP_FLOATVDDCPLO */
+#define _AMUXCP_TRIM_FLOATVDDCPLO_MASK 0x4UL /**< Bit mask for AMUXCP_FLOATVDDCPLO */
+#define _AMUXCP_TRIM_FLOATVDDCPLO_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TRIM */
+#define AMUXCP_TRIM_FLOATVDDCPLO_DEFAULT (_AMUXCP_TRIM_FLOATVDDCPLO_DEFAULT << 2) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
+#define AMUXCP_TRIM_FLOATVDDCPHI (0x1UL << 3) /**< Float VDDCP High Power */
+#define _AMUXCP_TRIM_FLOATVDDCPHI_SHIFT 3 /**< Shift value for AMUXCP_FLOATVDDCPHI */
+#define _AMUXCP_TRIM_FLOATVDDCPHI_MASK 0x8UL /**< Bit mask for AMUXCP_FLOATVDDCPHI */
+#define _AMUXCP_TRIM_FLOATVDDCPHI_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TRIM */
+#define AMUXCP_TRIM_FLOATVDDCPHI_DEFAULT (_AMUXCP_TRIM_FLOATVDDCPHI_DEFAULT << 3) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
+#define AMUXCP_TRIM_BYPASSDIV2LO (0x1UL << 4) /**< Bypass Div2 Low Power */
+#define _AMUXCP_TRIM_BYPASSDIV2LO_SHIFT 4 /**< Shift value for AMUXCP_BYPASSDIV2LO */
+#define _AMUXCP_TRIM_BYPASSDIV2LO_MASK 0x10UL /**< Bit mask for AMUXCP_BYPASSDIV2LO */
+#define _AMUXCP_TRIM_BYPASSDIV2LO_DEFAULT 0x00000001UL /**< Mode DEFAULT for AMUXCP_TRIM */
+#define AMUXCP_TRIM_BYPASSDIV2LO_DEFAULT (_AMUXCP_TRIM_BYPASSDIV2LO_DEFAULT << 4) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
+#define AMUXCP_TRIM_BYPASSDIV2HI (0x1UL << 5) /**< Bypass Div2 High Power */
+#define _AMUXCP_TRIM_BYPASSDIV2HI_SHIFT 5 /**< Shift value for AMUXCP_BYPASSDIV2HI */
+#define _AMUXCP_TRIM_BYPASSDIV2HI_MASK 0x20UL /**< Bit mask for AMUXCP_BYPASSDIV2HI */
+#define _AMUXCP_TRIM_BYPASSDIV2HI_DEFAULT 0x00000001UL /**< Mode DEFAULT for AMUXCP_TRIM */
+#define AMUXCP_TRIM_BYPASSDIV2HI_DEFAULT (_AMUXCP_TRIM_BYPASSDIV2HI_DEFAULT << 5) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
+#define AMUXCP_TRIM_BUMP0P5XLO (0x1UL << 6) /**< Bump 0.5X Low Power */
+#define _AMUXCP_TRIM_BUMP0P5XLO_SHIFT 6 /**< Shift value for AMUXCP_BUMP0P5XLO */
+#define _AMUXCP_TRIM_BUMP0P5XLO_MASK 0x40UL /**< Bit mask for AMUXCP_BUMP0P5XLO */
+#define _AMUXCP_TRIM_BUMP0P5XLO_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TRIM */
+#define AMUXCP_TRIM_BUMP0P5XLO_DEFAULT (_AMUXCP_TRIM_BUMP0P5XLO_DEFAULT << 6) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
+#define AMUXCP_TRIM_BUMP0P5XHI (0x1UL << 7) /**< Bump 0.5X High Power */
+#define _AMUXCP_TRIM_BUMP0P5XHI_SHIFT 7 /**< Shift value for AMUXCP_BUMP0P5XHI */
+#define _AMUXCP_TRIM_BUMP0P5XHI_MASK 0x80UL /**< Bit mask for AMUXCP_BUMP0P5XHI */
+#define _AMUXCP_TRIM_BUMP0P5XHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for AMUXCP_TRIM */
+#define AMUXCP_TRIM_BUMP0P5XHI_DEFAULT (_AMUXCP_TRIM_BUMP0P5XHI_DEFAULT << 7) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
+#define AMUXCP_TRIM_BIAS2XLO (0x1UL << 8) /**< Bias 2x Low Power */
+#define _AMUXCP_TRIM_BIAS2XLO_SHIFT 8 /**< Shift value for AMUXCP_BIAS2XLO */
+#define _AMUXCP_TRIM_BIAS2XLO_MASK 0x100UL /**< Bit mask for AMUXCP_BIAS2XLO */
+#define _AMUXCP_TRIM_BIAS2XLO_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TRIM */
+#define AMUXCP_TRIM_BIAS2XLO_DEFAULT (_AMUXCP_TRIM_BIAS2XLO_DEFAULT << 8) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
+#define AMUXCP_TRIM_BIAS2XHI (0x1UL << 9) /**< Bias 2x High Power */
+#define _AMUXCP_TRIM_BIAS2XHI_SHIFT 9 /**< Shift value for AMUXCP_BIAS2XHI */
+#define _AMUXCP_TRIM_BIAS2XHI_MASK 0x200UL /**< Bit mask for AMUXCP_BIAS2XHI */
+#define _AMUXCP_TRIM_BIAS2XHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for AMUXCP_TRIM */
+#define AMUXCP_TRIM_BIAS2XHI_DEFAULT (_AMUXCP_TRIM_BIAS2XHI_DEFAULT << 9) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
+#define _AMUXCP_TRIM_VOLTAGECTRLLO_SHIFT 10 /**< Shift value for AMUXCP_VOLTAGECTRLLO */
+#define _AMUXCP_TRIM_VOLTAGECTRLLO_MASK 0xC00UL /**< Bit mask for AMUXCP_VOLTAGECTRLLO */
+#define _AMUXCP_TRIM_VOLTAGECTRLLO_DEFAULT 0x00000002UL /**< Mode DEFAULT for AMUXCP_TRIM */
+#define AMUXCP_TRIM_VOLTAGECTRLLO_DEFAULT (_AMUXCP_TRIM_VOLTAGECTRLLO_DEFAULT << 10) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
+#define _AMUXCP_TRIM_VOLTAGECTRLHI_SHIFT 13 /**< Shift value for AMUXCP_VOLTAGECTRLHI */
+#define _AMUXCP_TRIM_VOLTAGECTRLHI_MASK 0x6000UL /**< Bit mask for AMUXCP_VOLTAGECTRLHI */
+#define _AMUXCP_TRIM_VOLTAGECTRLHI_DEFAULT 0x00000002UL /**< Mode DEFAULT for AMUXCP_TRIM */
+#define AMUXCP_TRIM_VOLTAGECTRLHI_DEFAULT (_AMUXCP_TRIM_VOLTAGECTRLHI_DEFAULT << 13) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
+#define _AMUXCP_TRIM_BIASCTRLLO_SHIFT 15 /**< Shift value for AMUXCP_BIASCTRLLO */
+#define _AMUXCP_TRIM_BIASCTRLLO_MASK 0x38000UL /**< Bit mask for AMUXCP_BIASCTRLLO */
+#define _AMUXCP_TRIM_BIASCTRLLO_DEFAULT 0x00000000UL /**< Mode DEFAULT for AMUXCP_TRIM */
+#define AMUXCP_TRIM_BIASCTRLLO_DEFAULT (_AMUXCP_TRIM_BIASCTRLLO_DEFAULT << 15) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
+#define _AMUXCP_TRIM_BIASCTRLLOCONT_SHIFT 18 /**< Shift value for AMUXCP_BIASCTRLLOCONT */
+#define _AMUXCP_TRIM_BIASCTRLLOCONT_MASK 0x1C0000UL /**< Bit mask for AMUXCP_BIASCTRLLOCONT */
+#define _AMUXCP_TRIM_BIASCTRLLOCONT_DEFAULT 0x00000001UL /**< Mode DEFAULT for AMUXCP_TRIM */
+#define AMUXCP_TRIM_BIASCTRLLOCONT_DEFAULT (_AMUXCP_TRIM_BIASCTRLLOCONT_DEFAULT << 18) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
+#define _AMUXCP_TRIM_BIASCTRLHI_SHIFT 21 /**< Shift value for AMUXCP_BIASCTRLHI */
+#define _AMUXCP_TRIM_BIASCTRLHI_MASK 0xE00000UL /**< Bit mask for AMUXCP_BIASCTRLHI */
+#define _AMUXCP_TRIM_BIASCTRLHI_DEFAULT 0x00000007UL /**< Mode DEFAULT for AMUXCP_TRIM */
+#define AMUXCP_TRIM_BIASCTRLHI_DEFAULT (_AMUXCP_TRIM_BIASCTRLHI_DEFAULT << 21) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
+#define _AMUXCP_TRIM_PUMPCAPLO_SHIFT 24 /**< Shift value for AMUXCP_PUMPCAPLO */
+#define _AMUXCP_TRIM_PUMPCAPLO_MASK 0x7000000UL /**< Bit mask for AMUXCP_PUMPCAPLO */
+#define _AMUXCP_TRIM_PUMPCAPLO_DEFAULT 0x00000007UL /**< Mode DEFAULT for AMUXCP_TRIM */
+#define AMUXCP_TRIM_PUMPCAPLO_DEFAULT (_AMUXCP_TRIM_PUMPCAPLO_DEFAULT << 24) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
+#define _AMUXCP_TRIM_PUMPCAPHI_SHIFT 28 /**< Shift value for AMUXCP_PUMPCAPHI */
+#define _AMUXCP_TRIM_PUMPCAPHI_MASK 0x70000000UL /**< Bit mask for AMUXCP_PUMPCAPHI */
+#define _AMUXCP_TRIM_PUMPCAPHI_DEFAULT 0x00000007UL /**< Mode DEFAULT for AMUXCP_TRIM */
+#define AMUXCP_TRIM_PUMPCAPHI_DEFAULT (_AMUXCP_TRIM_PUMPCAPHI_DEFAULT << 28) /**< Shifted mode DEFAULT for AMUXCP_TRIM */
+
+/** @} End of group EFR32MG24_AMUXCP_BitFields */
+/** @} End of group EFR32MG24_AMUXCP */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_AMUXCP_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_bufc.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_bufc.h
new file mode 100644
index 00000000..b7416d56
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_bufc.h
@@ -0,0 +1,746 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 BUFC register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_BUFC_H
+#define EFR32MG24_BUFC_H
+#define BUFC_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_BUFC BUFC
+ * @{
+ * @brief EFR32MG24 BUFC Register Declaration.
+ *****************************************************************************/
+
+/** BUFC BUF Register Group Declaration. */
+typedef struct {
+ __IOM uint32_t CTRL; /**< Buffer Control */
+ __IOM uint32_t ADDR; /**< Buffer Address */
+ __IOM uint32_t WRITEOFFSET; /**< Write Offset */
+ __IOM uint32_t READOFFSET; /**< Read Offset */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+ __IM uint32_t READDATA; /**< Buffer Read Data */
+ __IOM uint32_t WRITEDATA; /**< Buffer Write Data */
+ __IOM uint32_t XWRITE; /**< Buffer XOR Write */
+ __IM uint32_t STATUS; /**< Buffer Status Register */
+ __IOM uint32_t THRESHOLDCTRL; /**< Threshold Control */
+ __IOM uint32_t CMD; /**< Buffer Command */
+ __IOM uint32_t FIFOASYNC; /**< New Register */
+ __IM uint32_t READDATA32; /**< Buffer Read Data */
+ __IOM uint32_t WRITEDATA32; /**< Buffer Write Data */
+ __IOM uint32_t XWRITE32; /**< Buffer XOR Write */
+ uint32_t RESERVED1[1U]; /**< Reserved for future use */
+} BUFC_BUF_TypeDef;
+
+/** BUFC Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IP Version */
+ __IOM uint32_t EN; /**< Enable peripheral clock to this module */
+ __IOM uint32_t LPMODE; /**< Low power mode control */
+ BUFC_BUF_TypeDef BUF[4U]; /**< Data Buffer */
+ uint32_t RESERVED0[2U]; /**< Reserved for future use */
+ __IOM uint32_t IF; /**< BUFC Interrupt Flags */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IOM uint32_t SEQIF; /**< SEQ BUFC Interrupt Flags */
+ __IOM uint32_t SEQIEN; /**< SEQ Interrupt Enable Register */
+ __IOM uint32_t AHBCONFIG; /**< AHB Configuration */
+ uint32_t RESERVED1[950U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP Version */
+ __IOM uint32_t EN_SET; /**< Enable peripheral clock to this module */
+ __IOM uint32_t LPMODE_SET; /**< Low power mode control */
+ BUFC_BUF_TypeDef BUF_SET[4U]; /**< Data Buffer */
+ uint32_t RESERVED2[2U]; /**< Reserved for future use */
+ __IOM uint32_t IF_SET; /**< BUFC Interrupt Flags */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
+ __IOM uint32_t SEQIF_SET; /**< SEQ BUFC Interrupt Flags */
+ __IOM uint32_t SEQIEN_SET; /**< SEQ Interrupt Enable Register */
+ __IOM uint32_t AHBCONFIG_SET; /**< AHB Configuration */
+ uint32_t RESERVED3[950U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP Version */
+ __IOM uint32_t EN_CLR; /**< Enable peripheral clock to this module */
+ __IOM uint32_t LPMODE_CLR; /**< Low power mode control */
+ BUFC_BUF_TypeDef BUF_CLR[4U]; /**< Data Buffer */
+ uint32_t RESERVED4[2U]; /**< Reserved for future use */
+ __IOM uint32_t IF_CLR; /**< BUFC Interrupt Flags */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
+ __IOM uint32_t SEQIF_CLR; /**< SEQ BUFC Interrupt Flags */
+ __IOM uint32_t SEQIEN_CLR; /**< SEQ Interrupt Enable Register */
+ __IOM uint32_t AHBCONFIG_CLR; /**< AHB Configuration */
+ uint32_t RESERVED5[950U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP Version */
+ __IOM uint32_t EN_TGL; /**< Enable peripheral clock to this module */
+ __IOM uint32_t LPMODE_TGL; /**< Low power mode control */
+ BUFC_BUF_TypeDef BUF_TGL[4U]; /**< Data Buffer */
+ uint32_t RESERVED6[2U]; /**< Reserved for future use */
+ __IOM uint32_t IF_TGL; /**< BUFC Interrupt Flags */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
+ __IOM uint32_t SEQIF_TGL; /**< SEQ BUFC Interrupt Flags */
+ __IOM uint32_t SEQIEN_TGL; /**< SEQ Interrupt Enable Register */
+ __IOM uint32_t AHBCONFIG_TGL; /**< AHB Configuration */
+} BUFC_TypeDef;
+/** @} End of group EFR32MG24_BUFC */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_BUFC
+ * @{
+ * @defgroup EFR32MG24_BUFC_BitFields BUFC Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for BUFC IPVERSION */
+#define _BUFC_IPVERSION_RESETVALUE 0x00000004UL /**< Default value for BUFC_IPVERSION */
+#define _BUFC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for BUFC_IPVERSION */
+#define _BUFC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for BUFC_IPVERSION */
+#define _BUFC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for BUFC_IPVERSION */
+#define _BUFC_IPVERSION_IPVERSION_DEFAULT 0x00000004UL /**< Mode DEFAULT for BUFC_IPVERSION */
+#define BUFC_IPVERSION_IPVERSION_DEFAULT (_BUFC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_IPVERSION */
+
+/* Bit fields for BUFC EN */
+#define _BUFC_EN_RESETVALUE 0x00000000UL /**< Default value for BUFC_EN */
+#define _BUFC_EN_MASK 0x00000001UL /**< Mask for BUFC_EN */
+#define BUFC_EN_EN (0x1UL << 0) /**< Enable peripheral clock to this module */
+#define _BUFC_EN_EN_SHIFT 0 /**< Shift value for BUFC_EN */
+#define _BUFC_EN_EN_MASK 0x1UL /**< Bit mask for BUFC_EN */
+#define _BUFC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_EN */
+#define BUFC_EN_EN_DEFAULT (_BUFC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_EN */
+
+/* Bit fields for BUFC LPMODE */
+#define _BUFC_LPMODE_RESETVALUE 0x00000000UL /**< Default value for BUFC_LPMODE */
+#define _BUFC_LPMODE_MASK 0x00000003UL /**< Mask for BUFC_LPMODE */
+#define BUFC_LPMODE_LPENBYSEQ (0x1UL << 0) /**< Low power mode enable from sequencer */
+#define _BUFC_LPMODE_LPENBYSEQ_SHIFT 0 /**< Shift value for BUFC_LPENBYSEQ */
+#define _BUFC_LPMODE_LPENBYSEQ_MASK 0x1UL /**< Bit mask for BUFC_LPENBYSEQ */
+#define _BUFC_LPMODE_LPENBYSEQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_LPMODE */
+#define BUFC_LPMODE_LPENBYSEQ_DEFAULT (_BUFC_LPMODE_LPENBYSEQ_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_LPMODE */
+#define BUFC_LPMODE_LPENBYM33 (0x1UL << 1) /**< Low power mode enable from M33 */
+#define _BUFC_LPMODE_LPENBYM33_SHIFT 1 /**< Shift value for BUFC_LPENBYM33 */
+#define _BUFC_LPMODE_LPENBYM33_MASK 0x2UL /**< Bit mask for BUFC_LPENBYM33 */
+#define _BUFC_LPMODE_LPENBYM33_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_LPMODE */
+#define BUFC_LPMODE_LPENBYM33_DEFAULT (_BUFC_LPMODE_LPENBYM33_DEFAULT << 1) /**< Shifted mode DEFAULT for BUFC_LPMODE */
+
+/* Bit fields for BUFC BUF_CTRL */
+#define _BUFC_BUF_CTRL_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_CTRL */
+#define _BUFC_BUF_CTRL_MASK 0x00000007UL /**< Mask for BUFC_BUF_CTRL */
+#define _BUFC_BUF_CTRL_SIZE_SHIFT 0 /**< Shift value for BUFC_SIZE */
+#define _BUFC_BUF_CTRL_SIZE_MASK 0x7UL /**< Bit mask for BUFC_SIZE */
+#define _BUFC_BUF_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_CTRL */
+#define _BUFC_BUF_CTRL_SIZE_SIZE64 0x00000000UL /**< Mode SIZE64 for BUFC_BUF_CTRL */
+#define _BUFC_BUF_CTRL_SIZE_SIZE128 0x00000001UL /**< Mode SIZE128 for BUFC_BUF_CTRL */
+#define _BUFC_BUF_CTRL_SIZE_SIZE256 0x00000002UL /**< Mode SIZE256 for BUFC_BUF_CTRL */
+#define _BUFC_BUF_CTRL_SIZE_SIZE512 0x00000003UL /**< Mode SIZE512 for BUFC_BUF_CTRL */
+#define _BUFC_BUF_CTRL_SIZE_SIZE1024 0x00000004UL /**< Mode SIZE1024 for BUFC_BUF_CTRL */
+#define _BUFC_BUF_CTRL_SIZE_SIZE2048 0x00000005UL /**< Mode SIZE2048 for BUFC_BUF_CTRL */
+#define _BUFC_BUF_CTRL_SIZE_SIZE4096 0x00000006UL /**< Mode SIZE4096 for BUFC_BUF_CTRL */
+#define BUFC_BUF_CTRL_SIZE_DEFAULT (_BUFC_BUF_CTRL_SIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_CTRL */
+#define BUFC_BUF_CTRL_SIZE_SIZE64 (_BUFC_BUF_CTRL_SIZE_SIZE64 << 0) /**< Shifted mode SIZE64 for BUFC_BUF_CTRL */
+#define BUFC_BUF_CTRL_SIZE_SIZE128 (_BUFC_BUF_CTRL_SIZE_SIZE128 << 0) /**< Shifted mode SIZE128 for BUFC_BUF_CTRL */
+#define BUFC_BUF_CTRL_SIZE_SIZE256 (_BUFC_BUF_CTRL_SIZE_SIZE256 << 0) /**< Shifted mode SIZE256 for BUFC_BUF_CTRL */
+#define BUFC_BUF_CTRL_SIZE_SIZE512 (_BUFC_BUF_CTRL_SIZE_SIZE512 << 0) /**< Shifted mode SIZE512 for BUFC_BUF_CTRL */
+#define BUFC_BUF_CTRL_SIZE_SIZE1024 (_BUFC_BUF_CTRL_SIZE_SIZE1024 << 0) /**< Shifted mode SIZE1024 for BUFC_BUF_CTRL */
+#define BUFC_BUF_CTRL_SIZE_SIZE2048 (_BUFC_BUF_CTRL_SIZE_SIZE2048 << 0) /**< Shifted mode SIZE2048 for BUFC_BUF_CTRL */
+#define BUFC_BUF_CTRL_SIZE_SIZE4096 (_BUFC_BUF_CTRL_SIZE_SIZE4096 << 0) /**< Shifted mode SIZE4096 for BUFC_BUF_CTRL */
+
+/* Bit fields for BUFC BUF_ADDR */
+#define _BUFC_BUF_ADDR_RESETVALUE 0x20000000UL /**< Default value for BUFC_BUF_ADDR */
+#define _BUFC_BUF_ADDR_MASK 0xFFFFFFFCUL /**< Mask for BUFC_BUF_ADDR */
+#define _BUFC_BUF_ADDR_ADDR_SHIFT 2 /**< Shift value for BUFC_ADDR */
+#define _BUFC_BUF_ADDR_ADDR_MASK 0xFFFFFFFCUL /**< Bit mask for BUFC_ADDR */
+#define _BUFC_BUF_ADDR_ADDR_DEFAULT 0x08000000UL /**< Mode DEFAULT for BUFC_BUF_ADDR */
+#define BUFC_BUF_ADDR_ADDR_DEFAULT (_BUFC_BUF_ADDR_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for BUFC_BUF_ADDR */
+
+/* Bit fields for BUFC BUF_WRITEOFFSET */
+#define _BUFC_BUF_WRITEOFFSET_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_WRITEOFFSET */
+#define _BUFC_BUF_WRITEOFFSET_MASK 0x00001FFFUL /**< Mask for BUFC_BUF_WRITEOFFSET */
+#define _BUFC_BUF_WRITEOFFSET_WRITEOFFSET_SHIFT 0 /**< Shift value for BUFC_WRITEOFFSET */
+#define _BUFC_BUF_WRITEOFFSET_WRITEOFFSET_MASK 0x1FFFUL /**< Bit mask for BUFC_WRITEOFFSET */
+#define _BUFC_BUF_WRITEOFFSET_WRITEOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_WRITEOFFSET */
+#define BUFC_BUF_WRITEOFFSET_WRITEOFFSET_DEFAULT (_BUFC_BUF_WRITEOFFSET_WRITEOFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_WRITEOFFSET*/
+
+/* Bit fields for BUFC BUF_READOFFSET */
+#define _BUFC_BUF_READOFFSET_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_READOFFSET */
+#define _BUFC_BUF_READOFFSET_MASK 0x00001FFFUL /**< Mask for BUFC_BUF_READOFFSET */
+#define _BUFC_BUF_READOFFSET_READOFFSET_SHIFT 0 /**< Shift value for BUFC_READOFFSET */
+#define _BUFC_BUF_READOFFSET_READOFFSET_MASK 0x1FFFUL /**< Bit mask for BUFC_READOFFSET */
+#define _BUFC_BUF_READOFFSET_READOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_READOFFSET */
+#define BUFC_BUF_READOFFSET_READOFFSET_DEFAULT (_BUFC_BUF_READOFFSET_READOFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_READOFFSET*/
+
+/* Bit fields for BUFC BUF_READDATA */
+#define _BUFC_BUF_READDATA_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_READDATA */
+#define _BUFC_BUF_READDATA_MASK 0x000000FFUL /**< Mask for BUFC_BUF_READDATA */
+#define _BUFC_BUF_READDATA_READDATA_SHIFT 0 /**< Shift value for BUFC_READDATA */
+#define _BUFC_BUF_READDATA_READDATA_MASK 0xFFUL /**< Bit mask for BUFC_READDATA */
+#define _BUFC_BUF_READDATA_READDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_READDATA */
+#define BUFC_BUF_READDATA_READDATA_DEFAULT (_BUFC_BUF_READDATA_READDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_READDATA */
+
+/* Bit fields for BUFC BUF_WRITEDATA */
+#define _BUFC_BUF_WRITEDATA_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_WRITEDATA */
+#define _BUFC_BUF_WRITEDATA_MASK 0x000000FFUL /**< Mask for BUFC_BUF_WRITEDATA */
+#define _BUFC_BUF_WRITEDATA_WRITEDATA_SHIFT 0 /**< Shift value for BUFC_WRITEDATA */
+#define _BUFC_BUF_WRITEDATA_WRITEDATA_MASK 0xFFUL /**< Bit mask for BUFC_WRITEDATA */
+#define _BUFC_BUF_WRITEDATA_WRITEDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_WRITEDATA */
+#define BUFC_BUF_WRITEDATA_WRITEDATA_DEFAULT (_BUFC_BUF_WRITEDATA_WRITEDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_WRITEDATA */
+
+/* Bit fields for BUFC BUF_XWRITE */
+#define _BUFC_BUF_XWRITE_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_XWRITE */
+#define _BUFC_BUF_XWRITE_MASK 0x000000FFUL /**< Mask for BUFC_BUF_XWRITE */
+#define _BUFC_BUF_XWRITE_XORWRITEDATA_SHIFT 0 /**< Shift value for BUFC_XORWRITEDATA */
+#define _BUFC_BUF_XWRITE_XORWRITEDATA_MASK 0xFFUL /**< Bit mask for BUFC_XORWRITEDATA */
+#define _BUFC_BUF_XWRITE_XORWRITEDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_XWRITE */
+#define BUFC_BUF_XWRITE_XORWRITEDATA_DEFAULT (_BUFC_BUF_XWRITE_XORWRITEDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_XWRITE */
+
+/* Bit fields for BUFC BUF_STATUS */
+#define _BUFC_BUF_STATUS_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_STATUS */
+#define _BUFC_BUF_STATUS_MASK 0x01111FFFUL /**< Mask for BUFC_BUF_STATUS */
+#define _BUFC_BUF_STATUS_BYTES_SHIFT 0 /**< Shift value for BUFC_BYTES */
+#define _BUFC_BUF_STATUS_BYTES_MASK 0x1FFFUL /**< Bit mask for BUFC_BYTES */
+#define _BUFC_BUF_STATUS_BYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_STATUS */
+#define BUFC_BUF_STATUS_BYTES_DEFAULT (_BUFC_BUF_STATUS_BYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_STATUS */
+#define BUFC_BUF_STATUS_THRESHOLDFLAG (0x1UL << 20) /**< Buffer Threshold Flag */
+#define _BUFC_BUF_STATUS_THRESHOLDFLAG_SHIFT 20 /**< Shift value for BUFC_THRESHOLDFLAG */
+#define _BUFC_BUF_STATUS_THRESHOLDFLAG_MASK 0x100000UL /**< Bit mask for BUFC_THRESHOLDFLAG */
+#define _BUFC_BUF_STATUS_THRESHOLDFLAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_STATUS */
+#define BUFC_BUF_STATUS_THRESHOLDFLAG_DEFAULT (_BUFC_BUF_STATUS_THRESHOLDFLAG_DEFAULT << 20) /**< Shifted mode DEFAULT for BUFC_BUF_STATUS */
+
+/* Bit fields for BUFC BUF_THRESHOLDCTRL */
+#define _BUFC_BUF_THRESHOLDCTRL_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_THRESHOLDCTRL */
+#define _BUFC_BUF_THRESHOLDCTRL_MASK 0x00003FFFUL /**< Mask for BUFC_BUF_THRESHOLDCTRL */
+#define _BUFC_BUF_THRESHOLDCTRL_THRESHOLD_SHIFT 0 /**< Shift value for BUFC_THRESHOLD */
+#define _BUFC_BUF_THRESHOLDCTRL_THRESHOLD_MASK 0x1FFFUL /**< Bit mask for BUFC_THRESHOLD */
+#define _BUFC_BUF_THRESHOLDCTRL_THRESHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_THRESHOLDCTRL */
+#define BUFC_BUF_THRESHOLDCTRL_THRESHOLD_DEFAULT (_BUFC_BUF_THRESHOLDCTRL_THRESHOLD_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_THRESHOLDCTRL*/
+#define BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE (0x1UL << 13) /**< Buffer Threshold Mode */
+#define _BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_SHIFT 13 /**< Shift value for BUFC_THRESHOLDMODE */
+#define _BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_MASK 0x2000UL /**< Bit mask for BUFC_THRESHOLDMODE */
+#define _BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_THRESHOLDCTRL */
+#define _BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_LARGER 0x00000000UL /**< Mode LARGER for BUFC_BUF_THRESHOLDCTRL */
+#define _BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_LESSOREQUAL 0x00000001UL /**< Mode LESSOREQUAL for BUFC_BUF_THRESHOLDCTRL */
+#define BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_DEFAULT (_BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_DEFAULT << 13) /**< Shifted mode DEFAULT for BUFC_BUF_THRESHOLDCTRL*/
+#define BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_LARGER (_BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_LARGER << 13) /**< Shifted mode LARGER for BUFC_BUF_THRESHOLDCTRL*/
+#define BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_LESSOREQUAL (_BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_LESSOREQUAL << 13) /**< Shifted mode LESSOREQUAL for BUFC_BUF_THRESHOLDCTRL*/
+
+/* Bit fields for BUFC BUF_CMD */
+#define _BUFC_BUF_CMD_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_CMD */
+#define _BUFC_BUF_CMD_MASK 0x0000000FUL /**< Mask for BUFC_BUF_CMD */
+#define BUFC_BUF_CMD_CLEAR (0x1UL << 0) /**< Buffer Clear */
+#define _BUFC_BUF_CMD_CLEAR_SHIFT 0 /**< Shift value for BUFC_CLEAR */
+#define _BUFC_BUF_CMD_CLEAR_MASK 0x1UL /**< Bit mask for BUFC_CLEAR */
+#define _BUFC_BUF_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_CMD */
+#define BUFC_BUF_CMD_CLEAR_DEFAULT (_BUFC_BUF_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_CMD */
+#define BUFC_BUF_CMD_PREFETCH (0x1UL << 1) /**< Prefetch */
+#define _BUFC_BUF_CMD_PREFETCH_SHIFT 1 /**< Shift value for BUFC_PREFETCH */
+#define _BUFC_BUF_CMD_PREFETCH_MASK 0x2UL /**< Bit mask for BUFC_PREFETCH */
+#define _BUFC_BUF_CMD_PREFETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_CMD */
+#define BUFC_BUF_CMD_PREFETCH_DEFAULT (_BUFC_BUF_CMD_PREFETCH_DEFAULT << 1) /**< Shifted mode DEFAULT for BUFC_BUF_CMD */
+
+/* Bit fields for BUFC BUF_FIFOASYNC */
+#define _BUFC_BUF_FIFOASYNC_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_FIFOASYNC */
+#define _BUFC_BUF_FIFOASYNC_MASK 0x00000001UL /**< Mask for BUFC_BUF_FIFOASYNC */
+#define BUFC_BUF_FIFOASYNC_RST (0x1UL << 0) /**< Reset ASYNC */
+#define _BUFC_BUF_FIFOASYNC_RST_SHIFT 0 /**< Shift value for BUFC_RST */
+#define _BUFC_BUF_FIFOASYNC_RST_MASK 0x1UL /**< Bit mask for BUFC_RST */
+#define _BUFC_BUF_FIFOASYNC_RST_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_FIFOASYNC */
+#define BUFC_BUF_FIFOASYNC_RST_DEFAULT (_BUFC_BUF_FIFOASYNC_RST_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_FIFOASYNC */
+
+/* Bit fields for BUFC BUF_READDATA32 */
+#define _BUFC_BUF_READDATA32_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_READDATA32 */
+#define _BUFC_BUF_READDATA32_MASK 0xFFFFFFFFUL /**< Mask for BUFC_BUF_READDATA32 */
+#define _BUFC_BUF_READDATA32_READDATA32_SHIFT 0 /**< Shift value for BUFC_READDATA32 */
+#define _BUFC_BUF_READDATA32_READDATA32_MASK 0xFFFFFFFFUL /**< Bit mask for BUFC_READDATA32 */
+#define _BUFC_BUF_READDATA32_READDATA32_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_READDATA32 */
+#define BUFC_BUF_READDATA32_READDATA32_DEFAULT (_BUFC_BUF_READDATA32_READDATA32_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_READDATA32*/
+
+/* Bit fields for BUFC BUF_WRITEDATA32 */
+#define _BUFC_BUF_WRITEDATA32_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_WRITEDATA32 */
+#define _BUFC_BUF_WRITEDATA32_MASK 0xFFFFFFFFUL /**< Mask for BUFC_BUF_WRITEDATA32 */
+#define _BUFC_BUF_WRITEDATA32_WRITEDATA32_SHIFT 0 /**< Shift value for BUFC_WRITEDATA32 */
+#define _BUFC_BUF_WRITEDATA32_WRITEDATA32_MASK 0xFFFFFFFFUL /**< Bit mask for BUFC_WRITEDATA32 */
+#define _BUFC_BUF_WRITEDATA32_WRITEDATA32_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_WRITEDATA32 */
+#define BUFC_BUF_WRITEDATA32_WRITEDATA32_DEFAULT (_BUFC_BUF_WRITEDATA32_WRITEDATA32_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_WRITEDATA32*/
+
+/* Bit fields for BUFC BUF_XWRITE32 */
+#define _BUFC_BUF_XWRITE32_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_XWRITE32 */
+#define _BUFC_BUF_XWRITE32_MASK 0xFFFFFFFFUL /**< Mask for BUFC_BUF_XWRITE32 */
+#define _BUFC_BUF_XWRITE32_XORWRITEDATA32_SHIFT 0 /**< Shift value for BUFC_XORWRITEDATA32 */
+#define _BUFC_BUF_XWRITE32_XORWRITEDATA32_MASK 0xFFFFFFFFUL /**< Bit mask for BUFC_XORWRITEDATA32 */
+#define _BUFC_BUF_XWRITE32_XORWRITEDATA32_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_XWRITE32 */
+#define BUFC_BUF_XWRITE32_XORWRITEDATA32_DEFAULT (_BUFC_BUF_XWRITE32_XORWRITEDATA32_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_XWRITE32 */
+
+/* Bit fields for BUFC IF */
+#define _BUFC_IF_RESETVALUE 0x00000000UL /**< Default value for BUFC_IF */
+#define _BUFC_IF_MASK 0x9F1F1F1FUL /**< Mask for BUFC_IF */
+#define BUFC_IF_BUF0OF (0x1UL << 0) /**< Buffer 0 Overflow */
+#define _BUFC_IF_BUF0OF_SHIFT 0 /**< Shift value for BUFC_BUF0OF */
+#define _BUFC_IF_BUF0OF_MASK 0x1UL /**< Bit mask for BUFC_BUF0OF */
+#define _BUFC_IF_BUF0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF0OF_DEFAULT (_BUFC_IF_BUF0OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF0UF (0x1UL << 1) /**< Buffer 0 Underflow */
+#define _BUFC_IF_BUF0UF_SHIFT 1 /**< Shift value for BUFC_BUF0UF */
+#define _BUFC_IF_BUF0UF_MASK 0x2UL /**< Bit mask for BUFC_BUF0UF */
+#define _BUFC_IF_BUF0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF0UF_DEFAULT (_BUFC_IF_BUF0UF_DEFAULT << 1) /**< Shifted mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF0THR (0x1UL << 2) /**< Buffer 0 Threshold Event */
+#define _BUFC_IF_BUF0THR_SHIFT 2 /**< Shift value for BUFC_BUF0THR */
+#define _BUFC_IF_BUF0THR_MASK 0x4UL /**< Bit mask for BUFC_BUF0THR */
+#define _BUFC_IF_BUF0THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF0THR_DEFAULT (_BUFC_IF_BUF0THR_DEFAULT << 2) /**< Shifted mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF0CORR (0x1UL << 3) /**< Buffer 0 Corrupt */
+#define _BUFC_IF_BUF0CORR_SHIFT 3 /**< Shift value for BUFC_BUF0CORR */
+#define _BUFC_IF_BUF0CORR_MASK 0x8UL /**< Bit mask for BUFC_BUF0CORR */
+#define _BUFC_IF_BUF0CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF0CORR_DEFAULT (_BUFC_IF_BUF0CORR_DEFAULT << 3) /**< Shifted mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF0NWA (0x1UL << 4) /**< Buffer 0 Not Word-Aligned */
+#define _BUFC_IF_BUF0NWA_SHIFT 4 /**< Shift value for BUFC_BUF0NWA */
+#define _BUFC_IF_BUF0NWA_MASK 0x10UL /**< Bit mask for BUFC_BUF0NWA */
+#define _BUFC_IF_BUF0NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF0NWA_DEFAULT (_BUFC_IF_BUF0NWA_DEFAULT << 4) /**< Shifted mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF1OF (0x1UL << 8) /**< Buffer 1 Overflow */
+#define _BUFC_IF_BUF1OF_SHIFT 8 /**< Shift value for BUFC_BUF1OF */
+#define _BUFC_IF_BUF1OF_MASK 0x100UL /**< Bit mask for BUFC_BUF1OF */
+#define _BUFC_IF_BUF1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF1OF_DEFAULT (_BUFC_IF_BUF1OF_DEFAULT << 8) /**< Shifted mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF1UF (0x1UL << 9) /**< Buffer 1 Underflow */
+#define _BUFC_IF_BUF1UF_SHIFT 9 /**< Shift value for BUFC_BUF1UF */
+#define _BUFC_IF_BUF1UF_MASK 0x200UL /**< Bit mask for BUFC_BUF1UF */
+#define _BUFC_IF_BUF1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF1UF_DEFAULT (_BUFC_IF_BUF1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF1THR (0x1UL << 10) /**< Buffer 1 Threshold Event */
+#define _BUFC_IF_BUF1THR_SHIFT 10 /**< Shift value for BUFC_BUF1THR */
+#define _BUFC_IF_BUF1THR_MASK 0x400UL /**< Bit mask for BUFC_BUF1THR */
+#define _BUFC_IF_BUF1THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF1THR_DEFAULT (_BUFC_IF_BUF1THR_DEFAULT << 10) /**< Shifted mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF1CORR (0x1UL << 11) /**< Buffer 1 Corrupt */
+#define _BUFC_IF_BUF1CORR_SHIFT 11 /**< Shift value for BUFC_BUF1CORR */
+#define _BUFC_IF_BUF1CORR_MASK 0x800UL /**< Bit mask for BUFC_BUF1CORR */
+#define _BUFC_IF_BUF1CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF1CORR_DEFAULT (_BUFC_IF_BUF1CORR_DEFAULT << 11) /**< Shifted mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF1NWA (0x1UL << 12) /**< Buffer 1 Not Word-Aligned */
+#define _BUFC_IF_BUF1NWA_SHIFT 12 /**< Shift value for BUFC_BUF1NWA */
+#define _BUFC_IF_BUF1NWA_MASK 0x1000UL /**< Bit mask for BUFC_BUF1NWA */
+#define _BUFC_IF_BUF1NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF1NWA_DEFAULT (_BUFC_IF_BUF1NWA_DEFAULT << 12) /**< Shifted mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF2OF (0x1UL << 16) /**< Buffer 2 Overflow */
+#define _BUFC_IF_BUF2OF_SHIFT 16 /**< Shift value for BUFC_BUF2OF */
+#define _BUFC_IF_BUF2OF_MASK 0x10000UL /**< Bit mask for BUFC_BUF2OF */
+#define _BUFC_IF_BUF2OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF2OF_DEFAULT (_BUFC_IF_BUF2OF_DEFAULT << 16) /**< Shifted mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF2UF (0x1UL << 17) /**< Buffer 2 Underflow */
+#define _BUFC_IF_BUF2UF_SHIFT 17 /**< Shift value for BUFC_BUF2UF */
+#define _BUFC_IF_BUF2UF_MASK 0x20000UL /**< Bit mask for BUFC_BUF2UF */
+#define _BUFC_IF_BUF2UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF2UF_DEFAULT (_BUFC_IF_BUF2UF_DEFAULT << 17) /**< Shifted mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF2THR (0x1UL << 18) /**< Buffer 2 Threshold Event */
+#define _BUFC_IF_BUF2THR_SHIFT 18 /**< Shift value for BUFC_BUF2THR */
+#define _BUFC_IF_BUF2THR_MASK 0x40000UL /**< Bit mask for BUFC_BUF2THR */
+#define _BUFC_IF_BUF2THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF2THR_DEFAULT (_BUFC_IF_BUF2THR_DEFAULT << 18) /**< Shifted mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF2CORR (0x1UL << 19) /**< Buffer 2 Corrupt */
+#define _BUFC_IF_BUF2CORR_SHIFT 19 /**< Shift value for BUFC_BUF2CORR */
+#define _BUFC_IF_BUF2CORR_MASK 0x80000UL /**< Bit mask for BUFC_BUF2CORR */
+#define _BUFC_IF_BUF2CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF2CORR_DEFAULT (_BUFC_IF_BUF2CORR_DEFAULT << 19) /**< Shifted mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF2NWA (0x1UL << 20) /**< Buffer 2 Not Word-Aligned */
+#define _BUFC_IF_BUF2NWA_SHIFT 20 /**< Shift value for BUFC_BUF2NWA */
+#define _BUFC_IF_BUF2NWA_MASK 0x100000UL /**< Bit mask for BUFC_BUF2NWA */
+#define _BUFC_IF_BUF2NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF2NWA_DEFAULT (_BUFC_IF_BUF2NWA_DEFAULT << 20) /**< Shifted mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF3OF (0x1UL << 24) /**< Buffer 3 Overflow */
+#define _BUFC_IF_BUF3OF_SHIFT 24 /**< Shift value for BUFC_BUF3OF */
+#define _BUFC_IF_BUF3OF_MASK 0x1000000UL /**< Bit mask for BUFC_BUF3OF */
+#define _BUFC_IF_BUF3OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF3OF_DEFAULT (_BUFC_IF_BUF3OF_DEFAULT << 24) /**< Shifted mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF3UF (0x1UL << 25) /**< Buffer 3 Underflow */
+#define _BUFC_IF_BUF3UF_SHIFT 25 /**< Shift value for BUFC_BUF3UF */
+#define _BUFC_IF_BUF3UF_MASK 0x2000000UL /**< Bit mask for BUFC_BUF3UF */
+#define _BUFC_IF_BUF3UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF3UF_DEFAULT (_BUFC_IF_BUF3UF_DEFAULT << 25) /**< Shifted mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF3THR (0x1UL << 26) /**< Buffer 3 Threshold Event */
+#define _BUFC_IF_BUF3THR_SHIFT 26 /**< Shift value for BUFC_BUF3THR */
+#define _BUFC_IF_BUF3THR_MASK 0x4000000UL /**< Bit mask for BUFC_BUF3THR */
+#define _BUFC_IF_BUF3THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF3THR_DEFAULT (_BUFC_IF_BUF3THR_DEFAULT << 26) /**< Shifted mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF3CORR (0x1UL << 27) /**< Buffer 3 Corrupt */
+#define _BUFC_IF_BUF3CORR_SHIFT 27 /**< Shift value for BUFC_BUF3CORR */
+#define _BUFC_IF_BUF3CORR_MASK 0x8000000UL /**< Bit mask for BUFC_BUF3CORR */
+#define _BUFC_IF_BUF3CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF3CORR_DEFAULT (_BUFC_IF_BUF3CORR_DEFAULT << 27) /**< Shifted mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF3NWA (0x1UL << 28) /**< Buffer 3 Not Word-Aligned */
+#define _BUFC_IF_BUF3NWA_SHIFT 28 /**< Shift value for BUFC_BUF3NWA */
+#define _BUFC_IF_BUF3NWA_MASK 0x10000000UL /**< Bit mask for BUFC_BUF3NWA */
+#define _BUFC_IF_BUF3NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUF3NWA_DEFAULT (_BUFC_IF_BUF3NWA_DEFAULT << 28) /**< Shifted mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUSERROR (0x1UL << 31) /**< Bus Error */
+#define _BUFC_IF_BUSERROR_SHIFT 31 /**< Shift value for BUFC_BUSERROR */
+#define _BUFC_IF_BUSERROR_MASK 0x80000000UL /**< Bit mask for BUFC_BUSERROR */
+#define _BUFC_IF_BUSERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
+#define BUFC_IF_BUSERROR_DEFAULT (_BUFC_IF_BUSERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for BUFC_IF */
+
+/* Bit fields for BUFC IEN */
+#define _BUFC_IEN_RESETVALUE 0x00000000UL /**< Default value for BUFC_IEN */
+#define _BUFC_IEN_MASK 0x9F1F1F1FUL /**< Mask for BUFC_IEN */
+#define BUFC_IEN_BUF0OF (0x1UL << 0) /**< BUF0OF Interrupt Enable */
+#define _BUFC_IEN_BUF0OF_SHIFT 0 /**< Shift value for BUFC_BUF0OF */
+#define _BUFC_IEN_BUF0OF_MASK 0x1UL /**< Bit mask for BUFC_BUF0OF */
+#define _BUFC_IEN_BUF0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF0OF_DEFAULT (_BUFC_IEN_BUF0OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF0UF (0x1UL << 1) /**< BUF0UF Interrupt Enable */
+#define _BUFC_IEN_BUF0UF_SHIFT 1 /**< Shift value for BUFC_BUF0UF */
+#define _BUFC_IEN_BUF0UF_MASK 0x2UL /**< Bit mask for BUFC_BUF0UF */
+#define _BUFC_IEN_BUF0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF0UF_DEFAULT (_BUFC_IEN_BUF0UF_DEFAULT << 1) /**< Shifted mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF0THR (0x1UL << 2) /**< BUF0THR Interrupt Enable */
+#define _BUFC_IEN_BUF0THR_SHIFT 2 /**< Shift value for BUFC_BUF0THR */
+#define _BUFC_IEN_BUF0THR_MASK 0x4UL /**< Bit mask for BUFC_BUF0THR */
+#define _BUFC_IEN_BUF0THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF0THR_DEFAULT (_BUFC_IEN_BUF0THR_DEFAULT << 2) /**< Shifted mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF0CORR (0x1UL << 3) /**< BUF0CORR Interrupt Enable */
+#define _BUFC_IEN_BUF0CORR_SHIFT 3 /**< Shift value for BUFC_BUF0CORR */
+#define _BUFC_IEN_BUF0CORR_MASK 0x8UL /**< Bit mask for BUFC_BUF0CORR */
+#define _BUFC_IEN_BUF0CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF0CORR_DEFAULT (_BUFC_IEN_BUF0CORR_DEFAULT << 3) /**< Shifted mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF0NWA (0x1UL << 4) /**< BUF0NWA Interrupt Enable */
+#define _BUFC_IEN_BUF0NWA_SHIFT 4 /**< Shift value for BUFC_BUF0NWA */
+#define _BUFC_IEN_BUF0NWA_MASK 0x10UL /**< Bit mask for BUFC_BUF0NWA */
+#define _BUFC_IEN_BUF0NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF0NWA_DEFAULT (_BUFC_IEN_BUF0NWA_DEFAULT << 4) /**< Shifted mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF1OF (0x1UL << 8) /**< BUF1OF Interrupt Enable */
+#define _BUFC_IEN_BUF1OF_SHIFT 8 /**< Shift value for BUFC_BUF1OF */
+#define _BUFC_IEN_BUF1OF_MASK 0x100UL /**< Bit mask for BUFC_BUF1OF */
+#define _BUFC_IEN_BUF1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF1OF_DEFAULT (_BUFC_IEN_BUF1OF_DEFAULT << 8) /**< Shifted mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF1UF (0x1UL << 9) /**< BUF1UF Interrupt Enable */
+#define _BUFC_IEN_BUF1UF_SHIFT 9 /**< Shift value for BUFC_BUF1UF */
+#define _BUFC_IEN_BUF1UF_MASK 0x200UL /**< Bit mask for BUFC_BUF1UF */
+#define _BUFC_IEN_BUF1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF1UF_DEFAULT (_BUFC_IEN_BUF1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF1THR (0x1UL << 10) /**< BUF1THR Interrupt Enable */
+#define _BUFC_IEN_BUF1THR_SHIFT 10 /**< Shift value for BUFC_BUF1THR */
+#define _BUFC_IEN_BUF1THR_MASK 0x400UL /**< Bit mask for BUFC_BUF1THR */
+#define _BUFC_IEN_BUF1THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF1THR_DEFAULT (_BUFC_IEN_BUF1THR_DEFAULT << 10) /**< Shifted mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF1CORR (0x1UL << 11) /**< BUF1CORR Interrupt Enable */
+#define _BUFC_IEN_BUF1CORR_SHIFT 11 /**< Shift value for BUFC_BUF1CORR */
+#define _BUFC_IEN_BUF1CORR_MASK 0x800UL /**< Bit mask for BUFC_BUF1CORR */
+#define _BUFC_IEN_BUF1CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF1CORR_DEFAULT (_BUFC_IEN_BUF1CORR_DEFAULT << 11) /**< Shifted mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF1NWA (0x1UL << 12) /**< BUF1NWA Interrupt Enable */
+#define _BUFC_IEN_BUF1NWA_SHIFT 12 /**< Shift value for BUFC_BUF1NWA */
+#define _BUFC_IEN_BUF1NWA_MASK 0x1000UL /**< Bit mask for BUFC_BUF1NWA */
+#define _BUFC_IEN_BUF1NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF1NWA_DEFAULT (_BUFC_IEN_BUF1NWA_DEFAULT << 12) /**< Shifted mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF2OF (0x1UL << 16) /**< BUF2OF Interrupt Enable */
+#define _BUFC_IEN_BUF2OF_SHIFT 16 /**< Shift value for BUFC_BUF2OF */
+#define _BUFC_IEN_BUF2OF_MASK 0x10000UL /**< Bit mask for BUFC_BUF2OF */
+#define _BUFC_IEN_BUF2OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF2OF_DEFAULT (_BUFC_IEN_BUF2OF_DEFAULT << 16) /**< Shifted mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF2UF (0x1UL << 17) /**< BUF2UF Interrupt Enable */
+#define _BUFC_IEN_BUF2UF_SHIFT 17 /**< Shift value for BUFC_BUF2UF */
+#define _BUFC_IEN_BUF2UF_MASK 0x20000UL /**< Bit mask for BUFC_BUF2UF */
+#define _BUFC_IEN_BUF2UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF2UF_DEFAULT (_BUFC_IEN_BUF2UF_DEFAULT << 17) /**< Shifted mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF2THR (0x1UL << 18) /**< BUF2THR Interrupt Enable */
+#define _BUFC_IEN_BUF2THR_SHIFT 18 /**< Shift value for BUFC_BUF2THR */
+#define _BUFC_IEN_BUF2THR_MASK 0x40000UL /**< Bit mask for BUFC_BUF2THR */
+#define _BUFC_IEN_BUF2THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF2THR_DEFAULT (_BUFC_IEN_BUF2THR_DEFAULT << 18) /**< Shifted mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF2CORR (0x1UL << 19) /**< BUF2CORR Interrupt Enable */
+#define _BUFC_IEN_BUF2CORR_SHIFT 19 /**< Shift value for BUFC_BUF2CORR */
+#define _BUFC_IEN_BUF2CORR_MASK 0x80000UL /**< Bit mask for BUFC_BUF2CORR */
+#define _BUFC_IEN_BUF2CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF2CORR_DEFAULT (_BUFC_IEN_BUF2CORR_DEFAULT << 19) /**< Shifted mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF2NWA (0x1UL << 20) /**< BUF2NWA Interrupt Enable */
+#define _BUFC_IEN_BUF2NWA_SHIFT 20 /**< Shift value for BUFC_BUF2NWA */
+#define _BUFC_IEN_BUF2NWA_MASK 0x100000UL /**< Bit mask for BUFC_BUF2NWA */
+#define _BUFC_IEN_BUF2NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF2NWA_DEFAULT (_BUFC_IEN_BUF2NWA_DEFAULT << 20) /**< Shifted mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF3OF (0x1UL << 24) /**< BUF3OF Interrupt Enable */
+#define _BUFC_IEN_BUF3OF_SHIFT 24 /**< Shift value for BUFC_BUF3OF */
+#define _BUFC_IEN_BUF3OF_MASK 0x1000000UL /**< Bit mask for BUFC_BUF3OF */
+#define _BUFC_IEN_BUF3OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF3OF_DEFAULT (_BUFC_IEN_BUF3OF_DEFAULT << 24) /**< Shifted mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF3UF (0x1UL << 25) /**< BUF3UF Interrupt Enable */
+#define _BUFC_IEN_BUF3UF_SHIFT 25 /**< Shift value for BUFC_BUF3UF */
+#define _BUFC_IEN_BUF3UF_MASK 0x2000000UL /**< Bit mask for BUFC_BUF3UF */
+#define _BUFC_IEN_BUF3UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF3UF_DEFAULT (_BUFC_IEN_BUF3UF_DEFAULT << 25) /**< Shifted mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF3THR (0x1UL << 26) /**< BUF3THR Interrupt Enable */
+#define _BUFC_IEN_BUF3THR_SHIFT 26 /**< Shift value for BUFC_BUF3THR */
+#define _BUFC_IEN_BUF3THR_MASK 0x4000000UL /**< Bit mask for BUFC_BUF3THR */
+#define _BUFC_IEN_BUF3THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF3THR_DEFAULT (_BUFC_IEN_BUF3THR_DEFAULT << 26) /**< Shifted mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF3CORR (0x1UL << 27) /**< BUF3CORR Interrupt Enable */
+#define _BUFC_IEN_BUF3CORR_SHIFT 27 /**< Shift value for BUFC_BUF3CORR */
+#define _BUFC_IEN_BUF3CORR_MASK 0x8000000UL /**< Bit mask for BUFC_BUF3CORR */
+#define _BUFC_IEN_BUF3CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF3CORR_DEFAULT (_BUFC_IEN_BUF3CORR_DEFAULT << 27) /**< Shifted mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF3NWA (0x1UL << 28) /**< BUF3NWA Interrupt Enable */
+#define _BUFC_IEN_BUF3NWA_SHIFT 28 /**< Shift value for BUFC_BUF3NWA */
+#define _BUFC_IEN_BUF3NWA_MASK 0x10000000UL /**< Bit mask for BUFC_BUF3NWA */
+#define _BUFC_IEN_BUF3NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUF3NWA_DEFAULT (_BUFC_IEN_BUF3NWA_DEFAULT << 28) /**< Shifted mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUSERROR (0x1UL << 31) /**< BUSERROR Interrupt Enable */
+#define _BUFC_IEN_BUSERROR_SHIFT 31 /**< Shift value for BUFC_BUSERROR */
+#define _BUFC_IEN_BUSERROR_MASK 0x80000000UL /**< Bit mask for BUFC_BUSERROR */
+#define _BUFC_IEN_BUSERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
+#define BUFC_IEN_BUSERROR_DEFAULT (_BUFC_IEN_BUSERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for BUFC_IEN */
+
+/* Bit fields for BUFC SEQIF */
+#define _BUFC_SEQIF_RESETVALUE 0x00000000UL /**< Default value for BUFC_SEQIF */
+#define _BUFC_SEQIF_MASK 0x9F1F1F1FUL /**< Mask for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF0OF (0x1UL << 0) /**< Buffer 0 Overflow */
+#define _BUFC_SEQIF_BUF0OF_SHIFT 0 /**< Shift value for BUFC_BUF0OF */
+#define _BUFC_SEQIF_BUF0OF_MASK 0x1UL /**< Bit mask for BUFC_BUF0OF */
+#define _BUFC_SEQIF_BUF0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF0OF_DEFAULT (_BUFC_SEQIF_BUF0OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF0UF (0x1UL << 1) /**< Buffer 0 Underflow */
+#define _BUFC_SEQIF_BUF0UF_SHIFT 1 /**< Shift value for BUFC_BUF0UF */
+#define _BUFC_SEQIF_BUF0UF_MASK 0x2UL /**< Bit mask for BUFC_BUF0UF */
+#define _BUFC_SEQIF_BUF0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF0UF_DEFAULT (_BUFC_SEQIF_BUF0UF_DEFAULT << 1) /**< Shifted mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF0THR (0x1UL << 2) /**< Buffer 0 Threshold Event */
+#define _BUFC_SEQIF_BUF0THR_SHIFT 2 /**< Shift value for BUFC_BUF0THR */
+#define _BUFC_SEQIF_BUF0THR_MASK 0x4UL /**< Bit mask for BUFC_BUF0THR */
+#define _BUFC_SEQIF_BUF0THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF0THR_DEFAULT (_BUFC_SEQIF_BUF0THR_DEFAULT << 2) /**< Shifted mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF0CORR (0x1UL << 3) /**< Buffer 0 Corrupt */
+#define _BUFC_SEQIF_BUF0CORR_SHIFT 3 /**< Shift value for BUFC_BUF0CORR */
+#define _BUFC_SEQIF_BUF0CORR_MASK 0x8UL /**< Bit mask for BUFC_BUF0CORR */
+#define _BUFC_SEQIF_BUF0CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF0CORR_DEFAULT (_BUFC_SEQIF_BUF0CORR_DEFAULT << 3) /**< Shifted mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF0NWA (0x1UL << 4) /**< Buffer 0 Not Word-Aligned */
+#define _BUFC_SEQIF_BUF0NWA_SHIFT 4 /**< Shift value for BUFC_BUF0NWA */
+#define _BUFC_SEQIF_BUF0NWA_MASK 0x10UL /**< Bit mask for BUFC_BUF0NWA */
+#define _BUFC_SEQIF_BUF0NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF0NWA_DEFAULT (_BUFC_SEQIF_BUF0NWA_DEFAULT << 4) /**< Shifted mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF1OF (0x1UL << 8) /**< Buffer 1 Overflow */
+#define _BUFC_SEQIF_BUF1OF_SHIFT 8 /**< Shift value for BUFC_BUF1OF */
+#define _BUFC_SEQIF_BUF1OF_MASK 0x100UL /**< Bit mask for BUFC_BUF1OF */
+#define _BUFC_SEQIF_BUF1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF1OF_DEFAULT (_BUFC_SEQIF_BUF1OF_DEFAULT << 8) /**< Shifted mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF1UF (0x1UL << 9) /**< Buffer 1 Underflow */
+#define _BUFC_SEQIF_BUF1UF_SHIFT 9 /**< Shift value for BUFC_BUF1UF */
+#define _BUFC_SEQIF_BUF1UF_MASK 0x200UL /**< Bit mask for BUFC_BUF1UF */
+#define _BUFC_SEQIF_BUF1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF1UF_DEFAULT (_BUFC_SEQIF_BUF1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF1THR (0x1UL << 10) /**< Buffer 1 Threshold Event */
+#define _BUFC_SEQIF_BUF1THR_SHIFT 10 /**< Shift value for BUFC_BUF1THR */
+#define _BUFC_SEQIF_BUF1THR_MASK 0x400UL /**< Bit mask for BUFC_BUF1THR */
+#define _BUFC_SEQIF_BUF1THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF1THR_DEFAULT (_BUFC_SEQIF_BUF1THR_DEFAULT << 10) /**< Shifted mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF1CORR (0x1UL << 11) /**< Buffer 1 Corrupt */
+#define _BUFC_SEQIF_BUF1CORR_SHIFT 11 /**< Shift value for BUFC_BUF1CORR */
+#define _BUFC_SEQIF_BUF1CORR_MASK 0x800UL /**< Bit mask for BUFC_BUF1CORR */
+#define _BUFC_SEQIF_BUF1CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF1CORR_DEFAULT (_BUFC_SEQIF_BUF1CORR_DEFAULT << 11) /**< Shifted mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF1NWA (0x1UL << 12) /**< Buffer 1 Not Word-Aligned */
+#define _BUFC_SEQIF_BUF1NWA_SHIFT 12 /**< Shift value for BUFC_BUF1NWA */
+#define _BUFC_SEQIF_BUF1NWA_MASK 0x1000UL /**< Bit mask for BUFC_BUF1NWA */
+#define _BUFC_SEQIF_BUF1NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF1NWA_DEFAULT (_BUFC_SEQIF_BUF1NWA_DEFAULT << 12) /**< Shifted mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF2OF (0x1UL << 16) /**< Buffer 2 Overflow */
+#define _BUFC_SEQIF_BUF2OF_SHIFT 16 /**< Shift value for BUFC_BUF2OF */
+#define _BUFC_SEQIF_BUF2OF_MASK 0x10000UL /**< Bit mask for BUFC_BUF2OF */
+#define _BUFC_SEQIF_BUF2OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF2OF_DEFAULT (_BUFC_SEQIF_BUF2OF_DEFAULT << 16) /**< Shifted mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF2UF (0x1UL << 17) /**< Buffer 2 Underflow */
+#define _BUFC_SEQIF_BUF2UF_SHIFT 17 /**< Shift value for BUFC_BUF2UF */
+#define _BUFC_SEQIF_BUF2UF_MASK 0x20000UL /**< Bit mask for BUFC_BUF2UF */
+#define _BUFC_SEQIF_BUF2UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF2UF_DEFAULT (_BUFC_SEQIF_BUF2UF_DEFAULT << 17) /**< Shifted mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF2THR (0x1UL << 18) /**< Buffer 2 Threshold Event */
+#define _BUFC_SEQIF_BUF2THR_SHIFT 18 /**< Shift value for BUFC_BUF2THR */
+#define _BUFC_SEQIF_BUF2THR_MASK 0x40000UL /**< Bit mask for BUFC_BUF2THR */
+#define _BUFC_SEQIF_BUF2THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF2THR_DEFAULT (_BUFC_SEQIF_BUF2THR_DEFAULT << 18) /**< Shifted mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF2CORR (0x1UL << 19) /**< Buffer 2 Corrupt */
+#define _BUFC_SEQIF_BUF2CORR_SHIFT 19 /**< Shift value for BUFC_BUF2CORR */
+#define _BUFC_SEQIF_BUF2CORR_MASK 0x80000UL /**< Bit mask for BUFC_BUF2CORR */
+#define _BUFC_SEQIF_BUF2CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF2CORR_DEFAULT (_BUFC_SEQIF_BUF2CORR_DEFAULT << 19) /**< Shifted mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF2NWA (0x1UL << 20) /**< Buffer 2 Not Word-Aligned */
+#define _BUFC_SEQIF_BUF2NWA_SHIFT 20 /**< Shift value for BUFC_BUF2NWA */
+#define _BUFC_SEQIF_BUF2NWA_MASK 0x100000UL /**< Bit mask for BUFC_BUF2NWA */
+#define _BUFC_SEQIF_BUF2NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF2NWA_DEFAULT (_BUFC_SEQIF_BUF2NWA_DEFAULT << 20) /**< Shifted mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF3OF (0x1UL << 24) /**< Buffer 3 Overflow */
+#define _BUFC_SEQIF_BUF3OF_SHIFT 24 /**< Shift value for BUFC_BUF3OF */
+#define _BUFC_SEQIF_BUF3OF_MASK 0x1000000UL /**< Bit mask for BUFC_BUF3OF */
+#define _BUFC_SEQIF_BUF3OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF3OF_DEFAULT (_BUFC_SEQIF_BUF3OF_DEFAULT << 24) /**< Shifted mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF3UF (0x1UL << 25) /**< Buffer 3 Underflow */
+#define _BUFC_SEQIF_BUF3UF_SHIFT 25 /**< Shift value for BUFC_BUF3UF */
+#define _BUFC_SEQIF_BUF3UF_MASK 0x2000000UL /**< Bit mask for BUFC_BUF3UF */
+#define _BUFC_SEQIF_BUF3UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF3UF_DEFAULT (_BUFC_SEQIF_BUF3UF_DEFAULT << 25) /**< Shifted mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF3THR (0x1UL << 26) /**< Buffer 3 Threshold Event */
+#define _BUFC_SEQIF_BUF3THR_SHIFT 26 /**< Shift value for BUFC_BUF3THR */
+#define _BUFC_SEQIF_BUF3THR_MASK 0x4000000UL /**< Bit mask for BUFC_BUF3THR */
+#define _BUFC_SEQIF_BUF3THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF3THR_DEFAULT (_BUFC_SEQIF_BUF3THR_DEFAULT << 26) /**< Shifted mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF3CORR (0x1UL << 27) /**< Buffer 3 Corrupt */
+#define _BUFC_SEQIF_BUF3CORR_SHIFT 27 /**< Shift value for BUFC_BUF3CORR */
+#define _BUFC_SEQIF_BUF3CORR_MASK 0x8000000UL /**< Bit mask for BUFC_BUF3CORR */
+#define _BUFC_SEQIF_BUF3CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF3CORR_DEFAULT (_BUFC_SEQIF_BUF3CORR_DEFAULT << 27) /**< Shifted mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF3NWA (0x1UL << 28) /**< Buffer 3 Not Word-Aligned */
+#define _BUFC_SEQIF_BUF3NWA_SHIFT 28 /**< Shift value for BUFC_BUF3NWA */
+#define _BUFC_SEQIF_BUF3NWA_MASK 0x10000000UL /**< Bit mask for BUFC_BUF3NWA */
+#define _BUFC_SEQIF_BUF3NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUF3NWA_DEFAULT (_BUFC_SEQIF_BUF3NWA_DEFAULT << 28) /**< Shifted mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUSERROR (0x1UL << 31) /**< Bus Error */
+#define _BUFC_SEQIF_BUSERROR_SHIFT 31 /**< Shift value for BUFC_BUSERROR */
+#define _BUFC_SEQIF_BUSERROR_MASK 0x80000000UL /**< Bit mask for BUFC_BUSERROR */
+#define _BUFC_SEQIF_BUSERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
+#define BUFC_SEQIF_BUSERROR_DEFAULT (_BUFC_SEQIF_BUSERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for BUFC_SEQIF */
+
+/* Bit fields for BUFC SEQIEN */
+#define _BUFC_SEQIEN_RESETVALUE 0x00000000UL /**< Default value for BUFC_SEQIEN */
+#define _BUFC_SEQIEN_MASK 0x9F1F1F1FUL /**< Mask for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF0OF (0x1UL << 0) /**< BUF0OF Interrupt Enable */
+#define _BUFC_SEQIEN_BUF0OF_SHIFT 0 /**< Shift value for BUFC_BUF0OF */
+#define _BUFC_SEQIEN_BUF0OF_MASK 0x1UL /**< Bit mask for BUFC_BUF0OF */
+#define _BUFC_SEQIEN_BUF0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF0OF_DEFAULT (_BUFC_SEQIEN_BUF0OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF0UF (0x1UL << 1) /**< BUF0UF Interrupt Enable */
+#define _BUFC_SEQIEN_BUF0UF_SHIFT 1 /**< Shift value for BUFC_BUF0UF */
+#define _BUFC_SEQIEN_BUF0UF_MASK 0x2UL /**< Bit mask for BUFC_BUF0UF */
+#define _BUFC_SEQIEN_BUF0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF0UF_DEFAULT (_BUFC_SEQIEN_BUF0UF_DEFAULT << 1) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF0THR (0x1UL << 2) /**< BUF0THR Interrupt Enable */
+#define _BUFC_SEQIEN_BUF0THR_SHIFT 2 /**< Shift value for BUFC_BUF0THR */
+#define _BUFC_SEQIEN_BUF0THR_MASK 0x4UL /**< Bit mask for BUFC_BUF0THR */
+#define _BUFC_SEQIEN_BUF0THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF0THR_DEFAULT (_BUFC_SEQIEN_BUF0THR_DEFAULT << 2) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF0CORR (0x1UL << 3) /**< BUF0CORR Interrupt Enable */
+#define _BUFC_SEQIEN_BUF0CORR_SHIFT 3 /**< Shift value for BUFC_BUF0CORR */
+#define _BUFC_SEQIEN_BUF0CORR_MASK 0x8UL /**< Bit mask for BUFC_BUF0CORR */
+#define _BUFC_SEQIEN_BUF0CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF0CORR_DEFAULT (_BUFC_SEQIEN_BUF0CORR_DEFAULT << 3) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF0NWA (0x1UL << 4) /**< BUF0NWA Interrupt Enable */
+#define _BUFC_SEQIEN_BUF0NWA_SHIFT 4 /**< Shift value for BUFC_BUF0NWA */
+#define _BUFC_SEQIEN_BUF0NWA_MASK 0x10UL /**< Bit mask for BUFC_BUF0NWA */
+#define _BUFC_SEQIEN_BUF0NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF0NWA_DEFAULT (_BUFC_SEQIEN_BUF0NWA_DEFAULT << 4) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF1OF (0x1UL << 8) /**< BUF1OF Interrupt Enable */
+#define _BUFC_SEQIEN_BUF1OF_SHIFT 8 /**< Shift value for BUFC_BUF1OF */
+#define _BUFC_SEQIEN_BUF1OF_MASK 0x100UL /**< Bit mask for BUFC_BUF1OF */
+#define _BUFC_SEQIEN_BUF1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF1OF_DEFAULT (_BUFC_SEQIEN_BUF1OF_DEFAULT << 8) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF1UF (0x1UL << 9) /**< BUF1UF Interrupt Enable */
+#define _BUFC_SEQIEN_BUF1UF_SHIFT 9 /**< Shift value for BUFC_BUF1UF */
+#define _BUFC_SEQIEN_BUF1UF_MASK 0x200UL /**< Bit mask for BUFC_BUF1UF */
+#define _BUFC_SEQIEN_BUF1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF1UF_DEFAULT (_BUFC_SEQIEN_BUF1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF1THR (0x1UL << 10) /**< BUF1THR Interrupt Enable */
+#define _BUFC_SEQIEN_BUF1THR_SHIFT 10 /**< Shift value for BUFC_BUF1THR */
+#define _BUFC_SEQIEN_BUF1THR_MASK 0x400UL /**< Bit mask for BUFC_BUF1THR */
+#define _BUFC_SEQIEN_BUF1THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF1THR_DEFAULT (_BUFC_SEQIEN_BUF1THR_DEFAULT << 10) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF1CORR (0x1UL << 11) /**< BUF1CORR Interrupt Enable */
+#define _BUFC_SEQIEN_BUF1CORR_SHIFT 11 /**< Shift value for BUFC_BUF1CORR */
+#define _BUFC_SEQIEN_BUF1CORR_MASK 0x800UL /**< Bit mask for BUFC_BUF1CORR */
+#define _BUFC_SEQIEN_BUF1CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF1CORR_DEFAULT (_BUFC_SEQIEN_BUF1CORR_DEFAULT << 11) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF1NWA (0x1UL << 12) /**< BUF1NWA Interrupt Enable */
+#define _BUFC_SEQIEN_BUF1NWA_SHIFT 12 /**< Shift value for BUFC_BUF1NWA */
+#define _BUFC_SEQIEN_BUF1NWA_MASK 0x1000UL /**< Bit mask for BUFC_BUF1NWA */
+#define _BUFC_SEQIEN_BUF1NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF1NWA_DEFAULT (_BUFC_SEQIEN_BUF1NWA_DEFAULT << 12) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF2OF (0x1UL << 16) /**< BUF2OF Interrupt Enable */
+#define _BUFC_SEQIEN_BUF2OF_SHIFT 16 /**< Shift value for BUFC_BUF2OF */
+#define _BUFC_SEQIEN_BUF2OF_MASK 0x10000UL /**< Bit mask for BUFC_BUF2OF */
+#define _BUFC_SEQIEN_BUF2OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF2OF_DEFAULT (_BUFC_SEQIEN_BUF2OF_DEFAULT << 16) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF2UF (0x1UL << 17) /**< BUF2UF Interrupt Enable */
+#define _BUFC_SEQIEN_BUF2UF_SHIFT 17 /**< Shift value for BUFC_BUF2UF */
+#define _BUFC_SEQIEN_BUF2UF_MASK 0x20000UL /**< Bit mask for BUFC_BUF2UF */
+#define _BUFC_SEQIEN_BUF2UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF2UF_DEFAULT (_BUFC_SEQIEN_BUF2UF_DEFAULT << 17) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF2THR (0x1UL << 18) /**< BUF2THR Interrupt Enable */
+#define _BUFC_SEQIEN_BUF2THR_SHIFT 18 /**< Shift value for BUFC_BUF2THR */
+#define _BUFC_SEQIEN_BUF2THR_MASK 0x40000UL /**< Bit mask for BUFC_BUF2THR */
+#define _BUFC_SEQIEN_BUF2THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF2THR_DEFAULT (_BUFC_SEQIEN_BUF2THR_DEFAULT << 18) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF2CORR (0x1UL << 19) /**< BUF2CORR Interrupt Enable */
+#define _BUFC_SEQIEN_BUF2CORR_SHIFT 19 /**< Shift value for BUFC_BUF2CORR */
+#define _BUFC_SEQIEN_BUF2CORR_MASK 0x80000UL /**< Bit mask for BUFC_BUF2CORR */
+#define _BUFC_SEQIEN_BUF2CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF2CORR_DEFAULT (_BUFC_SEQIEN_BUF2CORR_DEFAULT << 19) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF2NWA (0x1UL << 20) /**< BUF2NWA Interrupt Enable */
+#define _BUFC_SEQIEN_BUF2NWA_SHIFT 20 /**< Shift value for BUFC_BUF2NWA */
+#define _BUFC_SEQIEN_BUF2NWA_MASK 0x100000UL /**< Bit mask for BUFC_BUF2NWA */
+#define _BUFC_SEQIEN_BUF2NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF2NWA_DEFAULT (_BUFC_SEQIEN_BUF2NWA_DEFAULT << 20) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF3OF (0x1UL << 24) /**< BUF3OF Interrupt Enable */
+#define _BUFC_SEQIEN_BUF3OF_SHIFT 24 /**< Shift value for BUFC_BUF3OF */
+#define _BUFC_SEQIEN_BUF3OF_MASK 0x1000000UL /**< Bit mask for BUFC_BUF3OF */
+#define _BUFC_SEQIEN_BUF3OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF3OF_DEFAULT (_BUFC_SEQIEN_BUF3OF_DEFAULT << 24) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF3UF (0x1UL << 25) /**< BUF3UF Interrupt Enable */
+#define _BUFC_SEQIEN_BUF3UF_SHIFT 25 /**< Shift value for BUFC_BUF3UF */
+#define _BUFC_SEQIEN_BUF3UF_MASK 0x2000000UL /**< Bit mask for BUFC_BUF3UF */
+#define _BUFC_SEQIEN_BUF3UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF3UF_DEFAULT (_BUFC_SEQIEN_BUF3UF_DEFAULT << 25) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF3THR (0x1UL << 26) /**< BUF3THR Interrupt Enable */
+#define _BUFC_SEQIEN_BUF3THR_SHIFT 26 /**< Shift value for BUFC_BUF3THR */
+#define _BUFC_SEQIEN_BUF3THR_MASK 0x4000000UL /**< Bit mask for BUFC_BUF3THR */
+#define _BUFC_SEQIEN_BUF3THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF3THR_DEFAULT (_BUFC_SEQIEN_BUF3THR_DEFAULT << 26) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF3CORR (0x1UL << 27) /**< BUF3CORR Interrupt Enable */
+#define _BUFC_SEQIEN_BUF3CORR_SHIFT 27 /**< Shift value for BUFC_BUF3CORR */
+#define _BUFC_SEQIEN_BUF3CORR_MASK 0x8000000UL /**< Bit mask for BUFC_BUF3CORR */
+#define _BUFC_SEQIEN_BUF3CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF3CORR_DEFAULT (_BUFC_SEQIEN_BUF3CORR_DEFAULT << 27) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF3NWA (0x1UL << 28) /**< BUF3NWA Interrupt Enable */
+#define _BUFC_SEQIEN_BUF3NWA_SHIFT 28 /**< Shift value for BUFC_BUF3NWA */
+#define _BUFC_SEQIEN_BUF3NWA_MASK 0x10000000UL /**< Bit mask for BUFC_BUF3NWA */
+#define _BUFC_SEQIEN_BUF3NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUF3NWA_DEFAULT (_BUFC_SEQIEN_BUF3NWA_DEFAULT << 28) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUSERROR (0x1UL << 31) /**< BUSERROR Interrupt Enable */
+#define _BUFC_SEQIEN_BUSERROR_SHIFT 31 /**< Shift value for BUFC_BUSERROR */
+#define _BUFC_SEQIEN_BUSERROR_MASK 0x80000000UL /**< Bit mask for BUFC_BUSERROR */
+#define _BUFC_SEQIEN_BUSERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
+#define BUFC_SEQIEN_BUSERROR_DEFAULT (_BUFC_SEQIEN_BUSERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
+
+/* Bit fields for BUFC AHBCONFIG */
+#define _BUFC_AHBCONFIG_RESETVALUE 0x00000001UL /**< Default value for BUFC_AHBCONFIG */
+#define _BUFC_AHBCONFIG_MASK 0x00000001UL /**< Mask for BUFC_AHBCONFIG */
+#define BUFC_AHBCONFIG_AHBHPROTBUFFERABLE (0x1UL << 0) /**< Bufferable privileged AHB */
+#define _BUFC_AHBCONFIG_AHBHPROTBUFFERABLE_SHIFT 0 /**< Shift value for BUFC_AHBHPROTBUFFERABLE */
+#define _BUFC_AHBCONFIG_AHBHPROTBUFFERABLE_MASK 0x1UL /**< Bit mask for BUFC_AHBHPROTBUFFERABLE */
+#define _BUFC_AHBCONFIG_AHBHPROTBUFFERABLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for BUFC_AHBCONFIG */
+#define BUFC_AHBCONFIG_AHBHPROTBUFFERABLE_DEFAULT (_BUFC_AHBCONFIG_AHBHPROTBUFFERABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_AHBCONFIG */
+
+/** @} End of group EFR32MG24_BUFC_BitFields */
+/** @} End of group EFR32MG24_BUFC */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_BUFC_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_buram.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_buram.h
new file mode 100644
index 00000000..e6d6d8bf
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_buram.h
@@ -0,0 +1,80 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 BURAM register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_BURAM_H
+#define EFR32MG24_BURAM_H
+#define BURAM_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_BURAM BURAM
+ * @{
+ * @brief EFR32MG24 BURAM Register Declaration.
+ *****************************************************************************/
+
+/** BURAM RET Register Group Declaration. */
+typedef struct {
+ __IOM uint32_t REG; /**< Retention Register */
+} BURAM_RET_TypeDef;
+
+/** BURAM Register Declaration. */
+typedef struct {
+ BURAM_RET_TypeDef RET[32U]; /**< RetentionReg */
+ uint32_t RESERVED0[992U]; /**< Reserved for future use */
+ BURAM_RET_TypeDef RET_SET[32U]; /**< RetentionReg */
+ uint32_t RESERVED1[992U]; /**< Reserved for future use */
+ BURAM_RET_TypeDef RET_CLR[32U]; /**< RetentionReg */
+ uint32_t RESERVED2[992U]; /**< Reserved for future use */
+ BURAM_RET_TypeDef RET_TGL[32U]; /**< RetentionReg */
+} BURAM_TypeDef;
+/** @} End of group EFR32MG24_BURAM */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_BURAM
+ * @{
+ * @defgroup EFR32MG24_BURAM_BitFields BURAM Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for BURAM RET_REG */
+#define _BURAM_RET_REG_RESETVALUE 0x00000000UL /**< Default value for BURAM_RET_REG */
+#define _BURAM_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for BURAM_RET_REG */
+#define _BURAM_RET_REG_RETREG_SHIFT 0 /**< Shift value for BURAM_RETREG */
+#define _BURAM_RET_REG_RETREG_MASK 0xFFFFFFFFUL /**< Bit mask for BURAM_RETREG */
+#define _BURAM_RET_REG_RETREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURAM_RET_REG */
+#define BURAM_RET_REG_RETREG_DEFAULT (_BURAM_RET_REG_RETREG_DEFAULT << 0) /**< Shifted mode DEFAULT for BURAM_RET_REG */
+
+/** @} End of group EFR32MG24_BURAM_BitFields */
+/** @} End of group EFR32MG24_BURAM */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_BURAM_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_burtc.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_burtc.h
new file mode 100644
index 00000000..bb3029e0
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_burtc.h
@@ -0,0 +1,332 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 BURTC register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_BURTC_H
+#define EFR32MG24_BURTC_H
+#define BURTC_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_BURTC BURTC
+ * @{
+ * @brief EFR32MG24 BURTC Register Declaration.
+ *****************************************************************************/
+
+/** BURTC Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IP version ID */
+ __IOM uint32_t EN; /**< Module Enable Register */
+ __IOM uint32_t CFG; /**< Configuration Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IOM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */
+ __IOM uint32_t CNT; /**< Counter Value Register */
+ __IOM uint32_t EM4WUEN; /**< EM4 wakeup request Enable Register */
+ __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
+ __IOM uint32_t LOCK; /**< Configuration Lock Register */
+ __IOM uint32_t COMP; /**< Compare Value Register */
+ uint32_t RESERVED0[1011U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP version ID */
+ __IOM uint32_t EN_SET; /**< Module Enable Register */
+ __IOM uint32_t CFG_SET; /**< Configuration Register */
+ __IOM uint32_t CMD_SET; /**< Command Register */
+ __IM uint32_t STATUS_SET; /**< Status Register */
+ __IOM uint32_t IF_SET; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
+ __IOM uint32_t PRECNT_SET; /**< Pre-Counter Value Register */
+ __IOM uint32_t CNT_SET; /**< Counter Value Register */
+ __IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup request Enable Register */
+ __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */
+ __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */
+ __IOM uint32_t COMP_SET; /**< Compare Value Register */
+ uint32_t RESERVED1[1011U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP version ID */
+ __IOM uint32_t EN_CLR; /**< Module Enable Register */
+ __IOM uint32_t CFG_CLR; /**< Configuration Register */
+ __IOM uint32_t CMD_CLR; /**< Command Register */
+ __IM uint32_t STATUS_CLR; /**< Status Register */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
+ __IOM uint32_t PRECNT_CLR; /**< Pre-Counter Value Register */
+ __IOM uint32_t CNT_CLR; /**< Counter Value Register */
+ __IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup request Enable Register */
+ __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */
+ __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */
+ __IOM uint32_t COMP_CLR; /**< Compare Value Register */
+ uint32_t RESERVED2[1011U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP version ID */
+ __IOM uint32_t EN_TGL; /**< Module Enable Register */
+ __IOM uint32_t CFG_TGL; /**< Configuration Register */
+ __IOM uint32_t CMD_TGL; /**< Command Register */
+ __IM uint32_t STATUS_TGL; /**< Status Register */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
+ __IOM uint32_t PRECNT_TGL; /**< Pre-Counter Value Register */
+ __IOM uint32_t CNT_TGL; /**< Counter Value Register */
+ __IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup request Enable Register */
+ __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */
+ __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */
+ __IOM uint32_t COMP_TGL; /**< Compare Value Register */
+} BURTC_TypeDef;
+/** @} End of group EFR32MG24_BURTC */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_BURTC
+ * @{
+ * @defgroup EFR32MG24_BURTC_BitFields BURTC Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for BURTC IPVERSION */
+#define _BURTC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for BURTC_IPVERSION */
+#define _BURTC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for BURTC_IPVERSION */
+#define _BURTC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for BURTC_IPVERSION */
+#define _BURTC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_IPVERSION */
+#define _BURTC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for BURTC_IPVERSION */
+#define BURTC_IPVERSION_IPVERSION_DEFAULT (_BURTC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IPVERSION */
+
+/* Bit fields for BURTC EN */
+#define _BURTC_EN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EN */
+#define _BURTC_EN_MASK 0x00000003UL /**< Mask for BURTC_EN */
+#define BURTC_EN_EN (0x1UL << 0) /**< BURTC Enable */
+#define _BURTC_EN_EN_SHIFT 0 /**< Shift value for BURTC_EN */
+#define _BURTC_EN_EN_MASK 0x1UL /**< Bit mask for BURTC_EN */
+#define _BURTC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EN */
+#define BURTC_EN_EN_DEFAULT (_BURTC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EN */
+#define BURTC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */
+#define _BURTC_EN_DISABLING_SHIFT 1 /**< Shift value for BURTC_DISABLING */
+#define _BURTC_EN_DISABLING_MASK 0x2UL /**< Bit mask for BURTC_DISABLING */
+#define _BURTC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EN */
+#define BURTC_EN_DISABLING_DEFAULT (_BURTC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_EN */
+
+/* Bit fields for BURTC CFG */
+#define _BURTC_CFG_RESETVALUE 0x00000000UL /**< Default value for BURTC_CFG */
+#define _BURTC_CFG_MASK 0x000000F3UL /**< Mask for BURTC_CFG */
+#define BURTC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */
+#define _BURTC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for BURTC_DEBUGRUN */
+#define _BURTC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for BURTC_DEBUGRUN */
+#define _BURTC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */
+#define _BURTC_CFG_DEBUGRUN_X0 0x00000000UL /**< Mode X0 for BURTC_CFG */
+#define _BURTC_CFG_DEBUGRUN_X1 0x00000001UL /**< Mode X1 for BURTC_CFG */
+#define BURTC_CFG_DEBUGRUN_DEFAULT (_BURTC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CFG */
+#define BURTC_CFG_DEBUGRUN_X0 (_BURTC_CFG_DEBUGRUN_X0 << 0) /**< Shifted mode X0 for BURTC_CFG */
+#define BURTC_CFG_DEBUGRUN_X1 (_BURTC_CFG_DEBUGRUN_X1 << 0) /**< Shifted mode X1 for BURTC_CFG */
+#define BURTC_CFG_COMPTOP (0x1UL << 1) /**< Compare Channel is Top Value */
+#define _BURTC_CFG_COMPTOP_SHIFT 1 /**< Shift value for BURTC_COMPTOP */
+#define _BURTC_CFG_COMPTOP_MASK 0x2UL /**< Bit mask for BURTC_COMPTOP */
+#define _BURTC_CFG_COMPTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */
+#define _BURTC_CFG_COMPTOP_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_CFG */
+#define _BURTC_CFG_COMPTOP_ENABLE 0x00000001UL /**< Mode ENABLE for BURTC_CFG */
+#define BURTC_CFG_COMPTOP_DEFAULT (_BURTC_CFG_COMPTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CFG */
+#define BURTC_CFG_COMPTOP_DISABLE (_BURTC_CFG_COMPTOP_DISABLE << 1) /**< Shifted mode DISABLE for BURTC_CFG */
+#define BURTC_CFG_COMPTOP_ENABLE (_BURTC_CFG_COMPTOP_ENABLE << 1) /**< Shifted mode ENABLE for BURTC_CFG */
+#define _BURTC_CFG_CNTPRESC_SHIFT 4 /**< Shift value for BURTC_CNTPRESC */
+#define _BURTC_CFG_CNTPRESC_MASK 0xF0UL /**< Bit mask for BURTC_CNTPRESC */
+#define _BURTC_CFG_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */
+#define _BURTC_CFG_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for BURTC_CFG */
+#define _BURTC_CFG_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for BURTC_CFG */
+#define _BURTC_CFG_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for BURTC_CFG */
+#define _BURTC_CFG_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for BURTC_CFG */
+#define _BURTC_CFG_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for BURTC_CFG */
+#define _BURTC_CFG_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for BURTC_CFG */
+#define _BURTC_CFG_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for BURTC_CFG */
+#define _BURTC_CFG_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for BURTC_CFG */
+#define _BURTC_CFG_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for BURTC_CFG */
+#define _BURTC_CFG_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for BURTC_CFG */
+#define _BURTC_CFG_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for BURTC_CFG */
+#define _BURTC_CFG_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for BURTC_CFG */
+#define _BURTC_CFG_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for BURTC_CFG */
+#define _BURTC_CFG_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for BURTC_CFG */
+#define _BURTC_CFG_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for BURTC_CFG */
+#define _BURTC_CFG_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for BURTC_CFG */
+#define BURTC_CFG_CNTPRESC_DEFAULT (_BURTC_CFG_CNTPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_CFG */
+#define BURTC_CFG_CNTPRESC_DIV1 (_BURTC_CFG_CNTPRESC_DIV1 << 4) /**< Shifted mode DIV1 for BURTC_CFG */
+#define BURTC_CFG_CNTPRESC_DIV2 (_BURTC_CFG_CNTPRESC_DIV2 << 4) /**< Shifted mode DIV2 for BURTC_CFG */
+#define BURTC_CFG_CNTPRESC_DIV4 (_BURTC_CFG_CNTPRESC_DIV4 << 4) /**< Shifted mode DIV4 for BURTC_CFG */
+#define BURTC_CFG_CNTPRESC_DIV8 (_BURTC_CFG_CNTPRESC_DIV8 << 4) /**< Shifted mode DIV8 for BURTC_CFG */
+#define BURTC_CFG_CNTPRESC_DIV16 (_BURTC_CFG_CNTPRESC_DIV16 << 4) /**< Shifted mode DIV16 for BURTC_CFG */
+#define BURTC_CFG_CNTPRESC_DIV32 (_BURTC_CFG_CNTPRESC_DIV32 << 4) /**< Shifted mode DIV32 for BURTC_CFG */
+#define BURTC_CFG_CNTPRESC_DIV64 (_BURTC_CFG_CNTPRESC_DIV64 << 4) /**< Shifted mode DIV64 for BURTC_CFG */
+#define BURTC_CFG_CNTPRESC_DIV128 (_BURTC_CFG_CNTPRESC_DIV128 << 4) /**< Shifted mode DIV128 for BURTC_CFG */
+#define BURTC_CFG_CNTPRESC_DIV256 (_BURTC_CFG_CNTPRESC_DIV256 << 4) /**< Shifted mode DIV256 for BURTC_CFG */
+#define BURTC_CFG_CNTPRESC_DIV512 (_BURTC_CFG_CNTPRESC_DIV512 << 4) /**< Shifted mode DIV512 for BURTC_CFG */
+#define BURTC_CFG_CNTPRESC_DIV1024 (_BURTC_CFG_CNTPRESC_DIV1024 << 4) /**< Shifted mode DIV1024 for BURTC_CFG */
+#define BURTC_CFG_CNTPRESC_DIV2048 (_BURTC_CFG_CNTPRESC_DIV2048 << 4) /**< Shifted mode DIV2048 for BURTC_CFG */
+#define BURTC_CFG_CNTPRESC_DIV4096 (_BURTC_CFG_CNTPRESC_DIV4096 << 4) /**< Shifted mode DIV4096 for BURTC_CFG */
+#define BURTC_CFG_CNTPRESC_DIV8192 (_BURTC_CFG_CNTPRESC_DIV8192 << 4) /**< Shifted mode DIV8192 for BURTC_CFG */
+#define BURTC_CFG_CNTPRESC_DIV16384 (_BURTC_CFG_CNTPRESC_DIV16384 << 4) /**< Shifted mode DIV16384 for BURTC_CFG */
+#define BURTC_CFG_CNTPRESC_DIV32768 (_BURTC_CFG_CNTPRESC_DIV32768 << 4) /**< Shifted mode DIV32768 for BURTC_CFG */
+
+/* Bit fields for BURTC CMD */
+#define _BURTC_CMD_RESETVALUE 0x00000000UL /**< Default value for BURTC_CMD */
+#define _BURTC_CMD_MASK 0x00000003UL /**< Mask for BURTC_CMD */
+#define BURTC_CMD_START (0x1UL << 0) /**< Start BURTC counter */
+#define _BURTC_CMD_START_SHIFT 0 /**< Shift value for BURTC_START */
+#define _BURTC_CMD_START_MASK 0x1UL /**< Bit mask for BURTC_START */
+#define _BURTC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */
+#define BURTC_CMD_START_DEFAULT (_BURTC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CMD */
+#define BURTC_CMD_STOP (0x1UL << 1) /**< Stop BURTC counter */
+#define _BURTC_CMD_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */
+#define _BURTC_CMD_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */
+#define _BURTC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */
+#define BURTC_CMD_STOP_DEFAULT (_BURTC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CMD */
+
+/* Bit fields for BURTC STATUS */
+#define _BURTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for BURTC_STATUS */
+#define _BURTC_STATUS_MASK 0x00000003UL /**< Mask for BURTC_STATUS */
+#define BURTC_STATUS_RUNNING (0x1UL << 0) /**< BURTC running status */
+#define _BURTC_STATUS_RUNNING_SHIFT 0 /**< Shift value for BURTC_RUNNING */
+#define _BURTC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for BURTC_RUNNING */
+#define _BURTC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */
+#define BURTC_STATUS_RUNNING_DEFAULT (_BURTC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_STATUS */
+#define BURTC_STATUS_LOCK (0x1UL << 1) /**< Configuration Lock Status */
+#define _BURTC_STATUS_LOCK_SHIFT 1 /**< Shift value for BURTC_LOCK */
+#define _BURTC_STATUS_LOCK_MASK 0x2UL /**< Bit mask for BURTC_LOCK */
+#define _BURTC_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */
+#define _BURTC_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for BURTC_STATUS */
+#define _BURTC_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for BURTC_STATUS */
+#define BURTC_STATUS_LOCK_DEFAULT (_BURTC_STATUS_LOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_STATUS */
+#define BURTC_STATUS_LOCK_UNLOCKED (_BURTC_STATUS_LOCK_UNLOCKED << 1) /**< Shifted mode UNLOCKED for BURTC_STATUS */
+#define BURTC_STATUS_LOCK_LOCKED (_BURTC_STATUS_LOCK_LOCKED << 1) /**< Shifted mode LOCKED for BURTC_STATUS */
+
+/* Bit fields for BURTC IF */
+#define _BURTC_IF_RESETVALUE 0x00000000UL /**< Default value for BURTC_IF */
+#define _BURTC_IF_MASK 0x00000003UL /**< Mask for BURTC_IF */
+#define BURTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */
+#define _BURTC_IF_OF_SHIFT 0 /**< Shift value for BURTC_OF */
+#define _BURTC_IF_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */
+#define _BURTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */
+#define BURTC_IF_OF_DEFAULT (_BURTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IF */
+#define BURTC_IF_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */
+#define _BURTC_IF_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */
+#define _BURTC_IF_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */
+#define _BURTC_IF_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */
+#define BURTC_IF_COMP_DEFAULT (_BURTC_IF_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IF */
+
+/* Bit fields for BURTC IEN */
+#define _BURTC_IEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_IEN */
+#define _BURTC_IEN_MASK 0x00000003UL /**< Mask for BURTC_IEN */
+#define BURTC_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Flag */
+#define _BURTC_IEN_OF_SHIFT 0 /**< Shift value for BURTC_OF */
+#define _BURTC_IEN_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */
+#define _BURTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */
+#define BURTC_IEN_OF_DEFAULT (_BURTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IEN */
+#define BURTC_IEN_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */
+#define _BURTC_IEN_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */
+#define _BURTC_IEN_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */
+#define _BURTC_IEN_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */
+#define BURTC_IEN_COMP_DEFAULT (_BURTC_IEN_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IEN */
+
+/* Bit fields for BURTC PRECNT */
+#define _BURTC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_PRECNT */
+#define _BURTC_PRECNT_MASK 0x00007FFFUL /**< Mask for BURTC_PRECNT */
+#define _BURTC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for BURTC_PRECNT */
+#define _BURTC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for BURTC_PRECNT */
+#define _BURTC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_PRECNT */
+#define BURTC_PRECNT_PRECNT_DEFAULT (_BURTC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_PRECNT */
+
+/* Bit fields for BURTC CNT */
+#define _BURTC_CNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_CNT */
+#define _BURTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for BURTC_CNT */
+#define _BURTC_CNT_CNT_SHIFT 0 /**< Shift value for BURTC_CNT */
+#define _BURTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_CNT */
+#define _BURTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CNT */
+#define BURTC_CNT_CNT_DEFAULT (_BURTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CNT */
+
+/* Bit fields for BURTC EM4WUEN */
+#define _BURTC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EM4WUEN */
+#define _BURTC_EM4WUEN_MASK 0x00000003UL /**< Mask for BURTC_EM4WUEN */
+#define BURTC_EM4WUEN_OFEM4WUEN (0x1UL << 0) /**< Overflow EM4 Wakeup Enable */
+#define _BURTC_EM4WUEN_OFEM4WUEN_SHIFT 0 /**< Shift value for BURTC_OFEM4WUEN */
+#define _BURTC_EM4WUEN_OFEM4WUEN_MASK 0x1UL /**< Bit mask for BURTC_OFEM4WUEN */
+#define _BURTC_EM4WUEN_OFEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */
+#define BURTC_EM4WUEN_OFEM4WUEN_DEFAULT (_BURTC_EM4WUEN_OFEM4WUEN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */
+#define BURTC_EM4WUEN_COMPEM4WUEN (0x1UL << 1) /**< Compare Match EM4 Wakeup Enable */
+#define _BURTC_EM4WUEN_COMPEM4WUEN_SHIFT 1 /**< Shift value for BURTC_COMPEM4WUEN */
+#define _BURTC_EM4WUEN_COMPEM4WUEN_MASK 0x2UL /**< Bit mask for BURTC_COMPEM4WUEN */
+#define _BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */
+#define BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT (_BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */
+
+/* Bit fields for BURTC SYNCBUSY */
+#define _BURTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for BURTC_SYNCBUSY */
+#define _BURTC_SYNCBUSY_MASK 0x0000001FUL /**< Mask for BURTC_SYNCBUSY */
+#define BURTC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START */
+#define _BURTC_SYNCBUSY_START_SHIFT 0 /**< Shift value for BURTC_START */
+#define _BURTC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for BURTC_START */
+#define _BURTC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */
+#define BURTC_SYNCBUSY_START_DEFAULT (_BURTC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */
+#define BURTC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP */
+#define _BURTC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */
+#define _BURTC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */
+#define _BURTC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */
+#define BURTC_SYNCBUSY_STOP_DEFAULT (_BURTC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */
+#define BURTC_SYNCBUSY_PRECNT (0x1UL << 2) /**< Sync busy for PRECNT */
+#define _BURTC_SYNCBUSY_PRECNT_SHIFT 2 /**< Shift value for BURTC_PRECNT */
+#define _BURTC_SYNCBUSY_PRECNT_MASK 0x4UL /**< Bit mask for BURTC_PRECNT */
+#define _BURTC_SYNCBUSY_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */
+#define BURTC_SYNCBUSY_PRECNT_DEFAULT (_BURTC_SYNCBUSY_PRECNT_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */
+#define BURTC_SYNCBUSY_CNT (0x1UL << 3) /**< Sync busy for CNT */
+#define _BURTC_SYNCBUSY_CNT_SHIFT 3 /**< Shift value for BURTC_CNT */
+#define _BURTC_SYNCBUSY_CNT_MASK 0x8UL /**< Bit mask for BURTC_CNT */
+#define _BURTC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */
+#define BURTC_SYNCBUSY_CNT_DEFAULT (_BURTC_SYNCBUSY_CNT_DEFAULT << 3) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */
+#define BURTC_SYNCBUSY_COMP (0x1UL << 4) /**< Sync busy for COMP */
+#define _BURTC_SYNCBUSY_COMP_SHIFT 4 /**< Shift value for BURTC_COMP */
+#define _BURTC_SYNCBUSY_COMP_MASK 0x10UL /**< Bit mask for BURTC_COMP */
+#define _BURTC_SYNCBUSY_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */
+#define BURTC_SYNCBUSY_COMP_DEFAULT (_BURTC_SYNCBUSY_COMP_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */
+
+/* Bit fields for BURTC LOCK */
+#define _BURTC_LOCK_RESETVALUE 0x0000AEE8UL /**< Default value for BURTC_LOCK */
+#define _BURTC_LOCK_MASK 0x0000FFFFUL /**< Mask for BURTC_LOCK */
+#define _BURTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for BURTC_LOCKKEY */
+#define _BURTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for BURTC_LOCKKEY */
+#define _BURTC_LOCK_LOCKKEY_DEFAULT 0x0000AEE8UL /**< Mode DEFAULT for BURTC_LOCK */
+#define _BURTC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for BURTC_LOCK */
+#define BURTC_LOCK_LOCKKEY_DEFAULT (_BURTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_LOCK */
+#define BURTC_LOCK_LOCKKEY_UNLOCK (_BURTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for BURTC_LOCK */
+
+/* Bit fields for BURTC COMP */
+#define _BURTC_COMP_RESETVALUE 0x00000000UL /**< Default value for BURTC_COMP */
+#define _BURTC_COMP_MASK 0xFFFFFFFFUL /**< Mask for BURTC_COMP */
+#define _BURTC_COMP_COMP_SHIFT 0 /**< Shift value for BURTC_COMP */
+#define _BURTC_COMP_COMP_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_COMP */
+#define _BURTC_COMP_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_COMP */
+#define BURTC_COMP_COMP_DEFAULT (_BURTC_COMP_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_COMP */
+
+/** @} End of group EFR32MG24_BURTC_BitFields */
+/** @} End of group EFR32MG24_BURTC */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_BURTC_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_cmu.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_cmu.h
new file mode 100644
index 00000000..b5995d4b
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_cmu.h
@@ -0,0 +1,1121 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 CMU register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_CMU_H
+#define EFR32MG24_CMU_H
+#define CMU_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_CMU CMU
+ * @{
+ * @brief EFR32MG24 CMU Register Declaration.
+ *****************************************************************************/
+
+/** CMU Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IP version ID */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+ __IM uint32_t STATUS; /**< Status Register */
+ uint32_t RESERVED1[1U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK; /**< Configuration Lock Register */
+ __IOM uint32_t WDOGLOCK; /**< WDOG Configuration Lock Register */
+ uint32_t RESERVED2[2U]; /**< Reserved for future use */
+ __IOM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ uint32_t RESERVED3[10U]; /**< Reserved for future use */
+ __IOM uint32_t CALCMD; /**< Calibration Command Register */
+ __IOM uint32_t CALCTRL; /**< Calibration Control Register */
+ __IM uint32_t CALCNT; /**< Calibration Result Counter Register */
+ uint32_t RESERVED4[2U]; /**< Reserved for future use */
+ __IOM uint32_t CLKEN0; /**< Clock Enable Register 0 */
+ __IOM uint32_t CLKEN1; /**< Clock Enable Register 1 */
+ uint32_t RESERVED5[1U]; /**< Reserved for future use */
+ __IOM uint32_t SYSCLKCTRL; /**< System Clock Control */
+ uint32_t RESERVED6[3U]; /**< Reserved for future use */
+ __IOM uint32_t TRACECLKCTRL; /**< Debug Trace Clock Control */
+ uint32_t RESERVED7[3U]; /**< Reserved for future use */
+ __IOM uint32_t EXPORTCLKCTRL; /**< Export Clock Control */
+ uint32_t RESERVED8[27U]; /**< Reserved for future use */
+ __IOM uint32_t DPLLREFCLKCTRL; /**< Digital PLL Reference Clock Control */
+ uint32_t RESERVED9[7U]; /**< Reserved for future use */
+ __IOM uint32_t EM01GRPACLKCTRL; /**< EM01 Peripheral Group A Clock Control */
+ uint32_t RESERVED10[1U]; /**< Reserved for future use */
+ __IOM uint32_t EM01GRPCCLKCTRL; /**< EM01 Peripheral Group C Clock Control */
+ uint32_t RESERVED11[5U]; /**< Reserved for future use */
+ __IOM uint32_t EM23GRPACLKCTRL; /**< EM23 Peripheral Group A Clock Control */
+ uint32_t RESERVED12[7U]; /**< Reserved for future use */
+ __IOM uint32_t EM4GRPACLKCTRL; /**< EM4 Peripheral Group A Clock Control */
+ uint32_t RESERVED13[7U]; /**< Reserved for future use */
+ __IOM uint32_t IADCCLKCTRL; /**< IADC Clock Control */
+ uint32_t RESERVED14[31U]; /**< Reserved for future use */
+ __IOM uint32_t WDOG0CLKCTRL; /**< Watchdog0 Clock Control */
+ uint32_t RESERVED15[1U]; /**< Reserved for future use */
+ __IOM uint32_t WDOG1CLKCTRL; /**< Watchdog1 Clock Control */
+ uint32_t RESERVED16[5U]; /**< Reserved for future use */
+ __IOM uint32_t EUSART0CLKCTRL; /**< EUSART0 Clock Control */
+ uint32_t RESERVED17[7U]; /**< Reserved for future use */
+ __IOM uint32_t SYSRTC0CLKCTRL; /**< System RTC0 Clock Control */
+ uint32_t RESERVED18[7U]; /**< Reserved for future use */
+ __IOM uint32_t VDAC0CLKCTRL; /**< VDAC0 Clock Control */
+ uint32_t RESERVED19[3U]; /**< Reserved for future use */
+ __IOM uint32_t PCNT0CLKCTRL; /**< Pulse counter 0 Clock Control */
+ uint32_t RESERVED20[3U]; /**< Reserved for future use */
+ __IOM uint32_t RADIOCLKCTRL; /**< Radio Clock Control */
+ uint32_t RESERVED21[4U]; /**< Reserved for future use */
+ __IOM uint32_t VDAC1CLKCTRL; /**< VDAC1 Clock Control */
+ uint32_t RESERVED22[1U]; /**< Reserved for future use */
+ uint32_t RESERVED23[857U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP version ID */
+ uint32_t RESERVED24[1U]; /**< Reserved for future use */
+ __IM uint32_t STATUS_SET; /**< Status Register */
+ uint32_t RESERVED25[1U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */
+ __IOM uint32_t WDOGLOCK_SET; /**< WDOG Configuration Lock Register */
+ uint32_t RESERVED26[2U]; /**< Reserved for future use */
+ __IOM uint32_t IF_SET; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
+ uint32_t RESERVED27[10U]; /**< Reserved for future use */
+ __IOM uint32_t CALCMD_SET; /**< Calibration Command Register */
+ __IOM uint32_t CALCTRL_SET; /**< Calibration Control Register */
+ __IM uint32_t CALCNT_SET; /**< Calibration Result Counter Register */
+ uint32_t RESERVED28[2U]; /**< Reserved for future use */
+ __IOM uint32_t CLKEN0_SET; /**< Clock Enable Register 0 */
+ __IOM uint32_t CLKEN1_SET; /**< Clock Enable Register 1 */
+ uint32_t RESERVED29[1U]; /**< Reserved for future use */
+ __IOM uint32_t SYSCLKCTRL_SET; /**< System Clock Control */
+ uint32_t RESERVED30[3U]; /**< Reserved for future use */
+ __IOM uint32_t TRACECLKCTRL_SET; /**< Debug Trace Clock Control */
+ uint32_t RESERVED31[3U]; /**< Reserved for future use */
+ __IOM uint32_t EXPORTCLKCTRL_SET; /**< Export Clock Control */
+ uint32_t RESERVED32[27U]; /**< Reserved for future use */
+ __IOM uint32_t DPLLREFCLKCTRL_SET; /**< Digital PLL Reference Clock Control */
+ uint32_t RESERVED33[7U]; /**< Reserved for future use */
+ __IOM uint32_t EM01GRPACLKCTRL_SET; /**< EM01 Peripheral Group A Clock Control */
+ uint32_t RESERVED34[1U]; /**< Reserved for future use */
+ __IOM uint32_t EM01GRPCCLKCTRL_SET; /**< EM01 Peripheral Group C Clock Control */
+ uint32_t RESERVED35[5U]; /**< Reserved for future use */
+ __IOM uint32_t EM23GRPACLKCTRL_SET; /**< EM23 Peripheral Group A Clock Control */
+ uint32_t RESERVED36[7U]; /**< Reserved for future use */
+ __IOM uint32_t EM4GRPACLKCTRL_SET; /**< EM4 Peripheral Group A Clock Control */
+ uint32_t RESERVED37[7U]; /**< Reserved for future use */
+ __IOM uint32_t IADCCLKCTRL_SET; /**< IADC Clock Control */
+ uint32_t RESERVED38[31U]; /**< Reserved for future use */
+ __IOM uint32_t WDOG0CLKCTRL_SET; /**< Watchdog0 Clock Control */
+ uint32_t RESERVED39[1U]; /**< Reserved for future use */
+ __IOM uint32_t WDOG1CLKCTRL_SET; /**< Watchdog1 Clock Control */
+ uint32_t RESERVED40[5U]; /**< Reserved for future use */
+ __IOM uint32_t EUSART0CLKCTRL_SET; /**< EUSART0 Clock Control */
+ uint32_t RESERVED41[7U]; /**< Reserved for future use */
+ __IOM uint32_t SYSRTC0CLKCTRL_SET; /**< System RTC0 Clock Control */
+ uint32_t RESERVED42[7U]; /**< Reserved for future use */
+ __IOM uint32_t VDAC0CLKCTRL_SET; /**< VDAC0 Clock Control */
+ uint32_t RESERVED43[3U]; /**< Reserved for future use */
+ __IOM uint32_t PCNT0CLKCTRL_SET; /**< Pulse counter 0 Clock Control */
+ uint32_t RESERVED44[3U]; /**< Reserved for future use */
+ __IOM uint32_t RADIOCLKCTRL_SET; /**< Radio Clock Control */
+ uint32_t RESERVED45[4U]; /**< Reserved for future use */
+ __IOM uint32_t VDAC1CLKCTRL_SET; /**< VDAC1 Clock Control */
+ uint32_t RESERVED46[1U]; /**< Reserved for future use */
+ uint32_t RESERVED47[857U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP version ID */
+ uint32_t RESERVED48[1U]; /**< Reserved for future use */
+ __IM uint32_t STATUS_CLR; /**< Status Register */
+ uint32_t RESERVED49[1U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */
+ __IOM uint32_t WDOGLOCK_CLR; /**< WDOG Configuration Lock Register */
+ uint32_t RESERVED50[2U]; /**< Reserved for future use */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
+ uint32_t RESERVED51[10U]; /**< Reserved for future use */
+ __IOM uint32_t CALCMD_CLR; /**< Calibration Command Register */
+ __IOM uint32_t CALCTRL_CLR; /**< Calibration Control Register */
+ __IM uint32_t CALCNT_CLR; /**< Calibration Result Counter Register */
+ uint32_t RESERVED52[2U]; /**< Reserved for future use */
+ __IOM uint32_t CLKEN0_CLR; /**< Clock Enable Register 0 */
+ __IOM uint32_t CLKEN1_CLR; /**< Clock Enable Register 1 */
+ uint32_t RESERVED53[1U]; /**< Reserved for future use */
+ __IOM uint32_t SYSCLKCTRL_CLR; /**< System Clock Control */
+ uint32_t RESERVED54[3U]; /**< Reserved for future use */
+ __IOM uint32_t TRACECLKCTRL_CLR; /**< Debug Trace Clock Control */
+ uint32_t RESERVED55[3U]; /**< Reserved for future use */
+ __IOM uint32_t EXPORTCLKCTRL_CLR; /**< Export Clock Control */
+ uint32_t RESERVED56[27U]; /**< Reserved for future use */
+ __IOM uint32_t DPLLREFCLKCTRL_CLR; /**< Digital PLL Reference Clock Control */
+ uint32_t RESERVED57[7U]; /**< Reserved for future use */
+ __IOM uint32_t EM01GRPACLKCTRL_CLR; /**< EM01 Peripheral Group A Clock Control */
+ uint32_t RESERVED58[1U]; /**< Reserved for future use */
+ __IOM uint32_t EM01GRPCCLKCTRL_CLR; /**< EM01 Peripheral Group C Clock Control */
+ uint32_t RESERVED59[5U]; /**< Reserved for future use */
+ __IOM uint32_t EM23GRPACLKCTRL_CLR; /**< EM23 Peripheral Group A Clock Control */
+ uint32_t RESERVED60[7U]; /**< Reserved for future use */
+ __IOM uint32_t EM4GRPACLKCTRL_CLR; /**< EM4 Peripheral Group A Clock Control */
+ uint32_t RESERVED61[7U]; /**< Reserved for future use */
+ __IOM uint32_t IADCCLKCTRL_CLR; /**< IADC Clock Control */
+ uint32_t RESERVED62[31U]; /**< Reserved for future use */
+ __IOM uint32_t WDOG0CLKCTRL_CLR; /**< Watchdog0 Clock Control */
+ uint32_t RESERVED63[1U]; /**< Reserved for future use */
+ __IOM uint32_t WDOG1CLKCTRL_CLR; /**< Watchdog1 Clock Control */
+ uint32_t RESERVED64[5U]; /**< Reserved for future use */
+ __IOM uint32_t EUSART0CLKCTRL_CLR; /**< EUSART0 Clock Control */
+ uint32_t RESERVED65[7U]; /**< Reserved for future use */
+ __IOM uint32_t SYSRTC0CLKCTRL_CLR; /**< System RTC0 Clock Control */
+ uint32_t RESERVED66[7U]; /**< Reserved for future use */
+ __IOM uint32_t VDAC0CLKCTRL_CLR; /**< VDAC0 Clock Control */
+ uint32_t RESERVED67[3U]; /**< Reserved for future use */
+ __IOM uint32_t PCNT0CLKCTRL_CLR; /**< Pulse counter 0 Clock Control */
+ uint32_t RESERVED68[3U]; /**< Reserved for future use */
+ __IOM uint32_t RADIOCLKCTRL_CLR; /**< Radio Clock Control */
+ uint32_t RESERVED69[4U]; /**< Reserved for future use */
+ __IOM uint32_t VDAC1CLKCTRL_CLR; /**< VDAC1 Clock Control */
+ uint32_t RESERVED70[1U]; /**< Reserved for future use */
+ uint32_t RESERVED71[857U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP version ID */
+ uint32_t RESERVED72[1U]; /**< Reserved for future use */
+ __IM uint32_t STATUS_TGL; /**< Status Register */
+ uint32_t RESERVED73[1U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */
+ __IOM uint32_t WDOGLOCK_TGL; /**< WDOG Configuration Lock Register */
+ uint32_t RESERVED74[2U]; /**< Reserved for future use */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
+ uint32_t RESERVED75[10U]; /**< Reserved for future use */
+ __IOM uint32_t CALCMD_TGL; /**< Calibration Command Register */
+ __IOM uint32_t CALCTRL_TGL; /**< Calibration Control Register */
+ __IM uint32_t CALCNT_TGL; /**< Calibration Result Counter Register */
+ uint32_t RESERVED76[2U]; /**< Reserved for future use */
+ __IOM uint32_t CLKEN0_TGL; /**< Clock Enable Register 0 */
+ __IOM uint32_t CLKEN1_TGL; /**< Clock Enable Register 1 */
+ uint32_t RESERVED77[1U]; /**< Reserved for future use */
+ __IOM uint32_t SYSCLKCTRL_TGL; /**< System Clock Control */
+ uint32_t RESERVED78[3U]; /**< Reserved for future use */
+ __IOM uint32_t TRACECLKCTRL_TGL; /**< Debug Trace Clock Control */
+ uint32_t RESERVED79[3U]; /**< Reserved for future use */
+ __IOM uint32_t EXPORTCLKCTRL_TGL; /**< Export Clock Control */
+ uint32_t RESERVED80[27U]; /**< Reserved for future use */
+ __IOM uint32_t DPLLREFCLKCTRL_TGL; /**< Digital PLL Reference Clock Control */
+ uint32_t RESERVED81[7U]; /**< Reserved for future use */
+ __IOM uint32_t EM01GRPACLKCTRL_TGL; /**< EM01 Peripheral Group A Clock Control */
+ uint32_t RESERVED82[1U]; /**< Reserved for future use */
+ __IOM uint32_t EM01GRPCCLKCTRL_TGL; /**< EM01 Peripheral Group C Clock Control */
+ uint32_t RESERVED83[5U]; /**< Reserved for future use */
+ __IOM uint32_t EM23GRPACLKCTRL_TGL; /**< EM23 Peripheral Group A Clock Control */
+ uint32_t RESERVED84[7U]; /**< Reserved for future use */
+ __IOM uint32_t EM4GRPACLKCTRL_TGL; /**< EM4 Peripheral Group A Clock Control */
+ uint32_t RESERVED85[7U]; /**< Reserved for future use */
+ __IOM uint32_t IADCCLKCTRL_TGL; /**< IADC Clock Control */
+ uint32_t RESERVED86[31U]; /**< Reserved for future use */
+ __IOM uint32_t WDOG0CLKCTRL_TGL; /**< Watchdog0 Clock Control */
+ uint32_t RESERVED87[1U]; /**< Reserved for future use */
+ __IOM uint32_t WDOG1CLKCTRL_TGL; /**< Watchdog1 Clock Control */
+ uint32_t RESERVED88[5U]; /**< Reserved for future use */
+ __IOM uint32_t EUSART0CLKCTRL_TGL; /**< EUSART0 Clock Control */
+ uint32_t RESERVED89[7U]; /**< Reserved for future use */
+ __IOM uint32_t SYSRTC0CLKCTRL_TGL; /**< System RTC0 Clock Control */
+ uint32_t RESERVED90[7U]; /**< Reserved for future use */
+ __IOM uint32_t VDAC0CLKCTRL_TGL; /**< VDAC0 Clock Control */
+ uint32_t RESERVED91[3U]; /**< Reserved for future use */
+ __IOM uint32_t PCNT0CLKCTRL_TGL; /**< Pulse counter 0 Clock Control */
+ uint32_t RESERVED92[3U]; /**< Reserved for future use */
+ __IOM uint32_t RADIOCLKCTRL_TGL; /**< Radio Clock Control */
+ uint32_t RESERVED93[4U]; /**< Reserved for future use */
+ __IOM uint32_t VDAC1CLKCTRL_TGL; /**< VDAC1 Clock Control */
+ uint32_t RESERVED94[1U]; /**< Reserved for future use */
+} CMU_TypeDef;
+/** @} End of group EFR32MG24_CMU */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_CMU
+ * @{
+ * @defgroup EFR32MG24_CMU_BitFields CMU Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for CMU IPVERSION */
+#define _CMU_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for CMU_IPVERSION */
+#define _CMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for CMU_IPVERSION */
+#define _CMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for CMU_IPVERSION */
+#define _CMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for CMU_IPVERSION */
+#define _CMU_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_IPVERSION */
+#define CMU_IPVERSION_IPVERSION_DEFAULT (_CMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IPVERSION */
+
+/* Bit fields for CMU STATUS */
+#define _CMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_STATUS */
+#define _CMU_STATUS_MASK 0xC0038001UL /**< Mask for CMU_STATUS */
+#define CMU_STATUS_CALRDY (0x1UL << 0) /**< Calibration Ready */
+#define _CMU_STATUS_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */
+#define _CMU_STATUS_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */
+#define _CMU_STATUS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_WDOGLOCK (0x1UL << 30) /**< Configuration Lock Status for WDOG */
+#define _CMU_STATUS_WDOGLOCK_SHIFT 30 /**< Shift value for CMU_WDOGLOCK */
+#define _CMU_STATUS_WDOGLOCK_MASK 0x40000000UL /**< Bit mask for CMU_WDOGLOCK */
+#define _CMU_STATUS_WDOGLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
+#define _CMU_STATUS_WDOGLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */
+#define _CMU_STATUS_WDOGLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */
+#define CMU_STATUS_WDOGLOCK_DEFAULT (_CMU_STATUS_WDOGLOCK_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_WDOGLOCK_UNLOCKED (_CMU_STATUS_WDOGLOCK_UNLOCKED << 30) /**< Shifted mode UNLOCKED for CMU_STATUS */
+#define CMU_STATUS_WDOGLOCK_LOCKED (_CMU_STATUS_WDOGLOCK_LOCKED << 30) /**< Shifted mode LOCKED for CMU_STATUS */
+#define CMU_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */
+#define _CMU_STATUS_LOCK_SHIFT 31 /**< Shift value for CMU_LOCK */
+#define _CMU_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for CMU_LOCK */
+#define _CMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
+#define _CMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */
+#define _CMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */
+#define CMU_STATUS_LOCK_DEFAULT (_CMU_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_STATUS */
+#define CMU_STATUS_LOCK_UNLOCKED (_CMU_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for CMU_STATUS */
+#define CMU_STATUS_LOCK_LOCKED (_CMU_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for CMU_STATUS */
+
+/* Bit fields for CMU LOCK */
+#define _CMU_LOCK_RESETVALUE 0x000093F7UL /**< Default value for CMU_LOCK */
+#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */
+#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */
+#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */
+#define _CMU_LOCK_LOCKKEY_DEFAULT 0x000093F7UL /**< Mode DEFAULT for CMU_LOCK */
+#define _CMU_LOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_LOCK */
+#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */
+#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */
+
+/* Bit fields for CMU WDOGLOCK */
+#define _CMU_WDOGLOCK_RESETVALUE 0x00005257UL /**< Default value for CMU_WDOGLOCK */
+#define _CMU_WDOGLOCK_MASK 0x0000FFFFUL /**< Mask for CMU_WDOGLOCK */
+#define _CMU_WDOGLOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */
+#define _CMU_WDOGLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */
+#define _CMU_WDOGLOCK_LOCKKEY_DEFAULT 0x00005257UL /**< Mode DEFAULT for CMU_WDOGLOCK */
+#define _CMU_WDOGLOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_WDOGLOCK */
+#define CMU_WDOGLOCK_LOCKKEY_DEFAULT (_CMU_WDOGLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOGLOCK */
+#define CMU_WDOGLOCK_LOCKKEY_UNLOCK (_CMU_WDOGLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_WDOGLOCK */
+
+/* Bit fields for CMU IF */
+#define _CMU_IF_RESETVALUE 0x00000000UL /**< Default value for CMU_IF */
+#define _CMU_IF_MASK 0x00000003UL /**< Mask for CMU_IF */
+#define CMU_IF_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Flag */
+#define _CMU_IF_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */
+#define _CMU_IF_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */
+#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */
+#define CMU_IF_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Flag */
+#define _CMU_IF_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */
+#define _CMU_IF_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */
+#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
+#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */
+
+/* Bit fields for CMU IEN */
+#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */
+#define _CMU_IEN_MASK 0x00000003UL /**< Mask for CMU_IEN */
+#define CMU_IEN_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Enable */
+#define _CMU_IEN_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */
+#define _CMU_IEN_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */
+#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */
+#define CMU_IEN_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Enable */
+#define _CMU_IEN_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */
+#define _CMU_IEN_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */
+#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
+#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */
+
+/* Bit fields for CMU CALCMD */
+#define _CMU_CALCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCMD */
+#define _CMU_CALCMD_MASK 0x00000003UL /**< Mask for CMU_CALCMD */
+#define CMU_CALCMD_CALSTART (0x1UL << 0) /**< Calibration Start */
+#define _CMU_CALCMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */
+#define _CMU_CALCMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */
+#define _CMU_CALCMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */
+#define CMU_CALCMD_CALSTART_DEFAULT (_CMU_CALCMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCMD */
+#define CMU_CALCMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */
+#define _CMU_CALCMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */
+#define _CMU_CALCMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */
+#define _CMU_CALCMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */
+#define CMU_CALCMD_CALSTOP_DEFAULT (_CMU_CALCMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CALCMD */
+
+/* Bit fields for CMU CALCTRL */
+#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */
+#define _CMU_CALCTRL_MASK 0xFF8FFFFFUL /**< Mask for CMU_CALCTRL */
+#define _CMU_CALCTRL_CALTOP_SHIFT 0 /**< Shift value for CMU_CALTOP */
+#define _CMU_CALCTRL_CALTOP_MASK 0xFFFFFUL /**< Bit mask for CMU_CALTOP */
+#define _CMU_CALCTRL_CALTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
+#define CMU_CALCTRL_CALTOP_DEFAULT (_CMU_CALCTRL_CALTOP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */
+#define CMU_CALCTRL_CONT (0x1UL << 23) /**< Continuous Calibration */
+#define _CMU_CALCTRL_CONT_SHIFT 23 /**< Shift value for CMU_CONT */
+#define _CMU_CALCTRL_CONT_MASK 0x800000UL /**< Bit mask for CMU_CONT */
+#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
+#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CALCTRL */
+#define _CMU_CALCTRL_UPSEL_SHIFT 24 /**< Shift value for CMU_UPSEL */
+#define _CMU_CALCTRL_UPSEL_MASK 0xF000000UL /**< Bit mask for CMU_UPSEL */
+#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
+#define _CMU_CALCTRL_UPSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */
+#define _CMU_CALCTRL_UPSEL_PRS 0x00000001UL /**< Mode PRS for CMU_CALCTRL */
+#define _CMU_CALCTRL_UPSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CALCTRL */
+#define _CMU_CALCTRL_UPSEL_LFXO 0x00000003UL /**< Mode LFXO for CMU_CALCTRL */
+#define _CMU_CALCTRL_UPSEL_HFRCODPLL 0x00000004UL /**< Mode HFRCODPLL for CMU_CALCTRL */
+#define _CMU_CALCTRL_UPSEL_HFRCOEM23 0x00000005UL /**< Mode HFRCOEM23 for CMU_CALCTRL */
+#define _CMU_CALCTRL_UPSEL_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_CALCTRL */
+#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000009UL /**< Mode LFRCO for CMU_CALCTRL */
+#define _CMU_CALCTRL_UPSEL_ULFRCO 0x0000000AUL /**< Mode ULFRCO for CMU_CALCTRL */
+#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */
+#define CMU_CALCTRL_UPSEL_DISABLED (_CMU_CALCTRL_UPSEL_DISABLED << 24) /**< Shifted mode DISABLED for CMU_CALCTRL */
+#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 24) /**< Shifted mode PRS for CMU_CALCTRL */
+#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 24) /**< Shifted mode HFXO for CMU_CALCTRL */
+#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 24) /**< Shifted mode LFXO for CMU_CALCTRL */
+#define CMU_CALCTRL_UPSEL_HFRCODPLL (_CMU_CALCTRL_UPSEL_HFRCODPLL << 24) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */
+#define CMU_CALCTRL_UPSEL_HFRCOEM23 (_CMU_CALCTRL_UPSEL_HFRCOEM23 << 24) /**< Shifted mode HFRCOEM23 for CMU_CALCTRL */
+#define CMU_CALCTRL_UPSEL_FSRCO (_CMU_CALCTRL_UPSEL_FSRCO << 24) /**< Shifted mode FSRCO for CMU_CALCTRL */
+#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 24) /**< Shifted mode LFRCO for CMU_CALCTRL */
+#define CMU_CALCTRL_UPSEL_ULFRCO (_CMU_CALCTRL_UPSEL_ULFRCO << 24) /**< Shifted mode ULFRCO for CMU_CALCTRL */
+#define _CMU_CALCTRL_DOWNSEL_SHIFT 28 /**< Shift value for CMU_DOWNSEL */
+#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0000000UL /**< Bit mask for CMU_DOWNSEL */
+#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
+#define _CMU_CALCTRL_DOWNSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */
+#define _CMU_CALCTRL_DOWNSEL_HCLK 0x00000001UL /**< Mode HCLK for CMU_CALCTRL */
+#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000002UL /**< Mode PRS for CMU_CALCTRL */
+#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_CALCTRL */
+#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CALCTRL */
+#define _CMU_CALCTRL_DOWNSEL_HFRCODPLL 0x00000005UL /**< Mode HFRCODPLL for CMU_CALCTRL */
+#define _CMU_CALCTRL_DOWNSEL_HFRCOEM23 0x00000006UL /**< Mode HFRCOEM23 for CMU_CALCTRL */
+#define _CMU_CALCTRL_DOWNSEL_FSRCO 0x00000009UL /**< Mode FSRCO for CMU_CALCTRL */
+#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x0000000AUL /**< Mode LFRCO for CMU_CALCTRL */
+#define _CMU_CALCTRL_DOWNSEL_ULFRCO 0x0000000BUL /**< Mode ULFRCO for CMU_CALCTRL */
+#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CALCTRL */
+#define CMU_CALCTRL_DOWNSEL_DISABLED (_CMU_CALCTRL_DOWNSEL_DISABLED << 28) /**< Shifted mode DISABLED for CMU_CALCTRL */
+#define CMU_CALCTRL_DOWNSEL_HCLK (_CMU_CALCTRL_DOWNSEL_HCLK << 28) /**< Shifted mode HCLK for CMU_CALCTRL */
+#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 28) /**< Shifted mode PRS for CMU_CALCTRL */
+#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 28) /**< Shifted mode HFXO for CMU_CALCTRL */
+#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 28) /**< Shifted mode LFXO for CMU_CALCTRL */
+#define CMU_CALCTRL_DOWNSEL_HFRCODPLL (_CMU_CALCTRL_DOWNSEL_HFRCODPLL << 28) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */
+#define CMU_CALCTRL_DOWNSEL_HFRCOEM23 (_CMU_CALCTRL_DOWNSEL_HFRCOEM23 << 28) /**< Shifted mode HFRCOEM23 for CMU_CALCTRL */
+#define CMU_CALCTRL_DOWNSEL_FSRCO (_CMU_CALCTRL_DOWNSEL_FSRCO << 28) /**< Shifted mode FSRCO for CMU_CALCTRL */
+#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 28) /**< Shifted mode LFRCO for CMU_CALCTRL */
+#define CMU_CALCTRL_DOWNSEL_ULFRCO (_CMU_CALCTRL_DOWNSEL_ULFRCO << 28) /**< Shifted mode ULFRCO for CMU_CALCTRL */
+
+/* Bit fields for CMU CALCNT */
+#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */
+#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */
+#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */
+#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */
+#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */
+#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */
+
+/* Bit fields for CMU CLKEN0 */
+#define _CMU_CLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_CLKEN0 */
+#define _CMU_CLKEN0_MASK 0xFDFFFFFFUL /**< Mask for CMU_CLKEN0 */
+#define CMU_CLKEN0_LDMA (0x1UL << 0) /**< Enable Bus Clock */
+#define _CMU_CLKEN0_LDMA_SHIFT 0 /**< Shift value for CMU_LDMA */
+#define _CMU_CLKEN0_LDMA_MASK 0x1UL /**< Bit mask for CMU_LDMA */
+#define _CMU_CLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_LDMA_DEFAULT (_CMU_CLKEN0_LDMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_LDMAXBAR (0x1UL << 1) /**< Enable Bus Clock */
+#define _CMU_CLKEN0_LDMAXBAR_SHIFT 1 /**< Shift value for CMU_LDMAXBAR */
+#define _CMU_CLKEN0_LDMAXBAR_MASK 0x2UL /**< Bit mask for CMU_LDMAXBAR */
+#define _CMU_CLKEN0_LDMAXBAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_LDMAXBAR_DEFAULT (_CMU_CLKEN0_LDMAXBAR_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_RADIOAES (0x1UL << 2) /**< Enable Bus Clock */
+#define _CMU_CLKEN0_RADIOAES_SHIFT 2 /**< Shift value for CMU_RADIOAES */
+#define _CMU_CLKEN0_RADIOAES_MASK 0x4UL /**< Bit mask for CMU_RADIOAES */
+#define _CMU_CLKEN0_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_RADIOAES_DEFAULT (_CMU_CLKEN0_RADIOAES_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_GPCRC (0x1UL << 3) /**< Enable Bus Clock */
+#define _CMU_CLKEN0_GPCRC_SHIFT 3 /**< Shift value for CMU_GPCRC */
+#define _CMU_CLKEN0_GPCRC_MASK 0x8UL /**< Bit mask for CMU_GPCRC */
+#define _CMU_CLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_GPCRC_DEFAULT (_CMU_CLKEN0_GPCRC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_TIMER0 (0x1UL << 4) /**< Enable Bus Clock */
+#define _CMU_CLKEN0_TIMER0_SHIFT 4 /**< Shift value for CMU_TIMER0 */
+#define _CMU_CLKEN0_TIMER0_MASK 0x10UL /**< Bit mask for CMU_TIMER0 */
+#define _CMU_CLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_TIMER0_DEFAULT (_CMU_CLKEN0_TIMER0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_TIMER1 (0x1UL << 5) /**< Enable Bus Clock */
+#define _CMU_CLKEN0_TIMER1_SHIFT 5 /**< Shift value for CMU_TIMER1 */
+#define _CMU_CLKEN0_TIMER1_MASK 0x20UL /**< Bit mask for CMU_TIMER1 */
+#define _CMU_CLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_TIMER1_DEFAULT (_CMU_CLKEN0_TIMER1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_TIMER2 (0x1UL << 6) /**< Enable Bus Clock */
+#define _CMU_CLKEN0_TIMER2_SHIFT 6 /**< Shift value for CMU_TIMER2 */
+#define _CMU_CLKEN0_TIMER2_MASK 0x40UL /**< Bit mask for CMU_TIMER2 */
+#define _CMU_CLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_TIMER2_DEFAULT (_CMU_CLKEN0_TIMER2_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_TIMER3 (0x1UL << 7) /**< Enable Bus Clock */
+#define _CMU_CLKEN0_TIMER3_SHIFT 7 /**< Shift value for CMU_TIMER3 */
+#define _CMU_CLKEN0_TIMER3_MASK 0x80UL /**< Bit mask for CMU_TIMER3 */
+#define _CMU_CLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_TIMER3_DEFAULT (_CMU_CLKEN0_TIMER3_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_TIMER4 (0x1UL << 8) /**< Enable Bus Clock */
+#define _CMU_CLKEN0_TIMER4_SHIFT 8 /**< Shift value for CMU_TIMER4 */
+#define _CMU_CLKEN0_TIMER4_MASK 0x100UL /**< Bit mask for CMU_TIMER4 */
+#define _CMU_CLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_TIMER4_DEFAULT (_CMU_CLKEN0_TIMER4_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_USART0 (0x1UL << 9) /**< Enable Bus Clock */
+#define _CMU_CLKEN0_USART0_SHIFT 9 /**< Shift value for CMU_USART0 */
+#define _CMU_CLKEN0_USART0_MASK 0x200UL /**< Bit mask for CMU_USART0 */
+#define _CMU_CLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_USART0_DEFAULT (_CMU_CLKEN0_USART0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_IADC0 (0x1UL << 10) /**< Enable Bus Clock */
+#define _CMU_CLKEN0_IADC0_SHIFT 10 /**< Shift value for CMU_IADC0 */
+#define _CMU_CLKEN0_IADC0_MASK 0x400UL /**< Bit mask for CMU_IADC0 */
+#define _CMU_CLKEN0_IADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_IADC0_DEFAULT (_CMU_CLKEN0_IADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_AMUXCP0 (0x1UL << 11) /**< Enable Bus Clock */
+#define _CMU_CLKEN0_AMUXCP0_SHIFT 11 /**< Shift value for CMU_AMUXCP0 */
+#define _CMU_CLKEN0_AMUXCP0_MASK 0x800UL /**< Bit mask for CMU_AMUXCP0 */
+#define _CMU_CLKEN0_AMUXCP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_AMUXCP0_DEFAULT (_CMU_CLKEN0_AMUXCP0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_LETIMER0 (0x1UL << 12) /**< Enable Bus Clock */
+#define _CMU_CLKEN0_LETIMER0_SHIFT 12 /**< Shift value for CMU_LETIMER0 */
+#define _CMU_CLKEN0_LETIMER0_MASK 0x1000UL /**< Bit mask for CMU_LETIMER0 */
+#define _CMU_CLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_LETIMER0_DEFAULT (_CMU_CLKEN0_LETIMER0_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_WDOG0 (0x1UL << 13) /**< Enable Bus Clock */
+#define _CMU_CLKEN0_WDOG0_SHIFT 13 /**< Shift value for CMU_WDOG0 */
+#define _CMU_CLKEN0_WDOG0_MASK 0x2000UL /**< Bit mask for CMU_WDOG0 */
+#define _CMU_CLKEN0_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_WDOG0_DEFAULT (_CMU_CLKEN0_WDOG0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_I2C0 (0x1UL << 14) /**< Enable Bus Clock */
+#define _CMU_CLKEN0_I2C0_SHIFT 14 /**< Shift value for CMU_I2C0 */
+#define _CMU_CLKEN0_I2C0_MASK 0x4000UL /**< Bit mask for CMU_I2C0 */
+#define _CMU_CLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_I2C0_DEFAULT (_CMU_CLKEN0_I2C0_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_I2C1 (0x1UL << 15) /**< Enable Bus Clock */
+#define _CMU_CLKEN0_I2C1_SHIFT 15 /**< Shift value for CMU_I2C1 */
+#define _CMU_CLKEN0_I2C1_MASK 0x8000UL /**< Bit mask for CMU_I2C1 */
+#define _CMU_CLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_I2C1_DEFAULT (_CMU_CLKEN0_I2C1_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_SYSCFG (0x1UL << 16) /**< Enable Bus Clock */
+#define _CMU_CLKEN0_SYSCFG_SHIFT 16 /**< Shift value for CMU_SYSCFG */
+#define _CMU_CLKEN0_SYSCFG_MASK 0x10000UL /**< Bit mask for CMU_SYSCFG */
+#define _CMU_CLKEN0_SYSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_SYSCFG_DEFAULT (_CMU_CLKEN0_SYSCFG_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_DPLL0 (0x1UL << 17) /**< Enable Bus Clock */
+#define _CMU_CLKEN0_DPLL0_SHIFT 17 /**< Shift value for CMU_DPLL0 */
+#define _CMU_CLKEN0_DPLL0_MASK 0x20000UL /**< Bit mask for CMU_DPLL0 */
+#define _CMU_CLKEN0_DPLL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_DPLL0_DEFAULT (_CMU_CLKEN0_DPLL0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_HFRCO0 (0x1UL << 18) /**< Enable Bus Clock */
+#define _CMU_CLKEN0_HFRCO0_SHIFT 18 /**< Shift value for CMU_HFRCO0 */
+#define _CMU_CLKEN0_HFRCO0_MASK 0x40000UL /**< Bit mask for CMU_HFRCO0 */
+#define _CMU_CLKEN0_HFRCO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_HFRCO0_DEFAULT (_CMU_CLKEN0_HFRCO0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_HFRCOEM23 (0x1UL << 19) /**< Enable Bus Clock */
+#define _CMU_CLKEN0_HFRCOEM23_SHIFT 19 /**< Shift value for CMU_HFRCOEM23 */
+#define _CMU_CLKEN0_HFRCOEM23_MASK 0x80000UL /**< Bit mask for CMU_HFRCOEM23 */
+#define _CMU_CLKEN0_HFRCOEM23_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_HFRCOEM23_DEFAULT (_CMU_CLKEN0_HFRCOEM23_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_HFXO0 (0x1UL << 20) /**< Enable Bus Clock */
+#define _CMU_CLKEN0_HFXO0_SHIFT 20 /**< Shift value for CMU_HFXO0 */
+#define _CMU_CLKEN0_HFXO0_MASK 0x100000UL /**< Bit mask for CMU_HFXO0 */
+#define _CMU_CLKEN0_HFXO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_HFXO0_DEFAULT (_CMU_CLKEN0_HFXO0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_FSRCO (0x1UL << 21) /**< Enable Bus Clock */
+#define _CMU_CLKEN0_FSRCO_SHIFT 21 /**< Shift value for CMU_FSRCO */
+#define _CMU_CLKEN0_FSRCO_MASK 0x200000UL /**< Bit mask for CMU_FSRCO */
+#define _CMU_CLKEN0_FSRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_FSRCO_DEFAULT (_CMU_CLKEN0_FSRCO_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_LFRCO (0x1UL << 22) /**< Enable Bus Clock */
+#define _CMU_CLKEN0_LFRCO_SHIFT 22 /**< Shift value for CMU_LFRCO */
+#define _CMU_CLKEN0_LFRCO_MASK 0x400000UL /**< Bit mask for CMU_LFRCO */
+#define _CMU_CLKEN0_LFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_LFRCO_DEFAULT (_CMU_CLKEN0_LFRCO_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_LFXO (0x1UL << 23) /**< Enable Bus Clock */
+#define _CMU_CLKEN0_LFXO_SHIFT 23 /**< Shift value for CMU_LFXO */
+#define _CMU_CLKEN0_LFXO_MASK 0x800000UL /**< Bit mask for CMU_LFXO */
+#define _CMU_CLKEN0_LFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_LFXO_DEFAULT (_CMU_CLKEN0_LFXO_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_ULFRCO (0x1UL << 24) /**< Enable Bus Clock */
+#define _CMU_CLKEN0_ULFRCO_SHIFT 24 /**< Shift value for CMU_ULFRCO */
+#define _CMU_CLKEN0_ULFRCO_MASK 0x1000000UL /**< Bit mask for CMU_ULFRCO */
+#define _CMU_CLKEN0_ULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_ULFRCO_DEFAULT (_CMU_CLKEN0_ULFRCO_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_GPIO (0x1UL << 26) /**< Enable Bus Clock */
+#define _CMU_CLKEN0_GPIO_SHIFT 26 /**< Shift value for CMU_GPIO */
+#define _CMU_CLKEN0_GPIO_MASK 0x4000000UL /**< Bit mask for CMU_GPIO */
+#define _CMU_CLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_GPIO_DEFAULT (_CMU_CLKEN0_GPIO_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_PRS (0x1UL << 27) /**< Enable Bus Clock */
+#define _CMU_CLKEN0_PRS_SHIFT 27 /**< Shift value for CMU_PRS */
+#define _CMU_CLKEN0_PRS_MASK 0x8000000UL /**< Bit mask for CMU_PRS */
+#define _CMU_CLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_PRS_DEFAULT (_CMU_CLKEN0_PRS_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_BURAM (0x1UL << 28) /**< Enable Bus Clock */
+#define _CMU_CLKEN0_BURAM_SHIFT 28 /**< Shift value for CMU_BURAM */
+#define _CMU_CLKEN0_BURAM_MASK 0x10000000UL /**< Bit mask for CMU_BURAM */
+#define _CMU_CLKEN0_BURAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_BURAM_DEFAULT (_CMU_CLKEN0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_BURTC (0x1UL << 29) /**< Enable Bus Clock */
+#define _CMU_CLKEN0_BURTC_SHIFT 29 /**< Shift value for CMU_BURTC */
+#define _CMU_CLKEN0_BURTC_MASK 0x20000000UL /**< Bit mask for CMU_BURTC */
+#define _CMU_CLKEN0_BURTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_BURTC_DEFAULT (_CMU_CLKEN0_BURTC_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_SYSRTC0 (0x1UL << 30) /**< Enable Bus Clock */
+#define _CMU_CLKEN0_SYSRTC0_SHIFT 30 /**< Shift value for CMU_SYSRTC0 */
+#define _CMU_CLKEN0_SYSRTC0_MASK 0x40000000UL /**< Bit mask for CMU_SYSRTC0 */
+#define _CMU_CLKEN0_SYSRTC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_SYSRTC0_DEFAULT (_CMU_CLKEN0_SYSRTC0_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_DCDC (0x1UL << 31) /**< Enable Bus Clock */
+#define _CMU_CLKEN0_DCDC_SHIFT 31 /**< Shift value for CMU_DCDC */
+#define _CMU_CLKEN0_DCDC_MASK 0x80000000UL /**< Bit mask for CMU_DCDC */
+#define _CMU_CLKEN0_DCDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */
+#define CMU_CLKEN0_DCDC_DEFAULT (_CMU_CLKEN0_DCDC_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_CLKEN0 */
+
+/* Bit fields for CMU CLKEN1 */
+#define _CMU_CLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_CLKEN1 */
+#define _CMU_CLKEN1_MASK 0x7EFFEFFFUL /**< Mask for CMU_CLKEN1 */
+#define CMU_CLKEN1_AGC (0x1UL << 0) /**< Enable Bus Clock */
+#define _CMU_CLKEN1_AGC_SHIFT 0 /**< Shift value for CMU_AGC */
+#define _CMU_CLKEN1_AGC_MASK 0x1UL /**< Bit mask for CMU_AGC */
+#define _CMU_CLKEN1_AGC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_AGC_DEFAULT (_CMU_CLKEN1_AGC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_MODEM (0x1UL << 1) /**< Enable Bus Clock */
+#define _CMU_CLKEN1_MODEM_SHIFT 1 /**< Shift value for CMU_MODEM */
+#define _CMU_CLKEN1_MODEM_MASK 0x2UL /**< Bit mask for CMU_MODEM */
+#define _CMU_CLKEN1_MODEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_MODEM_DEFAULT (_CMU_CLKEN1_MODEM_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_RFCRC (0x1UL << 2) /**< Enable Bus Clock */
+#define _CMU_CLKEN1_RFCRC_SHIFT 2 /**< Shift value for CMU_RFCRC */
+#define _CMU_CLKEN1_RFCRC_MASK 0x4UL /**< Bit mask for CMU_RFCRC */
+#define _CMU_CLKEN1_RFCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_RFCRC_DEFAULT (_CMU_CLKEN1_RFCRC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_FRC (0x1UL << 3) /**< Enable Bus Clock */
+#define _CMU_CLKEN1_FRC_SHIFT 3 /**< Shift value for CMU_FRC */
+#define _CMU_CLKEN1_FRC_MASK 0x8UL /**< Bit mask for CMU_FRC */
+#define _CMU_CLKEN1_FRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_FRC_DEFAULT (_CMU_CLKEN1_FRC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_PROTIMER (0x1UL << 4) /**< Enable Bus Clock */
+#define _CMU_CLKEN1_PROTIMER_SHIFT 4 /**< Shift value for CMU_PROTIMER */
+#define _CMU_CLKEN1_PROTIMER_MASK 0x10UL /**< Bit mask for CMU_PROTIMER */
+#define _CMU_CLKEN1_PROTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_PROTIMER_DEFAULT (_CMU_CLKEN1_PROTIMER_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_RAC (0x1UL << 5) /**< Enable Bus Clock */
+#define _CMU_CLKEN1_RAC_SHIFT 5 /**< Shift value for CMU_RAC */
+#define _CMU_CLKEN1_RAC_MASK 0x20UL /**< Bit mask for CMU_RAC */
+#define _CMU_CLKEN1_RAC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_RAC_DEFAULT (_CMU_CLKEN1_RAC_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_SYNTH (0x1UL << 6) /**< Enable Bus Clock */
+#define _CMU_CLKEN1_SYNTH_SHIFT 6 /**< Shift value for CMU_SYNTH */
+#define _CMU_CLKEN1_SYNTH_MASK 0x40UL /**< Bit mask for CMU_SYNTH */
+#define _CMU_CLKEN1_SYNTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_SYNTH_DEFAULT (_CMU_CLKEN1_SYNTH_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_RFSCRATCHPAD (0x1UL << 7) /**< Enable Bus Clock */
+#define _CMU_CLKEN1_RFSCRATCHPAD_SHIFT 7 /**< Shift value for CMU_RFSCRATCHPAD */
+#define _CMU_CLKEN1_RFSCRATCHPAD_MASK 0x80UL /**< Bit mask for CMU_RFSCRATCHPAD */
+#define _CMU_CLKEN1_RFSCRATCHPAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_RFSCRATCHPAD_DEFAULT (_CMU_CLKEN1_RFSCRATCHPAD_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_HOSTMAILBOX (0x1UL << 8) /**< Enable Bus Clock */
+#define _CMU_CLKEN1_HOSTMAILBOX_SHIFT 8 /**< Shift value for CMU_HOSTMAILBOX */
+#define _CMU_CLKEN1_HOSTMAILBOX_MASK 0x100UL /**< Bit mask for CMU_HOSTMAILBOX */
+#define _CMU_CLKEN1_HOSTMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_HOSTMAILBOX_DEFAULT (_CMU_CLKEN1_HOSTMAILBOX_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_RFMAILBOX (0x1UL << 9) /**< Enable Bus Clock */
+#define _CMU_CLKEN1_RFMAILBOX_SHIFT 9 /**< Shift value for CMU_RFMAILBOX */
+#define _CMU_CLKEN1_RFMAILBOX_MASK 0x200UL /**< Bit mask for CMU_RFMAILBOX */
+#define _CMU_CLKEN1_RFMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_RFMAILBOX_DEFAULT (_CMU_CLKEN1_RFMAILBOX_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_SEMAILBOXHOST (0x1UL << 10) /**< Enable Bus Clock */
+#define _CMU_CLKEN1_SEMAILBOXHOST_SHIFT 10 /**< Shift value for CMU_SEMAILBOXHOST */
+#define _CMU_CLKEN1_SEMAILBOXHOST_MASK 0x400UL /**< Bit mask for CMU_SEMAILBOXHOST */
+#define _CMU_CLKEN1_SEMAILBOXHOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_SEMAILBOXHOST_DEFAULT (_CMU_CLKEN1_SEMAILBOXHOST_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_BUFC (0x1UL << 11) /**< Enable Bus Clock */
+#define _CMU_CLKEN1_BUFC_SHIFT 11 /**< Shift value for CMU_BUFC */
+#define _CMU_CLKEN1_BUFC_MASK 0x800UL /**< Bit mask for CMU_BUFC */
+#define _CMU_CLKEN1_BUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_BUFC_DEFAULT (_CMU_CLKEN1_BUFC_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_KEYSCAN (0x1UL << 13) /**< Enable Bus Clock */
+#define _CMU_CLKEN1_KEYSCAN_SHIFT 13 /**< Shift value for CMU_KEYSCAN */
+#define _CMU_CLKEN1_KEYSCAN_MASK 0x2000UL /**< Bit mask for CMU_KEYSCAN */
+#define _CMU_CLKEN1_KEYSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_KEYSCAN_DEFAULT (_CMU_CLKEN1_KEYSCAN_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_SMU (0x1UL << 14) /**< Enable Bus Clock */
+#define _CMU_CLKEN1_SMU_SHIFT 14 /**< Shift value for CMU_SMU */
+#define _CMU_CLKEN1_SMU_MASK 0x4000UL /**< Bit mask for CMU_SMU */
+#define _CMU_CLKEN1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_SMU_DEFAULT (_CMU_CLKEN1_SMU_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_ICACHE0 (0x1UL << 15) /**< Enable Bus Clock */
+#define _CMU_CLKEN1_ICACHE0_SHIFT 15 /**< Shift value for CMU_ICACHE0 */
+#define _CMU_CLKEN1_ICACHE0_MASK 0x8000UL /**< Bit mask for CMU_ICACHE0 */
+#define _CMU_CLKEN1_ICACHE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_ICACHE0_DEFAULT (_CMU_CLKEN1_ICACHE0_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_MSC (0x1UL << 16) /**< Enable Bus Clock */
+#define _CMU_CLKEN1_MSC_SHIFT 16 /**< Shift value for CMU_MSC */
+#define _CMU_CLKEN1_MSC_MASK 0x10000UL /**< Bit mask for CMU_MSC */
+#define _CMU_CLKEN1_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_MSC_DEFAULT (_CMU_CLKEN1_MSC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_WDOG1 (0x1UL << 17) /**< Enable Bus Clock */
+#define _CMU_CLKEN1_WDOG1_SHIFT 17 /**< Shift value for CMU_WDOG1 */
+#define _CMU_CLKEN1_WDOG1_MASK 0x20000UL /**< Bit mask for CMU_WDOG1 */
+#define _CMU_CLKEN1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_WDOG1_DEFAULT (_CMU_CLKEN1_WDOG1_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_ACMP0 (0x1UL << 18) /**< Enable Bus Clock */
+#define _CMU_CLKEN1_ACMP0_SHIFT 18 /**< Shift value for CMU_ACMP0 */
+#define _CMU_CLKEN1_ACMP0_MASK 0x40000UL /**< Bit mask for CMU_ACMP0 */
+#define _CMU_CLKEN1_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_ACMP0_DEFAULT (_CMU_CLKEN1_ACMP0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_ACMP1 (0x1UL << 19) /**< Enable Bus Clock */
+#define _CMU_CLKEN1_ACMP1_SHIFT 19 /**< Shift value for CMU_ACMP1 */
+#define _CMU_CLKEN1_ACMP1_MASK 0x80000UL /**< Bit mask for CMU_ACMP1 */
+#define _CMU_CLKEN1_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_ACMP1_DEFAULT (_CMU_CLKEN1_ACMP1_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_VDAC0 (0x1UL << 20) /**< Enable Bus Clock */
+#define _CMU_CLKEN1_VDAC0_SHIFT 20 /**< Shift value for CMU_VDAC0 */
+#define _CMU_CLKEN1_VDAC0_MASK 0x100000UL /**< Bit mask for CMU_VDAC0 */
+#define _CMU_CLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_VDAC0_DEFAULT (_CMU_CLKEN1_VDAC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_PCNT0 (0x1UL << 21) /**< Enable Bus Clock */
+#define _CMU_CLKEN1_PCNT0_SHIFT 21 /**< Shift value for CMU_PCNT0 */
+#define _CMU_CLKEN1_PCNT0_MASK 0x200000UL /**< Bit mask for CMU_PCNT0 */
+#define _CMU_CLKEN1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_PCNT0_DEFAULT (_CMU_CLKEN1_PCNT0_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_EUSART0 (0x1UL << 22) /**< Enable Bus Clock */
+#define _CMU_CLKEN1_EUSART0_SHIFT 22 /**< Shift value for CMU_EUSART0 */
+#define _CMU_CLKEN1_EUSART0_MASK 0x400000UL /**< Bit mask for CMU_EUSART0 */
+#define _CMU_CLKEN1_EUSART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_EUSART0_DEFAULT (_CMU_CLKEN1_EUSART0_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_EUSART1 (0x1UL << 23) /**< Enable Bus Clock */
+#define _CMU_CLKEN1_EUSART1_SHIFT 23 /**< Shift value for CMU_EUSART1 */
+#define _CMU_CLKEN1_EUSART1_MASK 0x800000UL /**< Bit mask for CMU_EUSART1 */
+#define _CMU_CLKEN1_EUSART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_EUSART1_DEFAULT (_CMU_CLKEN1_EUSART1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_RFECA0 (0x1UL << 25) /**< Enable Bus Clock */
+#define _CMU_CLKEN1_RFECA0_SHIFT 25 /**< Shift value for CMU_RFECA0 */
+#define _CMU_CLKEN1_RFECA0_MASK 0x2000000UL /**< Bit mask for CMU_RFECA0 */
+#define _CMU_CLKEN1_RFECA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_RFECA0_DEFAULT (_CMU_CLKEN1_RFECA0_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_RFECA1 (0x1UL << 26) /**< Enable Bus Clock */
+#define _CMU_CLKEN1_RFECA1_SHIFT 26 /**< Shift value for CMU_RFECA1 */
+#define _CMU_CLKEN1_RFECA1_MASK 0x4000000UL /**< Bit mask for CMU_RFECA1 */
+#define _CMU_CLKEN1_RFECA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_RFECA1_DEFAULT (_CMU_CLKEN1_RFECA1_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_DMEM (0x1UL << 27) /**< Enable Bus Clock */
+#define _CMU_CLKEN1_DMEM_SHIFT 27 /**< Shift value for CMU_DMEM */
+#define _CMU_CLKEN1_DMEM_MASK 0x8000000UL /**< Bit mask for CMU_DMEM */
+#define _CMU_CLKEN1_DMEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_DMEM_DEFAULT (_CMU_CLKEN1_DMEM_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_ECAIFADC (0x1UL << 28) /**< Enable Bus Clock */
+#define _CMU_CLKEN1_ECAIFADC_SHIFT 28 /**< Shift value for CMU_ECAIFADC */
+#define _CMU_CLKEN1_ECAIFADC_MASK 0x10000000UL /**< Bit mask for CMU_ECAIFADC */
+#define _CMU_CLKEN1_ECAIFADC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_ECAIFADC_DEFAULT (_CMU_CLKEN1_ECAIFADC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_VDAC1 (0x1UL << 29) /**< Enable Bus Clock */
+#define _CMU_CLKEN1_VDAC1_SHIFT 29 /**< Shift value for CMU_VDAC1 */
+#define _CMU_CLKEN1_VDAC1_MASK 0x20000000UL /**< Bit mask for CMU_VDAC1 */
+#define _CMU_CLKEN1_VDAC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_VDAC1_DEFAULT (_CMU_CLKEN1_VDAC1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_MVP (0x1UL << 30) /**< Enable Bus Clock */
+#define _CMU_CLKEN1_MVP_SHIFT 30 /**< Shift value for CMU_MVP */
+#define _CMU_CLKEN1_MVP_MASK 0x40000000UL /**< Bit mask for CMU_MVP */
+#define _CMU_CLKEN1_MVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */
+#define CMU_CLKEN1_MVP_DEFAULT (_CMU_CLKEN1_MVP_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CLKEN1 */
+
+/* Bit fields for CMU SYSCLKCTRL */
+#define _CMU_SYSCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_SYSCLKCTRL */
+#define _CMU_SYSCLKCTRL_MASK 0x0001F507UL /**< Mask for CMU_SYSCLKCTRL */
+#define _CMU_SYSCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */
+#define _CMU_SYSCLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */
+#define _CMU_SYSCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */
+#define _CMU_SYSCLKCTRL_CLKSEL_FSRCO 0x00000001UL /**< Mode FSRCO for CMU_SYSCLKCTRL */
+#define _CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL 0x00000002UL /**< Mode HFRCODPLL for CMU_SYSCLKCTRL */
+#define _CMU_SYSCLKCTRL_CLKSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_SYSCLKCTRL */
+#define _CMU_SYSCLKCTRL_CLKSEL_CLKIN0 0x00000004UL /**< Mode CLKIN0 for CMU_SYSCLKCTRL */
+#define CMU_SYSCLKCTRL_CLKSEL_DEFAULT (_CMU_SYSCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */
+#define CMU_SYSCLKCTRL_CLKSEL_FSRCO (_CMU_SYSCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_SYSCLKCTRL */
+#define CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL (_CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_SYSCLKCTRL */
+#define CMU_SYSCLKCTRL_CLKSEL_HFXO (_CMU_SYSCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_SYSCLKCTRL */
+#define CMU_SYSCLKCTRL_CLKSEL_CLKIN0 (_CMU_SYSCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_SYSCLKCTRL */
+#define CMU_SYSCLKCTRL_PCLKPRESC (0x1UL << 10) /**< PCLK Prescaler */
+#define _CMU_SYSCLKCTRL_PCLKPRESC_SHIFT 10 /**< Shift value for CMU_PCLKPRESC */
+#define _CMU_SYSCLKCTRL_PCLKPRESC_MASK 0x400UL /**< Bit mask for CMU_PCLKPRESC */
+#define _CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */
+#define _CMU_SYSCLKCTRL_PCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */
+#define _CMU_SYSCLKCTRL_PCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */
+#define CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */
+#define CMU_SYSCLKCTRL_PCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV1 << 10) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */
+#define CMU_SYSCLKCTRL_PCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV2 << 10) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */
+#define _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT 12 /**< Shift value for CMU_HCLKPRESC */
+#define _CMU_SYSCLKCTRL_HCLKPRESC_MASK 0xF000UL /**< Bit mask for CMU_HCLKPRESC */
+#define _CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */
+#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */
+#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */
+#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV4 0x00000003UL /**< Mode DIV4 for CMU_SYSCLKCTRL */
+#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV8 0x00000007UL /**< Mode DIV8 for CMU_SYSCLKCTRL */
+#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV16 0x0000000FUL /**< Mode DIV16 for CMU_SYSCLKCTRL */
+#define CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */
+#define CMU_SYSCLKCTRL_HCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV1 << 12) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */
+#define CMU_SYSCLKCTRL_HCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV2 << 12) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */
+#define CMU_SYSCLKCTRL_HCLKPRESC_DIV4 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV4 << 12) /**< Shifted mode DIV4 for CMU_SYSCLKCTRL */
+#define CMU_SYSCLKCTRL_HCLKPRESC_DIV8 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV8 << 12) /**< Shifted mode DIV8 for CMU_SYSCLKCTRL */
+#define CMU_SYSCLKCTRL_HCLKPRESC_DIV16 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV16 << 12) /**< Shifted mode DIV16 for CMU_SYSCLKCTRL */
+#define CMU_SYSCLKCTRL_RHCLKPRESC (0x1UL << 16) /**< Radio HCLK Prescaler */
+#define _CMU_SYSCLKCTRL_RHCLKPRESC_SHIFT 16 /**< Shift value for CMU_RHCLKPRESC */
+#define _CMU_SYSCLKCTRL_RHCLKPRESC_MASK 0x10000UL /**< Bit mask for CMU_RHCLKPRESC */
+#define _CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */
+#define _CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */
+#define _CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */
+#define CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */
+#define CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */
+#define CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */
+
+/* Bit fields for CMU TRACECLKCTRL */
+#define _CMU_TRACECLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_TRACECLKCTRL */
+#define _CMU_TRACECLKCTRL_MASK 0x00000033UL /**< Mask for CMU_TRACECLKCTRL */
+#define _CMU_TRACECLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */
+#define _CMU_TRACECLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */
+#define _CMU_TRACECLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_TRACECLKCTRL */
+#define _CMU_TRACECLKCTRL_CLKSEL_DISABLE 0x00000000UL /**< Mode DISABLE for CMU_TRACECLKCTRL */
+#define _CMU_TRACECLKCTRL_CLKSEL_SYSCLK 0x00000001UL /**< Mode SYSCLK for CMU_TRACECLKCTRL */
+#define _CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 0x00000002UL /**< Mode HFRCOEM23 for CMU_TRACECLKCTRL */
+#define _CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT 0x00000003UL /**< Mode HFRCODPLLRT for CMU_TRACECLKCTRL */
+#define CMU_TRACECLKCTRL_CLKSEL_DEFAULT (_CMU_TRACECLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_TRACECLKCTRL */
+#define CMU_TRACECLKCTRL_CLKSEL_DISABLE (_CMU_TRACECLKCTRL_CLKSEL_DISABLE << 0) /**< Shifted mode DISABLE for CMU_TRACECLKCTRL */
+#define CMU_TRACECLKCTRL_CLKSEL_SYSCLK (_CMU_TRACECLKCTRL_CLKSEL_SYSCLK << 0) /**< Shifted mode SYSCLK for CMU_TRACECLKCTRL */
+#define CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 (_CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_TRACECLKCTRL */
+#define CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_TRACECLKCTRL*/
+#define _CMU_TRACECLKCTRL_PRESC_SHIFT 4 /**< Shift value for CMU_PRESC */
+#define _CMU_TRACECLKCTRL_PRESC_MASK 0x30UL /**< Bit mask for CMU_PRESC */
+#define _CMU_TRACECLKCTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_TRACECLKCTRL */
+#define _CMU_TRACECLKCTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_TRACECLKCTRL */
+#define _CMU_TRACECLKCTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_TRACECLKCTRL */
+#define _CMU_TRACECLKCTRL_PRESC_DIV3 0x00000002UL /**< Mode DIV3 for CMU_TRACECLKCTRL */
+#define _CMU_TRACECLKCTRL_PRESC_DIV4 0x00000003UL /**< Mode DIV4 for CMU_TRACECLKCTRL */
+#define CMU_TRACECLKCTRL_PRESC_DEFAULT (_CMU_TRACECLKCTRL_PRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_TRACECLKCTRL */
+#define CMU_TRACECLKCTRL_PRESC_DIV1 (_CMU_TRACECLKCTRL_PRESC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_TRACECLKCTRL */
+#define CMU_TRACECLKCTRL_PRESC_DIV2 (_CMU_TRACECLKCTRL_PRESC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_TRACECLKCTRL */
+#define CMU_TRACECLKCTRL_PRESC_DIV3 (_CMU_TRACECLKCTRL_PRESC_DIV3 << 4) /**< Shifted mode DIV3 for CMU_TRACECLKCTRL */
+#define CMU_TRACECLKCTRL_PRESC_DIV4 (_CMU_TRACECLKCTRL_PRESC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_TRACECLKCTRL */
+
+/* Bit fields for CMU EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_MASK 0x1F0F0F0FUL /**< Mask for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_MASK 0xFUL /**< Bit mask for CMU_CLKOUTSEL0 */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 0x00000009UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK << 0) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_SHIFT 8 /**< Shift value for CMU_CLKOUTSEL1 */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_MASK 0xF00UL /**< Bit mask for CMU_CLKOUTSEL1 */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 0x00000009UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED << 8) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK << 8) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK << 8) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO << 8) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO << 8) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO << 8) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL << 8) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO << 8) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO << 8) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 << 8) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_SHIFT 16 /**< Shift value for CMU_CLKOUTSEL2 */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_MASK 0xF0000UL /**< Bit mask for CMU_CLKOUTSEL2 */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */
+#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 0x00000009UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED << 16) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK << 16) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK << 16) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO << 16) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO << 16) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL << 16) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO << 16) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO << 16) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */
+#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 << 16) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/
+#define _CMU_EXPORTCLKCTRL_PRESC_SHIFT 24 /**< Shift value for CMU_PRESC */
+#define _CMU_EXPORTCLKCTRL_PRESC_MASK 0x1F000000UL /**< Bit mask for CMU_PRESC */
+#define _CMU_EXPORTCLKCTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */
+#define CMU_EXPORTCLKCTRL_PRESC_DEFAULT (_CMU_EXPORTCLKCTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */
+
+/* Bit fields for CMU DPLLREFCLKCTRL */
+#define _CMU_DPLLREFCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLREFCLKCTRL */
+#define _CMU_DPLLREFCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_DPLLREFCLKCTRL */
+#define _CMU_DPLLREFCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */
+#define _CMU_DPLLREFCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */
+#define _CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLREFCLKCTRL */
+#define _CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_DPLLREFCLKCTRL */
+#define _CMU_DPLLREFCLKCTRL_CLKSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_DPLLREFCLKCTRL */
+#define _CMU_DPLLREFCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_DPLLREFCLKCTRL */
+#define _CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLREFCLKCTRL */
+#define CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT (_CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLREFCLKCTRL */
+#define CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED (_CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_DPLLREFCLKCTRL*/
+#define CMU_DPLLREFCLKCTRL_CLKSEL_HFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_DPLLREFCLKCTRL */
+#define CMU_DPLLREFCLKCTRL_CLKSEL_LFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_DPLLREFCLKCTRL */
+#define CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 (_CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_DPLLREFCLKCTRL */
+
+/* Bit fields for CMU EM01GRPACLKCTRL */
+#define _CMU_EM01GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPACLKCTRL */
+#define _CMU_EM01GRPACLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EM01GRPACLKCTRL */
+#define _CMU_EM01GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */
+#define _CMU_EM01GRPACLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */
+#define _CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPACLKCTRL */
+#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPACLKCTRL */
+#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPACLKCTRL */
+#define _CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPACLKCTRL */
+#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_EM01GRPACLKCTRL */
+#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT 0x00000005UL /**< Mode HFRCODPLLRT for CMU_EM01GRPACLKCTRL */
+#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT 0x00000006UL /**< Mode HFXORT for CMU_EM01GRPACLKCTRL */
+#define CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPACLKCTRL*/
+#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPACLKCTRL*/
+#define CMU_EM01GRPACLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPACLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPACLKCTRL */
+#define CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPACLKCTRL */
+#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EM01GRPACLKCTRL*/
+#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_EM01GRPACLKCTRL*/
+#define CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT (_CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT << 0) /**< Shifted mode HFXORT for CMU_EM01GRPACLKCTRL */
+
+/* Bit fields for CMU EM01GRPCCLKCTRL */
+#define _CMU_EM01GRPCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPCCLKCTRL */
+#define _CMU_EM01GRPCCLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EM01GRPCCLKCTRL */
+#define _CMU_EM01GRPCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */
+#define _CMU_EM01GRPCCLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */
+#define _CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPCCLKCTRL */
+#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPCCLKCTRL */
+#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPCCLKCTRL */
+#define _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPCCLKCTRL */
+#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_EM01GRPCCLKCTRL */
+#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT 0x00000005UL /**< Mode HFRCODPLLRT for CMU_EM01GRPCCLKCTRL */
+#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT 0x00000006UL /**< Mode HFXORT for CMU_EM01GRPCCLKCTRL */
+#define CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPCCLKCTRL*/
+#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPCCLKCTRL*/
+#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPCCLKCTRL */
+#define CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPCCLKCTRL */
+#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23 (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EM01GRPCCLKCTRL*/
+#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_EM01GRPCCLKCTRL*/
+#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT << 0) /**< Shifted mode HFXORT for CMU_EM01GRPCCLKCTRL */
+
+/* Bit fields for CMU EM23GRPACLKCTRL */
+#define _CMU_EM23GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM23GRPACLKCTRL */
+#define _CMU_EM23GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM23GRPACLKCTRL */
+#define _CMU_EM23GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */
+#define _CMU_EM23GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */
+#define _CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM23GRPACLKCTRL */
+#define _CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM23GRPACLKCTRL */
+#define _CMU_EM23GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM23GRPACLKCTRL */
+#define _CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM23GRPACLKCTRL */
+#define CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM23GRPACLKCTRL*/
+#define CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM23GRPACLKCTRL */
+#define CMU_EM23GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM23GRPACLKCTRL */
+#define CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM23GRPACLKCTRL */
+
+/* Bit fields for CMU EM4GRPACLKCTRL */
+#define _CMU_EM4GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM4GRPACLKCTRL */
+#define _CMU_EM4GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM4GRPACLKCTRL */
+#define _CMU_EM4GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */
+#define _CMU_EM4GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */
+#define _CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM4GRPACLKCTRL */
+#define _CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM4GRPACLKCTRL */
+#define _CMU_EM4GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM4GRPACLKCTRL */
+#define _CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM4GRPACLKCTRL */
+#define CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM4GRPACLKCTRL */
+#define CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM4GRPACLKCTRL */
+#define CMU_EM4GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM4GRPACLKCTRL */
+#define CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM4GRPACLKCTRL */
+
+/* Bit fields for CMU IADCCLKCTRL */
+#define _CMU_IADCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_IADCCLKCTRL */
+#define _CMU_IADCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_IADCCLKCTRL */
+#define _CMU_IADCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */
+#define _CMU_IADCCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */
+#define _CMU_IADCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IADCCLKCTRL */
+#define _CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_IADCCLKCTRL */
+#define _CMU_IADCCLKCTRL_CLKSEL_FSRCO 0x00000002UL /**< Mode FSRCO for CMU_IADCCLKCTRL */
+#define _CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 0x00000003UL /**< Mode HFRCOEM23 for CMU_IADCCLKCTRL */
+#define CMU_IADCCLKCTRL_CLKSEL_DEFAULT (_CMU_IADCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IADCCLKCTRL */
+#define CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK (_CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_IADCCLKCTRL*/
+#define CMU_IADCCLKCTRL_CLKSEL_FSRCO (_CMU_IADCCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_IADCCLKCTRL */
+#define CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 (_CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_IADCCLKCTRL */
+
+/* Bit fields for CMU WDOG0CLKCTRL */
+#define _CMU_WDOG0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_WDOG0CLKCTRL */
+#define _CMU_WDOG0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_WDOG0CLKCTRL */
+#define _CMU_WDOG0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */
+#define _CMU_WDOG0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */
+#define _CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_WDOG0CLKCTRL */
+#define _CMU_WDOG0CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_WDOG0CLKCTRL */
+#define _CMU_WDOG0CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_WDOG0CLKCTRL */
+#define _CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_WDOG0CLKCTRL */
+#define _CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 0x00000004UL /**< Mode HCLKDIV1024 for CMU_WDOG0CLKCTRL */
+#define CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT (_CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOG0CLKCTRL */
+#define CMU_WDOG0CLKCTRL_CLKSEL_LFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_WDOG0CLKCTRL */
+#define CMU_WDOG0CLKCTRL_CLKSEL_LFXO (_CMU_WDOG0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_WDOG0CLKCTRL */
+#define CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_WDOG0CLKCTRL */
+#define CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 (_CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 << 0) /**< Shifted mode HCLKDIV1024 for CMU_WDOG0CLKCTRL*/
+
+/* Bit fields for CMU WDOG1CLKCTRL */
+#define _CMU_WDOG1CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_WDOG1CLKCTRL */
+#define _CMU_WDOG1CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_WDOG1CLKCTRL */
+#define _CMU_WDOG1CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */
+#define _CMU_WDOG1CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */
+#define _CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_WDOG1CLKCTRL */
+#define _CMU_WDOG1CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_WDOG1CLKCTRL */
+#define _CMU_WDOG1CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_WDOG1CLKCTRL */
+#define _CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_WDOG1CLKCTRL */
+#define _CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 0x00000004UL /**< Mode HCLKDIV1024 for CMU_WDOG1CLKCTRL */
+#define CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT (_CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOG1CLKCTRL */
+#define CMU_WDOG1CLKCTRL_CLKSEL_LFRCO (_CMU_WDOG1CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_WDOG1CLKCTRL */
+#define CMU_WDOG1CLKCTRL_CLKSEL_LFXO (_CMU_WDOG1CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_WDOG1CLKCTRL */
+#define CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO (_CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_WDOG1CLKCTRL */
+#define CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 (_CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 << 0) /**< Shifted mode HCLKDIV1024 for CMU_WDOG1CLKCTRL*/
+
+/* Bit fields for CMU EUSART0CLKCTRL */
+#define _CMU_EUSART0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EUSART0CLKCTRL */
+#define _CMU_EUSART0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EUSART0CLKCTRL */
+#define _CMU_EUSART0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */
+#define _CMU_EUSART0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */
+#define _CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EUSART0CLKCTRL */
+#define _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EUSART0CLKCTRL */
+#define _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK 0x00000001UL /**< Mode EM01GRPCCLK for CMU_EUSART0CLKCTRL */
+#define _CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 0x00000002UL /**< Mode HFRCOEM23 for CMU_EUSART0CLKCTRL */
+#define _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_EUSART0CLKCTRL */
+#define _CMU_EUSART0CLKCTRL_CLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_EUSART0CLKCTRL */
+#define CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT (_CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EUSART0CLKCTRL */
+#define CMU_EUSART0CLKCTRL_CLKSEL_DISABLED (_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EUSART0CLKCTRL*/
+#define CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK (_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK << 0) /**< Shifted mode EM01GRPCCLK for CMU_EUSART0CLKCTRL*/
+#define CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 (_CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EUSART0CLKCTRL*/
+#define CMU_EUSART0CLKCTRL_CLKSEL_LFRCO (_CMU_EUSART0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EUSART0CLKCTRL */
+#define CMU_EUSART0CLKCTRL_CLKSEL_LFXO (_CMU_EUSART0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EUSART0CLKCTRL */
+
+/* Bit fields for CMU SYSRTC0CLKCTRL */
+#define _CMU_SYSRTC0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_SYSRTC0CLKCTRL */
+#define _CMU_SYSRTC0CLKCTRL_MASK 0x00000003UL /**< Mask for CMU_SYSRTC0CLKCTRL */
+#define _CMU_SYSRTC0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */
+#define _CMU_SYSRTC0CLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */
+#define _CMU_SYSRTC0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_SYSRTC0CLKCTRL */
+#define _CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_SYSRTC0CLKCTRL */
+#define _CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_SYSRTC0CLKCTRL */
+#define _CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_SYSRTC0CLKCTRL */
+#define CMU_SYSRTC0CLKCTRL_CLKSEL_DEFAULT (_CMU_SYSRTC0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYSRTC0CLKCTRL */
+#define CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO (_CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_SYSRTC0CLKCTRL */
+#define CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO (_CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_SYSRTC0CLKCTRL */
+#define CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO (_CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_SYSRTC0CLKCTRL */
+
+/* Bit fields for CMU VDAC0CLKCTRL */
+#define _CMU_VDAC0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_VDAC0CLKCTRL */
+#define _CMU_VDAC0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_VDAC0CLKCTRL */
+#define _CMU_VDAC0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */
+#define _CMU_VDAC0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */
+#define _CMU_VDAC0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_VDAC0CLKCTRL */
+#define _CMU_VDAC0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_VDAC0CLKCTRL */
+#define _CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_VDAC0CLKCTRL */
+#define _CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK 0x00000002UL /**< Mode EM23GRPACLK for CMU_VDAC0CLKCTRL */
+#define _CMU_VDAC0CLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_VDAC0CLKCTRL */
+#define _CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_VDAC0CLKCTRL */
+#define CMU_VDAC0CLKCTRL_CLKSEL_DEFAULT (_CMU_VDAC0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_VDAC0CLKCTRL */
+#define CMU_VDAC0CLKCTRL_CLKSEL_DISABLED (_CMU_VDAC0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_VDAC0CLKCTRL */
+#define CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK (_CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_VDAC0CLKCTRL*/
+#define CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK (_CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK << 0) /**< Shifted mode EM23GRPACLK for CMU_VDAC0CLKCTRL*/
+#define CMU_VDAC0CLKCTRL_CLKSEL_FSRCO (_CMU_VDAC0CLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_VDAC0CLKCTRL */
+#define CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23 (_CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_VDAC0CLKCTRL */
+
+/* Bit fields for CMU PCNT0CLKCTRL */
+#define _CMU_PCNT0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_PCNT0CLKCTRL */
+#define _CMU_PCNT0CLKCTRL_MASK 0x00000003UL /**< Mask for CMU_PCNT0CLKCTRL */
+#define _CMU_PCNT0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */
+#define _CMU_PCNT0CLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */
+#define _CMU_PCNT0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_PCNT0CLKCTRL */
+#define _CMU_PCNT0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_PCNT0CLKCTRL */
+#define _CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK 0x00000001UL /**< Mode EM23GRPACLK for CMU_PCNT0CLKCTRL */
+#define _CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0 0x00000002UL /**< Mode PCNTS0 for CMU_PCNT0CLKCTRL */
+#define CMU_PCNT0CLKCTRL_CLKSEL_DEFAULT (_CMU_PCNT0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNT0CLKCTRL */
+#define CMU_PCNT0CLKCTRL_CLKSEL_DISABLED (_CMU_PCNT0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_PCNT0CLKCTRL */
+#define CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK (_CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK << 0) /**< Shifted mode EM23GRPACLK for CMU_PCNT0CLKCTRL*/
+#define CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0 (_CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0 << 0) /**< Shifted mode PCNTS0 for CMU_PCNT0CLKCTRL */
+
+/* Bit fields for CMU RADIOCLKCTRL */
+#define _CMU_RADIOCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_RADIOCLKCTRL */
+#define _CMU_RADIOCLKCTRL_MASK 0x80000003UL /**< Mask for CMU_RADIOCLKCTRL */
+#define CMU_RADIOCLKCTRL_EN (0x1UL << 0) /**< Enable */
+#define _CMU_RADIOCLKCTRL_EN_SHIFT 0 /**< Shift value for CMU_EN */
+#define _CMU_RADIOCLKCTRL_EN_MASK 0x1UL /**< Bit mask for CMU_EN */
+#define _CMU_RADIOCLKCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */
+#define CMU_RADIOCLKCTRL_EN_DEFAULT (_CMU_RADIOCLKCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */
+#define CMU_RADIOCLKCTRL_DBGCLK (0x1UL << 31) /**< Enable Clock for Debugger */
+#define _CMU_RADIOCLKCTRL_DBGCLK_SHIFT 31 /**< Shift value for CMU_DBGCLK */
+#define _CMU_RADIOCLKCTRL_DBGCLK_MASK 0x80000000UL /**< Bit mask for CMU_DBGCLK */
+#define _CMU_RADIOCLKCTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */
+#define CMU_RADIOCLKCTRL_DBGCLK_DEFAULT (_CMU_RADIOCLKCTRL_DBGCLK_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */
+
+/* Bit fields for CMU VDAC1CLKCTRL */
+#define _CMU_VDAC1CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_VDAC1CLKCTRL */
+#define _CMU_VDAC1CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_VDAC1CLKCTRL */
+#define _CMU_VDAC1CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */
+#define _CMU_VDAC1CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */
+#define _CMU_VDAC1CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_VDAC1CLKCTRL */
+#define _CMU_VDAC1CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_VDAC1CLKCTRL */
+#define _CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_VDAC1CLKCTRL */
+#define _CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK 0x00000002UL /**< Mode EM23GRPACLK for CMU_VDAC1CLKCTRL */
+#define _CMU_VDAC1CLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_VDAC1CLKCTRL */
+#define _CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_VDAC1CLKCTRL */
+#define CMU_VDAC1CLKCTRL_CLKSEL_DEFAULT (_CMU_VDAC1CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_VDAC1CLKCTRL */
+#define CMU_VDAC1CLKCTRL_CLKSEL_DISABLED (_CMU_VDAC1CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_VDAC1CLKCTRL */
+#define CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK (_CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_VDAC1CLKCTRL*/
+#define CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK (_CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK << 0) /**< Shifted mode EM23GRPACLK for CMU_VDAC1CLKCTRL*/
+#define CMU_VDAC1CLKCTRL_CLKSEL_FSRCO (_CMU_VDAC1CLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_VDAC1CLKCTRL */
+#define CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23 (_CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_VDAC1CLKCTRL */
+
+/** @} End of group EFR32MG24_CMU_BitFields */
+/** @} End of group EFR32MG24_CMU */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_CMU_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_dcdc.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_dcdc.h
new file mode 100644
index 00000000..77dc91a0
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_dcdc.h
@@ -0,0 +1,436 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 DCDC register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_DCDC_H
+#define EFR32MG24_DCDC_H
+#define DCDC_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_DCDC DCDC
+ * @{
+ * @brief EFR32MG24 DCDC Register Declaration.
+ *****************************************************************************/
+
+/** DCDC Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IPVERSION */
+ __IOM uint32_t CTRL; /**< Control */
+ __IOM uint32_t EM01CTRL0; /**< EM01 Control */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+ __IOM uint32_t EM23CTRL0; /**< EM23 Control */
+ uint32_t RESERVED1[3U]; /**< Reserved for future use */
+ __IOM uint32_t PFMXCTRL; /**< PFMX Control Register */
+ uint32_t RESERVED2[1U]; /**< Reserved for future use */
+ __IOM uint32_t IF; /**< Interrupt Flags */
+ __IOM uint32_t IEN; /**< Interrupt Enable */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IM uint32_t SYNCBUSY; /**< Syncbusy Status Register */
+ uint32_t RESERVED3[2U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK; /**< Lock Register */
+ __IM uint32_t LOCKSTATUS; /**< Lock Status Register */
+ uint32_t RESERVED4[2U]; /**< Reserved for future use */
+ uint32_t RESERVED5[1U]; /**< Reserved for future use */
+ uint32_t RESERVED6[7U]; /**< Reserved for future use */
+ uint32_t RESERVED7[1U]; /**< Reserved for future use */
+ uint32_t RESERVED8[7U]; /**< Reserved for future use */
+ uint32_t RESERVED9[1U]; /**< Reserved for future use */
+ uint32_t RESERVED10[987U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IPVERSION */
+ __IOM uint32_t CTRL_SET; /**< Control */
+ __IOM uint32_t EM01CTRL0_SET; /**< EM01 Control */
+ uint32_t RESERVED11[1U]; /**< Reserved for future use */
+ __IOM uint32_t EM23CTRL0_SET; /**< EM23 Control */
+ uint32_t RESERVED12[3U]; /**< Reserved for future use */
+ __IOM uint32_t PFMXCTRL_SET; /**< PFMX Control Register */
+ uint32_t RESERVED13[1U]; /**< Reserved for future use */
+ __IOM uint32_t IF_SET; /**< Interrupt Flags */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable */
+ __IM uint32_t STATUS_SET; /**< Status Register */
+ __IM uint32_t SYNCBUSY_SET; /**< Syncbusy Status Register */
+ uint32_t RESERVED14[2U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK_SET; /**< Lock Register */
+ __IM uint32_t LOCKSTATUS_SET; /**< Lock Status Register */
+ uint32_t RESERVED15[2U]; /**< Reserved for future use */
+ uint32_t RESERVED16[1U]; /**< Reserved for future use */
+ uint32_t RESERVED17[7U]; /**< Reserved for future use */
+ uint32_t RESERVED18[1U]; /**< Reserved for future use */
+ uint32_t RESERVED19[7U]; /**< Reserved for future use */
+ uint32_t RESERVED20[1U]; /**< Reserved for future use */
+ uint32_t RESERVED21[987U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IPVERSION */
+ __IOM uint32_t CTRL_CLR; /**< Control */
+ __IOM uint32_t EM01CTRL0_CLR; /**< EM01 Control */
+ uint32_t RESERVED22[1U]; /**< Reserved for future use */
+ __IOM uint32_t EM23CTRL0_CLR; /**< EM23 Control */
+ uint32_t RESERVED23[3U]; /**< Reserved for future use */
+ __IOM uint32_t PFMXCTRL_CLR; /**< PFMX Control Register */
+ uint32_t RESERVED24[1U]; /**< Reserved for future use */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flags */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable */
+ __IM uint32_t STATUS_CLR; /**< Status Register */
+ __IM uint32_t SYNCBUSY_CLR; /**< Syncbusy Status Register */
+ uint32_t RESERVED25[2U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK_CLR; /**< Lock Register */
+ __IM uint32_t LOCKSTATUS_CLR; /**< Lock Status Register */
+ uint32_t RESERVED26[2U]; /**< Reserved for future use */
+ uint32_t RESERVED27[1U]; /**< Reserved for future use */
+ uint32_t RESERVED28[7U]; /**< Reserved for future use */
+ uint32_t RESERVED29[1U]; /**< Reserved for future use */
+ uint32_t RESERVED30[7U]; /**< Reserved for future use */
+ uint32_t RESERVED31[1U]; /**< Reserved for future use */
+ uint32_t RESERVED32[987U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IPVERSION */
+ __IOM uint32_t CTRL_TGL; /**< Control */
+ __IOM uint32_t EM01CTRL0_TGL; /**< EM01 Control */
+ uint32_t RESERVED33[1U]; /**< Reserved for future use */
+ __IOM uint32_t EM23CTRL0_TGL; /**< EM23 Control */
+ uint32_t RESERVED34[3U]; /**< Reserved for future use */
+ __IOM uint32_t PFMXCTRL_TGL; /**< PFMX Control Register */
+ uint32_t RESERVED35[1U]; /**< Reserved for future use */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flags */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable */
+ __IM uint32_t STATUS_TGL; /**< Status Register */
+ __IM uint32_t SYNCBUSY_TGL; /**< Syncbusy Status Register */
+ uint32_t RESERVED36[2U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK_TGL; /**< Lock Register */
+ __IM uint32_t LOCKSTATUS_TGL; /**< Lock Status Register */
+ uint32_t RESERVED37[2U]; /**< Reserved for future use */
+ uint32_t RESERVED38[1U]; /**< Reserved for future use */
+ uint32_t RESERVED39[7U]; /**< Reserved for future use */
+ uint32_t RESERVED40[1U]; /**< Reserved for future use */
+ uint32_t RESERVED41[7U]; /**< Reserved for future use */
+ uint32_t RESERVED42[1U]; /**< Reserved for future use */
+} DCDC_TypeDef;
+/** @} End of group EFR32MG24_DCDC */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_DCDC
+ * @{
+ * @defgroup EFR32MG24_DCDC_BitFields DCDC Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for DCDC IPVERSION */
+#define _DCDC_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for DCDC_IPVERSION */
+#define _DCDC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for DCDC_IPVERSION */
+#define _DCDC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for DCDC_IPVERSION */
+#define _DCDC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for DCDC_IPVERSION */
+#define _DCDC_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for DCDC_IPVERSION */
+#define DCDC_IPVERSION_IPVERSION_DEFAULT (_DCDC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IPVERSION */
+
+/* Bit fields for DCDC CTRL */
+#define _DCDC_CTRL_RESETVALUE 0x00000100UL /**< Default value for DCDC_CTRL */
+#define _DCDC_CTRL_MASK 0x800001F1UL /**< Mask for DCDC_CTRL */
+#define DCDC_CTRL_MODE (0x1UL << 0) /**< DCDC/Bypass Mode Control */
+#define _DCDC_CTRL_MODE_SHIFT 0 /**< Shift value for DCDC_MODE */
+#define _DCDC_CTRL_MODE_MASK 0x1UL /**< Bit mask for DCDC_MODE */
+#define _DCDC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */
+#define _DCDC_CTRL_MODE_BYPASS 0x00000000UL /**< Mode BYPASS for DCDC_CTRL */
+#define _DCDC_CTRL_MODE_DCDCREGULATION 0x00000001UL /**< Mode DCDCREGULATION for DCDC_CTRL */
+#define DCDC_CTRL_MODE_DEFAULT (_DCDC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CTRL */
+#define DCDC_CTRL_MODE_BYPASS (_DCDC_CTRL_MODE_BYPASS << 0) /**< Shifted mode BYPASS for DCDC_CTRL */
+#define DCDC_CTRL_MODE_DCDCREGULATION (_DCDC_CTRL_MODE_DCDCREGULATION << 0) /**< Shifted mode DCDCREGULATION for DCDC_CTRL */
+#define _DCDC_CTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */
+#define _DCDC_CTRL_IPKTMAXCTRL_MASK 0x1F0UL /**< Bit mask for DCDC_IPKTMAXCTRL */
+#define _DCDC_CTRL_IPKTMAXCTRL_DEFAULT 0x00000010UL /**< Mode DEFAULT for DCDC_CTRL */
+#define DCDC_CTRL_IPKTMAXCTRL_DEFAULT (_DCDC_CTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_CTRL */
+
+/* Bit fields for DCDC EM01CTRL0 */
+#define _DCDC_EM01CTRL0_RESETVALUE 0x00000109UL /**< Default value for DCDC_EM01CTRL0 */
+#define _DCDC_EM01CTRL0_MASK 0x0000030FUL /**< Mask for DCDC_EM01CTRL0 */
+#define _DCDC_EM01CTRL0_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */
+#define _DCDC_EM01CTRL0_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */
+#define _DCDC_EM01CTRL0_IPKVAL_DEFAULT 0x00000009UL /**< Mode DEFAULT for DCDC_EM01CTRL0 */
+#define _DCDC_EM01CTRL0_IPKVAL_Load36mA 0x00000003UL /**< Mode Load36mA for DCDC_EM01CTRL0 */
+#define _DCDC_EM01CTRL0_IPKVAL_Load40mA 0x00000004UL /**< Mode Load40mA for DCDC_EM01CTRL0 */
+#define _DCDC_EM01CTRL0_IPKVAL_Load44mA 0x00000005UL /**< Mode Load44mA for DCDC_EM01CTRL0 */
+#define _DCDC_EM01CTRL0_IPKVAL_Load48mA 0x00000006UL /**< Mode Load48mA for DCDC_EM01CTRL0 */
+#define _DCDC_EM01CTRL0_IPKVAL_Load52mA 0x00000007UL /**< Mode Load52mA for DCDC_EM01CTRL0 */
+#define _DCDC_EM01CTRL0_IPKVAL_Load56mA 0x00000008UL /**< Mode Load56mA for DCDC_EM01CTRL0 */
+#define _DCDC_EM01CTRL0_IPKVAL_Load60mA 0x00000009UL /**< Mode Load60mA for DCDC_EM01CTRL0 */
+#define DCDC_EM01CTRL0_IPKVAL_DEFAULT (_DCDC_EM01CTRL0_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_EM01CTRL0 */
+#define DCDC_EM01CTRL0_IPKVAL_Load36mA (_DCDC_EM01CTRL0_IPKVAL_Load36mA << 0) /**< Shifted mode Load36mA for DCDC_EM01CTRL0 */
+#define DCDC_EM01CTRL0_IPKVAL_Load40mA (_DCDC_EM01CTRL0_IPKVAL_Load40mA << 0) /**< Shifted mode Load40mA for DCDC_EM01CTRL0 */
+#define DCDC_EM01CTRL0_IPKVAL_Load44mA (_DCDC_EM01CTRL0_IPKVAL_Load44mA << 0) /**< Shifted mode Load44mA for DCDC_EM01CTRL0 */
+#define DCDC_EM01CTRL0_IPKVAL_Load48mA (_DCDC_EM01CTRL0_IPKVAL_Load48mA << 0) /**< Shifted mode Load48mA for DCDC_EM01CTRL0 */
+#define DCDC_EM01CTRL0_IPKVAL_Load52mA (_DCDC_EM01CTRL0_IPKVAL_Load52mA << 0) /**< Shifted mode Load52mA for DCDC_EM01CTRL0 */
+#define DCDC_EM01CTRL0_IPKVAL_Load56mA (_DCDC_EM01CTRL0_IPKVAL_Load56mA << 0) /**< Shifted mode Load56mA for DCDC_EM01CTRL0 */
+#define DCDC_EM01CTRL0_IPKVAL_Load60mA (_DCDC_EM01CTRL0_IPKVAL_Load60mA << 0) /**< Shifted mode Load60mA for DCDC_EM01CTRL0 */
+#define _DCDC_EM01CTRL0_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */
+#define _DCDC_EM01CTRL0_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */
+#define _DCDC_EM01CTRL0_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_EM01CTRL0 */
+#define _DCDC_EM01CTRL0_DRVSPEED_BEST_EMI 0x00000000UL /**< Mode BEST_EMI for DCDC_EM01CTRL0 */
+#define _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_EM01CTRL0 */
+#define _DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE 0x00000002UL /**< Mode INTERMEDIATE for DCDC_EM01CTRL0 */
+#define _DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY 0x00000003UL /**< Mode BEST_EFFICIENCY for DCDC_EM01CTRL0 */
+#define DCDC_EM01CTRL0_DRVSPEED_DEFAULT (_DCDC_EM01CTRL0_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_EM01CTRL0 */
+#define DCDC_EM01CTRL0_DRVSPEED_BEST_EMI (_DCDC_EM01CTRL0_DRVSPEED_BEST_EMI << 8) /**< Shifted mode BEST_EMI for DCDC_EM01CTRL0 */
+#define DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING (_DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_EM01CTRL0*/
+#define DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE (_DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE << 8) /**< Shifted mode INTERMEDIATE for DCDC_EM01CTRL0*/
+#define DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY (_DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY << 8) /**< Shifted mode BEST_EFFICIENCY for DCDC_EM01CTRL0*/
+
+/* Bit fields for DCDC EM23CTRL0 */
+#define _DCDC_EM23CTRL0_RESETVALUE 0x00000103UL /**< Default value for DCDC_EM23CTRL0 */
+#define _DCDC_EM23CTRL0_MASK 0x0000030FUL /**< Mask for DCDC_EM23CTRL0 */
+#define _DCDC_EM23CTRL0_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */
+#define _DCDC_EM23CTRL0_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */
+#define _DCDC_EM23CTRL0_IPKVAL_DEFAULT 0x00000003UL /**< Mode DEFAULT for DCDC_EM23CTRL0 */
+#define _DCDC_EM23CTRL0_IPKVAL_Load36mA 0x00000003UL /**< Mode Load36mA for DCDC_EM23CTRL0 */
+#define _DCDC_EM23CTRL0_IPKVAL_Load40mA 0x00000004UL /**< Mode Load40mA for DCDC_EM23CTRL0 */
+#define _DCDC_EM23CTRL0_IPKVAL_Load44mA 0x00000005UL /**< Mode Load44mA for DCDC_EM23CTRL0 */
+#define _DCDC_EM23CTRL0_IPKVAL_Load48mA 0x00000006UL /**< Mode Load48mA for DCDC_EM23CTRL0 */
+#define _DCDC_EM23CTRL0_IPKVAL_Load52mA 0x00000007UL /**< Mode Load52mA for DCDC_EM23CTRL0 */
+#define _DCDC_EM23CTRL0_IPKVAL_Load56mA 0x00000008UL /**< Mode Load56mA for DCDC_EM23CTRL0 */
+#define _DCDC_EM23CTRL0_IPKVAL_Load60mA 0x00000009UL /**< Mode Load60mA for DCDC_EM23CTRL0 */
+#define DCDC_EM23CTRL0_IPKVAL_DEFAULT (_DCDC_EM23CTRL0_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_EM23CTRL0 */
+#define DCDC_EM23CTRL0_IPKVAL_Load36mA (_DCDC_EM23CTRL0_IPKVAL_Load36mA << 0) /**< Shifted mode Load36mA for DCDC_EM23CTRL0 */
+#define DCDC_EM23CTRL0_IPKVAL_Load40mA (_DCDC_EM23CTRL0_IPKVAL_Load40mA << 0) /**< Shifted mode Load40mA for DCDC_EM23CTRL0 */
+#define DCDC_EM23CTRL0_IPKVAL_Load44mA (_DCDC_EM23CTRL0_IPKVAL_Load44mA << 0) /**< Shifted mode Load44mA for DCDC_EM23CTRL0 */
+#define DCDC_EM23CTRL0_IPKVAL_Load48mA (_DCDC_EM23CTRL0_IPKVAL_Load48mA << 0) /**< Shifted mode Load48mA for DCDC_EM23CTRL0 */
+#define DCDC_EM23CTRL0_IPKVAL_Load52mA (_DCDC_EM23CTRL0_IPKVAL_Load52mA << 0) /**< Shifted mode Load52mA for DCDC_EM23CTRL0 */
+#define DCDC_EM23CTRL0_IPKVAL_Load56mA (_DCDC_EM23CTRL0_IPKVAL_Load56mA << 0) /**< Shifted mode Load56mA for DCDC_EM23CTRL0 */
+#define DCDC_EM23CTRL0_IPKVAL_Load60mA (_DCDC_EM23CTRL0_IPKVAL_Load60mA << 0) /**< Shifted mode Load60mA for DCDC_EM23CTRL0 */
+#define _DCDC_EM23CTRL0_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */
+#define _DCDC_EM23CTRL0_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */
+#define _DCDC_EM23CTRL0_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_EM23CTRL0 */
+#define _DCDC_EM23CTRL0_DRVSPEED_BEST_EMI 0x00000000UL /**< Mode BEST_EMI for DCDC_EM23CTRL0 */
+#define _DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_EM23CTRL0 */
+#define _DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE 0x00000002UL /**< Mode INTERMEDIATE for DCDC_EM23CTRL0 */
+#define _DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY 0x00000003UL /**< Mode BEST_EFFICIENCY for DCDC_EM23CTRL0 */
+#define DCDC_EM23CTRL0_DRVSPEED_DEFAULT (_DCDC_EM23CTRL0_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_EM23CTRL0 */
+#define DCDC_EM23CTRL0_DRVSPEED_BEST_EMI (_DCDC_EM23CTRL0_DRVSPEED_BEST_EMI << 8) /**< Shifted mode BEST_EMI for DCDC_EM23CTRL0 */
+#define DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING (_DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_EM23CTRL0*/
+#define DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE (_DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE << 8) /**< Shifted mode INTERMEDIATE for DCDC_EM23CTRL0*/
+#define DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY (_DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY << 8) /**< Shifted mode BEST_EFFICIENCY for DCDC_EM23CTRL0*/
+
+/* Bit fields for DCDC PFMXCTRL */
+#define _DCDC_PFMXCTRL_RESETVALUE 0x00000B0CUL /**< Default value for DCDC_PFMXCTRL */
+#define _DCDC_PFMXCTRL_MASK 0x00001F0FUL /**< Mask for DCDC_PFMXCTRL */
+#define _DCDC_PFMXCTRL_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */
+#define _DCDC_PFMXCTRL_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */
+#define _DCDC_PFMXCTRL_IPKVAL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for DCDC_PFMXCTRL */
+#define DCDC_PFMXCTRL_IPKVAL_DEFAULT (_DCDC_PFMXCTRL_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_PFMXCTRL */
+#define _DCDC_PFMXCTRL_IPKTMAXCTRL_SHIFT 8 /**< Shift value for DCDC_IPKTMAXCTRL */
+#define _DCDC_PFMXCTRL_IPKTMAXCTRL_MASK 0x1F00UL /**< Bit mask for DCDC_IPKTMAXCTRL */
+#define _DCDC_PFMXCTRL_IPKTMAXCTRL_DEFAULT 0x0000000BUL /**< Mode DEFAULT for DCDC_PFMXCTRL */
+#define DCDC_PFMXCTRL_IPKTMAXCTRL_DEFAULT (_DCDC_PFMXCTRL_IPKTMAXCTRL_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_PFMXCTRL */
+
+/* Bit fields for DCDC IF */
+#define _DCDC_IF_RESETVALUE 0x00000000UL /**< Default value for DCDC_IF */
+#define _DCDC_IF_MASK 0x000003FFUL /**< Mask for DCDC_IF */
+#define DCDC_IF_BYPSW (0x1UL << 0) /**< Bypass Switch Enabled */
+#define _DCDC_IF_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */
+#define _DCDC_IF_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */
+#define _DCDC_IF_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */
+#define DCDC_IF_BYPSW_DEFAULT (_DCDC_IF_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IF */
+#define DCDC_IF_WARM (0x1UL << 1) /**< DCDC Warmup Time Done */
+#define _DCDC_IF_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */
+#define _DCDC_IF_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */
+#define _DCDC_IF_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */
+#define DCDC_IF_WARM_DEFAULT (_DCDC_IF_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_IF */
+#define DCDC_IF_RUNNING (0x1UL << 2) /**< DCDC Running */
+#define _DCDC_IF_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */
+#define _DCDC_IF_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */
+#define _DCDC_IF_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */
+#define DCDC_IF_RUNNING_DEFAULT (_DCDC_IF_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_IF */
+#define DCDC_IF_VREGINLOW (0x1UL << 3) /**< VREGIN below threshold */
+#define _DCDC_IF_VREGINLOW_SHIFT 3 /**< Shift value for DCDC_VREGINLOW */
+#define _DCDC_IF_VREGINLOW_MASK 0x8UL /**< Bit mask for DCDC_VREGINLOW */
+#define _DCDC_IF_VREGINLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */
+#define DCDC_IF_VREGINLOW_DEFAULT (_DCDC_IF_VREGINLOW_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_IF */
+#define DCDC_IF_VREGINHIGH (0x1UL << 4) /**< VREGIN above threshold */
+#define _DCDC_IF_VREGINHIGH_SHIFT 4 /**< Shift value for DCDC_VREGINHIGH */
+#define _DCDC_IF_VREGINHIGH_MASK 0x10UL /**< Bit mask for DCDC_VREGINHIGH */
+#define _DCDC_IF_VREGINHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */
+#define DCDC_IF_VREGINHIGH_DEFAULT (_DCDC_IF_VREGINHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_IF */
+#define DCDC_IF_REGULATION (0x1UL << 5) /**< DCDC in regulation */
+#define _DCDC_IF_REGULATION_SHIFT 5 /**< Shift value for DCDC_REGULATION */
+#define _DCDC_IF_REGULATION_MASK 0x20UL /**< Bit mask for DCDC_REGULATION */
+#define _DCDC_IF_REGULATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */
+#define DCDC_IF_REGULATION_DEFAULT (_DCDC_IF_REGULATION_DEFAULT << 5) /**< Shifted mode DEFAULT for DCDC_IF */
+#define DCDC_IF_TMAX (0x1UL << 6) /**< Ton_max Timeout Reached */
+#define _DCDC_IF_TMAX_SHIFT 6 /**< Shift value for DCDC_TMAX */
+#define _DCDC_IF_TMAX_MASK 0x40UL /**< Bit mask for DCDC_TMAX */
+#define _DCDC_IF_TMAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */
+#define DCDC_IF_TMAX_DEFAULT (_DCDC_IF_TMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for DCDC_IF */
+#define DCDC_IF_EM4ERR (0x1UL << 7) /**< EM4 Entry Request Error */
+#define _DCDC_IF_EM4ERR_SHIFT 7 /**< Shift value for DCDC_EM4ERR */
+#define _DCDC_IF_EM4ERR_MASK 0x80UL /**< Bit mask for DCDC_EM4ERR */
+#define _DCDC_IF_EM4ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */
+#define DCDC_IF_EM4ERR_DEFAULT (_DCDC_IF_EM4ERR_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_IF */
+#define DCDC_IF_PFMXMODE (0x1UL << 9) /**< Entered PFMX mode */
+#define _DCDC_IF_PFMXMODE_SHIFT 9 /**< Shift value for DCDC_PFMXMODE */
+#define _DCDC_IF_PFMXMODE_MASK 0x200UL /**< Bit mask for DCDC_PFMXMODE */
+#define _DCDC_IF_PFMXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */
+#define DCDC_IF_PFMXMODE_DEFAULT (_DCDC_IF_PFMXMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for DCDC_IF */
+
+/* Bit fields for DCDC IEN */
+#define _DCDC_IEN_RESETVALUE 0x00000000UL /**< Default value for DCDC_IEN */
+#define _DCDC_IEN_MASK 0x000003FFUL /**< Mask for DCDC_IEN */
+#define DCDC_IEN_BYPSW (0x1UL << 0) /**< Bypass Switch Enabled Interrupt Enable */
+#define _DCDC_IEN_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */
+#define _DCDC_IEN_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */
+#define _DCDC_IEN_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */
+#define DCDC_IEN_BYPSW_DEFAULT (_DCDC_IEN_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IEN */
+#define DCDC_IEN_WARM (0x1UL << 1) /**< DCDC Warmup Time Done Interrupt Enable */
+#define _DCDC_IEN_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */
+#define _DCDC_IEN_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */
+#define _DCDC_IEN_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */
+#define DCDC_IEN_WARM_DEFAULT (_DCDC_IEN_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_IEN */
+#define DCDC_IEN_RUNNING (0x1UL << 2) /**< DCDC Running Interrupt Enable */
+#define _DCDC_IEN_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */
+#define _DCDC_IEN_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */
+#define _DCDC_IEN_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */
+#define DCDC_IEN_RUNNING_DEFAULT (_DCDC_IEN_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_IEN */
+#define DCDC_IEN_VREGINLOW (0x1UL << 3) /**< VREGIN below threshold Interrupt Enable */
+#define _DCDC_IEN_VREGINLOW_SHIFT 3 /**< Shift value for DCDC_VREGINLOW */
+#define _DCDC_IEN_VREGINLOW_MASK 0x8UL /**< Bit mask for DCDC_VREGINLOW */
+#define _DCDC_IEN_VREGINLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */
+#define DCDC_IEN_VREGINLOW_DEFAULT (_DCDC_IEN_VREGINLOW_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_IEN */
+#define DCDC_IEN_VREGINHIGH (0x1UL << 4) /**< VREGIN above threshold Interrupt Enable */
+#define _DCDC_IEN_VREGINHIGH_SHIFT 4 /**< Shift value for DCDC_VREGINHIGH */
+#define _DCDC_IEN_VREGINHIGH_MASK 0x10UL /**< Bit mask for DCDC_VREGINHIGH */
+#define _DCDC_IEN_VREGINHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */
+#define DCDC_IEN_VREGINHIGH_DEFAULT (_DCDC_IEN_VREGINHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_IEN */
+#define DCDC_IEN_REGULATION (0x1UL << 5) /**< DCDC in Regulation Interrupt Enable */
+#define _DCDC_IEN_REGULATION_SHIFT 5 /**< Shift value for DCDC_REGULATION */
+#define _DCDC_IEN_REGULATION_MASK 0x20UL /**< Bit mask for DCDC_REGULATION */
+#define _DCDC_IEN_REGULATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */
+#define DCDC_IEN_REGULATION_DEFAULT (_DCDC_IEN_REGULATION_DEFAULT << 5) /**< Shifted mode DEFAULT for DCDC_IEN */
+#define DCDC_IEN_TMAX (0x1UL << 6) /**< Ton_max Timeout Interrupt Enable */
+#define _DCDC_IEN_TMAX_SHIFT 6 /**< Shift value for DCDC_TMAX */
+#define _DCDC_IEN_TMAX_MASK 0x40UL /**< Bit mask for DCDC_TMAX */
+#define _DCDC_IEN_TMAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */
+#define DCDC_IEN_TMAX_DEFAULT (_DCDC_IEN_TMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for DCDC_IEN */
+#define DCDC_IEN_EM4ERR (0x1UL << 7) /**< EM4 Entry Req Interrupt Enable */
+#define _DCDC_IEN_EM4ERR_SHIFT 7 /**< Shift value for DCDC_EM4ERR */
+#define _DCDC_IEN_EM4ERR_MASK 0x80UL /**< Bit mask for DCDC_EM4ERR */
+#define _DCDC_IEN_EM4ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */
+#define DCDC_IEN_EM4ERR_DEFAULT (_DCDC_IEN_EM4ERR_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_IEN */
+#define DCDC_IEN_PFMXMODE (0x1UL << 9) /**< PFMX Mode Interrupt Enable */
+#define _DCDC_IEN_PFMXMODE_SHIFT 9 /**< Shift value for DCDC_PFMXMODE */
+#define _DCDC_IEN_PFMXMODE_MASK 0x200UL /**< Bit mask for DCDC_PFMXMODE */
+#define _DCDC_IEN_PFMXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */
+#define DCDC_IEN_PFMXMODE_DEFAULT (_DCDC_IEN_PFMXMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for DCDC_IEN */
+
+/* Bit fields for DCDC STATUS */
+#define _DCDC_STATUS_RESETVALUE 0x00000000UL /**< Default value for DCDC_STATUS */
+#define _DCDC_STATUS_MASK 0x0000071FUL /**< Mask for DCDC_STATUS */
+#define DCDC_STATUS_BYPSW (0x1UL << 0) /**< Bypass Switch is currently enabled */
+#define _DCDC_STATUS_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */
+#define _DCDC_STATUS_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */
+#define _DCDC_STATUS_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */
+#define DCDC_STATUS_BYPSW_DEFAULT (_DCDC_STATUS_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_STATUS */
+#define DCDC_STATUS_WARM (0x1UL << 1) /**< DCDC Warmup Done */
+#define _DCDC_STATUS_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */
+#define _DCDC_STATUS_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */
+#define _DCDC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */
+#define DCDC_STATUS_WARM_DEFAULT (_DCDC_STATUS_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_STATUS */
+#define DCDC_STATUS_RUNNING (0x1UL << 2) /**< DCDC is running */
+#define _DCDC_STATUS_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */
+#define _DCDC_STATUS_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */
+#define _DCDC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */
+#define DCDC_STATUS_RUNNING_DEFAULT (_DCDC_STATUS_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_STATUS */
+#define DCDC_STATUS_VREGIN (0x1UL << 3) /**< VREGIN comparator status */
+#define _DCDC_STATUS_VREGIN_SHIFT 3 /**< Shift value for DCDC_VREGIN */
+#define _DCDC_STATUS_VREGIN_MASK 0x8UL /**< Bit mask for DCDC_VREGIN */
+#define _DCDC_STATUS_VREGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */
+#define DCDC_STATUS_VREGIN_DEFAULT (_DCDC_STATUS_VREGIN_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_STATUS */
+#define DCDC_STATUS_BYPCMPOUT (0x1UL << 4) /**< Bypass Comparator Output */
+#define _DCDC_STATUS_BYPCMPOUT_SHIFT 4 /**< Shift value for DCDC_BYPCMPOUT */
+#define _DCDC_STATUS_BYPCMPOUT_MASK 0x10UL /**< Bit mask for DCDC_BYPCMPOUT */
+#define _DCDC_STATUS_BYPCMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */
+#define DCDC_STATUS_BYPCMPOUT_DEFAULT (_DCDC_STATUS_BYPCMPOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_STATUS */
+#define DCDC_STATUS_PFMXMODE (0x1UL << 9) /**< DCDC in PFMX mode */
+#define _DCDC_STATUS_PFMXMODE_SHIFT 9 /**< Shift value for DCDC_PFMXMODE */
+#define _DCDC_STATUS_PFMXMODE_MASK 0x200UL /**< Bit mask for DCDC_PFMXMODE */
+#define _DCDC_STATUS_PFMXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */
+#define DCDC_STATUS_PFMXMODE_DEFAULT (_DCDC_STATUS_PFMXMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for DCDC_STATUS */
+
+/* Bit fields for DCDC SYNCBUSY */
+#define _DCDC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for DCDC_SYNCBUSY */
+#define _DCDC_SYNCBUSY_MASK 0x000000FFUL /**< Mask for DCDC_SYNCBUSY */
+#define DCDC_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Sync Busy Status */
+#define _DCDC_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for DCDC_CTRL */
+#define _DCDC_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for DCDC_CTRL */
+#define _DCDC_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */
+#define DCDC_SYNCBUSY_CTRL_DEFAULT (_DCDC_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */
+#define DCDC_SYNCBUSY_EM01CTRL0 (0x1UL << 1) /**< EM01CTRL0 Sync Busy Status */
+#define _DCDC_SYNCBUSY_EM01CTRL0_SHIFT 1 /**< Shift value for DCDC_EM01CTRL0 */
+#define _DCDC_SYNCBUSY_EM01CTRL0_MASK 0x2UL /**< Bit mask for DCDC_EM01CTRL0 */
+#define _DCDC_SYNCBUSY_EM01CTRL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */
+#define DCDC_SYNCBUSY_EM01CTRL0_DEFAULT (_DCDC_SYNCBUSY_EM01CTRL0_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */
+#define DCDC_SYNCBUSY_EM01CTRL1 (0x1UL << 2) /**< EM01CTRL1 Sync Bust Status */
+#define _DCDC_SYNCBUSY_EM01CTRL1_SHIFT 2 /**< Shift value for DCDC_EM01CTRL1 */
+#define _DCDC_SYNCBUSY_EM01CTRL1_MASK 0x4UL /**< Bit mask for DCDC_EM01CTRL1 */
+#define _DCDC_SYNCBUSY_EM01CTRL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */
+#define DCDC_SYNCBUSY_EM01CTRL1_DEFAULT (_DCDC_SYNCBUSY_EM01CTRL1_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */
+#define DCDC_SYNCBUSY_EM23CTRL0 (0x1UL << 3) /**< EM23CTRL0 Sync Busy Status */
+#define _DCDC_SYNCBUSY_EM23CTRL0_SHIFT 3 /**< Shift value for DCDC_EM23CTRL0 */
+#define _DCDC_SYNCBUSY_EM23CTRL0_MASK 0x8UL /**< Bit mask for DCDC_EM23CTRL0 */
+#define _DCDC_SYNCBUSY_EM23CTRL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */
+#define DCDC_SYNCBUSY_EM23CTRL0_DEFAULT (_DCDC_SYNCBUSY_EM23CTRL0_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */
+#define DCDC_SYNCBUSY_PFMXCTRL (0x1UL << 7) /**< PFMXCTRL Sync Busy Status */
+#define _DCDC_SYNCBUSY_PFMXCTRL_SHIFT 7 /**< Shift value for DCDC_PFMXCTRL */
+#define _DCDC_SYNCBUSY_PFMXCTRL_MASK 0x80UL /**< Bit mask for DCDC_PFMXCTRL */
+#define _DCDC_SYNCBUSY_PFMXCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */
+#define DCDC_SYNCBUSY_PFMXCTRL_DEFAULT (_DCDC_SYNCBUSY_PFMXCTRL_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */
+
+/* Bit fields for DCDC LOCK */
+#define _DCDC_LOCK_RESETVALUE 0x00000000UL /**< Default value for DCDC_LOCK */
+#define _DCDC_LOCK_MASK 0x0000FFFFUL /**< Mask for DCDC_LOCK */
+#define _DCDC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for DCDC_LOCKKEY */
+#define _DCDC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for DCDC_LOCKKEY */
+#define _DCDC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_LOCK */
+#define _DCDC_LOCK_LOCKKEY_UNLOCKKEY 0x0000ABCDUL /**< Mode UNLOCKKEY for DCDC_LOCK */
+#define DCDC_LOCK_LOCKKEY_DEFAULT (_DCDC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_LOCK */
+#define DCDC_LOCK_LOCKKEY_UNLOCKKEY (_DCDC_LOCK_LOCKKEY_UNLOCKKEY << 0) /**< Shifted mode UNLOCKKEY for DCDC_LOCK */
+
+/* Bit fields for DCDC LOCKSTATUS */
+#define _DCDC_LOCKSTATUS_RESETVALUE 0x00000000UL /**< Default value for DCDC_LOCKSTATUS */
+#define _DCDC_LOCKSTATUS_MASK 0x00000001UL /**< Mask for DCDC_LOCKSTATUS */
+#define DCDC_LOCKSTATUS_LOCK (0x1UL << 0) /**< Lock Status */
+#define _DCDC_LOCKSTATUS_LOCK_SHIFT 0 /**< Shift value for DCDC_LOCK */
+#define _DCDC_LOCKSTATUS_LOCK_MASK 0x1UL /**< Bit mask for DCDC_LOCK */
+#define _DCDC_LOCKSTATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_LOCKSTATUS */
+#define _DCDC_LOCKSTATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for DCDC_LOCKSTATUS */
+#define _DCDC_LOCKSTATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for DCDC_LOCKSTATUS */
+#define DCDC_LOCKSTATUS_LOCK_DEFAULT (_DCDC_LOCKSTATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_LOCKSTATUS */
+#define DCDC_LOCKSTATUS_LOCK_UNLOCKED (_DCDC_LOCKSTATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for DCDC_LOCKSTATUS */
+#define DCDC_LOCKSTATUS_LOCK_LOCKED (_DCDC_LOCKSTATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for DCDC_LOCKSTATUS */
+
+/** @} End of group EFR32MG24_DCDC_BitFields */
+/** @} End of group EFR32MG24_DCDC */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_DCDC_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_devinfo.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_devinfo.h
new file mode 100644
index 00000000..aec0de88
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_devinfo.h
@@ -0,0 +1,976 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 DEVINFO register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_DEVINFO_H
+#define EFR32MG24_DEVINFO_H
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_DEVINFO DEVINFO
+ * @{
+ * @brief EFR32MG24 DEVINFO Register Declaration.
+ *****************************************************************************/
+
+/** DEVINFO HFRCODPLLCAL Register Group Declaration. */
+typedef struct {
+ __IM uint32_t HFRCODPLLCAL; /**< HFRCODPLL Calibration */
+} DEVINFO_HFRCODPLLCAL_TypeDef;
+
+/** DEVINFO HFRCOEM23CAL Register Group Declaration. */
+typedef struct {
+ __IM uint32_t HFRCOEM23CAL; /**< HFRCOEM23 Calibration */
+} DEVINFO_HFRCOEM23CAL_TypeDef;
+
+/** DEVINFO HFRCOSECAL Register Group Declaration. */
+typedef struct {
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+} DEVINFO_HFRCOSECAL_TypeDef;
+
+/** DEVINFO Register Declaration. */
+typedef struct {
+ __IM uint32_t INFO; /**< DI Information */
+ __IM uint32_t PART; /**< Part Info */
+ __IM uint32_t MEMINFO; /**< Memory Info */
+ __IM uint32_t MSIZE; /**< Memory Size */
+ __IM uint32_t PKGINFO; /**< Misc Device Info */
+ __IM uint32_t CUSTOMINFO; /**< Custom Part Info */
+ __IM uint32_t SWFIX; /**< SW Fix Register */
+ __IM uint32_t SWCAPA0; /**< Software Restriction */
+ __IM uint32_t SWCAPA1; /**< Software Restriction */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+ __IM uint32_t EXTINFO; /**< External Component Info */
+ uint32_t RESERVED1[2U]; /**< Reserved for future use */
+ uint32_t RESERVED2[3U]; /**< Reserved for future use */
+ __IM uint32_t EUI48L; /**< EUI 48 Low */
+ __IM uint32_t EUI48H; /**< EUI 48 High */
+ __IM uint32_t EUI64L; /**< EUI64 Low */
+ __IM uint32_t EUI64H; /**< EUI64 High */
+ __IM uint32_t CALTEMP; /**< Calibration temperature */
+ __IM uint32_t EMUTEMP; /**< EMU Temp */
+ DEVINFO_HFRCODPLLCAL_TypeDef HFRCODPLLCAL[18U]; /**< */
+ DEVINFO_HFRCOEM23CAL_TypeDef HFRCOEM23CAL[18U]; /**< */
+ DEVINFO_HFRCOSECAL_TypeDef HFRCOSECAL[18U]; /**< */
+ __IM uint32_t MODULENAME0; /**< Module Name Information */
+ __IM uint32_t MODULENAME1; /**< Module Name Information */
+ __IM uint32_t MODULENAME2; /**< Module Name Information */
+ __IM uint32_t MODULENAME3; /**< Module Name Information */
+ __IM uint32_t MODULENAME4; /**< Module Name Information */
+ __IM uint32_t MODULENAME5; /**< Module Name Information */
+ __IM uint32_t MODULENAME6; /**< Module Name Information */
+ __IM uint32_t MODULEINFO; /**< Module Information */
+ __IM uint32_t MODXOCAL; /**< Module External Oscillator Calibration Information */
+ uint32_t RESERVED3[11U]; /**< Reserved for future use */
+ __IM uint32_t IADC0GAIN0; /**< IADC Gain Calibration */
+ __IM uint32_t IADC0GAIN1; /**< IADC Gain Calibration */
+ __IM uint32_t IADC0OFFSETCAL0; /**< IADC Offset Calibration */
+ __IM uint32_t IADC0NORMALOFFSETCAL0; /**< IADC Offset Calibration */
+ __IM uint32_t IADC0NORMALOFFSETCAL1; /**< IADC Offset Calibration */
+ __IM uint32_t IADC0HISPDOFFSETCAL0; /**< IADC Offset Calibration */
+ __IM uint32_t IADC0HISPDOFFSETCAL1; /**< IADC Offset Calibration */
+ uint32_t RESERVED4[24U]; /**< Reserved for future use */
+ __IM uint32_t LEGACY; /**< Legacy Device Info */
+ uint32_t RESERVED5[23U]; /**< Reserved for future use */
+ __IM uint32_t RTHERM; /**< Thermistor Calibration */
+ uint32_t RESERVED6[1U]; /**< Reserved for future use */
+ __IM uint32_t FENOTCHCAL; /**< FENOTCH Calibration */
+ uint32_t RESERVED7[78U]; /**< Reserved for future use */
+ uint32_t RESERVED8[1U]; /**< Reserved for future use */
+} DEVINFO_TypeDef;
+/** @} End of group EFR32MG24_DEVINFO */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_DEVINFO
+ * @{
+ * @defgroup EFR32MG24_DEVINFO_BitFields DEVINFO Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for DEVINFO INFO */
+#define _DEVINFO_INFO_RESETVALUE 0x0B000000UL /**< Default value for DEVINFO_INFO */
+#define _DEVINFO_INFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_INFO */
+#define _DEVINFO_INFO_CRC_SHIFT 0 /**< Shift value for DEVINFO_CRC */
+#define _DEVINFO_INFO_CRC_MASK 0xFFFFUL /**< Bit mask for DEVINFO_CRC */
+#define _DEVINFO_INFO_CRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_INFO */
+#define DEVINFO_INFO_CRC_DEFAULT (_DEVINFO_INFO_CRC_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_INFO */
+#define _DEVINFO_INFO_PRODREV_SHIFT 16 /**< Shift value for DEVINFO_PRODREV */
+#define _DEVINFO_INFO_PRODREV_MASK 0xFF0000UL /**< Bit mask for DEVINFO_PRODREV */
+#define _DEVINFO_INFO_PRODREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_INFO */
+#define DEVINFO_INFO_PRODREV_DEFAULT (_DEVINFO_INFO_PRODREV_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_INFO */
+#define _DEVINFO_INFO_DEVINFOREV_SHIFT 24 /**< Shift value for DEVINFO_DEVINFOREV */
+#define _DEVINFO_INFO_DEVINFOREV_MASK 0xFF000000UL /**< Bit mask for DEVINFO_DEVINFOREV */
+#define _DEVINFO_INFO_DEVINFOREV_DEFAULT 0x0000000BUL /**< Mode DEFAULT for DEVINFO_INFO */
+#define DEVINFO_INFO_DEVINFOREV_DEFAULT (_DEVINFO_INFO_DEVINFOREV_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_INFO */
+
+/* Bit fields for DEVINFO PART */
+#define _DEVINFO_PART_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_PART */
+#define _DEVINFO_PART_MASK 0x3F3FFFFFUL /**< Mask for DEVINFO_PART */
+#define _DEVINFO_PART_DEVICENUM_SHIFT 0 /**< Shift value for DEVINFO_DEVICENUM */
+#define _DEVINFO_PART_DEVICENUM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_DEVICENUM */
+#define _DEVINFO_PART_DEVICENUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PART */
+#define DEVINFO_PART_DEVICENUM_DEFAULT (_DEVINFO_PART_DEVICENUM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_PART */
+#define _DEVINFO_PART_FAMILYNUM_SHIFT 16 /**< Shift value for DEVINFO_FAMILYNUM */
+#define _DEVINFO_PART_FAMILYNUM_MASK 0x3F0000UL /**< Bit mask for DEVINFO_FAMILYNUM */
+#define _DEVINFO_PART_FAMILYNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PART */
+#define DEVINFO_PART_FAMILYNUM_DEFAULT (_DEVINFO_PART_FAMILYNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_PART */
+#define _DEVINFO_PART_FAMILY_SHIFT 24 /**< Shift value for DEVINFO_FAMILY */
+#define _DEVINFO_PART_FAMILY_MASK 0x3F000000UL /**< Bit mask for DEVINFO_FAMILY */
+#define _DEVINFO_PART_FAMILY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PART */
+#define _DEVINFO_PART_FAMILY_FG 0x00000000UL /**< Mode FG for DEVINFO_PART */
+#define _DEVINFO_PART_FAMILY_MG 0x00000001UL /**< Mode MG for DEVINFO_PART */
+#define _DEVINFO_PART_FAMILY_BG 0x00000002UL /**< Mode BG for DEVINFO_PART */
+#define DEVINFO_PART_FAMILY_DEFAULT (_DEVINFO_PART_FAMILY_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_PART */
+#define DEVINFO_PART_FAMILY_FG (_DEVINFO_PART_FAMILY_FG << 24) /**< Shifted mode FG for DEVINFO_PART */
+#define DEVINFO_PART_FAMILY_MG (_DEVINFO_PART_FAMILY_MG << 24) /**< Shifted mode MG for DEVINFO_PART */
+#define DEVINFO_PART_FAMILY_BG (_DEVINFO_PART_FAMILY_BG << 24) /**< Shifted mode BG for DEVINFO_PART */
+
+/* Bit fields for DEVINFO MEMINFO */
+#define _DEVINFO_MEMINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_MEMINFO */
+#define _DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MEMINFO */
+#define _DEVINFO_MEMINFO_FLASHPAGESIZE_SHIFT 0 /**< Shift value for DEVINFO_FLASHPAGESIZE */
+#define _DEVINFO_MEMINFO_FLASHPAGESIZE_MASK 0xFFUL /**< Bit mask for DEVINFO_FLASHPAGESIZE */
+#define _DEVINFO_MEMINFO_FLASHPAGESIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MEMINFO */
+#define DEVINFO_MEMINFO_FLASHPAGESIZE_DEFAULT (_DEVINFO_MEMINFO_FLASHPAGESIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MEMINFO */
+#define _DEVINFO_MEMINFO_UDPAGESIZE_SHIFT 8 /**< Shift value for DEVINFO_UDPAGESIZE */
+#define _DEVINFO_MEMINFO_UDPAGESIZE_MASK 0xFF00UL /**< Bit mask for DEVINFO_UDPAGESIZE */
+#define _DEVINFO_MEMINFO_UDPAGESIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MEMINFO */
+#define DEVINFO_MEMINFO_UDPAGESIZE_DEFAULT (_DEVINFO_MEMINFO_UDPAGESIZE_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MEMINFO */
+#define _DEVINFO_MEMINFO_DILEN_SHIFT 16 /**< Shift value for DEVINFO_DILEN */
+#define _DEVINFO_MEMINFO_DILEN_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_DILEN */
+#define _DEVINFO_MEMINFO_DILEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MEMINFO */
+#define DEVINFO_MEMINFO_DILEN_DEFAULT (_DEVINFO_MEMINFO_DILEN_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MEMINFO */
+
+/* Bit fields for DEVINFO MSIZE */
+#define _DEVINFO_MSIZE_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_MSIZE */
+#define _DEVINFO_MSIZE_MASK 0x07FFFFFFUL /**< Mask for DEVINFO_MSIZE */
+#define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Shift value for DEVINFO_FLASH */
+#define _DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL /**< Bit mask for DEVINFO_FLASH */
+#define _DEVINFO_MSIZE_FLASH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MSIZE */
+#define DEVINFO_MSIZE_FLASH_DEFAULT (_DEVINFO_MSIZE_FLASH_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MSIZE */
+#define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Shift value for DEVINFO_SRAM */
+#define _DEVINFO_MSIZE_SRAM_MASK 0x7FF0000UL /**< Bit mask for DEVINFO_SRAM */
+#define _DEVINFO_MSIZE_SRAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MSIZE */
+#define DEVINFO_MSIZE_SRAM_DEFAULT (_DEVINFO_MSIZE_SRAM_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MSIZE */
+
+/* Bit fields for DEVINFO PKGINFO */
+#define _DEVINFO_PKGINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_PKGINFO */
+#define _DEVINFO_PKGINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_PKGINFO */
+#define _DEVINFO_PKGINFO_TEMPGRADE_SHIFT 0 /**< Shift value for DEVINFO_TEMPGRADE */
+#define _DEVINFO_PKGINFO_TEMPGRADE_MASK 0xFFUL /**< Bit mask for DEVINFO_TEMPGRADE */
+#define _DEVINFO_PKGINFO_TEMPGRADE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PKGINFO */
+#define _DEVINFO_PKGINFO_TEMPGRADE_N40TO85 0x00000000UL /**< Mode N40TO85 for DEVINFO_PKGINFO */
+#define _DEVINFO_PKGINFO_TEMPGRADE_N40TO125 0x00000001UL /**< Mode N40TO125 for DEVINFO_PKGINFO */
+#define _DEVINFO_PKGINFO_TEMPGRADE_N40TO105 0x00000002UL /**< Mode N40TO105 for DEVINFO_PKGINFO */
+#define _DEVINFO_PKGINFO_TEMPGRADE_N0TO70 0x00000003UL /**< Mode N0TO70 for DEVINFO_PKGINFO */
+#define DEVINFO_PKGINFO_TEMPGRADE_DEFAULT (_DEVINFO_PKGINFO_TEMPGRADE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_PKGINFO */
+#define DEVINFO_PKGINFO_TEMPGRADE_N40TO85 (_DEVINFO_PKGINFO_TEMPGRADE_N40TO85 << 0) /**< Shifted mode N40TO85 for DEVINFO_PKGINFO */
+#define DEVINFO_PKGINFO_TEMPGRADE_N40TO125 (_DEVINFO_PKGINFO_TEMPGRADE_N40TO125 << 0) /**< Shifted mode N40TO125 for DEVINFO_PKGINFO */
+#define DEVINFO_PKGINFO_TEMPGRADE_N40TO105 (_DEVINFO_PKGINFO_TEMPGRADE_N40TO105 << 0) /**< Shifted mode N40TO105 for DEVINFO_PKGINFO */
+#define DEVINFO_PKGINFO_TEMPGRADE_N0TO70 (_DEVINFO_PKGINFO_TEMPGRADE_N0TO70 << 0) /**< Shifted mode N0TO70 for DEVINFO_PKGINFO */
+#define _DEVINFO_PKGINFO_PKGTYPE_SHIFT 8 /**< Shift value for DEVINFO_PKGTYPE */
+#define _DEVINFO_PKGINFO_PKGTYPE_MASK 0xFF00UL /**< Bit mask for DEVINFO_PKGTYPE */
+#define _DEVINFO_PKGINFO_PKGTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PKGINFO */
+#define _DEVINFO_PKGINFO_PKGTYPE_WLCSP 0x0000004AUL /**< Mode WLCSP for DEVINFO_PKGINFO */
+#define _DEVINFO_PKGINFO_PKGTYPE_BGA 0x0000004CUL /**< Mode BGA for DEVINFO_PKGINFO */
+#define _DEVINFO_PKGINFO_PKGTYPE_QFN 0x0000004DUL /**< Mode QFN for DEVINFO_PKGINFO */
+#define _DEVINFO_PKGINFO_PKGTYPE_QFP 0x00000051UL /**< Mode QFP for DEVINFO_PKGINFO */
+#define DEVINFO_PKGINFO_PKGTYPE_DEFAULT (_DEVINFO_PKGINFO_PKGTYPE_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_PKGINFO */
+#define DEVINFO_PKGINFO_PKGTYPE_WLCSP (_DEVINFO_PKGINFO_PKGTYPE_WLCSP << 8) /**< Shifted mode WLCSP for DEVINFO_PKGINFO */
+#define DEVINFO_PKGINFO_PKGTYPE_BGA (_DEVINFO_PKGINFO_PKGTYPE_BGA << 8) /**< Shifted mode BGA for DEVINFO_PKGINFO */
+#define DEVINFO_PKGINFO_PKGTYPE_QFN (_DEVINFO_PKGINFO_PKGTYPE_QFN << 8) /**< Shifted mode QFN for DEVINFO_PKGINFO */
+#define DEVINFO_PKGINFO_PKGTYPE_QFP (_DEVINFO_PKGINFO_PKGTYPE_QFP << 8) /**< Shifted mode QFP for DEVINFO_PKGINFO */
+#define _DEVINFO_PKGINFO_PINCOUNT_SHIFT 16 /**< Shift value for DEVINFO_PINCOUNT */
+#define _DEVINFO_PKGINFO_PINCOUNT_MASK 0xFF0000UL /**< Bit mask for DEVINFO_PINCOUNT */
+#define _DEVINFO_PKGINFO_PINCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PKGINFO */
+#define DEVINFO_PKGINFO_PINCOUNT_DEFAULT (_DEVINFO_PKGINFO_PINCOUNT_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_PKGINFO */
+
+/* Bit fields for DEVINFO CUSTOMINFO */
+#define _DEVINFO_CUSTOMINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_CUSTOMINFO */
+#define _DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL /**< Mask for DEVINFO_CUSTOMINFO */
+#define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16 /**< Shift value for DEVINFO_PARTNO */
+#define _DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_PARTNO */
+#define _DEVINFO_CUSTOMINFO_PARTNO_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CUSTOMINFO */
+#define DEVINFO_CUSTOMINFO_PARTNO_DEFAULT (_DEVINFO_CUSTOMINFO_PARTNO_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_CUSTOMINFO */
+
+/* Bit fields for DEVINFO SWFIX */
+#define _DEVINFO_SWFIX_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_SWFIX */
+#define _DEVINFO_SWFIX_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_SWFIX */
+#define _DEVINFO_SWFIX_RSV_SHIFT 0 /**< Shift value for DEVINFO_RSV */
+#define _DEVINFO_SWFIX_RSV_MASK 0xFFFFFFFFUL /**< Bit mask for DEVINFO_RSV */
+#define _DEVINFO_SWFIX_RSV_DEFAULT 0xFFFFFFFFUL /**< Mode DEFAULT for DEVINFO_SWFIX */
+#define DEVINFO_SWFIX_RSV_DEFAULT (_DEVINFO_SWFIX_RSV_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_SWFIX */
+
+/* Bit fields for DEVINFO SWCAPA0 */
+#define _DEVINFO_SWCAPA0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_MASK 0x07333333UL /**< Mask for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_ZIGBEE_SHIFT 0 /**< Shift value for DEVINFO_ZIGBEE */
+#define _DEVINFO_SWCAPA0_ZIGBEE_MASK 0x3UL /**< Bit mask for DEVINFO_ZIGBEE */
+#define _DEVINFO_SWCAPA0_ZIGBEE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_ZIGBEE_DEFAULT (_DEVINFO_SWCAPA0_ZIGBEE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL0 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL0 << 0) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL1 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL1 << 0) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL2 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL2 << 0) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL3 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL3 << 0) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_THREAD_SHIFT 4 /**< Shift value for DEVINFO_THREAD */
+#define _DEVINFO_SWCAPA0_THREAD_MASK 0x30UL /**< Bit mask for DEVINFO_THREAD */
+#define _DEVINFO_SWCAPA0_THREAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_THREAD_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_THREAD_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_THREAD_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_THREAD_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_THREAD_DEFAULT (_DEVINFO_SWCAPA0_THREAD_DEFAULT << 4) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_THREAD_LEVEL0 (_DEVINFO_SWCAPA0_THREAD_LEVEL0 << 4) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_THREAD_LEVEL1 (_DEVINFO_SWCAPA0_THREAD_LEVEL1 << 4) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_THREAD_LEVEL2 (_DEVINFO_SWCAPA0_THREAD_LEVEL2 << 4) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_THREAD_LEVEL3 (_DEVINFO_SWCAPA0_THREAD_LEVEL3 << 4) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_RF4CE_SHIFT 8 /**< Shift value for DEVINFO_RF4CE */
+#define _DEVINFO_SWCAPA0_RF4CE_MASK 0x300UL /**< Bit mask for DEVINFO_RF4CE */
+#define _DEVINFO_SWCAPA0_RF4CE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_RF4CE_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_RF4CE_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_RF4CE_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_RF4CE_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_RF4CE_DEFAULT (_DEVINFO_SWCAPA0_RF4CE_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_RF4CE_LEVEL0 (_DEVINFO_SWCAPA0_RF4CE_LEVEL0 << 8) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_RF4CE_LEVEL1 (_DEVINFO_SWCAPA0_RF4CE_LEVEL1 << 8) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_RF4CE_LEVEL2 (_DEVINFO_SWCAPA0_RF4CE_LEVEL2 << 8) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_RF4CE_LEVEL3 (_DEVINFO_SWCAPA0_RF4CE_LEVEL3 << 8) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_BTSMART_SHIFT 12 /**< Shift value for DEVINFO_BTSMART */
+#define _DEVINFO_SWCAPA0_BTSMART_MASK 0x3000UL /**< Bit mask for DEVINFO_BTSMART */
+#define _DEVINFO_SWCAPA0_BTSMART_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_BTSMART_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_BTSMART_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_BTSMART_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_BTSMART_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_BTSMART_DEFAULT (_DEVINFO_SWCAPA0_BTSMART_DEFAULT << 12) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_BTSMART_LEVEL0 (_DEVINFO_SWCAPA0_BTSMART_LEVEL0 << 12) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_BTSMART_LEVEL1 (_DEVINFO_SWCAPA0_BTSMART_LEVEL1 << 12) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_BTSMART_LEVEL2 (_DEVINFO_SWCAPA0_BTSMART_LEVEL2 << 12) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_BTSMART_LEVEL3 (_DEVINFO_SWCAPA0_BTSMART_LEVEL3 << 12) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_CONNECT_SHIFT 16 /**< Shift value for DEVINFO_CONNECT */
+#define _DEVINFO_SWCAPA0_CONNECT_MASK 0x30000UL /**< Bit mask for DEVINFO_CONNECT */
+#define _DEVINFO_SWCAPA0_CONNECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_CONNECT_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_CONNECT_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_CONNECT_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_CONNECT_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_CONNECT_DEFAULT (_DEVINFO_SWCAPA0_CONNECT_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_CONNECT_LEVEL0 (_DEVINFO_SWCAPA0_CONNECT_LEVEL0 << 16) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_CONNECT_LEVEL1 (_DEVINFO_SWCAPA0_CONNECT_LEVEL1 << 16) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_CONNECT_LEVEL2 (_DEVINFO_SWCAPA0_CONNECT_LEVEL2 << 16) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_CONNECT_LEVEL3 (_DEVINFO_SWCAPA0_CONNECT_LEVEL3 << 16) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_SRI_SHIFT 20 /**< Shift value for DEVINFO_SRI */
+#define _DEVINFO_SWCAPA0_SRI_MASK 0x300000UL /**< Bit mask for DEVINFO_SRI */
+#define _DEVINFO_SWCAPA0_SRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_SRI_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_SRI_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_SRI_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_SRI_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_SRI_DEFAULT (_DEVINFO_SWCAPA0_SRI_DEFAULT << 20) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_SRI_LEVEL0 (_DEVINFO_SWCAPA0_SRI_LEVEL0 << 20) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_SRI_LEVEL1 (_DEVINFO_SWCAPA0_SRI_LEVEL1 << 20) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_SRI_LEVEL2 (_DEVINFO_SWCAPA0_SRI_LEVEL2 << 20) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_SRI_LEVEL3 (_DEVINFO_SWCAPA0_SRI_LEVEL3 << 20) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_ZWAVE_SHIFT 24 /**< Shift value for DEVINFO_ZWAVE */
+#define _DEVINFO_SWCAPA0_ZWAVE_MASK 0x7000000UL /**< Bit mask for DEVINFO_ZWAVE */
+#define _DEVINFO_SWCAPA0_ZWAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_ZWAVE_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_ZWAVE_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_ZWAVE_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_ZWAVE_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */
+#define _DEVINFO_SWCAPA0_ZWAVE_LEVEL4 0x00000004UL /**< Mode LEVEL4 for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_ZWAVE_DEFAULT (_DEVINFO_SWCAPA0_ZWAVE_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_ZWAVE_LEVEL0 (_DEVINFO_SWCAPA0_ZWAVE_LEVEL0 << 24) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_ZWAVE_LEVEL1 (_DEVINFO_SWCAPA0_ZWAVE_LEVEL1 << 24) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_ZWAVE_LEVEL2 (_DEVINFO_SWCAPA0_ZWAVE_LEVEL2 << 24) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_ZWAVE_LEVEL3 (_DEVINFO_SWCAPA0_ZWAVE_LEVEL3 << 24) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */
+#define DEVINFO_SWCAPA0_ZWAVE_LEVEL4 (_DEVINFO_SWCAPA0_ZWAVE_LEVEL4 << 24) /**< Shifted mode LEVEL4 for DEVINFO_SWCAPA0 */
+
+/* Bit fields for DEVINFO SWCAPA1 */
+#define _DEVINFO_SWCAPA1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_SWCAPA1 */
+#define _DEVINFO_SWCAPA1_MASK 0x0000001FUL /**< Mask for DEVINFO_SWCAPA1 */
+#define DEVINFO_SWCAPA1_RFMCUEN (0x1UL << 0) /**< RF-MCU */
+#define _DEVINFO_SWCAPA1_RFMCUEN_SHIFT 0 /**< Shift value for DEVINFO_RFMCUEN */
+#define _DEVINFO_SWCAPA1_RFMCUEN_MASK 0x1UL /**< Bit mask for DEVINFO_RFMCUEN */
+#define _DEVINFO_SWCAPA1_RFMCUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */
+#define DEVINFO_SWCAPA1_RFMCUEN_DEFAULT (_DEVINFO_SWCAPA1_RFMCUEN_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */
+#define DEVINFO_SWCAPA1_NCPEN (0x1UL << 1) /**< NCP */
+#define _DEVINFO_SWCAPA1_NCPEN_SHIFT 1 /**< Shift value for DEVINFO_NCPEN */
+#define _DEVINFO_SWCAPA1_NCPEN_MASK 0x2UL /**< Bit mask for DEVINFO_NCPEN */
+#define _DEVINFO_SWCAPA1_NCPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */
+#define DEVINFO_SWCAPA1_NCPEN_DEFAULT (_DEVINFO_SWCAPA1_NCPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */
+#define DEVINFO_SWCAPA1_GWEN (0x1UL << 2) /**< Gateway */
+#define _DEVINFO_SWCAPA1_GWEN_SHIFT 2 /**< Shift value for DEVINFO_GWEN */
+#define _DEVINFO_SWCAPA1_GWEN_MASK 0x4UL /**< Bit mask for DEVINFO_GWEN */
+#define _DEVINFO_SWCAPA1_GWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */
+#define DEVINFO_SWCAPA1_GWEN_DEFAULT (_DEVINFO_SWCAPA1_GWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */
+#define DEVINFO_SWCAPA1_XOUT (0x1UL << 3) /**< XOUT */
+#define _DEVINFO_SWCAPA1_XOUT_SHIFT 3 /**< Shift value for DEVINFO_XOUT */
+#define _DEVINFO_SWCAPA1_XOUT_MASK 0x8UL /**< Bit mask for DEVINFO_XOUT */
+#define _DEVINFO_SWCAPA1_XOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */
+#define DEVINFO_SWCAPA1_XOUT_DEFAULT (_DEVINFO_SWCAPA1_XOUT_DEFAULT << 3) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */
+#define DEVINFO_SWCAPA1_FENOTCH (0x1UL << 4) /**< FENOTCH */
+#define _DEVINFO_SWCAPA1_FENOTCH_SHIFT 4 /**< Shift value for DEVINFO_FENOTCH */
+#define _DEVINFO_SWCAPA1_FENOTCH_MASK 0x10UL /**< Bit mask for DEVINFO_FENOTCH */
+#define _DEVINFO_SWCAPA1_FENOTCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */
+#define DEVINFO_SWCAPA1_FENOTCH_DEFAULT (_DEVINFO_SWCAPA1_FENOTCH_DEFAULT << 4) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */
+
+/* Bit fields for DEVINFO EXTINFO */
+#define _DEVINFO_EXTINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EXTINFO */
+#define _DEVINFO_EXTINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_EXTINFO */
+#define _DEVINFO_EXTINFO_TYPE_SHIFT 0 /**< Shift value for DEVINFO_TYPE */
+#define _DEVINFO_EXTINFO_TYPE_MASK 0xFFUL /**< Bit mask for DEVINFO_TYPE */
+#define _DEVINFO_EXTINFO_TYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EXTINFO */
+#define _DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */
+#define DEVINFO_EXTINFO_TYPE_DEFAULT (_DEVINFO_EXTINFO_TYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EXTINFO */
+#define DEVINFO_EXTINFO_TYPE_NONE (_DEVINFO_EXTINFO_TYPE_NONE << 0) /**< Shifted mode NONE for DEVINFO_EXTINFO */
+#define _DEVINFO_EXTINFO_CONNECTION_SHIFT 8 /**< Shift value for DEVINFO_CONNECTION */
+#define _DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL /**< Bit mask for DEVINFO_CONNECTION */
+#define _DEVINFO_EXTINFO_CONNECTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EXTINFO */
+#define _DEVINFO_EXTINFO_CONNECTION_SPI 0x00000000UL /**< Mode SPI for DEVINFO_EXTINFO */
+#define _DEVINFO_EXTINFO_CONNECTION_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */
+#define DEVINFO_EXTINFO_CONNECTION_DEFAULT (_DEVINFO_EXTINFO_CONNECTION_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_EXTINFO */
+#define DEVINFO_EXTINFO_CONNECTION_SPI (_DEVINFO_EXTINFO_CONNECTION_SPI << 8) /**< Shifted mode SPI for DEVINFO_EXTINFO */
+#define DEVINFO_EXTINFO_CONNECTION_NONE (_DEVINFO_EXTINFO_CONNECTION_NONE << 8) /**< Shifted mode NONE for DEVINFO_EXTINFO */
+#define _DEVINFO_EXTINFO_REV_SHIFT 16 /**< Shift value for DEVINFO_REV */
+#define _DEVINFO_EXTINFO_REV_MASK 0xFF0000UL /**< Bit mask for DEVINFO_REV */
+#define _DEVINFO_EXTINFO_REV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EXTINFO */
+#define DEVINFO_EXTINFO_REV_DEFAULT (_DEVINFO_EXTINFO_REV_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_EXTINFO */
+
+/* Bit fields for DEVINFO EUI48L */
+#define _DEVINFO_EUI48L_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EUI48L */
+#define _DEVINFO_EUI48L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48L */
+#define _DEVINFO_EUI48L_UNIQUEID_SHIFT 0 /**< Shift value for DEVINFO_UNIQUEID */
+#define _DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL /**< Bit mask for DEVINFO_UNIQUEID */
+#define _DEVINFO_EUI48L_UNIQUEID_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI48L */
+#define DEVINFO_EUI48L_UNIQUEID_DEFAULT (_DEVINFO_EUI48L_UNIQUEID_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI48L */
+#define _DEVINFO_EUI48L_OUI48L_SHIFT 24 /**< Shift value for DEVINFO_OUI48L */
+#define _DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL /**< Bit mask for DEVINFO_OUI48L */
+#define _DEVINFO_EUI48L_OUI48L_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI48L */
+#define DEVINFO_EUI48L_OUI48L_DEFAULT (_DEVINFO_EUI48L_OUI48L_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_EUI48L */
+
+/* Bit fields for DEVINFO EUI48H */
+#define _DEVINFO_EUI48H_RESETVALUE 0xFFFF0000UL /**< Default value for DEVINFO_EUI48H */
+#define _DEVINFO_EUI48H_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48H */
+#define _DEVINFO_EUI48H_OUI48H_SHIFT 0 /**< Shift value for DEVINFO_OUI48H */
+#define _DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OUI48H */
+#define _DEVINFO_EUI48H_OUI48H_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI48H */
+#define DEVINFO_EUI48H_OUI48H_DEFAULT (_DEVINFO_EUI48H_OUI48H_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI48H */
+#define _DEVINFO_EUI48H_RESERVED_SHIFT 16 /**< Shift value for DEVINFO_RESERVED */
+#define _DEVINFO_EUI48H_RESERVED_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_RESERVED */
+#define _DEVINFO_EUI48H_RESERVED_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for DEVINFO_EUI48H */
+#define DEVINFO_EUI48H_RESERVED_DEFAULT (_DEVINFO_EUI48H_RESERVED_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_EUI48H */
+
+/* Bit fields for DEVINFO EUI64L */
+#define _DEVINFO_EUI64L_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EUI64L */
+#define _DEVINFO_EUI64L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI64L */
+#define _DEVINFO_EUI64L_UNIQUEL_SHIFT 0 /**< Shift value for DEVINFO_UNIQUEL */
+#define _DEVINFO_EUI64L_UNIQUEL_MASK 0xFFFFFFFFUL /**< Bit mask for DEVINFO_UNIQUEL */
+#define _DEVINFO_EUI64L_UNIQUEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI64L */
+#define DEVINFO_EUI64L_UNIQUEL_DEFAULT (_DEVINFO_EUI64L_UNIQUEL_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI64L */
+
+/* Bit fields for DEVINFO EUI64H */
+#define _DEVINFO_EUI64H_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EUI64H */
+#define _DEVINFO_EUI64H_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI64H */
+#define _DEVINFO_EUI64H_UNIQUEH_SHIFT 0 /**< Shift value for DEVINFO_UNIQUEH */
+#define _DEVINFO_EUI64H_UNIQUEH_MASK 0xFFUL /**< Bit mask for DEVINFO_UNIQUEH */
+#define _DEVINFO_EUI64H_UNIQUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI64H */
+#define DEVINFO_EUI64H_UNIQUEH_DEFAULT (_DEVINFO_EUI64H_UNIQUEH_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI64H */
+#define _DEVINFO_EUI64H_OUI64_SHIFT 8 /**< Shift value for DEVINFO_OUI64 */
+#define _DEVINFO_EUI64H_OUI64_MASK 0xFFFFFF00UL /**< Bit mask for DEVINFO_OUI64 */
+#define _DEVINFO_EUI64H_OUI64_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI64H */
+#define DEVINFO_EUI64H_OUI64_DEFAULT (_DEVINFO_EUI64H_OUI64_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_EUI64H */
+
+/* Bit fields for DEVINFO CALTEMP */
+#define _DEVINFO_CALTEMP_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_CALTEMP */
+#define _DEVINFO_CALTEMP_MASK 0x000000FFUL /**< Mask for DEVINFO_CALTEMP */
+#define _DEVINFO_CALTEMP_TEMP_SHIFT 0 /**< Shift value for DEVINFO_TEMP */
+#define _DEVINFO_CALTEMP_TEMP_MASK 0xFFUL /**< Bit mask for DEVINFO_TEMP */
+#define _DEVINFO_CALTEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CALTEMP */
+#define DEVINFO_CALTEMP_TEMP_DEFAULT (_DEVINFO_CALTEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_CALTEMP */
+
+/* Bit fields for DEVINFO EMUTEMP */
+#define _DEVINFO_EMUTEMP_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EMUTEMP */
+#define _DEVINFO_EMUTEMP_MASK 0x1FFF07FCUL /**< Mask for DEVINFO_EMUTEMP */
+#define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 2 /**< Shift value for DEVINFO_EMUTEMPROOM */
+#define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0x7FCUL /**< Bit mask for DEVINFO_EMUTEMPROOM */
+#define _DEVINFO_EMUTEMP_EMUTEMPROOM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EMUTEMP */
+#define DEVINFO_EMUTEMP_EMUTEMPROOM_DEFAULT (_DEVINFO_EMUTEMP_EMUTEMPROOM_DEFAULT << 2) /**< Shifted mode DEFAULT for DEVINFO_EMUTEMP */
+
+/* Bit fields for DEVINFO HFRCODPLLCAL */
+#define _DEVINFO_HFRCODPLLCAL_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_HFRCODPLLCAL */
+#define _DEVINFO_HFRCODPLLCAL_MASK 0xFFFFBF7FUL /**< Mask for DEVINFO_HFRCODPLLCAL */
+#define _DEVINFO_HFRCODPLLCAL_TUNING_SHIFT 0 /**< Shift value for DEVINFO_TUNING */
+#define _DEVINFO_HFRCODPLLCAL_TUNING_MASK 0x7FUL /**< Bit mask for DEVINFO_TUNING */
+#define _DEVINFO_HFRCODPLLCAL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */
+#define DEVINFO_HFRCODPLLCAL_TUNING_DEFAULT (_DEVINFO_HFRCODPLLCAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/
+#define _DEVINFO_HFRCODPLLCAL_FINETUNING_SHIFT 8 /**< Shift value for DEVINFO_FINETUNING */
+#define _DEVINFO_HFRCODPLLCAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for DEVINFO_FINETUNING */
+#define _DEVINFO_HFRCODPLLCAL_FINETUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */
+#define DEVINFO_HFRCODPLLCAL_FINETUNING_DEFAULT (_DEVINFO_HFRCODPLLCAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/
+#define DEVINFO_HFRCODPLLCAL_LDOHP (0x1UL << 15) /**< */
+#define _DEVINFO_HFRCODPLLCAL_LDOHP_SHIFT 15 /**< Shift value for DEVINFO_LDOHP */
+#define _DEVINFO_HFRCODPLLCAL_LDOHP_MASK 0x8000UL /**< Bit mask for DEVINFO_LDOHP */
+#define _DEVINFO_HFRCODPLLCAL_LDOHP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */
+#define DEVINFO_HFRCODPLLCAL_LDOHP_DEFAULT (_DEVINFO_HFRCODPLLCAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/
+#define _DEVINFO_HFRCODPLLCAL_FREQRANGE_SHIFT 16 /**< Shift value for DEVINFO_FREQRANGE */
+#define _DEVINFO_HFRCODPLLCAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for DEVINFO_FREQRANGE */
+#define _DEVINFO_HFRCODPLLCAL_FREQRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */
+#define DEVINFO_HFRCODPLLCAL_FREQRANGE_DEFAULT (_DEVINFO_HFRCODPLLCAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/
+#define _DEVINFO_HFRCODPLLCAL_CMPBIAS_SHIFT 21 /**< Shift value for DEVINFO_CMPBIAS */
+#define _DEVINFO_HFRCODPLLCAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for DEVINFO_CMPBIAS */
+#define _DEVINFO_HFRCODPLLCAL_CMPBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */
+#define DEVINFO_HFRCODPLLCAL_CMPBIAS_DEFAULT (_DEVINFO_HFRCODPLLCAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/
+#define _DEVINFO_HFRCODPLLCAL_CLKDIV_SHIFT 24 /**< Shift value for DEVINFO_CLKDIV */
+#define _DEVINFO_HFRCODPLLCAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for DEVINFO_CLKDIV */
+#define _DEVINFO_HFRCODPLLCAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */
+#define DEVINFO_HFRCODPLLCAL_CLKDIV_DEFAULT (_DEVINFO_HFRCODPLLCAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/
+#define _DEVINFO_HFRCODPLLCAL_CMPSEL_SHIFT 26 /**< Shift value for DEVINFO_CMPSEL */
+#define _DEVINFO_HFRCODPLLCAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for DEVINFO_CMPSEL */
+#define _DEVINFO_HFRCODPLLCAL_CMPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */
+#define DEVINFO_HFRCODPLLCAL_CMPSEL_DEFAULT (_DEVINFO_HFRCODPLLCAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/
+#define _DEVINFO_HFRCODPLLCAL_IREFTC_SHIFT 28 /**< Shift value for DEVINFO_IREFTC */
+#define _DEVINFO_HFRCODPLLCAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for DEVINFO_IREFTC */
+#define _DEVINFO_HFRCODPLLCAL_IREFTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */
+#define DEVINFO_HFRCODPLLCAL_IREFTC_DEFAULT (_DEVINFO_HFRCODPLLCAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/
+
+/* Bit fields for DEVINFO HFRCOEM23CAL */
+#define _DEVINFO_HFRCOEM23CAL_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_HFRCOEM23CAL */
+#define _DEVINFO_HFRCOEM23CAL_MASK 0xFFFFBF7FUL /**< Mask for DEVINFO_HFRCOEM23CAL */
+#define _DEVINFO_HFRCOEM23CAL_TUNING_SHIFT 0 /**< Shift value for DEVINFO_TUNING */
+#define _DEVINFO_HFRCOEM23CAL_TUNING_MASK 0x7FUL /**< Bit mask for DEVINFO_TUNING */
+#define _DEVINFO_HFRCOEM23CAL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */
+#define DEVINFO_HFRCOEM23CAL_TUNING_DEFAULT (_DEVINFO_HFRCOEM23CAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/
+#define _DEVINFO_HFRCOEM23CAL_FINETUNING_SHIFT 8 /**< Shift value for DEVINFO_FINETUNING */
+#define _DEVINFO_HFRCOEM23CAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for DEVINFO_FINETUNING */
+#define _DEVINFO_HFRCOEM23CAL_FINETUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */
+#define DEVINFO_HFRCOEM23CAL_FINETUNING_DEFAULT (_DEVINFO_HFRCOEM23CAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/
+#define DEVINFO_HFRCOEM23CAL_LDOHP (0x1UL << 15) /**< */
+#define _DEVINFO_HFRCOEM23CAL_LDOHP_SHIFT 15 /**< Shift value for DEVINFO_LDOHP */
+#define _DEVINFO_HFRCOEM23CAL_LDOHP_MASK 0x8000UL /**< Bit mask for DEVINFO_LDOHP */
+#define _DEVINFO_HFRCOEM23CAL_LDOHP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */
+#define DEVINFO_HFRCOEM23CAL_LDOHP_DEFAULT (_DEVINFO_HFRCOEM23CAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/
+#define _DEVINFO_HFRCOEM23CAL_FREQRANGE_SHIFT 16 /**< Shift value for DEVINFO_FREQRANGE */
+#define _DEVINFO_HFRCOEM23CAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for DEVINFO_FREQRANGE */
+#define _DEVINFO_HFRCOEM23CAL_FREQRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */
+#define DEVINFO_HFRCOEM23CAL_FREQRANGE_DEFAULT (_DEVINFO_HFRCOEM23CAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/
+#define _DEVINFO_HFRCOEM23CAL_CMPBIAS_SHIFT 21 /**< Shift value for DEVINFO_CMPBIAS */
+#define _DEVINFO_HFRCOEM23CAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for DEVINFO_CMPBIAS */
+#define _DEVINFO_HFRCOEM23CAL_CMPBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */
+#define DEVINFO_HFRCOEM23CAL_CMPBIAS_DEFAULT (_DEVINFO_HFRCOEM23CAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/
+#define _DEVINFO_HFRCOEM23CAL_CLKDIV_SHIFT 24 /**< Shift value for DEVINFO_CLKDIV */
+#define _DEVINFO_HFRCOEM23CAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for DEVINFO_CLKDIV */
+#define _DEVINFO_HFRCOEM23CAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */
+#define DEVINFO_HFRCOEM23CAL_CLKDIV_DEFAULT (_DEVINFO_HFRCOEM23CAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/
+#define _DEVINFO_HFRCOEM23CAL_CMPSEL_SHIFT 26 /**< Shift value for DEVINFO_CMPSEL */
+#define _DEVINFO_HFRCOEM23CAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for DEVINFO_CMPSEL */
+#define _DEVINFO_HFRCOEM23CAL_CMPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */
+#define DEVINFO_HFRCOEM23CAL_CMPSEL_DEFAULT (_DEVINFO_HFRCOEM23CAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/
+#define _DEVINFO_HFRCOEM23CAL_IREFTC_SHIFT 28 /**< Shift value for DEVINFO_IREFTC */
+#define _DEVINFO_HFRCOEM23CAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for DEVINFO_IREFTC */
+#define _DEVINFO_HFRCOEM23CAL_IREFTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */
+#define DEVINFO_HFRCOEM23CAL_IREFTC_DEFAULT (_DEVINFO_HFRCOEM23CAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/
+
+/* Bit fields for DEVINFO MODULENAME0 */
+#define _DEVINFO_MODULENAME0_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME0 */
+#define _DEVINFO_MODULENAME0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME0 */
+#define _DEVINFO_MODULENAME0_MODCHAR1_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR1 */
+#define _DEVINFO_MODULENAME0_MODCHAR1_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR1 */
+#define _DEVINFO_MODULENAME0_MODCHAR1_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */
+#define DEVINFO_MODULENAME0_MODCHAR1_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR1_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/
+#define _DEVINFO_MODULENAME0_MODCHAR2_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR2 */
+#define _DEVINFO_MODULENAME0_MODCHAR2_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR2 */
+#define _DEVINFO_MODULENAME0_MODCHAR2_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */
+#define DEVINFO_MODULENAME0_MODCHAR2_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR2_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/
+#define _DEVINFO_MODULENAME0_MODCHAR3_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR3 */
+#define _DEVINFO_MODULENAME0_MODCHAR3_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR3 */
+#define _DEVINFO_MODULENAME0_MODCHAR3_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */
+#define DEVINFO_MODULENAME0_MODCHAR3_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR3_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/
+#define _DEVINFO_MODULENAME0_MODCHAR4_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR4 */
+#define _DEVINFO_MODULENAME0_MODCHAR4_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR4 */
+#define _DEVINFO_MODULENAME0_MODCHAR4_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */
+#define DEVINFO_MODULENAME0_MODCHAR4_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR4_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/
+
+/* Bit fields for DEVINFO MODULENAME1 */
+#define _DEVINFO_MODULENAME1_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME1 */
+#define _DEVINFO_MODULENAME1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME1 */
+#define _DEVINFO_MODULENAME1_MODCHAR5_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR5 */
+#define _DEVINFO_MODULENAME1_MODCHAR5_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR5 */
+#define _DEVINFO_MODULENAME1_MODCHAR5_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */
+#define DEVINFO_MODULENAME1_MODCHAR5_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR5_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/
+#define _DEVINFO_MODULENAME1_MODCHAR6_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR6 */
+#define _DEVINFO_MODULENAME1_MODCHAR6_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR6 */
+#define _DEVINFO_MODULENAME1_MODCHAR6_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */
+#define DEVINFO_MODULENAME1_MODCHAR6_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR6_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/
+#define _DEVINFO_MODULENAME1_MODCHAR7_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR7 */
+#define _DEVINFO_MODULENAME1_MODCHAR7_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR7 */
+#define _DEVINFO_MODULENAME1_MODCHAR7_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */
+#define DEVINFO_MODULENAME1_MODCHAR7_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR7_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/
+#define _DEVINFO_MODULENAME1_MODCHAR8_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR8 */
+#define _DEVINFO_MODULENAME1_MODCHAR8_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR8 */
+#define _DEVINFO_MODULENAME1_MODCHAR8_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */
+#define DEVINFO_MODULENAME1_MODCHAR8_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR8_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/
+
+/* Bit fields for DEVINFO MODULENAME2 */
+#define _DEVINFO_MODULENAME2_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME2 */
+#define _DEVINFO_MODULENAME2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME2 */
+#define _DEVINFO_MODULENAME2_MODCHAR9_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR9 */
+#define _DEVINFO_MODULENAME2_MODCHAR9_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR9 */
+#define _DEVINFO_MODULENAME2_MODCHAR9_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */
+#define DEVINFO_MODULENAME2_MODCHAR9_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR9_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/
+#define _DEVINFO_MODULENAME2_MODCHAR10_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR10 */
+#define _DEVINFO_MODULENAME2_MODCHAR10_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR10 */
+#define _DEVINFO_MODULENAME2_MODCHAR10_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */
+#define DEVINFO_MODULENAME2_MODCHAR10_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR10_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/
+#define _DEVINFO_MODULENAME2_MODCHAR11_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR11 */
+#define _DEVINFO_MODULENAME2_MODCHAR11_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR11 */
+#define _DEVINFO_MODULENAME2_MODCHAR11_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */
+#define DEVINFO_MODULENAME2_MODCHAR11_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR11_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/
+#define _DEVINFO_MODULENAME2_MODCHAR12_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR12 */
+#define _DEVINFO_MODULENAME2_MODCHAR12_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR12 */
+#define _DEVINFO_MODULENAME2_MODCHAR12_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */
+#define DEVINFO_MODULENAME2_MODCHAR12_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR12_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/
+
+/* Bit fields for DEVINFO MODULENAME3 */
+#define _DEVINFO_MODULENAME3_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME3 */
+#define _DEVINFO_MODULENAME3_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME3 */
+#define _DEVINFO_MODULENAME3_MODCHAR13_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR13 */
+#define _DEVINFO_MODULENAME3_MODCHAR13_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR13 */
+#define _DEVINFO_MODULENAME3_MODCHAR13_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */
+#define DEVINFO_MODULENAME3_MODCHAR13_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR13_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/
+#define _DEVINFO_MODULENAME3_MODCHAR14_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR14 */
+#define _DEVINFO_MODULENAME3_MODCHAR14_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR14 */
+#define _DEVINFO_MODULENAME3_MODCHAR14_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */
+#define DEVINFO_MODULENAME3_MODCHAR14_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR14_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/
+#define _DEVINFO_MODULENAME3_MODCHAR15_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR15 */
+#define _DEVINFO_MODULENAME3_MODCHAR15_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR15 */
+#define _DEVINFO_MODULENAME3_MODCHAR15_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */
+#define DEVINFO_MODULENAME3_MODCHAR15_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR15_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/
+#define _DEVINFO_MODULENAME3_MODCHAR16_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR16 */
+#define _DEVINFO_MODULENAME3_MODCHAR16_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR16 */
+#define _DEVINFO_MODULENAME3_MODCHAR16_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */
+#define DEVINFO_MODULENAME3_MODCHAR16_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR16_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/
+
+/* Bit fields for DEVINFO MODULENAME4 */
+#define _DEVINFO_MODULENAME4_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME4 */
+#define _DEVINFO_MODULENAME4_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME4 */
+#define _DEVINFO_MODULENAME4_MODCHAR17_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR17 */
+#define _DEVINFO_MODULENAME4_MODCHAR17_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR17 */
+#define _DEVINFO_MODULENAME4_MODCHAR17_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */
+#define DEVINFO_MODULENAME4_MODCHAR17_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR17_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/
+#define _DEVINFO_MODULENAME4_MODCHAR18_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR18 */
+#define _DEVINFO_MODULENAME4_MODCHAR18_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR18 */
+#define _DEVINFO_MODULENAME4_MODCHAR18_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */
+#define DEVINFO_MODULENAME4_MODCHAR18_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR18_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/
+#define _DEVINFO_MODULENAME4_MODCHAR19_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR19 */
+#define _DEVINFO_MODULENAME4_MODCHAR19_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR19 */
+#define _DEVINFO_MODULENAME4_MODCHAR19_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */
+#define DEVINFO_MODULENAME4_MODCHAR19_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR19_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/
+#define _DEVINFO_MODULENAME4_MODCHAR20_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR20 */
+#define _DEVINFO_MODULENAME4_MODCHAR20_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR20 */
+#define _DEVINFO_MODULENAME4_MODCHAR20_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */
+#define DEVINFO_MODULENAME4_MODCHAR20_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR20_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/
+
+/* Bit fields for DEVINFO MODULENAME5 */
+#define _DEVINFO_MODULENAME5_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME5 */
+#define _DEVINFO_MODULENAME5_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME5 */
+#define _DEVINFO_MODULENAME5_MODCHAR21_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR21 */
+#define _DEVINFO_MODULENAME5_MODCHAR21_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR21 */
+#define _DEVINFO_MODULENAME5_MODCHAR21_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */
+#define DEVINFO_MODULENAME5_MODCHAR21_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR21_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/
+#define _DEVINFO_MODULENAME5_MODCHAR22_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR22 */
+#define _DEVINFO_MODULENAME5_MODCHAR22_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR22 */
+#define _DEVINFO_MODULENAME5_MODCHAR22_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */
+#define DEVINFO_MODULENAME5_MODCHAR22_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR22_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/
+#define _DEVINFO_MODULENAME5_MODCHAR23_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR23 */
+#define _DEVINFO_MODULENAME5_MODCHAR23_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR23 */
+#define _DEVINFO_MODULENAME5_MODCHAR23_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */
+#define DEVINFO_MODULENAME5_MODCHAR23_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR23_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/
+#define _DEVINFO_MODULENAME5_MODCHAR24_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR24 */
+#define _DEVINFO_MODULENAME5_MODCHAR24_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR24 */
+#define _DEVINFO_MODULENAME5_MODCHAR24_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */
+#define DEVINFO_MODULENAME5_MODCHAR24_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR24_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/
+
+/* Bit fields for DEVINFO MODULENAME6 */
+#define _DEVINFO_MODULENAME6_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME6 */
+#define _DEVINFO_MODULENAME6_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME6 */
+#define _DEVINFO_MODULENAME6_MODCHAR25_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR25 */
+#define _DEVINFO_MODULENAME6_MODCHAR25_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR25 */
+#define _DEVINFO_MODULENAME6_MODCHAR25_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME6 */
+#define DEVINFO_MODULENAME6_MODCHAR25_DEFAULT (_DEVINFO_MODULENAME6_MODCHAR25_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME6*/
+#define _DEVINFO_MODULENAME6_MODCHAR26_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR26 */
+#define _DEVINFO_MODULENAME6_MODCHAR26_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR26 */
+#define _DEVINFO_MODULENAME6_MODCHAR26_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME6 */
+#define DEVINFO_MODULENAME6_MODCHAR26_DEFAULT (_DEVINFO_MODULENAME6_MODCHAR26_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME6*/
+#define _DEVINFO_MODULENAME6_RSV_SHIFT 16 /**< Shift value for DEVINFO_RSV */
+#define _DEVINFO_MODULENAME6_RSV_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_RSV */
+#define _DEVINFO_MODULENAME6_RSV_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for DEVINFO_MODULENAME6 */
+#define DEVINFO_MODULENAME6_RSV_DEFAULT (_DEVINFO_MODULENAME6_RSV_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME6*/
+
+/* Bit fields for DEVINFO MODULEINFO */
+#define _DEVINFO_MODULEINFO_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_HWREV_SHIFT 0 /**< Shift value for DEVINFO_HWREV */
+#define _DEVINFO_MODULEINFO_HWREV_MASK 0x1FUL /**< Bit mask for DEVINFO_HWREV */
+#define _DEVINFO_MODULEINFO_HWREV_DEFAULT 0x0000001FUL /**< Mode DEFAULT for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_HWREV_DEFAULT (_DEVINFO_MODULEINFO_HWREV_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_ANTENNA_SHIFT 5 /**< Shift value for DEVINFO_ANTENNA */
+#define _DEVINFO_MODULEINFO_ANTENNA_MASK 0xE0UL /**< Bit mask for DEVINFO_ANTENNA */
+#define _DEVINFO_MODULEINFO_ANTENNA_DEFAULT 0x00000007UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_ANTENNA_BUILTIN 0x00000000UL /**< Mode BUILTIN for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_ANTENNA_CONNECTOR 0x00000001UL /**< Mode CONNECTOR for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_ANTENNA_RFPAD 0x00000002UL /**< Mode RFPAD for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_ANTENNA_INVERTEDF 0x00000003UL /**< Mode INVERTEDF for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_ANTENNA_DEFAULT (_DEVINFO_MODULEINFO_ANTENNA_DEFAULT << 5) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_ANTENNA_BUILTIN (_DEVINFO_MODULEINFO_ANTENNA_BUILTIN << 5) /**< Shifted mode BUILTIN for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_ANTENNA_CONNECTOR (_DEVINFO_MODULEINFO_ANTENNA_CONNECTOR << 5) /**< Shifted mode CONNECTOR for DEVINFO_MODULEINFO*/
+#define DEVINFO_MODULEINFO_ANTENNA_RFPAD (_DEVINFO_MODULEINFO_ANTENNA_RFPAD << 5) /**< Shifted mode RFPAD for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_ANTENNA_INVERTEDF (_DEVINFO_MODULEINFO_ANTENNA_INVERTEDF << 5) /**< Shifted mode INVERTEDF for DEVINFO_MODULEINFO*/
+#define _DEVINFO_MODULEINFO_MODNUMBER_SHIFT 8 /**< Shift value for DEVINFO_MODNUMBER */
+#define _DEVINFO_MODULEINFO_MODNUMBER_MASK 0x7F00UL /**< Bit mask for DEVINFO_MODNUMBER */
+#define _DEVINFO_MODULEINFO_MODNUMBER_DEFAULT 0x0000007FUL /**< Mode DEFAULT for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_MODNUMBER_DEFAULT (_DEVINFO_MODULEINFO_MODNUMBER_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_TYPE (0x1UL << 15) /**< */
+#define _DEVINFO_MODULEINFO_TYPE_SHIFT 15 /**< Shift value for DEVINFO_TYPE */
+#define _DEVINFO_MODULEINFO_TYPE_MASK 0x8000UL /**< Bit mask for DEVINFO_TYPE */
+#define _DEVINFO_MODULEINFO_TYPE_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_TYPE_PCB 0x00000000UL /**< Mode PCB for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_TYPE_SIP 0x00000001UL /**< Mode SIP for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_TYPE_DEFAULT (_DEVINFO_MODULEINFO_TYPE_DEFAULT << 15) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_TYPE_PCB (_DEVINFO_MODULEINFO_TYPE_PCB << 15) /**< Shifted mode PCB for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_TYPE_SIP (_DEVINFO_MODULEINFO_TYPE_SIP << 15) /**< Shifted mode SIP for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_LFXO (0x1UL << 16) /**< */
+#define _DEVINFO_MODULEINFO_LFXO_SHIFT 16 /**< Shift value for DEVINFO_LFXO */
+#define _DEVINFO_MODULEINFO_LFXO_MASK 0x10000UL /**< Bit mask for DEVINFO_LFXO */
+#define _DEVINFO_MODULEINFO_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_LFXO_NONE 0x00000000UL /**< Mode NONE for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_LFXO_PRESENT 0x00000001UL /**< Mode PRESENT for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_LFXO_DEFAULT (_DEVINFO_MODULEINFO_LFXO_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_LFXO_NONE (_DEVINFO_MODULEINFO_LFXO_NONE << 16) /**< Shifted mode NONE for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_LFXO_PRESENT (_DEVINFO_MODULEINFO_LFXO_PRESENT << 16) /**< Shifted mode PRESENT for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_EXPRESS (0x1UL << 17) /**< */
+#define _DEVINFO_MODULEINFO_EXPRESS_SHIFT 17 /**< Shift value for DEVINFO_EXPRESS */
+#define _DEVINFO_MODULEINFO_EXPRESS_MASK 0x20000UL /**< Bit mask for DEVINFO_EXPRESS */
+#define _DEVINFO_MODULEINFO_EXPRESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_EXPRESS_SUPPORTED 0x00000000UL /**< Mode SUPPORTED for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_EXPRESS_NONE 0x00000001UL /**< Mode NONE for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_EXPRESS_DEFAULT (_DEVINFO_MODULEINFO_EXPRESS_DEFAULT << 17) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_EXPRESS_SUPPORTED (_DEVINFO_MODULEINFO_EXPRESS_SUPPORTED << 17) /**< Shifted mode SUPPORTED for DEVINFO_MODULEINFO*/
+#define DEVINFO_MODULEINFO_EXPRESS_NONE (_DEVINFO_MODULEINFO_EXPRESS_NONE << 17) /**< Shifted mode NONE for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_LFXOCALVAL (0x1UL << 18) /**< */
+#define _DEVINFO_MODULEINFO_LFXOCALVAL_SHIFT 18 /**< Shift value for DEVINFO_LFXOCALVAL */
+#define _DEVINFO_MODULEINFO_LFXOCALVAL_MASK 0x40000UL /**< Bit mask for DEVINFO_LFXOCALVAL */
+#define _DEVINFO_MODULEINFO_LFXOCALVAL_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_LFXOCALVAL_VALID 0x00000000UL /**< Mode VALID for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID 0x00000001UL /**< Mode NOTVALID for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_LFXOCALVAL_DEFAULT (_DEVINFO_MODULEINFO_LFXOCALVAL_DEFAULT << 18) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_LFXOCALVAL_VALID (_DEVINFO_MODULEINFO_LFXOCALVAL_VALID << 18) /**< Shifted mode VALID for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID (_DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID << 18) /**< Shifted mode NOTVALID for DEVINFO_MODULEINFO*/
+#define DEVINFO_MODULEINFO_HFXOCALVAL (0x1UL << 19) /**< */
+#define _DEVINFO_MODULEINFO_HFXOCALVAL_SHIFT 19 /**< Shift value for DEVINFO_HFXOCALVAL */
+#define _DEVINFO_MODULEINFO_HFXOCALVAL_MASK 0x80000UL /**< Bit mask for DEVINFO_HFXOCALVAL */
+#define _DEVINFO_MODULEINFO_HFXOCALVAL_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_HFXOCALVAL_VALID 0x00000000UL /**< Mode VALID for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID 0x00000001UL /**< Mode NOTVALID for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_HFXOCALVAL_DEFAULT (_DEVINFO_MODULEINFO_HFXOCALVAL_DEFAULT << 19) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_HFXOCALVAL_VALID (_DEVINFO_MODULEINFO_HFXOCALVAL_VALID << 19) /**< Shifted mode VALID for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID (_DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID << 19) /**< Shifted mode NOTVALID for DEVINFO_MODULEINFO*/
+#define _DEVINFO_MODULEINFO_MODNUMBERMSB_SHIFT 20 /**< Shift value for DEVINFO_MODNUMBERMSB */
+#define _DEVINFO_MODULEINFO_MODNUMBERMSB_MASK 0x1FF00000UL /**< Bit mask for DEVINFO_MODNUMBERMSB */
+#define _DEVINFO_MODULEINFO_MODNUMBERMSB_DEFAULT 0x000001FFUL /**< Mode DEFAULT for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_MODNUMBERMSB_DEFAULT (_DEVINFO_MODULEINFO_MODNUMBERMSB_DEFAULT << 20) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_PADCDC (0x1UL << 29) /**< */
+#define _DEVINFO_MODULEINFO_PADCDC_SHIFT 29 /**< Shift value for DEVINFO_PADCDC */
+#define _DEVINFO_MODULEINFO_PADCDC_MASK 0x20000000UL /**< Bit mask for DEVINFO_PADCDC */
+#define _DEVINFO_MODULEINFO_PADCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_PADCDC_VDCDC 0x00000000UL /**< Mode VDCDC for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_PADCDC_OTHER 0x00000001UL /**< Mode OTHER for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_PADCDC_DEFAULT (_DEVINFO_MODULEINFO_PADCDC_DEFAULT << 29) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_PADCDC_VDCDC (_DEVINFO_MODULEINFO_PADCDC_VDCDC << 29) /**< Shifted mode VDCDC for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_PADCDC_OTHER (_DEVINFO_MODULEINFO_PADCDC_OTHER << 29) /**< Shifted mode OTHER for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_PHYLIMITED (0x1UL << 30) /**< */
+#define _DEVINFO_MODULEINFO_PHYLIMITED_SHIFT 30 /**< Shift value for DEVINFO_PHYLIMITED */
+#define _DEVINFO_MODULEINFO_PHYLIMITED_MASK 0x40000000UL /**< Bit mask for DEVINFO_PHYLIMITED */
+#define _DEVINFO_MODULEINFO_PHYLIMITED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_PHYLIMITED_LIMITED 0x00000000UL /**< Mode LIMITED for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_PHYLIMITED_UNLIMITED 0x00000001UL /**< Mode UNLIMITED for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_PHYLIMITED_DEFAULT (_DEVINFO_MODULEINFO_PHYLIMITED_DEFAULT << 30) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_PHYLIMITED_LIMITED (_DEVINFO_MODULEINFO_PHYLIMITED_LIMITED << 30) /**< Shifted mode LIMITED for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_PHYLIMITED_UNLIMITED (_DEVINFO_MODULEINFO_PHYLIMITED_UNLIMITED << 30) /**< Shifted mode UNLIMITED for DEVINFO_MODULEINFO*/
+#define DEVINFO_MODULEINFO_EXTVALID (0x1UL << 31) /**< */
+#define _DEVINFO_MODULEINFO_EXTVALID_SHIFT 31 /**< Shift value for DEVINFO_EXTVALID */
+#define _DEVINFO_MODULEINFO_EXTVALID_MASK 0x80000000UL /**< Bit mask for DEVINFO_EXTVALID */
+#define _DEVINFO_MODULEINFO_EXTVALID_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_EXTVALID_EXTUSED 0x00000000UL /**< Mode EXTUSED for DEVINFO_MODULEINFO */
+#define _DEVINFO_MODULEINFO_EXTVALID_EXTUNUSED 0x00000001UL /**< Mode EXTUNUSED for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_EXTVALID_DEFAULT (_DEVINFO_MODULEINFO_EXTVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_EXTVALID_EXTUSED (_DEVINFO_MODULEINFO_EXTVALID_EXTUSED << 31) /**< Shifted mode EXTUSED for DEVINFO_MODULEINFO */
+#define DEVINFO_MODULEINFO_EXTVALID_EXTUNUSED (_DEVINFO_MODULEINFO_EXTVALID_EXTUNUSED << 31) /**< Shifted mode EXTUNUSED for DEVINFO_MODULEINFO*/
+
+/* Bit fields for DEVINFO MODXOCAL */
+#define _DEVINFO_MODXOCAL_RESETVALUE 0x007FFFFFUL /**< Default value for DEVINFO_MODXOCAL */
+#define _DEVINFO_MODXOCAL_MASK 0x007FFFFFUL /**< Mask for DEVINFO_MODXOCAL */
+#define _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_SHIFT 0 /**< Shift value for DEVINFO_HFXOCTUNEXIANA */
+#define _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK 0xFFUL /**< Bit mask for DEVINFO_HFXOCTUNEXIANA */
+#define _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODXOCAL */
+#define DEVINFO_MODXOCAL_HFXOCTUNEXIANA_DEFAULT (_DEVINFO_MODXOCAL_HFXOCTUNEXIANA_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODXOCAL */
+#define _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_SHIFT 8 /**< Shift value for DEVINFO_HFXOCTUNEXOANA */
+#define _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_MASK 0xFF00UL /**< Bit mask for DEVINFO_HFXOCTUNEXOANA */
+#define _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODXOCAL */
+#define DEVINFO_MODXOCAL_HFXOCTUNEXOANA_DEFAULT (_DEVINFO_MODXOCAL_HFXOCTUNEXOANA_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODXOCAL */
+#define _DEVINFO_MODXOCAL_LFXOCAPTUNE_SHIFT 16 /**< Shift value for DEVINFO_LFXOCAPTUNE */
+#define _DEVINFO_MODXOCAL_LFXOCAPTUNE_MASK 0x7F0000UL /**< Bit mask for DEVINFO_LFXOCAPTUNE */
+#define _DEVINFO_MODXOCAL_LFXOCAPTUNE_DEFAULT 0x0000007FUL /**< Mode DEFAULT for DEVINFO_MODXOCAL */
+#define DEVINFO_MODXOCAL_LFXOCAPTUNE_DEFAULT (_DEVINFO_MODXOCAL_LFXOCAPTUNE_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODXOCAL */
+
+/* Bit fields for DEVINFO IADC0GAIN0 */
+#define _DEVINFO_IADC0GAIN0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0GAIN0 */
+#define _DEVINFO_IADC0GAIN0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0GAIN0 */
+#define _DEVINFO_IADC0GAIN0_GAINCANA1_SHIFT 0 /**< Shift value for DEVINFO_GAINCANA1 */
+#define _DEVINFO_IADC0GAIN0_GAINCANA1_MASK 0xFFFFUL /**< Bit mask for DEVINFO_GAINCANA1 */
+#define _DEVINFO_IADC0GAIN0_GAINCANA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN0 */
+#define DEVINFO_IADC0GAIN0_GAINCANA1_DEFAULT (_DEVINFO_IADC0GAIN0_GAINCANA1_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN0 */
+#define _DEVINFO_IADC0GAIN0_GAINCANA2_SHIFT 16 /**< Shift value for DEVINFO_GAINCANA2 */
+#define _DEVINFO_IADC0GAIN0_GAINCANA2_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_GAINCANA2 */
+#define _DEVINFO_IADC0GAIN0_GAINCANA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN0 */
+#define DEVINFO_IADC0GAIN0_GAINCANA2_DEFAULT (_DEVINFO_IADC0GAIN0_GAINCANA2_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN0 */
+
+/* Bit fields for DEVINFO IADC0GAIN1 */
+#define _DEVINFO_IADC0GAIN1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0GAIN1 */
+#define _DEVINFO_IADC0GAIN1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0GAIN1 */
+#define _DEVINFO_IADC0GAIN1_GAINCANA3_SHIFT 0 /**< Shift value for DEVINFO_GAINCANA3 */
+#define _DEVINFO_IADC0GAIN1_GAINCANA3_MASK 0xFFFFUL /**< Bit mask for DEVINFO_GAINCANA3 */
+#define _DEVINFO_IADC0GAIN1_GAINCANA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN1 */
+#define DEVINFO_IADC0GAIN1_GAINCANA3_DEFAULT (_DEVINFO_IADC0GAIN1_GAINCANA3_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN1 */
+#define _DEVINFO_IADC0GAIN1_GAINCANA4_SHIFT 16 /**< Shift value for DEVINFO_GAINCANA4 */
+#define _DEVINFO_IADC0GAIN1_GAINCANA4_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_GAINCANA4 */
+#define _DEVINFO_IADC0GAIN1_GAINCANA4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN1 */
+#define DEVINFO_IADC0GAIN1_GAINCANA4_DEFAULT (_DEVINFO_IADC0GAIN1_GAINCANA4_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN1 */
+
+/* Bit fields for DEVINFO IADC0OFFSETCAL0 */
+#define _DEVINFO_IADC0OFFSETCAL0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0OFFSETCAL0 */
+#define _DEVINFO_IADC0OFFSETCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0OFFSETCAL0 */
+#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANABASE */
+#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANABASE */
+#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0OFFSETCAL0 */
+#define DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_DEFAULT (_DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0OFFSETCAL0*/
+#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_SHIFT 16 /**< Shift value for DEVINFO_OFFSETANA1HIACC */
+#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_OFFSETANA1HIACC */
+#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0OFFSETCAL0 */
+#define DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_DEFAULT (_DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0OFFSETCAL0*/
+
+/* Bit fields for DEVINFO IADC0NORMALOFFSETCAL0 */
+#define _DEVINFO_IADC0NORMALOFFSETCAL0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0NORMALOFFSETCAL0*/
+#define _DEVINFO_IADC0NORMALOFFSETCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0NORMALOFFSETCAL0 */
+#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA1NORM */
+#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA1NORM */
+#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/
+#define DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_DEFAULT (_DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/
+#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_SHIFT 16 /**< Shift value for DEVINFO_OFFSETANA2NORM */
+#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_OFFSETANA2NORM */
+#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/
+#define DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_DEFAULT (_DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/
+
+/* Bit fields for DEVINFO IADC0NORMALOFFSETCAL1 */
+#define _DEVINFO_IADC0NORMALOFFSETCAL1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0NORMALOFFSETCAL1*/
+#define _DEVINFO_IADC0NORMALOFFSETCAL1_MASK 0x0000FFFFUL /**< Mask for DEVINFO_IADC0NORMALOFFSETCAL1 */
+#define _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA3NORM */
+#define _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA3NORM */
+#define _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL1*/
+#define DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_DEFAULT (_DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL1*/
+
+/* Bit fields for DEVINFO IADC0HISPDOFFSETCAL0 */
+#define _DEVINFO_IADC0HISPDOFFSETCAL0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0HISPDOFFSETCAL0*/
+#define _DEVINFO_IADC0HISPDOFFSETCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0HISPDOFFSETCAL0 */
+#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA1HISPD */
+#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA1HISPD */
+#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/
+#define DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_DEFAULT (_DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/
+#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_SHIFT 16 /**< Shift value for DEVINFO_OFFSETANA2HISPD */
+#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_OFFSETANA2HISPD */
+#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/
+#define DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_DEFAULT (_DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/
+
+/* Bit fields for DEVINFO IADC0HISPDOFFSETCAL1 */
+#define _DEVINFO_IADC0HISPDOFFSETCAL1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0HISPDOFFSETCAL1*/
+#define _DEVINFO_IADC0HISPDOFFSETCAL1_MASK 0x0000FFFFUL /**< Mask for DEVINFO_IADC0HISPDOFFSETCAL1 */
+#define _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA3HISPD */
+#define _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA3HISPD */
+#define _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL1*/
+#define DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_DEFAULT (_DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL1*/
+
+/* Bit fields for DEVINFO LEGACY */
+#define _DEVINFO_LEGACY_RESETVALUE 0x00800000UL /**< Default value for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_MASK 0x00FF0000UL /**< Mask for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_SHIFT 16 /**< Shift value for DEVINFO_DEVICEFAMILY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_MASK 0xFF0000UL /**< Bit mask for DEVINFO_DEVICEFAMILY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_DEFAULT 0x00000080UL /**< Mode DEFAULT for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1P 0x00000010UL /**< Mode EFR32MG1P for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1B 0x00000011UL /**< Mode EFR32MG1B for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1V 0x00000012UL /**< Mode EFR32MG1V for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1P 0x00000013UL /**< Mode EFR32BG1P for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1B 0x00000014UL /**< Mode EFR32BG1B for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1V 0x00000015UL /**< Mode EFR32BG1V for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1P 0x00000019UL /**< Mode EFR32FG1P for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1B 0x0000001AUL /**< Mode EFR32FG1B for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1V 0x0000001BUL /**< Mode EFR32FG1V for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12P 0x0000001CUL /**< Mode EFR32MG12P for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12B 0x0000001DUL /**< Mode EFR32MG12B for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12V 0x0000001EUL /**< Mode EFR32MG12V for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12P 0x0000001FUL /**< Mode EFR32BG12P for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12B 0x00000020UL /**< Mode EFR32BG12B for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12V 0x00000021UL /**< Mode EFR32BG12V for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12P 0x00000025UL /**< Mode EFR32FG12P for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12B 0x00000026UL /**< Mode EFR32FG12B for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12V 0x00000027UL /**< Mode EFR32FG12V for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13P 0x00000028UL /**< Mode EFR32MG13P for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13B 0x00000029UL /**< Mode EFR32MG13B for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13V 0x0000002AUL /**< Mode EFR32MG13V for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13P 0x0000002BUL /**< Mode EFR32BG13P for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13B 0x0000002CUL /**< Mode EFR32BG13B for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13V 0x0000002DUL /**< Mode EFR32BG13V for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13P 0x00000031UL /**< Mode EFR32FG13P for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13B 0x00000032UL /**< Mode EFR32FG13B for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13V 0x00000033UL /**< Mode EFR32FG13V for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14P 0x00000034UL /**< Mode EFR32MG14P for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14B 0x00000035UL /**< Mode EFR32MG14B for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14V 0x00000036UL /**< Mode EFR32MG14V for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14P 0x00000037UL /**< Mode EFR32BG14P for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14B 0x00000038UL /**< Mode EFR32BG14B for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14V 0x00000039UL /**< Mode EFR32BG14V for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14P 0x0000003DUL /**< Mode EFR32FG14P for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14B 0x0000003EUL /**< Mode EFR32FG14B for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14V 0x0000003FUL /**< Mode EFR32FG14V for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32G 0x00000047UL /**< Mode EFM32G for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG 0x00000049UL /**< Mode EFM32TG for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32LG 0x0000004AUL /**< Mode EFM32LG for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32ZG 0x0000004CUL /**< Mode EFM32ZG for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32HG 0x0000004DUL /**< Mode EFM32HG for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG1B 0x00000051UL /**< Mode EFM32PG1B for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG12B 0x00000055UL /**< Mode EFM32PG12B for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG12B 0x00000057UL /**< Mode EFM32JG12B for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG13B 0x00000059UL /**< Mode EFM32PG13B for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG13B 0x0000005BUL /**< Mode EFM32JG13B for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG11B 0x00000064UL /**< Mode EFM32GG11B for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG11B 0x00000067UL /**< Mode EFM32TG11B for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EZR32LG 0x00000078UL /**< Mode EZR32LG for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EZR32WG 0x00000079UL /**< Mode EZR32WG for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_EZR32HG 0x0000007AUL /**< Mode EZR32HG for DEVINFO_LEGACY */
+#define _DEVINFO_LEGACY_DEVICEFAMILY_SERIES2V0 0x00000080UL /**< Mode SERIES2V0 for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_DEFAULT (_DEVINFO_LEGACY_DEVICEFAMILY_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1P << 16) /**< Shifted mode EFR32MG1P for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1B << 16) /**< Shifted mode EFR32MG1B for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1V << 16) /**< Shifted mode EFR32MG1V for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1P << 16) /**< Shifted mode EFR32BG1P for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1B << 16) /**< Shifted mode EFR32BG1B for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1V << 16) /**< Shifted mode EFR32BG1V for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1P << 16) /**< Shifted mode EFR32FG1P for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1B << 16) /**< Shifted mode EFR32FG1B for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1V << 16) /**< Shifted mode EFR32FG1V for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12P << 16) /**< Shifted mode EFR32MG12P for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12B << 16) /**< Shifted mode EFR32MG12B for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12V << 16) /**< Shifted mode EFR32MG12V for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12P << 16) /**< Shifted mode EFR32BG12P for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12B << 16) /**< Shifted mode EFR32BG12B for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12V << 16) /**< Shifted mode EFR32BG12V for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12P << 16) /**< Shifted mode EFR32FG12P for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12B << 16) /**< Shifted mode EFR32FG12B for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12V << 16) /**< Shifted mode EFR32FG12V for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13P << 16) /**< Shifted mode EFR32MG13P for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13B << 16) /**< Shifted mode EFR32MG13B for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13V << 16) /**< Shifted mode EFR32MG13V for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13P << 16) /**< Shifted mode EFR32BG13P for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13B << 16) /**< Shifted mode EFR32BG13B for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13V << 16) /**< Shifted mode EFR32BG13V for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13P << 16) /**< Shifted mode EFR32FG13P for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13B << 16) /**< Shifted mode EFR32FG13B for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13V << 16) /**< Shifted mode EFR32FG13V for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14P << 16) /**< Shifted mode EFR32MG14P for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14B << 16) /**< Shifted mode EFR32MG14B for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14V << 16) /**< Shifted mode EFR32MG14V for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14P << 16) /**< Shifted mode EFR32BG14P for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14B << 16) /**< Shifted mode EFR32BG14B for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14V << 16) /**< Shifted mode EFR32BG14V for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14P << 16) /**< Shifted mode EFR32FG14P for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14B << 16) /**< Shifted mode EFR32FG14B for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14V << 16) /**< Shifted mode EFR32FG14V for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32G (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32G << 16) /**< Shifted mode EFM32G for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG << 16) /**< Shifted mode EFM32TG for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32LG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32LG << 16) /**< Shifted mode EFM32LG for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32WG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32ZG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32ZG << 16) /**< Shifted mode EFM32ZG for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32HG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32HG << 16) /**< Shifted mode EFM32HG for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG12B << 16) /**< Shifted mode EFM32PG12B for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG12B << 16) /**< Shifted mode EFM32JG12B for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG13B << 16) /**< Shifted mode EFM32PG13B for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG13B << 16) /**< Shifted mode EFM32JG13B for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG11B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG11B << 16) /**< Shifted mode EFM32GG11B for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG11B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG11B << 16) /**< Shifted mode EFM32TG11B for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EZR32LG (_DEVINFO_LEGACY_DEVICEFAMILY_EZR32LG << 16) /**< Shifted mode EZR32LG for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EZR32WG (_DEVINFO_LEGACY_DEVICEFAMILY_EZR32WG << 16) /**< Shifted mode EZR32WG for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_EZR32HG (_DEVINFO_LEGACY_DEVICEFAMILY_EZR32HG << 16) /**< Shifted mode EZR32HG for DEVINFO_LEGACY */
+#define DEVINFO_LEGACY_DEVICEFAMILY_SERIES2V0 (_DEVINFO_LEGACY_DEVICEFAMILY_SERIES2V0 << 16) /**< Shifted mode SERIES2V0 for DEVINFO_LEGACY */
+
+/* Bit fields for DEVINFO RTHERM */
+#define _DEVINFO_RTHERM_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_RTHERM */
+#define _DEVINFO_RTHERM_MASK 0x0000FFFFUL /**< Mask for DEVINFO_RTHERM */
+#define _DEVINFO_RTHERM_RTHERM_SHIFT 0 /**< Shift value for DEVINFO_RTHERM */
+#define _DEVINFO_RTHERM_RTHERM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_RTHERM */
+#define _DEVINFO_RTHERM_RTHERM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_RTHERM */
+#define DEVINFO_RTHERM_RTHERM_DEFAULT (_DEVINFO_RTHERM_RTHERM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_RTHERM */
+
+/* Bit fields for DEVINFO FENOTCHCAL */
+#define _DEVINFO_FENOTCHCAL_RESETVALUE 0x000000FFUL /**< Default value for DEVINFO_FENOTCHCAL */
+#define _DEVINFO_FENOTCHCAL_MASK 0x000000FFUL /**< Mask for DEVINFO_FENOTCHCAL */
+#define _DEVINFO_FENOTCHCAL_FENOTCHCAPCRSE_SHIFT 0 /**< Shift value for DEVINFO_FENOTCHCAPCRSE */
+#define _DEVINFO_FENOTCHCAL_FENOTCHCAPCRSE_MASK 0xFUL /**< Bit mask for DEVINFO_FENOTCHCAPCRSE */
+#define _DEVINFO_FENOTCHCAL_FENOTCHCAPCRSE_DEFAULT 0x0000000FUL /**< Mode DEFAULT for DEVINFO_FENOTCHCAL */
+#define DEVINFO_FENOTCHCAL_FENOTCHCAPCRSE_DEFAULT (_DEVINFO_FENOTCHCAL_FENOTCHCAPCRSE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_FENOTCHCAL */
+#define _DEVINFO_FENOTCHCAL_FENOTCHCAPFINE_SHIFT 4 /**< Shift value for DEVINFO_FENOTCHCAPFINE */
+#define _DEVINFO_FENOTCHCAL_FENOTCHCAPFINE_MASK 0xF0UL /**< Bit mask for DEVINFO_FENOTCHCAPFINE */
+#define _DEVINFO_FENOTCHCAL_FENOTCHCAPFINE_DEFAULT 0x0000000FUL /**< Mode DEFAULT for DEVINFO_FENOTCHCAL */
+#define DEVINFO_FENOTCHCAL_FENOTCHCAPFINE_DEFAULT (_DEVINFO_FENOTCHCAL_FENOTCHCAPFINE_DEFAULT << 4) /**< Shifted mode DEFAULT for DEVINFO_FENOTCHCAL */
+
+/** @} End of group EFR32MG24_DEVINFO_BitFields */
+/** @} End of group EFR32MG24_DEVINFO */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_DEVINFO_H */
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_dma_descriptor.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_dma_descriptor.h
similarity index 65%
rename from mcu/efr/common/vendor/efr32fg13/efr32fg13p_dma_descriptor.h
rename to mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_dma_descriptor.h
index f5f85870..d5aeb7a4 100644
--- a/mcu/efr/common/vendor/efr32fg13/efr32fg13p_dma_descriptor.h
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_dma_descriptor.h
@@ -1,33 +1,31 @@
/**************************************************************************//**
- * @file efr32fg13p_dma_descriptor.h
- * @brief EFR32FG13P_DMA_DESCRIPTOR register and bit field definitions
- * @version 5.4.0
+ * @file
+ * @brief EFR32MG24 DMA descriptor bit field definitions
******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
******************************************************************************
*
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.@n
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.@n
+ * misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
- * has no obligation to support this Software. Silicon Laboratories, Inc. is
- * providing the Software "AS IS", with no express or implied warranties of any
- * kind, including, but not limited to, any implied warranties of
- * merchantability or fitness for any particular purpose or warranties against
- * infringement of any proprietary rights of a third party.
- *
- * Silicon Laboratories, Inc. will not be liable for any consequential,
- * incidental, or special damages, or any other relief, or for any claim by
- * any third party, arising from your use of this Software.
- *
*****************************************************************************/
#if defined(__ICCARM__)
@@ -41,7 +39,7 @@
* @{
******************************************************************************/
/**************************************************************************//**
- * @defgroup EFR32FG13P_DMA_DESCRIPTOR DMA Descriptor
+ * @defgroup DMA_DESCRIPTOR DMA Descriptor
* @{
*****************************************************************************/
/** DMA_DESCRIPTOR Register Declaration */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_dpll.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_dpll.h
new file mode 100644
index 00000000..18cf0384
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_dpll.h
@@ -0,0 +1,232 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 DPLL register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_DPLL_H
+#define EFR32MG24_DPLL_H
+#define DPLL_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_DPLL DPLL
+ * @{
+ * @brief EFR32MG24 DPLL Register Declaration.
+ *****************************************************************************/
+
+/** DPLL Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IP Version */
+ __IOM uint32_t EN; /**< Enable */
+ __IOM uint32_t CFG; /**< Config */
+ __IOM uint32_t CFG1; /**< Config1 */
+ __IOM uint32_t IF; /**< Interrupt Flag */
+ __IOM uint32_t IEN; /**< Interrupt Enable */
+ __IM uint32_t STATUS; /**< Status */
+ uint32_t RESERVED0[2U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK; /**< Lock */
+ uint32_t RESERVED1[1014U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP Version */
+ __IOM uint32_t EN_SET; /**< Enable */
+ __IOM uint32_t CFG_SET; /**< Config */
+ __IOM uint32_t CFG1_SET; /**< Config1 */
+ __IOM uint32_t IF_SET; /**< Interrupt Flag */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable */
+ __IM uint32_t STATUS_SET; /**< Status */
+ uint32_t RESERVED2[2U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK_SET; /**< Lock */
+ uint32_t RESERVED3[1014U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP Version */
+ __IOM uint32_t EN_CLR; /**< Enable */
+ __IOM uint32_t CFG_CLR; /**< Config */
+ __IOM uint32_t CFG1_CLR; /**< Config1 */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flag */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable */
+ __IM uint32_t STATUS_CLR; /**< Status */
+ uint32_t RESERVED4[2U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK_CLR; /**< Lock */
+ uint32_t RESERVED5[1014U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP Version */
+ __IOM uint32_t EN_TGL; /**< Enable */
+ __IOM uint32_t CFG_TGL; /**< Config */
+ __IOM uint32_t CFG1_TGL; /**< Config1 */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flag */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable */
+ __IM uint32_t STATUS_TGL; /**< Status */
+ uint32_t RESERVED6[2U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK_TGL; /**< Lock */
+} DPLL_TypeDef;
+/** @} End of group EFR32MG24_DPLL */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_DPLL
+ * @{
+ * @defgroup EFR32MG24_DPLL_BitFields DPLL Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for DPLL IPVERSION */
+#define _DPLL_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for DPLL_IPVERSION */
+#define _DPLL_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for DPLL_IPVERSION */
+#define _DPLL_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for DPLL_IPVERSION */
+#define _DPLL_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for DPLL_IPVERSION */
+#define _DPLL_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for DPLL_IPVERSION */
+#define DPLL_IPVERSION_IPVERSION_DEFAULT (_DPLL_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IPVERSION */
+
+/* Bit fields for DPLL EN */
+#define _DPLL_EN_RESETVALUE 0x00000000UL /**< Default value for DPLL_EN */
+#define _DPLL_EN_MASK 0x00000003UL /**< Mask for DPLL_EN */
+#define DPLL_EN_EN (0x1UL << 0) /**< Module Enable */
+#define _DPLL_EN_EN_SHIFT 0 /**< Shift value for DPLL_EN */
+#define _DPLL_EN_EN_MASK 0x1UL /**< Bit mask for DPLL_EN */
+#define _DPLL_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_EN */
+#define DPLL_EN_EN_DEFAULT (_DPLL_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_EN */
+#define DPLL_EN_DISABLING (0x1UL << 1) /**< Disablement Busy Status */
+#define _DPLL_EN_DISABLING_SHIFT 1 /**< Shift value for DPLL_DISABLING */
+#define _DPLL_EN_DISABLING_MASK 0x2UL /**< Bit mask for DPLL_DISABLING */
+#define _DPLL_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_EN */
+#define DPLL_EN_DISABLING_DEFAULT (_DPLL_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_EN */
+
+/* Bit fields for DPLL CFG */
+#define _DPLL_CFG_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG */
+#define _DPLL_CFG_MASK 0x00000047UL /**< Mask for DPLL_CFG */
+#define DPLL_CFG_MODE (0x1UL << 0) /**< Operating Mode Control */
+#define _DPLL_CFG_MODE_SHIFT 0 /**< Shift value for DPLL_MODE */
+#define _DPLL_CFG_MODE_MASK 0x1UL /**< Bit mask for DPLL_MODE */
+#define _DPLL_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */
+#define _DPLL_CFG_MODE_FLL 0x00000000UL /**< Mode FLL for DPLL_CFG */
+#define _DPLL_CFG_MODE_PLL 0x00000001UL /**< Mode PLL for DPLL_CFG */
+#define DPLL_CFG_MODE_DEFAULT (_DPLL_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG */
+#define DPLL_CFG_MODE_FLL (_DPLL_CFG_MODE_FLL << 0) /**< Shifted mode FLL for DPLL_CFG */
+#define DPLL_CFG_MODE_PLL (_DPLL_CFG_MODE_PLL << 0) /**< Shifted mode PLL for DPLL_CFG */
+#define DPLL_CFG_EDGESEL (0x1UL << 1) /**< Reference Edge Select */
+#define _DPLL_CFG_EDGESEL_SHIFT 1 /**< Shift value for DPLL_EDGESEL */
+#define _DPLL_CFG_EDGESEL_MASK 0x2UL /**< Bit mask for DPLL_EDGESEL */
+#define _DPLL_CFG_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */
+#define DPLL_CFG_EDGESEL_DEFAULT (_DPLL_CFG_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_CFG */
+#define DPLL_CFG_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Control */
+#define _DPLL_CFG_AUTORECOVER_SHIFT 2 /**< Shift value for DPLL_AUTORECOVER */
+#define _DPLL_CFG_AUTORECOVER_MASK 0x4UL /**< Bit mask for DPLL_AUTORECOVER */
+#define _DPLL_CFG_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */
+#define DPLL_CFG_AUTORECOVER_DEFAULT (_DPLL_CFG_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_CFG */
+#define DPLL_CFG_DITHEN (0x1UL << 6) /**< Dither Enable Control */
+#define _DPLL_CFG_DITHEN_SHIFT 6 /**< Shift value for DPLL_DITHEN */
+#define _DPLL_CFG_DITHEN_MASK 0x40UL /**< Bit mask for DPLL_DITHEN */
+#define _DPLL_CFG_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */
+#define DPLL_CFG_DITHEN_DEFAULT (_DPLL_CFG_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for DPLL_CFG */
+
+/* Bit fields for DPLL CFG1 */
+#define _DPLL_CFG1_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG1 */
+#define _DPLL_CFG1_MASK 0x0FFF0FFFUL /**< Mask for DPLL_CFG1 */
+#define _DPLL_CFG1_M_SHIFT 0 /**< Shift value for DPLL_M */
+#define _DPLL_CFG1_M_MASK 0xFFFUL /**< Bit mask for DPLL_M */
+#define _DPLL_CFG1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */
+#define DPLL_CFG1_M_DEFAULT (_DPLL_CFG1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG1 */
+#define _DPLL_CFG1_N_SHIFT 16 /**< Shift value for DPLL_N */
+#define _DPLL_CFG1_N_MASK 0xFFF0000UL /**< Bit mask for DPLL_N */
+#define _DPLL_CFG1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */
+#define DPLL_CFG1_N_DEFAULT (_DPLL_CFG1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for DPLL_CFG1 */
+
+/* Bit fields for DPLL IF */
+#define _DPLL_IF_RESETVALUE 0x00000000UL /**< Default value for DPLL_IF */
+#define _DPLL_IF_MASK 0x00000007UL /**< Mask for DPLL_IF */
+#define DPLL_IF_LOCK (0x1UL << 0) /**< Lock Interrupt Flag */
+#define _DPLL_IF_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */
+#define _DPLL_IF_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */
+#define _DPLL_IF_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */
+#define DPLL_IF_LOCK_DEFAULT (_DPLL_IF_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IF */
+#define DPLL_IF_LOCKFAILLOW (0x1UL << 1) /**< Lock Failure Low Interrupt Flag */
+#define _DPLL_IF_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */
+#define _DPLL_IF_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */
+#define _DPLL_IF_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */
+#define DPLL_IF_LOCKFAILLOW_DEFAULT (_DPLL_IF_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IF */
+#define DPLL_IF_LOCKFAILHIGH (0x1UL << 2) /**< Lock Failure High Interrupt Flag */
+#define _DPLL_IF_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */
+#define _DPLL_IF_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */
+#define _DPLL_IF_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */
+#define DPLL_IF_LOCKFAILHIGH_DEFAULT (_DPLL_IF_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IF */
+
+/* Bit fields for DPLL IEN */
+#define _DPLL_IEN_RESETVALUE 0x00000000UL /**< Default value for DPLL_IEN */
+#define _DPLL_IEN_MASK 0x00000007UL /**< Mask for DPLL_IEN */
+#define DPLL_IEN_LOCK (0x1UL << 0) /**< LOCK interrupt Enable */
+#define _DPLL_IEN_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */
+#define _DPLL_IEN_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */
+#define _DPLL_IEN_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */
+#define DPLL_IEN_LOCK_DEFAULT (_DPLL_IEN_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IEN */
+#define DPLL_IEN_LOCKFAILLOW (0x1UL << 1) /**< LOCKFAILLOW Interrupe Enable */
+#define _DPLL_IEN_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */
+#define _DPLL_IEN_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */
+#define _DPLL_IEN_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */
+#define DPLL_IEN_LOCKFAILLOW_DEFAULT (_DPLL_IEN_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IEN */
+#define DPLL_IEN_LOCKFAILHIGH (0x1UL << 2) /**< LOCKFAILHIGH Interrupt Enable */
+#define _DPLL_IEN_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */
+#define _DPLL_IEN_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */
+#define _DPLL_IEN_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */
+#define DPLL_IEN_LOCKFAILHIGH_DEFAULT (_DPLL_IEN_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IEN */
+
+/* Bit fields for DPLL STATUS */
+#define _DPLL_STATUS_RESETVALUE 0x00000000UL /**< Default value for DPLL_STATUS */
+#define _DPLL_STATUS_MASK 0x80000003UL /**< Mask for DPLL_STATUS */
+#define DPLL_STATUS_RDY (0x1UL << 0) /**< Ready Status */
+#define _DPLL_STATUS_RDY_SHIFT 0 /**< Shift value for DPLL_RDY */
+#define _DPLL_STATUS_RDY_MASK 0x1UL /**< Bit mask for DPLL_RDY */
+#define _DPLL_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */
+#define DPLL_STATUS_RDY_DEFAULT (_DPLL_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_STATUS */
+#define DPLL_STATUS_ENS (0x1UL << 1) /**< Enable Status */
+#define _DPLL_STATUS_ENS_SHIFT 1 /**< Shift value for DPLL_ENS */
+#define _DPLL_STATUS_ENS_MASK 0x2UL /**< Bit mask for DPLL_ENS */
+#define _DPLL_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */
+#define DPLL_STATUS_ENS_DEFAULT (_DPLL_STATUS_ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_STATUS */
+#define DPLL_STATUS_LOCK (0x1UL << 31) /**< Lock Status */
+#define _DPLL_STATUS_LOCK_SHIFT 31 /**< Shift value for DPLL_LOCK */
+#define _DPLL_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for DPLL_LOCK */
+#define _DPLL_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */
+#define _DPLL_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for DPLL_STATUS */
+#define _DPLL_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for DPLL_STATUS */
+#define DPLL_STATUS_LOCK_DEFAULT (_DPLL_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for DPLL_STATUS */
+#define DPLL_STATUS_LOCK_UNLOCKED (_DPLL_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for DPLL_STATUS */
+#define DPLL_STATUS_LOCK_LOCKED (_DPLL_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for DPLL_STATUS */
+
+/* Bit fields for DPLL LOCK */
+#define _DPLL_LOCK_RESETVALUE 0x00007102UL /**< Default value for DPLL_LOCK */
+#define _DPLL_LOCK_MASK 0x0000FFFFUL /**< Mask for DPLL_LOCK */
+#define _DPLL_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for DPLL_LOCKKEY */
+#define _DPLL_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for DPLL_LOCKKEY */
+#define _DPLL_LOCK_LOCKKEY_DEFAULT 0x00007102UL /**< Mode DEFAULT for DPLL_LOCK */
+#define _DPLL_LOCK_LOCKKEY_UNLOCK 0x00007102UL /**< Mode UNLOCK for DPLL_LOCK */
+#define DPLL_LOCK_LOCKKEY_DEFAULT (_DPLL_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_LOCK */
+#define DPLL_LOCK_LOCKKEY_UNLOCK (_DPLL_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for DPLL_LOCK */
+
+/** @} End of group EFR32MG24_DPLL_BitFields */
+/** @} End of group EFR32MG24_DPLL */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_DPLL_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_eca.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_eca.h
new file mode 100644
index 00000000..6387314e
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_eca.h
@@ -0,0 +1,820 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 ECA register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_ECA_H
+#define EFR32MG24_ECA_H
+#define ECA_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_ECA ECA
+ * @{
+ * @brief EFR32MG24 ECA Register Declaration.
+ *****************************************************************************/
+
+/** ECA BUF Register Group Declaration. */
+typedef struct {
+ __IOM uint32_t BASE; /**< BUFFER BASE ADDRESS */
+ __IOM uint32_t LIMITOFFSET; /**< Limit Offset */
+ __IOM uint32_t WMOFFSET; /**< Watermark Offset */
+} ECA_BUF_TypeDef;
+
+/** ECA Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IP Version ID */
+ __IOM uint32_t EN; /**< Module Enable */
+ __IOM uint32_t SWRST; /**< Software Reset */
+ __IOM uint32_t CMD; /**< Command */
+ __IOM uint32_t CONTROL; /**< Control */
+ __IM uint32_t STATUS; /**< Status */
+ __IOM uint32_t IF; /**< Interrupt Flag */
+ __IOM uint32_t IEN; /**< Interrupt EN */
+ __IM uint32_t DMABUSERRORSTATUS; /**< DMA Bus Error Status */
+ ECA_BUF_TypeDef BUF[2U]; /**< */
+ __IM uint32_t BUFPTRSTATUS; /**< Buffer Pointer Status */
+ __IOM uint32_t STARTTRIGCTRL; /**< Start Trigger Control */
+ __IOM uint32_t STOPTRIGCTRL; /**< Stop Trigger Control */
+ __IOM uint32_t STARTTRIGENMASK; /**< Start Trigger Enable Mask */
+ __IOM uint32_t STARTTRIGREDMASK; /**< Start Trigger Rising Edge Mask */
+ __IOM uint32_t STARTTRIGFEDMASK; /**< Start Trigger Falling Edge Mask */
+ __IOM uint32_t STARTTRIGLVL0MASK; /**< Start Trigger Level 0 Mask */
+ __IOM uint32_t STARTTRIGLVL1MASK; /**< Start Trigger Level 1 Mask */
+ __IOM uint32_t STOPTRIGENMASK; /**< Stop Trigger Enable Mask */
+ __IOM uint32_t STOPTRIGREDMASK; /**< Stop Trigger Rising Edge Mask */
+ __IOM uint32_t STOPTRIGFEDMASK; /**< Stop Trigger Falling Edge Mask */
+ __IOM uint32_t STOPTRIGLVL0MASK; /**< Stop Trigger Level 0 Mask */
+ __IOM uint32_t STOPTRIGLVL1MASK; /**< Stop Trigger Level 1 Mask */
+ __IOM uint32_t CAPTURECTRL; /**< Capture Control */
+ __IOM uint32_t CAPTURESTARTDELAY; /**< Capture Start Delay */
+ __IOM uint32_t CAPTURESTOPDELAY; /**< Capture Stop Delay */
+ __IOM uint32_t CAPTURERATECTRL; /**< Capture Rate Control */
+ __IOM uint32_t PLAYBACKCTRL; /**< Playback Control */
+ __IOM uint32_t PLAYBACKRATECTRL; /**< Playback Rate Control */
+ __IOM uint32_t EVENTCNTRCTRL; /**< Event Counter Control */
+ __IOM uint32_t EVENTCNTRCOMPARE; /**< Event Counter Compare */
+ __IM uint32_t EVENTCNTRSTATUS; /**< Event Counter Status */
+ uint32_t RESERVED0[987U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP Version ID */
+ __IOM uint32_t EN_SET; /**< Module Enable */
+ __IOM uint32_t SWRST_SET; /**< Software Reset */
+ __IOM uint32_t CMD_SET; /**< Command */
+ __IOM uint32_t CONTROL_SET; /**< Control */
+ __IM uint32_t STATUS_SET; /**< Status */
+ __IOM uint32_t IF_SET; /**< Interrupt Flag */
+ __IOM uint32_t IEN_SET; /**< Interrupt EN */
+ __IM uint32_t DMABUSERRORSTATUS_SET; /**< DMA Bus Error Status */
+ ECA_BUF_TypeDef BUF_SET[2U]; /**< */
+ __IM uint32_t BUFPTRSTATUS_SET; /**< Buffer Pointer Status */
+ __IOM uint32_t STARTTRIGCTRL_SET; /**< Start Trigger Control */
+ __IOM uint32_t STOPTRIGCTRL_SET; /**< Stop Trigger Control */
+ __IOM uint32_t STARTTRIGENMASK_SET; /**< Start Trigger Enable Mask */
+ __IOM uint32_t STARTTRIGREDMASK_SET; /**< Start Trigger Rising Edge Mask */
+ __IOM uint32_t STARTTRIGFEDMASK_SET; /**< Start Trigger Falling Edge Mask */
+ __IOM uint32_t STARTTRIGLVL0MASK_SET; /**< Start Trigger Level 0 Mask */
+ __IOM uint32_t STARTTRIGLVL1MASK_SET; /**< Start Trigger Level 1 Mask */
+ __IOM uint32_t STOPTRIGENMASK_SET; /**< Stop Trigger Enable Mask */
+ __IOM uint32_t STOPTRIGREDMASK_SET; /**< Stop Trigger Rising Edge Mask */
+ __IOM uint32_t STOPTRIGFEDMASK_SET; /**< Stop Trigger Falling Edge Mask */
+ __IOM uint32_t STOPTRIGLVL0MASK_SET; /**< Stop Trigger Level 0 Mask */
+ __IOM uint32_t STOPTRIGLVL1MASK_SET; /**< Stop Trigger Level 1 Mask */
+ __IOM uint32_t CAPTURECTRL_SET; /**< Capture Control */
+ __IOM uint32_t CAPTURESTARTDELAY_SET; /**< Capture Start Delay */
+ __IOM uint32_t CAPTURESTOPDELAY_SET; /**< Capture Stop Delay */
+ __IOM uint32_t CAPTURERATECTRL_SET; /**< Capture Rate Control */
+ __IOM uint32_t PLAYBACKCTRL_SET; /**< Playback Control */
+ __IOM uint32_t PLAYBACKRATECTRL_SET; /**< Playback Rate Control */
+ __IOM uint32_t EVENTCNTRCTRL_SET; /**< Event Counter Control */
+ __IOM uint32_t EVENTCNTRCOMPARE_SET; /**< Event Counter Compare */
+ __IM uint32_t EVENTCNTRSTATUS_SET; /**< Event Counter Status */
+ uint32_t RESERVED1[987U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP Version ID */
+ __IOM uint32_t EN_CLR; /**< Module Enable */
+ __IOM uint32_t SWRST_CLR; /**< Software Reset */
+ __IOM uint32_t CMD_CLR; /**< Command */
+ __IOM uint32_t CONTROL_CLR; /**< Control */
+ __IM uint32_t STATUS_CLR; /**< Status */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flag */
+ __IOM uint32_t IEN_CLR; /**< Interrupt EN */
+ __IM uint32_t DMABUSERRORSTATUS_CLR; /**< DMA Bus Error Status */
+ ECA_BUF_TypeDef BUF_CLR[2U]; /**< */
+ __IM uint32_t BUFPTRSTATUS_CLR; /**< Buffer Pointer Status */
+ __IOM uint32_t STARTTRIGCTRL_CLR; /**< Start Trigger Control */
+ __IOM uint32_t STOPTRIGCTRL_CLR; /**< Stop Trigger Control */
+ __IOM uint32_t STARTTRIGENMASK_CLR; /**< Start Trigger Enable Mask */
+ __IOM uint32_t STARTTRIGREDMASK_CLR; /**< Start Trigger Rising Edge Mask */
+ __IOM uint32_t STARTTRIGFEDMASK_CLR; /**< Start Trigger Falling Edge Mask */
+ __IOM uint32_t STARTTRIGLVL0MASK_CLR; /**< Start Trigger Level 0 Mask */
+ __IOM uint32_t STARTTRIGLVL1MASK_CLR; /**< Start Trigger Level 1 Mask */
+ __IOM uint32_t STOPTRIGENMASK_CLR; /**< Stop Trigger Enable Mask */
+ __IOM uint32_t STOPTRIGREDMASK_CLR; /**< Stop Trigger Rising Edge Mask */
+ __IOM uint32_t STOPTRIGFEDMASK_CLR; /**< Stop Trigger Falling Edge Mask */
+ __IOM uint32_t STOPTRIGLVL0MASK_CLR; /**< Stop Trigger Level 0 Mask */
+ __IOM uint32_t STOPTRIGLVL1MASK_CLR; /**< Stop Trigger Level 1 Mask */
+ __IOM uint32_t CAPTURECTRL_CLR; /**< Capture Control */
+ __IOM uint32_t CAPTURESTARTDELAY_CLR; /**< Capture Start Delay */
+ __IOM uint32_t CAPTURESTOPDELAY_CLR; /**< Capture Stop Delay */
+ __IOM uint32_t CAPTURERATECTRL_CLR; /**< Capture Rate Control */
+ __IOM uint32_t PLAYBACKCTRL_CLR; /**< Playback Control */
+ __IOM uint32_t PLAYBACKRATECTRL_CLR; /**< Playback Rate Control */
+ __IOM uint32_t EVENTCNTRCTRL_CLR; /**< Event Counter Control */
+ __IOM uint32_t EVENTCNTRCOMPARE_CLR; /**< Event Counter Compare */
+ __IM uint32_t EVENTCNTRSTATUS_CLR; /**< Event Counter Status */
+ uint32_t RESERVED2[987U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP Version ID */
+ __IOM uint32_t EN_TGL; /**< Module Enable */
+ __IOM uint32_t SWRST_TGL; /**< Software Reset */
+ __IOM uint32_t CMD_TGL; /**< Command */
+ __IOM uint32_t CONTROL_TGL; /**< Control */
+ __IM uint32_t STATUS_TGL; /**< Status */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flag */
+ __IOM uint32_t IEN_TGL; /**< Interrupt EN */
+ __IM uint32_t DMABUSERRORSTATUS_TGL; /**< DMA Bus Error Status */
+ ECA_BUF_TypeDef BUF_TGL[2U]; /**< */
+ __IM uint32_t BUFPTRSTATUS_TGL; /**< Buffer Pointer Status */
+ __IOM uint32_t STARTTRIGCTRL_TGL; /**< Start Trigger Control */
+ __IOM uint32_t STOPTRIGCTRL_TGL; /**< Stop Trigger Control */
+ __IOM uint32_t STARTTRIGENMASK_TGL; /**< Start Trigger Enable Mask */
+ __IOM uint32_t STARTTRIGREDMASK_TGL; /**< Start Trigger Rising Edge Mask */
+ __IOM uint32_t STARTTRIGFEDMASK_TGL; /**< Start Trigger Falling Edge Mask */
+ __IOM uint32_t STARTTRIGLVL0MASK_TGL; /**< Start Trigger Level 0 Mask */
+ __IOM uint32_t STARTTRIGLVL1MASK_TGL; /**< Start Trigger Level 1 Mask */
+ __IOM uint32_t STOPTRIGENMASK_TGL; /**< Stop Trigger Enable Mask */
+ __IOM uint32_t STOPTRIGREDMASK_TGL; /**< Stop Trigger Rising Edge Mask */
+ __IOM uint32_t STOPTRIGFEDMASK_TGL; /**< Stop Trigger Falling Edge Mask */
+ __IOM uint32_t STOPTRIGLVL0MASK_TGL; /**< Stop Trigger Level 0 Mask */
+ __IOM uint32_t STOPTRIGLVL1MASK_TGL; /**< Stop Trigger Level 1 Mask */
+ __IOM uint32_t CAPTURECTRL_TGL; /**< Capture Control */
+ __IOM uint32_t CAPTURESTARTDELAY_TGL; /**< Capture Start Delay */
+ __IOM uint32_t CAPTURESTOPDELAY_TGL; /**< Capture Stop Delay */
+ __IOM uint32_t CAPTURERATECTRL_TGL; /**< Capture Rate Control */
+ __IOM uint32_t PLAYBACKCTRL_TGL; /**< Playback Control */
+ __IOM uint32_t PLAYBACKRATECTRL_TGL; /**< Playback Rate Control */
+ __IOM uint32_t EVENTCNTRCTRL_TGL; /**< Event Counter Control */
+ __IOM uint32_t EVENTCNTRCOMPARE_TGL; /**< Event Counter Compare */
+ __IM uint32_t EVENTCNTRSTATUS_TGL; /**< Event Counter Status */
+} ECA_TypeDef;
+/** @} End of group EFR32MG24_ECA */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_ECA
+ * @{
+ * @defgroup EFR32MG24_ECA_BitFields ECA Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for ECA IPVERSION */
+#define _ECA_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for ECA_IPVERSION */
+#define _ECA_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ECA_IPVERSION */
+#define _ECA_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ECA_IPVERSION */
+#define _ECA_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_IPVERSION */
+#define _ECA_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for ECA_IPVERSION */
+#define ECA_IPVERSION_IPVERSION_DEFAULT (_ECA_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_IPVERSION */
+
+/* Bit fields for ECA EN */
+#define _ECA_EN_RESETVALUE 0x00000000UL /**< Default value for ECA_EN */
+#define _ECA_EN_MASK 0x00000003UL /**< Mask for ECA_EN */
+#define ECA_EN_EN (0x1UL << 0) /**< Module Enable */
+#define _ECA_EN_EN_SHIFT 0 /**< Shift value for ECA_EN */
+#define _ECA_EN_EN_MASK 0x1UL /**< Bit mask for ECA_EN */
+#define _ECA_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_EN */
+#define ECA_EN_EN_DEFAULT (_ECA_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_EN */
+#define ECA_EN_DISABLING (0x1UL << 1) /**< Disablement Busy Status */
+#define _ECA_EN_DISABLING_SHIFT 1 /**< Shift value for ECA_DISABLING */
+#define _ECA_EN_DISABLING_MASK 0x2UL /**< Bit mask for ECA_DISABLING */
+#define _ECA_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_EN */
+#define ECA_EN_DISABLING_DEFAULT (_ECA_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for ECA_EN */
+
+/* Bit fields for ECA SWRST */
+#define _ECA_SWRST_RESETVALUE 0x00000000UL /**< Default value for ECA_SWRST */
+#define _ECA_SWRST_MASK 0x00000003UL /**< Mask for ECA_SWRST */
+#define ECA_SWRST_SWRST (0x1UL << 0) /**< Software Reset Command */
+#define _ECA_SWRST_SWRST_SHIFT 0 /**< Shift value for ECA_SWRST */
+#define _ECA_SWRST_SWRST_MASK 0x1UL /**< Bit mask for ECA_SWRST */
+#define _ECA_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_SWRST */
+#define ECA_SWRST_SWRST_DEFAULT (_ECA_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_SWRST */
+#define ECA_SWRST_RESETTING (0x1UL << 1) /**< Software Reset Busy Status */
+#define _ECA_SWRST_RESETTING_SHIFT 1 /**< Shift value for ECA_RESETTING */
+#define _ECA_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for ECA_RESETTING */
+#define _ECA_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_SWRST */
+#define ECA_SWRST_RESETTING_DEFAULT (_ECA_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for ECA_SWRST */
+
+/* Bit fields for ECA CMD */
+#define _ECA_CMD_RESETVALUE 0x00000000UL /**< Default value for ECA_CMD */
+#define _ECA_CMD_MASK 0x0000001FUL /**< Mask for ECA_CMD */
+#define _ECA_CMD_MODE_SHIFT 0 /**< Shift value for ECA_MODE */
+#define _ECA_CMD_MODE_MASK 0x3UL /**< Bit mask for ECA_MODE */
+#define _ECA_CMD_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CMD */
+#define _ECA_CMD_MODE_DISABLED 0x00000001UL /**< Mode DISABLED for ECA_CMD */
+#define _ECA_CMD_MODE_CAPTURE 0x00000002UL /**< Mode CAPTURE for ECA_CMD */
+#define _ECA_CMD_MODE_PLAYBACK 0x00000003UL /**< Mode PLAYBACK for ECA_CMD */
+#define ECA_CMD_MODE_DEFAULT (_ECA_CMD_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_CMD */
+#define ECA_CMD_MODE_DISABLED (_ECA_CMD_MODE_DISABLED << 0) /**< Shifted mode DISABLED for ECA_CMD */
+#define ECA_CMD_MODE_CAPTURE (_ECA_CMD_MODE_CAPTURE << 0) /**< Shifted mode CAPTURE for ECA_CMD */
+#define ECA_CMD_MODE_PLAYBACK (_ECA_CMD_MODE_PLAYBACK << 0) /**< Shifted mode PLAYBACK for ECA_CMD */
+#define ECA_CMD_STARTEVENTCNTR (0x1UL << 2) /**< Start Event Counter */
+#define _ECA_CMD_STARTEVENTCNTR_SHIFT 2 /**< Shift value for ECA_STARTEVENTCNTR */
+#define _ECA_CMD_STARTEVENTCNTR_MASK 0x4UL /**< Bit mask for ECA_STARTEVENTCNTR */
+#define _ECA_CMD_STARTEVENTCNTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CMD */
+#define ECA_CMD_STARTEVENTCNTR_DEFAULT (_ECA_CMD_STARTEVENTCNTR_DEFAULT << 2) /**< Shifted mode DEFAULT for ECA_CMD */
+#define ECA_CMD_STOPEVENTCNTR (0x1UL << 3) /**< Stop Event Counter */
+#define _ECA_CMD_STOPEVENTCNTR_SHIFT 3 /**< Shift value for ECA_STOPEVENTCNTR */
+#define _ECA_CMD_STOPEVENTCNTR_MASK 0x8UL /**< Bit mask for ECA_STOPEVENTCNTR */
+#define _ECA_CMD_STOPEVENTCNTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CMD */
+#define ECA_CMD_STOPEVENTCNTR_DEFAULT (_ECA_CMD_STOPEVENTCNTR_DEFAULT << 3) /**< Shifted mode DEFAULT for ECA_CMD */
+#define ECA_CMD_CLEAREVENTCNTR (0x1UL << 4) /**< Clear Event Counter */
+#define _ECA_CMD_CLEAREVENTCNTR_SHIFT 4 /**< Shift value for ECA_CLEAREVENTCNTR */
+#define _ECA_CMD_CLEAREVENTCNTR_MASK 0x10UL /**< Bit mask for ECA_CLEAREVENTCNTR */
+#define _ECA_CMD_CLEAREVENTCNTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CMD */
+#define ECA_CMD_CLEAREVENTCNTR_DEFAULT (_ECA_CMD_CLEAREVENTCNTR_DEFAULT << 4) /**< Shifted mode DEFAULT for ECA_CMD */
+
+/* Bit fields for ECA CONTROL */
+#define _ECA_CONTROL_RESETVALUE 0x00000000UL /**< Default value for ECA_CONTROL */
+#define _ECA_CONTROL_MASK 0x00000003UL /**< Mask for ECA_CONTROL */
+#define ECA_CONTROL_BUFMODE (0x1UL << 0) /**< Buffer Mode */
+#define _ECA_CONTROL_BUFMODE_SHIFT 0 /**< Shift value for ECA_BUFMODE */
+#define _ECA_CONTROL_BUFMODE_MASK 0x1UL /**< Bit mask for ECA_BUFMODE */
+#define _ECA_CONTROL_BUFMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CONTROL */
+#define _ECA_CONTROL_BUFMODE_SINGLE 0x00000000UL /**< Mode SINGLE for ECA_CONTROL */
+#define _ECA_CONTROL_BUFMODE_DUAL 0x00000001UL /**< Mode DUAL for ECA_CONTROL */
+#define ECA_CONTROL_BUFMODE_DEFAULT (_ECA_CONTROL_BUFMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_CONTROL */
+#define ECA_CONTROL_BUFMODE_SINGLE (_ECA_CONTROL_BUFMODE_SINGLE << 0) /**< Shifted mode SINGLE for ECA_CONTROL */
+#define ECA_CONTROL_BUFMODE_DUAL (_ECA_CONTROL_BUFMODE_DUAL << 0) /**< Shifted mode DUAL for ECA_CONTROL */
+#define ECA_CONTROL_QCHANNELMODE (0x1UL << 1) /**< Q-Channel Mode */
+#define _ECA_CONTROL_QCHANNELMODE_SHIFT 1 /**< Shift value for ECA_QCHANNELMODE */
+#define _ECA_CONTROL_QCHANNELMODE_MASK 0x2UL /**< Bit mask for ECA_QCHANNELMODE */
+#define _ECA_CONTROL_QCHANNELMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CONTROL */
+#define _ECA_CONTROL_QCHANNELMODE_ACCEPT 0x00000000UL /**< Mode ACCEPT for ECA_CONTROL */
+#define _ECA_CONTROL_QCHANNELMODE_DENY 0x00000001UL /**< Mode DENY for ECA_CONTROL */
+#define ECA_CONTROL_QCHANNELMODE_DEFAULT (_ECA_CONTROL_QCHANNELMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for ECA_CONTROL */
+#define ECA_CONTROL_QCHANNELMODE_ACCEPT (_ECA_CONTROL_QCHANNELMODE_ACCEPT << 1) /**< Shifted mode ACCEPT for ECA_CONTROL */
+#define ECA_CONTROL_QCHANNELMODE_DENY (_ECA_CONTROL_QCHANNELMODE_DENY << 1) /**< Shifted mode DENY for ECA_CONTROL */
+
+/* Bit fields for ECA STATUS */
+#define _ECA_STATUS_RESETVALUE 0x00000000UL /**< Default value for ECA_STATUS */
+#define _ECA_STATUS_MASK 0x0000000FUL /**< Mask for ECA_STATUS */
+#define _ECA_STATUS_RUNMODE_SHIFT 0 /**< Shift value for ECA_RUNMODE */
+#define _ECA_STATUS_RUNMODE_MASK 0x3UL /**< Bit mask for ECA_RUNMODE */
+#define _ECA_STATUS_RUNMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STATUS */
+#define _ECA_STATUS_RUNMODE_DISABLED 0x00000000UL /**< Mode DISABLED for ECA_STATUS */
+#define _ECA_STATUS_RUNMODE_CAPTURE 0x00000001UL /**< Mode CAPTURE for ECA_STATUS */
+#define _ECA_STATUS_RUNMODE_PLAYBACK 0x00000002UL /**< Mode PLAYBACK for ECA_STATUS */
+#define ECA_STATUS_RUNMODE_DEFAULT (_ECA_STATUS_RUNMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_STATUS */
+#define ECA_STATUS_RUNMODE_DISABLED (_ECA_STATUS_RUNMODE_DISABLED << 0) /**< Shifted mode DISABLED for ECA_STATUS */
+#define ECA_STATUS_RUNMODE_CAPTURE (_ECA_STATUS_RUNMODE_CAPTURE << 0) /**< Shifted mode CAPTURE for ECA_STATUS */
+#define ECA_STATUS_RUNMODE_PLAYBACK (_ECA_STATUS_RUNMODE_PLAYBACK << 0) /**< Shifted mode PLAYBACK for ECA_STATUS */
+#define ECA_STATUS_SYNCBUSY (0x1UL << 2) /**< Sync Busy */
+#define _ECA_STATUS_SYNCBUSY_SHIFT 2 /**< Shift value for ECA_SYNCBUSY */
+#define _ECA_STATUS_SYNCBUSY_MASK 0x4UL /**< Bit mask for ECA_SYNCBUSY */
+#define _ECA_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STATUS */
+#define ECA_STATUS_SYNCBUSY_DEFAULT (_ECA_STATUS_SYNCBUSY_DEFAULT << 2) /**< Shifted mode DEFAULT for ECA_STATUS */
+#define ECA_STATUS_EVENTCNTRSTARTED (0x1UL << 3) /**< Event Counter Started */
+#define _ECA_STATUS_EVENTCNTRSTARTED_SHIFT 3 /**< Shift value for ECA_EVENTCNTRSTARTED */
+#define _ECA_STATUS_EVENTCNTRSTARTED_MASK 0x8UL /**< Bit mask for ECA_EVENTCNTRSTARTED */
+#define _ECA_STATUS_EVENTCNTRSTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STATUS */
+#define ECA_STATUS_EVENTCNTRSTARTED_DEFAULT (_ECA_STATUS_EVENTCNTRSTARTED_DEFAULT << 3) /**< Shifted mode DEFAULT for ECA_STATUS */
+
+/* Bit fields for ECA IF */
+#define _ECA_IF_RESETVALUE 0x00000000UL /**< Default value for ECA_IF */
+#define _ECA_IF_MASK 0x00003FFFUL /**< Mask for ECA_IF */
+#define ECA_IF_BUF0WMIND (0x1UL << 0) /**< BUF0 Watermark Indication */
+#define _ECA_IF_BUF0WMIND_SHIFT 0 /**< Shift value for ECA_BUF0WMIND */
+#define _ECA_IF_BUF0WMIND_MASK 0x1UL /**< Bit mask for ECA_BUF0WMIND */
+#define _ECA_IF_BUF0WMIND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IF */
+#define ECA_IF_BUF0WMIND_DEFAULT (_ECA_IF_BUF0WMIND_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_IF */
+#define ECA_IF_BUF1WMIND (0x1UL << 1) /**< BUF1 Watermark Indication */
+#define _ECA_IF_BUF1WMIND_SHIFT 1 /**< Shift value for ECA_BUF1WMIND */
+#define _ECA_IF_BUF1WMIND_MASK 0x2UL /**< Bit mask for ECA_BUF1WMIND */
+#define _ECA_IF_BUF1WMIND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IF */
+#define ECA_IF_BUF1WMIND_DEFAULT (_ECA_IF_BUF1WMIND_DEFAULT << 1) /**< Shifted mode DEFAULT for ECA_IF */
+#define ECA_IF_BUF0FULLIND (0x1UL << 2) /**< BUF0 Full Indication */
+#define _ECA_IF_BUF0FULLIND_SHIFT 2 /**< Shift value for ECA_BUF0FULLIND */
+#define _ECA_IF_BUF0FULLIND_MASK 0x4UL /**< Bit mask for ECA_BUF0FULLIND */
+#define _ECA_IF_BUF0FULLIND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IF */
+#define ECA_IF_BUF0FULLIND_DEFAULT (_ECA_IF_BUF0FULLIND_DEFAULT << 2) /**< Shifted mode DEFAULT for ECA_IF */
+#define ECA_IF_BUF1FULLIND (0x1UL << 3) /**< BUF1 Full Indication */
+#define _ECA_IF_BUF1FULLIND_SHIFT 3 /**< Shift value for ECA_BUF1FULLIND */
+#define _ECA_IF_BUF1FULLIND_MASK 0x8UL /**< Bit mask for ECA_BUF1FULLIND */
+#define _ECA_IF_BUF1FULLIND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IF */
+#define ECA_IF_BUF1FULLIND_DEFAULT (_ECA_IF_BUF1FULLIND_DEFAULT << 3) /**< Shifted mode DEFAULT for ECA_IF */
+#define ECA_IF_STARTTRIG (0x1UL << 4) /**< Start Trigger */
+#define _ECA_IF_STARTTRIG_SHIFT 4 /**< Shift value for ECA_STARTTRIG */
+#define _ECA_IF_STARTTRIG_MASK 0x10UL /**< Bit mask for ECA_STARTTRIG */
+#define _ECA_IF_STARTTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IF */
+#define ECA_IF_STARTTRIG_DEFAULT (_ECA_IF_STARTTRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for ECA_IF */
+#define ECA_IF_STOPTRIG (0x1UL << 5) /**< Stop Trigger */
+#define _ECA_IF_STOPTRIG_SHIFT 5 /**< Shift value for ECA_STOPTRIG */
+#define _ECA_IF_STOPTRIG_MASK 0x20UL /**< Bit mask for ECA_STOPTRIG */
+#define _ECA_IF_STOPTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IF */
+#define ECA_IF_STOPTRIG_DEFAULT (_ECA_IF_STOPTRIG_DEFAULT << 5) /**< Shifted mode DEFAULT for ECA_IF */
+#define ECA_IF_CAPTURESTART (0x1UL << 6) /**< Capture Start */
+#define _ECA_IF_CAPTURESTART_SHIFT 6 /**< Shift value for ECA_CAPTURESTART */
+#define _ECA_IF_CAPTURESTART_MASK 0x40UL /**< Bit mask for ECA_CAPTURESTART */
+#define _ECA_IF_CAPTURESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IF */
+#define ECA_IF_CAPTURESTART_DEFAULT (_ECA_IF_CAPTURESTART_DEFAULT << 6) /**< Shifted mode DEFAULT for ECA_IF */
+#define ECA_IF_CAPTUREEND (0x1UL << 7) /**< Capture End */
+#define _ECA_IF_CAPTUREEND_SHIFT 7 /**< Shift value for ECA_CAPTUREEND */
+#define _ECA_IF_CAPTUREEND_MASK 0x80UL /**< Bit mask for ECA_CAPTUREEND */
+#define _ECA_IF_CAPTUREEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IF */
+#define ECA_IF_CAPTUREEND_DEFAULT (_ECA_IF_CAPTUREEND_DEFAULT << 7) /**< Shifted mode DEFAULT for ECA_IF */
+#define ECA_IF_PLAYBACKSTART (0x1UL << 8) /**< Playback Start */
+#define _ECA_IF_PLAYBACKSTART_SHIFT 8 /**< Shift value for ECA_PLAYBACKSTART */
+#define _ECA_IF_PLAYBACKSTART_MASK 0x100UL /**< Bit mask for ECA_PLAYBACKSTART */
+#define _ECA_IF_PLAYBACKSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IF */
+#define ECA_IF_PLAYBACKSTART_DEFAULT (_ECA_IF_PLAYBACKSTART_DEFAULT << 8) /**< Shifted mode DEFAULT for ECA_IF */
+#define ECA_IF_PLAYBACKEND (0x1UL << 9) /**< Playback End */
+#define _ECA_IF_PLAYBACKEND_SHIFT 9 /**< Shift value for ECA_PLAYBACKEND */
+#define _ECA_IF_PLAYBACKEND_MASK 0x200UL /**< Bit mask for ECA_PLAYBACKEND */
+#define _ECA_IF_PLAYBACKEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IF */
+#define ECA_IF_PLAYBACKEND_DEFAULT (_ECA_IF_PLAYBACKEND_DEFAULT << 9) /**< Shifted mode DEFAULT for ECA_IF */
+#define ECA_IF_EVENTCNTRCOMP (0x1UL << 10) /**< Event Counter Compare */
+#define _ECA_IF_EVENTCNTRCOMP_SHIFT 10 /**< Shift value for ECA_EVENTCNTRCOMP */
+#define _ECA_IF_EVENTCNTRCOMP_MASK 0x400UL /**< Bit mask for ECA_EVENTCNTRCOMP */
+#define _ECA_IF_EVENTCNTRCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IF */
+#define ECA_IF_EVENTCNTRCOMP_DEFAULT (_ECA_IF_EVENTCNTRCOMP_DEFAULT << 10) /**< Shifted mode DEFAULT for ECA_IF */
+#define ECA_IF_FIFOORERROR (0x1UL << 11) /**< FIFO Overrun Error */
+#define _ECA_IF_FIFOORERROR_SHIFT 11 /**< Shift value for ECA_FIFOORERROR */
+#define _ECA_IF_FIFOORERROR_MASK 0x800UL /**< Bit mask for ECA_FIFOORERROR */
+#define _ECA_IF_FIFOORERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IF */
+#define ECA_IF_FIFOORERROR_DEFAULT (_ECA_IF_FIFOORERROR_DEFAULT << 11) /**< Shifted mode DEFAULT for ECA_IF */
+#define ECA_IF_FIFOURERROR (0x1UL << 12) /**< FIFO Underrun Error */
+#define _ECA_IF_FIFOURERROR_SHIFT 12 /**< Shift value for ECA_FIFOURERROR */
+#define _ECA_IF_FIFOURERROR_MASK 0x1000UL /**< Bit mask for ECA_FIFOURERROR */
+#define _ECA_IF_FIFOURERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IF */
+#define ECA_IF_FIFOURERROR_DEFAULT (_ECA_IF_FIFOURERROR_DEFAULT << 12) /**< Shifted mode DEFAULT for ECA_IF */
+#define ECA_IF_DMABUSERROR (0x1UL << 13) /**< DMA Bus Error */
+#define _ECA_IF_DMABUSERROR_SHIFT 13 /**< Shift value for ECA_DMABUSERROR */
+#define _ECA_IF_DMABUSERROR_MASK 0x2000UL /**< Bit mask for ECA_DMABUSERROR */
+#define _ECA_IF_DMABUSERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IF */
+#define ECA_IF_DMABUSERROR_DEFAULT (_ECA_IF_DMABUSERROR_DEFAULT << 13) /**< Shifted mode DEFAULT for ECA_IF */
+
+/* Bit fields for ECA IEN */
+#define _ECA_IEN_RESETVALUE 0x00000000UL /**< Default value for ECA_IEN */
+#define _ECA_IEN_MASK 0x00003FFFUL /**< Mask for ECA_IEN */
+#define ECA_IEN_BUF0WMIND (0x1UL << 0) /**< New BitField */
+#define _ECA_IEN_BUF0WMIND_SHIFT 0 /**< Shift value for ECA_BUF0WMIND */
+#define _ECA_IEN_BUF0WMIND_MASK 0x1UL /**< Bit mask for ECA_BUF0WMIND */
+#define _ECA_IEN_BUF0WMIND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IEN */
+#define ECA_IEN_BUF0WMIND_DEFAULT (_ECA_IEN_BUF0WMIND_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_IEN */
+#define ECA_IEN_BUF1WMIND (0x1UL << 1) /**< New BitField */
+#define _ECA_IEN_BUF1WMIND_SHIFT 1 /**< Shift value for ECA_BUF1WMIND */
+#define _ECA_IEN_BUF1WMIND_MASK 0x2UL /**< Bit mask for ECA_BUF1WMIND */
+#define _ECA_IEN_BUF1WMIND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IEN */
+#define ECA_IEN_BUF1WMIND_DEFAULT (_ECA_IEN_BUF1WMIND_DEFAULT << 1) /**< Shifted mode DEFAULT for ECA_IEN */
+#define ECA_IEN_BUF0FULLIND (0x1UL << 2) /**< New BitField */
+#define _ECA_IEN_BUF0FULLIND_SHIFT 2 /**< Shift value for ECA_BUF0FULLIND */
+#define _ECA_IEN_BUF0FULLIND_MASK 0x4UL /**< Bit mask for ECA_BUF0FULLIND */
+#define _ECA_IEN_BUF0FULLIND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IEN */
+#define ECA_IEN_BUF0FULLIND_DEFAULT (_ECA_IEN_BUF0FULLIND_DEFAULT << 2) /**< Shifted mode DEFAULT for ECA_IEN */
+#define ECA_IEN_BUF1FULLIND (0x1UL << 3) /**< New BitField */
+#define _ECA_IEN_BUF1FULLIND_SHIFT 3 /**< Shift value for ECA_BUF1FULLIND */
+#define _ECA_IEN_BUF1FULLIND_MASK 0x8UL /**< Bit mask for ECA_BUF1FULLIND */
+#define _ECA_IEN_BUF1FULLIND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IEN */
+#define ECA_IEN_BUF1FULLIND_DEFAULT (_ECA_IEN_BUF1FULLIND_DEFAULT << 3) /**< Shifted mode DEFAULT for ECA_IEN */
+#define ECA_IEN_STARTTRIG (0x1UL << 4) /**< New BitField */
+#define _ECA_IEN_STARTTRIG_SHIFT 4 /**< Shift value for ECA_STARTTRIG */
+#define _ECA_IEN_STARTTRIG_MASK 0x10UL /**< Bit mask for ECA_STARTTRIG */
+#define _ECA_IEN_STARTTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IEN */
+#define ECA_IEN_STARTTRIG_DEFAULT (_ECA_IEN_STARTTRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for ECA_IEN */
+#define ECA_IEN_STOPTRIG (0x1UL << 5) /**< New BitField */
+#define _ECA_IEN_STOPTRIG_SHIFT 5 /**< Shift value for ECA_STOPTRIG */
+#define _ECA_IEN_STOPTRIG_MASK 0x20UL /**< Bit mask for ECA_STOPTRIG */
+#define _ECA_IEN_STOPTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IEN */
+#define ECA_IEN_STOPTRIG_DEFAULT (_ECA_IEN_STOPTRIG_DEFAULT << 5) /**< Shifted mode DEFAULT for ECA_IEN */
+#define ECA_IEN_CAPTURESTART (0x1UL << 6) /**< New BitField */
+#define _ECA_IEN_CAPTURESTART_SHIFT 6 /**< Shift value for ECA_CAPTURESTART */
+#define _ECA_IEN_CAPTURESTART_MASK 0x40UL /**< Bit mask for ECA_CAPTURESTART */
+#define _ECA_IEN_CAPTURESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IEN */
+#define ECA_IEN_CAPTURESTART_DEFAULT (_ECA_IEN_CAPTURESTART_DEFAULT << 6) /**< Shifted mode DEFAULT for ECA_IEN */
+#define ECA_IEN_CAPTUREEND (0x1UL << 7) /**< New BitField */
+#define _ECA_IEN_CAPTUREEND_SHIFT 7 /**< Shift value for ECA_CAPTUREEND */
+#define _ECA_IEN_CAPTUREEND_MASK 0x80UL /**< Bit mask for ECA_CAPTUREEND */
+#define _ECA_IEN_CAPTUREEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IEN */
+#define ECA_IEN_CAPTUREEND_DEFAULT (_ECA_IEN_CAPTUREEND_DEFAULT << 7) /**< Shifted mode DEFAULT for ECA_IEN */
+#define ECA_IEN_PLAYBACKSTART (0x1UL << 8) /**< New BitField */
+#define _ECA_IEN_PLAYBACKSTART_SHIFT 8 /**< Shift value for ECA_PLAYBACKSTART */
+#define _ECA_IEN_PLAYBACKSTART_MASK 0x100UL /**< Bit mask for ECA_PLAYBACKSTART */
+#define _ECA_IEN_PLAYBACKSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IEN */
+#define ECA_IEN_PLAYBACKSTART_DEFAULT (_ECA_IEN_PLAYBACKSTART_DEFAULT << 8) /**< Shifted mode DEFAULT for ECA_IEN */
+#define ECA_IEN_PLAYBACKEND (0x1UL << 9) /**< New BitField */
+#define _ECA_IEN_PLAYBACKEND_SHIFT 9 /**< Shift value for ECA_PLAYBACKEND */
+#define _ECA_IEN_PLAYBACKEND_MASK 0x200UL /**< Bit mask for ECA_PLAYBACKEND */
+#define _ECA_IEN_PLAYBACKEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IEN */
+#define ECA_IEN_PLAYBACKEND_DEFAULT (_ECA_IEN_PLAYBACKEND_DEFAULT << 9) /**< Shifted mode DEFAULT for ECA_IEN */
+#define ECA_IEN_EVENTCNTRCOMP (0x1UL << 10) /**< New BitField */
+#define _ECA_IEN_EVENTCNTRCOMP_SHIFT 10 /**< Shift value for ECA_EVENTCNTRCOMP */
+#define _ECA_IEN_EVENTCNTRCOMP_MASK 0x400UL /**< Bit mask for ECA_EVENTCNTRCOMP */
+#define _ECA_IEN_EVENTCNTRCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IEN */
+#define ECA_IEN_EVENTCNTRCOMP_DEFAULT (_ECA_IEN_EVENTCNTRCOMP_DEFAULT << 10) /**< Shifted mode DEFAULT for ECA_IEN */
+#define ECA_IEN_FIFOORERROR (0x1UL << 11) /**< New BitField */
+#define _ECA_IEN_FIFOORERROR_SHIFT 11 /**< Shift value for ECA_FIFOORERROR */
+#define _ECA_IEN_FIFOORERROR_MASK 0x800UL /**< Bit mask for ECA_FIFOORERROR */
+#define _ECA_IEN_FIFOORERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IEN */
+#define ECA_IEN_FIFOORERROR_DEFAULT (_ECA_IEN_FIFOORERROR_DEFAULT << 11) /**< Shifted mode DEFAULT for ECA_IEN */
+#define ECA_IEN_FIFOURERROR (0x1UL << 12) /**< New BitField */
+#define _ECA_IEN_FIFOURERROR_SHIFT 12 /**< Shift value for ECA_FIFOURERROR */
+#define _ECA_IEN_FIFOURERROR_MASK 0x1000UL /**< Bit mask for ECA_FIFOURERROR */
+#define _ECA_IEN_FIFOURERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IEN */
+#define ECA_IEN_FIFOURERROR_DEFAULT (_ECA_IEN_FIFOURERROR_DEFAULT << 12) /**< Shifted mode DEFAULT for ECA_IEN */
+#define ECA_IEN_DMABUSERROR (0x1UL << 13) /**< New BitField */
+#define _ECA_IEN_DMABUSERROR_SHIFT 13 /**< Shift value for ECA_DMABUSERROR */
+#define _ECA_IEN_DMABUSERROR_MASK 0x2000UL /**< Bit mask for ECA_DMABUSERROR */
+#define _ECA_IEN_DMABUSERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_IEN */
+#define ECA_IEN_DMABUSERROR_DEFAULT (_ECA_IEN_DMABUSERROR_DEFAULT << 13) /**< Shifted mode DEFAULT for ECA_IEN */
+
+/* Bit fields for ECA DMABUSERRORSTATUS */
+#define _ECA_DMABUSERRORSTATUS_RESETVALUE 0x00000000UL /**< Default value for ECA_DMABUSERRORSTATUS */
+#define _ECA_DMABUSERRORSTATUS_MASK 0xFFFFFFFFUL /**< Mask for ECA_DMABUSERRORSTATUS */
+#define _ECA_DMABUSERRORSTATUS_ADDR_SHIFT 0 /**< Shift value for ECA_ADDR */
+#define _ECA_DMABUSERRORSTATUS_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_ADDR */
+#define _ECA_DMABUSERRORSTATUS_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_DMABUSERRORSTATUS */
+#define ECA_DMABUSERRORSTATUS_ADDR_DEFAULT (_ECA_DMABUSERRORSTATUS_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_DMABUSERRORSTATUS*/
+
+/* Bit fields for ECA BUF_BASE */
+#define _ECA_BUF_BASE_RESETVALUE 0x00000000UL /**< Default value for ECA_BUF_BASE */
+#define _ECA_BUF_BASE_MASK 0xFFFFFFFFUL /**< Mask for ECA_BUF_BASE */
+#define _ECA_BUF_BASE_BASE_SHIFT 0 /**< Shift value for ECA_BASE */
+#define _ECA_BUF_BASE_BASE_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_BASE */
+#define _ECA_BUF_BASE_BASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_BUF_BASE */
+#define ECA_BUF_BASE_BASE_DEFAULT (_ECA_BUF_BASE_BASE_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_BUF_BASE */
+
+/* Bit fields for ECA BUF_LIMITOFFSET */
+#define _ECA_BUF_LIMITOFFSET_RESETVALUE 0x00000000UL /**< Default value for ECA_BUF_LIMITOFFSET */
+#define _ECA_BUF_LIMITOFFSET_MASK 0x0007FFFCUL /**< Mask for ECA_BUF_LIMITOFFSET */
+#define _ECA_BUF_LIMITOFFSET_OFFSET_SHIFT 2 /**< Shift value for ECA_OFFSET */
+#define _ECA_BUF_LIMITOFFSET_OFFSET_MASK 0x7FFFCUL /**< Bit mask for ECA_OFFSET */
+#define _ECA_BUF_LIMITOFFSET_OFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_BUF_LIMITOFFSET */
+#define ECA_BUF_LIMITOFFSET_OFFSET_DEFAULT (_ECA_BUF_LIMITOFFSET_OFFSET_DEFAULT << 2) /**< Shifted mode DEFAULT for ECA_BUF_LIMITOFFSET*/
+
+/* Bit fields for ECA BUF_WMOFFSET */
+#define _ECA_BUF_WMOFFSET_RESETVALUE 0x00000000UL /**< Default value for ECA_BUF_WMOFFSET */
+#define _ECA_BUF_WMOFFSET_MASK 0x0007FFFCUL /**< Mask for ECA_BUF_WMOFFSET */
+#define _ECA_BUF_WMOFFSET_OFFSET_SHIFT 2 /**< Shift value for ECA_OFFSET */
+#define _ECA_BUF_WMOFFSET_OFFSET_MASK 0x7FFFCUL /**< Bit mask for ECA_OFFSET */
+#define _ECA_BUF_WMOFFSET_OFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_BUF_WMOFFSET */
+#define ECA_BUF_WMOFFSET_OFFSET_DEFAULT (_ECA_BUF_WMOFFSET_OFFSET_DEFAULT << 2) /**< Shifted mode DEFAULT for ECA_BUF_WMOFFSET */
+
+/* Bit fields for ECA BUFPTRSTATUS */
+#define _ECA_BUFPTRSTATUS_RESETVALUE 0x00000000UL /**< Default value for ECA_BUFPTRSTATUS */
+#define _ECA_BUFPTRSTATUS_MASK 0xFFFFFFFFUL /**< Mask for ECA_BUFPTRSTATUS */
+#define _ECA_BUFPTRSTATUS_STATUS_SHIFT 0 /**< Shift value for ECA_STATUS */
+#define _ECA_BUFPTRSTATUS_STATUS_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_STATUS */
+#define _ECA_BUFPTRSTATUS_STATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_BUFPTRSTATUS */
+#define ECA_BUFPTRSTATUS_STATUS_DEFAULT (_ECA_BUFPTRSTATUS_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_BUFPTRSTATUS */
+
+/* Bit fields for ECA STARTTRIGCTRL */
+#define _ECA_STARTTRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for ECA_STARTTRIGCTRL */
+#define _ECA_STARTTRIGCTRL_MASK 0x0000001FUL /**< Mask for ECA_STARTTRIGCTRL */
+#define _ECA_STARTTRIGCTRL_TRACESEL_SHIFT 0 /**< Shift value for ECA_TRACESEL */
+#define _ECA_STARTTRIGCTRL_TRACESEL_MASK 0x7UL /**< Bit mask for ECA_TRACESEL */
+#define _ECA_STARTTRIGCTRL_TRACESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STARTTRIGCTRL */
+#define ECA_STARTTRIGCTRL_TRACESEL_DEFAULT (_ECA_STARTTRIGCTRL_TRACESEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_STARTTRIGCTRL */
+#define ECA_STARTTRIGCTRL_ENABLE (0x1UL << 3) /**< Enable */
+#define _ECA_STARTTRIGCTRL_ENABLE_SHIFT 3 /**< Shift value for ECA_ENABLE */
+#define _ECA_STARTTRIGCTRL_ENABLE_MASK 0x8UL /**< Bit mask for ECA_ENABLE */
+#define _ECA_STARTTRIGCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STARTTRIGCTRL */
+#define ECA_STARTTRIGCTRL_ENABLE_DEFAULT (_ECA_STARTTRIGCTRL_ENABLE_DEFAULT << 3) /**< Shifted mode DEFAULT for ECA_STARTTRIGCTRL */
+#define ECA_STARTTRIGCTRL_COMBMODE (0x1UL << 4) /**< Combination Mode */
+#define _ECA_STARTTRIGCTRL_COMBMODE_SHIFT 4 /**< Shift value for ECA_COMBMODE */
+#define _ECA_STARTTRIGCTRL_COMBMODE_MASK 0x10UL /**< Bit mask for ECA_COMBMODE */
+#define _ECA_STARTTRIGCTRL_COMBMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STARTTRIGCTRL */
+#define _ECA_STARTTRIGCTRL_COMBMODE_AND 0x00000000UL /**< Mode AND for ECA_STARTTRIGCTRL */
+#define _ECA_STARTTRIGCTRL_COMBMODE_OR 0x00000001UL /**< Mode OR for ECA_STARTTRIGCTRL */
+#define ECA_STARTTRIGCTRL_COMBMODE_DEFAULT (_ECA_STARTTRIGCTRL_COMBMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for ECA_STARTTRIGCTRL */
+#define ECA_STARTTRIGCTRL_COMBMODE_AND (_ECA_STARTTRIGCTRL_COMBMODE_AND << 4) /**< Shifted mode AND for ECA_STARTTRIGCTRL */
+#define ECA_STARTTRIGCTRL_COMBMODE_OR (_ECA_STARTTRIGCTRL_COMBMODE_OR << 4) /**< Shifted mode OR for ECA_STARTTRIGCTRL */
+
+/* Bit fields for ECA STOPTRIGCTRL */
+#define _ECA_STOPTRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for ECA_STOPTRIGCTRL */
+#define _ECA_STOPTRIGCTRL_MASK 0x0000001FUL /**< Mask for ECA_STOPTRIGCTRL */
+#define _ECA_STOPTRIGCTRL_TRACESEL_SHIFT 0 /**< Shift value for ECA_TRACESEL */
+#define _ECA_STOPTRIGCTRL_TRACESEL_MASK 0x7UL /**< Bit mask for ECA_TRACESEL */
+#define _ECA_STOPTRIGCTRL_TRACESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STOPTRIGCTRL */
+#define ECA_STOPTRIGCTRL_TRACESEL_DEFAULT (_ECA_STOPTRIGCTRL_TRACESEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_STOPTRIGCTRL */
+#define ECA_STOPTRIGCTRL_ENABLE (0x1UL << 3) /**< Enable */
+#define _ECA_STOPTRIGCTRL_ENABLE_SHIFT 3 /**< Shift value for ECA_ENABLE */
+#define _ECA_STOPTRIGCTRL_ENABLE_MASK 0x8UL /**< Bit mask for ECA_ENABLE */
+#define _ECA_STOPTRIGCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STOPTRIGCTRL */
+#define ECA_STOPTRIGCTRL_ENABLE_DEFAULT (_ECA_STOPTRIGCTRL_ENABLE_DEFAULT << 3) /**< Shifted mode DEFAULT for ECA_STOPTRIGCTRL */
+#define ECA_STOPTRIGCTRL_COMBMODE (0x1UL << 4) /**< Combination Mode */
+#define _ECA_STOPTRIGCTRL_COMBMODE_SHIFT 4 /**< Shift value for ECA_COMBMODE */
+#define _ECA_STOPTRIGCTRL_COMBMODE_MASK 0x10UL /**< Bit mask for ECA_COMBMODE */
+#define _ECA_STOPTRIGCTRL_COMBMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STOPTRIGCTRL */
+#define _ECA_STOPTRIGCTRL_COMBMODE_AND 0x00000000UL /**< Mode AND for ECA_STOPTRIGCTRL */
+#define _ECA_STOPTRIGCTRL_COMBMODE_OR 0x00000001UL /**< Mode OR for ECA_STOPTRIGCTRL */
+#define ECA_STOPTRIGCTRL_COMBMODE_DEFAULT (_ECA_STOPTRIGCTRL_COMBMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for ECA_STOPTRIGCTRL */
+#define ECA_STOPTRIGCTRL_COMBMODE_AND (_ECA_STOPTRIGCTRL_COMBMODE_AND << 4) /**< Shifted mode AND for ECA_STOPTRIGCTRL */
+#define ECA_STOPTRIGCTRL_COMBMODE_OR (_ECA_STOPTRIGCTRL_COMBMODE_OR << 4) /**< Shifted mode OR for ECA_STOPTRIGCTRL */
+
+/* Bit fields for ECA STARTTRIGENMASK */
+#define _ECA_STARTTRIGENMASK_RESETVALUE 0x00000000UL /**< Default value for ECA_STARTTRIGENMASK */
+#define _ECA_STARTTRIGENMASK_MASK 0xFFFFFFFFUL /**< Mask for ECA_STARTTRIGENMASK */
+#define _ECA_STARTTRIGENMASK_ENMASK_SHIFT 0 /**< Shift value for ECA_ENMASK */
+#define _ECA_STARTTRIGENMASK_ENMASK_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_ENMASK */
+#define _ECA_STARTTRIGENMASK_ENMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STARTTRIGENMASK */
+#define ECA_STARTTRIGENMASK_ENMASK_DEFAULT (_ECA_STARTTRIGENMASK_ENMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_STARTTRIGENMASK*/
+
+/* Bit fields for ECA STARTTRIGREDMASK */
+#define _ECA_STARTTRIGREDMASK_RESETVALUE 0x00000000UL /**< Default value for ECA_STARTTRIGREDMASK */
+#define _ECA_STARTTRIGREDMASK_MASK 0xFFFFFFFFUL /**< Mask for ECA_STARTTRIGREDMASK */
+#define _ECA_STARTTRIGREDMASK_REDMASK_SHIFT 0 /**< Shift value for ECA_REDMASK */
+#define _ECA_STARTTRIGREDMASK_REDMASK_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_REDMASK */
+#define _ECA_STARTTRIGREDMASK_REDMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STARTTRIGREDMASK */
+#define ECA_STARTTRIGREDMASK_REDMASK_DEFAULT (_ECA_STARTTRIGREDMASK_REDMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_STARTTRIGREDMASK*/
+
+/* Bit fields for ECA STARTTRIGFEDMASK */
+#define _ECA_STARTTRIGFEDMASK_RESETVALUE 0x00000000UL /**< Default value for ECA_STARTTRIGFEDMASK */
+#define _ECA_STARTTRIGFEDMASK_MASK 0xFFFFFFFFUL /**< Mask for ECA_STARTTRIGFEDMASK */
+#define _ECA_STARTTRIGFEDMASK_FEDMASK_SHIFT 0 /**< Shift value for ECA_FEDMASK */
+#define _ECA_STARTTRIGFEDMASK_FEDMASK_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_FEDMASK */
+#define _ECA_STARTTRIGFEDMASK_FEDMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STARTTRIGFEDMASK */
+#define ECA_STARTTRIGFEDMASK_FEDMASK_DEFAULT (_ECA_STARTTRIGFEDMASK_FEDMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_STARTTRIGFEDMASK*/
+
+/* Bit fields for ECA STARTTRIGLVL0MASK */
+#define _ECA_STARTTRIGLVL0MASK_RESETVALUE 0x00000000UL /**< Default value for ECA_STARTTRIGLVL0MASK */
+#define _ECA_STARTTRIGLVL0MASK_MASK 0xFFFFFFFFUL /**< Mask for ECA_STARTTRIGLVL0MASK */
+#define _ECA_STARTTRIGLVL0MASK_LVL0MASK_SHIFT 0 /**< Shift value for ECA_LVL0MASK */
+#define _ECA_STARTTRIGLVL0MASK_LVL0MASK_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_LVL0MASK */
+#define _ECA_STARTTRIGLVL0MASK_LVL0MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STARTTRIGLVL0MASK */
+#define ECA_STARTTRIGLVL0MASK_LVL0MASK_DEFAULT (_ECA_STARTTRIGLVL0MASK_LVL0MASK_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_STARTTRIGLVL0MASK*/
+
+/* Bit fields for ECA STARTTRIGLVL1MASK */
+#define _ECA_STARTTRIGLVL1MASK_RESETVALUE 0x00000000UL /**< Default value for ECA_STARTTRIGLVL1MASK */
+#define _ECA_STARTTRIGLVL1MASK_MASK 0xFFFFFFFFUL /**< Mask for ECA_STARTTRIGLVL1MASK */
+#define _ECA_STARTTRIGLVL1MASK_LVL1MASK_SHIFT 0 /**< Shift value for ECA_LVL1MASK */
+#define _ECA_STARTTRIGLVL1MASK_LVL1MASK_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_LVL1MASK */
+#define _ECA_STARTTRIGLVL1MASK_LVL1MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STARTTRIGLVL1MASK */
+#define ECA_STARTTRIGLVL1MASK_LVL1MASK_DEFAULT (_ECA_STARTTRIGLVL1MASK_LVL1MASK_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_STARTTRIGLVL1MASK*/
+
+/* Bit fields for ECA STOPTRIGENMASK */
+#define _ECA_STOPTRIGENMASK_RESETVALUE 0x00000000UL /**< Default value for ECA_STOPTRIGENMASK */
+#define _ECA_STOPTRIGENMASK_MASK 0xFFFFFFFFUL /**< Mask for ECA_STOPTRIGENMASK */
+#define _ECA_STOPTRIGENMASK_ENMASK_SHIFT 0 /**< Shift value for ECA_ENMASK */
+#define _ECA_STOPTRIGENMASK_ENMASK_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_ENMASK */
+#define _ECA_STOPTRIGENMASK_ENMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STOPTRIGENMASK */
+#define ECA_STOPTRIGENMASK_ENMASK_DEFAULT (_ECA_STOPTRIGENMASK_ENMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_STOPTRIGENMASK */
+
+/* Bit fields for ECA STOPTRIGREDMASK */
+#define _ECA_STOPTRIGREDMASK_RESETVALUE 0x00000000UL /**< Default value for ECA_STOPTRIGREDMASK */
+#define _ECA_STOPTRIGREDMASK_MASK 0xFFFFFFFFUL /**< Mask for ECA_STOPTRIGREDMASK */
+#define _ECA_STOPTRIGREDMASK_REDMASK_SHIFT 0 /**< Shift value for ECA_REDMASK */
+#define _ECA_STOPTRIGREDMASK_REDMASK_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_REDMASK */
+#define _ECA_STOPTRIGREDMASK_REDMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STOPTRIGREDMASK */
+#define ECA_STOPTRIGREDMASK_REDMASK_DEFAULT (_ECA_STOPTRIGREDMASK_REDMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_STOPTRIGREDMASK*/
+
+/* Bit fields for ECA STOPTRIGFEDMASK */
+#define _ECA_STOPTRIGFEDMASK_RESETVALUE 0x00000000UL /**< Default value for ECA_STOPTRIGFEDMASK */
+#define _ECA_STOPTRIGFEDMASK_MASK 0xFFFFFFFFUL /**< Mask for ECA_STOPTRIGFEDMASK */
+#define _ECA_STOPTRIGFEDMASK_FEDMASK_SHIFT 0 /**< Shift value for ECA_FEDMASK */
+#define _ECA_STOPTRIGFEDMASK_FEDMASK_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_FEDMASK */
+#define _ECA_STOPTRIGFEDMASK_FEDMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STOPTRIGFEDMASK */
+#define ECA_STOPTRIGFEDMASK_FEDMASK_DEFAULT (_ECA_STOPTRIGFEDMASK_FEDMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_STOPTRIGFEDMASK*/
+
+/* Bit fields for ECA STOPTRIGLVL0MASK */
+#define _ECA_STOPTRIGLVL0MASK_RESETVALUE 0x00000000UL /**< Default value for ECA_STOPTRIGLVL0MASK */
+#define _ECA_STOPTRIGLVL0MASK_MASK 0xFFFFFFFFUL /**< Mask for ECA_STOPTRIGLVL0MASK */
+#define _ECA_STOPTRIGLVL0MASK_LVL0MASK_SHIFT 0 /**< Shift value for ECA_LVL0MASK */
+#define _ECA_STOPTRIGLVL0MASK_LVL0MASK_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_LVL0MASK */
+#define _ECA_STOPTRIGLVL0MASK_LVL0MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STOPTRIGLVL0MASK */
+#define ECA_STOPTRIGLVL0MASK_LVL0MASK_DEFAULT (_ECA_STOPTRIGLVL0MASK_LVL0MASK_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_STOPTRIGLVL0MASK*/
+
+/* Bit fields for ECA STOPTRIGLVL1MASK */
+#define _ECA_STOPTRIGLVL1MASK_RESETVALUE 0x00000000UL /**< Default value for ECA_STOPTRIGLVL1MASK */
+#define _ECA_STOPTRIGLVL1MASK_MASK 0xFFFFFFFFUL /**< Mask for ECA_STOPTRIGLVL1MASK */
+#define _ECA_STOPTRIGLVL1MASK_LVL1MASK_SHIFT 0 /**< Shift value for ECA_LVL1MASK */
+#define _ECA_STOPTRIGLVL1MASK_LVL1MASK_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_LVL1MASK */
+#define _ECA_STOPTRIGLVL1MASK_LVL1MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_STOPTRIGLVL1MASK */
+#define ECA_STOPTRIGLVL1MASK_LVL1MASK_DEFAULT (_ECA_STOPTRIGLVL1MASK_LVL1MASK_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_STOPTRIGLVL1MASK*/
+
+/* Bit fields for ECA CAPTURECTRL */
+#define _ECA_CAPTURECTRL_RESETVALUE 0x00000501UL /**< Default value for ECA_CAPTURECTRL */
+#define _ECA_CAPTURECTRL_MASK 0x7FF7FFFFUL /**< Mask for ECA_CAPTURECTRL */
+#define _ECA_CAPTURECTRL_TRACESEL_SHIFT 0 /**< Shift value for ECA_TRACESEL */
+#define _ECA_CAPTURECTRL_TRACESEL_MASK 0xFFUL /**< Bit mask for ECA_TRACESEL */
+#define _ECA_CAPTURECTRL_TRACESEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ECA_CAPTURECTRL */
+#define ECA_CAPTURECTRL_TRACESEL_DEFAULT (_ECA_CAPTURECTRL_TRACESEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_CAPTURECTRL */
+#define _ECA_CAPTURECTRL_DATAWIDTH_SHIFT 8 /**< Shift value for ECA_DATAWIDTH */
+#define _ECA_CAPTURECTRL_DATAWIDTH_MASK 0x700UL /**< Bit mask for ECA_DATAWIDTH */
+#define _ECA_CAPTURECTRL_DATAWIDTH_DEFAULT 0x00000005UL /**< Mode DEFAULT for ECA_CAPTURECTRL */
+#define _ECA_CAPTURECTRL_DATAWIDTH_BIT1 0x00000000UL /**< Mode BIT1 for ECA_CAPTURECTRL */
+#define _ECA_CAPTURECTRL_DATAWIDTH_BIT2 0x00000001UL /**< Mode BIT2 for ECA_CAPTURECTRL */
+#define _ECA_CAPTURECTRL_DATAWIDTH_BIT4 0x00000002UL /**< Mode BIT4 for ECA_CAPTURECTRL */
+#define _ECA_CAPTURECTRL_DATAWIDTH_BIT8 0x00000003UL /**< Mode BIT8 for ECA_CAPTURECTRL */
+#define _ECA_CAPTURECTRL_DATAWIDTH_BIT16 0x00000004UL /**< Mode BIT16 for ECA_CAPTURECTRL */
+#define _ECA_CAPTURECTRL_DATAWIDTH_BIT32 0x00000005UL /**< Mode BIT32 for ECA_CAPTURECTRL */
+#define ECA_CAPTURECTRL_DATAWIDTH_DEFAULT (_ECA_CAPTURECTRL_DATAWIDTH_DEFAULT << 8) /**< Shifted mode DEFAULT for ECA_CAPTURECTRL */
+#define ECA_CAPTURECTRL_DATAWIDTH_BIT1 (_ECA_CAPTURECTRL_DATAWIDTH_BIT1 << 8) /**< Shifted mode BIT1 for ECA_CAPTURECTRL */
+#define ECA_CAPTURECTRL_DATAWIDTH_BIT2 (_ECA_CAPTURECTRL_DATAWIDTH_BIT2 << 8) /**< Shifted mode BIT2 for ECA_CAPTURECTRL */
+#define ECA_CAPTURECTRL_DATAWIDTH_BIT4 (_ECA_CAPTURECTRL_DATAWIDTH_BIT4 << 8) /**< Shifted mode BIT4 for ECA_CAPTURECTRL */
+#define ECA_CAPTURECTRL_DATAWIDTH_BIT8 (_ECA_CAPTURECTRL_DATAWIDTH_BIT8 << 8) /**< Shifted mode BIT8 for ECA_CAPTURECTRL */
+#define ECA_CAPTURECTRL_DATAWIDTH_BIT16 (_ECA_CAPTURECTRL_DATAWIDTH_BIT16 << 8) /**< Shifted mode BIT16 for ECA_CAPTURECTRL */
+#define ECA_CAPTURECTRL_DATAWIDTH_BIT32 (_ECA_CAPTURECTRL_DATAWIDTH_BIT32 << 8) /**< Shifted mode BIT32 for ECA_CAPTURECTRL */
+#define _ECA_CAPTURECTRL_DATAROTATESIZE_SHIFT 11 /**< Shift value for ECA_DATAROTATESIZE */
+#define _ECA_CAPTURECTRL_DATAROTATESIZE_MASK 0xF800UL /**< Bit mask for ECA_DATAROTATESIZE */
+#define _ECA_CAPTURECTRL_DATAROTATESIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CAPTURECTRL */
+#define ECA_CAPTURECTRL_DATAROTATESIZE_DEFAULT (_ECA_CAPTURECTRL_DATAROTATESIZE_DEFAULT << 11) /**< Shifted mode DEFAULT for ECA_CAPTURECTRL */
+#define ECA_CAPTURECTRL_STARTMODE (0x1UL << 16) /**< Start Mode */
+#define _ECA_CAPTURECTRL_STARTMODE_SHIFT 16 /**< Shift value for ECA_STARTMODE */
+#define _ECA_CAPTURECTRL_STARTMODE_MASK 0x10000UL /**< Bit mask for ECA_STARTMODE */
+#define _ECA_CAPTURECTRL_STARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CAPTURECTRL */
+#define _ECA_CAPTURECTRL_STARTMODE_MANUAL 0x00000000UL /**< Mode MANUAL for ECA_CAPTURECTRL */
+#define _ECA_CAPTURECTRL_STARTMODE_START_TRIGGER 0x00000001UL /**< Mode START_TRIGGER for ECA_CAPTURECTRL */
+#define ECA_CAPTURECTRL_STARTMODE_DEFAULT (_ECA_CAPTURECTRL_STARTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ECA_CAPTURECTRL */
+#define ECA_CAPTURECTRL_STARTMODE_MANUAL (_ECA_CAPTURECTRL_STARTMODE_MANUAL << 16) /**< Shifted mode MANUAL for ECA_CAPTURECTRL */
+#define ECA_CAPTURECTRL_STARTMODE_START_TRIGGER (_ECA_CAPTURECTRL_STARTMODE_START_TRIGGER << 16) /**< Shifted mode START_TRIGGER for ECA_CAPTURECTRL*/
+#define _ECA_CAPTURECTRL_STOPMODE_SHIFT 17 /**< Shift value for ECA_STOPMODE */
+#define _ECA_CAPTURECTRL_STOPMODE_MASK 0x60000UL /**< Bit mask for ECA_STOPMODE */
+#define _ECA_CAPTURECTRL_STOPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CAPTURECTRL */
+#define _ECA_CAPTURECTRL_STOPMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for ECA_CAPTURECTRL */
+#define _ECA_CAPTURECTRL_STOPMODE_BUF_FULL 0x00000001UL /**< Mode BUF_FULL for ECA_CAPTURECTRL */
+#define _ECA_CAPTURECTRL_STOPMODE_STOP_TRIGGER 0x00000002UL /**< Mode STOP_TRIGGER for ECA_CAPTURECTRL */
+#define _ECA_CAPTURECTRL_STOPMODE_STOP_TRIGGER_FULL 0x00000003UL /**< Mode STOP_TRIGGER_FULL for ECA_CAPTURECTRL */
+#define ECA_CAPTURECTRL_STOPMODE_DEFAULT (_ECA_CAPTURECTRL_STOPMODE_DEFAULT << 17) /**< Shifted mode DEFAULT for ECA_CAPTURECTRL */
+#define ECA_CAPTURECTRL_STOPMODE_CONTINUOUS (_ECA_CAPTURECTRL_STOPMODE_CONTINUOUS << 17) /**< Shifted mode CONTINUOUS for ECA_CAPTURECTRL */
+#define ECA_CAPTURECTRL_STOPMODE_BUF_FULL (_ECA_CAPTURECTRL_STOPMODE_BUF_FULL << 17) /**< Shifted mode BUF_FULL for ECA_CAPTURECTRL */
+#define ECA_CAPTURECTRL_STOPMODE_STOP_TRIGGER (_ECA_CAPTURECTRL_STOPMODE_STOP_TRIGGER << 17) /**< Shifted mode STOP_TRIGGER for ECA_CAPTURECTRL*/
+#define ECA_CAPTURECTRL_STOPMODE_STOP_TRIGGER_FULL (_ECA_CAPTURECTRL_STOPMODE_STOP_TRIGGER_FULL << 17) /**< Shifted mode STOP_TRIGGER_FULL for ECA_CAPTURECTRL*/
+#define _ECA_CAPTURECTRL_COND_SHIFT 20 /**< Shift value for ECA_COND */
+#define _ECA_CAPTURECTRL_COND_MASK 0x300000UL /**< Bit mask for ECA_COND */
+#define _ECA_CAPTURECTRL_COND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CAPTURECTRL */
+#define _ECA_CAPTURECTRL_COND_TIMED 0x00000000UL /**< Mode TIMED for ECA_CAPTURECTRL */
+#define _ECA_CAPTURECTRL_COND_START_TRIGGER 0x00000001UL /**< Mode START_TRIGGER for ECA_CAPTURECTRL */
+#define _ECA_CAPTURECTRL_COND_SLAVE 0x00000002UL /**< Mode SLAVE for ECA_CAPTURECTRL */
+#define ECA_CAPTURECTRL_COND_DEFAULT (_ECA_CAPTURECTRL_COND_DEFAULT << 20) /**< Shifted mode DEFAULT for ECA_CAPTURECTRL */
+#define ECA_CAPTURECTRL_COND_TIMED (_ECA_CAPTURECTRL_COND_TIMED << 20) /**< Shifted mode TIMED for ECA_CAPTURECTRL */
+#define ECA_CAPTURECTRL_COND_START_TRIGGER (_ECA_CAPTURECTRL_COND_START_TRIGGER << 20) /**< Shifted mode START_TRIGGER for ECA_CAPTURECTRL*/
+#define ECA_CAPTURECTRL_COND_SLAVE (_ECA_CAPTURECTRL_COND_SLAVE << 20) /**< Shifted mode SLAVE for ECA_CAPTURECTRL */
+#define ECA_CAPTURECTRL_STOPCONDPRI (0x1UL << 22) /**< Stop Condition Priority */
+#define _ECA_CAPTURECTRL_STOPCONDPRI_SHIFT 22 /**< Shift value for ECA_STOPCONDPRI */
+#define _ECA_CAPTURECTRL_STOPCONDPRI_MASK 0x400000UL /**< Bit mask for ECA_STOPCONDPRI */
+#define _ECA_CAPTURECTRL_STOPCONDPRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CAPTURECTRL */
+#define ECA_CAPTURECTRL_STOPCONDPRI_DEFAULT (_ECA_CAPTURECTRL_STOPCONDPRI_DEFAULT << 22) /**< Shifted mode DEFAULT for ECA_CAPTURECTRL */
+#define ECA_CAPTURECTRL_WRITEDIS (0x1UL << 23) /**< Write Memory Disable */
+#define _ECA_CAPTURECTRL_WRITEDIS_SHIFT 23 /**< Shift value for ECA_WRITEDIS */
+#define _ECA_CAPTURECTRL_WRITEDIS_MASK 0x800000UL /**< Bit mask for ECA_WRITEDIS */
+#define _ECA_CAPTURECTRL_WRITEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CAPTURECTRL */
+#define ECA_CAPTURECTRL_WRITEDIS_DEFAULT (_ECA_CAPTURECTRL_WRITEDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for ECA_CAPTURECTRL */
+#define ECA_CAPTURECTRL_DATAOUTEN (0x1UL << 24) /**< Port Interface Enable */
+#define _ECA_CAPTURECTRL_DATAOUTEN_SHIFT 24 /**< Shift value for ECA_DATAOUTEN */
+#define _ECA_CAPTURECTRL_DATAOUTEN_MASK 0x1000000UL /**< Bit mask for ECA_DATAOUTEN */
+#define _ECA_CAPTURECTRL_DATAOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CAPTURECTRL */
+#define ECA_CAPTURECTRL_DATAOUTEN_DEFAULT (_ECA_CAPTURECTRL_DATAOUTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for ECA_CAPTURECTRL */
+#define _ECA_CAPTURECTRL_DATAOUTDSHIFT_SHIFT 25 /**< Shift value for ECA_DATAOUTDSHIFT */
+#define _ECA_CAPTURECTRL_DATAOUTDSHIFT_MASK 0x7E000000UL /**< Bit mask for ECA_DATAOUTDSHIFT */
+#define _ECA_CAPTURECTRL_DATAOUTDSHIFT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CAPTURECTRL */
+#define ECA_CAPTURECTRL_DATAOUTDSHIFT_DEFAULT (_ECA_CAPTURECTRL_DATAOUTDSHIFT_DEFAULT << 25) /**< Shifted mode DEFAULT for ECA_CAPTURECTRL */
+
+/* Bit fields for ECA CAPTURESTARTDELAY */
+#define _ECA_CAPTURESTARTDELAY_RESETVALUE 0x00000000UL /**< Default value for ECA_CAPTURESTARTDELAY */
+#define _ECA_CAPTURESTARTDELAY_MASK 0xFFFFFFFFUL /**< Mask for ECA_CAPTURESTARTDELAY */
+#define _ECA_CAPTURESTARTDELAY_DELAY_SHIFT 0 /**< Shift value for ECA_DELAY */
+#define _ECA_CAPTURESTARTDELAY_DELAY_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_DELAY */
+#define _ECA_CAPTURESTARTDELAY_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CAPTURESTARTDELAY */
+#define ECA_CAPTURESTARTDELAY_DELAY_DEFAULT (_ECA_CAPTURESTARTDELAY_DELAY_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_CAPTURESTARTDELAY*/
+
+/* Bit fields for ECA CAPTURESTOPDELAY */
+#define _ECA_CAPTURESTOPDELAY_RESETVALUE 0x00000000UL /**< Default value for ECA_CAPTURESTOPDELAY */
+#define _ECA_CAPTURESTOPDELAY_MASK 0xFFFFFFFFUL /**< Mask for ECA_CAPTURESTOPDELAY */
+#define _ECA_CAPTURESTOPDELAY_DELAY_SHIFT 0 /**< Shift value for ECA_DELAY */
+#define _ECA_CAPTURESTOPDELAY_DELAY_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_DELAY */
+#define _ECA_CAPTURESTOPDELAY_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CAPTURESTOPDELAY */
+#define ECA_CAPTURESTOPDELAY_DELAY_DEFAULT (_ECA_CAPTURESTOPDELAY_DELAY_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_CAPTURESTOPDELAY*/
+
+/* Bit fields for ECA CAPTURERATECTRL */
+#define _ECA_CAPTURERATECTRL_RESETVALUE 0x00000000UL /**< Default value for ECA_CAPTURERATECTRL */
+#define _ECA_CAPTURERATECTRL_MASK 0x0000FFFFUL /**< Mask for ECA_CAPTURERATECTRL */
+#define _ECA_CAPTURERATECTRL_RATE_SHIFT 0 /**< Shift value for ECA_RATE */
+#define _ECA_CAPTURERATECTRL_RATE_MASK 0xFFFFUL /**< Bit mask for ECA_RATE */
+#define _ECA_CAPTURERATECTRL_RATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_CAPTURERATECTRL */
+#define ECA_CAPTURERATECTRL_RATE_DEFAULT (_ECA_CAPTURERATECTRL_RATE_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_CAPTURERATECTRL*/
+
+/* Bit fields for ECA PLAYBACKCTRL */
+#define _ECA_PLAYBACKCTRL_RESETVALUE 0x00000014UL /**< Default value for ECA_PLAYBACKCTRL */
+#define _ECA_PLAYBACKCTRL_MASK 0x0000001FUL /**< Mask for ECA_PLAYBACKCTRL */
+#define ECA_PLAYBACKCTRL_MODE (0x1UL << 0) /**< Playback Mode */
+#define _ECA_PLAYBACKCTRL_MODE_SHIFT 0 /**< Shift value for ECA_MODE */
+#define _ECA_PLAYBACKCTRL_MODE_MASK 0x1UL /**< Bit mask for ECA_MODE */
+#define _ECA_PLAYBACKCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_PLAYBACKCTRL */
+#define _ECA_PLAYBACKCTRL_MODE_SINGLE 0x00000000UL /**< Mode SINGLE for ECA_PLAYBACKCTRL */
+#define _ECA_PLAYBACKCTRL_MODE_LOOP 0x00000001UL /**< Mode LOOP for ECA_PLAYBACKCTRL */
+#define ECA_PLAYBACKCTRL_MODE_DEFAULT (_ECA_PLAYBACKCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_PLAYBACKCTRL */
+#define ECA_PLAYBACKCTRL_MODE_SINGLE (_ECA_PLAYBACKCTRL_MODE_SINGLE << 0) /**< Shifted mode SINGLE for ECA_PLAYBACKCTRL */
+#define ECA_PLAYBACKCTRL_MODE_LOOP (_ECA_PLAYBACKCTRL_MODE_LOOP << 0) /**< Shifted mode LOOP for ECA_PLAYBACKCTRL */
+#define ECA_PLAYBACKCTRL_COND (0x1UL << 1) /**< Playback Condition */
+#define _ECA_PLAYBACKCTRL_COND_SHIFT 1 /**< Shift value for ECA_COND */
+#define _ECA_PLAYBACKCTRL_COND_MASK 0x2UL /**< Bit mask for ECA_COND */
+#define _ECA_PLAYBACKCTRL_COND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_PLAYBACKCTRL */
+#define _ECA_PLAYBACKCTRL_COND_START_TRIGGER 0x00000000UL /**< Mode START_TRIGGER for ECA_PLAYBACKCTRL */
+#define _ECA_PLAYBACKCTRL_COND_TIMED 0x00000001UL /**< Mode TIMED for ECA_PLAYBACKCTRL */
+#define ECA_PLAYBACKCTRL_COND_DEFAULT (_ECA_PLAYBACKCTRL_COND_DEFAULT << 1) /**< Shifted mode DEFAULT for ECA_PLAYBACKCTRL */
+#define ECA_PLAYBACKCTRL_COND_START_TRIGGER (_ECA_PLAYBACKCTRL_COND_START_TRIGGER << 1) /**< Shifted mode START_TRIGGER for ECA_PLAYBACKCTRL*/
+#define ECA_PLAYBACKCTRL_COND_TIMED (_ECA_PLAYBACKCTRL_COND_TIMED << 1) /**< Shifted mode TIMED for ECA_PLAYBACKCTRL */
+#define _ECA_PLAYBACKCTRL_DATAWIDTH_SHIFT 2 /**< Shift value for ECA_DATAWIDTH */
+#define _ECA_PLAYBACKCTRL_DATAWIDTH_MASK 0x1CUL /**< Bit mask for ECA_DATAWIDTH */
+#define _ECA_PLAYBACKCTRL_DATAWIDTH_DEFAULT 0x00000005UL /**< Mode DEFAULT for ECA_PLAYBACKCTRL */
+#define _ECA_PLAYBACKCTRL_DATAWIDTH_BIT1 0x00000000UL /**< Mode BIT1 for ECA_PLAYBACKCTRL */
+#define _ECA_PLAYBACKCTRL_DATAWIDTH_BIT2 0x00000001UL /**< Mode BIT2 for ECA_PLAYBACKCTRL */
+#define _ECA_PLAYBACKCTRL_DATAWIDTH_BIT4 0x00000002UL /**< Mode BIT4 for ECA_PLAYBACKCTRL */
+#define _ECA_PLAYBACKCTRL_DATAWIDTH_BIT8 0x00000003UL /**< Mode BIT8 for ECA_PLAYBACKCTRL */
+#define _ECA_PLAYBACKCTRL_DATAWIDTH_BIT16 0x00000004UL /**< Mode BIT16 for ECA_PLAYBACKCTRL */
+#define _ECA_PLAYBACKCTRL_DATAWIDTH_BIT32 0x00000005UL /**< Mode BIT32 for ECA_PLAYBACKCTRL */
+#define ECA_PLAYBACKCTRL_DATAWIDTH_DEFAULT (_ECA_PLAYBACKCTRL_DATAWIDTH_DEFAULT << 2) /**< Shifted mode DEFAULT for ECA_PLAYBACKCTRL */
+#define ECA_PLAYBACKCTRL_DATAWIDTH_BIT1 (_ECA_PLAYBACKCTRL_DATAWIDTH_BIT1 << 2) /**< Shifted mode BIT1 for ECA_PLAYBACKCTRL */
+#define ECA_PLAYBACKCTRL_DATAWIDTH_BIT2 (_ECA_PLAYBACKCTRL_DATAWIDTH_BIT2 << 2) /**< Shifted mode BIT2 for ECA_PLAYBACKCTRL */
+#define ECA_PLAYBACKCTRL_DATAWIDTH_BIT4 (_ECA_PLAYBACKCTRL_DATAWIDTH_BIT4 << 2) /**< Shifted mode BIT4 for ECA_PLAYBACKCTRL */
+#define ECA_PLAYBACKCTRL_DATAWIDTH_BIT8 (_ECA_PLAYBACKCTRL_DATAWIDTH_BIT8 << 2) /**< Shifted mode BIT8 for ECA_PLAYBACKCTRL */
+#define ECA_PLAYBACKCTRL_DATAWIDTH_BIT16 (_ECA_PLAYBACKCTRL_DATAWIDTH_BIT16 << 2) /**< Shifted mode BIT16 for ECA_PLAYBACKCTRL */
+#define ECA_PLAYBACKCTRL_DATAWIDTH_BIT32 (_ECA_PLAYBACKCTRL_DATAWIDTH_BIT32 << 2) /**< Shifted mode BIT32 for ECA_PLAYBACKCTRL */
+
+/* Bit fields for ECA PLAYBACKRATECTRL */
+#define _ECA_PLAYBACKRATECTRL_RESETVALUE 0x00000000UL /**< Default value for ECA_PLAYBACKRATECTRL */
+#define _ECA_PLAYBACKRATECTRL_MASK 0x0000FFFFUL /**< Mask for ECA_PLAYBACKRATECTRL */
+#define _ECA_PLAYBACKRATECTRL_RATE_SHIFT 0 /**< Shift value for ECA_RATE */
+#define _ECA_PLAYBACKRATECTRL_RATE_MASK 0xFFFFUL /**< Bit mask for ECA_RATE */
+#define _ECA_PLAYBACKRATECTRL_RATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_PLAYBACKRATECTRL */
+#define ECA_PLAYBACKRATECTRL_RATE_DEFAULT (_ECA_PLAYBACKRATECTRL_RATE_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_PLAYBACKRATECTRL*/
+
+/* Bit fields for ECA EVENTCNTRCTRL */
+#define _ECA_EVENTCNTRCTRL_RESETVALUE 0x00000000UL /**< Default value for ECA_EVENTCNTRCTRL */
+#define _ECA_EVENTCNTRCTRL_MASK 0x0000001FUL /**< Mask for ECA_EVENTCNTRCTRL */
+#define ECA_EVENTCNTRCTRL_STARTMODE (0x1UL << 0) /**< Start Mode */
+#define _ECA_EVENTCNTRCTRL_STARTMODE_SHIFT 0 /**< Shift value for ECA_STARTMODE */
+#define _ECA_EVENTCNTRCTRL_STARTMODE_MASK 0x1UL /**< Bit mask for ECA_STARTMODE */
+#define _ECA_EVENTCNTRCTRL_STARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_EVENTCNTRCTRL */
+#define _ECA_EVENTCNTRCTRL_STARTMODE_MANUAL 0x00000000UL /**< Mode MANUAL for ECA_EVENTCNTRCTRL */
+#define _ECA_EVENTCNTRCTRL_STARTMODE_START_TRIGGER 0x00000001UL /**< Mode START_TRIGGER for ECA_EVENTCNTRCTRL */
+#define ECA_EVENTCNTRCTRL_STARTMODE_DEFAULT (_ECA_EVENTCNTRCTRL_STARTMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_EVENTCNTRCTRL */
+#define ECA_EVENTCNTRCTRL_STARTMODE_MANUAL (_ECA_EVENTCNTRCTRL_STARTMODE_MANUAL << 0) /**< Shifted mode MANUAL for ECA_EVENTCNTRCTRL */
+#define ECA_EVENTCNTRCTRL_STARTMODE_START_TRIGGER (_ECA_EVENTCNTRCTRL_STARTMODE_START_TRIGGER << 0) /**< Shifted mode START_TRIGGER for ECA_EVENTCNTRCTRL*/
+#define _ECA_EVENTCNTRCTRL_STOPMODE_SHIFT 1 /**< Shift value for ECA_STOPMODE */
+#define _ECA_EVENTCNTRCTRL_STOPMODE_MASK 0x6UL /**< Bit mask for ECA_STOPMODE */
+#define _ECA_EVENTCNTRCTRL_STOPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_EVENTCNTRCTRL */
+#define _ECA_EVENTCNTRCTRL_STOPMODE_MANUAL 0x00000000UL /**< Mode MANUAL for ECA_EVENTCNTRCTRL */
+#define _ECA_EVENTCNTRCTRL_STOPMODE_STOP_TRIGGER 0x00000001UL /**< Mode STOP_TRIGGER for ECA_EVENTCNTRCTRL */
+#define _ECA_EVENTCNTRCTRL_STOPMODE_COMPARE 0x00000002UL /**< Mode COMPARE for ECA_EVENTCNTRCTRL */
+#define ECA_EVENTCNTRCTRL_STOPMODE_DEFAULT (_ECA_EVENTCNTRCTRL_STOPMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for ECA_EVENTCNTRCTRL */
+#define ECA_EVENTCNTRCTRL_STOPMODE_MANUAL (_ECA_EVENTCNTRCTRL_STOPMODE_MANUAL << 1) /**< Shifted mode MANUAL for ECA_EVENTCNTRCTRL */
+#define ECA_EVENTCNTRCTRL_STOPMODE_STOP_TRIGGER (_ECA_EVENTCNTRCTRL_STOPMODE_STOP_TRIGGER << 1) /**< Shifted mode STOP_TRIGGER for ECA_EVENTCNTRCTRL*/
+#define ECA_EVENTCNTRCTRL_STOPMODE_COMPARE (_ECA_EVENTCNTRCTRL_STOPMODE_COMPARE << 1) /**< Shifted mode COMPARE for ECA_EVENTCNTRCTRL */
+#define _ECA_EVENTCNTRCTRL_COUNTMODE_SHIFT 3 /**< Shift value for ECA_COUNTMODE */
+#define _ECA_EVENTCNTRCTRL_COUNTMODE_MASK 0x18UL /**< Bit mask for ECA_COUNTMODE */
+#define _ECA_EVENTCNTRCTRL_COUNTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_EVENTCNTRCTRL */
+#define _ECA_EVENTCNTRCTRL_COUNTMODE_ALWAYS 0x00000000UL /**< Mode ALWAYS for ECA_EVENTCNTRCTRL */
+#define _ECA_EVENTCNTRCTRL_COUNTMODE_START_TRIGGER 0x00000001UL /**< Mode START_TRIGGER for ECA_EVENTCNTRCTRL */
+#define _ECA_EVENTCNTRCTRL_COUNTMODE_STOP_TRIGGER 0x00000002UL /**< Mode STOP_TRIGGER for ECA_EVENTCNTRCTRL */
+#define _ECA_EVENTCNTRCTRL_COUNTMODE_ALL_TRIGGER 0x00000003UL /**< Mode ALL_TRIGGER for ECA_EVENTCNTRCTRL */
+#define ECA_EVENTCNTRCTRL_COUNTMODE_DEFAULT (_ECA_EVENTCNTRCTRL_COUNTMODE_DEFAULT << 3) /**< Shifted mode DEFAULT for ECA_EVENTCNTRCTRL */
+#define ECA_EVENTCNTRCTRL_COUNTMODE_ALWAYS (_ECA_EVENTCNTRCTRL_COUNTMODE_ALWAYS << 3) /**< Shifted mode ALWAYS for ECA_EVENTCNTRCTRL */
+#define ECA_EVENTCNTRCTRL_COUNTMODE_START_TRIGGER (_ECA_EVENTCNTRCTRL_COUNTMODE_START_TRIGGER << 3) /**< Shifted mode START_TRIGGER for ECA_EVENTCNTRCTRL*/
+#define ECA_EVENTCNTRCTRL_COUNTMODE_STOP_TRIGGER (_ECA_EVENTCNTRCTRL_COUNTMODE_STOP_TRIGGER << 3) /**< Shifted mode STOP_TRIGGER for ECA_EVENTCNTRCTRL*/
+#define ECA_EVENTCNTRCTRL_COUNTMODE_ALL_TRIGGER (_ECA_EVENTCNTRCTRL_COUNTMODE_ALL_TRIGGER << 3) /**< Shifted mode ALL_TRIGGER for ECA_EVENTCNTRCTRL*/
+
+/* Bit fields for ECA EVENTCNTRCOMPARE */
+#define _ECA_EVENTCNTRCOMPARE_RESETVALUE 0x00000000UL /**< Default value for ECA_EVENTCNTRCOMPARE */
+#define _ECA_EVENTCNTRCOMPARE_MASK 0xFFFFFFFFUL /**< Mask for ECA_EVENTCNTRCOMPARE */
+#define _ECA_EVENTCNTRCOMPARE_COMPARE_SHIFT 0 /**< Shift value for ECA_COMPARE */
+#define _ECA_EVENTCNTRCOMPARE_COMPARE_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_COMPARE */
+#define _ECA_EVENTCNTRCOMPARE_COMPARE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_EVENTCNTRCOMPARE */
+#define ECA_EVENTCNTRCOMPARE_COMPARE_DEFAULT (_ECA_EVENTCNTRCOMPARE_COMPARE_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_EVENTCNTRCOMPARE*/
+
+/* Bit fields for ECA EVENTCNTRSTATUS */
+#define _ECA_EVENTCNTRSTATUS_RESETVALUE 0x00000000UL /**< Default value for ECA_EVENTCNTRSTATUS */
+#define _ECA_EVENTCNTRSTATUS_MASK 0xFFFFFFFFUL /**< Mask for ECA_EVENTCNTRSTATUS */
+#define _ECA_EVENTCNTRSTATUS_STATUS_SHIFT 0 /**< Shift value for ECA_STATUS */
+#define _ECA_EVENTCNTRSTATUS_STATUS_MASK 0xFFFFFFFFUL /**< Bit mask for ECA_STATUS */
+#define _ECA_EVENTCNTRSTATUS_STATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECA_EVENTCNTRSTATUS */
+#define ECA_EVENTCNTRSTATUS_STATUS_DEFAULT (_ECA_EVENTCNTRSTATUS_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for ECA_EVENTCNTRSTATUS*/
+
+/** @} End of group EFR32MG24_ECA_BitFields */
+/** @} End of group EFR32MG24_ECA */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_ECA_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_ecaifadc.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_ecaifadc.h
new file mode 100644
index 00000000..2d513b40
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_ecaifadc.h
@@ -0,0 +1,134 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 ECAIFADC register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_ECAIFADC_H
+#define EFR32MG24_ECAIFADC_H
+#define ECAIFADC_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_ECAIFADC ECAIFADC
+ * @{
+ * @brief EFR32MG24 ECAIFADC Register Declaration.
+ *****************************************************************************/
+
+/** ECAIFADC Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< New Register */
+ __IOM uint32_t EN; /**< Enable Register */
+ __IOM uint32_t CTRL; /**< Control Register */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+ __IM uint32_t STATUS; /**< Status Register */
+ uint32_t RESERVED1[1019U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< New Register */
+ __IOM uint32_t EN_SET; /**< Enable Register */
+ __IOM uint32_t CTRL_SET; /**< Control Register */
+ uint32_t RESERVED2[1U]; /**< Reserved for future use */
+ __IM uint32_t STATUS_SET; /**< Status Register */
+ uint32_t RESERVED3[1019U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< New Register */
+ __IOM uint32_t EN_CLR; /**< Enable Register */
+ __IOM uint32_t CTRL_CLR; /**< Control Register */
+ uint32_t RESERVED4[1U]; /**< Reserved for future use */
+ __IM uint32_t STATUS_CLR; /**< Status Register */
+ uint32_t RESERVED5[1019U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< New Register */
+ __IOM uint32_t EN_TGL; /**< Enable Register */
+ __IOM uint32_t CTRL_TGL; /**< Control Register */
+ uint32_t RESERVED6[1U]; /**< Reserved for future use */
+ __IM uint32_t STATUS_TGL; /**< Status Register */
+} ECAIFADC_TypeDef;
+/** @} End of group EFR32MG24_ECAIFADC */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_ECAIFADC
+ * @{
+ * @defgroup EFR32MG24_ECAIFADC_BitFields ECAIFADC Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for ECAIFADC IPVERSION */
+#define _ECAIFADC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for ECAIFADC_IPVERSION */
+#define _ECAIFADC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ECAIFADC_IPVERSION */
+#define _ECAIFADC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ECAIFADC_IPVERSION */
+#define _ECAIFADC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ECAIFADC_IPVERSION */
+#define _ECAIFADC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for ECAIFADC_IPVERSION */
+#define ECAIFADC_IPVERSION_IPVERSION_DEFAULT (_ECAIFADC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ECAIFADC_IPVERSION */
+
+/* Bit fields for ECAIFADC EN */
+#define _ECAIFADC_EN_RESETVALUE 0x00000000UL /**< Default value for ECAIFADC_EN */
+#define _ECAIFADC_EN_MASK 0x00000001UL /**< Mask for ECAIFADC_EN */
+#define ECAIFADC_EN_EN (0x1UL << 0) /**< IFADC Debug Enable */
+#define _ECAIFADC_EN_EN_SHIFT 0 /**< Shift value for ECAIFADC_EN */
+#define _ECAIFADC_EN_EN_MASK 0x1UL /**< Bit mask for ECAIFADC_EN */
+#define _ECAIFADC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECAIFADC_EN */
+#define ECAIFADC_EN_EN_DEFAULT (_ECAIFADC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ECAIFADC_EN */
+
+/* Bit fields for ECAIFADC CTRL */
+#define _ECAIFADC_CTRL_RESETVALUE 0x00000000UL /**< Default value for ECAIFADC_CTRL */
+#define _ECAIFADC_CTRL_MASK 0x00000007UL /**< Mask for ECAIFADC_CTRL */
+#define ECAIFADC_CTRL_MODE (0x1UL << 0) /**< Mode */
+#define _ECAIFADC_CTRL_MODE_SHIFT 0 /**< Shift value for ECAIFADC_MODE */
+#define _ECAIFADC_CTRL_MODE_MASK 0x1UL /**< Bit mask for ECAIFADC_MODE */
+#define _ECAIFADC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECAIFADC_CTRL */
+#define _ECAIFADC_CTRL_MODE_MP 0x00000000UL /**< Mode MP for ECAIFADC_CTRL */
+#define _ECAIFADC_CTRL_MODE_IQ 0x00000001UL /**< Mode IQ for ECAIFADC_CTRL */
+#define ECAIFADC_CTRL_MODE_DEFAULT (_ECAIFADC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ECAIFADC_CTRL */
+#define ECAIFADC_CTRL_MODE_MP (_ECAIFADC_CTRL_MODE_MP << 0) /**< Shifted mode MP for ECAIFADC_CTRL */
+#define ECAIFADC_CTRL_MODE_IQ (_ECAIFADC_CTRL_MODE_IQ << 0) /**< Shifted mode IQ for ECAIFADC_CTRL */
+#define _ECAIFADC_CTRL_IQSEL_SHIFT 1 /**< Shift value for ECAIFADC_IQSEL */
+#define _ECAIFADC_CTRL_IQSEL_MASK 0x6UL /**< Bit mask for ECAIFADC_IQSEL */
+#define _ECAIFADC_CTRL_IQSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECAIFADC_CTRL */
+#define _ECAIFADC_CTRL_IQSEL_NA 0x00000000UL /**< Mode NA for ECAIFADC_CTRL */
+#define _ECAIFADC_CTRL_IQSEL_IONLY 0x00000001UL /**< Mode IONLY for ECAIFADC_CTRL */
+#define _ECAIFADC_CTRL_IQSEL_QONLY 0x00000002UL /**< Mode QONLY for ECAIFADC_CTRL */
+#define _ECAIFADC_CTRL_IQSEL_IANDQ 0x00000003UL /**< Mode IANDQ for ECAIFADC_CTRL */
+#define ECAIFADC_CTRL_IQSEL_DEFAULT (_ECAIFADC_CTRL_IQSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for ECAIFADC_CTRL */
+#define ECAIFADC_CTRL_IQSEL_NA (_ECAIFADC_CTRL_IQSEL_NA << 1) /**< Shifted mode NA for ECAIFADC_CTRL */
+#define ECAIFADC_CTRL_IQSEL_IONLY (_ECAIFADC_CTRL_IQSEL_IONLY << 1) /**< Shifted mode IONLY for ECAIFADC_CTRL */
+#define ECAIFADC_CTRL_IQSEL_QONLY (_ECAIFADC_CTRL_IQSEL_QONLY << 1) /**< Shifted mode QONLY for ECAIFADC_CTRL */
+#define ECAIFADC_CTRL_IQSEL_IANDQ (_ECAIFADC_CTRL_IQSEL_IANDQ << 1) /**< Shifted mode IANDQ for ECAIFADC_CTRL */
+
+/* Bit fields for ECAIFADC STATUS */
+#define _ECAIFADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for ECAIFADC_STATUS */
+#define _ECAIFADC_STATUS_MASK 0x00000001UL /**< Mask for ECAIFADC_STATUS */
+#define ECAIFADC_STATUS_OVERFLOW (0x1UL << 0) /**< Capture Overflow */
+#define _ECAIFADC_STATUS_OVERFLOW_SHIFT 0 /**< Shift value for ECAIFADC_OVERFLOW */
+#define _ECAIFADC_STATUS_OVERFLOW_MASK 0x1UL /**< Bit mask for ECAIFADC_OVERFLOW */
+#define _ECAIFADC_STATUS_OVERFLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for ECAIFADC_STATUS */
+#define ECAIFADC_STATUS_OVERFLOW_DEFAULT (_ECAIFADC_STATUS_OVERFLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for ECAIFADC_STATUS */
+
+/** @} End of group EFR32MG24_ECAIFADC_BitFields */
+/** @} End of group EFR32MG24_ECAIFADC */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_ECAIFADC_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_emu.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_emu.h
new file mode 100644
index 00000000..90a1693e
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_emu.h
@@ -0,0 +1,803 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 EMU register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_EMU_H
+#define EFR32MG24_EMU_H
+#define EMU_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_EMU EMU
+ * @{
+ * @brief EFR32MG24 EMU Register Declaration.
+ *****************************************************************************/
+
+/** EMU Register Declaration. */
+typedef struct {
+ uint32_t RESERVED0[4U]; /**< Reserved for future use */
+ __IOM uint32_t DECBOD; /**< DECOUPLE LVBOD Control register */
+ uint32_t RESERVED1[3U]; /**< Reserved for future use */
+ __IOM uint32_t BOD3SENSE; /**< BOD3SENSE Control register */
+ uint32_t RESERVED2[6U]; /**< Reserved for future use */
+ __IOM uint32_t VREGVDDCMPCTRL; /**< DC-DC VREGVDD Comparator Control Register */
+ __IOM uint32_t PD1PARETCTRL; /**< PD1 Partial Retention Control */
+ uint32_t RESERVED3[6U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION; /**< IP Version */
+ __IOM uint32_t LOCK; /**< EMU Configuration lock register */
+ __IOM uint32_t IF; /**< Interrupt Flags */
+ __IOM uint32_t IEN; /**< Interrupt Enables */
+ __IOM uint32_t EM4CTRL; /**< EM4 Control */
+ __IOM uint32_t CMD; /**< EMU Command register */
+ __IOM uint32_t CTRL; /**< EMU Control register */
+ __IOM uint32_t TEMPLIMITS; /**< EMU Temperature thresholds */
+ uint32_t RESERVED4[2U]; /**< Reserved for future use */
+ __IM uint32_t STATUS; /**< EMU Status register */
+ __IM uint32_t TEMP; /**< Temperature */
+ uint32_t RESERVED5[1U]; /**< Reserved for future use */
+ __IOM uint32_t RSTCTRL; /**< Reset Management Control register */
+ __IM uint32_t RSTCAUSE; /**< Reset cause */
+ uint32_t RESERVED6[2U]; /**< Reserved for future use */
+ __IOM uint32_t DGIF; /**< Interrupt Flags Debug */
+ __IOM uint32_t DGIEN; /**< Interrupt Enables Debug */
+ __IOM uint32_t SEQIF; /**< Interrupt Flags Sequencer */
+ __IOM uint32_t SEQIEN; /**< Interrupt Enables Sequencer */
+ uint32_t RESERVED7[4U]; /**< Reserved for future use */
+ uint32_t RESERVED8[1U]; /**< Reserved for future use */
+ uint32_t RESERVED9[15U]; /**< Reserved for future use */
+ __IOM uint32_t EFPIF; /**< EFP Interrupt Register */
+ __IOM uint32_t EFPIEN; /**< EFP Interrupt Enable Register */
+ uint32_t RESERVED10[14U]; /**< Reserved for future use */
+ uint32_t RESERVED11[1U]; /**< Reserved for future use */
+ uint32_t RESERVED12[18U]; /**< Reserved for future use */
+ uint32_t RESERVED13[1U]; /**< Reserved for future use */
+ uint32_t RESERVED14[924U]; /**< Reserved for future use */
+ uint32_t RESERVED15[4U]; /**< Reserved for future use */
+ __IOM uint32_t DECBOD_SET; /**< DECOUPLE LVBOD Control register */
+ uint32_t RESERVED16[3U]; /**< Reserved for future use */
+ __IOM uint32_t BOD3SENSE_SET; /**< BOD3SENSE Control register */
+ uint32_t RESERVED17[6U]; /**< Reserved for future use */
+ __IOM uint32_t VREGVDDCMPCTRL_SET; /**< DC-DC VREGVDD Comparator Control Register */
+ __IOM uint32_t PD1PARETCTRL_SET; /**< PD1 Partial Retention Control */
+ uint32_t RESERVED18[6U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP Version */
+ __IOM uint32_t LOCK_SET; /**< EMU Configuration lock register */
+ __IOM uint32_t IF_SET; /**< Interrupt Flags */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enables */
+ __IOM uint32_t EM4CTRL_SET; /**< EM4 Control */
+ __IOM uint32_t CMD_SET; /**< EMU Command register */
+ __IOM uint32_t CTRL_SET; /**< EMU Control register */
+ __IOM uint32_t TEMPLIMITS_SET; /**< EMU Temperature thresholds */
+ uint32_t RESERVED19[2U]; /**< Reserved for future use */
+ __IM uint32_t STATUS_SET; /**< EMU Status register */
+ __IM uint32_t TEMP_SET; /**< Temperature */
+ uint32_t RESERVED20[1U]; /**< Reserved for future use */
+ __IOM uint32_t RSTCTRL_SET; /**< Reset Management Control register */
+ __IM uint32_t RSTCAUSE_SET; /**< Reset cause */
+ uint32_t RESERVED21[2U]; /**< Reserved for future use */
+ __IOM uint32_t DGIF_SET; /**< Interrupt Flags Debug */
+ __IOM uint32_t DGIEN_SET; /**< Interrupt Enables Debug */
+ __IOM uint32_t SEQIF_SET; /**< Interrupt Flags Sequencer */
+ __IOM uint32_t SEQIEN_SET; /**< Interrupt Enables Sequencer */
+ uint32_t RESERVED22[4U]; /**< Reserved for future use */
+ uint32_t RESERVED23[1U]; /**< Reserved for future use */
+ uint32_t RESERVED24[15U]; /**< Reserved for future use */
+ __IOM uint32_t EFPIF_SET; /**< EFP Interrupt Register */
+ __IOM uint32_t EFPIEN_SET; /**< EFP Interrupt Enable Register */
+ uint32_t RESERVED25[14U]; /**< Reserved for future use */
+ uint32_t RESERVED26[1U]; /**< Reserved for future use */
+ uint32_t RESERVED27[18U]; /**< Reserved for future use */
+ uint32_t RESERVED28[1U]; /**< Reserved for future use */
+ uint32_t RESERVED29[924U]; /**< Reserved for future use */
+ uint32_t RESERVED30[4U]; /**< Reserved for future use */
+ __IOM uint32_t DECBOD_CLR; /**< DECOUPLE LVBOD Control register */
+ uint32_t RESERVED31[3U]; /**< Reserved for future use */
+ __IOM uint32_t BOD3SENSE_CLR; /**< BOD3SENSE Control register */
+ uint32_t RESERVED32[6U]; /**< Reserved for future use */
+ __IOM uint32_t VREGVDDCMPCTRL_CLR; /**< DC-DC VREGVDD Comparator Control Register */
+ __IOM uint32_t PD1PARETCTRL_CLR; /**< PD1 Partial Retention Control */
+ uint32_t RESERVED33[6U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP Version */
+ __IOM uint32_t LOCK_CLR; /**< EMU Configuration lock register */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flags */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enables */
+ __IOM uint32_t EM4CTRL_CLR; /**< EM4 Control */
+ __IOM uint32_t CMD_CLR; /**< EMU Command register */
+ __IOM uint32_t CTRL_CLR; /**< EMU Control register */
+ __IOM uint32_t TEMPLIMITS_CLR; /**< EMU Temperature thresholds */
+ uint32_t RESERVED34[2U]; /**< Reserved for future use */
+ __IM uint32_t STATUS_CLR; /**< EMU Status register */
+ __IM uint32_t TEMP_CLR; /**< Temperature */
+ uint32_t RESERVED35[1U]; /**< Reserved for future use */
+ __IOM uint32_t RSTCTRL_CLR; /**< Reset Management Control register */
+ __IM uint32_t RSTCAUSE_CLR; /**< Reset cause */
+ uint32_t RESERVED36[2U]; /**< Reserved for future use */
+ __IOM uint32_t DGIF_CLR; /**< Interrupt Flags Debug */
+ __IOM uint32_t DGIEN_CLR; /**< Interrupt Enables Debug */
+ __IOM uint32_t SEQIF_CLR; /**< Interrupt Flags Sequencer */
+ __IOM uint32_t SEQIEN_CLR; /**< Interrupt Enables Sequencer */
+ uint32_t RESERVED37[4U]; /**< Reserved for future use */
+ uint32_t RESERVED38[1U]; /**< Reserved for future use */
+ uint32_t RESERVED39[15U]; /**< Reserved for future use */
+ __IOM uint32_t EFPIF_CLR; /**< EFP Interrupt Register */
+ __IOM uint32_t EFPIEN_CLR; /**< EFP Interrupt Enable Register */
+ uint32_t RESERVED40[14U]; /**< Reserved for future use */
+ uint32_t RESERVED41[1U]; /**< Reserved for future use */
+ uint32_t RESERVED42[18U]; /**< Reserved for future use */
+ uint32_t RESERVED43[1U]; /**< Reserved for future use */
+ uint32_t RESERVED44[924U]; /**< Reserved for future use */
+ uint32_t RESERVED45[4U]; /**< Reserved for future use */
+ __IOM uint32_t DECBOD_TGL; /**< DECOUPLE LVBOD Control register */
+ uint32_t RESERVED46[3U]; /**< Reserved for future use */
+ __IOM uint32_t BOD3SENSE_TGL; /**< BOD3SENSE Control register */
+ uint32_t RESERVED47[6U]; /**< Reserved for future use */
+ __IOM uint32_t VREGVDDCMPCTRL_TGL; /**< DC-DC VREGVDD Comparator Control Register */
+ __IOM uint32_t PD1PARETCTRL_TGL; /**< PD1 Partial Retention Control */
+ uint32_t RESERVED48[6U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP Version */
+ __IOM uint32_t LOCK_TGL; /**< EMU Configuration lock register */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flags */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enables */
+ __IOM uint32_t EM4CTRL_TGL; /**< EM4 Control */
+ __IOM uint32_t CMD_TGL; /**< EMU Command register */
+ __IOM uint32_t CTRL_TGL; /**< EMU Control register */
+ __IOM uint32_t TEMPLIMITS_TGL; /**< EMU Temperature thresholds */
+ uint32_t RESERVED49[2U]; /**< Reserved for future use */
+ __IM uint32_t STATUS_TGL; /**< EMU Status register */
+ __IM uint32_t TEMP_TGL; /**< Temperature */
+ uint32_t RESERVED50[1U]; /**< Reserved for future use */
+ __IOM uint32_t RSTCTRL_TGL; /**< Reset Management Control register */
+ __IM uint32_t RSTCAUSE_TGL; /**< Reset cause */
+ uint32_t RESERVED51[2U]; /**< Reserved for future use */
+ __IOM uint32_t DGIF_TGL; /**< Interrupt Flags Debug */
+ __IOM uint32_t DGIEN_TGL; /**< Interrupt Enables Debug */
+ __IOM uint32_t SEQIF_TGL; /**< Interrupt Flags Sequencer */
+ __IOM uint32_t SEQIEN_TGL; /**< Interrupt Enables Sequencer */
+ uint32_t RESERVED52[4U]; /**< Reserved for future use */
+ uint32_t RESERVED53[1U]; /**< Reserved for future use */
+ uint32_t RESERVED54[15U]; /**< Reserved for future use */
+ __IOM uint32_t EFPIF_TGL; /**< EFP Interrupt Register */
+ __IOM uint32_t EFPIEN_TGL; /**< EFP Interrupt Enable Register */
+ uint32_t RESERVED55[14U]; /**< Reserved for future use */
+ uint32_t RESERVED56[1U]; /**< Reserved for future use */
+ uint32_t RESERVED57[18U]; /**< Reserved for future use */
+ uint32_t RESERVED58[1U]; /**< Reserved for future use */
+} EMU_TypeDef;
+/** @} End of group EFR32MG24_EMU */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_EMU
+ * @{
+ * @defgroup EFR32MG24_EMU_BitFields EMU Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for EMU DECBOD */
+#define _EMU_DECBOD_RESETVALUE 0x00000022UL /**< Default value for EMU_DECBOD */
+#define _EMU_DECBOD_MASK 0x00000033UL /**< Mask for EMU_DECBOD */
+#define EMU_DECBOD_DECBODEN (0x1UL << 0) /**< DECBOD enable */
+#define _EMU_DECBOD_DECBODEN_SHIFT 0 /**< Shift value for EMU_DECBODEN */
+#define _EMU_DECBOD_DECBODEN_MASK 0x1UL /**< Bit mask for EMU_DECBODEN */
+#define _EMU_DECBOD_DECBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */
+#define EMU_DECBOD_DECBODEN_DEFAULT (_EMU_DECBOD_DECBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DECBOD */
+#define EMU_DECBOD_DECBODMASK (0x1UL << 1) /**< DECBOD Mask */
+#define _EMU_DECBOD_DECBODMASK_SHIFT 1 /**< Shift value for EMU_DECBODMASK */
+#define _EMU_DECBOD_DECBODMASK_MASK 0x2UL /**< Bit mask for EMU_DECBODMASK */
+#define _EMU_DECBOD_DECBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */
+#define EMU_DECBOD_DECBODMASK_DEFAULT (_EMU_DECBOD_DECBODMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DECBOD */
+#define EMU_DECBOD_DECOVMBODEN (0x1UL << 4) /**< Over Voltage Monitor enable */
+#define _EMU_DECBOD_DECOVMBODEN_SHIFT 4 /**< Shift value for EMU_DECOVMBODEN */
+#define _EMU_DECBOD_DECOVMBODEN_MASK 0x10UL /**< Bit mask for EMU_DECOVMBODEN */
+#define _EMU_DECBOD_DECOVMBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */
+#define EMU_DECBOD_DECOVMBODEN_DEFAULT (_EMU_DECBOD_DECOVMBODEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DECBOD */
+#define EMU_DECBOD_DECOVMBODMASK (0x1UL << 5) /**< Over Voltage Monitor Mask */
+#define _EMU_DECBOD_DECOVMBODMASK_SHIFT 5 /**< Shift value for EMU_DECOVMBODMASK */
+#define _EMU_DECBOD_DECOVMBODMASK_MASK 0x20UL /**< Bit mask for EMU_DECOVMBODMASK */
+#define _EMU_DECBOD_DECOVMBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */
+#define EMU_DECBOD_DECOVMBODMASK_DEFAULT (_EMU_DECBOD_DECOVMBODMASK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DECBOD */
+
+/* Bit fields for EMU BOD3SENSE */
+#define _EMU_BOD3SENSE_RESETVALUE 0x00000000UL /**< Default value for EMU_BOD3SENSE */
+#define _EMU_BOD3SENSE_MASK 0x00000077UL /**< Mask for EMU_BOD3SENSE */
+#define EMU_BOD3SENSE_AVDDBODEN (0x1UL << 0) /**< AVDD BOD enable */
+#define _EMU_BOD3SENSE_AVDDBODEN_SHIFT 0 /**< Shift value for EMU_AVDDBODEN */
+#define _EMU_BOD3SENSE_AVDDBODEN_MASK 0x1UL /**< Bit mask for EMU_AVDDBODEN */
+#define _EMU_BOD3SENSE_AVDDBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */
+#define EMU_BOD3SENSE_AVDDBODEN_DEFAULT (_EMU_BOD3SENSE_AVDDBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */
+#define EMU_BOD3SENSE_VDDIO0BODEN (0x1UL << 1) /**< VDDIO0 BOD enable */
+#define _EMU_BOD3SENSE_VDDIO0BODEN_SHIFT 1 /**< Shift value for EMU_VDDIO0BODEN */
+#define _EMU_BOD3SENSE_VDDIO0BODEN_MASK 0x2UL /**< Bit mask for EMU_VDDIO0BODEN */
+#define _EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */
+#define EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */
+#define EMU_BOD3SENSE_VDDIO1BODEN (0x1UL << 2) /**< VDDIO1 BOD enable */
+#define _EMU_BOD3SENSE_VDDIO1BODEN_SHIFT 2 /**< Shift value for EMU_VDDIO1BODEN */
+#define _EMU_BOD3SENSE_VDDIO1BODEN_MASK 0x4UL /**< Bit mask for EMU_VDDIO1BODEN */
+#define _EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */
+#define EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */
+
+/* Bit fields for EMU VREGVDDCMPCTRL */
+#define _EMU_VREGVDDCMPCTRL_RESETVALUE 0x00000006UL /**< Default value for EMU_VREGVDDCMPCTRL */
+#define _EMU_VREGVDDCMPCTRL_MASK 0x00000007UL /**< Mask for EMU_VREGVDDCMPCTRL */
+#define EMU_VREGVDDCMPCTRL_VREGINCMPEN (0x1UL << 0) /**< VREGVDD comparator enable */
+#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_SHIFT 0 /**< Shift value for EMU_VREGINCMPEN */
+#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_MASK 0x1UL /**< Bit mask for EMU_VREGINCMPEN */
+#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */
+#define EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT (_EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */
+#define _EMU_VREGVDDCMPCTRL_THRESSEL_SHIFT 1 /**< Shift value for EMU_THRESSEL */
+#define _EMU_VREGVDDCMPCTRL_THRESSEL_MASK 0x6UL /**< Bit mask for EMU_THRESSEL */
+#define _EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */
+#define EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT (_EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */
+
+/* Bit fields for EMU PD1PARETCTRL */
+#define _EMU_PD1PARETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PD1PARETCTRL */
+#define _EMU_PD1PARETCTRL_MASK 0x0000FFFFUL /**< Mask for EMU_PD1PARETCTRL */
+#define _EMU_PD1PARETCTRL_PD1PARETDIS_SHIFT 0 /**< Shift value for EMU_PD1PARETDIS */
+#define _EMU_PD1PARETCTRL_PD1PARETDIS_MASK 0xFFFFUL /**< Bit mask for EMU_PD1PARETDIS */
+#define _EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PD1PARETCTRL */
+#define _EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN 0x00000001UL /**< Mode PERIPHNORETAIN for EMU_PD1PARETCTRL */
+#define _EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN 0x00000002UL /**< Mode RADIONORETAIN for EMU_PD1PARETCTRL */
+#define EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT (_EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PD1PARETCTRL */
+#define EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN << 0) /**< Shifted mode PERIPHNORETAIN for EMU_PD1PARETCTRL*/
+#define EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN << 0) /**< Shifted mode RADIONORETAIN for EMU_PD1PARETCTRL*/
+
+/* Bit fields for EMU IPVERSION */
+#define _EMU_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for EMU_IPVERSION */
+#define _EMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for EMU_IPVERSION */
+#define _EMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for EMU_IPVERSION */
+#define _EMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for EMU_IPVERSION */
+#define _EMU_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_IPVERSION */
+#define EMU_IPVERSION_IPVERSION_DEFAULT (_EMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IPVERSION */
+
+/* Bit fields for EMU LOCK */
+#define _EMU_LOCK_RESETVALUE 0x0000ADE8UL /**< Default value for EMU_LOCK */
+#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */
+#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
+#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
+#define _EMU_LOCK_LOCKKEY_DEFAULT 0x0000ADE8UL /**< Mode DEFAULT for EMU_LOCK */
+#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */
+#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */
+#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */
+
+/* Bit fields for EMU IF */
+#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */
+#define _EMU_IF_MASK 0xEB070000UL /**< Mask for EMU_IF */
+#define EMU_IF_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt flag */
+#define _EMU_IF_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */
+#define _EMU_IF_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */
+#define _EMU_IF_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_AVDDBOD_DEFAULT (_EMU_IF_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt flag */
+#define _EMU_IF_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */
+#define _EMU_IF_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */
+#define _EMU_IF_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_IOVDD0BOD_DEFAULT (_EMU_IF_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt flag */
+#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */
+#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */
+#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt flag */
+#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */
+#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */
+#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_TEMPAVG (0x1UL << 27) /**< Temperature Average Interrupt flag */
+#define _EMU_IF_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */
+#define _EMU_IF_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */
+#define _EMU_IF_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_TEMPAVG_DEFAULT (_EMU_IF_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_TEMP (0x1UL << 29) /**< Temperature Interrupt flag */
+#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */
+#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */
+#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt flag */
+#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */
+#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */
+#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */
+#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt flag */
+#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */
+#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */
+#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
+#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */
+
+/* Bit fields for EMU IEN */
+#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */
+#define _EMU_IEN_MASK 0xEB070000UL /**< Mask for EMU_IEN */
+#define EMU_IEN_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt enable */
+#define _EMU_IEN_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */
+#define _EMU_IEN_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */
+#define _EMU_IEN_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_AVDDBOD_DEFAULT (_EMU_IEN_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt enable */
+#define _EMU_IEN_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */
+#define _EMU_IEN_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */
+#define _EMU_IEN_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_IOVDD0BOD_DEFAULT (_EMU_IEN_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt enable */
+#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */
+#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */
+#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt enable */
+#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */
+#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */
+#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_TEMPAVG (0x1UL << 27) /**< Temperature Interrupt enable */
+#define _EMU_IEN_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */
+#define _EMU_IEN_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */
+#define _EMU_IEN_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_TEMPAVG_DEFAULT (_EMU_IEN_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_TEMP (0x1UL << 29) /**< Temperature Interrupt enable */
+#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */
+#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */
+#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt enable */
+#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */
+#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */
+#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */
+#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt enable */
+#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */
+#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */
+#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
+#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */
+
+/* Bit fields for EMU EM4CTRL */
+#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */
+#define _EMU_EM4CTRL_MASK 0x00000133UL /**< Mask for EMU_EM4CTRL */
+#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 0 /**< Shift value for EMU_EM4ENTRY */
+#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x3UL /**< Bit mask for EMU_EM4ENTRY */
+#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
+#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
+#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */
+#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */
+#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
+#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */
+#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */
+#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */
+#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
+#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */
+#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */
+#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */
+#define EMU_EM4CTRL_BOD3SENSEEM4WU (0x1UL << 8) /**< Set BOD3SENSE as EM4 wakeup */
+#define _EMU_EM4CTRL_BOD3SENSEEM4WU_SHIFT 8 /**< Shift value for EMU_BOD3SENSEEM4WU */
+#define _EMU_EM4CTRL_BOD3SENSEEM4WU_MASK 0x100UL /**< Bit mask for EMU_BOD3SENSEEM4WU */
+#define _EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
+#define EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT (_EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
+
+/* Bit fields for EMU CMD */
+#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */
+#define _EMU_CMD_MASK 0x00060E12UL /**< Mask for EMU_CMD */
+#define EMU_CMD_EM4UNLATCH (0x1UL << 1) /**< EM4 unlatch */
+#define _EMU_CMD_EM4UNLATCH_SHIFT 1 /**< Shift value for EMU_EM4UNLATCH */
+#define _EMU_CMD_EM4UNLATCH_MASK 0x2UL /**< Bit mask for EMU_EM4UNLATCH */
+#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */
+#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CMD */
+#define EMU_CMD_TEMPAVGREQ (0x1UL << 4) /**< Temperature Average Request */
+#define _EMU_CMD_TEMPAVGREQ_SHIFT 4 /**< Shift value for EMU_TEMPAVGREQ */
+#define _EMU_CMD_TEMPAVGREQ_MASK 0x10UL /**< Bit mask for EMU_TEMPAVGREQ */
+#define _EMU_CMD_TEMPAVGREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */
+#define EMU_CMD_TEMPAVGREQ_DEFAULT (_EMU_CMD_TEMPAVGREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */
+#define EMU_CMD_EM01VSCALE1 (0x1UL << 10) /**< Scale voltage to Vscale1 */
+#define _EMU_CMD_EM01VSCALE1_SHIFT 10 /**< Shift value for EMU_EM01VSCALE1 */
+#define _EMU_CMD_EM01VSCALE1_MASK 0x400UL /**< Bit mask for EMU_EM01VSCALE1 */
+#define _EMU_CMD_EM01VSCALE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */
+#define EMU_CMD_EM01VSCALE1_DEFAULT (_EMU_CMD_EM01VSCALE1_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_CMD */
+#define EMU_CMD_EM01VSCALE2 (0x1UL << 11) /**< Scale voltage to Vscale2 */
+#define _EMU_CMD_EM01VSCALE2_SHIFT 11 /**< Shift value for EMU_EM01VSCALE2 */
+#define _EMU_CMD_EM01VSCALE2_MASK 0x800UL /**< Bit mask for EMU_EM01VSCALE2 */
+#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */
+#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_CMD */
+#define EMU_CMD_RSTCAUSECLR (0x1UL << 17) /**< Reset Cause Clear */
+#define _EMU_CMD_RSTCAUSECLR_SHIFT 17 /**< Shift value for EMU_RSTCAUSECLR */
+#define _EMU_CMD_RSTCAUSECLR_MASK 0x20000UL /**< Bit mask for EMU_RSTCAUSECLR */
+#define _EMU_CMD_RSTCAUSECLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */
+#define EMU_CMD_RSTCAUSECLR_DEFAULT (_EMU_CMD_RSTCAUSECLR_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_CMD */
+
+/* Bit fields for EMU CTRL */
+#define _EMU_CTRL_RESETVALUE 0x00000200UL /**< Default value for EMU_CTRL */
+#define _EMU_CTRL_MASK 0xE0010309UL /**< Mask for EMU_CTRL */
+#define EMU_CTRL_EM2DBGEN (0x1UL << 0) /**< Enable debugging in EM2 */
+#define _EMU_CTRL_EM2DBGEN_SHIFT 0 /**< Shift value for EMU_EM2DBGEN */
+#define _EMU_CTRL_EM2DBGEN_MASK 0x1UL /**< Bit mask for EMU_EM2DBGEN */
+#define _EMU_CTRL_EM2DBGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
+#define EMU_CTRL_EM2DBGEN_DEFAULT (_EMU_CTRL_EM2DBGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CTRL */
+#define EMU_CTRL_TEMPAVGNUM (0x1UL << 3) /**< Averaged Temperature samples num */
+#define _EMU_CTRL_TEMPAVGNUM_SHIFT 3 /**< Shift value for EMU_TEMPAVGNUM */
+#define _EMU_CTRL_TEMPAVGNUM_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGNUM */
+#define _EMU_CTRL_TEMPAVGNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
+#define _EMU_CTRL_TEMPAVGNUM_N16 0x00000000UL /**< Mode N16 for EMU_CTRL */
+#define _EMU_CTRL_TEMPAVGNUM_N64 0x00000001UL /**< Mode N64 for EMU_CTRL */
+#define EMU_CTRL_TEMPAVGNUM_DEFAULT (_EMU_CTRL_TEMPAVGNUM_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */
+#define EMU_CTRL_TEMPAVGNUM_N16 (_EMU_CTRL_TEMPAVGNUM_N16 << 3) /**< Shifted mode N16 for EMU_CTRL */
+#define EMU_CTRL_TEMPAVGNUM_N64 (_EMU_CTRL_TEMPAVGNUM_N64 << 3) /**< Shifted mode N64 for EMU_CTRL */
+#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */
+#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */
+#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_CTRL */
+#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_CTRL */
+#define _EMU_CTRL_EM23VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_CTRL */
+#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_CTRL */
+#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */
+#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */
+#define EMU_CTRL_EM23VSCALE_VSCALE1 (_EMU_CTRL_EM23VSCALE_VSCALE1 << 8) /**< Shifted mode VSCALE1 for EMU_CTRL */
+#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */
+#define EMU_CTRL_FLASHPWRUPONDEMAND (0x1UL << 16) /**< Enable flash on demand wakeup */
+#define _EMU_CTRL_FLASHPWRUPONDEMAND_SHIFT 16 /**< Shift value for EMU_FLASHPWRUPONDEMAND */
+#define _EMU_CTRL_FLASHPWRUPONDEMAND_MASK 0x10000UL /**< Bit mask for EMU_FLASHPWRUPONDEMAND */
+#define _EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
+#define EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT (_EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */
+#define EMU_CTRL_EFPDIRECTMODEEN (0x1UL << 29) /**< EFP Direct Mode Enable */
+#define _EMU_CTRL_EFPDIRECTMODEEN_SHIFT 29 /**< Shift value for EMU_EFPDIRECTMODEEN */
+#define _EMU_CTRL_EFPDIRECTMODEEN_MASK 0x20000000UL /**< Bit mask for EMU_EFPDIRECTMODEEN */
+#define _EMU_CTRL_EFPDIRECTMODEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
+#define EMU_CTRL_EFPDIRECTMODEEN_DEFAULT (_EMU_CTRL_EFPDIRECTMODEEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_CTRL */
+#define EMU_CTRL_EFPDRVDECOUPLE (0x1UL << 30) /**< EFP drives DECOUPLE */
+#define _EMU_CTRL_EFPDRVDECOUPLE_SHIFT 30 /**< Shift value for EMU_EFPDRVDECOUPLE */
+#define _EMU_CTRL_EFPDRVDECOUPLE_MASK 0x40000000UL /**< Bit mask for EMU_EFPDRVDECOUPLE */
+#define _EMU_CTRL_EFPDRVDECOUPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
+#define EMU_CTRL_EFPDRVDECOUPLE_DEFAULT (_EMU_CTRL_EFPDRVDECOUPLE_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_CTRL */
+#define EMU_CTRL_EFPDRVDVDD (0x1UL << 31) /**< EFP drives DVDD */
+#define _EMU_CTRL_EFPDRVDVDD_SHIFT 31 /**< Shift value for EMU_EFPDRVDVDD */
+#define _EMU_CTRL_EFPDRVDVDD_MASK 0x80000000UL /**< Bit mask for EMU_EFPDRVDVDD */
+#define _EMU_CTRL_EFPDRVDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
+#define EMU_CTRL_EFPDRVDVDD_DEFAULT (_EMU_CTRL_EFPDRVDVDD_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_CTRL */
+
+/* Bit fields for EMU TEMPLIMITS */
+#define _EMU_TEMPLIMITS_RESETVALUE 0x01FF0000UL /**< Default value for EMU_TEMPLIMITS */
+#define _EMU_TEMPLIMITS_MASK 0x01FF01FFUL /**< Mask for EMU_TEMPLIMITS */
+#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */
+#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0x1FFUL /**< Bit mask for EMU_TEMPLOW */
+#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */
+#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */
+#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 16 /**< Shift value for EMU_TEMPHIGH */
+#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0x1FF0000UL /**< Bit mask for EMU_TEMPHIGH */
+#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000001FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */
+#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */
+
+/* Bit fields for EMU STATUS */
+#define _EMU_STATUS_RESETVALUE 0x00000080UL /**< Default value for EMU_STATUS */
+#define _EMU_STATUS_MASK 0xFFFFEFFFUL /**< Mask for EMU_STATUS */
+#define EMU_STATUS_LOCK (0x1UL << 0) /**< Lock status */
+#define _EMU_STATUS_LOCK_SHIFT 0 /**< Shift value for EMU_LOCK */
+#define _EMU_STATUS_LOCK_MASK 0x1UL /**< Bit mask for EMU_LOCK */
+#define _EMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
+#define _EMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_STATUS */
+#define _EMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_STATUS */
+#define EMU_STATUS_LOCK_DEFAULT (_EMU_STATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_LOCK_UNLOCKED (_EMU_STATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_STATUS */
+#define EMU_STATUS_LOCK_LOCKED (_EMU_STATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for EMU_STATUS */
+#define EMU_STATUS_FIRSTTEMPDONE (0x1UL << 1) /**< First Temp done */
+#define _EMU_STATUS_FIRSTTEMPDONE_SHIFT 1 /**< Shift value for EMU_FIRSTTEMPDONE */
+#define _EMU_STATUS_FIRSTTEMPDONE_MASK 0x2UL /**< Bit mask for EMU_FIRSTTEMPDONE */
+#define _EMU_STATUS_FIRSTTEMPDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_FIRSTTEMPDONE_DEFAULT (_EMU_STATUS_FIRSTTEMPDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_TEMPACTIVE (0x1UL << 2) /**< Temp active */
+#define _EMU_STATUS_TEMPACTIVE_SHIFT 2 /**< Shift value for EMU_TEMPACTIVE */
+#define _EMU_STATUS_TEMPACTIVE_MASK 0x4UL /**< Bit mask for EMU_TEMPACTIVE */
+#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_TEMPAVGACTIVE (0x1UL << 3) /**< Temp Average active */
+#define _EMU_STATUS_TEMPAVGACTIVE_SHIFT 3 /**< Shift value for EMU_TEMPAVGACTIVE */
+#define _EMU_STATUS_TEMPAVGACTIVE_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGACTIVE */
+#define _EMU_STATUS_TEMPAVGACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_TEMPAVGACTIVE_DEFAULT (_EMU_STATUS_TEMPAVGACTIVE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_VSCALEBUSY (0x1UL << 4) /**< Vscale busy */
+#define _EMU_STATUS_VSCALEBUSY_SHIFT 4 /**< Shift value for EMU_VSCALEBUSY */
+#define _EMU_STATUS_VSCALEBUSY_MASK 0x10UL /**< Bit mask for EMU_VSCALEBUSY */
+#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_VSCALEFAILED (0x1UL << 5) /**< Vscale failed */
+#define _EMU_STATUS_VSCALEFAILED_SHIFT 5 /**< Shift value for EMU_VSCALEFAILED */
+#define _EMU_STATUS_VSCALEFAILED_MASK 0x20UL /**< Bit mask for EMU_VSCALEFAILED */
+#define _EMU_STATUS_VSCALEFAILED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_VSCALEFAILED_DEFAULT (_EMU_STATUS_VSCALEFAILED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */
+#define _EMU_STATUS_VSCALE_SHIFT 6 /**< Shift value for EMU_VSCALE */
+#define _EMU_STATUS_VSCALE_MASK 0xC0UL /**< Bit mask for EMU_VSCALE */
+#define _EMU_STATUS_VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_STATUS */
+#define _EMU_STATUS_VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_STATUS */
+#define _EMU_STATUS_VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_STATUS */
+#define _EMU_STATUS_VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_STATUS */
+#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 6) /**< Shifted mode VSCALE0 for EMU_STATUS */
+#define EMU_STATUS_VSCALE_VSCALE1 (_EMU_STATUS_VSCALE_VSCALE1 << 6) /**< Shifted mode VSCALE1 for EMU_STATUS */
+#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 6) /**< Shifted mode VSCALE2 for EMU_STATUS */
+#define EMU_STATUS_RACACTIVE (0x1UL << 8) /**< RAC active */
+#define _EMU_STATUS_RACACTIVE_SHIFT 8 /**< Shift value for EMU_RACACTIVE */
+#define _EMU_STATUS_RACACTIVE_MASK 0x100UL /**< Bit mask for EMU_RACACTIVE */
+#define _EMU_STATUS_RACACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_RACACTIVE_DEFAULT (_EMU_STATUS_RACACTIVE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_EM4IORET (0x1UL << 9) /**< EM4 IO retention status */
+#define _EMU_STATUS_EM4IORET_SHIFT 9 /**< Shift value for EMU_EM4IORET */
+#define _EMU_STATUS_EM4IORET_MASK 0x200UL /**< Bit mask for EMU_EM4IORET */
+#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_EM2ENTERED (0x1UL << 10) /**< EM2 entered */
+#define _EMU_STATUS_EM2ENTERED_SHIFT 10 /**< Shift value for EMU_EM2ENTERED */
+#define _EMU_STATUS_EM2ENTERED_MASK 0x400UL /**< Bit mask for EMU_EM2ENTERED */
+#define _EMU_STATUS_EM2ENTERED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
+#define EMU_STATUS_EM2ENTERED_DEFAULT (_EMU_STATUS_EM2ENTERED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_STATUS */
+
+/* Bit fields for EMU TEMP */
+#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */
+#define _EMU_TEMP_MASK 0x07FF07FFUL /**< Mask for EMU_TEMP */
+#define _EMU_TEMP_TEMPLSB_SHIFT 0 /**< Shift value for EMU_TEMPLSB */
+#define _EMU_TEMP_TEMPLSB_MASK 0x3UL /**< Bit mask for EMU_TEMPLSB */
+#define _EMU_TEMP_TEMPLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */
+#define EMU_TEMP_TEMPLSB_DEFAULT (_EMU_TEMP_TEMPLSB_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */
+#define _EMU_TEMP_TEMP_SHIFT 2 /**< Shift value for EMU_TEMP */
+#define _EMU_TEMP_TEMP_MASK 0x7FCUL /**< Bit mask for EMU_TEMP */
+#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */
+#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_TEMP */
+#define _EMU_TEMP_TEMPAVG_SHIFT 16 /**< Shift value for EMU_TEMPAVG */
+#define _EMU_TEMP_TEMPAVG_MASK 0x7FF0000UL /**< Bit mask for EMU_TEMPAVG */
+#define _EMU_TEMP_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */
+#define EMU_TEMP_TEMPAVG_DEFAULT (_EMU_TEMP_TEMPAVG_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMP */
+
+/* Bit fields for EMU RSTCTRL */
+#define _EMU_RSTCTRL_RESETVALUE 0x00060407UL /**< Default value for EMU_RSTCTRL */
+#define _EMU_RSTCTRL_MASK 0xC006C5CFUL /**< Mask for EMU_RSTCTRL */
+#define EMU_RSTCTRL_WDOG0RMODE (0x1UL << 0) /**< Enable WDOG0 reset */
+#define _EMU_RSTCTRL_WDOG0RMODE_SHIFT 0 /**< Shift value for EMU_WDOG0RMODE */
+#define _EMU_RSTCTRL_WDOG0RMODE_MASK 0x1UL /**< Bit mask for EMU_WDOG0RMODE */
+#define _EMU_RSTCTRL_WDOG0RMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */
+#define _EMU_RSTCTRL_WDOG0RMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */
+#define _EMU_RSTCTRL_WDOG0RMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */
+#define EMU_RSTCTRL_WDOG0RMODE_DEFAULT (_EMU_RSTCTRL_WDOG0RMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCTRL */
+#define EMU_RSTCTRL_WDOG0RMODE_DISABLED (_EMU_RSTCTRL_WDOG0RMODE_DISABLED << 0) /**< Shifted mode DISABLED for EMU_RSTCTRL */
+#define EMU_RSTCTRL_WDOG0RMODE_ENABLED (_EMU_RSTCTRL_WDOG0RMODE_ENABLED << 0) /**< Shifted mode ENABLED for EMU_RSTCTRL */
+#define EMU_RSTCTRL_SYSRMODE (0x1UL << 2) /**< Enable M33 System reset */
+#define _EMU_RSTCTRL_SYSRMODE_SHIFT 2 /**< Shift value for EMU_SYSRMODE */
+#define _EMU_RSTCTRL_SYSRMODE_MASK 0x4UL /**< Bit mask for EMU_SYSRMODE */
+#define _EMU_RSTCTRL_SYSRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */
+#define _EMU_RSTCTRL_SYSRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */
+#define _EMU_RSTCTRL_SYSRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */
+#define EMU_RSTCTRL_SYSRMODE_DEFAULT (_EMU_RSTCTRL_SYSRMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCTRL */
+#define EMU_RSTCTRL_SYSRMODE_DISABLED (_EMU_RSTCTRL_SYSRMODE_DISABLED << 2) /**< Shifted mode DISABLED for EMU_RSTCTRL */
+#define EMU_RSTCTRL_SYSRMODE_ENABLED (_EMU_RSTCTRL_SYSRMODE_ENABLED << 2) /**< Shifted mode ENABLED for EMU_RSTCTRL */
+#define EMU_RSTCTRL_LOCKUPRMODE (0x1UL << 3) /**< Enable M33 Lockup reset */
+#define _EMU_RSTCTRL_LOCKUPRMODE_SHIFT 3 /**< Shift value for EMU_LOCKUPRMODE */
+#define _EMU_RSTCTRL_LOCKUPRMODE_MASK 0x8UL /**< Bit mask for EMU_LOCKUPRMODE */
+#define _EMU_RSTCTRL_LOCKUPRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */
+#define _EMU_RSTCTRL_LOCKUPRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */
+#define _EMU_RSTCTRL_LOCKUPRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */
+#define EMU_RSTCTRL_LOCKUPRMODE_DEFAULT (_EMU_RSTCTRL_LOCKUPRMODE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCTRL */
+#define EMU_RSTCTRL_LOCKUPRMODE_DISABLED (_EMU_RSTCTRL_LOCKUPRMODE_DISABLED << 3) /**< Shifted mode DISABLED for EMU_RSTCTRL */
+#define EMU_RSTCTRL_LOCKUPRMODE_ENABLED (_EMU_RSTCTRL_LOCKUPRMODE_ENABLED << 3) /**< Shifted mode ENABLED for EMU_RSTCTRL */
+#define EMU_RSTCTRL_AVDDBODRMODE (0x1UL << 6) /**< Enable AVDD BOD reset */
+#define _EMU_RSTCTRL_AVDDBODRMODE_SHIFT 6 /**< Shift value for EMU_AVDDBODRMODE */
+#define _EMU_RSTCTRL_AVDDBODRMODE_MASK 0x40UL /**< Bit mask for EMU_AVDDBODRMODE */
+#define _EMU_RSTCTRL_AVDDBODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */
+#define _EMU_RSTCTRL_AVDDBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */
+#define _EMU_RSTCTRL_AVDDBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */
+#define EMU_RSTCTRL_AVDDBODRMODE_DEFAULT (_EMU_RSTCTRL_AVDDBODRMODE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCTRL */
+#define EMU_RSTCTRL_AVDDBODRMODE_DISABLED (_EMU_RSTCTRL_AVDDBODRMODE_DISABLED << 6) /**< Shifted mode DISABLED for EMU_RSTCTRL */
+#define EMU_RSTCTRL_AVDDBODRMODE_ENABLED (_EMU_RSTCTRL_AVDDBODRMODE_ENABLED << 6) /**< Shifted mode ENABLED for EMU_RSTCTRL */
+#define EMU_RSTCTRL_IOVDD0BODRMODE (0x1UL << 7) /**< Enable VDDIO0 BOD reset */
+#define _EMU_RSTCTRL_IOVDD0BODRMODE_SHIFT 7 /**< Shift value for EMU_IOVDD0BODRMODE */
+#define _EMU_RSTCTRL_IOVDD0BODRMODE_MASK 0x80UL /**< Bit mask for EMU_IOVDD0BODRMODE */
+#define _EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */
+#define _EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */
+#define _EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */
+#define EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT (_EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCTRL */
+#define EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED << 7) /**< Shifted mode DISABLED for EMU_RSTCTRL */
+#define EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED << 7) /**< Shifted mode ENABLED for EMU_RSTCTRL */
+#define EMU_RSTCTRL_DECBODRMODE (0x1UL << 10) /**< Enable DECBOD reset */
+#define _EMU_RSTCTRL_DECBODRMODE_SHIFT 10 /**< Shift value for EMU_DECBODRMODE */
+#define _EMU_RSTCTRL_DECBODRMODE_MASK 0x400UL /**< Bit mask for EMU_DECBODRMODE */
+#define _EMU_RSTCTRL_DECBODRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */
+#define _EMU_RSTCTRL_DECBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */
+#define _EMU_RSTCTRL_DECBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */
+#define EMU_RSTCTRL_DECBODRMODE_DEFAULT (_EMU_RSTCTRL_DECBODRMODE_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCTRL */
+#define EMU_RSTCTRL_DECBODRMODE_DISABLED (_EMU_RSTCTRL_DECBODRMODE_DISABLED << 10) /**< Shifted mode DISABLED for EMU_RSTCTRL */
+#define EMU_RSTCTRL_DECBODRMODE_ENABLED (_EMU_RSTCTRL_DECBODRMODE_ENABLED << 10) /**< Shifted mode ENABLED for EMU_RSTCTRL */
+
+/* Bit fields for EMU RSTCAUSE */
+#define _EMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for EMU_RSTCAUSE */
+#define _EMU_RSTCAUSE_MASK 0x8006FFFFUL /**< Mask for EMU_RSTCAUSE */
+#define EMU_RSTCAUSE_POR (0x1UL << 0) /**< Power On Reset */
+#define _EMU_RSTCAUSE_POR_SHIFT 0 /**< Shift value for EMU_POR */
+#define _EMU_RSTCAUSE_POR_MASK 0x1UL /**< Bit mask for EMU_POR */
+#define _EMU_RSTCAUSE_POR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */
+#define EMU_RSTCAUSE_POR_DEFAULT (_EMU_RSTCAUSE_POR_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */
+#define EMU_RSTCAUSE_PIN (0x1UL << 1) /**< Pin Reset */
+#define _EMU_RSTCAUSE_PIN_SHIFT 1 /**< Shift value for EMU_PIN */
+#define _EMU_RSTCAUSE_PIN_MASK 0x2UL /**< Bit mask for EMU_PIN */
+#define _EMU_RSTCAUSE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */
+#define EMU_RSTCAUSE_PIN_DEFAULT (_EMU_RSTCAUSE_PIN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */
+#define EMU_RSTCAUSE_EM4 (0x1UL << 2) /**< EM4 Wakeup Reset */
+#define _EMU_RSTCAUSE_EM4_SHIFT 2 /**< Shift value for EMU_EM4 */
+#define _EMU_RSTCAUSE_EM4_MASK 0x4UL /**< Bit mask for EMU_EM4 */
+#define _EMU_RSTCAUSE_EM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */
+#define EMU_RSTCAUSE_EM4_DEFAULT (_EMU_RSTCAUSE_EM4_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */
+#define EMU_RSTCAUSE_WDOG0 (0x1UL << 3) /**< Watchdog 0 Reset */
+#define _EMU_RSTCAUSE_WDOG0_SHIFT 3 /**< Shift value for EMU_WDOG0 */
+#define _EMU_RSTCAUSE_WDOG0_MASK 0x8UL /**< Bit mask for EMU_WDOG0 */
+#define _EMU_RSTCAUSE_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */
+#define EMU_RSTCAUSE_WDOG0_DEFAULT (_EMU_RSTCAUSE_WDOG0_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */
+#define EMU_RSTCAUSE_WDOG1 (0x1UL << 4) /**< Watchdog 1 Reset */
+#define _EMU_RSTCAUSE_WDOG1_SHIFT 4 /**< Shift value for EMU_WDOG1 */
+#define _EMU_RSTCAUSE_WDOG1_MASK 0x10UL /**< Bit mask for EMU_WDOG1 */
+#define _EMU_RSTCAUSE_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */
+#define EMU_RSTCAUSE_WDOG1_DEFAULT (_EMU_RSTCAUSE_WDOG1_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */
+#define EMU_RSTCAUSE_LOCKUP (0x1UL << 5) /**< M33 Core Lockup Reset */
+#define _EMU_RSTCAUSE_LOCKUP_SHIFT 5 /**< Shift value for EMU_LOCKUP */
+#define _EMU_RSTCAUSE_LOCKUP_MASK 0x20UL /**< Bit mask for EMU_LOCKUP */
+#define _EMU_RSTCAUSE_LOCKUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */
+#define EMU_RSTCAUSE_LOCKUP_DEFAULT (_EMU_RSTCAUSE_LOCKUP_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */
+#define EMU_RSTCAUSE_SYSREQ (0x1UL << 6) /**< M33 Core Sys Reset */
+#define _EMU_RSTCAUSE_SYSREQ_SHIFT 6 /**< Shift value for EMU_SYSREQ */
+#define _EMU_RSTCAUSE_SYSREQ_MASK 0x40UL /**< Bit mask for EMU_SYSREQ */
+#define _EMU_RSTCAUSE_SYSREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */
+#define EMU_RSTCAUSE_SYSREQ_DEFAULT (_EMU_RSTCAUSE_SYSREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */
+#define EMU_RSTCAUSE_DVDDBOD (0x1UL << 7) /**< HVBOD Reset */
+#define _EMU_RSTCAUSE_DVDDBOD_SHIFT 7 /**< Shift value for EMU_DVDDBOD */
+#define _EMU_RSTCAUSE_DVDDBOD_MASK 0x80UL /**< Bit mask for EMU_DVDDBOD */
+#define _EMU_RSTCAUSE_DVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */
+#define EMU_RSTCAUSE_DVDDBOD_DEFAULT (_EMU_RSTCAUSE_DVDDBOD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */
+#define EMU_RSTCAUSE_DVDDLEBOD (0x1UL << 8) /**< LEBOD Reset */
+#define _EMU_RSTCAUSE_DVDDLEBOD_SHIFT 8 /**< Shift value for EMU_DVDDLEBOD */
+#define _EMU_RSTCAUSE_DVDDLEBOD_MASK 0x100UL /**< Bit mask for EMU_DVDDLEBOD */
+#define _EMU_RSTCAUSE_DVDDLEBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */
+#define EMU_RSTCAUSE_DVDDLEBOD_DEFAULT (_EMU_RSTCAUSE_DVDDLEBOD_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */
+#define EMU_RSTCAUSE_DECBOD (0x1UL << 9) /**< LVBOD Reset */
+#define _EMU_RSTCAUSE_DECBOD_SHIFT 9 /**< Shift value for EMU_DECBOD */
+#define _EMU_RSTCAUSE_DECBOD_MASK 0x200UL /**< Bit mask for EMU_DECBOD */
+#define _EMU_RSTCAUSE_DECBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */
+#define EMU_RSTCAUSE_DECBOD_DEFAULT (_EMU_RSTCAUSE_DECBOD_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */
+#define EMU_RSTCAUSE_AVDDBOD (0x1UL << 10) /**< LEBOD1 Reset */
+#define _EMU_RSTCAUSE_AVDDBOD_SHIFT 10 /**< Shift value for EMU_AVDDBOD */
+#define _EMU_RSTCAUSE_AVDDBOD_MASK 0x400UL /**< Bit mask for EMU_AVDDBOD */
+#define _EMU_RSTCAUSE_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */
+#define EMU_RSTCAUSE_AVDDBOD_DEFAULT (_EMU_RSTCAUSE_AVDDBOD_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */
+#define EMU_RSTCAUSE_IOVDD0BOD (0x1UL << 11) /**< LEBOD2 Reset */
+#define _EMU_RSTCAUSE_IOVDD0BOD_SHIFT 11 /**< Shift value for EMU_IOVDD0BOD */
+#define _EMU_RSTCAUSE_IOVDD0BOD_MASK 0x800UL /**< Bit mask for EMU_IOVDD0BOD */
+#define _EMU_RSTCAUSE_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */
+#define EMU_RSTCAUSE_IOVDD0BOD_DEFAULT (_EMU_RSTCAUSE_IOVDD0BOD_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */
+#define EMU_RSTCAUSE_VREGIN (0x1UL << 31) /**< DCDC VREGIN comparator */
+#define _EMU_RSTCAUSE_VREGIN_SHIFT 31 /**< Shift value for EMU_VREGIN */
+#define _EMU_RSTCAUSE_VREGIN_MASK 0x80000000UL /**< Bit mask for EMU_VREGIN */
+#define _EMU_RSTCAUSE_VREGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */
+#define EMU_RSTCAUSE_VREGIN_DEFAULT (_EMU_RSTCAUSE_VREGIN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */
+
+/* Bit fields for EMU DGIF */
+#define _EMU_DGIF_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIF */
+#define _EMU_DGIF_MASK 0xE1000000UL /**< Mask for EMU_DGIF */
+#define EMU_DGIF_EM23WAKEUPDGIF (0x1UL << 24) /**< EM23 Wake up Interrupt flag */
+#define _EMU_DGIF_EM23WAKEUPDGIF_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIF */
+#define _EMU_DGIF_EM23WAKEUPDGIF_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIF */
+#define _EMU_DGIF_EM23WAKEUPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */
+#define EMU_DGIF_EM23WAKEUPDGIF_DEFAULT (_EMU_DGIF_EM23WAKEUPDGIF_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIF */
+#define EMU_DGIF_TEMPDGIF (0x1UL << 29) /**< Temperature Interrupt flag */
+#define _EMU_DGIF_TEMPDGIF_SHIFT 29 /**< Shift value for EMU_TEMPDGIF */
+#define _EMU_DGIF_TEMPDGIF_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIF */
+#define _EMU_DGIF_TEMPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */
+#define EMU_DGIF_TEMPDGIF_DEFAULT (_EMU_DGIF_TEMPDGIF_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIF */
+#define EMU_DGIF_TEMPLOWDGIF (0x1UL << 30) /**< Temperature low Interrupt flag */
+#define _EMU_DGIF_TEMPLOWDGIF_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIF */
+#define _EMU_DGIF_TEMPLOWDGIF_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIF */
+#define _EMU_DGIF_TEMPLOWDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */
+#define EMU_DGIF_TEMPLOWDGIF_DEFAULT (_EMU_DGIF_TEMPLOWDGIF_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIF */
+#define EMU_DGIF_TEMPHIGHDGIF (0x1UL << 31) /**< Temperature high Interrupt flag */
+#define _EMU_DGIF_TEMPHIGHDGIF_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIF */
+#define _EMU_DGIF_TEMPHIGHDGIF_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIF */
+#define _EMU_DGIF_TEMPHIGHDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */
+#define EMU_DGIF_TEMPHIGHDGIF_DEFAULT (_EMU_DGIF_TEMPHIGHDGIF_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIF */
+
+/* Bit fields for EMU DGIEN */
+#define _EMU_DGIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIEN */
+#define _EMU_DGIEN_MASK 0xE1000000UL /**< Mask for EMU_DGIEN */
+#define EMU_DGIEN_EM23WAKEUPDGIEN (0x1UL << 24) /**< EM23 Wake up Interrupt enable */
+#define _EMU_DGIEN_EM23WAKEUPDGIEN_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIEN */
+#define _EMU_DGIEN_EM23WAKEUPDGIEN_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIEN */
+#define _EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */
+#define EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT (_EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIEN */
+#define EMU_DGIEN_TEMPDGIEN (0x1UL << 29) /**< Temperature Interrupt enable */
+#define _EMU_DGIEN_TEMPDGIEN_SHIFT 29 /**< Shift value for EMU_TEMPDGIEN */
+#define _EMU_DGIEN_TEMPDGIEN_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIEN */
+#define _EMU_DGIEN_TEMPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */
+#define EMU_DGIEN_TEMPDGIEN_DEFAULT (_EMU_DGIEN_TEMPDGIEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIEN */
+#define EMU_DGIEN_TEMPLOWDGIEN (0x1UL << 30) /**< Temperature low Interrupt enable */
+#define _EMU_DGIEN_TEMPLOWDGIEN_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIEN */
+#define _EMU_DGIEN_TEMPLOWDGIEN_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIEN */
+#define _EMU_DGIEN_TEMPLOWDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */
+#define EMU_DGIEN_TEMPLOWDGIEN_DEFAULT (_EMU_DGIEN_TEMPLOWDGIEN_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIEN */
+#define EMU_DGIEN_TEMPHIGHDGIEN (0x1UL << 31) /**< Temperature high Interrupt enable */
+#define _EMU_DGIEN_TEMPHIGHDGIEN_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIEN */
+#define _EMU_DGIEN_TEMPHIGHDGIEN_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIEN */
+#define _EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */
+#define EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT (_EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIEN */
+
+/* Bit fields for EMU SEQIF */
+#define _EMU_SEQIF_RESETVALUE 0x00000000UL /**< Default value for EMU_SEQIF */
+#define _EMU_SEQIF_MASK 0xE0000000UL /**< Mask for EMU_SEQIF */
+#define EMU_SEQIF_TEMP (0x1UL << 29) /**< Temperature Interrupt flag */
+#define _EMU_SEQIF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */
+#define _EMU_SEQIF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */
+#define _EMU_SEQIF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_SEQIF */
+#define EMU_SEQIF_TEMP_DEFAULT (_EMU_SEQIF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_SEQIF */
+#define EMU_SEQIF_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt flag */
+#define _EMU_SEQIF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */
+#define _EMU_SEQIF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */
+#define _EMU_SEQIF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_SEQIF */
+#define EMU_SEQIF_TEMPLOW_DEFAULT (_EMU_SEQIF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_SEQIF */
+#define EMU_SEQIF_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt flag */
+#define _EMU_SEQIF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */
+#define _EMU_SEQIF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */
+#define _EMU_SEQIF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_SEQIF */
+#define EMU_SEQIF_TEMPHIGH_DEFAULT (_EMU_SEQIF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_SEQIF */
+
+/* Bit fields for EMU SEQIEN */
+#define _EMU_SEQIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_SEQIEN */
+#define _EMU_SEQIEN_MASK 0xE0000000UL /**< Mask for EMU_SEQIEN */
+#define EMU_SEQIEN_TEMP (0x1UL << 29) /**< Temperature Interrupt enable */
+#define _EMU_SEQIEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */
+#define _EMU_SEQIEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */
+#define _EMU_SEQIEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_SEQIEN */
+#define EMU_SEQIEN_TEMP_DEFAULT (_EMU_SEQIEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_SEQIEN */
+#define EMU_SEQIEN_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt enable */
+#define _EMU_SEQIEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */
+#define _EMU_SEQIEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */
+#define _EMU_SEQIEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_SEQIEN */
+#define EMU_SEQIEN_TEMPLOW_DEFAULT (_EMU_SEQIEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_SEQIEN */
+#define EMU_SEQIEN_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt enable */
+#define _EMU_SEQIEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */
+#define _EMU_SEQIEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */
+#define _EMU_SEQIEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_SEQIEN */
+#define EMU_SEQIEN_TEMPHIGH_DEFAULT (_EMU_SEQIEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_SEQIEN */
+
+/* Bit fields for EMU EFPIF */
+#define _EMU_EFPIF_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIF */
+#define _EMU_EFPIF_MASK 0x00000001UL /**< Mask for EMU_EFPIF */
+#define EMU_EFPIF_EFPIF (0x1UL << 0) /**< EFP Interrupt Flag */
+#define _EMU_EFPIF_EFPIF_SHIFT 0 /**< Shift value for EMU_EFPIF */
+#define _EMU_EFPIF_EFPIF_MASK 0x1UL /**< Bit mask for EMU_EFPIF */
+#define _EMU_EFPIF_EFPIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIF */
+#define EMU_EFPIF_EFPIF_DEFAULT (_EMU_EFPIF_EFPIF_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIF */
+
+/* Bit fields for EMU EFPIEN */
+#define _EMU_EFPIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIEN */
+#define _EMU_EFPIEN_MASK 0x00000001UL /**< Mask for EMU_EFPIEN */
+#define EMU_EFPIEN_EFPIEN (0x1UL << 0) /**< EFP Interrupt enable */
+#define _EMU_EFPIEN_EFPIEN_SHIFT 0 /**< Shift value for EMU_EFPIEN */
+#define _EMU_EFPIEN_EFPIEN_MASK 0x1UL /**< Bit mask for EMU_EFPIEN */
+#define _EMU_EFPIEN_EFPIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIEN */
+#define EMU_EFPIEN_EFPIEN_DEFAULT (_EMU_EFPIEN_EFPIEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIEN */
+
+/** @} End of group EFR32MG24_EMU_BitFields */
+/** @} End of group EFR32MG24_EMU */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_EMU_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_eusart.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_eusart.h
new file mode 100644
index 00000000..320131bf
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_eusart.h
@@ -0,0 +1,1319 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 EUSART register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_EUSART_H
+#define EFR32MG24_EUSART_H
+#define EUSART_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_EUSART EUSART
+ * @{
+ * @brief EFR32MG24 EUSART Register Declaration.
+ *****************************************************************************/
+
+/** EUSART Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IP version ID */
+ __IOM uint32_t EN; /**< Enable Register */
+ __IOM uint32_t CFG0; /**< Configuration 0 Register */
+ __IOM uint32_t CFG1; /**< Configuration 1 Register */
+ __IOM uint32_t CFG2; /**< Configuration 2 Register */
+ __IOM uint32_t FRAMECFG; /**< Frame Format Register */
+ __IOM uint32_t DTXDATCFG; /**< Default TX DATA Register */
+ __IOM uint32_t IRHFCFG; /**< HF IrDA Mod Config Register */
+ __IOM uint32_t IRLFCFG; /**< LF IrDA Pulse Config Register */
+ __IOM uint32_t TIMINGCFG; /**< Timing Register */
+ __IOM uint32_t STARTFRAMECFG; /**< Start Frame Register */
+ __IOM uint32_t SIGFRAMECFG; /**< Signal Frame Register */
+ __IOM uint32_t CLKDIV; /**< Clock Divider Register */
+ __IOM uint32_t TRIGCTRL; /**< Trigger Control Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IM uint32_t RXDATA; /**< RX Data Register */
+ __IM uint32_t RXDATAP; /**< RX Data Peek Register */
+ __IOM uint32_t TXDATA; /**< TX Data Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IOM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
+ __IOM uint32_t DALICFG; /**< DALI Config Register */
+ uint32_t RESERVED0[41U]; /**< Reserved for future use */
+ uint32_t RESERVED1[1U]; /**< Reserved for future use */
+ uint32_t RESERVED2[959U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP version ID */
+ __IOM uint32_t EN_SET; /**< Enable Register */
+ __IOM uint32_t CFG0_SET; /**< Configuration 0 Register */
+ __IOM uint32_t CFG1_SET; /**< Configuration 1 Register */
+ __IOM uint32_t CFG2_SET; /**< Configuration 2 Register */
+ __IOM uint32_t FRAMECFG_SET; /**< Frame Format Register */
+ __IOM uint32_t DTXDATCFG_SET; /**< Default TX DATA Register */
+ __IOM uint32_t IRHFCFG_SET; /**< HF IrDA Mod Config Register */
+ __IOM uint32_t IRLFCFG_SET; /**< LF IrDA Pulse Config Register */
+ __IOM uint32_t TIMINGCFG_SET; /**< Timing Register */
+ __IOM uint32_t STARTFRAMECFG_SET; /**< Start Frame Register */
+ __IOM uint32_t SIGFRAMECFG_SET; /**< Signal Frame Register */
+ __IOM uint32_t CLKDIV_SET; /**< Clock Divider Register */
+ __IOM uint32_t TRIGCTRL_SET; /**< Trigger Control Register */
+ __IOM uint32_t CMD_SET; /**< Command Register */
+ __IM uint32_t RXDATA_SET; /**< RX Data Register */
+ __IM uint32_t RXDATAP_SET; /**< RX Data Peek Register */
+ __IOM uint32_t TXDATA_SET; /**< TX Data Register */
+ __IM uint32_t STATUS_SET; /**< Status Register */
+ __IOM uint32_t IF_SET; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
+ __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */
+ __IOM uint32_t DALICFG_SET; /**< DALI Config Register */
+ uint32_t RESERVED3[41U]; /**< Reserved for future use */
+ uint32_t RESERVED4[1U]; /**< Reserved for future use */
+ uint32_t RESERVED5[959U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP version ID */
+ __IOM uint32_t EN_CLR; /**< Enable Register */
+ __IOM uint32_t CFG0_CLR; /**< Configuration 0 Register */
+ __IOM uint32_t CFG1_CLR; /**< Configuration 1 Register */
+ __IOM uint32_t CFG2_CLR; /**< Configuration 2 Register */
+ __IOM uint32_t FRAMECFG_CLR; /**< Frame Format Register */
+ __IOM uint32_t DTXDATCFG_CLR; /**< Default TX DATA Register */
+ __IOM uint32_t IRHFCFG_CLR; /**< HF IrDA Mod Config Register */
+ __IOM uint32_t IRLFCFG_CLR; /**< LF IrDA Pulse Config Register */
+ __IOM uint32_t TIMINGCFG_CLR; /**< Timing Register */
+ __IOM uint32_t STARTFRAMECFG_CLR; /**< Start Frame Register */
+ __IOM uint32_t SIGFRAMECFG_CLR; /**< Signal Frame Register */
+ __IOM uint32_t CLKDIV_CLR; /**< Clock Divider Register */
+ __IOM uint32_t TRIGCTRL_CLR; /**< Trigger Control Register */
+ __IOM uint32_t CMD_CLR; /**< Command Register */
+ __IM uint32_t RXDATA_CLR; /**< RX Data Register */
+ __IM uint32_t RXDATAP_CLR; /**< RX Data Peek Register */
+ __IOM uint32_t TXDATA_CLR; /**< TX Data Register */
+ __IM uint32_t STATUS_CLR; /**< Status Register */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
+ __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */
+ __IOM uint32_t DALICFG_CLR; /**< DALI Config Register */
+ uint32_t RESERVED6[41U]; /**< Reserved for future use */
+ uint32_t RESERVED7[1U]; /**< Reserved for future use */
+ uint32_t RESERVED8[959U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP version ID */
+ __IOM uint32_t EN_TGL; /**< Enable Register */
+ __IOM uint32_t CFG0_TGL; /**< Configuration 0 Register */
+ __IOM uint32_t CFG1_TGL; /**< Configuration 1 Register */
+ __IOM uint32_t CFG2_TGL; /**< Configuration 2 Register */
+ __IOM uint32_t FRAMECFG_TGL; /**< Frame Format Register */
+ __IOM uint32_t DTXDATCFG_TGL; /**< Default TX DATA Register */
+ __IOM uint32_t IRHFCFG_TGL; /**< HF IrDA Mod Config Register */
+ __IOM uint32_t IRLFCFG_TGL; /**< LF IrDA Pulse Config Register */
+ __IOM uint32_t TIMINGCFG_TGL; /**< Timing Register */
+ __IOM uint32_t STARTFRAMECFG_TGL; /**< Start Frame Register */
+ __IOM uint32_t SIGFRAMECFG_TGL; /**< Signal Frame Register */
+ __IOM uint32_t CLKDIV_TGL; /**< Clock Divider Register */
+ __IOM uint32_t TRIGCTRL_TGL; /**< Trigger Control Register */
+ __IOM uint32_t CMD_TGL; /**< Command Register */
+ __IM uint32_t RXDATA_TGL; /**< RX Data Register */
+ __IM uint32_t RXDATAP_TGL; /**< RX Data Peek Register */
+ __IOM uint32_t TXDATA_TGL; /**< TX Data Register */
+ __IM uint32_t STATUS_TGL; /**< Status Register */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
+ __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */
+ __IOM uint32_t DALICFG_TGL; /**< DALI Config Register */
+ uint32_t RESERVED9[41U]; /**< Reserved for future use */
+ uint32_t RESERVED10[1U]; /**< Reserved for future use */
+} EUSART_TypeDef;
+/** @} End of group EFR32MG24_EUSART */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_EUSART
+ * @{
+ * @defgroup EFR32MG24_EUSART_BitFields EUSART Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for EUSART IPVERSION */
+#define _EUSART_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for EUSART_IPVERSION */
+#define _EUSART_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for EUSART_IPVERSION */
+#define _EUSART_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for EUSART_IPVERSION */
+#define _EUSART_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for EUSART_IPVERSION */
+#define _EUSART_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for EUSART_IPVERSION */
+#define EUSART_IPVERSION_IPVERSION_DEFAULT (_EUSART_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IPVERSION */
+
+/* Bit fields for EUSART EN */
+#define _EUSART_EN_RESETVALUE 0x00000000UL /**< Default value for EUSART_EN */
+#define _EUSART_EN_MASK 0x00000003UL /**< Mask for EUSART_EN */
+#define EUSART_EN_EN (0x1UL << 0) /**< Module enable */
+#define _EUSART_EN_EN_SHIFT 0 /**< Shift value for EUSART_EN */
+#define _EUSART_EN_EN_MASK 0x1UL /**< Bit mask for EUSART_EN */
+#define _EUSART_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_EN */
+#define EUSART_EN_EN_DEFAULT (_EUSART_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_EN */
+#define EUSART_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */
+#define _EUSART_EN_DISABLING_SHIFT 1 /**< Shift value for EUSART_DISABLING */
+#define _EUSART_EN_DISABLING_MASK 0x2UL /**< Bit mask for EUSART_DISABLING */
+#define _EUSART_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_EN */
+#define EUSART_EN_DISABLING_DEFAULT (_EUSART_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_EN */
+
+/* Bit fields for EUSART CFG0 */
+#define _EUSART_CFG0_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG0 */
+#define _EUSART_CFG0_MASK 0xC1D264FFUL /**< Mask for EUSART_CFG0 */
+#define EUSART_CFG0_SYNC (0x1UL << 0) /**< Synchronous Mode */
+#define _EUSART_CFG0_SYNC_SHIFT 0 /**< Shift value for EUSART_SYNC */
+#define _EUSART_CFG0_SYNC_MASK 0x1UL /**< Bit mask for EUSART_SYNC */
+#define _EUSART_CFG0_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */
+#define _EUSART_CFG0_SYNC_ASYNC 0x00000000UL /**< Mode ASYNC for EUSART_CFG0 */
+#define _EUSART_CFG0_SYNC_SYNC 0x00000001UL /**< Mode SYNC for EUSART_CFG0 */
+#define EUSART_CFG0_SYNC_DEFAULT (_EUSART_CFG0_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG0 */
+#define EUSART_CFG0_SYNC_ASYNC (_EUSART_CFG0_SYNC_ASYNC << 0) /**< Shifted mode ASYNC for EUSART_CFG0 */
+#define EUSART_CFG0_SYNC_SYNC (_EUSART_CFG0_SYNC_SYNC << 0) /**< Shifted mode SYNC for EUSART_CFG0 */
+#define EUSART_CFG0_LOOPBK (0x1UL << 1) /**< Loopback Enable */
+#define _EUSART_CFG0_LOOPBK_SHIFT 1 /**< Shift value for EUSART_LOOPBK */
+#define _EUSART_CFG0_LOOPBK_MASK 0x2UL /**< Bit mask for EUSART_LOOPBK */
+#define _EUSART_CFG0_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */
+#define _EUSART_CFG0_LOOPBK_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */
+#define _EUSART_CFG0_LOOPBK_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */
+#define EUSART_CFG0_LOOPBK_DEFAULT (_EUSART_CFG0_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG0 */
+#define EUSART_CFG0_LOOPBK_DISABLE (_EUSART_CFG0_LOOPBK_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG0 */
+#define EUSART_CFG0_LOOPBK_ENABLE (_EUSART_CFG0_LOOPBK_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG0 */
+#define EUSART_CFG0_CCEN (0x1UL << 2) /**< Collision Check Enable */
+#define _EUSART_CFG0_CCEN_SHIFT 2 /**< Shift value for EUSART_CCEN */
+#define _EUSART_CFG0_CCEN_MASK 0x4UL /**< Bit mask for EUSART_CCEN */
+#define _EUSART_CFG0_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */
+#define _EUSART_CFG0_CCEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */
+#define _EUSART_CFG0_CCEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */
+#define EUSART_CFG0_CCEN_DEFAULT (_EUSART_CFG0_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG0 */
+#define EUSART_CFG0_CCEN_DISABLE (_EUSART_CFG0_CCEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG0 */
+#define EUSART_CFG0_CCEN_ENABLE (_EUSART_CFG0_CCEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG0 */
+#define EUSART_CFG0_MPM (0x1UL << 3) /**< Multi-Processor Mode */
+#define _EUSART_CFG0_MPM_SHIFT 3 /**< Shift value for EUSART_MPM */
+#define _EUSART_CFG0_MPM_MASK 0x8UL /**< Bit mask for EUSART_MPM */
+#define _EUSART_CFG0_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */
+#define _EUSART_CFG0_MPM_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */
+#define _EUSART_CFG0_MPM_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */
+#define EUSART_CFG0_MPM_DEFAULT (_EUSART_CFG0_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG0 */
+#define EUSART_CFG0_MPM_DISABLE (_EUSART_CFG0_MPM_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG0 */
+#define EUSART_CFG0_MPM_ENABLE (_EUSART_CFG0_MPM_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG0 */
+#define EUSART_CFG0_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */
+#define _EUSART_CFG0_MPAB_SHIFT 4 /**< Shift value for EUSART_MPAB */
+#define _EUSART_CFG0_MPAB_MASK 0x10UL /**< Bit mask for EUSART_MPAB */
+#define _EUSART_CFG0_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */
+#define EUSART_CFG0_MPAB_DEFAULT (_EUSART_CFG0_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG0 */
+#define _EUSART_CFG0_OVS_SHIFT 5 /**< Shift value for EUSART_OVS */
+#define _EUSART_CFG0_OVS_MASK 0xE0UL /**< Bit mask for EUSART_OVS */
+#define _EUSART_CFG0_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */
+#define _EUSART_CFG0_OVS_X16 0x00000000UL /**< Mode X16 for EUSART_CFG0 */
+#define _EUSART_CFG0_OVS_X8 0x00000001UL /**< Mode X8 for EUSART_CFG0 */
+#define _EUSART_CFG0_OVS_X6 0x00000002UL /**< Mode X6 for EUSART_CFG0 */
+#define _EUSART_CFG0_OVS_X4 0x00000003UL /**< Mode X4 for EUSART_CFG0 */
+#define _EUSART_CFG0_OVS_DISABLE 0x00000004UL /**< Mode DISABLE for EUSART_CFG0 */
+#define EUSART_CFG0_OVS_DEFAULT (_EUSART_CFG0_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CFG0 */
+#define EUSART_CFG0_OVS_X16 (_EUSART_CFG0_OVS_X16 << 5) /**< Shifted mode X16 for EUSART_CFG0 */
+#define EUSART_CFG0_OVS_X8 (_EUSART_CFG0_OVS_X8 << 5) /**< Shifted mode X8 for EUSART_CFG0 */
+#define EUSART_CFG0_OVS_X6 (_EUSART_CFG0_OVS_X6 << 5) /**< Shifted mode X6 for EUSART_CFG0 */
+#define EUSART_CFG0_OVS_X4 (_EUSART_CFG0_OVS_X4 << 5) /**< Shifted mode X4 for EUSART_CFG0 */
+#define EUSART_CFG0_OVS_DISABLE (_EUSART_CFG0_OVS_DISABLE << 5) /**< Shifted mode DISABLE for EUSART_CFG0 */
+#define EUSART_CFG0_MSBF (0x1UL << 10) /**< Most Significant Bit First */
+#define _EUSART_CFG0_MSBF_SHIFT 10 /**< Shift value for EUSART_MSBF */
+#define _EUSART_CFG0_MSBF_MASK 0x400UL /**< Bit mask for EUSART_MSBF */
+#define _EUSART_CFG0_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */
+#define _EUSART_CFG0_MSBF_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */
+#define _EUSART_CFG0_MSBF_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */
+#define EUSART_CFG0_MSBF_DEFAULT (_EUSART_CFG0_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG0 */
+#define EUSART_CFG0_MSBF_DISABLE (_EUSART_CFG0_MSBF_DISABLE << 10) /**< Shifted mode DISABLE for EUSART_CFG0 */
+#define EUSART_CFG0_MSBF_ENABLE (_EUSART_CFG0_MSBF_ENABLE << 10) /**< Shifted mode ENABLE for EUSART_CFG0 */
+#define EUSART_CFG0_RXINV (0x1UL << 13) /**< Receiver Input Invert */
+#define _EUSART_CFG0_RXINV_SHIFT 13 /**< Shift value for EUSART_RXINV */
+#define _EUSART_CFG0_RXINV_MASK 0x2000UL /**< Bit mask for EUSART_RXINV */
+#define _EUSART_CFG0_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */
+#define _EUSART_CFG0_RXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */
+#define _EUSART_CFG0_RXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */
+#define EUSART_CFG0_RXINV_DEFAULT (_EUSART_CFG0_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_CFG0 */
+#define EUSART_CFG0_RXINV_DISABLE (_EUSART_CFG0_RXINV_DISABLE << 13) /**< Shifted mode DISABLE for EUSART_CFG0 */
+#define EUSART_CFG0_RXINV_ENABLE (_EUSART_CFG0_RXINV_ENABLE << 13) /**< Shifted mode ENABLE for EUSART_CFG0 */
+#define EUSART_CFG0_TXINV (0x1UL << 14) /**< Transmitter output Invert */
+#define _EUSART_CFG0_TXINV_SHIFT 14 /**< Shift value for EUSART_TXINV */
+#define _EUSART_CFG0_TXINV_MASK 0x4000UL /**< Bit mask for EUSART_TXINV */
+#define _EUSART_CFG0_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */
+#define _EUSART_CFG0_TXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */
+#define _EUSART_CFG0_TXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */
+#define EUSART_CFG0_TXINV_DEFAULT (_EUSART_CFG0_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for EUSART_CFG0 */
+#define EUSART_CFG0_TXINV_DISABLE (_EUSART_CFG0_TXINV_DISABLE << 14) /**< Shifted mode DISABLE for EUSART_CFG0 */
+#define EUSART_CFG0_TXINV_ENABLE (_EUSART_CFG0_TXINV_ENABLE << 14) /**< Shifted mode ENABLE for EUSART_CFG0 */
+#define EUSART_CFG0_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */
+#define _EUSART_CFG0_AUTOTRI_SHIFT 17 /**< Shift value for EUSART_AUTOTRI */
+#define _EUSART_CFG0_AUTOTRI_MASK 0x20000UL /**< Bit mask for EUSART_AUTOTRI */
+#define _EUSART_CFG0_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */
+#define _EUSART_CFG0_AUTOTRI_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */
+#define _EUSART_CFG0_AUTOTRI_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */
+#define EUSART_CFG0_AUTOTRI_DEFAULT (_EUSART_CFG0_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for EUSART_CFG0 */
+#define EUSART_CFG0_AUTOTRI_DISABLE (_EUSART_CFG0_AUTOTRI_DISABLE << 17) /**< Shifted mode DISABLE for EUSART_CFG0 */
+#define EUSART_CFG0_AUTOTRI_ENABLE (_EUSART_CFG0_AUTOTRI_ENABLE << 17) /**< Shifted mode ENABLE for EUSART_CFG0 */
+#define EUSART_CFG0_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */
+#define _EUSART_CFG0_SKIPPERRF_SHIFT 20 /**< Shift value for EUSART_SKIPPERRF */
+#define _EUSART_CFG0_SKIPPERRF_MASK 0x100000UL /**< Bit mask for EUSART_SKIPPERRF */
+#define _EUSART_CFG0_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */
+#define EUSART_CFG0_SKIPPERRF_DEFAULT (_EUSART_CFG0_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for EUSART_CFG0 */
+#define EUSART_CFG0_ERRSDMA (0x1UL << 22) /**< Halt DMA Read On Error */
+#define _EUSART_CFG0_ERRSDMA_SHIFT 22 /**< Shift value for EUSART_ERRSDMA */
+#define _EUSART_CFG0_ERRSDMA_MASK 0x400000UL /**< Bit mask for EUSART_ERRSDMA */
+#define _EUSART_CFG0_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */
+#define _EUSART_CFG0_ERRSDMA_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */
+#define _EUSART_CFG0_ERRSDMA_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */
+#define EUSART_CFG0_ERRSDMA_DEFAULT (_EUSART_CFG0_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG0 */
+#define EUSART_CFG0_ERRSDMA_DISABLE (_EUSART_CFG0_ERRSDMA_DISABLE << 22) /**< Shifted mode DISABLE for EUSART_CFG0 */
+#define EUSART_CFG0_ERRSDMA_ENABLE (_EUSART_CFG0_ERRSDMA_ENABLE << 22) /**< Shifted mode ENABLE for EUSART_CFG0 */
+#define EUSART_CFG0_ERRSRX (0x1UL << 23) /**< Disable RX On Error */
+#define _EUSART_CFG0_ERRSRX_SHIFT 23 /**< Shift value for EUSART_ERRSRX */
+#define _EUSART_CFG0_ERRSRX_MASK 0x800000UL /**< Bit mask for EUSART_ERRSRX */
+#define _EUSART_CFG0_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */
+#define _EUSART_CFG0_ERRSRX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */
+#define _EUSART_CFG0_ERRSRX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */
+#define EUSART_CFG0_ERRSRX_DEFAULT (_EUSART_CFG0_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for EUSART_CFG0 */
+#define EUSART_CFG0_ERRSRX_DISABLE (_EUSART_CFG0_ERRSRX_DISABLE << 23) /**< Shifted mode DISABLE for EUSART_CFG0 */
+#define EUSART_CFG0_ERRSRX_ENABLE (_EUSART_CFG0_ERRSRX_ENABLE << 23) /**< Shifted mode ENABLE for EUSART_CFG0 */
+#define EUSART_CFG0_ERRSTX (0x1UL << 24) /**< Disable TX On Error */
+#define _EUSART_CFG0_ERRSTX_SHIFT 24 /**< Shift value for EUSART_ERRSTX */
+#define _EUSART_CFG0_ERRSTX_MASK 0x1000000UL /**< Bit mask for EUSART_ERRSTX */
+#define _EUSART_CFG0_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */
+#define _EUSART_CFG0_ERRSTX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */
+#define _EUSART_CFG0_ERRSTX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */
+#define EUSART_CFG0_ERRSTX_DEFAULT (_EUSART_CFG0_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_CFG0 */
+#define EUSART_CFG0_ERRSTX_DISABLE (_EUSART_CFG0_ERRSTX_DISABLE << 24) /**< Shifted mode DISABLE for EUSART_CFG0 */
+#define EUSART_CFG0_ERRSTX_ENABLE (_EUSART_CFG0_ERRSTX_ENABLE << 24) /**< Shifted mode ENABLE for EUSART_CFG0 */
+#define EUSART_CFG0_MVDIS (0x1UL << 30) /**< Majority Vote Disable */
+#define _EUSART_CFG0_MVDIS_SHIFT 30 /**< Shift value for EUSART_MVDIS */
+#define _EUSART_CFG0_MVDIS_MASK 0x40000000UL /**< Bit mask for EUSART_MVDIS */
+#define _EUSART_CFG0_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */
+#define EUSART_CFG0_MVDIS_DEFAULT (_EUSART_CFG0_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for EUSART_CFG0 */
+#define EUSART_CFG0_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */
+#define _EUSART_CFG0_AUTOBAUDEN_SHIFT 31 /**< Shift value for EUSART_AUTOBAUDEN */
+#define _EUSART_CFG0_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for EUSART_AUTOBAUDEN */
+#define _EUSART_CFG0_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */
+#define EUSART_CFG0_AUTOBAUDEN_DEFAULT (_EUSART_CFG0_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EUSART_CFG0 */
+
+/* Bit fields for EUSART CFG1 */
+#define _EUSART_CFG1_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG1 */
+#define _EUSART_CFG1_MASK 0x7BCF8E7FUL /**< Mask for EUSART_CFG1 */
+#define EUSART_CFG1_DBGHALT (0x1UL << 0) /**< Debug halt */
+#define _EUSART_CFG1_DBGHALT_SHIFT 0 /**< Shift value for EUSART_DBGHALT */
+#define _EUSART_CFG1_DBGHALT_MASK 0x1UL /**< Bit mask for EUSART_DBGHALT */
+#define _EUSART_CFG1_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */
+#define _EUSART_CFG1_DBGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */
+#define _EUSART_CFG1_DBGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */
+#define EUSART_CFG1_DBGHALT_DEFAULT (_EUSART_CFG1_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG1 */
+#define EUSART_CFG1_DBGHALT_DISABLE (_EUSART_CFG1_DBGHALT_DISABLE << 0) /**< Shifted mode DISABLE for EUSART_CFG1 */
+#define EUSART_CFG1_DBGHALT_ENABLE (_EUSART_CFG1_DBGHALT_ENABLE << 0) /**< Shifted mode ENABLE for EUSART_CFG1 */
+#define EUSART_CFG1_CTSINV (0x1UL << 1) /**< Clear-to-send Invert Enable */
+#define _EUSART_CFG1_CTSINV_SHIFT 1 /**< Shift value for EUSART_CTSINV */
+#define _EUSART_CFG1_CTSINV_MASK 0x2UL /**< Bit mask for EUSART_CTSINV */
+#define _EUSART_CFG1_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */
+#define _EUSART_CFG1_CTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */
+#define _EUSART_CFG1_CTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */
+#define EUSART_CFG1_CTSINV_DEFAULT (_EUSART_CFG1_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG1 */
+#define EUSART_CFG1_CTSINV_DISABLE (_EUSART_CFG1_CTSINV_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG1 */
+#define EUSART_CFG1_CTSINV_ENABLE (_EUSART_CFG1_CTSINV_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG1 */
+#define EUSART_CFG1_CTSEN (0x1UL << 2) /**< Clear-to-send Enable */
+#define _EUSART_CFG1_CTSEN_SHIFT 2 /**< Shift value for EUSART_CTSEN */
+#define _EUSART_CFG1_CTSEN_MASK 0x4UL /**< Bit mask for EUSART_CTSEN */
+#define _EUSART_CFG1_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */
+#define _EUSART_CFG1_CTSEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */
+#define _EUSART_CFG1_CTSEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */
+#define EUSART_CFG1_CTSEN_DEFAULT (_EUSART_CFG1_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG1 */
+#define EUSART_CFG1_CTSEN_DISABLE (_EUSART_CFG1_CTSEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG1 */
+#define EUSART_CFG1_CTSEN_ENABLE (_EUSART_CFG1_CTSEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG1 */
+#define EUSART_CFG1_RTSINV (0x1UL << 3) /**< Request-to-send Invert Enable */
+#define _EUSART_CFG1_RTSINV_SHIFT 3 /**< Shift value for EUSART_RTSINV */
+#define _EUSART_CFG1_RTSINV_MASK 0x8UL /**< Bit mask for EUSART_RTSINV */
+#define _EUSART_CFG1_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */
+#define _EUSART_CFG1_RTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */
+#define _EUSART_CFG1_RTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */
+#define EUSART_CFG1_RTSINV_DEFAULT (_EUSART_CFG1_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG1 */
+#define EUSART_CFG1_RTSINV_DISABLE (_EUSART_CFG1_RTSINV_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG1 */
+#define EUSART_CFG1_RTSINV_ENABLE (_EUSART_CFG1_RTSINV_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG1 */
+#define _EUSART_CFG1_RXTIMEOUT_SHIFT 4 /**< Shift value for EUSART_RXTIMEOUT */
+#define _EUSART_CFG1_RXTIMEOUT_MASK 0x70UL /**< Bit mask for EUSART_RXTIMEOUT */
+#define _EUSART_CFG1_RXTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */
+#define _EUSART_CFG1_RXTIMEOUT_DISABLED 0x00000000UL /**< Mode DISABLED for EUSART_CFG1 */
+#define _EUSART_CFG1_RXTIMEOUT_ONEFRAME 0x00000001UL /**< Mode ONEFRAME for EUSART_CFG1 */
+#define _EUSART_CFG1_RXTIMEOUT_TWOFRAMES 0x00000002UL /**< Mode TWOFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RXTIMEOUT_THREEFRAMES 0x00000003UL /**< Mode THREEFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RXTIMEOUT_FOURFRAMES 0x00000004UL /**< Mode FOURFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RXTIMEOUT_FIVEFRAMES 0x00000005UL /**< Mode FIVEFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RXTIMEOUT_SIXFRAMES 0x00000006UL /**< Mode SIXFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RXTIMEOUT_SEVENFRAMES 0x00000007UL /**< Mode SEVENFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RXTIMEOUT_DEFAULT (_EUSART_CFG1_RXTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG1 */
+#define EUSART_CFG1_RXTIMEOUT_DISABLED (_EUSART_CFG1_RXTIMEOUT_DISABLED << 4) /**< Shifted mode DISABLED for EUSART_CFG1 */
+#define EUSART_CFG1_RXTIMEOUT_ONEFRAME (_EUSART_CFG1_RXTIMEOUT_ONEFRAME << 4) /**< Shifted mode ONEFRAME for EUSART_CFG1 */
+#define EUSART_CFG1_RXTIMEOUT_TWOFRAMES (_EUSART_CFG1_RXTIMEOUT_TWOFRAMES << 4) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RXTIMEOUT_THREEFRAMES (_EUSART_CFG1_RXTIMEOUT_THREEFRAMES << 4) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RXTIMEOUT_FOURFRAMES (_EUSART_CFG1_RXTIMEOUT_FOURFRAMES << 4) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RXTIMEOUT_FIVEFRAMES (_EUSART_CFG1_RXTIMEOUT_FIVEFRAMES << 4) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RXTIMEOUT_SIXFRAMES (_EUSART_CFG1_RXTIMEOUT_SIXFRAMES << 4) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RXTIMEOUT_SEVENFRAMES (_EUSART_CFG1_RXTIMEOUT_SEVENFRAMES << 4) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_TXDMAWU (0x1UL << 9) /**< Transmitter DMA Wakeup */
+#define _EUSART_CFG1_TXDMAWU_SHIFT 9 /**< Shift value for EUSART_TXDMAWU */
+#define _EUSART_CFG1_TXDMAWU_MASK 0x200UL /**< Bit mask for EUSART_TXDMAWU */
+#define _EUSART_CFG1_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */
+#define EUSART_CFG1_TXDMAWU_DEFAULT (_EUSART_CFG1_TXDMAWU_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_CFG1 */
+#define EUSART_CFG1_RXDMAWU (0x1UL << 10) /**< Receiver DMA Wakeup */
+#define _EUSART_CFG1_RXDMAWU_SHIFT 10 /**< Shift value for EUSART_RXDMAWU */
+#define _EUSART_CFG1_RXDMAWU_MASK 0x400UL /**< Bit mask for EUSART_RXDMAWU */
+#define _EUSART_CFG1_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */
+#define EUSART_CFG1_RXDMAWU_DEFAULT (_EUSART_CFG1_RXDMAWU_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG1 */
+#define EUSART_CFG1_SFUBRX (0x1UL << 11) /**< Start Frame Unblock Receiver */
+#define _EUSART_CFG1_SFUBRX_SHIFT 11 /**< Shift value for EUSART_SFUBRX */
+#define _EUSART_CFG1_SFUBRX_MASK 0x800UL /**< Bit mask for EUSART_SFUBRX */
+#define _EUSART_CFG1_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */
+#define EUSART_CFG1_SFUBRX_DEFAULT (_EUSART_CFG1_SFUBRX_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_CFG1 */
+#define EUSART_CFG1_RXPRSEN (0x1UL << 15) /**< PRS RX Enable */
+#define _EUSART_CFG1_RXPRSEN_SHIFT 15 /**< Shift value for EUSART_RXPRSEN */
+#define _EUSART_CFG1_RXPRSEN_MASK 0x8000UL /**< Bit mask for EUSART_RXPRSEN */
+#define _EUSART_CFG1_RXPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */
+#define EUSART_CFG1_RXPRSEN_DEFAULT (_EUSART_CFG1_RXPRSEN_DEFAULT << 15) /**< Shifted mode DEFAULT for EUSART_CFG1 */
+#define _EUSART_CFG1_TXFIW_SHIFT 16 /**< Shift value for EUSART_TXFIW */
+#define _EUSART_CFG1_TXFIW_MASK 0xF0000UL /**< Bit mask for EUSART_TXFIW */
+#define _EUSART_CFG1_TXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */
+#define _EUSART_CFG1_TXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */
+#define _EUSART_CFG1_TXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_TXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_TXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_TXFIW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_TXFIW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_TXFIW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_TXFIW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_TXFIW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_TXFIW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_TXFIW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_TXFIW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_TXFIW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_TXFIW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_TXFIW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_TXFIW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_TXFIW_DEFAULT (_EUSART_CFG1_TXFIW_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_CFG1 */
+#define EUSART_CFG1_TXFIW_ONEFRAME (_EUSART_CFG1_TXFIW_ONEFRAME << 16) /**< Shifted mode ONEFRAME for EUSART_CFG1 */
+#define EUSART_CFG1_TXFIW_TWOFRAMES (_EUSART_CFG1_TXFIW_TWOFRAMES << 16) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_TXFIW_THREEFRAMES (_EUSART_CFG1_TXFIW_THREEFRAMES << 16) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_TXFIW_FOURFRAMES (_EUSART_CFG1_TXFIW_FOURFRAMES << 16) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_TXFIW_FIVEFRAMES (_EUSART_CFG1_TXFIW_FIVEFRAMES << 16) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_TXFIW_SIXFRAMES (_EUSART_CFG1_TXFIW_SIXFRAMES << 16) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_TXFIW_SEVENFRAMES (_EUSART_CFG1_TXFIW_SEVENFRAMES << 16) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_TXFIW_EIGHTFRAMES (_EUSART_CFG1_TXFIW_EIGHTFRAMES << 16) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_TXFIW_NINEFRAMES (_EUSART_CFG1_TXFIW_NINEFRAMES << 16) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_TXFIW_TENFRAMES (_EUSART_CFG1_TXFIW_TENFRAMES << 16) /**< Shifted mode TENFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_TXFIW_ELEVENFRAMES (_EUSART_CFG1_TXFIW_ELEVENFRAMES << 16) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_TXFIW_TWELVEFRAMES (_EUSART_CFG1_TXFIW_TWELVEFRAMES << 16) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_TXFIW_THIRTEENFRAMES (_EUSART_CFG1_TXFIW_THIRTEENFRAMES << 16) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_TXFIW_FOURTEENFRAMES (_EUSART_CFG1_TXFIW_FOURTEENFRAMES << 16) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_TXFIW_FIFTEENFRAMES (_EUSART_CFG1_TXFIW_FIFTEENFRAMES << 16) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_TXFIW_SIXTEENFRAMES (_EUSART_CFG1_TXFIW_SIXTEENFRAMES << 16) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RTSRXFW_SHIFT 22 /**< Shift value for EUSART_RTSRXFW */
+#define _EUSART_CFG1_RTSRXFW_MASK 0x3C00000UL /**< Bit mask for EUSART_RTSRXFW */
+#define _EUSART_CFG1_RTSRXFW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */
+#define _EUSART_CFG1_RTSRXFW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */
+#define _EUSART_CFG1_RTSRXFW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RTSRXFW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RTSRXFW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RTSRXFW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RTSRXFW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RTSRXFW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RTSRXFW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RTSRXFW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RTSRXFW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RTSRXFW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RTSRXFW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RTSRXFW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RTSRXFW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RTSRXFW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RTSRXFW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RTSRXFW_DEFAULT (_EUSART_CFG1_RTSRXFW_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG1 */
+#define EUSART_CFG1_RTSRXFW_ONEFRAME (_EUSART_CFG1_RTSRXFW_ONEFRAME << 22) /**< Shifted mode ONEFRAME for EUSART_CFG1 */
+#define EUSART_CFG1_RTSRXFW_TWOFRAMES (_EUSART_CFG1_RTSRXFW_TWOFRAMES << 22) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RTSRXFW_THREEFRAMES (_EUSART_CFG1_RTSRXFW_THREEFRAMES << 22) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RTSRXFW_FOURFRAMES (_EUSART_CFG1_RTSRXFW_FOURFRAMES << 22) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RTSRXFW_FIVEFRAMES (_EUSART_CFG1_RTSRXFW_FIVEFRAMES << 22) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RTSRXFW_SIXFRAMES (_EUSART_CFG1_RTSRXFW_SIXFRAMES << 22) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RTSRXFW_SEVENFRAMES (_EUSART_CFG1_RTSRXFW_SEVENFRAMES << 22) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RTSRXFW_EIGHTFRAMES (_EUSART_CFG1_RTSRXFW_EIGHTFRAMES << 22) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RTSRXFW_NINEFRAMES (_EUSART_CFG1_RTSRXFW_NINEFRAMES << 22) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RTSRXFW_TENFRAMES (_EUSART_CFG1_RTSRXFW_TENFRAMES << 22) /**< Shifted mode TENFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RTSRXFW_ELEVENFRAMES (_EUSART_CFG1_RTSRXFW_ELEVENFRAMES << 22) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RTSRXFW_TWELVEFRAMES (_EUSART_CFG1_RTSRXFW_TWELVEFRAMES << 22) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RTSRXFW_THIRTEENFRAMES (_EUSART_CFG1_RTSRXFW_THIRTEENFRAMES << 22) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RTSRXFW_FOURTEENFRAMES (_EUSART_CFG1_RTSRXFW_FOURTEENFRAMES << 22) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RTSRXFW_FIFTEENFRAMES (_EUSART_CFG1_RTSRXFW_FIFTEENFRAMES << 22) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RTSRXFW_SIXTEENFRAMES (_EUSART_CFG1_RTSRXFW_SIXTEENFRAMES << 22) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RXFIW_SHIFT 27 /**< Shift value for EUSART_RXFIW */
+#define _EUSART_CFG1_RXFIW_MASK 0x78000000UL /**< Bit mask for EUSART_RXFIW */
+#define _EUSART_CFG1_RXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */
+#define _EUSART_CFG1_RXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */
+#define _EUSART_CFG1_RXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RXFIW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RXFIW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RXFIW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RXFIW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RXFIW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RXFIW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RXFIW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RXFIW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RXFIW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RXFIW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RXFIW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */
+#define _EUSART_CFG1_RXFIW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RXFIW_DEFAULT (_EUSART_CFG1_RXFIW_DEFAULT << 27) /**< Shifted mode DEFAULT for EUSART_CFG1 */
+#define EUSART_CFG1_RXFIW_ONEFRAME (_EUSART_CFG1_RXFIW_ONEFRAME << 27) /**< Shifted mode ONEFRAME for EUSART_CFG1 */
+#define EUSART_CFG1_RXFIW_TWOFRAMES (_EUSART_CFG1_RXFIW_TWOFRAMES << 27) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RXFIW_THREEFRAMES (_EUSART_CFG1_RXFIW_THREEFRAMES << 27) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RXFIW_FOURFRAMES (_EUSART_CFG1_RXFIW_FOURFRAMES << 27) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RXFIW_FIVEFRAMES (_EUSART_CFG1_RXFIW_FIVEFRAMES << 27) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RXFIW_SIXFRAMES (_EUSART_CFG1_RXFIW_SIXFRAMES << 27) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RXFIW_SEVENFRAMES (_EUSART_CFG1_RXFIW_SEVENFRAMES << 27) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RXFIW_EIGHTFRAMES (_EUSART_CFG1_RXFIW_EIGHTFRAMES << 27) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RXFIW_NINEFRAMES (_EUSART_CFG1_RXFIW_NINEFRAMES << 27) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RXFIW_TENFRAMES (_EUSART_CFG1_RXFIW_TENFRAMES << 27) /**< Shifted mode TENFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RXFIW_ELEVENFRAMES (_EUSART_CFG1_RXFIW_ELEVENFRAMES << 27) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RXFIW_TWELVEFRAMES (_EUSART_CFG1_RXFIW_TWELVEFRAMES << 27) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RXFIW_THIRTEENFRAMES (_EUSART_CFG1_RXFIW_THIRTEENFRAMES << 27) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RXFIW_FOURTEENFRAMES (_EUSART_CFG1_RXFIW_FOURTEENFRAMES << 27) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RXFIW_FIFTEENFRAMES (_EUSART_CFG1_RXFIW_FIFTEENFRAMES << 27) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */
+#define EUSART_CFG1_RXFIW_SIXTEENFRAMES (_EUSART_CFG1_RXFIW_SIXTEENFRAMES << 27) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */
+
+/* Bit fields for EUSART CFG2 */
+#define _EUSART_CFG2_RESETVALUE 0x00000020UL /**< Default value for EUSART_CFG2 */
+#define _EUSART_CFG2_MASK 0xFF0000FFUL /**< Mask for EUSART_CFG2 */
+#define EUSART_CFG2_MASTER (0x1UL << 0) /**< Main mode */
+#define _EUSART_CFG2_MASTER_SHIFT 0 /**< Shift value for EUSART_MASTER */
+#define _EUSART_CFG2_MASTER_MASK 0x1UL /**< Bit mask for EUSART_MASTER */
+#define _EUSART_CFG2_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */
+#define _EUSART_CFG2_MASTER_SLAVE 0x00000000UL /**< Mode SLAVE for EUSART_CFG2 */
+#define _EUSART_CFG2_MASTER_MASTER 0x00000001UL /**< Mode MASTER for EUSART_CFG2 */
+#define EUSART_CFG2_MASTER_DEFAULT (_EUSART_CFG2_MASTER_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG2 */
+#define EUSART_CFG2_MASTER_SLAVE (_EUSART_CFG2_MASTER_SLAVE << 0) /**< Shifted mode SLAVE for EUSART_CFG2 */
+#define EUSART_CFG2_MASTER_MASTER (_EUSART_CFG2_MASTER_MASTER << 0) /**< Shifted mode MASTER for EUSART_CFG2 */
+#define EUSART_CFG2_CLKPOL (0x1UL << 1) /**< Clock Polarity */
+#define _EUSART_CFG2_CLKPOL_SHIFT 1 /**< Shift value for EUSART_CLKPOL */
+#define _EUSART_CFG2_CLKPOL_MASK 0x2UL /**< Bit mask for EUSART_CLKPOL */
+#define _EUSART_CFG2_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */
+#define _EUSART_CFG2_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for EUSART_CFG2 */
+#define _EUSART_CFG2_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for EUSART_CFG2 */
+#define EUSART_CFG2_CLKPOL_DEFAULT (_EUSART_CFG2_CLKPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG2 */
+#define EUSART_CFG2_CLKPOL_IDLELOW (_EUSART_CFG2_CLKPOL_IDLELOW << 1) /**< Shifted mode IDLELOW for EUSART_CFG2 */
+#define EUSART_CFG2_CLKPOL_IDLEHIGH (_EUSART_CFG2_CLKPOL_IDLEHIGH << 1) /**< Shifted mode IDLEHIGH for EUSART_CFG2 */
+#define EUSART_CFG2_CLKPHA (0x1UL << 2) /**< Clock Edge for Setup/Sample */
+#define _EUSART_CFG2_CLKPHA_SHIFT 2 /**< Shift value for EUSART_CLKPHA */
+#define _EUSART_CFG2_CLKPHA_MASK 0x4UL /**< Bit mask for EUSART_CLKPHA */
+#define _EUSART_CFG2_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */
+#define _EUSART_CFG2_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for EUSART_CFG2 */
+#define _EUSART_CFG2_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for EUSART_CFG2 */
+#define EUSART_CFG2_CLKPHA_DEFAULT (_EUSART_CFG2_CLKPHA_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG2 */
+#define EUSART_CFG2_CLKPHA_SAMPLELEADING (_EUSART_CFG2_CLKPHA_SAMPLELEADING << 2) /**< Shifted mode SAMPLELEADING for EUSART_CFG2 */
+#define EUSART_CFG2_CLKPHA_SAMPLETRAILING (_EUSART_CFG2_CLKPHA_SAMPLETRAILING << 2) /**< Shifted mode SAMPLETRAILING for EUSART_CFG2 */
+#define EUSART_CFG2_CSINV (0x1UL << 3) /**< Chip Select Invert */
+#define _EUSART_CFG2_CSINV_SHIFT 3 /**< Shift value for EUSART_CSINV */
+#define _EUSART_CFG2_CSINV_MASK 0x8UL /**< Bit mask for EUSART_CSINV */
+#define _EUSART_CFG2_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */
+#define _EUSART_CFG2_CSINV_AL 0x00000000UL /**< Mode AL for EUSART_CFG2 */
+#define _EUSART_CFG2_CSINV_AH 0x00000001UL /**< Mode AH for EUSART_CFG2 */
+#define EUSART_CFG2_CSINV_DEFAULT (_EUSART_CFG2_CSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG2 */
+#define EUSART_CFG2_CSINV_AL (_EUSART_CFG2_CSINV_AL << 3) /**< Shifted mode AL for EUSART_CFG2 */
+#define EUSART_CFG2_CSINV_AH (_EUSART_CFG2_CSINV_AH << 3) /**< Shifted mode AH for EUSART_CFG2 */
+#define EUSART_CFG2_AUTOTX (0x1UL << 4) /**< Always Transmit When RXFIFO Not Full */
+#define _EUSART_CFG2_AUTOTX_SHIFT 4 /**< Shift value for EUSART_AUTOTX */
+#define _EUSART_CFG2_AUTOTX_MASK 0x10UL /**< Bit mask for EUSART_AUTOTX */
+#define _EUSART_CFG2_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */
+#define EUSART_CFG2_AUTOTX_DEFAULT (_EUSART_CFG2_AUTOTX_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG2 */
+#define EUSART_CFG2_AUTOCS (0x1UL << 5) /**< Automatic Chip Select */
+#define _EUSART_CFG2_AUTOCS_SHIFT 5 /**< Shift value for EUSART_AUTOCS */
+#define _EUSART_CFG2_AUTOCS_MASK 0x20UL /**< Bit mask for EUSART_AUTOCS */
+#define _EUSART_CFG2_AUTOCS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_CFG2 */
+#define EUSART_CFG2_AUTOCS_DEFAULT (_EUSART_CFG2_AUTOCS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CFG2 */
+#define EUSART_CFG2_CLKPRSEN (0x1UL << 6) /**< PRS CLK Enable */
+#define _EUSART_CFG2_CLKPRSEN_SHIFT 6 /**< Shift value for EUSART_CLKPRSEN */
+#define _EUSART_CFG2_CLKPRSEN_MASK 0x40UL /**< Bit mask for EUSART_CLKPRSEN */
+#define _EUSART_CFG2_CLKPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */
+#define EUSART_CFG2_CLKPRSEN_DEFAULT (_EUSART_CFG2_CLKPRSEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_CFG2 */
+#define EUSART_CFG2_FORCELOAD (0x1UL << 7) /**< Force Load to Shift Register */
+#define _EUSART_CFG2_FORCELOAD_SHIFT 7 /**< Shift value for EUSART_FORCELOAD */
+#define _EUSART_CFG2_FORCELOAD_MASK 0x80UL /**< Bit mask for EUSART_FORCELOAD */
+#define _EUSART_CFG2_FORCELOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */
+#define EUSART_CFG2_FORCELOAD_DEFAULT (_EUSART_CFG2_FORCELOAD_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_CFG2 */
+#define _EUSART_CFG2_SDIV_SHIFT 24 /**< Shift value for EUSART_SDIV */
+#define _EUSART_CFG2_SDIV_MASK 0xFF000000UL /**< Bit mask for EUSART_SDIV */
+#define _EUSART_CFG2_SDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */
+#define EUSART_CFG2_SDIV_DEFAULT (_EUSART_CFG2_SDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_CFG2 */
+
+/* Bit fields for EUSART FRAMECFG */
+#define _EUSART_FRAMECFG_RESETVALUE 0x00001002UL /**< Default value for EUSART_FRAMECFG */
+#define _EUSART_FRAMECFG_MASK 0x0000330FUL /**< Mask for EUSART_FRAMECFG */
+#define _EUSART_FRAMECFG_DATABITS_SHIFT 0 /**< Shift value for EUSART_DATABITS */
+#define _EUSART_FRAMECFG_DATABITS_MASK 0xFUL /**< Bit mask for EUSART_DATABITS */
+#define _EUSART_FRAMECFG_DATABITS_DEFAULT 0x00000002UL /**< Mode DEFAULT for EUSART_FRAMECFG */
+#define _EUSART_FRAMECFG_DATABITS_SEVEN 0x00000001UL /**< Mode SEVEN for EUSART_FRAMECFG */
+#define _EUSART_FRAMECFG_DATABITS_EIGHT 0x00000002UL /**< Mode EIGHT for EUSART_FRAMECFG */
+#define _EUSART_FRAMECFG_DATABITS_NINE 0x00000003UL /**< Mode NINE for EUSART_FRAMECFG */
+#define _EUSART_FRAMECFG_DATABITS_TEN 0x00000004UL /**< Mode TEN for EUSART_FRAMECFG */
+#define _EUSART_FRAMECFG_DATABITS_ELEVEN 0x00000005UL /**< Mode ELEVEN for EUSART_FRAMECFG */
+#define _EUSART_FRAMECFG_DATABITS_TWELVE 0x00000006UL /**< Mode TWELVE for EUSART_FRAMECFG */
+#define _EUSART_FRAMECFG_DATABITS_THIRTEEN 0x00000007UL /**< Mode THIRTEEN for EUSART_FRAMECFG */
+#define _EUSART_FRAMECFG_DATABITS_FOURTEEN 0x00000008UL /**< Mode FOURTEEN for EUSART_FRAMECFG */
+#define _EUSART_FRAMECFG_DATABITS_FIFTEEN 0x00000009UL /**< Mode FIFTEEN for EUSART_FRAMECFG */
+#define _EUSART_FRAMECFG_DATABITS_SIXTEEN 0x0000000AUL /**< Mode SIXTEEN for EUSART_FRAMECFG */
+#define EUSART_FRAMECFG_DATABITS_DEFAULT (_EUSART_FRAMECFG_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */
+#define EUSART_FRAMECFG_DATABITS_SEVEN (_EUSART_FRAMECFG_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for EUSART_FRAMECFG */
+#define EUSART_FRAMECFG_DATABITS_EIGHT (_EUSART_FRAMECFG_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for EUSART_FRAMECFG */
+#define EUSART_FRAMECFG_DATABITS_NINE (_EUSART_FRAMECFG_DATABITS_NINE << 0) /**< Shifted mode NINE for EUSART_FRAMECFG */
+#define EUSART_FRAMECFG_DATABITS_TEN (_EUSART_FRAMECFG_DATABITS_TEN << 0) /**< Shifted mode TEN for EUSART_FRAMECFG */
+#define EUSART_FRAMECFG_DATABITS_ELEVEN (_EUSART_FRAMECFG_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for EUSART_FRAMECFG */
+#define EUSART_FRAMECFG_DATABITS_TWELVE (_EUSART_FRAMECFG_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for EUSART_FRAMECFG */
+#define EUSART_FRAMECFG_DATABITS_THIRTEEN (_EUSART_FRAMECFG_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for EUSART_FRAMECFG */
+#define EUSART_FRAMECFG_DATABITS_FOURTEEN (_EUSART_FRAMECFG_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for EUSART_FRAMECFG */
+#define EUSART_FRAMECFG_DATABITS_FIFTEEN (_EUSART_FRAMECFG_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for EUSART_FRAMECFG */
+#define EUSART_FRAMECFG_DATABITS_SIXTEEN (_EUSART_FRAMECFG_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for EUSART_FRAMECFG */
+#define _EUSART_FRAMECFG_PARITY_SHIFT 8 /**< Shift value for EUSART_PARITY */
+#define _EUSART_FRAMECFG_PARITY_MASK 0x300UL /**< Bit mask for EUSART_PARITY */
+#define _EUSART_FRAMECFG_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_FRAMECFG */
+#define _EUSART_FRAMECFG_PARITY_NONE 0x00000000UL /**< Mode NONE for EUSART_FRAMECFG */
+#define _EUSART_FRAMECFG_PARITY_EVEN 0x00000002UL /**< Mode EVEN for EUSART_FRAMECFG */
+#define _EUSART_FRAMECFG_PARITY_ODD 0x00000003UL /**< Mode ODD for EUSART_FRAMECFG */
+#define EUSART_FRAMECFG_PARITY_DEFAULT (_EUSART_FRAMECFG_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */
+#define EUSART_FRAMECFG_PARITY_NONE (_EUSART_FRAMECFG_PARITY_NONE << 8) /**< Shifted mode NONE for EUSART_FRAMECFG */
+#define EUSART_FRAMECFG_PARITY_EVEN (_EUSART_FRAMECFG_PARITY_EVEN << 8) /**< Shifted mode EVEN for EUSART_FRAMECFG */
+#define EUSART_FRAMECFG_PARITY_ODD (_EUSART_FRAMECFG_PARITY_ODD << 8) /**< Shifted mode ODD for EUSART_FRAMECFG */
+#define _EUSART_FRAMECFG_STOPBITS_SHIFT 12 /**< Shift value for EUSART_STOPBITS */
+#define _EUSART_FRAMECFG_STOPBITS_MASK 0x3000UL /**< Bit mask for EUSART_STOPBITS */
+#define _EUSART_FRAMECFG_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_FRAMECFG */
+#define _EUSART_FRAMECFG_STOPBITS_HALF 0x00000000UL /**< Mode HALF for EUSART_FRAMECFG */
+#define _EUSART_FRAMECFG_STOPBITS_ONE 0x00000001UL /**< Mode ONE for EUSART_FRAMECFG */
+#define _EUSART_FRAMECFG_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for EUSART_FRAMECFG */
+#define _EUSART_FRAMECFG_STOPBITS_TWO 0x00000003UL /**< Mode TWO for EUSART_FRAMECFG */
+#define EUSART_FRAMECFG_STOPBITS_DEFAULT (_EUSART_FRAMECFG_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */
+#define EUSART_FRAMECFG_STOPBITS_HALF (_EUSART_FRAMECFG_STOPBITS_HALF << 12) /**< Shifted mode HALF for EUSART_FRAMECFG */
+#define EUSART_FRAMECFG_STOPBITS_ONE (_EUSART_FRAMECFG_STOPBITS_ONE << 12) /**< Shifted mode ONE for EUSART_FRAMECFG */
+#define EUSART_FRAMECFG_STOPBITS_ONEANDAHALF (_EUSART_FRAMECFG_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for EUSART_FRAMECFG*/
+#define EUSART_FRAMECFG_STOPBITS_TWO (_EUSART_FRAMECFG_STOPBITS_TWO << 12) /**< Shifted mode TWO for EUSART_FRAMECFG */
+
+/* Bit fields for EUSART DTXDATCFG */
+#define _EUSART_DTXDATCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_DTXDATCFG */
+#define _EUSART_DTXDATCFG_MASK 0x0000FFFFUL /**< Mask for EUSART_DTXDATCFG */
+#define _EUSART_DTXDATCFG_DTXDAT_SHIFT 0 /**< Shift value for EUSART_DTXDAT */
+#define _EUSART_DTXDATCFG_DTXDAT_MASK 0xFFFFUL /**< Bit mask for EUSART_DTXDAT */
+#define _EUSART_DTXDATCFG_DTXDAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DTXDATCFG */
+#define EUSART_DTXDATCFG_DTXDAT_DEFAULT (_EUSART_DTXDATCFG_DTXDAT_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_DTXDATCFG */
+
+/* Bit fields for EUSART IRHFCFG */
+#define _EUSART_IRHFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRHFCFG */
+#define _EUSART_IRHFCFG_MASK 0x0000000FUL /**< Mask for EUSART_IRHFCFG */
+#define EUSART_IRHFCFG_IRHFEN (0x1UL << 0) /**< Enable IrDA Module */
+#define _EUSART_IRHFCFG_IRHFEN_SHIFT 0 /**< Shift value for EUSART_IRHFEN */
+#define _EUSART_IRHFCFG_IRHFEN_MASK 0x1UL /**< Bit mask for EUSART_IRHFEN */
+#define _EUSART_IRHFCFG_IRHFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */
+#define EUSART_IRHFCFG_IRHFEN_DEFAULT (_EUSART_IRHFCFG_IRHFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */
+#define _EUSART_IRHFCFG_IRHFPW_SHIFT 1 /**< Shift value for EUSART_IRHFPW */
+#define _EUSART_IRHFCFG_IRHFPW_MASK 0x6UL /**< Bit mask for EUSART_IRHFPW */
+#define _EUSART_IRHFCFG_IRHFPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */
+#define _EUSART_IRHFCFG_IRHFPW_ONE 0x00000000UL /**< Mode ONE for EUSART_IRHFCFG */
+#define _EUSART_IRHFCFG_IRHFPW_TWO 0x00000001UL /**< Mode TWO for EUSART_IRHFCFG */
+#define _EUSART_IRHFCFG_IRHFPW_THREE 0x00000002UL /**< Mode THREE for EUSART_IRHFCFG */
+#define _EUSART_IRHFCFG_IRHFPW_FOUR 0x00000003UL /**< Mode FOUR for EUSART_IRHFCFG */
+#define EUSART_IRHFCFG_IRHFPW_DEFAULT (_EUSART_IRHFCFG_IRHFPW_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */
+#define EUSART_IRHFCFG_IRHFPW_ONE (_EUSART_IRHFCFG_IRHFPW_ONE << 1) /**< Shifted mode ONE for EUSART_IRHFCFG */
+#define EUSART_IRHFCFG_IRHFPW_TWO (_EUSART_IRHFCFG_IRHFPW_TWO << 1) /**< Shifted mode TWO for EUSART_IRHFCFG */
+#define EUSART_IRHFCFG_IRHFPW_THREE (_EUSART_IRHFCFG_IRHFPW_THREE << 1) /**< Shifted mode THREE for EUSART_IRHFCFG */
+#define EUSART_IRHFCFG_IRHFPW_FOUR (_EUSART_IRHFCFG_IRHFPW_FOUR << 1) /**< Shifted mode FOUR for EUSART_IRHFCFG */
+#define EUSART_IRHFCFG_IRHFFILT (0x1UL << 3) /**< IrDA RX Filter */
+#define _EUSART_IRHFCFG_IRHFFILT_SHIFT 3 /**< Shift value for EUSART_IRHFFILT */
+#define _EUSART_IRHFCFG_IRHFFILT_MASK 0x8UL /**< Bit mask for EUSART_IRHFFILT */
+#define _EUSART_IRHFCFG_IRHFFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */
+#define _EUSART_IRHFCFG_IRHFFILT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_IRHFCFG */
+#define _EUSART_IRHFCFG_IRHFFILT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_IRHFCFG */
+#define EUSART_IRHFCFG_IRHFFILT_DEFAULT (_EUSART_IRHFCFG_IRHFFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */
+#define EUSART_IRHFCFG_IRHFFILT_DISABLE (_EUSART_IRHFCFG_IRHFFILT_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_IRHFCFG */
+#define EUSART_IRHFCFG_IRHFFILT_ENABLE (_EUSART_IRHFCFG_IRHFFILT_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_IRHFCFG */
+
+/* Bit fields for EUSART IRLFCFG */
+#define _EUSART_IRLFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRLFCFG */
+#define _EUSART_IRLFCFG_MASK 0x00000001UL /**< Mask for EUSART_IRLFCFG */
+#define EUSART_IRLFCFG_IRLFEN (0x1UL << 0) /**< Pulse Generator/Extender Enable */
+#define _EUSART_IRLFCFG_IRLFEN_SHIFT 0 /**< Shift value for EUSART_IRLFEN */
+#define _EUSART_IRLFCFG_IRLFEN_MASK 0x1UL /**< Bit mask for EUSART_IRLFEN */
+#define _EUSART_IRLFCFG_IRLFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRLFCFG */
+#define EUSART_IRLFCFG_IRLFEN_DEFAULT (_EUSART_IRLFCFG_IRLFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRLFCFG */
+
+/* Bit fields for EUSART TIMINGCFG */
+#define _EUSART_TIMINGCFG_RESETVALUE 0x00050000UL /**< Default value for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_MASK 0x000F7773UL /**< Mask for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_TXDELAY_SHIFT 0 /**< Shift value for EUSART_TXDELAY */
+#define _EUSART_TIMINGCFG_TXDELAY_MASK 0x3UL /**< Bit mask for EUSART_TXDELAY */
+#define _EUSART_TIMINGCFG_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_TXDELAY_NONE 0x00000000UL /**< Mode NONE for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_TXDELAY_TRIPPLE 0x00000003UL /**< Mode TRIPPLE for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_TXDELAY_DEFAULT (_EUSART_TIMINGCFG_TXDELAY_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_TXDELAY_NONE (_EUSART_TIMINGCFG_TXDELAY_NONE << 0) /**< Shifted mode NONE for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_TXDELAY_SINGLE (_EUSART_TIMINGCFG_TXDELAY_SINGLE << 0) /**< Shifted mode SINGLE for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_TXDELAY_DOUBLE (_EUSART_TIMINGCFG_TXDELAY_DOUBLE << 0) /**< Shifted mode DOUBLE for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_TXDELAY_TRIPPLE (_EUSART_TIMINGCFG_TXDELAY_TRIPPLE << 0) /**< Shifted mode TRIPPLE for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_CSSETUP_SHIFT 4 /**< Shift value for EUSART_CSSETUP */
+#define _EUSART_TIMINGCFG_CSSETUP_MASK 0x70UL /**< Bit mask for EUSART_CSSETUP */
+#define _EUSART_TIMINGCFG_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_CSSETUP_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_CSSETUP_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_CSSETUP_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_CSSETUP_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_CSSETUP_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_CSSETUP_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_CSSETUP_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_CSSETUP_DEFAULT (_EUSART_TIMINGCFG_CSSETUP_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_CSSETUP_ZERO (_EUSART_TIMINGCFG_CSSETUP_ZERO << 4) /**< Shifted mode ZERO for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_CSSETUP_ONE (_EUSART_TIMINGCFG_CSSETUP_ONE << 4) /**< Shifted mode ONE for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_CSSETUP_TWO (_EUSART_TIMINGCFG_CSSETUP_TWO << 4) /**< Shifted mode TWO for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_CSSETUP_THREE (_EUSART_TIMINGCFG_CSSETUP_THREE << 4) /**< Shifted mode THREE for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_CSSETUP_FOUR (_EUSART_TIMINGCFG_CSSETUP_FOUR << 4) /**< Shifted mode FOUR for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_CSSETUP_FIVE (_EUSART_TIMINGCFG_CSSETUP_FIVE << 4) /**< Shifted mode FIVE for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_CSSETUP_SIX (_EUSART_TIMINGCFG_CSSETUP_SIX << 4) /**< Shifted mode SIX for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_CSSETUP_SEVEN (_EUSART_TIMINGCFG_CSSETUP_SEVEN << 4) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_CSHOLD_SHIFT 8 /**< Shift value for EUSART_CSHOLD */
+#define _EUSART_TIMINGCFG_CSHOLD_MASK 0x700UL /**< Bit mask for EUSART_CSHOLD */
+#define _EUSART_TIMINGCFG_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_CSHOLD_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_CSHOLD_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_CSHOLD_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_CSHOLD_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_CSHOLD_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_CSHOLD_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_CSHOLD_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_CSHOLD_DEFAULT (_EUSART_TIMINGCFG_CSHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_CSHOLD_ZERO (_EUSART_TIMINGCFG_CSHOLD_ZERO << 8) /**< Shifted mode ZERO for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_CSHOLD_ONE (_EUSART_TIMINGCFG_CSHOLD_ONE << 8) /**< Shifted mode ONE for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_CSHOLD_TWO (_EUSART_TIMINGCFG_CSHOLD_TWO << 8) /**< Shifted mode TWO for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_CSHOLD_THREE (_EUSART_TIMINGCFG_CSHOLD_THREE << 8) /**< Shifted mode THREE for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_CSHOLD_FOUR (_EUSART_TIMINGCFG_CSHOLD_FOUR << 8) /**< Shifted mode FOUR for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_CSHOLD_FIVE (_EUSART_TIMINGCFG_CSHOLD_FIVE << 8) /**< Shifted mode FIVE for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_CSHOLD_SIX (_EUSART_TIMINGCFG_CSHOLD_SIX << 8) /**< Shifted mode SIX for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_CSHOLD_SEVEN (_EUSART_TIMINGCFG_CSHOLD_SEVEN << 8) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_ICS_SHIFT 12 /**< Shift value for EUSART_ICS */
+#define _EUSART_TIMINGCFG_ICS_MASK 0x7000UL /**< Bit mask for EUSART_ICS */
+#define _EUSART_TIMINGCFG_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_ICS_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_ICS_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_ICS_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_ICS_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_ICS_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_ICS_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_ICS_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_ICS_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_ICS_DEFAULT (_EUSART_TIMINGCFG_ICS_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_ICS_ZERO (_EUSART_TIMINGCFG_ICS_ZERO << 12) /**< Shifted mode ZERO for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_ICS_ONE (_EUSART_TIMINGCFG_ICS_ONE << 12) /**< Shifted mode ONE for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_ICS_TWO (_EUSART_TIMINGCFG_ICS_TWO << 12) /**< Shifted mode TWO for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_ICS_THREE (_EUSART_TIMINGCFG_ICS_THREE << 12) /**< Shifted mode THREE for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_ICS_FOUR (_EUSART_TIMINGCFG_ICS_FOUR << 12) /**< Shifted mode FOUR for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_ICS_FIVE (_EUSART_TIMINGCFG_ICS_FIVE << 12) /**< Shifted mode FIVE for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_ICS_SIX (_EUSART_TIMINGCFG_ICS_SIX << 12) /**< Shifted mode SIX for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_ICS_SEVEN (_EUSART_TIMINGCFG_ICS_SEVEN << 12) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */
+#define _EUSART_TIMINGCFG_SETUPWINDOW_SHIFT 16 /**< Shift value for EUSART_SETUPWINDOW */
+#define _EUSART_TIMINGCFG_SETUPWINDOW_MASK 0xF0000UL /**< Bit mask for EUSART_SETUPWINDOW */
+#define _EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT 0x00000005UL /**< Mode DEFAULT for EUSART_TIMINGCFG */
+#define EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT (_EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */
+
+/* Bit fields for EUSART STARTFRAMECFG */
+#define _EUSART_STARTFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_STARTFRAMECFG */
+#define _EUSART_STARTFRAMECFG_MASK 0x000001FFUL /**< Mask for EUSART_STARTFRAMECFG */
+#define _EUSART_STARTFRAMECFG_STARTFRAME_SHIFT 0 /**< Shift value for EUSART_STARTFRAME */
+#define _EUSART_STARTFRAMECFG_STARTFRAME_MASK 0x1FFUL /**< Bit mask for EUSART_STARTFRAME */
+#define _EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STARTFRAMECFG */
+#define EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT (_EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STARTFRAMECFG*/
+
+/* Bit fields for EUSART SIGFRAMECFG */
+#define _EUSART_SIGFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_SIGFRAMECFG */
+#define _EUSART_SIGFRAMECFG_MASK 0xFFFFFFFFUL /**< Mask for EUSART_SIGFRAMECFG */
+#define _EUSART_SIGFRAMECFG_SIGFRAME_SHIFT 0 /**< Shift value for EUSART_SIGFRAME */
+#define _EUSART_SIGFRAMECFG_SIGFRAME_MASK 0xFFFFFFFFUL /**< Bit mask for EUSART_SIGFRAME */
+#define _EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SIGFRAMECFG */
+#define EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT (_EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SIGFRAMECFG */
+
+/* Bit fields for EUSART CLKDIV */
+#define _EUSART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for EUSART_CLKDIV */
+#define _EUSART_CLKDIV_MASK 0x007FFFF8UL /**< Mask for EUSART_CLKDIV */
+#define _EUSART_CLKDIV_DIV_SHIFT 3 /**< Shift value for EUSART_DIV */
+#define _EUSART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for EUSART_DIV */
+#define _EUSART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CLKDIV */
+#define EUSART_CLKDIV_DIV_DEFAULT (_EUSART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CLKDIV */
+
+/* Bit fields for EUSART TRIGCTRL */
+#define _EUSART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for EUSART_TRIGCTRL */
+#define _EUSART_TRIGCTRL_MASK 0x00000007UL /**< Mask for EUSART_TRIGCTRL */
+#define EUSART_TRIGCTRL_RXTEN (0x1UL << 0) /**< Receive Trigger Enable */
+#define _EUSART_TRIGCTRL_RXTEN_SHIFT 0 /**< Shift value for EUSART_RXTEN */
+#define _EUSART_TRIGCTRL_RXTEN_MASK 0x1UL /**< Bit mask for EUSART_RXTEN */
+#define _EUSART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */
+#define EUSART_TRIGCTRL_RXTEN_DEFAULT (_EUSART_TRIGCTRL_RXTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */
+#define EUSART_TRIGCTRL_TXTEN (0x1UL << 1) /**< Transmit Trigger Enable */
+#define _EUSART_TRIGCTRL_TXTEN_SHIFT 1 /**< Shift value for EUSART_TXTEN */
+#define _EUSART_TRIGCTRL_TXTEN_MASK 0x2UL /**< Bit mask for EUSART_TXTEN */
+#define _EUSART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */
+#define EUSART_TRIGCTRL_TXTEN_DEFAULT (_EUSART_TRIGCTRL_TXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */
+#define EUSART_TRIGCTRL_AUTOTXTEN (0x1UL << 2) /**< AUTOTX Trigger Enable */
+#define _EUSART_TRIGCTRL_AUTOTXTEN_SHIFT 2 /**< Shift value for EUSART_AUTOTXTEN */
+#define _EUSART_TRIGCTRL_AUTOTXTEN_MASK 0x4UL /**< Bit mask for EUSART_AUTOTXTEN */
+#define _EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */
+#define EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT (_EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */
+
+/* Bit fields for EUSART CMD */
+#define _EUSART_CMD_RESETVALUE 0x00000000UL /**< Default value for EUSART_CMD */
+#define _EUSART_CMD_MASK 0x000001FFUL /**< Mask for EUSART_CMD */
+#define EUSART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */
+#define _EUSART_CMD_RXEN_SHIFT 0 /**< Shift value for EUSART_RXEN */
+#define _EUSART_CMD_RXEN_MASK 0x1UL /**< Bit mask for EUSART_RXEN */
+#define _EUSART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */
+#define EUSART_CMD_RXEN_DEFAULT (_EUSART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CMD */
+#define EUSART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */
+#define _EUSART_CMD_RXDIS_SHIFT 1 /**< Shift value for EUSART_RXDIS */
+#define _EUSART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for EUSART_RXDIS */
+#define _EUSART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */
+#define EUSART_CMD_RXDIS_DEFAULT (_EUSART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CMD */
+#define EUSART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */
+#define _EUSART_CMD_TXEN_SHIFT 2 /**< Shift value for EUSART_TXEN */
+#define _EUSART_CMD_TXEN_MASK 0x4UL /**< Bit mask for EUSART_TXEN */
+#define _EUSART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */
+#define EUSART_CMD_TXEN_DEFAULT (_EUSART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CMD */
+#define EUSART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */
+#define _EUSART_CMD_TXDIS_SHIFT 3 /**< Shift value for EUSART_TXDIS */
+#define _EUSART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for EUSART_TXDIS */
+#define _EUSART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */
+#define EUSART_CMD_TXDIS_DEFAULT (_EUSART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CMD */
+#define EUSART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */
+#define _EUSART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for EUSART_RXBLOCKEN */
+#define _EUSART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for EUSART_RXBLOCKEN */
+#define _EUSART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */
+#define EUSART_CMD_RXBLOCKEN_DEFAULT (_EUSART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CMD */
+#define EUSART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */
+#define _EUSART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for EUSART_RXBLOCKDIS */
+#define _EUSART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for EUSART_RXBLOCKDIS */
+#define _EUSART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */
+#define EUSART_CMD_RXBLOCKDIS_DEFAULT (_EUSART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CMD */
+#define EUSART_CMD_TXTRIEN (0x1UL << 6) /**< Transmitter Tristate Enable */
+#define _EUSART_CMD_TXTRIEN_SHIFT 6 /**< Shift value for EUSART_TXTRIEN */
+#define _EUSART_CMD_TXTRIEN_MASK 0x40UL /**< Bit mask for EUSART_TXTRIEN */
+#define _EUSART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */
+#define EUSART_CMD_TXTRIEN_DEFAULT (_EUSART_CMD_TXTRIEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_CMD */
+#define EUSART_CMD_TXTRIDIS (0x1UL << 7) /**< Transmitter Tristate Disable */
+#define _EUSART_CMD_TXTRIDIS_SHIFT 7 /**< Shift value for EUSART_TXTRIDIS */
+#define _EUSART_CMD_TXTRIDIS_MASK 0x80UL /**< Bit mask for EUSART_TXTRIDIS */
+#define _EUSART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */
+#define EUSART_CMD_TXTRIDIS_DEFAULT (_EUSART_CMD_TXTRIDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_CMD */
+#define EUSART_CMD_CLEARTX (0x1UL << 8) /**< Clear TX FIFO */
+#define _EUSART_CMD_CLEARTX_SHIFT 8 /**< Shift value for EUSART_CLEARTX */
+#define _EUSART_CMD_CLEARTX_MASK 0x100UL /**< Bit mask for EUSART_CLEARTX */
+#define _EUSART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */
+#define EUSART_CMD_CLEARTX_DEFAULT (_EUSART_CMD_CLEARTX_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_CMD */
+
+/* Bit fields for EUSART RXDATA */
+#define _EUSART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATA */
+#define _EUSART_RXDATA_MASK 0x0000FFFFUL /**< Mask for EUSART_RXDATA */
+#define _EUSART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for EUSART_RXDATA */
+#define _EUSART_RXDATA_RXDATA_MASK 0xFFFFUL /**< Bit mask for EUSART_RXDATA */
+#define _EUSART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATA */
+#define EUSART_RXDATA_RXDATA_DEFAULT (_EUSART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATA */
+
+/* Bit fields for EUSART RXDATAP */
+#define _EUSART_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATAP */
+#define _EUSART_RXDATAP_MASK 0x0000FFFFUL /**< Mask for EUSART_RXDATAP */
+#define _EUSART_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for EUSART_RXDATAP */
+#define _EUSART_RXDATAP_RXDATAP_MASK 0xFFFFUL /**< Bit mask for EUSART_RXDATAP */
+#define _EUSART_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATAP */
+#define EUSART_RXDATAP_RXDATAP_DEFAULT (_EUSART_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATAP */
+
+/* Bit fields for EUSART TXDATA */
+#define _EUSART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_TXDATA */
+#define _EUSART_TXDATA_MASK 0x0000FFFFUL /**< Mask for EUSART_TXDATA */
+#define _EUSART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for EUSART_TXDATA */
+#define _EUSART_TXDATA_TXDATA_MASK 0xFFFFUL /**< Bit mask for EUSART_TXDATA */
+#define _EUSART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TXDATA */
+#define EUSART_TXDATA_TXDATA_DEFAULT (_EUSART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TXDATA */
+
+/* Bit fields for EUSART STATUS */
+#define _EUSART_STATUS_RESETVALUE 0x00003040UL /**< Default value for EUSART_STATUS */
+#define _EUSART_STATUS_MASK 0x031F31FBUL /**< Mask for EUSART_STATUS */
+#define EUSART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */
+#define _EUSART_STATUS_RXENS_SHIFT 0 /**< Shift value for EUSART_RXENS */
+#define _EUSART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for EUSART_RXENS */
+#define _EUSART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */
+#define EUSART_STATUS_RXENS_DEFAULT (_EUSART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STATUS */
+#define EUSART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */
+#define _EUSART_STATUS_TXENS_SHIFT 1 /**< Shift value for EUSART_TXENS */
+#define _EUSART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for EUSART_TXENS */
+#define _EUSART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */
+#define EUSART_STATUS_TXENS_DEFAULT (_EUSART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_STATUS */
+#define EUSART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */
+#define _EUSART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for EUSART_RXBLOCK */
+#define _EUSART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for EUSART_RXBLOCK */
+#define _EUSART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */
+#define EUSART_STATUS_RXBLOCK_DEFAULT (_EUSART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_STATUS */
+#define EUSART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */
+#define _EUSART_STATUS_TXTRI_SHIFT 4 /**< Shift value for EUSART_TXTRI */
+#define _EUSART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for EUSART_TXTRI */
+#define _EUSART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */
+#define EUSART_STATUS_TXTRI_DEFAULT (_EUSART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_STATUS */
+#define EUSART_STATUS_TXC (0x1UL << 5) /**< TX Complete */
+#define _EUSART_STATUS_TXC_SHIFT 5 /**< Shift value for EUSART_TXC */
+#define _EUSART_STATUS_TXC_MASK 0x20UL /**< Bit mask for EUSART_TXC */
+#define _EUSART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */
+#define EUSART_STATUS_TXC_DEFAULT (_EUSART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_STATUS */
+#define EUSART_STATUS_TXFL (0x1UL << 6) /**< TX FIFO Level */
+#define _EUSART_STATUS_TXFL_SHIFT 6 /**< Shift value for EUSART_TXFL */
+#define _EUSART_STATUS_TXFL_MASK 0x40UL /**< Bit mask for EUSART_TXFL */
+#define _EUSART_STATUS_TXFL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */
+#define EUSART_STATUS_TXFL_DEFAULT (_EUSART_STATUS_TXFL_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_STATUS */
+#define EUSART_STATUS_RXFL (0x1UL << 7) /**< RX FIFO Level */
+#define _EUSART_STATUS_RXFL_SHIFT 7 /**< Shift value for EUSART_RXFL */
+#define _EUSART_STATUS_RXFL_MASK 0x80UL /**< Bit mask for EUSART_RXFL */
+#define _EUSART_STATUS_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */
+#define EUSART_STATUS_RXFL_DEFAULT (_EUSART_STATUS_RXFL_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_STATUS */
+#define EUSART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */
+#define _EUSART_STATUS_RXFULL_SHIFT 8 /**< Shift value for EUSART_RXFULL */
+#define _EUSART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for EUSART_RXFULL */
+#define _EUSART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */
+#define EUSART_STATUS_RXFULL_DEFAULT (_EUSART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_STATUS */
+#define EUSART_STATUS_RXIDLE (0x1UL << 12) /**< RX Idle */
+#define _EUSART_STATUS_RXIDLE_SHIFT 12 /**< Shift value for EUSART_RXIDLE */
+#define _EUSART_STATUS_RXIDLE_MASK 0x1000UL /**< Bit mask for EUSART_RXIDLE */
+#define _EUSART_STATUS_RXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */
+#define EUSART_STATUS_RXIDLE_DEFAULT (_EUSART_STATUS_RXIDLE_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_STATUS */
+#define EUSART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */
+#define _EUSART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */
+#define _EUSART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */
+#define _EUSART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */
+#define EUSART_STATUS_TXIDLE_DEFAULT (_EUSART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_STATUS */
+#define _EUSART_STATUS_TXFCNT_SHIFT 16 /**< Shift value for EUSART_TXFCNT */
+#define _EUSART_STATUS_TXFCNT_MASK 0x1F0000UL /**< Bit mask for EUSART_TXFCNT */
+#define _EUSART_STATUS_TXFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */
+#define EUSART_STATUS_TXFCNT_DEFAULT (_EUSART_STATUS_TXFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_STATUS */
+#define EUSART_STATUS_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Rate Detection Completed */
+#define _EUSART_STATUS_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */
+#define _EUSART_STATUS_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */
+#define _EUSART_STATUS_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */
+#define EUSART_STATUS_AUTOBAUDDONE_DEFAULT (_EUSART_STATUS_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_STATUS */
+#define EUSART_STATUS_CLEARTXBUSY (0x1UL << 25) /**< TX FIFO Clear Busy */
+#define _EUSART_STATUS_CLEARTXBUSY_SHIFT 25 /**< Shift value for EUSART_CLEARTXBUSY */
+#define _EUSART_STATUS_CLEARTXBUSY_MASK 0x2000000UL /**< Bit mask for EUSART_CLEARTXBUSY */
+#define _EUSART_STATUS_CLEARTXBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */
+#define EUSART_STATUS_CLEARTXBUSY_DEFAULT (_EUSART_STATUS_CLEARTXBUSY_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_STATUS */
+
+/* Bit fields for EUSART IF */
+#define _EUSART_IF_RESETVALUE 0x00000000UL /**< Default value for EUSART_IF */
+#define _EUSART_IF_MASK 0x030D3FFFUL /**< Mask for EUSART_IF */
+#define EUSART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */
+#define _EUSART_IF_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */
+#define _EUSART_IF_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */
+#define _EUSART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */
+#define EUSART_IF_TXC_DEFAULT (_EUSART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IF */
+#define EUSART_IF_TXFL (0x1UL << 1) /**< TX FIFO Level Interrupt Flag */
+#define _EUSART_IF_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */
+#define _EUSART_IF_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */
+#define _EUSART_IF_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */
+#define EUSART_IF_TXFL_DEFAULT (_EUSART_IF_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IF */
+#define EUSART_IF_RXFL (0x1UL << 2) /**< RX FIFO Level Interrupt Flag */
+#define _EUSART_IF_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */
+#define _EUSART_IF_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */
+#define _EUSART_IF_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */
+#define EUSART_IF_RXFL_DEFAULT (_EUSART_IF_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IF */
+#define EUSART_IF_RXFULL (0x1UL << 3) /**< RX FIFO Full Interrupt Flag */
+#define _EUSART_IF_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */
+#define _EUSART_IF_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */
+#define _EUSART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */
+#define EUSART_IF_RXFULL_DEFAULT (_EUSART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IF */
+#define EUSART_IF_RXOF (0x1UL << 4) /**< RX FIFO Overflow Interrupt Flag */
+#define _EUSART_IF_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */
+#define _EUSART_IF_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */
+#define _EUSART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */
+#define EUSART_IF_RXOF_DEFAULT (_EUSART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IF */
+#define EUSART_IF_RXUF (0x1UL << 5) /**< RX FIFO Underflow Interrupt Flag */
+#define _EUSART_IF_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */
+#define _EUSART_IF_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */
+#define _EUSART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */
+#define EUSART_IF_RXUF_DEFAULT (_EUSART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IF */
+#define EUSART_IF_TXOF (0x1UL << 6) /**< TX FIFO Overflow Interrupt Flag */
+#define _EUSART_IF_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */
+#define _EUSART_IF_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */
+#define _EUSART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */
+#define EUSART_IF_TXOF_DEFAULT (_EUSART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IF */
+#define EUSART_IF_TXUF (0x1UL << 7) /**< TX FIFO Underflow Interrupt Flag */
+#define _EUSART_IF_TXUF_SHIFT 7 /**< Shift value for EUSART_TXUF */
+#define _EUSART_IF_TXUF_MASK 0x80UL /**< Bit mask for EUSART_TXUF */
+#define _EUSART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */
+#define EUSART_IF_TXUF_DEFAULT (_EUSART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_IF */
+#define EUSART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */
+#define _EUSART_IF_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */
+#define _EUSART_IF_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */
+#define _EUSART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */
+#define EUSART_IF_PERR_DEFAULT (_EUSART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IF */
+#define EUSART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */
+#define _EUSART_IF_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */
+#define _EUSART_IF_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */
+#define _EUSART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */
+#define EUSART_IF_FERR_DEFAULT (_EUSART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IF */
+#define EUSART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */
+#define _EUSART_IF_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */
+#define _EUSART_IF_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */
+#define _EUSART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */
+#define EUSART_IF_MPAF_DEFAULT (_EUSART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IF */
+#define EUSART_IF_LOADERR (0x1UL << 11) /**< Load Error Interrupt Flag */
+#define _EUSART_IF_LOADERR_SHIFT 11 /**< Shift value for EUSART_LOADERR */
+#define _EUSART_IF_LOADERR_MASK 0x800UL /**< Bit mask for EUSART_LOADERR */
+#define _EUSART_IF_LOADERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */
+#define EUSART_IF_LOADERR_DEFAULT (_EUSART_IF_LOADERR_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_IF */
+#define EUSART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */
+#define _EUSART_IF_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */
+#define _EUSART_IF_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */
+#define _EUSART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */
+#define EUSART_IF_CCF_DEFAULT (_EUSART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IF */
+#define EUSART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */
+#define _EUSART_IF_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */
+#define _EUSART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */
+#define _EUSART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */
+#define EUSART_IF_TXIDLE_DEFAULT (_EUSART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IF */
+#define EUSART_IF_CSWU (0x1UL << 16) /**< CS Wake-up Interrupt Flag */
+#define _EUSART_IF_CSWU_SHIFT 16 /**< Shift value for EUSART_CSWU */
+#define _EUSART_IF_CSWU_MASK 0x10000UL /**< Bit mask for EUSART_CSWU */
+#define _EUSART_IF_CSWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */
+#define EUSART_IF_CSWU_DEFAULT (_EUSART_IF_CSWU_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_IF */
+#define EUSART_IF_STARTF (0x1UL << 18) /**< Start Frame Interrupt Flag */
+#define _EUSART_IF_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */
+#define _EUSART_IF_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */
+#define _EUSART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */
+#define EUSART_IF_STARTF_DEFAULT (_EUSART_IF_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IF */
+#define EUSART_IF_SIGF (0x1UL << 19) /**< Signal Frame Interrupt Flag */
+#define _EUSART_IF_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */
+#define _EUSART_IF_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */
+#define _EUSART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */
+#define EUSART_IF_SIGF_DEFAULT (_EUSART_IF_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IF */
+#define EUSART_IF_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete Interrupt Flag */
+#define _EUSART_IF_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */
+#define _EUSART_IF_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */
+#define _EUSART_IF_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */
+#define EUSART_IF_AUTOBAUDDONE_DEFAULT (_EUSART_IF_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IF */
+#define EUSART_IF_RXTO (0x1UL << 25) /**< RX Timeout Interrupt Flag */
+#define _EUSART_IF_RXTO_SHIFT 25 /**< Shift value for EUSART_RXTO */
+#define _EUSART_IF_RXTO_MASK 0x2000000UL /**< Bit mask for EUSART_RXTO */
+#define _EUSART_IF_RXTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */
+#define EUSART_IF_RXTO_DEFAULT (_EUSART_IF_RXTO_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_IF */
+
+/* Bit fields for EUSART IEN */
+#define _EUSART_IEN_RESETVALUE 0x00000000UL /**< Default value for EUSART_IEN */
+#define _EUSART_IEN_MASK 0x030D3FFFUL /**< Mask for EUSART_IEN */
+#define EUSART_IEN_TXC (0x1UL << 0) /**< TX Complete Enable */
+#define _EUSART_IEN_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */
+#define _EUSART_IEN_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */
+#define _EUSART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_TXC_DEFAULT (_EUSART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_TXFL (0x1UL << 1) /**< TX FIFO Level Enable */
+#define _EUSART_IEN_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */
+#define _EUSART_IEN_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */
+#define _EUSART_IEN_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_TXFL_DEFAULT (_EUSART_IEN_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_RXFL (0x1UL << 2) /**< RX FIFO Level Enable */
+#define _EUSART_IEN_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */
+#define _EUSART_IEN_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */
+#define _EUSART_IEN_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_RXFL_DEFAULT (_EUSART_IEN_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_RXFULL (0x1UL << 3) /**< RX FIFO Full Enable */
+#define _EUSART_IEN_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */
+#define _EUSART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */
+#define _EUSART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_RXFULL_DEFAULT (_EUSART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_RXOF (0x1UL << 4) /**< RX FIFO Overflow Enable */
+#define _EUSART_IEN_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */
+#define _EUSART_IEN_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */
+#define _EUSART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_RXOF_DEFAULT (_EUSART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_RXUF (0x1UL << 5) /**< RX FIFO Underflow Enable */
+#define _EUSART_IEN_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */
+#define _EUSART_IEN_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */
+#define _EUSART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_RXUF_DEFAULT (_EUSART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_TXOF (0x1UL << 6) /**< TX FIFO Overflow Enable */
+#define _EUSART_IEN_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */
+#define _EUSART_IEN_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */
+#define _EUSART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_TXOF_DEFAULT (_EUSART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_TXUF (0x1UL << 7) /**< TX FIFO Underflow Enable */
+#define _EUSART_IEN_TXUF_SHIFT 7 /**< Shift value for EUSART_TXUF */
+#define _EUSART_IEN_TXUF_MASK 0x80UL /**< Bit mask for EUSART_TXUF */
+#define _EUSART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_TXUF_DEFAULT (_EUSART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_PERR (0x1UL << 8) /**< Parity Error Enable */
+#define _EUSART_IEN_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */
+#define _EUSART_IEN_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */
+#define _EUSART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_PERR_DEFAULT (_EUSART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_FERR (0x1UL << 9) /**< Framing Error Enable */
+#define _EUSART_IEN_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */
+#define _EUSART_IEN_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */
+#define _EUSART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_FERR_DEFAULT (_EUSART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Addr Frame Enable */
+#define _EUSART_IEN_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */
+#define _EUSART_IEN_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */
+#define _EUSART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_MPAF_DEFAULT (_EUSART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_LOADERR (0x1UL << 11) /**< Load Error Enable */
+#define _EUSART_IEN_LOADERR_SHIFT 11 /**< Shift value for EUSART_LOADERR */
+#define _EUSART_IEN_LOADERR_MASK 0x800UL /**< Bit mask for EUSART_LOADERR */
+#define _EUSART_IEN_LOADERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_LOADERR_DEFAULT (_EUSART_IEN_LOADERR_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail Enable */
+#define _EUSART_IEN_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */
+#define _EUSART_IEN_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */
+#define _EUSART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_CCF_DEFAULT (_EUSART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_TXIDLE (0x1UL << 13) /**< TX IDLE Enable */
+#define _EUSART_IEN_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */
+#define _EUSART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */
+#define _EUSART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_TXIDLE_DEFAULT (_EUSART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_CSWU (0x1UL << 16) /**< CS Wake-up Enable */
+#define _EUSART_IEN_CSWU_SHIFT 16 /**< Shift value for EUSART_CSWU */
+#define _EUSART_IEN_CSWU_MASK 0x10000UL /**< Bit mask for EUSART_CSWU */
+#define _EUSART_IEN_CSWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_CSWU_DEFAULT (_EUSART_IEN_CSWU_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_STARTF (0x1UL << 18) /**< Start Frame Enable */
+#define _EUSART_IEN_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */
+#define _EUSART_IEN_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */
+#define _EUSART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_STARTF_DEFAULT (_EUSART_IEN_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_SIGF (0x1UL << 19) /**< Signal Frame Enable */
+#define _EUSART_IEN_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */
+#define _EUSART_IEN_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */
+#define _EUSART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_SIGF_DEFAULT (_EUSART_IEN_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete Enable */
+#define _EUSART_IEN_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */
+#define _EUSART_IEN_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */
+#define _EUSART_IEN_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_AUTOBAUDDONE_DEFAULT (_EUSART_IEN_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_RXTO (0x1UL << 25) /**< RX Timeout Enable */
+#define _EUSART_IEN_RXTO_SHIFT 25 /**< Shift value for EUSART_RXTO */
+#define _EUSART_IEN_RXTO_MASK 0x2000000UL /**< Bit mask for EUSART_RXTO */
+#define _EUSART_IEN_RXTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */
+#define EUSART_IEN_RXTO_DEFAULT (_EUSART_IEN_RXTO_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_IEN */
+
+/* Bit fields for EUSART SYNCBUSY */
+#define _EUSART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for EUSART_SYNCBUSY */
+#define _EUSART_SYNCBUSY_MASK 0x00000FFFUL /**< Mask for EUSART_SYNCBUSY */
+#define EUSART_SYNCBUSY_DIV (0x1UL << 0) /**< SYNCBUSY for DIV in CLKDIV */
+#define _EUSART_SYNCBUSY_DIV_SHIFT 0 /**< Shift value for EUSART_DIV */
+#define _EUSART_SYNCBUSY_DIV_MASK 0x1UL /**< Bit mask for EUSART_DIV */
+#define _EUSART_SYNCBUSY_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */
+#define EUSART_SYNCBUSY_DIV_DEFAULT (_EUSART_SYNCBUSY_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */
+#define EUSART_SYNCBUSY_RXTEN (0x1UL << 1) /**< SYNCBUSY for RXTEN in TRIGCTRL */
+#define _EUSART_SYNCBUSY_RXTEN_SHIFT 1 /**< Shift value for EUSART_RXTEN */
+#define _EUSART_SYNCBUSY_RXTEN_MASK 0x2UL /**< Bit mask for EUSART_RXTEN */
+#define _EUSART_SYNCBUSY_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */
+#define EUSART_SYNCBUSY_RXTEN_DEFAULT (_EUSART_SYNCBUSY_RXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */
+#define EUSART_SYNCBUSY_TXTEN (0x1UL << 2) /**< SYNCBUSY for TXTEN in TRIGCTRL */
+#define _EUSART_SYNCBUSY_TXTEN_SHIFT 2 /**< Shift value for EUSART_TXTEN */
+#define _EUSART_SYNCBUSY_TXTEN_MASK 0x4UL /**< Bit mask for EUSART_TXTEN */
+#define _EUSART_SYNCBUSY_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */
+#define EUSART_SYNCBUSY_TXTEN_DEFAULT (_EUSART_SYNCBUSY_TXTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */
+#define EUSART_SYNCBUSY_RXEN (0x1UL << 3) /**< SYNCBUSY for RXEN in CMD */
+#define _EUSART_SYNCBUSY_RXEN_SHIFT 3 /**< Shift value for EUSART_RXEN */
+#define _EUSART_SYNCBUSY_RXEN_MASK 0x8UL /**< Bit mask for EUSART_RXEN */
+#define _EUSART_SYNCBUSY_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */
+#define EUSART_SYNCBUSY_RXEN_DEFAULT (_EUSART_SYNCBUSY_RXEN_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */
+#define EUSART_SYNCBUSY_RXDIS (0x1UL << 4) /**< SYNCBUSY for RXDIS in CMD */
+#define _EUSART_SYNCBUSY_RXDIS_SHIFT 4 /**< Shift value for EUSART_RXDIS */
+#define _EUSART_SYNCBUSY_RXDIS_MASK 0x10UL /**< Bit mask for EUSART_RXDIS */
+#define _EUSART_SYNCBUSY_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */
+#define EUSART_SYNCBUSY_RXDIS_DEFAULT (_EUSART_SYNCBUSY_RXDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */
+#define EUSART_SYNCBUSY_TXEN (0x1UL << 5) /**< SYNCBUSY for TXEN in CMD */
+#define _EUSART_SYNCBUSY_TXEN_SHIFT 5 /**< Shift value for EUSART_TXEN */
+#define _EUSART_SYNCBUSY_TXEN_MASK 0x20UL /**< Bit mask for EUSART_TXEN */
+#define _EUSART_SYNCBUSY_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */
+#define EUSART_SYNCBUSY_TXEN_DEFAULT (_EUSART_SYNCBUSY_TXEN_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */
+#define EUSART_SYNCBUSY_TXDIS (0x1UL << 6) /**< SYNCBUSY for TXDIS in CMD */
+#define _EUSART_SYNCBUSY_TXDIS_SHIFT 6 /**< Shift value for EUSART_TXDIS */
+#define _EUSART_SYNCBUSY_TXDIS_MASK 0x40UL /**< Bit mask for EUSART_TXDIS */
+#define _EUSART_SYNCBUSY_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */
+#define EUSART_SYNCBUSY_TXDIS_DEFAULT (_EUSART_SYNCBUSY_TXDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */
+#define EUSART_SYNCBUSY_RXBLOCKEN (0x1UL << 7) /**< SYNCBUSY for RXBLOCKEN in CMD */
+#define _EUSART_SYNCBUSY_RXBLOCKEN_SHIFT 7 /**< Shift value for EUSART_RXBLOCKEN */
+#define _EUSART_SYNCBUSY_RXBLOCKEN_MASK 0x80UL /**< Bit mask for EUSART_RXBLOCKEN */
+#define _EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */
+#define EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */
+#define EUSART_SYNCBUSY_RXBLOCKDIS (0x1UL << 8) /**< SYNCBUSY for RXBLOCKDIS in CMD */
+#define _EUSART_SYNCBUSY_RXBLOCKDIS_SHIFT 8 /**< Shift value for EUSART_RXBLOCKDIS */
+#define _EUSART_SYNCBUSY_RXBLOCKDIS_MASK 0x100UL /**< Bit mask for EUSART_RXBLOCKDIS */
+#define _EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */
+#define EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */
+#define EUSART_SYNCBUSY_TXTRIEN (0x1UL << 9) /**< SYNCBUSY for TXTRIEN in CMD */
+#define _EUSART_SYNCBUSY_TXTRIEN_SHIFT 9 /**< Shift value for EUSART_TXTRIEN */
+#define _EUSART_SYNCBUSY_TXTRIEN_MASK 0x200UL /**< Bit mask for EUSART_TXTRIEN */
+#define _EUSART_SYNCBUSY_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */
+#define EUSART_SYNCBUSY_TXTRIEN_DEFAULT (_EUSART_SYNCBUSY_TXTRIEN_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */
+#define EUSART_SYNCBUSY_TXTRIDIS (0x1UL << 10) /**< SYNCBUSY in TXTRIDIS in CMD */
+#define _EUSART_SYNCBUSY_TXTRIDIS_SHIFT 10 /**< Shift value for EUSART_TXTRIDIS */
+#define _EUSART_SYNCBUSY_TXTRIDIS_MASK 0x400UL /**< Bit mask for EUSART_TXTRIDIS */
+#define _EUSART_SYNCBUSY_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */
+#define EUSART_SYNCBUSY_TXTRIDIS_DEFAULT (_EUSART_SYNCBUSY_TXTRIDIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */
+#define EUSART_SYNCBUSY_AUTOTXTEN (0x1UL << 11) /**< SYNCBUSY for AUTOTXTEN in TRIGCTRL */
+#define _EUSART_SYNCBUSY_AUTOTXTEN_SHIFT 11 /**< Shift value for EUSART_AUTOTXTEN */
+#define _EUSART_SYNCBUSY_AUTOTXTEN_MASK 0x800UL /**< Bit mask for EUSART_AUTOTXTEN */
+#define _EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */
+#define EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT (_EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */
+
+/* Bit fields for EUSART DALICFG */
+#define _EUSART_DALICFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_DALICFG */
+#define _EUSART_DALICFG_MASK 0x00009F3FUL /**< Mask for EUSART_DALICFG */
+#define EUSART_DALICFG_DALIEN (0x1UL << 0) /**< DALI Enable Bit */
+#define _EUSART_DALICFG_DALIEN_SHIFT 0 /**< Shift value for EUSART_DALIEN */
+#define _EUSART_DALICFG_DALIEN_MASK 0x1UL /**< Bit mask for EUSART_DALIEN */
+#define _EUSART_DALICFG_DALIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DALICFG */
+#define EUSART_DALICFG_DALIEN_DEFAULT (_EUSART_DALICFG_DALIEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALITXDATABITS_SHIFT 1 /**< Shift value for EUSART_DALITXDATABITS */
+#define _EUSART_DALICFG_DALITXDATABITS_MASK 0x3EUL /**< Bit mask for EUSART_DALITXDATABITS */
+#define _EUSART_DALICFG_DALITXDATABITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALITXDATABITS_EIGHT 0x00000000UL /**< Mode EIGHT for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALITXDATABITS_NINE 0x00000001UL /**< Mode NINE for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALITXDATABITS_TEN 0x00000002UL /**< Mode TEN for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALITXDATABITS_ELEVEN 0x00000003UL /**< Mode ELEVEN for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALITXDATABITS_TWELVE 0x00000004UL /**< Mode TWELVE for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALITXDATABITS_THIRTEEN 0x00000005UL /**< Mode THIRTEEN for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALITXDATABITS_FOURTEEN 0x00000006UL /**< Mode FOURTEEN for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALITXDATABITS_FIFTEEN 0x00000007UL /**< Mode FIFTEEN for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALITXDATABITS_SIXTEEN 0x00000008UL /**< Mode SIXTEEN for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALITXDATABITS_SEVENTEEN 0x00000009UL /**< Mode SEVENTEEN for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALITXDATABITS_EIGHTEEN 0x0000000AUL /**< Mode EIGHTEEN for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALITXDATABITS_NINETEEN 0x0000000BUL /**< Mode NINETEEN for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALITXDATABITS_TWENTY 0x0000000CUL /**< Mode TWENTY for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALITXDATABITS_TWENTYONE 0x0000000DUL /**< Mode TWENTYONE for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALITXDATABITS_TWENTYTWO 0x0000000EUL /**< Mode TWENTYTWO for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALITXDATABITS_TWENTYTHREE 0x0000000FUL /**< Mode TWENTYTHREE for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALITXDATABITS_TWENTYFOUR 0x00000010UL /**< Mode TWENTYFOUR for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALITXDATABITS_TWENTYFIVE 0x00000011UL /**< Mode TWENTYFIVE for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALITXDATABITS_TWENTYSIX 0x00000012UL /**< Mode TWENTYSIX for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALITXDATABITS_TWENTYSEVEN 0x00000013UL /**< Mode TWENTYSEVEN for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALITXDATABITS_TWENTYEIGHT 0x00000014UL /**< Mode TWENTYEIGHT for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALITXDATABITS_TWENTYNINE 0x00000015UL /**< Mode TWENTYNINE for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALITXDATABITS_THIRTY 0x00000016UL /**< Mode THIRTY for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALITXDATABITS_THIRTYONE 0x00000017UL /**< Mode THIRTYONE for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALITXDATABITS_THIRTYTWO 0x00000018UL /**< Mode THIRTYTWO for EUSART_DALICFG */
+#define EUSART_DALICFG_DALITXDATABITS_DEFAULT (_EUSART_DALICFG_DALITXDATABITS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_DALICFG */
+#define EUSART_DALICFG_DALITXDATABITS_EIGHT (_EUSART_DALICFG_DALITXDATABITS_EIGHT << 1) /**< Shifted mode EIGHT for EUSART_DALICFG */
+#define EUSART_DALICFG_DALITXDATABITS_NINE (_EUSART_DALICFG_DALITXDATABITS_NINE << 1) /**< Shifted mode NINE for EUSART_DALICFG */
+#define EUSART_DALICFG_DALITXDATABITS_TEN (_EUSART_DALICFG_DALITXDATABITS_TEN << 1) /**< Shifted mode TEN for EUSART_DALICFG */
+#define EUSART_DALICFG_DALITXDATABITS_ELEVEN (_EUSART_DALICFG_DALITXDATABITS_ELEVEN << 1) /**< Shifted mode ELEVEN for EUSART_DALICFG */
+#define EUSART_DALICFG_DALITXDATABITS_TWELVE (_EUSART_DALICFG_DALITXDATABITS_TWELVE << 1) /**< Shifted mode TWELVE for EUSART_DALICFG */
+#define EUSART_DALICFG_DALITXDATABITS_THIRTEEN (_EUSART_DALICFG_DALITXDATABITS_THIRTEEN << 1) /**< Shifted mode THIRTEEN for EUSART_DALICFG */
+#define EUSART_DALICFG_DALITXDATABITS_FOURTEEN (_EUSART_DALICFG_DALITXDATABITS_FOURTEEN << 1) /**< Shifted mode FOURTEEN for EUSART_DALICFG */
+#define EUSART_DALICFG_DALITXDATABITS_FIFTEEN (_EUSART_DALICFG_DALITXDATABITS_FIFTEEN << 1) /**< Shifted mode FIFTEEN for EUSART_DALICFG */
+#define EUSART_DALICFG_DALITXDATABITS_SIXTEEN (_EUSART_DALICFG_DALITXDATABITS_SIXTEEN << 1) /**< Shifted mode SIXTEEN for EUSART_DALICFG */
+#define EUSART_DALICFG_DALITXDATABITS_SEVENTEEN (_EUSART_DALICFG_DALITXDATABITS_SEVENTEEN << 1) /**< Shifted mode SEVENTEEN for EUSART_DALICFG */
+#define EUSART_DALICFG_DALITXDATABITS_EIGHTEEN (_EUSART_DALICFG_DALITXDATABITS_EIGHTEEN << 1) /**< Shifted mode EIGHTEEN for EUSART_DALICFG */
+#define EUSART_DALICFG_DALITXDATABITS_NINETEEN (_EUSART_DALICFG_DALITXDATABITS_NINETEEN << 1) /**< Shifted mode NINETEEN for EUSART_DALICFG */
+#define EUSART_DALICFG_DALITXDATABITS_TWENTY (_EUSART_DALICFG_DALITXDATABITS_TWENTY << 1) /**< Shifted mode TWENTY for EUSART_DALICFG */
+#define EUSART_DALICFG_DALITXDATABITS_TWENTYONE (_EUSART_DALICFG_DALITXDATABITS_TWENTYONE << 1) /**< Shifted mode TWENTYONE for EUSART_DALICFG */
+#define EUSART_DALICFG_DALITXDATABITS_TWENTYTWO (_EUSART_DALICFG_DALITXDATABITS_TWENTYTWO << 1) /**< Shifted mode TWENTYTWO for EUSART_DALICFG */
+#define EUSART_DALICFG_DALITXDATABITS_TWENTYTHREE (_EUSART_DALICFG_DALITXDATABITS_TWENTYTHREE << 1) /**< Shifted mode TWENTYTHREE for EUSART_DALICFG */
+#define EUSART_DALICFG_DALITXDATABITS_TWENTYFOUR (_EUSART_DALICFG_DALITXDATABITS_TWENTYFOUR << 1) /**< Shifted mode TWENTYFOUR for EUSART_DALICFG */
+#define EUSART_DALICFG_DALITXDATABITS_TWENTYFIVE (_EUSART_DALICFG_DALITXDATABITS_TWENTYFIVE << 1) /**< Shifted mode TWENTYFIVE for EUSART_DALICFG */
+#define EUSART_DALICFG_DALITXDATABITS_TWENTYSIX (_EUSART_DALICFG_DALITXDATABITS_TWENTYSIX << 1) /**< Shifted mode TWENTYSIX for EUSART_DALICFG */
+#define EUSART_DALICFG_DALITXDATABITS_TWENTYSEVEN (_EUSART_DALICFG_DALITXDATABITS_TWENTYSEVEN << 1) /**< Shifted mode TWENTYSEVEN for EUSART_DALICFG */
+#define EUSART_DALICFG_DALITXDATABITS_TWENTYEIGHT (_EUSART_DALICFG_DALITXDATABITS_TWENTYEIGHT << 1) /**< Shifted mode TWENTYEIGHT for EUSART_DALICFG */
+#define EUSART_DALICFG_DALITXDATABITS_TWENTYNINE (_EUSART_DALICFG_DALITXDATABITS_TWENTYNINE << 1) /**< Shifted mode TWENTYNINE for EUSART_DALICFG */
+#define EUSART_DALICFG_DALITXDATABITS_THIRTY (_EUSART_DALICFG_DALITXDATABITS_THIRTY << 1) /**< Shifted mode THIRTY for EUSART_DALICFG */
+#define EUSART_DALICFG_DALITXDATABITS_THIRTYONE (_EUSART_DALICFG_DALITXDATABITS_THIRTYONE << 1) /**< Shifted mode THIRTYONE for EUSART_DALICFG */
+#define EUSART_DALICFG_DALITXDATABITS_THIRTYTWO (_EUSART_DALICFG_DALITXDATABITS_THIRTYTWO << 1) /**< Shifted mode THIRTYTWO for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALIRXDATABITS_SHIFT 8 /**< Shift value for EUSART_DALIRXDATABITS */
+#define _EUSART_DALICFG_DALIRXDATABITS_MASK 0x1F00UL /**< Bit mask for EUSART_DALIRXDATABITS */
+#define _EUSART_DALICFG_DALIRXDATABITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALIRXDATABITS_EIGHT 0x00000000UL /**< Mode EIGHT for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALIRXDATABITS_NINE 0x00000001UL /**< Mode NINE for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALIRXDATABITS_TEN 0x00000002UL /**< Mode TEN for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALIRXDATABITS_ELEVEN 0x00000003UL /**< Mode ELEVEN for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALIRXDATABITS_TWELVE 0x00000004UL /**< Mode TWELVE for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALIRXDATABITS_THIRTEEN 0x00000005UL /**< Mode THIRTEEN for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALIRXDATABITS_FOURTEEN 0x00000006UL /**< Mode FOURTEEN for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALIRXDATABITS_FIFTEEN 0x00000007UL /**< Mode FIFTEEN for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALIRXDATABITS_SIXTEEN 0x00000008UL /**< Mode SIXTEEN for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALIRXDATABITS_SEVENTEEN 0x00000009UL /**< Mode SEVENTEEN for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALIRXDATABITS_EIGHTEEN 0x0000000AUL /**< Mode EIGHTEEN for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALIRXDATABITS_NINETEEN 0x0000000BUL /**< Mode NINETEEN for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALIRXDATABITS_TWENTY 0x0000000CUL /**< Mode TWENTY for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYONE 0x0000000DUL /**< Mode TWENTYONE for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYTWO 0x0000000EUL /**< Mode TWENTYTWO for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYTHREE 0x0000000FUL /**< Mode TWENTYTHREE for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYFOUR 0x00000010UL /**< Mode TWENTYFOUR for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYFIVE 0x00000011UL /**< Mode TWENTYFIVE for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYSIX 0x00000012UL /**< Mode TWENTYSIX for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYSEVEN 0x00000013UL /**< Mode TWENTYSEVEN for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYEIGHT 0x00000014UL /**< Mode TWENTYEIGHT for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYNINE 0x00000015UL /**< Mode TWENTYNINE for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALIRXDATABITS_THIRTY 0x00000016UL /**< Mode THIRTY for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALIRXDATABITS_THIRTYONE 0x00000017UL /**< Mode THIRTYONE for EUSART_DALICFG */
+#define _EUSART_DALICFG_DALIRXDATABITS_THIRTYTWO 0x00000018UL /**< Mode THIRTYTWO for EUSART_DALICFG */
+#define EUSART_DALICFG_DALIRXDATABITS_DEFAULT (_EUSART_DALICFG_DALIRXDATABITS_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_DALICFG */
+#define EUSART_DALICFG_DALIRXDATABITS_EIGHT (_EUSART_DALICFG_DALIRXDATABITS_EIGHT << 8) /**< Shifted mode EIGHT for EUSART_DALICFG */
+#define EUSART_DALICFG_DALIRXDATABITS_NINE (_EUSART_DALICFG_DALIRXDATABITS_NINE << 8) /**< Shifted mode NINE for EUSART_DALICFG */
+#define EUSART_DALICFG_DALIRXDATABITS_TEN (_EUSART_DALICFG_DALIRXDATABITS_TEN << 8) /**< Shifted mode TEN for EUSART_DALICFG */
+#define EUSART_DALICFG_DALIRXDATABITS_ELEVEN (_EUSART_DALICFG_DALIRXDATABITS_ELEVEN << 8) /**< Shifted mode ELEVEN for EUSART_DALICFG */
+#define EUSART_DALICFG_DALIRXDATABITS_TWELVE (_EUSART_DALICFG_DALIRXDATABITS_TWELVE << 8) /**< Shifted mode TWELVE for EUSART_DALICFG */
+#define EUSART_DALICFG_DALIRXDATABITS_THIRTEEN (_EUSART_DALICFG_DALIRXDATABITS_THIRTEEN << 8) /**< Shifted mode THIRTEEN for EUSART_DALICFG */
+#define EUSART_DALICFG_DALIRXDATABITS_FOURTEEN (_EUSART_DALICFG_DALIRXDATABITS_FOURTEEN << 8) /**< Shifted mode FOURTEEN for EUSART_DALICFG */
+#define EUSART_DALICFG_DALIRXDATABITS_FIFTEEN (_EUSART_DALICFG_DALIRXDATABITS_FIFTEEN << 8) /**< Shifted mode FIFTEEN for EUSART_DALICFG */
+#define EUSART_DALICFG_DALIRXDATABITS_SIXTEEN (_EUSART_DALICFG_DALIRXDATABITS_SIXTEEN << 8) /**< Shifted mode SIXTEEN for EUSART_DALICFG */
+#define EUSART_DALICFG_DALIRXDATABITS_SEVENTEEN (_EUSART_DALICFG_DALIRXDATABITS_SEVENTEEN << 8) /**< Shifted mode SEVENTEEN for EUSART_DALICFG */
+#define EUSART_DALICFG_DALIRXDATABITS_EIGHTEEN (_EUSART_DALICFG_DALIRXDATABITS_EIGHTEEN << 8) /**< Shifted mode EIGHTEEN for EUSART_DALICFG */
+#define EUSART_DALICFG_DALIRXDATABITS_NINETEEN (_EUSART_DALICFG_DALIRXDATABITS_NINETEEN << 8) /**< Shifted mode NINETEEN for EUSART_DALICFG */
+#define EUSART_DALICFG_DALIRXDATABITS_TWENTY (_EUSART_DALICFG_DALIRXDATABITS_TWENTY << 8) /**< Shifted mode TWENTY for EUSART_DALICFG */
+#define EUSART_DALICFG_DALIRXDATABITS_TWENTYONE (_EUSART_DALICFG_DALIRXDATABITS_TWENTYONE << 8) /**< Shifted mode TWENTYONE for EUSART_DALICFG */
+#define EUSART_DALICFG_DALIRXDATABITS_TWENTYTWO (_EUSART_DALICFG_DALIRXDATABITS_TWENTYTWO << 8) /**< Shifted mode TWENTYTWO for EUSART_DALICFG */
+#define EUSART_DALICFG_DALIRXDATABITS_TWENTYTHREE (_EUSART_DALICFG_DALIRXDATABITS_TWENTYTHREE << 8) /**< Shifted mode TWENTYTHREE for EUSART_DALICFG */
+#define EUSART_DALICFG_DALIRXDATABITS_TWENTYFOUR (_EUSART_DALICFG_DALIRXDATABITS_TWENTYFOUR << 8) /**< Shifted mode TWENTYFOUR for EUSART_DALICFG */
+#define EUSART_DALICFG_DALIRXDATABITS_TWENTYFIVE (_EUSART_DALICFG_DALIRXDATABITS_TWENTYFIVE << 8) /**< Shifted mode TWENTYFIVE for EUSART_DALICFG */
+#define EUSART_DALICFG_DALIRXDATABITS_TWENTYSIX (_EUSART_DALICFG_DALIRXDATABITS_TWENTYSIX << 8) /**< Shifted mode TWENTYSIX for EUSART_DALICFG */
+#define EUSART_DALICFG_DALIRXDATABITS_TWENTYSEVEN (_EUSART_DALICFG_DALIRXDATABITS_TWENTYSEVEN << 8) /**< Shifted mode TWENTYSEVEN for EUSART_DALICFG */
+#define EUSART_DALICFG_DALIRXDATABITS_TWENTYEIGHT (_EUSART_DALICFG_DALIRXDATABITS_TWENTYEIGHT << 8) /**< Shifted mode TWENTYEIGHT for EUSART_DALICFG */
+#define EUSART_DALICFG_DALIRXDATABITS_TWENTYNINE (_EUSART_DALICFG_DALIRXDATABITS_TWENTYNINE << 8) /**< Shifted mode TWENTYNINE for EUSART_DALICFG */
+#define EUSART_DALICFG_DALIRXDATABITS_THIRTY (_EUSART_DALICFG_DALIRXDATABITS_THIRTY << 8) /**< Shifted mode THIRTY for EUSART_DALICFG */
+#define EUSART_DALICFG_DALIRXDATABITS_THIRTYONE (_EUSART_DALICFG_DALIRXDATABITS_THIRTYONE << 8) /**< Shifted mode THIRTYONE for EUSART_DALICFG */
+#define EUSART_DALICFG_DALIRXDATABITS_THIRTYTWO (_EUSART_DALICFG_DALIRXDATABITS_THIRTYTWO << 8) /**< Shifted mode THIRTYTWO for EUSART_DALICFG */
+#define EUSART_DALICFG_DALIRXENDT (0x1UL << 15) /**< DALI RX Enabled During Transmission */
+#define _EUSART_DALICFG_DALIRXENDT_SHIFT 15 /**< Shift value for EUSART_DALIRXENDT */
+#define _EUSART_DALICFG_DALIRXENDT_MASK 0x8000UL /**< Bit mask for EUSART_DALIRXENDT */
+#define _EUSART_DALICFG_DALIRXENDT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DALICFG */
+#define EUSART_DALICFG_DALIRXENDT_DEFAULT (_EUSART_DALICFG_DALIRXENDT_DEFAULT << 15) /**< Shifted mode DEFAULT for EUSART_DALICFG */
+
+/** @} End of group EFR32MG24_EUSART_BitFields */
+/** @} End of group EFR32MG24_EUSART */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_EUSART_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_frc.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_frc.h
new file mode 100644
index 00000000..49073eae
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_frc.h
@@ -0,0 +1,2608 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 FRC register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_FRC_H
+#define EFR32MG24_FRC_H
+#define FRC_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_FRC FRC
+ * @{
+ * @brief EFR32MG24 FRC Register Declaration.
+ *****************************************************************************/
+
+/** FRC FCD Register Group Declaration. */
+typedef struct {
+ __IOM uint32_t FCD; /**< Frame Control Descriptor */
+} FRC_FCD_TypeDef;
+
+/** FRC INTELEMENT Register Group Declaration. */
+typedef struct {
+ __IM uint32_t INTELEMENT; /**< Interleaver element value */
+} FRC_INTELEMENT_TypeDef;
+
+/** FRC Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IP Version */
+ __IOM uint32_t EN; /**< Enable peripheral clock to this module */
+ __IM uint32_t STATUS; /**< FRC Status */
+ __IOM uint32_t DFLCTRL; /**< Dynamic Frame Length Control */
+ __IOM uint32_t MAXLENGTH; /**< Maximum Frame Length Register */
+ __IOM uint32_t ADDRFILTCTRL; /**< Address Filter Control */
+ __IOM uint32_t DATABUFFER; /**< Frame controller data buffer */
+ __IM uint32_t WCNT; /**< Word Counter Value Register */
+ __IOM uint32_t WCNTCMP0; /**< Word Counter Compare 0 */
+ __IOM uint32_t WCNTCMP1; /**< Word Counter Compare 1 */
+ __IOM uint32_t WCNTCMP2; /**< Word Counter Compare 2 */
+ __IOM uint32_t CMD; /**< FRC Commands */
+ __IOM uint32_t WHITECTRL; /**< Whitener Control */
+ __IOM uint32_t WHITEPOLY; /**< Whitener Polynomial */
+ __IOM uint32_t WHITEINIT; /**< Whitener Initial Value */
+ __IOM uint32_t FECCTRL; /**< Forward Error Correction Control */
+ __IOM uint32_t BLOCKRAMADDR; /**< Block decoding RAM address register */
+ __IOM uint32_t CONVRAMADDR; /**< Convolutional decoding RAM address */
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t RXCTRL; /**< RX Control Register */
+ __IOM uint32_t TRAILTXDATACTRL; /**< Trailing TX Data Control */
+ __IOM uint32_t TRAILRXDATA; /**< Trailing RX Data */
+ __IM uint32_t SCNT; /**< Sub-Frame Counter Value Register */
+ __IOM uint32_t CONVGENERATOR; /**< Convolutional Coder Polynomials */
+ __IOM uint32_t PUNCTCTRL; /**< Puncturing Control */
+ __IOM uint32_t PAUSECTRL; /**< Pause Control */
+ __IOM uint32_t IF; /**< Frame Controller Interrupt Flags */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IM uint32_t OTACNT; /**< Over the air number of bits counter */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+ __IOM uint32_t BUFFERMODE; /**< FRC Buffer Control */
+ uint32_t RESERVED1[2U]; /**< Reserved for future use */
+ __IOM uint32_t SNIFFCTRL; /**< FRC Sniffer Control Register */
+ __IOM uint32_t AUXDATA; /**< Auxiliary sniffer data output register */
+ __IOM uint32_t RAWCTRL; /**< Raw data control */
+ __IM uint32_t RXRAWDATA; /**< Receiver RAW data */
+ __IM uint32_t PAUSEDATA; /**< Receiver pause data */
+ __IM uint32_t LIKELYCONVSTATE; /**< Most likely convolutional decoder state */
+ __IM uint32_t INTELEMENTNEXT; /**< Interleaver element value */
+ __IOM uint32_t INTWRITEPOINT; /**< Interleaver write pointer */
+ __IOM uint32_t INTREADPOINT; /**< Interleaver read pointer */
+ __IOM uint32_t AUTOCG; /**< Automatic clock gating */
+ __IOM uint32_t CGCLKSTOP; /**< Automatic clock gating */
+ uint32_t RESERVED2[1U]; /**< Reserved for future use */
+ __IOM uint32_t SEQIF; /**< SEQ Frame Controller Interrupt Flags */
+ __IOM uint32_t SEQIEN; /**< SEQ Interrupt Enable Register */
+ __IOM uint32_t WCNTCMP3; /**< Word Counter Compare 3 */
+ __IOM uint32_t BOICTRL; /**< Bit of Interest Control */
+ __IOM uint32_t DSLCTRL; /**< Dynamic Supp Length Control */
+ __IOM uint32_t WCNTCMP4; /**< Word Counter Compare 4 */
+ __IOM uint32_t WCNTCMP5; /**< Word Counter Compare 5 */
+ __IOM uint32_t PKTBUFCTRL; /**< Packet Capture Buffer Ctrl */
+ __IM uint32_t PKTBUFSTATUS; /**< Packet Capture Buffer Status */
+ __IM uint32_t PKTBUF0; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF1; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF2; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF3; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF4; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF5; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF6; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF7; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF8; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF9; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF10; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF11; /**< Packet Capture Data Buffer */
+ FRC_FCD_TypeDef FCD[4U]; /**< Frame Descriptors */
+ uint32_t RESERVED3[10U]; /**< Reserved for future use */
+ FRC_INTELEMENT_TypeDef INTELEMENT[16U]; /**< Interleaver element */
+ __IOM uint32_t AHBCONFIG; /**< AHB Configuration */
+ uint32_t RESERVED4[927U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP Version */
+ __IOM uint32_t EN_SET; /**< Enable peripheral clock to this module */
+ __IM uint32_t STATUS_SET; /**< FRC Status */
+ __IOM uint32_t DFLCTRL_SET; /**< Dynamic Frame Length Control */
+ __IOM uint32_t MAXLENGTH_SET; /**< Maximum Frame Length Register */
+ __IOM uint32_t ADDRFILTCTRL_SET; /**< Address Filter Control */
+ __IOM uint32_t DATABUFFER_SET; /**< Frame controller data buffer */
+ __IM uint32_t WCNT_SET; /**< Word Counter Value Register */
+ __IOM uint32_t WCNTCMP0_SET; /**< Word Counter Compare 0 */
+ __IOM uint32_t WCNTCMP1_SET; /**< Word Counter Compare 1 */
+ __IOM uint32_t WCNTCMP2_SET; /**< Word Counter Compare 2 */
+ __IOM uint32_t CMD_SET; /**< FRC Commands */
+ __IOM uint32_t WHITECTRL_SET; /**< Whitener Control */
+ __IOM uint32_t WHITEPOLY_SET; /**< Whitener Polynomial */
+ __IOM uint32_t WHITEINIT_SET; /**< Whitener Initial Value */
+ __IOM uint32_t FECCTRL_SET; /**< Forward Error Correction Control */
+ __IOM uint32_t BLOCKRAMADDR_SET; /**< Block decoding RAM address register */
+ __IOM uint32_t CONVRAMADDR_SET; /**< Convolutional decoding RAM address */
+ __IOM uint32_t CTRL_SET; /**< Control Register */
+ __IOM uint32_t RXCTRL_SET; /**< RX Control Register */
+ __IOM uint32_t TRAILTXDATACTRL_SET; /**< Trailing TX Data Control */
+ __IOM uint32_t TRAILRXDATA_SET; /**< Trailing RX Data */
+ __IM uint32_t SCNT_SET; /**< Sub-Frame Counter Value Register */
+ __IOM uint32_t CONVGENERATOR_SET; /**< Convolutional Coder Polynomials */
+ __IOM uint32_t PUNCTCTRL_SET; /**< Puncturing Control */
+ __IOM uint32_t PAUSECTRL_SET; /**< Pause Control */
+ __IOM uint32_t IF_SET; /**< Frame Controller Interrupt Flags */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
+ __IM uint32_t OTACNT_SET; /**< Over the air number of bits counter */
+ uint32_t RESERVED5[1U]; /**< Reserved for future use */
+ __IOM uint32_t BUFFERMODE_SET; /**< FRC Buffer Control */
+ uint32_t RESERVED6[2U]; /**< Reserved for future use */
+ __IOM uint32_t SNIFFCTRL_SET; /**< FRC Sniffer Control Register */
+ __IOM uint32_t AUXDATA_SET; /**< Auxiliary sniffer data output register */
+ __IOM uint32_t RAWCTRL_SET; /**< Raw data control */
+ __IM uint32_t RXRAWDATA_SET; /**< Receiver RAW data */
+ __IM uint32_t PAUSEDATA_SET; /**< Receiver pause data */
+ __IM uint32_t LIKELYCONVSTATE_SET; /**< Most likely convolutional decoder state */
+ __IM uint32_t INTELEMENTNEXT_SET; /**< Interleaver element value */
+ __IOM uint32_t INTWRITEPOINT_SET; /**< Interleaver write pointer */
+ __IOM uint32_t INTREADPOINT_SET; /**< Interleaver read pointer */
+ __IOM uint32_t AUTOCG_SET; /**< Automatic clock gating */
+ __IOM uint32_t CGCLKSTOP_SET; /**< Automatic clock gating */
+ uint32_t RESERVED7[1U]; /**< Reserved for future use */
+ __IOM uint32_t SEQIF_SET; /**< SEQ Frame Controller Interrupt Flags */
+ __IOM uint32_t SEQIEN_SET; /**< SEQ Interrupt Enable Register */
+ __IOM uint32_t WCNTCMP3_SET; /**< Word Counter Compare 3 */
+ __IOM uint32_t BOICTRL_SET; /**< Bit of Interest Control */
+ __IOM uint32_t DSLCTRL_SET; /**< Dynamic Supp Length Control */
+ __IOM uint32_t WCNTCMP4_SET; /**< Word Counter Compare 4 */
+ __IOM uint32_t WCNTCMP5_SET; /**< Word Counter Compare 5 */
+ __IOM uint32_t PKTBUFCTRL_SET; /**< Packet Capture Buffer Ctrl */
+ __IM uint32_t PKTBUFSTATUS_SET; /**< Packet Capture Buffer Status */
+ __IM uint32_t PKTBUF0_SET; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF1_SET; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF2_SET; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF3_SET; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF4_SET; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF5_SET; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF6_SET; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF7_SET; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF8_SET; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF9_SET; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF10_SET; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF11_SET; /**< Packet Capture Data Buffer */
+ FRC_FCD_TypeDef FCD_SET[4U]; /**< Frame Descriptors */
+ uint32_t RESERVED8[10U]; /**< Reserved for future use */
+ FRC_INTELEMENT_TypeDef INTELEMENT_SET[16U]; /**< Interleaver element */
+ __IOM uint32_t AHBCONFIG_SET; /**< AHB Configuration */
+ uint32_t RESERVED9[927U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP Version */
+ __IOM uint32_t EN_CLR; /**< Enable peripheral clock to this module */
+ __IM uint32_t STATUS_CLR; /**< FRC Status */
+ __IOM uint32_t DFLCTRL_CLR; /**< Dynamic Frame Length Control */
+ __IOM uint32_t MAXLENGTH_CLR; /**< Maximum Frame Length Register */
+ __IOM uint32_t ADDRFILTCTRL_CLR; /**< Address Filter Control */
+ __IOM uint32_t DATABUFFER_CLR; /**< Frame controller data buffer */
+ __IM uint32_t WCNT_CLR; /**< Word Counter Value Register */
+ __IOM uint32_t WCNTCMP0_CLR; /**< Word Counter Compare 0 */
+ __IOM uint32_t WCNTCMP1_CLR; /**< Word Counter Compare 1 */
+ __IOM uint32_t WCNTCMP2_CLR; /**< Word Counter Compare 2 */
+ __IOM uint32_t CMD_CLR; /**< FRC Commands */
+ __IOM uint32_t WHITECTRL_CLR; /**< Whitener Control */
+ __IOM uint32_t WHITEPOLY_CLR; /**< Whitener Polynomial */
+ __IOM uint32_t WHITEINIT_CLR; /**< Whitener Initial Value */
+ __IOM uint32_t FECCTRL_CLR; /**< Forward Error Correction Control */
+ __IOM uint32_t BLOCKRAMADDR_CLR; /**< Block decoding RAM address register */
+ __IOM uint32_t CONVRAMADDR_CLR; /**< Convolutional decoding RAM address */
+ __IOM uint32_t CTRL_CLR; /**< Control Register */
+ __IOM uint32_t RXCTRL_CLR; /**< RX Control Register */
+ __IOM uint32_t TRAILTXDATACTRL_CLR; /**< Trailing TX Data Control */
+ __IOM uint32_t TRAILRXDATA_CLR; /**< Trailing RX Data */
+ __IM uint32_t SCNT_CLR; /**< Sub-Frame Counter Value Register */
+ __IOM uint32_t CONVGENERATOR_CLR; /**< Convolutional Coder Polynomials */
+ __IOM uint32_t PUNCTCTRL_CLR; /**< Puncturing Control */
+ __IOM uint32_t PAUSECTRL_CLR; /**< Pause Control */
+ __IOM uint32_t IF_CLR; /**< Frame Controller Interrupt Flags */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
+ __IM uint32_t OTACNT_CLR; /**< Over the air number of bits counter */
+ uint32_t RESERVED10[1U]; /**< Reserved for future use */
+ __IOM uint32_t BUFFERMODE_CLR; /**< FRC Buffer Control */
+ uint32_t RESERVED11[2U]; /**< Reserved for future use */
+ __IOM uint32_t SNIFFCTRL_CLR; /**< FRC Sniffer Control Register */
+ __IOM uint32_t AUXDATA_CLR; /**< Auxiliary sniffer data output register */
+ __IOM uint32_t RAWCTRL_CLR; /**< Raw data control */
+ __IM uint32_t RXRAWDATA_CLR; /**< Receiver RAW data */
+ __IM uint32_t PAUSEDATA_CLR; /**< Receiver pause data */
+ __IM uint32_t LIKELYCONVSTATE_CLR; /**< Most likely convolutional decoder state */
+ __IM uint32_t INTELEMENTNEXT_CLR; /**< Interleaver element value */
+ __IOM uint32_t INTWRITEPOINT_CLR; /**< Interleaver write pointer */
+ __IOM uint32_t INTREADPOINT_CLR; /**< Interleaver read pointer */
+ __IOM uint32_t AUTOCG_CLR; /**< Automatic clock gating */
+ __IOM uint32_t CGCLKSTOP_CLR; /**< Automatic clock gating */
+ uint32_t RESERVED12[1U]; /**< Reserved for future use */
+ __IOM uint32_t SEQIF_CLR; /**< SEQ Frame Controller Interrupt Flags */
+ __IOM uint32_t SEQIEN_CLR; /**< SEQ Interrupt Enable Register */
+ __IOM uint32_t WCNTCMP3_CLR; /**< Word Counter Compare 3 */
+ __IOM uint32_t BOICTRL_CLR; /**< Bit of Interest Control */
+ __IOM uint32_t DSLCTRL_CLR; /**< Dynamic Supp Length Control */
+ __IOM uint32_t WCNTCMP4_CLR; /**< Word Counter Compare 4 */
+ __IOM uint32_t WCNTCMP5_CLR; /**< Word Counter Compare 5 */
+ __IOM uint32_t PKTBUFCTRL_CLR; /**< Packet Capture Buffer Ctrl */
+ __IM uint32_t PKTBUFSTATUS_CLR; /**< Packet Capture Buffer Status */
+ __IM uint32_t PKTBUF0_CLR; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF1_CLR; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF2_CLR; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF3_CLR; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF4_CLR; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF5_CLR; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF6_CLR; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF7_CLR; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF8_CLR; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF9_CLR; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF10_CLR; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF11_CLR; /**< Packet Capture Data Buffer */
+ FRC_FCD_TypeDef FCD_CLR[4U]; /**< Frame Descriptors */
+ uint32_t RESERVED13[10U]; /**< Reserved for future use */
+ FRC_INTELEMENT_TypeDef INTELEMENT_CLR[16U]; /**< Interleaver element */
+ __IOM uint32_t AHBCONFIG_CLR; /**< AHB Configuration */
+ uint32_t RESERVED14[927U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP Version */
+ __IOM uint32_t EN_TGL; /**< Enable peripheral clock to this module */
+ __IM uint32_t STATUS_TGL; /**< FRC Status */
+ __IOM uint32_t DFLCTRL_TGL; /**< Dynamic Frame Length Control */
+ __IOM uint32_t MAXLENGTH_TGL; /**< Maximum Frame Length Register */
+ __IOM uint32_t ADDRFILTCTRL_TGL; /**< Address Filter Control */
+ __IOM uint32_t DATABUFFER_TGL; /**< Frame controller data buffer */
+ __IM uint32_t WCNT_TGL; /**< Word Counter Value Register */
+ __IOM uint32_t WCNTCMP0_TGL; /**< Word Counter Compare 0 */
+ __IOM uint32_t WCNTCMP1_TGL; /**< Word Counter Compare 1 */
+ __IOM uint32_t WCNTCMP2_TGL; /**< Word Counter Compare 2 */
+ __IOM uint32_t CMD_TGL; /**< FRC Commands */
+ __IOM uint32_t WHITECTRL_TGL; /**< Whitener Control */
+ __IOM uint32_t WHITEPOLY_TGL; /**< Whitener Polynomial */
+ __IOM uint32_t WHITEINIT_TGL; /**< Whitener Initial Value */
+ __IOM uint32_t FECCTRL_TGL; /**< Forward Error Correction Control */
+ __IOM uint32_t BLOCKRAMADDR_TGL; /**< Block decoding RAM address register */
+ __IOM uint32_t CONVRAMADDR_TGL; /**< Convolutional decoding RAM address */
+ __IOM uint32_t CTRL_TGL; /**< Control Register */
+ __IOM uint32_t RXCTRL_TGL; /**< RX Control Register */
+ __IOM uint32_t TRAILTXDATACTRL_TGL; /**< Trailing TX Data Control */
+ __IOM uint32_t TRAILRXDATA_TGL; /**< Trailing RX Data */
+ __IM uint32_t SCNT_TGL; /**< Sub-Frame Counter Value Register */
+ __IOM uint32_t CONVGENERATOR_TGL; /**< Convolutional Coder Polynomials */
+ __IOM uint32_t PUNCTCTRL_TGL; /**< Puncturing Control */
+ __IOM uint32_t PAUSECTRL_TGL; /**< Pause Control */
+ __IOM uint32_t IF_TGL; /**< Frame Controller Interrupt Flags */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
+ __IM uint32_t OTACNT_TGL; /**< Over the air number of bits counter */
+ uint32_t RESERVED15[1U]; /**< Reserved for future use */
+ __IOM uint32_t BUFFERMODE_TGL; /**< FRC Buffer Control */
+ uint32_t RESERVED16[2U]; /**< Reserved for future use */
+ __IOM uint32_t SNIFFCTRL_TGL; /**< FRC Sniffer Control Register */
+ __IOM uint32_t AUXDATA_TGL; /**< Auxiliary sniffer data output register */
+ __IOM uint32_t RAWCTRL_TGL; /**< Raw data control */
+ __IM uint32_t RXRAWDATA_TGL; /**< Receiver RAW data */
+ __IM uint32_t PAUSEDATA_TGL; /**< Receiver pause data */
+ __IM uint32_t LIKELYCONVSTATE_TGL; /**< Most likely convolutional decoder state */
+ __IM uint32_t INTELEMENTNEXT_TGL; /**< Interleaver element value */
+ __IOM uint32_t INTWRITEPOINT_TGL; /**< Interleaver write pointer */
+ __IOM uint32_t INTREADPOINT_TGL; /**< Interleaver read pointer */
+ __IOM uint32_t AUTOCG_TGL; /**< Automatic clock gating */
+ __IOM uint32_t CGCLKSTOP_TGL; /**< Automatic clock gating */
+ uint32_t RESERVED17[1U]; /**< Reserved for future use */
+ __IOM uint32_t SEQIF_TGL; /**< SEQ Frame Controller Interrupt Flags */
+ __IOM uint32_t SEQIEN_TGL; /**< SEQ Interrupt Enable Register */
+ __IOM uint32_t WCNTCMP3_TGL; /**< Word Counter Compare 3 */
+ __IOM uint32_t BOICTRL_TGL; /**< Bit of Interest Control */
+ __IOM uint32_t DSLCTRL_TGL; /**< Dynamic Supp Length Control */
+ __IOM uint32_t WCNTCMP4_TGL; /**< Word Counter Compare 4 */
+ __IOM uint32_t WCNTCMP5_TGL; /**< Word Counter Compare 5 */
+ __IOM uint32_t PKTBUFCTRL_TGL; /**< Packet Capture Buffer Ctrl */
+ __IM uint32_t PKTBUFSTATUS_TGL; /**< Packet Capture Buffer Status */
+ __IM uint32_t PKTBUF0_TGL; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF1_TGL; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF2_TGL; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF3_TGL; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF4_TGL; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF5_TGL; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF6_TGL; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF7_TGL; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF8_TGL; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF9_TGL; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF10_TGL; /**< Packet Capture Data Buffer */
+ __IM uint32_t PKTBUF11_TGL; /**< Packet Capture Data Buffer */
+ FRC_FCD_TypeDef FCD_TGL[4U]; /**< Frame Descriptors */
+ uint32_t RESERVED18[10U]; /**< Reserved for future use */
+ FRC_INTELEMENT_TypeDef INTELEMENT_TGL[16U]; /**< Interleaver element */
+ __IOM uint32_t AHBCONFIG_TGL; /**< AHB Configuration */
+} FRC_TypeDef;
+/** @} End of group EFR32MG24_FRC */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_FRC
+ * @{
+ * @defgroup EFR32MG24_FRC_BitFields FRC Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for FRC IPVERSION */
+#define _FRC_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for FRC_IPVERSION */
+#define _FRC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for FRC_IPVERSION */
+#define _FRC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for FRC_IPVERSION */
+#define _FRC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for FRC_IPVERSION */
+#define _FRC_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for FRC_IPVERSION */
+#define FRC_IPVERSION_IPVERSION_DEFAULT (_FRC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_IPVERSION */
+
+/* Bit fields for FRC EN */
+#define _FRC_EN_RESETVALUE 0x00000000UL /**< Default value for FRC_EN */
+#define _FRC_EN_MASK 0x00000001UL /**< Mask for FRC_EN */
+#define FRC_EN_EN (0x1UL << 0) /**< Enable peripheral clock to this module */
+#define _FRC_EN_EN_SHIFT 0 /**< Shift value for FRC_EN */
+#define _FRC_EN_EN_MASK 0x1UL /**< Bit mask for FRC_EN */
+#define _FRC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_EN */
+#define FRC_EN_EN_DEFAULT (_FRC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_EN */
+
+/* Bit fields for FRC STATUS */
+#define _FRC_STATUS_RESETVALUE 0x00000000UL /**< Default value for FRC_STATUS */
+#define _FRC_STATUS_MASK 0x07FFFFFFUL /**< Mask for FRC_STATUS */
+#define _FRC_STATUS_SNIFFDCOUNT_SHIFT 0 /**< Shift value for FRC_SNIFFDCOUNT */
+#define _FRC_STATUS_SNIFFDCOUNT_MASK 0x1FUL /**< Bit mask for FRC_SNIFFDCOUNT */
+#define _FRC_STATUS_SNIFFDCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_SNIFFDCOUNT_DEFAULT (_FRC_STATUS_SNIFFDCOUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_ACTIVETXFCD (0x1UL << 5) /**< Active Transmit Frame Descriptor */
+#define _FRC_STATUS_ACTIVETXFCD_SHIFT 5 /**< Shift value for FRC_ACTIVETXFCD */
+#define _FRC_STATUS_ACTIVETXFCD_MASK 0x20UL /**< Bit mask for FRC_ACTIVETXFCD */
+#define _FRC_STATUS_ACTIVETXFCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */
+#define _FRC_STATUS_ACTIVETXFCD_FCD0 0x00000000UL /**< Mode FCD0 for FRC_STATUS */
+#define _FRC_STATUS_ACTIVETXFCD_FCD1 0x00000001UL /**< Mode FCD1 for FRC_STATUS */
+#define FRC_STATUS_ACTIVETXFCD_DEFAULT (_FRC_STATUS_ACTIVETXFCD_DEFAULT << 5) /**< Shifted mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_ACTIVETXFCD_FCD0 (_FRC_STATUS_ACTIVETXFCD_FCD0 << 5) /**< Shifted mode FCD0 for FRC_STATUS */
+#define FRC_STATUS_ACTIVETXFCD_FCD1 (_FRC_STATUS_ACTIVETXFCD_FCD1 << 5) /**< Shifted mode FCD1 for FRC_STATUS */
+#define FRC_STATUS_ACTIVERXFCD (0x1UL << 6) /**< Active Receive Frame Descriptor */
+#define _FRC_STATUS_ACTIVERXFCD_SHIFT 6 /**< Shift value for FRC_ACTIVERXFCD */
+#define _FRC_STATUS_ACTIVERXFCD_MASK 0x40UL /**< Bit mask for FRC_ACTIVERXFCD */
+#define _FRC_STATUS_ACTIVERXFCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */
+#define _FRC_STATUS_ACTIVERXFCD_FCD2 0x00000000UL /**< Mode FCD2 for FRC_STATUS */
+#define _FRC_STATUS_ACTIVERXFCD_FCD3 0x00000001UL /**< Mode FCD3 for FRC_STATUS */
+#define FRC_STATUS_ACTIVERXFCD_DEFAULT (_FRC_STATUS_ACTIVERXFCD_DEFAULT << 6) /**< Shifted mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_ACTIVERXFCD_FCD2 (_FRC_STATUS_ACTIVERXFCD_FCD2 << 6) /**< Shifted mode FCD2 for FRC_STATUS */
+#define FRC_STATUS_ACTIVERXFCD_FCD3 (_FRC_STATUS_ACTIVERXFCD_FCD3 << 6) /**< Shifted mode FCD3 for FRC_STATUS */
+#define FRC_STATUS_SNIFFDFRAME (0x1UL << 7) /**< Sniffer data frame active status */
+#define _FRC_STATUS_SNIFFDFRAME_SHIFT 7 /**< Shift value for FRC_SNIFFDFRAME */
+#define _FRC_STATUS_SNIFFDFRAME_MASK 0x80UL /**< Bit mask for FRC_SNIFFDFRAME */
+#define _FRC_STATUS_SNIFFDFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_SNIFFDFRAME_DEFAULT (_FRC_STATUS_SNIFFDFRAME_DEFAULT << 7) /**< Shifted mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_RXRAWBLOCKED (0x1UL << 8) /**< Receiver raw trigger block is active */
+#define _FRC_STATUS_RXRAWBLOCKED_SHIFT 8 /**< Shift value for FRC_RXRAWBLOCKED */
+#define _FRC_STATUS_RXRAWBLOCKED_MASK 0x100UL /**< Bit mask for FRC_RXRAWBLOCKED */
+#define _FRC_STATUS_RXRAWBLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_RXRAWBLOCKED_DEFAULT (_FRC_STATUS_RXRAWBLOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_FRAMEOK (0x1UL << 9) /**< Frame valid */
+#define _FRC_STATUS_FRAMEOK_SHIFT 9 /**< Shift value for FRC_FRAMEOK */
+#define _FRC_STATUS_FRAMEOK_MASK 0x200UL /**< Bit mask for FRC_FRAMEOK */
+#define _FRC_STATUS_FRAMEOK_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_FRAMEOK_DEFAULT (_FRC_STATUS_FRAMEOK_DEFAULT << 9) /**< Shifted mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_RXABORTINPROGRESS (0x1UL << 10) /**< Receive aborted in progress status flag */
+#define _FRC_STATUS_RXABORTINPROGRESS_SHIFT 10 /**< Shift value for FRC_RXABORTINPROGRESS */
+#define _FRC_STATUS_RXABORTINPROGRESS_MASK 0x400UL /**< Bit mask for FRC_RXABORTINPROGRESS */
+#define _FRC_STATUS_RXABORTINPROGRESS_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_RXABORTINPROGRESS_DEFAULT (_FRC_STATUS_RXABORTINPROGRESS_DEFAULT << 10) /**< Shifted mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_TXWORD (0x1UL << 11) /**< Transmit Word Flag */
+#define _FRC_STATUS_TXWORD_SHIFT 11 /**< Shift value for FRC_TXWORD */
+#define _FRC_STATUS_TXWORD_MASK 0x800UL /**< Bit mask for FRC_TXWORD */
+#define _FRC_STATUS_TXWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_TXWORD_DEFAULT (_FRC_STATUS_TXWORD_DEFAULT << 11) /**< Shifted mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_RXWORD (0x1UL << 12) /**< Receive Word Flag */
+#define _FRC_STATUS_RXWORD_SHIFT 12 /**< Shift value for FRC_RXWORD */
+#define _FRC_STATUS_RXWORD_MASK 0x1000UL /**< Bit mask for FRC_RXWORD */
+#define _FRC_STATUS_RXWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_RXWORD_DEFAULT (_FRC_STATUS_RXWORD_DEFAULT << 12) /**< Shifted mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_CONVPAUSED (0x1UL << 13) /**< Convolutional coder pause event active */
+#define _FRC_STATUS_CONVPAUSED_SHIFT 13 /**< Shift value for FRC_CONVPAUSED */
+#define _FRC_STATUS_CONVPAUSED_MASK 0x2000UL /**< Bit mask for FRC_CONVPAUSED */
+#define _FRC_STATUS_CONVPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_CONVPAUSED_DEFAULT (_FRC_STATUS_CONVPAUSED_DEFAULT << 13) /**< Shifted mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_TXSUBFRAMEPAUSED (0x1UL << 14) /**< Transmit subframe pause event active */
+#define _FRC_STATUS_TXSUBFRAMEPAUSED_SHIFT 14 /**< Shift value for FRC_TXSUBFRAMEPAUSED */
+#define _FRC_STATUS_TXSUBFRAMEPAUSED_MASK 0x4000UL /**< Bit mask for FRC_TXSUBFRAMEPAUSED */
+#define _FRC_STATUS_TXSUBFRAMEPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_TXSUBFRAMEPAUSED_DEFAULT (_FRC_STATUS_TXSUBFRAMEPAUSED_DEFAULT << 14) /**< Shifted mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_INTERLEAVEREADPAUSED (0x1UL << 15) /**< Interleaver read pause event active */
+#define _FRC_STATUS_INTERLEAVEREADPAUSED_SHIFT 15 /**< Shift value for FRC_INTERLEAVEREADPAUSED */
+#define _FRC_STATUS_INTERLEAVEREADPAUSED_MASK 0x8000UL /**< Bit mask for FRC_INTERLEAVEREADPAUSED */
+#define _FRC_STATUS_INTERLEAVEREADPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_INTERLEAVEREADPAUSED_DEFAULT (_FRC_STATUS_INTERLEAVEREADPAUSED_DEFAULT << 15) /**< Shifted mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_INTERLEAVEWRITEPAUSED (0x1UL << 16) /**< Interleaver write pause event active */
+#define _FRC_STATUS_INTERLEAVEWRITEPAUSED_SHIFT 16 /**< Shift value for FRC_INTERLEAVEWRITEPAUSED */
+#define _FRC_STATUS_INTERLEAVEWRITEPAUSED_MASK 0x10000UL /**< Bit mask for FRC_INTERLEAVEWRITEPAUSED */
+#define _FRC_STATUS_INTERLEAVEWRITEPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_INTERLEAVEWRITEPAUSED_DEFAULT (_FRC_STATUS_INTERLEAVEWRITEPAUSED_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_FRAMEDETPAUSED (0x1UL << 17) /**< Frame detected pause event active */
+#define _FRC_STATUS_FRAMEDETPAUSED_SHIFT 17 /**< Shift value for FRC_FRAMEDETPAUSED */
+#define _FRC_STATUS_FRAMEDETPAUSED_MASK 0x20000UL /**< Bit mask for FRC_FRAMEDETPAUSED */
+#define _FRC_STATUS_FRAMEDETPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_FRAMEDETPAUSED_DEFAULT (_FRC_STATUS_FRAMEDETPAUSED_DEFAULT << 17) /**< Shifted mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_FRAMELENGTHERROR (0x1UL << 18) /**< Frame Length Error for RX and TX */
+#define _FRC_STATUS_FRAMELENGTHERROR_SHIFT 18 /**< Shift value for FRC_FRAMELENGTHERROR */
+#define _FRC_STATUS_FRAMELENGTHERROR_MASK 0x40000UL /**< Bit mask for FRC_FRAMELENGTHERROR */
+#define _FRC_STATUS_FRAMELENGTHERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_FRAMELENGTHERROR_DEFAULT (_FRC_STATUS_FRAMELENGTHERROR_DEFAULT << 18) /**< Shifted mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_DEMODERROR (0x1UL << 19) /**< Demod Error in RX */
+#define _FRC_STATUS_DEMODERROR_SHIFT 19 /**< Shift value for FRC_DEMODERROR */
+#define _FRC_STATUS_DEMODERROR_MASK 0x80000UL /**< Bit mask for FRC_DEMODERROR */
+#define _FRC_STATUS_DEMODERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_DEMODERROR_DEFAULT (_FRC_STATUS_DEMODERROR_DEFAULT << 19) /**< Shifted mode DEFAULT for FRC_STATUS */
+#define _FRC_STATUS_FSMSTATE_SHIFT 20 /**< Shift value for FRC_FSMSTATE */
+#define _FRC_STATUS_FSMSTATE_MASK 0x1F00000UL /**< Bit mask for FRC_FSMSTATE */
+#define _FRC_STATUS_FSMSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */
+#define _FRC_STATUS_FSMSTATE_IDLE 0x00000000UL /**< Mode IDLE for FRC_STATUS */
+#define _FRC_STATUS_FSMSTATE_RX_INIT 0x00000001UL /**< Mode RX_INIT for FRC_STATUS */
+#define _FRC_STATUS_FSMSTATE_RX_DATA 0x00000002UL /**< Mode RX_DATA for FRC_STATUS */
+#define _FRC_STATUS_FSMSTATE_RX_CRC 0x00000003UL /**< Mode RX_CRC for FRC_STATUS */
+#define _FRC_STATUS_FSMSTATE_RX_FCD_UPDATE 0x00000004UL /**< Mode RX_FCD_UPDATE for FRC_STATUS */
+#define _FRC_STATUS_FSMSTATE_RX_DISCARD 0x00000005UL /**< Mode RX_DISCARD for FRC_STATUS */
+#define _FRC_STATUS_FSMSTATE_RX_TRAIL 0x00000006UL /**< Mode RX_TRAIL for FRC_STATUS */
+#define _FRC_STATUS_FSMSTATE_RX_DONE 0x00000007UL /**< Mode RX_DONE for FRC_STATUS */
+#define _FRC_STATUS_FSMSTATE_RX_PAUSE_INIT 0x00000008UL /**< Mode RX_PAUSE_INIT for FRC_STATUS */
+#define _FRC_STATUS_FSMSTATE_RX_PAUSED 0x00000009UL /**< Mode RX_PAUSED for FRC_STATUS */
+#define _FRC_STATUS_FSMSTATE_UNDEFINED1 0x0000000AUL /**< Mode UNDEFINED1 for FRC_STATUS */
+#define _FRC_STATUS_FSMSTATE_UNDEFINED2 0x0000000BUL /**< Mode UNDEFINED2 for FRC_STATUS */
+#define _FRC_STATUS_FSMSTATE_RX_CRC_ZEROCHECK 0x0000000CUL /**< Mode RX_CRC_ZEROCHECK for FRC_STATUS */
+#define _FRC_STATUS_FSMSTATE_RX_SUP 0x0000000DUL /**< Mode RX_SUP for FRC_STATUS */
+#define _FRC_STATUS_FSMSTATE_RX_WAITEOF 0x0000000EUL /**< Mode RX_WAITEOF for FRC_STATUS */
+#define _FRC_STATUS_FSMSTATE_UNDEFINED3 0x0000000FUL /**< Mode UNDEFINED3 for FRC_STATUS */
+#define _FRC_STATUS_FSMSTATE_TX_INIT 0x00000010UL /**< Mode TX_INIT for FRC_STATUS */
+#define _FRC_STATUS_FSMSTATE_TX_DATA 0x00000011UL /**< Mode TX_DATA for FRC_STATUS */
+#define _FRC_STATUS_FSMSTATE_TX_CRC 0x00000012UL /**< Mode TX_CRC for FRC_STATUS */
+#define _FRC_STATUS_FSMSTATE_TX_FCD_UPDATE 0x00000013UL /**< Mode TX_FCD_UPDATE for FRC_STATUS */
+#define _FRC_STATUS_FSMSTATE_TX_TRAIL 0x00000014UL /**< Mode TX_TRAIL for FRC_STATUS */
+#define _FRC_STATUS_FSMSTATE_TX_FLUSH 0x00000015UL /**< Mode TX_FLUSH for FRC_STATUS */
+#define _FRC_STATUS_FSMSTATE_TX_DONE 0x00000016UL /**< Mode TX_DONE for FRC_STATUS */
+#define _FRC_STATUS_FSMSTATE_TX_DONE_WAIT 0x00000017UL /**< Mode TX_DONE_WAIT for FRC_STATUS */
+#define _FRC_STATUS_FSMSTATE_TX_RAW 0x00000018UL /**< Mode TX_RAW for FRC_STATUS */
+#define _FRC_STATUS_FSMSTATE_TX_PAUSEFLUSH 0x00000019UL /**< Mode TX_PAUSEFLUSH for FRC_STATUS */
+#define FRC_STATUS_FSMSTATE_DEFAULT (_FRC_STATUS_FSMSTATE_DEFAULT << 20) /**< Shifted mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_FSMSTATE_IDLE (_FRC_STATUS_FSMSTATE_IDLE << 20) /**< Shifted mode IDLE for FRC_STATUS */
+#define FRC_STATUS_FSMSTATE_RX_INIT (_FRC_STATUS_FSMSTATE_RX_INIT << 20) /**< Shifted mode RX_INIT for FRC_STATUS */
+#define FRC_STATUS_FSMSTATE_RX_DATA (_FRC_STATUS_FSMSTATE_RX_DATA << 20) /**< Shifted mode RX_DATA for FRC_STATUS */
+#define FRC_STATUS_FSMSTATE_RX_CRC (_FRC_STATUS_FSMSTATE_RX_CRC << 20) /**< Shifted mode RX_CRC for FRC_STATUS */
+#define FRC_STATUS_FSMSTATE_RX_FCD_UPDATE (_FRC_STATUS_FSMSTATE_RX_FCD_UPDATE << 20) /**< Shifted mode RX_FCD_UPDATE for FRC_STATUS */
+#define FRC_STATUS_FSMSTATE_RX_DISCARD (_FRC_STATUS_FSMSTATE_RX_DISCARD << 20) /**< Shifted mode RX_DISCARD for FRC_STATUS */
+#define FRC_STATUS_FSMSTATE_RX_TRAIL (_FRC_STATUS_FSMSTATE_RX_TRAIL << 20) /**< Shifted mode RX_TRAIL for FRC_STATUS */
+#define FRC_STATUS_FSMSTATE_RX_DONE (_FRC_STATUS_FSMSTATE_RX_DONE << 20) /**< Shifted mode RX_DONE for FRC_STATUS */
+#define FRC_STATUS_FSMSTATE_RX_PAUSE_INIT (_FRC_STATUS_FSMSTATE_RX_PAUSE_INIT << 20) /**< Shifted mode RX_PAUSE_INIT for FRC_STATUS */
+#define FRC_STATUS_FSMSTATE_RX_PAUSED (_FRC_STATUS_FSMSTATE_RX_PAUSED << 20) /**< Shifted mode RX_PAUSED for FRC_STATUS */
+#define FRC_STATUS_FSMSTATE_UNDEFINED1 (_FRC_STATUS_FSMSTATE_UNDEFINED1 << 20) /**< Shifted mode UNDEFINED1 for FRC_STATUS */
+#define FRC_STATUS_FSMSTATE_UNDEFINED2 (_FRC_STATUS_FSMSTATE_UNDEFINED2 << 20) /**< Shifted mode UNDEFINED2 for FRC_STATUS */
+#define FRC_STATUS_FSMSTATE_RX_CRC_ZEROCHECK (_FRC_STATUS_FSMSTATE_RX_CRC_ZEROCHECK << 20) /**< Shifted mode RX_CRC_ZEROCHECK for FRC_STATUS*/
+#define FRC_STATUS_FSMSTATE_RX_SUP (_FRC_STATUS_FSMSTATE_RX_SUP << 20) /**< Shifted mode RX_SUP for FRC_STATUS */
+#define FRC_STATUS_FSMSTATE_RX_WAITEOF (_FRC_STATUS_FSMSTATE_RX_WAITEOF << 20) /**< Shifted mode RX_WAITEOF for FRC_STATUS */
+#define FRC_STATUS_FSMSTATE_UNDEFINED3 (_FRC_STATUS_FSMSTATE_UNDEFINED3 << 20) /**< Shifted mode UNDEFINED3 for FRC_STATUS */
+#define FRC_STATUS_FSMSTATE_TX_INIT (_FRC_STATUS_FSMSTATE_TX_INIT << 20) /**< Shifted mode TX_INIT for FRC_STATUS */
+#define FRC_STATUS_FSMSTATE_TX_DATA (_FRC_STATUS_FSMSTATE_TX_DATA << 20) /**< Shifted mode TX_DATA for FRC_STATUS */
+#define FRC_STATUS_FSMSTATE_TX_CRC (_FRC_STATUS_FSMSTATE_TX_CRC << 20) /**< Shifted mode TX_CRC for FRC_STATUS */
+#define FRC_STATUS_FSMSTATE_TX_FCD_UPDATE (_FRC_STATUS_FSMSTATE_TX_FCD_UPDATE << 20) /**< Shifted mode TX_FCD_UPDATE for FRC_STATUS */
+#define FRC_STATUS_FSMSTATE_TX_TRAIL (_FRC_STATUS_FSMSTATE_TX_TRAIL << 20) /**< Shifted mode TX_TRAIL for FRC_STATUS */
+#define FRC_STATUS_FSMSTATE_TX_FLUSH (_FRC_STATUS_FSMSTATE_TX_FLUSH << 20) /**< Shifted mode TX_FLUSH for FRC_STATUS */
+#define FRC_STATUS_FSMSTATE_TX_DONE (_FRC_STATUS_FSMSTATE_TX_DONE << 20) /**< Shifted mode TX_DONE for FRC_STATUS */
+#define FRC_STATUS_FSMSTATE_TX_DONE_WAIT (_FRC_STATUS_FSMSTATE_TX_DONE_WAIT << 20) /**< Shifted mode TX_DONE_WAIT for FRC_STATUS */
+#define FRC_STATUS_FSMSTATE_TX_RAW (_FRC_STATUS_FSMSTATE_TX_RAW << 20) /**< Shifted mode TX_RAW for FRC_STATUS */
+#define FRC_STATUS_FSMSTATE_TX_PAUSEFLUSH (_FRC_STATUS_FSMSTATE_TX_PAUSEFLUSH << 20) /**< Shifted mode TX_PAUSEFLUSH for FRC_STATUS */
+#define FRC_STATUS_RXWCNTMATCHPAUSED (0x1UL << 25) /**< Nth byte received pause event active */
+#define _FRC_STATUS_RXWCNTMATCHPAUSED_SHIFT 25 /**< Shift value for FRC_RXWCNTMATCHPAUSED */
+#define _FRC_STATUS_RXWCNTMATCHPAUSED_MASK 0x2000000UL /**< Bit mask for FRC_RXWCNTMATCHPAUSED */
+#define _FRC_STATUS_RXWCNTMATCHPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_RXWCNTMATCHPAUSED_DEFAULT (_FRC_STATUS_RXWCNTMATCHPAUSED_DEFAULT << 25) /**< Shifted mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_CRCERRORTOLERATED (0x1UL << 26) /**< CRC error tolerated */
+#define _FRC_STATUS_CRCERRORTOLERATED_SHIFT 26 /**< Shift value for FRC_CRCERRORTOLERATED */
+#define _FRC_STATUS_CRCERRORTOLERATED_MASK 0x4000000UL /**< Bit mask for FRC_CRCERRORTOLERATED */
+#define _FRC_STATUS_CRCERRORTOLERATED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_STATUS */
+#define FRC_STATUS_CRCERRORTOLERATED_DEFAULT (_FRC_STATUS_CRCERRORTOLERATED_DEFAULT << 26) /**< Shifted mode DEFAULT for FRC_STATUS */
+
+/* Bit fields for FRC DFLCTRL */
+#define _FRC_DFLCTRL_RESETVALUE 0x00000000UL /**< Default value for FRC_DFLCTRL */
+#define _FRC_DFLCTRL_MASK 0x01FFFF7FUL /**< Mask for FRC_DFLCTRL */
+#define _FRC_DFLCTRL_DFLMODE_SHIFT 0 /**< Shift value for FRC_DFLMODE */
+#define _FRC_DFLCTRL_DFLMODE_MASK 0x7UL /**< Bit mask for FRC_DFLMODE */
+#define _FRC_DFLCTRL_DFLMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DFLCTRL */
+#define _FRC_DFLCTRL_DFLMODE_DISABLE 0x00000000UL /**< Mode DISABLE for FRC_DFLCTRL */
+#define _FRC_DFLCTRL_DFLMODE_SINGLEBYTE 0x00000001UL /**< Mode SINGLEBYTE for FRC_DFLCTRL */
+#define _FRC_DFLCTRL_DFLMODE_SINGLEBYTEMSB 0x00000002UL /**< Mode SINGLEBYTEMSB for FRC_DFLCTRL */
+#define _FRC_DFLCTRL_DFLMODE_DUALBYTELSBFIRST 0x00000003UL /**< Mode DUALBYTELSBFIRST for FRC_DFLCTRL */
+#define _FRC_DFLCTRL_DFLMODE_DUALBYTEMSBFIRST 0x00000004UL /**< Mode DUALBYTEMSBFIRST for FRC_DFLCTRL */
+#define _FRC_DFLCTRL_DFLMODE_INFINITE 0x00000005UL /**< Mode INFINITE for FRC_DFLCTRL */
+#define _FRC_DFLCTRL_DFLMODE_BLOCKERROR 0x00000006UL /**< Mode BLOCKERROR for FRC_DFLCTRL */
+#define FRC_DFLCTRL_DFLMODE_DEFAULT (_FRC_DFLCTRL_DFLMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_DFLCTRL */
+#define FRC_DFLCTRL_DFLMODE_DISABLE (_FRC_DFLCTRL_DFLMODE_DISABLE << 0) /**< Shifted mode DISABLE for FRC_DFLCTRL */
+#define FRC_DFLCTRL_DFLMODE_SINGLEBYTE (_FRC_DFLCTRL_DFLMODE_SINGLEBYTE << 0) /**< Shifted mode SINGLEBYTE for FRC_DFLCTRL */
+#define FRC_DFLCTRL_DFLMODE_SINGLEBYTEMSB (_FRC_DFLCTRL_DFLMODE_SINGLEBYTEMSB << 0) /**< Shifted mode SINGLEBYTEMSB for FRC_DFLCTRL */
+#define FRC_DFLCTRL_DFLMODE_DUALBYTELSBFIRST (_FRC_DFLCTRL_DFLMODE_DUALBYTELSBFIRST << 0) /**< Shifted mode DUALBYTELSBFIRST for FRC_DFLCTRL*/
+#define FRC_DFLCTRL_DFLMODE_DUALBYTEMSBFIRST (_FRC_DFLCTRL_DFLMODE_DUALBYTEMSBFIRST << 0) /**< Shifted mode DUALBYTEMSBFIRST for FRC_DFLCTRL*/
+#define FRC_DFLCTRL_DFLMODE_INFINITE (_FRC_DFLCTRL_DFLMODE_INFINITE << 0) /**< Shifted mode INFINITE for FRC_DFLCTRL */
+#define FRC_DFLCTRL_DFLMODE_BLOCKERROR (_FRC_DFLCTRL_DFLMODE_BLOCKERROR << 0) /**< Shifted mode BLOCKERROR for FRC_DFLCTRL */
+#define FRC_DFLCTRL_DFLBITORDER (0x1UL << 3) /**< Dynamic Frame Length Bit order */
+#define _FRC_DFLCTRL_DFLBITORDER_SHIFT 3 /**< Shift value for FRC_DFLBITORDER */
+#define _FRC_DFLCTRL_DFLBITORDER_MASK 0x8UL /**< Bit mask for FRC_DFLBITORDER */
+#define _FRC_DFLCTRL_DFLBITORDER_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DFLCTRL */
+#define _FRC_DFLCTRL_DFLBITORDER_NORMAL 0x00000000UL /**< Mode NORMAL for FRC_DFLCTRL */
+#define _FRC_DFLCTRL_DFLBITORDER_REVERSE 0x00000001UL /**< Mode REVERSE for FRC_DFLCTRL */
+#define FRC_DFLCTRL_DFLBITORDER_DEFAULT (_FRC_DFLCTRL_DFLBITORDER_DEFAULT << 3) /**< Shifted mode DEFAULT for FRC_DFLCTRL */
+#define FRC_DFLCTRL_DFLBITORDER_NORMAL (_FRC_DFLCTRL_DFLBITORDER_NORMAL << 3) /**< Shifted mode NORMAL for FRC_DFLCTRL */
+#define FRC_DFLCTRL_DFLBITORDER_REVERSE (_FRC_DFLCTRL_DFLBITORDER_REVERSE << 3) /**< Shifted mode REVERSE for FRC_DFLCTRL */
+#define _FRC_DFLCTRL_DFLSHIFT_SHIFT 4 /**< Shift value for FRC_DFLSHIFT */
+#define _FRC_DFLCTRL_DFLSHIFT_MASK 0x70UL /**< Bit mask for FRC_DFLSHIFT */
+#define _FRC_DFLCTRL_DFLSHIFT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DFLCTRL */
+#define FRC_DFLCTRL_DFLSHIFT_DEFAULT (_FRC_DFLCTRL_DFLSHIFT_DEFAULT << 4) /**< Shifted mode DEFAULT for FRC_DFLCTRL */
+#define _FRC_DFLCTRL_DFLOFFSET_SHIFT 8 /**< Shift value for FRC_DFLOFFSET */
+#define _FRC_DFLCTRL_DFLOFFSET_MASK 0xF00UL /**< Bit mask for FRC_DFLOFFSET */
+#define _FRC_DFLCTRL_DFLOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DFLCTRL */
+#define FRC_DFLCTRL_DFLOFFSET_DEFAULT (_FRC_DFLCTRL_DFLOFFSET_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_DFLCTRL */
+#define _FRC_DFLCTRL_DFLBITS_SHIFT 12 /**< Shift value for FRC_DFLBITS */
+#define _FRC_DFLCTRL_DFLBITS_MASK 0xF000UL /**< Bit mask for FRC_DFLBITS */
+#define _FRC_DFLCTRL_DFLBITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DFLCTRL */
+#define FRC_DFLCTRL_DFLBITS_DEFAULT (_FRC_DFLCTRL_DFLBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for FRC_DFLCTRL */
+#define _FRC_DFLCTRL_MINLENGTH_SHIFT 16 /**< Shift value for FRC_MINLENGTH */
+#define _FRC_DFLCTRL_MINLENGTH_MASK 0xF0000UL /**< Bit mask for FRC_MINLENGTH */
+#define _FRC_DFLCTRL_MINLENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DFLCTRL */
+#define FRC_DFLCTRL_MINLENGTH_DEFAULT (_FRC_DFLCTRL_MINLENGTH_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_DFLCTRL */
+#define FRC_DFLCTRL_DFLINCLUDECRC (0x1UL << 20) /**< Length field includes CRC values or not */
+#define _FRC_DFLCTRL_DFLINCLUDECRC_SHIFT 20 /**< Shift value for FRC_DFLINCLUDECRC */
+#define _FRC_DFLCTRL_DFLINCLUDECRC_MASK 0x100000UL /**< Bit mask for FRC_DFLINCLUDECRC */
+#define _FRC_DFLCTRL_DFLINCLUDECRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DFLCTRL */
+#define _FRC_DFLCTRL_DFLINCLUDECRC_X0 0x00000000UL /**< Mode X0 for FRC_DFLCTRL */
+#define _FRC_DFLCTRL_DFLINCLUDECRC_X1 0x00000001UL /**< Mode X1 for FRC_DFLCTRL */
+#define FRC_DFLCTRL_DFLINCLUDECRC_DEFAULT (_FRC_DFLCTRL_DFLINCLUDECRC_DEFAULT << 20) /**< Shifted mode DEFAULT for FRC_DFLCTRL */
+#define FRC_DFLCTRL_DFLINCLUDECRC_X0 (_FRC_DFLCTRL_DFLINCLUDECRC_X0 << 20) /**< Shifted mode X0 for FRC_DFLCTRL */
+#define FRC_DFLCTRL_DFLINCLUDECRC_X1 (_FRC_DFLCTRL_DFLINCLUDECRC_X1 << 20) /**< Shifted mode X1 for FRC_DFLCTRL */
+#define _FRC_DFLCTRL_DFLBOIOFFSET_SHIFT 21 /**< Shift value for FRC_DFLBOIOFFSET */
+#define _FRC_DFLCTRL_DFLBOIOFFSET_MASK 0x1E00000UL /**< Bit mask for FRC_DFLBOIOFFSET */
+#define _FRC_DFLCTRL_DFLBOIOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DFLCTRL */
+#define FRC_DFLCTRL_DFLBOIOFFSET_DEFAULT (_FRC_DFLCTRL_DFLBOIOFFSET_DEFAULT << 21) /**< Shifted mode DEFAULT for FRC_DFLCTRL */
+
+/* Bit fields for FRC MAXLENGTH */
+#define _FRC_MAXLENGTH_RESETVALUE 0x00004FFFUL /**< Default value for FRC_MAXLENGTH */
+#define _FRC_MAXLENGTH_MASK 0x0000FFFFUL /**< Mask for FRC_MAXLENGTH */
+#define _FRC_MAXLENGTH_MAXLENGTH_SHIFT 0 /**< Shift value for FRC_MAXLENGTH */
+#define _FRC_MAXLENGTH_MAXLENGTH_MASK 0xFFFUL /**< Bit mask for FRC_MAXLENGTH */
+#define _FRC_MAXLENGTH_MAXLENGTH_DEFAULT 0x00000FFFUL /**< Mode DEFAULT for FRC_MAXLENGTH */
+#define FRC_MAXLENGTH_MAXLENGTH_DEFAULT (_FRC_MAXLENGTH_MAXLENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_MAXLENGTH */
+#define _FRC_MAXLENGTH_INILENGTH_SHIFT 12 /**< Shift value for FRC_INILENGTH */
+#define _FRC_MAXLENGTH_INILENGTH_MASK 0xF000UL /**< Bit mask for FRC_INILENGTH */
+#define _FRC_MAXLENGTH_INILENGTH_DEFAULT 0x00000004UL /**< Mode DEFAULT for FRC_MAXLENGTH */
+#define FRC_MAXLENGTH_INILENGTH_DEFAULT (_FRC_MAXLENGTH_INILENGTH_DEFAULT << 12) /**< Shifted mode DEFAULT for FRC_MAXLENGTH */
+
+/* Bit fields for FRC ADDRFILTCTRL */
+#define _FRC_ADDRFILTCTRL_RESETVALUE 0x00000000UL /**< Default value for FRC_ADDRFILTCTRL */
+#define _FRC_ADDRFILTCTRL_MASK 0x0000FF07UL /**< Mask for FRC_ADDRFILTCTRL */
+#define FRC_ADDRFILTCTRL_EN (0x1UL << 0) /**< Address Filter Enable */
+#define _FRC_ADDRFILTCTRL_EN_SHIFT 0 /**< Shift value for FRC_EN */
+#define _FRC_ADDRFILTCTRL_EN_MASK 0x1UL /**< Bit mask for FRC_EN */
+#define _FRC_ADDRFILTCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_ADDRFILTCTRL */
+#define FRC_ADDRFILTCTRL_EN_DEFAULT (_FRC_ADDRFILTCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_ADDRFILTCTRL */
+#define FRC_ADDRFILTCTRL_BRDCST00EN (0x1UL << 1) /**< Broadcast Address 0x00 Enable */
+#define _FRC_ADDRFILTCTRL_BRDCST00EN_SHIFT 1 /**< Shift value for FRC_BRDCST00EN */
+#define _FRC_ADDRFILTCTRL_BRDCST00EN_MASK 0x2UL /**< Bit mask for FRC_BRDCST00EN */
+#define _FRC_ADDRFILTCTRL_BRDCST00EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_ADDRFILTCTRL */
+#define FRC_ADDRFILTCTRL_BRDCST00EN_DEFAULT (_FRC_ADDRFILTCTRL_BRDCST00EN_DEFAULT << 1) /**< Shifted mode DEFAULT for FRC_ADDRFILTCTRL */
+#define FRC_ADDRFILTCTRL_BRDCSTFFEN (0x1UL << 2) /**< Broadcast Address 0xFF Enable */
+#define _FRC_ADDRFILTCTRL_BRDCSTFFEN_SHIFT 2 /**< Shift value for FRC_BRDCSTFFEN */
+#define _FRC_ADDRFILTCTRL_BRDCSTFFEN_MASK 0x4UL /**< Bit mask for FRC_BRDCSTFFEN */
+#define _FRC_ADDRFILTCTRL_BRDCSTFFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_ADDRFILTCTRL */
+#define FRC_ADDRFILTCTRL_BRDCSTFFEN_DEFAULT (_FRC_ADDRFILTCTRL_BRDCSTFFEN_DEFAULT << 2) /**< Shifted mode DEFAULT for FRC_ADDRFILTCTRL */
+#define _FRC_ADDRFILTCTRL_ADDRESS_SHIFT 8 /**< Shift value for FRC_ADDRESS */
+#define _FRC_ADDRFILTCTRL_ADDRESS_MASK 0xFF00UL /**< Bit mask for FRC_ADDRESS */
+#define _FRC_ADDRFILTCTRL_ADDRESS_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_ADDRFILTCTRL */
+#define FRC_ADDRFILTCTRL_ADDRESS_DEFAULT (_FRC_ADDRFILTCTRL_ADDRESS_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_ADDRFILTCTRL */
+
+/* Bit fields for FRC DATABUFFER */
+#define _FRC_DATABUFFER_RESETVALUE 0x00000000UL /**< Default value for FRC_DATABUFFER */
+#define _FRC_DATABUFFER_MASK 0x000000FFUL /**< Mask for FRC_DATABUFFER */
+#define _FRC_DATABUFFER_DATABUFFER_SHIFT 0 /**< Shift value for FRC_DATABUFFER */
+#define _FRC_DATABUFFER_DATABUFFER_MASK 0xFFUL /**< Bit mask for FRC_DATABUFFER */
+#define _FRC_DATABUFFER_DATABUFFER_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DATABUFFER */
+#define FRC_DATABUFFER_DATABUFFER_DEFAULT (_FRC_DATABUFFER_DATABUFFER_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_DATABUFFER */
+
+/* Bit fields for FRC WCNT */
+#define _FRC_WCNT_RESETVALUE 0x00000000UL /**< Default value for FRC_WCNT */
+#define _FRC_WCNT_MASK 0x00000FFFUL /**< Mask for FRC_WCNT */
+#define _FRC_WCNT_WCNT_SHIFT 0 /**< Shift value for FRC_WCNT */
+#define _FRC_WCNT_WCNT_MASK 0xFFFUL /**< Bit mask for FRC_WCNT */
+#define _FRC_WCNT_WCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_WCNT */
+#define FRC_WCNT_WCNT_DEFAULT (_FRC_WCNT_WCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_WCNT */
+
+/* Bit fields for FRC WCNTCMP0 */
+#define _FRC_WCNTCMP0_RESETVALUE 0x00000000UL /**< Default value for FRC_WCNTCMP0 */
+#define _FRC_WCNTCMP0_MASK 0x00000FFFUL /**< Mask for FRC_WCNTCMP0 */
+#define _FRC_WCNTCMP0_FRAMELENGTH_SHIFT 0 /**< Shift value for FRC_FRAMELENGTH */
+#define _FRC_WCNTCMP0_FRAMELENGTH_MASK 0xFFFUL /**< Bit mask for FRC_FRAMELENGTH */
+#define _FRC_WCNTCMP0_FRAMELENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_WCNTCMP0 */
+#define FRC_WCNTCMP0_FRAMELENGTH_DEFAULT (_FRC_WCNTCMP0_FRAMELENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_WCNTCMP0 */
+
+/* Bit fields for FRC WCNTCMP1 */
+#define _FRC_WCNTCMP1_RESETVALUE 0x00000000UL /**< Default value for FRC_WCNTCMP1 */
+#define _FRC_WCNTCMP1_MASK 0x00000FFFUL /**< Mask for FRC_WCNTCMP1 */
+#define _FRC_WCNTCMP1_LENGTHFIELDLOC_SHIFT 0 /**< Shift value for FRC_LENGTHFIELDLOC */
+#define _FRC_WCNTCMP1_LENGTHFIELDLOC_MASK 0xFFFUL /**< Bit mask for FRC_LENGTHFIELDLOC */
+#define _FRC_WCNTCMP1_LENGTHFIELDLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_WCNTCMP1 */
+#define FRC_WCNTCMP1_LENGTHFIELDLOC_DEFAULT (_FRC_WCNTCMP1_LENGTHFIELDLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_WCNTCMP1 */
+
+/* Bit fields for FRC WCNTCMP2 */
+#define _FRC_WCNTCMP2_RESETVALUE 0x00000000UL /**< Default value for FRC_WCNTCMP2 */
+#define _FRC_WCNTCMP2_MASK 0x00000FFFUL /**< Mask for FRC_WCNTCMP2 */
+#define _FRC_WCNTCMP2_ADDRFIELDLOC_SHIFT 0 /**< Shift value for FRC_ADDRFIELDLOC */
+#define _FRC_WCNTCMP2_ADDRFIELDLOC_MASK 0xFFFUL /**< Bit mask for FRC_ADDRFIELDLOC */
+#define _FRC_WCNTCMP2_ADDRFIELDLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_WCNTCMP2 */
+#define FRC_WCNTCMP2_ADDRFIELDLOC_DEFAULT (_FRC_WCNTCMP2_ADDRFIELDLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_WCNTCMP2 */
+
+/* Bit fields for FRC CMD */
+#define _FRC_CMD_RESETVALUE 0x00000000UL /**< Default value for FRC_CMD */
+#define _FRC_CMD_MASK 0x00003FFFUL /**< Mask for FRC_CMD */
+#define FRC_CMD_RXABORT (0x1UL << 0) /**< RX Abort */
+#define _FRC_CMD_RXABORT_SHIFT 0 /**< Shift value for FRC_RXABORT */
+#define _FRC_CMD_RXABORT_MASK 0x1UL /**< Bit mask for FRC_RXABORT */
+#define _FRC_CMD_RXABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CMD */
+#define FRC_CMD_RXABORT_DEFAULT (_FRC_CMD_RXABORT_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_CMD */
+#define FRC_CMD_FRAMEDETRESUME (0x1UL << 1) /**< FRAMEDET resume */
+#define _FRC_CMD_FRAMEDETRESUME_SHIFT 1 /**< Shift value for FRC_FRAMEDETRESUME */
+#define _FRC_CMD_FRAMEDETRESUME_MASK 0x2UL /**< Bit mask for FRC_FRAMEDETRESUME */
+#define _FRC_CMD_FRAMEDETRESUME_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CMD */
+#define FRC_CMD_FRAMEDETRESUME_DEFAULT (_FRC_CMD_FRAMEDETRESUME_DEFAULT << 1) /**< Shifted mode DEFAULT for FRC_CMD */
+#define FRC_CMD_INTERLEAVEWRITERESUME (0x1UL << 2) /**< Interleaver write resume */
+#define _FRC_CMD_INTERLEAVEWRITERESUME_SHIFT 2 /**< Shift value for FRC_INTERLEAVEWRITERESUME */
+#define _FRC_CMD_INTERLEAVEWRITERESUME_MASK 0x4UL /**< Bit mask for FRC_INTERLEAVEWRITERESUME */
+#define _FRC_CMD_INTERLEAVEWRITERESUME_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CMD */
+#define FRC_CMD_INTERLEAVEWRITERESUME_DEFAULT (_FRC_CMD_INTERLEAVEWRITERESUME_DEFAULT << 2) /**< Shifted mode DEFAULT for FRC_CMD */
+#define FRC_CMD_INTERLEAVEREADRESUME (0x1UL << 3) /**< Interleaver read resume */
+#define _FRC_CMD_INTERLEAVEREADRESUME_SHIFT 3 /**< Shift value for FRC_INTERLEAVEREADRESUME */
+#define _FRC_CMD_INTERLEAVEREADRESUME_MASK 0x8UL /**< Bit mask for FRC_INTERLEAVEREADRESUME */
+#define _FRC_CMD_INTERLEAVEREADRESUME_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CMD */
+#define FRC_CMD_INTERLEAVEREADRESUME_DEFAULT (_FRC_CMD_INTERLEAVEREADRESUME_DEFAULT << 3) /**< Shifted mode DEFAULT for FRC_CMD */
+#define FRC_CMD_CONVRESUME (0x1UL << 4) /**< Convolutional coder resume */
+#define _FRC_CMD_CONVRESUME_SHIFT 4 /**< Shift value for FRC_CONVRESUME */
+#define _FRC_CMD_CONVRESUME_MASK 0x10UL /**< Bit mask for FRC_CONVRESUME */
+#define _FRC_CMD_CONVRESUME_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CMD */
+#define FRC_CMD_CONVRESUME_DEFAULT (_FRC_CMD_CONVRESUME_DEFAULT << 4) /**< Shifted mode DEFAULT for FRC_CMD */
+#define FRC_CMD_CONVTERMINATE (0x1UL << 5) /**< Convolutional coder termination */
+#define _FRC_CMD_CONVTERMINATE_SHIFT 5 /**< Shift value for FRC_CONVTERMINATE */
+#define _FRC_CMD_CONVTERMINATE_MASK 0x20UL /**< Bit mask for FRC_CONVTERMINATE */
+#define _FRC_CMD_CONVTERMINATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CMD */
+#define FRC_CMD_CONVTERMINATE_DEFAULT (_FRC_CMD_CONVTERMINATE_DEFAULT << 5) /**< Shifted mode DEFAULT for FRC_CMD */
+#define FRC_CMD_TXSUBFRAMERESUME (0x1UL << 6) /**< TX subframe resume */
+#define _FRC_CMD_TXSUBFRAMERESUME_SHIFT 6 /**< Shift value for FRC_TXSUBFRAMERESUME */
+#define _FRC_CMD_TXSUBFRAMERESUME_MASK 0x40UL /**< Bit mask for FRC_TXSUBFRAMERESUME */
+#define _FRC_CMD_TXSUBFRAMERESUME_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CMD */
+#define FRC_CMD_TXSUBFRAMERESUME_DEFAULT (_FRC_CMD_TXSUBFRAMERESUME_DEFAULT << 6) /**< Shifted mode DEFAULT for FRC_CMD */
+#define FRC_CMD_INTERLEAVEINIT (0x1UL << 7) /**< Interleaver initialization */
+#define _FRC_CMD_INTERLEAVEINIT_SHIFT 7 /**< Shift value for FRC_INTERLEAVEINIT */
+#define _FRC_CMD_INTERLEAVEINIT_MASK 0x80UL /**< Bit mask for FRC_INTERLEAVEINIT */
+#define _FRC_CMD_INTERLEAVEINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CMD */
+#define FRC_CMD_INTERLEAVEINIT_DEFAULT (_FRC_CMD_INTERLEAVEINIT_DEFAULT << 7) /**< Shifted mode DEFAULT for FRC_CMD */
+#define FRC_CMD_INTERLEAVECNTCLEAR (0x1UL << 8) /**< Interleaver counter clear */
+#define _FRC_CMD_INTERLEAVECNTCLEAR_SHIFT 8 /**< Shift value for FRC_INTERLEAVECNTCLEAR */
+#define _FRC_CMD_INTERLEAVECNTCLEAR_MASK 0x100UL /**< Bit mask for FRC_INTERLEAVECNTCLEAR */
+#define _FRC_CMD_INTERLEAVECNTCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CMD */
+#define FRC_CMD_INTERLEAVECNTCLEAR_DEFAULT (_FRC_CMD_INTERLEAVECNTCLEAR_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_CMD */
+#define FRC_CMD_CONVINIT (0x1UL << 9) /**< Convolutional coder initialize */
+#define _FRC_CMD_CONVINIT_SHIFT 9 /**< Shift value for FRC_CONVINIT */
+#define _FRC_CMD_CONVINIT_MASK 0x200UL /**< Bit mask for FRC_CONVINIT */
+#define _FRC_CMD_CONVINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CMD */
+#define FRC_CMD_CONVINIT_DEFAULT (_FRC_CMD_CONVINIT_DEFAULT << 9) /**< Shifted mode DEFAULT for FRC_CMD */
+#define FRC_CMD_BLOCKINIT (0x1UL << 10) /**< Block coder initialize */
+#define _FRC_CMD_BLOCKINIT_SHIFT 10 /**< Shift value for FRC_BLOCKINIT */
+#define _FRC_CMD_BLOCKINIT_MASK 0x400UL /**< Bit mask for FRC_BLOCKINIT */
+#define _FRC_CMD_BLOCKINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CMD */
+#define FRC_CMD_BLOCKINIT_DEFAULT (_FRC_CMD_BLOCKINIT_DEFAULT << 10) /**< Shifted mode DEFAULT for FRC_CMD */
+#define FRC_CMD_STATEINIT (0x1UL << 11) /**< FRC State initialize */
+#define _FRC_CMD_STATEINIT_SHIFT 11 /**< Shift value for FRC_STATEINIT */
+#define _FRC_CMD_STATEINIT_MASK 0x800UL /**< Bit mask for FRC_STATEINIT */
+#define _FRC_CMD_STATEINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CMD */
+#define FRC_CMD_STATEINIT_DEFAULT (_FRC_CMD_STATEINIT_DEFAULT << 11) /**< Shifted mode DEFAULT for FRC_CMD */
+#define FRC_CMD_RXRAWUNBLOCK (0x1UL << 12) /**< Clear RXRAWBLOCKED status flag */
+#define _FRC_CMD_RXRAWUNBLOCK_SHIFT 12 /**< Shift value for FRC_RXRAWUNBLOCK */
+#define _FRC_CMD_RXRAWUNBLOCK_MASK 0x1000UL /**< Bit mask for FRC_RXRAWUNBLOCK */
+#define _FRC_CMD_RXRAWUNBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CMD */
+#define FRC_CMD_RXRAWUNBLOCK_DEFAULT (_FRC_CMD_RXRAWUNBLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for FRC_CMD */
+#define FRC_CMD_RXPAUSERESUME (0x1UL << 13) /**< RX pause on nth byte resume */
+#define _FRC_CMD_RXPAUSERESUME_SHIFT 13 /**< Shift value for FRC_RXPAUSERESUME */
+#define _FRC_CMD_RXPAUSERESUME_MASK 0x2000UL /**< Bit mask for FRC_RXPAUSERESUME */
+#define _FRC_CMD_RXPAUSERESUME_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CMD */
+#define FRC_CMD_RXPAUSERESUME_DEFAULT (_FRC_CMD_RXPAUSERESUME_DEFAULT << 13) /**< Shifted mode DEFAULT for FRC_CMD */
+
+/* Bit fields for FRC WHITECTRL */
+#define _FRC_WHITECTRL_RESETVALUE 0x00000000UL /**< Default value for FRC_WHITECTRL */
+#define _FRC_WHITECTRL_MASK 0x00001F7FUL /**< Mask for FRC_WHITECTRL */
+#define _FRC_WHITECTRL_FEEDBACKSEL_SHIFT 0 /**< Shift value for FRC_FEEDBACKSEL */
+#define _FRC_WHITECTRL_FEEDBACKSEL_MASK 0x1FUL /**< Bit mask for FRC_FEEDBACKSEL */
+#define _FRC_WHITECTRL_FEEDBACKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_WHITECTRL */
+#define _FRC_WHITECTRL_FEEDBACKSEL_BIT0 0x00000000UL /**< Mode BIT0 for FRC_WHITECTRL */
+#define _FRC_WHITECTRL_FEEDBACKSEL_BIT1 0x00000001UL /**< Mode BIT1 for FRC_WHITECTRL */
+#define _FRC_WHITECTRL_FEEDBACKSEL_BIT2 0x00000002UL /**< Mode BIT2 for FRC_WHITECTRL */
+#define _FRC_WHITECTRL_FEEDBACKSEL_BIT3 0x00000003UL /**< Mode BIT3 for FRC_WHITECTRL */
+#define _FRC_WHITECTRL_FEEDBACKSEL_BIT4 0x00000004UL /**< Mode BIT4 for FRC_WHITECTRL */
+#define _FRC_WHITECTRL_FEEDBACKSEL_BIT5 0x00000005UL /**< Mode BIT5 for FRC_WHITECTRL */
+#define _FRC_WHITECTRL_FEEDBACKSEL_BIT6 0x00000006UL /**< Mode BIT6 for FRC_WHITECTRL */
+#define _FRC_WHITECTRL_FEEDBACKSEL_BIT7 0x00000007UL /**< Mode BIT7 for FRC_WHITECTRL */
+#define _FRC_WHITECTRL_FEEDBACKSEL_BIT8 0x00000008UL /**< Mode BIT8 for FRC_WHITECTRL */
+#define _FRC_WHITECTRL_FEEDBACKSEL_BIT9 0x00000009UL /**< Mode BIT9 for FRC_WHITECTRL */
+#define _FRC_WHITECTRL_FEEDBACKSEL_BIT10 0x0000000AUL /**< Mode BIT10 for FRC_WHITECTRL */
+#define _FRC_WHITECTRL_FEEDBACKSEL_BIT11 0x0000000BUL /**< Mode BIT11 for FRC_WHITECTRL */
+#define _FRC_WHITECTRL_FEEDBACKSEL_BIT12 0x0000000CUL /**< Mode BIT12 for FRC_WHITECTRL */
+#define _FRC_WHITECTRL_FEEDBACKSEL_BIT13 0x0000000DUL /**< Mode BIT13 for FRC_WHITECTRL */
+#define _FRC_WHITECTRL_FEEDBACKSEL_BIT14 0x0000000EUL /**< Mode BIT14 for FRC_WHITECTRL */
+#define _FRC_WHITECTRL_FEEDBACKSEL_BIT15 0x0000000FUL /**< Mode BIT15 for FRC_WHITECTRL */
+#define _FRC_WHITECTRL_FEEDBACKSEL_INPUT 0x00000010UL /**< Mode INPUT for FRC_WHITECTRL */
+#define _FRC_WHITECTRL_FEEDBACKSEL_ZERO 0x00000011UL /**< Mode ZERO for FRC_WHITECTRL */
+#define _FRC_WHITECTRL_FEEDBACKSEL_ONE 0x00000012UL /**< Mode ONE for FRC_WHITECTRL */
+#define _FRC_WHITECTRL_FEEDBACKSEL_TXLASTWORD 0x00000013UL /**< Mode TXLASTWORD for FRC_WHITECTRL */
+#define FRC_WHITECTRL_FEEDBACKSEL_DEFAULT (_FRC_WHITECTRL_FEEDBACKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_WHITECTRL */
+#define FRC_WHITECTRL_FEEDBACKSEL_BIT0 (_FRC_WHITECTRL_FEEDBACKSEL_BIT0 << 0) /**< Shifted mode BIT0 for FRC_WHITECTRL */
+#define FRC_WHITECTRL_FEEDBACKSEL_BIT1 (_FRC_WHITECTRL_FEEDBACKSEL_BIT1 << 0) /**< Shifted mode BIT1 for FRC_WHITECTRL */
+#define FRC_WHITECTRL_FEEDBACKSEL_BIT2 (_FRC_WHITECTRL_FEEDBACKSEL_BIT2 << 0) /**< Shifted mode BIT2 for FRC_WHITECTRL */
+#define FRC_WHITECTRL_FEEDBACKSEL_BIT3 (_FRC_WHITECTRL_FEEDBACKSEL_BIT3 << 0) /**< Shifted mode BIT3 for FRC_WHITECTRL */
+#define FRC_WHITECTRL_FEEDBACKSEL_BIT4 (_FRC_WHITECTRL_FEEDBACKSEL_BIT4 << 0) /**< Shifted mode BIT4 for FRC_WHITECTRL */
+#define FRC_WHITECTRL_FEEDBACKSEL_BIT5 (_FRC_WHITECTRL_FEEDBACKSEL_BIT5 << 0) /**< Shifted mode BIT5 for FRC_WHITECTRL */
+#define FRC_WHITECTRL_FEEDBACKSEL_BIT6 (_FRC_WHITECTRL_FEEDBACKSEL_BIT6 << 0) /**< Shifted mode BIT6 for FRC_WHITECTRL */
+#define FRC_WHITECTRL_FEEDBACKSEL_BIT7 (_FRC_WHITECTRL_FEEDBACKSEL_BIT7 << 0) /**< Shifted mode BIT7 for FRC_WHITECTRL */
+#define FRC_WHITECTRL_FEEDBACKSEL_BIT8 (_FRC_WHITECTRL_FEEDBACKSEL_BIT8 << 0) /**< Shifted mode BIT8 for FRC_WHITECTRL */
+#define FRC_WHITECTRL_FEEDBACKSEL_BIT9 (_FRC_WHITECTRL_FEEDBACKSEL_BIT9 << 0) /**< Shifted mode BIT9 for FRC_WHITECTRL */
+#define FRC_WHITECTRL_FEEDBACKSEL_BIT10 (_FRC_WHITECTRL_FEEDBACKSEL_BIT10 << 0) /**< Shifted mode BIT10 for FRC_WHITECTRL */
+#define FRC_WHITECTRL_FEEDBACKSEL_BIT11 (_FRC_WHITECTRL_FEEDBACKSEL_BIT11 << 0) /**< Shifted mode BIT11 for FRC_WHITECTRL */
+#define FRC_WHITECTRL_FEEDBACKSEL_BIT12 (_FRC_WHITECTRL_FEEDBACKSEL_BIT12 << 0) /**< Shifted mode BIT12 for FRC_WHITECTRL */
+#define FRC_WHITECTRL_FEEDBACKSEL_BIT13 (_FRC_WHITECTRL_FEEDBACKSEL_BIT13 << 0) /**< Shifted mode BIT13 for FRC_WHITECTRL */
+#define FRC_WHITECTRL_FEEDBACKSEL_BIT14 (_FRC_WHITECTRL_FEEDBACKSEL_BIT14 << 0) /**< Shifted mode BIT14 for FRC_WHITECTRL */
+#define FRC_WHITECTRL_FEEDBACKSEL_BIT15 (_FRC_WHITECTRL_FEEDBACKSEL_BIT15 << 0) /**< Shifted mode BIT15 for FRC_WHITECTRL */
+#define FRC_WHITECTRL_FEEDBACKSEL_INPUT (_FRC_WHITECTRL_FEEDBACKSEL_INPUT << 0) /**< Shifted mode INPUT for FRC_WHITECTRL */
+#define FRC_WHITECTRL_FEEDBACKSEL_ZERO (_FRC_WHITECTRL_FEEDBACKSEL_ZERO << 0) /**< Shifted mode ZERO for FRC_WHITECTRL */
+#define FRC_WHITECTRL_FEEDBACKSEL_ONE (_FRC_WHITECTRL_FEEDBACKSEL_ONE << 0) /**< Shifted mode ONE for FRC_WHITECTRL */
+#define FRC_WHITECTRL_FEEDBACKSEL_TXLASTWORD (_FRC_WHITECTRL_FEEDBACKSEL_TXLASTWORD << 0) /**< Shifted mode TXLASTWORD for FRC_WHITECTRL */
+#define _FRC_WHITECTRL_XORFEEDBACK_SHIFT 5 /**< Shift value for FRC_XORFEEDBACK */
+#define _FRC_WHITECTRL_XORFEEDBACK_MASK 0x60UL /**< Bit mask for FRC_XORFEEDBACK */
+#define _FRC_WHITECTRL_XORFEEDBACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_WHITECTRL */
+#define _FRC_WHITECTRL_XORFEEDBACK_DIRECT 0x00000000UL /**< Mode DIRECT for FRC_WHITECTRL */
+#define _FRC_WHITECTRL_XORFEEDBACK_XOR 0x00000001UL /**< Mode XOR for FRC_WHITECTRL */
+#define _FRC_WHITECTRL_XORFEEDBACK_ZERO 0x00000002UL /**< Mode ZERO for FRC_WHITECTRL */
+#define FRC_WHITECTRL_XORFEEDBACK_DEFAULT (_FRC_WHITECTRL_XORFEEDBACK_DEFAULT << 5) /**< Shifted mode DEFAULT for FRC_WHITECTRL */
+#define FRC_WHITECTRL_XORFEEDBACK_DIRECT (_FRC_WHITECTRL_XORFEEDBACK_DIRECT << 5) /**< Shifted mode DIRECT for FRC_WHITECTRL */
+#define FRC_WHITECTRL_XORFEEDBACK_XOR (_FRC_WHITECTRL_XORFEEDBACK_XOR << 5) /**< Shifted mode XOR for FRC_WHITECTRL */
+#define FRC_WHITECTRL_XORFEEDBACK_ZERO (_FRC_WHITECTRL_XORFEEDBACK_ZERO << 5) /**< Shifted mode ZERO for FRC_WHITECTRL */
+#define _FRC_WHITECTRL_SHROUTPUTSEL_SHIFT 8 /**< Shift value for FRC_SHROUTPUTSEL */
+#define _FRC_WHITECTRL_SHROUTPUTSEL_MASK 0xF00UL /**< Bit mask for FRC_SHROUTPUTSEL */
+#define _FRC_WHITECTRL_SHROUTPUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_WHITECTRL */
+#define FRC_WHITECTRL_SHROUTPUTSEL_DEFAULT (_FRC_WHITECTRL_SHROUTPUTSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_WHITECTRL */
+#define FRC_WHITECTRL_BLOCKERRORCORRECT (0x1UL << 12) /**< Block Errors Correction enable */
+#define _FRC_WHITECTRL_BLOCKERRORCORRECT_SHIFT 12 /**< Shift value for FRC_BLOCKERRORCORRECT */
+#define _FRC_WHITECTRL_BLOCKERRORCORRECT_MASK 0x1000UL /**< Bit mask for FRC_BLOCKERRORCORRECT */
+#define _FRC_WHITECTRL_BLOCKERRORCORRECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_WHITECTRL */
+#define _FRC_WHITECTRL_BLOCKERRORCORRECT_X0 0x00000000UL /**< Mode X0 for FRC_WHITECTRL */
+#define _FRC_WHITECTRL_BLOCKERRORCORRECT_X1 0x00000001UL /**< Mode X1 for FRC_WHITECTRL */
+#define FRC_WHITECTRL_BLOCKERRORCORRECT_DEFAULT (_FRC_WHITECTRL_BLOCKERRORCORRECT_DEFAULT << 12) /**< Shifted mode DEFAULT for FRC_WHITECTRL */
+#define FRC_WHITECTRL_BLOCKERRORCORRECT_X0 (_FRC_WHITECTRL_BLOCKERRORCORRECT_X0 << 12) /**< Shifted mode X0 for FRC_WHITECTRL */
+#define FRC_WHITECTRL_BLOCKERRORCORRECT_X1 (_FRC_WHITECTRL_BLOCKERRORCORRECT_X1 << 12) /**< Shifted mode X1 for FRC_WHITECTRL */
+
+/* Bit fields for FRC WHITEPOLY */
+#define _FRC_WHITEPOLY_RESETVALUE 0x00000000UL /**< Default value for FRC_WHITEPOLY */
+#define _FRC_WHITEPOLY_MASK 0x0000FFFFUL /**< Mask for FRC_WHITEPOLY */
+#define _FRC_WHITEPOLY_POLY_SHIFT 0 /**< Shift value for FRC_POLY */
+#define _FRC_WHITEPOLY_POLY_MASK 0xFFFFUL /**< Bit mask for FRC_POLY */
+#define _FRC_WHITEPOLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_WHITEPOLY */
+#define FRC_WHITEPOLY_POLY_DEFAULT (_FRC_WHITEPOLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_WHITEPOLY */
+
+/* Bit fields for FRC WHITEINIT */
+#define _FRC_WHITEINIT_RESETVALUE 0x00000000UL /**< Default value for FRC_WHITEINIT */
+#define _FRC_WHITEINIT_MASK 0x0000FFFFUL /**< Mask for FRC_WHITEINIT */
+#define _FRC_WHITEINIT_WHITEINIT_SHIFT 0 /**< Shift value for FRC_WHITEINIT */
+#define _FRC_WHITEINIT_WHITEINIT_MASK 0xFFFFUL /**< Bit mask for FRC_WHITEINIT */
+#define _FRC_WHITEINIT_WHITEINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_WHITEINIT */
+#define FRC_WHITEINIT_WHITEINIT_DEFAULT (_FRC_WHITEINIT_WHITEINIT_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_WHITEINIT */
+
+/* Bit fields for FRC FECCTRL */
+#define _FRC_FECCTRL_RESETVALUE 0x00000000UL /**< Default value for FRC_FECCTRL */
+#define _FRC_FECCTRL_MASK 0x003FFFF7UL /**< Mask for FRC_FECCTRL */
+#define _FRC_FECCTRL_BLOCKWHITEMODE_SHIFT 0 /**< Shift value for FRC_BLOCKWHITEMODE */
+#define _FRC_FECCTRL_BLOCKWHITEMODE_MASK 0x7UL /**< Bit mask for FRC_BLOCKWHITEMODE */
+#define _FRC_FECCTRL_BLOCKWHITEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FECCTRL */
+#define _FRC_FECCTRL_BLOCKWHITEMODE_DIRECT 0x00000000UL /**< Mode DIRECT for FRC_FECCTRL */
+#define _FRC_FECCTRL_BLOCKWHITEMODE_WHITE 0x00000001UL /**< Mode WHITE for FRC_FECCTRL */
+#define _FRC_FECCTRL_BLOCKWHITEMODE_BYTEWHITE 0x00000002UL /**< Mode BYTEWHITE for FRC_FECCTRL */
+#define _FRC_FECCTRL_BLOCKWHITEMODE_INTERLEAVEDWHITE0 0x00000003UL /**< Mode INTERLEAVEDWHITE0 for FRC_FECCTRL */
+#define _FRC_FECCTRL_BLOCKWHITEMODE_INTERLEAVEDWHITE1 0x00000004UL /**< Mode INTERLEAVEDWHITE1 for FRC_FECCTRL */
+#define _FRC_FECCTRL_BLOCKWHITEMODE_BLOCKCODEINSERT 0x00000005UL /**< Mode BLOCKCODEINSERT for FRC_FECCTRL */
+#define _FRC_FECCTRL_BLOCKWHITEMODE_BLOCKCODEREPLACE 0x00000006UL /**< Mode BLOCKCODEREPLACE for FRC_FECCTRL */
+#define _FRC_FECCTRL_BLOCKWHITEMODE_BLOCKLOOKUP 0x00000007UL /**< Mode BLOCKLOOKUP for FRC_FECCTRL */
+#define FRC_FECCTRL_BLOCKWHITEMODE_DEFAULT (_FRC_FECCTRL_BLOCKWHITEMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_FECCTRL */
+#define FRC_FECCTRL_BLOCKWHITEMODE_DIRECT (_FRC_FECCTRL_BLOCKWHITEMODE_DIRECT << 0) /**< Shifted mode DIRECT for FRC_FECCTRL */
+#define FRC_FECCTRL_BLOCKWHITEMODE_WHITE (_FRC_FECCTRL_BLOCKWHITEMODE_WHITE << 0) /**< Shifted mode WHITE for FRC_FECCTRL */
+#define FRC_FECCTRL_BLOCKWHITEMODE_BYTEWHITE (_FRC_FECCTRL_BLOCKWHITEMODE_BYTEWHITE << 0) /**< Shifted mode BYTEWHITE for FRC_FECCTRL */
+#define FRC_FECCTRL_BLOCKWHITEMODE_INTERLEAVEDWHITE0 (_FRC_FECCTRL_BLOCKWHITEMODE_INTERLEAVEDWHITE0 << 0) /**< Shifted mode INTERLEAVEDWHITE0 for FRC_FECCTRL*/
+#define FRC_FECCTRL_BLOCKWHITEMODE_INTERLEAVEDWHITE1 (_FRC_FECCTRL_BLOCKWHITEMODE_INTERLEAVEDWHITE1 << 0) /**< Shifted mode INTERLEAVEDWHITE1 for FRC_FECCTRL*/
+#define FRC_FECCTRL_BLOCKWHITEMODE_BLOCKCODEINSERT (_FRC_FECCTRL_BLOCKWHITEMODE_BLOCKCODEINSERT << 0) /**< Shifted mode BLOCKCODEINSERT for FRC_FECCTRL*/
+#define FRC_FECCTRL_BLOCKWHITEMODE_BLOCKCODEREPLACE (_FRC_FECCTRL_BLOCKWHITEMODE_BLOCKCODEREPLACE << 0) /**< Shifted mode BLOCKCODEREPLACE for FRC_FECCTRL*/
+#define FRC_FECCTRL_BLOCKWHITEMODE_BLOCKLOOKUP (_FRC_FECCTRL_BLOCKWHITEMODE_BLOCKLOOKUP << 0) /**< Shifted mode BLOCKLOOKUP for FRC_FECCTRL */
+#define _FRC_FECCTRL_CONVMODE_SHIFT 4 /**< Shift value for FRC_CONVMODE */
+#define _FRC_FECCTRL_CONVMODE_MASK 0x30UL /**< Bit mask for FRC_CONVMODE */
+#define _FRC_FECCTRL_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FECCTRL */
+#define _FRC_FECCTRL_CONVMODE_DISABLE 0x00000000UL /**< Mode DISABLE for FRC_FECCTRL */
+#define _FRC_FECCTRL_CONVMODE_CONVOLUTIONAL 0x00000001UL /**< Mode CONVOLUTIONAL for FRC_FECCTRL */
+#define _FRC_FECCTRL_CONVMODE_REPEAT 0x00000002UL /**< Mode REPEAT for FRC_FECCTRL */
+#define FRC_FECCTRL_CONVMODE_DEFAULT (_FRC_FECCTRL_CONVMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for FRC_FECCTRL */
+#define FRC_FECCTRL_CONVMODE_DISABLE (_FRC_FECCTRL_CONVMODE_DISABLE << 4) /**< Shifted mode DISABLE for FRC_FECCTRL */
+#define FRC_FECCTRL_CONVMODE_CONVOLUTIONAL (_FRC_FECCTRL_CONVMODE_CONVOLUTIONAL << 4) /**< Shifted mode CONVOLUTIONAL for FRC_FECCTRL */
+#define FRC_FECCTRL_CONVMODE_REPEAT (_FRC_FECCTRL_CONVMODE_REPEAT << 4) /**< Shifted mode REPEAT for FRC_FECCTRL */
+#define FRC_FECCTRL_CONVDECODEMODE (0x1UL << 6) /**< Convolutional decoding mode setting. */
+#define _FRC_FECCTRL_CONVDECODEMODE_SHIFT 6 /**< Shift value for FRC_CONVDECODEMODE */
+#define _FRC_FECCTRL_CONVDECODEMODE_MASK 0x40UL /**< Bit mask for FRC_CONVDECODEMODE */
+#define _FRC_FECCTRL_CONVDECODEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FECCTRL */
+#define _FRC_FECCTRL_CONVDECODEMODE_SOFT 0x00000000UL /**< Mode SOFT for FRC_FECCTRL */
+#define _FRC_FECCTRL_CONVDECODEMODE_HARD 0x00000001UL /**< Mode HARD for FRC_FECCTRL */
+#define FRC_FECCTRL_CONVDECODEMODE_DEFAULT (_FRC_FECCTRL_CONVDECODEMODE_DEFAULT << 6) /**< Shifted mode DEFAULT for FRC_FECCTRL */
+#define FRC_FECCTRL_CONVDECODEMODE_SOFT (_FRC_FECCTRL_CONVDECODEMODE_SOFT << 6) /**< Shifted mode SOFT for FRC_FECCTRL */
+#define FRC_FECCTRL_CONVDECODEMODE_HARD (_FRC_FECCTRL_CONVDECODEMODE_HARD << 6) /**< Shifted mode HARD for FRC_FECCTRL */
+#define FRC_FECCTRL_CONVTRACEBACKDISABLE (0x1UL << 7) /**< Convolutional traceback disabling */
+#define _FRC_FECCTRL_CONVTRACEBACKDISABLE_SHIFT 7 /**< Shift value for FRC_CONVTRACEBACKDISABLE */
+#define _FRC_FECCTRL_CONVTRACEBACKDISABLE_MASK 0x80UL /**< Bit mask for FRC_CONVTRACEBACKDISABLE */
+#define _FRC_FECCTRL_CONVTRACEBACKDISABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FECCTRL */
+#define _FRC_FECCTRL_CONVTRACEBACKDISABLE_X0 0x00000000UL /**< Mode X0 for FRC_FECCTRL */
+#define _FRC_FECCTRL_CONVTRACEBACKDISABLE_X1 0x00000001UL /**< Mode X1 for FRC_FECCTRL */
+#define FRC_FECCTRL_CONVTRACEBACKDISABLE_DEFAULT (_FRC_FECCTRL_CONVTRACEBACKDISABLE_DEFAULT << 7) /**< Shifted mode DEFAULT for FRC_FECCTRL */
+#define FRC_FECCTRL_CONVTRACEBACKDISABLE_X0 (_FRC_FECCTRL_CONVTRACEBACKDISABLE_X0 << 7) /**< Shifted mode X0 for FRC_FECCTRL */
+#define FRC_FECCTRL_CONVTRACEBACKDISABLE_X1 (_FRC_FECCTRL_CONVTRACEBACKDISABLE_X1 << 7) /**< Shifted mode X1 for FRC_FECCTRL */
+#define _FRC_FECCTRL_CONVINV_SHIFT 8 /**< Shift value for FRC_CONVINV */
+#define _FRC_FECCTRL_CONVINV_MASK 0x300UL /**< Bit mask for FRC_CONVINV */
+#define _FRC_FECCTRL_CONVINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FECCTRL */
+#define FRC_FECCTRL_CONVINV_DEFAULT (_FRC_FECCTRL_CONVINV_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_FECCTRL */
+#define _FRC_FECCTRL_INTERLEAVEMODE_SHIFT 10 /**< Shift value for FRC_INTERLEAVEMODE */
+#define _FRC_FECCTRL_INTERLEAVEMODE_MASK 0xC00UL /**< Bit mask for FRC_INTERLEAVEMODE */
+#define _FRC_FECCTRL_INTERLEAVEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FECCTRL */
+#define _FRC_FECCTRL_INTERLEAVEMODE_DISABLE 0x00000000UL /**< Mode DISABLE for FRC_FECCTRL */
+#define _FRC_FECCTRL_INTERLEAVEMODE_ENABLE 0x00000001UL /**< Mode ENABLE for FRC_FECCTRL */
+#define _FRC_FECCTRL_INTERLEAVEMODE_RXBUFFER 0x00000002UL /**< Mode RXBUFFER for FRC_FECCTRL */
+#define _FRC_FECCTRL_INTERLEAVEMODE_RXTXBUFFER 0x00000003UL /**< Mode RXTXBUFFER for FRC_FECCTRL */
+#define FRC_FECCTRL_INTERLEAVEMODE_DEFAULT (_FRC_FECCTRL_INTERLEAVEMODE_DEFAULT << 10) /**< Shifted mode DEFAULT for FRC_FECCTRL */
+#define FRC_FECCTRL_INTERLEAVEMODE_DISABLE (_FRC_FECCTRL_INTERLEAVEMODE_DISABLE << 10) /**< Shifted mode DISABLE for FRC_FECCTRL */
+#define FRC_FECCTRL_INTERLEAVEMODE_ENABLE (_FRC_FECCTRL_INTERLEAVEMODE_ENABLE << 10) /**< Shifted mode ENABLE for FRC_FECCTRL */
+#define FRC_FECCTRL_INTERLEAVEMODE_RXBUFFER (_FRC_FECCTRL_INTERLEAVEMODE_RXBUFFER << 10) /**< Shifted mode RXBUFFER for FRC_FECCTRL */
+#define FRC_FECCTRL_INTERLEAVEMODE_RXTXBUFFER (_FRC_FECCTRL_INTERLEAVEMODE_RXTXBUFFER << 10) /**< Shifted mode RXTXBUFFER for FRC_FECCTRL */
+#define _FRC_FECCTRL_INTERLEAVEFIRSTINDEX_SHIFT 12 /**< Shift value for FRC_INTERLEAVEFIRSTINDEX */
+#define _FRC_FECCTRL_INTERLEAVEFIRSTINDEX_MASK 0xF000UL /**< Bit mask for FRC_INTERLEAVEFIRSTINDEX */
+#define _FRC_FECCTRL_INTERLEAVEFIRSTINDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FECCTRL */
+#define FRC_FECCTRL_INTERLEAVEFIRSTINDEX_DEFAULT (_FRC_FECCTRL_INTERLEAVEFIRSTINDEX_DEFAULT << 12) /**< Shifted mode DEFAULT for FRC_FECCTRL */
+#define FRC_FECCTRL_INTERLEAVEWIDTH (0x1UL << 16) /**< Interleave symbol width. */
+#define _FRC_FECCTRL_INTERLEAVEWIDTH_SHIFT 16 /**< Shift value for FRC_INTERLEAVEWIDTH */
+#define _FRC_FECCTRL_INTERLEAVEWIDTH_MASK 0x10000UL /**< Bit mask for FRC_INTERLEAVEWIDTH */
+#define _FRC_FECCTRL_INTERLEAVEWIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FECCTRL */
+#define _FRC_FECCTRL_INTERLEAVEWIDTH_ONE 0x00000000UL /**< Mode ONE for FRC_FECCTRL */
+#define _FRC_FECCTRL_INTERLEAVEWIDTH_TWO 0x00000001UL /**< Mode TWO for FRC_FECCTRL */
+#define FRC_FECCTRL_INTERLEAVEWIDTH_DEFAULT (_FRC_FECCTRL_INTERLEAVEWIDTH_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_FECCTRL */
+#define FRC_FECCTRL_INTERLEAVEWIDTH_ONE (_FRC_FECCTRL_INTERLEAVEWIDTH_ONE << 16) /**< Shifted mode ONE for FRC_FECCTRL */
+#define FRC_FECCTRL_INTERLEAVEWIDTH_TWO (_FRC_FECCTRL_INTERLEAVEWIDTH_TWO << 16) /**< Shifted mode TWO for FRC_FECCTRL */
+#define FRC_FECCTRL_CONVBUSLOCK (0x1UL << 17) /**< Convolutional decoding bus lock */
+#define _FRC_FECCTRL_CONVBUSLOCK_SHIFT 17 /**< Shift value for FRC_CONVBUSLOCK */
+#define _FRC_FECCTRL_CONVBUSLOCK_MASK 0x20000UL /**< Bit mask for FRC_CONVBUSLOCK */
+#define _FRC_FECCTRL_CONVBUSLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FECCTRL */
+#define FRC_FECCTRL_CONVBUSLOCK_DEFAULT (_FRC_FECCTRL_CONVBUSLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for FRC_FECCTRL */
+#define FRC_FECCTRL_CONVSUBFRAMETERMINATE (0x1UL << 18) /**< Enable trellis termination for subframes */
+#define _FRC_FECCTRL_CONVSUBFRAMETERMINATE_SHIFT 18 /**< Shift value for FRC_CONVSUBFRAMETERMINATE */
+#define _FRC_FECCTRL_CONVSUBFRAMETERMINATE_MASK 0x40000UL /**< Bit mask for FRC_CONVSUBFRAMETERMINATE */
+#define _FRC_FECCTRL_CONVSUBFRAMETERMINATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FECCTRL */
+#define _FRC_FECCTRL_CONVSUBFRAMETERMINATE_X0 0x00000000UL /**< Mode X0 for FRC_FECCTRL */
+#define _FRC_FECCTRL_CONVSUBFRAMETERMINATE_X1 0x00000001UL /**< Mode X1 for FRC_FECCTRL */
+#define FRC_FECCTRL_CONVSUBFRAMETERMINATE_DEFAULT (_FRC_FECCTRL_CONVSUBFRAMETERMINATE_DEFAULT << 18) /**< Shifted mode DEFAULT for FRC_FECCTRL */
+#define FRC_FECCTRL_CONVSUBFRAMETERMINATE_X0 (_FRC_FECCTRL_CONVSUBFRAMETERMINATE_X0 << 18) /**< Shifted mode X0 for FRC_FECCTRL */
+#define FRC_FECCTRL_CONVSUBFRAMETERMINATE_X1 (_FRC_FECCTRL_CONVSUBFRAMETERMINATE_X1 << 18) /**< Shifted mode X1 for FRC_FECCTRL */
+#define FRC_FECCTRL_SINGLEBLOCK (0x1UL << 19) /**< Single block code per frame */
+#define _FRC_FECCTRL_SINGLEBLOCK_SHIFT 19 /**< Shift value for FRC_SINGLEBLOCK */
+#define _FRC_FECCTRL_SINGLEBLOCK_MASK 0x80000UL /**< Bit mask for FRC_SINGLEBLOCK */
+#define _FRC_FECCTRL_SINGLEBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FECCTRL */
+#define FRC_FECCTRL_SINGLEBLOCK_DEFAULT (_FRC_FECCTRL_SINGLEBLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for FRC_FECCTRL */
+#define FRC_FECCTRL_FORCE2FSK (0x1UL << 20) /**< Force use of 2-FSK */
+#define _FRC_FECCTRL_FORCE2FSK_SHIFT 20 /**< Shift value for FRC_FORCE2FSK */
+#define _FRC_FECCTRL_FORCE2FSK_MASK 0x100000UL /**< Bit mask for FRC_FORCE2FSK */
+#define _FRC_FECCTRL_FORCE2FSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FECCTRL */
+#define FRC_FECCTRL_FORCE2FSK_DEFAULT (_FRC_FECCTRL_FORCE2FSK_DEFAULT << 20) /**< Shifted mode DEFAULT for FRC_FECCTRL */
+#define FRC_FECCTRL_CONVHARDERROR (0x1UL << 21) /**< Enable convolutional decoding hard error */
+#define _FRC_FECCTRL_CONVHARDERROR_SHIFT 21 /**< Shift value for FRC_CONVHARDERROR */
+#define _FRC_FECCTRL_CONVHARDERROR_MASK 0x200000UL /**< Bit mask for FRC_CONVHARDERROR */
+#define _FRC_FECCTRL_CONVHARDERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FECCTRL */
+#define _FRC_FECCTRL_CONVHARDERROR_X0 0x00000000UL /**< Mode X0 for FRC_FECCTRL */
+#define _FRC_FECCTRL_CONVHARDERROR_X1 0x00000001UL /**< Mode X1 for FRC_FECCTRL */
+#define FRC_FECCTRL_CONVHARDERROR_DEFAULT (_FRC_FECCTRL_CONVHARDERROR_DEFAULT << 21) /**< Shifted mode DEFAULT for FRC_FECCTRL */
+#define FRC_FECCTRL_CONVHARDERROR_X0 (_FRC_FECCTRL_CONVHARDERROR_X0 << 21) /**< Shifted mode X0 for FRC_FECCTRL */
+#define FRC_FECCTRL_CONVHARDERROR_X1 (_FRC_FECCTRL_CONVHARDERROR_X1 << 21) /**< Shifted mode X1 for FRC_FECCTRL */
+
+/* Bit fields for FRC BLOCKRAMADDR */
+#define _FRC_BLOCKRAMADDR_RESETVALUE 0x00004000UL /**< Default value for FRC_BLOCKRAMADDR */
+#define _FRC_BLOCKRAMADDR_MASK 0xFFFFFFFCUL /**< Mask for FRC_BLOCKRAMADDR */
+#define _FRC_BLOCKRAMADDR_BLOCKRAMADDR_SHIFT 2 /**< Shift value for FRC_BLOCKRAMADDR */
+#define _FRC_BLOCKRAMADDR_BLOCKRAMADDR_MASK 0xFFFFFFFCUL /**< Bit mask for FRC_BLOCKRAMADDR */
+#define _FRC_BLOCKRAMADDR_BLOCKRAMADDR_DEFAULT 0x00001000UL /**< Mode DEFAULT for FRC_BLOCKRAMADDR */
+#define FRC_BLOCKRAMADDR_BLOCKRAMADDR_DEFAULT (_FRC_BLOCKRAMADDR_BLOCKRAMADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for FRC_BLOCKRAMADDR */
+
+/* Bit fields for FRC CONVRAMADDR */
+#define _FRC_CONVRAMADDR_RESETVALUE 0x00004000UL /**< Default value for FRC_CONVRAMADDR */
+#define _FRC_CONVRAMADDR_MASK 0xFFFFFFFCUL /**< Mask for FRC_CONVRAMADDR */
+#define _FRC_CONVRAMADDR_CONVRAMADDR_SHIFT 2 /**< Shift value for FRC_CONVRAMADDR */
+#define _FRC_CONVRAMADDR_CONVRAMADDR_MASK 0xFFFFFFFCUL /**< Bit mask for FRC_CONVRAMADDR */
+#define _FRC_CONVRAMADDR_CONVRAMADDR_DEFAULT 0x00001000UL /**< Mode DEFAULT for FRC_CONVRAMADDR */
+#define FRC_CONVRAMADDR_CONVRAMADDR_DEFAULT (_FRC_CONVRAMADDR_CONVRAMADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for FRC_CONVRAMADDR */
+
+/* Bit fields for FRC CTRL */
+#define _FRC_CTRL_RESETVALUE 0x03000700UL /**< Default value for FRC_CTRL */
+#define _FRC_CTRL_MASK 0x071F7FF7UL /**< Mask for FRC_CTRL */
+#define FRC_CTRL_RANDOMTX (0x1UL << 0) /**< Random TX Mode */
+#define _FRC_CTRL_RANDOMTX_SHIFT 0 /**< Shift value for FRC_RANDOMTX */
+#define _FRC_CTRL_RANDOMTX_MASK 0x1UL /**< Bit mask for FRC_RANDOMTX */
+#define _FRC_CTRL_RANDOMTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CTRL */
+#define FRC_CTRL_RANDOMTX_DEFAULT (_FRC_CTRL_RANDOMTX_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_CTRL */
+#define FRC_CTRL_UARTMODE (0x1UL << 1) /**< Data Uart Mode */
+#define _FRC_CTRL_UARTMODE_SHIFT 1 /**< Shift value for FRC_UARTMODE */
+#define _FRC_CTRL_UARTMODE_MASK 0x2UL /**< Bit mask for FRC_UARTMODE */
+#define _FRC_CTRL_UARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CTRL */
+#define FRC_CTRL_UARTMODE_DEFAULT (_FRC_CTRL_UARTMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for FRC_CTRL */
+#define FRC_CTRL_BITORDER (0x1UL << 2) /**< Data Bit Order. */
+#define _FRC_CTRL_BITORDER_SHIFT 2 /**< Shift value for FRC_BITORDER */
+#define _FRC_CTRL_BITORDER_MASK 0x4UL /**< Bit mask for FRC_BITORDER */
+#define _FRC_CTRL_BITORDER_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CTRL */
+#define _FRC_CTRL_BITORDER_LSBFIRST 0x00000000UL /**< Mode LSBFIRST for FRC_CTRL */
+#define _FRC_CTRL_BITORDER_MSBFIRST 0x00000001UL /**< Mode MSBFIRST for FRC_CTRL */
+#define FRC_CTRL_BITORDER_DEFAULT (_FRC_CTRL_BITORDER_DEFAULT << 2) /**< Shifted mode DEFAULT for FRC_CTRL */
+#define FRC_CTRL_BITORDER_LSBFIRST (_FRC_CTRL_BITORDER_LSBFIRST << 2) /**< Shifted mode LSBFIRST for FRC_CTRL */
+#define FRC_CTRL_BITORDER_MSBFIRST (_FRC_CTRL_BITORDER_MSBFIRST << 2) /**< Shifted mode MSBFIRST for FRC_CTRL */
+#define _FRC_CTRL_TXFCDMODE_SHIFT 4 /**< Shift value for FRC_TXFCDMODE */
+#define _FRC_CTRL_TXFCDMODE_MASK 0x30UL /**< Bit mask for FRC_TXFCDMODE */
+#define _FRC_CTRL_TXFCDMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CTRL */
+#define _FRC_CTRL_TXFCDMODE_FCDMODE0 0x00000000UL /**< Mode FCDMODE0 for FRC_CTRL */
+#define _FRC_CTRL_TXFCDMODE_FCDMODE1 0x00000001UL /**< Mode FCDMODE1 for FRC_CTRL */
+#define _FRC_CTRL_TXFCDMODE_FCDMODE2 0x00000002UL /**< Mode FCDMODE2 for FRC_CTRL */
+#define _FRC_CTRL_TXFCDMODE_FCDMODE3 0x00000003UL /**< Mode FCDMODE3 for FRC_CTRL */
+#define FRC_CTRL_TXFCDMODE_DEFAULT (_FRC_CTRL_TXFCDMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for FRC_CTRL */
+#define FRC_CTRL_TXFCDMODE_FCDMODE0 (_FRC_CTRL_TXFCDMODE_FCDMODE0 << 4) /**< Shifted mode FCDMODE0 for FRC_CTRL */
+#define FRC_CTRL_TXFCDMODE_FCDMODE1 (_FRC_CTRL_TXFCDMODE_FCDMODE1 << 4) /**< Shifted mode FCDMODE1 for FRC_CTRL */
+#define FRC_CTRL_TXFCDMODE_FCDMODE2 (_FRC_CTRL_TXFCDMODE_FCDMODE2 << 4) /**< Shifted mode FCDMODE2 for FRC_CTRL */
+#define FRC_CTRL_TXFCDMODE_FCDMODE3 (_FRC_CTRL_TXFCDMODE_FCDMODE3 << 4) /**< Shifted mode FCDMODE3 for FRC_CTRL */
+#define _FRC_CTRL_RXFCDMODE_SHIFT 6 /**< Shift value for FRC_RXFCDMODE */
+#define _FRC_CTRL_RXFCDMODE_MASK 0xC0UL /**< Bit mask for FRC_RXFCDMODE */
+#define _FRC_CTRL_RXFCDMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CTRL */
+#define _FRC_CTRL_RXFCDMODE_FCDMODE0 0x00000000UL /**< Mode FCDMODE0 for FRC_CTRL */
+#define _FRC_CTRL_RXFCDMODE_FCDMODE1 0x00000001UL /**< Mode FCDMODE1 for FRC_CTRL */
+#define _FRC_CTRL_RXFCDMODE_FCDMODE2 0x00000002UL /**< Mode FCDMODE2 for FRC_CTRL */
+#define _FRC_CTRL_RXFCDMODE_FCDMODE3 0x00000003UL /**< Mode FCDMODE3 for FRC_CTRL */
+#define FRC_CTRL_RXFCDMODE_DEFAULT (_FRC_CTRL_RXFCDMODE_DEFAULT << 6) /**< Shifted mode DEFAULT for FRC_CTRL */
+#define FRC_CTRL_RXFCDMODE_FCDMODE0 (_FRC_CTRL_RXFCDMODE_FCDMODE0 << 6) /**< Shifted mode FCDMODE0 for FRC_CTRL */
+#define FRC_CTRL_RXFCDMODE_FCDMODE1 (_FRC_CTRL_RXFCDMODE_FCDMODE1 << 6) /**< Shifted mode FCDMODE1 for FRC_CTRL */
+#define FRC_CTRL_RXFCDMODE_FCDMODE2 (_FRC_CTRL_RXFCDMODE_FCDMODE2 << 6) /**< Shifted mode FCDMODE2 for FRC_CTRL */
+#define FRC_CTRL_RXFCDMODE_FCDMODE3 (_FRC_CTRL_RXFCDMODE_FCDMODE3 << 6) /**< Shifted mode FCDMODE3 for FRC_CTRL */
+#define _FRC_CTRL_BITSPERWORD_SHIFT 8 /**< Shift value for FRC_BITSPERWORD */
+#define _FRC_CTRL_BITSPERWORD_MASK 0x700UL /**< Bit mask for FRC_BITSPERWORD */
+#define _FRC_CTRL_BITSPERWORD_DEFAULT 0x00000007UL /**< Mode DEFAULT for FRC_CTRL */
+#define FRC_CTRL_BITSPERWORD_DEFAULT (_FRC_CTRL_BITSPERWORD_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_CTRL */
+#define _FRC_CTRL_RATESELECT_SHIFT 11 /**< Shift value for FRC_RATESELECT */
+#define _FRC_CTRL_RATESELECT_MASK 0x1800UL /**< Bit mask for FRC_RATESELECT */
+#define _FRC_CTRL_RATESELECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CTRL */
+#define FRC_CTRL_RATESELECT_DEFAULT (_FRC_CTRL_RATESELECT_DEFAULT << 11) /**< Shifted mode DEFAULT for FRC_CTRL */
+#define FRC_CTRL_TXPREFETCH (0x1UL << 13) /**< Transmit prefetch data */
+#define _FRC_CTRL_TXPREFETCH_SHIFT 13 /**< Shift value for FRC_TXPREFETCH */
+#define _FRC_CTRL_TXPREFETCH_MASK 0x2000UL /**< Bit mask for FRC_TXPREFETCH */
+#define _FRC_CTRL_TXPREFETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CTRL */
+#define _FRC_CTRL_TXPREFETCH_X0 0x00000000UL /**< Mode X0 for FRC_CTRL */
+#define _FRC_CTRL_TXPREFETCH_X1 0x00000001UL /**< Mode X1 for FRC_CTRL */
+#define FRC_CTRL_TXPREFETCH_DEFAULT (_FRC_CTRL_TXPREFETCH_DEFAULT << 13) /**< Shifted mode DEFAULT for FRC_CTRL */
+#define FRC_CTRL_TXPREFETCH_X0 (_FRC_CTRL_TXPREFETCH_X0 << 13) /**< Shifted mode X0 for FRC_CTRL */
+#define FRC_CTRL_TXPREFETCH_X1 (_FRC_CTRL_TXPREFETCH_X1 << 13) /**< Shifted mode X1 for FRC_CTRL */
+#define FRC_CTRL_TXFETCHBLOCKING (0x1UL << 14) /**< Transmit fetch data blocking */
+#define _FRC_CTRL_TXFETCHBLOCKING_SHIFT 14 /**< Shift value for FRC_TXFETCHBLOCKING */
+#define _FRC_CTRL_TXFETCHBLOCKING_MASK 0x4000UL /**< Bit mask for FRC_TXFETCHBLOCKING */
+#define _FRC_CTRL_TXFETCHBLOCKING_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CTRL */
+#define FRC_CTRL_TXFETCHBLOCKING_DEFAULT (_FRC_CTRL_TXFETCHBLOCKING_DEFAULT << 14) /**< Shifted mode DEFAULT for FRC_CTRL */
+#define FRC_CTRL_SEQHANDSHAKE (0x1UL << 16) /**< Sequencer data handshake */
+#define _FRC_CTRL_SEQHANDSHAKE_SHIFT 16 /**< Shift value for FRC_SEQHANDSHAKE */
+#define _FRC_CTRL_SEQHANDSHAKE_MASK 0x10000UL /**< Bit mask for FRC_SEQHANDSHAKE */
+#define _FRC_CTRL_SEQHANDSHAKE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CTRL */
+#define _FRC_CTRL_SEQHANDSHAKE_X0 0x00000000UL /**< Mode X0 for FRC_CTRL */
+#define _FRC_CTRL_SEQHANDSHAKE_X1 0x00000001UL /**< Mode X1 for FRC_CTRL */
+#define FRC_CTRL_SEQHANDSHAKE_DEFAULT (_FRC_CTRL_SEQHANDSHAKE_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_CTRL */
+#define FRC_CTRL_SEQHANDSHAKE_X0 (_FRC_CTRL_SEQHANDSHAKE_X0 << 16) /**< Shifted mode X0 for FRC_CTRL */
+#define FRC_CTRL_SEQHANDSHAKE_X1 (_FRC_CTRL_SEQHANDSHAKE_X1 << 16) /**< Shifted mode X1 for FRC_CTRL */
+#define FRC_CTRL_PRBSTEST (0x1UL << 17) /**< Pseudo-Random Bit Sequence Testmode */
+#define _FRC_CTRL_PRBSTEST_SHIFT 17 /**< Shift value for FRC_PRBSTEST */
+#define _FRC_CTRL_PRBSTEST_MASK 0x20000UL /**< Bit mask for FRC_PRBSTEST */
+#define _FRC_CTRL_PRBSTEST_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CTRL */
+#define FRC_CTRL_PRBSTEST_DEFAULT (_FRC_CTRL_PRBSTEST_DEFAULT << 17) /**< Shifted mode DEFAULT for FRC_CTRL */
+#define FRC_CTRL_LPMODEDIS (0x1UL << 18) /**< Disable FRC low power */
+#define _FRC_CTRL_LPMODEDIS_SHIFT 18 /**< Shift value for FRC_LPMODEDIS */
+#define _FRC_CTRL_LPMODEDIS_MASK 0x40000UL /**< Bit mask for FRC_LPMODEDIS */
+#define _FRC_CTRL_LPMODEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CTRL */
+#define FRC_CTRL_LPMODEDIS_DEFAULT (_FRC_CTRL_LPMODEDIS_DEFAULT << 18) /**< Shifted mode DEFAULT for FRC_CTRL */
+#define FRC_CTRL_WAITEOFEN (0x1UL << 19) /**< Enable STATE_TX_WAITEOF */
+#define _FRC_CTRL_WAITEOFEN_SHIFT 19 /**< Shift value for FRC_WAITEOFEN */
+#define _FRC_CTRL_WAITEOFEN_MASK 0x80000UL /**< Bit mask for FRC_WAITEOFEN */
+#define _FRC_CTRL_WAITEOFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CTRL */
+#define FRC_CTRL_WAITEOFEN_DEFAULT (_FRC_CTRL_WAITEOFEN_DEFAULT << 19) /**< Shifted mode DEFAULT for FRC_CTRL */
+#define FRC_CTRL_RXABORTIGNOREDIS (0x1UL << 20) /**< Disable ignoring CMD_RXABORT */
+#define _FRC_CTRL_RXABORTIGNOREDIS_SHIFT 20 /**< Shift value for FRC_RXABORTIGNOREDIS */
+#define _FRC_CTRL_RXABORTIGNOREDIS_MASK 0x100000UL /**< Bit mask for FRC_RXABORTIGNOREDIS */
+#define _FRC_CTRL_RXABORTIGNOREDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CTRL */
+#define FRC_CTRL_RXABORTIGNOREDIS_DEFAULT (_FRC_CTRL_RXABORTIGNOREDIS_DEFAULT << 20) /**< Shifted mode DEFAULT for FRC_CTRL */
+#define FRC_CTRL_SKIPTXTRAILDATAWHITEN (0x1UL << 24) /**< TX Trail Data Skip Whitening */
+#define _FRC_CTRL_SKIPTXTRAILDATAWHITEN_SHIFT 24 /**< Shift value for FRC_SKIPTXTRAILDATAWHITEN */
+#define _FRC_CTRL_SKIPTXTRAILDATAWHITEN_MASK 0x1000000UL /**< Bit mask for FRC_SKIPTXTRAILDATAWHITEN */
+#define _FRC_CTRL_SKIPTXTRAILDATAWHITEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for FRC_CTRL */
+#define FRC_CTRL_SKIPTXTRAILDATAWHITEN_DEFAULT (_FRC_CTRL_SKIPTXTRAILDATAWHITEN_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_CTRL */
+#define FRC_CTRL_SKIPRXSUPSTATEWHITEN (0x1UL << 25) /**< RX Supplemental Data Skip Whitening */
+#define _FRC_CTRL_SKIPRXSUPSTATEWHITEN_SHIFT 25 /**< Shift value for FRC_SKIPRXSUPSTATEWHITEN */
+#define _FRC_CTRL_SKIPRXSUPSTATEWHITEN_MASK 0x2000000UL /**< Bit mask for FRC_SKIPRXSUPSTATEWHITEN */
+#define _FRC_CTRL_SKIPRXSUPSTATEWHITEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for FRC_CTRL */
+#define FRC_CTRL_SKIPRXSUPSTATEWHITEN_DEFAULT (_FRC_CTRL_SKIPRXSUPSTATEWHITEN_DEFAULT << 25) /**< Shifted mode DEFAULT for FRC_CTRL */
+#define FRC_CTRL_HOLDTXTRAILDATAACTIVE (0x1UL << 26) /**< Defeat bit to hold txtraildata active */
+#define _FRC_CTRL_HOLDTXTRAILDATAACTIVE_SHIFT 26 /**< Shift value for FRC_HOLDTXTRAILDATAACTIVE */
+#define _FRC_CTRL_HOLDTXTRAILDATAACTIVE_MASK 0x4000000UL /**< Bit mask for FRC_HOLDTXTRAILDATAACTIVE */
+#define _FRC_CTRL_HOLDTXTRAILDATAACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CTRL */
+#define FRC_CTRL_HOLDTXTRAILDATAACTIVE_DEFAULT (_FRC_CTRL_HOLDTXTRAILDATAACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for FRC_CTRL */
+
+/* Bit fields for FRC RXCTRL */
+#define _FRC_RXCTRL_RESETVALUE 0x00000000UL /**< Default value for FRC_RXCTRL */
+#define _FRC_RXCTRL_MASK 0x00000FFFUL /**< Mask for FRC_RXCTRL */
+#define FRC_RXCTRL_STORECRC (0x1UL << 0) /**< Store CRC value. */
+#define _FRC_RXCTRL_STORECRC_SHIFT 0 /**< Shift value for FRC_STORECRC */
+#define _FRC_RXCTRL_STORECRC_MASK 0x1UL /**< Bit mask for FRC_STORECRC */
+#define _FRC_RXCTRL_STORECRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_RXCTRL */
+#define FRC_RXCTRL_STORECRC_DEFAULT (_FRC_RXCTRL_STORECRC_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_RXCTRL */
+#define FRC_RXCTRL_ACCEPTCRCERRORS (0x1UL << 1) /**< Accept CRC Errors. */
+#define _FRC_RXCTRL_ACCEPTCRCERRORS_SHIFT 1 /**< Shift value for FRC_ACCEPTCRCERRORS */
+#define _FRC_RXCTRL_ACCEPTCRCERRORS_MASK 0x2UL /**< Bit mask for FRC_ACCEPTCRCERRORS */
+#define _FRC_RXCTRL_ACCEPTCRCERRORS_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_RXCTRL */
+#define _FRC_RXCTRL_ACCEPTCRCERRORS_REJECT 0x00000000UL /**< Mode REJECT for FRC_RXCTRL */
+#define _FRC_RXCTRL_ACCEPTCRCERRORS_ACCEPT 0x00000001UL /**< Mode ACCEPT for FRC_RXCTRL */
+#define FRC_RXCTRL_ACCEPTCRCERRORS_DEFAULT (_FRC_RXCTRL_ACCEPTCRCERRORS_DEFAULT << 1) /**< Shifted mode DEFAULT for FRC_RXCTRL */
+#define FRC_RXCTRL_ACCEPTCRCERRORS_REJECT (_FRC_RXCTRL_ACCEPTCRCERRORS_REJECT << 1) /**< Shifted mode REJECT for FRC_RXCTRL */
+#define FRC_RXCTRL_ACCEPTCRCERRORS_ACCEPT (_FRC_RXCTRL_ACCEPTCRCERRORS_ACCEPT << 1) /**< Shifted mode ACCEPT for FRC_RXCTRL */
+#define FRC_RXCTRL_ACCEPTBLOCKERRORS (0x1UL << 2) /**< Accept Block Decoding Errors. */
+#define _FRC_RXCTRL_ACCEPTBLOCKERRORS_SHIFT 2 /**< Shift value for FRC_ACCEPTBLOCKERRORS */
+#define _FRC_RXCTRL_ACCEPTBLOCKERRORS_MASK 0x4UL /**< Bit mask for FRC_ACCEPTBLOCKERRORS */
+#define _FRC_RXCTRL_ACCEPTBLOCKERRORS_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_RXCTRL */
+#define _FRC_RXCTRL_ACCEPTBLOCKERRORS_REJECT 0x00000000UL /**< Mode REJECT for FRC_RXCTRL */
+#define _FRC_RXCTRL_ACCEPTBLOCKERRORS_ACCEPT 0x00000001UL /**< Mode ACCEPT for FRC_RXCTRL */
+#define FRC_RXCTRL_ACCEPTBLOCKERRORS_DEFAULT (_FRC_RXCTRL_ACCEPTBLOCKERRORS_DEFAULT << 2) /**< Shifted mode DEFAULT for FRC_RXCTRL */
+#define FRC_RXCTRL_ACCEPTBLOCKERRORS_REJECT (_FRC_RXCTRL_ACCEPTBLOCKERRORS_REJECT << 2) /**< Shifted mode REJECT for FRC_RXCTRL */
+#define FRC_RXCTRL_ACCEPTBLOCKERRORS_ACCEPT (_FRC_RXCTRL_ACCEPTBLOCKERRORS_ACCEPT << 2) /**< Shifted mode ACCEPT for FRC_RXCTRL */
+#define FRC_RXCTRL_TRACKABFRAME (0x1UL << 3) /**< Track Aborted RX Frame */
+#define _FRC_RXCTRL_TRACKABFRAME_SHIFT 3 /**< Shift value for FRC_TRACKABFRAME */
+#define _FRC_RXCTRL_TRACKABFRAME_MASK 0x8UL /**< Bit mask for FRC_TRACKABFRAME */
+#define _FRC_RXCTRL_TRACKABFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_RXCTRL */
+#define _FRC_RXCTRL_TRACKABFRAME_X0 0x00000000UL /**< Mode X0 for FRC_RXCTRL */
+#define _FRC_RXCTRL_TRACKABFRAME_X1 0x00000001UL /**< Mode X1 for FRC_RXCTRL */
+#define FRC_RXCTRL_TRACKABFRAME_DEFAULT (_FRC_RXCTRL_TRACKABFRAME_DEFAULT << 3) /**< Shifted mode DEFAULT for FRC_RXCTRL */
+#define FRC_RXCTRL_TRACKABFRAME_X0 (_FRC_RXCTRL_TRACKABFRAME_X0 << 3) /**< Shifted mode X0 for FRC_RXCTRL */
+#define FRC_RXCTRL_TRACKABFRAME_X1 (_FRC_RXCTRL_TRACKABFRAME_X1 << 3) /**< Shifted mode X1 for FRC_RXCTRL */
+#define FRC_RXCTRL_BUFCLEAR (0x1UL << 4) /**< Buffer Clear */
+#define _FRC_RXCTRL_BUFCLEAR_SHIFT 4 /**< Shift value for FRC_BUFCLEAR */
+#define _FRC_RXCTRL_BUFCLEAR_MASK 0x10UL /**< Bit mask for FRC_BUFCLEAR */
+#define _FRC_RXCTRL_BUFCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_RXCTRL */
+#define FRC_RXCTRL_BUFCLEAR_DEFAULT (_FRC_RXCTRL_BUFCLEAR_DEFAULT << 4) /**< Shifted mode DEFAULT for FRC_RXCTRL */
+#define FRC_RXCTRL_BUFRESTOREFRAMEERROR (0x1UL << 5) /**< Buffer restore on frame error */
+#define _FRC_RXCTRL_BUFRESTOREFRAMEERROR_SHIFT 5 /**< Shift value for FRC_BUFRESTOREFRAMEERROR */
+#define _FRC_RXCTRL_BUFRESTOREFRAMEERROR_MASK 0x20UL /**< Bit mask for FRC_BUFRESTOREFRAMEERROR */
+#define _FRC_RXCTRL_BUFRESTOREFRAMEERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_RXCTRL */
+#define FRC_RXCTRL_BUFRESTOREFRAMEERROR_DEFAULT (_FRC_RXCTRL_BUFRESTOREFRAMEERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for FRC_RXCTRL */
+#define FRC_RXCTRL_BUFRESTORERXABORTED (0x1UL << 6) /**< Buffer restore on RXABORTED */
+#define _FRC_RXCTRL_BUFRESTORERXABORTED_SHIFT 6 /**< Shift value for FRC_BUFRESTORERXABORTED */
+#define _FRC_RXCTRL_BUFRESTORERXABORTED_MASK 0x40UL /**< Bit mask for FRC_BUFRESTORERXABORTED */
+#define _FRC_RXCTRL_BUFRESTORERXABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_RXCTRL */
+#define FRC_RXCTRL_BUFRESTORERXABORTED_DEFAULT (_FRC_RXCTRL_BUFRESTORERXABORTED_DEFAULT << 6) /**< Shifted mode DEFAULT for FRC_RXCTRL */
+#define _FRC_RXCTRL_RXFRAMEENDAHEADBYTES_SHIFT 7 /**< Shift value for FRC_RXFRAMEENDAHEADBYTES */
+#define _FRC_RXCTRL_RXFRAMEENDAHEADBYTES_MASK 0x780UL /**< Bit mask for FRC_RXFRAMEENDAHEADBYTES */
+#define _FRC_RXCTRL_RXFRAMEENDAHEADBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_RXCTRL */
+#define FRC_RXCTRL_RXFRAMEENDAHEADBYTES_DEFAULT (_FRC_RXCTRL_RXFRAMEENDAHEADBYTES_DEFAULT << 7) /**< Shifted mode DEFAULT for FRC_RXCTRL */
+#define FRC_RXCTRL_ACCEPTUARTERRORS (0x1UL << 11) /**< Accept UART Start/Stop bit Errors. */
+#define _FRC_RXCTRL_ACCEPTUARTERRORS_SHIFT 11 /**< Shift value for FRC_ACCEPTUARTERRORS */
+#define _FRC_RXCTRL_ACCEPTUARTERRORS_MASK 0x800UL /**< Bit mask for FRC_ACCEPTUARTERRORS */
+#define _FRC_RXCTRL_ACCEPTUARTERRORS_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_RXCTRL */
+#define FRC_RXCTRL_ACCEPTUARTERRORS_DEFAULT (_FRC_RXCTRL_ACCEPTUARTERRORS_DEFAULT << 11) /**< Shifted mode DEFAULT for FRC_RXCTRL */
+
+/* Bit fields for FRC TRAILTXDATACTRL */
+#define _FRC_TRAILTXDATACTRL_RESETVALUE 0x00000000UL /**< Default value for FRC_TRAILTXDATACTRL */
+#define _FRC_TRAILTXDATACTRL_MASK 0x00FFFFFFUL /**< Mask for FRC_TRAILTXDATACTRL */
+#define _FRC_TRAILTXDATACTRL_TRAILTXDATA_SHIFT 0 /**< Shift value for FRC_TRAILTXDATA */
+#define _FRC_TRAILTXDATACTRL_TRAILTXDATA_MASK 0xFFUL /**< Bit mask for FRC_TRAILTXDATA */
+#define _FRC_TRAILTXDATACTRL_TRAILTXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_TRAILTXDATACTRL */
+#define FRC_TRAILTXDATACTRL_TRAILTXDATA_DEFAULT (_FRC_TRAILTXDATACTRL_TRAILTXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_TRAILTXDATACTRL*/
+#define _FRC_TRAILTXDATACTRL_TRAILTXDATACNT_SHIFT 8 /**< Shift value for FRC_TRAILTXDATACNT */
+#define _FRC_TRAILTXDATACTRL_TRAILTXDATACNT_MASK 0x700UL /**< Bit mask for FRC_TRAILTXDATACNT */
+#define _FRC_TRAILTXDATACTRL_TRAILTXDATACNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_TRAILTXDATACTRL */
+#define FRC_TRAILTXDATACTRL_TRAILTXDATACNT_DEFAULT (_FRC_TRAILTXDATACTRL_TRAILTXDATACNT_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_TRAILTXDATACTRL*/
+#define FRC_TRAILTXDATACTRL_TRAILTXDATAFORCE (0x1UL << 11) /**< Force trailing TX data insertion */
+#define _FRC_TRAILTXDATACTRL_TRAILTXDATAFORCE_SHIFT 11 /**< Shift value for FRC_TRAILTXDATAFORCE */
+#define _FRC_TRAILTXDATACTRL_TRAILTXDATAFORCE_MASK 0x800UL /**< Bit mask for FRC_TRAILTXDATAFORCE */
+#define _FRC_TRAILTXDATACTRL_TRAILTXDATAFORCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_TRAILTXDATACTRL */
+#define _FRC_TRAILTXDATACTRL_TRAILTXDATAFORCE_X0 0x00000000UL /**< Mode X0 for FRC_TRAILTXDATACTRL */
+#define _FRC_TRAILTXDATACTRL_TRAILTXDATAFORCE_X1 0x00000001UL /**< Mode X1 for FRC_TRAILTXDATACTRL */
+#define FRC_TRAILTXDATACTRL_TRAILTXDATAFORCE_DEFAULT (_FRC_TRAILTXDATACTRL_TRAILTXDATAFORCE_DEFAULT << 11) /**< Shifted mode DEFAULT for FRC_TRAILTXDATACTRL*/
+#define FRC_TRAILTXDATACTRL_TRAILTXDATAFORCE_X0 (_FRC_TRAILTXDATACTRL_TRAILTXDATAFORCE_X0 << 11) /**< Shifted mode X0 for FRC_TRAILTXDATACTRL */
+#define FRC_TRAILTXDATACTRL_TRAILTXDATAFORCE_X1 (_FRC_TRAILTXDATACTRL_TRAILTXDATAFORCE_X1 << 11) /**< Shifted mode X1 for FRC_TRAILTXDATACTRL */
+#define _FRC_TRAILTXDATACTRL_TRAILTXREPLEN_SHIFT 12 /**< Shift value for FRC_TRAILTXREPLEN */
+#define _FRC_TRAILTXDATACTRL_TRAILTXREPLEN_MASK 0x3FF000UL /**< Bit mask for FRC_TRAILTXREPLEN */
+#define _FRC_TRAILTXDATACTRL_TRAILTXREPLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_TRAILTXDATACTRL */
+#define FRC_TRAILTXDATACTRL_TRAILTXREPLEN_DEFAULT (_FRC_TRAILTXDATACTRL_TRAILTXREPLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for FRC_TRAILTXDATACTRL*/
+#define FRC_TRAILTXDATACTRL_TXSUPPLENOVERIDE (0x1UL << 22) /**< TX Sup Len Override */
+#define _FRC_TRAILTXDATACTRL_TXSUPPLENOVERIDE_SHIFT 22 /**< Shift value for FRC_TXSUPPLENOVERIDE */
+#define _FRC_TRAILTXDATACTRL_TXSUPPLENOVERIDE_MASK 0x400000UL /**< Bit mask for FRC_TXSUPPLENOVERIDE */
+#define _FRC_TRAILTXDATACTRL_TXSUPPLENOVERIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_TRAILTXDATACTRL */
+#define FRC_TRAILTXDATACTRL_TXSUPPLENOVERIDE_DEFAULT (_FRC_TRAILTXDATACTRL_TXSUPPLENOVERIDE_DEFAULT << 22) /**< Shifted mode DEFAULT for FRC_TRAILTXDATACTRL*/
+#define FRC_TRAILTXDATACTRL_POSTAMBLEEN (0x1UL << 23) /**< WMBUS T mode postamble enable */
+#define _FRC_TRAILTXDATACTRL_POSTAMBLEEN_SHIFT 23 /**< Shift value for FRC_POSTAMBLEEN */
+#define _FRC_TRAILTXDATACTRL_POSTAMBLEEN_MASK 0x800000UL /**< Bit mask for FRC_POSTAMBLEEN */
+#define _FRC_TRAILTXDATACTRL_POSTAMBLEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_TRAILTXDATACTRL */
+#define FRC_TRAILTXDATACTRL_POSTAMBLEEN_DEFAULT (_FRC_TRAILTXDATACTRL_POSTAMBLEEN_DEFAULT << 23) /**< Shifted mode DEFAULT for FRC_TRAILTXDATACTRL*/
+
+/* Bit fields for FRC TRAILRXDATA */
+#define _FRC_TRAILRXDATA_RESETVALUE 0x00000000UL /**< Default value for FRC_TRAILRXDATA */
+#define _FRC_TRAILRXDATA_MASK 0x0000003FUL /**< Mask for FRC_TRAILRXDATA */
+#define FRC_TRAILRXDATA_RSSI (0x1UL << 0) /**< Append RSSI */
+#define _FRC_TRAILRXDATA_RSSI_SHIFT 0 /**< Shift value for FRC_RSSI */
+#define _FRC_TRAILRXDATA_RSSI_MASK 0x1UL /**< Bit mask for FRC_RSSI */
+#define _FRC_TRAILRXDATA_RSSI_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_TRAILRXDATA */
+#define FRC_TRAILRXDATA_RSSI_DEFAULT (_FRC_TRAILRXDATA_RSSI_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_TRAILRXDATA */
+#define FRC_TRAILRXDATA_CRCOK (0x1UL << 1) /**< Append CRC OK Indicator */
+#define _FRC_TRAILRXDATA_CRCOK_SHIFT 1 /**< Shift value for FRC_CRCOK */
+#define _FRC_TRAILRXDATA_CRCOK_MASK 0x2UL /**< Bit mask for FRC_CRCOK */
+#define _FRC_TRAILRXDATA_CRCOK_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_TRAILRXDATA */
+#define FRC_TRAILRXDATA_CRCOK_DEFAULT (_FRC_TRAILRXDATA_CRCOK_DEFAULT << 1) /**< Shifted mode DEFAULT for FRC_TRAILRXDATA */
+#define FRC_TRAILRXDATA_PROTIMERCC0BASE (0x1UL << 2) /**< PROTIMER Capture Compare channel 0 Base */
+#define _FRC_TRAILRXDATA_PROTIMERCC0BASE_SHIFT 2 /**< Shift value for FRC_PROTIMERCC0BASE */
+#define _FRC_TRAILRXDATA_PROTIMERCC0BASE_MASK 0x4UL /**< Bit mask for FRC_PROTIMERCC0BASE */
+#define _FRC_TRAILRXDATA_PROTIMERCC0BASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_TRAILRXDATA */
+#define FRC_TRAILRXDATA_PROTIMERCC0BASE_DEFAULT (_FRC_TRAILRXDATA_PROTIMERCC0BASE_DEFAULT << 2) /**< Shifted mode DEFAULT for FRC_TRAILRXDATA */
+#define FRC_TRAILRXDATA_PROTIMERCC0WRAPL (0x1UL << 3) /**< PROTIMER Capture Compare channel 0 WrapL */
+#define _FRC_TRAILRXDATA_PROTIMERCC0WRAPL_SHIFT 3 /**< Shift value for FRC_PROTIMERCC0WRAPL */
+#define _FRC_TRAILRXDATA_PROTIMERCC0WRAPL_MASK 0x8UL /**< Bit mask for FRC_PROTIMERCC0WRAPL */
+#define _FRC_TRAILRXDATA_PROTIMERCC0WRAPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_TRAILRXDATA */
+#define FRC_TRAILRXDATA_PROTIMERCC0WRAPL_DEFAULT (_FRC_TRAILRXDATA_PROTIMERCC0WRAPL_DEFAULT << 3) /**< Shifted mode DEFAULT for FRC_TRAILRXDATA */
+#define FRC_TRAILRXDATA_PROTIMERCC0WRAPH (0x1UL << 4) /**< PROTIMER Capture Compare channel 0 WrapH */
+#define _FRC_TRAILRXDATA_PROTIMERCC0WRAPH_SHIFT 4 /**< Shift value for FRC_PROTIMERCC0WRAPH */
+#define _FRC_TRAILRXDATA_PROTIMERCC0WRAPH_MASK 0x10UL /**< Bit mask for FRC_PROTIMERCC0WRAPH */
+#define _FRC_TRAILRXDATA_PROTIMERCC0WRAPH_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_TRAILRXDATA */
+#define FRC_TRAILRXDATA_PROTIMERCC0WRAPH_DEFAULT (_FRC_TRAILRXDATA_PROTIMERCC0WRAPH_DEFAULT << 4) /**< Shifted mode DEFAULT for FRC_TRAILRXDATA */
+#define FRC_TRAILRXDATA_RTCSTAMP (0x1UL << 5) /**< RTCC Time Stamp */
+#define _FRC_TRAILRXDATA_RTCSTAMP_SHIFT 5 /**< Shift value for FRC_RTCSTAMP */
+#define _FRC_TRAILRXDATA_RTCSTAMP_MASK 0x20UL /**< Bit mask for FRC_RTCSTAMP */
+#define _FRC_TRAILRXDATA_RTCSTAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_TRAILRXDATA */
+#define FRC_TRAILRXDATA_RTCSTAMP_DEFAULT (_FRC_TRAILRXDATA_RTCSTAMP_DEFAULT << 5) /**< Shifted mode DEFAULT for FRC_TRAILRXDATA */
+
+/* Bit fields for FRC SCNT */
+#define _FRC_SCNT_RESETVALUE 0x00000000UL /**< Default value for FRC_SCNT */
+#define _FRC_SCNT_MASK 0x000000FFUL /**< Mask for FRC_SCNT */
+#define _FRC_SCNT_SCNT_SHIFT 0 /**< Shift value for FRC_SCNT */
+#define _FRC_SCNT_SCNT_MASK 0xFFUL /**< Bit mask for FRC_SCNT */
+#define _FRC_SCNT_SCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SCNT */
+#define FRC_SCNT_SCNT_DEFAULT (_FRC_SCNT_SCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_SCNT */
+
+/* Bit fields for FRC CONVGENERATOR */
+#define _FRC_CONVGENERATOR_RESETVALUE 0x00000000UL /**< Default value for FRC_CONVGENERATOR */
+#define _FRC_CONVGENERATOR_MASK 0x00037F7FUL /**< Mask for FRC_CONVGENERATOR */
+#define _FRC_CONVGENERATOR_GENERATOR0_SHIFT 0 /**< Shift value for FRC_GENERATOR0 */
+#define _FRC_CONVGENERATOR_GENERATOR0_MASK 0x7FUL /**< Bit mask for FRC_GENERATOR0 */
+#define _FRC_CONVGENERATOR_GENERATOR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CONVGENERATOR */
+#define FRC_CONVGENERATOR_GENERATOR0_DEFAULT (_FRC_CONVGENERATOR_GENERATOR0_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_CONVGENERATOR */
+#define _FRC_CONVGENERATOR_GENERATOR1_SHIFT 8 /**< Shift value for FRC_GENERATOR1 */
+#define _FRC_CONVGENERATOR_GENERATOR1_MASK 0x7F00UL /**< Bit mask for FRC_GENERATOR1 */
+#define _FRC_CONVGENERATOR_GENERATOR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CONVGENERATOR */
+#define FRC_CONVGENERATOR_GENERATOR1_DEFAULT (_FRC_CONVGENERATOR_GENERATOR1_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_CONVGENERATOR */
+#define FRC_CONVGENERATOR_RECURSIVE (0x1UL << 16) /**< Convolutional encoding */
+#define _FRC_CONVGENERATOR_RECURSIVE_SHIFT 16 /**< Shift value for FRC_RECURSIVE */
+#define _FRC_CONVGENERATOR_RECURSIVE_MASK 0x10000UL /**< Bit mask for FRC_RECURSIVE */
+#define _FRC_CONVGENERATOR_RECURSIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CONVGENERATOR */
+#define _FRC_CONVGENERATOR_RECURSIVE_X0 0x00000000UL /**< Mode X0 for FRC_CONVGENERATOR */
+#define _FRC_CONVGENERATOR_RECURSIVE_X1 0x00000001UL /**< Mode X1 for FRC_CONVGENERATOR */
+#define FRC_CONVGENERATOR_RECURSIVE_DEFAULT (_FRC_CONVGENERATOR_RECURSIVE_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_CONVGENERATOR */
+#define FRC_CONVGENERATOR_RECURSIVE_X0 (_FRC_CONVGENERATOR_RECURSIVE_X0 << 16) /**< Shifted mode X0 for FRC_CONVGENERATOR */
+#define FRC_CONVGENERATOR_RECURSIVE_X1 (_FRC_CONVGENERATOR_RECURSIVE_X1 << 16) /**< Shifted mode X1 for FRC_CONVGENERATOR */
+#define FRC_CONVGENERATOR_NONSYSTEMATIC (0x1UL << 17) /**< Non systematic recursive code */
+#define _FRC_CONVGENERATOR_NONSYSTEMATIC_SHIFT 17 /**< Shift value for FRC_NONSYSTEMATIC */
+#define _FRC_CONVGENERATOR_NONSYSTEMATIC_MASK 0x20000UL /**< Bit mask for FRC_NONSYSTEMATIC */
+#define _FRC_CONVGENERATOR_NONSYSTEMATIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CONVGENERATOR */
+#define _FRC_CONVGENERATOR_NONSYSTEMATIC_X0 0x00000000UL /**< Mode X0 for FRC_CONVGENERATOR */
+#define _FRC_CONVGENERATOR_NONSYSTEMATIC_X1 0x00000001UL /**< Mode X1 for FRC_CONVGENERATOR */
+#define FRC_CONVGENERATOR_NONSYSTEMATIC_DEFAULT (_FRC_CONVGENERATOR_NONSYSTEMATIC_DEFAULT << 17) /**< Shifted mode DEFAULT for FRC_CONVGENERATOR */
+#define FRC_CONVGENERATOR_NONSYSTEMATIC_X0 (_FRC_CONVGENERATOR_NONSYSTEMATIC_X0 << 17) /**< Shifted mode X0 for FRC_CONVGENERATOR */
+#define FRC_CONVGENERATOR_NONSYSTEMATIC_X1 (_FRC_CONVGENERATOR_NONSYSTEMATIC_X1 << 17) /**< Shifted mode X1 for FRC_CONVGENERATOR */
+
+/* Bit fields for FRC PUNCTCTRL */
+#define _FRC_PUNCTCTRL_RESETVALUE 0x00000101UL /**< Default value for FRC_PUNCTCTRL */
+#define _FRC_PUNCTCTRL_MASK 0x00007F7FUL /**< Mask for FRC_PUNCTCTRL */
+#define _FRC_PUNCTCTRL_PUNCT0_SHIFT 0 /**< Shift value for FRC_PUNCT0 */
+#define _FRC_PUNCTCTRL_PUNCT0_MASK 0x7FUL /**< Bit mask for FRC_PUNCT0 */
+#define _FRC_PUNCTCTRL_PUNCT0_DEFAULT 0x00000001UL /**< Mode DEFAULT for FRC_PUNCTCTRL */
+#define FRC_PUNCTCTRL_PUNCT0_DEFAULT (_FRC_PUNCTCTRL_PUNCT0_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PUNCTCTRL */
+#define _FRC_PUNCTCTRL_PUNCT1_SHIFT 8 /**< Shift value for FRC_PUNCT1 */
+#define _FRC_PUNCTCTRL_PUNCT1_MASK 0x7F00UL /**< Bit mask for FRC_PUNCT1 */
+#define _FRC_PUNCTCTRL_PUNCT1_DEFAULT 0x00000001UL /**< Mode DEFAULT for FRC_PUNCTCTRL */
+#define FRC_PUNCTCTRL_PUNCT1_DEFAULT (_FRC_PUNCTCTRL_PUNCT1_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_PUNCTCTRL */
+
+/* Bit fields for FRC PAUSECTRL */
+#define _FRC_PAUSECTRL_RESETVALUE 0x00000000UL /**< Default value for FRC_PAUSECTRL */
+#define _FRC_PAUSECTRL_MASK 0x07FFF83FUL /**< Mask for FRC_PAUSECTRL */
+#define FRC_PAUSECTRL_FRAMEDETPAUSEEN (0x1UL << 0) /**< Frame detect pause enable */
+#define _FRC_PAUSECTRL_FRAMEDETPAUSEEN_SHIFT 0 /**< Shift value for FRC_FRAMEDETPAUSEEN */
+#define _FRC_PAUSECTRL_FRAMEDETPAUSEEN_MASK 0x1UL /**< Bit mask for FRC_FRAMEDETPAUSEEN */
+#define _FRC_PAUSECTRL_FRAMEDETPAUSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PAUSECTRL */
+#define FRC_PAUSECTRL_FRAMEDETPAUSEEN_DEFAULT (_FRC_PAUSECTRL_FRAMEDETPAUSEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PAUSECTRL */
+#define FRC_PAUSECTRL_TXINTERLEAVEWRITEPAUSEEN (0x1UL << 1) /**< Transmit interleaver write pause enable */
+#define _FRC_PAUSECTRL_TXINTERLEAVEWRITEPAUSEEN_SHIFT 1 /**< Shift value for FRC_TXINTERLEAVEWRITEPAUSEEN*/
+#define _FRC_PAUSECTRL_TXINTERLEAVEWRITEPAUSEEN_MASK 0x2UL /**< Bit mask for FRC_TXINTERLEAVEWRITEPAUSEEN */
+#define _FRC_PAUSECTRL_TXINTERLEAVEWRITEPAUSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PAUSECTRL */
+#define FRC_PAUSECTRL_TXINTERLEAVEWRITEPAUSEEN_DEFAULT (_FRC_PAUSECTRL_TXINTERLEAVEWRITEPAUSEEN_DEFAULT << 1) /**< Shifted mode DEFAULT for FRC_PAUSECTRL */
+#define FRC_PAUSECTRL_RXINTERLEAVEWRITEPAUSEEN (0x1UL << 2) /**< Receive interleaver write pause enable */
+#define _FRC_PAUSECTRL_RXINTERLEAVEWRITEPAUSEEN_SHIFT 2 /**< Shift value for FRC_RXINTERLEAVEWRITEPAUSEEN*/
+#define _FRC_PAUSECTRL_RXINTERLEAVEWRITEPAUSEEN_MASK 0x4UL /**< Bit mask for FRC_RXINTERLEAVEWRITEPAUSEEN */
+#define _FRC_PAUSECTRL_RXINTERLEAVEWRITEPAUSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PAUSECTRL */
+#define FRC_PAUSECTRL_RXINTERLEAVEWRITEPAUSEEN_DEFAULT (_FRC_PAUSECTRL_RXINTERLEAVEWRITEPAUSEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for FRC_PAUSECTRL */
+#define FRC_PAUSECTRL_INTERLEAVEREADPAUSEEN (0x1UL << 3) /**< Interleaver read pause enable */
+#define _FRC_PAUSECTRL_INTERLEAVEREADPAUSEEN_SHIFT 3 /**< Shift value for FRC_INTERLEAVEREADPAUSEEN */
+#define _FRC_PAUSECTRL_INTERLEAVEREADPAUSEEN_MASK 0x8UL /**< Bit mask for FRC_INTERLEAVEREADPAUSEEN */
+#define _FRC_PAUSECTRL_INTERLEAVEREADPAUSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PAUSECTRL */
+#define FRC_PAUSECTRL_INTERLEAVEREADPAUSEEN_DEFAULT (_FRC_PAUSECTRL_INTERLEAVEREADPAUSEEN_DEFAULT << 3) /**< Shifted mode DEFAULT for FRC_PAUSECTRL */
+#define FRC_PAUSECTRL_TXSUBFRAMEPAUSEEN (0x1UL << 4) /**< Transmit subframe pause enable */
+#define _FRC_PAUSECTRL_TXSUBFRAMEPAUSEEN_SHIFT 4 /**< Shift value for FRC_TXSUBFRAMEPAUSEEN */
+#define _FRC_PAUSECTRL_TXSUBFRAMEPAUSEEN_MASK 0x10UL /**< Bit mask for FRC_TXSUBFRAMEPAUSEEN */
+#define _FRC_PAUSECTRL_TXSUBFRAMEPAUSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PAUSECTRL */
+#define FRC_PAUSECTRL_TXSUBFRAMEPAUSEEN_DEFAULT (_FRC_PAUSECTRL_TXSUBFRAMEPAUSEEN_DEFAULT << 4) /**< Shifted mode DEFAULT for FRC_PAUSECTRL */
+#define FRC_PAUSECTRL_RXWCNTMATCHPAUSEEN (0x1UL << 5) /**< Receive wcnt match pause enable */
+#define _FRC_PAUSECTRL_RXWCNTMATCHPAUSEEN_SHIFT 5 /**< Shift value for FRC_RXWCNTMATCHPAUSEEN */
+#define _FRC_PAUSECTRL_RXWCNTMATCHPAUSEEN_MASK 0x20UL /**< Bit mask for FRC_RXWCNTMATCHPAUSEEN */
+#define _FRC_PAUSECTRL_RXWCNTMATCHPAUSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PAUSECTRL */
+#define FRC_PAUSECTRL_RXWCNTMATCHPAUSEEN_DEFAULT (_FRC_PAUSECTRL_RXWCNTMATCHPAUSEEN_DEFAULT << 5) /**< Shifted mode DEFAULT for FRC_PAUSECTRL */
+#define _FRC_PAUSECTRL_CONVPAUSECNT_SHIFT 11 /**< Shift value for FRC_CONVPAUSECNT */
+#define _FRC_PAUSECTRL_CONVPAUSECNT_MASK 0x1F800UL /**< Bit mask for FRC_CONVPAUSECNT */
+#define _FRC_PAUSECTRL_CONVPAUSECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PAUSECTRL */
+#define FRC_PAUSECTRL_CONVPAUSECNT_DEFAULT (_FRC_PAUSECTRL_CONVPAUSECNT_DEFAULT << 11) /**< Shifted mode DEFAULT for FRC_PAUSECTRL */
+#define _FRC_PAUSECTRL_INTERLEAVEWRITEPAUSECNT_SHIFT 17 /**< Shift value for FRC_INTERLEAVEWRITEPAUSECNT */
+#define _FRC_PAUSECTRL_INTERLEAVEWRITEPAUSECNT_MASK 0x3E0000UL /**< Bit mask for FRC_INTERLEAVEWRITEPAUSECNT */
+#define _FRC_PAUSECTRL_INTERLEAVEWRITEPAUSECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PAUSECTRL */
+#define FRC_PAUSECTRL_INTERLEAVEWRITEPAUSECNT_DEFAULT (_FRC_PAUSECTRL_INTERLEAVEWRITEPAUSECNT_DEFAULT << 17) /**< Shifted mode DEFAULT for FRC_PAUSECTRL */
+#define _FRC_PAUSECTRL_INTERLEAVEREADPAUSECNT_SHIFT 22 /**< Shift value for FRC_INTERLEAVEREADPAUSECNT */
+#define _FRC_PAUSECTRL_INTERLEAVEREADPAUSECNT_MASK 0x7C00000UL /**< Bit mask for FRC_INTERLEAVEREADPAUSECNT */
+#define _FRC_PAUSECTRL_INTERLEAVEREADPAUSECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PAUSECTRL */
+#define FRC_PAUSECTRL_INTERLEAVEREADPAUSECNT_DEFAULT (_FRC_PAUSECTRL_INTERLEAVEREADPAUSECNT_DEFAULT << 22) /**< Shifted mode DEFAULT for FRC_PAUSECTRL */
+
+/* Bit fields for FRC IF */
+#define _FRC_IF_RESETVALUE 0x00000000UL /**< Default value for FRC_IF */
+#define _FRC_IF_MASK 0xFFFFFFFFUL /**< Mask for FRC_IF */
+#define FRC_IF_TXDONE (0x1UL << 0) /**< TX Done Interrupt Flag */
+#define _FRC_IF_TXDONE_SHIFT 0 /**< Shift value for FRC_TXDONE */
+#define _FRC_IF_TXDONE_MASK 0x1UL /**< Bit mask for FRC_TXDONE */
+#define _FRC_IF_TXDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_TXDONE_DEFAULT (_FRC_IF_TXDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_IF */
+#define FRC_IF_TXAFTERFRAMEDONE (0x1UL << 1) /**< TX after frame Done Interrupt Flag */
+#define _FRC_IF_TXAFTERFRAMEDONE_SHIFT 1 /**< Shift value for FRC_TXAFTERFRAMEDONE */
+#define _FRC_IF_TXAFTERFRAMEDONE_MASK 0x2UL /**< Bit mask for FRC_TXAFTERFRAMEDONE */
+#define _FRC_IF_TXAFTERFRAMEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_TXAFTERFRAMEDONE_DEFAULT (_FRC_IF_TXAFTERFRAMEDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for FRC_IF */
+#define FRC_IF_TXABORTED (0x1UL << 2) /**< Transmit Aborted Interrupt Flag */
+#define _FRC_IF_TXABORTED_SHIFT 2 /**< Shift value for FRC_TXABORTED */
+#define _FRC_IF_TXABORTED_MASK 0x4UL /**< Bit mask for FRC_TXABORTED */
+#define _FRC_IF_TXABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_TXABORTED_DEFAULT (_FRC_IF_TXABORTED_DEFAULT << 2) /**< Shifted mode DEFAULT for FRC_IF */
+#define FRC_IF_TXUF (0x1UL << 3) /**< Transmit Underflow Interrupt Flag */
+#define _FRC_IF_TXUF_SHIFT 3 /**< Shift value for FRC_TXUF */
+#define _FRC_IF_TXUF_MASK 0x8UL /**< Bit mask for FRC_TXUF */
+#define _FRC_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_TXUF_DEFAULT (_FRC_IF_TXUF_DEFAULT << 3) /**< Shifted mode DEFAULT for FRC_IF */
+#define FRC_IF_RXDONE (0x1UL << 4) /**< RX Done Interrupt Flag */
+#define _FRC_IF_RXDONE_SHIFT 4 /**< Shift value for FRC_RXDONE */
+#define _FRC_IF_RXDONE_MASK 0x10UL /**< Bit mask for FRC_RXDONE */
+#define _FRC_IF_RXDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_RXDONE_DEFAULT (_FRC_IF_RXDONE_DEFAULT << 4) /**< Shifted mode DEFAULT for FRC_IF */
+#define FRC_IF_RXABORTED (0x1UL << 5) /**< RX Aborted Interrupt Flag */
+#define _FRC_IF_RXABORTED_SHIFT 5 /**< Shift value for FRC_RXABORTED */
+#define _FRC_IF_RXABORTED_MASK 0x20UL /**< Bit mask for FRC_RXABORTED */
+#define _FRC_IF_RXABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_RXABORTED_DEFAULT (_FRC_IF_RXABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for FRC_IF */
+#define FRC_IF_FRAMEERROR (0x1UL << 6) /**< Frame Error Interrupt Flag */
+#define _FRC_IF_FRAMEERROR_SHIFT 6 /**< Shift value for FRC_FRAMEERROR */
+#define _FRC_IF_FRAMEERROR_MASK 0x40UL /**< Bit mask for FRC_FRAMEERROR */
+#define _FRC_IF_FRAMEERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_FRAMEERROR_DEFAULT (_FRC_IF_FRAMEERROR_DEFAULT << 6) /**< Shifted mode DEFAULT for FRC_IF */
+#define FRC_IF_BLOCKERROR (0x1UL << 7) /**< Block Error Interrupt Flag */
+#define _FRC_IF_BLOCKERROR_SHIFT 7 /**< Shift value for FRC_BLOCKERROR */
+#define _FRC_IF_BLOCKERROR_MASK 0x80UL /**< Bit mask for FRC_BLOCKERROR */
+#define _FRC_IF_BLOCKERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_BLOCKERROR_DEFAULT (_FRC_IF_BLOCKERROR_DEFAULT << 7) /**< Shifted mode DEFAULT for FRC_IF */
+#define FRC_IF_RXOF (0x1UL << 8) /**< Receive Overflow Interrupt Flag */
+#define _FRC_IF_RXOF_SHIFT 8 /**< Shift value for FRC_RXOF */
+#define _FRC_IF_RXOF_MASK 0x100UL /**< Bit mask for FRC_RXOF */
+#define _FRC_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_RXOF_DEFAULT (_FRC_IF_RXOF_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_IF */
+#define FRC_IF_WCNTCMP0 (0x1UL << 9) /**< Word Counter Compare 0 Event */
+#define _FRC_IF_WCNTCMP0_SHIFT 9 /**< Shift value for FRC_WCNTCMP0 */
+#define _FRC_IF_WCNTCMP0_MASK 0x200UL /**< Bit mask for FRC_WCNTCMP0 */
+#define _FRC_IF_WCNTCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_WCNTCMP0_DEFAULT (_FRC_IF_WCNTCMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for FRC_IF */
+#define FRC_IF_WCNTCMP1 (0x1UL << 10) /**< Word Counter Compare 1 Event */
+#define _FRC_IF_WCNTCMP1_SHIFT 10 /**< Shift value for FRC_WCNTCMP1 */
+#define _FRC_IF_WCNTCMP1_MASK 0x400UL /**< Bit mask for FRC_WCNTCMP1 */
+#define _FRC_IF_WCNTCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_WCNTCMP1_DEFAULT (_FRC_IF_WCNTCMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for FRC_IF */
+#define FRC_IF_WCNTCMP2 (0x1UL << 11) /**< Word Counter Compare 2 Event */
+#define _FRC_IF_WCNTCMP2_SHIFT 11 /**< Shift value for FRC_WCNTCMP2 */
+#define _FRC_IF_WCNTCMP2_MASK 0x800UL /**< Bit mask for FRC_WCNTCMP2 */
+#define _FRC_IF_WCNTCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_WCNTCMP2_DEFAULT (_FRC_IF_WCNTCMP2_DEFAULT << 11) /**< Shifted mode DEFAULT for FRC_IF */
+#define FRC_IF_ADDRERROR (0x1UL << 12) /**< Receive address error event */
+#define _FRC_IF_ADDRERROR_SHIFT 12 /**< Shift value for FRC_ADDRERROR */
+#define _FRC_IF_ADDRERROR_MASK 0x1000UL /**< Bit mask for FRC_ADDRERROR */
+#define _FRC_IF_ADDRERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_ADDRERROR_DEFAULT (_FRC_IF_ADDRERROR_DEFAULT << 12) /**< Shifted mode DEFAULT for FRC_IF */
+#define FRC_IF_BUSERROR (0x1UL << 13) /**< A bus error event occurred */
+#define _FRC_IF_BUSERROR_SHIFT 13 /**< Shift value for FRC_BUSERROR */
+#define _FRC_IF_BUSERROR_MASK 0x2000UL /**< Bit mask for FRC_BUSERROR */
+#define _FRC_IF_BUSERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_BUSERROR_DEFAULT (_FRC_IF_BUSERROR_DEFAULT << 13) /**< Shifted mode DEFAULT for FRC_IF */
+#define FRC_IF_RXRAWEVENT (0x1UL << 14) /**< Receiver raw data event */
+#define _FRC_IF_RXRAWEVENT_SHIFT 14 /**< Shift value for FRC_RXRAWEVENT */
+#define _FRC_IF_RXRAWEVENT_MASK 0x4000UL /**< Bit mask for FRC_RXRAWEVENT */
+#define _FRC_IF_RXRAWEVENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_RXRAWEVENT_DEFAULT (_FRC_IF_RXRAWEVENT_DEFAULT << 14) /**< Shifted mode DEFAULT for FRC_IF */
+#define FRC_IF_TXRAWEVENT (0x1UL << 15) /**< Transmit raw data event */
+#define _FRC_IF_TXRAWEVENT_SHIFT 15 /**< Shift value for FRC_TXRAWEVENT */
+#define _FRC_IF_TXRAWEVENT_MASK 0x8000UL /**< Bit mask for FRC_TXRAWEVENT */
+#define _FRC_IF_TXRAWEVENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_TXRAWEVENT_DEFAULT (_FRC_IF_TXRAWEVENT_DEFAULT << 15) /**< Shifted mode DEFAULT for FRC_IF */
+#define FRC_IF_SNIFFOF (0x1UL << 16) /**< Data sniffer overflow */
+#define _FRC_IF_SNIFFOF_SHIFT 16 /**< Shift value for FRC_SNIFFOF */
+#define _FRC_IF_SNIFFOF_MASK 0x10000UL /**< Bit mask for FRC_SNIFFOF */
+#define _FRC_IF_SNIFFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_SNIFFOF_DEFAULT (_FRC_IF_SNIFFOF_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_IF */
+#define FRC_IF_WCNTCMP3 (0x1UL << 17) /**< Word Counter Compare 3 Event */
+#define _FRC_IF_WCNTCMP3_SHIFT 17 /**< Shift value for FRC_WCNTCMP3 */
+#define _FRC_IF_WCNTCMP3_MASK 0x20000UL /**< Bit mask for FRC_WCNTCMP3 */
+#define _FRC_IF_WCNTCMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_WCNTCMP3_DEFAULT (_FRC_IF_WCNTCMP3_DEFAULT << 17) /**< Shifted mode DEFAULT for FRC_IF */
+#define FRC_IF_WCNTCMP4 (0x1UL << 18) /**< Word Counter Compare 4 Event */
+#define _FRC_IF_WCNTCMP4_SHIFT 18 /**< Shift value for FRC_WCNTCMP4 */
+#define _FRC_IF_WCNTCMP4_MASK 0x40000UL /**< Bit mask for FRC_WCNTCMP4 */
+#define _FRC_IF_WCNTCMP4_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_WCNTCMP4_DEFAULT (_FRC_IF_WCNTCMP4_DEFAULT << 18) /**< Shifted mode DEFAULT for FRC_IF */
+#define FRC_IF_BOISET (0x1UL << 19) /**< BOI SET */
+#define _FRC_IF_BOISET_SHIFT 19 /**< Shift value for FRC_BOISET */
+#define _FRC_IF_BOISET_MASK 0x80000UL /**< Bit mask for FRC_BOISET */
+#define _FRC_IF_BOISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_BOISET_DEFAULT (_FRC_IF_BOISET_DEFAULT << 19) /**< Shifted mode DEFAULT for FRC_IF */
+#define FRC_IF_PKTBUFSTART (0x1UL << 20) /**< Packet Buffer Start */
+#define _FRC_IF_PKTBUFSTART_SHIFT 20 /**< Shift value for FRC_PKTBUFSTART */
+#define _FRC_IF_PKTBUFSTART_MASK 0x100000UL /**< Bit mask for FRC_PKTBUFSTART */
+#define _FRC_IF_PKTBUFSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_PKTBUFSTART_DEFAULT (_FRC_IF_PKTBUFSTART_DEFAULT << 20) /**< Shifted mode DEFAULT for FRC_IF */
+#define FRC_IF_PKTBUFTHRESHOLD (0x1UL << 21) /**< Packet Buffer Threshold */
+#define _FRC_IF_PKTBUFTHRESHOLD_SHIFT 21 /**< Shift value for FRC_PKTBUFTHRESHOLD */
+#define _FRC_IF_PKTBUFTHRESHOLD_MASK 0x200000UL /**< Bit mask for FRC_PKTBUFTHRESHOLD */
+#define _FRC_IF_PKTBUFTHRESHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_PKTBUFTHRESHOLD_DEFAULT (_FRC_IF_PKTBUFTHRESHOLD_DEFAULT << 21) /**< Shifted mode DEFAULT for FRC_IF */
+#define FRC_IF_RXRAWOF (0x1UL << 22) /**< RX raw FIFO overflow */
+#define _FRC_IF_RXRAWOF_SHIFT 22 /**< Shift value for FRC_RXRAWOF */
+#define _FRC_IF_RXRAWOF_MASK 0x400000UL /**< Bit mask for FRC_RXRAWOF */
+#define _FRC_IF_RXRAWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_RXRAWOF_DEFAULT (_FRC_IF_RXRAWOF_DEFAULT << 22) /**< Shifted mode DEFAULT for FRC_IF */
+#define FRC_IF_WCNTCMP5 (0x1UL << 23) /**< Word Counter Compare 5 Event */
+#define _FRC_IF_WCNTCMP5_SHIFT 23 /**< Shift value for FRC_WCNTCMP5 */
+#define _FRC_IF_WCNTCMP5_MASK 0x800000UL /**< Bit mask for FRC_WCNTCMP5 */
+#define _FRC_IF_WCNTCMP5_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_WCNTCMP5_DEFAULT (_FRC_IF_WCNTCMP5_DEFAULT << 23) /**< Shifted mode DEFAULT for FRC_IF */
+#define FRC_IF_FRAMEDETPAUSED (0x1UL << 24) /**< Frame detected pause event active */
+#define _FRC_IF_FRAMEDETPAUSED_SHIFT 24 /**< Shift value for FRC_FRAMEDETPAUSED */
+#define _FRC_IF_FRAMEDETPAUSED_MASK 0x1000000UL /**< Bit mask for FRC_FRAMEDETPAUSED */
+#define _FRC_IF_FRAMEDETPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_FRAMEDETPAUSED_DEFAULT (_FRC_IF_FRAMEDETPAUSED_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_IF */
+#define FRC_IF_INTERLEAVEWRITEPAUSED (0x1UL << 25) /**< Interleaver write pause event active */
+#define _FRC_IF_INTERLEAVEWRITEPAUSED_SHIFT 25 /**< Shift value for FRC_INTERLEAVEWRITEPAUSED */
+#define _FRC_IF_INTERLEAVEWRITEPAUSED_MASK 0x2000000UL /**< Bit mask for FRC_INTERLEAVEWRITEPAUSED */
+#define _FRC_IF_INTERLEAVEWRITEPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_INTERLEAVEWRITEPAUSED_DEFAULT (_FRC_IF_INTERLEAVEWRITEPAUSED_DEFAULT << 25) /**< Shifted mode DEFAULT for FRC_IF */
+#define FRC_IF_INTERLEAVEREADPAUSED (0x1UL << 26) /**< Interleaver read pause event active */
+#define _FRC_IF_INTERLEAVEREADPAUSED_SHIFT 26 /**< Shift value for FRC_INTERLEAVEREADPAUSED */
+#define _FRC_IF_INTERLEAVEREADPAUSED_MASK 0x4000000UL /**< Bit mask for FRC_INTERLEAVEREADPAUSED */
+#define _FRC_IF_INTERLEAVEREADPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_INTERLEAVEREADPAUSED_DEFAULT (_FRC_IF_INTERLEAVEREADPAUSED_DEFAULT << 26) /**< Shifted mode DEFAULT for FRC_IF */
+#define FRC_IF_TXSUBFRAMEPAUSED (0x1UL << 27) /**< Transmit subframe pause event active */
+#define _FRC_IF_TXSUBFRAMEPAUSED_SHIFT 27 /**< Shift value for FRC_TXSUBFRAMEPAUSED */
+#define _FRC_IF_TXSUBFRAMEPAUSED_MASK 0x8000000UL /**< Bit mask for FRC_TXSUBFRAMEPAUSED */
+#define _FRC_IF_TXSUBFRAMEPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_TXSUBFRAMEPAUSED_DEFAULT (_FRC_IF_TXSUBFRAMEPAUSED_DEFAULT << 27) /**< Shifted mode DEFAULT for FRC_IF */
+#define FRC_IF_CONVPAUSED (0x1UL << 28) /**< Convolutional coder pause event active */
+#define _FRC_IF_CONVPAUSED_SHIFT 28 /**< Shift value for FRC_CONVPAUSED */
+#define _FRC_IF_CONVPAUSED_MASK 0x10000000UL /**< Bit mask for FRC_CONVPAUSED */
+#define _FRC_IF_CONVPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_CONVPAUSED_DEFAULT (_FRC_IF_CONVPAUSED_DEFAULT << 28) /**< Shifted mode DEFAULT for FRC_IF */
+#define FRC_IF_RXWORD (0x1UL << 29) /**< Receive Word Interrupt Flag */
+#define _FRC_IF_RXWORD_SHIFT 29 /**< Shift value for FRC_RXWORD */
+#define _FRC_IF_RXWORD_MASK 0x20000000UL /**< Bit mask for FRC_RXWORD */
+#define _FRC_IF_RXWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_RXWORD_DEFAULT (_FRC_IF_RXWORD_DEFAULT << 29) /**< Shifted mode DEFAULT for FRC_IF */
+#define FRC_IF_TXWORD (0x1UL << 30) /**< Transmit Word Interrupt Flag */
+#define _FRC_IF_TXWORD_SHIFT 30 /**< Shift value for FRC_TXWORD */
+#define _FRC_IF_TXWORD_MASK 0x40000000UL /**< Bit mask for FRC_TXWORD */
+#define _FRC_IF_TXWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_TXWORD_DEFAULT (_FRC_IF_TXWORD_DEFAULT << 30) /**< Shifted mode DEFAULT for FRC_IF */
+#define FRC_IF_UARTERROR (0x1UL << 31) /**< Uart Error Interrupt Flag */
+#define _FRC_IF_UARTERROR_SHIFT 31 /**< Shift value for FRC_UARTERROR */
+#define _FRC_IF_UARTERROR_MASK 0x80000000UL /**< Bit mask for FRC_UARTERROR */
+#define _FRC_IF_UARTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IF */
+#define FRC_IF_UARTERROR_DEFAULT (_FRC_IF_UARTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for FRC_IF */
+
+/* Bit fields for FRC IEN */
+#define _FRC_IEN_RESETVALUE 0x00000000UL /**< Default value for FRC_IEN */
+#define _FRC_IEN_MASK 0xFFFFFFFFUL /**< Mask for FRC_IEN */
+#define FRC_IEN_TXDONE (0x1UL << 0) /**< TX Done Interrupt Enable */
+#define _FRC_IEN_TXDONE_SHIFT 0 /**< Shift value for FRC_TXDONE */
+#define _FRC_IEN_TXDONE_MASK 0x1UL /**< Bit mask for FRC_TXDONE */
+#define _FRC_IEN_TXDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_TXDONE_DEFAULT (_FRC_IEN_TXDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_IEN */
+#define FRC_IEN_TXAFTERFRAMEDONE (0x1UL << 1) /**< TX after frame Done Interrupt Enable */
+#define _FRC_IEN_TXAFTERFRAMEDONE_SHIFT 1 /**< Shift value for FRC_TXAFTERFRAMEDONE */
+#define _FRC_IEN_TXAFTERFRAMEDONE_MASK 0x2UL /**< Bit mask for FRC_TXAFTERFRAMEDONE */
+#define _FRC_IEN_TXAFTERFRAMEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_TXAFTERFRAMEDONE_DEFAULT (_FRC_IEN_TXAFTERFRAMEDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for FRC_IEN */
+#define FRC_IEN_TXABORTED (0x1UL << 2) /**< Transmit Aborted Interrupt Enable */
+#define _FRC_IEN_TXABORTED_SHIFT 2 /**< Shift value for FRC_TXABORTED */
+#define _FRC_IEN_TXABORTED_MASK 0x4UL /**< Bit mask for FRC_TXABORTED */
+#define _FRC_IEN_TXABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_TXABORTED_DEFAULT (_FRC_IEN_TXABORTED_DEFAULT << 2) /**< Shifted mode DEFAULT for FRC_IEN */
+#define FRC_IEN_TXUF (0x1UL << 3) /**< Transmit Underflow Interrupt Enable */
+#define _FRC_IEN_TXUF_SHIFT 3 /**< Shift value for FRC_TXUF */
+#define _FRC_IEN_TXUF_MASK 0x8UL /**< Bit mask for FRC_TXUF */
+#define _FRC_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_TXUF_DEFAULT (_FRC_IEN_TXUF_DEFAULT << 3) /**< Shifted mode DEFAULT for FRC_IEN */
+#define FRC_IEN_RXDONE (0x1UL << 4) /**< RX Done Interrupt Enable */
+#define _FRC_IEN_RXDONE_SHIFT 4 /**< Shift value for FRC_RXDONE */
+#define _FRC_IEN_RXDONE_MASK 0x10UL /**< Bit mask for FRC_RXDONE */
+#define _FRC_IEN_RXDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_RXDONE_DEFAULT (_FRC_IEN_RXDONE_DEFAULT << 4) /**< Shifted mode DEFAULT for FRC_IEN */
+#define FRC_IEN_RXABORTED (0x1UL << 5) /**< RX Aborted Interrupt Enable */
+#define _FRC_IEN_RXABORTED_SHIFT 5 /**< Shift value for FRC_RXABORTED */
+#define _FRC_IEN_RXABORTED_MASK 0x20UL /**< Bit mask for FRC_RXABORTED */
+#define _FRC_IEN_RXABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_RXABORTED_DEFAULT (_FRC_IEN_RXABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for FRC_IEN */
+#define FRC_IEN_FRAMEERROR (0x1UL << 6) /**< Frame Error Interrupt Enable */
+#define _FRC_IEN_FRAMEERROR_SHIFT 6 /**< Shift value for FRC_FRAMEERROR */
+#define _FRC_IEN_FRAMEERROR_MASK 0x40UL /**< Bit mask for FRC_FRAMEERROR */
+#define _FRC_IEN_FRAMEERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_FRAMEERROR_DEFAULT (_FRC_IEN_FRAMEERROR_DEFAULT << 6) /**< Shifted mode DEFAULT for FRC_IEN */
+#define FRC_IEN_BLOCKERROR (0x1UL << 7) /**< Block Error Interrupt Enable */
+#define _FRC_IEN_BLOCKERROR_SHIFT 7 /**< Shift value for FRC_BLOCKERROR */
+#define _FRC_IEN_BLOCKERROR_MASK 0x80UL /**< Bit mask for FRC_BLOCKERROR */
+#define _FRC_IEN_BLOCKERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_BLOCKERROR_DEFAULT (_FRC_IEN_BLOCKERROR_DEFAULT << 7) /**< Shifted mode DEFAULT for FRC_IEN */
+#define FRC_IEN_RXOF (0x1UL << 8) /**< Receive Overflow Interrupt Enable */
+#define _FRC_IEN_RXOF_SHIFT 8 /**< Shift value for FRC_RXOF */
+#define _FRC_IEN_RXOF_MASK 0x100UL /**< Bit mask for FRC_RXOF */
+#define _FRC_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_RXOF_DEFAULT (_FRC_IEN_RXOF_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_IEN */
+#define FRC_IEN_WCNTCMP0 (0x1UL << 9) /**< Word Counter Compare 0 Enable */
+#define _FRC_IEN_WCNTCMP0_SHIFT 9 /**< Shift value for FRC_WCNTCMP0 */
+#define _FRC_IEN_WCNTCMP0_MASK 0x200UL /**< Bit mask for FRC_WCNTCMP0 */
+#define _FRC_IEN_WCNTCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_WCNTCMP0_DEFAULT (_FRC_IEN_WCNTCMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for FRC_IEN */
+#define FRC_IEN_WCNTCMP1 (0x1UL << 10) /**< Word Counter Compare 1 Enable */
+#define _FRC_IEN_WCNTCMP1_SHIFT 10 /**< Shift value for FRC_WCNTCMP1 */
+#define _FRC_IEN_WCNTCMP1_MASK 0x400UL /**< Bit mask for FRC_WCNTCMP1 */
+#define _FRC_IEN_WCNTCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_WCNTCMP1_DEFAULT (_FRC_IEN_WCNTCMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for FRC_IEN */
+#define FRC_IEN_WCNTCMP2 (0x1UL << 11) /**< Word Counter Compare 2 Enable */
+#define _FRC_IEN_WCNTCMP2_SHIFT 11 /**< Shift value for FRC_WCNTCMP2 */
+#define _FRC_IEN_WCNTCMP2_MASK 0x800UL /**< Bit mask for FRC_WCNTCMP2 */
+#define _FRC_IEN_WCNTCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_WCNTCMP2_DEFAULT (_FRC_IEN_WCNTCMP2_DEFAULT << 11) /**< Shifted mode DEFAULT for FRC_IEN */
+#define FRC_IEN_ADDRERROR (0x1UL << 12) /**< Receive address error enable */
+#define _FRC_IEN_ADDRERROR_SHIFT 12 /**< Shift value for FRC_ADDRERROR */
+#define _FRC_IEN_ADDRERROR_MASK 0x1000UL /**< Bit mask for FRC_ADDRERROR */
+#define _FRC_IEN_ADDRERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_ADDRERROR_DEFAULT (_FRC_IEN_ADDRERROR_DEFAULT << 12) /**< Shifted mode DEFAULT for FRC_IEN */
+#define FRC_IEN_BUSERROR (0x1UL << 13) /**< Bus error enable */
+#define _FRC_IEN_BUSERROR_SHIFT 13 /**< Shift value for FRC_BUSERROR */
+#define _FRC_IEN_BUSERROR_MASK 0x2000UL /**< Bit mask for FRC_BUSERROR */
+#define _FRC_IEN_BUSERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_BUSERROR_DEFAULT (_FRC_IEN_BUSERROR_DEFAULT << 13) /**< Shifted mode DEFAULT for FRC_IEN */
+#define FRC_IEN_RXRAWEVENT (0x1UL << 14) /**< Receiver raw data enable */
+#define _FRC_IEN_RXRAWEVENT_SHIFT 14 /**< Shift value for FRC_RXRAWEVENT */
+#define _FRC_IEN_RXRAWEVENT_MASK 0x4000UL /**< Bit mask for FRC_RXRAWEVENT */
+#define _FRC_IEN_RXRAWEVENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_RXRAWEVENT_DEFAULT (_FRC_IEN_RXRAWEVENT_DEFAULT << 14) /**< Shifted mode DEFAULT for FRC_IEN */
+#define FRC_IEN_TXRAWEVENT (0x1UL << 15) /**< Transmit raw data enable */
+#define _FRC_IEN_TXRAWEVENT_SHIFT 15 /**< Shift value for FRC_TXRAWEVENT */
+#define _FRC_IEN_TXRAWEVENT_MASK 0x8000UL /**< Bit mask for FRC_TXRAWEVENT */
+#define _FRC_IEN_TXRAWEVENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_TXRAWEVENT_DEFAULT (_FRC_IEN_TXRAWEVENT_DEFAULT << 15) /**< Shifted mode DEFAULT for FRC_IEN */
+#define FRC_IEN_SNIFFOF (0x1UL << 16) /**< Data sniffer overflow enable */
+#define _FRC_IEN_SNIFFOF_SHIFT 16 /**< Shift value for FRC_SNIFFOF */
+#define _FRC_IEN_SNIFFOF_MASK 0x10000UL /**< Bit mask for FRC_SNIFFOF */
+#define _FRC_IEN_SNIFFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_SNIFFOF_DEFAULT (_FRC_IEN_SNIFFOF_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_IEN */
+#define FRC_IEN_WCNTCMP3 (0x1UL << 17) /**< Word Counter Compare 3 Enable */
+#define _FRC_IEN_WCNTCMP3_SHIFT 17 /**< Shift value for FRC_WCNTCMP3 */
+#define _FRC_IEN_WCNTCMP3_MASK 0x20000UL /**< Bit mask for FRC_WCNTCMP3 */
+#define _FRC_IEN_WCNTCMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_WCNTCMP3_DEFAULT (_FRC_IEN_WCNTCMP3_DEFAULT << 17) /**< Shifted mode DEFAULT for FRC_IEN */
+#define FRC_IEN_WCNTCMP4 (0x1UL << 18) /**< Word Counter Compare 4 Enable */
+#define _FRC_IEN_WCNTCMP4_SHIFT 18 /**< Shift value for FRC_WCNTCMP4 */
+#define _FRC_IEN_WCNTCMP4_MASK 0x40000UL /**< Bit mask for FRC_WCNTCMP4 */
+#define _FRC_IEN_WCNTCMP4_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_WCNTCMP4_DEFAULT (_FRC_IEN_WCNTCMP4_DEFAULT << 18) /**< Shifted mode DEFAULT for FRC_IEN */
+#define FRC_IEN_BOISET (0x1UL << 19) /**< BOISET */
+#define _FRC_IEN_BOISET_SHIFT 19 /**< Shift value for FRC_BOISET */
+#define _FRC_IEN_BOISET_MASK 0x80000UL /**< Bit mask for FRC_BOISET */
+#define _FRC_IEN_BOISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_BOISET_DEFAULT (_FRC_IEN_BOISET_DEFAULT << 19) /**< Shifted mode DEFAULT for FRC_IEN */
+#define FRC_IEN_PKTBUFSTART (0x1UL << 20) /**< PKTBUFSTART Enable */
+#define _FRC_IEN_PKTBUFSTART_SHIFT 20 /**< Shift value for FRC_PKTBUFSTART */
+#define _FRC_IEN_PKTBUFSTART_MASK 0x100000UL /**< Bit mask for FRC_PKTBUFSTART */
+#define _FRC_IEN_PKTBUFSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_PKTBUFSTART_DEFAULT (_FRC_IEN_PKTBUFSTART_DEFAULT << 20) /**< Shifted mode DEFAULT for FRC_IEN */
+#define FRC_IEN_PKTBUFTHRESHOLD (0x1UL << 21) /**< PKTBUFTHRESHOLD Enable */
+#define _FRC_IEN_PKTBUFTHRESHOLD_SHIFT 21 /**< Shift value for FRC_PKTBUFTHRESHOLD */
+#define _FRC_IEN_PKTBUFTHRESHOLD_MASK 0x200000UL /**< Bit mask for FRC_PKTBUFTHRESHOLD */
+#define _FRC_IEN_PKTBUFTHRESHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_PKTBUFTHRESHOLD_DEFAULT (_FRC_IEN_PKTBUFTHRESHOLD_DEFAULT << 21) /**< Shifted mode DEFAULT for FRC_IEN */
+#define FRC_IEN_RXRAWOF (0x1UL << 22) /**< RXRAWOF Enable */
+#define _FRC_IEN_RXRAWOF_SHIFT 22 /**< Shift value for FRC_RXRAWOF */
+#define _FRC_IEN_RXRAWOF_MASK 0x400000UL /**< Bit mask for FRC_RXRAWOF */
+#define _FRC_IEN_RXRAWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_RXRAWOF_DEFAULT (_FRC_IEN_RXRAWOF_DEFAULT << 22) /**< Shifted mode DEFAULT for FRC_IEN */
+#define FRC_IEN_WCNTCMP5 (0x1UL << 23) /**< Word Counter Compare 5 Enable */
+#define _FRC_IEN_WCNTCMP5_SHIFT 23 /**< Shift value for FRC_WCNTCMP5 */
+#define _FRC_IEN_WCNTCMP5_MASK 0x800000UL /**< Bit mask for FRC_WCNTCMP5 */
+#define _FRC_IEN_WCNTCMP5_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_WCNTCMP5_DEFAULT (_FRC_IEN_WCNTCMP5_DEFAULT << 23) /**< Shifted mode DEFAULT for FRC_IEN */
+#define FRC_IEN_FRAMEDETPAUSED (0x1UL << 24) /**< Frame detected pause event enable */
+#define _FRC_IEN_FRAMEDETPAUSED_SHIFT 24 /**< Shift value for FRC_FRAMEDETPAUSED */
+#define _FRC_IEN_FRAMEDETPAUSED_MASK 0x1000000UL /**< Bit mask for FRC_FRAMEDETPAUSED */
+#define _FRC_IEN_FRAMEDETPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_FRAMEDETPAUSED_DEFAULT (_FRC_IEN_FRAMEDETPAUSED_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_IEN */
+#define FRC_IEN_INTERLEAVEWRITEPAUSED (0x1UL << 25) /**< Interleaver write pause event enable */
+#define _FRC_IEN_INTERLEAVEWRITEPAUSED_SHIFT 25 /**< Shift value for FRC_INTERLEAVEWRITEPAUSED */
+#define _FRC_IEN_INTERLEAVEWRITEPAUSED_MASK 0x2000000UL /**< Bit mask for FRC_INTERLEAVEWRITEPAUSED */
+#define _FRC_IEN_INTERLEAVEWRITEPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_INTERLEAVEWRITEPAUSED_DEFAULT (_FRC_IEN_INTERLEAVEWRITEPAUSED_DEFAULT << 25) /**< Shifted mode DEFAULT for FRC_IEN */
+#define FRC_IEN_INTERLEAVEREADPAUSED (0x1UL << 26) /**< Interleaver read pause event enable */
+#define _FRC_IEN_INTERLEAVEREADPAUSED_SHIFT 26 /**< Shift value for FRC_INTERLEAVEREADPAUSED */
+#define _FRC_IEN_INTERLEAVEREADPAUSED_MASK 0x4000000UL /**< Bit mask for FRC_INTERLEAVEREADPAUSED */
+#define _FRC_IEN_INTERLEAVEREADPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_INTERLEAVEREADPAUSED_DEFAULT (_FRC_IEN_INTERLEAVEREADPAUSED_DEFAULT << 26) /**< Shifted mode DEFAULT for FRC_IEN */
+#define FRC_IEN_TXSUBFRAMEPAUSED (0x1UL << 27) /**< Transmit subframe pause event enable */
+#define _FRC_IEN_TXSUBFRAMEPAUSED_SHIFT 27 /**< Shift value for FRC_TXSUBFRAMEPAUSED */
+#define _FRC_IEN_TXSUBFRAMEPAUSED_MASK 0x8000000UL /**< Bit mask for FRC_TXSUBFRAMEPAUSED */
+#define _FRC_IEN_TXSUBFRAMEPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_TXSUBFRAMEPAUSED_DEFAULT (_FRC_IEN_TXSUBFRAMEPAUSED_DEFAULT << 27) /**< Shifted mode DEFAULT for FRC_IEN */
+#define FRC_IEN_CONVPAUSED (0x1UL << 28) /**< Convolutional coder pause event enable */
+#define _FRC_IEN_CONVPAUSED_SHIFT 28 /**< Shift value for FRC_CONVPAUSED */
+#define _FRC_IEN_CONVPAUSED_MASK 0x10000000UL /**< Bit mask for FRC_CONVPAUSED */
+#define _FRC_IEN_CONVPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_CONVPAUSED_DEFAULT (_FRC_IEN_CONVPAUSED_DEFAULT << 28) /**< Shifted mode DEFAULT for FRC_IEN */
+#define FRC_IEN_RXWORD (0x1UL << 29) /**< Receive Word Interrupt Enable */
+#define _FRC_IEN_RXWORD_SHIFT 29 /**< Shift value for FRC_RXWORD */
+#define _FRC_IEN_RXWORD_MASK 0x20000000UL /**< Bit mask for FRC_RXWORD */
+#define _FRC_IEN_RXWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_RXWORD_DEFAULT (_FRC_IEN_RXWORD_DEFAULT << 29) /**< Shifted mode DEFAULT for FRC_IEN */
+#define FRC_IEN_TXWORD (0x1UL << 30) /**< Transmit Word Interrupt Enable */
+#define _FRC_IEN_TXWORD_SHIFT 30 /**< Shift value for FRC_TXWORD */
+#define _FRC_IEN_TXWORD_MASK 0x40000000UL /**< Bit mask for FRC_TXWORD */
+#define _FRC_IEN_TXWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_TXWORD_DEFAULT (_FRC_IEN_TXWORD_DEFAULT << 30) /**< Shifted mode DEFAULT for FRC_IEN */
+#define FRC_IEN_UARTERROR (0x1UL << 31) /**< UART Error Interrupt Enable */
+#define _FRC_IEN_UARTERROR_SHIFT 31 /**< Shift value for FRC_UARTERROR */
+#define _FRC_IEN_UARTERROR_MASK 0x80000000UL /**< Bit mask for FRC_UARTERROR */
+#define _FRC_IEN_UARTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_IEN */
+#define FRC_IEN_UARTERROR_DEFAULT (_FRC_IEN_UARTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for FRC_IEN */
+
+/* Bit fields for FRC OTACNT */
+#define _FRC_OTACNT_RESETVALUE 0x00000000UL /**< Default value for FRC_OTACNT */
+#define _FRC_OTACNT_MASK 0xFFFFFFFFUL /**< Mask for FRC_OTACNT */
+#define _FRC_OTACNT_OTARXCNT_SHIFT 0 /**< Shift value for FRC_OTARXCNT */
+#define _FRC_OTACNT_OTARXCNT_MASK 0xFFFFUL /**< Bit mask for FRC_OTARXCNT */
+#define _FRC_OTACNT_OTARXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_OTACNT */
+#define FRC_OTACNT_OTARXCNT_DEFAULT (_FRC_OTACNT_OTARXCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_OTACNT */
+#define _FRC_OTACNT_OTATXCNT_SHIFT 16 /**< Shift value for FRC_OTATXCNT */
+#define _FRC_OTACNT_OTATXCNT_MASK 0xFFFF0000UL /**< Bit mask for FRC_OTATXCNT */
+#define _FRC_OTACNT_OTATXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_OTACNT */
+#define FRC_OTACNT_OTATXCNT_DEFAULT (_FRC_OTACNT_OTATXCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_OTACNT */
+
+/* Bit fields for FRC BUFFERMODE */
+#define _FRC_BUFFERMODE_RESETVALUE 0x00000000UL /**< Default value for FRC_BUFFERMODE */
+#define _FRC_BUFFERMODE_MASK 0x0000000FUL /**< Mask for FRC_BUFFERMODE */
+#define FRC_BUFFERMODE_TXBUFFERMODE (0x1UL << 0) /**< Transmit Buffer Mode */
+#define _FRC_BUFFERMODE_TXBUFFERMODE_SHIFT 0 /**< Shift value for FRC_TXBUFFERMODE */
+#define _FRC_BUFFERMODE_TXBUFFERMODE_MASK 0x1UL /**< Bit mask for FRC_TXBUFFERMODE */
+#define _FRC_BUFFERMODE_TXBUFFERMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_BUFFERMODE */
+#define _FRC_BUFFERMODE_TXBUFFERMODE_BUFC 0x00000000UL /**< Mode BUFC for FRC_BUFFERMODE */
+#define _FRC_BUFFERMODE_TXBUFFERMODE_REGISTER 0x00000001UL /**< Mode REGISTER for FRC_BUFFERMODE */
+#define FRC_BUFFERMODE_TXBUFFERMODE_DEFAULT (_FRC_BUFFERMODE_TXBUFFERMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_BUFFERMODE */
+#define FRC_BUFFERMODE_TXBUFFERMODE_BUFC (_FRC_BUFFERMODE_TXBUFFERMODE_BUFC << 0) /**< Shifted mode BUFC for FRC_BUFFERMODE */
+#define FRC_BUFFERMODE_TXBUFFERMODE_REGISTER (_FRC_BUFFERMODE_TXBUFFERMODE_REGISTER << 0) /**< Shifted mode REGISTER for FRC_BUFFERMODE */
+#define _FRC_BUFFERMODE_RXBUFFERMODE_SHIFT 1 /**< Shift value for FRC_RXBUFFERMODE */
+#define _FRC_BUFFERMODE_RXBUFFERMODE_MASK 0x6UL /**< Bit mask for FRC_RXBUFFERMODE */
+#define _FRC_BUFFERMODE_RXBUFFERMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_BUFFERMODE */
+#define _FRC_BUFFERMODE_RXBUFFERMODE_BUFC 0x00000000UL /**< Mode BUFC for FRC_BUFFERMODE */
+#define _FRC_BUFFERMODE_RXBUFFERMODE_REGISTER 0x00000001UL /**< Mode REGISTER for FRC_BUFFERMODE */
+#define _FRC_BUFFERMODE_RXBUFFERMODE_DISABLE 0x00000002UL /**< Mode DISABLE for FRC_BUFFERMODE */
+#define FRC_BUFFERMODE_RXBUFFERMODE_DEFAULT (_FRC_BUFFERMODE_RXBUFFERMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for FRC_BUFFERMODE */
+#define FRC_BUFFERMODE_RXBUFFERMODE_BUFC (_FRC_BUFFERMODE_RXBUFFERMODE_BUFC << 1) /**< Shifted mode BUFC for FRC_BUFFERMODE */
+#define FRC_BUFFERMODE_RXBUFFERMODE_REGISTER (_FRC_BUFFERMODE_RXBUFFERMODE_REGISTER << 1) /**< Shifted mode REGISTER for FRC_BUFFERMODE */
+#define FRC_BUFFERMODE_RXBUFFERMODE_DISABLE (_FRC_BUFFERMODE_RXBUFFERMODE_DISABLE << 1) /**< Shifted mode DISABLE for FRC_BUFFERMODE */
+#define FRC_BUFFERMODE_RXFRCBUFMUX (0x1UL << 3) /**< RX FRC Buffer Mux */
+#define _FRC_BUFFERMODE_RXFRCBUFMUX_SHIFT 3 /**< Shift value for FRC_RXFRCBUFMUX */
+#define _FRC_BUFFERMODE_RXFRCBUFMUX_MASK 0x8UL /**< Bit mask for FRC_RXFRCBUFMUX */
+#define _FRC_BUFFERMODE_RXFRCBUFMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_BUFFERMODE */
+#define FRC_BUFFERMODE_RXFRCBUFMUX_DEFAULT (_FRC_BUFFERMODE_RXFRCBUFMUX_DEFAULT << 3) /**< Shifted mode DEFAULT for FRC_BUFFERMODE */
+
+/* Bit fields for FRC SNIFFCTRL */
+#define _FRC_SNIFFCTRL_RESETVALUE 0x000007FCUL /**< Default value for FRC_SNIFFCTRL */
+#define _FRC_SNIFFCTRL_MASK 0x0003FFFFUL /**< Mask for FRC_SNIFFCTRL */
+#define _FRC_SNIFFCTRL_SNIFFMODE_SHIFT 0 /**< Shift value for FRC_SNIFFMODE */
+#define _FRC_SNIFFCTRL_SNIFFMODE_MASK 0x3UL /**< Bit mask for FRC_SNIFFMODE */
+#define _FRC_SNIFFCTRL_SNIFFMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SNIFFCTRL */
+#define _FRC_SNIFFCTRL_SNIFFMODE_OFF 0x00000000UL /**< Mode OFF for FRC_SNIFFCTRL */
+#define _FRC_SNIFFCTRL_SNIFFMODE_UART 0x00000001UL /**< Mode UART for FRC_SNIFFCTRL */
+#define _FRC_SNIFFCTRL_SNIFFMODE_SPI 0x00000002UL /**< Mode SPI for FRC_SNIFFCTRL */
+#define FRC_SNIFFCTRL_SNIFFMODE_DEFAULT (_FRC_SNIFFCTRL_SNIFFMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_SNIFFCTRL */
+#define FRC_SNIFFCTRL_SNIFFMODE_OFF (_FRC_SNIFFCTRL_SNIFFMODE_OFF << 0) /**< Shifted mode OFF for FRC_SNIFFCTRL */
+#define FRC_SNIFFCTRL_SNIFFMODE_UART (_FRC_SNIFFCTRL_SNIFFMODE_UART << 0) /**< Shifted mode UART for FRC_SNIFFCTRL */
+#define FRC_SNIFFCTRL_SNIFFMODE_SPI (_FRC_SNIFFCTRL_SNIFFMODE_SPI << 0) /**< Shifted mode SPI for FRC_SNIFFCTRL */
+#define FRC_SNIFFCTRL_SNIFFBITS (0x1UL << 2) /**< Data sniff data bits */
+#define _FRC_SNIFFCTRL_SNIFFBITS_SHIFT 2 /**< Shift value for FRC_SNIFFBITS */
+#define _FRC_SNIFFCTRL_SNIFFBITS_MASK 0x4UL /**< Bit mask for FRC_SNIFFBITS */
+#define _FRC_SNIFFCTRL_SNIFFBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for FRC_SNIFFCTRL */
+#define _FRC_SNIFFCTRL_SNIFFBITS_EIGHT 0x00000000UL /**< Mode EIGHT for FRC_SNIFFCTRL */
+#define _FRC_SNIFFCTRL_SNIFFBITS_NINE 0x00000001UL /**< Mode NINE for FRC_SNIFFCTRL */
+#define FRC_SNIFFCTRL_SNIFFBITS_DEFAULT (_FRC_SNIFFCTRL_SNIFFBITS_DEFAULT << 2) /**< Shifted mode DEFAULT for FRC_SNIFFCTRL */
+#define FRC_SNIFFCTRL_SNIFFBITS_EIGHT (_FRC_SNIFFCTRL_SNIFFBITS_EIGHT << 2) /**< Shifted mode EIGHT for FRC_SNIFFCTRL */
+#define FRC_SNIFFCTRL_SNIFFBITS_NINE (_FRC_SNIFFCTRL_SNIFFBITS_NINE << 2) /**< Shifted mode NINE for FRC_SNIFFCTRL */
+#define FRC_SNIFFCTRL_SNIFFRXDATA (0x1UL << 3) /**< Enable sniffing of received data. */
+#define _FRC_SNIFFCTRL_SNIFFRXDATA_SHIFT 3 /**< Shift value for FRC_SNIFFRXDATA */
+#define _FRC_SNIFFCTRL_SNIFFRXDATA_MASK 0x8UL /**< Bit mask for FRC_SNIFFRXDATA */
+#define _FRC_SNIFFCTRL_SNIFFRXDATA_DEFAULT 0x00000001UL /**< Mode DEFAULT for FRC_SNIFFCTRL */
+#define FRC_SNIFFCTRL_SNIFFRXDATA_DEFAULT (_FRC_SNIFFCTRL_SNIFFRXDATA_DEFAULT << 3) /**< Shifted mode DEFAULT for FRC_SNIFFCTRL */
+#define FRC_SNIFFCTRL_SNIFFTXDATA (0x1UL << 4) /**< Enable sniffing of transmitted data. */
+#define _FRC_SNIFFCTRL_SNIFFTXDATA_SHIFT 4 /**< Shift value for FRC_SNIFFTXDATA */
+#define _FRC_SNIFFCTRL_SNIFFTXDATA_MASK 0x10UL /**< Bit mask for FRC_SNIFFTXDATA */
+#define _FRC_SNIFFCTRL_SNIFFTXDATA_DEFAULT 0x00000001UL /**< Mode DEFAULT for FRC_SNIFFCTRL */
+#define FRC_SNIFFCTRL_SNIFFTXDATA_DEFAULT (_FRC_SNIFFCTRL_SNIFFTXDATA_DEFAULT << 4) /**< Shifted mode DEFAULT for FRC_SNIFFCTRL */
+#define FRC_SNIFFCTRL_SNIFFRSSI (0x1UL << 5) /**< Enable sniffing of RSSI */
+#define _FRC_SNIFFCTRL_SNIFFRSSI_SHIFT 5 /**< Shift value for FRC_SNIFFRSSI */
+#define _FRC_SNIFFCTRL_SNIFFRSSI_MASK 0x20UL /**< Bit mask for FRC_SNIFFRSSI */
+#define _FRC_SNIFFCTRL_SNIFFRSSI_DEFAULT 0x00000001UL /**< Mode DEFAULT for FRC_SNIFFCTRL */
+#define FRC_SNIFFCTRL_SNIFFRSSI_DEFAULT (_FRC_SNIFFCTRL_SNIFFRSSI_DEFAULT << 5) /**< Shifted mode DEFAULT for FRC_SNIFFCTRL */
+#define FRC_SNIFFCTRL_SNIFFSTATE (0x1UL << 6) /**< Enable sniffing of state information */
+#define _FRC_SNIFFCTRL_SNIFFSTATE_SHIFT 6 /**< Shift value for FRC_SNIFFSTATE */
+#define _FRC_SNIFFCTRL_SNIFFSTATE_MASK 0x40UL /**< Bit mask for FRC_SNIFFSTATE */
+#define _FRC_SNIFFCTRL_SNIFFSTATE_DEFAULT 0x00000001UL /**< Mode DEFAULT for FRC_SNIFFCTRL */
+#define FRC_SNIFFCTRL_SNIFFSTATE_DEFAULT (_FRC_SNIFFCTRL_SNIFFSTATE_DEFAULT << 6) /**< Shifted mode DEFAULT for FRC_SNIFFCTRL */
+#define FRC_SNIFFCTRL_SNIFFAUXDATA (0x1UL << 7) /**< Enable sniffing of auxiliary data */
+#define _FRC_SNIFFCTRL_SNIFFAUXDATA_SHIFT 7 /**< Shift value for FRC_SNIFFAUXDATA */
+#define _FRC_SNIFFCTRL_SNIFFAUXDATA_MASK 0x80UL /**< Bit mask for FRC_SNIFFAUXDATA */
+#define _FRC_SNIFFCTRL_SNIFFAUXDATA_DEFAULT 0x00000001UL /**< Mode DEFAULT for FRC_SNIFFCTRL */
+#define FRC_SNIFFCTRL_SNIFFAUXDATA_DEFAULT (_FRC_SNIFFCTRL_SNIFFAUXDATA_DEFAULT << 7) /**< Shifted mode DEFAULT for FRC_SNIFFCTRL */
+#define _FRC_SNIFFCTRL_SNIFFBR_SHIFT 8 /**< Shift value for FRC_SNIFFBR */
+#define _FRC_SNIFFCTRL_SNIFFBR_MASK 0xFF00UL /**< Bit mask for FRC_SNIFFBR */
+#define _FRC_SNIFFCTRL_SNIFFBR_DEFAULT 0x00000007UL /**< Mode DEFAULT for FRC_SNIFFCTRL */
+#define FRC_SNIFFCTRL_SNIFFBR_DEFAULT (_FRC_SNIFFCTRL_SNIFFBR_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_SNIFFCTRL */
+#define FRC_SNIFFCTRL_SNIFFSYNCWORD (0x1UL << 17) /**< Sniffer baudrate setting */
+#define _FRC_SNIFFCTRL_SNIFFSYNCWORD_SHIFT 17 /**< Shift value for FRC_SNIFFSYNCWORD */
+#define _FRC_SNIFFCTRL_SNIFFSYNCWORD_MASK 0x20000UL /**< Bit mask for FRC_SNIFFSYNCWORD */
+#define _FRC_SNIFFCTRL_SNIFFSYNCWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SNIFFCTRL */
+#define FRC_SNIFFCTRL_SNIFFSYNCWORD_DEFAULT (_FRC_SNIFFCTRL_SNIFFSYNCWORD_DEFAULT << 17) /**< Shifted mode DEFAULT for FRC_SNIFFCTRL */
+
+/* Bit fields for FRC AUXDATA */
+#define _FRC_AUXDATA_RESETVALUE 0x00000000UL /**< Default value for FRC_AUXDATA */
+#define _FRC_AUXDATA_MASK 0x000001FFUL /**< Mask for FRC_AUXDATA */
+#define _FRC_AUXDATA_AUXDATA_SHIFT 0 /**< Shift value for FRC_AUXDATA */
+#define _FRC_AUXDATA_AUXDATA_MASK 0x1FFUL /**< Bit mask for FRC_AUXDATA */
+#define _FRC_AUXDATA_AUXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_AUXDATA */
+#define FRC_AUXDATA_AUXDATA_DEFAULT (_FRC_AUXDATA_AUXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_AUXDATA */
+
+/* Bit fields for FRC RAWCTRL */
+#define _FRC_RAWCTRL_RESETVALUE 0x00000000UL /**< Default value for FRC_RAWCTRL */
+#define _FRC_RAWCTRL_MASK 0x000021BFUL /**< Mask for FRC_RAWCTRL */
+#define _FRC_RAWCTRL_TXRAWMODE_SHIFT 0 /**< Shift value for FRC_TXRAWMODE */
+#define _FRC_RAWCTRL_TXRAWMODE_MASK 0x3UL /**< Bit mask for FRC_TXRAWMODE */
+#define _FRC_RAWCTRL_TXRAWMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_RAWCTRL */
+#define _FRC_RAWCTRL_TXRAWMODE_DISABLE 0x00000000UL /**< Mode DISABLE for FRC_RAWCTRL */
+#define _FRC_RAWCTRL_TXRAWMODE_SINGLEBUFFER 0x00000001UL /**< Mode SINGLEBUFFER for FRC_RAWCTRL */
+#define _FRC_RAWCTRL_TXRAWMODE_REPEATBUFFER 0x00000002UL /**< Mode REPEATBUFFER for FRC_RAWCTRL */
+#define FRC_RAWCTRL_TXRAWMODE_DEFAULT (_FRC_RAWCTRL_TXRAWMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_RAWCTRL */
+#define FRC_RAWCTRL_TXRAWMODE_DISABLE (_FRC_RAWCTRL_TXRAWMODE_DISABLE << 0) /**< Shifted mode DISABLE for FRC_RAWCTRL */
+#define FRC_RAWCTRL_TXRAWMODE_SINGLEBUFFER (_FRC_RAWCTRL_TXRAWMODE_SINGLEBUFFER << 0) /**< Shifted mode SINGLEBUFFER for FRC_RAWCTRL */
+#define FRC_RAWCTRL_TXRAWMODE_REPEATBUFFER (_FRC_RAWCTRL_TXRAWMODE_REPEATBUFFER << 0) /**< Shifted mode REPEATBUFFER for FRC_RAWCTRL */
+#define _FRC_RAWCTRL_RXRAWMODE_SHIFT 2 /**< Shift value for FRC_RXRAWMODE */
+#define _FRC_RAWCTRL_RXRAWMODE_MASK 0x1CUL /**< Bit mask for FRC_RXRAWMODE */
+#define _FRC_RAWCTRL_RXRAWMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_RAWCTRL */
+#define _FRC_RAWCTRL_RXRAWMODE_DISABLE 0x00000000UL /**< Mode DISABLE for FRC_RAWCTRL */
+#define _FRC_RAWCTRL_RXRAWMODE_SINGLEITEM 0x00000001UL /**< Mode SINGLEITEM for FRC_RAWCTRL */
+#define _FRC_RAWCTRL_RXRAWMODE_SINGLEBUFFER 0x00000002UL /**< Mode SINGLEBUFFER for FRC_RAWCTRL */
+#define _FRC_RAWCTRL_RXRAWMODE_SINGLEBUFFERFRAME 0x00000003UL /**< Mode SINGLEBUFFERFRAME for FRC_RAWCTRL */
+#define _FRC_RAWCTRL_RXRAWMODE_REPEATBUFFER 0x00000004UL /**< Mode REPEATBUFFER for FRC_RAWCTRL */
+#define FRC_RAWCTRL_RXRAWMODE_DEFAULT (_FRC_RAWCTRL_RXRAWMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for FRC_RAWCTRL */
+#define FRC_RAWCTRL_RXRAWMODE_DISABLE (_FRC_RAWCTRL_RXRAWMODE_DISABLE << 2) /**< Shifted mode DISABLE for FRC_RAWCTRL */
+#define FRC_RAWCTRL_RXRAWMODE_SINGLEITEM (_FRC_RAWCTRL_RXRAWMODE_SINGLEITEM << 2) /**< Shifted mode SINGLEITEM for FRC_RAWCTRL */
+#define FRC_RAWCTRL_RXRAWMODE_SINGLEBUFFER (_FRC_RAWCTRL_RXRAWMODE_SINGLEBUFFER << 2) /**< Shifted mode SINGLEBUFFER for FRC_RAWCTRL */
+#define FRC_RAWCTRL_RXRAWMODE_SINGLEBUFFERFRAME (_FRC_RAWCTRL_RXRAWMODE_SINGLEBUFFERFRAME << 2) /**< Shifted mode SINGLEBUFFERFRAME for FRC_RAWCTRL*/
+#define FRC_RAWCTRL_RXRAWMODE_REPEATBUFFER (_FRC_RAWCTRL_RXRAWMODE_REPEATBUFFER << 2) /**< Shifted mode REPEATBUFFER for FRC_RAWCTRL */
+#define FRC_RAWCTRL_RXRAWRANDOM (0x1UL << 5) /**< Receive raw data random number generator */
+#define _FRC_RAWCTRL_RXRAWRANDOM_SHIFT 5 /**< Shift value for FRC_RXRAWRANDOM */
+#define _FRC_RAWCTRL_RXRAWRANDOM_MASK 0x20UL /**< Bit mask for FRC_RXRAWRANDOM */
+#define _FRC_RAWCTRL_RXRAWRANDOM_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_RAWCTRL */
+#define FRC_RAWCTRL_RXRAWRANDOM_DEFAULT (_FRC_RAWCTRL_RXRAWRANDOM_DEFAULT << 5) /**< Shifted mode DEFAULT for FRC_RAWCTRL */
+#define _FRC_RAWCTRL_RXRAWTRIGGER_SHIFT 7 /**< Shift value for FRC_RXRAWTRIGGER */
+#define _FRC_RAWCTRL_RXRAWTRIGGER_MASK 0x180UL /**< Bit mask for FRC_RXRAWTRIGGER */
+#define _FRC_RAWCTRL_RXRAWTRIGGER_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_RAWCTRL */
+#define _FRC_RAWCTRL_RXRAWTRIGGER_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for FRC_RAWCTRL */
+#define _FRC_RAWCTRL_RXRAWTRIGGER_PRS 0x00000001UL /**< Mode PRS for FRC_RAWCTRL */
+#define _FRC_RAWCTRL_RXRAWTRIGGER_INTERNALSIG 0x00000002UL /**< Mode INTERNALSIG for FRC_RAWCTRL */
+#define FRC_RAWCTRL_RXRAWTRIGGER_DEFAULT (_FRC_RAWCTRL_RXRAWTRIGGER_DEFAULT << 7) /**< Shifted mode DEFAULT for FRC_RAWCTRL */
+#define FRC_RAWCTRL_RXRAWTRIGGER_IMMEDIATE (_FRC_RAWCTRL_RXRAWTRIGGER_IMMEDIATE << 7) /**< Shifted mode IMMEDIATE for FRC_RAWCTRL */
+#define FRC_RAWCTRL_RXRAWTRIGGER_PRS (_FRC_RAWCTRL_RXRAWTRIGGER_PRS << 7) /**< Shifted mode PRS for FRC_RAWCTRL */
+#define FRC_RAWCTRL_RXRAWTRIGGER_INTERNALSIG (_FRC_RAWCTRL_RXRAWTRIGGER_INTERNALSIG << 7) /**< Shifted mode INTERNALSIG for FRC_RAWCTRL */
+#define FRC_RAWCTRL_DEMODRAWDATAMUX (0x1UL << 13) /**< Raw data mux control */
+#define _FRC_RAWCTRL_DEMODRAWDATAMUX_SHIFT 13 /**< Shift value for FRC_DEMODRAWDATAMUX */
+#define _FRC_RAWCTRL_DEMODRAWDATAMUX_MASK 0x2000UL /**< Bit mask for FRC_DEMODRAWDATAMUX */
+#define _FRC_RAWCTRL_DEMODRAWDATAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_RAWCTRL */
+#define _FRC_RAWCTRL_DEMODRAWDATAMUX_DEMODRAWDATASEL 0x00000000UL /**< Mode DEMODRAWDATASEL for FRC_RAWCTRL */
+#define _FRC_RAWCTRL_DEMODRAWDATAMUX_DEMODRAWDATASEL2 0x00000001UL /**< Mode DEMODRAWDATASEL2 for FRC_RAWCTRL */
+#define FRC_RAWCTRL_DEMODRAWDATAMUX_DEFAULT (_FRC_RAWCTRL_DEMODRAWDATAMUX_DEFAULT << 13) /**< Shifted mode DEFAULT for FRC_RAWCTRL */
+#define FRC_RAWCTRL_DEMODRAWDATAMUX_DEMODRAWDATASEL (_FRC_RAWCTRL_DEMODRAWDATAMUX_DEMODRAWDATASEL << 13) /**< Shifted mode DEMODRAWDATASEL for FRC_RAWCTRL*/
+#define FRC_RAWCTRL_DEMODRAWDATAMUX_DEMODRAWDATASEL2 (_FRC_RAWCTRL_DEMODRAWDATAMUX_DEMODRAWDATASEL2 << 13) /**< Shifted mode DEMODRAWDATASEL2 for FRC_RAWCTRL*/
+
+/* Bit fields for FRC RXRAWDATA */
+#define _FRC_RXRAWDATA_RESETVALUE 0x00000000UL /**< Default value for FRC_RXRAWDATA */
+#define _FRC_RXRAWDATA_MASK 0xFFFFFFFFUL /**< Mask for FRC_RXRAWDATA */
+#define _FRC_RXRAWDATA_RXRAWDATA_SHIFT 0 /**< Shift value for FRC_RXRAWDATA */
+#define _FRC_RXRAWDATA_RXRAWDATA_MASK 0xFFFFFFFFUL /**< Bit mask for FRC_RXRAWDATA */
+#define _FRC_RXRAWDATA_RXRAWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_RXRAWDATA */
+#define FRC_RXRAWDATA_RXRAWDATA_DEFAULT (_FRC_RXRAWDATA_RXRAWDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_RXRAWDATA */
+
+/* Bit fields for FRC PAUSEDATA */
+#define _FRC_PAUSEDATA_RESETVALUE 0x00000000UL /**< Default value for FRC_PAUSEDATA */
+#define _FRC_PAUSEDATA_MASK 0xFFFFFFFFUL /**< Mask for FRC_PAUSEDATA */
+#define _FRC_PAUSEDATA_PAUSEDATA_SHIFT 0 /**< Shift value for FRC_PAUSEDATA */
+#define _FRC_PAUSEDATA_PAUSEDATA_MASK 0xFFFFFFFFUL /**< Bit mask for FRC_PAUSEDATA */
+#define _FRC_PAUSEDATA_PAUSEDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PAUSEDATA */
+#define FRC_PAUSEDATA_PAUSEDATA_DEFAULT (_FRC_PAUSEDATA_PAUSEDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PAUSEDATA */
+
+/* Bit fields for FRC LIKELYCONVSTATE */
+#define _FRC_LIKELYCONVSTATE_RESETVALUE 0x00000000UL /**< Default value for FRC_LIKELYCONVSTATE */
+#define _FRC_LIKELYCONVSTATE_MASK 0x0000003FUL /**< Mask for FRC_LIKELYCONVSTATE */
+#define _FRC_LIKELYCONVSTATE_LIKELYCONVSTATE_SHIFT 0 /**< Shift value for FRC_LIKELYCONVSTATE */
+#define _FRC_LIKELYCONVSTATE_LIKELYCONVSTATE_MASK 0x3FUL /**< Bit mask for FRC_LIKELYCONVSTATE */
+#define _FRC_LIKELYCONVSTATE_LIKELYCONVSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_LIKELYCONVSTATE */
+#define FRC_LIKELYCONVSTATE_LIKELYCONVSTATE_DEFAULT (_FRC_LIKELYCONVSTATE_LIKELYCONVSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_LIKELYCONVSTATE*/
+
+/* Bit fields for FRC INTELEMENTNEXT */
+#define _FRC_INTELEMENTNEXT_RESETVALUE 0x00000000UL /**< Default value for FRC_INTELEMENTNEXT */
+#define _FRC_INTELEMENTNEXT_MASK 0x000000FFUL /**< Mask for FRC_INTELEMENTNEXT */
+#define _FRC_INTELEMENTNEXT_INTELEMENTNEXT_SHIFT 0 /**< Shift value for FRC_INTELEMENTNEXT */
+#define _FRC_INTELEMENTNEXT_INTELEMENTNEXT_MASK 0xFFUL /**< Bit mask for FRC_INTELEMENTNEXT */
+#define _FRC_INTELEMENTNEXT_INTELEMENTNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_INTELEMENTNEXT */
+#define FRC_INTELEMENTNEXT_INTELEMENTNEXT_DEFAULT (_FRC_INTELEMENTNEXT_INTELEMENTNEXT_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_INTELEMENTNEXT */
+
+/* Bit fields for FRC INTWRITEPOINT */
+#define _FRC_INTWRITEPOINT_RESETVALUE 0x00000000UL /**< Default value for FRC_INTWRITEPOINT */
+#define _FRC_INTWRITEPOINT_MASK 0x0000001FUL /**< Mask for FRC_INTWRITEPOINT */
+#define _FRC_INTWRITEPOINT_INTWRITEPOINT_SHIFT 0 /**< Shift value for FRC_INTWRITEPOINT */
+#define _FRC_INTWRITEPOINT_INTWRITEPOINT_MASK 0x1FUL /**< Bit mask for FRC_INTWRITEPOINT */
+#define _FRC_INTWRITEPOINT_INTWRITEPOINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_INTWRITEPOINT */
+#define FRC_INTWRITEPOINT_INTWRITEPOINT_DEFAULT (_FRC_INTWRITEPOINT_INTWRITEPOINT_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_INTWRITEPOINT */
+
+/* Bit fields for FRC INTREADPOINT */
+#define _FRC_INTREADPOINT_RESETVALUE 0x00000000UL /**< Default value for FRC_INTREADPOINT */
+#define _FRC_INTREADPOINT_MASK 0x0000001FUL /**< Mask for FRC_INTREADPOINT */
+#define _FRC_INTREADPOINT_INTREADPOINT_SHIFT 0 /**< Shift value for FRC_INTREADPOINT */
+#define _FRC_INTREADPOINT_INTREADPOINT_MASK 0x1FUL /**< Bit mask for FRC_INTREADPOINT */
+#define _FRC_INTREADPOINT_INTREADPOINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_INTREADPOINT */
+#define FRC_INTREADPOINT_INTREADPOINT_DEFAULT (_FRC_INTREADPOINT_INTREADPOINT_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_INTREADPOINT */
+
+/* Bit fields for FRC AUTOCG */
+#define _FRC_AUTOCG_RESETVALUE 0x00000000UL /**< Default value for FRC_AUTOCG */
+#define _FRC_AUTOCG_MASK 0x0000FFFFUL /**< Mask for FRC_AUTOCG */
+#define _FRC_AUTOCG_AUTOCGEN_SHIFT 0 /**< Shift value for FRC_AUTOCGEN */
+#define _FRC_AUTOCG_AUTOCGEN_MASK 0xFFFFUL /**< Bit mask for FRC_AUTOCGEN */
+#define _FRC_AUTOCG_AUTOCGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_AUTOCG */
+#define FRC_AUTOCG_AUTOCGEN_DEFAULT (_FRC_AUTOCG_AUTOCGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_AUTOCG */
+
+/* Bit fields for FRC CGCLKSTOP */
+#define _FRC_CGCLKSTOP_RESETVALUE 0x00000000UL /**< Default value for FRC_CGCLKSTOP */
+#define _FRC_CGCLKSTOP_MASK 0x0000FFFFUL /**< Mask for FRC_CGCLKSTOP */
+#define _FRC_CGCLKSTOP_FORCEOFF_SHIFT 0 /**< Shift value for FRC_FORCEOFF */
+#define _FRC_CGCLKSTOP_FORCEOFF_MASK 0xFFFFUL /**< Bit mask for FRC_FORCEOFF */
+#define _FRC_CGCLKSTOP_FORCEOFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_CGCLKSTOP */
+#define FRC_CGCLKSTOP_FORCEOFF_DEFAULT (_FRC_CGCLKSTOP_FORCEOFF_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_CGCLKSTOP */
+
+/* Bit fields for FRC SEQIF */
+#define _FRC_SEQIF_RESETVALUE 0x00000000UL /**< Default value for FRC_SEQIF */
+#define _FRC_SEQIF_MASK 0xFFFFFFFFUL /**< Mask for FRC_SEQIF */
+#define FRC_SEQIF_TXDONE (0x1UL << 0) /**< TX Done Interrupt Flag */
+#define _FRC_SEQIF_TXDONE_SHIFT 0 /**< Shift value for FRC_TXDONE */
+#define _FRC_SEQIF_TXDONE_MASK 0x1UL /**< Bit mask for FRC_TXDONE */
+#define _FRC_SEQIF_TXDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_TXDONE_DEFAULT (_FRC_SEQIF_TXDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_TXAFTERFRAMEDONE (0x1UL << 1) /**< TX after frame Done Interrupt Flag */
+#define _FRC_SEQIF_TXAFTERFRAMEDONE_SHIFT 1 /**< Shift value for FRC_TXAFTERFRAMEDONE */
+#define _FRC_SEQIF_TXAFTERFRAMEDONE_MASK 0x2UL /**< Bit mask for FRC_TXAFTERFRAMEDONE */
+#define _FRC_SEQIF_TXAFTERFRAMEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_TXAFTERFRAMEDONE_DEFAULT (_FRC_SEQIF_TXAFTERFRAMEDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_TXABORTED (0x1UL << 2) /**< Transmit Aborted Interrupt Flag */
+#define _FRC_SEQIF_TXABORTED_SHIFT 2 /**< Shift value for FRC_TXABORTED */
+#define _FRC_SEQIF_TXABORTED_MASK 0x4UL /**< Bit mask for FRC_TXABORTED */
+#define _FRC_SEQIF_TXABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_TXABORTED_DEFAULT (_FRC_SEQIF_TXABORTED_DEFAULT << 2) /**< Shifted mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_TXUF (0x1UL << 3) /**< Transmit Underflow Interrupt Flag */
+#define _FRC_SEQIF_TXUF_SHIFT 3 /**< Shift value for FRC_TXUF */
+#define _FRC_SEQIF_TXUF_MASK 0x8UL /**< Bit mask for FRC_TXUF */
+#define _FRC_SEQIF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_TXUF_DEFAULT (_FRC_SEQIF_TXUF_DEFAULT << 3) /**< Shifted mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_RXDONE (0x1UL << 4) /**< RX Done Interrupt Flag */
+#define _FRC_SEQIF_RXDONE_SHIFT 4 /**< Shift value for FRC_RXDONE */
+#define _FRC_SEQIF_RXDONE_MASK 0x10UL /**< Bit mask for FRC_RXDONE */
+#define _FRC_SEQIF_RXDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_RXDONE_DEFAULT (_FRC_SEQIF_RXDONE_DEFAULT << 4) /**< Shifted mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_RXABORTED (0x1UL << 5) /**< RX Aborted Interrupt Flag */
+#define _FRC_SEQIF_RXABORTED_SHIFT 5 /**< Shift value for FRC_RXABORTED */
+#define _FRC_SEQIF_RXABORTED_MASK 0x20UL /**< Bit mask for FRC_RXABORTED */
+#define _FRC_SEQIF_RXABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_RXABORTED_DEFAULT (_FRC_SEQIF_RXABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_FRAMEERROR (0x1UL << 6) /**< Frame Error Interrupt Flag */
+#define _FRC_SEQIF_FRAMEERROR_SHIFT 6 /**< Shift value for FRC_FRAMEERROR */
+#define _FRC_SEQIF_FRAMEERROR_MASK 0x40UL /**< Bit mask for FRC_FRAMEERROR */
+#define _FRC_SEQIF_FRAMEERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_FRAMEERROR_DEFAULT (_FRC_SEQIF_FRAMEERROR_DEFAULT << 6) /**< Shifted mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_BLOCKERROR (0x1UL << 7) /**< Block Error Interrupt Flag */
+#define _FRC_SEQIF_BLOCKERROR_SHIFT 7 /**< Shift value for FRC_BLOCKERROR */
+#define _FRC_SEQIF_BLOCKERROR_MASK 0x80UL /**< Bit mask for FRC_BLOCKERROR */
+#define _FRC_SEQIF_BLOCKERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_BLOCKERROR_DEFAULT (_FRC_SEQIF_BLOCKERROR_DEFAULT << 7) /**< Shifted mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_RXOF (0x1UL << 8) /**< Receive Overflow Interrupt Flag */
+#define _FRC_SEQIF_RXOF_SHIFT 8 /**< Shift value for FRC_RXOF */
+#define _FRC_SEQIF_RXOF_MASK 0x100UL /**< Bit mask for FRC_RXOF */
+#define _FRC_SEQIF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_RXOF_DEFAULT (_FRC_SEQIF_RXOF_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_WCNTCMP0 (0x1UL << 9) /**< Word Counter Compare 0 Event */
+#define _FRC_SEQIF_WCNTCMP0_SHIFT 9 /**< Shift value for FRC_WCNTCMP0 */
+#define _FRC_SEQIF_WCNTCMP0_MASK 0x200UL /**< Bit mask for FRC_WCNTCMP0 */
+#define _FRC_SEQIF_WCNTCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_WCNTCMP0_DEFAULT (_FRC_SEQIF_WCNTCMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_WCNTCMP1 (0x1UL << 10) /**< Word Counter Compare 1 Event */
+#define _FRC_SEQIF_WCNTCMP1_SHIFT 10 /**< Shift value for FRC_WCNTCMP1 */
+#define _FRC_SEQIF_WCNTCMP1_MASK 0x400UL /**< Bit mask for FRC_WCNTCMP1 */
+#define _FRC_SEQIF_WCNTCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_WCNTCMP1_DEFAULT (_FRC_SEQIF_WCNTCMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_WCNTCMP2 (0x1UL << 11) /**< Word Counter Compare 2 Event */
+#define _FRC_SEQIF_WCNTCMP2_SHIFT 11 /**< Shift value for FRC_WCNTCMP2 */
+#define _FRC_SEQIF_WCNTCMP2_MASK 0x800UL /**< Bit mask for FRC_WCNTCMP2 */
+#define _FRC_SEQIF_WCNTCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_WCNTCMP2_DEFAULT (_FRC_SEQIF_WCNTCMP2_DEFAULT << 11) /**< Shifted mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_ADDRERROR (0x1UL << 12) /**< Receive address error event */
+#define _FRC_SEQIF_ADDRERROR_SHIFT 12 /**< Shift value for FRC_ADDRERROR */
+#define _FRC_SEQIF_ADDRERROR_MASK 0x1000UL /**< Bit mask for FRC_ADDRERROR */
+#define _FRC_SEQIF_ADDRERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_ADDRERROR_DEFAULT (_FRC_SEQIF_ADDRERROR_DEFAULT << 12) /**< Shifted mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_BUSERROR (0x1UL << 13) /**< A bus error event occurred */
+#define _FRC_SEQIF_BUSERROR_SHIFT 13 /**< Shift value for FRC_BUSERROR */
+#define _FRC_SEQIF_BUSERROR_MASK 0x2000UL /**< Bit mask for FRC_BUSERROR */
+#define _FRC_SEQIF_BUSERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_BUSERROR_DEFAULT (_FRC_SEQIF_BUSERROR_DEFAULT << 13) /**< Shifted mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_RXRAWEVENT (0x1UL << 14) /**< Receiver raw data event */
+#define _FRC_SEQIF_RXRAWEVENT_SHIFT 14 /**< Shift value for FRC_RXRAWEVENT */
+#define _FRC_SEQIF_RXRAWEVENT_MASK 0x4000UL /**< Bit mask for FRC_RXRAWEVENT */
+#define _FRC_SEQIF_RXRAWEVENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_RXRAWEVENT_DEFAULT (_FRC_SEQIF_RXRAWEVENT_DEFAULT << 14) /**< Shifted mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_TXRAWEVENT (0x1UL << 15) /**< Transmit raw data event */
+#define _FRC_SEQIF_TXRAWEVENT_SHIFT 15 /**< Shift value for FRC_TXRAWEVENT */
+#define _FRC_SEQIF_TXRAWEVENT_MASK 0x8000UL /**< Bit mask for FRC_TXRAWEVENT */
+#define _FRC_SEQIF_TXRAWEVENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_TXRAWEVENT_DEFAULT (_FRC_SEQIF_TXRAWEVENT_DEFAULT << 15) /**< Shifted mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_SNIFFOF (0x1UL << 16) /**< Data sniffer overflow */
+#define _FRC_SEQIF_SNIFFOF_SHIFT 16 /**< Shift value for FRC_SNIFFOF */
+#define _FRC_SEQIF_SNIFFOF_MASK 0x10000UL /**< Bit mask for FRC_SNIFFOF */
+#define _FRC_SEQIF_SNIFFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_SNIFFOF_DEFAULT (_FRC_SEQIF_SNIFFOF_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_WCNTCMP3 (0x1UL << 17) /**< Word Counter Compare 3 Event */
+#define _FRC_SEQIF_WCNTCMP3_SHIFT 17 /**< Shift value for FRC_WCNTCMP3 */
+#define _FRC_SEQIF_WCNTCMP3_MASK 0x20000UL /**< Bit mask for FRC_WCNTCMP3 */
+#define _FRC_SEQIF_WCNTCMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_WCNTCMP3_DEFAULT (_FRC_SEQIF_WCNTCMP3_DEFAULT << 17) /**< Shifted mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_WCNTCMP4 (0x1UL << 18) /**< Word Counter Compare 4 Event */
+#define _FRC_SEQIF_WCNTCMP4_SHIFT 18 /**< Shift value for FRC_WCNTCMP4 */
+#define _FRC_SEQIF_WCNTCMP4_MASK 0x40000UL /**< Bit mask for FRC_WCNTCMP4 */
+#define _FRC_SEQIF_WCNTCMP4_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_WCNTCMP4_DEFAULT (_FRC_SEQIF_WCNTCMP4_DEFAULT << 18) /**< Shifted mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_BOISET (0x1UL << 19) /**< BOISET Event */
+#define _FRC_SEQIF_BOISET_SHIFT 19 /**< Shift value for FRC_BOISET */
+#define _FRC_SEQIF_BOISET_MASK 0x80000UL /**< Bit mask for FRC_BOISET */
+#define _FRC_SEQIF_BOISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_BOISET_DEFAULT (_FRC_SEQIF_BOISET_DEFAULT << 19) /**< Shifted mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_PKTBUFSTART (0x1UL << 20) /**< Packet Buffer Start */
+#define _FRC_SEQIF_PKTBUFSTART_SHIFT 20 /**< Shift value for FRC_PKTBUFSTART */
+#define _FRC_SEQIF_PKTBUFSTART_MASK 0x100000UL /**< Bit mask for FRC_PKTBUFSTART */
+#define _FRC_SEQIF_PKTBUFSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_PKTBUFSTART_DEFAULT (_FRC_SEQIF_PKTBUFSTART_DEFAULT << 20) /**< Shifted mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_PKTBUFTHRESHOLD (0x1UL << 21) /**< Packet Buffer Threshold */
+#define _FRC_SEQIF_PKTBUFTHRESHOLD_SHIFT 21 /**< Shift value for FRC_PKTBUFTHRESHOLD */
+#define _FRC_SEQIF_PKTBUFTHRESHOLD_MASK 0x200000UL /**< Bit mask for FRC_PKTBUFTHRESHOLD */
+#define _FRC_SEQIF_PKTBUFTHRESHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_PKTBUFTHRESHOLD_DEFAULT (_FRC_SEQIF_PKTBUFTHRESHOLD_DEFAULT << 21) /**< Shifted mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_RXRAWOF (0x1UL << 22) /**< RX raw FIFO overflow */
+#define _FRC_SEQIF_RXRAWOF_SHIFT 22 /**< Shift value for FRC_RXRAWOF */
+#define _FRC_SEQIF_RXRAWOF_MASK 0x400000UL /**< Bit mask for FRC_RXRAWOF */
+#define _FRC_SEQIF_RXRAWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_RXRAWOF_DEFAULT (_FRC_SEQIF_RXRAWOF_DEFAULT << 22) /**< Shifted mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_WCNTCMP5 (0x1UL << 23) /**< Word Counter Compare 5 Event */
+#define _FRC_SEQIF_WCNTCMP5_SHIFT 23 /**< Shift value for FRC_WCNTCMP5 */
+#define _FRC_SEQIF_WCNTCMP5_MASK 0x800000UL /**< Bit mask for FRC_WCNTCMP5 */
+#define _FRC_SEQIF_WCNTCMP5_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_WCNTCMP5_DEFAULT (_FRC_SEQIF_WCNTCMP5_DEFAULT << 23) /**< Shifted mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_FRAMEDETPAUSED (0x1UL << 24) /**< Frame detected pause event active */
+#define _FRC_SEQIF_FRAMEDETPAUSED_SHIFT 24 /**< Shift value for FRC_FRAMEDETPAUSED */
+#define _FRC_SEQIF_FRAMEDETPAUSED_MASK 0x1000000UL /**< Bit mask for FRC_FRAMEDETPAUSED */
+#define _FRC_SEQIF_FRAMEDETPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_FRAMEDETPAUSED_DEFAULT (_FRC_SEQIF_FRAMEDETPAUSED_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_INTERLEAVEWRITEPAUSED (0x1UL << 25) /**< Interleaver write pause event active */
+#define _FRC_SEQIF_INTERLEAVEWRITEPAUSED_SHIFT 25 /**< Shift value for FRC_INTERLEAVEWRITEPAUSED */
+#define _FRC_SEQIF_INTERLEAVEWRITEPAUSED_MASK 0x2000000UL /**< Bit mask for FRC_INTERLEAVEWRITEPAUSED */
+#define _FRC_SEQIF_INTERLEAVEWRITEPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_INTERLEAVEWRITEPAUSED_DEFAULT (_FRC_SEQIF_INTERLEAVEWRITEPAUSED_DEFAULT << 25) /**< Shifted mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_INTERLEAVEREADPAUSED (0x1UL << 26) /**< Interleaver read pause event active */
+#define _FRC_SEQIF_INTERLEAVEREADPAUSED_SHIFT 26 /**< Shift value for FRC_INTERLEAVEREADPAUSED */
+#define _FRC_SEQIF_INTERLEAVEREADPAUSED_MASK 0x4000000UL /**< Bit mask for FRC_INTERLEAVEREADPAUSED */
+#define _FRC_SEQIF_INTERLEAVEREADPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_INTERLEAVEREADPAUSED_DEFAULT (_FRC_SEQIF_INTERLEAVEREADPAUSED_DEFAULT << 26) /**< Shifted mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_TXSUBFRAMEPAUSED (0x1UL << 27) /**< Transmit subframe pause event active */
+#define _FRC_SEQIF_TXSUBFRAMEPAUSED_SHIFT 27 /**< Shift value for FRC_TXSUBFRAMEPAUSED */
+#define _FRC_SEQIF_TXSUBFRAMEPAUSED_MASK 0x8000000UL /**< Bit mask for FRC_TXSUBFRAMEPAUSED */
+#define _FRC_SEQIF_TXSUBFRAMEPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_TXSUBFRAMEPAUSED_DEFAULT (_FRC_SEQIF_TXSUBFRAMEPAUSED_DEFAULT << 27) /**< Shifted mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_CONVPAUSED (0x1UL << 28) /**< Convolutional coder pause event active */
+#define _FRC_SEQIF_CONVPAUSED_SHIFT 28 /**< Shift value for FRC_CONVPAUSED */
+#define _FRC_SEQIF_CONVPAUSED_MASK 0x10000000UL /**< Bit mask for FRC_CONVPAUSED */
+#define _FRC_SEQIF_CONVPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_CONVPAUSED_DEFAULT (_FRC_SEQIF_CONVPAUSED_DEFAULT << 28) /**< Shifted mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_RXWORD (0x1UL << 29) /**< Receive Word Interrupt Flag */
+#define _FRC_SEQIF_RXWORD_SHIFT 29 /**< Shift value for FRC_RXWORD */
+#define _FRC_SEQIF_RXWORD_MASK 0x20000000UL /**< Bit mask for FRC_RXWORD */
+#define _FRC_SEQIF_RXWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_RXWORD_DEFAULT (_FRC_SEQIF_RXWORD_DEFAULT << 29) /**< Shifted mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_TXWORD (0x1UL << 30) /**< Transmit Word Interrupt Flag */
+#define _FRC_SEQIF_TXWORD_SHIFT 30 /**< Shift value for FRC_TXWORD */
+#define _FRC_SEQIF_TXWORD_MASK 0x40000000UL /**< Bit mask for FRC_TXWORD */
+#define _FRC_SEQIF_TXWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_TXWORD_DEFAULT (_FRC_SEQIF_TXWORD_DEFAULT << 30) /**< Shifted mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_UARTERROR (0x1UL << 31) /**< Uart Error Interrupt Flag */
+#define _FRC_SEQIF_UARTERROR_SHIFT 31 /**< Shift value for FRC_UARTERROR */
+#define _FRC_SEQIF_UARTERROR_MASK 0x80000000UL /**< Bit mask for FRC_UARTERROR */
+#define _FRC_SEQIF_UARTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIF */
+#define FRC_SEQIF_UARTERROR_DEFAULT (_FRC_SEQIF_UARTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for FRC_SEQIF */
+
+/* Bit fields for FRC SEQIEN */
+#define _FRC_SEQIEN_RESETVALUE 0x00000000UL /**< Default value for FRC_SEQIEN */
+#define _FRC_SEQIEN_MASK 0xFFFFFFFFUL /**< Mask for FRC_SEQIEN */
+#define FRC_SEQIEN_TXDONE (0x1UL << 0) /**< TX Done Interrupt Enable */
+#define _FRC_SEQIEN_TXDONE_SHIFT 0 /**< Shift value for FRC_TXDONE */
+#define _FRC_SEQIEN_TXDONE_MASK 0x1UL /**< Bit mask for FRC_TXDONE */
+#define _FRC_SEQIEN_TXDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_TXDONE_DEFAULT (_FRC_SEQIEN_TXDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_TXAFTERFRAMEDONE (0x1UL << 1) /**< TX after frame Done Interrupt Enable */
+#define _FRC_SEQIEN_TXAFTERFRAMEDONE_SHIFT 1 /**< Shift value for FRC_TXAFTERFRAMEDONE */
+#define _FRC_SEQIEN_TXAFTERFRAMEDONE_MASK 0x2UL /**< Bit mask for FRC_TXAFTERFRAMEDONE */
+#define _FRC_SEQIEN_TXAFTERFRAMEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_TXAFTERFRAMEDONE_DEFAULT (_FRC_SEQIEN_TXAFTERFRAMEDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_TXABORTED (0x1UL << 2) /**< Transmit Aborted Interrupt Enable */
+#define _FRC_SEQIEN_TXABORTED_SHIFT 2 /**< Shift value for FRC_TXABORTED */
+#define _FRC_SEQIEN_TXABORTED_MASK 0x4UL /**< Bit mask for FRC_TXABORTED */
+#define _FRC_SEQIEN_TXABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_TXABORTED_DEFAULT (_FRC_SEQIEN_TXABORTED_DEFAULT << 2) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_TXUF (0x1UL << 3) /**< Transmit Underflow Interrupt Enable */
+#define _FRC_SEQIEN_TXUF_SHIFT 3 /**< Shift value for FRC_TXUF */
+#define _FRC_SEQIEN_TXUF_MASK 0x8UL /**< Bit mask for FRC_TXUF */
+#define _FRC_SEQIEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_TXUF_DEFAULT (_FRC_SEQIEN_TXUF_DEFAULT << 3) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_RXDONE (0x1UL << 4) /**< RX Done Interrupt Enable */
+#define _FRC_SEQIEN_RXDONE_SHIFT 4 /**< Shift value for FRC_RXDONE */
+#define _FRC_SEQIEN_RXDONE_MASK 0x10UL /**< Bit mask for FRC_RXDONE */
+#define _FRC_SEQIEN_RXDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_RXDONE_DEFAULT (_FRC_SEQIEN_RXDONE_DEFAULT << 4) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_RXABORTED (0x1UL << 5) /**< RX Aborted Interrupt Enable */
+#define _FRC_SEQIEN_RXABORTED_SHIFT 5 /**< Shift value for FRC_RXABORTED */
+#define _FRC_SEQIEN_RXABORTED_MASK 0x20UL /**< Bit mask for FRC_RXABORTED */
+#define _FRC_SEQIEN_RXABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_RXABORTED_DEFAULT (_FRC_SEQIEN_RXABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_FRAMEERROR (0x1UL << 6) /**< Frame Error Interrupt Enable */
+#define _FRC_SEQIEN_FRAMEERROR_SHIFT 6 /**< Shift value for FRC_FRAMEERROR */
+#define _FRC_SEQIEN_FRAMEERROR_MASK 0x40UL /**< Bit mask for FRC_FRAMEERROR */
+#define _FRC_SEQIEN_FRAMEERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_FRAMEERROR_DEFAULT (_FRC_SEQIEN_FRAMEERROR_DEFAULT << 6) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_BLOCKERROR (0x1UL << 7) /**< Block Error Interrupt Enable */
+#define _FRC_SEQIEN_BLOCKERROR_SHIFT 7 /**< Shift value for FRC_BLOCKERROR */
+#define _FRC_SEQIEN_BLOCKERROR_MASK 0x80UL /**< Bit mask for FRC_BLOCKERROR */
+#define _FRC_SEQIEN_BLOCKERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_BLOCKERROR_DEFAULT (_FRC_SEQIEN_BLOCKERROR_DEFAULT << 7) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_RXOF (0x1UL << 8) /**< Receive Overflow Interrupt Enable */
+#define _FRC_SEQIEN_RXOF_SHIFT 8 /**< Shift value for FRC_RXOF */
+#define _FRC_SEQIEN_RXOF_MASK 0x100UL /**< Bit mask for FRC_RXOF */
+#define _FRC_SEQIEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_RXOF_DEFAULT (_FRC_SEQIEN_RXOF_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_WCNTCMP0 (0x1UL << 9) /**< Word Counter Compare 0 Enable */
+#define _FRC_SEQIEN_WCNTCMP0_SHIFT 9 /**< Shift value for FRC_WCNTCMP0 */
+#define _FRC_SEQIEN_WCNTCMP0_MASK 0x200UL /**< Bit mask for FRC_WCNTCMP0 */
+#define _FRC_SEQIEN_WCNTCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_WCNTCMP0_DEFAULT (_FRC_SEQIEN_WCNTCMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_WCNTCMP1 (0x1UL << 10) /**< Word Counter Compare 1 Enable */
+#define _FRC_SEQIEN_WCNTCMP1_SHIFT 10 /**< Shift value for FRC_WCNTCMP1 */
+#define _FRC_SEQIEN_WCNTCMP1_MASK 0x400UL /**< Bit mask for FRC_WCNTCMP1 */
+#define _FRC_SEQIEN_WCNTCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_WCNTCMP1_DEFAULT (_FRC_SEQIEN_WCNTCMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_WCNTCMP2 (0x1UL << 11) /**< Word Counter Compare 2 Enable */
+#define _FRC_SEQIEN_WCNTCMP2_SHIFT 11 /**< Shift value for FRC_WCNTCMP2 */
+#define _FRC_SEQIEN_WCNTCMP2_MASK 0x800UL /**< Bit mask for FRC_WCNTCMP2 */
+#define _FRC_SEQIEN_WCNTCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_WCNTCMP2_DEFAULT (_FRC_SEQIEN_WCNTCMP2_DEFAULT << 11) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_ADDRERROR (0x1UL << 12) /**< Receive address error enable */
+#define _FRC_SEQIEN_ADDRERROR_SHIFT 12 /**< Shift value for FRC_ADDRERROR */
+#define _FRC_SEQIEN_ADDRERROR_MASK 0x1000UL /**< Bit mask for FRC_ADDRERROR */
+#define _FRC_SEQIEN_ADDRERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_ADDRERROR_DEFAULT (_FRC_SEQIEN_ADDRERROR_DEFAULT << 12) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_BUSERROR (0x1UL << 13) /**< Bus error enable */
+#define _FRC_SEQIEN_BUSERROR_SHIFT 13 /**< Shift value for FRC_BUSERROR */
+#define _FRC_SEQIEN_BUSERROR_MASK 0x2000UL /**< Bit mask for FRC_BUSERROR */
+#define _FRC_SEQIEN_BUSERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_BUSERROR_DEFAULT (_FRC_SEQIEN_BUSERROR_DEFAULT << 13) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_RXRAWEVENT (0x1UL << 14) /**< Receiver raw data enable */
+#define _FRC_SEQIEN_RXRAWEVENT_SHIFT 14 /**< Shift value for FRC_RXRAWEVENT */
+#define _FRC_SEQIEN_RXRAWEVENT_MASK 0x4000UL /**< Bit mask for FRC_RXRAWEVENT */
+#define _FRC_SEQIEN_RXRAWEVENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_RXRAWEVENT_DEFAULT (_FRC_SEQIEN_RXRAWEVENT_DEFAULT << 14) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_TXRAWEVENT (0x1UL << 15) /**< Transmit raw data enable */
+#define _FRC_SEQIEN_TXRAWEVENT_SHIFT 15 /**< Shift value for FRC_TXRAWEVENT */
+#define _FRC_SEQIEN_TXRAWEVENT_MASK 0x8000UL /**< Bit mask for FRC_TXRAWEVENT */
+#define _FRC_SEQIEN_TXRAWEVENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_TXRAWEVENT_DEFAULT (_FRC_SEQIEN_TXRAWEVENT_DEFAULT << 15) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_SNIFFOF (0x1UL << 16) /**< Data sniffer overflow enable */
+#define _FRC_SEQIEN_SNIFFOF_SHIFT 16 /**< Shift value for FRC_SNIFFOF */
+#define _FRC_SEQIEN_SNIFFOF_MASK 0x10000UL /**< Bit mask for FRC_SNIFFOF */
+#define _FRC_SEQIEN_SNIFFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_SNIFFOF_DEFAULT (_FRC_SEQIEN_SNIFFOF_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_WCNTCMP3 (0x1UL << 17) /**< Word Counter Compare 3 Enable */
+#define _FRC_SEQIEN_WCNTCMP3_SHIFT 17 /**< Shift value for FRC_WCNTCMP3 */
+#define _FRC_SEQIEN_WCNTCMP3_MASK 0x20000UL /**< Bit mask for FRC_WCNTCMP3 */
+#define _FRC_SEQIEN_WCNTCMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_WCNTCMP3_DEFAULT (_FRC_SEQIEN_WCNTCMP3_DEFAULT << 17) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_WCNTCMP4 (0x1UL << 18) /**< Word Counter Compare 4 Enable */
+#define _FRC_SEQIEN_WCNTCMP4_SHIFT 18 /**< Shift value for FRC_WCNTCMP4 */
+#define _FRC_SEQIEN_WCNTCMP4_MASK 0x40000UL /**< Bit mask for FRC_WCNTCMP4 */
+#define _FRC_SEQIEN_WCNTCMP4_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_WCNTCMP4_DEFAULT (_FRC_SEQIEN_WCNTCMP4_DEFAULT << 18) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_BOISET (0x1UL << 19) /**< Word Counter Compare 2 Enable */
+#define _FRC_SEQIEN_BOISET_SHIFT 19 /**< Shift value for FRC_BOISET */
+#define _FRC_SEQIEN_BOISET_MASK 0x80000UL /**< Bit mask for FRC_BOISET */
+#define _FRC_SEQIEN_BOISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_BOISET_DEFAULT (_FRC_SEQIEN_BOISET_DEFAULT << 19) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_PKTBUFSTART (0x1UL << 20) /**< PKTBUFSTART Enable */
+#define _FRC_SEQIEN_PKTBUFSTART_SHIFT 20 /**< Shift value for FRC_PKTBUFSTART */
+#define _FRC_SEQIEN_PKTBUFSTART_MASK 0x100000UL /**< Bit mask for FRC_PKTBUFSTART */
+#define _FRC_SEQIEN_PKTBUFSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_PKTBUFSTART_DEFAULT (_FRC_SEQIEN_PKTBUFSTART_DEFAULT << 20) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_PKTBUFTHRESHOLD (0x1UL << 21) /**< PKTBUFTHRESHOLD Enable */
+#define _FRC_SEQIEN_PKTBUFTHRESHOLD_SHIFT 21 /**< Shift value for FRC_PKTBUFTHRESHOLD */
+#define _FRC_SEQIEN_PKTBUFTHRESHOLD_MASK 0x200000UL /**< Bit mask for FRC_PKTBUFTHRESHOLD */
+#define _FRC_SEQIEN_PKTBUFTHRESHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_PKTBUFTHRESHOLD_DEFAULT (_FRC_SEQIEN_PKTBUFTHRESHOLD_DEFAULT << 21) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_RXRAWOF (0x1UL << 22) /**< RXRAWOF Enable */
+#define _FRC_SEQIEN_RXRAWOF_SHIFT 22 /**< Shift value for FRC_RXRAWOF */
+#define _FRC_SEQIEN_RXRAWOF_MASK 0x400000UL /**< Bit mask for FRC_RXRAWOF */
+#define _FRC_SEQIEN_RXRAWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_RXRAWOF_DEFAULT (_FRC_SEQIEN_RXRAWOF_DEFAULT << 22) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_WCNTCMP5 (0x1UL << 23) /**< Word Counter Compare 5 Enable */
+#define _FRC_SEQIEN_WCNTCMP5_SHIFT 23 /**< Shift value for FRC_WCNTCMP5 */
+#define _FRC_SEQIEN_WCNTCMP5_MASK 0x800000UL /**< Bit mask for FRC_WCNTCMP5 */
+#define _FRC_SEQIEN_WCNTCMP5_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_WCNTCMP5_DEFAULT (_FRC_SEQIEN_WCNTCMP5_DEFAULT << 23) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_FRAMEDETPAUSED (0x1UL << 24) /**< Frame detected pause event enable */
+#define _FRC_SEQIEN_FRAMEDETPAUSED_SHIFT 24 /**< Shift value for FRC_FRAMEDETPAUSED */
+#define _FRC_SEQIEN_FRAMEDETPAUSED_MASK 0x1000000UL /**< Bit mask for FRC_FRAMEDETPAUSED */
+#define _FRC_SEQIEN_FRAMEDETPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_FRAMEDETPAUSED_DEFAULT (_FRC_SEQIEN_FRAMEDETPAUSED_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_INTERLEAVEWRITEPAUSED (0x1UL << 25) /**< Interleaver write pause event enable */
+#define _FRC_SEQIEN_INTERLEAVEWRITEPAUSED_SHIFT 25 /**< Shift value for FRC_INTERLEAVEWRITEPAUSED */
+#define _FRC_SEQIEN_INTERLEAVEWRITEPAUSED_MASK 0x2000000UL /**< Bit mask for FRC_INTERLEAVEWRITEPAUSED */
+#define _FRC_SEQIEN_INTERLEAVEWRITEPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_INTERLEAVEWRITEPAUSED_DEFAULT (_FRC_SEQIEN_INTERLEAVEWRITEPAUSED_DEFAULT << 25) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_INTERLEAVEREADPAUSED (0x1UL << 26) /**< Interleaver read pause event enable */
+#define _FRC_SEQIEN_INTERLEAVEREADPAUSED_SHIFT 26 /**< Shift value for FRC_INTERLEAVEREADPAUSED */
+#define _FRC_SEQIEN_INTERLEAVEREADPAUSED_MASK 0x4000000UL /**< Bit mask for FRC_INTERLEAVEREADPAUSED */
+#define _FRC_SEQIEN_INTERLEAVEREADPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_INTERLEAVEREADPAUSED_DEFAULT (_FRC_SEQIEN_INTERLEAVEREADPAUSED_DEFAULT << 26) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_TXSUBFRAMEPAUSED (0x1UL << 27) /**< Transmit subframe pause event enable */
+#define _FRC_SEQIEN_TXSUBFRAMEPAUSED_SHIFT 27 /**< Shift value for FRC_TXSUBFRAMEPAUSED */
+#define _FRC_SEQIEN_TXSUBFRAMEPAUSED_MASK 0x8000000UL /**< Bit mask for FRC_TXSUBFRAMEPAUSED */
+#define _FRC_SEQIEN_TXSUBFRAMEPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_TXSUBFRAMEPAUSED_DEFAULT (_FRC_SEQIEN_TXSUBFRAMEPAUSED_DEFAULT << 27) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_CONVPAUSED (0x1UL << 28) /**< Convolutional coder pause event enable */
+#define _FRC_SEQIEN_CONVPAUSED_SHIFT 28 /**< Shift value for FRC_CONVPAUSED */
+#define _FRC_SEQIEN_CONVPAUSED_MASK 0x10000000UL /**< Bit mask for FRC_CONVPAUSED */
+#define _FRC_SEQIEN_CONVPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_CONVPAUSED_DEFAULT (_FRC_SEQIEN_CONVPAUSED_DEFAULT << 28) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_RXWORD (0x1UL << 29) /**< Receive Word Interrupt Enable */
+#define _FRC_SEQIEN_RXWORD_SHIFT 29 /**< Shift value for FRC_RXWORD */
+#define _FRC_SEQIEN_RXWORD_MASK 0x20000000UL /**< Bit mask for FRC_RXWORD */
+#define _FRC_SEQIEN_RXWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_RXWORD_DEFAULT (_FRC_SEQIEN_RXWORD_DEFAULT << 29) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_TXWORD (0x1UL << 30) /**< Transmit Word Interrupt Enable */
+#define _FRC_SEQIEN_TXWORD_SHIFT 30 /**< Shift value for FRC_TXWORD */
+#define _FRC_SEQIEN_TXWORD_MASK 0x40000000UL /**< Bit mask for FRC_TXWORD */
+#define _FRC_SEQIEN_TXWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_TXWORD_DEFAULT (_FRC_SEQIEN_TXWORD_DEFAULT << 30) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_UARTERROR (0x1UL << 31) /**< UART Error Interrupt Enable */
+#define _FRC_SEQIEN_UARTERROR_SHIFT 31 /**< Shift value for FRC_UARTERROR */
+#define _FRC_SEQIEN_UARTERROR_MASK 0x80000000UL /**< Bit mask for FRC_UARTERROR */
+#define _FRC_SEQIEN_UARTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_SEQIEN */
+#define FRC_SEQIEN_UARTERROR_DEFAULT (_FRC_SEQIEN_UARTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for FRC_SEQIEN */
+
+/* Bit fields for FRC WCNTCMP3 */
+#define _FRC_WCNTCMP3_RESETVALUE 0x00000000UL /**< Default value for FRC_WCNTCMP3 */
+#define _FRC_WCNTCMP3_MASK 0x00000FFFUL /**< Mask for FRC_WCNTCMP3 */
+#define _FRC_WCNTCMP3_SUPPLENFIELDLOC_SHIFT 0 /**< Shift value for FRC_SUPPLENFIELDLOC */
+#define _FRC_WCNTCMP3_SUPPLENFIELDLOC_MASK 0xFFFUL /**< Bit mask for FRC_SUPPLENFIELDLOC */
+#define _FRC_WCNTCMP3_SUPPLENFIELDLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_WCNTCMP3 */
+#define FRC_WCNTCMP3_SUPPLENFIELDLOC_DEFAULT (_FRC_WCNTCMP3_SUPPLENFIELDLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_WCNTCMP3 */
+
+/* Bit fields for FRC BOICTRL */
+#define _FRC_BOICTRL_RESETVALUE 0x00000000UL /**< Default value for FRC_BOICTRL */
+#define _FRC_BOICTRL_MASK 0x0001FFFFUL /**< Mask for FRC_BOICTRL */
+#define FRC_BOICTRL_BOIEN (0x1UL << 0) /**< BOI EN */
+#define _FRC_BOICTRL_BOIEN_SHIFT 0 /**< Shift value for FRC_BOIEN */
+#define _FRC_BOICTRL_BOIEN_MASK 0x1UL /**< Bit mask for FRC_BOIEN */
+#define _FRC_BOICTRL_BOIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_BOICTRL */
+#define FRC_BOICTRL_BOIEN_DEFAULT (_FRC_BOICTRL_BOIEN_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_BOICTRL */
+#define _FRC_BOICTRL_BOIFIELDLOC_SHIFT 1 /**< Shift value for FRC_BOIFIELDLOC */
+#define _FRC_BOICTRL_BOIFIELDLOC_MASK 0x1FFEUL /**< Bit mask for FRC_BOIFIELDLOC */
+#define _FRC_BOICTRL_BOIFIELDLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_BOICTRL */
+#define FRC_BOICTRL_BOIFIELDLOC_DEFAULT (_FRC_BOICTRL_BOIFIELDLOC_DEFAULT << 1) /**< Shifted mode DEFAULT for FRC_BOICTRL */
+#define _FRC_BOICTRL_BOIBITPOS_SHIFT 13 /**< Shift value for FRC_BOIBITPOS */
+#define _FRC_BOICTRL_BOIBITPOS_MASK 0xE000UL /**< Bit mask for FRC_BOIBITPOS */
+#define _FRC_BOICTRL_BOIBITPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_BOICTRL */
+#define FRC_BOICTRL_BOIBITPOS_DEFAULT (_FRC_BOICTRL_BOIBITPOS_DEFAULT << 13) /**< Shifted mode DEFAULT for FRC_BOICTRL */
+#define FRC_BOICTRL_BOIMATCHVAL (0x1UL << 16) /**< BOI match value */
+#define _FRC_BOICTRL_BOIMATCHVAL_SHIFT 16 /**< Shift value for FRC_BOIMATCHVAL */
+#define _FRC_BOICTRL_BOIMATCHVAL_MASK 0x10000UL /**< Bit mask for FRC_BOIMATCHVAL */
+#define _FRC_BOICTRL_BOIMATCHVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_BOICTRL */
+#define FRC_BOICTRL_BOIMATCHVAL_DEFAULT (_FRC_BOICTRL_BOIMATCHVAL_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_BOICTRL */
+
+/* Bit fields for FRC DSLCTRL */
+#define _FRC_DSLCTRL_RESETVALUE 0x00000000UL /**< Default value for FRC_DSLCTRL */
+#define _FRC_DSLCTRL_MASK 0x7FFFFF7FUL /**< Mask for FRC_DSLCTRL */
+#define _FRC_DSLCTRL_DSLMODE_SHIFT 0 /**< Shift value for FRC_DSLMODE */
+#define _FRC_DSLCTRL_DSLMODE_MASK 0x7UL /**< Bit mask for FRC_DSLMODE */
+#define _FRC_DSLCTRL_DSLMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DSLCTRL */
+#define _FRC_DSLCTRL_DSLMODE_DISABLE 0x00000000UL /**< Mode DISABLE for FRC_DSLCTRL */
+#define _FRC_DSLCTRL_DSLMODE_SINGLEBYTE 0x00000001UL /**< Mode SINGLEBYTE for FRC_DSLCTRL */
+#define _FRC_DSLCTRL_DSLMODE_SINGLEBYTEMSB 0x00000002UL /**< Mode SINGLEBYTEMSB for FRC_DSLCTRL */
+#define _FRC_DSLCTRL_DSLMODE_DUALBYTELSBFIRST 0x00000003UL /**< Mode DUALBYTELSBFIRST for FRC_DSLCTRL */
+#define _FRC_DSLCTRL_DSLMODE_DUALBYTEMSBFIRST 0x00000004UL /**< Mode DUALBYTEMSBFIRST for FRC_DSLCTRL */
+#define _FRC_DSLCTRL_DSLMODE_INFINITE 0x00000005UL /**< Mode INFINITE for FRC_DSLCTRL */
+#define _FRC_DSLCTRL_DSLMODE_BLOCKERROR 0x00000006UL /**< Mode BLOCKERROR for FRC_DSLCTRL */
+#define FRC_DSLCTRL_DSLMODE_DEFAULT (_FRC_DSLCTRL_DSLMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_DSLCTRL */
+#define FRC_DSLCTRL_DSLMODE_DISABLE (_FRC_DSLCTRL_DSLMODE_DISABLE << 0) /**< Shifted mode DISABLE for FRC_DSLCTRL */
+#define FRC_DSLCTRL_DSLMODE_SINGLEBYTE (_FRC_DSLCTRL_DSLMODE_SINGLEBYTE << 0) /**< Shifted mode SINGLEBYTE for FRC_DSLCTRL */
+#define FRC_DSLCTRL_DSLMODE_SINGLEBYTEMSB (_FRC_DSLCTRL_DSLMODE_SINGLEBYTEMSB << 0) /**< Shifted mode SINGLEBYTEMSB for FRC_DSLCTRL */
+#define FRC_DSLCTRL_DSLMODE_DUALBYTELSBFIRST (_FRC_DSLCTRL_DSLMODE_DUALBYTELSBFIRST << 0) /**< Shifted mode DUALBYTELSBFIRST for FRC_DSLCTRL*/
+#define FRC_DSLCTRL_DSLMODE_DUALBYTEMSBFIRST (_FRC_DSLCTRL_DSLMODE_DUALBYTEMSBFIRST << 0) /**< Shifted mode DUALBYTEMSBFIRST for FRC_DSLCTRL*/
+#define FRC_DSLCTRL_DSLMODE_INFINITE (_FRC_DSLCTRL_DSLMODE_INFINITE << 0) /**< Shifted mode INFINITE for FRC_DSLCTRL */
+#define FRC_DSLCTRL_DSLMODE_BLOCKERROR (_FRC_DSLCTRL_DSLMODE_BLOCKERROR << 0) /**< Shifted mode BLOCKERROR for FRC_DSLCTRL */
+#define FRC_DSLCTRL_DSLBITORDER (0x1UL << 3) /**< Dynamic Frame Length Bit order */
+#define _FRC_DSLCTRL_DSLBITORDER_SHIFT 3 /**< Shift value for FRC_DSLBITORDER */
+#define _FRC_DSLCTRL_DSLBITORDER_MASK 0x8UL /**< Bit mask for FRC_DSLBITORDER */
+#define _FRC_DSLCTRL_DSLBITORDER_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DSLCTRL */
+#define _FRC_DSLCTRL_DSLBITORDER_NORMAL 0x00000000UL /**< Mode NORMAL for FRC_DSLCTRL */
+#define _FRC_DSLCTRL_DSLBITORDER_REVERSE 0x00000001UL /**< Mode REVERSE for FRC_DSLCTRL */
+#define FRC_DSLCTRL_DSLBITORDER_DEFAULT (_FRC_DSLCTRL_DSLBITORDER_DEFAULT << 3) /**< Shifted mode DEFAULT for FRC_DSLCTRL */
+#define FRC_DSLCTRL_DSLBITORDER_NORMAL (_FRC_DSLCTRL_DSLBITORDER_NORMAL << 3) /**< Shifted mode NORMAL for FRC_DSLCTRL */
+#define FRC_DSLCTRL_DSLBITORDER_REVERSE (_FRC_DSLCTRL_DSLBITORDER_REVERSE << 3) /**< Shifted mode REVERSE for FRC_DSLCTRL */
+#define _FRC_DSLCTRL_DSLSHIFT_SHIFT 4 /**< Shift value for FRC_DSLSHIFT */
+#define _FRC_DSLCTRL_DSLSHIFT_MASK 0x70UL /**< Bit mask for FRC_DSLSHIFT */
+#define _FRC_DSLCTRL_DSLSHIFT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DSLCTRL */
+#define FRC_DSLCTRL_DSLSHIFT_DEFAULT (_FRC_DSLCTRL_DSLSHIFT_DEFAULT << 4) /**< Shifted mode DEFAULT for FRC_DSLCTRL */
+#define _FRC_DSLCTRL_DSLOFFSET_SHIFT 8 /**< Shift value for FRC_DSLOFFSET */
+#define _FRC_DSLCTRL_DSLOFFSET_MASK 0xFF00UL /**< Bit mask for FRC_DSLOFFSET */
+#define _FRC_DSLCTRL_DSLOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DSLCTRL */
+#define FRC_DSLCTRL_DSLOFFSET_DEFAULT (_FRC_DSLCTRL_DSLOFFSET_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_DSLCTRL */
+#define _FRC_DSLCTRL_DSLBITS_SHIFT 16 /**< Shift value for FRC_DSLBITS */
+#define _FRC_DSLCTRL_DSLBITS_MASK 0xF0000UL /**< Bit mask for FRC_DSLBITS */
+#define _FRC_DSLCTRL_DSLBITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DSLCTRL */
+#define FRC_DSLCTRL_DSLBITS_DEFAULT (_FRC_DSLCTRL_DSLBITS_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_DSLCTRL */
+#define _FRC_DSLCTRL_DSLMINLENGTH_SHIFT 20 /**< Shift value for FRC_DSLMINLENGTH */
+#define _FRC_DSLCTRL_DSLMINLENGTH_MASK 0xF00000UL /**< Bit mask for FRC_DSLMINLENGTH */
+#define _FRC_DSLCTRL_DSLMINLENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DSLCTRL */
+#define FRC_DSLCTRL_DSLMINLENGTH_DEFAULT (_FRC_DSLCTRL_DSLMINLENGTH_DEFAULT << 20) /**< Shifted mode DEFAULT for FRC_DSLCTRL */
+#define _FRC_DSLCTRL_RXSUPRECEPMODE_SHIFT 24 /**< Shift value for FRC_RXSUPRECEPMODE */
+#define _FRC_DSLCTRL_RXSUPRECEPMODE_MASK 0x7000000UL /**< Bit mask for FRC_RXSUPRECEPMODE */
+#define _FRC_DSLCTRL_RXSUPRECEPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DSLCTRL */
+#define _FRC_DSLCTRL_RXSUPRECEPMODE_NOSUP 0x00000000UL /**< Mode NOSUP for FRC_DSLCTRL */
+#define _FRC_DSLCTRL_RXSUPRECEPMODE_BOIDSLBASED 0x00000001UL /**< Mode BOIDSLBASED for FRC_DSLCTRL */
+#define _FRC_DSLCTRL_RXSUPRECEPMODE_BOIFIXEDSLBASED 0x00000002UL /**< Mode BOIFIXEDSLBASED for FRC_DSLCTRL */
+#define _FRC_DSLCTRL_RXSUPRECEPMODE_DSLBASED 0x00000003UL /**< Mode DSLBASED for FRC_DSLCTRL */
+#define _FRC_DSLCTRL_RXSUPRECEPMODE_FIXEDSLBASED 0x00000004UL /**< Mode FIXEDSLBASED for FRC_DSLCTRL */
+#define FRC_DSLCTRL_RXSUPRECEPMODE_DEFAULT (_FRC_DSLCTRL_RXSUPRECEPMODE_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_DSLCTRL */
+#define FRC_DSLCTRL_RXSUPRECEPMODE_NOSUP (_FRC_DSLCTRL_RXSUPRECEPMODE_NOSUP << 24) /**< Shifted mode NOSUP for FRC_DSLCTRL */
+#define FRC_DSLCTRL_RXSUPRECEPMODE_BOIDSLBASED (_FRC_DSLCTRL_RXSUPRECEPMODE_BOIDSLBASED << 24) /**< Shifted mode BOIDSLBASED for FRC_DSLCTRL */
+#define FRC_DSLCTRL_RXSUPRECEPMODE_BOIFIXEDSLBASED (_FRC_DSLCTRL_RXSUPRECEPMODE_BOIFIXEDSLBASED << 24) /**< Shifted mode BOIFIXEDSLBASED for FRC_DSLCTRL*/
+#define FRC_DSLCTRL_RXSUPRECEPMODE_DSLBASED (_FRC_DSLCTRL_RXSUPRECEPMODE_DSLBASED << 24) /**< Shifted mode DSLBASED for FRC_DSLCTRL */
+#define FRC_DSLCTRL_RXSUPRECEPMODE_FIXEDSLBASED (_FRC_DSLCTRL_RXSUPRECEPMODE_FIXEDSLBASED << 24) /**< Shifted mode FIXEDSLBASED for FRC_DSLCTRL */
+#define FRC_DSLCTRL_STORESUP (0x1UL << 27) /**< Store SUPP in BUFC */
+#define _FRC_DSLCTRL_STORESUP_SHIFT 27 /**< Shift value for FRC_STORESUP */
+#define _FRC_DSLCTRL_STORESUP_MASK 0x8000000UL /**< Bit mask for FRC_STORESUP */
+#define _FRC_DSLCTRL_STORESUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DSLCTRL */
+#define FRC_DSLCTRL_STORESUP_DEFAULT (_FRC_DSLCTRL_STORESUP_DEFAULT << 27) /**< Shifted mode DEFAULT for FRC_DSLCTRL */
+#define _FRC_DSLCTRL_SUPSHFFACTOR_SHIFT 28 /**< Shift value for FRC_SUPSHFFACTOR */
+#define _FRC_DSLCTRL_SUPSHFFACTOR_MASK 0x70000000UL /**< Bit mask for FRC_SUPSHFFACTOR */
+#define _FRC_DSLCTRL_SUPSHFFACTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_DSLCTRL */
+#define FRC_DSLCTRL_SUPSHFFACTOR_DEFAULT (_FRC_DSLCTRL_SUPSHFFACTOR_DEFAULT << 28) /**< Shifted mode DEFAULT for FRC_DSLCTRL */
+
+/* Bit fields for FRC WCNTCMP4 */
+#define _FRC_WCNTCMP4_RESETVALUE 0x00000000UL /**< Default value for FRC_WCNTCMP4 */
+#define _FRC_WCNTCMP4_MASK 0x00000FFFUL /**< Mask for FRC_WCNTCMP4 */
+#define _FRC_WCNTCMP4_SUPPLENGTH_SHIFT 0 /**< Shift value for FRC_SUPPLENGTH */
+#define _FRC_WCNTCMP4_SUPPLENGTH_MASK 0xFFFUL /**< Bit mask for FRC_SUPPLENGTH */
+#define _FRC_WCNTCMP4_SUPPLENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_WCNTCMP4 */
+#define FRC_WCNTCMP4_SUPPLENGTH_DEFAULT (_FRC_WCNTCMP4_SUPPLENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_WCNTCMP4 */
+
+/* Bit fields for FRC WCNTCMP5 */
+#define _FRC_WCNTCMP5_RESETVALUE 0x00000000UL /**< Default value for FRC_WCNTCMP5 */
+#define _FRC_WCNTCMP5_MASK 0x00000FFFUL /**< Mask for FRC_WCNTCMP5 */
+#define _FRC_WCNTCMP5_RXPAUSELOC_SHIFT 0 /**< Shift value for FRC_RXPAUSELOC */
+#define _FRC_WCNTCMP5_RXPAUSELOC_MASK 0xFFFUL /**< Bit mask for FRC_RXPAUSELOC */
+#define _FRC_WCNTCMP5_RXPAUSELOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_WCNTCMP5 */
+#define FRC_WCNTCMP5_RXPAUSELOC_DEFAULT (_FRC_WCNTCMP5_RXPAUSELOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_WCNTCMP5 */
+
+/* Bit fields for FRC PKTBUFCTRL */
+#define _FRC_PKTBUFCTRL_RESETVALUE 0x00000000UL /**< Default value for FRC_PKTBUFCTRL */
+#define _FRC_PKTBUFCTRL_MASK 0x0303FFFFUL /**< Mask for FRC_PKTBUFCTRL */
+#define _FRC_PKTBUFCTRL_PKTBUFSTARTLOC_SHIFT 0 /**< Shift value for FRC_PKTBUFSTARTLOC */
+#define _FRC_PKTBUFCTRL_PKTBUFSTARTLOC_MASK 0xFFFUL /**< Bit mask for FRC_PKTBUFSTARTLOC */
+#define _FRC_PKTBUFCTRL_PKTBUFSTARTLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUFCTRL */
+#define FRC_PKTBUFCTRL_PKTBUFSTARTLOC_DEFAULT (_FRC_PKTBUFCTRL_PKTBUFSTARTLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PKTBUFCTRL */
+#define _FRC_PKTBUFCTRL_PKTBUFTHRESHOLD_SHIFT 12 /**< Shift value for FRC_PKTBUFTHRESHOLD */
+#define _FRC_PKTBUFCTRL_PKTBUFTHRESHOLD_MASK 0x3F000UL /**< Bit mask for FRC_PKTBUFTHRESHOLD */
+#define _FRC_PKTBUFCTRL_PKTBUFTHRESHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUFCTRL */
+#define FRC_PKTBUFCTRL_PKTBUFTHRESHOLD_DEFAULT (_FRC_PKTBUFCTRL_PKTBUFTHRESHOLD_DEFAULT << 12) /**< Shifted mode DEFAULT for FRC_PKTBUFCTRL */
+#define FRC_PKTBUFCTRL_PKTBUFTHRESHOLDEN (0x1UL << 24) /**< Packet Buffer Threshold Enable */
+#define _FRC_PKTBUFCTRL_PKTBUFTHRESHOLDEN_SHIFT 24 /**< Shift value for FRC_PKTBUFTHRESHOLDEN */
+#define _FRC_PKTBUFCTRL_PKTBUFTHRESHOLDEN_MASK 0x1000000UL /**< Bit mask for FRC_PKTBUFTHRESHOLDEN */
+#define _FRC_PKTBUFCTRL_PKTBUFTHRESHOLDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUFCTRL */
+#define FRC_PKTBUFCTRL_PKTBUFTHRESHOLDEN_DEFAULT (_FRC_PKTBUFCTRL_PKTBUFTHRESHOLDEN_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_PKTBUFCTRL */
+#define FRC_PKTBUFCTRL_PKTBUFSTOP (0x1UL << 25) /**< Packet Buffer stop receiving command */
+#define _FRC_PKTBUFCTRL_PKTBUFSTOP_SHIFT 25 /**< Shift value for FRC_PKTBUFSTOP */
+#define _FRC_PKTBUFCTRL_PKTBUFSTOP_MASK 0x2000000UL /**< Bit mask for FRC_PKTBUFSTOP */
+#define _FRC_PKTBUFCTRL_PKTBUFSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUFCTRL */
+#define FRC_PKTBUFCTRL_PKTBUFSTOP_DEFAULT (_FRC_PKTBUFCTRL_PKTBUFSTOP_DEFAULT << 25) /**< Shifted mode DEFAULT for FRC_PKTBUFCTRL */
+
+/* Bit fields for FRC PKTBUFSTATUS */
+#define _FRC_PKTBUFSTATUS_RESETVALUE 0x00000000UL /**< Default value for FRC_PKTBUFSTATUS */
+#define _FRC_PKTBUFSTATUS_MASK 0x0000003FUL /**< Mask for FRC_PKTBUFSTATUS */
+#define _FRC_PKTBUFSTATUS_PKTBUFCOUNT_SHIFT 0 /**< Shift value for FRC_PKTBUFCOUNT */
+#define _FRC_PKTBUFSTATUS_PKTBUFCOUNT_MASK 0x3FUL /**< Bit mask for FRC_PKTBUFCOUNT */
+#define _FRC_PKTBUFSTATUS_PKTBUFCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUFSTATUS */
+#define FRC_PKTBUFSTATUS_PKTBUFCOUNT_DEFAULT (_FRC_PKTBUFSTATUS_PKTBUFCOUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PKTBUFSTATUS */
+
+/* Bit fields for FRC PKTBUF0 */
+#define _FRC_PKTBUF0_RESETVALUE 0x00000000UL /**< Default value for FRC_PKTBUF0 */
+#define _FRC_PKTBUF0_MASK 0xFFFFFFFFUL /**< Mask for FRC_PKTBUF0 */
+#define _FRC_PKTBUF0_PKTBUF0_SHIFT 0 /**< Shift value for FRC_PKTBUF0 */
+#define _FRC_PKTBUF0_PKTBUF0_MASK 0xFFUL /**< Bit mask for FRC_PKTBUF0 */
+#define _FRC_PKTBUF0_PKTBUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF0 */
+#define FRC_PKTBUF0_PKTBUF0_DEFAULT (_FRC_PKTBUF0_PKTBUF0_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PKTBUF0 */
+#define _FRC_PKTBUF0_PKTBUF1_SHIFT 8 /**< Shift value for FRC_PKTBUF1 */
+#define _FRC_PKTBUF0_PKTBUF1_MASK 0xFF00UL /**< Bit mask for FRC_PKTBUF1 */
+#define _FRC_PKTBUF0_PKTBUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF0 */
+#define FRC_PKTBUF0_PKTBUF1_DEFAULT (_FRC_PKTBUF0_PKTBUF1_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_PKTBUF0 */
+#define _FRC_PKTBUF0_PKTBUF2_SHIFT 16 /**< Shift value for FRC_PKTBUF2 */
+#define _FRC_PKTBUF0_PKTBUF2_MASK 0xFF0000UL /**< Bit mask for FRC_PKTBUF2 */
+#define _FRC_PKTBUF0_PKTBUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF0 */
+#define FRC_PKTBUF0_PKTBUF2_DEFAULT (_FRC_PKTBUF0_PKTBUF2_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_PKTBUF0 */
+#define _FRC_PKTBUF0_PKTBUF3_SHIFT 24 /**< Shift value for FRC_PKTBUF3 */
+#define _FRC_PKTBUF0_PKTBUF3_MASK 0xFF000000UL /**< Bit mask for FRC_PKTBUF3 */
+#define _FRC_PKTBUF0_PKTBUF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF0 */
+#define FRC_PKTBUF0_PKTBUF3_DEFAULT (_FRC_PKTBUF0_PKTBUF3_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_PKTBUF0 */
+
+/* Bit fields for FRC PKTBUF1 */
+#define _FRC_PKTBUF1_RESETVALUE 0x00000000UL /**< Default value for FRC_PKTBUF1 */
+#define _FRC_PKTBUF1_MASK 0xFFFFFFFFUL /**< Mask for FRC_PKTBUF1 */
+#define _FRC_PKTBUF1_PKTBUF4_SHIFT 0 /**< Shift value for FRC_PKTBUF4 */
+#define _FRC_PKTBUF1_PKTBUF4_MASK 0xFFUL /**< Bit mask for FRC_PKTBUF4 */
+#define _FRC_PKTBUF1_PKTBUF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF1 */
+#define FRC_PKTBUF1_PKTBUF4_DEFAULT (_FRC_PKTBUF1_PKTBUF4_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PKTBUF1 */
+#define _FRC_PKTBUF1_PKTBUF5_SHIFT 8 /**< Shift value for FRC_PKTBUF5 */
+#define _FRC_PKTBUF1_PKTBUF5_MASK 0xFF00UL /**< Bit mask for FRC_PKTBUF5 */
+#define _FRC_PKTBUF1_PKTBUF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF1 */
+#define FRC_PKTBUF1_PKTBUF5_DEFAULT (_FRC_PKTBUF1_PKTBUF5_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_PKTBUF1 */
+#define _FRC_PKTBUF1_PKTBUF6_SHIFT 16 /**< Shift value for FRC_PKTBUF6 */
+#define _FRC_PKTBUF1_PKTBUF6_MASK 0xFF0000UL /**< Bit mask for FRC_PKTBUF6 */
+#define _FRC_PKTBUF1_PKTBUF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF1 */
+#define FRC_PKTBUF1_PKTBUF6_DEFAULT (_FRC_PKTBUF1_PKTBUF6_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_PKTBUF1 */
+#define _FRC_PKTBUF1_PKTBUF7_SHIFT 24 /**< Shift value for FRC_PKTBUF7 */
+#define _FRC_PKTBUF1_PKTBUF7_MASK 0xFF000000UL /**< Bit mask for FRC_PKTBUF7 */
+#define _FRC_PKTBUF1_PKTBUF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF1 */
+#define FRC_PKTBUF1_PKTBUF7_DEFAULT (_FRC_PKTBUF1_PKTBUF7_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_PKTBUF1 */
+
+/* Bit fields for FRC PKTBUF2 */
+#define _FRC_PKTBUF2_RESETVALUE 0x00000000UL /**< Default value for FRC_PKTBUF2 */
+#define _FRC_PKTBUF2_MASK 0xFFFFFFFFUL /**< Mask for FRC_PKTBUF2 */
+#define _FRC_PKTBUF2_PKTBUF8_SHIFT 0 /**< Shift value for FRC_PKTBUF8 */
+#define _FRC_PKTBUF2_PKTBUF8_MASK 0xFFUL /**< Bit mask for FRC_PKTBUF8 */
+#define _FRC_PKTBUF2_PKTBUF8_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF2 */
+#define FRC_PKTBUF2_PKTBUF8_DEFAULT (_FRC_PKTBUF2_PKTBUF8_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PKTBUF2 */
+#define _FRC_PKTBUF2_PKTBUF9_SHIFT 8 /**< Shift value for FRC_PKTBUF9 */
+#define _FRC_PKTBUF2_PKTBUF9_MASK 0xFF00UL /**< Bit mask for FRC_PKTBUF9 */
+#define _FRC_PKTBUF2_PKTBUF9_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF2 */
+#define FRC_PKTBUF2_PKTBUF9_DEFAULT (_FRC_PKTBUF2_PKTBUF9_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_PKTBUF2 */
+#define _FRC_PKTBUF2_PKTBUF10_SHIFT 16 /**< Shift value for FRC_PKTBUF10 */
+#define _FRC_PKTBUF2_PKTBUF10_MASK 0xFF0000UL /**< Bit mask for FRC_PKTBUF10 */
+#define _FRC_PKTBUF2_PKTBUF10_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF2 */
+#define FRC_PKTBUF2_PKTBUF10_DEFAULT (_FRC_PKTBUF2_PKTBUF10_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_PKTBUF2 */
+#define _FRC_PKTBUF2_PKTBUF11_SHIFT 24 /**< Shift value for FRC_PKTBUF11 */
+#define _FRC_PKTBUF2_PKTBUF11_MASK 0xFF000000UL /**< Bit mask for FRC_PKTBUF11 */
+#define _FRC_PKTBUF2_PKTBUF11_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF2 */
+#define FRC_PKTBUF2_PKTBUF11_DEFAULT (_FRC_PKTBUF2_PKTBUF11_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_PKTBUF2 */
+
+/* Bit fields for FRC PKTBUF3 */
+#define _FRC_PKTBUF3_RESETVALUE 0x00000000UL /**< Default value for FRC_PKTBUF3 */
+#define _FRC_PKTBUF3_MASK 0xFFFFFFFFUL /**< Mask for FRC_PKTBUF3 */
+#define _FRC_PKTBUF3_PKTBUF12_SHIFT 0 /**< Shift value for FRC_PKTBUF12 */
+#define _FRC_PKTBUF3_PKTBUF12_MASK 0xFFUL /**< Bit mask for FRC_PKTBUF12 */
+#define _FRC_PKTBUF3_PKTBUF12_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF3 */
+#define FRC_PKTBUF3_PKTBUF12_DEFAULT (_FRC_PKTBUF3_PKTBUF12_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PKTBUF3 */
+#define _FRC_PKTBUF3_PKTBUF13_SHIFT 8 /**< Shift value for FRC_PKTBUF13 */
+#define _FRC_PKTBUF3_PKTBUF13_MASK 0xFF00UL /**< Bit mask for FRC_PKTBUF13 */
+#define _FRC_PKTBUF3_PKTBUF13_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF3 */
+#define FRC_PKTBUF3_PKTBUF13_DEFAULT (_FRC_PKTBUF3_PKTBUF13_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_PKTBUF3 */
+#define _FRC_PKTBUF3_PKTBUF14_SHIFT 16 /**< Shift value for FRC_PKTBUF14 */
+#define _FRC_PKTBUF3_PKTBUF14_MASK 0xFF0000UL /**< Bit mask for FRC_PKTBUF14 */
+#define _FRC_PKTBUF3_PKTBUF14_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF3 */
+#define FRC_PKTBUF3_PKTBUF14_DEFAULT (_FRC_PKTBUF3_PKTBUF14_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_PKTBUF3 */
+#define _FRC_PKTBUF3_PKTBUF15_SHIFT 24 /**< Shift value for FRC_PKTBUF15 */
+#define _FRC_PKTBUF3_PKTBUF15_MASK 0xFF000000UL /**< Bit mask for FRC_PKTBUF15 */
+#define _FRC_PKTBUF3_PKTBUF15_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF3 */
+#define FRC_PKTBUF3_PKTBUF15_DEFAULT (_FRC_PKTBUF3_PKTBUF15_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_PKTBUF3 */
+
+/* Bit fields for FRC PKTBUF4 */
+#define _FRC_PKTBUF4_RESETVALUE 0x00000000UL /**< Default value for FRC_PKTBUF4 */
+#define _FRC_PKTBUF4_MASK 0xFFFFFFFFUL /**< Mask for FRC_PKTBUF4 */
+#define _FRC_PKTBUF4_PKTBUF16_SHIFT 0 /**< Shift value for FRC_PKTBUF16 */
+#define _FRC_PKTBUF4_PKTBUF16_MASK 0xFFUL /**< Bit mask for FRC_PKTBUF16 */
+#define _FRC_PKTBUF4_PKTBUF16_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF4 */
+#define FRC_PKTBUF4_PKTBUF16_DEFAULT (_FRC_PKTBUF4_PKTBUF16_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PKTBUF4 */
+#define _FRC_PKTBUF4_PKTBUF17_SHIFT 8 /**< Shift value for FRC_PKTBUF17 */
+#define _FRC_PKTBUF4_PKTBUF17_MASK 0xFF00UL /**< Bit mask for FRC_PKTBUF17 */
+#define _FRC_PKTBUF4_PKTBUF17_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF4 */
+#define FRC_PKTBUF4_PKTBUF17_DEFAULT (_FRC_PKTBUF4_PKTBUF17_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_PKTBUF4 */
+#define _FRC_PKTBUF4_PKTBUF18_SHIFT 16 /**< Shift value for FRC_PKTBUF18 */
+#define _FRC_PKTBUF4_PKTBUF18_MASK 0xFF0000UL /**< Bit mask for FRC_PKTBUF18 */
+#define _FRC_PKTBUF4_PKTBUF18_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF4 */
+#define FRC_PKTBUF4_PKTBUF18_DEFAULT (_FRC_PKTBUF4_PKTBUF18_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_PKTBUF4 */
+#define _FRC_PKTBUF4_PKTBUF19_SHIFT 24 /**< Shift value for FRC_PKTBUF19 */
+#define _FRC_PKTBUF4_PKTBUF19_MASK 0xFF000000UL /**< Bit mask for FRC_PKTBUF19 */
+#define _FRC_PKTBUF4_PKTBUF19_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF4 */
+#define FRC_PKTBUF4_PKTBUF19_DEFAULT (_FRC_PKTBUF4_PKTBUF19_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_PKTBUF4 */
+
+/* Bit fields for FRC PKTBUF5 */
+#define _FRC_PKTBUF5_RESETVALUE 0x00000000UL /**< Default value for FRC_PKTBUF5 */
+#define _FRC_PKTBUF5_MASK 0xFFFFFFFFUL /**< Mask for FRC_PKTBUF5 */
+#define _FRC_PKTBUF5_PKTBUF20_SHIFT 0 /**< Shift value for FRC_PKTBUF20 */
+#define _FRC_PKTBUF5_PKTBUF20_MASK 0xFFUL /**< Bit mask for FRC_PKTBUF20 */
+#define _FRC_PKTBUF5_PKTBUF20_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF5 */
+#define FRC_PKTBUF5_PKTBUF20_DEFAULT (_FRC_PKTBUF5_PKTBUF20_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PKTBUF5 */
+#define _FRC_PKTBUF5_PKTBUF21_SHIFT 8 /**< Shift value for FRC_PKTBUF21 */
+#define _FRC_PKTBUF5_PKTBUF21_MASK 0xFF00UL /**< Bit mask for FRC_PKTBUF21 */
+#define _FRC_PKTBUF5_PKTBUF21_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF5 */
+#define FRC_PKTBUF5_PKTBUF21_DEFAULT (_FRC_PKTBUF5_PKTBUF21_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_PKTBUF5 */
+#define _FRC_PKTBUF5_PKTBUF22_SHIFT 16 /**< Shift value for FRC_PKTBUF22 */
+#define _FRC_PKTBUF5_PKTBUF22_MASK 0xFF0000UL /**< Bit mask for FRC_PKTBUF22 */
+#define _FRC_PKTBUF5_PKTBUF22_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF5 */
+#define FRC_PKTBUF5_PKTBUF22_DEFAULT (_FRC_PKTBUF5_PKTBUF22_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_PKTBUF5 */
+#define _FRC_PKTBUF5_PKTBUF23_SHIFT 24 /**< Shift value for FRC_PKTBUF23 */
+#define _FRC_PKTBUF5_PKTBUF23_MASK 0xFF000000UL /**< Bit mask for FRC_PKTBUF23 */
+#define _FRC_PKTBUF5_PKTBUF23_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF5 */
+#define FRC_PKTBUF5_PKTBUF23_DEFAULT (_FRC_PKTBUF5_PKTBUF23_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_PKTBUF5 */
+
+/* Bit fields for FRC PKTBUF6 */
+#define _FRC_PKTBUF6_RESETVALUE 0x00000000UL /**< Default value for FRC_PKTBUF6 */
+#define _FRC_PKTBUF6_MASK 0xFFFFFFFFUL /**< Mask for FRC_PKTBUF6 */
+#define _FRC_PKTBUF6_PKTBUF24_SHIFT 0 /**< Shift value for FRC_PKTBUF24 */
+#define _FRC_PKTBUF6_PKTBUF24_MASK 0xFFUL /**< Bit mask for FRC_PKTBUF24 */
+#define _FRC_PKTBUF6_PKTBUF24_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF6 */
+#define FRC_PKTBUF6_PKTBUF24_DEFAULT (_FRC_PKTBUF6_PKTBUF24_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PKTBUF6 */
+#define _FRC_PKTBUF6_PKTBUF25_SHIFT 8 /**< Shift value for FRC_PKTBUF25 */
+#define _FRC_PKTBUF6_PKTBUF25_MASK 0xFF00UL /**< Bit mask for FRC_PKTBUF25 */
+#define _FRC_PKTBUF6_PKTBUF25_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF6 */
+#define FRC_PKTBUF6_PKTBUF25_DEFAULT (_FRC_PKTBUF6_PKTBUF25_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_PKTBUF6 */
+#define _FRC_PKTBUF6_PKTBUF26_SHIFT 16 /**< Shift value for FRC_PKTBUF26 */
+#define _FRC_PKTBUF6_PKTBUF26_MASK 0xFF0000UL /**< Bit mask for FRC_PKTBUF26 */
+#define _FRC_PKTBUF6_PKTBUF26_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF6 */
+#define FRC_PKTBUF6_PKTBUF26_DEFAULT (_FRC_PKTBUF6_PKTBUF26_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_PKTBUF6 */
+#define _FRC_PKTBUF6_PKTBUF27_SHIFT 24 /**< Shift value for FRC_PKTBUF27 */
+#define _FRC_PKTBUF6_PKTBUF27_MASK 0xFF000000UL /**< Bit mask for FRC_PKTBUF27 */
+#define _FRC_PKTBUF6_PKTBUF27_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF6 */
+#define FRC_PKTBUF6_PKTBUF27_DEFAULT (_FRC_PKTBUF6_PKTBUF27_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_PKTBUF6 */
+
+/* Bit fields for FRC PKTBUF7 */
+#define _FRC_PKTBUF7_RESETVALUE 0x00000000UL /**< Default value for FRC_PKTBUF7 */
+#define _FRC_PKTBUF7_MASK 0xFFFFFFFFUL /**< Mask for FRC_PKTBUF7 */
+#define _FRC_PKTBUF7_PKTBUF28_SHIFT 0 /**< Shift value for FRC_PKTBUF28 */
+#define _FRC_PKTBUF7_PKTBUF28_MASK 0xFFUL /**< Bit mask for FRC_PKTBUF28 */
+#define _FRC_PKTBUF7_PKTBUF28_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF7 */
+#define FRC_PKTBUF7_PKTBUF28_DEFAULT (_FRC_PKTBUF7_PKTBUF28_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PKTBUF7 */
+#define _FRC_PKTBUF7_PKTBUF29_SHIFT 8 /**< Shift value for FRC_PKTBUF29 */
+#define _FRC_PKTBUF7_PKTBUF29_MASK 0xFF00UL /**< Bit mask for FRC_PKTBUF29 */
+#define _FRC_PKTBUF7_PKTBUF29_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF7 */
+#define FRC_PKTBUF7_PKTBUF29_DEFAULT (_FRC_PKTBUF7_PKTBUF29_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_PKTBUF7 */
+#define _FRC_PKTBUF7_PKTBUF30_SHIFT 16 /**< Shift value for FRC_PKTBUF30 */
+#define _FRC_PKTBUF7_PKTBUF30_MASK 0xFF0000UL /**< Bit mask for FRC_PKTBUF30 */
+#define _FRC_PKTBUF7_PKTBUF30_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF7 */
+#define FRC_PKTBUF7_PKTBUF30_DEFAULT (_FRC_PKTBUF7_PKTBUF30_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_PKTBUF7 */
+#define _FRC_PKTBUF7_PKTBUF31_SHIFT 24 /**< Shift value for FRC_PKTBUF31 */
+#define _FRC_PKTBUF7_PKTBUF31_MASK 0xFF000000UL /**< Bit mask for FRC_PKTBUF31 */
+#define _FRC_PKTBUF7_PKTBUF31_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF7 */
+#define FRC_PKTBUF7_PKTBUF31_DEFAULT (_FRC_PKTBUF7_PKTBUF31_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_PKTBUF7 */
+
+/* Bit fields for FRC PKTBUF8 */
+#define _FRC_PKTBUF8_RESETVALUE 0x00000000UL /**< Default value for FRC_PKTBUF8 */
+#define _FRC_PKTBUF8_MASK 0xFFFFFFFFUL /**< Mask for FRC_PKTBUF8 */
+#define _FRC_PKTBUF8_PKTBUF32_SHIFT 0 /**< Shift value for FRC_PKTBUF32 */
+#define _FRC_PKTBUF8_PKTBUF32_MASK 0xFFUL /**< Bit mask for FRC_PKTBUF32 */
+#define _FRC_PKTBUF8_PKTBUF32_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF8 */
+#define FRC_PKTBUF8_PKTBUF32_DEFAULT (_FRC_PKTBUF8_PKTBUF32_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PKTBUF8 */
+#define _FRC_PKTBUF8_PKTBUF33_SHIFT 8 /**< Shift value for FRC_PKTBUF33 */
+#define _FRC_PKTBUF8_PKTBUF33_MASK 0xFF00UL /**< Bit mask for FRC_PKTBUF33 */
+#define _FRC_PKTBUF8_PKTBUF33_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF8 */
+#define FRC_PKTBUF8_PKTBUF33_DEFAULT (_FRC_PKTBUF8_PKTBUF33_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_PKTBUF8 */
+#define _FRC_PKTBUF8_PKTBUF34_SHIFT 16 /**< Shift value for FRC_PKTBUF34 */
+#define _FRC_PKTBUF8_PKTBUF34_MASK 0xFF0000UL /**< Bit mask for FRC_PKTBUF34 */
+#define _FRC_PKTBUF8_PKTBUF34_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF8 */
+#define FRC_PKTBUF8_PKTBUF34_DEFAULT (_FRC_PKTBUF8_PKTBUF34_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_PKTBUF8 */
+#define _FRC_PKTBUF8_PKTBUF35_SHIFT 24 /**< Shift value for FRC_PKTBUF35 */
+#define _FRC_PKTBUF8_PKTBUF35_MASK 0xFF000000UL /**< Bit mask for FRC_PKTBUF35 */
+#define _FRC_PKTBUF8_PKTBUF35_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF8 */
+#define FRC_PKTBUF8_PKTBUF35_DEFAULT (_FRC_PKTBUF8_PKTBUF35_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_PKTBUF8 */
+
+/* Bit fields for FRC PKTBUF9 */
+#define _FRC_PKTBUF9_RESETVALUE 0x00000000UL /**< Default value for FRC_PKTBUF9 */
+#define _FRC_PKTBUF9_MASK 0xFFFFFFFFUL /**< Mask for FRC_PKTBUF9 */
+#define _FRC_PKTBUF9_PKTBUF36_SHIFT 0 /**< Shift value for FRC_PKTBUF36 */
+#define _FRC_PKTBUF9_PKTBUF36_MASK 0xFFUL /**< Bit mask for FRC_PKTBUF36 */
+#define _FRC_PKTBUF9_PKTBUF36_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF9 */
+#define FRC_PKTBUF9_PKTBUF36_DEFAULT (_FRC_PKTBUF9_PKTBUF36_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PKTBUF9 */
+#define _FRC_PKTBUF9_PKTBUF37_SHIFT 8 /**< Shift value for FRC_PKTBUF37 */
+#define _FRC_PKTBUF9_PKTBUF37_MASK 0xFF00UL /**< Bit mask for FRC_PKTBUF37 */
+#define _FRC_PKTBUF9_PKTBUF37_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF9 */
+#define FRC_PKTBUF9_PKTBUF37_DEFAULT (_FRC_PKTBUF9_PKTBUF37_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_PKTBUF9 */
+#define _FRC_PKTBUF9_PKTBUF38_SHIFT 16 /**< Shift value for FRC_PKTBUF38 */
+#define _FRC_PKTBUF9_PKTBUF38_MASK 0xFF0000UL /**< Bit mask for FRC_PKTBUF38 */
+#define _FRC_PKTBUF9_PKTBUF38_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF9 */
+#define FRC_PKTBUF9_PKTBUF38_DEFAULT (_FRC_PKTBUF9_PKTBUF38_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_PKTBUF9 */
+#define _FRC_PKTBUF9_PKTBUF39_SHIFT 24 /**< Shift value for FRC_PKTBUF39 */
+#define _FRC_PKTBUF9_PKTBUF39_MASK 0xFF000000UL /**< Bit mask for FRC_PKTBUF39 */
+#define _FRC_PKTBUF9_PKTBUF39_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF9 */
+#define FRC_PKTBUF9_PKTBUF39_DEFAULT (_FRC_PKTBUF9_PKTBUF39_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_PKTBUF9 */
+
+/* Bit fields for FRC PKTBUF10 */
+#define _FRC_PKTBUF10_RESETVALUE 0x00000000UL /**< Default value for FRC_PKTBUF10 */
+#define _FRC_PKTBUF10_MASK 0xFFFFFFFFUL /**< Mask for FRC_PKTBUF10 */
+#define _FRC_PKTBUF10_PKTBUF40_SHIFT 0 /**< Shift value for FRC_PKTBUF40 */
+#define _FRC_PKTBUF10_PKTBUF40_MASK 0xFFUL /**< Bit mask for FRC_PKTBUF40 */
+#define _FRC_PKTBUF10_PKTBUF40_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF10 */
+#define FRC_PKTBUF10_PKTBUF40_DEFAULT (_FRC_PKTBUF10_PKTBUF40_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PKTBUF10 */
+#define _FRC_PKTBUF10_PKTBUF41_SHIFT 8 /**< Shift value for FRC_PKTBUF41 */
+#define _FRC_PKTBUF10_PKTBUF41_MASK 0xFF00UL /**< Bit mask for FRC_PKTBUF41 */
+#define _FRC_PKTBUF10_PKTBUF41_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF10 */
+#define FRC_PKTBUF10_PKTBUF41_DEFAULT (_FRC_PKTBUF10_PKTBUF41_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_PKTBUF10 */
+#define _FRC_PKTBUF10_PKTBUF42_SHIFT 16 /**< Shift value for FRC_PKTBUF42 */
+#define _FRC_PKTBUF10_PKTBUF42_MASK 0xFF0000UL /**< Bit mask for FRC_PKTBUF42 */
+#define _FRC_PKTBUF10_PKTBUF42_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF10 */
+#define FRC_PKTBUF10_PKTBUF42_DEFAULT (_FRC_PKTBUF10_PKTBUF42_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_PKTBUF10 */
+#define _FRC_PKTBUF10_PKTBUF43_SHIFT 24 /**< Shift value for FRC_PKTBUF43 */
+#define _FRC_PKTBUF10_PKTBUF43_MASK 0xFF000000UL /**< Bit mask for FRC_PKTBUF43 */
+#define _FRC_PKTBUF10_PKTBUF43_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF10 */
+#define FRC_PKTBUF10_PKTBUF43_DEFAULT (_FRC_PKTBUF10_PKTBUF43_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_PKTBUF10 */
+
+/* Bit fields for FRC PKTBUF11 */
+#define _FRC_PKTBUF11_RESETVALUE 0x00000000UL /**< Default value for FRC_PKTBUF11 */
+#define _FRC_PKTBUF11_MASK 0xFFFFFFFFUL /**< Mask for FRC_PKTBUF11 */
+#define _FRC_PKTBUF11_PKTBUF44_SHIFT 0 /**< Shift value for FRC_PKTBUF44 */
+#define _FRC_PKTBUF11_PKTBUF44_MASK 0xFFUL /**< Bit mask for FRC_PKTBUF44 */
+#define _FRC_PKTBUF11_PKTBUF44_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF11 */
+#define FRC_PKTBUF11_PKTBUF44_DEFAULT (_FRC_PKTBUF11_PKTBUF44_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_PKTBUF11 */
+#define _FRC_PKTBUF11_PKTBUF45_SHIFT 8 /**< Shift value for FRC_PKTBUF45 */
+#define _FRC_PKTBUF11_PKTBUF45_MASK 0xFF00UL /**< Bit mask for FRC_PKTBUF45 */
+#define _FRC_PKTBUF11_PKTBUF45_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF11 */
+#define FRC_PKTBUF11_PKTBUF45_DEFAULT (_FRC_PKTBUF11_PKTBUF45_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_PKTBUF11 */
+#define _FRC_PKTBUF11_PKTBUF46_SHIFT 16 /**< Shift value for FRC_PKTBUF46 */
+#define _FRC_PKTBUF11_PKTBUF46_MASK 0xFF0000UL /**< Bit mask for FRC_PKTBUF46 */
+#define _FRC_PKTBUF11_PKTBUF46_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF11 */
+#define FRC_PKTBUF11_PKTBUF46_DEFAULT (_FRC_PKTBUF11_PKTBUF46_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_PKTBUF11 */
+#define _FRC_PKTBUF11_PKTBUF47_SHIFT 24 /**< Shift value for FRC_PKTBUF47 */
+#define _FRC_PKTBUF11_PKTBUF47_MASK 0xFF000000UL /**< Bit mask for FRC_PKTBUF47 */
+#define _FRC_PKTBUF11_PKTBUF47_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_PKTBUF11 */
+#define FRC_PKTBUF11_PKTBUF47_DEFAULT (_FRC_PKTBUF11_PKTBUF47_DEFAULT << 24) /**< Shifted mode DEFAULT for FRC_PKTBUF11 */
+
+/* Bit fields for FRC FCD */
+#define _FRC_FCD_RESETVALUE 0x000000FFUL /**< Default value for FRC_FCD */
+#define _FRC_FCD_MASK 0x0001FFFFUL /**< Mask for FRC_FCD */
+#define _FRC_FCD_WORDS_SHIFT 0 /**< Shift value for FRC_WORDS */
+#define _FRC_FCD_WORDS_MASK 0xFFUL /**< Bit mask for FRC_WORDS */
+#define _FRC_FCD_WORDS_DEFAULT 0x000000FFUL /**< Mode DEFAULT for FRC_FCD */
+#define FRC_FCD_WORDS_DEFAULT (_FRC_FCD_WORDS_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_FCD */
+#define _FRC_FCD_BUFFER_SHIFT 8 /**< Shift value for FRC_BUFFER */
+#define _FRC_FCD_BUFFER_MASK 0x300UL /**< Bit mask for FRC_BUFFER */
+#define _FRC_FCD_BUFFER_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FCD */
+#define FRC_FCD_BUFFER_DEFAULT (_FRC_FCD_BUFFER_DEFAULT << 8) /**< Shifted mode DEFAULT for FRC_FCD */
+#define FRC_FCD_INCLUDECRC (0x1UL << 10) /**< Include CRC */
+#define _FRC_FCD_INCLUDECRC_SHIFT 10 /**< Shift value for FRC_INCLUDECRC */
+#define _FRC_FCD_INCLUDECRC_MASK 0x400UL /**< Bit mask for FRC_INCLUDECRC */
+#define _FRC_FCD_INCLUDECRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FCD */
+#define FRC_FCD_INCLUDECRC_DEFAULT (_FRC_FCD_INCLUDECRC_DEFAULT << 10) /**< Shifted mode DEFAULT for FRC_FCD */
+#define FRC_FCD_CALCCRC (0x1UL << 11) /**< Calculate CRC */
+#define _FRC_FCD_CALCCRC_SHIFT 11 /**< Shift value for FRC_CALCCRC */
+#define _FRC_FCD_CALCCRC_MASK 0x800UL /**< Bit mask for FRC_CALCCRC */
+#define _FRC_FCD_CALCCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FCD */
+#define FRC_FCD_CALCCRC_DEFAULT (_FRC_FCD_CALCCRC_DEFAULT << 11) /**< Shifted mode DEFAULT for FRC_FCD */
+#define _FRC_FCD_SKIPCRC_SHIFT 12 /**< Shift value for FRC_SKIPCRC */
+#define _FRC_FCD_SKIPCRC_MASK 0x3000UL /**< Bit mask for FRC_SKIPCRC */
+#define _FRC_FCD_SKIPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FCD */
+#define FRC_FCD_SKIPCRC_DEFAULT (_FRC_FCD_SKIPCRC_DEFAULT << 12) /**< Shifted mode DEFAULT for FRC_FCD */
+#define FRC_FCD_SKIPWHITE (0x1UL << 14) /**< Skip data whitening in this subframe */
+#define _FRC_FCD_SKIPWHITE_SHIFT 14 /**< Shift value for FRC_SKIPWHITE */
+#define _FRC_FCD_SKIPWHITE_MASK 0x4000UL /**< Bit mask for FRC_SKIPWHITE */
+#define _FRC_FCD_SKIPWHITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FCD */
+#define FRC_FCD_SKIPWHITE_DEFAULT (_FRC_FCD_SKIPWHITE_DEFAULT << 14) /**< Shifted mode DEFAULT for FRC_FCD */
+#define FRC_FCD_ADDTRAILTXDATA (0x1UL << 15) /**< Add trailing TX data in this subframe */
+#define _FRC_FCD_ADDTRAILTXDATA_SHIFT 15 /**< Shift value for FRC_ADDTRAILTXDATA */
+#define _FRC_FCD_ADDTRAILTXDATA_MASK 0x8000UL /**< Bit mask for FRC_ADDTRAILTXDATA */
+#define _FRC_FCD_ADDTRAILTXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FCD */
+#define FRC_FCD_ADDTRAILTXDATA_DEFAULT (_FRC_FCD_ADDTRAILTXDATA_DEFAULT << 15) /**< Shifted mode DEFAULT for FRC_FCD */
+#define FRC_FCD_EXCLUDESUBFRAMEWCNT (0x1UL << 16) /**< Exclude subframe from WCNT */
+#define _FRC_FCD_EXCLUDESUBFRAMEWCNT_SHIFT 16 /**< Shift value for FRC_EXCLUDESUBFRAMEWCNT */
+#define _FRC_FCD_EXCLUDESUBFRAMEWCNT_MASK 0x10000UL /**< Bit mask for FRC_EXCLUDESUBFRAMEWCNT */
+#define _FRC_FCD_EXCLUDESUBFRAMEWCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_FCD */
+#define FRC_FCD_EXCLUDESUBFRAMEWCNT_DEFAULT (_FRC_FCD_EXCLUDESUBFRAMEWCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for FRC_FCD */
+
+/* Bit fields for FRC INTELEMENT */
+#define _FRC_INTELEMENT_RESETVALUE 0x00000000UL /**< Default value for FRC_INTELEMENT */
+#define _FRC_INTELEMENT_MASK 0x000000FFUL /**< Mask for FRC_INTELEMENT */
+#define _FRC_INTELEMENT_INTELEMENT_SHIFT 0 /**< Shift value for FRC_INTELEMENT */
+#define _FRC_INTELEMENT_INTELEMENT_MASK 0xFFUL /**< Bit mask for FRC_INTELEMENT */
+#define _FRC_INTELEMENT_INTELEMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for FRC_INTELEMENT */
+#define FRC_INTELEMENT_INTELEMENT_DEFAULT (_FRC_INTELEMENT_INTELEMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_INTELEMENT */
+
+/* Bit fields for FRC AHBCONFIG */
+#define _FRC_AHBCONFIG_RESETVALUE 0x00000001UL /**< Default value for FRC_AHBCONFIG */
+#define _FRC_AHBCONFIG_MASK 0x00000001UL /**< Mask for FRC_AHBCONFIG */
+#define FRC_AHBCONFIG_AHBHPROTBUFFERABLE (0x1UL << 0) /**< Bufferable Privileged data for AHB */
+#define _FRC_AHBCONFIG_AHBHPROTBUFFERABLE_SHIFT 0 /**< Shift value for FRC_AHBHPROTBUFFERABLE */
+#define _FRC_AHBCONFIG_AHBHPROTBUFFERABLE_MASK 0x1UL /**< Bit mask for FRC_AHBHPROTBUFFERABLE */
+#define _FRC_AHBCONFIG_AHBHPROTBUFFERABLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for FRC_AHBCONFIG */
+#define FRC_AHBCONFIG_AHBHPROTBUFFERABLE_DEFAULT (_FRC_AHBCONFIG_AHBHPROTBUFFERABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for FRC_AHBCONFIG */
+
+/** @} End of group EFR32MG24_FRC_BitFields */
+/** @} End of group EFR32MG24_FRC */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_FRC_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_fsrco.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_fsrco.h
new file mode 100644
index 00000000..a12fda11
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_fsrco.h
@@ -0,0 +1,75 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 FSRCO register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_FSRCO_H
+#define EFR32MG24_FSRCO_H
+#define FSRCO_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_FSRCO FSRCO
+ * @{
+ * @brief EFR32MG24 FSRCO Register Declaration.
+ *****************************************************************************/
+
+/** FSRCO Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IP Version */
+ uint32_t RESERVED0[1023U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP Version */
+ uint32_t RESERVED1[1023U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP Version */
+ uint32_t RESERVED2[1023U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP Version */
+} FSRCO_TypeDef;
+/** @} End of group EFR32MG24_FSRCO */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_FSRCO
+ * @{
+ * @defgroup EFR32MG24_FSRCO_BitFields FSRCO Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for FSRCO IPVERSION */
+#define _FSRCO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for FSRCO_IPVERSION */
+#define _FSRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for FSRCO_IPVERSION */
+#define _FSRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for FSRCO_IPVERSION */
+#define _FSRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for FSRCO_IPVERSION */
+#define _FSRCO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for FSRCO_IPVERSION */
+#define FSRCO_IPVERSION_IPVERSION_DEFAULT (_FSRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for FSRCO_IPVERSION */
+
+/** @} End of group EFR32MG24_FSRCO_BitFields */
+/** @} End of group EFR32MG24_FSRCO */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_FSRCO_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_gpcrc.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_gpcrc.h
new file mode 100644
index 00000000..07689097
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_gpcrc.h
@@ -0,0 +1,246 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 GPCRC register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_GPCRC_H
+#define EFR32MG24_GPCRC_H
+#define GPCRC_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_GPCRC GPCRC
+ * @{
+ * @brief EFR32MG24 GPCRC Register Declaration.
+ *****************************************************************************/
+
+/** GPCRC Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IP Version ID */
+ __IOM uint32_t EN; /**< CRC Enable */
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IOM uint32_t INIT; /**< CRC Init Value */
+ __IOM uint32_t POLY; /**< CRC Polynomial Value */
+ __IOM uint32_t INPUTDATA; /**< Input 32-bit Data Register */
+ __IOM uint32_t INPUTDATAHWORD; /**< Input 16-bit Data Register */
+ __IOM uint32_t INPUTDATABYTE; /**< Input 8-bit Data Register */
+ __IM uint32_t DATA; /**< CRC Data Register */
+ __IM uint32_t DATAREV; /**< CRC Data Reverse Register */
+ __IM uint32_t DATABYTEREV; /**< CRC Data Byte Reverse Register */
+ uint32_t RESERVED0[1012U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP Version ID */
+ __IOM uint32_t EN_SET; /**< CRC Enable */
+ __IOM uint32_t CTRL_SET; /**< Control Register */
+ __IOM uint32_t CMD_SET; /**< Command Register */
+ __IOM uint32_t INIT_SET; /**< CRC Init Value */
+ __IOM uint32_t POLY_SET; /**< CRC Polynomial Value */
+ __IOM uint32_t INPUTDATA_SET; /**< Input 32-bit Data Register */
+ __IOM uint32_t INPUTDATAHWORD_SET; /**< Input 16-bit Data Register */
+ __IOM uint32_t INPUTDATABYTE_SET; /**< Input 8-bit Data Register */
+ __IM uint32_t DATA_SET; /**< CRC Data Register */
+ __IM uint32_t DATAREV_SET; /**< CRC Data Reverse Register */
+ __IM uint32_t DATABYTEREV_SET; /**< CRC Data Byte Reverse Register */
+ uint32_t RESERVED1[1012U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP Version ID */
+ __IOM uint32_t EN_CLR; /**< CRC Enable */
+ __IOM uint32_t CTRL_CLR; /**< Control Register */
+ __IOM uint32_t CMD_CLR; /**< Command Register */
+ __IOM uint32_t INIT_CLR; /**< CRC Init Value */
+ __IOM uint32_t POLY_CLR; /**< CRC Polynomial Value */
+ __IOM uint32_t INPUTDATA_CLR; /**< Input 32-bit Data Register */
+ __IOM uint32_t INPUTDATAHWORD_CLR; /**< Input 16-bit Data Register */
+ __IOM uint32_t INPUTDATABYTE_CLR; /**< Input 8-bit Data Register */
+ __IM uint32_t DATA_CLR; /**< CRC Data Register */
+ __IM uint32_t DATAREV_CLR; /**< CRC Data Reverse Register */
+ __IM uint32_t DATABYTEREV_CLR; /**< CRC Data Byte Reverse Register */
+ uint32_t RESERVED2[1012U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP Version ID */
+ __IOM uint32_t EN_TGL; /**< CRC Enable */
+ __IOM uint32_t CTRL_TGL; /**< Control Register */
+ __IOM uint32_t CMD_TGL; /**< Command Register */
+ __IOM uint32_t INIT_TGL; /**< CRC Init Value */
+ __IOM uint32_t POLY_TGL; /**< CRC Polynomial Value */
+ __IOM uint32_t INPUTDATA_TGL; /**< Input 32-bit Data Register */
+ __IOM uint32_t INPUTDATAHWORD_TGL; /**< Input 16-bit Data Register */
+ __IOM uint32_t INPUTDATABYTE_TGL; /**< Input 8-bit Data Register */
+ __IM uint32_t DATA_TGL; /**< CRC Data Register */
+ __IM uint32_t DATAREV_TGL; /**< CRC Data Reverse Register */
+ __IM uint32_t DATABYTEREV_TGL; /**< CRC Data Byte Reverse Register */
+} GPCRC_TypeDef;
+/** @} End of group EFR32MG24_GPCRC */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_GPCRC
+ * @{
+ * @defgroup EFR32MG24_GPCRC_BitFields GPCRC Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for GPCRC IPVERSION */
+#define _GPCRC_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for GPCRC_IPVERSION */
+#define _GPCRC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_IPVERSION */
+#define _GPCRC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for GPCRC_IPVERSION */
+#define _GPCRC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_IPVERSION */
+#define _GPCRC_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_IPVERSION */
+#define GPCRC_IPVERSION_IPVERSION_DEFAULT (_GPCRC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_IPVERSION */
+
+/* Bit fields for GPCRC EN */
+#define _GPCRC_EN_RESETVALUE 0x00000000UL /**< Default value for GPCRC_EN */
+#define _GPCRC_EN_MASK 0x00000001UL /**< Mask for GPCRC_EN */
+#define GPCRC_EN_EN (0x1UL << 0) /**< CRC Enable */
+#define _GPCRC_EN_EN_SHIFT 0 /**< Shift value for GPCRC_EN */
+#define _GPCRC_EN_EN_MASK 0x1UL /**< Bit mask for GPCRC_EN */
+#define _GPCRC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_EN */
+#define _GPCRC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for GPCRC_EN */
+#define _GPCRC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for GPCRC_EN */
+#define GPCRC_EN_EN_DEFAULT (_GPCRC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_EN */
+#define GPCRC_EN_EN_DISABLE (_GPCRC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for GPCRC_EN */
+#define GPCRC_EN_EN_ENABLE (_GPCRC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for GPCRC_EN */
+
+/* Bit fields for GPCRC CTRL */
+#define _GPCRC_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CTRL */
+#define _GPCRC_CTRL_MASK 0x00002710UL /**< Mask for GPCRC_CTRL */
+#define GPCRC_CTRL_POLYSEL (0x1UL << 4) /**< Polynomial Select */
+#define _GPCRC_CTRL_POLYSEL_SHIFT 4 /**< Shift value for GPCRC_POLYSEL */
+#define _GPCRC_CTRL_POLYSEL_MASK 0x10UL /**< Bit mask for GPCRC_POLYSEL */
+#define _GPCRC_CTRL_POLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
+#define _GPCRC_CTRL_POLYSEL_CRC32 0x00000000UL /**< Mode CRC32 for GPCRC_CTRL */
+#define _GPCRC_CTRL_POLYSEL_CRC16 0x00000001UL /**< Mode CRC16 for GPCRC_CTRL */
+#define GPCRC_CTRL_POLYSEL_DEFAULT (_GPCRC_CTRL_POLYSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for GPCRC_CTRL */
+#define GPCRC_CTRL_POLYSEL_CRC32 (_GPCRC_CTRL_POLYSEL_CRC32 << 4) /**< Shifted mode CRC32 for GPCRC_CTRL */
+#define GPCRC_CTRL_POLYSEL_CRC16 (_GPCRC_CTRL_POLYSEL_CRC16 << 4) /**< Shifted mode CRC16 for GPCRC_CTRL */
+#define GPCRC_CTRL_BYTEMODE (0x1UL << 8) /**< Byte Mode Enable */
+#define _GPCRC_CTRL_BYTEMODE_SHIFT 8 /**< Shift value for GPCRC_BYTEMODE */
+#define _GPCRC_CTRL_BYTEMODE_MASK 0x100UL /**< Bit mask for GPCRC_BYTEMODE */
+#define _GPCRC_CTRL_BYTEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
+#define GPCRC_CTRL_BYTEMODE_DEFAULT (_GPCRC_CTRL_BYTEMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for GPCRC_CTRL */
+#define GPCRC_CTRL_BITREVERSE (0x1UL << 9) /**< Byte-level Bit Reverse Enable */
+#define _GPCRC_CTRL_BITREVERSE_SHIFT 9 /**< Shift value for GPCRC_BITREVERSE */
+#define _GPCRC_CTRL_BITREVERSE_MASK 0x200UL /**< Bit mask for GPCRC_BITREVERSE */
+#define _GPCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
+#define _GPCRC_CTRL_BITREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */
+#define _GPCRC_CTRL_BITREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */
+#define GPCRC_CTRL_BITREVERSE_DEFAULT (_GPCRC_CTRL_BITREVERSE_DEFAULT << 9) /**< Shifted mode DEFAULT for GPCRC_CTRL */
+#define GPCRC_CTRL_BITREVERSE_NORMAL (_GPCRC_CTRL_BITREVERSE_NORMAL << 9) /**< Shifted mode NORMAL for GPCRC_CTRL */
+#define GPCRC_CTRL_BITREVERSE_REVERSED (_GPCRC_CTRL_BITREVERSE_REVERSED << 9) /**< Shifted mode REVERSED for GPCRC_CTRL */
+#define GPCRC_CTRL_BYTEREVERSE (0x1UL << 10) /**< Byte Reverse Mode */
+#define _GPCRC_CTRL_BYTEREVERSE_SHIFT 10 /**< Shift value for GPCRC_BYTEREVERSE */
+#define _GPCRC_CTRL_BYTEREVERSE_MASK 0x400UL /**< Bit mask for GPCRC_BYTEREVERSE */
+#define _GPCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
+#define _GPCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */
+#define _GPCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */
+#define GPCRC_CTRL_BYTEREVERSE_DEFAULT (_GPCRC_CTRL_BYTEREVERSE_DEFAULT << 10) /**< Shifted mode DEFAULT for GPCRC_CTRL */
+#define GPCRC_CTRL_BYTEREVERSE_NORMAL (_GPCRC_CTRL_BYTEREVERSE_NORMAL << 10) /**< Shifted mode NORMAL for GPCRC_CTRL */
+#define GPCRC_CTRL_BYTEREVERSE_REVERSED (_GPCRC_CTRL_BYTEREVERSE_REVERSED << 10) /**< Shifted mode REVERSED for GPCRC_CTRL */
+#define GPCRC_CTRL_AUTOINIT (0x1UL << 13) /**< Auto Init Enable */
+#define _GPCRC_CTRL_AUTOINIT_SHIFT 13 /**< Shift value for GPCRC_AUTOINIT */
+#define _GPCRC_CTRL_AUTOINIT_MASK 0x2000UL /**< Bit mask for GPCRC_AUTOINIT */
+#define _GPCRC_CTRL_AUTOINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
+#define GPCRC_CTRL_AUTOINIT_DEFAULT (_GPCRC_CTRL_AUTOINIT_DEFAULT << 13) /**< Shifted mode DEFAULT for GPCRC_CTRL */
+
+/* Bit fields for GPCRC CMD */
+#define _GPCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CMD */
+#define _GPCRC_CMD_MASK 0x80000001UL /**< Mask for GPCRC_CMD */
+#define GPCRC_CMD_INIT (0x1UL << 0) /**< Initialization Enable */
+#define _GPCRC_CMD_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */
+#define _GPCRC_CMD_INIT_MASK 0x1UL /**< Bit mask for GPCRC_INIT */
+#define _GPCRC_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CMD */
+#define GPCRC_CMD_INIT_DEFAULT (_GPCRC_CMD_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CMD */
+
+/* Bit fields for GPCRC INIT */
+#define _GPCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INIT */
+#define _GPCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INIT */
+#define _GPCRC_INIT_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */
+#define _GPCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INIT */
+#define _GPCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INIT */
+#define GPCRC_INIT_INIT_DEFAULT (_GPCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INIT */
+
+/* Bit fields for GPCRC POLY */
+#define _GPCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for GPCRC_POLY */
+#define _GPCRC_POLY_MASK 0x0000FFFFUL /**< Mask for GPCRC_POLY */
+#define _GPCRC_POLY_POLY_SHIFT 0 /**< Shift value for GPCRC_POLY */
+#define _GPCRC_POLY_POLY_MASK 0xFFFFUL /**< Bit mask for GPCRC_POLY */
+#define _GPCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_POLY */
+#define GPCRC_POLY_POLY_DEFAULT (_GPCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_POLY */
+
+/* Bit fields for GPCRC INPUTDATA */
+#define _GPCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATA */
+#define _GPCRC_INPUTDATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INPUTDATA */
+#define _GPCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for GPCRC_INPUTDATA */
+#define _GPCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INPUTDATA */
+#define _GPCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATA */
+#define GPCRC_INPUTDATA_INPUTDATA_DEFAULT (_GPCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATA */
+
+/* Bit fields for GPCRC INPUTDATAHWORD */
+#define _GPCRC_INPUTDATAHWORD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATAHWORD */
+#define _GPCRC_INPUTDATAHWORD_MASK 0x0000FFFFUL /**< Mask for GPCRC_INPUTDATAHWORD */
+#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_SHIFT 0 /**< Shift value for GPCRC_INPUTDATAHWORD */
+#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_MASK 0xFFFFUL /**< Bit mask for GPCRC_INPUTDATAHWORD */
+#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATAHWORD */
+#define GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT (_GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATAHWORD*/
+
+/* Bit fields for GPCRC INPUTDATABYTE */
+#define _GPCRC_INPUTDATABYTE_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATABYTE */
+#define _GPCRC_INPUTDATABYTE_MASK 0x000000FFUL /**< Mask for GPCRC_INPUTDATABYTE */
+#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_SHIFT 0 /**< Shift value for GPCRC_INPUTDATABYTE */
+#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_MASK 0xFFUL /**< Bit mask for GPCRC_INPUTDATABYTE */
+#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATABYTE */
+#define GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT (_GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATABYTE*/
+
+/* Bit fields for GPCRC DATA */
+#define _GPCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATA */
+#define _GPCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATA */
+#define _GPCRC_DATA_DATA_SHIFT 0 /**< Shift value for GPCRC_DATA */
+#define _GPCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATA */
+#define _GPCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATA */
+#define GPCRC_DATA_DATA_DEFAULT (_GPCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATA */
+
+/* Bit fields for GPCRC DATAREV */
+#define _GPCRC_DATAREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATAREV */
+#define _GPCRC_DATAREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATAREV */
+#define _GPCRC_DATAREV_DATAREV_SHIFT 0 /**< Shift value for GPCRC_DATAREV */
+#define _GPCRC_DATAREV_DATAREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATAREV */
+#define _GPCRC_DATAREV_DATAREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATAREV */
+#define GPCRC_DATAREV_DATAREV_DEFAULT (_GPCRC_DATAREV_DATAREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATAREV */
+
+/* Bit fields for GPCRC DATABYTEREV */
+#define _GPCRC_DATABYTEREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATABYTEREV */
+#define _GPCRC_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATABYTEREV */
+#define _GPCRC_DATABYTEREV_DATABYTEREV_SHIFT 0 /**< Shift value for GPCRC_DATABYTEREV */
+#define _GPCRC_DATABYTEREV_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATABYTEREV */
+#define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATABYTEREV */
+#define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */
+
+/** @} End of group EFR32MG24_GPCRC_BitFields */
+/** @} End of group EFR32MG24_GPCRC */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_GPCRC_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_gpio.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_gpio.h
new file mode 100644
index 00000000..a93bd227
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_gpio.h
@@ -0,0 +1,2682 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 GPIO register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_GPIO_H
+#define EFR32MG24_GPIO_H
+#define GPIO_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+
+#include "efr32mg24_gpio_port.h"
+
+typedef struct {
+ __IOM uint32_t ROUTEEN; /**< ACMP0 pin enable */
+ __IOM uint32_t ACMPOUTROUTE; /**< ACMPOUT port/pin select */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+} GPIO_ACMPROUTE_TypeDef;
+
+typedef struct {
+ __IOM uint32_t ROUTEEN; /**< CMU pin enable */
+ __IOM uint32_t CLKIN0ROUTE; /**< CLKIN0 port/pin select */
+ __IOM uint32_t CLKOUT0ROUTE; /**< CLKOUT0 port/pin select */
+ __IOM uint32_t CLKOUT1ROUTE; /**< CLKOUT1 port/pin select */
+ __IOM uint32_t CLKOUT2ROUTE; /**< CLKOUT2 port/pin select */
+ uint32_t RESERVED0[2U]; /**< Reserved for future use */
+} GPIO_CMUROUTE_TypeDef;
+
+typedef struct {
+ __IOM uint32_t ROUTEEN; /**< DCDC pin enable */
+ uint32_t RESERVED0[3U]; /**< Reserved for future use */
+} GPIO_DCDCROUTE_TypeDef;
+
+typedef struct {
+ __IOM uint32_t ROUTEEN; /**< EUSART0 pin enable */
+ __IOM uint32_t CSROUTE; /**< CS port/pin select */
+ __IOM uint32_t CTSROUTE; /**< CTS port/pin select */
+ __IOM uint32_t RTSROUTE; /**< RTS port/pin select */
+ __IOM uint32_t RXROUTE; /**< RX port/pin select */
+ __IOM uint32_t SCLKROUTE; /**< SCLK port/pin select */
+ __IOM uint32_t TXROUTE; /**< TX port/pin select */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+} GPIO_EUSARTROUTE_TypeDef;
+
+typedef struct {
+ __IOM uint32_t ROUTEEN; /**< FRC pin enable */
+ __IOM uint32_t DCLKROUTE; /**< DCLK port/pin select */
+ __IOM uint32_t DFRAMEROUTE; /**< DFRAME port/pin select */
+ __IOM uint32_t DOUTROUTE; /**< DOUT port/pin select */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+} GPIO_FRCROUTE_TypeDef;
+
+typedef struct {
+ __IOM uint32_t ROUTEEN; /**< I2C0 pin enable */
+ __IOM uint32_t SCLROUTE; /**< SCL port/pin select */
+ __IOM uint32_t SDAROUTE; /**< SDA port/pin select */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+} GPIO_I2CROUTE_TypeDef;
+
+typedef struct {
+ __IOM uint32_t ROUTEEN; /**< KEYSCAN pin enable */
+ __IOM uint32_t COLOUT0ROUTE; /**< COLOUT0 port/pin select */
+ __IOM uint32_t COLOUT1ROUTE; /**< COLOUT1 port/pin select */
+ __IOM uint32_t COLOUT2ROUTE; /**< COLOUT2 port/pin select */
+ __IOM uint32_t COLOUT3ROUTE; /**< COLOUT3 port/pin select */
+ __IOM uint32_t COLOUT4ROUTE; /**< COLOUT4 port/pin select */
+ __IOM uint32_t COLOUT5ROUTE; /**< COLOUT5 port/pin select */
+ __IOM uint32_t COLOUT6ROUTE; /**< COLOUT6 port/pin select */
+ __IOM uint32_t COLOUT7ROUTE; /**< COLOUT7 port/pin select */
+ __IOM uint32_t ROWSENSE0ROUTE; /**< ROWSENSE0 port/pin select */
+ __IOM uint32_t ROWSENSE1ROUTE; /**< ROWSENSE1 port/pin select */
+ __IOM uint32_t ROWSENSE2ROUTE; /**< ROWSENSE2 port/pin select */
+ __IOM uint32_t ROWSENSE3ROUTE; /**< ROWSENSE3 port/pin select */
+ __IOM uint32_t ROWSENSE4ROUTE; /**< ROWSENSE4 port/pin select */
+ __IOM uint32_t ROWSENSE5ROUTE; /**< ROWSENSE5 port/pin select */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+} GPIO_KEYSCANROUTE_TypeDef;
+
+typedef struct {
+ __IOM uint32_t ROUTEEN; /**< LETIMER pin enable */
+ __IOM uint32_t OUT0ROUTE; /**< OUT0 port/pin select */
+ __IOM uint32_t OUT1ROUTE; /**< OUT1 port/pin select */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+} GPIO_LETIMERROUTE_TypeDef;
+
+typedef struct {
+ __IOM uint32_t ROUTEEN; /**< MODEM pin enable */
+ __IOM uint32_t ANT0ROUTE; /**< ANT0 port/pin select */
+ __IOM uint32_t ANT1ROUTE; /**< ANT1 port/pin select */
+ __IOM uint32_t ANTROLLOVERROUTE; /**< ANTROLLOVER port/pin select */
+ __IOM uint32_t ANTRR0ROUTE; /**< ANTRR0 port/pin select */
+ __IOM uint32_t ANTRR1ROUTE; /**< ANTRR1 port/pin select */
+ __IOM uint32_t ANTRR2ROUTE; /**< ANTRR2 port/pin select */
+ __IOM uint32_t ANTRR3ROUTE; /**< ANTRR3 port/pin select */
+ __IOM uint32_t ANTRR4ROUTE; /**< ANTRR4 port/pin select */
+ __IOM uint32_t ANTRR5ROUTE; /**< ANTRR5 port/pin select */
+ __IOM uint32_t ANTSWENROUTE; /**< ANTSWEN port/pin select */
+ __IOM uint32_t ANTSWUSROUTE; /**< ANTSWUS port/pin select */
+ __IOM uint32_t ANTTRIGROUTE; /**< ANTTRIG port/pin select */
+ __IOM uint32_t ANTTRIGSTOPROUTE; /**< ANTTRIGSTOP port/pin select */
+ __IOM uint32_t DCLKROUTE; /**< DCLK port/pin select */
+ __IOM uint32_t DINROUTE; /**< DIN port/pin select */
+ __IOM uint32_t DOUTROUTE; /**< DOUT port/pin select */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+} GPIO_MODEMROUTE_TypeDef;
+
+typedef struct {
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+ __IOM uint32_t S0INROUTE; /**< S0IN port/pin select */
+ __IOM uint32_t S1INROUTE; /**< S1IN port/pin select */
+ uint32_t RESERVED1[1U]; /**< Reserved for future use */
+} GPIO_PCNTROUTE_TypeDef;
+
+typedef struct {
+ __IOM uint32_t ROUTEEN; /**< PRS0 pin enable */
+ __IOM uint32_t ASYNCH0ROUTE; /**< ASYNCH0 port/pin select */
+ __IOM uint32_t ASYNCH1ROUTE; /**< ASYNCH1 port/pin select */
+ __IOM uint32_t ASYNCH2ROUTE; /**< ASYNCH2 port/pin select */
+ __IOM uint32_t ASYNCH3ROUTE; /**< ASYNCH3 port/pin select */
+ __IOM uint32_t ASYNCH4ROUTE; /**< ASYNCH4 port/pin select */
+ __IOM uint32_t ASYNCH5ROUTE; /**< ASYNCH5 port/pin select */
+ __IOM uint32_t ASYNCH6ROUTE; /**< ASYNCH6 port/pin select */
+ __IOM uint32_t ASYNCH7ROUTE; /**< ASYNCH7 port/pin select */
+ __IOM uint32_t ASYNCH8ROUTE; /**< ASYNCH8 port/pin select */
+ __IOM uint32_t ASYNCH9ROUTE; /**< ASYNCH9 port/pin select */
+ __IOM uint32_t ASYNCH10ROUTE; /**< ASYNCH10 port/pin select */
+ __IOM uint32_t ASYNCH11ROUTE; /**< ASYNCH11 port/pin select */
+ __IOM uint32_t ASYNCH12ROUTE; /**< ASYNCH12 port/pin select */
+ __IOM uint32_t ASYNCH13ROUTE; /**< ASYNCH13 port/pin select */
+ __IOM uint32_t ASYNCH14ROUTE; /**< ASYNCH14 port/pin select */
+ __IOM uint32_t ASYNCH15ROUTE; /**< ASYNCH15 port/pin select */
+ __IOM uint32_t SYNCH0ROUTE; /**< SYNCH0 port/pin select */
+ __IOM uint32_t SYNCH1ROUTE; /**< SYNCH1 port/pin select */
+ __IOM uint32_t SYNCH2ROUTE; /**< SYNCH2 port/pin select */
+ __IOM uint32_t SYNCH3ROUTE; /**< SYNCH3 port/pin select */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+} GPIO_PRSROUTE_TypeDef;
+
+typedef struct {
+ __IOM uint32_t ROUTEEN; /**< RAC pin enable */
+ __IOM uint32_t LNAENROUTE; /**< LNAEN port/pin select */
+ __IOM uint32_t PAENROUTE; /**< PAEN port/pin select */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+} GPIO_RACROUTE_TypeDef;
+
+typedef struct {
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+ __IOM uint32_t BUFOUTREQINASYNCROUTE; /**< BUFOUTREQINASYNC port/pin select */
+ uint32_t RESERVED1[1U]; /**< Reserved for future use */
+} GPIO_SYXOROUTE_TypeDef;
+
+typedef struct {
+ __IOM uint32_t ROUTEEN; /**< TIMER0 pin enable */
+ __IOM uint32_t CC0ROUTE; /**< CC0 port/pin select */
+ __IOM uint32_t CC1ROUTE; /**< CC1 port/pin select */
+ __IOM uint32_t CC2ROUTE; /**< CC2 port/pin select */
+ __IOM uint32_t CDTI0ROUTE; /**< CDTI0 port/pin select */
+ __IOM uint32_t CDTI1ROUTE; /**< CDTI1 port/pin select */
+ __IOM uint32_t CDTI2ROUTE; /**< CDTI2 port/pin select */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+} GPIO_TIMERROUTE_TypeDef;
+
+typedef struct {
+ __IOM uint32_t ROUTEEN; /**< USART0 pin enable */
+ __IOM uint32_t CSROUTE; /**< CS port/pin select */
+ __IOM uint32_t CTSROUTE; /**< CTS port/pin select */
+ __IOM uint32_t RTSROUTE; /**< RTS port/pin select */
+ __IOM uint32_t RXROUTE; /**< RX port/pin select */
+ __IOM uint32_t CLKROUTE; /**< SCLK port/pin select */
+ __IOM uint32_t TXROUTE; /**< TX port/pin select */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+} GPIO_USARTROUTE_TypeDef;
+
+typedef struct {
+ __IM uint32_t IPVERSION; /**< main */
+ uint32_t RESERVED0[11U]; /**< Reserved for future use */
+ GPIO_PORT_TypeDef P[4U]; /**< */
+ uint32_t RESERVED1[132U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK; /**< Lock Register */
+ uint32_t RESERVED2[3U]; /**< Reserved for future use */
+ __IM uint32_t GPIOLOCKSTATUS; /**< Lock Status */
+ uint32_t RESERVED3[3U]; /**< Reserved for future use */
+ __IOM uint32_t ABUSALLOC; /**< A Bus allocation */
+ __IOM uint32_t BBUSALLOC; /**< B Bus allocation */
+ __IOM uint32_t CDBUSALLOC; /**< CD Bus allocation */
+ uint32_t RESERVED4[53U]; /**< Reserved for future use */
+ __IOM uint32_t EXTIPSELL; /**< External Interrupt Port Select Low */
+ __IOM uint32_t EXTIPSELH; /**< External interrupt Port Select High */
+ __IOM uint32_t EXTIPINSELL; /**< External Interrupt Pin Select Low */
+ __IOM uint32_t EXTIPINSELH; /**< External Interrupt Pin Select High */
+ __IOM uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger */
+ __IOM uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger */
+ uint32_t RESERVED5[2U]; /**< Reserved for future use */
+ __IOM uint32_t IF; /**< Interrupt Flag */
+ __IOM uint32_t IEN; /**< Interrupt Enable */
+ uint32_t RESERVED6[1U]; /**< Reserved for future use */
+ __IOM uint32_t EM4WUEN; /**< EM4 wakeup enable */
+ __IOM uint32_t EM4WUPOL; /**< EM4 wakeup polarity */
+ uint32_t RESERVED7[3U]; /**< Reserved for future use */
+ __IOM uint32_t DBGROUTEPEN; /**< Debugger Route Pin enable */
+ __IOM uint32_t TRACEROUTEPEN; /**< Trace Route Pin Enable */
+ uint32_t RESERVED8[2U]; /**< Reserved for future use */
+ GPIO_ACMPROUTE_TypeDef ACMPROUTE[2U]; /**< acmp0 DBUS config registers */
+ GPIO_CMUROUTE_TypeDef CMUROUTE; /**< cmu DBUS config registers */
+ GPIO_DCDCROUTE_TypeDef DCDCROUTE; /**< dcdc DBUS config registers */
+ GPIO_EUSARTROUTE_TypeDef EUSARTROUTE[2U]; /**< eusart0 DBUS config registers */
+ GPIO_FRCROUTE_TypeDef FRCROUTE; /**< frc DBUS config registers */
+ GPIO_I2CROUTE_TypeDef I2CROUTE[2U]; /**< i2c0 DBUS config registers */
+ GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE; /**< keypad DBUS config registers */
+ GPIO_LETIMERROUTE_TypeDef LETIMERROUTE; /**< letimer DBUS config registers */
+ GPIO_MODEMROUTE_TypeDef MODEMROUTE; /**< modem DBUS config registers */
+ GPIO_PCNTROUTE_TypeDef PCNTROUTE[1U]; /**< pcnt0 DBUS config registers */
+ GPIO_PRSROUTE_TypeDef PRSROUTE[1U]; /**< prs0 DBUS config registers */
+ GPIO_RACROUTE_TypeDef RACROUTE; /**< rac DBUS config registers */
+ uint32_t RESERVED9[23U]; /**< Reserved for future use */
+ GPIO_SYXOROUTE_TypeDef SYXOROUTE[1U]; /**< syxo0 DBUS config registers */
+ GPIO_TIMERROUTE_TypeDef TIMERROUTE[5U]; /**< timer0 DBUS config registers */
+ GPIO_USARTROUTE_TypeDef USARTROUTE[1U]; /**< usart0 DBUS config registers */
+ uint32_t RESERVED10[560U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< main */
+ uint32_t RESERVED11[11U]; /**< Reserved for future use */
+ GPIO_PORT_TypeDef P_SET[4U]; /**< */
+ uint32_t RESERVED12[132U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK_SET; /**< Lock Register */
+ uint32_t RESERVED13[3U]; /**< Reserved for future use */
+ __IM uint32_t GPIOLOCKSTATUS_SET; /**< Lock Status */
+ uint32_t RESERVED14[3U]; /**< Reserved for future use */
+ __IOM uint32_t ABUSALLOC_SET; /**< A Bus allocation */
+ __IOM uint32_t BBUSALLOC_SET; /**< B Bus allocation */
+ __IOM uint32_t CDBUSALLOC_SET; /**< CD Bus allocation */
+ uint32_t RESERVED15[53U]; /**< Reserved for future use */
+ __IOM uint32_t EXTIPSELL_SET; /**< External Interrupt Port Select Low */
+ __IOM uint32_t EXTIPSELH_SET; /**< External interrupt Port Select High */
+ __IOM uint32_t EXTIPINSELL_SET; /**< External Interrupt Pin Select Low */
+ __IOM uint32_t EXTIPINSELH_SET; /**< External Interrupt Pin Select High */
+ __IOM uint32_t EXTIRISE_SET; /**< External Interrupt Rising Edge Trigger */
+ __IOM uint32_t EXTIFALL_SET; /**< External Interrupt Falling Edge Trigger */
+ uint32_t RESERVED16[2U]; /**< Reserved for future use */
+ __IOM uint32_t IF_SET; /**< Interrupt Flag */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable */
+ uint32_t RESERVED17[1U]; /**< Reserved for future use */
+ __IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup enable */
+ __IOM uint32_t EM4WUPOL_SET; /**< EM4 wakeup polarity */
+ uint32_t RESERVED18[3U]; /**< Reserved for future use */
+ __IOM uint32_t DBGROUTEPEN_SET; /**< Debugger Route Pin enable */
+ __IOM uint32_t TRACEROUTEPEN_SET; /**< Trace Route Pin Enable */
+ uint32_t RESERVED19[2U]; /**< Reserved for future use */
+ GPIO_ACMPROUTE_TypeDef ACMPROUTE_SET[2U]; /**< acmp0 DBUS config registers */
+ GPIO_CMUROUTE_TypeDef CMUROUTE_SET; /**< cmu DBUS config registers */
+ GPIO_DCDCROUTE_TypeDef DCDCROUTE_SET; /**< dcdc DBUS config registers */
+ GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_SET[2U]; /**< eusart0 DBUS config registers */
+ GPIO_FRCROUTE_TypeDef FRCROUTE_SET; /**< frc DBUS config registers */
+ GPIO_I2CROUTE_TypeDef I2CROUTE_SET[2U]; /**< i2c0 DBUS config registers */
+ GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE_SET; /**< keypad DBUS config registers */
+ GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_SET; /**< letimer DBUS config registers */
+ GPIO_MODEMROUTE_TypeDef MODEMROUTE_SET; /**< modem DBUS config registers */
+ GPIO_PCNTROUTE_TypeDef PCNTROUTE_SET[1U]; /**< pcnt0 DBUS config registers */
+ GPIO_PRSROUTE_TypeDef PRSROUTE_SET[1U]; /**< prs0 DBUS config registers */
+ GPIO_RACROUTE_TypeDef RACROUTE_SET; /**< rac DBUS config registers */
+ uint32_t RESERVED20[23U]; /**< Reserved for future use */
+ GPIO_SYXOROUTE_TypeDef SYXOROUTE_SET[1U]; /**< syxo0 DBUS config registers */
+ GPIO_TIMERROUTE_TypeDef TIMERROUTE_SET[5U]; /**< timer0 DBUS config registers */
+ GPIO_USARTROUTE_TypeDef USARTROUTE_SET[1U]; /**< usart0 DBUS config registers */
+ uint32_t RESERVED21[560U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< main */
+ uint32_t RESERVED22[11U]; /**< Reserved for future use */
+ GPIO_PORT_TypeDef P_CLR[4U]; /**< */
+ uint32_t RESERVED23[132U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK_CLR; /**< Lock Register */
+ uint32_t RESERVED24[3U]; /**< Reserved for future use */
+ __IM uint32_t GPIOLOCKSTATUS_CLR; /**< Lock Status */
+ uint32_t RESERVED25[3U]; /**< Reserved for future use */
+ __IOM uint32_t ABUSALLOC_CLR; /**< A Bus allocation */
+ __IOM uint32_t BBUSALLOC_CLR; /**< B Bus allocation */
+ __IOM uint32_t CDBUSALLOC_CLR; /**< CD Bus allocation */
+ uint32_t RESERVED26[53U]; /**< Reserved for future use */
+ __IOM uint32_t EXTIPSELL_CLR; /**< External Interrupt Port Select Low */
+ __IOM uint32_t EXTIPSELH_CLR; /**< External interrupt Port Select High */
+ __IOM uint32_t EXTIPINSELL_CLR; /**< External Interrupt Pin Select Low */
+ __IOM uint32_t EXTIPINSELH_CLR; /**< External Interrupt Pin Select High */
+ __IOM uint32_t EXTIRISE_CLR; /**< External Interrupt Rising Edge Trigger */
+ __IOM uint32_t EXTIFALL_CLR; /**< External Interrupt Falling Edge Trigger */
+ uint32_t RESERVED27[2U]; /**< Reserved for future use */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flag */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable */
+ uint32_t RESERVED28[1U]; /**< Reserved for future use */
+ __IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup enable */
+ __IOM uint32_t EM4WUPOL_CLR; /**< EM4 wakeup polarity */
+ uint32_t RESERVED29[3U]; /**< Reserved for future use */
+ __IOM uint32_t DBGROUTEPEN_CLR; /**< Debugger Route Pin enable */
+ __IOM uint32_t TRACEROUTEPEN_CLR; /**< Trace Route Pin Enable */
+ uint32_t RESERVED30[2U]; /**< Reserved for future use */
+ GPIO_ACMPROUTE_TypeDef ACMPROUTE_CLR[2U]; /**< acmp0 DBUS config registers */
+ GPIO_CMUROUTE_TypeDef CMUROUTE_CLR; /**< cmu DBUS config registers */
+ GPIO_DCDCROUTE_TypeDef DCDCROUTE_CLR; /**< dcdc DBUS config registers */
+ GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_CLR[2U]; /**< eusart0 DBUS config registers */
+ GPIO_FRCROUTE_TypeDef FRCROUTE_CLR; /**< frc DBUS config registers */
+ GPIO_I2CROUTE_TypeDef I2CROUTE_CLR[2U]; /**< i2c0 DBUS config registers */
+ GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE_CLR; /**< keypad DBUS config registers */
+ GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_CLR; /**< letimer DBUS config registers */
+ GPIO_MODEMROUTE_TypeDef MODEMROUTE_CLR; /**< modem DBUS config registers */
+ GPIO_PCNTROUTE_TypeDef PCNTROUTE_CLR[1U]; /**< pcnt0 DBUS config registers */
+ GPIO_PRSROUTE_TypeDef PRSROUTE_CLR[1U]; /**< prs0 DBUS config registers */
+ GPIO_RACROUTE_TypeDef RACROUTE_CLR; /**< rac DBUS config registers */
+ uint32_t RESERVED31[23U]; /**< Reserved for future use */
+ GPIO_SYXOROUTE_TypeDef SYXOROUTE_CLR[1U]; /**< syxo0 DBUS config registers */
+ GPIO_TIMERROUTE_TypeDef TIMERROUTE_CLR[5U]; /**< timer0 DBUS config registers */
+ GPIO_USARTROUTE_TypeDef USARTROUTE_CLR[1U]; /**< usart0 DBUS config registers */
+ uint32_t RESERVED32[560U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< main */
+ uint32_t RESERVED33[11U]; /**< Reserved for future use */
+ GPIO_PORT_TypeDef P_TGL[4U]; /**< */
+ uint32_t RESERVED34[132U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK_TGL; /**< Lock Register */
+ uint32_t RESERVED35[3U]; /**< Reserved for future use */
+ __IM uint32_t GPIOLOCKSTATUS_TGL; /**< Lock Status */
+ uint32_t RESERVED36[3U]; /**< Reserved for future use */
+ __IOM uint32_t ABUSALLOC_TGL; /**< A Bus allocation */
+ __IOM uint32_t BBUSALLOC_TGL; /**< B Bus allocation */
+ __IOM uint32_t CDBUSALLOC_TGL; /**< CD Bus allocation */
+ uint32_t RESERVED37[53U]; /**< Reserved for future use */
+ __IOM uint32_t EXTIPSELL_TGL; /**< External Interrupt Port Select Low */
+ __IOM uint32_t EXTIPSELH_TGL; /**< External interrupt Port Select High */
+ __IOM uint32_t EXTIPINSELL_TGL; /**< External Interrupt Pin Select Low */
+ __IOM uint32_t EXTIPINSELH_TGL; /**< External Interrupt Pin Select High */
+ __IOM uint32_t EXTIRISE_TGL; /**< External Interrupt Rising Edge Trigger */
+ __IOM uint32_t EXTIFALL_TGL; /**< External Interrupt Falling Edge Trigger */
+ uint32_t RESERVED38[2U]; /**< Reserved for future use */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flag */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable */
+ uint32_t RESERVED39[1U]; /**< Reserved for future use */
+ __IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup enable */
+ __IOM uint32_t EM4WUPOL_TGL; /**< EM4 wakeup polarity */
+ uint32_t RESERVED40[3U]; /**< Reserved for future use */
+ __IOM uint32_t DBGROUTEPEN_TGL; /**< Debugger Route Pin enable */
+ __IOM uint32_t TRACEROUTEPEN_TGL; /**< Trace Route Pin Enable */
+ uint32_t RESERVED41[2U]; /**< Reserved for future use */
+ GPIO_ACMPROUTE_TypeDef ACMPROUTE_TGL[2U]; /**< acmp0 DBUS config registers */
+ GPIO_CMUROUTE_TypeDef CMUROUTE_TGL; /**< cmu DBUS config registers */
+ GPIO_DCDCROUTE_TypeDef DCDCROUTE_TGL; /**< dcdc DBUS config registers */
+ GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_TGL[2U]; /**< eusart0 DBUS config registers */
+ GPIO_FRCROUTE_TypeDef FRCROUTE_TGL; /**< frc DBUS config registers */
+ GPIO_I2CROUTE_TypeDef I2CROUTE_TGL[2U]; /**< i2c0 DBUS config registers */
+ GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE_TGL; /**< keypad DBUS config registers */
+ GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_TGL; /**< letimer DBUS config registers */
+ GPIO_MODEMROUTE_TypeDef MODEMROUTE_TGL; /**< modem DBUS config registers */
+ GPIO_PCNTROUTE_TypeDef PCNTROUTE_TGL[1U]; /**< pcnt0 DBUS config registers */
+ GPIO_PRSROUTE_TypeDef PRSROUTE_TGL[1U]; /**< prs0 DBUS config registers */
+ GPIO_RACROUTE_TypeDef RACROUTE_TGL; /**< rac DBUS config registers */
+ uint32_t RESERVED42[23U]; /**< Reserved for future use */
+ GPIO_SYXOROUTE_TypeDef SYXOROUTE_TGL[1U]; /**< syxo0 DBUS config registers */
+ GPIO_TIMERROUTE_TypeDef TIMERROUTE_TGL[5U]; /**< timer0 DBUS config registers */
+ GPIO_USARTROUTE_TypeDef USARTROUTE_TGL[1U]; /**< usart0 DBUS config registers */
+} GPIO_TypeDef;
+
+/* Bit fields for GPIO IPVERSION */
+#define _GPIO_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for GPIO_IPVERSION */
+#define _GPIO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IPVERSION */
+#define _GPIO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for GPIO_IPVERSION */
+#define _GPIO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for GPIO_IPVERSION */
+#define _GPIO_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_IPVERSION */
+#define GPIO_IPVERSION_IPVERSION_DEFAULT (_GPIO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IPVERSION */
+#define GPIO_PORTA 0x00000000UL /**< PORTA index */
+#define GPIO_PORTB 0x00000001UL /**< PORTB index */
+#define GPIO_PORTC 0x00000002UL /**< PORTC index */
+#define GPIO_PORTD 0x00000003UL /**< PORTD index */
+
+/* Bit fields for GPIO LOCK */
+#define _GPIO_LOCK_RESETVALUE 0x0000A534UL /**< Default value for GPIO_LOCK */
+#define _GPIO_LOCK_MASK 0x0000FFFFUL /**< Mask for GPIO_LOCK */
+#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */
+#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */
+#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x0000A534UL /**< Mode DEFAULT for GPIO_LOCK */
+#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */
+#define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */
+#define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */
+
+/* Bit fields for GPIO GPIOLOCKSTATUS */
+#define _GPIO_GPIOLOCKSTATUS_RESETVALUE 0x00000000UL /**< Default value for GPIO_GPIOLOCKSTATUS */
+#define _GPIO_GPIOLOCKSTATUS_MASK 0x00000001UL /**< Mask for GPIO_GPIOLOCKSTATUS */
+#define GPIO_GPIOLOCKSTATUS_LOCK (0x1UL << 0) /**< GPIO LOCK status */
+#define _GPIO_GPIOLOCKSTATUS_LOCK_SHIFT 0 /**< Shift value for GPIO_LOCK */
+#define _GPIO_GPIOLOCKSTATUS_LOCK_MASK 0x1UL /**< Bit mask for GPIO_LOCK */
+#define _GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_GPIOLOCKSTATUS */
+#define _GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_GPIOLOCKSTATUS */
+#define _GPIO_GPIOLOCKSTATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_GPIOLOCKSTATUS */
+#define GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT (_GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_GPIOLOCKSTATUS*/
+#define GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED (_GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_GPIOLOCKSTATUS*/
+#define GPIO_GPIOLOCKSTATUS_LOCK_LOCKED (_GPIO_GPIOLOCKSTATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_GPIOLOCKSTATUS */
+
+/* Bit fields for GPIO ABUSALLOC */
+#define _GPIO_ABUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AEVEN0_SHIFT 0 /**< Shift value for GPIO_AEVEN0 */
+#define _GPIO_ABUSALLOC_AEVEN0_MASK 0xFUL /**< Bit mask for GPIO_AEVEN0 */
+#define _GPIO_ABUSALLOC_AEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AEVEN0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AEVEN0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AEVEN0_VDAC1CH0 0x00000005UL /**< Mode VDAC1CH0 for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AEVEN0_DIAGA 0x0000000EUL /**< Mode DIAGA for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AEVEN0_DEBUG 0x0000000FUL /**< Mode DEBUG for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AEVEN0_DEFAULT (_GPIO_ABUSALLOC_AEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AEVEN0_TRISTATE (_GPIO_ABUSALLOC_AEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AEVEN0_ADC0 (_GPIO_ABUSALLOC_AEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AEVEN0_ACMP0 (_GPIO_ABUSALLOC_AEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AEVEN0_ACMP1 (_GPIO_ABUSALLOC_AEVEN0_ACMP1 << 0) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AEVEN0_VDAC0CH0 (_GPIO_ABUSALLOC_AEVEN0_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AEVEN0_VDAC1CH0 (_GPIO_ABUSALLOC_AEVEN0_VDAC1CH0 << 0) /**< Shifted mode VDAC1CH0 for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AEVEN0_DIAGA (_GPIO_ABUSALLOC_AEVEN0_DIAGA << 0) /**< Shifted mode DIAGA for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AEVEN0_DEBUG (_GPIO_ABUSALLOC_AEVEN0_DEBUG << 0) /**< Shifted mode DEBUG for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AEVEN1_SHIFT 8 /**< Shift value for GPIO_AEVEN1 */
+#define _GPIO_ABUSALLOC_AEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_AEVEN1 */
+#define _GPIO_ABUSALLOC_AEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AEVEN1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AEVEN1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AEVEN1_VDAC1CH1 0x00000005UL /**< Mode VDAC1CH1 for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AEVEN1_DEBUG 0x0000000FUL /**< Mode DEBUG for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AEVEN1_DEFAULT (_GPIO_ABUSALLOC_AEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AEVEN1_TRISTATE (_GPIO_ABUSALLOC_AEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AEVEN1_ADC0 (_GPIO_ABUSALLOC_AEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AEVEN1_ACMP0 (_GPIO_ABUSALLOC_AEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AEVEN1_ACMP1 (_GPIO_ABUSALLOC_AEVEN1_ACMP1 << 8) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AEVEN1_VDAC0CH1 (_GPIO_ABUSALLOC_AEVEN1_VDAC0CH1 << 8) /**< Shifted mode VDAC0CH1 for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AEVEN1_VDAC1CH1 (_GPIO_ABUSALLOC_AEVEN1_VDAC1CH1 << 8) /**< Shifted mode VDAC1CH1 for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AEVEN1_DEBUG (_GPIO_ABUSALLOC_AEVEN1_DEBUG << 8) /**< Shifted mode DEBUG for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AODD0_SHIFT 16 /**< Shift value for GPIO_AODD0 */
+#define _GPIO_ABUSALLOC_AODD0_MASK 0xF0000UL /**< Bit mask for GPIO_AODD0 */
+#define _GPIO_ABUSALLOC_AODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AODD0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AODD0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AODD0_VDAC1CH0 0x00000005UL /**< Mode VDAC1CH0 for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AODD0_DIAGA 0x0000000EUL /**< Mode DIAGA for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AODD0_DEBUG 0x0000000FUL /**< Mode DEBUG for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AODD0_DEFAULT (_GPIO_ABUSALLOC_AODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AODD0_TRISTATE (_GPIO_ABUSALLOC_AODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AODD0_ADC0 (_GPIO_ABUSALLOC_AODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AODD0_ACMP0 (_GPIO_ABUSALLOC_AODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AODD0_ACMP1 (_GPIO_ABUSALLOC_AODD0_ACMP1 << 16) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AODD0_VDAC0CH0 (_GPIO_ABUSALLOC_AODD0_VDAC0CH0 << 16) /**< Shifted mode VDAC0CH0 for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AODD0_VDAC1CH0 (_GPIO_ABUSALLOC_AODD0_VDAC1CH0 << 16) /**< Shifted mode VDAC1CH0 for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AODD0_DIAGA (_GPIO_ABUSALLOC_AODD0_DIAGA << 16) /**< Shifted mode DIAGA for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AODD0_DEBUG (_GPIO_ABUSALLOC_AODD0_DEBUG << 16) /**< Shifted mode DEBUG for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AODD1_SHIFT 24 /**< Shift value for GPIO_AODD1 */
+#define _GPIO_ABUSALLOC_AODD1_MASK 0xF000000UL /**< Bit mask for GPIO_AODD1 */
+#define _GPIO_ABUSALLOC_AODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AODD1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AODD1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AODD1_VDAC1CH1 0x00000005UL /**< Mode VDAC1CH1 for GPIO_ABUSALLOC */
+#define _GPIO_ABUSALLOC_AODD1_DEBUG 0x0000000FUL /**< Mode DEBUG for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AODD1_DEFAULT (_GPIO_ABUSALLOC_AODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AODD1_TRISTATE (_GPIO_ABUSALLOC_AODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AODD1_ADC0 (_GPIO_ABUSALLOC_AODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AODD1_ACMP0 (_GPIO_ABUSALLOC_AODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AODD1_ACMP1 (_GPIO_ABUSALLOC_AODD1_ACMP1 << 24) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AODD1_VDAC0CH1 (_GPIO_ABUSALLOC_AODD1_VDAC0CH1 << 24) /**< Shifted mode VDAC0CH1 for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AODD1_VDAC1CH1 (_GPIO_ABUSALLOC_AODD1_VDAC1CH1 << 24) /**< Shifted mode VDAC1CH1 for GPIO_ABUSALLOC */
+#define GPIO_ABUSALLOC_AODD1_DEBUG (_GPIO_ABUSALLOC_AODD1_DEBUG << 24) /**< Shifted mode DEBUG for GPIO_ABUSALLOC */
+
+/* Bit fields for GPIO BBUSALLOC */
+#define _GPIO_BBUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BEVEN0_SHIFT 0 /**< Shift value for GPIO_BEVEN0 */
+#define _GPIO_BBUSALLOC_BEVEN0_MASK 0xFUL /**< Bit mask for GPIO_BEVEN0 */
+#define _GPIO_BBUSALLOC_BEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BEVEN0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BEVEN0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BEVEN0_VDAC1CH0 0x00000005UL /**< Mode VDAC1CH0 for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BEVEN0_DEBUG 0x0000000FUL /**< Mode DEBUG for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BEVEN0_DEFAULT (_GPIO_BBUSALLOC_BEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BEVEN0_TRISTATE (_GPIO_BBUSALLOC_BEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BEVEN0_ADC0 (_GPIO_BBUSALLOC_BEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BEVEN0_ACMP0 (_GPIO_BBUSALLOC_BEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BEVEN0_ACMP1 (_GPIO_BBUSALLOC_BEVEN0_ACMP1 << 0) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BEVEN0_VDAC0CH0 (_GPIO_BBUSALLOC_BEVEN0_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BEVEN0_VDAC1CH0 (_GPIO_BBUSALLOC_BEVEN0_VDAC1CH0 << 0) /**< Shifted mode VDAC1CH0 for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BEVEN0_DEBUG (_GPIO_BBUSALLOC_BEVEN0_DEBUG << 0) /**< Shifted mode DEBUG for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BEVEN1_SHIFT 8 /**< Shift value for GPIO_BEVEN1 */
+#define _GPIO_BBUSALLOC_BEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_BEVEN1 */
+#define _GPIO_BBUSALLOC_BEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BEVEN1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BEVEN1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BEVEN1_VDAC1CH1 0x00000005UL /**< Mode VDAC1CH1 for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BEVEN1_DEBUG 0x0000000FUL /**< Mode DEBUG for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BEVEN1_DEFAULT (_GPIO_BBUSALLOC_BEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BEVEN1_TRISTATE (_GPIO_BBUSALLOC_BEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BEVEN1_ADC0 (_GPIO_BBUSALLOC_BEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BEVEN1_ACMP0 (_GPIO_BBUSALLOC_BEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BEVEN1_ACMP1 (_GPIO_BBUSALLOC_BEVEN1_ACMP1 << 8) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BEVEN1_VDAC0CH1 (_GPIO_BBUSALLOC_BEVEN1_VDAC0CH1 << 8) /**< Shifted mode VDAC0CH1 for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BEVEN1_VDAC1CH1 (_GPIO_BBUSALLOC_BEVEN1_VDAC1CH1 << 8) /**< Shifted mode VDAC1CH1 for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BEVEN1_DEBUG (_GPIO_BBUSALLOC_BEVEN1_DEBUG << 8) /**< Shifted mode DEBUG for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BODD0_SHIFT 16 /**< Shift value for GPIO_BODD0 */
+#define _GPIO_BBUSALLOC_BODD0_MASK 0xF0000UL /**< Bit mask for GPIO_BODD0 */
+#define _GPIO_BBUSALLOC_BODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BODD0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BODD0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BODD0_VDAC1CH0 0x00000005UL /**< Mode VDAC1CH0 for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BODD0_DEBUG 0x0000000FUL /**< Mode DEBUG for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BODD0_DEFAULT (_GPIO_BBUSALLOC_BODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BODD0_TRISTATE (_GPIO_BBUSALLOC_BODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BODD0_ADC0 (_GPIO_BBUSALLOC_BODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BODD0_ACMP0 (_GPIO_BBUSALLOC_BODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BODD0_ACMP1 (_GPIO_BBUSALLOC_BODD0_ACMP1 << 16) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BODD0_VDAC0CH0 (_GPIO_BBUSALLOC_BODD0_VDAC0CH0 << 16) /**< Shifted mode VDAC0CH0 for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BODD0_VDAC1CH0 (_GPIO_BBUSALLOC_BODD0_VDAC1CH0 << 16) /**< Shifted mode VDAC1CH0 for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BODD0_DEBUG (_GPIO_BBUSALLOC_BODD0_DEBUG << 16) /**< Shifted mode DEBUG for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BODD1_SHIFT 24 /**< Shift value for GPIO_BODD1 */
+#define _GPIO_BBUSALLOC_BODD1_MASK 0xF000000UL /**< Bit mask for GPIO_BODD1 */
+#define _GPIO_BBUSALLOC_BODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BODD1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BODD1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BODD1_VDAC1CH1 0x00000005UL /**< Mode VDAC1CH1 for GPIO_BBUSALLOC */
+#define _GPIO_BBUSALLOC_BODD1_DEBUG 0x0000000FUL /**< Mode DEBUG for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BODD1_DEFAULT (_GPIO_BBUSALLOC_BODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BODD1_TRISTATE (_GPIO_BBUSALLOC_BODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BODD1_ADC0 (_GPIO_BBUSALLOC_BODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BODD1_ACMP0 (_GPIO_BBUSALLOC_BODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BODD1_ACMP1 (_GPIO_BBUSALLOC_BODD1_ACMP1 << 24) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BODD1_VDAC0CH1 (_GPIO_BBUSALLOC_BODD1_VDAC0CH1 << 24) /**< Shifted mode VDAC0CH1 for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BODD1_VDAC1CH1 (_GPIO_BBUSALLOC_BODD1_VDAC1CH1 << 24) /**< Shifted mode VDAC1CH1 for GPIO_BBUSALLOC */
+#define GPIO_BBUSALLOC_BODD1_DEBUG (_GPIO_BBUSALLOC_BODD1_DEBUG << 24) /**< Shifted mode DEBUG for GPIO_BBUSALLOC */
+
+/* Bit fields for GPIO CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDEVEN0_SHIFT 0 /**< Shift value for GPIO_CDEVEN0 */
+#define _GPIO_CDBUSALLOC_CDEVEN0_MASK 0xFUL /**< Bit mask for GPIO_CDEVEN0 */
+#define _GPIO_CDBUSALLOC_CDEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDEVEN0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDEVEN0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDEVEN0_VDAC1CH0 0x00000005UL /**< Mode VDAC1CH0 for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDEVEN0_REPEFUSE 0x0000000BUL /**< Mode REPEFUSE for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDEVEN0_PMON 0x0000000CUL /**< Mode PMON for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDEVEN0_EFUSE 0x0000000DUL /**< Mode EFUSE for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDEVEN0_DEBUG 0x0000000FUL /**< Mode DEBUG for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDEVEN0_DEFAULT (_GPIO_CDBUSALLOC_CDEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDEVEN0_TRISTATE (_GPIO_CDBUSALLOC_CDEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDEVEN0_ADC0 (_GPIO_CDBUSALLOC_CDEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDEVEN0_ACMP0 (_GPIO_CDBUSALLOC_CDEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDEVEN0_ACMP1 (_GPIO_CDBUSALLOC_CDEVEN0_ACMP1 << 0) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDEVEN0_VDAC0CH0 (_GPIO_CDBUSALLOC_CDEVEN0_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDEVEN0_VDAC1CH0 (_GPIO_CDBUSALLOC_CDEVEN0_VDAC1CH0 << 0) /**< Shifted mode VDAC1CH0 for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDEVEN0_REPEFUSE (_GPIO_CDBUSALLOC_CDEVEN0_REPEFUSE << 0) /**< Shifted mode REPEFUSE for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDEVEN0_PMON (_GPIO_CDBUSALLOC_CDEVEN0_PMON << 0) /**< Shifted mode PMON for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDEVEN0_EFUSE (_GPIO_CDBUSALLOC_CDEVEN0_EFUSE << 0) /**< Shifted mode EFUSE for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDEVEN0_DEBUG (_GPIO_CDBUSALLOC_CDEVEN0_DEBUG << 0) /**< Shifted mode DEBUG for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDEVEN1_SHIFT 8 /**< Shift value for GPIO_CDEVEN1 */
+#define _GPIO_CDBUSALLOC_CDEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_CDEVEN1 */
+#define _GPIO_CDBUSALLOC_CDEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDEVEN1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDEVEN1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDEVEN1_VDAC1CH1 0x00000005UL /**< Mode VDAC1CH1 for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDEVEN1_DEBUG 0x0000000FUL /**< Mode DEBUG for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDEVEN1_DEFAULT (_GPIO_CDBUSALLOC_CDEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDEVEN1_TRISTATE (_GPIO_CDBUSALLOC_CDEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDEVEN1_ADC0 (_GPIO_CDBUSALLOC_CDEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDEVEN1_ACMP0 (_GPIO_CDBUSALLOC_CDEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDEVEN1_ACMP1 (_GPIO_CDBUSALLOC_CDEVEN1_ACMP1 << 8) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDEVEN1_VDAC0CH1 (_GPIO_CDBUSALLOC_CDEVEN1_VDAC0CH1 << 8) /**< Shifted mode VDAC0CH1 for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDEVEN1_VDAC1CH1 (_GPIO_CDBUSALLOC_CDEVEN1_VDAC1CH1 << 8) /**< Shifted mode VDAC1CH1 for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDEVEN1_DEBUG (_GPIO_CDBUSALLOC_CDEVEN1_DEBUG << 8) /**< Shifted mode DEBUG for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDODD0_SHIFT 16 /**< Shift value for GPIO_CDODD0 */
+#define _GPIO_CDBUSALLOC_CDODD0_MASK 0xF0000UL /**< Bit mask for GPIO_CDODD0 */
+#define _GPIO_CDBUSALLOC_CDODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDODD0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDODD0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDODD0_VDAC1CH0 0x00000005UL /**< Mode VDAC1CH0 for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDODD0_PMON 0x0000000CUL /**< Mode PMON for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDODD0_DEBUG 0x0000000FUL /**< Mode DEBUG for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDODD0_DEFAULT (_GPIO_CDBUSALLOC_CDODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDODD0_TRISTATE (_GPIO_CDBUSALLOC_CDODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDODD0_ADC0 (_GPIO_CDBUSALLOC_CDODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDODD0_ACMP0 (_GPIO_CDBUSALLOC_CDODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDODD0_ACMP1 (_GPIO_CDBUSALLOC_CDODD0_ACMP1 << 16) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDODD0_VDAC0CH0 (_GPIO_CDBUSALLOC_CDODD0_VDAC0CH0 << 16) /**< Shifted mode VDAC0CH0 for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDODD0_VDAC1CH0 (_GPIO_CDBUSALLOC_CDODD0_VDAC1CH0 << 16) /**< Shifted mode VDAC1CH0 for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDODD0_PMON (_GPIO_CDBUSALLOC_CDODD0_PMON << 16) /**< Shifted mode PMON for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDODD0_DEBUG (_GPIO_CDBUSALLOC_CDODD0_DEBUG << 16) /**< Shifted mode DEBUG for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDODD1_SHIFT 24 /**< Shift value for GPIO_CDODD1 */
+#define _GPIO_CDBUSALLOC_CDODD1_MASK 0xF000000UL /**< Bit mask for GPIO_CDODD1 */
+#define _GPIO_CDBUSALLOC_CDODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDODD1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDODD1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDODD1_VDAC1CH1 0x00000005UL /**< Mode VDAC1CH1 for GPIO_CDBUSALLOC */
+#define _GPIO_CDBUSALLOC_CDODD1_DEBUG 0x0000000FUL /**< Mode DEBUG for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDODD1_DEFAULT (_GPIO_CDBUSALLOC_CDODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDODD1_TRISTATE (_GPIO_CDBUSALLOC_CDODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDODD1_ADC0 (_GPIO_CDBUSALLOC_CDODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDODD1_ACMP0 (_GPIO_CDBUSALLOC_CDODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDODD1_ACMP1 (_GPIO_CDBUSALLOC_CDODD1_ACMP1 << 24) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDODD1_VDAC0CH1 (_GPIO_CDBUSALLOC_CDODD1_VDAC0CH1 << 24) /**< Shifted mode VDAC0CH1 for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDODD1_VDAC1CH1 (_GPIO_CDBUSALLOC_CDODD1_VDAC1CH1 << 24) /**< Shifted mode VDAC1CH1 for GPIO_CDBUSALLOC */
+#define GPIO_CDBUSALLOC_CDODD1_DEBUG (_GPIO_CDBUSALLOC_CDODD1_DEBUG << 24) /**< Shifted mode DEBUG for GPIO_CDBUSALLOC */
+
+/* Bit fields for GPIO EXTIPSELL */
+#define _GPIO_EXTIPSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */
+#define _GPIO_EXTIPSELL_EXTIPSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPSEL0 */
+#define _GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL0_PORTA (_GPIO_EXTIPSELL_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL0_PORTB (_GPIO_EXTIPSELL_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL0_PORTC (_GPIO_EXTIPSELL_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL0_PORTD (_GPIO_EXTIPSELL_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */
+#define _GPIO_EXTIPSELL_EXTIPSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPSEL1 */
+#define _GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL1_PORTA (_GPIO_EXTIPSELL_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL1_PORTB (_GPIO_EXTIPSELL_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL1_PORTC (_GPIO_EXTIPSELL_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL1_PORTD (_GPIO_EXTIPSELL_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */
+#define _GPIO_EXTIPSELL_EXTIPSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPSEL2 */
+#define _GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL2_PORTA (_GPIO_EXTIPSELL_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL2_PORTB (_GPIO_EXTIPSELL_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL2_PORTC (_GPIO_EXTIPSELL_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL2_PORTD (_GPIO_EXTIPSELL_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */
+#define _GPIO_EXTIPSELL_EXTIPSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPSEL3 */
+#define _GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL3_PORTA (_GPIO_EXTIPSELL_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL3_PORTB (_GPIO_EXTIPSELL_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL3_PORTC (_GPIO_EXTIPSELL_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL3_PORTD (_GPIO_EXTIPSELL_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL4 */
+#define _GPIO_EXTIPSELL_EXTIPSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPSEL4 */
+#define _GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL4_PORTA (_GPIO_EXTIPSELL_EXTIPSEL4_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL4_PORTB (_GPIO_EXTIPSELL_EXTIPSEL4_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL4_PORTC (_GPIO_EXTIPSELL_EXTIPSEL4_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL4_PORTD (_GPIO_EXTIPSELL_EXTIPSEL4_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL5 */
+#define _GPIO_EXTIPSELL_EXTIPSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPSEL5 */
+#define _GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL5_PORTA (_GPIO_EXTIPSELL_EXTIPSEL5_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL5_PORTB (_GPIO_EXTIPSELL_EXTIPSEL5_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL5_PORTC (_GPIO_EXTIPSELL_EXTIPSEL5_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL5_PORTD (_GPIO_EXTIPSELL_EXTIPSEL5_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL6 */
+#define _GPIO_EXTIPSELL_EXTIPSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPSEL6 */
+#define _GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL6_PORTA (_GPIO_EXTIPSELL_EXTIPSEL6_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL6_PORTB (_GPIO_EXTIPSELL_EXTIPSEL6_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL6_PORTC (_GPIO_EXTIPSELL_EXTIPSEL6_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL6_PORTD (_GPIO_EXTIPSELL_EXTIPSEL6_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL7 */
+#define _GPIO_EXTIPSELL_EXTIPSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPSEL7 */
+#define _GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
+#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL7_PORTA (_GPIO_EXTIPSELL_EXTIPSEL7_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL7_PORTB (_GPIO_EXTIPSELL_EXTIPSEL7_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL7_PORTC (_GPIO_EXTIPSELL_EXTIPSEL7_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
+#define GPIO_EXTIPSELL_EXTIPSEL7_PORTD (_GPIO_EXTIPSELL_EXTIPSEL7_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
+
+/* Bit fields for GPIO EXTIPSELH */
+#define _GPIO_EXTIPSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_MASK 0x00003333UL /**< Mask for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */
+#define _GPIO_EXTIPSELH_EXTIPSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPSEL0 */
+#define _GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL0_PORTA (_GPIO_EXTIPSELH_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL0_PORTB (_GPIO_EXTIPSELH_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL0_PORTC (_GPIO_EXTIPSELH_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL0_PORTD (_GPIO_EXTIPSELH_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */
+#define _GPIO_EXTIPSELH_EXTIPSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPSEL1 */
+#define _GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL1_PORTA (_GPIO_EXTIPSELH_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL1_PORTB (_GPIO_EXTIPSELH_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL1_PORTC (_GPIO_EXTIPSELH_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL1_PORTD (_GPIO_EXTIPSELH_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */
+#define _GPIO_EXTIPSELH_EXTIPSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPSEL2 */
+#define _GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL2_PORTA (_GPIO_EXTIPSELH_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL2_PORTB (_GPIO_EXTIPSELH_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL2_PORTC (_GPIO_EXTIPSELH_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL2_PORTD (_GPIO_EXTIPSELH_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */
+#define _GPIO_EXTIPSELH_EXTIPSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPSEL3 */
+#define _GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */
+#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL3_PORTA (_GPIO_EXTIPSELH_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL3_PORTB (_GPIO_EXTIPSELH_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL3_PORTC (_GPIO_EXTIPSELH_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELH */
+#define GPIO_EXTIPSELH_EXTIPSEL3_PORTD (_GPIO_EXTIPSELH_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELH */
+
+/* Bit fields for GPIO EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 << 0) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 << 0) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 << 0) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 << 0) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 << 4) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 << 4) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 << 4) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 << 4) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 << 8) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 << 8) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 << 8) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 << 8) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 << 12) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 << 12) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 << 12) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 << 12) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL4 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL4 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 << 16) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 << 16) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 << 16) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 << 16) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL5 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL5 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 << 20) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 << 20) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 << 20) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 << 20) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL6 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL6 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 << 24) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 << 24) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 << 24) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 << 24) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL7 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL7 */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */
+#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 << 28) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 << 28) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 << 28) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */
+#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 << 28) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */
+
+/* Bit fields for GPIO EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_MASK 0x00003333UL /**< Mask for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 << 0) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 << 0) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 << 0) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 << 0) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 << 4) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 << 4) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 << 4) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 << 4) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 << 8) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 << 8) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 << 8) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 << 8) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */
+#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 << 12) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 << 12) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 << 12) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */
+#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 << 12) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */
+
+/* Bit fields for GPIO EXTIRISE */
+#define _GPIO_EXTIRISE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIRISE */
+#define _GPIO_EXTIRISE_MASK 0x00000FFFUL /**< Mask for GPIO_EXTIRISE */
+#define _GPIO_EXTIRISE_EXTIRISE_SHIFT 0 /**< Shift value for GPIO_EXTIRISE */
+#define _GPIO_EXTIRISE_EXTIRISE_MASK 0xFFFUL /**< Bit mask for GPIO_EXTIRISE */
+#define _GPIO_EXTIRISE_EXTIRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIRISE */
+#define GPIO_EXTIRISE_EXTIRISE_DEFAULT (_GPIO_EXTIRISE_EXTIRISE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIRISE */
+
+/* Bit fields for GPIO EXTIFALL */
+#define _GPIO_EXTIFALL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIFALL */
+#define _GPIO_EXTIFALL_MASK 0x00000FFFUL /**< Mask for GPIO_EXTIFALL */
+#define _GPIO_EXTIFALL_EXTIFALL_SHIFT 0 /**< Shift value for GPIO_EXTIFALL */
+#define _GPIO_EXTIFALL_EXTIFALL_MASK 0xFFFUL /**< Bit mask for GPIO_EXTIFALL */
+#define _GPIO_EXTIFALL_EXTIFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIFALL */
+#define GPIO_EXTIFALL_EXTIFALL_DEFAULT (_GPIO_EXTIFALL_EXTIFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIFALL */
+
+/* Bit fields for GPIO IF */
+#define _GPIO_IF_RESETVALUE 0x00000000UL /**< Default value for GPIO_IF */
+#define _GPIO_IF_MASK 0x0FFF0FFFUL /**< Mask for GPIO_IF */
+#define GPIO_IF_EXTIF0 (0x1UL << 0) /**< External Pin Flag */
+#define _GPIO_IF_EXTIF0_SHIFT 0 /**< Shift value for GPIO_EXTIF0 */
+#define _GPIO_IF_EXTIF0_MASK 0x1UL /**< Bit mask for GPIO_EXTIF0 */
+#define _GPIO_IF_EXTIF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */
+#define GPIO_IF_EXTIF0_DEFAULT (_GPIO_IF_EXTIF0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IF */
+#define GPIO_IF_EXTIF1 (0x1UL << 1) /**< External Pin Flag */
+#define _GPIO_IF_EXTIF1_SHIFT 1 /**< Shift value for GPIO_EXTIF1 */
+#define _GPIO_IF_EXTIF1_MASK 0x2UL /**< Bit mask for GPIO_EXTIF1 */
+#define _GPIO_IF_EXTIF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */
+#define GPIO_IF_EXTIF1_DEFAULT (_GPIO_IF_EXTIF1_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_IF */
+#define GPIO_IF_EXTIF2 (0x1UL << 2) /**< External Pin Flag */
+#define _GPIO_IF_EXTIF2_SHIFT 2 /**< Shift value for GPIO_EXTIF2 */
+#define _GPIO_IF_EXTIF2_MASK 0x4UL /**< Bit mask for GPIO_EXTIF2 */
+#define _GPIO_IF_EXTIF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */
+#define GPIO_IF_EXTIF2_DEFAULT (_GPIO_IF_EXTIF2_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_IF */
+#define GPIO_IF_EXTIF3 (0x1UL << 3) /**< External Pin Flag */
+#define _GPIO_IF_EXTIF3_SHIFT 3 /**< Shift value for GPIO_EXTIF3 */
+#define _GPIO_IF_EXTIF3_MASK 0x8UL /**< Bit mask for GPIO_EXTIF3 */
+#define _GPIO_IF_EXTIF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */
+#define GPIO_IF_EXTIF3_DEFAULT (_GPIO_IF_EXTIF3_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_IF */
+#define GPIO_IF_EXTIF4 (0x1UL << 4) /**< External Pin Flag */
+#define _GPIO_IF_EXTIF4_SHIFT 4 /**< Shift value for GPIO_EXTIF4 */
+#define _GPIO_IF_EXTIF4_MASK 0x10UL /**< Bit mask for GPIO_EXTIF4 */
+#define _GPIO_IF_EXTIF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */
+#define GPIO_IF_EXTIF4_DEFAULT (_GPIO_IF_EXTIF4_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_IF */
+#define GPIO_IF_EXTIF5 (0x1UL << 5) /**< External Pin Flag */
+#define _GPIO_IF_EXTIF5_SHIFT 5 /**< Shift value for GPIO_EXTIF5 */
+#define _GPIO_IF_EXTIF5_MASK 0x20UL /**< Bit mask for GPIO_EXTIF5 */
+#define _GPIO_IF_EXTIF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */
+#define GPIO_IF_EXTIF5_DEFAULT (_GPIO_IF_EXTIF5_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_IF */
+#define GPIO_IF_EXTIF6 (0x1UL << 6) /**< External Pin Flag */
+#define _GPIO_IF_EXTIF6_SHIFT 6 /**< Shift value for GPIO_EXTIF6 */
+#define _GPIO_IF_EXTIF6_MASK 0x40UL /**< Bit mask for GPIO_EXTIF6 */
+#define _GPIO_IF_EXTIF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */
+#define GPIO_IF_EXTIF6_DEFAULT (_GPIO_IF_EXTIF6_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_IF */
+#define GPIO_IF_EXTIF7 (0x1UL << 7) /**< External Pin Flag */
+#define _GPIO_IF_EXTIF7_SHIFT 7 /**< Shift value for GPIO_EXTIF7 */
+#define _GPIO_IF_EXTIF7_MASK 0x80UL /**< Bit mask for GPIO_EXTIF7 */
+#define _GPIO_IF_EXTIF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */
+#define GPIO_IF_EXTIF7_DEFAULT (_GPIO_IF_EXTIF7_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_IF */
+#define GPIO_IF_EXTIF8 (0x1UL << 8) /**< External Pin Flag */
+#define _GPIO_IF_EXTIF8_SHIFT 8 /**< Shift value for GPIO_EXTIF8 */
+#define _GPIO_IF_EXTIF8_MASK 0x100UL /**< Bit mask for GPIO_EXTIF8 */
+#define _GPIO_IF_EXTIF8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */
+#define GPIO_IF_EXTIF8_DEFAULT (_GPIO_IF_EXTIF8_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_IF */
+#define GPIO_IF_EXTIF9 (0x1UL << 9) /**< External Pin Flag */
+#define _GPIO_IF_EXTIF9_SHIFT 9 /**< Shift value for GPIO_EXTIF9 */
+#define _GPIO_IF_EXTIF9_MASK 0x200UL /**< Bit mask for GPIO_EXTIF9 */
+#define _GPIO_IF_EXTIF9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */
+#define GPIO_IF_EXTIF9_DEFAULT (_GPIO_IF_EXTIF9_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_IF */
+#define GPIO_IF_EXTIF10 (0x1UL << 10) /**< External Pin Flag */
+#define _GPIO_IF_EXTIF10_SHIFT 10 /**< Shift value for GPIO_EXTIF10 */
+#define _GPIO_IF_EXTIF10_MASK 0x400UL /**< Bit mask for GPIO_EXTIF10 */
+#define _GPIO_IF_EXTIF10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */
+#define GPIO_IF_EXTIF10_DEFAULT (_GPIO_IF_EXTIF10_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_IF */
+#define GPIO_IF_EXTIF11 (0x1UL << 11) /**< External Pin Flag */
+#define _GPIO_IF_EXTIF11_SHIFT 11 /**< Shift value for GPIO_EXTIF11 */
+#define _GPIO_IF_EXTIF11_MASK 0x800UL /**< Bit mask for GPIO_EXTIF11 */
+#define _GPIO_IF_EXTIF11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */
+#define GPIO_IF_EXTIF11_DEFAULT (_GPIO_IF_EXTIF11_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_IF */
+#define _GPIO_IF_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */
+#define _GPIO_IF_EM4WU_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WU */
+#define _GPIO_IF_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */
+#define GPIO_IF_EM4WU_DEFAULT (_GPIO_IF_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IF */
+
+/* Bit fields for GPIO IEN */
+#define _GPIO_IEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_IEN */
+#define _GPIO_IEN_MASK 0x0FFF0FFFUL /**< Mask for GPIO_IEN */
+#define GPIO_IEN_EXTIEN0 (0x1UL << 0) /**< External Pin Enable */
+#define _GPIO_IEN_EXTIEN0_SHIFT 0 /**< Shift value for GPIO_EXTIEN0 */
+#define _GPIO_IEN_EXTIEN0_MASK 0x1UL /**< Bit mask for GPIO_EXTIEN0 */
+#define _GPIO_IEN_EXTIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EXTIEN0_DEFAULT (_GPIO_IEN_EXTIEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EXTIEN1 (0x1UL << 1) /**< External Pin Enable */
+#define _GPIO_IEN_EXTIEN1_SHIFT 1 /**< Shift value for GPIO_EXTIEN1 */
+#define _GPIO_IEN_EXTIEN1_MASK 0x2UL /**< Bit mask for GPIO_EXTIEN1 */
+#define _GPIO_IEN_EXTIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EXTIEN1_DEFAULT (_GPIO_IEN_EXTIEN1_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EXTIEN2 (0x1UL << 2) /**< External Pin Enable */
+#define _GPIO_IEN_EXTIEN2_SHIFT 2 /**< Shift value for GPIO_EXTIEN2 */
+#define _GPIO_IEN_EXTIEN2_MASK 0x4UL /**< Bit mask for GPIO_EXTIEN2 */
+#define _GPIO_IEN_EXTIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EXTIEN2_DEFAULT (_GPIO_IEN_EXTIEN2_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EXTIEN3 (0x1UL << 3) /**< External Pin Enable */
+#define _GPIO_IEN_EXTIEN3_SHIFT 3 /**< Shift value for GPIO_EXTIEN3 */
+#define _GPIO_IEN_EXTIEN3_MASK 0x8UL /**< Bit mask for GPIO_EXTIEN3 */
+#define _GPIO_IEN_EXTIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EXTIEN3_DEFAULT (_GPIO_IEN_EXTIEN3_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EXTIEN4 (0x1UL << 4) /**< External Pin Enable */
+#define _GPIO_IEN_EXTIEN4_SHIFT 4 /**< Shift value for GPIO_EXTIEN4 */
+#define _GPIO_IEN_EXTIEN4_MASK 0x10UL /**< Bit mask for GPIO_EXTIEN4 */
+#define _GPIO_IEN_EXTIEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EXTIEN4_DEFAULT (_GPIO_IEN_EXTIEN4_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EXTIEN5 (0x1UL << 5) /**< External Pin Enable */
+#define _GPIO_IEN_EXTIEN5_SHIFT 5 /**< Shift value for GPIO_EXTIEN5 */
+#define _GPIO_IEN_EXTIEN5_MASK 0x20UL /**< Bit mask for GPIO_EXTIEN5 */
+#define _GPIO_IEN_EXTIEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EXTIEN5_DEFAULT (_GPIO_IEN_EXTIEN5_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EXTIEN6 (0x1UL << 6) /**< External Pin Enable */
+#define _GPIO_IEN_EXTIEN6_SHIFT 6 /**< Shift value for GPIO_EXTIEN6 */
+#define _GPIO_IEN_EXTIEN6_MASK 0x40UL /**< Bit mask for GPIO_EXTIEN6 */
+#define _GPIO_IEN_EXTIEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EXTIEN6_DEFAULT (_GPIO_IEN_EXTIEN6_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EXTIEN7 (0x1UL << 7) /**< External Pin Enable */
+#define _GPIO_IEN_EXTIEN7_SHIFT 7 /**< Shift value for GPIO_EXTIEN7 */
+#define _GPIO_IEN_EXTIEN7_MASK 0x80UL /**< Bit mask for GPIO_EXTIEN7 */
+#define _GPIO_IEN_EXTIEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EXTIEN7_DEFAULT (_GPIO_IEN_EXTIEN7_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EXTIEN8 (0x1UL << 8) /**< External Pin Enable */
+#define _GPIO_IEN_EXTIEN8_SHIFT 8 /**< Shift value for GPIO_EXTIEN8 */
+#define _GPIO_IEN_EXTIEN8_MASK 0x100UL /**< Bit mask for GPIO_EXTIEN8 */
+#define _GPIO_IEN_EXTIEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EXTIEN8_DEFAULT (_GPIO_IEN_EXTIEN8_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EXTIEN9 (0x1UL << 9) /**< External Pin Enable */
+#define _GPIO_IEN_EXTIEN9_SHIFT 9 /**< Shift value for GPIO_EXTIEN9 */
+#define _GPIO_IEN_EXTIEN9_MASK 0x200UL /**< Bit mask for GPIO_EXTIEN9 */
+#define _GPIO_IEN_EXTIEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EXTIEN9_DEFAULT (_GPIO_IEN_EXTIEN9_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EXTIEN10 (0x1UL << 10) /**< External Pin Enable */
+#define _GPIO_IEN_EXTIEN10_SHIFT 10 /**< Shift value for GPIO_EXTIEN10 */
+#define _GPIO_IEN_EXTIEN10_MASK 0x400UL /**< Bit mask for GPIO_EXTIEN10 */
+#define _GPIO_IEN_EXTIEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EXTIEN10_DEFAULT (_GPIO_IEN_EXTIEN10_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EXTIEN11 (0x1UL << 11) /**< External Pin Enable */
+#define _GPIO_IEN_EXTIEN11_SHIFT 11 /**< Shift value for GPIO_EXTIEN11 */
+#define _GPIO_IEN_EXTIEN11_MASK 0x800UL /**< Bit mask for GPIO_EXTIEN11 */
+#define _GPIO_IEN_EXTIEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EXTIEN11_DEFAULT (_GPIO_IEN_EXTIEN11_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EM4WUIEN0 (0x1UL << 16) /**< EM4 Wake Up Interrupt En */
+#define _GPIO_IEN_EM4WUIEN0_SHIFT 16 /**< Shift value for GPIO_EM4WUIEN0 */
+#define _GPIO_IEN_EM4WUIEN0_MASK 0x10000UL /**< Bit mask for GPIO_EM4WUIEN0 */
+#define _GPIO_IEN_EM4WUIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EM4WUIEN0_DEFAULT (_GPIO_IEN_EM4WUIEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EM4WUIEN1 (0x1UL << 17) /**< EM4 Wake Up Interrupt En */
+#define _GPIO_IEN_EM4WUIEN1_SHIFT 17 /**< Shift value for GPIO_EM4WUIEN1 */
+#define _GPIO_IEN_EM4WUIEN1_MASK 0x20000UL /**< Bit mask for GPIO_EM4WUIEN1 */
+#define _GPIO_IEN_EM4WUIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EM4WUIEN1_DEFAULT (_GPIO_IEN_EM4WUIEN1_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EM4WUIEN2 (0x1UL << 18) /**< EM4 Wake Up Interrupt En */
+#define _GPIO_IEN_EM4WUIEN2_SHIFT 18 /**< Shift value for GPIO_EM4WUIEN2 */
+#define _GPIO_IEN_EM4WUIEN2_MASK 0x40000UL /**< Bit mask for GPIO_EM4WUIEN2 */
+#define _GPIO_IEN_EM4WUIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EM4WUIEN2_DEFAULT (_GPIO_IEN_EM4WUIEN2_DEFAULT << 18) /**< Shifted mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EM4WUIEN3 (0x1UL << 19) /**< EM4 Wake Up Interrupt En */
+#define _GPIO_IEN_EM4WUIEN3_SHIFT 19 /**< Shift value for GPIO_EM4WUIEN3 */
+#define _GPIO_IEN_EM4WUIEN3_MASK 0x80000UL /**< Bit mask for GPIO_EM4WUIEN3 */
+#define _GPIO_IEN_EM4WUIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EM4WUIEN3_DEFAULT (_GPIO_IEN_EM4WUIEN3_DEFAULT << 19) /**< Shifted mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EM4WUIEN4 (0x1UL << 20) /**< EM4 Wake Up Interrupt En */
+#define _GPIO_IEN_EM4WUIEN4_SHIFT 20 /**< Shift value for GPIO_EM4WUIEN4 */
+#define _GPIO_IEN_EM4WUIEN4_MASK 0x100000UL /**< Bit mask for GPIO_EM4WUIEN4 */
+#define _GPIO_IEN_EM4WUIEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EM4WUIEN4_DEFAULT (_GPIO_IEN_EM4WUIEN4_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EM4WUIEN5 (0x1UL << 21) /**< EM4 Wake Up Interrupt En */
+#define _GPIO_IEN_EM4WUIEN5_SHIFT 21 /**< Shift value for GPIO_EM4WUIEN5 */
+#define _GPIO_IEN_EM4WUIEN5_MASK 0x200000UL /**< Bit mask for GPIO_EM4WUIEN5 */
+#define _GPIO_IEN_EM4WUIEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EM4WUIEN5_DEFAULT (_GPIO_IEN_EM4WUIEN5_DEFAULT << 21) /**< Shifted mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EM4WUIEN6 (0x1UL << 22) /**< EM4 Wake Up Interrupt En */
+#define _GPIO_IEN_EM4WUIEN6_SHIFT 22 /**< Shift value for GPIO_EM4WUIEN6 */
+#define _GPIO_IEN_EM4WUIEN6_MASK 0x400000UL /**< Bit mask for GPIO_EM4WUIEN6 */
+#define _GPIO_IEN_EM4WUIEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EM4WUIEN6_DEFAULT (_GPIO_IEN_EM4WUIEN6_DEFAULT << 22) /**< Shifted mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EM4WUIEN7 (0x1UL << 23) /**< EM4 Wake Up Interrupt En */
+#define _GPIO_IEN_EM4WUIEN7_SHIFT 23 /**< Shift value for GPIO_EM4WUIEN7 */
+#define _GPIO_IEN_EM4WUIEN7_MASK 0x800000UL /**< Bit mask for GPIO_EM4WUIEN7 */
+#define _GPIO_IEN_EM4WUIEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EM4WUIEN7_DEFAULT (_GPIO_IEN_EM4WUIEN7_DEFAULT << 23) /**< Shifted mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EM4WUIEN8 (0x1UL << 24) /**< EM4 Wake Up Interrupt En */
+#define _GPIO_IEN_EM4WUIEN8_SHIFT 24 /**< Shift value for GPIO_EM4WUIEN8 */
+#define _GPIO_IEN_EM4WUIEN8_MASK 0x1000000UL /**< Bit mask for GPIO_EM4WUIEN8 */
+#define _GPIO_IEN_EM4WUIEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EM4WUIEN8_DEFAULT (_GPIO_IEN_EM4WUIEN8_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EM4WUIEN9 (0x1UL << 25) /**< EM4 Wake Up Interrupt En */
+#define _GPIO_IEN_EM4WUIEN9_SHIFT 25 /**< Shift value for GPIO_EM4WUIEN9 */
+#define _GPIO_IEN_EM4WUIEN9_MASK 0x2000000UL /**< Bit mask for GPIO_EM4WUIEN9 */
+#define _GPIO_IEN_EM4WUIEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EM4WUIEN9_DEFAULT (_GPIO_IEN_EM4WUIEN9_DEFAULT << 25) /**< Shifted mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EM4WUIEN10 (0x1UL << 26) /**< EM4 Wake Up Interrupt En */
+#define _GPIO_IEN_EM4WUIEN10_SHIFT 26 /**< Shift value for GPIO_EM4WUIEN10 */
+#define _GPIO_IEN_EM4WUIEN10_MASK 0x4000000UL /**< Bit mask for GPIO_EM4WUIEN10 */
+#define _GPIO_IEN_EM4WUIEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EM4WUIEN10_DEFAULT (_GPIO_IEN_EM4WUIEN10_DEFAULT << 26) /**< Shifted mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EM4WUIEN11 (0x1UL << 27) /**< EM4 Wake Up Interrupt En */
+#define _GPIO_IEN_EM4WUIEN11_SHIFT 27 /**< Shift value for GPIO_EM4WUIEN11 */
+#define _GPIO_IEN_EM4WUIEN11_MASK 0x8000000UL /**< Bit mask for GPIO_EM4WUIEN11 */
+#define _GPIO_IEN_EM4WUIEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */
+#define GPIO_IEN_EM4WUIEN11_DEFAULT (_GPIO_IEN_EM4WUIEN11_DEFAULT << 27) /**< Shifted mode DEFAULT for GPIO_IEN */
+
+/* Bit fields for GPIO EM4WUEN */
+#define _GPIO_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUEN */
+#define _GPIO_EM4WUEN_MASK 0x0FFF0000UL /**< Mask for GPIO_EM4WUEN */
+#define _GPIO_EM4WUEN_EM4WUEN_SHIFT 16 /**< Shift value for GPIO_EM4WUEN */
+#define _GPIO_EM4WUEN_EM4WUEN_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WUEN */
+#define _GPIO_EM4WUEN_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUEN */
+#define GPIO_EM4WUEN_EM4WUEN_DEFAULT (_GPIO_EM4WUEN_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUEN */
+
+/* Bit fields for GPIO EM4WUPOL */
+#define _GPIO_EM4WUPOL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUPOL */
+#define _GPIO_EM4WUPOL_MASK 0x0FFF0000UL /**< Mask for GPIO_EM4WUPOL */
+#define _GPIO_EM4WUPOL_EM4WUPOL_SHIFT 16 /**< Shift value for GPIO_EM4WUPOL */
+#define _GPIO_EM4WUPOL_EM4WUPOL_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WUPOL */
+#define _GPIO_EM4WUPOL_EM4WUPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUPOL */
+#define GPIO_EM4WUPOL_EM4WUPOL_DEFAULT (_GPIO_EM4WUPOL_EM4WUPOL_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUPOL */
+
+/* Bit fields for GPIO DBGROUTEPEN */
+#define _GPIO_DBGROUTEPEN_RESETVALUE 0x0000000FUL /**< Default value for GPIO_DBGROUTEPEN */
+#define _GPIO_DBGROUTEPEN_MASK 0x0000000FUL /**< Mask for GPIO_DBGROUTEPEN */
+#define GPIO_DBGROUTEPEN_SWCLKTCKPEN (0x1UL << 0) /**< Route Pin Enable */
+#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_SHIFT 0 /**< Shift value for GPIO_SWCLKTCKPEN */
+#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_MASK 0x1UL /**< Bit mask for GPIO_SWCLKTCKPEN */
+#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */
+#define GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT (_GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */
+#define GPIO_DBGROUTEPEN_SWDIOTMSPEN (0x1UL << 1) /**< Route Location 0 */
+#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_SHIFT 1 /**< Shift value for GPIO_SWDIOTMSPEN */
+#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_MASK 0x2UL /**< Bit mask for GPIO_SWDIOTMSPEN */
+#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */
+#define GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT (_GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */
+#define GPIO_DBGROUTEPEN_TDOPEN (0x1UL << 2) /**< JTAG Test Debug Output Pin Enable */
+#define _GPIO_DBGROUTEPEN_TDOPEN_SHIFT 2 /**< Shift value for GPIO_TDOPEN */
+#define _GPIO_DBGROUTEPEN_TDOPEN_MASK 0x4UL /**< Bit mask for GPIO_TDOPEN */
+#define _GPIO_DBGROUTEPEN_TDOPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */
+#define GPIO_DBGROUTEPEN_TDOPEN_DEFAULT (_GPIO_DBGROUTEPEN_TDOPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */
+#define GPIO_DBGROUTEPEN_TDIPEN (0x1UL << 3) /**< JTAG Test Debug Input Pin Enable */
+#define _GPIO_DBGROUTEPEN_TDIPEN_SHIFT 3 /**< Shift value for GPIO_TDIPEN */
+#define _GPIO_DBGROUTEPEN_TDIPEN_MASK 0x8UL /**< Bit mask for GPIO_TDIPEN */
+#define _GPIO_DBGROUTEPEN_TDIPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */
+#define GPIO_DBGROUTEPEN_TDIPEN_DEFAULT (_GPIO_DBGROUTEPEN_TDIPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */
+
+/* Bit fields for GPIO TRACEROUTEPEN */
+#define _GPIO_TRACEROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_TRACEROUTEPEN */
+#define _GPIO_TRACEROUTEPEN_MASK 0x0000003FUL /**< Mask for GPIO_TRACEROUTEPEN */
+#define GPIO_TRACEROUTEPEN_SWVPEN (0x1UL << 0) /**< Serial Wire Viewer Output Pin Enable */
+#define _GPIO_TRACEROUTEPEN_SWVPEN_SHIFT 0 /**< Shift value for GPIO_SWVPEN */
+#define _GPIO_TRACEROUTEPEN_SWVPEN_MASK 0x1UL /**< Bit mask for GPIO_SWVPEN */
+#define _GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */
+#define GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT (_GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */
+#define GPIO_TRACEROUTEPEN_TRACECLKPEN (0x1UL << 1) /**< Trace Clk Pin Enable */
+#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_SHIFT 1 /**< Shift value for GPIO_TRACECLKPEN */
+#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_MASK 0x2UL /**< Bit mask for GPIO_TRACECLKPEN */
+#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */
+#define GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */
+#define GPIO_TRACEROUTEPEN_TRACEDATA0PEN (0x1UL << 2) /**< Trace Data0 Pin Enable */
+#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_SHIFT 2 /**< Shift value for GPIO_TRACEDATA0PEN */
+#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_MASK 0x4UL /**< Bit mask for GPIO_TRACEDATA0PEN */
+#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */
+#define GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */
+#define GPIO_TRACEROUTEPEN_TRACEDATA1PEN (0x1UL << 3) /**< Trace Data1 Pin Enable */
+#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_SHIFT 3 /**< Shift value for GPIO_TRACEDATA1PEN */
+#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_MASK 0x8UL /**< Bit mask for GPIO_TRACEDATA1PEN */
+#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */
+#define GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */
+#define GPIO_TRACEROUTEPEN_TRACEDATA2PEN (0x1UL << 4) /**< Trace Data2 Pin Enable */
+#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_SHIFT 4 /**< Shift value for GPIO_TRACEDATA2PEN */
+#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_MASK 0x10UL /**< Bit mask for GPIO_TRACEDATA2PEN */
+#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */
+#define GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */
+#define GPIO_TRACEROUTEPEN_TRACEDATA3PEN (0x1UL << 5) /**< Trace Data3 Pin Enable */
+#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_SHIFT 5 /**< Shift value for GPIO_TRACEDATA3PEN */
+#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_MASK 0x20UL /**< Bit mask for GPIO_TRACEDATA3PEN */
+#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */
+#define GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */
+
+/* Bit fields for GPIO_ACMP ROUTEEN */
+#define _GPIO_ACMP_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_ACMP_ROUTEEN */
+#define _GPIO_ACMP_ROUTEEN_MASK 0x00000001UL /**< Mask for GPIO_ACMP_ROUTEEN */
+#define GPIO_ACMP_ROUTEEN_ACMPOUTPEN (0x1UL << 0) /**< ACMPOUT pin enable control bit */
+#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_SHIFT 0 /**< Shift value for GPIO_ACMPOUTPEN */
+#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_MASK 0x1UL /**< Bit mask for GPIO_ACMPOUTPEN */
+#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ROUTEEN */
+#define GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT (_GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ACMP_ROUTEEN */
+
+/* Bit fields for GPIO_ACMP ACMPOUTROUTE */
+#define _GPIO_ACMP_ACMPOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_ACMP_ACMPOUTROUTE */
+#define _GPIO_ACMP_ACMPOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_ACMP_ACMPOUTROUTE */
+#define _GPIO_ACMP_ACMPOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_ACMP_ACMPOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE */
+#define GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT (_GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE*/
+#define _GPIO_ACMP_ACMPOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_ACMP_ACMPOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE */
+#define GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT (_GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE*/
+
+/* Bit fields for GPIO_CMU ROUTEEN */
+#define _GPIO_CMU_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_ROUTEEN */
+#define _GPIO_CMU_ROUTEEN_MASK 0x0000000FUL /**< Mask for GPIO_CMU_ROUTEEN */
+#define GPIO_CMU_ROUTEEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 pin enable control bit */
+#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for GPIO_CLKOUT0PEN */
+#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_CLKOUT0PEN */
+#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */
+#define GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */
+#define GPIO_CMU_ROUTEEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 pin enable control bit */
+#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for GPIO_CLKOUT1PEN */
+#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_CLKOUT1PEN */
+#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */
+#define GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */
+#define GPIO_CMU_ROUTEEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 pin enable control bit */
+#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for GPIO_CLKOUT2PEN */
+#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for GPIO_CLKOUT2PEN */
+#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */
+#define GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */
+
+/* Bit fields for GPIO_CMU CLKIN0ROUTE */
+#define _GPIO_CMU_CLKIN0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKIN0ROUTE */
+#define _GPIO_CMU_CLKIN0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKIN0ROUTE */
+#define _GPIO_CMU_CLKIN0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_CMU_CLKIN0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKIN0ROUTE */
+#define GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKIN0ROUTE*/
+#define _GPIO_CMU_CLKIN0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_CMU_CLKIN0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKIN0ROUTE */
+#define GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKIN0ROUTE*/
+
+/* Bit fields for GPIO_CMU CLKOUT0ROUTE */
+#define _GPIO_CMU_CLKOUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT0ROUTE */
+#define _GPIO_CMU_CLKOUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT0ROUTE */
+#define _GPIO_CMU_CLKOUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_CMU_CLKOUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE */
+#define GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE*/
+#define _GPIO_CMU_CLKOUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_CMU_CLKOUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE */
+#define GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE*/
+
+/* Bit fields for GPIO_CMU CLKOUT1ROUTE */
+#define _GPIO_CMU_CLKOUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT1ROUTE */
+#define _GPIO_CMU_CLKOUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT1ROUTE */
+#define _GPIO_CMU_CLKOUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_CMU_CLKOUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE */
+#define GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE*/
+#define _GPIO_CMU_CLKOUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_CMU_CLKOUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE */
+#define GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE*/
+
+/* Bit fields for GPIO_CMU CLKOUT2ROUTE */
+#define _GPIO_CMU_CLKOUT2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT2ROUTE */
+#define _GPIO_CMU_CLKOUT2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT2ROUTE */
+#define _GPIO_CMU_CLKOUT2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_CMU_CLKOUT2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE */
+#define GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE*/
+#define _GPIO_CMU_CLKOUT2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_CMU_CLKOUT2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE */
+#define GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE*/
+
+/* Bit fields for GPIO_DCDC ROUTEEN */
+#define _GPIO_DCDC_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_DCDC_ROUTEEN */
+#define _GPIO_DCDC_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_DCDC_ROUTEEN */
+#define GPIO_DCDC_ROUTEEN_DCDCCOREHIDDENPEN (0x1UL << 0) /**< DCDCCOREHIDDEN pin enable control bit */
+#define _GPIO_DCDC_ROUTEEN_DCDCCOREHIDDENPEN_SHIFT 0 /**< Shift value for GPIO_DCDCCOREHIDDENPEN */
+#define _GPIO_DCDC_ROUTEEN_DCDCCOREHIDDENPEN_MASK 0x1UL /**< Bit mask for GPIO_DCDCCOREHIDDENPEN */
+#define _GPIO_DCDC_ROUTEEN_DCDCCOREHIDDENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_DCDC_ROUTEEN */
+#define GPIO_DCDC_ROUTEEN_DCDCCOREHIDDENPEN_DEFAULT (_GPIO_DCDC_ROUTEEN_DCDCCOREHIDDENPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_DCDC_ROUTEEN */
+
+/* Bit fields for GPIO_EUSART ROUTEEN */
+#define _GPIO_EUSART_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_ROUTEEN */
+#define _GPIO_EUSART_ROUTEEN_MASK 0x0000001FUL /**< Mask for GPIO_EUSART_ROUTEEN */
+#define GPIO_EUSART_ROUTEEN_CSPEN (0x1UL << 0) /**< CS pin enable control bit */
+#define _GPIO_EUSART_ROUTEEN_CSPEN_SHIFT 0 /**< Shift value for GPIO_CSPEN */
+#define _GPIO_EUSART_ROUTEEN_CSPEN_MASK 0x1UL /**< Bit mask for GPIO_CSPEN */
+#define _GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */
+#define GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/
+#define GPIO_EUSART_ROUTEEN_RTSPEN (0x1UL << 1) /**< RTS pin enable control bit */
+#define _GPIO_EUSART_ROUTEEN_RTSPEN_SHIFT 1 /**< Shift value for GPIO_RTSPEN */
+#define _GPIO_EUSART_ROUTEEN_RTSPEN_MASK 0x2UL /**< Bit mask for GPIO_RTSPEN */
+#define _GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */
+#define GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/
+#define GPIO_EUSART_ROUTEEN_RXPEN (0x1UL << 2) /**< RX pin enable control bit */
+#define _GPIO_EUSART_ROUTEEN_RXPEN_SHIFT 2 /**< Shift value for GPIO_RXPEN */
+#define _GPIO_EUSART_ROUTEEN_RXPEN_MASK 0x4UL /**< Bit mask for GPIO_RXPEN */
+#define _GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */
+#define GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/
+#define GPIO_EUSART_ROUTEEN_SCLKPEN (0x1UL << 3) /**< SCLK pin enable control bit */
+#define _GPIO_EUSART_ROUTEEN_SCLKPEN_SHIFT 3 /**< Shift value for GPIO_SCLKPEN */
+#define _GPIO_EUSART_ROUTEEN_SCLKPEN_MASK 0x8UL /**< Bit mask for GPIO_SCLKPEN */
+#define _GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */
+#define GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/
+#define GPIO_EUSART_ROUTEEN_TXPEN (0x1UL << 4) /**< TX pin enable control bit */
+#define _GPIO_EUSART_ROUTEEN_TXPEN_SHIFT 4 /**< Shift value for GPIO_TXPEN */
+#define _GPIO_EUSART_ROUTEEN_TXPEN_MASK 0x10UL /**< Bit mask for GPIO_TXPEN */
+#define _GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */
+#define GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/
+
+/* Bit fields for GPIO_EUSART CSROUTE */
+#define _GPIO_EUSART_CSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_CSROUTE */
+#define _GPIO_EUSART_CSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_CSROUTE */
+#define _GPIO_EUSART_CSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_EUSART_CSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_EUSART_CSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CSROUTE */
+#define GPIO_EUSART_CSROUTE_PORT_DEFAULT (_GPIO_EUSART_CSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_CSROUTE*/
+#define _GPIO_EUSART_CSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_EUSART_CSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_EUSART_CSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CSROUTE */
+#define GPIO_EUSART_CSROUTE_PIN_DEFAULT (_GPIO_EUSART_CSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_CSROUTE*/
+
+/* Bit fields for GPIO_EUSART CTSROUTE */
+#define _GPIO_EUSART_CTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_CTSROUTE */
+#define _GPIO_EUSART_CTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_CTSROUTE */
+#define _GPIO_EUSART_CTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_EUSART_CTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_EUSART_CTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CTSROUTE */
+#define GPIO_EUSART_CTSROUTE_PORT_DEFAULT (_GPIO_EUSART_CTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_CTSROUTE*/
+#define _GPIO_EUSART_CTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_EUSART_CTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_EUSART_CTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CTSROUTE */
+#define GPIO_EUSART_CTSROUTE_PIN_DEFAULT (_GPIO_EUSART_CTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_CTSROUTE*/
+
+/* Bit fields for GPIO_EUSART RTSROUTE */
+#define _GPIO_EUSART_RTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_RTSROUTE */
+#define _GPIO_EUSART_RTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_RTSROUTE */
+#define _GPIO_EUSART_RTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_EUSART_RTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_EUSART_RTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RTSROUTE */
+#define GPIO_EUSART_RTSROUTE_PORT_DEFAULT (_GPIO_EUSART_RTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_RTSROUTE*/
+#define _GPIO_EUSART_RTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_EUSART_RTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_EUSART_RTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RTSROUTE */
+#define GPIO_EUSART_RTSROUTE_PIN_DEFAULT (_GPIO_EUSART_RTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_RTSROUTE*/
+
+/* Bit fields for GPIO_EUSART RXROUTE */
+#define _GPIO_EUSART_RXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_RXROUTE */
+#define _GPIO_EUSART_RXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_RXROUTE */
+#define _GPIO_EUSART_RXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_EUSART_RXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_EUSART_RXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RXROUTE */
+#define GPIO_EUSART_RXROUTE_PORT_DEFAULT (_GPIO_EUSART_RXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_RXROUTE*/
+#define _GPIO_EUSART_RXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_EUSART_RXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_EUSART_RXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RXROUTE */
+#define GPIO_EUSART_RXROUTE_PIN_DEFAULT (_GPIO_EUSART_RXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_RXROUTE*/
+
+/* Bit fields for GPIO_EUSART SCLKROUTE */
+#define _GPIO_EUSART_SCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_SCLKROUTE */
+#define _GPIO_EUSART_SCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_SCLKROUTE */
+#define _GPIO_EUSART_SCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_EUSART_SCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_EUSART_SCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_SCLKROUTE */
+#define GPIO_EUSART_SCLKROUTE_PORT_DEFAULT (_GPIO_EUSART_SCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_SCLKROUTE*/
+#define _GPIO_EUSART_SCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_EUSART_SCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_EUSART_SCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_SCLKROUTE */
+#define GPIO_EUSART_SCLKROUTE_PIN_DEFAULT (_GPIO_EUSART_SCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_SCLKROUTE*/
+
+/* Bit fields for GPIO_EUSART TXROUTE */
+#define _GPIO_EUSART_TXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_TXROUTE */
+#define _GPIO_EUSART_TXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_TXROUTE */
+#define _GPIO_EUSART_TXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_EUSART_TXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_EUSART_TXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_TXROUTE */
+#define GPIO_EUSART_TXROUTE_PORT_DEFAULT (_GPIO_EUSART_TXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_TXROUTE*/
+#define _GPIO_EUSART_TXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_EUSART_TXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_EUSART_TXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_TXROUTE */
+#define GPIO_EUSART_TXROUTE_PIN_DEFAULT (_GPIO_EUSART_TXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_TXROUTE*/
+
+/* Bit fields for GPIO_FRC ROUTEEN */
+#define _GPIO_FRC_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_ROUTEEN */
+#define _GPIO_FRC_ROUTEEN_MASK 0x00000007UL /**< Mask for GPIO_FRC_ROUTEEN */
+#define GPIO_FRC_ROUTEEN_DCLKPEN (0x1UL << 0) /**< DCLK pin enable control bit */
+#define _GPIO_FRC_ROUTEEN_DCLKPEN_SHIFT 0 /**< Shift value for GPIO_DCLKPEN */
+#define _GPIO_FRC_ROUTEEN_DCLKPEN_MASK 0x1UL /**< Bit mask for GPIO_DCLKPEN */
+#define _GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */
+#define GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */
+#define GPIO_FRC_ROUTEEN_DFRAMEPEN (0x1UL << 1) /**< DFRAME pin enable control bit */
+#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_SHIFT 1 /**< Shift value for GPIO_DFRAMEPEN */
+#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_MASK 0x2UL /**< Bit mask for GPIO_DFRAMEPEN */
+#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */
+#define GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */
+#define GPIO_FRC_ROUTEEN_DOUTPEN (0x1UL << 2) /**< DOUT pin enable control bit */
+#define _GPIO_FRC_ROUTEEN_DOUTPEN_SHIFT 2 /**< Shift value for GPIO_DOUTPEN */
+#define _GPIO_FRC_ROUTEEN_DOUTPEN_MASK 0x4UL /**< Bit mask for GPIO_DOUTPEN */
+#define _GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */
+#define GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */
+
+/* Bit fields for GPIO_FRC DCLKROUTE */
+#define _GPIO_FRC_DCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DCLKROUTE */
+#define _GPIO_FRC_DCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DCLKROUTE */
+#define _GPIO_FRC_DCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_FRC_DCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_FRC_DCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DCLKROUTE */
+#define GPIO_FRC_DCLKROUTE_PORT_DEFAULT (_GPIO_FRC_DCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DCLKROUTE */
+#define _GPIO_FRC_DCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_FRC_DCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_FRC_DCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DCLKROUTE */
+#define GPIO_FRC_DCLKROUTE_PIN_DEFAULT (_GPIO_FRC_DCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DCLKROUTE */
+
+/* Bit fields for GPIO_FRC DFRAMEROUTE */
+#define _GPIO_FRC_DFRAMEROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DFRAMEROUTE */
+#define _GPIO_FRC_DFRAMEROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DFRAMEROUTE */
+#define _GPIO_FRC_DFRAMEROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_FRC_DFRAMEROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DFRAMEROUTE */
+#define GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT (_GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DFRAMEROUTE*/
+#define _GPIO_FRC_DFRAMEROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_FRC_DFRAMEROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DFRAMEROUTE */
+#define GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT (_GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DFRAMEROUTE*/
+
+/* Bit fields for GPIO_FRC DOUTROUTE */
+#define _GPIO_FRC_DOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DOUTROUTE */
+#define _GPIO_FRC_DOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DOUTROUTE */
+#define _GPIO_FRC_DOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_FRC_DOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_FRC_DOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DOUTROUTE */
+#define GPIO_FRC_DOUTROUTE_PORT_DEFAULT (_GPIO_FRC_DOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DOUTROUTE */
+#define _GPIO_FRC_DOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_FRC_DOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_FRC_DOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DOUTROUTE */
+#define GPIO_FRC_DOUTROUTE_PIN_DEFAULT (_GPIO_FRC_DOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DOUTROUTE */
+
+/* Bit fields for GPIO_I2C ROUTEEN */
+#define _GPIO_I2C_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_ROUTEEN */
+#define _GPIO_I2C_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_I2C_ROUTEEN */
+#define GPIO_I2C_ROUTEEN_SCLPEN (0x1UL << 0) /**< SCL pin enable control bit */
+#define _GPIO_I2C_ROUTEEN_SCLPEN_SHIFT 0 /**< Shift value for GPIO_SCLPEN */
+#define _GPIO_I2C_ROUTEEN_SCLPEN_MASK 0x1UL /**< Bit mask for GPIO_SCLPEN */
+#define _GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_ROUTEEN */
+#define GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT (_GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_ROUTEEN */
+#define GPIO_I2C_ROUTEEN_SDAPEN (0x1UL << 1) /**< SDA pin enable control bit */
+#define _GPIO_I2C_ROUTEEN_SDAPEN_SHIFT 1 /**< Shift value for GPIO_SDAPEN */
+#define _GPIO_I2C_ROUTEEN_SDAPEN_MASK 0x2UL /**< Bit mask for GPIO_SDAPEN */
+#define _GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_ROUTEEN */
+#define GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT (_GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_I2C_ROUTEEN */
+
+/* Bit fields for GPIO_I2C SCLROUTE */
+#define _GPIO_I2C_SCLROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_SCLROUTE */
+#define _GPIO_I2C_SCLROUTE_MASK 0x000F0003UL /**< Mask for GPIO_I2C_SCLROUTE */
+#define _GPIO_I2C_SCLROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_I2C_SCLROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_I2C_SCLROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SCLROUTE */
+#define GPIO_I2C_SCLROUTE_PORT_DEFAULT (_GPIO_I2C_SCLROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_SCLROUTE */
+#define _GPIO_I2C_SCLROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_I2C_SCLROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_I2C_SCLROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SCLROUTE */
+#define GPIO_I2C_SCLROUTE_PIN_DEFAULT (_GPIO_I2C_SCLROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_I2C_SCLROUTE */
+
+/* Bit fields for GPIO_I2C SDAROUTE */
+#define _GPIO_I2C_SDAROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_SDAROUTE */
+#define _GPIO_I2C_SDAROUTE_MASK 0x000F0003UL /**< Mask for GPIO_I2C_SDAROUTE */
+#define _GPIO_I2C_SDAROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_I2C_SDAROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_I2C_SDAROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SDAROUTE */
+#define GPIO_I2C_SDAROUTE_PORT_DEFAULT (_GPIO_I2C_SDAROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_SDAROUTE */
+#define _GPIO_I2C_SDAROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_I2C_SDAROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_I2C_SDAROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SDAROUTE */
+#define GPIO_I2C_SDAROUTE_PIN_DEFAULT (_GPIO_I2C_SDAROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_I2C_SDAROUTE */
+
+/* Bit fields for GPIO_KEYSCAN ROUTEEN */
+#define _GPIO_KEYSCAN_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROUTEEN */
+#define _GPIO_KEYSCAN_ROUTEEN_MASK 0x000000FFUL /**< Mask for GPIO_KEYSCAN_ROUTEEN */
+#define GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN (0x1UL << 0) /**< COLOUT0 pin enable control bit */
+#define _GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_SHIFT 0 /**< Shift value for GPIO_COLOUT0PEN */
+#define _GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_COLOUT0PEN */
+#define _GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */
+#define GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/
+#define GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN (0x1UL << 1) /**< COLOUT1 pin enable control bit */
+#define _GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_SHIFT 1 /**< Shift value for GPIO_COLOUT1PEN */
+#define _GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_COLOUT1PEN */
+#define _GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */
+#define GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/
+#define GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN (0x1UL << 2) /**< COLOUT2 pin enable control bit */
+#define _GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_SHIFT 2 /**< Shift value for GPIO_COLOUT2PEN */
+#define _GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_MASK 0x4UL /**< Bit mask for GPIO_COLOUT2PEN */
+#define _GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */
+#define GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/
+#define GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN (0x1UL << 3) /**< COLOUT3 pin enable control bit */
+#define _GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_SHIFT 3 /**< Shift value for GPIO_COLOUT3PEN */
+#define _GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_MASK 0x8UL /**< Bit mask for GPIO_COLOUT3PEN */
+#define _GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */
+#define GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/
+#define GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN (0x1UL << 4) /**< COLOUT4 pin enable control bit */
+#define _GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_SHIFT 4 /**< Shift value for GPIO_COLOUT4PEN */
+#define _GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_MASK 0x10UL /**< Bit mask for GPIO_COLOUT4PEN */
+#define _GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */
+#define GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/
+#define GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN (0x1UL << 5) /**< COLOUT5 pin enable control bit */
+#define _GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_SHIFT 5 /**< Shift value for GPIO_COLOUT5PEN */
+#define _GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_MASK 0x20UL /**< Bit mask for GPIO_COLOUT5PEN */
+#define _GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */
+#define GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/
+#define GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN (0x1UL << 6) /**< COLOUT6 pin enable control bit */
+#define _GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_SHIFT 6 /**< Shift value for GPIO_COLOUT6PEN */
+#define _GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_MASK 0x40UL /**< Bit mask for GPIO_COLOUT6PEN */
+#define _GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */
+#define GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/
+#define GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN (0x1UL << 7) /**< COLOUT7 pin enable control bit */
+#define _GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_SHIFT 7 /**< Shift value for GPIO_COLOUT7PEN */
+#define _GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_MASK 0x80UL /**< Bit mask for GPIO_COLOUT7PEN */
+#define _GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */
+#define GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/
+
+/* Bit fields for GPIO_KEYSCAN COLOUT0ROUTE */
+#define _GPIO_KEYSCAN_COLOUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT0ROUTE */
+#define _GPIO_KEYSCAN_COLOUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT0ROUTE */
+#define _GPIO_KEYSCAN_COLOUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_KEYSCAN_COLOUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_KEYSCAN_COLOUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE */
+#define GPIO_KEYSCAN_COLOUT0ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE*/
+#define _GPIO_KEYSCAN_COLOUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_KEYSCAN_COLOUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_KEYSCAN_COLOUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE */
+#define GPIO_KEYSCAN_COLOUT0ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE*/
+
+/* Bit fields for GPIO_KEYSCAN COLOUT1ROUTE */
+#define _GPIO_KEYSCAN_COLOUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT1ROUTE */
+#define _GPIO_KEYSCAN_COLOUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT1ROUTE */
+#define _GPIO_KEYSCAN_COLOUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_KEYSCAN_COLOUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_KEYSCAN_COLOUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE */
+#define GPIO_KEYSCAN_COLOUT1ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE*/
+#define _GPIO_KEYSCAN_COLOUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_KEYSCAN_COLOUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_KEYSCAN_COLOUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE */
+#define GPIO_KEYSCAN_COLOUT1ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE*/
+
+/* Bit fields for GPIO_KEYSCAN COLOUT2ROUTE */
+#define _GPIO_KEYSCAN_COLOUT2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT2ROUTE */
+#define _GPIO_KEYSCAN_COLOUT2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT2ROUTE */
+#define _GPIO_KEYSCAN_COLOUT2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_KEYSCAN_COLOUT2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_KEYSCAN_COLOUT2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE */
+#define GPIO_KEYSCAN_COLOUT2ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE*/
+#define _GPIO_KEYSCAN_COLOUT2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_KEYSCAN_COLOUT2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_KEYSCAN_COLOUT2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE */
+#define GPIO_KEYSCAN_COLOUT2ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE*/
+
+/* Bit fields for GPIO_KEYSCAN COLOUT3ROUTE */
+#define _GPIO_KEYSCAN_COLOUT3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT3ROUTE */
+#define _GPIO_KEYSCAN_COLOUT3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT3ROUTE */
+#define _GPIO_KEYSCAN_COLOUT3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_KEYSCAN_COLOUT3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_KEYSCAN_COLOUT3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE */
+#define GPIO_KEYSCAN_COLOUT3ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE*/
+#define _GPIO_KEYSCAN_COLOUT3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_KEYSCAN_COLOUT3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_KEYSCAN_COLOUT3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE */
+#define GPIO_KEYSCAN_COLOUT3ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE*/
+
+/* Bit fields for GPIO_KEYSCAN COLOUT4ROUTE */
+#define _GPIO_KEYSCAN_COLOUT4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT4ROUTE */
+#define _GPIO_KEYSCAN_COLOUT4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT4ROUTE */
+#define _GPIO_KEYSCAN_COLOUT4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_KEYSCAN_COLOUT4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_KEYSCAN_COLOUT4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE */
+#define GPIO_KEYSCAN_COLOUT4ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE*/
+#define _GPIO_KEYSCAN_COLOUT4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_KEYSCAN_COLOUT4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_KEYSCAN_COLOUT4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE */
+#define GPIO_KEYSCAN_COLOUT4ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE*/
+
+/* Bit fields for GPIO_KEYSCAN COLOUT5ROUTE */
+#define _GPIO_KEYSCAN_COLOUT5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT5ROUTE */
+#define _GPIO_KEYSCAN_COLOUT5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT5ROUTE */
+#define _GPIO_KEYSCAN_COLOUT5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_KEYSCAN_COLOUT5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_KEYSCAN_COLOUT5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE */
+#define GPIO_KEYSCAN_COLOUT5ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE*/
+#define _GPIO_KEYSCAN_COLOUT5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_KEYSCAN_COLOUT5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_KEYSCAN_COLOUT5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE */
+#define GPIO_KEYSCAN_COLOUT5ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE*/
+
+/* Bit fields for GPIO_KEYSCAN COLOUT6ROUTE */
+#define _GPIO_KEYSCAN_COLOUT6ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT6ROUTE */
+#define _GPIO_KEYSCAN_COLOUT6ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT6ROUTE */
+#define _GPIO_KEYSCAN_COLOUT6ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_KEYSCAN_COLOUT6ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_KEYSCAN_COLOUT6ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE */
+#define GPIO_KEYSCAN_COLOUT6ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT6ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE*/
+#define _GPIO_KEYSCAN_COLOUT6ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_KEYSCAN_COLOUT6ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_KEYSCAN_COLOUT6ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE */
+#define GPIO_KEYSCAN_COLOUT6ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT6ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE*/
+
+/* Bit fields for GPIO_KEYSCAN COLOUT7ROUTE */
+#define _GPIO_KEYSCAN_COLOUT7ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT7ROUTE */
+#define _GPIO_KEYSCAN_COLOUT7ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT7ROUTE */
+#define _GPIO_KEYSCAN_COLOUT7ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_KEYSCAN_COLOUT7ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_KEYSCAN_COLOUT7ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE */
+#define GPIO_KEYSCAN_COLOUT7ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT7ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE*/
+#define _GPIO_KEYSCAN_COLOUT7ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_KEYSCAN_COLOUT7ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_KEYSCAN_COLOUT7ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE */
+#define GPIO_KEYSCAN_COLOUT7ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT7ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE*/
+
+/* Bit fields for GPIO_KEYSCAN ROWSENSE0ROUTE */
+#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE0ROUTE*/
+#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE0ROUTE */
+#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/
+#define GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/
+#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/
+#define GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/
+
+/* Bit fields for GPIO_KEYSCAN ROWSENSE1ROUTE */
+#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE1ROUTE*/
+#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE1ROUTE */
+#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/
+#define GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/
+#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/
+#define GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/
+
+/* Bit fields for GPIO_KEYSCAN ROWSENSE2ROUTE */
+#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE2ROUTE*/
+#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE2ROUTE */
+#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/
+#define GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/
+#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/
+#define GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/
+
+/* Bit fields for GPIO_KEYSCAN ROWSENSE3ROUTE */
+#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE3ROUTE*/
+#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE3ROUTE */
+#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/
+#define GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/
+#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/
+#define GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/
+
+/* Bit fields for GPIO_KEYSCAN ROWSENSE4ROUTE */
+#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE4ROUTE*/
+#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE4ROUTE */
+#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/
+#define GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/
+#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/
+#define GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/
+
+/* Bit fields for GPIO_KEYSCAN ROWSENSE5ROUTE */
+#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE5ROUTE*/
+#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE5ROUTE */
+#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/
+#define GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/
+#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/
+#define GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/
+
+/* Bit fields for GPIO_LETIMER ROUTEEN */
+#define _GPIO_LETIMER_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_ROUTEEN */
+#define _GPIO_LETIMER_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_LETIMER_ROUTEEN */
+#define GPIO_LETIMER_ROUTEEN_OUT0PEN (0x1UL << 0) /**< OUT0 pin enable control bit */
+#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_SHIFT 0 /**< Shift value for GPIO_OUT0PEN */
+#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_OUT0PEN */
+#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_ROUTEEN */
+#define GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT (_GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_ROUTEEN*/
+#define GPIO_LETIMER_ROUTEEN_OUT1PEN (0x1UL << 1) /**< OUT1 pin enable control bit */
+#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_SHIFT 1 /**< Shift value for GPIO_OUT1PEN */
+#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_OUT1PEN */
+#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_ROUTEEN */
+#define GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT (_GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_LETIMER_ROUTEEN*/
+
+/* Bit fields for GPIO_LETIMER OUT0ROUTE */
+#define _GPIO_LETIMER_OUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_OUT0ROUTE */
+#define _GPIO_LETIMER_OUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LETIMER_OUT0ROUTE */
+#define _GPIO_LETIMER_OUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_LETIMER_OUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT0ROUTE */
+#define GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT (_GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT0ROUTE*/
+#define _GPIO_LETIMER_OUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_LETIMER_OUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT0ROUTE */
+#define GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT (_GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT0ROUTE*/
+
+/* Bit fields for GPIO_LETIMER OUT1ROUTE */
+#define _GPIO_LETIMER_OUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_OUT1ROUTE */
+#define _GPIO_LETIMER_OUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LETIMER_OUT1ROUTE */
+#define _GPIO_LETIMER_OUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_LETIMER_OUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT1ROUTE */
+#define GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT (_GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT1ROUTE*/
+#define _GPIO_LETIMER_OUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_LETIMER_OUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT1ROUTE */
+#define GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT (_GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT1ROUTE*/
+
+/* Bit fields for GPIO_MODEM ROUTEEN */
+#define _GPIO_MODEM_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ROUTEEN */
+#define _GPIO_MODEM_ROUTEEN_MASK 0x00007FFFUL /**< Mask for GPIO_MODEM_ROUTEEN */
+#define GPIO_MODEM_ROUTEEN_ANT0PEN (0x1UL << 0) /**< ANT0 pin enable control bit */
+#define _GPIO_MODEM_ROUTEEN_ANT0PEN_SHIFT 0 /**< Shift value for GPIO_ANT0PEN */
+#define _GPIO_MODEM_ROUTEEN_ANT0PEN_MASK 0x1UL /**< Bit mask for GPIO_ANT0PEN */
+#define _GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */
+#define GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */
+#define GPIO_MODEM_ROUTEEN_ANT1PEN (0x1UL << 1) /**< ANT1 pin enable control bit */
+#define _GPIO_MODEM_ROUTEEN_ANT1PEN_SHIFT 1 /**< Shift value for GPIO_ANT1PEN */
+#define _GPIO_MODEM_ROUTEEN_ANT1PEN_MASK 0x2UL /**< Bit mask for GPIO_ANT1PEN */
+#define _GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */
+#define GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */
+#define GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN (0x1UL << 2) /**< ANTROLLOVER pin enable control bit */
+#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_SHIFT 2 /**< Shift value for GPIO_ANTROLLOVERPEN */
+#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_MASK 0x4UL /**< Bit mask for GPIO_ANTROLLOVERPEN */
+#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */
+#define GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */
+#define GPIO_MODEM_ROUTEEN_ANTRR0PEN (0x1UL << 3) /**< ANTRR0 pin enable control bit */
+#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_SHIFT 3 /**< Shift value for GPIO_ANTRR0PEN */
+#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_MASK 0x8UL /**< Bit mask for GPIO_ANTRR0PEN */
+#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */
+#define GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */
+#define GPIO_MODEM_ROUTEEN_ANTRR1PEN (0x1UL << 4) /**< ANTRR1 pin enable control bit */
+#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_SHIFT 4 /**< Shift value for GPIO_ANTRR1PEN */
+#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_MASK 0x10UL /**< Bit mask for GPIO_ANTRR1PEN */
+#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */
+#define GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */
+#define GPIO_MODEM_ROUTEEN_ANTRR2PEN (0x1UL << 5) /**< ANTRR2 pin enable control bit */
+#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_SHIFT 5 /**< Shift value for GPIO_ANTRR2PEN */
+#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_MASK 0x20UL /**< Bit mask for GPIO_ANTRR2PEN */
+#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */
+#define GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */
+#define GPIO_MODEM_ROUTEEN_ANTRR3PEN (0x1UL << 6) /**< ANTRR3 pin enable control bit */
+#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_SHIFT 6 /**< Shift value for GPIO_ANTRR3PEN */
+#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_MASK 0x40UL /**< Bit mask for GPIO_ANTRR3PEN */
+#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */
+#define GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */
+#define GPIO_MODEM_ROUTEEN_ANTRR4PEN (0x1UL << 7) /**< ANTRR4 pin enable control bit */
+#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_SHIFT 7 /**< Shift value for GPIO_ANTRR4PEN */
+#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_MASK 0x80UL /**< Bit mask for GPIO_ANTRR4PEN */
+#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */
+#define GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */
+#define GPIO_MODEM_ROUTEEN_ANTRR5PEN (0x1UL << 8) /**< ANTRR5 pin enable control bit */
+#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_SHIFT 8 /**< Shift value for GPIO_ANTRR5PEN */
+#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_MASK 0x100UL /**< Bit mask for GPIO_ANTRR5PEN */
+#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */
+#define GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */
+#define GPIO_MODEM_ROUTEEN_ANTSWENPEN (0x1UL << 9) /**< ANTSWEN pin enable control bit */
+#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_SHIFT 9 /**< Shift value for GPIO_ANTSWENPEN */
+#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_MASK 0x200UL /**< Bit mask for GPIO_ANTSWENPEN */
+#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */
+#define GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */
+#define GPIO_MODEM_ROUTEEN_ANTSWUSPEN (0x1UL << 10) /**< ANTSWUS pin enable control bit */
+#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_SHIFT 10 /**< Shift value for GPIO_ANTSWUSPEN */
+#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_MASK 0x400UL /**< Bit mask for GPIO_ANTSWUSPEN */
+#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */
+#define GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */
+#define GPIO_MODEM_ROUTEEN_ANTTRIGPEN (0x1UL << 11) /**< ANTTRIG pin enable control bit */
+#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_SHIFT 11 /**< Shift value for GPIO_ANTTRIGPEN */
+#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_MASK 0x800UL /**< Bit mask for GPIO_ANTTRIGPEN */
+#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */
+#define GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */
+#define GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN (0x1UL << 12) /**< ANTTRIGSTOP pin enable control bit */
+#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_SHIFT 12 /**< Shift value for GPIO_ANTTRIGSTOPPEN */
+#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_MASK 0x1000UL /**< Bit mask for GPIO_ANTTRIGSTOPPEN */
+#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */
+#define GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */
+#define GPIO_MODEM_ROUTEEN_DCLKPEN (0x1UL << 13) /**< DCLK pin enable control bit */
+#define _GPIO_MODEM_ROUTEEN_DCLKPEN_SHIFT 13 /**< Shift value for GPIO_DCLKPEN */
+#define _GPIO_MODEM_ROUTEEN_DCLKPEN_MASK 0x2000UL /**< Bit mask for GPIO_DCLKPEN */
+#define _GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */
+#define GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */
+#define GPIO_MODEM_ROUTEEN_DOUTPEN (0x1UL << 14) /**< DOUT pin enable control bit */
+#define _GPIO_MODEM_ROUTEEN_DOUTPEN_SHIFT 14 /**< Shift value for GPIO_DOUTPEN */
+#define _GPIO_MODEM_ROUTEEN_DOUTPEN_MASK 0x4000UL /**< Bit mask for GPIO_DOUTPEN */
+#define _GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */
+#define GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */
+
+/* Bit fields for GPIO_MODEM ANT0ROUTE */
+#define _GPIO_MODEM_ANT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANT0ROUTE */
+#define _GPIO_MODEM_ANT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANT0ROUTE */
+#define _GPIO_MODEM_ANT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_MODEM_ANT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT0ROUTE */
+#define GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT0ROUTE*/
+#define _GPIO_MODEM_ANT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_MODEM_ANT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT0ROUTE */
+#define GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT0ROUTE*/
+
+/* Bit fields for GPIO_MODEM ANT1ROUTE */
+#define _GPIO_MODEM_ANT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANT1ROUTE */
+#define _GPIO_MODEM_ANT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANT1ROUTE */
+#define _GPIO_MODEM_ANT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_MODEM_ANT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT1ROUTE */
+#define GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT1ROUTE*/
+#define _GPIO_MODEM_ANT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_MODEM_ANT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT1ROUTE */
+#define GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT1ROUTE*/
+
+/* Bit fields for GPIO_MODEM ANTROLLOVERROUTE */
+#define _GPIO_MODEM_ANTROLLOVERROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTROLLOVERROUTE*/
+#define _GPIO_MODEM_ANTROLLOVERROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTROLLOVERROUTE */
+#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/
+#define GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/
+#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/
+#define GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/
+
+/* Bit fields for GPIO_MODEM ANTRR0ROUTE */
+#define _GPIO_MODEM_ANTRR0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR0ROUTE */
+#define _GPIO_MODEM_ANTRR0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR0ROUTE */
+#define _GPIO_MODEM_ANTRR0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_MODEM_ANTRR0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE */
+#define GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE*/
+#define _GPIO_MODEM_ANTRR0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_MODEM_ANTRR0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE */
+#define GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE*/
+
+/* Bit fields for GPIO_MODEM ANTRR1ROUTE */
+#define _GPIO_MODEM_ANTRR1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR1ROUTE */
+#define _GPIO_MODEM_ANTRR1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR1ROUTE */
+#define _GPIO_MODEM_ANTRR1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_MODEM_ANTRR1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE */
+#define GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE*/
+#define _GPIO_MODEM_ANTRR1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_MODEM_ANTRR1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE */
+#define GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE*/
+
+/* Bit fields for GPIO_MODEM ANTRR2ROUTE */
+#define _GPIO_MODEM_ANTRR2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR2ROUTE */
+#define _GPIO_MODEM_ANTRR2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR2ROUTE */
+#define _GPIO_MODEM_ANTRR2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_MODEM_ANTRR2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE */
+#define GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE*/
+#define _GPIO_MODEM_ANTRR2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_MODEM_ANTRR2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE */
+#define GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE*/
+
+/* Bit fields for GPIO_MODEM ANTRR3ROUTE */
+#define _GPIO_MODEM_ANTRR3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR3ROUTE */
+#define _GPIO_MODEM_ANTRR3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR3ROUTE */
+#define _GPIO_MODEM_ANTRR3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_MODEM_ANTRR3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE */
+#define GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE*/
+#define _GPIO_MODEM_ANTRR3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_MODEM_ANTRR3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE */
+#define GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE*/
+
+/* Bit fields for GPIO_MODEM ANTRR4ROUTE */
+#define _GPIO_MODEM_ANTRR4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR4ROUTE */
+#define _GPIO_MODEM_ANTRR4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR4ROUTE */
+#define _GPIO_MODEM_ANTRR4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_MODEM_ANTRR4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE */
+#define GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE*/
+#define _GPIO_MODEM_ANTRR4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_MODEM_ANTRR4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE */
+#define GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE*/
+
+/* Bit fields for GPIO_MODEM ANTRR5ROUTE */
+#define _GPIO_MODEM_ANTRR5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR5ROUTE */
+#define _GPIO_MODEM_ANTRR5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR5ROUTE */
+#define _GPIO_MODEM_ANTRR5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_MODEM_ANTRR5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE */
+#define GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE*/
+#define _GPIO_MODEM_ANTRR5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_MODEM_ANTRR5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE */
+#define GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE*/
+
+/* Bit fields for GPIO_MODEM ANTSWENROUTE */
+#define _GPIO_MODEM_ANTSWENROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTSWENROUTE */
+#define _GPIO_MODEM_ANTSWENROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTSWENROUTE */
+#define _GPIO_MODEM_ANTSWENROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_MODEM_ANTSWENROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWENROUTE */
+#define GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWENROUTE*/
+#define _GPIO_MODEM_ANTSWENROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_MODEM_ANTSWENROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWENROUTE */
+#define GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWENROUTE*/
+
+/* Bit fields for GPIO_MODEM ANTSWUSROUTE */
+#define _GPIO_MODEM_ANTSWUSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTSWUSROUTE */
+#define _GPIO_MODEM_ANTSWUSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTSWUSROUTE */
+#define _GPIO_MODEM_ANTSWUSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_MODEM_ANTSWUSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE */
+#define GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE*/
+#define _GPIO_MODEM_ANTSWUSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_MODEM_ANTSWUSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE */
+#define GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE*/
+
+/* Bit fields for GPIO_MODEM ANTTRIGROUTE */
+#define _GPIO_MODEM_ANTTRIGROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTTRIGROUTE */
+#define _GPIO_MODEM_ANTTRIGROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTTRIGROUTE */
+#define _GPIO_MODEM_ANTTRIGROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_MODEM_ANTTRIGROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE */
+#define GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE*/
+#define _GPIO_MODEM_ANTTRIGROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_MODEM_ANTTRIGROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE */
+#define GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE*/
+
+/* Bit fields for GPIO_MODEM ANTTRIGSTOPROUTE */
+#define _GPIO_MODEM_ANTTRIGSTOPROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTTRIGSTOPROUTE*/
+#define _GPIO_MODEM_ANTTRIGSTOPROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTTRIGSTOPROUTE */
+#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/
+#define GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/
+#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/
+#define GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/
+
+/* Bit fields for GPIO_MODEM DCLKROUTE */
+#define _GPIO_MODEM_DCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DCLKROUTE */
+#define _GPIO_MODEM_DCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DCLKROUTE */
+#define _GPIO_MODEM_DCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_MODEM_DCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_MODEM_DCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DCLKROUTE */
+#define GPIO_MODEM_DCLKROUTE_PORT_DEFAULT (_GPIO_MODEM_DCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DCLKROUTE*/
+#define _GPIO_MODEM_DCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_MODEM_DCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_MODEM_DCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DCLKROUTE */
+#define GPIO_MODEM_DCLKROUTE_PIN_DEFAULT (_GPIO_MODEM_DCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DCLKROUTE*/
+
+/* Bit fields for GPIO_MODEM DINROUTE */
+#define _GPIO_MODEM_DINROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DINROUTE */
+#define _GPIO_MODEM_DINROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DINROUTE */
+#define _GPIO_MODEM_DINROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_MODEM_DINROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_MODEM_DINROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DINROUTE */
+#define GPIO_MODEM_DINROUTE_PORT_DEFAULT (_GPIO_MODEM_DINROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DINROUTE*/
+#define _GPIO_MODEM_DINROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_MODEM_DINROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_MODEM_DINROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DINROUTE */
+#define GPIO_MODEM_DINROUTE_PIN_DEFAULT (_GPIO_MODEM_DINROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DINROUTE*/
+
+/* Bit fields for GPIO_MODEM DOUTROUTE */
+#define _GPIO_MODEM_DOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DOUTROUTE */
+#define _GPIO_MODEM_DOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DOUTROUTE */
+#define _GPIO_MODEM_DOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_MODEM_DOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_MODEM_DOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DOUTROUTE */
+#define GPIO_MODEM_DOUTROUTE_PORT_DEFAULT (_GPIO_MODEM_DOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DOUTROUTE*/
+#define _GPIO_MODEM_DOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_MODEM_DOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_MODEM_DOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DOUTROUTE */
+#define GPIO_MODEM_DOUTROUTE_PIN_DEFAULT (_GPIO_MODEM_DOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DOUTROUTE*/
+
+/* Bit fields for GPIO_PCNT S0INROUTE */
+#define _GPIO_PCNT_S0INROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PCNT_S0INROUTE */
+#define _GPIO_PCNT_S0INROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PCNT_S0INROUTE */
+#define _GPIO_PCNT_S0INROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_PCNT_S0INROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_PCNT_S0INROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S0INROUTE */
+#define GPIO_PCNT_S0INROUTE_PORT_DEFAULT (_GPIO_PCNT_S0INROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PCNT_S0INROUTE*/
+#define _GPIO_PCNT_S0INROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_PCNT_S0INROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_PCNT_S0INROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S0INROUTE */
+#define GPIO_PCNT_S0INROUTE_PIN_DEFAULT (_GPIO_PCNT_S0INROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PCNT_S0INROUTE*/
+
+/* Bit fields for GPIO_PCNT S1INROUTE */
+#define _GPIO_PCNT_S1INROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PCNT_S1INROUTE */
+#define _GPIO_PCNT_S1INROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PCNT_S1INROUTE */
+#define _GPIO_PCNT_S1INROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_PCNT_S1INROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_PCNT_S1INROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S1INROUTE */
+#define GPIO_PCNT_S1INROUTE_PORT_DEFAULT (_GPIO_PCNT_S1INROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PCNT_S1INROUTE*/
+#define _GPIO_PCNT_S1INROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_PCNT_S1INROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_PCNT_S1INROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S1INROUTE */
+#define GPIO_PCNT_S1INROUTE_PIN_DEFAULT (_GPIO_PCNT_S1INROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PCNT_S1INROUTE*/
+
+/* Bit fields for GPIO_PRS ROUTEEN */
+#define _GPIO_PRS_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ROUTEEN */
+#define _GPIO_PRS_ROUTEEN_MASK 0x000FFFFFUL /**< Mask for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH0PEN (0x1UL << 0) /**< ASYNCH0 pin enable control bit */
+#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_SHIFT 0 /**< Shift value for GPIO_ASYNCH0PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_MASK 0x1UL /**< Bit mask for GPIO_ASYNCH0PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH1PEN (0x1UL << 1) /**< ASYNCH1 pin enable control bit */
+#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_SHIFT 1 /**< Shift value for GPIO_ASYNCH1PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_MASK 0x2UL /**< Bit mask for GPIO_ASYNCH1PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH2PEN (0x1UL << 2) /**< ASYNCH2 pin enable control bit */
+#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_SHIFT 2 /**< Shift value for GPIO_ASYNCH2PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_MASK 0x4UL /**< Bit mask for GPIO_ASYNCH2PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH3PEN (0x1UL << 3) /**< ASYNCH3 pin enable control bit */
+#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_SHIFT 3 /**< Shift value for GPIO_ASYNCH3PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_MASK 0x8UL /**< Bit mask for GPIO_ASYNCH3PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH4PEN (0x1UL << 4) /**< ASYNCH4 pin enable control bit */
+#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_SHIFT 4 /**< Shift value for GPIO_ASYNCH4PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_MASK 0x10UL /**< Bit mask for GPIO_ASYNCH4PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH5PEN (0x1UL << 5) /**< ASYNCH5 pin enable control bit */
+#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_SHIFT 5 /**< Shift value for GPIO_ASYNCH5PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_MASK 0x20UL /**< Bit mask for GPIO_ASYNCH5PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH6PEN (0x1UL << 6) /**< ASYNCH6 pin enable control bit */
+#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_SHIFT 6 /**< Shift value for GPIO_ASYNCH6PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_MASK 0x40UL /**< Bit mask for GPIO_ASYNCH6PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH7PEN (0x1UL << 7) /**< ASYNCH7 pin enable control bit */
+#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_SHIFT 7 /**< Shift value for GPIO_ASYNCH7PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_MASK 0x80UL /**< Bit mask for GPIO_ASYNCH7PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH8PEN (0x1UL << 8) /**< ASYNCH8 pin enable control bit */
+#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_SHIFT 8 /**< Shift value for GPIO_ASYNCH8PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_MASK 0x100UL /**< Bit mask for GPIO_ASYNCH8PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH9PEN (0x1UL << 9) /**< ASYNCH9 pin enable control bit */
+#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_SHIFT 9 /**< Shift value for GPIO_ASYNCH9PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_MASK 0x200UL /**< Bit mask for GPIO_ASYNCH9PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH10PEN (0x1UL << 10) /**< ASYNCH10 pin enable control bit */
+#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_SHIFT 10 /**< Shift value for GPIO_ASYNCH10PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_MASK 0x400UL /**< Bit mask for GPIO_ASYNCH10PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH11PEN (0x1UL << 11) /**< ASYNCH11 pin enable control bit */
+#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_SHIFT 11 /**< Shift value for GPIO_ASYNCH11PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_MASK 0x800UL /**< Bit mask for GPIO_ASYNCH11PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH12PEN (0x1UL << 12) /**< ASYNCH12 pin enable control bit */
+#define _GPIO_PRS_ROUTEEN_ASYNCH12PEN_SHIFT 12 /**< Shift value for GPIO_ASYNCH12PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH12PEN_MASK 0x1000UL /**< Bit mask for GPIO_ASYNCH12PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH12PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH13PEN (0x1UL << 13) /**< ASYNCH13 pin enable control bit */
+#define _GPIO_PRS_ROUTEEN_ASYNCH13PEN_SHIFT 13 /**< Shift value for GPIO_ASYNCH13PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH13PEN_MASK 0x2000UL /**< Bit mask for GPIO_ASYNCH13PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH13PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH14PEN (0x1UL << 14) /**< ASYNCH14 pin enable control bit */
+#define _GPIO_PRS_ROUTEEN_ASYNCH14PEN_SHIFT 14 /**< Shift value for GPIO_ASYNCH14PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH14PEN_MASK 0x4000UL /**< Bit mask for GPIO_ASYNCH14PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH14PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH15PEN (0x1UL << 15) /**< ASYNCH15 pin enable control bit */
+#define _GPIO_PRS_ROUTEEN_ASYNCH15PEN_SHIFT 15 /**< Shift value for GPIO_ASYNCH15PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH15PEN_MASK 0x8000UL /**< Bit mask for GPIO_ASYNCH15PEN */
+#define _GPIO_PRS_ROUTEEN_ASYNCH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_ASYNCH15PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_SYNCH0PEN (0x1UL << 16) /**< SYNCH0 pin enable control bit */
+#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_SHIFT 16 /**< Shift value for GPIO_SYNCH0PEN */
+#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_MASK 0x10000UL /**< Bit mask for GPIO_SYNCH0PEN */
+#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_SYNCH1PEN (0x1UL << 17) /**< SYNCH1 pin enable control bit */
+#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_SHIFT 17 /**< Shift value for GPIO_SYNCH1PEN */
+#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_MASK 0x20000UL /**< Bit mask for GPIO_SYNCH1PEN */
+#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_SYNCH2PEN (0x1UL << 18) /**< SYNCH2 pin enable control bit */
+#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_SHIFT 18 /**< Shift value for GPIO_SYNCH2PEN */
+#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_MASK 0x40000UL /**< Bit mask for GPIO_SYNCH2PEN */
+#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_SYNCH3PEN (0x1UL << 19) /**< SYNCH3 pin enable control bit */
+#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_SHIFT 19 /**< Shift value for GPIO_SYNCH3PEN */
+#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_MASK 0x80000UL /**< Bit mask for GPIO_SYNCH3PEN */
+#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */
+#define GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */
+
+/* Bit fields for GPIO_PRS ASYNCH0ROUTE */
+#define _GPIO_PRS_ASYNCH0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH0ROUTE */
+#define _GPIO_PRS_ASYNCH0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH0ROUTE */
+#define _GPIO_PRS_ASYNCH0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE */
+#define GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE*/
+#define _GPIO_PRS_ASYNCH0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE */
+#define GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE*/
+
+/* Bit fields for GPIO_PRS ASYNCH1ROUTE */
+#define _GPIO_PRS_ASYNCH1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH1ROUTE */
+#define _GPIO_PRS_ASYNCH1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH1ROUTE */
+#define _GPIO_PRS_ASYNCH1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE */
+#define GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE*/
+#define _GPIO_PRS_ASYNCH1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE */
+#define GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE*/
+
+/* Bit fields for GPIO_PRS ASYNCH2ROUTE */
+#define _GPIO_PRS_ASYNCH2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH2ROUTE */
+#define _GPIO_PRS_ASYNCH2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH2ROUTE */
+#define _GPIO_PRS_ASYNCH2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE */
+#define GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE*/
+#define _GPIO_PRS_ASYNCH2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE */
+#define GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE*/
+
+/* Bit fields for GPIO_PRS ASYNCH3ROUTE */
+#define _GPIO_PRS_ASYNCH3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH3ROUTE */
+#define _GPIO_PRS_ASYNCH3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH3ROUTE */
+#define _GPIO_PRS_ASYNCH3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE */
+#define GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE*/
+#define _GPIO_PRS_ASYNCH3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE */
+#define GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE*/
+
+/* Bit fields for GPIO_PRS ASYNCH4ROUTE */
+#define _GPIO_PRS_ASYNCH4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH4ROUTE */
+#define _GPIO_PRS_ASYNCH4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH4ROUTE */
+#define _GPIO_PRS_ASYNCH4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE */
+#define GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE*/
+#define _GPIO_PRS_ASYNCH4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE */
+#define GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE*/
+
+/* Bit fields for GPIO_PRS ASYNCH5ROUTE */
+#define _GPIO_PRS_ASYNCH5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH5ROUTE */
+#define _GPIO_PRS_ASYNCH5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH5ROUTE */
+#define _GPIO_PRS_ASYNCH5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE */
+#define GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE*/
+#define _GPIO_PRS_ASYNCH5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE */
+#define GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE*/
+
+/* Bit fields for GPIO_PRS ASYNCH6ROUTE */
+#define _GPIO_PRS_ASYNCH6ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH6ROUTE */
+#define _GPIO_PRS_ASYNCH6ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH6ROUTE */
+#define _GPIO_PRS_ASYNCH6ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH6ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE */
+#define GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE*/
+#define _GPIO_PRS_ASYNCH6ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH6ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE */
+#define GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE*/
+
+/* Bit fields for GPIO_PRS ASYNCH7ROUTE */
+#define _GPIO_PRS_ASYNCH7ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH7ROUTE */
+#define _GPIO_PRS_ASYNCH7ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH7ROUTE */
+#define _GPIO_PRS_ASYNCH7ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH7ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE */
+#define GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE*/
+#define _GPIO_PRS_ASYNCH7ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH7ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE */
+#define GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE*/
+
+/* Bit fields for GPIO_PRS ASYNCH8ROUTE */
+#define _GPIO_PRS_ASYNCH8ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH8ROUTE */
+#define _GPIO_PRS_ASYNCH8ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH8ROUTE */
+#define _GPIO_PRS_ASYNCH8ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH8ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE */
+#define GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE*/
+#define _GPIO_PRS_ASYNCH8ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH8ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE */
+#define GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE*/
+
+/* Bit fields for GPIO_PRS ASYNCH9ROUTE */
+#define _GPIO_PRS_ASYNCH9ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH9ROUTE */
+#define _GPIO_PRS_ASYNCH9ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH9ROUTE */
+#define _GPIO_PRS_ASYNCH9ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH9ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE */
+#define GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE*/
+#define _GPIO_PRS_ASYNCH9ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH9ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE */
+#define GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE*/
+
+/* Bit fields for GPIO_PRS ASYNCH10ROUTE */
+#define _GPIO_PRS_ASYNCH10ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH10ROUTE */
+#define _GPIO_PRS_ASYNCH10ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH10ROUTE */
+#define _GPIO_PRS_ASYNCH10ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH10ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE */
+#define GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE*/
+#define _GPIO_PRS_ASYNCH10ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH10ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE */
+#define GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE*/
+
+/* Bit fields for GPIO_PRS ASYNCH11ROUTE */
+#define _GPIO_PRS_ASYNCH11ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH11ROUTE */
+#define _GPIO_PRS_ASYNCH11ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH11ROUTE */
+#define _GPIO_PRS_ASYNCH11ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH11ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE */
+#define GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE*/
+#define _GPIO_PRS_ASYNCH11ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH11ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE */
+#define GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE*/
+
+/* Bit fields for GPIO_PRS ASYNCH12ROUTE */
+#define _GPIO_PRS_ASYNCH12ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH12ROUTE */
+#define _GPIO_PRS_ASYNCH12ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH12ROUTE */
+#define _GPIO_PRS_ASYNCH12ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH12ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH12ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH12ROUTE */
+#define GPIO_PRS_ASYNCH12ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH12ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH12ROUTE*/
+#define _GPIO_PRS_ASYNCH12ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH12ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH12ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH12ROUTE */
+#define GPIO_PRS_ASYNCH12ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH12ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH12ROUTE*/
+
+/* Bit fields for GPIO_PRS ASYNCH13ROUTE */
+#define _GPIO_PRS_ASYNCH13ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH13ROUTE */
+#define _GPIO_PRS_ASYNCH13ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH13ROUTE */
+#define _GPIO_PRS_ASYNCH13ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH13ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH13ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH13ROUTE */
+#define GPIO_PRS_ASYNCH13ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH13ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH13ROUTE*/
+#define _GPIO_PRS_ASYNCH13ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH13ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH13ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH13ROUTE */
+#define GPIO_PRS_ASYNCH13ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH13ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH13ROUTE*/
+
+/* Bit fields for GPIO_PRS ASYNCH14ROUTE */
+#define _GPIO_PRS_ASYNCH14ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH14ROUTE */
+#define _GPIO_PRS_ASYNCH14ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH14ROUTE */
+#define _GPIO_PRS_ASYNCH14ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH14ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH14ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH14ROUTE */
+#define GPIO_PRS_ASYNCH14ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH14ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH14ROUTE*/
+#define _GPIO_PRS_ASYNCH14ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH14ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH14ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH14ROUTE */
+#define GPIO_PRS_ASYNCH14ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH14ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH14ROUTE*/
+
+/* Bit fields for GPIO_PRS ASYNCH15ROUTE */
+#define _GPIO_PRS_ASYNCH15ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH15ROUTE */
+#define _GPIO_PRS_ASYNCH15ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH15ROUTE */
+#define _GPIO_PRS_ASYNCH15ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH15ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_PRS_ASYNCH15ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH15ROUTE */
+#define GPIO_PRS_ASYNCH15ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH15ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH15ROUTE*/
+#define _GPIO_PRS_ASYNCH15ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH15ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_PRS_ASYNCH15ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH15ROUTE */
+#define GPIO_PRS_ASYNCH15ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH15ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH15ROUTE*/
+
+/* Bit fields for GPIO_PRS SYNCH0ROUTE */
+#define _GPIO_PRS_SYNCH0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH0ROUTE */
+#define _GPIO_PRS_SYNCH0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH0ROUTE */
+#define _GPIO_PRS_SYNCH0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_PRS_SYNCH0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH0ROUTE */
+#define GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH0ROUTE*/
+#define _GPIO_PRS_SYNCH0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_PRS_SYNCH0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH0ROUTE */
+#define GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH0ROUTE*/
+
+/* Bit fields for GPIO_PRS SYNCH1ROUTE */
+#define _GPIO_PRS_SYNCH1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH1ROUTE */
+#define _GPIO_PRS_SYNCH1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH1ROUTE */
+#define _GPIO_PRS_SYNCH1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_PRS_SYNCH1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH1ROUTE */
+#define GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH1ROUTE*/
+#define _GPIO_PRS_SYNCH1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_PRS_SYNCH1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH1ROUTE */
+#define GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH1ROUTE*/
+
+/* Bit fields for GPIO_PRS SYNCH2ROUTE */
+#define _GPIO_PRS_SYNCH2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH2ROUTE */
+#define _GPIO_PRS_SYNCH2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH2ROUTE */
+#define _GPIO_PRS_SYNCH2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_PRS_SYNCH2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH2ROUTE */
+#define GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH2ROUTE*/
+#define _GPIO_PRS_SYNCH2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_PRS_SYNCH2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH2ROUTE */
+#define GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH2ROUTE*/
+
+/* Bit fields for GPIO_PRS SYNCH3ROUTE */
+#define _GPIO_PRS_SYNCH3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH3ROUTE */
+#define _GPIO_PRS_SYNCH3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH3ROUTE */
+#define _GPIO_PRS_SYNCH3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_PRS_SYNCH3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH3ROUTE */
+#define GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH3ROUTE*/
+#define _GPIO_PRS_SYNCH3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_PRS_SYNCH3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH3ROUTE */
+#define GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH3ROUTE*/
+
+/* Bit fields for GPIO_RAC ROUTEEN */
+#define _GPIO_RAC_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_RAC_ROUTEEN */
+#define _GPIO_RAC_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_RAC_ROUTEEN */
+#define GPIO_RAC_ROUTEEN_LNAENPEN (0x1UL << 0) /**< LNAEN pin enable control bit */
+#define _GPIO_RAC_ROUTEEN_LNAENPEN_SHIFT 0 /**< Shift value for GPIO_LNAENPEN */
+#define _GPIO_RAC_ROUTEEN_LNAENPEN_MASK 0x1UL /**< Bit mask for GPIO_LNAENPEN */
+#define _GPIO_RAC_ROUTEEN_LNAENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_RAC_ROUTEEN */
+#define GPIO_RAC_ROUTEEN_LNAENPEN_DEFAULT (_GPIO_RAC_ROUTEEN_LNAENPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_RAC_ROUTEEN */
+#define GPIO_RAC_ROUTEEN_PAENPEN (0x1UL << 1) /**< PAEN pin enable control bit */
+#define _GPIO_RAC_ROUTEEN_PAENPEN_SHIFT 1 /**< Shift value for GPIO_PAENPEN */
+#define _GPIO_RAC_ROUTEEN_PAENPEN_MASK 0x2UL /**< Bit mask for GPIO_PAENPEN */
+#define _GPIO_RAC_ROUTEEN_PAENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_RAC_ROUTEEN */
+#define GPIO_RAC_ROUTEEN_PAENPEN_DEFAULT (_GPIO_RAC_ROUTEEN_PAENPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_RAC_ROUTEEN */
+
+/* Bit fields for GPIO_RAC LNAENROUTE */
+#define _GPIO_RAC_LNAENROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_RAC_LNAENROUTE */
+#define _GPIO_RAC_LNAENROUTE_MASK 0x000F0003UL /**< Mask for GPIO_RAC_LNAENROUTE */
+#define _GPIO_RAC_LNAENROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_RAC_LNAENROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_RAC_LNAENROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_RAC_LNAENROUTE */
+#define GPIO_RAC_LNAENROUTE_PORT_DEFAULT (_GPIO_RAC_LNAENROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_RAC_LNAENROUTE*/
+#define _GPIO_RAC_LNAENROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_RAC_LNAENROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_RAC_LNAENROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_RAC_LNAENROUTE */
+#define GPIO_RAC_LNAENROUTE_PIN_DEFAULT (_GPIO_RAC_LNAENROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_RAC_LNAENROUTE*/
+
+/* Bit fields for GPIO_RAC PAENROUTE */
+#define _GPIO_RAC_PAENROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_RAC_PAENROUTE */
+#define _GPIO_RAC_PAENROUTE_MASK 0x000F0003UL /**< Mask for GPIO_RAC_PAENROUTE */
+#define _GPIO_RAC_PAENROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_RAC_PAENROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_RAC_PAENROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_RAC_PAENROUTE */
+#define GPIO_RAC_PAENROUTE_PORT_DEFAULT (_GPIO_RAC_PAENROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_RAC_PAENROUTE */
+#define _GPIO_RAC_PAENROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_RAC_PAENROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_RAC_PAENROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_RAC_PAENROUTE */
+#define GPIO_RAC_PAENROUTE_PIN_DEFAULT (_GPIO_RAC_PAENROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_RAC_PAENROUTE */
+
+/* Bit fields for GPIO_SYXO BUFOUTREQINASYNCROUTE */
+#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/
+#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_MASK 0x000F0003UL /**< Mask for GPIO_SYXO_BUFOUTREQINASYNCROUTE */
+#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/
+#define GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_DEFAULT (_GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/
+#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/
+#define GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_DEFAULT (_GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/
+
+/* Bit fields for GPIO_TIMER ROUTEEN */
+#define _GPIO_TIMER_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_ROUTEEN */
+#define _GPIO_TIMER_ROUTEEN_MASK 0x0000003FUL /**< Mask for GPIO_TIMER_ROUTEEN */
+#define GPIO_TIMER_ROUTEEN_CC0PEN (0x1UL << 0) /**< CC0 pin enable control bit */
+#define _GPIO_TIMER_ROUTEEN_CC0PEN_SHIFT 0 /**< Shift value for GPIO_CC0PEN */
+#define _GPIO_TIMER_ROUTEEN_CC0PEN_MASK 0x1UL /**< Bit mask for GPIO_CC0PEN */
+#define _GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */
+#define GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */
+#define GPIO_TIMER_ROUTEEN_CC1PEN (0x1UL << 1) /**< CC1 pin enable control bit */
+#define _GPIO_TIMER_ROUTEEN_CC1PEN_SHIFT 1 /**< Shift value for GPIO_CC1PEN */
+#define _GPIO_TIMER_ROUTEEN_CC1PEN_MASK 0x2UL /**< Bit mask for GPIO_CC1PEN */
+#define _GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */
+#define GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */
+#define GPIO_TIMER_ROUTEEN_CC2PEN (0x1UL << 2) /**< CC2 pin enable control bit */
+#define _GPIO_TIMER_ROUTEEN_CC2PEN_SHIFT 2 /**< Shift value for GPIO_CC2PEN */
+#define _GPIO_TIMER_ROUTEEN_CC2PEN_MASK 0x4UL /**< Bit mask for GPIO_CC2PEN */
+#define _GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */
+#define GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */
+#define GPIO_TIMER_ROUTEEN_CCC0PEN (0x1UL << 3) /**< CCC0 pin enable control bit */
+#define _GPIO_TIMER_ROUTEEN_CCC0PEN_SHIFT 3 /**< Shift value for GPIO_CCC0PEN */
+#define _GPIO_TIMER_ROUTEEN_CCC0PEN_MASK 0x8UL /**< Bit mask for GPIO_CCC0PEN */
+#define _GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */
+#define GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */
+#define GPIO_TIMER_ROUTEEN_CCC1PEN (0x1UL << 4) /**< CCC1 pin enable control bit */
+#define _GPIO_TIMER_ROUTEEN_CCC1PEN_SHIFT 4 /**< Shift value for GPIO_CCC1PEN */
+#define _GPIO_TIMER_ROUTEEN_CCC1PEN_MASK 0x10UL /**< Bit mask for GPIO_CCC1PEN */
+#define _GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */
+#define GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */
+#define GPIO_TIMER_ROUTEEN_CCC2PEN (0x1UL << 5) /**< CCC2 pin enable control bit */
+#define _GPIO_TIMER_ROUTEEN_CCC2PEN_SHIFT 5 /**< Shift value for GPIO_CCC2PEN */
+#define _GPIO_TIMER_ROUTEEN_CCC2PEN_MASK 0x20UL /**< Bit mask for GPIO_CCC2PEN */
+#define _GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */
+#define GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */
+
+/* Bit fields for GPIO_TIMER CC0ROUTE */
+#define _GPIO_TIMER_CC0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC0ROUTE */
+#define _GPIO_TIMER_CC0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC0ROUTE */
+#define _GPIO_TIMER_CC0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_TIMER_CC0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_TIMER_CC0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC0ROUTE */
+#define GPIO_TIMER_CC0ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC0ROUTE*/
+#define _GPIO_TIMER_CC0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_TIMER_CC0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_TIMER_CC0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC0ROUTE */
+#define GPIO_TIMER_CC0ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC0ROUTE*/
+
+/* Bit fields for GPIO_TIMER CC1ROUTE */
+#define _GPIO_TIMER_CC1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC1ROUTE */
+#define _GPIO_TIMER_CC1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC1ROUTE */
+#define _GPIO_TIMER_CC1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_TIMER_CC1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_TIMER_CC1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC1ROUTE */
+#define GPIO_TIMER_CC1ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC1ROUTE*/
+#define _GPIO_TIMER_CC1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_TIMER_CC1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_TIMER_CC1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC1ROUTE */
+#define GPIO_TIMER_CC1ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC1ROUTE*/
+
+/* Bit fields for GPIO_TIMER CC2ROUTE */
+#define _GPIO_TIMER_CC2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC2ROUTE */
+#define _GPIO_TIMER_CC2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC2ROUTE */
+#define _GPIO_TIMER_CC2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_TIMER_CC2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_TIMER_CC2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC2ROUTE */
+#define GPIO_TIMER_CC2ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC2ROUTE*/
+#define _GPIO_TIMER_CC2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_TIMER_CC2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_TIMER_CC2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC2ROUTE */
+#define GPIO_TIMER_CC2ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC2ROUTE*/
+
+/* Bit fields for GPIO_TIMER CDTI0ROUTE */
+#define _GPIO_TIMER_CDTI0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI0ROUTE */
+#define _GPIO_TIMER_CDTI0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI0ROUTE */
+#define _GPIO_TIMER_CDTI0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_TIMER_CDTI0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI0ROUTE */
+#define GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI0ROUTE*/
+#define _GPIO_TIMER_CDTI0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_TIMER_CDTI0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI0ROUTE */
+#define GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI0ROUTE*/
+
+/* Bit fields for GPIO_TIMER CDTI1ROUTE */
+#define _GPIO_TIMER_CDTI1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI1ROUTE */
+#define _GPIO_TIMER_CDTI1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI1ROUTE */
+#define _GPIO_TIMER_CDTI1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_TIMER_CDTI1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI1ROUTE */
+#define GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI1ROUTE*/
+#define _GPIO_TIMER_CDTI1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_TIMER_CDTI1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI1ROUTE */
+#define GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI1ROUTE*/
+
+/* Bit fields for GPIO_TIMER CDTI2ROUTE */
+#define _GPIO_TIMER_CDTI2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI2ROUTE */
+#define _GPIO_TIMER_CDTI2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI2ROUTE */
+#define _GPIO_TIMER_CDTI2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_TIMER_CDTI2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI2ROUTE */
+#define GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI2ROUTE*/
+#define _GPIO_TIMER_CDTI2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_TIMER_CDTI2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI2ROUTE */
+#define GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI2ROUTE*/
+
+/* Bit fields for GPIO_USART ROUTEEN */
+#define _GPIO_USART_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_ROUTEEN */
+#define _GPIO_USART_ROUTEEN_MASK 0x0000001FUL /**< Mask for GPIO_USART_ROUTEEN */
+#define GPIO_USART_ROUTEEN_CSPEN (0x1UL << 0) /**< CS pin enable control bit */
+#define _GPIO_USART_ROUTEEN_CSPEN_SHIFT 0 /**< Shift value for GPIO_CSPEN */
+#define _GPIO_USART_ROUTEEN_CSPEN_MASK 0x1UL /**< Bit mask for GPIO_CSPEN */
+#define _GPIO_USART_ROUTEEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */
+#define GPIO_USART_ROUTEEN_CSPEN_DEFAULT (_GPIO_USART_ROUTEEN_CSPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */
+#define GPIO_USART_ROUTEEN_RTSPEN (0x1UL << 1) /**< RTS pin enable control bit */
+#define _GPIO_USART_ROUTEEN_RTSPEN_SHIFT 1 /**< Shift value for GPIO_RTSPEN */
+#define _GPIO_USART_ROUTEEN_RTSPEN_MASK 0x2UL /**< Bit mask for GPIO_RTSPEN */
+#define _GPIO_USART_ROUTEEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */
+#define GPIO_USART_ROUTEEN_RTSPEN_DEFAULT (_GPIO_USART_ROUTEEN_RTSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */
+#define GPIO_USART_ROUTEEN_RXPEN (0x1UL << 2) /**< RX pin enable control bit */
+#define _GPIO_USART_ROUTEEN_RXPEN_SHIFT 2 /**< Shift value for GPIO_RXPEN */
+#define _GPIO_USART_ROUTEEN_RXPEN_MASK 0x4UL /**< Bit mask for GPIO_RXPEN */
+#define _GPIO_USART_ROUTEEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */
+#define GPIO_USART_ROUTEEN_RXPEN_DEFAULT (_GPIO_USART_ROUTEEN_RXPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */
+#define GPIO_USART_ROUTEEN_CLKPEN (0x1UL << 3) /**< SCLK pin enable control bit */
+#define _GPIO_USART_ROUTEEN_CLKPEN_SHIFT 3 /**< Shift value for GPIO_CLKPEN */
+#define _GPIO_USART_ROUTEEN_CLKPEN_MASK 0x8UL /**< Bit mask for GPIO_CLKPEN */
+#define _GPIO_USART_ROUTEEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */
+#define GPIO_USART_ROUTEEN_CLKPEN_DEFAULT (_GPIO_USART_ROUTEEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */
+#define GPIO_USART_ROUTEEN_TXPEN (0x1UL << 4) /**< TX pin enable control bit */
+#define _GPIO_USART_ROUTEEN_TXPEN_SHIFT 4 /**< Shift value for GPIO_TXPEN */
+#define _GPIO_USART_ROUTEEN_TXPEN_MASK 0x10UL /**< Bit mask for GPIO_TXPEN */
+#define _GPIO_USART_ROUTEEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */
+#define GPIO_USART_ROUTEEN_TXPEN_DEFAULT (_GPIO_USART_ROUTEEN_TXPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */
+
+/* Bit fields for GPIO_USART CSROUTE */
+#define _GPIO_USART_CSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CSROUTE */
+#define _GPIO_USART_CSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CSROUTE */
+#define _GPIO_USART_CSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_USART_CSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_USART_CSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CSROUTE */
+#define GPIO_USART_CSROUTE_PORT_DEFAULT (_GPIO_USART_CSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CSROUTE */
+#define _GPIO_USART_CSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_USART_CSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_USART_CSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CSROUTE */
+#define GPIO_USART_CSROUTE_PIN_DEFAULT (_GPIO_USART_CSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CSROUTE */
+
+/* Bit fields for GPIO_USART CTSROUTE */
+#define _GPIO_USART_CTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CTSROUTE */
+#define _GPIO_USART_CTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CTSROUTE */
+#define _GPIO_USART_CTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_USART_CTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_USART_CTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CTSROUTE */
+#define GPIO_USART_CTSROUTE_PORT_DEFAULT (_GPIO_USART_CTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CTSROUTE*/
+#define _GPIO_USART_CTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_USART_CTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_USART_CTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CTSROUTE */
+#define GPIO_USART_CTSROUTE_PIN_DEFAULT (_GPIO_USART_CTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CTSROUTE*/
+
+/* Bit fields for GPIO_USART RTSROUTE */
+#define _GPIO_USART_RTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_RTSROUTE */
+#define _GPIO_USART_RTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_RTSROUTE */
+#define _GPIO_USART_RTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_USART_RTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_USART_RTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RTSROUTE */
+#define GPIO_USART_RTSROUTE_PORT_DEFAULT (_GPIO_USART_RTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_RTSROUTE*/
+#define _GPIO_USART_RTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_USART_RTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_USART_RTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RTSROUTE */
+#define GPIO_USART_RTSROUTE_PIN_DEFAULT (_GPIO_USART_RTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_RTSROUTE*/
+
+/* Bit fields for GPIO_USART RXROUTE */
+#define _GPIO_USART_RXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_RXROUTE */
+#define _GPIO_USART_RXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_RXROUTE */
+#define _GPIO_USART_RXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_USART_RXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_USART_RXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RXROUTE */
+#define GPIO_USART_RXROUTE_PORT_DEFAULT (_GPIO_USART_RXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_RXROUTE */
+#define _GPIO_USART_RXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_USART_RXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_USART_RXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RXROUTE */
+#define GPIO_USART_RXROUTE_PIN_DEFAULT (_GPIO_USART_RXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_RXROUTE */
+
+/* Bit fields for GPIO_USART CLKROUTE */
+#define _GPIO_USART_CLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CLKROUTE */
+#define _GPIO_USART_CLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CLKROUTE */
+#define _GPIO_USART_CLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_USART_CLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_USART_CLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CLKROUTE */
+#define GPIO_USART_CLKROUTE_PORT_DEFAULT (_GPIO_USART_CLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CLKROUTE*/
+#define _GPIO_USART_CLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_USART_CLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_USART_CLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CLKROUTE */
+#define GPIO_USART_CLKROUTE_PIN_DEFAULT (_GPIO_USART_CLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CLKROUTE*/
+
+/* Bit fields for GPIO_USART TXROUTE */
+#define _GPIO_USART_TXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_TXROUTE */
+#define _GPIO_USART_TXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_TXROUTE */
+#define _GPIO_USART_TXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */
+#define _GPIO_USART_TXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */
+#define _GPIO_USART_TXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_TXROUTE */
+#define GPIO_USART_TXROUTE_PORT_DEFAULT (_GPIO_USART_TXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_TXROUTE */
+#define _GPIO_USART_TXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */
+#define _GPIO_USART_TXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */
+#define _GPIO_USART_TXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_TXROUTE */
+#define GPIO_USART_TXROUTE_PIN_DEFAULT (_GPIO_USART_TXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_TXROUTE */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_GPIO_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_gpio_port.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_gpio_port.h
new file mode 100644
index 00000000..898d4a1c
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_gpio_port.h
@@ -0,0 +1,457 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 GPIO Port register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef GPIO_PORT_H
+#define GPIO_PORT_H
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @brief EFR32MG24 GPIO PORT
+ *****************************************************************************/
+typedef struct {
+ __IOM uint32_t CTRL; /**< Port control */
+ __IOM uint32_t MODEL; /**< mode low */
+ uint32_t RESERVED0[1]; /**< Reserved for future use */
+ __IOM uint32_t MODEH; /**< mode high */
+ __IOM uint32_t DOUT; /**< data out */
+ __IM uint32_t DIN; /**< data in */
+ uint32_t RESERVED1[6]; /**< Reserved for future use */
+} GPIO_PORT_TypeDef;
+
+/* Bit fields for GPIO_P CTRL */
+#define _GPIO_P_CTRL_RESETVALUE 0x00400040UL /**< Default value for GPIO_P_CTRL */
+#define _GPIO_P_CTRL_MASK 0x10701070UL /**< Mask for GPIO_P_CTRL */
+#define _GPIO_P_CTRL_SLEWRATE_SHIFT 4 /**< Shift value for GPIO_SLEWRATE */
+#define _GPIO_P_CTRL_SLEWRATE_MASK 0x70UL /**< Bit mask for GPIO_SLEWRATE */
+#define _GPIO_P_CTRL_SLEWRATE_DEFAULT 0x00000004UL /**< Mode DEFAULT for GPIO_P_CTRL */
+#define GPIO_P_CTRL_SLEWRATE_DEFAULT (_GPIO_P_CTRL_SLEWRATE_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_CTRL */
+#define GPIO_P_CTRL_DINDIS (0x1UL << 12) /**< Data In Disable */
+#define _GPIO_P_CTRL_DINDIS_SHIFT 12 /**< Shift value for GPIO_DINDIS */
+#define _GPIO_P_CTRL_DINDIS_MASK 0x1000UL /**< Bit mask for GPIO_DINDIS */
+#define _GPIO_P_CTRL_DINDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */
+#define GPIO_P_CTRL_DINDIS_DEFAULT (_GPIO_P_CTRL_DINDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_CTRL */
+#define _GPIO_P_CTRL_SLEWRATEALT_SHIFT 20 /**< Shift value for GPIO_SLEWRATEALT */
+#define _GPIO_P_CTRL_SLEWRATEALT_MASK 0x700000UL /**< Bit mask for GPIO_SLEWRATEALT */
+#define _GPIO_P_CTRL_SLEWRATEALT_DEFAULT 0x00000004UL /**< Mode DEFAULT for GPIO_P_CTRL */
+#define GPIO_P_CTRL_SLEWRATEALT_DEFAULT (_GPIO_P_CTRL_SLEWRATEALT_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_CTRL */
+#define GPIO_P_CTRL_DINDISALT (0x1UL << 28) /**< Data In Disable Alt */
+#define _GPIO_P_CTRL_DINDISALT_SHIFT 28 /**< Shift value for GPIO_DINDISALT */
+#define _GPIO_P_CTRL_DINDISALT_MASK 0x10000000UL /**< Bit mask for GPIO_DINDISALT */
+#define _GPIO_P_CTRL_DINDISALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */
+#define GPIO_P_CTRL_DINDISALT_DEFAULT (_GPIO_P_CTRL_DINDISALT_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_CTRL */
+
+/* Bit fields for GPIO_P MODEL */
+#define _GPIO_P_MODEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */
+#define _GPIO_P_MODEL_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */
+#define _GPIO_P_MODEL_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE0_DEFAULT (_GPIO_P_MODEL_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_DISABLED (_GPIO_P_MODEL_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_INPUT (_GPIO_P_MODEL_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_INPUTPULL (_GPIO_P_MODEL_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_INPUTPULLFILTER (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE0_PUSHPULL (_GPIO_P_MODEL_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_PUSHPULLALT (_GPIO_P_MODEL_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_WIREDOR (_GPIO_P_MODEL_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE0_WIREDAND (_GPIO_P_MODEL_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_WIREDANDFILTER (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE0_WIREDANDPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE0_WIREDANDALT (_GPIO_P_MODEL_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
+#define _GPIO_P_MODEL_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */
+#define _GPIO_P_MODEL_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */
+#define _GPIO_P_MODEL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE1_DEFAULT (_GPIO_P_MODEL_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_DISABLED (_GPIO_P_MODEL_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_INPUT (_GPIO_P_MODEL_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_INPUTPULL (_GPIO_P_MODEL_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_INPUTPULLFILTER (_GPIO_P_MODEL_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE1_PUSHPULL (_GPIO_P_MODEL_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_PUSHPULLALT (_GPIO_P_MODEL_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_WIREDOR (_GPIO_P_MODEL_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE1_WIREDAND (_GPIO_P_MODEL_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_WIREDANDFILTER (_GPIO_P_MODEL_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE1_WIREDANDPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE1_WIREDANDALT (_GPIO_P_MODEL_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
+#define _GPIO_P_MODEL_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */
+#define _GPIO_P_MODEL_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */
+#define _GPIO_P_MODEL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE2_DEFAULT (_GPIO_P_MODEL_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_DISABLED (_GPIO_P_MODEL_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_INPUT (_GPIO_P_MODEL_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_INPUTPULL (_GPIO_P_MODEL_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_INPUTPULLFILTER (_GPIO_P_MODEL_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE2_PUSHPULL (_GPIO_P_MODEL_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_PUSHPULLALT (_GPIO_P_MODEL_MODE2_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_WIREDOR (_GPIO_P_MODEL_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE2_WIREDAND (_GPIO_P_MODEL_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_WIREDANDFILTER (_GPIO_P_MODEL_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE2_WIREDANDPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE2_WIREDANDALT (_GPIO_P_MODEL_MODE2_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE2_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
+#define _GPIO_P_MODEL_MODE3_SHIFT 12 /**< Shift value for GPIO_MODE3 */
+#define _GPIO_P_MODEL_MODE3_MASK 0xF000UL /**< Bit mask for GPIO_MODE3 */
+#define _GPIO_P_MODEL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE3_DEFAULT (_GPIO_P_MODEL_MODE3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_DISABLED (_GPIO_P_MODEL_MODE3_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_INPUT (_GPIO_P_MODEL_MODE3_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_INPUTPULL (_GPIO_P_MODEL_MODE3_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_INPUTPULLFILTER (_GPIO_P_MODEL_MODE3_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE3_PUSHPULL (_GPIO_P_MODEL_MODE3_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_PUSHPULLALT (_GPIO_P_MODEL_MODE3_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_WIREDOR (_GPIO_P_MODEL_MODE3_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE3_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE3_WIREDAND (_GPIO_P_MODEL_MODE3_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_WIREDANDFILTER (_GPIO_P_MODEL_MODE3_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE3_WIREDANDPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE3_WIREDANDALT (_GPIO_P_MODEL_MODE3_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE3_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
+#define _GPIO_P_MODEL_MODE4_SHIFT 16 /**< Shift value for GPIO_MODE4 */
+#define _GPIO_P_MODEL_MODE4_MASK 0xF0000UL /**< Bit mask for GPIO_MODE4 */
+#define _GPIO_P_MODEL_MODE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE4_DEFAULT (_GPIO_P_MODEL_MODE4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_DISABLED (_GPIO_P_MODEL_MODE4_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_INPUT (_GPIO_P_MODEL_MODE4_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_INPUTPULL (_GPIO_P_MODEL_MODE4_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_INPUTPULLFILTER (_GPIO_P_MODEL_MODE4_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE4_PUSHPULL (_GPIO_P_MODEL_MODE4_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_PUSHPULLALT (_GPIO_P_MODEL_MODE4_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_WIREDOR (_GPIO_P_MODEL_MODE4_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE4_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE4_WIREDAND (_GPIO_P_MODEL_MODE4_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_WIREDANDFILTER (_GPIO_P_MODEL_MODE4_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE4_WIREDANDPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE4_WIREDANDALT (_GPIO_P_MODEL_MODE4_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE4_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
+#define _GPIO_P_MODEL_MODE5_SHIFT 20 /**< Shift value for GPIO_MODE5 */
+#define _GPIO_P_MODEL_MODE5_MASK 0xF00000UL /**< Bit mask for GPIO_MODE5 */
+#define _GPIO_P_MODEL_MODE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE5_DEFAULT (_GPIO_P_MODEL_MODE5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_DISABLED (_GPIO_P_MODEL_MODE5_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_INPUT (_GPIO_P_MODEL_MODE5_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_INPUTPULL (_GPIO_P_MODEL_MODE5_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_INPUTPULLFILTER (_GPIO_P_MODEL_MODE5_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE5_PUSHPULL (_GPIO_P_MODEL_MODE5_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_PUSHPULLALT (_GPIO_P_MODEL_MODE5_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_WIREDOR (_GPIO_P_MODEL_MODE5_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE5_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE5_WIREDAND (_GPIO_P_MODEL_MODE5_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_WIREDANDFILTER (_GPIO_P_MODEL_MODE5_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE5_WIREDANDPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE5_WIREDANDALT (_GPIO_P_MODEL_MODE5_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE5_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
+#define _GPIO_P_MODEL_MODE6_SHIFT 24 /**< Shift value for GPIO_MODE6 */
+#define _GPIO_P_MODEL_MODE6_MASK 0xF000000UL /**< Bit mask for GPIO_MODE6 */
+#define _GPIO_P_MODEL_MODE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE6_DEFAULT (_GPIO_P_MODEL_MODE6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_DISABLED (_GPIO_P_MODEL_MODE6_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_INPUT (_GPIO_P_MODEL_MODE6_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_INPUTPULL (_GPIO_P_MODEL_MODE6_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_INPUTPULLFILTER (_GPIO_P_MODEL_MODE6_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE6_PUSHPULL (_GPIO_P_MODEL_MODE6_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_PUSHPULLALT (_GPIO_P_MODEL_MODE6_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_WIREDOR (_GPIO_P_MODEL_MODE6_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE6_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE6_WIREDAND (_GPIO_P_MODEL_MODE6_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_WIREDANDFILTER (_GPIO_P_MODEL_MODE6_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE6_WIREDANDPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE6_WIREDANDALT (_GPIO_P_MODEL_MODE6_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE6_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
+#define _GPIO_P_MODEL_MODE7_SHIFT 28 /**< Shift value for GPIO_MODE7 */
+#define _GPIO_P_MODEL_MODE7_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE7 */
+#define _GPIO_P_MODEL_MODE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */
+#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE7_DEFAULT (_GPIO_P_MODEL_MODE7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_DISABLED (_GPIO_P_MODEL_MODE7_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_INPUT (_GPIO_P_MODEL_MODE7_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_INPUTPULL (_GPIO_P_MODEL_MODE7_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_INPUTPULLFILTER (_GPIO_P_MODEL_MODE7_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE7_PUSHPULL (_GPIO_P_MODEL_MODE7_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_PUSHPULLALT (_GPIO_P_MODEL_MODE7_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_WIREDOR (_GPIO_P_MODEL_MODE7_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE7_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE7_WIREDAND (_GPIO_P_MODEL_MODE7_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_WIREDANDFILTER (_GPIO_P_MODEL_MODE7_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE7_WIREDANDPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE7_WIREDANDALT (_GPIO_P_MODEL_MODE7_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */
+#define GPIO_P_MODEL_MODE7_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/
+#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/
+
+/* Bit fields for GPIO_P MODEH */
+#define _GPIO_P_MODEH_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MASK 0x000000FFUL /**< Mask for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */
+#define _GPIO_P_MODEH_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */
+#define _GPIO_P_MODEH_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/
+#define GPIO_P_MODEH_MODE0_DEFAULT (_GPIO_P_MODEH_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE0_DISABLED (_GPIO_P_MODEH_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE0_INPUT (_GPIO_P_MODEH_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE0_INPUTPULL (_GPIO_P_MODEH_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE0_INPUTPULLFILTER (_GPIO_P_MODEH_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/
+#define GPIO_P_MODEH_MODE0_PUSHPULL (_GPIO_P_MODEH_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE0_PUSHPULLALT (_GPIO_P_MODEH_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE0_WIREDOR (_GPIO_P_MODEH_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/
+#define GPIO_P_MODEH_MODE0_WIREDAND (_GPIO_P_MODEH_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE0_WIREDANDFILTER (_GPIO_P_MODEH_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/
+#define GPIO_P_MODEH_MODE0_WIREDANDPULLUP (_GPIO_P_MODEH_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/
+#define GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/
+#define GPIO_P_MODEH_MODE0_WIREDANDALT (_GPIO_P_MODEH_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/
+#define GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/
+#define GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/
+#define _GPIO_P_MODEH_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */
+#define _GPIO_P_MODEH_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */
+#define _GPIO_P_MODEH_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */
+#define _GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/
+#define GPIO_P_MODEH_MODE1_DEFAULT (_GPIO_P_MODEH_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE1_DISABLED (_GPIO_P_MODEH_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE1_INPUT (_GPIO_P_MODEH_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE1_INPUTPULL (_GPIO_P_MODEH_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE1_INPUTPULLFILTER (_GPIO_P_MODEH_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/
+#define GPIO_P_MODEH_MODE1_PUSHPULL (_GPIO_P_MODEH_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE1_PUSHPULLALT (_GPIO_P_MODEH_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE1_WIREDOR (_GPIO_P_MODEH_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/
+#define GPIO_P_MODEH_MODE1_WIREDAND (_GPIO_P_MODEH_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE1_WIREDANDFILTER (_GPIO_P_MODEH_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/
+#define GPIO_P_MODEH_MODE1_WIREDANDPULLUP (_GPIO_P_MODEH_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/
+#define GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/
+#define GPIO_P_MODEH_MODE1_WIREDANDALT (_GPIO_P_MODEH_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */
+#define GPIO_P_MODEH_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/
+#define GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/
+#define GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/
+
+/* Bit fields for GPIO_P DOUT */
+#define _GPIO_P_DOUT_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUT */
+#define _GPIO_P_DOUT_MASK 0x000003FFUL /**< Mask for GPIO_P_DOUT */
+#define _GPIO_P_DOUT_DOUT_SHIFT 0 /**< Shift value for GPIO_DOUT */
+#define _GPIO_P_DOUT_DOUT_MASK 0x3FFUL /**< Bit mask for GPIO_DOUT */
+#define _GPIO_P_DOUT_DOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUT */
+#define GPIO_P_DOUT_DOUT_DEFAULT (_GPIO_P_DOUT_DOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUT */
+
+/* Bit fields for GPIO_P DIN */
+#define _GPIO_P_DIN_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DIN */
+#define _GPIO_P_DIN_MASK 0x000003FFUL /**< Mask for GPIO_P_DIN */
+#define _GPIO_P_DIN_DIN_SHIFT 0 /**< Shift value for GPIO_DIN */
+#define _GPIO_P_DIN_DIN_MASK 0x3FFUL /**< Bit mask for GPIO_DIN */
+#define _GPIO_P_DIN_DIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DIN */
+#define GPIO_P_DIN_DIN_DEFAULT (_GPIO_P_DIN_DIN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DIN */
+/** @} End of group Parts */
+
+#endif /* GPIO_PORT_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_hfrco.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_hfrco.h
new file mode 100644
index 00000000..3d6633c4
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_hfrco.h
@@ -0,0 +1,226 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 HFRCO register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_HFRCO_H
+#define EFR32MG24_HFRCO_H
+#define HFRCO_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_HFRCO HFRCO
+ * @{
+ * @brief EFR32MG24 HFRCO Register Declaration.
+ *****************************************************************************/
+
+/** HFRCO Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IP Version ID */
+ __IOM uint32_t CTRL; /**< Ctrl Register */
+ __IOM uint32_t CAL; /**< Calibration Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IOM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK; /**< Lock Register */
+ uint32_t RESERVED1[1016U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP Version ID */
+ __IOM uint32_t CTRL_SET; /**< Ctrl Register */
+ __IOM uint32_t CAL_SET; /**< Calibration Register */
+ __IM uint32_t STATUS_SET; /**< Status Register */
+ __IOM uint32_t IF_SET; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
+ uint32_t RESERVED2[1U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK_SET; /**< Lock Register */
+ uint32_t RESERVED3[1016U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP Version ID */
+ __IOM uint32_t CTRL_CLR; /**< Ctrl Register */
+ __IOM uint32_t CAL_CLR; /**< Calibration Register */
+ __IM uint32_t STATUS_CLR; /**< Status Register */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
+ uint32_t RESERVED4[1U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK_CLR; /**< Lock Register */
+ uint32_t RESERVED5[1016U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP Version ID */
+ __IOM uint32_t CTRL_TGL; /**< Ctrl Register */
+ __IOM uint32_t CAL_TGL; /**< Calibration Register */
+ __IM uint32_t STATUS_TGL; /**< Status Register */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
+ uint32_t RESERVED6[1U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK_TGL; /**< Lock Register */
+} HFRCO_TypeDef;
+/** @} End of group EFR32MG24_HFRCO */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_HFRCO
+ * @{
+ * @defgroup EFR32MG24_HFRCO_BitFields HFRCO Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for HFRCO IPVERSION */
+#define _HFRCO_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for HFRCO_IPVERSION */
+#define _HFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFRCO_IPVERSION */
+#define _HFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFRCO_IPVERSION */
+#define _HFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFRCO_IPVERSION */
+#define _HFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFRCO_IPVERSION */
+#define HFRCO_IPVERSION_IPVERSION_DEFAULT (_HFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IPVERSION */
+
+/* Bit fields for HFRCO CTRL */
+#define _HFRCO_CTRL_RESETVALUE 0x00000000UL /**< Default value for HFRCO_CTRL */
+#define _HFRCO_CTRL_MASK 0x00000007UL /**< Mask for HFRCO_CTRL */
+#define HFRCO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */
+#define _HFRCO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for HFRCO_FORCEEN */
+#define _HFRCO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for HFRCO_FORCEEN */
+#define _HFRCO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */
+#define HFRCO_CTRL_FORCEEN_DEFAULT (_HFRCO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CTRL */
+#define HFRCO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-demand */
+#define _HFRCO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for HFRCO_DISONDEMAND */
+#define _HFRCO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for HFRCO_DISONDEMAND */
+#define _HFRCO_CTRL_DISONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */
+#define HFRCO_CTRL_DISONDEMAND_DEFAULT (_HFRCO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_CTRL */
+#define HFRCO_CTRL_EM23ONDEMAND (0x1UL << 2) /**< EM23 On-demand */
+#define _HFRCO_CTRL_EM23ONDEMAND_SHIFT 2 /**< Shift value for HFRCO_EM23ONDEMAND */
+#define _HFRCO_CTRL_EM23ONDEMAND_MASK 0x4UL /**< Bit mask for HFRCO_EM23ONDEMAND */
+#define _HFRCO_CTRL_EM23ONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */
+#define HFRCO_CTRL_EM23ONDEMAND_DEFAULT (_HFRCO_CTRL_EM23ONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for HFRCO_CTRL */
+
+/* Bit fields for HFRCO CAL */
+#define _HFRCO_CAL_RESETVALUE 0xA8689F7FUL /**< Default value for HFRCO_CAL */
+#define _HFRCO_CAL_MASK 0xFFFFBF7FUL /**< Mask for HFRCO_CAL */
+#define _HFRCO_CAL_TUNING_SHIFT 0 /**< Shift value for HFRCO_TUNING */
+#define _HFRCO_CAL_TUNING_MASK 0x7FUL /**< Bit mask for HFRCO_TUNING */
+#define _HFRCO_CAL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for HFRCO_CAL */
+#define HFRCO_CAL_TUNING_DEFAULT (_HFRCO_CAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CAL */
+#define _HFRCO_CAL_FINETUNING_SHIFT 8 /**< Shift value for HFRCO_FINETUNING */
+#define _HFRCO_CAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for HFRCO_FINETUNING */
+#define _HFRCO_CAL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for HFRCO_CAL */
+#define HFRCO_CAL_FINETUNING_DEFAULT (_HFRCO_CAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for HFRCO_CAL */
+#define HFRCO_CAL_LDOHP (0x1UL << 15) /**< LDO High Power Mode */
+#define _HFRCO_CAL_LDOHP_SHIFT 15 /**< Shift value for HFRCO_LDOHP */
+#define _HFRCO_CAL_LDOHP_MASK 0x8000UL /**< Bit mask for HFRCO_LDOHP */
+#define _HFRCO_CAL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFRCO_CAL */
+#define HFRCO_CAL_LDOHP_DEFAULT (_HFRCO_CAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for HFRCO_CAL */
+#define _HFRCO_CAL_FREQRANGE_SHIFT 16 /**< Shift value for HFRCO_FREQRANGE */
+#define _HFRCO_CAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for HFRCO_FREQRANGE */
+#define _HFRCO_CAL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for HFRCO_CAL */
+#define HFRCO_CAL_FREQRANGE_DEFAULT (_HFRCO_CAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_CAL */
+#define _HFRCO_CAL_CMPBIAS_SHIFT 21 /**< Shift value for HFRCO_CMPBIAS */
+#define _HFRCO_CAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for HFRCO_CMPBIAS */
+#define _HFRCO_CAL_CMPBIAS_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFRCO_CAL */
+#define HFRCO_CAL_CMPBIAS_DEFAULT (_HFRCO_CAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for HFRCO_CAL */
+#define _HFRCO_CAL_CLKDIV_SHIFT 24 /**< Shift value for HFRCO_CLKDIV */
+#define _HFRCO_CAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for HFRCO_CLKDIV */
+#define _HFRCO_CAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CAL */
+#define _HFRCO_CAL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for HFRCO_CAL */
+#define _HFRCO_CAL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for HFRCO_CAL */
+#define _HFRCO_CAL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for HFRCO_CAL */
+#define HFRCO_CAL_CLKDIV_DEFAULT (_HFRCO_CAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for HFRCO_CAL */
+#define HFRCO_CAL_CLKDIV_DIV1 (_HFRCO_CAL_CLKDIV_DIV1 << 24) /**< Shifted mode DIV1 for HFRCO_CAL */
+#define HFRCO_CAL_CLKDIV_DIV2 (_HFRCO_CAL_CLKDIV_DIV2 << 24) /**< Shifted mode DIV2 for HFRCO_CAL */
+#define HFRCO_CAL_CLKDIV_DIV4 (_HFRCO_CAL_CLKDIV_DIV4 << 24) /**< Shifted mode DIV4 for HFRCO_CAL */
+#define _HFRCO_CAL_CMPSEL_SHIFT 26 /**< Shift value for HFRCO_CMPSEL */
+#define _HFRCO_CAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for HFRCO_CMPSEL */
+#define _HFRCO_CAL_CMPSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFRCO_CAL */
+#define HFRCO_CAL_CMPSEL_DEFAULT (_HFRCO_CAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for HFRCO_CAL */
+#define _HFRCO_CAL_IREFTC_SHIFT 28 /**< Shift value for HFRCO_IREFTC */
+#define _HFRCO_CAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for HFRCO_IREFTC */
+#define _HFRCO_CAL_IREFTC_DEFAULT 0x0000000AUL /**< Mode DEFAULT for HFRCO_CAL */
+#define HFRCO_CAL_IREFTC_DEFAULT (_HFRCO_CAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for HFRCO_CAL */
+
+/* Bit fields for HFRCO STATUS */
+#define _HFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFRCO_STATUS */
+#define _HFRCO_STATUS_MASK 0x80010007UL /**< Mask for HFRCO_STATUS */
+#define HFRCO_STATUS_RDY (0x1UL << 0) /**< Ready */
+#define _HFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */
+#define _HFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */
+#define _HFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */
+#define HFRCO_STATUS_RDY_DEFAULT (_HFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_STATUS */
+#define HFRCO_STATUS_FREQBSY (0x1UL << 1) /**< Frequency Updating Busy */
+#define _HFRCO_STATUS_FREQBSY_SHIFT 1 /**< Shift value for HFRCO_FREQBSY */
+#define _HFRCO_STATUS_FREQBSY_MASK 0x2UL /**< Bit mask for HFRCO_FREQBSY */
+#define _HFRCO_STATUS_FREQBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */
+#define HFRCO_STATUS_FREQBSY_DEFAULT (_HFRCO_STATUS_FREQBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_STATUS */
+#define HFRCO_STATUS_SYNCBUSY (0x1UL << 2) /**< Synchronization Busy */
+#define _HFRCO_STATUS_SYNCBUSY_SHIFT 2 /**< Shift value for HFRCO_SYNCBUSY */
+#define _HFRCO_STATUS_SYNCBUSY_MASK 0x4UL /**< Bit mask for HFRCO_SYNCBUSY */
+#define _HFRCO_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */
+#define HFRCO_STATUS_SYNCBUSY_DEFAULT (_HFRCO_STATUS_SYNCBUSY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFRCO_STATUS */
+#define HFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */
+#define _HFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for HFRCO_ENS */
+#define _HFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFRCO_ENS */
+#define _HFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */
+#define HFRCO_STATUS_ENS_DEFAULT (_HFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_STATUS */
+#define HFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */
+#define _HFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFRCO_LOCK */
+#define _HFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFRCO_LOCK */
+#define _HFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */
+#define _HFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFRCO_STATUS */
+#define _HFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFRCO_STATUS */
+#define HFRCO_STATUS_LOCK_DEFAULT (_HFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFRCO_STATUS */
+#define HFRCO_STATUS_LOCK_UNLOCKED (_HFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFRCO_STATUS */
+#define HFRCO_STATUS_LOCK_LOCKED (_HFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFRCO_STATUS */
+
+/* Bit fields for HFRCO IF */
+#define _HFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IF */
+#define _HFRCO_IF_MASK 0x00000001UL /**< Mask for HFRCO_IF */
+#define HFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */
+#define _HFRCO_IF_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */
+#define _HFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */
+#define _HFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IF */
+#define HFRCO_IF_RDY_DEFAULT (_HFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IF */
+
+/* Bit fields for HFRCO IEN */
+#define _HFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IEN */
+#define _HFRCO_IEN_MASK 0x00000001UL /**< Mask for HFRCO_IEN */
+#define HFRCO_IEN_RDY (0x1UL << 0) /**< RDY Interrupt Enable */
+#define _HFRCO_IEN_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */
+#define _HFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */
+#define _HFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IEN */
+#define HFRCO_IEN_RDY_DEFAULT (_HFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IEN */
+
+/* Bit fields for HFRCO LOCK */
+#define _HFRCO_LOCK_RESETVALUE 0x00008195UL /**< Default value for HFRCO_LOCK */
+#define _HFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFRCO_LOCK */
+#define _HFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFRCO_LOCKKEY */
+#define _HFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFRCO_LOCKKEY */
+#define _HFRCO_LOCK_LOCKKEY_DEFAULT 0x00008195UL /**< Mode DEFAULT for HFRCO_LOCK */
+#define _HFRCO_LOCK_LOCKKEY_UNLOCK 0x00008195UL /**< Mode UNLOCK for HFRCO_LOCK */
+#define HFRCO_LOCK_LOCKKEY_DEFAULT (_HFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_LOCK */
+#define HFRCO_LOCK_LOCKKEY_UNLOCK (_HFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFRCO_LOCK */
+
+/** @} End of group EFR32MG24_HFRCO_BitFields */
+/** @} End of group EFR32MG24_HFRCO */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_HFRCO_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_hfxo.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_hfxo.h
new file mode 100644
index 00000000..7be02825
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_hfxo.h
@@ -0,0 +1,801 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 HFXO register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_HFXO_H
+#define EFR32MG24_HFXO_H
+#define HFXO_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_HFXO HFXO
+ * @{
+ * @brief EFR32MG24 HFXO Register Declaration.
+ *****************************************************************************/
+
+/** HFXO Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IP version ID */
+ uint32_t RESERVED0[3U]; /**< Reserved for future use */
+ __IOM uint32_t XTALCFG; /**< Crystal Configuration Register */
+ uint32_t RESERVED1[1U]; /**< Reserved for future use */
+ __IOM uint32_t XTALCTRL; /**< Crystal Control Register */
+ __IOM uint32_t XTALCTRL1; /**< BUFOUT Crystal Control Register */
+ __IOM uint32_t CFG; /**< Configuration Register */
+ uint32_t RESERVED2[1U]; /**< Reserved for future use */
+ __IOM uint32_t CTRL; /**< Control Register */
+ uint32_t RESERVED3[5U]; /**< Reserved for future use */
+ __IOM uint32_t BUFOUTTRIM; /**< BUFOUT Trim Configuration Register */
+ __IOM uint32_t BUFOUTCTRL; /**< BUFOUT Control Register */
+ uint32_t RESERVED4[2U]; /**< Reserved for future use */
+ __IOM uint32_t CMD; /**< Command Register */
+ uint32_t RESERVED5[1U]; /**< Reserved for future use */
+ __IM uint32_t STATUS; /**< Status Register */
+ uint32_t RESERVED6[5U]; /**< Reserved for future use */
+ __IOM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ uint32_t RESERVED7[2U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK; /**< Configuration Lock Register */
+ uint32_t RESERVED8[991U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP version ID */
+ uint32_t RESERVED9[3U]; /**< Reserved for future use */
+ __IOM uint32_t XTALCFG_SET; /**< Crystal Configuration Register */
+ uint32_t RESERVED10[1U]; /**< Reserved for future use */
+ __IOM uint32_t XTALCTRL_SET; /**< Crystal Control Register */
+ __IOM uint32_t XTALCTRL1_SET; /**< BUFOUT Crystal Control Register */
+ __IOM uint32_t CFG_SET; /**< Configuration Register */
+ uint32_t RESERVED11[1U]; /**< Reserved for future use */
+ __IOM uint32_t CTRL_SET; /**< Control Register */
+ uint32_t RESERVED12[5U]; /**< Reserved for future use */
+ __IOM uint32_t BUFOUTTRIM_SET; /**< BUFOUT Trim Configuration Register */
+ __IOM uint32_t BUFOUTCTRL_SET; /**< BUFOUT Control Register */
+ uint32_t RESERVED13[2U]; /**< Reserved for future use */
+ __IOM uint32_t CMD_SET; /**< Command Register */
+ uint32_t RESERVED14[1U]; /**< Reserved for future use */
+ __IM uint32_t STATUS_SET; /**< Status Register */
+ uint32_t RESERVED15[5U]; /**< Reserved for future use */
+ __IOM uint32_t IF_SET; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
+ uint32_t RESERVED16[2U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */
+ uint32_t RESERVED17[991U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP version ID */
+ uint32_t RESERVED18[3U]; /**< Reserved for future use */
+ __IOM uint32_t XTALCFG_CLR; /**< Crystal Configuration Register */
+ uint32_t RESERVED19[1U]; /**< Reserved for future use */
+ __IOM uint32_t XTALCTRL_CLR; /**< Crystal Control Register */
+ __IOM uint32_t XTALCTRL1_CLR; /**< BUFOUT Crystal Control Register */
+ __IOM uint32_t CFG_CLR; /**< Configuration Register */
+ uint32_t RESERVED20[1U]; /**< Reserved for future use */
+ __IOM uint32_t CTRL_CLR; /**< Control Register */
+ uint32_t RESERVED21[5U]; /**< Reserved for future use */
+ __IOM uint32_t BUFOUTTRIM_CLR; /**< BUFOUT Trim Configuration Register */
+ __IOM uint32_t BUFOUTCTRL_CLR; /**< BUFOUT Control Register */
+ uint32_t RESERVED22[2U]; /**< Reserved for future use */
+ __IOM uint32_t CMD_CLR; /**< Command Register */
+ uint32_t RESERVED23[1U]; /**< Reserved for future use */
+ __IM uint32_t STATUS_CLR; /**< Status Register */
+ uint32_t RESERVED24[5U]; /**< Reserved for future use */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
+ uint32_t RESERVED25[2U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */
+ uint32_t RESERVED26[991U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP version ID */
+ uint32_t RESERVED27[3U]; /**< Reserved for future use */
+ __IOM uint32_t XTALCFG_TGL; /**< Crystal Configuration Register */
+ uint32_t RESERVED28[1U]; /**< Reserved for future use */
+ __IOM uint32_t XTALCTRL_TGL; /**< Crystal Control Register */
+ __IOM uint32_t XTALCTRL1_TGL; /**< BUFOUT Crystal Control Register */
+ __IOM uint32_t CFG_TGL; /**< Configuration Register */
+ uint32_t RESERVED29[1U]; /**< Reserved for future use */
+ __IOM uint32_t CTRL_TGL; /**< Control Register */
+ uint32_t RESERVED30[5U]; /**< Reserved for future use */
+ __IOM uint32_t BUFOUTTRIM_TGL; /**< BUFOUT Trim Configuration Register */
+ __IOM uint32_t BUFOUTCTRL_TGL; /**< BUFOUT Control Register */
+ uint32_t RESERVED31[2U]; /**< Reserved for future use */
+ __IOM uint32_t CMD_TGL; /**< Command Register */
+ uint32_t RESERVED32[1U]; /**< Reserved for future use */
+ __IM uint32_t STATUS_TGL; /**< Status Register */
+ uint32_t RESERVED33[5U]; /**< Reserved for future use */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
+ uint32_t RESERVED34[2U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */
+} HFXO_TypeDef;
+/** @} End of group EFR32MG24_HFXO */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_HFXO
+ * @{
+ * @defgroup EFR32MG24_HFXO_BitFields HFXO Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for HFXO IPVERSION */
+#define _HFXO_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for HFXO_IPVERSION */
+#define _HFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFXO_IPVERSION */
+#define _HFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFXO_IPVERSION */
+#define _HFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFXO_IPVERSION */
+#define _HFXO_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_IPVERSION */
+#define HFXO_IPVERSION_IPVERSION_DEFAULT (_HFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IPVERSION */
+
+/* Bit fields for HFXO XTALCFG */
+#define _HFXO_XTALCFG_RESETVALUE 0x0BB00820UL /**< Default value for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_MASK 0x0FFFFFFFUL /**< Mask for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT 0 /**< Shift value for HFXO_COREBIASSTARTUPI */
+#define _HFXO_XTALCFG_COREBIASSTARTUPI_MASK 0x3FUL /**< Bit mask for HFXO_COREBIASSTARTUPI */
+#define _HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT 0x00000020UL /**< Mode DEFAULT for HFXO_XTALCFG */
+#define HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT 6 /**< Shift value for HFXO_COREBIASSTARTUP */
+#define _HFXO_XTALCFG_COREBIASSTARTUP_MASK 0xFC0UL /**< Bit mask for HFXO_COREBIASSTARTUP */
+#define _HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT 0x00000020UL /**< Mode DEFAULT for HFXO_XTALCFG */
+#define HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT << 6) /**< Shifted mode DEFAULT for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_CTUNEXISTARTUP_SHIFT 12 /**< Shift value for HFXO_CTUNEXISTARTUP */
+#define _HFXO_XTALCFG_CTUNEXISTARTUP_MASK 0xF000UL /**< Bit mask for HFXO_CTUNEXISTARTUP */
+#define _HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCFG */
+#define HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_CTUNEXOSTARTUP_SHIFT 16 /**< Shift value for HFXO_CTUNEXOSTARTUP */
+#define _HFXO_XTALCFG_CTUNEXOSTARTUP_MASK 0xF0000UL /**< Bit mask for HFXO_CTUNEXOSTARTUP */
+#define _HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCFG */
+#define HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT 20 /**< Shift value for HFXO_TIMEOUTSTEADY */
+#define _HFXO_XTALCFG_TIMEOUTSTEADY_MASK 0xF00000UL /**< Bit mask for HFXO_TIMEOUTSTEADY */
+#define _HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT 0x0000000BUL /**< Mode DEFAULT for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTSTEADY_T4US 0x00000000UL /**< Mode T4US for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTSTEADY_T16US 0x00000001UL /**< Mode T16US for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTSTEADY_T41US 0x00000002UL /**< Mode T41US for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTSTEADY_T83US 0x00000003UL /**< Mode T83US for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTSTEADY_T125US 0x00000004UL /**< Mode T125US for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTSTEADY_T166US 0x00000005UL /**< Mode T166US for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTSTEADY_T208US 0x00000006UL /**< Mode T208US for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTSTEADY_T250US 0x00000007UL /**< Mode T250US for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTSTEADY_T333US 0x00000008UL /**< Mode T333US for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTSTEADY_T416US 0x00000009UL /**< Mode T416US for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTSTEADY_T500US 0x0000000AUL /**< Mode T500US for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTSTEADY_T666US 0x0000000BUL /**< Mode T666US for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTSTEADY_T833US 0x0000000CUL /**< Mode T833US for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTSTEADY_T1666US 0x0000000DUL /**< Mode T1666US for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTSTEADY_T2500US 0x0000000EUL /**< Mode T2500US for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTSTEADY_T4166US 0x0000000FUL /**< Mode T4166US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT (_HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTSTEADY_T4US (_HFXO_XTALCFG_TIMEOUTSTEADY_T4US << 20) /**< Shifted mode T4US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTSTEADY_T16US (_HFXO_XTALCFG_TIMEOUTSTEADY_T16US << 20) /**< Shifted mode T16US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTSTEADY_T41US (_HFXO_XTALCFG_TIMEOUTSTEADY_T41US << 20) /**< Shifted mode T41US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTSTEADY_T83US (_HFXO_XTALCFG_TIMEOUTSTEADY_T83US << 20) /**< Shifted mode T83US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTSTEADY_T125US (_HFXO_XTALCFG_TIMEOUTSTEADY_T125US << 20) /**< Shifted mode T125US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTSTEADY_T166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T166US << 20) /**< Shifted mode T166US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTSTEADY_T208US (_HFXO_XTALCFG_TIMEOUTSTEADY_T208US << 20) /**< Shifted mode T208US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTSTEADY_T250US (_HFXO_XTALCFG_TIMEOUTSTEADY_T250US << 20) /**< Shifted mode T250US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTSTEADY_T333US (_HFXO_XTALCFG_TIMEOUTSTEADY_T333US << 20) /**< Shifted mode T333US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTSTEADY_T416US (_HFXO_XTALCFG_TIMEOUTSTEADY_T416US << 20) /**< Shifted mode T416US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTSTEADY_T500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T500US << 20) /**< Shifted mode T500US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTSTEADY_T666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T666US << 20) /**< Shifted mode T666US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTSTEADY_T833US (_HFXO_XTALCFG_TIMEOUTSTEADY_T833US << 20) /**< Shifted mode T833US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTSTEADY_T1666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T1666US << 20) /**< Shifted mode T1666US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTSTEADY_T2500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T2500US << 20) /**< Shifted mode T2500US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTSTEADY_T4166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T4166US << 20) /**< Shifted mode T4166US for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTCBLSB_SHIFT 24 /**< Shift value for HFXO_TIMEOUTCBLSB */
+#define _HFXO_XTALCFG_TIMEOUTCBLSB_MASK 0xF000000UL /**< Bit mask for HFXO_TIMEOUTCBLSB */
+#define _HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT 0x0000000BUL /**< Mode DEFAULT for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTCBLSB_T8US 0x00000000UL /**< Mode T8US for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTCBLSB_T20US 0x00000001UL /**< Mode T20US for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTCBLSB_T41US 0x00000002UL /**< Mode T41US for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTCBLSB_T62US 0x00000003UL /**< Mode T62US for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTCBLSB_T83US 0x00000004UL /**< Mode T83US for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTCBLSB_T104US 0x00000005UL /**< Mode T104US for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTCBLSB_T125US 0x00000006UL /**< Mode T125US for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTCBLSB_T166US 0x00000007UL /**< Mode T166US for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTCBLSB_T208US 0x00000008UL /**< Mode T208US for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTCBLSB_T250US 0x00000009UL /**< Mode T250US for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTCBLSB_T333US 0x0000000AUL /**< Mode T333US for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTCBLSB_T416US 0x0000000BUL /**< Mode T416US for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTCBLSB_T833US 0x0000000CUL /**< Mode T833US for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTCBLSB_T1250US 0x0000000DUL /**< Mode T1250US for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTCBLSB_T2083US 0x0000000EUL /**< Mode T2083US for HFXO_XTALCFG */
+#define _HFXO_XTALCFG_TIMEOUTCBLSB_T3750US 0x0000000FUL /**< Mode T3750US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT (_HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTCBLSB_T8US (_HFXO_XTALCFG_TIMEOUTCBLSB_T8US << 24) /**< Shifted mode T8US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTCBLSB_T20US (_HFXO_XTALCFG_TIMEOUTCBLSB_T20US << 24) /**< Shifted mode T20US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTCBLSB_T41US (_HFXO_XTALCFG_TIMEOUTCBLSB_T41US << 24) /**< Shifted mode T41US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTCBLSB_T62US (_HFXO_XTALCFG_TIMEOUTCBLSB_T62US << 24) /**< Shifted mode T62US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTCBLSB_T83US (_HFXO_XTALCFG_TIMEOUTCBLSB_T83US << 24) /**< Shifted mode T83US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTCBLSB_T104US (_HFXO_XTALCFG_TIMEOUTCBLSB_T104US << 24) /**< Shifted mode T104US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTCBLSB_T125US (_HFXO_XTALCFG_TIMEOUTCBLSB_T125US << 24) /**< Shifted mode T125US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTCBLSB_T166US (_HFXO_XTALCFG_TIMEOUTCBLSB_T166US << 24) /**< Shifted mode T166US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTCBLSB_T208US (_HFXO_XTALCFG_TIMEOUTCBLSB_T208US << 24) /**< Shifted mode T208US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTCBLSB_T250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T250US << 24) /**< Shifted mode T250US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTCBLSB_T333US (_HFXO_XTALCFG_TIMEOUTCBLSB_T333US << 24) /**< Shifted mode T333US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTCBLSB_T416US (_HFXO_XTALCFG_TIMEOUTCBLSB_T416US << 24) /**< Shifted mode T416US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTCBLSB_T833US (_HFXO_XTALCFG_TIMEOUTCBLSB_T833US << 24) /**< Shifted mode T833US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTCBLSB_T1250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T1250US << 24) /**< Shifted mode T1250US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTCBLSB_T2083US (_HFXO_XTALCFG_TIMEOUTCBLSB_T2083US << 24) /**< Shifted mode T2083US for HFXO_XTALCFG */
+#define HFXO_XTALCFG_TIMEOUTCBLSB_T3750US (_HFXO_XTALCFG_TIMEOUTCBLSB_T3750US << 24) /**< Shifted mode T3750US for HFXO_XTALCFG */
+
+/* Bit fields for HFXO XTALCTRL */
+#define _HFXO_XTALCTRL_RESETVALUE 0x033C3C3CUL /**< Default value for HFXO_XTALCTRL */
+#define _HFXO_XTALCTRL_MASK 0x8FFFFFFFUL /**< Mask for HFXO_XTALCTRL */
+#define _HFXO_XTALCTRL_COREBIASANA_SHIFT 0 /**< Shift value for HFXO_COREBIASANA */
+#define _HFXO_XTALCTRL_COREBIASANA_MASK 0xFFUL /**< Bit mask for HFXO_COREBIASANA */
+#define _HFXO_XTALCTRL_COREBIASANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */
+#define HFXO_XTALCTRL_COREBIASANA_DEFAULT (_HFXO_XTALCTRL_COREBIASANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */
+#define _HFXO_XTALCTRL_CTUNEXIANA_SHIFT 8 /**< Shift value for HFXO_CTUNEXIANA */
+#define _HFXO_XTALCTRL_CTUNEXIANA_MASK 0xFF00UL /**< Bit mask for HFXO_CTUNEXIANA */
+#define _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */
+#define HFXO_XTALCTRL_CTUNEXIANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXIANA_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */
+#define _HFXO_XTALCTRL_CTUNEXOANA_SHIFT 16 /**< Shift value for HFXO_CTUNEXOANA */
+#define _HFXO_XTALCTRL_CTUNEXOANA_MASK 0xFF0000UL /**< Bit mask for HFXO_CTUNEXOANA */
+#define _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */
+#define HFXO_XTALCTRL_CTUNEXOANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXOANA_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */
+#define _HFXO_XTALCTRL_CTUNEFIXANA_SHIFT 24 /**< Shift value for HFXO_CTUNEFIXANA */
+#define _HFXO_XTALCTRL_CTUNEFIXANA_MASK 0x3000000UL /**< Bit mask for HFXO_CTUNEFIXANA */
+#define _HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_XTALCTRL */
+#define _HFXO_XTALCTRL_CTUNEFIXANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */
+#define _HFXO_XTALCTRL_CTUNEFIXANA_XI 0x00000001UL /**< Mode XI for HFXO_XTALCTRL */
+#define _HFXO_XTALCTRL_CTUNEFIXANA_XO 0x00000002UL /**< Mode XO for HFXO_XTALCTRL */
+#define _HFXO_XTALCTRL_CTUNEFIXANA_BOTH 0x00000003UL /**< Mode BOTH for HFXO_XTALCTRL */
+#define HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT (_HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */
+#define HFXO_XTALCTRL_CTUNEFIXANA_NONE (_HFXO_XTALCTRL_CTUNEFIXANA_NONE << 24) /**< Shifted mode NONE for HFXO_XTALCTRL */
+#define HFXO_XTALCTRL_CTUNEFIXANA_XI (_HFXO_XTALCTRL_CTUNEFIXANA_XI << 24) /**< Shifted mode XI for HFXO_XTALCTRL */
+#define HFXO_XTALCTRL_CTUNEFIXANA_XO (_HFXO_XTALCTRL_CTUNEFIXANA_XO << 24) /**< Shifted mode XO for HFXO_XTALCTRL */
+#define HFXO_XTALCTRL_CTUNEFIXANA_BOTH (_HFXO_XTALCTRL_CTUNEFIXANA_BOTH << 24) /**< Shifted mode BOTH for HFXO_XTALCTRL */
+#define _HFXO_XTALCTRL_COREDGENANA_SHIFT 26 /**< Shift value for HFXO_COREDGENANA */
+#define _HFXO_XTALCTRL_COREDGENANA_MASK 0xC000000UL /**< Bit mask for HFXO_COREDGENANA */
+#define _HFXO_XTALCTRL_COREDGENANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCTRL */
+#define _HFXO_XTALCTRL_COREDGENANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */
+#define _HFXO_XTALCTRL_COREDGENANA_DGEN33 0x00000001UL /**< Mode DGEN33 for HFXO_XTALCTRL */
+#define _HFXO_XTALCTRL_COREDGENANA_DGEN50 0x00000002UL /**< Mode DGEN50 for HFXO_XTALCTRL */
+#define _HFXO_XTALCTRL_COREDGENANA_DGEN100 0x00000003UL /**< Mode DGEN100 for HFXO_XTALCTRL */
+#define HFXO_XTALCTRL_COREDGENANA_DEFAULT (_HFXO_XTALCTRL_COREDGENANA_DEFAULT << 26) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */
+#define HFXO_XTALCTRL_COREDGENANA_NONE (_HFXO_XTALCTRL_COREDGENANA_NONE << 26) /**< Shifted mode NONE for HFXO_XTALCTRL */
+#define HFXO_XTALCTRL_COREDGENANA_DGEN33 (_HFXO_XTALCTRL_COREDGENANA_DGEN33 << 26) /**< Shifted mode DGEN33 for HFXO_XTALCTRL */
+#define HFXO_XTALCTRL_COREDGENANA_DGEN50 (_HFXO_XTALCTRL_COREDGENANA_DGEN50 << 26) /**< Shifted mode DGEN50 for HFXO_XTALCTRL */
+#define HFXO_XTALCTRL_COREDGENANA_DGEN100 (_HFXO_XTALCTRL_COREDGENANA_DGEN100 << 26) /**< Shifted mode DGEN100 for HFXO_XTALCTRL */
+#define HFXO_XTALCTRL_SKIPCOREBIASOPT (0x1UL << 31) /**< Skip Core Bias Optimization */
+#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_SHIFT 31 /**< Shift value for HFXO_SKIPCOREBIASOPT */
+#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_MASK 0x80000000UL /**< Bit mask for HFXO_SKIPCOREBIASOPT */
+#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCTRL */
+#define HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT (_HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */
+
+/* Bit fields for HFXO XTALCTRL1 */
+#define _HFXO_XTALCTRL1_RESETVALUE 0x0000003CUL /**< Default value for HFXO_XTALCTRL1 */
+#define _HFXO_XTALCTRL1_MASK 0x000000FFUL /**< Mask for HFXO_XTALCTRL1 */
+#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_SHIFT 0 /**< Shift value for HFXO_CTUNEXIBUFOUTANA */
+#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_MASK 0xFFUL /**< Bit mask for HFXO_CTUNEXIBUFOUTANA */
+#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL1 */
+#define HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT (_HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCTRL1 */
+
+/* Bit fields for HFXO CFG */
+#define _HFXO_CFG_RESETVALUE 0x10000000UL /**< Default value for HFXO_CFG */
+#define _HFXO_CFG_MASK 0xB000000FUL /**< Mask for HFXO_CFG */
+#define _HFXO_CFG_MODE_SHIFT 0 /**< Shift value for HFXO_MODE */
+#define _HFXO_CFG_MODE_MASK 0x3UL /**< Bit mask for HFXO_MODE */
+#define _HFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */
+#define _HFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for HFXO_CFG */
+#define _HFXO_CFG_MODE_EXTCLK 0x00000001UL /**< Mode EXTCLK for HFXO_CFG */
+#define _HFXO_CFG_MODE_EXTCLKPKDET 0x00000002UL /**< Mode EXTCLKPKDET for HFXO_CFG */
+#define HFXO_CFG_MODE_DEFAULT (_HFXO_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CFG */
+#define HFXO_CFG_MODE_XTAL (_HFXO_CFG_MODE_XTAL << 0) /**< Shifted mode XTAL for HFXO_CFG */
+#define HFXO_CFG_MODE_EXTCLK (_HFXO_CFG_MODE_EXTCLK << 0) /**< Shifted mode EXTCLK for HFXO_CFG */
+#define HFXO_CFG_MODE_EXTCLKPKDET (_HFXO_CFG_MODE_EXTCLKPKDET << 0) /**< Shifted mode EXTCLKPKDET for HFXO_CFG */
+#define HFXO_CFG_ENXIDCBIASANA (0x1UL << 2) /**< Enable XI Internal DC Bias */
+#define _HFXO_CFG_ENXIDCBIASANA_SHIFT 2 /**< Shift value for HFXO_ENXIDCBIASANA */
+#define _HFXO_CFG_ENXIDCBIASANA_MASK 0x4UL /**< Bit mask for HFXO_ENXIDCBIASANA */
+#define _HFXO_CFG_ENXIDCBIASANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */
+#define HFXO_CFG_ENXIDCBIASANA_DEFAULT (_HFXO_CFG_ENXIDCBIASANA_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CFG */
+#define HFXO_CFG_SQBUFSCHTRGANA (0x1UL << 3) /**< Squaring Buffer Schmitt Trigger */
+#define _HFXO_CFG_SQBUFSCHTRGANA_SHIFT 3 /**< Shift value for HFXO_SQBUFSCHTRGANA */
+#define _HFXO_CFG_SQBUFSCHTRGANA_MASK 0x8UL /**< Bit mask for HFXO_SQBUFSCHTRGANA */
+#define _HFXO_CFG_SQBUFSCHTRGANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */
+#define _HFXO_CFG_SQBUFSCHTRGANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CFG */
+#define _HFXO_CFG_SQBUFSCHTRGANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CFG */
+#define HFXO_CFG_SQBUFSCHTRGANA_DEFAULT (_HFXO_CFG_SQBUFSCHTRGANA_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_CFG */
+#define HFXO_CFG_SQBUFSCHTRGANA_DISABLE (_HFXO_CFG_SQBUFSCHTRGANA_DISABLE << 3) /**< Shifted mode DISABLE for HFXO_CFG */
+#define HFXO_CFG_SQBUFSCHTRGANA_ENABLE (_HFXO_CFG_SQBUFSCHTRGANA_ENABLE << 3) /**< Shifted mode ENABLE for HFXO_CFG */
+#define HFXO_CFG_FORCELFTIMEOUT (0x1UL << 28) /**< Force Low Frequency Timeout */
+#define _HFXO_CFG_FORCELFTIMEOUT_SHIFT 28 /**< Shift value for HFXO_FORCELFTIMEOUT */
+#define _HFXO_CFG_FORCELFTIMEOUT_MASK 0x10000000UL /**< Bit mask for HFXO_FORCELFTIMEOUT */
+#define _HFXO_CFG_FORCELFTIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CFG */
+#define HFXO_CFG_FORCELFTIMEOUT_DEFAULT (_HFXO_CFG_FORCELFTIMEOUT_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_CFG */
+
+/* Bit fields for HFXO CTRL */
+#define _HFXO_CTRL_RESETVALUE 0x07000040UL /**< Default value for HFXO_CTRL */
+#define _HFXO_CTRL_MASK 0x8707FF7DUL /**< Mask for HFXO_CTRL */
+#define HFXO_CTRL_BUFOUTFREEZE (0x1UL << 0) /**< Freeze BUFOUT Controls */
+#define _HFXO_CTRL_BUFOUTFREEZE_SHIFT 0 /**< Shift value for HFXO_BUFOUTFREEZE */
+#define _HFXO_CTRL_BUFOUTFREEZE_MASK 0x1UL /**< Bit mask for HFXO_BUFOUTFREEZE */
+#define _HFXO_CTRL_BUFOUTFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */
+#define HFXO_CTRL_BUFOUTFREEZE_DEFAULT (_HFXO_CTRL_BUFOUTFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CTRL */
+#define HFXO_CTRL_KEEPWARM (0x1UL << 2) /**< Keep Warm */
+#define _HFXO_CTRL_KEEPWARM_SHIFT 2 /**< Shift value for HFXO_KEEPWARM */
+#define _HFXO_CTRL_KEEPWARM_MASK 0x4UL /**< Bit mask for HFXO_KEEPWARM */
+#define _HFXO_CTRL_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */
+#define HFXO_CTRL_KEEPWARM_DEFAULT (_HFXO_CTRL_KEEPWARM_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CTRL */
+#define HFXO_CTRL_EM23ONDEMAND (0x1UL << 3) /**< On-demand During EM23 */
+#define _HFXO_CTRL_EM23ONDEMAND_SHIFT 3 /**< Shift value for HFXO_EM23ONDEMAND */
+#define _HFXO_CTRL_EM23ONDEMAND_MASK 0x8UL /**< Bit mask for HFXO_EM23ONDEMAND */
+#define _HFXO_CTRL_EM23ONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */
+#define HFXO_CTRL_EM23ONDEMAND_DEFAULT (_HFXO_CTRL_EM23ONDEMAND_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_CTRL */
+#define HFXO_CTRL_FORCEXI2GNDANA (0x1UL << 4) /**< Force XI Pin to Ground */
+#define _HFXO_CTRL_FORCEXI2GNDANA_SHIFT 4 /**< Shift value for HFXO_FORCEXI2GNDANA */
+#define _HFXO_CTRL_FORCEXI2GNDANA_MASK 0x10UL /**< Bit mask for HFXO_FORCEXI2GNDANA */
+#define _HFXO_CTRL_FORCEXI2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */
+#define _HFXO_CTRL_FORCEXI2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */
+#define _HFXO_CTRL_FORCEXI2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */
+#define HFXO_CTRL_FORCEXI2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXI2GNDANA_DEFAULT << 4) /**< Shifted mode DEFAULT for HFXO_CTRL */
+#define HFXO_CTRL_FORCEXI2GNDANA_DISABLE (_HFXO_CTRL_FORCEXI2GNDANA_DISABLE << 4) /**< Shifted mode DISABLE for HFXO_CTRL */
+#define HFXO_CTRL_FORCEXI2GNDANA_ENABLE (_HFXO_CTRL_FORCEXI2GNDANA_ENABLE << 4) /**< Shifted mode ENABLE for HFXO_CTRL */
+#define HFXO_CTRL_FORCEXO2GNDANA (0x1UL << 5) /**< Force XO Pin to Ground */
+#define _HFXO_CTRL_FORCEXO2GNDANA_SHIFT 5 /**< Shift value for HFXO_FORCEXO2GNDANA */
+#define _HFXO_CTRL_FORCEXO2GNDANA_MASK 0x20UL /**< Bit mask for HFXO_FORCEXO2GNDANA */
+#define _HFXO_CTRL_FORCEXO2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */
+#define _HFXO_CTRL_FORCEXO2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */
+#define _HFXO_CTRL_FORCEXO2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */
+#define HFXO_CTRL_FORCEXO2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXO2GNDANA_DEFAULT << 5) /**< Shifted mode DEFAULT for HFXO_CTRL */
+#define HFXO_CTRL_FORCEXO2GNDANA_DISABLE (_HFXO_CTRL_FORCEXO2GNDANA_DISABLE << 5) /**< Shifted mode DISABLE for HFXO_CTRL */
+#define HFXO_CTRL_FORCEXO2GNDANA_ENABLE (_HFXO_CTRL_FORCEXO2GNDANA_ENABLE << 5) /**< Shifted mode ENABLE for HFXO_CTRL */
+#define HFXO_CTRL_FORCECTUNEMAX (0x1UL << 6) /**< Force Tuning Cap to Max Value */
+#define _HFXO_CTRL_FORCECTUNEMAX_SHIFT 6 /**< Shift value for HFXO_FORCECTUNEMAX */
+#define _HFXO_CTRL_FORCECTUNEMAX_MASK 0x40UL /**< Bit mask for HFXO_FORCECTUNEMAX */
+#define _HFXO_CTRL_FORCECTUNEMAX_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */
+#define HFXO_CTRL_FORCECTUNEMAX_DEFAULT (_HFXO_CTRL_FORCECTUNEMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for HFXO_CTRL */
+#define _HFXO_CTRL_PRSSTATUSSEL0_SHIFT 8 /**< Shift value for HFXO_PRSSTATUSSEL0 */
+#define _HFXO_CTRL_PRSSTATUSSEL0_MASK 0xF00UL /**< Bit mask for HFXO_PRSSTATUSSEL0 */
+#define _HFXO_CTRL_PRSSTATUSSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */
+#define _HFXO_CTRL_PRSSTATUSSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for HFXO_CTRL */
+#define _HFXO_CTRL_PRSSTATUSSEL0_ENS 0x00000001UL /**< Mode ENS for HFXO_CTRL */
+#define _HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY 0x00000002UL /**< Mode COREBIASOPTRDY for HFXO_CTRL */
+#define _HFXO_CTRL_PRSSTATUSSEL0_RDY 0x00000003UL /**< Mode RDY for HFXO_CTRL */
+#define _HFXO_CTRL_PRSSTATUSSEL0_PRSRDY 0x00000004UL /**< Mode PRSRDY for HFXO_CTRL */
+#define _HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY 0x00000005UL /**< Mode BUFOUTRDY for HFXO_CTRL */
+#define _HFXO_CTRL_PRSSTATUSSEL0_HWREQ 0x00000008UL /**< Mode HWREQ for HFXO_CTRL */
+#define _HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ 0x00000009UL /**< Mode PRSHWREQ for HFXO_CTRL */
+#define _HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ 0x0000000AUL /**< Mode BUFOUTHWREQ for HFXO_CTRL */
+#define HFXO_CTRL_PRSSTATUSSEL0_DEFAULT (_HFXO_CTRL_PRSSTATUSSEL0_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_CTRL */
+#define HFXO_CTRL_PRSSTATUSSEL0_DISABLED (_HFXO_CTRL_PRSSTATUSSEL0_DISABLED << 8) /**< Shifted mode DISABLED for HFXO_CTRL */
+#define HFXO_CTRL_PRSSTATUSSEL0_ENS (_HFXO_CTRL_PRSSTATUSSEL0_ENS << 8) /**< Shifted mode ENS for HFXO_CTRL */
+#define HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY (_HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY << 8) /**< Shifted mode COREBIASOPTRDY for HFXO_CTRL */
+#define HFXO_CTRL_PRSSTATUSSEL0_RDY (_HFXO_CTRL_PRSSTATUSSEL0_RDY << 8) /**< Shifted mode RDY for HFXO_CTRL */
+#define HFXO_CTRL_PRSSTATUSSEL0_PRSRDY (_HFXO_CTRL_PRSSTATUSSEL0_PRSRDY << 8) /**< Shifted mode PRSRDY for HFXO_CTRL */
+#define HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY (_HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY << 8) /**< Shifted mode BUFOUTRDY for HFXO_CTRL */
+#define HFXO_CTRL_PRSSTATUSSEL0_HWREQ (_HFXO_CTRL_PRSSTATUSSEL0_HWREQ << 8) /**< Shifted mode HWREQ for HFXO_CTRL */
+#define HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ (_HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ << 8) /**< Shifted mode PRSHWREQ for HFXO_CTRL */
+#define HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ (_HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ << 8) /**< Shifted mode BUFOUTHWREQ for HFXO_CTRL */
+#define _HFXO_CTRL_PRSSTATUSSEL1_SHIFT 12 /**< Shift value for HFXO_PRSSTATUSSEL1 */
+#define _HFXO_CTRL_PRSSTATUSSEL1_MASK 0xF000UL /**< Bit mask for HFXO_PRSSTATUSSEL1 */
+#define _HFXO_CTRL_PRSSTATUSSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */
+#define _HFXO_CTRL_PRSSTATUSSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for HFXO_CTRL */
+#define _HFXO_CTRL_PRSSTATUSSEL1_ENS 0x00000001UL /**< Mode ENS for HFXO_CTRL */
+#define _HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY 0x00000002UL /**< Mode COREBIASOPTRDY for HFXO_CTRL */
+#define _HFXO_CTRL_PRSSTATUSSEL1_RDY 0x00000003UL /**< Mode RDY for HFXO_CTRL */
+#define _HFXO_CTRL_PRSSTATUSSEL1_PRSRDY 0x00000004UL /**< Mode PRSRDY for HFXO_CTRL */
+#define _HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY 0x00000005UL /**< Mode BUFOUTRDY for HFXO_CTRL */
+#define _HFXO_CTRL_PRSSTATUSSEL1_HWREQ 0x00000008UL /**< Mode HWREQ for HFXO_CTRL */
+#define _HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ 0x00000009UL /**< Mode PRSHWREQ for HFXO_CTRL */
+#define _HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ 0x0000000AUL /**< Mode BUFOUTHWREQ for HFXO_CTRL */
+#define HFXO_CTRL_PRSSTATUSSEL1_DEFAULT (_HFXO_CTRL_PRSSTATUSSEL1_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_CTRL */
+#define HFXO_CTRL_PRSSTATUSSEL1_DISABLED (_HFXO_CTRL_PRSSTATUSSEL1_DISABLED << 12) /**< Shifted mode DISABLED for HFXO_CTRL */
+#define HFXO_CTRL_PRSSTATUSSEL1_ENS (_HFXO_CTRL_PRSSTATUSSEL1_ENS << 12) /**< Shifted mode ENS for HFXO_CTRL */
+#define HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY (_HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY << 12) /**< Shifted mode COREBIASOPTRDY for HFXO_CTRL */
+#define HFXO_CTRL_PRSSTATUSSEL1_RDY (_HFXO_CTRL_PRSSTATUSSEL1_RDY << 12) /**< Shifted mode RDY for HFXO_CTRL */
+#define HFXO_CTRL_PRSSTATUSSEL1_PRSRDY (_HFXO_CTRL_PRSSTATUSSEL1_PRSRDY << 12) /**< Shifted mode PRSRDY for HFXO_CTRL */
+#define HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY (_HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY << 12) /**< Shifted mode BUFOUTRDY for HFXO_CTRL */
+#define HFXO_CTRL_PRSSTATUSSEL1_HWREQ (_HFXO_CTRL_PRSSTATUSSEL1_HWREQ << 12) /**< Shifted mode HWREQ for HFXO_CTRL */
+#define HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ (_HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ << 12) /**< Shifted mode PRSHWREQ for HFXO_CTRL */
+#define HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ (_HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ << 12) /**< Shifted mode BUFOUTHWREQ for HFXO_CTRL */
+#define HFXO_CTRL_FORCEEN (0x1UL << 16) /**< Force Digital Clock Request */
+#define _HFXO_CTRL_FORCEEN_SHIFT 16 /**< Shift value for HFXO_FORCEEN */
+#define _HFXO_CTRL_FORCEEN_MASK 0x10000UL /**< Bit mask for HFXO_FORCEEN */
+#define _HFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */
+#define HFXO_CTRL_FORCEEN_DEFAULT (_HFXO_CTRL_FORCEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_CTRL */
+#define HFXO_CTRL_FORCEENPRS (0x1UL << 17) /**< Force PRS Oscillator Request */
+#define _HFXO_CTRL_FORCEENPRS_SHIFT 17 /**< Shift value for HFXO_FORCEENPRS */
+#define _HFXO_CTRL_FORCEENPRS_MASK 0x20000UL /**< Bit mask for HFXO_FORCEENPRS */
+#define _HFXO_CTRL_FORCEENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */
+#define HFXO_CTRL_FORCEENPRS_DEFAULT (_HFXO_CTRL_FORCEENPRS_DEFAULT << 17) /**< Shifted mode DEFAULT for HFXO_CTRL */
+#define HFXO_CTRL_FORCEENBUFOUT (0x1UL << 18) /**< Force BUFOUT Request */
+#define _HFXO_CTRL_FORCEENBUFOUT_SHIFT 18 /**< Shift value for HFXO_FORCEENBUFOUT */
+#define _HFXO_CTRL_FORCEENBUFOUT_MASK 0x40000UL /**< Bit mask for HFXO_FORCEENBUFOUT */
+#define _HFXO_CTRL_FORCEENBUFOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */
+#define HFXO_CTRL_FORCEENBUFOUT_DEFAULT (_HFXO_CTRL_FORCEENBUFOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for HFXO_CTRL */
+#define HFXO_CTRL_DISONDEMAND (0x1UL << 24) /**< Disable On-demand For Digital Clock */
+#define _HFXO_CTRL_DISONDEMAND_SHIFT 24 /**< Shift value for HFXO_DISONDEMAND */
+#define _HFXO_CTRL_DISONDEMAND_MASK 0x1000000UL /**< Bit mask for HFXO_DISONDEMAND */
+#define _HFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */
+#define HFXO_CTRL_DISONDEMAND_DEFAULT (_HFXO_CTRL_DISONDEMAND_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_CTRL */
+#define HFXO_CTRL_DISONDEMANDPRS (0x1UL << 25) /**< Disable On-demand For PRS */
+#define _HFXO_CTRL_DISONDEMANDPRS_SHIFT 25 /**< Shift value for HFXO_DISONDEMANDPRS */
+#define _HFXO_CTRL_DISONDEMANDPRS_MASK 0x2000000UL /**< Bit mask for HFXO_DISONDEMANDPRS */
+#define _HFXO_CTRL_DISONDEMANDPRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */
+#define HFXO_CTRL_DISONDEMANDPRS_DEFAULT (_HFXO_CTRL_DISONDEMANDPRS_DEFAULT << 25) /**< Shifted mode DEFAULT for HFXO_CTRL */
+#define HFXO_CTRL_DISONDEMANDBUFOUT (0x1UL << 26) /**< Disable On-demand For BUFOUT */
+#define _HFXO_CTRL_DISONDEMANDBUFOUT_SHIFT 26 /**< Shift value for HFXO_DISONDEMANDBUFOUT */
+#define _HFXO_CTRL_DISONDEMANDBUFOUT_MASK 0x4000000UL /**< Bit mask for HFXO_DISONDEMANDBUFOUT */
+#define _HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */
+#define HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT (_HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT << 26) /**< Shifted mode DEFAULT for HFXO_CTRL */
+
+/* Bit fields for HFXO BUFOUTTRIM */
+#define _HFXO_BUFOUTTRIM_RESETVALUE 0x00000008UL /**< Default value for HFXO_BUFOUTTRIM */
+#define _HFXO_BUFOUTTRIM_MASK 0x0000000FUL /**< Mask for HFXO_BUFOUTTRIM */
+#define _HFXO_BUFOUTTRIM_VTRTRIMANA_SHIFT 0 /**< Shift value for HFXO_VTRTRIMANA */
+#define _HFXO_BUFOUTTRIM_VTRTRIMANA_MASK 0xFUL /**< Bit mask for HFXO_VTRTRIMANA */
+#define _HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT 0x00000008UL /**< Mode DEFAULT for HFXO_BUFOUTTRIM */
+#define HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT (_HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_BUFOUTTRIM */
+
+/* Bit fields for HFXO BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_RESETVALUE 0x00643C15UL /**< Default value for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_MASK 0xC0FFFFFFUL /**< Mask for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_XOUTBIASANA_SHIFT 0 /**< Shift value for HFXO_XOUTBIASANA */
+#define _HFXO_BUFOUTCTRL_XOUTBIASANA_MASK 0xFUL /**< Bit mask for HFXO_XOUTBIASANA */
+#define _HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT 0x00000005UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_XOUTCFANA_SHIFT 4 /**< Shift value for HFXO_XOUTCFANA */
+#define _HFXO_BUFOUTCTRL_XOUTCFANA_MASK 0xF0UL /**< Bit mask for HFXO_XOUTCFANA */
+#define _HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT << 4) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_XOUTGMANA_SHIFT 8 /**< Shift value for HFXO_XOUTGMANA */
+#define _HFXO_BUFOUTCTRL_XOUTGMANA_MASK 0xF00UL /**< Bit mask for HFXO_XOUTGMANA */
+#define _HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT 0x0000000CUL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_SHIFT 12 /**< Shift value for HFXO_PEAKDETTHRESANA */
+#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_MASK 0xF000UL /**< Bit mask for HFXO_PEAKDETTHRESANA */
+#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV 0x00000000UL /**< Mode V105MV for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV 0x00000001UL /**< Mode V132MV for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV 0x00000002UL /**< Mode V157MV for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV 0x00000003UL /**< Mode V184MV for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV 0x00000004UL /**< Mode V210MV for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV 0x00000005UL /**< Mode V236MV for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV 0x00000006UL /**< Mode V262MV for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV 0x00000007UL /**< Mode V289MV for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV 0x00000008UL /**< Mode V315MV for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV 0x00000009UL /**< Mode V341MV for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV 0x0000000AUL /**< Mode V367MV for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV 0x0000000BUL /**< Mode V394MV for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV 0x0000000CUL /**< Mode V420MV for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV 0x0000000DUL /**< Mode V446MV for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV 0x0000000EUL /**< Mode V472MV for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV 0x0000000FUL /**< Mode V499MV for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV << 12) /**< Shifted mode V105MV for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV << 12) /**< Shifted mode V132MV for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV << 12) /**< Shifted mode V157MV for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV << 12) /**< Shifted mode V184MV for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV << 12) /**< Shifted mode V210MV for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV << 12) /**< Shifted mode V236MV for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV << 12) /**< Shifted mode V262MV for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV << 12) /**< Shifted mode V289MV for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV << 12) /**< Shifted mode V315MV for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV << 12) /**< Shifted mode V341MV for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV << 12) /**< Shifted mode V367MV for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV << 12) /**< Shifted mode V394MV for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV << 12) /**< Shifted mode V420MV for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV << 12) /**< Shifted mode V446MV for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV << 12) /**< Shifted mode V472MV for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV << 12) /**< Shifted mode V499MV for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_SHIFT 16 /**< Shift value for HFXO_TIMEOUTCTUNE */
+#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_MASK 0xF0000UL /**< Bit mask for HFXO_TIMEOUTCTUNE */
+#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT 0x00000004UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US 0x00000000UL /**< Mode T2US for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US 0x00000001UL /**< Mode T5US for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US 0x00000002UL /**< Mode T10US for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US 0x00000003UL /**< Mode T16US for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US 0x00000004UL /**< Mode T21US for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US 0x00000005UL /**< Mode T26US for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US 0x00000006UL /**< Mode T31US for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US 0x00000007UL /**< Mode T42US for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US 0x00000008UL /**< Mode T52US for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US 0x00000009UL /**< Mode T63US for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US 0x0000000AUL /**< Mode T83US for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US 0x0000000BUL /**< Mode T104US for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US 0x0000000CUL /**< Mode T208US for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US 0x0000000DUL /**< Mode T313US for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US 0x0000000EUL /**< Mode T521US for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US 0x0000000FUL /**< Mode T938US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US << 16) /**< Shifted mode T2US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US << 16) /**< Shifted mode T5US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US << 16) /**< Shifted mode T10US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US << 16) /**< Shifted mode T16US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US << 16) /**< Shifted mode T21US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US << 16) /**< Shifted mode T26US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US << 16) /**< Shifted mode T31US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US << 16) /**< Shifted mode T42US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US << 16) /**< Shifted mode T52US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US << 16) /**< Shifted mode T63US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US << 16) /**< Shifted mode T83US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US << 16) /**< Shifted mode T104US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US << 16) /**< Shifted mode T208US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US << 16) /**< Shifted mode T313US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US << 16) /**< Shifted mode T521US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US << 16) /**< Shifted mode T938US for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_SHIFT 20 /**< Shift value for HFXO_TIMEOUTSTARTUP */
+#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_MASK 0xF00000UL /**< Bit mask for HFXO_TIMEOUTSTARTUP */
+#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT 0x00000006UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US 0x00000000UL /**< Mode T42US for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US 0x00000001UL /**< Mode T83US for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US 0x00000002UL /**< Mode T108US for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US 0x00000003UL /**< Mode T133US for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US 0x00000004UL /**< Mode T158US for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US 0x00000005UL /**< Mode T183US for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US 0x00000006UL /**< Mode T208US for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US 0x00000007UL /**< Mode T233US for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US 0x00000008UL /**< Mode T258US for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US 0x00000009UL /**< Mode T283US for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US 0x0000000AUL /**< Mode T333US for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US 0x0000000BUL /**< Mode T375US for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US 0x0000000CUL /**< Mode T417US for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US 0x0000000DUL /**< Mode T458US for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US 0x0000000EUL /**< Mode T500US for HFXO_BUFOUTCTRL */
+#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US 0x0000000FUL /**< Mode T667US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US << 20) /**< Shifted mode T42US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US << 20) /**< Shifted mode T83US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US << 20) /**< Shifted mode T108US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US << 20) /**< Shifted mode T133US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US << 20) /**< Shifted mode T158US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US << 20) /**< Shifted mode T183US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US << 20) /**< Shifted mode T208US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US << 20) /**< Shifted mode T233US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US << 20) /**< Shifted mode T258US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US << 20) /**< Shifted mode T283US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US << 20) /**< Shifted mode T333US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US << 20) /**< Shifted mode T375US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US << 20) /**< Shifted mode T417US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US << 20) /**< Shifted mode T458US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US << 20) /**< Shifted mode T500US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US << 20) /**< Shifted mode T667US for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY (0x1UL << 31) /**< Minimum Startup Delay */
+#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_SHIFT 31 /**< Shift value for HFXO_MINIMUMSTARTUPDELAY */
+#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_MASK 0x80000000UL /**< Bit mask for HFXO_MINIMUMSTARTUPDELAY */
+#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */
+#define HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT (_HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */
+
+/* Bit fields for HFXO CMD */
+#define _HFXO_CMD_RESETVALUE 0x00000000UL /**< Default value for HFXO_CMD */
+#define _HFXO_CMD_MASK 0x00000001UL /**< Mask for HFXO_CMD */
+#define HFXO_CMD_COREBIASOPT (0x1UL << 0) /**< Core Bias Optimizaton */
+#define _HFXO_CMD_COREBIASOPT_SHIFT 0 /**< Shift value for HFXO_COREBIASOPT */
+#define _HFXO_CMD_COREBIASOPT_MASK 0x1UL /**< Bit mask for HFXO_COREBIASOPT */
+#define _HFXO_CMD_COREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CMD */
+#define HFXO_CMD_COREBIASOPT_DEFAULT (_HFXO_CMD_COREBIASOPT_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CMD */
+
+/* Bit fields for HFXO STATUS */
+#define _HFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFXO_STATUS */
+#define _HFXO_STATUS_MASK 0xC03F800FUL /**< Mask for HFXO_STATUS */
+#define HFXO_STATUS_RDY (0x1UL << 0) /**< Ready Status */
+#define _HFXO_STATUS_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */
+#define _HFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */
+#define _HFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */
+#define HFXO_STATUS_RDY_DEFAULT (_HFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_STATUS */
+#define HFXO_STATUS_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready */
+#define _HFXO_STATUS_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */
+#define _HFXO_STATUS_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */
+#define _HFXO_STATUS_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */
+#define HFXO_STATUS_COREBIASOPTRDY_DEFAULT (_HFXO_STATUS_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_STATUS */
+#define HFXO_STATUS_PRSRDY (0x1UL << 2) /**< PRS Ready Status */
+#define _HFXO_STATUS_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */
+#define _HFXO_STATUS_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */
+#define _HFXO_STATUS_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */
+#define HFXO_STATUS_PRSRDY_DEFAULT (_HFXO_STATUS_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_STATUS */
+#define HFXO_STATUS_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Status */
+#define _HFXO_STATUS_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */
+#define _HFXO_STATUS_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */
+#define _HFXO_STATUS_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */
+#define HFXO_STATUS_BUFOUTRDY_DEFAULT (_HFXO_STATUS_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_STATUS */
+#define HFXO_STATUS_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT Frozen */
+#define _HFXO_STATUS_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */
+#define _HFXO_STATUS_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */
+#define _HFXO_STATUS_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */
+#define HFXO_STATUS_BUFOUTFROZEN_DEFAULT (_HFXO_STATUS_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_STATUS */
+#define HFXO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */
+#define _HFXO_STATUS_ENS_SHIFT 16 /**< Shift value for HFXO_ENS */
+#define _HFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFXO_ENS */
+#define _HFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */
+#define HFXO_STATUS_ENS_DEFAULT (_HFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_STATUS */
+#define HFXO_STATUS_HWREQ (0x1UL << 17) /**< Oscillator Requested by Digital Clock */
+#define _HFXO_STATUS_HWREQ_SHIFT 17 /**< Shift value for HFXO_HWREQ */
+#define _HFXO_STATUS_HWREQ_MASK 0x20000UL /**< Bit mask for HFXO_HWREQ */
+#define _HFXO_STATUS_HWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */
+#define HFXO_STATUS_HWREQ_DEFAULT (_HFXO_STATUS_HWREQ_DEFAULT << 17) /**< Shifted mode DEFAULT for HFXO_STATUS */
+#define HFXO_STATUS_ISWARM (0x1UL << 19) /**< Oscillator Is Kept Warm */
+#define _HFXO_STATUS_ISWARM_SHIFT 19 /**< Shift value for HFXO_ISWARM */
+#define _HFXO_STATUS_ISWARM_MASK 0x80000UL /**< Bit mask for HFXO_ISWARM */
+#define _HFXO_STATUS_ISWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */
+#define HFXO_STATUS_ISWARM_DEFAULT (_HFXO_STATUS_ISWARM_DEFAULT << 19) /**< Shifted mode DEFAULT for HFXO_STATUS */
+#define HFXO_STATUS_PRSHWREQ (0x1UL << 20) /**< Oscillator Requested by PRS Request */
+#define _HFXO_STATUS_PRSHWREQ_SHIFT 20 /**< Shift value for HFXO_PRSHWREQ */
+#define _HFXO_STATUS_PRSHWREQ_MASK 0x100000UL /**< Bit mask for HFXO_PRSHWREQ */
+#define _HFXO_STATUS_PRSHWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */
+#define HFXO_STATUS_PRSHWREQ_DEFAULT (_HFXO_STATUS_PRSHWREQ_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_STATUS */
+#define HFXO_STATUS_BUFOUTHWREQ (0x1UL << 21) /**< Oscillator Requested by BUFOUT Request */
+#define _HFXO_STATUS_BUFOUTHWREQ_SHIFT 21 /**< Shift value for HFXO_BUFOUTHWREQ */
+#define _HFXO_STATUS_BUFOUTHWREQ_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTHWREQ */
+#define _HFXO_STATUS_BUFOUTHWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */
+#define HFXO_STATUS_BUFOUTHWREQ_DEFAULT (_HFXO_STATUS_BUFOUTHWREQ_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_STATUS */
+#define HFXO_STATUS_SYNCBUSY (0x1UL << 30) /**< Sync Busy */
+#define _HFXO_STATUS_SYNCBUSY_SHIFT 30 /**< Shift value for HFXO_SYNCBUSY */
+#define _HFXO_STATUS_SYNCBUSY_MASK 0x40000000UL /**< Bit mask for HFXO_SYNCBUSY */
+#define _HFXO_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */
+#define HFXO_STATUS_SYNCBUSY_DEFAULT (_HFXO_STATUS_SYNCBUSY_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_STATUS */
+#define HFXO_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */
+#define _HFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFXO_LOCK */
+#define _HFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFXO_LOCK */
+#define _HFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */
+#define _HFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFXO_STATUS */
+#define _HFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFXO_STATUS */
+#define HFXO_STATUS_LOCK_DEFAULT (_HFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_STATUS */
+#define HFXO_STATUS_LOCK_UNLOCKED (_HFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFXO_STATUS */
+#define HFXO_STATUS_LOCK_LOCKED (_HFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFXO_STATUS */
+
+/* Bit fields for HFXO IF */
+#define _HFXO_IF_RESETVALUE 0x00000000UL /**< Default value for HFXO_IF */
+#define _HFXO_IF_MASK 0xF830800FUL /**< Mask for HFXO_IF */
+#define HFXO_IF_RDY (0x1UL << 0) /**< Digital Clock Ready Interrupt */
+#define _HFXO_IF_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */
+#define _HFXO_IF_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */
+#define _HFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */
+#define HFXO_IF_RDY_DEFAULT (_HFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IF */
+#define HFXO_IF_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */
+#define _HFXO_IF_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */
+#define _HFXO_IF_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */
+#define _HFXO_IF_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */
+#define HFXO_IF_COREBIASOPTRDY_DEFAULT (_HFXO_IF_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IF */
+#define HFXO_IF_PRSRDY (0x1UL << 2) /**< PRS Ready Interrupt */
+#define _HFXO_IF_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */
+#define _HFXO_IF_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */
+#define _HFXO_IF_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */
+#define HFXO_IF_PRSRDY_DEFAULT (_HFXO_IF_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_IF */
+#define HFXO_IF_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Interrupt */
+#define _HFXO_IF_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */
+#define _HFXO_IF_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */
+#define _HFXO_IF_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */
+#define HFXO_IF_BUFOUTRDY_DEFAULT (_HFXO_IF_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_IF */
+#define HFXO_IF_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT FROZEN Interrupt */
+#define _HFXO_IF_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */
+#define _HFXO_IF_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */
+#define _HFXO_IF_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */
+#define HFXO_IF_BUFOUTFROZEN_DEFAULT (_HFXO_IF_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_IF */
+#define HFXO_IF_PRSERR (0x1UL << 20) /**< PRS Requset Error Interrupt */
+#define _HFXO_IF_PRSERR_SHIFT 20 /**< Shift value for HFXO_PRSERR */
+#define _HFXO_IF_PRSERR_MASK 0x100000UL /**< Bit mask for HFXO_PRSERR */
+#define _HFXO_IF_PRSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */
+#define HFXO_IF_PRSERR_DEFAULT (_HFXO_IF_PRSERR_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_IF */
+#define HFXO_IF_BUFOUTERR (0x1UL << 21) /**< BUFOUT Request Error Interrupt */
+#define _HFXO_IF_BUFOUTERR_SHIFT 21 /**< Shift value for HFXO_BUFOUTERR */
+#define _HFXO_IF_BUFOUTERR_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTERR */
+#define _HFXO_IF_BUFOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */
+#define HFXO_IF_BUFOUTERR_DEFAULT (_HFXO_IF_BUFOUTERR_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_IF */
+#define HFXO_IF_BUFOUTFREEZEERR (0x1UL << 27) /**< BUFOUT Freeze Error Interrupt */
+#define _HFXO_IF_BUFOUTFREEZEERR_SHIFT 27 /**< Shift value for HFXO_BUFOUTFREEZEERR */
+#define _HFXO_IF_BUFOUTFREEZEERR_MASK 0x8000000UL /**< Bit mask for HFXO_BUFOUTFREEZEERR */
+#define _HFXO_IF_BUFOUTFREEZEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */
+#define HFXO_IF_BUFOUTFREEZEERR_DEFAULT (_HFXO_IF_BUFOUTFREEZEERR_DEFAULT << 27) /**< Shifted mode DEFAULT for HFXO_IF */
+#define HFXO_IF_BUFOUTDNSERR (0x1UL << 28) /**< BUFOUT Did Not Start Error Interrupt */
+#define _HFXO_IF_BUFOUTDNSERR_SHIFT 28 /**< Shift value for HFXO_BUFOUTDNSERR */
+#define _HFXO_IF_BUFOUTDNSERR_MASK 0x10000000UL /**< Bit mask for HFXO_BUFOUTDNSERR */
+#define _HFXO_IF_BUFOUTDNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */
+#define HFXO_IF_BUFOUTDNSERR_DEFAULT (_HFXO_IF_BUFOUTDNSERR_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_IF */
+#define HFXO_IF_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */
+#define _HFXO_IF_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */
+#define _HFXO_IF_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */
+#define _HFXO_IF_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */
+#define HFXO_IF_DNSERR_DEFAULT (_HFXO_IF_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IF */
+#define HFXO_IF_LFTIMEOUTERR (0x1UL << 30) /**< Low Frequency Timeout Error Interrupt */
+#define _HFXO_IF_LFTIMEOUTERR_SHIFT 30 /**< Shift value for HFXO_LFTIMEOUTERR */
+#define _HFXO_IF_LFTIMEOUTERR_MASK 0x40000000UL /**< Bit mask for HFXO_LFTIMEOUTERR */
+#define _HFXO_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */
+#define HFXO_IF_LFTIMEOUTERR_DEFAULT (_HFXO_IF_LFTIMEOUTERR_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_IF */
+#define HFXO_IF_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */
+#define _HFXO_IF_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */
+#define _HFXO_IF_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */
+#define _HFXO_IF_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */
+#define HFXO_IF_COREBIASOPTERR_DEFAULT (_HFXO_IF_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IF */
+
+/* Bit fields for HFXO IEN */
+#define _HFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFXO_IEN */
+#define _HFXO_IEN_MASK 0xF830800FUL /**< Mask for HFXO_IEN */
+#define HFXO_IEN_RDY (0x1UL << 0) /**< Digital Clock Ready Interrupt */
+#define _HFXO_IEN_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */
+#define _HFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */
+#define _HFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */
+#define HFXO_IEN_RDY_DEFAULT (_HFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IEN */
+#define HFXO_IEN_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */
+#define _HFXO_IEN_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */
+#define _HFXO_IEN_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */
+#define _HFXO_IEN_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */
+#define HFXO_IEN_COREBIASOPTRDY_DEFAULT (_HFXO_IEN_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IEN */
+#define HFXO_IEN_PRSRDY (0x1UL << 2) /**< PRS Ready Interrupt */
+#define _HFXO_IEN_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */
+#define _HFXO_IEN_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */
+#define _HFXO_IEN_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */
+#define HFXO_IEN_PRSRDY_DEFAULT (_HFXO_IEN_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_IEN */
+#define HFXO_IEN_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Interrupt */
+#define _HFXO_IEN_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */
+#define _HFXO_IEN_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */
+#define _HFXO_IEN_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */
+#define HFXO_IEN_BUFOUTRDY_DEFAULT (_HFXO_IEN_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_IEN */
+#define HFXO_IEN_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT FROZEN Interrupt */
+#define _HFXO_IEN_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */
+#define _HFXO_IEN_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */
+#define _HFXO_IEN_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */
+#define HFXO_IEN_BUFOUTFROZEN_DEFAULT (_HFXO_IEN_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_IEN */
+#define HFXO_IEN_PRSERR (0x1UL << 20) /**< PRS Requset Error Interrupt */
+#define _HFXO_IEN_PRSERR_SHIFT 20 /**< Shift value for HFXO_PRSERR */
+#define _HFXO_IEN_PRSERR_MASK 0x100000UL /**< Bit mask for HFXO_PRSERR */
+#define _HFXO_IEN_PRSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */
+#define HFXO_IEN_PRSERR_DEFAULT (_HFXO_IEN_PRSERR_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_IEN */
+#define HFXO_IEN_BUFOUTERR (0x1UL << 21) /**< BUFOUT Request Error Interrupt */
+#define _HFXO_IEN_BUFOUTERR_SHIFT 21 /**< Shift value for HFXO_BUFOUTERR */
+#define _HFXO_IEN_BUFOUTERR_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTERR */
+#define _HFXO_IEN_BUFOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */
+#define HFXO_IEN_BUFOUTERR_DEFAULT (_HFXO_IEN_BUFOUTERR_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_IEN */
+#define HFXO_IEN_BUFOUTFREEZEERR (0x1UL << 27) /**< BUFOUT Freeze Error Interrupt */
+#define _HFXO_IEN_BUFOUTFREEZEERR_SHIFT 27 /**< Shift value for HFXO_BUFOUTFREEZEERR */
+#define _HFXO_IEN_BUFOUTFREEZEERR_MASK 0x8000000UL /**< Bit mask for HFXO_BUFOUTFREEZEERR */
+#define _HFXO_IEN_BUFOUTFREEZEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */
+#define HFXO_IEN_BUFOUTFREEZEERR_DEFAULT (_HFXO_IEN_BUFOUTFREEZEERR_DEFAULT << 27) /**< Shifted mode DEFAULT for HFXO_IEN */
+#define HFXO_IEN_BUFOUTDNSERR (0x1UL << 28) /**< BUFOUT Did Not Start Error Interrupt */
+#define _HFXO_IEN_BUFOUTDNSERR_SHIFT 28 /**< Shift value for HFXO_BUFOUTDNSERR */
+#define _HFXO_IEN_BUFOUTDNSERR_MASK 0x10000000UL /**< Bit mask for HFXO_BUFOUTDNSERR */
+#define _HFXO_IEN_BUFOUTDNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */
+#define HFXO_IEN_BUFOUTDNSERR_DEFAULT (_HFXO_IEN_BUFOUTDNSERR_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_IEN */
+#define HFXO_IEN_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */
+#define _HFXO_IEN_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */
+#define _HFXO_IEN_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */
+#define _HFXO_IEN_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */
+#define HFXO_IEN_DNSERR_DEFAULT (_HFXO_IEN_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IEN */
+#define HFXO_IEN_LFTIMEOUTERR (0x1UL << 30) /**< Low Frequency Timeout Error Interrupt */
+#define _HFXO_IEN_LFTIMEOUTERR_SHIFT 30 /**< Shift value for HFXO_LFTIMEOUTERR */
+#define _HFXO_IEN_LFTIMEOUTERR_MASK 0x40000000UL /**< Bit mask for HFXO_LFTIMEOUTERR */
+#define _HFXO_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */
+#define HFXO_IEN_LFTIMEOUTERR_DEFAULT (_HFXO_IEN_LFTIMEOUTERR_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_IEN */
+#define HFXO_IEN_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */
+#define _HFXO_IEN_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */
+#define _HFXO_IEN_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */
+#define _HFXO_IEN_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */
+#define HFXO_IEN_COREBIASOPTERR_DEFAULT (_HFXO_IEN_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IEN */
+
+/* Bit fields for HFXO LOCK */
+#define _HFXO_LOCK_RESETVALUE 0x0000580EUL /**< Default value for HFXO_LOCK */
+#define _HFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFXO_LOCK */
+#define _HFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFXO_LOCKKEY */
+#define _HFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFXO_LOCKKEY */
+#define _HFXO_LOCK_LOCKKEY_DEFAULT 0x0000580EUL /**< Mode DEFAULT for HFXO_LOCK */
+#define _HFXO_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for HFXO_LOCK */
+#define HFXO_LOCK_LOCKKEY_DEFAULT (_HFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_LOCK */
+#define HFXO_LOCK_LOCKKEY_UNLOCK (_HFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFXO_LOCK */
+
+/** @} End of group EFR32MG24_HFXO_BitFields */
+/** @} End of group EFR32MG24_HFXO */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_HFXO_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_i2c.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_i2c.h
new file mode 100644
index 00000000..2ee8509c
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_i2c.h
@@ -0,0 +1,744 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 I2C register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_I2C_H
+#define EFR32MG24_I2C_H
+#define I2C_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_I2C I2C
+ * @{
+ * @brief EFR32MG24 I2C Register Declaration.
+ *****************************************************************************/
+
+/** I2C Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IP VERSION Register */
+ __IOM uint32_t EN; /**< Enable Register */
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IM uint32_t STATE; /**< State Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IOM uint32_t CLKDIV; /**< Clock Division Register */
+ __IOM uint32_t SADDR; /**< Follower Address Register */
+ __IOM uint32_t SADDRMASK; /**< Follower Address Mask Register */
+ __IM uint32_t RXDATA; /**< Receive Buffer Data Register */
+ __IM uint32_t RXDOUBLE; /**< Receive Buffer Double Data Register */
+ __IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */
+ __IM uint32_t RXDOUBLEP; /**< Receive Buffer Double Data Peek Register */
+ __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */
+ __IOM uint32_t TXDOUBLE; /**< Transmit Buffer Double Data Register */
+ __IOM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ uint32_t RESERVED0[1007U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP VERSION Register */
+ __IOM uint32_t EN_SET; /**< Enable Register */
+ __IOM uint32_t CTRL_SET; /**< Control Register */
+ __IOM uint32_t CMD_SET; /**< Command Register */
+ __IM uint32_t STATE_SET; /**< State Register */
+ __IM uint32_t STATUS_SET; /**< Status Register */
+ __IOM uint32_t CLKDIV_SET; /**< Clock Division Register */
+ __IOM uint32_t SADDR_SET; /**< Follower Address Register */
+ __IOM uint32_t SADDRMASK_SET; /**< Follower Address Mask Register */
+ __IM uint32_t RXDATA_SET; /**< Receive Buffer Data Register */
+ __IM uint32_t RXDOUBLE_SET; /**< Receive Buffer Double Data Register */
+ __IM uint32_t RXDATAP_SET; /**< Receive Buffer Data Peek Register */
+ __IM uint32_t RXDOUBLEP_SET; /**< Receive Buffer Double Data Peek Register */
+ __IOM uint32_t TXDATA_SET; /**< Transmit Buffer Data Register */
+ __IOM uint32_t TXDOUBLE_SET; /**< Transmit Buffer Double Data Register */
+ __IOM uint32_t IF_SET; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
+ uint32_t RESERVED1[1007U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP VERSION Register */
+ __IOM uint32_t EN_CLR; /**< Enable Register */
+ __IOM uint32_t CTRL_CLR; /**< Control Register */
+ __IOM uint32_t CMD_CLR; /**< Command Register */
+ __IM uint32_t STATE_CLR; /**< State Register */
+ __IM uint32_t STATUS_CLR; /**< Status Register */
+ __IOM uint32_t CLKDIV_CLR; /**< Clock Division Register */
+ __IOM uint32_t SADDR_CLR; /**< Follower Address Register */
+ __IOM uint32_t SADDRMASK_CLR; /**< Follower Address Mask Register */
+ __IM uint32_t RXDATA_CLR; /**< Receive Buffer Data Register */
+ __IM uint32_t RXDOUBLE_CLR; /**< Receive Buffer Double Data Register */
+ __IM uint32_t RXDATAP_CLR; /**< Receive Buffer Data Peek Register */
+ __IM uint32_t RXDOUBLEP_CLR; /**< Receive Buffer Double Data Peek Register */
+ __IOM uint32_t TXDATA_CLR; /**< Transmit Buffer Data Register */
+ __IOM uint32_t TXDOUBLE_CLR; /**< Transmit Buffer Double Data Register */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
+ uint32_t RESERVED2[1007U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP VERSION Register */
+ __IOM uint32_t EN_TGL; /**< Enable Register */
+ __IOM uint32_t CTRL_TGL; /**< Control Register */
+ __IOM uint32_t CMD_TGL; /**< Command Register */
+ __IM uint32_t STATE_TGL; /**< State Register */
+ __IM uint32_t STATUS_TGL; /**< Status Register */
+ __IOM uint32_t CLKDIV_TGL; /**< Clock Division Register */
+ __IOM uint32_t SADDR_TGL; /**< Follower Address Register */
+ __IOM uint32_t SADDRMASK_TGL; /**< Follower Address Mask Register */
+ __IM uint32_t RXDATA_TGL; /**< Receive Buffer Data Register */
+ __IM uint32_t RXDOUBLE_TGL; /**< Receive Buffer Double Data Register */
+ __IM uint32_t RXDATAP_TGL; /**< Receive Buffer Data Peek Register */
+ __IM uint32_t RXDOUBLEP_TGL; /**< Receive Buffer Double Data Peek Register */
+ __IOM uint32_t TXDATA_TGL; /**< Transmit Buffer Data Register */
+ __IOM uint32_t TXDOUBLE_TGL; /**< Transmit Buffer Double Data Register */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
+} I2C_TypeDef;
+/** @} End of group EFR32MG24_I2C */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_I2C
+ * @{
+ * @defgroup EFR32MG24_I2C_BitFields I2C Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for I2C IPVERSION */
+#define _I2C_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for I2C_IPVERSION */
+#define _I2C_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for I2C_IPVERSION */
+#define _I2C_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for I2C_IPVERSION */
+#define _I2C_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for I2C_IPVERSION */
+#define _I2C_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IPVERSION */
+#define I2C_IPVERSION_IPVERSION_DEFAULT (_I2C_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IPVERSION */
+
+/* Bit fields for I2C EN */
+#define _I2C_EN_RESETVALUE 0x00000000UL /**< Default value for I2C_EN */
+#define _I2C_EN_MASK 0x00000001UL /**< Mask for I2C_EN */
+#define I2C_EN_EN (0x1UL << 0) /**< module enable */
+#define _I2C_EN_EN_SHIFT 0 /**< Shift value for I2C_EN */
+#define _I2C_EN_EN_MASK 0x1UL /**< Bit mask for I2C_EN */
+#define _I2C_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_EN */
+#define _I2C_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_EN */
+#define _I2C_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_EN */
+#define I2C_EN_EN_DEFAULT (_I2C_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_EN */
+#define I2C_EN_EN_DISABLE (_I2C_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for I2C_EN */
+#define I2C_EN_EN_ENABLE (_I2C_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for I2C_EN */
+
+/* Bit fields for I2C CTRL */
+#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */
+#define _I2C_CTRL_MASK 0x0037B3FFUL /**< Mask for I2C_CTRL */
+#define I2C_CTRL_CORERST (0x1UL << 0) /**< Soft Reset the internal state registers */
+#define _I2C_CTRL_CORERST_SHIFT 0 /**< Shift value for I2C_CORERST */
+#define _I2C_CTRL_CORERST_MASK 0x1UL /**< Bit mask for I2C_CORERST */
+#define _I2C_CTRL_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_CORERST_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */
+#define _I2C_CTRL_CORERST_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */
+#define I2C_CTRL_CORERST_DEFAULT (_I2C_CTRL_CORERST_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_CORERST_DISABLE (_I2C_CTRL_CORERST_DISABLE << 0) /**< Shifted mode DISABLE for I2C_CTRL */
+#define I2C_CTRL_CORERST_ENABLE (_I2C_CTRL_CORERST_ENABLE << 0) /**< Shifted mode ENABLE for I2C_CTRL */
+#define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Follower */
+#define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */
+#define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */
+#define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_SLAVE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */
+#define _I2C_CTRL_SLAVE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */
+#define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_SLAVE_DISABLE (_I2C_CTRL_SLAVE_DISABLE << 1) /**< Shifted mode DISABLE for I2C_CTRL */
+#define I2C_CTRL_SLAVE_ENABLE (_I2C_CTRL_SLAVE_ENABLE << 1) /**< Shifted mode ENABLE for I2C_CTRL */
+#define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */
+#define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */
+#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */
+#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_AUTOACK_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */
+#define _I2C_CTRL_AUTOACK_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */
+#define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_AUTOACK_DISABLE (_I2C_CTRL_AUTOACK_DISABLE << 2) /**< Shifted mode DISABLE for I2C_CTRL */
+#define I2C_CTRL_AUTOACK_ENABLE (_I2C_CTRL_AUTOACK_ENABLE << 2) /**< Shifted mode ENABLE for I2C_CTRL */
+#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */
+#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */
+#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */
+#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_AUTOSE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */
+#define _I2C_CTRL_AUTOSE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */
+#define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_AUTOSE_DISABLE (_I2C_CTRL_AUTOSE_DISABLE << 3) /**< Shifted mode DISABLE for I2C_CTRL */
+#define I2C_CTRL_AUTOSE_ENABLE (_I2C_CTRL_AUTOSE_ENABLE << 3) /**< Shifted mode ENABLE for I2C_CTRL */
+#define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */
+#define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */
+#define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */
+#define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_AUTOSN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */
+#define _I2C_CTRL_AUTOSN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */
+#define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_AUTOSN_DISABLE (_I2C_CTRL_AUTOSN_DISABLE << 4) /**< Shifted mode DISABLE for I2C_CTRL */
+#define I2C_CTRL_AUTOSN_ENABLE (_I2C_CTRL_AUTOSN_ENABLE << 4) /**< Shifted mode ENABLE for I2C_CTRL */
+#define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */
+#define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */
+#define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */
+#define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_ARBDIS_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */
+#define _I2C_CTRL_ARBDIS_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */
+#define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_ARBDIS_DISABLE (_I2C_CTRL_ARBDIS_DISABLE << 5) /**< Shifted mode DISABLE for I2C_CTRL */
+#define I2C_CTRL_ARBDIS_ENABLE (_I2C_CTRL_ARBDIS_ENABLE << 5) /**< Shifted mode ENABLE for I2C_CTRL */
+#define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */
+#define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */
+#define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */
+#define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_GCAMEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */
+#define _I2C_CTRL_GCAMEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */
+#define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_GCAMEN_DISABLE (_I2C_CTRL_GCAMEN_DISABLE << 6) /**< Shifted mode DISABLE for I2C_CTRL */
+#define I2C_CTRL_GCAMEN_ENABLE (_I2C_CTRL_GCAMEN_ENABLE << 6) /**< Shifted mode ENABLE for I2C_CTRL */
+#define I2C_CTRL_TXBIL (0x1UL << 7) /**< TX Buffer Interrupt Level */
+#define _I2C_CTRL_TXBIL_SHIFT 7 /**< Shift value for I2C_TXBIL */
+#define _I2C_CTRL_TXBIL_MASK 0x80UL /**< Bit mask for I2C_TXBIL */
+#define _I2C_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for I2C_CTRL */
+#define _I2C_CTRL_TXBIL_HALF_FULL 0x00000001UL /**< Mode HALF_FULL for I2C_CTRL */
+#define I2C_CTRL_TXBIL_DEFAULT (_I2C_CTRL_TXBIL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_TXBIL_EMPTY (_I2C_CTRL_TXBIL_EMPTY << 7) /**< Shifted mode EMPTY for I2C_CTRL */
+#define I2C_CTRL_TXBIL_HALF_FULL (_I2C_CTRL_TXBIL_HALF_FULL << 7) /**< Shifted mode HALF_FULL for I2C_CTRL */
+#define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */
+#define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */
+#define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */
+#define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */
+#define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */
+#define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */
+#define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */
+#define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */
+#define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */
+#define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */
+#define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */
+#define _I2C_CTRL_BITO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */
+#define _I2C_CTRL_BITO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */
+#define _I2C_CTRL_BITO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */
+#define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */
+#define I2C_CTRL_BITO_I2C40PCC (_I2C_CTRL_BITO_I2C40PCC << 12) /**< Shifted mode I2C40PCC for I2C_CTRL */
+#define I2C_CTRL_BITO_I2C80PCC (_I2C_CTRL_BITO_I2C80PCC << 12) /**< Shifted mode I2C80PCC for I2C_CTRL */
+#define I2C_CTRL_BITO_I2C160PCC (_I2C_CTRL_BITO_I2C160PCC << 12) /**< Shifted mode I2C160PCC for I2C_CTRL */
+#define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */
+#define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */
+#define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */
+#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_GIBITO_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */
+#define _I2C_CTRL_GIBITO_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */
+#define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_GIBITO_DISABLE (_I2C_CTRL_GIBITO_DISABLE << 15) /**< Shifted mode DISABLE for I2C_CTRL */
+#define I2C_CTRL_GIBITO_ENABLE (_I2C_CTRL_GIBITO_ENABLE << 15) /**< Shifted mode ENABLE for I2C_CTRL */
+#define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */
+#define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */
+#define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */
+#define _I2C_CTRL_CLTO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */
+#define _I2C_CTRL_CLTO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */
+#define _I2C_CTRL_CLTO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */
+#define _I2C_CTRL_CLTO_I2C320PCC 0x00000004UL /**< Mode I2C320PCC for I2C_CTRL */
+#define _I2C_CTRL_CLTO_I2C1024PCC 0x00000005UL /**< Mode I2C1024PCC for I2C_CTRL */
+#define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */
+#define I2C_CTRL_CLTO_I2C40PCC (_I2C_CTRL_CLTO_I2C40PCC << 16) /**< Shifted mode I2C40PCC for I2C_CTRL */
+#define I2C_CTRL_CLTO_I2C80PCC (_I2C_CTRL_CLTO_I2C80PCC << 16) /**< Shifted mode I2C80PCC for I2C_CTRL */
+#define I2C_CTRL_CLTO_I2C160PCC (_I2C_CTRL_CLTO_I2C160PCC << 16) /**< Shifted mode I2C160PCC for I2C_CTRL */
+#define I2C_CTRL_CLTO_I2C320PCC (_I2C_CTRL_CLTO_I2C320PCC << 16) /**< Shifted mode I2C320PCC for I2C_CTRL */
+#define I2C_CTRL_CLTO_I2C1024PCC (_I2C_CTRL_CLTO_I2C1024PCC << 16) /**< Shifted mode I2C1024PCC for I2C_CTRL */
+#define I2C_CTRL_SCLMONEN (0x1UL << 20) /**< SCL Monitor Enable */
+#define _I2C_CTRL_SCLMONEN_SHIFT 20 /**< Shift value for I2C_SCLMONEN */
+#define _I2C_CTRL_SCLMONEN_MASK 0x100000UL /**< Bit mask for I2C_SCLMONEN */
+#define _I2C_CTRL_SCLMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_SCLMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */
+#define _I2C_CTRL_SCLMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */
+#define I2C_CTRL_SCLMONEN_DEFAULT (_I2C_CTRL_SCLMONEN_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_SCLMONEN_DISABLE (_I2C_CTRL_SCLMONEN_DISABLE << 20) /**< Shifted mode DISABLE for I2C_CTRL */
+#define I2C_CTRL_SCLMONEN_ENABLE (_I2C_CTRL_SCLMONEN_ENABLE << 20) /**< Shifted mode ENABLE for I2C_CTRL */
+#define I2C_CTRL_SDAMONEN (0x1UL << 21) /**< SDA Monitor Enable */
+#define _I2C_CTRL_SDAMONEN_SHIFT 21 /**< Shift value for I2C_SDAMONEN */
+#define _I2C_CTRL_SDAMONEN_MASK 0x200000UL /**< Bit mask for I2C_SDAMONEN */
+#define _I2C_CTRL_SDAMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
+#define _I2C_CTRL_SDAMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */
+#define _I2C_CTRL_SDAMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */
+#define I2C_CTRL_SDAMONEN_DEFAULT (_I2C_CTRL_SDAMONEN_DEFAULT << 21) /**< Shifted mode DEFAULT for I2C_CTRL */
+#define I2C_CTRL_SDAMONEN_DISABLE (_I2C_CTRL_SDAMONEN_DISABLE << 21) /**< Shifted mode DISABLE for I2C_CTRL */
+#define I2C_CTRL_SDAMONEN_ENABLE (_I2C_CTRL_SDAMONEN_ENABLE << 21) /**< Shifted mode ENABLE for I2C_CTRL */
+
+/* Bit fields for I2C CMD */
+#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */
+#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */
+#define I2C_CMD_START (0x1UL << 0) /**< Send start condition */
+#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */
+#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */
+#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */
+#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */
+#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */
+#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */
+#define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */
+#define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */
+#define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */
+#define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */
+#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */
+#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */
+#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */
+#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */
+#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */
+#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */
+#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */
+#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */
+#define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */
+#define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */
+#define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */
+#define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */
+#define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */
+#define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */
+#define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
+#define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */
+
+/* Bit fields for I2C STATE */
+#define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */
+#define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */
+#define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */
+#define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */
+#define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */
+#define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */
+#define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */
+#define I2C_STATE_MASTER (0x1UL << 1) /**< Leader */
+#define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */
+#define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */
+#define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
+#define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */
+#define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */
+#define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */
+#define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */
+#define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
+#define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */
+#define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */
+#define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */
+#define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */
+#define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
+#define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */
+#define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */
+#define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */
+#define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */
+#define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
+#define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */
+#define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */
+#define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */
+#define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
+#define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */
+#define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */
+#define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */
+#define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */
+#define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */
+#define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */
+#define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */
+#define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */
+#define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */
+#define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */
+#define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */
+#define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */
+#define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */
+#define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */
+#define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */
+
+/* Bit fields for I2C STATUS */
+#define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */
+#define _I2C_STATUS_MASK 0x00000FFFUL /**< Mask for I2C_STATUS */
+#define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */
+#define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */
+#define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */
+#define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */
+#define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */
+#define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */
+#define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */
+#define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */
+#define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */
+#define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */
+#define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */
+#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */
+#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */
+#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */
+#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */
+#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */
+#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */
+#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */
+#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */
+#define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */
+#define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */
+#define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */
+#define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */
+#define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */
+#define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */
+#define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */
+#define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */
+#define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_RXFULL (0x1UL << 9) /**< RX FIFO Full */
+#define _I2C_STATUS_RXFULL_SHIFT 9 /**< Shift value for I2C_RXFULL */
+#define _I2C_STATUS_RXFULL_MASK 0x200UL /**< Bit mask for I2C_RXFULL */
+#define _I2C_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_RXFULL_DEFAULT (_I2C_STATUS_RXFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_STATUS */
+#define _I2C_STATUS_TXBUFCNT_SHIFT 10 /**< Shift value for I2C_TXBUFCNT */
+#define _I2C_STATUS_TXBUFCNT_MASK 0xC00UL /**< Bit mask for I2C_TXBUFCNT */
+#define _I2C_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
+#define I2C_STATUS_TXBUFCNT_DEFAULT (_I2C_STATUS_TXBUFCNT_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_STATUS */
+
+/* Bit fields for I2C CLKDIV */
+#define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */
+#define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */
+#define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */
+#define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */
+#define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */
+#define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */
+
+/* Bit fields for I2C SADDR */
+#define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */
+#define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */
+#define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */
+#define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */
+#define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */
+#define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */
+
+/* Bit fields for I2C SADDRMASK */
+#define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */
+#define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */
+#define _I2C_SADDRMASK_SADDRMASK_SHIFT 1 /**< Shift value for I2C_SADDRMASK */
+#define _I2C_SADDRMASK_SADDRMASK_MASK 0xFEUL /**< Bit mask for I2C_SADDRMASK */
+#define _I2C_SADDRMASK_SADDRMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */
+#define I2C_SADDRMASK_SADDRMASK_DEFAULT (_I2C_SADDRMASK_SADDRMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */
+
+/* Bit fields for I2C RXDATA */
+#define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */
+#define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */
+#define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */
+#define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */
+#define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */
+#define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */
+
+/* Bit fields for I2C RXDOUBLE */
+#define _I2C_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLE */
+#define _I2C_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLE */
+#define _I2C_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for I2C_RXDATA0 */
+#define _I2C_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for I2C_RXDATA0 */
+#define _I2C_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */
+#define I2C_RXDOUBLE_RXDATA0_DEFAULT (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */
+#define _I2C_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for I2C_RXDATA1 */
+#define _I2C_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATA1 */
+#define _I2C_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */
+#define I2C_RXDOUBLE_RXDATA1_DEFAULT (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */
+
+/* Bit fields for I2C RXDATAP */
+#define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */
+#define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */
+#define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */
+#define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */
+#define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */
+#define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */
+
+/* Bit fields for I2C RXDOUBLEP */
+#define _I2C_RXDOUBLEP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLEP */
+#define _I2C_RXDOUBLEP_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLEP */
+#define _I2C_RXDOUBLEP_RXDATAP0_SHIFT 0 /**< Shift value for I2C_RXDATAP0 */
+#define _I2C_RXDOUBLEP_RXDATAP0_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP0 */
+#define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */
+#define I2C_RXDOUBLEP_RXDATAP0_DEFAULT (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */
+#define _I2C_RXDOUBLEP_RXDATAP1_SHIFT 8 /**< Shift value for I2C_RXDATAP1 */
+#define _I2C_RXDOUBLEP_RXDATAP1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATAP1 */
+#define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */
+#define I2C_RXDOUBLEP_RXDATAP1_DEFAULT (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */
+
+/* Bit fields for I2C TXDATA */
+#define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */
+#define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */
+#define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */
+#define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */
+#define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */
+#define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */
+
+/* Bit fields for I2C TXDOUBLE */
+#define _I2C_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDOUBLE */
+#define _I2C_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_TXDOUBLE */
+#define _I2C_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for I2C_TXDATA0 */
+#define _I2C_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for I2C_TXDATA0 */
+#define _I2C_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */
+#define I2C_TXDOUBLE_TXDATA0_DEFAULT (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */
+#define _I2C_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for I2C_TXDATA1 */
+#define _I2C_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_TXDATA1 */
+#define _I2C_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */
+#define I2C_TXDOUBLE_TXDATA1_DEFAULT (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */
+
+/* Bit fields for I2C IF */
+#define _I2C_IF_RESETVALUE 0x00000000UL /**< Default value for I2C_IF */
+#define _I2C_IF_MASK 0x001FFFFFUL /**< Mask for I2C_IF */
+#define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */
+#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */
+#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */
+#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */
+#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
+#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
+#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */
+#define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
+#define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
+#define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */
+#define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
+#define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
+#define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */
+#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
+#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
+#define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */
+#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
+#define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */
+#define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */
+#define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
+#define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
+#define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */
+#define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
+#define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
+#define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */
+#define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
+#define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
+#define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */
+#define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
+#define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
+#define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */
+#define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
+#define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
+#define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */
+#define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
+#define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
+#define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */
+#define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
+#define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
+#define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */
+#define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
+#define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
+#define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */
+#define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
+#define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
+#define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */
+#define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
+#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
+#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */
+#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
+#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
+#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */
+#define _I2C_IF_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
+#define _I2C_IF_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
+#define _I2C_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_RXFULL_DEFAULT (_I2C_IF_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */
+#define _I2C_IF_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
+#define _I2C_IF_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
+#define _I2C_IF_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_CLERR_DEFAULT (_I2C_IF_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */
+#define _I2C_IF_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */
+#define _I2C_IF_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */
+#define _I2C_IF_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_SCLERR_DEFAULT (_I2C_IF_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IF */
+#define I2C_IF_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */
+#define _I2C_IF_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */
+#define _I2C_IF_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */
+#define _I2C_IF_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
+#define I2C_IF_SDAERR_DEFAULT (_I2C_IF_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IF */
+
+/* Bit fields for I2C IEN */
+#define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */
+#define _I2C_IEN_MASK 0x001FFFFFUL /**< Mask for I2C_IEN */
+#define I2C_IEN_START (0x1UL << 0) /**< START condition Interrupt Flag */
+#define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */
+#define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */
+#define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */
+#define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
+#define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
+#define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_ADDR (0x1UL << 2) /**< Address Interrupt Flag */
+#define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
+#define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
+#define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */
+#define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
+#define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
+#define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */
+#define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
+#define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
+#define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */
+#define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
+#define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */
+#define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */
+#define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
+#define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
+#define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */
+#define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
+#define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
+#define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */
+#define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
+#define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
+#define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */
+#define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
+#define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
+#define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */
+#define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
+#define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
+#define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */
+#define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
+#define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
+#define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */
+#define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
+#define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
+#define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */
+#define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
+#define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
+#define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */
+#define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
+#define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
+#define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */
+#define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
+#define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
+#define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */
+#define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
+#define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
+#define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */
+#define _I2C_IEN_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
+#define _I2C_IEN_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
+#define _I2C_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_RXFULL_DEFAULT (_I2C_IEN_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */
+#define _I2C_IEN_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
+#define _I2C_IEN_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
+#define _I2C_IEN_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_CLERR_DEFAULT (_I2C_IEN_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */
+#define _I2C_IEN_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */
+#define _I2C_IEN_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */
+#define _I2C_IEN_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_SCLERR_DEFAULT (_I2C_IEN_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IEN */
+#define I2C_IEN_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */
+#define _I2C_IEN_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */
+#define _I2C_IEN_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */
+#define _I2C_IEN_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
+#define I2C_IEN_SDAERR_DEFAULT (_I2C_IEN_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IEN */
+
+/** @} End of group EFR32MG24_I2C_BitFields */
+/** @} End of group EFR32MG24_I2C */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_I2C_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_iadc.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_iadc.h
new file mode 100644
index 00000000..2a3c00b9
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_iadc.h
@@ -0,0 +1,1072 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 IADC register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_IADC_H
+#define EFR32MG24_IADC_H
+#define IADC_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_IADC IADC
+ * @{
+ * @brief EFR32MG24 IADC Register Declaration.
+ *****************************************************************************/
+
+/** IADC CFG Register Group Declaration. */
+typedef struct {
+ __IOM uint32_t CFG; /**< Configuration */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+ __IOM uint32_t SCALE; /**< Scaling */
+ __IOM uint32_t SCHED; /**< Scheduling */
+} IADC_CFG_TypeDef;
+
+/** IADC SCANTABLE Register Group Declaration. */
+typedef struct {
+ __IOM uint32_t SCAN; /**< SCAN Entry */
+} IADC_SCANTABLE_TypeDef;
+
+/** IADC Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IPVERSION */
+ __IOM uint32_t EN; /**< Enable */
+ __IOM uint32_t CTRL; /**< Control */
+ __IOM uint32_t CMD; /**< Command */
+ __IOM uint32_t TIMER; /**< Timer */
+ __IM uint32_t STATUS; /**< Status */
+ __IOM uint32_t MASKREQ; /**< Mask Request */
+ __IM uint32_t STMASK; /**< Scan Table Mask */
+ __IOM uint32_t CMPTHR; /**< Digital Window Comparator Threshold */
+ __IOM uint32_t IF; /**< Interrupt Flags */
+ __IOM uint32_t IEN; /**< Interrupt Enable */
+ __IOM uint32_t TRIGGER; /**< Trigger */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+ uint32_t RESERVED1[5U]; /**< Reserved for future use */
+ IADC_CFG_TypeDef CFG[2U]; /**< CFG */
+ uint32_t RESERVED2[2U]; /**< Reserved for future use */
+ __IOM uint32_t SINGLEFIFOCFG; /**< Single FIFO Configuration */
+ __IM uint32_t SINGLEFIFODATA; /**< Single FIFO DATA */
+ __IM uint32_t SINGLEFIFOSTAT; /**< Single FIFO Status */
+ __IM uint32_t SINGLEDATA; /**< Single Data */
+ __IOM uint32_t SCANFIFOCFG; /**< Scan FIFO Configuration */
+ __IM uint32_t SCANFIFODATA; /**< Scan FIFO Read Data */
+ __IM uint32_t SCANFIFOSTAT; /**< Scan FIFO Status */
+ __IM uint32_t SCANDATA; /**< Scan Data */
+ uint32_t RESERVED3[1U]; /**< Reserved for future use */
+ uint32_t RESERVED4[1U]; /**< Reserved for future use */
+ __IOM uint32_t SINGLE; /**< Single Queue Port Selection */
+ uint32_t RESERVED5[1U]; /**< Reserved for future use */
+ IADC_SCANTABLE_TypeDef SCANTABLE[16U]; /**< SCANTABLE */
+ uint32_t RESERVED6[4U]; /**< Reserved for future use */
+ uint32_t RESERVED7[1U]; /**< Reserved for future use */
+ uint32_t RESERVED8[963U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IPVERSION */
+ __IOM uint32_t EN_SET; /**< Enable */
+ __IOM uint32_t CTRL_SET; /**< Control */
+ __IOM uint32_t CMD_SET; /**< Command */
+ __IOM uint32_t TIMER_SET; /**< Timer */
+ __IM uint32_t STATUS_SET; /**< Status */
+ __IOM uint32_t MASKREQ_SET; /**< Mask Request */
+ __IM uint32_t STMASK_SET; /**< Scan Table Mask */
+ __IOM uint32_t CMPTHR_SET; /**< Digital Window Comparator Threshold */
+ __IOM uint32_t IF_SET; /**< Interrupt Flags */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable */
+ __IOM uint32_t TRIGGER_SET; /**< Trigger */
+ uint32_t RESERVED9[1U]; /**< Reserved for future use */
+ uint32_t RESERVED10[5U]; /**< Reserved for future use */
+ IADC_CFG_TypeDef CFG_SET[2U]; /**< CFG */
+ uint32_t RESERVED11[2U]; /**< Reserved for future use */
+ __IOM uint32_t SINGLEFIFOCFG_SET; /**< Single FIFO Configuration */
+ __IM uint32_t SINGLEFIFODATA_SET; /**< Single FIFO DATA */
+ __IM uint32_t SINGLEFIFOSTAT_SET; /**< Single FIFO Status */
+ __IM uint32_t SINGLEDATA_SET; /**< Single Data */
+ __IOM uint32_t SCANFIFOCFG_SET; /**< Scan FIFO Configuration */
+ __IM uint32_t SCANFIFODATA_SET; /**< Scan FIFO Read Data */
+ __IM uint32_t SCANFIFOSTAT_SET; /**< Scan FIFO Status */
+ __IM uint32_t SCANDATA_SET; /**< Scan Data */
+ uint32_t RESERVED12[1U]; /**< Reserved for future use */
+ uint32_t RESERVED13[1U]; /**< Reserved for future use */
+ __IOM uint32_t SINGLE_SET; /**< Single Queue Port Selection */
+ uint32_t RESERVED14[1U]; /**< Reserved for future use */
+ IADC_SCANTABLE_TypeDef SCANTABLE_SET[16U]; /**< SCANTABLE */
+ uint32_t RESERVED15[4U]; /**< Reserved for future use */
+ uint32_t RESERVED16[1U]; /**< Reserved for future use */
+ uint32_t RESERVED17[963U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IPVERSION */
+ __IOM uint32_t EN_CLR; /**< Enable */
+ __IOM uint32_t CTRL_CLR; /**< Control */
+ __IOM uint32_t CMD_CLR; /**< Command */
+ __IOM uint32_t TIMER_CLR; /**< Timer */
+ __IM uint32_t STATUS_CLR; /**< Status */
+ __IOM uint32_t MASKREQ_CLR; /**< Mask Request */
+ __IM uint32_t STMASK_CLR; /**< Scan Table Mask */
+ __IOM uint32_t CMPTHR_CLR; /**< Digital Window Comparator Threshold */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flags */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable */
+ __IOM uint32_t TRIGGER_CLR; /**< Trigger */
+ uint32_t RESERVED18[1U]; /**< Reserved for future use */
+ uint32_t RESERVED19[5U]; /**< Reserved for future use */
+ IADC_CFG_TypeDef CFG_CLR[2U]; /**< CFG */
+ uint32_t RESERVED20[2U]; /**< Reserved for future use */
+ __IOM uint32_t SINGLEFIFOCFG_CLR; /**< Single FIFO Configuration */
+ __IM uint32_t SINGLEFIFODATA_CLR; /**< Single FIFO DATA */
+ __IM uint32_t SINGLEFIFOSTAT_CLR; /**< Single FIFO Status */
+ __IM uint32_t SINGLEDATA_CLR; /**< Single Data */
+ __IOM uint32_t SCANFIFOCFG_CLR; /**< Scan FIFO Configuration */
+ __IM uint32_t SCANFIFODATA_CLR; /**< Scan FIFO Read Data */
+ __IM uint32_t SCANFIFOSTAT_CLR; /**< Scan FIFO Status */
+ __IM uint32_t SCANDATA_CLR; /**< Scan Data */
+ uint32_t RESERVED21[1U]; /**< Reserved for future use */
+ uint32_t RESERVED22[1U]; /**< Reserved for future use */
+ __IOM uint32_t SINGLE_CLR; /**< Single Queue Port Selection */
+ uint32_t RESERVED23[1U]; /**< Reserved for future use */
+ IADC_SCANTABLE_TypeDef SCANTABLE_CLR[16U]; /**< SCANTABLE */
+ uint32_t RESERVED24[4U]; /**< Reserved for future use */
+ uint32_t RESERVED25[1U]; /**< Reserved for future use */
+ uint32_t RESERVED26[963U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IPVERSION */
+ __IOM uint32_t EN_TGL; /**< Enable */
+ __IOM uint32_t CTRL_TGL; /**< Control */
+ __IOM uint32_t CMD_TGL; /**< Command */
+ __IOM uint32_t TIMER_TGL; /**< Timer */
+ __IM uint32_t STATUS_TGL; /**< Status */
+ __IOM uint32_t MASKREQ_TGL; /**< Mask Request */
+ __IM uint32_t STMASK_TGL; /**< Scan Table Mask */
+ __IOM uint32_t CMPTHR_TGL; /**< Digital Window Comparator Threshold */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flags */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable */
+ __IOM uint32_t TRIGGER_TGL; /**< Trigger */
+ uint32_t RESERVED27[1U]; /**< Reserved for future use */
+ uint32_t RESERVED28[5U]; /**< Reserved for future use */
+ IADC_CFG_TypeDef CFG_TGL[2U]; /**< CFG */
+ uint32_t RESERVED29[2U]; /**< Reserved for future use */
+ __IOM uint32_t SINGLEFIFOCFG_TGL; /**< Single FIFO Configuration */
+ __IM uint32_t SINGLEFIFODATA_TGL; /**< Single FIFO DATA */
+ __IM uint32_t SINGLEFIFOSTAT_TGL; /**< Single FIFO Status */
+ __IM uint32_t SINGLEDATA_TGL; /**< Single Data */
+ __IOM uint32_t SCANFIFOCFG_TGL; /**< Scan FIFO Configuration */
+ __IM uint32_t SCANFIFODATA_TGL; /**< Scan FIFO Read Data */
+ __IM uint32_t SCANFIFOSTAT_TGL; /**< Scan FIFO Status */
+ __IM uint32_t SCANDATA_TGL; /**< Scan Data */
+ uint32_t RESERVED30[1U]; /**< Reserved for future use */
+ uint32_t RESERVED31[1U]; /**< Reserved for future use */
+ __IOM uint32_t SINGLE_TGL; /**< Single Queue Port Selection */
+ uint32_t RESERVED32[1U]; /**< Reserved for future use */
+ IADC_SCANTABLE_TypeDef SCANTABLE_TGL[16U]; /**< SCANTABLE */
+ uint32_t RESERVED33[4U]; /**< Reserved for future use */
+ uint32_t RESERVED34[1U]; /**< Reserved for future use */
+} IADC_TypeDef;
+/** @} End of group EFR32MG24_IADC */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_IADC
+ * @{
+ * @defgroup EFR32MG24_IADC_BitFields IADC Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for IADC IPVERSION */
+#define _IADC_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for IADC_IPVERSION */
+#define _IADC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for IADC_IPVERSION */
+#define _IADC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for IADC_IPVERSION */
+#define _IADC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_IPVERSION */
+#define _IADC_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_IPVERSION */
+#define IADC_IPVERSION_IPVERSION_DEFAULT (_IADC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IPVERSION */
+
+/* Bit fields for IADC EN */
+#define _IADC_EN_RESETVALUE 0x00000000UL /**< Default value for IADC_EN */
+#define _IADC_EN_MASK 0x00000003UL /**< Mask for IADC_EN */
+#define IADC_EN_EN (0x1UL << 0) /**< Enable IADC Module */
+#define _IADC_EN_EN_SHIFT 0 /**< Shift value for IADC_EN */
+#define _IADC_EN_EN_MASK 0x1UL /**< Bit mask for IADC_EN */
+#define _IADC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_EN */
+#define _IADC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for IADC_EN */
+#define _IADC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for IADC_EN */
+#define IADC_EN_EN_DEFAULT (_IADC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_EN */
+#define IADC_EN_EN_DISABLE (_IADC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for IADC_EN */
+#define IADC_EN_EN_ENABLE (_IADC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for IADC_EN */
+#define IADC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */
+#define _IADC_EN_DISABLING_SHIFT 1 /**< Shift value for IADC_DISABLING */
+#define _IADC_EN_DISABLING_MASK 0x2UL /**< Bit mask for IADC_DISABLING */
+#define _IADC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_EN */
+#define IADC_EN_DISABLING_DEFAULT (_IADC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_EN */
+
+/* Bit fields for IADC CTRL */
+#define _IADC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IADC_CTRL */
+#define _IADC_CTRL_MASK 0x707F003FUL /**< Mask for IADC_CTRL */
+#define IADC_CTRL_EM23WUCONVERT (0x1UL << 0) /**< EM23 Wakeup on Conversion */
+#define _IADC_CTRL_EM23WUCONVERT_SHIFT 0 /**< Shift value for IADC_EM23WUCONVERT */
+#define _IADC_CTRL_EM23WUCONVERT_MASK 0x1UL /**< Bit mask for IADC_EM23WUCONVERT */
+#define _IADC_CTRL_EM23WUCONVERT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */
+#define _IADC_CTRL_EM23WUCONVERT_WUDVL 0x00000000UL /**< Mode WUDVL for IADC_CTRL */
+#define _IADC_CTRL_EM23WUCONVERT_WUCONVERT 0x00000001UL /**< Mode WUCONVERT for IADC_CTRL */
+#define IADC_CTRL_EM23WUCONVERT_DEFAULT (_IADC_CTRL_EM23WUCONVERT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CTRL */
+#define IADC_CTRL_EM23WUCONVERT_WUDVL (_IADC_CTRL_EM23WUCONVERT_WUDVL << 0) /**< Shifted mode WUDVL for IADC_CTRL */
+#define IADC_CTRL_EM23WUCONVERT_WUCONVERT (_IADC_CTRL_EM23WUCONVERT_WUCONVERT << 0) /**< Shifted mode WUCONVERT for IADC_CTRL */
+#define IADC_CTRL_ADCCLKSUSPEND0 (0x1UL << 1) /**< ADC_CLK Suspend - PRS0 */
+#define _IADC_CTRL_ADCCLKSUSPEND0_SHIFT 1 /**< Shift value for IADC_ADCCLKSUSPEND0 */
+#define _IADC_CTRL_ADCCLKSUSPEND0_MASK 0x2UL /**< Bit mask for IADC_ADCCLKSUSPEND0 */
+#define _IADC_CTRL_ADCCLKSUSPEND0_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */
+#define _IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS 0x00000000UL /**< Mode PRSWUDIS for IADC_CTRL */
+#define _IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN 0x00000001UL /**< Mode PRSWUEN for IADC_CTRL */
+#define IADC_CTRL_ADCCLKSUSPEND0_DEFAULT (_IADC_CTRL_ADCCLKSUSPEND0_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_CTRL */
+#define IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS (_IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS << 1) /**< Shifted mode PRSWUDIS for IADC_CTRL */
+#define IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN (_IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN << 1) /**< Shifted mode PRSWUEN for IADC_CTRL */
+#define IADC_CTRL_ADCCLKSUSPEND1 (0x1UL << 2) /**< ADC_CLK Suspend - PRS1 */
+#define _IADC_CTRL_ADCCLKSUSPEND1_SHIFT 2 /**< Shift value for IADC_ADCCLKSUSPEND1 */
+#define _IADC_CTRL_ADCCLKSUSPEND1_MASK 0x4UL /**< Bit mask for IADC_ADCCLKSUSPEND1 */
+#define _IADC_CTRL_ADCCLKSUSPEND1_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */
+#define _IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS 0x00000000UL /**< Mode PRSWUDIS for IADC_CTRL */
+#define _IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN 0x00000001UL /**< Mode PRSWUEN for IADC_CTRL */
+#define IADC_CTRL_ADCCLKSUSPEND1_DEFAULT (_IADC_CTRL_ADCCLKSUSPEND1_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_CTRL */
+#define IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS (_IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS << 2) /**< Shifted mode PRSWUDIS for IADC_CTRL */
+#define IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN (_IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN << 2) /**< Shifted mode PRSWUEN for IADC_CTRL */
+#define IADC_CTRL_DBGHALT (0x1UL << 3) /**< Debug Halt */
+#define _IADC_CTRL_DBGHALT_SHIFT 3 /**< Shift value for IADC_DBGHALT */
+#define _IADC_CTRL_DBGHALT_MASK 0x8UL /**< Bit mask for IADC_DBGHALT */
+#define _IADC_CTRL_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */
+#define _IADC_CTRL_DBGHALT_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CTRL */
+#define _IADC_CTRL_DBGHALT_HALT 0x00000001UL /**< Mode HALT for IADC_CTRL */
+#define IADC_CTRL_DBGHALT_DEFAULT (_IADC_CTRL_DBGHALT_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_CTRL */
+#define IADC_CTRL_DBGHALT_NORMAL (_IADC_CTRL_DBGHALT_NORMAL << 3) /**< Shifted mode NORMAL for IADC_CTRL */
+#define IADC_CTRL_DBGHALT_HALT (_IADC_CTRL_DBGHALT_HALT << 3) /**< Shifted mode HALT for IADC_CTRL */
+#define _IADC_CTRL_WARMUPMODE_SHIFT 4 /**< Shift value for IADC_WARMUPMODE */
+#define _IADC_CTRL_WARMUPMODE_MASK 0x30UL /**< Bit mask for IADC_WARMUPMODE */
+#define _IADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */
+#define _IADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CTRL */
+#define _IADC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for IADC_CTRL */
+#define _IADC_CTRL_WARMUPMODE_KEEPWARM 0x00000002UL /**< Mode KEEPWARM for IADC_CTRL */
+#define IADC_CTRL_WARMUPMODE_DEFAULT (_IADC_CTRL_WARMUPMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_CTRL */
+#define IADC_CTRL_WARMUPMODE_NORMAL (_IADC_CTRL_WARMUPMODE_NORMAL << 4) /**< Shifted mode NORMAL for IADC_CTRL */
+#define IADC_CTRL_WARMUPMODE_KEEPINSTANDBY (_IADC_CTRL_WARMUPMODE_KEEPINSTANDBY << 4) /**< Shifted mode KEEPINSTANDBY for IADC_CTRL */
+#define IADC_CTRL_WARMUPMODE_KEEPWARM (_IADC_CTRL_WARMUPMODE_KEEPWARM << 4) /**< Shifted mode KEEPWARM for IADC_CTRL */
+#define _IADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for IADC_TIMEBASE */
+#define _IADC_CTRL_TIMEBASE_MASK 0x7F0000UL /**< Bit mask for IADC_TIMEBASE */
+#define _IADC_CTRL_TIMEBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */
+#define IADC_CTRL_TIMEBASE_DEFAULT (_IADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CTRL */
+#define _IADC_CTRL_HSCLKRATE_SHIFT 28 /**< Shift value for IADC_HSCLKRATE */
+#define _IADC_CTRL_HSCLKRATE_MASK 0x70000000UL /**< Bit mask for IADC_HSCLKRATE */
+#define _IADC_CTRL_HSCLKRATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */
+#define _IADC_CTRL_HSCLKRATE_DIV1 0x00000000UL /**< Mode DIV1 for IADC_CTRL */
+#define _IADC_CTRL_HSCLKRATE_DIV2 0x00000001UL /**< Mode DIV2 for IADC_CTRL */
+#define _IADC_CTRL_HSCLKRATE_DIV3 0x00000002UL /**< Mode DIV3 for IADC_CTRL */
+#define _IADC_CTRL_HSCLKRATE_DIV4 0x00000003UL /**< Mode DIV4 for IADC_CTRL */
+#define IADC_CTRL_HSCLKRATE_DEFAULT (_IADC_CTRL_HSCLKRATE_DEFAULT << 28) /**< Shifted mode DEFAULT for IADC_CTRL */
+#define IADC_CTRL_HSCLKRATE_DIV1 (_IADC_CTRL_HSCLKRATE_DIV1 << 28) /**< Shifted mode DIV1 for IADC_CTRL */
+#define IADC_CTRL_HSCLKRATE_DIV2 (_IADC_CTRL_HSCLKRATE_DIV2 << 28) /**< Shifted mode DIV2 for IADC_CTRL */
+#define IADC_CTRL_HSCLKRATE_DIV3 (_IADC_CTRL_HSCLKRATE_DIV3 << 28) /**< Shifted mode DIV3 for IADC_CTRL */
+#define IADC_CTRL_HSCLKRATE_DIV4 (_IADC_CTRL_HSCLKRATE_DIV4 << 28) /**< Shifted mode DIV4 for IADC_CTRL */
+
+/* Bit fields for IADC CMD */
+#define _IADC_CMD_RESETVALUE 0x00000000UL /**< Default value for IADC_CMD */
+#define _IADC_CMD_MASK 0x0303001BUL /**< Mask for IADC_CMD */
+#define IADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Queue Start */
+#define _IADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for IADC_SINGLESTART */
+#define _IADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for IADC_SINGLESTART */
+#define _IADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */
+#define IADC_CMD_SINGLESTART_DEFAULT (_IADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CMD */
+#define IADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Queue Stop */
+#define _IADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for IADC_SINGLESTOP */
+#define _IADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for IADC_SINGLESTOP */
+#define _IADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */
+#define IADC_CMD_SINGLESTOP_DEFAULT (_IADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_CMD */
+#define IADC_CMD_SCANSTART (0x1UL << 3) /**< Scan Queue Start */
+#define _IADC_CMD_SCANSTART_SHIFT 3 /**< Shift value for IADC_SCANSTART */
+#define _IADC_CMD_SCANSTART_MASK 0x8UL /**< Bit mask for IADC_SCANSTART */
+#define _IADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */
+#define IADC_CMD_SCANSTART_DEFAULT (_IADC_CMD_SCANSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_CMD */
+#define IADC_CMD_SCANSTOP (0x1UL << 4) /**< Scan Queue Stop */
+#define _IADC_CMD_SCANSTOP_SHIFT 4 /**< Shift value for IADC_SCANSTOP */
+#define _IADC_CMD_SCANSTOP_MASK 0x10UL /**< Bit mask for IADC_SCANSTOP */
+#define _IADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */
+#define IADC_CMD_SCANSTOP_DEFAULT (_IADC_CMD_SCANSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_CMD */
+#define IADC_CMD_TIMEREN (0x1UL << 16) /**< Timer Enable */
+#define _IADC_CMD_TIMEREN_SHIFT 16 /**< Shift value for IADC_TIMEREN */
+#define _IADC_CMD_TIMEREN_MASK 0x10000UL /**< Bit mask for IADC_TIMEREN */
+#define _IADC_CMD_TIMEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */
+#define IADC_CMD_TIMEREN_DEFAULT (_IADC_CMD_TIMEREN_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CMD */
+#define IADC_CMD_TIMERDIS (0x1UL << 17) /**< Timer Disable */
+#define _IADC_CMD_TIMERDIS_SHIFT 17 /**< Shift value for IADC_TIMERDIS */
+#define _IADC_CMD_TIMERDIS_MASK 0x20000UL /**< Bit mask for IADC_TIMERDIS */
+#define _IADC_CMD_TIMERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */
+#define IADC_CMD_TIMERDIS_DEFAULT (_IADC_CMD_TIMERDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_CMD */
+#define IADC_CMD_SINGLEFIFOFLUSH (0x1UL << 24) /**< Flush the Single FIFO */
+#define _IADC_CMD_SINGLEFIFOFLUSH_SHIFT 24 /**< Shift value for IADC_SINGLEFIFOFLUSH */
+#define _IADC_CMD_SINGLEFIFOFLUSH_MASK 0x1000000UL /**< Bit mask for IADC_SINGLEFIFOFLUSH */
+#define _IADC_CMD_SINGLEFIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */
+#define IADC_CMD_SINGLEFIFOFLUSH_DEFAULT (_IADC_CMD_SINGLEFIFOFLUSH_DEFAULT << 24) /**< Shifted mode DEFAULT for IADC_CMD */
+#define IADC_CMD_SCANFIFOFLUSH (0x1UL << 25) /**< Flush the Scan FIFO */
+#define _IADC_CMD_SCANFIFOFLUSH_SHIFT 25 /**< Shift value for IADC_SCANFIFOFLUSH */
+#define _IADC_CMD_SCANFIFOFLUSH_MASK 0x2000000UL /**< Bit mask for IADC_SCANFIFOFLUSH */
+#define _IADC_CMD_SCANFIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */
+#define IADC_CMD_SCANFIFOFLUSH_DEFAULT (_IADC_CMD_SCANFIFOFLUSH_DEFAULT << 25) /**< Shifted mode DEFAULT for IADC_CMD */
+
+/* Bit fields for IADC TIMER */
+#define _IADC_TIMER_RESETVALUE 0x00000000UL /**< Default value for IADC_TIMER */
+#define _IADC_TIMER_MASK 0x0000FFFFUL /**< Mask for IADC_TIMER */
+#define _IADC_TIMER_TIMER_SHIFT 0 /**< Shift value for IADC_TIMER */
+#define _IADC_TIMER_TIMER_MASK 0xFFFFUL /**< Bit mask for IADC_TIMER */
+#define _IADC_TIMER_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TIMER */
+#define IADC_TIMER_TIMER_DEFAULT (_IADC_TIMER_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_TIMER */
+
+/* Bit fields for IADC STATUS */
+#define _IADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for IADC_STATUS */
+#define _IADC_STATUS_MASK 0x4131CF5BUL /**< Mask for IADC_STATUS */
+#define IADC_STATUS_SINGLEQEN (0x1UL << 0) /**< Single Queue Enabled */
+#define _IADC_STATUS_SINGLEQEN_SHIFT 0 /**< Shift value for IADC_SINGLEQEN */
+#define _IADC_STATUS_SINGLEQEN_MASK 0x1UL /**< Bit mask for IADC_SINGLEQEN */
+#define _IADC_STATUS_SINGLEQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */
+#define IADC_STATUS_SINGLEQEN_DEFAULT (_IADC_STATUS_SINGLEQEN_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_STATUS */
+#define IADC_STATUS_SINGLEQUEUEPENDING (0x1UL << 1) /**< Single Queue Pending */
+#define _IADC_STATUS_SINGLEQUEUEPENDING_SHIFT 1 /**< Shift value for IADC_SINGLEQUEUEPENDING */
+#define _IADC_STATUS_SINGLEQUEUEPENDING_MASK 0x2UL /**< Bit mask for IADC_SINGLEQUEUEPENDING */
+#define _IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */
+#define IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT (_IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_STATUS */
+#define IADC_STATUS_SCANQEN (0x1UL << 3) /**< Scan Queued Enabled */
+#define _IADC_STATUS_SCANQEN_SHIFT 3 /**< Shift value for IADC_SCANQEN */
+#define _IADC_STATUS_SCANQEN_MASK 0x8UL /**< Bit mask for IADC_SCANQEN */
+#define _IADC_STATUS_SCANQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */
+#define IADC_STATUS_SCANQEN_DEFAULT (_IADC_STATUS_SCANQEN_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_STATUS */
+#define IADC_STATUS_SCANQUEUEPENDING (0x1UL << 4) /**< Scan Queue Pending */
+#define _IADC_STATUS_SCANQUEUEPENDING_SHIFT 4 /**< Shift value for IADC_SCANQUEUEPENDING */
+#define _IADC_STATUS_SCANQUEUEPENDING_MASK 0x10UL /**< Bit mask for IADC_SCANQUEUEPENDING */
+#define _IADC_STATUS_SCANQUEUEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */
+#define IADC_STATUS_SCANQUEUEPENDING_DEFAULT (_IADC_STATUS_SCANQUEUEPENDING_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_STATUS */
+#define IADC_STATUS_CONVERTING (0x1UL << 6) /**< Converting */
+#define _IADC_STATUS_CONVERTING_SHIFT 6 /**< Shift value for IADC_CONVERTING */
+#define _IADC_STATUS_CONVERTING_MASK 0x40UL /**< Bit mask for IADC_CONVERTING */
+#define _IADC_STATUS_CONVERTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */
+#define IADC_STATUS_CONVERTING_DEFAULT (_IADC_STATUS_CONVERTING_DEFAULT << 6) /**< Shifted mode DEFAULT for IADC_STATUS */
+#define IADC_STATUS_SINGLEFIFODV (0x1UL << 8) /**< SINGLEFIFO Data Valid */
+#define _IADC_STATUS_SINGLEFIFODV_SHIFT 8 /**< Shift value for IADC_SINGLEFIFODV */
+#define _IADC_STATUS_SINGLEFIFODV_MASK 0x100UL /**< Bit mask for IADC_SINGLEFIFODV */
+#define _IADC_STATUS_SINGLEFIFODV_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */
+#define IADC_STATUS_SINGLEFIFODV_DEFAULT (_IADC_STATUS_SINGLEFIFODV_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_STATUS */
+#define IADC_STATUS_SCANFIFODV (0x1UL << 9) /**< SCANFIFO Data Valid */
+#define _IADC_STATUS_SCANFIFODV_SHIFT 9 /**< Shift value for IADC_SCANFIFODV */
+#define _IADC_STATUS_SCANFIFODV_MASK 0x200UL /**< Bit mask for IADC_SCANFIFODV */
+#define _IADC_STATUS_SCANFIFODV_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */
+#define IADC_STATUS_SCANFIFODV_DEFAULT (_IADC_STATUS_SCANFIFODV_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_STATUS */
+#define IADC_STATUS_SINGLEFIFOFLUSHING (0x1UL << 14) /**< The Single FIFO is flushing */
+#define _IADC_STATUS_SINGLEFIFOFLUSHING_SHIFT 14 /**< Shift value for IADC_SINGLEFIFOFLUSHING */
+#define _IADC_STATUS_SINGLEFIFOFLUSHING_MASK 0x4000UL /**< Bit mask for IADC_SINGLEFIFOFLUSHING */
+#define _IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */
+#define IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT (_IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT << 14) /**< Shifted mode DEFAULT for IADC_STATUS */
+#define IADC_STATUS_SCANFIFOFLUSHING (0x1UL << 15) /**< The Scan FIFO is flushing */
+#define _IADC_STATUS_SCANFIFOFLUSHING_SHIFT 15 /**< Shift value for IADC_SCANFIFOFLUSHING */
+#define _IADC_STATUS_SCANFIFOFLUSHING_MASK 0x8000UL /**< Bit mask for IADC_SCANFIFOFLUSHING */
+#define _IADC_STATUS_SCANFIFOFLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */
+#define IADC_STATUS_SCANFIFOFLUSHING_DEFAULT (_IADC_STATUS_SCANFIFOFLUSHING_DEFAULT << 15) /**< Shifted mode DEFAULT for IADC_STATUS */
+#define IADC_STATUS_TIMERACTIVE (0x1UL << 16) /**< Timer Active */
+#define _IADC_STATUS_TIMERACTIVE_SHIFT 16 /**< Shift value for IADC_TIMERACTIVE */
+#define _IADC_STATUS_TIMERACTIVE_MASK 0x10000UL /**< Bit mask for IADC_TIMERACTIVE */
+#define _IADC_STATUS_TIMERACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */
+#define IADC_STATUS_TIMERACTIVE_DEFAULT (_IADC_STATUS_TIMERACTIVE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_STATUS */
+#define IADC_STATUS_SINGLEWRITEPENDING (0x1UL << 20) /**< SINGLE write pending */
+#define _IADC_STATUS_SINGLEWRITEPENDING_SHIFT 20 /**< Shift value for IADC_SINGLEWRITEPENDING */
+#define _IADC_STATUS_SINGLEWRITEPENDING_MASK 0x100000UL /**< Bit mask for IADC_SINGLEWRITEPENDING */
+#define _IADC_STATUS_SINGLEWRITEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */
+#define IADC_STATUS_SINGLEWRITEPENDING_DEFAULT (_IADC_STATUS_SINGLEWRITEPENDING_DEFAULT << 20) /**< Shifted mode DEFAULT for IADC_STATUS */
+#define IADC_STATUS_MASKREQWRITEPENDING (0x1UL << 21) /**< MASKREQ write pending */
+#define _IADC_STATUS_MASKREQWRITEPENDING_SHIFT 21 /**< Shift value for IADC_MASKREQWRITEPENDING */
+#define _IADC_STATUS_MASKREQWRITEPENDING_MASK 0x200000UL /**< Bit mask for IADC_MASKREQWRITEPENDING */
+#define _IADC_STATUS_MASKREQWRITEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */
+#define IADC_STATUS_MASKREQWRITEPENDING_DEFAULT (_IADC_STATUS_MASKREQWRITEPENDING_DEFAULT << 21) /**< Shifted mode DEFAULT for IADC_STATUS */
+#define IADC_STATUS_SYNCBUSY (0x1UL << 24) /**< SYNCBUSY */
+#define _IADC_STATUS_SYNCBUSY_SHIFT 24 /**< Shift value for IADC_SYNCBUSY */
+#define _IADC_STATUS_SYNCBUSY_MASK 0x1000000UL /**< Bit mask for IADC_SYNCBUSY */
+#define _IADC_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */
+#define IADC_STATUS_SYNCBUSY_DEFAULT (_IADC_STATUS_SYNCBUSY_DEFAULT << 24) /**< Shifted mode DEFAULT for IADC_STATUS */
+#define IADC_STATUS_ADCWARM (0x1UL << 30) /**< ADCWARM */
+#define _IADC_STATUS_ADCWARM_SHIFT 30 /**< Shift value for IADC_ADCWARM */
+#define _IADC_STATUS_ADCWARM_MASK 0x40000000UL /**< Bit mask for IADC_ADCWARM */
+#define _IADC_STATUS_ADCWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */
+#define IADC_STATUS_ADCWARM_DEFAULT (_IADC_STATUS_ADCWARM_DEFAULT << 30) /**< Shifted mode DEFAULT for IADC_STATUS */
+
+/* Bit fields for IADC MASKREQ */
+#define _IADC_MASKREQ_RESETVALUE 0x00000000UL /**< Default value for IADC_MASKREQ */
+#define _IADC_MASKREQ_MASK 0x0000FFFFUL /**< Mask for IADC_MASKREQ */
+#define _IADC_MASKREQ_MASKREQ_SHIFT 0 /**< Shift value for IADC_MASKREQ */
+#define _IADC_MASKREQ_MASKREQ_MASK 0xFFFFUL /**< Bit mask for IADC_MASKREQ */
+#define _IADC_MASKREQ_MASKREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_MASKREQ */
+#define IADC_MASKREQ_MASKREQ_DEFAULT (_IADC_MASKREQ_MASKREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_MASKREQ */
+
+/* Bit fields for IADC STMASK */
+#define _IADC_STMASK_RESETVALUE 0x00000000UL /**< Default value for IADC_STMASK */
+#define _IADC_STMASK_MASK 0x0000FFFFUL /**< Mask for IADC_STMASK */
+#define _IADC_STMASK_STMASK_SHIFT 0 /**< Shift value for IADC_STMASK */
+#define _IADC_STMASK_STMASK_MASK 0xFFFFUL /**< Bit mask for IADC_STMASK */
+#define _IADC_STMASK_STMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STMASK */
+#define IADC_STMASK_STMASK_DEFAULT (_IADC_STMASK_STMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_STMASK */
+
+/* Bit fields for IADC CMPTHR */
+#define _IADC_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for IADC_CMPTHR */
+#define _IADC_CMPTHR_MASK 0xFFFFFFFFUL /**< Mask for IADC_CMPTHR */
+#define _IADC_CMPTHR_ADLT_SHIFT 0 /**< Shift value for IADC_ADLT */
+#define _IADC_CMPTHR_ADLT_MASK 0xFFFFUL /**< Bit mask for IADC_ADLT */
+#define _IADC_CMPTHR_ADLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMPTHR */
+#define IADC_CMPTHR_ADLT_DEFAULT (_IADC_CMPTHR_ADLT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CMPTHR */
+#define _IADC_CMPTHR_ADGT_SHIFT 16 /**< Shift value for IADC_ADGT */
+#define _IADC_CMPTHR_ADGT_MASK 0xFFFF0000UL /**< Bit mask for IADC_ADGT */
+#define _IADC_CMPTHR_ADGT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMPTHR */
+#define IADC_CMPTHR_ADGT_DEFAULT (_IADC_CMPTHR_ADGT_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CMPTHR */
+
+/* Bit fields for IADC IF */
+#define _IADC_IF_RESETVALUE 0x00000000UL /**< Default value for IADC_IF */
+#define _IADC_IF_MASK 0x800F338FUL /**< Mask for IADC_IF */
+#define IADC_IF_SINGLEFIFODVL (0x1UL << 0) /**< Single FIFO Data Valid Level */
+#define _IADC_IF_SINGLEFIFODVL_SHIFT 0 /**< Shift value for IADC_SINGLEFIFODVL */
+#define _IADC_IF_SINGLEFIFODVL_MASK 0x1UL /**< Bit mask for IADC_SINGLEFIFODVL */
+#define _IADC_IF_SINGLEFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */
+#define IADC_IF_SINGLEFIFODVL_DEFAULT (_IADC_IF_SINGLEFIFODVL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IF */
+#define IADC_IF_SCANFIFODVL (0x1UL << 1) /**< Scan FIFO Data Valid Level */
+#define _IADC_IF_SCANFIFODVL_SHIFT 1 /**< Shift value for IADC_SCANFIFODVL */
+#define _IADC_IF_SCANFIFODVL_MASK 0x2UL /**< Bit mask for IADC_SCANFIFODVL */
+#define _IADC_IF_SCANFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */
+#define IADC_IF_SCANFIFODVL_DEFAULT (_IADC_IF_SCANFIFODVL_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_IF */
+#define IADC_IF_SINGLECMP (0x1UL << 2) /**< Single Result Window Compare */
+#define _IADC_IF_SINGLECMP_SHIFT 2 /**< Shift value for IADC_SINGLECMP */
+#define _IADC_IF_SINGLECMP_MASK 0x4UL /**< Bit mask for IADC_SINGLECMP */
+#define _IADC_IF_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */
+#define IADC_IF_SINGLECMP_DEFAULT (_IADC_IF_SINGLECMP_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_IF */
+#define IADC_IF_SCANCMP (0x1UL << 3) /**< Scan Result Window Compare */
+#define _IADC_IF_SCANCMP_SHIFT 3 /**< Shift value for IADC_SCANCMP */
+#define _IADC_IF_SCANCMP_MASK 0x8UL /**< Bit mask for IADC_SCANCMP */
+#define _IADC_IF_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */
+#define IADC_IF_SCANCMP_DEFAULT (_IADC_IF_SCANCMP_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_IF */
+#define IADC_IF_SCANENTRYDONE (0x1UL << 7) /**< Scan Entry Done */
+#define _IADC_IF_SCANENTRYDONE_SHIFT 7 /**< Shift value for IADC_SCANENTRYDONE */
+#define _IADC_IF_SCANENTRYDONE_MASK 0x80UL /**< Bit mask for IADC_SCANENTRYDONE */
+#define _IADC_IF_SCANENTRYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */
+#define IADC_IF_SCANENTRYDONE_DEFAULT (_IADC_IF_SCANENTRYDONE_DEFAULT << 7) /**< Shifted mode DEFAULT for IADC_IF */
+#define IADC_IF_SCANTABLEDONE (0x1UL << 8) /**< Scan Table Done */
+#define _IADC_IF_SCANTABLEDONE_SHIFT 8 /**< Shift value for IADC_SCANTABLEDONE */
+#define _IADC_IF_SCANTABLEDONE_MASK 0x100UL /**< Bit mask for IADC_SCANTABLEDONE */
+#define _IADC_IF_SCANTABLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */
+#define IADC_IF_SCANTABLEDONE_DEFAULT (_IADC_IF_SCANTABLEDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_IF */
+#define IADC_IF_SINGLEDONE (0x1UL << 9) /**< Single Conversion Done */
+#define _IADC_IF_SINGLEDONE_SHIFT 9 /**< Shift value for IADC_SINGLEDONE */
+#define _IADC_IF_SINGLEDONE_MASK 0x200UL /**< Bit mask for IADC_SINGLEDONE */
+#define _IADC_IF_SINGLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */
+#define IADC_IF_SINGLEDONE_DEFAULT (_IADC_IF_SINGLEDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_IF */
+#define IADC_IF_POLARITYERR (0x1UL << 12) /**< Polarity Error */
+#define _IADC_IF_POLARITYERR_SHIFT 12 /**< Shift value for IADC_POLARITYERR */
+#define _IADC_IF_POLARITYERR_MASK 0x1000UL /**< Bit mask for IADC_POLARITYERR */
+#define _IADC_IF_POLARITYERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */
+#define IADC_IF_POLARITYERR_DEFAULT (_IADC_IF_POLARITYERR_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_IF */
+#define IADC_IF_PORTALLOCERR (0x1UL << 13) /**< Port Allocation Error */
+#define _IADC_IF_PORTALLOCERR_SHIFT 13 /**< Shift value for IADC_PORTALLOCERR */
+#define _IADC_IF_PORTALLOCERR_MASK 0x2000UL /**< Bit mask for IADC_PORTALLOCERR */
+#define _IADC_IF_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */
+#define IADC_IF_PORTALLOCERR_DEFAULT (_IADC_IF_PORTALLOCERR_DEFAULT << 13) /**< Shifted mode DEFAULT for IADC_IF */
+#define IADC_IF_SINGLEFIFOOF (0x1UL << 16) /**< Single FIFO Overflow */
+#define _IADC_IF_SINGLEFIFOOF_SHIFT 16 /**< Shift value for IADC_SINGLEFIFOOF */
+#define _IADC_IF_SINGLEFIFOOF_MASK 0x10000UL /**< Bit mask for IADC_SINGLEFIFOOF */
+#define _IADC_IF_SINGLEFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */
+#define IADC_IF_SINGLEFIFOOF_DEFAULT (_IADC_IF_SINGLEFIFOOF_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_IF */
+#define IADC_IF_SCANFIFOOF (0x1UL << 17) /**< Scan FIFO Overflow */
+#define _IADC_IF_SCANFIFOOF_SHIFT 17 /**< Shift value for IADC_SCANFIFOOF */
+#define _IADC_IF_SCANFIFOOF_MASK 0x20000UL /**< Bit mask for IADC_SCANFIFOOF */
+#define _IADC_IF_SCANFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */
+#define IADC_IF_SCANFIFOOF_DEFAULT (_IADC_IF_SCANFIFOOF_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_IF */
+#define IADC_IF_SINGLEFIFOUF (0x1UL << 18) /**< Single FIFO Underflow */
+#define _IADC_IF_SINGLEFIFOUF_SHIFT 18 /**< Shift value for IADC_SINGLEFIFOUF */
+#define _IADC_IF_SINGLEFIFOUF_MASK 0x40000UL /**< Bit mask for IADC_SINGLEFIFOUF */
+#define _IADC_IF_SINGLEFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */
+#define IADC_IF_SINGLEFIFOUF_DEFAULT (_IADC_IF_SINGLEFIFOUF_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_IF */
+#define IADC_IF_SCANFIFOUF (0x1UL << 19) /**< Scan FIFO Underflow */
+#define _IADC_IF_SCANFIFOUF_SHIFT 19 /**< Shift value for IADC_SCANFIFOUF */
+#define _IADC_IF_SCANFIFOUF_MASK 0x80000UL /**< Bit mask for IADC_SCANFIFOUF */
+#define _IADC_IF_SCANFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */
+#define IADC_IF_SCANFIFOUF_DEFAULT (_IADC_IF_SCANFIFOUF_DEFAULT << 19) /**< Shifted mode DEFAULT for IADC_IF */
+#define IADC_IF_EM23ABORTERROR (0x1UL << 31) /**< EM2/3 Abort Error */
+#define _IADC_IF_EM23ABORTERROR_SHIFT 31 /**< Shift value for IADC_EM23ABORTERROR */
+#define _IADC_IF_EM23ABORTERROR_MASK 0x80000000UL /**< Bit mask for IADC_EM23ABORTERROR */
+#define _IADC_IF_EM23ABORTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */
+#define IADC_IF_EM23ABORTERROR_DEFAULT (_IADC_IF_EM23ABORTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_IF */
+
+/* Bit fields for IADC IEN */
+#define _IADC_IEN_RESETVALUE 0x00000000UL /**< Default value for IADC_IEN */
+#define _IADC_IEN_MASK 0x800F338FUL /**< Mask for IADC_IEN */
+#define IADC_IEN_SINGLEFIFODVL (0x1UL << 0) /**< Single FIFO Data Valid Level Enable */
+#define _IADC_IEN_SINGLEFIFODVL_SHIFT 0 /**< Shift value for IADC_SINGLEFIFODVL */
+#define _IADC_IEN_SINGLEFIFODVL_MASK 0x1UL /**< Bit mask for IADC_SINGLEFIFODVL */
+#define _IADC_IEN_SINGLEFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */
+#define IADC_IEN_SINGLEFIFODVL_DEFAULT (_IADC_IEN_SINGLEFIFODVL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IEN */
+#define IADC_IEN_SCANFIFODVL (0x1UL << 1) /**< Scan FIFO Data Valid Level Enable */
+#define _IADC_IEN_SCANFIFODVL_SHIFT 1 /**< Shift value for IADC_SCANFIFODVL */
+#define _IADC_IEN_SCANFIFODVL_MASK 0x2UL /**< Bit mask for IADC_SCANFIFODVL */
+#define _IADC_IEN_SCANFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */
+#define IADC_IEN_SCANFIFODVL_DEFAULT (_IADC_IEN_SCANFIFODVL_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_IEN */
+#define IADC_IEN_SINGLECMP (0x1UL << 2) /**< Single Result Window Compare Enable */
+#define _IADC_IEN_SINGLECMP_SHIFT 2 /**< Shift value for IADC_SINGLECMP */
+#define _IADC_IEN_SINGLECMP_MASK 0x4UL /**< Bit mask for IADC_SINGLECMP */
+#define _IADC_IEN_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */
+#define IADC_IEN_SINGLECMP_DEFAULT (_IADC_IEN_SINGLECMP_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_IEN */
+#define IADC_IEN_SCANCMP (0x1UL << 3) /**< Scan Result Window Compare Enable */
+#define _IADC_IEN_SCANCMP_SHIFT 3 /**< Shift value for IADC_SCANCMP */
+#define _IADC_IEN_SCANCMP_MASK 0x8UL /**< Bit mask for IADC_SCANCMP */
+#define _IADC_IEN_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */
+#define IADC_IEN_SCANCMP_DEFAULT (_IADC_IEN_SCANCMP_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_IEN */
+#define IADC_IEN_SCANENTRYDONE (0x1UL << 7) /**< Scan Entry Done Enable */
+#define _IADC_IEN_SCANENTRYDONE_SHIFT 7 /**< Shift value for IADC_SCANENTRYDONE */
+#define _IADC_IEN_SCANENTRYDONE_MASK 0x80UL /**< Bit mask for IADC_SCANENTRYDONE */
+#define _IADC_IEN_SCANENTRYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */
+#define IADC_IEN_SCANENTRYDONE_DEFAULT (_IADC_IEN_SCANENTRYDONE_DEFAULT << 7) /**< Shifted mode DEFAULT for IADC_IEN */
+#define IADC_IEN_SCANTABLEDONE (0x1UL << 8) /**< Scan Table Done Enable */
+#define _IADC_IEN_SCANTABLEDONE_SHIFT 8 /**< Shift value for IADC_SCANTABLEDONE */
+#define _IADC_IEN_SCANTABLEDONE_MASK 0x100UL /**< Bit mask for IADC_SCANTABLEDONE */
+#define _IADC_IEN_SCANTABLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */
+#define IADC_IEN_SCANTABLEDONE_DEFAULT (_IADC_IEN_SCANTABLEDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_IEN */
+#define IADC_IEN_SINGLEDONE (0x1UL << 9) /**< Single Conversion Done Enable */
+#define _IADC_IEN_SINGLEDONE_SHIFT 9 /**< Shift value for IADC_SINGLEDONE */
+#define _IADC_IEN_SINGLEDONE_MASK 0x200UL /**< Bit mask for IADC_SINGLEDONE */
+#define _IADC_IEN_SINGLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */
+#define IADC_IEN_SINGLEDONE_DEFAULT (_IADC_IEN_SINGLEDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_IEN */
+#define IADC_IEN_POLARITYERR (0x1UL << 12) /**< Polarity Error Enable */
+#define _IADC_IEN_POLARITYERR_SHIFT 12 /**< Shift value for IADC_POLARITYERR */
+#define _IADC_IEN_POLARITYERR_MASK 0x1000UL /**< Bit mask for IADC_POLARITYERR */
+#define _IADC_IEN_POLARITYERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */
+#define IADC_IEN_POLARITYERR_DEFAULT (_IADC_IEN_POLARITYERR_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_IEN */
+#define IADC_IEN_PORTALLOCERR (0x1UL << 13) /**< Port Allocation Error Enable */
+#define _IADC_IEN_PORTALLOCERR_SHIFT 13 /**< Shift value for IADC_PORTALLOCERR */
+#define _IADC_IEN_PORTALLOCERR_MASK 0x2000UL /**< Bit mask for IADC_PORTALLOCERR */
+#define _IADC_IEN_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */
+#define IADC_IEN_PORTALLOCERR_DEFAULT (_IADC_IEN_PORTALLOCERR_DEFAULT << 13) /**< Shifted mode DEFAULT for IADC_IEN */
+#define IADC_IEN_SINGLEFIFOOF (0x1UL << 16) /**< Single FIFO Overflow Enable */
+#define _IADC_IEN_SINGLEFIFOOF_SHIFT 16 /**< Shift value for IADC_SINGLEFIFOOF */
+#define _IADC_IEN_SINGLEFIFOOF_MASK 0x10000UL /**< Bit mask for IADC_SINGLEFIFOOF */
+#define _IADC_IEN_SINGLEFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */
+#define IADC_IEN_SINGLEFIFOOF_DEFAULT (_IADC_IEN_SINGLEFIFOOF_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_IEN */
+#define IADC_IEN_SCANFIFOOF (0x1UL << 17) /**< Scan FIFO Overflow Enable */
+#define _IADC_IEN_SCANFIFOOF_SHIFT 17 /**< Shift value for IADC_SCANFIFOOF */
+#define _IADC_IEN_SCANFIFOOF_MASK 0x20000UL /**< Bit mask for IADC_SCANFIFOOF */
+#define _IADC_IEN_SCANFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */
+#define IADC_IEN_SCANFIFOOF_DEFAULT (_IADC_IEN_SCANFIFOOF_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_IEN */
+#define IADC_IEN_SINGLEFIFOUF (0x1UL << 18) /**< Single FIFO Underflow Enable */
+#define _IADC_IEN_SINGLEFIFOUF_SHIFT 18 /**< Shift value for IADC_SINGLEFIFOUF */
+#define _IADC_IEN_SINGLEFIFOUF_MASK 0x40000UL /**< Bit mask for IADC_SINGLEFIFOUF */
+#define _IADC_IEN_SINGLEFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */
+#define IADC_IEN_SINGLEFIFOUF_DEFAULT (_IADC_IEN_SINGLEFIFOUF_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_IEN */
+#define IADC_IEN_SCANFIFOUF (0x1UL << 19) /**< Scan FIFO Underflow Enable */
+#define _IADC_IEN_SCANFIFOUF_SHIFT 19 /**< Shift value for IADC_SCANFIFOUF */
+#define _IADC_IEN_SCANFIFOUF_MASK 0x80000UL /**< Bit mask for IADC_SCANFIFOUF */
+#define _IADC_IEN_SCANFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */
+#define IADC_IEN_SCANFIFOUF_DEFAULT (_IADC_IEN_SCANFIFOUF_DEFAULT << 19) /**< Shifted mode DEFAULT for IADC_IEN */
+#define IADC_IEN_EM23ABORTERROR (0x1UL << 31) /**< EM2/3 Abort Error Enable */
+#define _IADC_IEN_EM23ABORTERROR_SHIFT 31 /**< Shift value for IADC_EM23ABORTERROR */
+#define _IADC_IEN_EM23ABORTERROR_MASK 0x80000000UL /**< Bit mask for IADC_EM23ABORTERROR */
+#define _IADC_IEN_EM23ABORTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */
+#define IADC_IEN_EM23ABORTERROR_DEFAULT (_IADC_IEN_EM23ABORTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_IEN */
+
+/* Bit fields for IADC TRIGGER */
+#define _IADC_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for IADC_TRIGGER */
+#define _IADC_TRIGGER_MASK 0x00011717UL /**< Mask for IADC_TRIGGER */
+#define _IADC_TRIGGER_SCANTRIGSEL_SHIFT 0 /**< Shift value for IADC_SCANTRIGSEL */
+#define _IADC_TRIGGER_SCANTRIGSEL_MASK 0x7UL /**< Bit mask for IADC_SCANTRIGSEL */
+#define _IADC_TRIGGER_SCANTRIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */
+#define _IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for IADC_TRIGGER */
+#define _IADC_TRIGGER_SCANTRIGSEL_TIMER 0x00000001UL /**< Mode TIMER for IADC_TRIGGER */
+#define _IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP 0x00000002UL /**< Mode PRSCLKGRP for IADC_TRIGGER */
+#define _IADC_TRIGGER_SCANTRIGSEL_PRSPOS 0x00000003UL /**< Mode PRSPOS for IADC_TRIGGER */
+#define _IADC_TRIGGER_SCANTRIGSEL_PRSNEG 0x00000004UL /**< Mode PRSNEG for IADC_TRIGGER */
+#define IADC_TRIGGER_SCANTRIGSEL_DEFAULT (_IADC_TRIGGER_SCANTRIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_TRIGGER */
+#define IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE (_IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE << 0) /**< Shifted mode IMMEDIATE for IADC_TRIGGER */
+#define IADC_TRIGGER_SCANTRIGSEL_TIMER (_IADC_TRIGGER_SCANTRIGSEL_TIMER << 0) /**< Shifted mode TIMER for IADC_TRIGGER */
+#define IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP (_IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP << 0) /**< Shifted mode PRSCLKGRP for IADC_TRIGGER */
+#define IADC_TRIGGER_SCANTRIGSEL_PRSPOS (_IADC_TRIGGER_SCANTRIGSEL_PRSPOS << 0) /**< Shifted mode PRSPOS for IADC_TRIGGER */
+#define IADC_TRIGGER_SCANTRIGSEL_PRSNEG (_IADC_TRIGGER_SCANTRIGSEL_PRSNEG << 0) /**< Shifted mode PRSNEG for IADC_TRIGGER */
+#define IADC_TRIGGER_SCANTRIGACTION (0x1UL << 4) /**< Scan Trigger Action */
+#define _IADC_TRIGGER_SCANTRIGACTION_SHIFT 4 /**< Shift value for IADC_SCANTRIGACTION */
+#define _IADC_TRIGGER_SCANTRIGACTION_MASK 0x10UL /**< Bit mask for IADC_SCANTRIGACTION */
+#define _IADC_TRIGGER_SCANTRIGACTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */
+#define _IADC_TRIGGER_SCANTRIGACTION_ONCE 0x00000000UL /**< Mode ONCE for IADC_TRIGGER */
+#define _IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS 0x00000001UL /**< Mode CONTINUOUS for IADC_TRIGGER */
+#define IADC_TRIGGER_SCANTRIGACTION_DEFAULT (_IADC_TRIGGER_SCANTRIGACTION_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_TRIGGER */
+#define IADC_TRIGGER_SCANTRIGACTION_ONCE (_IADC_TRIGGER_SCANTRIGACTION_ONCE << 4) /**< Shifted mode ONCE for IADC_TRIGGER */
+#define IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS (_IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS << 4) /**< Shifted mode CONTINUOUS for IADC_TRIGGER */
+#define _IADC_TRIGGER_SINGLETRIGSEL_SHIFT 8 /**< Shift value for IADC_SINGLETRIGSEL */
+#define _IADC_TRIGGER_SINGLETRIGSEL_MASK 0x700UL /**< Bit mask for IADC_SINGLETRIGSEL */
+#define _IADC_TRIGGER_SINGLETRIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */
+#define _IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for IADC_TRIGGER */
+#define _IADC_TRIGGER_SINGLETRIGSEL_TIMER 0x00000001UL /**< Mode TIMER for IADC_TRIGGER */
+#define _IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP 0x00000002UL /**< Mode PRSCLKGRP for IADC_TRIGGER */
+#define _IADC_TRIGGER_SINGLETRIGSEL_PRSPOS 0x00000003UL /**< Mode PRSPOS for IADC_TRIGGER */
+#define _IADC_TRIGGER_SINGLETRIGSEL_PRSNEG 0x00000004UL /**< Mode PRSNEG for IADC_TRIGGER */
+#define IADC_TRIGGER_SINGLETRIGSEL_DEFAULT (_IADC_TRIGGER_SINGLETRIGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_TRIGGER */
+#define IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE (_IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE << 8) /**< Shifted mode IMMEDIATE for IADC_TRIGGER */
+#define IADC_TRIGGER_SINGLETRIGSEL_TIMER (_IADC_TRIGGER_SINGLETRIGSEL_TIMER << 8) /**< Shifted mode TIMER for IADC_TRIGGER */
+#define IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP (_IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP << 8) /**< Shifted mode PRSCLKGRP for IADC_TRIGGER */
+#define IADC_TRIGGER_SINGLETRIGSEL_PRSPOS (_IADC_TRIGGER_SINGLETRIGSEL_PRSPOS << 8) /**< Shifted mode PRSPOS for IADC_TRIGGER */
+#define IADC_TRIGGER_SINGLETRIGSEL_PRSNEG (_IADC_TRIGGER_SINGLETRIGSEL_PRSNEG << 8) /**< Shifted mode PRSNEG for IADC_TRIGGER */
+#define IADC_TRIGGER_SINGLETRIGACTION (0x1UL << 12) /**< Single Trigger Action */
+#define _IADC_TRIGGER_SINGLETRIGACTION_SHIFT 12 /**< Shift value for IADC_SINGLETRIGACTION */
+#define _IADC_TRIGGER_SINGLETRIGACTION_MASK 0x1000UL /**< Bit mask for IADC_SINGLETRIGACTION */
+#define _IADC_TRIGGER_SINGLETRIGACTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */
+#define _IADC_TRIGGER_SINGLETRIGACTION_ONCE 0x00000000UL /**< Mode ONCE for IADC_TRIGGER */
+#define _IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS 0x00000001UL /**< Mode CONTINUOUS for IADC_TRIGGER */
+#define IADC_TRIGGER_SINGLETRIGACTION_DEFAULT (_IADC_TRIGGER_SINGLETRIGACTION_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_TRIGGER */
+#define IADC_TRIGGER_SINGLETRIGACTION_ONCE (_IADC_TRIGGER_SINGLETRIGACTION_ONCE << 12) /**< Shifted mode ONCE for IADC_TRIGGER */
+#define IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS (_IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS << 12) /**< Shifted mode CONTINUOUS for IADC_TRIGGER */
+#define IADC_TRIGGER_SINGLETAILGATE (0x1UL << 16) /**< Single Tailgate Enable */
+#define _IADC_TRIGGER_SINGLETAILGATE_SHIFT 16 /**< Shift value for IADC_SINGLETAILGATE */
+#define _IADC_TRIGGER_SINGLETAILGATE_MASK 0x10000UL /**< Bit mask for IADC_SINGLETAILGATE */
+#define _IADC_TRIGGER_SINGLETAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */
+#define _IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF 0x00000000UL /**< Mode TAILGATEOFF for IADC_TRIGGER */
+#define _IADC_TRIGGER_SINGLETAILGATE_TAILGATEON 0x00000001UL /**< Mode TAILGATEON for IADC_TRIGGER */
+#define IADC_TRIGGER_SINGLETAILGATE_DEFAULT (_IADC_TRIGGER_SINGLETAILGATE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_TRIGGER */
+#define IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF (_IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF << 16) /**< Shifted mode TAILGATEOFF for IADC_TRIGGER */
+#define IADC_TRIGGER_SINGLETAILGATE_TAILGATEON (_IADC_TRIGGER_SINGLETAILGATE_TAILGATEON << 16) /**< Shifted mode TAILGATEON for IADC_TRIGGER */
+
+/* Bit fields for IADC CFG */
+#define _IADC_CFG_RESETVALUE 0x00002060UL /**< Default value for IADC_CFG */
+#define _IADC_CFG_MASK 0x30E770FFUL /**< Mask for IADC_CFG */
+#define _IADC_CFG_ADCMODE_SHIFT 0 /**< Shift value for IADC_ADCMODE */
+#define _IADC_CFG_ADCMODE_MASK 0x3UL /**< Bit mask for IADC_ADCMODE */
+#define _IADC_CFG_ADCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */
+#define _IADC_CFG_ADCMODE_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CFG */
+#define _IADC_CFG_ADCMODE_HIGHSPEED 0x00000001UL /**< Mode HIGHSPEED for IADC_CFG */
+#define _IADC_CFG_ADCMODE_HIGHACCURACY 0x00000002UL /**< Mode HIGHACCURACY for IADC_CFG */
+#define IADC_CFG_ADCMODE_DEFAULT (_IADC_CFG_ADCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CFG */
+#define IADC_CFG_ADCMODE_NORMAL (_IADC_CFG_ADCMODE_NORMAL << 0) /**< Shifted mode NORMAL for IADC_CFG */
+#define IADC_CFG_ADCMODE_HIGHSPEED (_IADC_CFG_ADCMODE_HIGHSPEED << 0) /**< Shifted mode HIGHSPEED for IADC_CFG */
+#define IADC_CFG_ADCMODE_HIGHACCURACY (_IADC_CFG_ADCMODE_HIGHACCURACY << 0) /**< Shifted mode HIGHACCURACY for IADC_CFG */
+#define _IADC_CFG_OSRHS_SHIFT 2 /**< Shift value for IADC_OSRHS */
+#define _IADC_CFG_OSRHS_MASK 0x1CUL /**< Bit mask for IADC_OSRHS */
+#define _IADC_CFG_OSRHS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */
+#define _IADC_CFG_OSRHS_HISPD2 0x00000000UL /**< Mode HISPD2 for IADC_CFG */
+#define _IADC_CFG_OSRHS_HISPD4 0x00000001UL /**< Mode HISPD4 for IADC_CFG */
+#define _IADC_CFG_OSRHS_HISPD8 0x00000002UL /**< Mode HISPD8 for IADC_CFG */
+#define _IADC_CFG_OSRHS_HISPD16 0x00000003UL /**< Mode HISPD16 for IADC_CFG */
+#define _IADC_CFG_OSRHS_HISPD32 0x00000004UL /**< Mode HISPD32 for IADC_CFG */
+#define _IADC_CFG_OSRHS_HISPD64 0x00000005UL /**< Mode HISPD64 for IADC_CFG */
+#define IADC_CFG_OSRHS_DEFAULT (_IADC_CFG_OSRHS_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_CFG */
+#define IADC_CFG_OSRHS_HISPD2 (_IADC_CFG_OSRHS_HISPD2 << 2) /**< Shifted mode HISPD2 for IADC_CFG */
+#define IADC_CFG_OSRHS_HISPD4 (_IADC_CFG_OSRHS_HISPD4 << 2) /**< Shifted mode HISPD4 for IADC_CFG */
+#define IADC_CFG_OSRHS_HISPD8 (_IADC_CFG_OSRHS_HISPD8 << 2) /**< Shifted mode HISPD8 for IADC_CFG */
+#define IADC_CFG_OSRHS_HISPD16 (_IADC_CFG_OSRHS_HISPD16 << 2) /**< Shifted mode HISPD16 for IADC_CFG */
+#define IADC_CFG_OSRHS_HISPD32 (_IADC_CFG_OSRHS_HISPD32 << 2) /**< Shifted mode HISPD32 for IADC_CFG */
+#define IADC_CFG_OSRHS_HISPD64 (_IADC_CFG_OSRHS_HISPD64 << 2) /**< Shifted mode HISPD64 for IADC_CFG */
+#define _IADC_CFG_OSRHA_SHIFT 5 /**< Shift value for IADC_OSRHA */
+#define _IADC_CFG_OSRHA_MASK 0xE0UL /**< Bit mask for IADC_OSRHA */
+#define _IADC_CFG_OSRHA_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_CFG */
+#define _IADC_CFG_OSRHA_HIACC16 0x00000000UL /**< Mode HIACC16 for IADC_CFG */
+#define _IADC_CFG_OSRHA_HIACC32 0x00000001UL /**< Mode HIACC32 for IADC_CFG */
+#define _IADC_CFG_OSRHA_HIACC64 0x00000002UL /**< Mode HIACC64 for IADC_CFG */
+#define _IADC_CFG_OSRHA_HIACC92 0x00000003UL /**< Mode HIACC92 for IADC_CFG */
+#define _IADC_CFG_OSRHA_HIACC128 0x00000004UL /**< Mode HIACC128 for IADC_CFG */
+#define _IADC_CFG_OSRHA_HIACC256 0x00000005UL /**< Mode HIACC256 for IADC_CFG */
+#define IADC_CFG_OSRHA_DEFAULT (_IADC_CFG_OSRHA_DEFAULT << 5) /**< Shifted mode DEFAULT for IADC_CFG */
+#define IADC_CFG_OSRHA_HIACC16 (_IADC_CFG_OSRHA_HIACC16 << 5) /**< Shifted mode HIACC16 for IADC_CFG */
+#define IADC_CFG_OSRHA_HIACC32 (_IADC_CFG_OSRHA_HIACC32 << 5) /**< Shifted mode HIACC32 for IADC_CFG */
+#define IADC_CFG_OSRHA_HIACC64 (_IADC_CFG_OSRHA_HIACC64 << 5) /**< Shifted mode HIACC64 for IADC_CFG */
+#define IADC_CFG_OSRHA_HIACC92 (_IADC_CFG_OSRHA_HIACC92 << 5) /**< Shifted mode HIACC92 for IADC_CFG */
+#define IADC_CFG_OSRHA_HIACC128 (_IADC_CFG_OSRHA_HIACC128 << 5) /**< Shifted mode HIACC128 for IADC_CFG */
+#define IADC_CFG_OSRHA_HIACC256 (_IADC_CFG_OSRHA_HIACC256 << 5) /**< Shifted mode HIACC256 for IADC_CFG */
+#define _IADC_CFG_ANALOGGAIN_SHIFT 12 /**< Shift value for IADC_ANALOGGAIN */
+#define _IADC_CFG_ANALOGGAIN_MASK 0x7000UL /**< Bit mask for IADC_ANALOGGAIN */
+#define _IADC_CFG_ANALOGGAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for IADC_CFG */
+#define _IADC_CFG_ANALOGGAIN_ANAGAIN0P5 0x00000001UL /**< Mode ANAGAIN0P5 for IADC_CFG */
+#define _IADC_CFG_ANALOGGAIN_ANAGAIN1 0x00000002UL /**< Mode ANAGAIN1 for IADC_CFG */
+#define _IADC_CFG_ANALOGGAIN_ANAGAIN2 0x00000003UL /**< Mode ANAGAIN2 for IADC_CFG */
+#define _IADC_CFG_ANALOGGAIN_ANAGAIN3 0x00000004UL /**< Mode ANAGAIN3 for IADC_CFG */
+#define _IADC_CFG_ANALOGGAIN_ANAGAIN4 0x00000005UL /**< Mode ANAGAIN4 for IADC_CFG */
+#define IADC_CFG_ANALOGGAIN_DEFAULT (_IADC_CFG_ANALOGGAIN_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_CFG */
+#define IADC_CFG_ANALOGGAIN_ANAGAIN0P5 (_IADC_CFG_ANALOGGAIN_ANAGAIN0P5 << 12) /**< Shifted mode ANAGAIN0P5 for IADC_CFG */
+#define IADC_CFG_ANALOGGAIN_ANAGAIN1 (_IADC_CFG_ANALOGGAIN_ANAGAIN1 << 12) /**< Shifted mode ANAGAIN1 for IADC_CFG */
+#define IADC_CFG_ANALOGGAIN_ANAGAIN2 (_IADC_CFG_ANALOGGAIN_ANAGAIN2 << 12) /**< Shifted mode ANAGAIN2 for IADC_CFG */
+#define IADC_CFG_ANALOGGAIN_ANAGAIN3 (_IADC_CFG_ANALOGGAIN_ANAGAIN3 << 12) /**< Shifted mode ANAGAIN3 for IADC_CFG */
+#define IADC_CFG_ANALOGGAIN_ANAGAIN4 (_IADC_CFG_ANALOGGAIN_ANAGAIN4 << 12) /**< Shifted mode ANAGAIN4 for IADC_CFG */
+#define _IADC_CFG_REFSEL_SHIFT 16 /**< Shift value for IADC_REFSEL */
+#define _IADC_CFG_REFSEL_MASK 0x70000UL /**< Bit mask for IADC_REFSEL */
+#define _IADC_CFG_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */
+#define _IADC_CFG_REFSEL_VBGR 0x00000000UL /**< Mode VBGR for IADC_CFG */
+#define _IADC_CFG_REFSEL_VREF 0x00000001UL /**< Mode VREF for IADC_CFG */
+#define _IADC_CFG_REFSEL_VREF2P5 0x00000002UL /**< Mode VREF2P5 for IADC_CFG */
+#define _IADC_CFG_REFSEL_VDDX 0x00000003UL /**< Mode VDDX for IADC_CFG */
+#define _IADC_CFG_REFSEL_VDDX0P8BUF 0x00000004UL /**< Mode VDDX0P8BUF for IADC_CFG */
+#define IADC_CFG_REFSEL_DEFAULT (_IADC_CFG_REFSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CFG */
+#define IADC_CFG_REFSEL_VBGR (_IADC_CFG_REFSEL_VBGR << 16) /**< Shifted mode VBGR for IADC_CFG */
+#define IADC_CFG_REFSEL_VREF (_IADC_CFG_REFSEL_VREF << 16) /**< Shifted mode VREF for IADC_CFG */
+#define IADC_CFG_REFSEL_VREF2P5 (_IADC_CFG_REFSEL_VREF2P5 << 16) /**< Shifted mode VREF2P5 for IADC_CFG */
+#define IADC_CFG_REFSEL_VDDX (_IADC_CFG_REFSEL_VDDX << 16) /**< Shifted mode VDDX for IADC_CFG */
+#define IADC_CFG_REFSEL_VDDX0P8BUF (_IADC_CFG_REFSEL_VDDX0P8BUF << 16) /**< Shifted mode VDDX0P8BUF for IADC_CFG */
+#define _IADC_CFG_DIGAVG_SHIFT 21 /**< Shift value for IADC_DIGAVG */
+#define _IADC_CFG_DIGAVG_MASK 0xE00000UL /**< Bit mask for IADC_DIGAVG */
+#define _IADC_CFG_DIGAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */
+#define _IADC_CFG_DIGAVG_AVG1 0x00000000UL /**< Mode AVG1 for IADC_CFG */
+#define _IADC_CFG_DIGAVG_AVG2 0x00000001UL /**< Mode AVG2 for IADC_CFG */
+#define _IADC_CFG_DIGAVG_AVG4 0x00000002UL /**< Mode AVG4 for IADC_CFG */
+#define _IADC_CFG_DIGAVG_AVG8 0x00000003UL /**< Mode AVG8 for IADC_CFG */
+#define _IADC_CFG_DIGAVG_AVG16 0x00000004UL /**< Mode AVG16 for IADC_CFG */
+#define IADC_CFG_DIGAVG_DEFAULT (_IADC_CFG_DIGAVG_DEFAULT << 21) /**< Shifted mode DEFAULT for IADC_CFG */
+#define IADC_CFG_DIGAVG_AVG1 (_IADC_CFG_DIGAVG_AVG1 << 21) /**< Shifted mode AVG1 for IADC_CFG */
+#define IADC_CFG_DIGAVG_AVG2 (_IADC_CFG_DIGAVG_AVG2 << 21) /**< Shifted mode AVG2 for IADC_CFG */
+#define IADC_CFG_DIGAVG_AVG4 (_IADC_CFG_DIGAVG_AVG4 << 21) /**< Shifted mode AVG4 for IADC_CFG */
+#define IADC_CFG_DIGAVG_AVG8 (_IADC_CFG_DIGAVG_AVG8 << 21) /**< Shifted mode AVG8 for IADC_CFG */
+#define IADC_CFG_DIGAVG_AVG16 (_IADC_CFG_DIGAVG_AVG16 << 21) /**< Shifted mode AVG16 for IADC_CFG */
+#define _IADC_CFG_TWOSCOMPL_SHIFT 28 /**< Shift value for IADC_TWOSCOMPL */
+#define _IADC_CFG_TWOSCOMPL_MASK 0x30000000UL /**< Bit mask for IADC_TWOSCOMPL */
+#define _IADC_CFG_TWOSCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */
+#define _IADC_CFG_TWOSCOMPL_AUTO 0x00000000UL /**< Mode AUTO for IADC_CFG */
+#define _IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR 0x00000001UL /**< Mode FORCEUNIPOLAR for IADC_CFG */
+#define _IADC_CFG_TWOSCOMPL_FORCEBIPOLAR 0x00000002UL /**< Mode FORCEBIPOLAR for IADC_CFG */
+#define IADC_CFG_TWOSCOMPL_DEFAULT (_IADC_CFG_TWOSCOMPL_DEFAULT << 28) /**< Shifted mode DEFAULT for IADC_CFG */
+#define IADC_CFG_TWOSCOMPL_AUTO (_IADC_CFG_TWOSCOMPL_AUTO << 28) /**< Shifted mode AUTO for IADC_CFG */
+#define IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR (_IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR << 28) /**< Shifted mode FORCEUNIPOLAR for IADC_CFG */
+#define IADC_CFG_TWOSCOMPL_FORCEBIPOLAR (_IADC_CFG_TWOSCOMPL_FORCEBIPOLAR << 28) /**< Shifted mode FORCEBIPOLAR for IADC_CFG */
+
+/* Bit fields for IADC SCALE */
+#define _IADC_SCALE_RESETVALUE 0x8002C000UL /**< Default value for IADC_SCALE */
+#define _IADC_SCALE_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCALE */
+#define _IADC_SCALE_OFFSET_SHIFT 0 /**< Shift value for IADC_OFFSET */
+#define _IADC_SCALE_OFFSET_MASK 0x3FFFFUL /**< Bit mask for IADC_OFFSET */
+#define _IADC_SCALE_OFFSET_DEFAULT 0x0002C000UL /**< Mode DEFAULT for IADC_SCALE */
+#define IADC_SCALE_OFFSET_DEFAULT (_IADC_SCALE_OFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCALE */
+#define _IADC_SCALE_GAIN13LSB_SHIFT 18 /**< Shift value for IADC_GAIN13LSB */
+#define _IADC_SCALE_GAIN13LSB_MASK 0x7FFC0000UL /**< Bit mask for IADC_GAIN13LSB */
+#define _IADC_SCALE_GAIN13LSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCALE */
+#define IADC_SCALE_GAIN13LSB_DEFAULT (_IADC_SCALE_GAIN13LSB_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_SCALE */
+#define IADC_SCALE_GAIN3MSB (0x1UL << 31) /**< Gain 3 MSBs */
+#define _IADC_SCALE_GAIN3MSB_SHIFT 31 /**< Shift value for IADC_GAIN3MSB */
+#define _IADC_SCALE_GAIN3MSB_MASK 0x80000000UL /**< Bit mask for IADC_GAIN3MSB */
+#define _IADC_SCALE_GAIN3MSB_DEFAULT 0x00000001UL /**< Mode DEFAULT for IADC_SCALE */
+#define _IADC_SCALE_GAIN3MSB_GAIN011 0x00000000UL /**< Mode GAIN011 for IADC_SCALE */
+#define _IADC_SCALE_GAIN3MSB_GAIN100 0x00000001UL /**< Mode GAIN100 for IADC_SCALE */
+#define IADC_SCALE_GAIN3MSB_DEFAULT (_IADC_SCALE_GAIN3MSB_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_SCALE */
+#define IADC_SCALE_GAIN3MSB_GAIN011 (_IADC_SCALE_GAIN3MSB_GAIN011 << 31) /**< Shifted mode GAIN011 for IADC_SCALE */
+#define IADC_SCALE_GAIN3MSB_GAIN100 (_IADC_SCALE_GAIN3MSB_GAIN100 << 31) /**< Shifted mode GAIN100 for IADC_SCALE */
+
+/* Bit fields for IADC SCHED */
+#define _IADC_SCHED_RESETVALUE 0x00000000UL /**< Default value for IADC_SCHED */
+#define _IADC_SCHED_MASK 0x000003FFUL /**< Mask for IADC_SCHED */
+#define _IADC_SCHED_PRESCALE_SHIFT 0 /**< Shift value for IADC_PRESCALE */
+#define _IADC_SCHED_PRESCALE_MASK 0x3FFUL /**< Bit mask for IADC_PRESCALE */
+#define _IADC_SCHED_PRESCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCHED */
+#define IADC_SCHED_PRESCALE_DEFAULT (_IADC_SCHED_PRESCALE_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCHED */
+
+/* Bit fields for IADC SINGLEFIFOCFG */
+#define _IADC_SINGLEFIFOCFG_RESETVALUE 0x00000030UL /**< Default value for IADC_SINGLEFIFOCFG */
+#define _IADC_SINGLEFIFOCFG_MASK 0x0000017FUL /**< Mask for IADC_SINGLEFIFOCFG */
+#define _IADC_SINGLEFIFOCFG_ALIGNMENT_SHIFT 0 /**< Shift value for IADC_ALIGNMENT */
+#define _IADC_SINGLEFIFOCFG_ALIGNMENT_MASK 0x7UL /**< Bit mask for IADC_ALIGNMENT */
+#define _IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */
+#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 0x00000000UL /**< Mode RIGHT12 for IADC_SINGLEFIFOCFG */
+#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 0x00000001UL /**< Mode RIGHT16 for IADC_SINGLEFIFOCFG */
+#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 0x00000002UL /**< Mode RIGHT20 for IADC_SINGLEFIFOCFG */
+#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 0x00000003UL /**< Mode LEFT12 for IADC_SINGLEFIFOCFG */
+#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 0x00000004UL /**< Mode LEFT16 for IADC_SINGLEFIFOCFG */
+#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 0x00000005UL /**< Mode LEFT20 for IADC_SINGLEFIFOCFG */
+#define IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT (_IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */
+#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 << 0) /**< Shifted mode RIGHT12 for IADC_SINGLEFIFOCFG */
+#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 << 0) /**< Shifted mode RIGHT16 for IADC_SINGLEFIFOCFG */
+#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 << 0) /**< Shifted mode RIGHT20 for IADC_SINGLEFIFOCFG */
+#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 << 0) /**< Shifted mode LEFT12 for IADC_SINGLEFIFOCFG */
+#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 << 0) /**< Shifted mode LEFT16 for IADC_SINGLEFIFOCFG */
+#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 << 0) /**< Shifted mode LEFT20 for IADC_SINGLEFIFOCFG */
+#define IADC_SINGLEFIFOCFG_SHOWID (0x1UL << 3) /**< Show ID */
+#define _IADC_SINGLEFIFOCFG_SHOWID_SHIFT 3 /**< Shift value for IADC_SHOWID */
+#define _IADC_SINGLEFIFOCFG_SHOWID_MASK 0x8UL /**< Bit mask for IADC_SHOWID */
+#define _IADC_SINGLEFIFOCFG_SHOWID_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */
+#define IADC_SINGLEFIFOCFG_SHOWID_DEFAULT (_IADC_SINGLEFIFOCFG_SHOWID_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */
+#define _IADC_SINGLEFIFOCFG_DVL_SHIFT 4 /**< Shift value for IADC_DVL */
+#define _IADC_SINGLEFIFOCFG_DVL_MASK 0x70UL /**< Bit mask for IADC_DVL */
+#define _IADC_SINGLEFIFOCFG_DVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */
+#define _IADC_SINGLEFIFOCFG_DVL_VALID1 0x00000000UL /**< Mode VALID1 for IADC_SINGLEFIFOCFG */
+#define _IADC_SINGLEFIFOCFG_DVL_VALID2 0x00000001UL /**< Mode VALID2 for IADC_SINGLEFIFOCFG */
+#define _IADC_SINGLEFIFOCFG_DVL_VALID3 0x00000002UL /**< Mode VALID3 for IADC_SINGLEFIFOCFG */
+#define _IADC_SINGLEFIFOCFG_DVL_VALID4 0x00000003UL /**< Mode VALID4 for IADC_SINGLEFIFOCFG */
+#define _IADC_SINGLEFIFOCFG_DVL_VALID5 0x00000004UL /**< Mode VALID5 for IADC_SINGLEFIFOCFG */
+#define _IADC_SINGLEFIFOCFG_DVL_VALID6 0x00000005UL /**< Mode VALID6 for IADC_SINGLEFIFOCFG */
+#define _IADC_SINGLEFIFOCFG_DVL_VALID7 0x00000006UL /**< Mode VALID7 for IADC_SINGLEFIFOCFG */
+#define _IADC_SINGLEFIFOCFG_DVL_VALID8 0x00000007UL /**< Mode VALID8 for IADC_SINGLEFIFOCFG */
+#define IADC_SINGLEFIFOCFG_DVL_DEFAULT (_IADC_SINGLEFIFOCFG_DVL_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */
+#define IADC_SINGLEFIFOCFG_DVL_VALID1 (_IADC_SINGLEFIFOCFG_DVL_VALID1 << 4) /**< Shifted mode VALID1 for IADC_SINGLEFIFOCFG */
+#define IADC_SINGLEFIFOCFG_DVL_VALID2 (_IADC_SINGLEFIFOCFG_DVL_VALID2 << 4) /**< Shifted mode VALID2 for IADC_SINGLEFIFOCFG */
+#define IADC_SINGLEFIFOCFG_DVL_VALID3 (_IADC_SINGLEFIFOCFG_DVL_VALID3 << 4) /**< Shifted mode VALID3 for IADC_SINGLEFIFOCFG */
+#define IADC_SINGLEFIFOCFG_DVL_VALID4 (_IADC_SINGLEFIFOCFG_DVL_VALID4 << 4) /**< Shifted mode VALID4 for IADC_SINGLEFIFOCFG */
+#define IADC_SINGLEFIFOCFG_DVL_VALID5 (_IADC_SINGLEFIFOCFG_DVL_VALID5 << 4) /**< Shifted mode VALID5 for IADC_SINGLEFIFOCFG */
+#define IADC_SINGLEFIFOCFG_DVL_VALID6 (_IADC_SINGLEFIFOCFG_DVL_VALID6 << 4) /**< Shifted mode VALID6 for IADC_SINGLEFIFOCFG */
+#define IADC_SINGLEFIFOCFG_DVL_VALID7 (_IADC_SINGLEFIFOCFG_DVL_VALID7 << 4) /**< Shifted mode VALID7 for IADC_SINGLEFIFOCFG */
+#define IADC_SINGLEFIFOCFG_DVL_VALID8 (_IADC_SINGLEFIFOCFG_DVL_VALID8 << 4) /**< Shifted mode VALID8 for IADC_SINGLEFIFOCFG */
+#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE (0x1UL << 8) /**< Single FIFO DMA wakeup. */
+#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_SHIFT 8 /**< Shift value for IADC_DMAWUFIFOSINGLE */
+#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_MASK 0x100UL /**< Bit mask for IADC_DMAWUFIFOSINGLE */
+#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */
+#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED 0x00000000UL /**< Mode DISABLED for IADC_SINGLEFIFOCFG */
+#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED 0x00000001UL /**< Mode ENABLED for IADC_SINGLEFIFOCFG */
+#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */
+#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED << 8) /**< Shifted mode DISABLED for IADC_SINGLEFIFOCFG*/
+#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED << 8) /**< Shifted mode ENABLED for IADC_SINGLEFIFOCFG */
+
+/* Bit fields for IADC SINGLEFIFODATA */
+#define _IADC_SINGLEFIFODATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEFIFODATA */
+#define _IADC_SINGLEFIFODATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SINGLEFIFODATA */
+#define _IADC_SINGLEFIFODATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */
+#define _IADC_SINGLEFIFODATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */
+#define _IADC_SINGLEFIFODATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFODATA */
+#define IADC_SINGLEFIFODATA_DATA_DEFAULT (_IADC_SINGLEFIFODATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFODATA*/
+
+/* Bit fields for IADC SINGLEFIFOSTAT */
+#define _IADC_SINGLEFIFOSTAT_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEFIFOSTAT */
+#define _IADC_SINGLEFIFOSTAT_MASK 0x0000000FUL /**< Mask for IADC_SINGLEFIFOSTAT */
+#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_SHIFT 0 /**< Shift value for IADC_FIFOREADCNT */
+#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_MASK 0xFUL /**< Bit mask for IADC_FIFOREADCNT */
+#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOSTAT */
+#define IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT (_IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOSTAT*/
+
+/* Bit fields for IADC SINGLEDATA */
+#define _IADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEDATA */
+#define _IADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SINGLEDATA */
+#define _IADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */
+#define _IADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */
+#define _IADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEDATA */
+#define IADC_SINGLEDATA_DATA_DEFAULT (_IADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEDATA */
+
+/* Bit fields for IADC SCANFIFOCFG */
+#define _IADC_SCANFIFOCFG_RESETVALUE 0x00000030UL /**< Default value for IADC_SCANFIFOCFG */
+#define _IADC_SCANFIFOCFG_MASK 0x0000017FUL /**< Mask for IADC_SCANFIFOCFG */
+#define _IADC_SCANFIFOCFG_ALIGNMENT_SHIFT 0 /**< Shift value for IADC_ALIGNMENT */
+#define _IADC_SCANFIFOCFG_ALIGNMENT_MASK 0x7UL /**< Bit mask for IADC_ALIGNMENT */
+#define _IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */
+#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 0x00000000UL /**< Mode RIGHT12 for IADC_SCANFIFOCFG */
+#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 0x00000001UL /**< Mode RIGHT16 for IADC_SCANFIFOCFG */
+#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 0x00000002UL /**< Mode RIGHT20 for IADC_SCANFIFOCFG */
+#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 0x00000003UL /**< Mode LEFT12 for IADC_SCANFIFOCFG */
+#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 0x00000004UL /**< Mode LEFT16 for IADC_SCANFIFOCFG */
+#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 0x00000005UL /**< Mode LEFT20 for IADC_SCANFIFOCFG */
+#define IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT (_IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */
+#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 << 0) /**< Shifted mode RIGHT12 for IADC_SCANFIFOCFG */
+#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 << 0) /**< Shifted mode RIGHT16 for IADC_SCANFIFOCFG */
+#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 << 0) /**< Shifted mode RIGHT20 for IADC_SCANFIFOCFG */
+#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 << 0) /**< Shifted mode LEFT12 for IADC_SCANFIFOCFG */
+#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 << 0) /**< Shifted mode LEFT16 for IADC_SCANFIFOCFG */
+#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 << 0) /**< Shifted mode LEFT20 for IADC_SCANFIFOCFG */
+#define IADC_SCANFIFOCFG_SHOWID (0x1UL << 3) /**< Show ID */
+#define _IADC_SCANFIFOCFG_SHOWID_SHIFT 3 /**< Shift value for IADC_SHOWID */
+#define _IADC_SCANFIFOCFG_SHOWID_MASK 0x8UL /**< Bit mask for IADC_SHOWID */
+#define _IADC_SCANFIFOCFG_SHOWID_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */
+#define IADC_SCANFIFOCFG_SHOWID_DEFAULT (_IADC_SCANFIFOCFG_SHOWID_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */
+#define _IADC_SCANFIFOCFG_DVL_SHIFT 4 /**< Shift value for IADC_DVL */
+#define _IADC_SCANFIFOCFG_DVL_MASK 0x70UL /**< Bit mask for IADC_DVL */
+#define _IADC_SCANFIFOCFG_DVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */
+#define _IADC_SCANFIFOCFG_DVL_VALID1 0x00000000UL /**< Mode VALID1 for IADC_SCANFIFOCFG */
+#define _IADC_SCANFIFOCFG_DVL_VALID2 0x00000001UL /**< Mode VALID2 for IADC_SCANFIFOCFG */
+#define _IADC_SCANFIFOCFG_DVL_VALID3 0x00000002UL /**< Mode VALID3 for IADC_SCANFIFOCFG */
+#define _IADC_SCANFIFOCFG_DVL_VALID4 0x00000003UL /**< Mode VALID4 for IADC_SCANFIFOCFG */
+#define _IADC_SCANFIFOCFG_DVL_VALID5 0x00000004UL /**< Mode VALID5 for IADC_SCANFIFOCFG */
+#define _IADC_SCANFIFOCFG_DVL_VALID6 0x00000005UL /**< Mode VALID6 for IADC_SCANFIFOCFG */
+#define _IADC_SCANFIFOCFG_DVL_VALID7 0x00000006UL /**< Mode VALID7 for IADC_SCANFIFOCFG */
+#define _IADC_SCANFIFOCFG_DVL_VALID8 0x00000007UL /**< Mode VALID8 for IADC_SCANFIFOCFG */
+#define IADC_SCANFIFOCFG_DVL_DEFAULT (_IADC_SCANFIFOCFG_DVL_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */
+#define IADC_SCANFIFOCFG_DVL_VALID1 (_IADC_SCANFIFOCFG_DVL_VALID1 << 4) /**< Shifted mode VALID1 for IADC_SCANFIFOCFG */
+#define IADC_SCANFIFOCFG_DVL_VALID2 (_IADC_SCANFIFOCFG_DVL_VALID2 << 4) /**< Shifted mode VALID2 for IADC_SCANFIFOCFG */
+#define IADC_SCANFIFOCFG_DVL_VALID3 (_IADC_SCANFIFOCFG_DVL_VALID3 << 4) /**< Shifted mode VALID3 for IADC_SCANFIFOCFG */
+#define IADC_SCANFIFOCFG_DVL_VALID4 (_IADC_SCANFIFOCFG_DVL_VALID4 << 4) /**< Shifted mode VALID4 for IADC_SCANFIFOCFG */
+#define IADC_SCANFIFOCFG_DVL_VALID5 (_IADC_SCANFIFOCFG_DVL_VALID5 << 4) /**< Shifted mode VALID5 for IADC_SCANFIFOCFG */
+#define IADC_SCANFIFOCFG_DVL_VALID6 (_IADC_SCANFIFOCFG_DVL_VALID6 << 4) /**< Shifted mode VALID6 for IADC_SCANFIFOCFG */
+#define IADC_SCANFIFOCFG_DVL_VALID7 (_IADC_SCANFIFOCFG_DVL_VALID7 << 4) /**< Shifted mode VALID7 for IADC_SCANFIFOCFG */
+#define IADC_SCANFIFOCFG_DVL_VALID8 (_IADC_SCANFIFOCFG_DVL_VALID8 << 4) /**< Shifted mode VALID8 for IADC_SCANFIFOCFG */
+#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN (0x1UL << 8) /**< Scan FIFO DMA Wakeup */
+#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_SHIFT 8 /**< Shift value for IADC_DMAWUFIFOSCAN */
+#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_MASK 0x100UL /**< Bit mask for IADC_DMAWUFIFOSCAN */
+#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */
+#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED 0x00000000UL /**< Mode DISABLED for IADC_SCANFIFOCFG */
+#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED 0x00000001UL /**< Mode ENABLED for IADC_SCANFIFOCFG */
+#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */
+#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED << 8) /**< Shifted mode DISABLED for IADC_SCANFIFOCFG */
+#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED << 8) /**< Shifted mode ENABLED for IADC_SCANFIFOCFG */
+
+/* Bit fields for IADC SCANFIFODATA */
+#define _IADC_SCANFIFODATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANFIFODATA */
+#define _IADC_SCANFIFODATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCANFIFODATA */
+#define _IADC_SCANFIFODATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */
+#define _IADC_SCANFIFODATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */
+#define _IADC_SCANFIFODATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFODATA */
+#define IADC_SCANFIFODATA_DATA_DEFAULT (_IADC_SCANFIFODATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFODATA */
+
+/* Bit fields for IADC SCANFIFOSTAT */
+#define _IADC_SCANFIFOSTAT_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANFIFOSTAT */
+#define _IADC_SCANFIFOSTAT_MASK 0x0000000FUL /**< Mask for IADC_SCANFIFOSTAT */
+#define _IADC_SCANFIFOSTAT_FIFOREADCNT_SHIFT 0 /**< Shift value for IADC_FIFOREADCNT */
+#define _IADC_SCANFIFOSTAT_FIFOREADCNT_MASK 0xFUL /**< Bit mask for IADC_FIFOREADCNT */
+#define _IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOSTAT */
+#define IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT (_IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFOSTAT */
+
+/* Bit fields for IADC SCANDATA */
+#define _IADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANDATA */
+#define _IADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCANDATA */
+#define _IADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */
+#define _IADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */
+#define _IADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANDATA */
+#define IADC_SCANDATA_DATA_DEFAULT (_IADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANDATA */
+
+/* Bit fields for IADC SINGLE */
+#define _IADC_SINGLE_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLE */
+#define _IADC_SINGLE_MASK 0x0003FFFFUL /**< Mask for IADC_SINGLE */
+#define _IADC_SINGLE_PINNEG_SHIFT 0 /**< Shift value for IADC_PINNEG */
+#define _IADC_SINGLE_PINNEG_MASK 0xFUL /**< Bit mask for IADC_PINNEG */
+#define _IADC_SINGLE_PINNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */
+#define IADC_SINGLE_PINNEG_DEFAULT (_IADC_SINGLE_PINNEG_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLE */
+#define _IADC_SINGLE_PORTNEG_SHIFT 4 /**< Shift value for IADC_PORTNEG */
+#define _IADC_SINGLE_PORTNEG_MASK 0xF0UL /**< Bit mask for IADC_PORTNEG */
+#define _IADC_SINGLE_PORTNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */
+#define _IADC_SINGLE_PORTNEG_GND 0x00000000UL /**< Mode GND for IADC_SINGLE */
+#define _IADC_SINGLE_PORTNEG_DAC1 0x00000002UL /**< Mode DAC1 for IADC_SINGLE */
+#define _IADC_SINGLE_PORTNEG_PADANA1 0x00000004UL /**< Mode PADANA1 for IADC_SINGLE */
+#define _IADC_SINGLE_PORTNEG_PADANA3 0x00000005UL /**< Mode PADANA3 for IADC_SINGLE */
+#define _IADC_SINGLE_PORTNEG_PORTA 0x00000008UL /**< Mode PORTA for IADC_SINGLE */
+#define _IADC_SINGLE_PORTNEG_PORTB 0x00000009UL /**< Mode PORTB for IADC_SINGLE */
+#define _IADC_SINGLE_PORTNEG_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SINGLE */
+#define _IADC_SINGLE_PORTNEG_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SINGLE */
+#define IADC_SINGLE_PORTNEG_DEFAULT (_IADC_SINGLE_PORTNEG_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SINGLE */
+#define IADC_SINGLE_PORTNEG_GND (_IADC_SINGLE_PORTNEG_GND << 4) /**< Shifted mode GND for IADC_SINGLE */
+#define IADC_SINGLE_PORTNEG_DAC1 (_IADC_SINGLE_PORTNEG_DAC1 << 4) /**< Shifted mode DAC1 for IADC_SINGLE */
+#define IADC_SINGLE_PORTNEG_PADANA1 (_IADC_SINGLE_PORTNEG_PADANA1 << 4) /**< Shifted mode PADANA1 for IADC_SINGLE */
+#define IADC_SINGLE_PORTNEG_PADANA3 (_IADC_SINGLE_PORTNEG_PADANA3 << 4) /**< Shifted mode PADANA3 for IADC_SINGLE */
+#define IADC_SINGLE_PORTNEG_PORTA (_IADC_SINGLE_PORTNEG_PORTA << 4) /**< Shifted mode PORTA for IADC_SINGLE */
+#define IADC_SINGLE_PORTNEG_PORTB (_IADC_SINGLE_PORTNEG_PORTB << 4) /**< Shifted mode PORTB for IADC_SINGLE */
+#define IADC_SINGLE_PORTNEG_PORTC (_IADC_SINGLE_PORTNEG_PORTC << 4) /**< Shifted mode PORTC for IADC_SINGLE */
+#define IADC_SINGLE_PORTNEG_PORTD (_IADC_SINGLE_PORTNEG_PORTD << 4) /**< Shifted mode PORTD for IADC_SINGLE */
+#define _IADC_SINGLE_PINPOS_SHIFT 8 /**< Shift value for IADC_PINPOS */
+#define _IADC_SINGLE_PINPOS_MASK 0xF00UL /**< Bit mask for IADC_PINPOS */
+#define _IADC_SINGLE_PINPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */
+#define IADC_SINGLE_PINPOS_DEFAULT (_IADC_SINGLE_PINPOS_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SINGLE */
+#define _IADC_SINGLE_PORTPOS_SHIFT 12 /**< Shift value for IADC_PORTPOS */
+#define _IADC_SINGLE_PORTPOS_MASK 0xF000UL /**< Bit mask for IADC_PORTPOS */
+#define _IADC_SINGLE_PORTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */
+#define _IADC_SINGLE_PORTPOS_GND 0x00000000UL /**< Mode GND for IADC_SINGLE */
+#define _IADC_SINGLE_PORTPOS_SUPPLY 0x00000001UL /**< Mode SUPPLY for IADC_SINGLE */
+#define _IADC_SINGLE_PORTPOS_DAC0 0x00000002UL /**< Mode DAC0 for IADC_SINGLE */
+#define _IADC_SINGLE_PORTPOS_PADANA0 0x00000004UL /**< Mode PADANA0 for IADC_SINGLE */
+#define _IADC_SINGLE_PORTPOS_PADANA2 0x00000005UL /**< Mode PADANA2 for IADC_SINGLE */
+#define _IADC_SINGLE_PORTPOS_PORTA 0x00000008UL /**< Mode PORTA for IADC_SINGLE */
+#define _IADC_SINGLE_PORTPOS_PORTB 0x00000009UL /**< Mode PORTB for IADC_SINGLE */
+#define _IADC_SINGLE_PORTPOS_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SINGLE */
+#define _IADC_SINGLE_PORTPOS_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SINGLE */
+#define IADC_SINGLE_PORTPOS_DEFAULT (_IADC_SINGLE_PORTPOS_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_SINGLE */
+#define IADC_SINGLE_PORTPOS_GND (_IADC_SINGLE_PORTPOS_GND << 12) /**< Shifted mode GND for IADC_SINGLE */
+#define IADC_SINGLE_PORTPOS_SUPPLY (_IADC_SINGLE_PORTPOS_SUPPLY << 12) /**< Shifted mode SUPPLY for IADC_SINGLE */
+#define IADC_SINGLE_PORTPOS_DAC0 (_IADC_SINGLE_PORTPOS_DAC0 << 12) /**< Shifted mode DAC0 for IADC_SINGLE */
+#define IADC_SINGLE_PORTPOS_PADANA0 (_IADC_SINGLE_PORTPOS_PADANA0 << 12) /**< Shifted mode PADANA0 for IADC_SINGLE */
+#define IADC_SINGLE_PORTPOS_PADANA2 (_IADC_SINGLE_PORTPOS_PADANA2 << 12) /**< Shifted mode PADANA2 for IADC_SINGLE */
+#define IADC_SINGLE_PORTPOS_PORTA (_IADC_SINGLE_PORTPOS_PORTA << 12) /**< Shifted mode PORTA for IADC_SINGLE */
+#define IADC_SINGLE_PORTPOS_PORTB (_IADC_SINGLE_PORTPOS_PORTB << 12) /**< Shifted mode PORTB for IADC_SINGLE */
+#define IADC_SINGLE_PORTPOS_PORTC (_IADC_SINGLE_PORTPOS_PORTC << 12) /**< Shifted mode PORTC for IADC_SINGLE */
+#define IADC_SINGLE_PORTPOS_PORTD (_IADC_SINGLE_PORTPOS_PORTD << 12) /**< Shifted mode PORTD for IADC_SINGLE */
+#define IADC_SINGLE_CFG (0x1UL << 16) /**< Configuration Group Select */
+#define _IADC_SINGLE_CFG_SHIFT 16 /**< Shift value for IADC_CFG */
+#define _IADC_SINGLE_CFG_MASK 0x10000UL /**< Bit mask for IADC_CFG */
+#define _IADC_SINGLE_CFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */
+#define _IADC_SINGLE_CFG_CONFIG0 0x00000000UL /**< Mode CONFIG0 for IADC_SINGLE */
+#define _IADC_SINGLE_CFG_CONFIG1 0x00000001UL /**< Mode CONFIG1 for IADC_SINGLE */
+#define IADC_SINGLE_CFG_DEFAULT (_IADC_SINGLE_CFG_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_SINGLE */
+#define IADC_SINGLE_CFG_CONFIG0 (_IADC_SINGLE_CFG_CONFIG0 << 16) /**< Shifted mode CONFIG0 for IADC_SINGLE */
+#define IADC_SINGLE_CFG_CONFIG1 (_IADC_SINGLE_CFG_CONFIG1 << 16) /**< Shifted mode CONFIG1 for IADC_SINGLE */
+#define IADC_SINGLE_CMP (0x1UL << 17) /**< Comparison Enable */
+#define _IADC_SINGLE_CMP_SHIFT 17 /**< Shift value for IADC_CMP */
+#define _IADC_SINGLE_CMP_MASK 0x20000UL /**< Bit mask for IADC_CMP */
+#define _IADC_SINGLE_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */
+#define IADC_SINGLE_CMP_DEFAULT (_IADC_SINGLE_CMP_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_SINGLE */
+
+/* Bit fields for IADC SCAN */
+#define _IADC_SCAN_RESETVALUE 0x00000000UL /**< Default value for IADC_SCAN */
+#define _IADC_SCAN_MASK 0x0003FFFFUL /**< Mask for IADC_SCAN */
+#define _IADC_SCAN_PINNEG_SHIFT 0 /**< Shift value for IADC_PINNEG */
+#define _IADC_SCAN_PINNEG_MASK 0xFUL /**< Bit mask for IADC_PINNEG */
+#define _IADC_SCAN_PINNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */
+#define IADC_SCAN_PINNEG_DEFAULT (_IADC_SCAN_PINNEG_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCAN */
+#define _IADC_SCAN_PORTNEG_SHIFT 4 /**< Shift value for IADC_PORTNEG */
+#define _IADC_SCAN_PORTNEG_MASK 0xF0UL /**< Bit mask for IADC_PORTNEG */
+#define _IADC_SCAN_PORTNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */
+#define _IADC_SCAN_PORTNEG_GND 0x00000000UL /**< Mode GND for IADC_SCAN */
+#define _IADC_SCAN_PORTNEG_DAC1 0x00000002UL /**< Mode DAC1 for IADC_SCAN */
+#define _IADC_SCAN_PORTNEG_PADANA1 0x00000004UL /**< Mode PADANA1 for IADC_SCAN */
+#define _IADC_SCAN_PORTNEG_PADANA3 0x00000005UL /**< Mode PADANA3 for IADC_SCAN */
+#define _IADC_SCAN_PORTNEG_PORTA 0x00000008UL /**< Mode PORTA for IADC_SCAN */
+#define _IADC_SCAN_PORTNEG_PORTB 0x00000009UL /**< Mode PORTB for IADC_SCAN */
+#define _IADC_SCAN_PORTNEG_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SCAN */
+#define _IADC_SCAN_PORTNEG_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SCAN */
+#define IADC_SCAN_PORTNEG_DEFAULT (_IADC_SCAN_PORTNEG_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SCAN */
+#define IADC_SCAN_PORTNEG_GND (_IADC_SCAN_PORTNEG_GND << 4) /**< Shifted mode GND for IADC_SCAN */
+#define IADC_SCAN_PORTNEG_DAC1 (_IADC_SCAN_PORTNEG_DAC1 << 4) /**< Shifted mode DAC1 for IADC_SCAN */
+#define IADC_SCAN_PORTNEG_PADANA1 (_IADC_SCAN_PORTNEG_PADANA1 << 4) /**< Shifted mode PADANA1 for IADC_SCAN */
+#define IADC_SCAN_PORTNEG_PADANA3 (_IADC_SCAN_PORTNEG_PADANA3 << 4) /**< Shifted mode PADANA3 for IADC_SCAN */
+#define IADC_SCAN_PORTNEG_PORTA (_IADC_SCAN_PORTNEG_PORTA << 4) /**< Shifted mode PORTA for IADC_SCAN */
+#define IADC_SCAN_PORTNEG_PORTB (_IADC_SCAN_PORTNEG_PORTB << 4) /**< Shifted mode PORTB for IADC_SCAN */
+#define IADC_SCAN_PORTNEG_PORTC (_IADC_SCAN_PORTNEG_PORTC << 4) /**< Shifted mode PORTC for IADC_SCAN */
+#define IADC_SCAN_PORTNEG_PORTD (_IADC_SCAN_PORTNEG_PORTD << 4) /**< Shifted mode PORTD for IADC_SCAN */
+#define _IADC_SCAN_PINPOS_SHIFT 8 /**< Shift value for IADC_PINPOS */
+#define _IADC_SCAN_PINPOS_MASK 0xF00UL /**< Bit mask for IADC_PINPOS */
+#define _IADC_SCAN_PINPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */
+#define IADC_SCAN_PINPOS_DEFAULT (_IADC_SCAN_PINPOS_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SCAN */
+#define _IADC_SCAN_PORTPOS_SHIFT 12 /**< Shift value for IADC_PORTPOS */
+#define _IADC_SCAN_PORTPOS_MASK 0xF000UL /**< Bit mask for IADC_PORTPOS */
+#define _IADC_SCAN_PORTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */
+#define _IADC_SCAN_PORTPOS_GND 0x00000000UL /**< Mode GND for IADC_SCAN */
+#define _IADC_SCAN_PORTPOS_SUPPLY 0x00000001UL /**< Mode SUPPLY for IADC_SCAN */
+#define _IADC_SCAN_PORTPOS_DAC0 0x00000002UL /**< Mode DAC0 for IADC_SCAN */
+#define _IADC_SCAN_PORTPOS_PADANA0 0x00000004UL /**< Mode PADANA0 for IADC_SCAN */
+#define _IADC_SCAN_PORTPOS_PADANA2 0x00000005UL /**< Mode PADANA2 for IADC_SCAN */
+#define _IADC_SCAN_PORTPOS_PORTA 0x00000008UL /**< Mode PORTA for IADC_SCAN */
+#define _IADC_SCAN_PORTPOS_PORTB 0x00000009UL /**< Mode PORTB for IADC_SCAN */
+#define _IADC_SCAN_PORTPOS_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SCAN */
+#define _IADC_SCAN_PORTPOS_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SCAN */
+#define IADC_SCAN_PORTPOS_DEFAULT (_IADC_SCAN_PORTPOS_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_SCAN */
+#define IADC_SCAN_PORTPOS_GND (_IADC_SCAN_PORTPOS_GND << 12) /**< Shifted mode GND for IADC_SCAN */
+#define IADC_SCAN_PORTPOS_SUPPLY (_IADC_SCAN_PORTPOS_SUPPLY << 12) /**< Shifted mode SUPPLY for IADC_SCAN */
+#define IADC_SCAN_PORTPOS_DAC0 (_IADC_SCAN_PORTPOS_DAC0 << 12) /**< Shifted mode DAC0 for IADC_SCAN */
+#define IADC_SCAN_PORTPOS_PADANA0 (_IADC_SCAN_PORTPOS_PADANA0 << 12) /**< Shifted mode PADANA0 for IADC_SCAN */
+#define IADC_SCAN_PORTPOS_PADANA2 (_IADC_SCAN_PORTPOS_PADANA2 << 12) /**< Shifted mode PADANA2 for IADC_SCAN */
+#define IADC_SCAN_PORTPOS_PORTA (_IADC_SCAN_PORTPOS_PORTA << 12) /**< Shifted mode PORTA for IADC_SCAN */
+#define IADC_SCAN_PORTPOS_PORTB (_IADC_SCAN_PORTPOS_PORTB << 12) /**< Shifted mode PORTB for IADC_SCAN */
+#define IADC_SCAN_PORTPOS_PORTC (_IADC_SCAN_PORTPOS_PORTC << 12) /**< Shifted mode PORTC for IADC_SCAN */
+#define IADC_SCAN_PORTPOS_PORTD (_IADC_SCAN_PORTPOS_PORTD << 12) /**< Shifted mode PORTD for IADC_SCAN */
+#define IADC_SCAN_CFG (0x1UL << 16) /**< Configuration Group Select */
+#define _IADC_SCAN_CFG_SHIFT 16 /**< Shift value for IADC_CFG */
+#define _IADC_SCAN_CFG_MASK 0x10000UL /**< Bit mask for IADC_CFG */
+#define _IADC_SCAN_CFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */
+#define _IADC_SCAN_CFG_CONFIG0 0x00000000UL /**< Mode CONFIG0 for IADC_SCAN */
+#define _IADC_SCAN_CFG_CONFIG1 0x00000001UL /**< Mode CONFIG1 for IADC_SCAN */
+#define IADC_SCAN_CFG_DEFAULT (_IADC_SCAN_CFG_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_SCAN */
+#define IADC_SCAN_CFG_CONFIG0 (_IADC_SCAN_CFG_CONFIG0 << 16) /**< Shifted mode CONFIG0 for IADC_SCAN */
+#define IADC_SCAN_CFG_CONFIG1 (_IADC_SCAN_CFG_CONFIG1 << 16) /**< Shifted mode CONFIG1 for IADC_SCAN */
+#define IADC_SCAN_CMP (0x1UL << 17) /**< Comparison Enable */
+#define _IADC_SCAN_CMP_SHIFT 17 /**< Shift value for IADC_CMP */
+#define _IADC_SCAN_CMP_MASK 0x20000UL /**< Bit mask for IADC_CMP */
+#define _IADC_SCAN_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */
+#define IADC_SCAN_CMP_DEFAULT (_IADC_SCAN_CMP_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_SCAN */
+
+/** @} End of group EFR32MG24_IADC_BitFields */
+/** @} End of group EFR32MG24_IADC */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_IADC_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_icache.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_icache.h
new file mode 100644
index 00000000..31902b72
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_icache.h
@@ -0,0 +1,248 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 ICACHE register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_ICACHE_H
+#define EFR32MG24_ICACHE_H
+#define ICACHE_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_ICACHE ICACHE
+ * @{
+ * @brief EFR32MG24 ICACHE Register Declaration.
+ *****************************************************************************/
+
+/** ICACHE Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IP Version */
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IM uint32_t PCHITS; /**< Performance Counter Hits */
+ __IM uint32_t PCMISSES; /**< Performance Counter Misses */
+ __IM uint32_t PCAHITS; /**< Performance Counter Advanced Hits */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IOM uint32_t LPMODE; /**< Low Power Mode */
+ __IOM uint32_t IF; /**< Interrupt Flag */
+ __IOM uint32_t IEN; /**< Interrupt Enable */
+ uint32_t RESERVED0[1014U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP Version */
+ __IOM uint32_t CTRL_SET; /**< Control Register */
+ __IM uint32_t PCHITS_SET; /**< Performance Counter Hits */
+ __IM uint32_t PCMISSES_SET; /**< Performance Counter Misses */
+ __IM uint32_t PCAHITS_SET; /**< Performance Counter Advanced Hits */
+ __IM uint32_t STATUS_SET; /**< Status Register */
+ __IOM uint32_t CMD_SET; /**< Command Register */
+ __IOM uint32_t LPMODE_SET; /**< Low Power Mode */
+ __IOM uint32_t IF_SET; /**< Interrupt Flag */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable */
+ uint32_t RESERVED1[1014U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP Version */
+ __IOM uint32_t CTRL_CLR; /**< Control Register */
+ __IM uint32_t PCHITS_CLR; /**< Performance Counter Hits */
+ __IM uint32_t PCMISSES_CLR; /**< Performance Counter Misses */
+ __IM uint32_t PCAHITS_CLR; /**< Performance Counter Advanced Hits */
+ __IM uint32_t STATUS_CLR; /**< Status Register */
+ __IOM uint32_t CMD_CLR; /**< Command Register */
+ __IOM uint32_t LPMODE_CLR; /**< Low Power Mode */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flag */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable */
+ uint32_t RESERVED2[1014U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP Version */
+ __IOM uint32_t CTRL_TGL; /**< Control Register */
+ __IM uint32_t PCHITS_TGL; /**< Performance Counter Hits */
+ __IM uint32_t PCMISSES_TGL; /**< Performance Counter Misses */
+ __IM uint32_t PCAHITS_TGL; /**< Performance Counter Advanced Hits */
+ __IM uint32_t STATUS_TGL; /**< Status Register */
+ __IOM uint32_t CMD_TGL; /**< Command Register */
+ __IOM uint32_t LPMODE_TGL; /**< Low Power Mode */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flag */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable */
+} ICACHE_TypeDef;
+/** @} End of group EFR32MG24_ICACHE */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_ICACHE
+ * @{
+ * @defgroup EFR32MG24_ICACHE_BitFields ICACHE Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for ICACHE IPVERSION */
+#define _ICACHE_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IPVERSION */
+#define _ICACHE_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_IPVERSION */
+#define _ICACHE_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ICACHE_IPVERSION */
+#define _ICACHE_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_IPVERSION */
+#define _ICACHE_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IPVERSION */
+#define ICACHE_IPVERSION_IPVERSION_DEFAULT (_ICACHE_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IPVERSION */
+
+/* Bit fields for ICACHE CTRL */
+#define _ICACHE_CTRL_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CTRL */
+#define _ICACHE_CTRL_MASK 0x00000007UL /**< Mask for ICACHE_CTRL */
+#define ICACHE_CTRL_CACHEDIS (0x1UL << 0) /**< Cache Disable */
+#define _ICACHE_CTRL_CACHEDIS_SHIFT 0 /**< Shift value for ICACHE_CACHEDIS */
+#define _ICACHE_CTRL_CACHEDIS_MASK 0x1UL /**< Bit mask for ICACHE_CACHEDIS */
+#define _ICACHE_CTRL_CACHEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */
+#define ICACHE_CTRL_CACHEDIS_DEFAULT (_ICACHE_CTRL_CACHEDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CTRL */
+#define ICACHE_CTRL_USEMPU (0x1UL << 1) /**< Use MPU */
+#define _ICACHE_CTRL_USEMPU_SHIFT 1 /**< Shift value for ICACHE_USEMPU */
+#define _ICACHE_CTRL_USEMPU_MASK 0x2UL /**< Bit mask for ICACHE_USEMPU */
+#define _ICACHE_CTRL_USEMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */
+#define ICACHE_CTRL_USEMPU_DEFAULT (_ICACHE_CTRL_USEMPU_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CTRL */
+#define ICACHE_CTRL_AUTOFLUSHDIS (0x1UL << 2) /**< Automatic Flushing Disable */
+#define _ICACHE_CTRL_AUTOFLUSHDIS_SHIFT 2 /**< Shift value for ICACHE_AUTOFLUSHDIS */
+#define _ICACHE_CTRL_AUTOFLUSHDIS_MASK 0x4UL /**< Bit mask for ICACHE_AUTOFLUSHDIS */
+#define _ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */
+#define ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT (_ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CTRL */
+
+/* Bit fields for ICACHE PCHITS */
+#define _ICACHE_PCHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCHITS */
+#define _ICACHE_PCHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCHITS */
+#define _ICACHE_PCHITS_PCHITS_SHIFT 0 /**< Shift value for ICACHE_PCHITS */
+#define _ICACHE_PCHITS_PCHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCHITS */
+#define _ICACHE_PCHITS_PCHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCHITS */
+#define ICACHE_PCHITS_PCHITS_DEFAULT (_ICACHE_PCHITS_PCHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCHITS */
+
+/* Bit fields for ICACHE PCMISSES */
+#define _ICACHE_PCMISSES_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCMISSES */
+#define _ICACHE_PCMISSES_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCMISSES */
+#define _ICACHE_PCMISSES_PCMISSES_SHIFT 0 /**< Shift value for ICACHE_PCMISSES */
+#define _ICACHE_PCMISSES_PCMISSES_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCMISSES */
+#define _ICACHE_PCMISSES_PCMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCMISSES */
+#define ICACHE_PCMISSES_PCMISSES_DEFAULT (_ICACHE_PCMISSES_PCMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCMISSES */
+
+/* Bit fields for ICACHE PCAHITS */
+#define _ICACHE_PCAHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCAHITS */
+#define _ICACHE_PCAHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCAHITS */
+#define _ICACHE_PCAHITS_PCAHITS_SHIFT 0 /**< Shift value for ICACHE_PCAHITS */
+#define _ICACHE_PCAHITS_PCAHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCAHITS */
+#define _ICACHE_PCAHITS_PCAHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCAHITS */
+#define ICACHE_PCAHITS_PCAHITS_DEFAULT (_ICACHE_PCAHITS_PCAHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCAHITS */
+
+/* Bit fields for ICACHE STATUS */
+#define _ICACHE_STATUS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_STATUS */
+#define _ICACHE_STATUS_MASK 0x00000001UL /**< Mask for ICACHE_STATUS */
+#define ICACHE_STATUS_PCRUNNING (0x1UL << 0) /**< PC Running */
+#define _ICACHE_STATUS_PCRUNNING_SHIFT 0 /**< Shift value for ICACHE_PCRUNNING */
+#define _ICACHE_STATUS_PCRUNNING_MASK 0x1UL /**< Bit mask for ICACHE_PCRUNNING */
+#define _ICACHE_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_STATUS */
+#define ICACHE_STATUS_PCRUNNING_DEFAULT (_ICACHE_STATUS_PCRUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_STATUS */
+
+/* Bit fields for ICACHE CMD */
+#define _ICACHE_CMD_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CMD */
+#define _ICACHE_CMD_MASK 0x00000007UL /**< Mask for ICACHE_CMD */
+#define ICACHE_CMD_FLUSH (0x1UL << 0) /**< Flush */
+#define _ICACHE_CMD_FLUSH_SHIFT 0 /**< Shift value for ICACHE_FLUSH */
+#define _ICACHE_CMD_FLUSH_MASK 0x1UL /**< Bit mask for ICACHE_FLUSH */
+#define _ICACHE_CMD_FLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */
+#define ICACHE_CMD_FLUSH_DEFAULT (_ICACHE_CMD_FLUSH_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CMD */
+#define ICACHE_CMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */
+#define _ICACHE_CMD_STARTPC_SHIFT 1 /**< Shift value for ICACHE_STARTPC */
+#define _ICACHE_CMD_STARTPC_MASK 0x2UL /**< Bit mask for ICACHE_STARTPC */
+#define _ICACHE_CMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */
+#define ICACHE_CMD_STARTPC_DEFAULT (_ICACHE_CMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CMD */
+#define ICACHE_CMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */
+#define _ICACHE_CMD_STOPPC_SHIFT 2 /**< Shift value for ICACHE_STOPPC */
+#define _ICACHE_CMD_STOPPC_MASK 0x4UL /**< Bit mask for ICACHE_STOPPC */
+#define _ICACHE_CMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */
+#define ICACHE_CMD_STOPPC_DEFAULT (_ICACHE_CMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CMD */
+
+/* Bit fields for ICACHE LPMODE */
+#define _ICACHE_LPMODE_RESETVALUE 0x00000023UL /**< Default value for ICACHE_LPMODE */
+#define _ICACHE_LPMODE_MASK 0x000000F3UL /**< Mask for ICACHE_LPMODE */
+#define _ICACHE_LPMODE_LPLEVEL_SHIFT 0 /**< Shift value for ICACHE_LPLEVEL */
+#define _ICACHE_LPMODE_LPLEVEL_MASK 0x3UL /**< Bit mask for ICACHE_LPLEVEL */
+#define _ICACHE_LPMODE_LPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ICACHE_LPMODE */
+#define _ICACHE_LPMODE_LPLEVEL_BASIC 0x00000000UL /**< Mode BASIC for ICACHE_LPMODE */
+#define _ICACHE_LPMODE_LPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for ICACHE_LPMODE */
+#define _ICACHE_LPMODE_LPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for ICACHE_LPMODE */
+#define ICACHE_LPMODE_LPLEVEL_DEFAULT (_ICACHE_LPMODE_LPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_LPMODE */
+#define ICACHE_LPMODE_LPLEVEL_BASIC (_ICACHE_LPMODE_LPLEVEL_BASIC << 0) /**< Shifted mode BASIC for ICACHE_LPMODE */
+#define ICACHE_LPMODE_LPLEVEL_ADVANCED (_ICACHE_LPMODE_LPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for ICACHE_LPMODE */
+#define ICACHE_LPMODE_LPLEVEL_MINACTIVITY (_ICACHE_LPMODE_LPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for ICACHE_LPMODE */
+#define _ICACHE_LPMODE_NESTFACTOR_SHIFT 4 /**< Shift value for ICACHE_NESTFACTOR */
+#define _ICACHE_LPMODE_NESTFACTOR_MASK 0xF0UL /**< Bit mask for ICACHE_NESTFACTOR */
+#define _ICACHE_LPMODE_NESTFACTOR_DEFAULT 0x00000002UL /**< Mode DEFAULT for ICACHE_LPMODE */
+#define ICACHE_LPMODE_NESTFACTOR_DEFAULT (_ICACHE_LPMODE_NESTFACTOR_DEFAULT << 4) /**< Shifted mode DEFAULT for ICACHE_LPMODE */
+
+/* Bit fields for ICACHE IF */
+#define _ICACHE_IF_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IF */
+#define _ICACHE_IF_MASK 0x00000107UL /**< Mask for ICACHE_IF */
+#define ICACHE_IF_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Flag */
+#define _ICACHE_IF_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */
+#define _ICACHE_IF_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */
+#define _ICACHE_IF_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */
+#define ICACHE_IF_HITOF_DEFAULT (_ICACHE_IF_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IF */
+#define ICACHE_IF_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Flag */
+#define _ICACHE_IF_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */
+#define _ICACHE_IF_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */
+#define _ICACHE_IF_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */
+#define ICACHE_IF_MISSOF_DEFAULT (_ICACHE_IF_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IF */
+#define ICACHE_IF_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Flag */
+#define _ICACHE_IF_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */
+#define _ICACHE_IF_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */
+#define _ICACHE_IF_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */
+#define ICACHE_IF_AHITOF_DEFAULT (_ICACHE_IF_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IF */
+#define ICACHE_IF_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Flag */
+#define _ICACHE_IF_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */
+#define _ICACHE_IF_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */
+#define _ICACHE_IF_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */
+#define ICACHE_IF_RAMERROR_DEFAULT (_ICACHE_IF_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IF */
+
+/* Bit fields for ICACHE IEN */
+#define _ICACHE_IEN_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IEN */
+#define _ICACHE_IEN_MASK 0x00000107UL /**< Mask for ICACHE_IEN */
+#define ICACHE_IEN_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Enable */
+#define _ICACHE_IEN_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */
+#define _ICACHE_IEN_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */
+#define _ICACHE_IEN_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */
+#define ICACHE_IEN_HITOF_DEFAULT (_ICACHE_IEN_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IEN */
+#define ICACHE_IEN_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Enable */
+#define _ICACHE_IEN_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */
+#define _ICACHE_IEN_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */
+#define _ICACHE_IEN_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */
+#define ICACHE_IEN_MISSOF_DEFAULT (_ICACHE_IEN_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IEN */
+#define ICACHE_IEN_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Enable */
+#define _ICACHE_IEN_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */
+#define _ICACHE_IEN_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */
+#define _ICACHE_IEN_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */
+#define ICACHE_IEN_AHITOF_DEFAULT (_ICACHE_IEN_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IEN */
+#define ICACHE_IEN_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Enable */
+#define _ICACHE_IEN_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */
+#define _ICACHE_IEN_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */
+#define _ICACHE_IEN_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */
+#define ICACHE_IEN_RAMERROR_DEFAULT (_ICACHE_IEN_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IEN */
+
+/** @} End of group EFR32MG24_ICACHE_BitFields */
+/** @} End of group EFR32MG24_ICACHE */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_ICACHE_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_keyscan.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_keyscan.h
new file mode 100644
index 00000000..31f4f58c
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_keyscan.h
@@ -0,0 +1,386 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 KEYSCAN register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_KEYSCAN_H
+#define EFR32MG24_KEYSCAN_H
+#define KEYSCAN_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_KEYSCAN KEYSCAN
+ * @{
+ * @brief EFR32MG24 KEYSCAN Register Declaration.
+ *****************************************************************************/
+
+/** KEYSCAN Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IPVERSION */
+ __IOM uint32_t EN; /**< Enable */
+ __IOM uint32_t SWRST; /**< Software Reset */
+ __IOM uint32_t CFG; /**< Config */
+ __IOM uint32_t CMD; /**< Command */
+ __IOM uint32_t DELAY; /**< Delay */
+ __IM uint32_t STATUS; /**< Status */
+ __IOM uint32_t IF; /**< Interrupt Flags */
+ __IOM uint32_t IEN; /**< Interrupt Enables */
+ uint32_t RESERVED0[1015U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IPVERSION */
+ __IOM uint32_t EN_SET; /**< Enable */
+ __IOM uint32_t SWRST_SET; /**< Software Reset */
+ __IOM uint32_t CFG_SET; /**< Config */
+ __IOM uint32_t CMD_SET; /**< Command */
+ __IOM uint32_t DELAY_SET; /**< Delay */
+ __IM uint32_t STATUS_SET; /**< Status */
+ __IOM uint32_t IF_SET; /**< Interrupt Flags */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enables */
+ uint32_t RESERVED1[1015U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IPVERSION */
+ __IOM uint32_t EN_CLR; /**< Enable */
+ __IOM uint32_t SWRST_CLR; /**< Software Reset */
+ __IOM uint32_t CFG_CLR; /**< Config */
+ __IOM uint32_t CMD_CLR; /**< Command */
+ __IOM uint32_t DELAY_CLR; /**< Delay */
+ __IM uint32_t STATUS_CLR; /**< Status */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flags */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enables */
+ uint32_t RESERVED2[1015U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IPVERSION */
+ __IOM uint32_t EN_TGL; /**< Enable */
+ __IOM uint32_t SWRST_TGL; /**< Software Reset */
+ __IOM uint32_t CFG_TGL; /**< Config */
+ __IOM uint32_t CMD_TGL; /**< Command */
+ __IOM uint32_t DELAY_TGL; /**< Delay */
+ __IM uint32_t STATUS_TGL; /**< Status */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flags */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enables */
+} KEYSCAN_TypeDef;
+/** @} End of group EFR32MG24_KEYSCAN */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_KEYSCAN
+ * @{
+ * @defgroup EFR32MG24_KEYSCAN_BitFields KEYSCAN Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for KEYSCAN IPVERSION */
+#define _KEYSCAN_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for KEYSCAN_IPVERSION */
+#define _KEYSCAN_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for KEYSCAN_IPVERSION */
+#define _KEYSCAN_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for KEYSCAN_IPVERSION */
+#define _KEYSCAN_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for KEYSCAN_IPVERSION */
+#define _KEYSCAN_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for KEYSCAN_IPVERSION */
+#define KEYSCAN_IPVERSION_IPVERSION_DEFAULT (_KEYSCAN_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_IPVERSION */
+
+/* Bit fields for KEYSCAN EN */
+#define _KEYSCAN_EN_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_EN */
+#define _KEYSCAN_EN_MASK 0x00000003UL /**< Mask for KEYSCAN_EN */
+#define KEYSCAN_EN_EN (0x1UL << 0) /**< Enable */
+#define _KEYSCAN_EN_EN_SHIFT 0 /**< Shift value for KEYSCAN_EN */
+#define _KEYSCAN_EN_EN_MASK 0x1UL /**< Bit mask for KEYSCAN_EN */
+#define _KEYSCAN_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_EN */
+#define _KEYSCAN_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for KEYSCAN_EN */
+#define _KEYSCAN_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for KEYSCAN_EN */
+#define KEYSCAN_EN_EN_DEFAULT (_KEYSCAN_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_EN */
+#define KEYSCAN_EN_EN_DISABLE (_KEYSCAN_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for KEYSCAN_EN */
+#define KEYSCAN_EN_EN_ENABLE (_KEYSCAN_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for KEYSCAN_EN */
+#define KEYSCAN_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */
+#define _KEYSCAN_EN_DISABLING_SHIFT 1 /**< Shift value for KEYSCAN_DISABLING */
+#define _KEYSCAN_EN_DISABLING_MASK 0x2UL /**< Bit mask for KEYSCAN_DISABLING */
+#define _KEYSCAN_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_EN */
+#define KEYSCAN_EN_DISABLING_DEFAULT (_KEYSCAN_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_EN */
+
+/* Bit fields for KEYSCAN SWRST */
+#define _KEYSCAN_SWRST_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_SWRST */
+#define _KEYSCAN_SWRST_MASK 0x00000003UL /**< Mask for KEYSCAN_SWRST */
+#define KEYSCAN_SWRST_SWRST (0x1UL << 0) /**< Software reset command */
+#define _KEYSCAN_SWRST_SWRST_SHIFT 0 /**< Shift value for KEYSCAN_SWRST */
+#define _KEYSCAN_SWRST_SWRST_MASK 0x1UL /**< Bit mask for KEYSCAN_SWRST */
+#define _KEYSCAN_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_SWRST */
+#define KEYSCAN_SWRST_SWRST_DEFAULT (_KEYSCAN_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_SWRST */
+#define KEYSCAN_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */
+#define _KEYSCAN_SWRST_RESETTING_SHIFT 1 /**< Shift value for KEYSCAN_RESETTING */
+#define _KEYSCAN_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for KEYSCAN_RESETTING */
+#define _KEYSCAN_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_SWRST */
+#define KEYSCAN_SWRST_RESETTING_DEFAULT (_KEYSCAN_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_SWRST */
+
+/* Bit fields for KEYSCAN CFG */
+#define _KEYSCAN_CFG_RESETVALUE 0x2501387FUL /**< Default value for KEYSCAN_CFG */
+#define _KEYSCAN_CFG_MASK 0x7753FFFFUL /**< Mask for KEYSCAN_CFG */
+#define _KEYSCAN_CFG_CLKDIV_SHIFT 0 /**< Shift value for KEYSCAN_CLKDIV */
+#define _KEYSCAN_CFG_CLKDIV_MASK 0x3FFFFUL /**< Bit mask for KEYSCAN_CLKDIV */
+#define _KEYSCAN_CFG_CLKDIV_DEFAULT 0x0001387FUL /**< Mode DEFAULT for KEYSCAN_CFG */
+#define KEYSCAN_CFG_CLKDIV_DEFAULT (_KEYSCAN_CFG_CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_CFG */
+#define KEYSCAN_CFG_SINGLEPRESS (0x1UL << 20) /**< Single Press */
+#define _KEYSCAN_CFG_SINGLEPRESS_SHIFT 20 /**< Shift value for KEYSCAN_SINGLEPRESS */
+#define _KEYSCAN_CFG_SINGLEPRESS_MASK 0x100000UL /**< Bit mask for KEYSCAN_SINGLEPRESS */
+#define _KEYSCAN_CFG_SINGLEPRESS_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CFG */
+#define _KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS 0x00000000UL /**< Mode MULTIPRESS for KEYSCAN_CFG */
+#define _KEYSCAN_CFG_SINGLEPRESS_SINGLEPRESS 0x00000001UL /**< Mode SINGLEPRESS for KEYSCAN_CFG */
+#define KEYSCAN_CFG_SINGLEPRESS_DEFAULT (_KEYSCAN_CFG_SINGLEPRESS_DEFAULT << 20) /**< Shifted mode DEFAULT for KEYSCAN_CFG */
+#define KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS (_KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS << 20) /**< Shifted mode MULTIPRESS for KEYSCAN_CFG */
+#define KEYSCAN_CFG_SINGLEPRESS_SINGLEPRESS (_KEYSCAN_CFG_SINGLEPRESS_SINGLEPRESS << 20) /**< Shifted mode SINGLEPRESS for KEYSCAN_CFG */
+#define KEYSCAN_CFG_AUTOSTART (0x1UL << 22) /**< Automatically Start */
+#define _KEYSCAN_CFG_AUTOSTART_SHIFT 22 /**< Shift value for KEYSCAN_AUTOSTART */
+#define _KEYSCAN_CFG_AUTOSTART_MASK 0x400000UL /**< Bit mask for KEYSCAN_AUTOSTART */
+#define _KEYSCAN_CFG_AUTOSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CFG */
+#define _KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS 0x00000000UL /**< Mode AUTOSTARTDIS for KEYSCAN_CFG */
+#define _KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN 0x00000001UL /**< Mode AUTOSTARTEN for KEYSCAN_CFG */
+#define KEYSCAN_CFG_AUTOSTART_DEFAULT (_KEYSCAN_CFG_AUTOSTART_DEFAULT << 22) /**< Shifted mode DEFAULT for KEYSCAN_CFG */
+#define KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS (_KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS << 22) /**< Shifted mode AUTOSTARTDIS for KEYSCAN_CFG */
+#define KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN (_KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN << 22) /**< Shifted mode AUTOSTARTEN for KEYSCAN_CFG */
+#define _KEYSCAN_CFG_NUMROWS_SHIFT 24 /**< Shift value for KEYSCAN_NUMROWS */
+#define _KEYSCAN_CFG_NUMROWS_MASK 0x7000000UL /**< Bit mask for KEYSCAN_NUMROWS */
+#define _KEYSCAN_CFG_NUMROWS_DEFAULT 0x00000005UL /**< Mode DEFAULT for KEYSCAN_CFG */
+#define _KEYSCAN_CFG_NUMROWS_RSV1 0x00000000UL /**< Mode RSV1 for KEYSCAN_CFG */
+#define _KEYSCAN_CFG_NUMROWS_RSV2 0x00000001UL /**< Mode RSV2 for KEYSCAN_CFG */
+#define _KEYSCAN_CFG_NUMROWS_ROW3 0x00000002UL /**< Mode ROW3 for KEYSCAN_CFG */
+#define _KEYSCAN_CFG_NUMROWS_ROW4 0x00000003UL /**< Mode ROW4 for KEYSCAN_CFG */
+#define _KEYSCAN_CFG_NUMROWS_ROW5 0x00000004UL /**< Mode ROW5 for KEYSCAN_CFG */
+#define _KEYSCAN_CFG_NUMROWS_ROW6 0x00000005UL /**< Mode ROW6 for KEYSCAN_CFG */
+#define KEYSCAN_CFG_NUMROWS_DEFAULT (_KEYSCAN_CFG_NUMROWS_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_CFG */
+#define KEYSCAN_CFG_NUMROWS_RSV1 (_KEYSCAN_CFG_NUMROWS_RSV1 << 24) /**< Shifted mode RSV1 for KEYSCAN_CFG */
+#define KEYSCAN_CFG_NUMROWS_RSV2 (_KEYSCAN_CFG_NUMROWS_RSV2 << 24) /**< Shifted mode RSV2 for KEYSCAN_CFG */
+#define KEYSCAN_CFG_NUMROWS_ROW3 (_KEYSCAN_CFG_NUMROWS_ROW3 << 24) /**< Shifted mode ROW3 for KEYSCAN_CFG */
+#define KEYSCAN_CFG_NUMROWS_ROW4 (_KEYSCAN_CFG_NUMROWS_ROW4 << 24) /**< Shifted mode ROW4 for KEYSCAN_CFG */
+#define KEYSCAN_CFG_NUMROWS_ROW5 (_KEYSCAN_CFG_NUMROWS_ROW5 << 24) /**< Shifted mode ROW5 for KEYSCAN_CFG */
+#define KEYSCAN_CFG_NUMROWS_ROW6 (_KEYSCAN_CFG_NUMROWS_ROW6 << 24) /**< Shifted mode ROW6 for KEYSCAN_CFG */
+#define _KEYSCAN_CFG_NUMCOLS_SHIFT 28 /**< Shift value for KEYSCAN_NUMCOLS */
+#define _KEYSCAN_CFG_NUMCOLS_MASK 0x70000000UL /**< Bit mask for KEYSCAN_NUMCOLS */
+#define _KEYSCAN_CFG_NUMCOLS_DEFAULT 0x00000002UL /**< Mode DEFAULT for KEYSCAN_CFG */
+#define KEYSCAN_CFG_NUMCOLS_DEFAULT (_KEYSCAN_CFG_NUMCOLS_DEFAULT << 28) /**< Shifted mode DEFAULT for KEYSCAN_CFG */
+
+/* Bit fields for KEYSCAN CMD */
+#define _KEYSCAN_CMD_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_CMD */
+#define _KEYSCAN_CMD_MASK 0x00000003UL /**< Mask for KEYSCAN_CMD */
+#define KEYSCAN_CMD_KEYSCANSTART (0x1UL << 0) /**< Keyscan Start */
+#define _KEYSCAN_CMD_KEYSCANSTART_SHIFT 0 /**< Shift value for KEYSCAN_KEYSCANSTART */
+#define _KEYSCAN_CMD_KEYSCANSTART_MASK 0x1UL /**< Bit mask for KEYSCAN_KEYSCANSTART */
+#define _KEYSCAN_CMD_KEYSCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CMD */
+#define KEYSCAN_CMD_KEYSCANSTART_DEFAULT (_KEYSCAN_CMD_KEYSCANSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_CMD */
+#define KEYSCAN_CMD_KEYSCANSTOP (0x1UL << 1) /**< Keyscan Stop */
+#define _KEYSCAN_CMD_KEYSCANSTOP_SHIFT 1 /**< Shift value for KEYSCAN_KEYSCANSTOP */
+#define _KEYSCAN_CMD_KEYSCANSTOP_MASK 0x2UL /**< Bit mask for KEYSCAN_KEYSCANSTOP */
+#define _KEYSCAN_CMD_KEYSCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CMD */
+#define KEYSCAN_CMD_KEYSCANSTOP_DEFAULT (_KEYSCAN_CMD_KEYSCANSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_CMD */
+
+/* Bit fields for KEYSCAN DELAY */
+#define _KEYSCAN_DELAY_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_MASK 0x0F0F0F00UL /**< Mask for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_SCANDLY_SHIFT 8 /**< Shift value for KEYSCAN_SCANDLY */
+#define _KEYSCAN_DELAY_SCANDLY_MASK 0xF00UL /**< Bit mask for KEYSCAN_SCANDLY */
+#define _KEYSCAN_DELAY_SCANDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_SCANDLY_SCANDLY2 0x00000000UL /**< Mode SCANDLY2 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_SCANDLY_SCANDLY4 0x00000001UL /**< Mode SCANDLY4 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_SCANDLY_SCANDLY6 0x00000002UL /**< Mode SCANDLY6 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_SCANDLY_SCANDLY8 0x00000003UL /**< Mode SCANDLY8 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_SCANDLY_SCANDLY10 0x00000004UL /**< Mode SCANDLY10 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_SCANDLY_SCANDLY12 0x00000005UL /**< Mode SCANDLY12 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_SCANDLY_SCANDLY14 0x00000006UL /**< Mode SCANDLY14 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_SCANDLY_SCANDLY16 0x00000007UL /**< Mode SCANDLY16 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_SCANDLY_SCANDLY18 0x00000008UL /**< Mode SCANDLY18 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_SCANDLY_SCANDLY20 0x00000009UL /**< Mode SCANDLY20 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_SCANDLY_SCANDLY22 0x0000000AUL /**< Mode SCANDLY22 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_SCANDLY_SCANDLY24 0x0000000BUL /**< Mode SCANDLY24 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_SCANDLY_SCANDLY26 0x0000000CUL /**< Mode SCANDLY26 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_SCANDLY_SCANDLY28 0x0000000DUL /**< Mode SCANDLY28 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_SCANDLY_SCANDLY30 0x0000000EUL /**< Mode SCANDLY30 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_SCANDLY_SCANDLY32 0x0000000FUL /**< Mode SCANDLY32 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_SCANDLY_DEFAULT (_KEYSCAN_DELAY_SCANDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_SCANDLY_SCANDLY2 (_KEYSCAN_DELAY_SCANDLY_SCANDLY2 << 8) /**< Shifted mode SCANDLY2 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_SCANDLY_SCANDLY4 (_KEYSCAN_DELAY_SCANDLY_SCANDLY4 << 8) /**< Shifted mode SCANDLY4 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_SCANDLY_SCANDLY6 (_KEYSCAN_DELAY_SCANDLY_SCANDLY6 << 8) /**< Shifted mode SCANDLY6 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_SCANDLY_SCANDLY8 (_KEYSCAN_DELAY_SCANDLY_SCANDLY8 << 8) /**< Shifted mode SCANDLY8 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_SCANDLY_SCANDLY10 (_KEYSCAN_DELAY_SCANDLY_SCANDLY10 << 8) /**< Shifted mode SCANDLY10 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_SCANDLY_SCANDLY12 (_KEYSCAN_DELAY_SCANDLY_SCANDLY12 << 8) /**< Shifted mode SCANDLY12 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_SCANDLY_SCANDLY14 (_KEYSCAN_DELAY_SCANDLY_SCANDLY14 << 8) /**< Shifted mode SCANDLY14 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_SCANDLY_SCANDLY16 (_KEYSCAN_DELAY_SCANDLY_SCANDLY16 << 8) /**< Shifted mode SCANDLY16 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_SCANDLY_SCANDLY18 (_KEYSCAN_DELAY_SCANDLY_SCANDLY18 << 8) /**< Shifted mode SCANDLY18 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_SCANDLY_SCANDLY20 (_KEYSCAN_DELAY_SCANDLY_SCANDLY20 << 8) /**< Shifted mode SCANDLY20 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_SCANDLY_SCANDLY22 (_KEYSCAN_DELAY_SCANDLY_SCANDLY22 << 8) /**< Shifted mode SCANDLY22 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_SCANDLY_SCANDLY24 (_KEYSCAN_DELAY_SCANDLY_SCANDLY24 << 8) /**< Shifted mode SCANDLY24 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_SCANDLY_SCANDLY26 (_KEYSCAN_DELAY_SCANDLY_SCANDLY26 << 8) /**< Shifted mode SCANDLY26 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_SCANDLY_SCANDLY28 (_KEYSCAN_DELAY_SCANDLY_SCANDLY28 << 8) /**< Shifted mode SCANDLY28 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_SCANDLY_SCANDLY30 (_KEYSCAN_DELAY_SCANDLY_SCANDLY30 << 8) /**< Shifted mode SCANDLY30 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_SCANDLY_SCANDLY32 (_KEYSCAN_DELAY_SCANDLY_SCANDLY32 << 8) /**< Shifted mode SCANDLY32 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_DEBDLY_SHIFT 16 /**< Shift value for KEYSCAN_DEBDLY */
+#define _KEYSCAN_DELAY_DEBDLY_MASK 0xF0000UL /**< Bit mask for KEYSCAN_DEBDLY */
+#define _KEYSCAN_DELAY_DEBDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_DEBDLY_DEBDLY2 0x00000000UL /**< Mode DEBDLY2 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_DEBDLY_DEBDLY4 0x00000001UL /**< Mode DEBDLY4 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_DEBDLY_DEBDLY6 0x00000002UL /**< Mode DEBDLY6 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_DEBDLY_DEBDLY8 0x00000003UL /**< Mode DEBDLY8 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_DEBDLY_DEBDLY10 0x00000004UL /**< Mode DEBDLY10 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_DEBDLY_DEBDLY12 0x00000005UL /**< Mode DEBDLY12 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_DEBDLY_DEBDLY14 0x00000006UL /**< Mode DEBDLY14 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_DEBDLY_DEBDLY16 0x00000007UL /**< Mode DEBDLY16 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_DEBDLY_DEBDLY18 0x00000008UL /**< Mode DEBDLY18 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_DEBDLY_DEBDLY20 0x00000009UL /**< Mode DEBDLY20 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_DEBDLY_DEBDLY22 0x0000000AUL /**< Mode DEBDLY22 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_DEBDLY_DEBDLY24 0x0000000BUL /**< Mode DEBDLY24 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_DEBDLY_DEBDLY26 0x0000000CUL /**< Mode DEBDLY26 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_DEBDLY_DEBDLY28 0x0000000DUL /**< Mode DEBDLY28 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_DEBDLY_DEBDLY30 0x0000000EUL /**< Mode DEBDLY30 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_DEBDLY_DEBDLY32 0x0000000FUL /**< Mode DEBDLY32 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_DEBDLY_DEFAULT (_KEYSCAN_DELAY_DEBDLY_DEFAULT << 16) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_DEBDLY_DEBDLY2 (_KEYSCAN_DELAY_DEBDLY_DEBDLY2 << 16) /**< Shifted mode DEBDLY2 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_DEBDLY_DEBDLY4 (_KEYSCAN_DELAY_DEBDLY_DEBDLY4 << 16) /**< Shifted mode DEBDLY4 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_DEBDLY_DEBDLY6 (_KEYSCAN_DELAY_DEBDLY_DEBDLY6 << 16) /**< Shifted mode DEBDLY6 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_DEBDLY_DEBDLY8 (_KEYSCAN_DELAY_DEBDLY_DEBDLY8 << 16) /**< Shifted mode DEBDLY8 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_DEBDLY_DEBDLY10 (_KEYSCAN_DELAY_DEBDLY_DEBDLY10 << 16) /**< Shifted mode DEBDLY10 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_DEBDLY_DEBDLY12 (_KEYSCAN_DELAY_DEBDLY_DEBDLY12 << 16) /**< Shifted mode DEBDLY12 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_DEBDLY_DEBDLY14 (_KEYSCAN_DELAY_DEBDLY_DEBDLY14 << 16) /**< Shifted mode DEBDLY14 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_DEBDLY_DEBDLY16 (_KEYSCAN_DELAY_DEBDLY_DEBDLY16 << 16) /**< Shifted mode DEBDLY16 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_DEBDLY_DEBDLY18 (_KEYSCAN_DELAY_DEBDLY_DEBDLY18 << 16) /**< Shifted mode DEBDLY18 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_DEBDLY_DEBDLY20 (_KEYSCAN_DELAY_DEBDLY_DEBDLY20 << 16) /**< Shifted mode DEBDLY20 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_DEBDLY_DEBDLY22 (_KEYSCAN_DELAY_DEBDLY_DEBDLY22 << 16) /**< Shifted mode DEBDLY22 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_DEBDLY_DEBDLY24 (_KEYSCAN_DELAY_DEBDLY_DEBDLY24 << 16) /**< Shifted mode DEBDLY24 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_DEBDLY_DEBDLY26 (_KEYSCAN_DELAY_DEBDLY_DEBDLY26 << 16) /**< Shifted mode DEBDLY26 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_DEBDLY_DEBDLY28 (_KEYSCAN_DELAY_DEBDLY_DEBDLY28 << 16) /**< Shifted mode DEBDLY28 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_DEBDLY_DEBDLY30 (_KEYSCAN_DELAY_DEBDLY_DEBDLY30 << 16) /**< Shifted mode DEBDLY30 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_DEBDLY_DEBDLY32 (_KEYSCAN_DELAY_DEBDLY_DEBDLY32 << 16) /**< Shifted mode DEBDLY32 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_STABDLY_SHIFT 24 /**< Shift value for KEYSCAN_STABDLY */
+#define _KEYSCAN_DELAY_STABDLY_MASK 0xF000000UL /**< Bit mask for KEYSCAN_STABDLY */
+#define _KEYSCAN_DELAY_STABDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_STABDLY_STABDLY2 0x00000000UL /**< Mode STABDLY2 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_STABDLY_STABDLY4 0x00000001UL /**< Mode STABDLY4 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_STABDLY_STABDLY6 0x00000002UL /**< Mode STABDLY6 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_STABDLY_STABDLY8 0x00000003UL /**< Mode STABDLY8 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_STABDLY_STABDLY10 0x00000004UL /**< Mode STABDLY10 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_STABDLY_STABDLY12 0x00000005UL /**< Mode STABDLY12 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_STABDLY_STABDLY14 0x00000006UL /**< Mode STABDLY14 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_STABDLY_STABDLY16 0x00000007UL /**< Mode STABDLY16 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_STABDLY_STABDLY18 0x00000008UL /**< Mode STABDLY18 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_STABDLY_STABDLY20 0x00000009UL /**< Mode STABDLY20 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_STABDLY_STABDLY22 0x0000000AUL /**< Mode STABDLY22 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_STABDLY_STABDLY24 0x0000000BUL /**< Mode STABDLY24 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_STABDLY_STABDLY26 0x0000000CUL /**< Mode STABDLY26 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_STABDLY_STABDLY28 0x0000000DUL /**< Mode STABDLY28 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_STABDLY_STABDLY30 0x0000000EUL /**< Mode STABDLY30 for KEYSCAN_DELAY */
+#define _KEYSCAN_DELAY_STABDLY_STABDLY32 0x0000000FUL /**< Mode STABDLY32 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_STABDLY_DEFAULT (_KEYSCAN_DELAY_STABDLY_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_STABDLY_STABDLY2 (_KEYSCAN_DELAY_STABDLY_STABDLY2 << 24) /**< Shifted mode STABDLY2 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_STABDLY_STABDLY4 (_KEYSCAN_DELAY_STABDLY_STABDLY4 << 24) /**< Shifted mode STABDLY4 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_STABDLY_STABDLY6 (_KEYSCAN_DELAY_STABDLY_STABDLY6 << 24) /**< Shifted mode STABDLY6 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_STABDLY_STABDLY8 (_KEYSCAN_DELAY_STABDLY_STABDLY8 << 24) /**< Shifted mode STABDLY8 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_STABDLY_STABDLY10 (_KEYSCAN_DELAY_STABDLY_STABDLY10 << 24) /**< Shifted mode STABDLY10 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_STABDLY_STABDLY12 (_KEYSCAN_DELAY_STABDLY_STABDLY12 << 24) /**< Shifted mode STABDLY12 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_STABDLY_STABDLY14 (_KEYSCAN_DELAY_STABDLY_STABDLY14 << 24) /**< Shifted mode STABDLY14 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_STABDLY_STABDLY16 (_KEYSCAN_DELAY_STABDLY_STABDLY16 << 24) /**< Shifted mode STABDLY16 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_STABDLY_STABDLY18 (_KEYSCAN_DELAY_STABDLY_STABDLY18 << 24) /**< Shifted mode STABDLY18 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_STABDLY_STABDLY20 (_KEYSCAN_DELAY_STABDLY_STABDLY20 << 24) /**< Shifted mode STABDLY20 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_STABDLY_STABDLY22 (_KEYSCAN_DELAY_STABDLY_STABDLY22 << 24) /**< Shifted mode STABDLY22 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_STABDLY_STABDLY24 (_KEYSCAN_DELAY_STABDLY_STABDLY24 << 24) /**< Shifted mode STABDLY24 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_STABDLY_STABDLY26 (_KEYSCAN_DELAY_STABDLY_STABDLY26 << 24) /**< Shifted mode STABDLY26 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_STABDLY_STABDLY28 (_KEYSCAN_DELAY_STABDLY_STABDLY28 << 24) /**< Shifted mode STABDLY28 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_STABDLY_STABDLY30 (_KEYSCAN_DELAY_STABDLY_STABDLY30 << 24) /**< Shifted mode STABDLY30 for KEYSCAN_DELAY */
+#define KEYSCAN_DELAY_STABDLY_STABDLY32 (_KEYSCAN_DELAY_STABDLY_STABDLY32 << 24) /**< Shifted mode STABDLY32 for KEYSCAN_DELAY */
+
+/* Bit fields for KEYSCAN STATUS */
+#define _KEYSCAN_STATUS_RESETVALUE 0x40000000UL /**< Default value for KEYSCAN_STATUS */
+#define _KEYSCAN_STATUS_MASK 0xC701003FUL /**< Mask for KEYSCAN_STATUS */
+#define _KEYSCAN_STATUS_ROW_SHIFT 0 /**< Shift value for KEYSCAN_ROW */
+#define _KEYSCAN_STATUS_ROW_MASK 0x3FUL /**< Bit mask for KEYSCAN_ROW */
+#define _KEYSCAN_STATUS_ROW_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */
+#define KEYSCAN_STATUS_ROW_DEFAULT (_KEYSCAN_STATUS_ROW_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */
+#define KEYSCAN_STATUS_RUNNING (0x1UL << 16) /**< Running */
+#define _KEYSCAN_STATUS_RUNNING_SHIFT 16 /**< Shift value for KEYSCAN_RUNNING */
+#define _KEYSCAN_STATUS_RUNNING_MASK 0x10000UL /**< Bit mask for KEYSCAN_RUNNING */
+#define _KEYSCAN_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */
+#define KEYSCAN_STATUS_RUNNING_DEFAULT (_KEYSCAN_STATUS_RUNNING_DEFAULT << 16) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */
+#define _KEYSCAN_STATUS_COL_SHIFT 24 /**< Shift value for KEYSCAN_COL */
+#define _KEYSCAN_STATUS_COL_MASK 0x7000000UL /**< Bit mask for KEYSCAN_COL */
+#define _KEYSCAN_STATUS_COL_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */
+#define KEYSCAN_STATUS_COL_DEFAULT (_KEYSCAN_STATUS_COL_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */
+#define KEYSCAN_STATUS_NOKEY (0x1UL << 30) /**< No Key pressed status */
+#define _KEYSCAN_STATUS_NOKEY_SHIFT 30 /**< Shift value for KEYSCAN_NOKEY */
+#define _KEYSCAN_STATUS_NOKEY_MASK 0x40000000UL /**< Bit mask for KEYSCAN_NOKEY */
+#define _KEYSCAN_STATUS_NOKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for KEYSCAN_STATUS */
+#define KEYSCAN_STATUS_NOKEY_DEFAULT (_KEYSCAN_STATUS_NOKEY_DEFAULT << 30) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */
+#define KEYSCAN_STATUS_SYNCBUSY (0x1UL << 31) /**< Sync Busy */
+#define _KEYSCAN_STATUS_SYNCBUSY_SHIFT 31 /**< Shift value for KEYSCAN_SYNCBUSY */
+#define _KEYSCAN_STATUS_SYNCBUSY_MASK 0x80000000UL /**< Bit mask for KEYSCAN_SYNCBUSY */
+#define _KEYSCAN_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */
+#define KEYSCAN_STATUS_SYNCBUSY_DEFAULT (_KEYSCAN_STATUS_SYNCBUSY_DEFAULT << 31) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */
+
+/* Bit fields for KEYSCAN IF */
+#define _KEYSCAN_IF_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_IF */
+#define _KEYSCAN_IF_MASK 0x0000000FUL /**< Mask for KEYSCAN_IF */
+#define KEYSCAN_IF_NOKEY (0x1UL << 0) /**< No key was pressed */
+#define _KEYSCAN_IF_NOKEY_SHIFT 0 /**< Shift value for KEYSCAN_NOKEY */
+#define _KEYSCAN_IF_NOKEY_MASK 0x1UL /**< Bit mask for KEYSCAN_NOKEY */
+#define _KEYSCAN_IF_NOKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IF */
+#define KEYSCAN_IF_NOKEY_DEFAULT (_KEYSCAN_IF_NOKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_IF */
+#define KEYSCAN_IF_KEY (0x1UL << 1) /**< A key was pressed */
+#define _KEYSCAN_IF_KEY_SHIFT 1 /**< Shift value for KEYSCAN_KEY */
+#define _KEYSCAN_IF_KEY_MASK 0x2UL /**< Bit mask for KEYSCAN_KEY */
+#define _KEYSCAN_IF_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IF */
+#define KEYSCAN_IF_KEY_DEFAULT (_KEYSCAN_IF_KEY_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_IF */
+#define KEYSCAN_IF_SCANNED (0x1UL << 2) /**< Completed scan */
+#define _KEYSCAN_IF_SCANNED_SHIFT 2 /**< Shift value for KEYSCAN_SCANNED */
+#define _KEYSCAN_IF_SCANNED_MASK 0x4UL /**< Bit mask for KEYSCAN_SCANNED */
+#define _KEYSCAN_IF_SCANNED_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IF */
+#define KEYSCAN_IF_SCANNED_DEFAULT (_KEYSCAN_IF_SCANNED_DEFAULT << 2) /**< Shifted mode DEFAULT for KEYSCAN_IF */
+#define KEYSCAN_IF_WAKEUP (0x1UL << 3) /**< Wake up */
+#define _KEYSCAN_IF_WAKEUP_SHIFT 3 /**< Shift value for KEYSCAN_WAKEUP */
+#define _KEYSCAN_IF_WAKEUP_MASK 0x8UL /**< Bit mask for KEYSCAN_WAKEUP */
+#define _KEYSCAN_IF_WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IF */
+#define KEYSCAN_IF_WAKEUP_DEFAULT (_KEYSCAN_IF_WAKEUP_DEFAULT << 3) /**< Shifted mode DEFAULT for KEYSCAN_IF */
+
+/* Bit fields for KEYSCAN IEN */
+#define _KEYSCAN_IEN_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_IEN */
+#define _KEYSCAN_IEN_MASK 0x0000000FUL /**< Mask for KEYSCAN_IEN */
+#define KEYSCAN_IEN_NOKEY (0x1UL << 0) /**< No Key was pressed */
+#define _KEYSCAN_IEN_NOKEY_SHIFT 0 /**< Shift value for KEYSCAN_NOKEY */
+#define _KEYSCAN_IEN_NOKEY_MASK 0x1UL /**< Bit mask for KEYSCAN_NOKEY */
+#define _KEYSCAN_IEN_NOKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IEN */
+#define KEYSCAN_IEN_NOKEY_DEFAULT (_KEYSCAN_IEN_NOKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_IEN */
+#define KEYSCAN_IEN_KEY (0x1UL << 1) /**< A Key was pressed */
+#define _KEYSCAN_IEN_KEY_SHIFT 1 /**< Shift value for KEYSCAN_KEY */
+#define _KEYSCAN_IEN_KEY_MASK 0x2UL /**< Bit mask for KEYSCAN_KEY */
+#define _KEYSCAN_IEN_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IEN */
+#define KEYSCAN_IEN_KEY_DEFAULT (_KEYSCAN_IEN_KEY_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_IEN */
+#define KEYSCAN_IEN_SCANNED (0x1UL << 2) /**< Completed Scanning */
+#define _KEYSCAN_IEN_SCANNED_SHIFT 2 /**< Shift value for KEYSCAN_SCANNED */
+#define _KEYSCAN_IEN_SCANNED_MASK 0x4UL /**< Bit mask for KEYSCAN_SCANNED */
+#define _KEYSCAN_IEN_SCANNED_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IEN */
+#define KEYSCAN_IEN_SCANNED_DEFAULT (_KEYSCAN_IEN_SCANNED_DEFAULT << 2) /**< Shifted mode DEFAULT for KEYSCAN_IEN */
+#define KEYSCAN_IEN_WAKEUP (0x1UL << 3) /**< Wake up */
+#define _KEYSCAN_IEN_WAKEUP_SHIFT 3 /**< Shift value for KEYSCAN_WAKEUP */
+#define _KEYSCAN_IEN_WAKEUP_MASK 0x8UL /**< Bit mask for KEYSCAN_WAKEUP */
+#define _KEYSCAN_IEN_WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IEN */
+#define KEYSCAN_IEN_WAKEUP_DEFAULT (_KEYSCAN_IEN_WAKEUP_DEFAULT << 3) /**< Shifted mode DEFAULT for KEYSCAN_IEN */
+
+/** @} End of group EFR32MG24_KEYSCAN_BitFields */
+/** @} End of group EFR32MG24_KEYSCAN */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_KEYSCAN_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_ldma.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_ldma.h
new file mode 100644
index 00000000..02662449
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_ldma.h
@@ -0,0 +1,685 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 LDMA register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_LDMA_H
+#define EFR32MG24_LDMA_H
+#define LDMA_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_LDMA LDMA
+ * @{
+ * @brief EFR32MG24 LDMA Register Declaration.
+ *****************************************************************************/
+
+/** LDMA CH Register Group Declaration. */
+typedef struct {
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+ __IOM uint32_t CFG; /**< Channel Configuration Register */
+ __IOM uint32_t LOOP; /**< Channel Loop Counter Register */
+ __IOM uint32_t CTRL; /**< Channel Descriptor Control Word Register */
+ __IOM uint32_t SRC; /**< Channel Descriptor Source Address */
+ __IOM uint32_t DST; /**< Channel Descriptor Destination Address */
+ __IOM uint32_t LINK; /**< Channel Descriptor Link Address */
+ uint32_t RESERVED1[5U]; /**< Reserved for future use */
+} LDMA_CH_TypeDef;
+
+/** LDMA Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< DMA Channel Request Clear Register */
+ __IOM uint32_t EN; /**< DMA module enable disable Register */
+ __IOM uint32_t CTRL; /**< DMA Control Register */
+ __IM uint32_t STATUS; /**< DMA Status Register */
+ __IOM uint32_t SYNCSWSET; /**< DMA Sync Trig Sw Set Register */
+ __IOM uint32_t SYNCSWCLR; /**< DMA Sync Trig Sw Clear register */
+ __IOM uint32_t SYNCHWEN; /**< DMA Sync HW trigger enable register */
+ __IOM uint32_t SYNCHWSEL; /**< DMA Sync HW trigger selection register */
+ __IM uint32_t SYNCSTATUS; /**< DMA Sync Trigger Status Register */
+ __IOM uint32_t CHEN; /**< DMA Channel Enable Register */
+ __IOM uint32_t CHDIS; /**< DMA Channel Disable Register */
+ __IM uint32_t CHSTATUS; /**< DMA Channel Status Register */
+ __IM uint32_t CHBUSY; /**< DMA Channel Busy Register */
+ __IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register */
+ __IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */
+ __IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request */
+ __IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */
+ __IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */
+ __IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */
+ __IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */
+ __IOM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ LDMA_CH_TypeDef CH[8U]; /**< DMA Channel Registers */
+ uint32_t RESERVED0[906U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< DMA Channel Request Clear Register */
+ __IOM uint32_t EN_SET; /**< DMA module enable disable Register */
+ __IOM uint32_t CTRL_SET; /**< DMA Control Register */
+ __IM uint32_t STATUS_SET; /**< DMA Status Register */
+ __IOM uint32_t SYNCSWSET_SET; /**< DMA Sync Trig Sw Set Register */
+ __IOM uint32_t SYNCSWCLR_SET; /**< DMA Sync Trig Sw Clear register */
+ __IOM uint32_t SYNCHWEN_SET; /**< DMA Sync HW trigger enable register */
+ __IOM uint32_t SYNCHWSEL_SET; /**< DMA Sync HW trigger selection register */
+ __IM uint32_t SYNCSTATUS_SET; /**< DMA Sync Trigger Status Register */
+ __IOM uint32_t CHEN_SET; /**< DMA Channel Enable Register */
+ __IOM uint32_t CHDIS_SET; /**< DMA Channel Disable Register */
+ __IM uint32_t CHSTATUS_SET; /**< DMA Channel Status Register */
+ __IM uint32_t CHBUSY_SET; /**< DMA Channel Busy Register */
+ __IOM uint32_t CHDONE_SET; /**< DMA Channel Linking Done Register */
+ __IOM uint32_t DBGHALT_SET; /**< DMA Channel Debug Halt Register */
+ __IOM uint32_t SWREQ_SET; /**< DMA Channel Software Transfer Request */
+ __IOM uint32_t REQDIS_SET; /**< DMA Channel Request Disable Register */
+ __IM uint32_t REQPEND_SET; /**< DMA Channel Requests Pending Register */
+ __IOM uint32_t LINKLOAD_SET; /**< DMA Channel Link Load Register */
+ __IOM uint32_t REQCLEAR_SET; /**< DMA Channel Request Clear Register */
+ __IOM uint32_t IF_SET; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
+ LDMA_CH_TypeDef CH_SET[8U]; /**< DMA Channel Registers */
+ uint32_t RESERVED1[906U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< DMA Channel Request Clear Register */
+ __IOM uint32_t EN_CLR; /**< DMA module enable disable Register */
+ __IOM uint32_t CTRL_CLR; /**< DMA Control Register */
+ __IM uint32_t STATUS_CLR; /**< DMA Status Register */
+ __IOM uint32_t SYNCSWSET_CLR; /**< DMA Sync Trig Sw Set Register */
+ __IOM uint32_t SYNCSWCLR_CLR; /**< DMA Sync Trig Sw Clear register */
+ __IOM uint32_t SYNCHWEN_CLR; /**< DMA Sync HW trigger enable register */
+ __IOM uint32_t SYNCHWSEL_CLR; /**< DMA Sync HW trigger selection register */
+ __IM uint32_t SYNCSTATUS_CLR; /**< DMA Sync Trigger Status Register */
+ __IOM uint32_t CHEN_CLR; /**< DMA Channel Enable Register */
+ __IOM uint32_t CHDIS_CLR; /**< DMA Channel Disable Register */
+ __IM uint32_t CHSTATUS_CLR; /**< DMA Channel Status Register */
+ __IM uint32_t CHBUSY_CLR; /**< DMA Channel Busy Register */
+ __IOM uint32_t CHDONE_CLR; /**< DMA Channel Linking Done Register */
+ __IOM uint32_t DBGHALT_CLR; /**< DMA Channel Debug Halt Register */
+ __IOM uint32_t SWREQ_CLR; /**< DMA Channel Software Transfer Request */
+ __IOM uint32_t REQDIS_CLR; /**< DMA Channel Request Disable Register */
+ __IM uint32_t REQPEND_CLR; /**< DMA Channel Requests Pending Register */
+ __IOM uint32_t LINKLOAD_CLR; /**< DMA Channel Link Load Register */
+ __IOM uint32_t REQCLEAR_CLR; /**< DMA Channel Request Clear Register */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
+ LDMA_CH_TypeDef CH_CLR[8U]; /**< DMA Channel Registers */
+ uint32_t RESERVED2[906U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< DMA Channel Request Clear Register */
+ __IOM uint32_t EN_TGL; /**< DMA module enable disable Register */
+ __IOM uint32_t CTRL_TGL; /**< DMA Control Register */
+ __IM uint32_t STATUS_TGL; /**< DMA Status Register */
+ __IOM uint32_t SYNCSWSET_TGL; /**< DMA Sync Trig Sw Set Register */
+ __IOM uint32_t SYNCSWCLR_TGL; /**< DMA Sync Trig Sw Clear register */
+ __IOM uint32_t SYNCHWEN_TGL; /**< DMA Sync HW trigger enable register */
+ __IOM uint32_t SYNCHWSEL_TGL; /**< DMA Sync HW trigger selection register */
+ __IM uint32_t SYNCSTATUS_TGL; /**< DMA Sync Trigger Status Register */
+ __IOM uint32_t CHEN_TGL; /**< DMA Channel Enable Register */
+ __IOM uint32_t CHDIS_TGL; /**< DMA Channel Disable Register */
+ __IM uint32_t CHSTATUS_TGL; /**< DMA Channel Status Register */
+ __IM uint32_t CHBUSY_TGL; /**< DMA Channel Busy Register */
+ __IOM uint32_t CHDONE_TGL; /**< DMA Channel Linking Done Register */
+ __IOM uint32_t DBGHALT_TGL; /**< DMA Channel Debug Halt Register */
+ __IOM uint32_t SWREQ_TGL; /**< DMA Channel Software Transfer Request */
+ __IOM uint32_t REQDIS_TGL; /**< DMA Channel Request Disable Register */
+ __IM uint32_t REQPEND_TGL; /**< DMA Channel Requests Pending Register */
+ __IOM uint32_t LINKLOAD_TGL; /**< DMA Channel Link Load Register */
+ __IOM uint32_t REQCLEAR_TGL; /**< DMA Channel Request Clear Register */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
+ LDMA_CH_TypeDef CH_TGL[8U]; /**< DMA Channel Registers */
+} LDMA_TypeDef;
+/** @} End of group EFR32MG24_LDMA */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_LDMA
+ * @{
+ * @defgroup EFR32MG24_LDMA_BitFields LDMA Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for LDMA IPVERSION */
+#define _LDMA_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LDMA_IPVERSION */
+#define _LDMA_IPVERSION_MASK 0x000000FFUL /**< Mask for LDMA_IPVERSION */
+#define _LDMA_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LDMA_IPVERSION */
+#define _LDMA_IPVERSION_IPVERSION_MASK 0xFFUL /**< Bit mask for LDMA_IPVERSION */
+#define _LDMA_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IPVERSION */
+#define LDMA_IPVERSION_IPVERSION_DEFAULT (_LDMA_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IPVERSION */
+
+/* Bit fields for LDMA EN */
+#define _LDMA_EN_RESETVALUE 0x00000000UL /**< Default value for LDMA_EN */
+#define _LDMA_EN_MASK 0x00000001UL /**< Mask for LDMA_EN */
+#define LDMA_EN_EN (0x1UL << 0) /**< LDMA module enable and disable register */
+#define _LDMA_EN_EN_SHIFT 0 /**< Shift value for LDMA_EN */
+#define _LDMA_EN_EN_MASK 0x1UL /**< Bit mask for LDMA_EN */
+#define _LDMA_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_EN */
+#define LDMA_EN_EN_DEFAULT (_LDMA_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_EN */
+
+/* Bit fields for LDMA CTRL */
+#define _LDMA_CTRL_RESETVALUE 0x1E000000UL /**< Default value for LDMA_CTRL */
+#define _LDMA_CTRL_MASK 0x9F000000UL /**< Mask for LDMA_CTRL */
+#define _LDMA_CTRL_NUMFIXED_SHIFT 24 /**< Shift value for LDMA_NUMFIXED */
+#define _LDMA_CTRL_NUMFIXED_MASK 0x1F000000UL /**< Bit mask for LDMA_NUMFIXED */
+#define _LDMA_CTRL_NUMFIXED_DEFAULT 0x0000001EUL /**< Mode DEFAULT for LDMA_CTRL */
+#define LDMA_CTRL_NUMFIXED_DEFAULT (_LDMA_CTRL_NUMFIXED_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CTRL */
+#define LDMA_CTRL_CORERST (0x1UL << 31) /**< Reset DMA controller */
+#define _LDMA_CTRL_CORERST_SHIFT 31 /**< Shift value for LDMA_CORERST */
+#define _LDMA_CTRL_CORERST_MASK 0x80000000UL /**< Bit mask for LDMA_CORERST */
+#define _LDMA_CTRL_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */
+#define LDMA_CTRL_CORERST_DEFAULT (_LDMA_CTRL_CORERST_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CTRL */
+
+/* Bit fields for LDMA STATUS */
+#define _LDMA_STATUS_RESETVALUE 0x1F100000UL /**< Default value for LDMA_STATUS */
+#define _LDMA_STATUS_MASK 0x1F1F1FFBUL /**< Mask for LDMA_STATUS */
+#define LDMA_STATUS_ANYBUSY (0x1UL << 0) /**< Any DMA Channel Busy */
+#define _LDMA_STATUS_ANYBUSY_SHIFT 0 /**< Shift value for LDMA_ANYBUSY */
+#define _LDMA_STATUS_ANYBUSY_MASK 0x1UL /**< Bit mask for LDMA_ANYBUSY */
+#define _LDMA_STATUS_ANYBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
+#define LDMA_STATUS_ANYBUSY_DEFAULT (_LDMA_STATUS_ANYBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_STATUS */
+#define LDMA_STATUS_ANYREQ (0x1UL << 1) /**< Any DMA Channel Request Pending */
+#define _LDMA_STATUS_ANYREQ_SHIFT 1 /**< Shift value for LDMA_ANYREQ */
+#define _LDMA_STATUS_ANYREQ_MASK 0x2UL /**< Bit mask for LDMA_ANYREQ */
+#define _LDMA_STATUS_ANYREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
+#define LDMA_STATUS_ANYREQ_DEFAULT (_LDMA_STATUS_ANYREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_STATUS */
+#define _LDMA_STATUS_CHGRANT_SHIFT 3 /**< Shift value for LDMA_CHGRANT */
+#define _LDMA_STATUS_CHGRANT_MASK 0xF8UL /**< Bit mask for LDMA_CHGRANT */
+#define _LDMA_STATUS_CHGRANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
+#define LDMA_STATUS_CHGRANT_DEFAULT (_LDMA_STATUS_CHGRANT_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_STATUS */
+#define _LDMA_STATUS_CHERROR_SHIFT 8 /**< Shift value for LDMA_CHERROR */
+#define _LDMA_STATUS_CHERROR_MASK 0x1F00UL /**< Bit mask for LDMA_CHERROR */
+#define _LDMA_STATUS_CHERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
+#define LDMA_STATUS_CHERROR_DEFAULT (_LDMA_STATUS_CHERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_STATUS */
+#define _LDMA_STATUS_FIFOLEVEL_SHIFT 16 /**< Shift value for LDMA_FIFOLEVEL */
+#define _LDMA_STATUS_FIFOLEVEL_MASK 0x1F0000UL /**< Bit mask for LDMA_FIFOLEVEL */
+#define _LDMA_STATUS_FIFOLEVEL_DEFAULT 0x00000010UL /**< Mode DEFAULT for LDMA_STATUS */
+#define LDMA_STATUS_FIFOLEVEL_DEFAULT (_LDMA_STATUS_FIFOLEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_STATUS */
+#define _LDMA_STATUS_CHNUM_SHIFT 24 /**< Shift value for LDMA_CHNUM */
+#define _LDMA_STATUS_CHNUM_MASK 0x1F000000UL /**< Bit mask for LDMA_CHNUM */
+#define _LDMA_STATUS_CHNUM_DEFAULT 0x0000001FUL /**< Mode DEFAULT for LDMA_STATUS */
+#define LDMA_STATUS_CHNUM_DEFAULT (_LDMA_STATUS_CHNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_STATUS */
+
+/* Bit fields for LDMA SYNCSWSET */
+#define _LDMA_SYNCSWSET_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWSET */
+#define _LDMA_SYNCSWSET_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWSET */
+#define _LDMA_SYNCSWSET_SYNCSWSET_SHIFT 0 /**< Shift value for LDMA_SYNCSWSET */
+#define _LDMA_SYNCSWSET_SYNCSWSET_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWSET */
+#define _LDMA_SYNCSWSET_SYNCSWSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWSET */
+#define LDMA_SYNCSWSET_SYNCSWSET_DEFAULT (_LDMA_SYNCSWSET_SYNCSWSET_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSWSET */
+
+/* Bit fields for LDMA SYNCSWCLR */
+#define _LDMA_SYNCSWCLR_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWCLR */
+#define _LDMA_SYNCSWCLR_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWCLR */
+#define _LDMA_SYNCSWCLR_SYNCSWCLR_SHIFT 0 /**< Shift value for LDMA_SYNCSWCLR */
+#define _LDMA_SYNCSWCLR_SYNCSWCLR_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWCLR */
+#define _LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWCLR */
+#define LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT (_LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSWCLR */
+
+/* Bit fields for LDMA SYNCHWEN */
+#define _LDMA_SYNCHWEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWEN */
+#define _LDMA_SYNCHWEN_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWEN */
+#define _LDMA_SYNCHWEN_SYNCSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCSETEN */
+#define _LDMA_SYNCHWEN_SYNCSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEN */
+#define _LDMA_SYNCHWEN_SYNCSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */
+#define LDMA_SYNCHWEN_SYNCSETEN_DEFAULT (_LDMA_SYNCHWEN_SYNCSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWEN */
+#define _LDMA_SYNCHWEN_SYNCCLREN_SHIFT 16 /**< Shift value for LDMA_SYNCCLREN */
+#define _LDMA_SYNCHWEN_SYNCCLREN_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREN */
+#define _LDMA_SYNCHWEN_SYNCCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */
+#define LDMA_SYNCHWEN_SYNCCLREN_DEFAULT (_LDMA_SYNCHWEN_SYNCCLREN_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_SYNCHWEN */
+
+/* Bit fields for LDMA SYNCHWSEL */
+#define _LDMA_SYNCHWSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWSEL */
+#define _LDMA_SYNCHWSEL_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWSEL */
+#define _LDMA_SYNCHWSEL_SYNCSETEDGE_SHIFT 0 /**< Shift value for LDMA_SYNCSETEDGE */
+#define _LDMA_SYNCHWSEL_SYNCSETEDGE_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEDGE */
+#define _LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */
+#define _LDMA_SYNCHWSEL_SYNCSETEDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */
+#define _LDMA_SYNCHWSEL_SYNCSETEDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */
+#define LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT (_LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWSEL */
+#define LDMA_SYNCHWSEL_SYNCSETEDGE_RISE (_LDMA_SYNCHWSEL_SYNCSETEDGE_RISE << 0) /**< Shifted mode RISE for LDMA_SYNCHWSEL */
+#define LDMA_SYNCHWSEL_SYNCSETEDGE_FALL (_LDMA_SYNCHWSEL_SYNCSETEDGE_FALL << 0) /**< Shifted mode FALL for LDMA_SYNCHWSEL */
+#define _LDMA_SYNCHWSEL_SYNCCLREDGE_SHIFT 16 /**< Shift value for LDMA_SYNCCLREDGE */
+#define _LDMA_SYNCHWSEL_SYNCCLREDGE_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREDGE */
+#define _LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */
+#define _LDMA_SYNCHWSEL_SYNCCLREDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */
+#define _LDMA_SYNCHWSEL_SYNCCLREDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */
+#define LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT (_LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_SYNCHWSEL */
+#define LDMA_SYNCHWSEL_SYNCCLREDGE_RISE (_LDMA_SYNCHWSEL_SYNCCLREDGE_RISE << 16) /**< Shifted mode RISE for LDMA_SYNCHWSEL */
+#define LDMA_SYNCHWSEL_SYNCCLREDGE_FALL (_LDMA_SYNCHWSEL_SYNCCLREDGE_FALL << 16) /**< Shifted mode FALL for LDMA_SYNCHWSEL */
+
+/* Bit fields for LDMA SYNCSTATUS */
+#define _LDMA_SYNCSTATUS_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSTATUS */
+#define _LDMA_SYNCSTATUS_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSTATUS */
+#define _LDMA_SYNCSTATUS_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */
+#define _LDMA_SYNCSTATUS_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */
+#define _LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSTATUS */
+#define LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT (_LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSTATUS */
+
+/* Bit fields for LDMA CHEN */
+#define _LDMA_CHEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHEN */
+#define _LDMA_CHEN_MASK 0x000000FFUL /**< Mask for LDMA_CHEN */
+#define _LDMA_CHEN_CHEN_SHIFT 0 /**< Shift value for LDMA_CHEN */
+#define _LDMA_CHEN_CHEN_MASK 0xFFUL /**< Bit mask for LDMA_CHEN */
+#define _LDMA_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHEN */
+#define LDMA_CHEN_CHEN_DEFAULT (_LDMA_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHEN */
+
+/* Bit fields for LDMA CHDIS */
+#define _LDMA_CHDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDIS */
+#define _LDMA_CHDIS_MASK 0x000000FFUL /**< Mask for LDMA_CHDIS */
+#define _LDMA_CHDIS_CHDIS_SHIFT 0 /**< Shift value for LDMA_CHDIS */
+#define _LDMA_CHDIS_CHDIS_MASK 0xFFUL /**< Bit mask for LDMA_CHDIS */
+#define _LDMA_CHDIS_CHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDIS */
+#define LDMA_CHDIS_CHDIS_DEFAULT (_LDMA_CHDIS_CHDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDIS */
+
+/* Bit fields for LDMA CHSTATUS */
+#define _LDMA_CHSTATUS_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHSTATUS */
+#define _LDMA_CHSTATUS_MASK 0x000000FFUL /**< Mask for LDMA_CHSTATUS */
+#define _LDMA_CHSTATUS_CHSTATUS_SHIFT 0 /**< Shift value for LDMA_CHSTATUS */
+#define _LDMA_CHSTATUS_CHSTATUS_MASK 0xFFUL /**< Bit mask for LDMA_CHSTATUS */
+#define _LDMA_CHSTATUS_CHSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHSTATUS */
+#define LDMA_CHSTATUS_CHSTATUS_DEFAULT (_LDMA_CHSTATUS_CHSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHSTATUS */
+
+/* Bit fields for LDMA CHBUSY */
+#define _LDMA_CHBUSY_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHBUSY */
+#define _LDMA_CHBUSY_MASK 0x000000FFUL /**< Mask for LDMA_CHBUSY */
+#define _LDMA_CHBUSY_BUSY_SHIFT 0 /**< Shift value for LDMA_BUSY */
+#define _LDMA_CHBUSY_BUSY_MASK 0xFFUL /**< Bit mask for LDMA_BUSY */
+#define _LDMA_CHBUSY_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHBUSY */
+#define LDMA_CHBUSY_BUSY_DEFAULT (_LDMA_CHBUSY_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHBUSY */
+
+/* Bit fields for LDMA CHDONE */
+#define _LDMA_CHDONE_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDONE */
+#define _LDMA_CHDONE_MASK 0x000000FFUL /**< Mask for LDMA_CHDONE */
+#define LDMA_CHDONE_CHDONE0 (0x1UL << 0) /**< DMA Channel Link done intr flag */
+#define _LDMA_CHDONE_CHDONE0_SHIFT 0 /**< Shift value for LDMA_CHDONE0 */
+#define _LDMA_CHDONE_CHDONE0_MASK 0x1UL /**< Bit mask for LDMA_CHDONE0 */
+#define _LDMA_CHDONE_CHDONE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */
+#define LDMA_CHDONE_CHDONE0_DEFAULT (_LDMA_CHDONE_CHDONE0_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDONE */
+#define LDMA_CHDONE_CHDONE1 (0x1UL << 1) /**< DMA Channel Link done intr flag */
+#define _LDMA_CHDONE_CHDONE1_SHIFT 1 /**< Shift value for LDMA_CHDONE1 */
+#define _LDMA_CHDONE_CHDONE1_MASK 0x2UL /**< Bit mask for LDMA_CHDONE1 */
+#define _LDMA_CHDONE_CHDONE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */
+#define LDMA_CHDONE_CHDONE1_DEFAULT (_LDMA_CHDONE_CHDONE1_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CHDONE */
+#define LDMA_CHDONE_CHDONE2 (0x1UL << 2) /**< DMA Channel Link done intr flag */
+#define _LDMA_CHDONE_CHDONE2_SHIFT 2 /**< Shift value for LDMA_CHDONE2 */
+#define _LDMA_CHDONE_CHDONE2_MASK 0x4UL /**< Bit mask for LDMA_CHDONE2 */
+#define _LDMA_CHDONE_CHDONE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */
+#define LDMA_CHDONE_CHDONE2_DEFAULT (_LDMA_CHDONE_CHDONE2_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CHDONE */
+#define LDMA_CHDONE_CHDONE3 (0x1UL << 3) /**< DMA Channel Link done intr flag */
+#define _LDMA_CHDONE_CHDONE3_SHIFT 3 /**< Shift value for LDMA_CHDONE3 */
+#define _LDMA_CHDONE_CHDONE3_MASK 0x8UL /**< Bit mask for LDMA_CHDONE3 */
+#define _LDMA_CHDONE_CHDONE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */
+#define LDMA_CHDONE_CHDONE3_DEFAULT (_LDMA_CHDONE_CHDONE3_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CHDONE */
+#define LDMA_CHDONE_CHDONE4 (0x1UL << 4) /**< DMA Channel Link done intr flag */
+#define _LDMA_CHDONE_CHDONE4_SHIFT 4 /**< Shift value for LDMA_CHDONE4 */
+#define _LDMA_CHDONE_CHDONE4_MASK 0x10UL /**< Bit mask for LDMA_CHDONE4 */
+#define _LDMA_CHDONE_CHDONE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */
+#define LDMA_CHDONE_CHDONE4_DEFAULT (_LDMA_CHDONE_CHDONE4_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CHDONE */
+#define LDMA_CHDONE_CHDONE5 (0x1UL << 5) /**< DMA Channel Link done intr flag */
+#define _LDMA_CHDONE_CHDONE5_SHIFT 5 /**< Shift value for LDMA_CHDONE5 */
+#define _LDMA_CHDONE_CHDONE5_MASK 0x20UL /**< Bit mask for LDMA_CHDONE5 */
+#define _LDMA_CHDONE_CHDONE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */
+#define LDMA_CHDONE_CHDONE5_DEFAULT (_LDMA_CHDONE_CHDONE5_DEFAULT << 5) /**< Shifted mode DEFAULT for LDMA_CHDONE */
+#define LDMA_CHDONE_CHDONE6 (0x1UL << 6) /**< DMA Channel Link done intr flag */
+#define _LDMA_CHDONE_CHDONE6_SHIFT 6 /**< Shift value for LDMA_CHDONE6 */
+#define _LDMA_CHDONE_CHDONE6_MASK 0x40UL /**< Bit mask for LDMA_CHDONE6 */
+#define _LDMA_CHDONE_CHDONE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */
+#define LDMA_CHDONE_CHDONE6_DEFAULT (_LDMA_CHDONE_CHDONE6_DEFAULT << 6) /**< Shifted mode DEFAULT for LDMA_CHDONE */
+#define LDMA_CHDONE_CHDONE7 (0x1UL << 7) /**< DMA Channel Link done intr flag */
+#define _LDMA_CHDONE_CHDONE7_SHIFT 7 /**< Shift value for LDMA_CHDONE7 */
+#define _LDMA_CHDONE_CHDONE7_MASK 0x80UL /**< Bit mask for LDMA_CHDONE7 */
+#define _LDMA_CHDONE_CHDONE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */
+#define LDMA_CHDONE_CHDONE7_DEFAULT (_LDMA_CHDONE_CHDONE7_DEFAULT << 7) /**< Shifted mode DEFAULT for LDMA_CHDONE */
+
+/* Bit fields for LDMA DBGHALT */
+#define _LDMA_DBGHALT_RESETVALUE 0x00000000UL /**< Default value for LDMA_DBGHALT */
+#define _LDMA_DBGHALT_MASK 0x000000FFUL /**< Mask for LDMA_DBGHALT */
+#define _LDMA_DBGHALT_DBGHALT_SHIFT 0 /**< Shift value for LDMA_DBGHALT */
+#define _LDMA_DBGHALT_DBGHALT_MASK 0xFFUL /**< Bit mask for LDMA_DBGHALT */
+#define _LDMA_DBGHALT_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_DBGHALT */
+#define LDMA_DBGHALT_DBGHALT_DEFAULT (_LDMA_DBGHALT_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_DBGHALT */
+
+/* Bit fields for LDMA SWREQ */
+#define _LDMA_SWREQ_RESETVALUE 0x00000000UL /**< Default value for LDMA_SWREQ */
+#define _LDMA_SWREQ_MASK 0x000000FFUL /**< Mask for LDMA_SWREQ */
+#define _LDMA_SWREQ_SWREQ_SHIFT 0 /**< Shift value for LDMA_SWREQ */
+#define _LDMA_SWREQ_SWREQ_MASK 0xFFUL /**< Bit mask for LDMA_SWREQ */
+#define _LDMA_SWREQ_SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SWREQ */
+#define LDMA_SWREQ_SWREQ_DEFAULT (_LDMA_SWREQ_SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SWREQ */
+
+/* Bit fields for LDMA REQDIS */
+#define _LDMA_REQDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQDIS */
+#define _LDMA_REQDIS_MASK 0x000000FFUL /**< Mask for LDMA_REQDIS */
+#define _LDMA_REQDIS_REQDIS_SHIFT 0 /**< Shift value for LDMA_REQDIS */
+#define _LDMA_REQDIS_REQDIS_MASK 0xFFUL /**< Bit mask for LDMA_REQDIS */
+#define _LDMA_REQDIS_REQDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQDIS */
+#define LDMA_REQDIS_REQDIS_DEFAULT (_LDMA_REQDIS_REQDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQDIS */
+
+/* Bit fields for LDMA REQPEND */
+#define _LDMA_REQPEND_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQPEND */
+#define _LDMA_REQPEND_MASK 0x000000FFUL /**< Mask for LDMA_REQPEND */
+#define _LDMA_REQPEND_REQPEND_SHIFT 0 /**< Shift value for LDMA_REQPEND */
+#define _LDMA_REQPEND_REQPEND_MASK 0xFFUL /**< Bit mask for LDMA_REQPEND */
+#define _LDMA_REQPEND_REQPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQPEND */
+#define LDMA_REQPEND_REQPEND_DEFAULT (_LDMA_REQPEND_REQPEND_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQPEND */
+
+/* Bit fields for LDMA LINKLOAD */
+#define _LDMA_LINKLOAD_RESETVALUE 0x00000000UL /**< Default value for LDMA_LINKLOAD */
+#define _LDMA_LINKLOAD_MASK 0x000000FFUL /**< Mask for LDMA_LINKLOAD */
+#define _LDMA_LINKLOAD_LINKLOAD_SHIFT 0 /**< Shift value for LDMA_LINKLOAD */
+#define _LDMA_LINKLOAD_LINKLOAD_MASK 0xFFUL /**< Bit mask for LDMA_LINKLOAD */
+#define _LDMA_LINKLOAD_LINKLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_LINKLOAD */
+#define LDMA_LINKLOAD_LINKLOAD_DEFAULT (_LDMA_LINKLOAD_LINKLOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_LINKLOAD */
+
+/* Bit fields for LDMA REQCLEAR */
+#define _LDMA_REQCLEAR_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQCLEAR */
+#define _LDMA_REQCLEAR_MASK 0x000000FFUL /**< Mask for LDMA_REQCLEAR */
+#define _LDMA_REQCLEAR_REQCLEAR_SHIFT 0 /**< Shift value for LDMA_REQCLEAR */
+#define _LDMA_REQCLEAR_REQCLEAR_MASK 0xFFUL /**< Bit mask for LDMA_REQCLEAR */
+#define _LDMA_REQCLEAR_REQCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQCLEAR */
+#define LDMA_REQCLEAR_REQCLEAR_DEFAULT (_LDMA_REQCLEAR_REQCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQCLEAR */
+
+/* Bit fields for LDMA IF */
+#define _LDMA_IF_RESETVALUE 0x00000000UL /**< Default value for LDMA_IF */
+#define _LDMA_IF_MASK 0x800000FFUL /**< Mask for LDMA_IF */
+#define LDMA_IF_DONE0 (0x1UL << 0) /**< DMA Structure Operation Done */
+#define _LDMA_IF_DONE0_SHIFT 0 /**< Shift value for LDMA_DONE0 */
+#define _LDMA_IF_DONE0_MASK 0x1UL /**< Bit mask for LDMA_DONE0 */
+#define _LDMA_IF_DONE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
+#define LDMA_IF_DONE0_DEFAULT (_LDMA_IF_DONE0_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IF */
+#define LDMA_IF_DONE1 (0x1UL << 1) /**< DMA Structure Operation Done */
+#define _LDMA_IF_DONE1_SHIFT 1 /**< Shift value for LDMA_DONE1 */
+#define _LDMA_IF_DONE1_MASK 0x2UL /**< Bit mask for LDMA_DONE1 */
+#define _LDMA_IF_DONE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
+#define LDMA_IF_DONE1_DEFAULT (_LDMA_IF_DONE1_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_IF */
+#define LDMA_IF_DONE2 (0x1UL << 2) /**< DMA Structure Operation Done */
+#define _LDMA_IF_DONE2_SHIFT 2 /**< Shift value for LDMA_DONE2 */
+#define _LDMA_IF_DONE2_MASK 0x4UL /**< Bit mask for LDMA_DONE2 */
+#define _LDMA_IF_DONE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
+#define LDMA_IF_DONE2_DEFAULT (_LDMA_IF_DONE2_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_IF */
+#define LDMA_IF_DONE3 (0x1UL << 3) /**< DMA Structure Operation Done */
+#define _LDMA_IF_DONE3_SHIFT 3 /**< Shift value for LDMA_DONE3 */
+#define _LDMA_IF_DONE3_MASK 0x8UL /**< Bit mask for LDMA_DONE3 */
+#define _LDMA_IF_DONE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
+#define LDMA_IF_DONE3_DEFAULT (_LDMA_IF_DONE3_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_IF */
+#define LDMA_IF_DONE4 (0x1UL << 4) /**< DMA Structure Operation Done */
+#define _LDMA_IF_DONE4_SHIFT 4 /**< Shift value for LDMA_DONE4 */
+#define _LDMA_IF_DONE4_MASK 0x10UL /**< Bit mask for LDMA_DONE4 */
+#define _LDMA_IF_DONE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
+#define LDMA_IF_DONE4_DEFAULT (_LDMA_IF_DONE4_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_IF */
+#define LDMA_IF_DONE5 (0x1UL << 5) /**< DMA Structure Operation Done */
+#define _LDMA_IF_DONE5_SHIFT 5 /**< Shift value for LDMA_DONE5 */
+#define _LDMA_IF_DONE5_MASK 0x20UL /**< Bit mask for LDMA_DONE5 */
+#define _LDMA_IF_DONE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
+#define LDMA_IF_DONE5_DEFAULT (_LDMA_IF_DONE5_DEFAULT << 5) /**< Shifted mode DEFAULT for LDMA_IF */
+#define LDMA_IF_DONE6 (0x1UL << 6) /**< DMA Structure Operation Done */
+#define _LDMA_IF_DONE6_SHIFT 6 /**< Shift value for LDMA_DONE6 */
+#define _LDMA_IF_DONE6_MASK 0x40UL /**< Bit mask for LDMA_DONE6 */
+#define _LDMA_IF_DONE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
+#define LDMA_IF_DONE6_DEFAULT (_LDMA_IF_DONE6_DEFAULT << 6) /**< Shifted mode DEFAULT for LDMA_IF */
+#define LDMA_IF_DONE7 (0x1UL << 7) /**< DMA Structure Operation Done */
+#define _LDMA_IF_DONE7_SHIFT 7 /**< Shift value for LDMA_DONE7 */
+#define _LDMA_IF_DONE7_MASK 0x80UL /**< Bit mask for LDMA_DONE7 */
+#define _LDMA_IF_DONE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
+#define LDMA_IF_DONE7_DEFAULT (_LDMA_IF_DONE7_DEFAULT << 7) /**< Shifted mode DEFAULT for LDMA_IF */
+#define LDMA_IF_ERROR (0x1UL << 31) /**< Error Flag */
+#define _LDMA_IF_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
+#define _LDMA_IF_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
+#define _LDMA_IF_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
+#define LDMA_IF_ERROR_DEFAULT (_LDMA_IF_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IF */
+
+/* Bit fields for LDMA IEN */
+#define _LDMA_IEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_IEN */
+#define _LDMA_IEN_MASK 0x800000FFUL /**< Mask for LDMA_IEN */
+#define _LDMA_IEN_CHDONE_SHIFT 0 /**< Shift value for LDMA_CHDONE */
+#define _LDMA_IEN_CHDONE_MASK 0xFFUL /**< Bit mask for LDMA_CHDONE */
+#define _LDMA_IEN_CHDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */
+#define LDMA_IEN_CHDONE_DEFAULT (_LDMA_IEN_CHDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IEN */
+#define LDMA_IEN_ERROR (0x1UL << 31) /**< Enable or disable the error interrupt */
+#define _LDMA_IEN_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
+#define _LDMA_IEN_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
+#define _LDMA_IEN_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */
+#define LDMA_IEN_ERROR_DEFAULT (_LDMA_IEN_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IEN */
+
+/* Bit fields for LDMA CH_CFG */
+#define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */
+#define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */
+#define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */
+#define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */
+#define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */
+#define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */
+#define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */
+#define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */
+#define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */
+#define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */
+#define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */
+#define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */
+#define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */
+#define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */
+#define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */
+#define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */
+#define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */
+#define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */
+#define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */
+#define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */
+#define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */
+#define LDMA_CH_CFG_SRCINCSIGN_POSITIVE (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20) /**< Shifted mode POSITIVE for LDMA_CH_CFG */
+#define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */
+#define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */
+#define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */
+#define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */
+#define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */
+#define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */
+#define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */
+#define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */
+#define LDMA_CH_CFG_DSTINCSIGN_POSITIVE (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21) /**< Shifted mode POSITIVE for LDMA_CH_CFG */
+#define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */
+
+/* Bit fields for LDMA CH_LOOP */
+#define _LDMA_CH_LOOP_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LOOP */
+#define _LDMA_CH_LOOP_MASK 0x000000FFUL /**< Mask for LDMA_CH_LOOP */
+#define _LDMA_CH_LOOP_LOOPCNT_SHIFT 0 /**< Shift value for LDMA_LOOPCNT */
+#define _LDMA_CH_LOOP_LOOPCNT_MASK 0xFFUL /**< Bit mask for LDMA_LOOPCNT */
+#define _LDMA_CH_LOOP_LOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LOOP */
+#define LDMA_CH_LOOP_LOOPCNT_DEFAULT (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LOOP */
+
+/* Bit fields for LDMA CH_CTRL */
+#define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */
+#define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */
+#define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0) /**< Shifted mode SYNCHRONIZE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */
+#define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */
+#define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */
+#define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */
+#define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */
+#define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */
+#define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */
+#define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */
+#define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */
+#define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */
+#define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DONEIEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set En */
+#define _LDMA_CH_CTRL_DONEIEN_SHIFT 20 /**< Shift value for LDMA_DONEIEN */
+#define _LDMA_CH_CTRL_DONEIEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIEN */
+#define _LDMA_CH_CTRL_DONEIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DONEIEN_DEFAULT (_LDMA_CH_CTRL_DONEIEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */
+#define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */
+#define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */
+#define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */
+#define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */
+#define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */
+#define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */
+#define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */
+#define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */
+#define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */
+#define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */
+#define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */
+#define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */
+#define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */
+#define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */
+#define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */
+#define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */
+#define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */
+#define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */
+#define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */
+#define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */
+#define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */
+#define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */
+#define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */
+
+/* Bit fields for LDMA CH_SRC */
+#define _LDMA_CH_SRC_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_SRC */
+#define _LDMA_CH_SRC_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_SRC */
+#define _LDMA_CH_SRC_SRCADDR_SHIFT 0 /**< Shift value for LDMA_SRCADDR */
+#define _LDMA_CH_SRC_SRCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_SRCADDR */
+#define _LDMA_CH_SRC_SRCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_SRC */
+#define LDMA_CH_SRC_SRCADDR_DEFAULT (_LDMA_CH_SRC_SRCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_SRC */
+
+/* Bit fields for LDMA CH_DST */
+#define _LDMA_CH_DST_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_DST */
+#define _LDMA_CH_DST_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_DST */
+#define _LDMA_CH_DST_DSTADDR_SHIFT 0 /**< Shift value for LDMA_DSTADDR */
+#define _LDMA_CH_DST_DSTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_DSTADDR */
+#define _LDMA_CH_DST_DSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_DST */
+#define LDMA_CH_DST_DSTADDR_DEFAULT (_LDMA_CH_DST_DSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_DST */
+
+/* Bit fields for LDMA CH_LINK */
+#define _LDMA_CH_LINK_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LINK */
+#define _LDMA_CH_LINK_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_LINK */
+#define LDMA_CH_LINK_LINKMODE (0x1UL << 0) /**< Link Structure Addressing Mode */
+#define _LDMA_CH_LINK_LINKMODE_SHIFT 0 /**< Shift value for LDMA_LINKMODE */
+#define _LDMA_CH_LINK_LINKMODE_MASK 0x1UL /**< Bit mask for LDMA_LINKMODE */
+#define _LDMA_CH_LINK_LINKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */
+#define _LDMA_CH_LINK_LINKMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_LINK */
+#define _LDMA_CH_LINK_LINKMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_LINK */
+#define LDMA_CH_LINK_LINKMODE_DEFAULT (_LDMA_CH_LINK_LINKMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LINK */
+#define LDMA_CH_LINK_LINKMODE_ABSOLUTE (_LDMA_CH_LINK_LINKMODE_ABSOLUTE << 0) /**< Shifted mode ABSOLUTE for LDMA_CH_LINK */
+#define LDMA_CH_LINK_LINKMODE_RELATIVE (_LDMA_CH_LINK_LINKMODE_RELATIVE << 0) /**< Shifted mode RELATIVE for LDMA_CH_LINK */
+#define LDMA_CH_LINK_LINK (0x1UL << 1) /**< Link Next Structure */
+#define _LDMA_CH_LINK_LINK_SHIFT 1 /**< Shift value for LDMA_LINK */
+#define _LDMA_CH_LINK_LINK_MASK 0x2UL /**< Bit mask for LDMA_LINK */
+#define _LDMA_CH_LINK_LINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */
+#define LDMA_CH_LINK_LINK_DEFAULT (_LDMA_CH_LINK_LINK_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CH_LINK */
+#define _LDMA_CH_LINK_LINKADDR_SHIFT 2 /**< Shift value for LDMA_LINKADDR */
+#define _LDMA_CH_LINK_LINKADDR_MASK 0xFFFFFFFCUL /**< Bit mask for LDMA_LINKADDR */
+#define _LDMA_CH_LINK_LINKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */
+#define LDMA_CH_LINK_LINKADDR_DEFAULT (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CH_LINK */
+
+/** @} End of group EFR32MG24_LDMA_BitFields */
+/** @} End of group EFR32MG24_LDMA */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_LDMA_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_ldmaxbar.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_ldmaxbar.h
new file mode 100644
index 00000000..9597832b
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_ldmaxbar.h
@@ -0,0 +1,96 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 LDMAXBAR register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_LDMAXBAR_H
+#define EFR32MG24_LDMAXBAR_H
+#define LDMAXBAR_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_LDMAXBAR LDMAXBAR
+ * @{
+ * @brief EFR32MG24 LDMAXBAR Register Declaration.
+ *****************************************************************************/
+
+/** LDMAXBAR CH Register Group Declaration. */
+typedef struct {
+ __IOM uint32_t REQSEL; /**< Channel Peripheral Request Select Reg... */
+} LDMAXBAR_CH_TypeDef;
+
+/** LDMAXBAR Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IP veersion ID */
+ LDMAXBAR_CH_TypeDef CH[8U]; /**< DMA Channel Registers */
+ uint32_t RESERVED0[1015U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP veersion ID */
+ LDMAXBAR_CH_TypeDef CH_SET[8U]; /**< DMA Channel Registers */
+ uint32_t RESERVED1[1015U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP veersion ID */
+ LDMAXBAR_CH_TypeDef CH_CLR[8U]; /**< DMA Channel Registers */
+ uint32_t RESERVED2[1015U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP veersion ID */
+ LDMAXBAR_CH_TypeDef CH_TGL[8U]; /**< DMA Channel Registers */
+} LDMAXBAR_TypeDef;
+/** @} End of group EFR32MG24_LDMAXBAR */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_LDMAXBAR
+ * @{
+ * @defgroup EFR32MG24_LDMAXBAR_BitFields LDMAXBAR Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for LDMAXBAR IPVERSION */
+#define _LDMAXBAR_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for LDMAXBAR_IPVERSION */
+#define _LDMAXBAR_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LDMAXBAR_IPVERSION */
+#define _LDMAXBAR_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LDMAXBAR_IPVERSION */
+#define _LDMAXBAR_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LDMAXBAR_IPVERSION */
+#define _LDMAXBAR_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for LDMAXBAR_IPVERSION */
+#define LDMAXBAR_IPVERSION_IPVERSION_DEFAULT (_LDMAXBAR_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMAXBAR_IPVERSION */
+
+/* Bit fields for LDMAXBAR CH_REQSEL */
+#define _LDMAXBAR_CH_REQSEL_RESETVALUE 0x00000000UL /**< Default value for LDMAXBAR_CH_REQSEL */
+#define _LDMAXBAR_CH_REQSEL_MASK 0x003F000FUL /**< Mask for LDMAXBAR_CH_REQSEL */
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_SHIFT 0 /**< Shift value for LDMAXBAR_SIGSEL */
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_MASK 0xFUL /**< Bit mask for LDMAXBAR_SIGSEL */
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMAXBAR_CH_REQSEL */
+#define LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT (_LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMAXBAR_CH_REQSEL */
+#define _LDMAXBAR_CH_REQSEL_SOURCESEL_SHIFT 16 /**< Shift value for LDMAXBAR_SOURCESEL */
+#define _LDMAXBAR_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for LDMAXBAR_SOURCESEL */
+#define _LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMAXBAR_CH_REQSEL */
+#define LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT (_LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMAXBAR_CH_REQSEL */
+
+/** @} End of group EFR32MG24_LDMAXBAR_BitFields */
+/** @} End of group EFR32MG24_LDMAXBAR */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_LDMAXBAR_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_ldmaxbar_defines.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_ldmaxbar_defines.h
new file mode 100644
index 00000000..a5f92e25
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_ldmaxbar_defines.h
@@ -0,0 +1,178 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 LDMA XBAR channel request soruce definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+/* Module source selection indices */
+#define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */
+#define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */
+#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 0x00000002UL /**< Mode TIMER0 for LDMAXBAR_CH_REQSEL */
+#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 0x00000003UL /**< Mode TIMER1 for LDMAXBAR_CH_REQSEL */
+#define _LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 0x00000004UL /**< Mode USART0 for LDMAXBAR_CH_REQSEL */
+#define _LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 0x00000005UL /**< Mode I2C0 for LDMAXBAR_CH_REQSEL */
+#define _LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 0x00000006UL /**< Mode I2C1 for LDMAXBAR_CH_REQSEL */
+#define _LDMAXBAR_CH_REQSEL_SOURCESEL_AGC 0x00000007UL /**< Mode AGC for LDMAXBAR_CH_REQSEL */
+#define _LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER 0x00000008UL /**< Mode PROTIMER for LDMAXBAR_CH_REQSEL */
+#define _LDMAXBAR_CH_REQSEL_SOURCESEL_MODEM 0x00000009UL /**< Mode MODEM for LDMAXBAR_CH_REQSEL */
+#define _LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 0x0000000aUL /**< Mode IADC0 for LDMAXBAR_CH_REQSEL */
+#define _LDMAXBAR_CH_REQSEL_SOURCESEL_MSC 0x0000000bUL /**< Mode MSC for LDMAXBAR_CH_REQSEL */
+#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 0x0000000cUL /**< Mode TIMER2 for LDMAXBAR_CH_REQSEL */
+#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 0x0000000dUL /**< Mode TIMER3 for LDMAXBAR_CH_REQSEL */
+#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 0x0000000eUL /**< Mode TIMER4 for LDMAXBAR_CH_REQSEL */
+#define _LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 0x0000000fUL /**< Mode EUSART0 for LDMAXBAR_CH_REQSEL */
+#define _LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 0x00000010UL /**< Mode EUSART1 for LDMAXBAR_CH_REQSEL */
+#define _LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0 0x00000011UL /**< Mode VDAC0 for LDMAXBAR_CH_REQSEL */
+#define _LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC1 0x00000012UL /**< Mode VDAC1 for LDMAXBAR_CH_REQSEL */
+
+/* Shifted source selection indices */
+#define LDMAXBAR_CH_REQSEL_SOURCESEL_NONE (_LDMAXBAR_CH_REQSEL_SOURCESEL_NONE << 16)
+#define LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR (_LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR << 16) /**< Shifted Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */
+#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 << 16) /**< Shifted Mode TIMER0 for LDMAXBAR_CH_REQSEL */
+#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 << 16) /**< Shifted Mode TIMER1 for LDMAXBAR_CH_REQSEL */
+#define LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 << 16) /**< Shifted Mode USART0 for LDMAXBAR_CH_REQSEL */
+#define LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 << 16) /**< Shifted Mode I2C0 for LDMAXBAR_CH_REQSEL */
+#define LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 << 16) /**< Shifted Mode I2C1 for LDMAXBAR_CH_REQSEL */
+#define LDMAXBAR_CH_REQSEL_SOURCESEL_AGC (_LDMAXBAR_CH_REQSEL_SOURCESEL_AGC << 16) /**< Shifted Mode AGC for LDMAXBAR_CH_REQSEL */
+#define LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER (_LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER << 16) /**< Shifted Mode PROTIMER for LDMAXBAR_CH_REQSEL */
+#define LDMAXBAR_CH_REQSEL_SOURCESEL_MODEM (_LDMAXBAR_CH_REQSEL_SOURCESEL_MODEM << 16) /**< Shifted Mode MODEM for LDMAXBAR_CH_REQSEL */
+#define LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 << 16) /**< Shifted Mode IADC0 for LDMAXBAR_CH_REQSEL */
+#define LDMAXBAR_CH_REQSEL_SOURCESEL_MSC (_LDMAXBAR_CH_REQSEL_SOURCESEL_MSC << 16) /**< Shifted Mode MSC for LDMAXBAR_CH_REQSEL */
+#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 << 16) /**< Shifted Mode TIMER2 for LDMAXBAR_CH_REQSEL */
+#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 << 16) /**< Shifted Mode TIMER3 for LDMAXBAR_CH_REQSEL */
+#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 << 16) /**< Shifted Mode TIMER4 for LDMAXBAR_CH_REQSEL */
+#define LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 << 16) /**< Shifted Mode EUSART0 for LDMAXBAR_CH_REQSEL */
+#define LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 << 16) /**< Shifted Mode EUSART1 for LDMAXBAR_CH_REQSEL */
+#define LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0 << 16) /**< Shifted Mode VDAC0 for LDMAXBAR_CH_REQSEL */
+#define LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC1 << 16) /**< Shifted Mode VDAC1 for LDMAXBAR_CH_REQSEL */
+
+/* Module signal selection indices */
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 0x00000000UL /** Mode LDMAXBARPRSREQ0 for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 0x00000001UL /** Mode LDMAXBARPRSREQ1 for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 0x00000000UL /** Mode TIMER0CC0 for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 0x00000001UL /** Mode TIMER0CC1 for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 0x00000002UL /** Mode TIMER0CC2 for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF 0x00000003UL /** Mode TIMER0UFOF for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 0x00000000UL /** Mode TIMER1CC0 for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 0x00000001UL /** Mode TIMER1CC1 for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 0x00000002UL /** Mode TIMER1CC2 for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF 0x00000003UL /** Mode TIMER1UFOF for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV 0x00000000UL /** Mode USART0RXDATAV for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT 0x00000001UL /** Mode USART0RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL 0x00000002UL /** Mode USART0TXBL for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT 0x00000003UL /** Mode USART0TXBLRIGHT for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY 0x00000004UL /** Mode USART0TXEMPTY for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV 0x00000000UL /** Mode I2C0RXDATAV for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL 0x00000001UL /** Mode I2C0TXBL for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV 0x00000000UL /** Mode I2C1RXDATAV for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL 0x00000001UL /** Mode I2C1TXBL for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI 0x00000000UL /** Mode AGCRSSI for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF 0x00000000UL /** Mode PROTIMERBOF for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0 0x00000001UL /** Mode PROTIMERCC0 for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1 0x00000002UL /** Mode PROTIMERCC1 for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2 0x00000003UL /** Mode PROTIMERCC2 for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3 0x00000004UL /** Mode PROTIMERCC3 for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4 0x00000005UL /** Mode PROTIMERCC4 for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF 0x00000006UL /** Mode PROTIMERPOF for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF 0x00000007UL /** Mode PROTIMERWOF for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG 0x00000000UL /** Mode MODEMDEBUG for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN 0x00000000UL /** Mode IADC0IADC_SCAN for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE 0x00000001UL /** Mode IADC0IADC_SINGLE for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA 0x00000000UL /** Mode MSCWDATA for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 0x00000000UL /** Mode TIMER2CC0 for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 0x00000001UL /** Mode TIMER2CC1 for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 0x00000002UL /** Mode TIMER2CC2 for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF 0x00000003UL /** Mode TIMER2UFOF for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 0x00000000UL /** Mode TIMER3CC0 for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 0x00000001UL /** Mode TIMER3CC1 for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 0x00000002UL /** Mode TIMER3CC2 for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF 0x00000003UL /** Mode TIMER3UFOF for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 0x00000000UL /** Mode TIMER4CC0 for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 0x00000001UL /** Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 0x00000002UL /** Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF 0x00000003UL /** Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL 0x00000000UL /** Mode EUSART0RXFL for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL 0x00000001UL /** Mode EUSART0TXFL for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL 0x00000000UL /** Mode EUSART1RXFL for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL 0x00000001UL /** Mode EUSART1TXFL for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ 0x00000000UL /** Mode VDAC0CH0_REQ for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ 0x00000001UL /** Mode VDAC0CH1_REQ for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ 0x00000000UL /** Mode VDAC1CH0_REQ for LDMAXBAR_CH_REQSEL**/
+#define _LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ 0x00000001UL /** Mode VDAC1CH1_REQ for LDMAXBAR_CH_REQSEL**/
+
+/* Shifted Module signal selection indices */
+#define LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 (_LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 << 0) /** Shifted Mode LDMAXBARPRSREQ0 for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 (_LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 << 0) /** Shifted Mode LDMAXBARPRSREQ1 for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 << 0) /** Shifted Mode TIMER0CC0 for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 << 0) /** Shifted Mode TIMER0CC1 for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 << 0) /** Shifted Mode TIMER0CC2 for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF << 0) /** Shifted Mode TIMER0UFOF for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 << 0) /** Shifted Mode TIMER1CC0 for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 << 0) /** Shifted Mode TIMER1CC1 for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 << 0) /** Shifted Mode TIMER1CC2 for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF << 0) /** Shifted Mode TIMER1UFOF for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV << 0) /** Shifted Mode USART0RXDATAV for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT << 0) /** Shifted Mode USART0RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL << 0) /** Shifted Mode USART0TXBL for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT << 0) /** Shifted Mode USART0TXBLRIGHT for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY << 0) /** Shifted Mode USART0TXEMPTY for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV << 0) /** Shifted Mode I2C0RXDATAV for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL << 0) /** Shifted Mode I2C0TXBL for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV << 0) /** Shifted Mode I2C1RXDATAV for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL << 0) /** Shifted Mode I2C1TXBL for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI (_LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI << 0) /** Shifted Mode AGCRSSI for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF (_LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF << 0) /** Shifted Mode PROTIMERBOF for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0 << 0) /** Shifted Mode PROTIMERCC0 for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1 << 0) /** Shifted Mode PROTIMERCC1 for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2 << 0) /** Shifted Mode PROTIMERCC2 for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3 (_LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3 << 0) /** Shifted Mode PROTIMERCC3 for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4 (_LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4 << 0) /** Shifted Mode PROTIMERCC4 for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF (_LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF << 0) /** Shifted Mode PROTIMERPOF for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF (_LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF << 0) /** Shifted Mode PROTIMERWOF for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG (_LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG << 0) /** Shifted Mode MODEMDEBUG for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN (_LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN << 0) /** Shifted Mode IADC0IADC_SCAN for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE (_LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE << 0) /** Shifted Mode IADC0IADC_SINGLE for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA (_LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA << 0) /** Shifted Mode MSCWDATA for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 << 0) /** Shifted Mode TIMER2CC0 for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 << 0) /** Shifted Mode TIMER2CC1 for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 << 0) /** Shifted Mode TIMER2CC2 for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF << 0) /** Shifted Mode TIMER2UFOF for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 << 0) /** Shifted Mode TIMER3CC0 for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 << 0) /** Shifted Mode TIMER3CC1 for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 << 0) /** Shifted Mode TIMER3CC2 for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF << 0) /** Shifted Mode TIMER3UFOF for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 << 0) /** Shifted Mode TIMER4CC0 for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 << 0) /** Shifted Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 << 0) /** Shifted Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF << 0) /** Shifted Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL << 0) /** Shifted Mode EUSART0RXFL for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL << 0) /** Shifted Mode EUSART0TXFL for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL << 0) /** Shifted Mode EUSART1RXFL for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL << 0) /** Shifted Mode EUSART1TXFL for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ << 0) /** Shifted Mode VDAC0CH0_REQ for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ << 0) /** Shifted Mode VDAC0CH1_REQ for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ << 0) /** Shifted Mode VDAC1CH0_REQ for LDMAXBAR_CH_REQSEL**/
+#define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ << 0) /** Shifted Mode VDAC1CH1_REQ for LDMAXBAR_CH_REQSEL**/
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_letimer.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_letimer.h
new file mode 100644
index 00000000..7439682a
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_letimer.h
@@ -0,0 +1,534 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 LETIMER register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_LETIMER_H
+#define EFR32MG24_LETIMER_H
+#define LETIMER_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_LETIMER LETIMER
+ * @{
+ * @brief EFR32MG24 LETIMER Register Declaration.
+ *****************************************************************************/
+
+/** LETIMER Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IP version */
+ __IOM uint32_t EN; /**< module en */
+ __IOM uint32_t SWRST; /**< Software Reset Register */
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IOM uint32_t CNT; /**< Counter Value Register */
+ __IOM uint32_t COMP0; /**< Compare Value Register 0 */
+ __IOM uint32_t COMP1; /**< Compare Value Register 1 */
+ __IOM uint32_t TOP; /**< Counter TOP Value Register */
+ __IOM uint32_t TOPBUFF; /**< Buffered Counter TOP Value */
+ __IOM uint32_t REP0; /**< Repeat Counter Register 0 */
+ __IOM uint32_t REP1; /**< Repeat Counter Register 1 */
+ __IOM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IOM uint32_t LOCK; /**< Configuration Lock Register */
+ __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
+ uint32_t RESERVED0[3U]; /**< Reserved for future use */
+ __IOM uint32_t PRSMODE; /**< PRS Input mode select Register */
+ uint32_t RESERVED1[1003U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP version */
+ __IOM uint32_t EN_SET; /**< module en */
+ __IOM uint32_t SWRST_SET; /**< Software Reset Register */
+ __IOM uint32_t CTRL_SET; /**< Control Register */
+ __IOM uint32_t CMD_SET; /**< Command Register */
+ __IM uint32_t STATUS_SET; /**< Status Register */
+ __IOM uint32_t CNT_SET; /**< Counter Value Register */
+ __IOM uint32_t COMP0_SET; /**< Compare Value Register 0 */
+ __IOM uint32_t COMP1_SET; /**< Compare Value Register 1 */
+ __IOM uint32_t TOP_SET; /**< Counter TOP Value Register */
+ __IOM uint32_t TOPBUFF_SET; /**< Buffered Counter TOP Value */
+ __IOM uint32_t REP0_SET; /**< Repeat Counter Register 0 */
+ __IOM uint32_t REP1_SET; /**< Repeat Counter Register 1 */
+ __IOM uint32_t IF_SET; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
+ __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */
+ __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */
+ uint32_t RESERVED2[3U]; /**< Reserved for future use */
+ __IOM uint32_t PRSMODE_SET; /**< PRS Input mode select Register */
+ uint32_t RESERVED3[1003U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP version */
+ __IOM uint32_t EN_CLR; /**< module en */
+ __IOM uint32_t SWRST_CLR; /**< Software Reset Register */
+ __IOM uint32_t CTRL_CLR; /**< Control Register */
+ __IOM uint32_t CMD_CLR; /**< Command Register */
+ __IM uint32_t STATUS_CLR; /**< Status Register */
+ __IOM uint32_t CNT_CLR; /**< Counter Value Register */
+ __IOM uint32_t COMP0_CLR; /**< Compare Value Register 0 */
+ __IOM uint32_t COMP1_CLR; /**< Compare Value Register 1 */
+ __IOM uint32_t TOP_CLR; /**< Counter TOP Value Register */
+ __IOM uint32_t TOPBUFF_CLR; /**< Buffered Counter TOP Value */
+ __IOM uint32_t REP0_CLR; /**< Repeat Counter Register 0 */
+ __IOM uint32_t REP1_CLR; /**< Repeat Counter Register 1 */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
+ __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */
+ __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */
+ uint32_t RESERVED4[3U]; /**< Reserved for future use */
+ __IOM uint32_t PRSMODE_CLR; /**< PRS Input mode select Register */
+ uint32_t RESERVED5[1003U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP version */
+ __IOM uint32_t EN_TGL; /**< module en */
+ __IOM uint32_t SWRST_TGL; /**< Software Reset Register */
+ __IOM uint32_t CTRL_TGL; /**< Control Register */
+ __IOM uint32_t CMD_TGL; /**< Command Register */
+ __IM uint32_t STATUS_TGL; /**< Status Register */
+ __IOM uint32_t CNT_TGL; /**< Counter Value Register */
+ __IOM uint32_t COMP0_TGL; /**< Compare Value Register 0 */
+ __IOM uint32_t COMP1_TGL; /**< Compare Value Register 1 */
+ __IOM uint32_t TOP_TGL; /**< Counter TOP Value Register */
+ __IOM uint32_t TOPBUFF_TGL; /**< Buffered Counter TOP Value */
+ __IOM uint32_t REP0_TGL; /**< Repeat Counter Register 0 */
+ __IOM uint32_t REP1_TGL; /**< Repeat Counter Register 1 */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
+ __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */
+ __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */
+ uint32_t RESERVED6[3U]; /**< Reserved for future use */
+ __IOM uint32_t PRSMODE_TGL; /**< PRS Input mode select Register */
+} LETIMER_TypeDef;
+/** @} End of group EFR32MG24_LETIMER */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_LETIMER
+ * @{
+ * @defgroup EFR32MG24_LETIMER_BitFields LETIMER Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for LETIMER IPVERSION */
+#define _LETIMER_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for LETIMER_IPVERSION */
+#define _LETIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LETIMER_IPVERSION */
+#define _LETIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LETIMER_IPVERSION */
+#define _LETIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LETIMER_IPVERSION */
+#define _LETIMER_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for LETIMER_IPVERSION */
+#define LETIMER_IPVERSION_IPVERSION_DEFAULT (_LETIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IPVERSION */
+
+/* Bit fields for LETIMER EN */
+#define _LETIMER_EN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_EN */
+#define _LETIMER_EN_MASK 0x00000003UL /**< Mask for LETIMER_EN */
+#define LETIMER_EN_EN (0x1UL << 0) /**< module en */
+#define _LETIMER_EN_EN_SHIFT 0 /**< Shift value for LETIMER_EN */
+#define _LETIMER_EN_EN_MASK 0x1UL /**< Bit mask for LETIMER_EN */
+#define _LETIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_EN */
+#define LETIMER_EN_EN_DEFAULT (_LETIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_EN */
+#define LETIMER_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */
+#define _LETIMER_EN_DISABLING_SHIFT 1 /**< Shift value for LETIMER_DISABLING */
+#define _LETIMER_EN_DISABLING_MASK 0x2UL /**< Bit mask for LETIMER_DISABLING */
+#define _LETIMER_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_EN */
+#define LETIMER_EN_DISABLING_DEFAULT (_LETIMER_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_EN */
+
+/* Bit fields for LETIMER SWRST */
+#define _LETIMER_SWRST_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SWRST */
+#define _LETIMER_SWRST_MASK 0x00000003UL /**< Mask for LETIMER_SWRST */
+#define LETIMER_SWRST_SWRST (0x1UL << 0) /**< Software reset command */
+#define _LETIMER_SWRST_SWRST_SHIFT 0 /**< Shift value for LETIMER_SWRST */
+#define _LETIMER_SWRST_SWRST_MASK 0x1UL /**< Bit mask for LETIMER_SWRST */
+#define _LETIMER_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SWRST */
+#define LETIMER_SWRST_SWRST_DEFAULT (_LETIMER_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_SWRST */
+#define LETIMER_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */
+#define _LETIMER_SWRST_RESETTING_SHIFT 1 /**< Shift value for LETIMER_RESETTING */
+#define _LETIMER_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for LETIMER_RESETTING */
+#define _LETIMER_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SWRST */
+#define LETIMER_SWRST_RESETTING_DEFAULT (_LETIMER_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_SWRST */
+
+/* Bit fields for LETIMER CTRL */
+#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */
+#define _LETIMER_CTRL_MASK 0x000F13FFUL /**< Mask for LETIMER_CTRL */
+#define _LETIMER_CTRL_REPMODE_SHIFT 0 /**< Shift value for LETIMER_REPMODE */
+#define _LETIMER_CTRL_REPMODE_MASK 0x3UL /**< Bit mask for LETIMER_REPMODE */
+#define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
+#define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /**< Mode FREE for LETIMER_CTRL */
+#define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LETIMER_CTRL */
+#define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /**< Mode BUFFERED for LETIMER_CTRL */
+#define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /**< Mode DOUBLE for LETIMER_CTRL */
+#define LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0) /**< Shifted mode FREE for LETIMER_CTRL */
+#define LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LETIMER_CTRL */
+#define LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0) /**< Shifted mode BUFFERED for LETIMER_CTRL */
+#define LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0) /**< Shifted mode DOUBLE for LETIMER_CTRL */
+#define _LETIMER_CTRL_UFOA0_SHIFT 2 /**< Shift value for LETIMER_UFOA0 */
+#define _LETIMER_CTRL_UFOA0_MASK 0xCUL /**< Bit mask for LETIMER_UFOA0 */
+#define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
+#define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */
+#define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */
+#define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */
+#define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */
+#define LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2) /**< Shifted mode NONE for LETIMER_CTRL */
+#define LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2) /**< Shifted mode TOGGLE for LETIMER_CTRL */
+#define LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2) /**< Shifted mode PULSE for LETIMER_CTRL */
+#define LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2) /**< Shifted mode PWM for LETIMER_CTRL */
+#define _LETIMER_CTRL_UFOA1_SHIFT 4 /**< Shift value for LETIMER_UFOA1 */
+#define _LETIMER_CTRL_UFOA1_MASK 0x30UL /**< Bit mask for LETIMER_UFOA1 */
+#define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
+#define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */
+#define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */
+#define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */
+#define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */
+#define LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4) /**< Shifted mode NONE for LETIMER_CTRL */
+#define LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4) /**< Shifted mode TOGGLE for LETIMER_CTRL */
+#define LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4) /**< Shifted mode PULSE for LETIMER_CTRL */
+#define LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4) /**< Shifted mode PWM for LETIMER_CTRL */
+#define LETIMER_CTRL_OPOL0 (0x1UL << 6) /**< Output 0 Polarity */
+#define _LETIMER_CTRL_OPOL0_SHIFT 6 /**< Shift value for LETIMER_OPOL0 */
+#define _LETIMER_CTRL_OPOL0_MASK 0x40UL /**< Bit mask for LETIMER_OPOL0 */
+#define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_OPOL1 (0x1UL << 7) /**< Output 1 Polarity */
+#define _LETIMER_CTRL_OPOL1_SHIFT 7 /**< Shift value for LETIMER_OPOL1 */
+#define _LETIMER_CTRL_OPOL1_MASK 0x80UL /**< Bit mask for LETIMER_OPOL1 */
+#define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_BUFTOP (0x1UL << 8) /**< Buffered Top */
+#define _LETIMER_CTRL_BUFTOP_SHIFT 8 /**< Shift value for LETIMER_BUFTOP */
+#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */
+#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
+#define _LETIMER_CTRL_BUFTOP_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */
+#define _LETIMER_CTRL_BUFTOP_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */
+#define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_BUFTOP_DISABLE (_LETIMER_CTRL_BUFTOP_DISABLE << 8) /**< Shifted mode DISABLE for LETIMER_CTRL */
+#define LETIMER_CTRL_BUFTOP_ENABLE (_LETIMER_CTRL_BUFTOP_ENABLE << 8) /**< Shifted mode ENABLE for LETIMER_CTRL */
+#define LETIMER_CTRL_CNTTOPEN (0x1UL << 9) /**< Compare Value 0 Is Top Value */
+#define _LETIMER_CTRL_CNTTOPEN_SHIFT 9 /**< Shift value for LETIMER_CNTTOPEN */
+#define _LETIMER_CTRL_CNTTOPEN_MASK 0x200UL /**< Bit mask for LETIMER_CNTTOPEN */
+#define _LETIMER_CTRL_CNTTOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
+#define _LETIMER_CTRL_CNTTOPEN_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */
+#define _LETIMER_CTRL_CNTTOPEN_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */
+#define LETIMER_CTRL_CNTTOPEN_DEFAULT (_LETIMER_CTRL_CNTTOPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_CNTTOPEN_DISABLE (_LETIMER_CTRL_CNTTOPEN_DISABLE << 9) /**< Shifted mode DISABLE for LETIMER_CTRL */
+#define LETIMER_CTRL_CNTTOPEN_ENABLE (_LETIMER_CTRL_CNTTOPEN_ENABLE << 9) /**< Shifted mode ENABLE for LETIMER_CTRL */
+#define LETIMER_CTRL_DEBUGRUN (0x1UL << 12) /**< Debug Mode Run Enable */
+#define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /**< Shift value for LETIMER_DEBUGRUN */
+#define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /**< Bit mask for LETIMER_DEBUGRUN */
+#define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
+#define _LETIMER_CTRL_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */
+#define _LETIMER_CTRL_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */
+#define LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_DEBUGRUN_DISABLE (_LETIMER_CTRL_DEBUGRUN_DISABLE << 12) /**< Shifted mode DISABLE for LETIMER_CTRL */
+#define LETIMER_CTRL_DEBUGRUN_ENABLE (_LETIMER_CTRL_DEBUGRUN_ENABLE << 12) /**< Shifted mode ENABLE for LETIMER_CTRL */
+#define _LETIMER_CTRL_CNTPRESC_SHIFT 16 /**< Shift value for LETIMER_CNTPRESC */
+#define _LETIMER_CTRL_CNTPRESC_MASK 0xF0000UL /**< Bit mask for LETIMER_CNTPRESC */
+#define _LETIMER_CTRL_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
+#define _LETIMER_CTRL_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LETIMER_CTRL */
+#define _LETIMER_CTRL_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LETIMER_CTRL */
+#define _LETIMER_CTRL_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LETIMER_CTRL */
+#define _LETIMER_CTRL_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LETIMER_CTRL */
+#define _LETIMER_CTRL_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LETIMER_CTRL */
+#define _LETIMER_CTRL_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LETIMER_CTRL */
+#define _LETIMER_CTRL_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LETIMER_CTRL */
+#define _LETIMER_CTRL_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LETIMER_CTRL */
+#define _LETIMER_CTRL_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for LETIMER_CTRL */
+#define LETIMER_CTRL_CNTPRESC_DEFAULT (_LETIMER_CTRL_CNTPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for LETIMER_CTRL */
+#define LETIMER_CTRL_CNTPRESC_DIV1 (_LETIMER_CTRL_CNTPRESC_DIV1 << 16) /**< Shifted mode DIV1 for LETIMER_CTRL */
+#define LETIMER_CTRL_CNTPRESC_DIV2 (_LETIMER_CTRL_CNTPRESC_DIV2 << 16) /**< Shifted mode DIV2 for LETIMER_CTRL */
+#define LETIMER_CTRL_CNTPRESC_DIV4 (_LETIMER_CTRL_CNTPRESC_DIV4 << 16) /**< Shifted mode DIV4 for LETIMER_CTRL */
+#define LETIMER_CTRL_CNTPRESC_DIV8 (_LETIMER_CTRL_CNTPRESC_DIV8 << 16) /**< Shifted mode DIV8 for LETIMER_CTRL */
+#define LETIMER_CTRL_CNTPRESC_DIV16 (_LETIMER_CTRL_CNTPRESC_DIV16 << 16) /**< Shifted mode DIV16 for LETIMER_CTRL */
+#define LETIMER_CTRL_CNTPRESC_DIV32 (_LETIMER_CTRL_CNTPRESC_DIV32 << 16) /**< Shifted mode DIV32 for LETIMER_CTRL */
+#define LETIMER_CTRL_CNTPRESC_DIV64 (_LETIMER_CTRL_CNTPRESC_DIV64 << 16) /**< Shifted mode DIV64 for LETIMER_CTRL */
+#define LETIMER_CTRL_CNTPRESC_DIV128 (_LETIMER_CTRL_CNTPRESC_DIV128 << 16) /**< Shifted mode DIV128 for LETIMER_CTRL */
+#define LETIMER_CTRL_CNTPRESC_DIV256 (_LETIMER_CTRL_CNTPRESC_DIV256 << 16) /**< Shifted mode DIV256 for LETIMER_CTRL */
+
+/* Bit fields for LETIMER CMD */
+#define _LETIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CMD */
+#define _LETIMER_CMD_MASK 0x0000001FUL /**< Mask for LETIMER_CMD */
+#define LETIMER_CMD_START (0x1UL << 0) /**< Start LETIMER */
+#define _LETIMER_CMD_START_SHIFT 0 /**< Shift value for LETIMER_START */
+#define _LETIMER_CMD_START_MASK 0x1UL /**< Bit mask for LETIMER_START */
+#define _LETIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
+#define LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CMD */
+#define LETIMER_CMD_STOP (0x1UL << 1) /**< Stop LETIMER */
+#define _LETIMER_CMD_STOP_SHIFT 1 /**< Shift value for LETIMER_STOP */
+#define _LETIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for LETIMER_STOP */
+#define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
+#define LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_CMD */
+#define LETIMER_CMD_CLEAR (0x1UL << 2) /**< Clear LETIMER */
+#define _LETIMER_CMD_CLEAR_SHIFT 2 /**< Shift value for LETIMER_CLEAR */
+#define _LETIMER_CMD_CLEAR_MASK 0x4UL /**< Bit mask for LETIMER_CLEAR */
+#define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
+#define LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CMD */
+#define LETIMER_CMD_CTO0 (0x1UL << 3) /**< Clear Toggle Output 0 */
+#define _LETIMER_CMD_CTO0_SHIFT 3 /**< Shift value for LETIMER_CTO0 */
+#define _LETIMER_CMD_CTO0_MASK 0x8UL /**< Bit mask for LETIMER_CTO0 */
+#define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
+#define LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_CMD */
+#define LETIMER_CMD_CTO1 (0x1UL << 4) /**< Clear Toggle Output 1 */
+#define _LETIMER_CMD_CTO1_SHIFT 4 /**< Shift value for LETIMER_CTO1 */
+#define _LETIMER_CMD_CTO1_MASK 0x10UL /**< Bit mask for LETIMER_CTO1 */
+#define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
+#define LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CMD */
+
+/* Bit fields for LETIMER STATUS */
+#define _LETIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_STATUS */
+#define _LETIMER_STATUS_MASK 0x00000003UL /**< Mask for LETIMER_STATUS */
+#define LETIMER_STATUS_RUNNING (0x1UL << 0) /**< LETIMER Running */
+#define _LETIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for LETIMER_RUNNING */
+#define _LETIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for LETIMER_RUNNING */
+#define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */
+#define LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_STATUS */
+#define LETIMER_STATUS_LETIMERLOCKSTATUS (0x1UL << 1) /**< LETIMER Lock Status */
+#define _LETIMER_STATUS_LETIMERLOCKSTATUS_SHIFT 1 /**< Shift value for LETIMER_LETIMERLOCKSTATUS */
+#define _LETIMER_STATUS_LETIMERLOCKSTATUS_MASK 0x2UL /**< Bit mask for LETIMER_LETIMERLOCKSTATUS */
+#define _LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */
+#define _LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LETIMER_STATUS */
+#define _LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for LETIMER_STATUS */
+#define LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT (_LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_STATUS */
+#define LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED (_LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED << 1) /**< Shifted mode UNLOCKED for LETIMER_STATUS */
+#define LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED (_LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED << 1) /**< Shifted mode LOCKED for LETIMER_STATUS */
+
+/* Bit fields for LETIMER CNT */
+#define _LETIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CNT */
+#define _LETIMER_CNT_MASK 0x00FFFFFFUL /**< Mask for LETIMER_CNT */
+#define _LETIMER_CNT_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */
+#define _LETIMER_CNT_CNT_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_CNT */
+#define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CNT */
+#define LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CNT */
+
+/* Bit fields for LETIMER COMP0 */
+#define _LETIMER_COMP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP0 */
+#define _LETIMER_COMP0_MASK 0x00FFFFFFUL /**< Mask for LETIMER_COMP0 */
+#define _LETIMER_COMP0_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
+#define _LETIMER_COMP0_COMP0_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_COMP0 */
+#define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP0 */
+#define LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP0 */
+
+/* Bit fields for LETIMER COMP1 */
+#define _LETIMER_COMP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP1 */
+#define _LETIMER_COMP1_MASK 0x00FFFFFFUL /**< Mask for LETIMER_COMP1 */
+#define _LETIMER_COMP1_COMP1_SHIFT 0 /**< Shift value for LETIMER_COMP1 */
+#define _LETIMER_COMP1_COMP1_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_COMP1 */
+#define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP1 */
+#define LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP1 */
+
+/* Bit fields for LETIMER TOP */
+#define _LETIMER_TOP_RESETVALUE 0x00000000UL /**< Default value for LETIMER_TOP */
+#define _LETIMER_TOP_MASK 0x00FFFFFFUL /**< Mask for LETIMER_TOP */
+#define _LETIMER_TOP_TOP_SHIFT 0 /**< Shift value for LETIMER_TOP */
+#define _LETIMER_TOP_TOP_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_TOP */
+#define _LETIMER_TOP_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_TOP */
+#define LETIMER_TOP_TOP_DEFAULT (_LETIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_TOP */
+
+/* Bit fields for LETIMER TOPBUFF */
+#define _LETIMER_TOPBUFF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_TOPBUFF */
+#define _LETIMER_TOPBUFF_MASK 0x00FFFFFFUL /**< Mask for LETIMER_TOPBUFF */
+#define _LETIMER_TOPBUFF_TOPBUFF_SHIFT 0 /**< Shift value for LETIMER_TOPBUFF */
+#define _LETIMER_TOPBUFF_TOPBUFF_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_TOPBUFF */
+#define _LETIMER_TOPBUFF_TOPBUFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_TOPBUFF */
+#define LETIMER_TOPBUFF_TOPBUFF_DEFAULT (_LETIMER_TOPBUFF_TOPBUFF_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_TOPBUFF */
+
+/* Bit fields for LETIMER REP0 */
+#define _LETIMER_REP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP0 */
+#define _LETIMER_REP0_MASK 0x000000FFUL /**< Mask for LETIMER_REP0 */
+#define _LETIMER_REP0_REP0_SHIFT 0 /**< Shift value for LETIMER_REP0 */
+#define _LETIMER_REP0_REP0_MASK 0xFFUL /**< Bit mask for LETIMER_REP0 */
+#define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP0 */
+#define LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP0 */
+
+/* Bit fields for LETIMER REP1 */
+#define _LETIMER_REP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP1 */
+#define _LETIMER_REP1_MASK 0x000000FFUL /**< Mask for LETIMER_REP1 */
+#define _LETIMER_REP1_REP1_SHIFT 0 /**< Shift value for LETIMER_REP1 */
+#define _LETIMER_REP1_REP1_MASK 0xFFUL /**< Bit mask for LETIMER_REP1 */
+#define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP1 */
+#define LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP1 */
+
+/* Bit fields for LETIMER IF */
+#define _LETIMER_IF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IF */
+#define _LETIMER_IF_MASK 0x0000001FUL /**< Mask for LETIMER_IF */
+#define LETIMER_IF_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Flag */
+#define _LETIMER_IF_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
+#define _LETIMER_IF_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */
+#define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
+#define LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IF */
+#define LETIMER_IF_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Flag */
+#define _LETIMER_IF_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */
+#define _LETIMER_IF_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */
+#define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
+#define LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IF */
+#define LETIMER_IF_UF (0x1UL << 2) /**< Underflow Interrupt Flag */
+#define _LETIMER_IF_UF_SHIFT 2 /**< Shift value for LETIMER_UF */
+#define _LETIMER_IF_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */
+#define _LETIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
+#define LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IF */
+#define LETIMER_IF_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Flag */
+#define _LETIMER_IF_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */
+#define _LETIMER_IF_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */
+#define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
+#define LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IF */
+#define LETIMER_IF_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Flag */
+#define _LETIMER_IF_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */
+#define _LETIMER_IF_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */
+#define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
+#define LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IF */
+
+/* Bit fields for LETIMER IEN */
+#define _LETIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IEN */
+#define _LETIMER_IEN_MASK 0x0000001FUL /**< Mask for LETIMER_IEN */
+#define LETIMER_IEN_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Enable */
+#define _LETIMER_IEN_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
+#define _LETIMER_IEN_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */
+#define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
+#define LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IEN */
+#define LETIMER_IEN_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Enable */
+#define _LETIMER_IEN_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */
+#define _LETIMER_IEN_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */
+#define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
+#define LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IEN */
+#define LETIMER_IEN_UF (0x1UL << 2) /**< Underflow Interrupt Enable */
+#define _LETIMER_IEN_UF_SHIFT 2 /**< Shift value for LETIMER_UF */
+#define _LETIMER_IEN_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */
+#define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
+#define LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IEN */
+#define LETIMER_IEN_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Enable */
+#define _LETIMER_IEN_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */
+#define _LETIMER_IEN_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */
+#define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
+#define LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IEN */
+#define LETIMER_IEN_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Enable */
+#define _LETIMER_IEN_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */
+#define _LETIMER_IEN_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */
+#define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
+#define LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IEN */
+
+/* Bit fields for LETIMER LOCK */
+#define _LETIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for LETIMER_LOCK */
+#define _LETIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for LETIMER_LOCK */
+#define _LETIMER_LOCK_LETIMERLOCKKEY_SHIFT 0 /**< Shift value for LETIMER_LETIMERLOCKKEY */
+#define _LETIMER_LOCK_LETIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for LETIMER_LETIMERLOCKKEY */
+#define _LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_LOCK */
+#define _LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK 0x0000CCFCUL /**< Mode UNLOCK for LETIMER_LOCK */
+#define LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT (_LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_LOCK */
+#define LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK (_LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LETIMER_LOCK */
+
+/* Bit fields for LETIMER SYNCBUSY */
+#define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SYNCBUSY */
+#define _LETIMER_SYNCBUSY_MASK 0x000003FDUL /**< Mask for LETIMER_SYNCBUSY */
+#define LETIMER_SYNCBUSY_CNT (0x1UL << 0) /**< Sync busy for CNT */
+#define _LETIMER_SYNCBUSY_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */
+#define _LETIMER_SYNCBUSY_CNT_MASK 0x1UL /**< Bit mask for LETIMER_CNT */
+#define _LETIMER_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
+#define LETIMER_SYNCBUSY_CNT_DEFAULT (_LETIMER_SYNCBUSY_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
+#define LETIMER_SYNCBUSY_TOP (0x1UL << 2) /**< Sync busy for TOP */
+#define _LETIMER_SYNCBUSY_TOP_SHIFT 2 /**< Shift value for LETIMER_TOP */
+#define _LETIMER_SYNCBUSY_TOP_MASK 0x4UL /**< Bit mask for LETIMER_TOP */
+#define _LETIMER_SYNCBUSY_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
+#define LETIMER_SYNCBUSY_TOP_DEFAULT (_LETIMER_SYNCBUSY_TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
+#define LETIMER_SYNCBUSY_REP0 (0x1UL << 3) /**< Sync busy for REP0 */
+#define _LETIMER_SYNCBUSY_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */
+#define _LETIMER_SYNCBUSY_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */
+#define _LETIMER_SYNCBUSY_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
+#define LETIMER_SYNCBUSY_REP0_DEFAULT (_LETIMER_SYNCBUSY_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
+#define LETIMER_SYNCBUSY_REP1 (0x1UL << 4) /**< Sync busy for REP1 */
+#define _LETIMER_SYNCBUSY_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */
+#define _LETIMER_SYNCBUSY_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */
+#define _LETIMER_SYNCBUSY_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
+#define LETIMER_SYNCBUSY_REP1_DEFAULT (_LETIMER_SYNCBUSY_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
+#define LETIMER_SYNCBUSY_START (0x1UL << 5) /**< Sync busy for START */
+#define _LETIMER_SYNCBUSY_START_SHIFT 5 /**< Shift value for LETIMER_START */
+#define _LETIMER_SYNCBUSY_START_MASK 0x20UL /**< Bit mask for LETIMER_START */
+#define _LETIMER_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
+#define LETIMER_SYNCBUSY_START_DEFAULT (_LETIMER_SYNCBUSY_START_DEFAULT << 5) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
+#define LETIMER_SYNCBUSY_STOP (0x1UL << 6) /**< Sync busy for STOP */
+#define _LETIMER_SYNCBUSY_STOP_SHIFT 6 /**< Shift value for LETIMER_STOP */
+#define _LETIMER_SYNCBUSY_STOP_MASK 0x40UL /**< Bit mask for LETIMER_STOP */
+#define _LETIMER_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
+#define LETIMER_SYNCBUSY_STOP_DEFAULT (_LETIMER_SYNCBUSY_STOP_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
+#define LETIMER_SYNCBUSY_CLEAR (0x1UL << 7) /**< Sync busy for CLEAR */
+#define _LETIMER_SYNCBUSY_CLEAR_SHIFT 7 /**< Shift value for LETIMER_CLEAR */
+#define _LETIMER_SYNCBUSY_CLEAR_MASK 0x80UL /**< Bit mask for LETIMER_CLEAR */
+#define _LETIMER_SYNCBUSY_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
+#define LETIMER_SYNCBUSY_CLEAR_DEFAULT (_LETIMER_SYNCBUSY_CLEAR_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
+#define LETIMER_SYNCBUSY_CTO0 (0x1UL << 8) /**< Sync busy for CTO0 */
+#define _LETIMER_SYNCBUSY_CTO0_SHIFT 8 /**< Shift value for LETIMER_CTO0 */
+#define _LETIMER_SYNCBUSY_CTO0_MASK 0x100UL /**< Bit mask for LETIMER_CTO0 */
+#define _LETIMER_SYNCBUSY_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
+#define LETIMER_SYNCBUSY_CTO0_DEFAULT (_LETIMER_SYNCBUSY_CTO0_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
+#define LETIMER_SYNCBUSY_CTO1 (0x1UL << 9) /**< Sync busy for CTO1 */
+#define _LETIMER_SYNCBUSY_CTO1_SHIFT 9 /**< Shift value for LETIMER_CTO1 */
+#define _LETIMER_SYNCBUSY_CTO1_MASK 0x200UL /**< Bit mask for LETIMER_CTO1 */
+#define _LETIMER_SYNCBUSY_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
+#define LETIMER_SYNCBUSY_CTO1_DEFAULT (_LETIMER_SYNCBUSY_CTO1_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
+
+/* Bit fields for LETIMER PRSMODE */
+#define _LETIMER_PRSMODE_RESETVALUE 0x00000000UL /**< Default value for LETIMER_PRSMODE */
+#define _LETIMER_PRSMODE_MASK 0x0CCC0000UL /**< Mask for LETIMER_PRSMODE */
+#define _LETIMER_PRSMODE_PRSSTARTMODE_SHIFT 18 /**< Shift value for LETIMER_PRSSTARTMODE */
+#define _LETIMER_PRSMODE_PRSSTARTMODE_MASK 0xC0000UL /**< Bit mask for LETIMER_PRSSTARTMODE */
+#define _LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */
+#define _LETIMER_PRSMODE_PRSSTARTMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */
+#define _LETIMER_PRSMODE_PRSSTARTMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */
+#define _LETIMER_PRSMODE_PRSSTARTMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */
+#define _LETIMER_PRSMODE_PRSSTARTMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */
+#define LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT (_LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */
+#define LETIMER_PRSMODE_PRSSTARTMODE_NONE (_LETIMER_PRSMODE_PRSSTARTMODE_NONE << 18) /**< Shifted mode NONE for LETIMER_PRSMODE */
+#define LETIMER_PRSMODE_PRSSTARTMODE_RISING (_LETIMER_PRSMODE_PRSSTARTMODE_RISING << 18) /**< Shifted mode RISING for LETIMER_PRSMODE */
+#define LETIMER_PRSMODE_PRSSTARTMODE_FALLING (_LETIMER_PRSMODE_PRSSTARTMODE_FALLING << 18) /**< Shifted mode FALLING for LETIMER_PRSMODE */
+#define LETIMER_PRSMODE_PRSSTARTMODE_BOTH (_LETIMER_PRSMODE_PRSSTARTMODE_BOTH << 18) /**< Shifted mode BOTH for LETIMER_PRSMODE */
+#define _LETIMER_PRSMODE_PRSSTOPMODE_SHIFT 22 /**< Shift value for LETIMER_PRSSTOPMODE */
+#define _LETIMER_PRSMODE_PRSSTOPMODE_MASK 0xC00000UL /**< Bit mask for LETIMER_PRSSTOPMODE */
+#define _LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */
+#define _LETIMER_PRSMODE_PRSSTOPMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */
+#define _LETIMER_PRSMODE_PRSSTOPMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */
+#define _LETIMER_PRSMODE_PRSSTOPMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */
+#define _LETIMER_PRSMODE_PRSSTOPMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */
+#define LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT (_LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */
+#define LETIMER_PRSMODE_PRSSTOPMODE_NONE (_LETIMER_PRSMODE_PRSSTOPMODE_NONE << 22) /**< Shifted mode NONE for LETIMER_PRSMODE */
+#define LETIMER_PRSMODE_PRSSTOPMODE_RISING (_LETIMER_PRSMODE_PRSSTOPMODE_RISING << 22) /**< Shifted mode RISING for LETIMER_PRSMODE */
+#define LETIMER_PRSMODE_PRSSTOPMODE_FALLING (_LETIMER_PRSMODE_PRSSTOPMODE_FALLING << 22) /**< Shifted mode FALLING for LETIMER_PRSMODE */
+#define LETIMER_PRSMODE_PRSSTOPMODE_BOTH (_LETIMER_PRSMODE_PRSSTOPMODE_BOTH << 22) /**< Shifted mode BOTH for LETIMER_PRSMODE */
+#define _LETIMER_PRSMODE_PRSCLEARMODE_SHIFT 26 /**< Shift value for LETIMER_PRSCLEARMODE */
+#define _LETIMER_PRSMODE_PRSCLEARMODE_MASK 0xC000000UL /**< Bit mask for LETIMER_PRSCLEARMODE */
+#define _LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */
+#define _LETIMER_PRSMODE_PRSCLEARMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */
+#define _LETIMER_PRSMODE_PRSCLEARMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */
+#define _LETIMER_PRSMODE_PRSCLEARMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */
+#define _LETIMER_PRSMODE_PRSCLEARMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */
+#define LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT (_LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */
+#define LETIMER_PRSMODE_PRSCLEARMODE_NONE (_LETIMER_PRSMODE_PRSCLEARMODE_NONE << 26) /**< Shifted mode NONE for LETIMER_PRSMODE */
+#define LETIMER_PRSMODE_PRSCLEARMODE_RISING (_LETIMER_PRSMODE_PRSCLEARMODE_RISING << 26) /**< Shifted mode RISING for LETIMER_PRSMODE */
+#define LETIMER_PRSMODE_PRSCLEARMODE_FALLING (_LETIMER_PRSMODE_PRSCLEARMODE_FALLING << 26) /**< Shifted mode FALLING for LETIMER_PRSMODE */
+#define LETIMER_PRSMODE_PRSCLEARMODE_BOTH (_LETIMER_PRSMODE_PRSCLEARMODE_BOTH << 26) /**< Shifted mode BOTH for LETIMER_PRSMODE */
+
+/** @} End of group EFR32MG24_LETIMER_BitFields */
+/** @} End of group EFR32MG24_LETIMER */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_LETIMER_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_lfrco.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_lfrco.h
new file mode 100644
index 00000000..a8c058ef
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_lfrco.h
@@ -0,0 +1,304 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 LFRCO register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_LFRCO_H
+#define EFR32MG24_LFRCO_H
+#define LFRCO_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_LFRCO LFRCO
+ * @{
+ * @brief EFR32MG24 LFRCO Register Declaration.
+ *****************************************************************************/
+
+/** LFRCO Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IP version */
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ uint32_t RESERVED0[2U]; /**< Reserved for future use */
+ __IOM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ uint32_t RESERVED1[1U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK; /**< Configuration Lock Register */
+ __IOM uint32_t CFG; /**< Configuration Register */
+ uint32_t RESERVED2[1U]; /**< Reserved for future use */
+ __IOM uint32_t NOMCAL; /**< Nominal Calibration Register */
+ __IOM uint32_t NOMCALINV; /**< Nominal Calibration Inverted Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ uint32_t RESERVED3[1010U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP version */
+ __IOM uint32_t CTRL_SET; /**< Control Register */
+ __IM uint32_t STATUS_SET; /**< Status Register */
+ uint32_t RESERVED4[2U]; /**< Reserved for future use */
+ __IOM uint32_t IF_SET; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
+ uint32_t RESERVED5[1U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */
+ __IOM uint32_t CFG_SET; /**< Configuration Register */
+ uint32_t RESERVED6[1U]; /**< Reserved for future use */
+ __IOM uint32_t NOMCAL_SET; /**< Nominal Calibration Register */
+ __IOM uint32_t NOMCALINV_SET; /**< Nominal Calibration Inverted Register */
+ __IOM uint32_t CMD_SET; /**< Command Register */
+ uint32_t RESERVED7[1010U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP version */
+ __IOM uint32_t CTRL_CLR; /**< Control Register */
+ __IM uint32_t STATUS_CLR; /**< Status Register */
+ uint32_t RESERVED8[2U]; /**< Reserved for future use */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
+ uint32_t RESERVED9[1U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */
+ __IOM uint32_t CFG_CLR; /**< Configuration Register */
+ uint32_t RESERVED10[1U]; /**< Reserved for future use */
+ __IOM uint32_t NOMCAL_CLR; /**< Nominal Calibration Register */
+ __IOM uint32_t NOMCALINV_CLR; /**< Nominal Calibration Inverted Register */
+ __IOM uint32_t CMD_CLR; /**< Command Register */
+ uint32_t RESERVED11[1010U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP version */
+ __IOM uint32_t CTRL_TGL; /**< Control Register */
+ __IM uint32_t STATUS_TGL; /**< Status Register */
+ uint32_t RESERVED12[2U]; /**< Reserved for future use */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
+ uint32_t RESERVED13[1U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */
+ __IOM uint32_t CFG_TGL; /**< Configuration Register */
+ uint32_t RESERVED14[1U]; /**< Reserved for future use */
+ __IOM uint32_t NOMCAL_TGL; /**< Nominal Calibration Register */
+ __IOM uint32_t NOMCALINV_TGL; /**< Nominal Calibration Inverted Register */
+ __IOM uint32_t CMD_TGL; /**< Command Register */
+} LFRCO_TypeDef;
+/** @} End of group EFR32MG24_LFRCO */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_LFRCO
+ * @{
+ * @defgroup EFR32MG24_LFRCO_BitFields LFRCO Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for LFRCO IPVERSION */
+#define _LFRCO_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for LFRCO_IPVERSION */
+#define _LFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFRCO_IPVERSION */
+#define _LFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFRCO_IPVERSION */
+#define _LFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFRCO_IPVERSION */
+#define _LFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for LFRCO_IPVERSION */
+#define LFRCO_IPVERSION_IPVERSION_DEFAULT (_LFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IPVERSION */
+
+/* Bit fields for LFRCO CTRL */
+#define _LFRCO_CTRL_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CTRL */
+#define _LFRCO_CTRL_MASK 0x00000003UL /**< Mask for LFRCO_CTRL */
+#define LFRCO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */
+#define _LFRCO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for LFRCO_FORCEEN */
+#define _LFRCO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for LFRCO_FORCEEN */
+#define _LFRCO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CTRL */
+#define LFRCO_CTRL_FORCEEN_DEFAULT (_LFRCO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CTRL */
+#define LFRCO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-Demand */
+#define _LFRCO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for LFRCO_DISONDEMAND */
+#define _LFRCO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for LFRCO_DISONDEMAND */
+#define _LFRCO_CTRL_DISONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CTRL */
+#define LFRCO_CTRL_DISONDEMAND_DEFAULT (_LFRCO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_CTRL */
+
+/* Bit fields for LFRCO STATUS */
+#define _LFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFRCO_STATUS */
+#define _LFRCO_STATUS_MASK 0x80010001UL /**< Mask for LFRCO_STATUS */
+#define LFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */
+#define _LFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */
+#define _LFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */
+#define _LFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */
+#define LFRCO_STATUS_RDY_DEFAULT (_LFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_STATUS */
+#define LFRCO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */
+#define _LFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for LFRCO_ENS */
+#define _LFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFRCO_ENS */
+#define _LFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */
+#define LFRCO_STATUS_ENS_DEFAULT (_LFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_STATUS */
+#define LFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */
+#define _LFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFRCO_LOCK */
+#define _LFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFRCO_LOCK */
+#define _LFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */
+#define _LFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFRCO_STATUS */
+#define _LFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFRCO_STATUS */
+#define LFRCO_STATUS_LOCK_DEFAULT (_LFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFRCO_STATUS */
+#define LFRCO_STATUS_LOCK_UNLOCKED (_LFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFRCO_STATUS */
+#define LFRCO_STATUS_LOCK_LOCKED (_LFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFRCO_STATUS */
+
+/* Bit fields for LFRCO IF */
+#define _LFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IF */
+#define _LFRCO_IF_MASK 0x00070707UL /**< Mask for LFRCO_IF */
+#define LFRCO_IF_RDY (0x1UL << 0) /**< Ready Flag */
+#define _LFRCO_IF_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */
+#define _LFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */
+#define _LFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */
+#define LFRCO_IF_RDY_DEFAULT (_LFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IF */
+#define LFRCO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Flag */
+#define _LFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */
+#define _LFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */
+#define _LFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */
+#define LFRCO_IF_POSEDGE_DEFAULT (_LFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IF */
+#define LFRCO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Flag */
+#define _LFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */
+#define _LFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */
+#define _LFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */
+#define LFRCO_IF_NEGEDGE_DEFAULT (_LFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IF */
+#define LFRCO_IF_TCDONE (0x1UL << 8) /**< Temperature Check Done Flag */
+#define _LFRCO_IF_TCDONE_SHIFT 8 /**< Shift value for LFRCO_TCDONE */
+#define _LFRCO_IF_TCDONE_MASK 0x100UL /**< Bit mask for LFRCO_TCDONE */
+#define _LFRCO_IF_TCDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */
+#define LFRCO_IF_TCDONE_DEFAULT (_LFRCO_IF_TCDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for LFRCO_IF */
+#define LFRCO_IF_CALDONE (0x1UL << 9) /**< Calibration Done Flag */
+#define _LFRCO_IF_CALDONE_SHIFT 9 /**< Shift value for LFRCO_CALDONE */
+#define _LFRCO_IF_CALDONE_MASK 0x200UL /**< Bit mask for LFRCO_CALDONE */
+#define _LFRCO_IF_CALDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */
+#define LFRCO_IF_CALDONE_DEFAULT (_LFRCO_IF_CALDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for LFRCO_IF */
+#define LFRCO_IF_TEMPCHANGE (0x1UL << 10) /**< Temperature Change Flag */
+#define _LFRCO_IF_TEMPCHANGE_SHIFT 10 /**< Shift value for LFRCO_TEMPCHANGE */
+#define _LFRCO_IF_TEMPCHANGE_MASK 0x400UL /**< Bit mask for LFRCO_TEMPCHANGE */
+#define _LFRCO_IF_TEMPCHANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */
+#define LFRCO_IF_TEMPCHANGE_DEFAULT (_LFRCO_IF_TEMPCHANGE_DEFAULT << 10) /**< Shifted mode DEFAULT for LFRCO_IF */
+#define LFRCO_IF_SCHEDERR (0x1UL << 16) /**< Scheduling Error Flag */
+#define _LFRCO_IF_SCHEDERR_SHIFT 16 /**< Shift value for LFRCO_SCHEDERR */
+#define _LFRCO_IF_SCHEDERR_MASK 0x10000UL /**< Bit mask for LFRCO_SCHEDERR */
+#define _LFRCO_IF_SCHEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */
+#define LFRCO_IF_SCHEDERR_DEFAULT (_LFRCO_IF_SCHEDERR_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_IF */
+#define LFRCO_IF_TCOOR (0x1UL << 17) /**< Temperature Check Out Of Range Flag */
+#define _LFRCO_IF_TCOOR_SHIFT 17 /**< Shift value for LFRCO_TCOOR */
+#define _LFRCO_IF_TCOOR_MASK 0x20000UL /**< Bit mask for LFRCO_TCOOR */
+#define _LFRCO_IF_TCOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */
+#define LFRCO_IF_TCOOR_DEFAULT (_LFRCO_IF_TCOOR_DEFAULT << 17) /**< Shifted mode DEFAULT for LFRCO_IF */
+#define LFRCO_IF_CALOOR (0x1UL << 18) /**< Calibration Out Of Range Flag */
+#define _LFRCO_IF_CALOOR_SHIFT 18 /**< Shift value for LFRCO_CALOOR */
+#define _LFRCO_IF_CALOOR_MASK 0x40000UL /**< Bit mask for LFRCO_CALOOR */
+#define _LFRCO_IF_CALOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */
+#define LFRCO_IF_CALOOR_DEFAULT (_LFRCO_IF_CALOOR_DEFAULT << 18) /**< Shifted mode DEFAULT for LFRCO_IF */
+
+/* Bit fields for LFRCO IEN */
+#define _LFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IEN */
+#define _LFRCO_IEN_MASK 0x00070707UL /**< Mask for LFRCO_IEN */
+#define LFRCO_IEN_RDY (0x1UL << 0) /**< Ready Enable */
+#define _LFRCO_IEN_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */
+#define _LFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */
+#define _LFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */
+#define LFRCO_IEN_RDY_DEFAULT (_LFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IEN */
+#define LFRCO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Enable */
+#define _LFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */
+#define _LFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */
+#define _LFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */
+#define LFRCO_IEN_POSEDGE_DEFAULT (_LFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IEN */
+#define LFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Enable */
+#define _LFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */
+#define _LFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */
+#define _LFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */
+#define LFRCO_IEN_NEGEDGE_DEFAULT (_LFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IEN */
+#define LFRCO_IEN_TCDONE (0x1UL << 8) /**< Temperature Check Done Enable */
+#define _LFRCO_IEN_TCDONE_SHIFT 8 /**< Shift value for LFRCO_TCDONE */
+#define _LFRCO_IEN_TCDONE_MASK 0x100UL /**< Bit mask for LFRCO_TCDONE */
+#define _LFRCO_IEN_TCDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */
+#define LFRCO_IEN_TCDONE_DEFAULT (_LFRCO_IEN_TCDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for LFRCO_IEN */
+#define LFRCO_IEN_CALDONE (0x1UL << 9) /**< Calibration Done Enable */
+#define _LFRCO_IEN_CALDONE_SHIFT 9 /**< Shift value for LFRCO_CALDONE */
+#define _LFRCO_IEN_CALDONE_MASK 0x200UL /**< Bit mask for LFRCO_CALDONE */
+#define _LFRCO_IEN_CALDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */
+#define LFRCO_IEN_CALDONE_DEFAULT (_LFRCO_IEN_CALDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for LFRCO_IEN */
+#define LFRCO_IEN_TEMPCHANGE (0x1UL << 10) /**< Temperature Change Enable */
+#define _LFRCO_IEN_TEMPCHANGE_SHIFT 10 /**< Shift value for LFRCO_TEMPCHANGE */
+#define _LFRCO_IEN_TEMPCHANGE_MASK 0x400UL /**< Bit mask for LFRCO_TEMPCHANGE */
+#define _LFRCO_IEN_TEMPCHANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */
+#define LFRCO_IEN_TEMPCHANGE_DEFAULT (_LFRCO_IEN_TEMPCHANGE_DEFAULT << 10) /**< Shifted mode DEFAULT for LFRCO_IEN */
+#define LFRCO_IEN_SCHEDERR (0x1UL << 16) /**< Scheduling Error Enable */
+#define _LFRCO_IEN_SCHEDERR_SHIFT 16 /**< Shift value for LFRCO_SCHEDERR */
+#define _LFRCO_IEN_SCHEDERR_MASK 0x10000UL /**< Bit mask for LFRCO_SCHEDERR */
+#define _LFRCO_IEN_SCHEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */
+#define LFRCO_IEN_SCHEDERR_DEFAULT (_LFRCO_IEN_SCHEDERR_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_IEN */
+#define LFRCO_IEN_TCOOR (0x1UL << 17) /**< Temperature Check Out Of Range Enable */
+#define _LFRCO_IEN_TCOOR_SHIFT 17 /**< Shift value for LFRCO_TCOOR */
+#define _LFRCO_IEN_TCOOR_MASK 0x20000UL /**< Bit mask for LFRCO_TCOOR */
+#define _LFRCO_IEN_TCOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */
+#define LFRCO_IEN_TCOOR_DEFAULT (_LFRCO_IEN_TCOOR_DEFAULT << 17) /**< Shifted mode DEFAULT for LFRCO_IEN */
+#define LFRCO_IEN_CALOOR (0x1UL << 18) /**< Calibration Out Of Range Enable */
+#define _LFRCO_IEN_CALOOR_SHIFT 18 /**< Shift value for LFRCO_CALOOR */
+#define _LFRCO_IEN_CALOOR_MASK 0x40000UL /**< Bit mask for LFRCO_CALOOR */
+#define _LFRCO_IEN_CALOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */
+#define LFRCO_IEN_CALOOR_DEFAULT (_LFRCO_IEN_CALOOR_DEFAULT << 18) /**< Shifted mode DEFAULT for LFRCO_IEN */
+
+/* Bit fields for LFRCO LOCK */
+#define _LFRCO_LOCK_RESETVALUE 0x00000000UL /**< Default value for LFRCO_LOCK */
+#define _LFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFRCO_LOCK */
+#define _LFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFRCO_LOCKKEY */
+#define _LFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFRCO_LOCKKEY */
+#define _LFRCO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_LOCK */
+#define _LFRCO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for LFRCO_LOCK */
+#define _LFRCO_LOCK_LOCKKEY_UNLOCK 0x00000F93UL /**< Mode UNLOCK for LFRCO_LOCK */
+#define LFRCO_LOCK_LOCKKEY_DEFAULT (_LFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_LOCK */
+#define LFRCO_LOCK_LOCKKEY_LOCK (_LFRCO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for LFRCO_LOCK */
+#define LFRCO_LOCK_LOCKKEY_UNLOCK (_LFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFRCO_LOCK */
+
+/* Bit fields for LFRCO CFG */
+#define _LFRCO_CFG_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CFG */
+#define _LFRCO_CFG_MASK 0x00000001UL /**< Mask for LFRCO_CFG */
+#define LFRCO_CFG_HIGHPRECEN (0x1UL << 0) /**< High Precision Enable */
+#define _LFRCO_CFG_HIGHPRECEN_SHIFT 0 /**< Shift value for LFRCO_HIGHPRECEN */
+#define _LFRCO_CFG_HIGHPRECEN_MASK 0x1UL /**< Bit mask for LFRCO_HIGHPRECEN */
+#define _LFRCO_CFG_HIGHPRECEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CFG */
+#define LFRCO_CFG_HIGHPRECEN_DEFAULT (_LFRCO_CFG_HIGHPRECEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CFG */
+
+/* Bit fields for LFRCO NOMCAL */
+#define _LFRCO_NOMCAL_RESETVALUE 0x0005B8D8UL /**< Default value for LFRCO_NOMCAL */
+#define _LFRCO_NOMCAL_MASK 0x001FFFFFUL /**< Mask for LFRCO_NOMCAL */
+#define _LFRCO_NOMCAL_NOMCALCNT_SHIFT 0 /**< Shift value for LFRCO_NOMCALCNT */
+#define _LFRCO_NOMCAL_NOMCALCNT_MASK 0x1FFFFFUL /**< Bit mask for LFRCO_NOMCALCNT */
+#define _LFRCO_NOMCAL_NOMCALCNT_DEFAULT 0x0005B8D8UL /**< Mode DEFAULT for LFRCO_NOMCAL */
+#define LFRCO_NOMCAL_NOMCALCNT_DEFAULT (_LFRCO_NOMCAL_NOMCALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_NOMCAL */
+
+/* Bit fields for LFRCO NOMCALINV */
+#define _LFRCO_NOMCALINV_RESETVALUE 0x0000597AUL /**< Default value for LFRCO_NOMCALINV */
+#define _LFRCO_NOMCALINV_MASK 0x0001FFFFUL /**< Mask for LFRCO_NOMCALINV */
+#define _LFRCO_NOMCALINV_NOMCALCNTINV_SHIFT 0 /**< Shift value for LFRCO_NOMCALCNTINV */
+#define _LFRCO_NOMCALINV_NOMCALCNTINV_MASK 0x1FFFFUL /**< Bit mask for LFRCO_NOMCALCNTINV */
+#define _LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT 0x0000597AUL /**< Mode DEFAULT for LFRCO_NOMCALINV */
+#define LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT (_LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_NOMCALINV */
+
+/* Bit fields for LFRCO CMD */
+#define _LFRCO_CMD_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CMD */
+#define _LFRCO_CMD_MASK 0x00000001UL /**< Mask for LFRCO_CMD */
+#define LFRCO_CMD_REDUCETCINT (0x1UL << 0) /**< Reduce Temperature Check Interval */
+#define _LFRCO_CMD_REDUCETCINT_SHIFT 0 /**< Shift value for LFRCO_REDUCETCINT */
+#define _LFRCO_CMD_REDUCETCINT_MASK 0x1UL /**< Bit mask for LFRCO_REDUCETCINT */
+#define _LFRCO_CMD_REDUCETCINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CMD */
+#define LFRCO_CMD_REDUCETCINT_DEFAULT (_LFRCO_CMD_REDUCETCINT_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CMD */
+
+/** @} End of group EFR32MG24_LFRCO_BitFields */
+/** @} End of group EFR32MG24_LFRCO */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_LFRCO_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_lfxo.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_lfxo.h
new file mode 100644
index 00000000..cda75b14
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_lfxo.h
@@ -0,0 +1,281 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 LFXO register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_LFXO_H
+#define EFR32MG24_LFXO_H
+#define LFXO_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_LFXO LFXO
+ * @{
+ * @brief EFR32MG24 LFXO Register Declaration.
+ *****************************************************************************/
+
+/** LFXO Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< LFXO IP version */
+ __IOM uint32_t CTRL; /**< LFXO Control Register */
+ __IOM uint32_t CFG; /**< LFXO Configuration Register */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+ __IM uint32_t STATUS; /**< LFXO Status Register */
+ __IOM uint32_t CAL; /**< LFXO Calibration Register */
+ __IOM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IM uint32_t SYNCBUSY; /**< LFXO Sync Busy Register */
+ __IOM uint32_t LOCK; /**< Configuration Lock Register */
+ uint32_t RESERVED1[1014U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< LFXO IP version */
+ __IOM uint32_t CTRL_SET; /**< LFXO Control Register */
+ __IOM uint32_t CFG_SET; /**< LFXO Configuration Register */
+ uint32_t RESERVED2[1U]; /**< Reserved for future use */
+ __IM uint32_t STATUS_SET; /**< LFXO Status Register */
+ __IOM uint32_t CAL_SET; /**< LFXO Calibration Register */
+ __IOM uint32_t IF_SET; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
+ __IM uint32_t SYNCBUSY_SET; /**< LFXO Sync Busy Register */
+ __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */
+ uint32_t RESERVED3[1014U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< LFXO IP version */
+ __IOM uint32_t CTRL_CLR; /**< LFXO Control Register */
+ __IOM uint32_t CFG_CLR; /**< LFXO Configuration Register */
+ uint32_t RESERVED4[1U]; /**< Reserved for future use */
+ __IM uint32_t STATUS_CLR; /**< LFXO Status Register */
+ __IOM uint32_t CAL_CLR; /**< LFXO Calibration Register */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
+ __IM uint32_t SYNCBUSY_CLR; /**< LFXO Sync Busy Register */
+ __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */
+ uint32_t RESERVED5[1014U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< LFXO IP version */
+ __IOM uint32_t CTRL_TGL; /**< LFXO Control Register */
+ __IOM uint32_t CFG_TGL; /**< LFXO Configuration Register */
+ uint32_t RESERVED6[1U]; /**< Reserved for future use */
+ __IM uint32_t STATUS_TGL; /**< LFXO Status Register */
+ __IOM uint32_t CAL_TGL; /**< LFXO Calibration Register */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
+ __IM uint32_t SYNCBUSY_TGL; /**< LFXO Sync Busy Register */
+ __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */
+} LFXO_TypeDef;
+/** @} End of group EFR32MG24_LFXO */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_LFXO
+ * @{
+ * @defgroup EFR32MG24_LFXO_BitFields LFXO Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for LFXO IPVERSION */
+#define _LFXO_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for LFXO_IPVERSION */
+#define _LFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFXO_IPVERSION */
+#define _LFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFXO_IPVERSION */
+#define _LFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFXO_IPVERSION */
+#define _LFXO_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_IPVERSION */
+#define LFXO_IPVERSION_IPVERSION_DEFAULT (_LFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IPVERSION */
+
+/* Bit fields for LFXO CTRL */
+#define _LFXO_CTRL_RESETVALUE 0x00000002UL /**< Default value for LFXO_CTRL */
+#define _LFXO_CTRL_MASK 0x00000033UL /**< Mask for LFXO_CTRL */
+#define LFXO_CTRL_FORCEEN (0x1UL << 0) /**< LFXO Force Enable */
+#define _LFXO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for LFXO_FORCEEN */
+#define _LFXO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for LFXO_FORCEEN */
+#define _LFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */
+#define LFXO_CTRL_FORCEEN_DEFAULT (_LFXO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CTRL */
+#define LFXO_CTRL_DISONDEMAND (0x1UL << 1) /**< LFXO Disable On-demand requests */
+#define _LFXO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for LFXO_DISONDEMAND */
+#define _LFXO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for LFXO_DISONDEMAND */
+#define _LFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CTRL */
+#define LFXO_CTRL_DISONDEMAND_DEFAULT (_LFXO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CTRL */
+#define LFXO_CTRL_FAILDETEN (0x1UL << 4) /**< LFXO Failure Detection Enable */
+#define _LFXO_CTRL_FAILDETEN_SHIFT 4 /**< Shift value for LFXO_FAILDETEN */
+#define _LFXO_CTRL_FAILDETEN_MASK 0x10UL /**< Bit mask for LFXO_FAILDETEN */
+#define _LFXO_CTRL_FAILDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */
+#define LFXO_CTRL_FAILDETEN_DEFAULT (_LFXO_CTRL_FAILDETEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CTRL */
+#define LFXO_CTRL_FAILDETEM4WUEN (0x1UL << 5) /**< LFXO Failure Detection EM4WU Enable */
+#define _LFXO_CTRL_FAILDETEM4WUEN_SHIFT 5 /**< Shift value for LFXO_FAILDETEM4WUEN */
+#define _LFXO_CTRL_FAILDETEM4WUEN_MASK 0x20UL /**< Bit mask for LFXO_FAILDETEM4WUEN */
+#define _LFXO_CTRL_FAILDETEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */
+#define LFXO_CTRL_FAILDETEM4WUEN_DEFAULT (_LFXO_CTRL_FAILDETEM4WUEN_DEFAULT << 5) /**< Shifted mode DEFAULT for LFXO_CTRL */
+
+/* Bit fields for LFXO CFG */
+#define _LFXO_CFG_RESETVALUE 0x00000701UL /**< Default value for LFXO_CFG */
+#define _LFXO_CFG_MASK 0x00000733UL /**< Mask for LFXO_CFG */
+#define LFXO_CFG_AGC (0x1UL << 0) /**< LFXO AGC Enable */
+#define _LFXO_CFG_AGC_SHIFT 0 /**< Shift value for LFXO_AGC */
+#define _LFXO_CFG_AGC_MASK 0x1UL /**< Bit mask for LFXO_AGC */
+#define _LFXO_CFG_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CFG */
+#define LFXO_CFG_AGC_DEFAULT (_LFXO_CFG_AGC_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CFG */
+#define LFXO_CFG_HIGHAMPL (0x1UL << 1) /**< LFXO High Amplitude Enable */
+#define _LFXO_CFG_HIGHAMPL_SHIFT 1 /**< Shift value for LFXO_HIGHAMPL */
+#define _LFXO_CFG_HIGHAMPL_MASK 0x2UL /**< Bit mask for LFXO_HIGHAMPL */
+#define _LFXO_CFG_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */
+#define LFXO_CFG_HIGHAMPL_DEFAULT (_LFXO_CFG_HIGHAMPL_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CFG */
+#define _LFXO_CFG_MODE_SHIFT 4 /**< Shift value for LFXO_MODE */
+#define _LFXO_CFG_MODE_MASK 0x30UL /**< Bit mask for LFXO_MODE */
+#define _LFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */
+#define _LFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for LFXO_CFG */
+#define _LFXO_CFG_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for LFXO_CFG */
+#define _LFXO_CFG_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for LFXO_CFG */
+#define LFXO_CFG_MODE_DEFAULT (_LFXO_CFG_MODE_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CFG */
+#define LFXO_CFG_MODE_XTAL (_LFXO_CFG_MODE_XTAL << 4) /**< Shifted mode XTAL for LFXO_CFG */
+#define LFXO_CFG_MODE_BUFEXTCLK (_LFXO_CFG_MODE_BUFEXTCLK << 4) /**< Shifted mode BUFEXTCLK for LFXO_CFG */
+#define LFXO_CFG_MODE_DIGEXTCLK (_LFXO_CFG_MODE_DIGEXTCLK << 4) /**< Shifted mode DIGEXTCLK for LFXO_CFG */
+#define _LFXO_CFG_TIMEOUT_SHIFT 8 /**< Shift value for LFXO_TIMEOUT */
+#define _LFXO_CFG_TIMEOUT_MASK 0x700UL /**< Bit mask for LFXO_TIMEOUT */
+#define _LFXO_CFG_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for LFXO_CFG */
+#define _LFXO_CFG_TIMEOUT_CYCLES2 0x00000000UL /**< Mode CYCLES2 for LFXO_CFG */
+#define _LFXO_CFG_TIMEOUT_CYCLES256 0x00000001UL /**< Mode CYCLES256 for LFXO_CFG */
+#define _LFXO_CFG_TIMEOUT_CYCLES1K 0x00000002UL /**< Mode CYCLES1K for LFXO_CFG */
+#define _LFXO_CFG_TIMEOUT_CYCLES2K 0x00000003UL /**< Mode CYCLES2K for LFXO_CFG */
+#define _LFXO_CFG_TIMEOUT_CYCLES4K 0x00000004UL /**< Mode CYCLES4K for LFXO_CFG */
+#define _LFXO_CFG_TIMEOUT_CYCLES8K 0x00000005UL /**< Mode CYCLES8K for LFXO_CFG */
+#define _LFXO_CFG_TIMEOUT_CYCLES16K 0x00000006UL /**< Mode CYCLES16K for LFXO_CFG */
+#define _LFXO_CFG_TIMEOUT_CYCLES32K 0x00000007UL /**< Mode CYCLES32K for LFXO_CFG */
+#define LFXO_CFG_TIMEOUT_DEFAULT (_LFXO_CFG_TIMEOUT_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CFG */
+#define LFXO_CFG_TIMEOUT_CYCLES2 (_LFXO_CFG_TIMEOUT_CYCLES2 << 8) /**< Shifted mode CYCLES2 for LFXO_CFG */
+#define LFXO_CFG_TIMEOUT_CYCLES256 (_LFXO_CFG_TIMEOUT_CYCLES256 << 8) /**< Shifted mode CYCLES256 for LFXO_CFG */
+#define LFXO_CFG_TIMEOUT_CYCLES1K (_LFXO_CFG_TIMEOUT_CYCLES1K << 8) /**< Shifted mode CYCLES1K for LFXO_CFG */
+#define LFXO_CFG_TIMEOUT_CYCLES2K (_LFXO_CFG_TIMEOUT_CYCLES2K << 8) /**< Shifted mode CYCLES2K for LFXO_CFG */
+#define LFXO_CFG_TIMEOUT_CYCLES4K (_LFXO_CFG_TIMEOUT_CYCLES4K << 8) /**< Shifted mode CYCLES4K for LFXO_CFG */
+#define LFXO_CFG_TIMEOUT_CYCLES8K (_LFXO_CFG_TIMEOUT_CYCLES8K << 8) /**< Shifted mode CYCLES8K for LFXO_CFG */
+#define LFXO_CFG_TIMEOUT_CYCLES16K (_LFXO_CFG_TIMEOUT_CYCLES16K << 8) /**< Shifted mode CYCLES16K for LFXO_CFG */
+#define LFXO_CFG_TIMEOUT_CYCLES32K (_LFXO_CFG_TIMEOUT_CYCLES32K << 8) /**< Shifted mode CYCLES32K for LFXO_CFG */
+
+/* Bit fields for LFXO STATUS */
+#define _LFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFXO_STATUS */
+#define _LFXO_STATUS_MASK 0x80010001UL /**< Mask for LFXO_STATUS */
+#define LFXO_STATUS_RDY (0x1UL << 0) /**< LFXO Ready Status */
+#define _LFXO_STATUS_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */
+#define _LFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */
+#define _LFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */
+#define LFXO_STATUS_RDY_DEFAULT (_LFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_STATUS */
+#define LFXO_STATUS_ENS (0x1UL << 16) /**< LFXO Enable Status */
+#define _LFXO_STATUS_ENS_SHIFT 16 /**< Shift value for LFXO_ENS */
+#define _LFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFXO_ENS */
+#define _LFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */
+#define LFXO_STATUS_ENS_DEFAULT (_LFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFXO_STATUS */
+#define LFXO_STATUS_LOCK (0x1UL << 31) /**< LFXO Locked Status */
+#define _LFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFXO_LOCK */
+#define _LFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFXO_LOCK */
+#define _LFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */
+#define _LFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFXO_STATUS */
+#define _LFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFXO_STATUS */
+#define LFXO_STATUS_LOCK_DEFAULT (_LFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFXO_STATUS */
+#define LFXO_STATUS_LOCK_UNLOCKED (_LFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFXO_STATUS */
+#define LFXO_STATUS_LOCK_LOCKED (_LFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFXO_STATUS */
+
+/* Bit fields for LFXO CAL */
+#define _LFXO_CAL_RESETVALUE 0x00000100UL /**< Default value for LFXO_CAL */
+#define _LFXO_CAL_MASK 0x0000037FUL /**< Mask for LFXO_CAL */
+#define _LFXO_CAL_CAPTUNE_SHIFT 0 /**< Shift value for LFXO_CAPTUNE */
+#define _LFXO_CAL_CAPTUNE_MASK 0x7FUL /**< Bit mask for LFXO_CAPTUNE */
+#define _LFXO_CAL_CAPTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CAL */
+#define LFXO_CAL_CAPTUNE_DEFAULT (_LFXO_CAL_CAPTUNE_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CAL */
+#define _LFXO_CAL_GAIN_SHIFT 8 /**< Shift value for LFXO_GAIN */
+#define _LFXO_CAL_GAIN_MASK 0x300UL /**< Bit mask for LFXO_GAIN */
+#define _LFXO_CAL_GAIN_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CAL */
+#define LFXO_CAL_GAIN_DEFAULT (_LFXO_CAL_GAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CAL */
+
+/* Bit fields for LFXO IF */
+#define _LFXO_IF_RESETVALUE 0x00000000UL /**< Default value for LFXO_IF */
+#define _LFXO_IF_MASK 0x0000000FUL /**< Mask for LFXO_IF */
+#define LFXO_IF_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Flag */
+#define _LFXO_IF_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */
+#define _LFXO_IF_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */
+#define _LFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */
+#define LFXO_IF_RDY_DEFAULT (_LFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IF */
+#define LFXO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Flag */
+#define _LFXO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */
+#define _LFXO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */
+#define _LFXO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */
+#define LFXO_IF_POSEDGE_DEFAULT (_LFXO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IF */
+#define LFXO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Flag */
+#define _LFXO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */
+#define _LFXO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */
+#define _LFXO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */
+#define LFXO_IF_NEGEDGE_DEFAULT (_LFXO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IF */
+#define LFXO_IF_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Flag */
+#define _LFXO_IF_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */
+#define _LFXO_IF_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */
+#define _LFXO_IF_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */
+#define LFXO_IF_FAIL_DEFAULT (_LFXO_IF_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IF */
+
+/* Bit fields for LFXO IEN */
+#define _LFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFXO_IEN */
+#define _LFXO_IEN_MASK 0x0000000FUL /**< Mask for LFXO_IEN */
+#define LFXO_IEN_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Enable */
+#define _LFXO_IEN_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */
+#define _LFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */
+#define _LFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */
+#define LFXO_IEN_RDY_DEFAULT (_LFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IEN */
+#define LFXO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Enable */
+#define _LFXO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */
+#define _LFXO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */
+#define _LFXO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */
+#define LFXO_IEN_POSEDGE_DEFAULT (_LFXO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IEN */
+#define LFXO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Enable */
+#define _LFXO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */
+#define _LFXO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */
+#define _LFXO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */
+#define LFXO_IEN_NEGEDGE_DEFAULT (_LFXO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IEN */
+#define LFXO_IEN_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Enable */
+#define _LFXO_IEN_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */
+#define _LFXO_IEN_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */
+#define _LFXO_IEN_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */
+#define LFXO_IEN_FAIL_DEFAULT (_LFXO_IEN_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IEN */
+
+/* Bit fields for LFXO SYNCBUSY */
+#define _LFXO_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LFXO_SYNCBUSY */
+#define _LFXO_SYNCBUSY_MASK 0x00000001UL /**< Mask for LFXO_SYNCBUSY */
+#define LFXO_SYNCBUSY_CAL (0x1UL << 0) /**< LFXO Synchronization status */
+#define _LFXO_SYNCBUSY_CAL_SHIFT 0 /**< Shift value for LFXO_CAL */
+#define _LFXO_SYNCBUSY_CAL_MASK 0x1UL /**< Bit mask for LFXO_CAL */
+#define _LFXO_SYNCBUSY_CAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_SYNCBUSY */
+#define LFXO_SYNCBUSY_CAL_DEFAULT (_LFXO_SYNCBUSY_CAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_SYNCBUSY */
+
+/* Bit fields for LFXO LOCK */
+#define _LFXO_LOCK_RESETVALUE 0x00001A20UL /**< Default value for LFXO_LOCK */
+#define _LFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFXO_LOCK */
+#define _LFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFXO_LOCKKEY */
+#define _LFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFXO_LOCKKEY */
+#define _LFXO_LOCK_LOCKKEY_DEFAULT 0x00001A20UL /**< Mode DEFAULT for LFXO_LOCK */
+#define _LFXO_LOCK_LOCKKEY_UNLOCK 0x00001A20UL /**< Mode UNLOCK for LFXO_LOCK */
+#define LFXO_LOCK_LOCKKEY_DEFAULT (_LFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_LOCK */
+#define LFXO_LOCK_LOCKKEY_UNLOCK (_LFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFXO_LOCK */
+
+/** @} End of group EFR32MG24_LFXO_BitFields */
+/** @} End of group EFR32MG24_LFXO */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_LFXO_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_mailbox.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_mailbox.h
new file mode 100644
index 00000000..0ff92ea1
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_mailbox.h
@@ -0,0 +1,140 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 MAILBOX register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_MAILBOX_H
+#define EFR32MG24_MAILBOX_H
+#define MAILBOX_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_MAILBOX MAILBOX
+ * @{
+ * @brief EFR32MG24 MAILBOX Register Declaration.
+ *****************************************************************************/
+
+/** MAILBOX MSGPTRS Register Group Declaration. */
+typedef struct {
+ __IOM uint32_t MSGPTR; /**< Message Pointer */
+} MAILBOX_MSGPTRS_TypeDef;
+
+/** MAILBOX Register Declaration. */
+typedef struct {
+ MAILBOX_MSGPTRS_TypeDef MSGPTRS[4U]; /**< Message Pointers */
+ uint32_t RESERVED0[12U]; /**< Reserved for future use */
+ __IOM uint32_t IF; /**< Interrupt Flag register */
+ __IOM uint32_t IEN; /**< Interrupt Enable register */
+ uint32_t RESERVED1[1006U]; /**< Reserved for future use */
+ MAILBOX_MSGPTRS_TypeDef MSGPTRS_SET[4U]; /**< Message Pointers */
+ uint32_t RESERVED2[12U]; /**< Reserved for future use */
+ __IOM uint32_t IF_SET; /**< Interrupt Flag register */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable register */
+ uint32_t RESERVED3[1006U]; /**< Reserved for future use */
+ MAILBOX_MSGPTRS_TypeDef MSGPTRS_CLR[4U]; /**< Message Pointers */
+ uint32_t RESERVED4[12U]; /**< Reserved for future use */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flag register */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable register */
+ uint32_t RESERVED5[1006U]; /**< Reserved for future use */
+ MAILBOX_MSGPTRS_TypeDef MSGPTRS_TGL[4U]; /**< Message Pointers */
+ uint32_t RESERVED6[12U]; /**< Reserved for future use */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flag register */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable register */
+} MAILBOX_TypeDef;
+/** @} End of group EFR32MG24_MAILBOX */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_MAILBOX
+ * @{
+ * @defgroup EFR32MG24_MAILBOX_BitFields MAILBOX Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for MAILBOX MSGPTR */
+#define _MAILBOX_MSGPTR_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_MSGPTR */
+#define _MAILBOX_MSGPTR_MASK 0xFFFFFFFFUL /**< Mask for MAILBOX_MSGPTR */
+#define _MAILBOX_MSGPTR_PTR_SHIFT 0 /**< Shift value for MAILBOX_PTR */
+#define _MAILBOX_MSGPTR_PTR_MASK 0xFFFFFFFFUL /**< Bit mask for MAILBOX_PTR */
+#define _MAILBOX_MSGPTR_PTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_MSGPTR */
+#define MAILBOX_MSGPTR_PTR_DEFAULT (_MAILBOX_MSGPTR_PTR_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_MSGPTR */
+
+/* Bit fields for MAILBOX IF */
+#define _MAILBOX_IF_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_IF */
+#define _MAILBOX_IF_MASK 0x0000000FUL /**< Mask for MAILBOX_IF */
+#define MAILBOX_IF_MBOXIF0 (0x1UL << 0) /**< Mailbox Interupt Flag */
+#define _MAILBOX_IF_MBOXIF0_SHIFT 0 /**< Shift value for MAILBOX_MBOXIF0 */
+#define _MAILBOX_IF_MBOXIF0_MASK 0x1UL /**< Bit mask for MAILBOX_MBOXIF0 */
+#define _MAILBOX_IF_MBOXIF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */
+#define MAILBOX_IF_MBOXIF0_DEFAULT (_MAILBOX_IF_MBOXIF0_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_IF */
+#define MAILBOX_IF_MBOXIF1 (0x1UL << 1) /**< Mailbox Interupt Flag */
+#define _MAILBOX_IF_MBOXIF1_SHIFT 1 /**< Shift value for MAILBOX_MBOXIF1 */
+#define _MAILBOX_IF_MBOXIF1_MASK 0x2UL /**< Bit mask for MAILBOX_MBOXIF1 */
+#define _MAILBOX_IF_MBOXIF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */
+#define MAILBOX_IF_MBOXIF1_DEFAULT (_MAILBOX_IF_MBOXIF1_DEFAULT << 1) /**< Shifted mode DEFAULT for MAILBOX_IF */
+#define MAILBOX_IF_MBOXIF2 (0x1UL << 2) /**< Mailbox Interupt Flag */
+#define _MAILBOX_IF_MBOXIF2_SHIFT 2 /**< Shift value for MAILBOX_MBOXIF2 */
+#define _MAILBOX_IF_MBOXIF2_MASK 0x4UL /**< Bit mask for MAILBOX_MBOXIF2 */
+#define _MAILBOX_IF_MBOXIF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */
+#define MAILBOX_IF_MBOXIF2_DEFAULT (_MAILBOX_IF_MBOXIF2_DEFAULT << 2) /**< Shifted mode DEFAULT for MAILBOX_IF */
+#define MAILBOX_IF_MBOXIF3 (0x1UL << 3) /**< Mailbox Interupt Flag */
+#define _MAILBOX_IF_MBOXIF3_SHIFT 3 /**< Shift value for MAILBOX_MBOXIF3 */
+#define _MAILBOX_IF_MBOXIF3_MASK 0x8UL /**< Bit mask for MAILBOX_MBOXIF3 */
+#define _MAILBOX_IF_MBOXIF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */
+#define MAILBOX_IF_MBOXIF3_DEFAULT (_MAILBOX_IF_MBOXIF3_DEFAULT << 3) /**< Shifted mode DEFAULT for MAILBOX_IF */
+
+/* Bit fields for MAILBOX IEN */
+#define _MAILBOX_IEN_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_IEN */
+#define _MAILBOX_IEN_MASK 0x0000000FUL /**< Mask for MAILBOX_IEN */
+#define MAILBOX_IEN_MBOXIEN0 (0x1UL << 0) /**< Mailbox Interrupt Enable */
+#define _MAILBOX_IEN_MBOXIEN0_SHIFT 0 /**< Shift value for MAILBOX_MBOXIEN0 */
+#define _MAILBOX_IEN_MBOXIEN0_MASK 0x1UL /**< Bit mask for MAILBOX_MBOXIEN0 */
+#define _MAILBOX_IEN_MBOXIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */
+#define MAILBOX_IEN_MBOXIEN0_DEFAULT (_MAILBOX_IEN_MBOXIEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_IEN */
+#define MAILBOX_IEN_MBOXIEN1 (0x1UL << 1) /**< Mailbox Interrupt Enable */
+#define _MAILBOX_IEN_MBOXIEN1_SHIFT 1 /**< Shift value for MAILBOX_MBOXIEN1 */
+#define _MAILBOX_IEN_MBOXIEN1_MASK 0x2UL /**< Bit mask for MAILBOX_MBOXIEN1 */
+#define _MAILBOX_IEN_MBOXIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */
+#define MAILBOX_IEN_MBOXIEN1_DEFAULT (_MAILBOX_IEN_MBOXIEN1_DEFAULT << 1) /**< Shifted mode DEFAULT for MAILBOX_IEN */
+#define MAILBOX_IEN_MBOXIEN2 (0x1UL << 2) /**< Mailbox Interrupt Enable */
+#define _MAILBOX_IEN_MBOXIEN2_SHIFT 2 /**< Shift value for MAILBOX_MBOXIEN2 */
+#define _MAILBOX_IEN_MBOXIEN2_MASK 0x4UL /**< Bit mask for MAILBOX_MBOXIEN2 */
+#define _MAILBOX_IEN_MBOXIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */
+#define MAILBOX_IEN_MBOXIEN2_DEFAULT (_MAILBOX_IEN_MBOXIEN2_DEFAULT << 2) /**< Shifted mode DEFAULT for MAILBOX_IEN */
+#define MAILBOX_IEN_MBOXIEN3 (0x1UL << 3) /**< Mailbox Interrupt Enable */
+#define _MAILBOX_IEN_MBOXIEN3_SHIFT 3 /**< Shift value for MAILBOX_MBOXIEN3 */
+#define _MAILBOX_IEN_MBOXIEN3_MASK 0x8UL /**< Bit mask for MAILBOX_MBOXIEN3 */
+#define _MAILBOX_IEN_MBOXIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */
+#define MAILBOX_IEN_MBOXIEN3_DEFAULT (_MAILBOX_IEN_MBOXIEN3_DEFAULT << 3) /**< Shifted mode DEFAULT for MAILBOX_IEN */
+
+/** @} End of group EFR32MG24_MAILBOX_BitFields */
+/** @} End of group EFR32MG24_MAILBOX */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_MAILBOX_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_modem.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_modem.h
new file mode 100644
index 00000000..e3d1c609
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_modem.h
@@ -0,0 +1,6657 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 MODEM register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_MODEM_H
+#define EFR32MG24_MODEM_H
+#define MODEM_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_MODEM MODEM
+ * @{
+ * @brief EFR32MG24 MODEM Register Declaration.
+ *****************************************************************************/
+
+/** MODEM IRCALCOEFWR Register Group Declaration. */
+typedef struct {
+ __IOM uint32_t IRCALCOEFWR; /**< IRCAL COEF WR per antenna */
+} MODEM_IRCALCOEFWR_TypeDef;
+
+/** MODEM Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IP Version */
+ __IOM uint32_t EN; /**< Enable peripheral clock to this module */
+ __IOM uint32_t IF; /**< Interrupt Flags */
+ __IOM uint32_t IEN; /**< Interrupt Enable */
+ __IOM uint32_t SEQIF; /**< SEQ Interrupt Flags */
+ __IOM uint32_t SEQIEN; /**< SEQ Interrupt Enable */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IM uint32_t STATUS2; /**< Status Register 2 */
+ __IM uint32_t STATUS3; /**< Status Register 3 */
+ __IM uint32_t STATUS4; /**< ANT DIV RSSI Status */
+ __IM uint32_t STATUS5; /**< Collision restart status */
+ __IM uint32_t STATUS6; /**< ANT DIV Correlation Status */
+ __IM uint32_t STATUS7; /**< PHASE Demod Status */
+ __IM uint32_t TIMDETSTATUS; /**< Timing Detection Status Register */
+ __IM uint32_t FSMSTATUS; /**< Demod FSM Status Register */
+ __IM uint32_t FREQOFFEST; /**< Frequency Offset Estimate */
+ __IOM uint32_t AFCADJRX; /**< AFC Adjustment RX */
+ __IOM uint32_t AFCADJTX; /**< AFC Adjustment TX */
+ __IOM uint32_t MIXCTRL; /**< Analog mixer control */
+ __IOM uint32_t CTRL0; /**< Control Register 0 */
+ __IOM uint32_t CTRL1; /**< Control Register 1 */
+ __IOM uint32_t CTRL2; /**< Control Register 2 */
+ __IOM uint32_t CTRL3; /**< Control Register 3 */
+ __IOM uint32_t CTRL4; /**< Control Register 4 */
+ __IOM uint32_t CTRL5; /**< Control Register 5 */
+ __IOM uint32_t CTRL6; /**< Control Register 6 */
+ __IOM uint32_t TXBR; /**< Transmit baudrate */
+ __IOM uint32_t RXBR; /**< Receive Baudrate */
+ __IOM uint32_t CF; /**< Channel Filter */
+ __IOM uint32_t PRE; /**< Preamble Register */
+ __IOM uint32_t SYNC0; /**< Sync word 0 */
+ __IOM uint32_t SYNC1; /**< Sync word 1 */
+ __IOM uint32_t TIMING; /**< Timing Register */
+ __IOM uint32_t DSSS0; /**< DSSS symbol 0 Register */
+ __IOM uint32_t MODINDEX; /**< Modulation Index */
+ __IOM uint32_t AFC; /**< Automatic Frequency Control */
+ __IOM uint32_t AFCADJLIM; /**< AFC Adjustment Limit */
+ __IOM uint32_t SHAPING0; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING1; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING2; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING3; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING4; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING5; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING6; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING7; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING8; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING9; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING10; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING11; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING12; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING13; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING14; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING15; /**< Shaping Coefficients */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+ __IOM uint32_t RAMPCTRL; /**< Ramping Register */
+ __IOM uint32_t RAMPLEV; /**< Ramping Register */
+ __IOM uint32_t ANARAMPCTRL; /**< Analog Ramping Control */
+ uint32_t RESERVED1[11U]; /**< Reserved for future use */
+ __IOM uint32_t DCCOMP; /**< DC Offset Compensation Filter Settings */
+ __IOM uint32_t DCCOMPFILTINIT; /**< DC Offset compensation Filter */
+ __IM uint32_t DCESTI; /**< DC Offset Estimated value */
+ __IOM uint32_t SRCCHF; /**< SRC ratio values and channel filter */
+ __IOM uint32_t INTAFC; /**< Internal AFC */
+ __IOM uint32_t DSATHD0; /**< DSA detector threshold-0 */
+ __IOM uint32_t DSATHD1; /**< DSA detector threshold-1 */
+ __IOM uint32_t DSATHD2; /**< DSA detector threshold-2 */
+ __IOM uint32_t DSATHD3; /**< DSA detector threshold 3 */
+ __IOM uint32_t DSATHD4; /**< DSA detector threshold 4 */
+ __IOM uint32_t DSACTRL; /**< DSA mode */
+ __IOM uint32_t DIGMIXCTRL; /**< Digital mixer control register */
+ __IOM uint32_t VITERBIDEMOD; /**< Viterbi demodulator */
+ __IOM uint32_t VTCORRCFG0; /**< Viterbi demodulator */
+ __IOM uint32_t VTCORRCFG1; /**< Viterbi demodulator */
+ __IOM uint32_t VTTRACK; /**< Viterbi demodulator tracking loop */
+ __IOM uint32_t VTBLETIMING; /**< Viterbi BLE timing stamp control */
+ __IM uint32_t BREST; /**< Baudrate Estimate */
+ __IOM uint32_t AUTOCG; /**< Automatic clock gating */
+ __IOM uint32_t CGCLKSTOP; /**< Automatic clock gating */
+ __IM uint32_t POE; /**< Phase Offset Estimate */
+ __IOM uint32_t DIRECTMODE; /**< Direct Mode Control */
+ __IOM uint32_t LONGRANGE; /**< BLE Long Range */
+ __IOM uint32_t LONGRANGE1; /**< BLE Long Range Set1 */
+ __IOM uint32_t LONGRANGE2; /**< BLE Long Range Set2 */
+ __IOM uint32_t LONGRANGE3; /**< BLE Long Range Set3 */
+ __IOM uint32_t LONGRANGE4; /**< BLE Long Range Set4 */
+ __IOM uint32_t LONGRANGE5; /**< BLE Long Range Set5 */
+ __IOM uint32_t LONGRANGE6; /**< BLE Long Range Set6 */
+ __IOM uint32_t LRFRC; /**< BLE Long Range FRC interface */
+ __IOM uint32_t COH0; /**< Coherent demodulator control signals */
+ __IOM uint32_t COH1; /**< Coherent demodulator control signals */
+ __IOM uint32_t COH2; /**< Coherent demodulator control signals */
+ __IOM uint32_t COH3; /**< Coherent demodulator control signals */
+ __IOM uint32_t CMD; /**< Command register */
+ uint32_t RESERVED2[2U]; /**< Reserved for future use */
+ __IOM uint32_t SYNCPROPERTIES; /**< Sync word properties */
+ __IOM uint32_t DIGIGAINCTRL; /**< Digital Gain Control */
+ __IOM uint32_t PRSCTRL; /**< Mux control for PRS outputs */
+ uint32_t RESERVED3[1U]; /**< Reserved for future use */
+ __IOM uint32_t REALTIMCFE; /**< Real time Cost Function Engine CTRL */
+ __IOM uint32_t ETSCTRL; /**< Early Time Stamp Control */
+ __IOM uint32_t ETSTIM; /**< Early Time Stamp Timing */
+ __IOM uint32_t ANTSWCTRL; /**< Antenna Switch Control */
+ __IOM uint32_t ANTSWCTRL1; /**< Antenna Switch Control 1 */
+ __IOM uint32_t ANTSWSTART; /**< Antenna Switch Start */
+ __IOM uint32_t ANTSWEND; /**< Antenna Switch End */
+ __IOM uint32_t TRECPMPATT; /**< TRECS Preamble pattern */
+ __IOM uint32_t TRECPMDET; /**< TRECS preamble Detection CTRL */
+ __IOM uint32_t TRECSCFG; /**< TRECS configuration */
+ __IOM uint32_t CFGANTPATT; /**< Configure Antenna Pattern */
+ __IOM uint32_t COCURRMODE; /**< CONCURRENT MODE */
+ __IOM uint32_t CHFCOE00; /**< CHF COE. Set0 group0 */
+ __IOM uint32_t CHFCOE01; /**< CHF COE. Set0 group1 */
+ __IOM uint32_t CHFCOE02; /**< CHF COE. Set0 group2 */
+ __IOM uint32_t CHFCOE03; /**< CHF COE. Set0 group3 */
+ __IOM uint32_t CHFCOE04; /**< CHF COE. Set0 group4 */
+ __IOM uint32_t CHFCOE05; /**< CHF COE. Set0 group5 */
+ __IOM uint32_t CHFCOE06; /**< CHF COE. Set0 group6 */
+ __IOM uint32_t CHFCOE10; /**< CHF COE. Set1 group0 */
+ __IOM uint32_t CHFCOE11; /**< CHF COE. Set1 group1 */
+ __IOM uint32_t CHFCOE12; /**< CHF COE. Set1 group2 */
+ __IOM uint32_t CHFCOE13; /**< CHF COE. Set1 group3 */
+ __IOM uint32_t CHFCOE14; /**< CHF COE. Set1 group4 */
+ __IOM uint32_t CHFCOE15; /**< CHF COE. Set1 group5 */
+ __IOM uint32_t CHFCOE16; /**< CHF COE. Set1 group6 */
+ __IOM uint32_t CHFCTRL; /**< CHF control */
+ __IOM uint32_t CHFLATENCYCTRL; /**< CHF Latency Control */
+ __IOM uint32_t FRMSCHTIME; /**< FRAM SCH TIME-OUT length */
+ __IOM uint32_t PREFILTCOEFF; /**< Preamble Filter Coefficients */
+ __IOM uint32_t RXRESTART; /**< Collision restart control */
+ __IOM uint32_t SQ; /**< Preamble Sense Mode */
+ __IOM uint32_t SQEXT; /**< Preamble Sense Mode EXT */
+ __IOM uint32_t SQI; /**< Signal quality indicator */
+ __IOM uint32_t ANTDIVCTRL; /**< Antenna Diversity Mode Control Register */
+ __IOM uint32_t ANTDIVFW; /**< PHASE DEMOD FW mode */
+ __IOM uint32_t PHDMODANTDIV; /**< PHASE DEMOD ANTENNA DIVSERSITY */
+ __IOM uint32_t PHANTDECSION; /**< PHASE DEMOD ANT-DIV Decision */
+ __IOM uint32_t PHDMODCTRL; /**< PHASE DEMOD CTRL */
+ __IOM uint32_t SICTRL0; /**< Signal Identifier CTRL0 */
+ __IOM uint32_t SICTRL1; /**< Signal Identifier CTRL1 */
+ __IM uint32_t SISTATUS; /**< Signal Identifier Status */
+ __IOM uint32_t CFGANTPATTEXT; /**< Configure Antenna Pattern */
+ uint32_t RESERVED4[1U]; /**< Reserved for future use */
+ __IOM uint32_t SICTRL2; /**< Signal Identifier CTRL2 */
+ __IOM uint32_t CHFSWCTRL; /**< Channel Filter Switch Time */
+ uint32_t RESERVED5[1U]; /**< Reserved for future use */
+ __IOM uint32_t IRCAL; /**< IRCAL control signals */
+ __IM uint32_t IRCALCOEF; /**< IRCAL COEF values */
+ MODEM_IRCALCOEFWR_TypeDef IRCALCOEFWR[2U]; /**< IRCAL COEFS WR per antenna */
+ __IOM uint32_t ADCTRL1; /**< ADCTRL1 */
+ __IOM uint32_t ADCTRL2; /**< ADCTRL2 */
+ __IM uint32_t ADQUAL0; /**< ADQUAL0 */
+ __IM uint32_t ADQUAL1; /**< ADQUAL1 */
+ __IM uint32_t ADQUAL2; /**< ADQUAL2 */
+ __IM uint32_t ADQUAL3; /**< ADQUAL3 */
+ __IOM uint32_t ADQUAL4; /**< ADQUAL4 */
+ __IOM uint32_t ADQUAL5; /**< ADQUAL5 */
+ __IOM uint32_t ADQUAL6; /**< ADQUAL6 */
+ __IOM uint32_t ADQUAL7; /**< ADQUAL7 */
+ __IOM uint32_t ADQUAL8; /**< ADQUAL8 */
+ __IM uint32_t ADQUAL9; /**< ADQUAL9 */
+ __IM uint32_t ADQUAL10; /**< ADQUAL10 */
+ __IOM uint32_t ADFSM0; /**< ADFSM0 */
+ __IOM uint32_t ADFSM1; /**< ADFSM1 */
+ __IOM uint32_t ADFSM2; /**< ADFSM2 */
+ __IOM uint32_t ADFSM3; /**< ADFSM3 */
+ __IOM uint32_t ADFSM4; /**< ADFSM4 */
+ __IOM uint32_t ADFSM5; /**< ADFSM5 */
+ __IOM uint32_t ADFSM6; /**< ADFSM6 */
+ __IOM uint32_t ADFSM7; /**< ADFSM7 */
+ __IOM uint32_t ADFSM8; /**< ADFSM8 */
+ __IOM uint32_t ADFSM9; /**< ADFSM9 */
+ __IOM uint32_t ADFSM10; /**< ADFSM10 */
+ __IOM uint32_t ADFSM11; /**< ADFSM11 */
+ __IOM uint32_t ADFSM12; /**< ADFSM12 */
+ __IOM uint32_t ADFSM13; /**< ADFSM13 */
+ __IOM uint32_t ADFSM14; /**< ADFSM14 */
+ __IOM uint32_t ADFSM15; /**< ADFSM15 */
+ __IOM uint32_t ADFSM16; /**< ADFSM16 */
+ __IOM uint32_t ADFSM17; /**< ADFSM17 */
+ __IOM uint32_t ADFSM18; /**< ADFSM18 */
+ __IOM uint32_t ADFSM19; /**< ADFSM19 */
+ __IOM uint32_t ADFSM20; /**< ADFSM20 */
+ __IOM uint32_t ADFSM21; /**< ADFSM21 */
+ __IM uint32_t ADFSM22; /**< ADFSM22 */
+ __IOM uint32_t ADFSM23; /**< ADFSM23 */
+ __IOM uint32_t ADFSM24; /**< ADFSM24 */
+ __IOM uint32_t ADFSM25; /**< ADFSM25 */
+ __IOM uint32_t ADFSM26; /**< ADFSM26 */
+ __IOM uint32_t ADFSM27; /**< ADFSM27 */
+ __IOM uint32_t ADFSM28; /**< ADFSM28 */
+ __IOM uint32_t ADFSM29; /**< ADFSM29 */
+ __IOM uint32_t ADFSM30; /**< ADFSM30 */
+ __IOM uint32_t ADPC1; /**< ADPC1 */
+ __IOM uint32_t ADPC2; /**< ADPC2 */
+ __IOM uint32_t ADPC3; /**< ADPC3 */
+ __IOM uint32_t ADPC4; /**< ADPC4 */
+ __IOM uint32_t ADPC5; /**< ADPC5 */
+ __IOM uint32_t ADPC6; /**< ADPC6 */
+ __IOM uint32_t ADPC7; /**< ADPC7 */
+ __IOM uint32_t ADPC8; /**< ADPC8 */
+ __IOM uint32_t ADPC9; /**< ADPC9 */
+ __IOM uint32_t ADPC10; /**< ADPC10 */
+ uint32_t RESERVED6[6U]; /**< Reserved for future use */
+ uint32_t RESERVED7[1U]; /**< Reserved for future use */
+ uint32_t RESERVED8[15U]; /**< Reserved for future use */
+ __IOM uint32_t HADMCTRL0; /**< HADM Control */
+ __IOM uint32_t HADMCTRL1; /**< HADM Control 1 */
+ __IM uint32_t HADMSTATUS0; /**< HADM Status */
+ __IM uint32_t HADMSTATUS1; /**< HADM Status 1 */
+ __IM uint32_t HADMSTATUS2; /**< HADM Status 2 */
+ __IM uint32_t HADMSTATUS3; /**< HADM Status 3 */
+ __IM uint32_t HADMSTATUS4; /**< HADM Status 4 */
+ __IM uint32_t HADMSTATUS5; /**< HADM Status 5 */
+ __IM uint32_t HADMSTATUS6; /**< HADM Status 6 */
+ uint32_t RESERVED9[3U]; /**< Reserved for future use */
+ __IOM uint32_t SRC2NCOCTRL; /**< SRC2 NCO CTRL */
+ uint32_t RESERVED10[7U]; /**< Reserved for future use */
+ __IOM uint32_t SPARE; /**< Spare register */
+ uint32_t RESERVED11[767U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP Version */
+ __IOM uint32_t EN_SET; /**< Enable peripheral clock to this module */
+ __IOM uint32_t IF_SET; /**< Interrupt Flags */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable */
+ __IOM uint32_t SEQIF_SET; /**< SEQ Interrupt Flags */
+ __IOM uint32_t SEQIEN_SET; /**< SEQ Interrupt Enable */
+ __IM uint32_t STATUS_SET; /**< Status Register */
+ __IM uint32_t STATUS2_SET; /**< Status Register 2 */
+ __IM uint32_t STATUS3_SET; /**< Status Register 3 */
+ __IM uint32_t STATUS4_SET; /**< ANT DIV RSSI Status */
+ __IM uint32_t STATUS5_SET; /**< Collision restart status */
+ __IM uint32_t STATUS6_SET; /**< ANT DIV Correlation Status */
+ __IM uint32_t STATUS7_SET; /**< PHASE Demod Status */
+ __IM uint32_t TIMDETSTATUS_SET; /**< Timing Detection Status Register */
+ __IM uint32_t FSMSTATUS_SET; /**< Demod FSM Status Register */
+ __IM uint32_t FREQOFFEST_SET; /**< Frequency Offset Estimate */
+ __IOM uint32_t AFCADJRX_SET; /**< AFC Adjustment RX */
+ __IOM uint32_t AFCADJTX_SET; /**< AFC Adjustment TX */
+ __IOM uint32_t MIXCTRL_SET; /**< Analog mixer control */
+ __IOM uint32_t CTRL0_SET; /**< Control Register 0 */
+ __IOM uint32_t CTRL1_SET; /**< Control Register 1 */
+ __IOM uint32_t CTRL2_SET; /**< Control Register 2 */
+ __IOM uint32_t CTRL3_SET; /**< Control Register 3 */
+ __IOM uint32_t CTRL4_SET; /**< Control Register 4 */
+ __IOM uint32_t CTRL5_SET; /**< Control Register 5 */
+ __IOM uint32_t CTRL6_SET; /**< Control Register 6 */
+ __IOM uint32_t TXBR_SET; /**< Transmit baudrate */
+ __IOM uint32_t RXBR_SET; /**< Receive Baudrate */
+ __IOM uint32_t CF_SET; /**< Channel Filter */
+ __IOM uint32_t PRE_SET; /**< Preamble Register */
+ __IOM uint32_t SYNC0_SET; /**< Sync word 0 */
+ __IOM uint32_t SYNC1_SET; /**< Sync word 1 */
+ __IOM uint32_t TIMING_SET; /**< Timing Register */
+ __IOM uint32_t DSSS0_SET; /**< DSSS symbol 0 Register */
+ __IOM uint32_t MODINDEX_SET; /**< Modulation Index */
+ __IOM uint32_t AFC_SET; /**< Automatic Frequency Control */
+ __IOM uint32_t AFCADJLIM_SET; /**< AFC Adjustment Limit */
+ __IOM uint32_t SHAPING0_SET; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING1_SET; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING2_SET; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING3_SET; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING4_SET; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING5_SET; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING6_SET; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING7_SET; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING8_SET; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING9_SET; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING10_SET; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING11_SET; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING12_SET; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING13_SET; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING14_SET; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING15_SET; /**< Shaping Coefficients */
+ uint32_t RESERVED12[1U]; /**< Reserved for future use */
+ __IOM uint32_t RAMPCTRL_SET; /**< Ramping Register */
+ __IOM uint32_t RAMPLEV_SET; /**< Ramping Register */
+ __IOM uint32_t ANARAMPCTRL_SET; /**< Analog Ramping Control */
+ uint32_t RESERVED13[11U]; /**< Reserved for future use */
+ __IOM uint32_t DCCOMP_SET; /**< DC Offset Compensation Filter Settings */
+ __IOM uint32_t DCCOMPFILTINIT_SET; /**< DC Offset compensation Filter */
+ __IM uint32_t DCESTI_SET; /**< DC Offset Estimated value */
+ __IOM uint32_t SRCCHF_SET; /**< SRC ratio values and channel filter */
+ __IOM uint32_t INTAFC_SET; /**< Internal AFC */
+ __IOM uint32_t DSATHD0_SET; /**< DSA detector threshold-0 */
+ __IOM uint32_t DSATHD1_SET; /**< DSA detector threshold-1 */
+ __IOM uint32_t DSATHD2_SET; /**< DSA detector threshold-2 */
+ __IOM uint32_t DSATHD3_SET; /**< DSA detector threshold 3 */
+ __IOM uint32_t DSATHD4_SET; /**< DSA detector threshold 4 */
+ __IOM uint32_t DSACTRL_SET; /**< DSA mode */
+ __IOM uint32_t DIGMIXCTRL_SET; /**< Digital mixer control register */
+ __IOM uint32_t VITERBIDEMOD_SET; /**< Viterbi demodulator */
+ __IOM uint32_t VTCORRCFG0_SET; /**< Viterbi demodulator */
+ __IOM uint32_t VTCORRCFG1_SET; /**< Viterbi demodulator */
+ __IOM uint32_t VTTRACK_SET; /**< Viterbi demodulator tracking loop */
+ __IOM uint32_t VTBLETIMING_SET; /**< Viterbi BLE timing stamp control */
+ __IM uint32_t BREST_SET; /**< Baudrate Estimate */
+ __IOM uint32_t AUTOCG_SET; /**< Automatic clock gating */
+ __IOM uint32_t CGCLKSTOP_SET; /**< Automatic clock gating */
+ __IM uint32_t POE_SET; /**< Phase Offset Estimate */
+ __IOM uint32_t DIRECTMODE_SET; /**< Direct Mode Control */
+ __IOM uint32_t LONGRANGE_SET; /**< BLE Long Range */
+ __IOM uint32_t LONGRANGE1_SET; /**< BLE Long Range Set1 */
+ __IOM uint32_t LONGRANGE2_SET; /**< BLE Long Range Set2 */
+ __IOM uint32_t LONGRANGE3_SET; /**< BLE Long Range Set3 */
+ __IOM uint32_t LONGRANGE4_SET; /**< BLE Long Range Set4 */
+ __IOM uint32_t LONGRANGE5_SET; /**< BLE Long Range Set5 */
+ __IOM uint32_t LONGRANGE6_SET; /**< BLE Long Range Set6 */
+ __IOM uint32_t LRFRC_SET; /**< BLE Long Range FRC interface */
+ __IOM uint32_t COH0_SET; /**< Coherent demodulator control signals */
+ __IOM uint32_t COH1_SET; /**< Coherent demodulator control signals */
+ __IOM uint32_t COH2_SET; /**< Coherent demodulator control signals */
+ __IOM uint32_t COH3_SET; /**< Coherent demodulator control signals */
+ __IOM uint32_t CMD_SET; /**< Command register */
+ uint32_t RESERVED14[2U]; /**< Reserved for future use */
+ __IOM uint32_t SYNCPROPERTIES_SET; /**< Sync word properties */
+ __IOM uint32_t DIGIGAINCTRL_SET; /**< Digital Gain Control */
+ __IOM uint32_t PRSCTRL_SET; /**< Mux control for PRS outputs */
+ uint32_t RESERVED15[1U]; /**< Reserved for future use */
+ __IOM uint32_t REALTIMCFE_SET; /**< Real time Cost Function Engine CTRL */
+ __IOM uint32_t ETSCTRL_SET; /**< Early Time Stamp Control */
+ __IOM uint32_t ETSTIM_SET; /**< Early Time Stamp Timing */
+ __IOM uint32_t ANTSWCTRL_SET; /**< Antenna Switch Control */
+ __IOM uint32_t ANTSWCTRL1_SET; /**< Antenna Switch Control 1 */
+ __IOM uint32_t ANTSWSTART_SET; /**< Antenna Switch Start */
+ __IOM uint32_t ANTSWEND_SET; /**< Antenna Switch End */
+ __IOM uint32_t TRECPMPATT_SET; /**< TRECS Preamble pattern */
+ __IOM uint32_t TRECPMDET_SET; /**< TRECS preamble Detection CTRL */
+ __IOM uint32_t TRECSCFG_SET; /**< TRECS configuration */
+ __IOM uint32_t CFGANTPATT_SET; /**< Configure Antenna Pattern */
+ __IOM uint32_t COCURRMODE_SET; /**< CONCURRENT MODE */
+ __IOM uint32_t CHFCOE00_SET; /**< CHF COE. Set0 group0 */
+ __IOM uint32_t CHFCOE01_SET; /**< CHF COE. Set0 group1 */
+ __IOM uint32_t CHFCOE02_SET; /**< CHF COE. Set0 group2 */
+ __IOM uint32_t CHFCOE03_SET; /**< CHF COE. Set0 group3 */
+ __IOM uint32_t CHFCOE04_SET; /**< CHF COE. Set0 group4 */
+ __IOM uint32_t CHFCOE05_SET; /**< CHF COE. Set0 group5 */
+ __IOM uint32_t CHFCOE06_SET; /**< CHF COE. Set0 group6 */
+ __IOM uint32_t CHFCOE10_SET; /**< CHF COE. Set1 group0 */
+ __IOM uint32_t CHFCOE11_SET; /**< CHF COE. Set1 group1 */
+ __IOM uint32_t CHFCOE12_SET; /**< CHF COE. Set1 group2 */
+ __IOM uint32_t CHFCOE13_SET; /**< CHF COE. Set1 group3 */
+ __IOM uint32_t CHFCOE14_SET; /**< CHF COE. Set1 group4 */
+ __IOM uint32_t CHFCOE15_SET; /**< CHF COE. Set1 group5 */
+ __IOM uint32_t CHFCOE16_SET; /**< CHF COE. Set1 group6 */
+ __IOM uint32_t CHFCTRL_SET; /**< CHF control */
+ __IOM uint32_t CHFLATENCYCTRL_SET; /**< CHF Latency Control */
+ __IOM uint32_t FRMSCHTIME_SET; /**< FRAM SCH TIME-OUT length */
+ __IOM uint32_t PREFILTCOEFF_SET; /**< Preamble Filter Coefficients */
+ __IOM uint32_t RXRESTART_SET; /**< Collision restart control */
+ __IOM uint32_t SQ_SET; /**< Preamble Sense Mode */
+ __IOM uint32_t SQEXT_SET; /**< Preamble Sense Mode EXT */
+ __IOM uint32_t SQI_SET; /**< Signal quality indicator */
+ __IOM uint32_t ANTDIVCTRL_SET; /**< Antenna Diversity Mode Control Register */
+ __IOM uint32_t ANTDIVFW_SET; /**< PHASE DEMOD FW mode */
+ __IOM uint32_t PHDMODANTDIV_SET; /**< PHASE DEMOD ANTENNA DIVSERSITY */
+ __IOM uint32_t PHANTDECSION_SET; /**< PHASE DEMOD ANT-DIV Decision */
+ __IOM uint32_t PHDMODCTRL_SET; /**< PHASE DEMOD CTRL */
+ __IOM uint32_t SICTRL0_SET; /**< Signal Identifier CTRL0 */
+ __IOM uint32_t SICTRL1_SET; /**< Signal Identifier CTRL1 */
+ __IM uint32_t SISTATUS_SET; /**< Signal Identifier Status */
+ __IOM uint32_t CFGANTPATTEXT_SET; /**< Configure Antenna Pattern */
+ uint32_t RESERVED16[1U]; /**< Reserved for future use */
+ __IOM uint32_t SICTRL2_SET; /**< Signal Identifier CTRL2 */
+ __IOM uint32_t CHFSWCTRL_SET; /**< Channel Filter Switch Time */
+ uint32_t RESERVED17[1U]; /**< Reserved for future use */
+ __IOM uint32_t IRCAL_SET; /**< IRCAL control signals */
+ __IM uint32_t IRCALCOEF_SET; /**< IRCAL COEF values */
+ MODEM_IRCALCOEFWR_TypeDef IRCALCOEFWR_SET[2U]; /**< IRCAL COEFS WR per antenna */
+ __IOM uint32_t ADCTRL1_SET; /**< ADCTRL1 */
+ __IOM uint32_t ADCTRL2_SET; /**< ADCTRL2 */
+ __IM uint32_t ADQUAL0_SET; /**< ADQUAL0 */
+ __IM uint32_t ADQUAL1_SET; /**< ADQUAL1 */
+ __IM uint32_t ADQUAL2_SET; /**< ADQUAL2 */
+ __IM uint32_t ADQUAL3_SET; /**< ADQUAL3 */
+ __IOM uint32_t ADQUAL4_SET; /**< ADQUAL4 */
+ __IOM uint32_t ADQUAL5_SET; /**< ADQUAL5 */
+ __IOM uint32_t ADQUAL6_SET; /**< ADQUAL6 */
+ __IOM uint32_t ADQUAL7_SET; /**< ADQUAL7 */
+ __IOM uint32_t ADQUAL8_SET; /**< ADQUAL8 */
+ __IM uint32_t ADQUAL9_SET; /**< ADQUAL9 */
+ __IM uint32_t ADQUAL10_SET; /**< ADQUAL10 */
+ __IOM uint32_t ADFSM0_SET; /**< ADFSM0 */
+ __IOM uint32_t ADFSM1_SET; /**< ADFSM1 */
+ __IOM uint32_t ADFSM2_SET; /**< ADFSM2 */
+ __IOM uint32_t ADFSM3_SET; /**< ADFSM3 */
+ __IOM uint32_t ADFSM4_SET; /**< ADFSM4 */
+ __IOM uint32_t ADFSM5_SET; /**< ADFSM5 */
+ __IOM uint32_t ADFSM6_SET; /**< ADFSM6 */
+ __IOM uint32_t ADFSM7_SET; /**< ADFSM7 */
+ __IOM uint32_t ADFSM8_SET; /**< ADFSM8 */
+ __IOM uint32_t ADFSM9_SET; /**< ADFSM9 */
+ __IOM uint32_t ADFSM10_SET; /**< ADFSM10 */
+ __IOM uint32_t ADFSM11_SET; /**< ADFSM11 */
+ __IOM uint32_t ADFSM12_SET; /**< ADFSM12 */
+ __IOM uint32_t ADFSM13_SET; /**< ADFSM13 */
+ __IOM uint32_t ADFSM14_SET; /**< ADFSM14 */
+ __IOM uint32_t ADFSM15_SET; /**< ADFSM15 */
+ __IOM uint32_t ADFSM16_SET; /**< ADFSM16 */
+ __IOM uint32_t ADFSM17_SET; /**< ADFSM17 */
+ __IOM uint32_t ADFSM18_SET; /**< ADFSM18 */
+ __IOM uint32_t ADFSM19_SET; /**< ADFSM19 */
+ __IOM uint32_t ADFSM20_SET; /**< ADFSM20 */
+ __IOM uint32_t ADFSM21_SET; /**< ADFSM21 */
+ __IM uint32_t ADFSM22_SET; /**< ADFSM22 */
+ __IOM uint32_t ADFSM23_SET; /**< ADFSM23 */
+ __IOM uint32_t ADFSM24_SET; /**< ADFSM24 */
+ __IOM uint32_t ADFSM25_SET; /**< ADFSM25 */
+ __IOM uint32_t ADFSM26_SET; /**< ADFSM26 */
+ __IOM uint32_t ADFSM27_SET; /**< ADFSM27 */
+ __IOM uint32_t ADFSM28_SET; /**< ADFSM28 */
+ __IOM uint32_t ADFSM29_SET; /**< ADFSM29 */
+ __IOM uint32_t ADFSM30_SET; /**< ADFSM30 */
+ __IOM uint32_t ADPC1_SET; /**< ADPC1 */
+ __IOM uint32_t ADPC2_SET; /**< ADPC2 */
+ __IOM uint32_t ADPC3_SET; /**< ADPC3 */
+ __IOM uint32_t ADPC4_SET; /**< ADPC4 */
+ __IOM uint32_t ADPC5_SET; /**< ADPC5 */
+ __IOM uint32_t ADPC6_SET; /**< ADPC6 */
+ __IOM uint32_t ADPC7_SET; /**< ADPC7 */
+ __IOM uint32_t ADPC8_SET; /**< ADPC8 */
+ __IOM uint32_t ADPC9_SET; /**< ADPC9 */
+ __IOM uint32_t ADPC10_SET; /**< ADPC10 */
+ uint32_t RESERVED18[6U]; /**< Reserved for future use */
+ uint32_t RESERVED19[1U]; /**< Reserved for future use */
+ uint32_t RESERVED20[15U]; /**< Reserved for future use */
+ __IOM uint32_t HADMCTRL0_SET; /**< HADM Control */
+ __IOM uint32_t HADMCTRL1_SET; /**< HADM Control 1 */
+ __IM uint32_t HADMSTATUS0_SET; /**< HADM Status */
+ __IM uint32_t HADMSTATUS1_SET; /**< HADM Status 1 */
+ __IM uint32_t HADMSTATUS2_SET; /**< HADM Status 2 */
+ __IM uint32_t HADMSTATUS3_SET; /**< HADM Status 3 */
+ __IM uint32_t HADMSTATUS4_SET; /**< HADM Status 4 */
+ __IM uint32_t HADMSTATUS5_SET; /**< HADM Status 5 */
+ __IM uint32_t HADMSTATUS6_SET; /**< HADM Status 6 */
+ uint32_t RESERVED21[3U]; /**< Reserved for future use */
+ __IOM uint32_t SRC2NCOCTRL_SET; /**< SRC2 NCO CTRL */
+ uint32_t RESERVED22[7U]; /**< Reserved for future use */
+ __IOM uint32_t SPARE_SET; /**< Spare register */
+ uint32_t RESERVED23[767U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP Version */
+ __IOM uint32_t EN_CLR; /**< Enable peripheral clock to this module */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flags */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable */
+ __IOM uint32_t SEQIF_CLR; /**< SEQ Interrupt Flags */
+ __IOM uint32_t SEQIEN_CLR; /**< SEQ Interrupt Enable */
+ __IM uint32_t STATUS_CLR; /**< Status Register */
+ __IM uint32_t STATUS2_CLR; /**< Status Register 2 */
+ __IM uint32_t STATUS3_CLR; /**< Status Register 3 */
+ __IM uint32_t STATUS4_CLR; /**< ANT DIV RSSI Status */
+ __IM uint32_t STATUS5_CLR; /**< Collision restart status */
+ __IM uint32_t STATUS6_CLR; /**< ANT DIV Correlation Status */
+ __IM uint32_t STATUS7_CLR; /**< PHASE Demod Status */
+ __IM uint32_t TIMDETSTATUS_CLR; /**< Timing Detection Status Register */
+ __IM uint32_t FSMSTATUS_CLR; /**< Demod FSM Status Register */
+ __IM uint32_t FREQOFFEST_CLR; /**< Frequency Offset Estimate */
+ __IOM uint32_t AFCADJRX_CLR; /**< AFC Adjustment RX */
+ __IOM uint32_t AFCADJTX_CLR; /**< AFC Adjustment TX */
+ __IOM uint32_t MIXCTRL_CLR; /**< Analog mixer control */
+ __IOM uint32_t CTRL0_CLR; /**< Control Register 0 */
+ __IOM uint32_t CTRL1_CLR; /**< Control Register 1 */
+ __IOM uint32_t CTRL2_CLR; /**< Control Register 2 */
+ __IOM uint32_t CTRL3_CLR; /**< Control Register 3 */
+ __IOM uint32_t CTRL4_CLR; /**< Control Register 4 */
+ __IOM uint32_t CTRL5_CLR; /**< Control Register 5 */
+ __IOM uint32_t CTRL6_CLR; /**< Control Register 6 */
+ __IOM uint32_t TXBR_CLR; /**< Transmit baudrate */
+ __IOM uint32_t RXBR_CLR; /**< Receive Baudrate */
+ __IOM uint32_t CF_CLR; /**< Channel Filter */
+ __IOM uint32_t PRE_CLR; /**< Preamble Register */
+ __IOM uint32_t SYNC0_CLR; /**< Sync word 0 */
+ __IOM uint32_t SYNC1_CLR; /**< Sync word 1 */
+ __IOM uint32_t TIMING_CLR; /**< Timing Register */
+ __IOM uint32_t DSSS0_CLR; /**< DSSS symbol 0 Register */
+ __IOM uint32_t MODINDEX_CLR; /**< Modulation Index */
+ __IOM uint32_t AFC_CLR; /**< Automatic Frequency Control */
+ __IOM uint32_t AFCADJLIM_CLR; /**< AFC Adjustment Limit */
+ __IOM uint32_t SHAPING0_CLR; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING1_CLR; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING2_CLR; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING3_CLR; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING4_CLR; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING5_CLR; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING6_CLR; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING7_CLR; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING8_CLR; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING9_CLR; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING10_CLR; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING11_CLR; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING12_CLR; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING13_CLR; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING14_CLR; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING15_CLR; /**< Shaping Coefficients */
+ uint32_t RESERVED24[1U]; /**< Reserved for future use */
+ __IOM uint32_t RAMPCTRL_CLR; /**< Ramping Register */
+ __IOM uint32_t RAMPLEV_CLR; /**< Ramping Register */
+ __IOM uint32_t ANARAMPCTRL_CLR; /**< Analog Ramping Control */
+ uint32_t RESERVED25[11U]; /**< Reserved for future use */
+ __IOM uint32_t DCCOMP_CLR; /**< DC Offset Compensation Filter Settings */
+ __IOM uint32_t DCCOMPFILTINIT_CLR; /**< DC Offset compensation Filter */
+ __IM uint32_t DCESTI_CLR; /**< DC Offset Estimated value */
+ __IOM uint32_t SRCCHF_CLR; /**< SRC ratio values and channel filter */
+ __IOM uint32_t INTAFC_CLR; /**< Internal AFC */
+ __IOM uint32_t DSATHD0_CLR; /**< DSA detector threshold-0 */
+ __IOM uint32_t DSATHD1_CLR; /**< DSA detector threshold-1 */
+ __IOM uint32_t DSATHD2_CLR; /**< DSA detector threshold-2 */
+ __IOM uint32_t DSATHD3_CLR; /**< DSA detector threshold 3 */
+ __IOM uint32_t DSATHD4_CLR; /**< DSA detector threshold 4 */
+ __IOM uint32_t DSACTRL_CLR; /**< DSA mode */
+ __IOM uint32_t DIGMIXCTRL_CLR; /**< Digital mixer control register */
+ __IOM uint32_t VITERBIDEMOD_CLR; /**< Viterbi demodulator */
+ __IOM uint32_t VTCORRCFG0_CLR; /**< Viterbi demodulator */
+ __IOM uint32_t VTCORRCFG1_CLR; /**< Viterbi demodulator */
+ __IOM uint32_t VTTRACK_CLR; /**< Viterbi demodulator tracking loop */
+ __IOM uint32_t VTBLETIMING_CLR; /**< Viterbi BLE timing stamp control */
+ __IM uint32_t BREST_CLR; /**< Baudrate Estimate */
+ __IOM uint32_t AUTOCG_CLR; /**< Automatic clock gating */
+ __IOM uint32_t CGCLKSTOP_CLR; /**< Automatic clock gating */
+ __IM uint32_t POE_CLR; /**< Phase Offset Estimate */
+ __IOM uint32_t DIRECTMODE_CLR; /**< Direct Mode Control */
+ __IOM uint32_t LONGRANGE_CLR; /**< BLE Long Range */
+ __IOM uint32_t LONGRANGE1_CLR; /**< BLE Long Range Set1 */
+ __IOM uint32_t LONGRANGE2_CLR; /**< BLE Long Range Set2 */
+ __IOM uint32_t LONGRANGE3_CLR; /**< BLE Long Range Set3 */
+ __IOM uint32_t LONGRANGE4_CLR; /**< BLE Long Range Set4 */
+ __IOM uint32_t LONGRANGE5_CLR; /**< BLE Long Range Set5 */
+ __IOM uint32_t LONGRANGE6_CLR; /**< BLE Long Range Set6 */
+ __IOM uint32_t LRFRC_CLR; /**< BLE Long Range FRC interface */
+ __IOM uint32_t COH0_CLR; /**< Coherent demodulator control signals */
+ __IOM uint32_t COH1_CLR; /**< Coherent demodulator control signals */
+ __IOM uint32_t COH2_CLR; /**< Coherent demodulator control signals */
+ __IOM uint32_t COH3_CLR; /**< Coherent demodulator control signals */
+ __IOM uint32_t CMD_CLR; /**< Command register */
+ uint32_t RESERVED26[2U]; /**< Reserved for future use */
+ __IOM uint32_t SYNCPROPERTIES_CLR; /**< Sync word properties */
+ __IOM uint32_t DIGIGAINCTRL_CLR; /**< Digital Gain Control */
+ __IOM uint32_t PRSCTRL_CLR; /**< Mux control for PRS outputs */
+ uint32_t RESERVED27[1U]; /**< Reserved for future use */
+ __IOM uint32_t REALTIMCFE_CLR; /**< Real time Cost Function Engine CTRL */
+ __IOM uint32_t ETSCTRL_CLR; /**< Early Time Stamp Control */
+ __IOM uint32_t ETSTIM_CLR; /**< Early Time Stamp Timing */
+ __IOM uint32_t ANTSWCTRL_CLR; /**< Antenna Switch Control */
+ __IOM uint32_t ANTSWCTRL1_CLR; /**< Antenna Switch Control 1 */
+ __IOM uint32_t ANTSWSTART_CLR; /**< Antenna Switch Start */
+ __IOM uint32_t ANTSWEND_CLR; /**< Antenna Switch End */
+ __IOM uint32_t TRECPMPATT_CLR; /**< TRECS Preamble pattern */
+ __IOM uint32_t TRECPMDET_CLR; /**< TRECS preamble Detection CTRL */
+ __IOM uint32_t TRECSCFG_CLR; /**< TRECS configuration */
+ __IOM uint32_t CFGANTPATT_CLR; /**< Configure Antenna Pattern */
+ __IOM uint32_t COCURRMODE_CLR; /**< CONCURRENT MODE */
+ __IOM uint32_t CHFCOE00_CLR; /**< CHF COE. Set0 group0 */
+ __IOM uint32_t CHFCOE01_CLR; /**< CHF COE. Set0 group1 */
+ __IOM uint32_t CHFCOE02_CLR; /**< CHF COE. Set0 group2 */
+ __IOM uint32_t CHFCOE03_CLR; /**< CHF COE. Set0 group3 */
+ __IOM uint32_t CHFCOE04_CLR; /**< CHF COE. Set0 group4 */
+ __IOM uint32_t CHFCOE05_CLR; /**< CHF COE. Set0 group5 */
+ __IOM uint32_t CHFCOE06_CLR; /**< CHF COE. Set0 group6 */
+ __IOM uint32_t CHFCOE10_CLR; /**< CHF COE. Set1 group0 */
+ __IOM uint32_t CHFCOE11_CLR; /**< CHF COE. Set1 group1 */
+ __IOM uint32_t CHFCOE12_CLR; /**< CHF COE. Set1 group2 */
+ __IOM uint32_t CHFCOE13_CLR; /**< CHF COE. Set1 group3 */
+ __IOM uint32_t CHFCOE14_CLR; /**< CHF COE. Set1 group4 */
+ __IOM uint32_t CHFCOE15_CLR; /**< CHF COE. Set1 group5 */
+ __IOM uint32_t CHFCOE16_CLR; /**< CHF COE. Set1 group6 */
+ __IOM uint32_t CHFCTRL_CLR; /**< CHF control */
+ __IOM uint32_t CHFLATENCYCTRL_CLR; /**< CHF Latency Control */
+ __IOM uint32_t FRMSCHTIME_CLR; /**< FRAM SCH TIME-OUT length */
+ __IOM uint32_t PREFILTCOEFF_CLR; /**< Preamble Filter Coefficients */
+ __IOM uint32_t RXRESTART_CLR; /**< Collision restart control */
+ __IOM uint32_t SQ_CLR; /**< Preamble Sense Mode */
+ __IOM uint32_t SQEXT_CLR; /**< Preamble Sense Mode EXT */
+ __IOM uint32_t SQI_CLR; /**< Signal quality indicator */
+ __IOM uint32_t ANTDIVCTRL_CLR; /**< Antenna Diversity Mode Control Register */
+ __IOM uint32_t ANTDIVFW_CLR; /**< PHASE DEMOD FW mode */
+ __IOM uint32_t PHDMODANTDIV_CLR; /**< PHASE DEMOD ANTENNA DIVSERSITY */
+ __IOM uint32_t PHANTDECSION_CLR; /**< PHASE DEMOD ANT-DIV Decision */
+ __IOM uint32_t PHDMODCTRL_CLR; /**< PHASE DEMOD CTRL */
+ __IOM uint32_t SICTRL0_CLR; /**< Signal Identifier CTRL0 */
+ __IOM uint32_t SICTRL1_CLR; /**< Signal Identifier CTRL1 */
+ __IM uint32_t SISTATUS_CLR; /**< Signal Identifier Status */
+ __IOM uint32_t CFGANTPATTEXT_CLR; /**< Configure Antenna Pattern */
+ uint32_t RESERVED28[1U]; /**< Reserved for future use */
+ __IOM uint32_t SICTRL2_CLR; /**< Signal Identifier CTRL2 */
+ __IOM uint32_t CHFSWCTRL_CLR; /**< Channel Filter Switch Time */
+ uint32_t RESERVED29[1U]; /**< Reserved for future use */
+ __IOM uint32_t IRCAL_CLR; /**< IRCAL control signals */
+ __IM uint32_t IRCALCOEF_CLR; /**< IRCAL COEF values */
+ MODEM_IRCALCOEFWR_TypeDef IRCALCOEFWR_CLR[2U]; /**< IRCAL COEFS WR per antenna */
+ __IOM uint32_t ADCTRL1_CLR; /**< ADCTRL1 */
+ __IOM uint32_t ADCTRL2_CLR; /**< ADCTRL2 */
+ __IM uint32_t ADQUAL0_CLR; /**< ADQUAL0 */
+ __IM uint32_t ADQUAL1_CLR; /**< ADQUAL1 */
+ __IM uint32_t ADQUAL2_CLR; /**< ADQUAL2 */
+ __IM uint32_t ADQUAL3_CLR; /**< ADQUAL3 */
+ __IOM uint32_t ADQUAL4_CLR; /**< ADQUAL4 */
+ __IOM uint32_t ADQUAL5_CLR; /**< ADQUAL5 */
+ __IOM uint32_t ADQUAL6_CLR; /**< ADQUAL6 */
+ __IOM uint32_t ADQUAL7_CLR; /**< ADQUAL7 */
+ __IOM uint32_t ADQUAL8_CLR; /**< ADQUAL8 */
+ __IM uint32_t ADQUAL9_CLR; /**< ADQUAL9 */
+ __IM uint32_t ADQUAL10_CLR; /**< ADQUAL10 */
+ __IOM uint32_t ADFSM0_CLR; /**< ADFSM0 */
+ __IOM uint32_t ADFSM1_CLR; /**< ADFSM1 */
+ __IOM uint32_t ADFSM2_CLR; /**< ADFSM2 */
+ __IOM uint32_t ADFSM3_CLR; /**< ADFSM3 */
+ __IOM uint32_t ADFSM4_CLR; /**< ADFSM4 */
+ __IOM uint32_t ADFSM5_CLR; /**< ADFSM5 */
+ __IOM uint32_t ADFSM6_CLR; /**< ADFSM6 */
+ __IOM uint32_t ADFSM7_CLR; /**< ADFSM7 */
+ __IOM uint32_t ADFSM8_CLR; /**< ADFSM8 */
+ __IOM uint32_t ADFSM9_CLR; /**< ADFSM9 */
+ __IOM uint32_t ADFSM10_CLR; /**< ADFSM10 */
+ __IOM uint32_t ADFSM11_CLR; /**< ADFSM11 */
+ __IOM uint32_t ADFSM12_CLR; /**< ADFSM12 */
+ __IOM uint32_t ADFSM13_CLR; /**< ADFSM13 */
+ __IOM uint32_t ADFSM14_CLR; /**< ADFSM14 */
+ __IOM uint32_t ADFSM15_CLR; /**< ADFSM15 */
+ __IOM uint32_t ADFSM16_CLR; /**< ADFSM16 */
+ __IOM uint32_t ADFSM17_CLR; /**< ADFSM17 */
+ __IOM uint32_t ADFSM18_CLR; /**< ADFSM18 */
+ __IOM uint32_t ADFSM19_CLR; /**< ADFSM19 */
+ __IOM uint32_t ADFSM20_CLR; /**< ADFSM20 */
+ __IOM uint32_t ADFSM21_CLR; /**< ADFSM21 */
+ __IM uint32_t ADFSM22_CLR; /**< ADFSM22 */
+ __IOM uint32_t ADFSM23_CLR; /**< ADFSM23 */
+ __IOM uint32_t ADFSM24_CLR; /**< ADFSM24 */
+ __IOM uint32_t ADFSM25_CLR; /**< ADFSM25 */
+ __IOM uint32_t ADFSM26_CLR; /**< ADFSM26 */
+ __IOM uint32_t ADFSM27_CLR; /**< ADFSM27 */
+ __IOM uint32_t ADFSM28_CLR; /**< ADFSM28 */
+ __IOM uint32_t ADFSM29_CLR; /**< ADFSM29 */
+ __IOM uint32_t ADFSM30_CLR; /**< ADFSM30 */
+ __IOM uint32_t ADPC1_CLR; /**< ADPC1 */
+ __IOM uint32_t ADPC2_CLR; /**< ADPC2 */
+ __IOM uint32_t ADPC3_CLR; /**< ADPC3 */
+ __IOM uint32_t ADPC4_CLR; /**< ADPC4 */
+ __IOM uint32_t ADPC5_CLR; /**< ADPC5 */
+ __IOM uint32_t ADPC6_CLR; /**< ADPC6 */
+ __IOM uint32_t ADPC7_CLR; /**< ADPC7 */
+ __IOM uint32_t ADPC8_CLR; /**< ADPC8 */
+ __IOM uint32_t ADPC9_CLR; /**< ADPC9 */
+ __IOM uint32_t ADPC10_CLR; /**< ADPC10 */
+ uint32_t RESERVED30[6U]; /**< Reserved for future use */
+ uint32_t RESERVED31[1U]; /**< Reserved for future use */
+ uint32_t RESERVED32[15U]; /**< Reserved for future use */
+ __IOM uint32_t HADMCTRL0_CLR; /**< HADM Control */
+ __IOM uint32_t HADMCTRL1_CLR; /**< HADM Control 1 */
+ __IM uint32_t HADMSTATUS0_CLR; /**< HADM Status */
+ __IM uint32_t HADMSTATUS1_CLR; /**< HADM Status 1 */
+ __IM uint32_t HADMSTATUS2_CLR; /**< HADM Status 2 */
+ __IM uint32_t HADMSTATUS3_CLR; /**< HADM Status 3 */
+ __IM uint32_t HADMSTATUS4_CLR; /**< HADM Status 4 */
+ __IM uint32_t HADMSTATUS5_CLR; /**< HADM Status 5 */
+ __IM uint32_t HADMSTATUS6_CLR; /**< HADM Status 6 */
+ uint32_t RESERVED33[3U]; /**< Reserved for future use */
+ __IOM uint32_t SRC2NCOCTRL_CLR; /**< SRC2 NCO CTRL */
+ uint32_t RESERVED34[7U]; /**< Reserved for future use */
+ __IOM uint32_t SPARE_CLR; /**< Spare register */
+ uint32_t RESERVED35[767U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP Version */
+ __IOM uint32_t EN_TGL; /**< Enable peripheral clock to this module */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flags */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable */
+ __IOM uint32_t SEQIF_TGL; /**< SEQ Interrupt Flags */
+ __IOM uint32_t SEQIEN_TGL; /**< SEQ Interrupt Enable */
+ __IM uint32_t STATUS_TGL; /**< Status Register */
+ __IM uint32_t STATUS2_TGL; /**< Status Register 2 */
+ __IM uint32_t STATUS3_TGL; /**< Status Register 3 */
+ __IM uint32_t STATUS4_TGL; /**< ANT DIV RSSI Status */
+ __IM uint32_t STATUS5_TGL; /**< Collision restart status */
+ __IM uint32_t STATUS6_TGL; /**< ANT DIV Correlation Status */
+ __IM uint32_t STATUS7_TGL; /**< PHASE Demod Status */
+ __IM uint32_t TIMDETSTATUS_TGL; /**< Timing Detection Status Register */
+ __IM uint32_t FSMSTATUS_TGL; /**< Demod FSM Status Register */
+ __IM uint32_t FREQOFFEST_TGL; /**< Frequency Offset Estimate */
+ __IOM uint32_t AFCADJRX_TGL; /**< AFC Adjustment RX */
+ __IOM uint32_t AFCADJTX_TGL; /**< AFC Adjustment TX */
+ __IOM uint32_t MIXCTRL_TGL; /**< Analog mixer control */
+ __IOM uint32_t CTRL0_TGL; /**< Control Register 0 */
+ __IOM uint32_t CTRL1_TGL; /**< Control Register 1 */
+ __IOM uint32_t CTRL2_TGL; /**< Control Register 2 */
+ __IOM uint32_t CTRL3_TGL; /**< Control Register 3 */
+ __IOM uint32_t CTRL4_TGL; /**< Control Register 4 */
+ __IOM uint32_t CTRL5_TGL; /**< Control Register 5 */
+ __IOM uint32_t CTRL6_TGL; /**< Control Register 6 */
+ __IOM uint32_t TXBR_TGL; /**< Transmit baudrate */
+ __IOM uint32_t RXBR_TGL; /**< Receive Baudrate */
+ __IOM uint32_t CF_TGL; /**< Channel Filter */
+ __IOM uint32_t PRE_TGL; /**< Preamble Register */
+ __IOM uint32_t SYNC0_TGL; /**< Sync word 0 */
+ __IOM uint32_t SYNC1_TGL; /**< Sync word 1 */
+ __IOM uint32_t TIMING_TGL; /**< Timing Register */
+ __IOM uint32_t DSSS0_TGL; /**< DSSS symbol 0 Register */
+ __IOM uint32_t MODINDEX_TGL; /**< Modulation Index */
+ __IOM uint32_t AFC_TGL; /**< Automatic Frequency Control */
+ __IOM uint32_t AFCADJLIM_TGL; /**< AFC Adjustment Limit */
+ __IOM uint32_t SHAPING0_TGL; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING1_TGL; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING2_TGL; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING3_TGL; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING4_TGL; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING5_TGL; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING6_TGL; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING7_TGL; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING8_TGL; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING9_TGL; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING10_TGL; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING11_TGL; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING12_TGL; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING13_TGL; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING14_TGL; /**< Shaping Coefficients */
+ __IOM uint32_t SHAPING15_TGL; /**< Shaping Coefficients */
+ uint32_t RESERVED36[1U]; /**< Reserved for future use */
+ __IOM uint32_t RAMPCTRL_TGL; /**< Ramping Register */
+ __IOM uint32_t RAMPLEV_TGL; /**< Ramping Register */
+ __IOM uint32_t ANARAMPCTRL_TGL; /**< Analog Ramping Control */
+ uint32_t RESERVED37[11U]; /**< Reserved for future use */
+ __IOM uint32_t DCCOMP_TGL; /**< DC Offset Compensation Filter Settings */
+ __IOM uint32_t DCCOMPFILTINIT_TGL; /**< DC Offset compensation Filter */
+ __IM uint32_t DCESTI_TGL; /**< DC Offset Estimated value */
+ __IOM uint32_t SRCCHF_TGL; /**< SRC ratio values and channel filter */
+ __IOM uint32_t INTAFC_TGL; /**< Internal AFC */
+ __IOM uint32_t DSATHD0_TGL; /**< DSA detector threshold-0 */
+ __IOM uint32_t DSATHD1_TGL; /**< DSA detector threshold-1 */
+ __IOM uint32_t DSATHD2_TGL; /**< DSA detector threshold-2 */
+ __IOM uint32_t DSATHD3_TGL; /**< DSA detector threshold 3 */
+ __IOM uint32_t DSATHD4_TGL; /**< DSA detector threshold 4 */
+ __IOM uint32_t DSACTRL_TGL; /**< DSA mode */
+ __IOM uint32_t DIGMIXCTRL_TGL; /**< Digital mixer control register */
+ __IOM uint32_t VITERBIDEMOD_TGL; /**< Viterbi demodulator */
+ __IOM uint32_t VTCORRCFG0_TGL; /**< Viterbi demodulator */
+ __IOM uint32_t VTCORRCFG1_TGL; /**< Viterbi demodulator */
+ __IOM uint32_t VTTRACK_TGL; /**< Viterbi demodulator tracking loop */
+ __IOM uint32_t VTBLETIMING_TGL; /**< Viterbi BLE timing stamp control */
+ __IM uint32_t BREST_TGL; /**< Baudrate Estimate */
+ __IOM uint32_t AUTOCG_TGL; /**< Automatic clock gating */
+ __IOM uint32_t CGCLKSTOP_TGL; /**< Automatic clock gating */
+ __IM uint32_t POE_TGL; /**< Phase Offset Estimate */
+ __IOM uint32_t DIRECTMODE_TGL; /**< Direct Mode Control */
+ __IOM uint32_t LONGRANGE_TGL; /**< BLE Long Range */
+ __IOM uint32_t LONGRANGE1_TGL; /**< BLE Long Range Set1 */
+ __IOM uint32_t LONGRANGE2_TGL; /**< BLE Long Range Set2 */
+ __IOM uint32_t LONGRANGE3_TGL; /**< BLE Long Range Set3 */
+ __IOM uint32_t LONGRANGE4_TGL; /**< BLE Long Range Set4 */
+ __IOM uint32_t LONGRANGE5_TGL; /**< BLE Long Range Set5 */
+ __IOM uint32_t LONGRANGE6_TGL; /**< BLE Long Range Set6 */
+ __IOM uint32_t LRFRC_TGL; /**< BLE Long Range FRC interface */
+ __IOM uint32_t COH0_TGL; /**< Coherent demodulator control signals */
+ __IOM uint32_t COH1_TGL; /**< Coherent demodulator control signals */
+ __IOM uint32_t COH2_TGL; /**< Coherent demodulator control signals */
+ __IOM uint32_t COH3_TGL; /**< Coherent demodulator control signals */
+ __IOM uint32_t CMD_TGL; /**< Command register */
+ uint32_t RESERVED38[2U]; /**< Reserved for future use */
+ __IOM uint32_t SYNCPROPERTIES_TGL; /**< Sync word properties */
+ __IOM uint32_t DIGIGAINCTRL_TGL; /**< Digital Gain Control */
+ __IOM uint32_t PRSCTRL_TGL; /**< Mux control for PRS outputs */
+ uint32_t RESERVED39[1U]; /**< Reserved for future use */
+ __IOM uint32_t REALTIMCFE_TGL; /**< Real time Cost Function Engine CTRL */
+ __IOM uint32_t ETSCTRL_TGL; /**< Early Time Stamp Control */
+ __IOM uint32_t ETSTIM_TGL; /**< Early Time Stamp Timing */
+ __IOM uint32_t ANTSWCTRL_TGL; /**< Antenna Switch Control */
+ __IOM uint32_t ANTSWCTRL1_TGL; /**< Antenna Switch Control 1 */
+ __IOM uint32_t ANTSWSTART_TGL; /**< Antenna Switch Start */
+ __IOM uint32_t ANTSWEND_TGL; /**< Antenna Switch End */
+ __IOM uint32_t TRECPMPATT_TGL; /**< TRECS Preamble pattern */
+ __IOM uint32_t TRECPMDET_TGL; /**< TRECS preamble Detection CTRL */
+ __IOM uint32_t TRECSCFG_TGL; /**< TRECS configuration */
+ __IOM uint32_t CFGANTPATT_TGL; /**< Configure Antenna Pattern */
+ __IOM uint32_t COCURRMODE_TGL; /**< CONCURRENT MODE */
+ __IOM uint32_t CHFCOE00_TGL; /**< CHF COE. Set0 group0 */
+ __IOM uint32_t CHFCOE01_TGL; /**< CHF COE. Set0 group1 */
+ __IOM uint32_t CHFCOE02_TGL; /**< CHF COE. Set0 group2 */
+ __IOM uint32_t CHFCOE03_TGL; /**< CHF COE. Set0 group3 */
+ __IOM uint32_t CHFCOE04_TGL; /**< CHF COE. Set0 group4 */
+ __IOM uint32_t CHFCOE05_TGL; /**< CHF COE. Set0 group5 */
+ __IOM uint32_t CHFCOE06_TGL; /**< CHF COE. Set0 group6 */
+ __IOM uint32_t CHFCOE10_TGL; /**< CHF COE. Set1 group0 */
+ __IOM uint32_t CHFCOE11_TGL; /**< CHF COE. Set1 group1 */
+ __IOM uint32_t CHFCOE12_TGL; /**< CHF COE. Set1 group2 */
+ __IOM uint32_t CHFCOE13_TGL; /**< CHF COE. Set1 group3 */
+ __IOM uint32_t CHFCOE14_TGL; /**< CHF COE. Set1 group4 */
+ __IOM uint32_t CHFCOE15_TGL; /**< CHF COE. Set1 group5 */
+ __IOM uint32_t CHFCOE16_TGL; /**< CHF COE. Set1 group6 */
+ __IOM uint32_t CHFCTRL_TGL; /**< CHF control */
+ __IOM uint32_t CHFLATENCYCTRL_TGL; /**< CHF Latency Control */
+ __IOM uint32_t FRMSCHTIME_TGL; /**< FRAM SCH TIME-OUT length */
+ __IOM uint32_t PREFILTCOEFF_TGL; /**< Preamble Filter Coefficients */
+ __IOM uint32_t RXRESTART_TGL; /**< Collision restart control */
+ __IOM uint32_t SQ_TGL; /**< Preamble Sense Mode */
+ __IOM uint32_t SQEXT_TGL; /**< Preamble Sense Mode EXT */
+ __IOM uint32_t SQI_TGL; /**< Signal quality indicator */
+ __IOM uint32_t ANTDIVCTRL_TGL; /**< Antenna Diversity Mode Control Register */
+ __IOM uint32_t ANTDIVFW_TGL; /**< PHASE DEMOD FW mode */
+ __IOM uint32_t PHDMODANTDIV_TGL; /**< PHASE DEMOD ANTENNA DIVSERSITY */
+ __IOM uint32_t PHANTDECSION_TGL; /**< PHASE DEMOD ANT-DIV Decision */
+ __IOM uint32_t PHDMODCTRL_TGL; /**< PHASE DEMOD CTRL */
+ __IOM uint32_t SICTRL0_TGL; /**< Signal Identifier CTRL0 */
+ __IOM uint32_t SICTRL1_TGL; /**< Signal Identifier CTRL1 */
+ __IM uint32_t SISTATUS_TGL; /**< Signal Identifier Status */
+ __IOM uint32_t CFGANTPATTEXT_TGL; /**< Configure Antenna Pattern */
+ uint32_t RESERVED40[1U]; /**< Reserved for future use */
+ __IOM uint32_t SICTRL2_TGL; /**< Signal Identifier CTRL2 */
+ __IOM uint32_t CHFSWCTRL_TGL; /**< Channel Filter Switch Time */
+ uint32_t RESERVED41[1U]; /**< Reserved for future use */
+ __IOM uint32_t IRCAL_TGL; /**< IRCAL control signals */
+ __IM uint32_t IRCALCOEF_TGL; /**< IRCAL COEF values */
+ MODEM_IRCALCOEFWR_TypeDef IRCALCOEFWR_TGL[2U]; /**< IRCAL COEFS WR per antenna */
+ __IOM uint32_t ADCTRL1_TGL; /**< ADCTRL1 */
+ __IOM uint32_t ADCTRL2_TGL; /**< ADCTRL2 */
+ __IM uint32_t ADQUAL0_TGL; /**< ADQUAL0 */
+ __IM uint32_t ADQUAL1_TGL; /**< ADQUAL1 */
+ __IM uint32_t ADQUAL2_TGL; /**< ADQUAL2 */
+ __IM uint32_t ADQUAL3_TGL; /**< ADQUAL3 */
+ __IOM uint32_t ADQUAL4_TGL; /**< ADQUAL4 */
+ __IOM uint32_t ADQUAL5_TGL; /**< ADQUAL5 */
+ __IOM uint32_t ADQUAL6_TGL; /**< ADQUAL6 */
+ __IOM uint32_t ADQUAL7_TGL; /**< ADQUAL7 */
+ __IOM uint32_t ADQUAL8_TGL; /**< ADQUAL8 */
+ __IM uint32_t ADQUAL9_TGL; /**< ADQUAL9 */
+ __IM uint32_t ADQUAL10_TGL; /**< ADQUAL10 */
+ __IOM uint32_t ADFSM0_TGL; /**< ADFSM0 */
+ __IOM uint32_t ADFSM1_TGL; /**< ADFSM1 */
+ __IOM uint32_t ADFSM2_TGL; /**< ADFSM2 */
+ __IOM uint32_t ADFSM3_TGL; /**< ADFSM3 */
+ __IOM uint32_t ADFSM4_TGL; /**< ADFSM4 */
+ __IOM uint32_t ADFSM5_TGL; /**< ADFSM5 */
+ __IOM uint32_t ADFSM6_TGL; /**< ADFSM6 */
+ __IOM uint32_t ADFSM7_TGL; /**< ADFSM7 */
+ __IOM uint32_t ADFSM8_TGL; /**< ADFSM8 */
+ __IOM uint32_t ADFSM9_TGL; /**< ADFSM9 */
+ __IOM uint32_t ADFSM10_TGL; /**< ADFSM10 */
+ __IOM uint32_t ADFSM11_TGL; /**< ADFSM11 */
+ __IOM uint32_t ADFSM12_TGL; /**< ADFSM12 */
+ __IOM uint32_t ADFSM13_TGL; /**< ADFSM13 */
+ __IOM uint32_t ADFSM14_TGL; /**< ADFSM14 */
+ __IOM uint32_t ADFSM15_TGL; /**< ADFSM15 */
+ __IOM uint32_t ADFSM16_TGL; /**< ADFSM16 */
+ __IOM uint32_t ADFSM17_TGL; /**< ADFSM17 */
+ __IOM uint32_t ADFSM18_TGL; /**< ADFSM18 */
+ __IOM uint32_t ADFSM19_TGL; /**< ADFSM19 */
+ __IOM uint32_t ADFSM20_TGL; /**< ADFSM20 */
+ __IOM uint32_t ADFSM21_TGL; /**< ADFSM21 */
+ __IM uint32_t ADFSM22_TGL; /**< ADFSM22 */
+ __IOM uint32_t ADFSM23_TGL; /**< ADFSM23 */
+ __IOM uint32_t ADFSM24_TGL; /**< ADFSM24 */
+ __IOM uint32_t ADFSM25_TGL; /**< ADFSM25 */
+ __IOM uint32_t ADFSM26_TGL; /**< ADFSM26 */
+ __IOM uint32_t ADFSM27_TGL; /**< ADFSM27 */
+ __IOM uint32_t ADFSM28_TGL; /**< ADFSM28 */
+ __IOM uint32_t ADFSM29_TGL; /**< ADFSM29 */
+ __IOM uint32_t ADFSM30_TGL; /**< ADFSM30 */
+ __IOM uint32_t ADPC1_TGL; /**< ADPC1 */
+ __IOM uint32_t ADPC2_TGL; /**< ADPC2 */
+ __IOM uint32_t ADPC3_TGL; /**< ADPC3 */
+ __IOM uint32_t ADPC4_TGL; /**< ADPC4 */
+ __IOM uint32_t ADPC5_TGL; /**< ADPC5 */
+ __IOM uint32_t ADPC6_TGL; /**< ADPC6 */
+ __IOM uint32_t ADPC7_TGL; /**< ADPC7 */
+ __IOM uint32_t ADPC8_TGL; /**< ADPC8 */
+ __IOM uint32_t ADPC9_TGL; /**< ADPC9 */
+ __IOM uint32_t ADPC10_TGL; /**< ADPC10 */
+ uint32_t RESERVED42[6U]; /**< Reserved for future use */
+ uint32_t RESERVED43[1U]; /**< Reserved for future use */
+ uint32_t RESERVED44[15U]; /**< Reserved for future use */
+ __IOM uint32_t HADMCTRL0_TGL; /**< HADM Control */
+ __IOM uint32_t HADMCTRL1_TGL; /**< HADM Control 1 */
+ __IM uint32_t HADMSTATUS0_TGL; /**< HADM Status */
+ __IM uint32_t HADMSTATUS1_TGL; /**< HADM Status 1 */
+ __IM uint32_t HADMSTATUS2_TGL; /**< HADM Status 2 */
+ __IM uint32_t HADMSTATUS3_TGL; /**< HADM Status 3 */
+ __IM uint32_t HADMSTATUS4_TGL; /**< HADM Status 4 */
+ __IM uint32_t HADMSTATUS5_TGL; /**< HADM Status 5 */
+ __IM uint32_t HADMSTATUS6_TGL; /**< HADM Status 6 */
+ uint32_t RESERVED45[3U]; /**< Reserved for future use */
+ __IOM uint32_t SRC2NCOCTRL_TGL; /**< SRC2 NCO CTRL */
+ uint32_t RESERVED46[7U]; /**< Reserved for future use */
+ __IOM uint32_t SPARE_TGL; /**< Spare register */
+} MODEM_TypeDef;
+/** @} End of group EFR32MG24_MODEM */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_MODEM
+ * @{
+ * @defgroup EFR32MG24_MODEM_BitFields MODEM Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for MODEM IPVERSION */
+#define _MODEM_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for MODEM_IPVERSION */
+#define _MODEM_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for MODEM_IPVERSION */
+#define _MODEM_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MODEM_IPVERSION */
+#define _MODEM_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for MODEM_IPVERSION */
+#define _MODEM_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for MODEM_IPVERSION */
+#define MODEM_IPVERSION_IPVERSION_DEFAULT (_MODEM_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_IPVERSION */
+
+/* Bit fields for MODEM EN */
+#define _MODEM_EN_RESETVALUE 0x00000000UL /**< Default value for MODEM_EN */
+#define _MODEM_EN_MASK 0x00000001UL /**< Mask for MODEM_EN */
+#define MODEM_EN_EN (0x1UL << 0) /**< Enable peripheral clock to this module */
+#define _MODEM_EN_EN_SHIFT 0 /**< Shift value for MODEM_EN */
+#define _MODEM_EN_EN_MASK 0x1UL /**< Bit mask for MODEM_EN */
+#define _MODEM_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_EN */
+#define MODEM_EN_EN_DEFAULT (_MODEM_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_EN */
+
+/* Bit fields for MODEM IF */
+#define _MODEM_IF_RESETVALUE 0x00000000UL /**< Default value for MODEM_IF */
+#define _MODEM_IF_MASK 0x3FFFFFFFUL /**< Mask for MODEM_IF */
+#define MODEM_IF_TXFRAMESENT (0x1UL << 0) /**< Frame sent */
+#define _MODEM_IF_TXFRAMESENT_SHIFT 0 /**< Shift value for MODEM_TXFRAMESENT */
+#define _MODEM_IF_TXFRAMESENT_MASK 0x1UL /**< Bit mask for MODEM_TXFRAMESENT */
+#define _MODEM_IF_TXFRAMESENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */
+#define MODEM_IF_TXFRAMESENT_DEFAULT (_MODEM_IF_TXFRAMESENT_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_IF */
+#define MODEM_IF_TXSYNCSENT (0x1UL << 1) /**< Sync word sent */
+#define _MODEM_IF_TXSYNCSENT_SHIFT 1 /**< Shift value for MODEM_TXSYNCSENT */
+#define _MODEM_IF_TXSYNCSENT_MASK 0x2UL /**< Bit mask for MODEM_TXSYNCSENT */
+#define _MODEM_IF_TXSYNCSENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */
+#define MODEM_IF_TXSYNCSENT_DEFAULT (_MODEM_IF_TXSYNCSENT_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_IF */
+#define MODEM_IF_TXPRESENT (0x1UL << 2) /**< Preamble sent */
+#define _MODEM_IF_TXPRESENT_SHIFT 2 /**< Shift value for MODEM_TXPRESENT */
+#define _MODEM_IF_TXPRESENT_MASK 0x4UL /**< Bit mask for MODEM_TXPRESENT */
+#define _MODEM_IF_TXPRESENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */
+#define MODEM_IF_TXPRESENT_DEFAULT (_MODEM_IF_TXPRESENT_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_IF */
+#define MODEM_IF_TXRAMPDONE (0x1UL << 3) /**< Mod ramper idle */
+#define _MODEM_IF_TXRAMPDONE_SHIFT 3 /**< Shift value for MODEM_TXRAMPDONE */
+#define _MODEM_IF_TXRAMPDONE_MASK 0x8UL /**< Bit mask for MODEM_TXRAMPDONE */
+#define _MODEM_IF_TXRAMPDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */
+#define MODEM_IF_TXRAMPDONE_DEFAULT (_MODEM_IF_TXRAMPDONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_IF */
+#define MODEM_IF_LDTNOARR (0x1UL << 4) /**< No signal Detected in LDT */
+#define _MODEM_IF_LDTNOARR_SHIFT 4 /**< Shift value for MODEM_LDTNOARR */
+#define _MODEM_IF_LDTNOARR_MASK 0x10UL /**< Bit mask for MODEM_LDTNOARR */
+#define _MODEM_IF_LDTNOARR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */
+#define MODEM_IF_LDTNOARR_DEFAULT (_MODEM_IF_LDTNOARR_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_IF */
+#define MODEM_IF_PHDSADET (0x1UL << 5) /**< PHASE DSA DETECT */
+#define _MODEM_IF_PHDSADET_SHIFT 5 /**< Shift value for MODEM_PHDSADET */
+#define _MODEM_IF_PHDSADET_MASK 0x20UL /**< Bit mask for MODEM_PHDSADET */
+#define _MODEM_IF_PHDSADET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */
+#define MODEM_IF_PHDSADET_DEFAULT (_MODEM_IF_PHDSADET_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_IF */
+#define MODEM_IF_PHYUNCODEDET (0x1UL << 6) /**< CONCURRENT UNCODED PHY DET */
+#define _MODEM_IF_PHYUNCODEDET_SHIFT 6 /**< Shift value for MODEM_PHYUNCODEDET */
+#define _MODEM_IF_PHYUNCODEDET_MASK 0x40UL /**< Bit mask for MODEM_PHYUNCODEDET */
+#define _MODEM_IF_PHYUNCODEDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */
+#define MODEM_IF_PHYUNCODEDET_DEFAULT (_MODEM_IF_PHYUNCODEDET_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_IF */
+#define MODEM_IF_PHYCODEDET (0x1UL << 7) /**< CONCURRENT CODED PHY DET */
+#define _MODEM_IF_PHYCODEDET_SHIFT 7 /**< Shift value for MODEM_PHYCODEDET */
+#define _MODEM_IF_PHYCODEDET_MASK 0x80UL /**< Bit mask for MODEM_PHYCODEDET */
+#define _MODEM_IF_PHYCODEDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */
+#define MODEM_IF_PHYCODEDET_DEFAULT (_MODEM_IF_PHYCODEDET_DEFAULT << 7) /**< Shifted mode DEFAULT for MODEM_IF */
+#define MODEM_IF_RXTIMDET (0x1UL << 8) /**< Timing detected */
+#define _MODEM_IF_RXTIMDET_SHIFT 8 /**< Shift value for MODEM_RXTIMDET */
+#define _MODEM_IF_RXTIMDET_MASK 0x100UL /**< Bit mask for MODEM_RXTIMDET */
+#define _MODEM_IF_RXTIMDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */
+#define MODEM_IF_RXTIMDET_DEFAULT (_MODEM_IF_RXTIMDET_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_IF */
+#define MODEM_IF_RXPREDET (0x1UL << 9) /**< Preamble detected */
+#define _MODEM_IF_RXPREDET_SHIFT 9 /**< Shift value for MODEM_RXPREDET */
+#define _MODEM_IF_RXPREDET_MASK 0x200UL /**< Bit mask for MODEM_RXPREDET */
+#define _MODEM_IF_RXPREDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */
+#define MODEM_IF_RXPREDET_DEFAULT (_MODEM_IF_RXPREDET_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_IF */
+#define MODEM_IF_RXFRAMEDET0 (0x1UL << 10) /**< Frame with sync-word 0 detected */
+#define _MODEM_IF_RXFRAMEDET0_SHIFT 10 /**< Shift value for MODEM_RXFRAMEDET0 */
+#define _MODEM_IF_RXFRAMEDET0_MASK 0x400UL /**< Bit mask for MODEM_RXFRAMEDET0 */
+#define _MODEM_IF_RXFRAMEDET0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */
+#define MODEM_IF_RXFRAMEDET0_DEFAULT (_MODEM_IF_RXFRAMEDET0_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_IF */
+#define MODEM_IF_RXFRAMEDET1 (0x1UL << 11) /**< Frame with sync-word 1 detected */
+#define _MODEM_IF_RXFRAMEDET1_SHIFT 11 /**< Shift value for MODEM_RXFRAMEDET1 */
+#define _MODEM_IF_RXFRAMEDET1_MASK 0x800UL /**< Bit mask for MODEM_RXFRAMEDET1 */
+#define _MODEM_IF_RXFRAMEDET1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */
+#define MODEM_IF_RXFRAMEDET1_DEFAULT (_MODEM_IF_RXFRAMEDET1_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_IF */
+#define MODEM_IF_RXTIMLOST (0x1UL << 12) /**< Timing lost */
+#define _MODEM_IF_RXTIMLOST_SHIFT 12 /**< Shift value for MODEM_RXTIMLOST */
+#define _MODEM_IF_RXTIMLOST_MASK 0x1000UL /**< Bit mask for MODEM_RXTIMLOST */
+#define _MODEM_IF_RXTIMLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */
+#define MODEM_IF_RXTIMLOST_DEFAULT (_MODEM_IF_RXTIMLOST_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_IF */
+#define MODEM_IF_RXPRELOST (0x1UL << 13) /**< Preamble lost */
+#define _MODEM_IF_RXPRELOST_SHIFT 13 /**< Shift value for MODEM_RXPRELOST */
+#define _MODEM_IF_RXPRELOST_MASK 0x2000UL /**< Bit mask for MODEM_RXPRELOST */
+#define _MODEM_IF_RXPRELOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */
+#define MODEM_IF_RXPRELOST_DEFAULT (_MODEM_IF_RXPRELOST_DEFAULT << 13) /**< Shifted mode DEFAULT for MODEM_IF */
+#define MODEM_IF_RXFRAMEDETOF (0x1UL << 14) /**< Frame detection overflow */
+#define _MODEM_IF_RXFRAMEDETOF_SHIFT 14 /**< Shift value for MODEM_RXFRAMEDETOF */
+#define _MODEM_IF_RXFRAMEDETOF_MASK 0x4000UL /**< Bit mask for MODEM_RXFRAMEDETOF */
+#define _MODEM_IF_RXFRAMEDETOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */
+#define MODEM_IF_RXFRAMEDETOF_DEFAULT (_MODEM_IF_RXFRAMEDETOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_IF */
+#define MODEM_IF_RXTIMNF (0x1UL << 15) /**< Timing not found */
+#define _MODEM_IF_RXTIMNF_SHIFT 15 /**< Shift value for MODEM_RXTIMNF */
+#define _MODEM_IF_RXTIMNF_MASK 0x8000UL /**< Bit mask for MODEM_RXTIMNF */
+#define _MODEM_IF_RXTIMNF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */
+#define MODEM_IF_RXTIMNF_DEFAULT (_MODEM_IF_RXTIMNF_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_IF */
+#define MODEM_IF_FRCTIMOUT (0x1UL << 16) /**< DEMOD-FRC req/ack timeout */
+#define _MODEM_IF_FRCTIMOUT_SHIFT 16 /**< Shift value for MODEM_FRCTIMOUT */
+#define _MODEM_IF_FRCTIMOUT_MASK 0x10000UL /**< Bit mask for MODEM_FRCTIMOUT */
+#define _MODEM_IF_FRCTIMOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */
+#define MODEM_IF_FRCTIMOUT_DEFAULT (_MODEM_IF_FRCTIMOUT_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_IF */
+#define MODEM_IF_ETS (0x1UL << 17) /**< Early Time Stamp detect */
+#define _MODEM_IF_ETS_SHIFT 17 /**< Shift value for MODEM_ETS */
+#define _MODEM_IF_ETS_MASK 0x20000UL /**< Bit mask for MODEM_ETS */
+#define _MODEM_IF_ETS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */
+#define MODEM_IF_ETS_DEFAULT (_MODEM_IF_ETS_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_IF */
+#define MODEM_IF_CFGANTPATTRD (0x1UL << 18) /**< cfg */
+#define _MODEM_IF_CFGANTPATTRD_SHIFT 18 /**< Shift value for MODEM_CFGANTPATTRD */
+#define _MODEM_IF_CFGANTPATTRD_MASK 0x40000UL /**< Bit mask for MODEM_CFGANTPATTRD */
+#define _MODEM_IF_CFGANTPATTRD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */
+#define MODEM_IF_CFGANTPATTRD_DEFAULT (_MODEM_IF_CFGANTPATTRD_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_IF */
+#define MODEM_IF_RXRESTARTRSSIMAPRE (0x1UL << 19) /**< RX restart using RSSI MA filter */
+#define _MODEM_IF_RXRESTARTRSSIMAPRE_SHIFT 19 /**< Shift value for MODEM_RXRESTARTRSSIMAPRE */
+#define _MODEM_IF_RXRESTARTRSSIMAPRE_MASK 0x80000UL /**< Bit mask for MODEM_RXRESTARTRSSIMAPRE */
+#define _MODEM_IF_RXRESTARTRSSIMAPRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */
+#define MODEM_IF_RXRESTARTRSSIMAPRE_DEFAULT (_MODEM_IF_RXRESTARTRSSIMAPRE_DEFAULT << 19) /**< Shifted mode DEFAULT for MODEM_IF */
+#define MODEM_IF_RXRESTARTRSSIMASYNC (0x1UL << 20) /**< RX restart using RSSI MA filter */
+#define _MODEM_IF_RXRESTARTRSSIMASYNC_SHIFT 20 /**< Shift value for MODEM_RXRESTARTRSSIMASYNC */
+#define _MODEM_IF_RXRESTARTRSSIMASYNC_MASK 0x100000UL /**< Bit mask for MODEM_RXRESTARTRSSIMASYNC */
+#define _MODEM_IF_RXRESTARTRSSIMASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */
+#define MODEM_IF_RXRESTARTRSSIMASYNC_DEFAULT (_MODEM_IF_RXRESTARTRSSIMASYNC_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_IF */
+#define MODEM_IF_SQDET (0x1UL << 21) /**< SQ Detect */
+#define _MODEM_IF_SQDET_SHIFT 21 /**< Shift value for MODEM_SQDET */
+#define _MODEM_IF_SQDET_MASK 0x200000UL /**< Bit mask for MODEM_SQDET */
+#define _MODEM_IF_SQDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */
+#define MODEM_IF_SQDET_DEFAULT (_MODEM_IF_SQDET_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_IF */
+#define MODEM_IF_SQNOTDET (0x1UL << 22) /**< SQ Not Detect */
+#define _MODEM_IF_SQNOTDET_SHIFT 22 /**< Shift value for MODEM_SQNOTDET */
+#define _MODEM_IF_SQNOTDET_MASK 0x400000UL /**< Bit mask for MODEM_SQNOTDET */
+#define _MODEM_IF_SQNOTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */
+#define MODEM_IF_SQNOTDET_DEFAULT (_MODEM_IF_SQNOTDET_DEFAULT << 22) /**< Shifted mode DEFAULT for MODEM_IF */
+#define MODEM_IF_ANTDIVRDY (0x1UL << 23) /**< RSSI and CORR data Ready */
+#define _MODEM_IF_ANTDIVRDY_SHIFT 23 /**< Shift value for MODEM_ANTDIVRDY */
+#define _MODEM_IF_ANTDIVRDY_MASK 0x800000UL /**< Bit mask for MODEM_ANTDIVRDY */
+#define _MODEM_IF_ANTDIVRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */
+#define MODEM_IF_ANTDIVRDY_DEFAULT (_MODEM_IF_ANTDIVRDY_DEFAULT << 23) /**< Shifted mode DEFAULT for MODEM_IF */
+#define MODEM_IF_SOFTRESETDONE (0x1UL << 24) /**< Soft reset done */
+#define _MODEM_IF_SOFTRESETDONE_SHIFT 24 /**< Shift value for MODEM_SOFTRESETDONE */
+#define _MODEM_IF_SOFTRESETDONE_MASK 0x1000000UL /**< Bit mask for MODEM_SOFTRESETDONE */
+#define _MODEM_IF_SOFTRESETDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */
+#define MODEM_IF_SOFTRESETDONE_DEFAULT (_MODEM_IF_SOFTRESETDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_IF */
+#define MODEM_IF_SQPRENOTDET (0x1UL << 25) /**< SQ Not Detect */
+#define _MODEM_IF_SQPRENOTDET_SHIFT 25 /**< Shift value for MODEM_SQPRENOTDET */
+#define _MODEM_IF_SQPRENOTDET_MASK 0x2000000UL /**< Bit mask for MODEM_SQPRENOTDET */
+#define _MODEM_IF_SQPRENOTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */
+#define MODEM_IF_SQPRENOTDET_DEFAULT (_MODEM_IF_SQPRENOTDET_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_IF */
+#define MODEM_IF_SQFRAMENOTDET (0x1UL << 26) /**< SQ Not Detect */
+#define _MODEM_IF_SQFRAMENOTDET_SHIFT 26 /**< Shift value for MODEM_SQFRAMENOTDET */
+#define _MODEM_IF_SQFRAMENOTDET_MASK 0x4000000UL /**< Bit mask for MODEM_SQFRAMENOTDET */
+#define _MODEM_IF_SQFRAMENOTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */
+#define MODEM_IF_SQFRAMENOTDET_DEFAULT (_MODEM_IF_SQFRAMENOTDET_DEFAULT << 26) /**< Shifted mode DEFAULT for MODEM_IF */
+#define MODEM_IF_SQAFCOUTOFBAND (0x1UL << 27) /**< SQ AFC out of band */
+#define _MODEM_IF_SQAFCOUTOFBAND_SHIFT 27 /**< Shift value for MODEM_SQAFCOUTOFBAND */
+#define _MODEM_IF_SQAFCOUTOFBAND_MASK 0x8000000UL /**< Bit mask for MODEM_SQAFCOUTOFBAND */
+#define _MODEM_IF_SQAFCOUTOFBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */
+#define MODEM_IF_SQAFCOUTOFBAND_DEFAULT (_MODEM_IF_SQAFCOUTOFBAND_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_IF */
+#define MODEM_IF_SIDET (0x1UL << 28) /**< Signal identified */
+#define _MODEM_IF_SIDET_SHIFT 28 /**< Shift value for MODEM_SIDET */
+#define _MODEM_IF_SIDET_MASK 0x10000000UL /**< Bit mask for MODEM_SIDET */
+#define _MODEM_IF_SIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */
+#define MODEM_IF_SIDET_DEFAULT (_MODEM_IF_SIDET_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_IF */
+#define MODEM_IF_SIRESET (0x1UL << 29) /**< Signal identifier reset */
+#define _MODEM_IF_SIRESET_SHIFT 29 /**< Shift value for MODEM_SIRESET */
+#define _MODEM_IF_SIRESET_MASK 0x20000000UL /**< Bit mask for MODEM_SIRESET */
+#define _MODEM_IF_SIRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IF */
+#define MODEM_IF_SIRESET_DEFAULT (_MODEM_IF_SIRESET_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_IF */
+
+/* Bit fields for MODEM IEN */
+#define _MODEM_IEN_RESETVALUE 0x00000000UL /**< Default value for MODEM_IEN */
+#define _MODEM_IEN_MASK 0x3FFFFFFFUL /**< Mask for MODEM_IEN */
+#define MODEM_IEN_TXFRAMESENT (0x1UL << 0) /**< Frame sent */
+#define _MODEM_IEN_TXFRAMESENT_SHIFT 0 /**< Shift value for MODEM_TXFRAMESENT */
+#define _MODEM_IEN_TXFRAMESENT_MASK 0x1UL /**< Bit mask for MODEM_TXFRAMESENT */
+#define _MODEM_IEN_TXFRAMESENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_TXFRAMESENT_DEFAULT (_MODEM_IEN_TXFRAMESENT_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_TXSYNCSENT (0x1UL << 1) /**< Sync word sent */
+#define _MODEM_IEN_TXSYNCSENT_SHIFT 1 /**< Shift value for MODEM_TXSYNCSENT */
+#define _MODEM_IEN_TXSYNCSENT_MASK 0x2UL /**< Bit mask for MODEM_TXSYNCSENT */
+#define _MODEM_IEN_TXSYNCSENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_TXSYNCSENT_DEFAULT (_MODEM_IEN_TXSYNCSENT_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_TXPRESENT (0x1UL << 2) /**< Preamble sent */
+#define _MODEM_IEN_TXPRESENT_SHIFT 2 /**< Shift value for MODEM_TXPRESENT */
+#define _MODEM_IEN_TXPRESENT_MASK 0x4UL /**< Bit mask for MODEM_TXPRESENT */
+#define _MODEM_IEN_TXPRESENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_TXPRESENT_DEFAULT (_MODEM_IEN_TXPRESENT_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_TXRAMPDONE (0x1UL << 3) /**< Mod ramper idle */
+#define _MODEM_IEN_TXRAMPDONE_SHIFT 3 /**< Shift value for MODEM_TXRAMPDONE */
+#define _MODEM_IEN_TXRAMPDONE_MASK 0x8UL /**< Bit mask for MODEM_TXRAMPDONE */
+#define _MODEM_IEN_TXRAMPDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_TXRAMPDONE_DEFAULT (_MODEM_IEN_TXRAMPDONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_LDTNOARR (0x1UL << 4) /**< No signal Detected in LDT */
+#define _MODEM_IEN_LDTNOARR_SHIFT 4 /**< Shift value for MODEM_LDTNOARR */
+#define _MODEM_IEN_LDTNOARR_MASK 0x10UL /**< Bit mask for MODEM_LDTNOARR */
+#define _MODEM_IEN_LDTNOARR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_LDTNOARR_DEFAULT (_MODEM_IEN_LDTNOARR_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_PHDSADET (0x1UL << 5) /**< PHASE DSA DETECT */
+#define _MODEM_IEN_PHDSADET_SHIFT 5 /**< Shift value for MODEM_PHDSADET */
+#define _MODEM_IEN_PHDSADET_MASK 0x20UL /**< Bit mask for MODEM_PHDSADET */
+#define _MODEM_IEN_PHDSADET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_PHDSADET_DEFAULT (_MODEM_IEN_PHDSADET_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_PHYUNCODEDET (0x1UL << 6) /**< CONCURRENT UNCODED PHY DET */
+#define _MODEM_IEN_PHYUNCODEDET_SHIFT 6 /**< Shift value for MODEM_PHYUNCODEDET */
+#define _MODEM_IEN_PHYUNCODEDET_MASK 0x40UL /**< Bit mask for MODEM_PHYUNCODEDET */
+#define _MODEM_IEN_PHYUNCODEDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_PHYUNCODEDET_DEFAULT (_MODEM_IEN_PHYUNCODEDET_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_PHYCODEDET (0x1UL << 7) /**< CONCURRENT CODED PHY DET */
+#define _MODEM_IEN_PHYCODEDET_SHIFT 7 /**< Shift value for MODEM_PHYCODEDET */
+#define _MODEM_IEN_PHYCODEDET_MASK 0x80UL /**< Bit mask for MODEM_PHYCODEDET */
+#define _MODEM_IEN_PHYCODEDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_PHYCODEDET_DEFAULT (_MODEM_IEN_PHYCODEDET_DEFAULT << 7) /**< Shifted mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_RXTIMDET (0x1UL << 8) /**< Timing detected */
+#define _MODEM_IEN_RXTIMDET_SHIFT 8 /**< Shift value for MODEM_RXTIMDET */
+#define _MODEM_IEN_RXTIMDET_MASK 0x100UL /**< Bit mask for MODEM_RXTIMDET */
+#define _MODEM_IEN_RXTIMDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_RXTIMDET_DEFAULT (_MODEM_IEN_RXTIMDET_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_RXPREDET (0x1UL << 9) /**< Preamble detected */
+#define _MODEM_IEN_RXPREDET_SHIFT 9 /**< Shift value for MODEM_RXPREDET */
+#define _MODEM_IEN_RXPREDET_MASK 0x200UL /**< Bit mask for MODEM_RXPREDET */
+#define _MODEM_IEN_RXPREDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_RXPREDET_DEFAULT (_MODEM_IEN_RXPREDET_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_RXFRAMEDET0 (0x1UL << 10) /**< Frame with sync-word 0 detected */
+#define _MODEM_IEN_RXFRAMEDET0_SHIFT 10 /**< Shift value for MODEM_RXFRAMEDET0 */
+#define _MODEM_IEN_RXFRAMEDET0_MASK 0x400UL /**< Bit mask for MODEM_RXFRAMEDET0 */
+#define _MODEM_IEN_RXFRAMEDET0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_RXFRAMEDET0_DEFAULT (_MODEM_IEN_RXFRAMEDET0_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_RXFRAMEDET1 (0x1UL << 11) /**< Frame with sync-word 1 detected */
+#define _MODEM_IEN_RXFRAMEDET1_SHIFT 11 /**< Shift value for MODEM_RXFRAMEDET1 */
+#define _MODEM_IEN_RXFRAMEDET1_MASK 0x800UL /**< Bit mask for MODEM_RXFRAMEDET1 */
+#define _MODEM_IEN_RXFRAMEDET1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_RXFRAMEDET1_DEFAULT (_MODEM_IEN_RXFRAMEDET1_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_RXTIMLOST (0x1UL << 12) /**< Timing lost */
+#define _MODEM_IEN_RXTIMLOST_SHIFT 12 /**< Shift value for MODEM_RXTIMLOST */
+#define _MODEM_IEN_RXTIMLOST_MASK 0x1000UL /**< Bit mask for MODEM_RXTIMLOST */
+#define _MODEM_IEN_RXTIMLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_RXTIMLOST_DEFAULT (_MODEM_IEN_RXTIMLOST_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_RXPRELOST (0x1UL << 13) /**< Preamble lost */
+#define _MODEM_IEN_RXPRELOST_SHIFT 13 /**< Shift value for MODEM_RXPRELOST */
+#define _MODEM_IEN_RXPRELOST_MASK 0x2000UL /**< Bit mask for MODEM_RXPRELOST */
+#define _MODEM_IEN_RXPRELOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_RXPRELOST_DEFAULT (_MODEM_IEN_RXPRELOST_DEFAULT << 13) /**< Shifted mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_RXFRAMEDETOF (0x1UL << 14) /**< Frame detection overflow */
+#define _MODEM_IEN_RXFRAMEDETOF_SHIFT 14 /**< Shift value for MODEM_RXFRAMEDETOF */
+#define _MODEM_IEN_RXFRAMEDETOF_MASK 0x4000UL /**< Bit mask for MODEM_RXFRAMEDETOF */
+#define _MODEM_IEN_RXFRAMEDETOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_RXFRAMEDETOF_DEFAULT (_MODEM_IEN_RXFRAMEDETOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_RXTIMNF (0x1UL << 15) /**< Timing not found */
+#define _MODEM_IEN_RXTIMNF_SHIFT 15 /**< Shift value for MODEM_RXTIMNF */
+#define _MODEM_IEN_RXTIMNF_MASK 0x8000UL /**< Bit mask for MODEM_RXTIMNF */
+#define _MODEM_IEN_RXTIMNF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_RXTIMNF_DEFAULT (_MODEM_IEN_RXTIMNF_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_FRCTIMOUT (0x1UL << 16) /**< DEMOD-FRC req/ack timeout */
+#define _MODEM_IEN_FRCTIMOUT_SHIFT 16 /**< Shift value for MODEM_FRCTIMOUT */
+#define _MODEM_IEN_FRCTIMOUT_MASK 0x10000UL /**< Bit mask for MODEM_FRCTIMOUT */
+#define _MODEM_IEN_FRCTIMOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_FRCTIMOUT_DEFAULT (_MODEM_IEN_FRCTIMOUT_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_ETS (0x1UL << 17) /**< Early Time Stamp detect */
+#define _MODEM_IEN_ETS_SHIFT 17 /**< Shift value for MODEM_ETS */
+#define _MODEM_IEN_ETS_MASK 0x20000UL /**< Bit mask for MODEM_ETS */
+#define _MODEM_IEN_ETS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_ETS_DEFAULT (_MODEM_IEN_ETS_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_CFGANTPATTRD (0x1UL << 18) /**< CFGANTPATTRD */
+#define _MODEM_IEN_CFGANTPATTRD_SHIFT 18 /**< Shift value for MODEM_CFGANTPATTRD */
+#define _MODEM_IEN_CFGANTPATTRD_MASK 0x40000UL /**< Bit mask for MODEM_CFGANTPATTRD */
+#define _MODEM_IEN_CFGANTPATTRD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_CFGANTPATTRD_DEFAULT (_MODEM_IEN_CFGANTPATTRD_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_RXRESTARTRSSIMAPRE (0x1UL << 19) /**< RX restart using RSSI MA filter */
+#define _MODEM_IEN_RXRESTARTRSSIMAPRE_SHIFT 19 /**< Shift value for MODEM_RXRESTARTRSSIMAPRE */
+#define _MODEM_IEN_RXRESTARTRSSIMAPRE_MASK 0x80000UL /**< Bit mask for MODEM_RXRESTARTRSSIMAPRE */
+#define _MODEM_IEN_RXRESTARTRSSIMAPRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_RXRESTARTRSSIMAPRE_DEFAULT (_MODEM_IEN_RXRESTARTRSSIMAPRE_DEFAULT << 19) /**< Shifted mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_RXRESTARTRSSIMASYNC (0x1UL << 20) /**< RX restart using RSSI MA filter */
+#define _MODEM_IEN_RXRESTARTRSSIMASYNC_SHIFT 20 /**< Shift value for MODEM_RXRESTARTRSSIMASYNC */
+#define _MODEM_IEN_RXRESTARTRSSIMASYNC_MASK 0x100000UL /**< Bit mask for MODEM_RXRESTARTRSSIMASYNC */
+#define _MODEM_IEN_RXRESTARTRSSIMASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_RXRESTARTRSSIMASYNC_DEFAULT (_MODEM_IEN_RXRESTARTRSSIMASYNC_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_SQDET (0x1UL << 21) /**< SQ Detected */
+#define _MODEM_IEN_SQDET_SHIFT 21 /**< Shift value for MODEM_SQDET */
+#define _MODEM_IEN_SQDET_MASK 0x200000UL /**< Bit mask for MODEM_SQDET */
+#define _MODEM_IEN_SQDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_SQDET_DEFAULT (_MODEM_IEN_SQDET_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_SQNOTDET (0x1UL << 22) /**< SQ Not Detected */
+#define _MODEM_IEN_SQNOTDET_SHIFT 22 /**< Shift value for MODEM_SQNOTDET */
+#define _MODEM_IEN_SQNOTDET_MASK 0x400000UL /**< Bit mask for MODEM_SQNOTDET */
+#define _MODEM_IEN_SQNOTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_SQNOTDET_DEFAULT (_MODEM_IEN_SQNOTDET_DEFAULT << 22) /**< Shifted mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_ANTDIVRDY (0x1UL << 23) /**< RSSI and CORR data Ready */
+#define _MODEM_IEN_ANTDIVRDY_SHIFT 23 /**< Shift value for MODEM_ANTDIVRDY */
+#define _MODEM_IEN_ANTDIVRDY_MASK 0x800000UL /**< Bit mask for MODEM_ANTDIVRDY */
+#define _MODEM_IEN_ANTDIVRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_ANTDIVRDY_DEFAULT (_MODEM_IEN_ANTDIVRDY_DEFAULT << 23) /**< Shifted mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_SOFTRESETDONE (0x1UL << 24) /**< Soft reset done */
+#define _MODEM_IEN_SOFTRESETDONE_SHIFT 24 /**< Shift value for MODEM_SOFTRESETDONE */
+#define _MODEM_IEN_SOFTRESETDONE_MASK 0x1000000UL /**< Bit mask for MODEM_SOFTRESETDONE */
+#define _MODEM_IEN_SOFTRESETDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_SOFTRESETDONE_DEFAULT (_MODEM_IEN_SOFTRESETDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_SQPRENOTDET (0x1UL << 25) /**< SQ Not Detected */
+#define _MODEM_IEN_SQPRENOTDET_SHIFT 25 /**< Shift value for MODEM_SQPRENOTDET */
+#define _MODEM_IEN_SQPRENOTDET_MASK 0x2000000UL /**< Bit mask for MODEM_SQPRENOTDET */
+#define _MODEM_IEN_SQPRENOTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_SQPRENOTDET_DEFAULT (_MODEM_IEN_SQPRENOTDET_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_SQFRAMENOTDET (0x1UL << 26) /**< SQ Not Detected */
+#define _MODEM_IEN_SQFRAMENOTDET_SHIFT 26 /**< Shift value for MODEM_SQFRAMENOTDET */
+#define _MODEM_IEN_SQFRAMENOTDET_MASK 0x4000000UL /**< Bit mask for MODEM_SQFRAMENOTDET */
+#define _MODEM_IEN_SQFRAMENOTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_SQFRAMENOTDET_DEFAULT (_MODEM_IEN_SQFRAMENOTDET_DEFAULT << 26) /**< Shifted mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_SQAFCOUTOFBAND (0x1UL << 27) /**< SQ afc out of band */
+#define _MODEM_IEN_SQAFCOUTOFBAND_SHIFT 27 /**< Shift value for MODEM_SQAFCOUTOFBAND */
+#define _MODEM_IEN_SQAFCOUTOFBAND_MASK 0x8000000UL /**< Bit mask for MODEM_SQAFCOUTOFBAND */
+#define _MODEM_IEN_SQAFCOUTOFBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_SQAFCOUTOFBAND_DEFAULT (_MODEM_IEN_SQAFCOUTOFBAND_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_SIDET (0x1UL << 28) /**< Signal Identified */
+#define _MODEM_IEN_SIDET_SHIFT 28 /**< Shift value for MODEM_SIDET */
+#define _MODEM_IEN_SIDET_MASK 0x10000000UL /**< Bit mask for MODEM_SIDET */
+#define _MODEM_IEN_SIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_SIDET_DEFAULT (_MODEM_IEN_SIDET_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_SIRESET (0x1UL << 29) /**< Signal identifier reset */
+#define _MODEM_IEN_SIRESET_SHIFT 29 /**< Shift value for MODEM_SIRESET */
+#define _MODEM_IEN_SIRESET_MASK 0x20000000UL /**< Bit mask for MODEM_SIRESET */
+#define _MODEM_IEN_SIRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IEN */
+#define MODEM_IEN_SIRESET_DEFAULT (_MODEM_IEN_SIRESET_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_IEN */
+
+/* Bit fields for MODEM SEQIF */
+#define _MODEM_SEQIF_RESETVALUE 0x00000000UL /**< Default value for MODEM_SEQIF */
+#define _MODEM_SEQIF_MASK 0x3FFFFFFFUL /**< Mask for MODEM_SEQIF */
+#define MODEM_SEQIF_TXFRAMESENT (0x1UL << 0) /**< Frame sent */
+#define _MODEM_SEQIF_TXFRAMESENT_SHIFT 0 /**< Shift value for MODEM_TXFRAMESENT */
+#define _MODEM_SEQIF_TXFRAMESENT_MASK 0x1UL /**< Bit mask for MODEM_TXFRAMESENT */
+#define _MODEM_SEQIF_TXFRAMESENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_TXFRAMESENT_DEFAULT (_MODEM_SEQIF_TXFRAMESENT_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_TXSYNCSENT (0x1UL << 1) /**< Sync word sent */
+#define _MODEM_SEQIF_TXSYNCSENT_SHIFT 1 /**< Shift value for MODEM_TXSYNCSENT */
+#define _MODEM_SEQIF_TXSYNCSENT_MASK 0x2UL /**< Bit mask for MODEM_TXSYNCSENT */
+#define _MODEM_SEQIF_TXSYNCSENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_TXSYNCSENT_DEFAULT (_MODEM_SEQIF_TXSYNCSENT_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_TXPRESENT (0x1UL << 2) /**< Preamble sent */
+#define _MODEM_SEQIF_TXPRESENT_SHIFT 2 /**< Shift value for MODEM_TXPRESENT */
+#define _MODEM_SEQIF_TXPRESENT_MASK 0x4UL /**< Bit mask for MODEM_TXPRESENT */
+#define _MODEM_SEQIF_TXPRESENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_TXPRESENT_DEFAULT (_MODEM_SEQIF_TXPRESENT_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_TXRAMPDONE (0x1UL << 3) /**< Mod ramper idle */
+#define _MODEM_SEQIF_TXRAMPDONE_SHIFT 3 /**< Shift value for MODEM_TXRAMPDONE */
+#define _MODEM_SEQIF_TXRAMPDONE_MASK 0x8UL /**< Bit mask for MODEM_TXRAMPDONE */
+#define _MODEM_SEQIF_TXRAMPDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_TXRAMPDONE_DEFAULT (_MODEM_SEQIF_TXRAMPDONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_LDTNOARR (0x1UL << 4) /**< No signal Detected in LDT */
+#define _MODEM_SEQIF_LDTNOARR_SHIFT 4 /**< Shift value for MODEM_LDTNOARR */
+#define _MODEM_SEQIF_LDTNOARR_MASK 0x10UL /**< Bit mask for MODEM_LDTNOARR */
+#define _MODEM_SEQIF_LDTNOARR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_LDTNOARR_DEFAULT (_MODEM_SEQIF_LDTNOARR_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_PHDSADET (0x1UL << 5) /**< PHASE DSA DETECT */
+#define _MODEM_SEQIF_PHDSADET_SHIFT 5 /**< Shift value for MODEM_PHDSADET */
+#define _MODEM_SEQIF_PHDSADET_MASK 0x20UL /**< Bit mask for MODEM_PHDSADET */
+#define _MODEM_SEQIF_PHDSADET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_PHDSADET_DEFAULT (_MODEM_SEQIF_PHDSADET_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_PHYUNCODEDET (0x1UL << 6) /**< CONCURRENT UNCODED PHY DET */
+#define _MODEM_SEQIF_PHYUNCODEDET_SHIFT 6 /**< Shift value for MODEM_PHYUNCODEDET */
+#define _MODEM_SEQIF_PHYUNCODEDET_MASK 0x40UL /**< Bit mask for MODEM_PHYUNCODEDET */
+#define _MODEM_SEQIF_PHYUNCODEDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_PHYUNCODEDET_DEFAULT (_MODEM_SEQIF_PHYUNCODEDET_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_PHYCODEDET (0x1UL << 7) /**< CONCURRENT CODED PHY DET */
+#define _MODEM_SEQIF_PHYCODEDET_SHIFT 7 /**< Shift value for MODEM_PHYCODEDET */
+#define _MODEM_SEQIF_PHYCODEDET_MASK 0x80UL /**< Bit mask for MODEM_PHYCODEDET */
+#define _MODEM_SEQIF_PHYCODEDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_PHYCODEDET_DEFAULT (_MODEM_SEQIF_PHYCODEDET_DEFAULT << 7) /**< Shifted mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_RXTIMDET (0x1UL << 8) /**< Timing detected */
+#define _MODEM_SEQIF_RXTIMDET_SHIFT 8 /**< Shift value for MODEM_RXTIMDET */
+#define _MODEM_SEQIF_RXTIMDET_MASK 0x100UL /**< Bit mask for MODEM_RXTIMDET */
+#define _MODEM_SEQIF_RXTIMDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_RXTIMDET_DEFAULT (_MODEM_SEQIF_RXTIMDET_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_RXPREDET (0x1UL << 9) /**< Preamble detected */
+#define _MODEM_SEQIF_RXPREDET_SHIFT 9 /**< Shift value for MODEM_RXPREDET */
+#define _MODEM_SEQIF_RXPREDET_MASK 0x200UL /**< Bit mask for MODEM_RXPREDET */
+#define _MODEM_SEQIF_RXPREDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_RXPREDET_DEFAULT (_MODEM_SEQIF_RXPREDET_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_RXFRAMEDET0 (0x1UL << 10) /**< Frame with sync-word 0 detected */
+#define _MODEM_SEQIF_RXFRAMEDET0_SHIFT 10 /**< Shift value for MODEM_RXFRAMEDET0 */
+#define _MODEM_SEQIF_RXFRAMEDET0_MASK 0x400UL /**< Bit mask for MODEM_RXFRAMEDET0 */
+#define _MODEM_SEQIF_RXFRAMEDET0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_RXFRAMEDET0_DEFAULT (_MODEM_SEQIF_RXFRAMEDET0_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_RXFRAMEDET1 (0x1UL << 11) /**< Frame with sync-word 1 detected */
+#define _MODEM_SEQIF_RXFRAMEDET1_SHIFT 11 /**< Shift value for MODEM_RXFRAMEDET1 */
+#define _MODEM_SEQIF_RXFRAMEDET1_MASK 0x800UL /**< Bit mask for MODEM_RXFRAMEDET1 */
+#define _MODEM_SEQIF_RXFRAMEDET1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_RXFRAMEDET1_DEFAULT (_MODEM_SEQIF_RXFRAMEDET1_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_RXTIMLOST (0x1UL << 12) /**< Timing lost */
+#define _MODEM_SEQIF_RXTIMLOST_SHIFT 12 /**< Shift value for MODEM_RXTIMLOST */
+#define _MODEM_SEQIF_RXTIMLOST_MASK 0x1000UL /**< Bit mask for MODEM_RXTIMLOST */
+#define _MODEM_SEQIF_RXTIMLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_RXTIMLOST_DEFAULT (_MODEM_SEQIF_RXTIMLOST_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_RXPRELOST (0x1UL << 13) /**< Preamble lost */
+#define _MODEM_SEQIF_RXPRELOST_SHIFT 13 /**< Shift value for MODEM_RXPRELOST */
+#define _MODEM_SEQIF_RXPRELOST_MASK 0x2000UL /**< Bit mask for MODEM_RXPRELOST */
+#define _MODEM_SEQIF_RXPRELOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_RXPRELOST_DEFAULT (_MODEM_SEQIF_RXPRELOST_DEFAULT << 13) /**< Shifted mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_RXFRAMEDETOF (0x1UL << 14) /**< Frame detection overflow */
+#define _MODEM_SEQIF_RXFRAMEDETOF_SHIFT 14 /**< Shift value for MODEM_RXFRAMEDETOF */
+#define _MODEM_SEQIF_RXFRAMEDETOF_MASK 0x4000UL /**< Bit mask for MODEM_RXFRAMEDETOF */
+#define _MODEM_SEQIF_RXFRAMEDETOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_RXFRAMEDETOF_DEFAULT (_MODEM_SEQIF_RXFRAMEDETOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_RXTIMNF (0x1UL << 15) /**< Timing not found */
+#define _MODEM_SEQIF_RXTIMNF_SHIFT 15 /**< Shift value for MODEM_RXTIMNF */
+#define _MODEM_SEQIF_RXTIMNF_MASK 0x8000UL /**< Bit mask for MODEM_RXTIMNF */
+#define _MODEM_SEQIF_RXTIMNF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_RXTIMNF_DEFAULT (_MODEM_SEQIF_RXTIMNF_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_FRCTIMOUT (0x1UL << 16) /**< DEMOD-FRC req/ack timeout */
+#define _MODEM_SEQIF_FRCTIMOUT_SHIFT 16 /**< Shift value for MODEM_FRCTIMOUT */
+#define _MODEM_SEQIF_FRCTIMOUT_MASK 0x10000UL /**< Bit mask for MODEM_FRCTIMOUT */
+#define _MODEM_SEQIF_FRCTIMOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_FRCTIMOUT_DEFAULT (_MODEM_SEQIF_FRCTIMOUT_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_ETS (0x1UL << 17) /**< Early timestamp */
+#define _MODEM_SEQIF_ETS_SHIFT 17 /**< Shift value for MODEM_ETS */
+#define _MODEM_SEQIF_ETS_MASK 0x20000UL /**< Bit mask for MODEM_ETS */
+#define _MODEM_SEQIF_ETS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_ETS_DEFAULT (_MODEM_SEQIF_ETS_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_CFGANTPATTRD (0x1UL << 18) /**< CFGANTPATTRD */
+#define _MODEM_SEQIF_CFGANTPATTRD_SHIFT 18 /**< Shift value for MODEM_CFGANTPATTRD */
+#define _MODEM_SEQIF_CFGANTPATTRD_MASK 0x40000UL /**< Bit mask for MODEM_CFGANTPATTRD */
+#define _MODEM_SEQIF_CFGANTPATTRD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_CFGANTPATTRD_DEFAULT (_MODEM_SEQIF_CFGANTPATTRD_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_RXRESTARTRSSIMAPRE (0x1UL << 19) /**< RX restart using RSSI MA filter */
+#define _MODEM_SEQIF_RXRESTARTRSSIMAPRE_SHIFT 19 /**< Shift value for MODEM_RXRESTARTRSSIMAPRE */
+#define _MODEM_SEQIF_RXRESTARTRSSIMAPRE_MASK 0x80000UL /**< Bit mask for MODEM_RXRESTARTRSSIMAPRE */
+#define _MODEM_SEQIF_RXRESTARTRSSIMAPRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_RXRESTARTRSSIMAPRE_DEFAULT (_MODEM_SEQIF_RXRESTARTRSSIMAPRE_DEFAULT << 19) /**< Shifted mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_RXRESTARTRSSIMASYNC (0x1UL << 20) /**< RX restart using RSSI MA filter */
+#define _MODEM_SEQIF_RXRESTARTRSSIMASYNC_SHIFT 20 /**< Shift value for MODEM_RXRESTARTRSSIMASYNC */
+#define _MODEM_SEQIF_RXRESTARTRSSIMASYNC_MASK 0x100000UL /**< Bit mask for MODEM_RXRESTARTRSSIMASYNC */
+#define _MODEM_SEQIF_RXRESTARTRSSIMASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_RXRESTARTRSSIMASYNC_DEFAULT (_MODEM_SEQIF_RXRESTARTRSSIMASYNC_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_SQDET (0x1UL << 21) /**< SQ Detected */
+#define _MODEM_SEQIF_SQDET_SHIFT 21 /**< Shift value for MODEM_SQDET */
+#define _MODEM_SEQIF_SQDET_MASK 0x200000UL /**< Bit mask for MODEM_SQDET */
+#define _MODEM_SEQIF_SQDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_SQDET_DEFAULT (_MODEM_SEQIF_SQDET_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_SQNOTDET (0x1UL << 22) /**< SQ NOT Detected */
+#define _MODEM_SEQIF_SQNOTDET_SHIFT 22 /**< Shift value for MODEM_SQNOTDET */
+#define _MODEM_SEQIF_SQNOTDET_MASK 0x400000UL /**< Bit mask for MODEM_SQNOTDET */
+#define _MODEM_SEQIF_SQNOTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_SQNOTDET_DEFAULT (_MODEM_SEQIF_SQNOTDET_DEFAULT << 22) /**< Shifted mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_ANTDIVRDY (0x1UL << 23) /**< RSSI and CORR data Ready */
+#define _MODEM_SEQIF_ANTDIVRDY_SHIFT 23 /**< Shift value for MODEM_ANTDIVRDY */
+#define _MODEM_SEQIF_ANTDIVRDY_MASK 0x800000UL /**< Bit mask for MODEM_ANTDIVRDY */
+#define _MODEM_SEQIF_ANTDIVRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_ANTDIVRDY_DEFAULT (_MODEM_SEQIF_ANTDIVRDY_DEFAULT << 23) /**< Shifted mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_SOFTRESETDONE (0x1UL << 24) /**< Soft reset done */
+#define _MODEM_SEQIF_SOFTRESETDONE_SHIFT 24 /**< Shift value for MODEM_SOFTRESETDONE */
+#define _MODEM_SEQIF_SOFTRESETDONE_MASK 0x1000000UL /**< Bit mask for MODEM_SOFTRESETDONE */
+#define _MODEM_SEQIF_SOFTRESETDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_SOFTRESETDONE_DEFAULT (_MODEM_SEQIF_SOFTRESETDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_SQPRENOTDET (0x1UL << 25) /**< SQ NOT Detected */
+#define _MODEM_SEQIF_SQPRENOTDET_SHIFT 25 /**< Shift value for MODEM_SQPRENOTDET */
+#define _MODEM_SEQIF_SQPRENOTDET_MASK 0x2000000UL /**< Bit mask for MODEM_SQPRENOTDET */
+#define _MODEM_SEQIF_SQPRENOTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_SQPRENOTDET_DEFAULT (_MODEM_SEQIF_SQPRENOTDET_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_SQFRAMENOTDET (0x1UL << 26) /**< SQ NOT Detected */
+#define _MODEM_SEQIF_SQFRAMENOTDET_SHIFT 26 /**< Shift value for MODEM_SQFRAMENOTDET */
+#define _MODEM_SEQIF_SQFRAMENOTDET_MASK 0x4000000UL /**< Bit mask for MODEM_SQFRAMENOTDET */
+#define _MODEM_SEQIF_SQFRAMENOTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_SQFRAMENOTDET_DEFAULT (_MODEM_SEQIF_SQFRAMENOTDET_DEFAULT << 26) /**< Shifted mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_SQAFCOUTOFBAND (0x1UL << 27) /**< SQ afc out of band */
+#define _MODEM_SEQIF_SQAFCOUTOFBAND_SHIFT 27 /**< Shift value for MODEM_SQAFCOUTOFBAND */
+#define _MODEM_SEQIF_SQAFCOUTOFBAND_MASK 0x8000000UL /**< Bit mask for MODEM_SQAFCOUTOFBAND */
+#define _MODEM_SEQIF_SQAFCOUTOFBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_SQAFCOUTOFBAND_DEFAULT (_MODEM_SEQIF_SQAFCOUTOFBAND_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_SIDET (0x1UL << 28) /**< Signal identified */
+#define _MODEM_SEQIF_SIDET_SHIFT 28 /**< Shift value for MODEM_SIDET */
+#define _MODEM_SEQIF_SIDET_MASK 0x10000000UL /**< Bit mask for MODEM_SIDET */
+#define _MODEM_SEQIF_SIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_SIDET_DEFAULT (_MODEM_SEQIF_SIDET_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_SIRESET (0x1UL << 29) /**< Signal identifier reset */
+#define _MODEM_SEQIF_SIRESET_SHIFT 29 /**< Shift value for MODEM_SIRESET */
+#define _MODEM_SEQIF_SIRESET_MASK 0x20000000UL /**< Bit mask for MODEM_SIRESET */
+#define _MODEM_SEQIF_SIRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIF */
+#define MODEM_SEQIF_SIRESET_DEFAULT (_MODEM_SEQIF_SIRESET_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_SEQIF */
+
+/* Bit fields for MODEM SEQIEN */
+#define _MODEM_SEQIEN_RESETVALUE 0x00000000UL /**< Default value for MODEM_SEQIEN */
+#define _MODEM_SEQIEN_MASK 0x3FFFFFFFUL /**< Mask for MODEM_SEQIEN */
+#define MODEM_SEQIEN_TXFRAMESENT (0x1UL << 0) /**< Frame sent */
+#define _MODEM_SEQIEN_TXFRAMESENT_SHIFT 0 /**< Shift value for MODEM_TXFRAMESENT */
+#define _MODEM_SEQIEN_TXFRAMESENT_MASK 0x1UL /**< Bit mask for MODEM_TXFRAMESENT */
+#define _MODEM_SEQIEN_TXFRAMESENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_TXFRAMESENT_DEFAULT (_MODEM_SEQIEN_TXFRAMESENT_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_TXSYNCSENT (0x1UL << 1) /**< Sync word sent */
+#define _MODEM_SEQIEN_TXSYNCSENT_SHIFT 1 /**< Shift value for MODEM_TXSYNCSENT */
+#define _MODEM_SEQIEN_TXSYNCSENT_MASK 0x2UL /**< Bit mask for MODEM_TXSYNCSENT */
+#define _MODEM_SEQIEN_TXSYNCSENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_TXSYNCSENT_DEFAULT (_MODEM_SEQIEN_TXSYNCSENT_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_TXPRESENT (0x1UL << 2) /**< Preamble sent */
+#define _MODEM_SEQIEN_TXPRESENT_SHIFT 2 /**< Shift value for MODEM_TXPRESENT */
+#define _MODEM_SEQIEN_TXPRESENT_MASK 0x4UL /**< Bit mask for MODEM_TXPRESENT */
+#define _MODEM_SEQIEN_TXPRESENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_TXPRESENT_DEFAULT (_MODEM_SEQIEN_TXPRESENT_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_TXRAMPDONE (0x1UL << 3) /**< Mod ramper idle */
+#define _MODEM_SEQIEN_TXRAMPDONE_SHIFT 3 /**< Shift value for MODEM_TXRAMPDONE */
+#define _MODEM_SEQIEN_TXRAMPDONE_MASK 0x8UL /**< Bit mask for MODEM_TXRAMPDONE */
+#define _MODEM_SEQIEN_TXRAMPDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_TXRAMPDONE_DEFAULT (_MODEM_SEQIEN_TXRAMPDONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_LDTNOARR (0x1UL << 4) /**< No signal Detected in LDT */
+#define _MODEM_SEQIEN_LDTNOARR_SHIFT 4 /**< Shift value for MODEM_LDTNOARR */
+#define _MODEM_SEQIEN_LDTNOARR_MASK 0x10UL /**< Bit mask for MODEM_LDTNOARR */
+#define _MODEM_SEQIEN_LDTNOARR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_LDTNOARR_DEFAULT (_MODEM_SEQIEN_LDTNOARR_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_PHDSADET (0x1UL << 5) /**< PHASE DSA DETECT */
+#define _MODEM_SEQIEN_PHDSADET_SHIFT 5 /**< Shift value for MODEM_PHDSADET */
+#define _MODEM_SEQIEN_PHDSADET_MASK 0x20UL /**< Bit mask for MODEM_PHDSADET */
+#define _MODEM_SEQIEN_PHDSADET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_PHDSADET_DEFAULT (_MODEM_SEQIEN_PHDSADET_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_PHYUNCODEDET (0x1UL << 6) /**< CONCURRENT UNCODED PHY DET */
+#define _MODEM_SEQIEN_PHYUNCODEDET_SHIFT 6 /**< Shift value for MODEM_PHYUNCODEDET */
+#define _MODEM_SEQIEN_PHYUNCODEDET_MASK 0x40UL /**< Bit mask for MODEM_PHYUNCODEDET */
+#define _MODEM_SEQIEN_PHYUNCODEDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_PHYUNCODEDET_DEFAULT (_MODEM_SEQIEN_PHYUNCODEDET_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_PHYCODEDET (0x1UL << 7) /**< CONCURRENT CODED PHY DET */
+#define _MODEM_SEQIEN_PHYCODEDET_SHIFT 7 /**< Shift value for MODEM_PHYCODEDET */
+#define _MODEM_SEQIEN_PHYCODEDET_MASK 0x80UL /**< Bit mask for MODEM_PHYCODEDET */
+#define _MODEM_SEQIEN_PHYCODEDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_PHYCODEDET_DEFAULT (_MODEM_SEQIEN_PHYCODEDET_DEFAULT << 7) /**< Shifted mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_RXTIMDET (0x1UL << 8) /**< Timing detected */
+#define _MODEM_SEQIEN_RXTIMDET_SHIFT 8 /**< Shift value for MODEM_RXTIMDET */
+#define _MODEM_SEQIEN_RXTIMDET_MASK 0x100UL /**< Bit mask for MODEM_RXTIMDET */
+#define _MODEM_SEQIEN_RXTIMDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_RXTIMDET_DEFAULT (_MODEM_SEQIEN_RXTIMDET_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_RXPREDET (0x1UL << 9) /**< Preamble detected */
+#define _MODEM_SEQIEN_RXPREDET_SHIFT 9 /**< Shift value for MODEM_RXPREDET */
+#define _MODEM_SEQIEN_RXPREDET_MASK 0x200UL /**< Bit mask for MODEM_RXPREDET */
+#define _MODEM_SEQIEN_RXPREDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_RXPREDET_DEFAULT (_MODEM_SEQIEN_RXPREDET_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_RXFRAMEDET0 (0x1UL << 10) /**< Frame with sync-word 0 detected */
+#define _MODEM_SEQIEN_RXFRAMEDET0_SHIFT 10 /**< Shift value for MODEM_RXFRAMEDET0 */
+#define _MODEM_SEQIEN_RXFRAMEDET0_MASK 0x400UL /**< Bit mask for MODEM_RXFRAMEDET0 */
+#define _MODEM_SEQIEN_RXFRAMEDET0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_RXFRAMEDET0_DEFAULT (_MODEM_SEQIEN_RXFRAMEDET0_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_RXFRAMEDET1 (0x1UL << 11) /**< Frame with sync-word 1 detected */
+#define _MODEM_SEQIEN_RXFRAMEDET1_SHIFT 11 /**< Shift value for MODEM_RXFRAMEDET1 */
+#define _MODEM_SEQIEN_RXFRAMEDET1_MASK 0x800UL /**< Bit mask for MODEM_RXFRAMEDET1 */
+#define _MODEM_SEQIEN_RXFRAMEDET1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_RXFRAMEDET1_DEFAULT (_MODEM_SEQIEN_RXFRAMEDET1_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_RXTIMLOST (0x1UL << 12) /**< Timing lost */
+#define _MODEM_SEQIEN_RXTIMLOST_SHIFT 12 /**< Shift value for MODEM_RXTIMLOST */
+#define _MODEM_SEQIEN_RXTIMLOST_MASK 0x1000UL /**< Bit mask for MODEM_RXTIMLOST */
+#define _MODEM_SEQIEN_RXTIMLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_RXTIMLOST_DEFAULT (_MODEM_SEQIEN_RXTIMLOST_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_RXPRELOST (0x1UL << 13) /**< Preamble lost */
+#define _MODEM_SEQIEN_RXPRELOST_SHIFT 13 /**< Shift value for MODEM_RXPRELOST */
+#define _MODEM_SEQIEN_RXPRELOST_MASK 0x2000UL /**< Bit mask for MODEM_RXPRELOST */
+#define _MODEM_SEQIEN_RXPRELOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_RXPRELOST_DEFAULT (_MODEM_SEQIEN_RXPRELOST_DEFAULT << 13) /**< Shifted mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_RXFRAMEDETOF (0x1UL << 14) /**< Frame detection overflow */
+#define _MODEM_SEQIEN_RXFRAMEDETOF_SHIFT 14 /**< Shift value for MODEM_RXFRAMEDETOF */
+#define _MODEM_SEQIEN_RXFRAMEDETOF_MASK 0x4000UL /**< Bit mask for MODEM_RXFRAMEDETOF */
+#define _MODEM_SEQIEN_RXFRAMEDETOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_RXFRAMEDETOF_DEFAULT (_MODEM_SEQIEN_RXFRAMEDETOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_RXTIMNF (0x1UL << 15) /**< Timing not found */
+#define _MODEM_SEQIEN_RXTIMNF_SHIFT 15 /**< Shift value for MODEM_RXTIMNF */
+#define _MODEM_SEQIEN_RXTIMNF_MASK 0x8000UL /**< Bit mask for MODEM_RXTIMNF */
+#define _MODEM_SEQIEN_RXTIMNF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_RXTIMNF_DEFAULT (_MODEM_SEQIEN_RXTIMNF_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_FRCTIMOUT (0x1UL << 16) /**< DEMOD-FRC req/ack timeout */
+#define _MODEM_SEQIEN_FRCTIMOUT_SHIFT 16 /**< Shift value for MODEM_FRCTIMOUT */
+#define _MODEM_SEQIEN_FRCTIMOUT_MASK 0x10000UL /**< Bit mask for MODEM_FRCTIMOUT */
+#define _MODEM_SEQIEN_FRCTIMOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_FRCTIMOUT_DEFAULT (_MODEM_SEQIEN_FRCTIMOUT_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_ETS (0x1UL << 17) /**< Early time stamp */
+#define _MODEM_SEQIEN_ETS_SHIFT 17 /**< Shift value for MODEM_ETS */
+#define _MODEM_SEQIEN_ETS_MASK 0x20000UL /**< Bit mask for MODEM_ETS */
+#define _MODEM_SEQIEN_ETS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_ETS_DEFAULT (_MODEM_SEQIEN_ETS_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_CFGANTPATTRD (0x1UL << 18) /**< CFGANTPATTRD */
+#define _MODEM_SEQIEN_CFGANTPATTRD_SHIFT 18 /**< Shift value for MODEM_CFGANTPATTRD */
+#define _MODEM_SEQIEN_CFGANTPATTRD_MASK 0x40000UL /**< Bit mask for MODEM_CFGANTPATTRD */
+#define _MODEM_SEQIEN_CFGANTPATTRD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_CFGANTPATTRD_DEFAULT (_MODEM_SEQIEN_CFGANTPATTRD_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_RXRESTARTRSSIMAPRE (0x1UL << 19) /**< RX restart using RSSI MA filter */
+#define _MODEM_SEQIEN_RXRESTARTRSSIMAPRE_SHIFT 19 /**< Shift value for MODEM_RXRESTARTRSSIMAPRE */
+#define _MODEM_SEQIEN_RXRESTARTRSSIMAPRE_MASK 0x80000UL /**< Bit mask for MODEM_RXRESTARTRSSIMAPRE */
+#define _MODEM_SEQIEN_RXRESTARTRSSIMAPRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_RXRESTARTRSSIMAPRE_DEFAULT (_MODEM_SEQIEN_RXRESTARTRSSIMAPRE_DEFAULT << 19) /**< Shifted mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_RXRESTARTRSSIMASYNC (0x1UL << 20) /**< RX restart using RSSI MA filter */
+#define _MODEM_SEQIEN_RXRESTARTRSSIMASYNC_SHIFT 20 /**< Shift value for MODEM_RXRESTARTRSSIMASYNC */
+#define _MODEM_SEQIEN_RXRESTARTRSSIMASYNC_MASK 0x100000UL /**< Bit mask for MODEM_RXRESTARTRSSIMASYNC */
+#define _MODEM_SEQIEN_RXRESTARTRSSIMASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_RXRESTARTRSSIMASYNC_DEFAULT (_MODEM_SEQIEN_RXRESTARTRSSIMASYNC_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_SQDET (0x1UL << 21) /**< SQ DET */
+#define _MODEM_SEQIEN_SQDET_SHIFT 21 /**< Shift value for MODEM_SQDET */
+#define _MODEM_SEQIEN_SQDET_MASK 0x200000UL /**< Bit mask for MODEM_SQDET */
+#define _MODEM_SEQIEN_SQDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_SQDET_DEFAULT (_MODEM_SEQIEN_SQDET_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_SQNOTDET (0x1UL << 22) /**< SQ Not DET */
+#define _MODEM_SEQIEN_SQNOTDET_SHIFT 22 /**< Shift value for MODEM_SQNOTDET */
+#define _MODEM_SEQIEN_SQNOTDET_MASK 0x400000UL /**< Bit mask for MODEM_SQNOTDET */
+#define _MODEM_SEQIEN_SQNOTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_SQNOTDET_DEFAULT (_MODEM_SEQIEN_SQNOTDET_DEFAULT << 22) /**< Shifted mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_ANTDIVRDY (0x1UL << 23) /**< RSSI and CORR data Ready */
+#define _MODEM_SEQIEN_ANTDIVRDY_SHIFT 23 /**< Shift value for MODEM_ANTDIVRDY */
+#define _MODEM_SEQIEN_ANTDIVRDY_MASK 0x800000UL /**< Bit mask for MODEM_ANTDIVRDY */
+#define _MODEM_SEQIEN_ANTDIVRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_ANTDIVRDY_DEFAULT (_MODEM_SEQIEN_ANTDIVRDY_DEFAULT << 23) /**< Shifted mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_SOFTRESETDONE (0x1UL << 24) /**< Soft reset done */
+#define _MODEM_SEQIEN_SOFTRESETDONE_SHIFT 24 /**< Shift value for MODEM_SOFTRESETDONE */
+#define _MODEM_SEQIEN_SOFTRESETDONE_MASK 0x1000000UL /**< Bit mask for MODEM_SOFTRESETDONE */
+#define _MODEM_SEQIEN_SOFTRESETDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_SOFTRESETDONE_DEFAULT (_MODEM_SEQIEN_SOFTRESETDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_SQPRENOTDET (0x1UL << 25) /**< SQ Not DET */
+#define _MODEM_SEQIEN_SQPRENOTDET_SHIFT 25 /**< Shift value for MODEM_SQPRENOTDET */
+#define _MODEM_SEQIEN_SQPRENOTDET_MASK 0x2000000UL /**< Bit mask for MODEM_SQPRENOTDET */
+#define _MODEM_SEQIEN_SQPRENOTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_SQPRENOTDET_DEFAULT (_MODEM_SEQIEN_SQPRENOTDET_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_SQFRAMENOTDET (0x1UL << 26) /**< SQ Not DET */
+#define _MODEM_SEQIEN_SQFRAMENOTDET_SHIFT 26 /**< Shift value for MODEM_SQFRAMENOTDET */
+#define _MODEM_SEQIEN_SQFRAMENOTDET_MASK 0x4000000UL /**< Bit mask for MODEM_SQFRAMENOTDET */
+#define _MODEM_SEQIEN_SQFRAMENOTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_SQFRAMENOTDET_DEFAULT (_MODEM_SEQIEN_SQFRAMENOTDET_DEFAULT << 26) /**< Shifted mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_SQAFCOUTOFBAND (0x1UL << 27) /**< SQ afc out of band */
+#define _MODEM_SEQIEN_SQAFCOUTOFBAND_SHIFT 27 /**< Shift value for MODEM_SQAFCOUTOFBAND */
+#define _MODEM_SEQIEN_SQAFCOUTOFBAND_MASK 0x8000000UL /**< Bit mask for MODEM_SQAFCOUTOFBAND */
+#define _MODEM_SEQIEN_SQAFCOUTOFBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_SQAFCOUTOFBAND_DEFAULT (_MODEM_SEQIEN_SQAFCOUTOFBAND_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_SIDET (0x1UL << 28) /**< Signal Identified */
+#define _MODEM_SEQIEN_SIDET_SHIFT 28 /**< Shift value for MODEM_SIDET */
+#define _MODEM_SEQIEN_SIDET_MASK 0x10000000UL /**< Bit mask for MODEM_SIDET */
+#define _MODEM_SEQIEN_SIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_SIDET_DEFAULT (_MODEM_SEQIEN_SIDET_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_SIRESET (0x1UL << 29) /**< Signal identifier reset */
+#define _MODEM_SEQIEN_SIRESET_SHIFT 29 /**< Shift value for MODEM_SIRESET */
+#define _MODEM_SEQIEN_SIRESET_MASK 0x20000000UL /**< Bit mask for MODEM_SIRESET */
+#define _MODEM_SEQIEN_SIRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SEQIEN */
+#define MODEM_SEQIEN_SIRESET_DEFAULT (_MODEM_SEQIEN_SIRESET_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_SEQIEN */
+
+/* Bit fields for MODEM STATUS */
+#define _MODEM_STATUS_RESETVALUE 0x00000000UL /**< Default value for MODEM_STATUS */
+#define _MODEM_STATUS_MASK 0xFFFFFFFFUL /**< Mask for MODEM_STATUS */
+#define _MODEM_STATUS_DEMODSTATE_SHIFT 0 /**< Shift value for MODEM_DEMODSTATE */
+#define _MODEM_STATUS_DEMODSTATE_MASK 0x7UL /**< Bit mask for MODEM_DEMODSTATE */
+#define _MODEM_STATUS_DEMODSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS */
+#define _MODEM_STATUS_DEMODSTATE_OFF 0x00000000UL /**< Mode OFF for MODEM_STATUS */
+#define _MODEM_STATUS_DEMODSTATE_TIMINGSEARCH 0x00000001UL /**< Mode TIMINGSEARCH for MODEM_STATUS */
+#define _MODEM_STATUS_DEMODSTATE_PRESEARCH 0x00000002UL /**< Mode PRESEARCH for MODEM_STATUS */
+#define _MODEM_STATUS_DEMODSTATE_FRAMESEARCH 0x00000003UL /**< Mode FRAMESEARCH for MODEM_STATUS */
+#define _MODEM_STATUS_DEMODSTATE_RXFRAME 0x00000004UL /**< Mode RXFRAME for MODEM_STATUS */
+#define _MODEM_STATUS_DEMODSTATE_FRAMEDETMODE0 0x00000005UL /**< Mode FRAMEDETMODE0 for MODEM_STATUS */
+#define MODEM_STATUS_DEMODSTATE_DEFAULT (_MODEM_STATUS_DEMODSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_STATUS */
+#define MODEM_STATUS_DEMODSTATE_OFF (_MODEM_STATUS_DEMODSTATE_OFF << 0) /**< Shifted mode OFF for MODEM_STATUS */
+#define MODEM_STATUS_DEMODSTATE_TIMINGSEARCH (_MODEM_STATUS_DEMODSTATE_TIMINGSEARCH << 0) /**< Shifted mode TIMINGSEARCH for MODEM_STATUS */
+#define MODEM_STATUS_DEMODSTATE_PRESEARCH (_MODEM_STATUS_DEMODSTATE_PRESEARCH << 0) /**< Shifted mode PRESEARCH for MODEM_STATUS */
+#define MODEM_STATUS_DEMODSTATE_FRAMESEARCH (_MODEM_STATUS_DEMODSTATE_FRAMESEARCH << 0) /**< Shifted mode FRAMESEARCH for MODEM_STATUS */
+#define MODEM_STATUS_DEMODSTATE_RXFRAME (_MODEM_STATUS_DEMODSTATE_RXFRAME << 0) /**< Shifted mode RXFRAME for MODEM_STATUS */
+#define MODEM_STATUS_DEMODSTATE_FRAMEDETMODE0 (_MODEM_STATUS_DEMODSTATE_FRAMEDETMODE0 << 0) /**< Shifted mode FRAMEDETMODE0 for MODEM_STATUS */
+#define MODEM_STATUS_BCRCFEDSADET (0x1UL << 3) /**< BCR CFE DSA DETECTION */
+#define _MODEM_STATUS_BCRCFEDSADET_SHIFT 3 /**< Shift value for MODEM_BCRCFEDSADET */
+#define _MODEM_STATUS_BCRCFEDSADET_MASK 0x8UL /**< Bit mask for MODEM_BCRCFEDSADET */
+#define _MODEM_STATUS_BCRCFEDSADET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS */
+#define MODEM_STATUS_BCRCFEDSADET_DEFAULT (_MODEM_STATUS_BCRCFEDSADET_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_STATUS */
+#define MODEM_STATUS_FRAMEDETID (0x1UL << 4) /**< Frame Detected ID */
+#define _MODEM_STATUS_FRAMEDETID_SHIFT 4 /**< Shift value for MODEM_FRAMEDETID */
+#define _MODEM_STATUS_FRAMEDETID_MASK 0x10UL /**< Bit mask for MODEM_FRAMEDETID */
+#define _MODEM_STATUS_FRAMEDETID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS */
+#define _MODEM_STATUS_FRAMEDETID_FRAMEDET0 0x00000000UL /**< Mode FRAMEDET0 for MODEM_STATUS */
+#define _MODEM_STATUS_FRAMEDETID_FRAMEDET1 0x00000001UL /**< Mode FRAMEDET1 for MODEM_STATUS */
+#define MODEM_STATUS_FRAMEDETID_DEFAULT (_MODEM_STATUS_FRAMEDETID_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_STATUS */
+#define MODEM_STATUS_FRAMEDETID_FRAMEDET0 (_MODEM_STATUS_FRAMEDETID_FRAMEDET0 << 4) /**< Shifted mode FRAMEDET0 for MODEM_STATUS */
+#define MODEM_STATUS_FRAMEDETID_FRAMEDET1 (_MODEM_STATUS_FRAMEDETID_FRAMEDET1 << 4) /**< Shifted mode FRAMEDET1 for MODEM_STATUS */
+#define MODEM_STATUS_ANTSEL (0x1UL << 5) /**< Selected Antenna */
+#define _MODEM_STATUS_ANTSEL_SHIFT 5 /**< Shift value for MODEM_ANTSEL */
+#define _MODEM_STATUS_ANTSEL_MASK 0x20UL /**< Bit mask for MODEM_ANTSEL */
+#define _MODEM_STATUS_ANTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS */
+#define _MODEM_STATUS_ANTSEL_ANTENNA0 0x00000000UL /**< Mode ANTENNA0 for MODEM_STATUS */
+#define _MODEM_STATUS_ANTSEL_ANTENNA1 0x00000001UL /**< Mode ANTENNA1 for MODEM_STATUS */
+#define MODEM_STATUS_ANTSEL_DEFAULT (_MODEM_STATUS_ANTSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_STATUS */
+#define MODEM_STATUS_ANTSEL_ANTENNA0 (_MODEM_STATUS_ANTSEL_ANTENNA0 << 5) /**< Shifted mode ANTENNA0 for MODEM_STATUS */
+#define MODEM_STATUS_ANTSEL_ANTENNA1 (_MODEM_STATUS_ANTSEL_ANTENNA1 << 5) /**< Shifted mode ANTENNA1 for MODEM_STATUS */
+#define MODEM_STATUS_TIMSEQINV (0x1UL << 6) /**< Timing Sequence Inverted */
+#define _MODEM_STATUS_TIMSEQINV_SHIFT 6 /**< Shift value for MODEM_TIMSEQINV */
+#define _MODEM_STATUS_TIMSEQINV_MASK 0x40UL /**< Bit mask for MODEM_TIMSEQINV */
+#define _MODEM_STATUS_TIMSEQINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS */
+#define MODEM_STATUS_TIMSEQINV_DEFAULT (_MODEM_STATUS_TIMSEQINV_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_STATUS */
+#define MODEM_STATUS_TIMLOSTCAUSE (0x1UL << 7) /**< Timing Lost Cause */
+#define _MODEM_STATUS_TIMLOSTCAUSE_SHIFT 7 /**< Shift value for MODEM_TIMLOSTCAUSE */
+#define _MODEM_STATUS_TIMLOSTCAUSE_MASK 0x80UL /**< Bit mask for MODEM_TIMLOSTCAUSE */
+#define _MODEM_STATUS_TIMLOSTCAUSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS */
+#define _MODEM_STATUS_TIMLOSTCAUSE_LOWCORR 0x00000000UL /**< Mode LOWCORR for MODEM_STATUS */
+#define _MODEM_STATUS_TIMLOSTCAUSE_TIMEOUT 0x00000001UL /**< Mode TIMEOUT for MODEM_STATUS */
+#define MODEM_STATUS_TIMLOSTCAUSE_DEFAULT (_MODEM_STATUS_TIMLOSTCAUSE_DEFAULT << 7) /**< Shifted mode DEFAULT for MODEM_STATUS */
+#define MODEM_STATUS_TIMLOSTCAUSE_LOWCORR (_MODEM_STATUS_TIMLOSTCAUSE_LOWCORR << 7) /**< Shifted mode LOWCORR for MODEM_STATUS */
+#define MODEM_STATUS_TIMLOSTCAUSE_TIMEOUT (_MODEM_STATUS_TIMLOSTCAUSE_TIMEOUT << 7) /**< Shifted mode TIMEOUT for MODEM_STATUS */
+#define MODEM_STATUS_DSADETECTED (0x1UL << 8) /**< PHASE-DSA detected */
+#define _MODEM_STATUS_DSADETECTED_SHIFT 8 /**< Shift value for MODEM_DSADETECTED */
+#define _MODEM_STATUS_DSADETECTED_MASK 0x100UL /**< Bit mask for MODEM_DSADETECTED */
+#define _MODEM_STATUS_DSADETECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS */
+#define MODEM_STATUS_DSADETECTED_DEFAULT (_MODEM_STATUS_DSADETECTED_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_STATUS */
+#define MODEM_STATUS_DSAFREQESTDONE (0x1UL << 9) /**< DSA frequency estimation complete */
+#define _MODEM_STATUS_DSAFREQESTDONE_SHIFT 9 /**< Shift value for MODEM_DSAFREQESTDONE */
+#define _MODEM_STATUS_DSAFREQESTDONE_MASK 0x200UL /**< Bit mask for MODEM_DSAFREQESTDONE */
+#define _MODEM_STATUS_DSAFREQESTDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS */
+#define MODEM_STATUS_DSAFREQESTDONE_DEFAULT (_MODEM_STATUS_DSAFREQESTDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_STATUS */
+#define MODEM_STATUS_VITERBIDEMODTIMDET (0x1UL << 10) /**< Viterbi Demod timing detected */
+#define _MODEM_STATUS_VITERBIDEMODTIMDET_SHIFT 10 /**< Shift value for MODEM_VITERBIDEMODTIMDET */
+#define _MODEM_STATUS_VITERBIDEMODTIMDET_MASK 0x400UL /**< Bit mask for MODEM_VITERBIDEMODTIMDET */
+#define _MODEM_STATUS_VITERBIDEMODTIMDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS */
+#define MODEM_STATUS_VITERBIDEMODTIMDET_DEFAULT (_MODEM_STATUS_VITERBIDEMODTIMDET_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_STATUS */
+#define MODEM_STATUS_VITERBIDEMODFRAMEDET (0x1UL << 11) /**< Viterbi Demod frame detected */
+#define _MODEM_STATUS_VITERBIDEMODFRAMEDET_SHIFT 11 /**< Shift value for MODEM_VITERBIDEMODFRAMEDET */
+#define _MODEM_STATUS_VITERBIDEMODFRAMEDET_MASK 0x800UL /**< Bit mask for MODEM_VITERBIDEMODFRAMEDET */
+#define _MODEM_STATUS_VITERBIDEMODFRAMEDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS */
+#define MODEM_STATUS_VITERBIDEMODFRAMEDET_DEFAULT (_MODEM_STATUS_VITERBIDEMODFRAMEDET_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_STATUS */
+#define _MODEM_STATUS_STAMPSTATE_SHIFT 12 /**< Shift value for MODEM_STAMPSTATE */
+#define _MODEM_STATUS_STAMPSTATE_MASK 0x7000UL /**< Bit mask for MODEM_STAMPSTATE */
+#define _MODEM_STATUS_STAMPSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS */
+#define MODEM_STATUS_STAMPSTATE_DEFAULT (_MODEM_STATUS_STAMPSTATE_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_STATUS */
+#define MODEM_STATUS_TRECSDSAADET (0x1UL << 15) /**< TRECS DSA DETECTION */
+#define _MODEM_STATUS_TRECSDSAADET_SHIFT 15 /**< Shift value for MODEM_TRECSDSAADET */
+#define _MODEM_STATUS_TRECSDSAADET_MASK 0x8000UL /**< Bit mask for MODEM_TRECSDSAADET */
+#define _MODEM_STATUS_TRECSDSAADET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS */
+#define MODEM_STATUS_TRECSDSAADET_DEFAULT (_MODEM_STATUS_TRECSDSAADET_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_STATUS */
+#define _MODEM_STATUS_CORR_SHIFT 16 /**< Shift value for MODEM_CORR */
+#define _MODEM_STATUS_CORR_MASK 0xFF0000UL /**< Bit mask for MODEM_CORR */
+#define _MODEM_STATUS_CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS */
+#define MODEM_STATUS_CORR_DEFAULT (_MODEM_STATUS_CORR_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_STATUS */
+#define _MODEM_STATUS_WEAKSYMBOLS_SHIFT 24 /**< Shift value for MODEM_WEAKSYMBOLS */
+#define _MODEM_STATUS_WEAKSYMBOLS_MASK 0xFF000000UL /**< Bit mask for MODEM_WEAKSYMBOLS */
+#define _MODEM_STATUS_WEAKSYMBOLS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS */
+#define MODEM_STATUS_WEAKSYMBOLS_DEFAULT (_MODEM_STATUS_WEAKSYMBOLS_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_STATUS */
+
+/* Bit fields for MODEM STATUS2 */
+#define _MODEM_STATUS2_RESETVALUE 0x00000000UL /**< Default value for MODEM_STATUS2 */
+#define _MODEM_STATUS2_MASK 0xFFFCFFFFUL /**< Mask for MODEM_STATUS2 */
+#define _MODEM_STATUS2_CHPWRACCUMUX_SHIFT 0 /**< Shift value for MODEM_CHPWRACCUMUX */
+#define _MODEM_STATUS2_CHPWRACCUMUX_MASK 0xFFUL /**< Bit mask for MODEM_CHPWRACCUMUX */
+#define _MODEM_STATUS2_CHPWRACCUMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS2 */
+#define MODEM_STATUS2_CHPWRACCUMUX_DEFAULT (_MODEM_STATUS2_CHPWRACCUMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_STATUS2 */
+#define _MODEM_STATUS2_BBSSMUX_SHIFT 8 /**< Shift value for MODEM_BBSSMUX */
+#define _MODEM_STATUS2_BBSSMUX_MASK 0xF00UL /**< Bit mask for MODEM_BBSSMUX */
+#define _MODEM_STATUS2_BBSSMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS2 */
+#define MODEM_STATUS2_BBSSMUX_DEFAULT (_MODEM_STATUS2_BBSSMUX_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_STATUS2 */
+#define _MODEM_STATUS2_LRBLECI_SHIFT 12 /**< Shift value for MODEM_LRBLECI */
+#define _MODEM_STATUS2_LRBLECI_MASK 0x3000UL /**< Bit mask for MODEM_LRBLECI */
+#define _MODEM_STATUS2_LRBLECI_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS2 */
+#define _MODEM_STATUS2_LRBLECI_LR125k 0x00000000UL /**< Mode LR125k for MODEM_STATUS2 */
+#define _MODEM_STATUS2_LRBLECI_LR500k 0x00000001UL /**< Mode LR500k for MODEM_STATUS2 */
+#define MODEM_STATUS2_LRBLECI_DEFAULT (_MODEM_STATUS2_LRBLECI_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_STATUS2 */
+#define MODEM_STATUS2_LRBLECI_LR125k (_MODEM_STATUS2_LRBLECI_LR125k << 12) /**< Shifted mode LR125k for MODEM_STATUS2 */
+#define MODEM_STATUS2_LRBLECI_LR500k (_MODEM_STATUS2_LRBLECI_LR500k << 12) /**< Shifted mode LR500k for MODEM_STATUS2 */
+#define MODEM_STATUS2_UNCODEDPHY (0x1UL << 14) /**< UNCODED PHY DET */
+#define _MODEM_STATUS2_UNCODEDPHY_SHIFT 14 /**< Shift value for MODEM_UNCODEDPHY */
+#define _MODEM_STATUS2_UNCODEDPHY_MASK 0x4000UL /**< Bit mask for MODEM_UNCODEDPHY */
+#define _MODEM_STATUS2_UNCODEDPHY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS2 */
+#define MODEM_STATUS2_UNCODEDPHY_DEFAULT (_MODEM_STATUS2_UNCODEDPHY_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_STATUS2 */
+#define MODEM_STATUS2_CODEDPHY (0x1UL << 15) /**< CODED PHY DET */
+#define _MODEM_STATUS2_CODEDPHY_SHIFT 15 /**< Shift value for MODEM_CODEDPHY */
+#define _MODEM_STATUS2_CODEDPHY_MASK 0x8000UL /**< Bit mask for MODEM_CODEDPHY */
+#define _MODEM_STATUS2_CODEDPHY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS2 */
+#define MODEM_STATUS2_CODEDPHY_DEFAULT (_MODEM_STATUS2_CODEDPHY_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_STATUS2 */
+#define _MODEM_STATUS2_RTCOST_SHIFT 18 /**< Shift value for MODEM_RTCOST */
+#define _MODEM_STATUS2_RTCOST_MASK 0xFFFC0000UL /**< Bit mask for MODEM_RTCOST */
+#define _MODEM_STATUS2_RTCOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS2 */
+#define MODEM_STATUS2_RTCOST_DEFAULT (_MODEM_STATUS2_RTCOST_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_STATUS2 */
+
+/* Bit fields for MODEM STATUS3 */
+#define _MODEM_STATUS3_RESETVALUE 0x00000000UL /**< Default value for MODEM_STATUS3 */
+#define _MODEM_STATUS3_MASK 0x0FFFFFFFUL /**< Mask for MODEM_STATUS3 */
+#define _MODEM_STATUS3_BBPFOUTABS1_SHIFT 0 /**< Shift value for MODEM_BBPFOUTABS1 */
+#define _MODEM_STATUS3_BBPFOUTABS1_MASK 0x7FFUL /**< Bit mask for MODEM_BBPFOUTABS1 */
+#define _MODEM_STATUS3_BBPFOUTABS1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS3 */
+#define MODEM_STATUS3_BBPFOUTABS1_DEFAULT (_MODEM_STATUS3_BBPFOUTABS1_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_STATUS3 */
+#define _MODEM_STATUS3_BBPFOUTABS_SHIFT 11 /**< Shift value for MODEM_BBPFOUTABS */
+#define _MODEM_STATUS3_BBPFOUTABS_MASK 0x3FF800UL /**< Bit mask for MODEM_BBPFOUTABS */
+#define _MODEM_STATUS3_BBPFOUTABS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS3 */
+#define MODEM_STATUS3_BBPFOUTABS_DEFAULT (_MODEM_STATUS3_BBPFOUTABS_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_STATUS3 */
+#define MODEM_STATUS3_LRDSALIVE (0x1UL << 22) /**< BLRDSA Prefilter above LRSPIKETHD */
+#define _MODEM_STATUS3_LRDSALIVE_SHIFT 22 /**< Shift value for MODEM_LRDSALIVE */
+#define _MODEM_STATUS3_LRDSALIVE_MASK 0x400000UL /**< Bit mask for MODEM_LRDSALIVE */
+#define _MODEM_STATUS3_LRDSALIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS3 */
+#define MODEM_STATUS3_LRDSALIVE_DEFAULT (_MODEM_STATUS3_LRDSALIVE_DEFAULT << 22) /**< Shifted mode DEFAULT for MODEM_STATUS3 */
+#define MODEM_STATUS3_COHDSALIVE (0x1UL << 23) /**< COHDSA Prefilter above CDTH */
+#define _MODEM_STATUS3_COHDSALIVE_SHIFT 23 /**< Shift value for MODEM_COHDSALIVE */
+#define _MODEM_STATUS3_COHDSALIVE_MASK 0x800000UL /**< Bit mask for MODEM_COHDSALIVE */
+#define _MODEM_STATUS3_COHDSALIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS3 */
+#define MODEM_STATUS3_COHDSALIVE_DEFAULT (_MODEM_STATUS3_COHDSALIVE_DEFAULT << 23) /**< Shifted mode DEFAULT for MODEM_STATUS3 */
+#define MODEM_STATUS3_LRDSADET (0x1UL << 24) /**< DSA prefilter above LRSPIKETHD */
+#define _MODEM_STATUS3_LRDSADET_SHIFT 24 /**< Shift value for MODEM_LRDSADET */
+#define _MODEM_STATUS3_LRDSADET_MASK 0x1000000UL /**< Bit mask for MODEM_LRDSADET */
+#define _MODEM_STATUS3_LRDSADET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS3 */
+#define MODEM_STATUS3_LRDSADET_DEFAULT (_MODEM_STATUS3_LRDSADET_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_STATUS3 */
+#define MODEM_STATUS3_COHDSADET (0x1UL << 25) /**< DSA prefilter above CDTH */
+#define _MODEM_STATUS3_COHDSADET_SHIFT 25 /**< Shift value for MODEM_COHDSADET */
+#define _MODEM_STATUS3_COHDSADET_MASK 0x2000000UL /**< Bit mask for MODEM_COHDSADET */
+#define _MODEM_STATUS3_COHDSADET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS3 */
+#define MODEM_STATUS3_COHDSADET_DEFAULT (_MODEM_STATUS3_COHDSADET_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_STATUS3 */
+#define MODEM_STATUS3_SYNCSECPEAKABTH (0x1UL << 26) /**< SYNC second peak above threshold */
+#define _MODEM_STATUS3_SYNCSECPEAKABTH_SHIFT 26 /**< Shift value for MODEM_SYNCSECPEAKABTH */
+#define _MODEM_STATUS3_SYNCSECPEAKABTH_MASK 0x4000000UL /**< Bit mask for MODEM_SYNCSECPEAKABTH */
+#define _MODEM_STATUS3_SYNCSECPEAKABTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS3 */
+#define MODEM_STATUS3_SYNCSECPEAKABTH_DEFAULT (_MODEM_STATUS3_SYNCSECPEAKABTH_DEFAULT << 26) /**< Shifted mode DEFAULT for MODEM_STATUS3 */
+#define MODEM_STATUS3_SOFTRSTDONE (0x1UL << 27) /**< Soft reset done */
+#define _MODEM_STATUS3_SOFTRSTDONE_SHIFT 27 /**< Shift value for MODEM_SOFTRSTDONE */
+#define _MODEM_STATUS3_SOFTRSTDONE_MASK 0x8000000UL /**< Bit mask for MODEM_SOFTRSTDONE */
+#define _MODEM_STATUS3_SOFTRSTDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS3 */
+#define MODEM_STATUS3_SOFTRSTDONE_DEFAULT (_MODEM_STATUS3_SOFTRSTDONE_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_STATUS3 */
+
+/* Bit fields for MODEM STATUS4 */
+#define _MODEM_STATUS4_RESETVALUE 0x00000000UL /**< Default value for MODEM_STATUS4 */
+#define _MODEM_STATUS4_MASK 0x01FF01FFUL /**< Mask for MODEM_STATUS4 */
+#define _MODEM_STATUS4_ANT0RSSI_SHIFT 0 /**< Shift value for MODEM_ANT0RSSI */
+#define _MODEM_STATUS4_ANT0RSSI_MASK 0x1FFUL /**< Bit mask for MODEM_ANT0RSSI */
+#define _MODEM_STATUS4_ANT0RSSI_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS4 */
+#define MODEM_STATUS4_ANT0RSSI_DEFAULT (_MODEM_STATUS4_ANT0RSSI_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_STATUS4 */
+#define _MODEM_STATUS4_ANT1RSSI_SHIFT 16 /**< Shift value for MODEM_ANT1RSSI */
+#define _MODEM_STATUS4_ANT1RSSI_MASK 0x1FF0000UL /**< Bit mask for MODEM_ANT1RSSI */
+#define _MODEM_STATUS4_ANT1RSSI_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS4 */
+#define MODEM_STATUS4_ANT1RSSI_DEFAULT (_MODEM_STATUS4_ANT1RSSI_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_STATUS4 */
+
+/* Bit fields for MODEM STATUS5 */
+#define _MODEM_STATUS5_RESETVALUE 0x00000000UL /**< Default value for MODEM_STATUS5 */
+#define _MODEM_STATUS5_MASK 0x000001FFUL /**< Mask for MODEM_STATUS5 */
+#define _MODEM_STATUS5_RXRESTARTMAFLTDOUT_SHIFT 0 /**< Shift value for MODEM_RXRESTARTMAFLTDOUT */
+#define _MODEM_STATUS5_RXRESTARTMAFLTDOUT_MASK 0x1FFUL /**< Bit mask for MODEM_RXRESTARTMAFLTDOUT */
+#define _MODEM_STATUS5_RXRESTARTMAFLTDOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS5 */
+#define MODEM_STATUS5_RXRESTARTMAFLTDOUT_DEFAULT (_MODEM_STATUS5_RXRESTARTMAFLTDOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_STATUS5 */
+
+/* Bit fields for MODEM STATUS6 */
+#define _MODEM_STATUS6_RESETVALUE 0x00000000UL /**< Default value for MODEM_STATUS6 */
+#define _MODEM_STATUS6_MASK 0xC00FFFFFUL /**< Mask for MODEM_STATUS6 */
+#define _MODEM_STATUS6_ANT0CORR_SHIFT 0 /**< Shift value for MODEM_ANT0CORR */
+#define _MODEM_STATUS6_ANT0CORR_MASK 0x3FFUL /**< Bit mask for MODEM_ANT0CORR */
+#define _MODEM_STATUS6_ANT0CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS6 */
+#define MODEM_STATUS6_ANT0CORR_DEFAULT (_MODEM_STATUS6_ANT0CORR_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_STATUS6 */
+#define _MODEM_STATUS6_ANT1CORR_SHIFT 10 /**< Shift value for MODEM_ANT1CORR */
+#define _MODEM_STATUS6_ANT1CORR_MASK 0xFFC00UL /**< Bit mask for MODEM_ANT1CORR */
+#define _MODEM_STATUS6_ANT1CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS6 */
+#define MODEM_STATUS6_ANT1CORR_DEFAULT (_MODEM_STATUS6_ANT1CORR_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_STATUS6 */
+#define MODEM_STATUS6_ANT0OUT (0x1UL << 30) /**< ANT0 OUTPUT */
+#define _MODEM_STATUS6_ANT0OUT_SHIFT 30 /**< Shift value for MODEM_ANT0OUT */
+#define _MODEM_STATUS6_ANT0OUT_MASK 0x40000000UL /**< Bit mask for MODEM_ANT0OUT */
+#define _MODEM_STATUS6_ANT0OUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS6 */
+#define MODEM_STATUS6_ANT0OUT_DEFAULT (_MODEM_STATUS6_ANT0OUT_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_STATUS6 */
+#define MODEM_STATUS6_ANT1OUT (0x1UL << 31) /**< ANT1 OUTPUT */
+#define _MODEM_STATUS6_ANT1OUT_SHIFT 31 /**< Shift value for MODEM_ANT1OUT */
+#define _MODEM_STATUS6_ANT1OUT_MASK 0x80000000UL /**< Bit mask for MODEM_ANT1OUT */
+#define _MODEM_STATUS6_ANT1OUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS6 */
+#define MODEM_STATUS6_ANT1OUT_DEFAULT (_MODEM_STATUS6_ANT1OUT_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_STATUS6 */
+
+/* Bit fields for MODEM STATUS7 */
+#define _MODEM_STATUS7_RESETVALUE 0x00000000UL /**< Default value for MODEM_STATUS7 */
+#define _MODEM_STATUS7_MASK 0xBFFFFFFFUL /**< Mask for MODEM_STATUS7 */
+#define _MODEM_STATUS7_FDEVEST_SHIFT 0 /**< Shift value for MODEM_FDEVEST */
+#define _MODEM_STATUS7_FDEVEST_MASK 0x3FUL /**< Bit mask for MODEM_FDEVEST */
+#define _MODEM_STATUS7_FDEVEST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS7 */
+#define MODEM_STATUS7_FDEVEST_DEFAULT (_MODEM_STATUS7_FDEVEST_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_STATUS7 */
+#define _MODEM_STATUS7_DEMODSOFT_SHIFT 6 /**< Shift value for MODEM_DEMODSOFT */
+#define _MODEM_STATUS7_DEMODSOFT_MASK 0x7FFC0UL /**< Bit mask for MODEM_DEMODSOFT */
+#define _MODEM_STATUS7_DEMODSOFT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS7 */
+#define MODEM_STATUS7_DEMODSOFT_DEFAULT (_MODEM_STATUS7_DEMODSOFT_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_STATUS7 */
+#define _MODEM_STATUS7_CFEPHDIFF_SHIFT 19 /**< Shift value for MODEM_CFEPHDIFF */
+#define _MODEM_STATUS7_CFEPHDIFF_MASK 0x1FF80000UL /**< Bit mask for MODEM_CFEPHDIFF */
+#define _MODEM_STATUS7_CFEPHDIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS7 */
+#define MODEM_STATUS7_CFEPHDIFF_DEFAULT (_MODEM_STATUS7_CFEPHDIFF_DEFAULT << 19) /**< Shifted mode DEFAULT for MODEM_STATUS7 */
+#define MODEM_STATUS7_MINCOSTPASS (0x1UL << 29) /**< Min.COST Threshold Pass */
+#define _MODEM_STATUS7_MINCOSTPASS_SHIFT 29 /**< Shift value for MODEM_MINCOSTPASS */
+#define _MODEM_STATUS7_MINCOSTPASS_MASK 0x20000000UL /**< Bit mask for MODEM_MINCOSTPASS */
+#define _MODEM_STATUS7_MINCOSTPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS7 */
+#define MODEM_STATUS7_MINCOSTPASS_DEFAULT (_MODEM_STATUS7_MINCOSTPASS_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_STATUS7 */
+#define MODEM_STATUS7_CFEDSADET (0x1UL << 31) /**< CFE-based DSA Detection */
+#define _MODEM_STATUS7_CFEDSADET_SHIFT 31 /**< Shift value for MODEM_CFEDSADET */
+#define _MODEM_STATUS7_CFEDSADET_MASK 0x80000000UL /**< Bit mask for MODEM_CFEDSADET */
+#define _MODEM_STATUS7_CFEDSADET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_STATUS7 */
+#define MODEM_STATUS7_CFEDSADET_DEFAULT (_MODEM_STATUS7_CFEDSADET_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_STATUS7 */
+
+/* Bit fields for MODEM TIMDETSTATUS */
+#define _MODEM_TIMDETSTATUS_RESETVALUE 0x00000000UL /**< Default value for MODEM_TIMDETSTATUS */
+#define _MODEM_TIMDETSTATUS_MASK 0x1F0FFFFFUL /**< Mask for MODEM_TIMDETSTATUS */
+#define _MODEM_TIMDETSTATUS_TIMDETCORR_SHIFT 0 /**< Shift value for MODEM_TIMDETCORR */
+#define _MODEM_TIMDETSTATUS_TIMDETCORR_MASK 0xFFUL /**< Bit mask for MODEM_TIMDETCORR */
+#define _MODEM_TIMDETSTATUS_TIMDETCORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TIMDETSTATUS */
+#define MODEM_TIMDETSTATUS_TIMDETCORR_DEFAULT (_MODEM_TIMDETSTATUS_TIMDETCORR_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_TIMDETSTATUS */
+#define _MODEM_TIMDETSTATUS_TIMDETFREQOFFEST_SHIFT 8 /**< Shift value for MODEM_TIMDETFREQOFFEST */
+#define _MODEM_TIMDETSTATUS_TIMDETFREQOFFEST_MASK 0xFF00UL /**< Bit mask for MODEM_TIMDETFREQOFFEST */
+#define _MODEM_TIMDETSTATUS_TIMDETFREQOFFEST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TIMDETSTATUS */
+#define MODEM_TIMDETSTATUS_TIMDETFREQOFFEST_DEFAULT (_MODEM_TIMDETSTATUS_TIMDETFREQOFFEST_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_TIMDETSTATUS */
+#define _MODEM_TIMDETSTATUS_TIMDETPREERRORS_SHIFT 16 /**< Shift value for MODEM_TIMDETPREERRORS */
+#define _MODEM_TIMDETSTATUS_TIMDETPREERRORS_MASK 0xF0000UL /**< Bit mask for MODEM_TIMDETPREERRORS */
+#define _MODEM_TIMDETSTATUS_TIMDETPREERRORS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TIMDETSTATUS */
+#define MODEM_TIMDETSTATUS_TIMDETPREERRORS_DEFAULT (_MODEM_TIMDETSTATUS_TIMDETPREERRORS_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_TIMDETSTATUS */
+#define MODEM_TIMDETSTATUS_TIMDETPASS (0x1UL << 24) /**< Timing detection pass */
+#define _MODEM_TIMDETSTATUS_TIMDETPASS_SHIFT 24 /**< Shift value for MODEM_TIMDETPASS */
+#define _MODEM_TIMDETSTATUS_TIMDETPASS_MASK 0x1000000UL /**< Bit mask for MODEM_TIMDETPASS */
+#define _MODEM_TIMDETSTATUS_TIMDETPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TIMDETSTATUS */
+#define MODEM_TIMDETSTATUS_TIMDETPASS_DEFAULT (_MODEM_TIMDETSTATUS_TIMDETPASS_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_TIMDETSTATUS */
+#define _MODEM_TIMDETSTATUS_TIMDETINDEX_SHIFT 25 /**< Shift value for MODEM_TIMDETINDEX */
+#define _MODEM_TIMDETSTATUS_TIMDETINDEX_MASK 0x1E000000UL /**< Bit mask for MODEM_TIMDETINDEX */
+#define _MODEM_TIMDETSTATUS_TIMDETINDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TIMDETSTATUS */
+#define MODEM_TIMDETSTATUS_TIMDETINDEX_DEFAULT (_MODEM_TIMDETSTATUS_TIMDETINDEX_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_TIMDETSTATUS */
+
+/* Bit fields for MODEM FSMSTATUS */
+#define _MODEM_FSMSTATUS_RESETVALUE 0x00000000UL /**< Default value for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_MASK 0x00FFFFFFUL /**< Mask for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_DETSTATE_SHIFT 0 /**< Shift value for MODEM_DETSTATE */
+#define _MODEM_FSMSTATUS_DETSTATE_MASK 0x7FUL /**< Bit mask for MODEM_DETSTATE */
+#define _MODEM_FSMSTATUS_DETSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_DETSTATE_OFF 0x00000000UL /**< Mode OFF for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_DETSTATE_TIMINGSEARCH 0x0000000AUL /**< Mode TIMINGSEARCH for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_DETSTATE_PRESEARCH 0x00000014UL /**< Mode PRESEARCH for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_DETSTATE_FRAMESEARCH 0x0000001EUL /**< Mode FRAMESEARCH for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_DETSTATE_RXFRAME 0x00000028UL /**< Mode RXFRAME for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_DETSTATE_FRAMEDETMODE0 0x00000032UL /**< Mode FRAMEDETMODE0 for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_DETSTATE_DEFAULT (_MODEM_FSMSTATUS_DETSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_DETSTATE_OFF (_MODEM_FSMSTATUS_DETSTATE_OFF << 0) /**< Shifted mode OFF for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_DETSTATE_TIMINGSEARCH (_MODEM_FSMSTATUS_DETSTATE_TIMINGSEARCH << 0) /**< Shifted mode TIMINGSEARCH for MODEM_FSMSTATUS*/
+#define MODEM_FSMSTATUS_DETSTATE_PRESEARCH (_MODEM_FSMSTATUS_DETSTATE_PRESEARCH << 0) /**< Shifted mode PRESEARCH for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_DETSTATE_FRAMESEARCH (_MODEM_FSMSTATUS_DETSTATE_FRAMESEARCH << 0) /**< Shifted mode FRAMESEARCH for MODEM_FSMSTATUS*/
+#define MODEM_FSMSTATUS_DETSTATE_RXFRAME (_MODEM_FSMSTATUS_DETSTATE_RXFRAME << 0) /**< Shifted mode RXFRAME for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_DETSTATE_FRAMEDETMODE0 (_MODEM_FSMSTATUS_DETSTATE_FRAMEDETMODE0 << 0) /**< Shifted mode FRAMEDETMODE0 for MODEM_FSMSTATUS*/
+#define _MODEM_FSMSTATUS_DSASTATE_SHIFT 7 /**< Shift value for MODEM_DSASTATE */
+#define _MODEM_FSMSTATUS_DSASTATE_MASK 0x380UL /**< Bit mask for MODEM_DSASTATE */
+#define _MODEM_FSMSTATUS_DSASTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_DSASTATE_IDLE 0x00000000UL /**< Mode IDLE for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_DSASTATE_ARRIVALCHK 0x00000001UL /**< Mode ARRIVALCHK for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_DSASTATE_STATUSCHK 0x00000002UL /**< Mode STATUSCHK for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_DSASTATE_SAMPPW 0x00000003UL /**< Mode SAMPPW for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_DSASTATE_WAITPWRUP 0x00000004UL /**< Mode WAITPWRUP for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_DSASTATE_WAITDSALO 0x00000005UL /**< Mode WAITDSALO for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_DSASTATE_WAITABORT 0x00000006UL /**< Mode WAITABORT for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_DSASTATE_STOP 0x00000007UL /**< Mode STOP for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_DSASTATE_DEFAULT (_MODEM_FSMSTATUS_DSASTATE_DEFAULT << 7) /**< Shifted mode DEFAULT for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_DSASTATE_IDLE (_MODEM_FSMSTATUS_DSASTATE_IDLE << 7) /**< Shifted mode IDLE for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_DSASTATE_ARRIVALCHK (_MODEM_FSMSTATUS_DSASTATE_ARRIVALCHK << 7) /**< Shifted mode ARRIVALCHK for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_DSASTATE_STATUSCHK (_MODEM_FSMSTATUS_DSASTATE_STATUSCHK << 7) /**< Shifted mode STATUSCHK for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_DSASTATE_SAMPPW (_MODEM_FSMSTATUS_DSASTATE_SAMPPW << 7) /**< Shifted mode SAMPPW for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_DSASTATE_WAITPWRUP (_MODEM_FSMSTATUS_DSASTATE_WAITPWRUP << 7) /**< Shifted mode WAITPWRUP for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_DSASTATE_WAITDSALO (_MODEM_FSMSTATUS_DSASTATE_WAITDSALO << 7) /**< Shifted mode WAITDSALO for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_DSASTATE_WAITABORT (_MODEM_FSMSTATUS_DSASTATE_WAITABORT << 7) /**< Shifted mode WAITABORT for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_DSASTATE_STOP (_MODEM_FSMSTATUS_DSASTATE_STOP << 7) /**< Shifted mode STOP for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_LRBLESTATE_SHIFT 10 /**< Shift value for MODEM_LRBLESTATE */
+#define _MODEM_FSMSTATUS_LRBLESTATE_MASK 0x7C00UL /**< Bit mask for MODEM_LRBLESTATE */
+#define _MODEM_FSMSTATUS_LRBLESTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_LRBLESTATE_IDLE 0x00000000UL /**< Mode IDLE for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_LRBLESTATE_CLEANUP 0x00000001UL /**< Mode CLEANUP for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_LRBLESTATE_CORRCOE 0x00000002UL /**< Mode CORRCOE for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_LRBLESTATE_WAITLRDSA 0x00000003UL /**< Mode WAITLRDSA for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_LRBLESTATE_MAXCORR 0x00000004UL /**< Mode MAXCORR for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_LRBLESTATE_WAITRDY 0x00000005UL /**< Mode WAITRDY for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_LRBLESTATE_FEC1DATA 0x00000006UL /**< Mode FEC1DATA for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_LRBLESTATE_FEC1ACK 0x00000007UL /**< Mode FEC1ACK for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_LRBLESTATE_PAUSE 0x00000008UL /**< Mode PAUSE for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_LRBLESTATE_FEC2DATA 0x00000009UL /**< Mode FEC2DATA for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_LRBLESTATE_FEC2ACK 0x0000000AUL /**< Mode FEC2ACK for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_LRBLESTATE_TRACKCUR 0x0000000BUL /**< Mode TRACKCUR for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_LRBLESTATE_TRACKEAR 0x0000000CUL /**< Mode TRACKEAR for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_LRBLESTATE_TRACKLAT 0x0000000DUL /**< Mode TRACKLAT for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_LRBLESTATE_TRACKDONE 0x0000000EUL /**< Mode TRACKDONE for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_LRBLESTATE_TDECISION 0x0000000FUL /**< Mode TDECISION for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_LRBLESTATE_STOP 0x00000010UL /**< Mode STOP for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_LRBLESTATE_DEFAULT (_MODEM_FSMSTATUS_LRBLESTATE_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_LRBLESTATE_IDLE (_MODEM_FSMSTATUS_LRBLESTATE_IDLE << 10) /**< Shifted mode IDLE for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_LRBLESTATE_CLEANUP (_MODEM_FSMSTATUS_LRBLESTATE_CLEANUP << 10) /**< Shifted mode CLEANUP for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_LRBLESTATE_CORRCOE (_MODEM_FSMSTATUS_LRBLESTATE_CORRCOE << 10) /**< Shifted mode CORRCOE for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_LRBLESTATE_WAITLRDSA (_MODEM_FSMSTATUS_LRBLESTATE_WAITLRDSA << 10) /**< Shifted mode WAITLRDSA for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_LRBLESTATE_MAXCORR (_MODEM_FSMSTATUS_LRBLESTATE_MAXCORR << 10) /**< Shifted mode MAXCORR for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_LRBLESTATE_WAITRDY (_MODEM_FSMSTATUS_LRBLESTATE_WAITRDY << 10) /**< Shifted mode WAITRDY for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_LRBLESTATE_FEC1DATA (_MODEM_FSMSTATUS_LRBLESTATE_FEC1DATA << 10) /**< Shifted mode FEC1DATA for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_LRBLESTATE_FEC1ACK (_MODEM_FSMSTATUS_LRBLESTATE_FEC1ACK << 10) /**< Shifted mode FEC1ACK for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_LRBLESTATE_PAUSE (_MODEM_FSMSTATUS_LRBLESTATE_PAUSE << 10) /**< Shifted mode PAUSE for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_LRBLESTATE_FEC2DATA (_MODEM_FSMSTATUS_LRBLESTATE_FEC2DATA << 10) /**< Shifted mode FEC2DATA for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_LRBLESTATE_FEC2ACK (_MODEM_FSMSTATUS_LRBLESTATE_FEC2ACK << 10) /**< Shifted mode FEC2ACK for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_LRBLESTATE_TRACKCUR (_MODEM_FSMSTATUS_LRBLESTATE_TRACKCUR << 10) /**< Shifted mode TRACKCUR for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_LRBLESTATE_TRACKEAR (_MODEM_FSMSTATUS_LRBLESTATE_TRACKEAR << 10) /**< Shifted mode TRACKEAR for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_LRBLESTATE_TRACKLAT (_MODEM_FSMSTATUS_LRBLESTATE_TRACKLAT << 10) /**< Shifted mode TRACKLAT for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_LRBLESTATE_TRACKDONE (_MODEM_FSMSTATUS_LRBLESTATE_TRACKDONE << 10) /**< Shifted mode TRACKDONE for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_LRBLESTATE_TDECISION (_MODEM_FSMSTATUS_LRBLESTATE_TDECISION << 10) /**< Shifted mode TDECISION for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_LRBLESTATE_STOP (_MODEM_FSMSTATUS_LRBLESTATE_STOP << 10) /**< Shifted mode STOP for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_NBBLESTATE_SHIFT 15 /**< Shift value for MODEM_NBBLESTATE */
+#define _MODEM_FSMSTATUS_NBBLESTATE_MASK 0xF8000UL /**< Bit mask for MODEM_NBBLESTATE */
+#define _MODEM_FSMSTATUS_NBBLESTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_NBBLESTATE_IDLE 0x00000000UL /**< Mode IDLE for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_NBBLESTATE_VTINITI 0x00000001UL /**< Mode VTINITI for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_NBBLESTATE_ADDRNXT 0x00000002UL /**< Mode ADDRNXT for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_NBBLESTATE_INICOST 0x00000003UL /**< Mode INICOST for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_NBBLESTATE_CALCCOST 0x00000004UL /**< Mode CALCCOST for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_NBBLESTATE_INITALACQU 0x00000005UL /**< Mode INITALACQU for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_NBBLESTATE_INITALCOSTCALC 0x00000006UL /**< Mode INITALCOSTCALC for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_NBBLESTATE_MINCOSTCALC 0x00000007UL /**< Mode MINCOSTCALC for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_NBBLESTATE_FREQACQU 0x00000008UL /**< Mode FREQACQU for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_NBBLESTATE_FREQACQUDONE 0x00000009UL /**< Mode FREQACQUDONE for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_NBBLESTATE_TIMINGACQUEARLY 0x0000000AUL /**< Mode TIMINGACQUEARLY for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_NBBLESTATE_TIMINGACQUCURR 0x0000000BUL /**< Mode TIMINGACQUCURR for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_NBBLESTATE_TIMINGACQULATE 0x0000000CUL /**< Mode TIMINGACQULATE for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_NBBLESTATE_TIMINGACQUDONE 0x0000000DUL /**< Mode TIMINGACQUDONE for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_NBBLESTATE_VIRTBIINIT0 0x0000000EUL /**< Mode VIRTBIINIT0 for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_NBBLESTATE_VIRTBIINIT1 0x0000000FUL /**< Mode VIRTBIINIT1 for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_NBBLESTATE_VIRTBIRXSYNC 0x00000010UL /**< Mode VIRTBIRXSYNC for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_NBBLESTATE_VIRTBIRXPAYLOAD 0x00000011UL /**< Mode VIRTBIRXPAYLOAD for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_NBBLESTATE_HARDRXSYNC 0x00000012UL /**< Mode HARDRXSYNC for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_NBBLESTATE_HARDXPAYLOAD 0x00000013UL /**< Mode HARDXPAYLOAD for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_NBBLESTATE_TRACKFREQ 0x00000014UL /**< Mode TRACKFREQ for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_NBBLESTATE_TRACKTIMEARLY 0x00000015UL /**< Mode TRACKTIMEARLY for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_NBBLESTATE_TRACKTIMCURR 0x00000016UL /**< Mode TRACKTIMCURR for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_NBBLESTATE_TRACKTIMLATE 0x00000017UL /**< Mode TRACKTIMLATE for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_NBBLESTATE_TRACKDONE 0x00000018UL /**< Mode TRACKDONE for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_NBBLESTATE_TRACKDECISION 0x00000019UL /**< Mode TRACKDECISION for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_NBBLESTATE_STOP 0x0000001AUL /**< Mode STOP for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_NBBLESTATE_WAITACK 0x0000001BUL /**< Mode WAITACK for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_NBBLESTATE_DEBUG 0x0000001CUL /**< Mode DEBUG for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_NBBLESTATE_DEFAULT (_MODEM_FSMSTATUS_NBBLESTATE_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_NBBLESTATE_IDLE (_MODEM_FSMSTATUS_NBBLESTATE_IDLE << 15) /**< Shifted mode IDLE for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_NBBLESTATE_VTINITI (_MODEM_FSMSTATUS_NBBLESTATE_VTINITI << 15) /**< Shifted mode VTINITI for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_NBBLESTATE_ADDRNXT (_MODEM_FSMSTATUS_NBBLESTATE_ADDRNXT << 15) /**< Shifted mode ADDRNXT for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_NBBLESTATE_INICOST (_MODEM_FSMSTATUS_NBBLESTATE_INICOST << 15) /**< Shifted mode INICOST for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_NBBLESTATE_CALCCOST (_MODEM_FSMSTATUS_NBBLESTATE_CALCCOST << 15) /**< Shifted mode CALCCOST for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_NBBLESTATE_INITALACQU (_MODEM_FSMSTATUS_NBBLESTATE_INITALACQU << 15) /**< Shifted mode INITALACQU for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_NBBLESTATE_INITALCOSTCALC (_MODEM_FSMSTATUS_NBBLESTATE_INITALCOSTCALC << 15) /**< Shifted mode INITALCOSTCALC for MODEM_FSMSTATUS*/
+#define MODEM_FSMSTATUS_NBBLESTATE_MINCOSTCALC (_MODEM_FSMSTATUS_NBBLESTATE_MINCOSTCALC << 15) /**< Shifted mode MINCOSTCALC for MODEM_FSMSTATUS*/
+#define MODEM_FSMSTATUS_NBBLESTATE_FREQACQU (_MODEM_FSMSTATUS_NBBLESTATE_FREQACQU << 15) /**< Shifted mode FREQACQU for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_NBBLESTATE_FREQACQUDONE (_MODEM_FSMSTATUS_NBBLESTATE_FREQACQUDONE << 15) /**< Shifted mode FREQACQUDONE for MODEM_FSMSTATUS*/
+#define MODEM_FSMSTATUS_NBBLESTATE_TIMINGACQUEARLY (_MODEM_FSMSTATUS_NBBLESTATE_TIMINGACQUEARLY << 15) /**< Shifted mode TIMINGACQUEARLY for MODEM_FSMSTATUS*/
+#define MODEM_FSMSTATUS_NBBLESTATE_TIMINGACQUCURR (_MODEM_FSMSTATUS_NBBLESTATE_TIMINGACQUCURR << 15) /**< Shifted mode TIMINGACQUCURR for MODEM_FSMSTATUS*/
+#define MODEM_FSMSTATUS_NBBLESTATE_TIMINGACQULATE (_MODEM_FSMSTATUS_NBBLESTATE_TIMINGACQULATE << 15) /**< Shifted mode TIMINGACQULATE for MODEM_FSMSTATUS*/
+#define MODEM_FSMSTATUS_NBBLESTATE_TIMINGACQUDONE (_MODEM_FSMSTATUS_NBBLESTATE_TIMINGACQUDONE << 15) /**< Shifted mode TIMINGACQUDONE for MODEM_FSMSTATUS*/
+#define MODEM_FSMSTATUS_NBBLESTATE_VIRTBIINIT0 (_MODEM_FSMSTATUS_NBBLESTATE_VIRTBIINIT0 << 15) /**< Shifted mode VIRTBIINIT0 for MODEM_FSMSTATUS*/
+#define MODEM_FSMSTATUS_NBBLESTATE_VIRTBIINIT1 (_MODEM_FSMSTATUS_NBBLESTATE_VIRTBIINIT1 << 15) /**< Shifted mode VIRTBIINIT1 for MODEM_FSMSTATUS*/
+#define MODEM_FSMSTATUS_NBBLESTATE_VIRTBIRXSYNC (_MODEM_FSMSTATUS_NBBLESTATE_VIRTBIRXSYNC << 15) /**< Shifted mode VIRTBIRXSYNC for MODEM_FSMSTATUS*/
+#define MODEM_FSMSTATUS_NBBLESTATE_VIRTBIRXPAYLOAD (_MODEM_FSMSTATUS_NBBLESTATE_VIRTBIRXPAYLOAD << 15) /**< Shifted mode VIRTBIRXPAYLOAD for MODEM_FSMSTATUS*/
+#define MODEM_FSMSTATUS_NBBLESTATE_HARDRXSYNC (_MODEM_FSMSTATUS_NBBLESTATE_HARDRXSYNC << 15) /**< Shifted mode HARDRXSYNC for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_NBBLESTATE_HARDXPAYLOAD (_MODEM_FSMSTATUS_NBBLESTATE_HARDXPAYLOAD << 15) /**< Shifted mode HARDXPAYLOAD for MODEM_FSMSTATUS*/
+#define MODEM_FSMSTATUS_NBBLESTATE_TRACKFREQ (_MODEM_FSMSTATUS_NBBLESTATE_TRACKFREQ << 15) /**< Shifted mode TRACKFREQ for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_NBBLESTATE_TRACKTIMEARLY (_MODEM_FSMSTATUS_NBBLESTATE_TRACKTIMEARLY << 15) /**< Shifted mode TRACKTIMEARLY for MODEM_FSMSTATUS*/
+#define MODEM_FSMSTATUS_NBBLESTATE_TRACKTIMCURR (_MODEM_FSMSTATUS_NBBLESTATE_TRACKTIMCURR << 15) /**< Shifted mode TRACKTIMCURR for MODEM_FSMSTATUS*/
+#define MODEM_FSMSTATUS_NBBLESTATE_TRACKTIMLATE (_MODEM_FSMSTATUS_NBBLESTATE_TRACKTIMLATE << 15) /**< Shifted mode TRACKTIMLATE for MODEM_FSMSTATUS*/
+#define MODEM_FSMSTATUS_NBBLESTATE_TRACKDONE (_MODEM_FSMSTATUS_NBBLESTATE_TRACKDONE << 15) /**< Shifted mode TRACKDONE for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_NBBLESTATE_TRACKDECISION (_MODEM_FSMSTATUS_NBBLESTATE_TRACKDECISION << 15) /**< Shifted mode TRACKDECISION for MODEM_FSMSTATUS*/
+#define MODEM_FSMSTATUS_NBBLESTATE_STOP (_MODEM_FSMSTATUS_NBBLESTATE_STOP << 15) /**< Shifted mode STOP for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_NBBLESTATE_WAITACK (_MODEM_FSMSTATUS_NBBLESTATE_WAITACK << 15) /**< Shifted mode WAITACK for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_NBBLESTATE_DEBUG (_MODEM_FSMSTATUS_NBBLESTATE_DEBUG << 15) /**< Shifted mode DEBUG for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_ANTDIVSTATE_SHIFT 20 /**< Shift value for MODEM_ANTDIVSTATE */
+#define _MODEM_FSMSTATUS_ANTDIVSTATE_MASK 0xF00000UL /**< Bit mask for MODEM_ANTDIVSTATE */
+#define _MODEM_FSMSTATUS_ANTDIVSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_ANTDIVSTATE_IDLE 0x00000000UL /**< Mode IDLE for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_ANTDIVSTATE_FIRST_ANT0 0x00000001UL /**< Mode FIRST_ANT0 for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_ANTDIVSTATE_FIRST_ANT1 0x00000002UL /**< Mode FIRST_ANT1 for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_ANTDIVSTATE_TIMSEARCH_ANT0 0x00000003UL /**< Mode TIMSEARCH_ANT0 for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_ANTDIVSTATE_TIMSEARCH_ANT1 0x00000004UL /**< Mode TIMSEARCH_ANT1 for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_ANTDIVSTATE_TIMDET_ANT0 0x00000005UL /**< Mode TIMDET_ANT0 for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_ANTDIVSTATE_TIMDET_ANT1 0x00000006UL /**< Mode TIMDET_ANT1 for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_ANTDIVSTATE_EVALUATE 0x00000007UL /**< Mode EVALUATE for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_ANTDIVSTATE_TIMSEARCH_SELECTED 0x00000008UL /**< Mode TIMSEARCH_SELECTED for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_ANTDIVSTATE_TIMDET_SELECTED 0x00000009UL /**< Mode TIMDET_SELECTED for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_ANTDIVSTATE_REPEAT_ANT0 0x0000000AUL /**< Mode REPEAT_ANT0 for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_ANTDIVSTATE_REPEAT_ANT1 0x0000000BUL /**< Mode REPEAT_ANT1 for MODEM_FSMSTATUS */
+#define _MODEM_FSMSTATUS_ANTDIVSTATE_MANUAL 0x0000000FUL /**< Mode MANUAL for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_ANTDIVSTATE_DEFAULT (_MODEM_FSMSTATUS_ANTDIVSTATE_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_ANTDIVSTATE_IDLE (_MODEM_FSMSTATUS_ANTDIVSTATE_IDLE << 20) /**< Shifted mode IDLE for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_ANTDIVSTATE_FIRST_ANT0 (_MODEM_FSMSTATUS_ANTDIVSTATE_FIRST_ANT0 << 20) /**< Shifted mode FIRST_ANT0 for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_ANTDIVSTATE_FIRST_ANT1 (_MODEM_FSMSTATUS_ANTDIVSTATE_FIRST_ANT1 << 20) /**< Shifted mode FIRST_ANT1 for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_ANTDIVSTATE_TIMSEARCH_ANT0 (_MODEM_FSMSTATUS_ANTDIVSTATE_TIMSEARCH_ANT0 << 20) /**< Shifted mode TIMSEARCH_ANT0 for MODEM_FSMSTATUS*/
+#define MODEM_FSMSTATUS_ANTDIVSTATE_TIMSEARCH_ANT1 (_MODEM_FSMSTATUS_ANTDIVSTATE_TIMSEARCH_ANT1 << 20) /**< Shifted mode TIMSEARCH_ANT1 for MODEM_FSMSTATUS*/
+#define MODEM_FSMSTATUS_ANTDIVSTATE_TIMDET_ANT0 (_MODEM_FSMSTATUS_ANTDIVSTATE_TIMDET_ANT0 << 20) /**< Shifted mode TIMDET_ANT0 for MODEM_FSMSTATUS*/
+#define MODEM_FSMSTATUS_ANTDIVSTATE_TIMDET_ANT1 (_MODEM_FSMSTATUS_ANTDIVSTATE_TIMDET_ANT1 << 20) /**< Shifted mode TIMDET_ANT1 for MODEM_FSMSTATUS*/
+#define MODEM_FSMSTATUS_ANTDIVSTATE_EVALUATE (_MODEM_FSMSTATUS_ANTDIVSTATE_EVALUATE << 20) /**< Shifted mode EVALUATE for MODEM_FSMSTATUS */
+#define MODEM_FSMSTATUS_ANTDIVSTATE_TIMSEARCH_SELECTED (_MODEM_FSMSTATUS_ANTDIVSTATE_TIMSEARCH_SELECTED << 20) /**< Shifted mode TIMSEARCH_SELECTED for MODEM_FSMSTATUS*/
+#define MODEM_FSMSTATUS_ANTDIVSTATE_TIMDET_SELECTED (_MODEM_FSMSTATUS_ANTDIVSTATE_TIMDET_SELECTED << 20) /**< Shifted mode TIMDET_SELECTED for MODEM_FSMSTATUS*/
+#define MODEM_FSMSTATUS_ANTDIVSTATE_REPEAT_ANT0 (_MODEM_FSMSTATUS_ANTDIVSTATE_REPEAT_ANT0 << 20) /**< Shifted mode REPEAT_ANT0 for MODEM_FSMSTATUS*/
+#define MODEM_FSMSTATUS_ANTDIVSTATE_REPEAT_ANT1 (_MODEM_FSMSTATUS_ANTDIVSTATE_REPEAT_ANT1 << 20) /**< Shifted mode REPEAT_ANT1 for MODEM_FSMSTATUS*/
+#define MODEM_FSMSTATUS_ANTDIVSTATE_MANUAL (_MODEM_FSMSTATUS_ANTDIVSTATE_MANUAL << 20) /**< Shifted mode MANUAL for MODEM_FSMSTATUS */
+
+/* Bit fields for MODEM FREQOFFEST */
+#define _MODEM_FREQOFFEST_RESETVALUE 0x00000000UL /**< Default value for MODEM_FREQOFFEST */
+#define _MODEM_FREQOFFEST_MASK 0xFFFFFFFFUL /**< Mask for MODEM_FREQOFFEST */
+#define _MODEM_FREQOFFEST_FREQOFFEST_SHIFT 0 /**< Shift value for MODEM_FREQOFFEST */
+#define _MODEM_FREQOFFEST_FREQOFFEST_MASK 0x1FFFUL /**< Bit mask for MODEM_FREQOFFEST */
+#define _MODEM_FREQOFFEST_FREQOFFEST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_FREQOFFEST */
+#define MODEM_FREQOFFEST_FREQOFFEST_DEFAULT (_MODEM_FREQOFFEST_FREQOFFEST_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_FREQOFFEST */
+#define _MODEM_FREQOFFEST_CORRVAL_SHIFT 13 /**< Shift value for MODEM_CORRVAL */
+#define _MODEM_FREQOFFEST_CORRVAL_MASK 0xFFE000UL /**< Bit mask for MODEM_CORRVAL */
+#define _MODEM_FREQOFFEST_CORRVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_FREQOFFEST */
+#define MODEM_FREQOFFEST_CORRVAL_DEFAULT (_MODEM_FREQOFFEST_CORRVAL_DEFAULT << 13) /**< Shifted mode DEFAULT for MODEM_FREQOFFEST */
+#define _MODEM_FREQOFFEST_SOFTVAL_SHIFT 24 /**< Shift value for MODEM_SOFTVAL */
+#define _MODEM_FREQOFFEST_SOFTVAL_MASK 0xFF000000UL /**< Bit mask for MODEM_SOFTVAL */
+#define _MODEM_FREQOFFEST_SOFTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_FREQOFFEST */
+#define MODEM_FREQOFFEST_SOFTVAL_DEFAULT (_MODEM_FREQOFFEST_SOFTVAL_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_FREQOFFEST */
+
+/* Bit fields for MODEM AFCADJRX */
+#define _MODEM_AFCADJRX_RESETVALUE 0x00000000UL /**< Default value for MODEM_AFCADJRX */
+#define _MODEM_AFCADJRX_MASK 0xF1F7FFFFUL /**< Mask for MODEM_AFCADJRX */
+#define _MODEM_AFCADJRX_AFCADJRX_SHIFT 0 /**< Shift value for MODEM_AFCADJRX */
+#define _MODEM_AFCADJRX_AFCADJRX_MASK 0x7FFFFUL /**< Bit mask for MODEM_AFCADJRX */
+#define _MODEM_AFCADJRX_AFCADJRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFCADJRX */
+#define MODEM_AFCADJRX_AFCADJRX_DEFAULT (_MODEM_AFCADJRX_AFCADJRX_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_AFCADJRX */
+#define _MODEM_AFCADJRX_AFCSCALEM_SHIFT 20 /**< Shift value for MODEM_AFCSCALEM */
+#define _MODEM_AFCADJRX_AFCSCALEM_MASK 0x1F00000UL /**< Bit mask for MODEM_AFCSCALEM */
+#define _MODEM_AFCADJRX_AFCSCALEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFCADJRX */
+#define MODEM_AFCADJRX_AFCSCALEM_DEFAULT (_MODEM_AFCADJRX_AFCSCALEM_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_AFCADJRX */
+#define _MODEM_AFCADJRX_AFCSCALEE_SHIFT 28 /**< Shift value for MODEM_AFCSCALEE */
+#define _MODEM_AFCADJRX_AFCSCALEE_MASK 0xF0000000UL /**< Bit mask for MODEM_AFCSCALEE */
+#define _MODEM_AFCADJRX_AFCSCALEE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFCADJRX */
+#define MODEM_AFCADJRX_AFCSCALEE_DEFAULT (_MODEM_AFCADJRX_AFCSCALEE_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_AFCADJRX */
+
+/* Bit fields for MODEM AFCADJTX */
+#define _MODEM_AFCADJTX_RESETVALUE 0x00000000UL /**< Default value for MODEM_AFCADJTX */
+#define _MODEM_AFCADJTX_MASK 0xF1F7FFFFUL /**< Mask for MODEM_AFCADJTX */
+#define _MODEM_AFCADJTX_AFCADJTX_SHIFT 0 /**< Shift value for MODEM_AFCADJTX */
+#define _MODEM_AFCADJTX_AFCADJTX_MASK 0x7FFFFUL /**< Bit mask for MODEM_AFCADJTX */
+#define _MODEM_AFCADJTX_AFCADJTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFCADJTX */
+#define MODEM_AFCADJTX_AFCADJTX_DEFAULT (_MODEM_AFCADJTX_AFCADJTX_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_AFCADJTX */
+#define _MODEM_AFCADJTX_AFCSCALEM_SHIFT 20 /**< Shift value for MODEM_AFCSCALEM */
+#define _MODEM_AFCADJTX_AFCSCALEM_MASK 0x1F00000UL /**< Bit mask for MODEM_AFCSCALEM */
+#define _MODEM_AFCADJTX_AFCSCALEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFCADJTX */
+#define MODEM_AFCADJTX_AFCSCALEM_DEFAULT (_MODEM_AFCADJTX_AFCSCALEM_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_AFCADJTX */
+#define _MODEM_AFCADJTX_AFCSCALEE_SHIFT 28 /**< Shift value for MODEM_AFCSCALEE */
+#define _MODEM_AFCADJTX_AFCSCALEE_MASK 0xF0000000UL /**< Bit mask for MODEM_AFCSCALEE */
+#define _MODEM_AFCADJTX_AFCSCALEE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFCADJTX */
+#define MODEM_AFCADJTX_AFCSCALEE_DEFAULT (_MODEM_AFCADJTX_AFCSCALEE_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_AFCADJTX */
+
+/* Bit fields for MODEM MIXCTRL */
+#define _MODEM_MIXCTRL_RESETVALUE 0x00000000UL /**< Default value for MODEM_MIXCTRL */
+#define _MODEM_MIXCTRL_MASK 0x00000010UL /**< Mask for MODEM_MIXCTRL */
+#define MODEM_MIXCTRL_DIGIQSWAPEN (0x1UL << 4) /**< Digital I/Q swap enable */
+#define _MODEM_MIXCTRL_DIGIQSWAPEN_SHIFT 4 /**< Shift value for MODEM_DIGIQSWAPEN */
+#define _MODEM_MIXCTRL_DIGIQSWAPEN_MASK 0x10UL /**< Bit mask for MODEM_DIGIQSWAPEN */
+#define _MODEM_MIXCTRL_DIGIQSWAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_MIXCTRL */
+#define MODEM_MIXCTRL_DIGIQSWAPEN_DEFAULT (_MODEM_MIXCTRL_DIGIQSWAPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_MIXCTRL */
+
+/* Bit fields for MODEM CTRL0 */
+#define _MODEM_CTRL0_RESETVALUE 0x00000000UL /**< Default value for MODEM_CTRL0 */
+#define _MODEM_CTRL0_MASK 0xFFFFFFFFUL /**< Mask for MODEM_CTRL0 */
+#define MODEM_CTRL0_FDM0DIFFDIS (0x1UL << 0) /**< Frame Detection Mode 0 disable */
+#define _MODEM_CTRL0_FDM0DIFFDIS_SHIFT 0 /**< Shift value for MODEM_FDM0DIFFDIS */
+#define _MODEM_CTRL0_FDM0DIFFDIS_MASK 0x1UL /**< Bit mask for MODEM_FDM0DIFFDIS */
+#define _MODEM_CTRL0_FDM0DIFFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL0 */
+#define MODEM_CTRL0_FDM0DIFFDIS_DEFAULT (_MODEM_CTRL0_FDM0DIFFDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CTRL0 */
+#define _MODEM_CTRL0_MAPFSK_SHIFT 1 /**< Shift value for MODEM_MAPFSK */
+#define _MODEM_CTRL0_MAPFSK_MASK 0xEUL /**< Bit mask for MODEM_MAPFSK */
+#define _MODEM_CTRL0_MAPFSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL0 */
+#define _MODEM_CTRL0_MAPFSK_MAP0 0x00000000UL /**< Mode MAP0 for MODEM_CTRL0 */
+#define _MODEM_CTRL0_MAPFSK_MAP1 0x00000001UL /**< Mode MAP1 for MODEM_CTRL0 */
+#define _MODEM_CTRL0_MAPFSK_MAP2 0x00000002UL /**< Mode MAP2 for MODEM_CTRL0 */
+#define _MODEM_CTRL0_MAPFSK_MAP3 0x00000003UL /**< Mode MAP3 for MODEM_CTRL0 */
+#define _MODEM_CTRL0_MAPFSK_MAP4 0x00000004UL /**< Mode MAP4 for MODEM_CTRL0 */
+#define _MODEM_CTRL0_MAPFSK_MAP5 0x00000005UL /**< Mode MAP5 for MODEM_CTRL0 */
+#define _MODEM_CTRL0_MAPFSK_MAP6 0x00000006UL /**< Mode MAP6 for MODEM_CTRL0 */
+#define _MODEM_CTRL0_MAPFSK_MAP7 0x00000007UL /**< Mode MAP7 for MODEM_CTRL0 */
+#define MODEM_CTRL0_MAPFSK_DEFAULT (_MODEM_CTRL0_MAPFSK_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_CTRL0 */
+#define MODEM_CTRL0_MAPFSK_MAP0 (_MODEM_CTRL0_MAPFSK_MAP0 << 1) /**< Shifted mode MAP0 for MODEM_CTRL0 */
+#define MODEM_CTRL0_MAPFSK_MAP1 (_MODEM_CTRL0_MAPFSK_MAP1 << 1) /**< Shifted mode MAP1 for MODEM_CTRL0 */
+#define MODEM_CTRL0_MAPFSK_MAP2 (_MODEM_CTRL0_MAPFSK_MAP2 << 1) /**< Shifted mode MAP2 for MODEM_CTRL0 */
+#define MODEM_CTRL0_MAPFSK_MAP3 (_MODEM_CTRL0_MAPFSK_MAP3 << 1) /**< Shifted mode MAP3 for MODEM_CTRL0 */
+#define MODEM_CTRL0_MAPFSK_MAP4 (_MODEM_CTRL0_MAPFSK_MAP4 << 1) /**< Shifted mode MAP4 for MODEM_CTRL0 */
+#define MODEM_CTRL0_MAPFSK_MAP5 (_MODEM_CTRL0_MAPFSK_MAP5 << 1) /**< Shifted mode MAP5 for MODEM_CTRL0 */
+#define MODEM_CTRL0_MAPFSK_MAP6 (_MODEM_CTRL0_MAPFSK_MAP6 << 1) /**< Shifted mode MAP6 for MODEM_CTRL0 */
+#define MODEM_CTRL0_MAPFSK_MAP7 (_MODEM_CTRL0_MAPFSK_MAP7 << 1) /**< Shifted mode MAP7 for MODEM_CTRL0 */
+#define _MODEM_CTRL0_CODING_SHIFT 4 /**< Shift value for MODEM_CODING */
+#define _MODEM_CTRL0_CODING_MASK 0x30UL /**< Bit mask for MODEM_CODING */
+#define _MODEM_CTRL0_CODING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL0 */
+#define _MODEM_CTRL0_CODING_NRZ 0x00000000UL /**< Mode NRZ for MODEM_CTRL0 */
+#define _MODEM_CTRL0_CODING_MANCHESTER 0x00000001UL /**< Mode MANCHESTER for MODEM_CTRL0 */
+#define _MODEM_CTRL0_CODING_DSSS 0x00000002UL /**< Mode DSSS for MODEM_CTRL0 */
+#define _MODEM_CTRL0_CODING_LINECODE 0x00000003UL /**< Mode LINECODE for MODEM_CTRL0 */
+#define MODEM_CTRL0_CODING_DEFAULT (_MODEM_CTRL0_CODING_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_CTRL0 */
+#define MODEM_CTRL0_CODING_NRZ (_MODEM_CTRL0_CODING_NRZ << 4) /**< Shifted mode NRZ for MODEM_CTRL0 */
+#define MODEM_CTRL0_CODING_MANCHESTER (_MODEM_CTRL0_CODING_MANCHESTER << 4) /**< Shifted mode MANCHESTER for MODEM_CTRL0 */
+#define MODEM_CTRL0_CODING_DSSS (_MODEM_CTRL0_CODING_DSSS << 4) /**< Shifted mode DSSS for MODEM_CTRL0 */
+#define MODEM_CTRL0_CODING_LINECODE (_MODEM_CTRL0_CODING_LINECODE << 4) /**< Shifted mode LINECODE for MODEM_CTRL0 */
+#define _MODEM_CTRL0_MODFORMAT_SHIFT 6 /**< Shift value for MODEM_MODFORMAT */
+#define _MODEM_CTRL0_MODFORMAT_MASK 0x1C0UL /**< Bit mask for MODEM_MODFORMAT */
+#define _MODEM_CTRL0_MODFORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL0 */
+#define _MODEM_CTRL0_MODFORMAT_FSK2 0x00000000UL /**< Mode FSK2 for MODEM_CTRL0 */
+#define _MODEM_CTRL0_MODFORMAT_FSK4 0x00000001UL /**< Mode FSK4 for MODEM_CTRL0 */
+#define _MODEM_CTRL0_MODFORMAT_BPSK 0x00000002UL /**< Mode BPSK for MODEM_CTRL0 */
+#define _MODEM_CTRL0_MODFORMAT_DBPSK 0x00000003UL /**< Mode DBPSK for MODEM_CTRL0 */
+#define _MODEM_CTRL0_MODFORMAT_OQPSK 0x00000004UL /**< Mode OQPSK for MODEM_CTRL0 */
+#define _MODEM_CTRL0_MODFORMAT_MSK 0x00000005UL /**< Mode MSK for MODEM_CTRL0 */
+#define _MODEM_CTRL0_MODFORMAT_OOKASK 0x00000006UL /**< Mode OOKASK for MODEM_CTRL0 */
+#define MODEM_CTRL0_MODFORMAT_DEFAULT (_MODEM_CTRL0_MODFORMAT_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_CTRL0 */
+#define MODEM_CTRL0_MODFORMAT_FSK2 (_MODEM_CTRL0_MODFORMAT_FSK2 << 6) /**< Shifted mode FSK2 for MODEM_CTRL0 */
+#define MODEM_CTRL0_MODFORMAT_FSK4 (_MODEM_CTRL0_MODFORMAT_FSK4 << 6) /**< Shifted mode FSK4 for MODEM_CTRL0 */
+#define MODEM_CTRL0_MODFORMAT_BPSK (_MODEM_CTRL0_MODFORMAT_BPSK << 6) /**< Shifted mode BPSK for MODEM_CTRL0 */
+#define MODEM_CTRL0_MODFORMAT_DBPSK (_MODEM_CTRL0_MODFORMAT_DBPSK << 6) /**< Shifted mode DBPSK for MODEM_CTRL0 */
+#define MODEM_CTRL0_MODFORMAT_OQPSK (_MODEM_CTRL0_MODFORMAT_OQPSK << 6) /**< Shifted mode OQPSK for MODEM_CTRL0 */
+#define MODEM_CTRL0_MODFORMAT_MSK (_MODEM_CTRL0_MODFORMAT_MSK << 6) /**< Shifted mode MSK for MODEM_CTRL0 */
+#define MODEM_CTRL0_MODFORMAT_OOKASK (_MODEM_CTRL0_MODFORMAT_OOKASK << 6) /**< Shifted mode OOKASK for MODEM_CTRL0 */
+#define MODEM_CTRL0_DUALCORROPTDIS (0x1UL << 9) /**< Dual Correlation Optimization Disable */
+#define _MODEM_CTRL0_DUALCORROPTDIS_SHIFT 9 /**< Shift value for MODEM_DUALCORROPTDIS */
+#define _MODEM_CTRL0_DUALCORROPTDIS_MASK 0x200UL /**< Bit mask for MODEM_DUALCORROPTDIS */
+#define _MODEM_CTRL0_DUALCORROPTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL0 */
+#define MODEM_CTRL0_DUALCORROPTDIS_DEFAULT (_MODEM_CTRL0_DUALCORROPTDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_CTRL0 */
+#define MODEM_CTRL0_OOKASYNCPIN (0x1UL << 10) /**< OOK asynchronous pin mode */
+#define _MODEM_CTRL0_OOKASYNCPIN_SHIFT 10 /**< Shift value for MODEM_OOKASYNCPIN */
+#define _MODEM_CTRL0_OOKASYNCPIN_MASK 0x400UL /**< Bit mask for MODEM_OOKASYNCPIN */
+#define _MODEM_CTRL0_OOKASYNCPIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL0 */
+#define MODEM_CTRL0_OOKASYNCPIN_DEFAULT (_MODEM_CTRL0_OOKASYNCPIN_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_CTRL0 */
+#define _MODEM_CTRL0_DSSSLEN_SHIFT 11 /**< Shift value for MODEM_DSSSLEN */
+#define _MODEM_CTRL0_DSSSLEN_MASK 0xF800UL /**< Bit mask for MODEM_DSSSLEN */
+#define _MODEM_CTRL0_DSSSLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL0 */
+#define MODEM_CTRL0_DSSSLEN_DEFAULT (_MODEM_CTRL0_DSSSLEN_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_CTRL0 */
+#define _MODEM_CTRL0_DSSSSHIFTS_SHIFT 16 /**< Shift value for MODEM_DSSSSHIFTS */
+#define _MODEM_CTRL0_DSSSSHIFTS_MASK 0x70000UL /**< Bit mask for MODEM_DSSSSHIFTS */
+#define _MODEM_CTRL0_DSSSSHIFTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL0 */
+#define _MODEM_CTRL0_DSSSSHIFTS_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for MODEM_CTRL0 */
+#define _MODEM_CTRL0_DSSSSHIFTS_SHIFT1 0x00000001UL /**< Mode SHIFT1 for MODEM_CTRL0 */
+#define _MODEM_CTRL0_DSSSSHIFTS_SHIFT2 0x00000002UL /**< Mode SHIFT2 for MODEM_CTRL0 */
+#define _MODEM_CTRL0_DSSSSHIFTS_SHIFT4 0x00000003UL /**< Mode SHIFT4 for MODEM_CTRL0 */
+#define _MODEM_CTRL0_DSSSSHIFTS_SHIFT8 0x00000004UL /**< Mode SHIFT8 for MODEM_CTRL0 */
+#define _MODEM_CTRL0_DSSSSHIFTS_SHIFT16 0x00000005UL /**< Mode SHIFT16 for MODEM_CTRL0 */
+#define MODEM_CTRL0_DSSSSHIFTS_DEFAULT (_MODEM_CTRL0_DSSSSHIFTS_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_CTRL0 */
+#define MODEM_CTRL0_DSSSSHIFTS_NOSHIFT (_MODEM_CTRL0_DSSSSHIFTS_NOSHIFT << 16) /**< Shifted mode NOSHIFT for MODEM_CTRL0 */
+#define MODEM_CTRL0_DSSSSHIFTS_SHIFT1 (_MODEM_CTRL0_DSSSSHIFTS_SHIFT1 << 16) /**< Shifted mode SHIFT1 for MODEM_CTRL0 */
+#define MODEM_CTRL0_DSSSSHIFTS_SHIFT2 (_MODEM_CTRL0_DSSSSHIFTS_SHIFT2 << 16) /**< Shifted mode SHIFT2 for MODEM_CTRL0 */
+#define MODEM_CTRL0_DSSSSHIFTS_SHIFT4 (_MODEM_CTRL0_DSSSSHIFTS_SHIFT4 << 16) /**< Shifted mode SHIFT4 for MODEM_CTRL0 */
+#define MODEM_CTRL0_DSSSSHIFTS_SHIFT8 (_MODEM_CTRL0_DSSSSHIFTS_SHIFT8 << 16) /**< Shifted mode SHIFT8 for MODEM_CTRL0 */
+#define MODEM_CTRL0_DSSSSHIFTS_SHIFT16 (_MODEM_CTRL0_DSSSSHIFTS_SHIFT16 << 16) /**< Shifted mode SHIFT16 for MODEM_CTRL0 */
+#define _MODEM_CTRL0_DSSSDOUBLE_SHIFT 19 /**< Shift value for MODEM_DSSSDOUBLE */
+#define _MODEM_CTRL0_DSSSDOUBLE_MASK 0x180000UL /**< Bit mask for MODEM_DSSSDOUBLE */
+#define _MODEM_CTRL0_DSSSDOUBLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL0 */
+#define _MODEM_CTRL0_DSSSDOUBLE_DIS 0x00000000UL /**< Mode DIS for MODEM_CTRL0 */
+#define _MODEM_CTRL0_DSSSDOUBLE_INV 0x00000001UL /**< Mode INV for MODEM_CTRL0 */
+#define _MODEM_CTRL0_DSSSDOUBLE_CONJ 0x00000002UL /**< Mode CONJ for MODEM_CTRL0 */
+#define MODEM_CTRL0_DSSSDOUBLE_DEFAULT (_MODEM_CTRL0_DSSSDOUBLE_DEFAULT << 19) /**< Shifted mode DEFAULT for MODEM_CTRL0 */
+#define MODEM_CTRL0_DSSSDOUBLE_DIS (_MODEM_CTRL0_DSSSDOUBLE_DIS << 19) /**< Shifted mode DIS for MODEM_CTRL0 */
+#define MODEM_CTRL0_DSSSDOUBLE_INV (_MODEM_CTRL0_DSSSDOUBLE_INV << 19) /**< Shifted mode INV for MODEM_CTRL0 */
+#define MODEM_CTRL0_DSSSDOUBLE_CONJ (_MODEM_CTRL0_DSSSDOUBLE_CONJ << 19) /**< Shifted mode CONJ for MODEM_CTRL0 */
+#define MODEM_CTRL0_DETDIS (0x1UL << 21) /**< Detection disable */
+#define _MODEM_CTRL0_DETDIS_SHIFT 21 /**< Shift value for MODEM_DETDIS */
+#define _MODEM_CTRL0_DETDIS_MASK 0x200000UL /**< Bit mask for MODEM_DETDIS */
+#define _MODEM_CTRL0_DETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL0 */
+#define MODEM_CTRL0_DETDIS_DEFAULT (_MODEM_CTRL0_DETDIS_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_CTRL0 */
+#define _MODEM_CTRL0_DIFFENCMODE_SHIFT 22 /**< Shift value for MODEM_DIFFENCMODE */
+#define _MODEM_CTRL0_DIFFENCMODE_MASK 0x1C00000UL /**< Bit mask for MODEM_DIFFENCMODE */
+#define _MODEM_CTRL0_DIFFENCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL0 */
+#define _MODEM_CTRL0_DIFFENCMODE_DIS 0x00000000UL /**< Mode DIS for MODEM_CTRL0 */
+#define _MODEM_CTRL0_DIFFENCMODE_RR0 0x00000001UL /**< Mode RR0 for MODEM_CTRL0 */
+#define _MODEM_CTRL0_DIFFENCMODE_RE0 0x00000002UL /**< Mode RE0 for MODEM_CTRL0 */
+#define _MODEM_CTRL0_DIFFENCMODE_RR1 0x00000003UL /**< Mode RR1 for MODEM_CTRL0 */
+#define _MODEM_CTRL0_DIFFENCMODE_RE1 0x00000004UL /**< Mode RE1 for MODEM_CTRL0 */
+#define MODEM_CTRL0_DIFFENCMODE_DEFAULT (_MODEM_CTRL0_DIFFENCMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for MODEM_CTRL0 */
+#define MODEM_CTRL0_DIFFENCMODE_DIS (_MODEM_CTRL0_DIFFENCMODE_DIS << 22) /**< Shifted mode DIS for MODEM_CTRL0 */
+#define MODEM_CTRL0_DIFFENCMODE_RR0 (_MODEM_CTRL0_DIFFENCMODE_RR0 << 22) /**< Shifted mode RR0 for MODEM_CTRL0 */
+#define MODEM_CTRL0_DIFFENCMODE_RE0 (_MODEM_CTRL0_DIFFENCMODE_RE0 << 22) /**< Shifted mode RE0 for MODEM_CTRL0 */
+#define MODEM_CTRL0_DIFFENCMODE_RR1 (_MODEM_CTRL0_DIFFENCMODE_RR1 << 22) /**< Shifted mode RR1 for MODEM_CTRL0 */
+#define MODEM_CTRL0_DIFFENCMODE_RE1 (_MODEM_CTRL0_DIFFENCMODE_RE1 << 22) /**< Shifted mode RE1 for MODEM_CTRL0 */
+#define _MODEM_CTRL0_SHAPING_SHIFT 25 /**< Shift value for MODEM_SHAPING */
+#define _MODEM_CTRL0_SHAPING_MASK 0x6000000UL /**< Bit mask for MODEM_SHAPING */
+#define _MODEM_CTRL0_SHAPING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL0 */
+#define _MODEM_CTRL0_SHAPING_DISABLED 0x00000000UL /**< Mode DISABLED for MODEM_CTRL0 */
+#define _MODEM_CTRL0_SHAPING_ODDLENGTH 0x00000001UL /**< Mode ODDLENGTH for MODEM_CTRL0 */
+#define _MODEM_CTRL0_SHAPING_EVENLENGTH 0x00000002UL /**< Mode EVENLENGTH for MODEM_CTRL0 */
+#define _MODEM_CTRL0_SHAPING_ASYMMETRIC 0x00000003UL /**< Mode ASYMMETRIC for MODEM_CTRL0 */
+#define MODEM_CTRL0_SHAPING_DEFAULT (_MODEM_CTRL0_SHAPING_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_CTRL0 */
+#define MODEM_CTRL0_SHAPING_DISABLED (_MODEM_CTRL0_SHAPING_DISABLED << 25) /**< Shifted mode DISABLED for MODEM_CTRL0 */
+#define MODEM_CTRL0_SHAPING_ODDLENGTH (_MODEM_CTRL0_SHAPING_ODDLENGTH << 25) /**< Shifted mode ODDLENGTH for MODEM_CTRL0 */
+#define MODEM_CTRL0_SHAPING_EVENLENGTH (_MODEM_CTRL0_SHAPING_EVENLENGTH << 25) /**< Shifted mode EVENLENGTH for MODEM_CTRL0 */
+#define MODEM_CTRL0_SHAPING_ASYMMETRIC (_MODEM_CTRL0_SHAPING_ASYMMETRIC << 25) /**< Shifted mode ASYMMETRIC for MODEM_CTRL0 */
+#define _MODEM_CTRL0_DEMODRAWDATASEL_SHIFT 27 /**< Shift value for MODEM_DEMODRAWDATASEL */
+#define _MODEM_CTRL0_DEMODRAWDATASEL_MASK 0x38000000UL /**< Bit mask for MODEM_DEMODRAWDATASEL */
+#define _MODEM_CTRL0_DEMODRAWDATASEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL0 */
+#define _MODEM_CTRL0_DEMODRAWDATASEL_DIS 0x00000000UL /**< Mode DIS for MODEM_CTRL0 */
+#define _MODEM_CTRL0_DEMODRAWDATASEL_ENTROPY 0x00000001UL /**< Mode ENTROPY for MODEM_CTRL0 */
+#define _MODEM_CTRL0_DEMODRAWDATASEL_ADC 0x00000002UL /**< Mode ADC for MODEM_CTRL0 */
+#define _MODEM_CTRL0_DEMODRAWDATASEL_FILTLSB 0x00000003UL /**< Mode FILTLSB for MODEM_CTRL0 */
+#define _MODEM_CTRL0_DEMODRAWDATASEL_FILTMSB 0x00000004UL /**< Mode FILTMSB for MODEM_CTRL0 */
+#define _MODEM_CTRL0_DEMODRAWDATASEL_FILTFULL 0x00000005UL /**< Mode FILTFULL for MODEM_CTRL0 */
+#define _MODEM_CTRL0_DEMODRAWDATASEL_FREQ 0x00000006UL /**< Mode FREQ for MODEM_CTRL0 */
+#define _MODEM_CTRL0_DEMODRAWDATASEL_DEMOD 0x00000007UL /**< Mode DEMOD for MODEM_CTRL0 */
+#define MODEM_CTRL0_DEMODRAWDATASEL_DEFAULT (_MODEM_CTRL0_DEMODRAWDATASEL_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_CTRL0 */
+#define MODEM_CTRL0_DEMODRAWDATASEL_DIS (_MODEM_CTRL0_DEMODRAWDATASEL_DIS << 27) /**< Shifted mode DIS for MODEM_CTRL0 */
+#define MODEM_CTRL0_DEMODRAWDATASEL_ENTROPY (_MODEM_CTRL0_DEMODRAWDATASEL_ENTROPY << 27) /**< Shifted mode ENTROPY for MODEM_CTRL0 */
+#define MODEM_CTRL0_DEMODRAWDATASEL_ADC (_MODEM_CTRL0_DEMODRAWDATASEL_ADC << 27) /**< Shifted mode ADC for MODEM_CTRL0 */
+#define MODEM_CTRL0_DEMODRAWDATASEL_FILTLSB (_MODEM_CTRL0_DEMODRAWDATASEL_FILTLSB << 27) /**< Shifted mode FILTLSB for MODEM_CTRL0 */
+#define MODEM_CTRL0_DEMODRAWDATASEL_FILTMSB (_MODEM_CTRL0_DEMODRAWDATASEL_FILTMSB << 27) /**< Shifted mode FILTMSB for MODEM_CTRL0 */
+#define MODEM_CTRL0_DEMODRAWDATASEL_FILTFULL (_MODEM_CTRL0_DEMODRAWDATASEL_FILTFULL << 27) /**< Shifted mode FILTFULL for MODEM_CTRL0 */
+#define MODEM_CTRL0_DEMODRAWDATASEL_FREQ (_MODEM_CTRL0_DEMODRAWDATASEL_FREQ << 27) /**< Shifted mode FREQ for MODEM_CTRL0 */
+#define MODEM_CTRL0_DEMODRAWDATASEL_DEMOD (_MODEM_CTRL0_DEMODRAWDATASEL_DEMOD << 27) /**< Shifted mode DEMOD for MODEM_CTRL0 */
+#define _MODEM_CTRL0_FRAMEDETDEL_SHIFT 30 /**< Shift value for MODEM_FRAMEDETDEL */
+#define _MODEM_CTRL0_FRAMEDETDEL_MASK 0xC0000000UL /**< Bit mask for MODEM_FRAMEDETDEL */
+#define _MODEM_CTRL0_FRAMEDETDEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL0 */
+#define _MODEM_CTRL0_FRAMEDETDEL_DEL0 0x00000000UL /**< Mode DEL0 for MODEM_CTRL0 */
+#define _MODEM_CTRL0_FRAMEDETDEL_DEL8 0x00000001UL /**< Mode DEL8 for MODEM_CTRL0 */
+#define _MODEM_CTRL0_FRAMEDETDEL_DEL16 0x00000002UL /**< Mode DEL16 for MODEM_CTRL0 */
+#define _MODEM_CTRL0_FRAMEDETDEL_DEL32 0x00000003UL /**< Mode DEL32 for MODEM_CTRL0 */
+#define MODEM_CTRL0_FRAMEDETDEL_DEFAULT (_MODEM_CTRL0_FRAMEDETDEL_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_CTRL0 */
+#define MODEM_CTRL0_FRAMEDETDEL_DEL0 (_MODEM_CTRL0_FRAMEDETDEL_DEL0 << 30) /**< Shifted mode DEL0 for MODEM_CTRL0 */
+#define MODEM_CTRL0_FRAMEDETDEL_DEL8 (_MODEM_CTRL0_FRAMEDETDEL_DEL8 << 30) /**< Shifted mode DEL8 for MODEM_CTRL0 */
+#define MODEM_CTRL0_FRAMEDETDEL_DEL16 (_MODEM_CTRL0_FRAMEDETDEL_DEL16 << 30) /**< Shifted mode DEL16 for MODEM_CTRL0 */
+#define MODEM_CTRL0_FRAMEDETDEL_DEL32 (_MODEM_CTRL0_FRAMEDETDEL_DEL32 << 30) /**< Shifted mode DEL32 for MODEM_CTRL0 */
+
+/* Bit fields for MODEM CTRL1 */
+#define _MODEM_CTRL1_RESETVALUE 0x00000000UL /**< Default value for MODEM_CTRL1 */
+#define _MODEM_CTRL1_MASK 0xFFFFDFFFUL /**< Mask for MODEM_CTRL1 */
+#define _MODEM_CTRL1_SYNCBITS_SHIFT 0 /**< Shift value for MODEM_SYNCBITS */
+#define _MODEM_CTRL1_SYNCBITS_MASK 0x1FUL /**< Bit mask for MODEM_SYNCBITS */
+#define _MODEM_CTRL1_SYNCBITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL1 */
+#define MODEM_CTRL1_SYNCBITS_DEFAULT (_MODEM_CTRL1_SYNCBITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CTRL1 */
+#define _MODEM_CTRL1_SYNCERRORS_SHIFT 5 /**< Shift value for MODEM_SYNCERRORS */
+#define _MODEM_CTRL1_SYNCERRORS_MASK 0x1E0UL /**< Bit mask for MODEM_SYNCERRORS */
+#define _MODEM_CTRL1_SYNCERRORS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL1 */
+#define MODEM_CTRL1_SYNCERRORS_DEFAULT (_MODEM_CTRL1_SYNCERRORS_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_CTRL1 */
+#define MODEM_CTRL1_DUALSYNC (0x1UL << 9) /**< Dual sync words. */
+#define _MODEM_CTRL1_DUALSYNC_SHIFT 9 /**< Shift value for MODEM_DUALSYNC */
+#define _MODEM_CTRL1_DUALSYNC_MASK 0x200UL /**< Bit mask for MODEM_DUALSYNC */
+#define _MODEM_CTRL1_DUALSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL1 */
+#define _MODEM_CTRL1_DUALSYNC_DISABLED 0x00000000UL /**< Mode DISABLED for MODEM_CTRL1 */
+#define _MODEM_CTRL1_DUALSYNC_ENABLED 0x00000001UL /**< Mode ENABLED for MODEM_CTRL1 */
+#define MODEM_CTRL1_DUALSYNC_DEFAULT (_MODEM_CTRL1_DUALSYNC_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_CTRL1 */
+#define MODEM_CTRL1_DUALSYNC_DISABLED (_MODEM_CTRL1_DUALSYNC_DISABLED << 9) /**< Shifted mode DISABLED for MODEM_CTRL1 */
+#define MODEM_CTRL1_DUALSYNC_ENABLED (_MODEM_CTRL1_DUALSYNC_ENABLED << 9) /**< Shifted mode ENABLED for MODEM_CTRL1 */
+#define MODEM_CTRL1_TXSYNC (0x1UL << 10) /**< Transmit sync word. */
+#define _MODEM_CTRL1_TXSYNC_SHIFT 10 /**< Shift value for MODEM_TXSYNC */
+#define _MODEM_CTRL1_TXSYNC_MASK 0x400UL /**< Bit mask for MODEM_TXSYNC */
+#define _MODEM_CTRL1_TXSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL1 */
+#define _MODEM_CTRL1_TXSYNC_SYNC0 0x00000000UL /**< Mode SYNC0 for MODEM_CTRL1 */
+#define _MODEM_CTRL1_TXSYNC_SYNC1 0x00000001UL /**< Mode SYNC1 for MODEM_CTRL1 */
+#define MODEM_CTRL1_TXSYNC_DEFAULT (_MODEM_CTRL1_TXSYNC_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_CTRL1 */
+#define MODEM_CTRL1_TXSYNC_SYNC0 (_MODEM_CTRL1_TXSYNC_SYNC0 << 10) /**< Shifted mode SYNC0 for MODEM_CTRL1 */
+#define MODEM_CTRL1_TXSYNC_SYNC1 (_MODEM_CTRL1_TXSYNC_SYNC1 << 10) /**< Shifted mode SYNC1 for MODEM_CTRL1 */
+#define MODEM_CTRL1_SYNCDATA (0x1UL << 11) /**< Sync data. */
+#define _MODEM_CTRL1_SYNCDATA_SHIFT 11 /**< Shift value for MODEM_SYNCDATA */
+#define _MODEM_CTRL1_SYNCDATA_MASK 0x800UL /**< Bit mask for MODEM_SYNCDATA */
+#define _MODEM_CTRL1_SYNCDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL1 */
+#define _MODEM_CTRL1_SYNCDATA_DISABLED 0x00000000UL /**< Mode DISABLED for MODEM_CTRL1 */
+#define _MODEM_CTRL1_SYNCDATA_ENABLED 0x00000001UL /**< Mode ENABLED for MODEM_CTRL1 */
+#define MODEM_CTRL1_SYNCDATA_DEFAULT (_MODEM_CTRL1_SYNCDATA_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_CTRL1 */
+#define MODEM_CTRL1_SYNCDATA_DISABLED (_MODEM_CTRL1_SYNCDATA_DISABLED << 11) /**< Shifted mode DISABLED for MODEM_CTRL1 */
+#define MODEM_CTRL1_SYNCDATA_ENABLED (_MODEM_CTRL1_SYNCDATA_ENABLED << 11) /**< Shifted mode ENABLED for MODEM_CTRL1 */
+#define MODEM_CTRL1_SYNC1INV (0x1UL << 12) /**< SYNC1 invert. */
+#define _MODEM_CTRL1_SYNC1INV_SHIFT 12 /**< Shift value for MODEM_SYNC1INV */
+#define _MODEM_CTRL1_SYNC1INV_MASK 0x1000UL /**< Bit mask for MODEM_SYNC1INV */
+#define _MODEM_CTRL1_SYNC1INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL1 */
+#define MODEM_CTRL1_SYNC1INV_DEFAULT (_MODEM_CTRL1_SYNC1INV_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_CTRL1 */
+#define _MODEM_CTRL1_COMPMODE_SHIFT 14 /**< Shift value for MODEM_COMPMODE */
+#define _MODEM_CTRL1_COMPMODE_MASK 0xC000UL /**< Bit mask for MODEM_COMPMODE */
+#define _MODEM_CTRL1_COMPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL1 */
+#define _MODEM_CTRL1_COMPMODE_DIS 0x00000000UL /**< Mode DIS for MODEM_CTRL1 */
+#define _MODEM_CTRL1_COMPMODE_PRELOCK 0x00000001UL /**< Mode PRELOCK for MODEM_CTRL1 */
+#define _MODEM_CTRL1_COMPMODE_FRAMELOCK 0x00000002UL /**< Mode FRAMELOCK for MODEM_CTRL1 */
+#define _MODEM_CTRL1_COMPMODE_NOLOCK 0x00000003UL /**< Mode NOLOCK for MODEM_CTRL1 */
+#define MODEM_CTRL1_COMPMODE_DEFAULT (_MODEM_CTRL1_COMPMODE_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_CTRL1 */
+#define MODEM_CTRL1_COMPMODE_DIS (_MODEM_CTRL1_COMPMODE_DIS << 14) /**< Shifted mode DIS for MODEM_CTRL1 */
+#define MODEM_CTRL1_COMPMODE_PRELOCK (_MODEM_CTRL1_COMPMODE_PRELOCK << 14) /**< Shifted mode PRELOCK for MODEM_CTRL1 */
+#define MODEM_CTRL1_COMPMODE_FRAMELOCK (_MODEM_CTRL1_COMPMODE_FRAMELOCK << 14) /**< Shifted mode FRAMELOCK for MODEM_CTRL1 */
+#define MODEM_CTRL1_COMPMODE_NOLOCK (_MODEM_CTRL1_COMPMODE_NOLOCK << 14) /**< Shifted mode NOLOCK for MODEM_CTRL1 */
+#define _MODEM_CTRL1_RESYNCPER_SHIFT 16 /**< Shift value for MODEM_RESYNCPER */
+#define _MODEM_CTRL1_RESYNCPER_MASK 0xF0000UL /**< Bit mask for MODEM_RESYNCPER */
+#define _MODEM_CTRL1_RESYNCPER_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL1 */
+#define MODEM_CTRL1_RESYNCPER_DEFAULT (_MODEM_CTRL1_RESYNCPER_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_CTRL1 */
+#define _MODEM_CTRL1_PHASEDEMOD_SHIFT 20 /**< Shift value for MODEM_PHASEDEMOD */
+#define _MODEM_CTRL1_PHASEDEMOD_MASK 0x300000UL /**< Bit mask for MODEM_PHASEDEMOD */
+#define _MODEM_CTRL1_PHASEDEMOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL1 */
+#define _MODEM_CTRL1_PHASEDEMOD_BDD 0x00000000UL /**< Mode BDD for MODEM_CTRL1 */
+#define _MODEM_CTRL1_PHASEDEMOD_MBDD 0x00000001UL /**< Mode MBDD for MODEM_CTRL1 */
+#define _MODEM_CTRL1_PHASEDEMOD_COH 0x00000002UL /**< Mode COH for MODEM_CTRL1 */
+#define MODEM_CTRL1_PHASEDEMOD_DEFAULT (_MODEM_CTRL1_PHASEDEMOD_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_CTRL1 */
+#define MODEM_CTRL1_PHASEDEMOD_BDD (_MODEM_CTRL1_PHASEDEMOD_BDD << 20) /**< Shifted mode BDD for MODEM_CTRL1 */
+#define MODEM_CTRL1_PHASEDEMOD_MBDD (_MODEM_CTRL1_PHASEDEMOD_MBDD << 20) /**< Shifted mode MBDD for MODEM_CTRL1 */
+#define MODEM_CTRL1_PHASEDEMOD_COH (_MODEM_CTRL1_PHASEDEMOD_COH << 20) /**< Shifted mode COH for MODEM_CTRL1 */
+#define _MODEM_CTRL1_FREQOFFESTPER_SHIFT 22 /**< Shift value for MODEM_FREQOFFESTPER */
+#define _MODEM_CTRL1_FREQOFFESTPER_MASK 0x1C00000UL /**< Bit mask for MODEM_FREQOFFESTPER */
+#define _MODEM_CTRL1_FREQOFFESTPER_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL1 */
+#define MODEM_CTRL1_FREQOFFESTPER_DEFAULT (_MODEM_CTRL1_FREQOFFESTPER_DEFAULT << 22) /**< Shifted mode DEFAULT for MODEM_CTRL1 */
+#define _MODEM_CTRL1_FREQOFFESTLIM_SHIFT 25 /**< Shift value for MODEM_FREQOFFESTLIM */
+#define _MODEM_CTRL1_FREQOFFESTLIM_MASK 0xFE000000UL /**< Bit mask for MODEM_FREQOFFESTLIM */
+#define _MODEM_CTRL1_FREQOFFESTLIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL1 */
+#define MODEM_CTRL1_FREQOFFESTLIM_DEFAULT (_MODEM_CTRL1_FREQOFFESTLIM_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_CTRL1 */
+
+/* Bit fields for MODEM CTRL2 */
+#define _MODEM_CTRL2_RESETVALUE 0x00001000UL /**< Default value for MODEM_CTRL2 */
+#define _MODEM_CTRL2_MASK 0xFFFFFFFFUL /**< Mask for MODEM_CTRL2 */
+#define _MODEM_CTRL2_SQITHRESH_SHIFT 0 /**< Shift value for MODEM_SQITHRESH */
+#define _MODEM_CTRL2_SQITHRESH_MASK 0xFFUL /**< Bit mask for MODEM_SQITHRESH */
+#define _MODEM_CTRL2_SQITHRESH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL2 */
+#define MODEM_CTRL2_SQITHRESH_DEFAULT (_MODEM_CTRL2_SQITHRESH_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CTRL2 */
+#define MODEM_CTRL2_RXFRCDIS (0x1UL << 8) /**< Receive FRC disable */
+#define _MODEM_CTRL2_RXFRCDIS_SHIFT 8 /**< Shift value for MODEM_RXFRCDIS */
+#define _MODEM_CTRL2_RXFRCDIS_MASK 0x100UL /**< Bit mask for MODEM_RXFRCDIS */
+#define _MODEM_CTRL2_RXFRCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL2 */
+#define MODEM_CTRL2_RXFRCDIS_DEFAULT (_MODEM_CTRL2_RXFRCDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_CTRL2 */
+#define MODEM_CTRL2_RXPINMODE (0x1UL << 9) /**< Receive pin mode */
+#define _MODEM_CTRL2_RXPINMODE_SHIFT 9 /**< Shift value for MODEM_RXPINMODE */
+#define _MODEM_CTRL2_RXPINMODE_MASK 0x200UL /**< Bit mask for MODEM_RXPINMODE */
+#define _MODEM_CTRL2_RXPINMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL2 */
+#define _MODEM_CTRL2_RXPINMODE_SYNCHRONOUS 0x00000000UL /**< Mode SYNCHRONOUS for MODEM_CTRL2 */
+#define _MODEM_CTRL2_RXPINMODE_ASYNCHRONOUS 0x00000001UL /**< Mode ASYNCHRONOUS for MODEM_CTRL2 */
+#define MODEM_CTRL2_RXPINMODE_DEFAULT (_MODEM_CTRL2_RXPINMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_CTRL2 */
+#define MODEM_CTRL2_RXPINMODE_SYNCHRONOUS (_MODEM_CTRL2_RXPINMODE_SYNCHRONOUS << 9) /**< Shifted mode SYNCHRONOUS for MODEM_CTRL2 */
+#define MODEM_CTRL2_RXPINMODE_ASYNCHRONOUS (_MODEM_CTRL2_RXPINMODE_ASYNCHRONOUS << 9) /**< Shifted mode ASYNCHRONOUS for MODEM_CTRL2 */
+#define _MODEM_CTRL2_TXPINMODE_SHIFT 10 /**< Shift value for MODEM_TXPINMODE */
+#define _MODEM_CTRL2_TXPINMODE_MASK 0xC00UL /**< Bit mask for MODEM_TXPINMODE */
+#define _MODEM_CTRL2_TXPINMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL2 */
+#define _MODEM_CTRL2_TXPINMODE_OFF 0x00000000UL /**< Mode OFF for MODEM_CTRL2 */
+#define _MODEM_CTRL2_TXPINMODE_MFM 0x00000001UL /**< Mode MFM for MODEM_CTRL2 */
+#define _MODEM_CTRL2_TXPINMODE_ASYNCHRONOUS 0x00000002UL /**< Mode ASYNCHRONOUS for MODEM_CTRL2 */
+#define _MODEM_CTRL2_TXPINMODE_SYNCHRONOUS 0x00000003UL /**< Mode SYNCHRONOUS for MODEM_CTRL2 */
+#define MODEM_CTRL2_TXPINMODE_DEFAULT (_MODEM_CTRL2_TXPINMODE_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_CTRL2 */
+#define MODEM_CTRL2_TXPINMODE_OFF (_MODEM_CTRL2_TXPINMODE_OFF << 10) /**< Shifted mode OFF for MODEM_CTRL2 */
+#define MODEM_CTRL2_TXPINMODE_MFM (_MODEM_CTRL2_TXPINMODE_MFM << 10) /**< Shifted mode MFM for MODEM_CTRL2 */
+#define MODEM_CTRL2_TXPINMODE_ASYNCHRONOUS (_MODEM_CTRL2_TXPINMODE_ASYNCHRONOUS << 10) /**< Shifted mode ASYNCHRONOUS for MODEM_CTRL2 */
+#define MODEM_CTRL2_TXPINMODE_SYNCHRONOUS (_MODEM_CTRL2_TXPINMODE_SYNCHRONOUS << 10) /**< Shifted mode SYNCHRONOUS for MODEM_CTRL2 */
+#define _MODEM_CTRL2_DATAFILTER_SHIFT 12 /**< Shift value for MODEM_DATAFILTER */
+#define _MODEM_CTRL2_DATAFILTER_MASK 0x7000UL /**< Bit mask for MODEM_DATAFILTER */
+#define _MODEM_CTRL2_DATAFILTER_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_CTRL2 */
+#define _MODEM_CTRL2_DATAFILTER_DISABLED 0x00000000UL /**< Mode DISABLED for MODEM_CTRL2 */
+#define _MODEM_CTRL2_DATAFILTER_SHORT 0x00000001UL /**< Mode SHORT for MODEM_CTRL2 */
+#define _MODEM_CTRL2_DATAFILTER_MEDIUM 0x00000002UL /**< Mode MEDIUM for MODEM_CTRL2 */
+#define _MODEM_CTRL2_DATAFILTER_LONG 0x00000003UL /**< Mode LONG for MODEM_CTRL2 */
+#define _MODEM_CTRL2_DATAFILTER_LEN6 0x00000004UL /**< Mode LEN6 for MODEM_CTRL2 */
+#define _MODEM_CTRL2_DATAFILTER_LEN7 0x00000005UL /**< Mode LEN7 for MODEM_CTRL2 */
+#define _MODEM_CTRL2_DATAFILTER_LEN8 0x00000006UL /**< Mode LEN8 for MODEM_CTRL2 */
+#define _MODEM_CTRL2_DATAFILTER_LEN9 0x00000007UL /**< Mode LEN9 for MODEM_CTRL2 */
+#define MODEM_CTRL2_DATAFILTER_DEFAULT (_MODEM_CTRL2_DATAFILTER_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_CTRL2 */
+#define MODEM_CTRL2_DATAFILTER_DISABLED (_MODEM_CTRL2_DATAFILTER_DISABLED << 12) /**< Shifted mode DISABLED for MODEM_CTRL2 */
+#define MODEM_CTRL2_DATAFILTER_SHORT (_MODEM_CTRL2_DATAFILTER_SHORT << 12) /**< Shifted mode SHORT for MODEM_CTRL2 */
+#define MODEM_CTRL2_DATAFILTER_MEDIUM (_MODEM_CTRL2_DATAFILTER_MEDIUM << 12) /**< Shifted mode MEDIUM for MODEM_CTRL2 */
+#define MODEM_CTRL2_DATAFILTER_LONG (_MODEM_CTRL2_DATAFILTER_LONG << 12) /**< Shifted mode LONG for MODEM_CTRL2 */
+#define MODEM_CTRL2_DATAFILTER_LEN6 (_MODEM_CTRL2_DATAFILTER_LEN6 << 12) /**< Shifted mode LEN6 for MODEM_CTRL2 */
+#define MODEM_CTRL2_DATAFILTER_LEN7 (_MODEM_CTRL2_DATAFILTER_LEN7 << 12) /**< Shifted mode LEN7 for MODEM_CTRL2 */
+#define MODEM_CTRL2_DATAFILTER_LEN8 (_MODEM_CTRL2_DATAFILTER_LEN8 << 12) /**< Shifted mode LEN8 for MODEM_CTRL2 */
+#define MODEM_CTRL2_DATAFILTER_LEN9 (_MODEM_CTRL2_DATAFILTER_LEN9 << 12) /**< Shifted mode LEN9 for MODEM_CTRL2 */
+#define _MODEM_CTRL2_BRDIVA_SHIFT 15 /**< Shift value for MODEM_BRDIVA */
+#define _MODEM_CTRL2_BRDIVA_MASK 0x78000UL /**< Bit mask for MODEM_BRDIVA */
+#define _MODEM_CTRL2_BRDIVA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL2 */
+#define MODEM_CTRL2_BRDIVA_DEFAULT (_MODEM_CTRL2_BRDIVA_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_CTRL2 */
+#define _MODEM_CTRL2_BRDIVB_SHIFT 19 /**< Shift value for MODEM_BRDIVB */
+#define _MODEM_CTRL2_BRDIVB_MASK 0x780000UL /**< Bit mask for MODEM_BRDIVB */
+#define _MODEM_CTRL2_BRDIVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL2 */
+#define MODEM_CTRL2_BRDIVB_DEFAULT (_MODEM_CTRL2_BRDIVB_DEFAULT << 19) /**< Shifted mode DEFAULT for MODEM_CTRL2 */
+#define _MODEM_CTRL2_DEVMULA_SHIFT 23 /**< Shift value for MODEM_DEVMULA */
+#define _MODEM_CTRL2_DEVMULA_MASK 0x1800000UL /**< Bit mask for MODEM_DEVMULA */
+#define _MODEM_CTRL2_DEVMULA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL2 */
+#define MODEM_CTRL2_DEVMULA_DEFAULT (_MODEM_CTRL2_DEVMULA_DEFAULT << 23) /**< Shifted mode DEFAULT for MODEM_CTRL2 */
+#define _MODEM_CTRL2_DEVMULB_SHIFT 25 /**< Shift value for MODEM_DEVMULB */
+#define _MODEM_CTRL2_DEVMULB_MASK 0x6000000UL /**< Bit mask for MODEM_DEVMULB */
+#define _MODEM_CTRL2_DEVMULB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL2 */
+#define MODEM_CTRL2_DEVMULB_DEFAULT (_MODEM_CTRL2_DEVMULB_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_CTRL2 */
+#define _MODEM_CTRL2_RATESELMODE_SHIFT 27 /**< Shift value for MODEM_RATESELMODE */
+#define _MODEM_CTRL2_RATESELMODE_MASK 0x18000000UL /**< Bit mask for MODEM_RATESELMODE */
+#define _MODEM_CTRL2_RATESELMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL2 */
+#define _MODEM_CTRL2_RATESELMODE_NOCHANGE 0x00000000UL /**< Mode NOCHANGE for MODEM_CTRL2 */
+#define _MODEM_CTRL2_RATESELMODE_PAYLOAD 0x00000001UL /**< Mode PAYLOAD for MODEM_CTRL2 */
+#define _MODEM_CTRL2_RATESELMODE_FRC 0x00000002UL /**< Mode FRC for MODEM_CTRL2 */
+#define _MODEM_CTRL2_RATESELMODE_SYNC 0x00000003UL /**< Mode SYNC for MODEM_CTRL2 */
+#define MODEM_CTRL2_RATESELMODE_DEFAULT (_MODEM_CTRL2_RATESELMODE_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_CTRL2 */
+#define MODEM_CTRL2_RATESELMODE_NOCHANGE (_MODEM_CTRL2_RATESELMODE_NOCHANGE << 27) /**< Shifted mode NOCHANGE for MODEM_CTRL2 */
+#define MODEM_CTRL2_RATESELMODE_PAYLOAD (_MODEM_CTRL2_RATESELMODE_PAYLOAD << 27) /**< Shifted mode PAYLOAD for MODEM_CTRL2 */
+#define MODEM_CTRL2_RATESELMODE_FRC (_MODEM_CTRL2_RATESELMODE_FRC << 27) /**< Shifted mode FRC for MODEM_CTRL2 */
+#define MODEM_CTRL2_RATESELMODE_SYNC (_MODEM_CTRL2_RATESELMODE_SYNC << 27) /**< Shifted mode SYNC for MODEM_CTRL2 */
+#define MODEM_CTRL2_DEVWEIGHTDIS (0x1UL << 29) /**< Deviation weighting disable. */
+#define _MODEM_CTRL2_DEVWEIGHTDIS_SHIFT 29 /**< Shift value for MODEM_DEVWEIGHTDIS */
+#define _MODEM_CTRL2_DEVWEIGHTDIS_MASK 0x20000000UL /**< Bit mask for MODEM_DEVWEIGHTDIS */
+#define _MODEM_CTRL2_DEVWEIGHTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL2 */
+#define MODEM_CTRL2_DEVWEIGHTDIS_DEFAULT (_MODEM_CTRL2_DEVWEIGHTDIS_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_CTRL2 */
+#define _MODEM_CTRL2_DMASEL_SHIFT 30 /**< Shift value for MODEM_DMASEL */
+#define _MODEM_CTRL2_DMASEL_MASK 0xC0000000UL /**< Bit mask for MODEM_DMASEL */
+#define _MODEM_CTRL2_DMASEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL2 */
+#define _MODEM_CTRL2_DMASEL_SOFT 0x00000000UL /**< Mode SOFT for MODEM_CTRL2 */
+#define _MODEM_CTRL2_DMASEL_CORR 0x00000001UL /**< Mode CORR for MODEM_CTRL2 */
+#define _MODEM_CTRL2_DMASEL_FREQOFFEST 0x00000002UL /**< Mode FREQOFFEST for MODEM_CTRL2 */
+#define _MODEM_CTRL2_DMASEL_POE 0x00000003UL /**< Mode POE for MODEM_CTRL2 */
+#define MODEM_CTRL2_DMASEL_DEFAULT (_MODEM_CTRL2_DMASEL_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_CTRL2 */
+#define MODEM_CTRL2_DMASEL_SOFT (_MODEM_CTRL2_DMASEL_SOFT << 30) /**< Shifted mode SOFT for MODEM_CTRL2 */
+#define MODEM_CTRL2_DMASEL_CORR (_MODEM_CTRL2_DMASEL_CORR << 30) /**< Shifted mode CORR for MODEM_CTRL2 */
+#define MODEM_CTRL2_DMASEL_FREQOFFEST (_MODEM_CTRL2_DMASEL_FREQOFFEST << 30) /**< Shifted mode FREQOFFEST for MODEM_CTRL2 */
+#define MODEM_CTRL2_DMASEL_POE (_MODEM_CTRL2_DMASEL_POE << 30) /**< Shifted mode POE for MODEM_CTRL2 */
+
+/* Bit fields for MODEM CTRL3 */
+#define _MODEM_CTRL3_RESETVALUE 0x00008000UL /**< Default value for MODEM_CTRL3 */
+#define _MODEM_CTRL3_MASK 0xFFFFFF8FUL /**< Mask for MODEM_CTRL3 */
+#define MODEM_CTRL3_PRSDINEN (0x1UL << 0) /**< DIN PRS enable */
+#define _MODEM_CTRL3_PRSDINEN_SHIFT 0 /**< Shift value for MODEM_PRSDINEN */
+#define _MODEM_CTRL3_PRSDINEN_MASK 0x1UL /**< Bit mask for MODEM_PRSDINEN */
+#define _MODEM_CTRL3_PRSDINEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL3 */
+#define MODEM_CTRL3_PRSDINEN_DEFAULT (_MODEM_CTRL3_PRSDINEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CTRL3 */
+#define _MODEM_CTRL3_TIMINGBASESGAIN_SHIFT 1 /**< Shift value for MODEM_TIMINGBASESGAIN */
+#define _MODEM_CTRL3_TIMINGBASESGAIN_MASK 0x6UL /**< Bit mask for MODEM_TIMINGBASESGAIN */
+#define _MODEM_CTRL3_TIMINGBASESGAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL3 */
+#define MODEM_CTRL3_TIMINGBASESGAIN_DEFAULT (_MODEM_CTRL3_TIMINGBASESGAIN_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_CTRL3 */
+#define MODEM_CTRL3_DEVMULBCW (0x1UL << 3) /**< Deviatiion Factor B CW Mode */
+#define _MODEM_CTRL3_DEVMULBCW_SHIFT 3 /**< Shift value for MODEM_DEVMULBCW */
+#define _MODEM_CTRL3_DEVMULBCW_MASK 0x8UL /**< Bit mask for MODEM_DEVMULBCW */
+#define _MODEM_CTRL3_DEVMULBCW_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL3 */
+#define MODEM_CTRL3_DEVMULBCW_DEFAULT (_MODEM_CTRL3_DEVMULBCW_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_CTRL3 */
+#define _MODEM_CTRL3_ANTDIVMODE_SHIFT 8 /**< Shift value for MODEM_ANTDIVMODE */
+#define _MODEM_CTRL3_ANTDIVMODE_MASK 0x700UL /**< Bit mask for MODEM_ANTDIVMODE */
+#define _MODEM_CTRL3_ANTDIVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL3 */
+#define _MODEM_CTRL3_ANTDIVMODE_ANTENNA0 0x00000000UL /**< Mode ANTENNA0 for MODEM_CTRL3 */
+#define _MODEM_CTRL3_ANTDIVMODE_ANTENNA1 0x00000001UL /**< Mode ANTENNA1 for MODEM_CTRL3 */
+#define _MODEM_CTRL3_ANTDIVMODE_ANTSELFIRST 0x00000002UL /**< Mode ANTSELFIRST for MODEM_CTRL3 */
+#define _MODEM_CTRL3_ANTDIVMODE_ANTSELCORR 0x00000003UL /**< Mode ANTSELCORR for MODEM_CTRL3 */
+#define _MODEM_CTRL3_ANTDIVMODE_ANTSELRSSI 0x00000004UL /**< Mode ANTSELRSSI for MODEM_CTRL3 */
+#define _MODEM_CTRL3_ANTDIVMODE_PHDEMODANTDIV 0x00000005UL /**< Mode PHDEMODANTDIV for MODEM_CTRL3 */
+#define MODEM_CTRL3_ANTDIVMODE_DEFAULT (_MODEM_CTRL3_ANTDIVMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_CTRL3 */
+#define MODEM_CTRL3_ANTDIVMODE_ANTENNA0 (_MODEM_CTRL3_ANTDIVMODE_ANTENNA0 << 8) /**< Shifted mode ANTENNA0 for MODEM_CTRL3 */
+#define MODEM_CTRL3_ANTDIVMODE_ANTENNA1 (_MODEM_CTRL3_ANTDIVMODE_ANTENNA1 << 8) /**< Shifted mode ANTENNA1 for MODEM_CTRL3 */
+#define MODEM_CTRL3_ANTDIVMODE_ANTSELFIRST (_MODEM_CTRL3_ANTDIVMODE_ANTSELFIRST << 8) /**< Shifted mode ANTSELFIRST for MODEM_CTRL3 */
+#define MODEM_CTRL3_ANTDIVMODE_ANTSELCORR (_MODEM_CTRL3_ANTDIVMODE_ANTSELCORR << 8) /**< Shifted mode ANTSELCORR for MODEM_CTRL3 */
+#define MODEM_CTRL3_ANTDIVMODE_ANTSELRSSI (_MODEM_CTRL3_ANTDIVMODE_ANTSELRSSI << 8) /**< Shifted mode ANTSELRSSI for MODEM_CTRL3 */
+#define MODEM_CTRL3_ANTDIVMODE_PHDEMODANTDIV (_MODEM_CTRL3_ANTDIVMODE_PHDEMODANTDIV << 8) /**< Shifted mode PHDEMODANTDIV for MODEM_CTRL3 */
+#define MODEM_CTRL3_ANTDIVREPEATDIS (0x1UL << 11) /**< Antenna diversity repeat disable */
+#define _MODEM_CTRL3_ANTDIVREPEATDIS_SHIFT 11 /**< Shift value for MODEM_ANTDIVREPEATDIS */
+#define _MODEM_CTRL3_ANTDIVREPEATDIS_MASK 0x800UL /**< Bit mask for MODEM_ANTDIVREPEATDIS */
+#define _MODEM_CTRL3_ANTDIVREPEATDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL3 */
+#define MODEM_CTRL3_ANTDIVREPEATDIS_DEFAULT (_MODEM_CTRL3_ANTDIVREPEATDIS_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_CTRL3 */
+#define _MODEM_CTRL3_TSAMPMODE_SHIFT 12 /**< Shift value for MODEM_TSAMPMODE */
+#define _MODEM_CTRL3_TSAMPMODE_MASK 0x3000UL /**< Bit mask for MODEM_TSAMPMODE */
+#define _MODEM_CTRL3_TSAMPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL3 */
+#define _MODEM_CTRL3_TSAMPMODE_OFF 0x00000000UL /**< Mode OFF for MODEM_CTRL3 */
+#define _MODEM_CTRL3_TSAMPMODE_ON 0x00000001UL /**< Mode ON for MODEM_CTRL3 */
+#define _MODEM_CTRL3_TSAMPMODE_DIFF 0x00000002UL /**< Mode DIFF for MODEM_CTRL3 */
+#define MODEM_CTRL3_TSAMPMODE_DEFAULT (_MODEM_CTRL3_TSAMPMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_CTRL3 */
+#define MODEM_CTRL3_TSAMPMODE_OFF (_MODEM_CTRL3_TSAMPMODE_OFF << 12) /**< Shifted mode OFF for MODEM_CTRL3 */
+#define MODEM_CTRL3_TSAMPMODE_ON (_MODEM_CTRL3_TSAMPMODE_ON << 12) /**< Shifted mode ON for MODEM_CTRL3 */
+#define MODEM_CTRL3_TSAMPMODE_DIFF (_MODEM_CTRL3_TSAMPMODE_DIFF << 12) /**< Shifted mode DIFF for MODEM_CTRL3 */
+#define _MODEM_CTRL3_TSAMPDEL_SHIFT 14 /**< Shift value for MODEM_TSAMPDEL */
+#define _MODEM_CTRL3_TSAMPDEL_MASK 0xC000UL /**< Bit mask for MODEM_TSAMPDEL */
+#define _MODEM_CTRL3_TSAMPDEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for MODEM_CTRL3 */
+#define MODEM_CTRL3_TSAMPDEL_DEFAULT (_MODEM_CTRL3_TSAMPDEL_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_CTRL3 */
+#define _MODEM_CTRL3_TSAMPLIM_SHIFT 16 /**< Shift value for MODEM_TSAMPLIM */
+#define _MODEM_CTRL3_TSAMPLIM_MASK 0xFFFF0000UL /**< Bit mask for MODEM_TSAMPLIM */
+#define _MODEM_CTRL3_TSAMPLIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL3 */
+#define MODEM_CTRL3_TSAMPLIM_DEFAULT (_MODEM_CTRL3_TSAMPLIM_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_CTRL3 */
+
+/* Bit fields for MODEM CTRL4 */
+#define _MODEM_CTRL4_RESETVALUE 0x03000000UL /**< Default value for MODEM_CTRL4 */
+#define _MODEM_CTRL4_MASK 0xBFFFFFFFUL /**< Mask for MODEM_CTRL4 */
+#define _MODEM_CTRL4_ISICOMP_SHIFT 0 /**< Shift value for MODEM_ISICOMP */
+#define _MODEM_CTRL4_ISICOMP_MASK 0xFUL /**< Bit mask for MODEM_ISICOMP */
+#define _MODEM_CTRL4_ISICOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL4 */
+#define MODEM_CTRL4_ISICOMP_DEFAULT (_MODEM_CTRL4_ISICOMP_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CTRL4 */
+#define MODEM_CTRL4_DEVOFFCOMP (0x1UL << 4) /**< Deviation offset compensation */
+#define _MODEM_CTRL4_DEVOFFCOMP_SHIFT 4 /**< Shift value for MODEM_DEVOFFCOMP */
+#define _MODEM_CTRL4_DEVOFFCOMP_MASK 0x10UL /**< Bit mask for MODEM_DEVOFFCOMP */
+#define _MODEM_CTRL4_DEVOFFCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL4 */
+#define MODEM_CTRL4_DEVOFFCOMP_DEFAULT (_MODEM_CTRL4_DEVOFFCOMP_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_CTRL4 */
+#define _MODEM_CTRL4_PREDISTGAIN_SHIFT 5 /**< Shift value for MODEM_PREDISTGAIN */
+#define _MODEM_CTRL4_PREDISTGAIN_MASK 0x3E0UL /**< Bit mask for MODEM_PREDISTGAIN */
+#define _MODEM_CTRL4_PREDISTGAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL4 */
+#define MODEM_CTRL4_PREDISTGAIN_DEFAULT (_MODEM_CTRL4_PREDISTGAIN_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_CTRL4 */
+#define _MODEM_CTRL4_PREDISTDEB_SHIFT 10 /**< Shift value for MODEM_PREDISTDEB */
+#define _MODEM_CTRL4_PREDISTDEB_MASK 0x1C00UL /**< Bit mask for MODEM_PREDISTDEB */
+#define _MODEM_CTRL4_PREDISTDEB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL4 */
+#define MODEM_CTRL4_PREDISTDEB_DEFAULT (_MODEM_CTRL4_PREDISTDEB_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_CTRL4 */
+#define MODEM_CTRL4_PREDISTAVG (0x1UL << 13) /**< Predistortion Average */
+#define _MODEM_CTRL4_PREDISTAVG_SHIFT 13 /**< Shift value for MODEM_PREDISTAVG */
+#define _MODEM_CTRL4_PREDISTAVG_MASK 0x2000UL /**< Bit mask for MODEM_PREDISTAVG */
+#define _MODEM_CTRL4_PREDISTAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL4 */
+#define _MODEM_CTRL4_PREDISTAVG_AVG8 0x00000000UL /**< Mode AVG8 for MODEM_CTRL4 */
+#define _MODEM_CTRL4_PREDISTAVG_AVG16 0x00000001UL /**< Mode AVG16 for MODEM_CTRL4 */
+#define MODEM_CTRL4_PREDISTAVG_DEFAULT (_MODEM_CTRL4_PREDISTAVG_DEFAULT << 13) /**< Shifted mode DEFAULT for MODEM_CTRL4 */
+#define MODEM_CTRL4_PREDISTAVG_AVG8 (_MODEM_CTRL4_PREDISTAVG_AVG8 << 13) /**< Shifted mode AVG8 for MODEM_CTRL4 */
+#define MODEM_CTRL4_PREDISTAVG_AVG16 (_MODEM_CTRL4_PREDISTAVG_AVG16 << 13) /**< Shifted mode AVG16 for MODEM_CTRL4 */
+#define MODEM_CTRL4_PREDISTRST (0x1UL << 14) /**< Predistortion Reset */
+#define _MODEM_CTRL4_PREDISTRST_SHIFT 14 /**< Shift value for MODEM_PREDISTRST */
+#define _MODEM_CTRL4_PREDISTRST_MASK 0x4000UL /**< Bit mask for MODEM_PREDISTRST */
+#define _MODEM_CTRL4_PREDISTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL4 */
+#define MODEM_CTRL4_PREDISTRST_DEFAULT (_MODEM_CTRL4_PREDISTRST_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_CTRL4 */
+#define _MODEM_CTRL4_PHASECLICKFILT_SHIFT 15 /**< Shift value for MODEM_PHASECLICKFILT */
+#define _MODEM_CTRL4_PHASECLICKFILT_MASK 0x3F8000UL /**< Bit mask for MODEM_PHASECLICKFILT */
+#define _MODEM_CTRL4_PHASECLICKFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL4 */
+#define MODEM_CTRL4_PHASECLICKFILT_DEFAULT (_MODEM_CTRL4_PHASECLICKFILT_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_CTRL4 */
+#define MODEM_CTRL4_SOFTDSSSMODE (0x1UL << 22) /**< Soft DSSS mode */
+#define _MODEM_CTRL4_SOFTDSSSMODE_SHIFT 22 /**< Shift value for MODEM_SOFTDSSSMODE */
+#define _MODEM_CTRL4_SOFTDSSSMODE_MASK 0x400000UL /**< Bit mask for MODEM_SOFTDSSSMODE */
+#define _MODEM_CTRL4_SOFTDSSSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL4 */
+#define _MODEM_CTRL4_SOFTDSSSMODE_CORR0INV 0x00000000UL /**< Mode CORR0INV for MODEM_CTRL4 */
+#define _MODEM_CTRL4_SOFTDSSSMODE_CORRDIFF 0x00000001UL /**< Mode CORRDIFF for MODEM_CTRL4 */
+#define MODEM_CTRL4_SOFTDSSSMODE_DEFAULT (_MODEM_CTRL4_SOFTDSSSMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for MODEM_CTRL4 */
+#define MODEM_CTRL4_SOFTDSSSMODE_CORR0INV (_MODEM_CTRL4_SOFTDSSSMODE_CORR0INV << 22) /**< Shifted mode CORR0INV for MODEM_CTRL4 */
+#define MODEM_CTRL4_SOFTDSSSMODE_CORRDIFF (_MODEM_CTRL4_SOFTDSSSMODE_CORRDIFF << 22) /**< Shifted mode CORRDIFF for MODEM_CTRL4 */
+#define _MODEM_CTRL4_ADCSATLEVEL_SHIFT 23 /**< Shift value for MODEM_ADCSATLEVEL */
+#define _MODEM_CTRL4_ADCSATLEVEL_MASK 0x3800000UL /**< Bit mask for MODEM_ADCSATLEVEL */
+#define _MODEM_CTRL4_ADCSATLEVEL_DEFAULT 0x00000006UL /**< Mode DEFAULT for MODEM_CTRL4 */
+#define _MODEM_CTRL4_ADCSATLEVEL_CONS1 0x00000000UL /**< Mode CONS1 for MODEM_CTRL4 */
+#define _MODEM_CTRL4_ADCSATLEVEL_CONS2 0x00000001UL /**< Mode CONS2 for MODEM_CTRL4 */
+#define _MODEM_CTRL4_ADCSATLEVEL_CONS4 0x00000002UL /**< Mode CONS4 for MODEM_CTRL4 */
+#define _MODEM_CTRL4_ADCSATLEVEL_CONS8 0x00000003UL /**< Mode CONS8 for MODEM_CTRL4 */
+#define _MODEM_CTRL4_ADCSATLEVEL_CONS16 0x00000004UL /**< Mode CONS16 for MODEM_CTRL4 */
+#define _MODEM_CTRL4_ADCSATLEVEL_CONS32 0x00000005UL /**< Mode CONS32 for MODEM_CTRL4 */
+#define _MODEM_CTRL4_ADCSATLEVEL_CONS64 0x00000006UL /**< Mode CONS64 for MODEM_CTRL4 */
+#define MODEM_CTRL4_ADCSATLEVEL_DEFAULT (_MODEM_CTRL4_ADCSATLEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for MODEM_CTRL4 */
+#define MODEM_CTRL4_ADCSATLEVEL_CONS1 (_MODEM_CTRL4_ADCSATLEVEL_CONS1 << 23) /**< Shifted mode CONS1 for MODEM_CTRL4 */
+#define MODEM_CTRL4_ADCSATLEVEL_CONS2 (_MODEM_CTRL4_ADCSATLEVEL_CONS2 << 23) /**< Shifted mode CONS2 for MODEM_CTRL4 */
+#define MODEM_CTRL4_ADCSATLEVEL_CONS4 (_MODEM_CTRL4_ADCSATLEVEL_CONS4 << 23) /**< Shifted mode CONS4 for MODEM_CTRL4 */
+#define MODEM_CTRL4_ADCSATLEVEL_CONS8 (_MODEM_CTRL4_ADCSATLEVEL_CONS8 << 23) /**< Shifted mode CONS8 for MODEM_CTRL4 */
+#define MODEM_CTRL4_ADCSATLEVEL_CONS16 (_MODEM_CTRL4_ADCSATLEVEL_CONS16 << 23) /**< Shifted mode CONS16 for MODEM_CTRL4 */
+#define MODEM_CTRL4_ADCSATLEVEL_CONS32 (_MODEM_CTRL4_ADCSATLEVEL_CONS32 << 23) /**< Shifted mode CONS32 for MODEM_CTRL4 */
+#define MODEM_CTRL4_ADCSATLEVEL_CONS64 (_MODEM_CTRL4_ADCSATLEVEL_CONS64 << 23) /**< Shifted mode CONS64 for MODEM_CTRL4 */
+#define _MODEM_CTRL4_ADCSATDENS_SHIFT 26 /**< Shift value for MODEM_ADCSATDENS */
+#define _MODEM_CTRL4_ADCSATDENS_MASK 0xC000000UL /**< Bit mask for MODEM_ADCSATDENS */
+#define _MODEM_CTRL4_ADCSATDENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL4 */
+#define MODEM_CTRL4_ADCSATDENS_DEFAULT (_MODEM_CTRL4_ADCSATDENS_DEFAULT << 26) /**< Shifted mode DEFAULT for MODEM_CTRL4 */
+#define MODEM_CTRL4_OFFSETPHASEMASKING (0x1UL << 28) /**< Offset phase masking */
+#define _MODEM_CTRL4_OFFSETPHASEMASKING_SHIFT 28 /**< Shift value for MODEM_OFFSETPHASEMASKING */
+#define _MODEM_CTRL4_OFFSETPHASEMASKING_MASK 0x10000000UL /**< Bit mask for MODEM_OFFSETPHASEMASKING */
+#define _MODEM_CTRL4_OFFSETPHASEMASKING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL4 */
+#define MODEM_CTRL4_OFFSETPHASEMASKING_DEFAULT (_MODEM_CTRL4_OFFSETPHASEMASKING_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_CTRL4 */
+#define MODEM_CTRL4_OFFSETPHASESCALING (0x1UL << 29) /**< Offset phase scaling */
+#define _MODEM_CTRL4_OFFSETPHASESCALING_SHIFT 29 /**< Shift value for MODEM_OFFSETPHASESCALING */
+#define _MODEM_CTRL4_OFFSETPHASESCALING_MASK 0x20000000UL /**< Bit mask for MODEM_OFFSETPHASESCALING */
+#define _MODEM_CTRL4_OFFSETPHASESCALING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL4 */
+#define MODEM_CTRL4_OFFSETPHASESCALING_DEFAULT (_MODEM_CTRL4_OFFSETPHASESCALING_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_CTRL4 */
+
+/* Bit fields for MODEM CTRL5 */
+#define _MODEM_CTRL5_RESETVALUE 0x00000000UL /**< Default value for MODEM_CTRL5 */
+#define _MODEM_CTRL5_MASK 0x6F7FFFFEUL /**< Mask for MODEM_CTRL5 */
+#define MODEM_CTRL5_BRCALEN (0x1UL << 1) /**< Baudrate calibration enable */
+#define _MODEM_CTRL5_BRCALEN_SHIFT 1 /**< Shift value for MODEM_BRCALEN */
+#define _MODEM_CTRL5_BRCALEN_MASK 0x2UL /**< Bit mask for MODEM_BRCALEN */
+#define _MODEM_CTRL5_BRCALEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL5 */
+#define MODEM_CTRL5_BRCALEN_DEFAULT (_MODEM_CTRL5_BRCALEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_CTRL5 */
+#define _MODEM_CTRL5_BRCALMODE_SHIFT 2 /**< Shift value for MODEM_BRCALMODE */
+#define _MODEM_CTRL5_BRCALMODE_MASK 0xCUL /**< Bit mask for MODEM_BRCALMODE */
+#define _MODEM_CTRL5_BRCALMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL5 */
+#define _MODEM_CTRL5_BRCALMODE_PEAK 0x00000000UL /**< Mode PEAK for MODEM_CTRL5 */
+#define _MODEM_CTRL5_BRCALMODE_ZERO 0x00000001UL /**< Mode ZERO for MODEM_CTRL5 */
+#define _MODEM_CTRL5_BRCALMODE_PEAKZERO 0x00000002UL /**< Mode PEAKZERO for MODEM_CTRL5 */
+#define MODEM_CTRL5_BRCALMODE_DEFAULT (_MODEM_CTRL5_BRCALMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_CTRL5 */
+#define MODEM_CTRL5_BRCALMODE_PEAK (_MODEM_CTRL5_BRCALMODE_PEAK << 2) /**< Shifted mode PEAK for MODEM_CTRL5 */
+#define MODEM_CTRL5_BRCALMODE_ZERO (_MODEM_CTRL5_BRCALMODE_ZERO << 2) /**< Shifted mode ZERO for MODEM_CTRL5 */
+#define MODEM_CTRL5_BRCALMODE_PEAKZERO (_MODEM_CTRL5_BRCALMODE_PEAKZERO << 2) /**< Shifted mode PEAKZERO for MODEM_CTRL5 */
+#define _MODEM_CTRL5_BRCALAVG_SHIFT 4 /**< Shift value for MODEM_BRCALAVG */
+#define _MODEM_CTRL5_BRCALAVG_MASK 0x30UL /**< Bit mask for MODEM_BRCALAVG */
+#define _MODEM_CTRL5_BRCALAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL5 */
+#define MODEM_CTRL5_BRCALAVG_DEFAULT (_MODEM_CTRL5_BRCALAVG_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_CTRL5 */
+#define _MODEM_CTRL5_DETDEL_SHIFT 6 /**< Shift value for MODEM_DETDEL */
+#define _MODEM_CTRL5_DETDEL_MASK 0x1C0UL /**< Bit mask for MODEM_DETDEL */
+#define _MODEM_CTRL5_DETDEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL5 */
+#define MODEM_CTRL5_DETDEL_DEFAULT (_MODEM_CTRL5_DETDEL_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_CTRL5 */
+#define MODEM_CTRL5_TDEDGE (0x1UL << 9) /**< Timing detection edge mode */
+#define _MODEM_CTRL5_TDEDGE_SHIFT 9 /**< Shift value for MODEM_TDEDGE */
+#define _MODEM_CTRL5_TDEDGE_MASK 0x200UL /**< Bit mask for MODEM_TDEDGE */
+#define _MODEM_CTRL5_TDEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL5 */
+#define MODEM_CTRL5_TDEDGE_DEFAULT (_MODEM_CTRL5_TDEDGE_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_CTRL5 */
+#define MODEM_CTRL5_TREDGE (0x1UL << 10) /**< Timing resynchronization edge mode */
+#define _MODEM_CTRL5_TREDGE_SHIFT 10 /**< Shift value for MODEM_TREDGE */
+#define _MODEM_CTRL5_TREDGE_MASK 0x400UL /**< Bit mask for MODEM_TREDGE */
+#define _MODEM_CTRL5_TREDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL5 */
+#define MODEM_CTRL5_TREDGE_DEFAULT (_MODEM_CTRL5_TREDGE_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_CTRL5 */
+#define MODEM_CTRL5_DSSSCTD (0x1UL << 11) /**< DSSS Correlation Threshold Disable */
+#define _MODEM_CTRL5_DSSSCTD_SHIFT 11 /**< Shift value for MODEM_DSSSCTD */
+#define _MODEM_CTRL5_DSSSCTD_MASK 0x800UL /**< Bit mask for MODEM_DSSSCTD */
+#define _MODEM_CTRL5_DSSSCTD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL5 */
+#define MODEM_CTRL5_DSSSCTD_DEFAULT (_MODEM_CTRL5_DSSSCTD_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_CTRL5 */
+#define _MODEM_CTRL5_BBSS_SHIFT 12 /**< Shift value for MODEM_BBSS */
+#define _MODEM_CTRL5_BBSS_MASK 0xF000UL /**< Bit mask for MODEM_BBSS */
+#define _MODEM_CTRL5_BBSS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL5 */
+#define MODEM_CTRL5_BBSS_DEFAULT (_MODEM_CTRL5_BBSS_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_CTRL5 */
+#define _MODEM_CTRL5_POEPER_SHIFT 16 /**< Shift value for MODEM_POEPER */
+#define _MODEM_CTRL5_POEPER_MASK 0xF0000UL /**< Bit mask for MODEM_POEPER */
+#define _MODEM_CTRL5_POEPER_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL5 */
+#define MODEM_CTRL5_POEPER_DEFAULT (_MODEM_CTRL5_POEPER_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_CTRL5 */
+#define _MODEM_CTRL5_DEMODRAWDATASEL2_SHIFT 20 /**< Shift value for MODEM_DEMODRAWDATASEL2 */
+#define _MODEM_CTRL5_DEMODRAWDATASEL2_MASK 0x700000UL /**< Bit mask for MODEM_DEMODRAWDATASEL2 */
+#define _MODEM_CTRL5_DEMODRAWDATASEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL5 */
+#define _MODEM_CTRL5_DEMODRAWDATASEL2_DIS 0x00000000UL /**< Mode DIS for MODEM_CTRL5 */
+#define _MODEM_CTRL5_DEMODRAWDATASEL2_COH 0x00000001UL /**< Mode COH for MODEM_CTRL5 */
+#define _MODEM_CTRL5_DEMODRAWDATASEL2_CORR 0x00000002UL /**< Mode CORR for MODEM_CTRL5 */
+#define _MODEM_CTRL5_DEMODRAWDATASEL2_CHPW 0x00000003UL /**< Mode CHPW for MODEM_CTRL5 */
+#define _MODEM_CTRL5_DEMODRAWDATASEL2_BBPF 0x00000004UL /**< Mode BBPF for MODEM_CTRL5 */
+#define _MODEM_CTRL5_DEMODRAWDATASEL2_FSM 0x00000005UL /**< Mode FSM for MODEM_CTRL5 */
+#define _MODEM_CTRL5_DEMODRAWDATASEL2_HADM 0x00000006UL /**< Mode HADM for MODEM_CTRL5 */
+#define MODEM_CTRL5_DEMODRAWDATASEL2_DEFAULT (_MODEM_CTRL5_DEMODRAWDATASEL2_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_CTRL5 */
+#define MODEM_CTRL5_DEMODRAWDATASEL2_DIS (_MODEM_CTRL5_DEMODRAWDATASEL2_DIS << 20) /**< Shifted mode DIS for MODEM_CTRL5 */
+#define MODEM_CTRL5_DEMODRAWDATASEL2_COH (_MODEM_CTRL5_DEMODRAWDATASEL2_COH << 20) /**< Shifted mode COH for MODEM_CTRL5 */
+#define MODEM_CTRL5_DEMODRAWDATASEL2_CORR (_MODEM_CTRL5_DEMODRAWDATASEL2_CORR << 20) /**< Shifted mode CORR for MODEM_CTRL5 */
+#define MODEM_CTRL5_DEMODRAWDATASEL2_CHPW (_MODEM_CTRL5_DEMODRAWDATASEL2_CHPW << 20) /**< Shifted mode CHPW for MODEM_CTRL5 */
+#define MODEM_CTRL5_DEMODRAWDATASEL2_BBPF (_MODEM_CTRL5_DEMODRAWDATASEL2_BBPF << 20) /**< Shifted mode BBPF for MODEM_CTRL5 */
+#define MODEM_CTRL5_DEMODRAWDATASEL2_FSM (_MODEM_CTRL5_DEMODRAWDATASEL2_FSM << 20) /**< Shifted mode FSM for MODEM_CTRL5 */
+#define MODEM_CTRL5_DEMODRAWDATASEL2_HADM (_MODEM_CTRL5_DEMODRAWDATASEL2_HADM << 20) /**< Shifted mode HADM for MODEM_CTRL5 */
+#define _MODEM_CTRL5_FOEPREAVG_SHIFT 24 /**< Shift value for MODEM_FOEPREAVG */
+#define _MODEM_CTRL5_FOEPREAVG_MASK 0x7000000UL /**< Bit mask for MODEM_FOEPREAVG */
+#define _MODEM_CTRL5_FOEPREAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL5 */
+#define MODEM_CTRL5_FOEPREAVG_DEFAULT (_MODEM_CTRL5_FOEPREAVG_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_CTRL5 */
+#define MODEM_CTRL5_LINCORR (0x1UL << 27) /**< Linear Correlation */
+#define _MODEM_CTRL5_LINCORR_SHIFT 27 /**< Shift value for MODEM_LINCORR */
+#define _MODEM_CTRL5_LINCORR_MASK 0x8000000UL /**< Bit mask for MODEM_LINCORR */
+#define _MODEM_CTRL5_LINCORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL5 */
+#define MODEM_CTRL5_LINCORR_DEFAULT (_MODEM_CTRL5_LINCORR_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_CTRL5 */
+#define MODEM_CTRL5_RESYNCBAUDTRANS (0x1UL << 29) /**< Resynchronization Baud Transitions */
+#define _MODEM_CTRL5_RESYNCBAUDTRANS_SHIFT 29 /**< Shift value for MODEM_RESYNCBAUDTRANS */
+#define _MODEM_CTRL5_RESYNCBAUDTRANS_MASK 0x20000000UL /**< Bit mask for MODEM_RESYNCBAUDTRANS */
+#define _MODEM_CTRL5_RESYNCBAUDTRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL5 */
+#define MODEM_CTRL5_RESYNCBAUDTRANS_DEFAULT (_MODEM_CTRL5_RESYNCBAUDTRANS_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_CTRL5 */
+#define MODEM_CTRL5_RESYNCLIMIT (0x1UL << 30) /**< Resynchronization Limit */
+#define _MODEM_CTRL5_RESYNCLIMIT_SHIFT 30 /**< Shift value for MODEM_RESYNCLIMIT */
+#define _MODEM_CTRL5_RESYNCLIMIT_MASK 0x40000000UL /**< Bit mask for MODEM_RESYNCLIMIT */
+#define _MODEM_CTRL5_RESYNCLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL5 */
+#define _MODEM_CTRL5_RESYNCLIMIT_HALF 0x00000000UL /**< Mode HALF for MODEM_CTRL5 */
+#define _MODEM_CTRL5_RESYNCLIMIT_ALWAYS 0x00000001UL /**< Mode ALWAYS for MODEM_CTRL5 */
+#define MODEM_CTRL5_RESYNCLIMIT_DEFAULT (_MODEM_CTRL5_RESYNCLIMIT_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_CTRL5 */
+#define MODEM_CTRL5_RESYNCLIMIT_HALF (_MODEM_CTRL5_RESYNCLIMIT_HALF << 30) /**< Shifted mode HALF for MODEM_CTRL5 */
+#define MODEM_CTRL5_RESYNCLIMIT_ALWAYS (_MODEM_CTRL5_RESYNCLIMIT_ALWAYS << 30) /**< Shifted mode ALWAYS for MODEM_CTRL5 */
+
+/* Bit fields for MODEM CTRL6 */
+#define _MODEM_CTRL6_RESETVALUE 0x00000000UL /**< Default value for MODEM_CTRL6 */
+#define _MODEM_CTRL6_MASK 0xFFFFFFFFUL /**< Mask for MODEM_CTRL6 */
+#define _MODEM_CTRL6_TDREW_SHIFT 0 /**< Shift value for MODEM_TDREW */
+#define _MODEM_CTRL6_TDREW_MASK 0x7FUL /**< Bit mask for MODEM_TDREW */
+#define _MODEM_CTRL6_TDREW_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */
+#define MODEM_CTRL6_TDREW_DEFAULT (_MODEM_CTRL6_TDREW_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CTRL6 */
+#define _MODEM_CTRL6_PREBASES_SHIFT 7 /**< Shift value for MODEM_PREBASES */
+#define _MODEM_CTRL6_PREBASES_MASK 0x780UL /**< Bit mask for MODEM_PREBASES */
+#define _MODEM_CTRL6_PREBASES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */
+#define MODEM_CTRL6_PREBASES_DEFAULT (_MODEM_CTRL6_PREBASES_DEFAULT << 7) /**< Shifted mode DEFAULT for MODEM_CTRL6 */
+#define MODEM_CTRL6_PSTIMABORT0 (0x1UL << 11) /**< Preamble Search Timing Abort Criteria 0 */
+#define _MODEM_CTRL6_PSTIMABORT0_SHIFT 11 /**< Shift value for MODEM_PSTIMABORT0 */
+#define _MODEM_CTRL6_PSTIMABORT0_MASK 0x800UL /**< Bit mask for MODEM_PSTIMABORT0 */
+#define _MODEM_CTRL6_PSTIMABORT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */
+#define MODEM_CTRL6_PSTIMABORT0_DEFAULT (_MODEM_CTRL6_PSTIMABORT0_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_CTRL6 */
+#define MODEM_CTRL6_PSTIMABORT1 (0x1UL << 12) /**< Preamble Search Timing Abort Criteria 1 */
+#define _MODEM_CTRL6_PSTIMABORT1_SHIFT 12 /**< Shift value for MODEM_PSTIMABORT1 */
+#define _MODEM_CTRL6_PSTIMABORT1_MASK 0x1000UL /**< Bit mask for MODEM_PSTIMABORT1 */
+#define _MODEM_CTRL6_PSTIMABORT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */
+#define MODEM_CTRL6_PSTIMABORT1_DEFAULT (_MODEM_CTRL6_PSTIMABORT1_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_CTRL6 */
+#define MODEM_CTRL6_PSTIMABORT2 (0x1UL << 13) /**< Preamble Search Timing Abort Criteria 2 */
+#define _MODEM_CTRL6_PSTIMABORT2_SHIFT 13 /**< Shift value for MODEM_PSTIMABORT2 */
+#define _MODEM_CTRL6_PSTIMABORT2_MASK 0x2000UL /**< Bit mask for MODEM_PSTIMABORT2 */
+#define _MODEM_CTRL6_PSTIMABORT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */
+#define MODEM_CTRL6_PSTIMABORT2_DEFAULT (_MODEM_CTRL6_PSTIMABORT2_DEFAULT << 13) /**< Shifted mode DEFAULT for MODEM_CTRL6 */
+#define MODEM_CTRL6_PSTIMABORT3 (0x1UL << 14) /**< Preamble Search Timing Abort Criteria 3 */
+#define _MODEM_CTRL6_PSTIMABORT3_SHIFT 14 /**< Shift value for MODEM_PSTIMABORT3 */
+#define _MODEM_CTRL6_PSTIMABORT3_MASK 0x4000UL /**< Bit mask for MODEM_PSTIMABORT3 */
+#define _MODEM_CTRL6_PSTIMABORT3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */
+#define MODEM_CTRL6_PSTIMABORT3_DEFAULT (_MODEM_CTRL6_PSTIMABORT3_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_CTRL6 */
+#define _MODEM_CTRL6_ARW_SHIFT 15 /**< Shift value for MODEM_ARW */
+#define _MODEM_CTRL6_ARW_MASK 0x18000UL /**< Bit mask for MODEM_ARW */
+#define _MODEM_CTRL6_ARW_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */
+#define _MODEM_CTRL6_ARW_SMALLWND 0x00000000UL /**< Mode SMALLWND for MODEM_CTRL6 */
+#define _MODEM_CTRL6_ARW_ALWAYS 0x00000001UL /**< Mode ALWAYS for MODEM_CTRL6 */
+#define _MODEM_CTRL6_ARW_NEVER 0x00000002UL /**< Mode NEVER for MODEM_CTRL6 */
+#define _MODEM_CTRL6_ARW_PSABORT 0x00000003UL /**< Mode PSABORT for MODEM_CTRL6 */
+#define MODEM_CTRL6_ARW_DEFAULT (_MODEM_CTRL6_ARW_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_CTRL6 */
+#define MODEM_CTRL6_ARW_SMALLWND (_MODEM_CTRL6_ARW_SMALLWND << 15) /**< Shifted mode SMALLWND for MODEM_CTRL6 */
+#define MODEM_CTRL6_ARW_ALWAYS (_MODEM_CTRL6_ARW_ALWAYS << 15) /**< Shifted mode ALWAYS for MODEM_CTRL6 */
+#define MODEM_CTRL6_ARW_NEVER (_MODEM_CTRL6_ARW_NEVER << 15) /**< Shifted mode NEVER for MODEM_CTRL6 */
+#define MODEM_CTRL6_ARW_PSABORT (_MODEM_CTRL6_ARW_PSABORT << 15) /**< Shifted mode PSABORT for MODEM_CTRL6 */
+#define _MODEM_CTRL6_TIMTHRESHGAIN_SHIFT 17 /**< Shift value for MODEM_TIMTHRESHGAIN */
+#define _MODEM_CTRL6_TIMTHRESHGAIN_MASK 0xE0000UL /**< Bit mask for MODEM_TIMTHRESHGAIN */
+#define _MODEM_CTRL6_TIMTHRESHGAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */
+#define MODEM_CTRL6_TIMTHRESHGAIN_DEFAULT (_MODEM_CTRL6_TIMTHRESHGAIN_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_CTRL6 */
+#define MODEM_CTRL6_CPLXCORREN (0x1UL << 20) /**< Enable Complex Correlation */
+#define _MODEM_CTRL6_CPLXCORREN_SHIFT 20 /**< Shift value for MODEM_CPLXCORREN */
+#define _MODEM_CTRL6_CPLXCORREN_MASK 0x100000UL /**< Bit mask for MODEM_CPLXCORREN */
+#define _MODEM_CTRL6_CPLXCORREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */
+#define MODEM_CTRL6_CPLXCORREN_DEFAULT (_MODEM_CTRL6_CPLXCORREN_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_CTRL6 */
+#define MODEM_CTRL6_DSSS3SYMBOLSYNCEN (0x1UL << 21) /**< Enable three symbol sync detection */
+#define _MODEM_CTRL6_DSSS3SYMBOLSYNCEN_SHIFT 21 /**< Shift value for MODEM_DSSS3SYMBOLSYNCEN */
+#define _MODEM_CTRL6_DSSS3SYMBOLSYNCEN_MASK 0x200000UL /**< Bit mask for MODEM_DSSS3SYMBOLSYNCEN */
+#define _MODEM_CTRL6_DSSS3SYMBOLSYNCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */
+#define MODEM_CTRL6_DSSS3SYMBOLSYNCEN_DEFAULT (_MODEM_CTRL6_DSSS3SYMBOLSYNCEN_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_CTRL6 */
+#define MODEM_CTRL6_TXDBPSKINV (0x1UL << 22) /**< TX DBPSK modulation encode invert */
+#define _MODEM_CTRL6_TXDBPSKINV_SHIFT 22 /**< Shift value for MODEM_TXDBPSKINV */
+#define _MODEM_CTRL6_TXDBPSKINV_MASK 0x400000UL /**< Bit mask for MODEM_TXDBPSKINV */
+#define _MODEM_CTRL6_TXDBPSKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */
+#define MODEM_CTRL6_TXDBPSKINV_DEFAULT (_MODEM_CTRL6_TXDBPSKINV_DEFAULT << 22) /**< Shifted mode DEFAULT for MODEM_CTRL6 */
+#define MODEM_CTRL6_TXDBPSKRAMPEN (0x1UL << 23) /**< TX DBPSK PA Ramp Enable */
+#define _MODEM_CTRL6_TXDBPSKRAMPEN_SHIFT 23 /**< Shift value for MODEM_TXDBPSKRAMPEN */
+#define _MODEM_CTRL6_TXDBPSKRAMPEN_MASK 0x800000UL /**< Bit mask for MODEM_TXDBPSKRAMPEN */
+#define _MODEM_CTRL6_TXDBPSKRAMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */
+#define MODEM_CTRL6_TXDBPSKRAMPEN_DEFAULT (_MODEM_CTRL6_TXDBPSKRAMPEN_DEFAULT << 23) /**< Shifted mode DEFAULT for MODEM_CTRL6 */
+#define MODEM_CTRL6_IFADCDIGGAINCLKSEL (0x1UL << 24) /**< IFADC Output Dig Gain Clock Select */
+#define _MODEM_CTRL6_IFADCDIGGAINCLKSEL_SHIFT 24 /**< Shift value for MODEM_IFADCDIGGAINCLKSEL */
+#define _MODEM_CTRL6_IFADCDIGGAINCLKSEL_MASK 0x1000000UL /**< Bit mask for MODEM_IFADCDIGGAINCLKSEL */
+#define _MODEM_CTRL6_IFADCDIGGAINCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */
+#define MODEM_CTRL6_IFADCDIGGAINCLKSEL_DEFAULT (_MODEM_CTRL6_IFADCDIGGAINCLKSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_CTRL6 */
+#define _MODEM_CTRL6_CODINGB_SHIFT 25 /**< Shift value for MODEM_CODINGB */
+#define _MODEM_CTRL6_CODINGB_MASK 0x6000000UL /**< Bit mask for MODEM_CODINGB */
+#define _MODEM_CTRL6_CODINGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */
+#define _MODEM_CTRL6_CODINGB_NRZ 0x00000000UL /**< Mode NRZ for MODEM_CTRL6 */
+#define _MODEM_CTRL6_CODINGB_MANCHESTER 0x00000001UL /**< Mode MANCHESTER for MODEM_CTRL6 */
+#define _MODEM_CTRL6_CODINGB_DSSS 0x00000002UL /**< Mode DSSS for MODEM_CTRL6 */
+#define _MODEM_CTRL6_CODINGB_LINECODE 0x00000003UL /**< Mode LINECODE for MODEM_CTRL6 */
+#define MODEM_CTRL6_CODINGB_DEFAULT (_MODEM_CTRL6_CODINGB_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_CTRL6 */
+#define MODEM_CTRL6_CODINGB_NRZ (_MODEM_CTRL6_CODINGB_NRZ << 25) /**< Shifted mode NRZ for MODEM_CTRL6 */
+#define MODEM_CTRL6_CODINGB_MANCHESTER (_MODEM_CTRL6_CODINGB_MANCHESTER << 25) /**< Shifted mode MANCHESTER for MODEM_CTRL6 */
+#define MODEM_CTRL6_CODINGB_DSSS (_MODEM_CTRL6_CODINGB_DSSS << 25) /**< Shifted mode DSSS for MODEM_CTRL6 */
+#define MODEM_CTRL6_CODINGB_LINECODE (_MODEM_CTRL6_CODINGB_LINECODE << 25) /**< Shifted mode LINECODE for MODEM_CTRL6 */
+#define MODEM_CTRL6_IFADCDIGGAIN (0x1UL << 27) /**< IFADC Output Dig Gain Select */
+#define _MODEM_CTRL6_IFADCDIGGAIN_SHIFT 27 /**< Shift value for MODEM_IFADCDIGGAIN */
+#define _MODEM_CTRL6_IFADCDIGGAIN_MASK 0x8000000UL /**< Bit mask for MODEM_IFADCDIGGAIN */
+#define _MODEM_CTRL6_IFADCDIGGAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */
+#define MODEM_CTRL6_IFADCDIGGAIN_DEFAULT (_MODEM_CTRL6_IFADCDIGGAIN_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_CTRL6 */
+#define MODEM_CTRL6_RXBRCALCDIS (0x1UL << 30) /**< RX Baudrate Calculation Disable */
+#define _MODEM_CTRL6_RXBRCALCDIS_SHIFT 30 /**< Shift value for MODEM_RXBRCALCDIS */
+#define _MODEM_CTRL6_RXBRCALCDIS_MASK 0x40000000UL /**< Bit mask for MODEM_RXBRCALCDIS */
+#define _MODEM_CTRL6_RXBRCALCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CTRL6 */
+#define MODEM_CTRL6_RXBRCALCDIS_DEFAULT (_MODEM_CTRL6_RXBRCALCDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_CTRL6 */
+
+/* Bit fields for MODEM TXBR */
+#define _MODEM_TXBR_RESETVALUE 0x00000000UL /**< Default value for MODEM_TXBR */
+#define _MODEM_TXBR_MASK 0x00FFFFFFUL /**< Mask for MODEM_TXBR */
+#define _MODEM_TXBR_TXBRNUM_SHIFT 0 /**< Shift value for MODEM_TXBRNUM */
+#define _MODEM_TXBR_TXBRNUM_MASK 0xFFFFUL /**< Bit mask for MODEM_TXBRNUM */
+#define _MODEM_TXBR_TXBRNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TXBR */
+#define MODEM_TXBR_TXBRNUM_DEFAULT (_MODEM_TXBR_TXBRNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_TXBR */
+#define _MODEM_TXBR_TXBRDEN_SHIFT 16 /**< Shift value for MODEM_TXBRDEN */
+#define _MODEM_TXBR_TXBRDEN_MASK 0xFF0000UL /**< Bit mask for MODEM_TXBRDEN */
+#define _MODEM_TXBR_TXBRDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TXBR */
+#define MODEM_TXBR_TXBRDEN_DEFAULT (_MODEM_TXBR_TXBRDEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_TXBR */
+
+/* Bit fields for MODEM RXBR */
+#define _MODEM_RXBR_RESETVALUE 0x00000000UL /**< Default value for MODEM_RXBR */
+#define _MODEM_RXBR_MASK 0x00001FFFUL /**< Mask for MODEM_RXBR */
+#define _MODEM_RXBR_RXBRNUM_SHIFT 0 /**< Shift value for MODEM_RXBRNUM */
+#define _MODEM_RXBR_RXBRNUM_MASK 0x1FUL /**< Bit mask for MODEM_RXBRNUM */
+#define _MODEM_RXBR_RXBRNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_RXBR */
+#define MODEM_RXBR_RXBRNUM_DEFAULT (_MODEM_RXBR_RXBRNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_RXBR */
+#define _MODEM_RXBR_RXBRDEN_SHIFT 5 /**< Shift value for MODEM_RXBRDEN */
+#define _MODEM_RXBR_RXBRDEN_MASK 0x3E0UL /**< Bit mask for MODEM_RXBRDEN */
+#define _MODEM_RXBR_RXBRDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_RXBR */
+#define MODEM_RXBR_RXBRDEN_DEFAULT (_MODEM_RXBR_RXBRDEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_RXBR */
+#define _MODEM_RXBR_RXBRINT_SHIFT 10 /**< Shift value for MODEM_RXBRINT */
+#define _MODEM_RXBR_RXBRINT_MASK 0x1C00UL /**< Bit mask for MODEM_RXBRINT */
+#define _MODEM_RXBR_RXBRINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_RXBR */
+#define MODEM_RXBR_RXBRINT_DEFAULT (_MODEM_RXBR_RXBRINT_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_RXBR */
+
+/* Bit fields for MODEM CF */
+#define _MODEM_CF_RESETVALUE 0x00000000UL /**< Default value for MODEM_CF */
+#define _MODEM_CF_MASK 0xCFFFFFFFUL /**< Mask for MODEM_CF */
+#define _MODEM_CF_DEC0_SHIFT 0 /**< Shift value for MODEM_DEC0 */
+#define _MODEM_CF_DEC0_MASK 0x7UL /**< Bit mask for MODEM_DEC0 */
+#define _MODEM_CF_DEC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CF */
+#define _MODEM_CF_DEC0_DF3 0x00000000UL /**< Mode DF3 for MODEM_CF */
+#define _MODEM_CF_DEC0_DF4WIDE 0x00000001UL /**< Mode DF4WIDE for MODEM_CF */
+#define _MODEM_CF_DEC0_DF4NARROW 0x00000002UL /**< Mode DF4NARROW for MODEM_CF */
+#define _MODEM_CF_DEC0_DF8WIDE 0x00000003UL /**< Mode DF8WIDE for MODEM_CF */
+#define _MODEM_CF_DEC0_DF8NARROW 0x00000004UL /**< Mode DF8NARROW for MODEM_CF */
+#define MODEM_CF_DEC0_DEFAULT (_MODEM_CF_DEC0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CF */
+#define MODEM_CF_DEC0_DF3 (_MODEM_CF_DEC0_DF3 << 0) /**< Shifted mode DF3 for MODEM_CF */
+#define MODEM_CF_DEC0_DF4WIDE (_MODEM_CF_DEC0_DF4WIDE << 0) /**< Shifted mode DF4WIDE for MODEM_CF */
+#define MODEM_CF_DEC0_DF4NARROW (_MODEM_CF_DEC0_DF4NARROW << 0) /**< Shifted mode DF4NARROW for MODEM_CF */
+#define MODEM_CF_DEC0_DF8WIDE (_MODEM_CF_DEC0_DF8WIDE << 0) /**< Shifted mode DF8WIDE for MODEM_CF */
+#define MODEM_CF_DEC0_DF8NARROW (_MODEM_CF_DEC0_DF8NARROW << 0) /**< Shifted mode DF8NARROW for MODEM_CF */
+#define _MODEM_CF_DEC1_SHIFT 3 /**< Shift value for MODEM_DEC1 */
+#define _MODEM_CF_DEC1_MASK 0x1FFF8UL /**< Bit mask for MODEM_DEC1 */
+#define _MODEM_CF_DEC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CF */
+#define MODEM_CF_DEC1_DEFAULT (_MODEM_CF_DEC1_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_CF */
+#define _MODEM_CF_DEC2_SHIFT 17 /**< Shift value for MODEM_DEC2 */
+#define _MODEM_CF_DEC2_MASK 0x7E0000UL /**< Bit mask for MODEM_DEC2 */
+#define _MODEM_CF_DEC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CF */
+#define MODEM_CF_DEC2_DEFAULT (_MODEM_CF_DEC2_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_CF */
+#define _MODEM_CF_CFOSR_SHIFT 23 /**< Shift value for MODEM_CFOSR */
+#define _MODEM_CF_CFOSR_MASK 0x3800000UL /**< Bit mask for MODEM_CFOSR */
+#define _MODEM_CF_CFOSR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CF */
+#define _MODEM_CF_CFOSR_CF7 0x00000000UL /**< Mode CF7 for MODEM_CF */
+#define _MODEM_CF_CFOSR_CF8 0x00000001UL /**< Mode CF8 for MODEM_CF */
+#define _MODEM_CF_CFOSR_CF12 0x00000002UL /**< Mode CF12 for MODEM_CF */
+#define _MODEM_CF_CFOSR_CF16 0x00000003UL /**< Mode CF16 for MODEM_CF */
+#define _MODEM_CF_CFOSR_CF32 0x00000004UL /**< Mode CF32 for MODEM_CF */
+#define _MODEM_CF_CFOSR_CF0 0x00000005UL /**< Mode CF0 for MODEM_CF */
+#define MODEM_CF_CFOSR_DEFAULT (_MODEM_CF_CFOSR_DEFAULT << 23) /**< Shifted mode DEFAULT for MODEM_CF */
+#define MODEM_CF_CFOSR_CF7 (_MODEM_CF_CFOSR_CF7 << 23) /**< Shifted mode CF7 for MODEM_CF */
+#define MODEM_CF_CFOSR_CF8 (_MODEM_CF_CFOSR_CF8 << 23) /**< Shifted mode CF8 for MODEM_CF */
+#define MODEM_CF_CFOSR_CF12 (_MODEM_CF_CFOSR_CF12 << 23) /**< Shifted mode CF12 for MODEM_CF */
+#define MODEM_CF_CFOSR_CF16 (_MODEM_CF_CFOSR_CF16 << 23) /**< Shifted mode CF16 for MODEM_CF */
+#define MODEM_CF_CFOSR_CF32 (_MODEM_CF_CFOSR_CF32 << 23) /**< Shifted mode CF32 for MODEM_CF */
+#define MODEM_CF_CFOSR_CF0 (_MODEM_CF_CFOSR_CF0 << 23) /**< Shifted mode CF0 for MODEM_CF */
+#define _MODEM_CF_DEC1GAIN_SHIFT 26 /**< Shift value for MODEM_DEC1GAIN */
+#define _MODEM_CF_DEC1GAIN_MASK 0xC000000UL /**< Bit mask for MODEM_DEC1GAIN */
+#define _MODEM_CF_DEC1GAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CF */
+#define _MODEM_CF_DEC1GAIN_ADD0 0x00000000UL /**< Mode ADD0 for MODEM_CF */
+#define _MODEM_CF_DEC1GAIN_ADD6 0x00000001UL /**< Mode ADD6 for MODEM_CF */
+#define _MODEM_CF_DEC1GAIN_ADD12 0x00000002UL /**< Mode ADD12 for MODEM_CF */
+#define MODEM_CF_DEC1GAIN_DEFAULT (_MODEM_CF_DEC1GAIN_DEFAULT << 26) /**< Shifted mode DEFAULT for MODEM_CF */
+#define MODEM_CF_DEC1GAIN_ADD0 (_MODEM_CF_DEC1GAIN_ADD0 << 26) /**< Shifted mode ADD0 for MODEM_CF */
+#define MODEM_CF_DEC1GAIN_ADD6 (_MODEM_CF_DEC1GAIN_ADD6 << 26) /**< Shifted mode ADD6 for MODEM_CF */
+#define MODEM_CF_DEC1GAIN_ADD12 (_MODEM_CF_DEC1GAIN_ADD12 << 26) /**< Shifted mode ADD12 for MODEM_CF */
+
+/* Bit fields for MODEM PRE */
+#define _MODEM_PRE_RESETVALUE 0x00000000UL /**< Default value for MODEM_PRE */
+#define _MODEM_PRE_MASK 0xFFFFFFFFUL /**< Mask for MODEM_PRE */
+#define _MODEM_PRE_BASE_SHIFT 0 /**< Shift value for MODEM_BASE */
+#define _MODEM_PRE_BASE_MASK 0xFUL /**< Bit mask for MODEM_BASE */
+#define _MODEM_PRE_BASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRE */
+#define MODEM_PRE_BASE_DEFAULT (_MODEM_PRE_BASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_PRE */
+#define _MODEM_PRE_BASEBITS_SHIFT 4 /**< Shift value for MODEM_BASEBITS */
+#define _MODEM_PRE_BASEBITS_MASK 0x30UL /**< Bit mask for MODEM_BASEBITS */
+#define _MODEM_PRE_BASEBITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRE */
+#define MODEM_PRE_BASEBITS_DEFAULT (_MODEM_PRE_BASEBITS_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_PRE */
+#define MODEM_PRE_PRESYMB4FSK (0x1UL << 6) /**< Preamble symbols 4-FSK */
+#define _MODEM_PRE_PRESYMB4FSK_SHIFT 6 /**< Shift value for MODEM_PRESYMB4FSK */
+#define _MODEM_PRE_PRESYMB4FSK_MASK 0x40UL /**< Bit mask for MODEM_PRESYMB4FSK */
+#define _MODEM_PRE_PRESYMB4FSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRE */
+#define _MODEM_PRE_PRESYMB4FSK_OUTER 0x00000000UL /**< Mode OUTER for MODEM_PRE */
+#define _MODEM_PRE_PRESYMB4FSK_INNER 0x00000001UL /**< Mode INNER for MODEM_PRE */
+#define MODEM_PRE_PRESYMB4FSK_DEFAULT (_MODEM_PRE_PRESYMB4FSK_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_PRE */
+#define MODEM_PRE_PRESYMB4FSK_OUTER (_MODEM_PRE_PRESYMB4FSK_OUTER << 6) /**< Shifted mode OUTER for MODEM_PRE */
+#define MODEM_PRE_PRESYMB4FSK_INNER (_MODEM_PRE_PRESYMB4FSK_INNER << 6) /**< Shifted mode INNER for MODEM_PRE */
+#define _MODEM_PRE_PREERRORS_SHIFT 7 /**< Shift value for MODEM_PREERRORS */
+#define _MODEM_PRE_PREERRORS_MASK 0x780UL /**< Bit mask for MODEM_PREERRORS */
+#define _MODEM_PRE_PREERRORS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRE */
+#define MODEM_PRE_PREERRORS_DEFAULT (_MODEM_PRE_PREERRORS_DEFAULT << 7) /**< Shifted mode DEFAULT for MODEM_PRE */
+#define MODEM_PRE_DSSSPRE (0x1UL << 11) /**< DSSS preamble */
+#define _MODEM_PRE_DSSSPRE_SHIFT 11 /**< Shift value for MODEM_DSSSPRE */
+#define _MODEM_PRE_DSSSPRE_MASK 0x800UL /**< Bit mask for MODEM_DSSSPRE */
+#define _MODEM_PRE_DSSSPRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRE */
+#define MODEM_PRE_DSSSPRE_DEFAULT (_MODEM_PRE_DSSSPRE_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_PRE */
+#define MODEM_PRE_SYNCSYMB4FSK (0x1UL << 12) /**< Sync symbols 4FSK */
+#define _MODEM_PRE_SYNCSYMB4FSK_SHIFT 12 /**< Shift value for MODEM_SYNCSYMB4FSK */
+#define _MODEM_PRE_SYNCSYMB4FSK_MASK 0x1000UL /**< Bit mask for MODEM_SYNCSYMB4FSK */
+#define _MODEM_PRE_SYNCSYMB4FSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRE */
+#define _MODEM_PRE_SYNCSYMB4FSK_FSK2 0x00000000UL /**< Mode FSK2 for MODEM_PRE */
+#define _MODEM_PRE_SYNCSYMB4FSK_FSK4 0x00000001UL /**< Mode FSK4 for MODEM_PRE */
+#define MODEM_PRE_SYNCSYMB4FSK_DEFAULT (_MODEM_PRE_SYNCSYMB4FSK_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_PRE */
+#define MODEM_PRE_SYNCSYMB4FSK_FSK2 (_MODEM_PRE_SYNCSYMB4FSK_FSK2 << 12) /**< Shifted mode FSK2 for MODEM_PRE */
+#define MODEM_PRE_SYNCSYMB4FSK_FSK4 (_MODEM_PRE_SYNCSYMB4FSK_FSK4 << 12) /**< Shifted mode FSK4 for MODEM_PRE */
+#define MODEM_PRE_PREAMBDETEN (0x1UL << 13) /**< Binary bit preamble det enable */
+#define _MODEM_PRE_PREAMBDETEN_SHIFT 13 /**< Shift value for MODEM_PREAMBDETEN */
+#define _MODEM_PRE_PREAMBDETEN_MASK 0x2000UL /**< Bit mask for MODEM_PREAMBDETEN */
+#define _MODEM_PRE_PREAMBDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRE */
+#define MODEM_PRE_PREAMBDETEN_DEFAULT (_MODEM_PRE_PREAMBDETEN_DEFAULT << 13) /**< Shifted mode DEFAULT for MODEM_PRE */
+#define _MODEM_PRE_PREWNDERRORS_SHIFT 14 /**< Shift value for MODEM_PREWNDERRORS */
+#define _MODEM_PRE_PREWNDERRORS_MASK 0xC000UL /**< Bit mask for MODEM_PREWNDERRORS */
+#define _MODEM_PRE_PREWNDERRORS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRE */
+#define MODEM_PRE_PREWNDERRORS_DEFAULT (_MODEM_PRE_PREWNDERRORS_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_PRE */
+#define _MODEM_PRE_TXBASES_SHIFT 16 /**< Shift value for MODEM_TXBASES */
+#define _MODEM_PRE_TXBASES_MASK 0xFFFF0000UL /**< Bit mask for MODEM_TXBASES */
+#define _MODEM_PRE_TXBASES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRE */
+#define MODEM_PRE_TXBASES_DEFAULT (_MODEM_PRE_TXBASES_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_PRE */
+
+/* Bit fields for MODEM SYNC0 */
+#define _MODEM_SYNC0_RESETVALUE 0x00000000UL /**< Default value for MODEM_SYNC0 */
+#define _MODEM_SYNC0_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SYNC0 */
+#define _MODEM_SYNC0_SYNC0_SHIFT 0 /**< Shift value for MODEM_SYNC0 */
+#define _MODEM_SYNC0_SYNC0_MASK 0xFFFFFFFFUL /**< Bit mask for MODEM_SYNC0 */
+#define _MODEM_SYNC0_SYNC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SYNC0 */
+#define MODEM_SYNC0_SYNC0_DEFAULT (_MODEM_SYNC0_SYNC0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SYNC0 */
+
+/* Bit fields for MODEM SYNC1 */
+#define _MODEM_SYNC1_RESETVALUE 0x00000000UL /**< Default value for MODEM_SYNC1 */
+#define _MODEM_SYNC1_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SYNC1 */
+#define _MODEM_SYNC1_SYNC1_SHIFT 0 /**< Shift value for MODEM_SYNC1 */
+#define _MODEM_SYNC1_SYNC1_MASK 0xFFFFFFFFUL /**< Bit mask for MODEM_SYNC1 */
+#define _MODEM_SYNC1_SYNC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SYNC1 */
+#define MODEM_SYNC1_SYNC1_DEFAULT (_MODEM_SYNC1_SYNC1_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SYNC1 */
+
+/* Bit fields for MODEM TIMING */
+#define _MODEM_TIMING_RESETVALUE 0x00000000UL /**< Default value for MODEM_TIMING */
+#define _MODEM_TIMING_MASK 0xFFFFFFFFUL /**< Mask for MODEM_TIMING */
+#define _MODEM_TIMING_TIMTHRESH_SHIFT 0 /**< Shift value for MODEM_TIMTHRESH */
+#define _MODEM_TIMING_TIMTHRESH_MASK 0xFFUL /**< Bit mask for MODEM_TIMTHRESH */
+#define _MODEM_TIMING_TIMTHRESH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TIMING */
+#define MODEM_TIMING_TIMTHRESH_DEFAULT (_MODEM_TIMING_TIMTHRESH_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_TIMING */
+#define _MODEM_TIMING_TIMINGBASES_SHIFT 8 /**< Shift value for MODEM_TIMINGBASES */
+#define _MODEM_TIMING_TIMINGBASES_MASK 0xF00UL /**< Bit mask for MODEM_TIMINGBASES */
+#define _MODEM_TIMING_TIMINGBASES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TIMING */
+#define MODEM_TIMING_TIMINGBASES_DEFAULT (_MODEM_TIMING_TIMINGBASES_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_TIMING */
+#define _MODEM_TIMING_ADDTIMSEQ_SHIFT 12 /**< Shift value for MODEM_ADDTIMSEQ */
+#define _MODEM_TIMING_ADDTIMSEQ_MASK 0xF000UL /**< Bit mask for MODEM_ADDTIMSEQ */
+#define _MODEM_TIMING_ADDTIMSEQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TIMING */
+#define MODEM_TIMING_ADDTIMSEQ_DEFAULT (_MODEM_TIMING_ADDTIMSEQ_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_TIMING */
+#define MODEM_TIMING_TIMSEQINVEN (0x1UL << 16) /**< Timing sequence inversion enable */
+#define _MODEM_TIMING_TIMSEQINVEN_SHIFT 16 /**< Shift value for MODEM_TIMSEQINVEN */
+#define _MODEM_TIMING_TIMSEQINVEN_MASK 0x10000UL /**< Bit mask for MODEM_TIMSEQINVEN */
+#define _MODEM_TIMING_TIMSEQINVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TIMING */
+#define MODEM_TIMING_TIMSEQINVEN_DEFAULT (_MODEM_TIMING_TIMSEQINVEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_TIMING */
+#define MODEM_TIMING_TIMSEQSYNC (0x1UL << 17) /**< Timing sequence part of sync-word */
+#define _MODEM_TIMING_TIMSEQSYNC_SHIFT 17 /**< Shift value for MODEM_TIMSEQSYNC */
+#define _MODEM_TIMING_TIMSEQSYNC_MASK 0x20000UL /**< Bit mask for MODEM_TIMSEQSYNC */
+#define _MODEM_TIMING_TIMSEQSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TIMING */
+#define MODEM_TIMING_TIMSEQSYNC_DEFAULT (_MODEM_TIMING_TIMSEQSYNC_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_TIMING */
+#define _MODEM_TIMING_FDM0THRESH_SHIFT 18 /**< Shift value for MODEM_FDM0THRESH */
+#define _MODEM_TIMING_FDM0THRESH_MASK 0x1C0000UL /**< Bit mask for MODEM_FDM0THRESH */
+#define _MODEM_TIMING_FDM0THRESH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TIMING */
+#define MODEM_TIMING_FDM0THRESH_DEFAULT (_MODEM_TIMING_FDM0THRESH_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_TIMING */
+#define _MODEM_TIMING_OFFSUBNUM_SHIFT 21 /**< Shift value for MODEM_OFFSUBNUM */
+#define _MODEM_TIMING_OFFSUBNUM_MASK 0x1E00000UL /**< Bit mask for MODEM_OFFSUBNUM */
+#define _MODEM_TIMING_OFFSUBNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TIMING */
+#define MODEM_TIMING_OFFSUBNUM_DEFAULT (_MODEM_TIMING_OFFSUBNUM_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_TIMING */
+#define _MODEM_TIMING_OFFSUBDEN_SHIFT 25 /**< Shift value for MODEM_OFFSUBDEN */
+#define _MODEM_TIMING_OFFSUBDEN_MASK 0x1E000000UL /**< Bit mask for MODEM_OFFSUBDEN */
+#define _MODEM_TIMING_OFFSUBDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TIMING */
+#define MODEM_TIMING_OFFSUBDEN_DEFAULT (_MODEM_TIMING_OFFSUBDEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_TIMING */
+#define MODEM_TIMING_TSAGCDEL (0x1UL << 29) /**< Timing Search AGC delay */
+#define _MODEM_TIMING_TSAGCDEL_SHIFT 29 /**< Shift value for MODEM_TSAGCDEL */
+#define _MODEM_TIMING_TSAGCDEL_MASK 0x20000000UL /**< Bit mask for MODEM_TSAGCDEL */
+#define _MODEM_TIMING_TSAGCDEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TIMING */
+#define MODEM_TIMING_TSAGCDEL_DEFAULT (_MODEM_TIMING_TSAGCDEL_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_TIMING */
+#define _MODEM_TIMING_FASTRESYNC_SHIFT 30 /**< Shift value for MODEM_FASTRESYNC */
+#define _MODEM_TIMING_FASTRESYNC_MASK 0xC0000000UL /**< Bit mask for MODEM_FASTRESYNC */
+#define _MODEM_TIMING_FASTRESYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TIMING */
+#define _MODEM_TIMING_FASTRESYNC_DIS 0x00000000UL /**< Mode DIS for MODEM_TIMING */
+#define _MODEM_TIMING_FASTRESYNC_PREDET 0x00000001UL /**< Mode PREDET for MODEM_TIMING */
+#define _MODEM_TIMING_FASTRESYNC_FRAMEDET 0x00000002UL /**< Mode FRAMEDET for MODEM_TIMING */
+#define MODEM_TIMING_FASTRESYNC_DEFAULT (_MODEM_TIMING_FASTRESYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_TIMING */
+#define MODEM_TIMING_FASTRESYNC_DIS (_MODEM_TIMING_FASTRESYNC_DIS << 30) /**< Shifted mode DIS for MODEM_TIMING */
+#define MODEM_TIMING_FASTRESYNC_PREDET (_MODEM_TIMING_FASTRESYNC_PREDET << 30) /**< Shifted mode PREDET for MODEM_TIMING */
+#define MODEM_TIMING_FASTRESYNC_FRAMEDET (_MODEM_TIMING_FASTRESYNC_FRAMEDET << 30) /**< Shifted mode FRAMEDET for MODEM_TIMING */
+
+/* Bit fields for MODEM DSSS0 */
+#define _MODEM_DSSS0_RESETVALUE 0x00000000UL /**< Default value for MODEM_DSSS0 */
+#define _MODEM_DSSS0_MASK 0xFFFFFFFFUL /**< Mask for MODEM_DSSS0 */
+#define _MODEM_DSSS0_DSSS0_SHIFT 0 /**< Shift value for MODEM_DSSS0 */
+#define _MODEM_DSSS0_DSSS0_MASK 0xFFFFFFFFUL /**< Bit mask for MODEM_DSSS0 */
+#define _MODEM_DSSS0_DSSS0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DSSS0 */
+#define MODEM_DSSS0_DSSS0_DEFAULT (_MODEM_DSSS0_DSSS0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_DSSS0 */
+
+/* Bit fields for MODEM MODINDEX */
+#define _MODEM_MODINDEX_RESETVALUE 0x00000000UL /**< Default value for MODEM_MODINDEX */
+#define _MODEM_MODINDEX_MASK 0x003F03FFUL /**< Mask for MODEM_MODINDEX */
+#define _MODEM_MODINDEX_MODINDEXM_SHIFT 0 /**< Shift value for MODEM_MODINDEXM */
+#define _MODEM_MODINDEX_MODINDEXM_MASK 0x1FUL /**< Bit mask for MODEM_MODINDEXM */
+#define _MODEM_MODINDEX_MODINDEXM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_MODINDEX */
+#define MODEM_MODINDEX_MODINDEXM_DEFAULT (_MODEM_MODINDEX_MODINDEXM_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_MODINDEX */
+#define _MODEM_MODINDEX_MODINDEXE_SHIFT 5 /**< Shift value for MODEM_MODINDEXE */
+#define _MODEM_MODINDEX_MODINDEXE_MASK 0x3E0UL /**< Bit mask for MODEM_MODINDEXE */
+#define _MODEM_MODINDEX_MODINDEXE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_MODINDEX */
+#define MODEM_MODINDEX_MODINDEXE_DEFAULT (_MODEM_MODINDEX_MODINDEXE_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_MODINDEX */
+#define _MODEM_MODINDEX_FREQGAINE_SHIFT 16 /**< Shift value for MODEM_FREQGAINE */
+#define _MODEM_MODINDEX_FREQGAINE_MASK 0x70000UL /**< Bit mask for MODEM_FREQGAINE */
+#define _MODEM_MODINDEX_FREQGAINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_MODINDEX */
+#define MODEM_MODINDEX_FREQGAINE_DEFAULT (_MODEM_MODINDEX_FREQGAINE_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_MODINDEX */
+#define _MODEM_MODINDEX_FREQGAINM_SHIFT 19 /**< Shift value for MODEM_FREQGAINM */
+#define _MODEM_MODINDEX_FREQGAINM_MASK 0x380000UL /**< Bit mask for MODEM_FREQGAINM */
+#define _MODEM_MODINDEX_FREQGAINM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_MODINDEX */
+#define MODEM_MODINDEX_FREQGAINM_DEFAULT (_MODEM_MODINDEX_FREQGAINM_DEFAULT << 19) /**< Shifted mode DEFAULT for MODEM_MODINDEX */
+
+/* Bit fields for MODEM AFC */
+#define _MODEM_AFC_RESETVALUE 0x00000000UL /**< Default value for MODEM_AFC */
+#define _MODEM_AFC_MASK 0xFFFFFC00UL /**< Mask for MODEM_AFC */
+#define _MODEM_AFC_AFCRXMODE_SHIFT 10 /**< Shift value for MODEM_AFCRXMODE */
+#define _MODEM_AFC_AFCRXMODE_MASK 0x1C00UL /**< Bit mask for MODEM_AFCRXMODE */
+#define _MODEM_AFC_AFCRXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFC */
+#define _MODEM_AFC_AFCRXMODE_DIS 0x00000000UL /**< Mode DIS for MODEM_AFC */
+#define _MODEM_AFC_AFCRXMODE_FREE 0x00000001UL /**< Mode FREE for MODEM_AFC */
+#define _MODEM_AFC_AFCRXMODE_FREEPRESTART 0x00000002UL /**< Mode FREEPRESTART for MODEM_AFC */
+#define _MODEM_AFC_AFCRXMODE_TIMLOCK 0x00000003UL /**< Mode TIMLOCK for MODEM_AFC */
+#define _MODEM_AFC_AFCRXMODE_PRELOCK 0x00000004UL /**< Mode PRELOCK for MODEM_AFC */
+#define _MODEM_AFC_AFCRXMODE_FRAMELOCK 0x00000005UL /**< Mode FRAMELOCK for MODEM_AFC */
+#define _MODEM_AFC_AFCRXMODE_FRAMELOCKPRESTART 0x00000006UL /**< Mode FRAMELOCKPRESTART for MODEM_AFC */
+#define MODEM_AFC_AFCRXMODE_DEFAULT (_MODEM_AFC_AFCRXMODE_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_AFC */
+#define MODEM_AFC_AFCRXMODE_DIS (_MODEM_AFC_AFCRXMODE_DIS << 10) /**< Shifted mode DIS for MODEM_AFC */
+#define MODEM_AFC_AFCRXMODE_FREE (_MODEM_AFC_AFCRXMODE_FREE << 10) /**< Shifted mode FREE for MODEM_AFC */
+#define MODEM_AFC_AFCRXMODE_FREEPRESTART (_MODEM_AFC_AFCRXMODE_FREEPRESTART << 10) /**< Shifted mode FREEPRESTART for MODEM_AFC */
+#define MODEM_AFC_AFCRXMODE_TIMLOCK (_MODEM_AFC_AFCRXMODE_TIMLOCK << 10) /**< Shifted mode TIMLOCK for MODEM_AFC */
+#define MODEM_AFC_AFCRXMODE_PRELOCK (_MODEM_AFC_AFCRXMODE_PRELOCK << 10) /**< Shifted mode PRELOCK for MODEM_AFC */
+#define MODEM_AFC_AFCRXMODE_FRAMELOCK (_MODEM_AFC_AFCRXMODE_FRAMELOCK << 10) /**< Shifted mode FRAMELOCK for MODEM_AFC */
+#define MODEM_AFC_AFCRXMODE_FRAMELOCKPRESTART (_MODEM_AFC_AFCRXMODE_FRAMELOCKPRESTART << 10) /**< Shifted mode FRAMELOCKPRESTART for MODEM_AFC*/
+#define _MODEM_AFC_AFCTXMODE_SHIFT 13 /**< Shift value for MODEM_AFCTXMODE */
+#define _MODEM_AFC_AFCTXMODE_MASK 0x6000UL /**< Bit mask for MODEM_AFCTXMODE */
+#define _MODEM_AFC_AFCTXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFC */
+#define _MODEM_AFC_AFCTXMODE_DIS 0x00000000UL /**< Mode DIS for MODEM_AFC */
+#define _MODEM_AFC_AFCTXMODE_PRELOCK 0x00000001UL /**< Mode PRELOCK for MODEM_AFC */
+#define _MODEM_AFC_AFCTXMODE_FRAMELOCK 0x00000002UL /**< Mode FRAMELOCK for MODEM_AFC */
+#define MODEM_AFC_AFCTXMODE_DEFAULT (_MODEM_AFC_AFCTXMODE_DEFAULT << 13) /**< Shifted mode DEFAULT for MODEM_AFC */
+#define MODEM_AFC_AFCTXMODE_DIS (_MODEM_AFC_AFCTXMODE_DIS << 13) /**< Shifted mode DIS for MODEM_AFC */
+#define MODEM_AFC_AFCTXMODE_PRELOCK (_MODEM_AFC_AFCTXMODE_PRELOCK << 13) /**< Shifted mode PRELOCK for MODEM_AFC */
+#define MODEM_AFC_AFCTXMODE_FRAMELOCK (_MODEM_AFC_AFCTXMODE_FRAMELOCK << 13) /**< Shifted mode FRAMELOCK for MODEM_AFC */
+#define MODEM_AFC_AFCRXCLR (0x1UL << 15) /**< AFCRX clear mode */
+#define _MODEM_AFC_AFCRXCLR_SHIFT 15 /**< Shift value for MODEM_AFCRXCLR */
+#define _MODEM_AFC_AFCRXCLR_MASK 0x8000UL /**< Bit mask for MODEM_AFCRXCLR */
+#define _MODEM_AFC_AFCRXCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFC */
+#define MODEM_AFC_AFCRXCLR_DEFAULT (_MODEM_AFC_AFCRXCLR_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_AFC */
+#define _MODEM_AFC_AFCDEL_SHIFT 16 /**< Shift value for MODEM_AFCDEL */
+#define _MODEM_AFC_AFCDEL_MASK 0x1F0000UL /**< Bit mask for MODEM_AFCDEL */
+#define _MODEM_AFC_AFCDEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFC */
+#define MODEM_AFC_AFCDEL_DEFAULT (_MODEM_AFC_AFCDEL_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_AFC */
+#define _MODEM_AFC_AFCAVGPER_SHIFT 21 /**< Shift value for MODEM_AFCAVGPER */
+#define _MODEM_AFC_AFCAVGPER_MASK 0xE00000UL /**< Bit mask for MODEM_AFCAVGPER */
+#define _MODEM_AFC_AFCAVGPER_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFC */
+#define MODEM_AFC_AFCAVGPER_DEFAULT (_MODEM_AFC_AFCAVGPER_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_AFC */
+#define MODEM_AFC_AFCLIMRESET (0x1UL << 24) /**< Reset AFCADJRX value */
+#define _MODEM_AFC_AFCLIMRESET_SHIFT 24 /**< Shift value for MODEM_AFCLIMRESET */
+#define _MODEM_AFC_AFCLIMRESET_MASK 0x1000000UL /**< Bit mask for MODEM_AFCLIMRESET */
+#define _MODEM_AFC_AFCLIMRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFC */
+#define MODEM_AFC_AFCLIMRESET_DEFAULT (_MODEM_AFC_AFCLIMRESET_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_AFC */
+#define MODEM_AFC_AFCONESHOT (0x1UL << 25) /**< AFC One-Shot feature */
+#define _MODEM_AFC_AFCONESHOT_SHIFT 25 /**< Shift value for MODEM_AFCONESHOT */
+#define _MODEM_AFC_AFCONESHOT_MASK 0x2000000UL /**< Bit mask for MODEM_AFCONESHOT */
+#define _MODEM_AFC_AFCONESHOT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFC */
+#define MODEM_AFC_AFCONESHOT_DEFAULT (_MODEM_AFC_AFCONESHOT_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_AFC */
+#define MODEM_AFC_AFCENINTCOMP (0x1UL << 26) /**< Internal frequency offset compensation */
+#define _MODEM_AFC_AFCENINTCOMP_SHIFT 26 /**< Shift value for MODEM_AFCENINTCOMP */
+#define _MODEM_AFC_AFCENINTCOMP_MASK 0x4000000UL /**< Bit mask for MODEM_AFCENINTCOMP */
+#define _MODEM_AFC_AFCENINTCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFC */
+#define MODEM_AFC_AFCENINTCOMP_DEFAULT (_MODEM_AFC_AFCENINTCOMP_DEFAULT << 26) /**< Shifted mode DEFAULT for MODEM_AFC */
+#define MODEM_AFC_AFCDSAFREQOFFEST (0x1UL << 27) /**< Consider frequency offset estimation */
+#define _MODEM_AFC_AFCDSAFREQOFFEST_SHIFT 27 /**< Shift value for MODEM_AFCDSAFREQOFFEST */
+#define _MODEM_AFC_AFCDSAFREQOFFEST_MASK 0x8000000UL /**< Bit mask for MODEM_AFCDSAFREQOFFEST */
+#define _MODEM_AFC_AFCDSAFREQOFFEST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFC */
+#define MODEM_AFC_AFCDSAFREQOFFEST_DEFAULT (_MODEM_AFC_AFCDSAFREQOFFEST_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_AFC */
+#define MODEM_AFC_AFCDELDET (0x1UL << 28) /**< Delay Detection state machine */
+#define _MODEM_AFC_AFCDELDET_SHIFT 28 /**< Shift value for MODEM_AFCDELDET */
+#define _MODEM_AFC_AFCDELDET_MASK 0x10000000UL /**< Bit mask for MODEM_AFCDELDET */
+#define _MODEM_AFC_AFCDELDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFC */
+#define MODEM_AFC_AFCDELDET_DEFAULT (_MODEM_AFC_AFCDELDET_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_AFC */
+#define _MODEM_AFC_AFCGEAR_SHIFT 29 /**< Shift value for MODEM_AFCGEAR */
+#define _MODEM_AFC_AFCGEAR_MASK 0x60000000UL /**< Bit mask for MODEM_AFCGEAR */
+#define _MODEM_AFC_AFCGEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFC */
+#define MODEM_AFC_AFCGEAR_DEFAULT (_MODEM_AFC_AFCGEAR_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_AFC */
+#define MODEM_AFC_DISAFCCTE (0x1UL << 31) /**< Disable AFC in AoX CTE */
+#define _MODEM_AFC_DISAFCCTE_SHIFT 31 /**< Shift value for MODEM_DISAFCCTE */
+#define _MODEM_AFC_DISAFCCTE_MASK 0x80000000UL /**< Bit mask for MODEM_DISAFCCTE */
+#define _MODEM_AFC_DISAFCCTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFC */
+#define MODEM_AFC_DISAFCCTE_DEFAULT (_MODEM_AFC_DISAFCCTE_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_AFC */
+
+/* Bit fields for MODEM AFCADJLIM */
+#define _MODEM_AFCADJLIM_RESETVALUE 0x00000000UL /**< Default value for MODEM_AFCADJLIM */
+#define _MODEM_AFCADJLIM_MASK 0x0003FFFFUL /**< Mask for MODEM_AFCADJLIM */
+#define _MODEM_AFCADJLIM_AFCADJLIM_SHIFT 0 /**< Shift value for MODEM_AFCADJLIM */
+#define _MODEM_AFCADJLIM_AFCADJLIM_MASK 0x3FFFFUL /**< Bit mask for MODEM_AFCADJLIM */
+#define _MODEM_AFCADJLIM_AFCADJLIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AFCADJLIM */
+#define MODEM_AFCADJLIM_AFCADJLIM_DEFAULT (_MODEM_AFCADJLIM_AFCADJLIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_AFCADJLIM */
+
+/* Bit fields for MODEM SHAPING0 */
+#define _MODEM_SHAPING0_RESETVALUE 0x22130A04UL /**< Default value for MODEM_SHAPING0 */
+#define _MODEM_SHAPING0_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING0 */
+#define _MODEM_SHAPING0_COEFF0_SHIFT 0 /**< Shift value for MODEM_COEFF0 */
+#define _MODEM_SHAPING0_COEFF0_MASK 0xFFUL /**< Bit mask for MODEM_COEFF0 */
+#define _MODEM_SHAPING0_COEFF0_DEFAULT 0x00000004UL /**< Mode DEFAULT for MODEM_SHAPING0 */
+#define MODEM_SHAPING0_COEFF0_DEFAULT (_MODEM_SHAPING0_COEFF0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING0 */
+#define _MODEM_SHAPING0_COEFF1_SHIFT 8 /**< Shift value for MODEM_COEFF1 */
+#define _MODEM_SHAPING0_COEFF1_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF1 */
+#define _MODEM_SHAPING0_COEFF1_DEFAULT 0x0000000AUL /**< Mode DEFAULT for MODEM_SHAPING0 */
+#define MODEM_SHAPING0_COEFF1_DEFAULT (_MODEM_SHAPING0_COEFF1_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING0 */
+#define _MODEM_SHAPING0_COEFF2_SHIFT 16 /**< Shift value for MODEM_COEFF2 */
+#define _MODEM_SHAPING0_COEFF2_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF2 */
+#define _MODEM_SHAPING0_COEFF2_DEFAULT 0x00000013UL /**< Mode DEFAULT for MODEM_SHAPING0 */
+#define MODEM_SHAPING0_COEFF2_DEFAULT (_MODEM_SHAPING0_COEFF2_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING0 */
+#define _MODEM_SHAPING0_COEFF3_SHIFT 24 /**< Shift value for MODEM_COEFF3 */
+#define _MODEM_SHAPING0_COEFF3_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF3 */
+#define _MODEM_SHAPING0_COEFF3_DEFAULT 0x00000022UL /**< Mode DEFAULT for MODEM_SHAPING0 */
+#define MODEM_SHAPING0_COEFF3_DEFAULT (_MODEM_SHAPING0_COEFF3_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING0 */
+
+/* Bit fields for MODEM SHAPING1 */
+#define _MODEM_SHAPING1_RESETVALUE 0x4F4A4132UL /**< Default value for MODEM_SHAPING1 */
+#define _MODEM_SHAPING1_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING1 */
+#define _MODEM_SHAPING1_COEFF4_SHIFT 0 /**< Shift value for MODEM_COEFF4 */
+#define _MODEM_SHAPING1_COEFF4_MASK 0xFFUL /**< Bit mask for MODEM_COEFF4 */
+#define _MODEM_SHAPING1_COEFF4_DEFAULT 0x00000032UL /**< Mode DEFAULT for MODEM_SHAPING1 */
+#define MODEM_SHAPING1_COEFF4_DEFAULT (_MODEM_SHAPING1_COEFF4_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING1 */
+#define _MODEM_SHAPING1_COEFF5_SHIFT 8 /**< Shift value for MODEM_COEFF5 */
+#define _MODEM_SHAPING1_COEFF5_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF5 */
+#define _MODEM_SHAPING1_COEFF5_DEFAULT 0x00000041UL /**< Mode DEFAULT for MODEM_SHAPING1 */
+#define MODEM_SHAPING1_COEFF5_DEFAULT (_MODEM_SHAPING1_COEFF5_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING1 */
+#define _MODEM_SHAPING1_COEFF6_SHIFT 16 /**< Shift value for MODEM_COEFF6 */
+#define _MODEM_SHAPING1_COEFF6_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF6 */
+#define _MODEM_SHAPING1_COEFF6_DEFAULT 0x0000004AUL /**< Mode DEFAULT for MODEM_SHAPING1 */
+#define MODEM_SHAPING1_COEFF6_DEFAULT (_MODEM_SHAPING1_COEFF6_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING1 */
+#define _MODEM_SHAPING1_COEFF7_SHIFT 24 /**< Shift value for MODEM_COEFF7 */
+#define _MODEM_SHAPING1_COEFF7_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF7 */
+#define _MODEM_SHAPING1_COEFF7_DEFAULT 0x0000004FUL /**< Mode DEFAULT for MODEM_SHAPING1 */
+#define MODEM_SHAPING1_COEFF7_DEFAULT (_MODEM_SHAPING1_COEFF7_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING1 */
+
+/* Bit fields for MODEM SHAPING2 */
+#define _MODEM_SHAPING2_RESETVALUE 0x00000000UL /**< Default value for MODEM_SHAPING2 */
+#define _MODEM_SHAPING2_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING2 */
+#define _MODEM_SHAPING2_COEFF8_SHIFT 0 /**< Shift value for MODEM_COEFF8 */
+#define _MODEM_SHAPING2_COEFF8_MASK 0xFFUL /**< Bit mask for MODEM_COEFF8 */
+#define _MODEM_SHAPING2_COEFF8_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING2 */
+#define MODEM_SHAPING2_COEFF8_DEFAULT (_MODEM_SHAPING2_COEFF8_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING2 */
+#define _MODEM_SHAPING2_COEFF9_SHIFT 8 /**< Shift value for MODEM_COEFF9 */
+#define _MODEM_SHAPING2_COEFF9_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF9 */
+#define _MODEM_SHAPING2_COEFF9_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING2 */
+#define MODEM_SHAPING2_COEFF9_DEFAULT (_MODEM_SHAPING2_COEFF9_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING2 */
+#define _MODEM_SHAPING2_COEFF10_SHIFT 16 /**< Shift value for MODEM_COEFF10 */
+#define _MODEM_SHAPING2_COEFF10_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF10 */
+#define _MODEM_SHAPING2_COEFF10_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING2 */
+#define MODEM_SHAPING2_COEFF10_DEFAULT (_MODEM_SHAPING2_COEFF10_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING2 */
+#define _MODEM_SHAPING2_COEFF11_SHIFT 24 /**< Shift value for MODEM_COEFF11 */
+#define _MODEM_SHAPING2_COEFF11_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF11 */
+#define _MODEM_SHAPING2_COEFF11_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING2 */
+#define MODEM_SHAPING2_COEFF11_DEFAULT (_MODEM_SHAPING2_COEFF11_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING2 */
+
+/* Bit fields for MODEM SHAPING3 */
+#define _MODEM_SHAPING3_RESETVALUE 0x00000000UL /**< Default value for MODEM_SHAPING3 */
+#define _MODEM_SHAPING3_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING3 */
+#define _MODEM_SHAPING3_COEFF12_SHIFT 0 /**< Shift value for MODEM_COEFF12 */
+#define _MODEM_SHAPING3_COEFF12_MASK 0xFFUL /**< Bit mask for MODEM_COEFF12 */
+#define _MODEM_SHAPING3_COEFF12_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING3 */
+#define MODEM_SHAPING3_COEFF12_DEFAULT (_MODEM_SHAPING3_COEFF12_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING3 */
+#define _MODEM_SHAPING3_COEFF13_SHIFT 8 /**< Shift value for MODEM_COEFF13 */
+#define _MODEM_SHAPING3_COEFF13_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF13 */
+#define _MODEM_SHAPING3_COEFF13_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING3 */
+#define MODEM_SHAPING3_COEFF13_DEFAULT (_MODEM_SHAPING3_COEFF13_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING3 */
+#define _MODEM_SHAPING3_COEFF14_SHIFT 16 /**< Shift value for MODEM_COEFF14 */
+#define _MODEM_SHAPING3_COEFF14_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF14 */
+#define _MODEM_SHAPING3_COEFF14_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING3 */
+#define MODEM_SHAPING3_COEFF14_DEFAULT (_MODEM_SHAPING3_COEFF14_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING3 */
+#define _MODEM_SHAPING3_COEFF15_SHIFT 24 /**< Shift value for MODEM_COEFF15 */
+#define _MODEM_SHAPING3_COEFF15_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF15 */
+#define _MODEM_SHAPING3_COEFF15_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING3 */
+#define MODEM_SHAPING3_COEFF15_DEFAULT (_MODEM_SHAPING3_COEFF15_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING3 */
+
+/* Bit fields for MODEM SHAPING4 */
+#define _MODEM_SHAPING4_RESETVALUE 0x00000000UL /**< Default value for MODEM_SHAPING4 */
+#define _MODEM_SHAPING4_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING4 */
+#define _MODEM_SHAPING4_COEFF16_SHIFT 0 /**< Shift value for MODEM_COEFF16 */
+#define _MODEM_SHAPING4_COEFF16_MASK 0xFFUL /**< Bit mask for MODEM_COEFF16 */
+#define _MODEM_SHAPING4_COEFF16_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING4 */
+#define MODEM_SHAPING4_COEFF16_DEFAULT (_MODEM_SHAPING4_COEFF16_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING4 */
+#define _MODEM_SHAPING4_COEFF17_SHIFT 8 /**< Shift value for MODEM_COEFF17 */
+#define _MODEM_SHAPING4_COEFF17_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF17 */
+#define _MODEM_SHAPING4_COEFF17_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING4 */
+#define MODEM_SHAPING4_COEFF17_DEFAULT (_MODEM_SHAPING4_COEFF17_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING4 */
+#define _MODEM_SHAPING4_COEFF18_SHIFT 16 /**< Shift value for MODEM_COEFF18 */
+#define _MODEM_SHAPING4_COEFF18_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF18 */
+#define _MODEM_SHAPING4_COEFF18_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING4 */
+#define MODEM_SHAPING4_COEFF18_DEFAULT (_MODEM_SHAPING4_COEFF18_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING4 */
+#define _MODEM_SHAPING4_COEFF19_SHIFT 24 /**< Shift value for MODEM_COEFF19 */
+#define _MODEM_SHAPING4_COEFF19_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF19 */
+#define _MODEM_SHAPING4_COEFF19_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING4 */
+#define MODEM_SHAPING4_COEFF19_DEFAULT (_MODEM_SHAPING4_COEFF19_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING4 */
+
+/* Bit fields for MODEM SHAPING5 */
+#define _MODEM_SHAPING5_RESETVALUE 0x00000000UL /**< Default value for MODEM_SHAPING5 */
+#define _MODEM_SHAPING5_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING5 */
+#define _MODEM_SHAPING5_COEFF20_SHIFT 0 /**< Shift value for MODEM_COEFF20 */
+#define _MODEM_SHAPING5_COEFF20_MASK 0xFFUL /**< Bit mask for MODEM_COEFF20 */
+#define _MODEM_SHAPING5_COEFF20_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING5 */
+#define MODEM_SHAPING5_COEFF20_DEFAULT (_MODEM_SHAPING5_COEFF20_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING5 */
+#define _MODEM_SHAPING5_COEFF21_SHIFT 8 /**< Shift value for MODEM_COEFF21 */
+#define _MODEM_SHAPING5_COEFF21_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF21 */
+#define _MODEM_SHAPING5_COEFF21_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING5 */
+#define MODEM_SHAPING5_COEFF21_DEFAULT (_MODEM_SHAPING5_COEFF21_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING5 */
+#define _MODEM_SHAPING5_COEFF22_SHIFT 16 /**< Shift value for MODEM_COEFF22 */
+#define _MODEM_SHAPING5_COEFF22_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF22 */
+#define _MODEM_SHAPING5_COEFF22_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING5 */
+#define MODEM_SHAPING5_COEFF22_DEFAULT (_MODEM_SHAPING5_COEFF22_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING5 */
+#define _MODEM_SHAPING5_COEFF23_SHIFT 24 /**< Shift value for MODEM_COEFF23 */
+#define _MODEM_SHAPING5_COEFF23_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF23 */
+#define _MODEM_SHAPING5_COEFF23_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING5 */
+#define MODEM_SHAPING5_COEFF23_DEFAULT (_MODEM_SHAPING5_COEFF23_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING5 */
+
+/* Bit fields for MODEM SHAPING6 */
+#define _MODEM_SHAPING6_RESETVALUE 0x00000000UL /**< Default value for MODEM_SHAPING6 */
+#define _MODEM_SHAPING6_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING6 */
+#define _MODEM_SHAPING6_COEFF24_SHIFT 0 /**< Shift value for MODEM_COEFF24 */
+#define _MODEM_SHAPING6_COEFF24_MASK 0xFFUL /**< Bit mask for MODEM_COEFF24 */
+#define _MODEM_SHAPING6_COEFF24_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING6 */
+#define MODEM_SHAPING6_COEFF24_DEFAULT (_MODEM_SHAPING6_COEFF24_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING6 */
+#define _MODEM_SHAPING6_COEFF25_SHIFT 8 /**< Shift value for MODEM_COEFF25 */
+#define _MODEM_SHAPING6_COEFF25_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF25 */
+#define _MODEM_SHAPING6_COEFF25_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING6 */
+#define MODEM_SHAPING6_COEFF25_DEFAULT (_MODEM_SHAPING6_COEFF25_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING6 */
+#define _MODEM_SHAPING6_COEFF26_SHIFT 16 /**< Shift value for MODEM_COEFF26 */
+#define _MODEM_SHAPING6_COEFF26_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF26 */
+#define _MODEM_SHAPING6_COEFF26_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING6 */
+#define MODEM_SHAPING6_COEFF26_DEFAULT (_MODEM_SHAPING6_COEFF26_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING6 */
+#define _MODEM_SHAPING6_COEFF27_SHIFT 24 /**< Shift value for MODEM_COEFF27 */
+#define _MODEM_SHAPING6_COEFF27_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF27 */
+#define _MODEM_SHAPING6_COEFF27_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING6 */
+#define MODEM_SHAPING6_COEFF27_DEFAULT (_MODEM_SHAPING6_COEFF27_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING6 */
+
+/* Bit fields for MODEM SHAPING7 */
+#define _MODEM_SHAPING7_RESETVALUE 0x00000000UL /**< Default value for MODEM_SHAPING7 */
+#define _MODEM_SHAPING7_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING7 */
+#define _MODEM_SHAPING7_COEFF28_SHIFT 0 /**< Shift value for MODEM_COEFF28 */
+#define _MODEM_SHAPING7_COEFF28_MASK 0xFFUL /**< Bit mask for MODEM_COEFF28 */
+#define _MODEM_SHAPING7_COEFF28_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING7 */
+#define MODEM_SHAPING7_COEFF28_DEFAULT (_MODEM_SHAPING7_COEFF28_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING7 */
+#define _MODEM_SHAPING7_COEFF29_SHIFT 8 /**< Shift value for MODEM_COEFF29 */
+#define _MODEM_SHAPING7_COEFF29_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF29 */
+#define _MODEM_SHAPING7_COEFF29_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING7 */
+#define MODEM_SHAPING7_COEFF29_DEFAULT (_MODEM_SHAPING7_COEFF29_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING7 */
+#define _MODEM_SHAPING7_COEFF30_SHIFT 16 /**< Shift value for MODEM_COEFF30 */
+#define _MODEM_SHAPING7_COEFF30_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF30 */
+#define _MODEM_SHAPING7_COEFF30_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING7 */
+#define MODEM_SHAPING7_COEFF30_DEFAULT (_MODEM_SHAPING7_COEFF30_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING7 */
+#define _MODEM_SHAPING7_COEFF31_SHIFT 24 /**< Shift value for MODEM_COEFF31 */
+#define _MODEM_SHAPING7_COEFF31_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF31 */
+#define _MODEM_SHAPING7_COEFF31_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING7 */
+#define MODEM_SHAPING7_COEFF31_DEFAULT (_MODEM_SHAPING7_COEFF31_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING7 */
+
+/* Bit fields for MODEM SHAPING8 */
+#define _MODEM_SHAPING8_RESETVALUE 0x00000000UL /**< Default value for MODEM_SHAPING8 */
+#define _MODEM_SHAPING8_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING8 */
+#define _MODEM_SHAPING8_COEFF32_SHIFT 0 /**< Shift value for MODEM_COEFF32 */
+#define _MODEM_SHAPING8_COEFF32_MASK 0xFFUL /**< Bit mask for MODEM_COEFF32 */
+#define _MODEM_SHAPING8_COEFF32_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING8 */
+#define MODEM_SHAPING8_COEFF32_DEFAULT (_MODEM_SHAPING8_COEFF32_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING8 */
+#define _MODEM_SHAPING8_COEFF33_SHIFT 8 /**< Shift value for MODEM_COEFF33 */
+#define _MODEM_SHAPING8_COEFF33_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF33 */
+#define _MODEM_SHAPING8_COEFF33_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING8 */
+#define MODEM_SHAPING8_COEFF33_DEFAULT (_MODEM_SHAPING8_COEFF33_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING8 */
+#define _MODEM_SHAPING8_COEFF34_SHIFT 16 /**< Shift value for MODEM_COEFF34 */
+#define _MODEM_SHAPING8_COEFF34_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF34 */
+#define _MODEM_SHAPING8_COEFF34_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING8 */
+#define MODEM_SHAPING8_COEFF34_DEFAULT (_MODEM_SHAPING8_COEFF34_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING8 */
+#define _MODEM_SHAPING8_COEFF35_SHIFT 24 /**< Shift value for MODEM_COEFF35 */
+#define _MODEM_SHAPING8_COEFF35_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF35 */
+#define _MODEM_SHAPING8_COEFF35_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING8 */
+#define MODEM_SHAPING8_COEFF35_DEFAULT (_MODEM_SHAPING8_COEFF35_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING8 */
+
+/* Bit fields for MODEM SHAPING9 */
+#define _MODEM_SHAPING9_RESETVALUE 0x00000000UL /**< Default value for MODEM_SHAPING9 */
+#define _MODEM_SHAPING9_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING9 */
+#define _MODEM_SHAPING9_COEFF36_SHIFT 0 /**< Shift value for MODEM_COEFF36 */
+#define _MODEM_SHAPING9_COEFF36_MASK 0xFFUL /**< Bit mask for MODEM_COEFF36 */
+#define _MODEM_SHAPING9_COEFF36_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING9 */
+#define MODEM_SHAPING9_COEFF36_DEFAULT (_MODEM_SHAPING9_COEFF36_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING9 */
+#define _MODEM_SHAPING9_COEFF37_SHIFT 8 /**< Shift value for MODEM_COEFF37 */
+#define _MODEM_SHAPING9_COEFF37_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF37 */
+#define _MODEM_SHAPING9_COEFF37_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING9 */
+#define MODEM_SHAPING9_COEFF37_DEFAULT (_MODEM_SHAPING9_COEFF37_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING9 */
+#define _MODEM_SHAPING9_COEFF38_SHIFT 16 /**< Shift value for MODEM_COEFF38 */
+#define _MODEM_SHAPING9_COEFF38_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF38 */
+#define _MODEM_SHAPING9_COEFF38_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING9 */
+#define MODEM_SHAPING9_COEFF38_DEFAULT (_MODEM_SHAPING9_COEFF38_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING9 */
+#define _MODEM_SHAPING9_COEFF39_SHIFT 24 /**< Shift value for MODEM_COEFF39 */
+#define _MODEM_SHAPING9_COEFF39_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF39 */
+#define _MODEM_SHAPING9_COEFF39_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING9 */
+#define MODEM_SHAPING9_COEFF39_DEFAULT (_MODEM_SHAPING9_COEFF39_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING9 */
+
+/* Bit fields for MODEM SHAPING10 */
+#define _MODEM_SHAPING10_RESETVALUE 0x00000000UL /**< Default value for MODEM_SHAPING10 */
+#define _MODEM_SHAPING10_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING10 */
+#define _MODEM_SHAPING10_COEFF40_SHIFT 0 /**< Shift value for MODEM_COEFF40 */
+#define _MODEM_SHAPING10_COEFF40_MASK 0xFFUL /**< Bit mask for MODEM_COEFF40 */
+#define _MODEM_SHAPING10_COEFF40_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING10 */
+#define MODEM_SHAPING10_COEFF40_DEFAULT (_MODEM_SHAPING10_COEFF40_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING10 */
+#define _MODEM_SHAPING10_COEFF41_SHIFT 8 /**< Shift value for MODEM_COEFF41 */
+#define _MODEM_SHAPING10_COEFF41_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF41 */
+#define _MODEM_SHAPING10_COEFF41_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING10 */
+#define MODEM_SHAPING10_COEFF41_DEFAULT (_MODEM_SHAPING10_COEFF41_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING10 */
+#define _MODEM_SHAPING10_COEFF42_SHIFT 16 /**< Shift value for MODEM_COEFF42 */
+#define _MODEM_SHAPING10_COEFF42_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF42 */
+#define _MODEM_SHAPING10_COEFF42_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING10 */
+#define MODEM_SHAPING10_COEFF42_DEFAULT (_MODEM_SHAPING10_COEFF42_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING10 */
+#define _MODEM_SHAPING10_COEFF43_SHIFT 24 /**< Shift value for MODEM_COEFF43 */
+#define _MODEM_SHAPING10_COEFF43_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF43 */
+#define _MODEM_SHAPING10_COEFF43_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING10 */
+#define MODEM_SHAPING10_COEFF43_DEFAULT (_MODEM_SHAPING10_COEFF43_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING10 */
+
+/* Bit fields for MODEM SHAPING11 */
+#define _MODEM_SHAPING11_RESETVALUE 0x00000000UL /**< Default value for MODEM_SHAPING11 */
+#define _MODEM_SHAPING11_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING11 */
+#define _MODEM_SHAPING11_COEFF44_SHIFT 0 /**< Shift value for MODEM_COEFF44 */
+#define _MODEM_SHAPING11_COEFF44_MASK 0xFFUL /**< Bit mask for MODEM_COEFF44 */
+#define _MODEM_SHAPING11_COEFF44_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING11 */
+#define MODEM_SHAPING11_COEFF44_DEFAULT (_MODEM_SHAPING11_COEFF44_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING11 */
+#define _MODEM_SHAPING11_COEFF45_SHIFT 8 /**< Shift value for MODEM_COEFF45 */
+#define _MODEM_SHAPING11_COEFF45_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF45 */
+#define _MODEM_SHAPING11_COEFF45_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING11 */
+#define MODEM_SHAPING11_COEFF45_DEFAULT (_MODEM_SHAPING11_COEFF45_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING11 */
+#define _MODEM_SHAPING11_COEFF46_SHIFT 16 /**< Shift value for MODEM_COEFF46 */
+#define _MODEM_SHAPING11_COEFF46_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF46 */
+#define _MODEM_SHAPING11_COEFF46_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING11 */
+#define MODEM_SHAPING11_COEFF46_DEFAULT (_MODEM_SHAPING11_COEFF46_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING11 */
+#define _MODEM_SHAPING11_COEFF47_SHIFT 24 /**< Shift value for MODEM_COEFF47 */
+#define _MODEM_SHAPING11_COEFF47_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF47 */
+#define _MODEM_SHAPING11_COEFF47_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING11 */
+#define MODEM_SHAPING11_COEFF47_DEFAULT (_MODEM_SHAPING11_COEFF47_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING11 */
+
+/* Bit fields for MODEM SHAPING12 */
+#define _MODEM_SHAPING12_RESETVALUE 0x00000000UL /**< Default value for MODEM_SHAPING12 */
+#define _MODEM_SHAPING12_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING12 */
+#define _MODEM_SHAPING12_COEFF48_SHIFT 0 /**< Shift value for MODEM_COEFF48 */
+#define _MODEM_SHAPING12_COEFF48_MASK 0xFFUL /**< Bit mask for MODEM_COEFF48 */
+#define _MODEM_SHAPING12_COEFF48_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING12 */
+#define MODEM_SHAPING12_COEFF48_DEFAULT (_MODEM_SHAPING12_COEFF48_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING12 */
+#define _MODEM_SHAPING12_COEFF49_SHIFT 8 /**< Shift value for MODEM_COEFF49 */
+#define _MODEM_SHAPING12_COEFF49_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF49 */
+#define _MODEM_SHAPING12_COEFF49_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING12 */
+#define MODEM_SHAPING12_COEFF49_DEFAULT (_MODEM_SHAPING12_COEFF49_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING12 */
+#define _MODEM_SHAPING12_COEFF50_SHIFT 16 /**< Shift value for MODEM_COEFF50 */
+#define _MODEM_SHAPING12_COEFF50_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF50 */
+#define _MODEM_SHAPING12_COEFF50_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING12 */
+#define MODEM_SHAPING12_COEFF50_DEFAULT (_MODEM_SHAPING12_COEFF50_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING12 */
+#define _MODEM_SHAPING12_COEFF51_SHIFT 24 /**< Shift value for MODEM_COEFF51 */
+#define _MODEM_SHAPING12_COEFF51_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF51 */
+#define _MODEM_SHAPING12_COEFF51_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING12 */
+#define MODEM_SHAPING12_COEFF51_DEFAULT (_MODEM_SHAPING12_COEFF51_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING12 */
+
+/* Bit fields for MODEM SHAPING13 */
+#define _MODEM_SHAPING13_RESETVALUE 0x00000000UL /**< Default value for MODEM_SHAPING13 */
+#define _MODEM_SHAPING13_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING13 */
+#define _MODEM_SHAPING13_COEFF52_SHIFT 0 /**< Shift value for MODEM_COEFF52 */
+#define _MODEM_SHAPING13_COEFF52_MASK 0xFFUL /**< Bit mask for MODEM_COEFF52 */
+#define _MODEM_SHAPING13_COEFF52_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING13 */
+#define MODEM_SHAPING13_COEFF52_DEFAULT (_MODEM_SHAPING13_COEFF52_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING13 */
+#define _MODEM_SHAPING13_COEFF53_SHIFT 8 /**< Shift value for MODEM_COEFF53 */
+#define _MODEM_SHAPING13_COEFF53_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF53 */
+#define _MODEM_SHAPING13_COEFF53_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING13 */
+#define MODEM_SHAPING13_COEFF53_DEFAULT (_MODEM_SHAPING13_COEFF53_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING13 */
+#define _MODEM_SHAPING13_COEFF54_SHIFT 16 /**< Shift value for MODEM_COEFF54 */
+#define _MODEM_SHAPING13_COEFF54_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF54 */
+#define _MODEM_SHAPING13_COEFF54_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING13 */
+#define MODEM_SHAPING13_COEFF54_DEFAULT (_MODEM_SHAPING13_COEFF54_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING13 */
+#define _MODEM_SHAPING13_COEFF55_SHIFT 24 /**< Shift value for MODEM_COEFF55 */
+#define _MODEM_SHAPING13_COEFF55_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF55 */
+#define _MODEM_SHAPING13_COEFF55_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING13 */
+#define MODEM_SHAPING13_COEFF55_DEFAULT (_MODEM_SHAPING13_COEFF55_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING13 */
+
+/* Bit fields for MODEM SHAPING14 */
+#define _MODEM_SHAPING14_RESETVALUE 0x00000000UL /**< Default value for MODEM_SHAPING14 */
+#define _MODEM_SHAPING14_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING14 */
+#define _MODEM_SHAPING14_COEFF56_SHIFT 0 /**< Shift value for MODEM_COEFF56 */
+#define _MODEM_SHAPING14_COEFF56_MASK 0xFFUL /**< Bit mask for MODEM_COEFF56 */
+#define _MODEM_SHAPING14_COEFF56_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING14 */
+#define MODEM_SHAPING14_COEFF56_DEFAULT (_MODEM_SHAPING14_COEFF56_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING14 */
+#define _MODEM_SHAPING14_COEFF57_SHIFT 8 /**< Shift value for MODEM_COEFF57 */
+#define _MODEM_SHAPING14_COEFF57_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF57 */
+#define _MODEM_SHAPING14_COEFF57_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING14 */
+#define MODEM_SHAPING14_COEFF57_DEFAULT (_MODEM_SHAPING14_COEFF57_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING14 */
+#define _MODEM_SHAPING14_COEFF58_SHIFT 16 /**< Shift value for MODEM_COEFF58 */
+#define _MODEM_SHAPING14_COEFF58_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF58 */
+#define _MODEM_SHAPING14_COEFF58_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING14 */
+#define MODEM_SHAPING14_COEFF58_DEFAULT (_MODEM_SHAPING14_COEFF58_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING14 */
+#define _MODEM_SHAPING14_COEFF59_SHIFT 24 /**< Shift value for MODEM_COEFF59 */
+#define _MODEM_SHAPING14_COEFF59_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF59 */
+#define _MODEM_SHAPING14_COEFF59_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING14 */
+#define MODEM_SHAPING14_COEFF59_DEFAULT (_MODEM_SHAPING14_COEFF59_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING14 */
+
+/* Bit fields for MODEM SHAPING15 */
+#define _MODEM_SHAPING15_RESETVALUE 0x00000000UL /**< Default value for MODEM_SHAPING15 */
+#define _MODEM_SHAPING15_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SHAPING15 */
+#define _MODEM_SHAPING15_COEFF60_SHIFT 0 /**< Shift value for MODEM_COEFF60 */
+#define _MODEM_SHAPING15_COEFF60_MASK 0xFFUL /**< Bit mask for MODEM_COEFF60 */
+#define _MODEM_SHAPING15_COEFF60_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING15 */
+#define MODEM_SHAPING15_COEFF60_DEFAULT (_MODEM_SHAPING15_COEFF60_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SHAPING15 */
+#define _MODEM_SHAPING15_COEFF61_SHIFT 8 /**< Shift value for MODEM_COEFF61 */
+#define _MODEM_SHAPING15_COEFF61_MASK 0xFF00UL /**< Bit mask for MODEM_COEFF61 */
+#define _MODEM_SHAPING15_COEFF61_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING15 */
+#define MODEM_SHAPING15_COEFF61_DEFAULT (_MODEM_SHAPING15_COEFF61_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SHAPING15 */
+#define _MODEM_SHAPING15_COEFF62_SHIFT 16 /**< Shift value for MODEM_COEFF62 */
+#define _MODEM_SHAPING15_COEFF62_MASK 0xFF0000UL /**< Bit mask for MODEM_COEFF62 */
+#define _MODEM_SHAPING15_COEFF62_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING15 */
+#define MODEM_SHAPING15_COEFF62_DEFAULT (_MODEM_SHAPING15_COEFF62_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SHAPING15 */
+#define _MODEM_SHAPING15_COEFF63_SHIFT 24 /**< Shift value for MODEM_COEFF63 */
+#define _MODEM_SHAPING15_COEFF63_MASK 0xFF000000UL /**< Bit mask for MODEM_COEFF63 */
+#define _MODEM_SHAPING15_COEFF63_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SHAPING15 */
+#define MODEM_SHAPING15_COEFF63_DEFAULT (_MODEM_SHAPING15_COEFF63_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_SHAPING15 */
+
+/* Bit fields for MODEM RAMPCTRL */
+#define _MODEM_RAMPCTRL_RESETVALUE 0x00000555UL /**< Default value for MODEM_RAMPCTRL */
+#define _MODEM_RAMPCTRL_MASK 0x00FF1FFFUL /**< Mask for MODEM_RAMPCTRL */
+#define _MODEM_RAMPCTRL_RAMPRATE0_SHIFT 0 /**< Shift value for MODEM_RAMPRATE0 */
+#define _MODEM_RAMPCTRL_RAMPRATE0_MASK 0xFUL /**< Bit mask for MODEM_RAMPRATE0 */
+#define _MODEM_RAMPCTRL_RAMPRATE0_DEFAULT 0x00000005UL /**< Mode DEFAULT for MODEM_RAMPCTRL */
+#define MODEM_RAMPCTRL_RAMPRATE0_DEFAULT (_MODEM_RAMPCTRL_RAMPRATE0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_RAMPCTRL */
+#define _MODEM_RAMPCTRL_RAMPRATE1_SHIFT 4 /**< Shift value for MODEM_RAMPRATE1 */
+#define _MODEM_RAMPCTRL_RAMPRATE1_MASK 0xF0UL /**< Bit mask for MODEM_RAMPRATE1 */
+#define _MODEM_RAMPCTRL_RAMPRATE1_DEFAULT 0x00000005UL /**< Mode DEFAULT for MODEM_RAMPCTRL */
+#define MODEM_RAMPCTRL_RAMPRATE1_DEFAULT (_MODEM_RAMPCTRL_RAMPRATE1_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_RAMPCTRL */
+#define _MODEM_RAMPCTRL_RAMPRATE2_SHIFT 8 /**< Shift value for MODEM_RAMPRATE2 */
+#define _MODEM_RAMPCTRL_RAMPRATE2_MASK 0xF00UL /**< Bit mask for MODEM_RAMPRATE2 */
+#define _MODEM_RAMPCTRL_RAMPRATE2_DEFAULT 0x00000005UL /**< Mode DEFAULT for MODEM_RAMPCTRL */
+#define MODEM_RAMPCTRL_RAMPRATE2_DEFAULT (_MODEM_RAMPCTRL_RAMPRATE2_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_RAMPCTRL */
+
+/* Bit fields for MODEM RAMPLEV */
+#define _MODEM_RAMPLEV_RESETVALUE 0x009F9F9FUL /**< Default value for MODEM_RAMPLEV */
+#define _MODEM_RAMPLEV_MASK 0x00FFFFFFUL /**< Mask for MODEM_RAMPLEV */
+#define _MODEM_RAMPLEV_RAMPLEV0_SHIFT 0 /**< Shift value for MODEM_RAMPLEV0 */
+#define _MODEM_RAMPLEV_RAMPLEV0_MASK 0xFFUL /**< Bit mask for MODEM_RAMPLEV0 */
+#define _MODEM_RAMPLEV_RAMPLEV0_DEFAULT 0x0000009FUL /**< Mode DEFAULT for MODEM_RAMPLEV */
+#define MODEM_RAMPLEV_RAMPLEV0_DEFAULT (_MODEM_RAMPLEV_RAMPLEV0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_RAMPLEV */
+#define _MODEM_RAMPLEV_RAMPLEV1_SHIFT 8 /**< Shift value for MODEM_RAMPLEV1 */
+#define _MODEM_RAMPLEV_RAMPLEV1_MASK 0xFF00UL /**< Bit mask for MODEM_RAMPLEV1 */
+#define _MODEM_RAMPLEV_RAMPLEV1_DEFAULT 0x0000009FUL /**< Mode DEFAULT for MODEM_RAMPLEV */
+#define MODEM_RAMPLEV_RAMPLEV1_DEFAULT (_MODEM_RAMPLEV_RAMPLEV1_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_RAMPLEV */
+#define _MODEM_RAMPLEV_RAMPLEV2_SHIFT 16 /**< Shift value for MODEM_RAMPLEV2 */
+#define _MODEM_RAMPLEV_RAMPLEV2_MASK 0xFF0000UL /**< Bit mask for MODEM_RAMPLEV2 */
+#define _MODEM_RAMPLEV_RAMPLEV2_DEFAULT 0x0000009FUL /**< Mode DEFAULT for MODEM_RAMPLEV */
+#define MODEM_RAMPLEV_RAMPLEV2_DEFAULT (_MODEM_RAMPLEV_RAMPLEV2_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_RAMPLEV */
+
+/* Bit fields for MODEM ANARAMPCTRL */
+#define _MODEM_ANARAMPCTRL_RESETVALUE 0x00000A00UL /**< Default value for MODEM_ANARAMPCTRL */
+#define _MODEM_ANARAMPCTRL_MASK 0x00001E06UL /**< Mask for MODEM_ANARAMPCTRL */
+#define MODEM_ANARAMPCTRL_RAMPOVREN (0x1UL << 1) /**< PA Analog Ramp Override */
+#define _MODEM_ANARAMPCTRL_RAMPOVREN_SHIFT 1 /**< Shift value for MODEM_RAMPOVREN */
+#define _MODEM_ANARAMPCTRL_RAMPOVREN_MASK 0x2UL /**< Bit mask for MODEM_RAMPOVREN */
+#define _MODEM_ANARAMPCTRL_RAMPOVREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANARAMPCTRL */
+#define MODEM_ANARAMPCTRL_RAMPOVREN_DEFAULT (_MODEM_ANARAMPCTRL_RAMPOVREN_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_ANARAMPCTRL */
+#define MODEM_ANARAMPCTRL_RAMPOVRUPD (0x1UL << 2) /**< PA Analog Ramp Override Update Pulse */
+#define _MODEM_ANARAMPCTRL_RAMPOVRUPD_SHIFT 2 /**< Shift value for MODEM_RAMPOVRUPD */
+#define _MODEM_ANARAMPCTRL_RAMPOVRUPD_MASK 0x4UL /**< Bit mask for MODEM_RAMPOVRUPD */
+#define _MODEM_ANARAMPCTRL_RAMPOVRUPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANARAMPCTRL */
+#define MODEM_ANARAMPCTRL_RAMPOVRUPD_DEFAULT (_MODEM_ANARAMPCTRL_RAMPOVRUPD_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_ANARAMPCTRL */
+#define _MODEM_ANARAMPCTRL_VMIDCTRL_SHIFT 9 /**< Shift value for MODEM_VMIDCTRL */
+#define _MODEM_ANARAMPCTRL_VMIDCTRL_MASK 0x600UL /**< Bit mask for MODEM_VMIDCTRL */
+#define _MODEM_ANARAMPCTRL_VMIDCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_ANARAMPCTRL */
+#define _MODEM_ANARAMPCTRL_VMIDCTRL_OFF 0x00000000UL /**< Mode OFF for MODEM_ANARAMPCTRL */
+#define _MODEM_ANARAMPCTRL_VMIDCTRL_MID 0x00000001UL /**< Mode MID for MODEM_ANARAMPCTRL */
+#define _MODEM_ANARAMPCTRL_VMIDCTRL_HIGH 0x00000002UL /**< Mode HIGH for MODEM_ANARAMPCTRL */
+#define _MODEM_ANARAMPCTRL_VMIDCTRL_ON 0x00000003UL /**< Mode ON for MODEM_ANARAMPCTRL */
+#define MODEM_ANARAMPCTRL_VMIDCTRL_DEFAULT (_MODEM_ANARAMPCTRL_VMIDCTRL_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_ANARAMPCTRL */
+#define MODEM_ANARAMPCTRL_VMIDCTRL_OFF (_MODEM_ANARAMPCTRL_VMIDCTRL_OFF << 9) /**< Shifted mode OFF for MODEM_ANARAMPCTRL */
+#define MODEM_ANARAMPCTRL_VMIDCTRL_MID (_MODEM_ANARAMPCTRL_VMIDCTRL_MID << 9) /**< Shifted mode MID for MODEM_ANARAMPCTRL */
+#define MODEM_ANARAMPCTRL_VMIDCTRL_HIGH (_MODEM_ANARAMPCTRL_VMIDCTRL_HIGH << 9) /**< Shifted mode HIGH for MODEM_ANARAMPCTRL */
+#define MODEM_ANARAMPCTRL_VMIDCTRL_ON (_MODEM_ANARAMPCTRL_VMIDCTRL_ON << 9) /**< Shifted mode ON for MODEM_ANARAMPCTRL */
+#define _MODEM_ANARAMPCTRL_MUTEDLY_SHIFT 11 /**< Shift value for MODEM_MUTEDLY */
+#define _MODEM_ANARAMPCTRL_MUTEDLY_MASK 0x1800UL /**< Bit mask for MODEM_MUTEDLY */
+#define _MODEM_ANARAMPCTRL_MUTEDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_ANARAMPCTRL */
+#define _MODEM_ANARAMPCTRL_MUTEDLY_TIME0US 0x00000000UL /**< Mode TIME0US for MODEM_ANARAMPCTRL */
+#define _MODEM_ANARAMPCTRL_MUTEDLY_TIME0P5US 0x00000001UL /**< Mode TIME0P5US for MODEM_ANARAMPCTRL */
+#define _MODEM_ANARAMPCTRL_MUTEDLY_TIME0P25US 0x00000002UL /**< Mode TIME0P25US for MODEM_ANARAMPCTRL */
+#define _MODEM_ANARAMPCTRL_MUTEDLY_NOTUSED 0x00000003UL /**< Mode NOTUSED for MODEM_ANARAMPCTRL */
+#define MODEM_ANARAMPCTRL_MUTEDLY_DEFAULT (_MODEM_ANARAMPCTRL_MUTEDLY_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_ANARAMPCTRL */
+#define MODEM_ANARAMPCTRL_MUTEDLY_TIME0US (_MODEM_ANARAMPCTRL_MUTEDLY_TIME0US << 11) /**< Shifted mode TIME0US for MODEM_ANARAMPCTRL */
+#define MODEM_ANARAMPCTRL_MUTEDLY_TIME0P5US (_MODEM_ANARAMPCTRL_MUTEDLY_TIME0P5US << 11) /**< Shifted mode TIME0P5US for MODEM_ANARAMPCTRL*/
+#define MODEM_ANARAMPCTRL_MUTEDLY_TIME0P25US (_MODEM_ANARAMPCTRL_MUTEDLY_TIME0P25US << 11) /**< Shifted mode TIME0P25US for MODEM_ANARAMPCTRL*/
+#define MODEM_ANARAMPCTRL_MUTEDLY_NOTUSED (_MODEM_ANARAMPCTRL_MUTEDLY_NOTUSED << 11) /**< Shifted mode NOTUSED for MODEM_ANARAMPCTRL */
+
+/* Bit fields for MODEM DCCOMP */
+#define _MODEM_DCCOMP_RESETVALUE 0x00000030UL /**< Default value for MODEM_DCCOMP */
+#define _MODEM_DCCOMP_MASK 0x001FFFFFUL /**< Mask for MODEM_DCCOMP */
+#define MODEM_DCCOMP_DCESTIEN (0x1UL << 0) /**< DC Offset Estimation Enable */
+#define _MODEM_DCCOMP_DCESTIEN_SHIFT 0 /**< Shift value for MODEM_DCESTIEN */
+#define _MODEM_DCCOMP_DCESTIEN_MASK 0x1UL /**< Bit mask for MODEM_DCESTIEN */
+#define _MODEM_DCCOMP_DCESTIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DCCOMP */
+#define MODEM_DCCOMP_DCESTIEN_DEFAULT (_MODEM_DCCOMP_DCESTIEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_DCCOMP */
+#define MODEM_DCCOMP_DCCOMPEN (0x1UL << 1) /**< DC Offset Compensation Enable */
+#define _MODEM_DCCOMP_DCCOMPEN_SHIFT 1 /**< Shift value for MODEM_DCCOMPEN */
+#define _MODEM_DCCOMP_DCCOMPEN_MASK 0x2UL /**< Bit mask for MODEM_DCCOMPEN */
+#define _MODEM_DCCOMP_DCCOMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DCCOMP */
+#define MODEM_DCCOMP_DCCOMPEN_DEFAULT (_MODEM_DCCOMP_DCCOMPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_DCCOMP */
+#define MODEM_DCCOMP_DCRSTEN (0x1UL << 2) /**< DC Compensation Filter Reset Enable */
+#define _MODEM_DCCOMP_DCRSTEN_SHIFT 2 /**< Shift value for MODEM_DCRSTEN */
+#define _MODEM_DCCOMP_DCRSTEN_MASK 0x4UL /**< Bit mask for MODEM_DCRSTEN */
+#define _MODEM_DCCOMP_DCRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DCCOMP */
+#define MODEM_DCCOMP_DCRSTEN_DEFAULT (_MODEM_DCCOMP_DCRSTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_DCCOMP */
+#define MODEM_DCCOMP_DCCOMPFREEZE (0x1UL << 3) /**< DC Offset Compensation Filter Freeze */
+#define _MODEM_DCCOMP_DCCOMPFREEZE_SHIFT 3 /**< Shift value for MODEM_DCCOMPFREEZE */
+#define _MODEM_DCCOMP_DCCOMPFREEZE_MASK 0x8UL /**< Bit mask for MODEM_DCCOMPFREEZE */
+#define _MODEM_DCCOMP_DCCOMPFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DCCOMP */
+#define MODEM_DCCOMP_DCCOMPFREEZE_DEFAULT (_MODEM_DCCOMP_DCCOMPFREEZE_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_DCCOMP */
+#define _MODEM_DCCOMP_DCCOMPGEAR_SHIFT 4 /**< Shift value for MODEM_DCCOMPGEAR */
+#define _MODEM_DCCOMP_DCCOMPGEAR_MASK 0x70UL /**< Bit mask for MODEM_DCCOMPGEAR */
+#define _MODEM_DCCOMP_DCCOMPGEAR_DEFAULT 0x00000003UL /**< Mode DEFAULT for MODEM_DCCOMP */
+#define MODEM_DCCOMP_DCCOMPGEAR_DEFAULT (_MODEM_DCCOMP_DCCOMPGEAR_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_DCCOMP */
+#define _MODEM_DCCOMP_DCLIMIT_SHIFT 7 /**< Shift value for MODEM_DCLIMIT */
+#define _MODEM_DCCOMP_DCLIMIT_MASK 0x180UL /**< Bit mask for MODEM_DCLIMIT */
+#define _MODEM_DCCOMP_DCLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DCCOMP */
+#define _MODEM_DCCOMP_DCLIMIT_FULLSCALE 0x00000000UL /**< Mode FULLSCALE for MODEM_DCCOMP */
+#define _MODEM_DCCOMP_DCLIMIT_FULLSCALEBY4 0x00000001UL /**< Mode FULLSCALEBY4 for MODEM_DCCOMP */
+#define _MODEM_DCCOMP_DCLIMIT_FULLSCALEBY8 0x00000002UL /**< Mode FULLSCALEBY8 for MODEM_DCCOMP */
+#define _MODEM_DCCOMP_DCLIMIT_FULLSCALEBY16 0x00000003UL /**< Mode FULLSCALEBY16 for MODEM_DCCOMP */
+#define MODEM_DCCOMP_DCLIMIT_DEFAULT (_MODEM_DCCOMP_DCLIMIT_DEFAULT << 7) /**< Shifted mode DEFAULT for MODEM_DCCOMP */
+#define MODEM_DCCOMP_DCLIMIT_FULLSCALE (_MODEM_DCCOMP_DCLIMIT_FULLSCALE << 7) /**< Shifted mode FULLSCALE for MODEM_DCCOMP */
+#define MODEM_DCCOMP_DCLIMIT_FULLSCALEBY4 (_MODEM_DCCOMP_DCLIMIT_FULLSCALEBY4 << 7) /**< Shifted mode FULLSCALEBY4 for MODEM_DCCOMP */
+#define MODEM_DCCOMP_DCLIMIT_FULLSCALEBY8 (_MODEM_DCCOMP_DCLIMIT_FULLSCALEBY8 << 7) /**< Shifted mode FULLSCALEBY8 for MODEM_DCCOMP */
+#define MODEM_DCCOMP_DCLIMIT_FULLSCALEBY16 (_MODEM_DCCOMP_DCLIMIT_FULLSCALEBY16 << 7) /**< Shifted mode FULLSCALEBY16 for MODEM_DCCOMP */
+#define MODEM_DCCOMP_DCGAINGEAREN (0x1UL << 9) /**< DC Offset Gain Change Filter Gear Enable */
+#define _MODEM_DCCOMP_DCGAINGEAREN_SHIFT 9 /**< Shift value for MODEM_DCGAINGEAREN */
+#define _MODEM_DCCOMP_DCGAINGEAREN_MASK 0x200UL /**< Bit mask for MODEM_DCGAINGEAREN */
+#define _MODEM_DCCOMP_DCGAINGEAREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DCCOMP */
+#define MODEM_DCCOMP_DCGAINGEAREN_DEFAULT (_MODEM_DCCOMP_DCGAINGEAREN_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_DCCOMP */
+#define _MODEM_DCCOMP_DCGAINGEAR_SHIFT 10 /**< Shift value for MODEM_DCGAINGEAR */
+#define _MODEM_DCCOMP_DCGAINGEAR_MASK 0x1C00UL /**< Bit mask for MODEM_DCGAINGEAR */
+#define _MODEM_DCCOMP_DCGAINGEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DCCOMP */
+#define MODEM_DCCOMP_DCGAINGEAR_DEFAULT (_MODEM_DCCOMP_DCGAINGEAR_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_DCCOMP */
+#define _MODEM_DCCOMP_DCGAINGEARSMPS_SHIFT 13 /**< Shift value for MODEM_DCGAINGEARSMPS */
+#define _MODEM_DCCOMP_DCGAINGEARSMPS_MASK 0x1FE000UL /**< Bit mask for MODEM_DCGAINGEARSMPS */
+#define _MODEM_DCCOMP_DCGAINGEARSMPS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DCCOMP */
+#define MODEM_DCCOMP_DCGAINGEARSMPS_DEFAULT (_MODEM_DCCOMP_DCGAINGEARSMPS_DEFAULT << 13) /**< Shifted mode DEFAULT for MODEM_DCCOMP */
+
+/* Bit fields for MODEM DCCOMPFILTINIT */
+#define _MODEM_DCCOMPFILTINIT_RESETVALUE 0x00000000UL /**< Default value for MODEM_DCCOMPFILTINIT */
+#define _MODEM_DCCOMPFILTINIT_MASK 0x7FFFFFFFUL /**< Mask for MODEM_DCCOMPFILTINIT */
+#define _MODEM_DCCOMPFILTINIT_DCCOMPINITVALI_SHIFT 0 /**< Shift value for MODEM_DCCOMPINITVALI */
+#define _MODEM_DCCOMPFILTINIT_DCCOMPINITVALI_MASK 0x7FFFUL /**< Bit mask for MODEM_DCCOMPINITVALI */
+#define _MODEM_DCCOMPFILTINIT_DCCOMPINITVALI_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DCCOMPFILTINIT */
+#define MODEM_DCCOMPFILTINIT_DCCOMPINITVALI_DEFAULT (_MODEM_DCCOMPFILTINIT_DCCOMPINITVALI_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_DCCOMPFILTINIT*/
+#define _MODEM_DCCOMPFILTINIT_DCCOMPINITVALQ_SHIFT 15 /**< Shift value for MODEM_DCCOMPINITVALQ */
+#define _MODEM_DCCOMPFILTINIT_DCCOMPINITVALQ_MASK 0x3FFF8000UL /**< Bit mask for MODEM_DCCOMPINITVALQ */
+#define _MODEM_DCCOMPFILTINIT_DCCOMPINITVALQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DCCOMPFILTINIT */
+#define MODEM_DCCOMPFILTINIT_DCCOMPINITVALQ_DEFAULT (_MODEM_DCCOMPFILTINIT_DCCOMPINITVALQ_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_DCCOMPFILTINIT*/
+#define MODEM_DCCOMPFILTINIT_DCCOMPINIT (0x1UL << 30) /**< Initialize filter state */
+#define _MODEM_DCCOMPFILTINIT_DCCOMPINIT_SHIFT 30 /**< Shift value for MODEM_DCCOMPINIT */
+#define _MODEM_DCCOMPFILTINIT_DCCOMPINIT_MASK 0x40000000UL /**< Bit mask for MODEM_DCCOMPINIT */
+#define _MODEM_DCCOMPFILTINIT_DCCOMPINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DCCOMPFILTINIT */
+#define MODEM_DCCOMPFILTINIT_DCCOMPINIT_DEFAULT (_MODEM_DCCOMPFILTINIT_DCCOMPINIT_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_DCCOMPFILTINIT*/
+
+/* Bit fields for MODEM DCESTI */
+#define _MODEM_DCESTI_RESETVALUE 0x00000000UL /**< Default value for MODEM_DCESTI */
+#define _MODEM_DCESTI_MASK 0x3FFFFFFFUL /**< Mask for MODEM_DCESTI */
+#define _MODEM_DCESTI_DCCOMPESTIVALI_SHIFT 0 /**< Shift value for MODEM_DCCOMPESTIVALI */
+#define _MODEM_DCESTI_DCCOMPESTIVALI_MASK 0x7FFFUL /**< Bit mask for MODEM_DCCOMPESTIVALI */
+#define _MODEM_DCESTI_DCCOMPESTIVALI_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DCESTI */
+#define MODEM_DCESTI_DCCOMPESTIVALI_DEFAULT (_MODEM_DCESTI_DCCOMPESTIVALI_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_DCESTI */
+#define _MODEM_DCESTI_DCCOMPESTIVALQ_SHIFT 15 /**< Shift value for MODEM_DCCOMPESTIVALQ */
+#define _MODEM_DCESTI_DCCOMPESTIVALQ_MASK 0x3FFF8000UL /**< Bit mask for MODEM_DCCOMPESTIVALQ */
+#define _MODEM_DCESTI_DCCOMPESTIVALQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DCESTI */
+#define MODEM_DCESTI_DCCOMPESTIVALQ_DEFAULT (_MODEM_DCESTI_DCCOMPESTIVALQ_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_DCESTI */
+
+/* Bit fields for MODEM SRCCHF */
+#define _MODEM_SRCCHF_RESETVALUE 0x00000000UL /**< Default value for MODEM_SRCCHF */
+#define _MODEM_SRCCHF_MASK 0x8FFFF000UL /**< Mask for MODEM_SRCCHF */
+#define _MODEM_SRCCHF_SRCRATIO2_SHIFT 12 /**< Shift value for MODEM_SRCRATIO2 */
+#define _MODEM_SRCCHF_SRCRATIO2_MASK 0x7FFF000UL /**< Bit mask for MODEM_SRCRATIO2 */
+#define _MODEM_SRCCHF_SRCRATIO2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SRCCHF */
+#define MODEM_SRCCHF_SRCRATIO2_DEFAULT (_MODEM_SRCCHF_SRCRATIO2_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_SRCCHF */
+#define MODEM_SRCCHF_SRCENABLE2 (0x1UL << 27) /**< SRC2 enable */
+#define _MODEM_SRCCHF_SRCENABLE2_SHIFT 27 /**< Shift value for MODEM_SRCENABLE2 */
+#define _MODEM_SRCCHF_SRCENABLE2_MASK 0x8000000UL /**< Bit mask for MODEM_SRCENABLE2 */
+#define _MODEM_SRCCHF_SRCENABLE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SRCCHF */
+#define MODEM_SRCCHF_SRCENABLE2_DEFAULT (_MODEM_SRCCHF_SRCENABLE2_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_SRCCHF */
+#define MODEM_SRCCHF_INTOSR (0x1UL << 31) /**< Forcing Integer OSR */
+#define _MODEM_SRCCHF_INTOSR_SHIFT 31 /**< Shift value for MODEM_INTOSR */
+#define _MODEM_SRCCHF_INTOSR_MASK 0x80000000UL /**< Bit mask for MODEM_INTOSR */
+#define _MODEM_SRCCHF_INTOSR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SRCCHF */
+#define MODEM_SRCCHF_INTOSR_DEFAULT (_MODEM_SRCCHF_INTOSR_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_SRCCHF */
+
+/* Bit fields for MODEM INTAFC */
+#define _MODEM_INTAFC_RESETVALUE 0x00000000UL /**< Default value for MODEM_INTAFC */
+#define _MODEM_INTAFC_MASK 0x00FFFFFFUL /**< Mask for MODEM_INTAFC */
+#define _MODEM_INTAFC_FOEPREAVG0_SHIFT 0 /**< Shift value for MODEM_FOEPREAVG0 */
+#define _MODEM_INTAFC_FOEPREAVG0_MASK 0x7UL /**< Bit mask for MODEM_FOEPREAVG0 */
+#define _MODEM_INTAFC_FOEPREAVG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_INTAFC */
+#define MODEM_INTAFC_FOEPREAVG0_DEFAULT (_MODEM_INTAFC_FOEPREAVG0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_INTAFC */
+#define _MODEM_INTAFC_FOEPREAVG1_SHIFT 3 /**< Shift value for MODEM_FOEPREAVG1 */
+#define _MODEM_INTAFC_FOEPREAVG1_MASK 0x38UL /**< Bit mask for MODEM_FOEPREAVG1 */
+#define _MODEM_INTAFC_FOEPREAVG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_INTAFC */
+#define MODEM_INTAFC_FOEPREAVG1_DEFAULT (_MODEM_INTAFC_FOEPREAVG1_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_INTAFC */
+#define _MODEM_INTAFC_FOEPREAVG2_SHIFT 6 /**< Shift value for MODEM_FOEPREAVG2 */
+#define _MODEM_INTAFC_FOEPREAVG2_MASK 0x1C0UL /**< Bit mask for MODEM_FOEPREAVG2 */
+#define _MODEM_INTAFC_FOEPREAVG2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_INTAFC */
+#define MODEM_INTAFC_FOEPREAVG2_DEFAULT (_MODEM_INTAFC_FOEPREAVG2_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_INTAFC */
+#define _MODEM_INTAFC_FOEPREAVG3_SHIFT 9 /**< Shift value for MODEM_FOEPREAVG3 */
+#define _MODEM_INTAFC_FOEPREAVG3_MASK 0xE00UL /**< Bit mask for MODEM_FOEPREAVG3 */
+#define _MODEM_INTAFC_FOEPREAVG3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_INTAFC */
+#define MODEM_INTAFC_FOEPREAVG3_DEFAULT (_MODEM_INTAFC_FOEPREAVG3_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_INTAFC */
+#define _MODEM_INTAFC_FOEPREAVG4_SHIFT 12 /**< Shift value for MODEM_FOEPREAVG4 */
+#define _MODEM_INTAFC_FOEPREAVG4_MASK 0x7000UL /**< Bit mask for MODEM_FOEPREAVG4 */
+#define _MODEM_INTAFC_FOEPREAVG4_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_INTAFC */
+#define MODEM_INTAFC_FOEPREAVG4_DEFAULT (_MODEM_INTAFC_FOEPREAVG4_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_INTAFC */
+#define _MODEM_INTAFC_FOEPREAVG5_SHIFT 15 /**< Shift value for MODEM_FOEPREAVG5 */
+#define _MODEM_INTAFC_FOEPREAVG5_MASK 0x38000UL /**< Bit mask for MODEM_FOEPREAVG5 */
+#define _MODEM_INTAFC_FOEPREAVG5_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_INTAFC */
+#define MODEM_INTAFC_FOEPREAVG5_DEFAULT (_MODEM_INTAFC_FOEPREAVG5_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_INTAFC */
+#define _MODEM_INTAFC_FOEPREAVG6_SHIFT 18 /**< Shift value for MODEM_FOEPREAVG6 */
+#define _MODEM_INTAFC_FOEPREAVG6_MASK 0x1C0000UL /**< Bit mask for MODEM_FOEPREAVG6 */
+#define _MODEM_INTAFC_FOEPREAVG6_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_INTAFC */
+#define MODEM_INTAFC_FOEPREAVG6_DEFAULT (_MODEM_INTAFC_FOEPREAVG6_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_INTAFC */
+#define _MODEM_INTAFC_FOEPREAVG7_SHIFT 21 /**< Shift value for MODEM_FOEPREAVG7 */
+#define _MODEM_INTAFC_FOEPREAVG7_MASK 0xE00000UL /**< Bit mask for MODEM_FOEPREAVG7 */
+#define _MODEM_INTAFC_FOEPREAVG7_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_INTAFC */
+#define MODEM_INTAFC_FOEPREAVG7_DEFAULT (_MODEM_INTAFC_FOEPREAVG7_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_INTAFC */
+
+/* Bit fields for MODEM DSATHD0 */
+#define _MODEM_DSATHD0_RESETVALUE 0x07830464UL /**< Default value for MODEM_DSATHD0 */
+#define _MODEM_DSATHD0_MASK 0xFFFFFFFFUL /**< Mask for MODEM_DSATHD0 */
+#define _MODEM_DSATHD0_SPIKETHD_SHIFT 0 /**< Shift value for MODEM_SPIKETHD */
+#define _MODEM_DSATHD0_SPIKETHD_MASK 0xFFUL /**< Bit mask for MODEM_SPIKETHD */
+#define _MODEM_DSATHD0_SPIKETHD_DEFAULT 0x00000064UL /**< Mode DEFAULT for MODEM_DSATHD0 */
+#define MODEM_DSATHD0_SPIKETHD_DEFAULT (_MODEM_DSATHD0_SPIKETHD_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_DSATHD0 */
+#define _MODEM_DSATHD0_UNMODTHD_SHIFT 8 /**< Shift value for MODEM_UNMODTHD */
+#define _MODEM_DSATHD0_UNMODTHD_MASK 0x3F00UL /**< Bit mask for MODEM_UNMODTHD */
+#define _MODEM_DSATHD0_UNMODTHD_DEFAULT 0x00000004UL /**< Mode DEFAULT for MODEM_DSATHD0 */
+#define MODEM_DSATHD0_UNMODTHD_DEFAULT (_MODEM_DSATHD0_UNMODTHD_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_DSATHD0 */
+#define _MODEM_DSATHD0_FDEVMINTHD_SHIFT 14 /**< Shift value for MODEM_FDEVMINTHD */
+#define _MODEM_DSATHD0_FDEVMINTHD_MASK 0xFC000UL /**< Bit mask for MODEM_FDEVMINTHD */
+#define _MODEM_DSATHD0_FDEVMINTHD_DEFAULT 0x0000000CUL /**< Mode DEFAULT for MODEM_DSATHD0 */
+#define MODEM_DSATHD0_FDEVMINTHD_DEFAULT (_MODEM_DSATHD0_FDEVMINTHD_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_DSATHD0 */
+#define _MODEM_DSATHD0_FDEVMAXTHD_SHIFT 20 /**< Shift value for MODEM_FDEVMAXTHD */
+#define _MODEM_DSATHD0_FDEVMAXTHD_MASK 0xFFF00000UL /**< Bit mask for MODEM_FDEVMAXTHD */
+#define _MODEM_DSATHD0_FDEVMAXTHD_DEFAULT 0x00000078UL /**< Mode DEFAULT for MODEM_DSATHD0 */
+#define MODEM_DSATHD0_FDEVMAXTHD_DEFAULT (_MODEM_DSATHD0_FDEVMAXTHD_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_DSATHD0 */
+
+/* Bit fields for MODEM DSATHD1 */
+#define _MODEM_DSATHD1_RESETVALUE 0x3AC81388UL /**< Default value for MODEM_DSATHD1 */
+#define _MODEM_DSATHD1_MASK 0x7FFFFFFFUL /**< Mask for MODEM_DSATHD1 */
+#define _MODEM_DSATHD1_POWABSTHD_SHIFT 0 /**< Shift value for MODEM_POWABSTHD */
+#define _MODEM_DSATHD1_POWABSTHD_MASK 0xFFFFUL /**< Bit mask for MODEM_POWABSTHD */
+#define _MODEM_DSATHD1_POWABSTHD_DEFAULT 0x00001388UL /**< Mode DEFAULT for MODEM_DSATHD1 */
+#define MODEM_DSATHD1_POWABSTHD_DEFAULT (_MODEM_DSATHD1_POWABSTHD_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_DSATHD1 */
+#define _MODEM_DSATHD1_POWRELTHD_SHIFT 16 /**< Shift value for MODEM_POWRELTHD */
+#define _MODEM_DSATHD1_POWRELTHD_MASK 0x30000UL /**< Bit mask for MODEM_POWRELTHD */
+#define _MODEM_DSATHD1_POWRELTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DSATHD1 */
+#define _MODEM_DSATHD1_POWRELTHD_DISABLED 0x00000000UL /**< Mode DISABLED for MODEM_DSATHD1 */
+#define _MODEM_DSATHD1_POWRELTHD_MODE1 0x00000001UL /**< Mode MODE1 for MODEM_DSATHD1 */
+#define _MODEM_DSATHD1_POWRELTHD_MODE2 0x00000002UL /**< Mode MODE2 for MODEM_DSATHD1 */
+#define _MODEM_DSATHD1_POWRELTHD_MODE3 0x00000003UL /**< Mode MODE3 for MODEM_DSATHD1 */
+#define MODEM_DSATHD1_POWRELTHD_DEFAULT (_MODEM_DSATHD1_POWRELTHD_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_DSATHD1 */
+#define MODEM_DSATHD1_POWRELTHD_DISABLED (_MODEM_DSATHD1_POWRELTHD_DISABLED << 16) /**< Shifted mode DISABLED for MODEM_DSATHD1 */
+#define MODEM_DSATHD1_POWRELTHD_MODE1 (_MODEM_DSATHD1_POWRELTHD_MODE1 << 16) /**< Shifted mode MODE1 for MODEM_DSATHD1 */
+#define MODEM_DSATHD1_POWRELTHD_MODE2 (_MODEM_DSATHD1_POWRELTHD_MODE2 << 16) /**< Shifted mode MODE2 for MODEM_DSATHD1 */
+#define MODEM_DSATHD1_POWRELTHD_MODE3 (_MODEM_DSATHD1_POWRELTHD_MODE3 << 16) /**< Shifted mode MODE3 for MODEM_DSATHD1 */
+#define _MODEM_DSATHD1_DSARSTCNT_SHIFT 18 /**< Shift value for MODEM_DSARSTCNT */
+#define _MODEM_DSATHD1_DSARSTCNT_MASK 0x1C0000UL /**< Bit mask for MODEM_DSARSTCNT */
+#define _MODEM_DSATHD1_DSARSTCNT_DEFAULT 0x00000002UL /**< Mode DEFAULT for MODEM_DSATHD1 */
+#define MODEM_DSATHD1_DSARSTCNT_DEFAULT (_MODEM_DSATHD1_DSARSTCNT_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_DSATHD1 */
+#define _MODEM_DSATHD1_RSSIJMPTHD_SHIFT 21 /**< Shift value for MODEM_RSSIJMPTHD */
+#define _MODEM_DSATHD1_RSSIJMPTHD_MASK 0x1E00000UL /**< Bit mask for MODEM_RSSIJMPTHD */
+#define _MODEM_DSATHD1_RSSIJMPTHD_DEFAULT 0x00000006UL /**< Mode DEFAULT for MODEM_DSATHD1 */
+#define MODEM_DSATHD1_RSSIJMPTHD_DEFAULT (_MODEM_DSATHD1_RSSIJMPTHD_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_DSATHD1 */
+#define _MODEM_DSATHD1_FREQLATDLY_SHIFT 25 /**< Shift value for MODEM_FREQLATDLY */
+#define _MODEM_DSATHD1_FREQLATDLY_MASK 0x6000000UL /**< Bit mask for MODEM_FREQLATDLY */
+#define _MODEM_DSATHD1_FREQLATDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_DSATHD1 */
+#define MODEM_DSATHD1_FREQLATDLY_DEFAULT (_MODEM_DSATHD1_FREQLATDLY_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_DSATHD1 */
+#define MODEM_DSATHD1_PWRFLTBYP (0x1UL << 27) /**< Power filter bypass */
+#define _MODEM_DSATHD1_PWRFLTBYP_SHIFT 27 /**< Shift value for MODEM_PWRFLTBYP */
+#define _MODEM_DSATHD1_PWRFLTBYP_MASK 0x8000000UL /**< Bit mask for MODEM_PWRFLTBYP */
+#define _MODEM_DSATHD1_PWRFLTBYP_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_DSATHD1 */
+#define MODEM_DSATHD1_PWRFLTBYP_DEFAULT (_MODEM_DSATHD1_PWRFLTBYP_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_DSATHD1 */
+#define MODEM_DSATHD1_AMPFLTBYP (0x1UL << 28) /**< Amplitude filter bypass */
+#define _MODEM_DSATHD1_AMPFLTBYP_SHIFT 28 /**< Shift value for MODEM_AMPFLTBYP */
+#define _MODEM_DSATHD1_AMPFLTBYP_MASK 0x10000000UL /**< Bit mask for MODEM_AMPFLTBYP */
+#define _MODEM_DSATHD1_AMPFLTBYP_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_DSATHD1 */
+#define MODEM_DSATHD1_AMPFLTBYP_DEFAULT (_MODEM_DSATHD1_AMPFLTBYP_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_DSATHD1 */
+#define MODEM_DSATHD1_PWRDETDIS (0x1UL << 29) /**< Power detection disabled */
+#define _MODEM_DSATHD1_PWRDETDIS_SHIFT 29 /**< Shift value for MODEM_PWRDETDIS */
+#define _MODEM_DSATHD1_PWRDETDIS_MASK 0x20000000UL /**< Bit mask for MODEM_PWRDETDIS */
+#define _MODEM_DSATHD1_PWRDETDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_DSATHD1 */
+#define MODEM_DSATHD1_PWRDETDIS_DEFAULT (_MODEM_DSATHD1_PWRDETDIS_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_DSATHD1 */
+#define MODEM_DSATHD1_FREQSCALE (0x1UL << 30) /**< Frequency scale factor */
+#define _MODEM_DSATHD1_FREQSCALE_SHIFT 30 /**< Shift value for MODEM_FREQSCALE */
+#define _MODEM_DSATHD1_FREQSCALE_MASK 0x40000000UL /**< Bit mask for MODEM_FREQSCALE */
+#define _MODEM_DSATHD1_FREQSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DSATHD1 */
+#define MODEM_DSATHD1_FREQSCALE_DEFAULT (_MODEM_DSATHD1_FREQSCALE_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_DSATHD1 */
+
+/* Bit fields for MODEM DSATHD2 */
+#define _MODEM_DSATHD2_RESETVALUE 0x0C660664UL /**< Default value for MODEM_DSATHD2 */
+#define _MODEM_DSATHD2_MASK 0x7FFFFEFFUL /**< Mask for MODEM_DSATHD2 */
+#define _MODEM_DSATHD2_POWABSTHDLOG_SHIFT 0 /**< Shift value for MODEM_POWABSTHDLOG */
+#define _MODEM_DSATHD2_POWABSTHDLOG_MASK 0xFFUL /**< Bit mask for MODEM_POWABSTHDLOG */
+#define _MODEM_DSATHD2_POWABSTHDLOG_DEFAULT 0x00000064UL /**< Mode DEFAULT for MODEM_DSATHD2 */
+#define MODEM_DSATHD2_POWABSTHDLOG_DEFAULT (_MODEM_DSATHD2_POWABSTHDLOG_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_DSATHD2 */
+#define MODEM_DSATHD2_JUMPDETEN (0x1UL << 9) /**< Power jump detection enable */
+#define _MODEM_DSATHD2_JUMPDETEN_SHIFT 9 /**< Shift value for MODEM_JUMPDETEN */
+#define _MODEM_DSATHD2_JUMPDETEN_MASK 0x200UL /**< Bit mask for MODEM_JUMPDETEN */
+#define _MODEM_DSATHD2_JUMPDETEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_DSATHD2 */
+#define MODEM_DSATHD2_JUMPDETEN_DEFAULT (_MODEM_DSATHD2_JUMPDETEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_DSATHD2 */
+#define _MODEM_DSATHD2_FDADJTHD_SHIFT 10 /**< Shift value for MODEM_FDADJTHD */
+#define _MODEM_DSATHD2_FDADJTHD_MASK 0xFC00UL /**< Bit mask for MODEM_FDADJTHD */
+#define _MODEM_DSATHD2_FDADJTHD_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_DSATHD2 */
+#define MODEM_DSATHD2_FDADJTHD_DEFAULT (_MODEM_DSATHD2_FDADJTHD_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_DSATHD2 */
+#define _MODEM_DSATHD2_PMDETPASSTHD_SHIFT 16 /**< Shift value for MODEM_PMDETPASSTHD */
+#define _MODEM_DSATHD2_PMDETPASSTHD_MASK 0xF0000UL /**< Bit mask for MODEM_PMDETPASSTHD */
+#define _MODEM_DSATHD2_PMDETPASSTHD_DEFAULT 0x00000006UL /**< Mode DEFAULT for MODEM_DSATHD2 */
+#define MODEM_DSATHD2_PMDETPASSTHD_DEFAULT (_MODEM_DSATHD2_PMDETPASSTHD_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_DSATHD2 */
+#define _MODEM_DSATHD2_FREQESTTHD_SHIFT 20 /**< Shift value for MODEM_FREQESTTHD */
+#define _MODEM_DSATHD2_FREQESTTHD_MASK 0x1F00000UL /**< Bit mask for MODEM_FREQESTTHD */
+#define _MODEM_DSATHD2_FREQESTTHD_DEFAULT 0x00000006UL /**< Mode DEFAULT for MODEM_DSATHD2 */
+#define MODEM_DSATHD2_FREQESTTHD_DEFAULT (_MODEM_DSATHD2_FREQESTTHD_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_DSATHD2 */
+#define _MODEM_DSATHD2_INTERFERDET_SHIFT 25 /**< Shift value for MODEM_INTERFERDET */
+#define _MODEM_DSATHD2_INTERFERDET_MASK 0x3E000000UL /**< Bit mask for MODEM_INTERFERDET */
+#define _MODEM_DSATHD2_INTERFERDET_DEFAULT 0x00000006UL /**< Mode DEFAULT for MODEM_DSATHD2 */
+#define MODEM_DSATHD2_INTERFERDET_DEFAULT (_MODEM_DSATHD2_INTERFERDET_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_DSATHD2 */
+#define MODEM_DSATHD2_PMDETFORCE (0x1UL << 30) /**< Force DSA preamble detector */
+#define _MODEM_DSATHD2_PMDETFORCE_SHIFT 30 /**< Shift value for MODEM_PMDETFORCE */
+#define _MODEM_DSATHD2_PMDETFORCE_MASK 0x40000000UL /**< Bit mask for MODEM_PMDETFORCE */
+#define _MODEM_DSATHD2_PMDETFORCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DSATHD2 */
+#define MODEM_DSATHD2_PMDETFORCE_DEFAULT (_MODEM_DSATHD2_PMDETFORCE_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_DSATHD2 */
+
+/* Bit fields for MODEM DSATHD3 */
+#define _MODEM_DSATHD3_RESETVALUE 0x07830464UL /**< Default value for MODEM_DSATHD3 */
+#define _MODEM_DSATHD3_MASK 0xFFFFFFFFUL /**< Mask for MODEM_DSATHD3 */
+#define _MODEM_DSATHD3_SPIKETHDLO_SHIFT 0 /**< Shift value for MODEM_SPIKETHDLO */
+#define _MODEM_DSATHD3_SPIKETHDLO_MASK 0xFFUL /**< Bit mask for MODEM_SPIKETHDLO */
+#define _MODEM_DSATHD3_SPIKETHDLO_DEFAULT 0x00000064UL /**< Mode DEFAULT for MODEM_DSATHD3 */
+#define MODEM_DSATHD3_SPIKETHDLO_DEFAULT (_MODEM_DSATHD3_SPIKETHDLO_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_DSATHD3 */
+#define _MODEM_DSATHD3_UNMODTHDLO_SHIFT 8 /**< Shift value for MODEM_UNMODTHDLO */
+#define _MODEM_DSATHD3_UNMODTHDLO_MASK 0x3F00UL /**< Bit mask for MODEM_UNMODTHDLO */
+#define _MODEM_DSATHD3_UNMODTHDLO_DEFAULT 0x00000004UL /**< Mode DEFAULT for MODEM_DSATHD3 */
+#define MODEM_DSATHD3_UNMODTHDLO_DEFAULT (_MODEM_DSATHD3_UNMODTHDLO_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_DSATHD3 */
+#define _MODEM_DSATHD3_FDEVMINTHDLO_SHIFT 14 /**< Shift value for MODEM_FDEVMINTHDLO */
+#define _MODEM_DSATHD3_FDEVMINTHDLO_MASK 0xFC000UL /**< Bit mask for MODEM_FDEVMINTHDLO */
+#define _MODEM_DSATHD3_FDEVMINTHDLO_DEFAULT 0x0000000CUL /**< Mode DEFAULT for MODEM_DSATHD3 */
+#define MODEM_DSATHD3_FDEVMINTHDLO_DEFAULT (_MODEM_DSATHD3_FDEVMINTHDLO_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_DSATHD3 */
+#define _MODEM_DSATHD3_FDEVMAXTHDLO_SHIFT 20 /**< Shift value for MODEM_FDEVMAXTHDLO */
+#define _MODEM_DSATHD3_FDEVMAXTHDLO_MASK 0xFFF00000UL /**< Bit mask for MODEM_FDEVMAXTHDLO */
+#define _MODEM_DSATHD3_FDEVMAXTHDLO_DEFAULT 0x00000078UL /**< Mode DEFAULT for MODEM_DSATHD3 */
+#define MODEM_DSATHD3_FDEVMAXTHDLO_DEFAULT (_MODEM_DSATHD3_FDEVMAXTHDLO_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_DSATHD3 */
+
+/* Bit fields for MODEM DSATHD4 */
+#define _MODEM_DSATHD4_RESETVALUE 0x00821388UL /**< Default value for MODEM_DSATHD4 */
+#define _MODEM_DSATHD4_MASK 0x07FFFFFFUL /**< Mask for MODEM_DSATHD4 */
+#define _MODEM_DSATHD4_POWABSTHDLO_SHIFT 0 /**< Shift value for MODEM_POWABSTHDLO */
+#define _MODEM_DSATHD4_POWABSTHDLO_MASK 0xFFFFUL /**< Bit mask for MODEM_POWABSTHDLO */
+#define _MODEM_DSATHD4_POWABSTHDLO_DEFAULT 0x00001388UL /**< Mode DEFAULT for MODEM_DSATHD4 */
+#define MODEM_DSATHD4_POWABSTHDLO_DEFAULT (_MODEM_DSATHD4_POWABSTHDLO_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_DSATHD4 */
+#define _MODEM_DSATHD4_ARRTOLERTHD0LO_SHIFT 16 /**< Shift value for MODEM_ARRTOLERTHD0LO */
+#define _MODEM_DSATHD4_ARRTOLERTHD0LO_MASK 0x1F0000UL /**< Bit mask for MODEM_ARRTOLERTHD0LO */
+#define _MODEM_DSATHD4_ARRTOLERTHD0LO_DEFAULT 0x00000002UL /**< Mode DEFAULT for MODEM_DSATHD4 */
+#define MODEM_DSATHD4_ARRTOLERTHD0LO_DEFAULT (_MODEM_DSATHD4_ARRTOLERTHD0LO_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_DSATHD4 */
+#define _MODEM_DSATHD4_ARRTOLERTHD1LO_SHIFT 21 /**< Shift value for MODEM_ARRTOLERTHD1LO */
+#define _MODEM_DSATHD4_ARRTOLERTHD1LO_MASK 0x3E00000UL /**< Bit mask for MODEM_ARRTOLERTHD1LO */
+#define _MODEM_DSATHD4_ARRTOLERTHD1LO_DEFAULT 0x00000004UL /**< Mode DEFAULT for MODEM_DSATHD4 */
+#define MODEM_DSATHD4_ARRTOLERTHD1LO_DEFAULT (_MODEM_DSATHD4_ARRTOLERTHD1LO_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_DSATHD4 */
+#define MODEM_DSATHD4_SWTHD (0x1UL << 26) /**< Enable switch threshold for low power */
+#define _MODEM_DSATHD4_SWTHD_SHIFT 26 /**< Shift value for MODEM_SWTHD */
+#define _MODEM_DSATHD4_SWTHD_MASK 0x4000000UL /**< Bit mask for MODEM_SWTHD */
+#define _MODEM_DSATHD4_SWTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DSATHD4 */
+#define MODEM_DSATHD4_SWTHD_DEFAULT (_MODEM_DSATHD4_SWTHD_DEFAULT << 26) /**< Shifted mode DEFAULT for MODEM_DSATHD4 */
+
+/* Bit fields for MODEM DSACTRL */
+#define _MODEM_DSACTRL_RESETVALUE 0x000A2090UL /**< Default value for MODEM_DSACTRL */
+#define _MODEM_DSACTRL_MASK 0xFFEFFFFFUL /**< Mask for MODEM_DSACTRL */
+#define _MODEM_DSACTRL_DSAMODE_SHIFT 0 /**< Shift value for MODEM_DSAMODE */
+#define _MODEM_DSACTRL_DSAMODE_MASK 0x3UL /**< Bit mask for MODEM_DSAMODE */
+#define _MODEM_DSACTRL_DSAMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DSACTRL */
+#define _MODEM_DSACTRL_DSAMODE_DISABLED 0x00000000UL /**< Mode DISABLED for MODEM_DSACTRL */
+#define _MODEM_DSACTRL_DSAMODE_ENABLED 0x00000001UL /**< Mode ENABLED for MODEM_DSACTRL */
+#define MODEM_DSACTRL_DSAMODE_DEFAULT (_MODEM_DSACTRL_DSAMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_DSACTRL */
+#define MODEM_DSACTRL_DSAMODE_DISABLED (_MODEM_DSACTRL_DSAMODE_DISABLED << 0) /**< Shifted mode DISABLED for MODEM_DSACTRL */
+#define MODEM_DSACTRL_DSAMODE_ENABLED (_MODEM_DSACTRL_DSAMODE_ENABLED << 0) /**< Shifted mode ENABLED for MODEM_DSACTRL */
+#define _MODEM_DSACTRL_ARRTHD_SHIFT 2 /**< Shift value for MODEM_ARRTHD */
+#define _MODEM_DSACTRL_ARRTHD_MASK 0x3CUL /**< Bit mask for MODEM_ARRTHD */
+#define _MODEM_DSACTRL_ARRTHD_DEFAULT 0x00000004UL /**< Mode DEFAULT for MODEM_DSACTRL */
+#define MODEM_DSACTRL_ARRTHD_DEFAULT (_MODEM_DSACTRL_ARRTHD_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_DSACTRL */
+#define _MODEM_DSACTRL_ARRTOLERTHD0_SHIFT 6 /**< Shift value for MODEM_ARRTOLERTHD0 */
+#define _MODEM_DSACTRL_ARRTOLERTHD0_MASK 0x7C0UL /**< Bit mask for MODEM_ARRTOLERTHD0 */
+#define _MODEM_DSACTRL_ARRTOLERTHD0_DEFAULT 0x00000002UL /**< Mode DEFAULT for MODEM_DSACTRL */
+#define MODEM_DSACTRL_ARRTOLERTHD0_DEFAULT (_MODEM_DSACTRL_ARRTOLERTHD0_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_DSACTRL */
+#define _MODEM_DSACTRL_ARRTOLERTHD1_SHIFT 11 /**< Shift value for MODEM_ARRTOLERTHD1 */
+#define _MODEM_DSACTRL_ARRTOLERTHD1_MASK 0xF800UL /**< Bit mask for MODEM_ARRTOLERTHD1 */
+#define _MODEM_DSACTRL_ARRTOLERTHD1_DEFAULT 0x00000004UL /**< Mode DEFAULT for MODEM_DSACTRL */
+#define MODEM_DSACTRL_ARRTOLERTHD1_DEFAULT (_MODEM_DSACTRL_ARRTOLERTHD1_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_DSACTRL */
+#define MODEM_DSACTRL_SCHPRD (0x1UL << 16) /**< Search period window length */
+#define _MODEM_DSACTRL_SCHPRD_SHIFT 16 /**< Shift value for MODEM_SCHPRD */
+#define _MODEM_DSACTRL_SCHPRD_MASK 0x10000UL /**< Bit mask for MODEM_SCHPRD */
+#define _MODEM_DSACTRL_SCHPRD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DSACTRL */
+#define _MODEM_DSACTRL_SCHPRD_TS2 0x00000000UL /**< Mode TS2 for MODEM_DSACTRL */
+#define _MODEM_DSACTRL_SCHPRD_TS4 0x00000001UL /**< Mode TS4 for MODEM_DSACTRL */
+#define MODEM_DSACTRL_SCHPRD_DEFAULT (_MODEM_DSACTRL_SCHPRD_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_DSACTRL */
+#define MODEM_DSACTRL_SCHPRD_TS2 (_MODEM_DSACTRL_SCHPRD_TS2 << 16) /**< Shifted mode TS2 for MODEM_DSACTRL */
+#define MODEM_DSACTRL_SCHPRD_TS4 (_MODEM_DSACTRL_SCHPRD_TS4 << 16) /**< Shifted mode TS4 for MODEM_DSACTRL */
+#define MODEM_DSACTRL_FREQAVGSYM (0x1UL << 17) /**< DSA frequency estimation averaging */
+#define _MODEM_DSACTRL_FREQAVGSYM_SHIFT 17 /**< Shift value for MODEM_FREQAVGSYM */
+#define _MODEM_DSACTRL_FREQAVGSYM_MASK 0x20000UL /**< Bit mask for MODEM_FREQAVGSYM */
+#define _MODEM_DSACTRL_FREQAVGSYM_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_DSACTRL */
+#define _MODEM_DSACTRL_FREQAVGSYM_AVG2TS 0x00000000UL /**< Mode AVG2TS for MODEM_DSACTRL */
+#define _MODEM_DSACTRL_FREQAVGSYM_AVG4TS 0x00000001UL /**< Mode AVG4TS for MODEM_DSACTRL */
+#define MODEM_DSACTRL_FREQAVGSYM_DEFAULT (_MODEM_DSACTRL_FREQAVGSYM_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_DSACTRL */
+#define MODEM_DSACTRL_FREQAVGSYM_AVG2TS (_MODEM_DSACTRL_FREQAVGSYM_AVG2TS << 17) /**< Shifted mode AVG2TS for MODEM_DSACTRL */
+#define MODEM_DSACTRL_FREQAVGSYM_AVG4TS (_MODEM_DSACTRL_FREQAVGSYM_AVG4TS << 17) /**< Shifted mode AVG4TS for MODEM_DSACTRL */
+#define MODEM_DSACTRL_TRANRSTDSA (0x1UL << 18) /**< power transient detector Reset DSA */
+#define _MODEM_DSACTRL_TRANRSTDSA_SHIFT 18 /**< Shift value for MODEM_TRANRSTDSA */
+#define _MODEM_DSACTRL_TRANRSTDSA_MASK 0x40000UL /**< Bit mask for MODEM_TRANRSTDSA */
+#define _MODEM_DSACTRL_TRANRSTDSA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DSACTRL */
+#define MODEM_DSACTRL_TRANRSTDSA_DEFAULT (_MODEM_DSACTRL_TRANRSTDSA_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_DSACTRL */
+#define MODEM_DSACTRL_DSARSTON (0x1UL << 19) /**< DSA detection reset */
+#define _MODEM_DSACTRL_DSARSTON_SHIFT 19 /**< Shift value for MODEM_DSARSTON */
+#define _MODEM_DSACTRL_DSARSTON_MASK 0x80000UL /**< Bit mask for MODEM_DSARSTON */
+#define _MODEM_DSACTRL_DSARSTON_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_DSACTRL */
+#define MODEM_DSACTRL_DSARSTON_DEFAULT (_MODEM_DSACTRL_DSARSTON_DEFAULT << 19) /**< Shifted mode DEFAULT for MODEM_DSACTRL */
+#define _MODEM_DSACTRL_GAINREDUCDLY_SHIFT 21 /**< Shift value for MODEM_GAINREDUCDLY */
+#define _MODEM_DSACTRL_GAINREDUCDLY_MASK 0x600000UL /**< Bit mask for MODEM_GAINREDUCDLY */
+#define _MODEM_DSACTRL_GAINREDUCDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DSACTRL */
+#define MODEM_DSACTRL_GAINREDUCDLY_DEFAULT (_MODEM_DSACTRL_GAINREDUCDLY_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_DSACTRL */
+#define _MODEM_DSACTRL_LOWDUTY_SHIFT 23 /**< Shift value for MODEM_LOWDUTY */
+#define _MODEM_DSACTRL_LOWDUTY_MASK 0x3800000UL /**< Bit mask for MODEM_LOWDUTY */
+#define _MODEM_DSACTRL_LOWDUTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DSACTRL */
+#define MODEM_DSACTRL_LOWDUTY_DEFAULT (_MODEM_DSACTRL_LOWDUTY_DEFAULT << 23) /**< Shifted mode DEFAULT for MODEM_DSACTRL */
+#define MODEM_DSACTRL_RESTORE (0x1UL << 26) /**< Power detector reset of DSA */
+#define _MODEM_DSACTRL_RESTORE_SHIFT 26 /**< Shift value for MODEM_RESTORE */
+#define _MODEM_DSACTRL_RESTORE_MASK 0x4000000UL /**< Bit mask for MODEM_RESTORE */
+#define _MODEM_DSACTRL_RESTORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DSACTRL */
+#define MODEM_DSACTRL_RESTORE_DEFAULT (_MODEM_DSACTRL_RESTORE_DEFAULT << 26) /**< Shifted mode DEFAULT for MODEM_DSACTRL */
+#define MODEM_DSACTRL_AGCBAUDEN (0x1UL << 27) /**< Consider Baud_en from AGC */
+#define _MODEM_DSACTRL_AGCBAUDEN_SHIFT 27 /**< Shift value for MODEM_AGCBAUDEN */
+#define _MODEM_DSACTRL_AGCBAUDEN_MASK 0x8000000UL /**< Bit mask for MODEM_AGCBAUDEN */
+#define _MODEM_DSACTRL_AGCBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DSACTRL */
+#define MODEM_DSACTRL_AGCBAUDEN_DEFAULT (_MODEM_DSACTRL_AGCBAUDEN_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_DSACTRL */
+#define _MODEM_DSACTRL_AMPJUPTHD_SHIFT 28 /**< Shift value for MODEM_AMPJUPTHD */
+#define _MODEM_DSACTRL_AMPJUPTHD_MASK 0xF0000000UL /**< Bit mask for MODEM_AMPJUPTHD */
+#define _MODEM_DSACTRL_AMPJUPTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DSACTRL */
+#define MODEM_DSACTRL_AMPJUPTHD_DEFAULT (_MODEM_DSACTRL_AMPJUPTHD_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_DSACTRL */
+
+/* Bit fields for MODEM DIGMIXCTRL */
+#define _MODEM_DIGMIXCTRL_RESETVALUE 0x00000000UL /**< Default value for MODEM_DIGMIXCTRL */
+#define _MODEM_DIGMIXCTRL_MASK 0x007FFFFFUL /**< Mask for MODEM_DIGMIXCTRL */
+#define _MODEM_DIGMIXCTRL_DIGMIXFREQ_SHIFT 0 /**< Shift value for MODEM_DIGMIXFREQ */
+#define _MODEM_DIGMIXCTRL_DIGMIXFREQ_MASK 0xFFFFFUL /**< Bit mask for MODEM_DIGMIXFREQ */
+#define _MODEM_DIGMIXCTRL_DIGMIXFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DIGMIXCTRL */
+#define MODEM_DIGMIXCTRL_DIGMIXFREQ_DEFAULT (_MODEM_DIGMIXCTRL_DIGMIXFREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_DIGMIXCTRL */
+#define MODEM_DIGMIXCTRL_DIGMIXMODE (0x1UL << 20) /**< Digital mixer frequency control */
+#define _MODEM_DIGMIXCTRL_DIGMIXMODE_SHIFT 20 /**< Shift value for MODEM_DIGMIXMODE */
+#define _MODEM_DIGMIXCTRL_DIGMIXMODE_MASK 0x100000UL /**< Bit mask for MODEM_DIGMIXMODE */
+#define _MODEM_DIGMIXCTRL_DIGMIXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DIGMIXCTRL */
+#define _MODEM_DIGMIXCTRL_DIGMIXMODE_CFOSR 0x00000000UL /**< Mode CFOSR for MODEM_DIGMIXCTRL */
+#define _MODEM_DIGMIXCTRL_DIGMIXMODE_DIGMIXFREQ 0x00000001UL /**< Mode DIGMIXFREQ for MODEM_DIGMIXCTRL */
+#define MODEM_DIGMIXCTRL_DIGMIXMODE_DEFAULT (_MODEM_DIGMIXCTRL_DIGMIXMODE_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_DIGMIXCTRL */
+#define MODEM_DIGMIXCTRL_DIGMIXMODE_CFOSR (_MODEM_DIGMIXCTRL_DIGMIXMODE_CFOSR << 20) /**< Shifted mode CFOSR for MODEM_DIGMIXCTRL */
+#define MODEM_DIGMIXCTRL_DIGMIXMODE_DIGMIXFREQ (_MODEM_DIGMIXCTRL_DIGMIXMODE_DIGMIXFREQ << 20) /**< Shifted mode DIGMIXFREQ for MODEM_DIGMIXCTRL*/
+#define MODEM_DIGMIXCTRL_MIXERCONJ (0x1UL << 21) /**< Digital mixer input conjugate */
+#define _MODEM_DIGMIXCTRL_MIXERCONJ_SHIFT 21 /**< Shift value for MODEM_MIXERCONJ */
+#define _MODEM_DIGMIXCTRL_MIXERCONJ_MASK 0x200000UL /**< Bit mask for MODEM_MIXERCONJ */
+#define _MODEM_DIGMIXCTRL_MIXERCONJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DIGMIXCTRL */
+#define MODEM_DIGMIXCTRL_MIXERCONJ_DEFAULT (_MODEM_DIGMIXCTRL_MIXERCONJ_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_DIGMIXCTRL */
+#define MODEM_DIGMIXCTRL_DIGMIXFB (0x1UL << 22) /**< Digital mixer Frequency Correction */
+#define _MODEM_DIGMIXCTRL_DIGMIXFB_SHIFT 22 /**< Shift value for MODEM_DIGMIXFB */
+#define _MODEM_DIGMIXCTRL_DIGMIXFB_MASK 0x400000UL /**< Bit mask for MODEM_DIGMIXFB */
+#define _MODEM_DIGMIXCTRL_DIGMIXFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DIGMIXCTRL */
+#define MODEM_DIGMIXCTRL_DIGMIXFB_DEFAULT (_MODEM_DIGMIXCTRL_DIGMIXFB_DEFAULT << 22) /**< Shifted mode DEFAULT for MODEM_DIGMIXCTRL */
+
+/* Bit fields for MODEM VITERBIDEMOD */
+#define _MODEM_VITERBIDEMOD_RESETVALUE 0x00206100UL /**< Default value for MODEM_VITERBIDEMOD */
+#define _MODEM_VITERBIDEMOD_MASK 0xFFFFFFFFUL /**< Mask for MODEM_VITERBIDEMOD */
+#define MODEM_VITERBIDEMOD_VTDEMODEN (0x1UL << 0) /**< Viterbi demodulator enable */
+#define _MODEM_VITERBIDEMOD_VTDEMODEN_SHIFT 0 /**< Shift value for MODEM_VTDEMODEN */
+#define _MODEM_VITERBIDEMOD_VTDEMODEN_MASK 0x1UL /**< Bit mask for MODEM_VTDEMODEN */
+#define _MODEM_VITERBIDEMOD_VTDEMODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_VITERBIDEMOD */
+#define MODEM_VITERBIDEMOD_VTDEMODEN_DEFAULT (_MODEM_VITERBIDEMOD_VTDEMODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_VITERBIDEMOD */
+#define MODEM_VITERBIDEMOD_HARDDECISION (0x1UL << 1) /**< Hard decision */
+#define _MODEM_VITERBIDEMOD_HARDDECISION_SHIFT 1 /**< Shift value for MODEM_HARDDECISION */
+#define _MODEM_VITERBIDEMOD_HARDDECISION_MASK 0x2UL /**< Bit mask for MODEM_HARDDECISION */
+#define _MODEM_VITERBIDEMOD_HARDDECISION_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_VITERBIDEMOD */
+#define MODEM_VITERBIDEMOD_HARDDECISION_DEFAULT (_MODEM_VITERBIDEMOD_HARDDECISION_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_VITERBIDEMOD */
+#define _MODEM_VITERBIDEMOD_VITERBIKSI1_SHIFT 2 /**< Shift value for MODEM_VITERBIKSI1 */
+#define _MODEM_VITERBIDEMOD_VITERBIKSI1_MASK 0x1FCUL /**< Bit mask for MODEM_VITERBIKSI1 */
+#define _MODEM_VITERBIDEMOD_VITERBIKSI1_DEFAULT 0x00000040UL /**< Mode DEFAULT for MODEM_VITERBIDEMOD */
+#define MODEM_VITERBIDEMOD_VITERBIKSI1_DEFAULT (_MODEM_VITERBIDEMOD_VITERBIKSI1_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_VITERBIDEMOD */
+#define _MODEM_VITERBIDEMOD_VITERBIKSI2_SHIFT 9 /**< Shift value for MODEM_VITERBIKSI2 */
+#define _MODEM_VITERBIDEMOD_VITERBIKSI2_MASK 0xFE00UL /**< Bit mask for MODEM_VITERBIKSI2 */
+#define _MODEM_VITERBIDEMOD_VITERBIKSI2_DEFAULT 0x00000030UL /**< Mode DEFAULT for MODEM_VITERBIDEMOD */
+#define MODEM_VITERBIDEMOD_VITERBIKSI2_DEFAULT (_MODEM_VITERBIDEMOD_VITERBIKSI2_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_VITERBIDEMOD */
+#define _MODEM_VITERBIDEMOD_VITERBIKSI3_SHIFT 16 /**< Shift value for MODEM_VITERBIKSI3 */
+#define _MODEM_VITERBIDEMOD_VITERBIKSI3_MASK 0x7F0000UL /**< Bit mask for MODEM_VITERBIKSI3 */
+#define _MODEM_VITERBIDEMOD_VITERBIKSI3_DEFAULT 0x00000020UL /**< Mode DEFAULT for MODEM_VITERBIDEMOD */
+#define MODEM_VITERBIDEMOD_VITERBIKSI3_DEFAULT (_MODEM_VITERBIDEMOD_VITERBIKSI3_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_VITERBIDEMOD */
+#define MODEM_VITERBIDEMOD_SYNTHAFC (0x1UL << 23) /**< Synthesizer AFC in Viterbi demod */
+#define _MODEM_VITERBIDEMOD_SYNTHAFC_SHIFT 23 /**< Shift value for MODEM_SYNTHAFC */
+#define _MODEM_VITERBIDEMOD_SYNTHAFC_MASK 0x800000UL /**< Bit mask for MODEM_SYNTHAFC */
+#define _MODEM_VITERBIDEMOD_SYNTHAFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_VITERBIDEMOD */
+#define MODEM_VITERBIDEMOD_SYNTHAFC_DEFAULT (_MODEM_VITERBIDEMOD_SYNTHAFC_DEFAULT << 23) /**< Shifted mode DEFAULT for MODEM_VITERBIDEMOD */
+#define _MODEM_VITERBIDEMOD_CORRCYCLE_SHIFT 24 /**< Shift value for MODEM_CORRCYCLE */
+#define _MODEM_VITERBIDEMOD_CORRCYCLE_MASK 0xF000000UL /**< Bit mask for MODEM_CORRCYCLE */
+#define _MODEM_VITERBIDEMOD_CORRCYCLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_VITERBIDEMOD */
+#define MODEM_VITERBIDEMOD_CORRCYCLE_DEFAULT (_MODEM_VITERBIDEMOD_CORRCYCLE_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_VITERBIDEMOD */
+#define _MODEM_VITERBIDEMOD_CORRSTPSIZE_SHIFT 28 /**< Shift value for MODEM_CORRSTPSIZE */
+#define _MODEM_VITERBIDEMOD_CORRSTPSIZE_MASK 0xF0000000UL /**< Bit mask for MODEM_CORRSTPSIZE */
+#define _MODEM_VITERBIDEMOD_CORRSTPSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_VITERBIDEMOD */
+#define MODEM_VITERBIDEMOD_CORRSTPSIZE_DEFAULT (_MODEM_VITERBIDEMOD_CORRSTPSIZE_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_VITERBIDEMOD */
+
+/* Bit fields for MODEM VTCORRCFG0 */
+#define _MODEM_VTCORRCFG0_RESETVALUE 0x123556B7UL /**< Default value for MODEM_VTCORRCFG0 */
+#define _MODEM_VTCORRCFG0_MASK 0xFFFFFFFFUL /**< Mask for MODEM_VTCORRCFG0 */
+#define _MODEM_VTCORRCFG0_EXPECTPATT_SHIFT 0 /**< Shift value for MODEM_EXPECTPATT */
+#define _MODEM_VTCORRCFG0_EXPECTPATT_MASK 0xFFFFFFFFUL /**< Bit mask for MODEM_EXPECTPATT */
+#define _MODEM_VTCORRCFG0_EXPECTPATT_DEFAULT 0x123556B7UL /**< Mode DEFAULT for MODEM_VTCORRCFG0 */
+#define MODEM_VTCORRCFG0_EXPECTPATT_DEFAULT (_MODEM_VTCORRCFG0_EXPECTPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_VTCORRCFG0 */
+
+/* Bit fields for MODEM VTCORRCFG1 */
+#define _MODEM_VTCORRCFG1_RESETVALUE 0x5020C000UL /**< Default value for MODEM_VTCORRCFG1 */
+#define _MODEM_VTCORRCFG1_MASK 0xF7FDFFFFUL /**< Mask for MODEM_VTCORRCFG1 */
+#define _MODEM_VTCORRCFG1_VITERBIKSI3WB_SHIFT 0 /**< Shift value for MODEM_VITERBIKSI3WB */
+#define _MODEM_VTCORRCFG1_VITERBIKSI3WB_MASK 0x7FUL /**< Bit mask for MODEM_VITERBIKSI3WB */
+#define _MODEM_VTCORRCFG1_VITERBIKSI3WB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_VTCORRCFG1 */
+#define MODEM_VTCORRCFG1_VITERBIKSI3WB_DEFAULT (_MODEM_VTCORRCFG1_VITERBIKSI3WB_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_VTCORRCFG1 */
+#define MODEM_VTCORRCFG1_KSI3SWENABLE (0x1UL << 7) /**< WB KSI3 Switching Enable */
+#define _MODEM_VTCORRCFG1_KSI3SWENABLE_SHIFT 7 /**< Shift value for MODEM_KSI3SWENABLE */
+#define _MODEM_VTCORRCFG1_KSI3SWENABLE_MASK 0x80UL /**< Bit mask for MODEM_KSI3SWENABLE */
+#define _MODEM_VTCORRCFG1_KSI3SWENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_VTCORRCFG1 */
+#define MODEM_VTCORRCFG1_KSI3SWENABLE_DEFAULT (_MODEM_VTCORRCFG1_KSI3SWENABLE_DEFAULT << 7) /**< Shifted mode DEFAULT for MODEM_VTCORRCFG1 */
+#define _MODEM_VTCORRCFG1_VTFRQLIM_SHIFT 8 /**< Shift value for MODEM_VTFRQLIM */
+#define _MODEM_VTCORRCFG1_VTFRQLIM_MASK 0x1FF00UL /**< Bit mask for MODEM_VTFRQLIM */
+#define _MODEM_VTCORRCFG1_VTFRQLIM_DEFAULT 0x000000C0UL /**< Mode DEFAULT for MODEM_VTCORRCFG1 */
+#define MODEM_VTCORRCFG1_VTFRQLIM_DEFAULT (_MODEM_VTCORRCFG1_VTFRQLIM_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_VTCORRCFG1 */
+#define _MODEM_VTCORRCFG1_EXPSYNCLEN_SHIFT 18 /**< Shift value for MODEM_EXPSYNCLEN */
+#define _MODEM_VTCORRCFG1_EXPSYNCLEN_MASK 0x7FC0000UL /**< Bit mask for MODEM_EXPSYNCLEN */
+#define _MODEM_VTCORRCFG1_EXPSYNCLEN_DEFAULT 0x00000008UL /**< Mode DEFAULT for MODEM_VTCORRCFG1 */
+#define MODEM_VTCORRCFG1_EXPSYNCLEN_DEFAULT (_MODEM_VTCORRCFG1_EXPSYNCLEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_VTCORRCFG1 */
+#define _MODEM_VTCORRCFG1_EXPECTHT_SHIFT 28 /**< Shift value for MODEM_EXPECTHT */
+#define _MODEM_VTCORRCFG1_EXPECTHT_MASK 0xF0000000UL /**< Bit mask for MODEM_EXPECTHT */
+#define _MODEM_VTCORRCFG1_EXPECTHT_DEFAULT 0x00000005UL /**< Mode DEFAULT for MODEM_VTCORRCFG1 */
+#define MODEM_VTCORRCFG1_EXPECTHT_DEFAULT (_MODEM_VTCORRCFG1_EXPECTHT_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_VTCORRCFG1 */
+
+/* Bit fields for MODEM VTTRACK */
+#define _MODEM_VTTRACK_RESETVALUE 0x0D803B88UL /**< Default value for MODEM_VTTRACK */
+#define _MODEM_VTTRACK_MASK 0x3FFF3FFFUL /**< Mask for MODEM_VTTRACK */
+#define _MODEM_VTTRACK_FREQTRACKMODE_SHIFT 0 /**< Shift value for MODEM_FREQTRACKMODE */
+#define _MODEM_VTTRACK_FREQTRACKMODE_MASK 0x3UL /**< Bit mask for MODEM_FREQTRACKMODE */
+#define _MODEM_VTTRACK_FREQTRACKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_VTTRACK */
+#define _MODEM_VTTRACK_FREQTRACKMODE_DISABLED 0x00000000UL /**< Mode DISABLED for MODEM_VTTRACK */
+#define _MODEM_VTTRACK_FREQTRACKMODE_MODE1 0x00000001UL /**< Mode MODE1 for MODEM_VTTRACK */
+#define _MODEM_VTTRACK_FREQTRACKMODE_MODE2 0x00000002UL /**< Mode MODE2 for MODEM_VTTRACK */
+#define _MODEM_VTTRACK_FREQTRACKMODE_MODE3 0x00000003UL /**< Mode MODE3 for MODEM_VTTRACK */
+#define MODEM_VTTRACK_FREQTRACKMODE_DEFAULT (_MODEM_VTTRACK_FREQTRACKMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_VTTRACK */
+#define MODEM_VTTRACK_FREQTRACKMODE_DISABLED (_MODEM_VTTRACK_FREQTRACKMODE_DISABLED << 0) /**< Shifted mode DISABLED for MODEM_VTTRACK */
+#define MODEM_VTTRACK_FREQTRACKMODE_MODE1 (_MODEM_VTTRACK_FREQTRACKMODE_MODE1 << 0) /**< Shifted mode MODE1 for MODEM_VTTRACK */
+#define MODEM_VTTRACK_FREQTRACKMODE_MODE2 (_MODEM_VTTRACK_FREQTRACKMODE_MODE2 << 0) /**< Shifted mode MODE2 for MODEM_VTTRACK */
+#define MODEM_VTTRACK_FREQTRACKMODE_MODE3 (_MODEM_VTTRACK_FREQTRACKMODE_MODE3 << 0) /**< Shifted mode MODE3 for MODEM_VTTRACK */
+#define _MODEM_VTTRACK_TIMTRACKTHD_SHIFT 2 /**< Shift value for MODEM_TIMTRACKTHD */
+#define _MODEM_VTTRACK_TIMTRACKTHD_MASK 0x3CUL /**< Bit mask for MODEM_TIMTRACKTHD */
+#define _MODEM_VTTRACK_TIMTRACKTHD_DEFAULT 0x00000002UL /**< Mode DEFAULT for MODEM_VTTRACK */
+#define MODEM_VTTRACK_TIMTRACKTHD_DEFAULT (_MODEM_VTTRACK_TIMTRACKTHD_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_VTTRACK */
+#define _MODEM_VTTRACK_TIMEACQUTHD_SHIFT 6 /**< Shift value for MODEM_TIMEACQUTHD */
+#define _MODEM_VTTRACK_TIMEACQUTHD_MASK 0x3FC0UL /**< Bit mask for MODEM_TIMEACQUTHD */
+#define _MODEM_VTTRACK_TIMEACQUTHD_DEFAULT 0x000000EEUL /**< Mode DEFAULT for MODEM_VTTRACK */
+#define MODEM_VTTRACK_TIMEACQUTHD_DEFAULT (_MODEM_VTTRACK_TIMEACQUTHD_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_VTTRACK */
+#define _MODEM_VTTRACK_TIMGEAR_SHIFT 16 /**< Shift value for MODEM_TIMGEAR */
+#define _MODEM_VTTRACK_TIMGEAR_MASK 0x30000UL /**< Bit mask for MODEM_TIMGEAR */
+#define _MODEM_VTTRACK_TIMGEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_VTTRACK */
+#define _MODEM_VTTRACK_TIMGEAR_GEAR0 0x00000000UL /**< Mode GEAR0 for MODEM_VTTRACK */
+#define _MODEM_VTTRACK_TIMGEAR_GEAR1 0x00000001UL /**< Mode GEAR1 for MODEM_VTTRACK */
+#define _MODEM_VTTRACK_TIMGEAR_GEAR2 0x00000002UL /**< Mode GEAR2 for MODEM_VTTRACK */
+#define MODEM_VTTRACK_TIMGEAR_DEFAULT (_MODEM_VTTRACK_TIMGEAR_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_VTTRACK */
+#define MODEM_VTTRACK_TIMGEAR_GEAR0 (_MODEM_VTTRACK_TIMGEAR_GEAR0 << 16) /**< Shifted mode GEAR0 for MODEM_VTTRACK */
+#define MODEM_VTTRACK_TIMGEAR_GEAR1 (_MODEM_VTTRACK_TIMGEAR_GEAR1 << 16) /**< Shifted mode GEAR1 for MODEM_VTTRACK */
+#define MODEM_VTTRACK_TIMGEAR_GEAR2 (_MODEM_VTTRACK_TIMGEAR_GEAR2 << 16) /**< Shifted mode GEAR2 for MODEM_VTTRACK */
+#define _MODEM_VTTRACK_FREQBIAS_SHIFT 18 /**< Shift value for MODEM_FREQBIAS */
+#define _MODEM_VTTRACK_FREQBIAS_MASK 0x3C0000UL /**< Bit mask for MODEM_FREQBIAS */
+#define _MODEM_VTTRACK_FREQBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_VTTRACK */
+#define MODEM_VTTRACK_FREQBIAS_DEFAULT (_MODEM_VTTRACK_FREQBIAS_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_VTTRACK */
+#define _MODEM_VTTRACK_HIPWRTHD_SHIFT 22 /**< Shift value for MODEM_HIPWRTHD */
+#define _MODEM_VTTRACK_HIPWRTHD_MASK 0x3FC00000UL /**< Bit mask for MODEM_HIPWRTHD */
+#define _MODEM_VTTRACK_HIPWRTHD_DEFAULT 0x00000036UL /**< Mode DEFAULT for MODEM_VTTRACK */
+#define MODEM_VTTRACK_HIPWRTHD_DEFAULT (_MODEM_VTTRACK_HIPWRTHD_DEFAULT << 22) /**< Shifted mode DEFAULT for MODEM_VTTRACK */
+
+/* Bit fields for MODEM VTBLETIMING */
+#define _MODEM_VTBLETIMING_RESETVALUE 0x00000000UL /**< Default value for MODEM_VTBLETIMING */
+#define _MODEM_VTBLETIMING_MASK 0x8000FFF7UL /**< Mask for MODEM_VTBLETIMING */
+#define _MODEM_VTBLETIMING_VTBLETIMINGSEL_SHIFT 0 /**< Shift value for MODEM_VTBLETIMINGSEL */
+#define _MODEM_VTBLETIMING_VTBLETIMINGSEL_MASK 0x3UL /**< Bit mask for MODEM_VTBLETIMINGSEL */
+#define _MODEM_VTBLETIMING_VTBLETIMINGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_VTBLETIMING */
+#define _MODEM_VTBLETIMING_VTBLETIMINGSEL_FRAMEDET_DELAY 0x00000000UL /**< Mode FRAMEDET_DELAY for MODEM_VTBLETIMING */
+#define _MODEM_VTBLETIMING_VTBLETIMINGSEL_END_FRAME_PULSE 0x00000001UL /**< Mode END_FRAME_PULSE for MODEM_VTBLETIMING */
+#define _MODEM_VTBLETIMING_VTBLETIMINGSEL_END_FRAME 0x00000002UL /**< Mode END_FRAME for MODEM_VTBLETIMING */
+#define _MODEM_VTBLETIMING_VTBLETIMINGSEL_INV_END_FRAME 0x00000003UL /**< Mode INV_END_FRAME for MODEM_VTBLETIMING */
+#define MODEM_VTBLETIMING_VTBLETIMINGSEL_DEFAULT (_MODEM_VTBLETIMING_VTBLETIMINGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_VTBLETIMING */
+#define MODEM_VTBLETIMING_VTBLETIMINGSEL_FRAMEDET_DELAY (_MODEM_VTBLETIMING_VTBLETIMINGSEL_FRAMEDET_DELAY << 0) /**< Shifted mode FRAMEDET_DELAY for MODEM_VTBLETIMING*/
+#define MODEM_VTBLETIMING_VTBLETIMINGSEL_END_FRAME_PULSE (_MODEM_VTBLETIMING_VTBLETIMINGSEL_END_FRAME_PULSE << 0) /**< Shifted mode END_FRAME_PULSE for MODEM_VTBLETIMING*/
+#define MODEM_VTBLETIMING_VTBLETIMINGSEL_END_FRAME (_MODEM_VTBLETIMING_VTBLETIMINGSEL_END_FRAME << 0) /**< Shifted mode END_FRAME for MODEM_VTBLETIMING*/
+#define MODEM_VTBLETIMING_VTBLETIMINGSEL_INV_END_FRAME (_MODEM_VTBLETIMING_VTBLETIMINGSEL_INV_END_FRAME << 0) /**< Shifted mode INV_END_FRAME for MODEM_VTBLETIMING*/
+#define MODEM_VTBLETIMING_VTBLETIMINGCLKSEL (0x1UL << 2) /**< Viterbi BLE timing stamp clock select */
+#define _MODEM_VTBLETIMING_VTBLETIMINGCLKSEL_SHIFT 2 /**< Shift value for MODEM_VTBLETIMINGCLKSEL */
+#define _MODEM_VTBLETIMING_VTBLETIMINGCLKSEL_MASK 0x4UL /**< Bit mask for MODEM_VTBLETIMINGCLKSEL */
+#define _MODEM_VTBLETIMING_VTBLETIMINGCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_VTBLETIMING */
+#define MODEM_VTBLETIMING_VTBLETIMINGCLKSEL_DEFAULT (_MODEM_VTBLETIMING_VTBLETIMINGCLKSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_VTBLETIMING */
+#define _MODEM_VTBLETIMING_TIMINGDELAY_SHIFT 4 /**< Shift value for MODEM_TIMINGDELAY */
+#define _MODEM_VTBLETIMING_TIMINGDELAY_MASK 0xFF0UL /**< Bit mask for MODEM_TIMINGDELAY */
+#define _MODEM_VTBLETIMING_TIMINGDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_VTBLETIMING */
+#define MODEM_VTBLETIMING_TIMINGDELAY_DEFAULT (_MODEM_VTBLETIMING_TIMINGDELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_VTBLETIMING */
+#define _MODEM_VTBLETIMING_FLENOFF_SHIFT 12 /**< Shift value for MODEM_FLENOFF */
+#define _MODEM_VTBLETIMING_FLENOFF_MASK 0xF000UL /**< Bit mask for MODEM_FLENOFF */
+#define _MODEM_VTBLETIMING_FLENOFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_VTBLETIMING */
+#define MODEM_VTBLETIMING_FLENOFF_DEFAULT (_MODEM_VTBLETIMING_FLENOFF_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_VTBLETIMING */
+#define MODEM_VTBLETIMING_DISDEMODOF (0x1UL << 31) /**< Disable VT Demod Over Flow Detection */
+#define _MODEM_VTBLETIMING_DISDEMODOF_SHIFT 31 /**< Shift value for MODEM_DISDEMODOF */
+#define _MODEM_VTBLETIMING_DISDEMODOF_MASK 0x80000000UL /**< Bit mask for MODEM_DISDEMODOF */
+#define _MODEM_VTBLETIMING_DISDEMODOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_VTBLETIMING */
+#define MODEM_VTBLETIMING_DISDEMODOF_DEFAULT (_MODEM_VTBLETIMING_DISDEMODOF_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_VTBLETIMING */
+
+/* Bit fields for MODEM BREST */
+#define _MODEM_BREST_RESETVALUE 0x00000000UL /**< Default value for MODEM_BREST */
+#define _MODEM_BREST_MASK 0x000007FFUL /**< Mask for MODEM_BREST */
+#define _MODEM_BREST_BRESTINT_SHIFT 0 /**< Shift value for MODEM_BRESTINT */
+#define _MODEM_BREST_BRESTINT_MASK 0x3FUL /**< Bit mask for MODEM_BRESTINT */
+#define _MODEM_BREST_BRESTINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_BREST */
+#define MODEM_BREST_BRESTINT_DEFAULT (_MODEM_BREST_BRESTINT_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_BREST */
+#define _MODEM_BREST_BRESTNUM_SHIFT 6 /**< Shift value for MODEM_BRESTNUM */
+#define _MODEM_BREST_BRESTNUM_MASK 0x7C0UL /**< Bit mask for MODEM_BRESTNUM */
+#define _MODEM_BREST_BRESTNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_BREST */
+#define MODEM_BREST_BRESTNUM_DEFAULT (_MODEM_BREST_BRESTNUM_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_BREST */
+
+/* Bit fields for MODEM AUTOCG */
+#define _MODEM_AUTOCG_RESETVALUE 0x00000000UL /**< Default value for MODEM_AUTOCG */
+#define _MODEM_AUTOCG_MASK 0x0000FFFFUL /**< Mask for MODEM_AUTOCG */
+#define _MODEM_AUTOCG_AUTOCGEN_SHIFT 0 /**< Shift value for MODEM_AUTOCGEN */
+#define _MODEM_AUTOCG_AUTOCGEN_MASK 0xFFFFUL /**< Bit mask for MODEM_AUTOCGEN */
+#define _MODEM_AUTOCG_AUTOCGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_AUTOCG */
+#define MODEM_AUTOCG_AUTOCGEN_DEFAULT (_MODEM_AUTOCG_AUTOCGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_AUTOCG */
+
+/* Bit fields for MODEM CGCLKSTOP */
+#define _MODEM_CGCLKSTOP_RESETVALUE 0x00000000UL /**< Default value for MODEM_CGCLKSTOP */
+#define _MODEM_CGCLKSTOP_MASK 0x0000FFFFUL /**< Mask for MODEM_CGCLKSTOP */
+#define _MODEM_CGCLKSTOP_FORCEOFF_SHIFT 0 /**< Shift value for MODEM_FORCEOFF */
+#define _MODEM_CGCLKSTOP_FORCEOFF_MASK 0xFFFFUL /**< Bit mask for MODEM_FORCEOFF */
+#define _MODEM_CGCLKSTOP_FORCEOFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CGCLKSTOP */
+#define MODEM_CGCLKSTOP_FORCEOFF_DEFAULT (_MODEM_CGCLKSTOP_FORCEOFF_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CGCLKSTOP */
+
+/* Bit fields for MODEM POE */
+#define _MODEM_POE_RESETVALUE 0x00000000UL /**< Default value for MODEM_POE */
+#define _MODEM_POE_MASK 0x03FF03FFUL /**< Mask for MODEM_POE */
+#define _MODEM_POE_POEI_SHIFT 0 /**< Shift value for MODEM_POEI */
+#define _MODEM_POE_POEI_MASK 0x3FFUL /**< Bit mask for MODEM_POEI */
+#define _MODEM_POE_POEI_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_POE */
+#define MODEM_POE_POEI_DEFAULT (_MODEM_POE_POEI_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_POE */
+#define _MODEM_POE_POEQ_SHIFT 16 /**< Shift value for MODEM_POEQ */
+#define _MODEM_POE_POEQ_MASK 0x3FF0000UL /**< Bit mask for MODEM_POEQ */
+#define _MODEM_POE_POEQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_POE */
+#define MODEM_POE_POEQ_DEFAULT (_MODEM_POE_POEQ_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_POE */
+
+/* Bit fields for MODEM DIRECTMODE */
+#define _MODEM_DIRECTMODE_RESETVALUE 0x0000010CUL /**< Default value for MODEM_DIRECTMODE */
+#define _MODEM_DIRECTMODE_MASK 0x00001F0FUL /**< Mask for MODEM_DIRECTMODE */
+#define MODEM_DIRECTMODE_DMENABLE (0x1UL << 0) /**< Enable Direct Mode */
+#define _MODEM_DIRECTMODE_DMENABLE_SHIFT 0 /**< Shift value for MODEM_DMENABLE */
+#define _MODEM_DIRECTMODE_DMENABLE_MASK 0x1UL /**< Bit mask for MODEM_DMENABLE */
+#define _MODEM_DIRECTMODE_DMENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DIRECTMODE */
+#define MODEM_DIRECTMODE_DMENABLE_DEFAULT (_MODEM_DIRECTMODE_DMENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_DIRECTMODE */
+#define MODEM_DIRECTMODE_SYNCASYNC (0x1UL << 1) /**< Choose Synchronous or Asynchronous mode */
+#define _MODEM_DIRECTMODE_SYNCASYNC_SHIFT 1 /**< Shift value for MODEM_SYNCASYNC */
+#define _MODEM_DIRECTMODE_SYNCASYNC_MASK 0x2UL /**< Bit mask for MODEM_SYNCASYNC */
+#define _MODEM_DIRECTMODE_SYNCASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DIRECTMODE */
+#define MODEM_DIRECTMODE_SYNCASYNC_DEFAULT (_MODEM_DIRECTMODE_SYNCASYNC_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_DIRECTMODE */
+#define _MODEM_DIRECTMODE_SYNCPREAM_SHIFT 2 /**< Shift value for MODEM_SYNCPREAM */
+#define _MODEM_DIRECTMODE_SYNCPREAM_MASK 0xCUL /**< Bit mask for MODEM_SYNCPREAM */
+#define _MODEM_DIRECTMODE_SYNCPREAM_DEFAULT 0x00000003UL /**< Mode DEFAULT for MODEM_DIRECTMODE */
+#define _MODEM_DIRECTMODE_SYNCPREAM_ADD0 0x00000000UL /**< Mode ADD0 for MODEM_DIRECTMODE */
+#define _MODEM_DIRECTMODE_SYNCPREAM_ADD8 0x00000001UL /**< Mode ADD8 for MODEM_DIRECTMODE */
+#define _MODEM_DIRECTMODE_SYNCPREAM_ADD16 0x00000002UL /**< Mode ADD16 for MODEM_DIRECTMODE */
+#define _MODEM_DIRECTMODE_SYNCPREAM_ADD32 0x00000003UL /**< Mode ADD32 for MODEM_DIRECTMODE */
+#define MODEM_DIRECTMODE_SYNCPREAM_DEFAULT (_MODEM_DIRECTMODE_SYNCPREAM_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_DIRECTMODE */
+#define MODEM_DIRECTMODE_SYNCPREAM_ADD0 (_MODEM_DIRECTMODE_SYNCPREAM_ADD0 << 2) /**< Shifted mode ADD0 for MODEM_DIRECTMODE */
+#define MODEM_DIRECTMODE_SYNCPREAM_ADD8 (_MODEM_DIRECTMODE_SYNCPREAM_ADD8 << 2) /**< Shifted mode ADD8 for MODEM_DIRECTMODE */
+#define MODEM_DIRECTMODE_SYNCPREAM_ADD16 (_MODEM_DIRECTMODE_SYNCPREAM_ADD16 << 2) /**< Shifted mode ADD16 for MODEM_DIRECTMODE */
+#define MODEM_DIRECTMODE_SYNCPREAM_ADD32 (_MODEM_DIRECTMODE_SYNCPREAM_ADD32 << 2) /**< Shifted mode ADD32 for MODEM_DIRECTMODE */
+#define _MODEM_DIRECTMODE_CLKWIDTH_SHIFT 8 /**< Shift value for MODEM_CLKWIDTH */
+#define _MODEM_DIRECTMODE_CLKWIDTH_MASK 0x1F00UL /**< Bit mask for MODEM_CLKWIDTH */
+#define _MODEM_DIRECTMODE_CLKWIDTH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_DIRECTMODE */
+#define MODEM_DIRECTMODE_CLKWIDTH_DEFAULT (_MODEM_DIRECTMODE_CLKWIDTH_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_DIRECTMODE */
+
+/* Bit fields for MODEM LONGRANGE */
+#define _MODEM_LONGRANGE_RESETVALUE 0x00FA53E8UL /**< Default value for MODEM_LONGRANGE */
+#define _MODEM_LONGRANGE_MASK 0x7FFFFFFFUL /**< Mask for MODEM_LONGRANGE */
+#define _MODEM_LONGRANGE_LRCORRTHD_SHIFT 0 /**< Shift value for MODEM_LRCORRTHD */
+#define _MODEM_LONGRANGE_LRCORRTHD_MASK 0x7FFUL /**< Bit mask for MODEM_LRCORRTHD */
+#define _MODEM_LONGRANGE_LRCORRTHD_DEFAULT 0x000003E8UL /**< Mode DEFAULT for MODEM_LONGRANGE */
+#define MODEM_LONGRANGE_LRCORRTHD_DEFAULT (_MODEM_LONGRANGE_LRCORRTHD_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_LONGRANGE */
+#define _MODEM_LONGRANGE_LRCORRSCHWIN_SHIFT 11 /**< Shift value for MODEM_LRCORRSCHWIN */
+#define _MODEM_LONGRANGE_LRCORRSCHWIN_MASK 0x7800UL /**< Bit mask for MODEM_LRCORRSCHWIN */
+#define _MODEM_LONGRANGE_LRCORRSCHWIN_DEFAULT 0x0000000AUL /**< Mode DEFAULT for MODEM_LONGRANGE */
+#define MODEM_LONGRANGE_LRCORRSCHWIN_DEFAULT (_MODEM_LONGRANGE_LRCORRSCHWIN_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_LONGRANGE */
+#define MODEM_LONGRANGE_LRBLE (0x1UL << 15) /**< Enable */
+#define _MODEM_LONGRANGE_LRBLE_SHIFT 15 /**< Shift value for MODEM_LRBLE */
+#define _MODEM_LONGRANGE_LRBLE_MASK 0x8000UL /**< Bit mask for MODEM_LRBLE */
+#define _MODEM_LONGRANGE_LRBLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE */
+#define MODEM_LONGRANGE_LRBLE_DEFAULT (_MODEM_LONGRANGE_LRBLE_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_LONGRANGE */
+#define _MODEM_LONGRANGE_LRTIMCORRTHD_SHIFT 16 /**< Shift value for MODEM_LRTIMCORRTHD */
+#define _MODEM_LONGRANGE_LRTIMCORRTHD_MASK 0x7FF0000UL /**< Bit mask for MODEM_LRTIMCORRTHD */
+#define _MODEM_LONGRANGE_LRTIMCORRTHD_DEFAULT 0x000000FAUL /**< Mode DEFAULT for MODEM_LONGRANGE */
+#define MODEM_LONGRANGE_LRTIMCORRTHD_DEFAULT (_MODEM_LONGRANGE_LRTIMCORRTHD_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_LONGRANGE */
+#define MODEM_LONGRANGE_LRBLEDSA (0x1UL << 27) /**< DSA enable */
+#define _MODEM_LONGRANGE_LRBLEDSA_SHIFT 27 /**< Shift value for MODEM_LRBLEDSA */
+#define _MODEM_LONGRANGE_LRBLEDSA_MASK 0x8000000UL /**< Bit mask for MODEM_LRBLEDSA */
+#define _MODEM_LONGRANGE_LRBLEDSA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE */
+#define MODEM_LONGRANGE_LRBLEDSA_DEFAULT (_MODEM_LONGRANGE_LRBLEDSA_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_LONGRANGE */
+#define _MODEM_LONGRANGE_LRDEC_SHIFT 28 /**< Shift value for MODEM_LRDEC */
+#define _MODEM_LONGRANGE_LRDEC_MASK 0x70000000UL /**< Bit mask for MODEM_LRDEC */
+#define _MODEM_LONGRANGE_LRDEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE */
+#define MODEM_LONGRANGE_LRDEC_DEFAULT (_MODEM_LONGRANGE_LRDEC_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_LONGRANGE */
+
+/* Bit fields for MODEM LONGRANGE1 */
+#define _MODEM_LONGRANGE1_RESETVALUE 0x40000000UL /**< Default value for MODEM_LONGRANGE1 */
+#define _MODEM_LONGRANGE1_MASK 0xFFFF7FFFUL /**< Mask for MODEM_LONGRANGE1 */
+#define _MODEM_LONGRANGE1_LRSS_SHIFT 0 /**< Shift value for MODEM_LRSS */
+#define _MODEM_LONGRANGE1_LRSS_MASK 0xFUL /**< Bit mask for MODEM_LRSS */
+#define _MODEM_LONGRANGE1_LRSS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE1 */
+#define MODEM_LONGRANGE1_LRSS_DEFAULT (_MODEM_LONGRANGE1_LRSS_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_LONGRANGE1 */
+#define _MODEM_LONGRANGE1_LRTIMEOUTTHD_SHIFT 4 /**< Shift value for MODEM_LRTIMEOUTTHD */
+#define _MODEM_LONGRANGE1_LRTIMEOUTTHD_MASK 0x7FF0UL /**< Bit mask for MODEM_LRTIMEOUTTHD */
+#define _MODEM_LONGRANGE1_LRTIMEOUTTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE1 */
+#define MODEM_LONGRANGE1_LRTIMEOUTTHD_DEFAULT (_MODEM_LONGRANGE1_LRTIMEOUTTHD_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_LONGRANGE1 */
+#define _MODEM_LONGRANGE1_CHPWRACCUDEL_SHIFT 16 /**< Shift value for MODEM_CHPWRACCUDEL */
+#define _MODEM_LONGRANGE1_CHPWRACCUDEL_MASK 0x30000UL /**< Bit mask for MODEM_CHPWRACCUDEL */
+#define _MODEM_LONGRANGE1_CHPWRACCUDEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE1 */
+#define _MODEM_LONGRANGE1_CHPWRACCUDEL_DEL0 0x00000000UL /**< Mode DEL0 for MODEM_LONGRANGE1 */
+#define _MODEM_LONGRANGE1_CHPWRACCUDEL_DEL32 0x00000001UL /**< Mode DEL32 for MODEM_LONGRANGE1 */
+#define _MODEM_LONGRANGE1_CHPWRACCUDEL_DEL64 0x00000002UL /**< Mode DEL64 for MODEM_LONGRANGE1 */
+#define MODEM_LONGRANGE1_CHPWRACCUDEL_DEFAULT (_MODEM_LONGRANGE1_CHPWRACCUDEL_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_LONGRANGE1 */
+#define MODEM_LONGRANGE1_CHPWRACCUDEL_DEL0 (_MODEM_LONGRANGE1_CHPWRACCUDEL_DEL0 << 16) /**< Shifted mode DEL0 for MODEM_LONGRANGE1 */
+#define MODEM_LONGRANGE1_CHPWRACCUDEL_DEL32 (_MODEM_LONGRANGE1_CHPWRACCUDEL_DEL32 << 16) /**< Shifted mode DEL32 for MODEM_LONGRANGE1 */
+#define MODEM_LONGRANGE1_CHPWRACCUDEL_DEL64 (_MODEM_LONGRANGE1_CHPWRACCUDEL_DEL64 << 16) /**< Shifted mode DEL64 for MODEM_LONGRANGE1 */
+#define _MODEM_LONGRANGE1_HYSVAL_SHIFT 18 /**< Shift value for MODEM_HYSVAL */
+#define _MODEM_LONGRANGE1_HYSVAL_MASK 0x1C0000UL /**< Bit mask for MODEM_HYSVAL */
+#define _MODEM_LONGRANGE1_HYSVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE1 */
+#define MODEM_LONGRANGE1_HYSVAL_DEFAULT (_MODEM_LONGRANGE1_HYSVAL_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_LONGRANGE1 */
+#define _MODEM_LONGRANGE1_AVGWIN_SHIFT 21 /**< Shift value for MODEM_AVGWIN */
+#define _MODEM_LONGRANGE1_AVGWIN_MASK 0xE00000UL /**< Bit mask for MODEM_AVGWIN */
+#define _MODEM_LONGRANGE1_AVGWIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE1 */
+#define MODEM_LONGRANGE1_AVGWIN_DEFAULT (_MODEM_LONGRANGE1_AVGWIN_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_LONGRANGE1 */
+#define _MODEM_LONGRANGE1_LRSPIKETHADD_SHIFT 24 /**< Shift value for MODEM_LRSPIKETHADD */
+#define _MODEM_LONGRANGE1_LRSPIKETHADD_MASK 0xF000000UL /**< Bit mask for MODEM_LRSPIKETHADD */
+#define _MODEM_LONGRANGE1_LRSPIKETHADD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE1 */
+#define MODEM_LONGRANGE1_LRSPIKETHADD_DEFAULT (_MODEM_LONGRANGE1_LRSPIKETHADD_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_LONGRANGE1 */
+#define MODEM_LONGRANGE1_LOGICBASEDPUGATE (0x1UL << 28) /**< Logic Based Phase Unwrap Gating */
+#define _MODEM_LONGRANGE1_LOGICBASEDPUGATE_SHIFT 28 /**< Shift value for MODEM_LOGICBASEDPUGATE */
+#define _MODEM_LONGRANGE1_LOGICBASEDPUGATE_MASK 0x10000000UL /**< Bit mask for MODEM_LOGICBASEDPUGATE */
+#define _MODEM_LONGRANGE1_LOGICBASEDPUGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE1 */
+#define MODEM_LONGRANGE1_LOGICBASEDPUGATE_DEFAULT (_MODEM_LONGRANGE1_LOGICBASEDPUGATE_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_LONGRANGE1 */
+#define MODEM_LONGRANGE1_LOGICBASEDLRDEMODGATE (0x1UL << 29) /**< Logic Based Long Range Demod Gating */
+#define _MODEM_LONGRANGE1_LOGICBASEDLRDEMODGATE_SHIFT 29 /**< Shift value for MODEM_LOGICBASEDLRDEMODGATE */
+#define _MODEM_LONGRANGE1_LOGICBASEDLRDEMODGATE_MASK 0x20000000UL /**< Bit mask for MODEM_LOGICBASEDLRDEMODGATE */
+#define _MODEM_LONGRANGE1_LOGICBASEDLRDEMODGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE1 */
+#define MODEM_LONGRANGE1_LOGICBASEDLRDEMODGATE_DEFAULT (_MODEM_LONGRANGE1_LOGICBASEDLRDEMODGATE_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_LONGRANGE1 */
+#define _MODEM_LONGRANGE1_PREFILTLEN_SHIFT 30 /**< Shift value for MODEM_PREFILTLEN */
+#define _MODEM_LONGRANGE1_PREFILTLEN_MASK 0xC0000000UL /**< Bit mask for MODEM_PREFILTLEN */
+#define _MODEM_LONGRANGE1_PREFILTLEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_LONGRANGE1 */
+#define _MODEM_LONGRANGE1_PREFILTLEN_LEN32 0x00000000UL /**< Mode LEN32 for MODEM_LONGRANGE1 */
+#define _MODEM_LONGRANGE1_PREFILTLEN_LEN64 0x00000001UL /**< Mode LEN64 for MODEM_LONGRANGE1 */
+#define _MODEM_LONGRANGE1_PREFILTLEN_LEN96 0x00000002UL /**< Mode LEN96 for MODEM_LONGRANGE1 */
+#define _MODEM_LONGRANGE1_PREFILTLEN_LEN128 0x00000003UL /**< Mode LEN128 for MODEM_LONGRANGE1 */
+#define MODEM_LONGRANGE1_PREFILTLEN_DEFAULT (_MODEM_LONGRANGE1_PREFILTLEN_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_LONGRANGE1 */
+#define MODEM_LONGRANGE1_PREFILTLEN_LEN32 (_MODEM_LONGRANGE1_PREFILTLEN_LEN32 << 30) /**< Shifted mode LEN32 for MODEM_LONGRANGE1 */
+#define MODEM_LONGRANGE1_PREFILTLEN_LEN64 (_MODEM_LONGRANGE1_PREFILTLEN_LEN64 << 30) /**< Shifted mode LEN64 for MODEM_LONGRANGE1 */
+#define MODEM_LONGRANGE1_PREFILTLEN_LEN96 (_MODEM_LONGRANGE1_PREFILTLEN_LEN96 << 30) /**< Shifted mode LEN96 for MODEM_LONGRANGE1 */
+#define MODEM_LONGRANGE1_PREFILTLEN_LEN128 (_MODEM_LONGRANGE1_PREFILTLEN_LEN128 << 30) /**< Shifted mode LEN128 for MODEM_LONGRANGE1 */
+
+/* Bit fields for MODEM LONGRANGE2 */
+#define _MODEM_LONGRANGE2_RESETVALUE 0x00000000UL /**< Default value for MODEM_LONGRANGE2 */
+#define _MODEM_LONGRANGE2_MASK 0xFFFFFFFFUL /**< Mask for MODEM_LONGRANGE2 */
+#define _MODEM_LONGRANGE2_LRCHPWRTH1_SHIFT 0 /**< Shift value for MODEM_LRCHPWRTH1 */
+#define _MODEM_LONGRANGE2_LRCHPWRTH1_MASK 0xFFUL /**< Bit mask for MODEM_LRCHPWRTH1 */
+#define _MODEM_LONGRANGE2_LRCHPWRTH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE2 */
+#define MODEM_LONGRANGE2_LRCHPWRTH1_DEFAULT (_MODEM_LONGRANGE2_LRCHPWRTH1_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_LONGRANGE2 */
+#define _MODEM_LONGRANGE2_LRCHPWRTH2_SHIFT 8 /**< Shift value for MODEM_LRCHPWRTH2 */
+#define _MODEM_LONGRANGE2_LRCHPWRTH2_MASK 0xFF00UL /**< Bit mask for MODEM_LRCHPWRTH2 */
+#define _MODEM_LONGRANGE2_LRCHPWRTH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE2 */
+#define MODEM_LONGRANGE2_LRCHPWRTH2_DEFAULT (_MODEM_LONGRANGE2_LRCHPWRTH2_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_LONGRANGE2 */
+#define _MODEM_LONGRANGE2_LRCHPWRTH3_SHIFT 16 /**< Shift value for MODEM_LRCHPWRTH3 */
+#define _MODEM_LONGRANGE2_LRCHPWRTH3_MASK 0xFF0000UL /**< Bit mask for MODEM_LRCHPWRTH3 */
+#define _MODEM_LONGRANGE2_LRCHPWRTH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE2 */
+#define MODEM_LONGRANGE2_LRCHPWRTH3_DEFAULT (_MODEM_LONGRANGE2_LRCHPWRTH3_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_LONGRANGE2 */
+#define _MODEM_LONGRANGE2_LRCHPWRTH4_SHIFT 24 /**< Shift value for MODEM_LRCHPWRTH4 */
+#define _MODEM_LONGRANGE2_LRCHPWRTH4_MASK 0xFF000000UL /**< Bit mask for MODEM_LRCHPWRTH4 */
+#define _MODEM_LONGRANGE2_LRCHPWRTH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE2 */
+#define MODEM_LONGRANGE2_LRCHPWRTH4_DEFAULT (_MODEM_LONGRANGE2_LRCHPWRTH4_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_LONGRANGE2 */
+
+/* Bit fields for MODEM LONGRANGE3 */
+#define _MODEM_LONGRANGE3_RESETVALUE 0x00000000UL /**< Default value for MODEM_LONGRANGE3 */
+#define _MODEM_LONGRANGE3_MASK 0xFFFFFFFFUL /**< Mask for MODEM_LONGRANGE3 */
+#define _MODEM_LONGRANGE3_LRCHPWRTH5_SHIFT 0 /**< Shift value for MODEM_LRCHPWRTH5 */
+#define _MODEM_LONGRANGE3_LRCHPWRTH5_MASK 0xFFUL /**< Bit mask for MODEM_LRCHPWRTH5 */
+#define _MODEM_LONGRANGE3_LRCHPWRTH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE3 */
+#define MODEM_LONGRANGE3_LRCHPWRTH5_DEFAULT (_MODEM_LONGRANGE3_LRCHPWRTH5_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_LONGRANGE3 */
+#define _MODEM_LONGRANGE3_LRCHPWRTH6_SHIFT 8 /**< Shift value for MODEM_LRCHPWRTH6 */
+#define _MODEM_LONGRANGE3_LRCHPWRTH6_MASK 0xFF00UL /**< Bit mask for MODEM_LRCHPWRTH6 */
+#define _MODEM_LONGRANGE3_LRCHPWRTH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE3 */
+#define MODEM_LONGRANGE3_LRCHPWRTH6_DEFAULT (_MODEM_LONGRANGE3_LRCHPWRTH6_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_LONGRANGE3 */
+#define _MODEM_LONGRANGE3_LRCHPWRTH7_SHIFT 16 /**< Shift value for MODEM_LRCHPWRTH7 */
+#define _MODEM_LONGRANGE3_LRCHPWRTH7_MASK 0xFF0000UL /**< Bit mask for MODEM_LRCHPWRTH7 */
+#define _MODEM_LONGRANGE3_LRCHPWRTH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE3 */
+#define MODEM_LONGRANGE3_LRCHPWRTH7_DEFAULT (_MODEM_LONGRANGE3_LRCHPWRTH7_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_LONGRANGE3 */
+#define _MODEM_LONGRANGE3_LRCHPWRTH8_SHIFT 24 /**< Shift value for MODEM_LRCHPWRTH8 */
+#define _MODEM_LONGRANGE3_LRCHPWRTH8_MASK 0xFF000000UL /**< Bit mask for MODEM_LRCHPWRTH8 */
+#define _MODEM_LONGRANGE3_LRCHPWRTH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE3 */
+#define MODEM_LONGRANGE3_LRCHPWRTH8_DEFAULT (_MODEM_LONGRANGE3_LRCHPWRTH8_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_LONGRANGE3 */
+
+/* Bit fields for MODEM LONGRANGE4 */
+#define _MODEM_LONGRANGE4_RESETVALUE 0x00000000UL /**< Default value for MODEM_LONGRANGE4 */
+#define _MODEM_LONGRANGE4_MASK 0xFFFFFFFFUL /**< Mask for MODEM_LONGRANGE4 */
+#define _MODEM_LONGRANGE4_LRCHPWRTH9_SHIFT 0 /**< Shift value for MODEM_LRCHPWRTH9 */
+#define _MODEM_LONGRANGE4_LRCHPWRTH9_MASK 0xFFUL /**< Bit mask for MODEM_LRCHPWRTH9 */
+#define _MODEM_LONGRANGE4_LRCHPWRTH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE4 */
+#define MODEM_LONGRANGE4_LRCHPWRTH9_DEFAULT (_MODEM_LONGRANGE4_LRCHPWRTH9_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_LONGRANGE4 */
+#define _MODEM_LONGRANGE4_LRCHPWRTH10_SHIFT 8 /**< Shift value for MODEM_LRCHPWRTH10 */
+#define _MODEM_LONGRANGE4_LRCHPWRTH10_MASK 0xFF00UL /**< Bit mask for MODEM_LRCHPWRTH10 */
+#define _MODEM_LONGRANGE4_LRCHPWRTH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE4 */
+#define MODEM_LONGRANGE4_LRCHPWRTH10_DEFAULT (_MODEM_LONGRANGE4_LRCHPWRTH10_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_LONGRANGE4 */
+#define _MODEM_LONGRANGE4_LRCHPWRSH1_SHIFT 16 /**< Shift value for MODEM_LRCHPWRSH1 */
+#define _MODEM_LONGRANGE4_LRCHPWRSH1_MASK 0xF0000UL /**< Bit mask for MODEM_LRCHPWRSH1 */
+#define _MODEM_LONGRANGE4_LRCHPWRSH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE4 */
+#define MODEM_LONGRANGE4_LRCHPWRSH1_DEFAULT (_MODEM_LONGRANGE4_LRCHPWRSH1_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_LONGRANGE4 */
+#define _MODEM_LONGRANGE4_LRCHPWRSH2_SHIFT 20 /**< Shift value for MODEM_LRCHPWRSH2 */
+#define _MODEM_LONGRANGE4_LRCHPWRSH2_MASK 0xF00000UL /**< Bit mask for MODEM_LRCHPWRSH2 */
+#define _MODEM_LONGRANGE4_LRCHPWRSH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE4 */
+#define MODEM_LONGRANGE4_LRCHPWRSH2_DEFAULT (_MODEM_LONGRANGE4_LRCHPWRSH2_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_LONGRANGE4 */
+#define _MODEM_LONGRANGE4_LRCHPWRSH3_SHIFT 24 /**< Shift value for MODEM_LRCHPWRSH3 */
+#define _MODEM_LONGRANGE4_LRCHPWRSH3_MASK 0xF000000UL /**< Bit mask for MODEM_LRCHPWRSH3 */
+#define _MODEM_LONGRANGE4_LRCHPWRSH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE4 */
+#define MODEM_LONGRANGE4_LRCHPWRSH3_DEFAULT (_MODEM_LONGRANGE4_LRCHPWRSH3_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_LONGRANGE4 */
+#define _MODEM_LONGRANGE4_LRCHPWRSH4_SHIFT 28 /**< Shift value for MODEM_LRCHPWRSH4 */
+#define _MODEM_LONGRANGE4_LRCHPWRSH4_MASK 0xF0000000UL /**< Bit mask for MODEM_LRCHPWRSH4 */
+#define _MODEM_LONGRANGE4_LRCHPWRSH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE4 */
+#define MODEM_LONGRANGE4_LRCHPWRSH4_DEFAULT (_MODEM_LONGRANGE4_LRCHPWRSH4_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_LONGRANGE4 */
+
+/* Bit fields for MODEM LONGRANGE5 */
+#define _MODEM_LONGRANGE5_RESETVALUE 0x00000000UL /**< Default value for MODEM_LONGRANGE5 */
+#define _MODEM_LONGRANGE5_MASK 0x0FFFFFFFUL /**< Mask for MODEM_LONGRANGE5 */
+#define _MODEM_LONGRANGE5_LRCHPWRSH5_SHIFT 0 /**< Shift value for MODEM_LRCHPWRSH5 */
+#define _MODEM_LONGRANGE5_LRCHPWRSH5_MASK 0xFUL /**< Bit mask for MODEM_LRCHPWRSH5 */
+#define _MODEM_LONGRANGE5_LRCHPWRSH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE5 */
+#define MODEM_LONGRANGE5_LRCHPWRSH5_DEFAULT (_MODEM_LONGRANGE5_LRCHPWRSH5_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_LONGRANGE5 */
+#define _MODEM_LONGRANGE5_LRCHPWRSH6_SHIFT 4 /**< Shift value for MODEM_LRCHPWRSH6 */
+#define _MODEM_LONGRANGE5_LRCHPWRSH6_MASK 0xF0UL /**< Bit mask for MODEM_LRCHPWRSH6 */
+#define _MODEM_LONGRANGE5_LRCHPWRSH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE5 */
+#define MODEM_LONGRANGE5_LRCHPWRSH6_DEFAULT (_MODEM_LONGRANGE5_LRCHPWRSH6_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_LONGRANGE5 */
+#define _MODEM_LONGRANGE5_LRCHPWRSH7_SHIFT 8 /**< Shift value for MODEM_LRCHPWRSH7 */
+#define _MODEM_LONGRANGE5_LRCHPWRSH7_MASK 0xF00UL /**< Bit mask for MODEM_LRCHPWRSH7 */
+#define _MODEM_LONGRANGE5_LRCHPWRSH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE5 */
+#define MODEM_LONGRANGE5_LRCHPWRSH7_DEFAULT (_MODEM_LONGRANGE5_LRCHPWRSH7_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_LONGRANGE5 */
+#define _MODEM_LONGRANGE5_LRCHPWRSH8_SHIFT 12 /**< Shift value for MODEM_LRCHPWRSH8 */
+#define _MODEM_LONGRANGE5_LRCHPWRSH8_MASK 0xF000UL /**< Bit mask for MODEM_LRCHPWRSH8 */
+#define _MODEM_LONGRANGE5_LRCHPWRSH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE5 */
+#define MODEM_LONGRANGE5_LRCHPWRSH8_DEFAULT (_MODEM_LONGRANGE5_LRCHPWRSH8_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_LONGRANGE5 */
+#define _MODEM_LONGRANGE5_LRCHPWRSH9_SHIFT 16 /**< Shift value for MODEM_LRCHPWRSH9 */
+#define _MODEM_LONGRANGE5_LRCHPWRSH9_MASK 0xF0000UL /**< Bit mask for MODEM_LRCHPWRSH9 */
+#define _MODEM_LONGRANGE5_LRCHPWRSH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE5 */
+#define MODEM_LONGRANGE5_LRCHPWRSH9_DEFAULT (_MODEM_LONGRANGE5_LRCHPWRSH9_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_LONGRANGE5 */
+#define _MODEM_LONGRANGE5_LRCHPWRSH10_SHIFT 20 /**< Shift value for MODEM_LRCHPWRSH10 */
+#define _MODEM_LONGRANGE5_LRCHPWRSH10_MASK 0xF00000UL /**< Bit mask for MODEM_LRCHPWRSH10 */
+#define _MODEM_LONGRANGE5_LRCHPWRSH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE5 */
+#define MODEM_LONGRANGE5_LRCHPWRSH10_DEFAULT (_MODEM_LONGRANGE5_LRCHPWRSH10_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_LONGRANGE5 */
+#define _MODEM_LONGRANGE5_LRCHPWRSH11_SHIFT 24 /**< Shift value for MODEM_LRCHPWRSH11 */
+#define _MODEM_LONGRANGE5_LRCHPWRSH11_MASK 0xF000000UL /**< Bit mask for MODEM_LRCHPWRSH11 */
+#define _MODEM_LONGRANGE5_LRCHPWRSH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE5 */
+#define MODEM_LONGRANGE5_LRCHPWRSH11_DEFAULT (_MODEM_LONGRANGE5_LRCHPWRSH11_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_LONGRANGE5 */
+
+/* Bit fields for MODEM LONGRANGE6 */
+#define _MODEM_LONGRANGE6_RESETVALUE 0x00000000UL /**< Default value for MODEM_LONGRANGE6 */
+#define _MODEM_LONGRANGE6_MASK 0xFFF7FFFFUL /**< Mask for MODEM_LONGRANGE6 */
+#define _MODEM_LONGRANGE6_LRCHPWRSPIKETH_SHIFT 0 /**< Shift value for MODEM_LRCHPWRSPIKETH */
+#define _MODEM_LONGRANGE6_LRCHPWRSPIKETH_MASK 0xFFUL /**< Bit mask for MODEM_LRCHPWRSPIKETH */
+#define _MODEM_LONGRANGE6_LRCHPWRSPIKETH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE6 */
+#define MODEM_LONGRANGE6_LRCHPWRSPIKETH_DEFAULT (_MODEM_LONGRANGE6_LRCHPWRSPIKETH_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_LONGRANGE6 */
+#define _MODEM_LONGRANGE6_LRSPIKETHD_SHIFT 8 /**< Shift value for MODEM_LRSPIKETHD */
+#define _MODEM_LONGRANGE6_LRSPIKETHD_MASK 0x7FF00UL /**< Bit mask for MODEM_LRSPIKETHD */
+#define _MODEM_LONGRANGE6_LRSPIKETHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE6 */
+#define MODEM_LONGRANGE6_LRSPIKETHD_DEFAULT (_MODEM_LONGRANGE6_LRSPIKETHD_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_LONGRANGE6 */
+#define _MODEM_LONGRANGE6_LRCHPWRTH11_SHIFT 20 /**< Shift value for MODEM_LRCHPWRTH11 */
+#define _MODEM_LONGRANGE6_LRCHPWRTH11_MASK 0xFF00000UL /**< Bit mask for MODEM_LRCHPWRTH11 */
+#define _MODEM_LONGRANGE6_LRCHPWRTH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE6 */
+#define MODEM_LONGRANGE6_LRCHPWRTH11_DEFAULT (_MODEM_LONGRANGE6_LRCHPWRTH11_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_LONGRANGE6 */
+#define _MODEM_LONGRANGE6_LRCHPWRSH12_SHIFT 28 /**< Shift value for MODEM_LRCHPWRSH12 */
+#define _MODEM_LONGRANGE6_LRCHPWRSH12_MASK 0xF0000000UL /**< Bit mask for MODEM_LRCHPWRSH12 */
+#define _MODEM_LONGRANGE6_LRCHPWRSH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LONGRANGE6 */
+#define MODEM_LONGRANGE6_LRCHPWRSH12_DEFAULT (_MODEM_LONGRANGE6_LRCHPWRSH12_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_LONGRANGE6 */
+
+/* Bit fields for MODEM LRFRC */
+#define _MODEM_LRFRC_RESETVALUE 0x00000101UL /**< Default value for MODEM_LRFRC */
+#define _MODEM_LRFRC_MASK 0x000001FFUL /**< Mask for MODEM_LRFRC */
+#define _MODEM_LRFRC_CI500_SHIFT 0 /**< Shift value for MODEM_CI500 */
+#define _MODEM_LRFRC_CI500_MASK 0x3UL /**< Bit mask for MODEM_CI500 */
+#define _MODEM_LRFRC_CI500_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_LRFRC */
+#define MODEM_LRFRC_CI500_DEFAULT (_MODEM_LRFRC_CI500_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_LRFRC */
+#define _MODEM_LRFRC_FRCACKTIMETHD_SHIFT 2 /**< Shift value for MODEM_FRCACKTIMETHD */
+#define _MODEM_LRFRC_FRCACKTIMETHD_MASK 0xFCUL /**< Bit mask for MODEM_FRCACKTIMETHD */
+#define _MODEM_LRFRC_FRCACKTIMETHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_LRFRC */
+#define MODEM_LRFRC_FRCACKTIMETHD_DEFAULT (_MODEM_LRFRC_FRCACKTIMETHD_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_LRFRC */
+#define MODEM_LRFRC_LRCORRMODE (0x1UL << 8) /**< LR Correlator operation Mode */
+#define _MODEM_LRFRC_LRCORRMODE_SHIFT 8 /**< Shift value for MODEM_LRCORRMODE */
+#define _MODEM_LRFRC_LRCORRMODE_MASK 0x100UL /**< Bit mask for MODEM_LRCORRMODE */
+#define _MODEM_LRFRC_LRCORRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_LRFRC */
+#define MODEM_LRFRC_LRCORRMODE_DEFAULT (_MODEM_LRFRC_LRCORRMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_LRFRC */
+
+/* Bit fields for MODEM COH0 */
+#define _MODEM_COH0_RESETVALUE 0x00000000UL /**< Default value for MODEM_COH0 */
+#define _MODEM_COH0_MASK 0xFFFFFFFFUL /**< Mask for MODEM_COH0 */
+#define MODEM_COH0_COHDYNAMICBBSSEN (0x1UL << 0) /**< Dynamic BBSS enable bit */
+#define _MODEM_COH0_COHDYNAMICBBSSEN_SHIFT 0 /**< Shift value for MODEM_COHDYNAMICBBSSEN */
+#define _MODEM_COH0_COHDYNAMICBBSSEN_MASK 0x1UL /**< Bit mask for MODEM_COHDYNAMICBBSSEN */
+#define _MODEM_COH0_COHDYNAMICBBSSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH0 */
+#define MODEM_COH0_COHDYNAMICBBSSEN_DEFAULT (_MODEM_COH0_COHDYNAMICBBSSEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_COH0 */
+#define MODEM_COH0_COHDYNAMICSYNCTHRESH (0x1UL << 1) /**< Dynamic syncword threshold enable bit */
+#define _MODEM_COH0_COHDYNAMICSYNCTHRESH_SHIFT 1 /**< Shift value for MODEM_COHDYNAMICSYNCTHRESH */
+#define _MODEM_COH0_COHDYNAMICSYNCTHRESH_MASK 0x2UL /**< Bit mask for MODEM_COHDYNAMICSYNCTHRESH */
+#define _MODEM_COH0_COHDYNAMICSYNCTHRESH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH0 */
+#define MODEM_COH0_COHDYNAMICSYNCTHRESH_DEFAULT (_MODEM_COH0_COHDYNAMICSYNCTHRESH_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_COH0 */
+#define MODEM_COH0_COHDYNAMICPRETHRESH (0x1UL << 2) /**< Dynamic preamble threshold enable bit */
+#define _MODEM_COH0_COHDYNAMICPRETHRESH_SHIFT 2 /**< Shift value for MODEM_COHDYNAMICPRETHRESH */
+#define _MODEM_COH0_COHDYNAMICPRETHRESH_MASK 0x4UL /**< Bit mask for MODEM_COHDYNAMICPRETHRESH */
+#define _MODEM_COH0_COHDYNAMICPRETHRESH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH0 */
+#define MODEM_COH0_COHDYNAMICPRETHRESH_DEFAULT (_MODEM_COH0_COHDYNAMICPRETHRESH_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_COH0 */
+#define MODEM_COH0_COHCHPWRLOCK (0x1UL << 3) /**< Channel power lock */
+#define _MODEM_COH0_COHCHPWRLOCK_SHIFT 3 /**< Shift value for MODEM_COHCHPWRLOCK */
+#define _MODEM_COH0_COHCHPWRLOCK_MASK 0x8UL /**< Bit mask for MODEM_COHCHPWRLOCK */
+#define _MODEM_COH0_COHCHPWRLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH0 */
+#define _MODEM_COH0_COHCHPWRLOCK_TIMDET 0x00000000UL /**< Mode TIMDET for MODEM_COH0 */
+#define _MODEM_COH0_COHCHPWRLOCK_DSADET 0x00000001UL /**< Mode DSADET for MODEM_COH0 */
+#define MODEM_COH0_COHCHPWRLOCK_DEFAULT (_MODEM_COH0_COHCHPWRLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_COH0 */
+#define MODEM_COH0_COHCHPWRLOCK_TIMDET (_MODEM_COH0_COHCHPWRLOCK_TIMDET << 3) /**< Shifted mode TIMDET for MODEM_COH0 */
+#define MODEM_COH0_COHCHPWRLOCK_DSADET (_MODEM_COH0_COHCHPWRLOCK_DSADET << 3) /**< Shifted mode DSADET for MODEM_COH0 */
+#define MODEM_COH0_COHCHPWRRESTART (0x1UL << 4) /**< Channel power restart */
+#define _MODEM_COH0_COHCHPWRRESTART_SHIFT 4 /**< Shift value for MODEM_COHCHPWRRESTART */
+#define _MODEM_COH0_COHCHPWRRESTART_MASK 0x10UL /**< Bit mask for MODEM_COHCHPWRRESTART */
+#define _MODEM_COH0_COHCHPWRRESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH0 */
+#define MODEM_COH0_COHCHPWRRESTART_DEFAULT (_MODEM_COH0_COHCHPWRRESTART_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_COH0 */
+#define _MODEM_COH0_COHDYNAMICPRETHRESHSEL_SHIFT 5 /**< Shift value for MODEM_COHDYNAMICPRETHRESHSEL*/
+#define _MODEM_COH0_COHDYNAMICPRETHRESHSEL_MASK 0xE0UL /**< Bit mask for MODEM_COHDYNAMICPRETHRESHSEL */
+#define _MODEM_COH0_COHDYNAMICPRETHRESHSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH0 */
+#define _MODEM_COH0_COHDYNAMICPRETHRESHSEL_SEL0 0x00000000UL /**< Mode SEL0 for MODEM_COH0 */
+#define _MODEM_COH0_COHDYNAMICPRETHRESHSEL_SEL1 0x00000001UL /**< Mode SEL1 for MODEM_COH0 */
+#define _MODEM_COH0_COHDYNAMICPRETHRESHSEL_SEL2 0x00000002UL /**< Mode SEL2 for MODEM_COH0 */
+#define _MODEM_COH0_COHDYNAMICPRETHRESHSEL_SEL3 0x00000003UL /**< Mode SEL3 for MODEM_COH0 */
+#define _MODEM_COH0_COHDYNAMICPRETHRESHSEL_SEL4 0x00000004UL /**< Mode SEL4 for MODEM_COH0 */
+#define MODEM_COH0_COHDYNAMICPRETHRESHSEL_DEFAULT (_MODEM_COH0_COHDYNAMICPRETHRESHSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_COH0 */
+#define MODEM_COH0_COHDYNAMICPRETHRESHSEL_SEL0 (_MODEM_COH0_COHDYNAMICPRETHRESHSEL_SEL0 << 5) /**< Shifted mode SEL0 for MODEM_COH0 */
+#define MODEM_COH0_COHDYNAMICPRETHRESHSEL_SEL1 (_MODEM_COH0_COHDYNAMICPRETHRESHSEL_SEL1 << 5) /**< Shifted mode SEL1 for MODEM_COH0 */
+#define MODEM_COH0_COHDYNAMICPRETHRESHSEL_SEL2 (_MODEM_COH0_COHDYNAMICPRETHRESHSEL_SEL2 << 5) /**< Shifted mode SEL2 for MODEM_COH0 */
+#define MODEM_COH0_COHDYNAMICPRETHRESHSEL_SEL3 (_MODEM_COH0_COHDYNAMICPRETHRESHSEL_SEL3 << 5) /**< Shifted mode SEL3 for MODEM_COH0 */
+#define MODEM_COH0_COHDYNAMICPRETHRESHSEL_SEL4 (_MODEM_COH0_COHDYNAMICPRETHRESHSEL_SEL4 << 5) /**< Shifted mode SEL4 for MODEM_COH0 */
+#define _MODEM_COH0_COHCHPWRTH0_SHIFT 8 /**< Shift value for MODEM_COHCHPWRTH0 */
+#define _MODEM_COH0_COHCHPWRTH0_MASK 0xFF00UL /**< Bit mask for MODEM_COHCHPWRTH0 */
+#define _MODEM_COH0_COHCHPWRTH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH0 */
+#define MODEM_COH0_COHCHPWRTH0_DEFAULT (_MODEM_COH0_COHCHPWRTH0_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_COH0 */
+#define _MODEM_COH0_COHCHPWRTH1_SHIFT 16 /**< Shift value for MODEM_COHCHPWRTH1 */
+#define _MODEM_COH0_COHCHPWRTH1_MASK 0xFF0000UL /**< Bit mask for MODEM_COHCHPWRTH1 */
+#define _MODEM_COH0_COHCHPWRTH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH0 */
+#define MODEM_COH0_COHCHPWRTH1_DEFAULT (_MODEM_COH0_COHCHPWRTH1_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_COH0 */
+#define _MODEM_COH0_COHCHPWRTH2_SHIFT 24 /**< Shift value for MODEM_COHCHPWRTH2 */
+#define _MODEM_COH0_COHCHPWRTH2_MASK 0xFF000000UL /**< Bit mask for MODEM_COHCHPWRTH2 */
+#define _MODEM_COH0_COHCHPWRTH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH0 */
+#define MODEM_COH0_COHCHPWRTH2_DEFAULT (_MODEM_COH0_COHCHPWRTH2_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_COH0 */
+
+/* Bit fields for MODEM COH1 */
+#define _MODEM_COH1_RESETVALUE 0x00000000UL /**< Default value for MODEM_COH1 */
+#define _MODEM_COH1_MASK 0xFFFFFFFFUL /**< Mask for MODEM_COH1 */
+#define _MODEM_COH1_SYNCTHRESH0_SHIFT 0 /**< Shift value for MODEM_SYNCTHRESH0 */
+#define _MODEM_COH1_SYNCTHRESH0_MASK 0xFFUL /**< Bit mask for MODEM_SYNCTHRESH0 */
+#define _MODEM_COH1_SYNCTHRESH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH1 */
+#define MODEM_COH1_SYNCTHRESH0_DEFAULT (_MODEM_COH1_SYNCTHRESH0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_COH1 */
+#define _MODEM_COH1_SYNCTHRESH1_SHIFT 8 /**< Shift value for MODEM_SYNCTHRESH1 */
+#define _MODEM_COH1_SYNCTHRESH1_MASK 0xFF00UL /**< Bit mask for MODEM_SYNCTHRESH1 */
+#define _MODEM_COH1_SYNCTHRESH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH1 */
+#define MODEM_COH1_SYNCTHRESH1_DEFAULT (_MODEM_COH1_SYNCTHRESH1_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_COH1 */
+#define _MODEM_COH1_SYNCTHRESH2_SHIFT 16 /**< Shift value for MODEM_SYNCTHRESH2 */
+#define _MODEM_COH1_SYNCTHRESH2_MASK 0xFF0000UL /**< Bit mask for MODEM_SYNCTHRESH2 */
+#define _MODEM_COH1_SYNCTHRESH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH1 */
+#define MODEM_COH1_SYNCTHRESH2_DEFAULT (_MODEM_COH1_SYNCTHRESH2_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_COH1 */
+#define _MODEM_COH1_SYNCTHRESH3_SHIFT 24 /**< Shift value for MODEM_SYNCTHRESH3 */
+#define _MODEM_COH1_SYNCTHRESH3_MASK 0xFF000000UL /**< Bit mask for MODEM_SYNCTHRESH3 */
+#define _MODEM_COH1_SYNCTHRESH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH1 */
+#define MODEM_COH1_SYNCTHRESH3_DEFAULT (_MODEM_COH1_SYNCTHRESH3_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_COH1 */
+
+/* Bit fields for MODEM COH2 */
+#define _MODEM_COH2_RESETVALUE 0x00000000UL /**< Default value for MODEM_COH2 */
+#define _MODEM_COH2_MASK 0xFFFFFFFFUL /**< Mask for MODEM_COH2 */
+#define _MODEM_COH2_SYNCTHRESHDELTA0_SHIFT 0 /**< Shift value for MODEM_SYNCTHRESHDELTA0 */
+#define _MODEM_COH2_SYNCTHRESHDELTA0_MASK 0xFUL /**< Bit mask for MODEM_SYNCTHRESHDELTA0 */
+#define _MODEM_COH2_SYNCTHRESHDELTA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH2 */
+#define MODEM_COH2_SYNCTHRESHDELTA0_DEFAULT (_MODEM_COH2_SYNCTHRESHDELTA0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_COH2 */
+#define _MODEM_COH2_SYNCTHRESHDELTA1_SHIFT 4 /**< Shift value for MODEM_SYNCTHRESHDELTA1 */
+#define _MODEM_COH2_SYNCTHRESHDELTA1_MASK 0xF0UL /**< Bit mask for MODEM_SYNCTHRESHDELTA1 */
+#define _MODEM_COH2_SYNCTHRESHDELTA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH2 */
+#define MODEM_COH2_SYNCTHRESHDELTA1_DEFAULT (_MODEM_COH2_SYNCTHRESHDELTA1_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_COH2 */
+#define _MODEM_COH2_SYNCTHRESHDELTA2_SHIFT 8 /**< Shift value for MODEM_SYNCTHRESHDELTA2 */
+#define _MODEM_COH2_SYNCTHRESHDELTA2_MASK 0xF00UL /**< Bit mask for MODEM_SYNCTHRESHDELTA2 */
+#define _MODEM_COH2_SYNCTHRESHDELTA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH2 */
+#define MODEM_COH2_SYNCTHRESHDELTA2_DEFAULT (_MODEM_COH2_SYNCTHRESHDELTA2_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_COH2 */
+#define _MODEM_COH2_SYNCTHRESHDELTA3_SHIFT 12 /**< Shift value for MODEM_SYNCTHRESHDELTA3 */
+#define _MODEM_COH2_SYNCTHRESHDELTA3_MASK 0xF000UL /**< Bit mask for MODEM_SYNCTHRESHDELTA3 */
+#define _MODEM_COH2_SYNCTHRESHDELTA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH2 */
+#define MODEM_COH2_SYNCTHRESHDELTA3_DEFAULT (_MODEM_COH2_SYNCTHRESHDELTA3_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_COH2 */
+#define _MODEM_COH2_DSAPEAKCHPWRTH_SHIFT 16 /**< Shift value for MODEM_DSAPEAKCHPWRTH */
+#define _MODEM_COH2_DSAPEAKCHPWRTH_MASK 0xFF0000UL /**< Bit mask for MODEM_DSAPEAKCHPWRTH */
+#define _MODEM_COH2_DSAPEAKCHPWRTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH2 */
+#define MODEM_COH2_DSAPEAKCHPWRTH_DEFAULT (_MODEM_COH2_DSAPEAKCHPWRTH_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_COH2 */
+#define _MODEM_COH2_FIXEDCDTHFORIIR_SHIFT 24 /**< Shift value for MODEM_FIXEDCDTHFORIIR */
+#define _MODEM_COH2_FIXEDCDTHFORIIR_MASK 0xFF000000UL /**< Bit mask for MODEM_FIXEDCDTHFORIIR */
+#define _MODEM_COH2_FIXEDCDTHFORIIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH2 */
+#define MODEM_COH2_FIXEDCDTHFORIIR_DEFAULT (_MODEM_COH2_FIXEDCDTHFORIIR_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_COH2 */
+
+/* Bit fields for MODEM COH3 */
+#define _MODEM_COH3_RESETVALUE 0x00000000UL /**< Default value for MODEM_COH3 */
+#define _MODEM_COH3_MASK 0x3FFFFFFFUL /**< Mask for MODEM_COH3 */
+#define MODEM_COH3_COHDSAEN (0x1UL << 0) /**< DSA enable bit */
+#define _MODEM_COH3_COHDSAEN_SHIFT 0 /**< Shift value for MODEM_COHDSAEN */
+#define _MODEM_COH3_COHDSAEN_MASK 0x1UL /**< Bit mask for MODEM_COHDSAEN */
+#define _MODEM_COH3_COHDSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH3 */
+#define MODEM_COH3_COHDSAEN_DEFAULT (_MODEM_COH3_COHDSAEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_COH3 */
+#define _MODEM_COH3_COHDSAADDWNDSIZE_SHIFT 1 /**< Shift value for MODEM_COHDSAADDWNDSIZE */
+#define _MODEM_COH3_COHDSAADDWNDSIZE_MASK 0x7FEUL /**< Bit mask for MODEM_COHDSAADDWNDSIZE */
+#define _MODEM_COH3_COHDSAADDWNDSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH3 */
+#define MODEM_COH3_COHDSAADDWNDSIZE_DEFAULT (_MODEM_COH3_COHDSAADDWNDSIZE_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_COH3 */
+#define _MODEM_COH3_CDSS_SHIFT 11 /**< Shift value for MODEM_CDSS */
+#define _MODEM_COH3_CDSS_MASK 0x3800UL /**< Bit mask for MODEM_CDSS */
+#define _MODEM_COH3_CDSS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH3 */
+#define MODEM_COH3_CDSS_DEFAULT (_MODEM_COH3_CDSS_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_COH3 */
+#define MODEM_COH3_DSAPEAKCHKEN (0x1UL << 14) /**< DSA Peak Checking Enable */
+#define _MODEM_COH3_DSAPEAKCHKEN_SHIFT 14 /**< Shift value for MODEM_DSAPEAKCHKEN */
+#define _MODEM_COH3_DSAPEAKCHKEN_MASK 0x4000UL /**< Bit mask for MODEM_DSAPEAKCHKEN */
+#define _MODEM_COH3_DSAPEAKCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH3 */
+#define MODEM_COH3_DSAPEAKCHKEN_DEFAULT (_MODEM_COH3_DSAPEAKCHKEN_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_COH3 */
+#define _MODEM_COH3_DSAPEAKINDLEN_SHIFT 15 /**< Shift value for MODEM_DSAPEAKINDLEN */
+#define _MODEM_COH3_DSAPEAKINDLEN_MASK 0x38000UL /**< Bit mask for MODEM_DSAPEAKINDLEN */
+#define _MODEM_COH3_DSAPEAKINDLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH3 */
+#define MODEM_COH3_DSAPEAKINDLEN_DEFAULT (_MODEM_COH3_DSAPEAKINDLEN_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_COH3 */
+#define MODEM_COH3_DSAPEAKCHPWREN (0x1UL << 18) /**< DSA Peak Check channel power enable */
+#define _MODEM_COH3_DSAPEAKCHPWREN_SHIFT 18 /**< Shift value for MODEM_DSAPEAKCHPWREN */
+#define _MODEM_COH3_DSAPEAKCHPWREN_MASK 0x40000UL /**< Bit mask for MODEM_DSAPEAKCHPWREN */
+#define _MODEM_COH3_DSAPEAKCHPWREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH3 */
+#define MODEM_COH3_DSAPEAKCHPWREN_DEFAULT (_MODEM_COH3_DSAPEAKCHPWREN_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_COH3 */
+#define MODEM_COH3_LOGICBASEDCOHDEMODGATE (0x1UL << 19) /**< Logic Based clock gate */
+#define _MODEM_COH3_LOGICBASEDCOHDEMODGATE_SHIFT 19 /**< Shift value for MODEM_LOGICBASEDCOHDEMODGATE*/
+#define _MODEM_COH3_LOGICBASEDCOHDEMODGATE_MASK 0x80000UL /**< Bit mask for MODEM_LOGICBASEDCOHDEMODGATE */
+#define _MODEM_COH3_LOGICBASEDCOHDEMODGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH3 */
+#define MODEM_COH3_LOGICBASEDCOHDEMODGATE_DEFAULT (_MODEM_COH3_LOGICBASEDCOHDEMODGATE_DEFAULT << 19) /**< Shifted mode DEFAULT for MODEM_COH3 */
+#define _MODEM_COH3_DYNIIRCOEFOPTION_SHIFT 20 /**< Shift value for MODEM_DYNIIRCOEFOPTION */
+#define _MODEM_COH3_DYNIIRCOEFOPTION_MASK 0x300000UL /**< Bit mask for MODEM_DYNIIRCOEFOPTION */
+#define _MODEM_COH3_DYNIIRCOEFOPTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH3 */
+#define MODEM_COH3_DYNIIRCOEFOPTION_DEFAULT (_MODEM_COH3_DYNIIRCOEFOPTION_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_COH3 */
+#define MODEM_COH3_ONEPEAKQUALEN (0x1UL << 22) /**< One Peak */
+#define _MODEM_COH3_ONEPEAKQUALEN_SHIFT 22 /**< Shift value for MODEM_ONEPEAKQUALEN */
+#define _MODEM_COH3_ONEPEAKQUALEN_MASK 0x400000UL /**< Bit mask for MODEM_ONEPEAKQUALEN */
+#define _MODEM_COH3_ONEPEAKQUALEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH3 */
+#define MODEM_COH3_ONEPEAKQUALEN_DEFAULT (_MODEM_COH3_ONEPEAKQUALEN_DEFAULT << 22) /**< Shifted mode DEFAULT for MODEM_COH3 */
+#define _MODEM_COH3_PEAKCHKTIMOUT_SHIFT 23 /**< Shift value for MODEM_PEAKCHKTIMOUT */
+#define _MODEM_COH3_PEAKCHKTIMOUT_MASK 0xF800000UL /**< Bit mask for MODEM_PEAKCHKTIMOUT */
+#define _MODEM_COH3_PEAKCHKTIMOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH3 */
+#define MODEM_COH3_PEAKCHKTIMOUT_DEFAULT (_MODEM_COH3_PEAKCHKTIMOUT_DEFAULT << 23) /**< Shifted mode DEFAULT for MODEM_COH3 */
+#define MODEM_COH3_COHDSADETDIS (0x1UL << 28) /**< DSA Detection Disable */
+#define _MODEM_COH3_COHDSADETDIS_SHIFT 28 /**< Shift value for MODEM_COHDSADETDIS */
+#define _MODEM_COH3_COHDSADETDIS_MASK 0x10000000UL /**< Bit mask for MODEM_COHDSADETDIS */
+#define _MODEM_COH3_COHDSADETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH3 */
+#define MODEM_COH3_COHDSADETDIS_DEFAULT (_MODEM_COH3_COHDSADETDIS_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_COH3 */
+#define MODEM_COH3_COHDSACMPLX (0x1UL << 29) /**< DSA Complex */
+#define _MODEM_COH3_COHDSACMPLX_SHIFT 29 /**< Shift value for MODEM_COHDSACMPLX */
+#define _MODEM_COH3_COHDSACMPLX_MASK 0x20000000UL /**< Bit mask for MODEM_COHDSACMPLX */
+#define _MODEM_COH3_COHDSACMPLX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COH3 */
+#define MODEM_COH3_COHDSACMPLX_DEFAULT (_MODEM_COH3_COHDSACMPLX_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_COH3 */
+
+/* Bit fields for MODEM CMD */
+#define _MODEM_CMD_RESETVALUE 0x00000000UL /**< Default value for MODEM_CMD */
+#define _MODEM_CMD_MASK 0x0000003BUL /**< Mask for MODEM_CMD */
+#define MODEM_CMD_PRESTOP (0x1UL << 0) /**< Preamble stop */
+#define _MODEM_CMD_PRESTOP_SHIFT 0 /**< Shift value for MODEM_PRESTOP */
+#define _MODEM_CMD_PRESTOP_MASK 0x1UL /**< Bit mask for MODEM_PRESTOP */
+#define _MODEM_CMD_PRESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CMD */
+#define MODEM_CMD_PRESTOP_DEFAULT (_MODEM_CMD_PRESTOP_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CMD */
+#define MODEM_CMD_CHPWRACCUCLR (0x1UL << 1) /**< Channel Power Accumulation Clear */
+#define _MODEM_CMD_CHPWRACCUCLR_SHIFT 1 /**< Shift value for MODEM_CHPWRACCUCLR */
+#define _MODEM_CMD_CHPWRACCUCLR_MASK 0x2UL /**< Bit mask for MODEM_CHPWRACCUCLR */
+#define _MODEM_CMD_CHPWRACCUCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CMD */
+#define MODEM_CMD_CHPWRACCUCLR_DEFAULT (_MODEM_CMD_CHPWRACCUCLR_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_CMD */
+#define MODEM_CMD_AFCTXLOCK (0x1UL << 3) /**< Lock AFC TX compensation */
+#define _MODEM_CMD_AFCTXLOCK_SHIFT 3 /**< Shift value for MODEM_AFCTXLOCK */
+#define _MODEM_CMD_AFCTXLOCK_MASK 0x8UL /**< Bit mask for MODEM_AFCTXLOCK */
+#define _MODEM_CMD_AFCTXLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CMD */
+#define MODEM_CMD_AFCTXLOCK_DEFAULT (_MODEM_CMD_AFCTXLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_CMD */
+#define MODEM_CMD_AFCTXCLEAR (0x1UL << 4) /**< Clear AFC TX compensation. */
+#define _MODEM_CMD_AFCTXCLEAR_SHIFT 4 /**< Shift value for MODEM_AFCTXCLEAR */
+#define _MODEM_CMD_AFCTXCLEAR_MASK 0x10UL /**< Bit mask for MODEM_AFCTXCLEAR */
+#define _MODEM_CMD_AFCTXCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CMD */
+#define MODEM_CMD_AFCTXCLEAR_DEFAULT (_MODEM_CMD_AFCTXCLEAR_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_CMD */
+#define MODEM_CMD_AFCRXCLEAR (0x1UL << 5) /**< Clear AFC RX compensation. */
+#define _MODEM_CMD_AFCRXCLEAR_SHIFT 5 /**< Shift value for MODEM_AFCRXCLEAR */
+#define _MODEM_CMD_AFCRXCLEAR_MASK 0x20UL /**< Bit mask for MODEM_AFCRXCLEAR */
+#define _MODEM_CMD_AFCRXCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CMD */
+#define MODEM_CMD_AFCRXCLEAR_DEFAULT (_MODEM_CMD_AFCRXCLEAR_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_CMD */
+
+/* Bit fields for MODEM SYNCPROPERTIES */
+#define _MODEM_SYNCPROPERTIES_RESETVALUE 0x00000000UL /**< Default value for MODEM_SYNCPROPERTIES */
+#define _MODEM_SYNCPROPERTIES_MASK 0x0001FF00UL /**< Mask for MODEM_SYNCPROPERTIES */
+#define MODEM_SYNCPROPERTIES_STATICSYNCTHRESHEN (0x1UL << 8) /**< Static Sync Threshold Enable */
+#define _MODEM_SYNCPROPERTIES_STATICSYNCTHRESHEN_SHIFT 8 /**< Shift value for MODEM_STATICSYNCTHRESHEN */
+#define _MODEM_SYNCPROPERTIES_STATICSYNCTHRESHEN_MASK 0x100UL /**< Bit mask for MODEM_STATICSYNCTHRESHEN */
+#define _MODEM_SYNCPROPERTIES_STATICSYNCTHRESHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SYNCPROPERTIES */
+#define MODEM_SYNCPROPERTIES_STATICSYNCTHRESHEN_DEFAULT (_MODEM_SYNCPROPERTIES_STATICSYNCTHRESHEN_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_SYNCPROPERTIES*/
+#define _MODEM_SYNCPROPERTIES_STATICSYNCTHRESH_SHIFT 9 /**< Shift value for MODEM_STATICSYNCTHRESH */
+#define _MODEM_SYNCPROPERTIES_STATICSYNCTHRESH_MASK 0x1FE00UL /**< Bit mask for MODEM_STATICSYNCTHRESH */
+#define _MODEM_SYNCPROPERTIES_STATICSYNCTHRESH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SYNCPROPERTIES */
+#define MODEM_SYNCPROPERTIES_STATICSYNCTHRESH_DEFAULT (_MODEM_SYNCPROPERTIES_STATICSYNCTHRESH_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_SYNCPROPERTIES*/
+
+/* Bit fields for MODEM DIGIGAINCTRL */
+#define _MODEM_DIGIGAINCTRL_RESETVALUE 0x00000000UL /**< Default value for MODEM_DIGIGAINCTRL */
+#define _MODEM_DIGIGAINCTRL_MASK 0x000001FFUL /**< Mask for MODEM_DIGIGAINCTRL */
+#define MODEM_DIGIGAINCTRL_DIGIGAINEN (0x1UL << 0) /**< Digital Gain Enable */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINEN_SHIFT 0 /**< Shift value for MODEM_DIGIGAINEN */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINEN_MASK 0x1UL /**< Bit mask for MODEM_DIGIGAINEN */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DIGIGAINCTRL */
+#define MODEM_DIGIGAINCTRL_DIGIGAINEN_DEFAULT (_MODEM_DIGIGAINCTRL_DIGIGAINEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_DIGIGAINCTRL */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_SHIFT 1 /**< Shift value for MODEM_DIGIGAINSEL */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_MASK 0x3EUL /**< Bit mask for MODEM_DIGIGAINSEL */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DIGIGAINCTRL */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM3 0x00000000UL /**< Mode GAINM3 for MODEM_DIGIGAINCTRL */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM2P75 0x00000001UL /**< Mode GAINM2P75 for MODEM_DIGIGAINCTRL */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM2P5 0x00000002UL /**< Mode GAINM2P5 for MODEM_DIGIGAINCTRL */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM2P25 0x00000003UL /**< Mode GAINM2P25 for MODEM_DIGIGAINCTRL */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM2 0x00000004UL /**< Mode GAINM2 for MODEM_DIGIGAINCTRL */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM1P75 0x00000005UL /**< Mode GAINM1P75 for MODEM_DIGIGAINCTRL */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM1P5 0x00000006UL /**< Mode GAINM1P5 for MODEM_DIGIGAINCTRL */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM1P25 0x00000007UL /**< Mode GAINM1P25 for MODEM_DIGIGAINCTRL */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM1 0x00000008UL /**< Mode GAINM1 for MODEM_DIGIGAINCTRL */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM0P75 0x00000009UL /**< Mode GAINM0P75 for MODEM_DIGIGAINCTRL */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM0P5 0x0000000AUL /**< Mode GAINM0P5 for MODEM_DIGIGAINCTRL */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM0P25 0x0000000BUL /**< Mode GAINM0P25 for MODEM_DIGIGAINCTRL */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM0 0x0000000CUL /**< Mode GAINM0 for MODEM_DIGIGAINCTRL */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP0P25 0x0000000DUL /**< Mode GAINP0P25 for MODEM_DIGIGAINCTRL */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP0P5 0x0000000EUL /**< Mode GAINP0P5 for MODEM_DIGIGAINCTRL */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP0P75 0x0000000FUL /**< Mode GAINP0P75 for MODEM_DIGIGAINCTRL */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP1 0x00000010UL /**< Mode GAINP1 for MODEM_DIGIGAINCTRL */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP1P25 0x00000011UL /**< Mode GAINP1P25 for MODEM_DIGIGAINCTRL */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP1P5 0x00000012UL /**< Mode GAINP1P5 for MODEM_DIGIGAINCTRL */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP1P75 0x00000013UL /**< Mode GAINP1P75 for MODEM_DIGIGAINCTRL */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP2 0x00000014UL /**< Mode GAINP2 for MODEM_DIGIGAINCTRL */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP2P25 0x00000015UL /**< Mode GAINP2P25 for MODEM_DIGIGAINCTRL */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP2P5 0x00000016UL /**< Mode GAINP2P5 for MODEM_DIGIGAINCTRL */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP2P75 0x00000017UL /**< Mode GAINP2P75 for MODEM_DIGIGAINCTRL */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP3 0x00000018UL /**< Mode GAINP3 for MODEM_DIGIGAINCTRL */
+#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_DEFAULT (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_DIGIGAINCTRL */
+#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM3 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM3 << 1) /**< Shifted mode GAINM3 for MODEM_DIGIGAINCTRL */
+#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM2P75 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM2P75 << 1) /**< Shifted mode GAINM2P75 for MODEM_DIGIGAINCTRL*/
+#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM2P5 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM2P5 << 1) /**< Shifted mode GAINM2P5 for MODEM_DIGIGAINCTRL*/
+#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM2P25 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM2P25 << 1) /**< Shifted mode GAINM2P25 for MODEM_DIGIGAINCTRL*/
+#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM2 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM2 << 1) /**< Shifted mode GAINM2 for MODEM_DIGIGAINCTRL */
+#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM1P75 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM1P75 << 1) /**< Shifted mode GAINM1P75 for MODEM_DIGIGAINCTRL*/
+#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM1P5 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM1P5 << 1) /**< Shifted mode GAINM1P5 for MODEM_DIGIGAINCTRL*/
+#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM1P25 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM1P25 << 1) /**< Shifted mode GAINM1P25 for MODEM_DIGIGAINCTRL*/
+#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM1 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM1 << 1) /**< Shifted mode GAINM1 for MODEM_DIGIGAINCTRL */
+#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM0P75 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM0P75 << 1) /**< Shifted mode GAINM0P75 for MODEM_DIGIGAINCTRL*/
+#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM0P5 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM0P5 << 1) /**< Shifted mode GAINM0P5 for MODEM_DIGIGAINCTRL*/
+#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM0P25 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM0P25 << 1) /**< Shifted mode GAINM0P25 for MODEM_DIGIGAINCTRL*/
+#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM0 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINM0 << 1) /**< Shifted mode GAINM0 for MODEM_DIGIGAINCTRL */
+#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP0P25 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP0P25 << 1) /**< Shifted mode GAINP0P25 for MODEM_DIGIGAINCTRL*/
+#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP0P5 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP0P5 << 1) /**< Shifted mode GAINP0P5 for MODEM_DIGIGAINCTRL*/
+#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP0P75 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP0P75 << 1) /**< Shifted mode GAINP0P75 for MODEM_DIGIGAINCTRL*/
+#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP1 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP1 << 1) /**< Shifted mode GAINP1 for MODEM_DIGIGAINCTRL */
+#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP1P25 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP1P25 << 1) /**< Shifted mode GAINP1P25 for MODEM_DIGIGAINCTRL*/
+#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP1P5 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP1P5 << 1) /**< Shifted mode GAINP1P5 for MODEM_DIGIGAINCTRL*/
+#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP1P75 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP1P75 << 1) /**< Shifted mode GAINP1P75 for MODEM_DIGIGAINCTRL*/
+#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP2 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP2 << 1) /**< Shifted mode GAINP2 for MODEM_DIGIGAINCTRL */
+#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP2P25 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP2P25 << 1) /**< Shifted mode GAINP2P25 for MODEM_DIGIGAINCTRL*/
+#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP2P5 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP2P5 << 1) /**< Shifted mode GAINP2P5 for MODEM_DIGIGAINCTRL*/
+#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP2P75 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP2P75 << 1) /**< Shifted mode GAINP2P75 for MODEM_DIGIGAINCTRL*/
+#define MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP3 (_MODEM_DIGIGAINCTRL_DIGIGAINSEL_GAINP3 << 1) /**< Shifted mode GAINP3 for MODEM_DIGIGAINCTRL */
+#define MODEM_DIGIGAINCTRL_DIGIGAINDOUBLE (0x1UL << 6) /**< Digital Gain Doubled */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINDOUBLE_SHIFT 6 /**< Shift value for MODEM_DIGIGAINDOUBLE */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINDOUBLE_MASK 0x40UL /**< Bit mask for MODEM_DIGIGAINDOUBLE */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINDOUBLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DIGIGAINCTRL */
+#define MODEM_DIGIGAINCTRL_DIGIGAINDOUBLE_DEFAULT (_MODEM_DIGIGAINCTRL_DIGIGAINDOUBLE_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_DIGIGAINCTRL */
+#define MODEM_DIGIGAINCTRL_DIGIGAINHALF (0x1UL << 7) /**< Digital Gain Halved */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINHALF_SHIFT 7 /**< Shift value for MODEM_DIGIGAINHALF */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINHALF_MASK 0x80UL /**< Bit mask for MODEM_DIGIGAINHALF */
+#define _MODEM_DIGIGAINCTRL_DIGIGAINHALF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DIGIGAINCTRL */
+#define MODEM_DIGIGAINCTRL_DIGIGAINHALF_DEFAULT (_MODEM_DIGIGAINCTRL_DIGIGAINHALF_DEFAULT << 7) /**< Shifted mode DEFAULT for MODEM_DIGIGAINCTRL */
+#define MODEM_DIGIGAINCTRL_DEC0GAIN (0x1UL << 8) /**< DEC0 Gain Select */
+#define _MODEM_DIGIGAINCTRL_DEC0GAIN_SHIFT 8 /**< Shift value for MODEM_DEC0GAIN */
+#define _MODEM_DIGIGAINCTRL_DEC0GAIN_MASK 0x100UL /**< Bit mask for MODEM_DEC0GAIN */
+#define _MODEM_DIGIGAINCTRL_DEC0GAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_DIGIGAINCTRL */
+#define MODEM_DIGIGAINCTRL_DEC0GAIN_DEFAULT (_MODEM_DIGIGAINCTRL_DEC0GAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_DIGIGAINCTRL */
+
+/* Bit fields for MODEM PRSCTRL */
+#define _MODEM_PRSCTRL_RESETVALUE 0x00000000UL /**< Default value for MODEM_PRSCTRL */
+#define _MODEM_PRSCTRL_MASK 0x000FFFFFUL /**< Mask for MODEM_PRSCTRL */
+#define _MODEM_PRSCTRL_POSTPONESEL_SHIFT 0 /**< Shift value for MODEM_POSTPONESEL */
+#define _MODEM_PRSCTRL_POSTPONESEL_MASK 0x3UL /**< Bit mask for MODEM_POSTPONESEL */
+#define _MODEM_PRSCTRL_POSTPONESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRSCTRL */
+#define MODEM_PRSCTRL_POSTPONESEL_DEFAULT (_MODEM_PRSCTRL_POSTPONESEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_PRSCTRL */
+#define _MODEM_PRSCTRL_ADVANCESEL_SHIFT 2 /**< Shift value for MODEM_ADVANCESEL */
+#define _MODEM_PRSCTRL_ADVANCESEL_MASK 0xCUL /**< Bit mask for MODEM_ADVANCESEL */
+#define _MODEM_PRSCTRL_ADVANCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRSCTRL */
+#define MODEM_PRSCTRL_ADVANCESEL_DEFAULT (_MODEM_PRSCTRL_ADVANCESEL_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_PRSCTRL */
+#define _MODEM_PRSCTRL_NEWWNDSEL_SHIFT 4 /**< Shift value for MODEM_NEWWNDSEL */
+#define _MODEM_PRSCTRL_NEWWNDSEL_MASK 0x30UL /**< Bit mask for MODEM_NEWWNDSEL */
+#define _MODEM_PRSCTRL_NEWWNDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRSCTRL */
+#define MODEM_PRSCTRL_NEWWNDSEL_DEFAULT (_MODEM_PRSCTRL_NEWWNDSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_PRSCTRL */
+#define _MODEM_PRSCTRL_WEAKSEL_SHIFT 6 /**< Shift value for MODEM_WEAKSEL */
+#define _MODEM_PRSCTRL_WEAKSEL_MASK 0xC0UL /**< Bit mask for MODEM_WEAKSEL */
+#define _MODEM_PRSCTRL_WEAKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRSCTRL */
+#define MODEM_PRSCTRL_WEAKSEL_DEFAULT (_MODEM_PRSCTRL_WEAKSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_PRSCTRL */
+#define _MODEM_PRSCTRL_SYNCSENTSEL_SHIFT 8 /**< Shift value for MODEM_SYNCSENTSEL */
+#define _MODEM_PRSCTRL_SYNCSENTSEL_MASK 0x300UL /**< Bit mask for MODEM_SYNCSENTSEL */
+#define _MODEM_PRSCTRL_SYNCSENTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRSCTRL */
+#define MODEM_PRSCTRL_SYNCSENTSEL_DEFAULT (_MODEM_PRSCTRL_SYNCSENTSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_PRSCTRL */
+#define _MODEM_PRSCTRL_PRESENTSEL_SHIFT 10 /**< Shift value for MODEM_PRESENTSEL */
+#define _MODEM_PRSCTRL_PRESENTSEL_MASK 0xC00UL /**< Bit mask for MODEM_PRESENTSEL */
+#define _MODEM_PRSCTRL_PRESENTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRSCTRL */
+#define MODEM_PRSCTRL_PRESENTSEL_DEFAULT (_MODEM_PRSCTRL_PRESENTSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_PRSCTRL */
+#define _MODEM_PRSCTRL_LOWCORRSEL_SHIFT 12 /**< Shift value for MODEM_LOWCORRSEL */
+#define _MODEM_PRSCTRL_LOWCORRSEL_MASK 0x3000UL /**< Bit mask for MODEM_LOWCORRSEL */
+#define _MODEM_PRSCTRL_LOWCORRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRSCTRL */
+#define MODEM_PRSCTRL_LOWCORRSEL_DEFAULT (_MODEM_PRSCTRL_LOWCORRSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_PRSCTRL */
+#define _MODEM_PRSCTRL_ANT0SEL_SHIFT 14 /**< Shift value for MODEM_ANT0SEL */
+#define _MODEM_PRSCTRL_ANT0SEL_MASK 0xC000UL /**< Bit mask for MODEM_ANT0SEL */
+#define _MODEM_PRSCTRL_ANT0SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRSCTRL */
+#define MODEM_PRSCTRL_ANT0SEL_DEFAULT (_MODEM_PRSCTRL_ANT0SEL_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_PRSCTRL */
+#define _MODEM_PRSCTRL_ANT1SEL_SHIFT 16 /**< Shift value for MODEM_ANT1SEL */
+#define _MODEM_PRSCTRL_ANT1SEL_MASK 0x30000UL /**< Bit mask for MODEM_ANT1SEL */
+#define _MODEM_PRSCTRL_ANT1SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRSCTRL */
+#define MODEM_PRSCTRL_ANT1SEL_DEFAULT (_MODEM_PRSCTRL_ANT1SEL_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_PRSCTRL */
+#define _MODEM_PRSCTRL_IFADCCLKSEL_SHIFT 18 /**< Shift value for MODEM_IFADCCLKSEL */
+#define _MODEM_PRSCTRL_IFADCCLKSEL_MASK 0xC0000UL /**< Bit mask for MODEM_IFADCCLKSEL */
+#define _MODEM_PRSCTRL_IFADCCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PRSCTRL */
+#define MODEM_PRSCTRL_IFADCCLKSEL_DEFAULT (_MODEM_PRSCTRL_IFADCCLKSEL_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_PRSCTRL */
+
+/* Bit fields for MODEM REALTIMCFE */
+#define _MODEM_REALTIMCFE_RESETVALUE 0x001F81F4UL /**< Default value for MODEM_REALTIMCFE */
+#define _MODEM_REALTIMCFE_MASK 0xE03FFFFFUL /**< Mask for MODEM_REALTIMCFE */
+#define _MODEM_REALTIMCFE_MINCOSTTHD_SHIFT 0 /**< Shift value for MODEM_MINCOSTTHD */
+#define _MODEM_REALTIMCFE_MINCOSTTHD_MASK 0x3FFUL /**< Bit mask for MODEM_MINCOSTTHD */
+#define _MODEM_REALTIMCFE_MINCOSTTHD_DEFAULT 0x000001F4UL /**< Mode DEFAULT for MODEM_REALTIMCFE */
+#define MODEM_REALTIMCFE_MINCOSTTHD_DEFAULT (_MODEM_REALTIMCFE_MINCOSTTHD_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_REALTIMCFE */
+#define _MODEM_REALTIMCFE_RTSCHWIN_SHIFT 10 /**< Shift value for MODEM_RTSCHWIN */
+#define _MODEM_REALTIMCFE_RTSCHWIN_MASK 0x3C00UL /**< Bit mask for MODEM_RTSCHWIN */
+#define _MODEM_REALTIMCFE_RTSCHWIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_REALTIMCFE */
+#define MODEM_REALTIMCFE_RTSCHWIN_DEFAULT (_MODEM_REALTIMCFE_RTSCHWIN_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_REALTIMCFE */
+#define MODEM_REALTIMCFE_RTSCHMODE (0x1UL << 14) /**< Real Time CFE searching mode */
+#define _MODEM_REALTIMCFE_RTSCHMODE_SHIFT 14 /**< Shift value for MODEM_RTSCHMODE */
+#define _MODEM_REALTIMCFE_RTSCHMODE_MASK 0x4000UL /**< Bit mask for MODEM_RTSCHMODE */
+#define _MODEM_REALTIMCFE_RTSCHMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_REALTIMCFE */
+#define MODEM_REALTIMCFE_RTSCHMODE_DEFAULT (_MODEM_REALTIMCFE_RTSCHMODE_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_REALTIMCFE */
+#define _MODEM_REALTIMCFE_TRACKINGWIN_SHIFT 15 /**< Shift value for MODEM_TRACKINGWIN */
+#define _MODEM_REALTIMCFE_TRACKINGWIN_MASK 0x38000UL /**< Bit mask for MODEM_TRACKINGWIN */
+#define _MODEM_REALTIMCFE_TRACKINGWIN_DEFAULT 0x00000007UL /**< Mode DEFAULT for MODEM_REALTIMCFE */
+#define MODEM_REALTIMCFE_TRACKINGWIN_DEFAULT (_MODEM_REALTIMCFE_TRACKINGWIN_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_REALTIMCFE */
+#define _MODEM_REALTIMCFE_SYNCACQWIN_SHIFT 18 /**< Shift value for MODEM_SYNCACQWIN */
+#define _MODEM_REALTIMCFE_SYNCACQWIN_MASK 0x1C0000UL /**< Bit mask for MODEM_SYNCACQWIN */
+#define _MODEM_REALTIMCFE_SYNCACQWIN_DEFAULT 0x00000007UL /**< Mode DEFAULT for MODEM_REALTIMCFE */
+#define MODEM_REALTIMCFE_SYNCACQWIN_DEFAULT (_MODEM_REALTIMCFE_SYNCACQWIN_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_REALTIMCFE */
+#define MODEM_REALTIMCFE_EXTENSCHBYP (0x1UL << 21) /**< Bypass extending Search Time */
+#define _MODEM_REALTIMCFE_EXTENSCHBYP_SHIFT 21 /**< Shift value for MODEM_EXTENSCHBYP */
+#define _MODEM_REALTIMCFE_EXTENSCHBYP_MASK 0x200000UL /**< Bit mask for MODEM_EXTENSCHBYP */
+#define _MODEM_REALTIMCFE_EXTENSCHBYP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_REALTIMCFE */
+#define MODEM_REALTIMCFE_EXTENSCHBYP_DEFAULT (_MODEM_REALTIMCFE_EXTENSCHBYP_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_REALTIMCFE */
+#define MODEM_REALTIMCFE_SINEWEN (0x1UL << 29) /**< Enable SINE WEIGHT */
+#define _MODEM_REALTIMCFE_SINEWEN_SHIFT 29 /**< Shift value for MODEM_SINEWEN */
+#define _MODEM_REALTIMCFE_SINEWEN_MASK 0x20000000UL /**< Bit mask for MODEM_SINEWEN */
+#define _MODEM_REALTIMCFE_SINEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_REALTIMCFE */
+#define MODEM_REALTIMCFE_SINEWEN_DEFAULT (_MODEM_REALTIMCFE_SINEWEN_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_REALTIMCFE */
+#define MODEM_REALTIMCFE_VTAFCFRAME (0x1UL << 30) /**< Viterbi AFC FRAME Mode */
+#define _MODEM_REALTIMCFE_VTAFCFRAME_SHIFT 30 /**< Shift value for MODEM_VTAFCFRAME */
+#define _MODEM_REALTIMCFE_VTAFCFRAME_MASK 0x40000000UL /**< Bit mask for MODEM_VTAFCFRAME */
+#define _MODEM_REALTIMCFE_VTAFCFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_REALTIMCFE */
+#define MODEM_REALTIMCFE_VTAFCFRAME_DEFAULT (_MODEM_REALTIMCFE_VTAFCFRAME_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_REALTIMCFE */
+#define MODEM_REALTIMCFE_RTCFEEN (0x1UL << 31) /**< TRECS Enable */
+#define _MODEM_REALTIMCFE_RTCFEEN_SHIFT 31 /**< Shift value for MODEM_RTCFEEN */
+#define _MODEM_REALTIMCFE_RTCFEEN_MASK 0x80000000UL /**< Bit mask for MODEM_RTCFEEN */
+#define _MODEM_REALTIMCFE_RTCFEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_REALTIMCFE */
+#define MODEM_REALTIMCFE_RTCFEEN_DEFAULT (_MODEM_REALTIMCFE_RTCFEEN_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_REALTIMCFE */
+
+/* Bit fields for MODEM ETSCTRL */
+#define _MODEM_ETSCTRL_RESETVALUE 0x00000000UL /**< Default value for MODEM_ETSCTRL */
+#define _MODEM_ETSCTRL_MASK 0x3FFFF7FFUL /**< Mask for MODEM_ETSCTRL */
+#define _MODEM_ETSCTRL_ETSLOC_SHIFT 0 /**< Shift value for MODEM_ETSLOC */
+#define _MODEM_ETSCTRL_ETSLOC_MASK 0x3FFUL /**< Bit mask for MODEM_ETSLOC */
+#define _MODEM_ETSCTRL_ETSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ETSCTRL */
+#define MODEM_ETSCTRL_ETSLOC_DEFAULT (_MODEM_ETSCTRL_ETSLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ETSCTRL */
+#define MODEM_ETSCTRL_CAPSIGONPRS (0x1UL << 10) /**< Capture Signal On PRS */
+#define _MODEM_ETSCTRL_CAPSIGONPRS_SHIFT 10 /**< Shift value for MODEM_CAPSIGONPRS */
+#define _MODEM_ETSCTRL_CAPSIGONPRS_MASK 0x400UL /**< Bit mask for MODEM_CAPSIGONPRS */
+#define _MODEM_ETSCTRL_CAPSIGONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ETSCTRL */
+#define MODEM_ETSCTRL_CAPSIGONPRS_DEFAULT (_MODEM_ETSCTRL_CAPSIGONPRS_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_ETSCTRL */
+#define _MODEM_ETSCTRL_CAPTRIG_SHIFT 12 /**< Shift value for MODEM_CAPTRIG */
+#define _MODEM_ETSCTRL_CAPTRIG_MASK 0x3FFFF000UL /**< Bit mask for MODEM_CAPTRIG */
+#define _MODEM_ETSCTRL_CAPTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ETSCTRL */
+#define MODEM_ETSCTRL_CAPTRIG_DEFAULT (_MODEM_ETSCTRL_CAPTRIG_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_ETSCTRL */
+
+/* Bit fields for MODEM ETSTIM */
+#define _MODEM_ETSTIM_RESETVALUE 0x00000000UL /**< Default value for MODEM_ETSTIM */
+#define _MODEM_ETSTIM_MASK 0x0003FFFFUL /**< Mask for MODEM_ETSTIM */
+#define _MODEM_ETSTIM_ETSTIMVAL_SHIFT 0 /**< Shift value for MODEM_ETSTIMVAL */
+#define _MODEM_ETSTIM_ETSTIMVAL_MASK 0x1FFFFUL /**< Bit mask for MODEM_ETSTIMVAL */
+#define _MODEM_ETSTIM_ETSTIMVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ETSTIM */
+#define MODEM_ETSTIM_ETSTIMVAL_DEFAULT (_MODEM_ETSTIM_ETSTIMVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ETSTIM */
+#define MODEM_ETSTIM_ETSCOUNTEREN (0x1UL << 17) /**< ETSCOUNTEREN */
+#define _MODEM_ETSTIM_ETSCOUNTEREN_SHIFT 17 /**< Shift value for MODEM_ETSCOUNTEREN */
+#define _MODEM_ETSTIM_ETSCOUNTEREN_MASK 0x20000UL /**< Bit mask for MODEM_ETSCOUNTEREN */
+#define _MODEM_ETSTIM_ETSCOUNTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ETSTIM */
+#define MODEM_ETSTIM_ETSCOUNTEREN_DEFAULT (_MODEM_ETSTIM_ETSCOUNTEREN_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_ETSTIM */
+
+/* Bit fields for MODEM ANTSWCTRL */
+#define _MODEM_ANTSWCTRL_RESETVALUE 0x003C0000UL /**< Default value for MODEM_ANTSWCTRL */
+#define _MODEM_ANTSWCTRL_MASK 0x01FFFFFFUL /**< Mask for MODEM_ANTSWCTRL */
+#define _MODEM_ANTSWCTRL_ANTDFLTSEL_SHIFT 0 /**< Shift value for MODEM_ANTDFLTSEL */
+#define _MODEM_ANTSWCTRL_ANTDFLTSEL_MASK 0x3FUL /**< Bit mask for MODEM_ANTDFLTSEL */
+#define _MODEM_ANTSWCTRL_ANTDFLTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANTSWCTRL */
+#define MODEM_ANTSWCTRL_ANTDFLTSEL_DEFAULT (_MODEM_ANTSWCTRL_ANTDFLTSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ANTSWCTRL */
+#define _MODEM_ANTSWCTRL_ANTCOUNT_SHIFT 6 /**< Shift value for MODEM_ANTCOUNT */
+#define _MODEM_ANTSWCTRL_ANTCOUNT_MASK 0xFC0UL /**< Bit mask for MODEM_ANTCOUNT */
+#define _MODEM_ANTSWCTRL_ANTCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANTSWCTRL */
+#define MODEM_ANTSWCTRL_ANTCOUNT_DEFAULT (_MODEM_ANTSWCTRL_ANTCOUNT_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_ANTSWCTRL */
+#define _MODEM_ANTSWCTRL_ANTSWTYPE_SHIFT 12 /**< Shift value for MODEM_ANTSWTYPE */
+#define _MODEM_ANTSWCTRL_ANTSWTYPE_MASK 0x3000UL /**< Bit mask for MODEM_ANTSWTYPE */
+#define _MODEM_ANTSWCTRL_ANTSWTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANTSWCTRL */
+#define _MODEM_ANTSWCTRL_ANTSWTYPE_US_2 0x00000000UL /**< Mode US_2 for MODEM_ANTSWCTRL */
+#define _MODEM_ANTSWCTRL_ANTSWTYPE_US_4 0x00000001UL /**< Mode US_4 for MODEM_ANTSWCTRL */
+#define _MODEM_ANTSWCTRL_ANTSWTYPE_US_6 0x00000002UL /**< Mode US_6 for MODEM_ANTSWCTRL */
+#define _MODEM_ANTSWCTRL_ANTSWTYPE_US_8 0x00000003UL /**< Mode US_8 for MODEM_ANTSWCTRL */
+#define MODEM_ANTSWCTRL_ANTSWTYPE_DEFAULT (_MODEM_ANTSWCTRL_ANTSWTYPE_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_ANTSWCTRL */
+#define MODEM_ANTSWCTRL_ANTSWTYPE_US_2 (_MODEM_ANTSWCTRL_ANTSWTYPE_US_2 << 12) /**< Shifted mode US_2 for MODEM_ANTSWCTRL */
+#define MODEM_ANTSWCTRL_ANTSWTYPE_US_4 (_MODEM_ANTSWCTRL_ANTSWTYPE_US_4 << 12) /**< Shifted mode US_4 for MODEM_ANTSWCTRL */
+#define MODEM_ANTSWCTRL_ANTSWTYPE_US_6 (_MODEM_ANTSWCTRL_ANTSWTYPE_US_6 << 12) /**< Shifted mode US_6 for MODEM_ANTSWCTRL */
+#define MODEM_ANTSWCTRL_ANTSWTYPE_US_8 (_MODEM_ANTSWCTRL_ANTSWTYPE_US_8 << 12) /**< Shifted mode US_8 for MODEM_ANTSWCTRL */
+#define MODEM_ANTSWCTRL_ANTSWRST (0x1UL << 14) /**< Ant SW rst pulse */
+#define _MODEM_ANTSWCTRL_ANTSWRST_SHIFT 14 /**< Shift value for MODEM_ANTSWRST */
+#define _MODEM_ANTSWCTRL_ANTSWRST_MASK 0x4000UL /**< Bit mask for MODEM_ANTSWRST */
+#define _MODEM_ANTSWCTRL_ANTSWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANTSWCTRL */
+#define MODEM_ANTSWCTRL_ANTSWRST_DEFAULT (_MODEM_ANTSWCTRL_ANTSWRST_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_ANTSWCTRL */
+#define MODEM_ANTSWCTRL_CFGANTPATTEN (0x1UL << 15) /**< Configure Ant Pattern Enable */
+#define _MODEM_ANTSWCTRL_CFGANTPATTEN_SHIFT 15 /**< Shift value for MODEM_CFGANTPATTEN */
+#define _MODEM_ANTSWCTRL_CFGANTPATTEN_MASK 0x8000UL /**< Bit mask for MODEM_CFGANTPATTEN */
+#define _MODEM_ANTSWCTRL_CFGANTPATTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANTSWCTRL */
+#define MODEM_ANTSWCTRL_CFGANTPATTEN_DEFAULT (_MODEM_ANTSWCTRL_CFGANTPATTEN_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_ANTSWCTRL */
+#define MODEM_ANTSWCTRL_ANTSWENABLE (0x1UL << 16) /**< Ant sw enable */
+#define _MODEM_ANTSWCTRL_ANTSWENABLE_SHIFT 16 /**< Shift value for MODEM_ANTSWENABLE */
+#define _MODEM_ANTSWCTRL_ANTSWENABLE_MASK 0x10000UL /**< Bit mask for MODEM_ANTSWENABLE */
+#define _MODEM_ANTSWCTRL_ANTSWENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANTSWCTRL */
+#define MODEM_ANTSWCTRL_ANTSWENABLE_DEFAULT (_MODEM_ANTSWCTRL_ANTSWENABLE_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ANTSWCTRL */
+#define _MODEM_ANTSWCTRL_EXTDSTOPPULSECNT_SHIFT 17 /**< Shift value for MODEM_EXTDSTOPPULSECNT */
+#define _MODEM_ANTSWCTRL_EXTDSTOPPULSECNT_MASK 0x1FE0000UL /**< Bit mask for MODEM_EXTDSTOPPULSECNT */
+#define _MODEM_ANTSWCTRL_EXTDSTOPPULSECNT_DEFAULT 0x0000001EUL /**< Mode DEFAULT for MODEM_ANTSWCTRL */
+#define MODEM_ANTSWCTRL_EXTDSTOPPULSECNT_DEFAULT (_MODEM_ANTSWCTRL_EXTDSTOPPULSECNT_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_ANTSWCTRL */
+
+/* Bit fields for MODEM ANTSWCTRL1 */
+#define _MODEM_ANTSWCTRL1_RESETVALUE 0x0006AAAAUL /**< Default value for MODEM_ANTSWCTRL1 */
+#define _MODEM_ANTSWCTRL1_MASK 0x00FFFFFFUL /**< Mask for MODEM_ANTSWCTRL1 */
+#define _MODEM_ANTSWCTRL1_TIMEPERIOD_SHIFT 0 /**< Shift value for MODEM_TIMEPERIOD */
+#define _MODEM_ANTSWCTRL1_TIMEPERIOD_MASK 0xFFFFFFUL /**< Bit mask for MODEM_TIMEPERIOD */
+#define _MODEM_ANTSWCTRL1_TIMEPERIOD_DEFAULT 0x0006AAAAUL /**< Mode DEFAULT for MODEM_ANTSWCTRL1 */
+#define MODEM_ANTSWCTRL1_TIMEPERIOD_DEFAULT (_MODEM_ANTSWCTRL1_TIMEPERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ANTSWCTRL1 */
+
+/* Bit fields for MODEM ANTSWSTART */
+#define _MODEM_ANTSWSTART_RESETVALUE 0x00000000UL /**< Default value for MODEM_ANTSWSTART */
+#define _MODEM_ANTSWSTART_MASK 0x0003FFFFUL /**< Mask for MODEM_ANTSWSTART */
+#define _MODEM_ANTSWSTART_ANTSWSTARTTIM_SHIFT 0 /**< Shift value for MODEM_ANTSWSTARTTIM */
+#define _MODEM_ANTSWSTART_ANTSWSTARTTIM_MASK 0x3FFFFUL /**< Bit mask for MODEM_ANTSWSTARTTIM */
+#define _MODEM_ANTSWSTART_ANTSWSTARTTIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANTSWSTART */
+#define MODEM_ANTSWSTART_ANTSWSTARTTIM_DEFAULT (_MODEM_ANTSWSTART_ANTSWSTARTTIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ANTSWSTART */
+
+/* Bit fields for MODEM ANTSWEND */
+#define _MODEM_ANTSWEND_RESETVALUE 0x00000000UL /**< Default value for MODEM_ANTSWEND */
+#define _MODEM_ANTSWEND_MASK 0x0003FFFFUL /**< Mask for MODEM_ANTSWEND */
+#define _MODEM_ANTSWEND_ANTSWENDTIM_SHIFT 0 /**< Shift value for MODEM_ANTSWENDTIM */
+#define _MODEM_ANTSWEND_ANTSWENDTIM_MASK 0x3FFFFUL /**< Bit mask for MODEM_ANTSWENDTIM */
+#define _MODEM_ANTSWEND_ANTSWENDTIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANTSWEND */
+#define MODEM_ANTSWEND_ANTSWENDTIM_DEFAULT (_MODEM_ANTSWEND_ANTSWENDTIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ANTSWEND */
+
+/* Bit fields for MODEM TRECPMPATT */
+#define _MODEM_TRECPMPATT_RESETVALUE 0x55555555UL /**< Default value for MODEM_TRECPMPATT */
+#define _MODEM_TRECPMPATT_MASK 0xFFFFFFFFUL /**< Mask for MODEM_TRECPMPATT */
+#define _MODEM_TRECPMPATT_PMEXPECTPATT_SHIFT 0 /**< Shift value for MODEM_PMEXPECTPATT */
+#define _MODEM_TRECPMPATT_PMEXPECTPATT_MASK 0xFFFFFFFFUL /**< Bit mask for MODEM_PMEXPECTPATT */
+#define _MODEM_TRECPMPATT_PMEXPECTPATT_DEFAULT 0x55555555UL /**< Mode DEFAULT for MODEM_TRECPMPATT */
+#define MODEM_TRECPMPATT_PMEXPECTPATT_DEFAULT (_MODEM_TRECPMPATT_PMEXPECTPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_TRECPMPATT */
+
+/* Bit fields for MODEM TRECPMDET */
+#define _MODEM_TRECPMDET_RESETVALUE 0x00000017UL /**< Default value for MODEM_TRECPMDET */
+#define _MODEM_TRECPMDET_MASK 0xBEFFC3FFUL /**< Mask for MODEM_TRECPMDET */
+#define _MODEM_TRECPMDET_PMACQUINGWIN_SHIFT 0 /**< Shift value for MODEM_PMACQUINGWIN */
+#define _MODEM_TRECPMDET_PMACQUINGWIN_MASK 0x7UL /**< Bit mask for MODEM_PMACQUINGWIN */
+#define _MODEM_TRECPMDET_PMACQUINGWIN_DEFAULT 0x00000007UL /**< Mode DEFAULT for MODEM_TRECPMDET */
+#define MODEM_TRECPMDET_PMACQUINGWIN_DEFAULT (_MODEM_TRECPMDET_PMACQUINGWIN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_TRECPMDET */
+#define _MODEM_TRECPMDET_PMCOSTVALTHD_SHIFT 3 /**< Shift value for MODEM_PMCOSTVALTHD */
+#define _MODEM_TRECPMDET_PMCOSTVALTHD_MASK 0x38UL /**< Bit mask for MODEM_PMCOSTVALTHD */
+#define _MODEM_TRECPMDET_PMCOSTVALTHD_DEFAULT 0x00000002UL /**< Mode DEFAULT for MODEM_TRECPMDET */
+#define MODEM_TRECPMDET_PMCOSTVALTHD_DEFAULT (_MODEM_TRECPMDET_PMCOSTVALTHD_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_TRECPMDET */
+#define _MODEM_TRECPMDET_PMTIMEOUTSEL_SHIFT 6 /**< Shift value for MODEM_PMTIMEOUTSEL */
+#define _MODEM_TRECPMDET_PMTIMEOUTSEL_MASK 0xC0UL /**< Bit mask for MODEM_PMTIMEOUTSEL */
+#define _MODEM_TRECPMDET_PMTIMEOUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TRECPMDET */
+#define MODEM_TRECPMDET_PMTIMEOUTSEL_DEFAULT (_MODEM_TRECPMDET_PMTIMEOUTSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_TRECPMDET */
+#define _MODEM_TRECPMDET_PHSCALE_SHIFT 8 /**< Shift value for MODEM_PHSCALE */
+#define _MODEM_TRECPMDET_PHSCALE_MASK 0x300UL /**< Bit mask for MODEM_PHSCALE */
+#define _MODEM_TRECPMDET_PHSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TRECPMDET */
+#define MODEM_TRECPMDET_PHSCALE_DEFAULT (_MODEM_TRECPMDET_PHSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_TRECPMDET */
+#define _MODEM_TRECPMDET_PMMINCOSTTHD_SHIFT 14 /**< Shift value for MODEM_PMMINCOSTTHD */
+#define _MODEM_TRECPMDET_PMMINCOSTTHD_MASK 0xFFC000UL /**< Bit mask for MODEM_PMMINCOSTTHD */
+#define _MODEM_TRECPMDET_PMMINCOSTTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TRECPMDET */
+#define MODEM_TRECPMDET_PMMINCOSTTHD_DEFAULT (_MODEM_TRECPMDET_PMMINCOSTTHD_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_TRECPMDET */
+#define _MODEM_TRECPMDET_COSTHYST_SHIFT 25 /**< Shift value for MODEM_COSTHYST */
+#define _MODEM_TRECPMDET_COSTHYST_MASK 0x3E000000UL /**< Bit mask for MODEM_COSTHYST */
+#define _MODEM_TRECPMDET_COSTHYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TRECPMDET */
+#define MODEM_TRECPMDET_COSTHYST_DEFAULT (_MODEM_TRECPMDET_COSTHYST_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_TRECPMDET */
+#define MODEM_TRECPMDET_PREAMSCH (0x1UL << 31) /**< PM detection enable in TRECS */
+#define _MODEM_TRECPMDET_PREAMSCH_SHIFT 31 /**< Shift value for MODEM_PREAMSCH */
+#define _MODEM_TRECPMDET_PREAMSCH_MASK 0x80000000UL /**< Bit mask for MODEM_PREAMSCH */
+#define _MODEM_TRECPMDET_PREAMSCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TRECPMDET */
+#define MODEM_TRECPMDET_PREAMSCH_DEFAULT (_MODEM_TRECPMDET_PREAMSCH_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_TRECPMDET */
+
+/* Bit fields for MODEM TRECSCFG */
+#define _MODEM_TRECSCFG_RESETVALUE 0x00020004UL /**< Default value for MODEM_TRECSCFG */
+#define _MODEM_TRECSCFG_MASK 0x01FF5FFFUL /**< Mask for MODEM_TRECSCFG */
+#define _MODEM_TRECSCFG_TRECSOSR_SHIFT 0 /**< Shift value for MODEM_TRECSOSR */
+#define _MODEM_TRECSCFG_TRECSOSR_MASK 0x7UL /**< Bit mask for MODEM_TRECSOSR */
+#define _MODEM_TRECSCFG_TRECSOSR_DEFAULT 0x00000004UL /**< Mode DEFAULT for MODEM_TRECSCFG */
+#define MODEM_TRECSCFG_TRECSOSR_DEFAULT (_MODEM_TRECSCFG_TRECSOSR_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_TRECSCFG */
+#define _MODEM_TRECSCFG_DTIMLOSSTHD_SHIFT 3 /**< Shift value for MODEM_DTIMLOSSTHD */
+#define _MODEM_TRECSCFG_DTIMLOSSTHD_MASK 0x1FF8UL /**< Bit mask for MODEM_DTIMLOSSTHD */
+#define _MODEM_TRECSCFG_DTIMLOSSTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TRECSCFG */
+#define MODEM_TRECSCFG_DTIMLOSSTHD_DEFAULT (_MODEM_TRECSCFG_DTIMLOSSTHD_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_TRECSCFG */
+#define MODEM_TRECSCFG_DTIMLOSSEN (0x1UL << 14) /**< ENABLE TIMING LOSS DETECTION */
+#define _MODEM_TRECSCFG_DTIMLOSSEN_SHIFT 14 /**< Shift value for MODEM_DTIMLOSSEN */
+#define _MODEM_TRECSCFG_DTIMLOSSEN_MASK 0x4000UL /**< Bit mask for MODEM_DTIMLOSSEN */
+#define _MODEM_TRECSCFG_DTIMLOSSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_TRECSCFG */
+#define MODEM_TRECSCFG_DTIMLOSSEN_DEFAULT (_MODEM_TRECSCFG_DTIMLOSSEN_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_TRECSCFG */
+#define _MODEM_TRECSCFG_PMOFFSET_SHIFT 16 /**< Shift value for MODEM_PMOFFSET */
+#define _MODEM_TRECSCFG_PMOFFSET_MASK 0x1FF0000UL /**< Bit mask for MODEM_PMOFFSET */
+#define _MODEM_TRECSCFG_PMOFFSET_DEFAULT 0x00000002UL /**< Mode DEFAULT for MODEM_TRECSCFG */
+#define MODEM_TRECSCFG_PMOFFSET_DEFAULT (_MODEM_TRECSCFG_PMOFFSET_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_TRECSCFG */
+
+/* Bit fields for MODEM CFGANTPATT */
+#define _MODEM_CFGANTPATT_RESETVALUE 0x00000000UL /**< Default value for MODEM_CFGANTPATT */
+#define _MODEM_CFGANTPATT_MASK 0x3FFFFFFFUL /**< Mask for MODEM_CFGANTPATT */
+#define _MODEM_CFGANTPATT_CFGANTPATTVAL_SHIFT 0 /**< Shift value for MODEM_CFGANTPATTVAL */
+#define _MODEM_CFGANTPATT_CFGANTPATTVAL_MASK 0x3FFFFFFFUL /**< Bit mask for MODEM_CFGANTPATTVAL */
+#define _MODEM_CFGANTPATT_CFGANTPATTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CFGANTPATT */
+#define MODEM_CFGANTPATT_CFGANTPATTVAL_DEFAULT (_MODEM_CFGANTPATT_CFGANTPATTVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CFGANTPATT */
+
+/* Bit fields for MODEM COCURRMODE */
+#define _MODEM_COCURRMODE_RESETVALUE 0x00000000UL /**< Default value for MODEM_COCURRMODE */
+#define _MODEM_COCURRMODE_MASK 0x80000000UL /**< Mask for MODEM_COCURRMODE */
+#define MODEM_COCURRMODE_CONCURRENT (0x1UL << 31) /**< CONCURRENT MODE Enable */
+#define _MODEM_COCURRMODE_CONCURRENT_SHIFT 31 /**< Shift value for MODEM_CONCURRENT */
+#define _MODEM_COCURRMODE_CONCURRENT_MASK 0x80000000UL /**< Bit mask for MODEM_CONCURRENT */
+#define _MODEM_COCURRMODE_CONCURRENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_COCURRMODE */
+#define MODEM_COCURRMODE_CONCURRENT_DEFAULT (_MODEM_COCURRMODE_CONCURRENT_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_COCURRMODE */
+
+/* Bit fields for MODEM CHFCOE00 */
+#define _MODEM_CHFCOE00_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFCOE00 */
+#define _MODEM_CHFCOE00_MASK 0x3FFFFFFFUL /**< Mask for MODEM_CHFCOE00 */
+#define _MODEM_CHFCOE00_SET0COEFF0_SHIFT 0 /**< Shift value for MODEM_SET0COEFF0 */
+#define _MODEM_CHFCOE00_SET0COEFF0_MASK 0x3FFUL /**< Bit mask for MODEM_SET0COEFF0 */
+#define _MODEM_CHFCOE00_SET0COEFF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE00 */
+#define MODEM_CHFCOE00_SET0COEFF0_DEFAULT (_MODEM_CHFCOE00_SET0COEFF0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFCOE00 */
+#define _MODEM_CHFCOE00_SET0COEFF1_SHIFT 10 /**< Shift value for MODEM_SET0COEFF1 */
+#define _MODEM_CHFCOE00_SET0COEFF1_MASK 0xFFC00UL /**< Bit mask for MODEM_SET0COEFF1 */
+#define _MODEM_CHFCOE00_SET0COEFF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE00 */
+#define MODEM_CHFCOE00_SET0COEFF1_DEFAULT (_MODEM_CHFCOE00_SET0COEFF1_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_CHFCOE00 */
+#define _MODEM_CHFCOE00_SET0COEFF2_SHIFT 20 /**< Shift value for MODEM_SET0COEFF2 */
+#define _MODEM_CHFCOE00_SET0COEFF2_MASK 0x3FF00000UL /**< Bit mask for MODEM_SET0COEFF2 */
+#define _MODEM_CHFCOE00_SET0COEFF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE00 */
+#define MODEM_CHFCOE00_SET0COEFF2_DEFAULT (_MODEM_CHFCOE00_SET0COEFF2_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_CHFCOE00 */
+
+/* Bit fields for MODEM CHFCOE01 */
+#define _MODEM_CHFCOE01_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFCOE01 */
+#define _MODEM_CHFCOE01_MASK 0x003FFFFFUL /**< Mask for MODEM_CHFCOE01 */
+#define _MODEM_CHFCOE01_SET0COEFF3_SHIFT 0 /**< Shift value for MODEM_SET0COEFF3 */
+#define _MODEM_CHFCOE01_SET0COEFF3_MASK 0x7FFUL /**< Bit mask for MODEM_SET0COEFF3 */
+#define _MODEM_CHFCOE01_SET0COEFF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE01 */
+#define MODEM_CHFCOE01_SET0COEFF3_DEFAULT (_MODEM_CHFCOE01_SET0COEFF3_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFCOE01 */
+#define _MODEM_CHFCOE01_SET0COEFF4_SHIFT 11 /**< Shift value for MODEM_SET0COEFF4 */
+#define _MODEM_CHFCOE01_SET0COEFF4_MASK 0x3FF800UL /**< Bit mask for MODEM_SET0COEFF4 */
+#define _MODEM_CHFCOE01_SET0COEFF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE01 */
+#define MODEM_CHFCOE01_SET0COEFF4_DEFAULT (_MODEM_CHFCOE01_SET0COEFF4_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_CHFCOE01 */
+
+/* Bit fields for MODEM CHFCOE02 */
+#define _MODEM_CHFCOE02_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFCOE02 */
+#define _MODEM_CHFCOE02_MASK 0x007FFFFFUL /**< Mask for MODEM_CHFCOE02 */
+#define _MODEM_CHFCOE02_SET0COEFF5_SHIFT 0 /**< Shift value for MODEM_SET0COEFF5 */
+#define _MODEM_CHFCOE02_SET0COEFF5_MASK 0x7FFUL /**< Bit mask for MODEM_SET0COEFF5 */
+#define _MODEM_CHFCOE02_SET0COEFF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE02 */
+#define MODEM_CHFCOE02_SET0COEFF5_DEFAULT (_MODEM_CHFCOE02_SET0COEFF5_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFCOE02 */
+#define _MODEM_CHFCOE02_SET0COEFF6_SHIFT 11 /**< Shift value for MODEM_SET0COEFF6 */
+#define _MODEM_CHFCOE02_SET0COEFF6_MASK 0x7FF800UL /**< Bit mask for MODEM_SET0COEFF6 */
+#define _MODEM_CHFCOE02_SET0COEFF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE02 */
+#define MODEM_CHFCOE02_SET0COEFF6_DEFAULT (_MODEM_CHFCOE02_SET0COEFF6_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_CHFCOE02 */
+
+/* Bit fields for MODEM CHFCOE03 */
+#define _MODEM_CHFCOE03_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFCOE03 */
+#define _MODEM_CHFCOE03_MASK 0x00FFFFFFUL /**< Mask for MODEM_CHFCOE03 */
+#define _MODEM_CHFCOE03_SET0COEFF7_SHIFT 0 /**< Shift value for MODEM_SET0COEFF7 */
+#define _MODEM_CHFCOE03_SET0COEFF7_MASK 0xFFFUL /**< Bit mask for MODEM_SET0COEFF7 */
+#define _MODEM_CHFCOE03_SET0COEFF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE03 */
+#define MODEM_CHFCOE03_SET0COEFF7_DEFAULT (_MODEM_CHFCOE03_SET0COEFF7_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFCOE03 */
+#define _MODEM_CHFCOE03_SET0COEFF8_SHIFT 12 /**< Shift value for MODEM_SET0COEFF8 */
+#define _MODEM_CHFCOE03_SET0COEFF8_MASK 0xFFF000UL /**< Bit mask for MODEM_SET0COEFF8 */
+#define _MODEM_CHFCOE03_SET0COEFF8_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE03 */
+#define MODEM_CHFCOE03_SET0COEFF8_DEFAULT (_MODEM_CHFCOE03_SET0COEFF8_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_CHFCOE03 */
+
+/* Bit fields for MODEM CHFCOE04 */
+#define _MODEM_CHFCOE04_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFCOE04 */
+#define _MODEM_CHFCOE04_MASK 0x0FFFFFFFUL /**< Mask for MODEM_CHFCOE04 */
+#define _MODEM_CHFCOE04_SET0COEFF9_SHIFT 0 /**< Shift value for MODEM_SET0COEFF9 */
+#define _MODEM_CHFCOE04_SET0COEFF9_MASK 0x3FFFUL /**< Bit mask for MODEM_SET0COEFF9 */
+#define _MODEM_CHFCOE04_SET0COEFF9_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE04 */
+#define MODEM_CHFCOE04_SET0COEFF9_DEFAULT (_MODEM_CHFCOE04_SET0COEFF9_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFCOE04 */
+#define _MODEM_CHFCOE04_SET0COEFF10_SHIFT 14 /**< Shift value for MODEM_SET0COEFF10 */
+#define _MODEM_CHFCOE04_SET0COEFF10_MASK 0xFFFC000UL /**< Bit mask for MODEM_SET0COEFF10 */
+#define _MODEM_CHFCOE04_SET0COEFF10_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE04 */
+#define MODEM_CHFCOE04_SET0COEFF10_DEFAULT (_MODEM_CHFCOE04_SET0COEFF10_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_CHFCOE04 */
+
+/* Bit fields for MODEM CHFCOE05 */
+#define _MODEM_CHFCOE05_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFCOE05 */
+#define _MODEM_CHFCOE05_MASK 0x3FFFFFFFUL /**< Mask for MODEM_CHFCOE05 */
+#define _MODEM_CHFCOE05_SET0COEFF11_SHIFT 0 /**< Shift value for MODEM_SET0COEFF11 */
+#define _MODEM_CHFCOE05_SET0COEFF11_MASK 0x3FFFUL /**< Bit mask for MODEM_SET0COEFF11 */
+#define _MODEM_CHFCOE05_SET0COEFF11_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE05 */
+#define MODEM_CHFCOE05_SET0COEFF11_DEFAULT (_MODEM_CHFCOE05_SET0COEFF11_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFCOE05 */
+#define _MODEM_CHFCOE05_SET0COEFF12_SHIFT 14 /**< Shift value for MODEM_SET0COEFF12 */
+#define _MODEM_CHFCOE05_SET0COEFF12_MASK 0x3FFFC000UL /**< Bit mask for MODEM_SET0COEFF12 */
+#define _MODEM_CHFCOE05_SET0COEFF12_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE05 */
+#define MODEM_CHFCOE05_SET0COEFF12_DEFAULT (_MODEM_CHFCOE05_SET0COEFF12_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_CHFCOE05 */
+
+/* Bit fields for MODEM CHFCOE06 */
+#define _MODEM_CHFCOE06_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFCOE06 */
+#define _MODEM_CHFCOE06_MASK 0xFFFFFFFFUL /**< Mask for MODEM_CHFCOE06 */
+#define _MODEM_CHFCOE06_SET0COEFF13_SHIFT 0 /**< Shift value for MODEM_SET0COEFF13 */
+#define _MODEM_CHFCOE06_SET0COEFF13_MASK 0xFFFFUL /**< Bit mask for MODEM_SET0COEFF13 */
+#define _MODEM_CHFCOE06_SET0COEFF13_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE06 */
+#define MODEM_CHFCOE06_SET0COEFF13_DEFAULT (_MODEM_CHFCOE06_SET0COEFF13_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFCOE06 */
+#define _MODEM_CHFCOE06_SET0COEFF14_SHIFT 16 /**< Shift value for MODEM_SET0COEFF14 */
+#define _MODEM_CHFCOE06_SET0COEFF14_MASK 0xFFFF0000UL /**< Bit mask for MODEM_SET0COEFF14 */
+#define _MODEM_CHFCOE06_SET0COEFF14_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE06 */
+#define MODEM_CHFCOE06_SET0COEFF14_DEFAULT (_MODEM_CHFCOE06_SET0COEFF14_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_CHFCOE06 */
+
+/* Bit fields for MODEM CHFCOE10 */
+#define _MODEM_CHFCOE10_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFCOE10 */
+#define _MODEM_CHFCOE10_MASK 0x3FFFFFFFUL /**< Mask for MODEM_CHFCOE10 */
+#define _MODEM_CHFCOE10_SET1COEFF0_SHIFT 0 /**< Shift value for MODEM_SET1COEFF0 */
+#define _MODEM_CHFCOE10_SET1COEFF0_MASK 0x3FFUL /**< Bit mask for MODEM_SET1COEFF0 */
+#define _MODEM_CHFCOE10_SET1COEFF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE10 */
+#define MODEM_CHFCOE10_SET1COEFF0_DEFAULT (_MODEM_CHFCOE10_SET1COEFF0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFCOE10 */
+#define _MODEM_CHFCOE10_SET1COEFF1_SHIFT 10 /**< Shift value for MODEM_SET1COEFF1 */
+#define _MODEM_CHFCOE10_SET1COEFF1_MASK 0xFFC00UL /**< Bit mask for MODEM_SET1COEFF1 */
+#define _MODEM_CHFCOE10_SET1COEFF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE10 */
+#define MODEM_CHFCOE10_SET1COEFF1_DEFAULT (_MODEM_CHFCOE10_SET1COEFF1_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_CHFCOE10 */
+#define _MODEM_CHFCOE10_SET1COEFF2_SHIFT 20 /**< Shift value for MODEM_SET1COEFF2 */
+#define _MODEM_CHFCOE10_SET1COEFF2_MASK 0x3FF00000UL /**< Bit mask for MODEM_SET1COEFF2 */
+#define _MODEM_CHFCOE10_SET1COEFF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE10 */
+#define MODEM_CHFCOE10_SET1COEFF2_DEFAULT (_MODEM_CHFCOE10_SET1COEFF2_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_CHFCOE10 */
+
+/* Bit fields for MODEM CHFCOE11 */
+#define _MODEM_CHFCOE11_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFCOE11 */
+#define _MODEM_CHFCOE11_MASK 0x003FFFFFUL /**< Mask for MODEM_CHFCOE11 */
+#define _MODEM_CHFCOE11_SET1COEFF3_SHIFT 0 /**< Shift value for MODEM_SET1COEFF3 */
+#define _MODEM_CHFCOE11_SET1COEFF3_MASK 0x7FFUL /**< Bit mask for MODEM_SET1COEFF3 */
+#define _MODEM_CHFCOE11_SET1COEFF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE11 */
+#define MODEM_CHFCOE11_SET1COEFF3_DEFAULT (_MODEM_CHFCOE11_SET1COEFF3_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFCOE11 */
+#define _MODEM_CHFCOE11_SET1COEFF4_SHIFT 11 /**< Shift value for MODEM_SET1COEFF4 */
+#define _MODEM_CHFCOE11_SET1COEFF4_MASK 0x3FF800UL /**< Bit mask for MODEM_SET1COEFF4 */
+#define _MODEM_CHFCOE11_SET1COEFF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE11 */
+#define MODEM_CHFCOE11_SET1COEFF4_DEFAULT (_MODEM_CHFCOE11_SET1COEFF4_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_CHFCOE11 */
+
+/* Bit fields for MODEM CHFCOE12 */
+#define _MODEM_CHFCOE12_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFCOE12 */
+#define _MODEM_CHFCOE12_MASK 0x007FFFFFUL /**< Mask for MODEM_CHFCOE12 */
+#define _MODEM_CHFCOE12_SET1COEFF5_SHIFT 0 /**< Shift value for MODEM_SET1COEFF5 */
+#define _MODEM_CHFCOE12_SET1COEFF5_MASK 0x7FFUL /**< Bit mask for MODEM_SET1COEFF5 */
+#define _MODEM_CHFCOE12_SET1COEFF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE12 */
+#define MODEM_CHFCOE12_SET1COEFF5_DEFAULT (_MODEM_CHFCOE12_SET1COEFF5_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFCOE12 */
+#define _MODEM_CHFCOE12_SET1COEFF6_SHIFT 11 /**< Shift value for MODEM_SET1COEFF6 */
+#define _MODEM_CHFCOE12_SET1COEFF6_MASK 0x7FF800UL /**< Bit mask for MODEM_SET1COEFF6 */
+#define _MODEM_CHFCOE12_SET1COEFF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE12 */
+#define MODEM_CHFCOE12_SET1COEFF6_DEFAULT (_MODEM_CHFCOE12_SET1COEFF6_DEFAULT << 11) /**< Shifted mode DEFAULT for MODEM_CHFCOE12 */
+
+/* Bit fields for MODEM CHFCOE13 */
+#define _MODEM_CHFCOE13_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFCOE13 */
+#define _MODEM_CHFCOE13_MASK 0x00FFFFFFUL /**< Mask for MODEM_CHFCOE13 */
+#define _MODEM_CHFCOE13_SET1COEFF7_SHIFT 0 /**< Shift value for MODEM_SET1COEFF7 */
+#define _MODEM_CHFCOE13_SET1COEFF7_MASK 0xFFFUL /**< Bit mask for MODEM_SET1COEFF7 */
+#define _MODEM_CHFCOE13_SET1COEFF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE13 */
+#define MODEM_CHFCOE13_SET1COEFF7_DEFAULT (_MODEM_CHFCOE13_SET1COEFF7_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFCOE13 */
+#define _MODEM_CHFCOE13_SET1COEFF8_SHIFT 12 /**< Shift value for MODEM_SET1COEFF8 */
+#define _MODEM_CHFCOE13_SET1COEFF8_MASK 0xFFF000UL /**< Bit mask for MODEM_SET1COEFF8 */
+#define _MODEM_CHFCOE13_SET1COEFF8_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE13 */
+#define MODEM_CHFCOE13_SET1COEFF8_DEFAULT (_MODEM_CHFCOE13_SET1COEFF8_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_CHFCOE13 */
+
+/* Bit fields for MODEM CHFCOE14 */
+#define _MODEM_CHFCOE14_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFCOE14 */
+#define _MODEM_CHFCOE14_MASK 0x0FFFFFFFUL /**< Mask for MODEM_CHFCOE14 */
+#define _MODEM_CHFCOE14_SET1COEFF9_SHIFT 0 /**< Shift value for MODEM_SET1COEFF9 */
+#define _MODEM_CHFCOE14_SET1COEFF9_MASK 0x3FFFUL /**< Bit mask for MODEM_SET1COEFF9 */
+#define _MODEM_CHFCOE14_SET1COEFF9_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE14 */
+#define MODEM_CHFCOE14_SET1COEFF9_DEFAULT (_MODEM_CHFCOE14_SET1COEFF9_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFCOE14 */
+#define _MODEM_CHFCOE14_SET1COEFF10_SHIFT 14 /**< Shift value for MODEM_SET1COEFF10 */
+#define _MODEM_CHFCOE14_SET1COEFF10_MASK 0xFFFC000UL /**< Bit mask for MODEM_SET1COEFF10 */
+#define _MODEM_CHFCOE14_SET1COEFF10_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE14 */
+#define MODEM_CHFCOE14_SET1COEFF10_DEFAULT (_MODEM_CHFCOE14_SET1COEFF10_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_CHFCOE14 */
+
+/* Bit fields for MODEM CHFCOE15 */
+#define _MODEM_CHFCOE15_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFCOE15 */
+#define _MODEM_CHFCOE15_MASK 0x3FFFFFFFUL /**< Mask for MODEM_CHFCOE15 */
+#define _MODEM_CHFCOE15_SET1COEFF11_SHIFT 0 /**< Shift value for MODEM_SET1COEFF11 */
+#define _MODEM_CHFCOE15_SET1COEFF11_MASK 0x3FFFUL /**< Bit mask for MODEM_SET1COEFF11 */
+#define _MODEM_CHFCOE15_SET1COEFF11_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE15 */
+#define MODEM_CHFCOE15_SET1COEFF11_DEFAULT (_MODEM_CHFCOE15_SET1COEFF11_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFCOE15 */
+#define _MODEM_CHFCOE15_SET1COEFF12_SHIFT 14 /**< Shift value for MODEM_SET1COEFF12 */
+#define _MODEM_CHFCOE15_SET1COEFF12_MASK 0x3FFFC000UL /**< Bit mask for MODEM_SET1COEFF12 */
+#define _MODEM_CHFCOE15_SET1COEFF12_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE15 */
+#define MODEM_CHFCOE15_SET1COEFF12_DEFAULT (_MODEM_CHFCOE15_SET1COEFF12_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_CHFCOE15 */
+
+/* Bit fields for MODEM CHFCOE16 */
+#define _MODEM_CHFCOE16_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFCOE16 */
+#define _MODEM_CHFCOE16_MASK 0xFFFFFFFFUL /**< Mask for MODEM_CHFCOE16 */
+#define _MODEM_CHFCOE16_SET1COEFF13_SHIFT 0 /**< Shift value for MODEM_SET1COEFF13 */
+#define _MODEM_CHFCOE16_SET1COEFF13_MASK 0xFFFFUL /**< Bit mask for MODEM_SET1COEFF13 */
+#define _MODEM_CHFCOE16_SET1COEFF13_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE16 */
+#define MODEM_CHFCOE16_SET1COEFF13_DEFAULT (_MODEM_CHFCOE16_SET1COEFF13_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFCOE16 */
+#define _MODEM_CHFCOE16_SET1COEFF14_SHIFT 16 /**< Shift value for MODEM_SET1COEFF14 */
+#define _MODEM_CHFCOE16_SET1COEFF14_MASK 0xFFFF0000UL /**< Bit mask for MODEM_SET1COEFF14 */
+#define _MODEM_CHFCOE16_SET1COEFF14_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCOE16 */
+#define MODEM_CHFCOE16_SET1COEFF14_DEFAULT (_MODEM_CHFCOE16_SET1COEFF14_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_CHFCOE16 */
+
+/* Bit fields for MODEM CHFCTRL */
+#define _MODEM_CHFCTRL_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFCTRL */
+#define _MODEM_CHFCTRL_MASK 0xB0000003UL /**< Mask for MODEM_CHFCTRL */
+#define MODEM_CHFCTRL_FWSWCOEFFEN (0x1UL << 0) /**< FW Switch CHF COE. Enable */
+#define _MODEM_CHFCTRL_FWSWCOEFFEN_SHIFT 0 /**< Shift value for MODEM_FWSWCOEFFEN */
+#define _MODEM_CHFCTRL_FWSWCOEFFEN_MASK 0x1UL /**< Bit mask for MODEM_FWSWCOEFFEN */
+#define _MODEM_CHFCTRL_FWSWCOEFFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCTRL */
+#define MODEM_CHFCTRL_FWSWCOEFFEN_DEFAULT (_MODEM_CHFCTRL_FWSWCOEFFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFCTRL */
+#define MODEM_CHFCTRL_FWSELCOEFF (0x1UL << 1) /**< FW Select CHF COE. set */
+#define _MODEM_CHFCTRL_FWSELCOEFF_SHIFT 1 /**< Shift value for MODEM_FWSELCOEFF */
+#define _MODEM_CHFCTRL_FWSELCOEFF_MASK 0x2UL /**< Bit mask for MODEM_FWSELCOEFF */
+#define _MODEM_CHFCTRL_FWSELCOEFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCTRL */
+#define MODEM_CHFCTRL_FWSELCOEFF_DEFAULT (_MODEM_CHFCTRL_FWSELCOEFF_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_CHFCTRL */
+#define _MODEM_CHFCTRL_CHFSWSEL_SHIFT 28 /**< Shift value for MODEM_CHFSWSEL */
+#define _MODEM_CHFCTRL_CHFSWSEL_MASK 0x30000000UL /**< Bit mask for MODEM_CHFSWSEL */
+#define _MODEM_CHFCTRL_CHFSWSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCTRL */
+#define _MODEM_CHFCTRL_CHFSWSEL_PREDET 0x00000000UL /**< Mode PREDET for MODEM_CHFCTRL */
+#define _MODEM_CHFCTRL_CHFSWSEL_FRC_SUP 0x00000001UL /**< Mode FRC_SUP for MODEM_CHFCTRL */
+#define _MODEM_CHFCTRL_CHFSWSEL_CHFSWTRIG 0x00000002UL /**< Mode CHFSWTRIG for MODEM_CHFCTRL */
+#define _MODEM_CHFCTRL_CHFSWSEL_INVALID 0x00000003UL /**< Mode INVALID for MODEM_CHFCTRL */
+#define MODEM_CHFCTRL_CHFSWSEL_DEFAULT (_MODEM_CHFCTRL_CHFSWSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_CHFCTRL */
+#define MODEM_CHFCTRL_CHFSWSEL_PREDET (_MODEM_CHFCTRL_CHFSWSEL_PREDET << 28) /**< Shifted mode PREDET for MODEM_CHFCTRL */
+#define MODEM_CHFCTRL_CHFSWSEL_FRC_SUP (_MODEM_CHFCTRL_CHFSWSEL_FRC_SUP << 28) /**< Shifted mode FRC_SUP for MODEM_CHFCTRL */
+#define MODEM_CHFCTRL_CHFSWSEL_CHFSWTRIG (_MODEM_CHFCTRL_CHFSWSEL_CHFSWTRIG << 28) /**< Shifted mode CHFSWTRIG for MODEM_CHFCTRL */
+#define MODEM_CHFCTRL_CHFSWSEL_INVALID (_MODEM_CHFCTRL_CHFSWSEL_INVALID << 28) /**< Shifted mode INVALID for MODEM_CHFCTRL */
+#define MODEM_CHFCTRL_SWCOEFFEN (0x1UL << 31) /**< Switch CHF COE. Enable */
+#define _MODEM_CHFCTRL_SWCOEFFEN_SHIFT 31 /**< Shift value for MODEM_SWCOEFFEN */
+#define _MODEM_CHFCTRL_SWCOEFFEN_MASK 0x80000000UL /**< Bit mask for MODEM_SWCOEFFEN */
+#define _MODEM_CHFCTRL_SWCOEFFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFCTRL */
+#define MODEM_CHFCTRL_SWCOEFFEN_DEFAULT (_MODEM_CHFCTRL_SWCOEFFEN_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_CHFCTRL */
+
+/* Bit fields for MODEM CHFLATENCYCTRL */
+#define _MODEM_CHFLATENCYCTRL_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFLATENCYCTRL */
+#define _MODEM_CHFLATENCYCTRL_MASK 0x00000003UL /**< Mask for MODEM_CHFLATENCYCTRL */
+#define _MODEM_CHFLATENCYCTRL_CHFLATENCY_SHIFT 0 /**< Shift value for MODEM_CHFLATENCY */
+#define _MODEM_CHFLATENCYCTRL_CHFLATENCY_MASK 0x3UL /**< Bit mask for MODEM_CHFLATENCY */
+#define _MODEM_CHFLATENCYCTRL_CHFLATENCY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFLATENCYCTRL */
+#define MODEM_CHFLATENCYCTRL_CHFLATENCY_DEFAULT (_MODEM_CHFLATENCYCTRL_CHFLATENCY_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFLATENCYCTRL*/
+
+/* Bit fields for MODEM FRMSCHTIME */
+#define _MODEM_FRMSCHTIME_RESETVALUE 0x00000040UL /**< Default value for MODEM_FRMSCHTIME */
+#define _MODEM_FRMSCHTIME_MASK 0xE000FFFFUL /**< Mask for MODEM_FRMSCHTIME */
+#define _MODEM_FRMSCHTIME_FRMSCHTIME_SHIFT 0 /**< Shift value for MODEM_FRMSCHTIME */
+#define _MODEM_FRMSCHTIME_FRMSCHTIME_MASK 0xFFFFUL /**< Bit mask for MODEM_FRMSCHTIME */
+#define _MODEM_FRMSCHTIME_FRMSCHTIME_DEFAULT 0x00000040UL /**< Mode DEFAULT for MODEM_FRMSCHTIME */
+#define MODEM_FRMSCHTIME_FRMSCHTIME_DEFAULT (_MODEM_FRMSCHTIME_FRMSCHTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_FRMSCHTIME */
+#define MODEM_FRMSCHTIME_PMRSTSYCNEN (0x1UL << 29) /**< ENABLE CLEAN SYNC */
+#define _MODEM_FRMSCHTIME_PMRSTSYCNEN_SHIFT 29 /**< Shift value for MODEM_PMRSTSYCNEN */
+#define _MODEM_FRMSCHTIME_PMRSTSYCNEN_MASK 0x20000000UL /**< Bit mask for MODEM_PMRSTSYCNEN */
+#define _MODEM_FRMSCHTIME_PMRSTSYCNEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_FRMSCHTIME */
+#define MODEM_FRMSCHTIME_PMRSTSYCNEN_DEFAULT (_MODEM_FRMSCHTIME_PMRSTSYCNEN_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_FRMSCHTIME */
+#define MODEM_FRMSCHTIME_DSARSTSYCNEN (0x1UL << 30) /**< ENABLE CLEAN SYNC */
+#define _MODEM_FRMSCHTIME_DSARSTSYCNEN_SHIFT 30 /**< Shift value for MODEM_DSARSTSYCNEN */
+#define _MODEM_FRMSCHTIME_DSARSTSYCNEN_MASK 0x40000000UL /**< Bit mask for MODEM_DSARSTSYCNEN */
+#define _MODEM_FRMSCHTIME_DSARSTSYCNEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_FRMSCHTIME */
+#define MODEM_FRMSCHTIME_DSARSTSYCNEN_DEFAULT (_MODEM_FRMSCHTIME_DSARSTSYCNEN_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_FRMSCHTIME */
+#define MODEM_FRMSCHTIME_PMENDSCHEN (0x1UL << 31) /**< EnABLE SCH PM END */
+#define _MODEM_FRMSCHTIME_PMENDSCHEN_SHIFT 31 /**< Shift value for MODEM_PMENDSCHEN */
+#define _MODEM_FRMSCHTIME_PMENDSCHEN_MASK 0x80000000UL /**< Bit mask for MODEM_PMENDSCHEN */
+#define _MODEM_FRMSCHTIME_PMENDSCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_FRMSCHTIME */
+#define MODEM_FRMSCHTIME_PMENDSCHEN_DEFAULT (_MODEM_FRMSCHTIME_PMENDSCHEN_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_FRMSCHTIME */
+
+/* Bit fields for MODEM PREFILTCOEFF */
+#define _MODEM_PREFILTCOEFF_RESETVALUE 0x3B3B3B3BUL /**< Default value for MODEM_PREFILTCOEFF */
+#define _MODEM_PREFILTCOEFF_MASK 0xFFFFFFFFUL /**< Mask for MODEM_PREFILTCOEFF */
+#define _MODEM_PREFILTCOEFF_PREFILTCOEFF_SHIFT 0 /**< Shift value for MODEM_PREFILTCOEFF */
+#define _MODEM_PREFILTCOEFF_PREFILTCOEFF_MASK 0xFFFFFFFFUL /**< Bit mask for MODEM_PREFILTCOEFF */
+#define _MODEM_PREFILTCOEFF_PREFILTCOEFF_DEFAULT 0x3B3B3B3BUL /**< Mode DEFAULT for MODEM_PREFILTCOEFF */
+#define MODEM_PREFILTCOEFF_PREFILTCOEFF_DEFAULT (_MODEM_PREFILTCOEFF_PREFILTCOEFF_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_PREFILTCOEFF */
+
+/* Bit fields for MODEM RXRESTART */
+#define _MODEM_RXRESTART_RESETVALUE 0x00001860UL /**< Default value for MODEM_RXRESTART */
+#define _MODEM_RXRESTART_MASK 0xC0011FF1UL /**< Mask for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTUPONMARSSI (0x1UL << 0) /**< Restart RX upon RSSI MA above threshold */
+#define _MODEM_RXRESTART_RXRESTARTUPONMARSSI_SHIFT 0 /**< Shift value for MODEM_RXRESTARTUPONMARSSI */
+#define _MODEM_RXRESTART_RXRESTARTUPONMARSSI_MASK 0x1UL /**< Bit mask for MODEM_RXRESTARTUPONMARSSI */
+#define _MODEM_RXRESTART_RXRESTARTUPONMARSSI_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTUPONMARSSI_DEFAULT (_MODEM_RXRESTART_RXRESTARTUPONMARSSI_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_RXRESTART */
+#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_SHIFT 4 /**< Shift value for MODEM_RXRESTARTMATHRESHOLD */
+#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_MASK 0xF0UL /**< Bit mask for MODEM_RXRESTARTMATHRESHOLD */
+#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DEFAULT 0x00000006UL /**< Mode DEFAULT for MODEM_RXRESTART */
+#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB0 0x00000000UL /**< Mode DB0 for MODEM_RXRESTART */
+#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB1 0x00000001UL /**< Mode DB1 for MODEM_RXRESTART */
+#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB2 0x00000002UL /**< Mode DB2 for MODEM_RXRESTART */
+#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB3 0x00000003UL /**< Mode DB3 for MODEM_RXRESTART */
+#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB4 0x00000004UL /**< Mode DB4 for MODEM_RXRESTART */
+#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB5 0x00000005UL /**< Mode DB5 for MODEM_RXRESTART */
+#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB6 0x00000006UL /**< Mode DB6 for MODEM_RXRESTART */
+#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB7 0x00000007UL /**< Mode DB7 for MODEM_RXRESTART */
+#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB8 0x00000008UL /**< Mode DB8 for MODEM_RXRESTART */
+#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB9 0x00000009UL /**< Mode DB9 for MODEM_RXRESTART */
+#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB10 0x0000000AUL /**< Mode DB10 for MODEM_RXRESTART */
+#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB11 0x0000000BUL /**< Mode DB11 for MODEM_RXRESTART */
+#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB12 0x0000000CUL /**< Mode DB12 for MODEM_RXRESTART */
+#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB13 0x0000000DUL /**< Mode DB13 for MODEM_RXRESTART */
+#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB14 0x0000000EUL /**< Mode DB14 for MODEM_RXRESTART */
+#define _MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB15 0x0000000FUL /**< Mode DB15 for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DEFAULT (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB0 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB0 << 4) /**< Shifted mode DB0 for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB1 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB1 << 4) /**< Shifted mode DB1 for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB2 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB2 << 4) /**< Shifted mode DB2 for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB3 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB3 << 4) /**< Shifted mode DB3 for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB4 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB4 << 4) /**< Shifted mode DB4 for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB5 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB5 << 4) /**< Shifted mode DB5 for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB6 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB6 << 4) /**< Shifted mode DB6 for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB7 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB7 << 4) /**< Shifted mode DB7 for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB8 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB8 << 4) /**< Shifted mode DB8 for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB9 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB9 << 4) /**< Shifted mode DB9 for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB10 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB10 << 4) /**< Shifted mode DB10 for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB11 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB11 << 4) /**< Shifted mode DB11 for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB12 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB12 << 4) /**< Shifted mode DB12 for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB13 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB13 << 4) /**< Shifted mode DB13 for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB14 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB14 << 4) /**< Shifted mode DB14 for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB15 (_MODEM_RXRESTART_RXRESTARTMATHRESHOLD_DB15 << 4) /**< Shifted mode DB15 for MODEM_RXRESTART */
+#define _MODEM_RXRESTART_RXRESTARTMALATCHSEL_SHIFT 8 /**< Shift value for MODEM_RXRESTARTMALATCHSEL */
+#define _MODEM_RXRESTART_RXRESTARTMALATCHSEL_MASK 0x300UL /**< Bit mask for MODEM_RXRESTARTMALATCHSEL */
+#define _MODEM_RXRESTART_RXRESTARTMALATCHSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_RXRESTART */
+#define _MODEM_RXRESTART_RXRESTARTMALATCHSEL_RE_PRE_DET 0x00000000UL /**< Mode RE_PRE_DET for MODEM_RXRESTART */
+#define _MODEM_RXRESTART_RXRESTARTMALATCHSEL_RE_SYNC_DET 0x00000001UL /**< Mode RE_SYNC_DET for MODEM_RXRESTART */
+#define _MODEM_RXRESTART_RXRESTARTMALATCHSEL_EITHER1 0x00000002UL /**< Mode EITHER1 for MODEM_RXRESTART */
+#define _MODEM_RXRESTART_RXRESTARTMALATCHSEL_EITHER2 0x00000003UL /**< Mode EITHER2 for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTMALATCHSEL_DEFAULT (_MODEM_RXRESTART_RXRESTARTMALATCHSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTMALATCHSEL_RE_PRE_DET (_MODEM_RXRESTART_RXRESTARTMALATCHSEL_RE_PRE_DET << 8) /**< Shifted mode RE_PRE_DET for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTMALATCHSEL_RE_SYNC_DET (_MODEM_RXRESTART_RXRESTARTMALATCHSEL_RE_SYNC_DET << 8) /**< Shifted mode RE_SYNC_DET for MODEM_RXRESTART*/
+#define MODEM_RXRESTART_RXRESTARTMALATCHSEL_EITHER1 (_MODEM_RXRESTART_RXRESTARTMALATCHSEL_EITHER1 << 8) /**< Shifted mode EITHER1 for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTMALATCHSEL_EITHER2 (_MODEM_RXRESTART_RXRESTARTMALATCHSEL_EITHER2 << 8) /**< Shifted mode EITHER2 for MODEM_RXRESTART */
+#define _MODEM_RXRESTART_RXRESTARTMACOMPENSEL_SHIFT 10 /**< Shift value for MODEM_RXRESTARTMACOMPENSEL */
+#define _MODEM_RXRESTART_RXRESTARTMACOMPENSEL_MASK 0xC00UL /**< Bit mask for MODEM_RXRESTARTMACOMPENSEL */
+#define _MODEM_RXRESTART_RXRESTARTMACOMPENSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for MODEM_RXRESTART */
+#define _MODEM_RXRESTART_RXRESTARTMACOMPENSEL_PRE_DET 0x00000000UL /**< Mode PRE_DET for MODEM_RXRESTART */
+#define _MODEM_RXRESTART_RXRESTARTMACOMPENSEL_FRAME_SYNC_DET 0x00000001UL /**< Mode FRAME_SYNC_DET for MODEM_RXRESTART */
+#define _MODEM_RXRESTART_RXRESTARTMACOMPENSEL_BOTH1 0x00000002UL /**< Mode BOTH1 for MODEM_RXRESTART */
+#define _MODEM_RXRESTART_RXRESTARTMACOMPENSEL_BOTH2 0x00000003UL /**< Mode BOTH2 for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTMACOMPENSEL_DEFAULT (_MODEM_RXRESTART_RXRESTARTMACOMPENSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTMACOMPENSEL_PRE_DET (_MODEM_RXRESTART_RXRESTARTMACOMPENSEL_PRE_DET << 10) /**< Shifted mode PRE_DET for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTMACOMPENSEL_FRAME_SYNC_DET (_MODEM_RXRESTART_RXRESTARTMACOMPENSEL_FRAME_SYNC_DET << 10) /**< Shifted mode FRAME_SYNC_DET for MODEM_RXRESTART*/
+#define MODEM_RXRESTART_RXRESTARTMACOMPENSEL_BOTH1 (_MODEM_RXRESTART_RXRESTARTMACOMPENSEL_BOTH1 << 10) /**< Shifted mode BOTH1 for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTMACOMPENSEL_BOTH2 (_MODEM_RXRESTART_RXRESTARTMACOMPENSEL_BOTH2 << 10) /**< Shifted mode BOTH2 for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTMATAP (0x1UL << 12) /**< Number of taps for the MA filter */
+#define _MODEM_RXRESTART_RXRESTARTMATAP_SHIFT 12 /**< Shift value for MODEM_RXRESTARTMATAP */
+#define _MODEM_RXRESTART_RXRESTARTMATAP_MASK 0x1000UL /**< Bit mask for MODEM_RXRESTARTMATAP */
+#define _MODEM_RXRESTART_RXRESTARTMATAP_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_RXRESTART */
+#define _MODEM_RXRESTART_RXRESTARTMATAP_TAPS4 0x00000000UL /**< Mode TAPS4 for MODEM_RXRESTART */
+#define _MODEM_RXRESTART_RXRESTARTMATAP_TAPS8 0x00000001UL /**< Mode TAPS8 for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTMATAP_DEFAULT (_MODEM_RXRESTART_RXRESTARTMATAP_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTMATAP_TAPS4 (_MODEM_RXRESTART_RXRESTARTMATAP_TAPS4 << 12) /**< Shifted mode TAPS4 for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTMATAP_TAPS8 (_MODEM_RXRESTART_RXRESTARTMATAP_TAPS8 << 12) /**< Shifted mode TAPS8 for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTB4PREDET (0x1UL << 16) /**< whether to restart RX before pre det */
+#define _MODEM_RXRESTART_RXRESTARTB4PREDET_SHIFT 16 /**< Shift value for MODEM_RXRESTARTB4PREDET */
+#define _MODEM_RXRESTART_RXRESTARTB4PREDET_MASK 0x10000UL /**< Bit mask for MODEM_RXRESTARTB4PREDET */
+#define _MODEM_RXRESTART_RXRESTARTB4PREDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_RXRESTART */
+#define MODEM_RXRESTART_RXRESTARTB4PREDET_DEFAULT (_MODEM_RXRESTART_RXRESTARTB4PREDET_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_RXRESTART */
+#define MODEM_RXRESTART_ANTSWRSTFLTTDIS (0x1UL << 30) /**< ANT SW RESET Filter Disable */
+#define _MODEM_RXRESTART_ANTSWRSTFLTTDIS_SHIFT 30 /**< Shift value for MODEM_ANTSWRSTFLTTDIS */
+#define _MODEM_RXRESTART_ANTSWRSTFLTTDIS_MASK 0x40000000UL /**< Bit mask for MODEM_ANTSWRSTFLTTDIS */
+#define _MODEM_RXRESTART_ANTSWRSTFLTTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_RXRESTART */
+#define MODEM_RXRESTART_ANTSWRSTFLTTDIS_DEFAULT (_MODEM_RXRESTART_ANTSWRSTFLTTDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_RXRESTART */
+#define MODEM_RXRESTART_FLTRSTEN (0x1UL << 31) /**< RX Chain Filter reset enable */
+#define _MODEM_RXRESTART_FLTRSTEN_SHIFT 31 /**< Shift value for MODEM_FLTRSTEN */
+#define _MODEM_RXRESTART_FLTRSTEN_MASK 0x80000000UL /**< Bit mask for MODEM_FLTRSTEN */
+#define _MODEM_RXRESTART_FLTRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_RXRESTART */
+#define MODEM_RXRESTART_FLTRSTEN_DEFAULT (_MODEM_RXRESTART_FLTRSTEN_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_RXRESTART */
+
+/* Bit fields for MODEM SQ */
+#define _MODEM_SQ_RESETVALUE 0x00000000UL /**< Default value for MODEM_SQ */
+#define _MODEM_SQ_MASK 0xFFFF0003UL /**< Mask for MODEM_SQ */
+#define MODEM_SQ_SQEN (0x1UL << 0) /**< SQ enable */
+#define _MODEM_SQ_SQEN_SHIFT 0 /**< Shift value for MODEM_SQEN */
+#define _MODEM_SQ_SQEN_MASK 0x1UL /**< Bit mask for MODEM_SQEN */
+#define _MODEM_SQ_SQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SQ */
+#define MODEM_SQ_SQEN_DEFAULT (_MODEM_SQ_SQEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SQ */
+#define MODEM_SQ_SQSWRST (0x1UL << 1) /**< SQ hold demod */
+#define _MODEM_SQ_SQSWRST_SHIFT 1 /**< Shift value for MODEM_SQSWRST */
+#define _MODEM_SQ_SQSWRST_MASK 0x2UL /**< Bit mask for MODEM_SQSWRST */
+#define _MODEM_SQ_SQSWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SQ */
+#define MODEM_SQ_SQSWRST_DEFAULT (_MODEM_SQ_SQSWRST_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_SQ */
+#define _MODEM_SQ_SQTIMOUT_SHIFT 16 /**< Shift value for MODEM_SQTIMOUT */
+#define _MODEM_SQ_SQTIMOUT_MASK 0xFFFF0000UL /**< Bit mask for MODEM_SQTIMOUT */
+#define _MODEM_SQ_SQTIMOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SQ */
+#define MODEM_SQ_SQTIMOUT_DEFAULT (_MODEM_SQ_SQTIMOUT_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SQ */
+
+/* Bit fields for MODEM SQEXT */
+#define _MODEM_SQEXT_RESETVALUE 0x00000000UL /**< Default value for MODEM_SQEXT */
+#define _MODEM_SQEXT_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SQEXT */
+#define _MODEM_SQEXT_SQSTG2TIMOUT_SHIFT 0 /**< Shift value for MODEM_SQSTG2TIMOUT */
+#define _MODEM_SQEXT_SQSTG2TIMOUT_MASK 0xFFFFUL /**< Bit mask for MODEM_SQSTG2TIMOUT */
+#define _MODEM_SQEXT_SQSTG2TIMOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SQEXT */
+#define MODEM_SQEXT_SQSTG2TIMOUT_DEFAULT (_MODEM_SQEXT_SQSTG2TIMOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SQEXT */
+#define _MODEM_SQEXT_SQSTG3TIMOUT_SHIFT 16 /**< Shift value for MODEM_SQSTG3TIMOUT */
+#define _MODEM_SQEXT_SQSTG3TIMOUT_MASK 0xFFFF0000UL /**< Bit mask for MODEM_SQSTG3TIMOUT */
+#define _MODEM_SQEXT_SQSTG3TIMOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SQEXT */
+#define MODEM_SQEXT_SQSTG3TIMOUT_DEFAULT (_MODEM_SQEXT_SQSTG3TIMOUT_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SQEXT */
+
+/* Bit fields for MODEM SQI */
+#define _MODEM_SQI_RESETVALUE 0x00000000UL /**< Default value for MODEM_SQI */
+#define _MODEM_SQI_MASK 0x00FF0001UL /**< Mask for MODEM_SQI */
+#define MODEM_SQI_SQISELECT (0x1UL << 0) /**< SQI selection bit */
+#define _MODEM_SQI_SQISELECT_SHIFT 0 /**< Shift value for MODEM_SQISELECT */
+#define _MODEM_SQI_SQISELECT_MASK 0x1UL /**< Bit mask for MODEM_SQISELECT */
+#define _MODEM_SQI_SQISELECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SQI */
+#define _MODEM_SQI_SQISELECT_CORR 0x00000000UL /**< Mode CORR for MODEM_SQI */
+#define _MODEM_SQI_SQISELECT_ERROR 0x00000001UL /**< Mode ERROR for MODEM_SQI */
+#define MODEM_SQI_SQISELECT_DEFAULT (_MODEM_SQI_SQISELECT_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SQI */
+#define MODEM_SQI_SQISELECT_CORR (_MODEM_SQI_SQISELECT_CORR << 0) /**< Shifted mode CORR for MODEM_SQI */
+#define MODEM_SQI_SQISELECT_ERROR (_MODEM_SQI_SQISELECT_ERROR << 0) /**< Shifted mode ERROR for MODEM_SQI */
+#define _MODEM_SQI_CHIPERROR_SHIFT 16 /**< Shift value for MODEM_CHIPERROR */
+#define _MODEM_SQI_CHIPERROR_MASK 0xFF0000UL /**< Bit mask for MODEM_CHIPERROR */
+#define _MODEM_SQI_CHIPERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SQI */
+#define MODEM_SQI_CHIPERROR_DEFAULT (_MODEM_SQI_CHIPERROR_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SQI */
+
+/* Bit fields for MODEM ANTDIVCTRL */
+#define _MODEM_ANTDIVCTRL_RESETVALUE 0x00000000UL /**< Default value for MODEM_ANTDIVCTRL */
+#define _MODEM_ANTDIVCTRL_MASK 0x000007FFUL /**< Mask for MODEM_ANTDIVCTRL */
+#define _MODEM_ANTDIVCTRL_ADPRETHRESH_SHIFT 0 /**< Shift value for MODEM_ADPRETHRESH */
+#define _MODEM_ANTDIVCTRL_ADPRETHRESH_MASK 0xFFUL /**< Bit mask for MODEM_ADPRETHRESH */
+#define _MODEM_ANTDIVCTRL_ADPRETHRESH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANTDIVCTRL */
+#define MODEM_ANTDIVCTRL_ADPRETHRESH_DEFAULT (_MODEM_ANTDIVCTRL_ADPRETHRESH_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ANTDIVCTRL */
+#define MODEM_ANTDIVCTRL_ENADPRETHRESH (0x1UL << 8) /**< Enable Preamble threshold */
+#define _MODEM_ANTDIVCTRL_ENADPRETHRESH_SHIFT 8 /**< Shift value for MODEM_ENADPRETHRESH */
+#define _MODEM_ANTDIVCTRL_ENADPRETHRESH_MASK 0x100UL /**< Bit mask for MODEM_ENADPRETHRESH */
+#define _MODEM_ANTDIVCTRL_ENADPRETHRESH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANTDIVCTRL */
+#define _MODEM_ANTDIVCTRL_ENADPRETHRESH_DISABLE 0x00000000UL /**< Mode DISABLE for MODEM_ANTDIVCTRL */
+#define _MODEM_ANTDIVCTRL_ENADPRETHRESH_ENABLE 0x00000001UL /**< Mode ENABLE for MODEM_ANTDIVCTRL */
+#define MODEM_ANTDIVCTRL_ENADPRETHRESH_DEFAULT (_MODEM_ANTDIVCTRL_ENADPRETHRESH_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_ANTDIVCTRL */
+#define MODEM_ANTDIVCTRL_ENADPRETHRESH_DISABLE (_MODEM_ANTDIVCTRL_ENADPRETHRESH_DISABLE << 8) /**< Shifted mode DISABLE for MODEM_ANTDIVCTRL */
+#define MODEM_ANTDIVCTRL_ENADPRETHRESH_ENABLE (_MODEM_ANTDIVCTRL_ENADPRETHRESH_ENABLE << 8) /**< Shifted mode ENABLE for MODEM_ANTDIVCTRL */
+#define MODEM_ANTDIVCTRL_ANTDIVDISCCA (0x1UL << 9) /**< Antenna switch disable for CSMA */
+#define _MODEM_ANTDIVCTRL_ANTDIVDISCCA_SHIFT 9 /**< Shift value for MODEM_ANTDIVDISCCA */
+#define _MODEM_ANTDIVCTRL_ANTDIVDISCCA_MASK 0x200UL /**< Bit mask for MODEM_ANTDIVDISCCA */
+#define _MODEM_ANTDIVCTRL_ANTDIVDISCCA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANTDIVCTRL */
+#define MODEM_ANTDIVCTRL_ANTDIVDISCCA_DEFAULT (_MODEM_ANTDIVCTRL_ANTDIVDISCCA_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_ANTDIVCTRL */
+#define MODEM_ANTDIVCTRL_ANTDIVSELCCA (0x1UL << 10) /**< Antenna switch selection for CSMA */
+#define _MODEM_ANTDIVCTRL_ANTDIVSELCCA_SHIFT 10 /**< Shift value for MODEM_ANTDIVSELCCA */
+#define _MODEM_ANTDIVCTRL_ANTDIVSELCCA_MASK 0x400UL /**< Bit mask for MODEM_ANTDIVSELCCA */
+#define _MODEM_ANTDIVCTRL_ANTDIVSELCCA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANTDIVCTRL */
+#define MODEM_ANTDIVCTRL_ANTDIVSELCCA_DEFAULT (_MODEM_ANTDIVCTRL_ANTDIVSELCCA_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_ANTDIVCTRL */
+
+/* Bit fields for MODEM ANTDIVFW */
+#define _MODEM_ANTDIVFW_RESETVALUE 0x00000000UL /**< Default value for MODEM_ANTDIVFW */
+#define _MODEM_ANTDIVFW_MASK 0x80000003UL /**< Mask for MODEM_ANTDIVFW */
+#define MODEM_ANTDIVFW_FWSELANT (0x1UL << 0) /**< FW antenna selection */
+#define _MODEM_ANTDIVFW_FWSELANT_SHIFT 0 /**< Shift value for MODEM_FWSELANT */
+#define _MODEM_ANTDIVFW_FWSELANT_MASK 0x1UL /**< Bit mask for MODEM_FWSELANT */
+#define _MODEM_ANTDIVFW_FWSELANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANTDIVFW */
+#define MODEM_ANTDIVFW_FWSELANT_DEFAULT (_MODEM_ANTDIVFW_FWSELANT_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ANTDIVFW */
+#define MODEM_ANTDIVFW_FWANTSWCMD (0x1UL << 1) /**< FW Antenna SW cmd */
+#define _MODEM_ANTDIVFW_FWANTSWCMD_SHIFT 1 /**< Shift value for MODEM_FWANTSWCMD */
+#define _MODEM_ANTDIVFW_FWANTSWCMD_MASK 0x2UL /**< Bit mask for MODEM_FWANTSWCMD */
+#define _MODEM_ANTDIVFW_FWANTSWCMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANTDIVFW */
+#define MODEM_ANTDIVFW_FWANTSWCMD_DEFAULT (_MODEM_ANTDIVFW_FWANTSWCMD_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_ANTDIVFW */
+#define MODEM_ANTDIVFW_FWANTDIVEN (0x1UL << 31) /**< Enable FW ANT-DIV mode */
+#define _MODEM_ANTDIVFW_FWANTDIVEN_SHIFT 31 /**< Shift value for MODEM_FWANTDIVEN */
+#define _MODEM_ANTDIVFW_FWANTDIVEN_MASK 0x80000000UL /**< Bit mask for MODEM_FWANTDIVEN */
+#define _MODEM_ANTDIVFW_FWANTDIVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ANTDIVFW */
+#define MODEM_ANTDIVFW_FWANTDIVEN_DEFAULT (_MODEM_ANTDIVFW_FWANTDIVEN_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_ANTDIVFW */
+
+/* Bit fields for MODEM PHDMODANTDIV */
+#define _MODEM_PHDMODANTDIV_RESETVALUE 0x0000000FUL /**< Default value for MODEM_PHDMODANTDIV */
+#define _MODEM_PHDMODANTDIV_MASK 0x40FF1FFFUL /**< Mask for MODEM_PHDMODANTDIV */
+#define _MODEM_PHDMODANTDIV_ANTWAIT_SHIFT 0 /**< Shift value for MODEM_ANTWAIT */
+#define _MODEM_PHDMODANTDIV_ANTWAIT_MASK 0x1FUL /**< Bit mask for MODEM_ANTWAIT */
+#define _MODEM_PHDMODANTDIV_ANTWAIT_DEFAULT 0x0000000FUL /**< Mode DEFAULT for MODEM_PHDMODANTDIV */
+#define MODEM_PHDMODANTDIV_ANTWAIT_DEFAULT (_MODEM_PHDMODANTDIV_ANTWAIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_PHDMODANTDIV */
+#define _MODEM_PHDMODANTDIV_SKIPRSSITHD_SHIFT 5 /**< Shift value for MODEM_SKIPRSSITHD */
+#define _MODEM_PHDMODANTDIV_SKIPRSSITHD_MASK 0x1FE0UL /**< Bit mask for MODEM_SKIPRSSITHD */
+#define _MODEM_PHDMODANTDIV_SKIPRSSITHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHDMODANTDIV */
+#define MODEM_PHDMODANTDIV_SKIPRSSITHD_DEFAULT (_MODEM_PHDMODANTDIV_SKIPRSSITHD_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_PHDMODANTDIV */
+#define _MODEM_PHDMODANTDIV_SKIPCORRTHD_SHIFT 16 /**< Shift value for MODEM_SKIPCORRTHD */
+#define _MODEM_PHDMODANTDIV_SKIPCORRTHD_MASK 0xFF0000UL /**< Bit mask for MODEM_SKIPCORRTHD */
+#define _MODEM_PHDMODANTDIV_SKIPCORRTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHDMODANTDIV */
+#define MODEM_PHDMODANTDIV_SKIPCORRTHD_DEFAULT (_MODEM_PHDMODANTDIV_SKIPCORRTHD_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_PHDMODANTDIV */
+#define MODEM_PHDMODANTDIV_SKIP2ANT (0x1UL << 30) /**< SKIP 2th ANTENNA Evaluate */
+#define _MODEM_PHDMODANTDIV_SKIP2ANT_SHIFT 30 /**< Shift value for MODEM_SKIP2ANT */
+#define _MODEM_PHDMODANTDIV_SKIP2ANT_MASK 0x40000000UL /**< Bit mask for MODEM_SKIP2ANT */
+#define _MODEM_PHDMODANTDIV_SKIP2ANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHDMODANTDIV */
+#define MODEM_PHDMODANTDIV_SKIP2ANT_DEFAULT (_MODEM_PHDMODANTDIV_SKIP2ANT_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_PHDMODANTDIV */
+
+/* Bit fields for MODEM PHANTDECSION */
+#define _MODEM_PHANTDECSION_RESETVALUE 0x00000000UL /**< Default value for MODEM_PHANTDECSION */
+#define _MODEM_PHANTDECSION_MASK 0xF007FFFFUL /**< Mask for MODEM_PHANTDECSION */
+#define _MODEM_PHANTDECSION_CORRANDDIVTHD_SHIFT 0 /**< Shift value for MODEM_CORRANDDIVTHD */
+#define _MODEM_PHANTDECSION_CORRANDDIVTHD_MASK 0x3FFUL /**< Bit mask for MODEM_CORRANDDIVTHD */
+#define _MODEM_PHANTDECSION_CORRANDDIVTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHANTDECSION */
+#define MODEM_PHANTDECSION_CORRANDDIVTHD_DEFAULT (_MODEM_PHANTDECSION_CORRANDDIVTHD_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_PHANTDECSION */
+#define _MODEM_PHANTDECSION_RSSIANDDIVTHD_SHIFT 10 /**< Shift value for MODEM_RSSIANDDIVTHD */
+#define _MODEM_PHANTDECSION_RSSIANDDIVTHD_MASK 0x7FC00UL /**< Bit mask for MODEM_RSSIANDDIVTHD */
+#define _MODEM_PHANTDECSION_RSSIANDDIVTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHANTDECSION */
+#define MODEM_PHANTDECSION_RSSIANDDIVTHD_DEFAULT (_MODEM_PHANTDECSION_RSSIANDDIVTHD_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_PHANTDECSION */
+#define MODEM_PHANTDECSION_RSSICORR0 (0x1UL << 28) /**< RSSI-CORR Selection in Region0 */
+#define _MODEM_PHANTDECSION_RSSICORR0_SHIFT 28 /**< Shift value for MODEM_RSSICORR0 */
+#define _MODEM_PHANTDECSION_RSSICORR0_MASK 0x10000000UL /**< Bit mask for MODEM_RSSICORR0 */
+#define _MODEM_PHANTDECSION_RSSICORR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHANTDECSION */
+#define MODEM_PHANTDECSION_RSSICORR0_DEFAULT (_MODEM_PHANTDECSION_RSSICORR0_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_PHANTDECSION */
+#define MODEM_PHANTDECSION_RSSICORR1 (0x1UL << 29) /**< RSSI-CORR Selection in Region1 */
+#define _MODEM_PHANTDECSION_RSSICORR1_SHIFT 29 /**< Shift value for MODEM_RSSICORR1 */
+#define _MODEM_PHANTDECSION_RSSICORR1_MASK 0x20000000UL /**< Bit mask for MODEM_RSSICORR1 */
+#define _MODEM_PHANTDECSION_RSSICORR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHANTDECSION */
+#define MODEM_PHANTDECSION_RSSICORR1_DEFAULT (_MODEM_PHANTDECSION_RSSICORR1_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_PHANTDECSION */
+#define MODEM_PHANTDECSION_RSSICORR2 (0x1UL << 30) /**< RSSI-CORR Selection in Region2 */
+#define _MODEM_PHANTDECSION_RSSICORR2_SHIFT 30 /**< Shift value for MODEM_RSSICORR2 */
+#define _MODEM_PHANTDECSION_RSSICORR2_MASK 0x40000000UL /**< Bit mask for MODEM_RSSICORR2 */
+#define _MODEM_PHANTDECSION_RSSICORR2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHANTDECSION */
+#define MODEM_PHANTDECSION_RSSICORR2_DEFAULT (_MODEM_PHANTDECSION_RSSICORR2_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_PHANTDECSION */
+#define MODEM_PHANTDECSION_RSSICORR3 (0x1UL << 31) /**< RSSI-CORR Selection in Region3 */
+#define _MODEM_PHANTDECSION_RSSICORR3_SHIFT 31 /**< Shift value for MODEM_RSSICORR3 */
+#define _MODEM_PHANTDECSION_RSSICORR3_MASK 0x80000000UL /**< Bit mask for MODEM_RSSICORR3 */
+#define _MODEM_PHANTDECSION_RSSICORR3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHANTDECSION */
+#define MODEM_PHANTDECSION_RSSICORR3_DEFAULT (_MODEM_PHANTDECSION_RSSICORR3_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_PHANTDECSION */
+
+/* Bit fields for MODEM PHDMODCTRL */
+#define _MODEM_PHDMODCTRL_RESETVALUE 0x01DF0004UL /**< Default value for MODEM_PHDMODCTRL */
+#define _MODEM_PHDMODCTRL_MASK 0xFFFFFFFFUL /**< Mask for MODEM_PHDMODCTRL */
+#define _MODEM_PHDMODCTRL_PMDETTHD_SHIFT 0 /**< Shift value for MODEM_PMDETTHD */
+#define _MODEM_PHDMODCTRL_PMDETTHD_MASK 0x1FUL /**< Bit mask for MODEM_PMDETTHD */
+#define _MODEM_PHDMODCTRL_PMDETTHD_DEFAULT 0x00000004UL /**< Mode DEFAULT for MODEM_PHDMODCTRL */
+#define MODEM_PHDMODCTRL_PMDETTHD_DEFAULT (_MODEM_PHDMODCTRL_PMDETTHD_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_PHDMODCTRL */
+#define _MODEM_PHDMODCTRL_PMTIMLOSTHD_SHIFT 5 /**< Shift value for MODEM_PMTIMLOSTHD */
+#define _MODEM_PHDMODCTRL_PMTIMLOSTHD_MASK 0x1FE0UL /**< Bit mask for MODEM_PMTIMLOSTHD */
+#define _MODEM_PHDMODCTRL_PMTIMLOSTHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHDMODCTRL */
+#define MODEM_PHDMODCTRL_PMTIMLOSTHD_DEFAULT (_MODEM_PHDMODCTRL_PMTIMLOSTHD_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_PHDMODCTRL */
+#define MODEM_PHDMODCTRL_PMTIMLOSEN (0x1UL << 13) /**< Preamble timing loss detection */
+#define _MODEM_PHDMODCTRL_PMTIMLOSEN_SHIFT 13 /**< Shift value for MODEM_PMTIMLOSEN */
+#define _MODEM_PHDMODCTRL_PMTIMLOSEN_MASK 0x2000UL /**< Bit mask for MODEM_PMTIMLOSEN */
+#define _MODEM_PHDMODCTRL_PMTIMLOSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHDMODCTRL */
+#define MODEM_PHDMODCTRL_PMTIMLOSEN_DEFAULT (_MODEM_PHDMODCTRL_PMTIMLOSEN_DEFAULT << 13) /**< Shifted mode DEFAULT for MODEM_PHDMODCTRL */
+#define MODEM_PHDMODCTRL_RSSIFLTBYP (0x1UL << 14) /**< Bypass RSSI Filering */
+#define _MODEM_PHDMODCTRL_RSSIFLTBYP_SHIFT 14 /**< Shift value for MODEM_RSSIFLTBYP */
+#define _MODEM_PHDMODCTRL_RSSIFLTBYP_MASK 0x4000UL /**< Bit mask for MODEM_RSSIFLTBYP */
+#define _MODEM_PHDMODCTRL_RSSIFLTBYP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHDMODCTRL */
+#define MODEM_PHDMODCTRL_RSSIFLTBYP_DEFAULT (_MODEM_PHDMODCTRL_RSSIFLTBYP_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_PHDMODCTRL */
+#define MODEM_PHDMODCTRL_PMDETEN (0x1UL << 15) /**< PREAMBLE DET */
+#define _MODEM_PHDMODCTRL_PMDETEN_SHIFT 15 /**< Shift value for MODEM_PMDETEN */
+#define _MODEM_PHDMODCTRL_PMDETEN_MASK 0x8000UL /**< Bit mask for MODEM_PMDETEN */
+#define _MODEM_PHDMODCTRL_PMDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHDMODCTRL */
+#define MODEM_PHDMODCTRL_PMDETEN_DEFAULT (_MODEM_PHDMODCTRL_PMDETEN_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_PHDMODCTRL */
+#define _MODEM_PHDMODCTRL_REMODOSR_SHIFT 16 /**< Shift value for MODEM_REMODOSR */
+#define _MODEM_PHDMODCTRL_REMODOSR_MASK 0x3F0000UL /**< Bit mask for MODEM_REMODOSR */
+#define _MODEM_PHDMODCTRL_REMODOSR_DEFAULT 0x0000001FUL /**< Mode DEFAULT for MODEM_PHDMODCTRL */
+#define MODEM_PHDMODCTRL_REMODOSR_DEFAULT (_MODEM_PHDMODCTRL_REMODOSR_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_PHDMODCTRL */
+#define _MODEM_PHDMODCTRL_REMODDWN_SHIFT 22 /**< Shift value for MODEM_REMODDWN */
+#define _MODEM_PHDMODCTRL_REMODDWN_MASK 0x3C00000UL /**< Bit mask for MODEM_REMODDWN */
+#define _MODEM_PHDMODCTRL_REMODDWN_DEFAULT 0x00000007UL /**< Mode DEFAULT for MODEM_PHDMODCTRL */
+#define MODEM_PHDMODCTRL_REMODDWN_DEFAULT (_MODEM_PHDMODCTRL_REMODDWN_DEFAULT << 22) /**< Shifted mode DEFAULT for MODEM_PHDMODCTRL */
+#define _MODEM_PHDMODCTRL_REMODOUTSEL_SHIFT 26 /**< Shift value for MODEM_REMODOUTSEL */
+#define _MODEM_PHDMODCTRL_REMODOUTSEL_MASK 0xC000000UL /**< Bit mask for MODEM_REMODOUTSEL */
+#define _MODEM_PHDMODCTRL_REMODOUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHDMODCTRL */
+#define MODEM_PHDMODCTRL_REMODOUTSEL_DEFAULT (_MODEM_PHDMODCTRL_REMODOUTSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for MODEM_PHDMODCTRL */
+#define MODEM_PHDMODCTRL_REMODEN (0x1UL << 28) /**< REMOD ENABLE */
+#define _MODEM_PHDMODCTRL_REMODEN_SHIFT 28 /**< Shift value for MODEM_REMODEN */
+#define _MODEM_PHDMODCTRL_REMODEN_MASK 0x10000000UL /**< Bit mask for MODEM_REMODEN */
+#define _MODEM_PHDMODCTRL_REMODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHDMODCTRL */
+#define MODEM_PHDMODCTRL_REMODEN_DEFAULT (_MODEM_PHDMODCTRL_REMODEN_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_PHDMODCTRL */
+#define MODEM_PHDMODCTRL_BCRDETECTOR (0x1UL << 29) /**< Enbale BCRDMOD Dtetector ONLY */
+#define _MODEM_PHDMODCTRL_BCRDETECTOR_SHIFT 29 /**< Shift value for MODEM_BCRDETECTOR */
+#define _MODEM_PHDMODCTRL_BCRDETECTOR_MASK 0x20000000UL /**< Bit mask for MODEM_BCRDETECTOR */
+#define _MODEM_PHDMODCTRL_BCRDETECTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHDMODCTRL */
+#define MODEM_PHDMODCTRL_BCRDETECTOR_DEFAULT (_MODEM_PHDMODCTRL_BCRDETECTOR_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_PHDMODCTRL */
+#define MODEM_PHDMODCTRL_BCRTRECSCONC (0x1UL << 30) /**< BCR/LEGACY CONCURRENT MODE */
+#define _MODEM_PHDMODCTRL_BCRTRECSCONC_SHIFT 30 /**< Shift value for MODEM_BCRTRECSCONC */
+#define _MODEM_PHDMODCTRL_BCRTRECSCONC_MASK 0x40000000UL /**< Bit mask for MODEM_BCRTRECSCONC */
+#define _MODEM_PHDMODCTRL_BCRTRECSCONC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHDMODCTRL */
+#define MODEM_PHDMODCTRL_BCRTRECSCONC_DEFAULT (_MODEM_PHDMODCTRL_BCRTRECSCONC_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_PHDMODCTRL */
+#define MODEM_PHDMODCTRL_BCRLEGACYCONC (0x1UL << 31) /**< BCR/TRECS CONCURRENT MODE */
+#define _MODEM_PHDMODCTRL_BCRLEGACYCONC_SHIFT 31 /**< Shift value for MODEM_BCRLEGACYCONC */
+#define _MODEM_PHDMODCTRL_BCRLEGACYCONC_MASK 0x80000000UL /**< Bit mask for MODEM_BCRLEGACYCONC */
+#define _MODEM_PHDMODCTRL_BCRLEGACYCONC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_PHDMODCTRL */
+#define MODEM_PHDMODCTRL_BCRLEGACYCONC_DEFAULT (_MODEM_PHDMODCTRL_BCRLEGACYCONC_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_PHDMODCTRL */
+
+/* Bit fields for MODEM SICTRL0 */
+#define _MODEM_SICTRL0_RESETVALUE 0x00000000UL /**< Default value for MODEM_SICTRL0 */
+#define _MODEM_SICTRL0_MASK 0x3FFFFFFFUL /**< Mask for MODEM_SICTRL0 */
+#define _MODEM_SICTRL0_MODE_SHIFT 0 /**< Shift value for MODEM_MODE */
+#define _MODEM_SICTRL0_MODE_MASK 0x3UL /**< Bit mask for MODEM_MODE */
+#define _MODEM_SICTRL0_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL0 */
+#define _MODEM_SICTRL0_MODE_DISABLE 0x00000000UL /**< Mode DISABLE for MODEM_SICTRL0 */
+#define _MODEM_SICTRL0_MODE_ZB 0x00000001UL /**< Mode ZB for MODEM_SICTRL0 */
+#define _MODEM_SICTRL0_MODE_BLE2 0x00000002UL /**< Mode BLE2 for MODEM_SICTRL0 */
+#define _MODEM_SICTRL0_MODE_BLE1 0x00000003UL /**< Mode BLE1 for MODEM_SICTRL0 */
+#define MODEM_SICTRL0_MODE_DEFAULT (_MODEM_SICTRL0_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SICTRL0 */
+#define MODEM_SICTRL0_MODE_DISABLE (_MODEM_SICTRL0_MODE_DISABLE << 0) /**< Shifted mode DISABLE for MODEM_SICTRL0 */
+#define MODEM_SICTRL0_MODE_ZB (_MODEM_SICTRL0_MODE_ZB << 0) /**< Shifted mode ZB for MODEM_SICTRL0 */
+#define MODEM_SICTRL0_MODE_BLE2 (_MODEM_SICTRL0_MODE_BLE2 << 0) /**< Shifted mode BLE2 for MODEM_SICTRL0 */
+#define MODEM_SICTRL0_MODE_BLE1 (_MODEM_SICTRL0_MODE_BLE1 << 0) /**< Shifted mode BLE1 for MODEM_SICTRL0 */
+#define _MODEM_SICTRL0_NOISETHRESH_SHIFT 2 /**< Shift value for MODEM_NOISETHRESH */
+#define _MODEM_SICTRL0_NOISETHRESH_MASK 0x3FCUL /**< Bit mask for MODEM_NOISETHRESH */
+#define _MODEM_SICTRL0_NOISETHRESH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL0 */
+#define MODEM_SICTRL0_NOISETHRESH_DEFAULT (_MODEM_SICTRL0_NOISETHRESH_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_SICTRL0 */
+#define _MODEM_SICTRL0_PEAKNUMTHRESHLW_SHIFT 10 /**< Shift value for MODEM_PEAKNUMTHRESHLW */
+#define _MODEM_SICTRL0_PEAKNUMTHRESHLW_MASK 0x7C00UL /**< Bit mask for MODEM_PEAKNUMTHRESHLW */
+#define _MODEM_SICTRL0_PEAKNUMTHRESHLW_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL0 */
+#define MODEM_SICTRL0_PEAKNUMTHRESHLW_DEFAULT (_MODEM_SICTRL0_PEAKNUMTHRESHLW_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_SICTRL0 */
+#define _MODEM_SICTRL0_PEAKNUMTHRESHSW_SHIFT 15 /**< Shift value for MODEM_PEAKNUMTHRESHSW */
+#define _MODEM_SICTRL0_PEAKNUMTHRESHSW_MASK 0x38000UL /**< Bit mask for MODEM_PEAKNUMTHRESHSW */
+#define _MODEM_SICTRL0_PEAKNUMTHRESHSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL0 */
+#define MODEM_SICTRL0_PEAKNUMTHRESHSW_DEFAULT (_MODEM_SICTRL0_PEAKNUMTHRESHSW_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_SICTRL0 */
+#define _MODEM_SICTRL0_SMALLSAMPLETHRESH_SHIFT 18 /**< Shift value for MODEM_SMALLSAMPLETHRESH */
+#define _MODEM_SICTRL0_SMALLSAMPLETHRESH_MASK 0x7C0000UL /**< Bit mask for MODEM_SMALLSAMPLETHRESH */
+#define _MODEM_SICTRL0_SMALLSAMPLETHRESH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL0 */
+#define MODEM_SICTRL0_SMALLSAMPLETHRESH_DEFAULT (_MODEM_SICTRL0_SMALLSAMPLETHRESH_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_SICTRL0 */
+#define _MODEM_SICTRL0_FREQNOMINAL_SHIFT 23 /**< Shift value for MODEM_FREQNOMINAL */
+#define _MODEM_SICTRL0_FREQNOMINAL_MASK 0x3F800000UL /**< Bit mask for MODEM_FREQNOMINAL */
+#define _MODEM_SICTRL0_FREQNOMINAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL0 */
+#define MODEM_SICTRL0_FREQNOMINAL_DEFAULT (_MODEM_SICTRL0_FREQNOMINAL_DEFAULT << 23) /**< Shifted mode DEFAULT for MODEM_SICTRL0 */
+
+/* Bit fields for MODEM SICTRL1 */
+#define _MODEM_SICTRL1_RESETVALUE 0x00000000UL /**< Default value for MODEM_SICTRL1 */
+#define _MODEM_SICTRL1_MASK 0xFFFFFFFFUL /**< Mask for MODEM_SICTRL1 */
+#define _MODEM_SICTRL1_SUPERCHIPTOLERANCE_SHIFT 0 /**< Shift value for MODEM_SUPERCHIPTOLERANCE */
+#define _MODEM_SICTRL1_SUPERCHIPTOLERANCE_MASK 0x1FUL /**< Bit mask for MODEM_SUPERCHIPTOLERANCE */
+#define _MODEM_SICTRL1_SUPERCHIPTOLERANCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL1 */
+#define MODEM_SICTRL1_SUPERCHIPTOLERANCE_DEFAULT (_MODEM_SICTRL1_SUPERCHIPTOLERANCE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SICTRL1 */
+#define _MODEM_SICTRL1_SUPERCHIPMEDIAN_SHIFT 5 /**< Shift value for MODEM_SUPERCHIPMEDIAN */
+#define _MODEM_SICTRL1_SUPERCHIPMEDIAN_MASK 0xFE0UL /**< Bit mask for MODEM_SUPERCHIPMEDIAN */
+#define _MODEM_SICTRL1_SUPERCHIPMEDIAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL1 */
+#define MODEM_SICTRL1_SUPERCHIPMEDIAN_DEFAULT (_MODEM_SICTRL1_SUPERCHIPMEDIAN_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_SICTRL1 */
+#define _MODEM_SICTRL1_CORRTHRESH_SHIFT 12 /**< Shift value for MODEM_CORRTHRESH */
+#define _MODEM_SICTRL1_CORRTHRESH_MASK 0x7FF000UL /**< Bit mask for MODEM_CORRTHRESH */
+#define _MODEM_SICTRL1_CORRTHRESH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL1 */
+#define MODEM_SICTRL1_CORRTHRESH_DEFAULT (_MODEM_SICTRL1_CORRTHRESH_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_SICTRL1 */
+#define _MODEM_SICTRL1_CORRNUM_SHIFT 23 /**< Shift value for MODEM_CORRNUM */
+#define _MODEM_SICTRL1_CORRNUM_MASK 0x3800000UL /**< Bit mask for MODEM_CORRNUM */
+#define _MODEM_SICTRL1_CORRNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL1 */
+#define MODEM_SICTRL1_CORRNUM_DEFAULT (_MODEM_SICTRL1_CORRNUM_DEFAULT << 23) /**< Shifted mode DEFAULT for MODEM_SICTRL1 */
+#define MODEM_SICTRL1_FASTMODE (0x1UL << 26) /**< Zigbee fast mode */
+#define _MODEM_SICTRL1_FASTMODE_SHIFT 26 /**< Shift value for MODEM_FASTMODE */
+#define _MODEM_SICTRL1_FASTMODE_MASK 0x4000000UL /**< Bit mask for MODEM_FASTMODE */
+#define _MODEM_SICTRL1_FASTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL1 */
+#define MODEM_SICTRL1_FASTMODE_DEFAULT (_MODEM_SICTRL1_FASTMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for MODEM_SICTRL1 */
+#define _MODEM_SICTRL1_NARROWPULSETHRESH_SHIFT 27 /**< Shift value for MODEM_NARROWPULSETHRESH */
+#define _MODEM_SICTRL1_NARROWPULSETHRESH_MASK 0xF8000000UL /**< Bit mask for MODEM_NARROWPULSETHRESH */
+#define _MODEM_SICTRL1_NARROWPULSETHRESH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL1 */
+#define MODEM_SICTRL1_NARROWPULSETHRESH_DEFAULT (_MODEM_SICTRL1_NARROWPULSETHRESH_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_SICTRL1 */
+
+/* Bit fields for MODEM SISTATUS */
+#define _MODEM_SISTATUS_RESETVALUE 0x00000000UL /**< Default value for MODEM_SISTATUS */
+#define _MODEM_SISTATUS_MASK 0x67FFFFFFUL /**< Mask for MODEM_SISTATUS */
+#define _MODEM_SISTATUS_SISTATE_SHIFT 0 /**< Shift value for MODEM_SISTATE */
+#define _MODEM_SISTATUS_SISTATE_MASK 0xFUL /**< Bit mask for MODEM_SISTATE */
+#define _MODEM_SISTATUS_SISTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SISTATUS */
+#define MODEM_SISTATUS_SISTATE_DEFAULT (_MODEM_SISTATUS_SISTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SISTATUS */
+#define MODEM_SISTATUS_NOISE (0x1UL << 4) /**< Noisy short window */
+#define _MODEM_SISTATUS_NOISE_SHIFT 4 /**< Shift value for MODEM_NOISE */
+#define _MODEM_SISTATUS_NOISE_MASK 0x10UL /**< Bit mask for MODEM_NOISE */
+#define _MODEM_SISTATUS_NOISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SISTATUS */
+#define MODEM_SISTATUS_NOISE_DEFAULT (_MODEM_SISTATUS_NOISE_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_SISTATUS */
+#define _MODEM_SISTATUS_LWPEAKCOUNT_SHIFT 5 /**< Shift value for MODEM_LWPEAKCOUNT */
+#define _MODEM_SISTATUS_LWPEAKCOUNT_MASK 0x3E0UL /**< Bit mask for MODEM_LWPEAKCOUNT */
+#define _MODEM_SISTATUS_LWPEAKCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SISTATUS */
+#define MODEM_SISTATUS_LWPEAKCOUNT_DEFAULT (_MODEM_SISTATUS_LWPEAKCOUNT_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_SISTATUS */
+#define _MODEM_SISTATUS_NARROWCOUNT_SHIFT 10 /**< Shift value for MODEM_NARROWCOUNT */
+#define _MODEM_SISTATUS_NARROWCOUNT_MASK 0x7C00UL /**< Bit mask for MODEM_NARROWCOUNT */
+#define _MODEM_SISTATUS_NARROWCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SISTATUS */
+#define MODEM_SISTATUS_NARROWCOUNT_DEFAULT (_MODEM_SISTATUS_NARROWCOUNT_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_SISTATUS */
+#define MODEM_SISTATUS_TIMELOCK (0x1UL << 15) /**< Timing locked */
+#define _MODEM_SISTATUS_TIMELOCK_SHIFT 15 /**< Shift value for MODEM_TIMELOCK */
+#define _MODEM_SISTATUS_TIMELOCK_MASK 0x8000UL /**< Bit mask for MODEM_TIMELOCK */
+#define _MODEM_SISTATUS_TIMELOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SISTATUS */
+#define MODEM_SISTATUS_TIMELOCK_DEFAULT (_MODEM_SISTATUS_TIMELOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_SISTATUS */
+#define MODEM_SISTATUS_SUPERCHIPFAIL (0x1UL << 16) /**< Superchip fail */
+#define _MODEM_SISTATUS_SUPERCHIPFAIL_SHIFT 16 /**< Shift value for MODEM_SUPERCHIPFAIL */
+#define _MODEM_SISTATUS_SUPERCHIPFAIL_MASK 0x10000UL /**< Bit mask for MODEM_SUPERCHIPFAIL */
+#define _MODEM_SISTATUS_SUPERCHIPFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SISTATUS */
+#define MODEM_SISTATUS_SUPERCHIPFAIL_DEFAULT (_MODEM_SISTATUS_SUPERCHIPFAIL_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_SISTATUS */
+#define MODEM_SISTATUS_SUPERCHIPPASS (0x1UL << 17) /**< Superchip pass */
+#define _MODEM_SISTATUS_SUPERCHIPPASS_SHIFT 17 /**< Shift value for MODEM_SUPERCHIPPASS */
+#define _MODEM_SISTATUS_SUPERCHIPPASS_MASK 0x20000UL /**< Bit mask for MODEM_SUPERCHIPPASS */
+#define _MODEM_SISTATUS_SUPERCHIPPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SISTATUS */
+#define MODEM_SISTATUS_SUPERCHIPPASS_DEFAULT (_MODEM_SISTATUS_SUPERCHIPPASS_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_SISTATUS */
+#define _MODEM_SISTATUS_TIMEOFFSET_SHIFT 18 /**< Shift value for MODEM_TIMEOFFSET */
+#define _MODEM_SISTATUS_TIMEOFFSET_MASK 0x1C0000UL /**< Bit mask for MODEM_TIMEOFFSET */
+#define _MODEM_SISTATUS_TIMEOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SISTATUS */
+#define MODEM_SISTATUS_TIMEOFFSET_DEFAULT (_MODEM_SISTATUS_TIMEOFFSET_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_SISTATUS */
+#define _MODEM_SISTATUS_CORRPASSNUM_SHIFT 21 /**< Shift value for MODEM_CORRPASSNUM */
+#define _MODEM_SISTATUS_CORRPASSNUM_MASK 0x7E00000UL /**< Bit mask for MODEM_CORRPASSNUM */
+#define _MODEM_SISTATUS_CORRPASSNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SISTATUS */
+#define MODEM_SISTATUS_CORRPASSNUM_DEFAULT (_MODEM_SISTATUS_CORRPASSNUM_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_SISTATUS */
+#define MODEM_SISTATUS_SNIFFDONE (0x1UL << 29) /**< Sniff done */
+#define _MODEM_SISTATUS_SNIFFDONE_SHIFT 29 /**< Shift value for MODEM_SNIFFDONE */
+#define _MODEM_SISTATUS_SNIFFDONE_MASK 0x20000000UL /**< Bit mask for MODEM_SNIFFDONE */
+#define _MODEM_SISTATUS_SNIFFDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SISTATUS */
+#define MODEM_SISTATUS_SNIFFDONE_DEFAULT (_MODEM_SISTATUS_SNIFFDONE_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_SISTATUS */
+#define MODEM_SISTATUS_SIDET (0x1UL << 30) /**< Signal detected */
+#define _MODEM_SISTATUS_SIDET_SHIFT 30 /**< Shift value for MODEM_SIDET */
+#define _MODEM_SISTATUS_SIDET_MASK 0x40000000UL /**< Bit mask for MODEM_SIDET */
+#define _MODEM_SISTATUS_SIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SISTATUS */
+#define MODEM_SISTATUS_SIDET_DEFAULT (_MODEM_SISTATUS_SIDET_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_SISTATUS */
+
+/* Bit fields for MODEM CFGANTPATTEXT */
+#define _MODEM_CFGANTPATTEXT_RESETVALUE 0x00000000UL /**< Default value for MODEM_CFGANTPATTEXT */
+#define _MODEM_CFGANTPATTEXT_MASK 0x3FFFFFFFUL /**< Mask for MODEM_CFGANTPATTEXT */
+#define _MODEM_CFGANTPATTEXT_CFGANTPATTVALEXT_SHIFT 0 /**< Shift value for MODEM_CFGANTPATTVALEXT */
+#define _MODEM_CFGANTPATTEXT_CFGANTPATTVALEXT_MASK 0x3FFFFFFFUL /**< Bit mask for MODEM_CFGANTPATTVALEXT */
+#define _MODEM_CFGANTPATTEXT_CFGANTPATTVALEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CFGANTPATTEXT */
+#define MODEM_CFGANTPATTEXT_CFGANTPATTVALEXT_DEFAULT (_MODEM_CFGANTPATTEXT_CFGANTPATTVALEXT_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CFGANTPATTEXT*/
+
+/* Bit fields for MODEM SICTRL2 */
+#define _MODEM_SICTRL2_RESETVALUE 0x00000000UL /**< Default value for MODEM_SICTRL2 */
+#define _MODEM_SICTRL2_MASK 0x000000FFUL /**< Mask for MODEM_SICTRL2 */
+#define MODEM_SICTRL2_SIRSTAGCMODE (0x1UL << 0) /**< SI reset by AGC */
+#define _MODEM_SICTRL2_SIRSTAGCMODE_SHIFT 0 /**< Shift value for MODEM_SIRSTAGCMODE */
+#define _MODEM_SICTRL2_SIRSTAGCMODE_MASK 0x1UL /**< Bit mask for MODEM_SIRSTAGCMODE */
+#define _MODEM_SICTRL2_SIRSTAGCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL2 */
+#define MODEM_SICTRL2_SIRSTAGCMODE_DEFAULT (_MODEM_SICTRL2_SIRSTAGCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SICTRL2 */
+#define MODEM_SICTRL2_SIRSTPRSMODE (0x1UL << 1) /**< SI reset by PRS PAEN */
+#define _MODEM_SICTRL2_SIRSTPRSMODE_SHIFT 1 /**< Shift value for MODEM_SIRSTPRSMODE */
+#define _MODEM_SICTRL2_SIRSTPRSMODE_MASK 0x2UL /**< Bit mask for MODEM_SIRSTPRSMODE */
+#define _MODEM_SICTRL2_SIRSTPRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL2 */
+#define MODEM_SICTRL2_SIRSTPRSMODE_DEFAULT (_MODEM_SICTRL2_SIRSTPRSMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_SICTRL2 */
+#define MODEM_SICTRL2_SIRSTCCAMODE (0x1UL << 2) /**< SI reset by CCA req */
+#define _MODEM_SICTRL2_SIRSTCCAMODE_SHIFT 2 /**< Shift value for MODEM_SIRSTCCAMODE */
+#define _MODEM_SICTRL2_SIRSTCCAMODE_MASK 0x4UL /**< Bit mask for MODEM_SIRSTCCAMODE */
+#define _MODEM_SICTRL2_SIRSTCCAMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL2 */
+#define MODEM_SICTRL2_SIRSTCCAMODE_DEFAULT (_MODEM_SICTRL2_SIRSTCCAMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_SICTRL2 */
+#define _MODEM_SICTRL2_SUPERCHIPTHRESH_SHIFT 3 /**< Shift value for MODEM_SUPERCHIPTHRESH */
+#define _MODEM_SICTRL2_SUPERCHIPTHRESH_MASK 0x38UL /**< Bit mask for MODEM_SUPERCHIPTHRESH */
+#define _MODEM_SICTRL2_SUPERCHIPTHRESH_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL2 */
+#define MODEM_SICTRL2_SUPERCHIPTHRESH_DEFAULT (_MODEM_SICTRL2_SUPERCHIPTHRESH_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_SICTRL2 */
+#define MODEM_SICTRL2_DISSIFRAMEDET (0x1UL << 6) /**< Disable SI when framedet */
+#define _MODEM_SICTRL2_DISSIFRAMEDET_SHIFT 6 /**< Shift value for MODEM_DISSIFRAMEDET */
+#define _MODEM_SICTRL2_DISSIFRAMEDET_MASK 0x40UL /**< Bit mask for MODEM_DISSIFRAMEDET */
+#define _MODEM_SICTRL2_DISSIFRAMEDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL2 */
+#define MODEM_SICTRL2_DISSIFRAMEDET_DEFAULT (_MODEM_SICTRL2_DISSIFRAMEDET_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_SICTRL2 */
+#define MODEM_SICTRL2_AGCRSTUPONSI (0x1UL << 7) /**< AGC reset on SI reset */
+#define _MODEM_SICTRL2_AGCRSTUPONSI_SHIFT 7 /**< Shift value for MODEM_AGCRSTUPONSI */
+#define _MODEM_SICTRL2_AGCRSTUPONSI_MASK 0x80UL /**< Bit mask for MODEM_AGCRSTUPONSI */
+#define _MODEM_SICTRL2_AGCRSTUPONSI_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SICTRL2 */
+#define MODEM_SICTRL2_AGCRSTUPONSI_DEFAULT (_MODEM_SICTRL2_AGCRSTUPONSI_DEFAULT << 7) /**< Shifted mode DEFAULT for MODEM_SICTRL2 */
+
+/* Bit fields for MODEM CHFSWCTRL */
+#define _MODEM_CHFSWCTRL_RESETVALUE 0x00000000UL /**< Default value for MODEM_CHFSWCTRL */
+#define _MODEM_CHFSWCTRL_MASK 0x0003FFFFUL /**< Mask for MODEM_CHFSWCTRL */
+#define _MODEM_CHFSWCTRL_CHFSWTIME_SHIFT 0 /**< Shift value for MODEM_CHFSWTIME */
+#define _MODEM_CHFSWCTRL_CHFSWTIME_MASK 0x3FFFFUL /**< Bit mask for MODEM_CHFSWTIME */
+#define _MODEM_CHFSWCTRL_CHFSWTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_CHFSWCTRL */
+#define MODEM_CHFSWCTRL_CHFSWTIME_DEFAULT (_MODEM_CHFSWCTRL_CHFSWTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_CHFSWCTRL */
+
+/* Bit fields for MODEM IRCAL */
+#define _MODEM_IRCAL_RESETVALUE 0x00000000UL /**< Default value for MODEM_IRCAL */
+#define _MODEM_IRCAL_MASK 0x0000FFBFUL /**< Mask for MODEM_IRCAL */
+#define MODEM_IRCAL_IRCALEN (0x1UL << 0) /**< IRCAL enable bit */
+#define _MODEM_IRCAL_IRCALEN_SHIFT 0 /**< Shift value for MODEM_IRCALEN */
+#define _MODEM_IRCAL_IRCALEN_MASK 0x1UL /**< Bit mask for MODEM_IRCALEN */
+#define _MODEM_IRCAL_IRCALEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IRCAL */
+#define MODEM_IRCAL_IRCALEN_DEFAULT (_MODEM_IRCAL_IRCALEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_IRCAL */
+#define _MODEM_IRCAL_MURSHF_SHIFT 1 /**< Shift value for MODEM_MURSHF */
+#define _MODEM_IRCAL_MURSHF_MASK 0x3EUL /**< Bit mask for MODEM_MURSHF */
+#define _MODEM_IRCAL_MURSHF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IRCAL */
+#define MODEM_IRCAL_MURSHF_DEFAULT (_MODEM_IRCAL_MURSHF_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_IRCAL */
+#define _MODEM_IRCAL_MUISHF_SHIFT 7 /**< Shift value for MODEM_MUISHF */
+#define _MODEM_IRCAL_MUISHF_MASK 0x1F80UL /**< Bit mask for MODEM_MUISHF */
+#define _MODEM_IRCAL_MUISHF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IRCAL */
+#define MODEM_IRCAL_MUISHF_DEFAULT (_MODEM_IRCAL_MUISHF_DEFAULT << 7) /**< Shifted mode DEFAULT for MODEM_IRCAL */
+#define MODEM_IRCAL_IRCORREN (0x1UL << 13) /**< IR Correction enable bit */
+#define _MODEM_IRCAL_IRCORREN_SHIFT 13 /**< Shift value for MODEM_IRCORREN */
+#define _MODEM_IRCAL_IRCORREN_MASK 0x2000UL /**< Bit mask for MODEM_IRCORREN */
+#define _MODEM_IRCAL_IRCORREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IRCAL */
+#define MODEM_IRCAL_IRCORREN_DEFAULT (_MODEM_IRCAL_IRCORREN_DEFAULT << 13) /**< Shifted mode DEFAULT for MODEM_IRCAL */
+#define MODEM_IRCAL_IRCALCOEFRSTCMD (0x1UL << 14) /**< IRCAL coef reset cmd */
+#define _MODEM_IRCAL_IRCALCOEFRSTCMD_SHIFT 14 /**< Shift value for MODEM_IRCALCOEFRSTCMD */
+#define _MODEM_IRCAL_IRCALCOEFRSTCMD_MASK 0x4000UL /**< Bit mask for MODEM_IRCALCOEFRSTCMD */
+#define _MODEM_IRCAL_IRCALCOEFRSTCMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IRCAL */
+#define MODEM_IRCAL_IRCALCOEFRSTCMD_DEFAULT (_MODEM_IRCAL_IRCALCOEFRSTCMD_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_IRCAL */
+#define MODEM_IRCAL_IRCALIFADCDBG (0x1UL << 15) /**< IRCAL IFADC DBG */
+#define _MODEM_IRCAL_IRCALIFADCDBG_SHIFT 15 /**< Shift value for MODEM_IRCALIFADCDBG */
+#define _MODEM_IRCAL_IRCALIFADCDBG_MASK 0x8000UL /**< Bit mask for MODEM_IRCALIFADCDBG */
+#define _MODEM_IRCAL_IRCALIFADCDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IRCAL */
+#define MODEM_IRCAL_IRCALIFADCDBG_DEFAULT (_MODEM_IRCAL_IRCALIFADCDBG_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_IRCAL */
+
+/* Bit fields for MODEM IRCALCOEF */
+#define _MODEM_IRCALCOEF_RESETVALUE 0x00000000UL /**< Default value for MODEM_IRCALCOEF */
+#define _MODEM_IRCALCOEF_MASK 0x7FFF7FFFUL /**< Mask for MODEM_IRCALCOEF */
+#define _MODEM_IRCALCOEF_CRV_SHIFT 0 /**< Shift value for MODEM_CRV */
+#define _MODEM_IRCALCOEF_CRV_MASK 0x7FFFUL /**< Bit mask for MODEM_CRV */
+#define _MODEM_IRCALCOEF_CRV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IRCALCOEF */
+#define MODEM_IRCALCOEF_CRV_DEFAULT (_MODEM_IRCALCOEF_CRV_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_IRCALCOEF */
+#define _MODEM_IRCALCOEF_CIV_SHIFT 16 /**< Shift value for MODEM_CIV */
+#define _MODEM_IRCALCOEF_CIV_MASK 0x7FFF0000UL /**< Bit mask for MODEM_CIV */
+#define _MODEM_IRCALCOEF_CIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IRCALCOEF */
+#define MODEM_IRCALCOEF_CIV_DEFAULT (_MODEM_IRCALCOEF_CIV_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_IRCALCOEF */
+
+/* Bit fields for MODEM IRCALCOEFWR */
+#define _MODEM_IRCALCOEFWR_RESETVALUE 0x00000000UL /**< Default value for MODEM_IRCALCOEFWR */
+#define _MODEM_IRCALCOEFWR_MASK 0xFFFFFFFFUL /**< Mask for MODEM_IRCALCOEFWR */
+#define _MODEM_IRCALCOEFWR_CRVWD_SHIFT 0 /**< Shift value for MODEM_CRVWD */
+#define _MODEM_IRCALCOEFWR_CRVWD_MASK 0x7FFFUL /**< Bit mask for MODEM_CRVWD */
+#define _MODEM_IRCALCOEFWR_CRVWD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IRCALCOEFWR */
+#define MODEM_IRCALCOEFWR_CRVWD_DEFAULT (_MODEM_IRCALCOEFWR_CRVWD_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_IRCALCOEFWR */
+#define MODEM_IRCALCOEFWR_CRVWEN (0x1UL << 15) /**< CIV Coefficient Write Enable */
+#define _MODEM_IRCALCOEFWR_CRVWEN_SHIFT 15 /**< Shift value for MODEM_CRVWEN */
+#define _MODEM_IRCALCOEFWR_CRVWEN_MASK 0x8000UL /**< Bit mask for MODEM_CRVWEN */
+#define _MODEM_IRCALCOEFWR_CRVWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IRCALCOEFWR */
+#define MODEM_IRCALCOEFWR_CRVWEN_DEFAULT (_MODEM_IRCALCOEFWR_CRVWEN_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_IRCALCOEFWR */
+#define _MODEM_IRCALCOEFWR_CIVWD_SHIFT 16 /**< Shift value for MODEM_CIVWD */
+#define _MODEM_IRCALCOEFWR_CIVWD_MASK 0x7FFF0000UL /**< Bit mask for MODEM_CIVWD */
+#define _MODEM_IRCALCOEFWR_CIVWD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IRCALCOEFWR */
+#define MODEM_IRCALCOEFWR_CIVWD_DEFAULT (_MODEM_IRCALCOEFWR_CIVWD_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_IRCALCOEFWR */
+#define MODEM_IRCALCOEFWR_CIVWEN (0x1UL << 31) /**< CIV Coefficient Write Enable */
+#define _MODEM_IRCALCOEFWR_CIVWEN_SHIFT 31 /**< Shift value for MODEM_CIVWEN */
+#define _MODEM_IRCALCOEFWR_CIVWEN_MASK 0x80000000UL /**< Bit mask for MODEM_CIVWEN */
+#define _MODEM_IRCALCOEFWR_CIVWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_IRCALCOEFWR */
+#define MODEM_IRCALCOEFWR_CIVWEN_DEFAULT (_MODEM_IRCALCOEFWR_CIVWEN_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_IRCALCOEFWR */
+
+/* Bit fields for MODEM ADCTRL1 */
+#define _MODEM_ADCTRL1_RESETVALUE 0x00080000UL /**< Default value for MODEM_ADCTRL1 */
+#define _MODEM_ADCTRL1_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADCTRL1 */
+#define _MODEM_ADCTRL1_ADCTRL1_SHIFT 0 /**< Shift value for MODEM_ADCTRL1 */
+#define _MODEM_ADCTRL1_ADCTRL1_MASK 0xFFFFFFFFUL /**< Bit mask for MODEM_ADCTRL1 */
+#define _MODEM_ADCTRL1_ADCTRL1_DEFAULT 0x00080000UL /**< Mode DEFAULT for MODEM_ADCTRL1 */
+#define MODEM_ADCTRL1_ADCTRL1_DEFAULT (_MODEM_ADCTRL1_ADCTRL1_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADCTRL1 */
+
+/* Bit fields for MODEM ADCTRL2 */
+#define _MODEM_ADCTRL2_RESETVALUE 0x00000001UL /**< Default value for MODEM_ADCTRL2 */
+#define _MODEM_ADCTRL2_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADCTRL2 */
+#define _MODEM_ADCTRL2_ADCTRL2_SHIFT 0 /**< Shift value for MODEM_ADCTRL2 */
+#define _MODEM_ADCTRL2_ADCTRL2_MASK 0xFFFFFFFFUL /**< Bit mask for MODEM_ADCTRL2 */
+#define _MODEM_ADCTRL2_ADCTRL2_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_ADCTRL2 */
+#define MODEM_ADCTRL2_ADCTRL2_DEFAULT (_MODEM_ADCTRL2_ADCTRL2_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADCTRL2 */
+
+/* Bit fields for MODEM ADQUAL0 */
+#define _MODEM_ADQUAL0_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADQUAL0 */
+#define _MODEM_ADQUAL0_MASK 0x03FF03FFUL /**< Mask for MODEM_ADQUAL0 */
+#define _MODEM_ADQUAL0_ADRSSI0_SHIFT 0 /**< Shift value for MODEM_ADRSSI0 */
+#define _MODEM_ADQUAL0_ADRSSI0_MASK 0x3FFUL /**< Bit mask for MODEM_ADRSSI0 */
+#define _MODEM_ADQUAL0_ADRSSI0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADQUAL0 */
+#define MODEM_ADQUAL0_ADRSSI0_DEFAULT (_MODEM_ADQUAL0_ADRSSI0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADQUAL0 */
+#define _MODEM_ADQUAL0_ADRSSI1_SHIFT 16 /**< Shift value for MODEM_ADRSSI1 */
+#define _MODEM_ADQUAL0_ADRSSI1_MASK 0x3FF0000UL /**< Bit mask for MODEM_ADRSSI1 */
+#define _MODEM_ADQUAL0_ADRSSI1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADQUAL0 */
+#define MODEM_ADQUAL0_ADRSSI1_DEFAULT (_MODEM_ADQUAL0_ADRSSI1_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADQUAL0 */
+
+/* Bit fields for MODEM ADQUAL1 */
+#define _MODEM_ADQUAL1_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADQUAL1 */
+#define _MODEM_ADQUAL1_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADQUAL1 */
+#define _MODEM_ADQUAL1_ADCORR0_SHIFT 0 /**< Shift value for MODEM_ADCORR0 */
+#define _MODEM_ADQUAL1_ADCORR0_MASK 0x1FFFFUL /**< Bit mask for MODEM_ADCORR0 */
+#define _MODEM_ADQUAL1_ADCORR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADQUAL1 */
+#define MODEM_ADQUAL1_ADCORR0_DEFAULT (_MODEM_ADQUAL1_ADCORR0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADQUAL1 */
+#define _MODEM_ADQUAL1_ADSTAT1_SHIFT 17 /**< Shift value for MODEM_ADSTAT1 */
+#define _MODEM_ADQUAL1_ADSTAT1_MASK 0xFFFE0000UL /**< Bit mask for MODEM_ADSTAT1 */
+#define _MODEM_ADQUAL1_ADSTAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADQUAL1 */
+#define MODEM_ADQUAL1_ADSTAT1_DEFAULT (_MODEM_ADQUAL1_ADSTAT1_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_ADQUAL1 */
+
+/* Bit fields for MODEM ADQUAL2 */
+#define _MODEM_ADQUAL2_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADQUAL2 */
+#define _MODEM_ADQUAL2_MASK 0x03FF03FFUL /**< Mask for MODEM_ADQUAL2 */
+#define _MODEM_ADQUAL2_ADRSSI0P_SHIFT 0 /**< Shift value for MODEM_ADRSSI0P */
+#define _MODEM_ADQUAL2_ADRSSI0P_MASK 0x3FFUL /**< Bit mask for MODEM_ADRSSI0P */
+#define _MODEM_ADQUAL2_ADRSSI0P_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADQUAL2 */
+#define MODEM_ADQUAL2_ADRSSI0P_DEFAULT (_MODEM_ADQUAL2_ADRSSI0P_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADQUAL2 */
+#define _MODEM_ADQUAL2_ADRSSI1P_SHIFT 16 /**< Shift value for MODEM_ADRSSI1P */
+#define _MODEM_ADQUAL2_ADRSSI1P_MASK 0x3FF0000UL /**< Bit mask for MODEM_ADRSSI1P */
+#define _MODEM_ADQUAL2_ADRSSI1P_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADQUAL2 */
+#define MODEM_ADQUAL2_ADRSSI1P_DEFAULT (_MODEM_ADQUAL2_ADRSSI1P_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADQUAL2 */
+
+/* Bit fields for MODEM ADQUAL3 */
+#define _MODEM_ADQUAL3_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADQUAL3 */
+#define _MODEM_ADQUAL3_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADQUAL3 */
+#define _MODEM_ADQUAL3_ADCORR0P_SHIFT 0 /**< Shift value for MODEM_ADCORR0P */
+#define _MODEM_ADQUAL3_ADCORR0P_MASK 0x1FFFFUL /**< Bit mask for MODEM_ADCORR0P */
+#define _MODEM_ADQUAL3_ADCORR0P_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADQUAL3 */
+#define MODEM_ADQUAL3_ADCORR0P_DEFAULT (_MODEM_ADQUAL3_ADCORR0P_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADQUAL3 */
+#define _MODEM_ADQUAL3_ADSTAT2_SHIFT 17 /**< Shift value for MODEM_ADSTAT2 */
+#define _MODEM_ADQUAL3_ADSTAT2_MASK 0xFFFE0000UL /**< Bit mask for MODEM_ADSTAT2 */
+#define _MODEM_ADQUAL3_ADSTAT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADQUAL3 */
+#define MODEM_ADQUAL3_ADSTAT2_DEFAULT (_MODEM_ADQUAL3_ADSTAT2_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_ADQUAL3 */
+
+/* Bit fields for MODEM ADQUAL4 */
+#define _MODEM_ADQUAL4_RESETVALUE 0x0200003FUL /**< Default value for MODEM_ADQUAL4 */
+#define _MODEM_ADQUAL4_MASK 0xC3FF003FUL /**< Mask for MODEM_ADQUAL4 */
+#define _MODEM_ADQUAL4_ADAGCGRTHR_SHIFT 0 /**< Shift value for MODEM_ADAGCGRTHR */
+#define _MODEM_ADQUAL4_ADAGCGRTHR_MASK 0x3FUL /**< Bit mask for MODEM_ADAGCGRTHR */
+#define _MODEM_ADQUAL4_ADAGCGRTHR_DEFAULT 0x0000003FUL /**< Mode DEFAULT for MODEM_ADQUAL4 */
+#define MODEM_ADQUAL4_ADAGCGRTHR_DEFAULT (_MODEM_ADQUAL4_ADAGCGRTHR_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADQUAL4 */
+#define _MODEM_ADQUAL4_ADRSSIGRTHR_SHIFT 16 /**< Shift value for MODEM_ADRSSIGRTHR */
+#define _MODEM_ADQUAL4_ADRSSIGRTHR_MASK 0x3FF0000UL /**< Bit mask for MODEM_ADRSSIGRTHR */
+#define _MODEM_ADQUAL4_ADRSSIGRTHR_DEFAULT 0x00000200UL /**< Mode DEFAULT for MODEM_ADQUAL4 */
+#define MODEM_ADQUAL4_ADRSSIGRTHR_DEFAULT (_MODEM_ADQUAL4_ADRSSIGRTHR_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADQUAL4 */
+#define _MODEM_ADQUAL4_ADGRMODE_SHIFT 30 /**< Shift value for MODEM_ADGRMODE */
+#define _MODEM_ADQUAL4_ADGRMODE_MASK 0xC0000000UL /**< Bit mask for MODEM_ADGRMODE */
+#define _MODEM_ADQUAL4_ADGRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADQUAL4 */
+#define MODEM_ADQUAL4_ADGRMODE_DEFAULT (_MODEM_ADQUAL4_ADGRMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_ADQUAL4 */
+
+/* Bit fields for MODEM ADQUAL5 */
+#define _MODEM_ADQUAL5_RESETVALUE 0x0000FFFFUL /**< Default value for MODEM_ADQUAL5 */
+#define _MODEM_ADQUAL5_MASK 0x0001FFFFUL /**< Mask for MODEM_ADQUAL5 */
+#define _MODEM_ADQUAL5_ADDIRECTCORR_SHIFT 0 /**< Shift value for MODEM_ADDIRECTCORR */
+#define _MODEM_ADQUAL5_ADDIRECTCORR_MASK 0x1FFFFUL /**< Bit mask for MODEM_ADDIRECTCORR */
+#define _MODEM_ADQUAL5_ADDIRECTCORR_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for MODEM_ADQUAL5 */
+#define MODEM_ADQUAL5_ADDIRECTCORR_DEFAULT (_MODEM_ADQUAL5_ADDIRECTCORR_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADQUAL5 */
+
+/* Bit fields for MODEM ADQUAL6 */
+#define _MODEM_ADQUAL6_RESETVALUE 0x0000FFFFUL /**< Default value for MODEM_ADQUAL6 */
+#define _MODEM_ADQUAL6_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADQUAL6 */
+#define _MODEM_ADQUAL6_ADBACORRTHR_SHIFT 0 /**< Shift value for MODEM_ADBACORRTHR */
+#define _MODEM_ADQUAL6_ADBACORRTHR_MASK 0x1FFFFUL /**< Bit mask for MODEM_ADBACORRTHR */
+#define _MODEM_ADQUAL6_ADBACORRTHR_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for MODEM_ADQUAL6 */
+#define MODEM_ADQUAL6_ADBACORRTHR_DEFAULT (_MODEM_ADQUAL6_ADBACORRTHR_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADQUAL6 */
+#define _MODEM_ADQUAL6_ADBACORRDIFF_SHIFT 17 /**< Shift value for MODEM_ADBACORRDIFF */
+#define _MODEM_ADQUAL6_ADBACORRDIFF_MASK 0xFFFE0000UL /**< Bit mask for MODEM_ADBACORRDIFF */
+#define _MODEM_ADQUAL6_ADBACORRDIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADQUAL6 */
+#define MODEM_ADQUAL6_ADBACORRDIFF_DEFAULT (_MODEM_ADQUAL6_ADBACORRDIFF_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_ADQUAL6 */
+
+/* Bit fields for MODEM ADQUAL7 */
+#define _MODEM_ADQUAL7_RESETVALUE 0x000003FFUL /**< Default value for MODEM_ADQUAL7 */
+#define _MODEM_ADQUAL7_MASK 0x03FF03FFUL /**< Mask for MODEM_ADQUAL7 */
+#define _MODEM_ADQUAL7_ADBARSSITHR_SHIFT 0 /**< Shift value for MODEM_ADBARSSITHR */
+#define _MODEM_ADQUAL7_ADBARSSITHR_MASK 0x3FFUL /**< Bit mask for MODEM_ADBARSSITHR */
+#define _MODEM_ADQUAL7_ADBARSSITHR_DEFAULT 0x000003FFUL /**< Mode DEFAULT for MODEM_ADQUAL7 */
+#define MODEM_ADQUAL7_ADBARSSITHR_DEFAULT (_MODEM_ADQUAL7_ADBARSSITHR_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADQUAL7 */
+#define _MODEM_ADQUAL7_ADBARSSIDIFF_SHIFT 16 /**< Shift value for MODEM_ADBARSSIDIFF */
+#define _MODEM_ADQUAL7_ADBARSSIDIFF_MASK 0x3FF0000UL /**< Bit mask for MODEM_ADBARSSIDIFF */
+#define _MODEM_ADQUAL7_ADBARSSIDIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADQUAL7 */
+#define MODEM_ADQUAL7_ADBARSSIDIFF_DEFAULT (_MODEM_ADQUAL7_ADBARSSIDIFF_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADQUAL7 */
+
+/* Bit fields for MODEM ADQUAL8 */
+#define _MODEM_ADQUAL8_RESETVALUE 0x0000FFFFUL /**< Default value for MODEM_ADQUAL8 */
+#define _MODEM_ADQUAL8_MASK 0x3F31FFFFUL /**< Mask for MODEM_ADQUAL8 */
+#define _MODEM_ADQUAL8_ADBACORRTHR2_SHIFT 0 /**< Shift value for MODEM_ADBACORRTHR2 */
+#define _MODEM_ADQUAL8_ADBACORRTHR2_MASK 0x1FFFFUL /**< Bit mask for MODEM_ADBACORRTHR2 */
+#define _MODEM_ADQUAL8_ADBACORRTHR2_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for MODEM_ADQUAL8 */
+#define MODEM_ADQUAL8_ADBACORRTHR2_DEFAULT (_MODEM_ADQUAL8_ADBACORRTHR2_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADQUAL8 */
+#define _MODEM_ADQUAL8_ADBAMODE_SHIFT 20 /**< Shift value for MODEM_ADBAMODE */
+#define _MODEM_ADQUAL8_ADBAMODE_MASK 0x300000UL /**< Bit mask for MODEM_ADBAMODE */
+#define _MODEM_ADQUAL8_ADBAMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADQUAL8 */
+#define MODEM_ADQUAL8_ADBAMODE_DEFAULT (_MODEM_ADQUAL8_ADBAMODE_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_ADQUAL8 */
+#define _MODEM_ADQUAL8_ADBAAGCTHR_SHIFT 24 /**< Shift value for MODEM_ADBAAGCTHR */
+#define _MODEM_ADQUAL8_ADBAAGCTHR_MASK 0x3F000000UL /**< Bit mask for MODEM_ADBAAGCTHR */
+#define _MODEM_ADQUAL8_ADBAAGCTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADQUAL8 */
+#define MODEM_ADQUAL8_ADBAAGCTHR_DEFAULT (_MODEM_ADQUAL8_ADBAAGCTHR_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_ADQUAL8 */
+
+/* Bit fields for MODEM ADQUAL9 */
+#define _MODEM_ADQUAL9_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADQUAL9 */
+#define _MODEM_ADQUAL9_MASK 0x0001FFFFUL /**< Mask for MODEM_ADQUAL9 */
+#define _MODEM_ADQUAL9_ADCORR1_SHIFT 0 /**< Shift value for MODEM_ADCORR1 */
+#define _MODEM_ADQUAL9_ADCORR1_MASK 0x1FFFFUL /**< Bit mask for MODEM_ADCORR1 */
+#define _MODEM_ADQUAL9_ADCORR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADQUAL9 */
+#define MODEM_ADQUAL9_ADCORR1_DEFAULT (_MODEM_ADQUAL9_ADCORR1_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADQUAL9 */
+
+/* Bit fields for MODEM ADQUAL10 */
+#define _MODEM_ADQUAL10_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADQUAL10 */
+#define _MODEM_ADQUAL10_MASK 0x0001FFFFUL /**< Mask for MODEM_ADQUAL10 */
+#define _MODEM_ADQUAL10_ADCORR1P_SHIFT 0 /**< Shift value for MODEM_ADCORR1P */
+#define _MODEM_ADQUAL10_ADCORR1P_MASK 0x1FFFFUL /**< Bit mask for MODEM_ADCORR1P */
+#define _MODEM_ADQUAL10_ADCORR1P_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADQUAL10 */
+#define MODEM_ADQUAL10_ADCORR1P_DEFAULT (_MODEM_ADQUAL10_ADCORR1P_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADQUAL10 */
+
+/* Bit fields for MODEM ADFSM0 */
+#define _MODEM_ADFSM0_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM0 */
+#define _MODEM_ADFSM0_MASK 0x7FFFFFFFUL /**< Mask for MODEM_ADFSM0 */
+#define _MODEM_ADFSM0_ADSTATEC_SHIFT 0 /**< Shift value for MODEM_ADSTATEC */
+#define _MODEM_ADFSM0_ADSTATEC_MASK 0xFUL /**< Bit mask for MODEM_ADSTATEC */
+#define _MODEM_ADFSM0_ADSTATEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM0 */
+#define MODEM_ADFSM0_ADSTATEC_DEFAULT (_MODEM_ADFSM0_ADSTATEC_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM0 */
+#define _MODEM_ADFSM0_ADSTATEP_SHIFT 4 /**< Shift value for MODEM_ADSTATEP */
+#define _MODEM_ADFSM0_ADSTATEP_MASK 0xF0UL /**< Bit mask for MODEM_ADSTATEP */
+#define _MODEM_ADFSM0_ADSTATEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM0 */
+#define MODEM_ADFSM0_ADSTATEP_DEFAULT (_MODEM_ADFSM0_ADSTATEP_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_ADFSM0 */
+#define _MODEM_ADFSM0_ADSTATEP2_SHIFT 8 /**< Shift value for MODEM_ADSTATEP2 */
+#define _MODEM_ADFSM0_ADSTATEP2_MASK 0xF00UL /**< Bit mask for MODEM_ADSTATEP2 */
+#define _MODEM_ADFSM0_ADSTATEP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM0 */
+#define MODEM_ADFSM0_ADSTATEP2_DEFAULT (_MODEM_ADFSM0_ADSTATEP2_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_ADFSM0 */
+#define _MODEM_ADFSM0_ADSTATEN_SHIFT 12 /**< Shift value for MODEM_ADSTATEN */
+#define _MODEM_ADFSM0_ADSTATEN_MASK 0xF000UL /**< Bit mask for MODEM_ADSTATEN */
+#define _MODEM_ADFSM0_ADSTATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM0 */
+#define MODEM_ADFSM0_ADSTATEN_DEFAULT (_MODEM_ADFSM0_ADSTATEN_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_ADFSM0 */
+#define MODEM_ADFSM0_ADTD0 (0x1UL << 16) /**< timdet0 */
+#define _MODEM_ADFSM0_ADTD0_SHIFT 16 /**< Shift value for MODEM_ADTD0 */
+#define _MODEM_ADFSM0_ADTD0_MASK 0x10000UL /**< Bit mask for MODEM_ADTD0 */
+#define _MODEM_ADFSM0_ADTD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM0 */
+#define MODEM_ADFSM0_ADTD0_DEFAULT (_MODEM_ADFSM0_ADTD0_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM0 */
+#define MODEM_ADFSM0_ADTD0P (0x1UL << 17) /**< timdet0p */
+#define _MODEM_ADFSM0_ADTD0P_SHIFT 17 /**< Shift value for MODEM_ADTD0P */
+#define _MODEM_ADFSM0_ADTD0P_MASK 0x20000UL /**< Bit mask for MODEM_ADTD0P */
+#define _MODEM_ADFSM0_ADTD0P_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM0 */
+#define MODEM_ADFSM0_ADTD0P_DEFAULT (_MODEM_ADFSM0_ADTD0P_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_ADFSM0 */
+#define MODEM_ADFSM0_ADTD1 (0x1UL << 18) /**< timdet1 */
+#define _MODEM_ADFSM0_ADTD1_SHIFT 18 /**< Shift value for MODEM_ADTD1 */
+#define _MODEM_ADFSM0_ADTD1_MASK 0x40000UL /**< Bit mask for MODEM_ADTD1 */
+#define _MODEM_ADFSM0_ADTD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM0 */
+#define MODEM_ADFSM0_ADTD1_DEFAULT (_MODEM_ADFSM0_ADTD1_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_ADFSM0 */
+#define MODEM_ADFSM0_ADTD1P (0x1UL << 19) /**< timdet1p */
+#define _MODEM_ADFSM0_ADTD1P_SHIFT 19 /**< Shift value for MODEM_ADTD1P */
+#define _MODEM_ADFSM0_ADTD1P_MASK 0x80000UL /**< Bit mask for MODEM_ADTD1P */
+#define _MODEM_ADFSM0_ADTD1P_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM0 */
+#define MODEM_ADFSM0_ADTD1P_DEFAULT (_MODEM_ADFSM0_ADTD1P_DEFAULT << 19) /**< Shifted mode DEFAULT for MODEM_ADFSM0 */
+#define MODEM_ADFSM0_ADSTATREAD (0x1UL << 20) /**< ADSTATREAD */
+#define _MODEM_ADFSM0_ADSTATREAD_SHIFT 20 /**< Shift value for MODEM_ADSTATREAD */
+#define _MODEM_ADFSM0_ADSTATREAD_MASK 0x100000UL /**< Bit mask for MODEM_ADSTATREAD */
+#define _MODEM_ADFSM0_ADSTATREAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM0 */
+#define MODEM_ADFSM0_ADSTATREAD_DEFAULT (_MODEM_ADFSM0_ADSTATREAD_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_ADFSM0 */
+#define _MODEM_ADFSM0_ADSTAT1SEL_SHIFT 21 /**< Shift value for MODEM_ADSTAT1SEL */
+#define _MODEM_ADFSM0_ADSTAT1SEL_MASK 0x3E00000UL /**< Bit mask for MODEM_ADSTAT1SEL */
+#define _MODEM_ADFSM0_ADSTAT1SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM0 */
+#define MODEM_ADFSM0_ADSTAT1SEL_DEFAULT (_MODEM_ADFSM0_ADSTAT1SEL_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_ADFSM0 */
+#define _MODEM_ADFSM0_ADSTAT2SEL_SHIFT 26 /**< Shift value for MODEM_ADSTAT2SEL */
+#define _MODEM_ADFSM0_ADSTAT2SEL_MASK 0x7C000000UL /**< Bit mask for MODEM_ADSTAT2SEL */
+#define _MODEM_ADFSM0_ADSTAT2SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM0 */
+#define MODEM_ADFSM0_ADSTAT2SEL_DEFAULT (_MODEM_ADFSM0_ADSTAT2SEL_DEFAULT << 26) /**< Shifted mode DEFAULT for MODEM_ADFSM0 */
+
+/* Bit fields for MODEM ADFSM1 */
+#define _MODEM_ADFSM1_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM1 */
+#define _MODEM_ADFSM1_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM1 */
+#define _MODEM_ADFSM1_ADOSETANT0_SHIFT 0 /**< Shift value for MODEM_ADOSETANT0 */
+#define _MODEM_ADFSM1_ADOSETANT0_MASK 0xFFFFUL /**< Bit mask for MODEM_ADOSETANT0 */
+#define _MODEM_ADFSM1_ADOSETANT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM1 */
+#define MODEM_ADFSM1_ADOSETANT0_DEFAULT (_MODEM_ADFSM1_ADOSETANT0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM1 */
+#define _MODEM_ADFSM1_ADOSETANT1_SHIFT 16 /**< Shift value for MODEM_ADOSETANT1 */
+#define _MODEM_ADFSM1_ADOSETANT1_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADOSETANT1 */
+#define _MODEM_ADFSM1_ADOSETANT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM1 */
+#define MODEM_ADFSM1_ADOSETANT1_DEFAULT (_MODEM_ADFSM1_ADOSETANT1_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM1 */
+
+/* Bit fields for MODEM ADFSM2 */
+#define _MODEM_ADFSM2_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM2 */
+#define _MODEM_ADFSM2_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM2 */
+#define _MODEM_ADFSM2_ADOSWITCHANT_SHIFT 0 /**< Shift value for MODEM_ADOSWITCHANT */
+#define _MODEM_ADFSM2_ADOSWITCHANT_MASK 0xFFFFUL /**< Bit mask for MODEM_ADOSWITCHANT */
+#define _MODEM_ADFSM2_ADOSWITCHANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM2 */
+#define MODEM_ADFSM2_ADOSWITCHANT_DEFAULT (_MODEM_ADFSM2_ADOSWITCHANT_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM2 */
+#define _MODEM_ADFSM2_ADORESTARTRX_SHIFT 16 /**< Shift value for MODEM_ADORESTARTRX */
+#define _MODEM_ADFSM2_ADORESTARTRX_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADORESTARTRX */
+#define _MODEM_ADFSM2_ADORESTARTRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM2 */
+#define MODEM_ADFSM2_ADORESTARTRX_DEFAULT (_MODEM_ADFSM2_ADORESTARTRX_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM2 */
+
+/* Bit fields for MODEM ADFSM3 */
+#define _MODEM_ADFSM3_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM3 */
+#define _MODEM_ADFSM3_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM3 */
+#define _MODEM_ADFSM3_ADOQUAL0UPDATE_SHIFT 0 /**< Shift value for MODEM_ADOQUAL0UPDATE */
+#define _MODEM_ADFSM3_ADOQUAL0UPDATE_MASK 0xFFFFUL /**< Bit mask for MODEM_ADOQUAL0UPDATE */
+#define _MODEM_ADFSM3_ADOQUAL0UPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM3 */
+#define MODEM_ADFSM3_ADOQUAL0UPDATE_DEFAULT (_MODEM_ADFSM3_ADOQUAL0UPDATE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM3 */
+#define _MODEM_ADFSM3_ADOQUAL1UPDATE_SHIFT 16 /**< Shift value for MODEM_ADOQUAL1UPDATE */
+#define _MODEM_ADFSM3_ADOQUAL1UPDATE_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADOQUAL1UPDATE */
+#define _MODEM_ADFSM3_ADOQUAL1UPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM3 */
+#define MODEM_ADFSM3_ADOQUAL1UPDATE_DEFAULT (_MODEM_ADFSM3_ADOQUAL1UPDATE_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM3 */
+
+/* Bit fields for MODEM ADFSM4 */
+#define _MODEM_ADFSM4_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM4 */
+#define _MODEM_ADFSM4_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM4 */
+#define _MODEM_ADFSM4_ADOQUAL0CLEAR_SHIFT 0 /**< Shift value for MODEM_ADOQUAL0CLEAR */
+#define _MODEM_ADFSM4_ADOQUAL0CLEAR_MASK 0xFFFFUL /**< Bit mask for MODEM_ADOQUAL0CLEAR */
+#define _MODEM_ADFSM4_ADOQUAL0CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM4 */
+#define MODEM_ADFSM4_ADOQUAL0CLEAR_DEFAULT (_MODEM_ADFSM4_ADOQUAL0CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM4 */
+#define _MODEM_ADFSM4_ADOQUAL1CLEAR_SHIFT 16 /**< Shift value for MODEM_ADOQUAL1CLEAR */
+#define _MODEM_ADFSM4_ADOQUAL1CLEAR_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADOQUAL1CLEAR */
+#define _MODEM_ADFSM4_ADOQUAL1CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM4 */
+#define MODEM_ADFSM4_ADOQUAL1CLEAR_DEFAULT (_MODEM_ADFSM4_ADOQUAL1CLEAR_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM4 */
+
+/* Bit fields for MODEM ADFSM5 */
+#define _MODEM_ADFSM5_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM5 */
+#define _MODEM_ADFSM5_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM5 */
+#define _MODEM_ADFSM5_ADOMUX_SHIFT 0 /**< Shift value for MODEM_ADOMUX */
+#define _MODEM_ADFSM5_ADOMUX_MASK 0xFFFFFFFFUL /**< Bit mask for MODEM_ADOMUX */
+#define _MODEM_ADFSM5_ADOMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM5 */
+#define MODEM_ADFSM5_ADOMUX_DEFAULT (_MODEM_ADFSM5_ADOMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM5 */
+
+/* Bit fields for MODEM ADFSM6 */
+#define _MODEM_ADFSM6_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM6 */
+#define _MODEM_ADFSM6_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM6 */
+#define _MODEM_ADFSM6_ADNEXTSTATESW0_SHIFT 0 /**< Shift value for MODEM_ADNEXTSTATESW0 */
+#define _MODEM_ADFSM6_ADNEXTSTATESW0_MASK 0xFFFFUL /**< Bit mask for MODEM_ADNEXTSTATESW0 */
+#define _MODEM_ADFSM6_ADNEXTSTATESW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM6 */
+#define MODEM_ADFSM6_ADNEXTSTATESW0_DEFAULT (_MODEM_ADFSM6_ADNEXTSTATESW0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM6 */
+#define _MODEM_ADFSM6_ADNEXTSTATESW1_SHIFT 16 /**< Shift value for MODEM_ADNEXTSTATESW1 */
+#define _MODEM_ADFSM6_ADNEXTSTATESW1_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADNEXTSTATESW1 */
+#define _MODEM_ADFSM6_ADNEXTSTATESW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM6 */
+#define MODEM_ADFSM6_ADNEXTSTATESW1_DEFAULT (_MODEM_ADFSM6_ADNEXTSTATESW1_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM6 */
+
+/* Bit fields for MODEM ADFSM7 */
+#define _MODEM_ADFSM7_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM7 */
+#define _MODEM_ADFSM7_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM7 */
+#define _MODEM_ADFSM7_ADNEXTSTATESW2_SHIFT 0 /**< Shift value for MODEM_ADNEXTSTATESW2 */
+#define _MODEM_ADFSM7_ADNEXTSTATESW2_MASK 0xFFFFUL /**< Bit mask for MODEM_ADNEXTSTATESW2 */
+#define _MODEM_ADFSM7_ADNEXTSTATESW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM7 */
+#define MODEM_ADFSM7_ADNEXTSTATESW2_DEFAULT (_MODEM_ADFSM7_ADNEXTSTATESW2_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM7 */
+#define _MODEM_ADFSM7_ADNEXTSTATESW3_SHIFT 16 /**< Shift value for MODEM_ADNEXTSTATESW3 */
+#define _MODEM_ADFSM7_ADNEXTSTATESW3_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADNEXTSTATESW3 */
+#define _MODEM_ADFSM7_ADNEXTSTATESW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM7 */
+#define MODEM_ADFSM7_ADNEXTSTATESW3_DEFAULT (_MODEM_ADFSM7_ADNEXTSTATESW3_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM7 */
+
+/* Bit fields for MODEM ADFSM8 */
+#define _MODEM_ADFSM8_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM8 */
+#define _MODEM_ADFSM8_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM8 */
+#define _MODEM_ADFSM8_ADNEXTSTATESW4_SHIFT 0 /**< Shift value for MODEM_ADNEXTSTATESW4 */
+#define _MODEM_ADFSM8_ADNEXTSTATESW4_MASK 0xFFFFUL /**< Bit mask for MODEM_ADNEXTSTATESW4 */
+#define _MODEM_ADFSM8_ADNEXTSTATESW4_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM8 */
+#define MODEM_ADFSM8_ADNEXTSTATESW4_DEFAULT (_MODEM_ADFSM8_ADNEXTSTATESW4_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM8 */
+#define _MODEM_ADFSM8_ADNEXTSTATESW5_SHIFT 16 /**< Shift value for MODEM_ADNEXTSTATESW5 */
+#define _MODEM_ADFSM8_ADNEXTSTATESW5_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADNEXTSTATESW5 */
+#define _MODEM_ADFSM8_ADNEXTSTATESW5_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM8 */
+#define MODEM_ADFSM8_ADNEXTSTATESW5_DEFAULT (_MODEM_ADFSM8_ADNEXTSTATESW5_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM8 */
+
+/* Bit fields for MODEM ADFSM9 */
+#define _MODEM_ADFSM9_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM9 */
+#define _MODEM_ADFSM9_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM9 */
+#define _MODEM_ADFSM9_ADNEXTSTATESW6_SHIFT 0 /**< Shift value for MODEM_ADNEXTSTATESW6 */
+#define _MODEM_ADFSM9_ADNEXTSTATESW6_MASK 0xFFFFUL /**< Bit mask for MODEM_ADNEXTSTATESW6 */
+#define _MODEM_ADFSM9_ADNEXTSTATESW6_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM9 */
+#define MODEM_ADFSM9_ADNEXTSTATESW6_DEFAULT (_MODEM_ADFSM9_ADNEXTSTATESW6_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM9 */
+#define _MODEM_ADFSM9_ADNEXTSTATESW7_SHIFT 16 /**< Shift value for MODEM_ADNEXTSTATESW7 */
+#define _MODEM_ADFSM9_ADNEXTSTATESW7_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADNEXTSTATESW7 */
+#define _MODEM_ADFSM9_ADNEXTSTATESW7_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM9 */
+#define MODEM_ADFSM9_ADNEXTSTATESW7_DEFAULT (_MODEM_ADFSM9_ADNEXTSTATESW7_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM9 */
+
+/* Bit fields for MODEM ADFSM10 */
+#define _MODEM_ADFSM10_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM10 */
+#define _MODEM_ADFSM10_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM10 */
+#define _MODEM_ADFSM10_ADNEXTSTATESW8_SHIFT 0 /**< Shift value for MODEM_ADNEXTSTATESW8 */
+#define _MODEM_ADFSM10_ADNEXTSTATESW8_MASK 0xFFFFUL /**< Bit mask for MODEM_ADNEXTSTATESW8 */
+#define _MODEM_ADFSM10_ADNEXTSTATESW8_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM10 */
+#define MODEM_ADFSM10_ADNEXTSTATESW8_DEFAULT (_MODEM_ADFSM10_ADNEXTSTATESW8_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM10 */
+#define _MODEM_ADFSM10_ADNEXTSTATESW9_SHIFT 16 /**< Shift value for MODEM_ADNEXTSTATESW9 */
+#define _MODEM_ADFSM10_ADNEXTSTATESW9_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADNEXTSTATESW9 */
+#define _MODEM_ADFSM10_ADNEXTSTATESW9_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM10 */
+#define MODEM_ADFSM10_ADNEXTSTATESW9_DEFAULT (_MODEM_ADFSM10_ADNEXTSTATESW9_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM10 */
+
+/* Bit fields for MODEM ADFSM11 */
+#define _MODEM_ADFSM11_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM11 */
+#define _MODEM_ADFSM11_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM11 */
+#define _MODEM_ADFSM11_ADNEXTSTATESW10_SHIFT 0 /**< Shift value for MODEM_ADNEXTSTATESW10 */
+#define _MODEM_ADFSM11_ADNEXTSTATESW10_MASK 0xFFFFUL /**< Bit mask for MODEM_ADNEXTSTATESW10 */
+#define _MODEM_ADFSM11_ADNEXTSTATESW10_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM11 */
+#define MODEM_ADFSM11_ADNEXTSTATESW10_DEFAULT (_MODEM_ADFSM11_ADNEXTSTATESW10_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM11 */
+#define _MODEM_ADFSM11_ADNEXTSTATESW11_SHIFT 16 /**< Shift value for MODEM_ADNEXTSTATESW11 */
+#define _MODEM_ADFSM11_ADNEXTSTATESW11_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADNEXTSTATESW11 */
+#define _MODEM_ADFSM11_ADNEXTSTATESW11_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM11 */
+#define MODEM_ADFSM11_ADNEXTSTATESW11_DEFAULT (_MODEM_ADFSM11_ADNEXTSTATESW11_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM11 */
+
+/* Bit fields for MODEM ADFSM12 */
+#define _MODEM_ADFSM12_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM12 */
+#define _MODEM_ADFSM12_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM12 */
+#define _MODEM_ADFSM12_ADNEXTSTATESW12_SHIFT 0 /**< Shift value for MODEM_ADNEXTSTATESW12 */
+#define _MODEM_ADFSM12_ADNEXTSTATESW12_MASK 0xFFFFUL /**< Bit mask for MODEM_ADNEXTSTATESW12 */
+#define _MODEM_ADFSM12_ADNEXTSTATESW12_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM12 */
+#define MODEM_ADFSM12_ADNEXTSTATESW12_DEFAULT (_MODEM_ADFSM12_ADNEXTSTATESW12_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM12 */
+#define _MODEM_ADFSM12_ADNEXTSTATESW13_SHIFT 16 /**< Shift value for MODEM_ADNEXTSTATESW13 */
+#define _MODEM_ADFSM12_ADNEXTSTATESW13_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADNEXTSTATESW13 */
+#define _MODEM_ADFSM12_ADNEXTSTATESW13_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM12 */
+#define MODEM_ADFSM12_ADNEXTSTATESW13_DEFAULT (_MODEM_ADFSM12_ADNEXTSTATESW13_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM12 */
+
+/* Bit fields for MODEM ADFSM13 */
+#define _MODEM_ADFSM13_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM13 */
+#define _MODEM_ADFSM13_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM13 */
+#define _MODEM_ADFSM13_ADNEXTSTATESW14_SHIFT 0 /**< Shift value for MODEM_ADNEXTSTATESW14 */
+#define _MODEM_ADFSM13_ADNEXTSTATESW14_MASK 0xFFFFUL /**< Bit mask for MODEM_ADNEXTSTATESW14 */
+#define _MODEM_ADFSM13_ADNEXTSTATESW14_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM13 */
+#define MODEM_ADFSM13_ADNEXTSTATESW14_DEFAULT (_MODEM_ADFSM13_ADNEXTSTATESW14_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM13 */
+#define _MODEM_ADFSM13_ADNEXTSTATESW15_SHIFT 16 /**< Shift value for MODEM_ADNEXTSTATESW15 */
+#define _MODEM_ADFSM13_ADNEXTSTATESW15_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADNEXTSTATESW15 */
+#define _MODEM_ADFSM13_ADNEXTSTATESW15_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM13 */
+#define MODEM_ADFSM13_ADNEXTSTATESW15_DEFAULT (_MODEM_ADFSM13_ADNEXTSTATESW15_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM13 */
+
+/* Bit fields for MODEM ADFSM14 */
+#define _MODEM_ADFSM14_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM14 */
+#define _MODEM_ADFSM14_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM14 */
+#define _MODEM_ADFSM14_ADFSMCOND0ENA_SHIFT 0 /**< Shift value for MODEM_ADFSMCOND0ENA */
+#define _MODEM_ADFSM14_ADFSMCOND0ENA_MASK 0xFFFFUL /**< Bit mask for MODEM_ADFSMCOND0ENA */
+#define _MODEM_ADFSM14_ADFSMCOND0ENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM14 */
+#define MODEM_ADFSM14_ADFSMCOND0ENA_DEFAULT (_MODEM_ADFSM14_ADFSMCOND0ENA_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM14 */
+#define _MODEM_ADFSM14_ADFSMCOND1ENA_SHIFT 16 /**< Shift value for MODEM_ADFSMCOND1ENA */
+#define _MODEM_ADFSM14_ADFSMCOND1ENA_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADFSMCOND1ENA */
+#define _MODEM_ADFSM14_ADFSMCOND1ENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM14 */
+#define MODEM_ADFSM14_ADFSMCOND1ENA_DEFAULT (_MODEM_ADFSM14_ADFSMCOND1ENA_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM14 */
+
+/* Bit fields for MODEM ADFSM15 */
+#define _MODEM_ADFSM15_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM15 */
+#define _MODEM_ADFSM15_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM15 */
+#define _MODEM_ADFSM15_ADFSMCOND2ENA_SHIFT 0 /**< Shift value for MODEM_ADFSMCOND2ENA */
+#define _MODEM_ADFSM15_ADFSMCOND2ENA_MASK 0xFFFFUL /**< Bit mask for MODEM_ADFSMCOND2ENA */
+#define _MODEM_ADFSM15_ADFSMCOND2ENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM15 */
+#define MODEM_ADFSM15_ADFSMCOND2ENA_DEFAULT (_MODEM_ADFSM15_ADFSMCOND2ENA_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM15 */
+#define _MODEM_ADFSM15_ADFSMCOND3ENA_SHIFT 16 /**< Shift value for MODEM_ADFSMCOND3ENA */
+#define _MODEM_ADFSM15_ADFSMCOND3ENA_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADFSMCOND3ENA */
+#define _MODEM_ADFSM15_ADFSMCOND3ENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM15 */
+#define MODEM_ADFSM15_ADFSMCOND3ENA_DEFAULT (_MODEM_ADFSM15_ADFSMCOND3ENA_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM15 */
+
+/* Bit fields for MODEM ADFSM16 */
+#define _MODEM_ADFSM16_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM16 */
+#define _MODEM_ADFSM16_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM16 */
+#define _MODEM_ADFSM16_ADFSMCOND0ENB_SHIFT 0 /**< Shift value for MODEM_ADFSMCOND0ENB */
+#define _MODEM_ADFSM16_ADFSMCOND0ENB_MASK 0xFFFFUL /**< Bit mask for MODEM_ADFSMCOND0ENB */
+#define _MODEM_ADFSM16_ADFSMCOND0ENB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM16 */
+#define MODEM_ADFSM16_ADFSMCOND0ENB_DEFAULT (_MODEM_ADFSM16_ADFSMCOND0ENB_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM16 */
+#define _MODEM_ADFSM16_ADFSMCOND1ENB_SHIFT 16 /**< Shift value for MODEM_ADFSMCOND1ENB */
+#define _MODEM_ADFSM16_ADFSMCOND1ENB_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADFSMCOND1ENB */
+#define _MODEM_ADFSM16_ADFSMCOND1ENB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM16 */
+#define MODEM_ADFSM16_ADFSMCOND1ENB_DEFAULT (_MODEM_ADFSM16_ADFSMCOND1ENB_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM16 */
+
+/* Bit fields for MODEM ADFSM17 */
+#define _MODEM_ADFSM17_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM17 */
+#define _MODEM_ADFSM17_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM17 */
+#define _MODEM_ADFSM17_ADFSMCOND2ENB_SHIFT 0 /**< Shift value for MODEM_ADFSMCOND2ENB */
+#define _MODEM_ADFSM17_ADFSMCOND2ENB_MASK 0xFFFFUL /**< Bit mask for MODEM_ADFSMCOND2ENB */
+#define _MODEM_ADFSM17_ADFSMCOND2ENB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM17 */
+#define MODEM_ADFSM17_ADFSMCOND2ENB_DEFAULT (_MODEM_ADFSM17_ADFSMCOND2ENB_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM17 */
+#define _MODEM_ADFSM17_ADFSMCOND3ENB_SHIFT 16 /**< Shift value for MODEM_ADFSMCOND3ENB */
+#define _MODEM_ADFSM17_ADFSMCOND3ENB_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADFSMCOND3ENB */
+#define _MODEM_ADFSM17_ADFSMCOND3ENB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM17 */
+#define MODEM_ADFSM17_ADFSMCOND3ENB_DEFAULT (_MODEM_ADFSM17_ADFSMCOND3ENB_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM17 */
+
+/* Bit fields for MODEM ADFSM18 */
+#define _MODEM_ADFSM18_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM18 */
+#define _MODEM_ADFSM18_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM18 */
+#define _MODEM_ADFSM18_ADFSMCONDSEL_SHIFT 0 /**< Shift value for MODEM_ADFSMCONDSEL */
+#define _MODEM_ADFSM18_ADFSMCONDSEL_MASK 0xFFFFFFFFUL /**< Bit mask for MODEM_ADFSMCONDSEL */
+#define _MODEM_ADFSM18_ADFSMCONDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM18 */
+#define MODEM_ADFSM18_ADFSMCONDSEL_DEFAULT (_MODEM_ADFSM18_ADFSMCONDSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM18 */
+
+/* Bit fields for MODEM ADFSM19 */
+#define _MODEM_ADFSM19_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM19 */
+#define _MODEM_ADFSM19_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM19 */
+#define _MODEM_ADFSM19_ADFSMNEXTFORCE_SHIFT 0 /**< Shift value for MODEM_ADFSMNEXTFORCE */
+#define _MODEM_ADFSM19_ADFSMNEXTFORCE_MASK 0xFFFFUL /**< Bit mask for MODEM_ADFSMNEXTFORCE */
+#define _MODEM_ADFSM19_ADFSMNEXTFORCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM19 */
+#define MODEM_ADFSM19_ADFSMNEXTFORCE_DEFAULT (_MODEM_ADFSM19_ADFSMNEXTFORCE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM19 */
+#define _MODEM_ADFSM19_ADFSMCONDTRUE_SHIFT 16 /**< Shift value for MODEM_ADFSMCONDTRUE */
+#define _MODEM_ADFSM19_ADFSMCONDTRUE_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADFSMCONDTRUE */
+#define _MODEM_ADFSM19_ADFSMCONDTRUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM19 */
+#define MODEM_ADFSM19_ADFSMCONDTRUE_DEFAULT (_MODEM_ADFSM19_ADFSMCONDTRUE_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM19 */
+
+/* Bit fields for MODEM ADFSM20 */
+#define _MODEM_ADFSM20_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM20 */
+#define _MODEM_ADFSM20_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM20 */
+#define _MODEM_ADFSM20_ADITENTEREN_SHIFT 0 /**< Shift value for MODEM_ADITENTEREN */
+#define _MODEM_ADFSM20_ADITENTEREN_MASK 0xFFFFUL /**< Bit mask for MODEM_ADITENTEREN */
+#define _MODEM_ADFSM20_ADITENTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM20 */
+#define MODEM_ADFSM20_ADITENTEREN_DEFAULT (_MODEM_ADFSM20_ADITENTEREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM20 */
+#define _MODEM_ADFSM20_ADITLEAVEEN_SHIFT 16 /**< Shift value for MODEM_ADITLEAVEEN */
+#define _MODEM_ADFSM20_ADITLEAVEEN_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADITLEAVEEN */
+#define _MODEM_ADFSM20_ADITLEAVEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM20 */
+#define MODEM_ADFSM20_ADITLEAVEEN_DEFAULT (_MODEM_ADFSM20_ADITLEAVEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM20 */
+
+/* Bit fields for MODEM ADFSM21 */
+#define _MODEM_ADFSM21_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM21 */
+#define _MODEM_ADFSM21_MASK 0x000101FFUL /**< Mask for MODEM_ADFSM21 */
+#define MODEM_ADFSM21_ADENTERFREEZEEN (0x1UL << 0) /**< AD FSM enter freeze enable */
+#define _MODEM_ADFSM21_ADENTERFREEZEEN_SHIFT 0 /**< Shift value for MODEM_ADENTERFREEZEEN */
+#define _MODEM_ADFSM21_ADENTERFREEZEEN_MASK 0x1UL /**< Bit mask for MODEM_ADENTERFREEZEEN */
+#define _MODEM_ADFSM21_ADENTERFREEZEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM21 */
+#define MODEM_ADFSM21_ADENTERFREEZEEN_DEFAULT (_MODEM_ADFSM21_ADENTERFREEZEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM21 */
+#define MODEM_ADFSM21_ADLEAVEFREEZEEN (0x1UL << 1) /**< AD FSM leave freeze enable */
+#define _MODEM_ADFSM21_ADLEAVEFREEZEEN_SHIFT 1 /**< Shift value for MODEM_ADLEAVEFREEZEEN */
+#define _MODEM_ADFSM21_ADLEAVEFREEZEEN_MASK 0x2UL /**< Bit mask for MODEM_ADLEAVEFREEZEEN */
+#define _MODEM_ADFSM21_ADLEAVEFREEZEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM21 */
+#define MODEM_ADFSM21_ADLEAVEFREEZEEN_DEFAULT (_MODEM_ADFSM21_ADLEAVEFREEZEEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_ADFSM21 */
+#define MODEM_ADFSM21_ADFROZEN (0x1UL << 2) /**< AD FSM frozen */
+#define _MODEM_ADFSM21_ADFROZEN_SHIFT 2 /**< Shift value for MODEM_ADFROZEN */
+#define _MODEM_ADFSM21_ADFROZEN_MASK 0x4UL /**< Bit mask for MODEM_ADFROZEN */
+#define _MODEM_ADFSM21_ADFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM21 */
+#define MODEM_ADFSM21_ADFROZEN_DEFAULT (_MODEM_ADFSM21_ADFROZEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_ADFSM21 */
+#define _MODEM_ADFSM21_ADUNFREEZENEXT_SHIFT 3 /**< Shift value for MODEM_ADUNFREEZENEXT */
+#define _MODEM_ADFSM21_ADUNFREEZENEXT_MASK 0x78UL /**< Bit mask for MODEM_ADUNFREEZENEXT */
+#define _MODEM_ADFSM21_ADUNFREEZENEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM21 */
+#define MODEM_ADFSM21_ADUNFREEZENEXT_DEFAULT (_MODEM_ADFSM21_ADUNFREEZENEXT_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_ADFSM21 */
+#define MODEM_ADFSM21_ADAS (0x1UL << 7) /**< antsel */
+#define _MODEM_ADFSM21_ADAS_SHIFT 7 /**< Shift value for MODEM_ADAS */
+#define _MODEM_ADFSM21_ADAS_MASK 0x80UL /**< Bit mask for MODEM_ADAS */
+#define _MODEM_ADFSM21_ADAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM21 */
+#define MODEM_ADFSM21_ADAS_DEFAULT (_MODEM_ADFSM21_ADAS_DEFAULT << 7) /**< Shifted mode DEFAULT for MODEM_ADFSM21 */
+#define MODEM_ADFSM21_ADBA (0x1UL << 8) /**< best_antenna */
+#define _MODEM_ADFSM21_ADBA_SHIFT 8 /**< Shift value for MODEM_ADBA */
+#define _MODEM_ADFSM21_ADBA_MASK 0x100UL /**< Bit mask for MODEM_ADBA */
+#define _MODEM_ADFSM21_ADBA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM21 */
+#define MODEM_ADFSM21_ADBA_DEFAULT (_MODEM_ADFSM21_ADBA_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_ADFSM21 */
+#define MODEM_ADFSM21_ADUNFREEZE (0x1UL << 16) /**< AD FSM unfreeze */
+#define _MODEM_ADFSM21_ADUNFREEZE_SHIFT 16 /**< Shift value for MODEM_ADUNFREEZE */
+#define _MODEM_ADFSM21_ADUNFREEZE_MASK 0x10000UL /**< Bit mask for MODEM_ADUNFREEZE */
+#define _MODEM_ADFSM21_ADUNFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM21 */
+#define MODEM_ADFSM21_ADUNFREEZE_DEFAULT (_MODEM_ADFSM21_ADUNFREEZE_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM21 */
+
+/* Bit fields for MODEM ADFSM22 */
+#define _MODEM_ADFSM22_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM22 */
+#define _MODEM_ADFSM22_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM22 */
+#define _MODEM_ADFSM22_ADITENTERSTATUS_SHIFT 0 /**< Shift value for MODEM_ADITENTERSTATUS */
+#define _MODEM_ADFSM22_ADITENTERSTATUS_MASK 0xFFFFUL /**< Bit mask for MODEM_ADITENTERSTATUS */
+#define _MODEM_ADFSM22_ADITENTERSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM22 */
+#define MODEM_ADFSM22_ADITENTERSTATUS_DEFAULT (_MODEM_ADFSM22_ADITENTERSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM22 */
+#define _MODEM_ADFSM22_ADITLEAVESTATUS_SHIFT 16 /**< Shift value for MODEM_ADITLEAVESTATUS */
+#define _MODEM_ADFSM22_ADITLEAVESTATUS_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADITLEAVESTATUS */
+#define _MODEM_ADFSM22_ADITLEAVESTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM22 */
+#define MODEM_ADFSM22_ADITLEAVESTATUS_DEFAULT (_MODEM_ADFSM22_ADITLEAVESTATUS_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM22 */
+
+/* Bit fields for MODEM ADFSM23 */
+#define _MODEM_ADFSM23_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM23 */
+#define _MODEM_ADFSM23_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM23 */
+#define _MODEM_ADFSM23_ADFSMCOND0ENC_SHIFT 0 /**< Shift value for MODEM_ADFSMCOND0ENC */
+#define _MODEM_ADFSM23_ADFSMCOND0ENC_MASK 0xFFFFUL /**< Bit mask for MODEM_ADFSMCOND0ENC */
+#define _MODEM_ADFSM23_ADFSMCOND0ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM23 */
+#define MODEM_ADFSM23_ADFSMCOND0ENC_DEFAULT (_MODEM_ADFSM23_ADFSMCOND0ENC_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM23 */
+#define _MODEM_ADFSM23_ADFSMCOND1ENC_SHIFT 16 /**< Shift value for MODEM_ADFSMCOND1ENC */
+#define _MODEM_ADFSM23_ADFSMCOND1ENC_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADFSMCOND1ENC */
+#define _MODEM_ADFSM23_ADFSMCOND1ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM23 */
+#define MODEM_ADFSM23_ADFSMCOND1ENC_DEFAULT (_MODEM_ADFSM23_ADFSMCOND1ENC_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM23 */
+
+/* Bit fields for MODEM ADFSM24 */
+#define _MODEM_ADFSM24_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM24 */
+#define _MODEM_ADFSM24_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM24 */
+#define _MODEM_ADFSM24_ADFSMCOND2ENC_SHIFT 0 /**< Shift value for MODEM_ADFSMCOND2ENC */
+#define _MODEM_ADFSM24_ADFSMCOND2ENC_MASK 0xFFFFUL /**< Bit mask for MODEM_ADFSMCOND2ENC */
+#define _MODEM_ADFSM24_ADFSMCOND2ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM24 */
+#define MODEM_ADFSM24_ADFSMCOND2ENC_DEFAULT (_MODEM_ADFSM24_ADFSMCOND2ENC_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM24 */
+#define _MODEM_ADFSM24_ADFSMCOND3ENC_SHIFT 16 /**< Shift value for MODEM_ADFSMCOND3ENC */
+#define _MODEM_ADFSM24_ADFSMCOND3ENC_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADFSMCOND3ENC */
+#define _MODEM_ADFSM24_ADFSMCOND3ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM24 */
+#define MODEM_ADFSM24_ADFSMCOND3ENC_DEFAULT (_MODEM_ADFSM24_ADFSMCOND3ENC_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM24 */
+
+/* Bit fields for MODEM ADFSM25 */
+#define _MODEM_ADFSM25_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM25 */
+#define _MODEM_ADFSM25_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM25 */
+#define _MODEM_ADFSM25_ADFSMCONDOR0_SHIFT 0 /**< Shift value for MODEM_ADFSMCONDOR0 */
+#define _MODEM_ADFSM25_ADFSMCONDOR0_MASK 0xFFFFUL /**< Bit mask for MODEM_ADFSMCONDOR0 */
+#define _MODEM_ADFSM25_ADFSMCONDOR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM25 */
+#define MODEM_ADFSM25_ADFSMCONDOR0_DEFAULT (_MODEM_ADFSM25_ADFSMCONDOR0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM25 */
+#define _MODEM_ADFSM25_ADFSMCONDOR1_SHIFT 16 /**< Shift value for MODEM_ADFSMCONDOR1 */
+#define _MODEM_ADFSM25_ADFSMCONDOR1_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADFSMCONDOR1 */
+#define _MODEM_ADFSM25_ADFSMCONDOR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM25 */
+#define MODEM_ADFSM25_ADFSMCONDOR1_DEFAULT (_MODEM_ADFSM25_ADFSMCONDOR1_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM25 */
+
+/* Bit fields for MODEM ADFSM26 */
+#define _MODEM_ADFSM26_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM26 */
+#define _MODEM_ADFSM26_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM26 */
+#define _MODEM_ADFSM26_ADFSMCOND0END_SHIFT 0 /**< Shift value for MODEM_ADFSMCOND0END */
+#define _MODEM_ADFSM26_ADFSMCOND0END_MASK 0xFFFFUL /**< Bit mask for MODEM_ADFSMCOND0END */
+#define _MODEM_ADFSM26_ADFSMCOND0END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM26 */
+#define MODEM_ADFSM26_ADFSMCOND0END_DEFAULT (_MODEM_ADFSM26_ADFSMCOND0END_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM26 */
+#define _MODEM_ADFSM26_ADFSMCOND1END_SHIFT 16 /**< Shift value for MODEM_ADFSMCOND1END */
+#define _MODEM_ADFSM26_ADFSMCOND1END_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADFSMCOND1END */
+#define _MODEM_ADFSM26_ADFSMCOND1END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM26 */
+#define MODEM_ADFSM26_ADFSMCOND1END_DEFAULT (_MODEM_ADFSM26_ADFSMCOND1END_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM26 */
+
+/* Bit fields for MODEM ADFSM27 */
+#define _MODEM_ADFSM27_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM27 */
+#define _MODEM_ADFSM27_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM27 */
+#define _MODEM_ADFSM27_ADFSMCOND2END_SHIFT 0 /**< Shift value for MODEM_ADFSMCOND2END */
+#define _MODEM_ADFSM27_ADFSMCOND2END_MASK 0xFFFFUL /**< Bit mask for MODEM_ADFSMCOND2END */
+#define _MODEM_ADFSM27_ADFSMCOND2END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM27 */
+#define MODEM_ADFSM27_ADFSMCOND2END_DEFAULT (_MODEM_ADFSM27_ADFSMCOND2END_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM27 */
+#define _MODEM_ADFSM27_ADFSMCOND3END_SHIFT 16 /**< Shift value for MODEM_ADFSMCOND3END */
+#define _MODEM_ADFSM27_ADFSMCOND3END_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADFSMCOND3END */
+#define _MODEM_ADFSM27_ADFSMCOND3END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM27 */
+#define MODEM_ADFSM27_ADFSMCOND3END_DEFAULT (_MODEM_ADFSM27_ADFSMCOND3END_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM27 */
+
+/* Bit fields for MODEM ADFSM28 */
+#define _MODEM_ADFSM28_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM28 */
+#define _MODEM_ADFSM28_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM28 */
+#define _MODEM_ADFSM28_ADOSETANTFORCE_SHIFT 0 /**< Shift value for MODEM_ADOSETANTFORCE */
+#define _MODEM_ADFSM28_ADOSETANTFORCE_MASK 0xFFFFUL /**< Bit mask for MODEM_ADOSETANTFORCE */
+#define _MODEM_ADFSM28_ADOSETANTFORCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM28 */
+#define MODEM_ADFSM28_ADOSETANTFORCE_DEFAULT (_MODEM_ADFSM28_ADOSETANTFORCE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM28 */
+#define _MODEM_ADFSM28_ADORESTARTRXFORCE_SHIFT 16 /**< Shift value for MODEM_ADORESTARTRXFORCE */
+#define _MODEM_ADFSM28_ADORESTARTRXFORCE_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADORESTARTRXFORCE */
+#define _MODEM_ADFSM28_ADORESTARTRXFORCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM28 */
+#define MODEM_ADFSM28_ADORESTARTRXFORCE_DEFAULT (_MODEM_ADFSM28_ADORESTARTRXFORCE_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM28 */
+
+/* Bit fields for MODEM ADFSM29 */
+#define _MODEM_ADFSM29_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM29 */
+#define _MODEM_ADFSM29_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM29 */
+#define _MODEM_ADFSM29_ADOQUALUPDATEFORCE_SHIFT 0 /**< Shift value for MODEM_ADOQUALUPDATEFORCE */
+#define _MODEM_ADFSM29_ADOQUALUPDATEFORCE_MASK 0xFFFFUL /**< Bit mask for MODEM_ADOQUALUPDATEFORCE */
+#define _MODEM_ADFSM29_ADOQUALUPDATEFORCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM29 */
+#define MODEM_ADFSM29_ADOQUALUPDATEFORCE_DEFAULT (_MODEM_ADFSM29_ADOQUALUPDATEFORCE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM29 */
+#define _MODEM_ADFSM29_ADOQUALCLEARFORCE_SHIFT 16 /**< Shift value for MODEM_ADOQUALCLEARFORCE */
+#define _MODEM_ADFSM29_ADOQUALCLEARFORCE_MASK 0xFFFF0000UL /**< Bit mask for MODEM_ADOQUALCLEARFORCE */
+#define _MODEM_ADFSM29_ADOQUALCLEARFORCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM29 */
+#define MODEM_ADFSM29_ADOQUALCLEARFORCE_DEFAULT (_MODEM_ADFSM29_ADOQUALCLEARFORCE_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADFSM29 */
+
+/* Bit fields for MODEM ADFSM30 */
+#define _MODEM_ADFSM30_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADFSM30 */
+#define _MODEM_ADFSM30_MASK 0xFFFFFFFFUL /**< Mask for MODEM_ADFSM30 */
+#define _MODEM_ADFSM30_ADODEMODRXREQ_SHIFT 0 /**< Shift value for MODEM_ADODEMODRXREQ */
+#define _MODEM_ADFSM30_ADODEMODRXREQ_MASK 0xFFFFFFFFUL /**< Bit mask for MODEM_ADODEMODRXREQ */
+#define _MODEM_ADFSM30_ADODEMODRXREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADFSM30 */
+#define MODEM_ADFSM30_ADODEMODRXREQ_DEFAULT (_MODEM_ADFSM30_ADODEMODRXREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADFSM30 */
+
+/* Bit fields for MODEM ADPC1 */
+#define _MODEM_ADPC1_RESETVALUE 0x01200040UL /**< Default value for MODEM_ADPC1 */
+#define _MODEM_ADPC1_MASK 0xFFFF7FFFUL /**< Mask for MODEM_ADPC1 */
+#define MODEM_ADPC1_ADPCEN (0x1UL << 0) /**< ADPC enable */
+#define _MODEM_ADPC1_ADPCEN_SHIFT 0 /**< Shift value for MODEM_ADPCEN */
+#define _MODEM_ADPC1_ADPCEN_MASK 0x1UL /**< Bit mask for MODEM_ADPCEN */
+#define _MODEM_ADPC1_ADPCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC1 */
+#define MODEM_ADPC1_ADPCEN_DEFAULT (_MODEM_ADPC1_ADPCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADPC1 */
+#define _MODEM_ADPC1_ADPCWNDSIZECHIP_SHIFT 1 /**< Shift value for MODEM_ADPCWNDSIZECHIP */
+#define _MODEM_ADPC1_ADPCWNDSIZECHIP_MASK 0xFEUL /**< Bit mask for MODEM_ADPCWNDSIZECHIP */
+#define _MODEM_ADPC1_ADPCWNDSIZECHIP_DEFAULT 0x00000020UL /**< Mode DEFAULT for MODEM_ADPC1 */
+#define MODEM_ADPC1_ADPCWNDSIZECHIP_DEFAULT (_MODEM_ADPC1_ADPCWNDSIZECHIP_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_ADPC1 */
+#define _MODEM_ADPC1_ADPCCORROFFSETCHIP_SHIFT 8 /**< Shift value for MODEM_ADPCCORROFFSETCHIP */
+#define _MODEM_ADPC1_ADPCCORROFFSETCHIP_MASK 0x7F00UL /**< Bit mask for MODEM_ADPCCORROFFSETCHIP */
+#define _MODEM_ADPC1_ADPCCORROFFSETCHIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC1 */
+#define MODEM_ADPC1_ADPCCORROFFSETCHIP_DEFAULT (_MODEM_ADPC1_ADPCCORROFFSETCHIP_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_ADPC1 */
+#define _MODEM_ADPC1_ADPCTIMINGBAUDS_SHIFT 16 /**< Shift value for MODEM_ADPCTIMINGBAUDS */
+#define _MODEM_ADPC1_ADPCTIMINGBAUDS_MASK 0xFF0000UL /**< Bit mask for MODEM_ADPCTIMINGBAUDS */
+#define _MODEM_ADPC1_ADPCTIMINGBAUDS_DEFAULT 0x00000020UL /**< Mode DEFAULT for MODEM_ADPC1 */
+#define MODEM_ADPC1_ADPCTIMINGBAUDS_DEFAULT (_MODEM_ADPC1_ADPCTIMINGBAUDS_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADPC1 */
+#define _MODEM_ADPC1_ADPCWNDCNT_SHIFT 24 /**< Shift value for MODEM_ADPCWNDCNT */
+#define _MODEM_ADPC1_ADPCWNDCNT_MASK 0x7000000UL /**< Bit mask for MODEM_ADPCWNDCNT */
+#define _MODEM_ADPC1_ADPCWNDCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_ADPC1 */
+#define MODEM_ADPC1_ADPCWNDCNT_DEFAULT (_MODEM_ADPC1_ADPCWNDCNT_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_ADPC1 */
+#define _MODEM_ADPC1_ADPCSKIPCHIPS_SHIFT 27 /**< Shift value for MODEM_ADPCSKIPCHIPS */
+#define _MODEM_ADPC1_ADPCSKIPCHIPS_MASK 0xF8000000UL /**< Bit mask for MODEM_ADPCSKIPCHIPS */
+#define _MODEM_ADPC1_ADPCSKIPCHIPS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC1 */
+#define MODEM_ADPC1_ADPCSKIPCHIPS_DEFAULT (_MODEM_ADPC1_ADPCSKIPCHIPS_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_ADPC1 */
+
+/* Bit fields for MODEM ADPC2 */
+#define _MODEM_ADPC2_RESETVALUE 0x000000A0UL /**< Default value for MODEM_ADPC2 */
+#define _MODEM_ADPC2_MASK 0x3FFFFFFFUL /**< Mask for MODEM_ADPC2 */
+#define _MODEM_ADPC2_ADPCCORRSAMPLES_SHIFT 0 /**< Shift value for MODEM_ADPCCORRSAMPLES */
+#define _MODEM_ADPC2_ADPCCORRSAMPLES_MASK 0x3FFUL /**< Bit mask for MODEM_ADPCCORRSAMPLES */
+#define _MODEM_ADPC2_ADPCCORRSAMPLES_DEFAULT 0x000000A0UL /**< Mode DEFAULT for MODEM_ADPC2 */
+#define MODEM_ADPC2_ADPCCORRSAMPLES_DEFAULT (_MODEM_ADPC2_ADPCCORRSAMPLES_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADPC2 */
+#define _MODEM_ADPC2_ADPCPRETIMINGBAUDS_SHIFT 10 /**< Shift value for MODEM_ADPCPRETIMINGBAUDS */
+#define _MODEM_ADPC2_ADPCPRETIMINGBAUDS_MASK 0x3FC00UL /**< Bit mask for MODEM_ADPCPRETIMINGBAUDS */
+#define _MODEM_ADPC2_ADPCPRETIMINGBAUDS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC2 */
+#define MODEM_ADPC2_ADPCPRETIMINGBAUDS_DEFAULT (_MODEM_ADPC2_ADPCPRETIMINGBAUDS_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_ADPC2 */
+#define MODEM_ADPC2_ADENCORR32 (0x1UL << 18) /**< ADPC enable correlators 16-31 */
+#define _MODEM_ADPC2_ADENCORR32_SHIFT 18 /**< Shift value for MODEM_ADENCORR32 */
+#define _MODEM_ADPC2_ADENCORR32_MASK 0x40000UL /**< Bit mask for MODEM_ADENCORR32 */
+#define _MODEM_ADPC2_ADENCORR32_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC2 */
+#define _MODEM_ADPC2_ADENCORR32_DISABLE 0x00000000UL /**< Mode DISABLE for MODEM_ADPC2 */
+#define _MODEM_ADPC2_ADENCORR32_ENABLE 0x00000001UL /**< Mode ENABLE for MODEM_ADPC2 */
+#define MODEM_ADPC2_ADENCORR32_DEFAULT (_MODEM_ADPC2_ADENCORR32_DEFAULT << 18) /**< Shifted mode DEFAULT for MODEM_ADPC2 */
+#define MODEM_ADPC2_ADENCORR32_DISABLE (_MODEM_ADPC2_ADENCORR32_DISABLE << 18) /**< Shifted mode DISABLE for MODEM_ADPC2 */
+#define MODEM_ADPC2_ADENCORR32_ENABLE (_MODEM_ADPC2_ADENCORR32_ENABLE << 18) /**< Shifted mode ENABLE for MODEM_ADPC2 */
+#define _MODEM_ADPC2_ADPCSIGAMPTHR_SHIFT 19 /**< Shift value for MODEM_ADPCSIGAMPTHR */
+#define _MODEM_ADPC2_ADPCSIGAMPTHR_MASK 0x7F80000UL /**< Bit mask for MODEM_ADPCSIGAMPTHR */
+#define _MODEM_ADPC2_ADPCSIGAMPTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC2 */
+#define MODEM_ADPC2_ADPCSIGAMPTHR_DEFAULT (_MODEM_ADPC2_ADPCSIGAMPTHR_DEFAULT << 19) /**< Shifted mode DEFAULT for MODEM_ADPC2 */
+#define _MODEM_ADPC2_ADPCWNDCNTRST_SHIFT 27 /**< Shift value for MODEM_ADPCWNDCNTRST */
+#define _MODEM_ADPC2_ADPCWNDCNTRST_MASK 0x38000000UL /**< Bit mask for MODEM_ADPCWNDCNTRST */
+#define _MODEM_ADPC2_ADPCWNDCNTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC2 */
+#define MODEM_ADPC2_ADPCWNDCNTRST_DEFAULT (_MODEM_ADPC2_ADPCWNDCNTRST_DEFAULT << 27) /**< Shifted mode DEFAULT for MODEM_ADPC2 */
+
+/* Bit fields for MODEM ADPC3 */
+#define _MODEM_ADPC3_RESETVALUE 0x01005008UL /**< Default value for MODEM_ADPC3 */
+#define _MODEM_ADPC3_MASK 0x03FFFFFFUL /**< Mask for MODEM_ADPC3 */
+#define MODEM_ADPC3_ADBBSSEN (0x1UL << 0) /**< ADBBSS enable */
+#define _MODEM_ADPC3_ADBBSSEN_SHIFT 0 /**< Shift value for MODEM_ADBBSSEN */
+#define _MODEM_ADPC3_ADBBSSEN_MASK 0x1UL /**< Bit mask for MODEM_ADBBSSEN */
+#define _MODEM_ADPC3_ADBBSSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC3 */
+#define MODEM_ADPC3_ADBBSSEN_DEFAULT (_MODEM_ADPC3_ADBBSSEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADPC3 */
+#define _MODEM_ADPC3_ADBBSSFILTLENGTH_SHIFT 1 /**< Shift value for MODEM_ADBBSSFILTLENGTH */
+#define _MODEM_ADPC3_ADBBSSFILTLENGTH_MASK 0xEUL /**< Bit mask for MODEM_ADBBSSFILTLENGTH */
+#define _MODEM_ADPC3_ADBBSSFILTLENGTH_DEFAULT 0x00000004UL /**< Mode DEFAULT for MODEM_ADPC3 */
+#define MODEM_ADPC3_ADBBSSFILTLENGTH_DEFAULT (_MODEM_ADPC3_ADBBSSFILTLENGTH_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_ADPC3 */
+#define MODEM_ADPC3_ADBBSSAVGEN (0x1UL << 4) /**< ADBBSS average enable */
+#define _MODEM_ADPC3_ADBBSSAVGEN_SHIFT 4 /**< Shift value for MODEM_ADBBSSAVGEN */
+#define _MODEM_ADPC3_ADBBSSAVGEN_MASK 0x10UL /**< Bit mask for MODEM_ADBBSSAVGEN */
+#define _MODEM_ADPC3_ADBBSSAVGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC3 */
+#define MODEM_ADPC3_ADBBSSAVGEN_DEFAULT (_MODEM_ADPC3_ADBBSSAVGEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_ADPC3 */
+#define _MODEM_ADPC3_ADBBSSAVGPER_SHIFT 5 /**< Shift value for MODEM_ADBBSSAVGPER */
+#define _MODEM_ADPC3_ADBBSSAVGPER_MASK 0xE0UL /**< Bit mask for MODEM_ADBBSSAVGPER */
+#define _MODEM_ADPC3_ADBBSSAVGPER_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC3 */
+#define MODEM_ADPC3_ADBBSSAVGPER_DEFAULT (_MODEM_ADPC3_ADBBSSAVGPER_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_ADPC3 */
+#define _MODEM_ADPC3_ADBBSSAMPMANT_SHIFT 8 /**< Shift value for MODEM_ADBBSSAMPMANT */
+#define _MODEM_ADPC3_ADBBSSAMPMANT_MASK 0xF00UL /**< Bit mask for MODEM_ADBBSSAMPMANT */
+#define _MODEM_ADPC3_ADBBSSAMPMANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC3 */
+#define MODEM_ADPC3_ADBBSSAMPMANT_DEFAULT (_MODEM_ADPC3_ADBBSSAMPMANT_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_ADPC3 */
+#define _MODEM_ADPC3_ADBBSSAMPEXP_SHIFT 12 /**< Shift value for MODEM_ADBBSSAMPEXP */
+#define _MODEM_ADPC3_ADBBSSAMPEXP_MASK 0xF000UL /**< Bit mask for MODEM_ADBBSSAMPEXP */
+#define _MODEM_ADPC3_ADBBSSAMPEXP_DEFAULT 0x00000005UL /**< Mode DEFAULT for MODEM_ADPC3 */
+#define MODEM_ADPC3_ADBBSSAMPEXP_DEFAULT (_MODEM_ADPC3_ADBBSSAMPEXP_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_ADPC3 */
+#define _MODEM_ADPC3_ADBBSSAVGWAIT_SHIFT 16 /**< Shift value for MODEM_ADBBSSAVGWAIT */
+#define _MODEM_ADPC3_ADBBSSAVGWAIT_MASK 0xFF0000UL /**< Bit mask for MODEM_ADBBSSAVGWAIT */
+#define _MODEM_ADPC3_ADBBSSAVGWAIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC3 */
+#define MODEM_ADPC3_ADBBSSAVGWAIT_DEFAULT (_MODEM_ADPC3_ADBBSSAVGWAIT_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADPC3 */
+#define MODEM_ADPC3_ADBBSSAVGFREEZE (0x1UL << 24) /**< ADBBSS average freeze */
+#define _MODEM_ADPC3_ADBBSSAVGFREEZE_SHIFT 24 /**< Shift value for MODEM_ADBBSSAVGFREEZE */
+#define _MODEM_ADPC3_ADBBSSAVGFREEZE_MASK 0x1000000UL /**< Bit mask for MODEM_ADBBSSAVGFREEZE */
+#define _MODEM_ADPC3_ADBBSSAVGFREEZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_ADPC3 */
+#define MODEM_ADPC3_ADBBSSAVGFREEZE_DEFAULT (_MODEM_ADPC3_ADBBSSAVGFREEZE_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_ADPC3 */
+#define MODEM_ADPC3_ADBBSSSELWRDATA (0x1UL << 25) /**< ADBBSS select RAM write data */
+#define _MODEM_ADPC3_ADBBSSSELWRDATA_SHIFT 25 /**< Shift value for MODEM_ADBBSSSELWRDATA */
+#define _MODEM_ADPC3_ADBBSSSELWRDATA_MASK 0x2000000UL /**< Bit mask for MODEM_ADBBSSSELWRDATA */
+#define _MODEM_ADPC3_ADBBSSSELWRDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC3 */
+#define _MODEM_ADPC3_ADBBSSSELWRDATA_ADBBSS 0x00000000UL /**< Mode ADBBSS for MODEM_ADPC3 */
+#define _MODEM_ADPC3_ADBBSSSELWRDATA_DATAFILTER 0x00000001UL /**< Mode DATAFILTER for MODEM_ADPC3 */
+#define MODEM_ADPC3_ADBBSSSELWRDATA_DEFAULT (_MODEM_ADPC3_ADBBSSSELWRDATA_DEFAULT << 25) /**< Shifted mode DEFAULT for MODEM_ADPC3 */
+#define MODEM_ADPC3_ADBBSSSELWRDATA_ADBBSS (_MODEM_ADPC3_ADBBSSSELWRDATA_ADBBSS << 25) /**< Shifted mode ADBBSS for MODEM_ADPC3 */
+#define MODEM_ADPC3_ADBBSSSELWRDATA_DATAFILTER (_MODEM_ADPC3_ADBBSSSELWRDATA_DATAFILTER << 25) /**< Shifted mode DATAFILTER for MODEM_ADPC3 */
+
+/* Bit fields for MODEM ADPC4 */
+#define _MODEM_ADPC4_RESETVALUE 0x1F1F1F1FUL /**< Default value for MODEM_ADPC4 */
+#define _MODEM_ADPC4_MASK 0x1F1F1F1FUL /**< Mask for MODEM_ADPC4 */
+#define _MODEM_ADPC4_ADBBSSAMPLUT0_SHIFT 0 /**< Shift value for MODEM_ADBBSSAMPLUT0 */
+#define _MODEM_ADPC4_ADBBSSAMPLUT0_MASK 0x1FUL /**< Bit mask for MODEM_ADBBSSAMPLUT0 */
+#define _MODEM_ADPC4_ADBBSSAMPLUT0_DEFAULT 0x0000001FUL /**< Mode DEFAULT for MODEM_ADPC4 */
+#define MODEM_ADPC4_ADBBSSAMPLUT0_DEFAULT (_MODEM_ADPC4_ADBBSSAMPLUT0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADPC4 */
+#define _MODEM_ADPC4_ADBBSSAMPLUT1_SHIFT 8 /**< Shift value for MODEM_ADBBSSAMPLUT1 */
+#define _MODEM_ADPC4_ADBBSSAMPLUT1_MASK 0x1F00UL /**< Bit mask for MODEM_ADBBSSAMPLUT1 */
+#define _MODEM_ADPC4_ADBBSSAMPLUT1_DEFAULT 0x0000001FUL /**< Mode DEFAULT for MODEM_ADPC4 */
+#define MODEM_ADPC4_ADBBSSAMPLUT1_DEFAULT (_MODEM_ADPC4_ADBBSSAMPLUT1_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_ADPC4 */
+#define _MODEM_ADPC4_ADBBSSAMPLUT2_SHIFT 16 /**< Shift value for MODEM_ADBBSSAMPLUT2 */
+#define _MODEM_ADPC4_ADBBSSAMPLUT2_MASK 0x1F0000UL /**< Bit mask for MODEM_ADBBSSAMPLUT2 */
+#define _MODEM_ADPC4_ADBBSSAMPLUT2_DEFAULT 0x0000001FUL /**< Mode DEFAULT for MODEM_ADPC4 */
+#define MODEM_ADPC4_ADBBSSAMPLUT2_DEFAULT (_MODEM_ADPC4_ADBBSSAMPLUT2_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADPC4 */
+#define _MODEM_ADPC4_ADBBSSAMPLUT3_SHIFT 24 /**< Shift value for MODEM_ADBBSSAMPLUT3 */
+#define _MODEM_ADPC4_ADBBSSAMPLUT3_MASK 0x1F000000UL /**< Bit mask for MODEM_ADBBSSAMPLUT3 */
+#define _MODEM_ADPC4_ADBBSSAMPLUT3_DEFAULT 0x0000001FUL /**< Mode DEFAULT for MODEM_ADPC4 */
+#define MODEM_ADPC4_ADBBSSAMPLUT3_DEFAULT (_MODEM_ADPC4_ADBBSSAMPLUT3_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_ADPC4 */
+
+/* Bit fields for MODEM ADPC5 */
+#define _MODEM_ADPC5_RESETVALUE 0x1B1F1F1FUL /**< Default value for MODEM_ADPC5 */
+#define _MODEM_ADPC5_MASK 0x1F1F1F1FUL /**< Mask for MODEM_ADPC5 */
+#define _MODEM_ADPC5_ADBBSSAMPLUT4_SHIFT 0 /**< Shift value for MODEM_ADBBSSAMPLUT4 */
+#define _MODEM_ADPC5_ADBBSSAMPLUT4_MASK 0x1FUL /**< Bit mask for MODEM_ADBBSSAMPLUT4 */
+#define _MODEM_ADPC5_ADBBSSAMPLUT4_DEFAULT 0x0000001FUL /**< Mode DEFAULT for MODEM_ADPC5 */
+#define MODEM_ADPC5_ADBBSSAMPLUT4_DEFAULT (_MODEM_ADPC5_ADBBSSAMPLUT4_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADPC5 */
+#define _MODEM_ADPC5_ADBBSSAMPLUT5_SHIFT 8 /**< Shift value for MODEM_ADBBSSAMPLUT5 */
+#define _MODEM_ADPC5_ADBBSSAMPLUT5_MASK 0x1F00UL /**< Bit mask for MODEM_ADBBSSAMPLUT5 */
+#define _MODEM_ADPC5_ADBBSSAMPLUT5_DEFAULT 0x0000001FUL /**< Mode DEFAULT for MODEM_ADPC5 */
+#define MODEM_ADPC5_ADBBSSAMPLUT5_DEFAULT (_MODEM_ADPC5_ADBBSSAMPLUT5_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_ADPC5 */
+#define _MODEM_ADPC5_ADBBSSAMPLUT6_SHIFT 16 /**< Shift value for MODEM_ADBBSSAMPLUT6 */
+#define _MODEM_ADPC5_ADBBSSAMPLUT6_MASK 0x1F0000UL /**< Bit mask for MODEM_ADBBSSAMPLUT6 */
+#define _MODEM_ADPC5_ADBBSSAMPLUT6_DEFAULT 0x0000001FUL /**< Mode DEFAULT for MODEM_ADPC5 */
+#define MODEM_ADPC5_ADBBSSAMPLUT6_DEFAULT (_MODEM_ADPC5_ADBBSSAMPLUT6_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADPC5 */
+#define _MODEM_ADPC5_ADBBSSAMPLUT7_SHIFT 24 /**< Shift value for MODEM_ADBBSSAMPLUT7 */
+#define _MODEM_ADPC5_ADBBSSAMPLUT7_MASK 0x1F000000UL /**< Bit mask for MODEM_ADBBSSAMPLUT7 */
+#define _MODEM_ADPC5_ADBBSSAMPLUT7_DEFAULT 0x0000001BUL /**< Mode DEFAULT for MODEM_ADPC5 */
+#define MODEM_ADPC5_ADBBSSAMPLUT7_DEFAULT (_MODEM_ADPC5_ADBBSSAMPLUT7_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_ADPC5 */
+
+/* Bit fields for MODEM ADPC6 */
+#define _MODEM_ADPC6_RESETVALUE 0x11131518UL /**< Default value for MODEM_ADPC6 */
+#define _MODEM_ADPC6_MASK 0x1F1F1F1FUL /**< Mask for MODEM_ADPC6 */
+#define _MODEM_ADPC6_ADBBSSAMPLUT8_SHIFT 0 /**< Shift value for MODEM_ADBBSSAMPLUT8 */
+#define _MODEM_ADPC6_ADBBSSAMPLUT8_MASK 0x1FUL /**< Bit mask for MODEM_ADBBSSAMPLUT8 */
+#define _MODEM_ADPC6_ADBBSSAMPLUT8_DEFAULT 0x00000018UL /**< Mode DEFAULT for MODEM_ADPC6 */
+#define MODEM_ADPC6_ADBBSSAMPLUT8_DEFAULT (_MODEM_ADPC6_ADBBSSAMPLUT8_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADPC6 */
+#define _MODEM_ADPC6_ADBBSSAMPLUT9_SHIFT 8 /**< Shift value for MODEM_ADBBSSAMPLUT9 */
+#define _MODEM_ADPC6_ADBBSSAMPLUT9_MASK 0x1F00UL /**< Bit mask for MODEM_ADBBSSAMPLUT9 */
+#define _MODEM_ADPC6_ADBBSSAMPLUT9_DEFAULT 0x00000015UL /**< Mode DEFAULT for MODEM_ADPC6 */
+#define MODEM_ADPC6_ADBBSSAMPLUT9_DEFAULT (_MODEM_ADPC6_ADBBSSAMPLUT9_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_ADPC6 */
+#define _MODEM_ADPC6_ADBBSSAMPLUT10_SHIFT 16 /**< Shift value for MODEM_ADBBSSAMPLUT10 */
+#define _MODEM_ADPC6_ADBBSSAMPLUT10_MASK 0x1F0000UL /**< Bit mask for MODEM_ADBBSSAMPLUT10 */
+#define _MODEM_ADPC6_ADBBSSAMPLUT10_DEFAULT 0x00000013UL /**< Mode DEFAULT for MODEM_ADPC6 */
+#define MODEM_ADPC6_ADBBSSAMPLUT10_DEFAULT (_MODEM_ADPC6_ADBBSSAMPLUT10_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADPC6 */
+#define _MODEM_ADPC6_ADBBSSAMPLUT11_SHIFT 24 /**< Shift value for MODEM_ADBBSSAMPLUT11 */
+#define _MODEM_ADPC6_ADBBSSAMPLUT11_MASK 0x1F000000UL /**< Bit mask for MODEM_ADBBSSAMPLUT11 */
+#define _MODEM_ADPC6_ADBBSSAMPLUT11_DEFAULT 0x00000011UL /**< Mode DEFAULT for MODEM_ADPC6 */
+#define MODEM_ADPC6_ADBBSSAMPLUT11_DEFAULT (_MODEM_ADPC6_ADBBSSAMPLUT11_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_ADPC6 */
+
+/* Bit fields for MODEM ADPC7 */
+#define _MODEM_ADPC7_RESETVALUE 0x0C0D0E10UL /**< Default value for MODEM_ADPC7 */
+#define _MODEM_ADPC7_MASK 0x1F1F1F1FUL /**< Mask for MODEM_ADPC7 */
+#define _MODEM_ADPC7_ADBBSSAMPLUT12_SHIFT 0 /**< Shift value for MODEM_ADBBSSAMPLUT12 */
+#define _MODEM_ADPC7_ADBBSSAMPLUT12_MASK 0x1FUL /**< Bit mask for MODEM_ADBBSSAMPLUT12 */
+#define _MODEM_ADPC7_ADBBSSAMPLUT12_DEFAULT 0x00000010UL /**< Mode DEFAULT for MODEM_ADPC7 */
+#define MODEM_ADPC7_ADBBSSAMPLUT12_DEFAULT (_MODEM_ADPC7_ADBBSSAMPLUT12_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADPC7 */
+#define _MODEM_ADPC7_ADBBSSAMPLUT13_SHIFT 8 /**< Shift value for MODEM_ADBBSSAMPLUT13 */
+#define _MODEM_ADPC7_ADBBSSAMPLUT13_MASK 0x1F00UL /**< Bit mask for MODEM_ADBBSSAMPLUT13 */
+#define _MODEM_ADPC7_ADBBSSAMPLUT13_DEFAULT 0x0000000EUL /**< Mode DEFAULT for MODEM_ADPC7 */
+#define MODEM_ADPC7_ADBBSSAMPLUT13_DEFAULT (_MODEM_ADPC7_ADBBSSAMPLUT13_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_ADPC7 */
+#define _MODEM_ADPC7_ADBBSSAMPLUT14_SHIFT 16 /**< Shift value for MODEM_ADBBSSAMPLUT14 */
+#define _MODEM_ADPC7_ADBBSSAMPLUT14_MASK 0x1F0000UL /**< Bit mask for MODEM_ADBBSSAMPLUT14 */
+#define _MODEM_ADPC7_ADBBSSAMPLUT14_DEFAULT 0x0000000DUL /**< Mode DEFAULT for MODEM_ADPC7 */
+#define MODEM_ADPC7_ADBBSSAMPLUT14_DEFAULT (_MODEM_ADPC7_ADBBSSAMPLUT14_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADPC7 */
+#define _MODEM_ADPC7_ADBBSSAMPLUT15_SHIFT 24 /**< Shift value for MODEM_ADBBSSAMPLUT15 */
+#define _MODEM_ADPC7_ADBBSSAMPLUT15_MASK 0x1F000000UL /**< Bit mask for MODEM_ADBBSSAMPLUT15 */
+#define _MODEM_ADPC7_ADBBSSAMPLUT15_DEFAULT 0x0000000CUL /**< Mode DEFAULT for MODEM_ADPC7 */
+#define MODEM_ADPC7_ADBBSSAMPLUT15_DEFAULT (_MODEM_ADPC7_ADBBSSAMPLUT15_DEFAULT << 24) /**< Shifted mode DEFAULT for MODEM_ADPC7 */
+
+/* Bit fields for MODEM ADPC8 */
+#define _MODEM_ADPC8_RESETVALUE 0x2F87C145UL /**< Default value for MODEM_ADPC8 */
+#define _MODEM_ADPC8_MASK 0xFFFFFF7FUL /**< Mask for MODEM_ADPC8 */
+#define _MODEM_ADPC8_ADPCOSR_SHIFT 0 /**< Shift value for MODEM_ADPCOSR */
+#define _MODEM_ADPC8_ADPCOSR_MASK 0x7UL /**< Bit mask for MODEM_ADPCOSR */
+#define _MODEM_ADPC8_ADPCOSR_DEFAULT 0x00000005UL /**< Mode DEFAULT for MODEM_ADPC8 */
+#define MODEM_ADPC8_ADPCOSR_DEFAULT (_MODEM_ADPC8_ADPCOSR_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADPC8 */
+#define _MODEM_ADPC8_ADPCANTSAMPOFFSET_SHIFT 3 /**< Shift value for MODEM_ADPCANTSAMPOFFSET */
+#define _MODEM_ADPC8_ADPCANTSAMPOFFSET_MASK 0x38UL /**< Bit mask for MODEM_ADPCANTSAMPOFFSET */
+#define _MODEM_ADPC8_ADPCANTSAMPOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC8 */
+#define MODEM_ADPC8_ADPCANTSAMPOFFSET_DEFAULT (_MODEM_ADPC8_ADPCANTSAMPOFFSET_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_ADPC8 */
+#define MODEM_ADPC8_ADPCANTSAMPSWITCHWAIT (0x1UL << 6) /**< ADPCANTSAMPSWITCHWAIT */
+#define _MODEM_ADPC8_ADPCANTSAMPSWITCHWAIT_SHIFT 6 /**< Shift value for MODEM_ADPCANTSAMPSWITCHWAIT */
+#define _MODEM_ADPC8_ADPCANTSAMPSWITCHWAIT_MASK 0x40UL /**< Bit mask for MODEM_ADPCANTSAMPSWITCHWAIT */
+#define _MODEM_ADPC8_ADPCANTSAMPSWITCHWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_ADPC8 */
+#define MODEM_ADPC8_ADPCANTSAMPSWITCHWAIT_DEFAULT (_MODEM_ADPC8_ADPCANTSAMPSWITCHWAIT_DEFAULT << 6) /**< Shifted mode DEFAULT for MODEM_ADPC8 */
+#define _MODEM_ADPC8_ADPCANTSAMPBUF_SHIFT 8 /**< Shift value for MODEM_ADPCANTSAMPBUF */
+#define _MODEM_ADPC8_ADPCANTSAMPBUF_MASK 0x3F00UL /**< Bit mask for MODEM_ADPCANTSAMPBUF */
+#define _MODEM_ADPC8_ADPCANTSAMPBUF_DEFAULT 0x00000001UL /**< Mode DEFAULT for MODEM_ADPC8 */
+#define MODEM_ADPC8_ADPCANTSAMPBUF_DEFAULT (_MODEM_ADPC8_ADPCANTSAMPBUF_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_ADPC8 */
+#define _MODEM_ADPC8_ADPCANTSAMPWRITE_SHIFT 14 /**< Shift value for MODEM_ADPCANTSAMPWRITE */
+#define _MODEM_ADPC8_ADPCANTSAMPWRITE_MASK 0x3FC000UL /**< Bit mask for MODEM_ADPCANTSAMPWRITE */
+#define _MODEM_ADPC8_ADPCANTSAMPWRITE_DEFAULT 0x0000001FUL /**< Mode DEFAULT for MODEM_ADPC8 */
+#define MODEM_ADPC8_ADPCANTSAMPWRITE_DEFAULT (_MODEM_ADPC8_ADPCANTSAMPWRITE_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_ADPC8 */
+#define _MODEM_ADPC8_ADPCANTSAMPSWITCH_SHIFT 22 /**< Shift value for MODEM_ADPCANTSAMPSWITCH */
+#define _MODEM_ADPC8_ADPCANTSAMPSWITCH_MASK 0xFFC00000UL /**< Bit mask for MODEM_ADPCANTSAMPSWITCH */
+#define _MODEM_ADPC8_ADPCANTSAMPSWITCH_DEFAULT 0x000000BEUL /**< Mode DEFAULT for MODEM_ADPC8 */
+#define MODEM_ADPC8_ADPCANTSAMPSWITCH_DEFAULT (_MODEM_ADPC8_ADPCANTSAMPSWITCH_DEFAULT << 22) /**< Shifted mode DEFAULT for MODEM_ADPC8 */
+
+/* Bit fields for MODEM ADPC9 */
+#define _MODEM_ADPC9_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADPC9 */
+#define _MODEM_ADPC9_MASK 0x01FFFFFFUL /**< Mask for MODEM_ADPC9 */
+#define _MODEM_ADPC9_ADBBSSAMPAVGLIM_SHIFT 0 /**< Shift value for MODEM_ADBBSSAMPAVGLIM */
+#define _MODEM_ADPC9_ADBBSSAMPAVGLIM_MASK 0xFFUL /**< Bit mask for MODEM_ADBBSSAMPAVGLIM */
+#define _MODEM_ADPC9_ADBBSSAMPAVGLIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC9 */
+#define MODEM_ADPC9_ADBBSSAMPAVGLIM_DEFAULT (_MODEM_ADPC9_ADBBSSAMPAVGLIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADPC9 */
+#define _MODEM_ADPC9_ADBBSSAMPTHR_SHIFT 8 /**< Shift value for MODEM_ADBBSSAMPTHR */
+#define _MODEM_ADPC9_ADBBSSAMPTHR_MASK 0xFF00UL /**< Bit mask for MODEM_ADBBSSAMPTHR */
+#define _MODEM_ADPC9_ADBBSSAMPTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC9 */
+#define MODEM_ADPC9_ADBBSSAMPTHR_DEFAULT (_MODEM_ADPC9_ADBBSSAMPTHR_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_ADPC9 */
+#define MODEM_ADPC9_ADBBSSSYNCEN (0x1UL << 16) /**< Enable sync of BBSS */
+#define _MODEM_ADPC9_ADBBSSSYNCEN_SHIFT 16 /**< Shift value for MODEM_ADBBSSSYNCEN */
+#define _MODEM_ADPC9_ADBBSSSYNCEN_MASK 0x10000UL /**< Bit mask for MODEM_ADBBSSSYNCEN */
+#define _MODEM_ADPC9_ADBBSSSYNCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC9 */
+#define _MODEM_ADPC9_ADBBSSSYNCEN_DISABLE 0x00000000UL /**< Mode DISABLE for MODEM_ADPC9 */
+#define _MODEM_ADPC9_ADBBSSSYNCEN_ENABLE 0x00000001UL /**< Mode ENABLE for MODEM_ADPC9 */
+#define MODEM_ADPC9_ADBBSSSYNCEN_DEFAULT (_MODEM_ADPC9_ADBBSSSYNCEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_ADPC9 */
+#define MODEM_ADPC9_ADBBSSSYNCEN_DISABLE (_MODEM_ADPC9_ADBBSSSYNCEN_DISABLE << 16) /**< Shifted mode DISABLE for MODEM_ADPC9 */
+#define MODEM_ADPC9_ADBBSSSYNCEN_ENABLE (_MODEM_ADPC9_ADBBSSSYNCEN_ENABLE << 16) /**< Shifted mode ENABLE for MODEM_ADPC9 */
+#define _MODEM_ADPC9_ADBBSSUPTHR_SHIFT 17 /**< Shift value for MODEM_ADBBSSUPTHR */
+#define _MODEM_ADPC9_ADBBSSUPTHR_MASK 0x1E0000UL /**< Bit mask for MODEM_ADBBSSUPTHR */
+#define _MODEM_ADPC9_ADBBSSUPTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC9 */
+#define MODEM_ADPC9_ADBBSSUPTHR_DEFAULT (_MODEM_ADPC9_ADBBSSUPTHR_DEFAULT << 17) /**< Shifted mode DEFAULT for MODEM_ADPC9 */
+#define _MODEM_ADPC9_ADBBSSDNTHR_SHIFT 21 /**< Shift value for MODEM_ADBBSSDNTHR */
+#define _MODEM_ADPC9_ADBBSSDNTHR_MASK 0x1E00000UL /**< Bit mask for MODEM_ADBBSSDNTHR */
+#define _MODEM_ADPC9_ADBBSSDNTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC9 */
+#define MODEM_ADPC9_ADBBSSDNTHR_DEFAULT (_MODEM_ADPC9_ADBBSSDNTHR_DEFAULT << 21) /**< Shifted mode DEFAULT for MODEM_ADPC9 */
+
+/* Bit fields for MODEM ADPC10 */
+#define _MODEM_ADPC10_RESETVALUE 0x00000000UL /**< Default value for MODEM_ADPC10 */
+#define _MODEM_ADPC10_MASK 0x0001FFFFUL /**< Mask for MODEM_ADPC10 */
+#define _MODEM_ADPC10_ADBBSSAMPJUMP_SHIFT 0 /**< Shift value for MODEM_ADBBSSAMPJUMP */
+#define _MODEM_ADPC10_ADBBSSAMPJUMP_MASK 0xFFUL /**< Bit mask for MODEM_ADBBSSAMPJUMP */
+#define _MODEM_ADPC10_ADBBSSAMPJUMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC10 */
+#define MODEM_ADPC10_ADBBSSAMPJUMP_DEFAULT (_MODEM_ADPC10_ADBBSSAMPJUMP_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_ADPC10 */
+#define MODEM_ADPC10_ADBBSSCHANGEEN (0x1UL << 8) /**< ADBBSSCHANGEEN */
+#define _MODEM_ADPC10_ADBBSSCHANGEEN_SHIFT 8 /**< Shift value for MODEM_ADBBSSCHANGEEN */
+#define _MODEM_ADPC10_ADBBSSCHANGEEN_MASK 0x100UL /**< Bit mask for MODEM_ADBBSSCHANGEEN */
+#define _MODEM_ADPC10_ADBBSSCHANGEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC10 */
+#define _MODEM_ADPC10_ADBBSSCHANGEEN_DISABLE 0x00000000UL /**< Mode DISABLE for MODEM_ADPC10 */
+#define _MODEM_ADPC10_ADBBSSCHANGEEN_ENABLE 0x00000001UL /**< Mode ENABLE for MODEM_ADPC10 */
+#define MODEM_ADPC10_ADBBSSCHANGEEN_DEFAULT (_MODEM_ADPC10_ADBBSSCHANGEEN_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_ADPC10 */
+#define MODEM_ADPC10_ADBBSSCHANGEEN_DISABLE (_MODEM_ADPC10_ADBBSSCHANGEEN_DISABLE << 8) /**< Shifted mode DISABLE for MODEM_ADPC10 */
+#define MODEM_ADPC10_ADBBSSCHANGEEN_ENABLE (_MODEM_ADPC10_ADBBSSCHANGEEN_ENABLE << 8) /**< Shifted mode ENABLE for MODEM_ADPC10 */
+#define _MODEM_ADPC10_ADBBSSCHGUPTHR_SHIFT 9 /**< Shift value for MODEM_ADBBSSCHGUPTHR */
+#define _MODEM_ADPC10_ADBBSSCHGUPTHR_MASK 0x1E00UL /**< Bit mask for MODEM_ADBBSSCHGUPTHR */
+#define _MODEM_ADPC10_ADBBSSCHGUPTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC10 */
+#define MODEM_ADPC10_ADBBSSCHGUPTHR_DEFAULT (_MODEM_ADPC10_ADBBSSCHGUPTHR_DEFAULT << 9) /**< Shifted mode DEFAULT for MODEM_ADPC10 */
+#define _MODEM_ADPC10_ADBBSSCHGDNTHR_SHIFT 13 /**< Shift value for MODEM_ADBBSSCHGDNTHR */
+#define _MODEM_ADPC10_ADBBSSCHGDNTHR_MASK 0x1E000UL /**< Bit mask for MODEM_ADBBSSCHGDNTHR */
+#define _MODEM_ADPC10_ADBBSSCHGDNTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_ADPC10 */
+#define MODEM_ADPC10_ADBBSSCHGDNTHR_DEFAULT (_MODEM_ADPC10_ADBBSSCHGDNTHR_DEFAULT << 13) /**< Shifted mode DEFAULT for MODEM_ADPC10 */
+
+/* Bit fields for MODEM HADMCTRL0 */
+#define _MODEM_HADMCTRL0_RESETVALUE 0x00000000UL /**< Default value for MODEM_HADMCTRL0 */
+#define _MODEM_HADMCTRL0_MASK 0xFC00703FUL /**< Mask for MODEM_HADMCTRL0 */
+#define MODEM_HADMCTRL0_HADMEN (0x1UL << 0) /**< Enable HADM */
+#define _MODEM_HADMCTRL0_HADMEN_SHIFT 0 /**< Shift value for MODEM_HADMEN */
+#define _MODEM_HADMCTRL0_HADMEN_MASK 0x1UL /**< Bit mask for MODEM_HADMEN */
+#define _MODEM_HADMCTRL0_HADMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL0 */
+#define MODEM_HADMCTRL0_HADMEN_DEFAULT (_MODEM_HADMCTRL0_HADMEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_HADMCTRL0 */
+#define MODEM_HADMCTRL0_TESEN (0x1UL << 1) /**< Tone Exchange Step Enable */
+#define _MODEM_HADMCTRL0_TESEN_SHIFT 1 /**< Shift value for MODEM_TESEN */
+#define _MODEM_HADMCTRL0_TESEN_MASK 0x2UL /**< Bit mask for MODEM_TESEN */
+#define _MODEM_HADMCTRL0_TESEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL0 */
+#define MODEM_HADMCTRL0_TESEN_DEFAULT (_MODEM_HADMCTRL0_TESEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_HADMCTRL0 */
+#define MODEM_HADMCTRL0_PESEN (0x1UL << 2) /**< Packet Exchange Step Enable */
+#define _MODEM_HADMCTRL0_PESEN_SHIFT 2 /**< Shift value for MODEM_PESEN */
+#define _MODEM_HADMCTRL0_PESEN_MASK 0x4UL /**< Bit mask for MODEM_PESEN */
+#define _MODEM_HADMCTRL0_PESEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL0 */
+#define MODEM_HADMCTRL0_PESEN_DEFAULT (_MODEM_HADMCTRL0_PESEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MODEM_HADMCTRL0 */
+#define MODEM_HADMCTRL0_SNDSEQEN (0x1UL << 3) /**< Sounding Sequence Enable */
+#define _MODEM_HADMCTRL0_SNDSEQEN_SHIFT 3 /**< Shift value for MODEM_SNDSEQEN */
+#define _MODEM_HADMCTRL0_SNDSEQEN_MASK 0x8UL /**< Bit mask for MODEM_SNDSEQEN */
+#define _MODEM_HADMCTRL0_SNDSEQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL0 */
+#define MODEM_HADMCTRL0_SNDSEQEN_DEFAULT (_MODEM_HADMCTRL0_SNDSEQEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MODEM_HADMCTRL0 */
+#define MODEM_HADMCTRL0_ROLE (0x1UL << 4) /**< HADM Role */
+#define _MODEM_HADMCTRL0_ROLE_SHIFT 4 /**< Shift value for MODEM_ROLE */
+#define _MODEM_HADMCTRL0_ROLE_MASK 0x10UL /**< Bit mask for MODEM_ROLE */
+#define _MODEM_HADMCTRL0_ROLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL0 */
+#define _MODEM_HADMCTRL0_ROLE_INITIATOR 0x00000000UL /**< Mode INITIATOR for MODEM_HADMCTRL0 */
+#define _MODEM_HADMCTRL0_ROLE_REFLECTOR 0x00000001UL /**< Mode REFLECTOR for MODEM_HADMCTRL0 */
+#define MODEM_HADMCTRL0_ROLE_DEFAULT (_MODEM_HADMCTRL0_ROLE_DEFAULT << 4) /**< Shifted mode DEFAULT for MODEM_HADMCTRL0 */
+#define MODEM_HADMCTRL0_ROLE_INITIATOR (_MODEM_HADMCTRL0_ROLE_INITIATOR << 4) /**< Shifted mode INITIATOR for MODEM_HADMCTRL0 */
+#define MODEM_HADMCTRL0_ROLE_REFLECTOR (_MODEM_HADMCTRL0_ROLE_REFLECTOR << 4) /**< Shifted mode REFLECTOR for MODEM_HADMCTRL0 */
+#define MODEM_HADMCTRL0_RTTPHY (0x1UL << 5) /**< PHY Used for RTT Packets */
+#define _MODEM_HADMCTRL0_RTTPHY_SHIFT 5 /**< Shift value for MODEM_RTTPHY */
+#define _MODEM_HADMCTRL0_RTTPHY_MASK 0x20UL /**< Bit mask for MODEM_RTTPHY */
+#define _MODEM_HADMCTRL0_RTTPHY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL0 */
+#define MODEM_HADMCTRL0_RTTPHY_DEFAULT (_MODEM_HADMCTRL0_RTTPHY_DEFAULT << 5) /**< Shifted mode DEFAULT for MODEM_HADMCTRL0 */
+#define _MODEM_HADMCTRL0_PM_SHIFT 12 /**< Shift value for MODEM_PM */
+#define _MODEM_HADMCTRL0_PM_MASK 0x3000UL /**< Bit mask for MODEM_PM */
+#define _MODEM_HADMCTRL0_PM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL0 */
+#define MODEM_HADMCTRL0_PM_DEFAULT (_MODEM_HADMCTRL0_PM_DEFAULT << 12) /**< Shifted mode DEFAULT for MODEM_HADMCTRL0 */
+#define MODEM_HADMCTRL0_AVGMODE (0x1UL << 14) /**< Averaging Mode */
+#define _MODEM_HADMCTRL0_AVGMODE_SHIFT 14 /**< Shift value for MODEM_AVGMODE */
+#define _MODEM_HADMCTRL0_AVGMODE_MASK 0x4000UL /**< Bit mask for MODEM_AVGMODE */
+#define _MODEM_HADMCTRL0_AVGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL0 */
+#define _MODEM_HADMCTRL0_AVGMODE_PHASEAMP 0x00000000UL /**< Mode PHASEAMP for MODEM_HADMCTRL0 */
+#define _MODEM_HADMCTRL0_AVGMODE_IQ 0x00000001UL /**< Mode IQ for MODEM_HADMCTRL0 */
+#define MODEM_HADMCTRL0_AVGMODE_DEFAULT (_MODEM_HADMCTRL0_AVGMODE_DEFAULT << 14) /**< Shifted mode DEFAULT for MODEM_HADMCTRL0 */
+#define MODEM_HADMCTRL0_AVGMODE_PHASEAMP (_MODEM_HADMCTRL0_AVGMODE_PHASEAMP << 14) /**< Shifted mode PHASEAMP for MODEM_HADMCTRL0 */
+#define MODEM_HADMCTRL0_AVGMODE_IQ (_MODEM_HADMCTRL0_AVGMODE_IQ << 14) /**< Shifted mode IQ for MODEM_HADMCTRL0 */
+#define _MODEM_HADMCTRL0_DFTSCALE_SHIFT 26 /**< Shift value for MODEM_DFTSCALE */
+#define _MODEM_HADMCTRL0_DFTSCALE_MASK 0xC000000UL /**< Bit mask for MODEM_DFTSCALE */
+#define _MODEM_HADMCTRL0_DFTSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL0 */
+#define MODEM_HADMCTRL0_DFTSCALE_DEFAULT (_MODEM_HADMCTRL0_DFTSCALE_DEFAULT << 26) /**< Shifted mode DEFAULT for MODEM_HADMCTRL0 */
+#define MODEM_HADMCTRL0_PKTSENTSEL (0x1UL << 28) /**< RTT Packet Sent Selection */
+#define _MODEM_HADMCTRL0_PKTSENTSEL_SHIFT 28 /**< Shift value for MODEM_PKTSENTSEL */
+#define _MODEM_HADMCTRL0_PKTSENTSEL_MASK 0x10000000UL /**< Bit mask for MODEM_PKTSENTSEL */
+#define _MODEM_HADMCTRL0_PKTSENTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL0 */
+#define _MODEM_HADMCTRL0_PKTSENTSEL_BAUD_PRESENT 0x00000000UL /**< Mode BAUD_PRESENT for MODEM_HADMCTRL0 */
+#define _MODEM_HADMCTRL0_PKTSENTSEL_MOD_PRESENT 0x00000001UL /**< Mode MOD_PRESENT for MODEM_HADMCTRL0 */
+#define MODEM_HADMCTRL0_PKTSENTSEL_DEFAULT (_MODEM_HADMCTRL0_PKTSENTSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for MODEM_HADMCTRL0 */
+#define MODEM_HADMCTRL0_PKTSENTSEL_BAUD_PRESENT (_MODEM_HADMCTRL0_PKTSENTSEL_BAUD_PRESENT << 28) /**< Shifted mode BAUD_PRESENT for MODEM_HADMCTRL0*/
+#define MODEM_HADMCTRL0_PKTSENTSEL_MOD_PRESENT (_MODEM_HADMCTRL0_PKTSENTSEL_MOD_PRESENT << 28) /**< Shifted mode MOD_PRESENT for MODEM_HADMCTRL0*/
+#define MODEM_HADMCTRL0_TXUPSAMPOSR4 (0x1UL << 29) /**< TX symbol UP Sampling by 4 */
+#define _MODEM_HADMCTRL0_TXUPSAMPOSR4_SHIFT 29 /**< Shift value for MODEM_TXUPSAMPOSR4 */
+#define _MODEM_HADMCTRL0_TXUPSAMPOSR4_MASK 0x20000000UL /**< Bit mask for MODEM_TXUPSAMPOSR4 */
+#define _MODEM_HADMCTRL0_TXUPSAMPOSR4_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL0 */
+#define MODEM_HADMCTRL0_TXUPSAMPOSR4_DEFAULT (_MODEM_HADMCTRL0_TXUPSAMPOSR4_DEFAULT << 29) /**< Shifted mode DEFAULT for MODEM_HADMCTRL0 */
+#define MODEM_HADMCTRL0_SSAFCGEAR (0x1UL << 30) /**< SS AFC Gear SW */
+#define _MODEM_HADMCTRL0_SSAFCGEAR_SHIFT 30 /**< Shift value for MODEM_SSAFCGEAR */
+#define _MODEM_HADMCTRL0_SSAFCGEAR_MASK 0x40000000UL /**< Bit mask for MODEM_SSAFCGEAR */
+#define _MODEM_HADMCTRL0_SSAFCGEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL0 */
+#define MODEM_HADMCTRL0_SSAFCGEAR_DEFAULT (_MODEM_HADMCTRL0_SSAFCGEAR_DEFAULT << 30) /**< Shifted mode DEFAULT for MODEM_HADMCTRL0 */
+#define MODEM_HADMCTRL0_SRC2AUTOSCALE (0x1UL << 31) /**< SRC2 Autoscaling Debug Output */
+#define _MODEM_HADMCTRL0_SRC2AUTOSCALE_SHIFT 31 /**< Shift value for MODEM_SRC2AUTOSCALE */
+#define _MODEM_HADMCTRL0_SRC2AUTOSCALE_MASK 0x80000000UL /**< Bit mask for MODEM_SRC2AUTOSCALE */
+#define _MODEM_HADMCTRL0_SRC2AUTOSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL0 */
+#define MODEM_HADMCTRL0_SRC2AUTOSCALE_DEFAULT (_MODEM_HADMCTRL0_SRC2AUTOSCALE_DEFAULT << 31) /**< Shifted mode DEFAULT for MODEM_HADMCTRL0 */
+
+/* Bit fields for MODEM HADMCTRL1 */
+#define _MODEM_HADMCTRL1_RESETVALUE 0x00040000UL /**< Default value for MODEM_HADMCTRL1 */
+#define _MODEM_HADMCTRL1_MASK 0xFFC7FF07UL /**< Mask for MODEM_HADMCTRL1 */
+#define _MODEM_HADMCTRL1_STEPSTATE_SHIFT 0 /**< Shift value for MODEM_STEPSTATE */
+#define _MODEM_HADMCTRL1_STEPSTATE_MASK 0x7UL /**< Bit mask for MODEM_STEPSTATE */
+#define _MODEM_HADMCTRL1_STEPSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL1 */
+#define _MODEM_HADMCTRL1_STEPSTATE_IDLE 0x00000000UL /**< Mode IDLE for MODEM_HADMCTRL1 */
+#define _MODEM_HADMCTRL1_STEPSTATE_I_FREQ_COMP 0x00000001UL /**< Mode I_FREQ_COMP for MODEM_HADMCTRL1 */
+#define _MODEM_HADMCTRL1_STEPSTATE_R_FREQ_COMP_FREQ_MEAS 0x00000002UL /**< Mode R_FREQ_COMP_FREQ_MEAS for MODEM_HADMCTRL1*/
+#define _MODEM_HADMCTRL1_STEPSTATE_I_PES 0x00000003UL /**< Mode I_PES for MODEM_HADMCTRL1 */
+#define _MODEM_HADMCTRL1_STEPSTATE_R_PES 0x00000004UL /**< Mode R_PES for MODEM_HADMCTRL1 */
+#define _MODEM_HADMCTRL1_STEPSTATE_R_PES_TES 0x00000005UL /**< Mode R_PES_TES for MODEM_HADMCTRL1 */
+#define _MODEM_HADMCTRL1_STEPSTATE_R_TES 0x00000006UL /**< Mode R_TES for MODEM_HADMCTRL1 */
+#define _MODEM_HADMCTRL1_STEPSTATE_I_TES 0x00000007UL /**< Mode I_TES for MODEM_HADMCTRL1 */
+#define MODEM_HADMCTRL1_STEPSTATE_DEFAULT (_MODEM_HADMCTRL1_STEPSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_HADMCTRL1 */
+#define MODEM_HADMCTRL1_STEPSTATE_IDLE (_MODEM_HADMCTRL1_STEPSTATE_IDLE << 0) /**< Shifted mode IDLE for MODEM_HADMCTRL1 */
+#define MODEM_HADMCTRL1_STEPSTATE_I_FREQ_COMP (_MODEM_HADMCTRL1_STEPSTATE_I_FREQ_COMP << 0) /**< Shifted mode I_FREQ_COMP for MODEM_HADMCTRL1*/
+#define MODEM_HADMCTRL1_STEPSTATE_R_FREQ_COMP_FREQ_MEAS (_MODEM_HADMCTRL1_STEPSTATE_R_FREQ_COMP_FREQ_MEAS << 0) /**< Shifted mode R_FREQ_COMP_FREQ_MEAS for MODEM_HADMCTRL1*/
+#define MODEM_HADMCTRL1_STEPSTATE_I_PES (_MODEM_HADMCTRL1_STEPSTATE_I_PES << 0) /**< Shifted mode I_PES for MODEM_HADMCTRL1 */
+#define MODEM_HADMCTRL1_STEPSTATE_R_PES (_MODEM_HADMCTRL1_STEPSTATE_R_PES << 0) /**< Shifted mode R_PES for MODEM_HADMCTRL1 */
+#define MODEM_HADMCTRL1_STEPSTATE_R_PES_TES (_MODEM_HADMCTRL1_STEPSTATE_R_PES_TES << 0) /**< Shifted mode R_PES_TES for MODEM_HADMCTRL1 */
+#define MODEM_HADMCTRL1_STEPSTATE_R_TES (_MODEM_HADMCTRL1_STEPSTATE_R_TES << 0) /**< Shifted mode R_TES for MODEM_HADMCTRL1 */
+#define MODEM_HADMCTRL1_STEPSTATE_I_TES (_MODEM_HADMCTRL1_STEPSTATE_I_TES << 0) /**< Shifted mode I_TES for MODEM_HADMCTRL1 */
+#define _MODEM_HADMCTRL1_DFTSTARTOFF_SHIFT 8 /**< Shift value for MODEM_DFTSTARTOFF */
+#define _MODEM_HADMCTRL1_DFTSTARTOFF_MASK 0x7F00UL /**< Bit mask for MODEM_DFTSTARTOFF */
+#define _MODEM_HADMCTRL1_DFTSTARTOFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL1 */
+#define MODEM_HADMCTRL1_DFTSTARTOFF_DEFAULT (_MODEM_HADMCTRL1_DFTSTARTOFF_DEFAULT << 8) /**< Shifted mode DEFAULT for MODEM_HADMCTRL1 */
+#define _MODEM_HADMCTRL1_MAXSCHWIN_SHIFT 15 /**< Shift value for MODEM_MAXSCHWIN */
+#define _MODEM_HADMCTRL1_MAXSCHWIN_MASK 0x78000UL /**< Bit mask for MODEM_MAXSCHWIN */
+#define _MODEM_HADMCTRL1_MAXSCHWIN_DEFAULT 0x00000008UL /**< Mode DEFAULT for MODEM_HADMCTRL1 */
+#define MODEM_HADMCTRL1_MAXSCHWIN_DEFAULT (_MODEM_HADMCTRL1_MAXSCHWIN_DEFAULT << 15) /**< Shifted mode DEFAULT for MODEM_HADMCTRL1 */
+#define _MODEM_HADMCTRL1_AVGSTARTOFF_SHIFT 22 /**< Shift value for MODEM_AVGSTARTOFF */
+#define _MODEM_HADMCTRL1_AVGSTARTOFF_MASK 0xFFC00000UL /**< Bit mask for MODEM_AVGSTARTOFF */
+#define _MODEM_HADMCTRL1_AVGSTARTOFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMCTRL1 */
+#define MODEM_HADMCTRL1_AVGSTARTOFF_DEFAULT (_MODEM_HADMCTRL1_AVGSTARTOFF_DEFAULT << 22) /**< Shifted mode DEFAULT for MODEM_HADMCTRL1 */
+
+/* Bit fields for MODEM HADMSTATUS0 */
+#define _MODEM_HADMSTATUS0_RESETVALUE 0x00000000UL /**< Default value for MODEM_HADMSTATUS0 */
+#define _MODEM_HADMSTATUS0_MASK 0xFFFFFFFFUL /**< Mask for MODEM_HADMSTATUS0 */
+#define _MODEM_HADMSTATUS0_AVG0_SHIFT 0 /**< Shift value for MODEM_AVG0 */
+#define _MODEM_HADMSTATUS0_AVG0_MASK 0xFFFFUL /**< Bit mask for MODEM_AVG0 */
+#define _MODEM_HADMSTATUS0_AVG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS0 */
+#define MODEM_HADMSTATUS0_AVG0_DEFAULT (_MODEM_HADMSTATUS0_AVG0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS0 */
+#define _MODEM_HADMSTATUS0_AVG1_SHIFT 16 /**< Shift value for MODEM_AVG1 */
+#define _MODEM_HADMSTATUS0_AVG1_MASK 0xFFFF0000UL /**< Bit mask for MODEM_AVG1 */
+#define _MODEM_HADMSTATUS0_AVG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS0 */
+#define MODEM_HADMSTATUS0_AVG1_DEFAULT (_MODEM_HADMSTATUS0_AVG1_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS0 */
+
+/* Bit fields for MODEM HADMSTATUS1 */
+#define _MODEM_HADMSTATUS1_RESETVALUE 0x00000000UL /**< Default value for MODEM_HADMSTATUS1 */
+#define _MODEM_HADMSTATUS1_MASK 0xFFFFFFFFUL /**< Mask for MODEM_HADMSTATUS1 */
+#define _MODEM_HADMSTATUS1_FREQOFFSET_SHIFT 0 /**< Shift value for MODEM_FREQOFFSET */
+#define _MODEM_HADMSTATUS1_FREQOFFSET_MASK 0xFFFFUL /**< Bit mask for MODEM_FREQOFFSET */
+#define _MODEM_HADMSTATUS1_FREQOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS1 */
+#define MODEM_HADMSTATUS1_FREQOFFSET_DEFAULT (_MODEM_HADMSTATUS1_FREQOFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS1 */
+#define _MODEM_HADMSTATUS1_TIMETOX_SHIFT 16 /**< Shift value for MODEM_TIMETOX */
+#define _MODEM_HADMSTATUS1_TIMETOX_MASK 0xFFFF0000UL /**< Bit mask for MODEM_TIMETOX */
+#define _MODEM_HADMSTATUS1_TIMETOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS1 */
+#define MODEM_HADMSTATUS1_TIMETOX_DEFAULT (_MODEM_HADMSTATUS1_TIMETOX_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS1 */
+
+/* Bit fields for MODEM HADMSTATUS2 */
+#define _MODEM_HADMSTATUS2_RESETVALUE 0x00000000UL /**< Default value for MODEM_HADMSTATUS2 */
+#define _MODEM_HADMSTATUS2_MASK 0x3FFFFFFFUL /**< Mask for MODEM_HADMSTATUS2 */
+#define _MODEM_HADMSTATUS2_COSTLATE1_SHIFT 0 /**< Shift value for MODEM_COSTLATE1 */
+#define _MODEM_HADMSTATUS2_COSTLATE1_MASK 0x3FFUL /**< Bit mask for MODEM_COSTLATE1 */
+#define _MODEM_HADMSTATUS2_COSTLATE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS2 */
+#define MODEM_HADMSTATUS2_COSTLATE1_DEFAULT (_MODEM_HADMSTATUS2_COSTLATE1_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS2 */
+#define _MODEM_HADMSTATUS2_COSTCURR1_SHIFT 10 /**< Shift value for MODEM_COSTCURR1 */
+#define _MODEM_HADMSTATUS2_COSTCURR1_MASK 0xFFC00UL /**< Bit mask for MODEM_COSTCURR1 */
+#define _MODEM_HADMSTATUS2_COSTCURR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS2 */
+#define MODEM_HADMSTATUS2_COSTCURR1_DEFAULT (_MODEM_HADMSTATUS2_COSTCURR1_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS2 */
+#define _MODEM_HADMSTATUS2_COSTEARL1_SHIFT 20 /**< Shift value for MODEM_COSTEARL1 */
+#define _MODEM_HADMSTATUS2_COSTEARL1_MASK 0x3FF00000UL /**< Bit mask for MODEM_COSTEARL1 */
+#define _MODEM_HADMSTATUS2_COSTEARL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS2 */
+#define MODEM_HADMSTATUS2_COSTEARL1_DEFAULT (_MODEM_HADMSTATUS2_COSTEARL1_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS2 */
+
+/* Bit fields for MODEM HADMSTATUS3 */
+#define _MODEM_HADMSTATUS3_RESETVALUE 0x00000000UL /**< Default value for MODEM_HADMSTATUS3 */
+#define _MODEM_HADMSTATUS3_MASK 0x3FFFFFFFUL /**< Mask for MODEM_HADMSTATUS3 */
+#define _MODEM_HADMSTATUS3_COSTLATE0_SHIFT 0 /**< Shift value for MODEM_COSTLATE0 */
+#define _MODEM_HADMSTATUS3_COSTLATE0_MASK 0x3FFUL /**< Bit mask for MODEM_COSTLATE0 */
+#define _MODEM_HADMSTATUS3_COSTLATE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS3 */
+#define MODEM_HADMSTATUS3_COSTLATE0_DEFAULT (_MODEM_HADMSTATUS3_COSTLATE0_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS3 */
+#define _MODEM_HADMSTATUS3_COSTCURR0_SHIFT 10 /**< Shift value for MODEM_COSTCURR0 */
+#define _MODEM_HADMSTATUS3_COSTCURR0_MASK 0xFFC00UL /**< Bit mask for MODEM_COSTCURR0 */
+#define _MODEM_HADMSTATUS3_COSTCURR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS3 */
+#define MODEM_HADMSTATUS3_COSTCURR0_DEFAULT (_MODEM_HADMSTATUS3_COSTCURR0_DEFAULT << 10) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS3 */
+#define _MODEM_HADMSTATUS3_COSTEARL0_SHIFT 20 /**< Shift value for MODEM_COSTEARL0 */
+#define _MODEM_HADMSTATUS3_COSTEARL0_MASK 0x3FF00000UL /**< Bit mask for MODEM_COSTEARL0 */
+#define _MODEM_HADMSTATUS3_COSTEARL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS3 */
+#define MODEM_HADMSTATUS3_COSTEARL0_DEFAULT (_MODEM_HADMSTATUS3_COSTEARL0_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS3 */
+
+/* Bit fields for MODEM HADMSTATUS4 */
+#define _MODEM_HADMSTATUS4_RESETVALUE 0x00000000UL /**< Default value for MODEM_HADMSTATUS4 */
+#define _MODEM_HADMSTATUS4_MASK 0x7FFF7FFFUL /**< Mask for MODEM_HADMSTATUS4 */
+#define _MODEM_HADMSTATUS4_SBSP500I_SHIFT 0 /**< Shift value for MODEM_SBSP500I */
+#define _MODEM_HADMSTATUS4_SBSP500I_MASK 0x7FFFUL /**< Bit mask for MODEM_SBSP500I */
+#define _MODEM_HADMSTATUS4_SBSP500I_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS4 */
+#define MODEM_HADMSTATUS4_SBSP500I_DEFAULT (_MODEM_HADMSTATUS4_SBSP500I_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS4 */
+#define _MODEM_HADMSTATUS4_SBSP500Q_SHIFT 16 /**< Shift value for MODEM_SBSP500Q */
+#define _MODEM_HADMSTATUS4_SBSP500Q_MASK 0x7FFF0000UL /**< Bit mask for MODEM_SBSP500Q */
+#define _MODEM_HADMSTATUS4_SBSP500Q_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS4 */
+#define MODEM_HADMSTATUS4_SBSP500Q_DEFAULT (_MODEM_HADMSTATUS4_SBSP500Q_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS4 */
+
+/* Bit fields for MODEM HADMSTATUS5 */
+#define _MODEM_HADMSTATUS5_RESETVALUE 0x00000000UL /**< Default value for MODEM_HADMSTATUS5 */
+#define _MODEM_HADMSTATUS5_MASK 0x7FFF7FFFUL /**< Mask for MODEM_HADMSTATUS5 */
+#define _MODEM_HADMSTATUS5_SBSM500I_SHIFT 0 /**< Shift value for MODEM_SBSM500I */
+#define _MODEM_HADMSTATUS5_SBSM500I_MASK 0x7FFFUL /**< Bit mask for MODEM_SBSM500I */
+#define _MODEM_HADMSTATUS5_SBSM500I_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS5 */
+#define MODEM_HADMSTATUS5_SBSM500I_DEFAULT (_MODEM_HADMSTATUS5_SBSM500I_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS5 */
+#define _MODEM_HADMSTATUS5_SBSM500Q_SHIFT 16 /**< Shift value for MODEM_SBSM500Q */
+#define _MODEM_HADMSTATUS5_SBSM500Q_MASK 0x7FFF0000UL /**< Bit mask for MODEM_SBSM500Q */
+#define _MODEM_HADMSTATUS5_SBSM500Q_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS5 */
+#define MODEM_HADMSTATUS5_SBSM500Q_DEFAULT (_MODEM_HADMSTATUS5_SBSM500Q_DEFAULT << 16) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS5 */
+
+/* Bit fields for MODEM HADMSTATUS6 */
+#define _MODEM_HADMSTATUS6_RESETVALUE 0x00000000UL /**< Default value for MODEM_HADMSTATUS6 */
+#define _MODEM_HADMSTATUS6_MASK 0xFFF0FFFFUL /**< Mask for MODEM_HADMSTATUS6 */
+#define _MODEM_HADMSTATUS6_FREQMEAS_SHIFT 0 /**< Shift value for MODEM_FREQMEAS */
+#define _MODEM_HADMSTATUS6_FREQMEAS_MASK 0xFFFFUL /**< Bit mask for MODEM_FREQMEAS */
+#define _MODEM_HADMSTATUS6_FREQMEAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS6 */
+#define MODEM_HADMSTATUS6_FREQMEAS_DEFAULT (_MODEM_HADMSTATUS6_FREQMEAS_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS6 */
+#define _MODEM_HADMSTATUS6_SBSPSCALE_SHIFT 20 /**< Shift value for MODEM_SBSPSCALE */
+#define _MODEM_HADMSTATUS6_SBSPSCALE_MASK 0x3F00000UL /**< Bit mask for MODEM_SBSPSCALE */
+#define _MODEM_HADMSTATUS6_SBSPSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS6 */
+#define MODEM_HADMSTATUS6_SBSPSCALE_DEFAULT (_MODEM_HADMSTATUS6_SBSPSCALE_DEFAULT << 20) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS6 */
+#define _MODEM_HADMSTATUS6_SBSMSCALE_SHIFT 26 /**< Shift value for MODEM_SBSMSCALE */
+#define _MODEM_HADMSTATUS6_SBSMSCALE_MASK 0xFC000000UL /**< Bit mask for MODEM_SBSMSCALE */
+#define _MODEM_HADMSTATUS6_SBSMSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_HADMSTATUS6 */
+#define MODEM_HADMSTATUS6_SBSMSCALE_DEFAULT (_MODEM_HADMSTATUS6_SBSMSCALE_DEFAULT << 26) /**< Shifted mode DEFAULT for MODEM_HADMSTATUS6 */
+
+/* Bit fields for MODEM SRC2NCOCTRL */
+#define _MODEM_SRC2NCOCTRL_RESETVALUE 0x00000000UL /**< Default value for MODEM_SRC2NCOCTRL */
+#define _MODEM_SRC2NCOCTRL_MASK 0x00007FFFUL /**< Mask for MODEM_SRC2NCOCTRL */
+#define MODEM_SRC2NCOCTRL_SRC2NCOEN (0x1UL << 0) /**< Enable SRC2 NCO supplemental clock */
+#define _MODEM_SRC2NCOCTRL_SRC2NCOEN_SHIFT 0 /**< Shift value for MODEM_SRC2NCOEN */
+#define _MODEM_SRC2NCOCTRL_SRC2NCOEN_MASK 0x1UL /**< Bit mask for MODEM_SRC2NCOEN */
+#define _MODEM_SRC2NCOCTRL_SRC2NCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SRC2NCOCTRL */
+#define MODEM_SRC2NCOCTRL_SRC2NCOEN_DEFAULT (_MODEM_SRC2NCOCTRL_SRC2NCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SRC2NCOCTRL */
+#define _MODEM_SRC2NCOCTRL_PHASEPERCLK_SHIFT 1 /**< Shift value for MODEM_PHASEPERCLK */
+#define _MODEM_SRC2NCOCTRL_PHASEPERCLK_MASK 0x7FFEUL /**< Bit mask for MODEM_PHASEPERCLK */
+#define _MODEM_SRC2NCOCTRL_PHASEPERCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SRC2NCOCTRL */
+#define MODEM_SRC2NCOCTRL_PHASEPERCLK_DEFAULT (_MODEM_SRC2NCOCTRL_PHASEPERCLK_DEFAULT << 1) /**< Shifted mode DEFAULT for MODEM_SRC2NCOCTRL */
+
+/* Bit fields for MODEM SPARE */
+#define _MODEM_SPARE_RESETVALUE 0x00000000UL /**< Default value for MODEM_SPARE */
+#define _MODEM_SPARE_MASK 0x000000FFUL /**< Mask for MODEM_SPARE */
+#define _MODEM_SPARE_SPARE_SHIFT 0 /**< Shift value for MODEM_SPARE */
+#define _MODEM_SPARE_SPARE_MASK 0xFFUL /**< Bit mask for MODEM_SPARE */
+#define _MODEM_SPARE_SPARE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MODEM_SPARE */
+#define MODEM_SPARE_SPARE_DEFAULT (_MODEM_SPARE_SPARE_DEFAULT << 0) /**< Shifted mode DEFAULT for MODEM_SPARE */
+
+/** @} End of group EFR32MG24_MODEM_BitFields */
+/** @} End of group EFR32MG24_MODEM */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_MODEM_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_mpahbram.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_mpahbram.h
new file mode 100644
index 00000000..ae62eb6e
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_mpahbram.h
@@ -0,0 +1,443 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 MPAHBRAM register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_MPAHBRAM_H
+#define EFR32MG24_MPAHBRAM_H
+#define MPAHBRAM_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_MPAHBRAM MPAHBRAM
+ * @{
+ * @brief EFR32MG24 MPAHBRAM Register Declaration.
+ *****************************************************************************/
+
+/** MPAHBRAM Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IP version ID */
+ __IOM uint32_t CMD; /**< Command register */
+ __IOM uint32_t CTRL; /**< Control register */
+ __IM uint32_t ECCERRADDR0; /**< ECC Error Address 0 */
+ __IM uint32_t ECCERRADDR1; /**< ECC Error Address 1 */
+ __IM uint32_t ECCERRADDR2; /**< ECC Error Address 2 */
+ __IM uint32_t ECCERRADDR3; /**< ECC Error Address 3 */
+ __IM uint32_t ECCMERRIND; /**< Multiple ECC error indication */
+ __IOM uint32_t IF; /**< Interrupt Flags */
+ __IOM uint32_t IEN; /**< Interrupt Enable */
+ __IOM uint32_t RAMBANKSVALID; /**< New Register */
+ __IOM uint32_t CFGSRTOP; /**< Sequential Region on Top */
+ __IOM uint32_t CFGSRMAP; /**< Sequential Region Map */
+ __IOM uint32_t CFGIU0MAP; /**< Interleaving Unit 0 Map */
+ __IOM uint32_t CFGIU1MAP; /**< Interleaving Unit 1 Map */
+ __IOM uint32_t CFGIU2MAP; /**< Interleaving Unit 2 Map */
+ __IOM uint32_t CFGIU3MAP; /**< Interleaving Unit 3 Map */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+ uint32_t RESERVED1[1006U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP version ID */
+ __IOM uint32_t CMD_SET; /**< Command register */
+ __IOM uint32_t CTRL_SET; /**< Control register */
+ __IM uint32_t ECCERRADDR0_SET; /**< ECC Error Address 0 */
+ __IM uint32_t ECCERRADDR1_SET; /**< ECC Error Address 1 */
+ __IM uint32_t ECCERRADDR2_SET; /**< ECC Error Address 2 */
+ __IM uint32_t ECCERRADDR3_SET; /**< ECC Error Address 3 */
+ __IM uint32_t ECCMERRIND_SET; /**< Multiple ECC error indication */
+ __IOM uint32_t IF_SET; /**< Interrupt Flags */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable */
+ __IOM uint32_t RAMBANKSVALID_SET; /**< New Register */
+ __IOM uint32_t CFGSRTOP_SET; /**< Sequential Region on Top */
+ __IOM uint32_t CFGSRMAP_SET; /**< Sequential Region Map */
+ __IOM uint32_t CFGIU0MAP_SET; /**< Interleaving Unit 0 Map */
+ __IOM uint32_t CFGIU1MAP_SET; /**< Interleaving Unit 1 Map */
+ __IOM uint32_t CFGIU2MAP_SET; /**< Interleaving Unit 2 Map */
+ __IOM uint32_t CFGIU3MAP_SET; /**< Interleaving Unit 3 Map */
+ uint32_t RESERVED2[1U]; /**< Reserved for future use */
+ uint32_t RESERVED3[1006U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP version ID */
+ __IOM uint32_t CMD_CLR; /**< Command register */
+ __IOM uint32_t CTRL_CLR; /**< Control register */
+ __IM uint32_t ECCERRADDR0_CLR; /**< ECC Error Address 0 */
+ __IM uint32_t ECCERRADDR1_CLR; /**< ECC Error Address 1 */
+ __IM uint32_t ECCERRADDR2_CLR; /**< ECC Error Address 2 */
+ __IM uint32_t ECCERRADDR3_CLR; /**< ECC Error Address 3 */
+ __IM uint32_t ECCMERRIND_CLR; /**< Multiple ECC error indication */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flags */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable */
+ __IOM uint32_t RAMBANKSVALID_CLR; /**< New Register */
+ __IOM uint32_t CFGSRTOP_CLR; /**< Sequential Region on Top */
+ __IOM uint32_t CFGSRMAP_CLR; /**< Sequential Region Map */
+ __IOM uint32_t CFGIU0MAP_CLR; /**< Interleaving Unit 0 Map */
+ __IOM uint32_t CFGIU1MAP_CLR; /**< Interleaving Unit 1 Map */
+ __IOM uint32_t CFGIU2MAP_CLR; /**< Interleaving Unit 2 Map */
+ __IOM uint32_t CFGIU3MAP_CLR; /**< Interleaving Unit 3 Map */
+ uint32_t RESERVED4[1U]; /**< Reserved for future use */
+ uint32_t RESERVED5[1006U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP version ID */
+ __IOM uint32_t CMD_TGL; /**< Command register */
+ __IOM uint32_t CTRL_TGL; /**< Control register */
+ __IM uint32_t ECCERRADDR0_TGL; /**< ECC Error Address 0 */
+ __IM uint32_t ECCERRADDR1_TGL; /**< ECC Error Address 1 */
+ __IM uint32_t ECCERRADDR2_TGL; /**< ECC Error Address 2 */
+ __IM uint32_t ECCERRADDR3_TGL; /**< ECC Error Address 3 */
+ __IM uint32_t ECCMERRIND_TGL; /**< Multiple ECC error indication */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flags */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable */
+ __IOM uint32_t RAMBANKSVALID_TGL; /**< New Register */
+ __IOM uint32_t CFGSRTOP_TGL; /**< Sequential Region on Top */
+ __IOM uint32_t CFGSRMAP_TGL; /**< Sequential Region Map */
+ __IOM uint32_t CFGIU0MAP_TGL; /**< Interleaving Unit 0 Map */
+ __IOM uint32_t CFGIU1MAP_TGL; /**< Interleaving Unit 1 Map */
+ __IOM uint32_t CFGIU2MAP_TGL; /**< Interleaving Unit 2 Map */
+ __IOM uint32_t CFGIU3MAP_TGL; /**< Interleaving Unit 3 Map */
+ uint32_t RESERVED6[1U]; /**< Reserved for future use */
+} MPAHBRAM_TypeDef;
+/** @} End of group EFR32MG24_MPAHBRAM */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_MPAHBRAM
+ * @{
+ * @defgroup EFR32MG24_MPAHBRAM_BitFields MPAHBRAM Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for MPAHBRAM IPVERSION */
+#define _MPAHBRAM_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for MPAHBRAM_IPVERSION */
+#define _MPAHBRAM_IPVERSION_MASK 0x00000003UL /**< Mask for MPAHBRAM_IPVERSION */
+#define _MPAHBRAM_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MPAHBRAM_IPVERSION */
+#define _MPAHBRAM_IPVERSION_IPVERSION_MASK 0x3UL /**< Bit mask for MPAHBRAM_IPVERSION */
+#define _MPAHBRAM_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for MPAHBRAM_IPVERSION */
+#define MPAHBRAM_IPVERSION_IPVERSION_DEFAULT (_MPAHBRAM_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IPVERSION */
+
+/* Bit fields for MPAHBRAM CMD */
+#define _MPAHBRAM_CMD_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_CMD */
+#define _MPAHBRAM_CMD_MASK 0x0000000FUL /**< Mask for MPAHBRAM_CMD */
+#define MPAHBRAM_CMD_CLEARECCADDR0 (0x1UL << 0) /**< Clear ECCERRADDR0 */
+#define _MPAHBRAM_CMD_CLEARECCADDR0_SHIFT 0 /**< Shift value for MPAHBRAM_CLEARECCADDR0 */
+#define _MPAHBRAM_CMD_CLEARECCADDR0_MASK 0x1UL /**< Bit mask for MPAHBRAM_CLEARECCADDR0 */
+#define _MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */
+#define MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */
+#define MPAHBRAM_CMD_CLEARECCADDR1 (0x1UL << 1) /**< Clear ECCERRADDR1 */
+#define _MPAHBRAM_CMD_CLEARECCADDR1_SHIFT 1 /**< Shift value for MPAHBRAM_CLEARECCADDR1 */
+#define _MPAHBRAM_CMD_CLEARECCADDR1_MASK 0x2UL /**< Bit mask for MPAHBRAM_CLEARECCADDR1 */
+#define _MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */
+#define MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */
+#define MPAHBRAM_CMD_CLEARECCADDR2 (0x1UL << 2) /**< Clear ECCERRADDR2 */
+#define _MPAHBRAM_CMD_CLEARECCADDR2_SHIFT 2 /**< Shift value for MPAHBRAM_CLEARECCADDR2 */
+#define _MPAHBRAM_CMD_CLEARECCADDR2_MASK 0x4UL /**< Bit mask for MPAHBRAM_CLEARECCADDR2 */
+#define _MPAHBRAM_CMD_CLEARECCADDR2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */
+#define MPAHBRAM_CMD_CLEARECCADDR2_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR2_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */
+#define MPAHBRAM_CMD_CLEARECCADDR3 (0x1UL << 3) /**< Clear ECCERRADDR3 */
+#define _MPAHBRAM_CMD_CLEARECCADDR3_SHIFT 3 /**< Shift value for MPAHBRAM_CLEARECCADDR3 */
+#define _MPAHBRAM_CMD_CLEARECCADDR3_MASK 0x8UL /**< Bit mask for MPAHBRAM_CLEARECCADDR3 */
+#define _MPAHBRAM_CMD_CLEARECCADDR3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */
+#define MPAHBRAM_CMD_CLEARECCADDR3_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR3_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */
+
+/* Bit fields for MPAHBRAM CTRL */
+#define _MPAHBRAM_CTRL_RESETVALUE 0x00000040UL /**< Default value for MPAHBRAM_CTRL */
+#define _MPAHBRAM_CTRL_MASK 0x000000FFUL /**< Mask for MPAHBRAM_CTRL */
+#define MPAHBRAM_CTRL_ECCEN (0x1UL << 0) /**< Enable ECC functionality */
+#define _MPAHBRAM_CTRL_ECCEN_SHIFT 0 /**< Shift value for MPAHBRAM_ECCEN */
+#define _MPAHBRAM_CTRL_ECCEN_MASK 0x1UL /**< Bit mask for MPAHBRAM_ECCEN */
+#define _MPAHBRAM_CTRL_ECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */
+#define MPAHBRAM_CTRL_ECCEN_DEFAULT (_MPAHBRAM_CTRL_ECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */
+#define MPAHBRAM_CTRL_ECCWEN (0x1UL << 1) /**< Enable ECC syndrome writes */
+#define _MPAHBRAM_CTRL_ECCWEN_SHIFT 1 /**< Shift value for MPAHBRAM_ECCWEN */
+#define _MPAHBRAM_CTRL_ECCWEN_MASK 0x2UL /**< Bit mask for MPAHBRAM_ECCWEN */
+#define _MPAHBRAM_CTRL_ECCWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */
+#define MPAHBRAM_CTRL_ECCWEN_DEFAULT (_MPAHBRAM_CTRL_ECCWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */
+#define MPAHBRAM_CTRL_ECCERRFAULTEN (0x1UL << 2) /**< ECC Error bus fault enable */
+#define _MPAHBRAM_CTRL_ECCERRFAULTEN_SHIFT 2 /**< Shift value for MPAHBRAM_ECCERRFAULTEN */
+#define _MPAHBRAM_CTRL_ECCERRFAULTEN_MASK 0x4UL /**< Bit mask for MPAHBRAM_ECCERRFAULTEN */
+#define _MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */
+#define MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT (_MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */
+#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT 3 /**< Shift value for MPAHBRAM_AHBPORTPRIORITY */
+#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK 0x38UL /**< Bit mask for MPAHBRAM_AHBPORTPRIORITY */
+#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */
+#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE 0x00000000UL /**< Mode NONE for MPAHBRAM_CTRL */
+#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 0x00000001UL /**< Mode PORT0 for MPAHBRAM_CTRL */
+#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 0x00000002UL /**< Mode PORT1 for MPAHBRAM_CTRL */
+#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT2 0x00000003UL /**< Mode PORT2 for MPAHBRAM_CTRL */
+#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT3 0x00000004UL /**< Mode PORT3 for MPAHBRAM_CTRL */
+#define MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT (_MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */
+#define MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE (_MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE << 3) /**< Shifted mode NONE for MPAHBRAM_CTRL */
+#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 << 3) /**< Shifted mode PORT0 for MPAHBRAM_CTRL */
+#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 << 3) /**< Shifted mode PORT1 for MPAHBRAM_CTRL */
+#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT2 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT2 << 3) /**< Shifted mode PORT2 for MPAHBRAM_CTRL */
+#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT3 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT3 << 3) /**< Shifted mode PORT3 for MPAHBRAM_CTRL */
+#define MPAHBRAM_CTRL_ADDRFAULTEN (0x1UL << 6) /**< Address fault bus fault enable */
+#define _MPAHBRAM_CTRL_ADDRFAULTEN_SHIFT 6 /**< Shift value for MPAHBRAM_ADDRFAULTEN */
+#define _MPAHBRAM_CTRL_ADDRFAULTEN_MASK 0x40UL /**< Bit mask for MPAHBRAM_ADDRFAULTEN */
+#define _MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MPAHBRAM_CTRL */
+#define MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT (_MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */
+#define MPAHBRAM_CTRL_WAITSTATES (0x1UL << 7) /**< RAM read wait states */
+#define _MPAHBRAM_CTRL_WAITSTATES_SHIFT 7 /**< Shift value for MPAHBRAM_WAITSTATES */
+#define _MPAHBRAM_CTRL_WAITSTATES_MASK 0x80UL /**< Bit mask for MPAHBRAM_WAITSTATES */
+#define _MPAHBRAM_CTRL_WAITSTATES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */
+#define MPAHBRAM_CTRL_WAITSTATES_DEFAULT (_MPAHBRAM_CTRL_WAITSTATES_DEFAULT << 7) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */
+
+/* Bit fields for MPAHBRAM ECCERRADDR0 */
+#define _MPAHBRAM_ECCERRADDR0_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR0 */
+#define _MPAHBRAM_ECCERRADDR0_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR0 */
+#define _MPAHBRAM_ECCERRADDR0_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */
+#define _MPAHBRAM_ECCERRADDR0_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */
+#define _MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR0 */
+#define MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR0*/
+
+/* Bit fields for MPAHBRAM ECCERRADDR1 */
+#define _MPAHBRAM_ECCERRADDR1_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR1 */
+#define _MPAHBRAM_ECCERRADDR1_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR1 */
+#define _MPAHBRAM_ECCERRADDR1_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */
+#define _MPAHBRAM_ECCERRADDR1_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */
+#define _MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR1 */
+#define MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR1*/
+
+/* Bit fields for MPAHBRAM ECCERRADDR2 */
+#define _MPAHBRAM_ECCERRADDR2_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR2 */
+#define _MPAHBRAM_ECCERRADDR2_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR2 */
+#define _MPAHBRAM_ECCERRADDR2_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */
+#define _MPAHBRAM_ECCERRADDR2_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */
+#define _MPAHBRAM_ECCERRADDR2_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR2 */
+#define MPAHBRAM_ECCERRADDR2_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR2_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR2*/
+
+/* Bit fields for MPAHBRAM ECCERRADDR3 */
+#define _MPAHBRAM_ECCERRADDR3_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR3 */
+#define _MPAHBRAM_ECCERRADDR3_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR3 */
+#define _MPAHBRAM_ECCERRADDR3_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */
+#define _MPAHBRAM_ECCERRADDR3_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */
+#define _MPAHBRAM_ECCERRADDR3_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR3 */
+#define MPAHBRAM_ECCERRADDR3_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR3_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR3*/
+
+/* Bit fields for MPAHBRAM ECCMERRIND */
+#define _MPAHBRAM_ECCMERRIND_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCMERRIND */
+#define _MPAHBRAM_ECCMERRIND_MASK 0x0000000FUL /**< Mask for MPAHBRAM_ECCMERRIND */
+#define MPAHBRAM_ECCMERRIND_P0 (0x1UL << 0) /**< Multiple ECC errors on AHB port 0 */
+#define _MPAHBRAM_ECCMERRIND_P0_SHIFT 0 /**< Shift value for MPAHBRAM_P0 */
+#define _MPAHBRAM_ECCMERRIND_P0_MASK 0x1UL /**< Bit mask for MPAHBRAM_P0 */
+#define _MPAHBRAM_ECCMERRIND_P0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */
+#define MPAHBRAM_ECCMERRIND_P0_DEFAULT (_MPAHBRAM_ECCMERRIND_P0_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/
+#define MPAHBRAM_ECCMERRIND_P1 (0x1UL << 1) /**< Multiple ECC errors on AHB port 1 */
+#define _MPAHBRAM_ECCMERRIND_P1_SHIFT 1 /**< Shift value for MPAHBRAM_P1 */
+#define _MPAHBRAM_ECCMERRIND_P1_MASK 0x2UL /**< Bit mask for MPAHBRAM_P1 */
+#define _MPAHBRAM_ECCMERRIND_P1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */
+#define MPAHBRAM_ECCMERRIND_P1_DEFAULT (_MPAHBRAM_ECCMERRIND_P1_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/
+#define MPAHBRAM_ECCMERRIND_P2 (0x1UL << 2) /**< Multiple ECC errors on AHB port 2 */
+#define _MPAHBRAM_ECCMERRIND_P2_SHIFT 2 /**< Shift value for MPAHBRAM_P2 */
+#define _MPAHBRAM_ECCMERRIND_P2_MASK 0x4UL /**< Bit mask for MPAHBRAM_P2 */
+#define _MPAHBRAM_ECCMERRIND_P2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */
+#define MPAHBRAM_ECCMERRIND_P2_DEFAULT (_MPAHBRAM_ECCMERRIND_P2_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/
+#define MPAHBRAM_ECCMERRIND_P3 (0x1UL << 3) /**< Multiple ECC errors on AHB port 2 */
+#define _MPAHBRAM_ECCMERRIND_P3_SHIFT 3 /**< Shift value for MPAHBRAM_P3 */
+#define _MPAHBRAM_ECCMERRIND_P3_MASK 0x8UL /**< Bit mask for MPAHBRAM_P3 */
+#define _MPAHBRAM_ECCMERRIND_P3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */
+#define MPAHBRAM_ECCMERRIND_P3_DEFAULT (_MPAHBRAM_ECCMERRIND_P3_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/
+
+/* Bit fields for MPAHBRAM IF */
+#define _MPAHBRAM_IF_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_IF */
+#define _MPAHBRAM_IF_MASK 0x000000FFUL /**< Mask for MPAHBRAM_IF */
+#define MPAHBRAM_IF_AHB0ERR1B (0x1UL << 0) /**< AHB0 1-bit ECC Error Interrupt Flag */
+#define _MPAHBRAM_IF_AHB0ERR1B_SHIFT 0 /**< Shift value for MPAHBRAM_AHB0ERR1B */
+#define _MPAHBRAM_IF_AHB0ERR1B_MASK 0x1UL /**< Bit mask for MPAHBRAM_AHB0ERR1B */
+#define _MPAHBRAM_IF_AHB0ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */
+#define MPAHBRAM_IF_AHB0ERR1B_DEFAULT (_MPAHBRAM_IF_AHB0ERR1B_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IF */
+#define MPAHBRAM_IF_AHB1ERR1B (0x1UL << 1) /**< AHB1 1-bit ECC Error Interrupt Flag */
+#define _MPAHBRAM_IF_AHB1ERR1B_SHIFT 1 /**< Shift value for MPAHBRAM_AHB1ERR1B */
+#define _MPAHBRAM_IF_AHB1ERR1B_MASK 0x2UL /**< Bit mask for MPAHBRAM_AHB1ERR1B */
+#define _MPAHBRAM_IF_AHB1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */
+#define MPAHBRAM_IF_AHB1ERR1B_DEFAULT (_MPAHBRAM_IF_AHB1ERR1B_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_IF */
+#define MPAHBRAM_IF_AHB2ERR1B (0x1UL << 2) /**< AHB2 1-bit ECC Error Interrupt Flag */
+#define _MPAHBRAM_IF_AHB2ERR1B_SHIFT 2 /**< Shift value for MPAHBRAM_AHB2ERR1B */
+#define _MPAHBRAM_IF_AHB2ERR1B_MASK 0x4UL /**< Bit mask for MPAHBRAM_AHB2ERR1B */
+#define _MPAHBRAM_IF_AHB2ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */
+#define MPAHBRAM_IF_AHB2ERR1B_DEFAULT (_MPAHBRAM_IF_AHB2ERR1B_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_IF */
+#define MPAHBRAM_IF_AHB3ERR1B (0x1UL << 3) /**< AHB3 1-bit ECC Error Interrupt Flag */
+#define _MPAHBRAM_IF_AHB3ERR1B_SHIFT 3 /**< Shift value for MPAHBRAM_AHB3ERR1B */
+#define _MPAHBRAM_IF_AHB3ERR1B_MASK 0x8UL /**< Bit mask for MPAHBRAM_AHB3ERR1B */
+#define _MPAHBRAM_IF_AHB3ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */
+#define MPAHBRAM_IF_AHB3ERR1B_DEFAULT (_MPAHBRAM_IF_AHB3ERR1B_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_IF */
+#define MPAHBRAM_IF_AHB0ERR2B (0x1UL << 4) /**< AHB0 2-bit ECC Error Interrupt Flag */
+#define _MPAHBRAM_IF_AHB0ERR2B_SHIFT 4 /**< Shift value for MPAHBRAM_AHB0ERR2B */
+#define _MPAHBRAM_IF_AHB0ERR2B_MASK 0x10UL /**< Bit mask for MPAHBRAM_AHB0ERR2B */
+#define _MPAHBRAM_IF_AHB0ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */
+#define MPAHBRAM_IF_AHB0ERR2B_DEFAULT (_MPAHBRAM_IF_AHB0ERR2B_DEFAULT << 4) /**< Shifted mode DEFAULT for MPAHBRAM_IF */
+#define MPAHBRAM_IF_AHB1ERR2B (0x1UL << 5) /**< AHB1 2-bit ECC Error Interrupt Flag */
+#define _MPAHBRAM_IF_AHB1ERR2B_SHIFT 5 /**< Shift value for MPAHBRAM_AHB1ERR2B */
+#define _MPAHBRAM_IF_AHB1ERR2B_MASK 0x20UL /**< Bit mask for MPAHBRAM_AHB1ERR2B */
+#define _MPAHBRAM_IF_AHB1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */
+#define MPAHBRAM_IF_AHB1ERR2B_DEFAULT (_MPAHBRAM_IF_AHB1ERR2B_DEFAULT << 5) /**< Shifted mode DEFAULT for MPAHBRAM_IF */
+#define MPAHBRAM_IF_AHB2ERR2B (0x1UL << 6) /**< AHB2 2-bit ECC Error Interrupt Flag */
+#define _MPAHBRAM_IF_AHB2ERR2B_SHIFT 6 /**< Shift value for MPAHBRAM_AHB2ERR2B */
+#define _MPAHBRAM_IF_AHB2ERR2B_MASK 0x40UL /**< Bit mask for MPAHBRAM_AHB2ERR2B */
+#define _MPAHBRAM_IF_AHB2ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */
+#define MPAHBRAM_IF_AHB2ERR2B_DEFAULT (_MPAHBRAM_IF_AHB2ERR2B_DEFAULT << 6) /**< Shifted mode DEFAULT for MPAHBRAM_IF */
+#define MPAHBRAM_IF_AHB3ERR2B (0x1UL << 7) /**< AHB3 2-bit ECC Error Interrupt Flag */
+#define _MPAHBRAM_IF_AHB3ERR2B_SHIFT 7 /**< Shift value for MPAHBRAM_AHB3ERR2B */
+#define _MPAHBRAM_IF_AHB3ERR2B_MASK 0x80UL /**< Bit mask for MPAHBRAM_AHB3ERR2B */
+#define _MPAHBRAM_IF_AHB3ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */
+#define MPAHBRAM_IF_AHB3ERR2B_DEFAULT (_MPAHBRAM_IF_AHB3ERR2B_DEFAULT << 7) /**< Shifted mode DEFAULT for MPAHBRAM_IF */
+
+/* Bit fields for MPAHBRAM IEN */
+#define _MPAHBRAM_IEN_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_IEN */
+#define _MPAHBRAM_IEN_MASK 0x000000FFUL /**< Mask for MPAHBRAM_IEN */
+#define MPAHBRAM_IEN_AHB0ERR1B (0x1UL << 0) /**< AHB0 1-bit ECC Error Interrupt Enable */
+#define _MPAHBRAM_IEN_AHB0ERR1B_SHIFT 0 /**< Shift value for MPAHBRAM_AHB0ERR1B */
+#define _MPAHBRAM_IEN_AHB0ERR1B_MASK 0x1UL /**< Bit mask for MPAHBRAM_AHB0ERR1B */
+#define _MPAHBRAM_IEN_AHB0ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */
+#define MPAHBRAM_IEN_AHB0ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB0ERR1B_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */
+#define MPAHBRAM_IEN_AHB1ERR1B (0x1UL << 1) /**< AHB1 1-bit ECC Error Interrupt Enable */
+#define _MPAHBRAM_IEN_AHB1ERR1B_SHIFT 1 /**< Shift value for MPAHBRAM_AHB1ERR1B */
+#define _MPAHBRAM_IEN_AHB1ERR1B_MASK 0x2UL /**< Bit mask for MPAHBRAM_AHB1ERR1B */
+#define _MPAHBRAM_IEN_AHB1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */
+#define MPAHBRAM_IEN_AHB1ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB1ERR1B_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */
+#define MPAHBRAM_IEN_AHB2ERR1B (0x1UL << 2) /**< AHB2 1-bit ECC Error Interrupt Enable */
+#define _MPAHBRAM_IEN_AHB2ERR1B_SHIFT 2 /**< Shift value for MPAHBRAM_AHB2ERR1B */
+#define _MPAHBRAM_IEN_AHB2ERR1B_MASK 0x4UL /**< Bit mask for MPAHBRAM_AHB2ERR1B */
+#define _MPAHBRAM_IEN_AHB2ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */
+#define MPAHBRAM_IEN_AHB2ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB2ERR1B_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */
+#define MPAHBRAM_IEN_AHB3ERR1B (0x1UL << 3) /**< AHB3 1-bit ECC Error Interrupt Enable */
+#define _MPAHBRAM_IEN_AHB3ERR1B_SHIFT 3 /**< Shift value for MPAHBRAM_AHB3ERR1B */
+#define _MPAHBRAM_IEN_AHB3ERR1B_MASK 0x8UL /**< Bit mask for MPAHBRAM_AHB3ERR1B */
+#define _MPAHBRAM_IEN_AHB3ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */
+#define MPAHBRAM_IEN_AHB3ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB3ERR1B_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */
+#define MPAHBRAM_IEN_AHB0ERR2B (0x1UL << 4) /**< AHB0 2-bit ECC Error Interrupt Enable */
+#define _MPAHBRAM_IEN_AHB0ERR2B_SHIFT 4 /**< Shift value for MPAHBRAM_AHB0ERR2B */
+#define _MPAHBRAM_IEN_AHB0ERR2B_MASK 0x10UL /**< Bit mask for MPAHBRAM_AHB0ERR2B */
+#define _MPAHBRAM_IEN_AHB0ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */
+#define MPAHBRAM_IEN_AHB0ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB0ERR2B_DEFAULT << 4) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */
+#define MPAHBRAM_IEN_AHB1ERR2B (0x1UL << 5) /**< AHB1 2-bit ECC Error Interrupt Enable */
+#define _MPAHBRAM_IEN_AHB1ERR2B_SHIFT 5 /**< Shift value for MPAHBRAM_AHB1ERR2B */
+#define _MPAHBRAM_IEN_AHB1ERR2B_MASK 0x20UL /**< Bit mask for MPAHBRAM_AHB1ERR2B */
+#define _MPAHBRAM_IEN_AHB1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */
+#define MPAHBRAM_IEN_AHB1ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB1ERR2B_DEFAULT << 5) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */
+#define MPAHBRAM_IEN_AHB2ERR2B (0x1UL << 6) /**< AHB2 2-bit ECC Error Interrupt Enable */
+#define _MPAHBRAM_IEN_AHB2ERR2B_SHIFT 6 /**< Shift value for MPAHBRAM_AHB2ERR2B */
+#define _MPAHBRAM_IEN_AHB2ERR2B_MASK 0x40UL /**< Bit mask for MPAHBRAM_AHB2ERR2B */
+#define _MPAHBRAM_IEN_AHB2ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */
+#define MPAHBRAM_IEN_AHB2ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB2ERR2B_DEFAULT << 6) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */
+#define MPAHBRAM_IEN_AHB3ERR2B (0x1UL << 7) /**< AHB3 2-bit ECC Error Interrupt Enable */
+#define _MPAHBRAM_IEN_AHB3ERR2B_SHIFT 7 /**< Shift value for MPAHBRAM_AHB3ERR2B */
+#define _MPAHBRAM_IEN_AHB3ERR2B_MASK 0x80UL /**< Bit mask for MPAHBRAM_AHB3ERR2B */
+#define _MPAHBRAM_IEN_AHB3ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */
+#define MPAHBRAM_IEN_AHB3ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB3ERR2B_DEFAULT << 7) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */
+
+/* Bit fields for MPAHBRAM RAMBANKSVALID */
+#define _MPAHBRAM_RAMBANKSVALID_RESETVALUE 0xFFFFFFFFUL /**< Default value for MPAHBRAM_RAMBANKSVALID */
+#define _MPAHBRAM_RAMBANKSVALID_MASK 0x0000FFFFUL /**< Mask for MPAHBRAM_RAMBANKSVALID */
+#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_SHIFT 0 /**< Shift value for MPAHBRAM_RAMBANKSVALID */
+#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_MASK 0xFFFFUL /**< Bit mask for MPAHBRAM_RAMBANKSVALID */
+#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_DEFAULT 0xFFFFFFFFUL /**< Mode DEFAULT for MPAHBRAM_RAMBANKSVALID */
+#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0 0x00000001UL /**< Mode BLK0 for MPAHBRAM_RAMBANKSVALID */
+#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO1 0x00000003UL /**< Mode BLK0TO1 for MPAHBRAM_RAMBANKSVALID */
+#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO2 0x00000007UL /**< Mode BLK0TO2 for MPAHBRAM_RAMBANKSVALID */
+#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for MPAHBRAM_RAMBANKSVALID */
+#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO4 0x0000001FUL /**< Mode BLK0TO4 for MPAHBRAM_RAMBANKSVALID */
+#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO5 0x0000003FUL /**< Mode BLK0TO5 for MPAHBRAM_RAMBANKSVALID */
+#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO6 0x0000007FUL /**< Mode BLK0TO6 for MPAHBRAM_RAMBANKSVALID */
+#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for MPAHBRAM_RAMBANKSVALID */
+#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO8 0x000001FFUL /**< Mode BLK0TO8 for MPAHBRAM_RAMBANKSVALID */
+#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO9 0x000003FFUL /**< Mode BLK0TO9 for MPAHBRAM_RAMBANKSVALID */
+#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO10 0x000007FFUL /**< Mode BLK0TO10 for MPAHBRAM_RAMBANKSVALID */
+#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO11 0x00000FFFUL /**< Mode BLK0TO11 for MPAHBRAM_RAMBANKSVALID */
+#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO12 0x00001FFFUL /**< Mode BLK0TO12 for MPAHBRAM_RAMBANKSVALID */
+#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO13 0x00003FFFUL /**< Mode BLK0TO13 for MPAHBRAM_RAMBANKSVALID */
+#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO14 0x00007FFFUL /**< Mode BLK0TO14 for MPAHBRAM_RAMBANKSVALID */
+#define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO15 0x0000FFFFUL /**< Mode BLK0TO15 for MPAHBRAM_RAMBANKSVALID */
+#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_DEFAULT (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_RAMBANKSVALID*/
+#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0 << 0) /**< Shifted mode BLK0 for MPAHBRAM_RAMBANKSVALID*/
+#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO1 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO1 << 0) /**< Shifted mode BLK0TO1 for MPAHBRAM_RAMBANKSVALID*/
+#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO2 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO2 << 0) /**< Shifted mode BLK0TO2 for MPAHBRAM_RAMBANKSVALID*/
+#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO3 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for MPAHBRAM_RAMBANKSVALID*/
+#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO4 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO4 << 0) /**< Shifted mode BLK0TO4 for MPAHBRAM_RAMBANKSVALID*/
+#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO5 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO5 << 0) /**< Shifted mode BLK0TO5 for MPAHBRAM_RAMBANKSVALID*/
+#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO6 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO6 << 0) /**< Shifted mode BLK0TO6 for MPAHBRAM_RAMBANKSVALID*/
+#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO7 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for MPAHBRAM_RAMBANKSVALID*/
+#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO8 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO8 << 0) /**< Shifted mode BLK0TO8 for MPAHBRAM_RAMBANKSVALID*/
+#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO9 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO9 << 0) /**< Shifted mode BLK0TO9 for MPAHBRAM_RAMBANKSVALID*/
+#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO10 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO10 << 0) /**< Shifted mode BLK0TO10 for MPAHBRAM_RAMBANKSVALID*/
+#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO11 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO11 << 0) /**< Shifted mode BLK0TO11 for MPAHBRAM_RAMBANKSVALID*/
+#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO12 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO12 << 0) /**< Shifted mode BLK0TO12 for MPAHBRAM_RAMBANKSVALID*/
+#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO13 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO13 << 0) /**< Shifted mode BLK0TO13 for MPAHBRAM_RAMBANKSVALID*/
+#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO14 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO14 << 0) /**< Shifted mode BLK0TO14 for MPAHBRAM_RAMBANKSVALID*/
+#define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO15 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO15 << 0) /**< Shifted mode BLK0TO15 for MPAHBRAM_RAMBANKSVALID*/
+
+/* Bit fields for MPAHBRAM CFGSRTOP */
+#define _MPAHBRAM_CFGSRTOP_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_CFGSRTOP */
+#define _MPAHBRAM_CFGSRTOP_MASK 0x00000001UL /**< Mask for MPAHBRAM_CFGSRTOP */
+#define MPAHBRAM_CFGSRTOP_SRTOP (0x1UL << 0) /**< Sequential region on top */
+#define _MPAHBRAM_CFGSRTOP_SRTOP_SHIFT 0 /**< Shift value for MPAHBRAM_SRTOP */
+#define _MPAHBRAM_CFGSRTOP_SRTOP_MASK 0x1UL /**< Bit mask for MPAHBRAM_SRTOP */
+#define _MPAHBRAM_CFGSRTOP_SRTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CFGSRTOP */
+#define MPAHBRAM_CFGSRTOP_SRTOP_DEFAULT (_MPAHBRAM_CFGSRTOP_SRTOP_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CFGSRTOP */
+
+/* Bit fields for MPAHBRAM CFGSRMAP */
+#define _MPAHBRAM_CFGSRMAP_RESETVALUE 0xFFFFFFFFUL /**< Default value for MPAHBRAM_CFGSRMAP */
+#define _MPAHBRAM_CFGSRMAP_MASK 0x0000FFFFUL /**< Mask for MPAHBRAM_CFGSRMAP */
+#define _MPAHBRAM_CFGSRMAP_MAP_SHIFT 0 /**< Shift value for MPAHBRAM_MAP */
+#define _MPAHBRAM_CFGSRMAP_MAP_MASK 0xFFFFUL /**< Bit mask for MPAHBRAM_MAP */
+#define _MPAHBRAM_CFGSRMAP_MAP_DEFAULT 0xFFFFFFFFUL /**< Mode DEFAULT for MPAHBRAM_CFGSRMAP */
+#define MPAHBRAM_CFGSRMAP_MAP_DEFAULT (_MPAHBRAM_CFGSRMAP_MAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CFGSRMAP */
+
+/* Bit fields for MPAHBRAM CFGIU0MAP */
+#define _MPAHBRAM_CFGIU0MAP_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_CFGIU0MAP */
+#define _MPAHBRAM_CFGIU0MAP_MASK 0x0000FFFFUL /**< Mask for MPAHBRAM_CFGIU0MAP */
+#define _MPAHBRAM_CFGIU0MAP_MAP_SHIFT 0 /**< Shift value for MPAHBRAM_MAP */
+#define _MPAHBRAM_CFGIU0MAP_MAP_MASK 0xFFFFUL /**< Bit mask for MPAHBRAM_MAP */
+#define _MPAHBRAM_CFGIU0MAP_MAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CFGIU0MAP */
+#define MPAHBRAM_CFGIU0MAP_MAP_DEFAULT (_MPAHBRAM_CFGIU0MAP_MAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CFGIU0MAP */
+
+/* Bit fields for MPAHBRAM CFGIU1MAP */
+#define _MPAHBRAM_CFGIU1MAP_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_CFGIU1MAP */
+#define _MPAHBRAM_CFGIU1MAP_MASK 0x0000FFFFUL /**< Mask for MPAHBRAM_CFGIU1MAP */
+#define _MPAHBRAM_CFGIU1MAP_MAP_SHIFT 0 /**< Shift value for MPAHBRAM_MAP */
+#define _MPAHBRAM_CFGIU1MAP_MAP_MASK 0xFFFFUL /**< Bit mask for MPAHBRAM_MAP */
+#define _MPAHBRAM_CFGIU1MAP_MAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CFGIU1MAP */
+#define MPAHBRAM_CFGIU1MAP_MAP_DEFAULT (_MPAHBRAM_CFGIU1MAP_MAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CFGIU1MAP */
+
+/* Bit fields for MPAHBRAM CFGIU2MAP */
+#define _MPAHBRAM_CFGIU2MAP_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_CFGIU2MAP */
+#define _MPAHBRAM_CFGIU2MAP_MASK 0x0000FFFFUL /**< Mask for MPAHBRAM_CFGIU2MAP */
+#define _MPAHBRAM_CFGIU2MAP_MAP_SHIFT 0 /**< Shift value for MPAHBRAM_MAP */
+#define _MPAHBRAM_CFGIU2MAP_MAP_MASK 0xFFFFUL /**< Bit mask for MPAHBRAM_MAP */
+#define _MPAHBRAM_CFGIU2MAP_MAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CFGIU2MAP */
+#define MPAHBRAM_CFGIU2MAP_MAP_DEFAULT (_MPAHBRAM_CFGIU2MAP_MAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CFGIU2MAP */
+
+/* Bit fields for MPAHBRAM CFGIU3MAP */
+#define _MPAHBRAM_CFGIU3MAP_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_CFGIU3MAP */
+#define _MPAHBRAM_CFGIU3MAP_MASK 0x0000FFFFUL /**< Mask for MPAHBRAM_CFGIU3MAP */
+#define _MPAHBRAM_CFGIU3MAP_MAP_SHIFT 0 /**< Shift value for MPAHBRAM_MAP */
+#define _MPAHBRAM_CFGIU3MAP_MAP_MASK 0xFFFFUL /**< Bit mask for MPAHBRAM_MAP */
+#define _MPAHBRAM_CFGIU3MAP_MAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CFGIU3MAP */
+#define MPAHBRAM_CFGIU3MAP_MAP_DEFAULT (_MPAHBRAM_CFGIU3MAP_MAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CFGIU3MAP */
+
+/** @} End of group EFR32MG24_MPAHBRAM_BitFields */
+/** @} End of group EFR32MG24_MPAHBRAM */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_MPAHBRAM_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_msc.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_msc.h
new file mode 100644
index 00000000..7442b047
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_msc.h
@@ -0,0 +1,546 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 MSC register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_MSC_H
+#define EFR32MG24_MSC_H
+#define MSC_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_MSC MSC
+ * @{
+ * @brief EFR32MG24 MSC Register Declaration.
+ *****************************************************************************/
+
+/** MSC Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IP version ID */
+ __IOM uint32_t READCTRL; /**< Read Control Register */
+ __IOM uint32_t RDATACTRL; /**< Read Data Control Register */
+ __IOM uint32_t WRITECTRL; /**< Write Control Register */
+ __IOM uint32_t WRITECMD; /**< Write Command Register */
+ __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */
+ __IOM uint32_t WDATA; /**< Write Data Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IOM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ uint32_t RESERVED0[3U]; /**< Reserved for future use */
+ __IM uint32_t USERDATASIZE; /**< User Data Region Size Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IOM uint32_t LOCK; /**< Configuration Lock Register */
+ __IOM uint32_t MISCLOCKWORD; /**< Mass erase and User data page lock word */
+ uint32_t RESERVED1[3U]; /**< Reserved for future use */
+ __IOM uint32_t PWRCTRL; /**< Power control register */
+ uint32_t RESERVED2[51U]; /**< Reserved for future use */
+ __IOM uint32_t PAGELOCK0; /**< Main space page 0-31 lock word */
+ __IOM uint32_t PAGELOCK1; /**< Main space page 32-63 lock word */
+ __IOM uint32_t PAGELOCK2; /**< Main space page 64-95 lock word */
+ __IOM uint32_t PAGELOCK3; /**< Main space page 96-127 lock word */
+ __IOM uint32_t PAGELOCK4; /**< Main space page 128-159 lock word */
+ __IOM uint32_t PAGELOCK5; /**< Main space page 160-191 lock word */
+ uint32_t RESERVED3[2U]; /**< Reserved for future use */
+ uint32_t RESERVED4[4U]; /**< Reserved for future use */
+ uint32_t RESERVED5[4U]; /**< Reserved for future use */
+ uint32_t RESERVED6[4U]; /**< Reserved for future use */
+ uint32_t RESERVED7[12U]; /**< Reserved for future use */
+ uint32_t RESERVED8[1U]; /**< Reserved for future use */
+ uint32_t RESERVED9[8U]; /**< Reserved for future use */
+ uint32_t RESERVED10[1U]; /**< Reserved for future use */
+ uint32_t RESERVED11[910U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP version ID */
+ __IOM uint32_t READCTRL_SET; /**< Read Control Register */
+ __IOM uint32_t RDATACTRL_SET; /**< Read Data Control Register */
+ __IOM uint32_t WRITECTRL_SET; /**< Write Control Register */
+ __IOM uint32_t WRITECMD_SET; /**< Write Command Register */
+ __IOM uint32_t ADDRB_SET; /**< Page Erase/Write Address Buffer */
+ __IOM uint32_t WDATA_SET; /**< Write Data Register */
+ __IM uint32_t STATUS_SET; /**< Status Register */
+ __IOM uint32_t IF_SET; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
+ uint32_t RESERVED12[3U]; /**< Reserved for future use */
+ __IM uint32_t USERDATASIZE_SET; /**< User Data Region Size Register */
+ __IOM uint32_t CMD_SET; /**< Command Register */
+ __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */
+ __IOM uint32_t MISCLOCKWORD_SET; /**< Mass erase and User data page lock word */
+ uint32_t RESERVED13[3U]; /**< Reserved for future use */
+ __IOM uint32_t PWRCTRL_SET; /**< Power control register */
+ uint32_t RESERVED14[51U]; /**< Reserved for future use */
+ __IOM uint32_t PAGELOCK0_SET; /**< Main space page 0-31 lock word */
+ __IOM uint32_t PAGELOCK1_SET; /**< Main space page 32-63 lock word */
+ __IOM uint32_t PAGELOCK2_SET; /**< Main space page 64-95 lock word */
+ __IOM uint32_t PAGELOCK3_SET; /**< Main space page 96-127 lock word */
+ __IOM uint32_t PAGELOCK4_SET; /**< Main space page 128-159 lock word */
+ __IOM uint32_t PAGELOCK5_SET; /**< Main space page 160-191 lock word */
+ uint32_t RESERVED15[2U]; /**< Reserved for future use */
+ uint32_t RESERVED16[4U]; /**< Reserved for future use */
+ uint32_t RESERVED17[4U]; /**< Reserved for future use */
+ uint32_t RESERVED18[4U]; /**< Reserved for future use */
+ uint32_t RESERVED19[12U]; /**< Reserved for future use */
+ uint32_t RESERVED20[1U]; /**< Reserved for future use */
+ uint32_t RESERVED21[8U]; /**< Reserved for future use */
+ uint32_t RESERVED22[1U]; /**< Reserved for future use */
+ uint32_t RESERVED23[910U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP version ID */
+ __IOM uint32_t READCTRL_CLR; /**< Read Control Register */
+ __IOM uint32_t RDATACTRL_CLR; /**< Read Data Control Register */
+ __IOM uint32_t WRITECTRL_CLR; /**< Write Control Register */
+ __IOM uint32_t WRITECMD_CLR; /**< Write Command Register */
+ __IOM uint32_t ADDRB_CLR; /**< Page Erase/Write Address Buffer */
+ __IOM uint32_t WDATA_CLR; /**< Write Data Register */
+ __IM uint32_t STATUS_CLR; /**< Status Register */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
+ uint32_t RESERVED24[3U]; /**< Reserved for future use */
+ __IM uint32_t USERDATASIZE_CLR; /**< User Data Region Size Register */
+ __IOM uint32_t CMD_CLR; /**< Command Register */
+ __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */
+ __IOM uint32_t MISCLOCKWORD_CLR; /**< Mass erase and User data page lock word */
+ uint32_t RESERVED25[3U]; /**< Reserved for future use */
+ __IOM uint32_t PWRCTRL_CLR; /**< Power control register */
+ uint32_t RESERVED26[51U]; /**< Reserved for future use */
+ __IOM uint32_t PAGELOCK0_CLR; /**< Main space page 0-31 lock word */
+ __IOM uint32_t PAGELOCK1_CLR; /**< Main space page 32-63 lock word */
+ __IOM uint32_t PAGELOCK2_CLR; /**< Main space page 64-95 lock word */
+ __IOM uint32_t PAGELOCK3_CLR; /**< Main space page 96-127 lock word */
+ __IOM uint32_t PAGELOCK4_CLR; /**< Main space page 128-159 lock word */
+ __IOM uint32_t PAGELOCK5_CLR; /**< Main space page 160-191 lock word */
+ uint32_t RESERVED27[2U]; /**< Reserved for future use */
+ uint32_t RESERVED28[4U]; /**< Reserved for future use */
+ uint32_t RESERVED29[4U]; /**< Reserved for future use */
+ uint32_t RESERVED30[4U]; /**< Reserved for future use */
+ uint32_t RESERVED31[12U]; /**< Reserved for future use */
+ uint32_t RESERVED32[1U]; /**< Reserved for future use */
+ uint32_t RESERVED33[8U]; /**< Reserved for future use */
+ uint32_t RESERVED34[1U]; /**< Reserved for future use */
+ uint32_t RESERVED35[910U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP version ID */
+ __IOM uint32_t READCTRL_TGL; /**< Read Control Register */
+ __IOM uint32_t RDATACTRL_TGL; /**< Read Data Control Register */
+ __IOM uint32_t WRITECTRL_TGL; /**< Write Control Register */
+ __IOM uint32_t WRITECMD_TGL; /**< Write Command Register */
+ __IOM uint32_t ADDRB_TGL; /**< Page Erase/Write Address Buffer */
+ __IOM uint32_t WDATA_TGL; /**< Write Data Register */
+ __IM uint32_t STATUS_TGL; /**< Status Register */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
+ uint32_t RESERVED36[3U]; /**< Reserved for future use */
+ __IM uint32_t USERDATASIZE_TGL; /**< User Data Region Size Register */
+ __IOM uint32_t CMD_TGL; /**< Command Register */
+ __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */
+ __IOM uint32_t MISCLOCKWORD_TGL; /**< Mass erase and User data page lock word */
+ uint32_t RESERVED37[3U]; /**< Reserved for future use */
+ __IOM uint32_t PWRCTRL_TGL; /**< Power control register */
+ uint32_t RESERVED38[51U]; /**< Reserved for future use */
+ __IOM uint32_t PAGELOCK0_TGL; /**< Main space page 0-31 lock word */
+ __IOM uint32_t PAGELOCK1_TGL; /**< Main space page 32-63 lock word */
+ __IOM uint32_t PAGELOCK2_TGL; /**< Main space page 64-95 lock word */
+ __IOM uint32_t PAGELOCK3_TGL; /**< Main space page 96-127 lock word */
+ __IOM uint32_t PAGELOCK4_TGL; /**< Main space page 128-159 lock word */
+ __IOM uint32_t PAGELOCK5_TGL; /**< Main space page 160-191 lock word */
+ uint32_t RESERVED39[2U]; /**< Reserved for future use */
+ uint32_t RESERVED40[4U]; /**< Reserved for future use */
+ uint32_t RESERVED41[4U]; /**< Reserved for future use */
+ uint32_t RESERVED42[4U]; /**< Reserved for future use */
+ uint32_t RESERVED43[12U]; /**< Reserved for future use */
+ uint32_t RESERVED44[1U]; /**< Reserved for future use */
+ uint32_t RESERVED45[8U]; /**< Reserved for future use */
+ uint32_t RESERVED46[1U]; /**< Reserved for future use */
+} MSC_TypeDef;
+/** @} End of group EFR32MG24_MSC */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_MSC
+ * @{
+ * @defgroup EFR32MG24_MSC_BitFields MSC Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for MSC IPVERSION */
+#define _MSC_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for MSC_IPVERSION */
+#define _MSC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for MSC_IPVERSION */
+#define _MSC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MSC_IPVERSION */
+#define _MSC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_IPVERSION */
+#define _MSC_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_IPVERSION */
+#define MSC_IPVERSION_IPVERSION_DEFAULT (_MSC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IPVERSION */
+
+/* Bit fields for MSC READCTRL */
+#define _MSC_READCTRL_RESETVALUE 0x00200000UL /**< Default value for MSC_READCTRL */
+#define _MSC_READCTRL_MASK 0x00300000UL /**< Mask for MSC_READCTRL */
+#define _MSC_READCTRL_MODE_SHIFT 20 /**< Shift value for MSC_MODE */
+#define _MSC_READCTRL_MODE_MASK 0x300000UL /**< Bit mask for MSC_MODE */
+#define _MSC_READCTRL_MODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for MSC_READCTRL */
+#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */
+#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */
+#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */
+#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */
+#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 20) /**< Shifted mode DEFAULT for MSC_READCTRL */
+#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 20) /**< Shifted mode WS0 for MSC_READCTRL */
+#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 20) /**< Shifted mode WS1 for MSC_READCTRL */
+#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 20) /**< Shifted mode WS2 for MSC_READCTRL */
+#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 20) /**< Shifted mode WS3 for MSC_READCTRL */
+
+/* Bit fields for MSC RDATACTRL */
+#define _MSC_RDATACTRL_RESETVALUE 0x00001000UL /**< Default value for MSC_RDATACTRL */
+#define _MSC_RDATACTRL_MASK 0x00001002UL /**< Mask for MSC_RDATACTRL */
+#define MSC_RDATACTRL_AFDIS (0x1UL << 1) /**< Automatic Invalidate Disable */
+#define _MSC_RDATACTRL_AFDIS_SHIFT 1 /**< Shift value for MSC_AFDIS */
+#define _MSC_RDATACTRL_AFDIS_MASK 0x2UL /**< Bit mask for MSC_AFDIS */
+#define _MSC_RDATACTRL_AFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RDATACTRL */
+#define MSC_RDATACTRL_AFDIS_DEFAULT (_MSC_RDATACTRL_AFDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RDATACTRL */
+#define MSC_RDATACTRL_DOUTBUFEN (0x1UL << 12) /**< Flash dout pipeline buffer enable */
+#define _MSC_RDATACTRL_DOUTBUFEN_SHIFT 12 /**< Shift value for MSC_DOUTBUFEN */
+#define _MSC_RDATACTRL_DOUTBUFEN_MASK 0x1000UL /**< Bit mask for MSC_DOUTBUFEN */
+#define _MSC_RDATACTRL_DOUTBUFEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_RDATACTRL */
+#define MSC_RDATACTRL_DOUTBUFEN_DEFAULT (_MSC_RDATACTRL_DOUTBUFEN_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_RDATACTRL */
+
+/* Bit fields for MSC WRITECTRL */
+#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */
+#define _MSC_WRITECTRL_MASK 0x03FF000BUL /**< Mask for MSC_WRITECTRL */
+#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */
+#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */
+#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */
+#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
+#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
+#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */
+#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */
+#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */
+#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
+#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
+#define MSC_WRITECTRL_LPWRITE (0x1UL << 3) /**< Low-Power Erase */
+#define _MSC_WRITECTRL_LPWRITE_SHIFT 3 /**< Shift value for MSC_LPWRITE */
+#define _MSC_WRITECTRL_LPWRITE_MASK 0x8UL /**< Bit mask for MSC_LPWRITE */
+#define _MSC_WRITECTRL_LPWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
+#define MSC_WRITECTRL_LPWRITE_DEFAULT (_MSC_WRITECTRL_LPWRITE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
+#define _MSC_WRITECTRL_RANGECOUNT_SHIFT 16 /**< Shift value for MSC_RANGECOUNT */
+#define _MSC_WRITECTRL_RANGECOUNT_MASK 0x3FF0000UL /**< Bit mask for MSC_RANGECOUNT */
+#define _MSC_WRITECTRL_RANGECOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
+#define MSC_WRITECTRL_RANGECOUNT_DEFAULT (_MSC_WRITECTRL_RANGECOUNT_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
+
+/* Bit fields for MSC WRITECMD */
+#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */
+#define _MSC_WRITECMD_MASK 0x00001136UL /**< Mask for MSC_WRITECMD */
+#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */
+#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */
+#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */
+#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */
+#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */
+#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */
+#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_ERASERANGE (0x1UL << 4) /**< Erase range of pages */
+#define _MSC_WRITECMD_ERASERANGE_SHIFT 4 /**< Shift value for MSC_ERASERANGE */
+#define _MSC_WRITECMD_ERASERANGE_MASK 0x10UL /**< Bit mask for MSC_ERASERANGE */
+#define _MSC_WRITECMD_ERASERANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_ERASERANGE_DEFAULT (_MSC_WRITECMD_ERASERANGE_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */
+#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */
+#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */
+#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */
+#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */
+#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */
+#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */
+#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */
+#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */
+#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
+#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */
+
+/* Bit fields for MSC ADDRB */
+#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */
+#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */
+#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */
+#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */
+#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */
+#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */
+
+/* Bit fields for MSC WDATA */
+#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */
+#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */
+#define _MSC_WDATA_DATAW_SHIFT 0 /**< Shift value for MSC_DATAW */
+#define _MSC_WDATA_DATAW_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_DATAW */
+#define _MSC_WDATA_DATAW_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */
+#define MSC_WDATA_DATAW_DEFAULT (_MSC_WDATA_DATAW_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */
+
+/* Bit fields for MSC STATUS */
+#define _MSC_STATUS_RESETVALUE 0x08000008UL /**< Default value for MSC_STATUS */
+#define _MSC_STATUS_MASK 0xF90100FFUL /**< Mask for MSC_STATUS */
+#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */
+#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */
+#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */
+#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */
+#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */
+#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */
+#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */
+#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */
+#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */
+#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */
+#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */
+#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */
+#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_ERASEABORTED (0x1UL << 4) /**< The Current Flash Erase Operation Aborte */
+#define _MSC_STATUS_ERASEABORTED_SHIFT 4 /**< Shift value for MSC_ERASEABORTED */
+#define _MSC_STATUS_ERASEABORTED_MASK 0x10UL /**< Bit mask for MSC_ERASEABORTED */
+#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_PENDING (0x1UL << 5) /**< Write command is in queue */
+#define _MSC_STATUS_PENDING_SHIFT 5 /**< Shift value for MSC_PENDING */
+#define _MSC_STATUS_PENDING_MASK 0x20UL /**< Bit mask for MSC_PENDING */
+#define _MSC_STATUS_PENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_PENDING_DEFAULT (_MSC_STATUS_PENDING_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_TIMEOUT (0x1UL << 6) /**< Write command timeout flag */
+#define _MSC_STATUS_TIMEOUT_SHIFT 6 /**< Shift value for MSC_TIMEOUT */
+#define _MSC_STATUS_TIMEOUT_MASK 0x40UL /**< Bit mask for MSC_TIMEOUT */
+#define _MSC_STATUS_TIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_TIMEOUT_DEFAULT (_MSC_STATUS_TIMEOUT_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_RANGEPARTIAL (0x1UL << 7) /**< EraseRange with skipped locked pages */
+#define _MSC_STATUS_RANGEPARTIAL_SHIFT 7 /**< Shift value for MSC_RANGEPARTIAL */
+#define _MSC_STATUS_RANGEPARTIAL_MASK 0x80UL /**< Bit mask for MSC_RANGEPARTIAL */
+#define _MSC_STATUS_RANGEPARTIAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_RANGEPARTIAL_DEFAULT (_MSC_STATUS_RANGEPARTIAL_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_REGLOCK (0x1UL << 16) /**< Register Lock Status */
+#define _MSC_STATUS_REGLOCK_SHIFT 16 /**< Shift value for MSC_REGLOCK */
+#define _MSC_STATUS_REGLOCK_MASK 0x10000UL /**< Bit mask for MSC_REGLOCK */
+#define _MSC_STATUS_REGLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
+#define _MSC_STATUS_REGLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_STATUS */
+#define _MSC_STATUS_REGLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_STATUS */
+#define MSC_STATUS_REGLOCK_DEFAULT (_MSC_STATUS_REGLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_REGLOCK_UNLOCKED (_MSC_STATUS_REGLOCK_UNLOCKED << 16) /**< Shifted mode UNLOCKED for MSC_STATUS */
+#define MSC_STATUS_REGLOCK_LOCKED (_MSC_STATUS_REGLOCK_LOCKED << 16) /**< Shifted mode LOCKED for MSC_STATUS */
+#define MSC_STATUS_PWRON (0x1UL << 24) /**< Flash power on status */
+#define _MSC_STATUS_PWRON_SHIFT 24 /**< Shift value for MSC_PWRON */
+#define _MSC_STATUS_PWRON_MASK 0x1000000UL /**< Bit mask for MSC_PWRON */
+#define _MSC_STATUS_PWRON_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_PWRON_DEFAULT (_MSC_STATUS_PWRON_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_WREADY (0x1UL << 27) /**< Flash Write Ready */
+#define _MSC_STATUS_WREADY_SHIFT 27 /**< Shift value for MSC_WREADY */
+#define _MSC_STATUS_WREADY_MASK 0x8000000UL /**< Bit mask for MSC_WREADY */
+#define _MSC_STATUS_WREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_WREADY_DEFAULT (_MSC_STATUS_WREADY_DEFAULT << 27) /**< Shifted mode DEFAULT for MSC_STATUS */
+#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */
+#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */
+#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
+#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */
+
+/* Bit fields for MSC IF */
+#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */
+#define _MSC_IF_MASK 0x00000307UL /**< Mask for MSC_IF */
+#define MSC_IF_ERASE (0x1UL << 0) /**< Host Erase Done Interrupt Read Flag */
+#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
+#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
+#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
+#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */
+#define MSC_IF_WRITE (0x1UL << 1) /**< Host Write Done Interrupt Read Flag */
+#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
+#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
+#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
+#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */
+#define MSC_IF_WDATAOV (0x1UL << 2) /**< Host write buffer overflow */
+#define _MSC_IF_WDATAOV_SHIFT 2 /**< Shift value for MSC_WDATAOV */
+#define _MSC_IF_WDATAOV_MASK 0x4UL /**< Bit mask for MSC_WDATAOV */
+#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
+#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */
+#define MSC_IF_PWRUPF (0x1UL << 8) /**< Flash Power Up Sequence Complete Flag */
+#define _MSC_IF_PWRUPF_SHIFT 8 /**< Shift value for MSC_PWRUPF */
+#define _MSC_IF_PWRUPF_MASK 0x100UL /**< Bit mask for MSC_PWRUPF */
+#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
+#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */
+#define MSC_IF_PWROFF (0x1UL << 9) /**< Flash Power Off Sequence Complete Flag */
+#define _MSC_IF_PWROFF_SHIFT 9 /**< Shift value for MSC_PWROFF */
+#define _MSC_IF_PWROFF_MASK 0x200UL /**< Bit mask for MSC_PWROFF */
+#define _MSC_IF_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
+#define MSC_IF_PWROFF_DEFAULT (_MSC_IF_PWROFF_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_IF */
+
+/* Bit fields for MSC IEN */
+#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */
+#define _MSC_IEN_MASK 0x00000307UL /**< Mask for MSC_IEN */
+#define MSC_IEN_ERASE (0x1UL << 0) /**< Erase Done Interrupt enable */
+#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
+#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
+#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
+#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */
+#define MSC_IEN_WRITE (0x1UL << 1) /**< Write Done Interrupt enable */
+#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
+#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
+#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
+#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */
+#define MSC_IEN_WDATAOV (0x1UL << 2) /**< write data buffer overflow irq enable */
+#define _MSC_IEN_WDATAOV_SHIFT 2 /**< Shift value for MSC_WDATAOV */
+#define _MSC_IEN_WDATAOV_MASK 0x4UL /**< Bit mask for MSC_WDATAOV */
+#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
+#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */
+#define MSC_IEN_PWRUPF (0x1UL << 8) /**< Flash Power Up Seq done irq enable */
+#define _MSC_IEN_PWRUPF_SHIFT 8 /**< Shift value for MSC_PWRUPF */
+#define _MSC_IEN_PWRUPF_MASK 0x100UL /**< Bit mask for MSC_PWRUPF */
+#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
+#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */
+#define MSC_IEN_PWROFF (0x1UL << 9) /**< Flash Power Off Seq done irq enable */
+#define _MSC_IEN_PWROFF_SHIFT 9 /**< Shift value for MSC_PWROFF */
+#define _MSC_IEN_PWROFF_MASK 0x200UL /**< Bit mask for MSC_PWROFF */
+#define _MSC_IEN_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
+#define MSC_IEN_PWROFF_DEFAULT (_MSC_IEN_PWROFF_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_IEN */
+
+/* Bit fields for MSC USERDATASIZE */
+#define _MSC_USERDATASIZE_RESETVALUE 0x00000004UL /**< Default value for MSC_USERDATASIZE */
+#define _MSC_USERDATASIZE_MASK 0x0000003FUL /**< Mask for MSC_USERDATASIZE */
+#define _MSC_USERDATASIZE_USERDATASIZE_SHIFT 0 /**< Shift value for MSC_USERDATASIZE */
+#define _MSC_USERDATASIZE_USERDATASIZE_MASK 0x3FUL /**< Bit mask for MSC_USERDATASIZE */
+#define _MSC_USERDATASIZE_USERDATASIZE_DEFAULT 0x00000004UL /**< Mode DEFAULT for MSC_USERDATASIZE */
+#define MSC_USERDATASIZE_USERDATASIZE_DEFAULT (_MSC_USERDATASIZE_USERDATASIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_USERDATASIZE */
+
+/* Bit fields for MSC CMD */
+#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */
+#define _MSC_CMD_MASK 0x00000011UL /**< Mask for MSC_CMD */
+#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */
+#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */
+#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */
+#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */
+#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */
+#define MSC_CMD_PWROFF (0x1UL << 4) /**< Flash power off/sleep command */
+#define _MSC_CMD_PWROFF_SHIFT 4 /**< Shift value for MSC_PWROFF */
+#define _MSC_CMD_PWROFF_MASK 0x10UL /**< Bit mask for MSC_PWROFF */
+#define _MSC_CMD_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */
+#define MSC_CMD_PWROFF_DEFAULT (_MSC_CMD_PWROFF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CMD */
+
+/* Bit fields for MSC LOCK */
+#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */
+#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */
+#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
+#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
+#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */
+#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */
+#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */
+#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */
+#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */
+#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */
+
+/* Bit fields for MSC MISCLOCKWORD */
+#define _MSC_MISCLOCKWORD_RESETVALUE 0x00000011UL /**< Default value for MSC_MISCLOCKWORD */
+#define _MSC_MISCLOCKWORD_MASK 0x00000011UL /**< Mask for MSC_MISCLOCKWORD */
+#define MSC_MISCLOCKWORD_MELOCKBIT (0x1UL << 0) /**< Mass Erase Lock */
+#define _MSC_MISCLOCKWORD_MELOCKBIT_SHIFT 0 /**< Shift value for MSC_MELOCKBIT */
+#define _MSC_MISCLOCKWORD_MELOCKBIT_MASK 0x1UL /**< Bit mask for MSC_MELOCKBIT */
+#define _MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MISCLOCKWORD */
+#define MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT (_MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MISCLOCKWORD */
+#define MSC_MISCLOCKWORD_UDLOCKBIT (0x1UL << 4) /**< User Data Lock */
+#define _MSC_MISCLOCKWORD_UDLOCKBIT_SHIFT 4 /**< Shift value for MSC_UDLOCKBIT */
+#define _MSC_MISCLOCKWORD_UDLOCKBIT_MASK 0x10UL /**< Bit mask for MSC_UDLOCKBIT */
+#define _MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MISCLOCKWORD */
+#define MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT (_MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_MISCLOCKWORD */
+
+/* Bit fields for MSC PWRCTRL */
+#define _MSC_PWRCTRL_RESETVALUE 0x00100002UL /**< Default value for MSC_PWRCTRL */
+#define _MSC_PWRCTRL_MASK 0x00FF0013UL /**< Mask for MSC_PWRCTRL */
+#define MSC_PWRCTRL_PWROFFONEM1ENTRY (0x1UL << 0) /**< Power down Flash macro when enter EM1 */
+#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_SHIFT 0 /**< Shift value for MSC_PWROFFONEM1ENTRY */
+#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_MASK 0x1UL /**< Bit mask for MSC_PWROFFONEM1ENTRY */
+#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PWRCTRL */
+#define MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT (_MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PWRCTRL */
+#define MSC_PWRCTRL_PWROFFONEM1PENTRY (0x1UL << 1) /**< Power down Flash macro when enter EM1P */
+#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_SHIFT 1 /**< Shift value for MSC_PWROFFONEM1PENTRY */
+#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_MASK 0x2UL /**< Bit mask for MSC_PWROFFONEM1PENTRY */
+#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_PWRCTRL */
+#define MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT (_MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_PWRCTRL */
+#define MSC_PWRCTRL_PWROFFENTRYAGAIN (0x1UL << 4) /**< POWER down flash again in EM1/EM1p */
+#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_SHIFT 4 /**< Shift value for MSC_PWROFFENTRYAGAIN */
+#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_MASK 0x10UL /**< Bit mask for MSC_PWROFFENTRYAGAIN */
+#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PWRCTRL */
+#define MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT (_MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_PWRCTRL */
+#define _MSC_PWRCTRL_PWROFFDLY_SHIFT 16 /**< Shift value for MSC_PWROFFDLY */
+#define _MSC_PWRCTRL_PWROFFDLY_MASK 0xFF0000UL /**< Bit mask for MSC_PWROFFDLY */
+#define _MSC_PWRCTRL_PWROFFDLY_DEFAULT 0x00000010UL /**< Mode DEFAULT for MSC_PWRCTRL */
+#define MSC_PWRCTRL_PWROFFDLY_DEFAULT (_MSC_PWRCTRL_PWROFFDLY_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_PWRCTRL */
+
+/* Bit fields for MSC PAGELOCK0 */
+#define _MSC_PAGELOCK0_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK0 */
+#define _MSC_PAGELOCK0_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK0 */
+#define _MSC_PAGELOCK0_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */
+#define _MSC_PAGELOCK0_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */
+#define _MSC_PAGELOCK0_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK0 */
+#define MSC_PAGELOCK0_LOCKBIT_DEFAULT (_MSC_PAGELOCK0_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK0 */
+
+/* Bit fields for MSC PAGELOCK1 */
+#define _MSC_PAGELOCK1_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK1 */
+#define _MSC_PAGELOCK1_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK1 */
+#define _MSC_PAGELOCK1_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */
+#define _MSC_PAGELOCK1_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */
+#define _MSC_PAGELOCK1_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK1 */
+#define MSC_PAGELOCK1_LOCKBIT_DEFAULT (_MSC_PAGELOCK1_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK1 */
+
+/* Bit fields for MSC PAGELOCK2 */
+#define _MSC_PAGELOCK2_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK2 */
+#define _MSC_PAGELOCK2_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK2 */
+#define _MSC_PAGELOCK2_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */
+#define _MSC_PAGELOCK2_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */
+#define _MSC_PAGELOCK2_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK2 */
+#define MSC_PAGELOCK2_LOCKBIT_DEFAULT (_MSC_PAGELOCK2_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK2 */
+
+/* Bit fields for MSC PAGELOCK3 */
+#define _MSC_PAGELOCK3_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK3 */
+#define _MSC_PAGELOCK3_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK3 */
+#define _MSC_PAGELOCK3_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */
+#define _MSC_PAGELOCK3_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */
+#define _MSC_PAGELOCK3_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK3 */
+#define MSC_PAGELOCK3_LOCKBIT_DEFAULT (_MSC_PAGELOCK3_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK3 */
+
+/* Bit fields for MSC PAGELOCK4 */
+#define _MSC_PAGELOCK4_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK4 */
+#define _MSC_PAGELOCK4_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK4 */
+#define _MSC_PAGELOCK4_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */
+#define _MSC_PAGELOCK4_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */
+#define _MSC_PAGELOCK4_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK4 */
+#define MSC_PAGELOCK4_LOCKBIT_DEFAULT (_MSC_PAGELOCK4_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK4 */
+
+/* Bit fields for MSC PAGELOCK5 */
+#define _MSC_PAGELOCK5_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK5 */
+#define _MSC_PAGELOCK5_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK5 */
+#define _MSC_PAGELOCK5_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */
+#define _MSC_PAGELOCK5_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */
+#define _MSC_PAGELOCK5_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK5 */
+#define MSC_PAGELOCK5_LOCKBIT_DEFAULT (_MSC_PAGELOCK5_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK5 */
+
+/** @} End of group EFR32MG24_MSC_BitFields */
+/** @} End of group EFR32MG24_MSC */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_MSC_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_mvp.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_mvp.h
new file mode 100644
index 00000000..2cf1f28b
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_mvp.h
@@ -0,0 +1,1386 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 MVP register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_MVP_H
+#define EFR32MG24_MVP_H
+#define MVP_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_MVP MVP
+ * @{
+ * @brief EFR32MG24 MVP Register Declaration.
+ *****************************************************************************/
+
+/** MVP PERF Register Group Declaration. */
+typedef struct {
+ __IM uint32_t CNT; /**< Run Counter */
+} MVP_PERF_TypeDef;
+
+/** MVP ARRAYST Register Group Declaration. */
+typedef struct {
+ __IOM uint32_t INDEXSTATE; /**< Index State */
+} MVP_ARRAYST_TypeDef;
+
+/** MVP LOOPST Register Group Declaration. */
+typedef struct {
+ __IOM uint32_t STATE; /**< Loop State */
+} MVP_LOOPST_TypeDef;
+
+/** MVP ALU Register Group Declaration. */
+typedef struct {
+ __IOM uint32_t REGSTATE; /**< ALU Rn Register */
+} MVP_ALU_TypeDef;
+
+/** MVP ARRAY Register Group Declaration. */
+typedef struct {
+ __IOM uint32_t ADDRCFG; /**< Array Base Address */
+ __IOM uint32_t DIM0CFG; /**< Dimension 0 Configuration */
+ __IOM uint32_t DIM1CFG; /**< Dimension 1 Configuration */
+ __IOM uint32_t DIM2CFG; /**< Dimension 2 Configuration */
+} MVP_ARRAY_TypeDef;
+
+/** MVP LOOP Register Group Declaration. */
+typedef struct {
+ __IOM uint32_t CFG; /**< Loop Configuration */
+ __IOM uint32_t RST; /**< Loop Reset */
+} MVP_LOOP_TypeDef;
+
+/** MVP INSTR Register Group Declaration. */
+typedef struct {
+ __IOM uint32_t CFG0; /**< Instruction Configuration Word 0 */
+ __IOM uint32_t CFG1; /**< Instruction Configuration Word 1 */
+ __IOM uint32_t CFG2; /**< Instruction Configuration Word 2 */
+} MVP_INSTR_TypeDef;
+
+/** MVP Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IP Version */
+ __IOM uint32_t EN; /**< Enable */
+ __IOM uint32_t SWRST; /**< Software Reset */
+ __IOM uint32_t CFG; /**< Configuration */
+ __IM uint32_t STATUS; /**< Status */
+ MVP_PERF_TypeDef PERF[2U]; /**< */
+ __IOM uint32_t IF; /**< Interrupt Flags */
+ __IOM uint32_t IEN; /**< Interrupt Enables */
+ __IM uint32_t FAULTSTATUS; /**< Fault Status */
+ __IM uint32_t FAULTADDR; /**< Fault Address */
+ __IOM uint32_t PROGRAMSTATE; /**< Program State */
+ MVP_ARRAYST_TypeDef ARRAYST[5U]; /**< */
+ MVP_LOOPST_TypeDef LOOPST[8U]; /**< */
+ MVP_ALU_TypeDef ALU[8U]; /**< */
+ MVP_ARRAY_TypeDef ARRAY[5U]; /**< */
+ MVP_LOOP_TypeDef LOOP[8U]; /**< */
+ MVP_INSTR_TypeDef INSTR[8U]; /**< */
+ __IOM uint32_t CMD; /**< Command Register */
+ uint32_t RESERVED0[34U]; /**< Reserved for future use */
+ __IOM uint32_t DEBUGEN; /**< Debug Enable Register */
+ __IOM uint32_t DEBUGSTEPCNT; /**< Debug Step Register */
+ uint32_t RESERVED1[894U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP Version */
+ __IOM uint32_t EN_SET; /**< Enable */
+ __IOM uint32_t SWRST_SET; /**< Software Reset */
+ __IOM uint32_t CFG_SET; /**< Configuration */
+ __IM uint32_t STATUS_SET; /**< Status */
+ MVP_PERF_TypeDef PERF_SET[2U]; /**< */
+ __IOM uint32_t IF_SET; /**< Interrupt Flags */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enables */
+ __IM uint32_t FAULTSTATUS_SET; /**< Fault Status */
+ __IM uint32_t FAULTADDR_SET; /**< Fault Address */
+ __IOM uint32_t PROGRAMSTATE_SET; /**< Program State */
+ MVP_ARRAYST_TypeDef ARRAYST_SET[5U]; /**< */
+ MVP_LOOPST_TypeDef LOOPST_SET[8U]; /**< */
+ MVP_ALU_TypeDef ALU_SET[8U]; /**< */
+ MVP_ARRAY_TypeDef ARRAY_SET[5U]; /**< */
+ MVP_LOOP_TypeDef LOOP_SET[8U]; /**< */
+ MVP_INSTR_TypeDef INSTR_SET[8U]; /**< */
+ __IOM uint32_t CMD_SET; /**< Command Register */
+ uint32_t RESERVED2[34U]; /**< Reserved for future use */
+ __IOM uint32_t DEBUGEN_SET; /**< Debug Enable Register */
+ __IOM uint32_t DEBUGSTEPCNT_SET; /**< Debug Step Register */
+ uint32_t RESERVED3[894U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP Version */
+ __IOM uint32_t EN_CLR; /**< Enable */
+ __IOM uint32_t SWRST_CLR; /**< Software Reset */
+ __IOM uint32_t CFG_CLR; /**< Configuration */
+ __IM uint32_t STATUS_CLR; /**< Status */
+ MVP_PERF_TypeDef PERF_CLR[2U]; /**< */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flags */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enables */
+ __IM uint32_t FAULTSTATUS_CLR; /**< Fault Status */
+ __IM uint32_t FAULTADDR_CLR; /**< Fault Address */
+ __IOM uint32_t PROGRAMSTATE_CLR; /**< Program State */
+ MVP_ARRAYST_TypeDef ARRAYST_CLR[5U]; /**< */
+ MVP_LOOPST_TypeDef LOOPST_CLR[8U]; /**< */
+ MVP_ALU_TypeDef ALU_CLR[8U]; /**< */
+ MVP_ARRAY_TypeDef ARRAY_CLR[5U]; /**< */
+ MVP_LOOP_TypeDef LOOP_CLR[8U]; /**< */
+ MVP_INSTR_TypeDef INSTR_CLR[8U]; /**< */
+ __IOM uint32_t CMD_CLR; /**< Command Register */
+ uint32_t RESERVED4[34U]; /**< Reserved for future use */
+ __IOM uint32_t DEBUGEN_CLR; /**< Debug Enable Register */
+ __IOM uint32_t DEBUGSTEPCNT_CLR; /**< Debug Step Register */
+ uint32_t RESERVED5[894U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP Version */
+ __IOM uint32_t EN_TGL; /**< Enable */
+ __IOM uint32_t SWRST_TGL; /**< Software Reset */
+ __IOM uint32_t CFG_TGL; /**< Configuration */
+ __IM uint32_t STATUS_TGL; /**< Status */
+ MVP_PERF_TypeDef PERF_TGL[2U]; /**< */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flags */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enables */
+ __IM uint32_t FAULTSTATUS_TGL; /**< Fault Status */
+ __IM uint32_t FAULTADDR_TGL; /**< Fault Address */
+ __IOM uint32_t PROGRAMSTATE_TGL; /**< Program State */
+ MVP_ARRAYST_TypeDef ARRAYST_TGL[5U]; /**< */
+ MVP_LOOPST_TypeDef LOOPST_TGL[8U]; /**< */
+ MVP_ALU_TypeDef ALU_TGL[8U]; /**< */
+ MVP_ARRAY_TypeDef ARRAY_TGL[5U]; /**< */
+ MVP_LOOP_TypeDef LOOP_TGL[8U]; /**< */
+ MVP_INSTR_TypeDef INSTR_TGL[8U]; /**< */
+ __IOM uint32_t CMD_TGL; /**< Command Register */
+ uint32_t RESERVED6[34U]; /**< Reserved for future use */
+ __IOM uint32_t DEBUGEN_TGL; /**< Debug Enable Register */
+ __IOM uint32_t DEBUGSTEPCNT_TGL; /**< Debug Step Register */
+} MVP_TypeDef;
+/** @} End of group EFR32MG24_MVP */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_MVP
+ * @{
+ * @defgroup EFR32MG24_MVP_BitFields MVP Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for MVP IPVERSION */
+#define _MVP_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for MVP_IPVERSION */
+#define _MVP_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for MVP_IPVERSION */
+#define _MVP_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MVP_IPVERSION */
+#define _MVP_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for MVP_IPVERSION */
+#define _MVP_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for MVP_IPVERSION */
+#define MVP_IPVERSION_IPVERSION_DEFAULT (_MVP_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_IPVERSION */
+
+/* Bit fields for MVP EN */
+#define _MVP_EN_RESETVALUE 0x00000000UL /**< Default value for MVP_EN */
+#define _MVP_EN_MASK 0x00000003UL /**< Mask for MVP_EN */
+#define MVP_EN_EN (0x1UL << 0) /**< Enable */
+#define _MVP_EN_EN_SHIFT 0 /**< Shift value for MVP_EN */
+#define _MVP_EN_EN_MASK 0x1UL /**< Bit mask for MVP_EN */
+#define _MVP_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_EN */
+#define MVP_EN_EN_DEFAULT (_MVP_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_EN */
+#define MVP_EN_DISABLING (0x1UL << 1) /**< Disablement Busy Status */
+#define _MVP_EN_DISABLING_SHIFT 1 /**< Shift value for MVP_DISABLING */
+#define _MVP_EN_DISABLING_MASK 0x2UL /**< Bit mask for MVP_DISABLING */
+#define _MVP_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_EN */
+#define MVP_EN_DISABLING_DEFAULT (_MVP_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_EN */
+
+/* Bit fields for MVP SWRST */
+#define _MVP_SWRST_RESETVALUE 0x00000000UL /**< Default value for MVP_SWRST */
+#define _MVP_SWRST_MASK 0x00000003UL /**< Mask for MVP_SWRST */
+#define MVP_SWRST_SWRST (0x1UL << 0) /**< Software Reset Command */
+#define _MVP_SWRST_SWRST_SHIFT 0 /**< Shift value for MVP_SWRST */
+#define _MVP_SWRST_SWRST_MASK 0x1UL /**< Bit mask for MVP_SWRST */
+#define _MVP_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_SWRST */
+#define MVP_SWRST_SWRST_DEFAULT (_MVP_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_SWRST */
+#define MVP_SWRST_RESETTING (0x1UL << 1) /**< Software Reset Busy Status */
+#define _MVP_SWRST_RESETTING_SHIFT 1 /**< Shift value for MVP_RESETTING */
+#define _MVP_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for MVP_RESETTING */
+#define _MVP_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_SWRST */
+#define MVP_SWRST_RESETTING_DEFAULT (_MVP_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_SWRST */
+
+/* Bit fields for MVP CFG */
+#define _MVP_CFG_RESETVALUE 0x00000000UL /**< Default value for MVP_CFG */
+#define _MVP_CFG_MASK 0x00FF000FUL /**< Mask for MVP_CFG */
+#define MVP_CFG_PERFCNTEN (0x1UL << 0) /**< Performance Counter Enable */
+#define _MVP_CFG_PERFCNTEN_SHIFT 0 /**< Shift value for MVP_PERFCNTEN */
+#define _MVP_CFG_PERFCNTEN_MASK 0x1UL /**< Bit mask for MVP_PERFCNTEN */
+#define _MVP_CFG_PERFCNTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */
+#define MVP_CFG_PERFCNTEN_DEFAULT (_MVP_CFG_PERFCNTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_CFG */
+#define MVP_CFG_OUTCOMPRESSDIS (0x1UL << 1) /**< ALU Output Stream Compression Disable */
+#define _MVP_CFG_OUTCOMPRESSDIS_SHIFT 1 /**< Shift value for MVP_OUTCOMPRESSDIS */
+#define _MVP_CFG_OUTCOMPRESSDIS_MASK 0x2UL /**< Bit mask for MVP_OUTCOMPRESSDIS */
+#define _MVP_CFG_OUTCOMPRESSDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */
+#define MVP_CFG_OUTCOMPRESSDIS_DEFAULT (_MVP_CFG_OUTCOMPRESSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_CFG */
+#define MVP_CFG_INCACHEDIS (0x1UL << 2) /**< ALU Input Word Cache Disable */
+#define _MVP_CFG_INCACHEDIS_SHIFT 2 /**< Shift value for MVP_INCACHEDIS */
+#define _MVP_CFG_INCACHEDIS_MASK 0x4UL /**< Bit mask for MVP_INCACHEDIS */
+#define _MVP_CFG_INCACHEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */
+#define MVP_CFG_INCACHEDIS_DEFAULT (_MVP_CFG_INCACHEDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_CFG */
+#define MVP_CFG_LOOPERRHALTDIS (0x1UL << 3) /**< Loop Error Halt Disable */
+#define _MVP_CFG_LOOPERRHALTDIS_SHIFT 3 /**< Shift value for MVP_LOOPERRHALTDIS */
+#define _MVP_CFG_LOOPERRHALTDIS_MASK 0x8UL /**< Bit mask for MVP_LOOPERRHALTDIS */
+#define _MVP_CFG_LOOPERRHALTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */
+#define MVP_CFG_LOOPERRHALTDIS_DEFAULT (_MVP_CFG_LOOPERRHALTDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_CFG */
+#define _MVP_CFG_PERF0CNTSEL_SHIFT 16 /**< Shift value for MVP_PERF0CNTSEL */
+#define _MVP_CFG_PERF0CNTSEL_MASK 0xF0000UL /**< Bit mask for MVP_PERF0CNTSEL */
+#define _MVP_CFG_PERF0CNTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */
+#define _MVP_CFG_PERF0CNTSEL_RUN 0x00000000UL /**< Mode RUN for MVP_CFG */
+#define _MVP_CFG_PERF0CNTSEL_CMD 0x00000001UL /**< Mode CMD for MVP_CFG */
+#define _MVP_CFG_PERF0CNTSEL_STALL 0x00000002UL /**< Mode STALL for MVP_CFG */
+#define _MVP_CFG_PERF0CNTSEL_NOOP 0x00000003UL /**< Mode NOOP for MVP_CFG */
+#define _MVP_CFG_PERF0CNTSEL_ALUACTIVE 0x00000004UL /**< Mode ALUACTIVE for MVP_CFG */
+#define _MVP_CFG_PERF0CNTSEL_PIPESTALL 0x00000005UL /**< Mode PIPESTALL for MVP_CFG */
+#define _MVP_CFG_PERF0CNTSEL_IOFENCESTALL 0x00000006UL /**< Mode IOFENCESTALL for MVP_CFG */
+#define _MVP_CFG_PERF0CNTSEL_LOAD0STALL 0x00000007UL /**< Mode LOAD0STALL for MVP_CFG */
+#define _MVP_CFG_PERF0CNTSEL_LOAD1STALL 0x00000008UL /**< Mode LOAD1STALL for MVP_CFG */
+#define _MVP_CFG_PERF0CNTSEL_STORESTALL 0x00000009UL /**< Mode STORESTALL for MVP_CFG */
+#define _MVP_CFG_PERF0CNTSEL_BUSSTALL 0x0000000AUL /**< Mode BUSSTALL for MVP_CFG */
+#define _MVP_CFG_PERF0CNTSEL_LOAD0AHBSTALL 0x0000000BUL /**< Mode LOAD0AHBSTALL for MVP_CFG */
+#define _MVP_CFG_PERF0CNTSEL_LOAD1AHBSTALL 0x0000000CUL /**< Mode LOAD1AHBSTALL for MVP_CFG */
+#define _MVP_CFG_PERF0CNTSEL_LOAD0FENCESTALL 0x0000000DUL /**< Mode LOAD0FENCESTALL for MVP_CFG */
+#define _MVP_CFG_PERF0CNTSEL_LOAD1FENCESTALL 0x0000000EUL /**< Mode LOAD1FENCESTALL for MVP_CFG */
+#define MVP_CFG_PERF0CNTSEL_DEFAULT (_MVP_CFG_PERF0CNTSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_CFG */
+#define MVP_CFG_PERF0CNTSEL_RUN (_MVP_CFG_PERF0CNTSEL_RUN << 16) /**< Shifted mode RUN for MVP_CFG */
+#define MVP_CFG_PERF0CNTSEL_CMD (_MVP_CFG_PERF0CNTSEL_CMD << 16) /**< Shifted mode CMD for MVP_CFG */
+#define MVP_CFG_PERF0CNTSEL_STALL (_MVP_CFG_PERF0CNTSEL_STALL << 16) /**< Shifted mode STALL for MVP_CFG */
+#define MVP_CFG_PERF0CNTSEL_NOOP (_MVP_CFG_PERF0CNTSEL_NOOP << 16) /**< Shifted mode NOOP for MVP_CFG */
+#define MVP_CFG_PERF0CNTSEL_ALUACTIVE (_MVP_CFG_PERF0CNTSEL_ALUACTIVE << 16) /**< Shifted mode ALUACTIVE for MVP_CFG */
+#define MVP_CFG_PERF0CNTSEL_PIPESTALL (_MVP_CFG_PERF0CNTSEL_PIPESTALL << 16) /**< Shifted mode PIPESTALL for MVP_CFG */
+#define MVP_CFG_PERF0CNTSEL_IOFENCESTALL (_MVP_CFG_PERF0CNTSEL_IOFENCESTALL << 16) /**< Shifted mode IOFENCESTALL for MVP_CFG */
+#define MVP_CFG_PERF0CNTSEL_LOAD0STALL (_MVP_CFG_PERF0CNTSEL_LOAD0STALL << 16) /**< Shifted mode LOAD0STALL for MVP_CFG */
+#define MVP_CFG_PERF0CNTSEL_LOAD1STALL (_MVP_CFG_PERF0CNTSEL_LOAD1STALL << 16) /**< Shifted mode LOAD1STALL for MVP_CFG */
+#define MVP_CFG_PERF0CNTSEL_STORESTALL (_MVP_CFG_PERF0CNTSEL_STORESTALL << 16) /**< Shifted mode STORESTALL for MVP_CFG */
+#define MVP_CFG_PERF0CNTSEL_BUSSTALL (_MVP_CFG_PERF0CNTSEL_BUSSTALL << 16) /**< Shifted mode BUSSTALL for MVP_CFG */
+#define MVP_CFG_PERF0CNTSEL_LOAD0AHBSTALL (_MVP_CFG_PERF0CNTSEL_LOAD0AHBSTALL << 16) /**< Shifted mode LOAD0AHBSTALL for MVP_CFG */
+#define MVP_CFG_PERF0CNTSEL_LOAD1AHBSTALL (_MVP_CFG_PERF0CNTSEL_LOAD1AHBSTALL << 16) /**< Shifted mode LOAD1AHBSTALL for MVP_CFG */
+#define MVP_CFG_PERF0CNTSEL_LOAD0FENCESTALL (_MVP_CFG_PERF0CNTSEL_LOAD0FENCESTALL << 16) /**< Shifted mode LOAD0FENCESTALL for MVP_CFG */
+#define MVP_CFG_PERF0CNTSEL_LOAD1FENCESTALL (_MVP_CFG_PERF0CNTSEL_LOAD1FENCESTALL << 16) /**< Shifted mode LOAD1FENCESTALL for MVP_CFG */
+#define _MVP_CFG_PERF1CNTSEL_SHIFT 20 /**< Shift value for MVP_PERF1CNTSEL */
+#define _MVP_CFG_PERF1CNTSEL_MASK 0xF00000UL /**< Bit mask for MVP_PERF1CNTSEL */
+#define _MVP_CFG_PERF1CNTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */
+#define _MVP_CFG_PERF1CNTSEL_RUN 0x00000000UL /**< Mode RUN for MVP_CFG */
+#define _MVP_CFG_PERF1CNTSEL_CMD 0x00000001UL /**< Mode CMD for MVP_CFG */
+#define _MVP_CFG_PERF1CNTSEL_STALL 0x00000002UL /**< Mode STALL for MVP_CFG */
+#define _MVP_CFG_PERF1CNTSEL_NOOP 0x00000003UL /**< Mode NOOP for MVP_CFG */
+#define _MVP_CFG_PERF1CNTSEL_ALUACTIVE 0x00000004UL /**< Mode ALUACTIVE for MVP_CFG */
+#define _MVP_CFG_PERF1CNTSEL_PIPESTALL 0x00000005UL /**< Mode PIPESTALL for MVP_CFG */
+#define _MVP_CFG_PERF1CNTSEL_IOFENCESTALL 0x00000006UL /**< Mode IOFENCESTALL for MVP_CFG */
+#define _MVP_CFG_PERF1CNTSEL_LOAD0STALL 0x00000007UL /**< Mode LOAD0STALL for MVP_CFG */
+#define _MVP_CFG_PERF1CNTSEL_LOAD1STALL 0x00000008UL /**< Mode LOAD1STALL for MVP_CFG */
+#define _MVP_CFG_PERF1CNTSEL_STORESTALL 0x00000009UL /**< Mode STORESTALL for MVP_CFG */
+#define _MVP_CFG_PERF1CNTSEL_BUSSTALL 0x0000000AUL /**< Mode BUSSTALL for MVP_CFG */
+#define _MVP_CFG_PERF1CNTSEL_LOAD0AHBSTALL 0x0000000BUL /**< Mode LOAD0AHBSTALL for MVP_CFG */
+#define _MVP_CFG_PERF1CNTSEL_LOAD1AHBSTALL 0x0000000CUL /**< Mode LOAD1AHBSTALL for MVP_CFG */
+#define _MVP_CFG_PERF1CNTSEL_LOAD0FENCESTALL 0x0000000DUL /**< Mode LOAD0FENCESTALL for MVP_CFG */
+#define _MVP_CFG_PERF1CNTSEL_LOAD1FENCESTALL 0x0000000EUL /**< Mode LOAD1FENCESTALL for MVP_CFG */
+#define MVP_CFG_PERF1CNTSEL_DEFAULT (_MVP_CFG_PERF1CNTSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_CFG */
+#define MVP_CFG_PERF1CNTSEL_RUN (_MVP_CFG_PERF1CNTSEL_RUN << 20) /**< Shifted mode RUN for MVP_CFG */
+#define MVP_CFG_PERF1CNTSEL_CMD (_MVP_CFG_PERF1CNTSEL_CMD << 20) /**< Shifted mode CMD for MVP_CFG */
+#define MVP_CFG_PERF1CNTSEL_STALL (_MVP_CFG_PERF1CNTSEL_STALL << 20) /**< Shifted mode STALL for MVP_CFG */
+#define MVP_CFG_PERF1CNTSEL_NOOP (_MVP_CFG_PERF1CNTSEL_NOOP << 20) /**< Shifted mode NOOP for MVP_CFG */
+#define MVP_CFG_PERF1CNTSEL_ALUACTIVE (_MVP_CFG_PERF1CNTSEL_ALUACTIVE << 20) /**< Shifted mode ALUACTIVE for MVP_CFG */
+#define MVP_CFG_PERF1CNTSEL_PIPESTALL (_MVP_CFG_PERF1CNTSEL_PIPESTALL << 20) /**< Shifted mode PIPESTALL for MVP_CFG */
+#define MVP_CFG_PERF1CNTSEL_IOFENCESTALL (_MVP_CFG_PERF1CNTSEL_IOFENCESTALL << 20) /**< Shifted mode IOFENCESTALL for MVP_CFG */
+#define MVP_CFG_PERF1CNTSEL_LOAD0STALL (_MVP_CFG_PERF1CNTSEL_LOAD0STALL << 20) /**< Shifted mode LOAD0STALL for MVP_CFG */
+#define MVP_CFG_PERF1CNTSEL_LOAD1STALL (_MVP_CFG_PERF1CNTSEL_LOAD1STALL << 20) /**< Shifted mode LOAD1STALL for MVP_CFG */
+#define MVP_CFG_PERF1CNTSEL_STORESTALL (_MVP_CFG_PERF1CNTSEL_STORESTALL << 20) /**< Shifted mode STORESTALL for MVP_CFG */
+#define MVP_CFG_PERF1CNTSEL_BUSSTALL (_MVP_CFG_PERF1CNTSEL_BUSSTALL << 20) /**< Shifted mode BUSSTALL for MVP_CFG */
+#define MVP_CFG_PERF1CNTSEL_LOAD0AHBSTALL (_MVP_CFG_PERF1CNTSEL_LOAD0AHBSTALL << 20) /**< Shifted mode LOAD0AHBSTALL for MVP_CFG */
+#define MVP_CFG_PERF1CNTSEL_LOAD1AHBSTALL (_MVP_CFG_PERF1CNTSEL_LOAD1AHBSTALL << 20) /**< Shifted mode LOAD1AHBSTALL for MVP_CFG */
+#define MVP_CFG_PERF1CNTSEL_LOAD0FENCESTALL (_MVP_CFG_PERF1CNTSEL_LOAD0FENCESTALL << 20) /**< Shifted mode LOAD0FENCESTALL for MVP_CFG */
+#define MVP_CFG_PERF1CNTSEL_LOAD1FENCESTALL (_MVP_CFG_PERF1CNTSEL_LOAD1FENCESTALL << 20) /**< Shifted mode LOAD1FENCESTALL for MVP_CFG */
+
+/* Bit fields for MVP STATUS */
+#define _MVP_STATUS_RESETVALUE 0x00000004UL /**< Default value for MVP_STATUS */
+#define _MVP_STATUS_MASK 0x00000007UL /**< Mask for MVP_STATUS */
+#define MVP_STATUS_RUNNING (0x1UL << 0) /**< Running Status */
+#define _MVP_STATUS_RUNNING_SHIFT 0 /**< Shift value for MVP_RUNNING */
+#define _MVP_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for MVP_RUNNING */
+#define _MVP_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_STATUS */
+#define MVP_STATUS_RUNNING_DEFAULT (_MVP_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_STATUS */
+#define MVP_STATUS_PAUSED (0x1UL << 1) /**< Paused Status */
+#define _MVP_STATUS_PAUSED_SHIFT 1 /**< Shift value for MVP_PAUSED */
+#define _MVP_STATUS_PAUSED_MASK 0x2UL /**< Bit mask for MVP_PAUSED */
+#define _MVP_STATUS_PAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_STATUS */
+#define MVP_STATUS_PAUSED_DEFAULT (_MVP_STATUS_PAUSED_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_STATUS */
+#define MVP_STATUS_IDLE (0x1UL << 2) /**< Idle Status */
+#define _MVP_STATUS_IDLE_SHIFT 2 /**< Shift value for MVP_IDLE */
+#define _MVP_STATUS_IDLE_MASK 0x4UL /**< Bit mask for MVP_IDLE */
+#define _MVP_STATUS_IDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MVP_STATUS */
+#define MVP_STATUS_IDLE_DEFAULT (_MVP_STATUS_IDLE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_STATUS */
+
+/* Bit fields for MVP PERFCNT */
+#define _MVP_PERFCNT_RESETVALUE 0x00000000UL /**< Default value for MVP_PERFCNT */
+#define _MVP_PERFCNT_MASK 0x00FFFFFFUL /**< Mask for MVP_PERFCNT */
+#define _MVP_PERFCNT_COUNT_SHIFT 0 /**< Shift value for MVP_COUNT */
+#define _MVP_PERFCNT_COUNT_MASK 0xFFFFFFUL /**< Bit mask for MVP_COUNT */
+#define _MVP_PERFCNT_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_PERFCNT */
+#define MVP_PERFCNT_COUNT_DEFAULT (_MVP_PERFCNT_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_PERFCNT */
+
+/* Bit fields for MVP IF */
+#define _MVP_IF_RESETVALUE 0x00000000UL /**< Default value for MVP_IF */
+#define _MVP_IF_MASK 0x1F0FFDFFUL /**< Mask for MVP_IF */
+#define MVP_IF_PROGDONE (0x1UL << 0) /**< Program Done Interrupt Flags */
+#define _MVP_IF_PROGDONE_SHIFT 0 /**< Shift value for MVP_PROGDONE */
+#define _MVP_IF_PROGDONE_MASK 0x1UL /**< Bit mask for MVP_PROGDONE */
+#define _MVP_IF_PROGDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
+#define MVP_IF_PROGDONE_DEFAULT (_MVP_IF_PROGDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_IF */
+#define MVP_IF_LOOP0DONE (0x1UL << 1) /**< Loop Done Interrupt Flag */
+#define _MVP_IF_LOOP0DONE_SHIFT 1 /**< Shift value for MVP_LOOP0DONE */
+#define _MVP_IF_LOOP0DONE_MASK 0x2UL /**< Bit mask for MVP_LOOP0DONE */
+#define _MVP_IF_LOOP0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
+#define MVP_IF_LOOP0DONE_DEFAULT (_MVP_IF_LOOP0DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_IF */
+#define MVP_IF_LOOP1DONE (0x1UL << 2) /**< Loop Done Interrupt Flag */
+#define _MVP_IF_LOOP1DONE_SHIFT 2 /**< Shift value for MVP_LOOP1DONE */
+#define _MVP_IF_LOOP1DONE_MASK 0x4UL /**< Bit mask for MVP_LOOP1DONE */
+#define _MVP_IF_LOOP1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
+#define MVP_IF_LOOP1DONE_DEFAULT (_MVP_IF_LOOP1DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_IF */
+#define MVP_IF_LOOP2DONE (0x1UL << 3) /**< Loop Done Interrupt Flag */
+#define _MVP_IF_LOOP2DONE_SHIFT 3 /**< Shift value for MVP_LOOP2DONE */
+#define _MVP_IF_LOOP2DONE_MASK 0x8UL /**< Bit mask for MVP_LOOP2DONE */
+#define _MVP_IF_LOOP2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
+#define MVP_IF_LOOP2DONE_DEFAULT (_MVP_IF_LOOP2DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_IF */
+#define MVP_IF_LOOP3DONE (0x1UL << 4) /**< Loop Done Interrupt Flag */
+#define _MVP_IF_LOOP3DONE_SHIFT 4 /**< Shift value for MVP_LOOP3DONE */
+#define _MVP_IF_LOOP3DONE_MASK 0x10UL /**< Bit mask for MVP_LOOP3DONE */
+#define _MVP_IF_LOOP3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
+#define MVP_IF_LOOP3DONE_DEFAULT (_MVP_IF_LOOP3DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_IF */
+#define MVP_IF_LOOP4DONE (0x1UL << 5) /**< Loop Done Interrupt Flag */
+#define _MVP_IF_LOOP4DONE_SHIFT 5 /**< Shift value for MVP_LOOP4DONE */
+#define _MVP_IF_LOOP4DONE_MASK 0x20UL /**< Bit mask for MVP_LOOP4DONE */
+#define _MVP_IF_LOOP4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
+#define MVP_IF_LOOP4DONE_DEFAULT (_MVP_IF_LOOP4DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_IF */
+#define MVP_IF_LOOP5DONE (0x1UL << 6) /**< Loop Done Interrupt Flag */
+#define _MVP_IF_LOOP5DONE_SHIFT 6 /**< Shift value for MVP_LOOP5DONE */
+#define _MVP_IF_LOOP5DONE_MASK 0x40UL /**< Bit mask for MVP_LOOP5DONE */
+#define _MVP_IF_LOOP5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
+#define MVP_IF_LOOP5DONE_DEFAULT (_MVP_IF_LOOP5DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_IF */
+#define MVP_IF_LOOP6DONE (0x1UL << 7) /**< Loop Done Interrupt Flag */
+#define _MVP_IF_LOOP6DONE_SHIFT 7 /**< Shift value for MVP_LOOP6DONE */
+#define _MVP_IF_LOOP6DONE_MASK 0x80UL /**< Bit mask for MVP_LOOP6DONE */
+#define _MVP_IF_LOOP6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
+#define MVP_IF_LOOP6DONE_DEFAULT (_MVP_IF_LOOP6DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_IF */
+#define MVP_IF_LOOP7DONE (0x1UL << 8) /**< Loop Done Interrupt Flag */
+#define _MVP_IF_LOOP7DONE_SHIFT 8 /**< Shift value for MVP_LOOP7DONE */
+#define _MVP_IF_LOOP7DONE_MASK 0x100UL /**< Bit mask for MVP_LOOP7DONE */
+#define _MVP_IF_LOOP7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
+#define MVP_IF_LOOP7DONE_DEFAULT (_MVP_IF_LOOP7DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_IF */
+#define MVP_IF_ALUNAN (0x1UL << 10) /**< Not-a-Number Interrupt Flag */
+#define _MVP_IF_ALUNAN_SHIFT 10 /**< Shift value for MVP_ALUNAN */
+#define _MVP_IF_ALUNAN_MASK 0x400UL /**< Bit mask for MVP_ALUNAN */
+#define _MVP_IF_ALUNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
+#define MVP_IF_ALUNAN_DEFAULT (_MVP_IF_ALUNAN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_IF */
+#define MVP_IF_R0POSREAL (0x1UL << 11) /**< R0 non-zero Interrupt Flag */
+#define _MVP_IF_R0POSREAL_SHIFT 11 /**< Shift value for MVP_R0POSREAL */
+#define _MVP_IF_R0POSREAL_MASK 0x800UL /**< Bit mask for MVP_R0POSREAL */
+#define _MVP_IF_R0POSREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
+#define MVP_IF_R0POSREAL_DEFAULT (_MVP_IF_R0POSREAL_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_IF */
+#define MVP_IF_ALUOF (0x1UL << 12) /**< ALU Overflow on result */
+#define _MVP_IF_ALUOF_SHIFT 12 /**< Shift value for MVP_ALUOF */
+#define _MVP_IF_ALUOF_MASK 0x1000UL /**< Bit mask for MVP_ALUOF */
+#define _MVP_IF_ALUOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
+#define MVP_IF_ALUOF_DEFAULT (_MVP_IF_ALUOF_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_IF */
+#define MVP_IF_ALUUF (0x1UL << 13) /**< ALU Underflow on result */
+#define _MVP_IF_ALUUF_SHIFT 13 /**< Shift value for MVP_ALUUF */
+#define _MVP_IF_ALUUF_MASK 0x2000UL /**< Bit mask for MVP_ALUUF */
+#define _MVP_IF_ALUUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
+#define MVP_IF_ALUUF_DEFAULT (_MVP_IF_ALUUF_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_IF */
+#define MVP_IF_STORECONVERTOF (0x1UL << 14) /**< Overflow during array store */
+#define _MVP_IF_STORECONVERTOF_SHIFT 14 /**< Shift value for MVP_STORECONVERTOF */
+#define _MVP_IF_STORECONVERTOF_MASK 0x4000UL /**< Bit mask for MVP_STORECONVERTOF */
+#define _MVP_IF_STORECONVERTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
+#define MVP_IF_STORECONVERTOF_DEFAULT (_MVP_IF_STORECONVERTOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_IF */
+#define MVP_IF_STORECONVERTUF (0x1UL << 15) /**< Underflow during array store conversion */
+#define _MVP_IF_STORECONVERTUF_SHIFT 15 /**< Shift value for MVP_STORECONVERTUF */
+#define _MVP_IF_STORECONVERTUF_MASK 0x8000UL /**< Bit mask for MVP_STORECONVERTUF */
+#define _MVP_IF_STORECONVERTUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
+#define MVP_IF_STORECONVERTUF_DEFAULT (_MVP_IF_STORECONVERTUF_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_IF */
+#define MVP_IF_STORECONVERTINF (0x1UL << 16) /**< Infinity encountered during array store conversion*/
+#define _MVP_IF_STORECONVERTINF_SHIFT 16 /**< Shift value for MVP_STORECONVERTINF */
+#define _MVP_IF_STORECONVERTINF_MASK 0x10000UL /**< Bit mask for MVP_STORECONVERTINF */
+#define _MVP_IF_STORECONVERTINF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
+#define MVP_IF_STORECONVERTINF_DEFAULT (_MVP_IF_STORECONVERTINF_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_IF */
+#define MVP_IF_STORECONVERTNAN (0x1UL << 17) /**< NaN encountered during array store conversion*/
+#define _MVP_IF_STORECONVERTNAN_SHIFT 17 /**< Shift value for MVP_STORECONVERTNAN */
+#define _MVP_IF_STORECONVERTNAN_MASK 0x20000UL /**< Bit mask for MVP_STORECONVERTNAN */
+#define _MVP_IF_STORECONVERTNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
+#define MVP_IF_STORECONVERTNAN_DEFAULT (_MVP_IF_STORECONVERTNAN_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_IF */
+#define MVP_IF_PERFCNT0 (0x1UL << 18) /**< Run Count Overflow Interrupt Flag */
+#define _MVP_IF_PERFCNT0_SHIFT 18 /**< Shift value for MVP_PERFCNT0 */
+#define _MVP_IF_PERFCNT0_MASK 0x40000UL /**< Bit mask for MVP_PERFCNT0 */
+#define _MVP_IF_PERFCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
+#define MVP_IF_PERFCNT0_DEFAULT (_MVP_IF_PERFCNT0_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_IF */
+#define MVP_IF_PERFCNT1 (0x1UL << 19) /**< Stall Count Overflow Interrupt Flag */
+#define _MVP_IF_PERFCNT1_SHIFT 19 /**< Shift value for MVP_PERFCNT1 */
+#define _MVP_IF_PERFCNT1_MASK 0x80000UL /**< Bit mask for MVP_PERFCNT1 */
+#define _MVP_IF_PERFCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
+#define MVP_IF_PERFCNT1_DEFAULT (_MVP_IF_PERFCNT1_DEFAULT << 19) /**< Shifted mode DEFAULT for MVP_IF */
+#define MVP_IF_LOOPFAULT (0x1UL << 24) /**< Loop Fault Interrupt Flag */
+#define _MVP_IF_LOOPFAULT_SHIFT 24 /**< Shift value for MVP_LOOPFAULT */
+#define _MVP_IF_LOOPFAULT_MASK 0x1000000UL /**< Bit mask for MVP_LOOPFAULT */
+#define _MVP_IF_LOOPFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
+#define MVP_IF_LOOPFAULT_DEFAULT (_MVP_IF_LOOPFAULT_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_IF */
+#define MVP_IF_BUSERRFAULT (0x1UL << 25) /**< Bus Error Fault Interrupt Flag */
+#define _MVP_IF_BUSERRFAULT_SHIFT 25 /**< Shift value for MVP_BUSERRFAULT */
+#define _MVP_IF_BUSERRFAULT_MASK 0x2000000UL /**< Bit mask for MVP_BUSERRFAULT */
+#define _MVP_IF_BUSERRFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
+#define MVP_IF_BUSERRFAULT_DEFAULT (_MVP_IF_BUSERRFAULT_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_IF */
+#define MVP_IF_BUSALIGNFAULT (0x1UL << 26) /**< Bus Alignment Fault Interrupt Flag */
+#define _MVP_IF_BUSALIGNFAULT_SHIFT 26 /**< Shift value for MVP_BUSALIGNFAULT */
+#define _MVP_IF_BUSALIGNFAULT_MASK 0x4000000UL /**< Bit mask for MVP_BUSALIGNFAULT */
+#define _MVP_IF_BUSALIGNFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
+#define MVP_IF_BUSALIGNFAULT_DEFAULT (_MVP_IF_BUSALIGNFAULT_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_IF */
+#define MVP_IF_ALUFAULT (0x1UL << 27) /**< ALU Fault Interrupt Flag */
+#define _MVP_IF_ALUFAULT_SHIFT 27 /**< Shift value for MVP_ALUFAULT */
+#define _MVP_IF_ALUFAULT_MASK 0x8000000UL /**< Bit mask for MVP_ALUFAULT */
+#define _MVP_IF_ALUFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
+#define MVP_IF_ALUFAULT_DEFAULT (_MVP_IF_ALUFAULT_DEFAULT << 27) /**< Shifted mode DEFAULT for MVP_IF */
+#define MVP_IF_ARRAYFAULT (0x1UL << 28) /**< Array Fault Interrupt Flag */
+#define _MVP_IF_ARRAYFAULT_SHIFT 28 /**< Shift value for MVP_ARRAYFAULT */
+#define _MVP_IF_ARRAYFAULT_MASK 0x10000000UL /**< Bit mask for MVP_ARRAYFAULT */
+#define _MVP_IF_ARRAYFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */
+#define MVP_IF_ARRAYFAULT_DEFAULT (_MVP_IF_ARRAYFAULT_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_IF */
+
+/* Bit fields for MVP IEN */
+#define _MVP_IEN_RESETVALUE 0x00000000UL /**< Default value for MVP_IEN */
+#define _MVP_IEN_MASK 0x1F0FFDFFUL /**< Mask for MVP_IEN */
+#define MVP_IEN_PROGDONE (0x1UL << 0) /**< Program Done Interrupt Enable */
+#define _MVP_IEN_PROGDONE_SHIFT 0 /**< Shift value for MVP_PROGDONE */
+#define _MVP_IEN_PROGDONE_MASK 0x1UL /**< Bit mask for MVP_PROGDONE */
+#define _MVP_IEN_PROGDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
+#define MVP_IEN_PROGDONE_DEFAULT (_MVP_IEN_PROGDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_IEN */
+#define MVP_IEN_LOOP0DONE (0x1UL << 1) /**< Loop Done Interrupt Enable */
+#define _MVP_IEN_LOOP0DONE_SHIFT 1 /**< Shift value for MVP_LOOP0DONE */
+#define _MVP_IEN_LOOP0DONE_MASK 0x2UL /**< Bit mask for MVP_LOOP0DONE */
+#define _MVP_IEN_LOOP0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
+#define MVP_IEN_LOOP0DONE_DEFAULT (_MVP_IEN_LOOP0DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_IEN */
+#define MVP_IEN_LOOP1DONE (0x1UL << 2) /**< Loop Done Interrupt Enable */
+#define _MVP_IEN_LOOP1DONE_SHIFT 2 /**< Shift value for MVP_LOOP1DONE */
+#define _MVP_IEN_LOOP1DONE_MASK 0x4UL /**< Bit mask for MVP_LOOP1DONE */
+#define _MVP_IEN_LOOP1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
+#define MVP_IEN_LOOP1DONE_DEFAULT (_MVP_IEN_LOOP1DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_IEN */
+#define MVP_IEN_LOOP2DONE (0x1UL << 3) /**< Loop Done Interrupt Enable */
+#define _MVP_IEN_LOOP2DONE_SHIFT 3 /**< Shift value for MVP_LOOP2DONE */
+#define _MVP_IEN_LOOP2DONE_MASK 0x8UL /**< Bit mask for MVP_LOOP2DONE */
+#define _MVP_IEN_LOOP2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
+#define MVP_IEN_LOOP2DONE_DEFAULT (_MVP_IEN_LOOP2DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_IEN */
+#define MVP_IEN_LOOP3DONE (0x1UL << 4) /**< Loop Done Interrupt Enable */
+#define _MVP_IEN_LOOP3DONE_SHIFT 4 /**< Shift value for MVP_LOOP3DONE */
+#define _MVP_IEN_LOOP3DONE_MASK 0x10UL /**< Bit mask for MVP_LOOP3DONE */
+#define _MVP_IEN_LOOP3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
+#define MVP_IEN_LOOP3DONE_DEFAULT (_MVP_IEN_LOOP3DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_IEN */
+#define MVP_IEN_LOOP4DONE (0x1UL << 5) /**< Loop Done Interrupt Enable */
+#define _MVP_IEN_LOOP4DONE_SHIFT 5 /**< Shift value for MVP_LOOP4DONE */
+#define _MVP_IEN_LOOP4DONE_MASK 0x20UL /**< Bit mask for MVP_LOOP4DONE */
+#define _MVP_IEN_LOOP4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
+#define MVP_IEN_LOOP4DONE_DEFAULT (_MVP_IEN_LOOP4DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_IEN */
+#define MVP_IEN_LOOP5DONE (0x1UL << 6) /**< Loop Done Interrupt Enable */
+#define _MVP_IEN_LOOP5DONE_SHIFT 6 /**< Shift value for MVP_LOOP5DONE */
+#define _MVP_IEN_LOOP5DONE_MASK 0x40UL /**< Bit mask for MVP_LOOP5DONE */
+#define _MVP_IEN_LOOP5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
+#define MVP_IEN_LOOP5DONE_DEFAULT (_MVP_IEN_LOOP5DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_IEN */
+#define MVP_IEN_LOOP6DONE (0x1UL << 7) /**< Loop Done Interrupt Enable */
+#define _MVP_IEN_LOOP6DONE_SHIFT 7 /**< Shift value for MVP_LOOP6DONE */
+#define _MVP_IEN_LOOP6DONE_MASK 0x80UL /**< Bit mask for MVP_LOOP6DONE */
+#define _MVP_IEN_LOOP6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
+#define MVP_IEN_LOOP6DONE_DEFAULT (_MVP_IEN_LOOP6DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_IEN */
+#define MVP_IEN_LOOP7DONE (0x1UL << 8) /**< Loop Done Interrupt Enable */
+#define _MVP_IEN_LOOP7DONE_SHIFT 8 /**< Shift value for MVP_LOOP7DONE */
+#define _MVP_IEN_LOOP7DONE_MASK 0x100UL /**< Bit mask for MVP_LOOP7DONE */
+#define _MVP_IEN_LOOP7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
+#define MVP_IEN_LOOP7DONE_DEFAULT (_MVP_IEN_LOOP7DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_IEN */
+#define MVP_IEN_ALUNAN (0x1UL << 10) /**< Not-a-Number Interrupt Enable */
+#define _MVP_IEN_ALUNAN_SHIFT 10 /**< Shift value for MVP_ALUNAN */
+#define _MVP_IEN_ALUNAN_MASK 0x400UL /**< Bit mask for MVP_ALUNAN */
+#define _MVP_IEN_ALUNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
+#define MVP_IEN_ALUNAN_DEFAULT (_MVP_IEN_ALUNAN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_IEN */
+#define MVP_IEN_R0POSREAL (0x1UL << 11) /**< R0 Non-Zero Interrupt Enable */
+#define _MVP_IEN_R0POSREAL_SHIFT 11 /**< Shift value for MVP_R0POSREAL */
+#define _MVP_IEN_R0POSREAL_MASK 0x800UL /**< Bit mask for MVP_R0POSREAL */
+#define _MVP_IEN_R0POSREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
+#define MVP_IEN_R0POSREAL_DEFAULT (_MVP_IEN_R0POSREAL_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_IEN */
+#define MVP_IEN_ALUOF (0x1UL << 12) /**< ALU Overflow Interrupt Enable */
+#define _MVP_IEN_ALUOF_SHIFT 12 /**< Shift value for MVP_ALUOF */
+#define _MVP_IEN_ALUOF_MASK 0x1000UL /**< Bit mask for MVP_ALUOF */
+#define _MVP_IEN_ALUOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
+#define MVP_IEN_ALUOF_DEFAULT (_MVP_IEN_ALUOF_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_IEN */
+#define MVP_IEN_ALUUF (0x1UL << 13) /**< ALU Underflow Interrupt Enable */
+#define _MVP_IEN_ALUUF_SHIFT 13 /**< Shift value for MVP_ALUUF */
+#define _MVP_IEN_ALUUF_MASK 0x2000UL /**< Bit mask for MVP_ALUUF */
+#define _MVP_IEN_ALUUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
+#define MVP_IEN_ALUUF_DEFAULT (_MVP_IEN_ALUUF_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_IEN */
+#define MVP_IEN_STORECONVERTOF (0x1UL << 14) /**< Store conversion Overflow Interrupt Enable */
+#define _MVP_IEN_STORECONVERTOF_SHIFT 14 /**< Shift value for MVP_STORECONVERTOF */
+#define _MVP_IEN_STORECONVERTOF_MASK 0x4000UL /**< Bit mask for MVP_STORECONVERTOF */
+#define _MVP_IEN_STORECONVERTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
+#define MVP_IEN_STORECONVERTOF_DEFAULT (_MVP_IEN_STORECONVERTOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_IEN */
+#define MVP_IEN_STORECONVERTUF (0x1UL << 15) /**< Store Conversion Underflow Interrupt Enable */
+#define _MVP_IEN_STORECONVERTUF_SHIFT 15 /**< Shift value for MVP_STORECONVERTUF */
+#define _MVP_IEN_STORECONVERTUF_MASK 0x8000UL /**< Bit mask for MVP_STORECONVERTUF */
+#define _MVP_IEN_STORECONVERTUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
+#define MVP_IEN_STORECONVERTUF_DEFAULT (_MVP_IEN_STORECONVERTUF_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_IEN */
+#define MVP_IEN_STORECONVERTINF (0x1UL << 16) /**< Store Conversion Infinity Interrupt Enable */
+#define _MVP_IEN_STORECONVERTINF_SHIFT 16 /**< Shift value for MVP_STORECONVERTINF */
+#define _MVP_IEN_STORECONVERTINF_MASK 0x10000UL /**< Bit mask for MVP_STORECONVERTINF */
+#define _MVP_IEN_STORECONVERTINF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
+#define MVP_IEN_STORECONVERTINF_DEFAULT (_MVP_IEN_STORECONVERTINF_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_IEN */
+#define MVP_IEN_STORECONVERTNAN (0x1UL << 17) /**< Store Conversion NaN Interrupt Enable */
+#define _MVP_IEN_STORECONVERTNAN_SHIFT 17 /**< Shift value for MVP_STORECONVERTNAN */
+#define _MVP_IEN_STORECONVERTNAN_MASK 0x20000UL /**< Bit mask for MVP_STORECONVERTNAN */
+#define _MVP_IEN_STORECONVERTNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
+#define MVP_IEN_STORECONVERTNAN_DEFAULT (_MVP_IEN_STORECONVERTNAN_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_IEN */
+#define MVP_IEN_PERFCNT0 (0x1UL << 18) /**< Perf Counter 0 Overflow Interrupt Enable */
+#define _MVP_IEN_PERFCNT0_SHIFT 18 /**< Shift value for MVP_PERFCNT0 */
+#define _MVP_IEN_PERFCNT0_MASK 0x40000UL /**< Bit mask for MVP_PERFCNT0 */
+#define _MVP_IEN_PERFCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
+#define MVP_IEN_PERFCNT0_DEFAULT (_MVP_IEN_PERFCNT0_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_IEN */
+#define MVP_IEN_PERFCNT1 (0x1UL << 19) /**< Perf Counter 1 Overflow Interrupt Enable */
+#define _MVP_IEN_PERFCNT1_SHIFT 19 /**< Shift value for MVP_PERFCNT1 */
+#define _MVP_IEN_PERFCNT1_MASK 0x80000UL /**< Bit mask for MVP_PERFCNT1 */
+#define _MVP_IEN_PERFCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
+#define MVP_IEN_PERFCNT1_DEFAULT (_MVP_IEN_PERFCNT1_DEFAULT << 19) /**< Shifted mode DEFAULT for MVP_IEN */
+#define MVP_IEN_LOOPFAULT (0x1UL << 24) /**< Loop Fault Interrupt Enable */
+#define _MVP_IEN_LOOPFAULT_SHIFT 24 /**< Shift value for MVP_LOOPFAULT */
+#define _MVP_IEN_LOOPFAULT_MASK 0x1000000UL /**< Bit mask for MVP_LOOPFAULT */
+#define _MVP_IEN_LOOPFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
+#define MVP_IEN_LOOPFAULT_DEFAULT (_MVP_IEN_LOOPFAULT_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_IEN */
+#define MVP_IEN_BUSERRFAULT (0x1UL << 25) /**< Bus Error Fault Interrupt Enable */
+#define _MVP_IEN_BUSERRFAULT_SHIFT 25 /**< Shift value for MVP_BUSERRFAULT */
+#define _MVP_IEN_BUSERRFAULT_MASK 0x2000000UL /**< Bit mask for MVP_BUSERRFAULT */
+#define _MVP_IEN_BUSERRFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
+#define MVP_IEN_BUSERRFAULT_DEFAULT (_MVP_IEN_BUSERRFAULT_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_IEN */
+#define MVP_IEN_BUSALIGNFAULT (0x1UL << 26) /**< Bus Alignment Fault Interrupt Enable */
+#define _MVP_IEN_BUSALIGNFAULT_SHIFT 26 /**< Shift value for MVP_BUSALIGNFAULT */
+#define _MVP_IEN_BUSALIGNFAULT_MASK 0x4000000UL /**< Bit mask for MVP_BUSALIGNFAULT */
+#define _MVP_IEN_BUSALIGNFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
+#define MVP_IEN_BUSALIGNFAULT_DEFAULT (_MVP_IEN_BUSALIGNFAULT_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_IEN */
+#define MVP_IEN_ALUFAULT (0x1UL << 27) /**< ALU Input Fault Interrupt Enable */
+#define _MVP_IEN_ALUFAULT_SHIFT 27 /**< Shift value for MVP_ALUFAULT */
+#define _MVP_IEN_ALUFAULT_MASK 0x8000000UL /**< Bit mask for MVP_ALUFAULT */
+#define _MVP_IEN_ALUFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
+#define MVP_IEN_ALUFAULT_DEFAULT (_MVP_IEN_ALUFAULT_DEFAULT << 27) /**< Shifted mode DEFAULT for MVP_IEN */
+#define MVP_IEN_ARRAYFAULT (0x1UL << 28) /**< Array Fault Interrupt Enable */
+#define _MVP_IEN_ARRAYFAULT_SHIFT 28 /**< Shift value for MVP_ARRAYFAULT */
+#define _MVP_IEN_ARRAYFAULT_MASK 0x10000000UL /**< Bit mask for MVP_ARRAYFAULT */
+#define _MVP_IEN_ARRAYFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */
+#define MVP_IEN_ARRAYFAULT_DEFAULT (_MVP_IEN_ARRAYFAULT_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_IEN */
+
+/* Bit fields for MVP FAULTSTATUS */
+#define _MVP_FAULTSTATUS_RESETVALUE 0x00000000UL /**< Default value for MVP_FAULTSTATUS */
+#define _MVP_FAULTSTATUS_MASK 0x000F3707UL /**< Mask for MVP_FAULTSTATUS */
+#define _MVP_FAULTSTATUS_FAULTPC_SHIFT 0 /**< Shift value for MVP_FAULTPC */
+#define _MVP_FAULTSTATUS_FAULTPC_MASK 0x7UL /**< Bit mask for MVP_FAULTPC */
+#define _MVP_FAULTSTATUS_FAULTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */
+#define MVP_FAULTSTATUS_FAULTPC_DEFAULT (_MVP_FAULTSTATUS_FAULTPC_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */
+#define _MVP_FAULTSTATUS_FAULTARRAY_SHIFT 8 /**< Shift value for MVP_FAULTARRAY */
+#define _MVP_FAULTSTATUS_FAULTARRAY_MASK 0x700UL /**< Bit mask for MVP_FAULTARRAY */
+#define _MVP_FAULTSTATUS_FAULTARRAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */
+#define MVP_FAULTSTATUS_FAULTARRAY_DEFAULT (_MVP_FAULTSTATUS_FAULTARRAY_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */
+#define _MVP_FAULTSTATUS_FAULTBUS_SHIFT 12 /**< Shift value for MVP_FAULTBUS */
+#define _MVP_FAULTSTATUS_FAULTBUS_MASK 0x3000UL /**< Bit mask for MVP_FAULTBUS */
+#define _MVP_FAULTSTATUS_FAULTBUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */
+#define _MVP_FAULTSTATUS_FAULTBUS_NONE 0x00000000UL /**< Mode NONE for MVP_FAULTSTATUS */
+#define _MVP_FAULTSTATUS_FAULTBUS_LOAD0STREAM 0x00000001UL /**< Mode LOAD0STREAM for MVP_FAULTSTATUS */
+#define _MVP_FAULTSTATUS_FAULTBUS_LOAD1STREAM 0x00000002UL /**< Mode LOAD1STREAM for MVP_FAULTSTATUS */
+#define _MVP_FAULTSTATUS_FAULTBUS_STORESTREAM 0x00000003UL /**< Mode STORESTREAM for MVP_FAULTSTATUS */
+#define MVP_FAULTSTATUS_FAULTBUS_DEFAULT (_MVP_FAULTSTATUS_FAULTBUS_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */
+#define MVP_FAULTSTATUS_FAULTBUS_NONE (_MVP_FAULTSTATUS_FAULTBUS_NONE << 12) /**< Shifted mode NONE for MVP_FAULTSTATUS */
+#define MVP_FAULTSTATUS_FAULTBUS_LOAD0STREAM (_MVP_FAULTSTATUS_FAULTBUS_LOAD0STREAM << 12) /**< Shifted mode LOAD0STREAM for MVP_FAULTSTATUS*/
+#define MVP_FAULTSTATUS_FAULTBUS_LOAD1STREAM (_MVP_FAULTSTATUS_FAULTBUS_LOAD1STREAM << 12) /**< Shifted mode LOAD1STREAM for MVP_FAULTSTATUS*/
+#define MVP_FAULTSTATUS_FAULTBUS_STORESTREAM (_MVP_FAULTSTATUS_FAULTBUS_STORESTREAM << 12) /**< Shifted mode STORESTREAM for MVP_FAULTSTATUS*/
+#define _MVP_FAULTSTATUS_FAULTLOOP_SHIFT 16 /**< Shift value for MVP_FAULTLOOP */
+#define _MVP_FAULTSTATUS_FAULTLOOP_MASK 0xF0000UL /**< Bit mask for MVP_FAULTLOOP */
+#define _MVP_FAULTSTATUS_FAULTLOOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */
+#define MVP_FAULTSTATUS_FAULTLOOP_DEFAULT (_MVP_FAULTSTATUS_FAULTLOOP_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */
+
+/* Bit fields for MVP FAULTADDR */
+#define _MVP_FAULTADDR_RESETVALUE 0x00000000UL /**< Default value for MVP_FAULTADDR */
+#define _MVP_FAULTADDR_MASK 0xFFFFFFFFUL /**< Mask for MVP_FAULTADDR */
+#define _MVP_FAULTADDR_FAULTADDR_SHIFT 0 /**< Shift value for MVP_FAULTADDR */
+#define _MVP_FAULTADDR_FAULTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MVP_FAULTADDR */
+#define _MVP_FAULTADDR_FAULTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTADDR */
+#define MVP_FAULTADDR_FAULTADDR_DEFAULT (_MVP_FAULTADDR_FAULTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_FAULTADDR */
+
+/* Bit fields for MVP PROGRAMSTATE */
+#define _MVP_PROGRAMSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_PROGRAMSTATE */
+#define _MVP_PROGRAMSTATE_MASK 0x00000007UL /**< Mask for MVP_PROGRAMSTATE */
+#define _MVP_PROGRAMSTATE_PC_SHIFT 0 /**< Shift value for MVP_PC */
+#define _MVP_PROGRAMSTATE_PC_MASK 0x7UL /**< Bit mask for MVP_PC */
+#define _MVP_PROGRAMSTATE_PC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_PROGRAMSTATE */
+#define MVP_PROGRAMSTATE_PC_DEFAULT (_MVP_PROGRAMSTATE_PC_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_PROGRAMSTATE */
+
+/* Bit fields for MVP ARRAYINDEXSTATE */
+#define _MVP_ARRAYINDEXSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYINDEXSTATE */
+#define _MVP_ARRAYINDEXSTATE_MASK 0x3FFFFFFFUL /**< Mask for MVP_ARRAYINDEXSTATE */
+#define _MVP_ARRAYINDEXSTATE_DIM0INDEX_SHIFT 0 /**< Shift value for MVP_DIM0INDEX */
+#define _MVP_ARRAYINDEXSTATE_DIM0INDEX_MASK 0x3FFUL /**< Bit mask for MVP_DIM0INDEX */
+#define _MVP_ARRAYINDEXSTATE_DIM0INDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYINDEXSTATE */
+#define MVP_ARRAYINDEXSTATE_DIM0INDEX_DEFAULT (_MVP_ARRAYINDEXSTATE_DIM0INDEX_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYINDEXSTATE*/
+#define _MVP_ARRAYINDEXSTATE_DIM1INDEX_SHIFT 10 /**< Shift value for MVP_DIM1INDEX */
+#define _MVP_ARRAYINDEXSTATE_DIM1INDEX_MASK 0xFFC00UL /**< Bit mask for MVP_DIM1INDEX */
+#define _MVP_ARRAYINDEXSTATE_DIM1INDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYINDEXSTATE */
+#define MVP_ARRAYINDEXSTATE_DIM1INDEX_DEFAULT (_MVP_ARRAYINDEXSTATE_DIM1INDEX_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_ARRAYINDEXSTATE*/
+#define _MVP_ARRAYINDEXSTATE_DIM2INDEX_SHIFT 20 /**< Shift value for MVP_DIM2INDEX */
+#define _MVP_ARRAYINDEXSTATE_DIM2INDEX_MASK 0x3FF00000UL /**< Bit mask for MVP_DIM2INDEX */
+#define _MVP_ARRAYINDEXSTATE_DIM2INDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYINDEXSTATE */
+#define MVP_ARRAYINDEXSTATE_DIM2INDEX_DEFAULT (_MVP_ARRAYINDEXSTATE_DIM2INDEX_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_ARRAYINDEXSTATE*/
+
+/* Bit fields for MVP LOOPSTATE */
+#define _MVP_LOOPSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_LOOPSTATE */
+#define _MVP_LOOPSTATE_MASK 0x000713FFUL /**< Mask for MVP_LOOPSTATE */
+#define _MVP_LOOPSTATE_CNT_SHIFT 0 /**< Shift value for MVP_CNT */
+#define _MVP_LOOPSTATE_CNT_MASK 0x3FFUL /**< Bit mask for MVP_CNT */
+#define _MVP_LOOPSTATE_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPSTATE */
+#define MVP_LOOPSTATE_CNT_DEFAULT (_MVP_LOOPSTATE_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_LOOPSTATE */
+#define MVP_LOOPSTATE_ACTIVE (0x1UL << 12) /**< Loop Active */
+#define _MVP_LOOPSTATE_ACTIVE_SHIFT 12 /**< Shift value for MVP_ACTIVE */
+#define _MVP_LOOPSTATE_ACTIVE_MASK 0x1000UL /**< Bit mask for MVP_ACTIVE */
+#define _MVP_LOOPSTATE_ACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPSTATE */
+#define MVP_LOOPSTATE_ACTIVE_DEFAULT (_MVP_LOOPSTATE_ACTIVE_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_LOOPSTATE */
+#define _MVP_LOOPSTATE_PCBEGIN_SHIFT 16 /**< Shift value for MVP_PCBEGIN */
+#define _MVP_LOOPSTATE_PCBEGIN_MASK 0x70000UL /**< Bit mask for MVP_PCBEGIN */
+#define _MVP_LOOPSTATE_PCBEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPSTATE */
+#define MVP_LOOPSTATE_PCBEGIN_DEFAULT (_MVP_LOOPSTATE_PCBEGIN_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_LOOPSTATE */
+
+/* Bit fields for MVP ALUREGSTATE */
+#define _MVP_ALUREGSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_ALUREGSTATE */
+#define _MVP_ALUREGSTATE_MASK 0xFFFFFFFFUL /**< Mask for MVP_ALUREGSTATE */
+#define _MVP_ALUREGSTATE_FREAL_SHIFT 0 /**< Shift value for MVP_FREAL */
+#define _MVP_ALUREGSTATE_FREAL_MASK 0xFFFFUL /**< Bit mask for MVP_FREAL */
+#define _MVP_ALUREGSTATE_FREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ALUREGSTATE */
+#define MVP_ALUREGSTATE_FREAL_DEFAULT (_MVP_ALUREGSTATE_FREAL_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ALUREGSTATE */
+#define _MVP_ALUREGSTATE_FIMAG_SHIFT 16 /**< Shift value for MVP_FIMAG */
+#define _MVP_ALUREGSTATE_FIMAG_MASK 0xFFFF0000UL /**< Bit mask for MVP_FIMAG */
+#define _MVP_ALUREGSTATE_FIMAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ALUREGSTATE */
+#define MVP_ALUREGSTATE_FIMAG_DEFAULT (_MVP_ALUREGSTATE_FIMAG_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ALUREGSTATE */
+
+/* Bit fields for MVP ARRAYADDRCFG */
+#define _MVP_ARRAYADDRCFG_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYADDRCFG */
+#define _MVP_ARRAYADDRCFG_MASK 0xFFFFFFFFUL /**< Mask for MVP_ARRAYADDRCFG */
+#define _MVP_ARRAYADDRCFG_BASE_SHIFT 0 /**< Shift value for MVP_BASE */
+#define _MVP_ARRAYADDRCFG_BASE_MASK 0xFFFFFFFFUL /**< Bit mask for MVP_BASE */
+#define _MVP_ARRAYADDRCFG_BASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYADDRCFG */
+#define MVP_ARRAYADDRCFG_BASE_DEFAULT (_MVP_ARRAYADDRCFG_BASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYADDRCFG */
+
+/* Bit fields for MVP ARRAYDIM0CFG */
+#define _MVP_ARRAYDIM0CFG_RESETVALUE 0x00002000UL /**< Default value for MVP_ARRAYDIM0CFG */
+#define _MVP_ARRAYDIM0CFG_MASK 0x0FFF73FFUL /**< Mask for MVP_ARRAYDIM0CFG */
+#define _MVP_ARRAYDIM0CFG_SIZE_SHIFT 0 /**< Shift value for MVP_SIZE */
+#define _MVP_ARRAYDIM0CFG_SIZE_MASK 0x3FFUL /**< Bit mask for MVP_SIZE */
+#define _MVP_ARRAYDIM0CFG_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */
+#define MVP_ARRAYDIM0CFG_SIZE_DEFAULT (_MVP_ARRAYDIM0CFG_SIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */
+#define _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT 12 /**< Shift value for MVP_BASETYPE */
+#define _MVP_ARRAYDIM0CFG_BASETYPE_MASK 0x3000UL /**< Bit mask for MVP_BASETYPE */
+#define _MVP_ARRAYDIM0CFG_BASETYPE_DEFAULT 0x00000002UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */
+#define _MVP_ARRAYDIM0CFG_BASETYPE_UINT8 0x00000000UL /**< Mode UINT8 for MVP_ARRAYDIM0CFG */
+#define _MVP_ARRAYDIM0CFG_BASETYPE_INT8 0x00000001UL /**< Mode INT8 for MVP_ARRAYDIM0CFG */
+#define _MVP_ARRAYDIM0CFG_BASETYPE_BINARY16 0x00000002UL /**< Mode BINARY16 for MVP_ARRAYDIM0CFG */
+#define _MVP_ARRAYDIM0CFG_BASETYPE_RESERVED 0x00000003UL /**< Mode RESERVED for MVP_ARRAYDIM0CFG */
+#define MVP_ARRAYDIM0CFG_BASETYPE_DEFAULT (_MVP_ARRAYDIM0CFG_BASETYPE_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */
+#define MVP_ARRAYDIM0CFG_BASETYPE_UINT8 (_MVP_ARRAYDIM0CFG_BASETYPE_UINT8 << 12) /**< Shifted mode UINT8 for MVP_ARRAYDIM0CFG */
+#define MVP_ARRAYDIM0CFG_BASETYPE_INT8 (_MVP_ARRAYDIM0CFG_BASETYPE_INT8 << 12) /**< Shifted mode INT8 for MVP_ARRAYDIM0CFG */
+#define MVP_ARRAYDIM0CFG_BASETYPE_BINARY16 (_MVP_ARRAYDIM0CFG_BASETYPE_BINARY16 << 12) /**< Shifted mode BINARY16 for MVP_ARRAYDIM0CFG */
+#define MVP_ARRAYDIM0CFG_COMPLEX (0x1UL << 14) /**< Complex Data Type */
+#define _MVP_ARRAYDIM0CFG_COMPLEX_SHIFT 14 /**< Shift value for MVP_COMPLEX */
+#define _MVP_ARRAYDIM0CFG_COMPLEX_MASK 0x4000UL /**< Bit mask for MVP_COMPLEX */
+#define _MVP_ARRAYDIM0CFG_COMPLEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */
+#define _MVP_ARRAYDIM0CFG_COMPLEX_SCALAR 0x00000000UL /**< Mode SCALAR for MVP_ARRAYDIM0CFG */
+#define _MVP_ARRAYDIM0CFG_COMPLEX_COMPLEX 0x00000001UL /**< Mode COMPLEX for MVP_ARRAYDIM0CFG */
+#define MVP_ARRAYDIM0CFG_COMPLEX_DEFAULT (_MVP_ARRAYDIM0CFG_COMPLEX_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */
+#define MVP_ARRAYDIM0CFG_COMPLEX_SCALAR (_MVP_ARRAYDIM0CFG_COMPLEX_SCALAR << 14) /**< Shifted mode SCALAR for MVP_ARRAYDIM0CFG */
+#define MVP_ARRAYDIM0CFG_COMPLEX_COMPLEX (_MVP_ARRAYDIM0CFG_COMPLEX_COMPLEX << 14) /**< Shifted mode COMPLEX for MVP_ARRAYDIM0CFG */
+#define _MVP_ARRAYDIM0CFG_STRIDE_SHIFT 16 /**< Shift value for MVP_STRIDE */
+#define _MVP_ARRAYDIM0CFG_STRIDE_MASK 0xFFF0000UL /**< Bit mask for MVP_STRIDE */
+#define _MVP_ARRAYDIM0CFG_STRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */
+#define MVP_ARRAYDIM0CFG_STRIDE_DEFAULT (_MVP_ARRAYDIM0CFG_STRIDE_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */
+
+/* Bit fields for MVP ARRAYDIM1CFG */
+#define _MVP_ARRAYDIM1CFG_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYDIM1CFG */
+#define _MVP_ARRAYDIM1CFG_MASK 0x0FFF03FFUL /**< Mask for MVP_ARRAYDIM1CFG */
+#define _MVP_ARRAYDIM1CFG_SIZE_SHIFT 0 /**< Shift value for MVP_SIZE */
+#define _MVP_ARRAYDIM1CFG_SIZE_MASK 0x3FFUL /**< Bit mask for MVP_SIZE */
+#define _MVP_ARRAYDIM1CFG_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM1CFG */
+#define MVP_ARRAYDIM1CFG_SIZE_DEFAULT (_MVP_ARRAYDIM1CFG_SIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYDIM1CFG */
+#define _MVP_ARRAYDIM1CFG_STRIDE_SHIFT 16 /**< Shift value for MVP_STRIDE */
+#define _MVP_ARRAYDIM1CFG_STRIDE_MASK 0xFFF0000UL /**< Bit mask for MVP_STRIDE */
+#define _MVP_ARRAYDIM1CFG_STRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM1CFG */
+#define MVP_ARRAYDIM1CFG_STRIDE_DEFAULT (_MVP_ARRAYDIM1CFG_STRIDE_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ARRAYDIM1CFG */
+
+/* Bit fields for MVP ARRAYDIM2CFG */
+#define _MVP_ARRAYDIM2CFG_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYDIM2CFG */
+#define _MVP_ARRAYDIM2CFG_MASK 0x0FFF03FFUL /**< Mask for MVP_ARRAYDIM2CFG */
+#define _MVP_ARRAYDIM2CFG_SIZE_SHIFT 0 /**< Shift value for MVP_SIZE */
+#define _MVP_ARRAYDIM2CFG_SIZE_MASK 0x3FFUL /**< Bit mask for MVP_SIZE */
+#define _MVP_ARRAYDIM2CFG_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM2CFG */
+#define MVP_ARRAYDIM2CFG_SIZE_DEFAULT (_MVP_ARRAYDIM2CFG_SIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYDIM2CFG */
+#define _MVP_ARRAYDIM2CFG_STRIDE_SHIFT 16 /**< Shift value for MVP_STRIDE */
+#define _MVP_ARRAYDIM2CFG_STRIDE_MASK 0xFFF0000UL /**< Bit mask for MVP_STRIDE */
+#define _MVP_ARRAYDIM2CFG_STRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM2CFG */
+#define MVP_ARRAYDIM2CFG_STRIDE_DEFAULT (_MVP_ARRAYDIM2CFG_STRIDE_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ARRAYDIM2CFG */
+
+/* Bit fields for MVP LOOPCFG */
+#define _MVP_LOOPCFG_RESETVALUE 0x00000000UL /**< Default value for MVP_LOOPCFG */
+#define _MVP_LOOPCFG_MASK 0x777773FFUL /**< Mask for MVP_LOOPCFG */
+#define _MVP_LOOPCFG_NUMITERS_SHIFT 0 /**< Shift value for MVP_NUMITERS */
+#define _MVP_LOOPCFG_NUMITERS_MASK 0x3FFUL /**< Bit mask for MVP_NUMITERS */
+#define _MVP_LOOPCFG_NUMITERS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
+#define MVP_LOOPCFG_NUMITERS_DEFAULT (_MVP_LOOPCFG_NUMITERS_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
+#define MVP_LOOPCFG_ARRAY0INCRDIM0 (0x1UL << 12) /**< Increment Dimension 0 */
+#define _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT 12 /**< Shift value for MVP_ARRAY0INCRDIM0 */
+#define _MVP_LOOPCFG_ARRAY0INCRDIM0_MASK 0x1000UL /**< Bit mask for MVP_ARRAY0INCRDIM0 */
+#define _MVP_LOOPCFG_ARRAY0INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
+#define MVP_LOOPCFG_ARRAY0INCRDIM0_DEFAULT (_MVP_LOOPCFG_ARRAY0INCRDIM0_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
+#define MVP_LOOPCFG_ARRAY0INCRDIM1 (0x1UL << 13) /**< Increment Dimension 1 */
+#define _MVP_LOOPCFG_ARRAY0INCRDIM1_SHIFT 13 /**< Shift value for MVP_ARRAY0INCRDIM1 */
+#define _MVP_LOOPCFG_ARRAY0INCRDIM1_MASK 0x2000UL /**< Bit mask for MVP_ARRAY0INCRDIM1 */
+#define _MVP_LOOPCFG_ARRAY0INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
+#define MVP_LOOPCFG_ARRAY0INCRDIM1_DEFAULT (_MVP_LOOPCFG_ARRAY0INCRDIM1_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
+#define MVP_LOOPCFG_ARRAY0INCRDIM2 (0x1UL << 14) /**< Increment Dimension 2 */
+#define _MVP_LOOPCFG_ARRAY0INCRDIM2_SHIFT 14 /**< Shift value for MVP_ARRAY0INCRDIM2 */
+#define _MVP_LOOPCFG_ARRAY0INCRDIM2_MASK 0x4000UL /**< Bit mask for MVP_ARRAY0INCRDIM2 */
+#define _MVP_LOOPCFG_ARRAY0INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
+#define MVP_LOOPCFG_ARRAY0INCRDIM2_DEFAULT (_MVP_LOOPCFG_ARRAY0INCRDIM2_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
+#define MVP_LOOPCFG_ARRAY1INCRDIM0 (0x1UL << 16) /**< Increment Dimension 0 */
+#define _MVP_LOOPCFG_ARRAY1INCRDIM0_SHIFT 16 /**< Shift value for MVP_ARRAY1INCRDIM0 */
+#define _MVP_LOOPCFG_ARRAY1INCRDIM0_MASK 0x10000UL /**< Bit mask for MVP_ARRAY1INCRDIM0 */
+#define _MVP_LOOPCFG_ARRAY1INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
+#define MVP_LOOPCFG_ARRAY1INCRDIM0_DEFAULT (_MVP_LOOPCFG_ARRAY1INCRDIM0_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
+#define MVP_LOOPCFG_ARRAY1INCRDIM1 (0x1UL << 17) /**< Increment Dimension 1 */
+#define _MVP_LOOPCFG_ARRAY1INCRDIM1_SHIFT 17 /**< Shift value for MVP_ARRAY1INCRDIM1 */
+#define _MVP_LOOPCFG_ARRAY1INCRDIM1_MASK 0x20000UL /**< Bit mask for MVP_ARRAY1INCRDIM1 */
+#define _MVP_LOOPCFG_ARRAY1INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
+#define MVP_LOOPCFG_ARRAY1INCRDIM1_DEFAULT (_MVP_LOOPCFG_ARRAY1INCRDIM1_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
+#define MVP_LOOPCFG_ARRAY1INCRDIM2 (0x1UL << 18) /**< Increment Dimension 2 */
+#define _MVP_LOOPCFG_ARRAY1INCRDIM2_SHIFT 18 /**< Shift value for MVP_ARRAY1INCRDIM2 */
+#define _MVP_LOOPCFG_ARRAY1INCRDIM2_MASK 0x40000UL /**< Bit mask for MVP_ARRAY1INCRDIM2 */
+#define _MVP_LOOPCFG_ARRAY1INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
+#define MVP_LOOPCFG_ARRAY1INCRDIM2_DEFAULT (_MVP_LOOPCFG_ARRAY1INCRDIM2_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
+#define MVP_LOOPCFG_ARRAY2INCRDIM0 (0x1UL << 20) /**< Increment Dimension 0 */
+#define _MVP_LOOPCFG_ARRAY2INCRDIM0_SHIFT 20 /**< Shift value for MVP_ARRAY2INCRDIM0 */
+#define _MVP_LOOPCFG_ARRAY2INCRDIM0_MASK 0x100000UL /**< Bit mask for MVP_ARRAY2INCRDIM0 */
+#define _MVP_LOOPCFG_ARRAY2INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
+#define MVP_LOOPCFG_ARRAY2INCRDIM0_DEFAULT (_MVP_LOOPCFG_ARRAY2INCRDIM0_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
+#define MVP_LOOPCFG_ARRAY2INCRDIM1 (0x1UL << 21) /**< Increment Dimension 1 */
+#define _MVP_LOOPCFG_ARRAY2INCRDIM1_SHIFT 21 /**< Shift value for MVP_ARRAY2INCRDIM1 */
+#define _MVP_LOOPCFG_ARRAY2INCRDIM1_MASK 0x200000UL /**< Bit mask for MVP_ARRAY2INCRDIM1 */
+#define _MVP_LOOPCFG_ARRAY2INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
+#define MVP_LOOPCFG_ARRAY2INCRDIM1_DEFAULT (_MVP_LOOPCFG_ARRAY2INCRDIM1_DEFAULT << 21) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
+#define MVP_LOOPCFG_ARRAY2INCRDIM2 (0x1UL << 22) /**< Increment Dimension 2 */
+#define _MVP_LOOPCFG_ARRAY2INCRDIM2_SHIFT 22 /**< Shift value for MVP_ARRAY2INCRDIM2 */
+#define _MVP_LOOPCFG_ARRAY2INCRDIM2_MASK 0x400000UL /**< Bit mask for MVP_ARRAY2INCRDIM2 */
+#define _MVP_LOOPCFG_ARRAY2INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
+#define MVP_LOOPCFG_ARRAY2INCRDIM2_DEFAULT (_MVP_LOOPCFG_ARRAY2INCRDIM2_DEFAULT << 22) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
+#define MVP_LOOPCFG_ARRAY3INCRDIM0 (0x1UL << 24) /**< Increment Dimension 0 */
+#define _MVP_LOOPCFG_ARRAY3INCRDIM0_SHIFT 24 /**< Shift value for MVP_ARRAY3INCRDIM0 */
+#define _MVP_LOOPCFG_ARRAY3INCRDIM0_MASK 0x1000000UL /**< Bit mask for MVP_ARRAY3INCRDIM0 */
+#define _MVP_LOOPCFG_ARRAY3INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
+#define MVP_LOOPCFG_ARRAY3INCRDIM0_DEFAULT (_MVP_LOOPCFG_ARRAY3INCRDIM0_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
+#define MVP_LOOPCFG_ARRAY3INCRDIM1 (0x1UL << 25) /**< Increment Dimension 1 */
+#define _MVP_LOOPCFG_ARRAY3INCRDIM1_SHIFT 25 /**< Shift value for MVP_ARRAY3INCRDIM1 */
+#define _MVP_LOOPCFG_ARRAY3INCRDIM1_MASK 0x2000000UL /**< Bit mask for MVP_ARRAY3INCRDIM1 */
+#define _MVP_LOOPCFG_ARRAY3INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
+#define MVP_LOOPCFG_ARRAY3INCRDIM1_DEFAULT (_MVP_LOOPCFG_ARRAY3INCRDIM1_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
+#define MVP_LOOPCFG_ARRAY3INCRDIM2 (0x1UL << 26) /**< Increment Dimension 2 */
+#define _MVP_LOOPCFG_ARRAY3INCRDIM2_SHIFT 26 /**< Shift value for MVP_ARRAY3INCRDIM2 */
+#define _MVP_LOOPCFG_ARRAY3INCRDIM2_MASK 0x4000000UL /**< Bit mask for MVP_ARRAY3INCRDIM2 */
+#define _MVP_LOOPCFG_ARRAY3INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
+#define MVP_LOOPCFG_ARRAY3INCRDIM2_DEFAULT (_MVP_LOOPCFG_ARRAY3INCRDIM2_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
+#define MVP_LOOPCFG_ARRAY4INCRDIM0 (0x1UL << 28) /**< Increment Dimension 0 */
+#define _MVP_LOOPCFG_ARRAY4INCRDIM0_SHIFT 28 /**< Shift value for MVP_ARRAY4INCRDIM0 */
+#define _MVP_LOOPCFG_ARRAY4INCRDIM0_MASK 0x10000000UL /**< Bit mask for MVP_ARRAY4INCRDIM0 */
+#define _MVP_LOOPCFG_ARRAY4INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
+#define MVP_LOOPCFG_ARRAY4INCRDIM0_DEFAULT (_MVP_LOOPCFG_ARRAY4INCRDIM0_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
+#define MVP_LOOPCFG_ARRAY4INCRDIM1 (0x1UL << 29) /**< Increment Dimension 1 */
+#define _MVP_LOOPCFG_ARRAY4INCRDIM1_SHIFT 29 /**< Shift value for MVP_ARRAY4INCRDIM1 */
+#define _MVP_LOOPCFG_ARRAY4INCRDIM1_MASK 0x20000000UL /**< Bit mask for MVP_ARRAY4INCRDIM1 */
+#define _MVP_LOOPCFG_ARRAY4INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
+#define MVP_LOOPCFG_ARRAY4INCRDIM1_DEFAULT (_MVP_LOOPCFG_ARRAY4INCRDIM1_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
+#define MVP_LOOPCFG_ARRAY4INCRDIM2 (0x1UL << 30) /**< Increment Dimension 2 */
+#define _MVP_LOOPCFG_ARRAY4INCRDIM2_SHIFT 30 /**< Shift value for MVP_ARRAY4INCRDIM2 */
+#define _MVP_LOOPCFG_ARRAY4INCRDIM2_MASK 0x40000000UL /**< Bit mask for MVP_ARRAY4INCRDIM2 */
+#define _MVP_LOOPCFG_ARRAY4INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */
+#define MVP_LOOPCFG_ARRAY4INCRDIM2_DEFAULT (_MVP_LOOPCFG_ARRAY4INCRDIM2_DEFAULT << 30) /**< Shifted mode DEFAULT for MVP_LOOPCFG */
+
+/* Bit fields for MVP LOOPRST */
+#define _MVP_LOOPRST_RESETVALUE 0x00000000UL /**< Default value for MVP_LOOPRST */
+#define _MVP_LOOPRST_MASK 0x77777000UL /**< Mask for MVP_LOOPRST */
+#define MVP_LOOPRST_ARRAY0RESETDIM0 (0x1UL << 12) /**< Reset Dimension 0 */
+#define _MVP_LOOPRST_ARRAY0RESETDIM0_SHIFT 12 /**< Shift value for MVP_ARRAY0RESETDIM0 */
+#define _MVP_LOOPRST_ARRAY0RESETDIM0_MASK 0x1000UL /**< Bit mask for MVP_ARRAY0RESETDIM0 */
+#define _MVP_LOOPRST_ARRAY0RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */
+#define MVP_LOOPRST_ARRAY0RESETDIM0_DEFAULT (_MVP_LOOPRST_ARRAY0RESETDIM0_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_LOOPRST */
+#define MVP_LOOPRST_ARRAY0RESETDIM1 (0x1UL << 13) /**< Reset Dimension 1 */
+#define _MVP_LOOPRST_ARRAY0RESETDIM1_SHIFT 13 /**< Shift value for MVP_ARRAY0RESETDIM1 */
+#define _MVP_LOOPRST_ARRAY0RESETDIM1_MASK 0x2000UL /**< Bit mask for MVP_ARRAY0RESETDIM1 */
+#define _MVP_LOOPRST_ARRAY0RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */
+#define MVP_LOOPRST_ARRAY0RESETDIM1_DEFAULT (_MVP_LOOPRST_ARRAY0RESETDIM1_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_LOOPRST */
+#define MVP_LOOPRST_ARRAY0RESETDIM2 (0x1UL << 14) /**< Reset Dimension 2 */
+#define _MVP_LOOPRST_ARRAY0RESETDIM2_SHIFT 14 /**< Shift value for MVP_ARRAY0RESETDIM2 */
+#define _MVP_LOOPRST_ARRAY0RESETDIM2_MASK 0x4000UL /**< Bit mask for MVP_ARRAY0RESETDIM2 */
+#define _MVP_LOOPRST_ARRAY0RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */
+#define MVP_LOOPRST_ARRAY0RESETDIM2_DEFAULT (_MVP_LOOPRST_ARRAY0RESETDIM2_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_LOOPRST */
+#define MVP_LOOPRST_ARRAY1RESETDIM0 (0x1UL << 16) /**< Reset Dimension 0 */
+#define _MVP_LOOPRST_ARRAY1RESETDIM0_SHIFT 16 /**< Shift value for MVP_ARRAY1RESETDIM0 */
+#define _MVP_LOOPRST_ARRAY1RESETDIM0_MASK 0x10000UL /**< Bit mask for MVP_ARRAY1RESETDIM0 */
+#define _MVP_LOOPRST_ARRAY1RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */
+#define MVP_LOOPRST_ARRAY1RESETDIM0_DEFAULT (_MVP_LOOPRST_ARRAY1RESETDIM0_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_LOOPRST */
+#define MVP_LOOPRST_ARRAY1RESETDIM1 (0x1UL << 17) /**< Reset Dimension 1 */
+#define _MVP_LOOPRST_ARRAY1RESETDIM1_SHIFT 17 /**< Shift value for MVP_ARRAY1RESETDIM1 */
+#define _MVP_LOOPRST_ARRAY1RESETDIM1_MASK 0x20000UL /**< Bit mask for MVP_ARRAY1RESETDIM1 */
+#define _MVP_LOOPRST_ARRAY1RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */
+#define MVP_LOOPRST_ARRAY1RESETDIM1_DEFAULT (_MVP_LOOPRST_ARRAY1RESETDIM1_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_LOOPRST */
+#define MVP_LOOPRST_ARRAY1RESETDIM2 (0x1UL << 18) /**< Reset Dimension 2 */
+#define _MVP_LOOPRST_ARRAY1RESETDIM2_SHIFT 18 /**< Shift value for MVP_ARRAY1RESETDIM2 */
+#define _MVP_LOOPRST_ARRAY1RESETDIM2_MASK 0x40000UL /**< Bit mask for MVP_ARRAY1RESETDIM2 */
+#define _MVP_LOOPRST_ARRAY1RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */
+#define MVP_LOOPRST_ARRAY1RESETDIM2_DEFAULT (_MVP_LOOPRST_ARRAY1RESETDIM2_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_LOOPRST */
+#define MVP_LOOPRST_ARRAY2RESETDIM0 (0x1UL << 20) /**< Reset Dimension 0 */
+#define _MVP_LOOPRST_ARRAY2RESETDIM0_SHIFT 20 /**< Shift value for MVP_ARRAY2RESETDIM0 */
+#define _MVP_LOOPRST_ARRAY2RESETDIM0_MASK 0x100000UL /**< Bit mask for MVP_ARRAY2RESETDIM0 */
+#define _MVP_LOOPRST_ARRAY2RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */
+#define MVP_LOOPRST_ARRAY2RESETDIM0_DEFAULT (_MVP_LOOPRST_ARRAY2RESETDIM0_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_LOOPRST */
+#define MVP_LOOPRST_ARRAY2RESETDIM1 (0x1UL << 21) /**< Reset Dimension 1 */
+#define _MVP_LOOPRST_ARRAY2RESETDIM1_SHIFT 21 /**< Shift value for MVP_ARRAY2RESETDIM1 */
+#define _MVP_LOOPRST_ARRAY2RESETDIM1_MASK 0x200000UL /**< Bit mask for MVP_ARRAY2RESETDIM1 */
+#define _MVP_LOOPRST_ARRAY2RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */
+#define MVP_LOOPRST_ARRAY2RESETDIM1_DEFAULT (_MVP_LOOPRST_ARRAY2RESETDIM1_DEFAULT << 21) /**< Shifted mode DEFAULT for MVP_LOOPRST */
+#define MVP_LOOPRST_ARRAY2RESETDIM2 (0x1UL << 22) /**< Reset Dimension 2 */
+#define _MVP_LOOPRST_ARRAY2RESETDIM2_SHIFT 22 /**< Shift value for MVP_ARRAY2RESETDIM2 */
+#define _MVP_LOOPRST_ARRAY2RESETDIM2_MASK 0x400000UL /**< Bit mask for MVP_ARRAY2RESETDIM2 */
+#define _MVP_LOOPRST_ARRAY2RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */
+#define MVP_LOOPRST_ARRAY2RESETDIM2_DEFAULT (_MVP_LOOPRST_ARRAY2RESETDIM2_DEFAULT << 22) /**< Shifted mode DEFAULT for MVP_LOOPRST */
+#define MVP_LOOPRST_ARRAY3RESETDIM0 (0x1UL << 24) /**< Reset Dimension 0 */
+#define _MVP_LOOPRST_ARRAY3RESETDIM0_SHIFT 24 /**< Shift value for MVP_ARRAY3RESETDIM0 */
+#define _MVP_LOOPRST_ARRAY3RESETDIM0_MASK 0x1000000UL /**< Bit mask for MVP_ARRAY3RESETDIM0 */
+#define _MVP_LOOPRST_ARRAY3RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */
+#define MVP_LOOPRST_ARRAY3RESETDIM0_DEFAULT (_MVP_LOOPRST_ARRAY3RESETDIM0_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_LOOPRST */
+#define MVP_LOOPRST_ARRAY3RESETDIM1 (0x1UL << 25) /**< Reset Dimension 1 */
+#define _MVP_LOOPRST_ARRAY3RESETDIM1_SHIFT 25 /**< Shift value for MVP_ARRAY3RESETDIM1 */
+#define _MVP_LOOPRST_ARRAY3RESETDIM1_MASK 0x2000000UL /**< Bit mask for MVP_ARRAY3RESETDIM1 */
+#define _MVP_LOOPRST_ARRAY3RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */
+#define MVP_LOOPRST_ARRAY3RESETDIM1_DEFAULT (_MVP_LOOPRST_ARRAY3RESETDIM1_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_LOOPRST */
+#define MVP_LOOPRST_ARRAY3RESETDIM2 (0x1UL << 26) /**< Reset Dimension 2 */
+#define _MVP_LOOPRST_ARRAY3RESETDIM2_SHIFT 26 /**< Shift value for MVP_ARRAY3RESETDIM2 */
+#define _MVP_LOOPRST_ARRAY3RESETDIM2_MASK 0x4000000UL /**< Bit mask for MVP_ARRAY3RESETDIM2 */
+#define _MVP_LOOPRST_ARRAY3RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */
+#define MVP_LOOPRST_ARRAY3RESETDIM2_DEFAULT (_MVP_LOOPRST_ARRAY3RESETDIM2_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_LOOPRST */
+#define MVP_LOOPRST_ARRAY4RESETDIM0 (0x1UL << 28) /**< Reset Dimension 0 */
+#define _MVP_LOOPRST_ARRAY4RESETDIM0_SHIFT 28 /**< Shift value for MVP_ARRAY4RESETDIM0 */
+#define _MVP_LOOPRST_ARRAY4RESETDIM0_MASK 0x10000000UL /**< Bit mask for MVP_ARRAY4RESETDIM0 */
+#define _MVP_LOOPRST_ARRAY4RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */
+#define MVP_LOOPRST_ARRAY4RESETDIM0_DEFAULT (_MVP_LOOPRST_ARRAY4RESETDIM0_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_LOOPRST */
+#define MVP_LOOPRST_ARRAY4RESETDIM1 (0x1UL << 29) /**< Reset Dimension 1 */
+#define _MVP_LOOPRST_ARRAY4RESETDIM1_SHIFT 29 /**< Shift value for MVP_ARRAY4RESETDIM1 */
+#define _MVP_LOOPRST_ARRAY4RESETDIM1_MASK 0x20000000UL /**< Bit mask for MVP_ARRAY4RESETDIM1 */
+#define _MVP_LOOPRST_ARRAY4RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */
+#define MVP_LOOPRST_ARRAY4RESETDIM1_DEFAULT (_MVP_LOOPRST_ARRAY4RESETDIM1_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_LOOPRST */
+#define MVP_LOOPRST_ARRAY4RESETDIM2 (0x1UL << 30) /**< Reset Dimension 2 */
+#define _MVP_LOOPRST_ARRAY4RESETDIM2_SHIFT 30 /**< Shift value for MVP_ARRAY4RESETDIM2 */
+#define _MVP_LOOPRST_ARRAY4RESETDIM2_MASK 0x40000000UL /**< Bit mask for MVP_ARRAY4RESETDIM2 */
+#define _MVP_LOOPRST_ARRAY4RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */
+#define MVP_LOOPRST_ARRAY4RESETDIM2_DEFAULT (_MVP_LOOPRST_ARRAY4RESETDIM2_DEFAULT << 30) /**< Shifted mode DEFAULT for MVP_LOOPRST */
+
+/* Bit fields for MVP INSTRCFG0 */
+#define _MVP_INSTRCFG0_RESETVALUE 0x00000000UL /**< Default value for MVP_INSTRCFG0 */
+#define _MVP_INSTRCFG0_MASK 0x70F7F7F7UL /**< Mask for MVP_INSTRCFG0 */
+#define _MVP_INSTRCFG0_ALUIN0REGID_SHIFT 0 /**< Shift value for MVP_ALUIN0REGID */
+#define _MVP_INSTRCFG0_ALUIN0REGID_MASK 0x7UL /**< Bit mask for MVP_ALUIN0REGID */
+#define _MVP_INSTRCFG0_ALUIN0REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
+#define MVP_INSTRCFG0_ALUIN0REGID_DEFAULT (_MVP_INSTRCFG0_ALUIN0REGID_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
+#define MVP_INSTRCFG0_ALUIN0REALZERO (0x1UL << 4) /**< Real Zero */
+#define _MVP_INSTRCFG0_ALUIN0REALZERO_SHIFT 4 /**< Shift value for MVP_ALUIN0REALZERO */
+#define _MVP_INSTRCFG0_ALUIN0REALZERO_MASK 0x10UL /**< Bit mask for MVP_ALUIN0REALZERO */
+#define _MVP_INSTRCFG0_ALUIN0REALZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
+#define MVP_INSTRCFG0_ALUIN0REALZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN0REALZERO_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
+#define MVP_INSTRCFG0_ALUIN0REALNEGATE (0x1UL << 5) /**< Real Negate */
+#define _MVP_INSTRCFG0_ALUIN0REALNEGATE_SHIFT 5 /**< Shift value for MVP_ALUIN0REALNEGATE */
+#define _MVP_INSTRCFG0_ALUIN0REALNEGATE_MASK 0x20UL /**< Bit mask for MVP_ALUIN0REALNEGATE */
+#define _MVP_INSTRCFG0_ALUIN0REALNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
+#define MVP_INSTRCFG0_ALUIN0REALNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN0REALNEGATE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
+#define MVP_INSTRCFG0_ALUIN0IMAGZERO (0x1UL << 6) /**< Imaginary Not Zero */
+#define _MVP_INSTRCFG0_ALUIN0IMAGZERO_SHIFT 6 /**< Shift value for MVP_ALUIN0IMAGZERO */
+#define _MVP_INSTRCFG0_ALUIN0IMAGZERO_MASK 0x40UL /**< Bit mask for MVP_ALUIN0IMAGZERO */
+#define _MVP_INSTRCFG0_ALUIN0IMAGZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
+#define MVP_INSTRCFG0_ALUIN0IMAGZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN0IMAGZERO_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
+#define MVP_INSTRCFG0_ALUIN0IMAGNEGATE (0x1UL << 7) /**< Imaginary Negate */
+#define _MVP_INSTRCFG0_ALUIN0IMAGNEGATE_SHIFT 7 /**< Shift value for MVP_ALUIN0IMAGNEGATE */
+#define _MVP_INSTRCFG0_ALUIN0IMAGNEGATE_MASK 0x80UL /**< Bit mask for MVP_ALUIN0IMAGNEGATE */
+#define _MVP_INSTRCFG0_ALUIN0IMAGNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
+#define MVP_INSTRCFG0_ALUIN0IMAGNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN0IMAGNEGATE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
+#define _MVP_INSTRCFG0_ALUIN1REGID_SHIFT 8 /**< Shift value for MVP_ALUIN1REGID */
+#define _MVP_INSTRCFG0_ALUIN1REGID_MASK 0x700UL /**< Bit mask for MVP_ALUIN1REGID */
+#define _MVP_INSTRCFG0_ALUIN1REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
+#define MVP_INSTRCFG0_ALUIN1REGID_DEFAULT (_MVP_INSTRCFG0_ALUIN1REGID_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
+#define MVP_INSTRCFG0_ALUIN1REALZERO (0x1UL << 12) /**< Real Zero */
+#define _MVP_INSTRCFG0_ALUIN1REALZERO_SHIFT 12 /**< Shift value for MVP_ALUIN1REALZERO */
+#define _MVP_INSTRCFG0_ALUIN1REALZERO_MASK 0x1000UL /**< Bit mask for MVP_ALUIN1REALZERO */
+#define _MVP_INSTRCFG0_ALUIN1REALZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
+#define MVP_INSTRCFG0_ALUIN1REALZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN1REALZERO_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
+#define MVP_INSTRCFG0_ALUIN1REALNEGATE (0x1UL << 13) /**< Real Negate */
+#define _MVP_INSTRCFG0_ALUIN1REALNEGATE_SHIFT 13 /**< Shift value for MVP_ALUIN1REALNEGATE */
+#define _MVP_INSTRCFG0_ALUIN1REALNEGATE_MASK 0x2000UL /**< Bit mask for MVP_ALUIN1REALNEGATE */
+#define _MVP_INSTRCFG0_ALUIN1REALNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
+#define MVP_INSTRCFG0_ALUIN1REALNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN1REALNEGATE_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
+#define MVP_INSTRCFG0_ALUIN1IMAGZERO (0x1UL << 14) /**< Imaginary Not Zero */
+#define _MVP_INSTRCFG0_ALUIN1IMAGZERO_SHIFT 14 /**< Shift value for MVP_ALUIN1IMAGZERO */
+#define _MVP_INSTRCFG0_ALUIN1IMAGZERO_MASK 0x4000UL /**< Bit mask for MVP_ALUIN1IMAGZERO */
+#define _MVP_INSTRCFG0_ALUIN1IMAGZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
+#define MVP_INSTRCFG0_ALUIN1IMAGZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN1IMAGZERO_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
+#define MVP_INSTRCFG0_ALUIN1IMAGNEGATE (0x1UL << 15) /**< Imaginary Negate */
+#define _MVP_INSTRCFG0_ALUIN1IMAGNEGATE_SHIFT 15 /**< Shift value for MVP_ALUIN1IMAGNEGATE */
+#define _MVP_INSTRCFG0_ALUIN1IMAGNEGATE_MASK 0x8000UL /**< Bit mask for MVP_ALUIN1IMAGNEGATE */
+#define _MVP_INSTRCFG0_ALUIN1IMAGNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
+#define MVP_INSTRCFG0_ALUIN1IMAGNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN1IMAGNEGATE_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
+#define _MVP_INSTRCFG0_ALUIN2REGID_SHIFT 16 /**< Shift value for MVP_ALUIN2REGID */
+#define _MVP_INSTRCFG0_ALUIN2REGID_MASK 0x70000UL /**< Bit mask for MVP_ALUIN2REGID */
+#define _MVP_INSTRCFG0_ALUIN2REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
+#define MVP_INSTRCFG0_ALUIN2REGID_DEFAULT (_MVP_INSTRCFG0_ALUIN2REGID_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
+#define MVP_INSTRCFG0_ALUIN2REALZERO (0x1UL << 20) /**< Real Zero */
+#define _MVP_INSTRCFG0_ALUIN2REALZERO_SHIFT 20 /**< Shift value for MVP_ALUIN2REALZERO */
+#define _MVP_INSTRCFG0_ALUIN2REALZERO_MASK 0x100000UL /**< Bit mask for MVP_ALUIN2REALZERO */
+#define _MVP_INSTRCFG0_ALUIN2REALZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
+#define MVP_INSTRCFG0_ALUIN2REALZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN2REALZERO_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
+#define MVP_INSTRCFG0_ALUIN2REALNEGATE (0x1UL << 21) /**< Real Negate */
+#define _MVP_INSTRCFG0_ALUIN2REALNEGATE_SHIFT 21 /**< Shift value for MVP_ALUIN2REALNEGATE */
+#define _MVP_INSTRCFG0_ALUIN2REALNEGATE_MASK 0x200000UL /**< Bit mask for MVP_ALUIN2REALNEGATE */
+#define _MVP_INSTRCFG0_ALUIN2REALNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
+#define MVP_INSTRCFG0_ALUIN2REALNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN2REALNEGATE_DEFAULT << 21) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
+#define MVP_INSTRCFG0_ALUIN2IMAGZERO (0x1UL << 22) /**< Imaginary Not Zero */
+#define _MVP_INSTRCFG0_ALUIN2IMAGZERO_SHIFT 22 /**< Shift value for MVP_ALUIN2IMAGZERO */
+#define _MVP_INSTRCFG0_ALUIN2IMAGZERO_MASK 0x400000UL /**< Bit mask for MVP_ALUIN2IMAGZERO */
+#define _MVP_INSTRCFG0_ALUIN2IMAGZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
+#define MVP_INSTRCFG0_ALUIN2IMAGZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN2IMAGZERO_DEFAULT << 22) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
+#define MVP_INSTRCFG0_ALUIN2IMAGNEGATE (0x1UL << 23) /**< Imaginary Negate */
+#define _MVP_INSTRCFG0_ALUIN2IMAGNEGATE_SHIFT 23 /**< Shift value for MVP_ALUIN2IMAGNEGATE */
+#define _MVP_INSTRCFG0_ALUIN2IMAGNEGATE_MASK 0x800000UL /**< Bit mask for MVP_ALUIN2IMAGNEGATE */
+#define _MVP_INSTRCFG0_ALUIN2IMAGNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
+#define MVP_INSTRCFG0_ALUIN2IMAGNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN2IMAGNEGATE_DEFAULT << 23) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
+#define _MVP_INSTRCFG0_ALUOUTREGID_SHIFT 28 /**< Shift value for MVP_ALUOUTREGID */
+#define _MVP_INSTRCFG0_ALUOUTREGID_MASK 0x70000000UL /**< Bit mask for MVP_ALUOUTREGID */
+#define _MVP_INSTRCFG0_ALUOUTREGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */
+#define MVP_INSTRCFG0_ALUOUTREGID_DEFAULT (_MVP_INSTRCFG0_ALUOUTREGID_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */
+
+/* Bit fields for MVP INSTRCFG1 */
+#define _MVP_INSTRCFG1_RESETVALUE 0x00000000UL /**< Default value for MVP_INSTRCFG1 */
+#define _MVP_INSTRCFG1_MASK 0x3FFFFFFFUL /**< Mask for MVP_INSTRCFG1 */
+#define _MVP_INSTRCFG1_ISTREAM0REGID_SHIFT 0 /**< Shift value for MVP_ISTREAM0REGID */
+#define _MVP_INSTRCFG1_ISTREAM0REGID_MASK 0x7UL /**< Bit mask for MVP_ISTREAM0REGID */
+#define _MVP_INSTRCFG1_ISTREAM0REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
+#define MVP_INSTRCFG1_ISTREAM0REGID_DEFAULT (_MVP_INSTRCFG1_ISTREAM0REGID_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
+#define MVP_INSTRCFG1_ISTREAM0LOAD (0x1UL << 3) /**< Load register */
+#define _MVP_INSTRCFG1_ISTREAM0LOAD_SHIFT 3 /**< Shift value for MVP_ISTREAM0LOAD */
+#define _MVP_INSTRCFG1_ISTREAM0LOAD_MASK 0x8UL /**< Bit mask for MVP_ISTREAM0LOAD */
+#define _MVP_INSTRCFG1_ISTREAM0LOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
+#define MVP_INSTRCFG1_ISTREAM0LOAD_DEFAULT (_MVP_INSTRCFG1_ISTREAM0LOAD_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
+#define _MVP_INSTRCFG1_ISTREAM0ARRAYID_SHIFT 4 /**< Shift value for MVP_ISTREAM0ARRAYID */
+#define _MVP_INSTRCFG1_ISTREAM0ARRAYID_MASK 0x70UL /**< Bit mask for MVP_ISTREAM0ARRAYID */
+#define _MVP_INSTRCFG1_ISTREAM0ARRAYID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
+#define MVP_INSTRCFG1_ISTREAM0ARRAYID_DEFAULT (_MVP_INSTRCFG1_ISTREAM0ARRAYID_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
+#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0 (0x1UL << 7) /**< Increment Array Dimension 0 */
+#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_SHIFT 7 /**< Shift value for MVP_ISTREAM0ARRAYINCRDIM0 */
+#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_MASK 0x80UL /**< Bit mask for MVP_ISTREAM0ARRAYINCRDIM0 */
+#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
+#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_DEFAULT (_MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
+#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1 (0x1UL << 8) /**< Increment Array Dimension 1 */
+#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_SHIFT 8 /**< Shift value for MVP_ISTREAM0ARRAYINCRDIM1 */
+#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_MASK 0x100UL /**< Bit mask for MVP_ISTREAM0ARRAYINCRDIM1 */
+#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
+#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_DEFAULT (_MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
+#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2 (0x1UL << 9) /**< Increment Array Dimension 2 */
+#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_SHIFT 9 /**< Shift value for MVP_ISTREAM0ARRAYINCRDIM2 */
+#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_MASK 0x200UL /**< Bit mask for MVP_ISTREAM0ARRAYINCRDIM2 */
+#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
+#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_DEFAULT (_MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_DEFAULT << 9) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
+#define _MVP_INSTRCFG1_ISTREAM1REGID_SHIFT 10 /**< Shift value for MVP_ISTREAM1REGID */
+#define _MVP_INSTRCFG1_ISTREAM1REGID_MASK 0x1C00UL /**< Bit mask for MVP_ISTREAM1REGID */
+#define _MVP_INSTRCFG1_ISTREAM1REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
+#define MVP_INSTRCFG1_ISTREAM1REGID_DEFAULT (_MVP_INSTRCFG1_ISTREAM1REGID_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
+#define MVP_INSTRCFG1_ISTREAM1LOAD (0x1UL << 13) /**< Load register */
+#define _MVP_INSTRCFG1_ISTREAM1LOAD_SHIFT 13 /**< Shift value for MVP_ISTREAM1LOAD */
+#define _MVP_INSTRCFG1_ISTREAM1LOAD_MASK 0x2000UL /**< Bit mask for MVP_ISTREAM1LOAD */
+#define _MVP_INSTRCFG1_ISTREAM1LOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
+#define MVP_INSTRCFG1_ISTREAM1LOAD_DEFAULT (_MVP_INSTRCFG1_ISTREAM1LOAD_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
+#define _MVP_INSTRCFG1_ISTREAM1ARRAYID_SHIFT 14 /**< Shift value for MVP_ISTREAM1ARRAYID */
+#define _MVP_INSTRCFG1_ISTREAM1ARRAYID_MASK 0x1C000UL /**< Bit mask for MVP_ISTREAM1ARRAYID */
+#define _MVP_INSTRCFG1_ISTREAM1ARRAYID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
+#define MVP_INSTRCFG1_ISTREAM1ARRAYID_DEFAULT (_MVP_INSTRCFG1_ISTREAM1ARRAYID_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
+#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0 (0x1UL << 17) /**< Increment Array Dimension 0 */
+#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_SHIFT 17 /**< Shift value for MVP_ISTREAM1ARRAYINCRDIM0 */
+#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_MASK 0x20000UL /**< Bit mask for MVP_ISTREAM1ARRAYINCRDIM0 */
+#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
+#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_DEFAULT (_MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
+#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1 (0x1UL << 18) /**< Increment Array Dimension 1 */
+#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_SHIFT 18 /**< Shift value for MVP_ISTREAM1ARRAYINCRDIM1 */
+#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_MASK 0x40000UL /**< Bit mask for MVP_ISTREAM1ARRAYINCRDIM1 */
+#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
+#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_DEFAULT (_MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
+#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2 (0x1UL << 19) /**< Increment Array Dimension 2 */
+#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_SHIFT 19 /**< Shift value for MVP_ISTREAM1ARRAYINCRDIM2 */
+#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_MASK 0x80000UL /**< Bit mask for MVP_ISTREAM1ARRAYINCRDIM2 */
+#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
+#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_DEFAULT (_MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_DEFAULT << 19) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
+#define _MVP_INSTRCFG1_OSTREAMREGID_SHIFT 20 /**< Shift value for MVP_OSTREAMREGID */
+#define _MVP_INSTRCFG1_OSTREAMREGID_MASK 0x700000UL /**< Bit mask for MVP_OSTREAMREGID */
+#define _MVP_INSTRCFG1_OSTREAMREGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
+#define MVP_INSTRCFG1_OSTREAMREGID_DEFAULT (_MVP_INSTRCFG1_OSTREAMREGID_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
+#define MVP_INSTRCFG1_OSTREAMSTORE (0x1UL << 23) /**< Store to Register */
+#define _MVP_INSTRCFG1_OSTREAMSTORE_SHIFT 23 /**< Shift value for MVP_OSTREAMSTORE */
+#define _MVP_INSTRCFG1_OSTREAMSTORE_MASK 0x800000UL /**< Bit mask for MVP_OSTREAMSTORE */
+#define _MVP_INSTRCFG1_OSTREAMSTORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
+#define MVP_INSTRCFG1_OSTREAMSTORE_DEFAULT (_MVP_INSTRCFG1_OSTREAMSTORE_DEFAULT << 23) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
+#define _MVP_INSTRCFG1_OSTREAMARRAYID_SHIFT 24 /**< Shift value for MVP_OSTREAMARRAYID */
+#define _MVP_INSTRCFG1_OSTREAMARRAYID_MASK 0x7000000UL /**< Bit mask for MVP_OSTREAMARRAYID */
+#define _MVP_INSTRCFG1_OSTREAMARRAYID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
+#define MVP_INSTRCFG1_OSTREAMARRAYID_DEFAULT (_MVP_INSTRCFG1_OSTREAMARRAYID_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
+#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0 (0x1UL << 27) /**< Increment Array Dimension 0 */
+#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_SHIFT 27 /**< Shift value for MVP_OSTREAMARRAYINCRDIM0 */
+#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_MASK 0x8000000UL /**< Bit mask for MVP_OSTREAMARRAYINCRDIM0 */
+#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
+#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_DEFAULT (_MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_DEFAULT << 27) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
+#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1 (0x1UL << 28) /**< Increment Array Dimension 1 */
+#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_SHIFT 28 /**< Shift value for MVP_OSTREAMARRAYINCRDIM1 */
+#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_MASK 0x10000000UL /**< Bit mask for MVP_OSTREAMARRAYINCRDIM1 */
+#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
+#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_DEFAULT (_MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
+#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2 (0x1UL << 29) /**< Increment Array Dimension 2 */
+#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_SHIFT 29 /**< Shift value for MVP_OSTREAMARRAYINCRDIM2 */
+#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_MASK 0x20000000UL /**< Bit mask for MVP_OSTREAMARRAYINCRDIM2 */
+#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */
+#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_DEFAULT (_MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */
+
+/* Bit fields for MVP INSTRCFG2 */
+#define _MVP_INSTRCFG2_RESETVALUE 0x00000000UL /**< Default value for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_MASK 0x9FF0FFFFUL /**< Mask for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP0BEGIN (0x1UL << 0) /**< Loop Begin */
+#define _MVP_INSTRCFG2_LOOP0BEGIN_SHIFT 0 /**< Shift value for MVP_LOOP0BEGIN */
+#define _MVP_INSTRCFG2_LOOP0BEGIN_MASK 0x1UL /**< Bit mask for MVP_LOOP0BEGIN */
+#define _MVP_INSTRCFG2_LOOP0BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP0BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP0BEGIN_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP0END (0x1UL << 1) /**< Loop End */
+#define _MVP_INSTRCFG2_LOOP0END_SHIFT 1 /**< Shift value for MVP_LOOP0END */
+#define _MVP_INSTRCFG2_LOOP0END_MASK 0x2UL /**< Bit mask for MVP_LOOP0END */
+#define _MVP_INSTRCFG2_LOOP0END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP0END_DEFAULT (_MVP_INSTRCFG2_LOOP0END_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP1BEGIN (0x1UL << 2) /**< Loop Begin */
+#define _MVP_INSTRCFG2_LOOP1BEGIN_SHIFT 2 /**< Shift value for MVP_LOOP1BEGIN */
+#define _MVP_INSTRCFG2_LOOP1BEGIN_MASK 0x4UL /**< Bit mask for MVP_LOOP1BEGIN */
+#define _MVP_INSTRCFG2_LOOP1BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP1BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP1BEGIN_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP1END (0x1UL << 3) /**< Loop End */
+#define _MVP_INSTRCFG2_LOOP1END_SHIFT 3 /**< Shift value for MVP_LOOP1END */
+#define _MVP_INSTRCFG2_LOOP1END_MASK 0x8UL /**< Bit mask for MVP_LOOP1END */
+#define _MVP_INSTRCFG2_LOOP1END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP1END_DEFAULT (_MVP_INSTRCFG2_LOOP1END_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP2BEGIN (0x1UL << 4) /**< Loop Begin */
+#define _MVP_INSTRCFG2_LOOP2BEGIN_SHIFT 4 /**< Shift value for MVP_LOOP2BEGIN */
+#define _MVP_INSTRCFG2_LOOP2BEGIN_MASK 0x10UL /**< Bit mask for MVP_LOOP2BEGIN */
+#define _MVP_INSTRCFG2_LOOP2BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP2BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP2BEGIN_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP2END (0x1UL << 5) /**< Loop End */
+#define _MVP_INSTRCFG2_LOOP2END_SHIFT 5 /**< Shift value for MVP_LOOP2END */
+#define _MVP_INSTRCFG2_LOOP2END_MASK 0x20UL /**< Bit mask for MVP_LOOP2END */
+#define _MVP_INSTRCFG2_LOOP2END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP2END_DEFAULT (_MVP_INSTRCFG2_LOOP2END_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP3BEGIN (0x1UL << 6) /**< Loop Begin */
+#define _MVP_INSTRCFG2_LOOP3BEGIN_SHIFT 6 /**< Shift value for MVP_LOOP3BEGIN */
+#define _MVP_INSTRCFG2_LOOP3BEGIN_MASK 0x40UL /**< Bit mask for MVP_LOOP3BEGIN */
+#define _MVP_INSTRCFG2_LOOP3BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP3BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP3BEGIN_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP3END (0x1UL << 7) /**< Loop End */
+#define _MVP_INSTRCFG2_LOOP3END_SHIFT 7 /**< Shift value for MVP_LOOP3END */
+#define _MVP_INSTRCFG2_LOOP3END_MASK 0x80UL /**< Bit mask for MVP_LOOP3END */
+#define _MVP_INSTRCFG2_LOOP3END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP3END_DEFAULT (_MVP_INSTRCFG2_LOOP3END_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP4BEGIN (0x1UL << 8) /**< Loop Begin */
+#define _MVP_INSTRCFG2_LOOP4BEGIN_SHIFT 8 /**< Shift value for MVP_LOOP4BEGIN */
+#define _MVP_INSTRCFG2_LOOP4BEGIN_MASK 0x100UL /**< Bit mask for MVP_LOOP4BEGIN */
+#define _MVP_INSTRCFG2_LOOP4BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP4BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP4BEGIN_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP4END (0x1UL << 9) /**< Loop End */
+#define _MVP_INSTRCFG2_LOOP4END_SHIFT 9 /**< Shift value for MVP_LOOP4END */
+#define _MVP_INSTRCFG2_LOOP4END_MASK 0x200UL /**< Bit mask for MVP_LOOP4END */
+#define _MVP_INSTRCFG2_LOOP4END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP4END_DEFAULT (_MVP_INSTRCFG2_LOOP4END_DEFAULT << 9) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP5BEGIN (0x1UL << 10) /**< Loop Begin */
+#define _MVP_INSTRCFG2_LOOP5BEGIN_SHIFT 10 /**< Shift value for MVP_LOOP5BEGIN */
+#define _MVP_INSTRCFG2_LOOP5BEGIN_MASK 0x400UL /**< Bit mask for MVP_LOOP5BEGIN */
+#define _MVP_INSTRCFG2_LOOP5BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP5BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP5BEGIN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP5END (0x1UL << 11) /**< Loop End */
+#define _MVP_INSTRCFG2_LOOP5END_SHIFT 11 /**< Shift value for MVP_LOOP5END */
+#define _MVP_INSTRCFG2_LOOP5END_MASK 0x800UL /**< Bit mask for MVP_LOOP5END */
+#define _MVP_INSTRCFG2_LOOP5END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP5END_DEFAULT (_MVP_INSTRCFG2_LOOP5END_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP6BEGIN (0x1UL << 12) /**< Loop Begin */
+#define _MVP_INSTRCFG2_LOOP6BEGIN_SHIFT 12 /**< Shift value for MVP_LOOP6BEGIN */
+#define _MVP_INSTRCFG2_LOOP6BEGIN_MASK 0x1000UL /**< Bit mask for MVP_LOOP6BEGIN */
+#define _MVP_INSTRCFG2_LOOP6BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP6BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP6BEGIN_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP6END (0x1UL << 13) /**< Loop End */
+#define _MVP_INSTRCFG2_LOOP6END_SHIFT 13 /**< Shift value for MVP_LOOP6END */
+#define _MVP_INSTRCFG2_LOOP6END_MASK 0x2000UL /**< Bit mask for MVP_LOOP6END */
+#define _MVP_INSTRCFG2_LOOP6END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP6END_DEFAULT (_MVP_INSTRCFG2_LOOP6END_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP7BEGIN (0x1UL << 14) /**< Loop Begin */
+#define _MVP_INSTRCFG2_LOOP7BEGIN_SHIFT 14 /**< Shift value for MVP_LOOP7BEGIN */
+#define _MVP_INSTRCFG2_LOOP7BEGIN_MASK 0x4000UL /**< Bit mask for MVP_LOOP7BEGIN */
+#define _MVP_INSTRCFG2_LOOP7BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP7BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP7BEGIN_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP7END (0x1UL << 15) /**< Loop End */
+#define _MVP_INSTRCFG2_LOOP7END_SHIFT 15 /**< Shift value for MVP_LOOP7END */
+#define _MVP_INSTRCFG2_LOOP7END_MASK 0x8000UL /**< Bit mask for MVP_LOOP7END */
+#define _MVP_INSTRCFG2_LOOP7END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_LOOP7END_DEFAULT (_MVP_INSTRCFG2_LOOP7END_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_SHIFT 20 /**< Shift value for MVP_ALUOP */
+#define _MVP_INSTRCFG2_ALUOP_MASK 0x1FF00000UL /**< Bit mask for MVP_ALUOP */
+#define _MVP_INSTRCFG2_ALUOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_NOOP 0x00000000UL /**< Mode NOOP for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_CLEAR 0x00000001UL /**< Mode CLEAR for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_COPY 0x00000041UL /**< Mode COPY for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_SWAP 0x00000042UL /**< Mode SWAP for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_DBL 0x00000043UL /**< Mode DBL for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_FANA 0x00000044UL /**< Mode FANA for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_FANB 0x00000045UL /**< Mode FANB for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_RELU2 0x00000046UL /**< Mode RELU2 for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_NRELU2 0x00000047UL /**< Mode NRELU2 for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_INC2 0x00000048UL /**< Mode INC2 for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_DEC2 0x00000049UL /**< Mode DEC2 for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_ADDR 0x0000004AUL /**< Mode ADDR for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_MAX 0x0000004BUL /**< Mode MAX for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_MIN 0x0000004CUL /**< Mode MIN for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_RSQR2B 0x00000124UL /**< Mode RSQR2B for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_ADDC 0x0000014EUL /**< Mode ADDC for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_MAX2A 0x00000153UL /**< Mode MAX2A for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_MIN2A 0x00000154UL /**< Mode MIN2A for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_XREALC2 0x0000015EUL /**< Mode XREALC2 for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_XIMAGC2 0x0000015FUL /**< Mode XIMAGC2 for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_ADDR2B 0x00000161UL /**< Mode ADDR2B for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_MAX2B 0x00000162UL /**< Mode MAX2B for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_MIN2B 0x00000163UL /**< Mode MIN2B for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_MULC 0x0000018DUL /**< Mode MULC for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_MULR2A 0x00000197UL /**< Mode MULR2A for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_MULR2B 0x00000198UL /**< Mode MULR2B for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_ADDR4 0x0000019AUL /**< Mode ADDR4 for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_MAX4 0x0000019BUL /**< Mode MAX4 for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_MIN4 0x0000019CUL /**< Mode MIN4 for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_SQRMAGC2 0x0000019DUL /**< Mode SQRMAGC2 for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_PRELU2B 0x000001A0UL /**< Mode PRELU2B for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_MACC 0x000001CDUL /**< Mode MACC for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_AACC 0x000001CEUL /**< Mode AACC for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_ELU2A 0x000001CFUL /**< Mode ELU2A for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_ELU2B 0x000001D0UL /**< Mode ELU2B for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_IFR2A 0x000001D1UL /**< Mode IFR2A for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_IFR2B 0x000001D2UL /**< Mode IFR2B for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_MAXAC2 0x000001D3UL /**< Mode MAXAC2 for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_MINAC2 0x000001D4UL /**< Mode MINAC2 for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_CLIP2A 0x000001D5UL /**< Mode CLIP2A for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_CLIP2B 0x000001D6UL /**< Mode CLIP2B for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_MACR2A 0x000001D7UL /**< Mode MACR2A for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_MACR2B 0x000001D8UL /**< Mode MACR2B for MVP_INSTRCFG2 */
+#define _MVP_INSTRCFG2_ALUOP_IFC 0x000001D9UL /**< Mode IFC for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_DEFAULT (_MVP_INSTRCFG2_ALUOP_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_NOOP (_MVP_INSTRCFG2_ALUOP_NOOP << 20) /**< Shifted mode NOOP for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_CLEAR (_MVP_INSTRCFG2_ALUOP_CLEAR << 20) /**< Shifted mode CLEAR for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_COPY (_MVP_INSTRCFG2_ALUOP_COPY << 20) /**< Shifted mode COPY for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_SWAP (_MVP_INSTRCFG2_ALUOP_SWAP << 20) /**< Shifted mode SWAP for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_DBL (_MVP_INSTRCFG2_ALUOP_DBL << 20) /**< Shifted mode DBL for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_FANA (_MVP_INSTRCFG2_ALUOP_FANA << 20) /**< Shifted mode FANA for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_FANB (_MVP_INSTRCFG2_ALUOP_FANB << 20) /**< Shifted mode FANB for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_RELU2 (_MVP_INSTRCFG2_ALUOP_RELU2 << 20) /**< Shifted mode RELU2 for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_NRELU2 (_MVP_INSTRCFG2_ALUOP_NRELU2 << 20) /**< Shifted mode NRELU2 for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_INC2 (_MVP_INSTRCFG2_ALUOP_INC2 << 20) /**< Shifted mode INC2 for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_DEC2 (_MVP_INSTRCFG2_ALUOP_DEC2 << 20) /**< Shifted mode DEC2 for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_ADDR (_MVP_INSTRCFG2_ALUOP_ADDR << 20) /**< Shifted mode ADDR for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_MAX (_MVP_INSTRCFG2_ALUOP_MAX << 20) /**< Shifted mode MAX for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_MIN (_MVP_INSTRCFG2_ALUOP_MIN << 20) /**< Shifted mode MIN for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_RSQR2B (_MVP_INSTRCFG2_ALUOP_RSQR2B << 20) /**< Shifted mode RSQR2B for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_ADDC (_MVP_INSTRCFG2_ALUOP_ADDC << 20) /**< Shifted mode ADDC for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_MAX2A (_MVP_INSTRCFG2_ALUOP_MAX2A << 20) /**< Shifted mode MAX2A for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_MIN2A (_MVP_INSTRCFG2_ALUOP_MIN2A << 20) /**< Shifted mode MIN2A for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_XREALC2 (_MVP_INSTRCFG2_ALUOP_XREALC2 << 20) /**< Shifted mode XREALC2 for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_XIMAGC2 (_MVP_INSTRCFG2_ALUOP_XIMAGC2 << 20) /**< Shifted mode XIMAGC2 for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_ADDR2B (_MVP_INSTRCFG2_ALUOP_ADDR2B << 20) /**< Shifted mode ADDR2B for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_MAX2B (_MVP_INSTRCFG2_ALUOP_MAX2B << 20) /**< Shifted mode MAX2B for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_MIN2B (_MVP_INSTRCFG2_ALUOP_MIN2B << 20) /**< Shifted mode MIN2B for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_MULC (_MVP_INSTRCFG2_ALUOP_MULC << 20) /**< Shifted mode MULC for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_MULR2A (_MVP_INSTRCFG2_ALUOP_MULR2A << 20) /**< Shifted mode MULR2A for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_MULR2B (_MVP_INSTRCFG2_ALUOP_MULR2B << 20) /**< Shifted mode MULR2B for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_ADDR4 (_MVP_INSTRCFG2_ALUOP_ADDR4 << 20) /**< Shifted mode ADDR4 for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_MAX4 (_MVP_INSTRCFG2_ALUOP_MAX4 << 20) /**< Shifted mode MAX4 for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_MIN4 (_MVP_INSTRCFG2_ALUOP_MIN4 << 20) /**< Shifted mode MIN4 for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_SQRMAGC2 (_MVP_INSTRCFG2_ALUOP_SQRMAGC2 << 20) /**< Shifted mode SQRMAGC2 for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_PRELU2B (_MVP_INSTRCFG2_ALUOP_PRELU2B << 20) /**< Shifted mode PRELU2B for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_MACC (_MVP_INSTRCFG2_ALUOP_MACC << 20) /**< Shifted mode MACC for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_AACC (_MVP_INSTRCFG2_ALUOP_AACC << 20) /**< Shifted mode AACC for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_ELU2A (_MVP_INSTRCFG2_ALUOP_ELU2A << 20) /**< Shifted mode ELU2A for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_ELU2B (_MVP_INSTRCFG2_ALUOP_ELU2B << 20) /**< Shifted mode ELU2B for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_IFR2A (_MVP_INSTRCFG2_ALUOP_IFR2A << 20) /**< Shifted mode IFR2A for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_IFR2B (_MVP_INSTRCFG2_ALUOP_IFR2B << 20) /**< Shifted mode IFR2B for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_MAXAC2 (_MVP_INSTRCFG2_ALUOP_MAXAC2 << 20) /**< Shifted mode MAXAC2 for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_MINAC2 (_MVP_INSTRCFG2_ALUOP_MINAC2 << 20) /**< Shifted mode MINAC2 for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_CLIP2A (_MVP_INSTRCFG2_ALUOP_CLIP2A << 20) /**< Shifted mode CLIP2A for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_CLIP2B (_MVP_INSTRCFG2_ALUOP_CLIP2B << 20) /**< Shifted mode CLIP2B for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_MACR2A (_MVP_INSTRCFG2_ALUOP_MACR2A << 20) /**< Shifted mode MACR2A for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_MACR2B (_MVP_INSTRCFG2_ALUOP_MACR2B << 20) /**< Shifted mode MACR2B for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ALUOP_IFC (_MVP_INSTRCFG2_ALUOP_IFC << 20) /**< Shifted mode IFC for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ENDPROG (0x1UL << 31) /**< End of Program */
+#define _MVP_INSTRCFG2_ENDPROG_SHIFT 31 /**< Shift value for MVP_ENDPROG */
+#define _MVP_INSTRCFG2_ENDPROG_MASK 0x80000000UL /**< Bit mask for MVP_ENDPROG */
+#define _MVP_INSTRCFG2_ENDPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */
+#define MVP_INSTRCFG2_ENDPROG_DEFAULT (_MVP_INSTRCFG2_ENDPROG_DEFAULT << 31) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */
+
+/* Bit fields for MVP CMD */
+#define _MVP_CMD_RESETVALUE 0x00000000UL /**< Default value for MVP_CMD */
+#define _MVP_CMD_MASK 0x0000000FUL /**< Mask for MVP_CMD */
+#define MVP_CMD_START (0x1UL << 0) /**< Start Command */
+#define _MVP_CMD_START_SHIFT 0 /**< Shift value for MVP_START */
+#define _MVP_CMD_START_MASK 0x1UL /**< Bit mask for MVP_START */
+#define _MVP_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */
+#define MVP_CMD_START_DEFAULT (_MVP_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_CMD */
+#define MVP_CMD_HALT (0x1UL << 1) /**< Halt Command */
+#define _MVP_CMD_HALT_SHIFT 1 /**< Shift value for MVP_HALT */
+#define _MVP_CMD_HALT_MASK 0x2UL /**< Bit mask for MVP_HALT */
+#define _MVP_CMD_HALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */
+#define MVP_CMD_HALT_DEFAULT (_MVP_CMD_HALT_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_CMD */
+#define MVP_CMD_STEP (0x1UL << 2) /**< Step Command */
+#define _MVP_CMD_STEP_SHIFT 2 /**< Shift value for MVP_STEP */
+#define _MVP_CMD_STEP_MASK 0x4UL /**< Bit mask for MVP_STEP */
+#define _MVP_CMD_STEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */
+#define MVP_CMD_STEP_DEFAULT (_MVP_CMD_STEP_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_CMD */
+#define MVP_CMD_INIT (0x1UL << 3) /**< Initialization Command/Qualifier */
+#define _MVP_CMD_INIT_SHIFT 3 /**< Shift value for MVP_INIT */
+#define _MVP_CMD_INIT_MASK 0x8UL /**< Bit mask for MVP_INIT */
+#define _MVP_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */
+#define MVP_CMD_INIT_DEFAULT (_MVP_CMD_INIT_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_CMD */
+
+/* Bit fields for MVP DEBUGEN */
+#define _MVP_DEBUGEN_RESETVALUE 0x00000000UL /**< Default value for MVP_DEBUGEN */
+#define _MVP_DEBUGEN_MASK 0x7003FDFEUL /**< Mask for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTLOOP0DONE (0x1UL << 1) /**< Enable Breakpoint on Loop Done */
+#define _MVP_DEBUGEN_BKPTLOOP0DONE_SHIFT 1 /**< Shift value for MVP_BKPTLOOP0DONE */
+#define _MVP_DEBUGEN_BKPTLOOP0DONE_MASK 0x2UL /**< Bit mask for MVP_BKPTLOOP0DONE */
+#define _MVP_DEBUGEN_BKPTLOOP0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTLOOP0DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP0DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTLOOP1DONE (0x1UL << 2) /**< Enable Breakpoint on Loop Done */
+#define _MVP_DEBUGEN_BKPTLOOP1DONE_SHIFT 2 /**< Shift value for MVP_BKPTLOOP1DONE */
+#define _MVP_DEBUGEN_BKPTLOOP1DONE_MASK 0x4UL /**< Bit mask for MVP_BKPTLOOP1DONE */
+#define _MVP_DEBUGEN_BKPTLOOP1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTLOOP1DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP1DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTLOOP2DONE (0x1UL << 3) /**< Enable Breakpoint on Loop Done */
+#define _MVP_DEBUGEN_BKPTLOOP2DONE_SHIFT 3 /**< Shift value for MVP_BKPTLOOP2DONE */
+#define _MVP_DEBUGEN_BKPTLOOP2DONE_MASK 0x8UL /**< Bit mask for MVP_BKPTLOOP2DONE */
+#define _MVP_DEBUGEN_BKPTLOOP2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTLOOP2DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP2DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTLOOP3DONE (0x1UL << 4) /**< Enable Breakpoint on Loop Done */
+#define _MVP_DEBUGEN_BKPTLOOP3DONE_SHIFT 4 /**< Shift value for MVP_BKPTLOOP3DONE */
+#define _MVP_DEBUGEN_BKPTLOOP3DONE_MASK 0x10UL /**< Bit mask for MVP_BKPTLOOP3DONE */
+#define _MVP_DEBUGEN_BKPTLOOP3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTLOOP3DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP3DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTLOOP4DONE (0x1UL << 5) /**< Enable Breakpoint on Loop Done */
+#define _MVP_DEBUGEN_BKPTLOOP4DONE_SHIFT 5 /**< Shift value for MVP_BKPTLOOP4DONE */
+#define _MVP_DEBUGEN_BKPTLOOP4DONE_MASK 0x20UL /**< Bit mask for MVP_BKPTLOOP4DONE */
+#define _MVP_DEBUGEN_BKPTLOOP4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTLOOP4DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP4DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTLOOP5DONE (0x1UL << 6) /**< Enable Breakpoint on Loop Done */
+#define _MVP_DEBUGEN_BKPTLOOP5DONE_SHIFT 6 /**< Shift value for MVP_BKPTLOOP5DONE */
+#define _MVP_DEBUGEN_BKPTLOOP5DONE_MASK 0x40UL /**< Bit mask for MVP_BKPTLOOP5DONE */
+#define _MVP_DEBUGEN_BKPTLOOP5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTLOOP5DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP5DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTLOOP6DONE (0x1UL << 7) /**< Enable Breakpoint on Loop Done */
+#define _MVP_DEBUGEN_BKPTLOOP6DONE_SHIFT 7 /**< Shift value for MVP_BKPTLOOP6DONE */
+#define _MVP_DEBUGEN_BKPTLOOP6DONE_MASK 0x80UL /**< Bit mask for MVP_BKPTLOOP6DONE */
+#define _MVP_DEBUGEN_BKPTLOOP6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTLOOP6DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP6DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTLOOP7DONE (0x1UL << 8) /**< Enable Breakpoint on Loop Done */
+#define _MVP_DEBUGEN_BKPTLOOP7DONE_SHIFT 8 /**< Shift value for MVP_BKPTLOOP7DONE */
+#define _MVP_DEBUGEN_BKPTLOOP7DONE_MASK 0x100UL /**< Bit mask for MVP_BKPTLOOP7DONE */
+#define _MVP_DEBUGEN_BKPTLOOP7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTLOOP7DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP7DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTALUNAN (0x1UL << 10) /**< Enable Breakpoint on ALUNAN */
+#define _MVP_DEBUGEN_BKPTALUNAN_SHIFT 10 /**< Shift value for MVP_BKPTALUNAN */
+#define _MVP_DEBUGEN_BKPTALUNAN_MASK 0x400UL /**< Bit mask for MVP_BKPTALUNAN */
+#define _MVP_DEBUGEN_BKPTALUNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTALUNAN_DEFAULT (_MVP_DEBUGEN_BKPTALUNAN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTR0POSREAL (0x1UL << 11) /**< Enable Breakpoint on R0POSREAL */
+#define _MVP_DEBUGEN_BKPTR0POSREAL_SHIFT 11 /**< Shift value for MVP_BKPTR0POSREAL */
+#define _MVP_DEBUGEN_BKPTR0POSREAL_MASK 0x800UL /**< Bit mask for MVP_BKPTR0POSREAL */
+#define _MVP_DEBUGEN_BKPTR0POSREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTR0POSREAL_DEFAULT (_MVP_DEBUGEN_BKPTR0POSREAL_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTALUOF (0x1UL << 12) /**< Enable Breakpoint on ALUOF */
+#define _MVP_DEBUGEN_BKPTALUOF_SHIFT 12 /**< Shift value for MVP_BKPTALUOF */
+#define _MVP_DEBUGEN_BKPTALUOF_MASK 0x1000UL /**< Bit mask for MVP_BKPTALUOF */
+#define _MVP_DEBUGEN_BKPTALUOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTALUOF_DEFAULT (_MVP_DEBUGEN_BKPTALUOF_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTALUUF (0x1UL << 13) /**< Enable Breakpoint on ALUUF */
+#define _MVP_DEBUGEN_BKPTALUUF_SHIFT 13 /**< Shift value for MVP_BKPTALUUF */
+#define _MVP_DEBUGEN_BKPTALUUF_MASK 0x2000UL /**< Bit mask for MVP_BKPTALUUF */
+#define _MVP_DEBUGEN_BKPTALUUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTALUUF_DEFAULT (_MVP_DEBUGEN_BKPTALUUF_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTSTORECONVERTOF (0x1UL << 14) /**< Enable Breakpoint on STORECONVERTOF */
+#define _MVP_DEBUGEN_BKPTSTORECONVERTOF_SHIFT 14 /**< Shift value for MVP_BKPTSTORECONVERTOF */
+#define _MVP_DEBUGEN_BKPTSTORECONVERTOF_MASK 0x4000UL /**< Bit mask for MVP_BKPTSTORECONVERTOF */
+#define _MVP_DEBUGEN_BKPTSTORECONVERTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTSTORECONVERTOF_DEFAULT (_MVP_DEBUGEN_BKPTSTORECONVERTOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTSTORECONVERTUF (0x1UL << 15) /**< Enable Breakpoint on STORECONVERTUF */
+#define _MVP_DEBUGEN_BKPTSTORECONVERTUF_SHIFT 15 /**< Shift value for MVP_BKPTSTORECONVERTUF */
+#define _MVP_DEBUGEN_BKPTSTORECONVERTUF_MASK 0x8000UL /**< Bit mask for MVP_BKPTSTORECONVERTUF */
+#define _MVP_DEBUGEN_BKPTSTORECONVERTUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTSTORECONVERTUF_DEFAULT (_MVP_DEBUGEN_BKPTSTORECONVERTUF_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTSTORECONVERTINF (0x1UL << 16) /**< Enable Breakpoint on STORECONVERTINF */
+#define _MVP_DEBUGEN_BKPTSTORECONVERTINF_SHIFT 16 /**< Shift value for MVP_BKPTSTORECONVERTINF */
+#define _MVP_DEBUGEN_BKPTSTORECONVERTINF_MASK 0x10000UL /**< Bit mask for MVP_BKPTSTORECONVERTINF */
+#define _MVP_DEBUGEN_BKPTSTORECONVERTINF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTSTORECONVERTINF_DEFAULT (_MVP_DEBUGEN_BKPTSTORECONVERTINF_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTSTORECONVERTNAN (0x1UL << 17) /**< Enable Breakpoint on STORECONVERTNAN */
+#define _MVP_DEBUGEN_BKPTSTORECONVERTNAN_SHIFT 17 /**< Shift value for MVP_BKPTSTORECONVERTNAN */
+#define _MVP_DEBUGEN_BKPTSTORECONVERTNAN_MASK 0x20000UL /**< Bit mask for MVP_BKPTSTORECONVERTNAN */
+#define _MVP_DEBUGEN_BKPTSTORECONVERTNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_BKPTSTORECONVERTNAN_DEFAULT (_MVP_DEBUGEN_BKPTSTORECONVERTNAN_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_DEBUGSTEPCNTEN (0x1UL << 28) /**< Debug Step Count Enable */
+#define _MVP_DEBUGEN_DEBUGSTEPCNTEN_SHIFT 28 /**< Shift value for MVP_DEBUGSTEPCNTEN */
+#define _MVP_DEBUGEN_DEBUGSTEPCNTEN_MASK 0x10000000UL /**< Bit mask for MVP_DEBUGSTEPCNTEN */
+#define _MVP_DEBUGEN_DEBUGSTEPCNTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_DEBUGSTEPCNTEN_DEFAULT (_MVP_DEBUGEN_DEBUGSTEPCNTEN_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_DEBUGBKPTALLEN (0x1UL << 29) /**< Trigger Breakpoint when ALL conditions match*/
+#define _MVP_DEBUGEN_DEBUGBKPTALLEN_SHIFT 29 /**< Shift value for MVP_DEBUGBKPTALLEN */
+#define _MVP_DEBUGEN_DEBUGBKPTALLEN_MASK 0x20000000UL /**< Bit mask for MVP_DEBUGBKPTALLEN */
+#define _MVP_DEBUGEN_DEBUGBKPTALLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_DEBUGBKPTALLEN_DEFAULT (_MVP_DEBUGEN_DEBUGBKPTALLEN_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_DEBUGBKPTANYEN (0x1UL << 30) /**< Enable Breakpoint when ANY conditions match */
+#define _MVP_DEBUGEN_DEBUGBKPTANYEN_SHIFT 30 /**< Shift value for MVP_DEBUGBKPTANYEN */
+#define _MVP_DEBUGEN_DEBUGBKPTANYEN_MASK 0x40000000UL /**< Bit mask for MVP_DEBUGBKPTANYEN */
+#define _MVP_DEBUGEN_DEBUGBKPTANYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */
+#define MVP_DEBUGEN_DEBUGBKPTANYEN_DEFAULT (_MVP_DEBUGEN_DEBUGBKPTANYEN_DEFAULT << 30) /**< Shifted mode DEFAULT for MVP_DEBUGEN */
+
+/* Bit fields for MVP DEBUGSTEPCNT */
+#define _MVP_DEBUGSTEPCNT_RESETVALUE 0x00000000UL /**< Default value for MVP_DEBUGSTEPCNT */
+#define _MVP_DEBUGSTEPCNT_MASK 0x00FFFFFFUL /**< Mask for MVP_DEBUGSTEPCNT */
+#define _MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_SHIFT 0 /**< Shift value for MVP_DEBUGSTEPCNT */
+#define _MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_MASK 0xFFFFFFUL /**< Bit mask for MVP_DEBUGSTEPCNT */
+#define _MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGSTEPCNT */
+#define MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_DEFAULT (_MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_DEBUGSTEPCNT */
+
+/** @} End of group EFR32MG24_MVP_BitFields */
+/** @} End of group EFR32MG24_MVP */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_MVP_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_pcnt.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_pcnt.h
new file mode 100644
index 00000000..e2f2efcf
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_pcnt.h
@@ -0,0 +1,482 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 PCNT register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_PCNT_H
+#define EFR32MG24_PCNT_H
+#define PCNT_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_PCNT PCNT
+ * @{
+ * @brief EFR32MG24 PCNT Register Declaration.
+ *****************************************************************************/
+
+/** PCNT Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IP version ID */
+ __IOM uint32_t EN; /**< Module Enable Register */
+ __IOM uint32_t SWRST; /**< Software Reset Register */
+ __IOM uint32_t CFG; /**< Configuration Register */
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IOM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IM uint32_t CNT; /**< Counter Value Register */
+ __IM uint32_t AUXCNT; /**< Auxiliary Counter Value Register */
+ __IOM uint32_t TOP; /**< Top Value Register */
+ __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */
+ __IOM uint32_t OVSCTRL; /**< Oversampling Control Register */
+ __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
+ __IOM uint32_t LOCK; /**< Configuration Lock Register */
+ uint32_t RESERVED0[1008U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP version ID */
+ __IOM uint32_t EN_SET; /**< Module Enable Register */
+ __IOM uint32_t SWRST_SET; /**< Software Reset Register */
+ __IOM uint32_t CFG_SET; /**< Configuration Register */
+ __IOM uint32_t CTRL_SET; /**< Control Register */
+ __IOM uint32_t CMD_SET; /**< Command Register */
+ __IM uint32_t STATUS_SET; /**< Status Register */
+ __IOM uint32_t IF_SET; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
+ __IM uint32_t CNT_SET; /**< Counter Value Register */
+ __IM uint32_t AUXCNT_SET; /**< Auxiliary Counter Value Register */
+ __IOM uint32_t TOP_SET; /**< Top Value Register */
+ __IOM uint32_t TOPB_SET; /**< Counter Top Value Buffer Register */
+ __IOM uint32_t OVSCTRL_SET; /**< Oversampling Control Register */
+ __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */
+ __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */
+ uint32_t RESERVED1[1008U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP version ID */
+ __IOM uint32_t EN_CLR; /**< Module Enable Register */
+ __IOM uint32_t SWRST_CLR; /**< Software Reset Register */
+ __IOM uint32_t CFG_CLR; /**< Configuration Register */
+ __IOM uint32_t CTRL_CLR; /**< Control Register */
+ __IOM uint32_t CMD_CLR; /**< Command Register */
+ __IM uint32_t STATUS_CLR; /**< Status Register */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
+ __IM uint32_t CNT_CLR; /**< Counter Value Register */
+ __IM uint32_t AUXCNT_CLR; /**< Auxiliary Counter Value Register */
+ __IOM uint32_t TOP_CLR; /**< Top Value Register */
+ __IOM uint32_t TOPB_CLR; /**< Counter Top Value Buffer Register */
+ __IOM uint32_t OVSCTRL_CLR; /**< Oversampling Control Register */
+ __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */
+ __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */
+ uint32_t RESERVED2[1008U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP version ID */
+ __IOM uint32_t EN_TGL; /**< Module Enable Register */
+ __IOM uint32_t SWRST_TGL; /**< Software Reset Register */
+ __IOM uint32_t CFG_TGL; /**< Configuration Register */
+ __IOM uint32_t CTRL_TGL; /**< Control Register */
+ __IOM uint32_t CMD_TGL; /**< Command Register */
+ __IM uint32_t STATUS_TGL; /**< Status Register */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
+ __IM uint32_t CNT_TGL; /**< Counter Value Register */
+ __IM uint32_t AUXCNT_TGL; /**< Auxiliary Counter Value Register */
+ __IOM uint32_t TOP_TGL; /**< Top Value Register */
+ __IOM uint32_t TOPB_TGL; /**< Counter Top Value Buffer Register */
+ __IOM uint32_t OVSCTRL_TGL; /**< Oversampling Control Register */
+ __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */
+ __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */
+} PCNT_TypeDef;
+/** @} End of group EFR32MG24_PCNT */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_PCNT
+ * @{
+ * @defgroup EFR32MG24_PCNT_BitFields PCNT Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for PCNT IPVERSION */
+#define _PCNT_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for PCNT_IPVERSION */
+#define _PCNT_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PCNT_IPVERSION */
+#define _PCNT_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PCNT_IPVERSION */
+#define _PCNT_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PCNT_IPVERSION */
+#define _PCNT_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for PCNT_IPVERSION */
+#define PCNT_IPVERSION_IPVERSION_DEFAULT (_PCNT_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IPVERSION */
+
+/* Bit fields for PCNT EN */
+#define _PCNT_EN_RESETVALUE 0x00000000UL /**< Default value for PCNT_EN */
+#define _PCNT_EN_MASK 0x00000003UL /**< Mask for PCNT_EN */
+#define PCNT_EN_EN (0x1UL << 0) /**< PCNT Module Enable */
+#define _PCNT_EN_EN_SHIFT 0 /**< Shift value for PCNT_EN */
+#define _PCNT_EN_EN_MASK 0x1UL /**< Bit mask for PCNT_EN */
+#define _PCNT_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_EN */
+#define PCNT_EN_EN_DEFAULT (_PCNT_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_EN */
+#define PCNT_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */
+#define _PCNT_EN_DISABLING_SHIFT 1 /**< Shift value for PCNT_DISABLING */
+#define _PCNT_EN_DISABLING_MASK 0x2UL /**< Bit mask for PCNT_DISABLING */
+#define _PCNT_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_EN */
+#define PCNT_EN_DISABLING_DEFAULT (_PCNT_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_EN */
+
+/* Bit fields for PCNT SWRST */
+#define _PCNT_SWRST_RESETVALUE 0x00000000UL /**< Default value for PCNT_SWRST */
+#define _PCNT_SWRST_MASK 0x00000003UL /**< Mask for PCNT_SWRST */
+#define PCNT_SWRST_SWRST (0x1UL << 0) /**< Software reset command */
+#define _PCNT_SWRST_SWRST_SHIFT 0 /**< Shift value for PCNT_SWRST */
+#define _PCNT_SWRST_SWRST_MASK 0x1UL /**< Bit mask for PCNT_SWRST */
+#define _PCNT_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SWRST */
+#define PCNT_SWRST_SWRST_DEFAULT (_PCNT_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_SWRST */
+#define PCNT_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */
+#define _PCNT_SWRST_RESETTING_SHIFT 1 /**< Shift value for PCNT_RESETTING */
+#define _PCNT_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for PCNT_RESETTING */
+#define _PCNT_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SWRST */
+#define PCNT_SWRST_RESETTING_DEFAULT (_PCNT_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_SWRST */
+
+/* Bit fields for PCNT CFG */
+#define _PCNT_CFG_RESETVALUE 0x00000000UL /**< Default value for PCNT_CFG */
+#define _PCNT_CFG_MASK 0x00000377UL /**< Mask for PCNT_CFG */
+#define _PCNT_CFG_MODE_SHIFT 0 /**< Shift value for PCNT_MODE */
+#define _PCNT_CFG_MODE_MASK 0x7UL /**< Bit mask for PCNT_MODE */
+#define _PCNT_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */
+#define _PCNT_CFG_MODE_OVSSINGLE 0x00000000UL /**< Mode OVSSINGLE for PCNT_CFG */
+#define _PCNT_CFG_MODE_EXTCLKSINGLE 0x00000001UL /**< Mode EXTCLKSINGLE for PCNT_CFG */
+#define _PCNT_CFG_MODE_EXTCLKQUAD 0x00000002UL /**< Mode EXTCLKQUAD for PCNT_CFG */
+#define _PCNT_CFG_MODE_OVSQUAD1X 0x00000003UL /**< Mode OVSQUAD1X for PCNT_CFG */
+#define _PCNT_CFG_MODE_OVSQUAD2X 0x00000004UL /**< Mode OVSQUAD2X for PCNT_CFG */
+#define _PCNT_CFG_MODE_OVSQUAD4X 0x00000005UL /**< Mode OVSQUAD4X for PCNT_CFG */
+#define PCNT_CFG_MODE_DEFAULT (_PCNT_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CFG */
+#define PCNT_CFG_MODE_OVSSINGLE (_PCNT_CFG_MODE_OVSSINGLE << 0) /**< Shifted mode OVSSINGLE for PCNT_CFG */
+#define PCNT_CFG_MODE_EXTCLKSINGLE (_PCNT_CFG_MODE_EXTCLKSINGLE << 0) /**< Shifted mode EXTCLKSINGLE for PCNT_CFG */
+#define PCNT_CFG_MODE_EXTCLKQUAD (_PCNT_CFG_MODE_EXTCLKQUAD << 0) /**< Shifted mode EXTCLKQUAD for PCNT_CFG */
+#define PCNT_CFG_MODE_OVSQUAD1X (_PCNT_CFG_MODE_OVSQUAD1X << 0) /**< Shifted mode OVSQUAD1X for PCNT_CFG */
+#define PCNT_CFG_MODE_OVSQUAD2X (_PCNT_CFG_MODE_OVSQUAD2X << 0) /**< Shifted mode OVSQUAD2X for PCNT_CFG */
+#define PCNT_CFG_MODE_OVSQUAD4X (_PCNT_CFG_MODE_OVSQUAD4X << 0) /**< Shifted mode OVSQUAD4X for PCNT_CFG */
+#define PCNT_CFG_DEBUGHALT (0x1UL << 4) /**< Debug Mode Halt Enable */
+#define _PCNT_CFG_DEBUGHALT_SHIFT 4 /**< Shift value for PCNT_DEBUGHALT */
+#define _PCNT_CFG_DEBUGHALT_MASK 0x10UL /**< Bit mask for PCNT_DEBUGHALT */
+#define _PCNT_CFG_DEBUGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */
+#define _PCNT_CFG_DEBUGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for PCNT_CFG */
+#define _PCNT_CFG_DEBUGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for PCNT_CFG */
+#define PCNT_CFG_DEBUGHALT_DEFAULT (_PCNT_CFG_DEBUGHALT_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CFG */
+#define PCNT_CFG_DEBUGHALT_DISABLE (_PCNT_CFG_DEBUGHALT_DISABLE << 4) /**< Shifted mode DISABLE for PCNT_CFG */
+#define PCNT_CFG_DEBUGHALT_ENABLE (_PCNT_CFG_DEBUGHALT_ENABLE << 4) /**< Shifted mode ENABLE for PCNT_CFG */
+#define PCNT_CFG_FILTEN (0x1UL << 5) /**< Enable Digital Pulse Width Filter */
+#define _PCNT_CFG_FILTEN_SHIFT 5 /**< Shift value for PCNT_FILTEN */
+#define _PCNT_CFG_FILTEN_MASK 0x20UL /**< Bit mask for PCNT_FILTEN */
+#define _PCNT_CFG_FILTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */
+#define PCNT_CFG_FILTEN_DEFAULT (_PCNT_CFG_FILTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_CFG */
+#define PCNT_CFG_HYST (0x1UL << 6) /**< Enable Hysteresis */
+#define _PCNT_CFG_HYST_SHIFT 6 /**< Shift value for PCNT_HYST */
+#define _PCNT_CFG_HYST_MASK 0x40UL /**< Bit mask for PCNT_HYST */
+#define _PCNT_CFG_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */
+#define PCNT_CFG_HYST_DEFAULT (_PCNT_CFG_HYST_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_CFG */
+#define PCNT_CFG_S0PRSEN (0x1UL << 8) /**< S0IN PRS Enable */
+#define _PCNT_CFG_S0PRSEN_SHIFT 8 /**< Shift value for PCNT_S0PRSEN */
+#define _PCNT_CFG_S0PRSEN_MASK 0x100UL /**< Bit mask for PCNT_S0PRSEN */
+#define _PCNT_CFG_S0PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */
+#define PCNT_CFG_S0PRSEN_DEFAULT (_PCNT_CFG_S0PRSEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_CFG */
+#define PCNT_CFG_S1PRSEN (0x1UL << 9) /**< S1IN PRS Enable */
+#define _PCNT_CFG_S1PRSEN_SHIFT 9 /**< Shift value for PCNT_S1PRSEN */
+#define _PCNT_CFG_S1PRSEN_MASK 0x200UL /**< Bit mask for PCNT_S1PRSEN */
+#define _PCNT_CFG_S1PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */
+#define PCNT_CFG_S1PRSEN_DEFAULT (_PCNT_CFG_S1PRSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PCNT_CFG */
+
+/* Bit fields for PCNT CTRL */
+#define _PCNT_CTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_CTRL */
+#define _PCNT_CTRL_MASK 0x000000F7UL /**< Mask for PCNT_CTRL */
+#define PCNT_CTRL_S1CDIR (0x1UL << 0) /**< Count Direction Determined By S1 */
+#define _PCNT_CTRL_S1CDIR_SHIFT 0 /**< Shift value for PCNT_S1CDIR */
+#define _PCNT_CTRL_S1CDIR_MASK 0x1UL /**< Bit mask for PCNT_S1CDIR */
+#define _PCNT_CTRL_S1CDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_S1CDIR_DEFAULT (_PCNT_CTRL_S1CDIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_CNTDIR (0x1UL << 1) /**< Non-Quadrature Mode Counter Direction Co */
+#define _PCNT_CTRL_CNTDIR_SHIFT 1 /**< Shift value for PCNT_CNTDIR */
+#define _PCNT_CTRL_CNTDIR_MASK 0x2UL /**< Bit mask for PCNT_CNTDIR */
+#define _PCNT_CTRL_CNTDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_CNTDIR_UP 0x00000000UL /**< Mode UP for PCNT_CTRL */
+#define _PCNT_CTRL_CNTDIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_CTRL */
+#define PCNT_CTRL_CNTDIR_DEFAULT (_PCNT_CTRL_CNTDIR_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_CNTDIR_UP (_PCNT_CTRL_CNTDIR_UP << 1) /**< Shifted mode UP for PCNT_CTRL */
+#define PCNT_CTRL_CNTDIR_DOWN (_PCNT_CTRL_CNTDIR_DOWN << 1) /**< Shifted mode DOWN for PCNT_CTRL */
+#define PCNT_CTRL_EDGE (0x1UL << 2) /**< Edge Select */
+#define _PCNT_CTRL_EDGE_SHIFT 2 /**< Shift value for PCNT_EDGE */
+#define _PCNT_CTRL_EDGE_MASK 0x4UL /**< Bit mask for PCNT_EDGE */
+#define _PCNT_CTRL_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_EDGE_POS 0x00000000UL /**< Mode POS for PCNT_CTRL */
+#define _PCNT_CTRL_EDGE_NEG 0x00000001UL /**< Mode NEG for PCNT_CTRL */
+#define PCNT_CTRL_EDGE_DEFAULT (_PCNT_CTRL_EDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_EDGE_POS (_PCNT_CTRL_EDGE_POS << 2) /**< Shifted mode POS for PCNT_CTRL */
+#define PCNT_CTRL_EDGE_NEG (_PCNT_CTRL_EDGE_NEG << 2) /**< Shifted mode NEG for PCNT_CTRL */
+#define _PCNT_CTRL_CNTEV_SHIFT 4 /**< Shift value for PCNT_CNTEV */
+#define _PCNT_CTRL_CNTEV_MASK 0x30UL /**< Bit mask for PCNT_CNTEV */
+#define _PCNT_CTRL_CNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_CNTEV_BOTH 0x00000000UL /**< Mode BOTH for PCNT_CTRL */
+#define _PCNT_CTRL_CNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */
+#define _PCNT_CTRL_CNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */
+#define PCNT_CTRL_CNTEV_DEFAULT (_PCNT_CTRL_CNTEV_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_CNTEV_BOTH (_PCNT_CTRL_CNTEV_BOTH << 4) /**< Shifted mode BOTH for PCNT_CTRL */
+#define PCNT_CTRL_CNTEV_UP (_PCNT_CTRL_CNTEV_UP << 4) /**< Shifted mode UP for PCNT_CTRL */
+#define PCNT_CTRL_CNTEV_DOWN (_PCNT_CTRL_CNTEV_DOWN << 4) /**< Shifted mode DOWN for PCNT_CTRL */
+#define _PCNT_CTRL_AUXCNTEV_SHIFT 6 /**< Shift value for PCNT_AUXCNTEV */
+#define _PCNT_CTRL_AUXCNTEV_MASK 0xC0UL /**< Bit mask for PCNT_AUXCNTEV */
+#define _PCNT_CTRL_AUXCNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
+#define _PCNT_CTRL_AUXCNTEV_BOTH 0x00000000UL /**< Mode BOTH for PCNT_CTRL */
+#define _PCNT_CTRL_AUXCNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */
+#define _PCNT_CTRL_AUXCNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */
+#define PCNT_CTRL_AUXCNTEV_DEFAULT (_PCNT_CTRL_AUXCNTEV_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_CTRL */
+#define PCNT_CTRL_AUXCNTEV_BOTH (_PCNT_CTRL_AUXCNTEV_BOTH << 6) /**< Shifted mode BOTH for PCNT_CTRL */
+#define PCNT_CTRL_AUXCNTEV_UP (_PCNT_CTRL_AUXCNTEV_UP << 6) /**< Shifted mode UP for PCNT_CTRL */
+#define PCNT_CTRL_AUXCNTEV_DOWN (_PCNT_CTRL_AUXCNTEV_DOWN << 6) /**< Shifted mode DOWN for PCNT_CTRL */
+
+/* Bit fields for PCNT CMD */
+#define _PCNT_CMD_RESETVALUE 0x00000000UL /**< Default value for PCNT_CMD */
+#define _PCNT_CMD_MASK 0x00000F17UL /**< Mask for PCNT_CMD */
+#define PCNT_CMD_CORERST (0x1UL << 0) /**< PCNT Clock Domain Reset */
+#define _PCNT_CMD_CORERST_SHIFT 0 /**< Shift value for PCNT_CORERST */
+#define _PCNT_CMD_CORERST_MASK 0x1UL /**< Bit mask for PCNT_CORERST */
+#define _PCNT_CMD_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */
+#define PCNT_CMD_CORERST_DEFAULT (_PCNT_CMD_CORERST_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CMD */
+#define PCNT_CMD_CNTRST (0x1UL << 1) /**< CNT Reset */
+#define _PCNT_CMD_CNTRST_SHIFT 1 /**< Shift value for PCNT_CNTRST */
+#define _PCNT_CMD_CNTRST_MASK 0x2UL /**< Bit mask for PCNT_CNTRST */
+#define _PCNT_CMD_CNTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */
+#define PCNT_CMD_CNTRST_DEFAULT (_PCNT_CMD_CNTRST_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CMD */
+#define PCNT_CMD_AUXCNTRST (0x1UL << 2) /**< AUXCNT Reset */
+#define _PCNT_CMD_AUXCNTRST_SHIFT 2 /**< Shift value for PCNT_AUXCNTRST */
+#define _PCNT_CMD_AUXCNTRST_MASK 0x4UL /**< Bit mask for PCNT_AUXCNTRST */
+#define _PCNT_CMD_AUXCNTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */
+#define PCNT_CMD_AUXCNTRST_DEFAULT (_PCNT_CMD_AUXCNTRST_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_CMD */
+#define PCNT_CMD_LCNTIM (0x1UL << 4) /**< Load CNT Immediately */
+#define _PCNT_CMD_LCNTIM_SHIFT 4 /**< Shift value for PCNT_LCNTIM */
+#define _PCNT_CMD_LCNTIM_MASK 0x10UL /**< Bit mask for PCNT_LCNTIM */
+#define _PCNT_CMD_LCNTIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */
+#define PCNT_CMD_LCNTIM_DEFAULT (_PCNT_CMD_LCNTIM_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CMD */
+#define PCNT_CMD_STARTCNT (0x1UL << 8) /**< Start Main Counter */
+#define _PCNT_CMD_STARTCNT_SHIFT 8 /**< Shift value for PCNT_STARTCNT */
+#define _PCNT_CMD_STARTCNT_MASK 0x100UL /**< Bit mask for PCNT_STARTCNT */
+#define _PCNT_CMD_STARTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */
+#define PCNT_CMD_STARTCNT_DEFAULT (_PCNT_CMD_STARTCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_CMD */
+#define PCNT_CMD_STARTAUXCNT (0x1UL << 9) /**< Start Aux Counter */
+#define _PCNT_CMD_STARTAUXCNT_SHIFT 9 /**< Shift value for PCNT_STARTAUXCNT */
+#define _PCNT_CMD_STARTAUXCNT_MASK 0x200UL /**< Bit mask for PCNT_STARTAUXCNT */
+#define _PCNT_CMD_STARTAUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */
+#define PCNT_CMD_STARTAUXCNT_DEFAULT (_PCNT_CMD_STARTAUXCNT_DEFAULT << 9) /**< Shifted mode DEFAULT for PCNT_CMD */
+#define PCNT_CMD_STOPCNT (0x1UL << 10) /**< Stop Main Counter */
+#define _PCNT_CMD_STOPCNT_SHIFT 10 /**< Shift value for PCNT_STOPCNT */
+#define _PCNT_CMD_STOPCNT_MASK 0x400UL /**< Bit mask for PCNT_STOPCNT */
+#define _PCNT_CMD_STOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */
+#define PCNT_CMD_STOPCNT_DEFAULT (_PCNT_CMD_STOPCNT_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_CMD */
+#define PCNT_CMD_STOPAUXCNT (0x1UL << 11) /**< Stop Aux Counter */
+#define _PCNT_CMD_STOPAUXCNT_SHIFT 11 /**< Shift value for PCNT_STOPAUXCNT */
+#define _PCNT_CMD_STOPAUXCNT_MASK 0x800UL /**< Bit mask for PCNT_STOPAUXCNT */
+#define _PCNT_CMD_STOPAUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */
+#define PCNT_CMD_STOPAUXCNT_DEFAULT (_PCNT_CMD_STOPAUXCNT_DEFAULT << 11) /**< Shifted mode DEFAULT for PCNT_CMD */
+
+/* Bit fields for PCNT STATUS */
+#define _PCNT_STATUS_RESETVALUE 0x00000000UL /**< Default value for PCNT_STATUS */
+#define _PCNT_STATUS_MASK 0x0000001FUL /**< Mask for PCNT_STATUS */
+#define PCNT_STATUS_DIR (0x1UL << 0) /**< Current Counter Direction */
+#define _PCNT_STATUS_DIR_SHIFT 0 /**< Shift value for PCNT_DIR */
+#define _PCNT_STATUS_DIR_MASK 0x1UL /**< Bit mask for PCNT_DIR */
+#define _PCNT_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */
+#define _PCNT_STATUS_DIR_UP 0x00000000UL /**< Mode UP for PCNT_STATUS */
+#define _PCNT_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_STATUS */
+#define PCNT_STATUS_DIR_DEFAULT (_PCNT_STATUS_DIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_STATUS */
+#define PCNT_STATUS_DIR_UP (_PCNT_STATUS_DIR_UP << 0) /**< Shifted mode UP for PCNT_STATUS */
+#define PCNT_STATUS_DIR_DOWN (_PCNT_STATUS_DIR_DOWN << 0) /**< Shifted mode DOWN for PCNT_STATUS */
+#define PCNT_STATUS_TOPBV (0x1UL << 1) /**< TOP Buffer Valid */
+#define _PCNT_STATUS_TOPBV_SHIFT 1 /**< Shift value for PCNT_TOPBV */
+#define _PCNT_STATUS_TOPBV_MASK 0x2UL /**< Bit mask for PCNT_TOPBV */
+#define _PCNT_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */
+#define PCNT_STATUS_TOPBV_DEFAULT (_PCNT_STATUS_TOPBV_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_STATUS */
+#define PCNT_STATUS_PCNTLOCKSTATUS (0x1UL << 2) /**< Lock Status */
+#define _PCNT_STATUS_PCNTLOCKSTATUS_SHIFT 2 /**< Shift value for PCNT_PCNTLOCKSTATUS */
+#define _PCNT_STATUS_PCNTLOCKSTATUS_MASK 0x4UL /**< Bit mask for PCNT_PCNTLOCKSTATUS */
+#define _PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */
+#define _PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for PCNT_STATUS */
+#define _PCNT_STATUS_PCNTLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for PCNT_STATUS */
+#define PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT (_PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_STATUS */
+#define PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED (_PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED << 2) /**< Shifted mode UNLOCKED for PCNT_STATUS */
+#define PCNT_STATUS_PCNTLOCKSTATUS_LOCKED (_PCNT_STATUS_PCNTLOCKSTATUS_LOCKED << 2) /**< Shifted mode LOCKED for PCNT_STATUS */
+#define PCNT_STATUS_CNTRUNNING (0x1UL << 3) /**< Main Counter running status */
+#define _PCNT_STATUS_CNTRUNNING_SHIFT 3 /**< Shift value for PCNT_CNTRUNNING */
+#define _PCNT_STATUS_CNTRUNNING_MASK 0x8UL /**< Bit mask for PCNT_CNTRUNNING */
+#define _PCNT_STATUS_CNTRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */
+#define PCNT_STATUS_CNTRUNNING_DEFAULT (_PCNT_STATUS_CNTRUNNING_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_STATUS */
+#define PCNT_STATUS_AUXCNTRUNNING (0x1UL << 4) /**< Aux Counter running status */
+#define _PCNT_STATUS_AUXCNTRUNNING_SHIFT 4 /**< Shift value for PCNT_AUXCNTRUNNING */
+#define _PCNT_STATUS_AUXCNTRUNNING_MASK 0x10UL /**< Bit mask for PCNT_AUXCNTRUNNING */
+#define _PCNT_STATUS_AUXCNTRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */
+#define PCNT_STATUS_AUXCNTRUNNING_DEFAULT (_PCNT_STATUS_AUXCNTRUNNING_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_STATUS */
+
+/* Bit fields for PCNT IF */
+#define _PCNT_IF_RESETVALUE 0x00000000UL /**< Default value for PCNT_IF */
+#define _PCNT_IF_MASK 0x0000001FUL /**< Mask for PCNT_IF */
+#define PCNT_IF_UF (0x1UL << 0) /**< Underflow Interrupt Read Flag */
+#define _PCNT_IF_UF_SHIFT 0 /**< Shift value for PCNT_UF */
+#define _PCNT_IF_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */
+#define _PCNT_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
+#define PCNT_IF_UF_DEFAULT (_PCNT_IF_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IF */
+#define PCNT_IF_OF (0x1UL << 1) /**< Overflow Interrupt Read Flag */
+#define _PCNT_IF_OF_SHIFT 1 /**< Shift value for PCNT_OF */
+#define _PCNT_IF_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */
+#define _PCNT_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
+#define PCNT_IF_OF_DEFAULT (_PCNT_IF_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IF */
+#define PCNT_IF_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */
+#define _PCNT_IF_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */
+#define _PCNT_IF_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */
+#define _PCNT_IF_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
+#define PCNT_IF_DIRCNG_DEFAULT (_PCNT_IF_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IF */
+#define PCNT_IF_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Read Flag */
+#define _PCNT_IF_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */
+#define _PCNT_IF_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */
+#define _PCNT_IF_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
+#define PCNT_IF_AUXOF_DEFAULT (_PCNT_IF_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IF */
+#define PCNT_IF_OQSTERR (0x1UL << 4) /**< Oversampling Quad State Err Int Flag */
+#define _PCNT_IF_OQSTERR_SHIFT 4 /**< Shift value for PCNT_OQSTERR */
+#define _PCNT_IF_OQSTERR_MASK 0x10UL /**< Bit mask for PCNT_OQSTERR */
+#define _PCNT_IF_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
+#define PCNT_IF_OQSTERR_DEFAULT (_PCNT_IF_OQSTERR_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IF */
+
+/* Bit fields for PCNT IEN */
+#define _PCNT_IEN_RESETVALUE 0x00000000UL /**< Default value for PCNT_IEN */
+#define _PCNT_IEN_MASK 0x0000001FUL /**< Mask for PCNT_IEN */
+#define PCNT_IEN_UF (0x1UL << 0) /**< Underflow Interrupt Read Flag */
+#define _PCNT_IEN_UF_SHIFT 0 /**< Shift value for PCNT_UF */
+#define _PCNT_IEN_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */
+#define _PCNT_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_UF_DEFAULT (_PCNT_IEN_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_OF (0x1UL << 1) /**< Overflow Interrupt Read Flag */
+#define _PCNT_IEN_OF_SHIFT 1 /**< Shift value for PCNT_OF */
+#define _PCNT_IEN_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */
+#define _PCNT_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_OF_DEFAULT (_PCNT_IEN_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */
+#define _PCNT_IEN_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */
+#define _PCNT_IEN_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */
+#define _PCNT_IEN_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_DIRCNG_DEFAULT (_PCNT_IEN_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Read Flag */
+#define _PCNT_IEN_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */
+#define _PCNT_IEN_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */
+#define _PCNT_IEN_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_AUXOF_DEFAULT (_PCNT_IEN_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_OQSTERR (0x1UL << 4) /**< Oversampling Quad State Err Int Flag */
+#define _PCNT_IEN_OQSTERR_SHIFT 4 /**< Shift value for PCNT_OQSTERR */
+#define _PCNT_IEN_OQSTERR_MASK 0x10UL /**< Bit mask for PCNT_OQSTERR */
+#define _PCNT_IEN_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
+#define PCNT_IEN_OQSTERR_DEFAULT (_PCNT_IEN_OQSTERR_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IEN */
+
+/* Bit fields for PCNT CNT */
+#define _PCNT_CNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_CNT */
+#define _PCNT_CNT_MASK 0x0000FFFFUL /**< Mask for PCNT_CNT */
+#define _PCNT_CNT_CNT_SHIFT 0 /**< Shift value for PCNT_CNT */
+#define _PCNT_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for PCNT_CNT */
+#define _PCNT_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CNT */
+#define PCNT_CNT_CNT_DEFAULT (_PCNT_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CNT */
+
+/* Bit fields for PCNT AUXCNT */
+#define _PCNT_AUXCNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_AUXCNT */
+#define _PCNT_AUXCNT_MASK 0x0000FFFFUL /**< Mask for PCNT_AUXCNT */
+#define _PCNT_AUXCNT_AUXCNT_SHIFT 0 /**< Shift value for PCNT_AUXCNT */
+#define _PCNT_AUXCNT_AUXCNT_MASK 0xFFFFUL /**< Bit mask for PCNT_AUXCNT */
+#define _PCNT_AUXCNT_AUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_AUXCNT */
+#define PCNT_AUXCNT_AUXCNT_DEFAULT (_PCNT_AUXCNT_AUXCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_AUXCNT */
+
+/* Bit fields for PCNT TOP */
+#define _PCNT_TOP_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOP */
+#define _PCNT_TOP_MASK 0x0000FFFFUL /**< Mask for PCNT_TOP */
+#define _PCNT_TOP_TOP_SHIFT 0 /**< Shift value for PCNT_TOP */
+#define _PCNT_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for PCNT_TOP */
+#define _PCNT_TOP_TOP_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOP */
+#define PCNT_TOP_TOP_DEFAULT (_PCNT_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOP */
+
+/* Bit fields for PCNT TOPB */
+#define _PCNT_TOPB_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOPB */
+#define _PCNT_TOPB_MASK 0x0000FFFFUL /**< Mask for PCNT_TOPB */
+#define _PCNT_TOPB_TOPB_SHIFT 0 /**< Shift value for PCNT_TOPB */
+#define _PCNT_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for PCNT_TOPB */
+#define _PCNT_TOPB_TOPB_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOPB */
+#define PCNT_TOPB_TOPB_DEFAULT (_PCNT_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOPB */
+
+/* Bit fields for PCNT OVSCTRL */
+#define _PCNT_OVSCTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_OVSCTRL */
+#define _PCNT_OVSCTRL_MASK 0x000010FFUL /**< Mask for PCNT_OVSCTRL */
+#define _PCNT_OVSCTRL_FILTLEN_SHIFT 0 /**< Shift value for PCNT_FILTLEN */
+#define _PCNT_OVSCTRL_FILTLEN_MASK 0xFFUL /**< Bit mask for PCNT_FILTLEN */
+#define _PCNT_OVSCTRL_FILTLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCTRL */
+#define PCNT_OVSCTRL_FILTLEN_DEFAULT (_PCNT_OVSCTRL_FILTLEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_OVSCTRL */
+#define PCNT_OVSCTRL_FLUTTERRM (0x1UL << 12) /**< Flutter Remove */
+#define _PCNT_OVSCTRL_FLUTTERRM_SHIFT 12 /**< Shift value for PCNT_FLUTTERRM */
+#define _PCNT_OVSCTRL_FLUTTERRM_MASK 0x1000UL /**< Bit mask for PCNT_FLUTTERRM */
+#define _PCNT_OVSCTRL_FLUTTERRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCTRL */
+#define PCNT_OVSCTRL_FLUTTERRM_DEFAULT (_PCNT_OVSCTRL_FLUTTERRM_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_OVSCTRL */
+
+/* Bit fields for PCNT SYNCBUSY */
+#define _PCNT_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for PCNT_SYNCBUSY */
+#define _PCNT_SYNCBUSY_MASK 0x0000001FUL /**< Mask for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
+#define _PCNT_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for PCNT_CTRL */
+#define _PCNT_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for PCNT_CTRL */
+#define _PCNT_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_CTRL_DEFAULT (_PCNT_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */
+#define _PCNT_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for PCNT_CMD */
+#define _PCNT_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for PCNT_CMD */
+#define _PCNT_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_CMD_DEFAULT (_PCNT_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_TOP (0x1UL << 2) /**< TOP Register Busy */
+#define _PCNT_SYNCBUSY_TOP_SHIFT 2 /**< Shift value for PCNT_TOP */
+#define _PCNT_SYNCBUSY_TOP_MASK 0x4UL /**< Bit mask for PCNT_TOP */
+#define _PCNT_SYNCBUSY_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_TOP_DEFAULT (_PCNT_SYNCBUSY_TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_TOPB (0x1UL << 3) /**< TOPB Register Busy */
+#define _PCNT_SYNCBUSY_TOPB_SHIFT 3 /**< Shift value for PCNT_TOPB */
+#define _PCNT_SYNCBUSY_TOPB_MASK 0x8UL /**< Bit mask for PCNT_TOPB */
+#define _PCNT_SYNCBUSY_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_TOPB_DEFAULT (_PCNT_SYNCBUSY_TOPB_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_OVSCTRL (0x1UL << 4) /**< OVSCTRL Register Busy */
+#define _PCNT_SYNCBUSY_OVSCTRL_SHIFT 4 /**< Shift value for PCNT_OVSCTRL */
+#define _PCNT_SYNCBUSY_OVSCTRL_MASK 0x10UL /**< Bit mask for PCNT_OVSCTRL */
+#define _PCNT_SYNCBUSY_OVSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
+#define PCNT_SYNCBUSY_OVSCTRL_DEFAULT (_PCNT_SYNCBUSY_OVSCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
+
+/* Bit fields for PCNT LOCK */
+#define _PCNT_LOCK_RESETVALUE 0x00000000UL /**< Default value for PCNT_LOCK */
+#define _PCNT_LOCK_MASK 0x0000FFFFUL /**< Mask for PCNT_LOCK */
+#define _PCNT_LOCK_PCNTLOCKKEY_SHIFT 0 /**< Shift value for PCNT_PCNTLOCKKEY */
+#define _PCNT_LOCK_PCNTLOCKKEY_MASK 0xFFFFUL /**< Bit mask for PCNT_PCNTLOCKKEY */
+#define _PCNT_LOCK_PCNTLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_LOCK */
+#define _PCNT_LOCK_PCNTLOCKKEY_UNLOCK 0x0000A7E0UL /**< Mode UNLOCK for PCNT_LOCK */
+#define PCNT_LOCK_PCNTLOCKKEY_DEFAULT (_PCNT_LOCK_PCNTLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_LOCK */
+#define PCNT_LOCK_PCNTLOCKKEY_UNLOCK (_PCNT_LOCK_PCNTLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for PCNT_LOCK */
+
+/** @} End of group EFR32MG24_PCNT_BitFields */
+/** @} End of group EFR32MG24_PCNT */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_PCNT_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_protimer.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_protimer.h
new file mode 100644
index 00000000..a5bb516b
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_protimer.h
@@ -0,0 +1,1838 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 PROTIMER register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_PROTIMER_H
+#define EFR32MG24_PROTIMER_H
+#define PROTIMER_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_PROTIMER PROTIMER
+ * @{
+ * @brief EFR32MG24 PROTIMER Register Declaration.
+ *****************************************************************************/
+
+/** PROTIMER CC Register Group Declaration. */
+typedef struct {
+ __IOM uint32_t CTRL; /**< CC Channel Control Register */
+ __IOM uint32_t PRE; /**< CC Channel PRE Value Register */
+ __IOM uint32_t BASE; /**< CC Channel BASE Value Register */
+ __IOM uint32_t WRAP; /**< CC Channel WRAP Value Register */
+} PROTIMER_CC_TypeDef;
+
+/** PROTIMER Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IPVERSION */
+ __IOM uint32_t EN; /**< EN */
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IOM uint32_t PRSCTRL; /**< PRS Channel selection */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IOM uint32_t PRECNT; /**< Pre Counter Value */
+ __IOM uint32_t BASECNT; /**< Base Counter Value */
+ __IOM uint32_t WRAPCNT; /**< Wrap Counter Value */
+ __IM uint32_t BASEPRE; /**< Base and Pre counter values */
+ __IM uint32_t LWRAPCNT; /**< Latched Wrap Counter Value */
+ __IOM uint32_t PRECNTTOPADJ; /**< PRECNT Top Adjust Value */
+ __IOM uint32_t PRECNTTOP; /**< PRECNT Top Value */
+ __IOM uint32_t BASECNTTOP; /**< BASECNT Top Value */
+ __IOM uint32_t WRAPCNTTOP; /**< WRAPCNT Top Value Register */
+ __IOM uint32_t TOUT0CNT; /**< TOUT0CNT Value Register */
+ __IOM uint32_t TOUT0CNTTOP; /**< TOUT0CNTTOP Value Register. */
+ __IOM uint32_t TOUT0COMP; /**< TOUT0COMP Register */
+ __IOM uint32_t TOUT1CNT; /**< TOUT1CNT Value Register */
+ __IOM uint32_t TOUT1CNTTOP; /**< TOUT1CNTTOP Value Register. */
+ __IOM uint32_t TOUT1COMP; /**< TOUT1COMP Register */
+ __IOM uint32_t LBTCTRL; /**< Listen Before Talk Wait Control */
+ __IOM uint32_t LBTPRSCTRL; /**< PRS Channel selection */
+ __IOM uint32_t LBTSTATE; /**< Listen Before Talk State */
+ __IOM uint32_t RANDOM; /**< Pseudo Random Generator Value Register */
+ __IOM uint32_t IF; /**< Interrupt Flag Register */
+ uint32_t RESERVED0[2U]; /**< Reserved for future use */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IOM uint32_t RXCTRL; /**< RX request signal from Protimer */
+ __IOM uint32_t TXCTRL; /**< TX request signal from Protimer */
+ __IOM uint32_t ETSI; /**< Support ETSI LBT */
+ __IOM uint32_t LBTSTATE1; /**< Listen Before Talk State */
+ __IOM uint32_t RANDOMFW0; /**< GENERATED LINEAR RANDOM VALUE */
+ __IOM uint32_t RANDOMFW1; /**< GENERATED LINEAR RANDOM VALUE */
+ __IOM uint32_t RANDOMFW2; /**< GENERATED LINEAR RANDOM VALUE */
+ __IOM uint32_t SEQIF; /**< SEQ Interrupt Flagh Register */
+ __IOM uint32_t SEQIEN; /**< SEQ Interrupt Enable Register */
+ uint32_t RESERVED1[26U]; /**< Reserved for future use */
+ PROTIMER_CC_TypeDef CC[8U]; /**< Compare/Capture Channel */
+ uint32_t RESERVED2[928U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IPVERSION */
+ __IOM uint32_t EN_SET; /**< EN */
+ __IOM uint32_t CTRL_SET; /**< Control Register */
+ __IOM uint32_t CMD_SET; /**< Command Register */
+ __IOM uint32_t PRSCTRL_SET; /**< PRS Channel selection */
+ __IM uint32_t STATUS_SET; /**< Status Register */
+ __IOM uint32_t PRECNT_SET; /**< Pre Counter Value */
+ __IOM uint32_t BASECNT_SET; /**< Base Counter Value */
+ __IOM uint32_t WRAPCNT_SET; /**< Wrap Counter Value */
+ __IM uint32_t BASEPRE_SET; /**< Base and Pre counter values */
+ __IM uint32_t LWRAPCNT_SET; /**< Latched Wrap Counter Value */
+ __IOM uint32_t PRECNTTOPADJ_SET; /**< PRECNT Top Adjust Value */
+ __IOM uint32_t PRECNTTOP_SET; /**< PRECNT Top Value */
+ __IOM uint32_t BASECNTTOP_SET; /**< BASECNT Top Value */
+ __IOM uint32_t WRAPCNTTOP_SET; /**< WRAPCNT Top Value Register */
+ __IOM uint32_t TOUT0CNT_SET; /**< TOUT0CNT Value Register */
+ __IOM uint32_t TOUT0CNTTOP_SET; /**< TOUT0CNTTOP Value Register. */
+ __IOM uint32_t TOUT0COMP_SET; /**< TOUT0COMP Register */
+ __IOM uint32_t TOUT1CNT_SET; /**< TOUT1CNT Value Register */
+ __IOM uint32_t TOUT1CNTTOP_SET; /**< TOUT1CNTTOP Value Register. */
+ __IOM uint32_t TOUT1COMP_SET; /**< TOUT1COMP Register */
+ __IOM uint32_t LBTCTRL_SET; /**< Listen Before Talk Wait Control */
+ __IOM uint32_t LBTPRSCTRL_SET; /**< PRS Channel selection */
+ __IOM uint32_t LBTSTATE_SET; /**< Listen Before Talk State */
+ __IOM uint32_t RANDOM_SET; /**< Pseudo Random Generator Value Register */
+ __IOM uint32_t IF_SET; /**< Interrupt Flag Register */
+ uint32_t RESERVED3[2U]; /**< Reserved for future use */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
+ __IOM uint32_t RXCTRL_SET; /**< RX request signal from Protimer */
+ __IOM uint32_t TXCTRL_SET; /**< TX request signal from Protimer */
+ __IOM uint32_t ETSI_SET; /**< Support ETSI LBT */
+ __IOM uint32_t LBTSTATE1_SET; /**< Listen Before Talk State */
+ __IOM uint32_t RANDOMFW0_SET; /**< GENERATED LINEAR RANDOM VALUE */
+ __IOM uint32_t RANDOMFW1_SET; /**< GENERATED LINEAR RANDOM VALUE */
+ __IOM uint32_t RANDOMFW2_SET; /**< GENERATED LINEAR RANDOM VALUE */
+ __IOM uint32_t SEQIF_SET; /**< SEQ Interrupt Flagh Register */
+ __IOM uint32_t SEQIEN_SET; /**< SEQ Interrupt Enable Register */
+ uint32_t RESERVED4[26U]; /**< Reserved for future use */
+ PROTIMER_CC_TypeDef CC_SET[8U]; /**< Compare/Capture Channel */
+ uint32_t RESERVED5[928U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IPVERSION */
+ __IOM uint32_t EN_CLR; /**< EN */
+ __IOM uint32_t CTRL_CLR; /**< Control Register */
+ __IOM uint32_t CMD_CLR; /**< Command Register */
+ __IOM uint32_t PRSCTRL_CLR; /**< PRS Channel selection */
+ __IM uint32_t STATUS_CLR; /**< Status Register */
+ __IOM uint32_t PRECNT_CLR; /**< Pre Counter Value */
+ __IOM uint32_t BASECNT_CLR; /**< Base Counter Value */
+ __IOM uint32_t WRAPCNT_CLR; /**< Wrap Counter Value */
+ __IM uint32_t BASEPRE_CLR; /**< Base and Pre counter values */
+ __IM uint32_t LWRAPCNT_CLR; /**< Latched Wrap Counter Value */
+ __IOM uint32_t PRECNTTOPADJ_CLR; /**< PRECNT Top Adjust Value */
+ __IOM uint32_t PRECNTTOP_CLR; /**< PRECNT Top Value */
+ __IOM uint32_t BASECNTTOP_CLR; /**< BASECNT Top Value */
+ __IOM uint32_t WRAPCNTTOP_CLR; /**< WRAPCNT Top Value Register */
+ __IOM uint32_t TOUT0CNT_CLR; /**< TOUT0CNT Value Register */
+ __IOM uint32_t TOUT0CNTTOP_CLR; /**< TOUT0CNTTOP Value Register. */
+ __IOM uint32_t TOUT0COMP_CLR; /**< TOUT0COMP Register */
+ __IOM uint32_t TOUT1CNT_CLR; /**< TOUT1CNT Value Register */
+ __IOM uint32_t TOUT1CNTTOP_CLR; /**< TOUT1CNTTOP Value Register. */
+ __IOM uint32_t TOUT1COMP_CLR; /**< TOUT1COMP Register */
+ __IOM uint32_t LBTCTRL_CLR; /**< Listen Before Talk Wait Control */
+ __IOM uint32_t LBTPRSCTRL_CLR; /**< PRS Channel selection */
+ __IOM uint32_t LBTSTATE_CLR; /**< Listen Before Talk State */
+ __IOM uint32_t RANDOM_CLR; /**< Pseudo Random Generator Value Register */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
+ uint32_t RESERVED6[2U]; /**< Reserved for future use */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
+ __IOM uint32_t RXCTRL_CLR; /**< RX request signal from Protimer */
+ __IOM uint32_t TXCTRL_CLR; /**< TX request signal from Protimer */
+ __IOM uint32_t ETSI_CLR; /**< Support ETSI LBT */
+ __IOM uint32_t LBTSTATE1_CLR; /**< Listen Before Talk State */
+ __IOM uint32_t RANDOMFW0_CLR; /**< GENERATED LINEAR RANDOM VALUE */
+ __IOM uint32_t RANDOMFW1_CLR; /**< GENERATED LINEAR RANDOM VALUE */
+ __IOM uint32_t RANDOMFW2_CLR; /**< GENERATED LINEAR RANDOM VALUE */
+ __IOM uint32_t SEQIF_CLR; /**< SEQ Interrupt Flagh Register */
+ __IOM uint32_t SEQIEN_CLR; /**< SEQ Interrupt Enable Register */
+ uint32_t RESERVED7[26U]; /**< Reserved for future use */
+ PROTIMER_CC_TypeDef CC_CLR[8U]; /**< Compare/Capture Channel */
+ uint32_t RESERVED8[928U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IPVERSION */
+ __IOM uint32_t EN_TGL; /**< EN */
+ __IOM uint32_t CTRL_TGL; /**< Control Register */
+ __IOM uint32_t CMD_TGL; /**< Command Register */
+ __IOM uint32_t PRSCTRL_TGL; /**< PRS Channel selection */
+ __IM uint32_t STATUS_TGL; /**< Status Register */
+ __IOM uint32_t PRECNT_TGL; /**< Pre Counter Value */
+ __IOM uint32_t BASECNT_TGL; /**< Base Counter Value */
+ __IOM uint32_t WRAPCNT_TGL; /**< Wrap Counter Value */
+ __IM uint32_t BASEPRE_TGL; /**< Base and Pre counter values */
+ __IM uint32_t LWRAPCNT_TGL; /**< Latched Wrap Counter Value */
+ __IOM uint32_t PRECNTTOPADJ_TGL; /**< PRECNT Top Adjust Value */
+ __IOM uint32_t PRECNTTOP_TGL; /**< PRECNT Top Value */
+ __IOM uint32_t BASECNTTOP_TGL; /**< BASECNT Top Value */
+ __IOM uint32_t WRAPCNTTOP_TGL; /**< WRAPCNT Top Value Register */
+ __IOM uint32_t TOUT0CNT_TGL; /**< TOUT0CNT Value Register */
+ __IOM uint32_t TOUT0CNTTOP_TGL; /**< TOUT0CNTTOP Value Register. */
+ __IOM uint32_t TOUT0COMP_TGL; /**< TOUT0COMP Register */
+ __IOM uint32_t TOUT1CNT_TGL; /**< TOUT1CNT Value Register */
+ __IOM uint32_t TOUT1CNTTOP_TGL; /**< TOUT1CNTTOP Value Register. */
+ __IOM uint32_t TOUT1COMP_TGL; /**< TOUT1COMP Register */
+ __IOM uint32_t LBTCTRL_TGL; /**< Listen Before Talk Wait Control */
+ __IOM uint32_t LBTPRSCTRL_TGL; /**< PRS Channel selection */
+ __IOM uint32_t LBTSTATE_TGL; /**< Listen Before Talk State */
+ __IOM uint32_t RANDOM_TGL; /**< Pseudo Random Generator Value Register */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
+ uint32_t RESERVED9[2U]; /**< Reserved for future use */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
+ __IOM uint32_t RXCTRL_TGL; /**< RX request signal from Protimer */
+ __IOM uint32_t TXCTRL_TGL; /**< TX request signal from Protimer */
+ __IOM uint32_t ETSI_TGL; /**< Support ETSI LBT */
+ __IOM uint32_t LBTSTATE1_TGL; /**< Listen Before Talk State */
+ __IOM uint32_t RANDOMFW0_TGL; /**< GENERATED LINEAR RANDOM VALUE */
+ __IOM uint32_t RANDOMFW1_TGL; /**< GENERATED LINEAR RANDOM VALUE */
+ __IOM uint32_t RANDOMFW2_TGL; /**< GENERATED LINEAR RANDOM VALUE */
+ __IOM uint32_t SEQIF_TGL; /**< SEQ Interrupt Flagh Register */
+ __IOM uint32_t SEQIEN_TGL; /**< SEQ Interrupt Enable Register */
+ uint32_t RESERVED10[26U]; /**< Reserved for future use */
+ PROTIMER_CC_TypeDef CC_TGL[8U]; /**< Compare/Capture Channel */
+} PROTIMER_TypeDef;
+/** @} End of group EFR32MG24_PROTIMER */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_PROTIMER
+ * @{
+ * @defgroup EFR32MG24_PROTIMER_BitFields PROTIMER Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for PROTIMER IPVERSION */
+#define _PROTIMER_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for PROTIMER_IPVERSION */
+#define _PROTIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PROTIMER_IPVERSION */
+#define _PROTIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PROTIMER_IPVERSION */
+#define _PROTIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PROTIMER_IPVERSION */
+#define _PROTIMER_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for PROTIMER_IPVERSION */
+#define PROTIMER_IPVERSION_IPVERSION_DEFAULT (_PROTIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_IPVERSION */
+
+/* Bit fields for PROTIMER EN */
+#define _PROTIMER_EN_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_EN */
+#define _PROTIMER_EN_MASK 0x00000001UL /**< Mask for PROTIMER_EN */
+#define PROTIMER_EN_EN (0x1UL << 0) /**< EN */
+#define _PROTIMER_EN_EN_SHIFT 0 /**< Shift value for PROTIMER_EN */
+#define _PROTIMER_EN_EN_MASK 0x1UL /**< Bit mask for PROTIMER_EN */
+#define _PROTIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_EN */
+#define PROTIMER_EN_EN_DEFAULT (_PROTIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_EN */
+
+/* Bit fields for PROTIMER CTRL */
+#define _PROTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_MASK 0x3FF33336UL /**< Mask for PROTIMER_CTRL */
+#define PROTIMER_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */
+#define _PROTIMER_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for PROTIMER_DEBUGRUN */
+#define _PROTIMER_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for PROTIMER_DEBUGRUN */
+#define _PROTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_DEBUGRUN_X0 0x00000000UL /**< Mode X0 for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_DEBUGRUN_X1 0x00000001UL /**< Mode X1 for PROTIMER_CTRL */
+#define PROTIMER_CTRL_DEBUGRUN_DEFAULT (_PROTIMER_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for PROTIMER_CTRL */
+#define PROTIMER_CTRL_DEBUGRUN_X0 (_PROTIMER_CTRL_DEBUGRUN_X0 << 1) /**< Shifted mode X0 for PROTIMER_CTRL */
+#define PROTIMER_CTRL_DEBUGRUN_X1 (_PROTIMER_CTRL_DEBUGRUN_X1 << 1) /**< Shifted mode X1 for PROTIMER_CTRL */
+#define PROTIMER_CTRL_DMACLRACT (0x1UL << 2) /**< DMA Request Clear on Active */
+#define _PROTIMER_CTRL_DMACLRACT_SHIFT 2 /**< Shift value for PROTIMER_DMACLRACT */
+#define _PROTIMER_CTRL_DMACLRACT_MASK 0x4UL /**< Bit mask for PROTIMER_DMACLRACT */
+#define _PROTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CTRL */
+#define PROTIMER_CTRL_DMACLRACT_DEFAULT (_PROTIMER_CTRL_DMACLRACT_DEFAULT << 2) /**< Shifted mode DEFAULT for PROTIMER_CTRL */
+#define PROTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-Shot Mode Enable */
+#define _PROTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for PROTIMER_OSMEN */
+#define _PROTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for PROTIMER_OSMEN */
+#define _PROTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_OSMEN_X0 0x00000000UL /**< Mode X0 for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_OSMEN_X1 0x00000001UL /**< Mode X1 for PROTIMER_CTRL */
+#define PROTIMER_CTRL_OSMEN_DEFAULT (_PROTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PROTIMER_CTRL */
+#define PROTIMER_CTRL_OSMEN_X0 (_PROTIMER_CTRL_OSMEN_X0 << 4) /**< Shifted mode X0 for PROTIMER_CTRL */
+#define PROTIMER_CTRL_OSMEN_X1 (_PROTIMER_CTRL_OSMEN_X1 << 4) /**< Shifted mode X1 for PROTIMER_CTRL */
+#define PROTIMER_CTRL_ZEROSTARTEN (0x1UL << 5) /**< Start from zero enable */
+#define _PROTIMER_CTRL_ZEROSTARTEN_SHIFT 5 /**< Shift value for PROTIMER_ZEROSTARTEN */
+#define _PROTIMER_CTRL_ZEROSTARTEN_MASK 0x20UL /**< Bit mask for PROTIMER_ZEROSTARTEN */
+#define _PROTIMER_CTRL_ZEROSTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_ZEROSTARTEN_X0 0x00000000UL /**< Mode X0 for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_ZEROSTARTEN_X1 0x00000001UL /**< Mode X1 for PROTIMER_CTRL */
+#define PROTIMER_CTRL_ZEROSTARTEN_DEFAULT (_PROTIMER_CTRL_ZEROSTARTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PROTIMER_CTRL */
+#define PROTIMER_CTRL_ZEROSTARTEN_X0 (_PROTIMER_CTRL_ZEROSTARTEN_X0 << 5) /**< Shifted mode X0 for PROTIMER_CTRL */
+#define PROTIMER_CTRL_ZEROSTARTEN_X1 (_PROTIMER_CTRL_ZEROSTARTEN_X1 << 5) /**< Shifted mode X1 for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_PRECNTSRC_SHIFT 8 /**< Shift value for PROTIMER_PRECNTSRC */
+#define _PROTIMER_CTRL_PRECNTSRC_MASK 0x300UL /**< Bit mask for PROTIMER_PRECNTSRC */
+#define _PROTIMER_CTRL_PRECNTSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_PRECNTSRC_DISABLED 0x00000000UL /**< Mode DISABLED for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_PRECNTSRC_CLOCK 0x00000001UL /**< Mode CLOCK for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_PRECNTSRC_UNUSED0 0x00000002UL /**< Mode UNUSED0 for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_PRECNTSRC_UNUSED1 0x00000003UL /**< Mode UNUSED1 for PROTIMER_CTRL */
+#define PROTIMER_CTRL_PRECNTSRC_DEFAULT (_PROTIMER_CTRL_PRECNTSRC_DEFAULT << 8) /**< Shifted mode DEFAULT for PROTIMER_CTRL */
+#define PROTIMER_CTRL_PRECNTSRC_DISABLED (_PROTIMER_CTRL_PRECNTSRC_DISABLED << 8) /**< Shifted mode DISABLED for PROTIMER_CTRL */
+#define PROTIMER_CTRL_PRECNTSRC_CLOCK (_PROTIMER_CTRL_PRECNTSRC_CLOCK << 8) /**< Shifted mode CLOCK for PROTIMER_CTRL */
+#define PROTIMER_CTRL_PRECNTSRC_UNUSED0 (_PROTIMER_CTRL_PRECNTSRC_UNUSED0 << 8) /**< Shifted mode UNUSED0 for PROTIMER_CTRL */
+#define PROTIMER_CTRL_PRECNTSRC_UNUSED1 (_PROTIMER_CTRL_PRECNTSRC_UNUSED1 << 8) /**< Shifted mode UNUSED1 for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_BASECNTSRC_SHIFT 12 /**< Shift value for PROTIMER_BASECNTSRC */
+#define _PROTIMER_CTRL_BASECNTSRC_MASK 0x3000UL /**< Bit mask for PROTIMER_BASECNTSRC */
+#define _PROTIMER_CTRL_BASECNTSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_BASECNTSRC_DISABLED 0x00000000UL /**< Mode DISABLED for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_BASECNTSRC_PRECNTOF 0x00000001UL /**< Mode PRECNTOF for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_BASECNTSRC_UNUSED0 0x00000002UL /**< Mode UNUSED0 for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_BASECNTSRC_UNUSED1 0x00000003UL /**< Mode UNUSED1 for PROTIMER_CTRL */
+#define PROTIMER_CTRL_BASECNTSRC_DEFAULT (_PROTIMER_CTRL_BASECNTSRC_DEFAULT << 12) /**< Shifted mode DEFAULT for PROTIMER_CTRL */
+#define PROTIMER_CTRL_BASECNTSRC_DISABLED (_PROTIMER_CTRL_BASECNTSRC_DISABLED << 12) /**< Shifted mode DISABLED for PROTIMER_CTRL */
+#define PROTIMER_CTRL_BASECNTSRC_PRECNTOF (_PROTIMER_CTRL_BASECNTSRC_PRECNTOF << 12) /**< Shifted mode PRECNTOF for PROTIMER_CTRL */
+#define PROTIMER_CTRL_BASECNTSRC_UNUSED0 (_PROTIMER_CTRL_BASECNTSRC_UNUSED0 << 12) /**< Shifted mode UNUSED0 for PROTIMER_CTRL */
+#define PROTIMER_CTRL_BASECNTSRC_UNUSED1 (_PROTIMER_CTRL_BASECNTSRC_UNUSED1 << 12) /**< Shifted mode UNUSED1 for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_WRAPCNTSRC_SHIFT 16 /**< Shift value for PROTIMER_WRAPCNTSRC */
+#define _PROTIMER_CTRL_WRAPCNTSRC_MASK 0x30000UL /**< Bit mask for PROTIMER_WRAPCNTSRC */
+#define _PROTIMER_CTRL_WRAPCNTSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_WRAPCNTSRC_DISABLED 0x00000000UL /**< Mode DISABLED for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_WRAPCNTSRC_PRECNTOF 0x00000001UL /**< Mode PRECNTOF for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_WRAPCNTSRC_BASECNTOF 0x00000002UL /**< Mode BASECNTOF for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_WRAPCNTSRC_UNUSED 0x00000003UL /**< Mode UNUSED for PROTIMER_CTRL */
+#define PROTIMER_CTRL_WRAPCNTSRC_DEFAULT (_PROTIMER_CTRL_WRAPCNTSRC_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_CTRL */
+#define PROTIMER_CTRL_WRAPCNTSRC_DISABLED (_PROTIMER_CTRL_WRAPCNTSRC_DISABLED << 16) /**< Shifted mode DISABLED for PROTIMER_CTRL */
+#define PROTIMER_CTRL_WRAPCNTSRC_PRECNTOF (_PROTIMER_CTRL_WRAPCNTSRC_PRECNTOF << 16) /**< Shifted mode PRECNTOF for PROTIMER_CTRL */
+#define PROTIMER_CTRL_WRAPCNTSRC_BASECNTOF (_PROTIMER_CTRL_WRAPCNTSRC_BASECNTOF << 16) /**< Shifted mode BASECNTOF for PROTIMER_CTRL */
+#define PROTIMER_CTRL_WRAPCNTSRC_UNUSED (_PROTIMER_CTRL_WRAPCNTSRC_UNUSED << 16) /**< Shifted mode UNUSED for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_TOUT0SRC_SHIFT 20 /**< Shift value for PROTIMER_TOUT0SRC */
+#define _PROTIMER_CTRL_TOUT0SRC_MASK 0x300000UL /**< Bit mask for PROTIMER_TOUT0SRC */
+#define _PROTIMER_CTRL_TOUT0SRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_TOUT0SRC_DISABLED 0x00000000UL /**< Mode DISABLED for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_TOUT0SRC_PRECNTOF 0x00000001UL /**< Mode PRECNTOF for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_TOUT0SRC_BASECNTOF 0x00000002UL /**< Mode BASECNTOF for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_TOUT0SRC_WRAPCNTOF 0x00000003UL /**< Mode WRAPCNTOF for PROTIMER_CTRL */
+#define PROTIMER_CTRL_TOUT0SRC_DEFAULT (_PROTIMER_CTRL_TOUT0SRC_DEFAULT << 20) /**< Shifted mode DEFAULT for PROTIMER_CTRL */
+#define PROTIMER_CTRL_TOUT0SRC_DISABLED (_PROTIMER_CTRL_TOUT0SRC_DISABLED << 20) /**< Shifted mode DISABLED for PROTIMER_CTRL */
+#define PROTIMER_CTRL_TOUT0SRC_PRECNTOF (_PROTIMER_CTRL_TOUT0SRC_PRECNTOF << 20) /**< Shifted mode PRECNTOF for PROTIMER_CTRL */
+#define PROTIMER_CTRL_TOUT0SRC_BASECNTOF (_PROTIMER_CTRL_TOUT0SRC_BASECNTOF << 20) /**< Shifted mode BASECNTOF for PROTIMER_CTRL */
+#define PROTIMER_CTRL_TOUT0SRC_WRAPCNTOF (_PROTIMER_CTRL_TOUT0SRC_WRAPCNTOF << 20) /**< Shifted mode WRAPCNTOF for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_TOUT0SYNCSRC_SHIFT 22 /**< Shift value for PROTIMER_TOUT0SYNCSRC */
+#define _PROTIMER_CTRL_TOUT0SYNCSRC_MASK 0xC00000UL /**< Bit mask for PROTIMER_TOUT0SYNCSRC */
+#define _PROTIMER_CTRL_TOUT0SYNCSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_TOUT0SYNCSRC_DISABLED 0x00000000UL /**< Mode DISABLED for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_TOUT0SYNCSRC_PRECNTOF 0x00000001UL /**< Mode PRECNTOF for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_TOUT0SYNCSRC_BASECNTOF 0x00000002UL /**< Mode BASECNTOF for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_TOUT0SYNCSRC_WRAPCNTOF 0x00000003UL /**< Mode WRAPCNTOF for PROTIMER_CTRL */
+#define PROTIMER_CTRL_TOUT0SYNCSRC_DEFAULT (_PROTIMER_CTRL_TOUT0SYNCSRC_DEFAULT << 22) /**< Shifted mode DEFAULT for PROTIMER_CTRL */
+#define PROTIMER_CTRL_TOUT0SYNCSRC_DISABLED (_PROTIMER_CTRL_TOUT0SYNCSRC_DISABLED << 22) /**< Shifted mode DISABLED for PROTIMER_CTRL */
+#define PROTIMER_CTRL_TOUT0SYNCSRC_PRECNTOF (_PROTIMER_CTRL_TOUT0SYNCSRC_PRECNTOF << 22) /**< Shifted mode PRECNTOF for PROTIMER_CTRL */
+#define PROTIMER_CTRL_TOUT0SYNCSRC_BASECNTOF (_PROTIMER_CTRL_TOUT0SYNCSRC_BASECNTOF << 22) /**< Shifted mode BASECNTOF for PROTIMER_CTRL */
+#define PROTIMER_CTRL_TOUT0SYNCSRC_WRAPCNTOF (_PROTIMER_CTRL_TOUT0SYNCSRC_WRAPCNTOF << 22) /**< Shifted mode WRAPCNTOF for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_TOUT1SRC_SHIFT 24 /**< Shift value for PROTIMER_TOUT1SRC */
+#define _PROTIMER_CTRL_TOUT1SRC_MASK 0x3000000UL /**< Bit mask for PROTIMER_TOUT1SRC */
+#define _PROTIMER_CTRL_TOUT1SRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_TOUT1SRC_DISABLED 0x00000000UL /**< Mode DISABLED for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_TOUT1SRC_PRECNTOF 0x00000001UL /**< Mode PRECNTOF for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_TOUT1SRC_BASECNTOF 0x00000002UL /**< Mode BASECNTOF for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_TOUT1SRC_WRAPCNTOF 0x00000003UL /**< Mode WRAPCNTOF for PROTIMER_CTRL */
+#define PROTIMER_CTRL_TOUT1SRC_DEFAULT (_PROTIMER_CTRL_TOUT1SRC_DEFAULT << 24) /**< Shifted mode DEFAULT for PROTIMER_CTRL */
+#define PROTIMER_CTRL_TOUT1SRC_DISABLED (_PROTIMER_CTRL_TOUT1SRC_DISABLED << 24) /**< Shifted mode DISABLED for PROTIMER_CTRL */
+#define PROTIMER_CTRL_TOUT1SRC_PRECNTOF (_PROTIMER_CTRL_TOUT1SRC_PRECNTOF << 24) /**< Shifted mode PRECNTOF for PROTIMER_CTRL */
+#define PROTIMER_CTRL_TOUT1SRC_BASECNTOF (_PROTIMER_CTRL_TOUT1SRC_BASECNTOF << 24) /**< Shifted mode BASECNTOF for PROTIMER_CTRL */
+#define PROTIMER_CTRL_TOUT1SRC_WRAPCNTOF (_PROTIMER_CTRL_TOUT1SRC_WRAPCNTOF << 24) /**< Shifted mode WRAPCNTOF for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_TOUT1SYNCSRC_SHIFT 26 /**< Shift value for PROTIMER_TOUT1SYNCSRC */
+#define _PROTIMER_CTRL_TOUT1SYNCSRC_MASK 0xC000000UL /**< Bit mask for PROTIMER_TOUT1SYNCSRC */
+#define _PROTIMER_CTRL_TOUT1SYNCSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_TOUT1SYNCSRC_DISABLED 0x00000000UL /**< Mode DISABLED for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_TOUT1SYNCSRC_PRECNTOF 0x00000001UL /**< Mode PRECNTOF for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_TOUT1SYNCSRC_BASECNTOF 0x00000002UL /**< Mode BASECNTOF for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_TOUT1SYNCSRC_WRAPCNTOF 0x00000003UL /**< Mode WRAPCNTOF for PROTIMER_CTRL */
+#define PROTIMER_CTRL_TOUT1SYNCSRC_DEFAULT (_PROTIMER_CTRL_TOUT1SYNCSRC_DEFAULT << 26) /**< Shifted mode DEFAULT for PROTIMER_CTRL */
+#define PROTIMER_CTRL_TOUT1SYNCSRC_DISABLED (_PROTIMER_CTRL_TOUT1SYNCSRC_DISABLED << 26) /**< Shifted mode DISABLED for PROTIMER_CTRL */
+#define PROTIMER_CTRL_TOUT1SYNCSRC_PRECNTOF (_PROTIMER_CTRL_TOUT1SYNCSRC_PRECNTOF << 26) /**< Shifted mode PRECNTOF for PROTIMER_CTRL */
+#define PROTIMER_CTRL_TOUT1SYNCSRC_BASECNTOF (_PROTIMER_CTRL_TOUT1SYNCSRC_BASECNTOF << 26) /**< Shifted mode BASECNTOF for PROTIMER_CTRL */
+#define PROTIMER_CTRL_TOUT1SYNCSRC_WRAPCNTOF (_PROTIMER_CTRL_TOUT1SYNCSRC_WRAPCNTOF << 26) /**< Shifted mode WRAPCNTOF for PROTIMER_CTRL */
+#define PROTIMER_CTRL_TOUT0MODE (0x1UL << 28) /**< Repeat Mode */
+#define _PROTIMER_CTRL_TOUT0MODE_SHIFT 28 /**< Shift value for PROTIMER_TOUT0MODE */
+#define _PROTIMER_CTRL_TOUT0MODE_MASK 0x10000000UL /**< Bit mask for PROTIMER_TOUT0MODE */
+#define _PROTIMER_CTRL_TOUT0MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_TOUT0MODE_FREE 0x00000000UL /**< Mode FREE for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_TOUT0MODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for PROTIMER_CTRL */
+#define PROTIMER_CTRL_TOUT0MODE_DEFAULT (_PROTIMER_CTRL_TOUT0MODE_DEFAULT << 28) /**< Shifted mode DEFAULT for PROTIMER_CTRL */
+#define PROTIMER_CTRL_TOUT0MODE_FREE (_PROTIMER_CTRL_TOUT0MODE_FREE << 28) /**< Shifted mode FREE for PROTIMER_CTRL */
+#define PROTIMER_CTRL_TOUT0MODE_ONESHOT (_PROTIMER_CTRL_TOUT0MODE_ONESHOT << 28) /**< Shifted mode ONESHOT for PROTIMER_CTRL */
+#define PROTIMER_CTRL_TOUT1MODE (0x1UL << 29) /**< Repeat Mode */
+#define _PROTIMER_CTRL_TOUT1MODE_SHIFT 29 /**< Shift value for PROTIMER_TOUT1MODE */
+#define _PROTIMER_CTRL_TOUT1MODE_MASK 0x20000000UL /**< Bit mask for PROTIMER_TOUT1MODE */
+#define _PROTIMER_CTRL_TOUT1MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_TOUT1MODE_FREE 0x00000000UL /**< Mode FREE for PROTIMER_CTRL */
+#define _PROTIMER_CTRL_TOUT1MODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for PROTIMER_CTRL */
+#define PROTIMER_CTRL_TOUT1MODE_DEFAULT (_PROTIMER_CTRL_TOUT1MODE_DEFAULT << 29) /**< Shifted mode DEFAULT for PROTIMER_CTRL */
+#define PROTIMER_CTRL_TOUT1MODE_FREE (_PROTIMER_CTRL_TOUT1MODE_FREE << 29) /**< Shifted mode FREE for PROTIMER_CTRL */
+#define PROTIMER_CTRL_TOUT1MODE_ONESHOT (_PROTIMER_CTRL_TOUT1MODE_ONESHOT << 29) /**< Shifted mode ONESHOT for PROTIMER_CTRL */
+
+/* Bit fields for PROTIMER CMD */
+#define _PROTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_CMD */
+#define _PROTIMER_CMD_MASK 0x000707F7UL /**< Mask for PROTIMER_CMD */
+#define PROTIMER_CMD_START (0x1UL << 0) /**< Start PROTIMER */
+#define _PROTIMER_CMD_START_SHIFT 0 /**< Shift value for PROTIMER_START */
+#define _PROTIMER_CMD_START_MASK 0x1UL /**< Bit mask for PROTIMER_START */
+#define _PROTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CMD */
+#define PROTIMER_CMD_START_DEFAULT (_PROTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_CMD */
+#define PROTIMER_CMD_RTCSYNCSTART (0x1UL << 1) /**< Start PROTIMER Synchronized with RTCC */
+#define _PROTIMER_CMD_RTCSYNCSTART_SHIFT 1 /**< Shift value for PROTIMER_RTCSYNCSTART */
+#define _PROTIMER_CMD_RTCSYNCSTART_MASK 0x2UL /**< Bit mask for PROTIMER_RTCSYNCSTART */
+#define _PROTIMER_CMD_RTCSYNCSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CMD */
+#define PROTIMER_CMD_RTCSYNCSTART_DEFAULT (_PROTIMER_CMD_RTCSYNCSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for PROTIMER_CMD */
+#define PROTIMER_CMD_STOP (0x1UL << 2) /**< Stop PROTIMER */
+#define _PROTIMER_CMD_STOP_SHIFT 2 /**< Shift value for PROTIMER_STOP */
+#define _PROTIMER_CMD_STOP_MASK 0x4UL /**< Bit mask for PROTIMER_STOP */
+#define _PROTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CMD */
+#define PROTIMER_CMD_STOP_DEFAULT (_PROTIMER_CMD_STOP_DEFAULT << 2) /**< Shifted mode DEFAULT for PROTIMER_CMD */
+#define PROTIMER_CMD_TOUT0START (0x1UL << 4) /**< Start Timeout counter 0 */
+#define _PROTIMER_CMD_TOUT0START_SHIFT 4 /**< Shift value for PROTIMER_TOUT0START */
+#define _PROTIMER_CMD_TOUT0START_MASK 0x10UL /**< Bit mask for PROTIMER_TOUT0START */
+#define _PROTIMER_CMD_TOUT0START_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CMD */
+#define PROTIMER_CMD_TOUT0START_DEFAULT (_PROTIMER_CMD_TOUT0START_DEFAULT << 4) /**< Shifted mode DEFAULT for PROTIMER_CMD */
+#define PROTIMER_CMD_TOUT0STOP (0x1UL << 5) /**< Stop Timeout counter 0 */
+#define _PROTIMER_CMD_TOUT0STOP_SHIFT 5 /**< Shift value for PROTIMER_TOUT0STOP */
+#define _PROTIMER_CMD_TOUT0STOP_MASK 0x20UL /**< Bit mask for PROTIMER_TOUT0STOP */
+#define _PROTIMER_CMD_TOUT0STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CMD */
+#define PROTIMER_CMD_TOUT0STOP_DEFAULT (_PROTIMER_CMD_TOUT0STOP_DEFAULT << 5) /**< Shifted mode DEFAULT for PROTIMER_CMD */
+#define PROTIMER_CMD_TOUT1START (0x1UL << 6) /**< Start Timeout counter 1 */
+#define _PROTIMER_CMD_TOUT1START_SHIFT 6 /**< Shift value for PROTIMER_TOUT1START */
+#define _PROTIMER_CMD_TOUT1START_MASK 0x40UL /**< Bit mask for PROTIMER_TOUT1START */
+#define _PROTIMER_CMD_TOUT1START_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CMD */
+#define PROTIMER_CMD_TOUT1START_DEFAULT (_PROTIMER_CMD_TOUT1START_DEFAULT << 6) /**< Shifted mode DEFAULT for PROTIMER_CMD */
+#define PROTIMER_CMD_TOUT1STOP (0x1UL << 7) /**< Stop Timeout counter 0 */
+#define _PROTIMER_CMD_TOUT1STOP_SHIFT 7 /**< Shift value for PROTIMER_TOUT1STOP */
+#define _PROTIMER_CMD_TOUT1STOP_MASK 0x80UL /**< Bit mask for PROTIMER_TOUT1STOP */
+#define _PROTIMER_CMD_TOUT1STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CMD */
+#define PROTIMER_CMD_TOUT1STOP_DEFAULT (_PROTIMER_CMD_TOUT1STOP_DEFAULT << 7) /**< Shifted mode DEFAULT for PROTIMER_CMD */
+#define PROTIMER_CMD_FORCETXIDLE (0x1UL << 8) /**< Force to Idle state of tx_state */
+#define _PROTIMER_CMD_FORCETXIDLE_SHIFT 8 /**< Shift value for PROTIMER_FORCETXIDLE */
+#define _PROTIMER_CMD_FORCETXIDLE_MASK 0x100UL /**< Bit mask for PROTIMER_FORCETXIDLE */
+#define _PROTIMER_CMD_FORCETXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CMD */
+#define PROTIMER_CMD_FORCETXIDLE_DEFAULT (_PROTIMER_CMD_FORCETXIDLE_DEFAULT << 8) /**< Shifted mode DEFAULT for PROTIMER_CMD */
+#define PROTIMER_CMD_FORCERXIDLE (0x1UL << 9) /**< Force to Idle state of rx_state */
+#define _PROTIMER_CMD_FORCERXIDLE_SHIFT 9 /**< Shift value for PROTIMER_FORCERXIDLE */
+#define _PROTIMER_CMD_FORCERXIDLE_MASK 0x200UL /**< Bit mask for PROTIMER_FORCERXIDLE */
+#define _PROTIMER_CMD_FORCERXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CMD */
+#define PROTIMER_CMD_FORCERXIDLE_DEFAULT (_PROTIMER_CMD_FORCERXIDLE_DEFAULT << 9) /**< Shifted mode DEFAULT for PROTIMER_CMD */
+#define PROTIMER_CMD_FORCERXRX (0x1UL << 10) /**< Force to Rx state of rx_state */
+#define _PROTIMER_CMD_FORCERXRX_SHIFT 10 /**< Shift value for PROTIMER_FORCERXRX */
+#define _PROTIMER_CMD_FORCERXRX_MASK 0x400UL /**< Bit mask for PROTIMER_FORCERXRX */
+#define _PROTIMER_CMD_FORCERXRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CMD */
+#define PROTIMER_CMD_FORCERXRX_DEFAULT (_PROTIMER_CMD_FORCERXRX_DEFAULT << 10) /**< Shifted mode DEFAULT for PROTIMER_CMD */
+#define PROTIMER_CMD_LBTSTART (0x1UL << 16) /**< LBT sequence start */
+#define _PROTIMER_CMD_LBTSTART_SHIFT 16 /**< Shift value for PROTIMER_LBTSTART */
+#define _PROTIMER_CMD_LBTSTART_MASK 0x10000UL /**< Bit mask for PROTIMER_LBTSTART */
+#define _PROTIMER_CMD_LBTSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CMD */
+#define PROTIMER_CMD_LBTSTART_DEFAULT (_PROTIMER_CMD_LBTSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_CMD */
+#define PROTIMER_CMD_LBTPAUSE (0x1UL << 17) /**< Pause LBT sequence */
+#define _PROTIMER_CMD_LBTPAUSE_SHIFT 17 /**< Shift value for PROTIMER_LBTPAUSE */
+#define _PROTIMER_CMD_LBTPAUSE_MASK 0x20000UL /**< Bit mask for PROTIMER_LBTPAUSE */
+#define _PROTIMER_CMD_LBTPAUSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CMD */
+#define PROTIMER_CMD_LBTPAUSE_DEFAULT (_PROTIMER_CMD_LBTPAUSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PROTIMER_CMD */
+#define PROTIMER_CMD_LBTSTOP (0x1UL << 18) /**< LBT sequence stop */
+#define _PROTIMER_CMD_LBTSTOP_SHIFT 18 /**< Shift value for PROTIMER_LBTSTOP */
+#define _PROTIMER_CMD_LBTSTOP_MASK 0x40000UL /**< Bit mask for PROTIMER_LBTSTOP */
+#define _PROTIMER_CMD_LBTSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CMD */
+#define PROTIMER_CMD_LBTSTOP_DEFAULT (_PROTIMER_CMD_LBTSTOP_DEFAULT << 18) /**< Shifted mode DEFAULT for PROTIMER_CMD */
+
+/* Bit fields for PROTIMER PRSCTRL */
+#define _PROTIMER_PRSCTRL_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_PRSCTRL */
+#define _PROTIMER_PRSCTRL_MASK 0x000E0E0EUL /**< Mask for PROTIMER_PRSCTRL */
+#define PROTIMER_PRSCTRL_STARTPRSEN (0x1UL << 1) /**< Enable Protimer start commands from PRS. */
+#define _PROTIMER_PRSCTRL_STARTPRSEN_SHIFT 1 /**< Shift value for PROTIMER_STARTPRSEN */
+#define _PROTIMER_PRSCTRL_STARTPRSEN_MASK 0x2UL /**< Bit mask for PROTIMER_STARTPRSEN */
+#define _PROTIMER_PRSCTRL_STARTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_PRSCTRL */
+#define PROTIMER_PRSCTRL_STARTPRSEN_DEFAULT (_PROTIMER_PRSCTRL_STARTPRSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PROTIMER_PRSCTRL */
+#define _PROTIMER_PRSCTRL_STARTEDGE_SHIFT 2 /**< Shift value for PROTIMER_STARTEDGE */
+#define _PROTIMER_PRSCTRL_STARTEDGE_MASK 0xCUL /**< Bit mask for PROTIMER_STARTEDGE */
+#define _PROTIMER_PRSCTRL_STARTEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_PRSCTRL */
+#define _PROTIMER_PRSCTRL_STARTEDGE_RISING 0x00000000UL /**< Mode RISING for PROTIMER_PRSCTRL */
+#define _PROTIMER_PRSCTRL_STARTEDGE_FALLING 0x00000001UL /**< Mode FALLING for PROTIMER_PRSCTRL */
+#define _PROTIMER_PRSCTRL_STARTEDGE_BOTH 0x00000002UL /**< Mode BOTH for PROTIMER_PRSCTRL */
+#define _PROTIMER_PRSCTRL_STARTEDGE_DISABLED 0x00000003UL /**< Mode DISABLED for PROTIMER_PRSCTRL */
+#define PROTIMER_PRSCTRL_STARTEDGE_DEFAULT (_PROTIMER_PRSCTRL_STARTEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for PROTIMER_PRSCTRL */
+#define PROTIMER_PRSCTRL_STARTEDGE_RISING (_PROTIMER_PRSCTRL_STARTEDGE_RISING << 2) /**< Shifted mode RISING for PROTIMER_PRSCTRL */
+#define PROTIMER_PRSCTRL_STARTEDGE_FALLING (_PROTIMER_PRSCTRL_STARTEDGE_FALLING << 2) /**< Shifted mode FALLING for PROTIMER_PRSCTRL */
+#define PROTIMER_PRSCTRL_STARTEDGE_BOTH (_PROTIMER_PRSCTRL_STARTEDGE_BOTH << 2) /**< Shifted mode BOTH for PROTIMER_PRSCTRL */
+#define PROTIMER_PRSCTRL_STARTEDGE_DISABLED (_PROTIMER_PRSCTRL_STARTEDGE_DISABLED << 2) /**< Shifted mode DISABLED for PROTIMER_PRSCTRL */
+#define PROTIMER_PRSCTRL_STOPPRSEN (0x1UL << 9) /**< Enable Protimer stop commands from PRS. */
+#define _PROTIMER_PRSCTRL_STOPPRSEN_SHIFT 9 /**< Shift value for PROTIMER_STOPPRSEN */
+#define _PROTIMER_PRSCTRL_STOPPRSEN_MASK 0x200UL /**< Bit mask for PROTIMER_STOPPRSEN */
+#define _PROTIMER_PRSCTRL_STOPPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_PRSCTRL */
+#define PROTIMER_PRSCTRL_STOPPRSEN_DEFAULT (_PROTIMER_PRSCTRL_STOPPRSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PROTIMER_PRSCTRL */
+#define _PROTIMER_PRSCTRL_STOPEDGE_SHIFT 10 /**< Shift value for PROTIMER_STOPEDGE */
+#define _PROTIMER_PRSCTRL_STOPEDGE_MASK 0xC00UL /**< Bit mask for PROTIMER_STOPEDGE */
+#define _PROTIMER_PRSCTRL_STOPEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_PRSCTRL */
+#define _PROTIMER_PRSCTRL_STOPEDGE_RISING 0x00000000UL /**< Mode RISING for PROTIMER_PRSCTRL */
+#define _PROTIMER_PRSCTRL_STOPEDGE_FALLING 0x00000001UL /**< Mode FALLING for PROTIMER_PRSCTRL */
+#define _PROTIMER_PRSCTRL_STOPEDGE_BOTH 0x00000002UL /**< Mode BOTH for PROTIMER_PRSCTRL */
+#define _PROTIMER_PRSCTRL_STOPEDGE_DISABLED 0x00000003UL /**< Mode DISABLED for PROTIMER_PRSCTRL */
+#define PROTIMER_PRSCTRL_STOPEDGE_DEFAULT (_PROTIMER_PRSCTRL_STOPEDGE_DEFAULT << 10) /**< Shifted mode DEFAULT for PROTIMER_PRSCTRL */
+#define PROTIMER_PRSCTRL_STOPEDGE_RISING (_PROTIMER_PRSCTRL_STOPEDGE_RISING << 10) /**< Shifted mode RISING for PROTIMER_PRSCTRL */
+#define PROTIMER_PRSCTRL_STOPEDGE_FALLING (_PROTIMER_PRSCTRL_STOPEDGE_FALLING << 10) /**< Shifted mode FALLING for PROTIMER_PRSCTRL */
+#define PROTIMER_PRSCTRL_STOPEDGE_BOTH (_PROTIMER_PRSCTRL_STOPEDGE_BOTH << 10) /**< Shifted mode BOTH for PROTIMER_PRSCTRL */
+#define PROTIMER_PRSCTRL_STOPEDGE_DISABLED (_PROTIMER_PRSCTRL_STOPEDGE_DISABLED << 10) /**< Shifted mode DISABLED for PROTIMER_PRSCTRL */
+#define PROTIMER_PRSCTRL_RTCCTRIGGERPRSEN (0x1UL << 17) /**< Enable RTCC Trigger from PRS. */
+#define _PROTIMER_PRSCTRL_RTCCTRIGGERPRSEN_SHIFT 17 /**< Shift value for PROTIMER_RTCCTRIGGERPRSEN */
+#define _PROTIMER_PRSCTRL_RTCCTRIGGERPRSEN_MASK 0x20000UL /**< Bit mask for PROTIMER_RTCCTRIGGERPRSEN */
+#define _PROTIMER_PRSCTRL_RTCCTRIGGERPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_PRSCTRL */
+#define PROTIMER_PRSCTRL_RTCCTRIGGERPRSEN_DEFAULT (_PROTIMER_PRSCTRL_RTCCTRIGGERPRSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PROTIMER_PRSCTRL */
+#define _PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_SHIFT 18 /**< Shift value for PROTIMER_RTCCTRIGGEREDGE */
+#define _PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_MASK 0xC0000UL /**< Bit mask for PROTIMER_RTCCTRIGGEREDGE */
+#define _PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_PRSCTRL */
+#define _PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_RISING 0x00000000UL /**< Mode RISING for PROTIMER_PRSCTRL */
+#define _PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_FALLING 0x00000001UL /**< Mode FALLING for PROTIMER_PRSCTRL */
+#define _PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_BOTH 0x00000002UL /**< Mode BOTH for PROTIMER_PRSCTRL */
+#define _PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_DISABLED 0x00000003UL /**< Mode DISABLED for PROTIMER_PRSCTRL */
+#define PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_DEFAULT (_PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_DEFAULT << 18) /**< Shifted mode DEFAULT for PROTIMER_PRSCTRL */
+#define PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_RISING (_PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_RISING << 18) /**< Shifted mode RISING for PROTIMER_PRSCTRL */
+#define PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_FALLING (_PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_FALLING << 18) /**< Shifted mode FALLING for PROTIMER_PRSCTRL */
+#define PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_BOTH (_PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_BOTH << 18) /**< Shifted mode BOTH for PROTIMER_PRSCTRL */
+#define PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_DISABLED (_PROTIMER_PRSCTRL_RTCCTRIGGEREDGE_DISABLED << 18) /**< Shifted mode DISABLED for PROTIMER_PRSCTRL */
+
+/* Bit fields for PROTIMER STATUS */
+#define _PROTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_STATUS */
+#define _PROTIMER_STATUS_MASK 0x0000FFFFUL /**< Mask for PROTIMER_STATUS */
+#define PROTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */
+#define _PROTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for PROTIMER_RUNNING */
+#define _PROTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for PROTIMER_RUNNING */
+#define _PROTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */
+#define PROTIMER_STATUS_RUNNING_DEFAULT (_PROTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_STATUS */
+#define PROTIMER_STATUS_LBTSYNC (0x1UL << 1) /**< LBT Synchronizing */
+#define _PROTIMER_STATUS_LBTSYNC_SHIFT 1 /**< Shift value for PROTIMER_LBTSYNC */
+#define _PROTIMER_STATUS_LBTSYNC_MASK 0x2UL /**< Bit mask for PROTIMER_LBTSYNC */
+#define _PROTIMER_STATUS_LBTSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */
+#define PROTIMER_STATUS_LBTSYNC_DEFAULT (_PROTIMER_STATUS_LBTSYNC_DEFAULT << 1) /**< Shifted mode DEFAULT for PROTIMER_STATUS */
+#define PROTIMER_STATUS_LBTRUNNING (0x1UL << 2) /**< LBT Running */
+#define _PROTIMER_STATUS_LBTRUNNING_SHIFT 2 /**< Shift value for PROTIMER_LBTRUNNING */
+#define _PROTIMER_STATUS_LBTRUNNING_MASK 0x4UL /**< Bit mask for PROTIMER_LBTRUNNING */
+#define _PROTIMER_STATUS_LBTRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */
+#define PROTIMER_STATUS_LBTRUNNING_DEFAULT (_PROTIMER_STATUS_LBTRUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for PROTIMER_STATUS */
+#define PROTIMER_STATUS_LBTPAUSED (0x1UL << 3) /**< LBT has been paused. */
+#define _PROTIMER_STATUS_LBTPAUSED_SHIFT 3 /**< Shift value for PROTIMER_LBTPAUSED */
+#define _PROTIMER_STATUS_LBTPAUSED_MASK 0x8UL /**< Bit mask for PROTIMER_LBTPAUSED */
+#define _PROTIMER_STATUS_LBTPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */
+#define PROTIMER_STATUS_LBTPAUSED_DEFAULT (_PROTIMER_STATUS_LBTPAUSED_DEFAULT << 3) /**< Shifted mode DEFAULT for PROTIMER_STATUS */
+#define PROTIMER_STATUS_TOUT0RUNNING (0x1UL << 4) /**< Timeout Counter 0 Running */
+#define _PROTIMER_STATUS_TOUT0RUNNING_SHIFT 4 /**< Shift value for PROTIMER_TOUT0RUNNING */
+#define _PROTIMER_STATUS_TOUT0RUNNING_MASK 0x10UL /**< Bit mask for PROTIMER_TOUT0RUNNING */
+#define _PROTIMER_STATUS_TOUT0RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */
+#define PROTIMER_STATUS_TOUT0RUNNING_DEFAULT (_PROTIMER_STATUS_TOUT0RUNNING_DEFAULT << 4) /**< Shifted mode DEFAULT for PROTIMER_STATUS */
+#define PROTIMER_STATUS_TOUT0SYNC (0x1UL << 5) /**< Timeout Counter 0 Synchronizing */
+#define _PROTIMER_STATUS_TOUT0SYNC_SHIFT 5 /**< Shift value for PROTIMER_TOUT0SYNC */
+#define _PROTIMER_STATUS_TOUT0SYNC_MASK 0x20UL /**< Bit mask for PROTIMER_TOUT0SYNC */
+#define _PROTIMER_STATUS_TOUT0SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */
+#define PROTIMER_STATUS_TOUT0SYNC_DEFAULT (_PROTIMER_STATUS_TOUT0SYNC_DEFAULT << 5) /**< Shifted mode DEFAULT for PROTIMER_STATUS */
+#define PROTIMER_STATUS_TOUT1RUNNING (0x1UL << 6) /**< Timeout Counter 1 Running */
+#define _PROTIMER_STATUS_TOUT1RUNNING_SHIFT 6 /**< Shift value for PROTIMER_TOUT1RUNNING */
+#define _PROTIMER_STATUS_TOUT1RUNNING_MASK 0x40UL /**< Bit mask for PROTIMER_TOUT1RUNNING */
+#define _PROTIMER_STATUS_TOUT1RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */
+#define PROTIMER_STATUS_TOUT1RUNNING_DEFAULT (_PROTIMER_STATUS_TOUT1RUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for PROTIMER_STATUS */
+#define PROTIMER_STATUS_TOUT1SYNC (0x1UL << 7) /**< Timeout Counter 1 Synchronizing */
+#define _PROTIMER_STATUS_TOUT1SYNC_SHIFT 7 /**< Shift value for PROTIMER_TOUT1SYNC */
+#define _PROTIMER_STATUS_TOUT1SYNC_MASK 0x80UL /**< Bit mask for PROTIMER_TOUT1SYNC */
+#define _PROTIMER_STATUS_TOUT1SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */
+#define PROTIMER_STATUS_TOUT1SYNC_DEFAULT (_PROTIMER_STATUS_TOUT1SYNC_DEFAULT << 7) /**< Shifted mode DEFAULT for PROTIMER_STATUS */
+#define PROTIMER_STATUS_ICV0 (0x1UL << 8) /**< CC0 Capture Valid */
+#define _PROTIMER_STATUS_ICV0_SHIFT 8 /**< Shift value for PROTIMER_ICV0 */
+#define _PROTIMER_STATUS_ICV0_MASK 0x100UL /**< Bit mask for PROTIMER_ICV0 */
+#define _PROTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */
+#define _PROTIMER_STATUS_ICV0_X0 0x00000000UL /**< Mode X0 for PROTIMER_STATUS */
+#define _PROTIMER_STATUS_ICV0_X1 0x00000001UL /**< Mode X1 for PROTIMER_STATUS */
+#define PROTIMER_STATUS_ICV0_DEFAULT (_PROTIMER_STATUS_ICV0_DEFAULT << 8) /**< Shifted mode DEFAULT for PROTIMER_STATUS */
+#define PROTIMER_STATUS_ICV0_X0 (_PROTIMER_STATUS_ICV0_X0 << 8) /**< Shifted mode X0 for PROTIMER_STATUS */
+#define PROTIMER_STATUS_ICV0_X1 (_PROTIMER_STATUS_ICV0_X1 << 8) /**< Shifted mode X1 for PROTIMER_STATUS */
+#define PROTIMER_STATUS_ICV1 (0x1UL << 9) /**< CC1 Capture Valid */
+#define _PROTIMER_STATUS_ICV1_SHIFT 9 /**< Shift value for PROTIMER_ICV1 */
+#define _PROTIMER_STATUS_ICV1_MASK 0x200UL /**< Bit mask for PROTIMER_ICV1 */
+#define _PROTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */
+#define _PROTIMER_STATUS_ICV1_X0 0x00000000UL /**< Mode X0 for PROTIMER_STATUS */
+#define _PROTIMER_STATUS_ICV1_X1 0x00000001UL /**< Mode X1 for PROTIMER_STATUS */
+#define PROTIMER_STATUS_ICV1_DEFAULT (_PROTIMER_STATUS_ICV1_DEFAULT << 9) /**< Shifted mode DEFAULT for PROTIMER_STATUS */
+#define PROTIMER_STATUS_ICV1_X0 (_PROTIMER_STATUS_ICV1_X0 << 9) /**< Shifted mode X0 for PROTIMER_STATUS */
+#define PROTIMER_STATUS_ICV1_X1 (_PROTIMER_STATUS_ICV1_X1 << 9) /**< Shifted mode X1 for PROTIMER_STATUS */
+#define PROTIMER_STATUS_ICV2 (0x1UL << 10) /**< CC2 Capture Valid */
+#define _PROTIMER_STATUS_ICV2_SHIFT 10 /**< Shift value for PROTIMER_ICV2 */
+#define _PROTIMER_STATUS_ICV2_MASK 0x400UL /**< Bit mask for PROTIMER_ICV2 */
+#define _PROTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */
+#define _PROTIMER_STATUS_ICV2_X0 0x00000000UL /**< Mode X0 for PROTIMER_STATUS */
+#define _PROTIMER_STATUS_ICV2_X1 0x00000001UL /**< Mode X1 for PROTIMER_STATUS */
+#define PROTIMER_STATUS_ICV2_DEFAULT (_PROTIMER_STATUS_ICV2_DEFAULT << 10) /**< Shifted mode DEFAULT for PROTIMER_STATUS */
+#define PROTIMER_STATUS_ICV2_X0 (_PROTIMER_STATUS_ICV2_X0 << 10) /**< Shifted mode X0 for PROTIMER_STATUS */
+#define PROTIMER_STATUS_ICV2_X1 (_PROTIMER_STATUS_ICV2_X1 << 10) /**< Shifted mode X1 for PROTIMER_STATUS */
+#define PROTIMER_STATUS_ICV3 (0x1UL << 11) /**< CC3 Capture Valid */
+#define _PROTIMER_STATUS_ICV3_SHIFT 11 /**< Shift value for PROTIMER_ICV3 */
+#define _PROTIMER_STATUS_ICV3_MASK 0x800UL /**< Bit mask for PROTIMER_ICV3 */
+#define _PROTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */
+#define _PROTIMER_STATUS_ICV3_X0 0x00000000UL /**< Mode X0 for PROTIMER_STATUS */
+#define _PROTIMER_STATUS_ICV3_X1 0x00000001UL /**< Mode X1 for PROTIMER_STATUS */
+#define PROTIMER_STATUS_ICV3_DEFAULT (_PROTIMER_STATUS_ICV3_DEFAULT << 11) /**< Shifted mode DEFAULT for PROTIMER_STATUS */
+#define PROTIMER_STATUS_ICV3_X0 (_PROTIMER_STATUS_ICV3_X0 << 11) /**< Shifted mode X0 for PROTIMER_STATUS */
+#define PROTIMER_STATUS_ICV3_X1 (_PROTIMER_STATUS_ICV3_X1 << 11) /**< Shifted mode X1 for PROTIMER_STATUS */
+#define PROTIMER_STATUS_ICV4 (0x1UL << 12) /**< CC4 Capture Valid */
+#define _PROTIMER_STATUS_ICV4_SHIFT 12 /**< Shift value for PROTIMER_ICV4 */
+#define _PROTIMER_STATUS_ICV4_MASK 0x1000UL /**< Bit mask for PROTIMER_ICV4 */
+#define _PROTIMER_STATUS_ICV4_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */
+#define _PROTIMER_STATUS_ICV4_X0 0x00000000UL /**< Mode X0 for PROTIMER_STATUS */
+#define _PROTIMER_STATUS_ICV4_X1 0x00000001UL /**< Mode X1 for PROTIMER_STATUS */
+#define PROTIMER_STATUS_ICV4_DEFAULT (_PROTIMER_STATUS_ICV4_DEFAULT << 12) /**< Shifted mode DEFAULT for PROTIMER_STATUS */
+#define PROTIMER_STATUS_ICV4_X0 (_PROTIMER_STATUS_ICV4_X0 << 12) /**< Shifted mode X0 for PROTIMER_STATUS */
+#define PROTIMER_STATUS_ICV4_X1 (_PROTIMER_STATUS_ICV4_X1 << 12) /**< Shifted mode X1 for PROTIMER_STATUS */
+#define PROTIMER_STATUS_ICV5 (0x1UL << 13) /**< CC5 Capture Valid */
+#define _PROTIMER_STATUS_ICV5_SHIFT 13 /**< Shift value for PROTIMER_ICV5 */
+#define _PROTIMER_STATUS_ICV5_MASK 0x2000UL /**< Bit mask for PROTIMER_ICV5 */
+#define _PROTIMER_STATUS_ICV5_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */
+#define PROTIMER_STATUS_ICV5_DEFAULT (_PROTIMER_STATUS_ICV5_DEFAULT << 13) /**< Shifted mode DEFAULT for PROTIMER_STATUS */
+#define PROTIMER_STATUS_ICV6 (0x1UL << 14) /**< CC6 Capture Valid */
+#define _PROTIMER_STATUS_ICV6_SHIFT 14 /**< Shift value for PROTIMER_ICV6 */
+#define _PROTIMER_STATUS_ICV6_MASK 0x4000UL /**< Bit mask for PROTIMER_ICV6 */
+#define _PROTIMER_STATUS_ICV6_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */
+#define PROTIMER_STATUS_ICV6_DEFAULT (_PROTIMER_STATUS_ICV6_DEFAULT << 14) /**< Shifted mode DEFAULT for PROTIMER_STATUS */
+#define PROTIMER_STATUS_ICV7 (0x1UL << 15) /**< CC7 Capture Valid */
+#define _PROTIMER_STATUS_ICV7_SHIFT 15 /**< Shift value for PROTIMER_ICV7 */
+#define _PROTIMER_STATUS_ICV7_MASK 0x8000UL /**< Bit mask for PROTIMER_ICV7 */
+#define _PROTIMER_STATUS_ICV7_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_STATUS */
+#define PROTIMER_STATUS_ICV7_DEFAULT (_PROTIMER_STATUS_ICV7_DEFAULT << 15) /**< Shifted mode DEFAULT for PROTIMER_STATUS */
+
+/* Bit fields for PROTIMER PRECNT */
+#define _PROTIMER_PRECNT_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_PRECNT */
+#define _PROTIMER_PRECNT_MASK 0x0000FFFFUL /**< Mask for PROTIMER_PRECNT */
+#define _PROTIMER_PRECNT_PRECNT_SHIFT 0 /**< Shift value for PROTIMER_PRECNT */
+#define _PROTIMER_PRECNT_PRECNT_MASK 0xFFFFUL /**< Bit mask for PROTIMER_PRECNT */
+#define _PROTIMER_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_PRECNT */
+#define PROTIMER_PRECNT_PRECNT_DEFAULT (_PROTIMER_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_PRECNT */
+
+/* Bit fields for PROTIMER BASECNT */
+#define _PROTIMER_BASECNT_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_BASECNT */
+#define _PROTIMER_BASECNT_MASK 0x0000FFFFUL /**< Mask for PROTIMER_BASECNT */
+#define _PROTIMER_BASECNT_BASECNT_SHIFT 0 /**< Shift value for PROTIMER_BASECNT */
+#define _PROTIMER_BASECNT_BASECNT_MASK 0xFFFFUL /**< Bit mask for PROTIMER_BASECNT */
+#define _PROTIMER_BASECNT_BASECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_BASECNT */
+#define PROTIMER_BASECNT_BASECNT_DEFAULT (_PROTIMER_BASECNT_BASECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_BASECNT */
+
+/* Bit fields for PROTIMER WRAPCNT */
+#define _PROTIMER_WRAPCNT_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_WRAPCNT */
+#define _PROTIMER_WRAPCNT_MASK 0xFFFFFFFFUL /**< Mask for PROTIMER_WRAPCNT */
+#define _PROTIMER_WRAPCNT_WRAPCNT_SHIFT 0 /**< Shift value for PROTIMER_WRAPCNT */
+#define _PROTIMER_WRAPCNT_WRAPCNT_MASK 0xFFFFFFFFUL /**< Bit mask for PROTIMER_WRAPCNT */
+#define _PROTIMER_WRAPCNT_WRAPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_WRAPCNT */
+#define PROTIMER_WRAPCNT_WRAPCNT_DEFAULT (_PROTIMER_WRAPCNT_WRAPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_WRAPCNT */
+
+/* Bit fields for PROTIMER BASEPRE */
+#define _PROTIMER_BASEPRE_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_BASEPRE */
+#define _PROTIMER_BASEPRE_MASK 0xFFFFFFFFUL /**< Mask for PROTIMER_BASEPRE */
+#define _PROTIMER_BASEPRE_PRECNTV_SHIFT 0 /**< Shift value for PROTIMER_PRECNTV */
+#define _PROTIMER_BASEPRE_PRECNTV_MASK 0xFFFFUL /**< Bit mask for PROTIMER_PRECNTV */
+#define _PROTIMER_BASEPRE_PRECNTV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_BASEPRE */
+#define PROTIMER_BASEPRE_PRECNTV_DEFAULT (_PROTIMER_BASEPRE_PRECNTV_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_BASEPRE */
+#define _PROTIMER_BASEPRE_BASECNTV_SHIFT 16 /**< Shift value for PROTIMER_BASECNTV */
+#define _PROTIMER_BASEPRE_BASECNTV_MASK 0xFFFF0000UL /**< Bit mask for PROTIMER_BASECNTV */
+#define _PROTIMER_BASEPRE_BASECNTV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_BASEPRE */
+#define PROTIMER_BASEPRE_BASECNTV_DEFAULT (_PROTIMER_BASEPRE_BASECNTV_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_BASEPRE */
+
+/* Bit fields for PROTIMER LWRAPCNT */
+#define _PROTIMER_LWRAPCNT_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_LWRAPCNT */
+#define _PROTIMER_LWRAPCNT_MASK 0xFFFFFFFFUL /**< Mask for PROTIMER_LWRAPCNT */
+#define _PROTIMER_LWRAPCNT_LWRAPCNT_SHIFT 0 /**< Shift value for PROTIMER_LWRAPCNT */
+#define _PROTIMER_LWRAPCNT_LWRAPCNT_MASK 0xFFFFFFFFUL /**< Bit mask for PROTIMER_LWRAPCNT */
+#define _PROTIMER_LWRAPCNT_LWRAPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_LWRAPCNT */
+#define PROTIMER_LWRAPCNT_LWRAPCNT_DEFAULT (_PROTIMER_LWRAPCNT_LWRAPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_LWRAPCNT */
+
+/* Bit fields for PROTIMER PRECNTTOPADJ */
+#define _PROTIMER_PRECNTTOPADJ_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_PRECNTTOPADJ */
+#define _PROTIMER_PRECNTTOPADJ_MASK 0x0000FFFFUL /**< Mask for PROTIMER_PRECNTTOPADJ */
+#define _PROTIMER_PRECNTTOPADJ_PRECNTTOPADJ_SHIFT 0 /**< Shift value for PROTIMER_PRECNTTOPADJ */
+#define _PROTIMER_PRECNTTOPADJ_PRECNTTOPADJ_MASK 0xFFFFUL /**< Bit mask for PROTIMER_PRECNTTOPADJ */
+#define _PROTIMER_PRECNTTOPADJ_PRECNTTOPADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_PRECNTTOPADJ */
+#define PROTIMER_PRECNTTOPADJ_PRECNTTOPADJ_DEFAULT (_PROTIMER_PRECNTTOPADJ_PRECNTTOPADJ_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_PRECNTTOPADJ*/
+
+/* Bit fields for PROTIMER PRECNTTOP */
+#define _PROTIMER_PRECNTTOP_RESETVALUE 0x00FFFF00UL /**< Default value for PROTIMER_PRECNTTOP */
+#define _PROTIMER_PRECNTTOP_MASK 0x00FFFFFFUL /**< Mask for PROTIMER_PRECNTTOP */
+#define _PROTIMER_PRECNTTOP_PRECNTTOPFRAC_SHIFT 0 /**< Shift value for PROTIMER_PRECNTTOPFRAC */
+#define _PROTIMER_PRECNTTOP_PRECNTTOPFRAC_MASK 0xFFUL /**< Bit mask for PROTIMER_PRECNTTOPFRAC */
+#define _PROTIMER_PRECNTTOP_PRECNTTOPFRAC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_PRECNTTOP */
+#define PROTIMER_PRECNTTOP_PRECNTTOPFRAC_DEFAULT (_PROTIMER_PRECNTTOP_PRECNTTOPFRAC_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_PRECNTTOP */
+#define _PROTIMER_PRECNTTOP_PRECNTTOP_SHIFT 8 /**< Shift value for PROTIMER_PRECNTTOP */
+#define _PROTIMER_PRECNTTOP_PRECNTTOP_MASK 0xFFFF00UL /**< Bit mask for PROTIMER_PRECNTTOP */
+#define _PROTIMER_PRECNTTOP_PRECNTTOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for PROTIMER_PRECNTTOP */
+#define PROTIMER_PRECNTTOP_PRECNTTOP_DEFAULT (_PROTIMER_PRECNTTOP_PRECNTTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for PROTIMER_PRECNTTOP */
+
+/* Bit fields for PROTIMER BASECNTTOP */
+#define _PROTIMER_BASECNTTOP_RESETVALUE 0x0000FFFFUL /**< Default value for PROTIMER_BASECNTTOP */
+#define _PROTIMER_BASECNTTOP_MASK 0x0000FFFFUL /**< Mask for PROTIMER_BASECNTTOP */
+#define _PROTIMER_BASECNTTOP_BASECNTTOP_SHIFT 0 /**< Shift value for PROTIMER_BASECNTTOP */
+#define _PROTIMER_BASECNTTOP_BASECNTTOP_MASK 0xFFFFUL /**< Bit mask for PROTIMER_BASECNTTOP */
+#define _PROTIMER_BASECNTTOP_BASECNTTOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for PROTIMER_BASECNTTOP */
+#define PROTIMER_BASECNTTOP_BASECNTTOP_DEFAULT (_PROTIMER_BASECNTTOP_BASECNTTOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_BASECNTTOP*/
+
+/* Bit fields for PROTIMER WRAPCNTTOP */
+#define _PROTIMER_WRAPCNTTOP_RESETVALUE 0xFFFFFFFFUL /**< Default value for PROTIMER_WRAPCNTTOP */
+#define _PROTIMER_WRAPCNTTOP_MASK 0xFFFFFFFFUL /**< Mask for PROTIMER_WRAPCNTTOP */
+#define _PROTIMER_WRAPCNTTOP_WRAPCNTTOP_SHIFT 0 /**< Shift value for PROTIMER_WRAPCNTTOP */
+#define _PROTIMER_WRAPCNTTOP_WRAPCNTTOP_MASK 0xFFFFFFFFUL /**< Bit mask for PROTIMER_WRAPCNTTOP */
+#define _PROTIMER_WRAPCNTTOP_WRAPCNTTOP_DEFAULT 0xFFFFFFFFUL /**< Mode DEFAULT for PROTIMER_WRAPCNTTOP */
+#define PROTIMER_WRAPCNTTOP_WRAPCNTTOP_DEFAULT (_PROTIMER_WRAPCNTTOP_WRAPCNTTOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_WRAPCNTTOP*/
+
+/* Bit fields for PROTIMER TOUT0CNT */
+#define _PROTIMER_TOUT0CNT_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_TOUT0CNT */
+#define _PROTIMER_TOUT0CNT_MASK 0xFFFFFFFFUL /**< Mask for PROTIMER_TOUT0CNT */
+#define _PROTIMER_TOUT0CNT_TOUT0PCNT_SHIFT 0 /**< Shift value for PROTIMER_TOUT0PCNT */
+#define _PROTIMER_TOUT0CNT_TOUT0PCNT_MASK 0xFFFFUL /**< Bit mask for PROTIMER_TOUT0PCNT */
+#define _PROTIMER_TOUT0CNT_TOUT0PCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_TOUT0CNT */
+#define PROTIMER_TOUT0CNT_TOUT0PCNT_DEFAULT (_PROTIMER_TOUT0CNT_TOUT0PCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_TOUT0CNT */
+#define _PROTIMER_TOUT0CNT_TOUT0CNT_SHIFT 16 /**< Shift value for PROTIMER_TOUT0CNT */
+#define _PROTIMER_TOUT0CNT_TOUT0CNT_MASK 0xFFFF0000UL /**< Bit mask for PROTIMER_TOUT0CNT */
+#define _PROTIMER_TOUT0CNT_TOUT0CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_TOUT0CNT */
+#define PROTIMER_TOUT0CNT_TOUT0CNT_DEFAULT (_PROTIMER_TOUT0CNT_TOUT0CNT_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_TOUT0CNT */
+
+/* Bit fields for PROTIMER TOUT0CNTTOP */
+#define _PROTIMER_TOUT0CNTTOP_RESETVALUE 0x00FF00FFUL /**< Default value for PROTIMER_TOUT0CNTTOP */
+#define _PROTIMER_TOUT0CNTTOP_MASK 0xFFFFFFFFUL /**< Mask for PROTIMER_TOUT0CNTTOP */
+#define _PROTIMER_TOUT0CNTTOP_TOUT0PCNTTOP_SHIFT 0 /**< Shift value for PROTIMER_TOUT0PCNTTOP */
+#define _PROTIMER_TOUT0CNTTOP_TOUT0PCNTTOP_MASK 0xFFFFUL /**< Bit mask for PROTIMER_TOUT0PCNTTOP */
+#define _PROTIMER_TOUT0CNTTOP_TOUT0PCNTTOP_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PROTIMER_TOUT0CNTTOP */
+#define PROTIMER_TOUT0CNTTOP_TOUT0PCNTTOP_DEFAULT (_PROTIMER_TOUT0CNTTOP_TOUT0PCNTTOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_TOUT0CNTTOP*/
+#define _PROTIMER_TOUT0CNTTOP_TOUT0CNTTOP_SHIFT 16 /**< Shift value for PROTIMER_TOUT0CNTTOP */
+#define _PROTIMER_TOUT0CNTTOP_TOUT0CNTTOP_MASK 0xFFFF0000UL /**< Bit mask for PROTIMER_TOUT0CNTTOP */
+#define _PROTIMER_TOUT0CNTTOP_TOUT0CNTTOP_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PROTIMER_TOUT0CNTTOP */
+#define PROTIMER_TOUT0CNTTOP_TOUT0CNTTOP_DEFAULT (_PROTIMER_TOUT0CNTTOP_TOUT0CNTTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_TOUT0CNTTOP*/
+
+/* Bit fields for PROTIMER TOUT0COMP */
+#define _PROTIMER_TOUT0COMP_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_TOUT0COMP */
+#define _PROTIMER_TOUT0COMP_MASK 0xFFFFFFFFUL /**< Mask for PROTIMER_TOUT0COMP */
+#define _PROTIMER_TOUT0COMP_TOUT0PCNTCOMP_SHIFT 0 /**< Shift value for PROTIMER_TOUT0PCNTCOMP */
+#define _PROTIMER_TOUT0COMP_TOUT0PCNTCOMP_MASK 0xFFFFUL /**< Bit mask for PROTIMER_TOUT0PCNTCOMP */
+#define _PROTIMER_TOUT0COMP_TOUT0PCNTCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_TOUT0COMP */
+#define PROTIMER_TOUT0COMP_TOUT0PCNTCOMP_DEFAULT (_PROTIMER_TOUT0COMP_TOUT0PCNTCOMP_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_TOUT0COMP */
+#define _PROTIMER_TOUT0COMP_TOUT0CNTCOMP_SHIFT 16 /**< Shift value for PROTIMER_TOUT0CNTCOMP */
+#define _PROTIMER_TOUT0COMP_TOUT0CNTCOMP_MASK 0xFFFF0000UL /**< Bit mask for PROTIMER_TOUT0CNTCOMP */
+#define _PROTIMER_TOUT0COMP_TOUT0CNTCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_TOUT0COMP */
+#define PROTIMER_TOUT0COMP_TOUT0CNTCOMP_DEFAULT (_PROTIMER_TOUT0COMP_TOUT0CNTCOMP_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_TOUT0COMP */
+
+/* Bit fields for PROTIMER TOUT1CNT */
+#define _PROTIMER_TOUT1CNT_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_TOUT1CNT */
+#define _PROTIMER_TOUT1CNT_MASK 0xFFFFFFFFUL /**< Mask for PROTIMER_TOUT1CNT */
+#define _PROTIMER_TOUT1CNT_TOUT1PCNT_SHIFT 0 /**< Shift value for PROTIMER_TOUT1PCNT */
+#define _PROTIMER_TOUT1CNT_TOUT1PCNT_MASK 0xFFFFUL /**< Bit mask for PROTIMER_TOUT1PCNT */
+#define _PROTIMER_TOUT1CNT_TOUT1PCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_TOUT1CNT */
+#define PROTIMER_TOUT1CNT_TOUT1PCNT_DEFAULT (_PROTIMER_TOUT1CNT_TOUT1PCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_TOUT1CNT */
+#define _PROTIMER_TOUT1CNT_TOUT1CNT_SHIFT 16 /**< Shift value for PROTIMER_TOUT1CNT */
+#define _PROTIMER_TOUT1CNT_TOUT1CNT_MASK 0xFFFF0000UL /**< Bit mask for PROTIMER_TOUT1CNT */
+#define _PROTIMER_TOUT1CNT_TOUT1CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_TOUT1CNT */
+#define PROTIMER_TOUT1CNT_TOUT1CNT_DEFAULT (_PROTIMER_TOUT1CNT_TOUT1CNT_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_TOUT1CNT */
+
+/* Bit fields for PROTIMER TOUT1CNTTOP */
+#define _PROTIMER_TOUT1CNTTOP_RESETVALUE 0x00FF00FFUL /**< Default value for PROTIMER_TOUT1CNTTOP */
+#define _PROTIMER_TOUT1CNTTOP_MASK 0xFFFFFFFFUL /**< Mask for PROTIMER_TOUT1CNTTOP */
+#define _PROTIMER_TOUT1CNTTOP_TOUT1PCNTTOP_SHIFT 0 /**< Shift value for PROTIMER_TOUT1PCNTTOP */
+#define _PROTIMER_TOUT1CNTTOP_TOUT1PCNTTOP_MASK 0xFFFFUL /**< Bit mask for PROTIMER_TOUT1PCNTTOP */
+#define _PROTIMER_TOUT1CNTTOP_TOUT1PCNTTOP_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PROTIMER_TOUT1CNTTOP */
+#define PROTIMER_TOUT1CNTTOP_TOUT1PCNTTOP_DEFAULT (_PROTIMER_TOUT1CNTTOP_TOUT1PCNTTOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_TOUT1CNTTOP*/
+#define _PROTIMER_TOUT1CNTTOP_TOUT1CNTTOP_SHIFT 16 /**< Shift value for PROTIMER_TOUT1CNTTOP */
+#define _PROTIMER_TOUT1CNTTOP_TOUT1CNTTOP_MASK 0xFFFF0000UL /**< Bit mask for PROTIMER_TOUT1CNTTOP */
+#define _PROTIMER_TOUT1CNTTOP_TOUT1CNTTOP_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PROTIMER_TOUT1CNTTOP */
+#define PROTIMER_TOUT1CNTTOP_TOUT1CNTTOP_DEFAULT (_PROTIMER_TOUT1CNTTOP_TOUT1CNTTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_TOUT1CNTTOP*/
+
+/* Bit fields for PROTIMER TOUT1COMP */
+#define _PROTIMER_TOUT1COMP_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_TOUT1COMP */
+#define _PROTIMER_TOUT1COMP_MASK 0xFFFFFFFFUL /**< Mask for PROTIMER_TOUT1COMP */
+#define _PROTIMER_TOUT1COMP_TOUT1PCNTCOMP_SHIFT 0 /**< Shift value for PROTIMER_TOUT1PCNTCOMP */
+#define _PROTIMER_TOUT1COMP_TOUT1PCNTCOMP_MASK 0xFFFFUL /**< Bit mask for PROTIMER_TOUT1PCNTCOMP */
+#define _PROTIMER_TOUT1COMP_TOUT1PCNTCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_TOUT1COMP */
+#define PROTIMER_TOUT1COMP_TOUT1PCNTCOMP_DEFAULT (_PROTIMER_TOUT1COMP_TOUT1PCNTCOMP_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_TOUT1COMP */
+#define _PROTIMER_TOUT1COMP_TOUT1CNTCOMP_SHIFT 16 /**< Shift value for PROTIMER_TOUT1CNTCOMP */
+#define _PROTIMER_TOUT1COMP_TOUT1CNTCOMP_MASK 0xFFFF0000UL /**< Bit mask for PROTIMER_TOUT1CNTCOMP */
+#define _PROTIMER_TOUT1COMP_TOUT1CNTCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_TOUT1COMP */
+#define PROTIMER_TOUT1COMP_TOUT1CNTCOMP_DEFAULT (_PROTIMER_TOUT1COMP_TOUT1CNTCOMP_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_TOUT1COMP */
+
+/* Bit fields for PROTIMER LBTCTRL */
+#define _PROTIMER_LBTCTRL_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_LBTCTRL */
+#define _PROTIMER_LBTCTRL_MASK 0x0F1F1FFFUL /**< Mask for PROTIMER_LBTCTRL */
+#define _PROTIMER_LBTCTRL_STARTEXP_SHIFT 0 /**< Shift value for PROTIMER_STARTEXP */
+#define _PROTIMER_LBTCTRL_STARTEXP_MASK 0xFUL /**< Bit mask for PROTIMER_STARTEXP */
+#define _PROTIMER_LBTCTRL_STARTEXP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_LBTCTRL */
+#define _PROTIMER_LBTCTRL_STARTEXP_EXP0 0x00000000UL /**< Mode EXP0 for PROTIMER_LBTCTRL */
+#define _PROTIMER_LBTCTRL_STARTEXP_EXP1 0x00000001UL /**< Mode EXP1 for PROTIMER_LBTCTRL */
+#define _PROTIMER_LBTCTRL_STARTEXP_EXP2 0x00000002UL /**< Mode EXP2 for PROTIMER_LBTCTRL */
+#define _PROTIMER_LBTCTRL_STARTEXP_EXP3 0x00000003UL /**< Mode EXP3 for PROTIMER_LBTCTRL */
+#define _PROTIMER_LBTCTRL_STARTEXP_EXP4 0x00000004UL /**< Mode EXP4 for PROTIMER_LBTCTRL */
+#define _PROTIMER_LBTCTRL_STARTEXP_EXP5 0x00000005UL /**< Mode EXP5 for PROTIMER_LBTCTRL */
+#define _PROTIMER_LBTCTRL_STARTEXP_EXP6 0x00000006UL /**< Mode EXP6 for PROTIMER_LBTCTRL */
+#define _PROTIMER_LBTCTRL_STARTEXP_EXP7 0x00000007UL /**< Mode EXP7 for PROTIMER_LBTCTRL */
+#define _PROTIMER_LBTCTRL_STARTEXP_EXP8 0x00000008UL /**< Mode EXP8 for PROTIMER_LBTCTRL */
+#define PROTIMER_LBTCTRL_STARTEXP_DEFAULT (_PROTIMER_LBTCTRL_STARTEXP_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_LBTCTRL */
+#define PROTIMER_LBTCTRL_STARTEXP_EXP0 (_PROTIMER_LBTCTRL_STARTEXP_EXP0 << 0) /**< Shifted mode EXP0 for PROTIMER_LBTCTRL */
+#define PROTIMER_LBTCTRL_STARTEXP_EXP1 (_PROTIMER_LBTCTRL_STARTEXP_EXP1 << 0) /**< Shifted mode EXP1 for PROTIMER_LBTCTRL */
+#define PROTIMER_LBTCTRL_STARTEXP_EXP2 (_PROTIMER_LBTCTRL_STARTEXP_EXP2 << 0) /**< Shifted mode EXP2 for PROTIMER_LBTCTRL */
+#define PROTIMER_LBTCTRL_STARTEXP_EXP3 (_PROTIMER_LBTCTRL_STARTEXP_EXP3 << 0) /**< Shifted mode EXP3 for PROTIMER_LBTCTRL */
+#define PROTIMER_LBTCTRL_STARTEXP_EXP4 (_PROTIMER_LBTCTRL_STARTEXP_EXP4 << 0) /**< Shifted mode EXP4 for PROTIMER_LBTCTRL */
+#define PROTIMER_LBTCTRL_STARTEXP_EXP5 (_PROTIMER_LBTCTRL_STARTEXP_EXP5 << 0) /**< Shifted mode EXP5 for PROTIMER_LBTCTRL */
+#define PROTIMER_LBTCTRL_STARTEXP_EXP6 (_PROTIMER_LBTCTRL_STARTEXP_EXP6 << 0) /**< Shifted mode EXP6 for PROTIMER_LBTCTRL */
+#define PROTIMER_LBTCTRL_STARTEXP_EXP7 (_PROTIMER_LBTCTRL_STARTEXP_EXP7 << 0) /**< Shifted mode EXP7 for PROTIMER_LBTCTRL */
+#define PROTIMER_LBTCTRL_STARTEXP_EXP8 (_PROTIMER_LBTCTRL_STARTEXP_EXP8 << 0) /**< Shifted mode EXP8 for PROTIMER_LBTCTRL */
+#define _PROTIMER_LBTCTRL_MAXEXP_SHIFT 4 /**< Shift value for PROTIMER_MAXEXP */
+#define _PROTIMER_LBTCTRL_MAXEXP_MASK 0xF0UL /**< Bit mask for PROTIMER_MAXEXP */
+#define _PROTIMER_LBTCTRL_MAXEXP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_LBTCTRL */
+#define _PROTIMER_LBTCTRL_MAXEXP_EXP0 0x00000000UL /**< Mode EXP0 for PROTIMER_LBTCTRL */
+#define _PROTIMER_LBTCTRL_MAXEXP_EXP1 0x00000001UL /**< Mode EXP1 for PROTIMER_LBTCTRL */
+#define _PROTIMER_LBTCTRL_MAXEXP_EXP2 0x00000002UL /**< Mode EXP2 for PROTIMER_LBTCTRL */
+#define _PROTIMER_LBTCTRL_MAXEXP_EXP3 0x00000003UL /**< Mode EXP3 for PROTIMER_LBTCTRL */
+#define _PROTIMER_LBTCTRL_MAXEXP_EXP4 0x00000004UL /**< Mode EXP4 for PROTIMER_LBTCTRL */
+#define _PROTIMER_LBTCTRL_MAXEXP_EXP5 0x00000005UL /**< Mode EXP5 for PROTIMER_LBTCTRL */
+#define _PROTIMER_LBTCTRL_MAXEXP_EXP6 0x00000006UL /**< Mode EXP6 for PROTIMER_LBTCTRL */
+#define _PROTIMER_LBTCTRL_MAXEXP_EXP7 0x00000007UL /**< Mode EXP7 for PROTIMER_LBTCTRL */
+#define _PROTIMER_LBTCTRL_MAXEXP_EXP8 0x00000008UL /**< Mode EXP8 for PROTIMER_LBTCTRL */
+#define PROTIMER_LBTCTRL_MAXEXP_DEFAULT (_PROTIMER_LBTCTRL_MAXEXP_DEFAULT << 4) /**< Shifted mode DEFAULT for PROTIMER_LBTCTRL */
+#define PROTIMER_LBTCTRL_MAXEXP_EXP0 (_PROTIMER_LBTCTRL_MAXEXP_EXP0 << 4) /**< Shifted mode EXP0 for PROTIMER_LBTCTRL */
+#define PROTIMER_LBTCTRL_MAXEXP_EXP1 (_PROTIMER_LBTCTRL_MAXEXP_EXP1 << 4) /**< Shifted mode EXP1 for PROTIMER_LBTCTRL */
+#define PROTIMER_LBTCTRL_MAXEXP_EXP2 (_PROTIMER_LBTCTRL_MAXEXP_EXP2 << 4) /**< Shifted mode EXP2 for PROTIMER_LBTCTRL */
+#define PROTIMER_LBTCTRL_MAXEXP_EXP3 (_PROTIMER_LBTCTRL_MAXEXP_EXP3 << 4) /**< Shifted mode EXP3 for PROTIMER_LBTCTRL */
+#define PROTIMER_LBTCTRL_MAXEXP_EXP4 (_PROTIMER_LBTCTRL_MAXEXP_EXP4 << 4) /**< Shifted mode EXP4 for PROTIMER_LBTCTRL */
+#define PROTIMER_LBTCTRL_MAXEXP_EXP5 (_PROTIMER_LBTCTRL_MAXEXP_EXP5 << 4) /**< Shifted mode EXP5 for PROTIMER_LBTCTRL */
+#define PROTIMER_LBTCTRL_MAXEXP_EXP6 (_PROTIMER_LBTCTRL_MAXEXP_EXP6 << 4) /**< Shifted mode EXP6 for PROTIMER_LBTCTRL */
+#define PROTIMER_LBTCTRL_MAXEXP_EXP7 (_PROTIMER_LBTCTRL_MAXEXP_EXP7 << 4) /**< Shifted mode EXP7 for PROTIMER_LBTCTRL */
+#define PROTIMER_LBTCTRL_MAXEXP_EXP8 (_PROTIMER_LBTCTRL_MAXEXP_EXP8 << 4) /**< Shifted mode EXP8 for PROTIMER_LBTCTRL */
+#define _PROTIMER_LBTCTRL_CCADELAY_SHIFT 8 /**< Shift value for PROTIMER_CCADELAY */
+#define _PROTIMER_LBTCTRL_CCADELAY_MASK 0x1F00UL /**< Bit mask for PROTIMER_CCADELAY */
+#define _PROTIMER_LBTCTRL_CCADELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_LBTCTRL */
+#define PROTIMER_LBTCTRL_CCADELAY_DEFAULT (_PROTIMER_LBTCTRL_CCADELAY_DEFAULT << 8) /**< Shifted mode DEFAULT for PROTIMER_LBTCTRL */
+#define _PROTIMER_LBTCTRL_CCAREPEAT_SHIFT 16 /**< Shift value for PROTIMER_CCAREPEAT */
+#define _PROTIMER_LBTCTRL_CCAREPEAT_MASK 0xF0000UL /**< Bit mask for PROTIMER_CCAREPEAT */
+#define _PROTIMER_LBTCTRL_CCAREPEAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_LBTCTRL */
+#define PROTIMER_LBTCTRL_CCAREPEAT_DEFAULT (_PROTIMER_LBTCTRL_CCAREPEAT_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_LBTCTRL */
+#define PROTIMER_LBTCTRL_FIXEDBACKOFF (0x1UL << 20) /**< Fixed backoff */
+#define _PROTIMER_LBTCTRL_FIXEDBACKOFF_SHIFT 20 /**< Shift value for PROTIMER_FIXEDBACKOFF */
+#define _PROTIMER_LBTCTRL_FIXEDBACKOFF_MASK 0x100000UL /**< Bit mask for PROTIMER_FIXEDBACKOFF */
+#define _PROTIMER_LBTCTRL_FIXEDBACKOFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_LBTCTRL */
+#define PROTIMER_LBTCTRL_FIXEDBACKOFF_DEFAULT (_PROTIMER_LBTCTRL_FIXEDBACKOFF_DEFAULT << 20) /**< Shifted mode DEFAULT for PROTIMER_LBTCTRL */
+#define _PROTIMER_LBTCTRL_RETRYLIMIT_SHIFT 24 /**< Shift value for PROTIMER_RETRYLIMIT */
+#define _PROTIMER_LBTCTRL_RETRYLIMIT_MASK 0xF000000UL /**< Bit mask for PROTIMER_RETRYLIMIT */
+#define _PROTIMER_LBTCTRL_RETRYLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_LBTCTRL */
+#define PROTIMER_LBTCTRL_RETRYLIMIT_DEFAULT (_PROTIMER_LBTCTRL_RETRYLIMIT_DEFAULT << 24) /**< Shifted mode DEFAULT for PROTIMER_LBTCTRL */
+
+/* Bit fields for PROTIMER LBTPRSCTRL */
+#define _PROTIMER_LBTPRSCTRL_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_LBTPRSCTRL */
+#define _PROTIMER_LBTPRSCTRL_MASK 0x01010100UL /**< Mask for PROTIMER_LBTPRSCTRL */
+#define PROTIMER_LBTPRSCTRL_LBTSTARTPRSEN (0x1UL << 8) /**< Enable LBT start commands from PRS. */
+#define _PROTIMER_LBTPRSCTRL_LBTSTARTPRSEN_SHIFT 8 /**< Shift value for PROTIMER_LBTSTARTPRSEN */
+#define _PROTIMER_LBTPRSCTRL_LBTSTARTPRSEN_MASK 0x100UL /**< Bit mask for PROTIMER_LBTSTARTPRSEN */
+#define _PROTIMER_LBTPRSCTRL_LBTSTARTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_LBTPRSCTRL */
+#define PROTIMER_LBTPRSCTRL_LBTSTARTPRSEN_DEFAULT (_PROTIMER_LBTPRSCTRL_LBTSTARTPRSEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PROTIMER_LBTPRSCTRL*/
+#define PROTIMER_LBTPRSCTRL_LBTPAUSEPRSEN (0x1UL << 16) /**< Enable LBT pause commands from PRS. */
+#define _PROTIMER_LBTPRSCTRL_LBTPAUSEPRSEN_SHIFT 16 /**< Shift value for PROTIMER_LBTPAUSEPRSEN */
+#define _PROTIMER_LBTPRSCTRL_LBTPAUSEPRSEN_MASK 0x10000UL /**< Bit mask for PROTIMER_LBTPAUSEPRSEN */
+#define _PROTIMER_LBTPRSCTRL_LBTPAUSEPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_LBTPRSCTRL */
+#define PROTIMER_LBTPRSCTRL_LBTPAUSEPRSEN_DEFAULT (_PROTIMER_LBTPRSCTRL_LBTPAUSEPRSEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_LBTPRSCTRL*/
+#define PROTIMER_LBTPRSCTRL_LBTSTOPPRSEN (0x1UL << 24) /**< Enable LBT stop commands from PRS. */
+#define _PROTIMER_LBTPRSCTRL_LBTSTOPPRSEN_SHIFT 24 /**< Shift value for PROTIMER_LBTSTOPPRSEN */
+#define _PROTIMER_LBTPRSCTRL_LBTSTOPPRSEN_MASK 0x1000000UL /**< Bit mask for PROTIMER_LBTSTOPPRSEN */
+#define _PROTIMER_LBTPRSCTRL_LBTSTOPPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_LBTPRSCTRL */
+#define PROTIMER_LBTPRSCTRL_LBTSTOPPRSEN_DEFAULT (_PROTIMER_LBTPRSCTRL_LBTSTOPPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for PROTIMER_LBTPRSCTRL*/
+
+/* Bit fields for PROTIMER LBTSTATE */
+#define _PROTIMER_LBTSTATE_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_LBTSTATE */
+#define _PROTIMER_LBTSTATE_MASK 0xFFFFFFFFUL /**< Mask for PROTIMER_LBTSTATE */
+#define _PROTIMER_LBTSTATE_TOUT0PCNT_SHIFT 0 /**< Shift value for PROTIMER_TOUT0PCNT */
+#define _PROTIMER_LBTSTATE_TOUT0PCNT_MASK 0xFFFFUL /**< Bit mask for PROTIMER_TOUT0PCNT */
+#define _PROTIMER_LBTSTATE_TOUT0PCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_LBTSTATE */
+#define PROTIMER_LBTSTATE_TOUT0PCNT_DEFAULT (_PROTIMER_LBTSTATE_TOUT0PCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_LBTSTATE */
+#define _PROTIMER_LBTSTATE_TOUT0CNT_SHIFT 16 /**< Shift value for PROTIMER_TOUT0CNT */
+#define _PROTIMER_LBTSTATE_TOUT0CNT_MASK 0xFFFF0000UL /**< Bit mask for PROTIMER_TOUT0CNT */
+#define _PROTIMER_LBTSTATE_TOUT0CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_LBTSTATE */
+#define PROTIMER_LBTSTATE_TOUT0CNT_DEFAULT (_PROTIMER_LBTSTATE_TOUT0CNT_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_LBTSTATE */
+
+/* Bit fields for PROTIMER RANDOM */
+#define _PROTIMER_RANDOM_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_RANDOM */
+#define _PROTIMER_RANDOM_MASK 0x0000FFFFUL /**< Mask for PROTIMER_RANDOM */
+#define _PROTIMER_RANDOM_RANDOM_SHIFT 0 /**< Shift value for PROTIMER_RANDOM */
+#define _PROTIMER_RANDOM_RANDOM_MASK 0xFFFFUL /**< Bit mask for PROTIMER_RANDOM */
+#define _PROTIMER_RANDOM_RANDOM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_RANDOM */
+#define PROTIMER_RANDOM_RANDOM_DEFAULT (_PROTIMER_RANDOM_RANDOM_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_RANDOM */
+
+/* Bit fields for PROTIMER IF */
+#define _PROTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_IF */
+#define _PROTIMER_IF_MASK 0x3FFFFFF7UL /**< Mask for PROTIMER_IF */
+#define PROTIMER_IF_PRECNTOF (0x1UL << 0) /**< PRECNT Overflow Interrupt Flag */
+#define _PROTIMER_IF_PRECNTOF_SHIFT 0 /**< Shift value for PROTIMER_PRECNTOF */
+#define _PROTIMER_IF_PRECNTOF_MASK 0x1UL /**< Bit mask for PROTIMER_PRECNTOF */
+#define _PROTIMER_IF_PRECNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_PRECNTOF_DEFAULT (_PROTIMER_IF_PRECNTOF_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_BASECNTOF (0x1UL << 1) /**< BASECNT Overflow Interrupt Flag */
+#define _PROTIMER_IF_BASECNTOF_SHIFT 1 /**< Shift value for PROTIMER_BASECNTOF */
+#define _PROTIMER_IF_BASECNTOF_MASK 0x2UL /**< Bit mask for PROTIMER_BASECNTOF */
+#define _PROTIMER_IF_BASECNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_BASECNTOF_DEFAULT (_PROTIMER_IF_BASECNTOF_DEFAULT << 1) /**< Shifted mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_WRAPCNTOF (0x1UL << 2) /**< WRAPCNT Overflow Interrupt Flag */
+#define _PROTIMER_IF_WRAPCNTOF_SHIFT 2 /**< Shift value for PROTIMER_WRAPCNTOF */
+#define _PROTIMER_IF_WRAPCNTOF_MASK 0x4UL /**< Bit mask for PROTIMER_WRAPCNTOF */
+#define _PROTIMER_IF_WRAPCNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_WRAPCNTOF_DEFAULT (_PROTIMER_IF_WRAPCNTOF_DEFAULT << 2) /**< Shifted mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_TOUT0 (0x1UL << 4) /**< TOUT0 underflow interrupt flag */
+#define _PROTIMER_IF_TOUT0_SHIFT 4 /**< Shift value for PROTIMER_TOUT0 */
+#define _PROTIMER_IF_TOUT0_MASK 0x10UL /**< Bit mask for PROTIMER_TOUT0 */
+#define _PROTIMER_IF_TOUT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_TOUT0_DEFAULT (_PROTIMER_IF_TOUT0_DEFAULT << 4) /**< Shifted mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_TOUT1 (0x1UL << 5) /**< TOUT1 underflow interrupt flag */
+#define _PROTIMER_IF_TOUT1_SHIFT 5 /**< Shift value for PROTIMER_TOUT1 */
+#define _PROTIMER_IF_TOUT1_MASK 0x20UL /**< Bit mask for PROTIMER_TOUT1 */
+#define _PROTIMER_IF_TOUT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_TOUT1_DEFAULT (_PROTIMER_IF_TOUT1_DEFAULT << 5) /**< Shifted mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_TOUT0MATCH (0x1UL << 6) /**< TOUT0 compare match interrupt flag */
+#define _PROTIMER_IF_TOUT0MATCH_SHIFT 6 /**< Shift value for PROTIMER_TOUT0MATCH */
+#define _PROTIMER_IF_TOUT0MATCH_MASK 0x40UL /**< Bit mask for PROTIMER_TOUT0MATCH */
+#define _PROTIMER_IF_TOUT0MATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_TOUT0MATCH_DEFAULT (_PROTIMER_IF_TOUT0MATCH_DEFAULT << 6) /**< Shifted mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_TOUT1MATCH (0x1UL << 7) /**< TOUT1 compare match interrupt flag */
+#define _PROTIMER_IF_TOUT1MATCH_SHIFT 7 /**< Shift value for PROTIMER_TOUT1MATCH */
+#define _PROTIMER_IF_TOUT1MATCH_MASK 0x80UL /**< Bit mask for PROTIMER_TOUT1MATCH */
+#define _PROTIMER_IF_TOUT1MATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_TOUT1MATCH_DEFAULT (_PROTIMER_IF_TOUT1MATCH_DEFAULT << 7) /**< Shifted mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_CC0 (0x1UL << 8) /**< CC Channel 0 Interrupt Flag */
+#define _PROTIMER_IF_CC0_SHIFT 8 /**< Shift value for PROTIMER_CC0 */
+#define _PROTIMER_IF_CC0_MASK 0x100UL /**< Bit mask for PROTIMER_CC0 */
+#define _PROTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_CC0_DEFAULT (_PROTIMER_IF_CC0_DEFAULT << 8) /**< Shifted mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_CC1 (0x1UL << 9) /**< CC Channel 1 Interrupt Flag */
+#define _PROTIMER_IF_CC1_SHIFT 9 /**< Shift value for PROTIMER_CC1 */
+#define _PROTIMER_IF_CC1_MASK 0x200UL /**< Bit mask for PROTIMER_CC1 */
+#define _PROTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_CC1_DEFAULT (_PROTIMER_IF_CC1_DEFAULT << 9) /**< Shifted mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_CC2 (0x1UL << 10) /**< CC Channel 2 Interrupt Flag */
+#define _PROTIMER_IF_CC2_SHIFT 10 /**< Shift value for PROTIMER_CC2 */
+#define _PROTIMER_IF_CC2_MASK 0x400UL /**< Bit mask for PROTIMER_CC2 */
+#define _PROTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_CC2_DEFAULT (_PROTIMER_IF_CC2_DEFAULT << 10) /**< Shifted mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_CC3 (0x1UL << 11) /**< CC Channel 3 Interrupt Flag */
+#define _PROTIMER_IF_CC3_SHIFT 11 /**< Shift value for PROTIMER_CC3 */
+#define _PROTIMER_IF_CC3_MASK 0x800UL /**< Bit mask for PROTIMER_CC3 */
+#define _PROTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_CC3_DEFAULT (_PROTIMER_IF_CC3_DEFAULT << 11) /**< Shifted mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_CC4 (0x1UL << 12) /**< CC Channel 4 Interrupt Flag */
+#define _PROTIMER_IF_CC4_SHIFT 12 /**< Shift value for PROTIMER_CC4 */
+#define _PROTIMER_IF_CC4_MASK 0x1000UL /**< Bit mask for PROTIMER_CC4 */
+#define _PROTIMER_IF_CC4_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_CC4_DEFAULT (_PROTIMER_IF_CC4_DEFAULT << 12) /**< Shifted mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_CC5 (0x1UL << 13) /**< CC Channel 5 Interrupt Flag */
+#define _PROTIMER_IF_CC5_SHIFT 13 /**< Shift value for PROTIMER_CC5 */
+#define _PROTIMER_IF_CC5_MASK 0x2000UL /**< Bit mask for PROTIMER_CC5 */
+#define _PROTIMER_IF_CC5_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_CC5_DEFAULT (_PROTIMER_IF_CC5_DEFAULT << 13) /**< Shifted mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_CC6 (0x1UL << 14) /**< CC Channel 6 Interrupt Flag */
+#define _PROTIMER_IF_CC6_SHIFT 14 /**< Shift value for PROTIMER_CC6 */
+#define _PROTIMER_IF_CC6_MASK 0x4000UL /**< Bit mask for PROTIMER_CC6 */
+#define _PROTIMER_IF_CC6_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_CC6_DEFAULT (_PROTIMER_IF_CC6_DEFAULT << 14) /**< Shifted mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_CC7 (0x1UL << 15) /**< CC Channel 7 Interrupt Flag */
+#define _PROTIMER_IF_CC7_SHIFT 15 /**< Shift value for PROTIMER_CC7 */
+#define _PROTIMER_IF_CC7_MASK 0x8000UL /**< Bit mask for PROTIMER_CC7 */
+#define _PROTIMER_IF_CC7_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_CC7_DEFAULT (_PROTIMER_IF_CC7_DEFAULT << 15) /**< Shifted mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_COF0 (0x1UL << 16) /**< CC Channel 0 Overflow Interrupt Flag */
+#define _PROTIMER_IF_COF0_SHIFT 16 /**< Shift value for PROTIMER_COF0 */
+#define _PROTIMER_IF_COF0_MASK 0x10000UL /**< Bit mask for PROTIMER_COF0 */
+#define _PROTIMER_IF_COF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_COF0_DEFAULT (_PROTIMER_IF_COF0_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_COF1 (0x1UL << 17) /**< CC Channel 1 Overflow Interrupt Flag */
+#define _PROTIMER_IF_COF1_SHIFT 17 /**< Shift value for PROTIMER_COF1 */
+#define _PROTIMER_IF_COF1_MASK 0x20000UL /**< Bit mask for PROTIMER_COF1 */
+#define _PROTIMER_IF_COF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_COF1_DEFAULT (_PROTIMER_IF_COF1_DEFAULT << 17) /**< Shifted mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_COF2 (0x1UL << 18) /**< CC Channel 2 Overflow Interrupt Flag */
+#define _PROTIMER_IF_COF2_SHIFT 18 /**< Shift value for PROTIMER_COF2 */
+#define _PROTIMER_IF_COF2_MASK 0x40000UL /**< Bit mask for PROTIMER_COF2 */
+#define _PROTIMER_IF_COF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_COF2_DEFAULT (_PROTIMER_IF_COF2_DEFAULT << 18) /**< Shifted mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_COF3 (0x1UL << 19) /**< CC Channel 3 Overflow Interrupt Flag */
+#define _PROTIMER_IF_COF3_SHIFT 19 /**< Shift value for PROTIMER_COF3 */
+#define _PROTIMER_IF_COF3_MASK 0x80000UL /**< Bit mask for PROTIMER_COF3 */
+#define _PROTIMER_IF_COF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_COF3_DEFAULT (_PROTIMER_IF_COF3_DEFAULT << 19) /**< Shifted mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_COF4 (0x1UL << 20) /**< CC Channel 4 Overflow Interrupt Flag */
+#define _PROTIMER_IF_COF4_SHIFT 20 /**< Shift value for PROTIMER_COF4 */
+#define _PROTIMER_IF_COF4_MASK 0x100000UL /**< Bit mask for PROTIMER_COF4 */
+#define _PROTIMER_IF_COF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_COF4_DEFAULT (_PROTIMER_IF_COF4_DEFAULT << 20) /**< Shifted mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_COF5 (0x1UL << 21) /**< CC Channel 5 Overflow Interrupt Flag */
+#define _PROTIMER_IF_COF5_SHIFT 21 /**< Shift value for PROTIMER_COF5 */
+#define _PROTIMER_IF_COF5_MASK 0x200000UL /**< Bit mask for PROTIMER_COF5 */
+#define _PROTIMER_IF_COF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_COF5_DEFAULT (_PROTIMER_IF_COF5_DEFAULT << 21) /**< Shifted mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_COF6 (0x1UL << 22) /**< CC Channel 6 Overflow Interrupt Flag */
+#define _PROTIMER_IF_COF6_SHIFT 22 /**< Shift value for PROTIMER_COF6 */
+#define _PROTIMER_IF_COF6_MASK 0x400000UL /**< Bit mask for PROTIMER_COF6 */
+#define _PROTIMER_IF_COF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_COF6_DEFAULT (_PROTIMER_IF_COF6_DEFAULT << 22) /**< Shifted mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_COF7 (0x1UL << 23) /**< CC Channel 7 Overflow Interrupt Flag */
+#define _PROTIMER_IF_COF7_SHIFT 23 /**< Shift value for PROTIMER_COF7 */
+#define _PROTIMER_IF_COF7_MASK 0x800000UL /**< Bit mask for PROTIMER_COF7 */
+#define _PROTIMER_IF_COF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_COF7_DEFAULT (_PROTIMER_IF_COF7_DEFAULT << 23) /**< Shifted mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_LBTSUCCESS (0x1UL << 24) /**< Listen Before Talk Success */
+#define _PROTIMER_IF_LBTSUCCESS_SHIFT 24 /**< Shift value for PROTIMER_LBTSUCCESS */
+#define _PROTIMER_IF_LBTSUCCESS_MASK 0x1000000UL /**< Bit mask for PROTIMER_LBTSUCCESS */
+#define _PROTIMER_IF_LBTSUCCESS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_LBTSUCCESS_DEFAULT (_PROTIMER_IF_LBTSUCCESS_DEFAULT << 24) /**< Shifted mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_LBTFAILURE (0x1UL << 25) /**< Listen Before Talk Failure */
+#define _PROTIMER_IF_LBTFAILURE_SHIFT 25 /**< Shift value for PROTIMER_LBTFAILURE */
+#define _PROTIMER_IF_LBTFAILURE_MASK 0x2000000UL /**< Bit mask for PROTIMER_LBTFAILURE */
+#define _PROTIMER_IF_LBTFAILURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_LBTFAILURE_DEFAULT (_PROTIMER_IF_LBTFAILURE_DEFAULT << 25) /**< Shifted mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_LBTPAUSED (0x1UL << 26) /**< Listen Before Talk Paused */
+#define _PROTIMER_IF_LBTPAUSED_SHIFT 26 /**< Shift value for PROTIMER_LBTPAUSED */
+#define _PROTIMER_IF_LBTPAUSED_MASK 0x4000000UL /**< Bit mask for PROTIMER_LBTPAUSED */
+#define _PROTIMER_IF_LBTPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_LBTPAUSED_DEFAULT (_PROTIMER_IF_LBTPAUSED_DEFAULT << 26) /**< Shifted mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_LBTRETRY (0x1UL << 27) /**< Listen Before Talk Retry */
+#define _PROTIMER_IF_LBTRETRY_SHIFT 27 /**< Shift value for PROTIMER_LBTRETRY */
+#define _PROTIMER_IF_LBTRETRY_MASK 0x8000000UL /**< Bit mask for PROTIMER_LBTRETRY */
+#define _PROTIMER_IF_LBTRETRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_LBTRETRY_DEFAULT (_PROTIMER_IF_LBTRETRY_DEFAULT << 27) /**< Shifted mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_RTCCSYNCHED (0x1UL << 28) /**< PROTIMER synchronized with the RTCC */
+#define _PROTIMER_IF_RTCCSYNCHED_SHIFT 28 /**< Shift value for PROTIMER_RTCCSYNCHED */
+#define _PROTIMER_IF_RTCCSYNCHED_MASK 0x10000000UL /**< Bit mask for PROTIMER_RTCCSYNCHED */
+#define _PROTIMER_IF_RTCCSYNCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_RTCCSYNCHED_DEFAULT (_PROTIMER_IF_RTCCSYNCHED_DEFAULT << 28) /**< Shifted mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_TOUT0MATCHLBT (0x1UL << 29) /**< TOUT0 compare match interrupt flag */
+#define _PROTIMER_IF_TOUT0MATCHLBT_SHIFT 29 /**< Shift value for PROTIMER_TOUT0MATCHLBT */
+#define _PROTIMER_IF_TOUT0MATCHLBT_MASK 0x20000000UL /**< Bit mask for PROTIMER_TOUT0MATCHLBT */
+#define _PROTIMER_IF_TOUT0MATCHLBT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IF */
+#define PROTIMER_IF_TOUT0MATCHLBT_DEFAULT (_PROTIMER_IF_TOUT0MATCHLBT_DEFAULT << 29) /**< Shifted mode DEFAULT for PROTIMER_IF */
+
+/* Bit fields for PROTIMER IEN */
+#define _PROTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_IEN */
+#define _PROTIMER_IEN_MASK 0x3FFFFFF7UL /**< Mask for PROTIMER_IEN */
+#define PROTIMER_IEN_PRECNTOF (0x1UL << 0) /**< PRECNTOF Interrupt Enable */
+#define _PROTIMER_IEN_PRECNTOF_SHIFT 0 /**< Shift value for PROTIMER_PRECNTOF */
+#define _PROTIMER_IEN_PRECNTOF_MASK 0x1UL /**< Bit mask for PROTIMER_PRECNTOF */
+#define _PROTIMER_IEN_PRECNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_PRECNTOF_DEFAULT (_PROTIMER_IEN_PRECNTOF_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_BASECNTOF (0x1UL << 1) /**< BASECNTOF Interrupt Enable */
+#define _PROTIMER_IEN_BASECNTOF_SHIFT 1 /**< Shift value for PROTIMER_BASECNTOF */
+#define _PROTIMER_IEN_BASECNTOF_MASK 0x2UL /**< Bit mask for PROTIMER_BASECNTOF */
+#define _PROTIMER_IEN_BASECNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_BASECNTOF_DEFAULT (_PROTIMER_IEN_BASECNTOF_DEFAULT << 1) /**< Shifted mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_WRAPCNTOF (0x1UL << 2) /**< WRAPCNTOF Interrupt Enable */
+#define _PROTIMER_IEN_WRAPCNTOF_SHIFT 2 /**< Shift value for PROTIMER_WRAPCNTOF */
+#define _PROTIMER_IEN_WRAPCNTOF_MASK 0x4UL /**< Bit mask for PROTIMER_WRAPCNTOF */
+#define _PROTIMER_IEN_WRAPCNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_WRAPCNTOF_DEFAULT (_PROTIMER_IEN_WRAPCNTOF_DEFAULT << 2) /**< Shifted mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_TOUT0 (0x1UL << 4) /**< TOUT0 Interrupt Enable */
+#define _PROTIMER_IEN_TOUT0_SHIFT 4 /**< Shift value for PROTIMER_TOUT0 */
+#define _PROTIMER_IEN_TOUT0_MASK 0x10UL /**< Bit mask for PROTIMER_TOUT0 */
+#define _PROTIMER_IEN_TOUT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_TOUT0_DEFAULT (_PROTIMER_IEN_TOUT0_DEFAULT << 4) /**< Shifted mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_TOUT1 (0x1UL << 5) /**< TOUT1 Interrupt Enable */
+#define _PROTIMER_IEN_TOUT1_SHIFT 5 /**< Shift value for PROTIMER_TOUT1 */
+#define _PROTIMER_IEN_TOUT1_MASK 0x20UL /**< Bit mask for PROTIMER_TOUT1 */
+#define _PROTIMER_IEN_TOUT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_TOUT1_DEFAULT (_PROTIMER_IEN_TOUT1_DEFAULT << 5) /**< Shifted mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_TOUT0MATCH (0x1UL << 6) /**< TOUT0MATCH Interrupt Enable */
+#define _PROTIMER_IEN_TOUT0MATCH_SHIFT 6 /**< Shift value for PROTIMER_TOUT0MATCH */
+#define _PROTIMER_IEN_TOUT0MATCH_MASK 0x40UL /**< Bit mask for PROTIMER_TOUT0MATCH */
+#define _PROTIMER_IEN_TOUT0MATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_TOUT0MATCH_DEFAULT (_PROTIMER_IEN_TOUT0MATCH_DEFAULT << 6) /**< Shifted mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_TOUT1MATCH (0x1UL << 7) /**< TOUT1MATCH Interrupt Enable */
+#define _PROTIMER_IEN_TOUT1MATCH_SHIFT 7 /**< Shift value for PROTIMER_TOUT1MATCH */
+#define _PROTIMER_IEN_TOUT1MATCH_MASK 0x80UL /**< Bit mask for PROTIMER_TOUT1MATCH */
+#define _PROTIMER_IEN_TOUT1MATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_TOUT1MATCH_DEFAULT (_PROTIMER_IEN_TOUT1MATCH_DEFAULT << 7) /**< Shifted mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_CC0 (0x1UL << 8) /**< CC0 Interrupt Enable */
+#define _PROTIMER_IEN_CC0_SHIFT 8 /**< Shift value for PROTIMER_CC0 */
+#define _PROTIMER_IEN_CC0_MASK 0x100UL /**< Bit mask for PROTIMER_CC0 */
+#define _PROTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_CC0_DEFAULT (_PROTIMER_IEN_CC0_DEFAULT << 8) /**< Shifted mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_CC1 (0x1UL << 9) /**< CC1 Interrupt Enable */
+#define _PROTIMER_IEN_CC1_SHIFT 9 /**< Shift value for PROTIMER_CC1 */
+#define _PROTIMER_IEN_CC1_MASK 0x200UL /**< Bit mask for PROTIMER_CC1 */
+#define _PROTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_CC1_DEFAULT (_PROTIMER_IEN_CC1_DEFAULT << 9) /**< Shifted mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_CC2 (0x1UL << 10) /**< CC2 Interrupt Enable */
+#define _PROTIMER_IEN_CC2_SHIFT 10 /**< Shift value for PROTIMER_CC2 */
+#define _PROTIMER_IEN_CC2_MASK 0x400UL /**< Bit mask for PROTIMER_CC2 */
+#define _PROTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_CC2_DEFAULT (_PROTIMER_IEN_CC2_DEFAULT << 10) /**< Shifted mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_CC3 (0x1UL << 11) /**< CC3 Interrupt Enable */
+#define _PROTIMER_IEN_CC3_SHIFT 11 /**< Shift value for PROTIMER_CC3 */
+#define _PROTIMER_IEN_CC3_MASK 0x800UL /**< Bit mask for PROTIMER_CC3 */
+#define _PROTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_CC3_DEFAULT (_PROTIMER_IEN_CC3_DEFAULT << 11) /**< Shifted mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_CC4 (0x1UL << 12) /**< CC4 Interrupt Enable */
+#define _PROTIMER_IEN_CC4_SHIFT 12 /**< Shift value for PROTIMER_CC4 */
+#define _PROTIMER_IEN_CC4_MASK 0x1000UL /**< Bit mask for PROTIMER_CC4 */
+#define _PROTIMER_IEN_CC4_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_CC4_DEFAULT (_PROTIMER_IEN_CC4_DEFAULT << 12) /**< Shifted mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_CC5 (0x1UL << 13) /**< CC5 Interrupt Enable */
+#define _PROTIMER_IEN_CC5_SHIFT 13 /**< Shift value for PROTIMER_CC5 */
+#define _PROTIMER_IEN_CC5_MASK 0x2000UL /**< Bit mask for PROTIMER_CC5 */
+#define _PROTIMER_IEN_CC5_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_CC5_DEFAULT (_PROTIMER_IEN_CC5_DEFAULT << 13) /**< Shifted mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_CC6 (0x1UL << 14) /**< CC6 Interrupt Enable */
+#define _PROTIMER_IEN_CC6_SHIFT 14 /**< Shift value for PROTIMER_CC6 */
+#define _PROTIMER_IEN_CC6_MASK 0x4000UL /**< Bit mask for PROTIMER_CC6 */
+#define _PROTIMER_IEN_CC6_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_CC6_DEFAULT (_PROTIMER_IEN_CC6_DEFAULT << 14) /**< Shifted mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_CC7 (0x1UL << 15) /**< CC7 Interrupt Enable */
+#define _PROTIMER_IEN_CC7_SHIFT 15 /**< Shift value for PROTIMER_CC7 */
+#define _PROTIMER_IEN_CC7_MASK 0x8000UL /**< Bit mask for PROTIMER_CC7 */
+#define _PROTIMER_IEN_CC7_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_CC7_DEFAULT (_PROTIMER_IEN_CC7_DEFAULT << 15) /**< Shifted mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_COF0 (0x1UL << 16) /**< COF0 Interrupt Enable */
+#define _PROTIMER_IEN_COF0_SHIFT 16 /**< Shift value for PROTIMER_COF0 */
+#define _PROTIMER_IEN_COF0_MASK 0x10000UL /**< Bit mask for PROTIMER_COF0 */
+#define _PROTIMER_IEN_COF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_COF0_DEFAULT (_PROTIMER_IEN_COF0_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_COF1 (0x1UL << 17) /**< COF1 Interrupt Enable */
+#define _PROTIMER_IEN_COF1_SHIFT 17 /**< Shift value for PROTIMER_COF1 */
+#define _PROTIMER_IEN_COF1_MASK 0x20000UL /**< Bit mask for PROTIMER_COF1 */
+#define _PROTIMER_IEN_COF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_COF1_DEFAULT (_PROTIMER_IEN_COF1_DEFAULT << 17) /**< Shifted mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_COF2 (0x1UL << 18) /**< COF2 Interrupt Enable */
+#define _PROTIMER_IEN_COF2_SHIFT 18 /**< Shift value for PROTIMER_COF2 */
+#define _PROTIMER_IEN_COF2_MASK 0x40000UL /**< Bit mask for PROTIMER_COF2 */
+#define _PROTIMER_IEN_COF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_COF2_DEFAULT (_PROTIMER_IEN_COF2_DEFAULT << 18) /**< Shifted mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_COF3 (0x1UL << 19) /**< COF3 Interrupt Enable */
+#define _PROTIMER_IEN_COF3_SHIFT 19 /**< Shift value for PROTIMER_COF3 */
+#define _PROTIMER_IEN_COF3_MASK 0x80000UL /**< Bit mask for PROTIMER_COF3 */
+#define _PROTIMER_IEN_COF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_COF3_DEFAULT (_PROTIMER_IEN_COF3_DEFAULT << 19) /**< Shifted mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_COF4 (0x1UL << 20) /**< COF4 Interrupt Enable */
+#define _PROTIMER_IEN_COF4_SHIFT 20 /**< Shift value for PROTIMER_COF4 */
+#define _PROTIMER_IEN_COF4_MASK 0x100000UL /**< Bit mask for PROTIMER_COF4 */
+#define _PROTIMER_IEN_COF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_COF4_DEFAULT (_PROTIMER_IEN_COF4_DEFAULT << 20) /**< Shifted mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_COF5 (0x1UL << 21) /**< COF5 Interrupt Enable */
+#define _PROTIMER_IEN_COF5_SHIFT 21 /**< Shift value for PROTIMER_COF5 */
+#define _PROTIMER_IEN_COF5_MASK 0x200000UL /**< Bit mask for PROTIMER_COF5 */
+#define _PROTIMER_IEN_COF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_COF5_DEFAULT (_PROTIMER_IEN_COF5_DEFAULT << 21) /**< Shifted mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_COF6 (0x1UL << 22) /**< COF6 Interrupt Enable */
+#define _PROTIMER_IEN_COF6_SHIFT 22 /**< Shift value for PROTIMER_COF6 */
+#define _PROTIMER_IEN_COF6_MASK 0x400000UL /**< Bit mask for PROTIMER_COF6 */
+#define _PROTIMER_IEN_COF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_COF6_DEFAULT (_PROTIMER_IEN_COF6_DEFAULT << 22) /**< Shifted mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_COF7 (0x1UL << 23) /**< COF7 Interrupt Enable */
+#define _PROTIMER_IEN_COF7_SHIFT 23 /**< Shift value for PROTIMER_COF7 */
+#define _PROTIMER_IEN_COF7_MASK 0x800000UL /**< Bit mask for PROTIMER_COF7 */
+#define _PROTIMER_IEN_COF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_COF7_DEFAULT (_PROTIMER_IEN_COF7_DEFAULT << 23) /**< Shifted mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_LBTSUCCESS (0x1UL << 24) /**< LBTSUCCESS Interrupt Enable */
+#define _PROTIMER_IEN_LBTSUCCESS_SHIFT 24 /**< Shift value for PROTIMER_LBTSUCCESS */
+#define _PROTIMER_IEN_LBTSUCCESS_MASK 0x1000000UL /**< Bit mask for PROTIMER_LBTSUCCESS */
+#define _PROTIMER_IEN_LBTSUCCESS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_LBTSUCCESS_DEFAULT (_PROTIMER_IEN_LBTSUCCESS_DEFAULT << 24) /**< Shifted mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_LBTFAILURE (0x1UL << 25) /**< LBTFAILURE Interrupt Enable */
+#define _PROTIMER_IEN_LBTFAILURE_SHIFT 25 /**< Shift value for PROTIMER_LBTFAILURE */
+#define _PROTIMER_IEN_LBTFAILURE_MASK 0x2000000UL /**< Bit mask for PROTIMER_LBTFAILURE */
+#define _PROTIMER_IEN_LBTFAILURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_LBTFAILURE_DEFAULT (_PROTIMER_IEN_LBTFAILURE_DEFAULT << 25) /**< Shifted mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_LBTPAUSED (0x1UL << 26) /**< LBTPAUSED Interrupt Enable */
+#define _PROTIMER_IEN_LBTPAUSED_SHIFT 26 /**< Shift value for PROTIMER_LBTPAUSED */
+#define _PROTIMER_IEN_LBTPAUSED_MASK 0x4000000UL /**< Bit mask for PROTIMER_LBTPAUSED */
+#define _PROTIMER_IEN_LBTPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_LBTPAUSED_DEFAULT (_PROTIMER_IEN_LBTPAUSED_DEFAULT << 26) /**< Shifted mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_LBTRETRY (0x1UL << 27) /**< LBTRETRY Interrupt Enable */
+#define _PROTIMER_IEN_LBTRETRY_SHIFT 27 /**< Shift value for PROTIMER_LBTRETRY */
+#define _PROTIMER_IEN_LBTRETRY_MASK 0x8000000UL /**< Bit mask for PROTIMER_LBTRETRY */
+#define _PROTIMER_IEN_LBTRETRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_LBTRETRY_DEFAULT (_PROTIMER_IEN_LBTRETRY_DEFAULT << 27) /**< Shifted mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_RTCCSYNCHED (0x1UL << 28) /**< RTCCSYNCHED Interrupt Enable */
+#define _PROTIMER_IEN_RTCCSYNCHED_SHIFT 28 /**< Shift value for PROTIMER_RTCCSYNCHED */
+#define _PROTIMER_IEN_RTCCSYNCHED_MASK 0x10000000UL /**< Bit mask for PROTIMER_RTCCSYNCHED */
+#define _PROTIMER_IEN_RTCCSYNCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_RTCCSYNCHED_DEFAULT (_PROTIMER_IEN_RTCCSYNCHED_DEFAULT << 28) /**< Shifted mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_TOUT0MATCHLBT (0x1UL << 29) /**< TOUT0MATCHLBT Interrupt Enable */
+#define _PROTIMER_IEN_TOUT0MATCHLBT_SHIFT 29 /**< Shift value for PROTIMER_TOUT0MATCHLBT */
+#define _PROTIMER_IEN_TOUT0MATCHLBT_MASK 0x20000000UL /**< Bit mask for PROTIMER_TOUT0MATCHLBT */
+#define _PROTIMER_IEN_TOUT0MATCHLBT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_IEN */
+#define PROTIMER_IEN_TOUT0MATCHLBT_DEFAULT (_PROTIMER_IEN_TOUT0MATCHLBT_DEFAULT << 29) /**< Shifted mode DEFAULT for PROTIMER_IEN */
+
+/* Bit fields for PROTIMER RXCTRL */
+#define _PROTIMER_RXCTRL_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_MASK 0x1F1F1F1FUL /**< Mask for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_RXSETEVENT1_SHIFT 0 /**< Shift value for PROTIMER_RXSETEVENT1 */
+#define _PROTIMER_RXCTRL_RXSETEVENT1_MASK 0x1FUL /**< Bit mask for PROTIMER_RXSETEVENT1 */
+#define _PROTIMER_RXCTRL_RXSETEVENT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_RXSETEVENT1_DISABLED 0x00000000UL /**< Mode DISABLED for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_RXSETEVENT1_ALWAYS 0x00000001UL /**< Mode ALWAYS for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_RXSETEVENT1_PRECNTOF 0x00000002UL /**< Mode PRECNTOF for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_RXSETEVENT1_BASECNTOF 0x00000003UL /**< Mode BASECNTOF for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_RXSETEVENT1_WRAPCNTOF 0x00000004UL /**< Mode WRAPCNTOF for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_RXSETEVENT1_TOUT0UF 0x00000005UL /**< Mode TOUT0UF for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_RXSETEVENT1_TOUT1UF 0x00000006UL /**< Mode TOUT1UF for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_RXSETEVENT1_TOUT0MATCH 0x00000007UL /**< Mode TOUT0MATCH for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_RXSETEVENT1_TOUT1MATCH 0x00000008UL /**< Mode TOUT1MATCH for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_RXSETEVENT1_CC0 0x00000009UL /**< Mode CC0 for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_RXSETEVENT1_CC1 0x0000000AUL /**< Mode CC1 for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_RXSETEVENT1_CC2 0x0000000BUL /**< Mode CC2 for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_RXSETEVENT1_CC3 0x0000000CUL /**< Mode CC3 for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_RXSETEVENT1_CC4 0x0000000DUL /**< Mode CC4 for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_RXSETEVENT1_TXDONE 0x0000000EUL /**< Mode TXDONE for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_RXSETEVENT1_RXDONE 0x0000000FUL /**< Mode RXDONE for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_RXSETEVENT1_TXORRXDONE 0x00000010UL /**< Mode TXORRXDONE for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_RXSETEVENT1_FDET0 0x00000011UL /**< Mode FDET0 for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_RXSETEVENT1_FDET1 0x00000012UL /**< Mode FDET1 for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_RXSETEVENT1_FDET0OR1 0x00000013UL /**< Mode FDET0OR1 for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_RXSETEVENT1_LBTSUCCESS 0x00000014UL /**< Mode LBTSUCCESS for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_RXSETEVENT1_LBTRETRY 0x00000015UL /**< Mode LBTRETRY for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_RXSETEVENT1_LBTFAILURE 0x00000016UL /**< Mode LBTFAILURE for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_RXSETEVENT1_ANYLBT 0x00000017UL /**< Mode ANYLBT for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_RXSETEVENT1_CCAACK 0x00000018UL /**< Mode CCAACK for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_RXSETEVENT1_CCA 0x00000019UL /**< Mode CCA for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_RXSETEVENT1_NOTCCA 0x0000001AUL /**< Mode NOTCCA for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_RXSETEVENT1_TOUT0MATCHLBT 0x0000001BUL /**< Mode TOUT0MATCHLBT for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXSETEVENT1_DEFAULT (_PROTIMER_RXCTRL_RXSETEVENT1_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXSETEVENT1_DISABLED (_PROTIMER_RXCTRL_RXSETEVENT1_DISABLED << 0) /**< Shifted mode DISABLED for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXSETEVENT1_ALWAYS (_PROTIMER_RXCTRL_RXSETEVENT1_ALWAYS << 0) /**< Shifted mode ALWAYS for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXSETEVENT1_PRECNTOF (_PROTIMER_RXCTRL_RXSETEVENT1_PRECNTOF << 0) /**< Shifted mode PRECNTOF for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXSETEVENT1_BASECNTOF (_PROTIMER_RXCTRL_RXSETEVENT1_BASECNTOF << 0) /**< Shifted mode BASECNTOF for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXSETEVENT1_WRAPCNTOF (_PROTIMER_RXCTRL_RXSETEVENT1_WRAPCNTOF << 0) /**< Shifted mode WRAPCNTOF for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXSETEVENT1_TOUT0UF (_PROTIMER_RXCTRL_RXSETEVENT1_TOUT0UF << 0) /**< Shifted mode TOUT0UF for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXSETEVENT1_TOUT1UF (_PROTIMER_RXCTRL_RXSETEVENT1_TOUT1UF << 0) /**< Shifted mode TOUT1UF for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXSETEVENT1_TOUT0MATCH (_PROTIMER_RXCTRL_RXSETEVENT1_TOUT0MATCH << 0) /**< Shifted mode TOUT0MATCH for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXSETEVENT1_TOUT1MATCH (_PROTIMER_RXCTRL_RXSETEVENT1_TOUT1MATCH << 0) /**< Shifted mode TOUT1MATCH for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXSETEVENT1_CC0 (_PROTIMER_RXCTRL_RXSETEVENT1_CC0 << 0) /**< Shifted mode CC0 for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXSETEVENT1_CC1 (_PROTIMER_RXCTRL_RXSETEVENT1_CC1 << 0) /**< Shifted mode CC1 for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXSETEVENT1_CC2 (_PROTIMER_RXCTRL_RXSETEVENT1_CC2 << 0) /**< Shifted mode CC2 for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXSETEVENT1_CC3 (_PROTIMER_RXCTRL_RXSETEVENT1_CC3 << 0) /**< Shifted mode CC3 for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXSETEVENT1_CC4 (_PROTIMER_RXCTRL_RXSETEVENT1_CC4 << 0) /**< Shifted mode CC4 for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXSETEVENT1_TXDONE (_PROTIMER_RXCTRL_RXSETEVENT1_TXDONE << 0) /**< Shifted mode TXDONE for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXSETEVENT1_RXDONE (_PROTIMER_RXCTRL_RXSETEVENT1_RXDONE << 0) /**< Shifted mode RXDONE for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXSETEVENT1_TXORRXDONE (_PROTIMER_RXCTRL_RXSETEVENT1_TXORRXDONE << 0) /**< Shifted mode TXORRXDONE for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXSETEVENT1_FDET0 (_PROTIMER_RXCTRL_RXSETEVENT1_FDET0 << 0) /**< Shifted mode FDET0 for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXSETEVENT1_FDET1 (_PROTIMER_RXCTRL_RXSETEVENT1_FDET1 << 0) /**< Shifted mode FDET1 for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXSETEVENT1_FDET0OR1 (_PROTIMER_RXCTRL_RXSETEVENT1_FDET0OR1 << 0) /**< Shifted mode FDET0OR1 for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXSETEVENT1_LBTSUCCESS (_PROTIMER_RXCTRL_RXSETEVENT1_LBTSUCCESS << 0) /**< Shifted mode LBTSUCCESS for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXSETEVENT1_LBTRETRY (_PROTIMER_RXCTRL_RXSETEVENT1_LBTRETRY << 0) /**< Shifted mode LBTRETRY for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXSETEVENT1_LBTFAILURE (_PROTIMER_RXCTRL_RXSETEVENT1_LBTFAILURE << 0) /**< Shifted mode LBTFAILURE for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXSETEVENT1_ANYLBT (_PROTIMER_RXCTRL_RXSETEVENT1_ANYLBT << 0) /**< Shifted mode ANYLBT for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXSETEVENT1_CCAACK (_PROTIMER_RXCTRL_RXSETEVENT1_CCAACK << 0) /**< Shifted mode CCAACK for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXSETEVENT1_CCA (_PROTIMER_RXCTRL_RXSETEVENT1_CCA << 0) /**< Shifted mode CCA for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXSETEVENT1_NOTCCA (_PROTIMER_RXCTRL_RXSETEVENT1_NOTCCA << 0) /**< Shifted mode NOTCCA for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXSETEVENT1_TOUT0MATCHLBT (_PROTIMER_RXCTRL_RXSETEVENT1_TOUT0MATCHLBT << 0) /**< Shifted mode TOUT0MATCHLBT for PROTIMER_RXCTRL*/
+#define _PROTIMER_RXCTRL_RXSETEVENT2_SHIFT 8 /**< Shift value for PROTIMER_RXSETEVENT2 */
+#define _PROTIMER_RXCTRL_RXSETEVENT2_MASK 0x1F00UL /**< Bit mask for PROTIMER_RXSETEVENT2 */
+#define _PROTIMER_RXCTRL_RXSETEVENT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXSETEVENT2_DEFAULT (_PROTIMER_RXCTRL_RXSETEVENT2_DEFAULT << 8) /**< Shifted mode DEFAULT for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_RXCLREVENT1_SHIFT 16 /**< Shift value for PROTIMER_RXCLREVENT1 */
+#define _PROTIMER_RXCTRL_RXCLREVENT1_MASK 0x1F0000UL /**< Bit mask for PROTIMER_RXCLREVENT1 */
+#define _PROTIMER_RXCTRL_RXCLREVENT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXCLREVENT1_DEFAULT (_PROTIMER_RXCTRL_RXCLREVENT1_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_RXCTRL */
+#define _PROTIMER_RXCTRL_RXCLREVENT2_SHIFT 24 /**< Shift value for PROTIMER_RXCLREVENT2 */
+#define _PROTIMER_RXCTRL_RXCLREVENT2_MASK 0x1F000000UL /**< Bit mask for PROTIMER_RXCLREVENT2 */
+#define _PROTIMER_RXCTRL_RXCLREVENT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_RXCTRL */
+#define PROTIMER_RXCTRL_RXCLREVENT2_DEFAULT (_PROTIMER_RXCTRL_RXCLREVENT2_DEFAULT << 24) /**< Shifted mode DEFAULT for PROTIMER_RXCTRL */
+
+/* Bit fields for PROTIMER TXCTRL */
+#define _PROTIMER_TXCTRL_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_TXCTRL */
+#define _PROTIMER_TXCTRL_MASK 0x00001F1FUL /**< Mask for PROTIMER_TXCTRL */
+#define _PROTIMER_TXCTRL_TXSETEVENT1_SHIFT 0 /**< Shift value for PROTIMER_TXSETEVENT1 */
+#define _PROTIMER_TXCTRL_TXSETEVENT1_MASK 0x1FUL /**< Bit mask for PROTIMER_TXSETEVENT1 */
+#define _PROTIMER_TXCTRL_TXSETEVENT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_TXCTRL */
+#define _PROTIMER_TXCTRL_TXSETEVENT1_DISABLED 0x00000000UL /**< Mode DISABLED for PROTIMER_TXCTRL */
+#define _PROTIMER_TXCTRL_TXSETEVENT1_ALWAYS 0x00000001UL /**< Mode ALWAYS for PROTIMER_TXCTRL */
+#define _PROTIMER_TXCTRL_TXSETEVENT1_PRECNTOF 0x00000002UL /**< Mode PRECNTOF for PROTIMER_TXCTRL */
+#define _PROTIMER_TXCTRL_TXSETEVENT1_BASECNTOF 0x00000003UL /**< Mode BASECNTOF for PROTIMER_TXCTRL */
+#define _PROTIMER_TXCTRL_TXSETEVENT1_WRAPCNTOF 0x00000004UL /**< Mode WRAPCNTOF for PROTIMER_TXCTRL */
+#define _PROTIMER_TXCTRL_TXSETEVENT1_TOUT0UF 0x00000005UL /**< Mode TOUT0UF for PROTIMER_TXCTRL */
+#define _PROTIMER_TXCTRL_TXSETEVENT1_TOUT1UF 0x00000006UL /**< Mode TOUT1UF for PROTIMER_TXCTRL */
+#define _PROTIMER_TXCTRL_TXSETEVENT1_TOUT0MATCH 0x00000007UL /**< Mode TOUT0MATCH for PROTIMER_TXCTRL */
+#define _PROTIMER_TXCTRL_TXSETEVENT1_TOUT1MATCH 0x00000008UL /**< Mode TOUT1MATCH for PROTIMER_TXCTRL */
+#define _PROTIMER_TXCTRL_TXSETEVENT1_CC0 0x00000009UL /**< Mode CC0 for PROTIMER_TXCTRL */
+#define _PROTIMER_TXCTRL_TXSETEVENT1_CC1 0x0000000AUL /**< Mode CC1 for PROTIMER_TXCTRL */
+#define _PROTIMER_TXCTRL_TXSETEVENT1_CC2 0x0000000BUL /**< Mode CC2 for PROTIMER_TXCTRL */
+#define _PROTIMER_TXCTRL_TXSETEVENT1_CC3 0x0000000CUL /**< Mode CC3 for PROTIMER_TXCTRL */
+#define _PROTIMER_TXCTRL_TXSETEVENT1_CC4 0x0000000DUL /**< Mode CC4 for PROTIMER_TXCTRL */
+#define _PROTIMER_TXCTRL_TXSETEVENT1_TXDONE 0x0000000EUL /**< Mode TXDONE for PROTIMER_TXCTRL */
+#define _PROTIMER_TXCTRL_TXSETEVENT1_RXDONE 0x0000000FUL /**< Mode RXDONE for PROTIMER_TXCTRL */
+#define _PROTIMER_TXCTRL_TXSETEVENT1_TXORRXDONE 0x00000010UL /**< Mode TXORRXDONE for PROTIMER_TXCTRL */
+#define _PROTIMER_TXCTRL_TXSETEVENT1_FDET0 0x00000011UL /**< Mode FDET0 for PROTIMER_TXCTRL */
+#define _PROTIMER_TXCTRL_TXSETEVENT1_FDET1 0x00000012UL /**< Mode FDET1 for PROTIMER_TXCTRL */
+#define _PROTIMER_TXCTRL_TXSETEVENT1_FDET0OR1 0x00000013UL /**< Mode FDET0OR1 for PROTIMER_TXCTRL */
+#define _PROTIMER_TXCTRL_TXSETEVENT1_LBTSUCCESS 0x00000014UL /**< Mode LBTSUCCESS for PROTIMER_TXCTRL */
+#define _PROTIMER_TXCTRL_TXSETEVENT1_LBTRETRY 0x00000015UL /**< Mode LBTRETRY for PROTIMER_TXCTRL */
+#define _PROTIMER_TXCTRL_TXSETEVENT1_LBTFAILURE 0x00000016UL /**< Mode LBTFAILURE for PROTIMER_TXCTRL */
+#define _PROTIMER_TXCTRL_TXSETEVENT1_ANYLBT 0x00000017UL /**< Mode ANYLBT for PROTIMER_TXCTRL */
+#define _PROTIMER_TXCTRL_TXSETEVENT1_CCAACK 0x00000018UL /**< Mode CCAACK for PROTIMER_TXCTRL */
+#define _PROTIMER_TXCTRL_TXSETEVENT1_CCA 0x00000019UL /**< Mode CCA for PROTIMER_TXCTRL */
+#define _PROTIMER_TXCTRL_TXSETEVENT1_NOTCCA 0x0000001AUL /**< Mode NOTCCA for PROTIMER_TXCTRL */
+#define _PROTIMER_TXCTRL_TXSETEVENT1_TOUT0MATCHLBT 0x0000001BUL /**< Mode TOUT0MATCHLBT for PROTIMER_TXCTRL */
+#define PROTIMER_TXCTRL_TXSETEVENT1_DEFAULT (_PROTIMER_TXCTRL_TXSETEVENT1_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_TXCTRL */
+#define PROTIMER_TXCTRL_TXSETEVENT1_DISABLED (_PROTIMER_TXCTRL_TXSETEVENT1_DISABLED << 0) /**< Shifted mode DISABLED for PROTIMER_TXCTRL */
+#define PROTIMER_TXCTRL_TXSETEVENT1_ALWAYS (_PROTIMER_TXCTRL_TXSETEVENT1_ALWAYS << 0) /**< Shifted mode ALWAYS for PROTIMER_TXCTRL */
+#define PROTIMER_TXCTRL_TXSETEVENT1_PRECNTOF (_PROTIMER_TXCTRL_TXSETEVENT1_PRECNTOF << 0) /**< Shifted mode PRECNTOF for PROTIMER_TXCTRL */
+#define PROTIMER_TXCTRL_TXSETEVENT1_BASECNTOF (_PROTIMER_TXCTRL_TXSETEVENT1_BASECNTOF << 0) /**< Shifted mode BASECNTOF for PROTIMER_TXCTRL */
+#define PROTIMER_TXCTRL_TXSETEVENT1_WRAPCNTOF (_PROTIMER_TXCTRL_TXSETEVENT1_WRAPCNTOF << 0) /**< Shifted mode WRAPCNTOF for PROTIMER_TXCTRL */
+#define PROTIMER_TXCTRL_TXSETEVENT1_TOUT0UF (_PROTIMER_TXCTRL_TXSETEVENT1_TOUT0UF << 0) /**< Shifted mode TOUT0UF for PROTIMER_TXCTRL */
+#define PROTIMER_TXCTRL_TXSETEVENT1_TOUT1UF (_PROTIMER_TXCTRL_TXSETEVENT1_TOUT1UF << 0) /**< Shifted mode TOUT1UF for PROTIMER_TXCTRL */
+#define PROTIMER_TXCTRL_TXSETEVENT1_TOUT0MATCH (_PROTIMER_TXCTRL_TXSETEVENT1_TOUT0MATCH << 0) /**< Shifted mode TOUT0MATCH for PROTIMER_TXCTRL */
+#define PROTIMER_TXCTRL_TXSETEVENT1_TOUT1MATCH (_PROTIMER_TXCTRL_TXSETEVENT1_TOUT1MATCH << 0) /**< Shifted mode TOUT1MATCH for PROTIMER_TXCTRL */
+#define PROTIMER_TXCTRL_TXSETEVENT1_CC0 (_PROTIMER_TXCTRL_TXSETEVENT1_CC0 << 0) /**< Shifted mode CC0 for PROTIMER_TXCTRL */
+#define PROTIMER_TXCTRL_TXSETEVENT1_CC1 (_PROTIMER_TXCTRL_TXSETEVENT1_CC1 << 0) /**< Shifted mode CC1 for PROTIMER_TXCTRL */
+#define PROTIMER_TXCTRL_TXSETEVENT1_CC2 (_PROTIMER_TXCTRL_TXSETEVENT1_CC2 << 0) /**< Shifted mode CC2 for PROTIMER_TXCTRL */
+#define PROTIMER_TXCTRL_TXSETEVENT1_CC3 (_PROTIMER_TXCTRL_TXSETEVENT1_CC3 << 0) /**< Shifted mode CC3 for PROTIMER_TXCTRL */
+#define PROTIMER_TXCTRL_TXSETEVENT1_CC4 (_PROTIMER_TXCTRL_TXSETEVENT1_CC4 << 0) /**< Shifted mode CC4 for PROTIMER_TXCTRL */
+#define PROTIMER_TXCTRL_TXSETEVENT1_TXDONE (_PROTIMER_TXCTRL_TXSETEVENT1_TXDONE << 0) /**< Shifted mode TXDONE for PROTIMER_TXCTRL */
+#define PROTIMER_TXCTRL_TXSETEVENT1_RXDONE (_PROTIMER_TXCTRL_TXSETEVENT1_RXDONE << 0) /**< Shifted mode RXDONE for PROTIMER_TXCTRL */
+#define PROTIMER_TXCTRL_TXSETEVENT1_TXORRXDONE (_PROTIMER_TXCTRL_TXSETEVENT1_TXORRXDONE << 0) /**< Shifted mode TXORRXDONE for PROTIMER_TXCTRL */
+#define PROTIMER_TXCTRL_TXSETEVENT1_FDET0 (_PROTIMER_TXCTRL_TXSETEVENT1_FDET0 << 0) /**< Shifted mode FDET0 for PROTIMER_TXCTRL */
+#define PROTIMER_TXCTRL_TXSETEVENT1_FDET1 (_PROTIMER_TXCTRL_TXSETEVENT1_FDET1 << 0) /**< Shifted mode FDET1 for PROTIMER_TXCTRL */
+#define PROTIMER_TXCTRL_TXSETEVENT1_FDET0OR1 (_PROTIMER_TXCTRL_TXSETEVENT1_FDET0OR1 << 0) /**< Shifted mode FDET0OR1 for PROTIMER_TXCTRL */
+#define PROTIMER_TXCTRL_TXSETEVENT1_LBTSUCCESS (_PROTIMER_TXCTRL_TXSETEVENT1_LBTSUCCESS << 0) /**< Shifted mode LBTSUCCESS for PROTIMER_TXCTRL */
+#define PROTIMER_TXCTRL_TXSETEVENT1_LBTRETRY (_PROTIMER_TXCTRL_TXSETEVENT1_LBTRETRY << 0) /**< Shifted mode LBTRETRY for PROTIMER_TXCTRL */
+#define PROTIMER_TXCTRL_TXSETEVENT1_LBTFAILURE (_PROTIMER_TXCTRL_TXSETEVENT1_LBTFAILURE << 0) /**< Shifted mode LBTFAILURE for PROTIMER_TXCTRL */
+#define PROTIMER_TXCTRL_TXSETEVENT1_ANYLBT (_PROTIMER_TXCTRL_TXSETEVENT1_ANYLBT << 0) /**< Shifted mode ANYLBT for PROTIMER_TXCTRL */
+#define PROTIMER_TXCTRL_TXSETEVENT1_CCAACK (_PROTIMER_TXCTRL_TXSETEVENT1_CCAACK << 0) /**< Shifted mode CCAACK for PROTIMER_TXCTRL */
+#define PROTIMER_TXCTRL_TXSETEVENT1_CCA (_PROTIMER_TXCTRL_TXSETEVENT1_CCA << 0) /**< Shifted mode CCA for PROTIMER_TXCTRL */
+#define PROTIMER_TXCTRL_TXSETEVENT1_NOTCCA (_PROTIMER_TXCTRL_TXSETEVENT1_NOTCCA << 0) /**< Shifted mode NOTCCA for PROTIMER_TXCTRL */
+#define PROTIMER_TXCTRL_TXSETEVENT1_TOUT0MATCHLBT (_PROTIMER_TXCTRL_TXSETEVENT1_TOUT0MATCHLBT << 0) /**< Shifted mode TOUT0MATCHLBT for PROTIMER_TXCTRL*/
+#define _PROTIMER_TXCTRL_TXSETEVENT2_SHIFT 8 /**< Shift value for PROTIMER_TXSETEVENT2 */
+#define _PROTIMER_TXCTRL_TXSETEVENT2_MASK 0x1F00UL /**< Bit mask for PROTIMER_TXSETEVENT2 */
+#define _PROTIMER_TXCTRL_TXSETEVENT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_TXCTRL */
+#define PROTIMER_TXCTRL_TXSETEVENT2_DEFAULT (_PROTIMER_TXCTRL_TXSETEVENT2_DEFAULT << 8) /**< Shifted mode DEFAULT for PROTIMER_TXCTRL */
+
+/* Bit fields for PROTIMER ETSI */
+#define _PROTIMER_ETSI_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_ETSI */
+#define _PROTIMER_ETSI_MASK 0x03FFFFFFUL /**< Mask for PROTIMER_ETSI */
+#define PROTIMER_ETSI_ETSIEN (0x1UL << 0) /**< ETSI LBT enabling */
+#define _PROTIMER_ETSI_ETSIEN_SHIFT 0 /**< Shift value for PROTIMER_ETSIEN */
+#define _PROTIMER_ETSI_ETSIEN_MASK 0x1UL /**< Bit mask for PROTIMER_ETSIEN */
+#define _PROTIMER_ETSI_ETSIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_ETSI */
+#define PROTIMER_ETSI_ETSIEN_DEFAULT (_PROTIMER_ETSI_ETSIEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_ETSI */
+#define PROTIMER_ETSI_GRANULARLESSTHANRXWARM (0x1UL << 1) /**< Granular less than RXWARM */
+#define _PROTIMER_ETSI_GRANULARLESSTHANRXWARM_SHIFT 1 /**< Shift value for PROTIMER_GRANULARLESSTHANRXWARM*/
+#define _PROTIMER_ETSI_GRANULARLESSTHANRXWARM_MASK 0x2UL /**< Bit mask for PROTIMER_GRANULARLESSTHANRXWARM*/
+#define _PROTIMER_ETSI_GRANULARLESSTHANRXWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_ETSI */
+#define PROTIMER_ETSI_GRANULARLESSTHANRXWARM_DEFAULT (_PROTIMER_ETSI_GRANULARLESSTHANRXWARM_DEFAULT << 1) /**< Shifted mode DEFAULT for PROTIMER_ETSI */
+#define _PROTIMER_ETSI_RXWARMTHLD_SHIFT 2 /**< Shift value for PROTIMER_RXWARMTHLD */
+#define _PROTIMER_ETSI_RXWARMTHLD_MASK 0x3FCUL /**< Bit mask for PROTIMER_RXWARMTHLD */
+#define _PROTIMER_ETSI_RXWARMTHLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_ETSI */
+#define PROTIMER_ETSI_RXWARMTHLD_DEFAULT (_PROTIMER_ETSI_RXWARMTHLD_DEFAULT << 2) /**< Shifted mode DEFAULT for PROTIMER_ETSI */
+#define _PROTIMER_ETSI_CCAFIXED_SHIFT 10 /**< Shift value for PROTIMER_CCAFIXED */
+#define _PROTIMER_ETSI_CCAFIXED_MASK 0x3FFFC00UL /**< Bit mask for PROTIMER_CCAFIXED */
+#define _PROTIMER_ETSI_CCAFIXED_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_ETSI */
+#define PROTIMER_ETSI_CCAFIXED_DEFAULT (_PROTIMER_ETSI_CCAFIXED_DEFAULT << 10) /**< Shifted mode DEFAULT for PROTIMER_ETSI */
+
+/* Bit fields for PROTIMER LBTSTATE1 */
+#define _PROTIMER_LBTSTATE1_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_LBTSTATE1 */
+#define _PROTIMER_LBTSTATE1_MASK 0x00000FFFUL /**< Mask for PROTIMER_LBTSTATE1 */
+#define _PROTIMER_LBTSTATE1_CCACNT_SHIFT 0 /**< Shift value for PROTIMER_CCACNT */
+#define _PROTIMER_LBTSTATE1_CCACNT_MASK 0xFUL /**< Bit mask for PROTIMER_CCACNT */
+#define _PROTIMER_LBTSTATE1_CCACNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_LBTSTATE1 */
+#define PROTIMER_LBTSTATE1_CCACNT_DEFAULT (_PROTIMER_LBTSTATE1_CCACNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_LBTSTATE1 */
+#define _PROTIMER_LBTSTATE1_EXP_SHIFT 4 /**< Shift value for PROTIMER_EXP */
+#define _PROTIMER_LBTSTATE1_EXP_MASK 0xF0UL /**< Bit mask for PROTIMER_EXP */
+#define _PROTIMER_LBTSTATE1_EXP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_LBTSTATE1 */
+#define PROTIMER_LBTSTATE1_EXP_DEFAULT (_PROTIMER_LBTSTATE1_EXP_DEFAULT << 4) /**< Shifted mode DEFAULT for PROTIMER_LBTSTATE1 */
+#define _PROTIMER_LBTSTATE1_RETRYCNT_SHIFT 8 /**< Shift value for PROTIMER_RETRYCNT */
+#define _PROTIMER_LBTSTATE1_RETRYCNT_MASK 0xF00UL /**< Bit mask for PROTIMER_RETRYCNT */
+#define _PROTIMER_LBTSTATE1_RETRYCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_LBTSTATE1 */
+#define PROTIMER_LBTSTATE1_RETRYCNT_DEFAULT (_PROTIMER_LBTSTATE1_RETRYCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for PROTIMER_LBTSTATE1 */
+
+/* Bit fields for PROTIMER RANDOMFW0 */
+#define _PROTIMER_RANDOMFW0_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_RANDOMFW0 */
+#define _PROTIMER_RANDOMFW0_MASK 0x07FFFFFFUL /**< Mask for PROTIMER_RANDOMFW0 */
+#define _PROTIMER_RANDOMFW0_RANDOM0_SHIFT 0 /**< Shift value for PROTIMER_RANDOM0 */
+#define _PROTIMER_RANDOMFW0_RANDOM0_MASK 0x1FFUL /**< Bit mask for PROTIMER_RANDOM0 */
+#define _PROTIMER_RANDOMFW0_RANDOM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_RANDOMFW0 */
+#define PROTIMER_RANDOMFW0_RANDOM0_DEFAULT (_PROTIMER_RANDOMFW0_RANDOM0_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_RANDOMFW0 */
+#define _PROTIMER_RANDOMFW0_RANDOM1_SHIFT 9 /**< Shift value for PROTIMER_RANDOM1 */
+#define _PROTIMER_RANDOMFW0_RANDOM1_MASK 0x3FE00UL /**< Bit mask for PROTIMER_RANDOM1 */
+#define _PROTIMER_RANDOMFW0_RANDOM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_RANDOMFW0 */
+#define PROTIMER_RANDOMFW0_RANDOM1_DEFAULT (_PROTIMER_RANDOMFW0_RANDOM1_DEFAULT << 9) /**< Shifted mode DEFAULT for PROTIMER_RANDOMFW0 */
+#define _PROTIMER_RANDOMFW0_RANDOM2_SHIFT 18 /**< Shift value for PROTIMER_RANDOM2 */
+#define _PROTIMER_RANDOMFW0_RANDOM2_MASK 0x7FC0000UL /**< Bit mask for PROTIMER_RANDOM2 */
+#define _PROTIMER_RANDOMFW0_RANDOM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_RANDOMFW0 */
+#define PROTIMER_RANDOMFW0_RANDOM2_DEFAULT (_PROTIMER_RANDOMFW0_RANDOM2_DEFAULT << 18) /**< Shifted mode DEFAULT for PROTIMER_RANDOMFW0 */
+
+/* Bit fields for PROTIMER RANDOMFW1 */
+#define _PROTIMER_RANDOMFW1_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_RANDOMFW1 */
+#define _PROTIMER_RANDOMFW1_MASK 0x07FFFFFFUL /**< Mask for PROTIMER_RANDOMFW1 */
+#define _PROTIMER_RANDOMFW1_RANDOM3_SHIFT 0 /**< Shift value for PROTIMER_RANDOM3 */
+#define _PROTIMER_RANDOMFW1_RANDOM3_MASK 0x1FFUL /**< Bit mask for PROTIMER_RANDOM3 */
+#define _PROTIMER_RANDOMFW1_RANDOM3_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_RANDOMFW1 */
+#define PROTIMER_RANDOMFW1_RANDOM3_DEFAULT (_PROTIMER_RANDOMFW1_RANDOM3_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_RANDOMFW1 */
+#define _PROTIMER_RANDOMFW1_RANDOM4_SHIFT 9 /**< Shift value for PROTIMER_RANDOM4 */
+#define _PROTIMER_RANDOMFW1_RANDOM4_MASK 0x3FE00UL /**< Bit mask for PROTIMER_RANDOM4 */
+#define _PROTIMER_RANDOMFW1_RANDOM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_RANDOMFW1 */
+#define PROTIMER_RANDOMFW1_RANDOM4_DEFAULT (_PROTIMER_RANDOMFW1_RANDOM4_DEFAULT << 9) /**< Shifted mode DEFAULT for PROTIMER_RANDOMFW1 */
+#define _PROTIMER_RANDOMFW1_RANDOM5_SHIFT 18 /**< Shift value for PROTIMER_RANDOM5 */
+#define _PROTIMER_RANDOMFW1_RANDOM5_MASK 0x7FC0000UL /**< Bit mask for PROTIMER_RANDOM5 */
+#define _PROTIMER_RANDOMFW1_RANDOM5_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_RANDOMFW1 */
+#define PROTIMER_RANDOMFW1_RANDOM5_DEFAULT (_PROTIMER_RANDOMFW1_RANDOM5_DEFAULT << 18) /**< Shifted mode DEFAULT for PROTIMER_RANDOMFW1 */
+
+/* Bit fields for PROTIMER RANDOMFW2 */
+#define _PROTIMER_RANDOMFW2_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_RANDOMFW2 */
+#define _PROTIMER_RANDOMFW2_MASK 0x0003FFFFUL /**< Mask for PROTIMER_RANDOMFW2 */
+#define _PROTIMER_RANDOMFW2_RANDOM6_SHIFT 0 /**< Shift value for PROTIMER_RANDOM6 */
+#define _PROTIMER_RANDOMFW2_RANDOM6_MASK 0x1FFUL /**< Bit mask for PROTIMER_RANDOM6 */
+#define _PROTIMER_RANDOMFW2_RANDOM6_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_RANDOMFW2 */
+#define PROTIMER_RANDOMFW2_RANDOM6_DEFAULT (_PROTIMER_RANDOMFW2_RANDOM6_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_RANDOMFW2 */
+#define _PROTIMER_RANDOMFW2_RANDOM7_SHIFT 9 /**< Shift value for PROTIMER_RANDOM7 */
+#define _PROTIMER_RANDOMFW2_RANDOM7_MASK 0x3FE00UL /**< Bit mask for PROTIMER_RANDOM7 */
+#define _PROTIMER_RANDOMFW2_RANDOM7_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_RANDOMFW2 */
+#define PROTIMER_RANDOMFW2_RANDOM7_DEFAULT (_PROTIMER_RANDOMFW2_RANDOM7_DEFAULT << 9) /**< Shifted mode DEFAULT for PROTIMER_RANDOMFW2 */
+
+/* Bit fields for PROTIMER SEQIF */
+#define _PROTIMER_SEQIF_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_SEQIF */
+#define _PROTIMER_SEQIF_MASK 0x3FFFFFF7UL /**< Mask for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_PRECNTOF (0x1UL << 0) /**< PRECNT Overflow Interrupt Flag */
+#define _PROTIMER_SEQIF_PRECNTOF_SHIFT 0 /**< Shift value for PROTIMER_PRECNTOF */
+#define _PROTIMER_SEQIF_PRECNTOF_MASK 0x1UL /**< Bit mask for PROTIMER_PRECNTOF */
+#define _PROTIMER_SEQIF_PRECNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_PRECNTOF_DEFAULT (_PROTIMER_SEQIF_PRECNTOF_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_BASECNTOF (0x1UL << 1) /**< BASECNT Overflow Interrupt Flag */
+#define _PROTIMER_SEQIF_BASECNTOF_SHIFT 1 /**< Shift value for PROTIMER_BASECNTOF */
+#define _PROTIMER_SEQIF_BASECNTOF_MASK 0x2UL /**< Bit mask for PROTIMER_BASECNTOF */
+#define _PROTIMER_SEQIF_BASECNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_BASECNTOF_DEFAULT (_PROTIMER_SEQIF_BASECNTOF_DEFAULT << 1) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_WRAPCNTOF (0x1UL << 2) /**< WRAPCNT Overflow Interrupt Flag */
+#define _PROTIMER_SEQIF_WRAPCNTOF_SHIFT 2 /**< Shift value for PROTIMER_WRAPCNTOF */
+#define _PROTIMER_SEQIF_WRAPCNTOF_MASK 0x4UL /**< Bit mask for PROTIMER_WRAPCNTOF */
+#define _PROTIMER_SEQIF_WRAPCNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_WRAPCNTOF_DEFAULT (_PROTIMER_SEQIF_WRAPCNTOF_DEFAULT << 2) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_TOUT0 (0x1UL << 4) /**< TOUT0 underflow interrupt flag */
+#define _PROTIMER_SEQIF_TOUT0_SHIFT 4 /**< Shift value for PROTIMER_TOUT0 */
+#define _PROTIMER_SEQIF_TOUT0_MASK 0x10UL /**< Bit mask for PROTIMER_TOUT0 */
+#define _PROTIMER_SEQIF_TOUT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_TOUT0_DEFAULT (_PROTIMER_SEQIF_TOUT0_DEFAULT << 4) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_TOUT1 (0x1UL << 5) /**< TOUT1 underflow interrupt flag */
+#define _PROTIMER_SEQIF_TOUT1_SHIFT 5 /**< Shift value for PROTIMER_TOUT1 */
+#define _PROTIMER_SEQIF_TOUT1_MASK 0x20UL /**< Bit mask for PROTIMER_TOUT1 */
+#define _PROTIMER_SEQIF_TOUT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_TOUT1_DEFAULT (_PROTIMER_SEQIF_TOUT1_DEFAULT << 5) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_TOUT0MATCH (0x1UL << 6) /**< TOUT0 compare match interrupt flag */
+#define _PROTIMER_SEQIF_TOUT0MATCH_SHIFT 6 /**< Shift value for PROTIMER_TOUT0MATCH */
+#define _PROTIMER_SEQIF_TOUT0MATCH_MASK 0x40UL /**< Bit mask for PROTIMER_TOUT0MATCH */
+#define _PROTIMER_SEQIF_TOUT0MATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_TOUT0MATCH_DEFAULT (_PROTIMER_SEQIF_TOUT0MATCH_DEFAULT << 6) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_TOUT1MATCH (0x1UL << 7) /**< TOUT1 compare match interrupt flag */
+#define _PROTIMER_SEQIF_TOUT1MATCH_SHIFT 7 /**< Shift value for PROTIMER_TOUT1MATCH */
+#define _PROTIMER_SEQIF_TOUT1MATCH_MASK 0x80UL /**< Bit mask for PROTIMER_TOUT1MATCH */
+#define _PROTIMER_SEQIF_TOUT1MATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_TOUT1MATCH_DEFAULT (_PROTIMER_SEQIF_TOUT1MATCH_DEFAULT << 7) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_CC0 (0x1UL << 8) /**< CC Channel 0 Interrupt Flag */
+#define _PROTIMER_SEQIF_CC0_SHIFT 8 /**< Shift value for PROTIMER_CC0 */
+#define _PROTIMER_SEQIF_CC0_MASK 0x100UL /**< Bit mask for PROTIMER_CC0 */
+#define _PROTIMER_SEQIF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_CC0_DEFAULT (_PROTIMER_SEQIF_CC0_DEFAULT << 8) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_CC1 (0x1UL << 9) /**< CC Channel 1 Interrupt Flag */
+#define _PROTIMER_SEQIF_CC1_SHIFT 9 /**< Shift value for PROTIMER_CC1 */
+#define _PROTIMER_SEQIF_CC1_MASK 0x200UL /**< Bit mask for PROTIMER_CC1 */
+#define _PROTIMER_SEQIF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_CC1_DEFAULT (_PROTIMER_SEQIF_CC1_DEFAULT << 9) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_CC2 (0x1UL << 10) /**< CC Channel 2 Interrupt Flag */
+#define _PROTIMER_SEQIF_CC2_SHIFT 10 /**< Shift value for PROTIMER_CC2 */
+#define _PROTIMER_SEQIF_CC2_MASK 0x400UL /**< Bit mask for PROTIMER_CC2 */
+#define _PROTIMER_SEQIF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_CC2_DEFAULT (_PROTIMER_SEQIF_CC2_DEFAULT << 10) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_CC3 (0x1UL << 11) /**< CC Channel 3 Interrupt Flag */
+#define _PROTIMER_SEQIF_CC3_SHIFT 11 /**< Shift value for PROTIMER_CC3 */
+#define _PROTIMER_SEQIF_CC3_MASK 0x800UL /**< Bit mask for PROTIMER_CC3 */
+#define _PROTIMER_SEQIF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_CC3_DEFAULT (_PROTIMER_SEQIF_CC3_DEFAULT << 11) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_CC4 (0x1UL << 12) /**< CC Channel 4 Interrupt Flag */
+#define _PROTIMER_SEQIF_CC4_SHIFT 12 /**< Shift value for PROTIMER_CC4 */
+#define _PROTIMER_SEQIF_CC4_MASK 0x1000UL /**< Bit mask for PROTIMER_CC4 */
+#define _PROTIMER_SEQIF_CC4_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_CC4_DEFAULT (_PROTIMER_SEQIF_CC4_DEFAULT << 12) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_CC5 (0x1UL << 13) /**< CC Channel 5 Interrupt Flag */
+#define _PROTIMER_SEQIF_CC5_SHIFT 13 /**< Shift value for PROTIMER_CC5 */
+#define _PROTIMER_SEQIF_CC5_MASK 0x2000UL /**< Bit mask for PROTIMER_CC5 */
+#define _PROTIMER_SEQIF_CC5_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_CC5_DEFAULT (_PROTIMER_SEQIF_CC5_DEFAULT << 13) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_CC6 (0x1UL << 14) /**< CC Channel 6 Interrupt Flag */
+#define _PROTIMER_SEQIF_CC6_SHIFT 14 /**< Shift value for PROTIMER_CC6 */
+#define _PROTIMER_SEQIF_CC6_MASK 0x4000UL /**< Bit mask for PROTIMER_CC6 */
+#define _PROTIMER_SEQIF_CC6_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_CC6_DEFAULT (_PROTIMER_SEQIF_CC6_DEFAULT << 14) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_CC7 (0x1UL << 15) /**< CC Channel 7 Interrupt Flag */
+#define _PROTIMER_SEQIF_CC7_SHIFT 15 /**< Shift value for PROTIMER_CC7 */
+#define _PROTIMER_SEQIF_CC7_MASK 0x8000UL /**< Bit mask for PROTIMER_CC7 */
+#define _PROTIMER_SEQIF_CC7_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_CC7_DEFAULT (_PROTIMER_SEQIF_CC7_DEFAULT << 15) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_COF0 (0x1UL << 16) /**< CC Channel 0 Overflow Interrupt Flag */
+#define _PROTIMER_SEQIF_COF0_SHIFT 16 /**< Shift value for PROTIMER_COF0 */
+#define _PROTIMER_SEQIF_COF0_MASK 0x10000UL /**< Bit mask for PROTIMER_COF0 */
+#define _PROTIMER_SEQIF_COF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_COF0_DEFAULT (_PROTIMER_SEQIF_COF0_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_COF1 (0x1UL << 17) /**< CC Channel 1 Overflow Interrupt Flag */
+#define _PROTIMER_SEQIF_COF1_SHIFT 17 /**< Shift value for PROTIMER_COF1 */
+#define _PROTIMER_SEQIF_COF1_MASK 0x20000UL /**< Bit mask for PROTIMER_COF1 */
+#define _PROTIMER_SEQIF_COF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_COF1_DEFAULT (_PROTIMER_SEQIF_COF1_DEFAULT << 17) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_COF2 (0x1UL << 18) /**< CC Channel 2 Overflow Interrupt Flag */
+#define _PROTIMER_SEQIF_COF2_SHIFT 18 /**< Shift value for PROTIMER_COF2 */
+#define _PROTIMER_SEQIF_COF2_MASK 0x40000UL /**< Bit mask for PROTIMER_COF2 */
+#define _PROTIMER_SEQIF_COF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_COF2_DEFAULT (_PROTIMER_SEQIF_COF2_DEFAULT << 18) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_COF3 (0x1UL << 19) /**< CC Channel 3 Overflow Interrupt Flag */
+#define _PROTIMER_SEQIF_COF3_SHIFT 19 /**< Shift value for PROTIMER_COF3 */
+#define _PROTIMER_SEQIF_COF3_MASK 0x80000UL /**< Bit mask for PROTIMER_COF3 */
+#define _PROTIMER_SEQIF_COF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_COF3_DEFAULT (_PROTIMER_SEQIF_COF3_DEFAULT << 19) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_COF4 (0x1UL << 20) /**< CC Channel 4 Overflow Interrupt Flag */
+#define _PROTIMER_SEQIF_COF4_SHIFT 20 /**< Shift value for PROTIMER_COF4 */
+#define _PROTIMER_SEQIF_COF4_MASK 0x100000UL /**< Bit mask for PROTIMER_COF4 */
+#define _PROTIMER_SEQIF_COF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_COF4_DEFAULT (_PROTIMER_SEQIF_COF4_DEFAULT << 20) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_COF5 (0x1UL << 21) /**< CC Channel 5 Overflow Interrupt Flag */
+#define _PROTIMER_SEQIF_COF5_SHIFT 21 /**< Shift value for PROTIMER_COF5 */
+#define _PROTIMER_SEQIF_COF5_MASK 0x200000UL /**< Bit mask for PROTIMER_COF5 */
+#define _PROTIMER_SEQIF_COF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_COF5_DEFAULT (_PROTIMER_SEQIF_COF5_DEFAULT << 21) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_COF6 (0x1UL << 22) /**< CC Channel 6 Overflow Interrupt Flag */
+#define _PROTIMER_SEQIF_COF6_SHIFT 22 /**< Shift value for PROTIMER_COF6 */
+#define _PROTIMER_SEQIF_COF6_MASK 0x400000UL /**< Bit mask for PROTIMER_COF6 */
+#define _PROTIMER_SEQIF_COF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_COF6_DEFAULT (_PROTIMER_SEQIF_COF6_DEFAULT << 22) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_COF7 (0x1UL << 23) /**< CC Channel 7 Overflow Interrupt Flag */
+#define _PROTIMER_SEQIF_COF7_SHIFT 23 /**< Shift value for PROTIMER_COF7 */
+#define _PROTIMER_SEQIF_COF7_MASK 0x800000UL /**< Bit mask for PROTIMER_COF7 */
+#define _PROTIMER_SEQIF_COF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_COF7_DEFAULT (_PROTIMER_SEQIF_COF7_DEFAULT << 23) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_LBTSUCCESS (0x1UL << 24) /**< Listen Before Talk Success */
+#define _PROTIMER_SEQIF_LBTSUCCESS_SHIFT 24 /**< Shift value for PROTIMER_LBTSUCCESS */
+#define _PROTIMER_SEQIF_LBTSUCCESS_MASK 0x1000000UL /**< Bit mask for PROTIMER_LBTSUCCESS */
+#define _PROTIMER_SEQIF_LBTSUCCESS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_LBTSUCCESS_DEFAULT (_PROTIMER_SEQIF_LBTSUCCESS_DEFAULT << 24) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_LBTFAILURE (0x1UL << 25) /**< Listen Before Talk Failure */
+#define _PROTIMER_SEQIF_LBTFAILURE_SHIFT 25 /**< Shift value for PROTIMER_LBTFAILURE */
+#define _PROTIMER_SEQIF_LBTFAILURE_MASK 0x2000000UL /**< Bit mask for PROTIMER_LBTFAILURE */
+#define _PROTIMER_SEQIF_LBTFAILURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_LBTFAILURE_DEFAULT (_PROTIMER_SEQIF_LBTFAILURE_DEFAULT << 25) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_LBTPAUSED (0x1UL << 26) /**< Listen Before Talk Paused */
+#define _PROTIMER_SEQIF_LBTPAUSED_SHIFT 26 /**< Shift value for PROTIMER_LBTPAUSED */
+#define _PROTIMER_SEQIF_LBTPAUSED_MASK 0x4000000UL /**< Bit mask for PROTIMER_LBTPAUSED */
+#define _PROTIMER_SEQIF_LBTPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_LBTPAUSED_DEFAULT (_PROTIMER_SEQIF_LBTPAUSED_DEFAULT << 26) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_LBTRETRY (0x1UL << 27) /**< Listen Before Talk Retry */
+#define _PROTIMER_SEQIF_LBTRETRY_SHIFT 27 /**< Shift value for PROTIMER_LBTRETRY */
+#define _PROTIMER_SEQIF_LBTRETRY_MASK 0x8000000UL /**< Bit mask for PROTIMER_LBTRETRY */
+#define _PROTIMER_SEQIF_LBTRETRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_LBTRETRY_DEFAULT (_PROTIMER_SEQIF_LBTRETRY_DEFAULT << 27) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_RTCCSYNCHED (0x1UL << 28) /**< PROTIMER synchronized with the RTCC */
+#define _PROTIMER_SEQIF_RTCCSYNCHED_SHIFT 28 /**< Shift value for PROTIMER_RTCCSYNCHED */
+#define _PROTIMER_SEQIF_RTCCSYNCHED_MASK 0x10000000UL /**< Bit mask for PROTIMER_RTCCSYNCHED */
+#define _PROTIMER_SEQIF_RTCCSYNCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_RTCCSYNCHED_DEFAULT (_PROTIMER_SEQIF_RTCCSYNCHED_DEFAULT << 28) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_TOUT0MATCHLBT (0x1UL << 29) /**< TOUT0 compare match interrupt flag */
+#define _PROTIMER_SEQIF_TOUT0MATCHLBT_SHIFT 29 /**< Shift value for PROTIMER_TOUT0MATCHLBT */
+#define _PROTIMER_SEQIF_TOUT0MATCHLBT_MASK 0x20000000UL /**< Bit mask for PROTIMER_TOUT0MATCHLBT */
+#define _PROTIMER_SEQIF_TOUT0MATCHLBT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIF */
+#define PROTIMER_SEQIF_TOUT0MATCHLBT_DEFAULT (_PROTIMER_SEQIF_TOUT0MATCHLBT_DEFAULT << 29) /**< Shifted mode DEFAULT for PROTIMER_SEQIF */
+
+/* Bit fields for PROTIMER SEQIEN */
+#define _PROTIMER_SEQIEN_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_SEQIEN */
+#define _PROTIMER_SEQIEN_MASK 0x3FFFFFF7UL /**< Mask for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_PRECNTOF (0x1UL << 0) /**< PRECNTOF Interrupt Enable */
+#define _PROTIMER_SEQIEN_PRECNTOF_SHIFT 0 /**< Shift value for PROTIMER_PRECNTOF */
+#define _PROTIMER_SEQIEN_PRECNTOF_MASK 0x1UL /**< Bit mask for PROTIMER_PRECNTOF */
+#define _PROTIMER_SEQIEN_PRECNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_PRECNTOF_DEFAULT (_PROTIMER_SEQIEN_PRECNTOF_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_BASECNTOF (0x1UL << 1) /**< BASECNTOF Interrupt Enable */
+#define _PROTIMER_SEQIEN_BASECNTOF_SHIFT 1 /**< Shift value for PROTIMER_BASECNTOF */
+#define _PROTIMER_SEQIEN_BASECNTOF_MASK 0x2UL /**< Bit mask for PROTIMER_BASECNTOF */
+#define _PROTIMER_SEQIEN_BASECNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_BASECNTOF_DEFAULT (_PROTIMER_SEQIEN_BASECNTOF_DEFAULT << 1) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_WRAPCNTOF (0x1UL << 2) /**< WRAPCNTOF Interrupt Enable */
+#define _PROTIMER_SEQIEN_WRAPCNTOF_SHIFT 2 /**< Shift value for PROTIMER_WRAPCNTOF */
+#define _PROTIMER_SEQIEN_WRAPCNTOF_MASK 0x4UL /**< Bit mask for PROTIMER_WRAPCNTOF */
+#define _PROTIMER_SEQIEN_WRAPCNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_WRAPCNTOF_DEFAULT (_PROTIMER_SEQIEN_WRAPCNTOF_DEFAULT << 2) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_TOUT0 (0x1UL << 4) /**< TOUT0 Interrupt Enable */
+#define _PROTIMER_SEQIEN_TOUT0_SHIFT 4 /**< Shift value for PROTIMER_TOUT0 */
+#define _PROTIMER_SEQIEN_TOUT0_MASK 0x10UL /**< Bit mask for PROTIMER_TOUT0 */
+#define _PROTIMER_SEQIEN_TOUT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_TOUT0_DEFAULT (_PROTIMER_SEQIEN_TOUT0_DEFAULT << 4) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_TOUT1 (0x1UL << 5) /**< TOUT1 Interrupt Enable */
+#define _PROTIMER_SEQIEN_TOUT1_SHIFT 5 /**< Shift value for PROTIMER_TOUT1 */
+#define _PROTIMER_SEQIEN_TOUT1_MASK 0x20UL /**< Bit mask for PROTIMER_TOUT1 */
+#define _PROTIMER_SEQIEN_TOUT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_TOUT1_DEFAULT (_PROTIMER_SEQIEN_TOUT1_DEFAULT << 5) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_TOUT0MATCH (0x1UL << 6) /**< TOUT0MATCH Interrupt Enable */
+#define _PROTIMER_SEQIEN_TOUT0MATCH_SHIFT 6 /**< Shift value for PROTIMER_TOUT0MATCH */
+#define _PROTIMER_SEQIEN_TOUT0MATCH_MASK 0x40UL /**< Bit mask for PROTIMER_TOUT0MATCH */
+#define _PROTIMER_SEQIEN_TOUT0MATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_TOUT0MATCH_DEFAULT (_PROTIMER_SEQIEN_TOUT0MATCH_DEFAULT << 6) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_TOUT1MATCH (0x1UL << 7) /**< TOUT1MATCH Interrupt Enable */
+#define _PROTIMER_SEQIEN_TOUT1MATCH_SHIFT 7 /**< Shift value for PROTIMER_TOUT1MATCH */
+#define _PROTIMER_SEQIEN_TOUT1MATCH_MASK 0x80UL /**< Bit mask for PROTIMER_TOUT1MATCH */
+#define _PROTIMER_SEQIEN_TOUT1MATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_TOUT1MATCH_DEFAULT (_PROTIMER_SEQIEN_TOUT1MATCH_DEFAULT << 7) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_CC0 (0x1UL << 8) /**< CC0 Interrupt Enable */
+#define _PROTIMER_SEQIEN_CC0_SHIFT 8 /**< Shift value for PROTIMER_CC0 */
+#define _PROTIMER_SEQIEN_CC0_MASK 0x100UL /**< Bit mask for PROTIMER_CC0 */
+#define _PROTIMER_SEQIEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_CC0_DEFAULT (_PROTIMER_SEQIEN_CC0_DEFAULT << 8) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_CC1 (0x1UL << 9) /**< CC1 Interrupt Enable */
+#define _PROTIMER_SEQIEN_CC1_SHIFT 9 /**< Shift value for PROTIMER_CC1 */
+#define _PROTIMER_SEQIEN_CC1_MASK 0x200UL /**< Bit mask for PROTIMER_CC1 */
+#define _PROTIMER_SEQIEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_CC1_DEFAULT (_PROTIMER_SEQIEN_CC1_DEFAULT << 9) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_CC2 (0x1UL << 10) /**< CC2 Interrupt Enable */
+#define _PROTIMER_SEQIEN_CC2_SHIFT 10 /**< Shift value for PROTIMER_CC2 */
+#define _PROTIMER_SEQIEN_CC2_MASK 0x400UL /**< Bit mask for PROTIMER_CC2 */
+#define _PROTIMER_SEQIEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_CC2_DEFAULT (_PROTIMER_SEQIEN_CC2_DEFAULT << 10) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_CC3 (0x1UL << 11) /**< CC3 Interrupt Enable */
+#define _PROTIMER_SEQIEN_CC3_SHIFT 11 /**< Shift value for PROTIMER_CC3 */
+#define _PROTIMER_SEQIEN_CC3_MASK 0x800UL /**< Bit mask for PROTIMER_CC3 */
+#define _PROTIMER_SEQIEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_CC3_DEFAULT (_PROTIMER_SEQIEN_CC3_DEFAULT << 11) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_CC4 (0x1UL << 12) /**< CC4 Interrupt Enable */
+#define _PROTIMER_SEQIEN_CC4_SHIFT 12 /**< Shift value for PROTIMER_CC4 */
+#define _PROTIMER_SEQIEN_CC4_MASK 0x1000UL /**< Bit mask for PROTIMER_CC4 */
+#define _PROTIMER_SEQIEN_CC4_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_CC4_DEFAULT (_PROTIMER_SEQIEN_CC4_DEFAULT << 12) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_CC5 (0x1UL << 13) /**< CC5 Interrupt Enable */
+#define _PROTIMER_SEQIEN_CC5_SHIFT 13 /**< Shift value for PROTIMER_CC5 */
+#define _PROTIMER_SEQIEN_CC5_MASK 0x2000UL /**< Bit mask for PROTIMER_CC5 */
+#define _PROTIMER_SEQIEN_CC5_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_CC5_DEFAULT (_PROTIMER_SEQIEN_CC5_DEFAULT << 13) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_CC6 (0x1UL << 14) /**< CC6 Interrupt Enable */
+#define _PROTIMER_SEQIEN_CC6_SHIFT 14 /**< Shift value for PROTIMER_CC6 */
+#define _PROTIMER_SEQIEN_CC6_MASK 0x4000UL /**< Bit mask for PROTIMER_CC6 */
+#define _PROTIMER_SEQIEN_CC6_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_CC6_DEFAULT (_PROTIMER_SEQIEN_CC6_DEFAULT << 14) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_CC7 (0x1UL << 15) /**< CC7 Interrupt Enable */
+#define _PROTIMER_SEQIEN_CC7_SHIFT 15 /**< Shift value for PROTIMER_CC7 */
+#define _PROTIMER_SEQIEN_CC7_MASK 0x8000UL /**< Bit mask for PROTIMER_CC7 */
+#define _PROTIMER_SEQIEN_CC7_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_CC7_DEFAULT (_PROTIMER_SEQIEN_CC7_DEFAULT << 15) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_COF0 (0x1UL << 16) /**< COF0 Interrupt Enable */
+#define _PROTIMER_SEQIEN_COF0_SHIFT 16 /**< Shift value for PROTIMER_COF0 */
+#define _PROTIMER_SEQIEN_COF0_MASK 0x10000UL /**< Bit mask for PROTIMER_COF0 */
+#define _PROTIMER_SEQIEN_COF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_COF0_DEFAULT (_PROTIMER_SEQIEN_COF0_DEFAULT << 16) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_COF1 (0x1UL << 17) /**< COF1 Interrupt Enable */
+#define _PROTIMER_SEQIEN_COF1_SHIFT 17 /**< Shift value for PROTIMER_COF1 */
+#define _PROTIMER_SEQIEN_COF1_MASK 0x20000UL /**< Bit mask for PROTIMER_COF1 */
+#define _PROTIMER_SEQIEN_COF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_COF1_DEFAULT (_PROTIMER_SEQIEN_COF1_DEFAULT << 17) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_COF2 (0x1UL << 18) /**< COF2 Interrupt Enable */
+#define _PROTIMER_SEQIEN_COF2_SHIFT 18 /**< Shift value for PROTIMER_COF2 */
+#define _PROTIMER_SEQIEN_COF2_MASK 0x40000UL /**< Bit mask for PROTIMER_COF2 */
+#define _PROTIMER_SEQIEN_COF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_COF2_DEFAULT (_PROTIMER_SEQIEN_COF2_DEFAULT << 18) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_COF3 (0x1UL << 19) /**< COF3 Interrupt Enable */
+#define _PROTIMER_SEQIEN_COF3_SHIFT 19 /**< Shift value for PROTIMER_COF3 */
+#define _PROTIMER_SEQIEN_COF3_MASK 0x80000UL /**< Bit mask for PROTIMER_COF3 */
+#define _PROTIMER_SEQIEN_COF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_COF3_DEFAULT (_PROTIMER_SEQIEN_COF3_DEFAULT << 19) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_COF4 (0x1UL << 20) /**< COF4 Interrupt Enable */
+#define _PROTIMER_SEQIEN_COF4_SHIFT 20 /**< Shift value for PROTIMER_COF4 */
+#define _PROTIMER_SEQIEN_COF4_MASK 0x100000UL /**< Bit mask for PROTIMER_COF4 */
+#define _PROTIMER_SEQIEN_COF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_COF4_DEFAULT (_PROTIMER_SEQIEN_COF4_DEFAULT << 20) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_COF5 (0x1UL << 21) /**< COF5 Interrupt Enable */
+#define _PROTIMER_SEQIEN_COF5_SHIFT 21 /**< Shift value for PROTIMER_COF5 */
+#define _PROTIMER_SEQIEN_COF5_MASK 0x200000UL /**< Bit mask for PROTIMER_COF5 */
+#define _PROTIMER_SEQIEN_COF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_COF5_DEFAULT (_PROTIMER_SEQIEN_COF5_DEFAULT << 21) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_COF6 (0x1UL << 22) /**< COF6 Interrupt Enable */
+#define _PROTIMER_SEQIEN_COF6_SHIFT 22 /**< Shift value for PROTIMER_COF6 */
+#define _PROTIMER_SEQIEN_COF6_MASK 0x400000UL /**< Bit mask for PROTIMER_COF6 */
+#define _PROTIMER_SEQIEN_COF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_COF6_DEFAULT (_PROTIMER_SEQIEN_COF6_DEFAULT << 22) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_COF7 (0x1UL << 23) /**< COF7 Interrupt Enable */
+#define _PROTIMER_SEQIEN_COF7_SHIFT 23 /**< Shift value for PROTIMER_COF7 */
+#define _PROTIMER_SEQIEN_COF7_MASK 0x800000UL /**< Bit mask for PROTIMER_COF7 */
+#define _PROTIMER_SEQIEN_COF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_COF7_DEFAULT (_PROTIMER_SEQIEN_COF7_DEFAULT << 23) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_LBTSUCCESS (0x1UL << 24) /**< LBTSUCCESS Interrupt Enable */
+#define _PROTIMER_SEQIEN_LBTSUCCESS_SHIFT 24 /**< Shift value for PROTIMER_LBTSUCCESS */
+#define _PROTIMER_SEQIEN_LBTSUCCESS_MASK 0x1000000UL /**< Bit mask for PROTIMER_LBTSUCCESS */
+#define _PROTIMER_SEQIEN_LBTSUCCESS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_LBTSUCCESS_DEFAULT (_PROTIMER_SEQIEN_LBTSUCCESS_DEFAULT << 24) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_LBTFAILURE (0x1UL << 25) /**< LBTFAILURE Interrupt Enable */
+#define _PROTIMER_SEQIEN_LBTFAILURE_SHIFT 25 /**< Shift value for PROTIMER_LBTFAILURE */
+#define _PROTIMER_SEQIEN_LBTFAILURE_MASK 0x2000000UL /**< Bit mask for PROTIMER_LBTFAILURE */
+#define _PROTIMER_SEQIEN_LBTFAILURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_LBTFAILURE_DEFAULT (_PROTIMER_SEQIEN_LBTFAILURE_DEFAULT << 25) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_LBTPAUSED (0x1UL << 26) /**< LBTPAUSED Interrupt Enable */
+#define _PROTIMER_SEQIEN_LBTPAUSED_SHIFT 26 /**< Shift value for PROTIMER_LBTPAUSED */
+#define _PROTIMER_SEQIEN_LBTPAUSED_MASK 0x4000000UL /**< Bit mask for PROTIMER_LBTPAUSED */
+#define _PROTIMER_SEQIEN_LBTPAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_LBTPAUSED_DEFAULT (_PROTIMER_SEQIEN_LBTPAUSED_DEFAULT << 26) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_LBTRETRY (0x1UL << 27) /**< LBTRETRY Interrupt Enable */
+#define _PROTIMER_SEQIEN_LBTRETRY_SHIFT 27 /**< Shift value for PROTIMER_LBTRETRY */
+#define _PROTIMER_SEQIEN_LBTRETRY_MASK 0x8000000UL /**< Bit mask for PROTIMER_LBTRETRY */
+#define _PROTIMER_SEQIEN_LBTRETRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_LBTRETRY_DEFAULT (_PROTIMER_SEQIEN_LBTRETRY_DEFAULT << 27) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_RTCCSYNCHED (0x1UL << 28) /**< RTCCSYNCHED Interrupt Enable */
+#define _PROTIMER_SEQIEN_RTCCSYNCHED_SHIFT 28 /**< Shift value for PROTIMER_RTCCSYNCHED */
+#define _PROTIMER_SEQIEN_RTCCSYNCHED_MASK 0x10000000UL /**< Bit mask for PROTIMER_RTCCSYNCHED */
+#define _PROTIMER_SEQIEN_RTCCSYNCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_RTCCSYNCHED_DEFAULT (_PROTIMER_SEQIEN_RTCCSYNCHED_DEFAULT << 28) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_TOUT0MATCHLBT (0x1UL << 29) /**< TOUT0MATCHLBT Interrupt Enable */
+#define _PROTIMER_SEQIEN_TOUT0MATCHLBT_SHIFT 29 /**< Shift value for PROTIMER_TOUT0MATCHLBT */
+#define _PROTIMER_SEQIEN_TOUT0MATCHLBT_MASK 0x20000000UL /**< Bit mask for PROTIMER_TOUT0MATCHLBT */
+#define _PROTIMER_SEQIEN_TOUT0MATCHLBT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_SEQIEN */
+#define PROTIMER_SEQIEN_TOUT0MATCHLBT_DEFAULT (_PROTIMER_SEQIEN_TOUT0MATCHLBT_DEFAULT << 29) /**< Shifted mode DEFAULT for PROTIMER_SEQIEN */
+
+/* Bit fields for PROTIMER CC_CTRL */
+#define _PROTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_MASK 0x07E07F7FUL /**< Mask for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_ENABLE (0x1UL << 0) /**< Channel Enable */
+#define _PROTIMER_CC_CTRL_ENABLE_SHIFT 0 /**< Shift value for PROTIMER_ENABLE */
+#define _PROTIMER_CC_CTRL_ENABLE_MASK 0x1UL /**< Bit mask for PROTIMER_ENABLE */
+#define _PROTIMER_CC_CTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_ENABLE_DEFAULT (_PROTIMER_CC_CTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_CCMODE (0x1UL << 1) /**< Compare/Capture mode */
+#define _PROTIMER_CC_CTRL_CCMODE_SHIFT 1 /**< Shift value for PROTIMER_CCMODE */
+#define _PROTIMER_CC_CTRL_CCMODE_MASK 0x2UL /**< Bit mask for PROTIMER_CCMODE */
+#define _PROTIMER_CC_CTRL_CCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_CCMODE_COMPARE 0x00000000UL /**< Mode COMPARE for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_CCMODE_CAPTURE 0x00000001UL /**< Mode CAPTURE for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_CCMODE_DEFAULT (_PROTIMER_CC_CTRL_CCMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_CCMODE_COMPARE (_PROTIMER_CC_CTRL_CCMODE_COMPARE << 1) /**< Shifted mode COMPARE for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_CCMODE_CAPTURE (_PROTIMER_CC_CTRL_CCMODE_CAPTURE << 1) /**< Shifted mode CAPTURE for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_PREMATCHEN (0x1UL << 2) /**< Enable PRECNT matching */
+#define _PROTIMER_CC_CTRL_PREMATCHEN_SHIFT 2 /**< Shift value for PROTIMER_PREMATCHEN */
+#define _PROTIMER_CC_CTRL_PREMATCHEN_MASK 0x4UL /**< Bit mask for PROTIMER_PREMATCHEN */
+#define _PROTIMER_CC_CTRL_PREMATCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_PREMATCHEN_DEFAULT (_PROTIMER_CC_CTRL_PREMATCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_BASEMATCHEN (0x1UL << 3) /**< Enable BASECNT matching */
+#define _PROTIMER_CC_CTRL_BASEMATCHEN_SHIFT 3 /**< Shift value for PROTIMER_BASEMATCHEN */
+#define _PROTIMER_CC_CTRL_BASEMATCHEN_MASK 0x8UL /**< Bit mask for PROTIMER_BASEMATCHEN */
+#define _PROTIMER_CC_CTRL_BASEMATCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_BASEMATCHEN_DEFAULT (_PROTIMER_CC_CTRL_BASEMATCHEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_WRAPMATCHEN (0x1UL << 4) /**< Enable WRAPCNT matching */
+#define _PROTIMER_CC_CTRL_WRAPMATCHEN_SHIFT 4 /**< Shift value for PROTIMER_WRAPMATCHEN */
+#define _PROTIMER_CC_CTRL_WRAPMATCHEN_MASK 0x10UL /**< Bit mask for PROTIMER_WRAPMATCHEN */
+#define _PROTIMER_CC_CTRL_WRAPMATCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_WRAPMATCHEN_DEFAULT (_PROTIMER_CC_CTRL_WRAPMATCHEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_OIST (0x1UL << 5) /**< Output Initial State */
+#define _PROTIMER_CC_CTRL_OIST_SHIFT 5 /**< Shift value for PROTIMER_OIST */
+#define _PROTIMER_CC_CTRL_OIST_MASK 0x20UL /**< Bit mask for PROTIMER_OIST */
+#define _PROTIMER_CC_CTRL_OIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_OIST_DEFAULT (_PROTIMER_CC_CTRL_OIST_DEFAULT << 5) /**< Shifted mode DEFAULT for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_OUTINV (0x1UL << 6) /**< Output Invert */
+#define _PROTIMER_CC_CTRL_OUTINV_SHIFT 6 /**< Shift value for PROTIMER_OUTINV */
+#define _PROTIMER_CC_CTRL_OUTINV_MASK 0x40UL /**< Bit mask for PROTIMER_OUTINV */
+#define _PROTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_OUTINV_DEFAULT (_PROTIMER_CC_CTRL_OUTINV_DEFAULT << 6) /**< Shifted mode DEFAULT for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_MOA_SHIFT 8 /**< Shift value for PROTIMER_MOA */
+#define _PROTIMER_CC_CTRL_MOA_MASK 0x300UL /**< Bit mask for PROTIMER_MOA */
+#define _PROTIMER_CC_CTRL_MOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_MOA_DISABLED 0x00000000UL /**< Mode DISABLED for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_MOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_MOA_CLEAR 0x00000002UL /**< Mode CLEAR for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_MOA_SET 0x00000003UL /**< Mode SET for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_MOA_DEFAULT (_PROTIMER_CC_CTRL_MOA_DEFAULT << 8) /**< Shifted mode DEFAULT for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_MOA_DISABLED (_PROTIMER_CC_CTRL_MOA_DISABLED << 8) /**< Shifted mode DISABLED for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_MOA_TOGGLE (_PROTIMER_CC_CTRL_MOA_TOGGLE << 8) /**< Shifted mode TOGGLE for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_MOA_CLEAR (_PROTIMER_CC_CTRL_MOA_CLEAR << 8) /**< Shifted mode CLEAR for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_MOA_SET (_PROTIMER_CC_CTRL_MOA_SET << 8) /**< Shifted mode SET for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_OFOA_SHIFT 10 /**< Shift value for PROTIMER_OFOA */
+#define _PROTIMER_CC_CTRL_OFOA_MASK 0xC00UL /**< Bit mask for PROTIMER_OFOA */
+#define _PROTIMER_CC_CTRL_OFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_OFOA_DISABLED 0x00000000UL /**< Mode DISABLED for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_OFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_OFOA_CLEAR 0x00000002UL /**< Mode CLEAR for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_OFOA_SET 0x00000003UL /**< Mode SET for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_OFOA_DEFAULT (_PROTIMER_CC_CTRL_OFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_OFOA_DISABLED (_PROTIMER_CC_CTRL_OFOA_DISABLED << 10) /**< Shifted mode DISABLED for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_OFOA_TOGGLE (_PROTIMER_CC_CTRL_OFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_OFOA_CLEAR (_PROTIMER_CC_CTRL_OFOA_CLEAR << 10) /**< Shifted mode CLEAR for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_OFOA_SET (_PROTIMER_CC_CTRL_OFOA_SET << 10) /**< Shifted mode SET for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_OFSEL_SHIFT 12 /**< Shift value for PROTIMER_OFSEL */
+#define _PROTIMER_CC_CTRL_OFSEL_MASK 0x3000UL /**< Bit mask for PROTIMER_OFSEL */
+#define _PROTIMER_CC_CTRL_OFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_OFSEL_PRECNT 0x00000000UL /**< Mode PRECNT for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_OFSEL_BASECNT 0x00000001UL /**< Mode BASECNT for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_OFSEL_WRAPCNT 0x00000002UL /**< Mode WRAPCNT for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_OFSEL_DISABLED 0x00000003UL /**< Mode DISABLED for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_OFSEL_DEFAULT (_PROTIMER_CC_CTRL_OFSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_OFSEL_PRECNT (_PROTIMER_CC_CTRL_OFSEL_PRECNT << 12) /**< Shifted mode PRECNT for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_OFSEL_BASECNT (_PROTIMER_CC_CTRL_OFSEL_BASECNT << 12) /**< Shifted mode BASECNT for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_OFSEL_WRAPCNT (_PROTIMER_CC_CTRL_OFSEL_WRAPCNT << 12) /**< Shifted mode WRAPCNT for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_OFSEL_DISABLED (_PROTIMER_CC_CTRL_OFSEL_DISABLED << 12) /**< Shifted mode DISABLED for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_PRSCONF (0x1UL << 14) /**< PRS Configuration */
+#define _PROTIMER_CC_CTRL_PRSCONF_SHIFT 14 /**< Shift value for PROTIMER_PRSCONF */
+#define _PROTIMER_CC_CTRL_PRSCONF_MASK 0x4000UL /**< Bit mask for PROTIMER_PRSCONF */
+#define _PROTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_PRSCONF_DEFAULT (_PROTIMER_CC_CTRL_PRSCONF_DEFAULT << 14) /**< Shifted mode DEFAULT for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_PRSCONF_PULSE (_PROTIMER_CC_CTRL_PRSCONF_PULSE << 14) /**< Shifted mode PULSE for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_PRSCONF_LEVEL (_PROTIMER_CC_CTRL_PRSCONF_LEVEL << 14) /**< Shifted mode LEVEL for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_INSEL_SHIFT 21 /**< Shift value for PROTIMER_INSEL */
+#define _PROTIMER_CC_CTRL_INSEL_MASK 0x1E00000UL /**< Bit mask for PROTIMER_INSEL */
+#define _PROTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_INSEL_PRS 0x00000000UL /**< Mode PRS for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_INSEL_TXDONE 0x00000001UL /**< Mode TXDONE for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_INSEL_RXDONE 0x00000002UL /**< Mode RXDONE for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_INSEL_TXORRXDONE 0x00000003UL /**< Mode TXORRXDONE for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_INSEL_FRAMEDET0 0x00000004UL /**< Mode FRAMEDET0 for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_INSEL_FRAMEDET1 0x00000005UL /**< Mode FRAMEDET1 for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_INSEL_FDET0OR1 0x00000006UL /**< Mode FDET0OR1 for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_INSEL_MODSYNCSENT 0x00000007UL /**< Mode MODSYNCSENT for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_INSEL_RXEOF 0x00000008UL /**< Mode RXEOF for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_INSEL_PRORTC0 0x00000009UL /**< Mode PRORTC0 for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_INSEL_PRORTC1 0x0000000AUL /**< Mode PRORTC1 for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_INSEL_DEFAULT (_PROTIMER_CC_CTRL_INSEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_INSEL_PRS (_PROTIMER_CC_CTRL_INSEL_PRS << 21) /**< Shifted mode PRS for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_INSEL_TXDONE (_PROTIMER_CC_CTRL_INSEL_TXDONE << 21) /**< Shifted mode TXDONE for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_INSEL_RXDONE (_PROTIMER_CC_CTRL_INSEL_RXDONE << 21) /**< Shifted mode RXDONE for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_INSEL_TXORRXDONE (_PROTIMER_CC_CTRL_INSEL_TXORRXDONE << 21) /**< Shifted mode TXORRXDONE for PROTIMER_CC_CTRL*/
+#define PROTIMER_CC_CTRL_INSEL_FRAMEDET0 (_PROTIMER_CC_CTRL_INSEL_FRAMEDET0 << 21) /**< Shifted mode FRAMEDET0 for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_INSEL_FRAMEDET1 (_PROTIMER_CC_CTRL_INSEL_FRAMEDET1 << 21) /**< Shifted mode FRAMEDET1 for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_INSEL_FDET0OR1 (_PROTIMER_CC_CTRL_INSEL_FDET0OR1 << 21) /**< Shifted mode FDET0OR1 for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_INSEL_MODSYNCSENT (_PROTIMER_CC_CTRL_INSEL_MODSYNCSENT << 21) /**< Shifted mode MODSYNCSENT for PROTIMER_CC_CTRL*/
+#define PROTIMER_CC_CTRL_INSEL_RXEOF (_PROTIMER_CC_CTRL_INSEL_RXEOF << 21) /**< Shifted mode RXEOF for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_INSEL_PRORTC0 (_PROTIMER_CC_CTRL_INSEL_PRORTC0 << 21) /**< Shifted mode PRORTC0 for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_INSEL_PRORTC1 (_PROTIMER_CC_CTRL_INSEL_PRORTC1 << 21) /**< Shifted mode PRORTC1 for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_ICEDGE_SHIFT 25 /**< Shift value for PROTIMER_ICEDGE */
+#define _PROTIMER_CC_CTRL_ICEDGE_MASK 0x6000000UL /**< Bit mask for PROTIMER_ICEDGE */
+#define _PROTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for PROTIMER_CC_CTRL */
+#define _PROTIMER_CC_CTRL_ICEDGE_DISABLED 0x00000003UL /**< Mode DISABLED for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_ICEDGE_DEFAULT (_PROTIMER_CC_CTRL_ICEDGE_DEFAULT << 25) /**< Shifted mode DEFAULT for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_ICEDGE_RISING (_PROTIMER_CC_CTRL_ICEDGE_RISING << 25) /**< Shifted mode RISING for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_ICEDGE_FALLING (_PROTIMER_CC_CTRL_ICEDGE_FALLING << 25) /**< Shifted mode FALLING for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_ICEDGE_BOTH (_PROTIMER_CC_CTRL_ICEDGE_BOTH << 25) /**< Shifted mode BOTH for PROTIMER_CC_CTRL */
+#define PROTIMER_CC_CTRL_ICEDGE_DISABLED (_PROTIMER_CC_CTRL_ICEDGE_DISABLED << 25) /**< Shifted mode DISABLED for PROTIMER_CC_CTRL */
+
+/* Bit fields for PROTIMER CC_PRE */
+#define _PROTIMER_CC_PRE_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_CC_PRE */
+#define _PROTIMER_CC_PRE_MASK 0x0000FFFFUL /**< Mask for PROTIMER_CC_PRE */
+#define _PROTIMER_CC_PRE_PRE_SHIFT 0 /**< Shift value for PROTIMER_PRE */
+#define _PROTIMER_CC_PRE_PRE_MASK 0xFFFFUL /**< Bit mask for PROTIMER_PRE */
+#define _PROTIMER_CC_PRE_PRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_PRE */
+#define PROTIMER_CC_PRE_PRE_DEFAULT (_PROTIMER_CC_PRE_PRE_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_CC_PRE */
+
+/* Bit fields for PROTIMER CC_BASE */
+#define _PROTIMER_CC_BASE_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_CC_BASE */
+#define _PROTIMER_CC_BASE_MASK 0x0000FFFFUL /**< Mask for PROTIMER_CC_BASE */
+#define _PROTIMER_CC_BASE_BASE_SHIFT 0 /**< Shift value for PROTIMER_BASE */
+#define _PROTIMER_CC_BASE_BASE_MASK 0xFFFFUL /**< Bit mask for PROTIMER_BASE */
+#define _PROTIMER_CC_BASE_BASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_BASE */
+#define PROTIMER_CC_BASE_BASE_DEFAULT (_PROTIMER_CC_BASE_BASE_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_CC_BASE */
+
+/* Bit fields for PROTIMER CC_WRAP */
+#define _PROTIMER_CC_WRAP_RESETVALUE 0x00000000UL /**< Default value for PROTIMER_CC_WRAP */
+#define _PROTIMER_CC_WRAP_MASK 0xFFFFFFFFUL /**< Mask for PROTIMER_CC_WRAP */
+#define _PROTIMER_CC_WRAP_WRAP_SHIFT 0 /**< Shift value for PROTIMER_WRAP */
+#define _PROTIMER_CC_WRAP_WRAP_MASK 0xFFFFFFFFUL /**< Bit mask for PROTIMER_WRAP */
+#define _PROTIMER_CC_WRAP_WRAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PROTIMER_CC_WRAP */
+#define PROTIMER_CC_WRAP_WRAP_DEFAULT (_PROTIMER_CC_WRAP_WRAP_DEFAULT << 0) /**< Shifted mode DEFAULT for PROTIMER_CC_WRAP */
+
+/** @} End of group EFR32MG24_PROTIMER_BitFields */
+/** @} End of group EFR32MG24_PROTIMER */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_PROTIMER_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_prs.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_prs.h
new file mode 100644
index 00000000..725b7381
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_prs.h
@@ -0,0 +1,1621 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 PRS register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_PRS_H
+#define EFR32MG24_PRS_H
+#define PRS_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_PRS PRS
+ * @{
+ * @brief EFR32MG24 PRS Register Declaration.
+ *****************************************************************************/
+
+/** PRS ASYNC_CH Register Group Declaration. */
+typedef struct {
+ __IOM uint32_t CTRL; /**< Async Channel Control Register */
+} PRS_ASYNC_CH_TypeDef;
+
+/** PRS SYNC_CH Register Group Declaration. */
+typedef struct {
+ __IOM uint32_t CTRL; /**< Sync Channel Control Register */
+} PRS_SYNC_CH_TypeDef;
+
+/** PRS Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< PRS IPVERSION */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+ __IOM uint32_t ASYNC_SWPULSE; /**< Software Pulse Register */
+ __IOM uint32_t ASYNC_SWLEVEL; /**< Software Level Register */
+ __IM uint32_t ASYNC_PEEK; /**< Async Channel Values */
+ __IM uint32_t SYNC_PEEK; /**< Sync Channel Values */
+ PRS_ASYNC_CH_TypeDef ASYNC_CH[16U]; /**< Async Channel registers */
+ PRS_SYNC_CH_TypeDef SYNC_CH[4U]; /**< Sync Channel registers */
+ __IOM uint32_t CONSUMER_CMU_CALDN; /**< CALDN consumer register */
+ __IOM uint32_t CONSUMER_CMU_CALUP; /**< CALUP Consumer register */
+ __IOM uint32_t CONSUMER_EUSART0_CLK; /**< CLK consumer register */
+ __IOM uint32_t CONSUMER_EUSART0_RX; /**< RX Consumer register */
+ __IOM uint32_t CONSUMER_EUSART0_TRIGGER; /**< TRIGGER Consumer register */
+ __IOM uint32_t CONSUMER_EUSART1_CLK; /**< CLK consumer register */
+ __IOM uint32_t CONSUMER_EUSART1_RX; /**< RX Consumer register */
+ __IOM uint32_t CONSUMER_EUSART1_TRIGGER; /**< TRIGGER Consumer register */
+ uint32_t RESERVED1[1U]; /**< Reserved for future use */
+ __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER; /**< SCAN consumer register */
+ __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER; /**< SINGLE Consumer register */
+ __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0; /**< DMAREQ0 consumer register */
+ __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1; /**< DMAREQ1 Consumer register */
+ __IOM uint32_t CONSUMER_LETIMER0_CLEAR; /**< CLEAR consumer register */
+ __IOM uint32_t CONSUMER_LETIMER0_START; /**< START Consumer register */
+ __IOM uint32_t CONSUMER_LETIMER0_STOP; /**< STOP Consumer register */
+ __IOM uint32_t CONSUMER_MODEM_DIN; /**< DIN consumer register */
+ __IOM uint32_t CONSUMER_MODEM_PAEN; /**< PAEN Consumer register */
+ __IOM uint32_t CONSUMER_PCNT0_S0IN; /**< S0IN consumer register */
+ __IOM uint32_t CONSUMER_PCNT0_S1IN; /**< S1IN Consumer register */
+ uint32_t RESERVED2[11U]; /**< Reserved for future use */
+ __IOM uint32_t CONSUMER_RAC_CLR; /**< CLR consumer register */
+ __IOM uint32_t CONSUMER_RAC_CTIIN0; /**< CTI Consumer register */
+ __IOM uint32_t CONSUMER_RAC_CTIIN1; /**< CTI Consumer register */
+ __IOM uint32_t CONSUMER_RAC_CTIIN2; /**< CTI Consumer register */
+ __IOM uint32_t CONSUMER_RAC_CTIIN3; /**< CTI Consumer register */
+ __IOM uint32_t CONSUMER_RAC_FORCETX; /**< FORCETX Consumer register */
+ __IOM uint32_t CONSUMER_RAC_RXDIS; /**< RXDIS Consumer register */
+ __IOM uint32_t CONSUMER_RAC_RXEN; /**< RXEN Consumer register */
+ __IOM uint32_t CONSUMER_RAC_TXEN; /**< TXEN Consumer register */
+ __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25; /**< TAMPERSRC25 consumer register */
+ __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26; /**< TAMPERSRC26 Consumer register */
+ __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27; /**< TAMPERSRC27 Consumer register */
+ __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28; /**< TAMPERSRC28 Consumer register */
+ __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29; /**< TAMPERSRC29 Consumer register */
+ __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30; /**< TAMPERSRC30 Consumer register */
+ __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31; /**< TAMPERSRC31 Consumer register */
+ __IOM uint32_t CONSUMER_SYSRTC0_IN0; /**< IN0 consumer register */
+ __IOM uint32_t CONSUMER_SYSRTC0_IN1; /**< IN1 Consumer register */
+ __IOM uint32_t CONSUMER_HFXO0_OSCREQ; /**< OSCREQ consumer register */
+ __IOM uint32_t CONSUMER_HFXO0_TIMEOUT; /**< TIMEOUT Consumer register */
+ __IOM uint32_t CONSUMER_CORE_CTIIN0; /**< CTI consumer register */
+ __IOM uint32_t CONSUMER_CORE_CTIIN1; /**< CTI Consumer register */
+ __IOM uint32_t CONSUMER_CORE_CTIIN2; /**< CTI Consumer register */
+ __IOM uint32_t CONSUMER_CORE_CTIIN3; /**< CTI Consumer register */
+ __IOM uint32_t CONSUMER_CORE_M33RXEV; /**< M33 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER0_CC0; /**< CC0 consumer register */
+ __IOM uint32_t CONSUMER_TIMER0_CC1; /**< CC1 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER0_CC2; /**< CC2 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER0_DTI; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER0_DTIFS1; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER0_DTIFS2; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER1_CC0; /**< CC0 consumer register */
+ __IOM uint32_t CONSUMER_TIMER1_CC1; /**< CC1 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER1_CC2; /**< CC2 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER1_DTI; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER1_DTIFS1; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER1_DTIFS2; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER2_CC0; /**< CC0 consumer register */
+ __IOM uint32_t CONSUMER_TIMER2_CC1; /**< CC1 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER2_CC2; /**< CC2 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER2_DTI; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER2_DTIFS1; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER2_DTIFS2; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER3_CC0; /**< CC0 consumer register */
+ __IOM uint32_t CONSUMER_TIMER3_CC1; /**< CC1 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER3_CC2; /**< CC2 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER3_DTI; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER3_DTIFS1; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER3_DTIFS2; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER4_CC0; /**< CC0 consumer register */
+ __IOM uint32_t CONSUMER_TIMER4_CC1; /**< CC1 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER4_CC2; /**< CC2 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER4_DTI; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER4_DTIFS1; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER4_DTIFS2; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_USART0_CLK; /**< CLK consumer register */
+ __IOM uint32_t CONSUMER_USART0_IR; /**< IR Consumer register */
+ __IOM uint32_t CONSUMER_USART0_RX; /**< RX Consumer register */
+ __IOM uint32_t CONSUMER_USART0_TRIGGER; /**< TRIGGER Consumer register */
+ uint32_t RESERVED3[3U]; /**< Reserved for future use */
+ __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0; /**< ASYNCTRIG consumer register */
+ __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1; /**< ASYNCTRIG Consumer register */
+ __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0; /**< SYNCTRIG Consumer register */
+ __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1; /**< SYNCTRIG Consumer register */
+ __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH0; /**< ASYNCTRIG consumer register */
+ __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH1; /**< ASYNCTRIG Consumer register */
+ __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH0; /**< SYNCTRIG Consumer register */
+ __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH1; /**< SYNCTRIG Consumer register */
+ __IOM uint32_t CONSUMER_WDOG0_SRC0; /**< SRC0 consumer register */
+ __IOM uint32_t CONSUMER_WDOG0_SRC1; /**< SRC1 Consumer register */
+ __IOM uint32_t CONSUMER_WDOG1_SRC0; /**< SRC0 consumer register */
+ __IOM uint32_t CONSUMER_WDOG1_SRC1; /**< SRC1 Consumer register */
+ uint32_t RESERVED4[1U]; /**< Reserved for future use */
+ uint32_t RESERVED5[892U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< PRS IPVERSION */
+ uint32_t RESERVED6[1U]; /**< Reserved for future use */
+ __IOM uint32_t ASYNC_SWPULSE_SET; /**< Software Pulse Register */
+ __IOM uint32_t ASYNC_SWLEVEL_SET; /**< Software Level Register */
+ __IM uint32_t ASYNC_PEEK_SET; /**< Async Channel Values */
+ __IM uint32_t SYNC_PEEK_SET; /**< Sync Channel Values */
+ PRS_ASYNC_CH_TypeDef ASYNC_CH_SET[16U]; /**< Async Channel registers */
+ PRS_SYNC_CH_TypeDef SYNC_CH_SET[4U]; /**< Sync Channel registers */
+ __IOM uint32_t CONSUMER_CMU_CALDN_SET; /**< CALDN consumer register */
+ __IOM uint32_t CONSUMER_CMU_CALUP_SET; /**< CALUP Consumer register */
+ __IOM uint32_t CONSUMER_EUSART0_CLK_SET; /**< CLK consumer register */
+ __IOM uint32_t CONSUMER_EUSART0_RX_SET; /**< RX Consumer register */
+ __IOM uint32_t CONSUMER_EUSART0_TRIGGER_SET; /**< TRIGGER Consumer register */
+ __IOM uint32_t CONSUMER_EUSART1_CLK_SET; /**< CLK consumer register */
+ __IOM uint32_t CONSUMER_EUSART1_RX_SET; /**< RX Consumer register */
+ __IOM uint32_t CONSUMER_EUSART1_TRIGGER_SET; /**< TRIGGER Consumer register */
+ uint32_t RESERVED7[1U]; /**< Reserved for future use */
+ __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_SET; /**< SCAN consumer register */
+ __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_SET; /**< SINGLE Consumer register */
+ __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_SET; /**< DMAREQ0 consumer register */
+ __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_SET; /**< DMAREQ1 Consumer register */
+ __IOM uint32_t CONSUMER_LETIMER0_CLEAR_SET; /**< CLEAR consumer register */
+ __IOM uint32_t CONSUMER_LETIMER0_START_SET; /**< START Consumer register */
+ __IOM uint32_t CONSUMER_LETIMER0_STOP_SET; /**< STOP Consumer register */
+ __IOM uint32_t CONSUMER_MODEM_DIN_SET; /**< DIN consumer register */
+ __IOM uint32_t CONSUMER_MODEM_PAEN_SET; /**< PAEN Consumer register */
+ __IOM uint32_t CONSUMER_PCNT0_S0IN_SET; /**< S0IN consumer register */
+ __IOM uint32_t CONSUMER_PCNT0_S1IN_SET; /**< S1IN Consumer register */
+ uint32_t RESERVED8[11U]; /**< Reserved for future use */
+ __IOM uint32_t CONSUMER_RAC_CLR_SET; /**< CLR consumer register */
+ __IOM uint32_t CONSUMER_RAC_CTIIN0_SET; /**< CTI Consumer register */
+ __IOM uint32_t CONSUMER_RAC_CTIIN1_SET; /**< CTI Consumer register */
+ __IOM uint32_t CONSUMER_RAC_CTIIN2_SET; /**< CTI Consumer register */
+ __IOM uint32_t CONSUMER_RAC_CTIIN3_SET; /**< CTI Consumer register */
+ __IOM uint32_t CONSUMER_RAC_FORCETX_SET; /**< FORCETX Consumer register */
+ __IOM uint32_t CONSUMER_RAC_RXDIS_SET; /**< RXDIS Consumer register */
+ __IOM uint32_t CONSUMER_RAC_RXEN_SET; /**< RXEN Consumer register */
+ __IOM uint32_t CONSUMER_RAC_TXEN_SET; /**< TXEN Consumer register */
+ __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25_SET; /**< TAMPERSRC25 consumer register */
+ __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_SET; /**< TAMPERSRC26 Consumer register */
+ __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_SET; /**< TAMPERSRC27 Consumer register */
+ __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_SET; /**< TAMPERSRC28 Consumer register */
+ __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_SET; /**< TAMPERSRC29 Consumer register */
+ __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_SET; /**< TAMPERSRC30 Consumer register */
+ __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_SET; /**< TAMPERSRC31 Consumer register */
+ __IOM uint32_t CONSUMER_SYSRTC0_IN0_SET; /**< IN0 consumer register */
+ __IOM uint32_t CONSUMER_SYSRTC0_IN1_SET; /**< IN1 Consumer register */
+ __IOM uint32_t CONSUMER_HFXO0_OSCREQ_SET; /**< OSCREQ consumer register */
+ __IOM uint32_t CONSUMER_HFXO0_TIMEOUT_SET; /**< TIMEOUT Consumer register */
+ __IOM uint32_t CONSUMER_CORE_CTIIN0_SET; /**< CTI consumer register */
+ __IOM uint32_t CONSUMER_CORE_CTIIN1_SET; /**< CTI Consumer register */
+ __IOM uint32_t CONSUMER_CORE_CTIIN2_SET; /**< CTI Consumer register */
+ __IOM uint32_t CONSUMER_CORE_CTIIN3_SET; /**< CTI Consumer register */
+ __IOM uint32_t CONSUMER_CORE_M33RXEV_SET; /**< M33 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER0_CC0_SET; /**< CC0 consumer register */
+ __IOM uint32_t CONSUMER_TIMER0_CC1_SET; /**< CC1 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER0_CC2_SET; /**< CC2 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER0_DTI_SET; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER0_DTIFS1_SET; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER0_DTIFS2_SET; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER1_CC0_SET; /**< CC0 consumer register */
+ __IOM uint32_t CONSUMER_TIMER1_CC1_SET; /**< CC1 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER1_CC2_SET; /**< CC2 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER1_DTI_SET; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER1_DTIFS1_SET; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER1_DTIFS2_SET; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER2_CC0_SET; /**< CC0 consumer register */
+ __IOM uint32_t CONSUMER_TIMER2_CC1_SET; /**< CC1 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER2_CC2_SET; /**< CC2 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER2_DTI_SET; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER2_DTIFS1_SET; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER2_DTIFS2_SET; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER3_CC0_SET; /**< CC0 consumer register */
+ __IOM uint32_t CONSUMER_TIMER3_CC1_SET; /**< CC1 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER3_CC2_SET; /**< CC2 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER3_DTI_SET; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER3_DTIFS1_SET; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER3_DTIFS2_SET; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER4_CC0_SET; /**< CC0 consumer register */
+ __IOM uint32_t CONSUMER_TIMER4_CC1_SET; /**< CC1 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER4_CC2_SET; /**< CC2 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER4_DTI_SET; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER4_DTIFS1_SET; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER4_DTIFS2_SET; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_USART0_CLK_SET; /**< CLK consumer register */
+ __IOM uint32_t CONSUMER_USART0_IR_SET; /**< IR Consumer register */
+ __IOM uint32_t CONSUMER_USART0_RX_SET; /**< RX Consumer register */
+ __IOM uint32_t CONSUMER_USART0_TRIGGER_SET; /**< TRIGGER Consumer register */
+ uint32_t RESERVED9[3U]; /**< Reserved for future use */
+ __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0_SET; /**< ASYNCTRIG consumer register */
+ __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1_SET; /**< ASYNCTRIG Consumer register */
+ __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0_SET; /**< SYNCTRIG Consumer register */
+ __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1_SET; /**< SYNCTRIG Consumer register */
+ __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH0_SET; /**< ASYNCTRIG consumer register */
+ __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH1_SET; /**< ASYNCTRIG Consumer register */
+ __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH0_SET; /**< SYNCTRIG Consumer register */
+ __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH1_SET; /**< SYNCTRIG Consumer register */
+ __IOM uint32_t CONSUMER_WDOG0_SRC0_SET; /**< SRC0 consumer register */
+ __IOM uint32_t CONSUMER_WDOG0_SRC1_SET; /**< SRC1 Consumer register */
+ __IOM uint32_t CONSUMER_WDOG1_SRC0_SET; /**< SRC0 consumer register */
+ __IOM uint32_t CONSUMER_WDOG1_SRC1_SET; /**< SRC1 Consumer register */
+ uint32_t RESERVED10[1U]; /**< Reserved for future use */
+ uint32_t RESERVED11[892U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< PRS IPVERSION */
+ uint32_t RESERVED12[1U]; /**< Reserved for future use */
+ __IOM uint32_t ASYNC_SWPULSE_CLR; /**< Software Pulse Register */
+ __IOM uint32_t ASYNC_SWLEVEL_CLR; /**< Software Level Register */
+ __IM uint32_t ASYNC_PEEK_CLR; /**< Async Channel Values */
+ __IM uint32_t SYNC_PEEK_CLR; /**< Sync Channel Values */
+ PRS_ASYNC_CH_TypeDef ASYNC_CH_CLR[16U]; /**< Async Channel registers */
+ PRS_SYNC_CH_TypeDef SYNC_CH_CLR[4U]; /**< Sync Channel registers */
+ __IOM uint32_t CONSUMER_CMU_CALDN_CLR; /**< CALDN consumer register */
+ __IOM uint32_t CONSUMER_CMU_CALUP_CLR; /**< CALUP Consumer register */
+ __IOM uint32_t CONSUMER_EUSART0_CLK_CLR; /**< CLK consumer register */
+ __IOM uint32_t CONSUMER_EUSART0_RX_CLR; /**< RX Consumer register */
+ __IOM uint32_t CONSUMER_EUSART0_TRIGGER_CLR; /**< TRIGGER Consumer register */
+ __IOM uint32_t CONSUMER_EUSART1_CLK_CLR; /**< CLK consumer register */
+ __IOM uint32_t CONSUMER_EUSART1_RX_CLR; /**< RX Consumer register */
+ __IOM uint32_t CONSUMER_EUSART1_TRIGGER_CLR; /**< TRIGGER Consumer register */
+ uint32_t RESERVED13[1U]; /**< Reserved for future use */
+ __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_CLR; /**< SCAN consumer register */
+ __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_CLR; /**< SINGLE Consumer register */
+ __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_CLR; /**< DMAREQ0 consumer register */
+ __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_CLR; /**< DMAREQ1 Consumer register */
+ __IOM uint32_t CONSUMER_LETIMER0_CLEAR_CLR; /**< CLEAR consumer register */
+ __IOM uint32_t CONSUMER_LETIMER0_START_CLR; /**< START Consumer register */
+ __IOM uint32_t CONSUMER_LETIMER0_STOP_CLR; /**< STOP Consumer register */
+ __IOM uint32_t CONSUMER_MODEM_DIN_CLR; /**< DIN consumer register */
+ __IOM uint32_t CONSUMER_MODEM_PAEN_CLR; /**< PAEN Consumer register */
+ __IOM uint32_t CONSUMER_PCNT0_S0IN_CLR; /**< S0IN consumer register */
+ __IOM uint32_t CONSUMER_PCNT0_S1IN_CLR; /**< S1IN Consumer register */
+ uint32_t RESERVED14[11U]; /**< Reserved for future use */
+ __IOM uint32_t CONSUMER_RAC_CLR_CLR; /**< CLR consumer register */
+ __IOM uint32_t CONSUMER_RAC_CTIIN0_CLR; /**< CTI Consumer register */
+ __IOM uint32_t CONSUMER_RAC_CTIIN1_CLR; /**< CTI Consumer register */
+ __IOM uint32_t CONSUMER_RAC_CTIIN2_CLR; /**< CTI Consumer register */
+ __IOM uint32_t CONSUMER_RAC_CTIIN3_CLR; /**< CTI Consumer register */
+ __IOM uint32_t CONSUMER_RAC_FORCETX_CLR; /**< FORCETX Consumer register */
+ __IOM uint32_t CONSUMER_RAC_RXDIS_CLR; /**< RXDIS Consumer register */
+ __IOM uint32_t CONSUMER_RAC_RXEN_CLR; /**< RXEN Consumer register */
+ __IOM uint32_t CONSUMER_RAC_TXEN_CLR; /**< TXEN Consumer register */
+ __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25_CLR; /**< TAMPERSRC25 consumer register */
+ __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_CLR; /**< TAMPERSRC26 Consumer register */
+ __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_CLR; /**< TAMPERSRC27 Consumer register */
+ __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_CLR; /**< TAMPERSRC28 Consumer register */
+ __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_CLR; /**< TAMPERSRC29 Consumer register */
+ __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_CLR; /**< TAMPERSRC30 Consumer register */
+ __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_CLR; /**< TAMPERSRC31 Consumer register */
+ __IOM uint32_t CONSUMER_SYSRTC0_IN0_CLR; /**< IN0 consumer register */
+ __IOM uint32_t CONSUMER_SYSRTC0_IN1_CLR; /**< IN1 Consumer register */
+ __IOM uint32_t CONSUMER_HFXO0_OSCREQ_CLR; /**< OSCREQ consumer register */
+ __IOM uint32_t CONSUMER_HFXO0_TIMEOUT_CLR; /**< TIMEOUT Consumer register */
+ __IOM uint32_t CONSUMER_CORE_CTIIN0_CLR; /**< CTI consumer register */
+ __IOM uint32_t CONSUMER_CORE_CTIIN1_CLR; /**< CTI Consumer register */
+ __IOM uint32_t CONSUMER_CORE_CTIIN2_CLR; /**< CTI Consumer register */
+ __IOM uint32_t CONSUMER_CORE_CTIIN3_CLR; /**< CTI Consumer register */
+ __IOM uint32_t CONSUMER_CORE_M33RXEV_CLR; /**< M33 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER0_CC0_CLR; /**< CC0 consumer register */
+ __IOM uint32_t CONSUMER_TIMER0_CC1_CLR; /**< CC1 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER0_CC2_CLR; /**< CC2 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER0_DTI_CLR; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER0_DTIFS1_CLR; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER0_DTIFS2_CLR; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER1_CC0_CLR; /**< CC0 consumer register */
+ __IOM uint32_t CONSUMER_TIMER1_CC1_CLR; /**< CC1 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER1_CC2_CLR; /**< CC2 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER1_DTI_CLR; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER1_DTIFS1_CLR; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER1_DTIFS2_CLR; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER2_CC0_CLR; /**< CC0 consumer register */
+ __IOM uint32_t CONSUMER_TIMER2_CC1_CLR; /**< CC1 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER2_CC2_CLR; /**< CC2 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER2_DTI_CLR; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER2_DTIFS1_CLR; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER2_DTIFS2_CLR; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER3_CC0_CLR; /**< CC0 consumer register */
+ __IOM uint32_t CONSUMER_TIMER3_CC1_CLR; /**< CC1 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER3_CC2_CLR; /**< CC2 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER3_DTI_CLR; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER3_DTIFS1_CLR; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER3_DTIFS2_CLR; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER4_CC0_CLR; /**< CC0 consumer register */
+ __IOM uint32_t CONSUMER_TIMER4_CC1_CLR; /**< CC1 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER4_CC2_CLR; /**< CC2 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER4_DTI_CLR; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER4_DTIFS1_CLR; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER4_DTIFS2_CLR; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_USART0_CLK_CLR; /**< CLK consumer register */
+ __IOM uint32_t CONSUMER_USART0_IR_CLR; /**< IR Consumer register */
+ __IOM uint32_t CONSUMER_USART0_RX_CLR; /**< RX Consumer register */
+ __IOM uint32_t CONSUMER_USART0_TRIGGER_CLR; /**< TRIGGER Consumer register */
+ uint32_t RESERVED15[3U]; /**< Reserved for future use */
+ __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0_CLR; /**< ASYNCTRIG consumer register */
+ __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1_CLR; /**< ASYNCTRIG Consumer register */
+ __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0_CLR; /**< SYNCTRIG Consumer register */
+ __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1_CLR; /**< SYNCTRIG Consumer register */
+ __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH0_CLR; /**< ASYNCTRIG consumer register */
+ __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH1_CLR; /**< ASYNCTRIG Consumer register */
+ __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH0_CLR; /**< SYNCTRIG Consumer register */
+ __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH1_CLR; /**< SYNCTRIG Consumer register */
+ __IOM uint32_t CONSUMER_WDOG0_SRC0_CLR; /**< SRC0 consumer register */
+ __IOM uint32_t CONSUMER_WDOG0_SRC1_CLR; /**< SRC1 Consumer register */
+ __IOM uint32_t CONSUMER_WDOG1_SRC0_CLR; /**< SRC0 consumer register */
+ __IOM uint32_t CONSUMER_WDOG1_SRC1_CLR; /**< SRC1 Consumer register */
+ uint32_t RESERVED16[1U]; /**< Reserved for future use */
+ uint32_t RESERVED17[892U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< PRS IPVERSION */
+ uint32_t RESERVED18[1U]; /**< Reserved for future use */
+ __IOM uint32_t ASYNC_SWPULSE_TGL; /**< Software Pulse Register */
+ __IOM uint32_t ASYNC_SWLEVEL_TGL; /**< Software Level Register */
+ __IM uint32_t ASYNC_PEEK_TGL; /**< Async Channel Values */
+ __IM uint32_t SYNC_PEEK_TGL; /**< Sync Channel Values */
+ PRS_ASYNC_CH_TypeDef ASYNC_CH_TGL[16U]; /**< Async Channel registers */
+ PRS_SYNC_CH_TypeDef SYNC_CH_TGL[4U]; /**< Sync Channel registers */
+ __IOM uint32_t CONSUMER_CMU_CALDN_TGL; /**< CALDN consumer register */
+ __IOM uint32_t CONSUMER_CMU_CALUP_TGL; /**< CALUP Consumer register */
+ __IOM uint32_t CONSUMER_EUSART0_CLK_TGL; /**< CLK consumer register */
+ __IOM uint32_t CONSUMER_EUSART0_RX_TGL; /**< RX Consumer register */
+ __IOM uint32_t CONSUMER_EUSART0_TRIGGER_TGL; /**< TRIGGER Consumer register */
+ __IOM uint32_t CONSUMER_EUSART1_CLK_TGL; /**< CLK consumer register */
+ __IOM uint32_t CONSUMER_EUSART1_RX_TGL; /**< RX Consumer register */
+ __IOM uint32_t CONSUMER_EUSART1_TRIGGER_TGL; /**< TRIGGER Consumer register */
+ uint32_t RESERVED19[1U]; /**< Reserved for future use */
+ __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_TGL; /**< SCAN consumer register */
+ __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_TGL; /**< SINGLE Consumer register */
+ __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_TGL; /**< DMAREQ0 consumer register */
+ __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_TGL; /**< DMAREQ1 Consumer register */
+ __IOM uint32_t CONSUMER_LETIMER0_CLEAR_TGL; /**< CLEAR consumer register */
+ __IOM uint32_t CONSUMER_LETIMER0_START_TGL; /**< START Consumer register */
+ __IOM uint32_t CONSUMER_LETIMER0_STOP_TGL; /**< STOP Consumer register */
+ __IOM uint32_t CONSUMER_MODEM_DIN_TGL; /**< DIN consumer register */
+ __IOM uint32_t CONSUMER_MODEM_PAEN_TGL; /**< PAEN Consumer register */
+ __IOM uint32_t CONSUMER_PCNT0_S0IN_TGL; /**< S0IN consumer register */
+ __IOM uint32_t CONSUMER_PCNT0_S1IN_TGL; /**< S1IN Consumer register */
+ uint32_t RESERVED20[11U]; /**< Reserved for future use */
+ __IOM uint32_t CONSUMER_RAC_CLR_TGL; /**< CLR consumer register */
+ __IOM uint32_t CONSUMER_RAC_CTIIN0_TGL; /**< CTI Consumer register */
+ __IOM uint32_t CONSUMER_RAC_CTIIN1_TGL; /**< CTI Consumer register */
+ __IOM uint32_t CONSUMER_RAC_CTIIN2_TGL; /**< CTI Consumer register */
+ __IOM uint32_t CONSUMER_RAC_CTIIN3_TGL; /**< CTI Consumer register */
+ __IOM uint32_t CONSUMER_RAC_FORCETX_TGL; /**< FORCETX Consumer register */
+ __IOM uint32_t CONSUMER_RAC_RXDIS_TGL; /**< RXDIS Consumer register */
+ __IOM uint32_t CONSUMER_RAC_RXEN_TGL; /**< RXEN Consumer register */
+ __IOM uint32_t CONSUMER_RAC_TXEN_TGL; /**< TXEN Consumer register */
+ __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25_TGL; /**< TAMPERSRC25 consumer register */
+ __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_TGL; /**< TAMPERSRC26 Consumer register */
+ __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_TGL; /**< TAMPERSRC27 Consumer register */
+ __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_TGL; /**< TAMPERSRC28 Consumer register */
+ __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_TGL; /**< TAMPERSRC29 Consumer register */
+ __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_TGL; /**< TAMPERSRC30 Consumer register */
+ __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_TGL; /**< TAMPERSRC31 Consumer register */
+ __IOM uint32_t CONSUMER_SYSRTC0_IN0_TGL; /**< IN0 consumer register */
+ __IOM uint32_t CONSUMER_SYSRTC0_IN1_TGL; /**< IN1 Consumer register */
+ __IOM uint32_t CONSUMER_HFXO0_OSCREQ_TGL; /**< OSCREQ consumer register */
+ __IOM uint32_t CONSUMER_HFXO0_TIMEOUT_TGL; /**< TIMEOUT Consumer register */
+ __IOM uint32_t CONSUMER_CORE_CTIIN0_TGL; /**< CTI consumer register */
+ __IOM uint32_t CONSUMER_CORE_CTIIN1_TGL; /**< CTI Consumer register */
+ __IOM uint32_t CONSUMER_CORE_CTIIN2_TGL; /**< CTI Consumer register */
+ __IOM uint32_t CONSUMER_CORE_CTIIN3_TGL; /**< CTI Consumer register */
+ __IOM uint32_t CONSUMER_CORE_M33RXEV_TGL; /**< M33 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER0_CC0_TGL; /**< CC0 consumer register */
+ __IOM uint32_t CONSUMER_TIMER0_CC1_TGL; /**< CC1 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER0_CC2_TGL; /**< CC2 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER0_DTI_TGL; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER0_DTIFS1_TGL; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER0_DTIFS2_TGL; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER1_CC0_TGL; /**< CC0 consumer register */
+ __IOM uint32_t CONSUMER_TIMER1_CC1_TGL; /**< CC1 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER1_CC2_TGL; /**< CC2 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER1_DTI_TGL; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER1_DTIFS1_TGL; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER1_DTIFS2_TGL; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER2_CC0_TGL; /**< CC0 consumer register */
+ __IOM uint32_t CONSUMER_TIMER2_CC1_TGL; /**< CC1 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER2_CC2_TGL; /**< CC2 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER2_DTI_TGL; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER2_DTIFS1_TGL; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER2_DTIFS2_TGL; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER3_CC0_TGL; /**< CC0 consumer register */
+ __IOM uint32_t CONSUMER_TIMER3_CC1_TGL; /**< CC1 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER3_CC2_TGL; /**< CC2 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER3_DTI_TGL; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER3_DTIFS1_TGL; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER3_DTIFS2_TGL; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER4_CC0_TGL; /**< CC0 consumer register */
+ __IOM uint32_t CONSUMER_TIMER4_CC1_TGL; /**< CC1 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER4_CC2_TGL; /**< CC2 Consumer register */
+ __IOM uint32_t CONSUMER_TIMER4_DTI_TGL; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER4_DTIFS1_TGL; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_TIMER4_DTIFS2_TGL; /**< DTI Consumer register */
+ __IOM uint32_t CONSUMER_USART0_CLK_TGL; /**< CLK consumer register */
+ __IOM uint32_t CONSUMER_USART0_IR_TGL; /**< IR Consumer register */
+ __IOM uint32_t CONSUMER_USART0_RX_TGL; /**< RX Consumer register */
+ __IOM uint32_t CONSUMER_USART0_TRIGGER_TGL; /**< TRIGGER Consumer register */
+ uint32_t RESERVED21[3U]; /**< Reserved for future use */
+ __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0_TGL; /**< ASYNCTRIG consumer register */
+ __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1_TGL; /**< ASYNCTRIG Consumer register */
+ __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0_TGL; /**< SYNCTRIG Consumer register */
+ __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1_TGL; /**< SYNCTRIG Consumer register */
+ __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH0_TGL; /**< ASYNCTRIG consumer register */
+ __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH1_TGL; /**< ASYNCTRIG Consumer register */
+ __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH0_TGL; /**< SYNCTRIG Consumer register */
+ __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH1_TGL; /**< SYNCTRIG Consumer register */
+ __IOM uint32_t CONSUMER_WDOG0_SRC0_TGL; /**< SRC0 consumer register */
+ __IOM uint32_t CONSUMER_WDOG0_SRC1_TGL; /**< SRC1 Consumer register */
+ __IOM uint32_t CONSUMER_WDOG1_SRC0_TGL; /**< SRC0 consumer register */
+ __IOM uint32_t CONSUMER_WDOG1_SRC1_TGL; /**< SRC1 Consumer register */
+ uint32_t RESERVED22[1U]; /**< Reserved for future use */
+} PRS_TypeDef;
+/** @} End of group EFR32MG24_PRS */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_PRS
+ * @{
+ * @defgroup EFR32MG24_PRS_BitFields PRS Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for PRS IPVERSION */
+#define _PRS_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for PRS_IPVERSION */
+#define _PRS_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PRS_IPVERSION */
+#define _PRS_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PRS_IPVERSION */
+#define _PRS_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PRS_IPVERSION */
+#define _PRS_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for PRS_IPVERSION */
+#define PRS_IPVERSION_IPVERSION_DEFAULT (_PRS_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_IPVERSION */
+
+/* Bit fields for PRS ASYNC_SWPULSE */
+#define _PRS_ASYNC_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWPULSE */
+#define _PRS_ASYNC_SWPULSE_MASK 0x0000FFFFUL /**< Mask for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel pulse */
+#define _PRS_ASYNC_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */
+#define _PRS_ASYNC_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */
+#define _PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel pulse */
+#define _PRS_ASYNC_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */
+#define _PRS_ASYNC_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */
+#define _PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel pulse */
+#define _PRS_ASYNC_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */
+#define _PRS_ASYNC_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */
+#define _PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel pulse */
+#define _PRS_ASYNC_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */
+#define _PRS_ASYNC_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */
+#define _PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel pulse */
+#define _PRS_ASYNC_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */
+#define _PRS_ASYNC_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */
+#define _PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel pulse */
+#define _PRS_ASYNC_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */
+#define _PRS_ASYNC_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */
+#define _PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel pulse */
+#define _PRS_ASYNC_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */
+#define _PRS_ASYNC_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */
+#define _PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel pulse */
+#define _PRS_ASYNC_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */
+#define _PRS_ASYNC_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */
+#define _PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel pulse */
+#define _PRS_ASYNC_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */
+#define _PRS_ASYNC_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */
+#define _PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel pulse */
+#define _PRS_ASYNC_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */
+#define _PRS_ASYNC_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */
+#define _PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel pulse */
+#define _PRS_ASYNC_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */
+#define _PRS_ASYNC_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */
+#define _PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel pulse */
+#define _PRS_ASYNC_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */
+#define _PRS_ASYNC_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */
+#define _PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel pulse */
+#define _PRS_ASYNC_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */
+#define _PRS_ASYNC_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */
+#define _PRS_ASYNC_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH12PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel pulse */
+#define _PRS_ASYNC_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */
+#define _PRS_ASYNC_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */
+#define _PRS_ASYNC_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH13PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel pulse */
+#define _PRS_ASYNC_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */
+#define _PRS_ASYNC_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */
+#define _PRS_ASYNC_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH14PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel pulse */
+#define _PRS_ASYNC_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */
+#define _PRS_ASYNC_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */
+#define _PRS_ASYNC_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */
+#define PRS_ASYNC_SWPULSE_CH15PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */
+
+/* Bit fields for PRS ASYNC_SWLEVEL */
+#define _PRS_ASYNC_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWLEVEL */
+#define _PRS_ASYNC_SWLEVEL_MASK 0x0000FFFFUL /**< Mask for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel Level */
+#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel Level */
+#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel Level */
+#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel Level */
+#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel Level */
+#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel Level */
+#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel Level */
+#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel Level */
+#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel Level */
+#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel Level */
+#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel Level */
+#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel Level */
+#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel Level */
+#define _PRS_ASYNC_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel Level */
+#define _PRS_ASYNC_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel Level */
+#define _PRS_ASYNC_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel Level */
+#define _PRS_ASYNC_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */
+#define _PRS_ASYNC_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */
+#define PRS_ASYNC_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */
+
+/* Bit fields for PRS ASYNC_PEEK */
+#define _PRS_ASYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_PEEK */
+#define _PRS_ASYNC_PEEK_MASK 0x0000FFFFUL /**< Mask for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */
+#define _PRS_ASYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */
+#define _PRS_ASYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */
+#define _PRS_ASYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH0VAL_DEFAULT (_PRS_ASYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */
+#define _PRS_ASYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */
+#define _PRS_ASYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */
+#define _PRS_ASYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH1VAL_DEFAULT (_PRS_ASYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */
+#define _PRS_ASYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */
+#define _PRS_ASYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */
+#define _PRS_ASYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH2VAL_DEFAULT (_PRS_ASYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */
+#define _PRS_ASYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */
+#define _PRS_ASYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */
+#define _PRS_ASYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH3VAL_DEFAULT (_PRS_ASYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */
+#define _PRS_ASYNC_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */
+#define _PRS_ASYNC_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */
+#define _PRS_ASYNC_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH4VAL_DEFAULT (_PRS_ASYNC_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */
+#define _PRS_ASYNC_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */
+#define _PRS_ASYNC_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */
+#define _PRS_ASYNC_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH5VAL_DEFAULT (_PRS_ASYNC_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */
+#define _PRS_ASYNC_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */
+#define _PRS_ASYNC_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */
+#define _PRS_ASYNC_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH6VAL_DEFAULT (_PRS_ASYNC_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */
+#define _PRS_ASYNC_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */
+#define _PRS_ASYNC_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */
+#define _PRS_ASYNC_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH7VAL_DEFAULT (_PRS_ASYNC_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */
+#define _PRS_ASYNC_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */
+#define _PRS_ASYNC_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */
+#define _PRS_ASYNC_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH8VAL_DEFAULT (_PRS_ASYNC_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */
+#define _PRS_ASYNC_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */
+#define _PRS_ASYNC_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */
+#define _PRS_ASYNC_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH9VAL_DEFAULT (_PRS_ASYNC_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */
+#define _PRS_ASYNC_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */
+#define _PRS_ASYNC_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */
+#define _PRS_ASYNC_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH10VAL_DEFAULT (_PRS_ASYNC_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */
+#define _PRS_ASYNC_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */
+#define _PRS_ASYNC_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */
+#define _PRS_ASYNC_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH11VAL_DEFAULT (_PRS_ASYNC_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */
+#define _PRS_ASYNC_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */
+#define _PRS_ASYNC_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */
+#define _PRS_ASYNC_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH12VAL_DEFAULT (_PRS_ASYNC_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 current value */
+#define _PRS_ASYNC_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */
+#define _PRS_ASYNC_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */
+#define _PRS_ASYNC_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH13VAL_DEFAULT (_PRS_ASYNC_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 current value */
+#define _PRS_ASYNC_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */
+#define _PRS_ASYNC_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */
+#define _PRS_ASYNC_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH14VAL_DEFAULT (_PRS_ASYNC_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 current value */
+#define _PRS_ASYNC_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */
+#define _PRS_ASYNC_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */
+#define _PRS_ASYNC_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */
+#define PRS_ASYNC_PEEK_CH15VAL_DEFAULT (_PRS_ASYNC_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */
+
+/* Bit fields for PRS SYNC_PEEK */
+#define _PRS_SYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_PEEK */
+#define _PRS_SYNC_PEEK_MASK 0x0000000FUL /**< Mask for PRS_SYNC_PEEK */
+#define PRS_SYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel Value */
+#define _PRS_SYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */
+#define _PRS_SYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */
+#define _PRS_SYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */
+#define PRS_SYNC_PEEK_CH0VAL_DEFAULT (_PRS_SYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */
+#define PRS_SYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel Value */
+#define _PRS_SYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */
+#define _PRS_SYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */
+#define _PRS_SYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */
+#define PRS_SYNC_PEEK_CH1VAL_DEFAULT (_PRS_SYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */
+#define PRS_SYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel Value */
+#define _PRS_SYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */
+#define _PRS_SYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */
+#define _PRS_SYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */
+#define PRS_SYNC_PEEK_CH2VAL_DEFAULT (_PRS_SYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */
+#define PRS_SYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel Value */
+#define _PRS_SYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */
+#define _PRS_SYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */
+#define _PRS_SYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */
+#define PRS_SYNC_PEEK_CH3VAL_DEFAULT (_PRS_SYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */
+
+/* Bit fields for PRS ASYNC_CH_CTRL */
+#define _PRS_ASYNC_CH_CTRL_RESETVALUE 0x000C0000UL /**< Default value for PRS_ASYNC_CH_CTRL */
+#define _PRS_ASYNC_CH_CTRL_MASK 0x0F0F7F07UL /**< Mask for PRS_ASYNC_CH_CTRL */
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_NONE 0x00000000UL /**< Mode NONE for PRS_ASYNC_CH_CTRL */
+#define PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */
+#define PRS_ASYNC_CH_CTRL_SIGSEL_NONE (_PRS_ASYNC_CH_CTRL_SIGSEL_NONE << 0) /**< Shifted mode NONE for PRS_ASYNC_CH_CTRL */
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */
+#define _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT 16 /**< Shift value for PRS_FNSEL */
+#define _PRS_ASYNC_CH_CTRL_FNSEL_MASK 0xF0000UL /**< Bit mask for PRS_FNSEL */
+#define _PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */
+#define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO 0x00000000UL /**< Mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL */
+#define _PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B 0x00000001UL /**< Mode A_NOR_B for PRS_ASYNC_CH_CTRL */
+#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B 0x00000002UL /**< Mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL */
+#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A 0x00000003UL /**< Mode NOT_A for PRS_ASYNC_CH_CTRL */
+#define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B 0x00000004UL /**< Mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL */
+#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_B 0x00000005UL /**< Mode NOT_B for PRS_ASYNC_CH_CTRL */
+#define _PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B 0x00000006UL /**< Mode A_XOR_B for PRS_ASYNC_CH_CTRL */
+#define _PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B 0x00000007UL /**< Mode A_NAND_B for PRS_ASYNC_CH_CTRL */
+#define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B 0x00000008UL /**< Mode A_AND_B for PRS_ASYNC_CH_CTRL */
+#define _PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B 0x00000009UL /**< Mode A_XNOR_B for PRS_ASYNC_CH_CTRL */
+#define _PRS_ASYNC_CH_CTRL_FNSEL_B 0x0000000AUL /**< Mode B for PRS_ASYNC_CH_CTRL */
+#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B 0x0000000BUL /**< Mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL */
+#define _PRS_ASYNC_CH_CTRL_FNSEL_A 0x0000000CUL /**< Mode A for PRS_ASYNC_CH_CTRL */
+#define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B 0x0000000DUL /**< Mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL */
+#define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B 0x0000000EUL /**< Mode A_OR_B for PRS_ASYNC_CH_CTRL */
+#define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE 0x0000000FUL /**< Mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL */
+#define PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */
+#define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO << 16) /**< Shifted mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL*/
+#define PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B << 16) /**< Shifted mode A_NOR_B for PRS_ASYNC_CH_CTRL */
+#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B << 16) /**< Shifted mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL*/
+#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A << 16) /**< Shifted mode NOT_A for PRS_ASYNC_CH_CTRL */
+#define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B << 16) /**< Shifted mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL*/
+#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_B << 16) /**< Shifted mode NOT_B for PRS_ASYNC_CH_CTRL */
+#define PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B << 16) /**< Shifted mode A_XOR_B for PRS_ASYNC_CH_CTRL */
+#define PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B << 16) /**< Shifted mode A_NAND_B for PRS_ASYNC_CH_CTRL */
+#define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B << 16) /**< Shifted mode A_AND_B for PRS_ASYNC_CH_CTRL */
+#define PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B << 16) /**< Shifted mode A_XNOR_B for PRS_ASYNC_CH_CTRL */
+#define PRS_ASYNC_CH_CTRL_FNSEL_B (_PRS_ASYNC_CH_CTRL_FNSEL_B << 16) /**< Shifted mode B for PRS_ASYNC_CH_CTRL */
+#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B << 16) /**< Shifted mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL*/
+#define PRS_ASYNC_CH_CTRL_FNSEL_A (_PRS_ASYNC_CH_CTRL_FNSEL_A << 16) /**< Shifted mode A for PRS_ASYNC_CH_CTRL */
+#define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B << 16) /**< Shifted mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL*/
+#define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B << 16) /**< Shifted mode A_OR_B for PRS_ASYNC_CH_CTRL */
+#define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE << 16) /**< Shifted mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL*/
+#define _PRS_ASYNC_CH_CTRL_AUXSEL_SHIFT 24 /**< Shift value for PRS_AUXSEL */
+#define _PRS_ASYNC_CH_CTRL_AUXSEL_MASK 0xF000000UL /**< Bit mask for PRS_AUXSEL */
+#define _PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */
+#define PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */
+
+/* Bit fields for PRS SYNC_CH_CTRL */
+#define _PRS_SYNC_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_CH_CTRL */
+#define _PRS_SYNC_CH_CTRL_MASK 0x00007F07UL /**< Mask for PRS_SYNC_CH_CTRL */
+#define _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */
+#define _PRS_SYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */
+#define _PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */
+#define _PRS_SYNC_CH_CTRL_SIGSEL_NONE 0x00000000UL /**< Mode NONE for PRS_SYNC_CH_CTRL */
+#define PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */
+#define PRS_SYNC_CH_CTRL_SIGSEL_NONE (_PRS_SYNC_CH_CTRL_SIGSEL_NONE << 0) /**< Shifted mode NONE for PRS_SYNC_CH_CTRL */
+#define _PRS_SYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */
+#define _PRS_SYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */
+#define _PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */
+#define PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */
+
+/* Bit fields for PRS CONSUMER_CMU_CALDN */
+#define _PRS_CONSUMER_CMU_CALDN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALDN */
+#define _PRS_CONSUMER_CMU_CALDN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALDN */
+#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALDN */
+#define PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALDN*/
+
+/* Bit fields for PRS CONSUMER_CMU_CALUP */
+#define _PRS_CONSUMER_CMU_CALUP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALUP */
+#define _PRS_CONSUMER_CMU_CALUP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALUP */
+#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALUP */
+#define PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALUP*/
+
+/* Bit fields for PRS CONSUMER_EUSART0_CLK */
+#define _PRS_CONSUMER_EUSART0_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_CLK */
+#define _PRS_CONSUMER_EUSART0_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_CLK */
+#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_CLK */
+#define PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_CLK*/
+
+/* Bit fields for PRS CONSUMER_EUSART0_RX */
+#define _PRS_CONSUMER_EUSART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_RX */
+#define _PRS_CONSUMER_EUSART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_RX */
+#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_RX */
+#define PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_RX*/
+
+/* Bit fields for PRS CONSUMER_EUSART0_TRIGGER */
+#define _PRS_CONSUMER_EUSART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_TRIGGER*/
+#define _PRS_CONSUMER_EUSART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_TRIGGER */
+#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_TRIGGER*/
+#define PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_TRIGGER*/
+
+/* Bit fields for PRS CONSUMER_EUSART1_CLK */
+#define _PRS_CONSUMER_EUSART1_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_CLK */
+#define _PRS_CONSUMER_EUSART1_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_CLK */
+#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_CLK */
+#define PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_CLK*/
+
+/* Bit fields for PRS CONSUMER_EUSART1_RX */
+#define _PRS_CONSUMER_EUSART1_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_RX */
+#define _PRS_CONSUMER_EUSART1_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_RX */
+#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_RX */
+#define PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_RX*/
+
+/* Bit fields for PRS CONSUMER_EUSART1_TRIGGER */
+#define _PRS_CONSUMER_EUSART1_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_TRIGGER*/
+#define _PRS_CONSUMER_EUSART1_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_TRIGGER */
+#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_TRIGGER*/
+#define PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_TRIGGER*/
+
+/* Bit fields for PRS CONSUMER_IADC0_SCANTRIGGER */
+#define _PRS_CONSUMER_IADC0_SCANTRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SCANTRIGGER*/
+#define _PRS_CONSUMER_IADC0_SCANTRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SCANTRIGGER */
+#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/
+#define PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/
+#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */
+#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */
+#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/
+#define PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/
+
+/* Bit fields for PRS CONSUMER_IADC0_SINGLETRIGGER */
+#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SINGLETRIGGER*/
+#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SINGLETRIGGER */
+#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/
+#define PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/
+#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */
+#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */
+#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/
+#define PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/
+
+/* Bit fields for PRS CONSUMER_LDMAXBAR_DMAREQ0 */
+#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/
+#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ0 */
+#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/
+#define PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/
+
+/* Bit fields for PRS CONSUMER_LDMAXBAR_DMAREQ1 */
+#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/
+#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ1 */
+#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/
+#define PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/
+
+/* Bit fields for PRS CONSUMER_LETIMER0_CLEAR */
+#define _PRS_CONSUMER_LETIMER0_CLEAR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_CLEAR*/
+#define _PRS_CONSUMER_LETIMER0_CLEAR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_CLEAR */
+#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/
+#define PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/
+
+/* Bit fields for PRS CONSUMER_LETIMER0_START */
+#define _PRS_CONSUMER_LETIMER0_START_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_START*/
+#define _PRS_CONSUMER_LETIMER0_START_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_START */
+#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/
+#define PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/
+
+/* Bit fields for PRS CONSUMER_LETIMER0_STOP */
+#define _PRS_CONSUMER_LETIMER0_STOP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_STOP*/
+#define _PRS_CONSUMER_LETIMER0_STOP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_STOP */
+#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP */
+#define PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP*/
+
+/* Bit fields for PRS CONSUMER_MODEM_DIN */
+#define _PRS_CONSUMER_MODEM_DIN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_MODEM_DIN */
+#define _PRS_CONSUMER_MODEM_DIN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_MODEM_DIN */
+#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_MODEM_DIN */
+#define PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT (_PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_MODEM_DIN*/
+
+/* Bit fields for PRS CONSUMER_MODEM_PAEN */
+#define _PRS_CONSUMER_MODEM_PAEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_MODEM_PAEN */
+#define _PRS_CONSUMER_MODEM_PAEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_MODEM_PAEN */
+#define _PRS_CONSUMER_MODEM_PAEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_MODEM_PAEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_MODEM_PAEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_MODEM_PAEN */
+#define PRS_CONSUMER_MODEM_PAEN_PRSSEL_DEFAULT (_PRS_CONSUMER_MODEM_PAEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_MODEM_PAEN*/
+
+/* Bit fields for PRS CONSUMER_PCNT0_S0IN */
+#define _PRS_CONSUMER_PCNT0_S0IN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_PCNT0_S0IN */
+#define _PRS_CONSUMER_PCNT0_S0IN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_PCNT0_S0IN */
+#define _PRS_CONSUMER_PCNT0_S0IN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_PCNT0_S0IN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_PCNT0_S0IN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_PCNT0_S0IN */
+#define PRS_CONSUMER_PCNT0_S0IN_PRSSEL_DEFAULT (_PRS_CONSUMER_PCNT0_S0IN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_PCNT0_S0IN*/
+
+/* Bit fields for PRS CONSUMER_PCNT0_S1IN */
+#define _PRS_CONSUMER_PCNT0_S1IN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_PCNT0_S1IN */
+#define _PRS_CONSUMER_PCNT0_S1IN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_PCNT0_S1IN */
+#define _PRS_CONSUMER_PCNT0_S1IN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_PCNT0_S1IN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_PCNT0_S1IN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_PCNT0_S1IN */
+#define PRS_CONSUMER_PCNT0_S1IN_PRSSEL_DEFAULT (_PRS_CONSUMER_PCNT0_S1IN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_PCNT0_S1IN*/
+
+/* Bit fields for PRS CONSUMER_RAC_CLR */
+#define _PRS_CONSUMER_RAC_CLR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CLR */
+#define _PRS_CONSUMER_RAC_CLR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CLR */
+#define _PRS_CONSUMER_RAC_CLR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_RAC_CLR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CLR */
+#define PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CLR*/
+
+/* Bit fields for PRS CONSUMER_RAC_CTIIN0 */
+#define _PRS_CONSUMER_RAC_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN0 */
+#define _PRS_CONSUMER_RAC_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN0 */
+#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0 */
+#define PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0*/
+
+/* Bit fields for PRS CONSUMER_RAC_CTIIN1 */
+#define _PRS_CONSUMER_RAC_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN1 */
+#define _PRS_CONSUMER_RAC_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN1 */
+#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1 */
+#define PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1*/
+
+/* Bit fields for PRS CONSUMER_RAC_CTIIN2 */
+#define _PRS_CONSUMER_RAC_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN2 */
+#define _PRS_CONSUMER_RAC_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN2 */
+#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2 */
+#define PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2*/
+
+/* Bit fields for PRS CONSUMER_RAC_CTIIN3 */
+#define _PRS_CONSUMER_RAC_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN3 */
+#define _PRS_CONSUMER_RAC_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN3 */
+#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3 */
+#define PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3*/
+
+/* Bit fields for PRS CONSUMER_RAC_FORCETX */
+#define _PRS_CONSUMER_RAC_FORCETX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_FORCETX */
+#define _PRS_CONSUMER_RAC_FORCETX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_FORCETX */
+#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_FORCETX */
+#define PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_FORCETX*/
+
+/* Bit fields for PRS CONSUMER_RAC_RXDIS */
+#define _PRS_CONSUMER_RAC_RXDIS_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXDIS */
+#define _PRS_CONSUMER_RAC_RXDIS_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXDIS */
+#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXDIS */
+#define PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXDIS*/
+
+/* Bit fields for PRS CONSUMER_RAC_RXEN */
+#define _PRS_CONSUMER_RAC_RXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXEN */
+#define _PRS_CONSUMER_RAC_RXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXEN */
+#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXEN */
+#define PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXEN*/
+
+/* Bit fields for PRS CONSUMER_RAC_TXEN */
+#define _PRS_CONSUMER_RAC_TXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_TXEN */
+#define _PRS_CONSUMER_RAC_TXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_TXEN */
+#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_TXEN */
+#define PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_TXEN*/
+
+/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC25 */
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC25*/
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC25 */
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC25*/
+#define PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC25*/
+
+/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC26 */
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC26 */
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/
+#define PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/
+
+/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC27 */
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC27 */
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/
+#define PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/
+
+/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC28 */
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC28 */
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/
+#define PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/
+
+/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC29 */
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC29 */
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/
+#define PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/
+
+/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC30 */
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC30 */
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/
+#define PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/
+
+/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC31 */
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC31 */
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/
+#define PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/
+
+/* Bit fields for PRS CONSUMER_SYSRTC0_IN0 */
+#define _PRS_CONSUMER_SYSRTC0_IN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SYSRTC0_IN0 */
+#define _PRS_CONSUMER_SYSRTC0_IN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SYSRTC0_IN0 */
+#define _PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN0 */
+#define PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_DEFAULT (_PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN0*/
+
+/* Bit fields for PRS CONSUMER_SYSRTC0_IN1 */
+#define _PRS_CONSUMER_SYSRTC0_IN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SYSRTC0_IN1 */
+#define _PRS_CONSUMER_SYSRTC0_IN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SYSRTC0_IN1 */
+#define _PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN1 */
+#define PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_DEFAULT (_PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN1*/
+
+/* Bit fields for PRS CONSUMER_HFXO0_OSCREQ */
+#define _PRS_CONSUMER_HFXO0_OSCREQ_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_HFXO0_OSCREQ */
+#define _PRS_CONSUMER_HFXO0_OSCREQ_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_HFXO0_OSCREQ */
+#define _PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_HFXO0_OSCREQ */
+#define PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_DEFAULT (_PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_HFXO0_OSCREQ*/
+
+/* Bit fields for PRS CONSUMER_HFXO0_TIMEOUT */
+#define _PRS_CONSUMER_HFXO0_TIMEOUT_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_HFXO0_TIMEOUT*/
+#define _PRS_CONSUMER_HFXO0_TIMEOUT_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_HFXO0_TIMEOUT */
+#define _PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_HFXO0_TIMEOUT */
+#define PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_DEFAULT (_PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_HFXO0_TIMEOUT*/
+
+/* Bit fields for PRS CONSUMER_CORE_CTIIN0 */
+#define _PRS_CONSUMER_CORE_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN0 */
+#define _PRS_CONSUMER_CORE_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN0 */
+#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0 */
+#define PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0*/
+
+/* Bit fields for PRS CONSUMER_CORE_CTIIN1 */
+#define _PRS_CONSUMER_CORE_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN1 */
+#define _PRS_CONSUMER_CORE_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN1 */
+#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1 */
+#define PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1*/
+
+/* Bit fields for PRS CONSUMER_CORE_CTIIN2 */
+#define _PRS_CONSUMER_CORE_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN2 */
+#define _PRS_CONSUMER_CORE_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN2 */
+#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2 */
+#define PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2*/
+
+/* Bit fields for PRS CONSUMER_CORE_CTIIN3 */
+#define _PRS_CONSUMER_CORE_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN3 */
+#define _PRS_CONSUMER_CORE_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN3 */
+#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3 */
+#define PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3*/
+
+/* Bit fields for PRS CONSUMER_CORE_M33RXEV */
+#define _PRS_CONSUMER_CORE_M33RXEV_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_M33RXEV */
+#define _PRS_CONSUMER_CORE_M33RXEV_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_M33RXEV */
+#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV */
+#define PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV*/
+
+/* Bit fields for PRS CONSUMER_TIMER0_CC0 */
+#define _PRS_CONSUMER_TIMER0_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC0 */
+#define _PRS_CONSUMER_TIMER0_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC0 */
+#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */
+#define PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/
+#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */
+#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */
+#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */
+#define PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/
+
+/* Bit fields for PRS CONSUMER_TIMER0_CC1 */
+#define _PRS_CONSUMER_TIMER0_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC1 */
+#define _PRS_CONSUMER_TIMER0_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC1 */
+#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */
+#define PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/
+#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */
+#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */
+#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */
+#define PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/
+
+/* Bit fields for PRS CONSUMER_TIMER0_CC2 */
+#define _PRS_CONSUMER_TIMER0_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC2 */
+#define _PRS_CONSUMER_TIMER0_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC2 */
+#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */
+#define PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/
+#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */
+#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */
+#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */
+#define PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/
+
+/* Bit fields for PRS CONSUMER_TIMER0_DTI */
+#define _PRS_CONSUMER_TIMER0_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTI */
+#define _PRS_CONSUMER_TIMER0_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTI */
+#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTI */
+#define PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTI*/
+
+/* Bit fields for PRS CONSUMER_TIMER0_DTIFS1 */
+#define _PRS_CONSUMER_TIMER0_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS1*/
+#define _PRS_CONSUMER_TIMER0_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS1 */
+#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1 */
+#define PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1*/
+
+/* Bit fields for PRS CONSUMER_TIMER0_DTIFS2 */
+#define _PRS_CONSUMER_TIMER0_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS2*/
+#define _PRS_CONSUMER_TIMER0_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS2 */
+#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2 */
+#define PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2*/
+
+/* Bit fields for PRS CONSUMER_TIMER1_CC0 */
+#define _PRS_CONSUMER_TIMER1_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC0 */
+#define _PRS_CONSUMER_TIMER1_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC0 */
+#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */
+#define PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/
+#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */
+#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */
+#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */
+#define PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/
+
+/* Bit fields for PRS CONSUMER_TIMER1_CC1 */
+#define _PRS_CONSUMER_TIMER1_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC1 */
+#define _PRS_CONSUMER_TIMER1_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC1 */
+#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */
+#define PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/
+#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */
+#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */
+#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */
+#define PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/
+
+/* Bit fields for PRS CONSUMER_TIMER1_CC2 */
+#define _PRS_CONSUMER_TIMER1_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC2 */
+#define _PRS_CONSUMER_TIMER1_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC2 */
+#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */
+#define PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/
+#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */
+#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */
+#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */
+#define PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/
+
+/* Bit fields for PRS CONSUMER_TIMER1_DTI */
+#define _PRS_CONSUMER_TIMER1_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTI */
+#define _PRS_CONSUMER_TIMER1_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTI */
+#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTI */
+#define PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTI*/
+
+/* Bit fields for PRS CONSUMER_TIMER1_DTIFS1 */
+#define _PRS_CONSUMER_TIMER1_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS1*/
+#define _PRS_CONSUMER_TIMER1_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS1 */
+#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1 */
+#define PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1*/
+
+/* Bit fields for PRS CONSUMER_TIMER1_DTIFS2 */
+#define _PRS_CONSUMER_TIMER1_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS2*/
+#define _PRS_CONSUMER_TIMER1_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS2 */
+#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2 */
+#define PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2*/
+
+/* Bit fields for PRS CONSUMER_TIMER2_CC0 */
+#define _PRS_CONSUMER_TIMER2_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC0 */
+#define _PRS_CONSUMER_TIMER2_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC0 */
+#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */
+#define PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/
+#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */
+#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */
+#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */
+#define PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/
+
+/* Bit fields for PRS CONSUMER_TIMER2_CC1 */
+#define _PRS_CONSUMER_TIMER2_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC1 */
+#define _PRS_CONSUMER_TIMER2_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC1 */
+#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */
+#define PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/
+#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */
+#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */
+#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */
+#define PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/
+
+/* Bit fields for PRS CONSUMER_TIMER2_CC2 */
+#define _PRS_CONSUMER_TIMER2_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC2 */
+#define _PRS_CONSUMER_TIMER2_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC2 */
+#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */
+#define PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/
+#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */
+#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */
+#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */
+#define PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/
+
+/* Bit fields for PRS CONSUMER_TIMER2_DTI */
+#define _PRS_CONSUMER_TIMER2_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTI */
+#define _PRS_CONSUMER_TIMER2_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTI */
+#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTI */
+#define PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTI*/
+
+/* Bit fields for PRS CONSUMER_TIMER2_DTIFS1 */
+#define _PRS_CONSUMER_TIMER2_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS1*/
+#define _PRS_CONSUMER_TIMER2_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS1 */
+#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1 */
+#define PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1*/
+
+/* Bit fields for PRS CONSUMER_TIMER2_DTIFS2 */
+#define _PRS_CONSUMER_TIMER2_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS2*/
+#define _PRS_CONSUMER_TIMER2_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS2 */
+#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2 */
+#define PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2*/
+
+/* Bit fields for PRS CONSUMER_TIMER3_CC0 */
+#define _PRS_CONSUMER_TIMER3_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC0 */
+#define _PRS_CONSUMER_TIMER3_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC0 */
+#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */
+#define PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/
+#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */
+#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */
+#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */
+#define PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/
+
+/* Bit fields for PRS CONSUMER_TIMER3_CC1 */
+#define _PRS_CONSUMER_TIMER3_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC1 */
+#define _PRS_CONSUMER_TIMER3_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC1 */
+#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */
+#define PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/
+#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */
+#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */
+#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */
+#define PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/
+
+/* Bit fields for PRS CONSUMER_TIMER3_CC2 */
+#define _PRS_CONSUMER_TIMER3_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC2 */
+#define _PRS_CONSUMER_TIMER3_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC2 */
+#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */
+#define PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/
+#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */
+#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */
+#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */
+#define PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/
+
+/* Bit fields for PRS CONSUMER_TIMER3_DTI */
+#define _PRS_CONSUMER_TIMER3_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTI */
+#define _PRS_CONSUMER_TIMER3_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTI */
+#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTI */
+#define PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTI*/
+
+/* Bit fields for PRS CONSUMER_TIMER3_DTIFS1 */
+#define _PRS_CONSUMER_TIMER3_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS1*/
+#define _PRS_CONSUMER_TIMER3_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS1 */
+#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1 */
+#define PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1*/
+
+/* Bit fields for PRS CONSUMER_TIMER3_DTIFS2 */
+#define _PRS_CONSUMER_TIMER3_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS2*/
+#define _PRS_CONSUMER_TIMER3_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS2 */
+#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2 */
+#define PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2*/
+
+/* Bit fields for PRS CONSUMER_TIMER4_CC0 */
+#define _PRS_CONSUMER_TIMER4_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC0 */
+#define _PRS_CONSUMER_TIMER4_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC0 */
+#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */
+#define PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/
+#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */
+#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */
+#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */
+#define PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/
+
+/* Bit fields for PRS CONSUMER_TIMER4_CC1 */
+#define _PRS_CONSUMER_TIMER4_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC1 */
+#define _PRS_CONSUMER_TIMER4_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC1 */
+#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */
+#define PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/
+#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */
+#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */
+#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */
+#define PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/
+
+/* Bit fields for PRS CONSUMER_TIMER4_CC2 */
+#define _PRS_CONSUMER_TIMER4_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC2 */
+#define _PRS_CONSUMER_TIMER4_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC2 */
+#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */
+#define PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/
+#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */
+#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */
+#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */
+#define PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/
+
+/* Bit fields for PRS CONSUMER_TIMER4_DTI */
+#define _PRS_CONSUMER_TIMER4_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTI */
+#define _PRS_CONSUMER_TIMER4_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTI */
+#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTI */
+#define PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTI*/
+
+/* Bit fields for PRS CONSUMER_TIMER4_DTIFS1 */
+#define _PRS_CONSUMER_TIMER4_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS1*/
+#define _PRS_CONSUMER_TIMER4_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS1 */
+#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1 */
+#define PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1*/
+
+/* Bit fields for PRS CONSUMER_TIMER4_DTIFS2 */
+#define _PRS_CONSUMER_TIMER4_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS2*/
+#define _PRS_CONSUMER_TIMER4_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS2 */
+#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2 */
+#define PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2*/
+
+/* Bit fields for PRS CONSUMER_USART0_CLK */
+#define _PRS_CONSUMER_USART0_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_CLK */
+#define _PRS_CONSUMER_USART0_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_CLK */
+#define _PRS_CONSUMER_USART0_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_USART0_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_CLK */
+#define PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_CLK*/
+
+/* Bit fields for PRS CONSUMER_USART0_IR */
+#define _PRS_CONSUMER_USART0_IR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_IR */
+#define _PRS_CONSUMER_USART0_IR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_IR */
+#define _PRS_CONSUMER_USART0_IR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_USART0_IR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_IR */
+#define PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_IR*/
+
+/* Bit fields for PRS CONSUMER_USART0_RX */
+#define _PRS_CONSUMER_USART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_RX */
+#define _PRS_CONSUMER_USART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_RX */
+#define _PRS_CONSUMER_USART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_USART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_RX */
+#define PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_RX*/
+
+/* Bit fields for PRS CONSUMER_USART0_TRIGGER */
+#define _PRS_CONSUMER_USART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_TRIGGER*/
+#define _PRS_CONSUMER_USART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_TRIGGER */
+#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/
+#define PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/
+
+/* Bit fields for PRS CONSUMER_VDAC0_ASYNCTRIGCH0 */
+#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0*/
+#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0 */
+#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0*/
+#define PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0*/
+
+/* Bit fields for PRS CONSUMER_VDAC0_ASYNCTRIGCH1 */
+#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1*/
+#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1 */
+#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1*/
+#define PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1*/
+
+/* Bit fields for PRS CONSUMER_VDAC0_SYNCTRIGCH0 */
+#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_SYNCTRIGCH0*/
+#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_MASK 0x00000300UL /**< Mask for PRS_CONSUMER_VDAC0_SYNCTRIGCH0 */
+#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */
+#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */
+#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH0*/
+#define PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH0*/
+
+/* Bit fields for PRS CONSUMER_VDAC0_SYNCTRIGCH1 */
+#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_SYNCTRIGCH1*/
+#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_MASK 0x00000300UL /**< Mask for PRS_CONSUMER_VDAC0_SYNCTRIGCH1 */
+#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */
+#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */
+#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH1*/
+#define PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH1*/
+
+/* Bit fields for PRS CONSUMER_VDAC1_ASYNCTRIGCH0 */
+#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC1_ASYNCTRIGCH0*/
+#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_VDAC1_ASYNCTRIGCH0 */
+#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC1_ASYNCTRIGCH0*/
+#define PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_PRSSEL_DEFAULT (_PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC1_ASYNCTRIGCH0*/
+
+/* Bit fields for PRS CONSUMER_VDAC1_ASYNCTRIGCH1 */
+#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC1_ASYNCTRIGCH1*/
+#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_VDAC1_ASYNCTRIGCH1 */
+#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC1_ASYNCTRIGCH1*/
+#define PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_PRSSEL_DEFAULT (_PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC1_ASYNCTRIGCH1*/
+
+/* Bit fields for PRS CONSUMER_VDAC1_SYNCTRIGCH0 */
+#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC1_SYNCTRIGCH0*/
+#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH0_MASK 0x00000300UL /**< Mask for PRS_CONSUMER_VDAC1_SYNCTRIGCH0 */
+#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */
+#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */
+#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC1_SYNCTRIGCH0*/
+#define PRS_CONSUMER_VDAC1_SYNCTRIGCH0_SPRSSEL_DEFAULT (_PRS_CONSUMER_VDAC1_SYNCTRIGCH0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC1_SYNCTRIGCH0*/
+
+/* Bit fields for PRS CONSUMER_VDAC1_SYNCTRIGCH1 */
+#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC1_SYNCTRIGCH1*/
+#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH1_MASK 0x00000300UL /**< Mask for PRS_CONSUMER_VDAC1_SYNCTRIGCH1 */
+#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */
+#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */
+#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC1_SYNCTRIGCH1*/
+#define PRS_CONSUMER_VDAC1_SYNCTRIGCH1_SPRSSEL_DEFAULT (_PRS_CONSUMER_VDAC1_SYNCTRIGCH1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC1_SYNCTRIGCH1*/
+
+/* Bit fields for PRS CONSUMER_WDOG0_SRC0 */
+#define _PRS_CONSUMER_WDOG0_SRC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC0 */
+#define _PRS_CONSUMER_WDOG0_SRC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC0 */
+#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0 */
+#define PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0*/
+
+/* Bit fields for PRS CONSUMER_WDOG0_SRC1 */
+#define _PRS_CONSUMER_WDOG0_SRC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC1 */
+#define _PRS_CONSUMER_WDOG0_SRC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC1 */
+#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1 */
+#define PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1*/
+
+/* Bit fields for PRS CONSUMER_WDOG1_SRC0 */
+#define _PRS_CONSUMER_WDOG1_SRC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG1_SRC0 */
+#define _PRS_CONSUMER_WDOG1_SRC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG1_SRC0 */
+#define _PRS_CONSUMER_WDOG1_SRC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_WDOG1_SRC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_WDOG1_SRC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG1_SRC0 */
+#define PRS_CONSUMER_WDOG1_SRC0_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG1_SRC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG1_SRC0*/
+
+/* Bit fields for PRS CONSUMER_WDOG1_SRC1 */
+#define _PRS_CONSUMER_WDOG1_SRC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG1_SRC1 */
+#define _PRS_CONSUMER_WDOG1_SRC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG1_SRC1 */
+#define _PRS_CONSUMER_WDOG1_SRC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */
+#define _PRS_CONSUMER_WDOG1_SRC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */
+#define _PRS_CONSUMER_WDOG1_SRC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG1_SRC1 */
+#define PRS_CONSUMER_WDOG1_SRC1_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG1_SRC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG1_SRC1*/
+
+/** @} End of group EFR32MG24_PRS_BitFields */
+/** @} End of group EFR32MG24_PRS */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_PRS_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_prs_signals.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_prs_signals.h
new file mode 100644
index 00000000..0183dfa0
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_prs_signals.h
@@ -0,0 +1,975 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 PRS register signal bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+/** Synchronous signal sources enumeration: */
+#define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL)
+#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL)
+#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 (0x00000002UL)
+#define _PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 (0x00000003UL)
+#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 (0x00000004UL)
+#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 (0x00000005UL)
+#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 (0x00000006UL)
+#define _PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 (0x00000007UL)
+#define _PRS_SYNC_CH_CTRL_SOURCESEL_VDAC1 (0x00000008UL)
+
+/** Synchronous signal sources enumeration aligned with register bit field: */
+#define PRS_SYNC_CH_CTRL_SOURCESEL_NONE (_PRS_SYNC_CH_CTRL_SOURCESEL_NONE << 8)
+#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 << 8)
+#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 << 8)
+#define PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 (_PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 << 8)
+#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 << 8)
+#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 << 8)
+#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 << 8)
+#define PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 (_PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 << 8)
+#define PRS_SYNC_CH_CTRL_SOURCESEL_VDAC1 (_PRS_SYNC_CH_CTRL_SOURCESEL_VDAC1 << 8)
+
+/** Synchronous signals enumeration: */
+#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF (0x00000000UL)
+#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF (0x00000001UL)
+#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 (0x00000002UL)
+#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 (0x00000003UL)
+#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 (0x00000004UL)
+#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF (0x00000000UL)
+#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF (0x00000001UL)
+#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 (0x00000002UL)
+#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 (0x00000003UL)
+#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 (0x00000004UL)
+#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (0x00000000UL)
+#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (0x00000001UL)
+#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (0x00000002UL)
+#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF (0x00000000UL)
+#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF (0x00000001UL)
+#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 (0x00000002UL)
+#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 (0x00000003UL)
+#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 (0x00000004UL)
+#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF (0x00000000UL)
+#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF (0x00000001UL)
+#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 (0x00000002UL)
+#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 (0x00000003UL)
+#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 (0x00000004UL)
+#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF (0x00000000UL)
+#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF (0x00000001UL)
+#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 (0x00000002UL)
+#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 (0x00000003UL)
+#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 (0x00000004UL)
+#define _PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC (0x00000000UL)
+#define _PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC (0x00000001UL)
+#define _PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH0DONESYNC (0x00000000UL)
+#define _PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH1DONESYNC (0x00000001UL)
+
+/** Synchronous signals enumeration aligned with register bit field: */
+#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF << 0)
+#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF << 0)
+#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 << 0)
+#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 << 0)
+#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 << 0)
+#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF << 0)
+#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF << 0)
+#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 << 0)
+#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 << 0)
+#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 << 0)
+#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE << 0)
+#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE << 0)
+#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE << 0)
+#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF << 0)
+#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF << 0)
+#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 << 0)
+#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 << 0)
+#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 << 0)
+#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF << 0)
+#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF << 0)
+#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 << 0)
+#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 << 0)
+#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 << 0)
+#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF << 0)
+#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF << 0)
+#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 << 0)
+#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 << 0)
+#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 << 0)
+#define PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC (_PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC << 0)
+#define PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC (_PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC << 0)
+#define PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH0DONESYNC (_PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH0DONESYNC << 0)
+#define PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH1DONESYNC (_PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH1DONESYNC << 0)
+
+/** Synchronous signals and sources combined and aligned with register bit fields: */
+#define PRS_SYNC_TIMER0_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF)
+#define PRS_SYNC_TIMER0_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF)
+#define PRS_SYNC_TIMER0_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0)
+#define PRS_SYNC_TIMER0_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1)
+#define PRS_SYNC_TIMER0_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2)
+#define PRS_SYNC_TIMER1_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF)
+#define PRS_SYNC_TIMER1_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF)
+#define PRS_SYNC_TIMER1_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0)
+#define PRS_SYNC_TIMER1_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1)
+#define PRS_SYNC_TIMER1_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2)
+#define PRS_SYNC_IADC0_SCAN_ENTRY_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE)
+#define PRS_SYNC_IADC0_SCAN_TABLE_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE)
+#define PRS_SYNC_IADC0_SINGLE_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE)
+#define PRS_SYNC_TIMER2_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF)
+#define PRS_SYNC_TIMER2_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF)
+#define PRS_SYNC_TIMER2_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0)
+#define PRS_SYNC_TIMER2_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1)
+#define PRS_SYNC_TIMER2_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2)
+#define PRS_SYNC_TIMER3_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF)
+#define PRS_SYNC_TIMER3_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF)
+#define PRS_SYNC_TIMER3_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0)
+#define PRS_SYNC_TIMER3_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1)
+#define PRS_SYNC_TIMER3_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2)
+#define PRS_SYNC_TIMER4_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF)
+#define PRS_SYNC_TIMER4_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF)
+#define PRS_SYNC_TIMER4_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0)
+#define PRS_SYNC_TIMER4_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1)
+#define PRS_SYNC_TIMER4_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2)
+#define PRS_SYNC_VDAC0_CH0_DONE_SYNC (PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 | PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC)
+#define PRS_SYNC_VDAC0_CH1_DONE_SYNC (PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 | PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC)
+#define PRS_SYNC_VDAC1_CH0_DONE_SYNC (PRS_SYNC_CH_CTRL_SOURCESEL_VDAC1 | PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH0DONESYNC)
+#define PRS_SYNC_VDAC1_CH1_DONE_SYNC (PRS_SYNC_CH_CTRL_SOURCESEL_VDAC1 | PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH1DONESYNC)
+
+/** Asynchronous signal sources enumeration: */
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 (0x00000002UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC (0x00000003UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO (0x00000004UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL (0x00000005UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMU (0x00000006UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH (0x00000007UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL (0x00000008UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PRS (0x00000009UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 (0x0000000aUL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP1 (0x0000000bUL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 (0x0000000cUL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 (0x0000000dUL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L (0x0000000eUL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 (0x0000000fUL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L (0x00000010UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0 (0x00000011UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L (0x00000012UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0 (0x00000013UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L (0x00000014UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1 (0x00000015UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL (0x00000016UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EMU (0x00000017UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO (0x00000018UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCOEM23 (0x00000019UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 (0x00000020UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000021UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 (0x00000022UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 (0x00000023UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 (0x00000024UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CORE (0x00000025UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL (0x00000026UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_AGC (0x00000027UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC (0x00000028UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML (0x00000029UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM (0x0000002aUL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH (0x0000002bUL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_FRC (0x0000002cUL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL (0x0000002dUL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER (0x0000002eUL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH (0x0000002fUL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_RACL (0x00000030UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_RAC (0x00000031UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 (0x00000032UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L (0x00000033UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1 (0x00000034UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 (0x00000035UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SEHFRCO (0x00000036UL)
+#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SEATAMPDET (0x00000037UL)
+
+/** Asynchronous signal sources enumeration aligned with register bit field: */
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_NONE (_PRS_ASYNC_CH_CTRL_SOURCESEL_NONE << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC (_PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO (_PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_CORE (_PRS_ASYNC_CH_CTRL_SOURCESEL_CORE << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMU (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMU << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL (_PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_AGC (_PRS_ASYNC_CH_CTRL_SOURCESEL_AGC << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC (_PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_FRC (_PRS_ASYNC_CH_CTRL_SOURCESEL_FRC << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL (_PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER (_PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH (_PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL (_PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_PRS (_PRS_ASYNC_CH_CTRL_SOURCESEL_PRS << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_RACL (_PRS_ASYNC_CH_CTRL_SOURCESEL_RACL << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_RAC (_PRS_ASYNC_CH_CTRL_SOURCESEL_RAC << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP1 << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0 << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1 << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L (_PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0 << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L (_PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1 << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL (_PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_EMU (_PRS_ASYNC_CH_CTRL_SOURCESEL_EMU << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO (_PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCOEM23 (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCOEM23 << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_SEHFRCO (_PRS_ASYNC_CH_CTRL_SOURCESEL_SEHFRCO << 8)
+#define PRS_ASYNC_CH_CTRL_SOURCESEL_SEATAMPDET (_PRS_ASYNC_CH_CTRL_SOURCESEL_SEATAMPDET << 8)
+
+/** Asynchronous signals enumeration: */
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS (0x00000002UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA (0x00000003UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX (0x00000004UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC (0x00000005UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 (0x00000002UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 (0x00000003UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 (0x00000004UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 (0x00000002UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 (0x00000003UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 (0x00000004UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (0x00000002UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 (0x00000002UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 (0x00000003UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 (0x00000004UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 (0x00000005UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 (0x00000006UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 (0x00000007UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 (0x00000002UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 (0x00000003UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 (0x00000004UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 (0x00000002UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 (0x00000003UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 (0x00000004UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 (0x00000002UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 (0x00000003UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 (0x00000002UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST (0x00000002UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK (0x00000003UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED (0x00000004UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 (0x00000005UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 (0x00000006UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST (0x00000007UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE (0x00000002UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 (0x00000002UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 (0x00000003UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 (0x00000004UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 (0x00000005UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL (0x00000006UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 (0x00000002UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET (0x00000003UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE (0x00000004UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK (0x00000005UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT (0x00000006UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET (0x00000007UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET (0x00000002UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE (0x00000003UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL (0x00000004UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND (0x00000005UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE (0x00000006UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET (0x00000007UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT (0x00000002UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET (0x00000003UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK (0x00000004UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF (0x00000005UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSI (0x00000006UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 (0x00000002UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 (0x00000003UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 (0x00000004UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 (0x00000005UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF (0x00000006UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR (0x00000007UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH (0x00000002UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF (0x00000003UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH (0x00000004UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF (0x00000005UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF (0x00000006UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 (0x00000002UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 (0x00000003UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 (0x00000004UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 (0x00000005UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 (0x00000006UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 (0x00000007UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 (0x00000002UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 (0x00000003UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN (0x00000002UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX (0x00000003UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX (0x00000004UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 (0x00000005UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 (0x00000006UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 (0x00000007UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID (0x00000002UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 (0x00000002UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 (0x00000003UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 (0x00000004UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_ACMP1OUT (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0DIR (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0UFOF (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT0 (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT1 (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT0 (0x00000002UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT1 (0x00000003UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1 (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS (0x00000002UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV (0x00000003UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX (0x00000004UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC (0x00000005UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL (0x00000006UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL (0x00000007UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS (0x00000002UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV (0x00000003UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX (0x00000004UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC (0x00000005UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL (0x00000006UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL (0x00000007UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0WARM (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1WARM (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC (0x00000002UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC (0x00000003UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LINTERNALTIMEROF (0x00000004UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LREFRESHTIMEROF (0x00000005UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0WARM (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1WARM (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0DONEASYNC (0x00000002UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1DONEASYNC (0x00000003UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LINTERNALTIMEROF (0x00000004UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LREFRESHTIMEROF (0x00000005UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS (0x00000000UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM (0x00000001UL)
+#define _PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS (0x00000002UL)
+
+/** Asynchronous signals enumeration aligned with register bit field: */
+#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP (_PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW (_PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSI (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSI << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK (_PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT (_PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA (_PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID (_PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_ASYNC_CH_CTRL_SIGSEL_ACMP1OUT << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0DIR << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0UFOF << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT0 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT1 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT0 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT1 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS (_PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1 (_PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1 << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0WARM (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0WARM << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1WARM (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1WARM << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LINTERNALTIMEROF (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LINTERNALTIMEROF << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LREFRESHTIMEROF (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LREFRESHTIMEROF << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0WARM (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0WARM << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1WARM (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1WARM << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0DONEASYNC (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0DONEASYNC << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1DONEASYNC (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1DONEASYNC << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LINTERNALTIMEROF (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LINTERNALTIMEROF << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LREFRESHTIMEROF (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LREFRESHTIMEROF << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS (_PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM (_PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM << 0)
+#define PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS (_PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS << 0)
+
+/** Asynchronous signals and sources combined and aligned with register bit fields: */
+#define PRS_ASYNC_USART0_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS)
+#define PRS_ASYNC_USART0_IRTX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX)
+#define PRS_ASYNC_USART0_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS)
+#define PRS_ASYNC_USART0_RXDATA (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA)
+#define PRS_ASYNC_USART0_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX)
+#define PRS_ASYNC_USART0_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC)
+#define PRS_ASYNC_TIMER0_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF)
+#define PRS_ASYNC_TIMER0_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF)
+#define PRS_ASYNC_TIMER0_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0)
+#define PRS_ASYNC_TIMER0_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1)
+#define PRS_ASYNC_TIMER0_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2)
+#define PRS_ASYNC_TIMER1_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF)
+#define PRS_ASYNC_TIMER1_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF)
+#define PRS_ASYNC_TIMER1_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0)
+#define PRS_ASYNC_TIMER1_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1)
+#define PRS_ASYNC_TIMER1_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2)
+#define PRS_ASYNC_IADC0_SCANENTRYDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE)
+#define PRS_ASYNC_IADC0_SCANTABLEDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE)
+#define PRS_ASYNC_IADC0_SINGLEDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE)
+#define PRS_ASYNC_LETIMER0_CH0 (PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0)
+#define PRS_ASYNC_LETIMER0_CH1 (PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1)
+#define PRS_ASYNC_BURTC_COMP (PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC | PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP)
+#define PRS_ASYNC_BURTC_OVERFLOW (PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC | PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW)
+#define PRS_ASYNC_GPIO_PIN0 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0)
+#define PRS_ASYNC_GPIO_PIN1 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1)
+#define PRS_ASYNC_GPIO_PIN2 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2)
+#define PRS_ASYNC_GPIO_PIN3 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3)
+#define PRS_ASYNC_GPIO_PIN4 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4)
+#define PRS_ASYNC_GPIO_PIN5 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5)
+#define PRS_ASYNC_GPIO_PIN6 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6)
+#define PRS_ASYNC_GPIO_PIN7 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7)
+#define PRS_ASYNC_TIMER2_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF)
+#define PRS_ASYNC_TIMER2_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF)
+#define PRS_ASYNC_TIMER2_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0)
+#define PRS_ASYNC_TIMER2_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1)
+#define PRS_ASYNC_TIMER2_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2)
+#define PRS_ASYNC_TIMER3_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF)
+#define PRS_ASYNC_TIMER3_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF)
+#define PRS_ASYNC_TIMER3_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0)
+#define PRS_ASYNC_TIMER3_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1)
+#define PRS_ASYNC_TIMER3_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2)
+#define PRS_ASYNC_CORE_CTIOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0)
+#define PRS_ASYNC_CORE_CTIOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1)
+#define PRS_ASYNC_CORE_CTIOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2)
+#define PRS_ASYNC_CORE_CTIOUT3 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3)
+#define PRS_ASYNC_CMUL_CLKOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0)
+#define PRS_ASYNC_CMUL_CLKOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1)
+#define PRS_ASYNC_CMUL_CLKOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2)
+#define PRS_ASYNC_AGCL_CCA (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA)
+#define PRS_ASYNC_AGCL_CCAREQ (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ)
+#define PRS_ASYNC_AGCL_GAINADJUST (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST)
+#define PRS_ASYNC_AGCL_GAINOK (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK)
+#define PRS_ASYNC_AGCL_GAINREDUCED (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED)
+#define PRS_ASYNC_AGCL_IFPKI1 (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1)
+#define PRS_ASYNC_AGCL_IFPKQ2 (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2)
+#define PRS_ASYNC_AGCL_IFPKRST (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST)
+#define PRS_ASYNC_AGC_PEAKDET (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET)
+#define PRS_ASYNC_AGC_PROPAGATED (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED)
+#define PRS_ASYNC_AGC_RSSIDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE)
+#define PRS_ASYNC_BUFC_THR0 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0)
+#define PRS_ASYNC_BUFC_THR1 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1)
+#define PRS_ASYNC_BUFC_THR2 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2)
+#define PRS_ASYNC_BUFC_THR3 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3)
+#define PRS_ASYNC_BUFC_CNT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0)
+#define PRS_ASYNC_BUFC_CNT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1)
+#define PRS_ASYNC_BUFC_FULL (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL)
+#define PRS_ASYNC_MODEML_ADVANCE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE)
+#define PRS_ASYNC_MODEML_ANT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0)
+#define PRS_ASYNC_MODEML_ANT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1)
+#define PRS_ASYNC_MODEML_COHDSADET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET)
+#define PRS_ASYNC_MODEML_COHDSALIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE)
+#define PRS_ASYNC_MODEML_DCLK (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK)
+#define PRS_ASYNC_MODEML_DOUT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT)
+#define PRS_ASYNC_MODEML_FRAMEDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET)
+#define PRS_ASYNC_MODEM_FRAMESENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT)
+#define PRS_ASYNC_MODEM_LOWCORR (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR)
+#define PRS_ASYNC_MODEM_LRDSADET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET)
+#define PRS_ASYNC_MODEM_LRDSALIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE)
+#define PRS_ASYNC_MODEM_NEWSYMBOL (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL)
+#define PRS_ASYNC_MODEM_NEWWND (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND)
+#define PRS_ASYNC_MODEM_POSTPONE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE)
+#define PRS_ASYNC_MODEM_PREDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET)
+#define PRS_ASYNC_MODEMH_PRESENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT)
+#define PRS_ASYNC_MODEMH_RSSIJUMP (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP)
+#define PRS_ASYNC_MODEMH_SYNCSENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT)
+#define PRS_ASYNC_MODEMH_TIMDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET)
+#define PRS_ASYNC_MODEMH_WEAK (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK)
+#define PRS_ASYNC_MODEMH_EOF (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF)
+#define PRS_ASYNC_MODEMH_SI (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSI)
+#define PRS_ASYNC_FRC_DCLK (PRS_ASYNC_CH_CTRL_SOURCESEL_FRC | PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK)
+#define PRS_ASYNC_FRC_DOUT (PRS_ASYNC_CH_CTRL_SOURCESEL_FRC | PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT)
+#define PRS_ASYNC_PROTIMERL_BOF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF)
+#define PRS_ASYNC_PROTIMERL_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0)
+#define PRS_ASYNC_PROTIMERL_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1)
+#define PRS_ASYNC_PROTIMERL_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2)
+#define PRS_ASYNC_PROTIMERL_CC3 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3)
+#define PRS_ASYNC_PROTIMERL_CC4 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4)
+#define PRS_ASYNC_PROTIMERL_LBTF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF)
+#define PRS_ASYNC_PROTIMERL_LBTR (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR)
+#define PRS_ASYNC_PROTIMER_LBTS (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS)
+#define PRS_ASYNC_PROTIMER_POF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF)
+#define PRS_ASYNC_PROTIMER_T0MATCH (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH)
+#define PRS_ASYNC_PROTIMER_T0UF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF)
+#define PRS_ASYNC_PROTIMER_T1MATCH (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH)
+#define PRS_ASYNC_PROTIMER_T1UF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF)
+#define PRS_ASYNC_PROTIMER_WOF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF)
+#define PRS_ASYNC_SYNTH_MUX0 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH | PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0)
+#define PRS_ASYNC_SYNTH_MUX1 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH | PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1)
+#define PRS_ASYNC_PRSL_ASYNCH0 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0)
+#define PRS_ASYNC_PRSL_ASYNCH1 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1)
+#define PRS_ASYNC_PRSL_ASYNCH2 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2)
+#define PRS_ASYNC_PRSL_ASYNCH3 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3)
+#define PRS_ASYNC_PRSL_ASYNCH4 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4)
+#define PRS_ASYNC_PRSL_ASYNCH5 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5)
+#define PRS_ASYNC_PRSL_ASYNCH6 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6)
+#define PRS_ASYNC_PRSL_ASYNCH7 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7)
+#define PRS_ASYNC_PRS_ASYNCH8 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8)
+#define PRS_ASYNC_PRS_ASYNCH9 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9)
+#define PRS_ASYNC_PRS_ASYNCH10 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10)
+#define PRS_ASYNC_PRS_ASYNCH11 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11)
+#define PRS_ASYNC_RACL_ACTIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE)
+#define PRS_ASYNC_RACL_LNAEN (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN)
+#define PRS_ASYNC_RACL_PAEN (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN)
+#define PRS_ASYNC_RACL_RX (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX)
+#define PRS_ASYNC_RACL_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX)
+#define PRS_ASYNC_RACL_CTIOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0)
+#define PRS_ASYNC_RACL_CTIOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1)
+#define PRS_ASYNC_RACL_CTIOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2)
+#define PRS_ASYNC_RAC_CTIOUT3 (PRS_ASYNC_CH_CTRL_SOURCESEL_RAC | PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3)
+#define PRS_ASYNC_RAC_AUXADCDATA (PRS_ASYNC_CH_CTRL_SOURCESEL_RAC | PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA)
+#define PRS_ASYNC_RAC_AUXADCDATAVALID (PRS_ASYNC_CH_CTRL_SOURCESEL_RAC | PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID)
+#define PRS_ASYNC_TIMER4_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF)
+#define PRS_ASYNC_TIMER4_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF)
+#define PRS_ASYNC_TIMER4_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0)
+#define PRS_ASYNC_TIMER4_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1)
+#define PRS_ASYNC_TIMER4_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2)
+#define PRS_ASYNC_ACMP0_OUT (PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 | PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT)
+#define PRS_ASYNC_ACMP1_OUT (PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP1 | PRS_ASYNC_CH_CTRL_SIGSEL_ACMP1OUT)
+#define PRS_ASYNC_PCNT0_DIR (PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 | PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0DIR)
+#define PRS_ASYNC_PCNT0_UFOF (PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 | PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0UFOF)
+#define PRS_ASYNC_SYSRTC0_GRP0OUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 | PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT0)
+#define PRS_ASYNC_SYSRTC0_GRP0OUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 | PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT1)
+#define PRS_ASYNC_SYSRTC0_GRP1OUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 | PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT0)
+#define PRS_ASYNC_SYSRTC0_GRP1OUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 | PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT1)
+#define PRS_ASYNC_HFXO0L_STATUS (PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L | PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS)
+#define PRS_ASYNC_HFXO0L_STATUS1 (PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L | PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1)
+#define PRS_ASYNC_EUSART0L_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS)
+#define PRS_ASYNC_EUSART0L_IRDATX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX)
+#define PRS_ASYNC_EUSART0L_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS)
+#define PRS_ASYNC_EUSART0L_RXDATAV (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV)
+#define PRS_ASYNC_EUSART0L_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX)
+#define PRS_ASYNC_EUSART0L_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC)
+#define PRS_ASYNC_EUSART0L_RXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL)
+#define PRS_ASYNC_EUSART0L_TXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL)
+#define PRS_ASYNC_EUSART1L_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS)
+#define PRS_ASYNC_EUSART1L_IRDATX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX)
+#define PRS_ASYNC_EUSART1L_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS)
+#define PRS_ASYNC_EUSART1L_RXDATAV (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV)
+#define PRS_ASYNC_EUSART1L_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX)
+#define PRS_ASYNC_EUSART1L_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC)
+#define PRS_ASYNC_EUSART1L_RXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL)
+#define PRS_ASYNC_EUSART1L_TXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL)
+#define PRS_ASYNC_VDAC0L_CH0WARM (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0WARM)
+#define PRS_ASYNC_VDAC0L_CH1WARM (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1WARM)
+#define PRS_ASYNC_VDAC0L_CH0DONEASYNC (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC)
+#define PRS_ASYNC_VDAC0L_CH1DONEASYNC (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC)
+#define PRS_ASYNC_VDAC0L_INTERNALTIMEROF (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LINTERNALTIMEROF)
+#define PRS_ASYNC_VDAC0L_REFRESHTIMEROF (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LREFRESHTIMEROF)
+#define PRS_ASYNC_VDAC1L_CH0WARM (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0WARM)
+#define PRS_ASYNC_VDAC1L_CH1WARM (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1WARM)
+#define PRS_ASYNC_VDAC1L_CH0DONEASYNC (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0DONEASYNC)
+#define PRS_ASYNC_VDAC1L_CH1DONEASYNC (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1DONEASYNC)
+#define PRS_ASYNC_VDAC1L_INTERNALTIMEROF (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LINTERNALTIMEROF)
+#define PRS_ASYNC_VDAC1L_REFRESHTIMEROF (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LREFRESHTIMEROF)
+#define PRS_ASYNC_LFRCO_CALMEAS (PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO | PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS)
+#define PRS_ASYNC_LFRCO_SDM (PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO | PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM)
+#define PRS_ASYNC_LFRCO_TCMEAS (PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO | PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS)
+
+/**
+ * Asynchronous signals and sources combined and aligned with register bit fields
+ * without the '_ASYNCH_' infix in order for backward compatibility:
+ */
+#define PRS_USART0_CS (PRS_ASYNC_USART0_CS)
+#define PRS_USART0_IRTX (PRS_ASYNC_USART0_IRTX)
+#define PRS_USART0_RTS (PRS_ASYNC_USART0_RTS)
+#define PRS_USART0_RXDATA (PRS_ASYNC_USART0_RXDATA)
+#define PRS_USART0_TX (PRS_ASYNC_USART0_TX)
+#define PRS_USART0_TXC (PRS_ASYNC_USART0_TXC)
+#define PRS_TIMER0_UF (PRS_ASYNC_TIMER0_UF)
+#define PRS_TIMER0_OF (PRS_ASYNC_TIMER0_OF)
+#define PRS_TIMER0_CC0 (PRS_ASYNC_TIMER0_CC0)
+#define PRS_TIMER0_CC1 (PRS_ASYNC_TIMER0_CC1)
+#define PRS_TIMER0_CC2 (PRS_ASYNC_TIMER0_CC2)
+#define PRS_TIMER1_UF (PRS_ASYNC_TIMER1_UF)
+#define PRS_TIMER1_OF (PRS_ASYNC_TIMER1_OF)
+#define PRS_TIMER1_CC0 (PRS_ASYNC_TIMER1_CC0)
+#define PRS_TIMER1_CC1 (PRS_ASYNC_TIMER1_CC1)
+#define PRS_TIMER1_CC2 (PRS_ASYNC_TIMER1_CC2)
+#define PRS_IADC0_SCANENTRYDONE (PRS_ASYNC_IADC0_SCANENTRYDONE)
+#define PRS_IADC0_SCANTABLEDONE (PRS_ASYNC_IADC0_SCANTABLEDONE)
+#define PRS_IADC0_SINGLEDONE (PRS_ASYNC_IADC0_SINGLEDONE)
+#define PRS_LETIMER0_CH0 (PRS_ASYNC_LETIMER0_CH0)
+#define PRS_LETIMER0_CH1 (PRS_ASYNC_LETIMER0_CH1)
+#define PRS_BURTC_COMP (PRS_ASYNC_BURTC_COMP)
+#define PRS_BURTC_OVERFLOW (PRS_ASYNC_BURTC_OVERFLOW)
+#define PRS_GPIO_PIN0 (PRS_ASYNC_GPIO_PIN0)
+#define PRS_GPIO_PIN1 (PRS_ASYNC_GPIO_PIN1)
+#define PRS_GPIO_PIN2 (PRS_ASYNC_GPIO_PIN2)
+#define PRS_GPIO_PIN3 (PRS_ASYNC_GPIO_PIN3)
+#define PRS_GPIO_PIN4 (PRS_ASYNC_GPIO_PIN4)
+#define PRS_GPIO_PIN5 (PRS_ASYNC_GPIO_PIN5)
+#define PRS_GPIO_PIN6 (PRS_ASYNC_GPIO_PIN6)
+#define PRS_GPIO_PIN7 (PRS_ASYNC_GPIO_PIN7)
+#define PRS_TIMER2_UF (PRS_ASYNC_TIMER2_UF)
+#define PRS_TIMER2_OF (PRS_ASYNC_TIMER2_OF)
+#define PRS_TIMER2_CC0 (PRS_ASYNC_TIMER2_CC0)
+#define PRS_TIMER2_CC1 (PRS_ASYNC_TIMER2_CC1)
+#define PRS_TIMER2_CC2 (PRS_ASYNC_TIMER2_CC2)
+#define PRS_TIMER3_UF (PRS_ASYNC_TIMER3_UF)
+#define PRS_TIMER3_OF (PRS_ASYNC_TIMER3_OF)
+#define PRS_TIMER3_CC0 (PRS_ASYNC_TIMER3_CC0)
+#define PRS_TIMER3_CC1 (PRS_ASYNC_TIMER3_CC1)
+#define PRS_TIMER3_CC2 (PRS_ASYNC_TIMER3_CC2)
+#define PRS_CORE_CTIOUT0 (PRS_ASYNC_CORE_CTIOUT0)
+#define PRS_CORE_CTIOUT1 (PRS_ASYNC_CORE_CTIOUT1)
+#define PRS_CORE_CTIOUT2 (PRS_ASYNC_CORE_CTIOUT2)
+#define PRS_CORE_CTIOUT3 (PRS_ASYNC_CORE_CTIOUT3)
+#define PRS_CMUL_CLKOUT0 (PRS_ASYNC_CMUL_CLKOUT0)
+#define PRS_CMUL_CLKOUT1 (PRS_ASYNC_CMUL_CLKOUT1)
+#define PRS_CMUL_CLKOUT2 (PRS_ASYNC_CMUL_CLKOUT2)
+#define PRS_AGCL_CCA (PRS_ASYNC_AGCL_CCA)
+#define PRS_AGCL_CCAREQ (PRS_ASYNC_AGCL_CCAREQ)
+#define PRS_AGCL_GAINADJUST (PRS_ASYNC_AGCL_GAINADJUST)
+#define PRS_AGCL_GAINOK (PRS_ASYNC_AGCL_GAINOK)
+#define PRS_AGCL_GAINREDUCED (PRS_ASYNC_AGCL_GAINREDUCED)
+#define PRS_AGCL_IFPKI1 (PRS_ASYNC_AGCL_IFPKI1)
+#define PRS_AGCL_IFPKQ2 (PRS_ASYNC_AGCL_IFPKQ2)
+#define PRS_AGCL_IFPKRST (PRS_ASYNC_AGCL_IFPKRST)
+#define PRS_AGC_PEAKDET (PRS_ASYNC_AGC_PEAKDET)
+#define PRS_AGC_PROPAGATED (PRS_ASYNC_AGC_PROPAGATED)
+#define PRS_AGC_RSSIDONE (PRS_ASYNC_AGC_RSSIDONE)
+#define PRS_BUFC_THR0 (PRS_ASYNC_BUFC_THR0)
+#define PRS_BUFC_THR1 (PRS_ASYNC_BUFC_THR1)
+#define PRS_BUFC_THR2 (PRS_ASYNC_BUFC_THR2)
+#define PRS_BUFC_THR3 (PRS_ASYNC_BUFC_THR3)
+#define PRS_BUFC_CNT0 (PRS_ASYNC_BUFC_CNT0)
+#define PRS_BUFC_CNT1 (PRS_ASYNC_BUFC_CNT1)
+#define PRS_BUFC_FULL (PRS_ASYNC_BUFC_FULL)
+#define PRS_MODEML_ADVANCE (PRS_ASYNC_MODEML_ADVANCE)
+#define PRS_MODEML_ANT0 (PRS_ASYNC_MODEML_ANT0)
+#define PRS_MODEML_ANT1 (PRS_ASYNC_MODEML_ANT1)
+#define PRS_MODEML_COHDSADET (PRS_ASYNC_MODEML_COHDSADET)
+#define PRS_MODEML_COHDSALIVE (PRS_ASYNC_MODEML_COHDSALIVE)
+#define PRS_MODEML_DCLK (PRS_ASYNC_MODEML_DCLK)
+#define PRS_MODEML_DOUT (PRS_ASYNC_MODEML_DOUT)
+#define PRS_MODEML_FRAMEDET (PRS_ASYNC_MODEML_FRAMEDET)
+#define PRS_MODEM_FRAMESENT (PRS_ASYNC_MODEM_FRAMESENT)
+#define PRS_MODEM_LOWCORR (PRS_ASYNC_MODEM_LOWCORR)
+#define PRS_MODEM_LRDSADET (PRS_ASYNC_MODEM_LRDSADET)
+#define PRS_MODEM_LRDSALIVE (PRS_ASYNC_MODEM_LRDSALIVE)
+#define PRS_MODEM_NEWSYMBOL (PRS_ASYNC_MODEM_NEWSYMBOL)
+#define PRS_MODEM_NEWWND (PRS_ASYNC_MODEM_NEWWND)
+#define PRS_MODEM_POSTPONE (PRS_ASYNC_MODEM_POSTPONE)
+#define PRS_MODEM_PREDET (PRS_ASYNC_MODEM_PREDET)
+#define PRS_MODEMH_PRESENT (PRS_ASYNC_MODEMH_PRESENT)
+#define PRS_MODEMH_RSSIJUMP (PRS_ASYNC_MODEMH_RSSIJUMP)
+#define PRS_MODEMH_SYNCSENT (PRS_ASYNC_MODEMH_SYNCSENT)
+#define PRS_MODEMH_TIMDET (PRS_ASYNC_MODEMH_TIMDET)
+#define PRS_MODEMH_WEAK (PRS_ASYNC_MODEMH_WEAK)
+#define PRS_MODEMH_EOF (PRS_ASYNC_MODEMH_EOF)
+#define PRS_MODEMH_SI (PRS_ASYNC_MODEMH_SI)
+#define PRS_FRC_DCLK (PRS_ASYNC_FRC_DCLK)
+#define PRS_FRC_DOUT (PRS_ASYNC_FRC_DOUT)
+#define PRS_PROTIMERL_BOF (PRS_ASYNC_PROTIMERL_BOF)
+#define PRS_PROTIMERL_CC0 (PRS_ASYNC_PROTIMERL_CC0)
+#define PRS_PROTIMERL_CC1 (PRS_ASYNC_PROTIMERL_CC1)
+#define PRS_PROTIMERL_CC2 (PRS_ASYNC_PROTIMERL_CC2)
+#define PRS_PROTIMERL_CC3 (PRS_ASYNC_PROTIMERL_CC3)
+#define PRS_PROTIMERL_CC4 (PRS_ASYNC_PROTIMERL_CC4)
+#define PRS_PROTIMERL_LBTF (PRS_ASYNC_PROTIMERL_LBTF)
+#define PRS_PROTIMERL_LBTR (PRS_ASYNC_PROTIMERL_LBTR)
+#define PRS_PROTIMER_LBTS (PRS_ASYNC_PROTIMER_LBTS)
+#define PRS_PROTIMER_POF (PRS_ASYNC_PROTIMER_POF)
+#define PRS_PROTIMER_T0MATCH (PRS_ASYNC_PROTIMER_T0MATCH)
+#define PRS_PROTIMER_T0UF (PRS_ASYNC_PROTIMER_T0UF)
+#define PRS_PROTIMER_T1MATCH (PRS_ASYNC_PROTIMER_T1MATCH)
+#define PRS_PROTIMER_T1UF (PRS_ASYNC_PROTIMER_T1UF)
+#define PRS_PROTIMER_WOF (PRS_ASYNC_PROTIMER_WOF)
+#define PRS_SYNTH_MUX0 (PRS_ASYNC_SYNTH_MUX0)
+#define PRS_SYNTH_MUX1 (PRS_ASYNC_SYNTH_MUX1)
+#define PRS_PRSL_ASYNCH0 (PRS_ASYNC_PRSL_ASYNCH0)
+#define PRS_PRSL_ASYNCH1 (PRS_ASYNC_PRSL_ASYNCH1)
+#define PRS_PRSL_ASYNCH2 (PRS_ASYNC_PRSL_ASYNCH2)
+#define PRS_PRSL_ASYNCH3 (PRS_ASYNC_PRSL_ASYNCH3)
+#define PRS_PRSL_ASYNCH4 (PRS_ASYNC_PRSL_ASYNCH4)
+#define PRS_PRSL_ASYNCH5 (PRS_ASYNC_PRSL_ASYNCH5)
+#define PRS_PRSL_ASYNCH6 (PRS_ASYNC_PRSL_ASYNCH6)
+#define PRS_PRSL_ASYNCH7 (PRS_ASYNC_PRSL_ASYNCH7)
+#define PRS_PRS_ASYNCH8 (PRS_ASYNC_PRS_ASYNCH8)
+#define PRS_PRS_ASYNCH9 (PRS_ASYNC_PRS_ASYNCH9)
+#define PRS_PRS_ASYNCH10 (PRS_ASYNC_PRS_ASYNCH10)
+#define PRS_PRS_ASYNCH11 (PRS_ASYNC_PRS_ASYNCH11)
+#define PRS_RACL_ACTIVE (PRS_ASYNC_RACL_ACTIVE)
+#define PRS_RACL_LNAEN (PRS_ASYNC_RACL_LNAEN)
+#define PRS_RACL_PAEN (PRS_ASYNC_RACL_PAEN)
+#define PRS_RACL_RX (PRS_ASYNC_RACL_RX)
+#define PRS_RACL_TX (PRS_ASYNC_RACL_TX)
+#define PRS_RACL_CTIOUT0 (PRS_ASYNC_RACL_CTIOUT0)
+#define PRS_RACL_CTIOUT1 (PRS_ASYNC_RACL_CTIOUT1)
+#define PRS_RACL_CTIOUT2 (PRS_ASYNC_RACL_CTIOUT2)
+#define PRS_RAC_CTIOUT3 (PRS_ASYNC_RAC_CTIOUT3)
+#define PRS_RAC_AUXADCDATA (PRS_ASYNC_RAC_AUXADCDATA)
+#define PRS_RAC_AUXADCDATAVALID (PRS_ASYNC_RAC_AUXADCDATAVALID)
+#define PRS_TIMER4_UF (PRS_ASYNC_TIMER4_UF)
+#define PRS_TIMER4_OF (PRS_ASYNC_TIMER4_OF)
+#define PRS_TIMER4_CC0 (PRS_ASYNC_TIMER4_CC0)
+#define PRS_TIMER4_CC1 (PRS_ASYNC_TIMER4_CC1)
+#define PRS_TIMER4_CC2 (PRS_ASYNC_TIMER4_CC2)
+#define PRS_ACMP0_OUT (PRS_ASYNC_ACMP0_OUT)
+#define PRS_ACMP1_OUT (PRS_ASYNC_ACMP1_OUT)
+#define PRS_PCNT0_DIR (PRS_ASYNC_PCNT0_DIR)
+#define PRS_PCNT0_UFOF (PRS_ASYNC_PCNT0_UFOF)
+#define PRS_SYSRTC0_GRP0OUT0 (PRS_ASYNC_SYSRTC0_GRP0OUT0)
+#define PRS_SYSRTC0_GRP0OUT1 (PRS_ASYNC_SYSRTC0_GRP0OUT1)
+#define PRS_SYSRTC0_GRP1OUT0 (PRS_ASYNC_SYSRTC0_GRP1OUT0)
+#define PRS_SYSRTC0_GRP1OUT1 (PRS_ASYNC_SYSRTC0_GRP1OUT1)
+#define PRS_HFXO0L_STATUS (PRS_ASYNC_HFXO0L_STATUS)
+#define PRS_HFXO0L_STATUS1 (PRS_ASYNC_HFXO0L_STATUS1)
+#define PRS_EUSART0L_CS (PRS_ASYNC_EUSART0L_CS)
+#define PRS_EUSART0L_IRDATX (PRS_ASYNC_EUSART0L_IRDATX)
+#define PRS_EUSART0L_RTS (PRS_ASYNC_EUSART0L_RTS)
+#define PRS_EUSART0L_RXDATAV (PRS_ASYNC_EUSART0L_RXDATAV)
+#define PRS_EUSART0L_TX (PRS_ASYNC_EUSART0L_TX)
+#define PRS_EUSART0L_TXC (PRS_ASYNC_EUSART0L_TXC)
+#define PRS_EUSART0L_RXFL (PRS_ASYNC_EUSART0L_RXFL)
+#define PRS_EUSART0L_TXFL (PRS_ASYNC_EUSART0L_TXFL)
+#define PRS_EUSART1L_CS (PRS_ASYNC_EUSART1L_CS)
+#define PRS_EUSART1L_IRDATX (PRS_ASYNC_EUSART1L_IRDATX)
+#define PRS_EUSART1L_RTS (PRS_ASYNC_EUSART1L_RTS)
+#define PRS_EUSART1L_RXDATAV (PRS_ASYNC_EUSART1L_RXDATAV)
+#define PRS_EUSART1L_TX (PRS_ASYNC_EUSART1L_TX)
+#define PRS_EUSART1L_TXC (PRS_ASYNC_EUSART1L_TXC)
+#define PRS_EUSART1L_RXFL (PRS_ASYNC_EUSART1L_RXFL)
+#define PRS_EUSART1L_TXFL (PRS_ASYNC_EUSART1L_TXFL)
+#define PRS_VDAC0L_CH0WARM (PRS_ASYNC_VDAC0L_CH0WARM)
+#define PRS_VDAC0L_CH1WARM (PRS_ASYNC_VDAC0L_CH1WARM)
+#define PRS_VDAC0L_CH0DONEASYNC (PRS_ASYNC_VDAC0L_CH0DONEASYNC)
+#define PRS_VDAC0L_CH1DONEASYNC (PRS_ASYNC_VDAC0L_CH1DONEASYNC)
+#define PRS_VDAC0L_INTERNALTIMEROF (PRS_ASYNC_VDAC0L_INTERNALTIMEROF)
+#define PRS_VDAC0L_REFRESHTIMEROF (PRS_ASYNC_VDAC0L_REFRESHTIMEROF)
+#define PRS_VDAC1L_CH0WARM (PRS_ASYNC_VDAC1L_CH0WARM)
+#define PRS_VDAC1L_CH1WARM (PRS_ASYNC_VDAC1L_CH1WARM)
+#define PRS_VDAC1L_CH0DONEASYNC (PRS_ASYNC_VDAC1L_CH0DONEASYNC)
+#define PRS_VDAC1L_CH1DONEASYNC (PRS_ASYNC_VDAC1L_CH1DONEASYNC)
+#define PRS_VDAC1L_INTERNALTIMEROF (PRS_ASYNC_VDAC1L_INTERNALTIMEROF)
+#define PRS_VDAC1L_REFRESHTIMEROF (PRS_ASYNC_VDAC1L_REFRESHTIMEROF)
+#define PRS_LFRCO_CALMEAS (PRS_ASYNC_LFRCO_CALMEAS)
+#define PRS_LFRCO_SDM (PRS_ASYNC_LFRCO_SDM)
+#define PRS_LFRCO_TCMEAS (PRS_ASYNC_LFRCO_TCMEAS)
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_rac.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_rac.h
new file mode 100644
index 00000000..a45313f6
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_rac.h
@@ -0,0 +1,5773 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 RAC register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_RAC_H
+#define EFR32MG24_RAC_H
+#define RAC_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_RAC RAC
+ * @{
+ * @brief EFR32MG24 RAC Register Declaration.
+ *****************************************************************************/
+
+/** RAC Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IP Version */
+ __IOM uint32_t EN; /**< Enable peripheral clock to this module */
+ __IOM uint32_t RXENSRCEN; /**< RXEN Source Enable */
+ __IM uint32_t STATUS; /**< Radio State Machine Status */
+ __IOM uint32_t CMD; /**< Radio Commands */
+ __IOM uint32_t CTRL; /**< Radio Control Register */
+ __IOM uint32_t FORCESTATE; /**< Force state transition */
+ __IOM uint32_t IF; /**< Radio Controller Interrupt Flags */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IOM uint32_t TESTCTRL; /**< Test Control Register */
+ __IOM uint32_t SEQIF; /**< SEQ Interrupt Flags */
+ __IOM uint32_t SEQIEN; /**< SEQ Interrupt Enable Register */
+ __IM uint32_t STATUS1; /**< Radio State Machine Status */
+ __IM uint32_t STIMER; /**< Sequencer Timer Value */
+ __IOM uint32_t STIMERCOMP; /**< Sequencer Timer Compare Value */
+ __IOM uint32_t SEQCTRL; /**< Sequencer Control Register */
+ __IOM uint32_t PRESC; /**< Sequencer prescaler Register */
+ __IOM uint32_t SR0; /**< Storage Register 0 */
+ __IOM uint32_t SR1; /**< Storage Register 1 */
+ __IOM uint32_t SR2; /**< Storage Register 2 */
+ __IOM uint32_t SR3; /**< Storage Register 3 */
+ __IOM uint32_t STCTRL; /**< Sys tick timer Control Register */
+ __IOM uint32_t FRCTXWORD; /**< FRC wordbuffer write */
+ __IM uint32_t FRCRXWORD; /**< FRC wordbuffer read */
+ __IOM uint32_t EM1PCSR; /**< Radio EM1P Control and Status Register */
+ uint32_t RESERVED0[13U]; /**< Reserved for future use */
+ __IOM uint32_t SYNTHENCTRL; /**< Synthesizer Enable Control Register */
+ __IOM uint32_t SYNTHREGCTRL; /**< Synthesizer Regulator Enable Control */
+ __IOM uint32_t VCOCTRL; /**< VCO Control Register */
+ uint32_t RESERVED1[2U]; /**< Reserved for future use */
+ uint32_t RESERVED2[1U]; /**< Reserved for future use */
+ __IM uint32_t STATUS2; /**< Radio State Machine Status 2 */
+ __IOM uint32_t IFPGACTRL; /**< IF PGA Control Register */
+ __IOM uint32_t PAENCTRL; /**< PA Enable Control Register */
+ __IOM uint32_t APC; /**< Automatic Power Control Register */
+ __IOM uint32_t ANTDIV; /**< ANTDIV */
+ __IOM uint32_t AUXADCTRIM; /**< AUXADCTRIM */
+ __IOM uint32_t AUXADCEN; /**< AUXADCEN */
+ __IOM uint32_t AUXADCCTRL0; /**< Auxiliary ADC register control */
+ __IOM uint32_t AUXADCCTRL1; /**< AUXADCCTRL1 */
+ __IM uint32_t AUXADCOUT; /**< Auxiliary ADC digital output */
+ __IOM uint32_t CLKMULTEN0; /**< CLKMULTEN0 */
+ __IOM uint32_t CLKMULTEN1; /**< CLKMULTEN1 */
+ __IOM uint32_t CLKMULTCTRL; /**< CLKMULTCTRL */
+ __IM uint32_t CLKMULTSTATUS; /**< CLKMULTSTATUS */
+ uint32_t RESERVED3[1U]; /**< Reserved for future use */
+ __IOM uint32_t IFADCTRIM0; /**< IFADCTRIM0 */
+ __IOM uint32_t IFADCTRIM1; /**< IFADCTRIM1 */
+ __IOM uint32_t IFADCCAL; /**< IFADCCAL */
+ __IM uint32_t IFADCSTATUS; /**< IFADCSTATUS */
+ uint32_t RESERVED4[1U]; /**< Reserved for future use */
+ __IOM uint32_t LNAMIXTRIM0; /**< LNAMIXTRIM0 */
+ __IOM uint32_t LNAMIXTRIM1; /**< LNAMIXTRIM1 */
+ __IOM uint32_t LNAMIXTRIM2; /**< LNAMIXTRIM2 */
+ __IOM uint32_t LNAMIXTRIM3; /**< LNAMIXTRIM3 */
+ __IOM uint32_t LNAMIXTRIM4; /**< LNAMIXTRIM4 */
+ __IOM uint32_t LNAMIXCAL; /**< LNAMIXCAL */
+ __IOM uint32_t LNAMIXEN; /**< LNAMIXEN */
+ __IOM uint32_t PRECTRL; /**< PRECTRL */
+ __IOM uint32_t PATRIM0; /**< PATRIM0 */
+ __IOM uint32_t PATRIM1; /**< PATRIM1 */
+ __IOM uint32_t PATRIM2; /**< PATRIM2 */
+ __IOM uint32_t PATRIM3; /**< PATRIM3 */
+ __IOM uint32_t PATRIM4; /**< PATRIM4 */
+ __IOM uint32_t PATRIM5; /**< PATRIM5 */
+ uint32_t RESERVED5[1U]; /**< Reserved for future use */
+ __IOM uint32_t TXPOWER; /**< TXPOWER */
+ __IOM uint32_t TXRAMP; /**< TXRAMP */
+ uint32_t RESERVED6[1U]; /**< Reserved for future use */
+ __IOM uint32_t PGATRIM; /**< PGATRIM */
+ __IOM uint32_t PGACAL; /**< PGACAL */
+ __IOM uint32_t PGACTRL; /**< PGACTRL */
+ __IOM uint32_t RFBIASCAL; /**< RFBIASCAL */
+ __IOM uint32_t RFBIASCTRL; /**< RFBIASCTRL */
+ __IOM uint32_t RADIOEN; /**< RADIOEN */
+ __IOM uint32_t RFPATHEN0; /**< RFPATHEN0 */
+ __IOM uint32_t RFPATHEN1; /**< RFPATHEN1 */
+ __IOM uint32_t RX; /**< RX */
+ __IOM uint32_t TX; /**< TX */
+ uint32_t RESERVED7[1U]; /**< Reserved for future use */
+ __IOM uint32_t SYTRIM0; /**< SYTRIM0 */
+ __IOM uint32_t SYTRIM1; /**< SYTRIM1 */
+ __IOM uint32_t SYCAL; /**< SYCAL */
+ __IOM uint32_t SYEN; /**< SYEN */
+ __IOM uint32_t SYLOEN; /**< SYLOEN */
+ __IOM uint32_t SYMMDCTRL; /**< SYMMDCTRL */
+ uint32_t RESERVED8[1U]; /**< Reserved for future use */
+ __IOM uint32_t DIGCLKRETIMECTRL; /**< DIGCLKRETIMECTRL */
+ __IM uint32_t DIGCLKRETIMESTATUS; /**< DIGCLKRETIMESTATUS */
+ __IOM uint32_t XORETIMECTRL; /**< XORETIMECTRL */
+ __IM uint32_t XORETIMESTATUS; /**< XORETIMESTATUS */
+ __IOM uint32_t AGCOVERWRITE0; /**< OVERWRITE AGC */
+ __IOM uint32_t AGCOVERWRITE1; /**< OVERWRITE AGC */
+ __IOM uint32_t AGCOVERWRITE2; /**< OVERWRITE AGC */
+ uint32_t RESERVED9[7U]; /**< Reserved for future use */
+ __IOM uint32_t PACTRL; /**< PACTRL */
+ __IOM uint32_t FENOTCH0; /**< FENOTCH0 */
+ __IOM uint32_t FENOTCH1; /**< FENOTCH1 */
+ uint32_t RESERVED10[131U]; /**< Reserved for future use */
+ __IOM uint32_t SCRATCH0; /**< SCRATCH0 */
+ __IOM uint32_t SCRATCH1; /**< SCRATCH1 */
+ __IOM uint32_t SCRATCH2; /**< SCRATCH2 */
+ __IOM uint32_t SCRATCH3; /**< SCRATCH3 */
+ __IOM uint32_t SCRATCH4; /**< SCRATCH4 */
+ __IOM uint32_t SCRATCH5; /**< SCRATCH5 */
+ __IOM uint32_t SCRATCH6; /**< SCRATCH6 */
+ __IOM uint32_t SCRATCH7; /**< SCRATCH7 */
+ uint32_t RESERVED11[250U]; /**< Reserved for future use */
+ __IOM uint32_t THMSW; /**< Thermister control */
+ uint32_t RESERVED12[1U]; /**< Reserved for future use */
+ uint32_t RESERVED13[2U]; /**< Reserved for future use */
+ uint32_t RESERVED14[1U]; /**< Reserved for future use */
+ uint32_t RESERVED15[513U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP Version */
+ __IOM uint32_t EN_SET; /**< Enable peripheral clock to this module */
+ __IOM uint32_t RXENSRCEN_SET; /**< RXEN Source Enable */
+ __IM uint32_t STATUS_SET; /**< Radio State Machine Status */
+ __IOM uint32_t CMD_SET; /**< Radio Commands */
+ __IOM uint32_t CTRL_SET; /**< Radio Control Register */
+ __IOM uint32_t FORCESTATE_SET; /**< Force state transition */
+ __IOM uint32_t IF_SET; /**< Radio Controller Interrupt Flags */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
+ __IOM uint32_t TESTCTRL_SET; /**< Test Control Register */
+ __IOM uint32_t SEQIF_SET; /**< SEQ Interrupt Flags */
+ __IOM uint32_t SEQIEN_SET; /**< SEQ Interrupt Enable Register */
+ __IM uint32_t STATUS1_SET; /**< Radio State Machine Status */
+ __IM uint32_t STIMER_SET; /**< Sequencer Timer Value */
+ __IOM uint32_t STIMERCOMP_SET; /**< Sequencer Timer Compare Value */
+ __IOM uint32_t SEQCTRL_SET; /**< Sequencer Control Register */
+ __IOM uint32_t PRESC_SET; /**< Sequencer prescaler Register */
+ __IOM uint32_t SR0_SET; /**< Storage Register 0 */
+ __IOM uint32_t SR1_SET; /**< Storage Register 1 */
+ __IOM uint32_t SR2_SET; /**< Storage Register 2 */
+ __IOM uint32_t SR3_SET; /**< Storage Register 3 */
+ __IOM uint32_t STCTRL_SET; /**< Sys tick timer Control Register */
+ __IOM uint32_t FRCTXWORD_SET; /**< FRC wordbuffer write */
+ __IM uint32_t FRCRXWORD_SET; /**< FRC wordbuffer read */
+ __IOM uint32_t EM1PCSR_SET; /**< Radio EM1P Control and Status Register */
+ uint32_t RESERVED16[13U]; /**< Reserved for future use */
+ __IOM uint32_t SYNTHENCTRL_SET; /**< Synthesizer Enable Control Register */
+ __IOM uint32_t SYNTHREGCTRL_SET; /**< Synthesizer Regulator Enable Control */
+ __IOM uint32_t VCOCTRL_SET; /**< VCO Control Register */
+ uint32_t RESERVED17[2U]; /**< Reserved for future use */
+ uint32_t RESERVED18[1U]; /**< Reserved for future use */
+ __IM uint32_t STATUS2_SET; /**< Radio State Machine Status 2 */
+ __IOM uint32_t IFPGACTRL_SET; /**< IF PGA Control Register */
+ __IOM uint32_t PAENCTRL_SET; /**< PA Enable Control Register */
+ __IOM uint32_t APC_SET; /**< Automatic Power Control Register */
+ __IOM uint32_t ANTDIV_SET; /**< ANTDIV */
+ __IOM uint32_t AUXADCTRIM_SET; /**< AUXADCTRIM */
+ __IOM uint32_t AUXADCEN_SET; /**< AUXADCEN */
+ __IOM uint32_t AUXADCCTRL0_SET; /**< Auxiliary ADC register control */
+ __IOM uint32_t AUXADCCTRL1_SET; /**< AUXADCCTRL1 */
+ __IM uint32_t AUXADCOUT_SET; /**< Auxiliary ADC digital output */
+ __IOM uint32_t CLKMULTEN0_SET; /**< CLKMULTEN0 */
+ __IOM uint32_t CLKMULTEN1_SET; /**< CLKMULTEN1 */
+ __IOM uint32_t CLKMULTCTRL_SET; /**< CLKMULTCTRL */
+ __IM uint32_t CLKMULTSTATUS_SET; /**< CLKMULTSTATUS */
+ uint32_t RESERVED19[1U]; /**< Reserved for future use */
+ __IOM uint32_t IFADCTRIM0_SET; /**< IFADCTRIM0 */
+ __IOM uint32_t IFADCTRIM1_SET; /**< IFADCTRIM1 */
+ __IOM uint32_t IFADCCAL_SET; /**< IFADCCAL */
+ __IM uint32_t IFADCSTATUS_SET; /**< IFADCSTATUS */
+ uint32_t RESERVED20[1U]; /**< Reserved for future use */
+ __IOM uint32_t LNAMIXTRIM0_SET; /**< LNAMIXTRIM0 */
+ __IOM uint32_t LNAMIXTRIM1_SET; /**< LNAMIXTRIM1 */
+ __IOM uint32_t LNAMIXTRIM2_SET; /**< LNAMIXTRIM2 */
+ __IOM uint32_t LNAMIXTRIM3_SET; /**< LNAMIXTRIM3 */
+ __IOM uint32_t LNAMIXTRIM4_SET; /**< LNAMIXTRIM4 */
+ __IOM uint32_t LNAMIXCAL_SET; /**< LNAMIXCAL */
+ __IOM uint32_t LNAMIXEN_SET; /**< LNAMIXEN */
+ __IOM uint32_t PRECTRL_SET; /**< PRECTRL */
+ __IOM uint32_t PATRIM0_SET; /**< PATRIM0 */
+ __IOM uint32_t PATRIM1_SET; /**< PATRIM1 */
+ __IOM uint32_t PATRIM2_SET; /**< PATRIM2 */
+ __IOM uint32_t PATRIM3_SET; /**< PATRIM3 */
+ __IOM uint32_t PATRIM4_SET; /**< PATRIM4 */
+ __IOM uint32_t PATRIM5_SET; /**< PATRIM5 */
+ uint32_t RESERVED21[1U]; /**< Reserved for future use */
+ __IOM uint32_t TXPOWER_SET; /**< TXPOWER */
+ __IOM uint32_t TXRAMP_SET; /**< TXRAMP */
+ uint32_t RESERVED22[1U]; /**< Reserved for future use */
+ __IOM uint32_t PGATRIM_SET; /**< PGATRIM */
+ __IOM uint32_t PGACAL_SET; /**< PGACAL */
+ __IOM uint32_t PGACTRL_SET; /**< PGACTRL */
+ __IOM uint32_t RFBIASCAL_SET; /**< RFBIASCAL */
+ __IOM uint32_t RFBIASCTRL_SET; /**< RFBIASCTRL */
+ __IOM uint32_t RADIOEN_SET; /**< RADIOEN */
+ __IOM uint32_t RFPATHEN0_SET; /**< RFPATHEN0 */
+ __IOM uint32_t RFPATHEN1_SET; /**< RFPATHEN1 */
+ __IOM uint32_t RX_SET; /**< RX */
+ __IOM uint32_t TX_SET; /**< TX */
+ uint32_t RESERVED23[1U]; /**< Reserved for future use */
+ __IOM uint32_t SYTRIM0_SET; /**< SYTRIM0 */
+ __IOM uint32_t SYTRIM1_SET; /**< SYTRIM1 */
+ __IOM uint32_t SYCAL_SET; /**< SYCAL */
+ __IOM uint32_t SYEN_SET; /**< SYEN */
+ __IOM uint32_t SYLOEN_SET; /**< SYLOEN */
+ __IOM uint32_t SYMMDCTRL_SET; /**< SYMMDCTRL */
+ uint32_t RESERVED24[1U]; /**< Reserved for future use */
+ __IOM uint32_t DIGCLKRETIMECTRL_SET; /**< DIGCLKRETIMECTRL */
+ __IM uint32_t DIGCLKRETIMESTATUS_SET; /**< DIGCLKRETIMESTATUS */
+ __IOM uint32_t XORETIMECTRL_SET; /**< XORETIMECTRL */
+ __IM uint32_t XORETIMESTATUS_SET; /**< XORETIMESTATUS */
+ __IOM uint32_t AGCOVERWRITE0_SET; /**< OVERWRITE AGC */
+ __IOM uint32_t AGCOVERWRITE1_SET; /**< OVERWRITE AGC */
+ __IOM uint32_t AGCOVERWRITE2_SET; /**< OVERWRITE AGC */
+ uint32_t RESERVED25[7U]; /**< Reserved for future use */
+ __IOM uint32_t PACTRL_SET; /**< PACTRL */
+ __IOM uint32_t FENOTCH0_SET; /**< FENOTCH0 */
+ __IOM uint32_t FENOTCH1_SET; /**< FENOTCH1 */
+ uint32_t RESERVED26[131U]; /**< Reserved for future use */
+ __IOM uint32_t SCRATCH0_SET; /**< SCRATCH0 */
+ __IOM uint32_t SCRATCH1_SET; /**< SCRATCH1 */
+ __IOM uint32_t SCRATCH2_SET; /**< SCRATCH2 */
+ __IOM uint32_t SCRATCH3_SET; /**< SCRATCH3 */
+ __IOM uint32_t SCRATCH4_SET; /**< SCRATCH4 */
+ __IOM uint32_t SCRATCH5_SET; /**< SCRATCH5 */
+ __IOM uint32_t SCRATCH6_SET; /**< SCRATCH6 */
+ __IOM uint32_t SCRATCH7_SET; /**< SCRATCH7 */
+ uint32_t RESERVED27[250U]; /**< Reserved for future use */
+ __IOM uint32_t THMSW_SET; /**< Thermister control */
+ uint32_t RESERVED28[1U]; /**< Reserved for future use */
+ uint32_t RESERVED29[2U]; /**< Reserved for future use */
+ uint32_t RESERVED30[1U]; /**< Reserved for future use */
+ uint32_t RESERVED31[513U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP Version */
+ __IOM uint32_t EN_CLR; /**< Enable peripheral clock to this module */
+ __IOM uint32_t RXENSRCEN_CLR; /**< RXEN Source Enable */
+ __IM uint32_t STATUS_CLR; /**< Radio State Machine Status */
+ __IOM uint32_t CMD_CLR; /**< Radio Commands */
+ __IOM uint32_t CTRL_CLR; /**< Radio Control Register */
+ __IOM uint32_t FORCESTATE_CLR; /**< Force state transition */
+ __IOM uint32_t IF_CLR; /**< Radio Controller Interrupt Flags */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
+ __IOM uint32_t TESTCTRL_CLR; /**< Test Control Register */
+ __IOM uint32_t SEQIF_CLR; /**< SEQ Interrupt Flags */
+ __IOM uint32_t SEQIEN_CLR; /**< SEQ Interrupt Enable Register */
+ __IM uint32_t STATUS1_CLR; /**< Radio State Machine Status */
+ __IM uint32_t STIMER_CLR; /**< Sequencer Timer Value */
+ __IOM uint32_t STIMERCOMP_CLR; /**< Sequencer Timer Compare Value */
+ __IOM uint32_t SEQCTRL_CLR; /**< Sequencer Control Register */
+ __IOM uint32_t PRESC_CLR; /**< Sequencer prescaler Register */
+ __IOM uint32_t SR0_CLR; /**< Storage Register 0 */
+ __IOM uint32_t SR1_CLR; /**< Storage Register 1 */
+ __IOM uint32_t SR2_CLR; /**< Storage Register 2 */
+ __IOM uint32_t SR3_CLR; /**< Storage Register 3 */
+ __IOM uint32_t STCTRL_CLR; /**< Sys tick timer Control Register */
+ __IOM uint32_t FRCTXWORD_CLR; /**< FRC wordbuffer write */
+ __IM uint32_t FRCRXWORD_CLR; /**< FRC wordbuffer read */
+ __IOM uint32_t EM1PCSR_CLR; /**< Radio EM1P Control and Status Register */
+ uint32_t RESERVED32[13U]; /**< Reserved for future use */
+ __IOM uint32_t SYNTHENCTRL_CLR; /**< Synthesizer Enable Control Register */
+ __IOM uint32_t SYNTHREGCTRL_CLR; /**< Synthesizer Regulator Enable Control */
+ __IOM uint32_t VCOCTRL_CLR; /**< VCO Control Register */
+ uint32_t RESERVED33[2U]; /**< Reserved for future use */
+ uint32_t RESERVED34[1U]; /**< Reserved for future use */
+ __IM uint32_t STATUS2_CLR; /**< Radio State Machine Status 2 */
+ __IOM uint32_t IFPGACTRL_CLR; /**< IF PGA Control Register */
+ __IOM uint32_t PAENCTRL_CLR; /**< PA Enable Control Register */
+ __IOM uint32_t APC_CLR; /**< Automatic Power Control Register */
+ __IOM uint32_t ANTDIV_CLR; /**< ANTDIV */
+ __IOM uint32_t AUXADCTRIM_CLR; /**< AUXADCTRIM */
+ __IOM uint32_t AUXADCEN_CLR; /**< AUXADCEN */
+ __IOM uint32_t AUXADCCTRL0_CLR; /**< Auxiliary ADC register control */
+ __IOM uint32_t AUXADCCTRL1_CLR; /**< AUXADCCTRL1 */
+ __IM uint32_t AUXADCOUT_CLR; /**< Auxiliary ADC digital output */
+ __IOM uint32_t CLKMULTEN0_CLR; /**< CLKMULTEN0 */
+ __IOM uint32_t CLKMULTEN1_CLR; /**< CLKMULTEN1 */
+ __IOM uint32_t CLKMULTCTRL_CLR; /**< CLKMULTCTRL */
+ __IM uint32_t CLKMULTSTATUS_CLR; /**< CLKMULTSTATUS */
+ uint32_t RESERVED35[1U]; /**< Reserved for future use */
+ __IOM uint32_t IFADCTRIM0_CLR; /**< IFADCTRIM0 */
+ __IOM uint32_t IFADCTRIM1_CLR; /**< IFADCTRIM1 */
+ __IOM uint32_t IFADCCAL_CLR; /**< IFADCCAL */
+ __IM uint32_t IFADCSTATUS_CLR; /**< IFADCSTATUS */
+ uint32_t RESERVED36[1U]; /**< Reserved for future use */
+ __IOM uint32_t LNAMIXTRIM0_CLR; /**< LNAMIXTRIM0 */
+ __IOM uint32_t LNAMIXTRIM1_CLR; /**< LNAMIXTRIM1 */
+ __IOM uint32_t LNAMIXTRIM2_CLR; /**< LNAMIXTRIM2 */
+ __IOM uint32_t LNAMIXTRIM3_CLR; /**< LNAMIXTRIM3 */
+ __IOM uint32_t LNAMIXTRIM4_CLR; /**< LNAMIXTRIM4 */
+ __IOM uint32_t LNAMIXCAL_CLR; /**< LNAMIXCAL */
+ __IOM uint32_t LNAMIXEN_CLR; /**< LNAMIXEN */
+ __IOM uint32_t PRECTRL_CLR; /**< PRECTRL */
+ __IOM uint32_t PATRIM0_CLR; /**< PATRIM0 */
+ __IOM uint32_t PATRIM1_CLR; /**< PATRIM1 */
+ __IOM uint32_t PATRIM2_CLR; /**< PATRIM2 */
+ __IOM uint32_t PATRIM3_CLR; /**< PATRIM3 */
+ __IOM uint32_t PATRIM4_CLR; /**< PATRIM4 */
+ __IOM uint32_t PATRIM5_CLR; /**< PATRIM5 */
+ uint32_t RESERVED37[1U]; /**< Reserved for future use */
+ __IOM uint32_t TXPOWER_CLR; /**< TXPOWER */
+ __IOM uint32_t TXRAMP_CLR; /**< TXRAMP */
+ uint32_t RESERVED38[1U]; /**< Reserved for future use */
+ __IOM uint32_t PGATRIM_CLR; /**< PGATRIM */
+ __IOM uint32_t PGACAL_CLR; /**< PGACAL */
+ __IOM uint32_t PGACTRL_CLR; /**< PGACTRL */
+ __IOM uint32_t RFBIASCAL_CLR; /**< RFBIASCAL */
+ __IOM uint32_t RFBIASCTRL_CLR; /**< RFBIASCTRL */
+ __IOM uint32_t RADIOEN_CLR; /**< RADIOEN */
+ __IOM uint32_t RFPATHEN0_CLR; /**< RFPATHEN0 */
+ __IOM uint32_t RFPATHEN1_CLR; /**< RFPATHEN1 */
+ __IOM uint32_t RX_CLR; /**< RX */
+ __IOM uint32_t TX_CLR; /**< TX */
+ uint32_t RESERVED39[1U]; /**< Reserved for future use */
+ __IOM uint32_t SYTRIM0_CLR; /**< SYTRIM0 */
+ __IOM uint32_t SYTRIM1_CLR; /**< SYTRIM1 */
+ __IOM uint32_t SYCAL_CLR; /**< SYCAL */
+ __IOM uint32_t SYEN_CLR; /**< SYEN */
+ __IOM uint32_t SYLOEN_CLR; /**< SYLOEN */
+ __IOM uint32_t SYMMDCTRL_CLR; /**< SYMMDCTRL */
+ uint32_t RESERVED40[1U]; /**< Reserved for future use */
+ __IOM uint32_t DIGCLKRETIMECTRL_CLR; /**< DIGCLKRETIMECTRL */
+ __IM uint32_t DIGCLKRETIMESTATUS_CLR; /**< DIGCLKRETIMESTATUS */
+ __IOM uint32_t XORETIMECTRL_CLR; /**< XORETIMECTRL */
+ __IM uint32_t XORETIMESTATUS_CLR; /**< XORETIMESTATUS */
+ __IOM uint32_t AGCOVERWRITE0_CLR; /**< OVERWRITE AGC */
+ __IOM uint32_t AGCOVERWRITE1_CLR; /**< OVERWRITE AGC */
+ __IOM uint32_t AGCOVERWRITE2_CLR; /**< OVERWRITE AGC */
+ uint32_t RESERVED41[7U]; /**< Reserved for future use */
+ __IOM uint32_t PACTRL_CLR; /**< PACTRL */
+ __IOM uint32_t FENOTCH0_CLR; /**< FENOTCH0 */
+ __IOM uint32_t FENOTCH1_CLR; /**< FENOTCH1 */
+ uint32_t RESERVED42[131U]; /**< Reserved for future use */
+ __IOM uint32_t SCRATCH0_CLR; /**< SCRATCH0 */
+ __IOM uint32_t SCRATCH1_CLR; /**< SCRATCH1 */
+ __IOM uint32_t SCRATCH2_CLR; /**< SCRATCH2 */
+ __IOM uint32_t SCRATCH3_CLR; /**< SCRATCH3 */
+ __IOM uint32_t SCRATCH4_CLR; /**< SCRATCH4 */
+ __IOM uint32_t SCRATCH5_CLR; /**< SCRATCH5 */
+ __IOM uint32_t SCRATCH6_CLR; /**< SCRATCH6 */
+ __IOM uint32_t SCRATCH7_CLR; /**< SCRATCH7 */
+ uint32_t RESERVED43[250U]; /**< Reserved for future use */
+ __IOM uint32_t THMSW_CLR; /**< Thermister control */
+ uint32_t RESERVED44[1U]; /**< Reserved for future use */
+ uint32_t RESERVED45[2U]; /**< Reserved for future use */
+ uint32_t RESERVED46[1U]; /**< Reserved for future use */
+ uint32_t RESERVED47[513U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP Version */
+ __IOM uint32_t EN_TGL; /**< Enable peripheral clock to this module */
+ __IOM uint32_t RXENSRCEN_TGL; /**< RXEN Source Enable */
+ __IM uint32_t STATUS_TGL; /**< Radio State Machine Status */
+ __IOM uint32_t CMD_TGL; /**< Radio Commands */
+ __IOM uint32_t CTRL_TGL; /**< Radio Control Register */
+ __IOM uint32_t FORCESTATE_TGL; /**< Force state transition */
+ __IOM uint32_t IF_TGL; /**< Radio Controller Interrupt Flags */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
+ __IOM uint32_t TESTCTRL_TGL; /**< Test Control Register */
+ __IOM uint32_t SEQIF_TGL; /**< SEQ Interrupt Flags */
+ __IOM uint32_t SEQIEN_TGL; /**< SEQ Interrupt Enable Register */
+ __IM uint32_t STATUS1_TGL; /**< Radio State Machine Status */
+ __IM uint32_t STIMER_TGL; /**< Sequencer Timer Value */
+ __IOM uint32_t STIMERCOMP_TGL; /**< Sequencer Timer Compare Value */
+ __IOM uint32_t SEQCTRL_TGL; /**< Sequencer Control Register */
+ __IOM uint32_t PRESC_TGL; /**< Sequencer prescaler Register */
+ __IOM uint32_t SR0_TGL; /**< Storage Register 0 */
+ __IOM uint32_t SR1_TGL; /**< Storage Register 1 */
+ __IOM uint32_t SR2_TGL; /**< Storage Register 2 */
+ __IOM uint32_t SR3_TGL; /**< Storage Register 3 */
+ __IOM uint32_t STCTRL_TGL; /**< Sys tick timer Control Register */
+ __IOM uint32_t FRCTXWORD_TGL; /**< FRC wordbuffer write */
+ __IM uint32_t FRCRXWORD_TGL; /**< FRC wordbuffer read */
+ __IOM uint32_t EM1PCSR_TGL; /**< Radio EM1P Control and Status Register */
+ uint32_t RESERVED48[13U]; /**< Reserved for future use */
+ __IOM uint32_t SYNTHENCTRL_TGL; /**< Synthesizer Enable Control Register */
+ __IOM uint32_t SYNTHREGCTRL_TGL; /**< Synthesizer Regulator Enable Control */
+ __IOM uint32_t VCOCTRL_TGL; /**< VCO Control Register */
+ uint32_t RESERVED49[2U]; /**< Reserved for future use */
+ uint32_t RESERVED50[1U]; /**< Reserved for future use */
+ __IM uint32_t STATUS2_TGL; /**< Radio State Machine Status 2 */
+ __IOM uint32_t IFPGACTRL_TGL; /**< IF PGA Control Register */
+ __IOM uint32_t PAENCTRL_TGL; /**< PA Enable Control Register */
+ __IOM uint32_t APC_TGL; /**< Automatic Power Control Register */
+ __IOM uint32_t ANTDIV_TGL; /**< ANTDIV */
+ __IOM uint32_t AUXADCTRIM_TGL; /**< AUXADCTRIM */
+ __IOM uint32_t AUXADCEN_TGL; /**< AUXADCEN */
+ __IOM uint32_t AUXADCCTRL0_TGL; /**< Auxiliary ADC register control */
+ __IOM uint32_t AUXADCCTRL1_TGL; /**< AUXADCCTRL1 */
+ __IM uint32_t AUXADCOUT_TGL; /**< Auxiliary ADC digital output */
+ __IOM uint32_t CLKMULTEN0_TGL; /**< CLKMULTEN0 */
+ __IOM uint32_t CLKMULTEN1_TGL; /**< CLKMULTEN1 */
+ __IOM uint32_t CLKMULTCTRL_TGL; /**< CLKMULTCTRL */
+ __IM uint32_t CLKMULTSTATUS_TGL; /**< CLKMULTSTATUS */
+ uint32_t RESERVED51[1U]; /**< Reserved for future use */
+ __IOM uint32_t IFADCTRIM0_TGL; /**< IFADCTRIM0 */
+ __IOM uint32_t IFADCTRIM1_TGL; /**< IFADCTRIM1 */
+ __IOM uint32_t IFADCCAL_TGL; /**< IFADCCAL */
+ __IM uint32_t IFADCSTATUS_TGL; /**< IFADCSTATUS */
+ uint32_t RESERVED52[1U]; /**< Reserved for future use */
+ __IOM uint32_t LNAMIXTRIM0_TGL; /**< LNAMIXTRIM0 */
+ __IOM uint32_t LNAMIXTRIM1_TGL; /**< LNAMIXTRIM1 */
+ __IOM uint32_t LNAMIXTRIM2_TGL; /**< LNAMIXTRIM2 */
+ __IOM uint32_t LNAMIXTRIM3_TGL; /**< LNAMIXTRIM3 */
+ __IOM uint32_t LNAMIXTRIM4_TGL; /**< LNAMIXTRIM4 */
+ __IOM uint32_t LNAMIXCAL_TGL; /**< LNAMIXCAL */
+ __IOM uint32_t LNAMIXEN_TGL; /**< LNAMIXEN */
+ __IOM uint32_t PRECTRL_TGL; /**< PRECTRL */
+ __IOM uint32_t PATRIM0_TGL; /**< PATRIM0 */
+ __IOM uint32_t PATRIM1_TGL; /**< PATRIM1 */
+ __IOM uint32_t PATRIM2_TGL; /**< PATRIM2 */
+ __IOM uint32_t PATRIM3_TGL; /**< PATRIM3 */
+ __IOM uint32_t PATRIM4_TGL; /**< PATRIM4 */
+ __IOM uint32_t PATRIM5_TGL; /**< PATRIM5 */
+ uint32_t RESERVED53[1U]; /**< Reserved for future use */
+ __IOM uint32_t TXPOWER_TGL; /**< TXPOWER */
+ __IOM uint32_t TXRAMP_TGL; /**< TXRAMP */
+ uint32_t RESERVED54[1U]; /**< Reserved for future use */
+ __IOM uint32_t PGATRIM_TGL; /**< PGATRIM */
+ __IOM uint32_t PGACAL_TGL; /**< PGACAL */
+ __IOM uint32_t PGACTRL_TGL; /**< PGACTRL */
+ __IOM uint32_t RFBIASCAL_TGL; /**< RFBIASCAL */
+ __IOM uint32_t RFBIASCTRL_TGL; /**< RFBIASCTRL */
+ __IOM uint32_t RADIOEN_TGL; /**< RADIOEN */
+ __IOM uint32_t RFPATHEN0_TGL; /**< RFPATHEN0 */
+ __IOM uint32_t RFPATHEN1_TGL; /**< RFPATHEN1 */
+ __IOM uint32_t RX_TGL; /**< RX */
+ __IOM uint32_t TX_TGL; /**< TX */
+ uint32_t RESERVED55[1U]; /**< Reserved for future use */
+ __IOM uint32_t SYTRIM0_TGL; /**< SYTRIM0 */
+ __IOM uint32_t SYTRIM1_TGL; /**< SYTRIM1 */
+ __IOM uint32_t SYCAL_TGL; /**< SYCAL */
+ __IOM uint32_t SYEN_TGL; /**< SYEN */
+ __IOM uint32_t SYLOEN_TGL; /**< SYLOEN */
+ __IOM uint32_t SYMMDCTRL_TGL; /**< SYMMDCTRL */
+ uint32_t RESERVED56[1U]; /**< Reserved for future use */
+ __IOM uint32_t DIGCLKRETIMECTRL_TGL; /**< DIGCLKRETIMECTRL */
+ __IM uint32_t DIGCLKRETIMESTATUS_TGL; /**< DIGCLKRETIMESTATUS */
+ __IOM uint32_t XORETIMECTRL_TGL; /**< XORETIMECTRL */
+ __IM uint32_t XORETIMESTATUS_TGL; /**< XORETIMESTATUS */
+ __IOM uint32_t AGCOVERWRITE0_TGL; /**< OVERWRITE AGC */
+ __IOM uint32_t AGCOVERWRITE1_TGL; /**< OVERWRITE AGC */
+ __IOM uint32_t AGCOVERWRITE2_TGL; /**< OVERWRITE AGC */
+ uint32_t RESERVED57[7U]; /**< Reserved for future use */
+ __IOM uint32_t PACTRL_TGL; /**< PACTRL */
+ __IOM uint32_t FENOTCH0_TGL; /**< FENOTCH0 */
+ __IOM uint32_t FENOTCH1_TGL; /**< FENOTCH1 */
+ uint32_t RESERVED58[131U]; /**< Reserved for future use */
+ __IOM uint32_t SCRATCH0_TGL; /**< SCRATCH0 */
+ __IOM uint32_t SCRATCH1_TGL; /**< SCRATCH1 */
+ __IOM uint32_t SCRATCH2_TGL; /**< SCRATCH2 */
+ __IOM uint32_t SCRATCH3_TGL; /**< SCRATCH3 */
+ __IOM uint32_t SCRATCH4_TGL; /**< SCRATCH4 */
+ __IOM uint32_t SCRATCH5_TGL; /**< SCRATCH5 */
+ __IOM uint32_t SCRATCH6_TGL; /**< SCRATCH6 */
+ __IOM uint32_t SCRATCH7_TGL; /**< SCRATCH7 */
+ uint32_t RESERVED59[250U]; /**< Reserved for future use */
+ __IOM uint32_t THMSW_TGL; /**< Thermister control */
+ uint32_t RESERVED60[1U]; /**< Reserved for future use */
+ uint32_t RESERVED61[2U]; /**< Reserved for future use */
+ uint32_t RESERVED62[1U]; /**< Reserved for future use */
+} RAC_TypeDef;
+/** @} End of group EFR32MG24_RAC */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_RAC
+ * @{
+ * @defgroup EFR32MG24_RAC_BitFields RAC Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for RAC IPVERSION */
+#define _RAC_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for RAC_IPVERSION */
+#define _RAC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for RAC_IPVERSION */
+#define _RAC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for RAC_IPVERSION */
+#define _RAC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for RAC_IPVERSION */
+#define _RAC_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for RAC_IPVERSION */
+#define RAC_IPVERSION_IPVERSION_DEFAULT (_RAC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_IPVERSION */
+
+/* Bit fields for RAC EN */
+#define _RAC_EN_RESETVALUE 0x00000000UL /**< Default value for RAC_EN */
+#define _RAC_EN_MASK 0x00000001UL /**< Mask for RAC_EN */
+#define RAC_EN_EN (0x1UL << 0) /**< Enable peripheral clock to this module */
+#define _RAC_EN_EN_SHIFT 0 /**< Shift value for RAC_EN */
+#define _RAC_EN_EN_MASK 0x1UL /**< Bit mask for RAC_EN */
+#define _RAC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_EN */
+#define RAC_EN_EN_DEFAULT (_RAC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_EN */
+
+/* Bit fields for RAC RXENSRCEN */
+#define _RAC_RXENSRCEN_RESETVALUE 0x00000000UL /**< Default value for RAC_RXENSRCEN */
+#define _RAC_RXENSRCEN_MASK 0x00003FFFUL /**< Mask for RAC_RXENSRCEN */
+#define _RAC_RXENSRCEN_SWRXEN_SHIFT 0 /**< Shift value for RAC_SWRXEN */
+#define _RAC_RXENSRCEN_SWRXEN_MASK 0xFFUL /**< Bit mask for RAC_SWRXEN */
+#define _RAC_RXENSRCEN_SWRXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RXENSRCEN */
+#define RAC_RXENSRCEN_SWRXEN_DEFAULT (_RAC_RXENSRCEN_SWRXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_RXENSRCEN */
+#define RAC_RXENSRCEN_CHANNELBUSYEN (0x1UL << 8) /**< Channel Busy Enable */
+#define _RAC_RXENSRCEN_CHANNELBUSYEN_SHIFT 8 /**< Shift value for RAC_CHANNELBUSYEN */
+#define _RAC_RXENSRCEN_CHANNELBUSYEN_MASK 0x100UL /**< Bit mask for RAC_CHANNELBUSYEN */
+#define _RAC_RXENSRCEN_CHANNELBUSYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RXENSRCEN */
+#define RAC_RXENSRCEN_CHANNELBUSYEN_DEFAULT (_RAC_RXENSRCEN_CHANNELBUSYEN_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_RXENSRCEN */
+#define RAC_RXENSRCEN_TIMDETEN (0x1UL << 9) /**< Timing Detected Enable */
+#define _RAC_RXENSRCEN_TIMDETEN_SHIFT 9 /**< Shift value for RAC_TIMDETEN */
+#define _RAC_RXENSRCEN_TIMDETEN_MASK 0x200UL /**< Bit mask for RAC_TIMDETEN */
+#define _RAC_RXENSRCEN_TIMDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RXENSRCEN */
+#define RAC_RXENSRCEN_TIMDETEN_DEFAULT (_RAC_RXENSRCEN_TIMDETEN_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_RXENSRCEN */
+#define RAC_RXENSRCEN_PREDETEN (0x1UL << 10) /**< Preamble Detected Enable */
+#define _RAC_RXENSRCEN_PREDETEN_SHIFT 10 /**< Shift value for RAC_PREDETEN */
+#define _RAC_RXENSRCEN_PREDETEN_MASK 0x400UL /**< Bit mask for RAC_PREDETEN */
+#define _RAC_RXENSRCEN_PREDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RXENSRCEN */
+#define RAC_RXENSRCEN_PREDETEN_DEFAULT (_RAC_RXENSRCEN_PREDETEN_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_RXENSRCEN */
+#define RAC_RXENSRCEN_FRAMEDETEN (0x1UL << 11) /**< Frame Detected Enable */
+#define _RAC_RXENSRCEN_FRAMEDETEN_SHIFT 11 /**< Shift value for RAC_FRAMEDETEN */
+#define _RAC_RXENSRCEN_FRAMEDETEN_MASK 0x800UL /**< Bit mask for RAC_FRAMEDETEN */
+#define _RAC_RXENSRCEN_FRAMEDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RXENSRCEN */
+#define RAC_RXENSRCEN_FRAMEDETEN_DEFAULT (_RAC_RXENSRCEN_FRAMEDETEN_DEFAULT << 11) /**< Shifted mode DEFAULT for RAC_RXENSRCEN */
+#define RAC_RXENSRCEN_DEMODRXREQEN (0x1UL << 12) /**< DEMOD RX Request Enable */
+#define _RAC_RXENSRCEN_DEMODRXREQEN_SHIFT 12 /**< Shift value for RAC_DEMODRXREQEN */
+#define _RAC_RXENSRCEN_DEMODRXREQEN_MASK 0x1000UL /**< Bit mask for RAC_DEMODRXREQEN */
+#define _RAC_RXENSRCEN_DEMODRXREQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RXENSRCEN */
+#define RAC_RXENSRCEN_DEMODRXREQEN_DEFAULT (_RAC_RXENSRCEN_DEMODRXREQEN_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_RXENSRCEN */
+#define RAC_RXENSRCEN_PRSRXEN (0x1UL << 13) /**< PRS RX Enable */
+#define _RAC_RXENSRCEN_PRSRXEN_SHIFT 13 /**< Shift value for RAC_PRSRXEN */
+#define _RAC_RXENSRCEN_PRSRXEN_MASK 0x2000UL /**< Bit mask for RAC_PRSRXEN */
+#define _RAC_RXENSRCEN_PRSRXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RXENSRCEN */
+#define RAC_RXENSRCEN_PRSRXEN_DEFAULT (_RAC_RXENSRCEN_PRSRXEN_DEFAULT << 13) /**< Shifted mode DEFAULT for RAC_RXENSRCEN */
+
+/* Bit fields for RAC STATUS */
+#define _RAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for RAC_STATUS */
+#define _RAC_STATUS_MASK 0xFFF8FFFFUL /**< Mask for RAC_STATUS */
+#define _RAC_STATUS_RXMASK_SHIFT 0 /**< Shift value for RAC_RXMASK */
+#define _RAC_STATUS_RXMASK_MASK 0xFFFFUL /**< Bit mask for RAC_RXMASK */
+#define _RAC_STATUS_RXMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STATUS */
+#define RAC_STATUS_RXMASK_DEFAULT (_RAC_STATUS_RXMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_STATUS */
+#define RAC_STATUS_FORCESTATEACTIVE (0x1UL << 19) /**< FSM state force active */
+#define _RAC_STATUS_FORCESTATEACTIVE_SHIFT 19 /**< Shift value for RAC_FORCESTATEACTIVE */
+#define _RAC_STATUS_FORCESTATEACTIVE_MASK 0x80000UL /**< Bit mask for RAC_FORCESTATEACTIVE */
+#define _RAC_STATUS_FORCESTATEACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STATUS */
+#define _RAC_STATUS_FORCESTATEACTIVE_X0 0x00000000UL /**< Mode X0 for RAC_STATUS */
+#define _RAC_STATUS_FORCESTATEACTIVE_X1 0x00000001UL /**< Mode X1 for RAC_STATUS */
+#define RAC_STATUS_FORCESTATEACTIVE_DEFAULT (_RAC_STATUS_FORCESTATEACTIVE_DEFAULT << 19) /**< Shifted mode DEFAULT for RAC_STATUS */
+#define RAC_STATUS_FORCESTATEACTIVE_X0 (_RAC_STATUS_FORCESTATEACTIVE_X0 << 19) /**< Shifted mode X0 for RAC_STATUS */
+#define RAC_STATUS_FORCESTATEACTIVE_X1 (_RAC_STATUS_FORCESTATEACTIVE_X1 << 19) /**< Shifted mode X1 for RAC_STATUS */
+#define RAC_STATUS_TXAFTERFRAMEPEND (0x1UL << 20) /**< TX After Frame Pending */
+#define _RAC_STATUS_TXAFTERFRAMEPEND_SHIFT 20 /**< Shift value for RAC_TXAFTERFRAMEPEND */
+#define _RAC_STATUS_TXAFTERFRAMEPEND_MASK 0x100000UL /**< Bit mask for RAC_TXAFTERFRAMEPEND */
+#define _RAC_STATUS_TXAFTERFRAMEPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STATUS */
+#define _RAC_STATUS_TXAFTERFRAMEPEND_X0 0x00000000UL /**< Mode X0 for RAC_STATUS */
+#define _RAC_STATUS_TXAFTERFRAMEPEND_X1 0x00000001UL /**< Mode X1 for RAC_STATUS */
+#define RAC_STATUS_TXAFTERFRAMEPEND_DEFAULT (_RAC_STATUS_TXAFTERFRAMEPEND_DEFAULT << 20) /**< Shifted mode DEFAULT for RAC_STATUS */
+#define RAC_STATUS_TXAFTERFRAMEPEND_X0 (_RAC_STATUS_TXAFTERFRAMEPEND_X0 << 20) /**< Shifted mode X0 for RAC_STATUS */
+#define RAC_STATUS_TXAFTERFRAMEPEND_X1 (_RAC_STATUS_TXAFTERFRAMEPEND_X1 << 20) /**< Shifted mode X1 for RAC_STATUS */
+#define RAC_STATUS_TXAFTERFRAMEACTIVE (0x1UL << 21) /**< TX After Frame Active */
+#define _RAC_STATUS_TXAFTERFRAMEACTIVE_SHIFT 21 /**< Shift value for RAC_TXAFTERFRAMEACTIVE */
+#define _RAC_STATUS_TXAFTERFRAMEACTIVE_MASK 0x200000UL /**< Bit mask for RAC_TXAFTERFRAMEACTIVE */
+#define _RAC_STATUS_TXAFTERFRAMEACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STATUS */
+#define _RAC_STATUS_TXAFTERFRAMEACTIVE_X0 0x00000000UL /**< Mode X0 for RAC_STATUS */
+#define _RAC_STATUS_TXAFTERFRAMEACTIVE_X1 0x00000001UL /**< Mode X1 for RAC_STATUS */
+#define RAC_STATUS_TXAFTERFRAMEACTIVE_DEFAULT (_RAC_STATUS_TXAFTERFRAMEACTIVE_DEFAULT << 21) /**< Shifted mode DEFAULT for RAC_STATUS */
+#define RAC_STATUS_TXAFTERFRAMEACTIVE_X0 (_RAC_STATUS_TXAFTERFRAMEACTIVE_X0 << 21) /**< Shifted mode X0 for RAC_STATUS */
+#define RAC_STATUS_TXAFTERFRAMEACTIVE_X1 (_RAC_STATUS_TXAFTERFRAMEACTIVE_X1 << 21) /**< Shifted mode X1 for RAC_STATUS */
+#define RAC_STATUS_SEQSLEEPING (0x1UL << 22) /**< SEQ in sleeping */
+#define _RAC_STATUS_SEQSLEEPING_SHIFT 22 /**< Shift value for RAC_SEQSLEEPING */
+#define _RAC_STATUS_SEQSLEEPING_MASK 0x400000UL /**< Bit mask for RAC_SEQSLEEPING */
+#define _RAC_STATUS_SEQSLEEPING_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STATUS */
+#define RAC_STATUS_SEQSLEEPING_DEFAULT (_RAC_STATUS_SEQSLEEPING_DEFAULT << 22) /**< Shifted mode DEFAULT for RAC_STATUS */
+#define RAC_STATUS_SEQSLEEPDEEP (0x1UL << 23) /**< SEQ in deep sleep */
+#define _RAC_STATUS_SEQSLEEPDEEP_SHIFT 23 /**< Shift value for RAC_SEQSLEEPDEEP */
+#define _RAC_STATUS_SEQSLEEPDEEP_MASK 0x800000UL /**< Bit mask for RAC_SEQSLEEPDEEP */
+#define _RAC_STATUS_SEQSLEEPDEEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STATUS */
+#define RAC_STATUS_SEQSLEEPDEEP_DEFAULT (_RAC_STATUS_SEQSLEEPDEEP_DEFAULT << 23) /**< Shifted mode DEFAULT for RAC_STATUS */
+#define _RAC_STATUS_STATE_SHIFT 24 /**< Shift value for RAC_STATE */
+#define _RAC_STATUS_STATE_MASK 0xF000000UL /**< Bit mask for RAC_STATE */
+#define _RAC_STATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STATUS */
+#define _RAC_STATUS_STATE_OFF 0x00000000UL /**< Mode OFF for RAC_STATUS */
+#define _RAC_STATUS_STATE_RXWARM 0x00000001UL /**< Mode RXWARM for RAC_STATUS */
+#define _RAC_STATUS_STATE_RXSEARCH 0x00000002UL /**< Mode RXSEARCH for RAC_STATUS */
+#define _RAC_STATUS_STATE_RXFRAME 0x00000003UL /**< Mode RXFRAME for RAC_STATUS */
+#define _RAC_STATUS_STATE_RXPD 0x00000004UL /**< Mode RXPD for RAC_STATUS */
+#define _RAC_STATUS_STATE_RX2RX 0x00000005UL /**< Mode RX2RX for RAC_STATUS */
+#define _RAC_STATUS_STATE_RXOVERFLOW 0x00000006UL /**< Mode RXOVERFLOW for RAC_STATUS */
+#define _RAC_STATUS_STATE_RX2TX 0x00000007UL /**< Mode RX2TX for RAC_STATUS */
+#define _RAC_STATUS_STATE_TXWARM 0x00000008UL /**< Mode TXWARM for RAC_STATUS */
+#define _RAC_STATUS_STATE_TX 0x00000009UL /**< Mode TX for RAC_STATUS */
+#define _RAC_STATUS_STATE_TXPD 0x0000000AUL /**< Mode TXPD for RAC_STATUS */
+#define _RAC_STATUS_STATE_TX2RX 0x0000000BUL /**< Mode TX2RX for RAC_STATUS */
+#define _RAC_STATUS_STATE_TX2TX 0x0000000CUL /**< Mode TX2TX for RAC_STATUS */
+#define _RAC_STATUS_STATE_SHUTDOWN 0x0000000DUL /**< Mode SHUTDOWN for RAC_STATUS */
+#define _RAC_STATUS_STATE_POR 0x0000000EUL /**< Mode POR for RAC_STATUS */
+#define RAC_STATUS_STATE_DEFAULT (_RAC_STATUS_STATE_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_STATUS */
+#define RAC_STATUS_STATE_OFF (_RAC_STATUS_STATE_OFF << 24) /**< Shifted mode OFF for RAC_STATUS */
+#define RAC_STATUS_STATE_RXWARM (_RAC_STATUS_STATE_RXWARM << 24) /**< Shifted mode RXWARM for RAC_STATUS */
+#define RAC_STATUS_STATE_RXSEARCH (_RAC_STATUS_STATE_RXSEARCH << 24) /**< Shifted mode RXSEARCH for RAC_STATUS */
+#define RAC_STATUS_STATE_RXFRAME (_RAC_STATUS_STATE_RXFRAME << 24) /**< Shifted mode RXFRAME for RAC_STATUS */
+#define RAC_STATUS_STATE_RXPD (_RAC_STATUS_STATE_RXPD << 24) /**< Shifted mode RXPD for RAC_STATUS */
+#define RAC_STATUS_STATE_RX2RX (_RAC_STATUS_STATE_RX2RX << 24) /**< Shifted mode RX2RX for RAC_STATUS */
+#define RAC_STATUS_STATE_RXOVERFLOW (_RAC_STATUS_STATE_RXOVERFLOW << 24) /**< Shifted mode RXOVERFLOW for RAC_STATUS */
+#define RAC_STATUS_STATE_RX2TX (_RAC_STATUS_STATE_RX2TX << 24) /**< Shifted mode RX2TX for RAC_STATUS */
+#define RAC_STATUS_STATE_TXWARM (_RAC_STATUS_STATE_TXWARM << 24) /**< Shifted mode TXWARM for RAC_STATUS */
+#define RAC_STATUS_STATE_TX (_RAC_STATUS_STATE_TX << 24) /**< Shifted mode TX for RAC_STATUS */
+#define RAC_STATUS_STATE_TXPD (_RAC_STATUS_STATE_TXPD << 24) /**< Shifted mode TXPD for RAC_STATUS */
+#define RAC_STATUS_STATE_TX2RX (_RAC_STATUS_STATE_TX2RX << 24) /**< Shifted mode TX2RX for RAC_STATUS */
+#define RAC_STATUS_STATE_TX2TX (_RAC_STATUS_STATE_TX2TX << 24) /**< Shifted mode TX2TX for RAC_STATUS */
+#define RAC_STATUS_STATE_SHUTDOWN (_RAC_STATUS_STATE_SHUTDOWN << 24) /**< Shifted mode SHUTDOWN for RAC_STATUS */
+#define RAC_STATUS_STATE_POR (_RAC_STATUS_STATE_POR << 24) /**< Shifted mode POR for RAC_STATUS */
+#define RAC_STATUS_SEQACTIVE (0x1UL << 28) /**< SEQ active */
+#define _RAC_STATUS_SEQACTIVE_SHIFT 28 /**< Shift value for RAC_SEQACTIVE */
+#define _RAC_STATUS_SEQACTIVE_MASK 0x10000000UL /**< Bit mask for RAC_SEQACTIVE */
+#define _RAC_STATUS_SEQACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STATUS */
+#define RAC_STATUS_SEQACTIVE_DEFAULT (_RAC_STATUS_SEQACTIVE_DEFAULT << 28) /**< Shifted mode DEFAULT for RAC_STATUS */
+#define RAC_STATUS_TXENS (0x1UL << 30) /**< TXEN Status */
+#define _RAC_STATUS_TXENS_SHIFT 30 /**< Shift value for RAC_TXENS */
+#define _RAC_STATUS_TXENS_MASK 0x40000000UL /**< Bit mask for RAC_TXENS */
+#define _RAC_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STATUS */
+#define _RAC_STATUS_TXENS_X0 0x00000000UL /**< Mode X0 for RAC_STATUS */
+#define _RAC_STATUS_TXENS_X1 0x00000001UL /**< Mode X1 for RAC_STATUS */
+#define RAC_STATUS_TXENS_DEFAULT (_RAC_STATUS_TXENS_DEFAULT << 30) /**< Shifted mode DEFAULT for RAC_STATUS */
+#define RAC_STATUS_TXENS_X0 (_RAC_STATUS_TXENS_X0 << 30) /**< Shifted mode X0 for RAC_STATUS */
+#define RAC_STATUS_TXENS_X1 (_RAC_STATUS_TXENS_X1 << 30) /**< Shifted mode X1 for RAC_STATUS */
+#define RAC_STATUS_RXENS (0x1UL << 31) /**< RXEN Status */
+#define _RAC_STATUS_RXENS_SHIFT 31 /**< Shift value for RAC_RXENS */
+#define _RAC_STATUS_RXENS_MASK 0x80000000UL /**< Bit mask for RAC_RXENS */
+#define _RAC_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STATUS */
+#define _RAC_STATUS_RXENS_X0 0x00000000UL /**< Mode X0 for RAC_STATUS */
+#define _RAC_STATUS_RXENS_X1 0x00000001UL /**< Mode X1 for RAC_STATUS */
+#define RAC_STATUS_RXENS_DEFAULT (_RAC_STATUS_RXENS_DEFAULT << 31) /**< Shifted mode DEFAULT for RAC_STATUS */
+#define RAC_STATUS_RXENS_X0 (_RAC_STATUS_RXENS_X0 << 31) /**< Shifted mode X0 for RAC_STATUS */
+#define RAC_STATUS_RXENS_X1 (_RAC_STATUS_RXENS_X1 << 31) /**< Shifted mode X1 for RAC_STATUS */
+
+/* Bit fields for RAC CMD */
+#define _RAC_CMD_RESETVALUE 0x00000000UL /**< Default value for RAC_CMD */
+#define _RAC_CMD_MASK 0xC000FDFFUL /**< Mask for RAC_CMD */
+#define RAC_CMD_TXEN (0x1UL << 0) /**< Transmitter Enable */
+#define _RAC_CMD_TXEN_SHIFT 0 /**< Shift value for RAC_TXEN */
+#define _RAC_CMD_TXEN_MASK 0x1UL /**< Bit mask for RAC_TXEN */
+#define _RAC_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CMD */
+#define RAC_CMD_TXEN_DEFAULT (_RAC_CMD_TXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_CMD */
+#define RAC_CMD_FORCETX (0x1UL << 1) /**< Force TX Command */
+#define _RAC_CMD_FORCETX_SHIFT 1 /**< Shift value for RAC_FORCETX */
+#define _RAC_CMD_FORCETX_MASK 0x2UL /**< Bit mask for RAC_FORCETX */
+#define _RAC_CMD_FORCETX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CMD */
+#define RAC_CMD_FORCETX_DEFAULT (_RAC_CMD_FORCETX_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_CMD */
+#define RAC_CMD_TXONCCA (0x1UL << 2) /**< Transmit On CCA */
+#define _RAC_CMD_TXONCCA_SHIFT 2 /**< Shift value for RAC_TXONCCA */
+#define _RAC_CMD_TXONCCA_MASK 0x4UL /**< Bit mask for RAC_TXONCCA */
+#define _RAC_CMD_TXONCCA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CMD */
+#define RAC_CMD_TXONCCA_DEFAULT (_RAC_CMD_TXONCCA_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_CMD */
+#define RAC_CMD_CLEARTXEN (0x1UL << 3) /**< Clear TX Enable */
+#define _RAC_CMD_CLEARTXEN_SHIFT 3 /**< Shift value for RAC_CLEARTXEN */
+#define _RAC_CMD_CLEARTXEN_MASK 0x8UL /**< Bit mask for RAC_CLEARTXEN */
+#define _RAC_CMD_CLEARTXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CMD */
+#define RAC_CMD_CLEARTXEN_DEFAULT (_RAC_CMD_CLEARTXEN_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_CMD */
+#define RAC_CMD_TXAFTERFRAME (0x1UL << 4) /**< TX After Frame */
+#define _RAC_CMD_TXAFTERFRAME_SHIFT 4 /**< Shift value for RAC_TXAFTERFRAME */
+#define _RAC_CMD_TXAFTERFRAME_MASK 0x10UL /**< Bit mask for RAC_TXAFTERFRAME */
+#define _RAC_CMD_TXAFTERFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CMD */
+#define RAC_CMD_TXAFTERFRAME_DEFAULT (_RAC_CMD_TXAFTERFRAME_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_CMD */
+#define RAC_CMD_TXDIS (0x1UL << 5) /**< TX Disable */
+#define _RAC_CMD_TXDIS_SHIFT 5 /**< Shift value for RAC_TXDIS */
+#define _RAC_CMD_TXDIS_MASK 0x20UL /**< Bit mask for RAC_TXDIS */
+#define _RAC_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CMD */
+#define RAC_CMD_TXDIS_DEFAULT (_RAC_CMD_TXDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_CMD */
+#define RAC_CMD_CLEARRXOVERFLOW (0x1UL << 6) /**< Clear RX Overflow */
+#define _RAC_CMD_CLEARRXOVERFLOW_SHIFT 6 /**< Shift value for RAC_CLEARRXOVERFLOW */
+#define _RAC_CMD_CLEARRXOVERFLOW_MASK 0x40UL /**< Bit mask for RAC_CLEARRXOVERFLOW */
+#define _RAC_CMD_CLEARRXOVERFLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CMD */
+#define RAC_CMD_CLEARRXOVERFLOW_DEFAULT (_RAC_CMD_CLEARRXOVERFLOW_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_CMD */
+#define RAC_CMD_RXCAL (0x1UL << 7) /**< Start an RX Calibration */
+#define _RAC_CMD_RXCAL_SHIFT 7 /**< Shift value for RAC_RXCAL */
+#define _RAC_CMD_RXCAL_MASK 0x80UL /**< Bit mask for RAC_RXCAL */
+#define _RAC_CMD_RXCAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CMD */
+#define RAC_CMD_RXCAL_DEFAULT (_RAC_CMD_RXCAL_DEFAULT << 7) /**< Shifted mode DEFAULT for RAC_CMD */
+#define RAC_CMD_RXDIS (0x1UL << 8) /**< RX Disable */
+#define _RAC_CMD_RXDIS_SHIFT 8 /**< Shift value for RAC_RXDIS */
+#define _RAC_CMD_RXDIS_MASK 0x100UL /**< Bit mask for RAC_RXDIS */
+#define _RAC_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CMD */
+#define RAC_CMD_RXDIS_DEFAULT (_RAC_CMD_RXDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_CMD */
+#define RAC_CMD_FRCWR (0x1UL << 10) /**< FRC write cmd */
+#define _RAC_CMD_FRCWR_SHIFT 10 /**< Shift value for RAC_FRCWR */
+#define _RAC_CMD_FRCWR_MASK 0x400UL /**< Bit mask for RAC_FRCWR */
+#define _RAC_CMD_FRCWR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CMD */
+#define RAC_CMD_FRCWR_DEFAULT (_RAC_CMD_FRCWR_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_CMD */
+#define RAC_CMD_FRCRD (0x1UL << 11) /**< FRC read cmd */
+#define _RAC_CMD_FRCRD_SHIFT 11 /**< Shift value for RAC_FRCRD */
+#define _RAC_CMD_FRCRD_MASK 0x800UL /**< Bit mask for RAC_FRCRD */
+#define _RAC_CMD_FRCRD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CMD */
+#define RAC_CMD_FRCRD_DEFAULT (_RAC_CMD_FRCRD_DEFAULT << 11) /**< Shifted mode DEFAULT for RAC_CMD */
+#define RAC_CMD_PAENSET (0x1UL << 12) /**< PAEN Set */
+#define _RAC_CMD_PAENSET_SHIFT 12 /**< Shift value for RAC_PAENSET */
+#define _RAC_CMD_PAENSET_MASK 0x1000UL /**< Bit mask for RAC_PAENSET */
+#define _RAC_CMD_PAENSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CMD */
+#define RAC_CMD_PAENSET_DEFAULT (_RAC_CMD_PAENSET_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_CMD */
+#define RAC_CMD_PAENCLEAR (0x1UL << 13) /**< PAEN Clear */
+#define _RAC_CMD_PAENCLEAR_SHIFT 13 /**< Shift value for RAC_PAENCLEAR */
+#define _RAC_CMD_PAENCLEAR_MASK 0x2000UL /**< Bit mask for RAC_PAENCLEAR */
+#define _RAC_CMD_PAENCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CMD */
+#define RAC_CMD_PAENCLEAR_DEFAULT (_RAC_CMD_PAENCLEAR_DEFAULT << 13) /**< Shifted mode DEFAULT for RAC_CMD */
+#define RAC_CMD_LNAENSET (0x1UL << 14) /**< LNAEN Set */
+#define _RAC_CMD_LNAENSET_SHIFT 14 /**< Shift value for RAC_LNAENSET */
+#define _RAC_CMD_LNAENSET_MASK 0x4000UL /**< Bit mask for RAC_LNAENSET */
+#define _RAC_CMD_LNAENSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CMD */
+#define RAC_CMD_LNAENSET_DEFAULT (_RAC_CMD_LNAENSET_DEFAULT << 14) /**< Shifted mode DEFAULT for RAC_CMD */
+#define RAC_CMD_LNAENCLEAR (0x1UL << 15) /**< LNAEN Clear */
+#define _RAC_CMD_LNAENCLEAR_SHIFT 15 /**< Shift value for RAC_LNAENCLEAR */
+#define _RAC_CMD_LNAENCLEAR_MASK 0x8000UL /**< Bit mask for RAC_LNAENCLEAR */
+#define _RAC_CMD_LNAENCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CMD */
+#define RAC_CMD_LNAENCLEAR_DEFAULT (_RAC_CMD_LNAENCLEAR_DEFAULT << 15) /**< Shifted mode DEFAULT for RAC_CMD */
+
+/* Bit fields for RAC CTRL */
+#define _RAC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RAC_CTRL */
+#define _RAC_CTRL_MASK 0x1F0107EFUL /**< Mask for RAC_CTRL */
+#define RAC_CTRL_FORCEDISABLE (0x1UL << 0) /**< Force Radio Disable */
+#define _RAC_CTRL_FORCEDISABLE_SHIFT 0 /**< Shift value for RAC_FORCEDISABLE */
+#define _RAC_CTRL_FORCEDISABLE_MASK 0x1UL /**< Bit mask for RAC_FORCEDISABLE */
+#define _RAC_CTRL_FORCEDISABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */
+#define RAC_CTRL_FORCEDISABLE_DEFAULT (_RAC_CTRL_FORCEDISABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_CTRL */
+#define RAC_CTRL_PRSTXEN (0x1UL << 1) /**< PRS TX Enable */
+#define _RAC_CTRL_PRSTXEN_SHIFT 1 /**< Shift value for RAC_PRSTXEN */
+#define _RAC_CTRL_PRSTXEN_MASK 0x2UL /**< Bit mask for RAC_PRSTXEN */
+#define _RAC_CTRL_PRSTXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */
+#define RAC_CTRL_PRSTXEN_DEFAULT (_RAC_CTRL_PRSTXEN_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_CTRL */
+#define RAC_CTRL_TXAFTERRX (0x1UL << 2) /**< TX After RX */
+#define _RAC_CTRL_TXAFTERRX_SHIFT 2 /**< Shift value for RAC_TXAFTERRX */
+#define _RAC_CTRL_TXAFTERRX_MASK 0x4UL /**< Bit mask for RAC_TXAFTERRX */
+#define _RAC_CTRL_TXAFTERRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */
+#define _RAC_CTRL_TXAFTERRX_X0 0x00000000UL /**< Mode X0 for RAC_CTRL */
+#define _RAC_CTRL_TXAFTERRX_X1 0x00000001UL /**< Mode X1 for RAC_CTRL */
+#define RAC_CTRL_TXAFTERRX_DEFAULT (_RAC_CTRL_TXAFTERRX_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_CTRL */
+#define RAC_CTRL_TXAFTERRX_X0 (_RAC_CTRL_TXAFTERRX_X0 << 2) /**< Shifted mode X0 for RAC_CTRL */
+#define RAC_CTRL_TXAFTERRX_X1 (_RAC_CTRL_TXAFTERRX_X1 << 2) /**< Shifted mode X1 for RAC_CTRL */
+#define RAC_CTRL_PRSMODE (0x1UL << 3) /**< PRS RXEN Mode */
+#define _RAC_CTRL_PRSMODE_SHIFT 3 /**< Shift value for RAC_PRSMODE */
+#define _RAC_CTRL_PRSMODE_MASK 0x8UL /**< Bit mask for RAC_PRSMODE */
+#define _RAC_CTRL_PRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */
+#define _RAC_CTRL_PRSMODE_DIRECT 0x00000000UL /**< Mode DIRECT for RAC_CTRL */
+#define _RAC_CTRL_PRSMODE_PULSE 0x00000001UL /**< Mode PULSE for RAC_CTRL */
+#define RAC_CTRL_PRSMODE_DEFAULT (_RAC_CTRL_PRSMODE_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_CTRL */
+#define RAC_CTRL_PRSMODE_DIRECT (_RAC_CTRL_PRSMODE_DIRECT << 3) /**< Shifted mode DIRECT for RAC_CTRL */
+#define RAC_CTRL_PRSMODE_PULSE (_RAC_CTRL_PRSMODE_PULSE << 3) /**< Shifted mode PULSE for RAC_CTRL */
+#define RAC_CTRL_PRSCLR (0x1UL << 5) /**< PRS RXEN Clear */
+#define _RAC_CTRL_PRSCLR_SHIFT 5 /**< Shift value for RAC_PRSCLR */
+#define _RAC_CTRL_PRSCLR_MASK 0x20UL /**< Bit mask for RAC_PRSCLR */
+#define _RAC_CTRL_PRSCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */
+#define _RAC_CTRL_PRSCLR_RXSEARCH 0x00000000UL /**< Mode RXSEARCH for RAC_CTRL */
+#define _RAC_CTRL_PRSCLR_PRSCH 0x00000001UL /**< Mode PRSCH for RAC_CTRL */
+#define RAC_CTRL_PRSCLR_DEFAULT (_RAC_CTRL_PRSCLR_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_CTRL */
+#define RAC_CTRL_PRSCLR_RXSEARCH (_RAC_CTRL_PRSCLR_RXSEARCH << 5) /**< Shifted mode RXSEARCH for RAC_CTRL */
+#define RAC_CTRL_PRSCLR_PRSCH (_RAC_CTRL_PRSCLR_PRSCH << 5) /**< Shifted mode PRSCH for RAC_CTRL */
+#define RAC_CTRL_TXPOSTPONE (0x1UL << 6) /**< TX Postpone */
+#define _RAC_CTRL_TXPOSTPONE_SHIFT 6 /**< Shift value for RAC_TXPOSTPONE */
+#define _RAC_CTRL_TXPOSTPONE_MASK 0x40UL /**< Bit mask for RAC_TXPOSTPONE */
+#define _RAC_CTRL_TXPOSTPONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */
+#define _RAC_CTRL_TXPOSTPONE_X0 0x00000000UL /**< Mode X0 for RAC_CTRL */
+#define _RAC_CTRL_TXPOSTPONE_X1 0x00000001UL /**< Mode X1 for RAC_CTRL */
+#define RAC_CTRL_TXPOSTPONE_DEFAULT (_RAC_CTRL_TXPOSTPONE_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_CTRL */
+#define RAC_CTRL_TXPOSTPONE_X0 (_RAC_CTRL_TXPOSTPONE_X0 << 6) /**< Shifted mode X0 for RAC_CTRL */
+#define RAC_CTRL_TXPOSTPONE_X1 (_RAC_CTRL_TXPOSTPONE_X1 << 6) /**< Shifted mode X1 for RAC_CTRL */
+#define RAC_CTRL_ACTIVEPOL (0x1UL << 7) /**< ACTIVE signal polarity */
+#define _RAC_CTRL_ACTIVEPOL_SHIFT 7 /**< Shift value for RAC_ACTIVEPOL */
+#define _RAC_CTRL_ACTIVEPOL_MASK 0x80UL /**< Bit mask for RAC_ACTIVEPOL */
+#define _RAC_CTRL_ACTIVEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */
+#define _RAC_CTRL_ACTIVEPOL_X0 0x00000000UL /**< Mode X0 for RAC_CTRL */
+#define _RAC_CTRL_ACTIVEPOL_X1 0x00000001UL /**< Mode X1 for RAC_CTRL */
+#define RAC_CTRL_ACTIVEPOL_DEFAULT (_RAC_CTRL_ACTIVEPOL_DEFAULT << 7) /**< Shifted mode DEFAULT for RAC_CTRL */
+#define RAC_CTRL_ACTIVEPOL_X0 (_RAC_CTRL_ACTIVEPOL_X0 << 7) /**< Shifted mode X0 for RAC_CTRL */
+#define RAC_CTRL_ACTIVEPOL_X1 (_RAC_CTRL_ACTIVEPOL_X1 << 7) /**< Shifted mode X1 for RAC_CTRL */
+#define RAC_CTRL_PAENPOL (0x1UL << 8) /**< PAEN signal polarity */
+#define _RAC_CTRL_PAENPOL_SHIFT 8 /**< Shift value for RAC_PAENPOL */
+#define _RAC_CTRL_PAENPOL_MASK 0x100UL /**< Bit mask for RAC_PAENPOL */
+#define _RAC_CTRL_PAENPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */
+#define _RAC_CTRL_PAENPOL_X0 0x00000000UL /**< Mode X0 for RAC_CTRL */
+#define _RAC_CTRL_PAENPOL_X1 0x00000001UL /**< Mode X1 for RAC_CTRL */
+#define RAC_CTRL_PAENPOL_DEFAULT (_RAC_CTRL_PAENPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_CTRL */
+#define RAC_CTRL_PAENPOL_X0 (_RAC_CTRL_PAENPOL_X0 << 8) /**< Shifted mode X0 for RAC_CTRL */
+#define RAC_CTRL_PAENPOL_X1 (_RAC_CTRL_PAENPOL_X1 << 8) /**< Shifted mode X1 for RAC_CTRL */
+#define RAC_CTRL_LNAENPOL (0x1UL << 9) /**< LNAEN signal polarity */
+#define _RAC_CTRL_LNAENPOL_SHIFT 9 /**< Shift value for RAC_LNAENPOL */
+#define _RAC_CTRL_LNAENPOL_MASK 0x200UL /**< Bit mask for RAC_LNAENPOL */
+#define _RAC_CTRL_LNAENPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */
+#define _RAC_CTRL_LNAENPOL_X0 0x00000000UL /**< Mode X0 for RAC_CTRL */
+#define _RAC_CTRL_LNAENPOL_X1 0x00000001UL /**< Mode X1 for RAC_CTRL */
+#define RAC_CTRL_LNAENPOL_DEFAULT (_RAC_CTRL_LNAENPOL_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_CTRL */
+#define RAC_CTRL_LNAENPOL_X0 (_RAC_CTRL_LNAENPOL_X0 << 9) /**< Shifted mode X0 for RAC_CTRL */
+#define RAC_CTRL_LNAENPOL_X1 (_RAC_CTRL_LNAENPOL_X1 << 9) /**< Shifted mode X1 for RAC_CTRL */
+#define RAC_CTRL_PRSRXDIS (0x1UL << 10) /**< PRS RX Disable */
+#define _RAC_CTRL_PRSRXDIS_SHIFT 10 /**< Shift value for RAC_PRSRXDIS */
+#define _RAC_CTRL_PRSRXDIS_MASK 0x400UL /**< Bit mask for RAC_PRSRXDIS */
+#define _RAC_CTRL_PRSRXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */
+#define _RAC_CTRL_PRSRXDIS_X0 0x00000000UL /**< Mode X0 for RAC_CTRL */
+#define _RAC_CTRL_PRSRXDIS_X1 0x00000001UL /**< Mode X1 for RAC_CTRL */
+#define RAC_CTRL_PRSRXDIS_DEFAULT (_RAC_CTRL_PRSRXDIS_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_CTRL */
+#define RAC_CTRL_PRSRXDIS_X0 (_RAC_CTRL_PRSRXDIS_X0 << 10) /**< Shifted mode X0 for RAC_CTRL */
+#define RAC_CTRL_PRSRXDIS_X1 (_RAC_CTRL_PRSRXDIS_X1 << 10) /**< Shifted mode X1 for RAC_CTRL */
+#define RAC_CTRL_PRSFORCETX (0x1UL << 16) /**< PRS Force RX */
+#define _RAC_CTRL_PRSFORCETX_SHIFT 16 /**< Shift value for RAC_PRSFORCETX */
+#define _RAC_CTRL_PRSFORCETX_MASK 0x10000UL /**< Bit mask for RAC_PRSFORCETX */
+#define _RAC_CTRL_PRSFORCETX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */
+#define _RAC_CTRL_PRSFORCETX_X0 0x00000000UL /**< Mode X0 for RAC_CTRL */
+#define _RAC_CTRL_PRSFORCETX_X1 0x00000001UL /**< Mode X1 for RAC_CTRL */
+#define RAC_CTRL_PRSFORCETX_DEFAULT (_RAC_CTRL_PRSFORCETX_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_CTRL */
+#define RAC_CTRL_PRSFORCETX_X0 (_RAC_CTRL_PRSFORCETX_X0 << 16) /**< Shifted mode X0 for RAC_CTRL */
+#define RAC_CTRL_PRSFORCETX_X1 (_RAC_CTRL_PRSFORCETX_X1 << 16) /**< Shifted mode X1 for RAC_CTRL */
+#define RAC_CTRL_SEQRESET (0x1UL << 24) /**< SEQ reset */
+#define _RAC_CTRL_SEQRESET_SHIFT 24 /**< Shift value for RAC_SEQRESET */
+#define _RAC_CTRL_SEQRESET_MASK 0x1000000UL /**< Bit mask for RAC_SEQRESET */
+#define _RAC_CTRL_SEQRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */
+#define RAC_CTRL_SEQRESET_DEFAULT (_RAC_CTRL_SEQRESET_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_CTRL */
+#define RAC_CTRL_EXITSHUTDOWNDIS (0x1UL << 25) /**< Exit SHUTDOWN state Disable */
+#define _RAC_CTRL_EXITSHUTDOWNDIS_SHIFT 25 /**< Shift value for RAC_EXITSHUTDOWNDIS */
+#define _RAC_CTRL_EXITSHUTDOWNDIS_MASK 0x2000000UL /**< Bit mask for RAC_EXITSHUTDOWNDIS */
+#define _RAC_CTRL_EXITSHUTDOWNDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */
+#define RAC_CTRL_EXITSHUTDOWNDIS_DEFAULT (_RAC_CTRL_EXITSHUTDOWNDIS_DEFAULT << 25) /**< Shifted mode DEFAULT for RAC_CTRL */
+#define RAC_CTRL_CPUWAITDIS (0x1UL << 26) /**< SEQ CPU Wait Disable */
+#define _RAC_CTRL_CPUWAITDIS_SHIFT 26 /**< Shift value for RAC_CPUWAITDIS */
+#define _RAC_CTRL_CPUWAITDIS_MASK 0x4000000UL /**< Bit mask for RAC_CPUWAITDIS */
+#define _RAC_CTRL_CPUWAITDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */
+#define RAC_CTRL_CPUWAITDIS_DEFAULT (_RAC_CTRL_CPUWAITDIS_DEFAULT << 26) /**< Shifted mode DEFAULT for RAC_CTRL */
+#define RAC_CTRL_SEQCLKDIS (0x1UL << 27) /**< SEQ Clk Disable */
+#define _RAC_CTRL_SEQCLKDIS_SHIFT 27 /**< Shift value for RAC_SEQCLKDIS */
+#define _RAC_CTRL_SEQCLKDIS_MASK 0x8000000UL /**< Bit mask for RAC_SEQCLKDIS */
+#define _RAC_CTRL_SEQCLKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */
+#define RAC_CTRL_SEQCLKDIS_DEFAULT (_RAC_CTRL_SEQCLKDIS_DEFAULT << 27) /**< Shifted mode DEFAULT for RAC_CTRL */
+#define RAC_CTRL_RXOFDIS (0x1UL << 28) /**< Switch to RXOVERFLOW Disable */
+#define _RAC_CTRL_RXOFDIS_SHIFT 28 /**< Shift value for RAC_RXOFDIS */
+#define _RAC_CTRL_RXOFDIS_MASK 0x10000000UL /**< Bit mask for RAC_RXOFDIS */
+#define _RAC_CTRL_RXOFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CTRL */
+#define RAC_CTRL_RXOFDIS_DEFAULT (_RAC_CTRL_RXOFDIS_DEFAULT << 28) /**< Shifted mode DEFAULT for RAC_CTRL */
+
+/* Bit fields for RAC FORCESTATE */
+#define _RAC_FORCESTATE_RESETVALUE 0x00000000UL /**< Default value for RAC_FORCESTATE */
+#define _RAC_FORCESTATE_MASK 0x0000000FUL /**< Mask for RAC_FORCESTATE */
+#define _RAC_FORCESTATE_FORCESTATE_SHIFT 0 /**< Shift value for RAC_FORCESTATE */
+#define _RAC_FORCESTATE_FORCESTATE_MASK 0xFUL /**< Bit mask for RAC_FORCESTATE */
+#define _RAC_FORCESTATE_FORCESTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_FORCESTATE */
+#define RAC_FORCESTATE_FORCESTATE_DEFAULT (_RAC_FORCESTATE_FORCESTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_FORCESTATE */
+
+/* Bit fields for RAC IF */
+#define _RAC_IF_RESETVALUE 0x00000000UL /**< Default value for RAC_IF */
+#define _RAC_IF_MASK 0x00FF000FUL /**< Mask for RAC_IF */
+#define RAC_IF_STATECHANGE (0x1UL << 0) /**< Radio State Change */
+#define _RAC_IF_STATECHANGE_SHIFT 0 /**< Shift value for RAC_STATECHANGE */
+#define _RAC_IF_STATECHANGE_MASK 0x1UL /**< Bit mask for RAC_STATECHANGE */
+#define _RAC_IF_STATECHANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IF */
+#define RAC_IF_STATECHANGE_DEFAULT (_RAC_IF_STATECHANGE_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_IF */
+#define RAC_IF_STIMCMPEV (0x1UL << 1) /**< STIMER Compare Event */
+#define _RAC_IF_STIMCMPEV_SHIFT 1 /**< Shift value for RAC_STIMCMPEV */
+#define _RAC_IF_STIMCMPEV_MASK 0x2UL /**< Bit mask for RAC_STIMCMPEV */
+#define _RAC_IF_STIMCMPEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IF */
+#define RAC_IF_STIMCMPEV_DEFAULT (_RAC_IF_STIMCMPEV_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_IF */
+#define RAC_IF_SEQLOCKUP (0x1UL << 2) /**< SEQ locked up */
+#define _RAC_IF_SEQLOCKUP_SHIFT 2 /**< Shift value for RAC_SEQLOCKUP */
+#define _RAC_IF_SEQLOCKUP_MASK 0x4UL /**< Bit mask for RAC_SEQLOCKUP */
+#define _RAC_IF_SEQLOCKUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IF */
+#define RAC_IF_SEQLOCKUP_DEFAULT (_RAC_IF_SEQLOCKUP_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_IF */
+#define RAC_IF_SEQRESETREQ (0x1UL << 3) /**< SEQ reset request */
+#define _RAC_IF_SEQRESETREQ_SHIFT 3 /**< Shift value for RAC_SEQRESETREQ */
+#define _RAC_IF_SEQRESETREQ_MASK 0x8UL /**< Bit mask for RAC_SEQRESETREQ */
+#define _RAC_IF_SEQRESETREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IF */
+#define RAC_IF_SEQRESETREQ_DEFAULT (_RAC_IF_SEQRESETREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_IF */
+#define _RAC_IF_SEQ_SHIFT 16 /**< Shift value for RAC_SEQ */
+#define _RAC_IF_SEQ_MASK 0xFF0000UL /**< Bit mask for RAC_SEQ */
+#define _RAC_IF_SEQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IF */
+#define RAC_IF_SEQ_DEFAULT (_RAC_IF_SEQ_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_IF */
+
+/* Bit fields for RAC IEN */
+#define _RAC_IEN_RESETVALUE 0x00000000UL /**< Default value for RAC_IEN */
+#define _RAC_IEN_MASK 0x00FF000FUL /**< Mask for RAC_IEN */
+#define RAC_IEN_STATECHANGE (0x1UL << 0) /**< Radio State Change Interrupt Enable */
+#define _RAC_IEN_STATECHANGE_SHIFT 0 /**< Shift value for RAC_STATECHANGE */
+#define _RAC_IEN_STATECHANGE_MASK 0x1UL /**< Bit mask for RAC_STATECHANGE */
+#define _RAC_IEN_STATECHANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IEN */
+#define RAC_IEN_STATECHANGE_DEFAULT (_RAC_IEN_STATECHANGE_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_IEN */
+#define RAC_IEN_STIMCMPEV (0x1UL << 1) /**< STIMER Compare Event Interrupt Enable */
+#define _RAC_IEN_STIMCMPEV_SHIFT 1 /**< Shift value for RAC_STIMCMPEV */
+#define _RAC_IEN_STIMCMPEV_MASK 0x2UL /**< Bit mask for RAC_STIMCMPEV */
+#define _RAC_IEN_STIMCMPEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IEN */
+#define RAC_IEN_STIMCMPEV_DEFAULT (_RAC_IEN_STIMCMPEV_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_IEN */
+#define RAC_IEN_SEQLOCKUP (0x1UL << 2) /**< SEQ locked up Interrupt Enable */
+#define _RAC_IEN_SEQLOCKUP_SHIFT 2 /**< Shift value for RAC_SEQLOCKUP */
+#define _RAC_IEN_SEQLOCKUP_MASK 0x4UL /**< Bit mask for RAC_SEQLOCKUP */
+#define _RAC_IEN_SEQLOCKUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IEN */
+#define RAC_IEN_SEQLOCKUP_DEFAULT (_RAC_IEN_SEQLOCKUP_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_IEN */
+#define RAC_IEN_SEQRESETREQ (0x1UL << 3) /**< SEQ reset request Interrupt Enable */
+#define _RAC_IEN_SEQRESETREQ_SHIFT 3 /**< Shift value for RAC_SEQRESETREQ */
+#define _RAC_IEN_SEQRESETREQ_MASK 0x8UL /**< Bit mask for RAC_SEQRESETREQ */
+#define _RAC_IEN_SEQRESETREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IEN */
+#define RAC_IEN_SEQRESETREQ_DEFAULT (_RAC_IEN_SEQRESETREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_IEN */
+#define _RAC_IEN_SEQ_SHIFT 16 /**< Shift value for RAC_SEQ */
+#define _RAC_IEN_SEQ_MASK 0xFF0000UL /**< Bit mask for RAC_SEQ */
+#define _RAC_IEN_SEQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IEN */
+#define RAC_IEN_SEQ_DEFAULT (_RAC_IEN_SEQ_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_IEN */
+
+/* Bit fields for RAC TESTCTRL */
+#define _RAC_TESTCTRL_RESETVALUE 0x00000000UL /**< Default value for RAC_TESTCTRL */
+#define _RAC_TESTCTRL_MASK 0x00000003UL /**< Mask for RAC_TESTCTRL */
+#define RAC_TESTCTRL_MODEN (0x1UL << 0) /**< Modulator enable */
+#define _RAC_TESTCTRL_MODEN_SHIFT 0 /**< Shift value for RAC_MODEN */
+#define _RAC_TESTCTRL_MODEN_MASK 0x1UL /**< Bit mask for RAC_MODEN */
+#define _RAC_TESTCTRL_MODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TESTCTRL */
+#define RAC_TESTCTRL_MODEN_DEFAULT (_RAC_TESTCTRL_MODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_TESTCTRL */
+#define RAC_TESTCTRL_DEMODEN (0x1UL << 1) /**< Demodulator enable */
+#define _RAC_TESTCTRL_DEMODEN_SHIFT 1 /**< Shift value for RAC_DEMODEN */
+#define _RAC_TESTCTRL_DEMODEN_MASK 0x2UL /**< Bit mask for RAC_DEMODEN */
+#define _RAC_TESTCTRL_DEMODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TESTCTRL */
+#define RAC_TESTCTRL_DEMODEN_DEFAULT (_RAC_TESTCTRL_DEMODEN_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_TESTCTRL */
+
+/* Bit fields for RAC SEQIF */
+#define _RAC_SEQIF_RESETVALUE 0x00000000UL /**< Default value for RAC_SEQIF */
+#define _RAC_SEQIF_MASK 0x3FFF000FUL /**< Mask for RAC_SEQIF */
+#define RAC_SEQIF_STATECHANGESEQ (0x1UL << 0) /**< Radio State Change */
+#define _RAC_SEQIF_STATECHANGESEQ_SHIFT 0 /**< Shift value for RAC_STATECHANGESEQ */
+#define _RAC_SEQIF_STATECHANGESEQ_MASK 0x1UL /**< Bit mask for RAC_STATECHANGESEQ */
+#define _RAC_SEQIF_STATECHANGESEQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_STATECHANGESEQ_DEFAULT (_RAC_SEQIF_STATECHANGESEQ_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_STIMCMPEVSEQ (0x1UL << 1) /**< STIMER Compare Event */
+#define _RAC_SEQIF_STIMCMPEVSEQ_SHIFT 1 /**< Shift value for RAC_STIMCMPEVSEQ */
+#define _RAC_SEQIF_STIMCMPEVSEQ_MASK 0x2UL /**< Bit mask for RAC_STIMCMPEVSEQ */
+#define _RAC_SEQIF_STIMCMPEVSEQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_STIMCMPEVSEQ_DEFAULT (_RAC_SEQIF_STIMCMPEVSEQ_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_DEMODRXREQCLRSEQ (0x1UL << 2) /**< Demod RX request clear */
+#define _RAC_SEQIF_DEMODRXREQCLRSEQ_SHIFT 2 /**< Shift value for RAC_DEMODRXREQCLRSEQ */
+#define _RAC_SEQIF_DEMODRXREQCLRSEQ_MASK 0x4UL /**< Bit mask for RAC_DEMODRXREQCLRSEQ */
+#define _RAC_SEQIF_DEMODRXREQCLRSEQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_DEMODRXREQCLRSEQ_DEFAULT (_RAC_SEQIF_DEMODRXREQCLRSEQ_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_PRSEVENTSEQ (0x1UL << 3) /**< SEQ PRS Event */
+#define _RAC_SEQIF_PRSEVENTSEQ_SHIFT 3 /**< Shift value for RAC_PRSEVENTSEQ */
+#define _RAC_SEQIF_PRSEVENTSEQ_MASK 0x8UL /**< Bit mask for RAC_PRSEVENTSEQ */
+#define _RAC_SEQIF_PRSEVENTSEQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_PRSEVENTSEQ_DEFAULT (_RAC_SEQIF_PRSEVENTSEQ_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_STATEOFF (0x1UL << 16) /**< entering STATE_OFF */
+#define _RAC_SEQIF_STATEOFF_SHIFT 16 /**< Shift value for RAC_STATEOFF */
+#define _RAC_SEQIF_STATEOFF_MASK 0x10000UL /**< Bit mask for RAC_STATEOFF */
+#define _RAC_SEQIF_STATEOFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_STATEOFF_DEFAULT (_RAC_SEQIF_STATEOFF_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_STATERXWARM (0x1UL << 17) /**< entering STATE_RXWARM */
+#define _RAC_SEQIF_STATERXWARM_SHIFT 17 /**< Shift value for RAC_STATERXWARM */
+#define _RAC_SEQIF_STATERXWARM_MASK 0x20000UL /**< Bit mask for RAC_STATERXWARM */
+#define _RAC_SEQIF_STATERXWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_STATERXWARM_DEFAULT (_RAC_SEQIF_STATERXWARM_DEFAULT << 17) /**< Shifted mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_STATERXSEARCH (0x1UL << 18) /**< entering STATE_RXSEARCH */
+#define _RAC_SEQIF_STATERXSEARCH_SHIFT 18 /**< Shift value for RAC_STATERXSEARCH */
+#define _RAC_SEQIF_STATERXSEARCH_MASK 0x40000UL /**< Bit mask for RAC_STATERXSEARCH */
+#define _RAC_SEQIF_STATERXSEARCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_STATERXSEARCH_DEFAULT (_RAC_SEQIF_STATERXSEARCH_DEFAULT << 18) /**< Shifted mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_STATERXFRAME (0x1UL << 19) /**< entering STATE_RXFRAME */
+#define _RAC_SEQIF_STATERXFRAME_SHIFT 19 /**< Shift value for RAC_STATERXFRAME */
+#define _RAC_SEQIF_STATERXFRAME_MASK 0x80000UL /**< Bit mask for RAC_STATERXFRAME */
+#define _RAC_SEQIF_STATERXFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_STATERXFRAME_DEFAULT (_RAC_SEQIF_STATERXFRAME_DEFAULT << 19) /**< Shifted mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_STATERXPD (0x1UL << 20) /**< entering STATE_RXPD */
+#define _RAC_SEQIF_STATERXPD_SHIFT 20 /**< Shift value for RAC_STATERXPD */
+#define _RAC_SEQIF_STATERXPD_MASK 0x100000UL /**< Bit mask for RAC_STATERXPD */
+#define _RAC_SEQIF_STATERXPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_STATERXPD_DEFAULT (_RAC_SEQIF_STATERXPD_DEFAULT << 20) /**< Shifted mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_STATERX2RX (0x1UL << 21) /**< entering STATE_RX2RX */
+#define _RAC_SEQIF_STATERX2RX_SHIFT 21 /**< Shift value for RAC_STATERX2RX */
+#define _RAC_SEQIF_STATERX2RX_MASK 0x200000UL /**< Bit mask for RAC_STATERX2RX */
+#define _RAC_SEQIF_STATERX2RX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_STATERX2RX_DEFAULT (_RAC_SEQIF_STATERX2RX_DEFAULT << 21) /**< Shifted mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_STATERXOVERFLOW (0x1UL << 22) /**< entering STATE_RXOVERFLOW */
+#define _RAC_SEQIF_STATERXOVERFLOW_SHIFT 22 /**< Shift value for RAC_STATERXOVERFLOW */
+#define _RAC_SEQIF_STATERXOVERFLOW_MASK 0x400000UL /**< Bit mask for RAC_STATERXOVERFLOW */
+#define _RAC_SEQIF_STATERXOVERFLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_STATERXOVERFLOW_DEFAULT (_RAC_SEQIF_STATERXOVERFLOW_DEFAULT << 22) /**< Shifted mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_STATERX2TX (0x1UL << 23) /**< entering STATE_RX2TX */
+#define _RAC_SEQIF_STATERX2TX_SHIFT 23 /**< Shift value for RAC_STATERX2TX */
+#define _RAC_SEQIF_STATERX2TX_MASK 0x800000UL /**< Bit mask for RAC_STATERX2TX */
+#define _RAC_SEQIF_STATERX2TX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_STATERX2TX_DEFAULT (_RAC_SEQIF_STATERX2TX_DEFAULT << 23) /**< Shifted mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_STATETXWARM (0x1UL << 24) /**< entering STATE_TXWARM */
+#define _RAC_SEQIF_STATETXWARM_SHIFT 24 /**< Shift value for RAC_STATETXWARM */
+#define _RAC_SEQIF_STATETXWARM_MASK 0x1000000UL /**< Bit mask for RAC_STATETXWARM */
+#define _RAC_SEQIF_STATETXWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_STATETXWARM_DEFAULT (_RAC_SEQIF_STATETXWARM_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_STATETX (0x1UL << 25) /**< entering STATE_TX */
+#define _RAC_SEQIF_STATETX_SHIFT 25 /**< Shift value for RAC_STATETX */
+#define _RAC_SEQIF_STATETX_MASK 0x2000000UL /**< Bit mask for RAC_STATETX */
+#define _RAC_SEQIF_STATETX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_STATETX_DEFAULT (_RAC_SEQIF_STATETX_DEFAULT << 25) /**< Shifted mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_STATETXPD (0x1UL << 26) /**< entering STATE_TXPD */
+#define _RAC_SEQIF_STATETXPD_SHIFT 26 /**< Shift value for RAC_STATETXPD */
+#define _RAC_SEQIF_STATETXPD_MASK 0x4000000UL /**< Bit mask for RAC_STATETXPD */
+#define _RAC_SEQIF_STATETXPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_STATETXPD_DEFAULT (_RAC_SEQIF_STATETXPD_DEFAULT << 26) /**< Shifted mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_STATETX2RX (0x1UL << 27) /**< entering STATE_TX2RX */
+#define _RAC_SEQIF_STATETX2RX_SHIFT 27 /**< Shift value for RAC_STATETX2RX */
+#define _RAC_SEQIF_STATETX2RX_MASK 0x8000000UL /**< Bit mask for RAC_STATETX2RX */
+#define _RAC_SEQIF_STATETX2RX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_STATETX2RX_DEFAULT (_RAC_SEQIF_STATETX2RX_DEFAULT << 27) /**< Shifted mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_STATETX2TX (0x1UL << 28) /**< entering STATE_TX2TX */
+#define _RAC_SEQIF_STATETX2TX_SHIFT 28 /**< Shift value for RAC_STATETX2TX */
+#define _RAC_SEQIF_STATETX2TX_MASK 0x10000000UL /**< Bit mask for RAC_STATETX2TX */
+#define _RAC_SEQIF_STATETX2TX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_STATETX2TX_DEFAULT (_RAC_SEQIF_STATETX2TX_DEFAULT << 28) /**< Shifted mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_STATESHUTDOWN (0x1UL << 29) /**< entering STATE_SHUTDOWN */
+#define _RAC_SEQIF_STATESHUTDOWN_SHIFT 29 /**< Shift value for RAC_STATESHUTDOWN */
+#define _RAC_SEQIF_STATESHUTDOWN_MASK 0x20000000UL /**< Bit mask for RAC_STATESHUTDOWN */
+#define _RAC_SEQIF_STATESHUTDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIF */
+#define RAC_SEQIF_STATESHUTDOWN_DEFAULT (_RAC_SEQIF_STATESHUTDOWN_DEFAULT << 29) /**< Shifted mode DEFAULT for RAC_SEQIF */
+
+/* Bit fields for RAC SEQIEN */
+#define _RAC_SEQIEN_RESETVALUE 0x00000000UL /**< Default value for RAC_SEQIEN */
+#define _RAC_SEQIEN_MASK 0x3FFF000FUL /**< Mask for RAC_SEQIEN */
+#define RAC_SEQIEN_STATECHANGESEQ (0x1UL << 0) /**< Radio State Change Interrupt Enable */
+#define _RAC_SEQIEN_STATECHANGESEQ_SHIFT 0 /**< Shift value for RAC_STATECHANGESEQ */
+#define _RAC_SEQIEN_STATECHANGESEQ_MASK 0x1UL /**< Bit mask for RAC_STATECHANGESEQ */
+#define _RAC_SEQIEN_STATECHANGESEQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_STATECHANGESEQ_DEFAULT (_RAC_SEQIEN_STATECHANGESEQ_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_STIMCMPEVSEQ (0x1UL << 1) /**< STIMER Compare Event Interrupt Enable */
+#define _RAC_SEQIEN_STIMCMPEVSEQ_SHIFT 1 /**< Shift value for RAC_STIMCMPEVSEQ */
+#define _RAC_SEQIEN_STIMCMPEVSEQ_MASK 0x2UL /**< Bit mask for RAC_STIMCMPEVSEQ */
+#define _RAC_SEQIEN_STIMCMPEVSEQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_STIMCMPEVSEQ_DEFAULT (_RAC_SEQIEN_STIMCMPEVSEQ_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_DEMODRXREQCLRSEQ (0x1UL << 2) /**< Demod RX req clr Interrupt Enable */
+#define _RAC_SEQIEN_DEMODRXREQCLRSEQ_SHIFT 2 /**< Shift value for RAC_DEMODRXREQCLRSEQ */
+#define _RAC_SEQIEN_DEMODRXREQCLRSEQ_MASK 0x4UL /**< Bit mask for RAC_DEMODRXREQCLRSEQ */
+#define _RAC_SEQIEN_DEMODRXREQCLRSEQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_DEMODRXREQCLRSEQ_DEFAULT (_RAC_SEQIEN_DEMODRXREQCLRSEQ_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_PRSEVENTSEQ (0x1UL << 3) /**< PRS SEQ EVENT Interrupt Enable */
+#define _RAC_SEQIEN_PRSEVENTSEQ_SHIFT 3 /**< Shift value for RAC_PRSEVENTSEQ */
+#define _RAC_SEQIEN_PRSEVENTSEQ_MASK 0x8UL /**< Bit mask for RAC_PRSEVENTSEQ */
+#define _RAC_SEQIEN_PRSEVENTSEQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_PRSEVENTSEQ_DEFAULT (_RAC_SEQIEN_PRSEVENTSEQ_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_STATEOFF (0x1UL << 16) /**< STATE_OFF Interrupt Enable */
+#define _RAC_SEQIEN_STATEOFF_SHIFT 16 /**< Shift value for RAC_STATEOFF */
+#define _RAC_SEQIEN_STATEOFF_MASK 0x10000UL /**< Bit mask for RAC_STATEOFF */
+#define _RAC_SEQIEN_STATEOFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_STATEOFF_DEFAULT (_RAC_SEQIEN_STATEOFF_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_STATERXWARM (0x1UL << 17) /**< STATE_RXWARM Interrupt Enable */
+#define _RAC_SEQIEN_STATERXWARM_SHIFT 17 /**< Shift value for RAC_STATERXWARM */
+#define _RAC_SEQIEN_STATERXWARM_MASK 0x20000UL /**< Bit mask for RAC_STATERXWARM */
+#define _RAC_SEQIEN_STATERXWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_STATERXWARM_DEFAULT (_RAC_SEQIEN_STATERXWARM_DEFAULT << 17) /**< Shifted mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_STATERXSEARCH (0x1UL << 18) /**< STATE_RXSEARC Interrupt Enable */
+#define _RAC_SEQIEN_STATERXSEARCH_SHIFT 18 /**< Shift value for RAC_STATERXSEARCH */
+#define _RAC_SEQIEN_STATERXSEARCH_MASK 0x40000UL /**< Bit mask for RAC_STATERXSEARCH */
+#define _RAC_SEQIEN_STATERXSEARCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_STATERXSEARCH_DEFAULT (_RAC_SEQIEN_STATERXSEARCH_DEFAULT << 18) /**< Shifted mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_STATERXFRAME (0x1UL << 19) /**< STATE_RXFRAME Interrupt Enable */
+#define _RAC_SEQIEN_STATERXFRAME_SHIFT 19 /**< Shift value for RAC_STATERXFRAME */
+#define _RAC_SEQIEN_STATERXFRAME_MASK 0x80000UL /**< Bit mask for RAC_STATERXFRAME */
+#define _RAC_SEQIEN_STATERXFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_STATERXFRAME_DEFAULT (_RAC_SEQIEN_STATERXFRAME_DEFAULT << 19) /**< Shifted mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_STATERXPD (0x1UL << 20) /**< STATE_RXPD Interrupt Enable */
+#define _RAC_SEQIEN_STATERXPD_SHIFT 20 /**< Shift value for RAC_STATERXPD */
+#define _RAC_SEQIEN_STATERXPD_MASK 0x100000UL /**< Bit mask for RAC_STATERXPD */
+#define _RAC_SEQIEN_STATERXPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_STATERXPD_DEFAULT (_RAC_SEQIEN_STATERXPD_DEFAULT << 20) /**< Shifted mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_STATERX2RX (0x1UL << 21) /**< STATE_RX2RX Interrupt Enable */
+#define _RAC_SEQIEN_STATERX2RX_SHIFT 21 /**< Shift value for RAC_STATERX2RX */
+#define _RAC_SEQIEN_STATERX2RX_MASK 0x200000UL /**< Bit mask for RAC_STATERX2RX */
+#define _RAC_SEQIEN_STATERX2RX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_STATERX2RX_DEFAULT (_RAC_SEQIEN_STATERX2RX_DEFAULT << 21) /**< Shifted mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_STATERXOVERFLOW (0x1UL << 22) /**< STATE_RXOVERFLOW Interrupt Enable */
+#define _RAC_SEQIEN_STATERXOVERFLOW_SHIFT 22 /**< Shift value for RAC_STATERXOVERFLOW */
+#define _RAC_SEQIEN_STATERXOVERFLOW_MASK 0x400000UL /**< Bit mask for RAC_STATERXOVERFLOW */
+#define _RAC_SEQIEN_STATERXOVERFLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_STATERXOVERFLOW_DEFAULT (_RAC_SEQIEN_STATERXOVERFLOW_DEFAULT << 22) /**< Shifted mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_STATERX2TX (0x1UL << 23) /**< STATE_RX2TX Interrupt Enable */
+#define _RAC_SEQIEN_STATERX2TX_SHIFT 23 /**< Shift value for RAC_STATERX2TX */
+#define _RAC_SEQIEN_STATERX2TX_MASK 0x800000UL /**< Bit mask for RAC_STATERX2TX */
+#define _RAC_SEQIEN_STATERX2TX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_STATERX2TX_DEFAULT (_RAC_SEQIEN_STATERX2TX_DEFAULT << 23) /**< Shifted mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_STATETXWARM (0x1UL << 24) /**< STATE_TXWARM Interrupt Enable */
+#define _RAC_SEQIEN_STATETXWARM_SHIFT 24 /**< Shift value for RAC_STATETXWARM */
+#define _RAC_SEQIEN_STATETXWARM_MASK 0x1000000UL /**< Bit mask for RAC_STATETXWARM */
+#define _RAC_SEQIEN_STATETXWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_STATETXWARM_DEFAULT (_RAC_SEQIEN_STATETXWARM_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_STATETX (0x1UL << 25) /**< STATE_TX Interrupt Enable */
+#define _RAC_SEQIEN_STATETX_SHIFT 25 /**< Shift value for RAC_STATETX */
+#define _RAC_SEQIEN_STATETX_MASK 0x2000000UL /**< Bit mask for RAC_STATETX */
+#define _RAC_SEQIEN_STATETX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_STATETX_DEFAULT (_RAC_SEQIEN_STATETX_DEFAULT << 25) /**< Shifted mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_STATETXPD (0x1UL << 26) /**< STATE_TXPD Interrupt Enable */
+#define _RAC_SEQIEN_STATETXPD_SHIFT 26 /**< Shift value for RAC_STATETXPD */
+#define _RAC_SEQIEN_STATETXPD_MASK 0x4000000UL /**< Bit mask for RAC_STATETXPD */
+#define _RAC_SEQIEN_STATETXPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_STATETXPD_DEFAULT (_RAC_SEQIEN_STATETXPD_DEFAULT << 26) /**< Shifted mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_STATETX2RX (0x1UL << 27) /**< STATE_TX2RX Interrupt Enable */
+#define _RAC_SEQIEN_STATETX2RX_SHIFT 27 /**< Shift value for RAC_STATETX2RX */
+#define _RAC_SEQIEN_STATETX2RX_MASK 0x8000000UL /**< Bit mask for RAC_STATETX2RX */
+#define _RAC_SEQIEN_STATETX2RX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_STATETX2RX_DEFAULT (_RAC_SEQIEN_STATETX2RX_DEFAULT << 27) /**< Shifted mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_STATETX2TX (0x1UL << 28) /**< STATE_TX2TX Interrupt Enable */
+#define _RAC_SEQIEN_STATETX2TX_SHIFT 28 /**< Shift value for RAC_STATETX2TX */
+#define _RAC_SEQIEN_STATETX2TX_MASK 0x10000000UL /**< Bit mask for RAC_STATETX2TX */
+#define _RAC_SEQIEN_STATETX2TX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_STATETX2TX_DEFAULT (_RAC_SEQIEN_STATETX2TX_DEFAULT << 28) /**< Shifted mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_STATESHUTDOWN (0x1UL << 29) /**< STATE_SHUTDOWN Interrupt Enable */
+#define _RAC_SEQIEN_STATESHUTDOWN_SHIFT 29 /**< Shift value for RAC_STATESHUTDOWN */
+#define _RAC_SEQIEN_STATESHUTDOWN_MASK 0x20000000UL /**< Bit mask for RAC_STATESHUTDOWN */
+#define _RAC_SEQIEN_STATESHUTDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQIEN */
+#define RAC_SEQIEN_STATESHUTDOWN_DEFAULT (_RAC_SEQIEN_STATESHUTDOWN_DEFAULT << 29) /**< Shifted mode DEFAULT for RAC_SEQIEN */
+
+/* Bit fields for RAC STATUS1 */
+#define _RAC_STATUS1_RESETVALUE 0x00000000UL /**< Default value for RAC_STATUS1 */
+#define _RAC_STATUS1_MASK 0x000000FFUL /**< Mask for RAC_STATUS1 */
+#define _RAC_STATUS1_TXMASK_SHIFT 0 /**< Shift value for RAC_TXMASK */
+#define _RAC_STATUS1_TXMASK_MASK 0xFFUL /**< Bit mask for RAC_TXMASK */
+#define _RAC_STATUS1_TXMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STATUS1 */
+#define RAC_STATUS1_TXMASK_DEFAULT (_RAC_STATUS1_TXMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_STATUS1 */
+
+/* Bit fields for RAC STIMER */
+#define _RAC_STIMER_RESETVALUE 0x00000000UL /**< Default value for RAC_STIMER */
+#define _RAC_STIMER_MASK 0x0000FFFFUL /**< Mask for RAC_STIMER */
+#define _RAC_STIMER_STIMER_SHIFT 0 /**< Shift value for RAC_STIMER */
+#define _RAC_STIMER_STIMER_MASK 0xFFFFUL /**< Bit mask for RAC_STIMER */
+#define _RAC_STIMER_STIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STIMER */
+#define RAC_STIMER_STIMER_DEFAULT (_RAC_STIMER_STIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_STIMER */
+
+/* Bit fields for RAC STIMERCOMP */
+#define _RAC_STIMERCOMP_RESETVALUE 0x00000000UL /**< Default value for RAC_STIMERCOMP */
+#define _RAC_STIMERCOMP_MASK 0x0000FFFFUL /**< Mask for RAC_STIMERCOMP */
+#define _RAC_STIMERCOMP_STIMERCOMP_SHIFT 0 /**< Shift value for RAC_STIMERCOMP */
+#define _RAC_STIMERCOMP_STIMERCOMP_MASK 0xFFFFUL /**< Bit mask for RAC_STIMERCOMP */
+#define _RAC_STIMERCOMP_STIMERCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STIMERCOMP */
+#define RAC_STIMERCOMP_STIMERCOMP_DEFAULT (_RAC_STIMERCOMP_STIMERCOMP_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_STIMERCOMP */
+
+/* Bit fields for RAC SEQCTRL */
+#define _RAC_SEQCTRL_RESETVALUE 0x00000000UL /**< Default value for RAC_SEQCTRL */
+#define _RAC_SEQCTRL_MASK 0x0300007FUL /**< Mask for RAC_SEQCTRL */
+#define RAC_SEQCTRL_COMPACT (0x1UL << 0) /**< STIMER Compare Action */
+#define _RAC_SEQCTRL_COMPACT_SHIFT 0 /**< Shift value for RAC_COMPACT */
+#define _RAC_SEQCTRL_COMPACT_MASK 0x1UL /**< Bit mask for RAC_COMPACT */
+#define _RAC_SEQCTRL_COMPACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQCTRL */
+#define _RAC_SEQCTRL_COMPACT_WRAP 0x00000000UL /**< Mode WRAP for RAC_SEQCTRL */
+#define _RAC_SEQCTRL_COMPACT_CONTINUE 0x00000001UL /**< Mode CONTINUE for RAC_SEQCTRL */
+#define RAC_SEQCTRL_COMPACT_DEFAULT (_RAC_SEQCTRL_COMPACT_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SEQCTRL */
+#define RAC_SEQCTRL_COMPACT_WRAP (_RAC_SEQCTRL_COMPACT_WRAP << 0) /**< Shifted mode WRAP for RAC_SEQCTRL */
+#define RAC_SEQCTRL_COMPACT_CONTINUE (_RAC_SEQCTRL_COMPACT_CONTINUE << 0) /**< Shifted mode CONTINUE for RAC_SEQCTRL */
+#define _RAC_SEQCTRL_COMPINVALMODE_SHIFT 1 /**< Shift value for RAC_COMPINVALMODE */
+#define _RAC_SEQCTRL_COMPINVALMODE_MASK 0x6UL /**< Bit mask for RAC_COMPINVALMODE */
+#define _RAC_SEQCTRL_COMPINVALMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQCTRL */
+#define _RAC_SEQCTRL_COMPINVALMODE_NEVER 0x00000000UL /**< Mode NEVER for RAC_SEQCTRL */
+#define _RAC_SEQCTRL_COMPINVALMODE_STATECHANGE 0x00000001UL /**< Mode STATECHANGE for RAC_SEQCTRL */
+#define _RAC_SEQCTRL_COMPINVALMODE_COMPEVENT 0x00000002UL /**< Mode COMPEVENT for RAC_SEQCTRL */
+#define _RAC_SEQCTRL_COMPINVALMODE_STATECOMP 0x00000003UL /**< Mode STATECOMP for RAC_SEQCTRL */
+#define RAC_SEQCTRL_COMPINVALMODE_DEFAULT (_RAC_SEQCTRL_COMPINVALMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_SEQCTRL */
+#define RAC_SEQCTRL_COMPINVALMODE_NEVER (_RAC_SEQCTRL_COMPINVALMODE_NEVER << 1) /**< Shifted mode NEVER for RAC_SEQCTRL */
+#define RAC_SEQCTRL_COMPINVALMODE_STATECHANGE (_RAC_SEQCTRL_COMPINVALMODE_STATECHANGE << 1) /**< Shifted mode STATECHANGE for RAC_SEQCTRL */
+#define RAC_SEQCTRL_COMPINVALMODE_COMPEVENT (_RAC_SEQCTRL_COMPINVALMODE_COMPEVENT << 1) /**< Shifted mode COMPEVENT for RAC_SEQCTRL */
+#define RAC_SEQCTRL_COMPINVALMODE_STATECOMP (_RAC_SEQCTRL_COMPINVALMODE_STATECOMP << 1) /**< Shifted mode STATECOMP for RAC_SEQCTRL */
+#define RAC_SEQCTRL_RELATIVE (0x1UL << 3) /**< STIMER Compare value relative */
+#define _RAC_SEQCTRL_RELATIVE_SHIFT 3 /**< Shift value for RAC_RELATIVE */
+#define _RAC_SEQCTRL_RELATIVE_MASK 0x8UL /**< Bit mask for RAC_RELATIVE */
+#define _RAC_SEQCTRL_RELATIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQCTRL */
+#define _RAC_SEQCTRL_RELATIVE_Absolute 0x00000000UL /**< Mode Absolute for RAC_SEQCTRL */
+#define _RAC_SEQCTRL_RELATIVE_Relative 0x00000001UL /**< Mode Relative for RAC_SEQCTRL */
+#define RAC_SEQCTRL_RELATIVE_DEFAULT (_RAC_SEQCTRL_RELATIVE_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_SEQCTRL */
+#define RAC_SEQCTRL_RELATIVE_Absolute (_RAC_SEQCTRL_RELATIVE_Absolute << 3) /**< Shifted mode Absolute for RAC_SEQCTRL */
+#define RAC_SEQCTRL_RELATIVE_Relative (_RAC_SEQCTRL_RELATIVE_Relative << 3) /**< Shifted mode Relative for RAC_SEQCTRL */
+#define RAC_SEQCTRL_STIMERALWAYSRUN (0x1UL << 4) /**< STIMER always Run */
+#define _RAC_SEQCTRL_STIMERALWAYSRUN_SHIFT 4 /**< Shift value for RAC_STIMERALWAYSRUN */
+#define _RAC_SEQCTRL_STIMERALWAYSRUN_MASK 0x10UL /**< Bit mask for RAC_STIMERALWAYSRUN */
+#define _RAC_SEQCTRL_STIMERALWAYSRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQCTRL */
+#define RAC_SEQCTRL_STIMERALWAYSRUN_DEFAULT (_RAC_SEQCTRL_STIMERALWAYSRUN_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_SEQCTRL */
+#define RAC_SEQCTRL_STIMERDEBUGRUN (0x1UL << 5) /**< STIMER Debug Run */
+#define _RAC_SEQCTRL_STIMERDEBUGRUN_SHIFT 5 /**< Shift value for RAC_STIMERDEBUGRUN */
+#define _RAC_SEQCTRL_STIMERDEBUGRUN_MASK 0x20UL /**< Bit mask for RAC_STIMERDEBUGRUN */
+#define _RAC_SEQCTRL_STIMERDEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQCTRL */
+#define _RAC_SEQCTRL_STIMERDEBUGRUN_X0 0x00000000UL /**< Mode X0 for RAC_SEQCTRL */
+#define _RAC_SEQCTRL_STIMERDEBUGRUN_X1 0x00000001UL /**< Mode X1 for RAC_SEQCTRL */
+#define RAC_SEQCTRL_STIMERDEBUGRUN_DEFAULT (_RAC_SEQCTRL_STIMERDEBUGRUN_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_SEQCTRL */
+#define RAC_SEQCTRL_STIMERDEBUGRUN_X0 (_RAC_SEQCTRL_STIMERDEBUGRUN_X0 << 5) /**< Shifted mode X0 for RAC_SEQCTRL */
+#define RAC_SEQCTRL_STIMERDEBUGRUN_X1 (_RAC_SEQCTRL_STIMERDEBUGRUN_X1 << 5) /**< Shifted mode X1 for RAC_SEQCTRL */
+#define RAC_SEQCTRL_STATEDEBUGRUN (0x1UL << 6) /**< FSM state Debug Run */
+#define _RAC_SEQCTRL_STATEDEBUGRUN_SHIFT 6 /**< Shift value for RAC_STATEDEBUGRUN */
+#define _RAC_SEQCTRL_STATEDEBUGRUN_MASK 0x40UL /**< Bit mask for RAC_STATEDEBUGRUN */
+#define _RAC_SEQCTRL_STATEDEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQCTRL */
+#define _RAC_SEQCTRL_STATEDEBUGRUN_X0 0x00000000UL /**< Mode X0 for RAC_SEQCTRL */
+#define _RAC_SEQCTRL_STATEDEBUGRUN_X1 0x00000001UL /**< Mode X1 for RAC_SEQCTRL */
+#define RAC_SEQCTRL_STATEDEBUGRUN_DEFAULT (_RAC_SEQCTRL_STATEDEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_SEQCTRL */
+#define RAC_SEQCTRL_STATEDEBUGRUN_X0 (_RAC_SEQCTRL_STATEDEBUGRUN_X0 << 6) /**< Shifted mode X0 for RAC_SEQCTRL */
+#define RAC_SEQCTRL_STATEDEBUGRUN_X1 (_RAC_SEQCTRL_STATEDEBUGRUN_X1 << 6) /**< Shifted mode X1 for RAC_SEQCTRL */
+#define _RAC_SEQCTRL_SWIRQ_SHIFT 24 /**< Shift value for RAC_SWIRQ */
+#define _RAC_SEQCTRL_SWIRQ_MASK 0x3000000UL /**< Bit mask for RAC_SWIRQ */
+#define _RAC_SEQCTRL_SWIRQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SEQCTRL */
+#define RAC_SEQCTRL_SWIRQ_DEFAULT (_RAC_SEQCTRL_SWIRQ_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_SEQCTRL */
+
+/* Bit fields for RAC PRESC */
+#define _RAC_PRESC_RESETVALUE 0x00000007UL /**< Default value for RAC_PRESC */
+#define _RAC_PRESC_MASK 0x0000007FUL /**< Mask for RAC_PRESC */
+#define _RAC_PRESC_STIMER_SHIFT 0 /**< Shift value for RAC_STIMER */
+#define _RAC_PRESC_STIMER_MASK 0x7FUL /**< Bit mask for RAC_STIMER */
+#define _RAC_PRESC_STIMER_DEFAULT 0x00000007UL /**< Mode DEFAULT for RAC_PRESC */
+#define RAC_PRESC_STIMER_DEFAULT (_RAC_PRESC_STIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_PRESC */
+
+/* Bit fields for RAC SR0 */
+#define _RAC_SR0_RESETVALUE 0x00000000UL /**< Default value for RAC_SR0 */
+#define _RAC_SR0_MASK 0xFFFFFFFFUL /**< Mask for RAC_SR0 */
+#define _RAC_SR0_SR0_SHIFT 0 /**< Shift value for RAC_SR0 */
+#define _RAC_SR0_SR0_MASK 0xFFFFFFFFUL /**< Bit mask for RAC_SR0 */
+#define _RAC_SR0_SR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SR0 */
+#define RAC_SR0_SR0_DEFAULT (_RAC_SR0_SR0_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SR0 */
+
+/* Bit fields for RAC SR1 */
+#define _RAC_SR1_RESETVALUE 0x00000000UL /**< Default value for RAC_SR1 */
+#define _RAC_SR1_MASK 0xFFFFFFFFUL /**< Mask for RAC_SR1 */
+#define _RAC_SR1_SR1_SHIFT 0 /**< Shift value for RAC_SR1 */
+#define _RAC_SR1_SR1_MASK 0xFFFFFFFFUL /**< Bit mask for RAC_SR1 */
+#define _RAC_SR1_SR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SR1 */
+#define RAC_SR1_SR1_DEFAULT (_RAC_SR1_SR1_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SR1 */
+
+/* Bit fields for RAC SR2 */
+#define _RAC_SR2_RESETVALUE 0x00000000UL /**< Default value for RAC_SR2 */
+#define _RAC_SR2_MASK 0xFFFFFFFFUL /**< Mask for RAC_SR2 */
+#define _RAC_SR2_SR2_SHIFT 0 /**< Shift value for RAC_SR2 */
+#define _RAC_SR2_SR2_MASK 0xFFFFFFFFUL /**< Bit mask for RAC_SR2 */
+#define _RAC_SR2_SR2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SR2 */
+#define RAC_SR2_SR2_DEFAULT (_RAC_SR2_SR2_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SR2 */
+
+/* Bit fields for RAC SR3 */
+#define _RAC_SR3_RESETVALUE 0x00000000UL /**< Default value for RAC_SR3 */
+#define _RAC_SR3_MASK 0xFFFFFFFFUL /**< Mask for RAC_SR3 */
+#define _RAC_SR3_SR3_SHIFT 0 /**< Shift value for RAC_SR3 */
+#define _RAC_SR3_SR3_MASK 0xFFFFFFFFUL /**< Bit mask for RAC_SR3 */
+#define _RAC_SR3_SR3_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SR3 */
+#define RAC_SR3_SR3_DEFAULT (_RAC_SR3_SR3_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SR3 */
+
+/* Bit fields for RAC STCTRL */
+#define _RAC_STCTRL_RESETVALUE 0x00000000UL /**< Default value for RAC_STCTRL */
+#define _RAC_STCTRL_MASK 0x01FFFFFFUL /**< Mask for RAC_STCTRL */
+#define _RAC_STCTRL_STCAL_SHIFT 0 /**< Shift value for RAC_STCAL */
+#define _RAC_STCTRL_STCAL_MASK 0xFFFFFFUL /**< Bit mask for RAC_STCAL */
+#define _RAC_STCTRL_STCAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STCTRL */
+#define RAC_STCTRL_STCAL_DEFAULT (_RAC_STCTRL_STCAL_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_STCTRL */
+#define RAC_STCTRL_STSKEW (0x1UL << 24) /**< Systick timer skew */
+#define _RAC_STCTRL_STSKEW_SHIFT 24 /**< Shift value for RAC_STSKEW */
+#define _RAC_STCTRL_STSKEW_MASK 0x1000000UL /**< Bit mask for RAC_STSKEW */
+#define _RAC_STCTRL_STSKEW_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STCTRL */
+#define RAC_STCTRL_STSKEW_DEFAULT (_RAC_STCTRL_STSKEW_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_STCTRL */
+
+/* Bit fields for RAC FRCTXWORD */
+#define _RAC_FRCTXWORD_RESETVALUE 0x00000000UL /**< Default value for RAC_FRCTXWORD */
+#define _RAC_FRCTXWORD_MASK 0x000000FFUL /**< Mask for RAC_FRCTXWORD */
+#define _RAC_FRCTXWORD_WDATA_SHIFT 0 /**< Shift value for RAC_WDATA */
+#define _RAC_FRCTXWORD_WDATA_MASK 0xFFUL /**< Bit mask for RAC_WDATA */
+#define _RAC_FRCTXWORD_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_FRCTXWORD */
+#define RAC_FRCTXWORD_WDATA_DEFAULT (_RAC_FRCTXWORD_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_FRCTXWORD */
+
+/* Bit fields for RAC FRCRXWORD */
+#define _RAC_FRCRXWORD_RESETVALUE 0x00000000UL /**< Default value for RAC_FRCRXWORD */
+#define _RAC_FRCRXWORD_MASK 0x000000FFUL /**< Mask for RAC_FRCRXWORD */
+#define _RAC_FRCRXWORD_RDATA_SHIFT 0 /**< Shift value for RAC_RDATA */
+#define _RAC_FRCRXWORD_RDATA_MASK 0xFFUL /**< Bit mask for RAC_RDATA */
+#define _RAC_FRCRXWORD_RDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_FRCRXWORD */
+#define RAC_FRCRXWORD_RDATA_DEFAULT (_RAC_FRCRXWORD_RDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_FRCRXWORD */
+
+/* Bit fields for RAC EM1PCSR */
+#define _RAC_EM1PCSR_RESETVALUE 0x00000000UL /**< Default value for RAC_EM1PCSR */
+#define _RAC_EM1PCSR_MASK 0x00070033UL /**< Mask for RAC_EM1PCSR */
+#define RAC_EM1PCSR_RADIOEM1PMODE (0x1UL << 0) /**< */
+#define _RAC_EM1PCSR_RADIOEM1PMODE_SHIFT 0 /**< Shift value for RAC_RADIOEM1PMODE */
+#define _RAC_EM1PCSR_RADIOEM1PMODE_MASK 0x1UL /**< Bit mask for RAC_RADIOEM1PMODE */
+#define _RAC_EM1PCSR_RADIOEM1PMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_EM1PCSR */
+#define _RAC_EM1PCSR_RADIOEM1PMODE_HWCTRL 0x00000000UL /**< Mode HWCTRL for RAC_EM1PCSR */
+#define _RAC_EM1PCSR_RADIOEM1PMODE_SWCTRL 0x00000001UL /**< Mode SWCTRL for RAC_EM1PCSR */
+#define RAC_EM1PCSR_RADIOEM1PMODE_DEFAULT (_RAC_EM1PCSR_RADIOEM1PMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_EM1PCSR */
+#define RAC_EM1PCSR_RADIOEM1PMODE_HWCTRL (_RAC_EM1PCSR_RADIOEM1PMODE_HWCTRL << 0) /**< Shifted mode HWCTRL for RAC_EM1PCSR */
+#define RAC_EM1PCSR_RADIOEM1PMODE_SWCTRL (_RAC_EM1PCSR_RADIOEM1PMODE_SWCTRL << 0) /**< Shifted mode SWCTRL for RAC_EM1PCSR */
+#define RAC_EM1PCSR_RADIOEM1PDISSWREQ (0x1UL << 1) /**< */
+#define _RAC_EM1PCSR_RADIOEM1PDISSWREQ_SHIFT 1 /**< Shift value for RAC_RADIOEM1PDISSWREQ */
+#define _RAC_EM1PCSR_RADIOEM1PDISSWREQ_MASK 0x2UL /**< Bit mask for RAC_RADIOEM1PDISSWREQ */
+#define _RAC_EM1PCSR_RADIOEM1PDISSWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_EM1PCSR */
+#define RAC_EM1PCSR_RADIOEM1PDISSWREQ_DEFAULT (_RAC_EM1PCSR_RADIOEM1PDISSWREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_EM1PCSR */
+#define RAC_EM1PCSR_MCUEM1PMODE (0x1UL << 4) /**< */
+#define _RAC_EM1PCSR_MCUEM1PMODE_SHIFT 4 /**< Shift value for RAC_MCUEM1PMODE */
+#define _RAC_EM1PCSR_MCUEM1PMODE_MASK 0x10UL /**< Bit mask for RAC_MCUEM1PMODE */
+#define _RAC_EM1PCSR_MCUEM1PMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_EM1PCSR */
+#define _RAC_EM1PCSR_MCUEM1PMODE_HWCTRL 0x00000000UL /**< Mode HWCTRL for RAC_EM1PCSR */
+#define _RAC_EM1PCSR_MCUEM1PMODE_SWCTRL 0x00000001UL /**< Mode SWCTRL for RAC_EM1PCSR */
+#define RAC_EM1PCSR_MCUEM1PMODE_DEFAULT (_RAC_EM1PCSR_MCUEM1PMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_EM1PCSR */
+#define RAC_EM1PCSR_MCUEM1PMODE_HWCTRL (_RAC_EM1PCSR_MCUEM1PMODE_HWCTRL << 4) /**< Shifted mode HWCTRL for RAC_EM1PCSR */
+#define RAC_EM1PCSR_MCUEM1PMODE_SWCTRL (_RAC_EM1PCSR_MCUEM1PMODE_SWCTRL << 4) /**< Shifted mode SWCTRL for RAC_EM1PCSR */
+#define RAC_EM1PCSR_MCUEM1PDISSWREQ (0x1UL << 5) /**< */
+#define _RAC_EM1PCSR_MCUEM1PDISSWREQ_SHIFT 5 /**< Shift value for RAC_MCUEM1PDISSWREQ */
+#define _RAC_EM1PCSR_MCUEM1PDISSWREQ_MASK 0x20UL /**< Bit mask for RAC_MCUEM1PDISSWREQ */
+#define _RAC_EM1PCSR_MCUEM1PDISSWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_EM1PCSR */
+#define RAC_EM1PCSR_MCUEM1PDISSWREQ_DEFAULT (_RAC_EM1PCSR_MCUEM1PDISSWREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_EM1PCSR */
+#define RAC_EM1PCSR_RADIOEM1PREQ (0x1UL << 16) /**< */
+#define _RAC_EM1PCSR_RADIOEM1PREQ_SHIFT 16 /**< Shift value for RAC_RADIOEM1PREQ */
+#define _RAC_EM1PCSR_RADIOEM1PREQ_MASK 0x10000UL /**< Bit mask for RAC_RADIOEM1PREQ */
+#define _RAC_EM1PCSR_RADIOEM1PREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_EM1PCSR */
+#define RAC_EM1PCSR_RADIOEM1PREQ_DEFAULT (_RAC_EM1PCSR_RADIOEM1PREQ_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_EM1PCSR */
+#define RAC_EM1PCSR_RADIOEM1PACK (0x1UL << 17) /**< */
+#define _RAC_EM1PCSR_RADIOEM1PACK_SHIFT 17 /**< Shift value for RAC_RADIOEM1PACK */
+#define _RAC_EM1PCSR_RADIOEM1PACK_MASK 0x20000UL /**< Bit mask for RAC_RADIOEM1PACK */
+#define _RAC_EM1PCSR_RADIOEM1PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_EM1PCSR */
+#define RAC_EM1PCSR_RADIOEM1PACK_DEFAULT (_RAC_EM1PCSR_RADIOEM1PACK_DEFAULT << 17) /**< Shifted mode DEFAULT for RAC_EM1PCSR */
+#define RAC_EM1PCSR_RADIOEM1PHWREQ (0x1UL << 18) /**< */
+#define _RAC_EM1PCSR_RADIOEM1PHWREQ_SHIFT 18 /**< Shift value for RAC_RADIOEM1PHWREQ */
+#define _RAC_EM1PCSR_RADIOEM1PHWREQ_MASK 0x40000UL /**< Bit mask for RAC_RADIOEM1PHWREQ */
+#define _RAC_EM1PCSR_RADIOEM1PHWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_EM1PCSR */
+#define RAC_EM1PCSR_RADIOEM1PHWREQ_DEFAULT (_RAC_EM1PCSR_RADIOEM1PHWREQ_DEFAULT << 18) /**< Shifted mode DEFAULT for RAC_EM1PCSR */
+
+/* Bit fields for RAC SYNTHENCTRL */
+#define _RAC_SYNTHENCTRL_RESETVALUE 0x00000000UL /**< Default value for RAC_SYNTHENCTRL */
+#define _RAC_SYNTHENCTRL_MASK 0x00100682UL /**< Mask for RAC_SYNTHENCTRL */
+#define RAC_SYNTHENCTRL_VCOSTARTUP (0x1UL << 1) /**< SYVCOFASTSTARTUP */
+#define _RAC_SYNTHENCTRL_VCOSTARTUP_SHIFT 1 /**< Shift value for RAC_VCOSTARTUP */
+#define _RAC_SYNTHENCTRL_VCOSTARTUP_MASK 0x2UL /**< Bit mask for RAC_VCOSTARTUP */
+#define _RAC_SYNTHENCTRL_VCOSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYNTHENCTRL */
+#define _RAC_SYNTHENCTRL_VCOSTARTUP_fast_start_up_0 0x00000000UL /**< Mode fast_start_up_0 for RAC_SYNTHENCTRL */
+#define _RAC_SYNTHENCTRL_VCOSTARTUP_fast_start_up_1 0x00000001UL /**< Mode fast_start_up_1 for RAC_SYNTHENCTRL */
+#define RAC_SYNTHENCTRL_VCOSTARTUP_DEFAULT (_RAC_SYNTHENCTRL_VCOSTARTUP_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_SYNTHENCTRL */
+#define RAC_SYNTHENCTRL_VCOSTARTUP_fast_start_up_0 (_RAC_SYNTHENCTRL_VCOSTARTUP_fast_start_up_0 << 1) /**< Shifted mode fast_start_up_0 for RAC_SYNTHENCTRL*/
+#define RAC_SYNTHENCTRL_VCOSTARTUP_fast_start_up_1 (_RAC_SYNTHENCTRL_VCOSTARTUP_fast_start_up_1 << 1) /**< Shifted mode fast_start_up_1 for RAC_SYNTHENCTRL*/
+#define RAC_SYNTHENCTRL_VCBUFEN (0x1UL << 7) /**< SYLPFVCBUFEN */
+#define _RAC_SYNTHENCTRL_VCBUFEN_SHIFT 7 /**< Shift value for RAC_VCBUFEN */
+#define _RAC_SYNTHENCTRL_VCBUFEN_MASK 0x80UL /**< Bit mask for RAC_VCBUFEN */
+#define _RAC_SYNTHENCTRL_VCBUFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYNTHENCTRL */
+#define _RAC_SYNTHENCTRL_VCBUFEN_Disabled 0x00000000UL /**< Mode Disabled for RAC_SYNTHENCTRL */
+#define _RAC_SYNTHENCTRL_VCBUFEN_Enabled 0x00000001UL /**< Mode Enabled for RAC_SYNTHENCTRL */
+#define RAC_SYNTHENCTRL_VCBUFEN_DEFAULT (_RAC_SYNTHENCTRL_VCBUFEN_DEFAULT << 7) /**< Shifted mode DEFAULT for RAC_SYNTHENCTRL */
+#define RAC_SYNTHENCTRL_VCBUFEN_Disabled (_RAC_SYNTHENCTRL_VCBUFEN_Disabled << 7) /**< Shifted mode Disabled for RAC_SYNTHENCTRL */
+#define RAC_SYNTHENCTRL_VCBUFEN_Enabled (_RAC_SYNTHENCTRL_VCBUFEN_Enabled << 7) /**< Shifted mode Enabled for RAC_SYNTHENCTRL */
+#define RAC_SYNTHENCTRL_MMDPOWERBALANCEDISABLE (0x1UL << 10) /**< SYMMDPOWERBALANCEENB */
+#define _RAC_SYNTHENCTRL_MMDPOWERBALANCEDISABLE_SHIFT 10 /**< Shift value for RAC_MMDPOWERBALANCEDISABLE */
+#define _RAC_SYNTHENCTRL_MMDPOWERBALANCEDISABLE_MASK 0x400UL /**< Bit mask for RAC_MMDPOWERBALANCEDISABLE */
+#define _RAC_SYNTHENCTRL_MMDPOWERBALANCEDISABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYNTHENCTRL */
+#define _RAC_SYNTHENCTRL_MMDPOWERBALANCEDISABLE_EnablePowerbleed 0x00000000UL /**< Mode EnablePowerbleed for RAC_SYNTHENCTRL */
+#define _RAC_SYNTHENCTRL_MMDPOWERBALANCEDISABLE_DisablePowerBleed 0x00000001UL /**< Mode DisablePowerBleed for RAC_SYNTHENCTRL */
+#define RAC_SYNTHENCTRL_MMDPOWERBALANCEDISABLE_DEFAULT (_RAC_SYNTHENCTRL_MMDPOWERBALANCEDISABLE_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_SYNTHENCTRL */
+#define RAC_SYNTHENCTRL_MMDPOWERBALANCEDISABLE_EnablePowerbleed (_RAC_SYNTHENCTRL_MMDPOWERBALANCEDISABLE_EnablePowerbleed << 10) /**< Shifted mode EnablePowerbleed for RAC_SYNTHENCTRL*/
+#define RAC_SYNTHENCTRL_MMDPOWERBALANCEDISABLE_DisablePowerBleed (_RAC_SYNTHENCTRL_MMDPOWERBALANCEDISABLE_DisablePowerBleed << 10) /**< Shifted mode DisablePowerBleed for RAC_SYNTHENCTRL*/
+#define RAC_SYNTHENCTRL_LPFBWSEL (0x1UL << 20) /**< LPF bandwidth register selection */
+#define _RAC_SYNTHENCTRL_LPFBWSEL_SHIFT 20 /**< Shift value for RAC_LPFBWSEL */
+#define _RAC_SYNTHENCTRL_LPFBWSEL_MASK 0x100000UL /**< Bit mask for RAC_LPFBWSEL */
+#define _RAC_SYNTHENCTRL_LPFBWSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYNTHENCTRL */
+#define _RAC_SYNTHENCTRL_LPFBWSEL_LPFBWRX 0x00000000UL /**< Mode LPFBWRX for RAC_SYNTHENCTRL */
+#define _RAC_SYNTHENCTRL_LPFBWSEL_LPFBWTX 0x00000001UL /**< Mode LPFBWTX for RAC_SYNTHENCTRL */
+#define RAC_SYNTHENCTRL_LPFBWSEL_DEFAULT (_RAC_SYNTHENCTRL_LPFBWSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for RAC_SYNTHENCTRL */
+#define RAC_SYNTHENCTRL_LPFBWSEL_LPFBWRX (_RAC_SYNTHENCTRL_LPFBWSEL_LPFBWRX << 20) /**< Shifted mode LPFBWRX for RAC_SYNTHENCTRL */
+#define RAC_SYNTHENCTRL_LPFBWSEL_LPFBWTX (_RAC_SYNTHENCTRL_LPFBWSEL_LPFBWTX << 20) /**< Shifted mode LPFBWTX for RAC_SYNTHENCTRL */
+
+/* Bit fields for RAC SYNTHREGCTRL */
+#define _RAC_SYNTHREGCTRL_RESETVALUE 0x04000000UL /**< Default value for RAC_SYNTHREGCTRL */
+#define _RAC_SYNTHREGCTRL_MASK 0x07001C00UL /**< Mask for RAC_SYNTHREGCTRL */
+#define _RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_SHIFT 10 /**< Shift value for RAC_MMDLDOVREFTRIM */
+#define _RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_MASK 0x1C00UL /**< Bit mask for RAC_MMDLDOVREFTRIM */
+#define _RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYNTHREGCTRL */
+#define _RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6000 0x00000000UL /**< Mode vref0p6000 for RAC_SYNTHREGCTRL */
+#define _RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6125 0x00000001UL /**< Mode vref0p6125 for RAC_SYNTHREGCTRL */
+#define _RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6250 0x00000002UL /**< Mode vref0p6250 for RAC_SYNTHREGCTRL */
+#define _RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6375 0x00000003UL /**< Mode vref0p6375 for RAC_SYNTHREGCTRL */
+#define _RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6500 0x00000004UL /**< Mode vref0p6500 for RAC_SYNTHREGCTRL */
+#define _RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6625 0x00000005UL /**< Mode vref0p6625 for RAC_SYNTHREGCTRL */
+#define _RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6750 0x00000006UL /**< Mode vref0p6750 for RAC_SYNTHREGCTRL */
+#define _RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6875 0x00000007UL /**< Mode vref0p6875 for RAC_SYNTHREGCTRL */
+#define RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_DEFAULT (_RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_SYNTHREGCTRL */
+#define RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6000 (_RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6000 << 10) /**< Shifted mode vref0p6000 for RAC_SYNTHREGCTRL*/
+#define RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6125 (_RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6125 << 10) /**< Shifted mode vref0p6125 for RAC_SYNTHREGCTRL*/
+#define RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6250 (_RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6250 << 10) /**< Shifted mode vref0p6250 for RAC_SYNTHREGCTRL*/
+#define RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6375 (_RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6375 << 10) /**< Shifted mode vref0p6375 for RAC_SYNTHREGCTRL*/
+#define RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6500 (_RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6500 << 10) /**< Shifted mode vref0p6500 for RAC_SYNTHREGCTRL*/
+#define RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6625 (_RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6625 << 10) /**< Shifted mode vref0p6625 for RAC_SYNTHREGCTRL*/
+#define RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6750 (_RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6750 << 10) /**< Shifted mode vref0p6750 for RAC_SYNTHREGCTRL*/
+#define RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6875 (_RAC_SYNTHREGCTRL_MMDLDOVREFTRIM_vref0p6875 << 10) /**< Shifted mode vref0p6875 for RAC_SYNTHREGCTRL*/
+#define _RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_SHIFT 24 /**< Shift value for RAC_CHPLDOVREFTRIM */
+#define _RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_MASK 0x7000000UL /**< Bit mask for RAC_CHPLDOVREFTRIM */
+#define _RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_DEFAULT 0x00000004UL /**< Mode DEFAULT for RAC_SYNTHREGCTRL */
+#define _RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6000 0x00000000UL /**< Mode vref0p6000 for RAC_SYNTHREGCTRL */
+#define _RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6125 0x00000001UL /**< Mode vref0p6125 for RAC_SYNTHREGCTRL */
+#define _RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6250 0x00000002UL /**< Mode vref0p6250 for RAC_SYNTHREGCTRL */
+#define _RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6375 0x00000003UL /**< Mode vref0p6375 for RAC_SYNTHREGCTRL */
+#define _RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6500 0x00000004UL /**< Mode vref0p6500 for RAC_SYNTHREGCTRL */
+#define _RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6625 0x00000005UL /**< Mode vref0p6625 for RAC_SYNTHREGCTRL */
+#define _RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6750 0x00000006UL /**< Mode vref0p6750 for RAC_SYNTHREGCTRL */
+#define _RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6875 0x00000007UL /**< Mode vref0p6875 for RAC_SYNTHREGCTRL */
+#define RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_DEFAULT (_RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_SYNTHREGCTRL */
+#define RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6000 (_RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6000 << 24) /**< Shifted mode vref0p6000 for RAC_SYNTHREGCTRL*/
+#define RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6125 (_RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6125 << 24) /**< Shifted mode vref0p6125 for RAC_SYNTHREGCTRL*/
+#define RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6250 (_RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6250 << 24) /**< Shifted mode vref0p6250 for RAC_SYNTHREGCTRL*/
+#define RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6375 (_RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6375 << 24) /**< Shifted mode vref0p6375 for RAC_SYNTHREGCTRL*/
+#define RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6500 (_RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6500 << 24) /**< Shifted mode vref0p6500 for RAC_SYNTHREGCTRL*/
+#define RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6625 (_RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6625 << 24) /**< Shifted mode vref0p6625 for RAC_SYNTHREGCTRL*/
+#define RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6750 (_RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6750 << 24) /**< Shifted mode vref0p6750 for RAC_SYNTHREGCTRL*/
+#define RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6875 (_RAC_SYNTHREGCTRL_CHPLDOVREFTRIM_vref0p6875 << 24) /**< Shifted mode vref0p6875 for RAC_SYNTHREGCTRL*/
+
+/* Bit fields for RAC VCOCTRL */
+#define _RAC_VCOCTRL_RESETVALUE 0x0000044CUL /**< Default value for RAC_VCOCTRL */
+#define _RAC_VCOCTRL_MASK 0x00000FFFUL /**< Mask for RAC_VCOCTRL */
+#define _RAC_VCOCTRL_VCOAMPLITUDE_SHIFT 0 /**< Shift value for RAC_VCOAMPLITUDE */
+#define _RAC_VCOCTRL_VCOAMPLITUDE_MASK 0xFUL /**< Bit mask for RAC_VCOAMPLITUDE */
+#define _RAC_VCOCTRL_VCOAMPLITUDE_DEFAULT 0x0000000CUL /**< Mode DEFAULT for RAC_VCOCTRL */
+#define RAC_VCOCTRL_VCOAMPLITUDE_DEFAULT (_RAC_VCOCTRL_VCOAMPLITUDE_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_VCOCTRL */
+#define _RAC_VCOCTRL_VCODETAMPLITUDERX_SHIFT 4 /**< Shift value for RAC_VCODETAMPLITUDERX */
+#define _RAC_VCOCTRL_VCODETAMPLITUDERX_MASK 0xF0UL /**< Bit mask for RAC_VCODETAMPLITUDERX */
+#define _RAC_VCOCTRL_VCODETAMPLITUDERX_DEFAULT 0x00000004UL /**< Mode DEFAULT for RAC_VCOCTRL */
+#define RAC_VCOCTRL_VCODETAMPLITUDERX_DEFAULT (_RAC_VCOCTRL_VCODETAMPLITUDERX_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_VCOCTRL */
+#define _RAC_VCOCTRL_VCODETAMPLITUDETX_SHIFT 8 /**< Shift value for RAC_VCODETAMPLITUDETX */
+#define _RAC_VCOCTRL_VCODETAMPLITUDETX_MASK 0xF00UL /**< Bit mask for RAC_VCODETAMPLITUDETX */
+#define _RAC_VCOCTRL_VCODETAMPLITUDETX_DEFAULT 0x00000004UL /**< Mode DEFAULT for RAC_VCOCTRL */
+#define RAC_VCOCTRL_VCODETAMPLITUDETX_DEFAULT (_RAC_VCOCTRL_VCODETAMPLITUDETX_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_VCOCTRL */
+
+/* Bit fields for RAC STATUS2 */
+#define _RAC_STATUS2_RESETVALUE 0x00000000UL /**< Default value for RAC_STATUS2 */
+#define _RAC_STATUS2_MASK 0x0000FFFFUL /**< Mask for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE1_SHIFT 0 /**< Shift value for RAC_PREVSTATE1 */
+#define _RAC_STATUS2_PREVSTATE1_MASK 0xFUL /**< Bit mask for RAC_PREVSTATE1 */
+#define _RAC_STATUS2_PREVSTATE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE1_OFF 0x00000000UL /**< Mode OFF for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE1_RXWARM 0x00000001UL /**< Mode RXWARM for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE1_RXSEARCH 0x00000002UL /**< Mode RXSEARCH for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE1_RXFRAME 0x00000003UL /**< Mode RXFRAME for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE1_RXPD 0x00000004UL /**< Mode RXPD for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE1_RX2RX 0x00000005UL /**< Mode RX2RX for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE1_RXOVERFLOW 0x00000006UL /**< Mode RXOVERFLOW for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE1_RX2TX 0x00000007UL /**< Mode RX2TX for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE1_TXWARM 0x00000008UL /**< Mode TXWARM for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE1_TX 0x00000009UL /**< Mode TX for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE1_TXPD 0x0000000AUL /**< Mode TXPD for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE1_TX2RX 0x0000000BUL /**< Mode TX2RX for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE1_TX2TX 0x0000000CUL /**< Mode TX2TX for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE1_SHUTDOWN 0x0000000DUL /**< Mode SHUTDOWN for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE1_POR 0x0000000EUL /**< Mode POR for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE1_DEFAULT (_RAC_STATUS2_PREVSTATE1_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE1_OFF (_RAC_STATUS2_PREVSTATE1_OFF << 0) /**< Shifted mode OFF for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE1_RXWARM (_RAC_STATUS2_PREVSTATE1_RXWARM << 0) /**< Shifted mode RXWARM for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE1_RXSEARCH (_RAC_STATUS2_PREVSTATE1_RXSEARCH << 0) /**< Shifted mode RXSEARCH for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE1_RXFRAME (_RAC_STATUS2_PREVSTATE1_RXFRAME << 0) /**< Shifted mode RXFRAME for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE1_RXPD (_RAC_STATUS2_PREVSTATE1_RXPD << 0) /**< Shifted mode RXPD for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE1_RX2RX (_RAC_STATUS2_PREVSTATE1_RX2RX << 0) /**< Shifted mode RX2RX for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE1_RXOVERFLOW (_RAC_STATUS2_PREVSTATE1_RXOVERFLOW << 0) /**< Shifted mode RXOVERFLOW for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE1_RX2TX (_RAC_STATUS2_PREVSTATE1_RX2TX << 0) /**< Shifted mode RX2TX for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE1_TXWARM (_RAC_STATUS2_PREVSTATE1_TXWARM << 0) /**< Shifted mode TXWARM for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE1_TX (_RAC_STATUS2_PREVSTATE1_TX << 0) /**< Shifted mode TX for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE1_TXPD (_RAC_STATUS2_PREVSTATE1_TXPD << 0) /**< Shifted mode TXPD for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE1_TX2RX (_RAC_STATUS2_PREVSTATE1_TX2RX << 0) /**< Shifted mode TX2RX for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE1_TX2TX (_RAC_STATUS2_PREVSTATE1_TX2TX << 0) /**< Shifted mode TX2TX for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE1_SHUTDOWN (_RAC_STATUS2_PREVSTATE1_SHUTDOWN << 0) /**< Shifted mode SHUTDOWN for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE1_POR (_RAC_STATUS2_PREVSTATE1_POR << 0) /**< Shifted mode POR for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE2_SHIFT 4 /**< Shift value for RAC_PREVSTATE2 */
+#define _RAC_STATUS2_PREVSTATE2_MASK 0xF0UL /**< Bit mask for RAC_PREVSTATE2 */
+#define _RAC_STATUS2_PREVSTATE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE2_OFF 0x00000000UL /**< Mode OFF for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE2_RXWARM 0x00000001UL /**< Mode RXWARM for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE2_RXSEARCH 0x00000002UL /**< Mode RXSEARCH for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE2_RXFRAME 0x00000003UL /**< Mode RXFRAME for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE2_RXPD 0x00000004UL /**< Mode RXPD for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE2_RX2RX 0x00000005UL /**< Mode RX2RX for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE2_RXOVERFLOW 0x00000006UL /**< Mode RXOVERFLOW for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE2_RX2TX 0x00000007UL /**< Mode RX2TX for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE2_TXWARM 0x00000008UL /**< Mode TXWARM for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE2_TX 0x00000009UL /**< Mode TX for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE2_TXPD 0x0000000AUL /**< Mode TXPD for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE2_TX2RX 0x0000000BUL /**< Mode TX2RX for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE2_TX2TX 0x0000000CUL /**< Mode TX2TX for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE2_SHUTDOWN 0x0000000DUL /**< Mode SHUTDOWN for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE2_POR 0x0000000EUL /**< Mode POR for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE2_DEFAULT (_RAC_STATUS2_PREVSTATE2_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE2_OFF (_RAC_STATUS2_PREVSTATE2_OFF << 4) /**< Shifted mode OFF for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE2_RXWARM (_RAC_STATUS2_PREVSTATE2_RXWARM << 4) /**< Shifted mode RXWARM for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE2_RXSEARCH (_RAC_STATUS2_PREVSTATE2_RXSEARCH << 4) /**< Shifted mode RXSEARCH for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE2_RXFRAME (_RAC_STATUS2_PREVSTATE2_RXFRAME << 4) /**< Shifted mode RXFRAME for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE2_RXPD (_RAC_STATUS2_PREVSTATE2_RXPD << 4) /**< Shifted mode RXPD for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE2_RX2RX (_RAC_STATUS2_PREVSTATE2_RX2RX << 4) /**< Shifted mode RX2RX for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE2_RXOVERFLOW (_RAC_STATUS2_PREVSTATE2_RXOVERFLOW << 4) /**< Shifted mode RXOVERFLOW for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE2_RX2TX (_RAC_STATUS2_PREVSTATE2_RX2TX << 4) /**< Shifted mode RX2TX for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE2_TXWARM (_RAC_STATUS2_PREVSTATE2_TXWARM << 4) /**< Shifted mode TXWARM for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE2_TX (_RAC_STATUS2_PREVSTATE2_TX << 4) /**< Shifted mode TX for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE2_TXPD (_RAC_STATUS2_PREVSTATE2_TXPD << 4) /**< Shifted mode TXPD for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE2_TX2RX (_RAC_STATUS2_PREVSTATE2_TX2RX << 4) /**< Shifted mode TX2RX for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE2_TX2TX (_RAC_STATUS2_PREVSTATE2_TX2TX << 4) /**< Shifted mode TX2TX for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE2_SHUTDOWN (_RAC_STATUS2_PREVSTATE2_SHUTDOWN << 4) /**< Shifted mode SHUTDOWN for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE2_POR (_RAC_STATUS2_PREVSTATE2_POR << 4) /**< Shifted mode POR for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE3_SHIFT 8 /**< Shift value for RAC_PREVSTATE3 */
+#define _RAC_STATUS2_PREVSTATE3_MASK 0xF00UL /**< Bit mask for RAC_PREVSTATE3 */
+#define _RAC_STATUS2_PREVSTATE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE3_OFF 0x00000000UL /**< Mode OFF for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE3_RXWARM 0x00000001UL /**< Mode RXWARM for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE3_RXSEARCH 0x00000002UL /**< Mode RXSEARCH for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE3_RXFRAME 0x00000003UL /**< Mode RXFRAME for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE3_RXPD 0x00000004UL /**< Mode RXPD for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE3_RX2RX 0x00000005UL /**< Mode RX2RX for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE3_RXOVERFLOW 0x00000006UL /**< Mode RXOVERFLOW for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE3_RX2TX 0x00000007UL /**< Mode RX2TX for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE3_TXWARM 0x00000008UL /**< Mode TXWARM for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE3_TX 0x00000009UL /**< Mode TX for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE3_TXPD 0x0000000AUL /**< Mode TXPD for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE3_TX2RX 0x0000000BUL /**< Mode TX2RX for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE3_TX2TX 0x0000000CUL /**< Mode TX2TX for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE3_SHUTDOWN 0x0000000DUL /**< Mode SHUTDOWN for RAC_STATUS2 */
+#define _RAC_STATUS2_PREVSTATE3_POR 0x0000000EUL /**< Mode POR for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE3_DEFAULT (_RAC_STATUS2_PREVSTATE3_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE3_OFF (_RAC_STATUS2_PREVSTATE3_OFF << 8) /**< Shifted mode OFF for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE3_RXWARM (_RAC_STATUS2_PREVSTATE3_RXWARM << 8) /**< Shifted mode RXWARM for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE3_RXSEARCH (_RAC_STATUS2_PREVSTATE3_RXSEARCH << 8) /**< Shifted mode RXSEARCH for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE3_RXFRAME (_RAC_STATUS2_PREVSTATE3_RXFRAME << 8) /**< Shifted mode RXFRAME for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE3_RXPD (_RAC_STATUS2_PREVSTATE3_RXPD << 8) /**< Shifted mode RXPD for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE3_RX2RX (_RAC_STATUS2_PREVSTATE3_RX2RX << 8) /**< Shifted mode RX2RX for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE3_RXOVERFLOW (_RAC_STATUS2_PREVSTATE3_RXOVERFLOW << 8) /**< Shifted mode RXOVERFLOW for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE3_RX2TX (_RAC_STATUS2_PREVSTATE3_RX2TX << 8) /**< Shifted mode RX2TX for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE3_TXWARM (_RAC_STATUS2_PREVSTATE3_TXWARM << 8) /**< Shifted mode TXWARM for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE3_TX (_RAC_STATUS2_PREVSTATE3_TX << 8) /**< Shifted mode TX for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE3_TXPD (_RAC_STATUS2_PREVSTATE3_TXPD << 8) /**< Shifted mode TXPD for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE3_TX2RX (_RAC_STATUS2_PREVSTATE3_TX2RX << 8) /**< Shifted mode TX2RX for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE3_TX2TX (_RAC_STATUS2_PREVSTATE3_TX2TX << 8) /**< Shifted mode TX2TX for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE3_SHUTDOWN (_RAC_STATUS2_PREVSTATE3_SHUTDOWN << 8) /**< Shifted mode SHUTDOWN for RAC_STATUS2 */
+#define RAC_STATUS2_PREVSTATE3_POR (_RAC_STATUS2_PREVSTATE3_POR << 8) /**< Shifted mode POR for RAC_STATUS2 */
+#define _RAC_STATUS2_CURRSTATE_SHIFT 12 /**< Shift value for RAC_CURRSTATE */
+#define _RAC_STATUS2_CURRSTATE_MASK 0xF000UL /**< Bit mask for RAC_CURRSTATE */
+#define _RAC_STATUS2_CURRSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_STATUS2 */
+#define _RAC_STATUS2_CURRSTATE_OFF 0x00000000UL /**< Mode OFF for RAC_STATUS2 */
+#define _RAC_STATUS2_CURRSTATE_RXWARM 0x00000001UL /**< Mode RXWARM for RAC_STATUS2 */
+#define _RAC_STATUS2_CURRSTATE_RXSEARCH 0x00000002UL /**< Mode RXSEARCH for RAC_STATUS2 */
+#define _RAC_STATUS2_CURRSTATE_RXFRAME 0x00000003UL /**< Mode RXFRAME for RAC_STATUS2 */
+#define _RAC_STATUS2_CURRSTATE_RXPD 0x00000004UL /**< Mode RXPD for RAC_STATUS2 */
+#define _RAC_STATUS2_CURRSTATE_RX2RX 0x00000005UL /**< Mode RX2RX for RAC_STATUS2 */
+#define _RAC_STATUS2_CURRSTATE_RXOVERFLOW 0x00000006UL /**< Mode RXOVERFLOW for RAC_STATUS2 */
+#define _RAC_STATUS2_CURRSTATE_RX2TX 0x00000007UL /**< Mode RX2TX for RAC_STATUS2 */
+#define _RAC_STATUS2_CURRSTATE_TXWARM 0x00000008UL /**< Mode TXWARM for RAC_STATUS2 */
+#define _RAC_STATUS2_CURRSTATE_TX 0x00000009UL /**< Mode TX for RAC_STATUS2 */
+#define _RAC_STATUS2_CURRSTATE_TXPD 0x0000000AUL /**< Mode TXPD for RAC_STATUS2 */
+#define _RAC_STATUS2_CURRSTATE_TX2RX 0x0000000BUL /**< Mode TX2RX for RAC_STATUS2 */
+#define _RAC_STATUS2_CURRSTATE_TX2TX 0x0000000CUL /**< Mode TX2TX for RAC_STATUS2 */
+#define _RAC_STATUS2_CURRSTATE_SHUTDOWN 0x0000000DUL /**< Mode SHUTDOWN for RAC_STATUS2 */
+#define _RAC_STATUS2_CURRSTATE_POR 0x0000000EUL /**< Mode POR for RAC_STATUS2 */
+#define RAC_STATUS2_CURRSTATE_DEFAULT (_RAC_STATUS2_CURRSTATE_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_STATUS2 */
+#define RAC_STATUS2_CURRSTATE_OFF (_RAC_STATUS2_CURRSTATE_OFF << 12) /**< Shifted mode OFF for RAC_STATUS2 */
+#define RAC_STATUS2_CURRSTATE_RXWARM (_RAC_STATUS2_CURRSTATE_RXWARM << 12) /**< Shifted mode RXWARM for RAC_STATUS2 */
+#define RAC_STATUS2_CURRSTATE_RXSEARCH (_RAC_STATUS2_CURRSTATE_RXSEARCH << 12) /**< Shifted mode RXSEARCH for RAC_STATUS2 */
+#define RAC_STATUS2_CURRSTATE_RXFRAME (_RAC_STATUS2_CURRSTATE_RXFRAME << 12) /**< Shifted mode RXFRAME for RAC_STATUS2 */
+#define RAC_STATUS2_CURRSTATE_RXPD (_RAC_STATUS2_CURRSTATE_RXPD << 12) /**< Shifted mode RXPD for RAC_STATUS2 */
+#define RAC_STATUS2_CURRSTATE_RX2RX (_RAC_STATUS2_CURRSTATE_RX2RX << 12) /**< Shifted mode RX2RX for RAC_STATUS2 */
+#define RAC_STATUS2_CURRSTATE_RXOVERFLOW (_RAC_STATUS2_CURRSTATE_RXOVERFLOW << 12) /**< Shifted mode RXOVERFLOW for RAC_STATUS2 */
+#define RAC_STATUS2_CURRSTATE_RX2TX (_RAC_STATUS2_CURRSTATE_RX2TX << 12) /**< Shifted mode RX2TX for RAC_STATUS2 */
+#define RAC_STATUS2_CURRSTATE_TXWARM (_RAC_STATUS2_CURRSTATE_TXWARM << 12) /**< Shifted mode TXWARM for RAC_STATUS2 */
+#define RAC_STATUS2_CURRSTATE_TX (_RAC_STATUS2_CURRSTATE_TX << 12) /**< Shifted mode TX for RAC_STATUS2 */
+#define RAC_STATUS2_CURRSTATE_TXPD (_RAC_STATUS2_CURRSTATE_TXPD << 12) /**< Shifted mode TXPD for RAC_STATUS2 */
+#define RAC_STATUS2_CURRSTATE_TX2RX (_RAC_STATUS2_CURRSTATE_TX2RX << 12) /**< Shifted mode TX2RX for RAC_STATUS2 */
+#define RAC_STATUS2_CURRSTATE_TX2TX (_RAC_STATUS2_CURRSTATE_TX2TX << 12) /**< Shifted mode TX2TX for RAC_STATUS2 */
+#define RAC_STATUS2_CURRSTATE_SHUTDOWN (_RAC_STATUS2_CURRSTATE_SHUTDOWN << 12) /**< Shifted mode SHUTDOWN for RAC_STATUS2 */
+#define RAC_STATUS2_CURRSTATE_POR (_RAC_STATUS2_CURRSTATE_POR << 12) /**< Shifted mode POR for RAC_STATUS2 */
+
+/* Bit fields for RAC IFPGACTRL */
+#define _RAC_IFPGACTRL_RESETVALUE 0x00000000UL /**< Default value for RAC_IFPGACTRL */
+#define _RAC_IFPGACTRL_MASK 0x0FF80000UL /**< Mask for RAC_IFPGACTRL */
+#define RAC_IFPGACTRL_DCCALON (0x1UL << 19) /**< Enable/Disable DCCAL in DEMOD */
+#define _RAC_IFPGACTRL_DCCALON_SHIFT 19 /**< Shift value for RAC_DCCALON */
+#define _RAC_IFPGACTRL_DCCALON_MASK 0x80000UL /**< Bit mask for RAC_DCCALON */
+#define _RAC_IFPGACTRL_DCCALON_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IFPGACTRL */
+#define _RAC_IFPGACTRL_DCCALON_DISABLE 0x00000000UL /**< Mode DISABLE for RAC_IFPGACTRL */
+#define _RAC_IFPGACTRL_DCCALON_ENABLE 0x00000001UL /**< Mode ENABLE for RAC_IFPGACTRL */
+#define RAC_IFPGACTRL_DCCALON_DEFAULT (_RAC_IFPGACTRL_DCCALON_DEFAULT << 19) /**< Shifted mode DEFAULT for RAC_IFPGACTRL */
+#define RAC_IFPGACTRL_DCCALON_DISABLE (_RAC_IFPGACTRL_DCCALON_DISABLE << 19) /**< Shifted mode DISABLE for RAC_IFPGACTRL */
+#define RAC_IFPGACTRL_DCCALON_ENABLE (_RAC_IFPGACTRL_DCCALON_ENABLE << 19) /**< Shifted mode ENABLE for RAC_IFPGACTRL */
+#define RAC_IFPGACTRL_DCRSTEN (0x1UL << 20) /**< DC Compensation Filter Reset Enable */
+#define _RAC_IFPGACTRL_DCRSTEN_SHIFT 20 /**< Shift value for RAC_DCRSTEN */
+#define _RAC_IFPGACTRL_DCRSTEN_MASK 0x100000UL /**< Bit mask for RAC_DCRSTEN */
+#define _RAC_IFPGACTRL_DCRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IFPGACTRL */
+#define _RAC_IFPGACTRL_DCRSTEN_DISABLE 0x00000000UL /**< Mode DISABLE for RAC_IFPGACTRL */
+#define _RAC_IFPGACTRL_DCRSTEN_ENABLE 0x00000001UL /**< Mode ENABLE for RAC_IFPGACTRL */
+#define RAC_IFPGACTRL_DCRSTEN_DEFAULT (_RAC_IFPGACTRL_DCRSTEN_DEFAULT << 20) /**< Shifted mode DEFAULT for RAC_IFPGACTRL */
+#define RAC_IFPGACTRL_DCRSTEN_DISABLE (_RAC_IFPGACTRL_DCRSTEN_DISABLE << 20) /**< Shifted mode DISABLE for RAC_IFPGACTRL */
+#define RAC_IFPGACTRL_DCRSTEN_ENABLE (_RAC_IFPGACTRL_DCRSTEN_ENABLE << 20) /**< Shifted mode ENABLE for RAC_IFPGACTRL */
+#define RAC_IFPGACTRL_DCESTIEN (0x1UL << 21) /**< DCESTIEN Override for RAC */
+#define _RAC_IFPGACTRL_DCESTIEN_SHIFT 21 /**< Shift value for RAC_DCESTIEN */
+#define _RAC_IFPGACTRL_DCESTIEN_MASK 0x200000UL /**< Bit mask for RAC_DCESTIEN */
+#define _RAC_IFPGACTRL_DCESTIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IFPGACTRL */
+#define _RAC_IFPGACTRL_DCESTIEN_DISABLE 0x00000000UL /**< Mode DISABLE for RAC_IFPGACTRL */
+#define _RAC_IFPGACTRL_DCESTIEN_ENABLE 0x00000001UL /**< Mode ENABLE for RAC_IFPGACTRL */
+#define RAC_IFPGACTRL_DCESTIEN_DEFAULT (_RAC_IFPGACTRL_DCESTIEN_DEFAULT << 21) /**< Shifted mode DEFAULT for RAC_IFPGACTRL */
+#define RAC_IFPGACTRL_DCESTIEN_DISABLE (_RAC_IFPGACTRL_DCESTIEN_DISABLE << 21) /**< Shifted mode DISABLE for RAC_IFPGACTRL */
+#define RAC_IFPGACTRL_DCESTIEN_ENABLE (_RAC_IFPGACTRL_DCESTIEN_ENABLE << 21) /**< Shifted mode ENABLE for RAC_IFPGACTRL */
+#define _RAC_IFPGACTRL_DCCALDEC0_SHIFT 22 /**< Shift value for RAC_DCCALDEC0 */
+#define _RAC_IFPGACTRL_DCCALDEC0_MASK 0x1C00000UL /**< Bit mask for RAC_DCCALDEC0 */
+#define _RAC_IFPGACTRL_DCCALDEC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IFPGACTRL */
+#define _RAC_IFPGACTRL_DCCALDEC0_DF3 0x00000000UL /**< Mode DF3 for RAC_IFPGACTRL */
+#define _RAC_IFPGACTRL_DCCALDEC0_DF4WIDE 0x00000001UL /**< Mode DF4WIDE for RAC_IFPGACTRL */
+#define _RAC_IFPGACTRL_DCCALDEC0_DF4NARROW 0x00000002UL /**< Mode DF4NARROW for RAC_IFPGACTRL */
+#define _RAC_IFPGACTRL_DCCALDEC0_DF8WIDE 0x00000003UL /**< Mode DF8WIDE for RAC_IFPGACTRL */
+#define _RAC_IFPGACTRL_DCCALDEC0_DF8NARROW 0x00000004UL /**< Mode DF8NARROW for RAC_IFPGACTRL */
+#define RAC_IFPGACTRL_DCCALDEC0_DEFAULT (_RAC_IFPGACTRL_DCCALDEC0_DEFAULT << 22) /**< Shifted mode DEFAULT for RAC_IFPGACTRL */
+#define RAC_IFPGACTRL_DCCALDEC0_DF3 (_RAC_IFPGACTRL_DCCALDEC0_DF3 << 22) /**< Shifted mode DF3 for RAC_IFPGACTRL */
+#define RAC_IFPGACTRL_DCCALDEC0_DF4WIDE (_RAC_IFPGACTRL_DCCALDEC0_DF4WIDE << 22) /**< Shifted mode DF4WIDE for RAC_IFPGACTRL */
+#define RAC_IFPGACTRL_DCCALDEC0_DF4NARROW (_RAC_IFPGACTRL_DCCALDEC0_DF4NARROW << 22) /**< Shifted mode DF4NARROW for RAC_IFPGACTRL */
+#define RAC_IFPGACTRL_DCCALDEC0_DF8WIDE (_RAC_IFPGACTRL_DCCALDEC0_DF8WIDE << 22) /**< Shifted mode DF8WIDE for RAC_IFPGACTRL */
+#define RAC_IFPGACTRL_DCCALDEC0_DF8NARROW (_RAC_IFPGACTRL_DCCALDEC0_DF8NARROW << 22) /**< Shifted mode DF8NARROW for RAC_IFPGACTRL */
+#define _RAC_IFPGACTRL_DCCALDCGEAR_SHIFT 25 /**< Shift value for RAC_DCCALDCGEAR */
+#define _RAC_IFPGACTRL_DCCALDCGEAR_MASK 0xE000000UL /**< Bit mask for RAC_DCCALDCGEAR */
+#define _RAC_IFPGACTRL_DCCALDCGEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IFPGACTRL */
+#define RAC_IFPGACTRL_DCCALDCGEAR_DEFAULT (_RAC_IFPGACTRL_DCCALDCGEAR_DEFAULT << 25) /**< Shifted mode DEFAULT for RAC_IFPGACTRL */
+
+/* Bit fields for RAC PAENCTRL */
+#define _RAC_PAENCTRL_RESETVALUE 0x00000000UL /**< Default value for RAC_PAENCTRL */
+#define _RAC_PAENCTRL_MASK 0x00070100UL /**< Mask for RAC_PAENCTRL */
+#define RAC_PAENCTRL_PARAMP (0x1UL << 8) /**< PA output level ramping */
+#define _RAC_PAENCTRL_PARAMP_SHIFT 8 /**< Shift value for RAC_PARAMP */
+#define _RAC_PAENCTRL_PARAMP_MASK 0x100UL /**< Bit mask for RAC_PARAMP */
+#define _RAC_PAENCTRL_PARAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PAENCTRL */
+#define RAC_PAENCTRL_PARAMP_DEFAULT (_RAC_PAENCTRL_PARAMP_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_PAENCTRL */
+#define RAC_PAENCTRL_INVRAMPCLK (0x1UL << 16) /**< Invert PA ramping clock */
+#define _RAC_PAENCTRL_INVRAMPCLK_SHIFT 16 /**< Shift value for RAC_INVRAMPCLK */
+#define _RAC_PAENCTRL_INVRAMPCLK_MASK 0x10000UL /**< Bit mask for RAC_INVRAMPCLK */
+#define _RAC_PAENCTRL_INVRAMPCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PAENCTRL */
+#define RAC_PAENCTRL_INVRAMPCLK_DEFAULT (_RAC_PAENCTRL_INVRAMPCLK_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_PAENCTRL */
+#define RAC_PAENCTRL_DIV2RAMPCLK (0x1UL << 17) /**< Div PA ramping clock by 2 */
+#define _RAC_PAENCTRL_DIV2RAMPCLK_SHIFT 17 /**< Shift value for RAC_DIV2RAMPCLK */
+#define _RAC_PAENCTRL_DIV2RAMPCLK_MASK 0x20000UL /**< Bit mask for RAC_DIV2RAMPCLK */
+#define _RAC_PAENCTRL_DIV2RAMPCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PAENCTRL */
+#define RAC_PAENCTRL_DIV2RAMPCLK_DEFAULT (_RAC_PAENCTRL_DIV2RAMPCLK_DEFAULT << 17) /**< Shifted mode DEFAULT for RAC_PAENCTRL */
+#define RAC_PAENCTRL_RSTDIV2RAMPCLK (0x1UL << 18) /**< Reset Div2 PA ramping clock */
+#define _RAC_PAENCTRL_RSTDIV2RAMPCLK_SHIFT 18 /**< Shift value for RAC_RSTDIV2RAMPCLK */
+#define _RAC_PAENCTRL_RSTDIV2RAMPCLK_MASK 0x40000UL /**< Bit mask for RAC_RSTDIV2RAMPCLK */
+#define _RAC_PAENCTRL_RSTDIV2RAMPCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PAENCTRL */
+#define RAC_PAENCTRL_RSTDIV2RAMPCLK_DEFAULT (_RAC_PAENCTRL_RSTDIV2RAMPCLK_DEFAULT << 18) /**< Shifted mode DEFAULT for RAC_PAENCTRL */
+
+/* Bit fields for RAC APC */
+#define _RAC_APC_RESETVALUE 0xFF000000UL /**< Default value for RAC_APC */
+#define _RAC_APC_MASK 0xFF000004UL /**< Mask for RAC_APC */
+#define RAC_APC_ENAPCSW (0x1UL << 2) /**< software control bit for apc */
+#define _RAC_APC_ENAPCSW_SHIFT 2 /**< Shift value for RAC_ENAPCSW */
+#define _RAC_APC_ENAPCSW_MASK 0x4UL /**< Bit mask for RAC_ENAPCSW */
+#define _RAC_APC_ENAPCSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_APC */
+#define _RAC_APC_ENAPCSW_DISABLE 0x00000000UL /**< Mode DISABLE for RAC_APC */
+#define _RAC_APC_ENAPCSW_ENABLE 0x00000001UL /**< Mode ENABLE for RAC_APC */
+#define RAC_APC_ENAPCSW_DEFAULT (_RAC_APC_ENAPCSW_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_APC */
+#define RAC_APC_ENAPCSW_DISABLE (_RAC_APC_ENAPCSW_DISABLE << 2) /**< Shifted mode DISABLE for RAC_APC */
+#define RAC_APC_ENAPCSW_ENABLE (_RAC_APC_ENAPCSW_ENABLE << 2) /**< Shifted mode ENABLE for RAC_APC */
+#define _RAC_APC_AMPCONTROLLIMITSW_SHIFT 24 /**< Shift value for RAC_AMPCONTROLLIMITSW */
+#define _RAC_APC_AMPCONTROLLIMITSW_MASK 0xFF000000UL /**< Bit mask for RAC_AMPCONTROLLIMITSW */
+#define _RAC_APC_AMPCONTROLLIMITSW_DEFAULT 0x000000FFUL /**< Mode DEFAULT for RAC_APC */
+#define RAC_APC_AMPCONTROLLIMITSW_DEFAULT (_RAC_APC_AMPCONTROLLIMITSW_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_APC */
+
+/* Bit fields for RAC ANTDIV */
+#define _RAC_ANTDIV_RESETVALUE 0x00000000UL /**< Default value for RAC_ANTDIV */
+#define _RAC_ANTDIV_MASK 0x00000FBDUL /**< Mask for RAC_ANTDIV */
+#define RAC_ANTDIV_INTDIVLNAMIXEN0 (0x1UL << 0) /**< INTDIVLNAMIXEN0 */
+#define _RAC_ANTDIV_INTDIVLNAMIXEN0_SHIFT 0 /**< Shift value for RAC_INTDIVLNAMIXEN0 */
+#define _RAC_ANTDIV_INTDIVLNAMIXEN0_MASK 0x1UL /**< Bit mask for RAC_INTDIVLNAMIXEN0 */
+#define _RAC_ANTDIV_INTDIVLNAMIXEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_ANTDIV */
+#define RAC_ANTDIV_INTDIVLNAMIXEN0_DEFAULT (_RAC_ANTDIV_INTDIVLNAMIXEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_ANTDIV */
+#define RAC_ANTDIV_INTDIVLNAMIXRFATTDCEN0 (0x1UL << 2) /**< INTDIVLNAMIXRFATTDCEN0 */
+#define _RAC_ANTDIV_INTDIVLNAMIXRFATTDCEN0_SHIFT 2 /**< Shift value for RAC_INTDIVLNAMIXRFATTDCEN0 */
+#define _RAC_ANTDIV_INTDIVLNAMIXRFATTDCEN0_MASK 0x4UL /**< Bit mask for RAC_INTDIVLNAMIXRFATTDCEN0 */
+#define _RAC_ANTDIV_INTDIVLNAMIXRFATTDCEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_ANTDIV */
+#define RAC_ANTDIV_INTDIVLNAMIXRFATTDCEN0_DEFAULT (_RAC_ANTDIV_INTDIVLNAMIXRFATTDCEN0_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_ANTDIV */
+#define RAC_ANTDIV_INTDIVLNAMIXRFPKDENRF0 (0x1UL << 3) /**< INTDIVLNAMIXRFPKDENRF0 */
+#define _RAC_ANTDIV_INTDIVLNAMIXRFPKDENRF0_SHIFT 3 /**< Shift value for RAC_INTDIVLNAMIXRFPKDENRF0 */
+#define _RAC_ANTDIV_INTDIVLNAMIXRFPKDENRF0_MASK 0x8UL /**< Bit mask for RAC_INTDIVLNAMIXRFPKDENRF0 */
+#define _RAC_ANTDIV_INTDIVLNAMIXRFPKDENRF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_ANTDIV */
+#define RAC_ANTDIV_INTDIVLNAMIXRFPKDENRF0_DEFAULT (_RAC_ANTDIV_INTDIVLNAMIXRFPKDENRF0_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_ANTDIV */
+#define RAC_ANTDIV_INTDIVSYLODIVRLO02G4EN (0x1UL << 4) /**< INTDIVSYLODIVRLO02G4EN */
+#define _RAC_ANTDIV_INTDIVSYLODIVRLO02G4EN_SHIFT 4 /**< Shift value for RAC_INTDIVSYLODIVRLO02G4EN */
+#define _RAC_ANTDIV_INTDIVSYLODIVRLO02G4EN_MASK 0x10UL /**< Bit mask for RAC_INTDIVSYLODIVRLO02G4EN */
+#define _RAC_ANTDIV_INTDIVSYLODIVRLO02G4EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_ANTDIV */
+#define RAC_ANTDIV_INTDIVSYLODIVRLO02G4EN_DEFAULT (_RAC_ANTDIV_INTDIVSYLODIVRLO02G4EN_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_ANTDIV */
+#define RAC_ANTDIV_INTDIVLNAMIXEN1 (0x1UL << 5) /**< INTDIVLNAMIXEN1 */
+#define _RAC_ANTDIV_INTDIVLNAMIXEN1_SHIFT 5 /**< Shift value for RAC_INTDIVLNAMIXEN1 */
+#define _RAC_ANTDIV_INTDIVLNAMIXEN1_MASK 0x20UL /**< Bit mask for RAC_INTDIVLNAMIXEN1 */
+#define _RAC_ANTDIV_INTDIVLNAMIXEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_ANTDIV */
+#define RAC_ANTDIV_INTDIVLNAMIXEN1_DEFAULT (_RAC_ANTDIV_INTDIVLNAMIXEN1_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_ANTDIV */
+#define RAC_ANTDIV_INTDIVLNAMIXRFATTDCEN1 (0x1UL << 7) /**< INTDIVLNAMIXRFATTDCEN1 */
+#define _RAC_ANTDIV_INTDIVLNAMIXRFATTDCEN1_SHIFT 7 /**< Shift value for RAC_INTDIVLNAMIXRFATTDCEN1 */
+#define _RAC_ANTDIV_INTDIVLNAMIXRFATTDCEN1_MASK 0x80UL /**< Bit mask for RAC_INTDIVLNAMIXRFATTDCEN1 */
+#define _RAC_ANTDIV_INTDIVLNAMIXRFATTDCEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_ANTDIV */
+#define RAC_ANTDIV_INTDIVLNAMIXRFATTDCEN1_DEFAULT (_RAC_ANTDIV_INTDIVLNAMIXRFATTDCEN1_DEFAULT << 7) /**< Shifted mode DEFAULT for RAC_ANTDIV */
+#define RAC_ANTDIV_INTDIVLNAMIXRFPKDENRF1 (0x1UL << 8) /**< INTDIVLNAMIXRFPKDENRF1 */
+#define _RAC_ANTDIV_INTDIVLNAMIXRFPKDENRF1_SHIFT 8 /**< Shift value for RAC_INTDIVLNAMIXRFPKDENRF1 */
+#define _RAC_ANTDIV_INTDIVLNAMIXRFPKDENRF1_MASK 0x100UL /**< Bit mask for RAC_INTDIVLNAMIXRFPKDENRF1 */
+#define _RAC_ANTDIV_INTDIVLNAMIXRFPKDENRF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_ANTDIV */
+#define RAC_ANTDIV_INTDIVLNAMIXRFPKDENRF1_DEFAULT (_RAC_ANTDIV_INTDIVLNAMIXRFPKDENRF1_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_ANTDIV */
+#define RAC_ANTDIV_INTDIVSYLODIVRLO12G4EN (0x1UL << 9) /**< INTDIVSYLODIVRLO12G4EN */
+#define _RAC_ANTDIV_INTDIVSYLODIVRLO12G4EN_SHIFT 9 /**< Shift value for RAC_INTDIVSYLODIVRLO12G4EN */
+#define _RAC_ANTDIV_INTDIVSYLODIVRLO12G4EN_MASK 0x200UL /**< Bit mask for RAC_INTDIVSYLODIVRLO12G4EN */
+#define _RAC_ANTDIV_INTDIVSYLODIVRLO12G4EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_ANTDIV */
+#define RAC_ANTDIV_INTDIVSYLODIVRLO12G4EN_DEFAULT (_RAC_ANTDIV_INTDIVSYLODIVRLO12G4EN_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_ANTDIV */
+#define _RAC_ANTDIV_ANTDIVSTATUS_SHIFT 10 /**< Shift value for RAC_ANTDIVSTATUS */
+#define _RAC_ANTDIV_ANTDIVSTATUS_MASK 0xC00UL /**< Bit mask for RAC_ANTDIVSTATUS */
+#define _RAC_ANTDIV_ANTDIVSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_ANTDIV */
+#define _RAC_ANTDIV_ANTDIVSTATUS_OFF 0x00000000UL /**< Mode OFF for RAC_ANTDIV */
+#define _RAC_ANTDIV_ANTDIVSTATUS_ANT1 0x00000001UL /**< Mode ANT1 for RAC_ANTDIV */
+#define _RAC_ANTDIV_ANTDIVSTATUS_ANT2 0x00000002UL /**< Mode ANT2 for RAC_ANTDIV */
+#define _RAC_ANTDIV_ANTDIVSTATUS_BOTH 0x00000003UL /**< Mode BOTH for RAC_ANTDIV */
+#define RAC_ANTDIV_ANTDIVSTATUS_DEFAULT (_RAC_ANTDIV_ANTDIVSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_ANTDIV */
+#define RAC_ANTDIV_ANTDIVSTATUS_OFF (_RAC_ANTDIV_ANTDIVSTATUS_OFF << 10) /**< Shifted mode OFF for RAC_ANTDIV */
+#define RAC_ANTDIV_ANTDIVSTATUS_ANT1 (_RAC_ANTDIV_ANTDIVSTATUS_ANT1 << 10) /**< Shifted mode ANT1 for RAC_ANTDIV */
+#define RAC_ANTDIV_ANTDIVSTATUS_ANT2 (_RAC_ANTDIV_ANTDIVSTATUS_ANT2 << 10) /**< Shifted mode ANT2 for RAC_ANTDIV */
+#define RAC_ANTDIV_ANTDIVSTATUS_BOTH (_RAC_ANTDIV_ANTDIVSTATUS_BOTH << 10) /**< Shifted mode BOTH for RAC_ANTDIV */
+
+/* Bit fields for RAC AUXADCTRIM */
+#define _RAC_AUXADCTRIM_RESETVALUE 0x06D55502UL /**< Default value for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_MASK 0x1FFFFFFFUL /**< Mask for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCCLKINVERT (0x1UL << 0) /**< AUXADCCLKINVERT */
+#define _RAC_AUXADCTRIM_AUXADCCLKINVERT_SHIFT 0 /**< Shift value for RAC_AUXADCCLKINVERT */
+#define _RAC_AUXADCTRIM_AUXADCCLKINVERT_MASK 0x1UL /**< Bit mask for RAC_AUXADCCLKINVERT */
+#define _RAC_AUXADCTRIM_AUXADCCLKINVERT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCCLKINVERT_Disable_Invert 0x00000000UL /**< Mode Disable_Invert for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCCLKINVERT_Enable_Invert 0x00000001UL /**< Mode Enable_Invert for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCCLKINVERT_DEFAULT (_RAC_AUXADCTRIM_AUXADCCLKINVERT_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCCLKINVERT_Disable_Invert (_RAC_AUXADCTRIM_AUXADCCLKINVERT_Disable_Invert << 0) /**< Shifted mode Disable_Invert for RAC_AUXADCTRIM*/
+#define RAC_AUXADCTRIM_AUXADCCLKINVERT_Enable_Invert (_RAC_AUXADCTRIM_AUXADCCLKINVERT_Enable_Invert << 0) /**< Shifted mode Enable_Invert for RAC_AUXADCTRIM*/
+#define _RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_SHIFT 1 /**< Shift value for RAC_AUXADCLDOVREFTRIM */
+#define _RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_MASK 0x6UL /**< Bit mask for RAC_AUXADCLDOVREFTRIM */
+#define _RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_TRIM1p27 0x00000000UL /**< Mode TRIM1p27 for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_TRIM1p3 0x00000001UL /**< Mode TRIM1p3 for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_TRIM1p35 0x00000002UL /**< Mode TRIM1p35 for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_TRIM1p4 0x00000003UL /**< Mode TRIM1p4 for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_DEFAULT (_RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_TRIM1p27 (_RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_TRIM1p27 << 1) /**< Shifted mode TRIM1p27 for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_TRIM1p3 (_RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_TRIM1p3 << 1) /**< Shifted mode TRIM1p3 for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_TRIM1p35 (_RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_TRIM1p35 << 1) /**< Shifted mode TRIM1p35 for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_TRIM1p4 (_RAC_AUXADCTRIM_AUXADCLDOVREFTRIM_TRIM1p4 << 1) /**< Shifted mode TRIM1p4 for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCOUTPUTINVERT (0x1UL << 3) /**< AUXADCOUTPUTINVERT */
+#define _RAC_AUXADCTRIM_AUXADCOUTPUTINVERT_SHIFT 3 /**< Shift value for RAC_AUXADCOUTPUTINVERT */
+#define _RAC_AUXADCTRIM_AUXADCOUTPUTINVERT_MASK 0x8UL /**< Bit mask for RAC_AUXADCOUTPUTINVERT */
+#define _RAC_AUXADCTRIM_AUXADCOUTPUTINVERT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCOUTPUTINVERT_Disabled 0x00000000UL /**< Mode Disabled for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCOUTPUTINVERT_Enabled 0x00000001UL /**< Mode Enabled for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCOUTPUTINVERT_DEFAULT (_RAC_AUXADCTRIM_AUXADCOUTPUTINVERT_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCOUTPUTINVERT_Disabled (_RAC_AUXADCTRIM_AUXADCOUTPUTINVERT_Disabled << 3) /**< Shifted mode Disabled for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCOUTPUTINVERT_Enabled (_RAC_AUXADCTRIM_AUXADCOUTPUTINVERT_Enabled << 3) /**< Shifted mode Enabled for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCRCTUNE_SHIFT 4 /**< Shift value for RAC_AUXADCRCTUNE */
+#define _RAC_AUXADCTRIM_AUXADCRCTUNE_MASK 0x1F0UL /**< Bit mask for RAC_AUXADCRCTUNE */
+#define _RAC_AUXADCTRIM_AUXADCRCTUNE_DEFAULT 0x00000010UL /**< Mode DEFAULT for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCRCTUNE_DEFAULT (_RAC_AUXADCTRIM_AUXADCRCTUNE_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_SHIFT 9 /**< Shift value for RAC_AUXADCTRIMADCINPUTRES */
+#define _RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_MASK 0x600UL /**< Bit mask for RAC_AUXADCTRIMADCINPUTRES */
+#define _RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_RES200k 0x00000000UL /**< Mode RES200k for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_RES250k 0x00000001UL /**< Mode RES250k for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_RES300k 0x00000002UL /**< Mode RES300k for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_RES350k 0x00000003UL /**< Mode RES350k for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_DEFAULT (_RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_RES200k (_RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_RES200k << 9) /**< Shifted mode RES200k for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_RES250k (_RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_RES250k << 9) /**< Shifted mode RES250k for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_RES300k (_RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_RES300k << 9) /**< Shifted mode RES300k for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_RES350k (_RAC_AUXADCTRIM_AUXADCTRIMADCINPUTRES_RES350k << 9) /**< Shifted mode RES350k for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_SHIFT 11 /**< Shift value for RAC_AUXADCTRIMCURRINPUTBUF */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_MASK 0x1800UL /**< Bit mask for RAC_AUXADCTRIMCURRINPUTBUF */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_Typ_minus_40pct 0x00000000UL /**< Mode Typ_minus_40pct for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_Typ_minus_20pct 0x00000001UL /**< Mode Typ_minus_20pct for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_Typ 0x00000002UL /**< Mode Typ for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_Typ_plus_20pct 0x00000003UL /**< Mode Typ_plus_20pct for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_DEFAULT (_RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_DEFAULT << 11) /**< Shifted mode DEFAULT for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_Typ_minus_40pct (_RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_Typ_minus_40pct << 11) /**< Shifted mode Typ_minus_40pct for RAC_AUXADCTRIM*/
+#define RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_Typ_minus_20pct (_RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_Typ_minus_20pct << 11) /**< Shifted mode Typ_minus_20pct for RAC_AUXADCTRIM*/
+#define RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_Typ (_RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_Typ << 11) /**< Shifted mode Typ for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_Typ_plus_20pct (_RAC_AUXADCTRIM_AUXADCTRIMCURRINPUTBUF_Typ_plus_20pct << 11) /**< Shifted mode Typ_plus_20pct for RAC_AUXADCTRIM*/
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_SHIFT 13 /**< Shift value for RAC_AUXADCTRIMCURROPA1 */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_MASK 0x6000UL /**< Bit mask for RAC_AUXADCTRIMCURROPA1 */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_Typ_minus_40pct 0x00000000UL /**< Mode Typ_minus_40pct for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_Typ_minus_20pct 0x00000001UL /**< Mode Typ_minus_20pct for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_Typ 0x00000002UL /**< Mode Typ for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_Typ_plus_20pct 0x00000003UL /**< Mode Typ_plus_20pct for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_DEFAULT (_RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_DEFAULT << 13) /**< Shifted mode DEFAULT for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_Typ_minus_40pct (_RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_Typ_minus_40pct << 13) /**< Shifted mode Typ_minus_40pct for RAC_AUXADCTRIM*/
+#define RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_Typ_minus_20pct (_RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_Typ_minus_20pct << 13) /**< Shifted mode Typ_minus_20pct for RAC_AUXADCTRIM*/
+#define RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_Typ (_RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_Typ << 13) /**< Shifted mode Typ for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_Typ_plus_20pct (_RAC_AUXADCTRIM_AUXADCTRIMCURROPA1_Typ_plus_20pct << 13) /**< Shifted mode Typ_plus_20pct for RAC_AUXADCTRIM*/
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_SHIFT 15 /**< Shift value for RAC_AUXADCTRIMCURROPA2 */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_MASK 0x18000UL /**< Bit mask for RAC_AUXADCTRIMCURROPA2 */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_Typ_minus_40pct 0x00000000UL /**< Mode Typ_minus_40pct for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_Typ_minus_20pct 0x00000001UL /**< Mode Typ_minus_20pct for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_Typ 0x00000002UL /**< Mode Typ for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_Typ_plus_20pct 0x00000003UL /**< Mode Typ_plus_20pct for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_DEFAULT (_RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_DEFAULT << 15) /**< Shifted mode DEFAULT for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_Typ_minus_40pct (_RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_Typ_minus_40pct << 15) /**< Shifted mode Typ_minus_40pct for RAC_AUXADCTRIM*/
+#define RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_Typ_minus_20pct (_RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_Typ_minus_20pct << 15) /**< Shifted mode Typ_minus_20pct for RAC_AUXADCTRIM*/
+#define RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_Typ (_RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_Typ << 15) /**< Shifted mode Typ for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_Typ_plus_20pct (_RAC_AUXADCTRIM_AUXADCTRIMCURROPA2_Typ_plus_20pct << 15) /**< Shifted mode Typ_plus_20pct for RAC_AUXADCTRIM*/
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_SHIFT 17 /**< Shift value for RAC_AUXADCTRIMCURRREFBUF */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_MASK 0x60000UL /**< Bit mask for RAC_AUXADCTRIMCURRREFBUF */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_Typ_minus_40pct 0x00000000UL /**< Mode Typ_minus_40pct for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_Typ_minus_20pct 0x00000001UL /**< Mode Typ_minus_20pct for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_Typ 0x00000002UL /**< Mode Typ for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_Typ_plus_20pct 0x00000003UL /**< Mode Typ_plus_20pct for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_DEFAULT (_RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_DEFAULT << 17) /**< Shifted mode DEFAULT for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_Typ_minus_40pct (_RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_Typ_minus_40pct << 17) /**< Shifted mode Typ_minus_40pct for RAC_AUXADCTRIM*/
+#define RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_Typ_minus_20pct (_RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_Typ_minus_20pct << 17) /**< Shifted mode Typ_minus_20pct for RAC_AUXADCTRIM*/
+#define RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_Typ (_RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_Typ << 17) /**< Shifted mode Typ for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_Typ_plus_20pct (_RAC_AUXADCTRIM_AUXADCTRIMCURRREFBUF_Typ_plus_20pct << 17) /**< Shifted mode Typ_plus_20pct for RAC_AUXADCTRIM*/
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_SHIFT 19 /**< Shift value for RAC_AUXADCTRIMCURRTSENSE */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_MASK 0x180000UL /**< Bit mask for RAC_AUXADCTRIMCURRTSENSE */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_Typ_minus_40pct 0x00000000UL /**< Mode Typ_minus_40pct for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_Typ_minus_20pct 0x00000001UL /**< Mode Typ_minus_20pct for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_Typ 0x00000002UL /**< Mode Typ for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_Typ_plus_20pct 0x00000003UL /**< Mode Typ_plus_20pct for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_DEFAULT (_RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_DEFAULT << 19) /**< Shifted mode DEFAULT for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_Typ_minus_40pct (_RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_Typ_minus_40pct << 19) /**< Shifted mode Typ_minus_40pct for RAC_AUXADCTRIM*/
+#define RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_Typ_minus_20pct (_RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_Typ_minus_20pct << 19) /**< Shifted mode Typ_minus_20pct for RAC_AUXADCTRIM*/
+#define RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_Typ (_RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_Typ << 19) /**< Shifted mode Typ for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_Typ_plus_20pct (_RAC_AUXADCTRIM_AUXADCTRIMCURRTSENSE_Typ_plus_20pct << 19) /**< Shifted mode Typ_plus_20pct for RAC_AUXADCTRIM*/
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_SHIFT 21 /**< Shift value for RAC_AUXADCTRIMCURRVCMBUF */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_MASK 0x600000UL /**< Bit mask for RAC_AUXADCTRIMCURRVCMBUF */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_Typ_minus_40pct 0x00000000UL /**< Mode Typ_minus_40pct for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_Typ_minus_20pct 0x00000001UL /**< Mode Typ_minus_20pct for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_Typ 0x00000002UL /**< Mode Typ for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_Typ_plus_20pct 0x00000003UL /**< Mode Typ_plus_20pct for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_DEFAULT (_RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_DEFAULT << 21) /**< Shifted mode DEFAULT for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_Typ_minus_40pct (_RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_Typ_minus_40pct << 21) /**< Shifted mode Typ_minus_40pct for RAC_AUXADCTRIM*/
+#define RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_Typ_minus_20pct (_RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_Typ_minus_20pct << 21) /**< Shifted mode Typ_minus_20pct for RAC_AUXADCTRIM*/
+#define RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_Typ (_RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_Typ << 21) /**< Shifted mode Typ for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_Typ_plus_20pct (_RAC_AUXADCTRIM_AUXADCTRIMCURRVCMBUF_Typ_plus_20pct << 21) /**< Shifted mode Typ_plus_20pct for RAC_AUXADCTRIM*/
+#define RAC_AUXADCTRIM_AUXADCTRIMLDOHIGHCURRENT (0x1UL << 23) /**< AUXADCTRIMLDOHIGHCURRENT */
+#define _RAC_AUXADCTRIM_AUXADCTRIMLDOHIGHCURRENT_SHIFT 23 /**< Shift value for RAC_AUXADCTRIMLDOHIGHCURRENT*/
+#define _RAC_AUXADCTRIM_AUXADCTRIMLDOHIGHCURRENT_MASK 0x800000UL /**< Bit mask for RAC_AUXADCTRIMLDOHIGHCURRENT */
+#define _RAC_AUXADCTRIM_AUXADCTRIMLDOHIGHCURRENT_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMLDOHIGHCURRENT_LowCurrentMode 0x00000000UL /**< Mode LowCurrentMode for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMLDOHIGHCURRENT_HighCurrentMode 0x00000001UL /**< Mode HighCurrentMode for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMLDOHIGHCURRENT_DEFAULT (_RAC_AUXADCTRIM_AUXADCTRIMLDOHIGHCURRENT_DEFAULT << 23) /**< Shifted mode DEFAULT for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMLDOHIGHCURRENT_LowCurrentMode (_RAC_AUXADCTRIM_AUXADCTRIMLDOHIGHCURRENT_LowCurrentMode << 23) /**< Shifted mode LowCurrentMode for RAC_AUXADCTRIM*/
+#define RAC_AUXADCTRIM_AUXADCTRIMLDOHIGHCURRENT_HighCurrentMode (_RAC_AUXADCTRIM_AUXADCTRIMLDOHIGHCURRENT_HighCurrentMode << 23) /**< Shifted mode HighCurrentMode for RAC_AUXADCTRIM*/
+#define _RAC_AUXADCTRIM_AUXADCTRIMREFP_SHIFT 24 /**< Shift value for RAC_AUXADCTRIMREFP */
+#define _RAC_AUXADCTRIM_AUXADCTRIMREFP_MASK 0x3000000UL /**< Bit mask for RAC_AUXADCTRIMREFP */
+#define _RAC_AUXADCTRIM_AUXADCTRIMREFP_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMREFP_REF1p05 0x00000000UL /**< Mode REF1p05 for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMREFP_REF1p16 0x00000001UL /**< Mode REF1p16 for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMREFP_REF1p2 0x00000002UL /**< Mode REF1p2 for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMREFP_REF1p25 0x00000003UL /**< Mode REF1p25 for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMREFP_DEFAULT (_RAC_AUXADCTRIM_AUXADCTRIMREFP_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMREFP_REF1p05 (_RAC_AUXADCTRIM_AUXADCTRIMREFP_REF1p05 << 24) /**< Shifted mode REF1p05 for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMREFP_REF1p16 (_RAC_AUXADCTRIM_AUXADCTRIMREFP_REF1p16 << 24) /**< Shifted mode REF1p16 for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMREFP_REF1p2 (_RAC_AUXADCTRIM_AUXADCTRIMREFP_REF1p2 << 24) /**< Shifted mode REF1p2 for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMREFP_REF1p25 (_RAC_AUXADCTRIM_AUXADCTRIMREFP_REF1p25 << 24) /**< Shifted mode REF1p25 for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_SHIFT 26 /**< Shift value for RAC_AUXADCTRIMVREFVCM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_MASK 0xC000000UL /**< Bit mask for RAC_AUXADCTRIMVREFVCM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_Trim0p6 0x00000000UL /**< Mode Trim0p6 for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_Trim0p65 0x00000001UL /**< Mode Trim0p65 for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_Trim0p7 0x00000002UL /**< Mode Trim0p7 for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_Trim0p75 0x00000003UL /**< Mode Trim0p75 for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_DEFAULT (_RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_DEFAULT << 26) /**< Shifted mode DEFAULT for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_Trim0p6 (_RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_Trim0p6 << 26) /**< Shifted mode Trim0p6 for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_Trim0p65 (_RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_Trim0p65 << 26) /**< Shifted mode Trim0p65 for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_Trim0p7 (_RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_Trim0p7 << 26) /**< Shifted mode Trim0p7 for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_Trim0p75 (_RAC_AUXADCTRIM_AUXADCTRIMVREFVCM_Trim0p75 << 26) /**< Shifted mode Trim0p75 for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTSENSETRIMVBE2 (0x1UL << 28) /**< AUXADCTSENSETRIMVBE2 */
+#define _RAC_AUXADCTRIM_AUXADCTSENSETRIMVBE2_SHIFT 28 /**< Shift value for RAC_AUXADCTSENSETRIMVBE2 */
+#define _RAC_AUXADCTRIM_AUXADCTSENSETRIMVBE2_MASK 0x10000000UL /**< Bit mask for RAC_AUXADCTSENSETRIMVBE2 */
+#define _RAC_AUXADCTRIM_AUXADCTSENSETRIMVBE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTSENSETRIMVBE2_VBE_16uA 0x00000000UL /**< Mode VBE_16uA for RAC_AUXADCTRIM */
+#define _RAC_AUXADCTRIM_AUXADCTSENSETRIMVBE2_VBE_32uA 0x00000001UL /**< Mode VBE_32uA for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTSENSETRIMVBE2_DEFAULT (_RAC_AUXADCTRIM_AUXADCTSENSETRIMVBE2_DEFAULT << 28) /**< Shifted mode DEFAULT for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTSENSETRIMVBE2_VBE_16uA (_RAC_AUXADCTRIM_AUXADCTSENSETRIMVBE2_VBE_16uA << 28) /**< Shifted mode VBE_16uA for RAC_AUXADCTRIM */
+#define RAC_AUXADCTRIM_AUXADCTSENSETRIMVBE2_VBE_32uA (_RAC_AUXADCTRIM_AUXADCTSENSETRIMVBE2_VBE_32uA << 28) /**< Shifted mode VBE_32uA for RAC_AUXADCTRIM */
+
+/* Bit fields for RAC AUXADCEN */
+#define _RAC_AUXADCEN_RESETVALUE 0x00000000UL /**< Default value for RAC_AUXADCEN */
+#define _RAC_AUXADCEN_MASK 0x000003FFUL /**< Mask for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENAUXADC (0x1UL << 0) /**< AUXADCENAUXADC */
+#define _RAC_AUXADCEN_AUXADCENAUXADC_SHIFT 0 /**< Shift value for RAC_AUXADCENAUXADC */
+#define _RAC_AUXADCEN_AUXADCENAUXADC_MASK 0x1UL /**< Bit mask for RAC_AUXADCENAUXADC */
+#define _RAC_AUXADCEN_AUXADCENAUXADC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCEN */
+#define _RAC_AUXADCEN_AUXADCENAUXADC_Disabled 0x00000000UL /**< Mode Disabled for RAC_AUXADCEN */
+#define _RAC_AUXADCEN_AUXADCENAUXADC_Enabled 0x00000001UL /**< Mode Enabled for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENAUXADC_DEFAULT (_RAC_AUXADCEN_AUXADCENAUXADC_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENAUXADC_Disabled (_RAC_AUXADCEN_AUXADCENAUXADC_Disabled << 0) /**< Shifted mode Disabled for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENAUXADC_Enabled (_RAC_AUXADCEN_AUXADCENAUXADC_Enabled << 0) /**< Shifted mode Enabled for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENINPUTBUFFER (0x1UL << 1) /**< AUXADCENINPUTBUFFER */
+#define _RAC_AUXADCEN_AUXADCENINPUTBUFFER_SHIFT 1 /**< Shift value for RAC_AUXADCENINPUTBUFFER */
+#define _RAC_AUXADCEN_AUXADCENINPUTBUFFER_MASK 0x2UL /**< Bit mask for RAC_AUXADCENINPUTBUFFER */
+#define _RAC_AUXADCEN_AUXADCENINPUTBUFFER_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCEN */
+#define _RAC_AUXADCEN_AUXADCENINPUTBUFFER_Disabled 0x00000000UL /**< Mode Disabled for RAC_AUXADCEN */
+#define _RAC_AUXADCEN_AUXADCENINPUTBUFFER_Enabled 0x00000001UL /**< Mode Enabled for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENINPUTBUFFER_DEFAULT (_RAC_AUXADCEN_AUXADCENINPUTBUFFER_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENINPUTBUFFER_Disabled (_RAC_AUXADCEN_AUXADCENINPUTBUFFER_Disabled << 1) /**< Shifted mode Disabled for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENINPUTBUFFER_Enabled (_RAC_AUXADCEN_AUXADCENINPUTBUFFER_Enabled << 1) /**< Shifted mode Enabled for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENLDO (0x1UL << 2) /**< AUXADCENLDO */
+#define _RAC_AUXADCEN_AUXADCENLDO_SHIFT 2 /**< Shift value for RAC_AUXADCENLDO */
+#define _RAC_AUXADCEN_AUXADCENLDO_MASK 0x4UL /**< Bit mask for RAC_AUXADCENLDO */
+#define _RAC_AUXADCEN_AUXADCENLDO_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCEN */
+#define _RAC_AUXADCEN_AUXADCENLDO_Disabled 0x00000000UL /**< Mode Disabled for RAC_AUXADCEN */
+#define _RAC_AUXADCEN_AUXADCENLDO_Enabled 0x00000001UL /**< Mode Enabled for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENLDO_DEFAULT (_RAC_AUXADCEN_AUXADCENLDO_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENLDO_Disabled (_RAC_AUXADCEN_AUXADCENLDO_Disabled << 2) /**< Shifted mode Disabled for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENLDO_Enabled (_RAC_AUXADCEN_AUXADCENLDO_Enabled << 2) /**< Shifted mode Enabled for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENOUTPUTDRV (0x1UL << 3) /**< AUXADCENOUTPUTDRV */
+#define _RAC_AUXADCEN_AUXADCENOUTPUTDRV_SHIFT 3 /**< Shift value for RAC_AUXADCENOUTPUTDRV */
+#define _RAC_AUXADCEN_AUXADCENOUTPUTDRV_MASK 0x8UL /**< Bit mask for RAC_AUXADCENOUTPUTDRV */
+#define _RAC_AUXADCEN_AUXADCENOUTPUTDRV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCEN */
+#define _RAC_AUXADCEN_AUXADCENOUTPUTDRV_Disabled 0x00000000UL /**< Mode Disabled for RAC_AUXADCEN */
+#define _RAC_AUXADCEN_AUXADCENOUTPUTDRV_Enabled 0x00000001UL /**< Mode Enabled for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENOUTPUTDRV_DEFAULT (_RAC_AUXADCEN_AUXADCENOUTPUTDRV_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENOUTPUTDRV_Disabled (_RAC_AUXADCEN_AUXADCENOUTPUTDRV_Disabled << 3) /**< Shifted mode Disabled for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENOUTPUTDRV_Enabled (_RAC_AUXADCEN_AUXADCENOUTPUTDRV_Enabled << 3) /**< Shifted mode Enabled for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENPMON (0x1UL << 4) /**< AUXADCENPMON */
+#define _RAC_AUXADCEN_AUXADCENPMON_SHIFT 4 /**< Shift value for RAC_AUXADCENPMON */
+#define _RAC_AUXADCEN_AUXADCENPMON_MASK 0x10UL /**< Bit mask for RAC_AUXADCENPMON */
+#define _RAC_AUXADCEN_AUXADCENPMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCEN */
+#define _RAC_AUXADCEN_AUXADCENPMON_Disabled 0x00000000UL /**< Mode Disabled for RAC_AUXADCEN */
+#define _RAC_AUXADCEN_AUXADCENPMON_Enabled 0x00000001UL /**< Mode Enabled for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENPMON_DEFAULT (_RAC_AUXADCEN_AUXADCENPMON_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENPMON_Disabled (_RAC_AUXADCEN_AUXADCENPMON_Disabled << 4) /**< Shifted mode Disabled for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENPMON_Enabled (_RAC_AUXADCEN_AUXADCENPMON_Enabled << 4) /**< Shifted mode Enabled for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENRESONDIAGA (0x1UL << 5) /**< AUXADCENRESONDIAGA */
+#define _RAC_AUXADCEN_AUXADCENRESONDIAGA_SHIFT 5 /**< Shift value for RAC_AUXADCENRESONDIAGA */
+#define _RAC_AUXADCEN_AUXADCENRESONDIAGA_MASK 0x20UL /**< Bit mask for RAC_AUXADCENRESONDIAGA */
+#define _RAC_AUXADCEN_AUXADCENRESONDIAGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCEN */
+#define _RAC_AUXADCEN_AUXADCENRESONDIAGA_Disabled 0x00000000UL /**< Mode Disabled for RAC_AUXADCEN */
+#define _RAC_AUXADCEN_AUXADCENRESONDIAGA_Enabled 0x00000001UL /**< Mode Enabled for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENRESONDIAGA_DEFAULT (_RAC_AUXADCEN_AUXADCENRESONDIAGA_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENRESONDIAGA_Disabled (_RAC_AUXADCEN_AUXADCENRESONDIAGA_Disabled << 5) /**< Shifted mode Disabled for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENRESONDIAGA_Enabled (_RAC_AUXADCEN_AUXADCENRESONDIAGA_Enabled << 5) /**< Shifted mode Enabled for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENTSENSE (0x1UL << 6) /**< AUXADCENTSENSE */
+#define _RAC_AUXADCEN_AUXADCENTSENSE_SHIFT 6 /**< Shift value for RAC_AUXADCENTSENSE */
+#define _RAC_AUXADCEN_AUXADCENTSENSE_MASK 0x40UL /**< Bit mask for RAC_AUXADCENTSENSE */
+#define _RAC_AUXADCEN_AUXADCENTSENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCEN */
+#define _RAC_AUXADCEN_AUXADCENTSENSE_Disabled 0x00000000UL /**< Mode Disabled for RAC_AUXADCEN */
+#define _RAC_AUXADCEN_AUXADCENTSENSE_Enabled 0x00000001UL /**< Mode Enabled for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENTSENSE_DEFAULT (_RAC_AUXADCEN_AUXADCENTSENSE_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENTSENSE_Disabled (_RAC_AUXADCEN_AUXADCENTSENSE_Disabled << 6) /**< Shifted mode Disabled for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENTSENSE_Enabled (_RAC_AUXADCEN_AUXADCENTSENSE_Enabled << 6) /**< Shifted mode Enabled for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENTSENSECAL (0x1UL << 7) /**< AUXADCENTSENSECAL */
+#define _RAC_AUXADCEN_AUXADCENTSENSECAL_SHIFT 7 /**< Shift value for RAC_AUXADCENTSENSECAL */
+#define _RAC_AUXADCEN_AUXADCENTSENSECAL_MASK 0x80UL /**< Bit mask for RAC_AUXADCENTSENSECAL */
+#define _RAC_AUXADCEN_AUXADCENTSENSECAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCEN */
+#define _RAC_AUXADCEN_AUXADCENTSENSECAL_Disabled 0x00000000UL /**< Mode Disabled for RAC_AUXADCEN */
+#define _RAC_AUXADCEN_AUXADCENTSENSECAL_Enabled 0x00000001UL /**< Mode Enabled for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENTSENSECAL_DEFAULT (_RAC_AUXADCEN_AUXADCENTSENSECAL_DEFAULT << 7) /**< Shifted mode DEFAULT for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENTSENSECAL_Disabled (_RAC_AUXADCEN_AUXADCENTSENSECAL_Disabled << 7) /**< Shifted mode Disabled for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENTSENSECAL_Enabled (_RAC_AUXADCEN_AUXADCENTSENSECAL_Enabled << 7) /**< Shifted mode Enabled for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCINPUTBUFFERBYPASS (0x1UL << 8) /**< AUXADCINPUTBUFFERBYPASS */
+#define _RAC_AUXADCEN_AUXADCINPUTBUFFERBYPASS_SHIFT 8 /**< Shift value for RAC_AUXADCINPUTBUFFERBYPASS */
+#define _RAC_AUXADCEN_AUXADCINPUTBUFFERBYPASS_MASK 0x100UL /**< Bit mask for RAC_AUXADCINPUTBUFFERBYPASS */
+#define _RAC_AUXADCEN_AUXADCINPUTBUFFERBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCEN */
+#define _RAC_AUXADCEN_AUXADCINPUTBUFFERBYPASS_Not_Bypassed 0x00000000UL /**< Mode Not_Bypassed for RAC_AUXADCEN */
+#define _RAC_AUXADCEN_AUXADCINPUTBUFFERBYPASS_Bypassed 0x00000001UL /**< Mode Bypassed for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCINPUTBUFFERBYPASS_DEFAULT (_RAC_AUXADCEN_AUXADCINPUTBUFFERBYPASS_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCINPUTBUFFERBYPASS_Not_Bypassed (_RAC_AUXADCEN_AUXADCINPUTBUFFERBYPASS_Not_Bypassed << 8) /**< Shifted mode Not_Bypassed for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCINPUTBUFFERBYPASS_Bypassed (_RAC_AUXADCEN_AUXADCINPUTBUFFERBYPASS_Bypassed << 8) /**< Shifted mode Bypassed for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENMEASTHERMISTOR (0x1UL << 9) /**< AUXADCENMEASTHERMISTOR */
+#define _RAC_AUXADCEN_AUXADCENMEASTHERMISTOR_SHIFT 9 /**< Shift value for RAC_AUXADCENMEASTHERMISTOR */
+#define _RAC_AUXADCEN_AUXADCENMEASTHERMISTOR_MASK 0x200UL /**< Bit mask for RAC_AUXADCENMEASTHERMISTOR */
+#define _RAC_AUXADCEN_AUXADCENMEASTHERMISTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCEN */
+#define _RAC_AUXADCEN_AUXADCENMEASTHERMISTOR_Disabled 0x00000000UL /**< Mode Disabled for RAC_AUXADCEN */
+#define _RAC_AUXADCEN_AUXADCENMEASTHERMISTOR_Enabled 0x00000001UL /**< Mode Enabled for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENMEASTHERMISTOR_DEFAULT (_RAC_AUXADCEN_AUXADCENMEASTHERMISTOR_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENMEASTHERMISTOR_Disabled (_RAC_AUXADCEN_AUXADCENMEASTHERMISTOR_Disabled << 9) /**< Shifted mode Disabled for RAC_AUXADCEN */
+#define RAC_AUXADCEN_AUXADCENMEASTHERMISTOR_Enabled (_RAC_AUXADCEN_AUXADCENMEASTHERMISTOR_Enabled << 9) /**< Shifted mode Enabled for RAC_AUXADCEN */
+
+/* Bit fields for RAC AUXADCCTRL0 */
+#define _RAC_AUXADCCTRL0_RESETVALUE 0x00000100UL /**< Default value for RAC_AUXADCCTRL0 */
+#define _RAC_AUXADCCTRL0_MASK 0x00003FFFUL /**< Mask for RAC_AUXADCCTRL0 */
+#define _RAC_AUXADCCTRL0_CYCLES_SHIFT 0 /**< Shift value for RAC_CYCLES */
+#define _RAC_AUXADCCTRL0_CYCLES_MASK 0x3FFUL /**< Bit mask for RAC_CYCLES */
+#define _RAC_AUXADCCTRL0_CYCLES_DEFAULT 0x00000100UL /**< Mode DEFAULT for RAC_AUXADCCTRL0 */
+#define RAC_AUXADCCTRL0_CYCLES_DEFAULT (_RAC_AUXADCCTRL0_CYCLES_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_AUXADCCTRL0 */
+#define _RAC_AUXADCCTRL0_MUXSEL_SHIFT 10 /**< Shift value for RAC_MUXSEL */
+#define _RAC_AUXADCCTRL0_MUXSEL_MASK 0xC00UL /**< Bit mask for RAC_MUXSEL */
+#define _RAC_AUXADCCTRL0_MUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCCTRL0 */
+#define RAC_AUXADCCTRL0_MUXSEL_DEFAULT (_RAC_AUXADCCTRL0_MUXSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_AUXADCCTRL0 */
+#define RAC_AUXADCCTRL0_CLRCOUNTER (0x1UL << 12) /**< Clear counter */
+#define _RAC_AUXADCCTRL0_CLRCOUNTER_SHIFT 12 /**< Shift value for RAC_CLRCOUNTER */
+#define _RAC_AUXADCCTRL0_CLRCOUNTER_MASK 0x1000UL /**< Bit mask for RAC_CLRCOUNTER */
+#define _RAC_AUXADCCTRL0_CLRCOUNTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCCTRL0 */
+#define RAC_AUXADCCTRL0_CLRCOUNTER_DEFAULT (_RAC_AUXADCCTRL0_CLRCOUNTER_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_AUXADCCTRL0 */
+#define RAC_AUXADCCTRL0_CLRFILTER (0x1UL << 13) /**< Clear accumulators */
+#define _RAC_AUXADCCTRL0_CLRFILTER_SHIFT 13 /**< Shift value for RAC_CLRFILTER */
+#define _RAC_AUXADCCTRL0_CLRFILTER_MASK 0x2000UL /**< Bit mask for RAC_CLRFILTER */
+#define _RAC_AUXADCCTRL0_CLRFILTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCCTRL0 */
+#define RAC_AUXADCCTRL0_CLRFILTER_DEFAULT (_RAC_AUXADCCTRL0_CLRFILTER_DEFAULT << 13) /**< Shifted mode DEFAULT for RAC_AUXADCCTRL0 */
+
+/* Bit fields for RAC AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_RESETVALUE 0x00000000UL /**< Default value for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_MASK 0xF31F0FFFUL /**< Mask for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_SHIFT 0 /**< Shift value for RAC_AUXADCINPUTRESSEL */
+#define _RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_MASK 0xFUL /**< Bit mask for RAC_AUXADCINPUTRESSEL */
+#define _RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES640kOhm 0x00000000UL /**< Mode RES640kOhm for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES320kOhm 0x00000001UL /**< Mode RES320kOhm for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES160kOhm 0x00000002UL /**< Mode RES160kOhm for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES80kOhm 0x00000003UL /**< Mode RES80kOhm for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES40kOhm 0x00000004UL /**< Mode RES40kOhm for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES20kOhm 0x00000005UL /**< Mode RES20kOhm for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES10kOhm 0x00000006UL /**< Mode RES10kOhm for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES5kOhm 0x00000007UL /**< Mode RES5kOhm for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES2p5kOhm 0x00000008UL /**< Mode RES2p5kOhm for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES1p25kOhm 0x00000009UL /**< Mode RES1p25kOhm for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES0p6kOhm 0x0000000AUL /**< Mode RES0p6kOhm for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES_switch 0x0000000BUL /**< Mode RES_switch for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_DEFAULT (_RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES640kOhm (_RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES640kOhm << 0) /**< Shifted mode RES640kOhm for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES320kOhm (_RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES320kOhm << 0) /**< Shifted mode RES320kOhm for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES160kOhm (_RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES160kOhm << 0) /**< Shifted mode RES160kOhm for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES80kOhm (_RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES80kOhm << 0) /**< Shifted mode RES80kOhm for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES40kOhm (_RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES40kOhm << 0) /**< Shifted mode RES40kOhm for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES20kOhm (_RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES20kOhm << 0) /**< Shifted mode RES20kOhm for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES10kOhm (_RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES10kOhm << 0) /**< Shifted mode RES10kOhm for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES5kOhm (_RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES5kOhm << 0) /**< Shifted mode RES5kOhm for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES2p5kOhm (_RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES2p5kOhm << 0) /**< Shifted mode RES2p5kOhm for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES1p25kOhm (_RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES1p25kOhm << 0) /**< Shifted mode RES1p25kOhm for RAC_AUXADCCTRL1*/
+#define RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES0p6kOhm (_RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES0p6kOhm << 0) /**< Shifted mode RES0p6kOhm for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES_switch (_RAC_AUXADCCTRL1_AUXADCINPUTRESSEL_RES_switch << 0) /**< Shifted mode RES_switch for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SHIFT 4 /**< Shift value for RAC_AUXADCINPUTSELECT */
+#define _RAC_AUXADCCTRL1_AUXADCINPUTSELECT_MASK 0xF0UL /**< Bit mask for RAC_AUXADCINPUTSELECT */
+#define _RAC_AUXADCCTRL1_AUXADCINPUTSELECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL0 0x00000000UL /**< Mode SEL0 for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL1 0x00000001UL /**< Mode SEL1 for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL2 0x00000002UL /**< Mode SEL2 for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL3 0x00000003UL /**< Mode SEL3 for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL4 0x00000004UL /**< Mode SEL4 for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL5 0x00000005UL /**< Mode SEL5 for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL6 0x00000006UL /**< Mode SEL6 for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL7 0x00000007UL /**< Mode SEL7 for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL8 0x00000008UL /**< Mode SEL8 for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL9 0x00000009UL /**< Mode SEL9 for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCINPUTSELECT_DEFAULT (_RAC_AUXADCCTRL1_AUXADCINPUTSELECT_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL0 (_RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL0 << 4) /**< Shifted mode SEL0 for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL1 (_RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL1 << 4) /**< Shifted mode SEL1 for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL2 (_RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL2 << 4) /**< Shifted mode SEL2 for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL3 (_RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL3 << 4) /**< Shifted mode SEL3 for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL4 (_RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL4 << 4) /**< Shifted mode SEL4 for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL5 (_RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL5 << 4) /**< Shifted mode SEL5 for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL6 (_RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL6 << 4) /**< Shifted mode SEL6 for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL7 (_RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL7 << 4) /**< Shifted mode SEL7 for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL8 (_RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL8 << 4) /**< Shifted mode SEL8 for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL9 (_RAC_AUXADCCTRL1_AUXADCINPUTSELECT_SEL9 << 4) /**< Shifted mode SEL9 for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCPMONSELECT_SHIFT 8 /**< Shift value for RAC_AUXADCPMONSELECT */
+#define _RAC_AUXADCCTRL1_AUXADCPMONSELECT_MASK 0xF00UL /**< Bit mask for RAC_AUXADCPMONSELECT */
+#define _RAC_AUXADCCTRL1_AUXADCPMONSELECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCPMONSELECT_DEFAULT (_RAC_AUXADCCTRL1_AUXADCPMONSELECT_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCTSENSESELCURR_SHIFT 16 /**< Shift value for RAC_AUXADCTSENSESELCURR */
+#define _RAC_AUXADCCTRL1_AUXADCTSENSESELCURR_MASK 0x1F0000UL /**< Bit mask for RAC_AUXADCTSENSESELCURR */
+#define _RAC_AUXADCCTRL1_AUXADCTSENSESELCURR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCTSENSESELCURR_DEFAULT (_RAC_AUXADCCTRL1_AUXADCTSENSESELCURR_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCRESET (0x1UL << 24) /**< AUXADCRESET */
+#define _RAC_AUXADCCTRL1_AUXADCRESET_SHIFT 24 /**< Shift value for RAC_AUXADCRESET */
+#define _RAC_AUXADCCTRL1_AUXADCRESET_MASK 0x1000000UL /**< Bit mask for RAC_AUXADCRESET */
+#define _RAC_AUXADCCTRL1_AUXADCRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCRESET_Reset_Disabled 0x00000000UL /**< Mode Reset_Disabled for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCRESET_Reset_Enabled 0x00000001UL /**< Mode Reset_Enabled for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCRESET_DEFAULT (_RAC_AUXADCCTRL1_AUXADCRESET_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCRESET_Reset_Disabled (_RAC_AUXADCCTRL1_AUXADCRESET_Reset_Disabled << 24) /**< Shifted mode Reset_Disabled for RAC_AUXADCCTRL1*/
+#define RAC_AUXADCCTRL1_AUXADCRESET_Reset_Enabled (_RAC_AUXADCCTRL1_AUXADCRESET_Reset_Enabled << 24) /**< Shifted mode Reset_Enabled for RAC_AUXADCCTRL1*/
+#define RAC_AUXADCCTRL1_AUXADCTSENSESELVBE (0x1UL << 25) /**< AUXADCTSENSESELVBE */
+#define _RAC_AUXADCCTRL1_AUXADCTSENSESELVBE_SHIFT 25 /**< Shift value for RAC_AUXADCTSENSESELVBE */
+#define _RAC_AUXADCCTRL1_AUXADCTSENSESELVBE_MASK 0x2000000UL /**< Bit mask for RAC_AUXADCTSENSESELVBE */
+#define _RAC_AUXADCCTRL1_AUXADCTSENSESELVBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCTSENSESELVBE_VBE1 0x00000000UL /**< Mode VBE1 for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCTSENSESELVBE_VBE2 0x00000001UL /**< Mode VBE2 for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCTSENSESELVBE_DEFAULT (_RAC_AUXADCCTRL1_AUXADCTSENSESELVBE_DEFAULT << 25) /**< Shifted mode DEFAULT for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCTSENSESELVBE_VBE1 (_RAC_AUXADCCTRL1_AUXADCTSENSESELVBE_VBE1 << 25) /**< Shifted mode VBE1 for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCTSENSESELVBE_VBE2 (_RAC_AUXADCCTRL1_AUXADCTSENSESELVBE_VBE2 << 25) /**< Shifted mode VBE2 for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_SHIFT 28 /**< Shift value for RAC_AUXADCTHERMISTORFREQSEL */
+#define _RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_MASK 0xF0000000UL /**< Bit mask for RAC_AUXADCTHERMISTORFREQSEL */
+#define _RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV1 0x00000000UL /**< Mode DIV1 for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV2 0x00000001UL /**< Mode DIV2 for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV4 0x00000002UL /**< Mode DIV4 for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV8 0x00000003UL /**< Mode DIV8 for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV16 0x00000004UL /**< Mode DIV16 for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV32 0x00000005UL /**< Mode DIV32 for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV64 0x00000006UL /**< Mode DIV64 for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV128 0x00000007UL /**< Mode DIV128 for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV256 0x00000008UL /**< Mode DIV256 for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV512 0x00000009UL /**< Mode DIV512 for RAC_AUXADCCTRL1 */
+#define _RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV1024 0x0000000AUL /**< Mode DIV1024 for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DEFAULT (_RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV1 (_RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV1 << 28) /**< Shifted mode DIV1 for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV2 (_RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV2 << 28) /**< Shifted mode DIV2 for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV4 (_RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV4 << 28) /**< Shifted mode DIV4 for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV8 (_RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV8 << 28) /**< Shifted mode DIV8 for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV16 (_RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV16 << 28) /**< Shifted mode DIV16 for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV32 (_RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV32 << 28) /**< Shifted mode DIV32 for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV64 (_RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV64 << 28) /**< Shifted mode DIV64 for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV128 (_RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV128 << 28) /**< Shifted mode DIV128 for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV256 (_RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV256 << 28) /**< Shifted mode DIV256 for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV512 (_RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV512 << 28) /**< Shifted mode DIV512 for RAC_AUXADCCTRL1 */
+#define RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV1024 (_RAC_AUXADCCTRL1_AUXADCTHERMISTORFREQSEL_DIV1024 << 28) /**< Shifted mode DIV1024 for RAC_AUXADCCTRL1 */
+
+/* Bit fields for RAC AUXADCOUT */
+#define _RAC_AUXADCOUT_RESETVALUE 0x00000000UL /**< Default value for RAC_AUXADCOUT */
+#define _RAC_AUXADCOUT_MASK 0x0FFFFFFFUL /**< Mask for RAC_AUXADCOUT */
+#define _RAC_AUXADCOUT_AUXADCOUT_SHIFT 0 /**< Shift value for RAC_AUXADCOUT */
+#define _RAC_AUXADCOUT_AUXADCOUT_MASK 0xFFFFFFFUL /**< Bit mask for RAC_AUXADCOUT */
+#define _RAC_AUXADCOUT_AUXADCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AUXADCOUT */
+#define RAC_AUXADCOUT_AUXADCOUT_DEFAULT (_RAC_AUXADCOUT_AUXADCOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_AUXADCOUT */
+
+/* Bit fields for RAC CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_RESETVALUE 0xAA400005UL /**< Default value for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_MASK 0xFFDFFFFFUL /**< Mask for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTBWCAL_SHIFT 0 /**< Shift value for RAC_CLKMULTBWCAL */
+#define _RAC_CLKMULTEN0_CLKMULTBWCAL_MASK 0x3UL /**< Bit mask for RAC_CLKMULTBWCAL */
+#define _RAC_CLKMULTEN0_CLKMULTBWCAL_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTBWCAL_bw_1lsb 0x00000000UL /**< Mode bw_1lsb for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTBWCAL_bw_2lsb 0x00000001UL /**< Mode bw_2lsb for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTBWCAL_bw_3lsb 0x00000002UL /**< Mode bw_3lsb for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTBWCAL_bw_4lsb 0x00000003UL /**< Mode bw_4lsb for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTBWCAL_DEFAULT (_RAC_CLKMULTEN0_CLKMULTBWCAL_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTBWCAL_bw_1lsb (_RAC_CLKMULTEN0_CLKMULTBWCAL_bw_1lsb << 0) /**< Shifted mode bw_1lsb for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTBWCAL_bw_2lsb (_RAC_CLKMULTEN0_CLKMULTBWCAL_bw_2lsb << 0) /**< Shifted mode bw_2lsb for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTBWCAL_bw_3lsb (_RAC_CLKMULTEN0_CLKMULTBWCAL_bw_3lsb << 0) /**< Shifted mode bw_3lsb for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTBWCAL_bw_4lsb (_RAC_CLKMULTEN0_CLKMULTBWCAL_bw_4lsb << 0) /**< Shifted mode bw_4lsb for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTDISICO (0x1UL << 2) /**< CLKMULTDISICO */
+#define _RAC_CLKMULTEN0_CLKMULTDISICO_SHIFT 2 /**< Shift value for RAC_CLKMULTDISICO */
+#define _RAC_CLKMULTEN0_CLKMULTDISICO_MASK 0x4UL /**< Bit mask for RAC_CLKMULTDISICO */
+#define _RAC_CLKMULTEN0_CLKMULTDISICO_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTDISICO_enable 0x00000000UL /**< Mode enable for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTDISICO_disable 0x00000001UL /**< Mode disable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTDISICO_DEFAULT (_RAC_CLKMULTEN0_CLKMULTDISICO_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTDISICO_enable (_RAC_CLKMULTEN0_CLKMULTDISICO_enable << 2) /**< Shifted mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTDISICO_disable (_RAC_CLKMULTEN0_CLKMULTDISICO_disable << 2) /**< Shifted mode disable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENBBDET (0x1UL << 3) /**< CLKMULTENBBDET */
+#define _RAC_CLKMULTEN0_CLKMULTENBBDET_SHIFT 3 /**< Shift value for RAC_CLKMULTENBBDET */
+#define _RAC_CLKMULTEN0_CLKMULTENBBDET_MASK 0x8UL /**< Bit mask for RAC_CLKMULTENBBDET */
+#define _RAC_CLKMULTEN0_CLKMULTENBBDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENBBDET_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENBBDET_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENBBDET_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENBBDET_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENBBDET_disable (_RAC_CLKMULTEN0_CLKMULTENBBDET_disable << 3) /**< Shifted mode disable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENBBDET_enable (_RAC_CLKMULTEN0_CLKMULTENBBDET_enable << 3) /**< Shifted mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENBBXLDET (0x1UL << 4) /**< CLKMULTENBBXLDET */
+#define _RAC_CLKMULTEN0_CLKMULTENBBXLDET_SHIFT 4 /**< Shift value for RAC_CLKMULTENBBXLDET */
+#define _RAC_CLKMULTEN0_CLKMULTENBBXLDET_MASK 0x10UL /**< Bit mask for RAC_CLKMULTENBBXLDET */
+#define _RAC_CLKMULTEN0_CLKMULTENBBXLDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENBBXLDET_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENBBXLDET_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENBBXLDET_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENBBXLDET_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENBBXLDET_disable (_RAC_CLKMULTEN0_CLKMULTENBBXLDET_disable << 4) /**< Shifted mode disable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENBBXLDET_enable (_RAC_CLKMULTEN0_CLKMULTENBBXLDET_enable << 4) /**< Shifted mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENBBXMDET (0x1UL << 5) /**< CLKMULTENBBXMDET */
+#define _RAC_CLKMULTEN0_CLKMULTENBBXMDET_SHIFT 5 /**< Shift value for RAC_CLKMULTENBBXMDET */
+#define _RAC_CLKMULTEN0_CLKMULTENBBXMDET_MASK 0x20UL /**< Bit mask for RAC_CLKMULTENBBXMDET */
+#define _RAC_CLKMULTEN0_CLKMULTENBBXMDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENBBXMDET_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENBBXMDET_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENBBXMDET_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENBBXMDET_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENBBXMDET_disable (_RAC_CLKMULTEN0_CLKMULTENBBXMDET_disable << 5) /**< Shifted mode disable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENBBXMDET_enable (_RAC_CLKMULTEN0_CLKMULTENBBXMDET_enable << 5) /**< Shifted mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENCFDET (0x1UL << 6) /**< CLKMULTENCFDET */
+#define _RAC_CLKMULTEN0_CLKMULTENCFDET_SHIFT 6 /**< Shift value for RAC_CLKMULTENCFDET */
+#define _RAC_CLKMULTEN0_CLKMULTENCFDET_MASK 0x40UL /**< Bit mask for RAC_CLKMULTENCFDET */
+#define _RAC_CLKMULTEN0_CLKMULTENCFDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENCFDET_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENCFDET_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENCFDET_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENCFDET_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENCFDET_disable (_RAC_CLKMULTEN0_CLKMULTENCFDET_disable << 6) /**< Shifted mode disable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENCFDET_enable (_RAC_CLKMULTEN0_CLKMULTENCFDET_enable << 6) /**< Shifted mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENDITHER (0x1UL << 7) /**< CLKMULTENDITHER */
+#define _RAC_CLKMULTEN0_CLKMULTENDITHER_SHIFT 7 /**< Shift value for RAC_CLKMULTENDITHER */
+#define _RAC_CLKMULTEN0_CLKMULTENDITHER_MASK 0x80UL /**< Bit mask for RAC_CLKMULTENDITHER */
+#define _RAC_CLKMULTEN0_CLKMULTENDITHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENDITHER_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENDITHER_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENDITHER_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENDITHER_DEFAULT << 7) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENDITHER_disable (_RAC_CLKMULTEN0_CLKMULTENDITHER_disable << 7) /**< Shifted mode disable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENDITHER_enable (_RAC_CLKMULTEN0_CLKMULTENDITHER_enable << 7) /**< Shifted mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENDRVADC (0x1UL << 8) /**< CLKMULTENDRVADC */
+#define _RAC_CLKMULTEN0_CLKMULTENDRVADC_SHIFT 8 /**< Shift value for RAC_CLKMULTENDRVADC */
+#define _RAC_CLKMULTEN0_CLKMULTENDRVADC_MASK 0x100UL /**< Bit mask for RAC_CLKMULTENDRVADC */
+#define _RAC_CLKMULTEN0_CLKMULTENDRVADC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENDRVADC_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENDRVADC_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENDRVADC_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENDRVADC_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENDRVADC_disable (_RAC_CLKMULTEN0_CLKMULTENDRVADC_disable << 8) /**< Shifted mode disable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENDRVADC_enable (_RAC_CLKMULTEN0_CLKMULTENDRVADC_enable << 8) /**< Shifted mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENDRVN (0x1UL << 9) /**< CLKMULTENDRVN */
+#define _RAC_CLKMULTEN0_CLKMULTENDRVN_SHIFT 9 /**< Shift value for RAC_CLKMULTENDRVN */
+#define _RAC_CLKMULTEN0_CLKMULTENDRVN_MASK 0x200UL /**< Bit mask for RAC_CLKMULTENDRVN */
+#define _RAC_CLKMULTEN0_CLKMULTENDRVN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENDRVN_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENDRVN_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENDRVN_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENDRVN_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENDRVN_disable (_RAC_CLKMULTEN0_CLKMULTENDRVN_disable << 9) /**< Shifted mode disable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENDRVN_enable (_RAC_CLKMULTEN0_CLKMULTENDRVN_enable << 9) /**< Shifted mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENDRVP (0x1UL << 10) /**< CLKMULTENDRVP */
+#define _RAC_CLKMULTEN0_CLKMULTENDRVP_SHIFT 10 /**< Shift value for RAC_CLKMULTENDRVP */
+#define _RAC_CLKMULTEN0_CLKMULTENDRVP_MASK 0x400UL /**< Bit mask for RAC_CLKMULTENDRVP */
+#define _RAC_CLKMULTEN0_CLKMULTENDRVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENDRVP_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENDRVP_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENDRVP_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENDRVP_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENDRVP_disable (_RAC_CLKMULTEN0_CLKMULTENDRVP_disable << 10) /**< Shifted mode disable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENDRVP_enable (_RAC_CLKMULTEN0_CLKMULTENDRVP_enable << 10) /**< Shifted mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENDRVRX2P4G (0x1UL << 11) /**< CLKMULTENDRVRX2P4G */
+#define _RAC_CLKMULTEN0_CLKMULTENDRVRX2P4G_SHIFT 11 /**< Shift value for RAC_CLKMULTENDRVRX2P4G */
+#define _RAC_CLKMULTEN0_CLKMULTENDRVRX2P4G_MASK 0x800UL /**< Bit mask for RAC_CLKMULTENDRVRX2P4G */
+#define _RAC_CLKMULTEN0_CLKMULTENDRVRX2P4G_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENDRVRX2P4G_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENDRVRX2P4G_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENDRVRX2P4G_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENDRVRX2P4G_DEFAULT << 11) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENDRVRX2P4G_disable (_RAC_CLKMULTEN0_CLKMULTENDRVRX2P4G_disable << 11) /**< Shifted mode disable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENDRVRX2P4G_enable (_RAC_CLKMULTEN0_CLKMULTENDRVRX2P4G_enable << 11) /**< Shifted mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENFBDIV (0x1UL << 14) /**< CLKMULTENFBDIV */
+#define _RAC_CLKMULTEN0_CLKMULTENFBDIV_SHIFT 14 /**< Shift value for RAC_CLKMULTENFBDIV */
+#define _RAC_CLKMULTEN0_CLKMULTENFBDIV_MASK 0x4000UL /**< Bit mask for RAC_CLKMULTENFBDIV */
+#define _RAC_CLKMULTEN0_CLKMULTENFBDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENFBDIV_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENFBDIV_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENFBDIV_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENFBDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENFBDIV_disable (_RAC_CLKMULTEN0_CLKMULTENFBDIV_disable << 14) /**< Shifted mode disable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENFBDIV_enable (_RAC_CLKMULTEN0_CLKMULTENFBDIV_enable << 14) /**< Shifted mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENREFDIV (0x1UL << 15) /**< CLKMULTENREFDIV */
+#define _RAC_CLKMULTEN0_CLKMULTENREFDIV_SHIFT 15 /**< Shift value for RAC_CLKMULTENREFDIV */
+#define _RAC_CLKMULTEN0_CLKMULTENREFDIV_MASK 0x8000UL /**< Bit mask for RAC_CLKMULTENREFDIV */
+#define _RAC_CLKMULTEN0_CLKMULTENREFDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENREFDIV_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENREFDIV_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENREFDIV_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENREFDIV_DEFAULT << 15) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENREFDIV_disable (_RAC_CLKMULTEN0_CLKMULTENREFDIV_disable << 15) /**< Shifted mode disable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENREFDIV_enable (_RAC_CLKMULTEN0_CLKMULTENREFDIV_enable << 15) /**< Shifted mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENREG1 (0x1UL << 16) /**< CLKMULTENREG1 */
+#define _RAC_CLKMULTEN0_CLKMULTENREG1_SHIFT 16 /**< Shift value for RAC_CLKMULTENREG1 */
+#define _RAC_CLKMULTEN0_CLKMULTENREG1_MASK 0x10000UL /**< Bit mask for RAC_CLKMULTENREG1 */
+#define _RAC_CLKMULTEN0_CLKMULTENREG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENREG1_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENREG1_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENREG1_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENREG1_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENREG1_disable (_RAC_CLKMULTEN0_CLKMULTENREG1_disable << 16) /**< Shifted mode disable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENREG1_enable (_RAC_CLKMULTEN0_CLKMULTENREG1_enable << 16) /**< Shifted mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENREG2 (0x1UL << 17) /**< CLKMULTENREG2 */
+#define _RAC_CLKMULTEN0_CLKMULTENREG2_SHIFT 17 /**< Shift value for RAC_CLKMULTENREG2 */
+#define _RAC_CLKMULTEN0_CLKMULTENREG2_MASK 0x20000UL /**< Bit mask for RAC_CLKMULTENREG2 */
+#define _RAC_CLKMULTEN0_CLKMULTENREG2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENREG2_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENREG2_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENREG2_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENREG2_DEFAULT << 17) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENREG2_disable (_RAC_CLKMULTEN0_CLKMULTENREG2_disable << 17) /**< Shifted mode disable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENREG2_enable (_RAC_CLKMULTEN0_CLKMULTENREG2_enable << 17) /**< Shifted mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENREG3 (0x1UL << 18) /**< CLKMULTENREG3 */
+#define _RAC_CLKMULTEN0_CLKMULTENREG3_SHIFT 18 /**< Shift value for RAC_CLKMULTENREG3 */
+#define _RAC_CLKMULTEN0_CLKMULTENREG3_MASK 0x40000UL /**< Bit mask for RAC_CLKMULTENREG3 */
+#define _RAC_CLKMULTEN0_CLKMULTENREG3_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENREG3_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENREG3_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENREG3_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENREG3_DEFAULT << 18) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENREG3_disable (_RAC_CLKMULTEN0_CLKMULTENREG3_disable << 18) /**< Shifted mode disable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENREG3_enable (_RAC_CLKMULTEN0_CLKMULTENREG3_enable << 18) /**< Shifted mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENROTDET (0x1UL << 19) /**< CLKMULTENROTDET */
+#define _RAC_CLKMULTEN0_CLKMULTENROTDET_SHIFT 19 /**< Shift value for RAC_CLKMULTENROTDET */
+#define _RAC_CLKMULTEN0_CLKMULTENROTDET_MASK 0x80000UL /**< Bit mask for RAC_CLKMULTENROTDET */
+#define _RAC_CLKMULTEN0_CLKMULTENROTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENROTDET_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENROTDET_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENROTDET_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENROTDET_DEFAULT << 19) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENROTDET_disable (_RAC_CLKMULTEN0_CLKMULTENROTDET_disable << 19) /**< Shifted mode disable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENROTDET_enable (_RAC_CLKMULTEN0_CLKMULTENROTDET_enable << 19) /**< Shifted mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENBYPASS40MHZ (0x1UL << 20) /**< CLKMULTENBYPASS40MHZ */
+#define _RAC_CLKMULTEN0_CLKMULTENBYPASS40MHZ_SHIFT 20 /**< Shift value for RAC_CLKMULTENBYPASS40MHZ */
+#define _RAC_CLKMULTEN0_CLKMULTENBYPASS40MHZ_MASK 0x100000UL /**< Bit mask for RAC_CLKMULTENBYPASS40MHZ */
+#define _RAC_CLKMULTEN0_CLKMULTENBYPASS40MHZ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENBYPASS40MHZ_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTENBYPASS40MHZ_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENBYPASS40MHZ_DEFAULT (_RAC_CLKMULTEN0_CLKMULTENBYPASS40MHZ_DEFAULT << 20) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENBYPASS40MHZ_disable (_RAC_CLKMULTEN0_CLKMULTENBYPASS40MHZ_disable << 20) /**< Shifted mode disable for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTENBYPASS40MHZ_enable (_RAC_CLKMULTEN0_CLKMULTENBYPASS40MHZ_enable << 20) /**< Shifted mode enable for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTFREQCAL_SHIFT 22 /**< Shift value for RAC_CLKMULTFREQCAL */
+#define _RAC_CLKMULTEN0_CLKMULTFREQCAL_MASK 0xC00000UL /**< Bit mask for RAC_CLKMULTFREQCAL */
+#define _RAC_CLKMULTEN0_CLKMULTFREQCAL_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTFREQCAL_pedes_14uA 0x00000000UL /**< Mode pedes_14uA for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTFREQCAL_pedes_22uA 0x00000001UL /**< Mode pedes_22uA for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTFREQCAL_pedes_30uA 0x00000002UL /**< Mode pedes_30uA for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTFREQCAL_pedes_38uA 0x00000003UL /**< Mode pedes_38uA for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTFREQCAL_DEFAULT (_RAC_CLKMULTEN0_CLKMULTFREQCAL_DEFAULT << 22) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTFREQCAL_pedes_14uA (_RAC_CLKMULTEN0_CLKMULTFREQCAL_pedes_14uA << 22) /**< Shifted mode pedes_14uA for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTFREQCAL_pedes_22uA (_RAC_CLKMULTEN0_CLKMULTFREQCAL_pedes_22uA << 22) /**< Shifted mode pedes_22uA for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTFREQCAL_pedes_30uA (_RAC_CLKMULTEN0_CLKMULTFREQCAL_pedes_30uA << 22) /**< Shifted mode pedes_30uA for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTFREQCAL_pedes_38uA (_RAC_CLKMULTEN0_CLKMULTFREQCAL_pedes_38uA << 22) /**< Shifted mode pedes_38uA for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTREG2ADJI_SHIFT 24 /**< Shift value for RAC_CLKMULTREG2ADJI */
+#define _RAC_CLKMULTEN0_CLKMULTREG2ADJI_MASK 0x3000000UL /**< Bit mask for RAC_CLKMULTREG2ADJI */
+#define _RAC_CLKMULTEN0_CLKMULTREG2ADJI_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTREG2ADJI_I_80uA 0x00000000UL /**< Mode I_80uA for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTREG2ADJI_I_100uA 0x00000001UL /**< Mode I_100uA for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTREG2ADJI_I_120uA 0x00000002UL /**< Mode I_120uA for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTREG2ADJI_I_140uA 0x00000003UL /**< Mode I_140uA for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTREG2ADJI_DEFAULT (_RAC_CLKMULTEN0_CLKMULTREG2ADJI_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTREG2ADJI_I_80uA (_RAC_CLKMULTEN0_CLKMULTREG2ADJI_I_80uA << 24) /**< Shifted mode I_80uA for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTREG2ADJI_I_100uA (_RAC_CLKMULTEN0_CLKMULTREG2ADJI_I_100uA << 24) /**< Shifted mode I_100uA for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTREG2ADJI_I_120uA (_RAC_CLKMULTEN0_CLKMULTREG2ADJI_I_120uA << 24) /**< Shifted mode I_120uA for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTREG2ADJI_I_140uA (_RAC_CLKMULTEN0_CLKMULTREG2ADJI_I_140uA << 24) /**< Shifted mode I_140uA for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTREG1ADJV_SHIFT 26 /**< Shift value for RAC_CLKMULTREG1ADJV */
+#define _RAC_CLKMULTEN0_CLKMULTREG1ADJV_MASK 0xC000000UL /**< Bit mask for RAC_CLKMULTREG1ADJV */
+#define _RAC_CLKMULTEN0_CLKMULTREG1ADJV_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTREG1ADJV_v1p28 0x00000000UL /**< Mode v1p28 for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTREG1ADJV_v1p32 0x00000001UL /**< Mode v1p32 for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTREG1ADJV_v1p33 0x00000002UL /**< Mode v1p33 for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTREG1ADJV_v1p38 0x00000003UL /**< Mode v1p38 for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTREG1ADJV_DEFAULT (_RAC_CLKMULTEN0_CLKMULTREG1ADJV_DEFAULT << 26) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTREG1ADJV_v1p28 (_RAC_CLKMULTEN0_CLKMULTREG1ADJV_v1p28 << 26) /**< Shifted mode v1p28 for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTREG1ADJV_v1p32 (_RAC_CLKMULTEN0_CLKMULTREG1ADJV_v1p32 << 26) /**< Shifted mode v1p32 for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTREG1ADJV_v1p33 (_RAC_CLKMULTEN0_CLKMULTREG1ADJV_v1p33 << 26) /**< Shifted mode v1p33 for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTREG1ADJV_v1p38 (_RAC_CLKMULTEN0_CLKMULTREG1ADJV_v1p38 << 26) /**< Shifted mode v1p38 for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTREG2ADJV_SHIFT 28 /**< Shift value for RAC_CLKMULTREG2ADJV */
+#define _RAC_CLKMULTEN0_CLKMULTREG2ADJV_MASK 0x30000000UL /**< Bit mask for RAC_CLKMULTREG2ADJV */
+#define _RAC_CLKMULTEN0_CLKMULTREG2ADJV_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTREG2ADJV_v1p03 0x00000000UL /**< Mode v1p03 for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTREG2ADJV_v1p09 0x00000001UL /**< Mode v1p09 for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTREG2ADJV_v1p10 0x00000002UL /**< Mode v1p10 for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTREG2ADJV_v1p16 0x00000003UL /**< Mode v1p16 for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTREG2ADJV_DEFAULT (_RAC_CLKMULTEN0_CLKMULTREG2ADJV_DEFAULT << 28) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTREG2ADJV_v1p03 (_RAC_CLKMULTEN0_CLKMULTREG2ADJV_v1p03 << 28) /**< Shifted mode v1p03 for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTREG2ADJV_v1p09 (_RAC_CLKMULTEN0_CLKMULTREG2ADJV_v1p09 << 28) /**< Shifted mode v1p09 for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTREG2ADJV_v1p10 (_RAC_CLKMULTEN0_CLKMULTREG2ADJV_v1p10 << 28) /**< Shifted mode v1p10 for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTREG2ADJV_v1p16 (_RAC_CLKMULTEN0_CLKMULTREG2ADJV_v1p16 << 28) /**< Shifted mode v1p16 for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTREG3ADJV_SHIFT 30 /**< Shift value for RAC_CLKMULTREG3ADJV */
+#define _RAC_CLKMULTEN0_CLKMULTREG3ADJV_MASK 0xC0000000UL /**< Bit mask for RAC_CLKMULTREG3ADJV */
+#define _RAC_CLKMULTEN0_CLKMULTREG3ADJV_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTREG3ADJV_v1p03 0x00000000UL /**< Mode v1p03 for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTREG3ADJV_v1p06 0x00000001UL /**< Mode v1p06 for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTREG3ADJV_v1p07 0x00000002UL /**< Mode v1p07 for RAC_CLKMULTEN0 */
+#define _RAC_CLKMULTEN0_CLKMULTREG3ADJV_v1p09 0x00000003UL /**< Mode v1p09 for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTREG3ADJV_DEFAULT (_RAC_CLKMULTEN0_CLKMULTREG3ADJV_DEFAULT << 30) /**< Shifted mode DEFAULT for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTREG3ADJV_v1p03 (_RAC_CLKMULTEN0_CLKMULTREG3ADJV_v1p03 << 30) /**< Shifted mode v1p03 for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTREG3ADJV_v1p06 (_RAC_CLKMULTEN0_CLKMULTREG3ADJV_v1p06 << 30) /**< Shifted mode v1p06 for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTREG3ADJV_v1p07 (_RAC_CLKMULTEN0_CLKMULTREG3ADJV_v1p07 << 30) /**< Shifted mode v1p07 for RAC_CLKMULTEN0 */
+#define RAC_CLKMULTEN0_CLKMULTREG3ADJV_v1p09 (_RAC_CLKMULTEN0_CLKMULTREG3ADJV_v1p09 << 30) /**< Shifted mode v1p09 for RAC_CLKMULTEN0 */
+
+/* Bit fields for RAC CLKMULTEN1 */
+#define _RAC_CLKMULTEN1_RESETVALUE 0x00000188UL /**< Default value for RAC_CLKMULTEN1 */
+#define _RAC_CLKMULTEN1_MASK 0x0001FDEFUL /**< Mask for RAC_CLKMULTEN1 */
+#define _RAC_CLKMULTEN1_CLKMULTINNIBBLE_SHIFT 0 /**< Shift value for RAC_CLKMULTINNIBBLE */
+#define _RAC_CLKMULTEN1_CLKMULTINNIBBLE_MASK 0xFUL /**< Bit mask for RAC_CLKMULTINNIBBLE */
+#define _RAC_CLKMULTEN1_CLKMULTINNIBBLE_DEFAULT 0x00000008UL /**< Mode DEFAULT for RAC_CLKMULTEN1 */
+#define RAC_CLKMULTEN1_CLKMULTINNIBBLE_DEFAULT (_RAC_CLKMULTEN1_CLKMULTINNIBBLE_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_CLKMULTEN1 */
+#define RAC_CLKMULTEN1_CLKMULTLDFNIB (0x1UL << 5) /**< CLKMULTLDFNIB */
+#define _RAC_CLKMULTEN1_CLKMULTLDFNIB_SHIFT 5 /**< Shift value for RAC_CLKMULTLDFNIB */
+#define _RAC_CLKMULTEN1_CLKMULTLDFNIB_MASK 0x20UL /**< Bit mask for RAC_CLKMULTLDFNIB */
+#define _RAC_CLKMULTEN1_CLKMULTLDFNIB_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN1 */
+#define _RAC_CLKMULTEN1_CLKMULTLDFNIB_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN1 */
+#define _RAC_CLKMULTEN1_CLKMULTLDFNIB_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN1 */
+#define RAC_CLKMULTEN1_CLKMULTLDFNIB_DEFAULT (_RAC_CLKMULTEN1_CLKMULTLDFNIB_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_CLKMULTEN1 */
+#define RAC_CLKMULTEN1_CLKMULTLDFNIB_disable (_RAC_CLKMULTEN1_CLKMULTLDFNIB_disable << 5) /**< Shifted mode disable for RAC_CLKMULTEN1 */
+#define RAC_CLKMULTEN1_CLKMULTLDFNIB_enable (_RAC_CLKMULTEN1_CLKMULTLDFNIB_enable << 5) /**< Shifted mode enable for RAC_CLKMULTEN1 */
+#define RAC_CLKMULTEN1_CLKMULTLDMNIB (0x1UL << 6) /**< CLKMULTLDMNIB */
+#define _RAC_CLKMULTEN1_CLKMULTLDMNIB_SHIFT 6 /**< Shift value for RAC_CLKMULTLDMNIB */
+#define _RAC_CLKMULTEN1_CLKMULTLDMNIB_MASK 0x40UL /**< Bit mask for RAC_CLKMULTLDMNIB */
+#define _RAC_CLKMULTEN1_CLKMULTLDMNIB_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN1 */
+#define _RAC_CLKMULTEN1_CLKMULTLDMNIB_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN1 */
+#define _RAC_CLKMULTEN1_CLKMULTLDMNIB_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN1 */
+#define RAC_CLKMULTEN1_CLKMULTLDMNIB_DEFAULT (_RAC_CLKMULTEN1_CLKMULTLDMNIB_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_CLKMULTEN1 */
+#define RAC_CLKMULTEN1_CLKMULTLDMNIB_disable (_RAC_CLKMULTEN1_CLKMULTLDMNIB_disable << 6) /**< Shifted mode disable for RAC_CLKMULTEN1 */
+#define RAC_CLKMULTEN1_CLKMULTLDMNIB_enable (_RAC_CLKMULTEN1_CLKMULTLDMNIB_enable << 6) /**< Shifted mode enable for RAC_CLKMULTEN1 */
+#define _RAC_CLKMULTEN1_CLKMULTRDNIBBLE_SHIFT 7 /**< Shift value for RAC_CLKMULTRDNIBBLE */
+#define _RAC_CLKMULTEN1_CLKMULTRDNIBBLE_MASK 0x180UL /**< Bit mask for RAC_CLKMULTRDNIBBLE */
+#define _RAC_CLKMULTEN1_CLKMULTRDNIBBLE_DEFAULT 0x00000003UL /**< Mode DEFAULT for RAC_CLKMULTEN1 */
+#define _RAC_CLKMULTEN1_CLKMULTRDNIBBLE_quarter_nibble 0x00000000UL /**< Mode quarter_nibble for RAC_CLKMULTEN1 */
+#define _RAC_CLKMULTEN1_CLKMULTRDNIBBLE_fine_nibble 0x00000001UL /**< Mode fine_nibble for RAC_CLKMULTEN1 */
+#define _RAC_CLKMULTEN1_CLKMULTRDNIBBLE_moderate_nibble 0x00000002UL /**< Mode moderate_nibble for RAC_CLKMULTEN1 */
+#define _RAC_CLKMULTEN1_CLKMULTRDNIBBLE_coarse_nibble 0x00000003UL /**< Mode coarse_nibble for RAC_CLKMULTEN1 */
+#define RAC_CLKMULTEN1_CLKMULTRDNIBBLE_DEFAULT (_RAC_CLKMULTEN1_CLKMULTRDNIBBLE_DEFAULT << 7) /**< Shifted mode DEFAULT for RAC_CLKMULTEN1 */
+#define RAC_CLKMULTEN1_CLKMULTRDNIBBLE_quarter_nibble (_RAC_CLKMULTEN1_CLKMULTRDNIBBLE_quarter_nibble << 7) /**< Shifted mode quarter_nibble for RAC_CLKMULTEN1*/
+#define RAC_CLKMULTEN1_CLKMULTRDNIBBLE_fine_nibble (_RAC_CLKMULTEN1_CLKMULTRDNIBBLE_fine_nibble << 7) /**< Shifted mode fine_nibble for RAC_CLKMULTEN1 */
+#define RAC_CLKMULTEN1_CLKMULTRDNIBBLE_moderate_nibble (_RAC_CLKMULTEN1_CLKMULTRDNIBBLE_moderate_nibble << 7) /**< Shifted mode moderate_nibble for RAC_CLKMULTEN1*/
+#define RAC_CLKMULTEN1_CLKMULTRDNIBBLE_coarse_nibble (_RAC_CLKMULTEN1_CLKMULTRDNIBBLE_coarse_nibble << 7) /**< Shifted mode coarse_nibble for RAC_CLKMULTEN1*/
+#define RAC_CLKMULTEN1_CLKMULTLDCNIB (0x1UL << 10) /**< CLKMULTLDCNIB */
+#define _RAC_CLKMULTEN1_CLKMULTLDCNIB_SHIFT 10 /**< Shift value for RAC_CLKMULTLDCNIB */
+#define _RAC_CLKMULTEN1_CLKMULTLDCNIB_MASK 0x400UL /**< Bit mask for RAC_CLKMULTLDCNIB */
+#define _RAC_CLKMULTEN1_CLKMULTLDCNIB_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN1 */
+#define _RAC_CLKMULTEN1_CLKMULTLDCNIB_disable 0x00000000UL /**< Mode disable for RAC_CLKMULTEN1 */
+#define _RAC_CLKMULTEN1_CLKMULTLDCNIB_enable 0x00000001UL /**< Mode enable for RAC_CLKMULTEN1 */
+#define RAC_CLKMULTEN1_CLKMULTLDCNIB_DEFAULT (_RAC_CLKMULTEN1_CLKMULTLDCNIB_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_CLKMULTEN1 */
+#define RAC_CLKMULTEN1_CLKMULTLDCNIB_disable (_RAC_CLKMULTEN1_CLKMULTLDCNIB_disable << 10) /**< Shifted mode disable for RAC_CLKMULTEN1 */
+#define RAC_CLKMULTEN1_CLKMULTLDCNIB_enable (_RAC_CLKMULTEN1_CLKMULTLDCNIB_enable << 10) /**< Shifted mode enable for RAC_CLKMULTEN1 */
+#define _RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_SHIFT 11 /**< Shift value for RAC_CLKMULTDRVAMPSEL */
+#define _RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_MASK 0x1F800UL /**< Bit mask for RAC_CLKMULTDRVAMPSEL */
+#define _RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTEN1 */
+#define _RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_off 0x00000000UL /**< Mode off for RAC_CLKMULTEN1 */
+#define _RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x1 0x00000001UL /**< Mode slide_x1 for RAC_CLKMULTEN1 */
+#define _RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x2 0x00000003UL /**< Mode slide_x2 for RAC_CLKMULTEN1 */
+#define _RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x3 0x00000007UL /**< Mode slide_x3 for RAC_CLKMULTEN1 */
+#define _RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x4 0x0000000FUL /**< Mode slide_x4 for RAC_CLKMULTEN1 */
+#define _RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x5 0x0000001FUL /**< Mode slide_x5 for RAC_CLKMULTEN1 */
+#define _RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x6 0x0000003FUL /**< Mode slide_x6 for RAC_CLKMULTEN1 */
+#define RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_DEFAULT (_RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for RAC_CLKMULTEN1 */
+#define RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_off (_RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_off << 11) /**< Shifted mode off for RAC_CLKMULTEN1 */
+#define RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x1 (_RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x1 << 11) /**< Shifted mode slide_x1 for RAC_CLKMULTEN1 */
+#define RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x2 (_RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x2 << 11) /**< Shifted mode slide_x2 for RAC_CLKMULTEN1 */
+#define RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x3 (_RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x3 << 11) /**< Shifted mode slide_x3 for RAC_CLKMULTEN1 */
+#define RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x4 (_RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x4 << 11) /**< Shifted mode slide_x4 for RAC_CLKMULTEN1 */
+#define RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x5 (_RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x5 << 11) /**< Shifted mode slide_x5 for RAC_CLKMULTEN1 */
+#define RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x6 (_RAC_CLKMULTEN1_CLKMULTDRVAMPSEL_slide_x6 << 11) /**< Shifted mode slide_x6 for RAC_CLKMULTEN1 */
+
+/* Bit fields for RAC CLKMULTCTRL */
+#define _RAC_CLKMULTCTRL_RESETVALUE 0x000000C0UL /**< Default value for RAC_CLKMULTCTRL */
+#define _RAC_CLKMULTCTRL_MASK 0x00007FFFUL /**< Mask for RAC_CLKMULTCTRL */
+#define _RAC_CLKMULTCTRL_CLKMULTDIVN_SHIFT 0 /**< Shift value for RAC_CLKMULTDIVN */
+#define _RAC_CLKMULTCTRL_CLKMULTDIVN_MASK 0x7FUL /**< Bit mask for RAC_CLKMULTDIVN */
+#define _RAC_CLKMULTCTRL_CLKMULTDIVN_DEFAULT 0x00000040UL /**< Mode DEFAULT for RAC_CLKMULTCTRL */
+#define RAC_CLKMULTCTRL_CLKMULTDIVN_DEFAULT (_RAC_CLKMULTCTRL_CLKMULTDIVN_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_CLKMULTCTRL */
+#define _RAC_CLKMULTCTRL_CLKMULTDIVR_SHIFT 7 /**< Shift value for RAC_CLKMULTDIVR */
+#define _RAC_CLKMULTCTRL_CLKMULTDIVR_MASK 0x380UL /**< Bit mask for RAC_CLKMULTDIVR */
+#define _RAC_CLKMULTCTRL_CLKMULTDIVR_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_CLKMULTCTRL */
+#define RAC_CLKMULTCTRL_CLKMULTDIVR_DEFAULT (_RAC_CLKMULTCTRL_CLKMULTDIVR_DEFAULT << 7) /**< Shifted mode DEFAULT for RAC_CLKMULTCTRL */
+#define _RAC_CLKMULTCTRL_CLKMULTDIVX_SHIFT 10 /**< Shift value for RAC_CLKMULTDIVX */
+#define _RAC_CLKMULTCTRL_CLKMULTDIVX_MASK 0x1C00UL /**< Bit mask for RAC_CLKMULTDIVX */
+#define _RAC_CLKMULTCTRL_CLKMULTDIVX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTCTRL */
+#define _RAC_CLKMULTCTRL_CLKMULTDIVX_div_1 0x00000000UL /**< Mode div_1 for RAC_CLKMULTCTRL */
+#define _RAC_CLKMULTCTRL_CLKMULTDIVX_div_2 0x00000001UL /**< Mode div_2 for RAC_CLKMULTCTRL */
+#define _RAC_CLKMULTCTRL_CLKMULTDIVX_div_4 0x00000002UL /**< Mode div_4 for RAC_CLKMULTCTRL */
+#define _RAC_CLKMULTCTRL_CLKMULTDIVX_div_6 0x00000003UL /**< Mode div_6 for RAC_CLKMULTCTRL */
+#define _RAC_CLKMULTCTRL_CLKMULTDIVX_div_8 0x00000004UL /**< Mode div_8 for RAC_CLKMULTCTRL */
+#define _RAC_CLKMULTCTRL_CLKMULTDIVX_div10 0x00000005UL /**< Mode div10 for RAC_CLKMULTCTRL */
+#define _RAC_CLKMULTCTRL_CLKMULTDIVX_div12 0x00000006UL /**< Mode div12 for RAC_CLKMULTCTRL */
+#define _RAC_CLKMULTCTRL_CLKMULTDIVX_div14 0x00000007UL /**< Mode div14 for RAC_CLKMULTCTRL */
+#define RAC_CLKMULTCTRL_CLKMULTDIVX_DEFAULT (_RAC_CLKMULTCTRL_CLKMULTDIVX_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_CLKMULTCTRL */
+#define RAC_CLKMULTCTRL_CLKMULTDIVX_div_1 (_RAC_CLKMULTCTRL_CLKMULTDIVX_div_1 << 10) /**< Shifted mode div_1 for RAC_CLKMULTCTRL */
+#define RAC_CLKMULTCTRL_CLKMULTDIVX_div_2 (_RAC_CLKMULTCTRL_CLKMULTDIVX_div_2 << 10) /**< Shifted mode div_2 for RAC_CLKMULTCTRL */
+#define RAC_CLKMULTCTRL_CLKMULTDIVX_div_4 (_RAC_CLKMULTCTRL_CLKMULTDIVX_div_4 << 10) /**< Shifted mode div_4 for RAC_CLKMULTCTRL */
+#define RAC_CLKMULTCTRL_CLKMULTDIVX_div_6 (_RAC_CLKMULTCTRL_CLKMULTDIVX_div_6 << 10) /**< Shifted mode div_6 for RAC_CLKMULTCTRL */
+#define RAC_CLKMULTCTRL_CLKMULTDIVX_div_8 (_RAC_CLKMULTCTRL_CLKMULTDIVX_div_8 << 10) /**< Shifted mode div_8 for RAC_CLKMULTCTRL */
+#define RAC_CLKMULTCTRL_CLKMULTDIVX_div10 (_RAC_CLKMULTCTRL_CLKMULTDIVX_div10 << 10) /**< Shifted mode div10 for RAC_CLKMULTCTRL */
+#define RAC_CLKMULTCTRL_CLKMULTDIVX_div12 (_RAC_CLKMULTCTRL_CLKMULTDIVX_div12 << 10) /**< Shifted mode div12 for RAC_CLKMULTCTRL */
+#define RAC_CLKMULTCTRL_CLKMULTDIVX_div14 (_RAC_CLKMULTCTRL_CLKMULTDIVX_div14 << 10) /**< Shifted mode div14 for RAC_CLKMULTCTRL */
+#define RAC_CLKMULTCTRL_CLKMULTENRESYNC (0x1UL << 13) /**< CLKMULTENRESYNC */
+#define _RAC_CLKMULTCTRL_CLKMULTENRESYNC_SHIFT 13 /**< Shift value for RAC_CLKMULTENRESYNC */
+#define _RAC_CLKMULTCTRL_CLKMULTENRESYNC_MASK 0x2000UL /**< Bit mask for RAC_CLKMULTENRESYNC */
+#define _RAC_CLKMULTCTRL_CLKMULTENRESYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTCTRL */
+#define _RAC_CLKMULTCTRL_CLKMULTENRESYNC_disable_sync 0x00000000UL /**< Mode disable_sync for RAC_CLKMULTCTRL */
+#define _RAC_CLKMULTCTRL_CLKMULTENRESYNC_enable_sync 0x00000001UL /**< Mode enable_sync for RAC_CLKMULTCTRL */
+#define RAC_CLKMULTCTRL_CLKMULTENRESYNC_DEFAULT (_RAC_CLKMULTCTRL_CLKMULTENRESYNC_DEFAULT << 13) /**< Shifted mode DEFAULT for RAC_CLKMULTCTRL */
+#define RAC_CLKMULTCTRL_CLKMULTENRESYNC_disable_sync (_RAC_CLKMULTCTRL_CLKMULTENRESYNC_disable_sync << 13) /**< Shifted mode disable_sync for RAC_CLKMULTCTRL*/
+#define RAC_CLKMULTCTRL_CLKMULTENRESYNC_enable_sync (_RAC_CLKMULTCTRL_CLKMULTENRESYNC_enable_sync << 13) /**< Shifted mode enable_sync for RAC_CLKMULTCTRL*/
+#define RAC_CLKMULTCTRL_CLKMULTVALID (0x1UL << 14) /**< CLKMULTVALID */
+#define _RAC_CLKMULTCTRL_CLKMULTVALID_SHIFT 14 /**< Shift value for RAC_CLKMULTVALID */
+#define _RAC_CLKMULTCTRL_CLKMULTVALID_MASK 0x4000UL /**< Bit mask for RAC_CLKMULTVALID */
+#define _RAC_CLKMULTCTRL_CLKMULTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTCTRL */
+#define _RAC_CLKMULTCTRL_CLKMULTVALID_invalid 0x00000000UL /**< Mode invalid for RAC_CLKMULTCTRL */
+#define _RAC_CLKMULTCTRL_CLKMULTVALID_valid 0x00000001UL /**< Mode valid for RAC_CLKMULTCTRL */
+#define RAC_CLKMULTCTRL_CLKMULTVALID_DEFAULT (_RAC_CLKMULTCTRL_CLKMULTVALID_DEFAULT << 14) /**< Shifted mode DEFAULT for RAC_CLKMULTCTRL */
+#define RAC_CLKMULTCTRL_CLKMULTVALID_invalid (_RAC_CLKMULTCTRL_CLKMULTVALID_invalid << 14) /**< Shifted mode invalid for RAC_CLKMULTCTRL */
+#define RAC_CLKMULTCTRL_CLKMULTVALID_valid (_RAC_CLKMULTCTRL_CLKMULTVALID_valid << 14) /**< Shifted mode valid for RAC_CLKMULTCTRL */
+
+/* Bit fields for RAC CLKMULTSTATUS */
+#define _RAC_CLKMULTSTATUS_RESETVALUE 0x00000000UL /**< Default value for RAC_CLKMULTSTATUS */
+#define _RAC_CLKMULTSTATUS_MASK 0x0000001FUL /**< Mask for RAC_CLKMULTSTATUS */
+#define _RAC_CLKMULTSTATUS_CLKMULTOUTNIBBLE_SHIFT 0 /**< Shift value for RAC_CLKMULTOUTNIBBLE */
+#define _RAC_CLKMULTSTATUS_CLKMULTOUTNIBBLE_MASK 0xFUL /**< Bit mask for RAC_CLKMULTOUTNIBBLE */
+#define _RAC_CLKMULTSTATUS_CLKMULTOUTNIBBLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTSTATUS */
+#define RAC_CLKMULTSTATUS_CLKMULTOUTNIBBLE_DEFAULT (_RAC_CLKMULTSTATUS_CLKMULTOUTNIBBLE_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_CLKMULTSTATUS */
+#define RAC_CLKMULTSTATUS_CLKMULTACKVALID (0x1UL << 4) /**< CLKMULTACKVALID */
+#define _RAC_CLKMULTSTATUS_CLKMULTACKVALID_SHIFT 4 /**< Shift value for RAC_CLKMULTACKVALID */
+#define _RAC_CLKMULTSTATUS_CLKMULTACKVALID_MASK 0x10UL /**< Bit mask for RAC_CLKMULTACKVALID */
+#define _RAC_CLKMULTSTATUS_CLKMULTACKVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_CLKMULTSTATUS */
+#define _RAC_CLKMULTSTATUS_CLKMULTACKVALID_invalid 0x00000000UL /**< Mode invalid for RAC_CLKMULTSTATUS */
+#define _RAC_CLKMULTSTATUS_CLKMULTACKVALID_valid 0x00000001UL /**< Mode valid for RAC_CLKMULTSTATUS */
+#define RAC_CLKMULTSTATUS_CLKMULTACKVALID_DEFAULT (_RAC_CLKMULTSTATUS_CLKMULTACKVALID_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_CLKMULTSTATUS */
+#define RAC_CLKMULTSTATUS_CLKMULTACKVALID_invalid (_RAC_CLKMULTSTATUS_CLKMULTACKVALID_invalid << 4) /**< Shifted mode invalid for RAC_CLKMULTSTATUS */
+#define RAC_CLKMULTSTATUS_CLKMULTACKVALID_valid (_RAC_CLKMULTSTATUS_CLKMULTACKVALID_valid << 4) /**< Shifted mode valid for RAC_CLKMULTSTATUS */
+
+/* Bit fields for RAC IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_RESETVALUE 0x11512C6CUL /**< Default value for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_MASK 0x7FFFFFFDUL /**< Mask for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCCLKSEL (0x1UL << 0) /**< IFADCCLKSEL */
+#define _RAC_IFADCTRIM0_IFADCCLKSEL_SHIFT 0 /**< Shift value for RAC_IFADCCLKSEL */
+#define _RAC_IFADCTRIM0_IFADCCLKSEL_MASK 0x1UL /**< Bit mask for RAC_IFADCCLKSEL */
+#define _RAC_IFADCTRIM0_IFADCCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCCLKSEL_clk_2p4g 0x00000000UL /**< Mode clk_2p4g for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCCLKSEL_clk_subg 0x00000001UL /**< Mode clk_subg for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCCLKSEL_DEFAULT (_RAC_IFADCTRIM0_IFADCCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCCLKSEL_clk_2p4g (_RAC_IFADCTRIM0_IFADCCLKSEL_clk_2p4g << 0) /**< Shifted mode clk_2p4g for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCCLKSEL_clk_subg (_RAC_IFADCTRIM0_IFADCCLKSEL_clk_subg << 0) /**< Shifted mode clk_subg for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_SHIFT 2 /**< Shift value for RAC_IFADCLDOSERIESAMPLVL */
+#define _RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_MASK 0x1CUL /**< Bit mask for RAC_IFADCLDOSERIESAMPLVL */
+#define _RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p225 0x00000000UL /**< Mode v1p225 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p250 0x00000001UL /**< Mode v1p250 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p275 0x00000002UL /**< Mode v1p275 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p300 0x00000003UL /**< Mode v1p300 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p325 0x00000004UL /**< Mode v1p325 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p350 0x00000005UL /**< Mode v1p350 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p375 0x00000006UL /**< Mode v1p375 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p400 0x00000007UL /**< Mode v1p400 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_DEFAULT (_RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p225 (_RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p225 << 2) /**< Shifted mode v1p225 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p250 (_RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p250 << 2) /**< Shifted mode v1p250 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p275 (_RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p275 << 2) /**< Shifted mode v1p275 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p300 (_RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p300 << 2) /**< Shifted mode v1p300 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p325 (_RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p325 << 2) /**< Shifted mode v1p325 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p350 (_RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p350 << 2) /**< Shifted mode v1p350 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p375 (_RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p375 << 2) /**< Shifted mode v1p375 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p400 (_RAC_IFADCTRIM0_IFADCLDOSERIESAMPLVL_v1p400 << 2) /**< Shifted mode v1p400 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_SHIFT 5 /**< Shift value for RAC_IFADCLDOSHUNTAMPLVL1 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_MASK 0xE0UL /**< Bit mask for RAC_IFADCLDOSHUNTAMPLVL1 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_DEFAULT 0x00000003UL /**< Mode DEFAULT for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p125 0x00000000UL /**< Mode v1p125 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p150 0x00000001UL /**< Mode v1p150 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p175 0x00000002UL /**< Mode v1p175 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p200 0x00000003UL /**< Mode v1p200 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p225 0x00000004UL /**< Mode v1p225 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p250 0x00000005UL /**< Mode v1p250 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p275 0x00000006UL /**< Mode v1p275 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p300 0x00000007UL /**< Mode v1p300 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_DEFAULT (_RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p125 (_RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p125 << 5) /**< Shifted mode v1p125 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p150 (_RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p150 << 5) /**< Shifted mode v1p150 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p175 (_RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p175 << 5) /**< Shifted mode v1p175 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p200 (_RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p200 << 5) /**< Shifted mode v1p200 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p225 (_RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p225 << 5) /**< Shifted mode v1p225 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p250 (_RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p250 << 5) /**< Shifted mode v1p250 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p275 (_RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p275 << 5) /**< Shifted mode v1p275 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p300 (_RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL1_v1p300 << 5) /**< Shifted mode v1p300 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL2 (0x1UL << 8) /**< IFADCLDOSHUNTAMPLVL2 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL2_SHIFT 8 /**< Shift value for RAC_IFADCLDOSHUNTAMPLVL2 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL2_MASK 0x100UL /**< Bit mask for RAC_IFADCLDOSHUNTAMPLVL2 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL2_disable 0x00000000UL /**< Mode disable for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL2_enable 0x00000001UL /**< Mode enable for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL2_DEFAULT (_RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL2_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL2_disable (_RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL2_disable << 8) /**< Shifted mode disable for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL2_enable (_RAC_IFADCTRIM0_IFADCLDOSHUNTAMPLVL2_enable << 8) /**< Shifted mode enable for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_SHIFT 9 /**< Shift value for RAC_IFADCLDOSHUNTCURLVL1 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_MASK 0xE00UL /**< Bit mask for RAC_IFADCLDOSHUNTCURLVL1 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_DEFAULT 0x00000006UL /**< Mode DEFAULT for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i55u 0x00000000UL /**< Mode i55u for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i65u 0x00000001UL /**< Mode i65u for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i70u 0x00000002UL /**< Mode i70u for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i85u 0x00000003UL /**< Mode i85u for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i85u2 0x00000004UL /**< Mode i85u2 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i95u 0x00000005UL /**< Mode i95u for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i100u 0x00000006UL /**< Mode i100u for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i110u 0x00000007UL /**< Mode i110u for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_DEFAULT (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i55u (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i55u << 9) /**< Shifted mode i55u for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i65u (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i65u << 9) /**< Shifted mode i65u for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i70u (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i70u << 9) /**< Shifted mode i70u for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i85u (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i85u << 9) /**< Shifted mode i85u for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i85u2 (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i85u2 << 9) /**< Shifted mode i85u2 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i95u (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i95u << 9) /**< Shifted mode i95u for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i100u (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i100u << 9) /**< Shifted mode i100u for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i110u (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL1_i110u << 9) /**< Shifted mode i110u for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_SHIFT 12 /**< Shift value for RAC_IFADCLDOSHUNTCURLVL2 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_MASK 0x7000UL /**< Bit mask for RAC_IFADCLDOSHUNTCURLVL2 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i4u 0x00000000UL /**< Mode i4u for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i4p5u 0x00000001UL /**< Mode i4p5u for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i5u 0x00000002UL /**< Mode i5u for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i5p5u 0x00000003UL /**< Mode i5p5u for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i5u2 0x00000004UL /**< Mode i5u2 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i5p5u2 0x00000005UL /**< Mode i5p5u2 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i6u 0x00000006UL /**< Mode i6u for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i6p5u 0x00000007UL /**< Mode i6p5u for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_DEFAULT (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i4u (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i4u << 12) /**< Shifted mode i4u for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i4p5u (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i4p5u << 12) /**< Shifted mode i4p5u for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i5u (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i5u << 12) /**< Shifted mode i5u for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i5p5u (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i5p5u << 12) /**< Shifted mode i5p5u for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i5u2 (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i5u2 << 12) /**< Shifted mode i5u2 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i5p5u2 (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i5p5u2 << 12) /**< Shifted mode i5p5u2 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i6u (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i6u << 12) /**< Shifted mode i6u for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i6p5u (_RAC_IFADCTRIM0_IFADCLDOSHUNTCURLVL2_i6p5u << 12) /**< Shifted mode i6p5u for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCOTACURRENT_SHIFT 15 /**< Shift value for RAC_IFADCOTACURRENT */
+#define _RAC_IFADCTRIM0_IFADCOTACURRENT_MASK 0x38000UL /**< Bit mask for RAC_IFADCOTACURRENT */
+#define _RAC_IFADCTRIM0_IFADCOTACURRENT_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCOTACURRENT_i3u 0x00000000UL /**< Mode i3u for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCOTACURRENT_i3p5u 0x00000001UL /**< Mode i3p5u for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCOTACURRENT_i4u 0x00000002UL /**< Mode i4u for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCOTACURRENT_i4p5u 0x00000003UL /**< Mode i4p5u for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCOTACURRENT_i4u2 0x00000004UL /**< Mode i4u2 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCOTACURRENT_i4p5u2 0x00000005UL /**< Mode i4p5u2 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCOTACURRENT_i5u 0x00000006UL /**< Mode i5u for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCOTACURRENT_i5p5u 0x00000007UL /**< Mode i5p5u for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCOTACURRENT_DEFAULT (_RAC_IFADCTRIM0_IFADCOTACURRENT_DEFAULT << 15) /**< Shifted mode DEFAULT for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCOTACURRENT_i3u (_RAC_IFADCTRIM0_IFADCOTACURRENT_i3u << 15) /**< Shifted mode i3u for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCOTACURRENT_i3p5u (_RAC_IFADCTRIM0_IFADCOTACURRENT_i3p5u << 15) /**< Shifted mode i3p5u for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCOTACURRENT_i4u (_RAC_IFADCTRIM0_IFADCOTACURRENT_i4u << 15) /**< Shifted mode i4u for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCOTACURRENT_i4p5u (_RAC_IFADCTRIM0_IFADCOTACURRENT_i4p5u << 15) /**< Shifted mode i4p5u for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCOTACURRENT_i4u2 (_RAC_IFADCTRIM0_IFADCOTACURRENT_i4u2 << 15) /**< Shifted mode i4u2 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCOTACURRENT_i4p5u2 (_RAC_IFADCTRIM0_IFADCOTACURRENT_i4p5u2 << 15) /**< Shifted mode i4p5u2 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCOTACURRENT_i5u (_RAC_IFADCTRIM0_IFADCOTACURRENT_i5u << 15) /**< Shifted mode i5u for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCOTACURRENT_i5p5u (_RAC_IFADCTRIM0_IFADCOTACURRENT_i5p5u << 15) /**< Shifted mode i5p5u for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_SHIFT 18 /**< Shift value for RAC_IFADCREFBUFAMPLVL */
+#define _RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_MASK 0x1C0000UL /**< Bit mask for RAC_IFADCREFBUFAMPLVL */
+#define _RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_DEFAULT 0x00000004UL /**< Mode DEFAULT for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v0p88 0x00000000UL /**< Mode v0p88 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v0p91 0x00000001UL /**< Mode v0p91 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v0p94 0x00000002UL /**< Mode v0p94 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v0p97 0x00000003UL /**< Mode v0p97 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v1p00 0x00000004UL /**< Mode v1p00 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v1p03 0x00000005UL /**< Mode v1p03 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v1p06 0x00000006UL /**< Mode v1p06 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v1p09 0x00000007UL /**< Mode v1p09 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_DEFAULT (_RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_DEFAULT << 18) /**< Shifted mode DEFAULT for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v0p88 (_RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v0p88 << 18) /**< Shifted mode v0p88 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v0p91 (_RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v0p91 << 18) /**< Shifted mode v0p91 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v0p94 (_RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v0p94 << 18) /**< Shifted mode v0p94 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v0p97 (_RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v0p97 << 18) /**< Shifted mode v0p97 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v1p00 (_RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v1p00 << 18) /**< Shifted mode v1p00 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v1p03 (_RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v1p03 << 18) /**< Shifted mode v1p03 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v1p06 (_RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v1p06 << 18) /**< Shifted mode v1p06 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v1p09 (_RAC_IFADCTRIM0_IFADCREFBUFAMPLVL_v1p09 << 18) /**< Shifted mode v1p09 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCREFBUFCURLVL_SHIFT 21 /**< Shift value for RAC_IFADCREFBUFCURLVL */
+#define _RAC_IFADCTRIM0_IFADCREFBUFCURLVL_MASK 0xE00000UL /**< Bit mask for RAC_IFADCREFBUFCURLVL */
+#define _RAC_IFADCTRIM0_IFADCREFBUFCURLVL_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i4u 0x00000000UL /**< Mode i4u for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i4p5u 0x00000001UL /**< Mode i4p5u for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i5u 0x00000002UL /**< Mode i5u for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i5p5u 0x00000003UL /**< Mode i5p5u for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i5u2 0x00000004UL /**< Mode i5u2 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i5p5u2 0x00000005UL /**< Mode i5p5u2 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i6u 0x00000006UL /**< Mode i6u for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i6p5u 0x00000007UL /**< Mode i6p5u for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCREFBUFCURLVL_DEFAULT (_RAC_IFADCTRIM0_IFADCREFBUFCURLVL_DEFAULT << 21) /**< Shifted mode DEFAULT for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i4u (_RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i4u << 21) /**< Shifted mode i4u for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i4p5u (_RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i4p5u << 21) /**< Shifted mode i4p5u for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i5u (_RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i5u << 21) /**< Shifted mode i5u for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i5p5u (_RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i5p5u << 21) /**< Shifted mode i5p5u for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i5u2 (_RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i5u2 << 21) /**< Shifted mode i5u2 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i5p5u2 (_RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i5p5u2 << 21) /**< Shifted mode i5p5u2 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i6u (_RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i6u << 21) /**< Shifted mode i6u for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i6p5u (_RAC_IFADCTRIM0_IFADCREFBUFCURLVL_i6p5u << 21) /**< Shifted mode i6p5u for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCSIDETONEAMP_SHIFT 24 /**< Shift value for RAC_IFADCSIDETONEAMP */
+#define _RAC_IFADCTRIM0_IFADCSIDETONEAMP_MASK 0x7000000UL /**< Bit mask for RAC_IFADCSIDETONEAMP */
+#define _RAC_IFADCTRIM0_IFADCSIDETONEAMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_5p68mV 0x00000000UL /**< Mode diff_5p68mV for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_29p1mV 0x00000001UL /**< Mode diff_29p1mV for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_9p73mV 0x00000002UL /**< Mode diff_9p73mV for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_76p9mV 0x00000003UL /**< Mode diff_76p9mV for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_9p68_mV 0x00000004UL /**< Mode diff_9p68_mV for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_51_mV 0x00000005UL /**< Mode diff_51_mV for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_17p2_mV 0x00000006UL /**< Mode diff_17p2_mV for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCSIDETONEAMP_disable 0x00000007UL /**< Mode disable for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCSIDETONEAMP_DEFAULT (_RAC_IFADCTRIM0_IFADCSIDETONEAMP_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_5p68mV (_RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_5p68mV << 24) /**< Shifted mode diff_5p68mV for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_29p1mV (_RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_29p1mV << 24) /**< Shifted mode diff_29p1mV for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_9p73mV (_RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_9p73mV << 24) /**< Shifted mode diff_9p73mV for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_76p9mV (_RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_76p9mV << 24) /**< Shifted mode diff_76p9mV for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_9p68_mV (_RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_9p68_mV << 24) /**< Shifted mode diff_9p68_mV for RAC_IFADCTRIM0*/
+#define RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_51_mV (_RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_51_mV << 24) /**< Shifted mode diff_51_mV for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_17p2_mV (_RAC_IFADCTRIM0_IFADCSIDETONEAMP_diff_17p2_mV << 24) /**< Shifted mode diff_17p2_mV for RAC_IFADCTRIM0*/
+#define RAC_IFADCTRIM0_IFADCSIDETONEAMP_disable (_RAC_IFADCTRIM0_IFADCSIDETONEAMP_disable << 24) /**< Shifted mode disable for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCSIDETONEFREQ_SHIFT 27 /**< Shift value for RAC_IFADCSIDETONEFREQ */
+#define _RAC_IFADCTRIM0_IFADCSIDETONEFREQ_MASK 0x38000000UL /**< Bit mask for RAC_IFADCSIDETONEFREQ */
+#define _RAC_IFADCTRIM0_IFADCSIDETONEFREQ_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCSIDETONEFREQ_na0 0x00000000UL /**< Mode na0 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_128 0x00000001UL /**< Mode div_128 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_64 0x00000002UL /**< Mode div_64 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_32 0x00000003UL /**< Mode div_32 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_16 0x00000004UL /**< Mode div_16 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_8 0x00000005UL /**< Mode div_8 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_4 0x00000006UL /**< Mode div_4 for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCSIDETONEFREQ_na7 0x00000007UL /**< Mode na7 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCSIDETONEFREQ_DEFAULT (_RAC_IFADCTRIM0_IFADCSIDETONEFREQ_DEFAULT << 27) /**< Shifted mode DEFAULT for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCSIDETONEFREQ_na0 (_RAC_IFADCTRIM0_IFADCSIDETONEFREQ_na0 << 27) /**< Shifted mode na0 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_128 (_RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_128 << 27) /**< Shifted mode div_128 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_64 (_RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_64 << 27) /**< Shifted mode div_64 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_32 (_RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_32 << 27) /**< Shifted mode div_32 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_16 (_RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_16 << 27) /**< Shifted mode div_16 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_8 (_RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_8 << 27) /**< Shifted mode div_8 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_4 (_RAC_IFADCTRIM0_IFADCSIDETONEFREQ_div_4 << 27) /**< Shifted mode div_4 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCSIDETONEFREQ_na7 (_RAC_IFADCTRIM0_IFADCSIDETONEFREQ_na7 << 27) /**< Shifted mode na7 for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCENHALFMODE (0x1UL << 30) /**< IFADCENHALFMODE */
+#define _RAC_IFADCTRIM0_IFADCENHALFMODE_SHIFT 30 /**< Shift value for RAC_IFADCENHALFMODE */
+#define _RAC_IFADCTRIM0_IFADCENHALFMODE_MASK 0x40000000UL /**< Bit mask for RAC_IFADCENHALFMODE */
+#define _RAC_IFADCTRIM0_IFADCENHALFMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCENHALFMODE_full_speed_mode 0x00000000UL /**< Mode full_speed_mode for RAC_IFADCTRIM0 */
+#define _RAC_IFADCTRIM0_IFADCENHALFMODE_half_speed_mode 0x00000001UL /**< Mode half_speed_mode for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCENHALFMODE_DEFAULT (_RAC_IFADCTRIM0_IFADCENHALFMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for RAC_IFADCTRIM0 */
+#define RAC_IFADCTRIM0_IFADCENHALFMODE_full_speed_mode (_RAC_IFADCTRIM0_IFADCENHALFMODE_full_speed_mode << 30) /**< Shifted mode full_speed_mode for RAC_IFADCTRIM0*/
+#define RAC_IFADCTRIM0_IFADCENHALFMODE_half_speed_mode (_RAC_IFADCTRIM0_IFADCENHALFMODE_half_speed_mode << 30) /**< Shifted mode half_speed_mode for RAC_IFADCTRIM0*/
+
+/* Bit fields for RAC IFADCTRIM1 */
+#define _RAC_IFADCTRIM1_RESETVALUE 0x00000123UL /**< Default value for RAC_IFADCTRIM1 */
+#define _RAC_IFADCTRIM1_MASK 0x000001FFUL /**< Mask for RAC_IFADCTRIM1 */
+#define _RAC_IFADCTRIM1_IFADCVCMLVL_SHIFT 0 /**< Shift value for RAC_IFADCVCMLVL */
+#define _RAC_IFADCTRIM1_IFADCVCMLVL_MASK 0x7UL /**< Bit mask for RAC_IFADCVCMLVL */
+#define _RAC_IFADCTRIM1_IFADCVCMLVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for RAC_IFADCTRIM1 */
+#define _RAC_IFADCTRIM1_IFADCVCMLVL_vcm_475mV 0x00000000UL /**< Mode vcm_475mV for RAC_IFADCTRIM1 */
+#define _RAC_IFADCTRIM1_IFADCVCMLVL_vcm_500mV 0x00000001UL /**< Mode vcm_500mV for RAC_IFADCTRIM1 */
+#define _RAC_IFADCTRIM1_IFADCVCMLVL_vcm_525mV 0x00000002UL /**< Mode vcm_525mV for RAC_IFADCTRIM1 */
+#define _RAC_IFADCTRIM1_IFADCVCMLVL_vcm_550mV 0x00000003UL /**< Mode vcm_550mV for RAC_IFADCTRIM1 */
+#define _RAC_IFADCTRIM1_IFADCVCMLVL_vcm_575mV 0x00000004UL /**< Mode vcm_575mV for RAC_IFADCTRIM1 */
+#define _RAC_IFADCTRIM1_IFADCVCMLVL_vcm_600mV 0x00000005UL /**< Mode vcm_600mV for RAC_IFADCTRIM1 */
+#define _RAC_IFADCTRIM1_IFADCVCMLVL_vcm_625mV 0x00000006UL /**< Mode vcm_625mV for RAC_IFADCTRIM1 */
+#define _RAC_IFADCTRIM1_IFADCVCMLVL_cm_650mV 0x00000007UL /**< Mode cm_650mV for RAC_IFADCTRIM1 */
+#define RAC_IFADCTRIM1_IFADCVCMLVL_DEFAULT (_RAC_IFADCTRIM1_IFADCVCMLVL_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_IFADCTRIM1 */
+#define RAC_IFADCTRIM1_IFADCVCMLVL_vcm_475mV (_RAC_IFADCTRIM1_IFADCVCMLVL_vcm_475mV << 0) /**< Shifted mode vcm_475mV for RAC_IFADCTRIM1 */
+#define RAC_IFADCTRIM1_IFADCVCMLVL_vcm_500mV (_RAC_IFADCTRIM1_IFADCVCMLVL_vcm_500mV << 0) /**< Shifted mode vcm_500mV for RAC_IFADCTRIM1 */
+#define RAC_IFADCTRIM1_IFADCVCMLVL_vcm_525mV (_RAC_IFADCTRIM1_IFADCVCMLVL_vcm_525mV << 0) /**< Shifted mode vcm_525mV for RAC_IFADCTRIM1 */
+#define RAC_IFADCTRIM1_IFADCVCMLVL_vcm_550mV (_RAC_IFADCTRIM1_IFADCVCMLVL_vcm_550mV << 0) /**< Shifted mode vcm_550mV for RAC_IFADCTRIM1 */
+#define RAC_IFADCTRIM1_IFADCVCMLVL_vcm_575mV (_RAC_IFADCTRIM1_IFADCVCMLVL_vcm_575mV << 0) /**< Shifted mode vcm_575mV for RAC_IFADCTRIM1 */
+#define RAC_IFADCTRIM1_IFADCVCMLVL_vcm_600mV (_RAC_IFADCTRIM1_IFADCVCMLVL_vcm_600mV << 0) /**< Shifted mode vcm_600mV for RAC_IFADCTRIM1 */
+#define RAC_IFADCTRIM1_IFADCVCMLVL_vcm_625mV (_RAC_IFADCTRIM1_IFADCVCMLVL_vcm_625mV << 0) /**< Shifted mode vcm_625mV for RAC_IFADCTRIM1 */
+#define RAC_IFADCTRIM1_IFADCVCMLVL_cm_650mV (_RAC_IFADCTRIM1_IFADCVCMLVL_cm_650mV << 0) /**< Shifted mode cm_650mV for RAC_IFADCTRIM1 */
+#define RAC_IFADCTRIM1_IFADCENNEGRES (0x1UL << 3) /**< IFADCENNEGRES */
+#define _RAC_IFADCTRIM1_IFADCENNEGRES_SHIFT 3 /**< Shift value for RAC_IFADCENNEGRES */
+#define _RAC_IFADCTRIM1_IFADCENNEGRES_MASK 0x8UL /**< Bit mask for RAC_IFADCENNEGRES */
+#define _RAC_IFADCTRIM1_IFADCENNEGRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IFADCTRIM1 */
+#define _RAC_IFADCTRIM1_IFADCENNEGRES_disable 0x00000000UL /**< Mode disable for RAC_IFADCTRIM1 */
+#define _RAC_IFADCTRIM1_IFADCENNEGRES_enable 0x00000001UL /**< Mode enable for RAC_IFADCTRIM1 */
+#define RAC_IFADCTRIM1_IFADCENNEGRES_DEFAULT (_RAC_IFADCTRIM1_IFADCENNEGRES_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_IFADCTRIM1 */
+#define RAC_IFADCTRIM1_IFADCENNEGRES_disable (_RAC_IFADCTRIM1_IFADCENNEGRES_disable << 3) /**< Shifted mode disable for RAC_IFADCTRIM1 */
+#define RAC_IFADCTRIM1_IFADCENNEGRES_enable (_RAC_IFADCTRIM1_IFADCENNEGRES_enable << 3) /**< Shifted mode enable for RAC_IFADCTRIM1 */
+#define _RAC_IFADCTRIM1_IFADCNEGRESCURRENT_SHIFT 4 /**< Shift value for RAC_IFADCNEGRESCURRENT */
+#define _RAC_IFADCTRIM1_IFADCNEGRESCURRENT_MASK 0x70UL /**< Bit mask for RAC_IFADCNEGRESCURRENT */
+#define _RAC_IFADCTRIM1_IFADCNEGRESCURRENT_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_IFADCTRIM1 */
+#define _RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i1p0u 0x00000000UL /**< Mode i1p0u for RAC_IFADCTRIM1 */
+#define _RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i1p5u 0x00000001UL /**< Mode i1p5u for RAC_IFADCTRIM1 */
+#define _RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i2p0u 0x00000002UL /**< Mode i2p0u for RAC_IFADCTRIM1 */
+#define _RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i2p5u 0x00000003UL /**< Mode i2p5u for RAC_IFADCTRIM1 */
+#define _RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i2p0u2 0x00000004UL /**< Mode i2p0u2 for RAC_IFADCTRIM1 */
+#define _RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i2p5u2 0x00000005UL /**< Mode i2p5u2 for RAC_IFADCTRIM1 */
+#define _RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i3p0u 0x00000006UL /**< Mode i3p0u for RAC_IFADCTRIM1 */
+#define _RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i3p5u 0x00000007UL /**< Mode i3p5u for RAC_IFADCTRIM1 */
+#define RAC_IFADCTRIM1_IFADCNEGRESCURRENT_DEFAULT (_RAC_IFADCTRIM1_IFADCNEGRESCURRENT_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_IFADCTRIM1 */
+#define RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i1p0u (_RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i1p0u << 4) /**< Shifted mode i1p0u for RAC_IFADCTRIM1 */
+#define RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i1p5u (_RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i1p5u << 4) /**< Shifted mode i1p5u for RAC_IFADCTRIM1 */
+#define RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i2p0u (_RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i2p0u << 4) /**< Shifted mode i2p0u for RAC_IFADCTRIM1 */
+#define RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i2p5u (_RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i2p5u << 4) /**< Shifted mode i2p5u for RAC_IFADCTRIM1 */
+#define RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i2p0u2 (_RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i2p0u2 << 4) /**< Shifted mode i2p0u2 for RAC_IFADCTRIM1 */
+#define RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i2p5u2 (_RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i2p5u2 << 4) /**< Shifted mode i2p5u2 for RAC_IFADCTRIM1 */
+#define RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i3p0u (_RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i3p0u << 4) /**< Shifted mode i3p0u for RAC_IFADCTRIM1 */
+#define RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i3p5u (_RAC_IFADCTRIM1_IFADCNEGRESCURRENT_i3p5u << 4) /**< Shifted mode i3p5u for RAC_IFADCTRIM1 */
+#define _RAC_IFADCTRIM1_IFADCNEGRESVCM_SHIFT 7 /**< Shift value for RAC_IFADCNEGRESVCM */
+#define _RAC_IFADCTRIM1_IFADCNEGRESVCM_MASK 0x180UL /**< Bit mask for RAC_IFADCNEGRESVCM */
+#define _RAC_IFADCTRIM1_IFADCNEGRESVCM_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_IFADCTRIM1 */
+#define _RAC_IFADCTRIM1_IFADCNEGRESVCM_r210k_x_1uA 0x00000000UL /**< Mode r210k_x_1uA for RAC_IFADCTRIM1 */
+#define _RAC_IFADCTRIM1_IFADCNEGRESVCM_r210k_x_1uA2 0x00000001UL /**< Mode r210k_x_1uA2 for RAC_IFADCTRIM1 */
+#define _RAC_IFADCTRIM1_IFADCNEGRESVCM_r100k_x_2uA 0x00000002UL /**< Mode r100k_x_2uA for RAC_IFADCTRIM1 */
+#define _RAC_IFADCTRIM1_IFADCNEGRESVCM_r50k_x_3uA 0x00000003UL /**< Mode r50k_x_3uA for RAC_IFADCTRIM1 */
+#define RAC_IFADCTRIM1_IFADCNEGRESVCM_DEFAULT (_RAC_IFADCTRIM1_IFADCNEGRESVCM_DEFAULT << 7) /**< Shifted mode DEFAULT for RAC_IFADCTRIM1 */
+#define RAC_IFADCTRIM1_IFADCNEGRESVCM_r210k_x_1uA (_RAC_IFADCTRIM1_IFADCNEGRESVCM_r210k_x_1uA << 7) /**< Shifted mode r210k_x_1uA for RAC_IFADCTRIM1 */
+#define RAC_IFADCTRIM1_IFADCNEGRESVCM_r210k_x_1uA2 (_RAC_IFADCTRIM1_IFADCNEGRESVCM_r210k_x_1uA2 << 7) /**< Shifted mode r210k_x_1uA2 for RAC_IFADCTRIM1*/
+#define RAC_IFADCTRIM1_IFADCNEGRESVCM_r100k_x_2uA (_RAC_IFADCTRIM1_IFADCNEGRESVCM_r100k_x_2uA << 7) /**< Shifted mode r100k_x_2uA for RAC_IFADCTRIM1 */
+#define RAC_IFADCTRIM1_IFADCNEGRESVCM_r50k_x_3uA (_RAC_IFADCTRIM1_IFADCNEGRESVCM_r50k_x_3uA << 7) /**< Shifted mode r50k_x_3uA for RAC_IFADCTRIM1 */
+
+/* Bit fields for RAC IFADCCAL */
+#define _RAC_IFADCCAL_RESETVALUE 0x00000C00UL /**< Default value for RAC_IFADCCAL */
+#define _RAC_IFADCCAL_MASK 0x00FF1F03UL /**< Mask for RAC_IFADCCAL */
+#define RAC_IFADCCAL_IFADCENRCCAL (0x1UL << 0) /**< IFADCENRCCAL */
+#define _RAC_IFADCCAL_IFADCENRCCAL_SHIFT 0 /**< Shift value for RAC_IFADCENRCCAL */
+#define _RAC_IFADCCAL_IFADCENRCCAL_MASK 0x1UL /**< Bit mask for RAC_IFADCENRCCAL */
+#define _RAC_IFADCCAL_IFADCENRCCAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IFADCCAL */
+#define _RAC_IFADCCAL_IFADCENRCCAL_rccal_disable 0x00000000UL /**< Mode rccal_disable for RAC_IFADCCAL */
+#define _RAC_IFADCCAL_IFADCENRCCAL_rccal_enable 0x00000001UL /**< Mode rccal_enable for RAC_IFADCCAL */
+#define RAC_IFADCCAL_IFADCENRCCAL_DEFAULT (_RAC_IFADCCAL_IFADCENRCCAL_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_IFADCCAL */
+#define RAC_IFADCCAL_IFADCENRCCAL_rccal_disable (_RAC_IFADCCAL_IFADCENRCCAL_rccal_disable << 0) /**< Shifted mode rccal_disable for RAC_IFADCCAL */
+#define RAC_IFADCCAL_IFADCENRCCAL_rccal_enable (_RAC_IFADCCAL_IFADCENRCCAL_rccal_enable << 0) /**< Shifted mode rccal_enable for RAC_IFADCCAL */
+#define RAC_IFADCCAL_IFADCTUNERCCALMODE (0x1UL << 1) /**< IFADCTUNERCCALMODE */
+#define _RAC_IFADCCAL_IFADCTUNERCCALMODE_SHIFT 1 /**< Shift value for RAC_IFADCTUNERCCALMODE */
+#define _RAC_IFADCCAL_IFADCTUNERCCALMODE_MASK 0x2UL /**< Bit mask for RAC_IFADCTUNERCCALMODE */
+#define _RAC_IFADCCAL_IFADCTUNERCCALMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IFADCCAL */
+#define _RAC_IFADCCAL_IFADCTUNERCCALMODE_SYmode 0x00000000UL /**< Mode SYmode for RAC_IFADCCAL */
+#define _RAC_IFADCCAL_IFADCTUNERCCALMODE_ADCmode 0x00000001UL /**< Mode ADCmode for RAC_IFADCCAL */
+#define RAC_IFADCCAL_IFADCTUNERCCALMODE_DEFAULT (_RAC_IFADCCAL_IFADCTUNERCCALMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_IFADCCAL */
+#define RAC_IFADCCAL_IFADCTUNERCCALMODE_SYmode (_RAC_IFADCCAL_IFADCTUNERCCALMODE_SYmode << 1) /**< Shifted mode SYmode for RAC_IFADCCAL */
+#define RAC_IFADCCAL_IFADCTUNERCCALMODE_ADCmode (_RAC_IFADCCAL_IFADCTUNERCCALMODE_ADCmode << 1) /**< Shifted mode ADCmode for RAC_IFADCCAL */
+#define _RAC_IFADCCAL_IFADCTUNERC_SHIFT 8 /**< Shift value for RAC_IFADCTUNERC */
+#define _RAC_IFADCCAL_IFADCTUNERC_MASK 0x1F00UL /**< Bit mask for RAC_IFADCTUNERC */
+#define _RAC_IFADCCAL_IFADCTUNERC_DEFAULT 0x0000000CUL /**< Mode DEFAULT for RAC_IFADCCAL */
+#define RAC_IFADCCAL_IFADCTUNERC_DEFAULT (_RAC_IFADCCAL_IFADCTUNERC_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_IFADCCAL */
+#define _RAC_IFADCCAL_IFADCRCCALCOUNTERSTARTVAL_SHIFT 16 /**< Shift value for RAC_IFADCRCCALCOUNTERSTARTVAL*/
+#define _RAC_IFADCCAL_IFADCRCCALCOUNTERSTARTVAL_MASK 0xFF0000UL /**< Bit mask for RAC_IFADCRCCALCOUNTERSTARTVAL */
+#define _RAC_IFADCCAL_IFADCRCCALCOUNTERSTARTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IFADCCAL */
+#define RAC_IFADCCAL_IFADCRCCALCOUNTERSTARTVAL_DEFAULT (_RAC_IFADCCAL_IFADCRCCALCOUNTERSTARTVAL_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_IFADCCAL */
+
+/* Bit fields for RAC IFADCSTATUS */
+#define _RAC_IFADCSTATUS_RESETVALUE 0x00000000UL /**< Default value for RAC_IFADCSTATUS */
+#define _RAC_IFADCSTATUS_MASK 0x00000001UL /**< Mask for RAC_IFADCSTATUS */
+#define RAC_IFADCSTATUS_IFADCRCCALOUT (0x1UL << 0) /**< IFADCRCCALOUT */
+#define _RAC_IFADCSTATUS_IFADCRCCALOUT_SHIFT 0 /**< Shift value for RAC_IFADCRCCALOUT */
+#define _RAC_IFADCSTATUS_IFADCRCCALOUT_MASK 0x1UL /**< Bit mask for RAC_IFADCRCCALOUT */
+#define _RAC_IFADCSTATUS_IFADCRCCALOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_IFADCSTATUS */
+#define _RAC_IFADCSTATUS_IFADCRCCALOUT_lo 0x00000000UL /**< Mode lo for RAC_IFADCSTATUS */
+#define _RAC_IFADCSTATUS_IFADCRCCALOUT_hi 0x00000001UL /**< Mode hi for RAC_IFADCSTATUS */
+#define RAC_IFADCSTATUS_IFADCRCCALOUT_DEFAULT (_RAC_IFADCSTATUS_IFADCRCCALOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_IFADCSTATUS */
+#define RAC_IFADCSTATUS_IFADCRCCALOUT_lo (_RAC_IFADCSTATUS_IFADCRCCALOUT_lo << 0) /**< Shifted mode lo for RAC_IFADCSTATUS */
+#define RAC_IFADCSTATUS_IFADCRCCALOUT_hi (_RAC_IFADCSTATUS_IFADCRCCALOUT_hi << 0) /**< Shifted mode hi for RAC_IFADCSTATUS */
+
+/* Bit fields for RAC LNAMIXTRIM0 */
+#define _RAC_LNAMIXTRIM0_RESETVALUE 0x00000110UL /**< Default value for RAC_LNAMIXTRIM0 */
+#define _RAC_LNAMIXTRIM0_MASK 0x000001FFUL /**< Mask for RAC_LNAMIXTRIM0 */
+#define _RAC_LNAMIXTRIM0_LNAMIXCAPSEL0_SHIFT 0 /**< Shift value for RAC_LNAMIXCAPSEL0 */
+#define _RAC_LNAMIXTRIM0_LNAMIXCAPSEL0_MASK 0x7UL /**< Bit mask for RAC_LNAMIXCAPSEL0 */
+#define _RAC_LNAMIXTRIM0_LNAMIXCAPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_LNAMIXTRIM0 */
+#define RAC_LNAMIXTRIM0_LNAMIXCAPSEL0_DEFAULT (_RAC_LNAMIXTRIM0_LNAMIXCAPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM0 */
+#define _RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_SHIFT 3 /**< Shift value for RAC_LNAMIXMXRBIAS0 */
+#define _RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_MASK 0x18UL /**< Bit mask for RAC_LNAMIXMXRBIAS0 */
+#define _RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_LNAMIXTRIM0 */
+#define _RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_bias_1V 0x00000000UL /**< Mode bias_1V for RAC_LNAMIXTRIM0 */
+#define _RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_unused 0x00000001UL /**< Mode unused for RAC_LNAMIXTRIM0 */
+#define _RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_bias_900m 0x00000002UL /**< Mode bias_900m for RAC_LNAMIXTRIM0 */
+#define _RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_bias_800m 0x00000003UL /**< Mode bias_800m for RAC_LNAMIXTRIM0 */
+#define RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_DEFAULT (_RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM0 */
+#define RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_bias_1V (_RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_bias_1V << 3) /**< Shifted mode bias_1V for RAC_LNAMIXTRIM0 */
+#define RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_unused (_RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_unused << 3) /**< Shifted mode unused for RAC_LNAMIXTRIM0 */
+#define RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_bias_900m (_RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_bias_900m << 3) /**< Shifted mode bias_900m for RAC_LNAMIXTRIM0 */
+#define RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_bias_800m (_RAC_LNAMIXTRIM0_LNAMIXMXRBIAS0_bias_800m << 3) /**< Shifted mode bias_800m for RAC_LNAMIXTRIM0 */
+#define _RAC_LNAMIXTRIM0_LNAMIXVOUTADJ0_SHIFT 5 /**< Shift value for RAC_LNAMIXVOUTADJ0 */
+#define _RAC_LNAMIXTRIM0_LNAMIXVOUTADJ0_MASK 0x1E0UL /**< Bit mask for RAC_LNAMIXVOUTADJ0 */
+#define _RAC_LNAMIXTRIM0_LNAMIXVOUTADJ0_DEFAULT 0x00000008UL /**< Mode DEFAULT for RAC_LNAMIXTRIM0 */
+#define RAC_LNAMIXTRIM0_LNAMIXVOUTADJ0_DEFAULT (_RAC_LNAMIXTRIM0_LNAMIXVOUTADJ0_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM0 */
+
+/* Bit fields for RAC LNAMIXTRIM1 */
+#define _RAC_LNAMIXTRIM1_RESETVALUE 0x00000110UL /**< Default value for RAC_LNAMIXTRIM1 */
+#define _RAC_LNAMIXTRIM1_MASK 0x000001FFUL /**< Mask for RAC_LNAMIXTRIM1 */
+#define _RAC_LNAMIXTRIM1_LNAMIXCAPSEL1_SHIFT 0 /**< Shift value for RAC_LNAMIXCAPSEL1 */
+#define _RAC_LNAMIXTRIM1_LNAMIXCAPSEL1_MASK 0x7UL /**< Bit mask for RAC_LNAMIXCAPSEL1 */
+#define _RAC_LNAMIXTRIM1_LNAMIXCAPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_LNAMIXTRIM1 */
+#define RAC_LNAMIXTRIM1_LNAMIXCAPSEL1_DEFAULT (_RAC_LNAMIXTRIM1_LNAMIXCAPSEL1_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM1 */
+#define _RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_SHIFT 3 /**< Shift value for RAC_LNAMIXMXRBIAS1 */
+#define _RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_MASK 0x18UL /**< Bit mask for RAC_LNAMIXMXRBIAS1 */
+#define _RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_LNAMIXTRIM1 */
+#define _RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_bias_1V 0x00000000UL /**< Mode bias_1V for RAC_LNAMIXTRIM1 */
+#define _RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_unused 0x00000001UL /**< Mode unused for RAC_LNAMIXTRIM1 */
+#define _RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_bias_900m 0x00000002UL /**< Mode bias_900m for RAC_LNAMIXTRIM1 */
+#define _RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_bias_800m 0x00000003UL /**< Mode bias_800m for RAC_LNAMIXTRIM1 */
+#define RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_DEFAULT (_RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM1 */
+#define RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_bias_1V (_RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_bias_1V << 3) /**< Shifted mode bias_1V for RAC_LNAMIXTRIM1 */
+#define RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_unused (_RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_unused << 3) /**< Shifted mode unused for RAC_LNAMIXTRIM1 */
+#define RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_bias_900m (_RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_bias_900m << 3) /**< Shifted mode bias_900m for RAC_LNAMIXTRIM1 */
+#define RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_bias_800m (_RAC_LNAMIXTRIM1_LNAMIXMXRBIAS1_bias_800m << 3) /**< Shifted mode bias_800m for RAC_LNAMIXTRIM1 */
+#define _RAC_LNAMIXTRIM1_LNAMIXVOUTADJ1_SHIFT 5 /**< Shift value for RAC_LNAMIXVOUTADJ1 */
+#define _RAC_LNAMIXTRIM1_LNAMIXVOUTADJ1_MASK 0x1E0UL /**< Bit mask for RAC_LNAMIXVOUTADJ1 */
+#define _RAC_LNAMIXTRIM1_LNAMIXVOUTADJ1_DEFAULT 0x00000008UL /**< Mode DEFAULT for RAC_LNAMIXTRIM1 */
+#define RAC_LNAMIXTRIM1_LNAMIXVOUTADJ1_DEFAULT (_RAC_LNAMIXTRIM1_LNAMIXVOUTADJ1_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM1 */
+
+/* Bit fields for RAC LNAMIXTRIM2 */
+#define _RAC_LNAMIXTRIM2_RESETVALUE 0x545033D0UL /**< Default value for RAC_LNAMIXTRIM2 */
+#define _RAC_LNAMIXTRIM2_MASK 0x7FF8FFF0UL /**< Mask for RAC_LNAMIXTRIM2 */
+#define _RAC_LNAMIXTRIM2_LNAMIXCURCTRL_SHIFT 4 /**< Shift value for RAC_LNAMIXCURCTRL */
+#define _RAC_LNAMIXTRIM2_LNAMIXCURCTRL_MASK 0x3F0UL /**< Bit mask for RAC_LNAMIXCURCTRL */
+#define _RAC_LNAMIXTRIM2_LNAMIXCURCTRL_DEFAULT 0x0000003DUL /**< Mode DEFAULT for RAC_LNAMIXTRIM2 */
+#define RAC_LNAMIXTRIM2_LNAMIXCURCTRL_DEFAULT (_RAC_LNAMIXTRIM2_LNAMIXCURCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM2 */
+#define _RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_SHIFT 10 /**< Shift value for RAC_LNAMIXHIGHCUR */
+#define _RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_MASK 0xC00UL /**< Bit mask for RAC_LNAMIXHIGHCUR */
+#define _RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_LNAMIXTRIM2 */
+#define _RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_current_470uA 0x00000000UL /**< Mode current_470uA for RAC_LNAMIXTRIM2 */
+#define _RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_current_530uA 0x00000001UL /**< Mode current_530uA for RAC_LNAMIXTRIM2 */
+#define _RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_unused 0x00000002UL /**< Mode unused for RAC_LNAMIXTRIM2 */
+#define _RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_current_590uA 0x00000003UL /**< Mode current_590uA for RAC_LNAMIXTRIM2 */
+#define RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_DEFAULT (_RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM2 */
+#define RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_current_470uA (_RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_current_470uA << 10) /**< Shifted mode current_470uA for RAC_LNAMIXTRIM2*/
+#define RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_current_530uA (_RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_current_530uA << 10) /**< Shifted mode current_530uA for RAC_LNAMIXTRIM2*/
+#define RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_unused (_RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_unused << 10) /**< Shifted mode unused for RAC_LNAMIXTRIM2 */
+#define RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_current_590uA (_RAC_LNAMIXTRIM2_LNAMIXHIGHCUR_current_590uA << 10) /**< Shifted mode current_590uA for RAC_LNAMIXTRIM2*/
+#define _RAC_LNAMIXTRIM2_LNAMIXLOWCUR_SHIFT 12 /**< Shift value for RAC_LNAMIXLOWCUR */
+#define _RAC_LNAMIXTRIM2_LNAMIXLOWCUR_MASK 0xF000UL /**< Bit mask for RAC_LNAMIXLOWCUR */
+#define _RAC_LNAMIXTRIM2_LNAMIXLOWCUR_DEFAULT 0x00000003UL /**< Mode DEFAULT for RAC_LNAMIXTRIM2 */
+#define RAC_LNAMIXTRIM2_LNAMIXLOWCUR_DEFAULT (_RAC_LNAMIXTRIM2_LNAMIXLOWCUR_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM2 */
+#define _RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_SHIFT 19 /**< Shift value for RAC_LNAMIXNCASADJ0 */
+#define _RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_MASK 0x180000UL /**< Bit mask for RAC_LNAMIXNCASADJ0 */
+#define _RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_LNAMIXTRIM2 */
+#define _RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_ncas_1V 0x00000000UL /**< Mode ncas_1V for RAC_LNAMIXTRIM2 */
+#define _RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_unused 0x00000001UL /**< Mode unused for RAC_LNAMIXTRIM2 */
+#define _RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_ncas_950m 0x00000002UL /**< Mode ncas_950m for RAC_LNAMIXTRIM2 */
+#define _RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_ncas_900m 0x00000003UL /**< Mode ncas_900m for RAC_LNAMIXTRIM2 */
+#define RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_DEFAULT (_RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_DEFAULT << 19) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM2 */
+#define RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_ncas_1V (_RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_ncas_1V << 19) /**< Shifted mode ncas_1V for RAC_LNAMIXTRIM2 */
+#define RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_unused (_RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_unused << 19) /**< Shifted mode unused for RAC_LNAMIXTRIM2 */
+#define RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_ncas_950m (_RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_ncas_950m << 19) /**< Shifted mode ncas_950m for RAC_LNAMIXTRIM2 */
+#define RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_ncas_900m (_RAC_LNAMIXTRIM2_LNAMIXNCASADJ0_ncas_900m << 19) /**< Shifted mode ncas_900m for RAC_LNAMIXTRIM2 */
+#define _RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_SHIFT 21 /**< Shift value for RAC_LNAMIXPCASADJ0 */
+#define _RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_MASK 0x600000UL /**< Bit mask for RAC_LNAMIXPCASADJ0 */
+#define _RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_LNAMIXTRIM2 */
+#define _RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_pcas_250m 0x00000000UL /**< Mode pcas_250m for RAC_LNAMIXTRIM2 */
+#define _RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_unused 0x00000001UL /**< Mode unused for RAC_LNAMIXTRIM2 */
+#define _RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_pcas_300m 0x00000002UL /**< Mode pcas_300m for RAC_LNAMIXTRIM2 */
+#define _RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_pcas_350m 0x00000003UL /**< Mode pcas_350m for RAC_LNAMIXTRIM2 */
+#define RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_DEFAULT (_RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_DEFAULT << 21) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM2 */
+#define RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_pcas_250m (_RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_pcas_250m << 21) /**< Shifted mode pcas_250m for RAC_LNAMIXTRIM2 */
+#define RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_unused (_RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_unused << 21) /**< Shifted mode unused for RAC_LNAMIXTRIM2 */
+#define RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_pcas_300m (_RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_pcas_300m << 21) /**< Shifted mode pcas_300m for RAC_LNAMIXTRIM2 */
+#define RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_pcas_350m (_RAC_LNAMIXTRIM2_LNAMIXPCASADJ0_pcas_350m << 21) /**< Shifted mode pcas_350m for RAC_LNAMIXTRIM2 */
+#define _RAC_LNAMIXTRIM2_LNAMIXTRIMVREG_SHIFT 23 /**< Shift value for RAC_LNAMIXTRIMVREG */
+#define _RAC_LNAMIXTRIM2_LNAMIXTRIMVREG_MASK 0x7800000UL /**< Bit mask for RAC_LNAMIXTRIMVREG */
+#define _RAC_LNAMIXTRIM2_LNAMIXTRIMVREG_DEFAULT 0x00000008UL /**< Mode DEFAULT for RAC_LNAMIXTRIM2 */
+#define RAC_LNAMIXTRIM2_LNAMIXTRIMVREG_DEFAULT (_RAC_LNAMIXTRIM2_LNAMIXTRIMVREG_DEFAULT << 23) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM2 */
+#define _RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_SHIFT 27 /**< Shift value for RAC_LNAMIXNCASADJ1 */
+#define _RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_MASK 0x18000000UL /**< Bit mask for RAC_LNAMIXNCASADJ1 */
+#define _RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_LNAMIXTRIM2 */
+#define _RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_ncas_1V 0x00000000UL /**< Mode ncas_1V for RAC_LNAMIXTRIM2 */
+#define _RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_unused 0x00000001UL /**< Mode unused for RAC_LNAMIXTRIM2 */
+#define _RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_ncas_950m 0x00000002UL /**< Mode ncas_950m for RAC_LNAMIXTRIM2 */
+#define _RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_ncas_900m 0x00000003UL /**< Mode ncas_900m for RAC_LNAMIXTRIM2 */
+#define RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_DEFAULT (_RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_DEFAULT << 27) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM2 */
+#define RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_ncas_1V (_RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_ncas_1V << 27) /**< Shifted mode ncas_1V for RAC_LNAMIXTRIM2 */
+#define RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_unused (_RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_unused << 27) /**< Shifted mode unused for RAC_LNAMIXTRIM2 */
+#define RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_ncas_950m (_RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_ncas_950m << 27) /**< Shifted mode ncas_950m for RAC_LNAMIXTRIM2 */
+#define RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_ncas_900m (_RAC_LNAMIXTRIM2_LNAMIXNCASADJ1_ncas_900m << 27) /**< Shifted mode ncas_900m for RAC_LNAMIXTRIM2 */
+#define _RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_SHIFT 29 /**< Shift value for RAC_LNAMIXPCASADJ1 */
+#define _RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_MASK 0x60000000UL /**< Bit mask for RAC_LNAMIXPCASADJ1 */
+#define _RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_LNAMIXTRIM2 */
+#define _RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_pcas_250m 0x00000000UL /**< Mode pcas_250m for RAC_LNAMIXTRIM2 */
+#define _RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_unused 0x00000001UL /**< Mode unused for RAC_LNAMIXTRIM2 */
+#define _RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_pcas_300m 0x00000002UL /**< Mode pcas_300m for RAC_LNAMIXTRIM2 */
+#define _RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_pcas_350m 0x00000003UL /**< Mode pcas_350m for RAC_LNAMIXTRIM2 */
+#define RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_DEFAULT (_RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_DEFAULT << 29) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM2 */
+#define RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_pcas_250m (_RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_pcas_250m << 29) /**< Shifted mode pcas_250m for RAC_LNAMIXTRIM2 */
+#define RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_unused (_RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_unused << 29) /**< Shifted mode unused for RAC_LNAMIXTRIM2 */
+#define RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_pcas_300m (_RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_pcas_300m << 29) /**< Shifted mode pcas_300m for RAC_LNAMIXTRIM2 */
+#define RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_pcas_350m (_RAC_LNAMIXTRIM2_LNAMIXPCASADJ1_pcas_350m << 29) /**< Shifted mode pcas_350m for RAC_LNAMIXTRIM2 */
+
+/* Bit fields for RAC LNAMIXTRIM3 */
+#define _RAC_LNAMIXTRIM3_RESETVALUE 0x00000208UL /**< Default value for RAC_LNAMIXTRIM3 */
+#define _RAC_LNAMIXTRIM3_MASK 0x00000FFFUL /**< Mask for RAC_LNAMIXTRIM3 */
+#define _RAC_LNAMIXTRIM3_LNAMIXIBIASADJ0_SHIFT 0 /**< Shift value for RAC_LNAMIXIBIASADJ0 */
+#define _RAC_LNAMIXTRIM3_LNAMIXIBIASADJ0_MASK 0x3FUL /**< Bit mask for RAC_LNAMIXIBIASADJ0 */
+#define _RAC_LNAMIXTRIM3_LNAMIXIBIASADJ0_DEFAULT 0x00000008UL /**< Mode DEFAULT for RAC_LNAMIXTRIM3 */
+#define RAC_LNAMIXTRIM3_LNAMIXIBIASADJ0_DEFAULT (_RAC_LNAMIXTRIM3_LNAMIXIBIASADJ0_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM3 */
+#define _RAC_LNAMIXTRIM3_LNAMIXIBIASADJ1_SHIFT 6 /**< Shift value for RAC_LNAMIXIBIASADJ1 */
+#define _RAC_LNAMIXTRIM3_LNAMIXIBIASADJ1_MASK 0xFC0UL /**< Bit mask for RAC_LNAMIXIBIASADJ1 */
+#define _RAC_LNAMIXTRIM3_LNAMIXIBIASADJ1_DEFAULT 0x00000008UL /**< Mode DEFAULT for RAC_LNAMIXTRIM3 */
+#define RAC_LNAMIXTRIM3_LNAMIXIBIASADJ1_DEFAULT (_RAC_LNAMIXTRIM3_LNAMIXIBIASADJ1_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM3 */
+
+/* Bit fields for RAC LNAMIXTRIM4 */
+#define _RAC_LNAMIXTRIM4_RESETVALUE 0x88082002UL /**< Default value for RAC_LNAMIXTRIM4 */
+#define _RAC_LNAMIXTRIM4_MASK 0xFF0FFF03UL /**< Mask for RAC_LNAMIXTRIM4 */
+#define _RAC_LNAMIXTRIM4_LNAMIXRFPKDBWSEL_SHIFT 0 /**< Shift value for RAC_LNAMIXRFPKDBWSEL */
+#define _RAC_LNAMIXTRIM4_LNAMIXRFPKDBWSEL_MASK 0x3UL /**< Bit mask for RAC_LNAMIXRFPKDBWSEL */
+#define _RAC_LNAMIXTRIM4_LNAMIXRFPKDBWSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_LNAMIXTRIM4 */
+#define RAC_LNAMIXTRIM4_LNAMIXRFPKDBWSEL_DEFAULT (_RAC_LNAMIXTRIM4_LNAMIXRFPKDBWSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM4 */
+#define _RAC_LNAMIXTRIM4_LNAMIXRFPKDCALCMLO_SHIFT 8 /**< Shift value for RAC_LNAMIXRFPKDCALCMLO */
+#define _RAC_LNAMIXTRIM4_LNAMIXRFPKDCALCMLO_MASK 0x3F00UL /**< Bit mask for RAC_LNAMIXRFPKDCALCMLO */
+#define _RAC_LNAMIXTRIM4_LNAMIXRFPKDCALCMLO_DEFAULT 0x00000020UL /**< Mode DEFAULT for RAC_LNAMIXTRIM4 */
+#define RAC_LNAMIXTRIM4_LNAMIXRFPKDCALCMLO_DEFAULT (_RAC_LNAMIXTRIM4_LNAMIXRFPKDCALCMLO_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM4 */
+#define _RAC_LNAMIXTRIM4_LNAMIXRFPKDCALCMHI_SHIFT 14 /**< Shift value for RAC_LNAMIXRFPKDCALCMHI */
+#define _RAC_LNAMIXTRIM4_LNAMIXRFPKDCALCMHI_MASK 0xFC000UL /**< Bit mask for RAC_LNAMIXRFPKDCALCMHI */
+#define _RAC_LNAMIXTRIM4_LNAMIXRFPKDCALCMHI_DEFAULT 0x00000020UL /**< Mode DEFAULT for RAC_LNAMIXTRIM4 */
+#define RAC_LNAMIXTRIM4_LNAMIXRFPKDCALCMHI_DEFAULT (_RAC_LNAMIXTRIM4_LNAMIXRFPKDCALCMHI_DEFAULT << 14) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM4 */
+#define _RAC_LNAMIXTRIM4_LNAMIXRFPKDTHRESHSELLO_SHIFT 24 /**< Shift value for RAC_LNAMIXRFPKDTHRESHSELLO */
+#define _RAC_LNAMIXTRIM4_LNAMIXRFPKDTHRESHSELLO_MASK 0xF000000UL /**< Bit mask for RAC_LNAMIXRFPKDTHRESHSELLO */
+#define _RAC_LNAMIXTRIM4_LNAMIXRFPKDTHRESHSELLO_DEFAULT 0x00000008UL /**< Mode DEFAULT for RAC_LNAMIXTRIM4 */
+#define RAC_LNAMIXTRIM4_LNAMIXRFPKDTHRESHSELLO_DEFAULT (_RAC_LNAMIXTRIM4_LNAMIXRFPKDTHRESHSELLO_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM4 */
+#define _RAC_LNAMIXTRIM4_LNAMIXRFPKDTHRESHSELHI_SHIFT 28 /**< Shift value for RAC_LNAMIXRFPKDTHRESHSELHI */
+#define _RAC_LNAMIXTRIM4_LNAMIXRFPKDTHRESHSELHI_MASK 0xF0000000UL /**< Bit mask for RAC_LNAMIXRFPKDTHRESHSELHI */
+#define _RAC_LNAMIXTRIM4_LNAMIXRFPKDTHRESHSELHI_DEFAULT 0x00000008UL /**< Mode DEFAULT for RAC_LNAMIXTRIM4 */
+#define RAC_LNAMIXTRIM4_LNAMIXRFPKDTHRESHSELHI_DEFAULT (_RAC_LNAMIXTRIM4_LNAMIXRFPKDTHRESHSELHI_DEFAULT << 28) /**< Shifted mode DEFAULT for RAC_LNAMIXTRIM4 */
+
+/* Bit fields for RAC LNAMIXCAL */
+#define _RAC_LNAMIXCAL_RESETVALUE 0x000007E0UL /**< Default value for RAC_LNAMIXCAL */
+#define _RAC_LNAMIXCAL_MASK 0x000007FDUL /**< Mask for RAC_LNAMIXCAL */
+#define RAC_LNAMIXCAL_LNAMIXCALEN (0x1UL << 0) /**< LNAMIXCALPMOSEN */
+#define _RAC_LNAMIXCAL_LNAMIXCALEN_SHIFT 0 /**< Shift value for RAC_LNAMIXCALEN */
+#define _RAC_LNAMIXCAL_LNAMIXCALEN_MASK 0x1UL /**< Bit mask for RAC_LNAMIXCALEN */
+#define _RAC_LNAMIXCAL_LNAMIXCALEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_LNAMIXCAL */
+#define _RAC_LNAMIXCAL_LNAMIXCALEN_cal_disable 0x00000000UL /**< Mode cal_disable for RAC_LNAMIXCAL */
+#define _RAC_LNAMIXCAL_LNAMIXCALEN_cal_enable 0x00000001UL /**< Mode cal_enable for RAC_LNAMIXCAL */
+#define RAC_LNAMIXCAL_LNAMIXCALEN_DEFAULT (_RAC_LNAMIXCAL_LNAMIXCALEN_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_LNAMIXCAL */
+#define RAC_LNAMIXCAL_LNAMIXCALEN_cal_disable (_RAC_LNAMIXCAL_LNAMIXCALEN_cal_disable << 0) /**< Shifted mode cal_disable for RAC_LNAMIXCAL */
+#define RAC_LNAMIXCAL_LNAMIXCALEN_cal_enable (_RAC_LNAMIXCAL_LNAMIXCALEN_cal_enable << 0) /**< Shifted mode cal_enable for RAC_LNAMIXCAL */
+#define RAC_LNAMIXCAL_LNAMIXCALVMODE (0x1UL << 2) /**< LNAMIXCALVMODE */
+#define _RAC_LNAMIXCAL_LNAMIXCALVMODE_SHIFT 2 /**< Shift value for RAC_LNAMIXCALVMODE */
+#define _RAC_LNAMIXCAL_LNAMIXCALVMODE_MASK 0x4UL /**< Bit mask for RAC_LNAMIXCALVMODE */
+#define _RAC_LNAMIXCAL_LNAMIXCALVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_LNAMIXCAL */
+#define _RAC_LNAMIXCAL_LNAMIXCALVMODE_current_mode 0x00000000UL /**< Mode current_mode for RAC_LNAMIXCAL */
+#define _RAC_LNAMIXCAL_LNAMIXCALVMODE_voltage_mode 0x00000001UL /**< Mode voltage_mode for RAC_LNAMIXCAL */
+#define RAC_LNAMIXCAL_LNAMIXCALVMODE_DEFAULT (_RAC_LNAMIXCAL_LNAMIXCALVMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_LNAMIXCAL */
+#define RAC_LNAMIXCAL_LNAMIXCALVMODE_current_mode (_RAC_LNAMIXCAL_LNAMIXCALVMODE_current_mode << 2) /**< Shifted mode current_mode for RAC_LNAMIXCAL */
+#define RAC_LNAMIXCAL_LNAMIXCALVMODE_voltage_mode (_RAC_LNAMIXCAL_LNAMIXCALVMODE_voltage_mode << 2) /**< Shifted mode voltage_mode for RAC_LNAMIXCAL */
+#define RAC_LNAMIXCAL_LNAMIXENIRCAL0 (0x1UL << 3) /**< LNAMIXENIRCAL0 */
+#define _RAC_LNAMIXCAL_LNAMIXENIRCAL0_SHIFT 3 /**< Shift value for RAC_LNAMIXENIRCAL0 */
+#define _RAC_LNAMIXCAL_LNAMIXENIRCAL0_MASK 0x8UL /**< Bit mask for RAC_LNAMIXENIRCAL0 */
+#define _RAC_LNAMIXCAL_LNAMIXENIRCAL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_LNAMIXCAL */
+#define _RAC_LNAMIXCAL_LNAMIXENIRCAL0_disable 0x00000000UL /**< Mode disable for RAC_LNAMIXCAL */
+#define _RAC_LNAMIXCAL_LNAMIXENIRCAL0_enable 0x00000001UL /**< Mode enable for RAC_LNAMIXCAL */
+#define RAC_LNAMIXCAL_LNAMIXENIRCAL0_DEFAULT (_RAC_LNAMIXCAL_LNAMIXENIRCAL0_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_LNAMIXCAL */
+#define RAC_LNAMIXCAL_LNAMIXENIRCAL0_disable (_RAC_LNAMIXCAL_LNAMIXENIRCAL0_disable << 3) /**< Shifted mode disable for RAC_LNAMIXCAL */
+#define RAC_LNAMIXCAL_LNAMIXENIRCAL0_enable (_RAC_LNAMIXCAL_LNAMIXENIRCAL0_enable << 3) /**< Shifted mode enable for RAC_LNAMIXCAL */
+#define RAC_LNAMIXCAL_LNAMIXENIRCAL1 (0x1UL << 4) /**< LNAMIXENIRCAL1 */
+#define _RAC_LNAMIXCAL_LNAMIXENIRCAL1_SHIFT 4 /**< Shift value for RAC_LNAMIXENIRCAL1 */
+#define _RAC_LNAMIXCAL_LNAMIXENIRCAL1_MASK 0x10UL /**< Bit mask for RAC_LNAMIXENIRCAL1 */
+#define _RAC_LNAMIXCAL_LNAMIXENIRCAL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_LNAMIXCAL */
+#define _RAC_LNAMIXCAL_LNAMIXENIRCAL1_disable 0x00000000UL /**< Mode disable for RAC_LNAMIXCAL */
+#define _RAC_LNAMIXCAL_LNAMIXENIRCAL1_enable 0x00000001UL /**< Mode enable for RAC_LNAMIXCAL */
+#define RAC_LNAMIXCAL_LNAMIXENIRCAL1_DEFAULT (_RAC_LNAMIXCAL_LNAMIXENIRCAL1_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_LNAMIXCAL */
+#define RAC_LNAMIXCAL_LNAMIXENIRCAL1_disable (_RAC_LNAMIXCAL_LNAMIXENIRCAL1_disable << 4) /**< Shifted mode disable for RAC_LNAMIXCAL */
+#define RAC_LNAMIXCAL_LNAMIXENIRCAL1_enable (_RAC_LNAMIXCAL_LNAMIXENIRCAL1_enable << 4) /**< Shifted mode enable for RAC_LNAMIXCAL */
+#define _RAC_LNAMIXCAL_LNAMIXIRCALAMP0_SHIFT 5 /**< Shift value for RAC_LNAMIXIRCALAMP0 */
+#define _RAC_LNAMIXCAL_LNAMIXIRCALAMP0_MASK 0xE0UL /**< Bit mask for RAC_LNAMIXIRCALAMP0 */
+#define _RAC_LNAMIXCAL_LNAMIXIRCALAMP0_DEFAULT 0x00000007UL /**< Mode DEFAULT for RAC_LNAMIXCAL */
+#define RAC_LNAMIXCAL_LNAMIXIRCALAMP0_DEFAULT (_RAC_LNAMIXCAL_LNAMIXIRCALAMP0_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_LNAMIXCAL */
+#define _RAC_LNAMIXCAL_LNAMIXIRCALAMP1_SHIFT 8 /**< Shift value for RAC_LNAMIXIRCALAMP1 */
+#define _RAC_LNAMIXCAL_LNAMIXIRCALAMP1_MASK 0x700UL /**< Bit mask for RAC_LNAMIXIRCALAMP1 */
+#define _RAC_LNAMIXCAL_LNAMIXIRCALAMP1_DEFAULT 0x00000007UL /**< Mode DEFAULT for RAC_LNAMIXCAL */
+#define RAC_LNAMIXCAL_LNAMIXIRCALAMP1_DEFAULT (_RAC_LNAMIXCAL_LNAMIXIRCALAMP1_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_LNAMIXCAL */
+
+/* Bit fields for RAC LNAMIXEN */
+#define _RAC_LNAMIXEN_RESETVALUE 0x00000000UL /**< Default value for RAC_LNAMIXEN */
+#define _RAC_LNAMIXEN_MASK 0x00000008UL /**< Mask for RAC_LNAMIXEN */
+#define RAC_LNAMIXEN_LNAMIXENLDO (0x1UL << 3) /**< LNAMIXENLDO */
+#define _RAC_LNAMIXEN_LNAMIXENLDO_SHIFT 3 /**< Shift value for RAC_LNAMIXENLDO */
+#define _RAC_LNAMIXEN_LNAMIXENLDO_MASK 0x8UL /**< Bit mask for RAC_LNAMIXENLDO */
+#define _RAC_LNAMIXEN_LNAMIXENLDO_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_LNAMIXEN */
+#define _RAC_LNAMIXEN_LNAMIXENLDO_disable 0x00000000UL /**< Mode disable for RAC_LNAMIXEN */
+#define _RAC_LNAMIXEN_LNAMIXENLDO_enable 0x00000001UL /**< Mode enable for RAC_LNAMIXEN */
+#define RAC_LNAMIXEN_LNAMIXENLDO_DEFAULT (_RAC_LNAMIXEN_LNAMIXENLDO_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_LNAMIXEN */
+#define RAC_LNAMIXEN_LNAMIXENLDO_disable (_RAC_LNAMIXEN_LNAMIXENLDO_disable << 3) /**< Shifted mode disable for RAC_LNAMIXEN */
+#define RAC_LNAMIXEN_LNAMIXENLDO_enable (_RAC_LNAMIXEN_LNAMIXENLDO_enable << 3) /**< Shifted mode enable for RAC_LNAMIXEN */
+
+/* Bit fields for RAC PRECTRL */
+#define _RAC_PRECTRL_RESETVALUE 0x00000026UL /**< Default value for RAC_PRECTRL */
+#define _RAC_PRECTRL_MASK 0x0000003FUL /**< Mask for RAC_PRECTRL */
+#define RAC_PRECTRL_PREBYPFORCE (0x1UL << 0) /**< PREBYPFORCE */
+#define _RAC_PRECTRL_PREBYPFORCE_SHIFT 0 /**< Shift value for RAC_PREBYPFORCE */
+#define _RAC_PRECTRL_PREBYPFORCE_MASK 0x1UL /**< Bit mask for RAC_PREBYPFORCE */
+#define _RAC_PRECTRL_PREBYPFORCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PRECTRL */
+#define _RAC_PRECTRL_PREBYPFORCE_not_forced 0x00000000UL /**< Mode not_forced for RAC_PRECTRL */
+#define _RAC_PRECTRL_PREBYPFORCE_forced 0x00000001UL /**< Mode forced for RAC_PRECTRL */
+#define RAC_PRECTRL_PREBYPFORCE_DEFAULT (_RAC_PRECTRL_PREBYPFORCE_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_PRECTRL */
+#define RAC_PRECTRL_PREBYPFORCE_not_forced (_RAC_PRECTRL_PREBYPFORCE_not_forced << 0) /**< Shifted mode not_forced for RAC_PRECTRL */
+#define RAC_PRECTRL_PREBYPFORCE_forced (_RAC_PRECTRL_PREBYPFORCE_forced << 0) /**< Shifted mode forced for RAC_PRECTRL */
+#define _RAC_PRECTRL_PREREGTRIM_SHIFT 1 /**< Shift value for RAC_PREREGTRIM */
+#define _RAC_PRECTRL_PREREGTRIM_MASK 0xEUL /**< Bit mask for RAC_PREREGTRIM */
+#define _RAC_PRECTRL_PREREGTRIM_DEFAULT 0x00000003UL /**< Mode DEFAULT for RAC_PRECTRL */
+#define _RAC_PRECTRL_PREREGTRIM_v1p61 0x00000000UL /**< Mode v1p61 for RAC_PRECTRL */
+#define _RAC_PRECTRL_PREREGTRIM_v1p68 0x00000001UL /**< Mode v1p68 for RAC_PRECTRL */
+#define _RAC_PRECTRL_PREREGTRIM_v1p74 0x00000002UL /**< Mode v1p74 for RAC_PRECTRL */
+#define _RAC_PRECTRL_PREREGTRIM_v1p80 0x00000003UL /**< Mode v1p80 for RAC_PRECTRL */
+#define _RAC_PRECTRL_PREREGTRIM_v1p86 0x00000004UL /**< Mode v1p86 for RAC_PRECTRL */
+#define _RAC_PRECTRL_PREREGTRIM_v1p91 0x00000005UL /**< Mode v1p91 for RAC_PRECTRL */
+#define _RAC_PRECTRL_PREREGTRIM_v1p96 0x00000006UL /**< Mode v1p96 for RAC_PRECTRL */
+#define _RAC_PRECTRL_PREREGTRIM_v2p00 0x00000007UL /**< Mode v2p00 for RAC_PRECTRL */
+#define RAC_PRECTRL_PREREGTRIM_DEFAULT (_RAC_PRECTRL_PREREGTRIM_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_PRECTRL */
+#define RAC_PRECTRL_PREREGTRIM_v1p61 (_RAC_PRECTRL_PREREGTRIM_v1p61 << 1) /**< Shifted mode v1p61 for RAC_PRECTRL */
+#define RAC_PRECTRL_PREREGTRIM_v1p68 (_RAC_PRECTRL_PREREGTRIM_v1p68 << 1) /**< Shifted mode v1p68 for RAC_PRECTRL */
+#define RAC_PRECTRL_PREREGTRIM_v1p74 (_RAC_PRECTRL_PREREGTRIM_v1p74 << 1) /**< Shifted mode v1p74 for RAC_PRECTRL */
+#define RAC_PRECTRL_PREREGTRIM_v1p80 (_RAC_PRECTRL_PREREGTRIM_v1p80 << 1) /**< Shifted mode v1p80 for RAC_PRECTRL */
+#define RAC_PRECTRL_PREREGTRIM_v1p86 (_RAC_PRECTRL_PREREGTRIM_v1p86 << 1) /**< Shifted mode v1p86 for RAC_PRECTRL */
+#define RAC_PRECTRL_PREREGTRIM_v1p91 (_RAC_PRECTRL_PREREGTRIM_v1p91 << 1) /**< Shifted mode v1p91 for RAC_PRECTRL */
+#define RAC_PRECTRL_PREREGTRIM_v1p96 (_RAC_PRECTRL_PREREGTRIM_v1p96 << 1) /**< Shifted mode v1p96 for RAC_PRECTRL */
+#define RAC_PRECTRL_PREREGTRIM_v2p00 (_RAC_PRECTRL_PREREGTRIM_v2p00 << 1) /**< Shifted mode v2p00 for RAC_PRECTRL */
+#define _RAC_PRECTRL_PREVREFTRIM_SHIFT 4 /**< Shift value for RAC_PREVREFTRIM */
+#define _RAC_PRECTRL_PREVREFTRIM_MASK 0x30UL /**< Bit mask for RAC_PREVREFTRIM */
+#define _RAC_PRECTRL_PREVREFTRIM_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_PRECTRL */
+#define _RAC_PRECTRL_PREVREFTRIM_v0p675 0x00000000UL /**< Mode v0p675 for RAC_PRECTRL */
+#define _RAC_PRECTRL_PREVREFTRIM_v0p688 0x00000001UL /**< Mode v0p688 for RAC_PRECTRL */
+#define _RAC_PRECTRL_PREVREFTRIM_v0p700 0x00000002UL /**< Mode v0p700 for RAC_PRECTRL */
+#define _RAC_PRECTRL_PREVREFTRIM_v0p713 0x00000003UL /**< Mode v0p713 for RAC_PRECTRL */
+#define RAC_PRECTRL_PREVREFTRIM_DEFAULT (_RAC_PRECTRL_PREVREFTRIM_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_PRECTRL */
+#define RAC_PRECTRL_PREVREFTRIM_v0p675 (_RAC_PRECTRL_PREVREFTRIM_v0p675 << 4) /**< Shifted mode v0p675 for RAC_PRECTRL */
+#define RAC_PRECTRL_PREVREFTRIM_v0p688 (_RAC_PRECTRL_PREVREFTRIM_v0p688 << 4) /**< Shifted mode v0p688 for RAC_PRECTRL */
+#define RAC_PRECTRL_PREVREFTRIM_v0p700 (_RAC_PRECTRL_PREVREFTRIM_v0p700 << 4) /**< Shifted mode v0p700 for RAC_PRECTRL */
+#define RAC_PRECTRL_PREVREFTRIM_v0p713 (_RAC_PRECTRL_PREVREFTRIM_v0p713 << 4) /**< Shifted mode v0p713 for RAC_PRECTRL */
+
+/* Bit fields for RAC PATRIM0 */
+#define _RAC_PATRIM0_RESETVALUE 0x00000077UL /**< Default value for RAC_PATRIM0 */
+#define _RAC_PATRIM0_MASK 0x0101FFFFUL /**< Mask for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASN_SHIFT 0 /**< Shift value for RAC_TX0DBMTRIMBIASN */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASN_MASK 0xFUL /**< Bit mask for RAC_TX0DBMTRIMBIASN */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASN_DEFAULT 0x00000007UL /**< Mode DEFAULT for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_367m 0x00000000UL /**< Mode v_367m for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_380m 0x00000001UL /**< Mode v_380m for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_393m 0x00000002UL /**< Mode v_393m for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_406m 0x00000003UL /**< Mode v_406m for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_419m 0x00000004UL /**< Mode v_419m for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_432m 0x00000005UL /**< Mode v_432m for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_445m 0x00000006UL /**< Mode v_445m for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_default_458m 0x00000007UL /**< Mode v_default_458m for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_483m 0x00000008UL /**< Mode v_483m for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_496m 0x00000009UL /**< Mode v_496m for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_509m 0x0000000AUL /**< Mode v_509m for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_522m 0x0000000BUL /**< Mode v_522m for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_535m 0x0000000CUL /**< Mode v_535m for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_548m 0x0000000DUL /**< Mode v_548m for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_561m 0x0000000EUL /**< Mode v_561m for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASN_v_574m 0x0000000FUL /**< Mode v_574m for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASN_DEFAULT (_RAC_PATRIM0_TX0DBMTRIMBIASN_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_367m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_367m << 0) /**< Shifted mode v_367m for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_380m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_380m << 0) /**< Shifted mode v_380m for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_393m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_393m << 0) /**< Shifted mode v_393m for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_406m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_406m << 0) /**< Shifted mode v_406m for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_419m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_419m << 0) /**< Shifted mode v_419m for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_432m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_432m << 0) /**< Shifted mode v_432m for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_445m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_445m << 0) /**< Shifted mode v_445m for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_default_458m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_default_458m << 0) /**< Shifted mode v_default_458m for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_483m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_483m << 0) /**< Shifted mode v_483m for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_496m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_496m << 0) /**< Shifted mode v_496m for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_509m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_509m << 0) /**< Shifted mode v_509m for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_522m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_522m << 0) /**< Shifted mode v_522m for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_535m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_535m << 0) /**< Shifted mode v_535m for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_548m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_548m << 0) /**< Shifted mode v_548m for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_561m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_561m << 0) /**< Shifted mode v_561m for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASN_v_574m (_RAC_PATRIM0_TX0DBMTRIMBIASN_v_574m << 0) /**< Shifted mode v_574m for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASP_SHIFT 4 /**< Shift value for RAC_TX0DBMTRIMBIASP */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASP_MASK 0xF0UL /**< Bit mask for RAC_TX0DBMTRIMBIASP */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASP_DEFAULT 0x00000007UL /**< Mode DEFAULT for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p186 0x00000000UL /**< Mode v_1p186 for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p173 0x00000001UL /**< Mode v_1p173 for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p16 0x00000002UL /**< Mode v_1p16 for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p147 0x00000003UL /**< Mode v_1p147 for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p134 0x00000004UL /**< Mode v_1p134 for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p121 0x00000005UL /**< Mode v_1p121 for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p108 0x00000006UL /**< Mode v_1p108 for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_default_1p095 0x00000007UL /**< Mode v_default_1p095 for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p083 0x00000008UL /**< Mode v_1p083 for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p07 0x00000009UL /**< Mode v_1p07 for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p057 0x0000000AUL /**< Mode v_1p057 for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p044 0x0000000BUL /**< Mode v_1p044 for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p031 0x0000000CUL /**< Mode v_1p031 for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p019 0x0000000DUL /**< Mode v_1p019 for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p006 0x0000000EUL /**< Mode v_1p006 for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TX0DBMTRIMBIASP_v_0p993 0x0000000FUL /**< Mode v_0p993 for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASP_DEFAULT (_RAC_PATRIM0_TX0DBMTRIMBIASP_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p186 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p186 << 4) /**< Shifted mode v_1p186 for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p173 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p173 << 4) /**< Shifted mode v_1p173 for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p16 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p16 << 4) /**< Shifted mode v_1p16 for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p147 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p147 << 4) /**< Shifted mode v_1p147 for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p134 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p134 << 4) /**< Shifted mode v_1p134 for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p121 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p121 << 4) /**< Shifted mode v_1p121 for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p108 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p108 << 4) /**< Shifted mode v_1p108 for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_default_1p095 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_default_1p095 << 4) /**< Shifted mode v_default_1p095 for RAC_PATRIM0*/
+#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p083 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p083 << 4) /**< Shifted mode v_1p083 for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p07 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p07 << 4) /**< Shifted mode v_1p07 for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p057 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p057 << 4) /**< Shifted mode v_1p057 for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p044 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p044 << 4) /**< Shifted mode v_1p044 for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p031 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p031 << 4) /**< Shifted mode v_1p031 for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p019 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p019 << 4) /**< Shifted mode v_1p019 for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p006 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_1p006 << 4) /**< Shifted mode v_1p006 for RAC_PATRIM0 */
+#define RAC_PATRIM0_TX0DBMTRIMBIASP_v_0p993 (_RAC_PATRIM0_TX0DBMTRIMBIASP_v_0p993 << 4) /**< Shifted mode v_0p993 for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TXPAAMPCTRL_SHIFT 8 /**< Shift value for RAC_TXPAAMPCTRL */
+#define _RAC_PATRIM0_TXPAAMPCTRL_MASK 0xFF00UL /**< Bit mask for RAC_TXPAAMPCTRL */
+#define _RAC_PATRIM0_TXPAAMPCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM0 */
+#define RAC_PATRIM0_TXPAAMPCTRL_DEFAULT (_RAC_PATRIM0_TXPAAMPCTRL_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_PATRIM0 */
+#define RAC_PATRIM0_TXPABYPASSREG (0x1UL << 16) /**< TXPABYPASSREG */
+#define _RAC_PATRIM0_TXPABYPASSREG_SHIFT 16 /**< Shift value for RAC_TXPABYPASSREG */
+#define _RAC_PATRIM0_TXPABYPASSREG_MASK 0x10000UL /**< Bit mask for RAC_TXPABYPASSREG */
+#define _RAC_PATRIM0_TXPABYPASSREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TXPABYPASSREG_not_bypass 0x00000000UL /**< Mode not_bypass for RAC_PATRIM0 */
+#define _RAC_PATRIM0_TXPABYPASSREG_bypass 0x00000001UL /**< Mode bypass for RAC_PATRIM0 */
+#define RAC_PATRIM0_TXPABYPASSREG_DEFAULT (_RAC_PATRIM0_TXPABYPASSREG_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_PATRIM0 */
+#define RAC_PATRIM0_TXPABYPASSREG_not_bypass (_RAC_PATRIM0_TXPABYPASSREG_not_bypass << 16) /**< Shifted mode not_bypass for RAC_PATRIM0 */
+#define RAC_PATRIM0_TXPABYPASSREG_bypass (_RAC_PATRIM0_TXPABYPASSREG_bypass << 16) /**< Shifted mode bypass for RAC_PATRIM0 */
+#define RAC_PATRIM0_ENAMPCTRLREG (0x1UL << 24) /**< ENAMPCTRLREG */
+#define _RAC_PATRIM0_ENAMPCTRLREG_SHIFT 24 /**< Shift value for RAC_ENAMPCTRLREG */
+#define _RAC_PATRIM0_ENAMPCTRLREG_MASK 0x1000000UL /**< Bit mask for RAC_ENAMPCTRLREG */
+#define _RAC_PATRIM0_ENAMPCTRLREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM0 */
+#define RAC_PATRIM0_ENAMPCTRLREG_DEFAULT (_RAC_PATRIM0_ENAMPCTRLREG_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_PATRIM0 */
+
+/* Bit fields for RAC PATRIM1 */
+#define _RAC_PATRIM1_RESETVALUE 0x03034373UL /**< Default value for RAC_PATRIM1 */
+#define _RAC_PATRIM1_MASK 0x0777F3F7UL /**< Mask for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_SHIFT 0 /**< Shift value for RAC_TX0DBMTRIMPREDRVREGIBCORE*/
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_MASK 0x3UL /**< Bit mask for RAC_TX0DBMTRIMPREDRVREGIBCORE */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_DEFAULT 0x00000003UL /**< Mode DEFAULT for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_i_4u 0x00000000UL /**< Mode i_4u for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_i_5u 0x00000001UL /**< Mode i_5u for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_i_6u 0x00000002UL /**< Mode i_6u for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_i_default_7u 0x00000003UL /**< Mode i_default_7u for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_DEFAULT (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_i_4u (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_i_4u << 0) /**< Shifted mode i_4u for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_i_5u (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_i_5u << 0) /**< Shifted mode i_5u for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_i_6u (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_i_6u << 0) /**< Shifted mode i_6u for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_i_default_7u (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBCORE_i_default_7u << 0) /**< Shifted mode i_default_7u for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGPSR (0x1UL << 2) /**< TX0DBMTRIMPREDRVREGPSR */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGPSR_SHIFT 2 /**< Shift value for RAC_TX0DBMTRIMPREDRVREGPSR */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGPSR_MASK 0x4UL /**< Bit mask for RAC_TX0DBMTRIMPREDRVREGPSR */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGPSR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGPSR_disable 0x00000000UL /**< Mode disable for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGPSR_enable 0x00000001UL /**< Mode enable for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGPSR_DEFAULT (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGPSR_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGPSR_disable (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGPSR_disable << 2) /**< Shifted mode disable for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGPSR_enable (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGPSR_enable << 2) /**< Shifted mode enable for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_SHIFT 4 /**< Shift value for RAC_TX0DBMTRIMPREDRVREGIBNDIO*/
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_MASK 0xF0UL /**< Bit mask for RAC_TX0DBMTRIMPREDRVREGIBNDIO */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_DEFAULT 0x00000007UL /**< Mode DEFAULT for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p127 0x00000000UL /**< Mode vreg_1p127 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p171 0x00000001UL /**< Mode vreg_1p171 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p209 0x00000002UL /**< Mode vreg_1p209 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p244 0x00000003UL /**< Mode vreg_1p244 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p275 0x00000004UL /**< Mode vreg_1p275 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p305 0x00000005UL /**< Mode vreg_1p305 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p335 0x00000006UL /**< Mode vreg_1p335 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_default_1p362 0x00000007UL /**< Mode vreg_default_1p362 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p388 0x00000008UL /**< Mode vreg_1p388 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p414 0x00000009UL /**< Mode vreg_1p414 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p439 0x0000000AUL /**< Mode vreg_1p439 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p463 0x0000000BUL /**< Mode vreg_1p463 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p486 0x0000000CUL /**< Mode vreg_1p486 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p509 0x0000000DUL /**< Mode vreg_1p509 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p532 0x0000000EUL /**< Mode vreg_1p532 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p555 0x0000000FUL /**< Mode vreg_1p555 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_DEFAULT (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p127 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p127 << 4) /**< Shifted mode vreg_1p127 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p171 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p171 << 4) /**< Shifted mode vreg_1p171 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p209 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p209 << 4) /**< Shifted mode vreg_1p209 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p244 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p244 << 4) /**< Shifted mode vreg_1p244 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p275 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p275 << 4) /**< Shifted mode vreg_1p275 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p305 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p305 << 4) /**< Shifted mode vreg_1p305 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p335 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p335 << 4) /**< Shifted mode vreg_1p335 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_default_1p362 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_default_1p362 << 4) /**< Shifted mode vreg_default_1p362 for RAC_PATRIM1*/
+#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p388 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p388 << 4) /**< Shifted mode vreg_1p388 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p414 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p414 << 4) /**< Shifted mode vreg_1p414 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p439 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p439 << 4) /**< Shifted mode vreg_1p439 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p463 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p463 << 4) /**< Shifted mode vreg_1p463 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p486 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p486 << 4) /**< Shifted mode vreg_1p486 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p509 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p509 << 4) /**< Shifted mode vreg_1p509 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p532 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p532 << 4) /**< Shifted mode vreg_1p532 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p555 (_RAC_PATRIM1_TX0DBMTRIMPREDRVREGIBNDIO_vreg_1p555 << 4) /**< Shifted mode vreg_1p555 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_SHIFT 8 /**< Shift value for RAC_TX0DBMTRIMPREDRVSLOPE */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_MASK 0x300UL /**< Bit mask for RAC_TX0DBMTRIMPREDRVSLOPE */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_DEFAULT 0x00000003UL /**< Mode DEFAULT for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_slope_0 0x00000000UL /**< Mode slope_0 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_slope_1 0x00000001UL /**< Mode slope_1 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_slope_2 0x00000002UL /**< Mode slope_2 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_slope_default_max 0x00000003UL /**< Mode slope_default_max for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_DEFAULT (_RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_slope_0 (_RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_slope_0 << 8) /**< Shifted mode slope_0 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_slope_1 (_RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_slope_1 << 8) /**< Shifted mode slope_1 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_slope_2 (_RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_slope_2 << 8) /**< Shifted mode slope_2 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_slope_default_max (_RAC_PATRIM1_TX0DBMTRIMPREDRVSLOPE_slope_default_max << 8) /**< Shifted mode slope_default_max for RAC_PATRIM1*/
+#define _RAC_PATRIM1_TX0DBMTRIMREGFB_SHIFT 12 /**< Shift value for RAC_TX0DBMTRIMREGFB */
+#define _RAC_PATRIM1_TX0DBMTRIMREGFB_MASK 0xF000UL /**< Bit mask for RAC_TX0DBMTRIMREGFB */
+#define _RAC_PATRIM1_TX0DBMTRIMREGFB_DEFAULT 0x00000004UL /**< Mode DEFAULT for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p976 0x00000000UL /**< Mode v_1p976 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p878 0x00000001UL /**< Mode v_1p878 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p788 0x00000002UL /**< Mode v_1p788 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p707 0x00000003UL /**< Mode v_1p707 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_default_1p633 0x00000004UL /**< Mode v_default_1p633 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p565 0x00000005UL /**< Mode v_1p565 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p503 0x00000006UL /**< Mode v_1p503 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p445 0x00000007UL /**< Mode v_1p445 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p392 0x00000008UL /**< Mode v_1p392 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p342 0x00000009UL /**< Mode v_1p342 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p296 0x0000000AUL /**< Mode v_1p296 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p253 0x0000000BUL /**< Mode v_1p253 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p213 0x0000000CUL /**< Mode v_1p213 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p175 0x0000000DUL /**< Mode v_1p175 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p14 0x0000000EUL /**< Mode v_1p14 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p106 0x0000000FUL /**< Mode v_1p106 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMREGFB_DEFAULT (_RAC_PATRIM1_TX0DBMTRIMREGFB_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p976 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p976 << 12) /**< Shifted mode v_1p976 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p878 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p878 << 12) /**< Shifted mode v_1p878 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p788 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p788 << 12) /**< Shifted mode v_1p788 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p707 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p707 << 12) /**< Shifted mode v_1p707 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_default_1p633 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_default_1p633 << 12) /**< Shifted mode v_default_1p633 for RAC_PATRIM1*/
+#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p565 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p565 << 12) /**< Shifted mode v_1p565 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p503 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p503 << 12) /**< Shifted mode v_1p503 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p445 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p445 << 12) /**< Shifted mode v_1p445 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p392 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p392 << 12) /**< Shifted mode v_1p392 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p342 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p342 << 12) /**< Shifted mode v_1p342 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p296 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p296 << 12) /**< Shifted mode v_1p296 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p253 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p253 << 12) /**< Shifted mode v_1p253 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p213 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p213 << 12) /**< Shifted mode v_1p213 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p175 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p175 << 12) /**< Shifted mode v_1p175 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p14 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p14 << 12) /**< Shifted mode v_1p14 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p106 (_RAC_PATRIM1_TX0DBMTRIMREGFB_v_1p106 << 12) /**< Shifted mode v_1p106 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMREGVREF_SHIFT 16 /**< Shift value for RAC_TX0DBMTRIMREGVREF */
+#define _RAC_PATRIM1_TX0DBMTRIMREGVREF_MASK 0x70000UL /**< Bit mask for RAC_TX0DBMTRIMREGVREF */
+#define _RAC_PATRIM1_TX0DBMTRIMREGVREF_DEFAULT 0x00000003UL /**< Mode DEFAULT for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p572 0x00000000UL /**< Mode v_1p572 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p593 0x00000001UL /**< Mode v_1p593 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p613 0x00000002UL /**< Mode v_1p613 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMREGVREF_v_default_1p634 0x00000003UL /**< Mode v_default_1p634 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p654 0x00000004UL /**< Mode v_1p654 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p674 0x00000005UL /**< Mode v_1p674 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p694 0x00000006UL /**< Mode v_1p694 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p714 0x00000007UL /**< Mode v_1p714 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMREGVREF_DEFAULT (_RAC_PATRIM1_TX0DBMTRIMREGVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p572 (_RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p572 << 16) /**< Shifted mode v_1p572 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p593 (_RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p593 << 16) /**< Shifted mode v_1p593 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p613 (_RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p613 << 16) /**< Shifted mode v_1p613 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMREGVREF_v_default_1p634 (_RAC_PATRIM1_TX0DBMTRIMREGVREF_v_default_1p634 << 16) /**< Shifted mode v_default_1p634 for RAC_PATRIM1*/
+#define RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p654 (_RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p654 << 16) /**< Shifted mode v_1p654 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p674 (_RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p674 << 16) /**< Shifted mode v_1p674 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p694 (_RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p694 << 16) /**< Shifted mode v_1p694 for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p714 (_RAC_PATRIM1_TX0DBMTRIMREGVREF_v_1p714 << 16) /**< Shifted mode v_1p714 for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_SHIFT 20 /**< Shift value for RAC_TX0DBMTRIMTAPCAP100F */
+#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_MASK 0x700000UL /**< Bit mask for RAC_TX0DBMTRIMTAPCAP100F */
+#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_0f 0x00000000UL /**< Mode Ctap_plus_0f for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_100f 0x00000001UL /**< Mode Ctap_plus_100f for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_200f 0x00000002UL /**< Mode Ctap_plus_200f for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_300f 0x00000003UL /**< Mode Ctap_plus_300f for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_400f 0x00000004UL /**< Mode Ctap_plus_400f for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_500f 0x00000005UL /**< Mode Ctap_plus_500f for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_600f 0x00000006UL /**< Mode Ctap_plus_600f for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_700f 0x00000007UL /**< Mode Ctap_plus_700f for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_DEFAULT (_RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_DEFAULT << 20) /**< Shifted mode DEFAULT for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_0f (_RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_0f << 20) /**< Shifted mode Ctap_plus_0f for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_100f (_RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_100f << 20) /**< Shifted mode Ctap_plus_100f for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_200f (_RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_200f << 20) /**< Shifted mode Ctap_plus_200f for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_300f (_RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_300f << 20) /**< Shifted mode Ctap_plus_300f for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_400f (_RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_400f << 20) /**< Shifted mode Ctap_plus_400f for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_500f (_RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_500f << 20) /**< Shifted mode Ctap_plus_500f for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_600f (_RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_600f << 20) /**< Shifted mode Ctap_plus_600f for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_700f (_RAC_PATRIM1_TX0DBMTRIMTAPCAP100F_Ctap_plus_700f << 20) /**< Shifted mode Ctap_plus_700f for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_SHIFT 24 /**< Shift value for RAC_TX0DBMTRIMTAPCAP200F */
+#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_MASK 0x7000000UL /**< Bit mask for RAC_TX0DBMTRIMTAPCAP200F */
+#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_DEFAULT 0x00000003UL /**< Mode DEFAULT for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_0f 0x00000000UL /**< Mode Ctap_plus_0f for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_200f 0x00000001UL /**< Mode Ctap_plus_200f for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_400f 0x00000002UL /**< Mode Ctap_plus_400f for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_600f 0x00000003UL /**< Mode Ctap_plus_600f for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_800f 0x00000004UL /**< Mode Ctap_plus_800f for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_1p 0x00000005UL /**< Mode Ctap_plus_1p for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_1p2p 0x00000006UL /**< Mode Ctap_plus_1p2p for RAC_PATRIM1 */
+#define _RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_1p4p 0x00000007UL /**< Mode Ctap_plus_1p4p for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_DEFAULT (_RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_0f (_RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_0f << 24) /**< Shifted mode Ctap_plus_0f for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_200f (_RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_200f << 24) /**< Shifted mode Ctap_plus_200f for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_400f (_RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_400f << 24) /**< Shifted mode Ctap_plus_400f for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_600f (_RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_600f << 24) /**< Shifted mode Ctap_plus_600f for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_800f (_RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_800f << 24) /**< Shifted mode Ctap_plus_800f for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_1p (_RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_1p << 24) /**< Shifted mode Ctap_plus_1p for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_1p2p (_RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_1p2p << 24) /**< Shifted mode Ctap_plus_1p2p for RAC_PATRIM1 */
+#define RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_1p4p (_RAC_PATRIM1_TX0DBMTRIMTAPCAP200F_Ctap_plus_1p4p << 24) /**< Shifted mode Ctap_plus_1p4p for RAC_PATRIM1 */
+
+/* Bit fields for RAC PATRIM2 */
+#define _RAC_PATRIM2_RESETVALUE 0x00000000UL /**< Default value for RAC_PATRIM2 */
+#define _RAC_PATRIM2_MASK 0x00007777UL /**< Mask for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYN_SHIFT 0 /**< Shift value for RAC_TX0DBMTRIMDUTYCYN */
+#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYN_MASK 0x7UL /**< Bit mask for RAC_TX0DBMTRIMDUTYCYN */
+#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_0pct 0x00000000UL /**< Mode up_0pct for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_1pct 0x00000001UL /**< Mode up_1pct for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_2pct 0x00000002UL /**< Mode up_2pct for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_3pct 0x00000003UL /**< Mode up_3pct for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_4pct 0x00000004UL /**< Mode up_4pct for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_5pct 0x00000005UL /**< Mode up_5pct for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_6pct 0x00000006UL /**< Mode up_6pct for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYN_na 0x00000007UL /**< Mode na for RAC_PATRIM2 */
+#define RAC_PATRIM2_TX0DBMTRIMDUTYCYN_DEFAULT (_RAC_PATRIM2_TX0DBMTRIMDUTYCYN_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_PATRIM2 */
+#define RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_0pct (_RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_0pct << 0) /**< Shifted mode up_0pct for RAC_PATRIM2 */
+#define RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_1pct (_RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_1pct << 0) /**< Shifted mode up_1pct for RAC_PATRIM2 */
+#define RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_2pct (_RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_2pct << 0) /**< Shifted mode up_2pct for RAC_PATRIM2 */
+#define RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_3pct (_RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_3pct << 0) /**< Shifted mode up_3pct for RAC_PATRIM2 */
+#define RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_4pct (_RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_4pct << 0) /**< Shifted mode up_4pct for RAC_PATRIM2 */
+#define RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_5pct (_RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_5pct << 0) /**< Shifted mode up_5pct for RAC_PATRIM2 */
+#define RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_6pct (_RAC_PATRIM2_TX0DBMTRIMDUTYCYN_up_6pct << 0) /**< Shifted mode up_6pct for RAC_PATRIM2 */
+#define RAC_PATRIM2_TX0DBMTRIMDUTYCYN_na (_RAC_PATRIM2_TX0DBMTRIMDUTYCYN_na << 0) /**< Shifted mode na for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYP_SHIFT 4 /**< Shift value for RAC_TX0DBMTRIMDUTYCYP */
+#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYP_MASK 0x70UL /**< Bit mask for RAC_TX0DBMTRIMDUTYCYP */
+#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_0pct 0x00000000UL /**< Mode dn_0pct for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_1pct 0x00000001UL /**< Mode dn_1pct for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_2pct 0x00000002UL /**< Mode dn_2pct for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_3pct 0x00000003UL /**< Mode dn_3pct for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_4pct 0x00000004UL /**< Mode dn_4pct for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_5pct 0x00000005UL /**< Mode dn_5pct for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_6pct 0x00000006UL /**< Mode dn_6pct for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TX0DBMTRIMDUTYCYP_na 0x00000007UL /**< Mode na for RAC_PATRIM2 */
+#define RAC_PATRIM2_TX0DBMTRIMDUTYCYP_DEFAULT (_RAC_PATRIM2_TX0DBMTRIMDUTYCYP_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_PATRIM2 */
+#define RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_0pct (_RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_0pct << 4) /**< Shifted mode dn_0pct for RAC_PATRIM2 */
+#define RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_1pct (_RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_1pct << 4) /**< Shifted mode dn_1pct for RAC_PATRIM2 */
+#define RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_2pct (_RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_2pct << 4) /**< Shifted mode dn_2pct for RAC_PATRIM2 */
+#define RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_3pct (_RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_3pct << 4) /**< Shifted mode dn_3pct for RAC_PATRIM2 */
+#define RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_4pct (_RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_4pct << 4) /**< Shifted mode dn_4pct for RAC_PATRIM2 */
+#define RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_5pct (_RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_5pct << 4) /**< Shifted mode dn_5pct for RAC_PATRIM2 */
+#define RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_6pct (_RAC_PATRIM2_TX0DBMTRIMDUTYCYP_dn_6pct << 4) /**< Shifted mode dn_6pct for RAC_PATRIM2 */
+#define RAC_PATRIM2_TX0DBMTRIMDUTYCYP_na (_RAC_PATRIM2_TX0DBMTRIMDUTYCYP_na << 4) /**< Shifted mode na for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_SHIFT 8 /**< Shift value for RAC_TXPATRIM10DBMDUTYCYN */
+#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_MASK 0x700UL /**< Bit mask for RAC_TXPATRIM10DBMDUTYCYN */
+#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_0pct 0x00000000UL /**< Mode up_0pct for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_1pct 0x00000001UL /**< Mode up_1pct for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_2pct 0x00000002UL /**< Mode up_2pct for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_3pct 0x00000003UL /**< Mode up_3pct for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_4pct 0x00000004UL /**< Mode up_4pct for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_5pct 0x00000005UL /**< Mode up_5pct for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_6pct 0x00000006UL /**< Mode up_6pct for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_na 0x00000007UL /**< Mode na for RAC_PATRIM2 */
+#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_DEFAULT (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_PATRIM2 */
+#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_0pct (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_0pct << 8) /**< Shifted mode up_0pct for RAC_PATRIM2 */
+#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_1pct (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_1pct << 8) /**< Shifted mode up_1pct for RAC_PATRIM2 */
+#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_2pct (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_2pct << 8) /**< Shifted mode up_2pct for RAC_PATRIM2 */
+#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_3pct (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_3pct << 8) /**< Shifted mode up_3pct for RAC_PATRIM2 */
+#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_4pct (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_4pct << 8) /**< Shifted mode up_4pct for RAC_PATRIM2 */
+#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_5pct (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_5pct << 8) /**< Shifted mode up_5pct for RAC_PATRIM2 */
+#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_6pct (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_up_6pct << 8) /**< Shifted mode up_6pct for RAC_PATRIM2 */
+#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_na (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYN_na << 8) /**< Shifted mode na for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_SHIFT 12 /**< Shift value for RAC_TXPATRIM10DBMDUTYCYP */
+#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_MASK 0x7000UL /**< Bit mask for RAC_TXPATRIM10DBMDUTYCYP */
+#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_0pct 0x00000000UL /**< Mode dn_0pct for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_1pct 0x00000001UL /**< Mode dn_1pct for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_2pct 0x00000002UL /**< Mode dn_2pct for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_3pct 0x00000003UL /**< Mode dn_3pct for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_4pct 0x00000004UL /**< Mode dn_4pct for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_5pct 0x00000005UL /**< Mode dn_5pct for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_6pct 0x00000006UL /**< Mode dn_6pct for RAC_PATRIM2 */
+#define _RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_na 0x00000007UL /**< Mode na for RAC_PATRIM2 */
+#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_DEFAULT (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_PATRIM2 */
+#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_0pct (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_0pct << 12) /**< Shifted mode dn_0pct for RAC_PATRIM2 */
+#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_1pct (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_1pct << 12) /**< Shifted mode dn_1pct for RAC_PATRIM2 */
+#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_2pct (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_2pct << 12) /**< Shifted mode dn_2pct for RAC_PATRIM2 */
+#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_3pct (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_3pct << 12) /**< Shifted mode dn_3pct for RAC_PATRIM2 */
+#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_4pct (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_4pct << 12) /**< Shifted mode dn_4pct for RAC_PATRIM2 */
+#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_5pct (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_5pct << 12) /**< Shifted mode dn_5pct for RAC_PATRIM2 */
+#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_6pct (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_dn_6pct << 12) /**< Shifted mode dn_6pct for RAC_PATRIM2 */
+#define RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_na (_RAC_PATRIM2_TXPATRIM10DBMDUTYCYP_na << 12) /**< Shifted mode na for RAC_PATRIM2 */
+
+/* Bit fields for RAC PATRIM3 */
+#define _RAC_PATRIM3_RESETVALUE 0x008D33AAUL /**< Default value for RAC_PATRIM3 */
+#define _RAC_PATRIM3_MASK 0x00FF73FEUL /**< Mask for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMBLEEDAUTOREG (0x1UL << 1) /**< TXPATRIMBLEEDAUTOREG */
+#define _RAC_PATRIM3_TXPATRIMBLEEDAUTOREG_SHIFT 1 /**< Shift value for RAC_TXPATRIMBLEEDAUTOREG */
+#define _RAC_PATRIM3_TXPATRIMBLEEDAUTOREG_MASK 0x2UL /**< Bit mask for RAC_TXPATRIMBLEEDAUTOREG */
+#define _RAC_PATRIM3_TXPATRIMBLEEDAUTOREG_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMBLEEDAUTOREG_not_automatic 0x00000000UL /**< Mode not_automatic for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMBLEEDAUTOREG_automatic 0x00000001UL /**< Mode automatic for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMBLEEDAUTOREG_DEFAULT (_RAC_PATRIM3_TXPATRIMBLEEDAUTOREG_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMBLEEDAUTOREG_not_automatic (_RAC_PATRIM3_TXPATRIMBLEEDAUTOREG_not_automatic << 1) /**< Shifted mode not_automatic for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMBLEEDAUTOREG_automatic (_RAC_PATRIM3_TXPATRIMBLEEDAUTOREG_automatic << 1) /**< Shifted mode automatic for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMIBIASMASTER_SHIFT 2 /**< Shift value for RAC_TXPATRIMIBIASMASTER */
+#define _RAC_PATRIM3_TXPATRIMIBIASMASTER_MASK 0xCUL /**< Bit mask for RAC_TXPATRIMIBIASMASTER */
+#define _RAC_PATRIM3_TXPATRIMIBIASMASTER_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMIBIASMASTER_Ibias_is_45u 0x00000000UL /**< Mode Ibias_is_45u for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMIBIASMASTER_Ibias_is_47p5u 0x00000001UL /**< Mode Ibias_is_47p5u for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMIBIASMASTER_Ibias_is_50u 0x00000002UL /**< Mode Ibias_is_50u for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMIBIASMASTER_Ibias_is_52p5u 0x00000003UL /**< Mode Ibias_is_52p5u for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMIBIASMASTER_DEFAULT (_RAC_PATRIM3_TXPATRIMIBIASMASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMIBIASMASTER_Ibias_is_45u (_RAC_PATRIM3_TXPATRIMIBIASMASTER_Ibias_is_45u << 2) /**< Shifted mode Ibias_is_45u for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMIBIASMASTER_Ibias_is_47p5u (_RAC_PATRIM3_TXPATRIMIBIASMASTER_Ibias_is_47p5u << 2) /**< Shifted mode Ibias_is_47p5u for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMIBIASMASTER_Ibias_is_50u (_RAC_PATRIM3_TXPATRIMIBIASMASTER_Ibias_is_50u << 2) /**< Shifted mode Ibias_is_50u for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMIBIASMASTER_Ibias_is_52p5u (_RAC_PATRIM3_TXPATRIMIBIASMASTER_Ibias_is_52p5u << 2) /**< Shifted mode Ibias_is_52p5u for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGFB_SHIFT 4 /**< Shift value for RAC_TXPATRIMPREDRVREGFB */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGFB_MASK 0x30UL /**< Bit mask for RAC_TXPATRIMPREDRVREGFB */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGFB_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGFB_vreg_1p22 0x00000000UL /**< Mode vreg_1p22 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGFB_vreg_1p28 0x00000001UL /**< Mode vreg_1p28 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGFB_vreg_1p35 0x00000002UL /**< Mode vreg_1p35 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGFB_vreg_1p44 0x00000003UL /**< Mode vreg_1p44 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMPREDRVREGFB_DEFAULT (_RAC_PATRIM3_TXPATRIMPREDRVREGFB_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMPREDRVREGFB_vreg_1p22 (_RAC_PATRIM3_TXPATRIMPREDRVREGFB_vreg_1p22 << 4) /**< Shifted mode vreg_1p22 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMPREDRVREGFB_vreg_1p28 (_RAC_PATRIM3_TXPATRIMPREDRVREGFB_vreg_1p28 << 4) /**< Shifted mode vreg_1p28 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMPREDRVREGFB_vreg_1p35 (_RAC_PATRIM3_TXPATRIMPREDRVREGFB_vreg_1p35 << 4) /**< Shifted mode vreg_1p35 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMPREDRVREGFB_vreg_1p44 (_RAC_PATRIM3_TXPATRIMPREDRVREGFB_vreg_1p44 << 4) /**< Shifted mode vreg_1p44 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMPREDRVREGFBKATT (0x1UL << 6) /**< TXPATRIMPREDRVREGFBKATT */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGFBKATT_SHIFT 6 /**< Shift value for RAC_TXPATRIMPREDRVREGFBKATT */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGFBKATT_MASK 0x40UL /**< Bit mask for RAC_TXPATRIMPREDRVREGFBKATT */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGFBKATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGFBKATT_less_bw 0x00000000UL /**< Mode less_bw for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGFBKATT_more_bw 0x00000001UL /**< Mode more_bw for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMPREDRVREGFBKATT_DEFAULT (_RAC_PATRIM3_TXPATRIMPREDRVREGFBKATT_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMPREDRVREGFBKATT_less_bw (_RAC_PATRIM3_TXPATRIMPREDRVREGFBKATT_less_bw << 6) /**< Shifted mode less_bw for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMPREDRVREGFBKATT_more_bw (_RAC_PATRIM3_TXPATRIMPREDRVREGFBKATT_more_bw << 6) /**< Shifted mode more_bw for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMPREDRVREGPSR (0x1UL << 7) /**< TXPATRIMPREDRVREGPSR */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGPSR_SHIFT 7 /**< Shift value for RAC_TXPATRIMPREDRVREGPSR */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGPSR_MASK 0x80UL /**< Bit mask for RAC_TXPATRIMPREDRVREGPSR */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGPSR_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGPSR_low_psr 0x00000000UL /**< Mode low_psr for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGPSR_high_psr 0x00000001UL /**< Mode high_psr for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMPREDRVREGPSR_DEFAULT (_RAC_PATRIM3_TXPATRIMPREDRVREGPSR_DEFAULT << 7) /**< Shifted mode DEFAULT for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMPREDRVREGPSR_low_psr (_RAC_PATRIM3_TXPATRIMPREDRVREGPSR_low_psr << 7) /**< Shifted mode low_psr for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMPREDRVREGPSR_high_psr (_RAC_PATRIM3_TXPATRIMPREDRVREGPSR_high_psr << 7) /**< Shifted mode high_psr for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_SHIFT 8 /**< Shift value for RAC_TXPATRIMPREDRVREGSLICES */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_MASK 0x300UL /**< Bit mask for RAC_TXPATRIMPREDRVREGSLICES */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_DEFAULT 0x00000003UL /**< Mode DEFAULT for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_iload_7p5mA 0x00000000UL /**< Mode iload_7p5mA for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_iload_15mA 0x00000001UL /**< Mode iload_15mA for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_iload_22p5mA 0x00000002UL /**< Mode iload_22p5mA for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_iload_30mA 0x00000003UL /**< Mode iload_30mA for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_DEFAULT (_RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_iload_7p5mA (_RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_iload_7p5mA << 8) /**< Shifted mode iload_7p5mA for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_iload_15mA (_RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_iload_15mA << 8) /**< Shifted mode iload_15mA for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_iload_22p5mA (_RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_iload_22p5mA << 8) /**< Shifted mode iload_22p5mA for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_iload_30mA (_RAC_PATRIM3_TXPATRIMPREDRVREGSLICES_iload_30mA << 8) /**< Shifted mode iload_30mA for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGVREF_SHIFT 12 /**< Shift value for RAC_TXPATRIMPREDRVREGVREF */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGVREF_MASK 0x7000UL /**< Bit mask for RAC_TXPATRIMPREDRVREGVREF */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGVREF_DEFAULT 0x00000003UL /**< Mode DEFAULT for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p675 0x00000000UL /**< Mode vref_0p675 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p700 0x00000001UL /**< Mode vref_0p700 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p725 0x00000002UL /**< Mode vref_0p725 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p750 0x00000003UL /**< Mode vref_0p750 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p775 0x00000004UL /**< Mode vref_0p775 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p800 0x00000005UL /**< Mode vref_0p800 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p825 0x00000006UL /**< Mode vref_0p825 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p850 0x00000007UL /**< Mode vref_0p850 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMPREDRVREGVREF_DEFAULT (_RAC_PATRIM3_TXPATRIMPREDRVREGVREF_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p675 (_RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p675 << 12) /**< Shifted mode vref_0p675 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p700 (_RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p700 << 12) /**< Shifted mode vref_0p700 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p725 (_RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p725 << 12) /**< Shifted mode vref_0p725 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p750 (_RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p750 << 12) /**< Shifted mode vref_0p750 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p775 (_RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p775 << 12) /**< Shifted mode vref_0p775 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p800 (_RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p800 << 12) /**< Shifted mode vref_0p800 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p825 (_RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p825 << 12) /**< Shifted mode vref_0p825 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p850 (_RAC_PATRIM3_TXPATRIMPREDRVREGVREF_vref_0p850 << 12) /**< Shifted mode vref_0p850 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMREGFB_SHIFT 16 /**< Shift value for RAC_TXPATRIMREGFB */
+#define _RAC_PATRIM3_TXPATRIMREGFB_MASK 0x70000UL /**< Bit mask for RAC_TXPATRIMREGFB */
+#define _RAC_PATRIM3_TXPATRIMREGFB_DEFAULT 0x00000005UL /**< Mode DEFAULT for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMREGFB_vreg_1p678 0x00000000UL /**< Mode vreg_1p678 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMREGFB_vreg_1p735 0x00000001UL /**< Mode vreg_1p735 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMREGFB_vreg_1p801 0x00000002UL /**< Mode vreg_1p801 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMREGFB_vreg_1p875 0x00000003UL /**< Mode vreg_1p875 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMREGFB_vreg_3p00 0x00000004UL /**< Mode vreg_3p00 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMREGFB_vreg_3p14 0x00000005UL /**< Mode vreg_3p14 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMREGFB_vreg_3p3 0x00000006UL /**< Mode vreg_3p3 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMREGFB_vreg_3p477 0x00000007UL /**< Mode vreg_3p477 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMREGFB_DEFAULT (_RAC_PATRIM3_TXPATRIMREGFB_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMREGFB_vreg_1p678 (_RAC_PATRIM3_TXPATRIMREGFB_vreg_1p678 << 16) /**< Shifted mode vreg_1p678 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMREGFB_vreg_1p735 (_RAC_PATRIM3_TXPATRIMREGFB_vreg_1p735 << 16) /**< Shifted mode vreg_1p735 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMREGFB_vreg_1p801 (_RAC_PATRIM3_TXPATRIMREGFB_vreg_1p801 << 16) /**< Shifted mode vreg_1p801 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMREGFB_vreg_1p875 (_RAC_PATRIM3_TXPATRIMREGFB_vreg_1p875 << 16) /**< Shifted mode vreg_1p875 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMREGFB_vreg_3p00 (_RAC_PATRIM3_TXPATRIMREGFB_vreg_3p00 << 16) /**< Shifted mode vreg_3p00 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMREGFB_vreg_3p14 (_RAC_PATRIM3_TXPATRIMREGFB_vreg_3p14 << 16) /**< Shifted mode vreg_3p14 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMREGFB_vreg_3p3 (_RAC_PATRIM3_TXPATRIMREGFB_vreg_3p3 << 16) /**< Shifted mode vreg_3p3 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMREGFB_vreg_3p477 (_RAC_PATRIM3_TXPATRIMREGFB_vreg_3p477 << 16) /**< Shifted mode vreg_3p477 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMREGPSR (0x1UL << 19) /**< TXPATRIMREGPSR */
+#define _RAC_PATRIM3_TXPATRIMREGPSR_SHIFT 19 /**< Shift value for RAC_TXPATRIMREGPSR */
+#define _RAC_PATRIM3_TXPATRIMREGPSR_MASK 0x80000UL /**< Bit mask for RAC_TXPATRIMREGPSR */
+#define _RAC_PATRIM3_TXPATRIMREGPSR_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMREGPSR_low_psr 0x00000000UL /**< Mode low_psr for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMREGPSR_high_psr 0x00000001UL /**< Mode high_psr for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMREGPSR_DEFAULT (_RAC_PATRIM3_TXPATRIMREGPSR_DEFAULT << 19) /**< Shifted mode DEFAULT for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMREGPSR_low_psr (_RAC_PATRIM3_TXPATRIMREGPSR_low_psr << 19) /**< Shifted mode low_psr for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMREGPSR_high_psr (_RAC_PATRIM3_TXPATRIMREGPSR_high_psr << 19) /**< Shifted mode high_psr for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMREGVREF_SHIFT 20 /**< Shift value for RAC_TXPATRIMREGVREF */
+#define _RAC_PATRIM3_TXPATRIMREGVREF_MASK 0xF00000UL /**< Bit mask for RAC_TXPATRIMREGVREF */
+#define _RAC_PATRIM3_TXPATRIMREGVREF_DEFAULT 0x00000008UL /**< Mode DEFAULT for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p651 0x00000000UL /**< Mode vref_0p651 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p663 0x00000001UL /**< Mode vref_0p663 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p676 0x00000002UL /**< Mode vref_0p676 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p688 0x00000003UL /**< Mode vref_0p688 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p701 0x00000004UL /**< Mode vref_0p701 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p713 0x00000005UL /**< Mode vref_0p713 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p726 0x00000006UL /**< Mode vref_0p726 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p738 0x00000007UL /**< Mode vref_0p738 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p751 0x00000008UL /**< Mode vref_0p751 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p763 0x00000009UL /**< Mode vref_0p763 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p776 0x0000000AUL /**< Mode vref_0p776 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p788 0x0000000BUL /**< Mode vref_0p788 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p801 0x0000000CUL /**< Mode vref_0p801 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p813 0x0000000DUL /**< Mode vref_0p813 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p826 0x0000000EUL /**< Mode vref_0p826 for RAC_PATRIM3 */
+#define _RAC_PATRIM3_TXPATRIMREGVREF_vref_0p838 0x0000000FUL /**< Mode vref_0p838 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMREGVREF_DEFAULT (_RAC_PATRIM3_TXPATRIMREGVREF_DEFAULT << 20) /**< Shifted mode DEFAULT for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p651 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p651 << 20) /**< Shifted mode vref_0p651 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p663 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p663 << 20) /**< Shifted mode vref_0p663 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p676 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p676 << 20) /**< Shifted mode vref_0p676 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p688 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p688 << 20) /**< Shifted mode vref_0p688 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p701 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p701 << 20) /**< Shifted mode vref_0p701 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p713 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p713 << 20) /**< Shifted mode vref_0p713 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p726 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p726 << 20) /**< Shifted mode vref_0p726 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p738 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p738 << 20) /**< Shifted mode vref_0p738 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p751 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p751 << 20) /**< Shifted mode vref_0p751 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p763 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p763 << 20) /**< Shifted mode vref_0p763 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p776 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p776 << 20) /**< Shifted mode vref_0p776 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p788 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p788 << 20) /**< Shifted mode vref_0p788 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p801 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p801 << 20) /**< Shifted mode vref_0p801 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p813 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p813 << 20) /**< Shifted mode vref_0p813 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p826 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p826 << 20) /**< Shifted mode vref_0p826 for RAC_PATRIM3 */
+#define RAC_PATRIM3_TXPATRIMREGVREF_vref_0p838 (_RAC_PATRIM3_TXPATRIMREGVREF_vref_0p838 << 20) /**< Shifted mode vref_0p838 for RAC_PATRIM3 */
+
+/* Bit fields for RAC PATRIM4 */
+#define _RAC_PATRIM4_RESETVALUE 0x00006000UL /**< Default value for RAC_PATRIM4 */
+#define _RAC_PATRIM4_MASK 0x03FFFFFFUL /**< Mask for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM10DBMCTAP_SHIFT 0 /**< Shift value for RAC_TXPATRIM10DBMCTAP */
+#define _RAC_PATRIM4_TXPATRIM10DBMCTAP_MASK 0xFUL /**< Bit mask for RAC_TXPATRIM10DBMCTAP */
+#define _RAC_PATRIM4_TXPATRIM10DBMCTAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_0 0x00000000UL /**< Mode ctap_trim_0 for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_1 0x00000001UL /**< Mode ctap_trim_1 for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_2 0x00000002UL /**< Mode ctap_trim_2 for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_3 0x00000003UL /**< Mode ctap_trim_3 for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_4 0x00000004UL /**< Mode ctap_trim_4 for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_5 0x00000005UL /**< Mode ctap_trim_5 for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_6 0x00000006UL /**< Mode ctap_trim_6 for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_7 0x00000007UL /**< Mode ctap_trim_7 for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_8 0x00000008UL /**< Mode ctap_trim_8 for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM10DBMCTAP_DEFAULT (_RAC_PATRIM4_TXPATRIM10DBMCTAP_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_0 (_RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_0 << 0) /**< Shifted mode ctap_trim_0 for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_1 (_RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_1 << 0) /**< Shifted mode ctap_trim_1 for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_2 (_RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_2 << 0) /**< Shifted mode ctap_trim_2 for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_3 (_RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_3 << 0) /**< Shifted mode ctap_trim_3 for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_4 (_RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_4 << 0) /**< Shifted mode ctap_trim_4 for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_5 (_RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_5 << 0) /**< Shifted mode ctap_trim_5 for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_6 (_RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_6 << 0) /**< Shifted mode ctap_trim_6 for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_7 (_RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_7 << 0) /**< Shifted mode ctap_trim_7 for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_8 (_RAC_PATRIM4_TXPATRIM10DBMCTAP_ctap_trim_8 << 0) /**< Shifted mode ctap_trim_8 for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_SHIFT 4 /**< Shift value for RAC_TXPATRIM10DBMPREDRVCAP */
+#define _RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_MASK 0x30UL /**< Bit mask for RAC_TXPATRIM10DBMPREDRVCAP */
+#define _RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_cap_0 0x00000000UL /**< Mode cap_0 for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_cap_1 0x00000001UL /**< Mode cap_1 for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_cap_2 0x00000002UL /**< Mode cap_2 for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_cap_3 0x00000003UL /**< Mode cap_3 for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_DEFAULT (_RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_cap_0 (_RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_cap_0 << 4) /**< Shifted mode cap_0 for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_cap_1 (_RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_cap_1 << 4) /**< Shifted mode cap_1 for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_cap_2 (_RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_cap_2 << 4) /**< Shifted mode cap_2 for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_cap_3 (_RAC_PATRIM4_TXPATRIM10DBMPREDRVCAP_cap_3 << 4) /**< Shifted mode cap_3 for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_SHIFT 6 /**< Shift value for RAC_TXPATRIM10DBMPREDRVSLC */
+#define _RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_MASK 0xC0UL /**< Bit mask for RAC_TXPATRIM10DBMPREDRVSLC */
+#define _RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_slc_0 0x00000000UL /**< Mode slc_0 for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_slc_1 0x00000001UL /**< Mode slc_1 for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_slc_2 0x00000002UL /**< Mode slc_2 for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_slc_3 0x00000003UL /**< Mode slc_3 for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_DEFAULT (_RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_slc_0 (_RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_slc_0 << 6) /**< Shifted mode slc_0 for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_slc_1 (_RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_slc_1 << 6) /**< Shifted mode slc_1 for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_slc_2 (_RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_slc_2 << 6) /**< Shifted mode slc_2 for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_slc_3 (_RAC_PATRIM4_TXPATRIM10DBMPREDRVSLC_slc_3 << 6) /**< Shifted mode slc_3 for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM20DBMCTAP_SHIFT 8 /**< Shift value for RAC_TXPATRIM20DBMCTAP */
+#define _RAC_PATRIM4_TXPATRIM20DBMCTAP_MASK 0xF00UL /**< Bit mask for RAC_TXPATRIM20DBMCTAP */
+#define _RAC_PATRIM4_TXPATRIM20DBMCTAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_0 0x00000000UL /**< Mode ctap_trim_0 for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_1 0x00000001UL /**< Mode ctap_trim_1 for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_2 0x00000002UL /**< Mode ctap_trim_2 for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_3 0x00000003UL /**< Mode ctap_trim_3 for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_4 0x00000004UL /**< Mode ctap_trim_4 for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_5 0x00000005UL /**< Mode ctap_trim_5 for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_6 0x00000006UL /**< Mode ctap_trim_6 for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_7 0x00000007UL /**< Mode ctap_trim_7 for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_8 0x00000008UL /**< Mode ctap_trim_8 for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM20DBMCTAP_DEFAULT (_RAC_PATRIM4_TXPATRIM20DBMCTAP_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_0 (_RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_0 << 8) /**< Shifted mode ctap_trim_0 for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_1 (_RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_1 << 8) /**< Shifted mode ctap_trim_1 for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_2 (_RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_2 << 8) /**< Shifted mode ctap_trim_2 for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_3 (_RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_3 << 8) /**< Shifted mode ctap_trim_3 for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_4 (_RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_4 << 8) /**< Shifted mode ctap_trim_4 for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_5 (_RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_5 << 8) /**< Shifted mode ctap_trim_5 for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_6 (_RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_6 << 8) /**< Shifted mode ctap_trim_6 for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_7 (_RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_7 << 8) /**< Shifted mode ctap_trim_7 for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_8 (_RAC_PATRIM4_TXPATRIM20DBMCTAP_ctap_trim_8 << 8) /**< Shifted mode ctap_trim_8 for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM20DBMPREDRV_SHIFT 12 /**< Shift value for RAC_TXPATRIM20DBMPREDRV */
+#define _RAC_PATRIM4_TXPATRIM20DBMPREDRV_MASK 0xF000UL /**< Bit mask for RAC_TXPATRIM20DBMPREDRV */
+#define _RAC_PATRIM4_TXPATRIM20DBMPREDRV_DEFAULT 0x00000006UL /**< Mode DEFAULT for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_137ps 0x00000000UL /**< Mode trise_137ps for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_127ps 0x00000001UL /**< Mode trise_127ps for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_117ps 0x00000002UL /**< Mode trise_117ps for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_110ps 0x00000003UL /**< Mode trise_110ps for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_75ps 0x00000004UL /**< Mode trise_75ps for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_73ps 0x00000005UL /**< Mode trise_73ps for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_71ps 0x00000006UL /**< Mode trise_71ps for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_70ps 0x00000007UL /**< Mode trise_70ps for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM20DBMPREDRV_DEFAULT (_RAC_PATRIM4_TXPATRIM20DBMPREDRV_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_137ps (_RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_137ps << 12) /**< Shifted mode trise_137ps for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_127ps (_RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_127ps << 12) /**< Shifted mode trise_127ps for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_117ps (_RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_117ps << 12) /**< Shifted mode trise_117ps for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_110ps (_RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_110ps << 12) /**< Shifted mode trise_110ps for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_75ps (_RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_75ps << 12) /**< Shifted mode trise_75ps for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_73ps (_RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_73ps << 12) /**< Shifted mode trise_73ps for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_71ps (_RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_71ps << 12) /**< Shifted mode trise_71ps for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_70ps (_RAC_PATRIM4_TXPATRIM20DBMPREDRV_trise_70ps << 12) /**< Shifted mode trise_70ps for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIMCAPPAOUTM_SHIFT 16 /**< Shift value for RAC_TXPATRIMCAPPAOUTM */
+#define _RAC_PATRIM4_TXPATRIMCAPPAOUTM_MASK 0xF0000UL /**< Bit mask for RAC_TXPATRIMCAPPAOUTM */
+#define _RAC_PATRIM4_TXPATRIMCAPPAOUTM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIMCAPPAOUTM_DEFAULT (_RAC_PATRIM4_TXPATRIMCAPPAOUTM_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIMCAPPAOUTP_SHIFT 20 /**< Shift value for RAC_TXPATRIMCAPPAOUTP */
+#define _RAC_PATRIM4_TXPATRIMCAPPAOUTP_MASK 0xF00000UL /**< Bit mask for RAC_TXPATRIMCAPPAOUTP */
+#define _RAC_PATRIM4_TXPATRIMCAPPAOUTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIMCAPPAOUTP_DEFAULT (_RAC_PATRIM4_TXPATRIMCAPPAOUTP_DEFAULT << 20) /**< Shifted mode DEFAULT for RAC_PATRIM4 */
+#define _RAC_PATRIM4_TXPATRIMCMGAIN_SHIFT 24 /**< Shift value for RAC_TXPATRIMCMGAIN */
+#define _RAC_PATRIM4_TXPATRIMCMGAIN_MASK 0x3000000UL /**< Bit mask for RAC_TXPATRIMCMGAIN */
+#define _RAC_PATRIM4_TXPATRIMCMGAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM4 */
+#define RAC_PATRIM4_TXPATRIMCMGAIN_DEFAULT (_RAC_PATRIM4_TXPATRIMCMGAIN_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_PATRIM4 */
+
+/* Bit fields for RAC PATRIM5 */
+#define _RAC_PATRIM5_RESETVALUE 0x00181800UL /**< Default value for RAC_PATRIM5 */
+#define _RAC_PATRIM5_MASK 0x033F3F7FUL /**< Mask for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMDACGLITCH (0x1UL << 0) /**< TXPATRIMDACGLITCH */
+#define _RAC_PATRIM5_TXPATRIMDACGLITCH_SHIFT 0 /**< Shift value for RAC_TXPATRIMDACGLITCH */
+#define _RAC_PATRIM5_TXPATRIMDACGLITCH_MASK 0x1UL /**< Bit mask for RAC_TXPATRIMDACGLITCH */
+#define _RAC_PATRIM5_TXPATRIMDACGLITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMDACGLITCH_larger_glitch 0x00000000UL /**< Mode larger_glitch for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMDACGLITCH_smaller_glitch 0x00000001UL /**< Mode smaller_glitch for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMDACGLITCH_DEFAULT (_RAC_PATRIM5_TXPATRIMDACGLITCH_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMDACGLITCH_larger_glitch (_RAC_PATRIM5_TXPATRIMDACGLITCH_larger_glitch << 0) /**< Shifted mode larger_glitch for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMDACGLITCH_smaller_glitch (_RAC_PATRIM5_TXPATRIMDACGLITCH_smaller_glitch << 0) /**< Shifted mode smaller_glitch for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMDLY0_SHIFT 1 /**< Shift value for RAC_TXPATRIMDLY0 */
+#define _RAC_PATRIM5_TXPATRIMDLY0_MASK 0xEUL /**< Bit mask for RAC_TXPATRIMDLY0 */
+#define _RAC_PATRIM5_TXPATRIMDLY0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMDLY0_tdly_0ps 0x00000000UL /**< Mode tdly_0ps for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMDLY0_tdly_64ps 0x00000001UL /**< Mode tdly_64ps for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMDLY0_tdly_65ps 0x00000002UL /**< Mode tdly_65ps for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMDLY0_tdly_66ps 0x00000003UL /**< Mode tdly_66ps for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMDLY0_tdly_68ps 0x00000004UL /**< Mode tdly_68ps for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMDLY0_tdly_70ps 0x00000005UL /**< Mode tdly_70ps for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMDLY0_tdly_75ps 0x00000006UL /**< Mode tdly_75ps for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMDLY0_tdly_83ps 0x00000007UL /**< Mode tdly_83ps for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMDLY0_DEFAULT (_RAC_PATRIM5_TXPATRIMDLY0_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMDLY0_tdly_0ps (_RAC_PATRIM5_TXPATRIMDLY0_tdly_0ps << 1) /**< Shifted mode tdly_0ps for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMDLY0_tdly_64ps (_RAC_PATRIM5_TXPATRIMDLY0_tdly_64ps << 1) /**< Shifted mode tdly_64ps for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMDLY0_tdly_65ps (_RAC_PATRIM5_TXPATRIMDLY0_tdly_65ps << 1) /**< Shifted mode tdly_65ps for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMDLY0_tdly_66ps (_RAC_PATRIM5_TXPATRIMDLY0_tdly_66ps << 1) /**< Shifted mode tdly_66ps for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMDLY0_tdly_68ps (_RAC_PATRIM5_TXPATRIMDLY0_tdly_68ps << 1) /**< Shifted mode tdly_68ps for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMDLY0_tdly_70ps (_RAC_PATRIM5_TXPATRIMDLY0_tdly_70ps << 1) /**< Shifted mode tdly_70ps for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMDLY0_tdly_75ps (_RAC_PATRIM5_TXPATRIMDLY0_tdly_75ps << 1) /**< Shifted mode tdly_75ps for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMDLY0_tdly_83ps (_RAC_PATRIM5_TXPATRIMDLY0_tdly_83ps << 1) /**< Shifted mode tdly_83ps for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMDLY1_SHIFT 4 /**< Shift value for RAC_TXPATRIMDLY1 */
+#define _RAC_PATRIM5_TXPATRIMDLY1_MASK 0x70UL /**< Bit mask for RAC_TXPATRIMDLY1 */
+#define _RAC_PATRIM5_TXPATRIMDLY1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMDLY1_tdly_0ps 0x00000000UL /**< Mode tdly_0ps for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMDLY1_tdly_64ps 0x00000001UL /**< Mode tdly_64ps for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMDLY1_tdly_65ps 0x00000002UL /**< Mode tdly_65ps for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMDLY1_tdly_66ps 0x00000003UL /**< Mode tdly_66ps for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMDLY1_tdly_68ps 0x00000004UL /**< Mode tdly_68ps for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMDLY1_tdly_70ps 0x00000005UL /**< Mode tdly_70ps for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMDLY1_tdly_75ps 0x00000006UL /**< Mode tdly_75ps for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMDLY1_tdly_83ps 0x00000007UL /**< Mode tdly_83ps for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMDLY1_DEFAULT (_RAC_PATRIM5_TXPATRIMDLY1_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMDLY1_tdly_0ps (_RAC_PATRIM5_TXPATRIMDLY1_tdly_0ps << 4) /**< Shifted mode tdly_0ps for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMDLY1_tdly_64ps (_RAC_PATRIM5_TXPATRIMDLY1_tdly_64ps << 4) /**< Shifted mode tdly_64ps for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMDLY1_tdly_65ps (_RAC_PATRIM5_TXPATRIMDLY1_tdly_65ps << 4) /**< Shifted mode tdly_65ps for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMDLY1_tdly_66ps (_RAC_PATRIM5_TXPATRIMDLY1_tdly_66ps << 4) /**< Shifted mode tdly_66ps for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMDLY1_tdly_68ps (_RAC_PATRIM5_TXPATRIMDLY1_tdly_68ps << 4) /**< Shifted mode tdly_68ps for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMDLY1_tdly_70ps (_RAC_PATRIM5_TXPATRIMDLY1_tdly_70ps << 4) /**< Shifted mode tdly_70ps for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMDLY1_tdly_75ps (_RAC_PATRIM5_TXPATRIMDLY1_tdly_75ps << 4) /**< Shifted mode tdly_75ps for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMDLY1_tdly_83ps (_RAC_PATRIM5_TXPATRIMDLY1_tdly_83ps << 4) /**< Shifted mode tdly_83ps for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMNBIAS_SHIFT 8 /**< Shift value for RAC_TXPATRIMNBIAS */
+#define _RAC_PATRIM5_TXPATRIMNBIAS_MASK 0xF00UL /**< Bit mask for RAC_TXPATRIMNBIAS */
+#define _RAC_PATRIM5_TXPATRIMNBIAS_DEFAULT 0x00000008UL /**< Mode DEFAULT for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn104mv 0x00000000UL /**< Mode vnbias_dn104mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn91mv 0x00000001UL /**< Mode vnbias_dn91mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn78mv 0x00000002UL /**< Mode vnbias_dn78mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn65mv 0x00000003UL /**< Mode vnbias_dn65mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn52mv 0x00000004UL /**< Mode vnbias_dn52mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn39mv 0x00000005UL /**< Mode vnbias_dn39mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn26mv 0x00000006UL /**< Mode vnbias_dn26mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn13mv 0x00000007UL /**< Mode vnbias_dn13mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_default 0x00000008UL /**< Mode vnbias_default for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up13mv 0x00000009UL /**< Mode vnbias_up13mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up26mv 0x0000000AUL /**< Mode vnbias_up26mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up39mv 0x0000000BUL /**< Mode vnbias_up39mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up52mv 0x0000000CUL /**< Mode vnbias_up52mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up65mv 0x0000000DUL /**< Mode vnbias_up65mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up78mv 0x0000000EUL /**< Mode vnbias_up78mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up91mv 0x0000000FUL /**< Mode vnbias_up91mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMNBIAS_DEFAULT (_RAC_PATRIM5_TXPATRIMNBIAS_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn104mv (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn104mv << 8) /**< Shifted mode vnbias_dn104mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn91mv (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn91mv << 8) /**< Shifted mode vnbias_dn91mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn78mv (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn78mv << 8) /**< Shifted mode vnbias_dn78mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn65mv (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn65mv << 8) /**< Shifted mode vnbias_dn65mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn52mv (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn52mv << 8) /**< Shifted mode vnbias_dn52mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn39mv (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn39mv << 8) /**< Shifted mode vnbias_dn39mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn26mv (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn26mv << 8) /**< Shifted mode vnbias_dn26mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn13mv (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_dn13mv << 8) /**< Shifted mode vnbias_dn13mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_default (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_default << 8) /**< Shifted mode vnbias_default for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up13mv (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up13mv << 8) /**< Shifted mode vnbias_up13mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up26mv (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up26mv << 8) /**< Shifted mode vnbias_up26mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up39mv (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up39mv << 8) /**< Shifted mode vnbias_up39mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up52mv (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up52mv << 8) /**< Shifted mode vnbias_up52mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up65mv (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up65mv << 8) /**< Shifted mode vnbias_up65mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up78mv (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up78mv << 8) /**< Shifted mode vnbias_up78mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up91mv (_RAC_PATRIM5_TXPATRIMNBIAS_vnbias_up91mv << 8) /**< Shifted mode vnbias_up91mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMNCASC_SHIFT 12 /**< Shift value for RAC_TXPATRIMNCASC */
+#define _RAC_PATRIM5_TXPATRIMNCASC_MASK 0x3000UL /**< Bit mask for RAC_TXPATRIMNCASC */
+#define _RAC_PATRIM5_TXPATRIMNCASC_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMNCASC_ncbias_m50mv 0x00000000UL /**< Mode ncbias_m50mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMNCASC_ncbiasdefault 0x00000001UL /**< Mode ncbiasdefault for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMNCASC_ncbias_p50mv 0x00000002UL /**< Mode ncbias_p50mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMNCASC_ncbias_p100mv 0x00000003UL /**< Mode ncbias_p100mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMNCASC_DEFAULT (_RAC_PATRIM5_TXPATRIMNCASC_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMNCASC_ncbias_m50mv (_RAC_PATRIM5_TXPATRIMNCASC_ncbias_m50mv << 12) /**< Shifted mode ncbias_m50mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMNCASC_ncbiasdefault (_RAC_PATRIM5_TXPATRIMNCASC_ncbiasdefault << 12) /**< Shifted mode ncbiasdefault for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMNCASC_ncbias_p50mv (_RAC_PATRIM5_TXPATRIMNCASC_ncbias_p50mv << 12) /**< Shifted mode ncbias_p50mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMNCASC_ncbias_p100mv (_RAC_PATRIM5_TXPATRIMNCASC_ncbias_p100mv << 12) /**< Shifted mode ncbias_p100mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMPBIAS_SHIFT 16 /**< Shift value for RAC_TXPATRIMPBIAS */
+#define _RAC_PATRIM5_TXPATRIMPBIAS_MASK 0xF0000UL /**< Bit mask for RAC_TXPATRIMPBIAS */
+#define _RAC_PATRIM5_TXPATRIMPBIAS_DEFAULT 0x00000008UL /**< Mode DEFAULT for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up104mv 0x00000000UL /**< Mode vpbias_up104mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up91mv 0x00000001UL /**< Mode vpbias_up91mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up78mv 0x00000002UL /**< Mode vpbias_up78mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up65mv 0x00000003UL /**< Mode vpbias_up65mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up52mv 0x00000004UL /**< Mode vpbias_up52mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up39mv 0x00000005UL /**< Mode vpbias_up39mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up26mv 0x00000006UL /**< Mode vpbias_up26mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up13mv 0x00000007UL /**< Mode vpbias_up13mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_default 0x00000008UL /**< Mode vpbias_default for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn13mv 0x00000009UL /**< Mode vpbias_dn13mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn26mv 0x0000000AUL /**< Mode vpbias_dn26mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn38mv 0x0000000BUL /**< Mode vpbias_dn38mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn52mv 0x0000000CUL /**< Mode vpbias_dn52mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn65mv 0x0000000DUL /**< Mode vpbias_dn65mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn78mv 0x0000000EUL /**< Mode vpbias_dn78mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn91mv 0x0000000FUL /**< Mode vpbias_dn91mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMPBIAS_DEFAULT (_RAC_PATRIM5_TXPATRIMPBIAS_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up104mv (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up104mv << 16) /**< Shifted mode vpbias_up104mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up91mv (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up91mv << 16) /**< Shifted mode vpbias_up91mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up78mv (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up78mv << 16) /**< Shifted mode vpbias_up78mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up65mv (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up65mv << 16) /**< Shifted mode vpbias_up65mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up52mv (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up52mv << 16) /**< Shifted mode vpbias_up52mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up39mv (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up39mv << 16) /**< Shifted mode vpbias_up39mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up26mv (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up26mv << 16) /**< Shifted mode vpbias_up26mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up13mv (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_up13mv << 16) /**< Shifted mode vpbias_up13mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_default (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_default << 16) /**< Shifted mode vpbias_default for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn13mv (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn13mv << 16) /**< Shifted mode vpbias_dn13mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn26mv (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn26mv << 16) /**< Shifted mode vpbias_dn26mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn38mv (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn38mv << 16) /**< Shifted mode vpbias_dn38mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn52mv (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn52mv << 16) /**< Shifted mode vpbias_dn52mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn65mv (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn65mv << 16) /**< Shifted mode vpbias_dn65mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn78mv (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn78mv << 16) /**< Shifted mode vpbias_dn78mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn91mv (_RAC_PATRIM5_TXPATRIMPBIAS_vpbias_dn91mv << 16) /**< Shifted mode vpbias_dn91mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMPCASC_SHIFT 20 /**< Shift value for RAC_TXPATRIMPCASC */
+#define _RAC_PATRIM5_TXPATRIMPCASC_MASK 0x300000UL /**< Bit mask for RAC_TXPATRIMPCASC */
+#define _RAC_PATRIM5_TXPATRIMPCASC_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMPCASC_pcbias_n50mv 0x00000000UL /**< Mode pcbias_n50mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMPCASC_pcbias_default 0x00000001UL /**< Mode pcbias_default for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMPCASC_pcbias_m50mv 0x00000002UL /**< Mode pcbias_m50mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMPCASC_pcbias_m100mv 0x00000003UL /**< Mode pcbias_m100mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMPCASC_DEFAULT (_RAC_PATRIM5_TXPATRIMPCASC_DEFAULT << 20) /**< Shifted mode DEFAULT for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMPCASC_pcbias_n50mv (_RAC_PATRIM5_TXPATRIMPCASC_pcbias_n50mv << 20) /**< Shifted mode pcbias_n50mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMPCASC_pcbias_default (_RAC_PATRIM5_TXPATRIMPCASC_pcbias_default << 20) /**< Shifted mode pcbias_default for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMPCASC_pcbias_m50mv (_RAC_PATRIM5_TXPATRIMPCASC_pcbias_m50mv << 20) /**< Shifted mode pcbias_m50mv for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMPCASC_pcbias_m100mv (_RAC_PATRIM5_TXPATRIMPCASC_pcbias_m100mv << 20) /**< Shifted mode pcbias_m100mv for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMREGSLICES_SHIFT 24 /**< Shift value for RAC_TXPATRIMREGSLICES */
+#define _RAC_PATRIM5_TXPATRIMREGSLICES_MASK 0x3000000UL /**< Bit mask for RAC_TXPATRIMREGSLICES */
+#define _RAC_PATRIM5_TXPATRIMREGSLICES_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMREGSLICES_spare1 0x00000000UL /**< Mode spare1 for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMREGSLICES_spare2 0x00000001UL /**< Mode spare2 for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMREGSLICES_spare3 0x00000002UL /**< Mode spare3 for RAC_PATRIM5 */
+#define _RAC_PATRIM5_TXPATRIMREGSLICES_spare4 0x00000003UL /**< Mode spare4 for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMREGSLICES_DEFAULT (_RAC_PATRIM5_TXPATRIMREGSLICES_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMREGSLICES_spare1 (_RAC_PATRIM5_TXPATRIMREGSLICES_spare1 << 24) /**< Shifted mode spare1 for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMREGSLICES_spare2 (_RAC_PATRIM5_TXPATRIMREGSLICES_spare2 << 24) /**< Shifted mode spare2 for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMREGSLICES_spare3 (_RAC_PATRIM5_TXPATRIMREGSLICES_spare3 << 24) /**< Shifted mode spare3 for RAC_PATRIM5 */
+#define RAC_PATRIM5_TXPATRIMREGSLICES_spare4 (_RAC_PATRIM5_TXPATRIMREGSLICES_spare4 << 24) /**< Shifted mode spare4 for RAC_PATRIM5 */
+
+/* Bit fields for RAC TXPOWER */
+#define _RAC_TXPOWER_RESETVALUE 0x00000010UL /**< Default value for RAC_TXPOWER */
+#define _RAC_TXPOWER_MASK 0x0000003FUL /**< Mask for RAC_TXPOWER */
+#define _RAC_TXPOWER_TX0DBMPOWER_SHIFT 0 /**< Shift value for RAC_TX0DBMPOWER */
+#define _RAC_TXPOWER_TX0DBMPOWER_MASK 0xFUL /**< Bit mask for RAC_TX0DBMPOWER */
+#define _RAC_TXPOWER_TX0DBMPOWER_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TXPOWER */
+#define _RAC_TXPOWER_TX0DBMPOWER_on_stripe_0 0x00000000UL /**< Mode on_stripe_0 for RAC_TXPOWER */
+#define _RAC_TXPOWER_TX0DBMPOWER_on_stripe_15 0x0000000FUL /**< Mode on_stripe_15 for RAC_TXPOWER */
+#define RAC_TXPOWER_TX0DBMPOWER_DEFAULT (_RAC_TXPOWER_TX0DBMPOWER_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_TXPOWER */
+#define RAC_TXPOWER_TX0DBMPOWER_on_stripe_0 (_RAC_TXPOWER_TX0DBMPOWER_on_stripe_0 << 0) /**< Shifted mode on_stripe_0 for RAC_TXPOWER */
+#define RAC_TXPOWER_TX0DBMPOWER_on_stripe_15 (_RAC_TXPOWER_TX0DBMPOWER_on_stripe_15 << 0) /**< Shifted mode on_stripe_15 for RAC_TXPOWER */
+#define _RAC_TXPOWER_TX0DBMSELSLICE_SHIFT 4 /**< Shift value for RAC_TX0DBMSELSLICE */
+#define _RAC_TXPOWER_TX0DBMSELSLICE_MASK 0x30UL /**< Bit mask for RAC_TX0DBMSELSLICE */
+#define _RAC_TXPOWER_TX0DBMSELSLICE_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_TXPOWER */
+#define _RAC_TXPOWER_TX0DBMSELSLICE_on_0_slice 0x00000000UL /**< Mode on_0_slice for RAC_TXPOWER */
+#define _RAC_TXPOWER_TX0DBMSELSLICE_on_1_slice 0x00000001UL /**< Mode on_1_slice for RAC_TXPOWER */
+#define _RAC_TXPOWER_TX0DBMSELSLICE_NA 0x00000002UL /**< Mode NA for RAC_TXPOWER */
+#define _RAC_TXPOWER_TX0DBMSELSLICE_on_1_slices 0x00000003UL /**< Mode on_1_slices for RAC_TXPOWER */
+#define RAC_TXPOWER_TX0DBMSELSLICE_DEFAULT (_RAC_TXPOWER_TX0DBMSELSLICE_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_TXPOWER */
+#define RAC_TXPOWER_TX0DBMSELSLICE_on_0_slice (_RAC_TXPOWER_TX0DBMSELSLICE_on_0_slice << 4) /**< Shifted mode on_0_slice for RAC_TXPOWER */
+#define RAC_TXPOWER_TX0DBMSELSLICE_on_1_slice (_RAC_TXPOWER_TX0DBMSELSLICE_on_1_slice << 4) /**< Shifted mode on_1_slice for RAC_TXPOWER */
+#define RAC_TXPOWER_TX0DBMSELSLICE_NA (_RAC_TXPOWER_TX0DBMSELSLICE_NA << 4) /**< Shifted mode NA for RAC_TXPOWER */
+#define RAC_TXPOWER_TX0DBMSELSLICE_on_1_slices (_RAC_TXPOWER_TX0DBMSELSLICE_on_1_slices << 4) /**< Shifted mode on_1_slices for RAC_TXPOWER */
+
+/* Bit fields for RAC TXRAMP */
+#define _RAC_TXRAMP_RESETVALUE 0x00000000UL /**< Default value for RAC_TXRAMP */
+#define _RAC_TXRAMP_MASK 0x00000001UL /**< Mask for RAC_TXRAMP */
+#define RAC_TXRAMP_PARAMPMODE (0x1UL << 0) /**< PARAMPMODE */
+#define _RAC_TXRAMP_PARAMPMODE_SHIFT 0 /**< Shift value for RAC_PARAMPMODE */
+#define _RAC_TXRAMP_PARAMPMODE_MASK 0x1UL /**< Bit mask for RAC_PARAMPMODE */
+#define _RAC_TXRAMP_PARAMPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TXRAMP */
+#define RAC_TXRAMP_PARAMPMODE_DEFAULT (_RAC_TXRAMP_PARAMPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_TXRAMP */
+
+/* Bit fields for RAC PGATRIM */
+#define _RAC_PGATRIM_RESETVALUE 0x00000B15UL /**< Default value for RAC_PGATRIM */
+#define _RAC_PGATRIM_MASK 0x00000FDFUL /**< Mask for RAC_PGATRIM */
+#define _RAC_PGATRIM_PGACTUNE_SHIFT 0 /**< Shift value for RAC_PGACTUNE */
+#define _RAC_PGATRIM_PGACTUNE_MASK 0x1FUL /**< Bit mask for RAC_PGACTUNE */
+#define _RAC_PGATRIM_PGACTUNE_DEFAULT 0x00000015UL /**< Mode DEFAULT for RAC_PGATRIM */
+#define RAC_PGATRIM_PGACTUNE_DEFAULT (_RAC_PGATRIM_PGACTUNE_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_PGATRIM */
+#define _RAC_PGATRIM_PGAVCMOUTTRIM_SHIFT 6 /**< Shift value for RAC_PGAVCMOUTTRIM */
+#define _RAC_PGATRIM_PGAVCMOUTTRIM_MASK 0x1C0UL /**< Bit mask for RAC_PGAVCMOUTTRIM */
+#define _RAC_PGATRIM_PGAVCMOUTTRIM_DEFAULT 0x00000004UL /**< Mode DEFAULT for RAC_PGATRIM */
+#define _RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_475 0x00000000UL /**< Mode vcm_out_475 for RAC_PGATRIM */
+#define _RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_500 0x00000001UL /**< Mode vcm_out_500 for RAC_PGATRIM */
+#define _RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_525 0x00000002UL /**< Mode vcm_out_525 for RAC_PGATRIM */
+#define _RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_550 0x00000003UL /**< Mode vcm_out_550 for RAC_PGATRIM */
+#define _RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_575 0x00000004UL /**< Mode vcm_out_575 for RAC_PGATRIM */
+#define _RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_600 0x00000005UL /**< Mode vcm_out_600 for RAC_PGATRIM */
+#define _RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_625 0x00000006UL /**< Mode vcm_out_625 for RAC_PGATRIM */
+#define _RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_650 0x00000007UL /**< Mode vcm_out_650 for RAC_PGATRIM */
+#define RAC_PGATRIM_PGAVCMOUTTRIM_DEFAULT (_RAC_PGATRIM_PGAVCMOUTTRIM_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_PGATRIM */
+#define RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_475 (_RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_475 << 6) /**< Shifted mode vcm_out_475 for RAC_PGATRIM */
+#define RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_500 (_RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_500 << 6) /**< Shifted mode vcm_out_500 for RAC_PGATRIM */
+#define RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_525 (_RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_525 << 6) /**< Shifted mode vcm_out_525 for RAC_PGATRIM */
+#define RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_550 (_RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_550 << 6) /**< Shifted mode vcm_out_550 for RAC_PGATRIM */
+#define RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_575 (_RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_575 << 6) /**< Shifted mode vcm_out_575 for RAC_PGATRIM */
+#define RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_600 (_RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_600 << 6) /**< Shifted mode vcm_out_600 for RAC_PGATRIM */
+#define RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_625 (_RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_625 << 6) /**< Shifted mode vcm_out_625 for RAC_PGATRIM */
+#define RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_650 (_RAC_PGATRIM_PGAVCMOUTTRIM_vcm_out_650 << 6) /**< Shifted mode vcm_out_650 for RAC_PGATRIM */
+#define _RAC_PGATRIM_PGAVLDOTRIM_SHIFT 9 /**< Shift value for RAC_PGAVLDOTRIM */
+#define _RAC_PGATRIM_PGAVLDOTRIM_MASK 0xE00UL /**< Bit mask for RAC_PGAVLDOTRIM */
+#define _RAC_PGATRIM_PGAVLDOTRIM_DEFAULT 0x00000005UL /**< Mode DEFAULT for RAC_PGATRIM */
+#define _RAC_PGATRIM_PGAVLDOTRIM_vdda_1225 0x00000000UL /**< Mode vdda_1225 for RAC_PGATRIM */
+#define _RAC_PGATRIM_PGAVLDOTRIM_vdda_1250 0x00000001UL /**< Mode vdda_1250 for RAC_PGATRIM */
+#define _RAC_PGATRIM_PGAVLDOTRIM_vdda_1275 0x00000002UL /**< Mode vdda_1275 for RAC_PGATRIM */
+#define _RAC_PGATRIM_PGAVLDOTRIM_vdda_1300 0x00000003UL /**< Mode vdda_1300 for RAC_PGATRIM */
+#define _RAC_PGATRIM_PGAVLDOTRIM_vdda_1325 0x00000004UL /**< Mode vdda_1325 for RAC_PGATRIM */
+#define _RAC_PGATRIM_PGAVLDOTRIM_vdda_1350 0x00000005UL /**< Mode vdda_1350 for RAC_PGATRIM */
+#define _RAC_PGATRIM_PGAVLDOTRIM_vdda_1375 0x00000006UL /**< Mode vdda_1375 for RAC_PGATRIM */
+#define _RAC_PGATRIM_PGAVLDOTRIM_vdda_1400 0x00000007UL /**< Mode vdda_1400 for RAC_PGATRIM */
+#define RAC_PGATRIM_PGAVLDOTRIM_DEFAULT (_RAC_PGATRIM_PGAVLDOTRIM_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_PGATRIM */
+#define RAC_PGATRIM_PGAVLDOTRIM_vdda_1225 (_RAC_PGATRIM_PGAVLDOTRIM_vdda_1225 << 9) /**< Shifted mode vdda_1225 for RAC_PGATRIM */
+#define RAC_PGATRIM_PGAVLDOTRIM_vdda_1250 (_RAC_PGATRIM_PGAVLDOTRIM_vdda_1250 << 9) /**< Shifted mode vdda_1250 for RAC_PGATRIM */
+#define RAC_PGATRIM_PGAVLDOTRIM_vdda_1275 (_RAC_PGATRIM_PGAVLDOTRIM_vdda_1275 << 9) /**< Shifted mode vdda_1275 for RAC_PGATRIM */
+#define RAC_PGATRIM_PGAVLDOTRIM_vdda_1300 (_RAC_PGATRIM_PGAVLDOTRIM_vdda_1300 << 9) /**< Shifted mode vdda_1300 for RAC_PGATRIM */
+#define RAC_PGATRIM_PGAVLDOTRIM_vdda_1325 (_RAC_PGATRIM_PGAVLDOTRIM_vdda_1325 << 9) /**< Shifted mode vdda_1325 for RAC_PGATRIM */
+#define RAC_PGATRIM_PGAVLDOTRIM_vdda_1350 (_RAC_PGATRIM_PGAVLDOTRIM_vdda_1350 << 9) /**< Shifted mode vdda_1350 for RAC_PGATRIM */
+#define RAC_PGATRIM_PGAVLDOTRIM_vdda_1375 (_RAC_PGATRIM_PGAVLDOTRIM_vdda_1375 << 9) /**< Shifted mode vdda_1375 for RAC_PGATRIM */
+#define RAC_PGATRIM_PGAVLDOTRIM_vdda_1400 (_RAC_PGATRIM_PGAVLDOTRIM_vdda_1400 << 9) /**< Shifted mode vdda_1400 for RAC_PGATRIM */
+
+/* Bit fields for RAC PGACAL */
+#define _RAC_PGACAL_RESETVALUE 0x00002020UL /**< Default value for RAC_PGACAL */
+#define _RAC_PGACAL_MASK 0x00003F3FUL /**< Mask for RAC_PGACAL */
+#define _RAC_PGACAL_PGAOFFCALI_SHIFT 0 /**< Shift value for RAC_PGAOFFCALI */
+#define _RAC_PGACAL_PGAOFFCALI_MASK 0x3FUL /**< Bit mask for RAC_PGAOFFCALI */
+#define _RAC_PGACAL_PGAOFFCALI_DEFAULT 0x00000020UL /**< Mode DEFAULT for RAC_PGACAL */
+#define RAC_PGACAL_PGAOFFCALI_DEFAULT (_RAC_PGACAL_PGAOFFCALI_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_PGACAL */
+#define _RAC_PGACAL_PGAOFFCALQ_SHIFT 8 /**< Shift value for RAC_PGAOFFCALQ */
+#define _RAC_PGACAL_PGAOFFCALQ_MASK 0x3F00UL /**< Bit mask for RAC_PGAOFFCALQ */
+#define _RAC_PGACAL_PGAOFFCALQ_DEFAULT 0x00000020UL /**< Mode DEFAULT for RAC_PGACAL */
+#define RAC_PGACAL_PGAOFFCALQ_DEFAULT (_RAC_PGACAL_PGAOFFCALQ_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_PGACAL */
+
+/* Bit fields for RAC PGACTRL */
+#define _RAC_PGACTRL_RESETVALUE 0x00008001UL /**< Default value for RAC_PGACTRL */
+#define _RAC_PGACTRL_MASK 0x01FFEFFFUL /**< Mask for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGABWMODE_SHIFT 0 /**< Shift value for RAC_PGABWMODE */
+#define _RAC_PGACTRL_PGABWMODE_MASK 0xFUL /**< Bit mask for RAC_PGABWMODE */
+#define _RAC_PGACTRL_PGABWMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_PGACTRL */
+#define RAC_PGACTRL_PGABWMODE_DEFAULT (_RAC_PGACTRL_PGABWMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAENGHZ (0x1UL << 4) /**< PGAENGHZ */
+#define _RAC_PGACTRL_PGAENGHZ_SHIFT 4 /**< Shift value for RAC_PGAENGHZ */
+#define _RAC_PGACTRL_PGAENGHZ_MASK 0x10UL /**< Bit mask for RAC_PGAENGHZ */
+#define _RAC_PGACTRL_PGAENGHZ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGAENGHZ_ghz_disable 0x00000000UL /**< Mode ghz_disable for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGAENGHZ_ghz_enable 0x00000001UL /**< Mode ghz_enable for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAENGHZ_DEFAULT (_RAC_PGACTRL_PGAENGHZ_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAENGHZ_ghz_disable (_RAC_PGACTRL_PGAENGHZ_ghz_disable << 4) /**< Shifted mode ghz_disable for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAENGHZ_ghz_enable (_RAC_PGACTRL_PGAENGHZ_ghz_enable << 4) /**< Shifted mode ghz_enable for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAENBIAS (0x1UL << 5) /**< PGAENBIAS */
+#define _RAC_PGACTRL_PGAENBIAS_SHIFT 5 /**< Shift value for RAC_PGAENBIAS */
+#define _RAC_PGACTRL_PGAENBIAS_MASK 0x20UL /**< Bit mask for RAC_PGAENBIAS */
+#define _RAC_PGACTRL_PGAENBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGAENBIAS_bias_disable 0x00000000UL /**< Mode bias_disable for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGAENBIAS_bias_enable 0x00000001UL /**< Mode bias_enable for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAENBIAS_DEFAULT (_RAC_PGACTRL_PGAENBIAS_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAENBIAS_bias_disable (_RAC_PGACTRL_PGAENBIAS_bias_disable << 5) /**< Shifted mode bias_disable for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAENBIAS_bias_enable (_RAC_PGACTRL_PGAENBIAS_bias_enable << 5) /**< Shifted mode bias_enable for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAENLATCHI (0x1UL << 6) /**< PGAENLATCHI */
+#define _RAC_PGACTRL_PGAENLATCHI_SHIFT 6 /**< Shift value for RAC_PGAENLATCHI */
+#define _RAC_PGACTRL_PGAENLATCHI_MASK 0x40UL /**< Bit mask for RAC_PGAENLATCHI */
+#define _RAC_PGACTRL_PGAENLATCHI_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGAENLATCHI_pkd_latch_i_disable 0x00000000UL /**< Mode pkd_latch_i_disable for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGAENLATCHI_pkd_latch_i_enable 0x00000001UL /**< Mode pkd_latch_i_enable for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAENLATCHI_DEFAULT (_RAC_PGACTRL_PGAENLATCHI_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAENLATCHI_pkd_latch_i_disable (_RAC_PGACTRL_PGAENLATCHI_pkd_latch_i_disable << 6) /**< Shifted mode pkd_latch_i_disable for RAC_PGACTRL*/
+#define RAC_PGACTRL_PGAENLATCHI_pkd_latch_i_enable (_RAC_PGACTRL_PGAENLATCHI_pkd_latch_i_enable << 6) /**< Shifted mode pkd_latch_i_enable for RAC_PGACTRL*/
+#define RAC_PGACTRL_PGAENLATCHQ (0x1UL << 7) /**< PGAENLATCHQ */
+#define _RAC_PGACTRL_PGAENLATCHQ_SHIFT 7 /**< Shift value for RAC_PGAENLATCHQ */
+#define _RAC_PGACTRL_PGAENLATCHQ_MASK 0x80UL /**< Bit mask for RAC_PGAENLATCHQ */
+#define _RAC_PGACTRL_PGAENLATCHQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGAENLATCHQ_pkd_latch_q_disable 0x00000000UL /**< Mode pkd_latch_q_disable for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGAENLATCHQ_pkd_latch_q_enable 0x00000001UL /**< Mode pkd_latch_q_enable for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAENLATCHQ_DEFAULT (_RAC_PGACTRL_PGAENLATCHQ_DEFAULT << 7) /**< Shifted mode DEFAULT for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAENLATCHQ_pkd_latch_q_disable (_RAC_PGACTRL_PGAENLATCHQ_pkd_latch_q_disable << 7) /**< Shifted mode pkd_latch_q_disable for RAC_PGACTRL*/
+#define RAC_PGACTRL_PGAENLATCHQ_pkd_latch_q_enable (_RAC_PGACTRL_PGAENLATCHQ_pkd_latch_q_enable << 7) /**< Shifted mode pkd_latch_q_enable for RAC_PGACTRL*/
+#define RAC_PGACTRL_PGAENLDOLOAD (0x1UL << 8) /**< PGAENLDOLOAD */
+#define _RAC_PGACTRL_PGAENLDOLOAD_SHIFT 8 /**< Shift value for RAC_PGAENLDOLOAD */
+#define _RAC_PGACTRL_PGAENLDOLOAD_MASK 0x100UL /**< Bit mask for RAC_PGAENLDOLOAD */
+#define _RAC_PGACTRL_PGAENLDOLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGAENLDOLOAD_disable_ldo_load 0x00000000UL /**< Mode disable_ldo_load for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGAENLDOLOAD_enable_ldo_load 0x00000001UL /**< Mode enable_ldo_load for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAENLDOLOAD_DEFAULT (_RAC_PGACTRL_PGAENLDOLOAD_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAENLDOLOAD_disable_ldo_load (_RAC_PGACTRL_PGAENLDOLOAD_disable_ldo_load << 8) /**< Shifted mode disable_ldo_load for RAC_PGACTRL*/
+#define RAC_PGACTRL_PGAENLDOLOAD_enable_ldo_load (_RAC_PGACTRL_PGAENLDOLOAD_enable_ldo_load << 8) /**< Shifted mode enable_ldo_load for RAC_PGACTRL*/
+#define RAC_PGACTRL_PGAENPGAI (0x1UL << 9) /**< PGAENPGAI */
+#define _RAC_PGACTRL_PGAENPGAI_SHIFT 9 /**< Shift value for RAC_PGAENPGAI */
+#define _RAC_PGACTRL_PGAENPGAI_MASK 0x200UL /**< Bit mask for RAC_PGAENPGAI */
+#define _RAC_PGACTRL_PGAENPGAI_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGAENPGAI_pgai_disable 0x00000000UL /**< Mode pgai_disable for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGAENPGAI_pgai_enable 0x00000001UL /**< Mode pgai_enable for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAENPGAI_DEFAULT (_RAC_PGACTRL_PGAENPGAI_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAENPGAI_pgai_disable (_RAC_PGACTRL_PGAENPGAI_pgai_disable << 9) /**< Shifted mode pgai_disable for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAENPGAI_pgai_enable (_RAC_PGACTRL_PGAENPGAI_pgai_enable << 9) /**< Shifted mode pgai_enable for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAENPGAQ (0x1UL << 10) /**< PGAENPGAQ */
+#define _RAC_PGACTRL_PGAENPGAQ_SHIFT 10 /**< Shift value for RAC_PGAENPGAQ */
+#define _RAC_PGACTRL_PGAENPGAQ_MASK 0x400UL /**< Bit mask for RAC_PGAENPGAQ */
+#define _RAC_PGACTRL_PGAENPGAQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGAENPGAQ_pgaq_disable 0x00000000UL /**< Mode pgaq_disable for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGAENPGAQ_pgaq_enable 0x00000001UL /**< Mode pgaq_enable for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAENPGAQ_DEFAULT (_RAC_PGACTRL_PGAENPGAQ_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAENPGAQ_pgaq_disable (_RAC_PGACTRL_PGAENPGAQ_pgaq_disable << 10) /**< Shifted mode pgaq_disable for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAENPGAQ_pgaq_enable (_RAC_PGACTRL_PGAENPGAQ_pgaq_enable << 10) /**< Shifted mode pgaq_enable for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAENPKD (0x1UL << 11) /**< PGAENPKD */
+#define _RAC_PGACTRL_PGAENPKD_SHIFT 11 /**< Shift value for RAC_PGAENPKD */
+#define _RAC_PGACTRL_PGAENPKD_MASK 0x800UL /**< Bit mask for RAC_PGAENPKD */
+#define _RAC_PGACTRL_PGAENPKD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGAENPKD_pkd_disable 0x00000000UL /**< Mode pkd_disable for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGAENPKD_pkd_enable 0x00000001UL /**< Mode pkd_enable for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAENPKD_DEFAULT (_RAC_PGACTRL_PGAENPKD_DEFAULT << 11) /**< Shifted mode DEFAULT for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAENPKD_pkd_disable (_RAC_PGACTRL_PGAENPKD_pkd_disable << 11) /**< Shifted mode pkd_disable for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAENPKD_pkd_enable (_RAC_PGACTRL_PGAENPKD_pkd_enable << 11) /**< Shifted mode pkd_enable for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGAPOWERMODE_SHIFT 14 /**< Shift value for RAC_PGAPOWERMODE */
+#define _RAC_PGACTRL_PGAPOWERMODE_MASK 0x1C000UL /**< Bit mask for RAC_PGAPOWERMODE */
+#define _RAC_PGACTRL_PGAPOWERMODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGAPOWERMODE_pm0_3u0 0x00000000UL /**< Mode pm0_3u0 for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGAPOWERMODE_pm1_3u5 0x00000001UL /**< Mode pm1_3u5 for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGAPOWERMODE_pm2_4u0 0x00000002UL /**< Mode pm2_4u0 for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGAPOWERMODE_pm3_4u5 0x00000003UL /**< Mode pm3_4u5 for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGAPOWERMODE_pm4_4u0 0x00000004UL /**< Mode pm4_4u0 for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGAPOWERMODE_pm5_4u5 0x00000005UL /**< Mode pm5_4u5 for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGAPOWERMODE_pm6_5u0 0x00000006UL /**< Mode pm6_5u0 for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGAPOWERMODE_pm7_5u5 0x00000007UL /**< Mode pm7_5u5 for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAPOWERMODE_DEFAULT (_RAC_PGACTRL_PGAPOWERMODE_DEFAULT << 14) /**< Shifted mode DEFAULT for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAPOWERMODE_pm0_3u0 (_RAC_PGACTRL_PGAPOWERMODE_pm0_3u0 << 14) /**< Shifted mode pm0_3u0 for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAPOWERMODE_pm1_3u5 (_RAC_PGACTRL_PGAPOWERMODE_pm1_3u5 << 14) /**< Shifted mode pm1_3u5 for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAPOWERMODE_pm2_4u0 (_RAC_PGACTRL_PGAPOWERMODE_pm2_4u0 << 14) /**< Shifted mode pm2_4u0 for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAPOWERMODE_pm3_4u5 (_RAC_PGACTRL_PGAPOWERMODE_pm3_4u5 << 14) /**< Shifted mode pm3_4u5 for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAPOWERMODE_pm4_4u0 (_RAC_PGACTRL_PGAPOWERMODE_pm4_4u0 << 14) /**< Shifted mode pm4_4u0 for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAPOWERMODE_pm5_4u5 (_RAC_PGACTRL_PGAPOWERMODE_pm5_4u5 << 14) /**< Shifted mode pm5_4u5 for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAPOWERMODE_pm6_5u0 (_RAC_PGACTRL_PGAPOWERMODE_pm6_5u0 << 14) /**< Shifted mode pm6_5u0 for RAC_PGACTRL */
+#define RAC_PGACTRL_PGAPOWERMODE_pm7_5u5 (_RAC_PGACTRL_PGAPOWERMODE_pm7_5u5 << 14) /**< Shifted mode pm7_5u5 for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGATHRPKDLOSEL_SHIFT 17 /**< Shift value for RAC_PGATHRPKDLOSEL */
+#define _RAC_PGACTRL_PGATHRPKDLOSEL_MASK 0x1E0000UL /**< Bit mask for RAC_PGATHRPKDLOSEL */
+#define _RAC_PGACTRL_PGATHRPKDLOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGATHRPKDLOSEL_vref50mv 0x00000000UL /**< Mode vref50mv for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGATHRPKDLOSEL_vref75mv 0x00000001UL /**< Mode vref75mv for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGATHRPKDLOSEL_vref100mv 0x00000002UL /**< Mode vref100mv for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGATHRPKDLOSEL_vref125mv 0x00000003UL /**< Mode vref125mv for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGATHRPKDLOSEL_vref150mv 0x00000004UL /**< Mode vref150mv for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGATHRPKDLOSEL_vref175mv 0x00000005UL /**< Mode vref175mv for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGATHRPKDLOSEL_vref200mv 0x00000006UL /**< Mode vref200mv for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGATHRPKDLOSEL_vref225mv 0x00000007UL /**< Mode vref225mv for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGATHRPKDLOSEL_vref250mv 0x00000008UL /**< Mode vref250mv for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGATHRPKDLOSEL_vref275mv 0x00000009UL /**< Mode vref275mv for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGATHRPKDLOSEL_vref300mv 0x0000000AUL /**< Mode vref300mv for RAC_PGACTRL */
+#define RAC_PGACTRL_PGATHRPKDLOSEL_DEFAULT (_RAC_PGACTRL_PGATHRPKDLOSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for RAC_PGACTRL */
+#define RAC_PGACTRL_PGATHRPKDLOSEL_vref50mv (_RAC_PGACTRL_PGATHRPKDLOSEL_vref50mv << 17) /**< Shifted mode vref50mv for RAC_PGACTRL */
+#define RAC_PGACTRL_PGATHRPKDLOSEL_vref75mv (_RAC_PGACTRL_PGATHRPKDLOSEL_vref75mv << 17) /**< Shifted mode vref75mv for RAC_PGACTRL */
+#define RAC_PGACTRL_PGATHRPKDLOSEL_vref100mv (_RAC_PGACTRL_PGATHRPKDLOSEL_vref100mv << 17) /**< Shifted mode vref100mv for RAC_PGACTRL */
+#define RAC_PGACTRL_PGATHRPKDLOSEL_vref125mv (_RAC_PGACTRL_PGATHRPKDLOSEL_vref125mv << 17) /**< Shifted mode vref125mv for RAC_PGACTRL */
+#define RAC_PGACTRL_PGATHRPKDLOSEL_vref150mv (_RAC_PGACTRL_PGATHRPKDLOSEL_vref150mv << 17) /**< Shifted mode vref150mv for RAC_PGACTRL */
+#define RAC_PGACTRL_PGATHRPKDLOSEL_vref175mv (_RAC_PGACTRL_PGATHRPKDLOSEL_vref175mv << 17) /**< Shifted mode vref175mv for RAC_PGACTRL */
+#define RAC_PGACTRL_PGATHRPKDLOSEL_vref200mv (_RAC_PGACTRL_PGATHRPKDLOSEL_vref200mv << 17) /**< Shifted mode vref200mv for RAC_PGACTRL */
+#define RAC_PGACTRL_PGATHRPKDLOSEL_vref225mv (_RAC_PGACTRL_PGATHRPKDLOSEL_vref225mv << 17) /**< Shifted mode vref225mv for RAC_PGACTRL */
+#define RAC_PGACTRL_PGATHRPKDLOSEL_vref250mv (_RAC_PGACTRL_PGATHRPKDLOSEL_vref250mv << 17) /**< Shifted mode vref250mv for RAC_PGACTRL */
+#define RAC_PGACTRL_PGATHRPKDLOSEL_vref275mv (_RAC_PGACTRL_PGATHRPKDLOSEL_vref275mv << 17) /**< Shifted mode vref275mv for RAC_PGACTRL */
+#define RAC_PGACTRL_PGATHRPKDLOSEL_vref300mv (_RAC_PGACTRL_PGATHRPKDLOSEL_vref300mv << 17) /**< Shifted mode vref300mv for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGATHRPKDHISEL_SHIFT 21 /**< Shift value for RAC_PGATHRPKDHISEL */
+#define _RAC_PGACTRL_PGATHRPKDHISEL_MASK 0x1E00000UL /**< Bit mask for RAC_PGATHRPKDHISEL */
+#define _RAC_PGACTRL_PGATHRPKDHISEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGATHRPKDHISEL_vref50mv 0x00000000UL /**< Mode vref50mv for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGATHRPKDHISEL_vref75mv 0x00000001UL /**< Mode vref75mv for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGATHRPKDHISEL_vref100mv 0x00000002UL /**< Mode vref100mv for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGATHRPKDHISEL_vref125mv 0x00000003UL /**< Mode vref125mv for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGATHRPKDHISEL_verf150mv 0x00000004UL /**< Mode verf150mv for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGATHRPKDHISEL_vref175mv 0x00000005UL /**< Mode vref175mv for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGATHRPKDHISEL_vref200mv 0x00000006UL /**< Mode vref200mv for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGATHRPKDHISEL_vref225mv 0x00000007UL /**< Mode vref225mv for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGATHRPKDHISEL_vref250mv 0x00000008UL /**< Mode vref250mv for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGATHRPKDHISEL_vref275mv 0x00000009UL /**< Mode vref275mv for RAC_PGACTRL */
+#define _RAC_PGACTRL_PGATHRPKDHISEL_vref300mv 0x0000000AUL /**< Mode vref300mv for RAC_PGACTRL */
+#define RAC_PGACTRL_PGATHRPKDHISEL_DEFAULT (_RAC_PGACTRL_PGATHRPKDHISEL_DEFAULT << 21) /**< Shifted mode DEFAULT for RAC_PGACTRL */
+#define RAC_PGACTRL_PGATHRPKDHISEL_vref50mv (_RAC_PGACTRL_PGATHRPKDHISEL_vref50mv << 21) /**< Shifted mode vref50mv for RAC_PGACTRL */
+#define RAC_PGACTRL_PGATHRPKDHISEL_vref75mv (_RAC_PGACTRL_PGATHRPKDHISEL_vref75mv << 21) /**< Shifted mode vref75mv for RAC_PGACTRL */
+#define RAC_PGACTRL_PGATHRPKDHISEL_vref100mv (_RAC_PGACTRL_PGATHRPKDHISEL_vref100mv << 21) /**< Shifted mode vref100mv for RAC_PGACTRL */
+#define RAC_PGACTRL_PGATHRPKDHISEL_vref125mv (_RAC_PGACTRL_PGATHRPKDHISEL_vref125mv << 21) /**< Shifted mode vref125mv for RAC_PGACTRL */
+#define RAC_PGACTRL_PGATHRPKDHISEL_verf150mv (_RAC_PGACTRL_PGATHRPKDHISEL_verf150mv << 21) /**< Shifted mode verf150mv for RAC_PGACTRL */
+#define RAC_PGACTRL_PGATHRPKDHISEL_vref175mv (_RAC_PGACTRL_PGATHRPKDHISEL_vref175mv << 21) /**< Shifted mode vref175mv for RAC_PGACTRL */
+#define RAC_PGACTRL_PGATHRPKDHISEL_vref200mv (_RAC_PGACTRL_PGATHRPKDHISEL_vref200mv << 21) /**< Shifted mode vref200mv for RAC_PGACTRL */
+#define RAC_PGACTRL_PGATHRPKDHISEL_vref225mv (_RAC_PGACTRL_PGATHRPKDHISEL_vref225mv << 21) /**< Shifted mode vref225mv for RAC_PGACTRL */
+#define RAC_PGACTRL_PGATHRPKDHISEL_vref250mv (_RAC_PGACTRL_PGATHRPKDHISEL_vref250mv << 21) /**< Shifted mode vref250mv for RAC_PGACTRL */
+#define RAC_PGACTRL_PGATHRPKDHISEL_vref275mv (_RAC_PGACTRL_PGATHRPKDHISEL_vref275mv << 21) /**< Shifted mode vref275mv for RAC_PGACTRL */
+#define RAC_PGACTRL_PGATHRPKDHISEL_vref300mv (_RAC_PGACTRL_PGATHRPKDHISEL_vref300mv << 21) /**< Shifted mode vref300mv for RAC_PGACTRL */
+
+/* Bit fields for RAC RFBIASCAL */
+#define _RAC_RFBIASCAL_RESETVALUE 0x30201A20UL /**< Default value for RAC_RFBIASCAL */
+#define _RAC_RFBIASCAL_MASK 0x3F3F3F3FUL /**< Mask for RAC_RFBIASCAL */
+#define _RAC_RFBIASCAL_RFBIASCALBIAS_SHIFT 0 /**< Shift value for RAC_RFBIASCALBIAS */
+#define _RAC_RFBIASCAL_RFBIASCALBIAS_MASK 0x3FUL /**< Bit mask for RAC_RFBIASCALBIAS */
+#define _RAC_RFBIASCAL_RFBIASCALBIAS_DEFAULT 0x00000020UL /**< Mode DEFAULT for RAC_RFBIASCAL */
+#define RAC_RFBIASCAL_RFBIASCALBIAS_DEFAULT (_RAC_RFBIASCAL_RFBIASCALBIAS_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_RFBIASCAL */
+#define _RAC_RFBIASCAL_RFBIASCALTC_SHIFT 8 /**< Shift value for RAC_RFBIASCALTC */
+#define _RAC_RFBIASCAL_RFBIASCALTC_MASK 0x3F00UL /**< Bit mask for RAC_RFBIASCALTC */
+#define _RAC_RFBIASCAL_RFBIASCALTC_DEFAULT 0x0000001AUL /**< Mode DEFAULT for RAC_RFBIASCAL */
+#define RAC_RFBIASCAL_RFBIASCALTC_DEFAULT (_RAC_RFBIASCAL_RFBIASCALTC_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_RFBIASCAL */
+#define _RAC_RFBIASCAL_RFBIASCALVREF_SHIFT 16 /**< Shift value for RAC_RFBIASCALVREF */
+#define _RAC_RFBIASCAL_RFBIASCALVREF_MASK 0x3F0000UL /**< Bit mask for RAC_RFBIASCALVREF */
+#define _RAC_RFBIASCAL_RFBIASCALVREF_DEFAULT 0x00000020UL /**< Mode DEFAULT for RAC_RFBIASCAL */
+#define RAC_RFBIASCAL_RFBIASCALVREF_DEFAULT (_RAC_RFBIASCAL_RFBIASCALVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_RFBIASCAL */
+#define _RAC_RFBIASCAL_RFBIASCALVREFSTARTUP_SHIFT 24 /**< Shift value for RAC_RFBIASCALVREFSTARTUP */
+#define _RAC_RFBIASCAL_RFBIASCALVREFSTARTUP_MASK 0x3F000000UL /**< Bit mask for RAC_RFBIASCALVREFSTARTUP */
+#define _RAC_RFBIASCAL_RFBIASCALVREFSTARTUP_DEFAULT 0x00000030UL /**< Mode DEFAULT for RAC_RFBIASCAL */
+#define RAC_RFBIASCAL_RFBIASCALVREFSTARTUP_DEFAULT (_RAC_RFBIASCAL_RFBIASCALVREFSTARTUP_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_RFBIASCAL */
+
+/* Bit fields for RAC RFBIASCTRL */
+#define _RAC_RFBIASCTRL_RESETVALUE 0x00040000UL /**< Default value for RAC_RFBIASCTRL */
+#define _RAC_RFBIASCTRL_MASK 0x000F001FUL /**< Mask for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASDISABLEBOOTSTRAP (0x1UL << 0) /**< RFBIASDISABLEBOOTSTRAP */
+#define _RAC_RFBIASCTRL_RFBIASDISABLEBOOTSTRAP_SHIFT 0 /**< Shift value for RAC_RFBIASDISABLEBOOTSTRAP */
+#define _RAC_RFBIASCTRL_RFBIASDISABLEBOOTSTRAP_MASK 0x1UL /**< Bit mask for RAC_RFBIASDISABLEBOOTSTRAP */
+#define _RAC_RFBIASCTRL_RFBIASDISABLEBOOTSTRAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RFBIASCTRL */
+#define _RAC_RFBIASCTRL_RFBIASDISABLEBOOTSTRAP_enable_startup 0x00000000UL /**< Mode enable_startup for RAC_RFBIASCTRL */
+#define _RAC_RFBIASCTRL_RFBIASDISABLEBOOTSTRAP_disable_startup 0x00000001UL /**< Mode disable_startup for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASDISABLEBOOTSTRAP_DEFAULT (_RAC_RFBIASCTRL_RFBIASDISABLEBOOTSTRAP_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASDISABLEBOOTSTRAP_enable_startup (_RAC_RFBIASCTRL_RFBIASDISABLEBOOTSTRAP_enable_startup << 0) /**< Shifted mode enable_startup for RAC_RFBIASCTRL*/
+#define RAC_RFBIASCTRL_RFBIASDISABLEBOOTSTRAP_disable_startup (_RAC_RFBIASCTRL_RFBIASDISABLEBOOTSTRAP_disable_startup << 0) /**< Shifted mode disable_startup for RAC_RFBIASCTRL*/
+#define RAC_RFBIASCTRL_RFBIASLDOHIGHCURRENT (0x1UL << 1) /**< RFBIASLDOHIGHCURRENT */
+#define _RAC_RFBIASCTRL_RFBIASLDOHIGHCURRENT_SHIFT 1 /**< Shift value for RAC_RFBIASLDOHIGHCURRENT */
+#define _RAC_RFBIASCTRL_RFBIASLDOHIGHCURRENT_MASK 0x2UL /**< Bit mask for RAC_RFBIASLDOHIGHCURRENT */
+#define _RAC_RFBIASCTRL_RFBIASLDOHIGHCURRENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RFBIASCTRL */
+#define _RAC_RFBIASCTRL_RFBIASLDOHIGHCURRENT_low_current 0x00000000UL /**< Mode low_current for RAC_RFBIASCTRL */
+#define _RAC_RFBIASCTRL_RFBIASLDOHIGHCURRENT_high_current 0x00000001UL /**< Mode high_current for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASLDOHIGHCURRENT_DEFAULT (_RAC_RFBIASCTRL_RFBIASLDOHIGHCURRENT_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASLDOHIGHCURRENT_low_current (_RAC_RFBIASCTRL_RFBIASLDOHIGHCURRENT_low_current << 1) /**< Shifted mode low_current for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASLDOHIGHCURRENT_high_current (_RAC_RFBIASCTRL_RFBIASLDOHIGHCURRENT_high_current << 1) /**< Shifted mode high_current for RAC_RFBIASCTRL*/
+#define RAC_RFBIASCTRL_RFBIASNONFLASHMODE (0x1UL << 2) /**< RFBIASNONFLASHMODE */
+#define _RAC_RFBIASCTRL_RFBIASNONFLASHMODE_SHIFT 2 /**< Shift value for RAC_RFBIASNONFLASHMODE */
+#define _RAC_RFBIASCTRL_RFBIASNONFLASHMODE_MASK 0x4UL /**< Bit mask for RAC_RFBIASNONFLASHMODE */
+#define _RAC_RFBIASCTRL_RFBIASNONFLASHMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RFBIASCTRL */
+#define _RAC_RFBIASCTRL_RFBIASNONFLASHMODE_flash_process 0x00000000UL /**< Mode flash_process for RAC_RFBIASCTRL */
+#define _RAC_RFBIASCTRL_RFBIASNONFLASHMODE_non_flash_process 0x00000001UL /**< Mode non_flash_process for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASNONFLASHMODE_DEFAULT (_RAC_RFBIASCTRL_RFBIASNONFLASHMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASNONFLASHMODE_flash_process (_RAC_RFBIASCTRL_RFBIASNONFLASHMODE_flash_process << 2) /**< Shifted mode flash_process for RAC_RFBIASCTRL*/
+#define RAC_RFBIASCTRL_RFBIASNONFLASHMODE_non_flash_process (_RAC_RFBIASCTRL_RFBIASNONFLASHMODE_non_flash_process << 2) /**< Shifted mode non_flash_process for RAC_RFBIASCTRL*/
+#define RAC_RFBIASCTRL_RFBIASSTARTUPCORE (0x1UL << 3) /**< RFBIASSTARTUPCORE */
+#define _RAC_RFBIASCTRL_RFBIASSTARTUPCORE_SHIFT 3 /**< Shift value for RAC_RFBIASSTARTUPCORE */
+#define _RAC_RFBIASCTRL_RFBIASSTARTUPCORE_MASK 0x8UL /**< Bit mask for RAC_RFBIASSTARTUPCORE */
+#define _RAC_RFBIASCTRL_RFBIASSTARTUPCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RFBIASCTRL */
+#define _RAC_RFBIASCTRL_RFBIASSTARTUPCORE_default 0x00000000UL /**< Mode default for RAC_RFBIASCTRL */
+#define _RAC_RFBIASCTRL_RFBIASSTARTUPCORE_force_start 0x00000001UL /**< Mode force_start for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASSTARTUPCORE_DEFAULT (_RAC_RFBIASCTRL_RFBIASSTARTUPCORE_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASSTARTUPCORE_default (_RAC_RFBIASCTRL_RFBIASSTARTUPCORE_default << 3) /**< Shifted mode default for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASSTARTUPCORE_force_start (_RAC_RFBIASCTRL_RFBIASSTARTUPCORE_force_start << 3) /**< Shifted mode force_start for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASSTARTUPSUPPLY (0x1UL << 4) /**< RFBIASSTARTUPSUPPLY */
+#define _RAC_RFBIASCTRL_RFBIASSTARTUPSUPPLY_SHIFT 4 /**< Shift value for RAC_RFBIASSTARTUPSUPPLY */
+#define _RAC_RFBIASCTRL_RFBIASSTARTUPSUPPLY_MASK 0x10UL /**< Bit mask for RAC_RFBIASSTARTUPSUPPLY */
+#define _RAC_RFBIASCTRL_RFBIASSTARTUPSUPPLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RFBIASCTRL */
+#define _RAC_RFBIASCTRL_RFBIASSTARTUPSUPPLY_default 0x00000000UL /**< Mode default for RAC_RFBIASCTRL */
+#define _RAC_RFBIASCTRL_RFBIASSTARTUPSUPPLY_forc_start 0x00000001UL /**< Mode forc_start for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASSTARTUPSUPPLY_DEFAULT (_RAC_RFBIASCTRL_RFBIASSTARTUPSUPPLY_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASSTARTUPSUPPLY_default (_RAC_RFBIASCTRL_RFBIASSTARTUPSUPPLY_default << 4) /**< Shifted mode default for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASSTARTUPSUPPLY_forc_start (_RAC_RFBIASCTRL_RFBIASSTARTUPSUPPLY_forc_start << 4) /**< Shifted mode forc_start for RAC_RFBIASCTRL */
+#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_SHIFT 16 /**< Shift value for RAC_RFBIASLDOVREFTRIM */
+#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_MASK 0xF0000UL /**< Bit mask for RAC_RFBIASLDOVREFTRIM */
+#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_DEFAULT 0x00000004UL /**< Mode DEFAULT for RAC_RFBIASCTRL */
+#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p800 0x00000000UL /**< Mode vref_v0p800 for RAC_RFBIASCTRL */
+#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p813 0x00000001UL /**< Mode vref_v0p813 for RAC_RFBIASCTRL */
+#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p825 0x00000002UL /**< Mode vref_v0p825 for RAC_RFBIASCTRL */
+#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p837 0x00000003UL /**< Mode vref_v0p837 for RAC_RFBIASCTRL */
+#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p850 0x00000004UL /**< Mode vref_v0p850 for RAC_RFBIASCTRL */
+#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p863 0x00000005UL /**< Mode vref_v0p863 for RAC_RFBIASCTRL */
+#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p875 0x00000006UL /**< Mode vref_v0p875 for RAC_RFBIASCTRL */
+#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p887 0x00000007UL /**< Mode vref_v0p887 for RAC_RFBIASCTRL */
+#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p900 0x00000008UL /**< Mode vref_v0p900 for RAC_RFBIASCTRL */
+#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p913 0x00000009UL /**< Mode vref_v0p913 for RAC_RFBIASCTRL */
+#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p925 0x0000000AUL /**< Mode vref_v0p925 for RAC_RFBIASCTRL */
+#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p938 0x0000000BUL /**< Mode vref_v0p938 for RAC_RFBIASCTRL */
+#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p950 0x0000000CUL /**< Mode vref_v0p950 for RAC_RFBIASCTRL */
+#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p963 0x0000000DUL /**< Mode vref_v0p963 for RAC_RFBIASCTRL */
+#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p975 0x0000000EUL /**< Mode vref_v0p975 for RAC_RFBIASCTRL */
+#define _RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p988 0x0000000FUL /**< Mode vref_v0p988 for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_DEFAULT (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p800 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p800 << 16) /**< Shifted mode vref_v0p800 for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p813 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p813 << 16) /**< Shifted mode vref_v0p813 for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p825 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p825 << 16) /**< Shifted mode vref_v0p825 for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p837 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p837 << 16) /**< Shifted mode vref_v0p837 for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p850 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p850 << 16) /**< Shifted mode vref_v0p850 for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p863 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p863 << 16) /**< Shifted mode vref_v0p863 for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p875 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p875 << 16) /**< Shifted mode vref_v0p875 for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p887 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p887 << 16) /**< Shifted mode vref_v0p887 for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p900 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p900 << 16) /**< Shifted mode vref_v0p900 for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p913 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p913 << 16) /**< Shifted mode vref_v0p913 for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p925 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p925 << 16) /**< Shifted mode vref_v0p925 for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p938 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p938 << 16) /**< Shifted mode vref_v0p938 for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p950 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p950 << 16) /**< Shifted mode vref_v0p950 for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p963 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p963 << 16) /**< Shifted mode vref_v0p963 for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p975 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p975 << 16) /**< Shifted mode vref_v0p975 for RAC_RFBIASCTRL */
+#define RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p988 (_RAC_RFBIASCTRL_RFBIASLDOVREFTRIM_vref_v0p988 << 16) /**< Shifted mode vref_v0p988 for RAC_RFBIASCTRL */
+
+/* Bit fields for RAC RADIOEN */
+#define _RAC_RADIOEN_RESETVALUE 0x00000000UL /**< Default value for RAC_RADIOEN */
+#define _RAC_RADIOEN_MASK 0x00000007UL /**< Mask for RAC_RADIOEN */
+#define RAC_RADIOEN_PREEN (0x1UL << 0) /**< PREEN */
+#define _RAC_RADIOEN_PREEN_SHIFT 0 /**< Shift value for RAC_PREEN */
+#define _RAC_RADIOEN_PREEN_MASK 0x1UL /**< Bit mask for RAC_PREEN */
+#define _RAC_RADIOEN_PREEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RADIOEN */
+#define _RAC_RADIOEN_PREEN_powered_off 0x00000000UL /**< Mode powered_off for RAC_RADIOEN */
+#define _RAC_RADIOEN_PREEN_powered_on 0x00000001UL /**< Mode powered_on for RAC_RADIOEN */
+#define RAC_RADIOEN_PREEN_DEFAULT (_RAC_RADIOEN_PREEN_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_RADIOEN */
+#define RAC_RADIOEN_PREEN_powered_off (_RAC_RADIOEN_PREEN_powered_off << 0) /**< Shifted mode powered_off for RAC_RADIOEN */
+#define RAC_RADIOEN_PREEN_powered_on (_RAC_RADIOEN_PREEN_powered_on << 0) /**< Shifted mode powered_on for RAC_RADIOEN */
+#define RAC_RADIOEN_PRESTB100UDIS (0x1UL << 1) /**< PRESTB100UDIS */
+#define _RAC_RADIOEN_PRESTB100UDIS_SHIFT 1 /**< Shift value for RAC_PRESTB100UDIS */
+#define _RAC_RADIOEN_PRESTB100UDIS_MASK 0x2UL /**< Bit mask for RAC_PRESTB100UDIS */
+#define _RAC_RADIOEN_PRESTB100UDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RADIOEN */
+#define _RAC_RADIOEN_PRESTB100UDIS_i100ua_enabled 0x00000000UL /**< Mode i100ua_enabled for RAC_RADIOEN */
+#define _RAC_RADIOEN_PRESTB100UDIS_i100ua_disabled 0x00000001UL /**< Mode i100ua_disabled for RAC_RADIOEN */
+#define RAC_RADIOEN_PRESTB100UDIS_DEFAULT (_RAC_RADIOEN_PRESTB100UDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_RADIOEN */
+#define RAC_RADIOEN_PRESTB100UDIS_i100ua_enabled (_RAC_RADIOEN_PRESTB100UDIS_i100ua_enabled << 1) /**< Shifted mode i100ua_enabled for RAC_RADIOEN */
+#define RAC_RADIOEN_PRESTB100UDIS_i100ua_disabled (_RAC_RADIOEN_PRESTB100UDIS_i100ua_disabled << 1) /**< Shifted mode i100ua_disabled for RAC_RADIOEN*/
+#define RAC_RADIOEN_RFBIASEN (0x1UL << 2) /**< RFBIASEN */
+#define _RAC_RADIOEN_RFBIASEN_SHIFT 2 /**< Shift value for RAC_RFBIASEN */
+#define _RAC_RADIOEN_RFBIASEN_MASK 0x4UL /**< Bit mask for RAC_RFBIASEN */
+#define _RAC_RADIOEN_RFBIASEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RADIOEN */
+#define _RAC_RADIOEN_RFBIASEN_disable_rfis_vtr 0x00000000UL /**< Mode disable_rfis_vtr for RAC_RADIOEN */
+#define _RAC_RADIOEN_RFBIASEN_enable_rfis_vtr 0x00000001UL /**< Mode enable_rfis_vtr for RAC_RADIOEN */
+#define RAC_RADIOEN_RFBIASEN_DEFAULT (_RAC_RADIOEN_RFBIASEN_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_RADIOEN */
+#define RAC_RADIOEN_RFBIASEN_disable_rfis_vtr (_RAC_RADIOEN_RFBIASEN_disable_rfis_vtr << 2) /**< Shifted mode disable_rfis_vtr for RAC_RADIOEN*/
+#define RAC_RADIOEN_RFBIASEN_enable_rfis_vtr (_RAC_RADIOEN_RFBIASEN_enable_rfis_vtr << 2) /**< Shifted mode enable_rfis_vtr for RAC_RADIOEN*/
+
+/* Bit fields for RAC RFPATHEN0 */
+#define _RAC_RFPATHEN0_RESETVALUE 0x00000002UL /**< Default value for RAC_RFPATHEN0 */
+#define _RAC_RFPATHEN0_MASK 0x0000004FUL /**< Mask for RAC_RFPATHEN0 */
+#define RAC_RFPATHEN0_LNAMIXEN0 (0x1UL << 0) /**< LNAMIXEN0 */
+#define _RAC_RFPATHEN0_LNAMIXEN0_SHIFT 0 /**< Shift value for RAC_LNAMIXEN0 */
+#define _RAC_RFPATHEN0_LNAMIXEN0_MASK 0x1UL /**< Bit mask for RAC_LNAMIXEN0 */
+#define _RAC_RFPATHEN0_LNAMIXEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RFPATHEN0 */
+#define _RAC_RFPATHEN0_LNAMIXEN0_disable 0x00000000UL /**< Mode disable for RAC_RFPATHEN0 */
+#define _RAC_RFPATHEN0_LNAMIXEN0_enable 0x00000001UL /**< Mode enable for RAC_RFPATHEN0 */
+#define RAC_RFPATHEN0_LNAMIXEN0_DEFAULT (_RAC_RFPATHEN0_LNAMIXEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_RFPATHEN0 */
+#define RAC_RFPATHEN0_LNAMIXEN0_disable (_RAC_RFPATHEN0_LNAMIXEN0_disable << 0) /**< Shifted mode disable for RAC_RFPATHEN0 */
+#define RAC_RFPATHEN0_LNAMIXEN0_enable (_RAC_RFPATHEN0_LNAMIXEN0_enable << 0) /**< Shifted mode enable for RAC_RFPATHEN0 */
+#define RAC_RFPATHEN0_LNAMIXRFATTDCEN0 (0x1UL << 1) /**< LNAMIXRFATTDCEN0 */
+#define _RAC_RFPATHEN0_LNAMIXRFATTDCEN0_SHIFT 1 /**< Shift value for RAC_LNAMIXRFATTDCEN0 */
+#define _RAC_RFPATHEN0_LNAMIXRFATTDCEN0_MASK 0x2UL /**< Bit mask for RAC_LNAMIXRFATTDCEN0 */
+#define _RAC_RFPATHEN0_LNAMIXRFATTDCEN0_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_RFPATHEN0 */
+#define _RAC_RFPATHEN0_LNAMIXRFATTDCEN0_disable_dc 0x00000000UL /**< Mode disable_dc for RAC_RFPATHEN0 */
+#define _RAC_RFPATHEN0_LNAMIXRFATTDCEN0_enable_dc 0x00000001UL /**< Mode enable_dc for RAC_RFPATHEN0 */
+#define RAC_RFPATHEN0_LNAMIXRFATTDCEN0_DEFAULT (_RAC_RFPATHEN0_LNAMIXRFATTDCEN0_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_RFPATHEN0 */
+#define RAC_RFPATHEN0_LNAMIXRFATTDCEN0_disable_dc (_RAC_RFPATHEN0_LNAMIXRFATTDCEN0_disable_dc << 1) /**< Shifted mode disable_dc for RAC_RFPATHEN0 */
+#define RAC_RFPATHEN0_LNAMIXRFATTDCEN0_enable_dc (_RAC_RFPATHEN0_LNAMIXRFATTDCEN0_enable_dc << 1) /**< Shifted mode enable_dc for RAC_RFPATHEN0 */
+#define RAC_RFPATHEN0_LNAMIXRFPKDENRF0 (0x1UL << 2) /**< LNAMIXRFPKDENRF0 */
+#define _RAC_RFPATHEN0_LNAMIXRFPKDENRF0_SHIFT 2 /**< Shift value for RAC_LNAMIXRFPKDENRF0 */
+#define _RAC_RFPATHEN0_LNAMIXRFPKDENRF0_MASK 0x4UL /**< Bit mask for RAC_LNAMIXRFPKDENRF0 */
+#define _RAC_RFPATHEN0_LNAMIXRFPKDENRF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RFPATHEN0 */
+#define _RAC_RFPATHEN0_LNAMIXRFPKDENRF0_disable 0x00000000UL /**< Mode disable for RAC_RFPATHEN0 */
+#define _RAC_RFPATHEN0_LNAMIXRFPKDENRF0_enable_path 0x00000001UL /**< Mode enable_path for RAC_RFPATHEN0 */
+#define RAC_RFPATHEN0_LNAMIXRFPKDENRF0_DEFAULT (_RAC_RFPATHEN0_LNAMIXRFPKDENRF0_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_RFPATHEN0 */
+#define RAC_RFPATHEN0_LNAMIXRFPKDENRF0_disable (_RAC_RFPATHEN0_LNAMIXRFPKDENRF0_disable << 2) /**< Shifted mode disable for RAC_RFPATHEN0 */
+#define RAC_RFPATHEN0_LNAMIXRFPKDENRF0_enable_path (_RAC_RFPATHEN0_LNAMIXRFPKDENRF0_enable_path << 2) /**< Shifted mode enable_path for RAC_RFPATHEN0 */
+#define RAC_RFPATHEN0_SYLODIVRLO02G4EN (0x1UL << 3) /**< SYLODIVRLO02G4EN */
+#define _RAC_RFPATHEN0_SYLODIVRLO02G4EN_SHIFT 3 /**< Shift value for RAC_SYLODIVRLO02G4EN */
+#define _RAC_RFPATHEN0_SYLODIVRLO02G4EN_MASK 0x8UL /**< Bit mask for RAC_SYLODIVRLO02G4EN */
+#define _RAC_RFPATHEN0_SYLODIVRLO02G4EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RFPATHEN0 */
+#define _RAC_RFPATHEN0_SYLODIVRLO02G4EN_disable 0x00000000UL /**< Mode disable for RAC_RFPATHEN0 */
+#define _RAC_RFPATHEN0_SYLODIVRLO02G4EN_enable 0x00000001UL /**< Mode enable for RAC_RFPATHEN0 */
+#define RAC_RFPATHEN0_SYLODIVRLO02G4EN_DEFAULT (_RAC_RFPATHEN0_SYLODIVRLO02G4EN_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_RFPATHEN0 */
+#define RAC_RFPATHEN0_SYLODIVRLO02G4EN_disable (_RAC_RFPATHEN0_SYLODIVRLO02G4EN_disable << 3) /**< Shifted mode disable for RAC_RFPATHEN0 */
+#define RAC_RFPATHEN0_SYLODIVRLO02G4EN_enable (_RAC_RFPATHEN0_SYLODIVRLO02G4EN_enable << 3) /**< Shifted mode enable for RAC_RFPATHEN0 */
+#define RAC_RFPATHEN0_LNAMIXTRSW0 (0x1UL << 6) /**< LNAMIXTRSW0 */
+#define _RAC_RFPATHEN0_LNAMIXTRSW0_SHIFT 6 /**< Shift value for RAC_LNAMIXTRSW0 */
+#define _RAC_RFPATHEN0_LNAMIXTRSW0_MASK 0x40UL /**< Bit mask for RAC_LNAMIXTRSW0 */
+#define _RAC_RFPATHEN0_LNAMIXTRSW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RFPATHEN0 */
+#define _RAC_RFPATHEN0_LNAMIXTRSW0_disabled 0x00000000UL /**< Mode disabled for RAC_RFPATHEN0 */
+#define _RAC_RFPATHEN0_LNAMIXTRSW0_enabled 0x00000001UL /**< Mode enabled for RAC_RFPATHEN0 */
+#define RAC_RFPATHEN0_LNAMIXTRSW0_DEFAULT (_RAC_RFPATHEN0_LNAMIXTRSW0_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_RFPATHEN0 */
+#define RAC_RFPATHEN0_LNAMIXTRSW0_disabled (_RAC_RFPATHEN0_LNAMIXTRSW0_disabled << 6) /**< Shifted mode disabled for RAC_RFPATHEN0 */
+#define RAC_RFPATHEN0_LNAMIXTRSW0_enabled (_RAC_RFPATHEN0_LNAMIXTRSW0_enabled << 6) /**< Shifted mode enabled for RAC_RFPATHEN0 */
+
+/* Bit fields for RAC RFPATHEN1 */
+#define _RAC_RFPATHEN1_RESETVALUE 0x00000002UL /**< Default value for RAC_RFPATHEN1 */
+#define _RAC_RFPATHEN1_MASK 0x0000004FUL /**< Mask for RAC_RFPATHEN1 */
+#define RAC_RFPATHEN1_LNAMIXEN1 (0x1UL << 0) /**< LNAMIXEN1 */
+#define _RAC_RFPATHEN1_LNAMIXEN1_SHIFT 0 /**< Shift value for RAC_LNAMIXEN1 */
+#define _RAC_RFPATHEN1_LNAMIXEN1_MASK 0x1UL /**< Bit mask for RAC_LNAMIXEN1 */
+#define _RAC_RFPATHEN1_LNAMIXEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RFPATHEN1 */
+#define _RAC_RFPATHEN1_LNAMIXEN1_disable 0x00000000UL /**< Mode disable for RAC_RFPATHEN1 */
+#define _RAC_RFPATHEN1_LNAMIXEN1_enable 0x00000001UL /**< Mode enable for RAC_RFPATHEN1 */
+#define RAC_RFPATHEN1_LNAMIXEN1_DEFAULT (_RAC_RFPATHEN1_LNAMIXEN1_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_RFPATHEN1 */
+#define RAC_RFPATHEN1_LNAMIXEN1_disable (_RAC_RFPATHEN1_LNAMIXEN1_disable << 0) /**< Shifted mode disable for RAC_RFPATHEN1 */
+#define RAC_RFPATHEN1_LNAMIXEN1_enable (_RAC_RFPATHEN1_LNAMIXEN1_enable << 0) /**< Shifted mode enable for RAC_RFPATHEN1 */
+#define RAC_RFPATHEN1_LNAMIXRFATTDCEN1 (0x1UL << 1) /**< LNAMIXRFATTDCEN1 */
+#define _RAC_RFPATHEN1_LNAMIXRFATTDCEN1_SHIFT 1 /**< Shift value for RAC_LNAMIXRFATTDCEN1 */
+#define _RAC_RFPATHEN1_LNAMIXRFATTDCEN1_MASK 0x2UL /**< Bit mask for RAC_LNAMIXRFATTDCEN1 */
+#define _RAC_RFPATHEN1_LNAMIXRFATTDCEN1_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_RFPATHEN1 */
+#define _RAC_RFPATHEN1_LNAMIXRFATTDCEN1_disable_dc 0x00000000UL /**< Mode disable_dc for RAC_RFPATHEN1 */
+#define _RAC_RFPATHEN1_LNAMIXRFATTDCEN1_enable_dc 0x00000001UL /**< Mode enable_dc for RAC_RFPATHEN1 */
+#define RAC_RFPATHEN1_LNAMIXRFATTDCEN1_DEFAULT (_RAC_RFPATHEN1_LNAMIXRFATTDCEN1_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_RFPATHEN1 */
+#define RAC_RFPATHEN1_LNAMIXRFATTDCEN1_disable_dc (_RAC_RFPATHEN1_LNAMIXRFATTDCEN1_disable_dc << 1) /**< Shifted mode disable_dc for RAC_RFPATHEN1 */
+#define RAC_RFPATHEN1_LNAMIXRFATTDCEN1_enable_dc (_RAC_RFPATHEN1_LNAMIXRFATTDCEN1_enable_dc << 1) /**< Shifted mode enable_dc for RAC_RFPATHEN1 */
+#define RAC_RFPATHEN1_LNAMIXRFPKDENRF1 (0x1UL << 2) /**< LNAMIXRFPKDENRF1 */
+#define _RAC_RFPATHEN1_LNAMIXRFPKDENRF1_SHIFT 2 /**< Shift value for RAC_LNAMIXRFPKDENRF1 */
+#define _RAC_RFPATHEN1_LNAMIXRFPKDENRF1_MASK 0x4UL /**< Bit mask for RAC_LNAMIXRFPKDENRF1 */
+#define _RAC_RFPATHEN1_LNAMIXRFPKDENRF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RFPATHEN1 */
+#define _RAC_RFPATHEN1_LNAMIXRFPKDENRF1_disable 0x00000000UL /**< Mode disable for RAC_RFPATHEN1 */
+#define _RAC_RFPATHEN1_LNAMIXRFPKDENRF1_enable_path 0x00000001UL /**< Mode enable_path for RAC_RFPATHEN1 */
+#define RAC_RFPATHEN1_LNAMIXRFPKDENRF1_DEFAULT (_RAC_RFPATHEN1_LNAMIXRFPKDENRF1_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_RFPATHEN1 */
+#define RAC_RFPATHEN1_LNAMIXRFPKDENRF1_disable (_RAC_RFPATHEN1_LNAMIXRFPKDENRF1_disable << 2) /**< Shifted mode disable for RAC_RFPATHEN1 */
+#define RAC_RFPATHEN1_LNAMIXRFPKDENRF1_enable_path (_RAC_RFPATHEN1_LNAMIXRFPKDENRF1_enable_path << 2) /**< Shifted mode enable_path for RAC_RFPATHEN1 */
+#define RAC_RFPATHEN1_SYLODIVRLO12G4EN (0x1UL << 3) /**< SYLODIVRLO12G4EN */
+#define _RAC_RFPATHEN1_SYLODIVRLO12G4EN_SHIFT 3 /**< Shift value for RAC_SYLODIVRLO12G4EN */
+#define _RAC_RFPATHEN1_SYLODIVRLO12G4EN_MASK 0x8UL /**< Bit mask for RAC_SYLODIVRLO12G4EN */
+#define _RAC_RFPATHEN1_SYLODIVRLO12G4EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RFPATHEN1 */
+#define _RAC_RFPATHEN1_SYLODIVRLO12G4EN_disable 0x00000000UL /**< Mode disable for RAC_RFPATHEN1 */
+#define _RAC_RFPATHEN1_SYLODIVRLO12G4EN_enable 0x00000001UL /**< Mode enable for RAC_RFPATHEN1 */
+#define RAC_RFPATHEN1_SYLODIVRLO12G4EN_DEFAULT (_RAC_RFPATHEN1_SYLODIVRLO12G4EN_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_RFPATHEN1 */
+#define RAC_RFPATHEN1_SYLODIVRLO12G4EN_disable (_RAC_RFPATHEN1_SYLODIVRLO12G4EN_disable << 3) /**< Shifted mode disable for RAC_RFPATHEN1 */
+#define RAC_RFPATHEN1_SYLODIVRLO12G4EN_enable (_RAC_RFPATHEN1_SYLODIVRLO12G4EN_enable << 3) /**< Shifted mode enable for RAC_RFPATHEN1 */
+#define RAC_RFPATHEN1_LNAMIXTRSW1 (0x1UL << 6) /**< LNAMIXTRSW1 */
+#define _RAC_RFPATHEN1_LNAMIXTRSW1_SHIFT 6 /**< Shift value for RAC_LNAMIXTRSW1 */
+#define _RAC_RFPATHEN1_LNAMIXTRSW1_MASK 0x40UL /**< Bit mask for RAC_LNAMIXTRSW1 */
+#define _RAC_RFPATHEN1_LNAMIXTRSW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RFPATHEN1 */
+#define _RAC_RFPATHEN1_LNAMIXTRSW1_disabled 0x00000000UL /**< Mode disabled for RAC_RFPATHEN1 */
+#define _RAC_RFPATHEN1_LNAMIXTRSW1_enabled 0x00000001UL /**< Mode enabled for RAC_RFPATHEN1 */
+#define RAC_RFPATHEN1_LNAMIXTRSW1_DEFAULT (_RAC_RFPATHEN1_LNAMIXTRSW1_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_RFPATHEN1 */
+#define RAC_RFPATHEN1_LNAMIXTRSW1_disabled (_RAC_RFPATHEN1_LNAMIXTRSW1_disabled << 6) /**< Shifted mode disabled for RAC_RFPATHEN1 */
+#define RAC_RFPATHEN1_LNAMIXTRSW1_enabled (_RAC_RFPATHEN1_LNAMIXTRSW1_enabled << 6) /**< Shifted mode enabled for RAC_RFPATHEN1 */
+
+/* Bit fields for RAC RX */
+#define _RAC_RX_RESETVALUE 0x00000020UL /**< Default value for RAC_RX */
+#define _RAC_RX_MASK 0x000703BFUL /**< Mask for RAC_RX */
+#define RAC_RX_IFADCCAPRESET (0x1UL << 0) /**< IFADCCAPRESET */
+#define _RAC_RX_IFADCCAPRESET_SHIFT 0 /**< Shift value for RAC_IFADCCAPRESET */
+#define _RAC_RX_IFADCCAPRESET_MASK 0x1UL /**< Bit mask for RAC_IFADCCAPRESET */
+#define _RAC_RX_IFADCCAPRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RX */
+#define _RAC_RX_IFADCCAPRESET_cap_reset_disable 0x00000000UL /**< Mode cap_reset_disable for RAC_RX */
+#define _RAC_RX_IFADCCAPRESET_cap_reset_enable 0x00000001UL /**< Mode cap_reset_enable for RAC_RX */
+#define RAC_RX_IFADCCAPRESET_DEFAULT (_RAC_RX_IFADCCAPRESET_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_RX */
+#define RAC_RX_IFADCCAPRESET_cap_reset_disable (_RAC_RX_IFADCCAPRESET_cap_reset_disable << 0) /**< Shifted mode cap_reset_disable for RAC_RX */
+#define RAC_RX_IFADCCAPRESET_cap_reset_enable (_RAC_RX_IFADCCAPRESET_cap_reset_enable << 0) /**< Shifted mode cap_reset_enable for RAC_RX */
+#define RAC_RX_IFADCENLDOSERIES (0x1UL << 1) /**< IFADCENLDOSERIES */
+#define _RAC_RX_IFADCENLDOSERIES_SHIFT 1 /**< Shift value for RAC_IFADCENLDOSERIES */
+#define _RAC_RX_IFADCENLDOSERIES_MASK 0x2UL /**< Bit mask for RAC_IFADCENLDOSERIES */
+#define _RAC_RX_IFADCENLDOSERIES_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RX */
+#define _RAC_RX_IFADCENLDOSERIES_series_ldo_disable 0x00000000UL /**< Mode series_ldo_disable for RAC_RX */
+#define _RAC_RX_IFADCENLDOSERIES_series_ldo_enable 0x00000001UL /**< Mode series_ldo_enable for RAC_RX */
+#define RAC_RX_IFADCENLDOSERIES_DEFAULT (_RAC_RX_IFADCENLDOSERIES_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_RX */
+#define RAC_RX_IFADCENLDOSERIES_series_ldo_disable (_RAC_RX_IFADCENLDOSERIES_series_ldo_disable << 1) /**< Shifted mode series_ldo_disable for RAC_RX */
+#define RAC_RX_IFADCENLDOSERIES_series_ldo_enable (_RAC_RX_IFADCENLDOSERIES_series_ldo_enable << 1) /**< Shifted mode series_ldo_enable for RAC_RX */
+#define RAC_RX_IFADCENLDOSHUNT (0x1UL << 2) /**< IFADCENLDOSHUNT */
+#define _RAC_RX_IFADCENLDOSHUNT_SHIFT 2 /**< Shift value for RAC_IFADCENLDOSHUNT */
+#define _RAC_RX_IFADCENLDOSHUNT_MASK 0x4UL /**< Bit mask for RAC_IFADCENLDOSHUNT */
+#define _RAC_RX_IFADCENLDOSHUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RX */
+#define _RAC_RX_IFADCENLDOSHUNT_shunt_ldo_disable 0x00000000UL /**< Mode shunt_ldo_disable for RAC_RX */
+#define _RAC_RX_IFADCENLDOSHUNT_shunt_ldo_enable 0x00000001UL /**< Mode shunt_ldo_enable for RAC_RX */
+#define RAC_RX_IFADCENLDOSHUNT_DEFAULT (_RAC_RX_IFADCENLDOSHUNT_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_RX */
+#define RAC_RX_IFADCENLDOSHUNT_shunt_ldo_disable (_RAC_RX_IFADCENLDOSHUNT_shunt_ldo_disable << 2) /**< Shifted mode shunt_ldo_disable for RAC_RX */
+#define RAC_RX_IFADCENLDOSHUNT_shunt_ldo_enable (_RAC_RX_IFADCENLDOSHUNT_shunt_ldo_enable << 2) /**< Shifted mode shunt_ldo_enable for RAC_RX */
+#define RAC_RX_LNAMIXENRFPKD (0x1UL << 3) /**< LNAMIXENRFPKD */
+#define _RAC_RX_LNAMIXENRFPKD_SHIFT 3 /**< Shift value for RAC_LNAMIXENRFPKD */
+#define _RAC_RX_LNAMIXENRFPKD_MASK 0x8UL /**< Bit mask for RAC_LNAMIXENRFPKD */
+#define _RAC_RX_LNAMIXENRFPKD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RX */
+#define _RAC_RX_LNAMIXENRFPKD_disable 0x00000000UL /**< Mode disable for RAC_RX */
+#define _RAC_RX_LNAMIXENRFPKD_enable 0x00000001UL /**< Mode enable for RAC_RX */
+#define RAC_RX_LNAMIXENRFPKD_DEFAULT (_RAC_RX_LNAMIXENRFPKD_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_RX */
+#define RAC_RX_LNAMIXENRFPKD_disable (_RAC_RX_LNAMIXENRFPKD_disable << 3) /**< Shifted mode disable for RAC_RX */
+#define RAC_RX_LNAMIXENRFPKD_enable (_RAC_RX_LNAMIXENRFPKD_enable << 3) /**< Shifted mode enable for RAC_RX */
+#define RAC_RX_LNAMIXENRFPKDLOTHRESH (0x1UL << 4) /**< LNAMIXENRFPKDLOTHRESH */
+#define _RAC_RX_LNAMIXENRFPKDLOTHRESH_SHIFT 4 /**< Shift value for RAC_LNAMIXENRFPKDLOTHRESH */
+#define _RAC_RX_LNAMIXENRFPKDLOTHRESH_MASK 0x10UL /**< Bit mask for RAC_LNAMIXENRFPKDLOTHRESH */
+#define _RAC_RX_LNAMIXENRFPKDLOTHRESH_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RX */
+#define _RAC_RX_LNAMIXENRFPKDLOTHRESH_disable 0x00000000UL /**< Mode disable for RAC_RX */
+#define _RAC_RX_LNAMIXENRFPKDLOTHRESH_enable 0x00000001UL /**< Mode enable for RAC_RX */
+#define RAC_RX_LNAMIXENRFPKDLOTHRESH_DEFAULT (_RAC_RX_LNAMIXENRFPKDLOTHRESH_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_RX */
+#define RAC_RX_LNAMIXENRFPKDLOTHRESH_disable (_RAC_RX_LNAMIXENRFPKDLOTHRESH_disable << 4) /**< Shifted mode disable for RAC_RX */
+#define RAC_RX_LNAMIXENRFPKDLOTHRESH_enable (_RAC_RX_LNAMIXENRFPKDLOTHRESH_enable << 4) /**< Shifted mode enable for RAC_RX */
+#define RAC_RX_LNAMIXLDOLOWCUR (0x1UL << 5) /**< LNAMIXLDOLOWCUR */
+#define _RAC_RX_LNAMIXLDOLOWCUR_SHIFT 5 /**< Shift value for RAC_LNAMIXLDOLOWCUR */
+#define _RAC_RX_LNAMIXLDOLOWCUR_MASK 0x20UL /**< Bit mask for RAC_LNAMIXLDOLOWCUR */
+#define _RAC_RX_LNAMIXLDOLOWCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_RX */
+#define _RAC_RX_LNAMIXLDOLOWCUR_regular_mode 0x00000000UL /**< Mode regular_mode for RAC_RX */
+#define _RAC_RX_LNAMIXLDOLOWCUR_low_current_mode 0x00000001UL /**< Mode low_current_mode for RAC_RX */
+#define RAC_RX_LNAMIXLDOLOWCUR_DEFAULT (_RAC_RX_LNAMIXLDOLOWCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_RX */
+#define RAC_RX_LNAMIXLDOLOWCUR_regular_mode (_RAC_RX_LNAMIXLDOLOWCUR_regular_mode << 5) /**< Shifted mode regular_mode for RAC_RX */
+#define RAC_RX_LNAMIXLDOLOWCUR_low_current_mode (_RAC_RX_LNAMIXLDOLOWCUR_low_current_mode << 5) /**< Shifted mode low_current_mode for RAC_RX */
+#define RAC_RX_LNAMIXREGLOADEN (0x1UL << 7) /**< LNAMIXREGLOADEN */
+#define _RAC_RX_LNAMIXREGLOADEN_SHIFT 7 /**< Shift value for RAC_LNAMIXREGLOADEN */
+#define _RAC_RX_LNAMIXREGLOADEN_MASK 0x80UL /**< Bit mask for RAC_LNAMIXREGLOADEN */
+#define _RAC_RX_LNAMIXREGLOADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RX */
+#define _RAC_RX_LNAMIXREGLOADEN_disable_resistor 0x00000000UL /**< Mode disable_resistor for RAC_RX */
+#define _RAC_RX_LNAMIXREGLOADEN_enable_resistor 0x00000001UL /**< Mode enable_resistor for RAC_RX */
+#define RAC_RX_LNAMIXREGLOADEN_DEFAULT (_RAC_RX_LNAMIXREGLOADEN_DEFAULT << 7) /**< Shifted mode DEFAULT for RAC_RX */
+#define RAC_RX_LNAMIXREGLOADEN_disable_resistor (_RAC_RX_LNAMIXREGLOADEN_disable_resistor << 7) /**< Shifted mode disable_resistor for RAC_RX */
+#define RAC_RX_LNAMIXREGLOADEN_enable_resistor (_RAC_RX_LNAMIXREGLOADEN_enable_resistor << 7) /**< Shifted mode enable_resistor for RAC_RX */
+#define RAC_RX_PGAENLDO (0x1UL << 8) /**< PGAENLDO */
+#define _RAC_RX_PGAENLDO_SHIFT 8 /**< Shift value for RAC_PGAENLDO */
+#define _RAC_RX_PGAENLDO_MASK 0x100UL /**< Bit mask for RAC_PGAENLDO */
+#define _RAC_RX_PGAENLDO_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RX */
+#define _RAC_RX_PGAENLDO_disable_ldo 0x00000000UL /**< Mode disable_ldo for RAC_RX */
+#define _RAC_RX_PGAENLDO_enable_ldo 0x00000001UL /**< Mode enable_ldo for RAC_RX */
+#define RAC_RX_PGAENLDO_DEFAULT (_RAC_RX_PGAENLDO_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_RX */
+#define RAC_RX_PGAENLDO_disable_ldo (_RAC_RX_PGAENLDO_disable_ldo << 8) /**< Shifted mode disable_ldo for RAC_RX */
+#define RAC_RX_PGAENLDO_enable_ldo (_RAC_RX_PGAENLDO_enable_ldo << 8) /**< Shifted mode enable_ldo for RAC_RX */
+#define RAC_RX_SYCHPQNC3EN (0x1UL << 9) /**< SYCHPQNC3EN */
+#define _RAC_RX_SYCHPQNC3EN_SHIFT 9 /**< Shift value for RAC_SYCHPQNC3EN */
+#define _RAC_RX_SYCHPQNC3EN_MASK 0x200UL /**< Bit mask for RAC_SYCHPQNC3EN */
+#define _RAC_RX_SYCHPQNC3EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RX */
+#define _RAC_RX_SYCHPQNC3EN_qnc_2 0x00000000UL /**< Mode qnc_2 for RAC_RX */
+#define _RAC_RX_SYCHPQNC3EN_qnc_3 0x00000001UL /**< Mode qnc_3 for RAC_RX */
+#define RAC_RX_SYCHPQNC3EN_DEFAULT (_RAC_RX_SYCHPQNC3EN_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_RX */
+#define RAC_RX_SYCHPQNC3EN_qnc_2 (_RAC_RX_SYCHPQNC3EN_qnc_2 << 9) /**< Shifted mode qnc_2 for RAC_RX */
+#define RAC_RX_SYCHPQNC3EN_qnc_3 (_RAC_RX_SYCHPQNC3EN_qnc_3 << 9) /**< Shifted mode qnc_3 for RAC_RX */
+#define RAC_RX_SYCHPBIASTRIMBUFRX (0x1UL << 16) /**< SYCHPBIASTRIMBUFRX */
+#define _RAC_RX_SYCHPBIASTRIMBUFRX_SHIFT 16 /**< Shift value for RAC_SYCHPBIASTRIMBUFRX */
+#define _RAC_RX_SYCHPBIASTRIMBUFRX_MASK 0x10000UL /**< Bit mask for RAC_SYCHPBIASTRIMBUFRX */
+#define _RAC_RX_SYCHPBIASTRIMBUFRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RX */
+#define _RAC_RX_SYCHPBIASTRIMBUFRX_i_tail_10u 0x00000000UL /**< Mode i_tail_10u for RAC_RX */
+#define _RAC_RX_SYCHPBIASTRIMBUFRX_i_tail_20u 0x00000001UL /**< Mode i_tail_20u for RAC_RX */
+#define RAC_RX_SYCHPBIASTRIMBUFRX_DEFAULT (_RAC_RX_SYCHPBIASTRIMBUFRX_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_RX */
+#define RAC_RX_SYCHPBIASTRIMBUFRX_i_tail_10u (_RAC_RX_SYCHPBIASTRIMBUFRX_i_tail_10u << 16) /**< Shifted mode i_tail_10u for RAC_RX */
+#define RAC_RX_SYCHPBIASTRIMBUFRX_i_tail_20u (_RAC_RX_SYCHPBIASTRIMBUFRX_i_tail_20u << 16) /**< Shifted mode i_tail_20u for RAC_RX */
+#define RAC_RX_SYPFDCHPLPENRX (0x1UL << 17) /**< SYPFDCHPLPENRX */
+#define _RAC_RX_SYPFDCHPLPENRX_SHIFT 17 /**< Shift value for RAC_SYPFDCHPLPENRX */
+#define _RAC_RX_SYPFDCHPLPENRX_MASK 0x20000UL /**< Bit mask for RAC_SYPFDCHPLPENRX */
+#define _RAC_RX_SYPFDCHPLPENRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RX */
+#define _RAC_RX_SYPFDCHPLPENRX_disable 0x00000000UL /**< Mode disable for RAC_RX */
+#define _RAC_RX_SYPFDCHPLPENRX_enable 0x00000001UL /**< Mode enable for RAC_RX */
+#define RAC_RX_SYPFDCHPLPENRX_DEFAULT (_RAC_RX_SYPFDCHPLPENRX_DEFAULT << 17) /**< Shifted mode DEFAULT for RAC_RX */
+#define RAC_RX_SYPFDCHPLPENRX_disable (_RAC_RX_SYPFDCHPLPENRX_disable << 17) /**< Shifted mode disable for RAC_RX */
+#define RAC_RX_SYPFDCHPLPENRX_enable (_RAC_RX_SYPFDCHPLPENRX_enable << 17) /**< Shifted mode enable for RAC_RX */
+#define RAC_RX_SYPFDFPWENRX (0x1UL << 18) /**< SYPFDFPWENRX */
+#define _RAC_RX_SYPFDFPWENRX_SHIFT 18 /**< Shift value for RAC_SYPFDFPWENRX */
+#define _RAC_RX_SYPFDFPWENRX_MASK 0x40000UL /**< Bit mask for RAC_SYPFDFPWENRX */
+#define _RAC_RX_SYPFDFPWENRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_RX */
+#define _RAC_RX_SYPFDFPWENRX_disable 0x00000000UL /**< Mode disable for RAC_RX */
+#define _RAC_RX_SYPFDFPWENRX_enable 0x00000001UL /**< Mode enable for RAC_RX */
+#define RAC_RX_SYPFDFPWENRX_DEFAULT (_RAC_RX_SYPFDFPWENRX_DEFAULT << 18) /**< Shifted mode DEFAULT for RAC_RX */
+#define RAC_RX_SYPFDFPWENRX_disable (_RAC_RX_SYPFDFPWENRX_disable << 18) /**< Shifted mode disable for RAC_RX */
+#define RAC_RX_SYPFDFPWENRX_enable (_RAC_RX_SYPFDFPWENRX_enable << 18) /**< Shifted mode enable for RAC_RX */
+
+/* Bit fields for RAC TX */
+#define _RAC_TX_RESETVALUE 0x00000000UL /**< Default value for RAC_TX */
+#define _RAC_TX_MASK 0xFFFFF7EFUL /**< Mask for RAC_TX */
+#define RAC_TX_TXPAENREG (0x1UL << 0) /**< TXPAENREG */
+#define _RAC_TX_TXPAENREG_SHIFT 0 /**< Shift value for RAC_TXPAENREG */
+#define _RAC_TX_TXPAENREG_MASK 0x1UL /**< Bit mask for RAC_TXPAENREG */
+#define _RAC_TX_TXPAENREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */
+#define _RAC_TX_TXPAENREG_disable 0x00000000UL /**< Mode disable for RAC_TX */
+#define _RAC_TX_TXPAENREG_enable 0x00000001UL /**< Mode enable for RAC_TX */
+#define RAC_TX_TXPAENREG_DEFAULT (_RAC_TX_TXPAENREG_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_TX */
+#define RAC_TX_TXPAENREG_disable (_RAC_TX_TXPAENREG_disable << 0) /**< Shifted mode disable for RAC_TX */
+#define RAC_TX_TXPAENREG_enable (_RAC_TX_TXPAENREG_enable << 0) /**< Shifted mode enable for RAC_TX */
+#define RAC_TX_TXPAENRAMPCLK (0x1UL << 1) /**< TXPAENRAMPCLK */
+#define _RAC_TX_TXPAENRAMPCLK_SHIFT 1 /**< Shift value for RAC_TXPAENRAMPCLK */
+#define _RAC_TX_TXPAENRAMPCLK_MASK 0x2UL /**< Bit mask for RAC_TXPAENRAMPCLK */
+#define _RAC_TX_TXPAENRAMPCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */
+#define _RAC_TX_TXPAENRAMPCLK_silence_clk 0x00000000UL /**< Mode silence_clk for RAC_TX */
+#define _RAC_TX_TXPAENRAMPCLK_en_clk 0x00000001UL /**< Mode en_clk for RAC_TX */
+#define RAC_TX_TXPAENRAMPCLK_DEFAULT (_RAC_TX_TXPAENRAMPCLK_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_TX */
+#define RAC_TX_TXPAENRAMPCLK_silence_clk (_RAC_TX_TXPAENRAMPCLK_silence_clk << 1) /**< Shifted mode silence_clk for RAC_TX */
+#define RAC_TX_TXPAENRAMPCLK_en_clk (_RAC_TX_TXPAENRAMPCLK_en_clk << 1) /**< Shifted mode en_clk for RAC_TX */
+#define RAC_TX_TX0DBMENBLEEDREG (0x1UL << 2) /**< TX0DBMENBLEEDREG */
+#define _RAC_TX_TX0DBMENBLEEDREG_SHIFT 2 /**< Shift value for RAC_TX0DBMENBLEEDREG */
+#define _RAC_TX_TX0DBMENBLEEDREG_MASK 0x4UL /**< Bit mask for RAC_TX0DBMENBLEEDREG */
+#define _RAC_TX_TX0DBMENBLEEDREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */
+#define _RAC_TX_TX0DBMENBLEEDREG_disable 0x00000000UL /**< Mode disable for RAC_TX */
+#define _RAC_TX_TX0DBMENBLEEDREG_enable 0x00000001UL /**< Mode enable for RAC_TX */
+#define RAC_TX_TX0DBMENBLEEDREG_DEFAULT (_RAC_TX_TX0DBMENBLEEDREG_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_TX */
+#define RAC_TX_TX0DBMENBLEEDREG_disable (_RAC_TX_TX0DBMENBLEEDREG_disable << 2) /**< Shifted mode disable for RAC_TX */
+#define RAC_TX_TX0DBMENBLEEDREG_enable (_RAC_TX_TX0DBMENBLEEDREG_enable << 2) /**< Shifted mode enable for RAC_TX */
+#define RAC_TX_TX0DBMENREG (0x1UL << 3) /**< TX0DBMENREG */
+#define _RAC_TX_TX0DBMENREG_SHIFT 3 /**< Shift value for RAC_TX0DBMENREG */
+#define _RAC_TX_TX0DBMENREG_MASK 0x8UL /**< Bit mask for RAC_TX0DBMENREG */
+#define _RAC_TX_TX0DBMENREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */
+#define _RAC_TX_TX0DBMENREG_disable 0x00000000UL /**< Mode disable for RAC_TX */
+#define _RAC_TX_TX0DBMENREG_enable 0x00000001UL /**< Mode enable for RAC_TX */
+#define RAC_TX_TX0DBMENREG_DEFAULT (_RAC_TX_TX0DBMENREG_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_TX */
+#define RAC_TX_TX0DBMENREG_disable (_RAC_TX_TX0DBMENREG_disable << 3) /**< Shifted mode disable for RAC_TX */
+#define RAC_TX_TX0DBMENREG_enable (_RAC_TX_TX0DBMENREG_enable << 3) /**< Shifted mode enable for RAC_TX */
+#define RAC_TX_TX0DBMENBIAS (0x1UL << 5) /**< TX0DBMENBIAS */
+#define _RAC_TX_TX0DBMENBIAS_SHIFT 5 /**< Shift value for RAC_TX0DBMENBIAS */
+#define _RAC_TX_TX0DBMENBIAS_MASK 0x20UL /**< Bit mask for RAC_TX0DBMENBIAS */
+#define _RAC_TX_TX0DBMENBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */
+#define _RAC_TX_TX0DBMENBIAS_disable 0x00000000UL /**< Mode disable for RAC_TX */
+#define _RAC_TX_TX0DBMENBIAS_enable 0x00000001UL /**< Mode enable for RAC_TX */
+#define RAC_TX_TX0DBMENBIAS_DEFAULT (_RAC_TX_TX0DBMENBIAS_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_TX */
+#define RAC_TX_TX0DBMENBIAS_disable (_RAC_TX_TX0DBMENBIAS_disable << 5) /**< Shifted mode disable for RAC_TX */
+#define RAC_TX_TX0DBMENBIAS_enable (_RAC_TX_TX0DBMENBIAS_enable << 5) /**< Shifted mode enable for RAC_TX */
+#define RAC_TX_TX0DBMENPREDRV (0x1UL << 6) /**< TX0DBMENPREDRV */
+#define _RAC_TX_TX0DBMENPREDRV_SHIFT 6 /**< Shift value for RAC_TX0DBMENPREDRV */
+#define _RAC_TX_TX0DBMENPREDRV_MASK 0x40UL /**< Bit mask for RAC_TX0DBMENPREDRV */
+#define _RAC_TX_TX0DBMENPREDRV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */
+#define _RAC_TX_TX0DBMENPREDRV_disable 0x00000000UL /**< Mode disable for RAC_TX */
+#define _RAC_TX_TX0DBMENPREDRV_enable 0x00000001UL /**< Mode enable for RAC_TX */
+#define RAC_TX_TX0DBMENPREDRV_DEFAULT (_RAC_TX_TX0DBMENPREDRV_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_TX */
+#define RAC_TX_TX0DBMENPREDRV_disable (_RAC_TX_TX0DBMENPREDRV_disable << 6) /**< Shifted mode disable for RAC_TX */
+#define RAC_TX_TX0DBMENPREDRV_enable (_RAC_TX_TX0DBMENPREDRV_enable << 6) /**< Shifted mode enable for RAC_TX */
+#define RAC_TX_TX0DBMENPREDRVREG (0x1UL << 7) /**< TX0DBMENPREDRVREG */
+#define _RAC_TX_TX0DBMENPREDRVREG_SHIFT 7 /**< Shift value for RAC_TX0DBMENPREDRVREG */
+#define _RAC_TX_TX0DBMENPREDRVREG_MASK 0x80UL /**< Bit mask for RAC_TX0DBMENPREDRVREG */
+#define _RAC_TX_TX0DBMENPREDRVREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */
+#define _RAC_TX_TX0DBMENPREDRVREG_disable 0x00000000UL /**< Mode disable for RAC_TX */
+#define _RAC_TX_TX0DBMENPREDRVREG_enable 0x00000001UL /**< Mode enable for RAC_TX */
+#define RAC_TX_TX0DBMENPREDRVREG_DEFAULT (_RAC_TX_TX0DBMENPREDRVREG_DEFAULT << 7) /**< Shifted mode DEFAULT for RAC_TX */
+#define RAC_TX_TX0DBMENPREDRVREG_disable (_RAC_TX_TX0DBMENPREDRVREG_disable << 7) /**< Shifted mode disable for RAC_TX */
+#define RAC_TX_TX0DBMENPREDRVREG_enable (_RAC_TX_TX0DBMENPREDRVREG_enable << 7) /**< Shifted mode enable for RAC_TX */
+#define RAC_TX_TX0DBMENPREDRVREGBIAS (0x1UL << 8) /**< TX0DBMENPREDRVREGBIAS */
+#define _RAC_TX_TX0DBMENPREDRVREGBIAS_SHIFT 8 /**< Shift value for RAC_TX0DBMENPREDRVREGBIAS */
+#define _RAC_TX_TX0DBMENPREDRVREGBIAS_MASK 0x100UL /**< Bit mask for RAC_TX0DBMENPREDRVREGBIAS */
+#define _RAC_TX_TX0DBMENPREDRVREGBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */
+#define _RAC_TX_TX0DBMENPREDRVREGBIAS_disable 0x00000000UL /**< Mode disable for RAC_TX */
+#define _RAC_TX_TX0DBMENPREDRVREGBIAS_enable 0x00000001UL /**< Mode enable for RAC_TX */
+#define RAC_TX_TX0DBMENPREDRVREGBIAS_DEFAULT (_RAC_TX_TX0DBMENPREDRVREGBIAS_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_TX */
+#define RAC_TX_TX0DBMENPREDRVREGBIAS_disable (_RAC_TX_TX0DBMENPREDRVREGBIAS_disable << 8) /**< Shifted mode disable for RAC_TX */
+#define RAC_TX_TX0DBMENPREDRVREGBIAS_enable (_RAC_TX_TX0DBMENPREDRVREGBIAS_enable << 8) /**< Shifted mode enable for RAC_TX */
+#define RAC_TX_TX0DBMENRAMPCLK (0x1UL << 9) /**< TX0DBMENRAMPCLK */
+#define _RAC_TX_TX0DBMENRAMPCLK_SHIFT 9 /**< Shift value for RAC_TX0DBMENRAMPCLK */
+#define _RAC_TX_TX0DBMENRAMPCLK_MASK 0x200UL /**< Bit mask for RAC_TX0DBMENRAMPCLK */
+#define _RAC_TX_TX0DBMENRAMPCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */
+#define _RAC_TX_TX0DBMENRAMPCLK_disable 0x00000000UL /**< Mode disable for RAC_TX */
+#define _RAC_TX_TX0DBMENRAMPCLK_enable 0x00000001UL /**< Mode enable for RAC_TX */
+#define RAC_TX_TX0DBMENRAMPCLK_DEFAULT (_RAC_TX_TX0DBMENRAMPCLK_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_TX */
+#define RAC_TX_TX0DBMENRAMPCLK_disable (_RAC_TX_TX0DBMENRAMPCLK_disable << 9) /**< Shifted mode disable for RAC_TX */
+#define RAC_TX_TX0DBMENRAMPCLK_enable (_RAC_TX_TX0DBMENRAMPCLK_enable << 9) /**< Shifted mode enable for RAC_TX */
+#define RAC_TX_TX0DBMENBLEEDPREDRVREG (0x1UL << 10) /**< TX0DBMENBLEEDPREDRVREG */
+#define _RAC_TX_TX0DBMENBLEEDPREDRVREG_SHIFT 10 /**< Shift value for RAC_TX0DBMENBLEEDPREDRVREG */
+#define _RAC_TX_TX0DBMENBLEEDPREDRVREG_MASK 0x400UL /**< Bit mask for RAC_TX0DBMENBLEEDPREDRVREG */
+#define _RAC_TX_TX0DBMENBLEEDPREDRVREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */
+#define _RAC_TX_TX0DBMENBLEEDPREDRVREG_disable 0x00000000UL /**< Mode disable for RAC_TX */
+#define _RAC_TX_TX0DBMENBLEEDPREDRVREG_enable 0x00000001UL /**< Mode enable for RAC_TX */
+#define RAC_TX_TX0DBMENBLEEDPREDRVREG_DEFAULT (_RAC_TX_TX0DBMENBLEEDPREDRVREG_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_TX */
+#define RAC_TX_TX0DBMENBLEEDPREDRVREG_disable (_RAC_TX_TX0DBMENBLEEDPREDRVREG_disable << 10) /**< Shifted mode disable for RAC_TX */
+#define RAC_TX_TX0DBMENBLEEDPREDRVREG_enable (_RAC_TX_TX0DBMENBLEEDPREDRVREG_enable << 10) /**< Shifted mode enable for RAC_TX */
+#define RAC_TX_TXPAENBLEEDPREDRVREG (0x1UL << 12) /**< TXPAENBLEEDPREDRVREG */
+#define _RAC_TX_TXPAENBLEEDPREDRVREG_SHIFT 12 /**< Shift value for RAC_TXPAENBLEEDPREDRVREG */
+#define _RAC_TX_TXPAENBLEEDPREDRVREG_MASK 0x1000UL /**< Bit mask for RAC_TXPAENBLEEDPREDRVREG */
+#define _RAC_TX_TXPAENBLEEDPREDRVREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */
+#define _RAC_TX_TXPAENBLEEDPREDRVREG_disable 0x00000000UL /**< Mode disable for RAC_TX */
+#define _RAC_TX_TXPAENBLEEDPREDRVREG_enable 0x00000001UL /**< Mode enable for RAC_TX */
+#define RAC_TX_TXPAENBLEEDPREDRVREG_DEFAULT (_RAC_TX_TXPAENBLEEDPREDRVREG_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_TX */
+#define RAC_TX_TXPAENBLEEDPREDRVREG_disable (_RAC_TX_TXPAENBLEEDPREDRVREG_disable << 12) /**< Shifted mode disable for RAC_TX */
+#define RAC_TX_TXPAENBLEEDPREDRVREG_enable (_RAC_TX_TXPAENBLEEDPREDRVREG_enable << 12) /**< Shifted mode enable for RAC_TX */
+#define RAC_TX_TXPAENBLEEDREG (0x1UL << 13) /**< TXPAENBLEEDREG */
+#define _RAC_TX_TXPAENBLEEDREG_SHIFT 13 /**< Shift value for RAC_TXPAENBLEEDREG */
+#define _RAC_TX_TXPAENBLEEDREG_MASK 0x2000UL /**< Bit mask for RAC_TXPAENBLEEDREG */
+#define _RAC_TX_TXPAENBLEEDREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */
+#define _RAC_TX_TXPAENBLEEDREG_disable 0x00000000UL /**< Mode disable for RAC_TX */
+#define _RAC_TX_TXPAENBLEEDREG_enable 0x00000001UL /**< Mode enable for RAC_TX */
+#define RAC_TX_TXPAENBLEEDREG_DEFAULT (_RAC_TX_TXPAENBLEEDREG_DEFAULT << 13) /**< Shifted mode DEFAULT for RAC_TX */
+#define RAC_TX_TXPAENBLEEDREG_disable (_RAC_TX_TXPAENBLEEDREG_disable << 13) /**< Shifted mode disable for RAC_TX */
+#define RAC_TX_TXPAENBLEEDREG_enable (_RAC_TX_TXPAENBLEEDREG_enable << 13) /**< Shifted mode enable for RAC_TX */
+#define RAC_TX_TXPAENPAOUT (0x1UL << 14) /**< TXPAENPAOUT */
+#define _RAC_TX_TXPAENPAOUT_SHIFT 14 /**< Shift value for RAC_TXPAENPAOUT */
+#define _RAC_TX_TXPAENPAOUT_MASK 0x4000UL /**< Bit mask for RAC_TXPAENPAOUT */
+#define _RAC_TX_TXPAENPAOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */
+#define _RAC_TX_TXPAENPAOUT_disable 0x00000000UL /**< Mode disable for RAC_TX */
+#define _RAC_TX_TXPAENPAOUT_enable 0x00000001UL /**< Mode enable for RAC_TX */
+#define RAC_TX_TXPAENPAOUT_DEFAULT (_RAC_TX_TXPAENPAOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for RAC_TX */
+#define RAC_TX_TXPAENPAOUT_disable (_RAC_TX_TXPAENPAOUT_disable << 14) /**< Shifted mode disable for RAC_TX */
+#define RAC_TX_TXPAENPAOUT_enable (_RAC_TX_TXPAENPAOUT_enable << 14) /**< Shifted mode enable for RAC_TX */
+#define RAC_TX_TXPAENPREDRVREG (0x1UL << 15) /**< TXPAENPREDRVREG */
+#define _RAC_TX_TXPAENPREDRVREG_SHIFT 15 /**< Shift value for RAC_TXPAENPREDRVREG */
+#define _RAC_TX_TXPAENPREDRVREG_MASK 0x8000UL /**< Bit mask for RAC_TXPAENPREDRVREG */
+#define _RAC_TX_TXPAENPREDRVREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */
+#define _RAC_TX_TXPAENPREDRVREG_disable 0x00000000UL /**< Mode disable for RAC_TX */
+#define _RAC_TX_TXPAENPREDRVREG_enable 0x00000001UL /**< Mode enable for RAC_TX */
+#define RAC_TX_TXPAENPREDRVREG_DEFAULT (_RAC_TX_TXPAENPREDRVREG_DEFAULT << 15) /**< Shifted mode DEFAULT for RAC_TX */
+#define RAC_TX_TXPAENPREDRVREG_disable (_RAC_TX_TXPAENPREDRVREG_disable << 15) /**< Shifted mode disable for RAC_TX */
+#define RAC_TX_TXPAENPREDRVREG_enable (_RAC_TX_TXPAENPREDRVREG_enable << 15) /**< Shifted mode enable for RAC_TX */
+#define RAC_TX_SYCHPBIASTRIMBUFTX (0x1UL << 16) /**< SYCHPBIASTRIMBUFTX */
+#define _RAC_TX_SYCHPBIASTRIMBUFTX_SHIFT 16 /**< Shift value for RAC_SYCHPBIASTRIMBUFTX */
+#define _RAC_TX_SYCHPBIASTRIMBUFTX_MASK 0x10000UL /**< Bit mask for RAC_SYCHPBIASTRIMBUFTX */
+#define _RAC_TX_SYCHPBIASTRIMBUFTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */
+#define _RAC_TX_SYCHPBIASTRIMBUFTX_i_tail_10u 0x00000000UL /**< Mode i_tail_10u for RAC_TX */
+#define _RAC_TX_SYCHPBIASTRIMBUFTX_i_tail_20u 0x00000001UL /**< Mode i_tail_20u for RAC_TX */
+#define RAC_TX_SYCHPBIASTRIMBUFTX_DEFAULT (_RAC_TX_SYCHPBIASTRIMBUFTX_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_TX */
+#define RAC_TX_SYCHPBIASTRIMBUFTX_i_tail_10u (_RAC_TX_SYCHPBIASTRIMBUFTX_i_tail_10u << 16) /**< Shifted mode i_tail_10u for RAC_TX */
+#define RAC_TX_SYCHPBIASTRIMBUFTX_i_tail_20u (_RAC_TX_SYCHPBIASTRIMBUFTX_i_tail_20u << 16) /**< Shifted mode i_tail_20u for RAC_TX */
+#define RAC_TX_SYPFDCHPLPENTX (0x1UL << 17) /**< SYPFDCHPLPENTX */
+#define _RAC_TX_SYPFDCHPLPENTX_SHIFT 17 /**< Shift value for RAC_SYPFDCHPLPENTX */
+#define _RAC_TX_SYPFDCHPLPENTX_MASK 0x20000UL /**< Bit mask for RAC_SYPFDCHPLPENTX */
+#define _RAC_TX_SYPFDCHPLPENTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */
+#define _RAC_TX_SYPFDCHPLPENTX_disable 0x00000000UL /**< Mode disable for RAC_TX */
+#define _RAC_TX_SYPFDCHPLPENTX_enable 0x00000001UL /**< Mode enable for RAC_TX */
+#define RAC_TX_SYPFDCHPLPENTX_DEFAULT (_RAC_TX_SYPFDCHPLPENTX_DEFAULT << 17) /**< Shifted mode DEFAULT for RAC_TX */
+#define RAC_TX_SYPFDCHPLPENTX_disable (_RAC_TX_SYPFDCHPLPENTX_disable << 17) /**< Shifted mode disable for RAC_TX */
+#define RAC_TX_SYPFDCHPLPENTX_enable (_RAC_TX_SYPFDCHPLPENTX_enable << 17) /**< Shifted mode enable for RAC_TX */
+#define RAC_TX_SYPFDFPWENTX (0x1UL << 18) /**< SYPFDFPWENTX */
+#define _RAC_TX_SYPFDFPWENTX_SHIFT 18 /**< Shift value for RAC_SYPFDFPWENTX */
+#define _RAC_TX_SYPFDFPWENTX_MASK 0x40000UL /**< Bit mask for RAC_SYPFDFPWENTX */
+#define _RAC_TX_SYPFDFPWENTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */
+#define _RAC_TX_SYPFDFPWENTX_disable 0x00000000UL /**< Mode disable for RAC_TX */
+#define _RAC_TX_SYPFDFPWENTX_enable 0x00000001UL /**< Mode enable for RAC_TX */
+#define RAC_TX_SYPFDFPWENTX_DEFAULT (_RAC_TX_SYPFDFPWENTX_DEFAULT << 18) /**< Shifted mode DEFAULT for RAC_TX */
+#define RAC_TX_SYPFDFPWENTX_disable (_RAC_TX_SYPFDFPWENTX_disable << 18) /**< Shifted mode disable for RAC_TX */
+#define RAC_TX_SYPFDFPWENTX_enable (_RAC_TX_SYPFDFPWENTX_enable << 18) /**< Shifted mode enable for RAC_TX */
+#define RAC_TX_TXPAEN10DBM (0x1UL << 19) /**< TXPAEN10DBM */
+#define _RAC_TX_TXPAEN10DBM_SHIFT 19 /**< Shift value for RAC_TXPAEN10DBM */
+#define _RAC_TX_TXPAEN10DBM_MASK 0x80000UL /**< Bit mask for RAC_TXPAEN10DBM */
+#define _RAC_TX_TXPAEN10DBM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */
+#define _RAC_TX_TXPAEN10DBM_disable 0x00000000UL /**< Mode disable for RAC_TX */
+#define _RAC_TX_TXPAEN10DBM_enable 0x00000001UL /**< Mode enable for RAC_TX */
+#define RAC_TX_TXPAEN10DBM_DEFAULT (_RAC_TX_TXPAEN10DBM_DEFAULT << 19) /**< Shifted mode DEFAULT for RAC_TX */
+#define RAC_TX_TXPAEN10DBM_disable (_RAC_TX_TXPAEN10DBM_disable << 19) /**< Shifted mode disable for RAC_TX */
+#define RAC_TX_TXPAEN10DBM_enable (_RAC_TX_TXPAEN10DBM_enable << 19) /**< Shifted mode enable for RAC_TX */
+#define RAC_TX_TXPAEN10DBMMAINCTAP (0x1UL << 20) /**< TXPAEN10DBMMAINCTAP */
+#define _RAC_TX_TXPAEN10DBMMAINCTAP_SHIFT 20 /**< Shift value for RAC_TXPAEN10DBMMAINCTAP */
+#define _RAC_TX_TXPAEN10DBMMAINCTAP_MASK 0x100000UL /**< Bit mask for RAC_TXPAEN10DBMMAINCTAP */
+#define _RAC_TX_TXPAEN10DBMMAINCTAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */
+#define _RAC_TX_TXPAEN10DBMMAINCTAP_ctap_main_dis 0x00000000UL /**< Mode ctap_main_dis for RAC_TX */
+#define _RAC_TX_TXPAEN10DBMMAINCTAP_ctap_main_en 0x00000001UL /**< Mode ctap_main_en for RAC_TX */
+#define RAC_TX_TXPAEN10DBMMAINCTAP_DEFAULT (_RAC_TX_TXPAEN10DBMMAINCTAP_DEFAULT << 20) /**< Shifted mode DEFAULT for RAC_TX */
+#define RAC_TX_TXPAEN10DBMMAINCTAP_ctap_main_dis (_RAC_TX_TXPAEN10DBMMAINCTAP_ctap_main_dis << 20) /**< Shifted mode ctap_main_dis for RAC_TX */
+#define RAC_TX_TXPAEN10DBMMAINCTAP_ctap_main_en (_RAC_TX_TXPAEN10DBMMAINCTAP_ctap_main_en << 20) /**< Shifted mode ctap_main_en for RAC_TX */
+#define RAC_TX_TXPAEN10DBMPREDRV (0x1UL << 21) /**< TXPAEN10DBMPREDRV */
+#define _RAC_TX_TXPAEN10DBMPREDRV_SHIFT 21 /**< Shift value for RAC_TXPAEN10DBMPREDRV */
+#define _RAC_TX_TXPAEN10DBMPREDRV_MASK 0x200000UL /**< Bit mask for RAC_TXPAEN10DBMPREDRV */
+#define _RAC_TX_TXPAEN10DBMPREDRV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */
+#define _RAC_TX_TXPAEN10DBMPREDRV_disable 0x00000000UL /**< Mode disable for RAC_TX */
+#define _RAC_TX_TXPAEN10DBMPREDRV_enable 0x00000001UL /**< Mode enable for RAC_TX */
+#define RAC_TX_TXPAEN10DBMPREDRV_DEFAULT (_RAC_TX_TXPAEN10DBMPREDRV_DEFAULT << 21) /**< Shifted mode DEFAULT for RAC_TX */
+#define RAC_TX_TXPAEN10DBMPREDRV_disable (_RAC_TX_TXPAEN10DBMPREDRV_disable << 21) /**< Shifted mode disable for RAC_TX */
+#define RAC_TX_TXPAEN10DBMPREDRV_enable (_RAC_TX_TXPAEN10DBMPREDRV_enable << 21) /**< Shifted mode enable for RAC_TX */
+#define RAC_TX_TXPAEN10DBMVMID (0x1UL << 22) /**< TXPAEN10DBMVMID */
+#define _RAC_TX_TXPAEN10DBMVMID_SHIFT 22 /**< Shift value for RAC_TXPAEN10DBMVMID */
+#define _RAC_TX_TXPAEN10DBMVMID_MASK 0x400000UL /**< Bit mask for RAC_TXPAEN10DBMVMID */
+#define _RAC_TX_TXPAEN10DBMVMID_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */
+#define _RAC_TX_TXPAEN10DBMVMID_disable 0x00000000UL /**< Mode disable for RAC_TX */
+#define _RAC_TX_TXPAEN10DBMVMID_enable 0x00000001UL /**< Mode enable for RAC_TX */
+#define RAC_TX_TXPAEN10DBMVMID_DEFAULT (_RAC_TX_TXPAEN10DBMVMID_DEFAULT << 22) /**< Shifted mode DEFAULT for RAC_TX */
+#define RAC_TX_TXPAEN10DBMVMID_disable (_RAC_TX_TXPAEN10DBMVMID_disable << 22) /**< Shifted mode disable for RAC_TX */
+#define RAC_TX_TXPAEN10DBMVMID_enable (_RAC_TX_TXPAEN10DBMVMID_enable << 22) /**< Shifted mode enable for RAC_TX */
+#define RAC_TX_TXPAEN20DBM (0x1UL << 23) /**< TXPAEN20DBM */
+#define _RAC_TX_TXPAEN20DBM_SHIFT 23 /**< Shift value for RAC_TXPAEN20DBM */
+#define _RAC_TX_TXPAEN20DBM_MASK 0x800000UL /**< Bit mask for RAC_TXPAEN20DBM */
+#define _RAC_TX_TXPAEN20DBM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */
+#define _RAC_TX_TXPAEN20DBM_disable 0x00000000UL /**< Mode disable for RAC_TX */
+#define _RAC_TX_TXPAEN20DBM_enable 0x00000001UL /**< Mode enable for RAC_TX */
+#define RAC_TX_TXPAEN20DBM_DEFAULT (_RAC_TX_TXPAEN20DBM_DEFAULT << 23) /**< Shifted mode DEFAULT for RAC_TX */
+#define RAC_TX_TXPAEN20DBM_disable (_RAC_TX_TXPAEN20DBM_disable << 23) /**< Shifted mode disable for RAC_TX */
+#define RAC_TX_TXPAEN20DBM_enable (_RAC_TX_TXPAEN20DBM_enable << 23) /**< Shifted mode enable for RAC_TX */
+#define RAC_TX_TXPAEN20DBMMAINCTAP (0x1UL << 24) /**< TXPAEN20DBMMAINCTAP */
+#define _RAC_TX_TXPAEN20DBMMAINCTAP_SHIFT 24 /**< Shift value for RAC_TXPAEN20DBMMAINCTAP */
+#define _RAC_TX_TXPAEN20DBMMAINCTAP_MASK 0x1000000UL /**< Bit mask for RAC_TXPAEN20DBMMAINCTAP */
+#define _RAC_TX_TXPAEN20DBMMAINCTAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */
+#define _RAC_TX_TXPAEN20DBMMAINCTAP_ctap_main_dis 0x00000000UL /**< Mode ctap_main_dis for RAC_TX */
+#define _RAC_TX_TXPAEN20DBMMAINCTAP_ctap_main_en 0x00000001UL /**< Mode ctap_main_en for RAC_TX */
+#define RAC_TX_TXPAEN20DBMMAINCTAP_DEFAULT (_RAC_TX_TXPAEN20DBMMAINCTAP_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_TX */
+#define RAC_TX_TXPAEN20DBMMAINCTAP_ctap_main_dis (_RAC_TX_TXPAEN20DBMMAINCTAP_ctap_main_dis << 24) /**< Shifted mode ctap_main_dis for RAC_TX */
+#define RAC_TX_TXPAEN20DBMMAINCTAP_ctap_main_en (_RAC_TX_TXPAEN20DBMMAINCTAP_ctap_main_en << 24) /**< Shifted mode ctap_main_en for RAC_TX */
+#define RAC_TX_TXPAEN20DBMPREDRV (0x1UL << 25) /**< TXPAEN20DBMPREDRV */
+#define _RAC_TX_TXPAEN20DBMPREDRV_SHIFT 25 /**< Shift value for RAC_TXPAEN20DBMPREDRV */
+#define _RAC_TX_TXPAEN20DBMPREDRV_MASK 0x2000000UL /**< Bit mask for RAC_TXPAEN20DBMPREDRV */
+#define _RAC_TX_TXPAEN20DBMPREDRV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */
+#define _RAC_TX_TXPAEN20DBMPREDRV_disable 0x00000000UL /**< Mode disable for RAC_TX */
+#define _RAC_TX_TXPAEN20DBMPREDRV_enable 0x00000001UL /**< Mode enable for RAC_TX */
+#define RAC_TX_TXPAEN20DBMPREDRV_DEFAULT (_RAC_TX_TXPAEN20DBMPREDRV_DEFAULT << 25) /**< Shifted mode DEFAULT for RAC_TX */
+#define RAC_TX_TXPAEN20DBMPREDRV_disable (_RAC_TX_TXPAEN20DBMPREDRV_disable << 25) /**< Shifted mode disable for RAC_TX */
+#define RAC_TX_TXPAEN20DBMPREDRV_enable (_RAC_TX_TXPAEN20DBMPREDRV_enable << 25) /**< Shifted mode enable for RAC_TX */
+#define RAC_TX_TXPAEN20DBMVMID (0x1UL << 26) /**< TXPAEN20DBMVMID */
+#define _RAC_TX_TXPAEN20DBMVMID_SHIFT 26 /**< Shift value for RAC_TXPAEN20DBMVMID */
+#define _RAC_TX_TXPAEN20DBMVMID_MASK 0x4000000UL /**< Bit mask for RAC_TXPAEN20DBMVMID */
+#define _RAC_TX_TXPAEN20DBMVMID_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */
+#define _RAC_TX_TXPAEN20DBMVMID_disable 0x00000000UL /**< Mode disable for RAC_TX */
+#define _RAC_TX_TXPAEN20DBMVMID_enable 0x00000001UL /**< Mode enable for RAC_TX */
+#define RAC_TX_TXPAEN20DBMVMID_DEFAULT (_RAC_TX_TXPAEN20DBMVMID_DEFAULT << 26) /**< Shifted mode DEFAULT for RAC_TX */
+#define RAC_TX_TXPAEN20DBMVMID_disable (_RAC_TX_TXPAEN20DBMVMID_disable << 26) /**< Shifted mode disable for RAC_TX */
+#define RAC_TX_TXPAEN20DBMVMID_enable (_RAC_TX_TXPAEN20DBMVMID_enable << 26) /**< Shifted mode enable for RAC_TX */
+#define RAC_TX_TXPAEN20DBMVBIASHF (0x1UL << 27) /**< TXPAEN20DBMVBIASHF */
+#define _RAC_TX_TXPAEN20DBMVBIASHF_SHIFT 27 /**< Shift value for RAC_TXPAEN20DBMVBIASHF */
+#define _RAC_TX_TXPAEN20DBMVBIASHF_MASK 0x8000000UL /**< Bit mask for RAC_TXPAEN20DBMVBIASHF */
+#define _RAC_TX_TXPAEN20DBMVBIASHF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */
+#define _RAC_TX_TXPAEN20DBMVBIASHF_disable_bias 0x00000000UL /**< Mode disable_bias for RAC_TX */
+#define _RAC_TX_TXPAEN20DBMVBIASHF_enable_bias 0x00000001UL /**< Mode enable_bias for RAC_TX */
+#define RAC_TX_TXPAEN20DBMVBIASHF_DEFAULT (_RAC_TX_TXPAEN20DBMVBIASHF_DEFAULT << 27) /**< Shifted mode DEFAULT for RAC_TX */
+#define RAC_TX_TXPAEN20DBMVBIASHF_disable_bias (_RAC_TX_TXPAEN20DBMVBIASHF_disable_bias << 27) /**< Shifted mode disable_bias for RAC_TX */
+#define RAC_TX_TXPAEN20DBMVBIASHF_enable_bias (_RAC_TX_TXPAEN20DBMVBIASHF_enable_bias << 27) /**< Shifted mode enable_bias for RAC_TX */
+#define _RAC_TX_TXPATRIM20DBMVBIASHF_SHIFT 28 /**< Shift value for RAC_TXPATRIM20DBMVBIASHF */
+#define _RAC_TX_TXPATRIM20DBMVBIASHF_MASK 0x30000000UL /**< Bit mask for RAC_TXPATRIM20DBMVBIASHF */
+#define _RAC_TX_TXPATRIM20DBMVBIASHF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */
+#define _RAC_TX_TXPATRIM20DBMVBIASHF_bias_avss 0x00000000UL /**< Mode bias_avss for RAC_TX */
+#define _RAC_TX_TXPATRIM20DBMVBIASHF_bias_low 0x00000001UL /**< Mode bias_low for RAC_TX */
+#define _RAC_TX_TXPATRIM20DBMVBIASHF_bias_mid 0x00000002UL /**< Mode bias_mid for RAC_TX */
+#define _RAC_TX_TXPATRIM20DBMVBIASHF_bias_high 0x00000003UL /**< Mode bias_high for RAC_TX */
+#define RAC_TX_TXPATRIM20DBMVBIASHF_DEFAULT (_RAC_TX_TXPATRIM20DBMVBIASHF_DEFAULT << 28) /**< Shifted mode DEFAULT for RAC_TX */
+#define RAC_TX_TXPATRIM20DBMVBIASHF_bias_avss (_RAC_TX_TXPATRIM20DBMVBIASHF_bias_avss << 28) /**< Shifted mode bias_avss for RAC_TX */
+#define RAC_TX_TXPATRIM20DBMVBIASHF_bias_low (_RAC_TX_TXPATRIM20DBMVBIASHF_bias_low << 28) /**< Shifted mode bias_low for RAC_TX */
+#define RAC_TX_TXPATRIM20DBMVBIASHF_bias_mid (_RAC_TX_TXPATRIM20DBMVBIASHF_bias_mid << 28) /**< Shifted mode bias_mid for RAC_TX */
+#define RAC_TX_TXPATRIM20DBMVBIASHF_bias_high (_RAC_TX_TXPATRIM20DBMVBIASHF_bias_high << 28) /**< Shifted mode bias_high for RAC_TX */
+#define RAC_TX_ENPAPOWER (0x1UL << 30) /**< Override */
+#define _RAC_TX_ENPAPOWER_SHIFT 30 /**< Shift value for RAC_ENPAPOWER */
+#define _RAC_TX_ENPAPOWER_MASK 0x40000000UL /**< Bit mask for RAC_ENPAPOWER */
+#define _RAC_TX_ENPAPOWER_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */
+#define RAC_TX_ENPAPOWER_DEFAULT (_RAC_TX_ENPAPOWER_DEFAULT << 30) /**< Shifted mode DEFAULT for RAC_TX */
+#define RAC_TX_ENPASELSLICE (0x1UL << 31) /**< Override */
+#define _RAC_TX_ENPASELSLICE_SHIFT 31 /**< Shift value for RAC_ENPASELSLICE */
+#define _RAC_TX_ENPASELSLICE_MASK 0x80000000UL /**< Bit mask for RAC_ENPASELSLICE */
+#define _RAC_TX_ENPASELSLICE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_TX */
+#define RAC_TX_ENPASELSLICE_DEFAULT (_RAC_TX_ENPASELSLICE_DEFAULT << 31) /**< Shifted mode DEFAULT for RAC_TX */
+
+/* Bit fields for RAC SYTRIM0 */
+#define _RAC_SYTRIM0_RESETVALUE 0x018FF169UL /**< Default value for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_MASK 0x0FFFFFFFUL /**< Mask for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPBIAS_SHIFT 0 /**< Shift value for RAC_SYCHPBIAS */
+#define _RAC_SYTRIM0_SYCHPBIAS_MASK 0x7UL /**< Bit mask for RAC_SYCHPBIAS */
+#define _RAC_SYTRIM0_SYCHPBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPBIAS_bias_0 0x00000000UL /**< Mode bias_0 for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPBIAS_bias_1 0x00000001UL /**< Mode bias_1 for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPBIAS_bias_2 0x00000003UL /**< Mode bias_2 for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPBIAS_bias_3 0x00000007UL /**< Mode bias_3 for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPBIAS_DEFAULT (_RAC_SYTRIM0_SYCHPBIAS_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPBIAS_bias_0 (_RAC_SYTRIM0_SYCHPBIAS_bias_0 << 0) /**< Shifted mode bias_0 for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPBIAS_bias_1 (_RAC_SYTRIM0_SYCHPBIAS_bias_1 << 0) /**< Shifted mode bias_1 for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPBIAS_bias_2 (_RAC_SYTRIM0_SYCHPBIAS_bias_2 << 0) /**< Shifted mode bias_2 for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPBIAS_bias_3 (_RAC_SYTRIM0_SYCHPBIAS_bias_3 << 0) /**< Shifted mode bias_3 for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPCURRRX_SHIFT 3 /**< Shift value for RAC_SYCHPCURRRX */
+#define _RAC_SYTRIM0_SYCHPCURRRX_MASK 0x38UL /**< Bit mask for RAC_SYCHPCURRRX */
+#define _RAC_SYTRIM0_SYCHPCURRRX_DEFAULT 0x00000005UL /**< Mode DEFAULT for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPCURRRX_curr_1p5uA 0x00000000UL /**< Mode curr_1p5uA for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPCURRRX_curr_2p0uA 0x00000001UL /**< Mode curr_2p0uA for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPCURRRX_curr_2p5uA 0x00000002UL /**< Mode curr_2p5uA for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPCURRRX_curr_3p0uA 0x00000003UL /**< Mode curr_3p0uA for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPCURRRX_curr_3p5uA 0x00000004UL /**< Mode curr_3p5uA for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPCURRRX_curr_4p0uA 0x00000005UL /**< Mode curr_4p0uA for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPCURRRX_curr_4p5uA 0x00000006UL /**< Mode curr_4p5uA for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPCURRRX_curr_5p0uA 0x00000007UL /**< Mode curr_5p0uA for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPCURRRX_DEFAULT (_RAC_SYTRIM0_SYCHPCURRRX_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPCURRRX_curr_1p5uA (_RAC_SYTRIM0_SYCHPCURRRX_curr_1p5uA << 3) /**< Shifted mode curr_1p5uA for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPCURRRX_curr_2p0uA (_RAC_SYTRIM0_SYCHPCURRRX_curr_2p0uA << 3) /**< Shifted mode curr_2p0uA for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPCURRRX_curr_2p5uA (_RAC_SYTRIM0_SYCHPCURRRX_curr_2p5uA << 3) /**< Shifted mode curr_2p5uA for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPCURRRX_curr_3p0uA (_RAC_SYTRIM0_SYCHPCURRRX_curr_3p0uA << 3) /**< Shifted mode curr_3p0uA for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPCURRRX_curr_3p5uA (_RAC_SYTRIM0_SYCHPCURRRX_curr_3p5uA << 3) /**< Shifted mode curr_3p5uA for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPCURRRX_curr_4p0uA (_RAC_SYTRIM0_SYCHPCURRRX_curr_4p0uA << 3) /**< Shifted mode curr_4p0uA for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPCURRRX_curr_4p5uA (_RAC_SYTRIM0_SYCHPCURRRX_curr_4p5uA << 3) /**< Shifted mode curr_4p5uA for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPCURRRX_curr_5p0uA (_RAC_SYTRIM0_SYCHPCURRRX_curr_5p0uA << 3) /**< Shifted mode curr_5p0uA for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPCURRTX_SHIFT 6 /**< Shift value for RAC_SYCHPCURRTX */
+#define _RAC_SYTRIM0_SYCHPCURRTX_MASK 0x1C0UL /**< Bit mask for RAC_SYCHPCURRTX */
+#define _RAC_SYTRIM0_SYCHPCURRTX_DEFAULT 0x00000005UL /**< Mode DEFAULT for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPCURRTX_curr_1p5uA 0x00000000UL /**< Mode curr_1p5uA for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPCURRTX_curr_2p0uA 0x00000001UL /**< Mode curr_2p0uA for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPCURRTX_curr_2p5uA 0x00000002UL /**< Mode curr_2p5uA for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPCURRTX_curr_3p0uA 0x00000003UL /**< Mode curr_3p0uA for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPCURRTX_curr_3p5uA 0x00000004UL /**< Mode curr_3p5uA for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPCURRTX_curr_4p0uA 0x00000005UL /**< Mode curr_4p0uA for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPCURRTX_curr_4p5uA 0x00000006UL /**< Mode curr_4p5uA for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPCURRTX_curr_5p0uA 0x00000007UL /**< Mode curr_5p0uA for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPCURRTX_DEFAULT (_RAC_SYTRIM0_SYCHPCURRTX_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPCURRTX_curr_1p5uA (_RAC_SYTRIM0_SYCHPCURRTX_curr_1p5uA << 6) /**< Shifted mode curr_1p5uA for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPCURRTX_curr_2p0uA (_RAC_SYTRIM0_SYCHPCURRTX_curr_2p0uA << 6) /**< Shifted mode curr_2p0uA for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPCURRTX_curr_2p5uA (_RAC_SYTRIM0_SYCHPCURRTX_curr_2p5uA << 6) /**< Shifted mode curr_2p5uA for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPCURRTX_curr_3p0uA (_RAC_SYTRIM0_SYCHPCURRTX_curr_3p0uA << 6) /**< Shifted mode curr_3p0uA for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPCURRTX_curr_3p5uA (_RAC_SYTRIM0_SYCHPCURRTX_curr_3p5uA << 6) /**< Shifted mode curr_3p5uA for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPCURRTX_curr_4p0uA (_RAC_SYTRIM0_SYCHPCURRTX_curr_4p0uA << 6) /**< Shifted mode curr_4p0uA for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPCURRTX_curr_4p5uA (_RAC_SYTRIM0_SYCHPCURRTX_curr_4p5uA << 6) /**< Shifted mode curr_4p5uA for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPCURRTX_curr_5p0uA (_RAC_SYTRIM0_SYCHPCURRTX_curr_5p0uA << 6) /**< Shifted mode curr_5p0uA for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPLEVNSRC_SHIFT 9 /**< Shift value for RAC_SYCHPLEVNSRC */
+#define _RAC_SYTRIM0_SYCHPLEVNSRC_MASK 0xE00UL /**< Bit mask for RAC_SYCHPLEVNSRC */
+#define _RAC_SYTRIM0_SYCHPLEVNSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPLEVNSRC_DEFAULT (_RAC_SYTRIM0_SYCHPLEVNSRC_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPLEVPSRCRX_SHIFT 12 /**< Shift value for RAC_SYCHPLEVPSRCRX */
+#define _RAC_SYTRIM0_SYCHPLEVPSRCRX_MASK 0x7000UL /**< Bit mask for RAC_SYCHPLEVPSRCRX */
+#define _RAC_SYTRIM0_SYCHPLEVPSRCRX_DEFAULT 0x00000007UL /**< Mode DEFAULT for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n105m 0x00000000UL /**< Mode vsrcp_n105m for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n90m 0x00000001UL /**< Mode vsrcp_n90m for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n75m 0x00000002UL /**< Mode vsrcp_n75m for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n60m 0x00000003UL /**< Mode vsrcp_n60m for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n45m 0x00000004UL /**< Mode vsrcp_n45m for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n30m 0x00000005UL /**< Mode vsrcp_n30m for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n15m 0x00000006UL /**< Mode vsrcp_n15m for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n0m 0x00000007UL /**< Mode vsrcp_n0m for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPLEVPSRCRX_DEFAULT (_RAC_SYTRIM0_SYCHPLEVPSRCRX_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n105m (_RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n105m << 12) /**< Shifted mode vsrcp_n105m for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n90m (_RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n90m << 12) /**< Shifted mode vsrcp_n90m for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n75m (_RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n75m << 12) /**< Shifted mode vsrcp_n75m for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n60m (_RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n60m << 12) /**< Shifted mode vsrcp_n60m for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n45m (_RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n45m << 12) /**< Shifted mode vsrcp_n45m for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n30m (_RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n30m << 12) /**< Shifted mode vsrcp_n30m for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n15m (_RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n15m << 12) /**< Shifted mode vsrcp_n15m for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n0m (_RAC_SYTRIM0_SYCHPLEVPSRCRX_vsrcp_n0m << 12) /**< Shifted mode vsrcp_n0m for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPLEVPSRCTX_SHIFT 15 /**< Shift value for RAC_SYCHPLEVPSRCTX */
+#define _RAC_SYTRIM0_SYCHPLEVPSRCTX_MASK 0x38000UL /**< Bit mask for RAC_SYCHPLEVPSRCTX */
+#define _RAC_SYTRIM0_SYCHPLEVPSRCTX_DEFAULT 0x00000007UL /**< Mode DEFAULT for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n105m 0x00000000UL /**< Mode vsrcp_n105m for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n90m 0x00000001UL /**< Mode vsrcp_n90m for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n75m 0x00000002UL /**< Mode vsrcp_n75m for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n60m 0x00000003UL /**< Mode vsrcp_n60m for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n45m 0x00000004UL /**< Mode vsrcp_n45m for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n30m 0x00000005UL /**< Mode vsrcp_n30m for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n15m 0x00000006UL /**< Mode vsrcp_n15m for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n0m 0x00000007UL /**< Mode vsrcp_n0m for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPLEVPSRCTX_DEFAULT (_RAC_SYTRIM0_SYCHPLEVPSRCTX_DEFAULT << 15) /**< Shifted mode DEFAULT for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n105m (_RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n105m << 15) /**< Shifted mode vsrcp_n105m for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n90m (_RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n90m << 15) /**< Shifted mode vsrcp_n90m for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n75m (_RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n75m << 15) /**< Shifted mode vsrcp_n75m for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n60m (_RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n60m << 15) /**< Shifted mode vsrcp_n60m for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n45m (_RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n45m << 15) /**< Shifted mode vsrcp_n45m for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n30m (_RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n30m << 15) /**< Shifted mode vsrcp_n30m for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n15m (_RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n15m << 15) /**< Shifted mode vsrcp_n15m for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n0m (_RAC_SYTRIM0_SYCHPLEVPSRCTX_vsrcp_n0m << 15) /**< Shifted mode vsrcp_n0m for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPSRCENRX (0x1UL << 18) /**< SYCHPSRCENRX */
+#define _RAC_SYTRIM0_SYCHPSRCENRX_SHIFT 18 /**< Shift value for RAC_SYCHPSRCENRX */
+#define _RAC_SYTRIM0_SYCHPSRCENRX_MASK 0x40000UL /**< Bit mask for RAC_SYCHPSRCENRX */
+#define _RAC_SYTRIM0_SYCHPSRCENRX_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPSRCENRX_disable 0x00000000UL /**< Mode disable for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPSRCENRX_enable 0x00000001UL /**< Mode enable for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPSRCENRX_DEFAULT (_RAC_SYTRIM0_SYCHPSRCENRX_DEFAULT << 18) /**< Shifted mode DEFAULT for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPSRCENRX_disable (_RAC_SYTRIM0_SYCHPSRCENRX_disable << 18) /**< Shifted mode disable for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPSRCENRX_enable (_RAC_SYTRIM0_SYCHPSRCENRX_enable << 18) /**< Shifted mode enable for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPSRCENTX (0x1UL << 19) /**< SYCHPSRCENTX */
+#define _RAC_SYTRIM0_SYCHPSRCENTX_SHIFT 19 /**< Shift value for RAC_SYCHPSRCENTX */
+#define _RAC_SYTRIM0_SYCHPSRCENTX_MASK 0x80000UL /**< Bit mask for RAC_SYCHPSRCENTX */
+#define _RAC_SYTRIM0_SYCHPSRCENTX_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPSRCENTX_disable 0x00000000UL /**< Mode disable for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPSRCENTX_enable 0x00000001UL /**< Mode enable for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPSRCENTX_DEFAULT (_RAC_SYTRIM0_SYCHPSRCENTX_DEFAULT << 19) /**< Shifted mode DEFAULT for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPSRCENTX_disable (_RAC_SYTRIM0_SYCHPSRCENTX_disable << 19) /**< Shifted mode disable for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPSRCENTX_enable (_RAC_SYTRIM0_SYCHPSRCENTX_enable << 19) /**< Shifted mode enable for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPREPLICACURRADJ_SHIFT 20 /**< Shift value for RAC_SYCHPREPLICACURRADJ */
+#define _RAC_SYTRIM0_SYCHPREPLICACURRADJ_MASK 0x700000UL /**< Bit mask for RAC_SYCHPREPLICACURRADJ */
+#define _RAC_SYTRIM0_SYCHPREPLICACURRADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_8ua 0x00000000UL /**< Mode load_8ua for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_16ua 0x00000001UL /**< Mode load_16ua for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_20ua 0x00000002UL /**< Mode load_20ua for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_28ua 0x00000003UL /**< Mode load_28ua for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_24ua 0x00000004UL /**< Mode load_24ua for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_32ua 0x00000005UL /**< Mode load_32ua for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_36ua 0x00000006UL /**< Mode load_36ua for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_44ua 0x00000007UL /**< Mode load_44ua for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPREPLICACURRADJ_DEFAULT (_RAC_SYTRIM0_SYCHPREPLICACURRADJ_DEFAULT << 20) /**< Shifted mode DEFAULT for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_8ua (_RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_8ua << 20) /**< Shifted mode load_8ua for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_16ua (_RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_16ua << 20) /**< Shifted mode load_16ua for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_20ua (_RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_20ua << 20) /**< Shifted mode load_20ua for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_28ua (_RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_28ua << 20) /**< Shifted mode load_28ua for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_24ua (_RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_24ua << 20) /**< Shifted mode load_24ua for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_32ua (_RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_32ua << 20) /**< Shifted mode load_32ua for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_36ua (_RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_36ua << 20) /**< Shifted mode load_36ua for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_44ua (_RAC_SYTRIM0_SYCHPREPLICACURRADJ_load_44ua << 20) /**< Shifted mode load_44ua for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_SHIFT 23 /**< Shift value for RAC_SYTRIMCHPREGAMPBIAS */
+#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_MASK 0x3800000UL /**< Bit mask for RAC_SYTRIMCHPREGAMPBIAS */
+#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_DEFAULT 0x00000003UL /**< Mode DEFAULT for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_14uA 0x00000000UL /**< Mode bias_14uA for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_20uA 0x00000001UL /**< Mode bias_20uA for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_26uA 0x00000002UL /**< Mode bias_26uA for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_32uA 0x00000003UL /**< Mode bias_32uA for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_38uA 0x00000004UL /**< Mode bias_38uA for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_44uA 0x00000005UL /**< Mode bias_44uA for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_50uA 0x00000006UL /**< Mode bias_50uA for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_56uA 0x00000007UL /**< Mode bias_56uA for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_DEFAULT (_RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_DEFAULT << 23) /**< Shifted mode DEFAULT for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_14uA (_RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_14uA << 23) /**< Shifted mode bias_14uA for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_20uA (_RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_20uA << 23) /**< Shifted mode bias_20uA for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_26uA (_RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_26uA << 23) /**< Shifted mode bias_26uA for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_32uA (_RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_32uA << 23) /**< Shifted mode bias_32uA for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_38uA (_RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_38uA << 23) /**< Shifted mode bias_38uA for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_44uA (_RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_44uA << 23) /**< Shifted mode bias_44uA for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_50uA (_RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_50uA << 23) /**< Shifted mode bias_50uA for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_56uA (_RAC_SYTRIM0_SYTRIMCHPREGAMPBIAS_bias_56uA << 23) /**< Shifted mode bias_56uA for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBW_SHIFT 26 /**< Shift value for RAC_SYTRIMCHPREGAMPBW */
+#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBW_MASK 0xC000000UL /**< Bit mask for RAC_SYTRIMCHPREGAMPBW */
+#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBW_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBW_C_000f 0x00000000UL /**< Mode C_000f for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBW_C_300f 0x00000001UL /**< Mode C_300f for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBW_C_600f 0x00000002UL /**< Mode C_600f for RAC_SYTRIM0 */
+#define _RAC_SYTRIM0_SYTRIMCHPREGAMPBW_C_900f 0x00000003UL /**< Mode C_900f for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYTRIMCHPREGAMPBW_DEFAULT (_RAC_SYTRIM0_SYTRIMCHPREGAMPBW_DEFAULT << 26) /**< Shifted mode DEFAULT for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYTRIMCHPREGAMPBW_C_000f (_RAC_SYTRIM0_SYTRIMCHPREGAMPBW_C_000f << 26) /**< Shifted mode C_000f for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYTRIMCHPREGAMPBW_C_300f (_RAC_SYTRIM0_SYTRIMCHPREGAMPBW_C_300f << 26) /**< Shifted mode C_300f for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYTRIMCHPREGAMPBW_C_600f (_RAC_SYTRIM0_SYTRIMCHPREGAMPBW_C_600f << 26) /**< Shifted mode C_600f for RAC_SYTRIM0 */
+#define RAC_SYTRIM0_SYTRIMCHPREGAMPBW_C_900f (_RAC_SYTRIM0_SYTRIMCHPREGAMPBW_C_900f << 26) /**< Shifted mode C_900f for RAC_SYTRIM0 */
+
+/* Bit fields for RAC SYTRIM1 */
+#define _RAC_SYTRIM1_RESETVALUE 0x1FE00410UL /**< Default value for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_MASK 0xFFFC0FFFUL /**< Mask for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMCORERX_SHIFT 0 /**< Shift value for RAC_SYLODIVLDOTRIMCORERX */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMCORERX_MASK 0x3UL /**< Bit mask for RAC_SYLODIVLDOTRIMCORERX */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMCORERX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMCORERX_RXLO 0x00000000UL /**< Mode RXLO for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMCORERX_TXLO 0x00000003UL /**< Mode TXLO for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYLODIVLDOTRIMCORERX_DEFAULT (_RAC_SYTRIM1_SYLODIVLDOTRIMCORERX_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYLODIVLDOTRIMCORERX_RXLO (_RAC_SYTRIM1_SYLODIVLDOTRIMCORERX_RXLO << 0) /**< Shifted mode RXLO for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYLODIVLDOTRIMCORERX_TXLO (_RAC_SYTRIM1_SYLODIVLDOTRIMCORERX_TXLO << 0) /**< Shifted mode TXLO for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMCORETX_SHIFT 2 /**< Shift value for RAC_SYLODIVLDOTRIMCORETX */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMCORETX_MASK 0xCUL /**< Bit mask for RAC_SYLODIVLDOTRIMCORETX */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMCORETX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMCORETX_RXLO 0x00000000UL /**< Mode RXLO for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMCORETX_TXLO 0x00000003UL /**< Mode TXLO for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYLODIVLDOTRIMCORETX_DEFAULT (_RAC_SYTRIM1_SYLODIVLDOTRIMCORETX_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYLODIVLDOTRIMCORETX_RXLO (_RAC_SYTRIM1_SYLODIVLDOTRIMCORETX_RXLO << 2) /**< Shifted mode RXLO for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYLODIVLDOTRIMCORETX_TXLO (_RAC_SYTRIM1_SYLODIVLDOTRIMCORETX_TXLO << 2) /**< Shifted mode TXLO for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_SHIFT 4 /**< Shift value for RAC_SYLODIVLDOTRIMNDIORX */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_MASK 0xF0UL /**< Bit mask for RAC_SYLODIVLDOTRIMNDIORX */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p08 0x00000000UL /**< Mode vreg_1p08 for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p11 0x00000001UL /**< Mode vreg_1p11 for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p15 0x00000002UL /**< Mode vreg_1p15 for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p18 0x00000003UL /**< Mode vreg_1p18 for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p21 0x00000004UL /**< Mode vreg_1p21 for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p24 0x00000005UL /**< Mode vreg_1p24 for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p27 0x00000006UL /**< Mode vreg_1p27 for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p29 0x00000007UL /**< Mode vreg_1p29 for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p32 0x00000008UL /**< Mode vreg_1p32 for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p34 0x00000009UL /**< Mode vreg_1p34 for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_DEFAULT (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p08 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p08 << 4) /**< Shifted mode vreg_1p08 for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p11 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p11 << 4) /**< Shifted mode vreg_1p11 for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p15 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p15 << 4) /**< Shifted mode vreg_1p15 for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p18 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p18 << 4) /**< Shifted mode vreg_1p18 for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p21 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p21 << 4) /**< Shifted mode vreg_1p21 for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p24 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p24 << 4) /**< Shifted mode vreg_1p24 for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p27 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p27 << 4) /**< Shifted mode vreg_1p27 for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p29 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p29 << 4) /**< Shifted mode vreg_1p29 for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p32 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p32 << 4) /**< Shifted mode vreg_1p32 for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p34 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIORX_vreg_1p34 << 4) /**< Shifted mode vreg_1p34 for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_SHIFT 8 /**< Shift value for RAC_SYLODIVLDOTRIMNDIOTX */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_MASK 0xF00UL /**< Bit mask for RAC_SYLODIVLDOTRIMNDIOTX */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_DEFAULT 0x00000004UL /**< Mode DEFAULT for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p08 0x00000000UL /**< Mode vreg_1p08 for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p11 0x00000001UL /**< Mode vreg_1p11 for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p15 0x00000002UL /**< Mode vreg_1p15 for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p18 0x00000003UL /**< Mode vreg_1p18 for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p21 0x00000004UL /**< Mode vreg_1p21 for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p24 0x00000005UL /**< Mode vreg_1p24 for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p27 0x00000006UL /**< Mode vreg_1p27 for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p29 0x00000007UL /**< Mode vreg_1p29 for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p32 0x00000008UL /**< Mode vreg_1p32 for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p34 0x00000009UL /**< Mode vreg_1p34 for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_DEFAULT (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p08 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p08 << 8) /**< Shifted mode vreg_1p08 for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p11 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p11 << 8) /**< Shifted mode vreg_1p11 for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p15 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p15 << 8) /**< Shifted mode vreg_1p15 for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p18 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p18 << 8) /**< Shifted mode vreg_1p18 for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p21 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p21 << 8) /**< Shifted mode vreg_1p21 for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p24 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p24 << 8) /**< Shifted mode vreg_1p24 for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p27 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p27 << 8) /**< Shifted mode vreg_1p27 for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p29 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p29 << 8) /**< Shifted mode vreg_1p29 for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p32 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p32 << 8) /**< Shifted mode vreg_1p32 for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p34 (_RAC_SYTRIM1_SYLODIVLDOTRIMNDIOTX_vreg_1p34 << 8) /**< Shifted mode vreg_1p34 for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYLODIVTLO20DBM2G4DELAY_SHIFT 18 /**< Shift value for RAC_SYLODIVTLO20DBM2G4DELAY */
+#define _RAC_SYTRIM1_SYLODIVTLO20DBM2G4DELAY_MASK 0x1C0000UL /**< Bit mask for RAC_SYLODIVTLO20DBM2G4DELAY */
+#define _RAC_SYTRIM1_SYLODIVTLO20DBM2G4DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYLODIVTLO20DBM2G4DELAY_DEFAULT (_RAC_SYTRIM1_SYLODIVTLO20DBM2G4DELAY_DEFAULT << 18) /**< Shifted mode DEFAULT for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_SHIFT 21 /**< Shift value for RAC_SYMMDREPLICA1CURRADJ */
+#define _RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_MASK 0xE00000UL /**< Bit mask for RAC_SYMMDREPLICA1CURRADJ */
+#define _RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_DEFAULT 0x00000007UL /**< Mode DEFAULT for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_8ua 0x00000000UL /**< Mode load_8ua for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_16u 0x00000001UL /**< Mode load_16u for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_20ua 0x00000002UL /**< Mode load_20ua for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_28ua 0x00000003UL /**< Mode load_28ua for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_24ua 0x00000004UL /**< Mode load_24ua for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_32ua 0x00000005UL /**< Mode load_32ua for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_36ua 0x00000006UL /**< Mode load_36ua for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_44ua 0x00000007UL /**< Mode load_44ua for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_DEFAULT (_RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_DEFAULT << 21) /**< Shifted mode DEFAULT for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_8ua (_RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_8ua << 21) /**< Shifted mode load_8ua for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_16u (_RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_16u << 21) /**< Shifted mode load_16u for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_20ua (_RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_20ua << 21) /**< Shifted mode load_20ua for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_28ua (_RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_28ua << 21) /**< Shifted mode load_28ua for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_24ua (_RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_24ua << 21) /**< Shifted mode load_24ua for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_32ua (_RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_32ua << 21) /**< Shifted mode load_32ua for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_36ua (_RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_36ua << 21) /**< Shifted mode load_36ua for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_44ua (_RAC_SYTRIM1_SYMMDREPLICA1CURRADJ_load_44ua << 21) /**< Shifted mode load_44ua for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_SHIFT 24 /**< Shift value for RAC_SYMMDREPLICA2CURRADJ */
+#define _RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_MASK 0x7000000UL /**< Bit mask for RAC_SYMMDREPLICA2CURRADJ */
+#define _RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_DEFAULT 0x00000007UL /**< Mode DEFAULT for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_32u 0x00000000UL /**< Mode load_32u for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_64u 0x00000001UL /**< Mode load_64u for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_96u 0x00000002UL /**< Mode load_96u for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_128u 0x00000003UL /**< Mode load_128u for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_160u 0x00000004UL /**< Mode load_160u for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_192u 0x00000005UL /**< Mode load_192u for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_224u 0x00000006UL /**< Mode load_224u for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_256u 0x00000007UL /**< Mode load_256u for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_DEFAULT (_RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_32u (_RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_32u << 24) /**< Shifted mode load_32u for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_64u (_RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_64u << 24) /**< Shifted mode load_64u for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_96u (_RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_96u << 24) /**< Shifted mode load_96u for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_128u (_RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_128u << 24) /**< Shifted mode load_128u for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_160u (_RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_160u << 24) /**< Shifted mode load_160u for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_192u (_RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_192u << 24) /**< Shifted mode load_192u for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_224u (_RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_224u << 24) /**< Shifted mode load_224u for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_256u (_RAC_SYTRIM1_SYMMDREPLICA2CURRADJ_load_256u << 24) /**< Shifted mode load_256u for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_SHIFT 27 /**< Shift value for RAC_SYTRIMMMDREGAMPBIAS */
+#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_MASK 0x38000000UL /**< Bit mask for RAC_SYTRIMMMDREGAMPBIAS */
+#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_DEFAULT 0x00000003UL /**< Mode DEFAULT for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_14uA 0x00000000UL /**< Mode bias_14uA for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_20uA 0x00000001UL /**< Mode bias_20uA for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_26uA 0x00000002UL /**< Mode bias_26uA for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_32uA 0x00000003UL /**< Mode bias_32uA for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_38uA 0x00000004UL /**< Mode bias_38uA for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_44uA 0x00000005UL /**< Mode bias_44uA for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_50uA 0x00000006UL /**< Mode bias_50uA for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_56uA 0x00000007UL /**< Mode bias_56uA for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_DEFAULT (_RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_DEFAULT << 27) /**< Shifted mode DEFAULT for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_14uA (_RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_14uA << 27) /**< Shifted mode bias_14uA for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_20uA (_RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_20uA << 27) /**< Shifted mode bias_20uA for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_26uA (_RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_26uA << 27) /**< Shifted mode bias_26uA for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_32uA (_RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_32uA << 27) /**< Shifted mode bias_32uA for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_38uA (_RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_38uA << 27) /**< Shifted mode bias_38uA for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_44uA (_RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_44uA << 27) /**< Shifted mode bias_44uA for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_50uA (_RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_50uA << 27) /**< Shifted mode bias_50uA for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_56uA (_RAC_SYTRIM1_SYTRIMMMDREGAMPBIAS_bias_56uA << 27) /**< Shifted mode bias_56uA for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBW_SHIFT 30 /**< Shift value for RAC_SYTRIMMMDREGAMPBW */
+#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBW_MASK 0xC0000000UL /**< Bit mask for RAC_SYTRIMMMDREGAMPBW */
+#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBW_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBW_C_000f 0x00000000UL /**< Mode C_000f for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBW_C_300f 0x00000001UL /**< Mode C_300f for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBW_C_600f 0x00000002UL /**< Mode C_600f for RAC_SYTRIM1 */
+#define _RAC_SYTRIM1_SYTRIMMMDREGAMPBW_C_900f 0x00000003UL /**< Mode C_900f for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYTRIMMMDREGAMPBW_DEFAULT (_RAC_SYTRIM1_SYTRIMMMDREGAMPBW_DEFAULT << 30) /**< Shifted mode DEFAULT for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYTRIMMMDREGAMPBW_C_000f (_RAC_SYTRIM1_SYTRIMMMDREGAMPBW_C_000f << 30) /**< Shifted mode C_000f for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYTRIMMMDREGAMPBW_C_300f (_RAC_SYTRIM1_SYTRIMMMDREGAMPBW_C_300f << 30) /**< Shifted mode C_300f for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYTRIMMMDREGAMPBW_C_600f (_RAC_SYTRIM1_SYTRIMMMDREGAMPBW_C_600f << 30) /**< Shifted mode C_600f for RAC_SYTRIM1 */
+#define RAC_SYTRIM1_SYTRIMMMDREGAMPBW_C_900f (_RAC_SYTRIM1_SYTRIMMMDREGAMPBW_C_900f << 30) /**< Shifted mode C_900f for RAC_SYTRIM1 */
+
+/* Bit fields for RAC SYCAL */
+#define _RAC_SYCAL_RESETVALUE 0x01008100UL /**< Default value for RAC_SYCAL */
+#define _RAC_SYCAL_MASK 0x03018700UL /**< Mask for RAC_SYCAL */
+#define RAC_SYCAL_SYVCOMODEPKD (0x1UL << 8) /**< SYVCOMODEPKD */
+#define _RAC_SYCAL_SYVCOMODEPKD_SHIFT 8 /**< Shift value for RAC_SYVCOMODEPKD */
+#define _RAC_SYCAL_SYVCOMODEPKD_MASK 0x100UL /**< Bit mask for RAC_SYVCOMODEPKD */
+#define _RAC_SYCAL_SYVCOMODEPKD_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_SYCAL */
+#define _RAC_SYCAL_SYVCOMODEPKD_t_openloop_0 0x00000000UL /**< Mode t_openloop_0 for RAC_SYCAL */
+#define _RAC_SYCAL_SYVCOMODEPKD_t_pkdetect_1 0x00000001UL /**< Mode t_pkdetect_1 for RAC_SYCAL */
+#define RAC_SYCAL_SYVCOMODEPKD_DEFAULT (_RAC_SYCAL_SYVCOMODEPKD_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_SYCAL */
+#define RAC_SYCAL_SYVCOMODEPKD_t_openloop_0 (_RAC_SYCAL_SYVCOMODEPKD_t_openloop_0 << 8) /**< Shifted mode t_openloop_0 for RAC_SYCAL */
+#define RAC_SYCAL_SYVCOMODEPKD_t_pkdetect_1 (_RAC_SYCAL_SYVCOMODEPKD_t_pkdetect_1 << 8) /**< Shifted mode t_pkdetect_1 for RAC_SYCAL */
+#define RAC_SYCAL_SYVCOMORECURRENT (0x1UL << 9) /**< SYVCOMORECURRENT */
+#define _RAC_SYCAL_SYVCOMORECURRENT_SHIFT 9 /**< Shift value for RAC_SYVCOMORECURRENT */
+#define _RAC_SYCAL_SYVCOMORECURRENT_MASK 0x200UL /**< Bit mask for RAC_SYVCOMORECURRENT */
+#define _RAC_SYCAL_SYVCOMORECURRENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYCAL */
+#define _RAC_SYCAL_SYVCOMORECURRENT_more_current_0 0x00000000UL /**< Mode more_current_0 for RAC_SYCAL */
+#define _RAC_SYCAL_SYVCOMORECURRENT_more_current_1 0x00000001UL /**< Mode more_current_1 for RAC_SYCAL */
+#define RAC_SYCAL_SYVCOMORECURRENT_DEFAULT (_RAC_SYCAL_SYVCOMORECURRENT_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_SYCAL */
+#define RAC_SYCAL_SYVCOMORECURRENT_more_current_0 (_RAC_SYCAL_SYVCOMORECURRENT_more_current_0 << 9) /**< Shifted mode more_current_0 for RAC_SYCAL */
+#define RAC_SYCAL_SYVCOMORECURRENT_more_current_1 (_RAC_SYCAL_SYVCOMORECURRENT_more_current_1 << 9) /**< Shifted mode more_current_1 for RAC_SYCAL */
+#define RAC_SYCAL_SYVCOSLOWNOISEFILTER (0x1UL << 10) /**< SYVCOSLOWNOISEFILTER */
+#define _RAC_SYCAL_SYVCOSLOWNOISEFILTER_SHIFT 10 /**< Shift value for RAC_SYVCOSLOWNOISEFILTER */
+#define _RAC_SYCAL_SYVCOSLOWNOISEFILTER_MASK 0x400UL /**< Bit mask for RAC_SYVCOSLOWNOISEFILTER */
+#define _RAC_SYCAL_SYVCOSLOWNOISEFILTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYCAL */
+#define _RAC_SYCAL_SYVCOSLOWNOISEFILTER_slow_noise_filter_0 0x00000000UL /**< Mode slow_noise_filter_0 for RAC_SYCAL */
+#define _RAC_SYCAL_SYVCOSLOWNOISEFILTER_slow_noise_filter_1 0x00000001UL /**< Mode slow_noise_filter_1 for RAC_SYCAL */
+#define RAC_SYCAL_SYVCOSLOWNOISEFILTER_DEFAULT (_RAC_SYCAL_SYVCOSLOWNOISEFILTER_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_SYCAL */
+#define RAC_SYCAL_SYVCOSLOWNOISEFILTER_slow_noise_filter_0 (_RAC_SYCAL_SYVCOSLOWNOISEFILTER_slow_noise_filter_0 << 10) /**< Shifted mode slow_noise_filter_0 for RAC_SYCAL*/
+#define RAC_SYCAL_SYVCOSLOWNOISEFILTER_slow_noise_filter_1 (_RAC_SYCAL_SYVCOSLOWNOISEFILTER_slow_noise_filter_1 << 10) /**< Shifted mode slow_noise_filter_1 for RAC_SYCAL*/
+#define _RAC_SYCAL_SYVCOVCAPVCM_SHIFT 15 /**< Shift value for RAC_SYVCOVCAPVCM */
+#define _RAC_SYCAL_SYVCOVCAPVCM_MASK 0x18000UL /**< Bit mask for RAC_SYVCOVCAPVCM */
+#define _RAC_SYCAL_SYVCOVCAPVCM_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_SYCAL */
+#define RAC_SYCAL_SYVCOVCAPVCM_DEFAULT (_RAC_SYCAL_SYVCOVCAPVCM_DEFAULT << 15) /**< Shifted mode DEFAULT for RAC_SYCAL */
+#define _RAC_SYCAL_SYHILOADCHPREG_SHIFT 24 /**< Shift value for RAC_SYHILOADCHPREG */
+#define _RAC_SYCAL_SYHILOADCHPREG_MASK 0x3000000UL /**< Bit mask for RAC_SYHILOADCHPREG */
+#define _RAC_SYCAL_SYHILOADCHPREG_DEFAULT 0x00000001UL /**< Mode DEFAULT for RAC_SYCAL */
+#define _RAC_SYCAL_SYHILOADCHPREG_i_350uA 0x00000000UL /**< Mode i_350uA for RAC_SYCAL */
+#define _RAC_SYCAL_SYHILOADCHPREG_i_500uA 0x00000001UL /**< Mode i_500uA for RAC_SYCAL */
+#define _RAC_SYCAL_SYHILOADCHPREG_i_550uA 0x00000002UL /**< Mode i_550uA for RAC_SYCAL */
+#define _RAC_SYCAL_SYHILOADCHPREG_i_700uA 0x00000003UL /**< Mode i_700uA for RAC_SYCAL */
+#define RAC_SYCAL_SYHILOADCHPREG_DEFAULT (_RAC_SYCAL_SYHILOADCHPREG_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_SYCAL */
+#define RAC_SYCAL_SYHILOADCHPREG_i_350uA (_RAC_SYCAL_SYHILOADCHPREG_i_350uA << 24) /**< Shifted mode i_350uA for RAC_SYCAL */
+#define RAC_SYCAL_SYHILOADCHPREG_i_500uA (_RAC_SYCAL_SYHILOADCHPREG_i_500uA << 24) /**< Shifted mode i_500uA for RAC_SYCAL */
+#define RAC_SYCAL_SYHILOADCHPREG_i_550uA (_RAC_SYCAL_SYHILOADCHPREG_i_550uA << 24) /**< Shifted mode i_550uA for RAC_SYCAL */
+#define RAC_SYCAL_SYHILOADCHPREG_i_700uA (_RAC_SYCAL_SYHILOADCHPREG_i_700uA << 24) /**< Shifted mode i_700uA for RAC_SYCAL */
+
+/* Bit fields for RAC SYEN */
+#define _RAC_SYEN_RESETVALUE 0x00000000UL /**< Default value for RAC_SYEN */
+#define _RAC_SYEN_MASK 0x000067FFUL /**< Mask for RAC_SYEN */
+#define RAC_SYEN_SYCHPEN (0x1UL << 0) /**< SYCHPEN */
+#define _RAC_SYEN_SYCHPEN_SHIFT 0 /**< Shift value for RAC_SYCHPEN */
+#define _RAC_SYEN_SYCHPEN_MASK 0x1UL /**< Bit mask for RAC_SYCHPEN */
+#define _RAC_SYEN_SYCHPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYEN */
+#define _RAC_SYEN_SYCHPEN_disable 0x00000000UL /**< Mode disable for RAC_SYEN */
+#define _RAC_SYEN_SYCHPEN_enable 0x00000001UL /**< Mode enable for RAC_SYEN */
+#define RAC_SYEN_SYCHPEN_DEFAULT (_RAC_SYEN_SYCHPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SYEN */
+#define RAC_SYEN_SYCHPEN_disable (_RAC_SYEN_SYCHPEN_disable << 0) /**< Shifted mode disable for RAC_SYEN */
+#define RAC_SYEN_SYCHPEN_enable (_RAC_SYEN_SYCHPEN_enable << 0) /**< Shifted mode enable for RAC_SYEN */
+#define RAC_SYEN_SYCHPLPENRX (0x1UL << 1) /**< SYCHPLPENRX */
+#define _RAC_SYEN_SYCHPLPENRX_SHIFT 1 /**< Shift value for RAC_SYCHPLPENRX */
+#define _RAC_SYEN_SYCHPLPENRX_MASK 0x2UL /**< Bit mask for RAC_SYCHPLPENRX */
+#define _RAC_SYEN_SYCHPLPENRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYEN */
+#define _RAC_SYEN_SYCHPLPENRX_disable 0x00000000UL /**< Mode disable for RAC_SYEN */
+#define _RAC_SYEN_SYCHPLPENRX_enable 0x00000001UL /**< Mode enable for RAC_SYEN */
+#define RAC_SYEN_SYCHPLPENRX_DEFAULT (_RAC_SYEN_SYCHPLPENRX_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_SYEN */
+#define RAC_SYEN_SYCHPLPENRX_disable (_RAC_SYEN_SYCHPLPENRX_disable << 1) /**< Shifted mode disable for RAC_SYEN */
+#define RAC_SYEN_SYCHPLPENRX_enable (_RAC_SYEN_SYCHPLPENRX_enable << 1) /**< Shifted mode enable for RAC_SYEN */
+#define RAC_SYEN_SYCHPLPENTX (0x1UL << 2) /**< SYCHPLPENTX */
+#define _RAC_SYEN_SYCHPLPENTX_SHIFT 2 /**< Shift value for RAC_SYCHPLPENTX */
+#define _RAC_SYEN_SYCHPLPENTX_MASK 0x4UL /**< Bit mask for RAC_SYCHPLPENTX */
+#define _RAC_SYEN_SYCHPLPENTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYEN */
+#define _RAC_SYEN_SYCHPLPENTX_disable 0x00000000UL /**< Mode disable for RAC_SYEN */
+#define _RAC_SYEN_SYCHPLPENTX_enable 0x00000001UL /**< Mode enable for RAC_SYEN */
+#define RAC_SYEN_SYCHPLPENTX_DEFAULT (_RAC_SYEN_SYCHPLPENTX_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_SYEN */
+#define RAC_SYEN_SYCHPLPENTX_disable (_RAC_SYEN_SYCHPLPENTX_disable << 2) /**< Shifted mode disable for RAC_SYEN */
+#define RAC_SYEN_SYCHPLPENTX_enable (_RAC_SYEN_SYCHPLPENTX_enable << 2) /**< Shifted mode enable for RAC_SYEN */
+#define RAC_SYEN_SYENCHPREG (0x1UL << 3) /**< SYENCHPREG */
+#define _RAC_SYEN_SYENCHPREG_SHIFT 3 /**< Shift value for RAC_SYENCHPREG */
+#define _RAC_SYEN_SYENCHPREG_MASK 0x8UL /**< Bit mask for RAC_SYENCHPREG */
+#define _RAC_SYEN_SYENCHPREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYEN */
+#define _RAC_SYEN_SYENCHPREG_Disable 0x00000000UL /**< Mode Disable for RAC_SYEN */
+#define _RAC_SYEN_SYENCHPREG_Enable 0x00000001UL /**< Mode Enable for RAC_SYEN */
+#define RAC_SYEN_SYENCHPREG_DEFAULT (_RAC_SYEN_SYENCHPREG_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_SYEN */
+#define RAC_SYEN_SYENCHPREG_Disable (_RAC_SYEN_SYENCHPREG_Disable << 3) /**< Shifted mode Disable for RAC_SYEN */
+#define RAC_SYEN_SYENCHPREG_Enable (_RAC_SYEN_SYENCHPREG_Enable << 3) /**< Shifted mode Enable for RAC_SYEN */
+#define RAC_SYEN_SYENCHPREPLICA (0x1UL << 4) /**< SYENCHPREPLICA */
+#define _RAC_SYEN_SYENCHPREPLICA_SHIFT 4 /**< Shift value for RAC_SYENCHPREPLICA */
+#define _RAC_SYEN_SYENCHPREPLICA_MASK 0x10UL /**< Bit mask for RAC_SYENCHPREPLICA */
+#define _RAC_SYEN_SYENCHPREPLICA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYEN */
+#define _RAC_SYEN_SYENCHPREPLICA_disable 0x00000000UL /**< Mode disable for RAC_SYEN */
+#define _RAC_SYEN_SYENCHPREPLICA_enable 0x00000001UL /**< Mode enable for RAC_SYEN */
+#define RAC_SYEN_SYENCHPREPLICA_DEFAULT (_RAC_SYEN_SYENCHPREPLICA_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_SYEN */
+#define RAC_SYEN_SYENCHPREPLICA_disable (_RAC_SYEN_SYENCHPREPLICA_disable << 4) /**< Shifted mode disable for RAC_SYEN */
+#define RAC_SYEN_SYENCHPREPLICA_enable (_RAC_SYEN_SYENCHPREPLICA_enable << 4) /**< Shifted mode enable for RAC_SYEN */
+#define RAC_SYEN_SYENMMDREG (0x1UL << 5) /**< SYENMMDREG */
+#define _RAC_SYEN_SYENMMDREG_SHIFT 5 /**< Shift value for RAC_SYENMMDREG */
+#define _RAC_SYEN_SYENMMDREG_MASK 0x20UL /**< Bit mask for RAC_SYENMMDREG */
+#define _RAC_SYEN_SYENMMDREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYEN */
+#define _RAC_SYEN_SYENMMDREG_Disable 0x00000000UL /**< Mode Disable for RAC_SYEN */
+#define _RAC_SYEN_SYENMMDREG_Enable 0x00000001UL /**< Mode Enable for RAC_SYEN */
+#define RAC_SYEN_SYENMMDREG_DEFAULT (_RAC_SYEN_SYENMMDREG_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_SYEN */
+#define RAC_SYEN_SYENMMDREG_Disable (_RAC_SYEN_SYENMMDREG_Disable << 5) /**< Shifted mode Disable for RAC_SYEN */
+#define RAC_SYEN_SYENMMDREG_Enable (_RAC_SYEN_SYENMMDREG_Enable << 5) /**< Shifted mode Enable for RAC_SYEN */
+#define RAC_SYEN_SYENMMDREPLICA1 (0x1UL << 6) /**< SYENMMDREPLICA1 */
+#define _RAC_SYEN_SYENMMDREPLICA1_SHIFT 6 /**< Shift value for RAC_SYENMMDREPLICA1 */
+#define _RAC_SYEN_SYENMMDREPLICA1_MASK 0x40UL /**< Bit mask for RAC_SYENMMDREPLICA1 */
+#define _RAC_SYEN_SYENMMDREPLICA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYEN */
+#define _RAC_SYEN_SYENMMDREPLICA1_disable 0x00000000UL /**< Mode disable for RAC_SYEN */
+#define _RAC_SYEN_SYENMMDREPLICA1_enable 0x00000001UL /**< Mode enable for RAC_SYEN */
+#define RAC_SYEN_SYENMMDREPLICA1_DEFAULT (_RAC_SYEN_SYENMMDREPLICA1_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_SYEN */
+#define RAC_SYEN_SYENMMDREPLICA1_disable (_RAC_SYEN_SYENMMDREPLICA1_disable << 6) /**< Shifted mode disable for RAC_SYEN */
+#define RAC_SYEN_SYENMMDREPLICA1_enable (_RAC_SYEN_SYENMMDREPLICA1_enable << 6) /**< Shifted mode enable for RAC_SYEN */
+#define RAC_SYEN_SYENMMDREPLICA2 (0x1UL << 7) /**< SYENMMDREPLICA2 */
+#define _RAC_SYEN_SYENMMDREPLICA2_SHIFT 7 /**< Shift value for RAC_SYENMMDREPLICA2 */
+#define _RAC_SYEN_SYENMMDREPLICA2_MASK 0x80UL /**< Bit mask for RAC_SYENMMDREPLICA2 */
+#define _RAC_SYEN_SYENMMDREPLICA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYEN */
+#define _RAC_SYEN_SYENMMDREPLICA2_Disable 0x00000000UL /**< Mode Disable for RAC_SYEN */
+#define _RAC_SYEN_SYENMMDREPLICA2_Enable 0x00000001UL /**< Mode Enable for RAC_SYEN */
+#define RAC_SYEN_SYENMMDREPLICA2_DEFAULT (_RAC_SYEN_SYENMMDREPLICA2_DEFAULT << 7) /**< Shifted mode DEFAULT for RAC_SYEN */
+#define RAC_SYEN_SYENMMDREPLICA2_Disable (_RAC_SYEN_SYENMMDREPLICA2_Disable << 7) /**< Shifted mode Disable for RAC_SYEN */
+#define RAC_SYEN_SYENMMDREPLICA2_Enable (_RAC_SYEN_SYENMMDREPLICA2_Enable << 7) /**< Shifted mode Enable for RAC_SYEN */
+#define RAC_SYEN_SYENVCOBIAS (0x1UL << 8) /**< SYENVCOBIAS */
+#define _RAC_SYEN_SYENVCOBIAS_SHIFT 8 /**< Shift value for RAC_SYENVCOBIAS */
+#define _RAC_SYEN_SYENVCOBIAS_MASK 0x100UL /**< Bit mask for RAC_SYENVCOBIAS */
+#define _RAC_SYEN_SYENVCOBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYEN */
+#define _RAC_SYEN_SYENVCOBIAS_en_vco_bias_0 0x00000000UL /**< Mode en_vco_bias_0 for RAC_SYEN */
+#define _RAC_SYEN_SYENVCOBIAS_en_vco_bias_1 0x00000001UL /**< Mode en_vco_bias_1 for RAC_SYEN */
+#define RAC_SYEN_SYENVCOBIAS_DEFAULT (_RAC_SYEN_SYENVCOBIAS_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_SYEN */
+#define RAC_SYEN_SYENVCOBIAS_en_vco_bias_0 (_RAC_SYEN_SYENVCOBIAS_en_vco_bias_0 << 8) /**< Shifted mode en_vco_bias_0 for RAC_SYEN */
+#define RAC_SYEN_SYENVCOBIAS_en_vco_bias_1 (_RAC_SYEN_SYENVCOBIAS_en_vco_bias_1 << 8) /**< Shifted mode en_vco_bias_1 for RAC_SYEN */
+#define RAC_SYEN_SYENVCOPFET (0x1UL << 9) /**< SYENVCOPFET */
+#define _RAC_SYEN_SYENVCOPFET_SHIFT 9 /**< Shift value for RAC_SYENVCOPFET */
+#define _RAC_SYEN_SYENVCOPFET_MASK 0x200UL /**< Bit mask for RAC_SYENVCOPFET */
+#define _RAC_SYEN_SYENVCOPFET_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYEN */
+#define _RAC_SYEN_SYENVCOPFET_en_vco_pfet_0 0x00000000UL /**< Mode en_vco_pfet_0 for RAC_SYEN */
+#define _RAC_SYEN_SYENVCOPFET_en_vco_pfet_1 0x00000001UL /**< Mode en_vco_pfet_1 for RAC_SYEN */
+#define RAC_SYEN_SYENVCOPFET_DEFAULT (_RAC_SYEN_SYENVCOPFET_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_SYEN */
+#define RAC_SYEN_SYENVCOPFET_en_vco_pfet_0 (_RAC_SYEN_SYENVCOPFET_en_vco_pfet_0 << 9) /**< Shifted mode en_vco_pfet_0 for RAC_SYEN */
+#define RAC_SYEN_SYENVCOPFET_en_vco_pfet_1 (_RAC_SYEN_SYENVCOPFET_en_vco_pfet_1 << 9) /**< Shifted mode en_vco_pfet_1 for RAC_SYEN */
+#define RAC_SYEN_SYENVCOREG (0x1UL << 10) /**< SYENVCOREG */
+#define _RAC_SYEN_SYENVCOREG_SHIFT 10 /**< Shift value for RAC_SYENVCOREG */
+#define _RAC_SYEN_SYENVCOREG_MASK 0x400UL /**< Bit mask for RAC_SYENVCOREG */
+#define _RAC_SYEN_SYENVCOREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYEN */
+#define _RAC_SYEN_SYENVCOREG_en_vco_reg_0 0x00000000UL /**< Mode en_vco_reg_0 for RAC_SYEN */
+#define _RAC_SYEN_SYENVCOREG_en_vco_reg_1 0x00000001UL /**< Mode en_vco_reg_1 for RAC_SYEN */
+#define RAC_SYEN_SYENVCOREG_DEFAULT (_RAC_SYEN_SYENVCOREG_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_SYEN */
+#define RAC_SYEN_SYENVCOREG_en_vco_reg_0 (_RAC_SYEN_SYENVCOREG_en_vco_reg_0 << 10) /**< Shifted mode en_vco_reg_0 for RAC_SYEN */
+#define RAC_SYEN_SYENVCOREG_en_vco_reg_1 (_RAC_SYEN_SYENVCOREG_en_vco_reg_1 << 10) /**< Shifted mode en_vco_reg_1 for RAC_SYEN */
+#define RAC_SYEN_SYSTARTCHPREG (0x1UL << 13) /**< SYSTARTCHPREG */
+#define _RAC_SYEN_SYSTARTCHPREG_SHIFT 13 /**< Shift value for RAC_SYSTARTCHPREG */
+#define _RAC_SYEN_SYSTARTCHPREG_MASK 0x2000UL /**< Bit mask for RAC_SYSTARTCHPREG */
+#define _RAC_SYEN_SYSTARTCHPREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYEN */
+#define _RAC_SYEN_SYSTARTCHPREG_no_fast_startup 0x00000000UL /**< Mode no_fast_startup for RAC_SYEN */
+#define _RAC_SYEN_SYSTARTCHPREG_fast_startup 0x00000001UL /**< Mode fast_startup for RAC_SYEN */
+#define RAC_SYEN_SYSTARTCHPREG_DEFAULT (_RAC_SYEN_SYSTARTCHPREG_DEFAULT << 13) /**< Shifted mode DEFAULT for RAC_SYEN */
+#define RAC_SYEN_SYSTARTCHPREG_no_fast_startup (_RAC_SYEN_SYSTARTCHPREG_no_fast_startup << 13) /**< Shifted mode no_fast_startup for RAC_SYEN */
+#define RAC_SYEN_SYSTARTCHPREG_fast_startup (_RAC_SYEN_SYSTARTCHPREG_fast_startup << 13) /**< Shifted mode fast_startup for RAC_SYEN */
+#define RAC_SYEN_SYSTARTMMDREG (0x1UL << 14) /**< SYSTARTMMDREG */
+#define _RAC_SYEN_SYSTARTMMDREG_SHIFT 14 /**< Shift value for RAC_SYSTARTMMDREG */
+#define _RAC_SYEN_SYSTARTMMDREG_MASK 0x4000UL /**< Bit mask for RAC_SYSTARTMMDREG */
+#define _RAC_SYEN_SYSTARTMMDREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYEN */
+#define _RAC_SYEN_SYSTARTMMDREG_no_fast_startup 0x00000000UL /**< Mode no_fast_startup for RAC_SYEN */
+#define _RAC_SYEN_SYSTARTMMDREG_fast_startup 0x00000001UL /**< Mode fast_startup for RAC_SYEN */
+#define RAC_SYEN_SYSTARTMMDREG_DEFAULT (_RAC_SYEN_SYSTARTMMDREG_DEFAULT << 14) /**< Shifted mode DEFAULT for RAC_SYEN */
+#define RAC_SYEN_SYSTARTMMDREG_no_fast_startup (_RAC_SYEN_SYSTARTMMDREG_no_fast_startup << 14) /**< Shifted mode no_fast_startup for RAC_SYEN */
+#define RAC_SYEN_SYSTARTMMDREG_fast_startup (_RAC_SYEN_SYSTARTMMDREG_fast_startup << 14) /**< Shifted mode fast_startup for RAC_SYEN */
+
+/* Bit fields for RAC SYLOEN */
+#define _RAC_SYLOEN_RESETVALUE 0x00000000UL /**< Default value for RAC_SYLOEN */
+#define _RAC_SYLOEN_MASK 0x00001F1EUL /**< Mask for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVEN (0x1UL << 1) /**< SYLODIVEN */
+#define _RAC_SYLOEN_SYLODIVEN_SHIFT 1 /**< Shift value for RAC_SYLODIVEN */
+#define _RAC_SYLOEN_SYLODIVEN_MASK 0x2UL /**< Bit mask for RAC_SYLODIVEN */
+#define _RAC_SYLOEN_SYLODIVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYLOEN */
+#define _RAC_SYLOEN_SYLODIVEN_disable 0x00000000UL /**< Mode disable for RAC_SYLOEN */
+#define _RAC_SYLOEN_SYLODIVEN_enable 0x00000001UL /**< Mode enable for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVEN_DEFAULT (_RAC_SYLOEN_SYLODIVEN_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVEN_disable (_RAC_SYLOEN_SYLODIVEN_disable << 1) /**< Shifted mode disable for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVEN_enable (_RAC_SYLOEN_SYLODIVEN_enable << 1) /**< Shifted mode enable for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVLDOBIASEN (0x1UL << 2) /**< SYLODIVLDOBIASEN */
+#define _RAC_SYLOEN_SYLODIVLDOBIASEN_SHIFT 2 /**< Shift value for RAC_SYLODIVLDOBIASEN */
+#define _RAC_SYLOEN_SYLODIVLDOBIASEN_MASK 0x4UL /**< Bit mask for RAC_SYLODIVLDOBIASEN */
+#define _RAC_SYLOEN_SYLODIVLDOBIASEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYLOEN */
+#define _RAC_SYLOEN_SYLODIVLDOBIASEN_disable 0x00000000UL /**< Mode disable for RAC_SYLOEN */
+#define _RAC_SYLOEN_SYLODIVLDOBIASEN_enable 0x00000001UL /**< Mode enable for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVLDOBIASEN_DEFAULT (_RAC_SYLOEN_SYLODIVLDOBIASEN_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVLDOBIASEN_disable (_RAC_SYLOEN_SYLODIVLDOBIASEN_disable << 2) /**< Shifted mode disable for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVLDOBIASEN_enable (_RAC_SYLOEN_SYLODIVLDOBIASEN_enable << 2) /**< Shifted mode enable for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVLDOEN (0x1UL << 3) /**< SYLODIVLDOEN */
+#define _RAC_SYLOEN_SYLODIVLDOEN_SHIFT 3 /**< Shift value for RAC_SYLODIVLDOEN */
+#define _RAC_SYLOEN_SYLODIVLDOEN_MASK 0x8UL /**< Bit mask for RAC_SYLODIVLDOEN */
+#define _RAC_SYLOEN_SYLODIVLDOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYLOEN */
+#define _RAC_SYLOEN_SYLODIVLDOEN_disable 0x00000000UL /**< Mode disable for RAC_SYLOEN */
+#define _RAC_SYLOEN_SYLODIVLDOEN_enable 0x00000001UL /**< Mode enable for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVLDOEN_DEFAULT (_RAC_SYLOEN_SYLODIVLDOEN_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVLDOEN_disable (_RAC_SYLOEN_SYLODIVLDOEN_disable << 3) /**< Shifted mode disable for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVLDOEN_enable (_RAC_SYLOEN_SYLODIVLDOEN_enable << 3) /**< Shifted mode enable for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVRLOADCCLK2G4EN (0x1UL << 4) /**< SYLODIVRLOADCCLK2G4EN */
+#define _RAC_SYLOEN_SYLODIVRLOADCCLK2G4EN_SHIFT 4 /**< Shift value for RAC_SYLODIVRLOADCCLK2G4EN */
+#define _RAC_SYLOEN_SYLODIVRLOADCCLK2G4EN_MASK 0x10UL /**< Bit mask for RAC_SYLODIVRLOADCCLK2G4EN */
+#define _RAC_SYLOEN_SYLODIVRLOADCCLK2G4EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYLOEN */
+#define _RAC_SYLOEN_SYLODIVRLOADCCLK2G4EN_disable 0x00000000UL /**< Mode disable for RAC_SYLOEN */
+#define _RAC_SYLOEN_SYLODIVRLOADCCLK2G4EN_enable 0x00000001UL /**< Mode enable for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVRLOADCCLK2G4EN_DEFAULT (_RAC_SYLOEN_SYLODIVRLOADCCLK2G4EN_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVRLOADCCLK2G4EN_disable (_RAC_SYLOEN_SYLODIVRLOADCCLK2G4EN_disable << 4) /**< Shifted mode disable for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVRLOADCCLK2G4EN_enable (_RAC_SYLOEN_SYLODIVRLOADCCLK2G4EN_enable << 4) /**< Shifted mode enable for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVTLO0DBM2G4AUXEN (0x1UL << 8) /**< SYLODIVTLO0DBM2G4AUXEN */
+#define _RAC_SYLOEN_SYLODIVTLO0DBM2G4AUXEN_SHIFT 8 /**< Shift value for RAC_SYLODIVTLO0DBM2G4AUXEN */
+#define _RAC_SYLOEN_SYLODIVTLO0DBM2G4AUXEN_MASK 0x100UL /**< Bit mask for RAC_SYLODIVTLO0DBM2G4AUXEN */
+#define _RAC_SYLOEN_SYLODIVTLO0DBM2G4AUXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYLOEN */
+#define _RAC_SYLOEN_SYLODIVTLO0DBM2G4AUXEN_disable 0x00000000UL /**< Mode disable for RAC_SYLOEN */
+#define _RAC_SYLOEN_SYLODIVTLO0DBM2G4AUXEN_enable 0x00000001UL /**< Mode enable for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVTLO0DBM2G4AUXEN_DEFAULT (_RAC_SYLOEN_SYLODIVTLO0DBM2G4AUXEN_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVTLO0DBM2G4AUXEN_disable (_RAC_SYLOEN_SYLODIVTLO0DBM2G4AUXEN_disable << 8) /**< Shifted mode disable for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVTLO0DBM2G4AUXEN_enable (_RAC_SYLOEN_SYLODIVTLO0DBM2G4AUXEN_enable << 8) /**< Shifted mode enable for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVTLO0DBM2G4EN (0x1UL << 9) /**< SYLODIVTLO0DBM2G4EN */
+#define _RAC_SYLOEN_SYLODIVTLO0DBM2G4EN_SHIFT 9 /**< Shift value for RAC_SYLODIVTLO0DBM2G4EN */
+#define _RAC_SYLOEN_SYLODIVTLO0DBM2G4EN_MASK 0x200UL /**< Bit mask for RAC_SYLODIVTLO0DBM2G4EN */
+#define _RAC_SYLOEN_SYLODIVTLO0DBM2G4EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYLOEN */
+#define _RAC_SYLOEN_SYLODIVTLO0DBM2G4EN_disable 0x00000000UL /**< Mode disable for RAC_SYLOEN */
+#define _RAC_SYLOEN_SYLODIVTLO0DBM2G4EN_enable 0x00000001UL /**< Mode enable for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVTLO0DBM2G4EN_DEFAULT (_RAC_SYLOEN_SYLODIVTLO0DBM2G4EN_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVTLO0DBM2G4EN_disable (_RAC_SYLOEN_SYLODIVTLO0DBM2G4EN_disable << 9) /**< Shifted mode disable for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVTLO0DBM2G4EN_enable (_RAC_SYLOEN_SYLODIVTLO0DBM2G4EN_enable << 9) /**< Shifted mode enable for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVTLO20DBM2G4AUXEN (0x1UL << 10) /**< SYLODIVTLO20DBM2G4AUXEN */
+#define _RAC_SYLOEN_SYLODIVTLO20DBM2G4AUXEN_SHIFT 10 /**< Shift value for RAC_SYLODIVTLO20DBM2G4AUXEN */
+#define _RAC_SYLOEN_SYLODIVTLO20DBM2G4AUXEN_MASK 0x400UL /**< Bit mask for RAC_SYLODIVTLO20DBM2G4AUXEN */
+#define _RAC_SYLOEN_SYLODIVTLO20DBM2G4AUXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYLOEN */
+#define _RAC_SYLOEN_SYLODIVTLO20DBM2G4AUXEN_disable 0x00000000UL /**< Mode disable for RAC_SYLOEN */
+#define _RAC_SYLOEN_SYLODIVTLO20DBM2G4AUXEN_enable 0x00000001UL /**< Mode enable for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVTLO20DBM2G4AUXEN_DEFAULT (_RAC_SYLOEN_SYLODIVTLO20DBM2G4AUXEN_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVTLO20DBM2G4AUXEN_disable (_RAC_SYLOEN_SYLODIVTLO20DBM2G4AUXEN_disable << 10) /**< Shifted mode disable for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVTLO20DBM2G4AUXEN_enable (_RAC_SYLOEN_SYLODIVTLO20DBM2G4AUXEN_enable << 10) /**< Shifted mode enable for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVTLO20DBM2G4EN (0x1UL << 11) /**< SYLODIVTLO20DBM2G4EN */
+#define _RAC_SYLOEN_SYLODIVTLO20DBM2G4EN_SHIFT 11 /**< Shift value for RAC_SYLODIVTLO20DBM2G4EN */
+#define _RAC_SYLOEN_SYLODIVTLO20DBM2G4EN_MASK 0x800UL /**< Bit mask for RAC_SYLODIVTLO20DBM2G4EN */
+#define _RAC_SYLOEN_SYLODIVTLO20DBM2G4EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYLOEN */
+#define _RAC_SYLOEN_SYLODIVTLO20DBM2G4EN_disable 0x00000000UL /**< Mode disable for RAC_SYLOEN */
+#define _RAC_SYLOEN_SYLODIVTLO20DBM2G4EN_enable 0x00000001UL /**< Mode enable for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVTLO20DBM2G4EN_DEFAULT (_RAC_SYLOEN_SYLODIVTLO20DBM2G4EN_DEFAULT << 11) /**< Shifted mode DEFAULT for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVTLO20DBM2G4EN_disable (_RAC_SYLOEN_SYLODIVTLO20DBM2G4EN_disable << 11) /**< Shifted mode disable for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVTLO20DBM2G4EN_enable (_RAC_SYLOEN_SYLODIVTLO20DBM2G4EN_enable << 11) /**< Shifted mode enable for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVRLOADCCLKSEL (0x1UL << 12) /**< SYLODIVRLOADCCLKSEL */
+#define _RAC_SYLOEN_SYLODIVRLOADCCLKSEL_SHIFT 12 /**< Shift value for RAC_SYLODIVRLOADCCLKSEL */
+#define _RAC_SYLOEN_SYLODIVRLOADCCLKSEL_MASK 0x1000UL /**< Bit mask for RAC_SYLODIVRLOADCCLKSEL */
+#define _RAC_SYLOEN_SYLODIVRLOADCCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYLOEN */
+#define _RAC_SYLOEN_SYLODIVRLOADCCLKSEL_adc_clk_div8 0x00000000UL /**< Mode adc_clk_div8 for RAC_SYLOEN */
+#define _RAC_SYLOEN_SYLODIVRLOADCCLKSEL_adc_clk_div16 0x00000001UL /**< Mode adc_clk_div16 for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVRLOADCCLKSEL_DEFAULT (_RAC_SYLOEN_SYLODIVRLOADCCLKSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVRLOADCCLKSEL_adc_clk_div8 (_RAC_SYLOEN_SYLODIVRLOADCCLKSEL_adc_clk_div8 << 12) /**< Shifted mode adc_clk_div8 for RAC_SYLOEN */
+#define RAC_SYLOEN_SYLODIVRLOADCCLKSEL_adc_clk_div16 (_RAC_SYLOEN_SYLODIVRLOADCCLKSEL_adc_clk_div16 << 12) /**< Shifted mode adc_clk_div16 for RAC_SYLOEN */
+
+/* Bit fields for RAC SYMMDCTRL */
+#define _RAC_SYMMDCTRL_RESETVALUE 0x00000048UL /**< Default value for RAC_SYMMDCTRL */
+#define _RAC_SYMMDCTRL_MASK 0x000001FFUL /**< Mask for RAC_SYMMDCTRL */
+#define _RAC_SYMMDCTRL_SYMMDDIVRSDIG_SHIFT 0 /**< Shift value for RAC_SYMMDDIVRSDIG */
+#define _RAC_SYMMDCTRL_SYMMDDIVRSDIG_MASK 0x3UL /**< Bit mask for RAC_SYMMDDIVRSDIG */
+#define _RAC_SYMMDCTRL_SYMMDDIVRSDIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYMMDCTRL */
+#define _RAC_SYMMDCTRL_SYMMDDIVRSDIG_Divideby1 0x00000000UL /**< Mode Divideby1 for RAC_SYMMDCTRL */
+#define _RAC_SYMMDCTRL_SYMMDDIVRSDIG_Divideby2 0x00000001UL /**< Mode Divideby2 for RAC_SYMMDCTRL */
+#define _RAC_SYMMDCTRL_SYMMDDIVRSDIG_Divideby4 0x00000002UL /**< Mode Divideby4 for RAC_SYMMDCTRL */
+#define _RAC_SYMMDCTRL_SYMMDDIVRSDIG_Divideby8 0x00000003UL /**< Mode Divideby8 for RAC_SYMMDCTRL */
+#define RAC_SYMMDCTRL_SYMMDDIVRSDIG_DEFAULT (_RAC_SYMMDCTRL_SYMMDDIVRSDIG_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SYMMDCTRL */
+#define RAC_SYMMDCTRL_SYMMDDIVRSDIG_Divideby1 (_RAC_SYMMDCTRL_SYMMDDIVRSDIG_Divideby1 << 0) /**< Shifted mode Divideby1 for RAC_SYMMDCTRL */
+#define RAC_SYMMDCTRL_SYMMDDIVRSDIG_Divideby2 (_RAC_SYMMDCTRL_SYMMDDIVRSDIG_Divideby2 << 0) /**< Shifted mode Divideby2 for RAC_SYMMDCTRL */
+#define RAC_SYMMDCTRL_SYMMDDIVRSDIG_Divideby4 (_RAC_SYMMDCTRL_SYMMDDIVRSDIG_Divideby4 << 0) /**< Shifted mode Divideby4 for RAC_SYMMDCTRL */
+#define RAC_SYMMDCTRL_SYMMDDIVRSDIG_Divideby8 (_RAC_SYMMDCTRL_SYMMDDIVRSDIG_Divideby8 << 0) /**< Shifted mode Divideby8 for RAC_SYMMDCTRL */
+#define _RAC_SYMMDCTRL_SYMMDMODERX_SHIFT 2 /**< Shift value for RAC_SYMMDMODERX */
+#define _RAC_SYMMDCTRL_SYMMDMODERX_MASK 0x1CUL /**< Bit mask for RAC_SYMMDMODERX */
+#define _RAC_SYMMDCTRL_SYMMDMODERX_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_SYMMDCTRL */
+#define _RAC_SYMMDCTRL_SYMMDMODERX_rx_w_swctrl 0x00000000UL /**< Mode rx_w_swctrl for RAC_SYMMDCTRL */
+#define _RAC_SYMMDCTRL_SYMMDMODERX_rx_wo_swctrl 0x00000001UL /**< Mode rx_wo_swctrl for RAC_SYMMDCTRL */
+#define _RAC_SYMMDCTRL_SYMMDMODERX_qnc_dsm2 0x00000002UL /**< Mode qnc_dsm2 for RAC_SYMMDCTRL */
+#define _RAC_SYMMDCTRL_SYMMDMODERX_qnc_dsm3 0x00000003UL /**< Mode qnc_dsm3 for RAC_SYMMDCTRL */
+#define _RAC_SYMMDCTRL_SYMMDMODERX_rxlp_wo_swctrl 0x00000004UL /**< Mode rxlp_wo_swctrl for RAC_SYMMDCTRL */
+#define _RAC_SYMMDCTRL_SYMMDMODERX_notuse_5 0x00000005UL /**< Mode notuse_5 for RAC_SYMMDCTRL */
+#define _RAC_SYMMDCTRL_SYMMDMODERX_notuse_6 0x00000006UL /**< Mode notuse_6 for RAC_SYMMDCTRL */
+#define _RAC_SYMMDCTRL_SYMMDMODERX_notuse_7 0x00000007UL /**< Mode notuse_7 for RAC_SYMMDCTRL */
+#define RAC_SYMMDCTRL_SYMMDMODERX_DEFAULT (_RAC_SYMMDCTRL_SYMMDMODERX_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_SYMMDCTRL */
+#define RAC_SYMMDCTRL_SYMMDMODERX_rx_w_swctrl (_RAC_SYMMDCTRL_SYMMDMODERX_rx_w_swctrl << 2) /**< Shifted mode rx_w_swctrl for RAC_SYMMDCTRL */
+#define RAC_SYMMDCTRL_SYMMDMODERX_rx_wo_swctrl (_RAC_SYMMDCTRL_SYMMDMODERX_rx_wo_swctrl << 2) /**< Shifted mode rx_wo_swctrl for RAC_SYMMDCTRL */
+#define RAC_SYMMDCTRL_SYMMDMODERX_qnc_dsm2 (_RAC_SYMMDCTRL_SYMMDMODERX_qnc_dsm2 << 2) /**< Shifted mode qnc_dsm2 for RAC_SYMMDCTRL */
+#define RAC_SYMMDCTRL_SYMMDMODERX_qnc_dsm3 (_RAC_SYMMDCTRL_SYMMDMODERX_qnc_dsm3 << 2) /**< Shifted mode qnc_dsm3 for RAC_SYMMDCTRL */
+#define RAC_SYMMDCTRL_SYMMDMODERX_rxlp_wo_swctrl (_RAC_SYMMDCTRL_SYMMDMODERX_rxlp_wo_swctrl << 2) /**< Shifted mode rxlp_wo_swctrl for RAC_SYMMDCTRL*/
+#define RAC_SYMMDCTRL_SYMMDMODERX_notuse_5 (_RAC_SYMMDCTRL_SYMMDMODERX_notuse_5 << 2) /**< Shifted mode notuse_5 for RAC_SYMMDCTRL */
+#define RAC_SYMMDCTRL_SYMMDMODERX_notuse_6 (_RAC_SYMMDCTRL_SYMMDMODERX_notuse_6 << 2) /**< Shifted mode notuse_6 for RAC_SYMMDCTRL */
+#define RAC_SYMMDCTRL_SYMMDMODERX_notuse_7 (_RAC_SYMMDCTRL_SYMMDMODERX_notuse_7 << 2) /**< Shifted mode notuse_7 for RAC_SYMMDCTRL */
+#define _RAC_SYMMDCTRL_SYMMDMODETX_SHIFT 5 /**< Shift value for RAC_SYMMDMODETX */
+#define _RAC_SYMMDCTRL_SYMMDMODETX_MASK 0xE0UL /**< Bit mask for RAC_SYMMDMODETX */
+#define _RAC_SYMMDCTRL_SYMMDMODETX_DEFAULT 0x00000002UL /**< Mode DEFAULT for RAC_SYMMDCTRL */
+#define _RAC_SYMMDCTRL_SYMMDMODETX_rx_w_swctrl 0x00000000UL /**< Mode rx_w_swctrl for RAC_SYMMDCTRL */
+#define _RAC_SYMMDCTRL_SYMMDMODETX_rx_wo_swctrl 0x00000001UL /**< Mode rx_wo_swctrl for RAC_SYMMDCTRL */
+#define _RAC_SYMMDCTRL_SYMMDMODETX_qnc_dsm2 0x00000002UL /**< Mode qnc_dsm2 for RAC_SYMMDCTRL */
+#define _RAC_SYMMDCTRL_SYMMDMODETX_qnc_dsm3 0x00000003UL /**< Mode qnc_dsm3 for RAC_SYMMDCTRL */
+#define _RAC_SYMMDCTRL_SYMMDMODETX_rxlp_wo_swctrl 0x00000004UL /**< Mode rxlp_wo_swctrl for RAC_SYMMDCTRL */
+#define _RAC_SYMMDCTRL_SYMMDMODETX_notuse_5 0x00000005UL /**< Mode notuse_5 for RAC_SYMMDCTRL */
+#define _RAC_SYMMDCTRL_SYMMDMODETX_notuse_6 0x00000006UL /**< Mode notuse_6 for RAC_SYMMDCTRL */
+#define _RAC_SYMMDCTRL_SYMMDMODETX_notuse_7 0x00000007UL /**< Mode notuse_7 for RAC_SYMMDCTRL */
+#define RAC_SYMMDCTRL_SYMMDMODETX_DEFAULT (_RAC_SYMMDCTRL_SYMMDMODETX_DEFAULT << 5) /**< Shifted mode DEFAULT for RAC_SYMMDCTRL */
+#define RAC_SYMMDCTRL_SYMMDMODETX_rx_w_swctrl (_RAC_SYMMDCTRL_SYMMDMODETX_rx_w_swctrl << 5) /**< Shifted mode rx_w_swctrl for RAC_SYMMDCTRL */
+#define RAC_SYMMDCTRL_SYMMDMODETX_rx_wo_swctrl (_RAC_SYMMDCTRL_SYMMDMODETX_rx_wo_swctrl << 5) /**< Shifted mode rx_wo_swctrl for RAC_SYMMDCTRL */
+#define RAC_SYMMDCTRL_SYMMDMODETX_qnc_dsm2 (_RAC_SYMMDCTRL_SYMMDMODETX_qnc_dsm2 << 5) /**< Shifted mode qnc_dsm2 for RAC_SYMMDCTRL */
+#define RAC_SYMMDCTRL_SYMMDMODETX_qnc_dsm3 (_RAC_SYMMDCTRL_SYMMDMODETX_qnc_dsm3 << 5) /**< Shifted mode qnc_dsm3 for RAC_SYMMDCTRL */
+#define RAC_SYMMDCTRL_SYMMDMODETX_rxlp_wo_swctrl (_RAC_SYMMDCTRL_SYMMDMODETX_rxlp_wo_swctrl << 5) /**< Shifted mode rxlp_wo_swctrl for RAC_SYMMDCTRL*/
+#define RAC_SYMMDCTRL_SYMMDMODETX_notuse_5 (_RAC_SYMMDCTRL_SYMMDMODETX_notuse_5 << 5) /**< Shifted mode notuse_5 for RAC_SYMMDCTRL */
+#define RAC_SYMMDCTRL_SYMMDMODETX_notuse_6 (_RAC_SYMMDCTRL_SYMMDMODETX_notuse_6 << 5) /**< Shifted mode notuse_6 for RAC_SYMMDCTRL */
+#define RAC_SYMMDCTRL_SYMMDMODETX_notuse_7 (_RAC_SYMMDCTRL_SYMMDMODETX_notuse_7 << 5) /**< Shifted mode notuse_7 for RAC_SYMMDCTRL */
+#define RAC_SYMMDCTRL_SYMMDENRSDIG (0x1UL << 8) /**< SYMMDENRSDIG */
+#define _RAC_SYMMDCTRL_SYMMDENRSDIG_SHIFT 8 /**< Shift value for RAC_SYMMDENRSDIG */
+#define _RAC_SYMMDCTRL_SYMMDENRSDIG_MASK 0x100UL /**< Bit mask for RAC_SYMMDENRSDIG */
+#define _RAC_SYMMDCTRL_SYMMDENRSDIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SYMMDCTRL */
+#define _RAC_SYMMDCTRL_SYMMDENRSDIG_disable 0x00000000UL /**< Mode disable for RAC_SYMMDCTRL */
+#define _RAC_SYMMDCTRL_SYMMDENRSDIG_enable 0x00000001UL /**< Mode enable for RAC_SYMMDCTRL */
+#define RAC_SYMMDCTRL_SYMMDENRSDIG_DEFAULT (_RAC_SYMMDCTRL_SYMMDENRSDIG_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_SYMMDCTRL */
+#define RAC_SYMMDCTRL_SYMMDENRSDIG_disable (_RAC_SYMMDCTRL_SYMMDENRSDIG_disable << 8) /**< Shifted mode disable for RAC_SYMMDCTRL */
+#define RAC_SYMMDCTRL_SYMMDENRSDIG_enable (_RAC_SYMMDCTRL_SYMMDENRSDIG_enable << 8) /**< Shifted mode enable for RAC_SYMMDCTRL */
+
+/* Bit fields for RAC DIGCLKRETIMECTRL */
+#define _RAC_DIGCLKRETIMECTRL_RESETVALUE 0x00000000UL /**< Default value for RAC_DIGCLKRETIMECTRL */
+#define _RAC_DIGCLKRETIMECTRL_MASK 0x00000777UL /**< Mask for RAC_DIGCLKRETIMECTRL */
+#define RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEENRETIME (0x1UL << 0) /**< DIGCLKRETIMEENRETIME */
+#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEENRETIME_SHIFT 0 /**< Shift value for RAC_DIGCLKRETIMEENRETIME */
+#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEENRETIME_MASK 0x1UL /**< Bit mask for RAC_DIGCLKRETIMEENRETIME */
+#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEENRETIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_DIGCLKRETIMECTRL */
+#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEENRETIME_disable 0x00000000UL /**< Mode disable for RAC_DIGCLKRETIMECTRL */
+#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEENRETIME_enable 0x00000001UL /**< Mode enable for RAC_DIGCLKRETIMECTRL */
+#define RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEENRETIME_DEFAULT (_RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEENRETIME_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_DIGCLKRETIMECTRL*/
+#define RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEENRETIME_disable (_RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEENRETIME_disable << 0) /**< Shifted mode disable for RAC_DIGCLKRETIMECTRL*/
+#define RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEENRETIME_enable (_RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEENRETIME_enable << 0) /**< Shifted mode enable for RAC_DIGCLKRETIMECTRL*/
+#define RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEDISRETIME (0x1UL << 1) /**< DIGCLKRETIMEDISRETIME */
+#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEDISRETIME_SHIFT 1 /**< Shift value for RAC_DIGCLKRETIMEDISRETIME */
+#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEDISRETIME_MASK 0x2UL /**< Bit mask for RAC_DIGCLKRETIMEDISRETIME */
+#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEDISRETIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_DIGCLKRETIMECTRL */
+#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEDISRETIME_enable_retime 0x00000000UL /**< Mode enable_retime for RAC_DIGCLKRETIMECTRL */
+#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEDISRETIME_disable_retime 0x00000001UL /**< Mode disable_retime for RAC_DIGCLKRETIMECTRL*/
+#define RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEDISRETIME_DEFAULT (_RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEDISRETIME_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_DIGCLKRETIMECTRL*/
+#define RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEDISRETIME_enable_retime (_RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEDISRETIME_enable_retime << 1) /**< Shifted mode enable_retime for RAC_DIGCLKRETIMECTRL*/
+#define RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEDISRETIME_disable_retime (_RAC_DIGCLKRETIMECTRL_DIGCLKRETIMEDISRETIME_disable_retime << 1) /**< Shifted mode disable_retime for RAC_DIGCLKRETIMECTRL*/
+#define RAC_DIGCLKRETIMECTRL_DIGCLKRETIMERESETN (0x1UL << 2) /**< DIGCLKRETIMERESETN */
+#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMERESETN_SHIFT 2 /**< Shift value for RAC_DIGCLKRETIMERESETN */
+#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMERESETN_MASK 0x4UL /**< Bit mask for RAC_DIGCLKRETIMERESETN */
+#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMERESETN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_DIGCLKRETIMECTRL */
+#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMERESETN_reset 0x00000000UL /**< Mode reset for RAC_DIGCLKRETIMECTRL */
+#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMERESETN_operate 0x00000001UL /**< Mode operate for RAC_DIGCLKRETIMECTRL */
+#define RAC_DIGCLKRETIMECTRL_DIGCLKRETIMERESETN_DEFAULT (_RAC_DIGCLKRETIMECTRL_DIGCLKRETIMERESETN_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_DIGCLKRETIMECTRL*/
+#define RAC_DIGCLKRETIMECTRL_DIGCLKRETIMERESETN_reset (_RAC_DIGCLKRETIMECTRL_DIGCLKRETIMERESETN_reset << 2) /**< Shifted mode reset for RAC_DIGCLKRETIMECTRL */
+#define RAC_DIGCLKRETIMECTRL_DIGCLKRETIMERESETN_operate (_RAC_DIGCLKRETIMECTRL_DIGCLKRETIMERESETN_operate << 2) /**< Shifted mode operate for RAC_DIGCLKRETIMECTRL*/
+#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMELIMITH_SHIFT 4 /**< Shift value for RAC_DIGCLKRETIMELIMITH */
+#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMELIMITH_MASK 0x70UL /**< Bit mask for RAC_DIGCLKRETIMELIMITH */
+#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMELIMITH_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_DIGCLKRETIMECTRL */
+#define RAC_DIGCLKRETIMECTRL_DIGCLKRETIMELIMITH_DEFAULT (_RAC_DIGCLKRETIMECTRL_DIGCLKRETIMELIMITH_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_DIGCLKRETIMECTRL*/
+#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMELIMITL_SHIFT 8 /**< Shift value for RAC_DIGCLKRETIMELIMITL */
+#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMELIMITL_MASK 0x700UL /**< Bit mask for RAC_DIGCLKRETIMELIMITL */
+#define _RAC_DIGCLKRETIMECTRL_DIGCLKRETIMELIMITL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_DIGCLKRETIMECTRL */
+#define RAC_DIGCLKRETIMECTRL_DIGCLKRETIMELIMITL_DEFAULT (_RAC_DIGCLKRETIMECTRL_DIGCLKRETIMELIMITL_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_DIGCLKRETIMECTRL*/
+
+/* Bit fields for RAC DIGCLKRETIMESTATUS */
+#define _RAC_DIGCLKRETIMESTATUS_RESETVALUE 0x00000000UL /**< Default value for RAC_DIGCLKRETIMESTATUS */
+#define _RAC_DIGCLKRETIMESTATUS_MASK 0x00000003UL /**< Mask for RAC_DIGCLKRETIMESTATUS */
+#define RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMECLKSEL (0x1UL << 0) /**< DIGCLKRETIMECLKSEL */
+#define _RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMECLKSEL_SHIFT 0 /**< Shift value for RAC_DIGCLKRETIMECLKSEL */
+#define _RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMECLKSEL_MASK 0x1UL /**< Bit mask for RAC_DIGCLKRETIMECLKSEL */
+#define _RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMECLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_DIGCLKRETIMESTATUS */
+#define _RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMECLKSEL_use_raw_clk 0x00000000UL /**< Mode use_raw_clk for RAC_DIGCLKRETIMESTATUS */
+#define _RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMECLKSEL_use_retimed_clk 0x00000001UL /**< Mode use_retimed_clk for RAC_DIGCLKRETIMESTATUS*/
+#define RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMECLKSEL_DEFAULT (_RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMECLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_DIGCLKRETIMESTATUS*/
+#define RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMECLKSEL_use_raw_clk (_RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMECLKSEL_use_raw_clk << 0) /**< Shifted mode use_raw_clk for RAC_DIGCLKRETIMESTATUS*/
+#define RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMECLKSEL_use_retimed_clk (_RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMECLKSEL_use_retimed_clk << 0) /**< Shifted mode use_retimed_clk for RAC_DIGCLKRETIMESTATUS*/
+#define RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMERESETNLO (0x1UL << 1) /**< DIGCLKRETIMERESETNLO */
+#define _RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMERESETNLO_SHIFT 1 /**< Shift value for RAC_DIGCLKRETIMERESETNLO */
+#define _RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMERESETNLO_MASK 0x2UL /**< Bit mask for RAC_DIGCLKRETIMERESETNLO */
+#define _RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMERESETNLO_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_DIGCLKRETIMESTATUS */
+#define _RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMERESETNLO_lo 0x00000000UL /**< Mode lo for RAC_DIGCLKRETIMESTATUS */
+#define _RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMERESETNLO_hi 0x00000001UL /**< Mode hi for RAC_DIGCLKRETIMESTATUS */
+#define RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMERESETNLO_DEFAULT (_RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMERESETNLO_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_DIGCLKRETIMESTATUS*/
+#define RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMERESETNLO_lo (_RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMERESETNLO_lo << 1) /**< Shifted mode lo for RAC_DIGCLKRETIMESTATUS */
+#define RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMERESETNLO_hi (_RAC_DIGCLKRETIMESTATUS_DIGCLKRETIMERESETNLO_hi << 1) /**< Shifted mode hi for RAC_DIGCLKRETIMESTATUS */
+
+/* Bit fields for RAC XORETIMECTRL */
+#define _RAC_XORETIMECTRL_RESETVALUE 0x00000000UL /**< Default value for RAC_XORETIMECTRL */
+#define _RAC_XORETIMECTRL_MASK 0x00000777UL /**< Mask for RAC_XORETIMECTRL */
+#define RAC_XORETIMECTRL_XORETIMEENRETIME (0x1UL << 0) /**< XORETIMEENRETIME */
+#define _RAC_XORETIMECTRL_XORETIMEENRETIME_SHIFT 0 /**< Shift value for RAC_XORETIMEENRETIME */
+#define _RAC_XORETIMECTRL_XORETIMEENRETIME_MASK 0x1UL /**< Bit mask for RAC_XORETIMEENRETIME */
+#define _RAC_XORETIMECTRL_XORETIMEENRETIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_XORETIMECTRL */
+#define _RAC_XORETIMECTRL_XORETIMEENRETIME_disable 0x00000000UL /**< Mode disable for RAC_XORETIMECTRL */
+#define _RAC_XORETIMECTRL_XORETIMEENRETIME_enable 0x00000001UL /**< Mode enable for RAC_XORETIMECTRL */
+#define RAC_XORETIMECTRL_XORETIMEENRETIME_DEFAULT (_RAC_XORETIMECTRL_XORETIMEENRETIME_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_XORETIMECTRL */
+#define RAC_XORETIMECTRL_XORETIMEENRETIME_disable (_RAC_XORETIMECTRL_XORETIMEENRETIME_disable << 0) /**< Shifted mode disable for RAC_XORETIMECTRL */
+#define RAC_XORETIMECTRL_XORETIMEENRETIME_enable (_RAC_XORETIMECTRL_XORETIMEENRETIME_enable << 0) /**< Shifted mode enable for RAC_XORETIMECTRL */
+#define RAC_XORETIMECTRL_XORETIMEDISRETIME (0x1UL << 1) /**< XORETIMEDISRETIME */
+#define _RAC_XORETIMECTRL_XORETIMEDISRETIME_SHIFT 1 /**< Shift value for RAC_XORETIMEDISRETIME */
+#define _RAC_XORETIMECTRL_XORETIMEDISRETIME_MASK 0x2UL /**< Bit mask for RAC_XORETIMEDISRETIME */
+#define _RAC_XORETIMECTRL_XORETIMEDISRETIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_XORETIMECTRL */
+#define _RAC_XORETIMECTRL_XORETIMEDISRETIME_enable_retime 0x00000000UL /**< Mode enable_retime for RAC_XORETIMECTRL */
+#define _RAC_XORETIMECTRL_XORETIMEDISRETIME_disable_retime 0x00000001UL /**< Mode disable_retime for RAC_XORETIMECTRL */
+#define RAC_XORETIMECTRL_XORETIMEDISRETIME_DEFAULT (_RAC_XORETIMECTRL_XORETIMEDISRETIME_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_XORETIMECTRL */
+#define RAC_XORETIMECTRL_XORETIMEDISRETIME_enable_retime (_RAC_XORETIMECTRL_XORETIMEDISRETIME_enable_retime << 1) /**< Shifted mode enable_retime for RAC_XORETIMECTRL*/
+#define RAC_XORETIMECTRL_XORETIMEDISRETIME_disable_retime (_RAC_XORETIMECTRL_XORETIMEDISRETIME_disable_retime << 1) /**< Shifted mode disable_retime for RAC_XORETIMECTRL*/
+#define RAC_XORETIMECTRL_XORETIMERESETN (0x1UL << 2) /**< XORETIMERESETN */
+#define _RAC_XORETIMECTRL_XORETIMERESETN_SHIFT 2 /**< Shift value for RAC_XORETIMERESETN */
+#define _RAC_XORETIMECTRL_XORETIMERESETN_MASK 0x4UL /**< Bit mask for RAC_XORETIMERESETN */
+#define _RAC_XORETIMECTRL_XORETIMERESETN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_XORETIMECTRL */
+#define _RAC_XORETIMECTRL_XORETIMERESETN_reset 0x00000000UL /**< Mode reset for RAC_XORETIMECTRL */
+#define _RAC_XORETIMECTRL_XORETIMERESETN_operate 0x00000001UL /**< Mode operate for RAC_XORETIMECTRL */
+#define RAC_XORETIMECTRL_XORETIMERESETN_DEFAULT (_RAC_XORETIMECTRL_XORETIMERESETN_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_XORETIMECTRL */
+#define RAC_XORETIMECTRL_XORETIMERESETN_reset (_RAC_XORETIMECTRL_XORETIMERESETN_reset << 2) /**< Shifted mode reset for RAC_XORETIMECTRL */
+#define RAC_XORETIMECTRL_XORETIMERESETN_operate (_RAC_XORETIMECTRL_XORETIMERESETN_operate << 2) /**< Shifted mode operate for RAC_XORETIMECTRL */
+#define _RAC_XORETIMECTRL_XORETIMELIMITH_SHIFT 4 /**< Shift value for RAC_XORETIMELIMITH */
+#define _RAC_XORETIMECTRL_XORETIMELIMITH_MASK 0x70UL /**< Bit mask for RAC_XORETIMELIMITH */
+#define _RAC_XORETIMECTRL_XORETIMELIMITH_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_XORETIMECTRL */
+#define RAC_XORETIMECTRL_XORETIMELIMITH_DEFAULT (_RAC_XORETIMECTRL_XORETIMELIMITH_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_XORETIMECTRL */
+#define _RAC_XORETIMECTRL_XORETIMELIMITL_SHIFT 8 /**< Shift value for RAC_XORETIMELIMITL */
+#define _RAC_XORETIMECTRL_XORETIMELIMITL_MASK 0x700UL /**< Bit mask for RAC_XORETIMELIMITL */
+#define _RAC_XORETIMECTRL_XORETIMELIMITL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_XORETIMECTRL */
+#define RAC_XORETIMECTRL_XORETIMELIMITL_DEFAULT (_RAC_XORETIMECTRL_XORETIMELIMITL_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_XORETIMECTRL */
+
+/* Bit fields for RAC XORETIMESTATUS */
+#define _RAC_XORETIMESTATUS_RESETVALUE 0x00000000UL /**< Default value for RAC_XORETIMESTATUS */
+#define _RAC_XORETIMESTATUS_MASK 0x00000003UL /**< Mask for RAC_XORETIMESTATUS */
+#define RAC_XORETIMESTATUS_XORETIMECLKSEL (0x1UL << 0) /**< XORETIMECLKSEL */
+#define _RAC_XORETIMESTATUS_XORETIMECLKSEL_SHIFT 0 /**< Shift value for RAC_XORETIMECLKSEL */
+#define _RAC_XORETIMESTATUS_XORETIMECLKSEL_MASK 0x1UL /**< Bit mask for RAC_XORETIMECLKSEL */
+#define _RAC_XORETIMESTATUS_XORETIMECLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_XORETIMESTATUS */
+#define _RAC_XORETIMESTATUS_XORETIMECLKSEL_use_raw_clk 0x00000000UL /**< Mode use_raw_clk for RAC_XORETIMESTATUS */
+#define _RAC_XORETIMESTATUS_XORETIMECLKSEL_use_retimed_clk 0x00000001UL /**< Mode use_retimed_clk for RAC_XORETIMESTATUS */
+#define RAC_XORETIMESTATUS_XORETIMECLKSEL_DEFAULT (_RAC_XORETIMESTATUS_XORETIMECLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_XORETIMESTATUS */
+#define RAC_XORETIMESTATUS_XORETIMECLKSEL_use_raw_clk (_RAC_XORETIMESTATUS_XORETIMECLKSEL_use_raw_clk << 0) /**< Shifted mode use_raw_clk for RAC_XORETIMESTATUS*/
+#define RAC_XORETIMESTATUS_XORETIMECLKSEL_use_retimed_clk (_RAC_XORETIMESTATUS_XORETIMECLKSEL_use_retimed_clk << 0) /**< Shifted mode use_retimed_clk for RAC_XORETIMESTATUS*/
+#define RAC_XORETIMESTATUS_XORETIMERESETNLO (0x1UL << 1) /**< XORETIMERESETNLO */
+#define _RAC_XORETIMESTATUS_XORETIMERESETNLO_SHIFT 1 /**< Shift value for RAC_XORETIMERESETNLO */
+#define _RAC_XORETIMESTATUS_XORETIMERESETNLO_MASK 0x2UL /**< Bit mask for RAC_XORETIMERESETNLO */
+#define _RAC_XORETIMESTATUS_XORETIMERESETNLO_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_XORETIMESTATUS */
+#define _RAC_XORETIMESTATUS_XORETIMERESETNLO_lo 0x00000000UL /**< Mode lo for RAC_XORETIMESTATUS */
+#define _RAC_XORETIMESTATUS_XORETIMERESETNLO_hi 0x00000001UL /**< Mode hi for RAC_XORETIMESTATUS */
+#define RAC_XORETIMESTATUS_XORETIMERESETNLO_DEFAULT (_RAC_XORETIMESTATUS_XORETIMERESETNLO_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_XORETIMESTATUS */
+#define RAC_XORETIMESTATUS_XORETIMERESETNLO_lo (_RAC_XORETIMESTATUS_XORETIMERESETNLO_lo << 1) /**< Shifted mode lo for RAC_XORETIMESTATUS */
+#define RAC_XORETIMESTATUS_XORETIMERESETNLO_hi (_RAC_XORETIMESTATUS_XORETIMERESETNLO_hi << 1) /**< Shifted mode hi for RAC_XORETIMESTATUS */
+
+/* Bit fields for RAC AGCOVERWRITE0 */
+#define _RAC_AGCOVERWRITE0_RESETVALUE 0x00000000UL /**< Default value for RAC_AGCOVERWRITE0 */
+#define _RAC_AGCOVERWRITE0_MASK 0x03F0FFFFUL /**< Mask for RAC_AGCOVERWRITE0 */
+#define RAC_AGCOVERWRITE0_ENMANLNAMIXRFATT (0x1UL << 0) /**< Enable RAC Overwite PN */
+#define _RAC_AGCOVERWRITE0_ENMANLNAMIXRFATT_SHIFT 0 /**< Shift value for RAC_ENMANLNAMIXRFATT */
+#define _RAC_AGCOVERWRITE0_ENMANLNAMIXRFATT_MASK 0x1UL /**< Bit mask for RAC_ENMANLNAMIXRFATT */
+#define _RAC_AGCOVERWRITE0_ENMANLNAMIXRFATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE0 */
+#define RAC_AGCOVERWRITE0_ENMANLNAMIXRFATT_DEFAULT (_RAC_AGCOVERWRITE0_ENMANLNAMIXRFATT_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE0 */
+#define RAC_AGCOVERWRITE0_ENMANLNAMIXSLICE (0x1UL << 1) /**< Enable RAC Overwite LNA */
+#define _RAC_AGCOVERWRITE0_ENMANLNAMIXSLICE_SHIFT 1 /**< Shift value for RAC_ENMANLNAMIXSLICE */
+#define _RAC_AGCOVERWRITE0_ENMANLNAMIXSLICE_MASK 0x2UL /**< Bit mask for RAC_ENMANLNAMIXSLICE */
+#define _RAC_AGCOVERWRITE0_ENMANLNAMIXSLICE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE0 */
+#define RAC_AGCOVERWRITE0_ENMANLNAMIXSLICE_DEFAULT (_RAC_AGCOVERWRITE0_ENMANLNAMIXSLICE_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE0 */
+#define RAC_AGCOVERWRITE0_ENMANPGAGAIN (0x1UL << 2) /**< Enable RAC Overwite PGA */
+#define _RAC_AGCOVERWRITE0_ENMANPGAGAIN_SHIFT 2 /**< Shift value for RAC_ENMANPGAGAIN */
+#define _RAC_AGCOVERWRITE0_ENMANPGAGAIN_MASK 0x4UL /**< Bit mask for RAC_ENMANPGAGAIN */
+#define _RAC_AGCOVERWRITE0_ENMANPGAGAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE0 */
+#define RAC_AGCOVERWRITE0_ENMANPGAGAIN_DEFAULT (_RAC_AGCOVERWRITE0_ENMANPGAGAIN_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE0 */
+#define RAC_AGCOVERWRITE0_ENMANIFADCSCALE (0x1UL << 3) /**< Enable RAC Overwite PN */
+#define _RAC_AGCOVERWRITE0_ENMANIFADCSCALE_SHIFT 3 /**< Shift value for RAC_ENMANIFADCSCALE */
+#define _RAC_AGCOVERWRITE0_ENMANIFADCSCALE_MASK 0x8UL /**< Bit mask for RAC_ENMANIFADCSCALE */
+#define _RAC_AGCOVERWRITE0_ENMANIFADCSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE0 */
+#define RAC_AGCOVERWRITE0_ENMANIFADCSCALE_DEFAULT (_RAC_AGCOVERWRITE0_ENMANIFADCSCALE_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE0 */
+#define _RAC_AGCOVERWRITE0_MANLNAMIXSLICE0_SHIFT 4 /**< Shift value for RAC_MANLNAMIXSLICE0 */
+#define _RAC_AGCOVERWRITE0_MANLNAMIXSLICE0_MASK 0x3F0UL /**< Bit mask for RAC_MANLNAMIXSLICE0 */
+#define _RAC_AGCOVERWRITE0_MANLNAMIXSLICE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE0 */
+#define RAC_AGCOVERWRITE0_MANLNAMIXSLICE0_DEFAULT (_RAC_AGCOVERWRITE0_MANLNAMIXSLICE0_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE0 */
+#define _RAC_AGCOVERWRITE0_MANLNAMIXSLICE1_SHIFT 10 /**< Shift value for RAC_MANLNAMIXSLICE1 */
+#define _RAC_AGCOVERWRITE0_MANLNAMIXSLICE1_MASK 0xFC00UL /**< Bit mask for RAC_MANLNAMIXSLICE1 */
+#define _RAC_AGCOVERWRITE0_MANLNAMIXSLICE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE0 */
+#define RAC_AGCOVERWRITE0_MANLNAMIXSLICE1_DEFAULT (_RAC_AGCOVERWRITE0_MANLNAMIXSLICE1_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE0 */
+#define _RAC_AGCOVERWRITE0_MANPGAGAIN_SHIFT 20 /**< Shift value for RAC_MANPGAGAIN */
+#define _RAC_AGCOVERWRITE0_MANPGAGAIN_MASK 0xF00000UL /**< Bit mask for RAC_MANPGAGAIN */
+#define _RAC_AGCOVERWRITE0_MANPGAGAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE0 */
+#define RAC_AGCOVERWRITE0_MANPGAGAIN_DEFAULT (_RAC_AGCOVERWRITE0_MANPGAGAIN_DEFAULT << 20) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE0 */
+#define _RAC_AGCOVERWRITE0_MANIFADCSCALE_SHIFT 24 /**< Shift value for RAC_MANIFADCSCALE */
+#define _RAC_AGCOVERWRITE0_MANIFADCSCALE_MASK 0x3000000UL /**< Bit mask for RAC_MANIFADCSCALE */
+#define _RAC_AGCOVERWRITE0_MANIFADCSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE0 */
+#define RAC_AGCOVERWRITE0_MANIFADCSCALE_DEFAULT (_RAC_AGCOVERWRITE0_MANIFADCSCALE_DEFAULT << 24) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE0 */
+
+/* Bit fields for RAC AGCOVERWRITE1 */
+#define _RAC_AGCOVERWRITE1_RESETVALUE 0x00000000UL /**< Default value for RAC_AGCOVERWRITE1 */
+#define _RAC_AGCOVERWRITE1_MASK 0x3FFF3FFFUL /**< Mask for RAC_AGCOVERWRITE1 */
+#define _RAC_AGCOVERWRITE1_MANLNAMIXRFATT0_SHIFT 0 /**< Shift value for RAC_MANLNAMIXRFATT0 */
+#define _RAC_AGCOVERWRITE1_MANLNAMIXRFATT0_MASK 0x3FFFUL /**< Bit mask for RAC_MANLNAMIXRFATT0 */
+#define _RAC_AGCOVERWRITE1_MANLNAMIXRFATT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE1 */
+#define RAC_AGCOVERWRITE1_MANLNAMIXRFATT0_DEFAULT (_RAC_AGCOVERWRITE1_MANLNAMIXRFATT0_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE1 */
+#define _RAC_AGCOVERWRITE1_MANLNAMIXRFATT1_SHIFT 16 /**< Shift value for RAC_MANLNAMIXRFATT1 */
+#define _RAC_AGCOVERWRITE1_MANLNAMIXRFATT1_MASK 0x3FFF0000UL /**< Bit mask for RAC_MANLNAMIXRFATT1 */
+#define _RAC_AGCOVERWRITE1_MANLNAMIXRFATT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE1 */
+#define RAC_AGCOVERWRITE1_MANLNAMIXRFATT1_DEFAULT (_RAC_AGCOVERWRITE1_MANLNAMIXRFATT1_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE1 */
+
+/* Bit fields for RAC AGCOVERWRITE2 */
+#define _RAC_AGCOVERWRITE2_RESETVALUE 0x00000000UL /**< Default value for RAC_AGCOVERWRITE2 */
+#define _RAC_AGCOVERWRITE2_MASK 0x0000FFFFUL /**< Mask for RAC_AGCOVERWRITE2 */
+#define RAC_AGCOVERWRITE2_ENMANFENOTCH (0x1UL << 0) /**< Enable RAC Overwrite FENOTCH */
+#define _RAC_AGCOVERWRITE2_ENMANFENOTCH_SHIFT 0 /**< Shift value for RAC_ENMANFENOTCH */
+#define _RAC_AGCOVERWRITE2_ENMANFENOTCH_MASK 0x1UL /**< Bit mask for RAC_ENMANFENOTCH */
+#define _RAC_AGCOVERWRITE2_ENMANFENOTCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE2 */
+#define RAC_AGCOVERWRITE2_ENMANFENOTCH_DEFAULT (_RAC_AGCOVERWRITE2_ENMANFENOTCH_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE2 */
+#define RAC_AGCOVERWRITE2_MANFENOTCHEN (0x1UL << 1) /**< RAC Overwrite fenotchen */
+#define _RAC_AGCOVERWRITE2_MANFENOTCHEN_SHIFT 1 /**< Shift value for RAC_MANFENOTCHEN */
+#define _RAC_AGCOVERWRITE2_MANFENOTCHEN_MASK 0x2UL /**< Bit mask for RAC_MANFENOTCHEN */
+#define _RAC_AGCOVERWRITE2_MANFENOTCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE2 */
+#define RAC_AGCOVERWRITE2_MANFENOTCHEN_DEFAULT (_RAC_AGCOVERWRITE2_MANFENOTCHEN_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE2 */
+#define _RAC_AGCOVERWRITE2_MANFENOTCHATTNSEL_SHIFT 2 /**< Shift value for RAC_MANFENOTCHATTNSEL */
+#define _RAC_AGCOVERWRITE2_MANFENOTCHATTNSEL_MASK 0x3CUL /**< Bit mask for RAC_MANFENOTCHATTNSEL */
+#define _RAC_AGCOVERWRITE2_MANFENOTCHATTNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE2 */
+#define RAC_AGCOVERWRITE2_MANFENOTCHATTNSEL_DEFAULT (_RAC_AGCOVERWRITE2_MANFENOTCHATTNSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE2 */
+#define RAC_AGCOVERWRITE2_MANFENOTCHRATTNENRF0 (0x1UL << 6) /**< RAC Overwrite fenotchrattnenrf0 */
+#define _RAC_AGCOVERWRITE2_MANFENOTCHRATTNENRF0_SHIFT 6 /**< Shift value for RAC_MANFENOTCHRATTNENRF0 */
+#define _RAC_AGCOVERWRITE2_MANFENOTCHRATTNENRF0_MASK 0x40UL /**< Bit mask for RAC_MANFENOTCHRATTNENRF0 */
+#define _RAC_AGCOVERWRITE2_MANFENOTCHRATTNENRF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE2 */
+#define RAC_AGCOVERWRITE2_MANFENOTCHRATTNENRF0_DEFAULT (_RAC_AGCOVERWRITE2_MANFENOTCHRATTNENRF0_DEFAULT << 6) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE2 */
+#define RAC_AGCOVERWRITE2_MANFENOTCHRATTNENRF1 (0x1UL << 7) /**< RAC Overwrite fenotchrattnenrf1 */
+#define _RAC_AGCOVERWRITE2_MANFENOTCHRATTNENRF1_SHIFT 7 /**< Shift value for RAC_MANFENOTCHRATTNENRF1 */
+#define _RAC_AGCOVERWRITE2_MANFENOTCHRATTNENRF1_MASK 0x80UL /**< Bit mask for RAC_MANFENOTCHRATTNENRF1 */
+#define _RAC_AGCOVERWRITE2_MANFENOTCHRATTNENRF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE2 */
+#define RAC_AGCOVERWRITE2_MANFENOTCHRATTNENRF1_DEFAULT (_RAC_AGCOVERWRITE2_MANFENOTCHRATTNENRF1_DEFAULT << 7) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE2 */
+#define _RAC_AGCOVERWRITE2_MANFENOTCHCAPCRSE_SHIFT 8 /**< Shift value for RAC_MANFENOTCHCAPCRSE */
+#define _RAC_AGCOVERWRITE2_MANFENOTCHCAPCRSE_MASK 0xF00UL /**< Bit mask for RAC_MANFENOTCHCAPCRSE */
+#define _RAC_AGCOVERWRITE2_MANFENOTCHCAPCRSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE2 */
+#define RAC_AGCOVERWRITE2_MANFENOTCHCAPCRSE_DEFAULT (_RAC_AGCOVERWRITE2_MANFENOTCHCAPCRSE_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE2 */
+#define _RAC_AGCOVERWRITE2_MANFENOTCHCAPFINE_SHIFT 12 /**< Shift value for RAC_MANFENOTCHCAPFINE */
+#define _RAC_AGCOVERWRITE2_MANFENOTCHCAPFINE_MASK 0xF000UL /**< Bit mask for RAC_MANFENOTCHCAPFINE */
+#define _RAC_AGCOVERWRITE2_MANFENOTCHCAPFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_AGCOVERWRITE2 */
+#define RAC_AGCOVERWRITE2_MANFENOTCHCAPFINE_DEFAULT (_RAC_AGCOVERWRITE2_MANFENOTCHCAPFINE_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_AGCOVERWRITE2 */
+
+/* Bit fields for RAC PACTRL */
+#define _RAC_PACTRL_RESETVALUE 0x00000000UL /**< Default value for RAC_PACTRL */
+#define _RAC_PACTRL_MASK 0x0001FFFFUL /**< Mask for RAC_PACTRL */
+#define RAC_PACTRL_TX0DBMLATCHBYPASS (0x1UL << 0) /**< TX0DBMLATCHBYPASS */
+#define _RAC_PACTRL_TX0DBMLATCHBYPASS_SHIFT 0 /**< Shift value for RAC_TX0DBMLATCHBYPASS */
+#define _RAC_PACTRL_TX0DBMLATCHBYPASS_MASK 0x1UL /**< Bit mask for RAC_TX0DBMLATCHBYPASS */
+#define _RAC_PACTRL_TX0DBMLATCHBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PACTRL */
+#define _RAC_PACTRL_TX0DBMLATCHBYPASS_disable 0x00000000UL /**< Mode disable for RAC_PACTRL */
+#define _RAC_PACTRL_TX0DBMLATCHBYPASS_enable 0x00000001UL /**< Mode enable for RAC_PACTRL */
+#define RAC_PACTRL_TX0DBMLATCHBYPASS_DEFAULT (_RAC_PACTRL_TX0DBMLATCHBYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_PACTRL */
+#define RAC_PACTRL_TX0DBMLATCHBYPASS_disable (_RAC_PACTRL_TX0DBMLATCHBYPASS_disable << 0) /**< Shifted mode disable for RAC_PACTRL */
+#define RAC_PACTRL_TX0DBMLATCHBYPASS_enable (_RAC_PACTRL_TX0DBMLATCHBYPASS_enable << 0) /**< Shifted mode enable for RAC_PACTRL */
+#define RAC_PACTRL_TX0DBMSLICERESET (0x1UL << 1) /**< TX0DBMSLICERESET */
+#define _RAC_PACTRL_TX0DBMSLICERESET_SHIFT 1 /**< Shift value for RAC_TX0DBMSLICERESET */
+#define _RAC_PACTRL_TX0DBMSLICERESET_MASK 0x2UL /**< Bit mask for RAC_TX0DBMSLICERESET */
+#define _RAC_PACTRL_TX0DBMSLICERESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PACTRL */
+#define _RAC_PACTRL_TX0DBMSLICERESET_active 0x00000000UL /**< Mode active for RAC_PACTRL */
+#define _RAC_PACTRL_TX0DBMSLICERESET_reset 0x00000001UL /**< Mode reset for RAC_PACTRL */
+#define RAC_PACTRL_TX0DBMSLICERESET_DEFAULT (_RAC_PACTRL_TX0DBMSLICERESET_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_PACTRL */
+#define RAC_PACTRL_TX0DBMSLICERESET_active (_RAC_PACTRL_TX0DBMSLICERESET_active << 1) /**< Shifted mode active for RAC_PACTRL */
+#define RAC_PACTRL_TX0DBMSLICERESET_reset (_RAC_PACTRL_TX0DBMSLICERESET_reset << 1) /**< Shifted mode reset for RAC_PACTRL */
+#define RAC_PACTRL_TXPABYPASSPREDRVREG (0x1UL << 2) /**< TXPABYPASSPREDRVREG */
+#define _RAC_PACTRL_TXPABYPASSPREDRVREG_SHIFT 2 /**< Shift value for RAC_TXPABYPASSPREDRVREG */
+#define _RAC_PACTRL_TXPABYPASSPREDRVREG_MASK 0x4UL /**< Bit mask for RAC_TXPABYPASSPREDRVREG */
+#define _RAC_PACTRL_TXPABYPASSPREDRVREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PACTRL */
+#define _RAC_PACTRL_TXPABYPASSPREDRVREG_not_bypass 0x00000000UL /**< Mode not_bypass for RAC_PACTRL */
+#define _RAC_PACTRL_TXPABYPASSPREDRVREG_bypass 0x00000001UL /**< Mode bypass for RAC_PACTRL */
+#define RAC_PACTRL_TXPABYPASSPREDRVREG_DEFAULT (_RAC_PACTRL_TXPABYPASSPREDRVREG_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_PACTRL */
+#define RAC_PACTRL_TXPABYPASSPREDRVREG_not_bypass (_RAC_PACTRL_TXPABYPASSPREDRVREG_not_bypass << 2) /**< Shifted mode not_bypass for RAC_PACTRL */
+#define RAC_PACTRL_TXPABYPASSPREDRVREG_bypass (_RAC_PACTRL_TXPABYPASSPREDRVREG_bypass << 2) /**< Shifted mode bypass for RAC_PACTRL */
+#define RAC_PACTRL_TXPAPULLDOWNVDDPA (0x1UL << 3) /**< TXPAPULLDOWNVDDPA */
+#define _RAC_PACTRL_TXPAPULLDOWNVDDPA_SHIFT 3 /**< Shift value for RAC_TXPAPULLDOWNVDDPA */
+#define _RAC_PACTRL_TXPAPULLDOWNVDDPA_MASK 0x8UL /**< Bit mask for RAC_TXPAPULLDOWNVDDPA */
+#define _RAC_PACTRL_TXPAPULLDOWNVDDPA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PACTRL */
+#define _RAC_PACTRL_TXPAPULLDOWNVDDPA_not_pull_down 0x00000000UL /**< Mode not_pull_down for RAC_PACTRL */
+#define _RAC_PACTRL_TXPAPULLDOWNVDDPA_pull_down_vddpa 0x00000001UL /**< Mode pull_down_vddpa for RAC_PACTRL */
+#define RAC_PACTRL_TXPAPULLDOWNVDDPA_DEFAULT (_RAC_PACTRL_TXPAPULLDOWNVDDPA_DEFAULT << 3) /**< Shifted mode DEFAULT for RAC_PACTRL */
+#define RAC_PACTRL_TXPAPULLDOWNVDDPA_not_pull_down (_RAC_PACTRL_TXPAPULLDOWNVDDPA_not_pull_down << 3) /**< Shifted mode not_pull_down for RAC_PACTRL */
+#define RAC_PACTRL_TXPAPULLDOWNVDDPA_pull_down_vddpa (_RAC_PACTRL_TXPAPULLDOWNVDDPA_pull_down_vddpa << 3) /**< Shifted mode pull_down_vddpa for RAC_PACTRL */
+#define _RAC_PACTRL_TXPAPOWER_SHIFT 4 /**< Shift value for RAC_TXPAPOWER */
+#define _RAC_PACTRL_TXPAPOWER_MASK 0xF0UL /**< Bit mask for RAC_TXPAPOWER */
+#define _RAC_PACTRL_TXPAPOWER_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PACTRL */
+#define _RAC_PACTRL_TXPAPOWER_t0stripeon 0x00000000UL /**< Mode t0stripeon for RAC_PACTRL */
+#define _RAC_PACTRL_TXPAPOWER_t1stripeon 0x00000001UL /**< Mode t1stripeon for RAC_PACTRL */
+#define _RAC_PACTRL_TXPAPOWER_t2stripeon 0x00000002UL /**< Mode t2stripeon for RAC_PACTRL */
+#define _RAC_PACTRL_TXPAPOWER_t3stripeon 0x00000003UL /**< Mode t3stripeon for RAC_PACTRL */
+#define _RAC_PACTRL_TXPAPOWER_t4stripeon 0x00000004UL /**< Mode t4stripeon for RAC_PACTRL */
+#define _RAC_PACTRL_TXPAPOWER_t5stripeon 0x00000005UL /**< Mode t5stripeon for RAC_PACTRL */
+#define _RAC_PACTRL_TXPAPOWER_t6stripeon 0x00000006UL /**< Mode t6stripeon for RAC_PACTRL */
+#define _RAC_PACTRL_TXPAPOWER_t7stripeon 0x00000007UL /**< Mode t7stripeon for RAC_PACTRL */
+#define _RAC_PACTRL_TXPAPOWER_t8stripeon 0x00000008UL /**< Mode t8stripeon for RAC_PACTRL */
+#define _RAC_PACTRL_TXPAPOWER_t9stripeon 0x00000009UL /**< Mode t9stripeon for RAC_PACTRL */
+#define _RAC_PACTRL_TXPAPOWER_t10stripeon 0x0000000AUL /**< Mode t10stripeon for RAC_PACTRL */
+#define _RAC_PACTRL_TXPAPOWER_t11stripeon 0x0000000BUL /**< Mode t11stripeon for RAC_PACTRL */
+#define _RAC_PACTRL_TXPAPOWER_t12stripeon 0x0000000CUL /**< Mode t12stripeon for RAC_PACTRL */
+#define _RAC_PACTRL_TXPAPOWER_t13stripeon 0x0000000DUL /**< Mode t13stripeon for RAC_PACTRL */
+#define _RAC_PACTRL_TXPAPOWER_t14stripeon 0x0000000EUL /**< Mode t14stripeon for RAC_PACTRL */
+#define _RAC_PACTRL_TXPAPOWER_t15stripeon 0x0000000FUL /**< Mode t15stripeon for RAC_PACTRL */
+#define RAC_PACTRL_TXPAPOWER_DEFAULT (_RAC_PACTRL_TXPAPOWER_DEFAULT << 4) /**< Shifted mode DEFAULT for RAC_PACTRL */
+#define RAC_PACTRL_TXPAPOWER_t0stripeon (_RAC_PACTRL_TXPAPOWER_t0stripeon << 4) /**< Shifted mode t0stripeon for RAC_PACTRL */
+#define RAC_PACTRL_TXPAPOWER_t1stripeon (_RAC_PACTRL_TXPAPOWER_t1stripeon << 4) /**< Shifted mode t1stripeon for RAC_PACTRL */
+#define RAC_PACTRL_TXPAPOWER_t2stripeon (_RAC_PACTRL_TXPAPOWER_t2stripeon << 4) /**< Shifted mode t2stripeon for RAC_PACTRL */
+#define RAC_PACTRL_TXPAPOWER_t3stripeon (_RAC_PACTRL_TXPAPOWER_t3stripeon << 4) /**< Shifted mode t3stripeon for RAC_PACTRL */
+#define RAC_PACTRL_TXPAPOWER_t4stripeon (_RAC_PACTRL_TXPAPOWER_t4stripeon << 4) /**< Shifted mode t4stripeon for RAC_PACTRL */
+#define RAC_PACTRL_TXPAPOWER_t5stripeon (_RAC_PACTRL_TXPAPOWER_t5stripeon << 4) /**< Shifted mode t5stripeon for RAC_PACTRL */
+#define RAC_PACTRL_TXPAPOWER_t6stripeon (_RAC_PACTRL_TXPAPOWER_t6stripeon << 4) /**< Shifted mode t6stripeon for RAC_PACTRL */
+#define RAC_PACTRL_TXPAPOWER_t7stripeon (_RAC_PACTRL_TXPAPOWER_t7stripeon << 4) /**< Shifted mode t7stripeon for RAC_PACTRL */
+#define RAC_PACTRL_TXPAPOWER_t8stripeon (_RAC_PACTRL_TXPAPOWER_t8stripeon << 4) /**< Shifted mode t8stripeon for RAC_PACTRL */
+#define RAC_PACTRL_TXPAPOWER_t9stripeon (_RAC_PACTRL_TXPAPOWER_t9stripeon << 4) /**< Shifted mode t9stripeon for RAC_PACTRL */
+#define RAC_PACTRL_TXPAPOWER_t10stripeon (_RAC_PACTRL_TXPAPOWER_t10stripeon << 4) /**< Shifted mode t10stripeon for RAC_PACTRL */
+#define RAC_PACTRL_TXPAPOWER_t11stripeon (_RAC_PACTRL_TXPAPOWER_t11stripeon << 4) /**< Shifted mode t11stripeon for RAC_PACTRL */
+#define RAC_PACTRL_TXPAPOWER_t12stripeon (_RAC_PACTRL_TXPAPOWER_t12stripeon << 4) /**< Shifted mode t12stripeon for RAC_PACTRL */
+#define RAC_PACTRL_TXPAPOWER_t13stripeon (_RAC_PACTRL_TXPAPOWER_t13stripeon << 4) /**< Shifted mode t13stripeon for RAC_PACTRL */
+#define RAC_PACTRL_TXPAPOWER_t14stripeon (_RAC_PACTRL_TXPAPOWER_t14stripeon << 4) /**< Shifted mode t14stripeon for RAC_PACTRL */
+#define RAC_PACTRL_TXPAPOWER_t15stripeon (_RAC_PACTRL_TXPAPOWER_t15stripeon << 4) /**< Shifted mode t15stripeon for RAC_PACTRL */
+#define RAC_PACTRL_TXPALATCHBYPASS10DBM (0x1UL << 8) /**< TXPALATCHBYPASS10DBM */
+#define _RAC_PACTRL_TXPALATCHBYPASS10DBM_SHIFT 8 /**< Shift value for RAC_TXPALATCHBYPASS10DBM */
+#define _RAC_PACTRL_TXPALATCHBYPASS10DBM_MASK 0x100UL /**< Bit mask for RAC_TXPALATCHBYPASS10DBM */
+#define _RAC_PACTRL_TXPALATCHBYPASS10DBM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PACTRL */
+#define _RAC_PACTRL_TXPALATCHBYPASS10DBM_disable 0x00000000UL /**< Mode disable for RAC_PACTRL */
+#define _RAC_PACTRL_TXPALATCHBYPASS10DBM_enable 0x00000001UL /**< Mode enable for RAC_PACTRL */
+#define RAC_PACTRL_TXPALATCHBYPASS10DBM_DEFAULT (_RAC_PACTRL_TXPALATCHBYPASS10DBM_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_PACTRL */
+#define RAC_PACTRL_TXPALATCHBYPASS10DBM_disable (_RAC_PACTRL_TXPALATCHBYPASS10DBM_disable << 8) /**< Shifted mode disable for RAC_PACTRL */
+#define RAC_PACTRL_TXPALATCHBYPASS10DBM_enable (_RAC_PACTRL_TXPALATCHBYPASS10DBM_enable << 8) /**< Shifted mode enable for RAC_PACTRL */
+#define RAC_PACTRL_TXPALATCHBYPASS20DBM (0x1UL << 9) /**< TXPALATCHBYPASS20DBM */
+#define _RAC_PACTRL_TXPALATCHBYPASS20DBM_SHIFT 9 /**< Shift value for RAC_TXPALATCHBYPASS20DBM */
+#define _RAC_PACTRL_TXPALATCHBYPASS20DBM_MASK 0x200UL /**< Bit mask for RAC_TXPALATCHBYPASS20DBM */
+#define _RAC_PACTRL_TXPALATCHBYPASS20DBM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PACTRL */
+#define _RAC_PACTRL_TXPALATCHBYPASS20DBM_disable 0x00000000UL /**< Mode disable for RAC_PACTRL */
+#define _RAC_PACTRL_TXPALATCHBYPASS20DBM_enable 0x00000001UL /**< Mode enable for RAC_PACTRL */
+#define RAC_PACTRL_TXPALATCHBYPASS20DBM_DEFAULT (_RAC_PACTRL_TXPALATCHBYPASS20DBM_DEFAULT << 9) /**< Shifted mode DEFAULT for RAC_PACTRL */
+#define RAC_PACTRL_TXPALATCHBYPASS20DBM_disable (_RAC_PACTRL_TXPALATCHBYPASS20DBM_disable << 9) /**< Shifted mode disable for RAC_PACTRL */
+#define RAC_PACTRL_TXPALATCHBYPASS20DBM_enable (_RAC_PACTRL_TXPALATCHBYPASS20DBM_enable << 9) /**< Shifted mode enable for RAC_PACTRL */
+#define RAC_PACTRL_TXPASELPREDRVREGVDDPA (0x1UL << 10) /**< TXPASELPREDRVREGVDDPA */
+#define _RAC_PACTRL_TXPASELPREDRVREGVDDPA_SHIFT 10 /**< Shift value for RAC_TXPASELPREDRVREGVDDPA */
+#define _RAC_PACTRL_TXPASELPREDRVREGVDDPA_MASK 0x400UL /**< Bit mask for RAC_TXPASELPREDRVREGVDDPA */
+#define _RAC_PACTRL_TXPASELPREDRVREGVDDPA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PACTRL */
+#define _RAC_PACTRL_TXPASELPREDRVREGVDDPA_not_selected 0x00000000UL /**< Mode not_selected for RAC_PACTRL */
+#define _RAC_PACTRL_TXPASELPREDRVREGVDDPA_selected 0x00000001UL /**< Mode selected for RAC_PACTRL */
+#define RAC_PACTRL_TXPASELPREDRVREGVDDPA_DEFAULT (_RAC_PACTRL_TXPASELPREDRVREGVDDPA_DEFAULT << 10) /**< Shifted mode DEFAULT for RAC_PACTRL */
+#define RAC_PACTRL_TXPASELPREDRVREGVDDPA_not_selected (_RAC_PACTRL_TXPASELPREDRVREGVDDPA_not_selected << 10) /**< Shifted mode not_selected for RAC_PACTRL */
+#define RAC_PACTRL_TXPASELPREDRVREGVDDPA_selected (_RAC_PACTRL_TXPASELPREDRVREGVDDPA_selected << 10) /**< Shifted mode selected for RAC_PACTRL */
+#define RAC_PACTRL_TXPASELPREDRVREGVDDRF (0x1UL << 11) /**< TXPASELPREDRVREGVDDRF */
+#define _RAC_PACTRL_TXPASELPREDRVREGVDDRF_SHIFT 11 /**< Shift value for RAC_TXPASELPREDRVREGVDDRF */
+#define _RAC_PACTRL_TXPASELPREDRVREGVDDRF_MASK 0x800UL /**< Bit mask for RAC_TXPASELPREDRVREGVDDRF */
+#define _RAC_PACTRL_TXPASELPREDRVREGVDDRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PACTRL */
+#define _RAC_PACTRL_TXPASELPREDRVREGVDDRF_not_selected 0x00000000UL /**< Mode not_selected for RAC_PACTRL */
+#define _RAC_PACTRL_TXPASELPREDRVREGVDDRF_selected 0x00000001UL /**< Mode selected for RAC_PACTRL */
+#define RAC_PACTRL_TXPASELPREDRVREGVDDRF_DEFAULT (_RAC_PACTRL_TXPASELPREDRVREGVDDRF_DEFAULT << 11) /**< Shifted mode DEFAULT for RAC_PACTRL */
+#define RAC_PACTRL_TXPASELPREDRVREGVDDRF_not_selected (_RAC_PACTRL_TXPASELPREDRVREGVDDRF_not_selected << 11) /**< Shifted mode not_selected for RAC_PACTRL */
+#define RAC_PACTRL_TXPASELPREDRVREGVDDRF_selected (_RAC_PACTRL_TXPASELPREDRVREGVDDRF_selected << 11) /**< Shifted mode selected for RAC_PACTRL */
+#define _RAC_PACTRL_TXPASELSLICE_SHIFT 12 /**< Shift value for RAC_TXPASELSLICE */
+#define _RAC_PACTRL_TXPASELSLICE_MASK 0xF000UL /**< Bit mask for RAC_TXPASELSLICE */
+#define _RAC_PACTRL_TXPASELSLICE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PACTRL */
+#define RAC_PACTRL_TXPASELSLICE_DEFAULT (_RAC_PACTRL_TXPASELSLICE_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_PACTRL */
+#define RAC_PACTRL_TXPASLICERST (0x1UL << 16) /**< TXPASLICERST */
+#define _RAC_PACTRL_TXPASLICERST_SHIFT 16 /**< Shift value for RAC_TXPASLICERST */
+#define _RAC_PACTRL_TXPASLICERST_MASK 0x10000UL /**< Bit mask for RAC_TXPASLICERST */
+#define _RAC_PACTRL_TXPASLICERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_PACTRL */
+#define _RAC_PACTRL_TXPASLICERST_disable 0x00000000UL /**< Mode disable for RAC_PACTRL */
+#define _RAC_PACTRL_TXPASLICERST_enable 0x00000001UL /**< Mode enable for RAC_PACTRL */
+#define RAC_PACTRL_TXPASLICERST_DEFAULT (_RAC_PACTRL_TXPASLICERST_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_PACTRL */
+#define RAC_PACTRL_TXPASLICERST_disable (_RAC_PACTRL_TXPASLICERST_disable << 16) /**< Shifted mode disable for RAC_PACTRL */
+#define RAC_PACTRL_TXPASLICERST_enable (_RAC_PACTRL_TXPASLICERST_enable << 16) /**< Shifted mode enable for RAC_PACTRL */
+
+/* Bit fields for RAC FENOTCH0 */
+#define _RAC_FENOTCH0_RESETVALUE 0x00004000UL /**< Default value for RAC_FENOTCH0 */
+#define _RAC_FENOTCH0_MASK 0x00007000UL /**< Mask for RAC_FENOTCH0 */
+#define _RAC_FENOTCH0_FENOTCHVBIAS_SHIFT 12 /**< Shift value for RAC_FENOTCHVBIAS */
+#define _RAC_FENOTCH0_FENOTCHVBIAS_MASK 0x7000UL /**< Bit mask for RAC_FENOTCHVBIAS */
+#define _RAC_FENOTCH0_FENOTCHVBIAS_DEFAULT 0x00000004UL /**< Mode DEFAULT for RAC_FENOTCH0 */
+#define RAC_FENOTCH0_FENOTCHVBIAS_DEFAULT (_RAC_FENOTCH0_FENOTCHVBIAS_DEFAULT << 12) /**< Shifted mode DEFAULT for RAC_FENOTCH0 */
+
+/* Bit fields for RAC FENOTCH1 */
+#define _RAC_FENOTCH1_RESETVALUE 0x00000000UL /**< Default value for RAC_FENOTCH1 */
+#define _RAC_FENOTCH1_MASK 0x001FFF05UL /**< Mask for RAC_FENOTCH1 */
+#define RAC_FENOTCH1_FENOTCHENVDDSW (0x1UL << 0) /**< FENOTCHENVDDSW */
+#define _RAC_FENOTCH1_FENOTCHENVDDSW_SHIFT 0 /**< Shift value for RAC_FENOTCHENVDDSW */
+#define _RAC_FENOTCH1_FENOTCHENVDDSW_MASK 0x1UL /**< Bit mask for RAC_FENOTCHENVDDSW */
+#define _RAC_FENOTCH1_FENOTCHENVDDSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_FENOTCH1 */
+#define _RAC_FENOTCH1_FENOTCHENVDDSW_disable 0x00000000UL /**< Mode disable for RAC_FENOTCH1 */
+#define _RAC_FENOTCH1_FENOTCHENVDDSW_enable 0x00000001UL /**< Mode enable for RAC_FENOTCH1 */
+#define RAC_FENOTCH1_FENOTCHENVDDSW_DEFAULT (_RAC_FENOTCH1_FENOTCHENVDDSW_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_FENOTCH1 */
+#define RAC_FENOTCH1_FENOTCHENVDDSW_disable (_RAC_FENOTCH1_FENOTCHENVDDSW_disable << 0) /**< Shifted mode disable for RAC_FENOTCH1 */
+#define RAC_FENOTCH1_FENOTCHENVDDSW_enable (_RAC_FENOTCH1_FENOTCHENVDDSW_enable << 0) /**< Shifted mode enable for RAC_FENOTCH1 */
+#define RAC_FENOTCH1_FENOTCHRCCALEN (0x1UL << 2) /**< FENOTCHRCCALEN */
+#define _RAC_FENOTCH1_FENOTCHRCCALEN_SHIFT 2 /**< Shift value for RAC_FENOTCHRCCALEN */
+#define _RAC_FENOTCH1_FENOTCHRCCALEN_MASK 0x4UL /**< Bit mask for RAC_FENOTCHRCCALEN */
+#define _RAC_FENOTCH1_FENOTCHRCCALEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_FENOTCH1 */
+#define _RAC_FENOTCH1_FENOTCHRCCALEN_disable 0x00000000UL /**< Mode disable for RAC_FENOTCH1 */
+#define _RAC_FENOTCH1_FENOTCHRCCALEN_enable 0x00000001UL /**< Mode enable for RAC_FENOTCH1 */
+#define RAC_FENOTCH1_FENOTCHRCCALEN_DEFAULT (_RAC_FENOTCH1_FENOTCHRCCALEN_DEFAULT << 2) /**< Shifted mode DEFAULT for RAC_FENOTCH1 */
+#define RAC_FENOTCH1_FENOTCHRCCALEN_disable (_RAC_FENOTCH1_FENOTCHRCCALEN_disable << 2) /**< Shifted mode disable for RAC_FENOTCH1 */
+#define RAC_FENOTCH1_FENOTCHRCCALEN_enable (_RAC_FENOTCH1_FENOTCHRCCALEN_enable << 2) /**< Shifted mode enable for RAC_FENOTCH1 */
+#define _RAC_FENOTCH1_FENOTCHRCCALCOUNTER_SHIFT 8 /**< Shift value for RAC_FENOTCHRCCALCOUNTER */
+#define _RAC_FENOTCH1_FENOTCHRCCALCOUNTER_MASK 0xFF00UL /**< Bit mask for RAC_FENOTCHRCCALCOUNTER */
+#define _RAC_FENOTCH1_FENOTCHRCCALCOUNTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_FENOTCH1 */
+#define RAC_FENOTCH1_FENOTCHRCCALCOUNTER_DEFAULT (_RAC_FENOTCH1_FENOTCHRCCALCOUNTER_DEFAULT << 8) /**< Shifted mode DEFAULT for RAC_FENOTCH1 */
+#define _RAC_FENOTCH1_FENOTCHRCCALOSC_SHIFT 16 /**< Shift value for RAC_FENOTCHRCCALOSC */
+#define _RAC_FENOTCH1_FENOTCHRCCALOSC_MASK 0xF0000UL /**< Bit mask for RAC_FENOTCHRCCALOSC */
+#define _RAC_FENOTCH1_FENOTCHRCCALOSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_FENOTCH1 */
+#define RAC_FENOTCH1_FENOTCHRCCALOSC_DEFAULT (_RAC_FENOTCH1_FENOTCHRCCALOSC_DEFAULT << 16) /**< Shifted mode DEFAULT for RAC_FENOTCH1 */
+#define RAC_FENOTCH1_FENOTCHRCCALOUT (0x1UL << 20) /**< FENOTCHRCCALOUT */
+#define _RAC_FENOTCH1_FENOTCHRCCALOUT_SHIFT 20 /**< Shift value for RAC_FENOTCHRCCALOUT */
+#define _RAC_FENOTCH1_FENOTCHRCCALOUT_MASK 0x100000UL /**< Bit mask for RAC_FENOTCHRCCALOUT */
+#define _RAC_FENOTCH1_FENOTCHRCCALOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_FENOTCH1 */
+#define RAC_FENOTCH1_FENOTCHRCCALOUT_DEFAULT (_RAC_FENOTCH1_FENOTCHRCCALOUT_DEFAULT << 20) /**< Shifted mode DEFAULT for RAC_FENOTCH1 */
+
+/* Bit fields for RAC SCRATCH0 */
+#define _RAC_SCRATCH0_RESETVALUE 0x00000000UL /**< Default value for RAC_SCRATCH0 */
+#define _RAC_SCRATCH0_MASK 0xFFFFFFFFUL /**< Mask for RAC_SCRATCH0 */
+#define _RAC_SCRATCH0_SCRATCH0_SHIFT 0 /**< Shift value for RAC_SCRATCH0 */
+#define _RAC_SCRATCH0_SCRATCH0_MASK 0xFFFFFFFFUL /**< Bit mask for RAC_SCRATCH0 */
+#define _RAC_SCRATCH0_SCRATCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SCRATCH0 */
+#define RAC_SCRATCH0_SCRATCH0_DEFAULT (_RAC_SCRATCH0_SCRATCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SCRATCH0 */
+
+/* Bit fields for RAC SCRATCH1 */
+#define _RAC_SCRATCH1_RESETVALUE 0x00000000UL /**< Default value for RAC_SCRATCH1 */
+#define _RAC_SCRATCH1_MASK 0xFFFFFFFFUL /**< Mask for RAC_SCRATCH1 */
+#define _RAC_SCRATCH1_SCRATCH1_SHIFT 0 /**< Shift value for RAC_SCRATCH1 */
+#define _RAC_SCRATCH1_SCRATCH1_MASK 0xFFFFFFFFUL /**< Bit mask for RAC_SCRATCH1 */
+#define _RAC_SCRATCH1_SCRATCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SCRATCH1 */
+#define RAC_SCRATCH1_SCRATCH1_DEFAULT (_RAC_SCRATCH1_SCRATCH1_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SCRATCH1 */
+
+/* Bit fields for RAC SCRATCH2 */
+#define _RAC_SCRATCH2_RESETVALUE 0x00000000UL /**< Default value for RAC_SCRATCH2 */
+#define _RAC_SCRATCH2_MASK 0xFFFFFFFFUL /**< Mask for RAC_SCRATCH2 */
+#define _RAC_SCRATCH2_SCRATCH2_SHIFT 0 /**< Shift value for RAC_SCRATCH2 */
+#define _RAC_SCRATCH2_SCRATCH2_MASK 0xFFFFFFFFUL /**< Bit mask for RAC_SCRATCH2 */
+#define _RAC_SCRATCH2_SCRATCH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SCRATCH2 */
+#define RAC_SCRATCH2_SCRATCH2_DEFAULT (_RAC_SCRATCH2_SCRATCH2_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SCRATCH2 */
+
+/* Bit fields for RAC SCRATCH3 */
+#define _RAC_SCRATCH3_RESETVALUE 0x00000000UL /**< Default value for RAC_SCRATCH3 */
+#define _RAC_SCRATCH3_MASK 0xFFFFFFFFUL /**< Mask for RAC_SCRATCH3 */
+#define _RAC_SCRATCH3_SCRATCH3_SHIFT 0 /**< Shift value for RAC_SCRATCH3 */
+#define _RAC_SCRATCH3_SCRATCH3_MASK 0xFFFFFFFFUL /**< Bit mask for RAC_SCRATCH3 */
+#define _RAC_SCRATCH3_SCRATCH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SCRATCH3 */
+#define RAC_SCRATCH3_SCRATCH3_DEFAULT (_RAC_SCRATCH3_SCRATCH3_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SCRATCH3 */
+
+/* Bit fields for RAC SCRATCH4 */
+#define _RAC_SCRATCH4_RESETVALUE 0x00000000UL /**< Default value for RAC_SCRATCH4 */
+#define _RAC_SCRATCH4_MASK 0xFFFFFFFFUL /**< Mask for RAC_SCRATCH4 */
+#define _RAC_SCRATCH4_SCRATCH4_SHIFT 0 /**< Shift value for RAC_SCRATCH4 */
+#define _RAC_SCRATCH4_SCRATCH4_MASK 0xFFFFFFFFUL /**< Bit mask for RAC_SCRATCH4 */
+#define _RAC_SCRATCH4_SCRATCH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SCRATCH4 */
+#define RAC_SCRATCH4_SCRATCH4_DEFAULT (_RAC_SCRATCH4_SCRATCH4_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SCRATCH4 */
+
+/* Bit fields for RAC SCRATCH5 */
+#define _RAC_SCRATCH5_RESETVALUE 0x00000000UL /**< Default value for RAC_SCRATCH5 */
+#define _RAC_SCRATCH5_MASK 0xFFFFFFFFUL /**< Mask for RAC_SCRATCH5 */
+#define _RAC_SCRATCH5_SCRATCH5_SHIFT 0 /**< Shift value for RAC_SCRATCH5 */
+#define _RAC_SCRATCH5_SCRATCH5_MASK 0xFFFFFFFFUL /**< Bit mask for RAC_SCRATCH5 */
+#define _RAC_SCRATCH5_SCRATCH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SCRATCH5 */
+#define RAC_SCRATCH5_SCRATCH5_DEFAULT (_RAC_SCRATCH5_SCRATCH5_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SCRATCH5 */
+
+/* Bit fields for RAC SCRATCH6 */
+#define _RAC_SCRATCH6_RESETVALUE 0x00000000UL /**< Default value for RAC_SCRATCH6 */
+#define _RAC_SCRATCH6_MASK 0xFFFFFFFFUL /**< Mask for RAC_SCRATCH6 */
+#define _RAC_SCRATCH6_SCRATCH6_SHIFT 0 /**< Shift value for RAC_SCRATCH6 */
+#define _RAC_SCRATCH6_SCRATCH6_MASK 0xFFFFFFFFUL /**< Bit mask for RAC_SCRATCH6 */
+#define _RAC_SCRATCH6_SCRATCH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SCRATCH6 */
+#define RAC_SCRATCH6_SCRATCH6_DEFAULT (_RAC_SCRATCH6_SCRATCH6_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SCRATCH6 */
+
+/* Bit fields for RAC SCRATCH7 */
+#define _RAC_SCRATCH7_RESETVALUE 0x00000000UL /**< Default value for RAC_SCRATCH7 */
+#define _RAC_SCRATCH7_MASK 0xFFFFFFFFUL /**< Mask for RAC_SCRATCH7 */
+#define _RAC_SCRATCH7_SCRATCH7_SHIFT 0 /**< Shift value for RAC_SCRATCH7 */
+#define _RAC_SCRATCH7_SCRATCH7_MASK 0xFFFFFFFFUL /**< Bit mask for RAC_SCRATCH7 */
+#define _RAC_SCRATCH7_SCRATCH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_SCRATCH7 */
+#define RAC_SCRATCH7_SCRATCH7_DEFAULT (_RAC_SCRATCH7_SCRATCH7_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_SCRATCH7 */
+
+/* Bit fields for RAC THMSW */
+#define _RAC_THMSW_RESETVALUE 0x00000000UL /**< Default value for RAC_THMSW */
+#define _RAC_THMSW_MASK 0x00000003UL /**< Mask for RAC_THMSW */
+#define RAC_THMSW_EN (0x1UL << 0) /**< Enable Switch */
+#define _RAC_THMSW_EN_SHIFT 0 /**< Shift value for RAC_EN */
+#define _RAC_THMSW_EN_MASK 0x1UL /**< Bit mask for RAC_EN */
+#define _RAC_THMSW_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_THMSW */
+#define _RAC_THMSW_EN_Disabled 0x00000000UL /**< Mode Disabled for RAC_THMSW */
+#define _RAC_THMSW_EN_Enabled 0x00000001UL /**< Mode Enabled for RAC_THMSW */
+#define RAC_THMSW_EN_DEFAULT (_RAC_THMSW_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for RAC_THMSW */
+#define RAC_THMSW_EN_Disabled (_RAC_THMSW_EN_Disabled << 0) /**< Shifted mode Disabled for RAC_THMSW */
+#define RAC_THMSW_EN_Enabled (_RAC_THMSW_EN_Enabled << 0) /**< Shifted mode Enabled for RAC_THMSW */
+#define RAC_THMSW_HALFSWITCH (0x1UL << 1) /**< Halfswitch Mode enable */
+#define _RAC_THMSW_HALFSWITCH_SHIFT 1 /**< Shift value for RAC_HALFSWITCH */
+#define _RAC_THMSW_HALFSWITCH_MASK 0x2UL /**< Bit mask for RAC_HALFSWITCH */
+#define _RAC_THMSW_HALFSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for RAC_THMSW */
+#define _RAC_THMSW_HALFSWITCH_Disabled 0x00000000UL /**< Mode Disabled for RAC_THMSW */
+#define _RAC_THMSW_HALFSWITCH_Enabled 0x00000001UL /**< Mode Enabled for RAC_THMSW */
+#define RAC_THMSW_HALFSWITCH_DEFAULT (_RAC_THMSW_HALFSWITCH_DEFAULT << 1) /**< Shifted mode DEFAULT for RAC_THMSW */
+#define RAC_THMSW_HALFSWITCH_Disabled (_RAC_THMSW_HALFSWITCH_Disabled << 1) /**< Shifted mode Disabled for RAC_THMSW */
+#define RAC_THMSW_HALFSWITCH_Enabled (_RAC_THMSW_HALFSWITCH_Enabled << 1) /**< Shifted mode Enabled for RAC_THMSW */
+
+/** @} End of group EFR32MG24_RAC_BitFields */
+/** @} End of group EFR32MG24_RAC */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_RAC_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_rfcrc.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_rfcrc.h
new file mode 100644
index 00000000..f207fc6b
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_rfcrc.h
@@ -0,0 +1,232 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 RFCRC register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_RFCRC_H
+#define EFR32MG24_RFCRC_H
+#define RFCRC_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_RFCRC RFCRC
+ * @{
+ * @brief EFR32MG24 RFCRC Register Declaration.
+ *****************************************************************************/
+
+/** RFCRC Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IP Version */
+ __IOM uint32_t EN; /**< Enable peripheral clock to this module */
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IOM uint32_t INPUTDATA; /**< Input Data Register */
+ __IOM uint32_t INIT; /**< CRC Initialization Value */
+ __IM uint32_t DATA; /**< CRC Data Register */
+ __IOM uint32_t POLY; /**< CRC Polynomial Value */
+ uint32_t RESERVED0[1015U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP Version */
+ __IOM uint32_t EN_SET; /**< Enable peripheral clock to this module */
+ __IOM uint32_t CTRL_SET; /**< Control Register */
+ __IM uint32_t STATUS_SET; /**< Status Register */
+ __IOM uint32_t CMD_SET; /**< Command Register */
+ __IOM uint32_t INPUTDATA_SET; /**< Input Data Register */
+ __IOM uint32_t INIT_SET; /**< CRC Initialization Value */
+ __IM uint32_t DATA_SET; /**< CRC Data Register */
+ __IOM uint32_t POLY_SET; /**< CRC Polynomial Value */
+ uint32_t RESERVED1[1015U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP Version */
+ __IOM uint32_t EN_CLR; /**< Enable peripheral clock to this module */
+ __IOM uint32_t CTRL_CLR; /**< Control Register */
+ __IM uint32_t STATUS_CLR; /**< Status Register */
+ __IOM uint32_t CMD_CLR; /**< Command Register */
+ __IOM uint32_t INPUTDATA_CLR; /**< Input Data Register */
+ __IOM uint32_t INIT_CLR; /**< CRC Initialization Value */
+ __IM uint32_t DATA_CLR; /**< CRC Data Register */
+ __IOM uint32_t POLY_CLR; /**< CRC Polynomial Value */
+ uint32_t RESERVED2[1015U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP Version */
+ __IOM uint32_t EN_TGL; /**< Enable peripheral clock to this module */
+ __IOM uint32_t CTRL_TGL; /**< Control Register */
+ __IM uint32_t STATUS_TGL; /**< Status Register */
+ __IOM uint32_t CMD_TGL; /**< Command Register */
+ __IOM uint32_t INPUTDATA_TGL; /**< Input Data Register */
+ __IOM uint32_t INIT_TGL; /**< CRC Initialization Value */
+ __IM uint32_t DATA_TGL; /**< CRC Data Register */
+ __IOM uint32_t POLY_TGL; /**< CRC Polynomial Value */
+} RFCRC_TypeDef;
+/** @} End of group EFR32MG24_RFCRC */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_RFCRC
+ * @{
+ * @defgroup EFR32MG24_RFCRC_BitFields RFCRC Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for RFCRC IPVERSION */
+#define _RFCRC_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for RFCRC_IPVERSION */
+#define _RFCRC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for RFCRC_IPVERSION */
+#define _RFCRC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for RFCRC_IPVERSION */
+#define _RFCRC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for RFCRC_IPVERSION */
+#define _RFCRC_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_IPVERSION */
+#define RFCRC_IPVERSION_IPVERSION_DEFAULT (_RFCRC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for RFCRC_IPVERSION */
+
+/* Bit fields for RFCRC EN */
+#define _RFCRC_EN_RESETVALUE 0x00000000UL /**< Default value for RFCRC_EN */
+#define _RFCRC_EN_MASK 0x00000001UL /**< Mask for RFCRC_EN */
+#define RFCRC_EN_EN (0x1UL << 0) /**< Enable peripheral clock to this module */
+#define _RFCRC_EN_EN_SHIFT 0 /**< Shift value for RFCRC_EN */
+#define _RFCRC_EN_EN_MASK 0x1UL /**< Bit mask for RFCRC_EN */
+#define _RFCRC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_EN */
+#define RFCRC_EN_EN_DEFAULT (_RFCRC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for RFCRC_EN */
+
+/* Bit fields for RFCRC CTRL */
+#define _RFCRC_CTRL_RESETVALUE 0x00000704UL /**< Default value for RFCRC_CTRL */
+#define _RFCRC_CTRL_MASK 0x00001FEFUL /**< Mask for RFCRC_CTRL */
+#define RFCRC_CTRL_INPUTINV (0x1UL << 0) /**< Input Invert */
+#define _RFCRC_CTRL_INPUTINV_SHIFT 0 /**< Shift value for RFCRC_INPUTINV */
+#define _RFCRC_CTRL_INPUTINV_MASK 0x1UL /**< Bit mask for RFCRC_INPUTINV */
+#define _RFCRC_CTRL_INPUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_CTRL */
+#define RFCRC_CTRL_INPUTINV_DEFAULT (_RFCRC_CTRL_INPUTINV_DEFAULT << 0) /**< Shifted mode DEFAULT for RFCRC_CTRL */
+#define RFCRC_CTRL_OUTPUTINV (0x1UL << 1) /**< Output Invert */
+#define _RFCRC_CTRL_OUTPUTINV_SHIFT 1 /**< Shift value for RFCRC_OUTPUTINV */
+#define _RFCRC_CTRL_OUTPUTINV_MASK 0x2UL /**< Bit mask for RFCRC_OUTPUTINV */
+#define _RFCRC_CTRL_OUTPUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_CTRL */
+#define RFCRC_CTRL_OUTPUTINV_DEFAULT (_RFCRC_CTRL_OUTPUTINV_DEFAULT << 1) /**< Shifted mode DEFAULT for RFCRC_CTRL */
+#define _RFCRC_CTRL_CRCWIDTH_SHIFT 2 /**< Shift value for RFCRC_CRCWIDTH */
+#define _RFCRC_CTRL_CRCWIDTH_MASK 0xCUL /**< Bit mask for RFCRC_CRCWIDTH */
+#define _RFCRC_CTRL_CRCWIDTH_DEFAULT 0x00000001UL /**< Mode DEFAULT for RFCRC_CTRL */
+#define _RFCRC_CTRL_CRCWIDTH_CRCWIDTH8 0x00000000UL /**< Mode CRCWIDTH8 for RFCRC_CTRL */
+#define _RFCRC_CTRL_CRCWIDTH_CRCWIDTH16 0x00000001UL /**< Mode CRCWIDTH16 for RFCRC_CTRL */
+#define _RFCRC_CTRL_CRCWIDTH_CRCWIDTH24 0x00000002UL /**< Mode CRCWIDTH24 for RFCRC_CTRL */
+#define _RFCRC_CTRL_CRCWIDTH_CRCWIDTH32 0x00000003UL /**< Mode CRCWIDTH32 for RFCRC_CTRL */
+#define RFCRC_CTRL_CRCWIDTH_DEFAULT (_RFCRC_CTRL_CRCWIDTH_DEFAULT << 2) /**< Shifted mode DEFAULT for RFCRC_CTRL */
+#define RFCRC_CTRL_CRCWIDTH_CRCWIDTH8 (_RFCRC_CTRL_CRCWIDTH_CRCWIDTH8 << 2) /**< Shifted mode CRCWIDTH8 for RFCRC_CTRL */
+#define RFCRC_CTRL_CRCWIDTH_CRCWIDTH16 (_RFCRC_CTRL_CRCWIDTH_CRCWIDTH16 << 2) /**< Shifted mode CRCWIDTH16 for RFCRC_CTRL */
+#define RFCRC_CTRL_CRCWIDTH_CRCWIDTH24 (_RFCRC_CTRL_CRCWIDTH_CRCWIDTH24 << 2) /**< Shifted mode CRCWIDTH24 for RFCRC_CTRL */
+#define RFCRC_CTRL_CRCWIDTH_CRCWIDTH32 (_RFCRC_CTRL_CRCWIDTH_CRCWIDTH32 << 2) /**< Shifted mode CRCWIDTH32 for RFCRC_CTRL */
+#define RFCRC_CTRL_INPUTBITORDER (0x1UL << 5) /**< CRC input bit ordering setting */
+#define _RFCRC_CTRL_INPUTBITORDER_SHIFT 5 /**< Shift value for RFCRC_INPUTBITORDER */
+#define _RFCRC_CTRL_INPUTBITORDER_MASK 0x20UL /**< Bit mask for RFCRC_INPUTBITORDER */
+#define _RFCRC_CTRL_INPUTBITORDER_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_CTRL */
+#define _RFCRC_CTRL_INPUTBITORDER_LSBFIRST 0x00000000UL /**< Mode LSBFIRST for RFCRC_CTRL */
+#define _RFCRC_CTRL_INPUTBITORDER_MSBFIRST 0x00000001UL /**< Mode MSBFIRST for RFCRC_CTRL */
+#define RFCRC_CTRL_INPUTBITORDER_DEFAULT (_RFCRC_CTRL_INPUTBITORDER_DEFAULT << 5) /**< Shifted mode DEFAULT for RFCRC_CTRL */
+#define RFCRC_CTRL_INPUTBITORDER_LSBFIRST (_RFCRC_CTRL_INPUTBITORDER_LSBFIRST << 5) /**< Shifted mode LSBFIRST for RFCRC_CTRL */
+#define RFCRC_CTRL_INPUTBITORDER_MSBFIRST (_RFCRC_CTRL_INPUTBITORDER_MSBFIRST << 5) /**< Shifted mode MSBFIRST for RFCRC_CTRL */
+#define RFCRC_CTRL_BYTEREVERSE (0x1UL << 6) /**< Reverse CRC byte ordering over air */
+#define _RFCRC_CTRL_BYTEREVERSE_SHIFT 6 /**< Shift value for RFCRC_BYTEREVERSE */
+#define _RFCRC_CTRL_BYTEREVERSE_MASK 0x40UL /**< Bit mask for RFCRC_BYTEREVERSE */
+#define _RFCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_CTRL */
+#define _RFCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for RFCRC_CTRL */
+#define _RFCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for RFCRC_CTRL */
+#define RFCRC_CTRL_BYTEREVERSE_DEFAULT (_RFCRC_CTRL_BYTEREVERSE_DEFAULT << 6) /**< Shifted mode DEFAULT for RFCRC_CTRL */
+#define RFCRC_CTRL_BYTEREVERSE_NORMAL (_RFCRC_CTRL_BYTEREVERSE_NORMAL << 6) /**< Shifted mode NORMAL for RFCRC_CTRL */
+#define RFCRC_CTRL_BYTEREVERSE_REVERSED (_RFCRC_CTRL_BYTEREVERSE_REVERSED << 6) /**< Shifted mode REVERSED for RFCRC_CTRL */
+#define RFCRC_CTRL_BITREVERSE (0x1UL << 7) /**< Reverse CRC bit ordering over air */
+#define _RFCRC_CTRL_BITREVERSE_SHIFT 7 /**< Shift value for RFCRC_BITREVERSE */
+#define _RFCRC_CTRL_BITREVERSE_MASK 0x80UL /**< Bit mask for RFCRC_BITREVERSE */
+#define _RFCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_CTRL */
+#define _RFCRC_CTRL_BITREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for RFCRC_CTRL */
+#define _RFCRC_CTRL_BITREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for RFCRC_CTRL */
+#define RFCRC_CTRL_BITREVERSE_DEFAULT (_RFCRC_CTRL_BITREVERSE_DEFAULT << 7) /**< Shifted mode DEFAULT for RFCRC_CTRL */
+#define RFCRC_CTRL_BITREVERSE_NORMAL (_RFCRC_CTRL_BITREVERSE_NORMAL << 7) /**< Shifted mode NORMAL for RFCRC_CTRL */
+#define RFCRC_CTRL_BITREVERSE_REVERSED (_RFCRC_CTRL_BITREVERSE_REVERSED << 7) /**< Shifted mode REVERSED for RFCRC_CTRL */
+#define _RFCRC_CTRL_BITSPERWORD_SHIFT 8 /**< Shift value for RFCRC_BITSPERWORD */
+#define _RFCRC_CTRL_BITSPERWORD_MASK 0xF00UL /**< Bit mask for RFCRC_BITSPERWORD */
+#define _RFCRC_CTRL_BITSPERWORD_DEFAULT 0x00000007UL /**< Mode DEFAULT for RFCRC_CTRL */
+#define RFCRC_CTRL_BITSPERWORD_DEFAULT (_RFCRC_CTRL_BITSPERWORD_DEFAULT << 8) /**< Shifted mode DEFAULT for RFCRC_CTRL */
+#define RFCRC_CTRL_PADCRCINPUT (0x1UL << 12) /**< Pad CRC input data */
+#define _RFCRC_CTRL_PADCRCINPUT_SHIFT 12 /**< Shift value for RFCRC_PADCRCINPUT */
+#define _RFCRC_CTRL_PADCRCINPUT_MASK 0x1000UL /**< Bit mask for RFCRC_PADCRCINPUT */
+#define _RFCRC_CTRL_PADCRCINPUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_CTRL */
+#define _RFCRC_CTRL_PADCRCINPUT_X0 0x00000000UL /**< Mode X0 for RFCRC_CTRL */
+#define _RFCRC_CTRL_PADCRCINPUT_X1 0x00000001UL /**< Mode X1 for RFCRC_CTRL */
+#define RFCRC_CTRL_PADCRCINPUT_DEFAULT (_RFCRC_CTRL_PADCRCINPUT_DEFAULT << 12) /**< Shifted mode DEFAULT for RFCRC_CTRL */
+#define RFCRC_CTRL_PADCRCINPUT_X0 (_RFCRC_CTRL_PADCRCINPUT_X0 << 12) /**< Shifted mode X0 for RFCRC_CTRL */
+#define RFCRC_CTRL_PADCRCINPUT_X1 (_RFCRC_CTRL_PADCRCINPUT_X1 << 12) /**< Shifted mode X1 for RFCRC_CTRL */
+
+/* Bit fields for RFCRC STATUS */
+#define _RFCRC_STATUS_RESETVALUE 0x00000000UL /**< Default value for RFCRC_STATUS */
+#define _RFCRC_STATUS_MASK 0x00000001UL /**< Mask for RFCRC_STATUS */
+#define RFCRC_STATUS_BUSY (0x1UL << 0) /**< CRC Running */
+#define _RFCRC_STATUS_BUSY_SHIFT 0 /**< Shift value for RFCRC_BUSY */
+#define _RFCRC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for RFCRC_BUSY */
+#define _RFCRC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_STATUS */
+#define RFCRC_STATUS_BUSY_DEFAULT (_RFCRC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for RFCRC_STATUS */
+
+/* Bit fields for RFCRC CMD */
+#define _RFCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for RFCRC_CMD */
+#define _RFCRC_CMD_MASK 0x00000001UL /**< Mask for RFCRC_CMD */
+#define RFCRC_CMD_INITIALIZE (0x1UL << 0) /**< Initialize CRC */
+#define _RFCRC_CMD_INITIALIZE_SHIFT 0 /**< Shift value for RFCRC_INITIALIZE */
+#define _RFCRC_CMD_INITIALIZE_MASK 0x1UL /**< Bit mask for RFCRC_INITIALIZE */
+#define _RFCRC_CMD_INITIALIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_CMD */
+#define RFCRC_CMD_INITIALIZE_DEFAULT (_RFCRC_CMD_INITIALIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for RFCRC_CMD */
+
+/* Bit fields for RFCRC INPUTDATA */
+#define _RFCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for RFCRC_INPUTDATA */
+#define _RFCRC_INPUTDATA_MASK 0x0000FFFFUL /**< Mask for RFCRC_INPUTDATA */
+#define _RFCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for RFCRC_INPUTDATA */
+#define _RFCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFUL /**< Bit mask for RFCRC_INPUTDATA */
+#define _RFCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_INPUTDATA */
+#define RFCRC_INPUTDATA_INPUTDATA_DEFAULT (_RFCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for RFCRC_INPUTDATA */
+
+/* Bit fields for RFCRC INIT */
+#define _RFCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for RFCRC_INIT */
+#define _RFCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for RFCRC_INIT */
+#define _RFCRC_INIT_INIT_SHIFT 0 /**< Shift value for RFCRC_INIT */
+#define _RFCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for RFCRC_INIT */
+#define _RFCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_INIT */
+#define RFCRC_INIT_INIT_DEFAULT (_RFCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for RFCRC_INIT */
+
+/* Bit fields for RFCRC DATA */
+#define _RFCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for RFCRC_DATA */
+#define _RFCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for RFCRC_DATA */
+#define _RFCRC_DATA_DATA_SHIFT 0 /**< Shift value for RFCRC_DATA */
+#define _RFCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for RFCRC_DATA */
+#define _RFCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_DATA */
+#define RFCRC_DATA_DATA_DEFAULT (_RFCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for RFCRC_DATA */
+
+/* Bit fields for RFCRC POLY */
+#define _RFCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for RFCRC_POLY */
+#define _RFCRC_POLY_MASK 0xFFFFFFFFUL /**< Mask for RFCRC_POLY */
+#define _RFCRC_POLY_POLY_SHIFT 0 /**< Shift value for RFCRC_POLY */
+#define _RFCRC_POLY_POLY_MASK 0xFFFFFFFFUL /**< Bit mask for RFCRC_POLY */
+#define _RFCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_POLY */
+#define RFCRC_POLY_POLY_DEFAULT (_RFCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for RFCRC_POLY */
+
+/** @} End of group EFR32MG24_RFCRC_BitFields */
+/** @} End of group EFR32MG24_RFCRC */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_RFCRC_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_scratchpad.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_scratchpad.h
new file mode 100644
index 00000000..d3008dcb
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_scratchpad.h
@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 SCRATCHPAD register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_SCRATCHPAD_H
+#define EFR32MG24_SCRATCHPAD_H
+#define SCRATCHPAD_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_SCRATCHPAD SCRATCHPAD
+ * @{
+ * @brief EFR32MG24 SCRATCHPAD Register Declaration.
+ *****************************************************************************/
+
+/** SCRATCHPAD Register Declaration. */
+typedef struct {
+ __IOM uint32_t SREG0; /**< Scratchpad Register 0 */
+ __IOM uint32_t SREG1; /**< Scratchpad Register 1 */
+ uint32_t RESERVED0[1022U]; /**< Reserved for future use */
+ __IOM uint32_t SREG0_SET; /**< Scratchpad Register 0 */
+ __IOM uint32_t SREG1_SET; /**< Scratchpad Register 1 */
+ uint32_t RESERVED1[1022U]; /**< Reserved for future use */
+ __IOM uint32_t SREG0_CLR; /**< Scratchpad Register 0 */
+ __IOM uint32_t SREG1_CLR; /**< Scratchpad Register 1 */
+ uint32_t RESERVED2[1022U]; /**< Reserved for future use */
+ __IOM uint32_t SREG0_TGL; /**< Scratchpad Register 0 */
+ __IOM uint32_t SREG1_TGL; /**< Scratchpad Register 1 */
+} SCRATCHPAD_TypeDef;
+/** @} End of group EFR32MG24_SCRATCHPAD */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_SCRATCHPAD
+ * @{
+ * @defgroup EFR32MG24_SCRATCHPAD_BitFields SCRATCHPAD Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for SCRATCHPAD SREG0 */
+#define _SCRATCHPAD_SREG0_RESETVALUE 0x00000000UL /**< Default value for SCRATCHPAD_SREG0 */
+#define _SCRATCHPAD_SREG0_MASK 0xFFFFFFFFUL /**< Mask for SCRATCHPAD_SREG0 */
+#define _SCRATCHPAD_SREG0_SCRATCH_SHIFT 0 /**< Shift value for SCRATCHPAD_SCRATCH */
+#define _SCRATCHPAD_SREG0_SCRATCH_MASK 0xFFFFFFFFUL /**< Bit mask for SCRATCHPAD_SCRATCH */
+#define _SCRATCHPAD_SREG0_SCRATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SCRATCHPAD_SREG0 */
+#define SCRATCHPAD_SREG0_SCRATCH_DEFAULT (_SCRATCHPAD_SREG0_SCRATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for SCRATCHPAD_SREG0 */
+
+/* Bit fields for SCRATCHPAD SREG1 */
+#define _SCRATCHPAD_SREG1_RESETVALUE 0x00000000UL /**< Default value for SCRATCHPAD_SREG1 */
+#define _SCRATCHPAD_SREG1_MASK 0xFFFFFFFFUL /**< Mask for SCRATCHPAD_SREG1 */
+#define _SCRATCHPAD_SREG1_SCRATCH_SHIFT 0 /**< Shift value for SCRATCHPAD_SCRATCH */
+#define _SCRATCHPAD_SREG1_SCRATCH_MASK 0xFFFFFFFFUL /**< Bit mask for SCRATCHPAD_SCRATCH */
+#define _SCRATCHPAD_SREG1_SCRATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SCRATCHPAD_SREG1 */
+#define SCRATCHPAD_SREG1_SCRATCH_DEFAULT (_SCRATCHPAD_SREG1_SCRATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for SCRATCHPAD_SREG1 */
+
+/** @} End of group EFR32MG24_SCRATCHPAD_BitFields */
+/** @} End of group EFR32MG24_SCRATCHPAD */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_SCRATCHPAD_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_semailbox.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_semailbox.h
new file mode 100644
index 00000000..cc82c6ad
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_semailbox.h
@@ -0,0 +1,383 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 SEMAILBOX register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_SEMAILBOX_H
+#define EFR32MG24_SEMAILBOX_H
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_SEMAILBOX_HOST SEMAILBOX_HOST
+ * @{
+ * @brief EFR32MG24 SEMAILBOX_HOST Register Declaration.
+ *****************************************************************************/
+
+/** SEMAILBOX_HOST Register Declaration. */
+typedef struct {
+ __IOM uint32_t FIFO; /**< ESECURE_MAILBOX_FIFO */
+ uint32_t RESERVED0[15U]; /**< Reserved for future use */
+ __IM uint32_t TX_STATUS; /**< ESECURE_MAILBOX_TXSTAT */
+ __IM uint32_t RX_STATUS; /**< ESECURE_MAILBOX_RXSTAT */
+ __IM uint32_t TX_PROT; /**< ESECURE_MAILBOX_TXPROTECT */
+ __IM uint32_t RX_PROT; /**< ESECURE_MAILBOX_RXPROTECT */
+ __IOM uint32_t TX_HEADER; /**< ESECURE_MAILBOX_TXHEADER */
+ __IM uint32_t RX_HEADER; /**< ESECURE_MAILBOX_RXHEADER */
+ __IOM uint32_t CONFIGURATION; /**< ESECURE_MAILBOX_CONFIG */
+} SEMAILBOX_HOST_TypeDef;
+/** @} End of group EFR32MG24_SEMAILBOX_HOST */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_SEMAILBOX_HOST
+ * @{
+ * @defgroup EFR32MG24_SEMAILBOX_HOST_BitFields SEMAILBOX_HOST Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for SEMAILBOX FIFO */
+#define _SEMAILBOX_FIFO_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_FIFO */
+#define _SEMAILBOX_FIFO_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_FIFO */
+#define _SEMAILBOX_FIFO_FIFO_SHIFT 0 /**< Shift value for SEMAILBOX_FIFO */
+#define _SEMAILBOX_FIFO_FIFO_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_FIFO */
+#define _SEMAILBOX_FIFO_FIFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_FIFO */
+#define SEMAILBOX_FIFO_FIFO_DEFAULT (_SEMAILBOX_FIFO_FIFO_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_FIFO */
+
+/* Bit fields for SEMAILBOX TX_STATUS */
+#define _SEMAILBOX_TX_STATUS_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_STATUS */
+#define _SEMAILBOX_TX_STATUS_MASK 0x00BFFFFFUL /**< Mask for SEMAILBOX_TX_STATUS */
+#define _SEMAILBOX_TX_STATUS_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */
+#define _SEMAILBOX_TX_STATUS_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */
+#define _SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */
+#define SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT (_SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/
+#define _SEMAILBOX_TX_STATUS_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */
+#define _SEMAILBOX_TX_STATUS_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */
+#define _SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */
+#define SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT (_SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/
+#define SEMAILBOX_TX_STATUS_TXINT (0x1UL << 20) /**< TXINT */
+#define _SEMAILBOX_TX_STATUS_TXINT_SHIFT 20 /**< Shift value for SEMAILBOX_TXINT */
+#define _SEMAILBOX_TX_STATUS_TXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_TXINT */
+#define _SEMAILBOX_TX_STATUS_TXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */
+#define SEMAILBOX_TX_STATUS_TXINT_DEFAULT (_SEMAILBOX_TX_STATUS_TXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/
+#define SEMAILBOX_TX_STATUS_TXFULL (0x1UL << 21) /**< TXFULL */
+#define _SEMAILBOX_TX_STATUS_TXFULL_SHIFT 21 /**< Shift value for SEMAILBOX_TXFULL */
+#define _SEMAILBOX_TX_STATUS_TXFULL_MASK 0x200000UL /**< Bit mask for SEMAILBOX_TXFULL */
+#define _SEMAILBOX_TX_STATUS_TXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */
+#define SEMAILBOX_TX_STATUS_TXFULL_DEFAULT (_SEMAILBOX_TX_STATUS_TXFULL_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/
+#define SEMAILBOX_TX_STATUS_TXERROR (0x1UL << 23) /**< TXERROR */
+#define _SEMAILBOX_TX_STATUS_TXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_TXERROR */
+#define _SEMAILBOX_TX_STATUS_TXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_TXERROR */
+#define _SEMAILBOX_TX_STATUS_TXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */
+#define SEMAILBOX_TX_STATUS_TXERROR_DEFAULT (_SEMAILBOX_TX_STATUS_TXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/
+
+/* Bit fields for SEMAILBOX RX_STATUS */
+#define _SEMAILBOX_RX_STATUS_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_STATUS */
+#define _SEMAILBOX_RX_STATUS_MASK 0x00FFFFFFUL /**< Mask for SEMAILBOX_RX_STATUS */
+#define _SEMAILBOX_RX_STATUS_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */
+#define _SEMAILBOX_RX_STATUS_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */
+#define _SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */
+#define SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT (_SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/
+#define _SEMAILBOX_RX_STATUS_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */
+#define _SEMAILBOX_RX_STATUS_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */
+#define _SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */
+#define SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT (_SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/
+#define SEMAILBOX_RX_STATUS_RXINT (0x1UL << 20) /**< RXINT */
+#define _SEMAILBOX_RX_STATUS_RXINT_SHIFT 20 /**< Shift value for SEMAILBOX_RXINT */
+#define _SEMAILBOX_RX_STATUS_RXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_RXINT */
+#define _SEMAILBOX_RX_STATUS_RXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */
+#define SEMAILBOX_RX_STATUS_RXINT_DEFAULT (_SEMAILBOX_RX_STATUS_RXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/
+#define SEMAILBOX_RX_STATUS_RXEMPTY (0x1UL << 21) /**< RXEMPTY */
+#define _SEMAILBOX_RX_STATUS_RXEMPTY_SHIFT 21 /**< Shift value for SEMAILBOX_RXEMPTY */
+#define _SEMAILBOX_RX_STATUS_RXEMPTY_MASK 0x200000UL /**< Bit mask for SEMAILBOX_RXEMPTY */
+#define _SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */
+#define SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT (_SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/
+#define SEMAILBOX_RX_STATUS_RXHDR (0x1UL << 22) /**< RXHDR */
+#define _SEMAILBOX_RX_STATUS_RXHDR_SHIFT 22 /**< Shift value for SEMAILBOX_RXHDR */
+#define _SEMAILBOX_RX_STATUS_RXHDR_MASK 0x400000UL /**< Bit mask for SEMAILBOX_RXHDR */
+#define _SEMAILBOX_RX_STATUS_RXHDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */
+#define SEMAILBOX_RX_STATUS_RXHDR_DEFAULT (_SEMAILBOX_RX_STATUS_RXHDR_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/
+#define SEMAILBOX_RX_STATUS_RXERROR (0x1UL << 23) /**< RXERROR */
+#define _SEMAILBOX_RX_STATUS_RXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_RXERROR */
+#define _SEMAILBOX_RX_STATUS_RXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_RXERROR */
+#define _SEMAILBOX_RX_STATUS_RXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */
+#define SEMAILBOX_RX_STATUS_RXERROR_DEFAULT (_SEMAILBOX_RX_STATUS_RXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/
+
+/* Bit fields for SEMAILBOX TX_PROT */
+#define _SEMAILBOX_TX_PROT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_PROT */
+#define _SEMAILBOX_TX_PROT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_TX_PROT */
+#define SEMAILBOX_TX_PROT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */
+#define _SEMAILBOX_TX_PROT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */
+#define _SEMAILBOX_TX_PROT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */
+#define _SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */
+#define SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT (_SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */
+#define SEMAILBOX_TX_PROT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */
+#define _SEMAILBOX_TX_PROT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */
+#define _SEMAILBOX_TX_PROT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */
+#define _SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */
+#define SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT (_SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */
+#define SEMAILBOX_TX_PROT_NONSECURE (0x1UL << 23) /**< NONSECURE */
+#define _SEMAILBOX_TX_PROT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */
+#define _SEMAILBOX_TX_PROT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */
+#define _SEMAILBOX_TX_PROT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */
+#define SEMAILBOX_TX_PROT_NONSECURE_DEFAULT (_SEMAILBOX_TX_PROT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */
+#define _SEMAILBOX_TX_PROT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */
+#define _SEMAILBOX_TX_PROT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */
+#define _SEMAILBOX_TX_PROT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */
+#define SEMAILBOX_TX_PROT_USER_DEFAULT (_SEMAILBOX_TX_PROT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */
+
+/* Bit fields for SEMAILBOX RX_PROT */
+#define _SEMAILBOX_RX_PROT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_PROT */
+#define _SEMAILBOX_RX_PROT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_RX_PROT */
+#define SEMAILBOX_RX_PROT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */
+#define _SEMAILBOX_RX_PROT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */
+#define _SEMAILBOX_RX_PROT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */
+#define _SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */
+#define SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT (_SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */
+#define SEMAILBOX_RX_PROT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */
+#define _SEMAILBOX_RX_PROT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */
+#define _SEMAILBOX_RX_PROT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */
+#define _SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */
+#define SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT (_SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */
+#define SEMAILBOX_RX_PROT_NONSECURE (0x1UL << 23) /**< NONSECURE */
+#define _SEMAILBOX_RX_PROT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */
+#define _SEMAILBOX_RX_PROT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */
+#define _SEMAILBOX_RX_PROT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */
+#define SEMAILBOX_RX_PROT_NONSECURE_DEFAULT (_SEMAILBOX_RX_PROT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */
+#define _SEMAILBOX_RX_PROT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */
+#define _SEMAILBOX_RX_PROT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */
+#define _SEMAILBOX_RX_PROT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */
+#define SEMAILBOX_RX_PROT_USER_DEFAULT (_SEMAILBOX_RX_PROT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */
+
+/* Bit fields for SEMAILBOX TX_HEADER */
+#define _SEMAILBOX_TX_HEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_HEADER */
+#define _SEMAILBOX_TX_HEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_TX_HEADER */
+#define _SEMAILBOX_TX_HEADER_TXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_TXHEADER */
+#define _SEMAILBOX_TX_HEADER_TXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_TXHEADER */
+#define _SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_HEADER */
+#define SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT (_SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_TX_HEADER*/
+
+/* Bit fields for SEMAILBOX RX_HEADER */
+#define _SEMAILBOX_RX_HEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_HEADER */
+#define _SEMAILBOX_RX_HEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_RX_HEADER */
+#define _SEMAILBOX_RX_HEADER_RXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_RXHEADER */
+#define _SEMAILBOX_RX_HEADER_RXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_RXHEADER */
+#define _SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_HEADER */
+#define SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT (_SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_RX_HEADER*/
+
+/* Bit fields for SEMAILBOX CONFIGURATION */
+#define _SEMAILBOX_CONFIGURATION_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_CONFIGURATION */
+#define _SEMAILBOX_CONFIGURATION_MASK 0x00000003UL /**< Mask for SEMAILBOX_CONFIGURATION */
+#define SEMAILBOX_CONFIGURATION_TXINTEN (0x1UL << 0) /**< TXINTEN */
+#define _SEMAILBOX_CONFIGURATION_TXINTEN_SHIFT 0 /**< Shift value for SEMAILBOX_TXINTEN */
+#define _SEMAILBOX_CONFIGURATION_TXINTEN_MASK 0x1UL /**< Bit mask for SEMAILBOX_TXINTEN */
+#define _SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_CONFIGURATION */
+#define SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT (_SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_CONFIGURATION*/
+#define SEMAILBOX_CONFIGURATION_RXINTEN (0x1UL << 1) /**< RXINTEN */
+#define _SEMAILBOX_CONFIGURATION_RXINTEN_SHIFT 1 /**< Shift value for SEMAILBOX_RXINTEN */
+#define _SEMAILBOX_CONFIGURATION_RXINTEN_MASK 0x2UL /**< Bit mask for SEMAILBOX_RXINTEN */
+#define _SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_CONFIGURATION */
+#define SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT (_SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SEMAILBOX_CONFIGURATION*/
+
+/** @} End of group EFR32MG24_SEMAILBOX_HOST_BitFields */
+/** @} End of group EFR32MG24_SEMAILBOX_HOST */
+/**************************************************************************//**
+ * @defgroup EFR32MG24_SEMAILBOX_APBSE SEMAILBOX_APBSE
+ * @{
+ * @brief EFR32MG24 SEMAILBOX_APBSE Register Declaration.
+ *****************************************************************************/
+
+/** SEMAILBOX_APBSE Register Declaration. */
+typedef struct {
+ __IOM uint32_t SE_ESECURE_MAILBOX_FIFO; /**< ESECURE_MAILBOX_FIFO */
+ uint32_t RESERVED0[15U]; /**< Reserved for future use */
+ __IM uint32_t SE_ESECURE_MAILBOX_TXSTAT; /**< ESECURE_MAILBOX_TXSTAT */
+ __IM uint32_t SE_ESECURE_MAILBOX_RXSTAT; /**< ESECURE_MAILBOX_RXSTAT */
+ __IM uint32_t SE_ESECURE_MAILBOX_TXPROTECT; /**< ESECURE_MAILBOX_TXPROTECT */
+ __IM uint32_t SE_ESECURE_MAILBOX_RXPROTECT; /**< ESECURE_MAILBOX_RXPROTECT */
+ __IOM uint32_t SE_ESECURE_MAILBOX_TXHEADER; /**< ESECURE_MAILBOX_TXHEADER */
+ __IM uint32_t SE_ESECURE_MAILBOX_RXHEADER; /**< ESECURE_MAILBOX_RXHEADER */
+ __IOM uint32_t SE_ESECURE_MAILBOX_CONFIG; /**< ESECURE_MAILBOX_CONFIG */
+} SEMAILBOX_APBSE_TypeDef;
+/** @} End of group EFR32MG24_SEMAILBOX_APBSE */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_SEMAILBOX_APBSE
+ * @{
+ * @defgroup EFR32MG24_SEMAILBOX_APBSE_BitFields SEMAILBOX_APBSE Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_FIFO */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_SHIFT 0 /**< Shift value for SEMAILBOX_FIFO */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_FIFO */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/
+
+/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXSTAT */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MASK 0x00BFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT (0x1UL << 20) /**< TXINT */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_SHIFT 20 /**< Shift value for SEMAILBOX_TXINT */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_TXINT */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL (0x1UL << 21) /**< TXFULL */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_SHIFT 21 /**< Shift value for SEMAILBOX_TXFULL */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_MASK 0x200000UL /**< Bit mask for SEMAILBOX_TXFULL */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR (0x1UL << 23) /**< TXERROR */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_TXERROR */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_TXERROR */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/
+
+/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXSTAT */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MASK 0x00FFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT (0x1UL << 20) /**< RXINT */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_SHIFT 20 /**< Shift value for SEMAILBOX_RXINT */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_RXINT */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY (0x1UL << 21) /**< RXEMPTY */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_SHIFT 21 /**< Shift value for SEMAILBOX_RXEMPTY */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_MASK 0x200000UL /**< Bit mask for SEMAILBOX_RXEMPTY */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR (0x1UL << 22) /**< RXHDR */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_SHIFT 22 /**< Shift value for SEMAILBOX_RXHDR */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_MASK 0x400000UL /**< Bit mask for SEMAILBOX_RXHDR */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR (0x1UL << 23) /**< RXERROR */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_RXERROR */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_RXERROR */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/
+
+/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXPROTECT */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE (0x1UL << 23) /**< NONSECURE */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/
+
+/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXPROTECT */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE (0x1UL << 23) /**< NONSECURE */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/
+
+/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXHEADER */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_TXHEADER */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_TXHEADER */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/
+
+/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXHEADER */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_RXHEADER */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_RXHEADER */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/
+
+/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_CONFIG */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_MASK 0x00000003UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN (0x1UL << 0) /**< TXINTEN */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_SHIFT 0 /**< Shift value for SEMAILBOX_TXINTEN */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_MASK 0x1UL /**< Bit mask for SEMAILBOX_TXINTEN */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN (0x1UL << 1) /**< RXINTEN */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_SHIFT 1 /**< Shift value for SEMAILBOX_RXINTEN */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_MASK 0x2UL /**< Bit mask for SEMAILBOX_RXINTEN */
+#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/
+#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/
+
+/** @} End of group EFR32MG24_SEMAILBOX_APBSE_BitFields */
+/** @} End of group EFR32MG24_SEMAILBOX_APBSE */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_SEMAILBOX_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_smu.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_smu.h
new file mode 100644
index 00000000..b4160993
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_smu.h
@@ -0,0 +1,1483 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 SMU register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_SMU_H
+#define EFR32MG24_SMU_H
+#define SMU_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_SMU SMU
+ * @{
+ * @brief EFR32MG24 SMU Register Declaration.
+ *****************************************************************************/
+
+/** SMU Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IP Version */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IOM uint32_t LOCK; /**< Lock Register */
+ __IOM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ uint32_t RESERVED0[3U]; /**< Reserved for future use */
+ __IOM uint32_t M33CTRL; /**< M33 Control Settings */
+ uint32_t RESERVED1[7U]; /**< Reserved for future use */
+ __IOM uint32_t PPUPATD0; /**< Privileged Access */
+ __IOM uint32_t PPUPATD1; /**< Privileged Access */
+ uint32_t RESERVED2[6U]; /**< Reserved for future use */
+ __IOM uint32_t PPUSATD0; /**< Secure Access */
+ __IOM uint32_t PPUSATD1; /**< Secure Access */
+ uint32_t RESERVED3[54U]; /**< Reserved for future use */
+ __IM uint32_t PPUFS; /**< Fault Status */
+ uint32_t RESERVED4[3U]; /**< Reserved for future use */
+ __IOM uint32_t BMPUPATD0; /**< Privileged Attribute */
+ uint32_t RESERVED5[7U]; /**< Reserved for future use */
+ __IOM uint32_t BMPUSATD0; /**< Secure Attribute */
+ uint32_t RESERVED6[55U]; /**< Reserved for future use */
+ __IM uint32_t BMPUFS; /**< Fault Status */
+ __IM uint32_t BMPUFSADDR; /**< Fault Status Address */
+ uint32_t RESERVED7[2U]; /**< Reserved for future use */
+ __IOM uint32_t ESAURTYPES0; /**< Region Types 0 */
+ __IOM uint32_t ESAURTYPES1; /**< Region Types 1 */
+ uint32_t RESERVED8[2U]; /**< Reserved for future use */
+ __IOM uint32_t ESAUMRB01; /**< Movable Region Boundary */
+ __IOM uint32_t ESAUMRB12; /**< Movable Region Boundary */
+ uint32_t RESERVED9[2U]; /**< Reserved for future use */
+ __IOM uint32_t ESAUMRB45; /**< Movable Region Boundary */
+ __IOM uint32_t ESAUMRB56; /**< Movable Region Boundary */
+ uint32_t RESERVED10[862U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP Version */
+ __IM uint32_t STATUS_SET; /**< Status Register */
+ __IOM uint32_t LOCK_SET; /**< Lock Register */
+ __IOM uint32_t IF_SET; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
+ uint32_t RESERVED11[3U]; /**< Reserved for future use */
+ __IOM uint32_t M33CTRL_SET; /**< M33 Control Settings */
+ uint32_t RESERVED12[7U]; /**< Reserved for future use */
+ __IOM uint32_t PPUPATD0_SET; /**< Privileged Access */
+ __IOM uint32_t PPUPATD1_SET; /**< Privileged Access */
+ uint32_t RESERVED13[6U]; /**< Reserved for future use */
+ __IOM uint32_t PPUSATD0_SET; /**< Secure Access */
+ __IOM uint32_t PPUSATD1_SET; /**< Secure Access */
+ uint32_t RESERVED14[54U]; /**< Reserved for future use */
+ __IM uint32_t PPUFS_SET; /**< Fault Status */
+ uint32_t RESERVED15[3U]; /**< Reserved for future use */
+ __IOM uint32_t BMPUPATD0_SET; /**< Privileged Attribute */
+ uint32_t RESERVED16[7U]; /**< Reserved for future use */
+ __IOM uint32_t BMPUSATD0_SET; /**< Secure Attribute */
+ uint32_t RESERVED17[55U]; /**< Reserved for future use */
+ __IM uint32_t BMPUFS_SET; /**< Fault Status */
+ __IM uint32_t BMPUFSADDR_SET; /**< Fault Status Address */
+ uint32_t RESERVED18[2U]; /**< Reserved for future use */
+ __IOM uint32_t ESAURTYPES0_SET; /**< Region Types 0 */
+ __IOM uint32_t ESAURTYPES1_SET; /**< Region Types 1 */
+ uint32_t RESERVED19[2U]; /**< Reserved for future use */
+ __IOM uint32_t ESAUMRB01_SET; /**< Movable Region Boundary */
+ __IOM uint32_t ESAUMRB12_SET; /**< Movable Region Boundary */
+ uint32_t RESERVED20[2U]; /**< Reserved for future use */
+ __IOM uint32_t ESAUMRB45_SET; /**< Movable Region Boundary */
+ __IOM uint32_t ESAUMRB56_SET; /**< Movable Region Boundary */
+ uint32_t RESERVED21[862U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP Version */
+ __IM uint32_t STATUS_CLR; /**< Status Register */
+ __IOM uint32_t LOCK_CLR; /**< Lock Register */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
+ uint32_t RESERVED22[3U]; /**< Reserved for future use */
+ __IOM uint32_t M33CTRL_CLR; /**< M33 Control Settings */
+ uint32_t RESERVED23[7U]; /**< Reserved for future use */
+ __IOM uint32_t PPUPATD0_CLR; /**< Privileged Access */
+ __IOM uint32_t PPUPATD1_CLR; /**< Privileged Access */
+ uint32_t RESERVED24[6U]; /**< Reserved for future use */
+ __IOM uint32_t PPUSATD0_CLR; /**< Secure Access */
+ __IOM uint32_t PPUSATD1_CLR; /**< Secure Access */
+ uint32_t RESERVED25[54U]; /**< Reserved for future use */
+ __IM uint32_t PPUFS_CLR; /**< Fault Status */
+ uint32_t RESERVED26[3U]; /**< Reserved for future use */
+ __IOM uint32_t BMPUPATD0_CLR; /**< Privileged Attribute */
+ uint32_t RESERVED27[7U]; /**< Reserved for future use */
+ __IOM uint32_t BMPUSATD0_CLR; /**< Secure Attribute */
+ uint32_t RESERVED28[55U]; /**< Reserved for future use */
+ __IM uint32_t BMPUFS_CLR; /**< Fault Status */
+ __IM uint32_t BMPUFSADDR_CLR; /**< Fault Status Address */
+ uint32_t RESERVED29[2U]; /**< Reserved for future use */
+ __IOM uint32_t ESAURTYPES0_CLR; /**< Region Types 0 */
+ __IOM uint32_t ESAURTYPES1_CLR; /**< Region Types 1 */
+ uint32_t RESERVED30[2U]; /**< Reserved for future use */
+ __IOM uint32_t ESAUMRB01_CLR; /**< Movable Region Boundary */
+ __IOM uint32_t ESAUMRB12_CLR; /**< Movable Region Boundary */
+ uint32_t RESERVED31[2U]; /**< Reserved for future use */
+ __IOM uint32_t ESAUMRB45_CLR; /**< Movable Region Boundary */
+ __IOM uint32_t ESAUMRB56_CLR; /**< Movable Region Boundary */
+ uint32_t RESERVED32[862U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP Version */
+ __IM uint32_t STATUS_TGL; /**< Status Register */
+ __IOM uint32_t LOCK_TGL; /**< Lock Register */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
+ uint32_t RESERVED33[3U]; /**< Reserved for future use */
+ __IOM uint32_t M33CTRL_TGL; /**< M33 Control Settings */
+ uint32_t RESERVED34[7U]; /**< Reserved for future use */
+ __IOM uint32_t PPUPATD0_TGL; /**< Privileged Access */
+ __IOM uint32_t PPUPATD1_TGL; /**< Privileged Access */
+ uint32_t RESERVED35[6U]; /**< Reserved for future use */
+ __IOM uint32_t PPUSATD0_TGL; /**< Secure Access */
+ __IOM uint32_t PPUSATD1_TGL; /**< Secure Access */
+ uint32_t RESERVED36[54U]; /**< Reserved for future use */
+ __IM uint32_t PPUFS_TGL; /**< Fault Status */
+ uint32_t RESERVED37[3U]; /**< Reserved for future use */
+ __IOM uint32_t BMPUPATD0_TGL; /**< Privileged Attribute */
+ uint32_t RESERVED38[7U]; /**< Reserved for future use */
+ __IOM uint32_t BMPUSATD0_TGL; /**< Secure Attribute */
+ uint32_t RESERVED39[55U]; /**< Reserved for future use */
+ __IM uint32_t BMPUFS_TGL; /**< Fault Status */
+ __IM uint32_t BMPUFSADDR_TGL; /**< Fault Status Address */
+ uint32_t RESERVED40[2U]; /**< Reserved for future use */
+ __IOM uint32_t ESAURTYPES0_TGL; /**< Region Types 0 */
+ __IOM uint32_t ESAURTYPES1_TGL; /**< Region Types 1 */
+ uint32_t RESERVED41[2U]; /**< Reserved for future use */
+ __IOM uint32_t ESAUMRB01_TGL; /**< Movable Region Boundary */
+ __IOM uint32_t ESAUMRB12_TGL; /**< Movable Region Boundary */
+ uint32_t RESERVED42[2U]; /**< Reserved for future use */
+ __IOM uint32_t ESAUMRB45_TGL; /**< Movable Region Boundary */
+ __IOM uint32_t ESAUMRB56_TGL; /**< Movable Region Boundary */
+} SMU_TypeDef;
+/** @} End of group EFR32MG24_SMU */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_SMU
+ * @{
+ * @defgroup EFR32MG24_SMU_BitFields SMU Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for SMU IPVERSION */
+#define _SMU_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for SMU_IPVERSION */
+#define _SMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SMU_IPVERSION */
+#define _SMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SMU_IPVERSION */
+#define _SMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_IPVERSION */
+#define _SMU_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for SMU_IPVERSION */
+#define SMU_IPVERSION_IPVERSION_DEFAULT (_SMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IPVERSION */
+
+/* Bit fields for SMU STATUS */
+#define _SMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for SMU_STATUS */
+#define _SMU_STATUS_MASK 0x00000003UL /**< Mask for SMU_STATUS */
+#define SMU_STATUS_SMULOCK (0x1UL << 0) /**< SMU Lock */
+#define _SMU_STATUS_SMULOCK_SHIFT 0 /**< Shift value for SMU_SMULOCK */
+#define _SMU_STATUS_SMULOCK_MASK 0x1UL /**< Bit mask for SMU_SMULOCK */
+#define _SMU_STATUS_SMULOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */
+#define _SMU_STATUS_SMULOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SMU_STATUS */
+#define _SMU_STATUS_SMULOCK_LOCKED 0x00000001UL /**< Mode LOCKED for SMU_STATUS */
+#define SMU_STATUS_SMULOCK_DEFAULT (_SMU_STATUS_SMULOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_STATUS */
+#define SMU_STATUS_SMULOCK_UNLOCKED (_SMU_STATUS_SMULOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for SMU_STATUS */
+#define SMU_STATUS_SMULOCK_LOCKED (_SMU_STATUS_SMULOCK_LOCKED << 0) /**< Shifted mode LOCKED for SMU_STATUS */
+#define SMU_STATUS_SMUPRGERR (0x1UL << 1) /**< SMU Programming Error */
+#define _SMU_STATUS_SMUPRGERR_SHIFT 1 /**< Shift value for SMU_SMUPRGERR */
+#define _SMU_STATUS_SMUPRGERR_MASK 0x2UL /**< Bit mask for SMU_SMUPRGERR */
+#define _SMU_STATUS_SMUPRGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */
+#define SMU_STATUS_SMUPRGERR_DEFAULT (_SMU_STATUS_SMUPRGERR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_STATUS */
+
+/* Bit fields for SMU LOCK */
+#define _SMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for SMU_LOCK */
+#define _SMU_LOCK_MASK 0x00FFFFFFUL /**< Mask for SMU_LOCK */
+#define _SMU_LOCK_SMULOCKKEY_SHIFT 0 /**< Shift value for SMU_SMULOCKKEY */
+#define _SMU_LOCK_SMULOCKKEY_MASK 0xFFFFFFUL /**< Bit mask for SMU_SMULOCKKEY */
+#define _SMU_LOCK_SMULOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_LOCK */
+#define _SMU_LOCK_SMULOCKKEY_UNLOCK 0x00ACCE55UL /**< Mode UNLOCK for SMU_LOCK */
+#define SMU_LOCK_SMULOCKKEY_DEFAULT (_SMU_LOCK_SMULOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_LOCK */
+#define SMU_LOCK_SMULOCKKEY_UNLOCK (_SMU_LOCK_SMULOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SMU_LOCK */
+
+/* Bit fields for SMU IF */
+#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */
+#define _SMU_IF_MASK 0x00030005UL /**< Mask for SMU_IF */
+#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */
+#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */
+#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */
+#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */
+#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */
+#define SMU_IF_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Flag */
+#define _SMU_IF_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */
+#define _SMU_IF_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */
+#define _SMU_IF_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */
+#define SMU_IF_PPUINST_DEFAULT (_SMU_IF_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IF */
+#define SMU_IF_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Flag */
+#define _SMU_IF_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */
+#define _SMU_IF_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */
+#define _SMU_IF_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */
+#define SMU_IF_PPUSEC_DEFAULT (_SMU_IF_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IF */
+#define SMU_IF_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Flag */
+#define _SMU_IF_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */
+#define _SMU_IF_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */
+#define _SMU_IF_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */
+#define SMU_IF_BMPUSEC_DEFAULT (_SMU_IF_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IF */
+
+/* Bit fields for SMU IEN */
+#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */
+#define _SMU_IEN_MASK 0x00030005UL /**< Mask for SMU_IEN */
+#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Enable */
+#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */
+#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */
+#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */
+#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */
+#define SMU_IEN_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Enable */
+#define _SMU_IEN_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */
+#define _SMU_IEN_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */
+#define _SMU_IEN_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */
+#define SMU_IEN_PPUINST_DEFAULT (_SMU_IEN_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IEN */
+#define SMU_IEN_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Enable */
+#define _SMU_IEN_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */
+#define _SMU_IEN_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */
+#define _SMU_IEN_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */
+#define SMU_IEN_PPUSEC_DEFAULT (_SMU_IEN_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IEN */
+#define SMU_IEN_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Enable */
+#define _SMU_IEN_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */
+#define _SMU_IEN_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */
+#define _SMU_IEN_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */
+#define SMU_IEN_BMPUSEC_DEFAULT (_SMU_IEN_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IEN */
+
+/* Bit fields for SMU M33CTRL */
+#define _SMU_M33CTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_M33CTRL */
+#define _SMU_M33CTRL_MASK 0x0000001FUL /**< Mask for SMU_M33CTRL */
+#define SMU_M33CTRL_LOCKSVTAIRCR (0x1UL << 0) /**< New BitField */
+#define _SMU_M33CTRL_LOCKSVTAIRCR_SHIFT 0 /**< Shift value for SMU_LOCKSVTAIRCR */
+#define _SMU_M33CTRL_LOCKSVTAIRCR_MASK 0x1UL /**< Bit mask for SMU_LOCKSVTAIRCR */
+#define _SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */
+#define SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT (_SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_M33CTRL */
+#define SMU_M33CTRL_LOCKNSVTOR (0x1UL << 1) /**< New BitField */
+#define _SMU_M33CTRL_LOCKNSVTOR_SHIFT 1 /**< Shift value for SMU_LOCKNSVTOR */
+#define _SMU_M33CTRL_LOCKNSVTOR_MASK 0x2UL /**< Bit mask for SMU_LOCKNSVTOR */
+#define _SMU_M33CTRL_LOCKNSVTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */
+#define SMU_M33CTRL_LOCKNSVTOR_DEFAULT (_SMU_M33CTRL_LOCKNSVTOR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_M33CTRL */
+#define SMU_M33CTRL_LOCKSMPU (0x1UL << 2) /**< New BitField */
+#define _SMU_M33CTRL_LOCKSMPU_SHIFT 2 /**< Shift value for SMU_LOCKSMPU */
+#define _SMU_M33CTRL_LOCKSMPU_MASK 0x4UL /**< Bit mask for SMU_LOCKSMPU */
+#define _SMU_M33CTRL_LOCKSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */
+#define SMU_M33CTRL_LOCKSMPU_DEFAULT (_SMU_M33CTRL_LOCKSMPU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_M33CTRL */
+#define SMU_M33CTRL_LOCKNSMPU (0x1UL << 3) /**< New BitField */
+#define _SMU_M33CTRL_LOCKNSMPU_SHIFT 3 /**< Shift value for SMU_LOCKNSMPU */
+#define _SMU_M33CTRL_LOCKNSMPU_MASK 0x8UL /**< Bit mask for SMU_LOCKNSMPU */
+#define _SMU_M33CTRL_LOCKNSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */
+#define SMU_M33CTRL_LOCKNSMPU_DEFAULT (_SMU_M33CTRL_LOCKNSMPU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_M33CTRL */
+#define SMU_M33CTRL_LOCKSAU (0x1UL << 4) /**< New BitField */
+#define _SMU_M33CTRL_LOCKSAU_SHIFT 4 /**< Shift value for SMU_LOCKSAU */
+#define _SMU_M33CTRL_LOCKSAU_MASK 0x10UL /**< Bit mask for SMU_LOCKSAU */
+#define _SMU_M33CTRL_LOCKSAU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */
+#define SMU_M33CTRL_LOCKSAU_DEFAULT (_SMU_M33CTRL_LOCKSAU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_M33CTRL */
+
+/* Bit fields for SMU PPUPATD0 */
+#define _SMU_PPUPATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUPATD0 */
+#define _SMU_PPUPATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_EMU (0x1UL << 1) /**< EMU Privileged Access */
+#define _SMU_PPUPATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */
+#define _SMU_PPUPATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */
+#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_CMU (0x1UL << 2) /**< CMU Privileged Access */
+#define _SMU_PPUPATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */
+#define _SMU_PPUPATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */
+#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_HFRCO0 (0x1UL << 3) /**< HFRCO0 Privileged Access */
+#define _SMU_PPUPATD0_HFRCO0_SHIFT 3 /**< Shift value for SMU_HFRCO0 */
+#define _SMU_PPUPATD0_HFRCO0_MASK 0x8UL /**< Bit mask for SMU_HFRCO0 */
+#define _SMU_PPUPATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_HFRCO0_DEFAULT (_SMU_PPUPATD0_HFRCO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_FSRCO (0x1UL << 4) /**< FSRCO Privileged Access */
+#define _SMU_PPUPATD0_FSRCO_SHIFT 4 /**< Shift value for SMU_FSRCO */
+#define _SMU_PPUPATD0_FSRCO_MASK 0x10UL /**< Bit mask for SMU_FSRCO */
+#define _SMU_PPUPATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_FSRCO_DEFAULT (_SMU_PPUPATD0_FSRCO_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_DPLL0 (0x1UL << 5) /**< DPLL0 Privileged Access */
+#define _SMU_PPUPATD0_DPLL0_SHIFT 5 /**< Shift value for SMU_DPLL0 */
+#define _SMU_PPUPATD0_DPLL0_MASK 0x20UL /**< Bit mask for SMU_DPLL0 */
+#define _SMU_PPUPATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_DPLL0_DEFAULT (_SMU_PPUPATD0_DPLL0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_LFXO (0x1UL << 6) /**< LFXO Privileged Access */
+#define _SMU_PPUPATD0_LFXO_SHIFT 6 /**< Shift value for SMU_LFXO */
+#define _SMU_PPUPATD0_LFXO_MASK 0x40UL /**< Bit mask for SMU_LFXO */
+#define _SMU_PPUPATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_LFXO_DEFAULT (_SMU_PPUPATD0_LFXO_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_LFRCO (0x1UL << 7) /**< LFRCO Privileged Access */
+#define _SMU_PPUPATD0_LFRCO_SHIFT 7 /**< Shift value for SMU_LFRCO */
+#define _SMU_PPUPATD0_LFRCO_MASK 0x80UL /**< Bit mask for SMU_LFRCO */
+#define _SMU_PPUPATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_LFRCO_DEFAULT (_SMU_PPUPATD0_LFRCO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_ULFRCO (0x1UL << 8) /**< ULFRCO Privileged Access */
+#define _SMU_PPUPATD0_ULFRCO_SHIFT 8 /**< Shift value for SMU_ULFRCO */
+#define _SMU_PPUPATD0_ULFRCO_MASK 0x100UL /**< Bit mask for SMU_ULFRCO */
+#define _SMU_PPUPATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_ULFRCO_DEFAULT (_SMU_PPUPATD0_ULFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_MSC (0x1UL << 9) /**< MSC Privileged Access */
+#define _SMU_PPUPATD0_MSC_SHIFT 9 /**< Shift value for SMU_MSC */
+#define _SMU_PPUPATD0_MSC_MASK 0x200UL /**< Bit mask for SMU_MSC */
+#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_ICACHE0 (0x1UL << 10) /**< ICACHE0 Privileged Access */
+#define _SMU_PPUPATD0_ICACHE0_SHIFT 10 /**< Shift value for SMU_ICACHE0 */
+#define _SMU_PPUPATD0_ICACHE0_MASK 0x400UL /**< Bit mask for SMU_ICACHE0 */
+#define _SMU_PPUPATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_ICACHE0_DEFAULT (_SMU_PPUPATD0_ICACHE0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_PRS (0x1UL << 11) /**< PRS Privileged Access */
+#define _SMU_PPUPATD0_PRS_SHIFT 11 /**< Shift value for SMU_PRS */
+#define _SMU_PPUPATD0_PRS_MASK 0x800UL /**< Bit mask for SMU_PRS */
+#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_GPIO (0x1UL << 12) /**< GPIO Privileged Access */
+#define _SMU_PPUPATD0_GPIO_SHIFT 12 /**< Shift value for SMU_GPIO */
+#define _SMU_PPUPATD0_GPIO_MASK 0x1000UL /**< Bit mask for SMU_GPIO */
+#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_LDMA (0x1UL << 13) /**< LDMA Privileged Access */
+#define _SMU_PPUPATD0_LDMA_SHIFT 13 /**< Shift value for SMU_LDMA */
+#define _SMU_PPUPATD0_LDMA_MASK 0x2000UL /**< Bit mask for SMU_LDMA */
+#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_LDMAXBAR (0x1UL << 14) /**< LDMAXBAR Privileged Access */
+#define _SMU_PPUPATD0_LDMAXBAR_SHIFT 14 /**< Shift value for SMU_LDMAXBAR */
+#define _SMU_PPUPATD0_LDMAXBAR_MASK 0x4000UL /**< Bit mask for SMU_LDMAXBAR */
+#define _SMU_PPUPATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_LDMAXBAR_DEFAULT (_SMU_PPUPATD0_LDMAXBAR_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_TIMER0 (0x1UL << 15) /**< TIMER0 Privileged Access */
+#define _SMU_PPUPATD0_TIMER0_SHIFT 15 /**< Shift value for SMU_TIMER0 */
+#define _SMU_PPUPATD0_TIMER0_MASK 0x8000UL /**< Bit mask for SMU_TIMER0 */
+#define _SMU_PPUPATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_TIMER0_DEFAULT (_SMU_PPUPATD0_TIMER0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_TIMER1 (0x1UL << 16) /**< TIMER1 Privileged Access */
+#define _SMU_PPUPATD0_TIMER1_SHIFT 16 /**< Shift value for SMU_TIMER1 */
+#define _SMU_PPUPATD0_TIMER1_MASK 0x10000UL /**< Bit mask for SMU_TIMER1 */
+#define _SMU_PPUPATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_TIMER1_DEFAULT (_SMU_PPUPATD0_TIMER1_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_TIMER2 (0x1UL << 17) /**< TIMER2 Privileged Access */
+#define _SMU_PPUPATD0_TIMER2_SHIFT 17 /**< Shift value for SMU_TIMER2 */
+#define _SMU_PPUPATD0_TIMER2_MASK 0x20000UL /**< Bit mask for SMU_TIMER2 */
+#define _SMU_PPUPATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_TIMER2_DEFAULT (_SMU_PPUPATD0_TIMER2_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_TIMER3 (0x1UL << 18) /**< TIMER3 Privileged Access */
+#define _SMU_PPUPATD0_TIMER3_SHIFT 18 /**< Shift value for SMU_TIMER3 */
+#define _SMU_PPUPATD0_TIMER3_MASK 0x40000UL /**< Bit mask for SMU_TIMER3 */
+#define _SMU_PPUPATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_TIMER3_DEFAULT (_SMU_PPUPATD0_TIMER3_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_TIMER4 (0x1UL << 19) /**< TIMER4 Privileged Access */
+#define _SMU_PPUPATD0_TIMER4_SHIFT 19 /**< Shift value for SMU_TIMER4 */
+#define _SMU_PPUPATD0_TIMER4_MASK 0x80000UL /**< Bit mask for SMU_TIMER4 */
+#define _SMU_PPUPATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_TIMER4_DEFAULT (_SMU_PPUPATD0_TIMER4_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_USART0 (0x1UL << 20) /**< USART0 Privileged Access */
+#define _SMU_PPUPATD0_USART0_SHIFT 20 /**< Shift value for SMU_USART0 */
+#define _SMU_PPUPATD0_USART0_MASK 0x100000UL /**< Bit mask for SMU_USART0 */
+#define _SMU_PPUPATD0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_USART0_DEFAULT (_SMU_PPUPATD0_USART0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_BURTC (0x1UL << 21) /**< BURTC Privileged Access */
+#define _SMU_PPUPATD0_BURTC_SHIFT 21 /**< Shift value for SMU_BURTC */
+#define _SMU_PPUPATD0_BURTC_MASK 0x200000UL /**< Bit mask for SMU_BURTC */
+#define _SMU_PPUPATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_BURTC_DEFAULT (_SMU_PPUPATD0_BURTC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_I2C1 (0x1UL << 22) /**< I2C1 Privileged Access */
+#define _SMU_PPUPATD0_I2C1_SHIFT 22 /**< Shift value for SMU_I2C1 */
+#define _SMU_PPUPATD0_I2C1_MASK 0x400000UL /**< Bit mask for SMU_I2C1 */
+#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_CHIPTESTCTRL (0x1UL << 23) /**< CHIPTESTCTRL Privileged Access */
+#define _SMU_PPUPATD0_CHIPTESTCTRL_SHIFT 23 /**< Shift value for SMU_CHIPTESTCTRL */
+#define _SMU_PPUPATD0_CHIPTESTCTRL_MASK 0x800000UL /**< Bit mask for SMU_CHIPTESTCTRL */
+#define _SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_SYSCFGCFGNS (0x1UL << 24) /**< SYSCFGCFGNS Privileged Access */
+#define _SMU_PPUPATD0_SYSCFGCFGNS_SHIFT 24 /**< Shift value for SMU_SYSCFGCFGNS */
+#define _SMU_PPUPATD0_SYSCFGCFGNS_MASK 0x1000000UL /**< Bit mask for SMU_SYSCFGCFGNS */
+#define _SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_SYSCFG (0x1UL << 25) /**< SYSCFG Privileged Access */
+#define _SMU_PPUPATD0_SYSCFG_SHIFT 25 /**< Shift value for SMU_SYSCFG */
+#define _SMU_PPUPATD0_SYSCFG_MASK 0x2000000UL /**< Bit mask for SMU_SYSCFG */
+#define _SMU_PPUPATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_SYSCFG_DEFAULT (_SMU_PPUPATD0_SYSCFG_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_BURAM (0x1UL << 26) /**< BURAM Privileged Access */
+#define _SMU_PPUPATD0_BURAM_SHIFT 26 /**< Shift value for SMU_BURAM */
+#define _SMU_PPUPATD0_BURAM_MASK 0x4000000UL /**< Bit mask for SMU_BURAM */
+#define _SMU_PPUPATD0_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_BURAM_DEFAULT (_SMU_PPUPATD0_BURAM_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_GPCRC (0x1UL << 27) /**< GPCRC Privileged Access */
+#define _SMU_PPUPATD0_GPCRC_SHIFT 27 /**< Shift value for SMU_GPCRC */
+#define _SMU_PPUPATD0_GPCRC_MASK 0x8000000UL /**< Bit mask for SMU_GPCRC */
+#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_DCDC (0x1UL << 28) /**< DCDC Privileged Access */
+#define _SMU_PPUPATD0_DCDC_SHIFT 28 /**< Shift value for SMU_DCDC */
+#define _SMU_PPUPATD0_DCDC_MASK 0x10000000UL /**< Bit mask for SMU_DCDC */
+#define _SMU_PPUPATD0_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_DCDC_DEFAULT (_SMU_PPUPATD0_DCDC_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_HOSTMAILBOX (0x1UL << 29) /**< HOSTMAILBOX Privileged Access */
+#define _SMU_PPUPATD0_HOSTMAILBOX_SHIFT 29 /**< Shift value for SMU_HOSTMAILBOX */
+#define _SMU_PPUPATD0_HOSTMAILBOX_MASK 0x20000000UL /**< Bit mask for SMU_HOSTMAILBOX */
+#define _SMU_PPUPATD0_HOSTMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_HOSTMAILBOX_DEFAULT (_SMU_PPUPATD0_HOSTMAILBOX_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_EUSART1 (0x1UL << 30) /**< EUSART1 Privileged Access */
+#define _SMU_PPUPATD0_EUSART1_SHIFT 30 /**< Shift value for SMU_EUSART1 */
+#define _SMU_PPUPATD0_EUSART1_MASK 0x40000000UL /**< Bit mask for SMU_EUSART1 */
+#define _SMU_PPUPATD0_EUSART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_EUSART1_DEFAULT (_SMU_PPUPATD0_EUSART1_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_SYSRTC (0x1UL << 31) /**< SYSRTC Privileged Access */
+#define _SMU_PPUPATD0_SYSRTC_SHIFT 31 /**< Shift value for SMU_SYSRTC */
+#define _SMU_PPUPATD0_SYSRTC_MASK 0x80000000UL /**< Bit mask for SMU_SYSRTC */
+#define _SMU_PPUPATD0_SYSRTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */
+#define SMU_PPUPATD0_SYSRTC_DEFAULT (_SMU_PPUPATD0_SYSRTC_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
+
+/* Bit fields for SMU PPUPATD1 */
+#define _SMU_PPUPATD1_RESETVALUE 0x003FFFFFUL /**< Default value for SMU_PPUPATD1 */
+#define _SMU_PPUPATD1_MASK 0x003FFFFFUL /**< Mask for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_KEYSCAN (0x1UL << 0) /**< KEYSCAN Privileged Access */
+#define _SMU_PPUPATD1_KEYSCAN_SHIFT 0 /**< Shift value for SMU_KEYSCAN */
+#define _SMU_PPUPATD1_KEYSCAN_MASK 0x1UL /**< Bit mask for SMU_KEYSCAN */
+#define _SMU_PPUPATD1_KEYSCAN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_KEYSCAN_DEFAULT (_SMU_PPUPATD1_KEYSCAN_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_DMEM (0x1UL << 1) /**< DMEM Privileged Access */
+#define _SMU_PPUPATD1_DMEM_SHIFT 1 /**< Shift value for SMU_DMEM */
+#define _SMU_PPUPATD1_DMEM_MASK 0x2UL /**< Bit mask for SMU_DMEM */
+#define _SMU_PPUPATD1_DMEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_DMEM_DEFAULT (_SMU_PPUPATD1_DMEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_RADIOAES (0x1UL << 2) /**< RADIOAES Privileged Access */
+#define _SMU_PPUPATD1_RADIOAES_SHIFT 2 /**< Shift value for SMU_RADIOAES */
+#define _SMU_PPUPATD1_RADIOAES_MASK 0x4UL /**< Bit mask for SMU_RADIOAES */
+#define _SMU_PPUPATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_RADIOAES_DEFAULT (_SMU_PPUPATD1_RADIOAES_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_SMU (0x1UL << 3) /**< SMU Privileged Access */
+#define _SMU_PPUPATD1_SMU_SHIFT 3 /**< Shift value for SMU_SMU */
+#define _SMU_PPUPATD1_SMU_MASK 0x8UL /**< Bit mask for SMU_SMU */
+#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_SMUCFGNS (0x1UL << 4) /**< SMUCFGNS Privileged Access */
+#define _SMU_PPUPATD1_SMUCFGNS_SHIFT 4 /**< Shift value for SMU_SMUCFGNS */
+#define _SMU_PPUPATD1_SMUCFGNS_MASK 0x10UL /**< Bit mask for SMU_SMUCFGNS */
+#define _SMU_PPUPATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_SMUCFGNS_DEFAULT (_SMU_PPUPATD1_SMUCFGNS_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_LETIMER0 (0x1UL << 5) /**< LETIMER0 Privileged Access */
+#define _SMU_PPUPATD1_LETIMER0_SHIFT 5 /**< Shift value for SMU_LETIMER0 */
+#define _SMU_PPUPATD1_LETIMER0_MASK 0x20UL /**< Bit mask for SMU_LETIMER0 */
+#define _SMU_PPUPATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_LETIMER0_DEFAULT (_SMU_PPUPATD1_LETIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_IADC0 (0x1UL << 6) /**< IADC0 Privileged Access */
+#define _SMU_PPUPATD1_IADC0_SHIFT 6 /**< Shift value for SMU_IADC0 */
+#define _SMU_PPUPATD1_IADC0_MASK 0x40UL /**< Bit mask for SMU_IADC0 */
+#define _SMU_PPUPATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_IADC0_DEFAULT (_SMU_PPUPATD1_IADC0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_ACMP0 (0x1UL << 7) /**< ACMP0 Privileged Access */
+#define _SMU_PPUPATD1_ACMP0_SHIFT 7 /**< Shift value for SMU_ACMP0 */
+#define _SMU_PPUPATD1_ACMP0_MASK 0x80UL /**< Bit mask for SMU_ACMP0 */
+#define _SMU_PPUPATD1_ACMP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_ACMP0_DEFAULT (_SMU_PPUPATD1_ACMP0_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_ACMP1 (0x1UL << 8) /**< ACMP1 Privileged Access */
+#define _SMU_PPUPATD1_ACMP1_SHIFT 8 /**< Shift value for SMU_ACMP1 */
+#define _SMU_PPUPATD1_ACMP1_MASK 0x100UL /**< Bit mask for SMU_ACMP1 */
+#define _SMU_PPUPATD1_ACMP1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_ACMP1_DEFAULT (_SMU_PPUPATD1_ACMP1_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_AMUXCP0 (0x1UL << 9) /**< AMUXCP0 Privileged Access */
+#define _SMU_PPUPATD1_AMUXCP0_SHIFT 9 /**< Shift value for SMU_AMUXCP0 */
+#define _SMU_PPUPATD1_AMUXCP0_MASK 0x200UL /**< Bit mask for SMU_AMUXCP0 */
+#define _SMU_PPUPATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_AMUXCP0_DEFAULT (_SMU_PPUPATD1_AMUXCP0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_VDAC0 (0x1UL << 10) /**< VDAC0 Privileged Access */
+#define _SMU_PPUPATD1_VDAC0_SHIFT 10 /**< Shift value for SMU_VDAC0 */
+#define _SMU_PPUPATD1_VDAC0_MASK 0x400UL /**< Bit mask for SMU_VDAC0 */
+#define _SMU_PPUPATD1_VDAC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_VDAC0_DEFAULT (_SMU_PPUPATD1_VDAC0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_VDAC1 (0x1UL << 11) /**< VDAC1 Privileged Access */
+#define _SMU_PPUPATD1_VDAC1_SHIFT 11 /**< Shift value for SMU_VDAC1 */
+#define _SMU_PPUPATD1_VDAC1_MASK 0x800UL /**< Bit mask for SMU_VDAC1 */
+#define _SMU_PPUPATD1_VDAC1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_VDAC1_DEFAULT (_SMU_PPUPATD1_VDAC1_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_PCNT (0x1UL << 12) /**< PCNT Privileged Access */
+#define _SMU_PPUPATD1_PCNT_SHIFT 12 /**< Shift value for SMU_PCNT */
+#define _SMU_PPUPATD1_PCNT_MASK 0x1000UL /**< Bit mask for SMU_PCNT */
+#define _SMU_PPUPATD1_PCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_PCNT_DEFAULT (_SMU_PPUPATD1_PCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_HFRCO1 (0x1UL << 13) /**< HFRCO1 Privileged Access */
+#define _SMU_PPUPATD1_HFRCO1_SHIFT 13 /**< Shift value for SMU_HFRCO1 */
+#define _SMU_PPUPATD1_HFRCO1_MASK 0x2000UL /**< Bit mask for SMU_HFRCO1 */
+#define _SMU_PPUPATD1_HFRCO1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_HFRCO1_DEFAULT (_SMU_PPUPATD1_HFRCO1_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_HFXO0 (0x1UL << 14) /**< HFXO0 Privileged Access */
+#define _SMU_PPUPATD1_HFXO0_SHIFT 14 /**< Shift value for SMU_HFXO0 */
+#define _SMU_PPUPATD1_HFXO0_MASK 0x4000UL /**< Bit mask for SMU_HFXO0 */
+#define _SMU_PPUPATD1_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_HFXO0_DEFAULT (_SMU_PPUPATD1_HFXO0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_I2C0 (0x1UL << 15) /**< I2C0 Privileged Access */
+#define _SMU_PPUPATD1_I2C0_SHIFT 15 /**< Shift value for SMU_I2C0 */
+#define _SMU_PPUPATD1_I2C0_MASK 0x8000UL /**< Bit mask for SMU_I2C0 */
+#define _SMU_PPUPATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_I2C0_DEFAULT (_SMU_PPUPATD1_I2C0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_WDOG0 (0x1UL << 16) /**< WDOG0 Privileged Access */
+#define _SMU_PPUPATD1_WDOG0_SHIFT 16 /**< Shift value for SMU_WDOG0 */
+#define _SMU_PPUPATD1_WDOG0_MASK 0x10000UL /**< Bit mask for SMU_WDOG0 */
+#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_WDOG1 (0x1UL << 17) /**< WDOG1 Privileged Access */
+#define _SMU_PPUPATD1_WDOG1_SHIFT 17 /**< Shift value for SMU_WDOG1 */
+#define _SMU_PPUPATD1_WDOG1_MASK 0x20000UL /**< Bit mask for SMU_WDOG1 */
+#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_EUSART0 (0x1UL << 18) /**< EUSART0 Privileged Access */
+#define _SMU_PPUPATD1_EUSART0_SHIFT 18 /**< Shift value for SMU_EUSART0 */
+#define _SMU_PPUPATD1_EUSART0_MASK 0x40000UL /**< Bit mask for SMU_EUSART0 */
+#define _SMU_PPUPATD1_EUSART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_EUSART0_DEFAULT (_SMU_PPUPATD1_EUSART0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_SEMAILBOX (0x1UL << 19) /**< SEMAILBOX Privileged Access */
+#define _SMU_PPUPATD1_SEMAILBOX_SHIFT 19 /**< Shift value for SMU_SEMAILBOX */
+#define _SMU_PPUPATD1_SEMAILBOX_MASK 0x80000UL /**< Bit mask for SMU_SEMAILBOX */
+#define _SMU_PPUPATD1_SEMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_SEMAILBOX_DEFAULT (_SMU_PPUPATD1_SEMAILBOX_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_MVP (0x1UL << 20) /**< MVP Privileged Access */
+#define _SMU_PPUPATD1_MVP_SHIFT 20 /**< Shift value for SMU_MVP */
+#define _SMU_PPUPATD1_MVP_MASK 0x100000UL /**< Bit mask for SMU_MVP */
+#define _SMU_PPUPATD1_MVP_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_MVP_DEFAULT (_SMU_PPUPATD1_MVP_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_AHBRADIO (0x1UL << 21) /**< AHBRADIO Privileged Access */
+#define _SMU_PPUPATD1_AHBRADIO_SHIFT 21 /**< Shift value for SMU_AHBRADIO */
+#define _SMU_PPUPATD1_AHBRADIO_MASK 0x200000UL /**< Bit mask for SMU_AHBRADIO */
+#define _SMU_PPUPATD1_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */
+#define SMU_PPUPATD1_AHBRADIO_DEFAULT (_SMU_PPUPATD1_AHBRADIO_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
+
+/* Bit fields for SMU PPUSATD0 */
+#define _SMU_PPUSATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUSATD0 */
+#define _SMU_PPUSATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_EMU (0x1UL << 1) /**< EMU Secure Access */
+#define _SMU_PPUSATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */
+#define _SMU_PPUSATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */
+#define _SMU_PPUSATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_EMU_DEFAULT (_SMU_PPUSATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_CMU (0x1UL << 2) /**< CMU Secure Access */
+#define _SMU_PPUSATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */
+#define _SMU_PPUSATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */
+#define _SMU_PPUSATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_CMU_DEFAULT (_SMU_PPUSATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_HFRCO0 (0x1UL << 3) /**< HFRCO0 Secure Access */
+#define _SMU_PPUSATD0_HFRCO0_SHIFT 3 /**< Shift value for SMU_HFRCO0 */
+#define _SMU_PPUSATD0_HFRCO0_MASK 0x8UL /**< Bit mask for SMU_HFRCO0 */
+#define _SMU_PPUSATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_HFRCO0_DEFAULT (_SMU_PPUSATD0_HFRCO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_FSRCO (0x1UL << 4) /**< FSRCO Secure Access */
+#define _SMU_PPUSATD0_FSRCO_SHIFT 4 /**< Shift value for SMU_FSRCO */
+#define _SMU_PPUSATD0_FSRCO_MASK 0x10UL /**< Bit mask for SMU_FSRCO */
+#define _SMU_PPUSATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_FSRCO_DEFAULT (_SMU_PPUSATD0_FSRCO_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_DPLL0 (0x1UL << 5) /**< DPLL0 Secure Access */
+#define _SMU_PPUSATD0_DPLL0_SHIFT 5 /**< Shift value for SMU_DPLL0 */
+#define _SMU_PPUSATD0_DPLL0_MASK 0x20UL /**< Bit mask for SMU_DPLL0 */
+#define _SMU_PPUSATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_DPLL0_DEFAULT (_SMU_PPUSATD0_DPLL0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_LFXO (0x1UL << 6) /**< LFXO Secure Access */
+#define _SMU_PPUSATD0_LFXO_SHIFT 6 /**< Shift value for SMU_LFXO */
+#define _SMU_PPUSATD0_LFXO_MASK 0x40UL /**< Bit mask for SMU_LFXO */
+#define _SMU_PPUSATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_LFXO_DEFAULT (_SMU_PPUSATD0_LFXO_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_LFRCO (0x1UL << 7) /**< LFRCO Secure Access */
+#define _SMU_PPUSATD0_LFRCO_SHIFT 7 /**< Shift value for SMU_LFRCO */
+#define _SMU_PPUSATD0_LFRCO_MASK 0x80UL /**< Bit mask for SMU_LFRCO */
+#define _SMU_PPUSATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_LFRCO_DEFAULT (_SMU_PPUSATD0_LFRCO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_ULFRCO (0x1UL << 8) /**< ULFRCO Secure Access */
+#define _SMU_PPUSATD0_ULFRCO_SHIFT 8 /**< Shift value for SMU_ULFRCO */
+#define _SMU_PPUSATD0_ULFRCO_MASK 0x100UL /**< Bit mask for SMU_ULFRCO */
+#define _SMU_PPUSATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_ULFRCO_DEFAULT (_SMU_PPUSATD0_ULFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_MSC (0x1UL << 9) /**< MSC Secure Access */
+#define _SMU_PPUSATD0_MSC_SHIFT 9 /**< Shift value for SMU_MSC */
+#define _SMU_PPUSATD0_MSC_MASK 0x200UL /**< Bit mask for SMU_MSC */
+#define _SMU_PPUSATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_MSC_DEFAULT (_SMU_PPUSATD0_MSC_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_ICACHE0 (0x1UL << 10) /**< ICACHE0 Secure Access */
+#define _SMU_PPUSATD0_ICACHE0_SHIFT 10 /**< Shift value for SMU_ICACHE0 */
+#define _SMU_PPUSATD0_ICACHE0_MASK 0x400UL /**< Bit mask for SMU_ICACHE0 */
+#define _SMU_PPUSATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_ICACHE0_DEFAULT (_SMU_PPUSATD0_ICACHE0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_PRS (0x1UL << 11) /**< PRS Secure Access */
+#define _SMU_PPUSATD0_PRS_SHIFT 11 /**< Shift value for SMU_PRS */
+#define _SMU_PPUSATD0_PRS_MASK 0x800UL /**< Bit mask for SMU_PRS */
+#define _SMU_PPUSATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_PRS_DEFAULT (_SMU_PPUSATD0_PRS_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_GPIO (0x1UL << 12) /**< GPIO Secure Access */
+#define _SMU_PPUSATD0_GPIO_SHIFT 12 /**< Shift value for SMU_GPIO */
+#define _SMU_PPUSATD0_GPIO_MASK 0x1000UL /**< Bit mask for SMU_GPIO */
+#define _SMU_PPUSATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_GPIO_DEFAULT (_SMU_PPUSATD0_GPIO_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_LDMA (0x1UL << 13) /**< LDMA Secure Access */
+#define _SMU_PPUSATD0_LDMA_SHIFT 13 /**< Shift value for SMU_LDMA */
+#define _SMU_PPUSATD0_LDMA_MASK 0x2000UL /**< Bit mask for SMU_LDMA */
+#define _SMU_PPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_LDMA_DEFAULT (_SMU_PPUSATD0_LDMA_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_LDMAXBAR (0x1UL << 14) /**< LDMAXBAR Secure Access */
+#define _SMU_PPUSATD0_LDMAXBAR_SHIFT 14 /**< Shift value for SMU_LDMAXBAR */
+#define _SMU_PPUSATD0_LDMAXBAR_MASK 0x4000UL /**< Bit mask for SMU_LDMAXBAR */
+#define _SMU_PPUSATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_LDMAXBAR_DEFAULT (_SMU_PPUSATD0_LDMAXBAR_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_TIMER0 (0x1UL << 15) /**< TIMER0 Secure Access */
+#define _SMU_PPUSATD0_TIMER0_SHIFT 15 /**< Shift value for SMU_TIMER0 */
+#define _SMU_PPUSATD0_TIMER0_MASK 0x8000UL /**< Bit mask for SMU_TIMER0 */
+#define _SMU_PPUSATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_TIMER0_DEFAULT (_SMU_PPUSATD0_TIMER0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_TIMER1 (0x1UL << 16) /**< TIMER1 Secure Access */
+#define _SMU_PPUSATD0_TIMER1_SHIFT 16 /**< Shift value for SMU_TIMER1 */
+#define _SMU_PPUSATD0_TIMER1_MASK 0x10000UL /**< Bit mask for SMU_TIMER1 */
+#define _SMU_PPUSATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_TIMER1_DEFAULT (_SMU_PPUSATD0_TIMER1_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_TIMER2 (0x1UL << 17) /**< TIMER2 Secure Access */
+#define _SMU_PPUSATD0_TIMER2_SHIFT 17 /**< Shift value for SMU_TIMER2 */
+#define _SMU_PPUSATD0_TIMER2_MASK 0x20000UL /**< Bit mask for SMU_TIMER2 */
+#define _SMU_PPUSATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_TIMER2_DEFAULT (_SMU_PPUSATD0_TIMER2_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_TIMER3 (0x1UL << 18) /**< TIMER3 Secure Access */
+#define _SMU_PPUSATD0_TIMER3_SHIFT 18 /**< Shift value for SMU_TIMER3 */
+#define _SMU_PPUSATD0_TIMER3_MASK 0x40000UL /**< Bit mask for SMU_TIMER3 */
+#define _SMU_PPUSATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_TIMER3_DEFAULT (_SMU_PPUSATD0_TIMER3_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_TIMER4 (0x1UL << 19) /**< TIMER4 Secure Access */
+#define _SMU_PPUSATD0_TIMER4_SHIFT 19 /**< Shift value for SMU_TIMER4 */
+#define _SMU_PPUSATD0_TIMER4_MASK 0x80000UL /**< Bit mask for SMU_TIMER4 */
+#define _SMU_PPUSATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_TIMER4_DEFAULT (_SMU_PPUSATD0_TIMER4_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_USART0 (0x1UL << 20) /**< USART0 Secure Access */
+#define _SMU_PPUSATD0_USART0_SHIFT 20 /**< Shift value for SMU_USART0 */
+#define _SMU_PPUSATD0_USART0_MASK 0x100000UL /**< Bit mask for SMU_USART0 */
+#define _SMU_PPUSATD0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_USART0_DEFAULT (_SMU_PPUSATD0_USART0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_BURTC (0x1UL << 21) /**< BURTC Secure Access */
+#define _SMU_PPUSATD0_BURTC_SHIFT 21 /**< Shift value for SMU_BURTC */
+#define _SMU_PPUSATD0_BURTC_MASK 0x200000UL /**< Bit mask for SMU_BURTC */
+#define _SMU_PPUSATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_BURTC_DEFAULT (_SMU_PPUSATD0_BURTC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_I2C1 (0x1UL << 22) /**< I2C1 Secure Access */
+#define _SMU_PPUSATD0_I2C1_SHIFT 22 /**< Shift value for SMU_I2C1 */
+#define _SMU_PPUSATD0_I2C1_MASK 0x400000UL /**< Bit mask for SMU_I2C1 */
+#define _SMU_PPUSATD0_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_I2C1_DEFAULT (_SMU_PPUSATD0_I2C1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_CHIPTESTCTRL (0x1UL << 23) /**< CHIPTESTCTRL Secure Access */
+#define _SMU_PPUSATD0_CHIPTESTCTRL_SHIFT 23 /**< Shift value for SMU_CHIPTESTCTRL */
+#define _SMU_PPUSATD0_CHIPTESTCTRL_MASK 0x800000UL /**< Bit mask for SMU_CHIPTESTCTRL */
+#define _SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_SYSCFGCFGNS (0x1UL << 24) /**< SYSCFGCFGNS Secure Access */
+#define _SMU_PPUSATD0_SYSCFGCFGNS_SHIFT 24 /**< Shift value for SMU_SYSCFGCFGNS */
+#define _SMU_PPUSATD0_SYSCFGCFGNS_MASK 0x1000000UL /**< Bit mask for SMU_SYSCFGCFGNS */
+#define _SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_SYSCFG (0x1UL << 25) /**< SYSCFG Secure Access */
+#define _SMU_PPUSATD0_SYSCFG_SHIFT 25 /**< Shift value for SMU_SYSCFG */
+#define _SMU_PPUSATD0_SYSCFG_MASK 0x2000000UL /**< Bit mask for SMU_SYSCFG */
+#define _SMU_PPUSATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_SYSCFG_DEFAULT (_SMU_PPUSATD0_SYSCFG_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_BURAM (0x1UL << 26) /**< BURAM Secure Access */
+#define _SMU_PPUSATD0_BURAM_SHIFT 26 /**< Shift value for SMU_BURAM */
+#define _SMU_PPUSATD0_BURAM_MASK 0x4000000UL /**< Bit mask for SMU_BURAM */
+#define _SMU_PPUSATD0_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_BURAM_DEFAULT (_SMU_PPUSATD0_BURAM_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_GPCRC (0x1UL << 27) /**< GPCRC Secure Access */
+#define _SMU_PPUSATD0_GPCRC_SHIFT 27 /**< Shift value for SMU_GPCRC */
+#define _SMU_PPUSATD0_GPCRC_MASK 0x8000000UL /**< Bit mask for SMU_GPCRC */
+#define _SMU_PPUSATD0_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_GPCRC_DEFAULT (_SMU_PPUSATD0_GPCRC_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_DCDC (0x1UL << 28) /**< DCDC Secure Access */
+#define _SMU_PPUSATD0_DCDC_SHIFT 28 /**< Shift value for SMU_DCDC */
+#define _SMU_PPUSATD0_DCDC_MASK 0x10000000UL /**< Bit mask for SMU_DCDC */
+#define _SMU_PPUSATD0_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_DCDC_DEFAULT (_SMU_PPUSATD0_DCDC_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_HOSTMAILBOX (0x1UL << 29) /**< HOSTMAILBOX Secure Access */
+#define _SMU_PPUSATD0_HOSTMAILBOX_SHIFT 29 /**< Shift value for SMU_HOSTMAILBOX */
+#define _SMU_PPUSATD0_HOSTMAILBOX_MASK 0x20000000UL /**< Bit mask for SMU_HOSTMAILBOX */
+#define _SMU_PPUSATD0_HOSTMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_HOSTMAILBOX_DEFAULT (_SMU_PPUSATD0_HOSTMAILBOX_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_EUSART1 (0x1UL << 30) /**< EUSART1 Secure Access */
+#define _SMU_PPUSATD0_EUSART1_SHIFT 30 /**< Shift value for SMU_EUSART1 */
+#define _SMU_PPUSATD0_EUSART1_MASK 0x40000000UL /**< Bit mask for SMU_EUSART1 */
+#define _SMU_PPUSATD0_EUSART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_EUSART1_DEFAULT (_SMU_PPUSATD0_EUSART1_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_SYSRTC (0x1UL << 31) /**< SYSRTC Secure Access */
+#define _SMU_PPUSATD0_SYSRTC_SHIFT 31 /**< Shift value for SMU_SYSRTC */
+#define _SMU_PPUSATD0_SYSRTC_MASK 0x80000000UL /**< Bit mask for SMU_SYSRTC */
+#define _SMU_PPUSATD0_SYSRTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */
+#define SMU_PPUSATD0_SYSRTC_DEFAULT (_SMU_PPUSATD0_SYSRTC_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */
+
+/* Bit fields for SMU PPUSATD1 */
+#define _SMU_PPUSATD1_RESETVALUE 0x003FFFFFUL /**< Default value for SMU_PPUSATD1 */
+#define _SMU_PPUSATD1_MASK 0x003FFFFFUL /**< Mask for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_KEYSCAN (0x1UL << 0) /**< KEYSCAN Secure Access */
+#define _SMU_PPUSATD1_KEYSCAN_SHIFT 0 /**< Shift value for SMU_KEYSCAN */
+#define _SMU_PPUSATD1_KEYSCAN_MASK 0x1UL /**< Bit mask for SMU_KEYSCAN */
+#define _SMU_PPUSATD1_KEYSCAN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_KEYSCAN_DEFAULT (_SMU_PPUSATD1_KEYSCAN_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_DMEM (0x1UL << 1) /**< DMEM Secure Access */
+#define _SMU_PPUSATD1_DMEM_SHIFT 1 /**< Shift value for SMU_DMEM */
+#define _SMU_PPUSATD1_DMEM_MASK 0x2UL /**< Bit mask for SMU_DMEM */
+#define _SMU_PPUSATD1_DMEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_DMEM_DEFAULT (_SMU_PPUSATD1_DMEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_RADIOAES (0x1UL << 2) /**< RADIOAES Secure Access */
+#define _SMU_PPUSATD1_RADIOAES_SHIFT 2 /**< Shift value for SMU_RADIOAES */
+#define _SMU_PPUSATD1_RADIOAES_MASK 0x4UL /**< Bit mask for SMU_RADIOAES */
+#define _SMU_PPUSATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_RADIOAES_DEFAULT (_SMU_PPUSATD1_RADIOAES_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_SMU (0x1UL << 3) /**< SMU Secure Access */
+#define _SMU_PPUSATD1_SMU_SHIFT 3 /**< Shift value for SMU_SMU */
+#define _SMU_PPUSATD1_SMU_MASK 0x8UL /**< Bit mask for SMU_SMU */
+#define _SMU_PPUSATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_SMU_DEFAULT (_SMU_PPUSATD1_SMU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_SMUCFGNS (0x1UL << 4) /**< SMUCFGNS Secure Access */
+#define _SMU_PPUSATD1_SMUCFGNS_SHIFT 4 /**< Shift value for SMU_SMUCFGNS */
+#define _SMU_PPUSATD1_SMUCFGNS_MASK 0x10UL /**< Bit mask for SMU_SMUCFGNS */
+#define _SMU_PPUSATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_SMUCFGNS_DEFAULT (_SMU_PPUSATD1_SMUCFGNS_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_LETIMER0 (0x1UL << 5) /**< LETIMER0 Secure Access */
+#define _SMU_PPUSATD1_LETIMER0_SHIFT 5 /**< Shift value for SMU_LETIMER0 */
+#define _SMU_PPUSATD1_LETIMER0_MASK 0x20UL /**< Bit mask for SMU_LETIMER0 */
+#define _SMU_PPUSATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_LETIMER0_DEFAULT (_SMU_PPUSATD1_LETIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_IADC0 (0x1UL << 6) /**< IADC0 Secure Access */
+#define _SMU_PPUSATD1_IADC0_SHIFT 6 /**< Shift value for SMU_IADC0 */
+#define _SMU_PPUSATD1_IADC0_MASK 0x40UL /**< Bit mask for SMU_IADC0 */
+#define _SMU_PPUSATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_IADC0_DEFAULT (_SMU_PPUSATD1_IADC0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_ACMP0 (0x1UL << 7) /**< ACMP0 Secure Access */
+#define _SMU_PPUSATD1_ACMP0_SHIFT 7 /**< Shift value for SMU_ACMP0 */
+#define _SMU_PPUSATD1_ACMP0_MASK 0x80UL /**< Bit mask for SMU_ACMP0 */
+#define _SMU_PPUSATD1_ACMP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_ACMP0_DEFAULT (_SMU_PPUSATD1_ACMP0_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_ACMP1 (0x1UL << 8) /**< ACMP1 Secure Access */
+#define _SMU_PPUSATD1_ACMP1_SHIFT 8 /**< Shift value for SMU_ACMP1 */
+#define _SMU_PPUSATD1_ACMP1_MASK 0x100UL /**< Bit mask for SMU_ACMP1 */
+#define _SMU_PPUSATD1_ACMP1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_ACMP1_DEFAULT (_SMU_PPUSATD1_ACMP1_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_AMUXCP0 (0x1UL << 9) /**< AMUXCP0 Secure Access */
+#define _SMU_PPUSATD1_AMUXCP0_SHIFT 9 /**< Shift value for SMU_AMUXCP0 */
+#define _SMU_PPUSATD1_AMUXCP0_MASK 0x200UL /**< Bit mask for SMU_AMUXCP0 */
+#define _SMU_PPUSATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_AMUXCP0_DEFAULT (_SMU_PPUSATD1_AMUXCP0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_VDAC0 (0x1UL << 10) /**< VDAC0 Secure Access */
+#define _SMU_PPUSATD1_VDAC0_SHIFT 10 /**< Shift value for SMU_VDAC0 */
+#define _SMU_PPUSATD1_VDAC0_MASK 0x400UL /**< Bit mask for SMU_VDAC0 */
+#define _SMU_PPUSATD1_VDAC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_VDAC0_DEFAULT (_SMU_PPUSATD1_VDAC0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_VDAC1 (0x1UL << 11) /**< VDAC1 Secure Access */
+#define _SMU_PPUSATD1_VDAC1_SHIFT 11 /**< Shift value for SMU_VDAC1 */
+#define _SMU_PPUSATD1_VDAC1_MASK 0x800UL /**< Bit mask for SMU_VDAC1 */
+#define _SMU_PPUSATD1_VDAC1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_VDAC1_DEFAULT (_SMU_PPUSATD1_VDAC1_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_PCNT (0x1UL << 12) /**< PCNT Secure Access */
+#define _SMU_PPUSATD1_PCNT_SHIFT 12 /**< Shift value for SMU_PCNT */
+#define _SMU_PPUSATD1_PCNT_MASK 0x1000UL /**< Bit mask for SMU_PCNT */
+#define _SMU_PPUSATD1_PCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_PCNT_DEFAULT (_SMU_PPUSATD1_PCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_HFRCO1 (0x1UL << 13) /**< HFRCO1 Secure Access */
+#define _SMU_PPUSATD1_HFRCO1_SHIFT 13 /**< Shift value for SMU_HFRCO1 */
+#define _SMU_PPUSATD1_HFRCO1_MASK 0x2000UL /**< Bit mask for SMU_HFRCO1 */
+#define _SMU_PPUSATD1_HFRCO1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_HFRCO1_DEFAULT (_SMU_PPUSATD1_HFRCO1_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_HFXO0 (0x1UL << 14) /**< HFXO0 Secure Access */
+#define _SMU_PPUSATD1_HFXO0_SHIFT 14 /**< Shift value for SMU_HFXO0 */
+#define _SMU_PPUSATD1_HFXO0_MASK 0x4000UL /**< Bit mask for SMU_HFXO0 */
+#define _SMU_PPUSATD1_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_HFXO0_DEFAULT (_SMU_PPUSATD1_HFXO0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_I2C0 (0x1UL << 15) /**< I2C0 Secure Access */
+#define _SMU_PPUSATD1_I2C0_SHIFT 15 /**< Shift value for SMU_I2C0 */
+#define _SMU_PPUSATD1_I2C0_MASK 0x8000UL /**< Bit mask for SMU_I2C0 */
+#define _SMU_PPUSATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_I2C0_DEFAULT (_SMU_PPUSATD1_I2C0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_WDOG0 (0x1UL << 16) /**< WDOG0 Secure Access */
+#define _SMU_PPUSATD1_WDOG0_SHIFT 16 /**< Shift value for SMU_WDOG0 */
+#define _SMU_PPUSATD1_WDOG0_MASK 0x10000UL /**< Bit mask for SMU_WDOG0 */
+#define _SMU_PPUSATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_WDOG0_DEFAULT (_SMU_PPUSATD1_WDOG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_WDOG1 (0x1UL << 17) /**< WDOG1 Secure Access */
+#define _SMU_PPUSATD1_WDOG1_SHIFT 17 /**< Shift value for SMU_WDOG1 */
+#define _SMU_PPUSATD1_WDOG1_MASK 0x20000UL /**< Bit mask for SMU_WDOG1 */
+#define _SMU_PPUSATD1_WDOG1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_WDOG1_DEFAULT (_SMU_PPUSATD1_WDOG1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_EUSART0 (0x1UL << 18) /**< EUSART0 Secure Access */
+#define _SMU_PPUSATD1_EUSART0_SHIFT 18 /**< Shift value for SMU_EUSART0 */
+#define _SMU_PPUSATD1_EUSART0_MASK 0x40000UL /**< Bit mask for SMU_EUSART0 */
+#define _SMU_PPUSATD1_EUSART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_EUSART0_DEFAULT (_SMU_PPUSATD1_EUSART0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_SEMAILBOX (0x1UL << 19) /**< SEMAILBOX Secure Access */
+#define _SMU_PPUSATD1_SEMAILBOX_SHIFT 19 /**< Shift value for SMU_SEMAILBOX */
+#define _SMU_PPUSATD1_SEMAILBOX_MASK 0x80000UL /**< Bit mask for SMU_SEMAILBOX */
+#define _SMU_PPUSATD1_SEMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_SEMAILBOX_DEFAULT (_SMU_PPUSATD1_SEMAILBOX_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_MVP (0x1UL << 20) /**< MVP Secure Access */
+#define _SMU_PPUSATD1_MVP_SHIFT 20 /**< Shift value for SMU_MVP */
+#define _SMU_PPUSATD1_MVP_MASK 0x100000UL /**< Bit mask for SMU_MVP */
+#define _SMU_PPUSATD1_MVP_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_MVP_DEFAULT (_SMU_PPUSATD1_MVP_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_AHBRADIO (0x1UL << 21) /**< AHBRADIO Secure Access */
+#define _SMU_PPUSATD1_AHBRADIO_SHIFT 21 /**< Shift value for SMU_AHBRADIO */
+#define _SMU_PPUSATD1_AHBRADIO_MASK 0x200000UL /**< Bit mask for SMU_AHBRADIO */
+#define _SMU_PPUSATD1_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */
+#define SMU_PPUSATD1_AHBRADIO_DEFAULT (_SMU_PPUSATD1_AHBRADIO_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */
+
+/* Bit fields for SMU PPUFS */
+#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */
+#define _SMU_PPUFS_MASK 0x000000FFUL /**< Mask for SMU_PPUFS */
+#define _SMU_PPUFS_PPUFSPERIPHID_SHIFT 0 /**< Shift value for SMU_PPUFSPERIPHID */
+#define _SMU_PPUFS_PPUFSPERIPHID_MASK 0xFFUL /**< Bit mask for SMU_PPUFSPERIPHID */
+#define _SMU_PPUFS_PPUFSPERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */
+#define SMU_PPUFS_PPUFSPERIPHID_DEFAULT (_SMU_PPUFS_PPUFSPERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */
+
+/* Bit fields for SMU BMPUPATD0 */
+#define _SMU_BMPUPATD0_RESETVALUE 0x0000003FUL /**< Default value for SMU_BMPUPATD0 */
+#define _SMU_BMPUPATD0_MASK 0x000001FFUL /**< Mask for SMU_BMPUPATD0 */
+#define SMU_BMPUPATD0_RADIOAES (0x1UL << 0) /**< RADIO AES DMA privileged mode */
+#define _SMU_BMPUPATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */
+#define _SMU_BMPUPATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */
+#define _SMU_BMPUPATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */
+#define SMU_BMPUPATD0_RADIOAES_DEFAULT (_SMU_BMPUPATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */
+#define SMU_BMPUPATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIO subsystem manager privileged mode */
+#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */
+#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */
+#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */
+#define SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */
+#define SMU_BMPUPATD0_LDMA (0x1UL << 2) /**< MCU LDMA privileged mode */
+#define _SMU_BMPUPATD0_LDMA_SHIFT 2 /**< Shift value for SMU_LDMA */
+#define _SMU_BMPUPATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */
+#define _SMU_BMPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */
+#define SMU_BMPUPATD0_LDMA_DEFAULT (_SMU_BMPUPATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */
+#define SMU_BMPUPATD0_MVPAHBDATA0 (0x1UL << 3) /**< MVPAHBDATA0 privileged mode */
+#define _SMU_BMPUPATD0_MVPAHBDATA0_SHIFT 3 /**< Shift value for SMU_MVPAHBDATA0 */
+#define _SMU_BMPUPATD0_MVPAHBDATA0_MASK 0x8UL /**< Bit mask for SMU_MVPAHBDATA0 */
+#define _SMU_BMPUPATD0_MVPAHBDATA0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */
+#define SMU_BMPUPATD0_MVPAHBDATA0_DEFAULT (_SMU_BMPUPATD0_MVPAHBDATA0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */
+#define SMU_BMPUPATD0_MVPAHBDATA1 (0x1UL << 4) /**< MVPAHBDATA1 privileged mode */
+#define _SMU_BMPUPATD0_MVPAHBDATA1_SHIFT 4 /**< Shift value for SMU_MVPAHBDATA1 */
+#define _SMU_BMPUPATD0_MVPAHBDATA1_MASK 0x10UL /**< Bit mask for SMU_MVPAHBDATA1 */
+#define _SMU_BMPUPATD0_MVPAHBDATA1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */
+#define SMU_BMPUPATD0_MVPAHBDATA1_DEFAULT (_SMU_BMPUPATD0_MVPAHBDATA1_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */
+#define SMU_BMPUPATD0_MVPAHBDATA2 (0x1UL << 5) /**< MVPAHBDATA2 privileged mode */
+#define _SMU_BMPUPATD0_MVPAHBDATA2_SHIFT 5 /**< Shift value for SMU_MVPAHBDATA2 */
+#define _SMU_BMPUPATD0_MVPAHBDATA2_MASK 0x20UL /**< Bit mask for SMU_MVPAHBDATA2 */
+#define _SMU_BMPUPATD0_MVPAHBDATA2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */
+#define SMU_BMPUPATD0_MVPAHBDATA2_DEFAULT (_SMU_BMPUPATD0_MVPAHBDATA2_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */
+#define SMU_BMPUPATD0_RFECA0 (0x1UL << 6) /**< RFECA0 privileged mode */
+#define _SMU_BMPUPATD0_RFECA0_SHIFT 6 /**< Shift value for SMU_RFECA0 */
+#define _SMU_BMPUPATD0_RFECA0_MASK 0x40UL /**< Bit mask for SMU_RFECA0 */
+#define _SMU_BMPUPATD0_RFECA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUPATD0 */
+#define SMU_BMPUPATD0_RFECA0_DEFAULT (_SMU_BMPUPATD0_RFECA0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */
+#define SMU_BMPUPATD0_RFECA1 (0x1UL << 7) /**< RFECA1 privileged mode */
+#define _SMU_BMPUPATD0_RFECA1_SHIFT 7 /**< Shift value for SMU_RFECA1 */
+#define _SMU_BMPUPATD0_RFECA1_MASK 0x80UL /**< Bit mask for SMU_RFECA1 */
+#define _SMU_BMPUPATD0_RFECA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUPATD0 */
+#define SMU_BMPUPATD0_RFECA1_DEFAULT (_SMU_BMPUPATD0_RFECA1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */
+#define SMU_BMPUPATD0_SEEXTDMA (0x1UL << 8) /**< SEEXTDMA privileged mode */
+#define _SMU_BMPUPATD0_SEEXTDMA_SHIFT 8 /**< Shift value for SMU_SEEXTDMA */
+#define _SMU_BMPUPATD0_SEEXTDMA_MASK 0x100UL /**< Bit mask for SMU_SEEXTDMA */
+#define _SMU_BMPUPATD0_SEEXTDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUPATD0 */
+#define SMU_BMPUPATD0_SEEXTDMA_DEFAULT (_SMU_BMPUPATD0_SEEXTDMA_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */
+
+/* Bit fields for SMU BMPUSATD0 */
+#define _SMU_BMPUSATD0_RESETVALUE 0x0000003FUL /**< Default value for SMU_BMPUSATD0 */
+#define _SMU_BMPUSATD0_MASK 0x000001FFUL /**< Mask for SMU_BMPUSATD0 */
+#define SMU_BMPUSATD0_RADIOAES (0x1UL << 0) /**< RADIOAES DMA secure mode */
+#define _SMU_BMPUSATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */
+#define _SMU_BMPUSATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */
+#define _SMU_BMPUSATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */
+#define SMU_BMPUSATD0_RADIOAES_DEFAULT (_SMU_BMPUSATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */
+#define SMU_BMPUSATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIO subsystem manager secure mode */
+#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */
+#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */
+#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */
+#define SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */
+#define SMU_BMPUSATD0_LDMA (0x1UL << 2) /**< MCU LDMA secure mode */
+#define _SMU_BMPUSATD0_LDMA_SHIFT 2 /**< Shift value for SMU_LDMA */
+#define _SMU_BMPUSATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */
+#define _SMU_BMPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */
+#define SMU_BMPUSATD0_LDMA_DEFAULT (_SMU_BMPUSATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */
+#define SMU_BMPUSATD0_MVPAHBDATA0 (0x1UL << 3) /**< MVPAHBDATA0 secure mode */
+#define _SMU_BMPUSATD0_MVPAHBDATA0_SHIFT 3 /**< Shift value for SMU_MVPAHBDATA0 */
+#define _SMU_BMPUSATD0_MVPAHBDATA0_MASK 0x8UL /**< Bit mask for SMU_MVPAHBDATA0 */
+#define _SMU_BMPUSATD0_MVPAHBDATA0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */
+#define SMU_BMPUSATD0_MVPAHBDATA0_DEFAULT (_SMU_BMPUSATD0_MVPAHBDATA0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */
+#define SMU_BMPUSATD0_MVPAHBDATA1 (0x1UL << 4) /**< MVPAHBDATA1 secure mode */
+#define _SMU_BMPUSATD0_MVPAHBDATA1_SHIFT 4 /**< Shift value for SMU_MVPAHBDATA1 */
+#define _SMU_BMPUSATD0_MVPAHBDATA1_MASK 0x10UL /**< Bit mask for SMU_MVPAHBDATA1 */
+#define _SMU_BMPUSATD0_MVPAHBDATA1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */
+#define SMU_BMPUSATD0_MVPAHBDATA1_DEFAULT (_SMU_BMPUSATD0_MVPAHBDATA1_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */
+#define SMU_BMPUSATD0_MVPAHBDATA2 (0x1UL << 5) /**< MVPAHBDATA2 secure mode */
+#define _SMU_BMPUSATD0_MVPAHBDATA2_SHIFT 5 /**< Shift value for SMU_MVPAHBDATA2 */
+#define _SMU_BMPUSATD0_MVPAHBDATA2_MASK 0x20UL /**< Bit mask for SMU_MVPAHBDATA2 */
+#define _SMU_BMPUSATD0_MVPAHBDATA2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */
+#define SMU_BMPUSATD0_MVPAHBDATA2_DEFAULT (_SMU_BMPUSATD0_MVPAHBDATA2_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */
+#define SMU_BMPUSATD0_RFECA0 (0x1UL << 6) /**< RFECA0 secure mode */
+#define _SMU_BMPUSATD0_RFECA0_SHIFT 6 /**< Shift value for SMU_RFECA0 */
+#define _SMU_BMPUSATD0_RFECA0_MASK 0x40UL /**< Bit mask for SMU_RFECA0 */
+#define _SMU_BMPUSATD0_RFECA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUSATD0 */
+#define SMU_BMPUSATD0_RFECA0_DEFAULT (_SMU_BMPUSATD0_RFECA0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */
+#define SMU_BMPUSATD0_RFECA1 (0x1UL << 7) /**< RFECA1 secure mode */
+#define _SMU_BMPUSATD0_RFECA1_SHIFT 7 /**< Shift value for SMU_RFECA1 */
+#define _SMU_BMPUSATD0_RFECA1_MASK 0x80UL /**< Bit mask for SMU_RFECA1 */
+#define _SMU_BMPUSATD0_RFECA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUSATD0 */
+#define SMU_BMPUSATD0_RFECA1_DEFAULT (_SMU_BMPUSATD0_RFECA1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */
+#define SMU_BMPUSATD0_SEEXTDMA (0x1UL << 8) /**< SEEXTDMA secure mode */
+#define _SMU_BMPUSATD0_SEEXTDMA_SHIFT 8 /**< Shift value for SMU_SEEXTDMA */
+#define _SMU_BMPUSATD0_SEEXTDMA_MASK 0x100UL /**< Bit mask for SMU_SEEXTDMA */
+#define _SMU_BMPUSATD0_SEEXTDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUSATD0 */
+#define SMU_BMPUSATD0_SEEXTDMA_DEFAULT (_SMU_BMPUSATD0_SEEXTDMA_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */
+
+/* Bit fields for SMU BMPUFS */
+#define _SMU_BMPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFS */
+#define _SMU_BMPUFS_MASK 0x000000FFUL /**< Mask for SMU_BMPUFS */
+#define _SMU_BMPUFS_BMPUFSMASTERID_SHIFT 0 /**< Shift value for SMU_BMPUFSMASTERID */
+#define _SMU_BMPUFS_BMPUFSMASTERID_MASK 0xFFUL /**< Bit mask for SMU_BMPUFSMASTERID */
+#define _SMU_BMPUFS_BMPUFSMASTERID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFS */
+#define SMU_BMPUFS_BMPUFSMASTERID_DEFAULT (_SMU_BMPUFS_BMPUFSMASTERID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFS */
+
+/* Bit fields for SMU BMPUFSADDR */
+#define _SMU_BMPUFSADDR_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFSADDR */
+#define _SMU_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Mask for SMU_BMPUFSADDR */
+#define _SMU_BMPUFSADDR_BMPUFSADDR_SHIFT 0 /**< Shift value for SMU_BMPUFSADDR */
+#define _SMU_BMPUFSADDR_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_BMPUFSADDR */
+#define _SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFSADDR */
+#define SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT (_SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFSADDR */
+
+/* Bit fields for SMU ESAURTYPES0 */
+#define _SMU_ESAURTYPES0_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES0 */
+#define _SMU_ESAURTYPES0_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES0 */
+#define SMU_ESAURTYPES0_ESAUR3NS (0x1UL << 12) /**< Region 3 Non-Secure */
+#define _SMU_ESAURTYPES0_ESAUR3NS_SHIFT 12 /**< Shift value for SMU_ESAUR3NS */
+#define _SMU_ESAURTYPES0_ESAUR3NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR3NS */
+#define _SMU_ESAURTYPES0_ESAUR3NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES0 */
+#define SMU_ESAURTYPES0_ESAUR3NS_DEFAULT (_SMU_ESAURTYPES0_ESAUR3NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES0 */
+
+/* Bit fields for SMU ESAURTYPES1 */
+#define _SMU_ESAURTYPES1_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES1 */
+#define _SMU_ESAURTYPES1_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES1 */
+#define SMU_ESAURTYPES1_ESAUR11NS (0x1UL << 12) /**< Region 11 Non-Secure */
+#define _SMU_ESAURTYPES1_ESAUR11NS_SHIFT 12 /**< Shift value for SMU_ESAUR11NS */
+#define _SMU_ESAURTYPES1_ESAUR11NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR11NS */
+#define _SMU_ESAURTYPES1_ESAUR11NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES1 */
+#define SMU_ESAURTYPES1_ESAUR11NS_DEFAULT (_SMU_ESAURTYPES1_ESAUR11NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES1 */
+
+/* Bit fields for SMU ESAUMRB01 */
+#define _SMU_ESAUMRB01_RESETVALUE 0x0A000000UL /**< Default value for SMU_ESAUMRB01 */
+#define _SMU_ESAUMRB01_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB01 */
+#define _SMU_ESAUMRB01_ESAUMRB01_SHIFT 12 /**< Shift value for SMU_ESAUMRB01 */
+#define _SMU_ESAUMRB01_ESAUMRB01_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB01 */
+#define _SMU_ESAUMRB01_ESAUMRB01_DEFAULT 0x0000A000UL /**< Mode DEFAULT for SMU_ESAUMRB01 */
+#define SMU_ESAUMRB01_ESAUMRB01_DEFAULT (_SMU_ESAUMRB01_ESAUMRB01_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB01 */
+
+/* Bit fields for SMU ESAUMRB12 */
+#define _SMU_ESAUMRB12_RESETVALUE 0x0C000000UL /**< Default value for SMU_ESAUMRB12 */
+#define _SMU_ESAUMRB12_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB12 */
+#define _SMU_ESAUMRB12_ESAUMRB12_SHIFT 12 /**< Shift value for SMU_ESAUMRB12 */
+#define _SMU_ESAUMRB12_ESAUMRB12_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB12 */
+#define _SMU_ESAUMRB12_ESAUMRB12_DEFAULT 0x0000C000UL /**< Mode DEFAULT for SMU_ESAUMRB12 */
+#define SMU_ESAUMRB12_ESAUMRB12_DEFAULT (_SMU_ESAUMRB12_ESAUMRB12_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB12 */
+
+/* Bit fields for SMU ESAUMRB45 */
+#define _SMU_ESAUMRB45_RESETVALUE 0x02000000UL /**< Default value for SMU_ESAUMRB45 */
+#define _SMU_ESAUMRB45_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB45 */
+#define _SMU_ESAUMRB45_ESAUMRB45_SHIFT 12 /**< Shift value for SMU_ESAUMRB45 */
+#define _SMU_ESAUMRB45_ESAUMRB45_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB45 */
+#define _SMU_ESAUMRB45_ESAUMRB45_DEFAULT 0x00002000UL /**< Mode DEFAULT for SMU_ESAUMRB45 */
+#define SMU_ESAUMRB45_ESAUMRB45_DEFAULT (_SMU_ESAUMRB45_ESAUMRB45_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB45 */
+
+/* Bit fields for SMU ESAUMRB56 */
+#define _SMU_ESAUMRB56_RESETVALUE 0x04000000UL /**< Default value for SMU_ESAUMRB56 */
+#define _SMU_ESAUMRB56_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB56 */
+#define _SMU_ESAUMRB56_ESAUMRB56_SHIFT 12 /**< Shift value for SMU_ESAUMRB56 */
+#define _SMU_ESAUMRB56_ESAUMRB56_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB56 */
+#define _SMU_ESAUMRB56_ESAUMRB56_DEFAULT 0x00004000UL /**< Mode DEFAULT for SMU_ESAUMRB56 */
+#define SMU_ESAUMRB56_ESAUMRB56_DEFAULT (_SMU_ESAUMRB56_ESAUMRB56_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB56 */
+
+/** @} End of group EFR32MG24_SMU_BitFields */
+/** @} End of group EFR32MG24_SMU */
+/**************************************************************************//**
+ * @defgroup EFR32MG24_SMU_CFGNS SMU_CFGNS
+ * @{
+ * @brief EFR32MG24 SMU_CFGNS Register Declaration.
+ *****************************************************************************/
+
+/** SMU_CFGNS Register Declaration. */
+typedef struct {
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+ __IM uint32_t NSSTATUS; /**< Status Register */
+ __IOM uint32_t NSLOCK; /**< Lock Register */
+ __IOM uint32_t NSIF; /**< Interrupt Flag Register */
+ __IOM uint32_t NSIEN; /**< Interrupt Enable Register */
+ uint32_t RESERVED1[3U]; /**< Reserved for future use */
+ uint32_t RESERVED2[8U]; /**< Reserved for future use */
+ __IOM uint32_t PPUNSPATD0; /**< Privileged Access */
+ __IOM uint32_t PPUNSPATD1; /**< Privileged Access */
+ uint32_t RESERVED3[62U]; /**< Reserved for future use */
+ __IM uint32_t PPUNSFS; /**< Fault Status */
+ uint32_t RESERVED4[3U]; /**< Reserved for future use */
+ __IOM uint32_t BMPUNSPATD0; /**< Privileged Attribute */
+ uint32_t RESERVED5[63U]; /**< Reserved for future use */
+ uint32_t RESERVED6[876U]; /**< Reserved for future use */
+ uint32_t RESERVED7[1U]; /**< Reserved for future use */
+ __IM uint32_t NSSTATUS_SET; /**< Status Register */
+ __IOM uint32_t NSLOCK_SET; /**< Lock Register */
+ __IOM uint32_t NSIF_SET; /**< Interrupt Flag Register */
+ __IOM uint32_t NSIEN_SET; /**< Interrupt Enable Register */
+ uint32_t RESERVED8[3U]; /**< Reserved for future use */
+ uint32_t RESERVED9[8U]; /**< Reserved for future use */
+ __IOM uint32_t PPUNSPATD0_SET; /**< Privileged Access */
+ __IOM uint32_t PPUNSPATD1_SET; /**< Privileged Access */
+ uint32_t RESERVED10[62U]; /**< Reserved for future use */
+ __IM uint32_t PPUNSFS_SET; /**< Fault Status */
+ uint32_t RESERVED11[3U]; /**< Reserved for future use */
+ __IOM uint32_t BMPUNSPATD0_SET; /**< Privileged Attribute */
+ uint32_t RESERVED12[63U]; /**< Reserved for future use */
+ uint32_t RESERVED13[876U]; /**< Reserved for future use */
+ uint32_t RESERVED14[1U]; /**< Reserved for future use */
+ __IM uint32_t NSSTATUS_CLR; /**< Status Register */
+ __IOM uint32_t NSLOCK_CLR; /**< Lock Register */
+ __IOM uint32_t NSIF_CLR; /**< Interrupt Flag Register */
+ __IOM uint32_t NSIEN_CLR; /**< Interrupt Enable Register */
+ uint32_t RESERVED15[3U]; /**< Reserved for future use */
+ uint32_t RESERVED16[8U]; /**< Reserved for future use */
+ __IOM uint32_t PPUNSPATD0_CLR; /**< Privileged Access */
+ __IOM uint32_t PPUNSPATD1_CLR; /**< Privileged Access */
+ uint32_t RESERVED17[62U]; /**< Reserved for future use */
+ __IM uint32_t PPUNSFS_CLR; /**< Fault Status */
+ uint32_t RESERVED18[3U]; /**< Reserved for future use */
+ __IOM uint32_t BMPUNSPATD0_CLR; /**< Privileged Attribute */
+ uint32_t RESERVED19[63U]; /**< Reserved for future use */
+ uint32_t RESERVED20[876U]; /**< Reserved for future use */
+ uint32_t RESERVED21[1U]; /**< Reserved for future use */
+ __IM uint32_t NSSTATUS_TGL; /**< Status Register */
+ __IOM uint32_t NSLOCK_TGL; /**< Lock Register */
+ __IOM uint32_t NSIF_TGL; /**< Interrupt Flag Register */
+ __IOM uint32_t NSIEN_TGL; /**< Interrupt Enable Register */
+ uint32_t RESERVED22[3U]; /**< Reserved for future use */
+ uint32_t RESERVED23[8U]; /**< Reserved for future use */
+ __IOM uint32_t PPUNSPATD0_TGL; /**< Privileged Access */
+ __IOM uint32_t PPUNSPATD1_TGL; /**< Privileged Access */
+ uint32_t RESERVED24[62U]; /**< Reserved for future use */
+ __IM uint32_t PPUNSFS_TGL; /**< Fault Status */
+ uint32_t RESERVED25[3U]; /**< Reserved for future use */
+ __IOM uint32_t BMPUNSPATD0_TGL; /**< Privileged Attribute */
+ uint32_t RESERVED26[63U]; /**< Reserved for future use */
+} SMU_CFGNS_TypeDef;
+/** @} End of group EFR32MG24_SMU_CFGNS */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_SMU_CFGNS
+ * @{
+ * @defgroup EFR32MG24_SMU_CFGNS_BitFields SMU_CFGNS Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for SMU NSSTATUS */
+#define _SMU_NSSTATUS_RESETVALUE 0x00000000UL /**< Default value for SMU_NSSTATUS */
+#define _SMU_NSSTATUS_MASK 0x00000001UL /**< Mask for SMU_NSSTATUS */
+#define SMU_NSSTATUS_SMUNSLOCK (0x1UL << 0) /**< SMUNS Lock */
+#define _SMU_NSSTATUS_SMUNSLOCK_SHIFT 0 /**< Shift value for SMU_SMUNSLOCK */
+#define _SMU_NSSTATUS_SMUNSLOCK_MASK 0x1UL /**< Bit mask for SMU_SMUNSLOCK */
+#define _SMU_NSSTATUS_SMUNSLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSSTATUS */
+#define _SMU_NSSTATUS_SMUNSLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SMU_NSSTATUS */
+#define _SMU_NSSTATUS_SMUNSLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for SMU_NSSTATUS */
+#define SMU_NSSTATUS_SMUNSLOCK_DEFAULT (_SMU_NSSTATUS_SMUNSLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSSTATUS */
+#define SMU_NSSTATUS_SMUNSLOCK_UNLOCKED (_SMU_NSSTATUS_SMUNSLOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for SMU_NSSTATUS */
+#define SMU_NSSTATUS_SMUNSLOCK_LOCKED (_SMU_NSSTATUS_SMUNSLOCK_LOCKED << 0) /**< Shifted mode LOCKED for SMU_NSSTATUS */
+
+/* Bit fields for SMU NSLOCK */
+#define _SMU_NSLOCK_RESETVALUE 0x00000000UL /**< Default value for SMU_NSLOCK */
+#define _SMU_NSLOCK_MASK 0x00FFFFFFUL /**< Mask for SMU_NSLOCK */
+#define _SMU_NSLOCK_SMUNSLOCKKEY_SHIFT 0 /**< Shift value for SMU_SMUNSLOCKKEY */
+#define _SMU_NSLOCK_SMUNSLOCKKEY_MASK 0xFFFFFFUL /**< Bit mask for SMU_SMUNSLOCKKEY */
+#define _SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSLOCK */
+#define _SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK 0x00ACCE55UL /**< Mode UNLOCK for SMU_NSLOCK */
+#define SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT (_SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSLOCK */
+#define SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK (_SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SMU_NSLOCK */
+
+/* Bit fields for SMU NSIF */
+#define _SMU_NSIF_RESETVALUE 0x00000000UL /**< Default value for SMU_NSIF */
+#define _SMU_NSIF_MASK 0x00000005UL /**< Mask for SMU_NSIF */
+#define SMU_NSIF_PPUNSPRIV (0x1UL << 0) /**< PPUNS Privilege Interrupt Flag */
+#define _SMU_NSIF_PPUNSPRIV_SHIFT 0 /**< Shift value for SMU_PPUNSPRIV */
+#define _SMU_NSIF_PPUNSPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUNSPRIV */
+#define _SMU_NSIF_PPUNSPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIF */
+#define SMU_NSIF_PPUNSPRIV_DEFAULT (_SMU_NSIF_PPUNSPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSIF */
+#define SMU_NSIF_PPUNSINST (0x1UL << 2) /**< PPUNS Instruction Interrupt Flag */
+#define _SMU_NSIF_PPUNSINST_SHIFT 2 /**< Shift value for SMU_PPUNSINST */
+#define _SMU_NSIF_PPUNSINST_MASK 0x4UL /**< Bit mask for SMU_PPUNSINST */
+#define _SMU_NSIF_PPUNSINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIF */
+#define SMU_NSIF_PPUNSINST_DEFAULT (_SMU_NSIF_PPUNSINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_NSIF */
+
+/* Bit fields for SMU NSIEN */
+#define _SMU_NSIEN_RESETVALUE 0x00000000UL /**< Default value for SMU_NSIEN */
+#define _SMU_NSIEN_MASK 0x00000005UL /**< Mask for SMU_NSIEN */
+#define SMU_NSIEN_PPUNSPRIV (0x1UL << 0) /**< PPUNS Privilege Interrupt Enable */
+#define _SMU_NSIEN_PPUNSPRIV_SHIFT 0 /**< Shift value for SMU_PPUNSPRIV */
+#define _SMU_NSIEN_PPUNSPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUNSPRIV */
+#define _SMU_NSIEN_PPUNSPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIEN */
+#define SMU_NSIEN_PPUNSPRIV_DEFAULT (_SMU_NSIEN_PPUNSPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSIEN */
+#define SMU_NSIEN_PPUNSINST (0x1UL << 2) /**< PPUNS Instruction Interrupt Enable */
+#define _SMU_NSIEN_PPUNSINST_SHIFT 2 /**< Shift value for SMU_PPUNSINST */
+#define _SMU_NSIEN_PPUNSINST_MASK 0x4UL /**< Bit mask for SMU_PPUNSINST */
+#define _SMU_NSIEN_PPUNSINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIEN */
+#define SMU_NSIEN_PPUNSINST_DEFAULT (_SMU_NSIEN_PPUNSINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_NSIEN */
+
+/* Bit fields for SMU PPUNSPATD0 */
+#define _SMU_PPUNSPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSPATD0 */
+#define _SMU_PPUNSPATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_SCRATCHPAD (0x1UL << 0) /**< SCRATCHPAD Privileged Access */
+#define _SMU_PPUNSPATD0_SCRATCHPAD_SHIFT 0 /**< Shift value for SMU_SCRATCHPAD */
+#define _SMU_PPUNSPATD0_SCRATCHPAD_MASK 0x1UL /**< Bit mask for SMU_SCRATCHPAD */
+#define _SMU_PPUNSPATD0_SCRATCHPAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_SCRATCHPAD_DEFAULT (_SMU_PPUNSPATD0_SCRATCHPAD_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_EMU (0x1UL << 1) /**< EMU Privileged Access */
+#define _SMU_PPUNSPATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */
+#define _SMU_PPUNSPATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */
+#define _SMU_PPUNSPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_EMU_DEFAULT (_SMU_PPUNSPATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_CMU (0x1UL << 2) /**< CMU Privileged Access */
+#define _SMU_PPUNSPATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */
+#define _SMU_PPUNSPATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */
+#define _SMU_PPUNSPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_CMU_DEFAULT (_SMU_PPUNSPATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_HFRCO0 (0x1UL << 3) /**< HFRCO0 Privileged Access */
+#define _SMU_PPUNSPATD0_HFRCO0_SHIFT 3 /**< Shift value for SMU_HFRCO0 */
+#define _SMU_PPUNSPATD0_HFRCO0_MASK 0x8UL /**< Bit mask for SMU_HFRCO0 */
+#define _SMU_PPUNSPATD0_HFRCO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_HFRCO0_DEFAULT (_SMU_PPUNSPATD0_HFRCO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_FSRCO (0x1UL << 4) /**< FSRCO Privileged Access */
+#define _SMU_PPUNSPATD0_FSRCO_SHIFT 4 /**< Shift value for SMU_FSRCO */
+#define _SMU_PPUNSPATD0_FSRCO_MASK 0x10UL /**< Bit mask for SMU_FSRCO */
+#define _SMU_PPUNSPATD0_FSRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_FSRCO_DEFAULT (_SMU_PPUNSPATD0_FSRCO_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_DPLL0 (0x1UL << 5) /**< DPLL0 Privileged Access */
+#define _SMU_PPUNSPATD0_DPLL0_SHIFT 5 /**< Shift value for SMU_DPLL0 */
+#define _SMU_PPUNSPATD0_DPLL0_MASK 0x20UL /**< Bit mask for SMU_DPLL0 */
+#define _SMU_PPUNSPATD0_DPLL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_DPLL0_DEFAULT (_SMU_PPUNSPATD0_DPLL0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_LFXO (0x1UL << 6) /**< LFXO Privileged Access */
+#define _SMU_PPUNSPATD0_LFXO_SHIFT 6 /**< Shift value for SMU_LFXO */
+#define _SMU_PPUNSPATD0_LFXO_MASK 0x40UL /**< Bit mask for SMU_LFXO */
+#define _SMU_PPUNSPATD0_LFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_LFXO_DEFAULT (_SMU_PPUNSPATD0_LFXO_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_LFRCO (0x1UL << 7) /**< LFRCO Privileged Access */
+#define _SMU_PPUNSPATD0_LFRCO_SHIFT 7 /**< Shift value for SMU_LFRCO */
+#define _SMU_PPUNSPATD0_LFRCO_MASK 0x80UL /**< Bit mask for SMU_LFRCO */
+#define _SMU_PPUNSPATD0_LFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_LFRCO_DEFAULT (_SMU_PPUNSPATD0_LFRCO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_ULFRCO (0x1UL << 8) /**< ULFRCO Privileged Access */
+#define _SMU_PPUNSPATD0_ULFRCO_SHIFT 8 /**< Shift value for SMU_ULFRCO */
+#define _SMU_PPUNSPATD0_ULFRCO_MASK 0x100UL /**< Bit mask for SMU_ULFRCO */
+#define _SMU_PPUNSPATD0_ULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_ULFRCO_DEFAULT (_SMU_PPUNSPATD0_ULFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_MSC (0x1UL << 9) /**< MSC Privileged Access */
+#define _SMU_PPUNSPATD0_MSC_SHIFT 9 /**< Shift value for SMU_MSC */
+#define _SMU_PPUNSPATD0_MSC_MASK 0x200UL /**< Bit mask for SMU_MSC */
+#define _SMU_PPUNSPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_MSC_DEFAULT (_SMU_PPUNSPATD0_MSC_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_ICACHE0 (0x1UL << 10) /**< ICACHE0 Privileged Access */
+#define _SMU_PPUNSPATD0_ICACHE0_SHIFT 10 /**< Shift value for SMU_ICACHE0 */
+#define _SMU_PPUNSPATD0_ICACHE0_MASK 0x400UL /**< Bit mask for SMU_ICACHE0 */
+#define _SMU_PPUNSPATD0_ICACHE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_ICACHE0_DEFAULT (_SMU_PPUNSPATD0_ICACHE0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_PRS (0x1UL << 11) /**< PRS Privileged Access */
+#define _SMU_PPUNSPATD0_PRS_SHIFT 11 /**< Shift value for SMU_PRS */
+#define _SMU_PPUNSPATD0_PRS_MASK 0x800UL /**< Bit mask for SMU_PRS */
+#define _SMU_PPUNSPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_PRS_DEFAULT (_SMU_PPUNSPATD0_PRS_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_GPIO (0x1UL << 12) /**< GPIO Privileged Access */
+#define _SMU_PPUNSPATD0_GPIO_SHIFT 12 /**< Shift value for SMU_GPIO */
+#define _SMU_PPUNSPATD0_GPIO_MASK 0x1000UL /**< Bit mask for SMU_GPIO */
+#define _SMU_PPUNSPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_GPIO_DEFAULT (_SMU_PPUNSPATD0_GPIO_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_LDMA (0x1UL << 13) /**< LDMA Privileged Access */
+#define _SMU_PPUNSPATD0_LDMA_SHIFT 13 /**< Shift value for SMU_LDMA */
+#define _SMU_PPUNSPATD0_LDMA_MASK 0x2000UL /**< Bit mask for SMU_LDMA */
+#define _SMU_PPUNSPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_LDMA_DEFAULT (_SMU_PPUNSPATD0_LDMA_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_LDMAXBAR (0x1UL << 14) /**< LDMAXBAR Privileged Access */
+#define _SMU_PPUNSPATD0_LDMAXBAR_SHIFT 14 /**< Shift value for SMU_LDMAXBAR */
+#define _SMU_PPUNSPATD0_LDMAXBAR_MASK 0x4000UL /**< Bit mask for SMU_LDMAXBAR */
+#define _SMU_PPUNSPATD0_LDMAXBAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_LDMAXBAR_DEFAULT (_SMU_PPUNSPATD0_LDMAXBAR_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_TIMER0 (0x1UL << 15) /**< TIMER0 Privileged Access */
+#define _SMU_PPUNSPATD0_TIMER0_SHIFT 15 /**< Shift value for SMU_TIMER0 */
+#define _SMU_PPUNSPATD0_TIMER0_MASK 0x8000UL /**< Bit mask for SMU_TIMER0 */
+#define _SMU_PPUNSPATD0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_TIMER0_DEFAULT (_SMU_PPUNSPATD0_TIMER0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_TIMER1 (0x1UL << 16) /**< TIMER1 Privileged Access */
+#define _SMU_PPUNSPATD0_TIMER1_SHIFT 16 /**< Shift value for SMU_TIMER1 */
+#define _SMU_PPUNSPATD0_TIMER1_MASK 0x10000UL /**< Bit mask for SMU_TIMER1 */
+#define _SMU_PPUNSPATD0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_TIMER1_DEFAULT (_SMU_PPUNSPATD0_TIMER1_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_TIMER2 (0x1UL << 17) /**< TIMER2 Privileged Access */
+#define _SMU_PPUNSPATD0_TIMER2_SHIFT 17 /**< Shift value for SMU_TIMER2 */
+#define _SMU_PPUNSPATD0_TIMER2_MASK 0x20000UL /**< Bit mask for SMU_TIMER2 */
+#define _SMU_PPUNSPATD0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_TIMER2_DEFAULT (_SMU_PPUNSPATD0_TIMER2_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_TIMER3 (0x1UL << 18) /**< TIMER3 Privileged Access */
+#define _SMU_PPUNSPATD0_TIMER3_SHIFT 18 /**< Shift value for SMU_TIMER3 */
+#define _SMU_PPUNSPATD0_TIMER3_MASK 0x40000UL /**< Bit mask for SMU_TIMER3 */
+#define _SMU_PPUNSPATD0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_TIMER3_DEFAULT (_SMU_PPUNSPATD0_TIMER3_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_TIMER4 (0x1UL << 19) /**< TIMER4 Privileged Access */
+#define _SMU_PPUNSPATD0_TIMER4_SHIFT 19 /**< Shift value for SMU_TIMER4 */
+#define _SMU_PPUNSPATD0_TIMER4_MASK 0x80000UL /**< Bit mask for SMU_TIMER4 */
+#define _SMU_PPUNSPATD0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_TIMER4_DEFAULT (_SMU_PPUNSPATD0_TIMER4_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_USART0 (0x1UL << 20) /**< USART0 Privileged Access */
+#define _SMU_PPUNSPATD0_USART0_SHIFT 20 /**< Shift value for SMU_USART0 */
+#define _SMU_PPUNSPATD0_USART0_MASK 0x100000UL /**< Bit mask for SMU_USART0 */
+#define _SMU_PPUNSPATD0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_USART0_DEFAULT (_SMU_PPUNSPATD0_USART0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_BURTC (0x1UL << 21) /**< BURTC Privileged Access */
+#define _SMU_PPUNSPATD0_BURTC_SHIFT 21 /**< Shift value for SMU_BURTC */
+#define _SMU_PPUNSPATD0_BURTC_MASK 0x200000UL /**< Bit mask for SMU_BURTC */
+#define _SMU_PPUNSPATD0_BURTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_BURTC_DEFAULT (_SMU_PPUNSPATD0_BURTC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_I2C1 (0x1UL << 22) /**< I2C1 Privileged Access */
+#define _SMU_PPUNSPATD0_I2C1_SHIFT 22 /**< Shift value for SMU_I2C1 */
+#define _SMU_PPUNSPATD0_I2C1_MASK 0x400000UL /**< Bit mask for SMU_I2C1 */
+#define _SMU_PPUNSPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_I2C1_DEFAULT (_SMU_PPUNSPATD0_I2C1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_CHIPTESTCTRL (0x1UL << 23) /**< CHIPTESTCTRL Privileged Access */
+#define _SMU_PPUNSPATD0_CHIPTESTCTRL_SHIFT 23 /**< Shift value for SMU_CHIPTESTCTRL */
+#define _SMU_PPUNSPATD0_CHIPTESTCTRL_MASK 0x800000UL /**< Bit mask for SMU_CHIPTESTCTRL */
+#define _SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_SYSCFGCFGNS (0x1UL << 24) /**< SYSCFGCFGNS Privileged Access */
+#define _SMU_PPUNSPATD0_SYSCFGCFGNS_SHIFT 24 /**< Shift value for SMU_SYSCFGCFGNS */
+#define _SMU_PPUNSPATD0_SYSCFGCFGNS_MASK 0x1000000UL /**< Bit mask for SMU_SYSCFGCFGNS */
+#define _SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_SYSCFG (0x1UL << 25) /**< SYSCFG Privileged Access */
+#define _SMU_PPUNSPATD0_SYSCFG_SHIFT 25 /**< Shift value for SMU_SYSCFG */
+#define _SMU_PPUNSPATD0_SYSCFG_MASK 0x2000000UL /**< Bit mask for SMU_SYSCFG */
+#define _SMU_PPUNSPATD0_SYSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_SYSCFG_DEFAULT (_SMU_PPUNSPATD0_SYSCFG_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_BURAM (0x1UL << 26) /**< BURAM Privileged Access */
+#define _SMU_PPUNSPATD0_BURAM_SHIFT 26 /**< Shift value for SMU_BURAM */
+#define _SMU_PPUNSPATD0_BURAM_MASK 0x4000000UL /**< Bit mask for SMU_BURAM */
+#define _SMU_PPUNSPATD0_BURAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_BURAM_DEFAULT (_SMU_PPUNSPATD0_BURAM_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_GPCRC (0x1UL << 27) /**< GPCRC Privileged Access */
+#define _SMU_PPUNSPATD0_GPCRC_SHIFT 27 /**< Shift value for SMU_GPCRC */
+#define _SMU_PPUNSPATD0_GPCRC_MASK 0x8000000UL /**< Bit mask for SMU_GPCRC */
+#define _SMU_PPUNSPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_GPCRC_DEFAULT (_SMU_PPUNSPATD0_GPCRC_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_DCDC (0x1UL << 28) /**< DCDC Privileged Access */
+#define _SMU_PPUNSPATD0_DCDC_SHIFT 28 /**< Shift value for SMU_DCDC */
+#define _SMU_PPUNSPATD0_DCDC_MASK 0x10000000UL /**< Bit mask for SMU_DCDC */
+#define _SMU_PPUNSPATD0_DCDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_DCDC_DEFAULT (_SMU_PPUNSPATD0_DCDC_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_HOSTMAILBOX (0x1UL << 29) /**< HOSTMAILBOX Privileged Access */
+#define _SMU_PPUNSPATD0_HOSTMAILBOX_SHIFT 29 /**< Shift value for SMU_HOSTMAILBOX */
+#define _SMU_PPUNSPATD0_HOSTMAILBOX_MASK 0x20000000UL /**< Bit mask for SMU_HOSTMAILBOX */
+#define _SMU_PPUNSPATD0_HOSTMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_HOSTMAILBOX_DEFAULT (_SMU_PPUNSPATD0_HOSTMAILBOX_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_EUSART1 (0x1UL << 30) /**< EUSART1 Privileged Access */
+#define _SMU_PPUNSPATD0_EUSART1_SHIFT 30 /**< Shift value for SMU_EUSART1 */
+#define _SMU_PPUNSPATD0_EUSART1_MASK 0x40000000UL /**< Bit mask for SMU_EUSART1 */
+#define _SMU_PPUNSPATD0_EUSART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_EUSART1_DEFAULT (_SMU_PPUNSPATD0_EUSART1_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_SYSRTC (0x1UL << 31) /**< SYSRTC Privileged Access */
+#define _SMU_PPUNSPATD0_SYSRTC_SHIFT 31 /**< Shift value for SMU_SYSRTC */
+#define _SMU_PPUNSPATD0_SYSRTC_MASK 0x80000000UL /**< Bit mask for SMU_SYSRTC */
+#define _SMU_PPUNSPATD0_SYSRTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */
+#define SMU_PPUNSPATD0_SYSRTC_DEFAULT (_SMU_PPUNSPATD0_SYSRTC_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */
+
+/* Bit fields for SMU PPUNSPATD1 */
+#define _SMU_PPUNSPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSPATD1 */
+#define _SMU_PPUNSPATD1_MASK 0x003FFFFFUL /**< Mask for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_KEYSCAN (0x1UL << 0) /**< KEYSCAN Privileged Access */
+#define _SMU_PPUNSPATD1_KEYSCAN_SHIFT 0 /**< Shift value for SMU_KEYSCAN */
+#define _SMU_PPUNSPATD1_KEYSCAN_MASK 0x1UL /**< Bit mask for SMU_KEYSCAN */
+#define _SMU_PPUNSPATD1_KEYSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_KEYSCAN_DEFAULT (_SMU_PPUNSPATD1_KEYSCAN_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_DMEM (0x1UL << 1) /**< DMEM Privileged Access */
+#define _SMU_PPUNSPATD1_DMEM_SHIFT 1 /**< Shift value for SMU_DMEM */
+#define _SMU_PPUNSPATD1_DMEM_MASK 0x2UL /**< Bit mask for SMU_DMEM */
+#define _SMU_PPUNSPATD1_DMEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_DMEM_DEFAULT (_SMU_PPUNSPATD1_DMEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_RADIOAES (0x1UL << 2) /**< RADIOAES Privileged Access */
+#define _SMU_PPUNSPATD1_RADIOAES_SHIFT 2 /**< Shift value for SMU_RADIOAES */
+#define _SMU_PPUNSPATD1_RADIOAES_MASK 0x4UL /**< Bit mask for SMU_RADIOAES */
+#define _SMU_PPUNSPATD1_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_RADIOAES_DEFAULT (_SMU_PPUNSPATD1_RADIOAES_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_SMU (0x1UL << 3) /**< SMU Privileged Access */
+#define _SMU_PPUNSPATD1_SMU_SHIFT 3 /**< Shift value for SMU_SMU */
+#define _SMU_PPUNSPATD1_SMU_MASK 0x8UL /**< Bit mask for SMU_SMU */
+#define _SMU_PPUNSPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_SMU_DEFAULT (_SMU_PPUNSPATD1_SMU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_SMUCFGNS (0x1UL << 4) /**< SMUCFGNS Privileged Access */
+#define _SMU_PPUNSPATD1_SMUCFGNS_SHIFT 4 /**< Shift value for SMU_SMUCFGNS */
+#define _SMU_PPUNSPATD1_SMUCFGNS_MASK 0x10UL /**< Bit mask for SMU_SMUCFGNS */
+#define _SMU_PPUNSPATD1_SMUCFGNS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_SMUCFGNS_DEFAULT (_SMU_PPUNSPATD1_SMUCFGNS_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_LETIMER0 (0x1UL << 5) /**< LETIMER0 Privileged Access */
+#define _SMU_PPUNSPATD1_LETIMER0_SHIFT 5 /**< Shift value for SMU_LETIMER0 */
+#define _SMU_PPUNSPATD1_LETIMER0_MASK 0x20UL /**< Bit mask for SMU_LETIMER0 */
+#define _SMU_PPUNSPATD1_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_LETIMER0_DEFAULT (_SMU_PPUNSPATD1_LETIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_IADC0 (0x1UL << 6) /**< IADC0 Privileged Access */
+#define _SMU_PPUNSPATD1_IADC0_SHIFT 6 /**< Shift value for SMU_IADC0 */
+#define _SMU_PPUNSPATD1_IADC0_MASK 0x40UL /**< Bit mask for SMU_IADC0 */
+#define _SMU_PPUNSPATD1_IADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_IADC0_DEFAULT (_SMU_PPUNSPATD1_IADC0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_ACMP0 (0x1UL << 7) /**< ACMP0 Privileged Access */
+#define _SMU_PPUNSPATD1_ACMP0_SHIFT 7 /**< Shift value for SMU_ACMP0 */
+#define _SMU_PPUNSPATD1_ACMP0_MASK 0x80UL /**< Bit mask for SMU_ACMP0 */
+#define _SMU_PPUNSPATD1_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_ACMP0_DEFAULT (_SMU_PPUNSPATD1_ACMP0_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_ACMP1 (0x1UL << 8) /**< ACMP1 Privileged Access */
+#define _SMU_PPUNSPATD1_ACMP1_SHIFT 8 /**< Shift value for SMU_ACMP1 */
+#define _SMU_PPUNSPATD1_ACMP1_MASK 0x100UL /**< Bit mask for SMU_ACMP1 */
+#define _SMU_PPUNSPATD1_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_ACMP1_DEFAULT (_SMU_PPUNSPATD1_ACMP1_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_AMUXCP0 (0x1UL << 9) /**< AMUXCP0 Privileged Access */
+#define _SMU_PPUNSPATD1_AMUXCP0_SHIFT 9 /**< Shift value for SMU_AMUXCP0 */
+#define _SMU_PPUNSPATD1_AMUXCP0_MASK 0x200UL /**< Bit mask for SMU_AMUXCP0 */
+#define _SMU_PPUNSPATD1_AMUXCP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_AMUXCP0_DEFAULT (_SMU_PPUNSPATD1_AMUXCP0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_VDAC0 (0x1UL << 10) /**< VDAC0 Privileged Access */
+#define _SMU_PPUNSPATD1_VDAC0_SHIFT 10 /**< Shift value for SMU_VDAC0 */
+#define _SMU_PPUNSPATD1_VDAC0_MASK 0x400UL /**< Bit mask for SMU_VDAC0 */
+#define _SMU_PPUNSPATD1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_VDAC0_DEFAULT (_SMU_PPUNSPATD1_VDAC0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_VDAC1 (0x1UL << 11) /**< VDAC1 Privileged Access */
+#define _SMU_PPUNSPATD1_VDAC1_SHIFT 11 /**< Shift value for SMU_VDAC1 */
+#define _SMU_PPUNSPATD1_VDAC1_MASK 0x800UL /**< Bit mask for SMU_VDAC1 */
+#define _SMU_PPUNSPATD1_VDAC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_VDAC1_DEFAULT (_SMU_PPUNSPATD1_VDAC1_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_PCNT (0x1UL << 12) /**< PCNT Privileged Access */
+#define _SMU_PPUNSPATD1_PCNT_SHIFT 12 /**< Shift value for SMU_PCNT */
+#define _SMU_PPUNSPATD1_PCNT_MASK 0x1000UL /**< Bit mask for SMU_PCNT */
+#define _SMU_PPUNSPATD1_PCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_PCNT_DEFAULT (_SMU_PPUNSPATD1_PCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_HFRCO1 (0x1UL << 13) /**< HFRCO1 Privileged Access */
+#define _SMU_PPUNSPATD1_HFRCO1_SHIFT 13 /**< Shift value for SMU_HFRCO1 */
+#define _SMU_PPUNSPATD1_HFRCO1_MASK 0x2000UL /**< Bit mask for SMU_HFRCO1 */
+#define _SMU_PPUNSPATD1_HFRCO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_HFRCO1_DEFAULT (_SMU_PPUNSPATD1_HFRCO1_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_HFXO0 (0x1UL << 14) /**< HFXO0 Privileged Access */
+#define _SMU_PPUNSPATD1_HFXO0_SHIFT 14 /**< Shift value for SMU_HFXO0 */
+#define _SMU_PPUNSPATD1_HFXO0_MASK 0x4000UL /**< Bit mask for SMU_HFXO0 */
+#define _SMU_PPUNSPATD1_HFXO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_HFXO0_DEFAULT (_SMU_PPUNSPATD1_HFXO0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_I2C0 (0x1UL << 15) /**< I2C0 Privileged Access */
+#define _SMU_PPUNSPATD1_I2C0_SHIFT 15 /**< Shift value for SMU_I2C0 */
+#define _SMU_PPUNSPATD1_I2C0_MASK 0x8000UL /**< Bit mask for SMU_I2C0 */
+#define _SMU_PPUNSPATD1_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_I2C0_DEFAULT (_SMU_PPUNSPATD1_I2C0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_WDOG0 (0x1UL << 16) /**< WDOG0 Privileged Access */
+#define _SMU_PPUNSPATD1_WDOG0_SHIFT 16 /**< Shift value for SMU_WDOG0 */
+#define _SMU_PPUNSPATD1_WDOG0_MASK 0x10000UL /**< Bit mask for SMU_WDOG0 */
+#define _SMU_PPUNSPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_WDOG0_DEFAULT (_SMU_PPUNSPATD1_WDOG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_WDOG1 (0x1UL << 17) /**< WDOG1 Privileged Access */
+#define _SMU_PPUNSPATD1_WDOG1_SHIFT 17 /**< Shift value for SMU_WDOG1 */
+#define _SMU_PPUNSPATD1_WDOG1_MASK 0x20000UL /**< Bit mask for SMU_WDOG1 */
+#define _SMU_PPUNSPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_WDOG1_DEFAULT (_SMU_PPUNSPATD1_WDOG1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_EUSART0 (0x1UL << 18) /**< EUSART0 Privileged Access */
+#define _SMU_PPUNSPATD1_EUSART0_SHIFT 18 /**< Shift value for SMU_EUSART0 */
+#define _SMU_PPUNSPATD1_EUSART0_MASK 0x40000UL /**< Bit mask for SMU_EUSART0 */
+#define _SMU_PPUNSPATD1_EUSART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_EUSART0_DEFAULT (_SMU_PPUNSPATD1_EUSART0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_SEMAILBOX (0x1UL << 19) /**< SEMAILBOX Privileged Access */
+#define _SMU_PPUNSPATD1_SEMAILBOX_SHIFT 19 /**< Shift value for SMU_SEMAILBOX */
+#define _SMU_PPUNSPATD1_SEMAILBOX_MASK 0x80000UL /**< Bit mask for SMU_SEMAILBOX */
+#define _SMU_PPUNSPATD1_SEMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_SEMAILBOX_DEFAULT (_SMU_PPUNSPATD1_SEMAILBOX_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_MVP (0x1UL << 20) /**< MVP Privileged Access */
+#define _SMU_PPUNSPATD1_MVP_SHIFT 20 /**< Shift value for SMU_MVP */
+#define _SMU_PPUNSPATD1_MVP_MASK 0x100000UL /**< Bit mask for SMU_MVP */
+#define _SMU_PPUNSPATD1_MVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_MVP_DEFAULT (_SMU_PPUNSPATD1_MVP_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_AHBRADIO (0x1UL << 21) /**< AHBRADIO Privileged Access */
+#define _SMU_PPUNSPATD1_AHBRADIO_SHIFT 21 /**< Shift value for SMU_AHBRADIO */
+#define _SMU_PPUNSPATD1_AHBRADIO_MASK 0x200000UL /**< Bit mask for SMU_AHBRADIO */
+#define _SMU_PPUNSPATD1_AHBRADIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */
+#define SMU_PPUNSPATD1_AHBRADIO_DEFAULT (_SMU_PPUNSPATD1_AHBRADIO_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */
+
+/* Bit fields for SMU PPUNSFS */
+#define _SMU_PPUNSFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSFS */
+#define _SMU_PPUNSFS_MASK 0x000000FFUL /**< Mask for SMU_PPUNSFS */
+#define _SMU_PPUNSFS_PPUFSPERIPHID_SHIFT 0 /**< Shift value for SMU_PPUFSPERIPHID */
+#define _SMU_PPUNSFS_PPUFSPERIPHID_MASK 0xFFUL /**< Bit mask for SMU_PPUFSPERIPHID */
+#define _SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSFS */
+#define SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT (_SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSFS */
+
+/* Bit fields for SMU BMPUNSPATD0 */
+#define _SMU_BMPUNSPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUNSPATD0 */
+#define _SMU_BMPUNSPATD0_MASK 0x000001FFUL /**< Mask for SMU_BMPUNSPATD0 */
+#define SMU_BMPUNSPATD0_RADIOAES (0x1UL << 0) /**< RADIO AES DMA privileged mode */
+#define _SMU_BMPUNSPATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */
+#define _SMU_BMPUNSPATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */
+#define _SMU_BMPUNSPATD0_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */
+#define SMU_BMPUNSPATD0_RADIOAES_DEFAULT (_SMU_BMPUNSPATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */
+#define SMU_BMPUNSPATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIO subsystem manager privileged mode */
+#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */
+#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */
+#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */
+#define SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */
+#define SMU_BMPUNSPATD0_LDMA (0x1UL << 2) /**< MCU LDMA privileged mode */
+#define _SMU_BMPUNSPATD0_LDMA_SHIFT 2 /**< Shift value for SMU_LDMA */
+#define _SMU_BMPUNSPATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */
+#define _SMU_BMPUNSPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */
+#define SMU_BMPUNSPATD0_LDMA_DEFAULT (_SMU_BMPUNSPATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */
+#define SMU_BMPUNSPATD0_MVPAHBDATA0 (0x1UL << 3) /**< MVPAHBDATA0 privileged mode */
+#define _SMU_BMPUNSPATD0_MVPAHBDATA0_SHIFT 3 /**< Shift value for SMU_MVPAHBDATA0 */
+#define _SMU_BMPUNSPATD0_MVPAHBDATA0_MASK 0x8UL /**< Bit mask for SMU_MVPAHBDATA0 */
+#define _SMU_BMPUNSPATD0_MVPAHBDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */
+#define SMU_BMPUNSPATD0_MVPAHBDATA0_DEFAULT (_SMU_BMPUNSPATD0_MVPAHBDATA0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */
+#define SMU_BMPUNSPATD0_MVPAHBDATA1 (0x1UL << 4) /**< MVPAHBDATA1 privileged mode */
+#define _SMU_BMPUNSPATD0_MVPAHBDATA1_SHIFT 4 /**< Shift value for SMU_MVPAHBDATA1 */
+#define _SMU_BMPUNSPATD0_MVPAHBDATA1_MASK 0x10UL /**< Bit mask for SMU_MVPAHBDATA1 */
+#define _SMU_BMPUNSPATD0_MVPAHBDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */
+#define SMU_BMPUNSPATD0_MVPAHBDATA1_DEFAULT (_SMU_BMPUNSPATD0_MVPAHBDATA1_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */
+#define SMU_BMPUNSPATD0_MVPAHBDATA2 (0x1UL << 5) /**< MVPAHBDATA2 privileged mode */
+#define _SMU_BMPUNSPATD0_MVPAHBDATA2_SHIFT 5 /**< Shift value for SMU_MVPAHBDATA2 */
+#define _SMU_BMPUNSPATD0_MVPAHBDATA2_MASK 0x20UL /**< Bit mask for SMU_MVPAHBDATA2 */
+#define _SMU_BMPUNSPATD0_MVPAHBDATA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */
+#define SMU_BMPUNSPATD0_MVPAHBDATA2_DEFAULT (_SMU_BMPUNSPATD0_MVPAHBDATA2_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */
+#define SMU_BMPUNSPATD0_RFECA0 (0x1UL << 6) /**< RFECA0 privileged mode */
+#define _SMU_BMPUNSPATD0_RFECA0_SHIFT 6 /**< Shift value for SMU_RFECA0 */
+#define _SMU_BMPUNSPATD0_RFECA0_MASK 0x40UL /**< Bit mask for SMU_RFECA0 */
+#define _SMU_BMPUNSPATD0_RFECA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */
+#define SMU_BMPUNSPATD0_RFECA0_DEFAULT (_SMU_BMPUNSPATD0_RFECA0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */
+#define SMU_BMPUNSPATD0_RFECA1 (0x1UL << 7) /**< RFECA1 privileged mode */
+#define _SMU_BMPUNSPATD0_RFECA1_SHIFT 7 /**< Shift value for SMU_RFECA1 */
+#define _SMU_BMPUNSPATD0_RFECA1_MASK 0x80UL /**< Bit mask for SMU_RFECA1 */
+#define _SMU_BMPUNSPATD0_RFECA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */
+#define SMU_BMPUNSPATD0_RFECA1_DEFAULT (_SMU_BMPUNSPATD0_RFECA1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */
+#define SMU_BMPUNSPATD0_SEEXTDMA (0x1UL << 8) /**< SEEXTDMA privileged mode */
+#define _SMU_BMPUNSPATD0_SEEXTDMA_SHIFT 8 /**< Shift value for SMU_SEEXTDMA */
+#define _SMU_BMPUNSPATD0_SEEXTDMA_MASK 0x100UL /**< Bit mask for SMU_SEEXTDMA */
+#define _SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */
+#define SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT (_SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */
+
+/** @} End of group EFR32MG24_SMU_CFGNS_BitFields */
+/** @} End of group EFR32MG24_SMU_CFGNS */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_SMU_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_synth.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_synth.h
new file mode 100644
index 00000000..28d070bc
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_synth.h
@@ -0,0 +1,1124 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 SYNTH register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_SYNTH_H
+#define EFR32MG24_SYNTH_H
+#define SYNTH_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_SYNTH SYNTH
+ * @{
+ * @brief EFR32MG24 SYNTH Register Declaration.
+ *****************************************************************************/
+
+/** SYNTH Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IP Version */
+ __IOM uint32_t EN; /**< Enable peripheral clock to this module */
+ __IM uint32_t STATUS; /**< Frequency Synthesizer Status */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IOM uint32_t CTRL; /**< Frequency Synthesizer Control register */
+ uint32_t RESERVED0[6U]; /**< Reserved for future use */
+ __IOM uint32_t VCDACCTRL; /**< VCDAC Control register */
+ uint32_t RESERVED1[1U]; /**< Reserved for future use */
+ __IOM uint32_t FREQ; /**< Frequency Word */
+ __IOM uint32_t IFFREQ; /**< IF frequency */
+ __IOM uint32_t DIVCTRL; /**< Frequency division control */
+ __IOM uint32_t CHCTRL; /**< Frequency Synthesizer Channel Control */
+ __IOM uint32_t CHSP; /**< Channel spacing */
+ __IOM uint32_t CALOFFSET; /**< Calibration offset */
+ __IOM uint32_t VCOTUNING; /**< VCO Frequency tuning */
+ uint32_t RESERVED2[2U]; /**< Reserved for future use */
+ __IOM uint32_t VCOGAIN; /**< Calibration values for VCO gain */
+ uint32_t RESERVED3[7U]; /**< Reserved for future use */
+ __IOM uint32_t IF; /**< Interrupt Flag Register */
+ uint32_t RESERVED4[2U]; /**< Reserved for future use */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IOM uint32_t LOCNTCTRL; /**< LO Counter Control Register */
+ __IM uint32_t LOCNTSTATUS; /**< LO Counter Status Register */
+ __IM uint32_t LOCNTTARGET; /**< LO Counter Target Value */
+ __IOM uint32_t MMDDENOMINIT; /**< Initial Values for MMD Denom */
+ __IOM uint32_t CHPDACINIT; /**< Initial Value for CHP DAC */
+ __IOM uint32_t LPFCTRL1CAL; /**< LPF control register 1 for CAL mode */
+ __IOM uint32_t LPFCTRL1RX; /**< LPF control register 1 for RX mode */
+ __IOM uint32_t LPFCTRL1TX; /**< LPF control register 1 for TX mode */
+ __IOM uint32_t LPFCTRL2RX; /**< LPF control register 2 for RX mode */
+ __IOM uint32_t LPFCTRL2TX; /**< LPF control register 2 for TX mode */
+ __IOM uint32_t DSMCTRLRX; /**< DSM Control register for RX mode */
+ __IOM uint32_t DSMCTRLTX; /**< DSM Control register for TX mode */
+ __IOM uint32_t SEQIF; /**< SEQ Interrupt Flag Register */
+ __IOM uint32_t SEQIEN; /**< SEQ Interrupt Enable Register */
+ uint32_t RESERVED5[976U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP Version */
+ __IOM uint32_t EN_SET; /**< Enable peripheral clock to this module */
+ __IM uint32_t STATUS_SET; /**< Frequency Synthesizer Status */
+ __IOM uint32_t CMD_SET; /**< Command Register */
+ __IOM uint32_t CTRL_SET; /**< Frequency Synthesizer Control register */
+ uint32_t RESERVED6[6U]; /**< Reserved for future use */
+ __IOM uint32_t VCDACCTRL_SET; /**< VCDAC Control register */
+ uint32_t RESERVED7[1U]; /**< Reserved for future use */
+ __IOM uint32_t FREQ_SET; /**< Frequency Word */
+ __IOM uint32_t IFFREQ_SET; /**< IF frequency */
+ __IOM uint32_t DIVCTRL_SET; /**< Frequency division control */
+ __IOM uint32_t CHCTRL_SET; /**< Frequency Synthesizer Channel Control */
+ __IOM uint32_t CHSP_SET; /**< Channel spacing */
+ __IOM uint32_t CALOFFSET_SET; /**< Calibration offset */
+ __IOM uint32_t VCOTUNING_SET; /**< VCO Frequency tuning */
+ uint32_t RESERVED8[2U]; /**< Reserved for future use */
+ __IOM uint32_t VCOGAIN_SET; /**< Calibration values for VCO gain */
+ uint32_t RESERVED9[7U]; /**< Reserved for future use */
+ __IOM uint32_t IF_SET; /**< Interrupt Flag Register */
+ uint32_t RESERVED10[2U]; /**< Reserved for future use */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
+ __IOM uint32_t LOCNTCTRL_SET; /**< LO Counter Control Register */
+ __IM uint32_t LOCNTSTATUS_SET; /**< LO Counter Status Register */
+ __IM uint32_t LOCNTTARGET_SET; /**< LO Counter Target Value */
+ __IOM uint32_t MMDDENOMINIT_SET; /**< Initial Values for MMD Denom */
+ __IOM uint32_t CHPDACINIT_SET; /**< Initial Value for CHP DAC */
+ __IOM uint32_t LPFCTRL1CAL_SET; /**< LPF control register 1 for CAL mode */
+ __IOM uint32_t LPFCTRL1RX_SET; /**< LPF control register 1 for RX mode */
+ __IOM uint32_t LPFCTRL1TX_SET; /**< LPF control register 1 for TX mode */
+ __IOM uint32_t LPFCTRL2RX_SET; /**< LPF control register 2 for RX mode */
+ __IOM uint32_t LPFCTRL2TX_SET; /**< LPF control register 2 for TX mode */
+ __IOM uint32_t DSMCTRLRX_SET; /**< DSM Control register for RX mode */
+ __IOM uint32_t DSMCTRLTX_SET; /**< DSM Control register for TX mode */
+ __IOM uint32_t SEQIF_SET; /**< SEQ Interrupt Flag Register */
+ __IOM uint32_t SEQIEN_SET; /**< SEQ Interrupt Enable Register */
+ uint32_t RESERVED11[976U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP Version */
+ __IOM uint32_t EN_CLR; /**< Enable peripheral clock to this module */
+ __IM uint32_t STATUS_CLR; /**< Frequency Synthesizer Status */
+ __IOM uint32_t CMD_CLR; /**< Command Register */
+ __IOM uint32_t CTRL_CLR; /**< Frequency Synthesizer Control register */
+ uint32_t RESERVED12[6U]; /**< Reserved for future use */
+ __IOM uint32_t VCDACCTRL_CLR; /**< VCDAC Control register */
+ uint32_t RESERVED13[1U]; /**< Reserved for future use */
+ __IOM uint32_t FREQ_CLR; /**< Frequency Word */
+ __IOM uint32_t IFFREQ_CLR; /**< IF frequency */
+ __IOM uint32_t DIVCTRL_CLR; /**< Frequency division control */
+ __IOM uint32_t CHCTRL_CLR; /**< Frequency Synthesizer Channel Control */
+ __IOM uint32_t CHSP_CLR; /**< Channel spacing */
+ __IOM uint32_t CALOFFSET_CLR; /**< Calibration offset */
+ __IOM uint32_t VCOTUNING_CLR; /**< VCO Frequency tuning */
+ uint32_t RESERVED14[2U]; /**< Reserved for future use */
+ __IOM uint32_t VCOGAIN_CLR; /**< Calibration values for VCO gain */
+ uint32_t RESERVED15[7U]; /**< Reserved for future use */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
+ uint32_t RESERVED16[2U]; /**< Reserved for future use */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
+ __IOM uint32_t LOCNTCTRL_CLR; /**< LO Counter Control Register */
+ __IM uint32_t LOCNTSTATUS_CLR; /**< LO Counter Status Register */
+ __IM uint32_t LOCNTTARGET_CLR; /**< LO Counter Target Value */
+ __IOM uint32_t MMDDENOMINIT_CLR; /**< Initial Values for MMD Denom */
+ __IOM uint32_t CHPDACINIT_CLR; /**< Initial Value for CHP DAC */
+ __IOM uint32_t LPFCTRL1CAL_CLR; /**< LPF control register 1 for CAL mode */
+ __IOM uint32_t LPFCTRL1RX_CLR; /**< LPF control register 1 for RX mode */
+ __IOM uint32_t LPFCTRL1TX_CLR; /**< LPF control register 1 for TX mode */
+ __IOM uint32_t LPFCTRL2RX_CLR; /**< LPF control register 2 for RX mode */
+ __IOM uint32_t LPFCTRL2TX_CLR; /**< LPF control register 2 for TX mode */
+ __IOM uint32_t DSMCTRLRX_CLR; /**< DSM Control register for RX mode */
+ __IOM uint32_t DSMCTRLTX_CLR; /**< DSM Control register for TX mode */
+ __IOM uint32_t SEQIF_CLR; /**< SEQ Interrupt Flag Register */
+ __IOM uint32_t SEQIEN_CLR; /**< SEQ Interrupt Enable Register */
+ uint32_t RESERVED17[976U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP Version */
+ __IOM uint32_t EN_TGL; /**< Enable peripheral clock to this module */
+ __IM uint32_t STATUS_TGL; /**< Frequency Synthesizer Status */
+ __IOM uint32_t CMD_TGL; /**< Command Register */
+ __IOM uint32_t CTRL_TGL; /**< Frequency Synthesizer Control register */
+ uint32_t RESERVED18[6U]; /**< Reserved for future use */
+ __IOM uint32_t VCDACCTRL_TGL; /**< VCDAC Control register */
+ uint32_t RESERVED19[1U]; /**< Reserved for future use */
+ __IOM uint32_t FREQ_TGL; /**< Frequency Word */
+ __IOM uint32_t IFFREQ_TGL; /**< IF frequency */
+ __IOM uint32_t DIVCTRL_TGL; /**< Frequency division control */
+ __IOM uint32_t CHCTRL_TGL; /**< Frequency Synthesizer Channel Control */
+ __IOM uint32_t CHSP_TGL; /**< Channel spacing */
+ __IOM uint32_t CALOFFSET_TGL; /**< Calibration offset */
+ __IOM uint32_t VCOTUNING_TGL; /**< VCO Frequency tuning */
+ uint32_t RESERVED20[2U]; /**< Reserved for future use */
+ __IOM uint32_t VCOGAIN_TGL; /**< Calibration values for VCO gain */
+ uint32_t RESERVED21[7U]; /**< Reserved for future use */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
+ uint32_t RESERVED22[2U]; /**< Reserved for future use */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
+ __IOM uint32_t LOCNTCTRL_TGL; /**< LO Counter Control Register */
+ __IM uint32_t LOCNTSTATUS_TGL; /**< LO Counter Status Register */
+ __IM uint32_t LOCNTTARGET_TGL; /**< LO Counter Target Value */
+ __IOM uint32_t MMDDENOMINIT_TGL; /**< Initial Values for MMD Denom */
+ __IOM uint32_t CHPDACINIT_TGL; /**< Initial Value for CHP DAC */
+ __IOM uint32_t LPFCTRL1CAL_TGL; /**< LPF control register 1 for CAL mode */
+ __IOM uint32_t LPFCTRL1RX_TGL; /**< LPF control register 1 for RX mode */
+ __IOM uint32_t LPFCTRL1TX_TGL; /**< LPF control register 1 for TX mode */
+ __IOM uint32_t LPFCTRL2RX_TGL; /**< LPF control register 2 for RX mode */
+ __IOM uint32_t LPFCTRL2TX_TGL; /**< LPF control register 2 for TX mode */
+ __IOM uint32_t DSMCTRLRX_TGL; /**< DSM Control register for RX mode */
+ __IOM uint32_t DSMCTRLTX_TGL; /**< DSM Control register for TX mode */
+ __IOM uint32_t SEQIF_TGL; /**< SEQ Interrupt Flag Register */
+ __IOM uint32_t SEQIEN_TGL; /**< SEQ Interrupt Enable Register */
+} SYNTH_TypeDef;
+/** @} End of group EFR32MG24_SYNTH */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_SYNTH
+ * @{
+ * @defgroup EFR32MG24_SYNTH_BitFields SYNTH Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for SYNTH IPVERSION */
+#define _SYNTH_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for SYNTH_IPVERSION */
+#define _SYNTH_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYNTH_IPVERSION */
+#define _SYNTH_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SYNTH_IPVERSION */
+#define _SYNTH_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYNTH_IPVERSION */
+#define _SYNTH_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for SYNTH_IPVERSION */
+#define SYNTH_IPVERSION_IPVERSION_DEFAULT (_SYNTH_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_IPVERSION */
+
+/* Bit fields for SYNTH EN */
+#define _SYNTH_EN_RESETVALUE 0x00000000UL /**< Default value for SYNTH_EN */
+#define _SYNTH_EN_MASK 0x00000001UL /**< Mask for SYNTH_EN */
+#define SYNTH_EN_EN (0x1UL << 0) /**< Enable peripheral clock to this module */
+#define _SYNTH_EN_EN_SHIFT 0 /**< Shift value for SYNTH_EN */
+#define _SYNTH_EN_EN_MASK 0x1UL /**< Bit mask for SYNTH_EN */
+#define _SYNTH_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_EN */
+#define SYNTH_EN_EN_DEFAULT (_SYNTH_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_EN */
+
+/* Bit fields for SYNTH STATUS */
+#define _SYNTH_STATUS_RESETVALUE 0x00000000UL /**< Default value for SYNTH_STATUS */
+#define _SYNTH_STATUS_MASK 0x04014707UL /**< Mask for SYNTH_STATUS */
+#define SYNTH_STATUS_INLOCK (0x1UL << 0) /**< RF Synthesizer in Lock */
+#define _SYNTH_STATUS_INLOCK_SHIFT 0 /**< Shift value for SYNTH_INLOCK */
+#define _SYNTH_STATUS_INLOCK_MASK 0x1UL /**< Bit mask for SYNTH_INLOCK */
+#define _SYNTH_STATUS_INLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_STATUS */
+#define SYNTH_STATUS_INLOCK_DEFAULT (_SYNTH_STATUS_INLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_STATUS */
+#define SYNTH_STATUS_IFFREQEN (0x1UL << 1) /**< Synthesizer IF frequency enable status */
+#define _SYNTH_STATUS_IFFREQEN_SHIFT 1 /**< Shift value for SYNTH_IFFREQEN */
+#define _SYNTH_STATUS_IFFREQEN_MASK 0x2UL /**< Bit mask for SYNTH_IFFREQEN */
+#define _SYNTH_STATUS_IFFREQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_STATUS */
+#define SYNTH_STATUS_IFFREQEN_DEFAULT (_SYNTH_STATUS_IFFREQEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYNTH_STATUS */
+
+/* Bit fields for SYNTH CMD */
+#define _SYNTH_CMD_RESETVALUE 0x00000000UL /**< Default value for SYNTH_CMD */
+#define _SYNTH_CMD_MASK 0x0000061FUL /**< Mask for SYNTH_CMD */
+#define SYNTH_CMD_SYNTHSTART (0x1UL << 0) /**< Starts the RF synthesizer */
+#define _SYNTH_CMD_SYNTHSTART_SHIFT 0 /**< Shift value for SYNTH_SYNTHSTART */
+#define _SYNTH_CMD_SYNTHSTART_MASK 0x1UL /**< Bit mask for SYNTH_SYNTHSTART */
+#define _SYNTH_CMD_SYNTHSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_CMD */
+#define SYNTH_CMD_SYNTHSTART_DEFAULT (_SYNTH_CMD_SYNTHSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_CMD */
+#define SYNTH_CMD_SYNTHSTOP (0x1UL << 1) /**< Stops the RF synthesizer */
+#define _SYNTH_CMD_SYNTHSTOP_SHIFT 1 /**< Shift value for SYNTH_SYNTHSTOP */
+#define _SYNTH_CMD_SYNTHSTOP_MASK 0x2UL /**< Bit mask for SYNTH_SYNTHSTOP */
+#define _SYNTH_CMD_SYNTHSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_CMD */
+#define SYNTH_CMD_SYNTHSTOP_DEFAULT (_SYNTH_CMD_SYNTHSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for SYNTH_CMD */
+#define SYNTH_CMD_ENABLEIF (0x1UL << 2) /**< Enable the synthesizer IF frequency */
+#define _SYNTH_CMD_ENABLEIF_SHIFT 2 /**< Shift value for SYNTH_ENABLEIF */
+#define _SYNTH_CMD_ENABLEIF_MASK 0x4UL /**< Bit mask for SYNTH_ENABLEIF */
+#define _SYNTH_CMD_ENABLEIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_CMD */
+#define SYNTH_CMD_ENABLEIF_DEFAULT (_SYNTH_CMD_ENABLEIF_DEFAULT << 2) /**< Shifted mode DEFAULT for SYNTH_CMD */
+#define SYNTH_CMD_DISABLEIF (0x1UL << 3) /**< Disable the synthesizer IF frequency */
+#define _SYNTH_CMD_DISABLEIF_SHIFT 3 /**< Shift value for SYNTH_DISABLEIF */
+#define _SYNTH_CMD_DISABLEIF_MASK 0x8UL /**< Bit mask for SYNTH_DISABLEIF */
+#define _SYNTH_CMD_DISABLEIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_CMD */
+#define SYNTH_CMD_DISABLEIF_DEFAULT (_SYNTH_CMD_DISABLEIF_DEFAULT << 3) /**< Shifted mode DEFAULT for SYNTH_CMD */
+#define SYNTH_CMD_CAPCALSTART (0x1UL << 4) /**< Start VCO capacitor array calibration */
+#define _SYNTH_CMD_CAPCALSTART_SHIFT 4 /**< Shift value for SYNTH_CAPCALSTART */
+#define _SYNTH_CMD_CAPCALSTART_MASK 0x10UL /**< Bit mask for SYNTH_CAPCALSTART */
+#define _SYNTH_CMD_CAPCALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_CMD */
+#define SYNTH_CMD_CAPCALSTART_DEFAULT (_SYNTH_CMD_CAPCALSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for SYNTH_CMD */
+
+/* Bit fields for SYNTH CTRL */
+#define _SYNTH_CTRL_RESETVALUE 0x00000003UL /**< Default value for SYNTH_CTRL */
+#define _SYNTH_CTRL_MASK 0xD9F70007UL /**< Mask for SYNTH_CTRL */
+#define _SYNTH_CTRL_LOCKTHRESHOLD_SHIFT 0 /**< Shift value for SYNTH_LOCKTHRESHOLD */
+#define _SYNTH_CTRL_LOCKTHRESHOLD_MASK 0x7UL /**< Bit mask for SYNTH_LOCKTHRESHOLD */
+#define _SYNTH_CTRL_LOCKTHRESHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for SYNTH_CTRL */
+#define SYNTH_CTRL_LOCKTHRESHOLD_DEFAULT (_SYNTH_CTRL_LOCKTHRESHOLD_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_CTRL */
+#define _SYNTH_CTRL_PRSMUX0_SHIFT 16 /**< Shift value for SYNTH_PRSMUX0 */
+#define _SYNTH_CTRL_PRSMUX0_MASK 0x70000UL /**< Bit mask for SYNTH_PRSMUX0 */
+#define _SYNTH_CTRL_PRSMUX0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_CTRL */
+#define _SYNTH_CTRL_PRSMUX0_DISABLED 0x00000000UL /**< Mode DISABLED for SYNTH_CTRL */
+#define _SYNTH_CTRL_PRSMUX0_INLOCK 0x00000001UL /**< Mode INLOCK for SYNTH_CTRL */
+#define _SYNTH_CTRL_PRSMUX0_LOCK_WINDOW 0x00000002UL /**< Mode LOCK_WINDOW for SYNTH_CTRL */
+#define _SYNTH_CTRL_PRSMUX0_FPLL 0x00000003UL /**< Mode FPLL for SYNTH_CTRL */
+#define _SYNTH_CTRL_PRSMUX0_VCCMP_HI 0x00000004UL /**< Mode VCCMP_HI for SYNTH_CTRL */
+#define _SYNTH_CTRL_PRSMUX0_VCO_AMPLITUDE_OK 0x00000005UL /**< Mode VCO_AMPLITUDE_OK for SYNTH_CTRL */
+#define _SYNTH_CTRL_PRSMUX0_VCO_DET_OUT_D 0x00000006UL /**< Mode VCO_DET_OUT_D for SYNTH_CTRL */
+#define SYNTH_CTRL_PRSMUX0_DEFAULT (_SYNTH_CTRL_PRSMUX0_DEFAULT << 16) /**< Shifted mode DEFAULT for SYNTH_CTRL */
+#define SYNTH_CTRL_PRSMUX0_DISABLED (_SYNTH_CTRL_PRSMUX0_DISABLED << 16) /**< Shifted mode DISABLED for SYNTH_CTRL */
+#define SYNTH_CTRL_PRSMUX0_INLOCK (_SYNTH_CTRL_PRSMUX0_INLOCK << 16) /**< Shifted mode INLOCK for SYNTH_CTRL */
+#define SYNTH_CTRL_PRSMUX0_LOCK_WINDOW (_SYNTH_CTRL_PRSMUX0_LOCK_WINDOW << 16) /**< Shifted mode LOCK_WINDOW for SYNTH_CTRL */
+#define SYNTH_CTRL_PRSMUX0_FPLL (_SYNTH_CTRL_PRSMUX0_FPLL << 16) /**< Shifted mode FPLL for SYNTH_CTRL */
+#define SYNTH_CTRL_PRSMUX0_VCCMP_HI (_SYNTH_CTRL_PRSMUX0_VCCMP_HI << 16) /**< Shifted mode VCCMP_HI for SYNTH_CTRL */
+#define SYNTH_CTRL_PRSMUX0_VCO_AMPLITUDE_OK (_SYNTH_CTRL_PRSMUX0_VCO_AMPLITUDE_OK << 16) /**< Shifted mode VCO_AMPLITUDE_OK for SYNTH_CTRL*/
+#define SYNTH_CTRL_PRSMUX0_VCO_DET_OUT_D (_SYNTH_CTRL_PRSMUX0_VCO_DET_OUT_D << 16) /**< Shifted mode VCO_DET_OUT_D for SYNTH_CTRL */
+#define _SYNTH_CTRL_PRSMUX1_SHIFT 20 /**< Shift value for SYNTH_PRSMUX1 */
+#define _SYNTH_CTRL_PRSMUX1_MASK 0x700000UL /**< Bit mask for SYNTH_PRSMUX1 */
+#define _SYNTH_CTRL_PRSMUX1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_CTRL */
+#define _SYNTH_CTRL_PRSMUX1_DISABLED 0x00000000UL /**< Mode DISABLED for SYNTH_CTRL */
+#define _SYNTH_CTRL_PRSMUX1_AUXINLOCK 0x00000001UL /**< Mode AUXINLOCK for SYNTH_CTRL */
+#define _SYNTH_CTRL_PRSMUX1_REF_IS_LEADING 0x00000002UL /**< Mode REF_IS_LEADING for SYNTH_CTRL */
+#define _SYNTH_CTRL_PRSMUX1_FPLL 0x00000003UL /**< Mode FPLL for SYNTH_CTRL */
+#define _SYNTH_CTRL_PRSMUX1_VCCMP_LOW 0x00000004UL /**< Mode VCCMP_LOW for SYNTH_CTRL */
+#define _SYNTH_CTRL_PRSMUX1_MMD_PRESCALER_RESET_N 0x00000005UL /**< Mode MMD_PRESCALER_RESET_N for SYNTH_CTRL */
+#define _SYNTH_CTRL_PRSMUX1_CLK_SYNTH_DIV2 0x00000006UL /**< Mode CLK_SYNTH_DIV2 for SYNTH_CTRL */
+#define SYNTH_CTRL_PRSMUX1_DEFAULT (_SYNTH_CTRL_PRSMUX1_DEFAULT << 20) /**< Shifted mode DEFAULT for SYNTH_CTRL */
+#define SYNTH_CTRL_PRSMUX1_DISABLED (_SYNTH_CTRL_PRSMUX1_DISABLED << 20) /**< Shifted mode DISABLED for SYNTH_CTRL */
+#define SYNTH_CTRL_PRSMUX1_AUXINLOCK (_SYNTH_CTRL_PRSMUX1_AUXINLOCK << 20) /**< Shifted mode AUXINLOCK for SYNTH_CTRL */
+#define SYNTH_CTRL_PRSMUX1_REF_IS_LEADING (_SYNTH_CTRL_PRSMUX1_REF_IS_LEADING << 20) /**< Shifted mode REF_IS_LEADING for SYNTH_CTRL */
+#define SYNTH_CTRL_PRSMUX1_FPLL (_SYNTH_CTRL_PRSMUX1_FPLL << 20) /**< Shifted mode FPLL for SYNTH_CTRL */
+#define SYNTH_CTRL_PRSMUX1_VCCMP_LOW (_SYNTH_CTRL_PRSMUX1_VCCMP_LOW << 20) /**< Shifted mode VCCMP_LOW for SYNTH_CTRL */
+#define SYNTH_CTRL_PRSMUX1_MMD_PRESCALER_RESET_N (_SYNTH_CTRL_PRSMUX1_MMD_PRESCALER_RESET_N << 20) /**< Shifted mode MMD_PRESCALER_RESET_N for SYNTH_CTRL*/
+#define SYNTH_CTRL_PRSMUX1_CLK_SYNTH_DIV2 (_SYNTH_CTRL_PRSMUX1_CLK_SYNTH_DIV2 << 20) /**< Shifted mode CLK_SYNTH_DIV2 for SYNTH_CTRL */
+#define SYNTH_CTRL_DISCLKSYNTH (0x1UL << 23) /**< Disable clk_synth */
+#define _SYNTH_CTRL_DISCLKSYNTH_SHIFT 23 /**< Shift value for SYNTH_DISCLKSYNTH */
+#define _SYNTH_CTRL_DISCLKSYNTH_MASK 0x800000UL /**< Bit mask for SYNTH_DISCLKSYNTH */
+#define _SYNTH_CTRL_DISCLKSYNTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_CTRL */
+#define _SYNTH_CTRL_DISCLKSYNTH_ENABLE 0x00000000UL /**< Mode ENABLE for SYNTH_CTRL */
+#define _SYNTH_CTRL_DISCLKSYNTH_DISABLE 0x00000001UL /**< Mode DISABLE for SYNTH_CTRL */
+#define SYNTH_CTRL_DISCLKSYNTH_DEFAULT (_SYNTH_CTRL_DISCLKSYNTH_DEFAULT << 23) /**< Shifted mode DEFAULT for SYNTH_CTRL */
+#define SYNTH_CTRL_DISCLKSYNTH_ENABLE (_SYNTH_CTRL_DISCLKSYNTH_ENABLE << 23) /**< Shifted mode ENABLE for SYNTH_CTRL */
+#define SYNTH_CTRL_DISCLKSYNTH_DISABLE (_SYNTH_CTRL_DISCLKSYNTH_DISABLE << 23) /**< Shifted mode DISABLE for SYNTH_CTRL */
+#define SYNTH_CTRL_INVCLKSYNTH (0x1UL << 24) /**< Invert clk_synth */
+#define _SYNTH_CTRL_INVCLKSYNTH_SHIFT 24 /**< Shift value for SYNTH_INVCLKSYNTH */
+#define _SYNTH_CTRL_INVCLKSYNTH_MASK 0x1000000UL /**< Bit mask for SYNTH_INVCLKSYNTH */
+#define _SYNTH_CTRL_INVCLKSYNTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_CTRL */
+#define _SYNTH_CTRL_INVCLKSYNTH_NO 0x00000000UL /**< Mode NO for SYNTH_CTRL */
+#define _SYNTH_CTRL_INVCLKSYNTH_YES 0x00000001UL /**< Mode YES for SYNTH_CTRL */
+#define SYNTH_CTRL_INVCLKSYNTH_DEFAULT (_SYNTH_CTRL_INVCLKSYNTH_DEFAULT << 24) /**< Shifted mode DEFAULT for SYNTH_CTRL */
+#define SYNTH_CTRL_INVCLKSYNTH_NO (_SYNTH_CTRL_INVCLKSYNTH_NO << 24) /**< Shifted mode NO for SYNTH_CTRL */
+#define SYNTH_CTRL_INVCLKSYNTH_YES (_SYNTH_CTRL_INVCLKSYNTH_YES << 24) /**< Shifted mode YES for SYNTH_CTRL */
+#define SYNTH_CTRL_MMDRSTNOVERRIDEEN (0x1UL << 30) /**< Enable MMD reset override */
+#define _SYNTH_CTRL_MMDRSTNOVERRIDEEN_SHIFT 30 /**< Shift value for SYNTH_MMDRSTNOVERRIDEEN */
+#define _SYNTH_CTRL_MMDRSTNOVERRIDEEN_MASK 0x40000000UL /**< Bit mask for SYNTH_MMDRSTNOVERRIDEEN */
+#define _SYNTH_CTRL_MMDRSTNOVERRIDEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_CTRL */
+#define _SYNTH_CTRL_MMDRSTNOVERRIDEEN_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_CTRL */
+#define _SYNTH_CTRL_MMDRSTNOVERRIDEEN_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_CTRL */
+#define SYNTH_CTRL_MMDRSTNOVERRIDEEN_DEFAULT (_SYNTH_CTRL_MMDRSTNOVERRIDEEN_DEFAULT << 30) /**< Shifted mode DEFAULT for SYNTH_CTRL */
+#define SYNTH_CTRL_MMDRSTNOVERRIDEEN_DISABLE (_SYNTH_CTRL_MMDRSTNOVERRIDEEN_DISABLE << 30) /**< Shifted mode DISABLE for SYNTH_CTRL */
+#define SYNTH_CTRL_MMDRSTNOVERRIDEEN_ENABLE (_SYNTH_CTRL_MMDRSTNOVERRIDEEN_ENABLE << 30) /**< Shifted mode ENABLE for SYNTH_CTRL */
+#define SYNTH_CTRL_MMDMANRSTN (0x1UL << 31) /**< Manual MMD reset */
+#define _SYNTH_CTRL_MMDMANRSTN_SHIFT 31 /**< Shift value for SYNTH_MMDMANRSTN */
+#define _SYNTH_CTRL_MMDMANRSTN_MASK 0x80000000UL /**< Bit mask for SYNTH_MMDMANRSTN */
+#define _SYNTH_CTRL_MMDMANRSTN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_CTRL */
+#define _SYNTH_CTRL_MMDMANRSTN_RESET 0x00000000UL /**< Mode RESET for SYNTH_CTRL */
+#define _SYNTH_CTRL_MMDMANRSTN_NORESET 0x00000001UL /**< Mode NORESET for SYNTH_CTRL */
+#define SYNTH_CTRL_MMDMANRSTN_DEFAULT (_SYNTH_CTRL_MMDMANRSTN_DEFAULT << 31) /**< Shifted mode DEFAULT for SYNTH_CTRL */
+#define SYNTH_CTRL_MMDMANRSTN_RESET (_SYNTH_CTRL_MMDMANRSTN_RESET << 31) /**< Shifted mode RESET for SYNTH_CTRL */
+#define SYNTH_CTRL_MMDMANRSTN_NORESET (_SYNTH_CTRL_MMDMANRSTN_NORESET << 31) /**< Shifted mode NORESET for SYNTH_CTRL */
+
+/* Bit fields for SYNTH VCDACCTRL */
+#define _SYNTH_VCDACCTRL_RESETVALUE 0x00000020UL /**< Default value for SYNTH_VCDACCTRL */
+#define _SYNTH_VCDACCTRL_MASK 0x000001FFUL /**< Mask for SYNTH_VCDACCTRL */
+#define _SYNTH_VCDACCTRL_VCDACVAL_SHIFT 0 /**< Shift value for SYNTH_VCDACVAL */
+#define _SYNTH_VCDACCTRL_VCDACVAL_MASK 0x3FUL /**< Bit mask for SYNTH_VCDACVAL */
+#define _SYNTH_VCDACCTRL_VCDACVAL_DEFAULT 0x00000020UL /**< Mode DEFAULT for SYNTH_VCDACCTRL */
+#define SYNTH_VCDACCTRL_VCDACVAL_DEFAULT (_SYNTH_VCDACCTRL_VCDACVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_VCDACCTRL */
+#define SYNTH_VCDACCTRL_VCDACEN (0x1UL << 6) /**< Enable VCDAC */
+#define _SYNTH_VCDACCTRL_VCDACEN_SHIFT 6 /**< Shift value for SYNTH_VCDACEN */
+#define _SYNTH_VCDACCTRL_VCDACEN_MASK 0x40UL /**< Bit mask for SYNTH_VCDACEN */
+#define _SYNTH_VCDACCTRL_VCDACEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_VCDACCTRL */
+#define _SYNTH_VCDACCTRL_VCDACEN_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_VCDACCTRL */
+#define _SYNTH_VCDACCTRL_VCDACEN_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_VCDACCTRL */
+#define SYNTH_VCDACCTRL_VCDACEN_DEFAULT (_SYNTH_VCDACCTRL_VCDACEN_DEFAULT << 6) /**< Shifted mode DEFAULT for SYNTH_VCDACCTRL */
+#define SYNTH_VCDACCTRL_VCDACEN_DISABLE (_SYNTH_VCDACCTRL_VCDACEN_DISABLE << 6) /**< Shifted mode DISABLE for SYNTH_VCDACCTRL */
+#define SYNTH_VCDACCTRL_VCDACEN_ENABLE (_SYNTH_VCDACCTRL_VCDACEN_ENABLE << 6) /**< Shifted mode ENABLE for SYNTH_VCDACCTRL */
+#define SYNTH_VCDACCTRL_LPFEN (0x1UL << 7) /**< LPF Enable Control */
+#define _SYNTH_VCDACCTRL_LPFEN_SHIFT 7 /**< Shift value for SYNTH_LPFEN */
+#define _SYNTH_VCDACCTRL_LPFEN_MASK 0x80UL /**< Bit mask for SYNTH_LPFEN */
+#define _SYNTH_VCDACCTRL_LPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_VCDACCTRL */
+#define _SYNTH_VCDACCTRL_LPFEN_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_VCDACCTRL */
+#define _SYNTH_VCDACCTRL_LPFEN_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_VCDACCTRL */
+#define SYNTH_VCDACCTRL_LPFEN_DEFAULT (_SYNTH_VCDACCTRL_LPFEN_DEFAULT << 7) /**< Shifted mode DEFAULT for SYNTH_VCDACCTRL */
+#define SYNTH_VCDACCTRL_LPFEN_DISABLE (_SYNTH_VCDACCTRL_LPFEN_DISABLE << 7) /**< Shifted mode DISABLE for SYNTH_VCDACCTRL */
+#define SYNTH_VCDACCTRL_LPFEN_ENABLE (_SYNTH_VCDACCTRL_LPFEN_ENABLE << 7) /**< Shifted mode ENABLE for SYNTH_VCDACCTRL */
+#define SYNTH_VCDACCTRL_LPFQSEN (0x1UL << 8) /**< LPF Quickstart Control */
+#define _SYNTH_VCDACCTRL_LPFQSEN_SHIFT 8 /**< Shift value for SYNTH_LPFQSEN */
+#define _SYNTH_VCDACCTRL_LPFQSEN_MASK 0x100UL /**< Bit mask for SYNTH_LPFQSEN */
+#define _SYNTH_VCDACCTRL_LPFQSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_VCDACCTRL */
+#define _SYNTH_VCDACCTRL_LPFQSEN_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_VCDACCTRL */
+#define _SYNTH_VCDACCTRL_LPFQSEN_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_VCDACCTRL */
+#define SYNTH_VCDACCTRL_LPFQSEN_DEFAULT (_SYNTH_VCDACCTRL_LPFQSEN_DEFAULT << 8) /**< Shifted mode DEFAULT for SYNTH_VCDACCTRL */
+#define SYNTH_VCDACCTRL_LPFQSEN_DISABLE (_SYNTH_VCDACCTRL_LPFQSEN_DISABLE << 8) /**< Shifted mode DISABLE for SYNTH_VCDACCTRL */
+#define SYNTH_VCDACCTRL_LPFQSEN_ENABLE (_SYNTH_VCDACCTRL_LPFQSEN_ENABLE << 8) /**< Shifted mode ENABLE for SYNTH_VCDACCTRL */
+
+/* Bit fields for SYNTH FREQ */
+#define _SYNTH_FREQ_RESETVALUE 0x00000000UL /**< Default value for SYNTH_FREQ */
+#define _SYNTH_FREQ_MASK 0x0FFFFFFFUL /**< Mask for SYNTH_FREQ */
+#define _SYNTH_FREQ_FREQ_SHIFT 0 /**< Shift value for SYNTH_FREQ */
+#define _SYNTH_FREQ_FREQ_MASK 0xFFFFFFFUL /**< Bit mask for SYNTH_FREQ */
+#define _SYNTH_FREQ_FREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_FREQ */
+#define SYNTH_FREQ_FREQ_DEFAULT (_SYNTH_FREQ_FREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_FREQ */
+
+/* Bit fields for SYNTH IFFREQ */
+#define _SYNTH_IFFREQ_RESETVALUE 0x00000000UL /**< Default value for SYNTH_IFFREQ */
+#define _SYNTH_IFFREQ_MASK 0x001FFFFFUL /**< Mask for SYNTH_IFFREQ */
+#define _SYNTH_IFFREQ_IFFREQ_SHIFT 0 /**< Shift value for SYNTH_IFFREQ */
+#define _SYNTH_IFFREQ_IFFREQ_MASK 0xFFFFFUL /**< Bit mask for SYNTH_IFFREQ */
+#define _SYNTH_IFFREQ_IFFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_IFFREQ */
+#define SYNTH_IFFREQ_IFFREQ_DEFAULT (_SYNTH_IFFREQ_IFFREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_IFFREQ */
+#define SYNTH_IFFREQ_LOSIDE (0x1UL << 20) /**< Configure LO in receive */
+#define _SYNTH_IFFREQ_LOSIDE_SHIFT 20 /**< Shift value for SYNTH_LOSIDE */
+#define _SYNTH_IFFREQ_LOSIDE_MASK 0x100000UL /**< Bit mask for SYNTH_LOSIDE */
+#define _SYNTH_IFFREQ_LOSIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_IFFREQ */
+#define _SYNTH_IFFREQ_LOSIDE_LOW 0x00000000UL /**< Mode LOW for SYNTH_IFFREQ */
+#define _SYNTH_IFFREQ_LOSIDE_HIGH 0x00000001UL /**< Mode HIGH for SYNTH_IFFREQ */
+#define SYNTH_IFFREQ_LOSIDE_DEFAULT (_SYNTH_IFFREQ_LOSIDE_DEFAULT << 20) /**< Shifted mode DEFAULT for SYNTH_IFFREQ */
+#define SYNTH_IFFREQ_LOSIDE_LOW (_SYNTH_IFFREQ_LOSIDE_LOW << 20) /**< Shifted mode LOW for SYNTH_IFFREQ */
+#define SYNTH_IFFREQ_LOSIDE_HIGH (_SYNTH_IFFREQ_LOSIDE_HIGH << 20) /**< Shifted mode HIGH for SYNTH_IFFREQ */
+
+/* Bit fields for SYNTH DIVCTRL */
+#define _SYNTH_DIVCTRL_RESETVALUE 0x00000001UL /**< Default value for SYNTH_DIVCTRL */
+#define _SYNTH_DIVCTRL_MASK 0x000001FFUL /**< Mask for SYNTH_DIVCTRL */
+#define _SYNTH_DIVCTRL_LODIVFREQCTRL_SHIFT 0 /**< Shift value for SYNTH_LODIVFREQCTRL */
+#define _SYNTH_DIVCTRL_LODIVFREQCTRL_MASK 0x1FFUL /**< Bit mask for SYNTH_LODIVFREQCTRL */
+#define _SYNTH_DIVCTRL_LODIVFREQCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYNTH_DIVCTRL */
+#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV1 0x00000001UL /**< Mode LODIV1 for SYNTH_DIVCTRL */
+#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV2 0x00000002UL /**< Mode LODIV2 for SYNTH_DIVCTRL */
+#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV3 0x00000003UL /**< Mode LODIV3 for SYNTH_DIVCTRL */
+#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV4 0x00000004UL /**< Mode LODIV4 for SYNTH_DIVCTRL */
+#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV5 0x00000005UL /**< Mode LODIV5 for SYNTH_DIVCTRL */
+#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV7 0x00000007UL /**< Mode LODIV7 for SYNTH_DIVCTRL */
+#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV6 0x00000013UL /**< Mode LODIV6 for SYNTH_DIVCTRL */
+#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV8 0x00000014UL /**< Mode LODIV8 for SYNTH_DIVCTRL */
+#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV10 0x00000015UL /**< Mode LODIV10 for SYNTH_DIVCTRL */
+#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV14 0x00000017UL /**< Mode LODIV14 for SYNTH_DIVCTRL */
+#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV9 0x0000001BUL /**< Mode LODIV9 for SYNTH_DIVCTRL */
+#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV12 0x0000001CUL /**< Mode LODIV12 for SYNTH_DIVCTRL */
+#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV15 0x0000001DUL /**< Mode LODIV15 for SYNTH_DIVCTRL */
+#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV16 0x00000024UL /**< Mode LODIV16 for SYNTH_DIVCTRL */
+#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV20 0x00000025UL /**< Mode LODIV20 for SYNTH_DIVCTRL */
+#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV18 0x0000009BUL /**< Mode LODIV18 for SYNTH_DIVCTRL */
+#define _SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV24 0x0000009CUL /**< Mode LODIV24 for SYNTH_DIVCTRL */
+#define SYNTH_DIVCTRL_LODIVFREQCTRL_DEFAULT (_SYNTH_DIVCTRL_LODIVFREQCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_DIVCTRL */
+#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV1 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV1 << 0) /**< Shifted mode LODIV1 for SYNTH_DIVCTRL */
+#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV2 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV2 << 0) /**< Shifted mode LODIV2 for SYNTH_DIVCTRL */
+#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV3 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV3 << 0) /**< Shifted mode LODIV3 for SYNTH_DIVCTRL */
+#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV4 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV4 << 0) /**< Shifted mode LODIV4 for SYNTH_DIVCTRL */
+#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV5 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV5 << 0) /**< Shifted mode LODIV5 for SYNTH_DIVCTRL */
+#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV7 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV7 << 0) /**< Shifted mode LODIV7 for SYNTH_DIVCTRL */
+#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV6 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV6 << 0) /**< Shifted mode LODIV6 for SYNTH_DIVCTRL */
+#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV8 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV8 << 0) /**< Shifted mode LODIV8 for SYNTH_DIVCTRL */
+#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV10 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV10 << 0) /**< Shifted mode LODIV10 for SYNTH_DIVCTRL */
+#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV14 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV14 << 0) /**< Shifted mode LODIV14 for SYNTH_DIVCTRL */
+#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV9 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV9 << 0) /**< Shifted mode LODIV9 for SYNTH_DIVCTRL */
+#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV12 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV12 << 0) /**< Shifted mode LODIV12 for SYNTH_DIVCTRL */
+#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV15 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV15 << 0) /**< Shifted mode LODIV15 for SYNTH_DIVCTRL */
+#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV16 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV16 << 0) /**< Shifted mode LODIV16 for SYNTH_DIVCTRL */
+#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV20 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV20 << 0) /**< Shifted mode LODIV20 for SYNTH_DIVCTRL */
+#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV18 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV18 << 0) /**< Shifted mode LODIV18 for SYNTH_DIVCTRL */
+#define SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV24 (_SYNTH_DIVCTRL_LODIVFREQCTRL_LODIV24 << 0) /**< Shifted mode LODIV24 for SYNTH_DIVCTRL */
+
+/* Bit fields for SYNTH CHCTRL */
+#define _SYNTH_CHCTRL_RESETVALUE 0x00000000UL /**< Default value for SYNTH_CHCTRL */
+#define _SYNTH_CHCTRL_MASK 0x0000003FUL /**< Mask for SYNTH_CHCTRL */
+#define _SYNTH_CHCTRL_CHNO_SHIFT 0 /**< Shift value for SYNTH_CHNO */
+#define _SYNTH_CHCTRL_CHNO_MASK 0x3FUL /**< Bit mask for SYNTH_CHNO */
+#define _SYNTH_CHCTRL_CHNO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_CHCTRL */
+#define SYNTH_CHCTRL_CHNO_DEFAULT (_SYNTH_CHCTRL_CHNO_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_CHCTRL */
+
+/* Bit fields for SYNTH CHSP */
+#define _SYNTH_CHSP_RESETVALUE 0x00000000UL /**< Default value for SYNTH_CHSP */
+#define _SYNTH_CHSP_MASK 0x0003FFFFUL /**< Mask for SYNTH_CHSP */
+#define _SYNTH_CHSP_CHSP_SHIFT 0 /**< Shift value for SYNTH_CHSP */
+#define _SYNTH_CHSP_CHSP_MASK 0x3FFFFUL /**< Bit mask for SYNTH_CHSP */
+#define _SYNTH_CHSP_CHSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_CHSP */
+#define SYNTH_CHSP_CHSP_DEFAULT (_SYNTH_CHSP_CHSP_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_CHSP */
+
+/* Bit fields for SYNTH CALOFFSET */
+#define _SYNTH_CALOFFSET_RESETVALUE 0x00000000UL /**< Default value for SYNTH_CALOFFSET */
+#define _SYNTH_CALOFFSET_MASK 0x00007FFFUL /**< Mask for SYNTH_CALOFFSET */
+#define _SYNTH_CALOFFSET_CALOFFSET_SHIFT 0 /**< Shift value for SYNTH_CALOFFSET */
+#define _SYNTH_CALOFFSET_CALOFFSET_MASK 0x7FFFUL /**< Bit mask for SYNTH_CALOFFSET */
+#define _SYNTH_CALOFFSET_CALOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_CALOFFSET */
+#define SYNTH_CALOFFSET_CALOFFSET_DEFAULT (_SYNTH_CALOFFSET_CALOFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_CALOFFSET */
+
+/* Bit fields for SYNTH VCOTUNING */
+#define _SYNTH_VCOTUNING_RESETVALUE 0x00008400UL /**< Default value for SYNTH_VCOTUNING */
+#define _SYNTH_VCOTUNING_MASK 0x0000FFFFUL /**< Mask for SYNTH_VCOTUNING */
+#define _SYNTH_VCOTUNING_VCOTUNING_SHIFT 0 /**< Shift value for SYNTH_VCOTUNING */
+#define _SYNTH_VCOTUNING_VCOTUNING_MASK 0x7FFUL /**< Bit mask for SYNTH_VCOTUNING */
+#define _SYNTH_VCOTUNING_VCOTUNING_DEFAULT 0x00000400UL /**< Mode DEFAULT for SYNTH_VCOTUNING */
+#define SYNTH_VCOTUNING_VCOTUNING_DEFAULT (_SYNTH_VCOTUNING_VCOTUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_VCOTUNING */
+#define _SYNTH_VCOTUNING_VCAPSEL_SHIFT 11 /**< Shift value for SYNTH_VCAPSEL */
+#define _SYNTH_VCOTUNING_VCAPSEL_MASK 0xF800UL /**< Bit mask for SYNTH_VCAPSEL */
+#define _SYNTH_VCOTUNING_VCAPSEL_DEFAULT 0x00000010UL /**< Mode DEFAULT for SYNTH_VCOTUNING */
+#define SYNTH_VCOTUNING_VCAPSEL_DEFAULT (_SYNTH_VCOTUNING_VCAPSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for SYNTH_VCOTUNING */
+
+/* Bit fields for SYNTH VCOGAIN */
+#define _SYNTH_VCOGAIN_RESETVALUE 0x00000077UL /**< Default value for SYNTH_VCOGAIN */
+#define _SYNTH_VCOGAIN_MASK 0x000000FFUL /**< Mask for SYNTH_VCOGAIN */
+#define _SYNTH_VCOGAIN_VCOKVCOARSE_SHIFT 0 /**< Shift value for SYNTH_VCOKVCOARSE */
+#define _SYNTH_VCOGAIN_VCOKVCOARSE_MASK 0xFUL /**< Bit mask for SYNTH_VCOKVCOARSE */
+#define _SYNTH_VCOGAIN_VCOKVCOARSE_DEFAULT 0x00000007UL /**< Mode DEFAULT for SYNTH_VCOGAIN */
+#define SYNTH_VCOGAIN_VCOKVCOARSE_DEFAULT (_SYNTH_VCOGAIN_VCOKVCOARSE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_VCOGAIN */
+#define _SYNTH_VCOGAIN_VCOKVFINE_SHIFT 4 /**< Shift value for SYNTH_VCOKVFINE */
+#define _SYNTH_VCOGAIN_VCOKVFINE_MASK 0xF0UL /**< Bit mask for SYNTH_VCOKVFINE */
+#define _SYNTH_VCOGAIN_VCOKVFINE_DEFAULT 0x00000007UL /**< Mode DEFAULT for SYNTH_VCOGAIN */
+#define SYNTH_VCOGAIN_VCOKVFINE_DEFAULT (_SYNTH_VCOGAIN_VCOKVFINE_DEFAULT << 4) /**< Shifted mode DEFAULT for SYNTH_VCOGAIN */
+
+/* Bit fields for SYNTH IF */
+#define _SYNTH_IF_RESETVALUE 0x00000000UL /**< Default value for SYNTH_IF */
+#define _SYNTH_IF_MASK 0x00000237UL /**< Mask for SYNTH_IF */
+#define SYNTH_IF_LOCKED (0x1UL << 0) /**< Synthesizer locked Interrupt Flag */
+#define _SYNTH_IF_LOCKED_SHIFT 0 /**< Shift value for SYNTH_LOCKED */
+#define _SYNTH_IF_LOCKED_MASK 0x1UL /**< Bit mask for SYNTH_LOCKED */
+#define _SYNTH_IF_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_IF */
+#define SYNTH_IF_LOCKED_DEFAULT (_SYNTH_IF_LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_IF */
+#define SYNTH_IF_UNLOCKED (0x1UL << 1) /**< Synthesizer unlocked Interrupt Flag */
+#define _SYNTH_IF_UNLOCKED_SHIFT 1 /**< Shift value for SYNTH_UNLOCKED */
+#define _SYNTH_IF_UNLOCKED_MASK 0x2UL /**< Bit mask for SYNTH_UNLOCKED */
+#define _SYNTH_IF_UNLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_IF */
+#define SYNTH_IF_UNLOCKED_DEFAULT (_SYNTH_IF_UNLOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for SYNTH_IF */
+#define SYNTH_IF_SYRDY (0x1UL << 2) /**< Synthesizer ready Interrupt Flag */
+#define _SYNTH_IF_SYRDY_SHIFT 2 /**< Shift value for SYNTH_SYRDY */
+#define _SYNTH_IF_SYRDY_MASK 0x4UL /**< Bit mask for SYNTH_SYRDY */
+#define _SYNTH_IF_SYRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_IF */
+#define SYNTH_IF_SYRDY_DEFAULT (_SYNTH_IF_SYRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for SYNTH_IF */
+#define SYNTH_IF_VCOHIGH (0x1UL << 4) /**< VCO high voltage Interrupt Flag */
+#define _SYNTH_IF_VCOHIGH_SHIFT 4 /**< Shift value for SYNTH_VCOHIGH */
+#define _SYNTH_IF_VCOHIGH_MASK 0x10UL /**< Bit mask for SYNTH_VCOHIGH */
+#define _SYNTH_IF_VCOHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_IF */
+#define SYNTH_IF_VCOHIGH_DEFAULT (_SYNTH_IF_VCOHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for SYNTH_IF */
+#define SYNTH_IF_VCOLOW (0x1UL << 5) /**< VCO low voltage Interrupt Flag */
+#define _SYNTH_IF_VCOLOW_SHIFT 5 /**< Shift value for SYNTH_VCOLOW */
+#define _SYNTH_IF_VCOLOW_MASK 0x20UL /**< Bit mask for SYNTH_VCOLOW */
+#define _SYNTH_IF_VCOLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_IF */
+#define SYNTH_IF_VCOLOW_DEFAULT (_SYNTH_IF_VCOLOW_DEFAULT << 5) /**< Shifted mode DEFAULT for SYNTH_IF */
+#define SYNTH_IF_LOCNTDONE (0x1UL << 9) /**< LOCNT measurement done Interrupt Flag */
+#define _SYNTH_IF_LOCNTDONE_SHIFT 9 /**< Shift value for SYNTH_LOCNTDONE */
+#define _SYNTH_IF_LOCNTDONE_MASK 0x200UL /**< Bit mask for SYNTH_LOCNTDONE */
+#define _SYNTH_IF_LOCNTDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_IF */
+#define SYNTH_IF_LOCNTDONE_DEFAULT (_SYNTH_IF_LOCNTDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for SYNTH_IF */
+
+/* Bit fields for SYNTH IEN */
+#define _SYNTH_IEN_RESETVALUE 0x00000000UL /**< Default value for SYNTH_IEN */
+#define _SYNTH_IEN_MASK 0x00000237UL /**< Mask for SYNTH_IEN */
+#define SYNTH_IEN_LOCKED (0x1UL << 0) /**< LOCKED Interrupt Enable */
+#define _SYNTH_IEN_LOCKED_SHIFT 0 /**< Shift value for SYNTH_LOCKED */
+#define _SYNTH_IEN_LOCKED_MASK 0x1UL /**< Bit mask for SYNTH_LOCKED */
+#define _SYNTH_IEN_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_IEN */
+#define SYNTH_IEN_LOCKED_DEFAULT (_SYNTH_IEN_LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_IEN */
+#define SYNTH_IEN_UNLOCKED (0x1UL << 1) /**< UNLOCKED Interrupt Enable */
+#define _SYNTH_IEN_UNLOCKED_SHIFT 1 /**< Shift value for SYNTH_UNLOCKED */
+#define _SYNTH_IEN_UNLOCKED_MASK 0x2UL /**< Bit mask for SYNTH_UNLOCKED */
+#define _SYNTH_IEN_UNLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_IEN */
+#define SYNTH_IEN_UNLOCKED_DEFAULT (_SYNTH_IEN_UNLOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for SYNTH_IEN */
+#define SYNTH_IEN_SYRDY (0x1UL << 2) /**< CAPCALDONE Interrupt Enable */
+#define _SYNTH_IEN_SYRDY_SHIFT 2 /**< Shift value for SYNTH_SYRDY */
+#define _SYNTH_IEN_SYRDY_MASK 0x4UL /**< Bit mask for SYNTH_SYRDY */
+#define _SYNTH_IEN_SYRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_IEN */
+#define SYNTH_IEN_SYRDY_DEFAULT (_SYNTH_IEN_SYRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for SYNTH_IEN */
+#define SYNTH_IEN_VCOHIGH (0x1UL << 4) /**< VCOHIGH Interrupt Enable */
+#define _SYNTH_IEN_VCOHIGH_SHIFT 4 /**< Shift value for SYNTH_VCOHIGH */
+#define _SYNTH_IEN_VCOHIGH_MASK 0x10UL /**< Bit mask for SYNTH_VCOHIGH */
+#define _SYNTH_IEN_VCOHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_IEN */
+#define SYNTH_IEN_VCOHIGH_DEFAULT (_SYNTH_IEN_VCOHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for SYNTH_IEN */
+#define SYNTH_IEN_VCOLOW (0x1UL << 5) /**< VCOLOW Interrupt Enable */
+#define _SYNTH_IEN_VCOLOW_SHIFT 5 /**< Shift value for SYNTH_VCOLOW */
+#define _SYNTH_IEN_VCOLOW_MASK 0x20UL /**< Bit mask for SYNTH_VCOLOW */
+#define _SYNTH_IEN_VCOLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_IEN */
+#define SYNTH_IEN_VCOLOW_DEFAULT (_SYNTH_IEN_VCOLOW_DEFAULT << 5) /**< Shifted mode DEFAULT for SYNTH_IEN */
+#define SYNTH_IEN_LOCNTDONE (0x1UL << 9) /**< LOCNTDONE Interrupt Enable */
+#define _SYNTH_IEN_LOCNTDONE_SHIFT 9 /**< Shift value for SYNTH_LOCNTDONE */
+#define _SYNTH_IEN_LOCNTDONE_MASK 0x200UL /**< Bit mask for SYNTH_LOCNTDONE */
+#define _SYNTH_IEN_LOCNTDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_IEN */
+#define SYNTH_IEN_LOCNTDONE_DEFAULT (_SYNTH_IEN_LOCNTDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for SYNTH_IEN */
+
+/* Bit fields for SYNTH LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for SYNTH_LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_MASK 0x00000FFFUL /**< Mask for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_ENABLE (0x1UL << 0) /**< Enable LO Counter */
+#define _SYNTH_LOCNTCTRL_ENABLE_SHIFT 0 /**< Shift value for SYNTH_ENABLE */
+#define _SYNTH_LOCNTCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SYNTH_ENABLE */
+#define _SYNTH_LOCNTCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_ENABLE_OFF 0x00000000UL /**< Mode OFF for SYNTH_LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_ENABLE_ON 0x00000001UL /**< Mode ON for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_ENABLE_DEFAULT (_SYNTH_LOCNTCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_ENABLE_OFF (_SYNTH_LOCNTCTRL_ENABLE_OFF << 0) /**< Shifted mode OFF for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_ENABLE_ON (_SYNTH_LOCNTCTRL_ENABLE_ON << 0) /**< Shifted mode ON for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_CLEAR (0x1UL << 1) /**< Clear LO Counter */
+#define _SYNTH_LOCNTCTRL_CLEAR_SHIFT 1 /**< Shift value for SYNTH_CLEAR */
+#define _SYNTH_LOCNTCTRL_CLEAR_MASK 0x2UL /**< Bit mask for SYNTH_CLEAR */
+#define _SYNTH_LOCNTCTRL_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_CLEAR_OFF 0x00000000UL /**< Mode OFF for SYNTH_LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_CLEAR_ON 0x00000001UL /**< Mode ON for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_CLEAR_DEFAULT (_SYNTH_LOCNTCTRL_CLEAR_DEFAULT << 1) /**< Shifted mode DEFAULT for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_CLEAR_OFF (_SYNTH_LOCNTCTRL_CLEAR_OFF << 1) /**< Shifted mode OFF for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_CLEAR_ON (_SYNTH_LOCNTCTRL_CLEAR_ON << 1) /**< Shifted mode ON for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_RUN (0x1UL << 2) /**< Run LO Counter */
+#define _SYNTH_LOCNTCTRL_RUN_SHIFT 2 /**< Shift value for SYNTH_RUN */
+#define _SYNTH_LOCNTCTRL_RUN_MASK 0x4UL /**< Bit mask for SYNTH_RUN */
+#define _SYNTH_LOCNTCTRL_RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_RUN_OFF 0x00000000UL /**< Mode OFF for SYNTH_LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_RUN_ON 0x00000001UL /**< Mode ON for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_RUN_DEFAULT (_SYNTH_LOCNTCTRL_RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_RUN_OFF (_SYNTH_LOCNTCTRL_RUN_OFF << 2) /**< Shifted mode OFF for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_RUN_ON (_SYNTH_LOCNTCTRL_RUN_ON << 2) /**< Shifted mode ON for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_READ (0x1UL << 3) /**< Read LO Counter */
+#define _SYNTH_LOCNTCTRL_READ_SHIFT 3 /**< Shift value for SYNTH_READ */
+#define _SYNTH_LOCNTCTRL_READ_MASK 0x8UL /**< Bit mask for SYNTH_READ */
+#define _SYNTH_LOCNTCTRL_READ_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_READ_OFF 0x00000000UL /**< Mode OFF for SYNTH_LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_READ_ON 0x00000001UL /**< Mode ON for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_READ_DEFAULT (_SYNTH_LOCNTCTRL_READ_DEFAULT << 3) /**< Shifted mode DEFAULT for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_READ_OFF (_SYNTH_LOCNTCTRL_READ_OFF << 3) /**< Shifted mode OFF for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_READ_ON (_SYNTH_LOCNTCTRL_READ_ON << 3) /**< Shifted mode ON for SYNTH_LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_NUMCYCLE_SHIFT 4 /**< Shift value for SYNTH_NUMCYCLE */
+#define _SYNTH_LOCNTCTRL_NUMCYCLE_MASK 0xF0UL /**< Bit mask for SYNTH_NUMCYCLE */
+#define _SYNTH_LOCNTCTRL_NUMCYCLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_NUMCYCLE_CNT_2 0x00000000UL /**< Mode CNT_2 for SYNTH_LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_NUMCYCLE_CNT_4 0x00000001UL /**< Mode CNT_4 for SYNTH_LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_NUMCYCLE_CNT_8 0x00000002UL /**< Mode CNT_8 for SYNTH_LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_NUMCYCLE_CNT_16 0x00000003UL /**< Mode CNT_16 for SYNTH_LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_NUMCYCLE_CNT_32 0x00000004UL /**< Mode CNT_32 for SYNTH_LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_NUMCYCLE_CNT_64 0x00000005UL /**< Mode CNT_64 for SYNTH_LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_NUMCYCLE_CNT_128 0x00000006UL /**< Mode CNT_128 for SYNTH_LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_NUMCYCLE_CNT_256 0x00000007UL /**< Mode CNT_256 for SYNTH_LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_NUMCYCLE_CNT_512 0x00000008UL /**< Mode CNT_512 for SYNTH_LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_NUMCYCLE_CNT_1024 0x00000009UL /**< Mode CNT_1024 for SYNTH_LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_NUMCYCLE_CNT_2048 0x0000000AUL /**< Mode CNT_2048 for SYNTH_LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_NUMCYCLE_CNT_4096 0x0000000BUL /**< Mode CNT_4096 for SYNTH_LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_NUMCYCLE_CNT_8192 0x0000000CUL /**< Mode CNT_8192 for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_NUMCYCLE_DEFAULT (_SYNTH_LOCNTCTRL_NUMCYCLE_DEFAULT << 4) /**< Shifted mode DEFAULT for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_NUMCYCLE_CNT_2 (_SYNTH_LOCNTCTRL_NUMCYCLE_CNT_2 << 4) /**< Shifted mode CNT_2 for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_NUMCYCLE_CNT_4 (_SYNTH_LOCNTCTRL_NUMCYCLE_CNT_4 << 4) /**< Shifted mode CNT_4 for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_NUMCYCLE_CNT_8 (_SYNTH_LOCNTCTRL_NUMCYCLE_CNT_8 << 4) /**< Shifted mode CNT_8 for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_NUMCYCLE_CNT_16 (_SYNTH_LOCNTCTRL_NUMCYCLE_CNT_16 << 4) /**< Shifted mode CNT_16 for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_NUMCYCLE_CNT_32 (_SYNTH_LOCNTCTRL_NUMCYCLE_CNT_32 << 4) /**< Shifted mode CNT_32 for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_NUMCYCLE_CNT_64 (_SYNTH_LOCNTCTRL_NUMCYCLE_CNT_64 << 4) /**< Shifted mode CNT_64 for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_NUMCYCLE_CNT_128 (_SYNTH_LOCNTCTRL_NUMCYCLE_CNT_128 << 4) /**< Shifted mode CNT_128 for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_NUMCYCLE_CNT_256 (_SYNTH_LOCNTCTRL_NUMCYCLE_CNT_256 << 4) /**< Shifted mode CNT_256 for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_NUMCYCLE_CNT_512 (_SYNTH_LOCNTCTRL_NUMCYCLE_CNT_512 << 4) /**< Shifted mode CNT_512 for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_NUMCYCLE_CNT_1024 (_SYNTH_LOCNTCTRL_NUMCYCLE_CNT_1024 << 4) /**< Shifted mode CNT_1024 for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_NUMCYCLE_CNT_2048 (_SYNTH_LOCNTCTRL_NUMCYCLE_CNT_2048 << 4) /**< Shifted mode CNT_2048 for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_NUMCYCLE_CNT_4096 (_SYNTH_LOCNTCTRL_NUMCYCLE_CNT_4096 << 4) /**< Shifted mode CNT_4096 for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_NUMCYCLE_CNT_8192 (_SYNTH_LOCNTCTRL_NUMCYCLE_CNT_8192 << 4) /**< Shifted mode CNT_8192 for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_LOCNTOVERRIDEEN (0x1UL << 8) /**< Enable manual override of CLEAR and RUN */
+#define _SYNTH_LOCNTCTRL_LOCNTOVERRIDEEN_SHIFT 8 /**< Shift value for SYNTH_LOCNTOVERRIDEEN */
+#define _SYNTH_LOCNTCTRL_LOCNTOVERRIDEEN_MASK 0x100UL /**< Bit mask for SYNTH_LOCNTOVERRIDEEN */
+#define _SYNTH_LOCNTCTRL_LOCNTOVERRIDEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_LOCNTOVERRIDEEN_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_LOCNTOVERRIDEEN_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_LOCNTOVERRIDEEN_DEFAULT (_SYNTH_LOCNTCTRL_LOCNTOVERRIDEEN_DEFAULT << 8) /**< Shifted mode DEFAULT for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_LOCNTOVERRIDEEN_DISABLE (_SYNTH_LOCNTCTRL_LOCNTOVERRIDEEN_DISABLE << 8) /**< Shifted mode DISABLE for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_LOCNTOVERRIDEEN_ENABLE (_SYNTH_LOCNTCTRL_LOCNTOVERRIDEEN_ENABLE << 8) /**< Shifted mode ENABLE for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_LOCNTMANCLEAR (0x1UL << 9) /**< Manual Control of LO counter CLEAR */
+#define _SYNTH_LOCNTCTRL_LOCNTMANCLEAR_SHIFT 9 /**< Shift value for SYNTH_LOCNTMANCLEAR */
+#define _SYNTH_LOCNTCTRL_LOCNTMANCLEAR_MASK 0x200UL /**< Bit mask for SYNTH_LOCNTMANCLEAR */
+#define _SYNTH_LOCNTCTRL_LOCNTMANCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_LOCNTMANCLEAR_NOCLEAR 0x00000000UL /**< Mode NOCLEAR for SYNTH_LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_LOCNTMANCLEAR_CLEAR 0x00000001UL /**< Mode CLEAR for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_LOCNTMANCLEAR_DEFAULT (_SYNTH_LOCNTCTRL_LOCNTMANCLEAR_DEFAULT << 9) /**< Shifted mode DEFAULT for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_LOCNTMANCLEAR_NOCLEAR (_SYNTH_LOCNTCTRL_LOCNTMANCLEAR_NOCLEAR << 9) /**< Shifted mode NOCLEAR for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_LOCNTMANCLEAR_CLEAR (_SYNTH_LOCNTCTRL_LOCNTMANCLEAR_CLEAR << 9) /**< Shifted mode CLEAR for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_LOCNTMANRUN (0x1UL << 10) /**< Manual Control of the LO counter RUN */
+#define _SYNTH_LOCNTCTRL_LOCNTMANRUN_SHIFT 10 /**< Shift value for SYNTH_LOCNTMANRUN */
+#define _SYNTH_LOCNTCTRL_LOCNTMANRUN_MASK 0x400UL /**< Bit mask for SYNTH_LOCNTMANRUN */
+#define _SYNTH_LOCNTCTRL_LOCNTMANRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_LOCNTMANRUN_NORUN 0x00000000UL /**< Mode NORUN for SYNTH_LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_LOCNTMANRUN_RUN 0x00000001UL /**< Mode RUN for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_LOCNTMANRUN_DEFAULT (_SYNTH_LOCNTCTRL_LOCNTMANRUN_DEFAULT << 10) /**< Shifted mode DEFAULT for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_LOCNTMANRUN_NORUN (_SYNTH_LOCNTCTRL_LOCNTMANRUN_NORUN << 10) /**< Shifted mode NORUN for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_LOCNTMANRUN_RUN (_SYNTH_LOCNTCTRL_LOCNTMANRUN_RUN << 10) /**< Shifted mode RUN for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_FCALRUNCLKEN (0x1UL << 11) /**< Enable FCAL run pulse counter clock */
+#define _SYNTH_LOCNTCTRL_FCALRUNCLKEN_SHIFT 11 /**< Shift value for SYNTH_FCALRUNCLKEN */
+#define _SYNTH_LOCNTCTRL_FCALRUNCLKEN_MASK 0x800UL /**< Bit mask for SYNTH_FCALRUNCLKEN */
+#define _SYNTH_LOCNTCTRL_FCALRUNCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_FCALRUNCLKEN_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_LOCNTCTRL */
+#define _SYNTH_LOCNTCTRL_FCALRUNCLKEN_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_FCALRUNCLKEN_DEFAULT (_SYNTH_LOCNTCTRL_FCALRUNCLKEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_FCALRUNCLKEN_DISABLE (_SYNTH_LOCNTCTRL_FCALRUNCLKEN_DISABLE << 11) /**< Shifted mode DISABLE for SYNTH_LOCNTCTRL */
+#define SYNTH_LOCNTCTRL_FCALRUNCLKEN_ENABLE (_SYNTH_LOCNTCTRL_FCALRUNCLKEN_ENABLE << 11) /**< Shifted mode ENABLE for SYNTH_LOCNTCTRL */
+
+/* Bit fields for SYNTH LOCNTSTATUS */
+#define _SYNTH_LOCNTSTATUS_RESETVALUE 0x00000000UL /**< Default value for SYNTH_LOCNTSTATUS */
+#define _SYNTH_LOCNTSTATUS_MASK 0x000FFFFFUL /**< Mask for SYNTH_LOCNTSTATUS */
+#define _SYNTH_LOCNTSTATUS_LOCOUNT_SHIFT 0 /**< Shift value for SYNTH_LOCOUNT */
+#define _SYNTH_LOCNTSTATUS_LOCOUNT_MASK 0x7FFFFUL /**< Bit mask for SYNTH_LOCOUNT */
+#define _SYNTH_LOCNTSTATUS_LOCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LOCNTSTATUS */
+#define SYNTH_LOCNTSTATUS_LOCOUNT_DEFAULT (_SYNTH_LOCNTSTATUS_LOCOUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_LOCNTSTATUS */
+#define SYNTH_LOCNTSTATUS_BUSY (0x1UL << 19) /**< LO Counter is Busy */
+#define _SYNTH_LOCNTSTATUS_BUSY_SHIFT 19 /**< Shift value for SYNTH_BUSY */
+#define _SYNTH_LOCNTSTATUS_BUSY_MASK 0x80000UL /**< Bit mask for SYNTH_BUSY */
+#define _SYNTH_LOCNTSTATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LOCNTSTATUS */
+#define SYNTH_LOCNTSTATUS_BUSY_DEFAULT (_SYNTH_LOCNTSTATUS_BUSY_DEFAULT << 19) /**< Shifted mode DEFAULT for SYNTH_LOCNTSTATUS */
+
+/* Bit fields for SYNTH LOCNTTARGET */
+#define _SYNTH_LOCNTTARGET_RESETVALUE 0x00000000UL /**< Default value for SYNTH_LOCNTTARGET */
+#define _SYNTH_LOCNTTARGET_MASK 0x0007FFFFUL /**< Mask for SYNTH_LOCNTTARGET */
+#define _SYNTH_LOCNTTARGET_TARGET_SHIFT 0 /**< Shift value for SYNTH_TARGET */
+#define _SYNTH_LOCNTTARGET_TARGET_MASK 0x7FFFFUL /**< Bit mask for SYNTH_TARGET */
+#define _SYNTH_LOCNTTARGET_TARGET_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LOCNTTARGET */
+#define SYNTH_LOCNTTARGET_TARGET_DEFAULT (_SYNTH_LOCNTTARGET_TARGET_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_LOCNTTARGET */
+
+/* Bit fields for SYNTH MMDDENOMINIT */
+#define _SYNTH_MMDDENOMINIT_RESETVALUE 0x00000000UL /**< Default value for SYNTH_MMDDENOMINIT */
+#define _SYNTH_MMDDENOMINIT_MASK 0x07FFFFFFUL /**< Mask for SYNTH_MMDDENOMINIT */
+#define _SYNTH_MMDDENOMINIT_DENOMINIT0_SHIFT 0 /**< Shift value for SYNTH_DENOMINIT0 */
+#define _SYNTH_MMDDENOMINIT_DENOMINIT0_MASK 0x1FFUL /**< Bit mask for SYNTH_DENOMINIT0 */
+#define _SYNTH_MMDDENOMINIT_DENOMINIT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_MMDDENOMINIT */
+#define SYNTH_MMDDENOMINIT_DENOMINIT0_DEFAULT (_SYNTH_MMDDENOMINIT_DENOMINIT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_MMDDENOMINIT */
+#define _SYNTH_MMDDENOMINIT_DENOMINIT1_SHIFT 9 /**< Shift value for SYNTH_DENOMINIT1 */
+#define _SYNTH_MMDDENOMINIT_DENOMINIT1_MASK 0x3FE00UL /**< Bit mask for SYNTH_DENOMINIT1 */
+#define _SYNTH_MMDDENOMINIT_DENOMINIT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_MMDDENOMINIT */
+#define SYNTH_MMDDENOMINIT_DENOMINIT1_DEFAULT (_SYNTH_MMDDENOMINIT_DENOMINIT1_DEFAULT << 9) /**< Shifted mode DEFAULT for SYNTH_MMDDENOMINIT */
+#define _SYNTH_MMDDENOMINIT_DENOMINIT2_SHIFT 18 /**< Shift value for SYNTH_DENOMINIT2 */
+#define _SYNTH_MMDDENOMINIT_DENOMINIT2_MASK 0x7FC0000UL /**< Bit mask for SYNTH_DENOMINIT2 */
+#define _SYNTH_MMDDENOMINIT_DENOMINIT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_MMDDENOMINIT */
+#define SYNTH_MMDDENOMINIT_DENOMINIT2_DEFAULT (_SYNTH_MMDDENOMINIT_DENOMINIT2_DEFAULT << 18) /**< Shifted mode DEFAULT for SYNTH_MMDDENOMINIT */
+
+/* Bit fields for SYNTH CHPDACINIT */
+#define _SYNTH_CHPDACINIT_RESETVALUE 0x00000000UL /**< Default value for SYNTH_CHPDACINIT */
+#define _SYNTH_CHPDACINIT_MASK 0x00000FFFUL /**< Mask for SYNTH_CHPDACINIT */
+#define _SYNTH_CHPDACINIT_DACINIT_SHIFT 0 /**< Shift value for SYNTH_DACINIT */
+#define _SYNTH_CHPDACINIT_DACINIT_MASK 0xFFFUL /**< Bit mask for SYNTH_DACINIT */
+#define _SYNTH_CHPDACINIT_DACINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_CHPDACINIT */
+#define SYNTH_CHPDACINIT_DACINIT_DEFAULT (_SYNTH_CHPDACINIT_DACINIT_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_CHPDACINIT */
+
+/* Bit fields for SYNTH LPFCTRL1CAL */
+#define _SYNTH_LPFCTRL1CAL_RESETVALUE 0x00000000UL /**< Default value for SYNTH_LPFCTRL1CAL */
+#define _SYNTH_LPFCTRL1CAL_MASK 0x0003FFFFUL /**< Mask for SYNTH_LPFCTRL1CAL */
+#define _SYNTH_LPFCTRL1CAL_OP1BWCAL_SHIFT 0 /**< Shift value for SYNTH_OP1BWCAL */
+#define _SYNTH_LPFCTRL1CAL_OP1BWCAL_MASK 0xFUL /**< Bit mask for SYNTH_OP1BWCAL */
+#define _SYNTH_LPFCTRL1CAL_OP1BWCAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL1CAL */
+#define SYNTH_LPFCTRL1CAL_OP1BWCAL_DEFAULT (_SYNTH_LPFCTRL1CAL_OP1BWCAL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL1CAL */
+#define _SYNTH_LPFCTRL1CAL_OP1COMPCAL_SHIFT 4 /**< Shift value for SYNTH_OP1COMPCAL */
+#define _SYNTH_LPFCTRL1CAL_OP1COMPCAL_MASK 0xF0UL /**< Bit mask for SYNTH_OP1COMPCAL */
+#define _SYNTH_LPFCTRL1CAL_OP1COMPCAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL1CAL */
+#define SYNTH_LPFCTRL1CAL_OP1COMPCAL_DEFAULT (_SYNTH_LPFCTRL1CAL_OP1COMPCAL_DEFAULT << 4) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL1CAL */
+#define _SYNTH_LPFCTRL1CAL_RFBVALCAL_SHIFT 8 /**< Shift value for SYNTH_RFBVALCAL */
+#define _SYNTH_LPFCTRL1CAL_RFBVALCAL_MASK 0x700UL /**< Bit mask for SYNTH_RFBVALCAL */
+#define _SYNTH_LPFCTRL1CAL_RFBVALCAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL1CAL */
+#define SYNTH_LPFCTRL1CAL_RFBVALCAL_DEFAULT (_SYNTH_LPFCTRL1CAL_RFBVALCAL_DEFAULT << 8) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL1CAL */
+#define _SYNTH_LPFCTRL1CAL_RPVALCAL_SHIFT 11 /**< Shift value for SYNTH_RPVALCAL */
+#define _SYNTH_LPFCTRL1CAL_RPVALCAL_MASK 0x3800UL /**< Bit mask for SYNTH_RPVALCAL */
+#define _SYNTH_LPFCTRL1CAL_RPVALCAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL1CAL */
+#define SYNTH_LPFCTRL1CAL_RPVALCAL_DEFAULT (_SYNTH_LPFCTRL1CAL_RPVALCAL_DEFAULT << 11) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL1CAL */
+#define _SYNTH_LPFCTRL1CAL_RZVALCAL_SHIFT 14 /**< Shift value for SYNTH_RZVALCAL */
+#define _SYNTH_LPFCTRL1CAL_RZVALCAL_MASK 0x3C000UL /**< Bit mask for SYNTH_RZVALCAL */
+#define _SYNTH_LPFCTRL1CAL_RZVALCAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL1CAL */
+#define SYNTH_LPFCTRL1CAL_RZVALCAL_DEFAULT (_SYNTH_LPFCTRL1CAL_RZVALCAL_DEFAULT << 14) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL1CAL */
+
+/* Bit fields for SYNTH LPFCTRL1RX */
+#define _SYNTH_LPFCTRL1RX_RESETVALUE 0x00000000UL /**< Default value for SYNTH_LPFCTRL1RX */
+#define _SYNTH_LPFCTRL1RX_MASK 0x0003FFFFUL /**< Mask for SYNTH_LPFCTRL1RX */
+#define _SYNTH_LPFCTRL1RX_OP1BWRX_SHIFT 0 /**< Shift value for SYNTH_OP1BWRX */
+#define _SYNTH_LPFCTRL1RX_OP1BWRX_MASK 0xFUL /**< Bit mask for SYNTH_OP1BWRX */
+#define _SYNTH_LPFCTRL1RX_OP1BWRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL1RX */
+#define SYNTH_LPFCTRL1RX_OP1BWRX_DEFAULT (_SYNTH_LPFCTRL1RX_OP1BWRX_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL1RX */
+#define _SYNTH_LPFCTRL1RX_OP1COMPRX_SHIFT 4 /**< Shift value for SYNTH_OP1COMPRX */
+#define _SYNTH_LPFCTRL1RX_OP1COMPRX_MASK 0xF0UL /**< Bit mask for SYNTH_OP1COMPRX */
+#define _SYNTH_LPFCTRL1RX_OP1COMPRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL1RX */
+#define SYNTH_LPFCTRL1RX_OP1COMPRX_DEFAULT (_SYNTH_LPFCTRL1RX_OP1COMPRX_DEFAULT << 4) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL1RX */
+#define _SYNTH_LPFCTRL1RX_RFBVALRX_SHIFT 8 /**< Shift value for SYNTH_RFBVALRX */
+#define _SYNTH_LPFCTRL1RX_RFBVALRX_MASK 0x700UL /**< Bit mask for SYNTH_RFBVALRX */
+#define _SYNTH_LPFCTRL1RX_RFBVALRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL1RX */
+#define SYNTH_LPFCTRL1RX_RFBVALRX_DEFAULT (_SYNTH_LPFCTRL1RX_RFBVALRX_DEFAULT << 8) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL1RX */
+#define _SYNTH_LPFCTRL1RX_RPVALRX_SHIFT 11 /**< Shift value for SYNTH_RPVALRX */
+#define _SYNTH_LPFCTRL1RX_RPVALRX_MASK 0x3800UL /**< Bit mask for SYNTH_RPVALRX */
+#define _SYNTH_LPFCTRL1RX_RPVALRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL1RX */
+#define SYNTH_LPFCTRL1RX_RPVALRX_DEFAULT (_SYNTH_LPFCTRL1RX_RPVALRX_DEFAULT << 11) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL1RX */
+#define _SYNTH_LPFCTRL1RX_RZVALRX_SHIFT 14 /**< Shift value for SYNTH_RZVALRX */
+#define _SYNTH_LPFCTRL1RX_RZVALRX_MASK 0x3C000UL /**< Bit mask for SYNTH_RZVALRX */
+#define _SYNTH_LPFCTRL1RX_RZVALRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL1RX */
+#define SYNTH_LPFCTRL1RX_RZVALRX_DEFAULT (_SYNTH_LPFCTRL1RX_RZVALRX_DEFAULT << 14) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL1RX */
+
+/* Bit fields for SYNTH LPFCTRL1TX */
+#define _SYNTH_LPFCTRL1TX_RESETVALUE 0x00000000UL /**< Default value for SYNTH_LPFCTRL1TX */
+#define _SYNTH_LPFCTRL1TX_MASK 0x0003FFFFUL /**< Mask for SYNTH_LPFCTRL1TX */
+#define _SYNTH_LPFCTRL1TX_OP1BWTX_SHIFT 0 /**< Shift value for SYNTH_OP1BWTX */
+#define _SYNTH_LPFCTRL1TX_OP1BWTX_MASK 0xFUL /**< Bit mask for SYNTH_OP1BWTX */
+#define _SYNTH_LPFCTRL1TX_OP1BWTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL1TX */
+#define SYNTH_LPFCTRL1TX_OP1BWTX_DEFAULT (_SYNTH_LPFCTRL1TX_OP1BWTX_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL1TX */
+#define _SYNTH_LPFCTRL1TX_OP1COMPTX_SHIFT 4 /**< Shift value for SYNTH_OP1COMPTX */
+#define _SYNTH_LPFCTRL1TX_OP1COMPTX_MASK 0xF0UL /**< Bit mask for SYNTH_OP1COMPTX */
+#define _SYNTH_LPFCTRL1TX_OP1COMPTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL1TX */
+#define SYNTH_LPFCTRL1TX_OP1COMPTX_DEFAULT (_SYNTH_LPFCTRL1TX_OP1COMPTX_DEFAULT << 4) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL1TX */
+#define _SYNTH_LPFCTRL1TX_RFBVALTX_SHIFT 8 /**< Shift value for SYNTH_RFBVALTX */
+#define _SYNTH_LPFCTRL1TX_RFBVALTX_MASK 0x700UL /**< Bit mask for SYNTH_RFBVALTX */
+#define _SYNTH_LPFCTRL1TX_RFBVALTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL1TX */
+#define SYNTH_LPFCTRL1TX_RFBVALTX_DEFAULT (_SYNTH_LPFCTRL1TX_RFBVALTX_DEFAULT << 8) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL1TX */
+#define _SYNTH_LPFCTRL1TX_RPVALTX_SHIFT 11 /**< Shift value for SYNTH_RPVALTX */
+#define _SYNTH_LPFCTRL1TX_RPVALTX_MASK 0x3800UL /**< Bit mask for SYNTH_RPVALTX */
+#define _SYNTH_LPFCTRL1TX_RPVALTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL1TX */
+#define SYNTH_LPFCTRL1TX_RPVALTX_DEFAULT (_SYNTH_LPFCTRL1TX_RPVALTX_DEFAULT << 11) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL1TX */
+#define _SYNTH_LPFCTRL1TX_RZVALTX_SHIFT 14 /**< Shift value for SYNTH_RZVALTX */
+#define _SYNTH_LPFCTRL1TX_RZVALTX_MASK 0x3C000UL /**< Bit mask for SYNTH_RZVALTX */
+#define _SYNTH_LPFCTRL1TX_RZVALTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL1TX */
+#define SYNTH_LPFCTRL1TX_RZVALTX_DEFAULT (_SYNTH_LPFCTRL1TX_RZVALTX_DEFAULT << 14) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL1TX */
+
+/* Bit fields for SYNTH LPFCTRL2RX */
+#define _SYNTH_LPFCTRL2RX_RESETVALUE 0x00000000UL /**< Default value for SYNTH_LPFCTRL2RX */
+#define _SYNTH_LPFCTRL2RX_MASK 0x1FFFFFFFUL /**< Mask for SYNTH_LPFCTRL2RX */
+#define SYNTH_LPFCTRL2RX_LPFSWENRX (0x1UL << 0) /**< LPF Switching Enable in RX Mode */
+#define _SYNTH_LPFCTRL2RX_LPFSWENRX_SHIFT 0 /**< Shift value for SYNTH_LPFSWENRX */
+#define _SYNTH_LPFCTRL2RX_LPFSWENRX_MASK 0x1UL /**< Bit mask for SYNTH_LPFSWENRX */
+#define _SYNTH_LPFCTRL2RX_LPFSWENRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2RX */
+#define _SYNTH_LPFCTRL2RX_LPFSWENRX_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_LPFCTRL2RX */
+#define _SYNTH_LPFCTRL2RX_LPFSWENRX_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_LPFCTRL2RX */
+#define SYNTH_LPFCTRL2RX_LPFSWENRX_DEFAULT (_SYNTH_LPFCTRL2RX_LPFSWENRX_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2RX */
+#define SYNTH_LPFCTRL2RX_LPFSWENRX_DISABLE (_SYNTH_LPFCTRL2RX_LPFSWENRX_DISABLE << 0) /**< Shifted mode DISABLE for SYNTH_LPFCTRL2RX */
+#define SYNTH_LPFCTRL2RX_LPFSWENRX_ENABLE (_SYNTH_LPFCTRL2RX_LPFSWENRX_ENABLE << 0) /**< Shifted mode ENABLE for SYNTH_LPFCTRL2RX */
+#define _SYNTH_LPFCTRL2RX_LPFINCAPRX_SHIFT 1 /**< Shift value for SYNTH_LPFINCAPRX */
+#define _SYNTH_LPFCTRL2RX_LPFINCAPRX_MASK 0x6UL /**< Bit mask for SYNTH_LPFINCAPRX */
+#define _SYNTH_LPFCTRL2RX_LPFINCAPRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2RX */
+#define SYNTH_LPFCTRL2RX_LPFINCAPRX_DEFAULT (_SYNTH_LPFCTRL2RX_LPFINCAPRX_DEFAULT << 1) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2RX */
+#define SYNTH_LPFCTRL2RX_LPFGNDSWENRX (0x1UL << 3) /**< LPF Gnd Switch Enable in RX Mode */
+#define _SYNTH_LPFCTRL2RX_LPFGNDSWENRX_SHIFT 3 /**< Shift value for SYNTH_LPFGNDSWENRX */
+#define _SYNTH_LPFCTRL2RX_LPFGNDSWENRX_MASK 0x8UL /**< Bit mask for SYNTH_LPFGNDSWENRX */
+#define _SYNTH_LPFCTRL2RX_LPFGNDSWENRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2RX */
+#define _SYNTH_LPFCTRL2RX_LPFGNDSWENRX_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_LPFCTRL2RX */
+#define _SYNTH_LPFCTRL2RX_LPFGNDSWENRX_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_LPFCTRL2RX */
+#define SYNTH_LPFCTRL2RX_LPFGNDSWENRX_DEFAULT (_SYNTH_LPFCTRL2RX_LPFGNDSWENRX_DEFAULT << 3) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2RX */
+#define SYNTH_LPFCTRL2RX_LPFGNDSWENRX_DISABLE (_SYNTH_LPFCTRL2RX_LPFGNDSWENRX_DISABLE << 3) /**< Shifted mode DISABLE for SYNTH_LPFCTRL2RX */
+#define SYNTH_LPFCTRL2RX_LPFGNDSWENRX_ENABLE (_SYNTH_LPFCTRL2RX_LPFGNDSWENRX_ENABLE << 3) /**< Shifted mode ENABLE for SYNTH_LPFCTRL2RX */
+#define _SYNTH_LPFCTRL2RX_CALCRX_SHIFT 4 /**< Shift value for SYNTH_CALCRX */
+#define _SYNTH_LPFCTRL2RX_CALCRX_MASK 0x1F0UL /**< Bit mask for SYNTH_CALCRX */
+#define _SYNTH_LPFCTRL2RX_CALCRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2RX */
+#define SYNTH_LPFCTRL2RX_CALCRX_DEFAULT (_SYNTH_LPFCTRL2RX_CALCRX_DEFAULT << 4) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2RX */
+#define SYNTH_LPFCTRL2RX_CASELRX (0x1UL << 9) /**< LPF Ca Select in RX Mode */
+#define _SYNTH_LPFCTRL2RX_CASELRX_SHIFT 9 /**< Shift value for SYNTH_CASELRX */
+#define _SYNTH_LPFCTRL2RX_CASELRX_MASK 0x200UL /**< Bit mask for SYNTH_CASELRX */
+#define _SYNTH_LPFCTRL2RX_CASELRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2RX */
+#define _SYNTH_LPFCTRL2RX_CASELRX_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_LPFCTRL2RX */
+#define _SYNTH_LPFCTRL2RX_CASELRX_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_LPFCTRL2RX */
+#define SYNTH_LPFCTRL2RX_CASELRX_DEFAULT (_SYNTH_LPFCTRL2RX_CASELRX_DEFAULT << 9) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2RX */
+#define SYNTH_LPFCTRL2RX_CASELRX_DISABLE (_SYNTH_LPFCTRL2RX_CASELRX_DISABLE << 9) /**< Shifted mode DISABLE for SYNTH_LPFCTRL2RX */
+#define SYNTH_LPFCTRL2RX_CASELRX_ENABLE (_SYNTH_LPFCTRL2RX_CASELRX_ENABLE << 9) /**< Shifted mode ENABLE for SYNTH_LPFCTRL2RX */
+#define _SYNTH_LPFCTRL2RX_CAVALRX_SHIFT 10 /**< Shift value for SYNTH_CAVALRX */
+#define _SYNTH_LPFCTRL2RX_CAVALRX_MASK 0x7C00UL /**< Bit mask for SYNTH_CAVALRX */
+#define _SYNTH_LPFCTRL2RX_CAVALRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2RX */
+#define SYNTH_LPFCTRL2RX_CAVALRX_DEFAULT (_SYNTH_LPFCTRL2RX_CAVALRX_DEFAULT << 10) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2RX */
+#define SYNTH_LPFCTRL2RX_CFBSELRX (0x1UL << 15) /**< LPF Cfb Select in RX Mode */
+#define _SYNTH_LPFCTRL2RX_CFBSELRX_SHIFT 15 /**< Shift value for SYNTH_CFBSELRX */
+#define _SYNTH_LPFCTRL2RX_CFBSELRX_MASK 0x8000UL /**< Bit mask for SYNTH_CFBSELRX */
+#define _SYNTH_LPFCTRL2RX_CFBSELRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2RX */
+#define _SYNTH_LPFCTRL2RX_CFBSELRX_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_LPFCTRL2RX */
+#define _SYNTH_LPFCTRL2RX_CFBSELRX_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_LPFCTRL2RX */
+#define SYNTH_LPFCTRL2RX_CFBSELRX_DEFAULT (_SYNTH_LPFCTRL2RX_CFBSELRX_DEFAULT << 15) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2RX */
+#define SYNTH_LPFCTRL2RX_CFBSELRX_DISABLE (_SYNTH_LPFCTRL2RX_CFBSELRX_DISABLE << 15) /**< Shifted mode DISABLE for SYNTH_LPFCTRL2RX */
+#define SYNTH_LPFCTRL2RX_CFBSELRX_ENABLE (_SYNTH_LPFCTRL2RX_CFBSELRX_ENABLE << 15) /**< Shifted mode ENABLE for SYNTH_LPFCTRL2RX */
+#define SYNTH_LPFCTRL2RX_CZSELRX (0x1UL << 16) /**< LPF Cz Select in RX Mode */
+#define _SYNTH_LPFCTRL2RX_CZSELRX_SHIFT 16 /**< Shift value for SYNTH_CZSELRX */
+#define _SYNTH_LPFCTRL2RX_CZSELRX_MASK 0x10000UL /**< Bit mask for SYNTH_CZSELRX */
+#define _SYNTH_LPFCTRL2RX_CZSELRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2RX */
+#define _SYNTH_LPFCTRL2RX_CZSELRX_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_LPFCTRL2RX */
+#define _SYNTH_LPFCTRL2RX_CZSELRX_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_LPFCTRL2RX */
+#define SYNTH_LPFCTRL2RX_CZSELRX_DEFAULT (_SYNTH_LPFCTRL2RX_CZSELRX_DEFAULT << 16) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2RX */
+#define SYNTH_LPFCTRL2RX_CZSELRX_DISABLE (_SYNTH_LPFCTRL2RX_CZSELRX_DISABLE << 16) /**< Shifted mode DISABLE for SYNTH_LPFCTRL2RX */
+#define SYNTH_LPFCTRL2RX_CZSELRX_ENABLE (_SYNTH_LPFCTRL2RX_CZSELRX_ENABLE << 16) /**< Shifted mode ENABLE for SYNTH_LPFCTRL2RX */
+#define _SYNTH_LPFCTRL2RX_CZVALRX_SHIFT 17 /**< Shift value for SYNTH_CZVALRX */
+#define _SYNTH_LPFCTRL2RX_CZVALRX_MASK 0x1FE0000UL /**< Bit mask for SYNTH_CZVALRX */
+#define _SYNTH_LPFCTRL2RX_CZVALRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2RX */
+#define SYNTH_LPFCTRL2RX_CZVALRX_DEFAULT (_SYNTH_LPFCTRL2RX_CZVALRX_DEFAULT << 17) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2RX */
+#define SYNTH_LPFCTRL2RX_MODESELRX (0x1UL << 25) /**< LPF Filter Mode Select in RX Mode */
+#define _SYNTH_LPFCTRL2RX_MODESELRX_SHIFT 25 /**< Shift value for SYNTH_MODESELRX */
+#define _SYNTH_LPFCTRL2RX_MODESELRX_MASK 0x2000000UL /**< Bit mask for SYNTH_MODESELRX */
+#define _SYNTH_LPFCTRL2RX_MODESELRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2RX */
+#define _SYNTH_LPFCTRL2RX_MODESELRX_ONEOP 0x00000000UL /**< Mode ONEOP for SYNTH_LPFCTRL2RX */
+#define _SYNTH_LPFCTRL2RX_MODESELRX_TWOOP 0x00000001UL /**< Mode TWOOP for SYNTH_LPFCTRL2RX */
+#define SYNTH_LPFCTRL2RX_MODESELRX_DEFAULT (_SYNTH_LPFCTRL2RX_MODESELRX_DEFAULT << 25) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2RX */
+#define SYNTH_LPFCTRL2RX_MODESELRX_ONEOP (_SYNTH_LPFCTRL2RX_MODESELRX_ONEOP << 25) /**< Shifted mode ONEOP for SYNTH_LPFCTRL2RX */
+#define SYNTH_LPFCTRL2RX_MODESELRX_TWOOP (_SYNTH_LPFCTRL2RX_MODESELRX_TWOOP << 25) /**< Shifted mode TWOOP for SYNTH_LPFCTRL2RX */
+#define _SYNTH_LPFCTRL2RX_VCMLVLRX_SHIFT 26 /**< Shift value for SYNTH_VCMLVLRX */
+#define _SYNTH_LPFCTRL2RX_VCMLVLRX_MASK 0x1C000000UL /**< Bit mask for SYNTH_VCMLVLRX */
+#define _SYNTH_LPFCTRL2RX_VCMLVLRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2RX */
+#define SYNTH_LPFCTRL2RX_VCMLVLRX_DEFAULT (_SYNTH_LPFCTRL2RX_VCMLVLRX_DEFAULT << 26) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2RX */
+
+/* Bit fields for SYNTH LPFCTRL2TX */
+#define _SYNTH_LPFCTRL2TX_RESETVALUE 0x00000000UL /**< Default value for SYNTH_LPFCTRL2TX */
+#define _SYNTH_LPFCTRL2TX_MASK 0x1FFFFFFFUL /**< Mask for SYNTH_LPFCTRL2TX */
+#define SYNTH_LPFCTRL2TX_LPFSWENTX (0x1UL << 0) /**< LPF Switching Enable in TX Mode */
+#define _SYNTH_LPFCTRL2TX_LPFSWENTX_SHIFT 0 /**< Shift value for SYNTH_LPFSWENTX */
+#define _SYNTH_LPFCTRL2TX_LPFSWENTX_MASK 0x1UL /**< Bit mask for SYNTH_LPFSWENTX */
+#define _SYNTH_LPFCTRL2TX_LPFSWENTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2TX */
+#define _SYNTH_LPFCTRL2TX_LPFSWENTX_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_LPFCTRL2TX */
+#define _SYNTH_LPFCTRL2TX_LPFSWENTX_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_LPFCTRL2TX */
+#define SYNTH_LPFCTRL2TX_LPFSWENTX_DEFAULT (_SYNTH_LPFCTRL2TX_LPFSWENTX_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2TX */
+#define SYNTH_LPFCTRL2TX_LPFSWENTX_DISABLE (_SYNTH_LPFCTRL2TX_LPFSWENTX_DISABLE << 0) /**< Shifted mode DISABLE for SYNTH_LPFCTRL2TX */
+#define SYNTH_LPFCTRL2TX_LPFSWENTX_ENABLE (_SYNTH_LPFCTRL2TX_LPFSWENTX_ENABLE << 0) /**< Shifted mode ENABLE for SYNTH_LPFCTRL2TX */
+#define _SYNTH_LPFCTRL2TX_LPFINCAPTX_SHIFT 1 /**< Shift value for SYNTH_LPFINCAPTX */
+#define _SYNTH_LPFCTRL2TX_LPFINCAPTX_MASK 0x6UL /**< Bit mask for SYNTH_LPFINCAPTX */
+#define _SYNTH_LPFCTRL2TX_LPFINCAPTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2TX */
+#define SYNTH_LPFCTRL2TX_LPFINCAPTX_DEFAULT (_SYNTH_LPFCTRL2TX_LPFINCAPTX_DEFAULT << 1) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2TX */
+#define SYNTH_LPFCTRL2TX_LPFGNDSWENTX (0x1UL << 3) /**< LPF Gnd Switch Enable in TX Mode */
+#define _SYNTH_LPFCTRL2TX_LPFGNDSWENTX_SHIFT 3 /**< Shift value for SYNTH_LPFGNDSWENTX */
+#define _SYNTH_LPFCTRL2TX_LPFGNDSWENTX_MASK 0x8UL /**< Bit mask for SYNTH_LPFGNDSWENTX */
+#define _SYNTH_LPFCTRL2TX_LPFGNDSWENTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2TX */
+#define _SYNTH_LPFCTRL2TX_LPFGNDSWENTX_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_LPFCTRL2TX */
+#define _SYNTH_LPFCTRL2TX_LPFGNDSWENTX_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_LPFCTRL2TX */
+#define SYNTH_LPFCTRL2TX_LPFGNDSWENTX_DEFAULT (_SYNTH_LPFCTRL2TX_LPFGNDSWENTX_DEFAULT << 3) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2TX */
+#define SYNTH_LPFCTRL2TX_LPFGNDSWENTX_DISABLE (_SYNTH_LPFCTRL2TX_LPFGNDSWENTX_DISABLE << 3) /**< Shifted mode DISABLE for SYNTH_LPFCTRL2TX */
+#define SYNTH_LPFCTRL2TX_LPFGNDSWENTX_ENABLE (_SYNTH_LPFCTRL2TX_LPFGNDSWENTX_ENABLE << 3) /**< Shifted mode ENABLE for SYNTH_LPFCTRL2TX */
+#define _SYNTH_LPFCTRL2TX_CALCTX_SHIFT 4 /**< Shift value for SYNTH_CALCTX */
+#define _SYNTH_LPFCTRL2TX_CALCTX_MASK 0x1F0UL /**< Bit mask for SYNTH_CALCTX */
+#define _SYNTH_LPFCTRL2TX_CALCTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2TX */
+#define SYNTH_LPFCTRL2TX_CALCTX_DEFAULT (_SYNTH_LPFCTRL2TX_CALCTX_DEFAULT << 4) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2TX */
+#define SYNTH_LPFCTRL2TX_CASELTX (0x1UL << 9) /**< LPF Ca Select in TX Mode */
+#define _SYNTH_LPFCTRL2TX_CASELTX_SHIFT 9 /**< Shift value for SYNTH_CASELTX */
+#define _SYNTH_LPFCTRL2TX_CASELTX_MASK 0x200UL /**< Bit mask for SYNTH_CASELTX */
+#define _SYNTH_LPFCTRL2TX_CASELTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2TX */
+#define _SYNTH_LPFCTRL2TX_CASELTX_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_LPFCTRL2TX */
+#define _SYNTH_LPFCTRL2TX_CASELTX_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_LPFCTRL2TX */
+#define SYNTH_LPFCTRL2TX_CASELTX_DEFAULT (_SYNTH_LPFCTRL2TX_CASELTX_DEFAULT << 9) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2TX */
+#define SYNTH_LPFCTRL2TX_CASELTX_DISABLE (_SYNTH_LPFCTRL2TX_CASELTX_DISABLE << 9) /**< Shifted mode DISABLE for SYNTH_LPFCTRL2TX */
+#define SYNTH_LPFCTRL2TX_CASELTX_ENABLE (_SYNTH_LPFCTRL2TX_CASELTX_ENABLE << 9) /**< Shifted mode ENABLE for SYNTH_LPFCTRL2TX */
+#define _SYNTH_LPFCTRL2TX_CAVALTX_SHIFT 10 /**< Shift value for SYNTH_CAVALTX */
+#define _SYNTH_LPFCTRL2TX_CAVALTX_MASK 0x7C00UL /**< Bit mask for SYNTH_CAVALTX */
+#define _SYNTH_LPFCTRL2TX_CAVALTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2TX */
+#define SYNTH_LPFCTRL2TX_CAVALTX_DEFAULT (_SYNTH_LPFCTRL2TX_CAVALTX_DEFAULT << 10) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2TX */
+#define SYNTH_LPFCTRL2TX_CFBSELTX (0x1UL << 15) /**< LPF Cfb Select in TX Mode */
+#define _SYNTH_LPFCTRL2TX_CFBSELTX_SHIFT 15 /**< Shift value for SYNTH_CFBSELTX */
+#define _SYNTH_LPFCTRL2TX_CFBSELTX_MASK 0x8000UL /**< Bit mask for SYNTH_CFBSELTX */
+#define _SYNTH_LPFCTRL2TX_CFBSELTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2TX */
+#define _SYNTH_LPFCTRL2TX_CFBSELTX_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_LPFCTRL2TX */
+#define _SYNTH_LPFCTRL2TX_CFBSELTX_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_LPFCTRL2TX */
+#define SYNTH_LPFCTRL2TX_CFBSELTX_DEFAULT (_SYNTH_LPFCTRL2TX_CFBSELTX_DEFAULT << 15) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2TX */
+#define SYNTH_LPFCTRL2TX_CFBSELTX_DISABLE (_SYNTH_LPFCTRL2TX_CFBSELTX_DISABLE << 15) /**< Shifted mode DISABLE for SYNTH_LPFCTRL2TX */
+#define SYNTH_LPFCTRL2TX_CFBSELTX_ENABLE (_SYNTH_LPFCTRL2TX_CFBSELTX_ENABLE << 15) /**< Shifted mode ENABLE for SYNTH_LPFCTRL2TX */
+#define SYNTH_LPFCTRL2TX_CZSELTX (0x1UL << 16) /**< LPF Cz Select in TX Mode */
+#define _SYNTH_LPFCTRL2TX_CZSELTX_SHIFT 16 /**< Shift value for SYNTH_CZSELTX */
+#define _SYNTH_LPFCTRL2TX_CZSELTX_MASK 0x10000UL /**< Bit mask for SYNTH_CZSELTX */
+#define _SYNTH_LPFCTRL2TX_CZSELTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2TX */
+#define _SYNTH_LPFCTRL2TX_CZSELTX_DISABLE 0x00000000UL /**< Mode DISABLE for SYNTH_LPFCTRL2TX */
+#define _SYNTH_LPFCTRL2TX_CZSELTX_ENABLE 0x00000001UL /**< Mode ENABLE for SYNTH_LPFCTRL2TX */
+#define SYNTH_LPFCTRL2TX_CZSELTX_DEFAULT (_SYNTH_LPFCTRL2TX_CZSELTX_DEFAULT << 16) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2TX */
+#define SYNTH_LPFCTRL2TX_CZSELTX_DISABLE (_SYNTH_LPFCTRL2TX_CZSELTX_DISABLE << 16) /**< Shifted mode DISABLE for SYNTH_LPFCTRL2TX */
+#define SYNTH_LPFCTRL2TX_CZSELTX_ENABLE (_SYNTH_LPFCTRL2TX_CZSELTX_ENABLE << 16) /**< Shifted mode ENABLE for SYNTH_LPFCTRL2TX */
+#define _SYNTH_LPFCTRL2TX_CZVALTX_SHIFT 17 /**< Shift value for SYNTH_CZVALTX */
+#define _SYNTH_LPFCTRL2TX_CZVALTX_MASK 0x1FE0000UL /**< Bit mask for SYNTH_CZVALTX */
+#define _SYNTH_LPFCTRL2TX_CZVALTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2TX */
+#define SYNTH_LPFCTRL2TX_CZVALTX_DEFAULT (_SYNTH_LPFCTRL2TX_CZVALTX_DEFAULT << 17) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2TX */
+#define SYNTH_LPFCTRL2TX_MODESELTX (0x1UL << 25) /**< LPF Filter Mode Select in TX Mode */
+#define _SYNTH_LPFCTRL2TX_MODESELTX_SHIFT 25 /**< Shift value for SYNTH_MODESELTX */
+#define _SYNTH_LPFCTRL2TX_MODESELTX_MASK 0x2000000UL /**< Bit mask for SYNTH_MODESELTX */
+#define _SYNTH_LPFCTRL2TX_MODESELTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2TX */
+#define _SYNTH_LPFCTRL2TX_MODESELTX_ONEOP 0x00000000UL /**< Mode ONEOP for SYNTH_LPFCTRL2TX */
+#define _SYNTH_LPFCTRL2TX_MODESELTX_TWOOP 0x00000001UL /**< Mode TWOOP for SYNTH_LPFCTRL2TX */
+#define SYNTH_LPFCTRL2TX_MODESELTX_DEFAULT (_SYNTH_LPFCTRL2TX_MODESELTX_DEFAULT << 25) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2TX */
+#define SYNTH_LPFCTRL2TX_MODESELTX_ONEOP (_SYNTH_LPFCTRL2TX_MODESELTX_ONEOP << 25) /**< Shifted mode ONEOP for SYNTH_LPFCTRL2TX */
+#define SYNTH_LPFCTRL2TX_MODESELTX_TWOOP (_SYNTH_LPFCTRL2TX_MODESELTX_TWOOP << 25) /**< Shifted mode TWOOP for SYNTH_LPFCTRL2TX */
+#define _SYNTH_LPFCTRL2TX_VCMLVLTX_SHIFT 26 /**< Shift value for SYNTH_VCMLVLTX */
+#define _SYNTH_LPFCTRL2TX_VCMLVLTX_MASK 0x1C000000UL /**< Bit mask for SYNTH_VCMLVLTX */
+#define _SYNTH_LPFCTRL2TX_VCMLVLTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_LPFCTRL2TX */
+#define SYNTH_LPFCTRL2TX_VCMLVLTX_DEFAULT (_SYNTH_LPFCTRL2TX_VCMLVLTX_DEFAULT << 26) /**< Shifted mode DEFAULT for SYNTH_LPFCTRL2TX */
+
+/* Bit fields for SYNTH DSMCTRLRX */
+#define _SYNTH_DSMCTRLRX_RESETVALUE 0x00000013UL /**< Default value for SYNTH_DSMCTRLRX */
+#define _SYNTH_DSMCTRLRX_MASK 0x070003FFUL /**< Mask for SYNTH_DSMCTRLRX */
+#define SYNTH_DSMCTRLRX_DITHERDSMINPUTRX (0x1UL << 0) /**< Dithering of DSM input for RX mode */
+#define _SYNTH_DSMCTRLRX_DITHERDSMINPUTRX_SHIFT 0 /**< Shift value for SYNTH_DITHERDSMINPUTRX */
+#define _SYNTH_DSMCTRLRX_DITHERDSMINPUTRX_MASK 0x1UL /**< Bit mask for SYNTH_DITHERDSMINPUTRX */
+#define _SYNTH_DSMCTRLRX_DITHERDSMINPUTRX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYNTH_DSMCTRLRX */
+#define SYNTH_DSMCTRLRX_DITHERDSMINPUTRX_DEFAULT (_SYNTH_DSMCTRLRX_DITHERDSMINPUTRX_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLRX */
+#define _SYNTH_DSMCTRLRX_DITHERDSMOUTPUTRX_SHIFT 1 /**< Shift value for SYNTH_DITHERDSMOUTPUTRX */
+#define _SYNTH_DSMCTRLRX_DITHERDSMOUTPUTRX_MASK 0xEUL /**< Bit mask for SYNTH_DITHERDSMOUTPUTRX */
+#define _SYNTH_DSMCTRLRX_DITHERDSMOUTPUTRX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYNTH_DSMCTRLRX */
+#define SYNTH_DSMCTRLRX_DITHERDSMOUTPUTRX_DEFAULT (_SYNTH_DSMCTRLRX_DITHERDSMOUTPUTRX_DEFAULT << 1) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLRX */
+#define _SYNTH_DSMCTRLRX_DITHERDACRX_SHIFT 4 /**< Shift value for SYNTH_DITHERDACRX */
+#define _SYNTH_DSMCTRLRX_DITHERDACRX_MASK 0xF0UL /**< Bit mask for SYNTH_DITHERDACRX */
+#define _SYNTH_DSMCTRLRX_DITHERDACRX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYNTH_DSMCTRLRX */
+#define SYNTH_DSMCTRLRX_DITHERDACRX_DEFAULT (_SYNTH_DSMCTRLRX_DITHERDACRX_DEFAULT << 4) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLRX */
+#define SYNTH_DSMCTRLRX_DSMMODERX (0x1UL << 8) /**< Delta-sigma topology for RX mode */
+#define _SYNTH_DSMCTRLRX_DSMMODERX_SHIFT 8 /**< Shift value for SYNTH_DSMMODERX */
+#define _SYNTH_DSMCTRLRX_DSMMODERX_MASK 0x100UL /**< Bit mask for SYNTH_DSMMODERX */
+#define _SYNTH_DSMCTRLRX_DSMMODERX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_DSMCTRLRX */
+#define _SYNTH_DSMCTRLRX_DSMMODERX_FEEDFORWARD 0x00000000UL /**< Mode FEEDFORWARD for SYNTH_DSMCTRLRX */
+#define _SYNTH_DSMCTRLRX_DSMMODERX_MASH 0x00000001UL /**< Mode MASH for SYNTH_DSMCTRLRX */
+#define SYNTH_DSMCTRLRX_DSMMODERX_DEFAULT (_SYNTH_DSMCTRLRX_DSMMODERX_DEFAULT << 8) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLRX */
+#define SYNTH_DSMCTRLRX_DSMMODERX_FEEDFORWARD (_SYNTH_DSMCTRLRX_DSMMODERX_FEEDFORWARD << 8) /**< Shifted mode FEEDFORWARD for SYNTH_DSMCTRLRX*/
+#define SYNTH_DSMCTRLRX_DSMMODERX_MASH (_SYNTH_DSMCTRLRX_DSMMODERX_MASH << 8) /**< Shifted mode MASH for SYNTH_DSMCTRLRX */
+#define SYNTH_DSMCTRLRX_LSBFORCERX (0x1UL << 9) /**< Delta-sigma input force LSB for RX mode */
+#define _SYNTH_DSMCTRLRX_LSBFORCERX_SHIFT 9 /**< Shift value for SYNTH_LSBFORCERX */
+#define _SYNTH_DSMCTRLRX_LSBFORCERX_MASK 0x200UL /**< Bit mask for SYNTH_LSBFORCERX */
+#define _SYNTH_DSMCTRLRX_LSBFORCERX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_DSMCTRLRX */
+#define SYNTH_DSMCTRLRX_LSBFORCERX_DEFAULT (_SYNTH_DSMCTRLRX_LSBFORCERX_DEFAULT << 9) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLRX */
+#define SYNTH_DSMCTRLRX_DEMMODERX (0x1UL << 24) /**< DEM Mode for RX mode */
+#define _SYNTH_DSMCTRLRX_DEMMODERX_SHIFT 24 /**< Shift value for SYNTH_DEMMODERX */
+#define _SYNTH_DSMCTRLRX_DEMMODERX_MASK 0x1000000UL /**< Bit mask for SYNTH_DEMMODERX */
+#define _SYNTH_DSMCTRLRX_DEMMODERX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_DSMCTRLRX */
+#define _SYNTH_DSMCTRLRX_DEMMODERX_DISABLED 0x00000000UL /**< Mode DISABLED for SYNTH_DSMCTRLRX */
+#define _SYNTH_DSMCTRLRX_DEMMODERX_ENABLED 0x00000001UL /**< Mode ENABLED for SYNTH_DSMCTRLRX */
+#define SYNTH_DSMCTRLRX_DEMMODERX_DEFAULT (_SYNTH_DSMCTRLRX_DEMMODERX_DEFAULT << 24) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLRX */
+#define SYNTH_DSMCTRLRX_DEMMODERX_DISABLED (_SYNTH_DSMCTRLRX_DEMMODERX_DISABLED << 24) /**< Shifted mode DISABLED for SYNTH_DSMCTRLRX */
+#define SYNTH_DSMCTRLRX_DEMMODERX_ENABLED (_SYNTH_DSMCTRLRX_DEMMODERX_ENABLED << 24) /**< Shifted mode ENABLED for SYNTH_DSMCTRLRX */
+#define SYNTH_DSMCTRLRX_MASHORDERRX (0x1UL << 25) /**< MASH order for RX mode */
+#define _SYNTH_DSMCTRLRX_MASHORDERRX_SHIFT 25 /**< Shift value for SYNTH_MASHORDERRX */
+#define _SYNTH_DSMCTRLRX_MASHORDERRX_MASK 0x2000000UL /**< Bit mask for SYNTH_MASHORDERRX */
+#define _SYNTH_DSMCTRLRX_MASHORDERRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_DSMCTRLRX */
+#define _SYNTH_DSMCTRLRX_MASHORDERRX_SECOND 0x00000000UL /**< Mode SECOND for SYNTH_DSMCTRLRX */
+#define _SYNTH_DSMCTRLRX_MASHORDERRX_THIRD 0x00000001UL /**< Mode THIRD for SYNTH_DSMCTRLRX */
+#define SYNTH_DSMCTRLRX_MASHORDERRX_DEFAULT (_SYNTH_DSMCTRLRX_MASHORDERRX_DEFAULT << 25) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLRX */
+#define SYNTH_DSMCTRLRX_MASHORDERRX_SECOND (_SYNTH_DSMCTRLRX_MASHORDERRX_SECOND << 25) /**< Shifted mode SECOND for SYNTH_DSMCTRLRX */
+#define SYNTH_DSMCTRLRX_MASHORDERRX_THIRD (_SYNTH_DSMCTRLRX_MASHORDERRX_THIRD << 25) /**< Shifted mode THIRD for SYNTH_DSMCTRLRX */
+#define SYNTH_DSMCTRLRX_REQORDERRX (0x1UL << 26) /**< ReQuant order for RX mode */
+#define _SYNTH_DSMCTRLRX_REQORDERRX_SHIFT 26 /**< Shift value for SYNTH_REQORDERRX */
+#define _SYNTH_DSMCTRLRX_REQORDERRX_MASK 0x4000000UL /**< Bit mask for SYNTH_REQORDERRX */
+#define _SYNTH_DSMCTRLRX_REQORDERRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_DSMCTRLRX */
+#define _SYNTH_DSMCTRLRX_REQORDERRX_FIRST 0x00000000UL /**< Mode FIRST for SYNTH_DSMCTRLRX */
+#define _SYNTH_DSMCTRLRX_REQORDERRX_SECOND 0x00000001UL /**< Mode SECOND for SYNTH_DSMCTRLRX */
+#define SYNTH_DSMCTRLRX_REQORDERRX_DEFAULT (_SYNTH_DSMCTRLRX_REQORDERRX_DEFAULT << 26) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLRX */
+#define SYNTH_DSMCTRLRX_REQORDERRX_FIRST (_SYNTH_DSMCTRLRX_REQORDERRX_FIRST << 26) /**< Shifted mode FIRST for SYNTH_DSMCTRLRX */
+#define SYNTH_DSMCTRLRX_REQORDERRX_SECOND (_SYNTH_DSMCTRLRX_REQORDERRX_SECOND << 26) /**< Shifted mode SECOND for SYNTH_DSMCTRLRX */
+
+/* Bit fields for SYNTH DSMCTRLTX */
+#define _SYNTH_DSMCTRLTX_RESETVALUE 0x00000013UL /**< Default value for SYNTH_DSMCTRLTX */
+#define _SYNTH_DSMCTRLTX_MASK 0x070003FFUL /**< Mask for SYNTH_DSMCTRLTX */
+#define SYNTH_DSMCTRLTX_DITHERDSMINPUTTX (0x1UL << 0) /**< Dithering of DSM input for TX mode */
+#define _SYNTH_DSMCTRLTX_DITHERDSMINPUTTX_SHIFT 0 /**< Shift value for SYNTH_DITHERDSMINPUTTX */
+#define _SYNTH_DSMCTRLTX_DITHERDSMINPUTTX_MASK 0x1UL /**< Bit mask for SYNTH_DITHERDSMINPUTTX */
+#define _SYNTH_DSMCTRLTX_DITHERDSMINPUTTX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYNTH_DSMCTRLTX */
+#define SYNTH_DSMCTRLTX_DITHERDSMINPUTTX_DEFAULT (_SYNTH_DSMCTRLTX_DITHERDSMINPUTTX_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLTX */
+#define _SYNTH_DSMCTRLTX_DITHERDSMOUTPUTTX_SHIFT 1 /**< Shift value for SYNTH_DITHERDSMOUTPUTTX */
+#define _SYNTH_DSMCTRLTX_DITHERDSMOUTPUTTX_MASK 0xEUL /**< Bit mask for SYNTH_DITHERDSMOUTPUTTX */
+#define _SYNTH_DSMCTRLTX_DITHERDSMOUTPUTTX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYNTH_DSMCTRLTX */
+#define SYNTH_DSMCTRLTX_DITHERDSMOUTPUTTX_DEFAULT (_SYNTH_DSMCTRLTX_DITHERDSMOUTPUTTX_DEFAULT << 1) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLTX */
+#define _SYNTH_DSMCTRLTX_DITHERDACTX_SHIFT 4 /**< Shift value for SYNTH_DITHERDACTX */
+#define _SYNTH_DSMCTRLTX_DITHERDACTX_MASK 0xF0UL /**< Bit mask for SYNTH_DITHERDACTX */
+#define _SYNTH_DSMCTRLTX_DITHERDACTX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYNTH_DSMCTRLTX */
+#define SYNTH_DSMCTRLTX_DITHERDACTX_DEFAULT (_SYNTH_DSMCTRLTX_DITHERDACTX_DEFAULT << 4) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLTX */
+#define SYNTH_DSMCTRLTX_DSMMODETX (0x1UL << 8) /**< Delta-sigma topology for TX mode */
+#define _SYNTH_DSMCTRLTX_DSMMODETX_SHIFT 8 /**< Shift value for SYNTH_DSMMODETX */
+#define _SYNTH_DSMCTRLTX_DSMMODETX_MASK 0x100UL /**< Bit mask for SYNTH_DSMMODETX */
+#define _SYNTH_DSMCTRLTX_DSMMODETX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_DSMCTRLTX */
+#define _SYNTH_DSMCTRLTX_DSMMODETX_FEEDFORWARD 0x00000000UL /**< Mode FEEDFORWARD for SYNTH_DSMCTRLTX */
+#define _SYNTH_DSMCTRLTX_DSMMODETX_MASH 0x00000001UL /**< Mode MASH for SYNTH_DSMCTRLTX */
+#define SYNTH_DSMCTRLTX_DSMMODETX_DEFAULT (_SYNTH_DSMCTRLTX_DSMMODETX_DEFAULT << 8) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLTX */
+#define SYNTH_DSMCTRLTX_DSMMODETX_FEEDFORWARD (_SYNTH_DSMCTRLTX_DSMMODETX_FEEDFORWARD << 8) /**< Shifted mode FEEDFORWARD for SYNTH_DSMCTRLTX*/
+#define SYNTH_DSMCTRLTX_DSMMODETX_MASH (_SYNTH_DSMCTRLTX_DSMMODETX_MASH << 8) /**< Shifted mode MASH for SYNTH_DSMCTRLTX */
+#define SYNTH_DSMCTRLTX_LSBFORCETX (0x1UL << 9) /**< Delta-sigma input force LSB for TX mode */
+#define _SYNTH_DSMCTRLTX_LSBFORCETX_SHIFT 9 /**< Shift value for SYNTH_LSBFORCETX */
+#define _SYNTH_DSMCTRLTX_LSBFORCETX_MASK 0x200UL /**< Bit mask for SYNTH_LSBFORCETX */
+#define _SYNTH_DSMCTRLTX_LSBFORCETX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_DSMCTRLTX */
+#define SYNTH_DSMCTRLTX_LSBFORCETX_DEFAULT (_SYNTH_DSMCTRLTX_LSBFORCETX_DEFAULT << 9) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLTX */
+#define SYNTH_DSMCTRLTX_DEMMODETX (0x1UL << 24) /**< DEM Mode for TX mode */
+#define _SYNTH_DSMCTRLTX_DEMMODETX_SHIFT 24 /**< Shift value for SYNTH_DEMMODETX */
+#define _SYNTH_DSMCTRLTX_DEMMODETX_MASK 0x1000000UL /**< Bit mask for SYNTH_DEMMODETX */
+#define _SYNTH_DSMCTRLTX_DEMMODETX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_DSMCTRLTX */
+#define _SYNTH_DSMCTRLTX_DEMMODETX_DISABLED 0x00000000UL /**< Mode DISABLED for SYNTH_DSMCTRLTX */
+#define _SYNTH_DSMCTRLTX_DEMMODETX_ENABLED 0x00000001UL /**< Mode ENABLED for SYNTH_DSMCTRLTX */
+#define SYNTH_DSMCTRLTX_DEMMODETX_DEFAULT (_SYNTH_DSMCTRLTX_DEMMODETX_DEFAULT << 24) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLTX */
+#define SYNTH_DSMCTRLTX_DEMMODETX_DISABLED (_SYNTH_DSMCTRLTX_DEMMODETX_DISABLED << 24) /**< Shifted mode DISABLED for SYNTH_DSMCTRLTX */
+#define SYNTH_DSMCTRLTX_DEMMODETX_ENABLED (_SYNTH_DSMCTRLTX_DEMMODETX_ENABLED << 24) /**< Shifted mode ENABLED for SYNTH_DSMCTRLTX */
+#define SYNTH_DSMCTRLTX_MASHORDERTX (0x1UL << 25) /**< MASH order for TX mode */
+#define _SYNTH_DSMCTRLTX_MASHORDERTX_SHIFT 25 /**< Shift value for SYNTH_MASHORDERTX */
+#define _SYNTH_DSMCTRLTX_MASHORDERTX_MASK 0x2000000UL /**< Bit mask for SYNTH_MASHORDERTX */
+#define _SYNTH_DSMCTRLTX_MASHORDERTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_DSMCTRLTX */
+#define _SYNTH_DSMCTRLTX_MASHORDERTX_SECOND 0x00000000UL /**< Mode SECOND for SYNTH_DSMCTRLTX */
+#define _SYNTH_DSMCTRLTX_MASHORDERTX_THIRD 0x00000001UL /**< Mode THIRD for SYNTH_DSMCTRLTX */
+#define SYNTH_DSMCTRLTX_MASHORDERTX_DEFAULT (_SYNTH_DSMCTRLTX_MASHORDERTX_DEFAULT << 25) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLTX */
+#define SYNTH_DSMCTRLTX_MASHORDERTX_SECOND (_SYNTH_DSMCTRLTX_MASHORDERTX_SECOND << 25) /**< Shifted mode SECOND for SYNTH_DSMCTRLTX */
+#define SYNTH_DSMCTRLTX_MASHORDERTX_THIRD (_SYNTH_DSMCTRLTX_MASHORDERTX_THIRD << 25) /**< Shifted mode THIRD for SYNTH_DSMCTRLTX */
+#define SYNTH_DSMCTRLTX_REQORDERTX (0x1UL << 26) /**< ReQuant order for TX mode */
+#define _SYNTH_DSMCTRLTX_REQORDERTX_SHIFT 26 /**< Shift value for SYNTH_REQORDERTX */
+#define _SYNTH_DSMCTRLTX_REQORDERTX_MASK 0x4000000UL /**< Bit mask for SYNTH_REQORDERTX */
+#define _SYNTH_DSMCTRLTX_REQORDERTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_DSMCTRLTX */
+#define _SYNTH_DSMCTRLTX_REQORDERTX_FIRST 0x00000000UL /**< Mode FIRST for SYNTH_DSMCTRLTX */
+#define _SYNTH_DSMCTRLTX_REQORDERTX_SECOND 0x00000001UL /**< Mode SECOND for SYNTH_DSMCTRLTX */
+#define SYNTH_DSMCTRLTX_REQORDERTX_DEFAULT (_SYNTH_DSMCTRLTX_REQORDERTX_DEFAULT << 26) /**< Shifted mode DEFAULT for SYNTH_DSMCTRLTX */
+#define SYNTH_DSMCTRLTX_REQORDERTX_FIRST (_SYNTH_DSMCTRLTX_REQORDERTX_FIRST << 26) /**< Shifted mode FIRST for SYNTH_DSMCTRLTX */
+#define SYNTH_DSMCTRLTX_REQORDERTX_SECOND (_SYNTH_DSMCTRLTX_REQORDERTX_SECOND << 26) /**< Shifted mode SECOND for SYNTH_DSMCTRLTX */
+
+/* Bit fields for SYNTH SEQIF */
+#define _SYNTH_SEQIF_RESETVALUE 0x00000000UL /**< Default value for SYNTH_SEQIF */
+#define _SYNTH_SEQIF_MASK 0x00000237UL /**< Mask for SYNTH_SEQIF */
+#define SYNTH_SEQIF_LOCKED (0x1UL << 0) /**< Synthesizer locked Interrupt Flag */
+#define _SYNTH_SEQIF_LOCKED_SHIFT 0 /**< Shift value for SYNTH_LOCKED */
+#define _SYNTH_SEQIF_LOCKED_MASK 0x1UL /**< Bit mask for SYNTH_LOCKED */
+#define _SYNTH_SEQIF_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_SEQIF */
+#define SYNTH_SEQIF_LOCKED_DEFAULT (_SYNTH_SEQIF_LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_SEQIF */
+#define SYNTH_SEQIF_UNLOCKED (0x1UL << 1) /**< Synthesizer unlocked Interrupt Flag */
+#define _SYNTH_SEQIF_UNLOCKED_SHIFT 1 /**< Shift value for SYNTH_UNLOCKED */
+#define _SYNTH_SEQIF_UNLOCKED_MASK 0x2UL /**< Bit mask for SYNTH_UNLOCKED */
+#define _SYNTH_SEQIF_UNLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_SEQIF */
+#define SYNTH_SEQIF_UNLOCKED_DEFAULT (_SYNTH_SEQIF_UNLOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for SYNTH_SEQIF */
+#define SYNTH_SEQIF_SYRDY (0x1UL << 2) /**< Synthesizer ready Interrupt Flag */
+#define _SYNTH_SEQIF_SYRDY_SHIFT 2 /**< Shift value for SYNTH_SYRDY */
+#define _SYNTH_SEQIF_SYRDY_MASK 0x4UL /**< Bit mask for SYNTH_SYRDY */
+#define _SYNTH_SEQIF_SYRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_SEQIF */
+#define SYNTH_SEQIF_SYRDY_DEFAULT (_SYNTH_SEQIF_SYRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for SYNTH_SEQIF */
+#define SYNTH_SEQIF_VCOHIGH (0x1UL << 4) /**< VCO high voltage Interrupt Flag */
+#define _SYNTH_SEQIF_VCOHIGH_SHIFT 4 /**< Shift value for SYNTH_VCOHIGH */
+#define _SYNTH_SEQIF_VCOHIGH_MASK 0x10UL /**< Bit mask for SYNTH_VCOHIGH */
+#define _SYNTH_SEQIF_VCOHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_SEQIF */
+#define SYNTH_SEQIF_VCOHIGH_DEFAULT (_SYNTH_SEQIF_VCOHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for SYNTH_SEQIF */
+#define SYNTH_SEQIF_VCOLOW (0x1UL << 5) /**< VCO low voltage Interrupt Flag */
+#define _SYNTH_SEQIF_VCOLOW_SHIFT 5 /**< Shift value for SYNTH_VCOLOW */
+#define _SYNTH_SEQIF_VCOLOW_MASK 0x20UL /**< Bit mask for SYNTH_VCOLOW */
+#define _SYNTH_SEQIF_VCOLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_SEQIF */
+#define SYNTH_SEQIF_VCOLOW_DEFAULT (_SYNTH_SEQIF_VCOLOW_DEFAULT << 5) /**< Shifted mode DEFAULT for SYNTH_SEQIF */
+#define SYNTH_SEQIF_LOCNTDONE (0x1UL << 9) /**< LOCNT measurement done Interrupt Flag */
+#define _SYNTH_SEQIF_LOCNTDONE_SHIFT 9 /**< Shift value for SYNTH_LOCNTDONE */
+#define _SYNTH_SEQIF_LOCNTDONE_MASK 0x200UL /**< Bit mask for SYNTH_LOCNTDONE */
+#define _SYNTH_SEQIF_LOCNTDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_SEQIF */
+#define SYNTH_SEQIF_LOCNTDONE_DEFAULT (_SYNTH_SEQIF_LOCNTDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for SYNTH_SEQIF */
+
+/* Bit fields for SYNTH SEQIEN */
+#define _SYNTH_SEQIEN_RESETVALUE 0x00000000UL /**< Default value for SYNTH_SEQIEN */
+#define _SYNTH_SEQIEN_MASK 0x00000237UL /**< Mask for SYNTH_SEQIEN */
+#define SYNTH_SEQIEN_LOCKED (0x1UL << 0) /**< LOCKED Interrupt Enable */
+#define _SYNTH_SEQIEN_LOCKED_SHIFT 0 /**< Shift value for SYNTH_LOCKED */
+#define _SYNTH_SEQIEN_LOCKED_MASK 0x1UL /**< Bit mask for SYNTH_LOCKED */
+#define _SYNTH_SEQIEN_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_SEQIEN */
+#define SYNTH_SEQIEN_LOCKED_DEFAULT (_SYNTH_SEQIEN_LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for SYNTH_SEQIEN */
+#define SYNTH_SEQIEN_UNLOCKED (0x1UL << 1) /**< UNLOCKED Interrupt Enable */
+#define _SYNTH_SEQIEN_UNLOCKED_SHIFT 1 /**< Shift value for SYNTH_UNLOCKED */
+#define _SYNTH_SEQIEN_UNLOCKED_MASK 0x2UL /**< Bit mask for SYNTH_UNLOCKED */
+#define _SYNTH_SEQIEN_UNLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_SEQIEN */
+#define SYNTH_SEQIEN_UNLOCKED_DEFAULT (_SYNTH_SEQIEN_UNLOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for SYNTH_SEQIEN */
+#define SYNTH_SEQIEN_SYRDY (0x1UL << 2) /**< CAPCALDONE Interrupt Enable */
+#define _SYNTH_SEQIEN_SYRDY_SHIFT 2 /**< Shift value for SYNTH_SYRDY */
+#define _SYNTH_SEQIEN_SYRDY_MASK 0x4UL /**< Bit mask for SYNTH_SYRDY */
+#define _SYNTH_SEQIEN_SYRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_SEQIEN */
+#define SYNTH_SEQIEN_SYRDY_DEFAULT (_SYNTH_SEQIEN_SYRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for SYNTH_SEQIEN */
+#define SYNTH_SEQIEN_VCOHIGH (0x1UL << 4) /**< VCOHIGH Interrupt Enable */
+#define _SYNTH_SEQIEN_VCOHIGH_SHIFT 4 /**< Shift value for SYNTH_VCOHIGH */
+#define _SYNTH_SEQIEN_VCOHIGH_MASK 0x10UL /**< Bit mask for SYNTH_VCOHIGH */
+#define _SYNTH_SEQIEN_VCOHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_SEQIEN */
+#define SYNTH_SEQIEN_VCOHIGH_DEFAULT (_SYNTH_SEQIEN_VCOHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for SYNTH_SEQIEN */
+#define SYNTH_SEQIEN_VCOLOW (0x1UL << 5) /**< VCOLOW Interrupt Enable */
+#define _SYNTH_SEQIEN_VCOLOW_SHIFT 5 /**< Shift value for SYNTH_VCOLOW */
+#define _SYNTH_SEQIEN_VCOLOW_MASK 0x20UL /**< Bit mask for SYNTH_VCOLOW */
+#define _SYNTH_SEQIEN_VCOLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_SEQIEN */
+#define SYNTH_SEQIEN_VCOLOW_DEFAULT (_SYNTH_SEQIEN_VCOLOW_DEFAULT << 5) /**< Shifted mode DEFAULT for SYNTH_SEQIEN */
+#define SYNTH_SEQIEN_LOCNTDONE (0x1UL << 9) /**< LOCNTDONE Interrupt Enable */
+#define _SYNTH_SEQIEN_LOCNTDONE_SHIFT 9 /**< Shift value for SYNTH_LOCNTDONE */
+#define _SYNTH_SEQIEN_LOCNTDONE_MASK 0x200UL /**< Bit mask for SYNTH_LOCNTDONE */
+#define _SYNTH_SEQIEN_LOCNTDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYNTH_SEQIEN */
+#define SYNTH_SEQIEN_LOCNTDONE_DEFAULT (_SYNTH_SEQIEN_LOCNTDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for SYNTH_SEQIEN */
+
+/** @} End of group EFR32MG24_SYNTH_BitFields */
+/** @} End of group EFR32MG24_SYNTH */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_SYNTH_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_syscfg.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_syscfg.h
new file mode 100644
index 00000000..5d2cc86b
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_syscfg.h
@@ -0,0 +1,772 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 SYSCFG register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_SYSCFG_H
+#define EFR32MG24_SYSCFG_H
+#define SYSCFG_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_SYSCFG SYSCFG
+ * @{
+ * @brief EFR32MG24 SYSCFG Register Declaration.
+ *****************************************************************************/
+
+/** SYSCFG Register Declaration. */
+typedef struct {
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION; /**< IP version ID */
+ __IOM uint32_t IF; /**< Interrupt Flag */
+ __IOM uint32_t IEN; /**< Interrupt Enable */
+ uint32_t RESERVED1[1U]; /**< Reserved for future use */
+ __IOM uint32_t CHIPREVHW; /**< Chip Revision, Hard-wired */
+ __IOM uint32_t CHIPREV; /**< Part Family and Revision Values */
+ uint32_t RESERVED2[2U]; /**< Reserved for future use */
+ __IOM uint32_t CFGSYSTIC; /**< SysTick clock source */
+ uint32_t RESERVED3[54U]; /**< Reserved for future use */
+ uint32_t RESERVED4[1U]; /**< Reserved for future use */
+ uint32_t RESERVED5[63U]; /**< Reserved for future use */
+ __IOM uint32_t CTRL; /**< Control */
+ uint32_t RESERVED6[1U]; /**< Reserved for future use */
+ __IOM uint32_t DMEM0RETNCTRL; /**< DMEM0 Retention Control */
+ uint32_t RESERVED7[64U]; /**< Reserved for future use */
+ __IOM uint32_t RAMBIASCONF; /**< RAM Bias Configuration */
+ uint32_t RESERVED8[60U]; /**< Reserved for future use */
+ __IOM uint32_t RADIORAMRETNCTRL; /**< RADIO RAM Retention Control */
+ uint32_t RESERVED9[1U]; /**< Reserved for future use */
+ __IOM uint32_t RADIOECCCTRL; /**< RADIO RAM ECC Control Register */
+ uint32_t RESERVED10[1U]; /**< Reserved for future use */
+ __IM uint32_t SEQRAMECCADDR; /**< SEQRAM ECC Address */
+ __IM uint32_t FRCRAMECCADDR; /**< FRCRAM ECC Address */
+ __IOM uint32_t ICACHERAMRETNCTRL; /**< HOST ICACHERAM Retention Control */
+ __IOM uint32_t DMEM0PORTMAPSEL; /**< DMEM0 port remap selection */
+ uint32_t RESERVED11[120U]; /**< Reserved for future use */
+ __IOM uint32_t ROOTDATA0; /**< Data Register 0 */
+ __IOM uint32_t ROOTDATA1; /**< Data Register 1 */
+ __IM uint32_t ROOTLOCKSTATUS; /**< Lock Status */
+ __IOM uint32_t ROOTSESWVERSION; /**< SE SW Version */
+ uint32_t RESERVED12[1U]; /**< Reserved for future use */
+ uint32_t RESERVED13[635U]; /**< Reserved for future use */
+ uint32_t RESERVED14[1U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP version ID */
+ __IOM uint32_t IF_SET; /**< Interrupt Flag */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable */
+ uint32_t RESERVED15[1U]; /**< Reserved for future use */
+ __IOM uint32_t CHIPREVHW_SET; /**< Chip Revision, Hard-wired */
+ __IOM uint32_t CHIPREV_SET; /**< Part Family and Revision Values */
+ uint32_t RESERVED16[2U]; /**< Reserved for future use */
+ __IOM uint32_t CFGSYSTIC_SET; /**< SysTick clock source */
+ uint32_t RESERVED17[54U]; /**< Reserved for future use */
+ uint32_t RESERVED18[1U]; /**< Reserved for future use */
+ uint32_t RESERVED19[63U]; /**< Reserved for future use */
+ __IOM uint32_t CTRL_SET; /**< Control */
+ uint32_t RESERVED20[1U]; /**< Reserved for future use */
+ __IOM uint32_t DMEM0RETNCTRL_SET; /**< DMEM0 Retention Control */
+ uint32_t RESERVED21[64U]; /**< Reserved for future use */
+ __IOM uint32_t RAMBIASCONF_SET; /**< RAM Bias Configuration */
+ uint32_t RESERVED22[60U]; /**< Reserved for future use */
+ __IOM uint32_t RADIORAMRETNCTRL_SET; /**< RADIO RAM Retention Control */
+ uint32_t RESERVED23[1U]; /**< Reserved for future use */
+ __IOM uint32_t RADIOECCCTRL_SET; /**< RADIO RAM ECC Control Register */
+ uint32_t RESERVED24[1U]; /**< Reserved for future use */
+ __IM uint32_t SEQRAMECCADDR_SET; /**< SEQRAM ECC Address */
+ __IM uint32_t FRCRAMECCADDR_SET; /**< FRCRAM ECC Address */
+ __IOM uint32_t ICACHERAMRETNCTRL_SET; /**< HOST ICACHERAM Retention Control */
+ __IOM uint32_t DMEM0PORTMAPSEL_SET; /**< DMEM0 port remap selection */
+ uint32_t RESERVED25[120U]; /**< Reserved for future use */
+ __IOM uint32_t ROOTDATA0_SET; /**< Data Register 0 */
+ __IOM uint32_t ROOTDATA1_SET; /**< Data Register 1 */
+ __IM uint32_t ROOTLOCKSTATUS_SET; /**< Lock Status */
+ __IOM uint32_t ROOTSESWVERSION_SET; /**< SE SW Version */
+ uint32_t RESERVED26[1U]; /**< Reserved for future use */
+ uint32_t RESERVED27[635U]; /**< Reserved for future use */
+ uint32_t RESERVED28[1U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP version ID */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flag */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable */
+ uint32_t RESERVED29[1U]; /**< Reserved for future use */
+ __IOM uint32_t CHIPREVHW_CLR; /**< Chip Revision, Hard-wired */
+ __IOM uint32_t CHIPREV_CLR; /**< Part Family and Revision Values */
+ uint32_t RESERVED30[2U]; /**< Reserved for future use */
+ __IOM uint32_t CFGSYSTIC_CLR; /**< SysTick clock source */
+ uint32_t RESERVED31[54U]; /**< Reserved for future use */
+ uint32_t RESERVED32[1U]; /**< Reserved for future use */
+ uint32_t RESERVED33[63U]; /**< Reserved for future use */
+ __IOM uint32_t CTRL_CLR; /**< Control */
+ uint32_t RESERVED34[1U]; /**< Reserved for future use */
+ __IOM uint32_t DMEM0RETNCTRL_CLR; /**< DMEM0 Retention Control */
+ uint32_t RESERVED35[64U]; /**< Reserved for future use */
+ __IOM uint32_t RAMBIASCONF_CLR; /**< RAM Bias Configuration */
+ uint32_t RESERVED36[60U]; /**< Reserved for future use */
+ __IOM uint32_t RADIORAMRETNCTRL_CLR; /**< RADIO RAM Retention Control */
+ uint32_t RESERVED37[1U]; /**< Reserved for future use */
+ __IOM uint32_t RADIOECCCTRL_CLR; /**< RADIO RAM ECC Control Register */
+ uint32_t RESERVED38[1U]; /**< Reserved for future use */
+ __IM uint32_t SEQRAMECCADDR_CLR; /**< SEQRAM ECC Address */
+ __IM uint32_t FRCRAMECCADDR_CLR; /**< FRCRAM ECC Address */
+ __IOM uint32_t ICACHERAMRETNCTRL_CLR; /**< HOST ICACHERAM Retention Control */
+ __IOM uint32_t DMEM0PORTMAPSEL_CLR; /**< DMEM0 port remap selection */
+ uint32_t RESERVED39[120U]; /**< Reserved for future use */
+ __IOM uint32_t ROOTDATA0_CLR; /**< Data Register 0 */
+ __IOM uint32_t ROOTDATA1_CLR; /**< Data Register 1 */
+ __IM uint32_t ROOTLOCKSTATUS_CLR; /**< Lock Status */
+ __IOM uint32_t ROOTSESWVERSION_CLR; /**< SE SW Version */
+ uint32_t RESERVED40[1U]; /**< Reserved for future use */
+ uint32_t RESERVED41[635U]; /**< Reserved for future use */
+ uint32_t RESERVED42[1U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP version ID */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flag */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable */
+ uint32_t RESERVED43[1U]; /**< Reserved for future use */
+ __IOM uint32_t CHIPREVHW_TGL; /**< Chip Revision, Hard-wired */
+ __IOM uint32_t CHIPREV_TGL; /**< Part Family and Revision Values */
+ uint32_t RESERVED44[2U]; /**< Reserved for future use */
+ __IOM uint32_t CFGSYSTIC_TGL; /**< SysTick clock source */
+ uint32_t RESERVED45[54U]; /**< Reserved for future use */
+ uint32_t RESERVED46[1U]; /**< Reserved for future use */
+ uint32_t RESERVED47[63U]; /**< Reserved for future use */
+ __IOM uint32_t CTRL_TGL; /**< Control */
+ uint32_t RESERVED48[1U]; /**< Reserved for future use */
+ __IOM uint32_t DMEM0RETNCTRL_TGL; /**< DMEM0 Retention Control */
+ uint32_t RESERVED49[64U]; /**< Reserved for future use */
+ __IOM uint32_t RAMBIASCONF_TGL; /**< RAM Bias Configuration */
+ uint32_t RESERVED50[60U]; /**< Reserved for future use */
+ __IOM uint32_t RADIORAMRETNCTRL_TGL; /**< RADIO RAM Retention Control */
+ uint32_t RESERVED51[1U]; /**< Reserved for future use */
+ __IOM uint32_t RADIOECCCTRL_TGL; /**< RADIO RAM ECC Control Register */
+ uint32_t RESERVED52[1U]; /**< Reserved for future use */
+ __IM uint32_t SEQRAMECCADDR_TGL; /**< SEQRAM ECC Address */
+ __IM uint32_t FRCRAMECCADDR_TGL; /**< FRCRAM ECC Address */
+ __IOM uint32_t ICACHERAMRETNCTRL_TGL; /**< HOST ICACHERAM Retention Control */
+ __IOM uint32_t DMEM0PORTMAPSEL_TGL; /**< DMEM0 port remap selection */
+ uint32_t RESERVED53[120U]; /**< Reserved for future use */
+ __IOM uint32_t ROOTDATA0_TGL; /**< Data Register 0 */
+ __IOM uint32_t ROOTDATA1_TGL; /**< Data Register 1 */
+ __IM uint32_t ROOTLOCKSTATUS_TGL; /**< Lock Status */
+ __IOM uint32_t ROOTSESWVERSION_TGL; /**< SE SW Version */
+ uint32_t RESERVED54[1U]; /**< Reserved for future use */
+} SYSCFG_TypeDef;
+/** @} End of group EFR32MG24_SYSCFG */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_SYSCFG
+ * @{
+ * @defgroup EFR32MG24_SYSCFG_BitFields SYSCFG Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for SYSCFG IPVERSION */
+#define _SYSCFG_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for SYSCFG_IPVERSION */
+#define _SYSCFG_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_IPVERSION */
+#define _SYSCFG_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SYSCFG_IPVERSION */
+#define _SYSCFG_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_IPVERSION */
+#define _SYSCFG_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for SYSCFG_IPVERSION */
+#define SYSCFG_IPVERSION_IPVERSION_DEFAULT (_SYSCFG_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IPVERSION */
+
+/* Bit fields for SYSCFG IF */
+#define _SYSCFG_IF_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IF */
+#define _SYSCFG_IF_MASK 0x33033F0FUL /**< Mask for SYSCFG_IF */
+#define SYSCFG_IF_SW0 (0x1UL << 0) /**< Software Interrupt Flag */
+#define _SYSCFG_IF_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */
+#define _SYSCFG_IF_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */
+#define _SYSCFG_IF_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */
+#define SYSCFG_IF_SW0_DEFAULT (_SYSCFG_IF_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IF */
+#define SYSCFG_IF_SW1 (0x1UL << 1) /**< Software Interrupt Flag */
+#define _SYSCFG_IF_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */
+#define _SYSCFG_IF_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */
+#define _SYSCFG_IF_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */
+#define SYSCFG_IF_SW1_DEFAULT (_SYSCFG_IF_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IF */
+#define SYSCFG_IF_SW2 (0x1UL << 2) /**< Software Interrupt Flag */
+#define _SYSCFG_IF_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */
+#define _SYSCFG_IF_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */
+#define _SYSCFG_IF_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */
+#define SYSCFG_IF_SW2_DEFAULT (_SYSCFG_IF_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IF */
+#define SYSCFG_IF_SW3 (0x1UL << 3) /**< Software Interrupt Flag */
+#define _SYSCFG_IF_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */
+#define _SYSCFG_IF_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */
+#define _SYSCFG_IF_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */
+#define SYSCFG_IF_SW3_DEFAULT (_SYSCFG_IF_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IF */
+#define SYSCFG_IF_FPIOC (0x1UL << 8) /**< FPU Invalid Operation interrupt flag */
+#define _SYSCFG_IF_FPIOC_SHIFT 8 /**< Shift value for SYSCFG_FPIOC */
+#define _SYSCFG_IF_FPIOC_MASK 0x100UL /**< Bit mask for SYSCFG_FPIOC */
+#define _SYSCFG_IF_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */
+#define SYSCFG_IF_FPIOC_DEFAULT (_SYSCFG_IF_FPIOC_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_IF */
+#define SYSCFG_IF_FPDZC (0x1UL << 9) /**< FPU Divide by zero interrupt flag */
+#define _SYSCFG_IF_FPDZC_SHIFT 9 /**< Shift value for SYSCFG_FPDZC */
+#define _SYSCFG_IF_FPDZC_MASK 0x200UL /**< Bit mask for SYSCFG_FPDZC */
+#define _SYSCFG_IF_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */
+#define SYSCFG_IF_FPDZC_DEFAULT (_SYSCFG_IF_FPDZC_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_IF */
+#define SYSCFG_IF_FPUFC (0x1UL << 10) /**< FPU Underflow interrupt flag */
+#define _SYSCFG_IF_FPUFC_SHIFT 10 /**< Shift value for SYSCFG_FPUFC */
+#define _SYSCFG_IF_FPUFC_MASK 0x400UL /**< Bit mask for SYSCFG_FPUFC */
+#define _SYSCFG_IF_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */
+#define SYSCFG_IF_FPUFC_DEFAULT (_SYSCFG_IF_FPUFC_DEFAULT << 10) /**< Shifted mode DEFAULT for SYSCFG_IF */
+#define SYSCFG_IF_FPOFC (0x1UL << 11) /**< FPU Overflow interrupt flag */
+#define _SYSCFG_IF_FPOFC_SHIFT 11 /**< Shift value for SYSCFG_FPOFC */
+#define _SYSCFG_IF_FPOFC_MASK 0x800UL /**< Bit mask for SYSCFG_FPOFC */
+#define _SYSCFG_IF_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */
+#define SYSCFG_IF_FPOFC_DEFAULT (_SYSCFG_IF_FPOFC_DEFAULT << 11) /**< Shifted mode DEFAULT for SYSCFG_IF */
+#define SYSCFG_IF_FPIDC (0x1UL << 12) /**< FPU Input denormal interrupt flag */
+#define _SYSCFG_IF_FPIDC_SHIFT 12 /**< Shift value for SYSCFG_FPIDC */
+#define _SYSCFG_IF_FPIDC_MASK 0x1000UL /**< Bit mask for SYSCFG_FPIDC */
+#define _SYSCFG_IF_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */
+#define SYSCFG_IF_FPIDC_DEFAULT (_SYSCFG_IF_FPIDC_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_IF */
+#define SYSCFG_IF_FPIXC (0x1UL << 13) /**< FPU Inexact interrupt flag */
+#define _SYSCFG_IF_FPIXC_SHIFT 13 /**< Shift value for SYSCFG_FPIXC */
+#define _SYSCFG_IF_FPIXC_MASK 0x2000UL /**< Bit mask for SYSCFG_FPIXC */
+#define _SYSCFG_IF_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */
+#define SYSCFG_IF_FPIXC_DEFAULT (_SYSCFG_IF_FPIXC_DEFAULT << 13) /**< Shifted mode DEFAULT for SYSCFG_IF */
+#define SYSCFG_IF_HOST2SRWBUSERR (0x1UL << 16) /**< HOST2SRWBUSERRIF Interrupt Flag */
+#define _SYSCFG_IF_HOST2SRWBUSERR_SHIFT 16 /**< Shift value for SYSCFG_HOST2SRWBUSERR */
+#define _SYSCFG_IF_HOST2SRWBUSERR_MASK 0x10000UL /**< Bit mask for SYSCFG_HOST2SRWBUSERR */
+#define _SYSCFG_IF_HOST2SRWBUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */
+#define SYSCFG_IF_HOST2SRWBUSERR_DEFAULT (_SYSCFG_IF_HOST2SRWBUSERR_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_IF */
+#define SYSCFG_IF_SRW2HOSTBUSERR (0x1UL << 17) /**< SRW2HOSTBUSERRIF Interrupt Flag */
+#define _SYSCFG_IF_SRW2HOSTBUSERR_SHIFT 17 /**< Shift value for SYSCFG_SRW2HOSTBUSERR */
+#define _SYSCFG_IF_SRW2HOSTBUSERR_MASK 0x20000UL /**< Bit mask for SYSCFG_SRW2HOSTBUSERR */
+#define _SYSCFG_IF_SRW2HOSTBUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */
+#define SYSCFG_IF_SRW2HOSTBUSERR_DEFAULT (_SYSCFG_IF_SRW2HOSTBUSERR_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_IF */
+#define SYSCFG_IF_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM Error 1-bit Interrupt Flag */
+#define _SYSCFG_IF_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */
+#define _SYSCFG_IF_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */
+#define _SYSCFG_IF_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */
+#define SYSCFG_IF_SEQRAMERR1B_DEFAULT (_SYSCFG_IF_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IF */
+#define SYSCFG_IF_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM Error 2-bit Interrupt Flag */
+#define _SYSCFG_IF_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */
+#define _SYSCFG_IF_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */
+#define _SYSCFG_IF_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */
+#define SYSCFG_IF_SEQRAMERR2B_DEFAULT (_SYSCFG_IF_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IF */
+#define SYSCFG_IF_FRCRAMERR1B (0x1UL << 28) /**< FRCRAM Error 1-bit Interrupt Flag */
+#define _SYSCFG_IF_FRCRAMERR1B_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1B */
+#define _SYSCFG_IF_FRCRAMERR1B_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1B */
+#define _SYSCFG_IF_FRCRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */
+#define SYSCFG_IF_FRCRAMERR1B_DEFAULT (_SYSCFG_IF_FRCRAMERR1B_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IF */
+#define SYSCFG_IF_FRCRAMERR2B (0x1UL << 29) /**< FRCRAM Error 2-bit Interrupt Flag */
+#define _SYSCFG_IF_FRCRAMERR2B_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2B */
+#define _SYSCFG_IF_FRCRAMERR2B_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2B */
+#define _SYSCFG_IF_FRCRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */
+#define SYSCFG_IF_FRCRAMERR2B_DEFAULT (_SYSCFG_IF_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IF */
+
+/* Bit fields for SYSCFG IEN */
+#define _SYSCFG_IEN_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IEN */
+#define _SYSCFG_IEN_MASK 0x33033F0FUL /**< Mask for SYSCFG_IEN */
+#define SYSCFG_IEN_SW0 (0x1UL << 0) /**< Software Interrupt Enable */
+#define _SYSCFG_IEN_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */
+#define _SYSCFG_IEN_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */
+#define _SYSCFG_IEN_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */
+#define SYSCFG_IEN_SW0_DEFAULT (_SYSCFG_IEN_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IEN */
+#define SYSCFG_IEN_SW1 (0x1UL << 1) /**< Software Interrupt Enable */
+#define _SYSCFG_IEN_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */
+#define _SYSCFG_IEN_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */
+#define _SYSCFG_IEN_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */
+#define SYSCFG_IEN_SW1_DEFAULT (_SYSCFG_IEN_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IEN */
+#define SYSCFG_IEN_SW2 (0x1UL << 2) /**< Software Interrupt Enable */
+#define _SYSCFG_IEN_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */
+#define _SYSCFG_IEN_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */
+#define _SYSCFG_IEN_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */
+#define SYSCFG_IEN_SW2_DEFAULT (_SYSCFG_IEN_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IEN */
+#define SYSCFG_IEN_SW3 (0x1UL << 3) /**< Software Interrupt Enable */
+#define _SYSCFG_IEN_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */
+#define _SYSCFG_IEN_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */
+#define _SYSCFG_IEN_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */
+#define SYSCFG_IEN_SW3_DEFAULT (_SYSCFG_IEN_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IEN */
+#define SYSCFG_IEN_FPIOC (0x1UL << 8) /**< FPU Invalid Operation Interrupt Enable */
+#define _SYSCFG_IEN_FPIOC_SHIFT 8 /**< Shift value for SYSCFG_FPIOC */
+#define _SYSCFG_IEN_FPIOC_MASK 0x100UL /**< Bit mask for SYSCFG_FPIOC */
+#define _SYSCFG_IEN_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */
+#define SYSCFG_IEN_FPIOC_DEFAULT (_SYSCFG_IEN_FPIOC_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_IEN */
+#define SYSCFG_IEN_FPDZC (0x1UL << 9) /**< FPU Divide by zero Interrupt Enable */
+#define _SYSCFG_IEN_FPDZC_SHIFT 9 /**< Shift value for SYSCFG_FPDZC */
+#define _SYSCFG_IEN_FPDZC_MASK 0x200UL /**< Bit mask for SYSCFG_FPDZC */
+#define _SYSCFG_IEN_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */
+#define SYSCFG_IEN_FPDZC_DEFAULT (_SYSCFG_IEN_FPDZC_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_IEN */
+#define SYSCFG_IEN_FPUFC (0x1UL << 10) /**< FPU Underflow Interrupt Enable */
+#define _SYSCFG_IEN_FPUFC_SHIFT 10 /**< Shift value for SYSCFG_FPUFC */
+#define _SYSCFG_IEN_FPUFC_MASK 0x400UL /**< Bit mask for SYSCFG_FPUFC */
+#define _SYSCFG_IEN_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */
+#define SYSCFG_IEN_FPUFC_DEFAULT (_SYSCFG_IEN_FPUFC_DEFAULT << 10) /**< Shifted mode DEFAULT for SYSCFG_IEN */
+#define SYSCFG_IEN_FPOFC (0x1UL << 11) /**< FPU Overflow Interrupt Enable */
+#define _SYSCFG_IEN_FPOFC_SHIFT 11 /**< Shift value for SYSCFG_FPOFC */
+#define _SYSCFG_IEN_FPOFC_MASK 0x800UL /**< Bit mask for SYSCFG_FPOFC */
+#define _SYSCFG_IEN_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */
+#define SYSCFG_IEN_FPOFC_DEFAULT (_SYSCFG_IEN_FPOFC_DEFAULT << 11) /**< Shifted mode DEFAULT for SYSCFG_IEN */
+#define SYSCFG_IEN_FPIDC (0x1UL << 12) /**< FPU Input denormal Interrupt Enable */
+#define _SYSCFG_IEN_FPIDC_SHIFT 12 /**< Shift value for SYSCFG_FPIDC */
+#define _SYSCFG_IEN_FPIDC_MASK 0x1000UL /**< Bit mask for SYSCFG_FPIDC */
+#define _SYSCFG_IEN_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */
+#define SYSCFG_IEN_FPIDC_DEFAULT (_SYSCFG_IEN_FPIDC_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_IEN */
+#define SYSCFG_IEN_FPIXC (0x1UL << 13) /**< FPU Inexact Interrupt Enable */
+#define _SYSCFG_IEN_FPIXC_SHIFT 13 /**< Shift value for SYSCFG_FPIXC */
+#define _SYSCFG_IEN_FPIXC_MASK 0x2000UL /**< Bit mask for SYSCFG_FPIXC */
+#define _SYSCFG_IEN_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */
+#define SYSCFG_IEN_FPIXC_DEFAULT (_SYSCFG_IEN_FPIXC_DEFAULT << 13) /**< Shifted mode DEFAULT for SYSCFG_IEN */
+#define SYSCFG_IEN_HOST2SRWBUSERR (0x1UL << 16) /**< HOST2SRWBUSERRIEN Interrupt Enable */
+#define _SYSCFG_IEN_HOST2SRWBUSERR_SHIFT 16 /**< Shift value for SYSCFG_HOST2SRWBUSERR */
+#define _SYSCFG_IEN_HOST2SRWBUSERR_MASK 0x10000UL /**< Bit mask for SYSCFG_HOST2SRWBUSERR */
+#define _SYSCFG_IEN_HOST2SRWBUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */
+#define SYSCFG_IEN_HOST2SRWBUSERR_DEFAULT (_SYSCFG_IEN_HOST2SRWBUSERR_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_IEN */
+#define SYSCFG_IEN_SRW2HOSTBUSERR (0x1UL << 17) /**< SRW2HOSTBUSERRIEN Interrupt Enable */
+#define _SYSCFG_IEN_SRW2HOSTBUSERR_SHIFT 17 /**< Shift value for SYSCFG_SRW2HOSTBUSERR */
+#define _SYSCFG_IEN_SRW2HOSTBUSERR_MASK 0x20000UL /**< Bit mask for SYSCFG_SRW2HOSTBUSERR */
+#define _SYSCFG_IEN_SRW2HOSTBUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */
+#define SYSCFG_IEN_SRW2HOSTBUSERR_DEFAULT (_SYSCFG_IEN_SRW2HOSTBUSERR_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_IEN */
+#define SYSCFG_IEN_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM Error 1-bit Interrupt Enable */
+#define _SYSCFG_IEN_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */
+#define _SYSCFG_IEN_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */
+#define _SYSCFG_IEN_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */
+#define SYSCFG_IEN_SEQRAMERR1B_DEFAULT (_SYSCFG_IEN_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IEN */
+#define SYSCFG_IEN_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM Error 2-bit Interrupt Enable */
+#define _SYSCFG_IEN_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */
+#define _SYSCFG_IEN_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */
+#define _SYSCFG_IEN_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */
+#define SYSCFG_IEN_SEQRAMERR2B_DEFAULT (_SYSCFG_IEN_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IEN */
+#define SYSCFG_IEN_FRCRAMERR1B (0x1UL << 28) /**< FRCRAM Error 1-bit Interrupt Enable */
+#define _SYSCFG_IEN_FRCRAMERR1B_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1B */
+#define _SYSCFG_IEN_FRCRAMERR1B_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1B */
+#define _SYSCFG_IEN_FRCRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */
+#define SYSCFG_IEN_FRCRAMERR1B_DEFAULT (_SYSCFG_IEN_FRCRAMERR1B_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IEN */
+#define SYSCFG_IEN_FRCRAMERR2B (0x1UL << 29) /**< FRCRAM Error 2-bit Interrupt Enable */
+#define _SYSCFG_IEN_FRCRAMERR2B_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2B */
+#define _SYSCFG_IEN_FRCRAMERR2B_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2B */
+#define _SYSCFG_IEN_FRCRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */
+#define SYSCFG_IEN_FRCRAMERR2B_DEFAULT (_SYSCFG_IEN_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IEN */
+
+/* Bit fields for SYSCFG CHIPREVHW */
+#define _SYSCFG_CHIPREVHW_RESETVALUE 0x00000C01UL /**< Default value for SYSCFG_CHIPREVHW */
+#define _SYSCFG_CHIPREVHW_MASK 0xFF0FFFFFUL /**< Mask for SYSCFG_CHIPREVHW */
+#define _SYSCFG_CHIPREVHW_MAJOR_SHIFT 0 /**< Shift value for SYSCFG_MAJOR */
+#define _SYSCFG_CHIPREVHW_MAJOR_MASK 0x3FUL /**< Bit mask for SYSCFG_MAJOR */
+#define _SYSCFG_CHIPREVHW_MAJOR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */
+#define SYSCFG_CHIPREVHW_MAJOR_DEFAULT (_SYSCFG_CHIPREVHW_MAJOR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */
+#define _SYSCFG_CHIPREVHW_FAMILY_SHIFT 6 /**< Shift value for SYSCFG_FAMILY */
+#define _SYSCFG_CHIPREVHW_FAMILY_MASK 0xFC0UL /**< Bit mask for SYSCFG_FAMILY */
+#define _SYSCFG_CHIPREVHW_FAMILY_DEFAULT 0x00000030UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */
+#define SYSCFG_CHIPREVHW_FAMILY_DEFAULT (_SYSCFG_CHIPREVHW_FAMILY_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */
+#define _SYSCFG_CHIPREVHW_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */
+#define _SYSCFG_CHIPREVHW_MINOR_MASK 0xFF000UL /**< Bit mask for SYSCFG_MINOR */
+#define _SYSCFG_CHIPREVHW_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */
+#define SYSCFG_CHIPREVHW_MINOR_DEFAULT (_SYSCFG_CHIPREVHW_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */
+
+/* Bit fields for SYSCFG CHIPREV */
+#define _SYSCFG_CHIPREV_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CHIPREV */
+#define _SYSCFG_CHIPREV_MASK 0x000FFFFFUL /**< Mask for SYSCFG_CHIPREV */
+#define _SYSCFG_CHIPREV_MAJOR_SHIFT 0 /**< Shift value for SYSCFG_MAJOR */
+#define _SYSCFG_CHIPREV_MAJOR_MASK 0x3FUL /**< Bit mask for SYSCFG_MAJOR */
+#define _SYSCFG_CHIPREV_MAJOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */
+#define SYSCFG_CHIPREV_MAJOR_DEFAULT (_SYSCFG_CHIPREV_MAJOR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */
+#define _SYSCFG_CHIPREV_FAMILY_SHIFT 6 /**< Shift value for SYSCFG_FAMILY */
+#define _SYSCFG_CHIPREV_FAMILY_MASK 0xFC0UL /**< Bit mask for SYSCFG_FAMILY */
+#define _SYSCFG_CHIPREV_FAMILY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */
+#define SYSCFG_CHIPREV_FAMILY_DEFAULT (_SYSCFG_CHIPREV_FAMILY_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */
+#define _SYSCFG_CHIPREV_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */
+#define _SYSCFG_CHIPREV_MINOR_MASK 0xFF000UL /**< Bit mask for SYSCFG_MINOR */
+#define _SYSCFG_CHIPREV_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */
+#define SYSCFG_CHIPREV_MINOR_DEFAULT (_SYSCFG_CHIPREV_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */
+
+/* Bit fields for SYSCFG CFGSYSTIC */
+#define _SYSCFG_CFGSYSTIC_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CFGSYSTIC */
+#define _SYSCFG_CFGSYSTIC_MASK 0x00000001UL /**< Mask for SYSCFG_CFGSYSTIC */
+#define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN (0x1UL << 0) /**< SysTick External Clock Enable */
+#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_SHIFT 0 /**< Shift value for SYSCFG_SYSTICEXTCLKEN */
+#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK 0x1UL /**< Bit mask for SYSCFG_SYSTICEXTCLKEN */
+#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CFGSYSTIC */
+#define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT (_SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CFGSYSTIC */
+
+/* Bit fields for SYSCFG CTRL */
+#define _SYSCFG_CTRL_RESETVALUE 0x00000023UL /**< Default value for SYSCFG_CTRL */
+#define _SYSCFG_CTRL_MASK 0x00000023UL /**< Mask for SYSCFG_CTRL */
+#define SYSCFG_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enabl */
+#define _SYSCFG_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for SYSCFG_ADDRFAULTEN */
+#define _SYSCFG_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for SYSCFG_ADDRFAULTEN */
+#define _SYSCFG_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */
+#define SYSCFG_CTRL_ADDRFAULTEN_DEFAULT (_SYSCFG_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CTRL */
+#define SYSCFG_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Disabled Clkbus Bus Fault Enable */
+#define _SYSCFG_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for SYSCFG_CLKDISFAULTEN */
+#define _SYSCFG_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for SYSCFG_CLKDISFAULTEN */
+#define _SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */
+#define SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT (_SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_CTRL */
+#define SYSCFG_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two bit ECC error bus fault response ena */
+#define _SYSCFG_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for SYSCFG_RAMECCERRFAULTEN */
+#define _SYSCFG_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for SYSCFG_RAMECCERRFAULTEN */
+#define _SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */
+#define SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT (_SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for SYSCFG_CTRL */
+
+/* Bit fields for SYSCFG DMEM0RETNCTRL */
+#define _SYSCFG_DMEM0RETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_DMEM0RETNCTRL */
+#define _SYSCFG_DMEM0RETNCTRL_MASK 0x00007FFFUL /**< Mask for SYSCFG_DMEM0RETNCTRL */
+#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMRETNCTRL */
+#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_MASK 0x7FFFUL /**< Bit mask for SYSCFG_RAMRETNCTRL */
+#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0RETNCTRL */
+#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_DMEM0RETNCTRL */
+#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK15 0x00004000UL /**< Mode BLK15 for SYSCFG_DMEM0RETNCTRL */
+#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK14TO15 0x00006000UL /**< Mode BLK14TO15 for SYSCFG_DMEM0RETNCTRL */
+#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK13TO15 0x00007000UL /**< Mode BLK13TO15 for SYSCFG_DMEM0RETNCTRL */
+#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK12TO15 0x00007800UL /**< Mode BLK12TO15 for SYSCFG_DMEM0RETNCTRL */
+#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK11TO15 0x00007C00UL /**< Mode BLK11TO15 for SYSCFG_DMEM0RETNCTRL */
+#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK10TO15 0x00007E00UL /**< Mode BLK10TO15 for SYSCFG_DMEM0RETNCTRL */
+#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK9TO15 0x00007F00UL /**< Mode BLK9TO15 for SYSCFG_DMEM0RETNCTRL */
+#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK8TO15 0x00007F80UL /**< Mode BLK8TO15 for SYSCFG_DMEM0RETNCTRL */
+#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK7TO15 0x00007FC0UL /**< Mode BLK7TO15 for SYSCFG_DMEM0RETNCTRL */
+#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK6TO15 0x00007FE0UL /**< Mode BLK6TO15 for SYSCFG_DMEM0RETNCTRL */
+#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK5TO15 0x00007FF0UL /**< Mode BLK5TO15 for SYSCFG_DMEM0RETNCTRL */
+#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK4TO15 0x00007FF8UL /**< Mode BLK4TO15 for SYSCFG_DMEM0RETNCTRL */
+#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3TO15 0x00007FFCUL /**< Mode BLK3TO15 for SYSCFG_DMEM0RETNCTRL */
+#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO15 0x00007FFEUL /**< Mode BLK2TO15 for SYSCFG_DMEM0RETNCTRL */
+#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO15 0x00007FFFUL /**< Mode BLK1TO15 for SYSCFG_DMEM0RETNCTRL */
+#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0RETNCTRL*/
+#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_DMEM0RETNCTRL */
+#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK15 << 0) /**< Shifted mode BLK15 for SYSCFG_DMEM0RETNCTRL */
+#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK14TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK14TO15 << 0) /**< Shifted mode BLK14TO15 for SYSCFG_DMEM0RETNCTRL*/
+#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK13TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK13TO15 << 0) /**< Shifted mode BLK13TO15 for SYSCFG_DMEM0RETNCTRL*/
+#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK12TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK12TO15 << 0) /**< Shifted mode BLK12TO15 for SYSCFG_DMEM0RETNCTRL*/
+#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK11TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK11TO15 << 0) /**< Shifted mode BLK11TO15 for SYSCFG_DMEM0RETNCTRL*/
+#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK10TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK10TO15 << 0) /**< Shifted mode BLK10TO15 for SYSCFG_DMEM0RETNCTRL*/
+#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK9TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK9TO15 << 0) /**< Shifted mode BLK9TO15 for SYSCFG_DMEM0RETNCTRL*/
+#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK8TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK8TO15 << 0) /**< Shifted mode BLK8TO15 for SYSCFG_DMEM0RETNCTRL*/
+#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK7TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK7TO15 << 0) /**< Shifted mode BLK7TO15 for SYSCFG_DMEM0RETNCTRL*/
+#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK6TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK6TO15 << 0) /**< Shifted mode BLK6TO15 for SYSCFG_DMEM0RETNCTRL*/
+#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK5TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK5TO15 << 0) /**< Shifted mode BLK5TO15 for SYSCFG_DMEM0RETNCTRL*/
+#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK4TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK4TO15 << 0) /**< Shifted mode BLK4TO15 for SYSCFG_DMEM0RETNCTRL*/
+#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3TO15 << 0) /**< Shifted mode BLK3TO15 for SYSCFG_DMEM0RETNCTRL*/
+#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO15 << 0) /**< Shifted mode BLK2TO15 for SYSCFG_DMEM0RETNCTRL*/
+#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO15 << 0) /**< Shifted mode BLK1TO15 for SYSCFG_DMEM0RETNCTRL*/
+
+/* Bit fields for SYSCFG RAMBIASCONF */
+#define _SYSCFG_RAMBIASCONF_RESETVALUE 0x00000002UL /**< Default value for SYSCFG_RAMBIASCONF */
+#define _SYSCFG_RAMBIASCONF_MASK 0x0000000FUL /**< Mask for SYSCFG_RAMBIASCONF */
+#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMBIASCTRL */
+#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_MASK 0xFUL /**< Bit mask for SYSCFG_RAMBIASCTRL */
+#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT 0x00000002UL /**< Mode DEFAULT for SYSCFG_RAMBIASCONF */
+#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_No 0x00000000UL /**< Mode No for SYSCFG_RAMBIASCONF */
+#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 0x00000001UL /**< Mode VSB100 for SYSCFG_RAMBIASCONF */
+#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 0x00000002UL /**< Mode VSB200 for SYSCFG_RAMBIASCONF */
+#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 0x00000004UL /**< Mode VSB300 for SYSCFG_RAMBIASCONF */
+#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 0x00000008UL /**< Mode VSB400 for SYSCFG_RAMBIASCONF */
+#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RAMBIASCONF */
+#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_No (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_No << 0) /**< Shifted mode No for SYSCFG_RAMBIASCONF */
+#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 << 0) /**< Shifted mode VSB100 for SYSCFG_RAMBIASCONF */
+#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 << 0) /**< Shifted mode VSB200 for SYSCFG_RAMBIASCONF */
+#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 << 0) /**< Shifted mode VSB300 for SYSCFG_RAMBIASCONF */
+#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 << 0) /**< Shifted mode VSB400 for SYSCFG_RAMBIASCONF */
+
+/* Bit fields for SYSCFG RADIORAMRETNCTRL */
+#define _SYSCFG_RADIORAMRETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIORAMRETNCTRL */
+#define _SYSCFG_RADIORAMRETNCTRL_MASK 0x00000103UL /**< Mask for SYSCFG_RADIORAMRETNCTRL */
+#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMRETNCTRL */
+#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_MASK 0x3UL /**< Bit mask for SYSCFG_SEQRAMRETNCTRL */
+#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */
+#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */
+#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 0x00000001UL /**< Mode BLK0 for SYSCFG_RADIORAMRETNCTRL */
+#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 0x00000002UL /**< Mode BLK1 for SYSCFG_RADIORAMRETNCTRL */
+#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF 0x00000003UL /**< Mode ALLOFF for SYSCFG_RADIORAMRETNCTRL */
+#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/
+#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/
+#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 << 0) /**< Shifted mode BLK0 for SYSCFG_RADIORAMRETNCTRL*/
+#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 << 0) /**< Shifted mode BLK1 for SYSCFG_RADIORAMRETNCTRL*/
+#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF << 0) /**< Shifted mode ALLOFF for SYSCFG_RADIORAMRETNCTRL*/
+#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL (0x1UL << 8) /**< FRCRAM Retention Control */
+#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMRETNCTRL */
+#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMRETNCTRL */
+#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */
+#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */
+#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF 0x00000001UL /**< Mode ALLOFF for SYSCFG_RADIORAMRETNCTRL */
+#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/
+#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON << 8) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/
+#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF << 8) /**< Shifted mode ALLOFF for SYSCFG_RADIORAMRETNCTRL*/
+
+/* Bit fields for SYSCFG RADIOECCCTRL */
+#define _SYSCFG_RADIOECCCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIOECCCTRL */
+#define _SYSCFG_RADIOECCCTRL_MASK 0x00000303UL /**< Mask for SYSCFG_RADIOECCCTRL */
+#define SYSCFG_RADIOECCCTRL_SEQRAMECCEN (0x1UL << 0) /**< SEQRAM ECC Enable */
+#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCEN */
+#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_MASK 0x1UL /**< Bit mask for SYSCFG_SEQRAMECCEN */
+#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */
+#define SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/
+#define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN (0x1UL << 1) /**< SEQRAM ECC Error Writeback Enable */
+#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_SHIFT 1 /**< Shift value for SYSCFG_SEQRAMECCEWEN */
+#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_MASK 0x2UL /**< Bit mask for SYSCFG_SEQRAMECCEWEN */
+#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */
+#define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/
+#define SYSCFG_RADIOECCCTRL_FRCRAMECCEN (0x1UL << 8) /**< FRCRAM ECC Enable */
+#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMECCEN */
+#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMECCEN */
+#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */
+#define SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/
+#define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN (0x1UL << 9) /**< FRCRAM ECC Error Writeback Enable */
+#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_SHIFT 9 /**< Shift value for SYSCFG_FRCRAMECCEWEN */
+#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_MASK 0x200UL /**< Bit mask for SYSCFG_FRCRAMECCEWEN */
+#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */
+#define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/
+
+/* Bit fields for SYSCFG SEQRAMECCADDR */
+#define _SYSCFG_SEQRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_SEQRAMECCADDR */
+#define _SYSCFG_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_SEQRAMECCADDR */
+#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCADDR */
+#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_SEQRAMECCADDR */
+#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_SEQRAMECCADDR */
+#define SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT (_SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_SEQRAMECCADDR*/
+
+/* Bit fields for SYSCFG FRCRAMECCADDR */
+#define _SYSCFG_FRCRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_FRCRAMECCADDR */
+#define _SYSCFG_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_FRCRAMECCADDR */
+#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_FRCRAMECCADDR */
+#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_FRCRAMECCADDR */
+#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_FRCRAMECCADDR */
+#define SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT (_SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_FRCRAMECCADDR*/
+
+/* Bit fields for SYSCFG ICACHERAMRETNCTRL */
+#define _SYSCFG_ICACHERAMRETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ICACHERAMRETNCTRL */
+#define _SYSCFG_ICACHERAMRETNCTRL_MASK 0x00000001UL /**< Mask for SYSCFG_ICACHERAMRETNCTRL */
+#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL (0x1UL << 0) /**< ICACHERAM Retention control */
+#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMRETNCTRL */
+#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_MASK 0x1UL /**< Bit mask for SYSCFG_RAMRETNCTRL */
+#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ICACHERAMRETNCTRL */
+#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_ICACHERAMRETNCTRL */
+#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF 0x00000001UL /**< Mode ALLOFF for SYSCFG_ICACHERAMRETNCTRL */
+#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ICACHERAMRETNCTRL*/
+#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_ICACHERAMRETNCTRL*/
+#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF << 0) /**< Shifted mode ALLOFF for SYSCFG_ICACHERAMRETNCTRL*/
+
+/* Bit fields for SYSCFG DMEM0PORTMAPSEL */
+#define _SYSCFG_DMEM0PORTMAPSEL_RESETVALUE 0x00007905UL /**< Default value for SYSCFG_DMEM0PORTMAPSEL */
+#define _SYSCFG_DMEM0PORTMAPSEL_MASK 0x0000FFFFUL /**< Mask for SYSCFG_DMEM0PORTMAPSEL */
+#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_SHIFT 0 /**< Shift value for SYSCFG_LDMAPORTSEL */
+#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_MASK 0x3UL /**< Bit mask for SYSCFG_LDMAPORTSEL */
+#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */
+#define SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/
+#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_SHIFT 2 /**< Shift value for SYSCFG_SRWAESPORTSEL */
+#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_MASK 0xCUL /**< Bit mask for SYSCFG_SRWAESPORTSEL */
+#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */
+#define SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/
+#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_SHIFT 4 /**< Shift value for SYSCFG_AHBSRWPORTSEL */
+#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_MASK 0x30UL /**< Bit mask for SYSCFG_AHBSRWPORTSEL */
+#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */
+#define SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/
+#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_SHIFT 6 /**< Shift value for SYSCFG_SRWECA0PORTSEL */
+#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_MASK 0xC0UL /**< Bit mask for SYSCFG_SRWECA0PORTSEL */
+#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */
+#define SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/
+#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_SHIFT 8 /**< Shift value for SYSCFG_SRWECA1PORTSEL */
+#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_MASK 0x300UL /**< Bit mask for SYSCFG_SRWECA1PORTSEL */
+#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */
+#define SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/
+#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_SHIFT 10 /**< Shift value for SYSCFG_MVPAHBDATA0PORTSEL */
+#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_MASK 0xC00UL /**< Bit mask for SYSCFG_MVPAHBDATA0PORTSEL */
+#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */
+#define SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/
+#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_SHIFT 12 /**< Shift value for SYSCFG_MVPAHBDATA1PORTSEL */
+#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_MASK 0x3000UL /**< Bit mask for SYSCFG_MVPAHBDATA1PORTSEL */
+#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */
+#define SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/
+#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_SHIFT 14 /**< Shift value for SYSCFG_MVPAHBDATA2PORTSEL */
+#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_MASK 0xC000UL /**< Bit mask for SYSCFG_MVPAHBDATA2PORTSEL */
+#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */
+#define SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_DEFAULT << 14) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/
+
+/* Bit fields for SYSCFG ROOTDATA0 */
+#define _SYSCFG_ROOTDATA0_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTDATA0 */
+#define _SYSCFG_ROOTDATA0_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTDATA0 */
+#define _SYSCFG_ROOTDATA0_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */
+#define _SYSCFG_ROOTDATA0_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */
+#define _SYSCFG_ROOTDATA0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTDATA0 */
+#define SYSCFG_ROOTDATA0_DATA_DEFAULT (_SYSCFG_ROOTDATA0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTDATA0 */
+
+/* Bit fields for SYSCFG ROOTDATA1 */
+#define _SYSCFG_ROOTDATA1_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTDATA1 */
+#define _SYSCFG_ROOTDATA1_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTDATA1 */
+#define _SYSCFG_ROOTDATA1_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */
+#define _SYSCFG_ROOTDATA1_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */
+#define _SYSCFG_ROOTDATA1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTDATA1 */
+#define SYSCFG_ROOTDATA1_DATA_DEFAULT (_SYSCFG_ROOTDATA1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTDATA1 */
+
+/* Bit fields for SYSCFG ROOTLOCKSTATUS */
+#define _SYSCFG_ROOTLOCKSTATUS_RESETVALUE 0x007F0107UL /**< Default value for SYSCFG_ROOTLOCKSTATUS */
+#define _SYSCFG_ROOTLOCKSTATUS_MASK 0x807F0107UL /**< Mask for SYSCFG_ROOTLOCKSTATUS */
+#define SYSCFG_ROOTLOCKSTATUS_BUSLOCK (0x1UL << 0) /**< Bus Lock */
+#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_SHIFT 0 /**< Shift value for SYSCFG_BUSLOCK */
+#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_MASK 0x1UL /**< Bit mask for SYSCFG_BUSLOCK */
+#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */
+#define SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/
+#define SYSCFG_ROOTLOCKSTATUS_REGLOCK (0x1UL << 1) /**< Register Lock */
+#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_SHIFT 1 /**< Shift value for SYSCFG_REGLOCK */
+#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_MASK 0x2UL /**< Bit mask for SYSCFG_REGLOCK */
+#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */
+#define SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/
+#define SYSCFG_ROOTLOCKSTATUS_MFRLOCK (0x1UL << 2) /**< Manufacture Lock */
+#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_SHIFT 2 /**< Shift value for SYSCFG_MFRLOCK */
+#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_MASK 0x4UL /**< Bit mask for SYSCFG_MFRLOCK */
+#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */
+#define SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/
+#define SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK (0x1UL << 8) /**< Root Debug Lock */
+#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_SHIFT 8 /**< Shift value for SYSCFG_ROOTDBGLOCK */
+#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_MASK 0x100UL /**< Bit mask for SYSCFG_ROOTDBGLOCK */
+#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */
+#define SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/
+#define SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK (0x1UL << 16) /**< User Debug Access Port Lock */
+#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_SHIFT 16 /**< Shift value for SYSCFG_USERDBGAPLOCK */
+#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_MASK 0x10000UL /**< Bit mask for SYSCFG_USERDBGAPLOCK */
+#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */
+#define SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/
+#define SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK (0x1UL << 17) /**< User Invasive Debug Lock */
+#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_SHIFT 17 /**< Shift value for SYSCFG_USERDBGLOCK */
+#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_MASK 0x20000UL /**< Bit mask for SYSCFG_USERDBGLOCK */
+#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */
+#define SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/
+#define SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK (0x1UL << 18) /**< User Non-invasive Debug Lock */
+#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_SHIFT 18 /**< Shift value for SYSCFG_USERNIDLOCK */
+#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_MASK 0x40000UL /**< Bit mask for SYSCFG_USERNIDLOCK */
+#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */
+#define SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/
+#define SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK (0x1UL << 19) /**< User Secure Invasive Debug Lock */
+#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_SHIFT 19 /**< Shift value for SYSCFG_USERSPIDLOCK */
+#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_MASK 0x80000UL /**< Bit mask for SYSCFG_USERSPIDLOCK */
+#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */
+#define SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/
+#define SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK (0x1UL << 20) /**< User Secure Non-invasive Debug Lock */
+#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_SHIFT 20 /**< Shift value for SYSCFG_USERSPNIDLOCK */
+#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_MASK 0x100000UL /**< Bit mask for SYSCFG_USERSPNIDLOCK */
+#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */
+#define SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/
+#define SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK (0x1UL << 21) /**< Radio Invasive Debug Lock */
+#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_SHIFT 21 /**< Shift value for SYSCFG_RADIOIDBGLOCK */
+#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_MASK 0x200000UL /**< Bit mask for SYSCFG_RADIOIDBGLOCK */
+#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */
+#define SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/
+#define SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK (0x1UL << 22) /**< Radio Non-invasive Debug Lock */
+#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_SHIFT 22 /**< Shift value for SYSCFG_RADIONIDBGLOCK */
+#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_MASK 0x400000UL /**< Bit mask for SYSCFG_RADIONIDBGLOCK */
+#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */
+#define SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/
+#define SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED (0x1UL << 31) /**< E-Fuse Unlocked */
+#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_SHIFT 31 /**< Shift value for SYSCFG_EFUSEUNLOCKED */
+#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_MASK 0x80000000UL /**< Bit mask for SYSCFG_EFUSEUNLOCKED */
+#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */
+#define SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT << 31) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/
+
+/* Bit fields for SYSCFG ROOTSESWVERSION */
+#define _SYSCFG_ROOTSESWVERSION_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTSESWVERSION */
+#define _SYSCFG_ROOTSESWVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTSESWVERSION */
+#define _SYSCFG_ROOTSESWVERSION_SWVERSION_SHIFT 0 /**< Shift value for SYSCFG_SWVERSION */
+#define _SYSCFG_ROOTSESWVERSION_SWVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_SWVERSION */
+#define _SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTSESWVERSION */
+#define SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT (_SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTSESWVERSION*/
+
+/** @} End of group EFR32MG24_SYSCFG_BitFields */
+/** @} End of group EFR32MG24_SYSCFG */
+/**************************************************************************//**
+ * @defgroup EFR32MG24_SYSCFG_CFGNS SYSCFG_CFGNS
+ * @{
+ * @brief EFR32MG24 SYSCFG_CFGNS Register Declaration.
+ *****************************************************************************/
+
+/** SYSCFG_CFGNS Register Declaration. */
+typedef struct {
+ uint32_t RESERVED0[7U]; /**< Reserved for future use */
+ __IOM uint32_t CFGNSTCALIB; /**< Configure Non-Secure Sys-Tick cal. */
+ uint32_t RESERVED1[376U]; /**< Reserved for future use */
+ __IOM uint32_t ROOTNSDATA0; /**< Data Register 0 */
+ __IOM uint32_t ROOTNSDATA1; /**< Data Register 1 */
+ uint32_t RESERVED2[1U]; /**< Reserved for future use */
+ uint32_t RESERVED3[637U]; /**< Reserved for future use */
+ uint32_t RESERVED4[7U]; /**< Reserved for future use */
+ __IOM uint32_t CFGNSTCALIB_SET; /**< Configure Non-Secure Sys-Tick cal. */
+ uint32_t RESERVED5[376U]; /**< Reserved for future use */
+ __IOM uint32_t ROOTNSDATA0_SET; /**< Data Register 0 */
+ __IOM uint32_t ROOTNSDATA1_SET; /**< Data Register 1 */
+ uint32_t RESERVED6[1U]; /**< Reserved for future use */
+ uint32_t RESERVED7[637U]; /**< Reserved for future use */
+ uint32_t RESERVED8[7U]; /**< Reserved for future use */
+ __IOM uint32_t CFGNSTCALIB_CLR; /**< Configure Non-Secure Sys-Tick cal. */
+ uint32_t RESERVED9[376U]; /**< Reserved for future use */
+ __IOM uint32_t ROOTNSDATA0_CLR; /**< Data Register 0 */
+ __IOM uint32_t ROOTNSDATA1_CLR; /**< Data Register 1 */
+ uint32_t RESERVED10[1U]; /**< Reserved for future use */
+ uint32_t RESERVED11[637U]; /**< Reserved for future use */
+ uint32_t RESERVED12[7U]; /**< Reserved for future use */
+ __IOM uint32_t CFGNSTCALIB_TGL; /**< Configure Non-Secure Sys-Tick cal. */
+ uint32_t RESERVED13[376U]; /**< Reserved for future use */
+ __IOM uint32_t ROOTNSDATA0_TGL; /**< Data Register 0 */
+ __IOM uint32_t ROOTNSDATA1_TGL; /**< Data Register 1 */
+ uint32_t RESERVED14[1U]; /**< Reserved for future use */
+} SYSCFG_CFGNS_TypeDef;
+/** @} End of group EFR32MG24_SYSCFG_CFGNS */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_SYSCFG_CFGNS
+ * @{
+ * @defgroup EFR32MG24_SYSCFG_CFGNS_BitFields SYSCFG_CFGNS Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for SYSCFG CFGNSTCALIB */
+#define _SYSCFG_CFGNSTCALIB_RESETVALUE 0x01004A37UL /**< Default value for SYSCFG_CFGNSTCALIB */
+#define _SYSCFG_CFGNSTCALIB_MASK 0x03FFFFFFUL /**< Mask for SYSCFG_CFGNSTCALIB */
+#define _SYSCFG_CFGNSTCALIB_TENMS_SHIFT 0 /**< Shift value for SYSCFG_TENMS */
+#define _SYSCFG_CFGNSTCALIB_TENMS_MASK 0xFFFFFFUL /**< Bit mask for SYSCFG_TENMS */
+#define _SYSCFG_CFGNSTCALIB_TENMS_DEFAULT 0x00004A37UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */
+#define SYSCFG_CFGNSTCALIB_TENMS_DEFAULT (_SYSCFG_CFGNSTCALIB_TENMS_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */
+#define SYSCFG_CFGNSTCALIB_SKEW (0x1UL << 24) /**< Skew */
+#define _SYSCFG_CFGNSTCALIB_SKEW_SHIFT 24 /**< Shift value for SYSCFG_SKEW */
+#define _SYSCFG_CFGNSTCALIB_SKEW_MASK 0x1000000UL /**< Bit mask for SYSCFG_SKEW */
+#define _SYSCFG_CFGNSTCALIB_SKEW_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */
+#define SYSCFG_CFGNSTCALIB_SKEW_DEFAULT (_SYSCFG_CFGNSTCALIB_SKEW_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */
+#define SYSCFG_CFGNSTCALIB_NOREF (0x1UL << 25) /**< No Reference */
+#define _SYSCFG_CFGNSTCALIB_NOREF_SHIFT 25 /**< Shift value for SYSCFG_NOREF */
+#define _SYSCFG_CFGNSTCALIB_NOREF_MASK 0x2000000UL /**< Bit mask for SYSCFG_NOREF */
+#define _SYSCFG_CFGNSTCALIB_NOREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */
+#define _SYSCFG_CFGNSTCALIB_NOREF_REF 0x00000000UL /**< Mode REF for SYSCFG_CFGNSTCALIB */
+#define _SYSCFG_CFGNSTCALIB_NOREF_NOREF 0x00000001UL /**< Mode NOREF for SYSCFG_CFGNSTCALIB */
+#define SYSCFG_CFGNSTCALIB_NOREF_DEFAULT (_SYSCFG_CFGNSTCALIB_NOREF_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */
+#define SYSCFG_CFGNSTCALIB_NOREF_REF (_SYSCFG_CFGNSTCALIB_NOREF_REF << 25) /**< Shifted mode REF for SYSCFG_CFGNSTCALIB */
+#define SYSCFG_CFGNSTCALIB_NOREF_NOREF (_SYSCFG_CFGNSTCALIB_NOREF_NOREF << 25) /**< Shifted mode NOREF for SYSCFG_CFGNSTCALIB */
+
+/* Bit fields for SYSCFG ROOTNSDATA0 */
+#define _SYSCFG_ROOTNSDATA0_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTNSDATA0 */
+#define _SYSCFG_ROOTNSDATA0_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTNSDATA0 */
+#define _SYSCFG_ROOTNSDATA0_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */
+#define _SYSCFG_ROOTNSDATA0_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */
+#define _SYSCFG_ROOTNSDATA0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTNSDATA0 */
+#define SYSCFG_ROOTNSDATA0_DATA_DEFAULT (_SYSCFG_ROOTNSDATA0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTNSDATA0 */
+
+/* Bit fields for SYSCFG ROOTNSDATA1 */
+#define _SYSCFG_ROOTNSDATA1_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTNSDATA1 */
+#define _SYSCFG_ROOTNSDATA1_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTNSDATA1 */
+#define _SYSCFG_ROOTNSDATA1_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */
+#define _SYSCFG_ROOTNSDATA1_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */
+#define _SYSCFG_ROOTNSDATA1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTNSDATA1 */
+#define SYSCFG_ROOTNSDATA1_DATA_DEFAULT (_SYSCFG_ROOTNSDATA1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTNSDATA1 */
+
+/** @} End of group EFR32MG24_SYSCFG_CFGNS_BitFields */
+/** @} End of group EFR32MG24_SYSCFG_CFGNS */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_SYSCFG_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_sysrtc.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_sysrtc.h
new file mode 100644
index 00000000..797abf8b
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_sysrtc.h
@@ -0,0 +1,421 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 SYSRTC register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_SYSRTC_H
+#define EFR32MG24_SYSRTC_H
+#define SYSRTC_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_SYSRTC SYSRTC
+ * @{
+ * @brief EFR32MG24 SYSRTC Register Declaration.
+ *****************************************************************************/
+
+/** SYSRTC Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IP VERSION */
+ __IOM uint32_t EN; /**< Module Enable Register */
+ __IOM uint32_t SWRST; /**< Software Reset Register */
+ __IOM uint32_t CFG; /**< Configuration Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IM uint32_t STATUS; /**< Status register */
+ __IOM uint32_t CNT; /**< Counter Value Register */
+ __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
+ __IOM uint32_t LOCK; /**< Configuration Lock Register */
+ uint32_t RESERVED0[3U]; /**< Reserved for future use */
+ uint32_t RESERVED1[1U]; /**< Reserved for future use */
+ uint32_t RESERVED2[3U]; /**< Reserved for future use */
+ __IOM uint32_t GRP0_IF; /**< Group Interrupt Flags */
+ __IOM uint32_t GRP0_IEN; /**< Group Interrupt Enables */
+ __IOM uint32_t GRP0_CTRL; /**< Group Control Register */
+ __IOM uint32_t GRP0_CMP0VALUE; /**< Compare 0 Value Register */
+ __IOM uint32_t GRP0_CMP1VALUE; /**< Compare 1 Value Register */
+ __IM uint32_t GRP0_CAP0VALUE; /**< Capture 0 Value Register */
+ __IM uint32_t GRP0_SYNCBUSY; /**< Synchronization busy Register */
+ uint32_t RESERVED3[1U]; /**< Reserved for future use */
+ uint32_t RESERVED4[1U]; /**< Reserved for future use */
+ uint32_t RESERVED5[7U]; /**< Reserved for future use */
+ uint32_t RESERVED6[1U]; /**< Reserved for future use */
+ uint32_t RESERVED7[991U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP VERSION */
+ __IOM uint32_t EN_SET; /**< Module Enable Register */
+ __IOM uint32_t SWRST_SET; /**< Software Reset Register */
+ __IOM uint32_t CFG_SET; /**< Configuration Register */
+ __IOM uint32_t CMD_SET; /**< Command Register */
+ __IM uint32_t STATUS_SET; /**< Status register */
+ __IOM uint32_t CNT_SET; /**< Counter Value Register */
+ __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */
+ __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */
+ uint32_t RESERVED8[3U]; /**< Reserved for future use */
+ uint32_t RESERVED9[1U]; /**< Reserved for future use */
+ uint32_t RESERVED10[3U]; /**< Reserved for future use */
+ __IOM uint32_t GRP0_IF_SET; /**< Group Interrupt Flags */
+ __IOM uint32_t GRP0_IEN_SET; /**< Group Interrupt Enables */
+ __IOM uint32_t GRP0_CTRL_SET; /**< Group Control Register */
+ __IOM uint32_t GRP0_CMP0VALUE_SET; /**< Compare 0 Value Register */
+ __IOM uint32_t GRP0_CMP1VALUE_SET; /**< Compare 1 Value Register */
+ __IM uint32_t GRP0_CAP0VALUE_SET; /**< Capture 0 Value Register */
+ __IM uint32_t GRP0_SYNCBUSY_SET; /**< Synchronization busy Register */
+ uint32_t RESERVED11[1U]; /**< Reserved for future use */
+ uint32_t RESERVED12[1U]; /**< Reserved for future use */
+ uint32_t RESERVED13[7U]; /**< Reserved for future use */
+ uint32_t RESERVED14[1U]; /**< Reserved for future use */
+ uint32_t RESERVED15[991U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP VERSION */
+ __IOM uint32_t EN_CLR; /**< Module Enable Register */
+ __IOM uint32_t SWRST_CLR; /**< Software Reset Register */
+ __IOM uint32_t CFG_CLR; /**< Configuration Register */
+ __IOM uint32_t CMD_CLR; /**< Command Register */
+ __IM uint32_t STATUS_CLR; /**< Status register */
+ __IOM uint32_t CNT_CLR; /**< Counter Value Register */
+ __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */
+ __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */
+ uint32_t RESERVED16[3U]; /**< Reserved for future use */
+ uint32_t RESERVED17[1U]; /**< Reserved for future use */
+ uint32_t RESERVED18[3U]; /**< Reserved for future use */
+ __IOM uint32_t GRP0_IF_CLR; /**< Group Interrupt Flags */
+ __IOM uint32_t GRP0_IEN_CLR; /**< Group Interrupt Enables */
+ __IOM uint32_t GRP0_CTRL_CLR; /**< Group Control Register */
+ __IOM uint32_t GRP0_CMP0VALUE_CLR; /**< Compare 0 Value Register */
+ __IOM uint32_t GRP0_CMP1VALUE_CLR; /**< Compare 1 Value Register */
+ __IM uint32_t GRP0_CAP0VALUE_CLR; /**< Capture 0 Value Register */
+ __IM uint32_t GRP0_SYNCBUSY_CLR; /**< Synchronization busy Register */
+ uint32_t RESERVED19[1U]; /**< Reserved for future use */
+ uint32_t RESERVED20[1U]; /**< Reserved for future use */
+ uint32_t RESERVED21[7U]; /**< Reserved for future use */
+ uint32_t RESERVED22[1U]; /**< Reserved for future use */
+ uint32_t RESERVED23[991U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP VERSION */
+ __IOM uint32_t EN_TGL; /**< Module Enable Register */
+ __IOM uint32_t SWRST_TGL; /**< Software Reset Register */
+ __IOM uint32_t CFG_TGL; /**< Configuration Register */
+ __IOM uint32_t CMD_TGL; /**< Command Register */
+ __IM uint32_t STATUS_TGL; /**< Status register */
+ __IOM uint32_t CNT_TGL; /**< Counter Value Register */
+ __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */
+ __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */
+ uint32_t RESERVED24[3U]; /**< Reserved for future use */
+ uint32_t RESERVED25[1U]; /**< Reserved for future use */
+ uint32_t RESERVED26[3U]; /**< Reserved for future use */
+ __IOM uint32_t GRP0_IF_TGL; /**< Group Interrupt Flags */
+ __IOM uint32_t GRP0_IEN_TGL; /**< Group Interrupt Enables */
+ __IOM uint32_t GRP0_CTRL_TGL; /**< Group Control Register */
+ __IOM uint32_t GRP0_CMP0VALUE_TGL; /**< Compare 0 Value Register */
+ __IOM uint32_t GRP0_CMP1VALUE_TGL; /**< Compare 1 Value Register */
+ __IM uint32_t GRP0_CAP0VALUE_TGL; /**< Capture 0 Value Register */
+ __IM uint32_t GRP0_SYNCBUSY_TGL; /**< Synchronization busy Register */
+ uint32_t RESERVED27[1U]; /**< Reserved for future use */
+ uint32_t RESERVED28[1U]; /**< Reserved for future use */
+ uint32_t RESERVED29[7U]; /**< Reserved for future use */
+ uint32_t RESERVED30[1U]; /**< Reserved for future use */
+} SYSRTC_TypeDef;
+/** @} End of group EFR32MG24_SYSRTC */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_SYSRTC
+ * @{
+ * @defgroup EFR32MG24_SYSRTC_BitFields SYSRTC Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for SYSRTC IPVERSION */
+#define _SYSRTC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for SYSRTC_IPVERSION */
+#define _SYSRTC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_IPVERSION */
+#define _SYSRTC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SYSRTC_IPVERSION */
+#define _SYSRTC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_IPVERSION */
+#define _SYSRTC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSRTC_IPVERSION */
+#define SYSRTC_IPVERSION_IPVERSION_DEFAULT (_SYSRTC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_IPVERSION */
+
+/* Bit fields for SYSRTC EN */
+#define _SYSRTC_EN_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_EN */
+#define _SYSRTC_EN_MASK 0x00000003UL /**< Mask for SYSRTC_EN */
+#define SYSRTC_EN_EN (0x1UL << 0) /**< SYSRTC Enable */
+#define _SYSRTC_EN_EN_SHIFT 0 /**< Shift value for SYSRTC_EN */
+#define _SYSRTC_EN_EN_MASK 0x1UL /**< Bit mask for SYSRTC_EN */
+#define _SYSRTC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_EN */
+#define SYSRTC_EN_EN_DEFAULT (_SYSRTC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_EN */
+#define SYSRTC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */
+#define _SYSRTC_EN_DISABLING_SHIFT 1 /**< Shift value for SYSRTC_DISABLING */
+#define _SYSRTC_EN_DISABLING_MASK 0x2UL /**< Bit mask for SYSRTC_DISABLING */
+#define _SYSRTC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_EN */
+#define SYSRTC_EN_DISABLING_DEFAULT (_SYSRTC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_EN */
+
+/* Bit fields for SYSRTC SWRST */
+#define _SYSRTC_SWRST_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_SWRST */
+#define _SYSRTC_SWRST_MASK 0x00000003UL /**< Mask for SYSRTC_SWRST */
+#define SYSRTC_SWRST_SWRST (0x1UL << 0) /**< Software reset command */
+#define _SYSRTC_SWRST_SWRST_SHIFT 0 /**< Shift value for SYSRTC_SWRST */
+#define _SYSRTC_SWRST_SWRST_MASK 0x1UL /**< Bit mask for SYSRTC_SWRST */
+#define _SYSRTC_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SWRST */
+#define SYSRTC_SWRST_SWRST_DEFAULT (_SYSRTC_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_SWRST */
+#define SYSRTC_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */
+#define _SYSRTC_SWRST_RESETTING_SHIFT 1 /**< Shift value for SYSRTC_RESETTING */
+#define _SYSRTC_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for SYSRTC_RESETTING */
+#define _SYSRTC_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SWRST */
+#define SYSRTC_SWRST_RESETTING_DEFAULT (_SYSRTC_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_SWRST */
+
+/* Bit fields for SYSRTC CFG */
+#define _SYSRTC_CFG_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CFG */
+#define _SYSRTC_CFG_MASK 0x00000001UL /**< Mask for SYSRTC_CFG */
+#define SYSRTC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */
+#define _SYSRTC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for SYSRTC_DEBUGRUN */
+#define _SYSRTC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for SYSRTC_DEBUGRUN */
+#define _SYSRTC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CFG */
+#define _SYSRTC_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for SYSRTC_CFG */
+#define _SYSRTC_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for SYSRTC_CFG */
+#define SYSRTC_CFG_DEBUGRUN_DEFAULT (_SYSRTC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CFG */
+#define SYSRTC_CFG_DEBUGRUN_DISABLE (_SYSRTC_CFG_DEBUGRUN_DISABLE << 0) /**< Shifted mode DISABLE for SYSRTC_CFG */
+#define SYSRTC_CFG_DEBUGRUN_ENABLE (_SYSRTC_CFG_DEBUGRUN_ENABLE << 0) /**< Shifted mode ENABLE for SYSRTC_CFG */
+
+/* Bit fields for SYSRTC CMD */
+#define _SYSRTC_CMD_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CMD */
+#define _SYSRTC_CMD_MASK 0x00000003UL /**< Mask for SYSRTC_CMD */
+#define SYSRTC_CMD_START (0x1UL << 0) /**< Start SYSRTC */
+#define _SYSRTC_CMD_START_SHIFT 0 /**< Shift value for SYSRTC_START */
+#define _SYSRTC_CMD_START_MASK 0x1UL /**< Bit mask for SYSRTC_START */
+#define _SYSRTC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CMD */
+#define SYSRTC_CMD_START_DEFAULT (_SYSRTC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CMD */
+#define SYSRTC_CMD_STOP (0x1UL << 1) /**< Stop SYSRTC */
+#define _SYSRTC_CMD_STOP_SHIFT 1 /**< Shift value for SYSRTC_STOP */
+#define _SYSRTC_CMD_STOP_MASK 0x2UL /**< Bit mask for SYSRTC_STOP */
+#define _SYSRTC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CMD */
+#define SYSRTC_CMD_STOP_DEFAULT (_SYSRTC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_CMD */
+
+/* Bit fields for SYSRTC STATUS */
+#define _SYSRTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_STATUS */
+#define _SYSRTC_STATUS_MASK 0x00000007UL /**< Mask for SYSRTC_STATUS */
+#define SYSRTC_STATUS_RUNNING (0x1UL << 0) /**< SYSRTC running status */
+#define _SYSRTC_STATUS_RUNNING_SHIFT 0 /**< Shift value for SYSRTC_RUNNING */
+#define _SYSRTC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for SYSRTC_RUNNING */
+#define _SYSRTC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_STATUS */
+#define SYSRTC_STATUS_RUNNING_DEFAULT (_SYSRTC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_STATUS */
+#define SYSRTC_STATUS_LOCKSTATUS (0x1UL << 1) /**< Lock Status */
+#define _SYSRTC_STATUS_LOCKSTATUS_SHIFT 1 /**< Shift value for SYSRTC_LOCKSTATUS */
+#define _SYSRTC_STATUS_LOCKSTATUS_MASK 0x2UL /**< Bit mask for SYSRTC_LOCKSTATUS */
+#define _SYSRTC_STATUS_LOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_STATUS */
+#define _SYSRTC_STATUS_LOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SYSRTC_STATUS */
+#define _SYSRTC_STATUS_LOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for SYSRTC_STATUS */
+#define SYSRTC_STATUS_LOCKSTATUS_DEFAULT (_SYSRTC_STATUS_LOCKSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_STATUS */
+#define SYSRTC_STATUS_LOCKSTATUS_UNLOCKED (_SYSRTC_STATUS_LOCKSTATUS_UNLOCKED << 1) /**< Shifted mode UNLOCKED for SYSRTC_STATUS */
+#define SYSRTC_STATUS_LOCKSTATUS_LOCKED (_SYSRTC_STATUS_LOCKSTATUS_LOCKED << 1) /**< Shifted mode LOCKED for SYSRTC_STATUS */
+
+/* Bit fields for SYSRTC CNT */
+#define _SYSRTC_CNT_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CNT */
+#define _SYSRTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_CNT */
+#define _SYSRTC_CNT_CNT_SHIFT 0 /**< Shift value for SYSRTC_CNT */
+#define _SYSRTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CNT */
+#define _SYSRTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CNT */
+#define SYSRTC_CNT_CNT_DEFAULT (_SYSRTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CNT */
+
+/* Bit fields for SYSRTC SYNCBUSY */
+#define _SYSRTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_SYNCBUSY */
+#define _SYSRTC_SYNCBUSY_MASK 0x0000000FUL /**< Mask for SYSRTC_SYNCBUSY */
+#define SYSRTC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START bitfield */
+#define _SYSRTC_SYNCBUSY_START_SHIFT 0 /**< Shift value for SYSRTC_START */
+#define _SYSRTC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for SYSRTC_START */
+#define _SYSRTC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */
+#define SYSRTC_SYNCBUSY_START_DEFAULT (_SYSRTC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */
+#define SYSRTC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP bitfield */
+#define _SYSRTC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for SYSRTC_STOP */
+#define _SYSRTC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for SYSRTC_STOP */
+#define _SYSRTC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */
+#define SYSRTC_SYNCBUSY_STOP_DEFAULT (_SYSRTC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */
+#define SYSRTC_SYNCBUSY_CNT (0x1UL << 2) /**< Sync busy for CNT bitfield */
+#define _SYSRTC_SYNCBUSY_CNT_SHIFT 2 /**< Shift value for SYSRTC_CNT */
+#define _SYSRTC_SYNCBUSY_CNT_MASK 0x4UL /**< Bit mask for SYSRTC_CNT */
+#define _SYSRTC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */
+#define SYSRTC_SYNCBUSY_CNT_DEFAULT (_SYSRTC_SYNCBUSY_CNT_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */
+
+/* Bit fields for SYSRTC LOCK */
+#define _SYSRTC_LOCK_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_LOCK */
+#define _SYSRTC_LOCK_MASK 0x0000FFFFUL /**< Mask for SYSRTC_LOCK */
+#define _SYSRTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for SYSRTC_LOCKKEY */
+#define _SYSRTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for SYSRTC_LOCKKEY */
+#define _SYSRTC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_LOCK */
+#define _SYSRTC_LOCK_LOCKKEY_UNLOCK 0x00004776UL /**< Mode UNLOCK for SYSRTC_LOCK */
+#define SYSRTC_LOCK_LOCKKEY_DEFAULT (_SYSRTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_LOCK */
+#define SYSRTC_LOCK_LOCKKEY_UNLOCK (_SYSRTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SYSRTC_LOCK */
+
+/* Bit fields for SYSRTC GRP0_IF */
+#define _SYSRTC_GRP0_IF_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_IF */
+#define _SYSRTC_GRP0_IF_MASK 0x0000000FUL /**< Mask for SYSRTC_GRP0_IF */
+#define SYSRTC_GRP0_IF_OVF (0x1UL << 0) /**< Overflow Interrupt Flag */
+#define _SYSRTC_GRP0_IF_OVF_SHIFT 0 /**< Shift value for SYSRTC_OVF */
+#define _SYSRTC_GRP0_IF_OVF_MASK 0x1UL /**< Bit mask for SYSRTC_OVF */
+#define _SYSRTC_GRP0_IF_OVF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */
+#define SYSRTC_GRP0_IF_OVF_DEFAULT (_SYSRTC_GRP0_IF_OVF_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */
+#define SYSRTC_GRP0_IF_CMP0 (0x1UL << 1) /**< Compare 0 Interrupt Flag */
+#define _SYSRTC_GRP0_IF_CMP0_SHIFT 1 /**< Shift value for SYSRTC_CMP0 */
+#define _SYSRTC_GRP0_IF_CMP0_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0 */
+#define _SYSRTC_GRP0_IF_CMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */
+#define SYSRTC_GRP0_IF_CMP0_DEFAULT (_SYSRTC_GRP0_IF_CMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */
+#define SYSRTC_GRP0_IF_CMP1 (0x1UL << 2) /**< Compare 1 Interrupt Flag */
+#define _SYSRTC_GRP0_IF_CMP1_SHIFT 2 /**< Shift value for SYSRTC_CMP1 */
+#define _SYSRTC_GRP0_IF_CMP1_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1 */
+#define _SYSRTC_GRP0_IF_CMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */
+#define SYSRTC_GRP0_IF_CMP1_DEFAULT (_SYSRTC_GRP0_IF_CMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */
+#define SYSRTC_GRP0_IF_CAP0 (0x1UL << 3) /**< Capture 0 Interrupt Flag */
+#define _SYSRTC_GRP0_IF_CAP0_SHIFT 3 /**< Shift value for SYSRTC_CAP0 */
+#define _SYSRTC_GRP0_IF_CAP0_MASK 0x8UL /**< Bit mask for SYSRTC_CAP0 */
+#define _SYSRTC_GRP0_IF_CAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */
+#define SYSRTC_GRP0_IF_CAP0_DEFAULT (_SYSRTC_GRP0_IF_CAP0_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */
+
+/* Bit fields for SYSRTC GRP0_IEN */
+#define _SYSRTC_GRP0_IEN_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_IEN */
+#define _SYSRTC_GRP0_IEN_MASK 0x0000000FUL /**< Mask for SYSRTC_GRP0_IEN */
+#define SYSRTC_GRP0_IEN_OVF (0x1UL << 0) /**< Overflow Interrupt Enable */
+#define _SYSRTC_GRP0_IEN_OVF_SHIFT 0 /**< Shift value for SYSRTC_OVF */
+#define _SYSRTC_GRP0_IEN_OVF_MASK 0x1UL /**< Bit mask for SYSRTC_OVF */
+#define _SYSRTC_GRP0_IEN_OVF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */
+#define SYSRTC_GRP0_IEN_OVF_DEFAULT (_SYSRTC_GRP0_IEN_OVF_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */
+#define SYSRTC_GRP0_IEN_CMP0 (0x1UL << 1) /**< Compare 0 Interrupt Enable */
+#define _SYSRTC_GRP0_IEN_CMP0_SHIFT 1 /**< Shift value for SYSRTC_CMP0 */
+#define _SYSRTC_GRP0_IEN_CMP0_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0 */
+#define _SYSRTC_GRP0_IEN_CMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */
+#define SYSRTC_GRP0_IEN_CMP0_DEFAULT (_SYSRTC_GRP0_IEN_CMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */
+#define SYSRTC_GRP0_IEN_CMP1 (0x1UL << 2) /**< Compare 1 Interrupt Enable */
+#define _SYSRTC_GRP0_IEN_CMP1_SHIFT 2 /**< Shift value for SYSRTC_CMP1 */
+#define _SYSRTC_GRP0_IEN_CMP1_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1 */
+#define _SYSRTC_GRP0_IEN_CMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */
+#define SYSRTC_GRP0_IEN_CMP1_DEFAULT (_SYSRTC_GRP0_IEN_CMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */
+#define SYSRTC_GRP0_IEN_CAP0 (0x1UL << 3) /**< Capture 0 Interrupt Enable */
+#define _SYSRTC_GRP0_IEN_CAP0_SHIFT 3 /**< Shift value for SYSRTC_CAP0 */
+#define _SYSRTC_GRP0_IEN_CAP0_MASK 0x8UL /**< Bit mask for SYSRTC_CAP0 */
+#define _SYSRTC_GRP0_IEN_CAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */
+#define SYSRTC_GRP0_IEN_CAP0_DEFAULT (_SYSRTC_GRP0_IEN_CAP0_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */
+
+/* Bit fields for SYSRTC GRP0_CTRL */
+#define _SYSRTC_GRP0_CTRL_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CTRL */
+#define _SYSRTC_GRP0_CTRL_MASK 0x000007FFUL /**< Mask for SYSRTC_GRP0_CTRL */
+#define SYSRTC_GRP0_CTRL_CMP0EN (0x1UL << 0) /**< Compare 0 Enable */
+#define _SYSRTC_GRP0_CTRL_CMP0EN_SHIFT 0 /**< Shift value for SYSRTC_CMP0EN */
+#define _SYSRTC_GRP0_CTRL_CMP0EN_MASK 0x1UL /**< Bit mask for SYSRTC_CMP0EN */
+#define _SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */
+#define SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT (_SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */
+#define SYSRTC_GRP0_CTRL_CMP1EN (0x1UL << 1) /**< Compare 1 Enable */
+#define _SYSRTC_GRP0_CTRL_CMP1EN_SHIFT 1 /**< Shift value for SYSRTC_CMP1EN */
+#define _SYSRTC_GRP0_CTRL_CMP1EN_MASK 0x2UL /**< Bit mask for SYSRTC_CMP1EN */
+#define _SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */
+#define SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT (_SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */
+#define SYSRTC_GRP0_CTRL_CAP0EN (0x1UL << 2) /**< Capture 0 Enable */
+#define _SYSRTC_GRP0_CTRL_CAP0EN_SHIFT 2 /**< Shift value for SYSRTC_CAP0EN */
+#define _SYSRTC_GRP0_CTRL_CAP0EN_MASK 0x4UL /**< Bit mask for SYSRTC_CAP0EN */
+#define _SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */
+#define SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT (_SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */
+#define _SYSRTC_GRP0_CTRL_CMP0CMOA_SHIFT 3 /**< Shift value for SYSRTC_CMP0CMOA */
+#define _SYSRTC_GRP0_CTRL_CMP0CMOA_MASK 0x38UL /**< Bit mask for SYSRTC_CMP0CMOA */
+#define _SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */
+#define _SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR 0x00000000UL /**< Mode CLEAR for SYSRTC_GRP0_CTRL */
+#define _SYSRTC_GRP0_CTRL_CMP0CMOA_SET 0x00000001UL /**< Mode SET for SYSRTC_GRP0_CTRL */
+#define _SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE 0x00000002UL /**< Mode PULSE for SYSRTC_GRP0_CTRL */
+#define _SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE 0x00000003UL /**< Mode TOGGLE for SYSRTC_GRP0_CTRL */
+#define _SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF 0x00000004UL /**< Mode CMPIF for SYSRTC_GRP0_CTRL */
+#define SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT (_SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */
+#define SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR (_SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR << 3) /**< Shifted mode CLEAR for SYSRTC_GRP0_CTRL */
+#define SYSRTC_GRP0_CTRL_CMP0CMOA_SET (_SYSRTC_GRP0_CTRL_CMP0CMOA_SET << 3) /**< Shifted mode SET for SYSRTC_GRP0_CTRL */
+#define SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE (_SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE << 3) /**< Shifted mode PULSE for SYSRTC_GRP0_CTRL */
+#define SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE (_SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE << 3) /**< Shifted mode TOGGLE for SYSRTC_GRP0_CTRL */
+#define SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF (_SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF << 3) /**< Shifted mode CMPIF for SYSRTC_GRP0_CTRL */
+#define _SYSRTC_GRP0_CTRL_CMP1CMOA_SHIFT 6 /**< Shift value for SYSRTC_CMP1CMOA */
+#define _SYSRTC_GRP0_CTRL_CMP1CMOA_MASK 0x1C0UL /**< Bit mask for SYSRTC_CMP1CMOA */
+#define _SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */
+#define _SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR 0x00000000UL /**< Mode CLEAR for SYSRTC_GRP0_CTRL */
+#define _SYSRTC_GRP0_CTRL_CMP1CMOA_SET 0x00000001UL /**< Mode SET for SYSRTC_GRP0_CTRL */
+#define _SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE 0x00000002UL /**< Mode PULSE for SYSRTC_GRP0_CTRL */
+#define _SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE 0x00000003UL /**< Mode TOGGLE for SYSRTC_GRP0_CTRL */
+#define _SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF 0x00000004UL /**< Mode CMPIF for SYSRTC_GRP0_CTRL */
+#define SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT (_SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */
+#define SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR (_SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR << 6) /**< Shifted mode CLEAR for SYSRTC_GRP0_CTRL */
+#define SYSRTC_GRP0_CTRL_CMP1CMOA_SET (_SYSRTC_GRP0_CTRL_CMP1CMOA_SET << 6) /**< Shifted mode SET for SYSRTC_GRP0_CTRL */
+#define SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE (_SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE << 6) /**< Shifted mode PULSE for SYSRTC_GRP0_CTRL */
+#define SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE (_SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE << 6) /**< Shifted mode TOGGLE for SYSRTC_GRP0_CTRL */
+#define SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF (_SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF << 6) /**< Shifted mode CMPIF for SYSRTC_GRP0_CTRL */
+#define _SYSRTC_GRP0_CTRL_CAP0EDGE_SHIFT 9 /**< Shift value for SYSRTC_CAP0EDGE */
+#define _SYSRTC_GRP0_CTRL_CAP0EDGE_MASK 0x600UL /**< Bit mask for SYSRTC_CAP0EDGE */
+#define _SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */
+#define _SYSRTC_GRP0_CTRL_CAP0EDGE_RISING 0x00000000UL /**< Mode RISING for SYSRTC_GRP0_CTRL */
+#define _SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING 0x00000001UL /**< Mode FALLING for SYSRTC_GRP0_CTRL */
+#define _SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH 0x00000002UL /**< Mode BOTH for SYSRTC_GRP0_CTRL */
+#define SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT (_SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */
+#define SYSRTC_GRP0_CTRL_CAP0EDGE_RISING (_SYSRTC_GRP0_CTRL_CAP0EDGE_RISING << 9) /**< Shifted mode RISING for SYSRTC_GRP0_CTRL */
+#define SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING (_SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING << 9) /**< Shifted mode FALLING for SYSRTC_GRP0_CTRL */
+#define SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH (_SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH << 9) /**< Shifted mode BOTH for SYSRTC_GRP0_CTRL */
+
+/* Bit fields for SYSRTC GRP0_CMP0VALUE */
+#define _SYSRTC_GRP0_CMP0VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CMP0VALUE */
+#define _SYSRTC_GRP0_CMP0VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CMP0VALUE */
+#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_SHIFT 0 /**< Shift value for SYSRTC_CMP0VALUE */
+#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CMP0VALUE */
+#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CMP0VALUE */
+#define SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT (_SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CMP0VALUE*/
+
+/* Bit fields for SYSRTC GRP0_CMP1VALUE */
+#define _SYSRTC_GRP0_CMP1VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CMP1VALUE */
+#define _SYSRTC_GRP0_CMP1VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CMP1VALUE */
+#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_SHIFT 0 /**< Shift value for SYSRTC_CMP1VALUE */
+#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CMP1VALUE */
+#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CMP1VALUE */
+#define SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT (_SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CMP1VALUE*/
+
+/* Bit fields for SYSRTC GRP0_CAP0VALUE */
+#define _SYSRTC_GRP0_CAP0VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CAP0VALUE */
+#define _SYSRTC_GRP0_CAP0VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CAP0VALUE */
+#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_SHIFT 0 /**< Shift value for SYSRTC_CAP0VALUE */
+#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CAP0VALUE */
+#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CAP0VALUE */
+#define SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT (_SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CAP0VALUE*/
+
+/* Bit fields for SYSRTC GRP0_SYNCBUSY */
+#define _SYSRTC_GRP0_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_SYNCBUSY */
+#define _SYSRTC_GRP0_SYNCBUSY_MASK 0x00000007UL /**< Mask for SYSRTC_GRP0_SYNCBUSY */
+#define SYSRTC_GRP0_SYNCBUSY_CTRL (0x1UL << 0) /**< Sync busy for CTRL register */
+#define _SYSRTC_GRP0_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for SYSRTC_CTRL */
+#define _SYSRTC_GRP0_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for SYSRTC_CTRL */
+#define _SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */
+#define SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/
+#define SYSRTC_GRP0_SYNCBUSY_CMP0VALUE (0x1UL << 1) /**< Sync busy for CMP0VALUE register */
+#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_SHIFT 1 /**< Shift value for SYSRTC_CMP0VALUE */
+#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0VALUE */
+#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */
+#define SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/
+#define SYSRTC_GRP0_SYNCBUSY_CMP1VALUE (0x1UL << 2) /**< Sync busy for CMP1VALUE register */
+#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_SHIFT 2 /**< Shift value for SYSRTC_CMP1VALUE */
+#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1VALUE */
+#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */
+#define SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/
+
+/** @} End of group EFR32MG24_SYSRTC_BitFields */
+/** @} End of group EFR32MG24_SYSRTC */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_SYSRTC_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_timer.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_timer.h
new file mode 100644
index 00000000..d43e8d32
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_timer.h
@@ -0,0 +1,1020 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 TIMER register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_TIMER_H
+#define EFR32MG24_TIMER_H
+#define TIMER_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_TIMER TIMER
+ * @{
+ * @brief EFR32MG24 TIMER Register Declaration.
+ *****************************************************************************/
+
+/** TIMER CC Register Group Declaration. */
+typedef struct {
+ __IOM uint32_t CFG; /**< CC Channel Configuration Register */
+ __IOM uint32_t CTRL; /**< CC Channel Control Register */
+ __IOM uint32_t OC; /**< OC Channel Value Register */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+ __IOM uint32_t OCB; /**< OC Channel Value Buffer Register */
+ __IM uint32_t ICF; /**< IC Channel Value Register */
+ __IM uint32_t ICOF; /**< IC Channel Value Overflow Register */
+ uint32_t RESERVED1[1U]; /**< Reserved for future use */
+} TIMER_CC_TypeDef;
+
+/** TIMER Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IP version ID */
+ __IOM uint32_t CFG; /**< Configuration Register */
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IOM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IOM uint32_t TOP; /**< Counter Top Value Register */
+ __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */
+ __IOM uint32_t CNT; /**< Counter Value Register */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK; /**< TIMER Configuration Lock Register */
+ __IOM uint32_t EN; /**< module en */
+ uint32_t RESERVED1[11U]; /**< Reserved for future use */
+ TIMER_CC_TypeDef CC[3U]; /**< Compare/Capture Channel */
+ uint32_t RESERVED2[8U]; /**< Reserved for future use */
+ __IOM uint32_t DTCFG; /**< DTI Configuration Register */
+ __IOM uint32_t DTTIMECFG; /**< DTI Time Configuration Register */
+ __IOM uint32_t DTFCFG; /**< DTI Fault Configuration Register */
+ __IOM uint32_t DTCTRL; /**< DTI Control Register */
+ __IOM uint32_t DTOGEN; /**< DTI Output Generation Enable Register */
+ __IM uint32_t DTFAULT; /**< DTI Fault Register */
+ __IOM uint32_t DTFAULTC; /**< DTI Fault Clear Register */
+ __IOM uint32_t DTLOCK; /**< DTI Configuration Lock Register */
+ uint32_t RESERVED3[960U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP version ID */
+ __IOM uint32_t CFG_SET; /**< Configuration Register */
+ __IOM uint32_t CTRL_SET; /**< Control Register */
+ __IOM uint32_t CMD_SET; /**< Command Register */
+ __IM uint32_t STATUS_SET; /**< Status Register */
+ __IOM uint32_t IF_SET; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
+ __IOM uint32_t TOP_SET; /**< Counter Top Value Register */
+ __IOM uint32_t TOPB_SET; /**< Counter Top Value Buffer Register */
+ __IOM uint32_t CNT_SET; /**< Counter Value Register */
+ uint32_t RESERVED4[1U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK_SET; /**< TIMER Configuration Lock Register */
+ __IOM uint32_t EN_SET; /**< module en */
+ uint32_t RESERVED5[11U]; /**< Reserved for future use */
+ TIMER_CC_TypeDef CC_SET[3U]; /**< Compare/Capture Channel */
+ uint32_t RESERVED6[8U]; /**< Reserved for future use */
+ __IOM uint32_t DTCFG_SET; /**< DTI Configuration Register */
+ __IOM uint32_t DTTIMECFG_SET; /**< DTI Time Configuration Register */
+ __IOM uint32_t DTFCFG_SET; /**< DTI Fault Configuration Register */
+ __IOM uint32_t DTCTRL_SET; /**< DTI Control Register */
+ __IOM uint32_t DTOGEN_SET; /**< DTI Output Generation Enable Register */
+ __IM uint32_t DTFAULT_SET; /**< DTI Fault Register */
+ __IOM uint32_t DTFAULTC_SET; /**< DTI Fault Clear Register */
+ __IOM uint32_t DTLOCK_SET; /**< DTI Configuration Lock Register */
+ uint32_t RESERVED7[960U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP version ID */
+ __IOM uint32_t CFG_CLR; /**< Configuration Register */
+ __IOM uint32_t CTRL_CLR; /**< Control Register */
+ __IOM uint32_t CMD_CLR; /**< Command Register */
+ __IM uint32_t STATUS_CLR; /**< Status Register */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
+ __IOM uint32_t TOP_CLR; /**< Counter Top Value Register */
+ __IOM uint32_t TOPB_CLR; /**< Counter Top Value Buffer Register */
+ __IOM uint32_t CNT_CLR; /**< Counter Value Register */
+ uint32_t RESERVED8[1U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK_CLR; /**< TIMER Configuration Lock Register */
+ __IOM uint32_t EN_CLR; /**< module en */
+ uint32_t RESERVED9[11U]; /**< Reserved for future use */
+ TIMER_CC_TypeDef CC_CLR[3U]; /**< Compare/Capture Channel */
+ uint32_t RESERVED10[8U]; /**< Reserved for future use */
+ __IOM uint32_t DTCFG_CLR; /**< DTI Configuration Register */
+ __IOM uint32_t DTTIMECFG_CLR; /**< DTI Time Configuration Register */
+ __IOM uint32_t DTFCFG_CLR; /**< DTI Fault Configuration Register */
+ __IOM uint32_t DTCTRL_CLR; /**< DTI Control Register */
+ __IOM uint32_t DTOGEN_CLR; /**< DTI Output Generation Enable Register */
+ __IM uint32_t DTFAULT_CLR; /**< DTI Fault Register */
+ __IOM uint32_t DTFAULTC_CLR; /**< DTI Fault Clear Register */
+ __IOM uint32_t DTLOCK_CLR; /**< DTI Configuration Lock Register */
+ uint32_t RESERVED11[960U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP version ID */
+ __IOM uint32_t CFG_TGL; /**< Configuration Register */
+ __IOM uint32_t CTRL_TGL; /**< Control Register */
+ __IOM uint32_t CMD_TGL; /**< Command Register */
+ __IM uint32_t STATUS_TGL; /**< Status Register */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
+ __IOM uint32_t TOP_TGL; /**< Counter Top Value Register */
+ __IOM uint32_t TOPB_TGL; /**< Counter Top Value Buffer Register */
+ __IOM uint32_t CNT_TGL; /**< Counter Value Register */
+ uint32_t RESERVED12[1U]; /**< Reserved for future use */
+ __IOM uint32_t LOCK_TGL; /**< TIMER Configuration Lock Register */
+ __IOM uint32_t EN_TGL; /**< module en */
+ uint32_t RESERVED13[11U]; /**< Reserved for future use */
+ TIMER_CC_TypeDef CC_TGL[3U]; /**< Compare/Capture Channel */
+ uint32_t RESERVED14[8U]; /**< Reserved for future use */
+ __IOM uint32_t DTCFG_TGL; /**< DTI Configuration Register */
+ __IOM uint32_t DTTIMECFG_TGL; /**< DTI Time Configuration Register */
+ __IOM uint32_t DTFCFG_TGL; /**< DTI Fault Configuration Register */
+ __IOM uint32_t DTCTRL_TGL; /**< DTI Control Register */
+ __IOM uint32_t DTOGEN_TGL; /**< DTI Output Generation Enable Register */
+ __IM uint32_t DTFAULT_TGL; /**< DTI Fault Register */
+ __IOM uint32_t DTFAULTC_TGL; /**< DTI Fault Clear Register */
+ __IOM uint32_t DTLOCK_TGL; /**< DTI Configuration Lock Register */
+} TIMER_TypeDef;
+/** @} End of group EFR32MG24_TIMER */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_TIMER
+ * @{
+ * @defgroup EFR32MG24_TIMER_BitFields TIMER Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for TIMER IPVERSION */
+#define _TIMER_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for TIMER_IPVERSION */
+#define _TIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for TIMER_IPVERSION */
+#define _TIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for TIMER_IPVERSION */
+#define _TIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_IPVERSION */
+#define _TIMER_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for TIMER_IPVERSION */
+#define TIMER_IPVERSION_IPVERSION_DEFAULT (_TIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IPVERSION */
+
+/* Bit fields for TIMER CFG */
+#define _TIMER_CFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_CFG */
+#define _TIMER_CFG_MASK 0x0FFF1FFBUL /**< Mask for TIMER_CFG */
+#define _TIMER_CFG_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
+#define _TIMER_CFG_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
+#define _TIMER_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */
+#define _TIMER_CFG_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CFG */
+#define _TIMER_CFG_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CFG */
+#define _TIMER_CFG_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CFG */
+#define _TIMER_CFG_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CFG */
+#define TIMER_CFG_MODE_DEFAULT (_TIMER_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CFG */
+#define TIMER_CFG_MODE_UP (_TIMER_CFG_MODE_UP << 0) /**< Shifted mode UP for TIMER_CFG */
+#define TIMER_CFG_MODE_DOWN (_TIMER_CFG_MODE_DOWN << 0) /**< Shifted mode DOWN for TIMER_CFG */
+#define TIMER_CFG_MODE_UPDOWN (_TIMER_CFG_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for TIMER_CFG */
+#define TIMER_CFG_MODE_QDEC (_TIMER_CFG_MODE_QDEC << 0) /**< Shifted mode QDEC for TIMER_CFG */
+#define TIMER_CFG_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */
+#define _TIMER_CFG_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */
+#define _TIMER_CFG_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */
+#define _TIMER_CFG_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */
+#define _TIMER_CFG_SYNC_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CFG */
+#define _TIMER_CFG_SYNC_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CFG */
+#define TIMER_CFG_SYNC_DEFAULT (_TIMER_CFG_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_CFG */
+#define TIMER_CFG_SYNC_DISABLE (_TIMER_CFG_SYNC_DISABLE << 3) /**< Shifted mode DISABLE for TIMER_CFG */
+#define TIMER_CFG_SYNC_ENABLE (_TIMER_CFG_SYNC_ENABLE << 3) /**< Shifted mode ENABLE for TIMER_CFG */
+#define TIMER_CFG_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */
+#define _TIMER_CFG_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */
+#define _TIMER_CFG_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */
+#define _TIMER_CFG_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */
+#define TIMER_CFG_OSMEN_DEFAULT (_TIMER_CFG_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CFG */
+#define TIMER_CFG_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */
+#define _TIMER_CFG_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */
+#define _TIMER_CFG_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */
+#define _TIMER_CFG_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */
+#define _TIMER_CFG_QDM_X2 0x00000000UL /**< Mode X2 for TIMER_CFG */
+#define _TIMER_CFG_QDM_X4 0x00000001UL /**< Mode X4 for TIMER_CFG */
+#define TIMER_CFG_QDM_DEFAULT (_TIMER_CFG_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_CFG */
+#define TIMER_CFG_QDM_X2 (_TIMER_CFG_QDM_X2 << 5) /**< Shifted mode X2 for TIMER_CFG */
+#define TIMER_CFG_QDM_X4 (_TIMER_CFG_QDM_X4 << 5) /**< Shifted mode X4 for TIMER_CFG */
+#define TIMER_CFG_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */
+#define _TIMER_CFG_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */
+#define _TIMER_CFG_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */
+#define _TIMER_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */
+#define _TIMER_CFG_DEBUGRUN_HALT 0x00000000UL /**< Mode HALT for TIMER_CFG */
+#define _TIMER_CFG_DEBUGRUN_RUN 0x00000001UL /**< Mode RUN for TIMER_CFG */
+#define TIMER_CFG_DEBUGRUN_DEFAULT (_TIMER_CFG_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_CFG */
+#define TIMER_CFG_DEBUGRUN_HALT (_TIMER_CFG_DEBUGRUN_HALT << 6) /**< Shifted mode HALT for TIMER_CFG */
+#define TIMER_CFG_DEBUGRUN_RUN (_TIMER_CFG_DEBUGRUN_RUN << 6) /**< Shifted mode RUN for TIMER_CFG */
+#define TIMER_CFG_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */
+#define _TIMER_CFG_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */
+#define _TIMER_CFG_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */
+#define _TIMER_CFG_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */
+#define TIMER_CFG_DMACLRACT_DEFAULT (_TIMER_CFG_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_CFG */
+#define _TIMER_CFG_CLKSEL_SHIFT 8 /**< Shift value for TIMER_CLKSEL */
+#define _TIMER_CFG_CLKSEL_MASK 0x300UL /**< Bit mask for TIMER_CLKSEL */
+#define _TIMER_CFG_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */
+#define _TIMER_CFG_CLKSEL_PRESCEM01GRPACLK 0x00000000UL /**< Mode PRESCEM01GRPACLK for TIMER_CFG */
+#define _TIMER_CFG_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CFG */
+#define _TIMER_CFG_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CFG */
+#define TIMER_CFG_CLKSEL_DEFAULT (_TIMER_CFG_CLKSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CFG */
+#define TIMER_CFG_CLKSEL_PRESCEM01GRPACLK (_TIMER_CFG_CLKSEL_PRESCEM01GRPACLK << 8) /**< Shifted mode PRESCEM01GRPACLK for TIMER_CFG */
+#define TIMER_CFG_CLKSEL_CC1 (_TIMER_CFG_CLKSEL_CC1 << 8) /**< Shifted mode CC1 for TIMER_CFG */
+#define TIMER_CFG_CLKSEL_TIMEROUF (_TIMER_CFG_CLKSEL_TIMEROUF << 8) /**< Shifted mode TIMEROUF for TIMER_CFG */
+#define TIMER_CFG_RETIMEEN (0x1UL << 10) /**< PWM output retimed enable */
+#define _TIMER_CFG_RETIMEEN_SHIFT 10 /**< Shift value for TIMER_RETIMEEN */
+#define _TIMER_CFG_RETIMEEN_MASK 0x400UL /**< Bit mask for TIMER_RETIMEEN */
+#define _TIMER_CFG_RETIMEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */
+#define _TIMER_CFG_RETIMEEN_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CFG */
+#define _TIMER_CFG_RETIMEEN_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CFG */
+#define TIMER_CFG_RETIMEEN_DEFAULT (_TIMER_CFG_RETIMEEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CFG */
+#define TIMER_CFG_RETIMEEN_DISABLE (_TIMER_CFG_RETIMEEN_DISABLE << 10) /**< Shifted mode DISABLE for TIMER_CFG */
+#define TIMER_CFG_RETIMEEN_ENABLE (_TIMER_CFG_RETIMEEN_ENABLE << 10) /**< Shifted mode ENABLE for TIMER_CFG */
+#define TIMER_CFG_DISSYNCOUT (0x1UL << 11) /**< Disable Timer Start/Stop/Reload output */
+#define _TIMER_CFG_DISSYNCOUT_SHIFT 11 /**< Shift value for TIMER_DISSYNCOUT */
+#define _TIMER_CFG_DISSYNCOUT_MASK 0x800UL /**< Bit mask for TIMER_DISSYNCOUT */
+#define _TIMER_CFG_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */
+#define _TIMER_CFG_DISSYNCOUT_EN 0x00000000UL /**< Mode EN for TIMER_CFG */
+#define _TIMER_CFG_DISSYNCOUT_DIS 0x00000001UL /**< Mode DIS for TIMER_CFG */
+#define TIMER_CFG_DISSYNCOUT_DEFAULT (_TIMER_CFG_DISSYNCOUT_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_CFG */
+#define TIMER_CFG_DISSYNCOUT_EN (_TIMER_CFG_DISSYNCOUT_EN << 11) /**< Shifted mode EN for TIMER_CFG */
+#define TIMER_CFG_DISSYNCOUT_DIS (_TIMER_CFG_DISSYNCOUT_DIS << 11) /**< Shifted mode DIS for TIMER_CFG */
+#define TIMER_CFG_RETIMESEL (0x1UL << 12) /**< PWM output retime select */
+#define _TIMER_CFG_RETIMESEL_SHIFT 12 /**< Shift value for TIMER_RETIMESEL */
+#define _TIMER_CFG_RETIMESEL_MASK 0x1000UL /**< Bit mask for TIMER_RETIMESEL */
+#define _TIMER_CFG_RETIMESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */
+#define TIMER_CFG_RETIMESEL_DEFAULT (_TIMER_CFG_RETIMESEL_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CFG */
+#define TIMER_CFG_ATI (0x1UL << 16) /**< Always Track Inputs */
+#define _TIMER_CFG_ATI_SHIFT 16 /**< Shift value for TIMER_ATI */
+#define _TIMER_CFG_ATI_MASK 0x10000UL /**< Bit mask for TIMER_ATI */
+#define _TIMER_CFG_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */
+#define TIMER_CFG_ATI_DEFAULT (_TIMER_CFG_ATI_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CFG */
+#define TIMER_CFG_RSSCOIST (0x1UL << 17) /**< Reload-Start Sets COIST */
+#define _TIMER_CFG_RSSCOIST_SHIFT 17 /**< Shift value for TIMER_RSSCOIST */
+#define _TIMER_CFG_RSSCOIST_MASK 0x20000UL /**< Bit mask for TIMER_RSSCOIST */
+#define _TIMER_CFG_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */
+#define TIMER_CFG_RSSCOIST_DEFAULT (_TIMER_CFG_RSSCOIST_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_CFG */
+#define _TIMER_CFG_PRESC_SHIFT 18 /**< Shift value for TIMER_PRESC */
+#define _TIMER_CFG_PRESC_MASK 0xFFC0000UL /**< Bit mask for TIMER_PRESC */
+#define _TIMER_CFG_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */
+#define _TIMER_CFG_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CFG */
+#define _TIMER_CFG_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CFG */
+#define _TIMER_CFG_PRESC_DIV4 0x00000003UL /**< Mode DIV4 for TIMER_CFG */
+#define _TIMER_CFG_PRESC_DIV8 0x00000007UL /**< Mode DIV8 for TIMER_CFG */
+#define _TIMER_CFG_PRESC_DIV16 0x0000000FUL /**< Mode DIV16 for TIMER_CFG */
+#define _TIMER_CFG_PRESC_DIV32 0x0000001FUL /**< Mode DIV32 for TIMER_CFG */
+#define _TIMER_CFG_PRESC_DIV64 0x0000003FUL /**< Mode DIV64 for TIMER_CFG */
+#define _TIMER_CFG_PRESC_DIV128 0x0000007FUL /**< Mode DIV128 for TIMER_CFG */
+#define _TIMER_CFG_PRESC_DIV256 0x000000FFUL /**< Mode DIV256 for TIMER_CFG */
+#define _TIMER_CFG_PRESC_DIV512 0x000001FFUL /**< Mode DIV512 for TIMER_CFG */
+#define _TIMER_CFG_PRESC_DIV1024 0x000003FFUL /**< Mode DIV1024 for TIMER_CFG */
+#define TIMER_CFG_PRESC_DEFAULT (_TIMER_CFG_PRESC_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_CFG */
+#define TIMER_CFG_PRESC_DIV1 (_TIMER_CFG_PRESC_DIV1 << 18) /**< Shifted mode DIV1 for TIMER_CFG */
+#define TIMER_CFG_PRESC_DIV2 (_TIMER_CFG_PRESC_DIV2 << 18) /**< Shifted mode DIV2 for TIMER_CFG */
+#define TIMER_CFG_PRESC_DIV4 (_TIMER_CFG_PRESC_DIV4 << 18) /**< Shifted mode DIV4 for TIMER_CFG */
+#define TIMER_CFG_PRESC_DIV8 (_TIMER_CFG_PRESC_DIV8 << 18) /**< Shifted mode DIV8 for TIMER_CFG */
+#define TIMER_CFG_PRESC_DIV16 (_TIMER_CFG_PRESC_DIV16 << 18) /**< Shifted mode DIV16 for TIMER_CFG */
+#define TIMER_CFG_PRESC_DIV32 (_TIMER_CFG_PRESC_DIV32 << 18) /**< Shifted mode DIV32 for TIMER_CFG */
+#define TIMER_CFG_PRESC_DIV64 (_TIMER_CFG_PRESC_DIV64 << 18) /**< Shifted mode DIV64 for TIMER_CFG */
+#define TIMER_CFG_PRESC_DIV128 (_TIMER_CFG_PRESC_DIV128 << 18) /**< Shifted mode DIV128 for TIMER_CFG */
+#define TIMER_CFG_PRESC_DIV256 (_TIMER_CFG_PRESC_DIV256 << 18) /**< Shifted mode DIV256 for TIMER_CFG */
+#define TIMER_CFG_PRESC_DIV512 (_TIMER_CFG_PRESC_DIV512 << 18) /**< Shifted mode DIV512 for TIMER_CFG */
+#define TIMER_CFG_PRESC_DIV1024 (_TIMER_CFG_PRESC_DIV1024 << 18) /**< Shifted mode DIV1024 for TIMER_CFG */
+
+/* Bit fields for TIMER CTRL */
+#define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */
+#define _TIMER_CTRL_MASK 0x0000001FUL /**< Mask for TIMER_CTRL */
+#define _TIMER_CTRL_RISEA_SHIFT 0 /**< Shift value for TIMER_RISEA */
+#define _TIMER_CTRL_RISEA_MASK 0x3UL /**< Bit mask for TIMER_RISEA */
+#define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
+#define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */
+#define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */
+#define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */
+#define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */
+#define TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 0) /**< Shifted mode NONE for TIMER_CTRL */
+#define TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 0) /**< Shifted mode START for TIMER_CTRL */
+#define TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 0) /**< Shifted mode STOP for TIMER_CTRL */
+#define TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 0) /**< Shifted mode RELOADSTART for TIMER_CTRL */
+#define _TIMER_CTRL_FALLA_SHIFT 2 /**< Shift value for TIMER_FALLA */
+#define _TIMER_CTRL_FALLA_MASK 0xCUL /**< Bit mask for TIMER_FALLA */
+#define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
+#define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */
+#define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */
+#define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */
+#define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */
+#define TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 2) /**< Shifted mode NONE for TIMER_CTRL */
+#define TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 2) /**< Shifted mode START for TIMER_CTRL */
+#define TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 2) /**< Shifted mode STOP for TIMER_CTRL */
+#define TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 2) /**< Shifted mode RELOADSTART for TIMER_CTRL */
+#define TIMER_CTRL_X2CNT (0x1UL << 4) /**< 2x Count Mode */
+#define _TIMER_CTRL_X2CNT_SHIFT 4 /**< Shift value for TIMER_X2CNT */
+#define _TIMER_CTRL_X2CNT_MASK 0x10UL /**< Bit mask for TIMER_X2CNT */
+#define _TIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
+#define TIMER_CTRL_X2CNT_DEFAULT (_TIMER_CTRL_X2CNT_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */
+
+/* Bit fields for TIMER CMD */
+#define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */
+#define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */
+#define TIMER_CMD_START (0x1UL << 0) /**< Start Timer */
+#define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */
+#define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */
+#define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */
+#define TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CMD */
+#define TIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */
+#define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */
+#define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */
+#define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */
+#define TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_CMD */
+
+/* Bit fields for TIMER STATUS */
+#define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */
+#define _TIMER_STATUS_MASK 0x07070777UL /**< Mask for TIMER_STATUS */
+#define TIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */
+#define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */
+#define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */
+#define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_DIR (0x1UL << 1) /**< Direction */
+#define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */
+#define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */
+#define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
+#define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */
+#define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */
+#define TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for TIMER_STATUS */
+#define TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for TIMER_STATUS */
+#define TIMER_STATUS_TOPBV (0x1UL << 2) /**< TOP Buffer Valid */
+#define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */
+#define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */
+#define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_TIMERLOCKSTATUS (0x1UL << 4) /**< Timer lock status */
+#define _TIMER_STATUS_TIMERLOCKSTATUS_SHIFT 4 /**< Shift value for TIMER_TIMERLOCKSTATUS */
+#define _TIMER_STATUS_TIMERLOCKSTATUS_MASK 0x10UL /**< Bit mask for TIMER_TIMERLOCKSTATUS */
+#define _TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
+#define _TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_STATUS */
+#define _TIMER_STATUS_TIMERLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_STATUS */
+#define TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT (_TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED (_TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED << 4) /**< Shifted mode UNLOCKED for TIMER_STATUS */
+#define TIMER_STATUS_TIMERLOCKSTATUS_LOCKED (_TIMER_STATUS_TIMERLOCKSTATUS_LOCKED << 4) /**< Shifted mode LOCKED for TIMER_STATUS */
+#define TIMER_STATUS_DTILOCKSTATUS (0x1UL << 5) /**< DTI lock status */
+#define _TIMER_STATUS_DTILOCKSTATUS_SHIFT 5 /**< Shift value for TIMER_DTILOCKSTATUS */
+#define _TIMER_STATUS_DTILOCKSTATUS_MASK 0x20UL /**< Bit mask for TIMER_DTILOCKSTATUS */
+#define _TIMER_STATUS_DTILOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
+#define _TIMER_STATUS_DTILOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_STATUS */
+#define _TIMER_STATUS_DTILOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_STATUS */
+#define TIMER_STATUS_DTILOCKSTATUS_DEFAULT (_TIMER_STATUS_DTILOCKSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_DTILOCKSTATUS_UNLOCKED (_TIMER_STATUS_DTILOCKSTATUS_UNLOCKED << 5) /**< Shifted mode UNLOCKED for TIMER_STATUS */
+#define TIMER_STATUS_DTILOCKSTATUS_LOCKED (_TIMER_STATUS_DTILOCKSTATUS_LOCKED << 5) /**< Shifted mode LOCKED for TIMER_STATUS */
+#define TIMER_STATUS_SYNCBUSY (0x1UL << 6) /**< Sync Busy */
+#define _TIMER_STATUS_SYNCBUSY_SHIFT 6 /**< Shift value for TIMER_SYNCBUSY */
+#define _TIMER_STATUS_SYNCBUSY_MASK 0x40UL /**< Bit mask for TIMER_SYNCBUSY */
+#define _TIMER_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_SYNCBUSY_DEFAULT (_TIMER_STATUS_SYNCBUSY_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_OCBV0 (0x1UL << 8) /**< Output Compare Buffer Valid */
+#define _TIMER_STATUS_OCBV0_SHIFT 8 /**< Shift value for TIMER_OCBV0 */
+#define _TIMER_STATUS_OCBV0_MASK 0x100UL /**< Bit mask for TIMER_OCBV0 */
+#define _TIMER_STATUS_OCBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_OCBV0_DEFAULT (_TIMER_STATUS_OCBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_OCBV1 (0x1UL << 9) /**< Output Compare Buffer Valid */
+#define _TIMER_STATUS_OCBV1_SHIFT 9 /**< Shift value for TIMER_OCBV1 */
+#define _TIMER_STATUS_OCBV1_MASK 0x200UL /**< Bit mask for TIMER_OCBV1 */
+#define _TIMER_STATUS_OCBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_OCBV1_DEFAULT (_TIMER_STATUS_OCBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_OCBV2 (0x1UL << 10) /**< Output Compare Buffer Valid */
+#define _TIMER_STATUS_OCBV2_SHIFT 10 /**< Shift value for TIMER_OCBV2 */
+#define _TIMER_STATUS_OCBV2_MASK 0x400UL /**< Bit mask for TIMER_OCBV2 */
+#define _TIMER_STATUS_OCBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_OCBV2_DEFAULT (_TIMER_STATUS_OCBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_ICFEMPTY0 (0x1UL << 16) /**< Input capture fifo empty */
+#define _TIMER_STATUS_ICFEMPTY0_SHIFT 16 /**< Shift value for TIMER_ICFEMPTY0 */
+#define _TIMER_STATUS_ICFEMPTY0_MASK 0x10000UL /**< Bit mask for TIMER_ICFEMPTY0 */
+#define _TIMER_STATUS_ICFEMPTY0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_ICFEMPTY0_DEFAULT (_TIMER_STATUS_ICFEMPTY0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_ICFEMPTY1 (0x1UL << 17) /**< Input capture fifo empty */
+#define _TIMER_STATUS_ICFEMPTY1_SHIFT 17 /**< Shift value for TIMER_ICFEMPTY1 */
+#define _TIMER_STATUS_ICFEMPTY1_MASK 0x20000UL /**< Bit mask for TIMER_ICFEMPTY1 */
+#define _TIMER_STATUS_ICFEMPTY1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_ICFEMPTY1_DEFAULT (_TIMER_STATUS_ICFEMPTY1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_ICFEMPTY2 (0x1UL << 18) /**< Input capture fifo empty */
+#define _TIMER_STATUS_ICFEMPTY2_SHIFT 18 /**< Shift value for TIMER_ICFEMPTY2 */
+#define _TIMER_STATUS_ICFEMPTY2_MASK 0x40000UL /**< Bit mask for TIMER_ICFEMPTY2 */
+#define _TIMER_STATUS_ICFEMPTY2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_ICFEMPTY2_DEFAULT (_TIMER_STATUS_ICFEMPTY2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CCn Polarity */
+#define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */
+#define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */
+#define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
+#define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */
+#define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CCn Polarity */
+#define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */
+#define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */
+#define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
+#define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */
+#define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CCn Polarity */
+#define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */
+#define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */
+#define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
+#define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */
+#define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */
+#define TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */
+
+/* Bit fields for TIMER IF */
+#define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */
+#define _TIMER_IF_MASK 0x07770077UL /**< Mask for TIMER_IF */
+#define TIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */
+#define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */
+#define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
+#define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */
+#define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */
+#define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
+#define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */
+#define _TIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
+#define _TIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
+#define _TIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_DIRCHG_DEFAULT (_TIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_CC0 (0x1UL << 4) /**< Capture Compare Channel 0 Interrupt Flag */
+#define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
+#define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
+#define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_CC1 (0x1UL << 5) /**< Capture Compare Channel 1 Interrupt Flag */
+#define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
+#define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
+#define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_CC2 (0x1UL << 6) /**< Capture Compare Channel 2 Interrupt Flag */
+#define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
+#define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
+#define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICFWLFULL0 (0x1UL << 16) /**< Input Capture Watermark Level Full */
+#define _TIMER_IF_ICFWLFULL0_SHIFT 16 /**< Shift value for TIMER_ICFWLFULL0 */
+#define _TIMER_IF_ICFWLFULL0_MASK 0x10000UL /**< Bit mask for TIMER_ICFWLFULL0 */
+#define _TIMER_IF_ICFWLFULL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICFWLFULL0_DEFAULT (_TIMER_IF_ICFWLFULL0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICFWLFULL1 (0x1UL << 17) /**< Input Capture Watermark Level Full */
+#define _TIMER_IF_ICFWLFULL1_SHIFT 17 /**< Shift value for TIMER_ICFWLFULL1 */
+#define _TIMER_IF_ICFWLFULL1_MASK 0x20000UL /**< Bit mask for TIMER_ICFWLFULL1 */
+#define _TIMER_IF_ICFWLFULL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICFWLFULL1_DEFAULT (_TIMER_IF_ICFWLFULL1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICFWLFULL2 (0x1UL << 18) /**< Input Capture Watermark Level Full */
+#define _TIMER_IF_ICFWLFULL2_SHIFT 18 /**< Shift value for TIMER_ICFWLFULL2 */
+#define _TIMER_IF_ICFWLFULL2_MASK 0x40000UL /**< Bit mask for TIMER_ICFWLFULL2 */
+#define _TIMER_IF_ICFWLFULL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICFWLFULL2_DEFAULT (_TIMER_IF_ICFWLFULL2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICFOF0 (0x1UL << 20) /**< Input Capture FIFO overflow */
+#define _TIMER_IF_ICFOF0_SHIFT 20 /**< Shift value for TIMER_ICFOF0 */
+#define _TIMER_IF_ICFOF0_MASK 0x100000UL /**< Bit mask for TIMER_ICFOF0 */
+#define _TIMER_IF_ICFOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICFOF0_DEFAULT (_TIMER_IF_ICFOF0_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICFOF1 (0x1UL << 21) /**< Input Capture FIFO overflow */
+#define _TIMER_IF_ICFOF1_SHIFT 21 /**< Shift value for TIMER_ICFOF1 */
+#define _TIMER_IF_ICFOF1_MASK 0x200000UL /**< Bit mask for TIMER_ICFOF1 */
+#define _TIMER_IF_ICFOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICFOF1_DEFAULT (_TIMER_IF_ICFOF1_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICFOF2 (0x1UL << 22) /**< Input Capture FIFO overflow */
+#define _TIMER_IF_ICFOF2_SHIFT 22 /**< Shift value for TIMER_ICFOF2 */
+#define _TIMER_IF_ICFOF2_MASK 0x400000UL /**< Bit mask for TIMER_ICFOF2 */
+#define _TIMER_IF_ICFOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICFOF2_DEFAULT (_TIMER_IF_ICFOF2_DEFAULT << 22) /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICFUF0 (0x1UL << 24) /**< Input capture FIFO underflow */
+#define _TIMER_IF_ICFUF0_SHIFT 24 /**< Shift value for TIMER_ICFUF0 */
+#define _TIMER_IF_ICFUF0_MASK 0x1000000UL /**< Bit mask for TIMER_ICFUF0 */
+#define _TIMER_IF_ICFUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICFUF0_DEFAULT (_TIMER_IF_ICFUF0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICFUF1 (0x1UL << 25) /**< Input capture FIFO underflow */
+#define _TIMER_IF_ICFUF1_SHIFT 25 /**< Shift value for TIMER_ICFUF1 */
+#define _TIMER_IF_ICFUF1_MASK 0x2000000UL /**< Bit mask for TIMER_ICFUF1 */
+#define _TIMER_IF_ICFUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICFUF1_DEFAULT (_TIMER_IF_ICFUF1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICFUF2 (0x1UL << 26) /**< Input capture FIFO underflow */
+#define _TIMER_IF_ICFUF2_SHIFT 26 /**< Shift value for TIMER_ICFUF2 */
+#define _TIMER_IF_ICFUF2_MASK 0x4000000UL /**< Bit mask for TIMER_ICFUF2 */
+#define _TIMER_IF_ICFUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
+#define TIMER_IF_ICFUF2_DEFAULT (_TIMER_IF_ICFUF2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_IF */
+
+/* Bit fields for TIMER IEN */
+#define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */
+#define _TIMER_IEN_MASK 0x07770077UL /**< Mask for TIMER_IEN */
+#define TIMER_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */
+#define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */
+#define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
+#define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_UF (0x1UL << 1) /**< Underflow Interrupt Enable */
+#define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */
+#define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
+#define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Enable */
+#define _TIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
+#define _TIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
+#define _TIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_DIRCHG_DEFAULT (_TIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */
+#define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
+#define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
+#define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */
+#define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
+#define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
+#define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */
+#define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
+#define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
+#define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICFWLFULL0 (0x1UL << 16) /**< ICFWLFULL0 Interrupt Enable */
+#define _TIMER_IEN_ICFWLFULL0_SHIFT 16 /**< Shift value for TIMER_ICFWLFULL0 */
+#define _TIMER_IEN_ICFWLFULL0_MASK 0x10000UL /**< Bit mask for TIMER_ICFWLFULL0 */
+#define _TIMER_IEN_ICFWLFULL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICFWLFULL0_DEFAULT (_TIMER_IEN_ICFWLFULL0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICFWLFULL1 (0x1UL << 17) /**< ICFWLFULL1 Interrupt Enable */
+#define _TIMER_IEN_ICFWLFULL1_SHIFT 17 /**< Shift value for TIMER_ICFWLFULL1 */
+#define _TIMER_IEN_ICFWLFULL1_MASK 0x20000UL /**< Bit mask for TIMER_ICFWLFULL1 */
+#define _TIMER_IEN_ICFWLFULL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICFWLFULL1_DEFAULT (_TIMER_IEN_ICFWLFULL1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICFWLFULL2 (0x1UL << 18) /**< ICFWLFULL2 Interrupt Enable */
+#define _TIMER_IEN_ICFWLFULL2_SHIFT 18 /**< Shift value for TIMER_ICFWLFULL2 */
+#define _TIMER_IEN_ICFWLFULL2_MASK 0x40000UL /**< Bit mask for TIMER_ICFWLFULL2 */
+#define _TIMER_IEN_ICFWLFULL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICFWLFULL2_DEFAULT (_TIMER_IEN_ICFWLFULL2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICFOF0 (0x1UL << 20) /**< ICFOF0 Interrupt Enable */
+#define _TIMER_IEN_ICFOF0_SHIFT 20 /**< Shift value for TIMER_ICFOF0 */
+#define _TIMER_IEN_ICFOF0_MASK 0x100000UL /**< Bit mask for TIMER_ICFOF0 */
+#define _TIMER_IEN_ICFOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICFOF0_DEFAULT (_TIMER_IEN_ICFOF0_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICFOF1 (0x1UL << 21) /**< ICFOF1 Interrupt Enable */
+#define _TIMER_IEN_ICFOF1_SHIFT 21 /**< Shift value for TIMER_ICFOF1 */
+#define _TIMER_IEN_ICFOF1_MASK 0x200000UL /**< Bit mask for TIMER_ICFOF1 */
+#define _TIMER_IEN_ICFOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICFOF1_DEFAULT (_TIMER_IEN_ICFOF1_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICFOF2 (0x1UL << 22) /**< ICFOF2 Interrupt Enable */
+#define _TIMER_IEN_ICFOF2_SHIFT 22 /**< Shift value for TIMER_ICFOF2 */
+#define _TIMER_IEN_ICFOF2_MASK 0x400000UL /**< Bit mask for TIMER_ICFOF2 */
+#define _TIMER_IEN_ICFOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICFOF2_DEFAULT (_TIMER_IEN_ICFOF2_DEFAULT << 22) /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICFUF0 (0x1UL << 24) /**< ICFUF0 Interrupt Enable */
+#define _TIMER_IEN_ICFUF0_SHIFT 24 /**< Shift value for TIMER_ICFUF0 */
+#define _TIMER_IEN_ICFUF0_MASK 0x1000000UL /**< Bit mask for TIMER_ICFUF0 */
+#define _TIMER_IEN_ICFUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICFUF0_DEFAULT (_TIMER_IEN_ICFUF0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICFUF1 (0x1UL << 25) /**< ICFUF1 Interrupt Enable */
+#define _TIMER_IEN_ICFUF1_SHIFT 25 /**< Shift value for TIMER_ICFUF1 */
+#define _TIMER_IEN_ICFUF1_MASK 0x2000000UL /**< Bit mask for TIMER_ICFUF1 */
+#define _TIMER_IEN_ICFUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICFUF1_DEFAULT (_TIMER_IEN_ICFUF1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICFUF2 (0x1UL << 26) /**< ICFUF2 Interrupt Enable */
+#define _TIMER_IEN_ICFUF2_SHIFT 26 /**< Shift value for TIMER_ICFUF2 */
+#define _TIMER_IEN_ICFUF2_MASK 0x4000000UL /**< Bit mask for TIMER_ICFUF2 */
+#define _TIMER_IEN_ICFUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
+#define TIMER_IEN_ICFUF2_DEFAULT (_TIMER_IEN_ICFUF2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_IEN */
+
+/* Bit fields for TIMER TOP */
+#define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */
+#define _TIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for TIMER_TOP */
+#define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */
+#define _TIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */
+#define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */
+#define TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOP */
+
+/* Bit fields for TIMER TOPB */
+#define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */
+#define _TIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for TIMER_TOPB */
+#define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */
+#define _TIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */
+#define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */
+#define TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */
+
+/* Bit fields for TIMER CNT */
+#define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */
+#define _TIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CNT */
+#define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */
+#define _TIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */
+#define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */
+#define TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CNT */
+
+/* Bit fields for TIMER LOCK */
+#define _TIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_LOCK */
+#define _TIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_LOCK */
+#define _TIMER_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
+#define _TIMER_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
+#define _TIMER_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_LOCK */
+#define _TIMER_LOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_LOCK */
+#define TIMER_LOCK_LOCKKEY_DEFAULT (_TIMER_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_LOCK */
+#define TIMER_LOCK_LOCKKEY_UNLOCK (_TIMER_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_LOCK */
+
+/* Bit fields for TIMER EN */
+#define _TIMER_EN_RESETVALUE 0x00000000UL /**< Default value for TIMER_EN */
+#define _TIMER_EN_MASK 0x00000003UL /**< Mask for TIMER_EN */
+#define TIMER_EN_EN (0x1UL << 0) /**< Timer Module Enable */
+#define _TIMER_EN_EN_SHIFT 0 /**< Shift value for TIMER_EN */
+#define _TIMER_EN_EN_MASK 0x1UL /**< Bit mask for TIMER_EN */
+#define _TIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_EN */
+#define TIMER_EN_EN_DEFAULT (_TIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_EN */
+#define TIMER_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */
+#define _TIMER_EN_DISABLING_SHIFT 1 /**< Shift value for TIMER_DISABLING */
+#define _TIMER_EN_DISABLING_MASK 0x2UL /**< Bit mask for TIMER_DISABLING */
+#define _TIMER_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_EN */
+#define TIMER_EN_DISABLING_DEFAULT (_TIMER_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_EN */
+
+/* Bit fields for TIMER CC_CFG */
+#define _TIMER_CC_CFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CFG */
+#define _TIMER_CC_CFG_MASK 0x003E0013UL /**< Mask for TIMER_CC_CFG */
+#define _TIMER_CC_CFG_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
+#define _TIMER_CC_CFG_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
+#define _TIMER_CC_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */
+#define _TIMER_CC_CFG_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CFG */
+#define _TIMER_CC_CFG_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CFG */
+#define _TIMER_CC_CFG_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CFG */
+#define _TIMER_CC_CFG_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CFG */
+#define TIMER_CC_CFG_MODE_DEFAULT (_TIMER_CC_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CFG */
+#define TIMER_CC_CFG_MODE_OFF (_TIMER_CC_CFG_MODE_OFF << 0) /**< Shifted mode OFF for TIMER_CC_CFG */
+#define TIMER_CC_CFG_MODE_INPUTCAPTURE (_TIMER_CC_CFG_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CFG */
+#define TIMER_CC_CFG_MODE_OUTPUTCOMPARE (_TIMER_CC_CFG_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CFG */
+#define TIMER_CC_CFG_MODE_PWM (_TIMER_CC_CFG_MODE_PWM << 0) /**< Shifted mode PWM for TIMER_CC_CFG */
+#define TIMER_CC_CFG_COIST (0x1UL << 4) /**< Compare Output Initial State */
+#define _TIMER_CC_CFG_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */
+#define _TIMER_CC_CFG_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */
+#define _TIMER_CC_CFG_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */
+#define TIMER_CC_CFG_COIST_DEFAULT (_TIMER_CC_CFG_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CC_CFG */
+#define _TIMER_CC_CFG_INSEL_SHIFT 17 /**< Shift value for TIMER_INSEL */
+#define _TIMER_CC_CFG_INSEL_MASK 0x60000UL /**< Bit mask for TIMER_INSEL */
+#define _TIMER_CC_CFG_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */
+#define _TIMER_CC_CFG_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CFG */
+#define _TIMER_CC_CFG_INSEL_PRSSYNC 0x00000001UL /**< Mode PRSSYNC for TIMER_CC_CFG */
+#define _TIMER_CC_CFG_INSEL_PRSASYNCLEVEL 0x00000002UL /**< Mode PRSASYNCLEVEL for TIMER_CC_CFG */
+#define _TIMER_CC_CFG_INSEL_PRSASYNCPULSE 0x00000003UL /**< Mode PRSASYNCPULSE for TIMER_CC_CFG */
+#define TIMER_CC_CFG_INSEL_DEFAULT (_TIMER_CC_CFG_INSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_CC_CFG */
+#define TIMER_CC_CFG_INSEL_PIN (_TIMER_CC_CFG_INSEL_PIN << 17) /**< Shifted mode PIN for TIMER_CC_CFG */
+#define TIMER_CC_CFG_INSEL_PRSSYNC (_TIMER_CC_CFG_INSEL_PRSSYNC << 17) /**< Shifted mode PRSSYNC for TIMER_CC_CFG */
+#define TIMER_CC_CFG_INSEL_PRSASYNCLEVEL (_TIMER_CC_CFG_INSEL_PRSASYNCLEVEL << 17) /**< Shifted mode PRSASYNCLEVEL for TIMER_CC_CFG */
+#define TIMER_CC_CFG_INSEL_PRSASYNCPULSE (_TIMER_CC_CFG_INSEL_PRSASYNCPULSE << 17) /**< Shifted mode PRSASYNCPULSE for TIMER_CC_CFG */
+#define TIMER_CC_CFG_PRSCONF (0x1UL << 19) /**< PRS Configuration */
+#define _TIMER_CC_CFG_PRSCONF_SHIFT 19 /**< Shift value for TIMER_PRSCONF */
+#define _TIMER_CC_CFG_PRSCONF_MASK 0x80000UL /**< Bit mask for TIMER_PRSCONF */
+#define _TIMER_CC_CFG_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */
+#define _TIMER_CC_CFG_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for TIMER_CC_CFG */
+#define _TIMER_CC_CFG_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for TIMER_CC_CFG */
+#define TIMER_CC_CFG_PRSCONF_DEFAULT (_TIMER_CC_CFG_PRSCONF_DEFAULT << 19) /**< Shifted mode DEFAULT for TIMER_CC_CFG */
+#define TIMER_CC_CFG_PRSCONF_PULSE (_TIMER_CC_CFG_PRSCONF_PULSE << 19) /**< Shifted mode PULSE for TIMER_CC_CFG */
+#define TIMER_CC_CFG_PRSCONF_LEVEL (_TIMER_CC_CFG_PRSCONF_LEVEL << 19) /**< Shifted mode LEVEL for TIMER_CC_CFG */
+#define TIMER_CC_CFG_FILT (0x1UL << 20) /**< Digital Filter */
+#define _TIMER_CC_CFG_FILT_SHIFT 20 /**< Shift value for TIMER_FILT */
+#define _TIMER_CC_CFG_FILT_MASK 0x100000UL /**< Bit mask for TIMER_FILT */
+#define _TIMER_CC_CFG_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */
+#define _TIMER_CC_CFG_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CFG */
+#define _TIMER_CC_CFG_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CFG */
+#define TIMER_CC_CFG_FILT_DEFAULT (_TIMER_CC_CFG_FILT_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_CC_CFG */
+#define TIMER_CC_CFG_FILT_DISABLE (_TIMER_CC_CFG_FILT_DISABLE << 20) /**< Shifted mode DISABLE for TIMER_CC_CFG */
+#define TIMER_CC_CFG_FILT_ENABLE (_TIMER_CC_CFG_FILT_ENABLE << 20) /**< Shifted mode ENABLE for TIMER_CC_CFG */
+#define TIMER_CC_CFG_ICFWL (0x1UL << 21) /**< Input Capture FIFO watermark level */
+#define _TIMER_CC_CFG_ICFWL_SHIFT 21 /**< Shift value for TIMER_ICFWL */
+#define _TIMER_CC_CFG_ICFWL_MASK 0x200000UL /**< Bit mask for TIMER_ICFWL */
+#define _TIMER_CC_CFG_ICFWL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */
+#define TIMER_CC_CFG_ICFWL_DEFAULT (_TIMER_CC_CFG_ICFWL_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_CC_CFG */
+
+/* Bit fields for TIMER CC_CTRL */
+#define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_MASK 0x0F003F04UL /**< Mask for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */
+#define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */
+#define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */
+#define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */
+#define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */
+#define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */
+#define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */
+#define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */
+#define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */
+#define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */
+#define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */
+#define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */
+#define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */
+#define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */
+#define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL*/
+#define TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */
+#define TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */
+
+/* Bit fields for TIMER CC_OC */
+#define _TIMER_CC_OC_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_OC */
+#define _TIMER_CC_OC_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_OC */
+#define _TIMER_CC_OC_OC_SHIFT 0 /**< Shift value for TIMER_OC */
+#define _TIMER_CC_OC_OC_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_OC */
+#define _TIMER_CC_OC_OC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_OC */
+#define TIMER_CC_OC_OC_DEFAULT (_TIMER_CC_OC_OC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_OC */
+
+/* Bit fields for TIMER CC_OCB */
+#define _TIMER_CC_OCB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_OCB */
+#define _TIMER_CC_OCB_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_OCB */
+#define _TIMER_CC_OCB_OCB_SHIFT 0 /**< Shift value for TIMER_OCB */
+#define _TIMER_CC_OCB_OCB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_OCB */
+#define _TIMER_CC_OCB_OCB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_OCB */
+#define TIMER_CC_OCB_OCB_DEFAULT (_TIMER_CC_OCB_OCB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_OCB */
+
+/* Bit fields for TIMER CC_ICF */
+#define _TIMER_CC_ICF_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_ICF */
+#define _TIMER_CC_ICF_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_ICF */
+#define _TIMER_CC_ICF_ICF_SHIFT 0 /**< Shift value for TIMER_ICF */
+#define _TIMER_CC_ICF_ICF_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_ICF */
+#define _TIMER_CC_ICF_ICF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_ICF */
+#define TIMER_CC_ICF_ICF_DEFAULT (_TIMER_CC_ICF_ICF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_ICF */
+
+/* Bit fields for TIMER CC_ICOF */
+#define _TIMER_CC_ICOF_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_ICOF */
+#define _TIMER_CC_ICOF_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_ICOF */
+#define _TIMER_CC_ICOF_ICOF_SHIFT 0 /**< Shift value for TIMER_ICOF */
+#define _TIMER_CC_ICOF_ICOF_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_ICOF */
+#define _TIMER_CC_ICOF_ICOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_ICOF */
+#define TIMER_CC_ICOF_ICOF_DEFAULT (_TIMER_CC_ICOF_ICOF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_ICOF */
+
+/* Bit fields for TIMER DTCFG */
+#define _TIMER_DTCFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCFG */
+#define _TIMER_DTCFG_MASK 0x00000E03UL /**< Mask for TIMER_DTCFG */
+#define TIMER_DTCFG_DTEN (0x1UL << 0) /**< DTI Enable */
+#define _TIMER_DTCFG_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */
+#define _TIMER_DTCFG_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */
+#define _TIMER_DTCFG_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */
+#define TIMER_DTCFG_DTEN_DEFAULT (_TIMER_DTCFG_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCFG */
+#define TIMER_DTCFG_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */
+#define _TIMER_DTCFG_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */
+#define _TIMER_DTCFG_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */
+#define _TIMER_DTCFG_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */
+#define _TIMER_DTCFG_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCFG */
+#define _TIMER_DTCFG_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCFG */
+#define TIMER_DTCFG_DTDAS_DEFAULT (_TIMER_DTCFG_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCFG */
+#define TIMER_DTCFG_DTDAS_NORESTART (_TIMER_DTCFG_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for TIMER_DTCFG */
+#define TIMER_DTCFG_DTDAS_RESTART (_TIMER_DTCFG_DTDAS_RESTART << 1) /**< Shifted mode RESTART for TIMER_DTCFG */
+#define TIMER_DTCFG_DTAR (0x1UL << 9) /**< DTI Always Run */
+#define _TIMER_DTCFG_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */
+#define _TIMER_DTCFG_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */
+#define _TIMER_DTCFG_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */
+#define TIMER_DTCFG_DTAR_DEFAULT (_TIMER_DTCFG_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_DTCFG */
+#define TIMER_DTCFG_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */
+#define _TIMER_DTCFG_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */
+#define _TIMER_DTCFG_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */
+#define _TIMER_DTCFG_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */
+#define TIMER_DTCFG_DTFATS_DEFAULT (_TIMER_DTCFG_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTCFG */
+#define TIMER_DTCFG_DTPRSEN (0x1UL << 11) /**< DTI PRS Source Enable */
+#define _TIMER_DTCFG_DTPRSEN_SHIFT 11 /**< Shift value for TIMER_DTPRSEN */
+#define _TIMER_DTCFG_DTPRSEN_MASK 0x800UL /**< Bit mask for TIMER_DTPRSEN */
+#define _TIMER_DTCFG_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */
+#define TIMER_DTCFG_DTPRSEN_DEFAULT (_TIMER_DTCFG_DTPRSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_DTCFG */
+
+/* Bit fields for TIMER DTTIMECFG */
+#define _TIMER_DTTIMECFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIMECFG */
+#define _TIMER_DTTIMECFG_MASK 0x003FFFFFUL /**< Mask for TIMER_DTTIMECFG */
+#define _TIMER_DTTIMECFG_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */
+#define _TIMER_DTTIMECFG_DTPRESC_MASK 0x3FFUL /**< Bit mask for TIMER_DTPRESC */
+#define _TIMER_DTTIMECFG_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */
+#define TIMER_DTTIMECFG_DTPRESC_DEFAULT (_TIMER_DTTIMECFG_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */
+#define _TIMER_DTTIMECFG_DTRISET_SHIFT 10 /**< Shift value for TIMER_DTRISET */
+#define _TIMER_DTTIMECFG_DTRISET_MASK 0xFC00UL /**< Bit mask for TIMER_DTRISET */
+#define _TIMER_DTTIMECFG_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */
+#define TIMER_DTTIMECFG_DTRISET_DEFAULT (_TIMER_DTTIMECFG_DTRISET_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */
+#define _TIMER_DTTIMECFG_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */
+#define _TIMER_DTTIMECFG_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */
+#define _TIMER_DTTIMECFG_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */
+#define TIMER_DTTIMECFG_DTFALLT_DEFAULT (_TIMER_DTTIMECFG_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */
+
+/* Bit fields for TIMER DTFCFG */
+#define _TIMER_DTFCFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFCFG */
+#define _TIMER_DTFCFG_MASK 0x1F030000UL /**< Mask for TIMER_DTFCFG */
+#define _TIMER_DTFCFG_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */
+#define _TIMER_DTFCFG_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */
+#define _TIMER_DTFCFG_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */
+#define _TIMER_DTFCFG_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFCFG */
+#define _TIMER_DTFCFG_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFCFG */
+#define _TIMER_DTFCFG_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFCFG */
+#define _TIMER_DTFCFG_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFCFG */
+#define TIMER_DTFCFG_DTFA_DEFAULT (_TIMER_DTFCFG_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTFCFG */
+#define TIMER_DTFCFG_DTFA_NONE (_TIMER_DTFCFG_DTFA_NONE << 16) /**< Shifted mode NONE for TIMER_DTFCFG */
+#define TIMER_DTFCFG_DTFA_INACTIVE (_TIMER_DTFCFG_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for TIMER_DTFCFG */
+#define TIMER_DTFCFG_DTFA_CLEAR (_TIMER_DTFCFG_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for TIMER_DTFCFG */
+#define TIMER_DTFCFG_DTFA_TRISTATE (_TIMER_DTFCFG_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for TIMER_DTFCFG */
+#define TIMER_DTFCFG_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */
+#define _TIMER_DTFCFG_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */
+#define _TIMER_DTFCFG_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */
+#define _TIMER_DTFCFG_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */
+#define TIMER_DTFCFG_DTPRS0FEN_DEFAULT (_TIMER_DTFCFG_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTFCFG */
+#define TIMER_DTFCFG_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */
+#define _TIMER_DTFCFG_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */
+#define _TIMER_DTFCFG_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */
+#define _TIMER_DTFCFG_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */
+#define TIMER_DTFCFG_DTPRS1FEN_DEFAULT (_TIMER_DTFCFG_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_DTFCFG */
+#define TIMER_DTFCFG_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */
+#define _TIMER_DTFCFG_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */
+#define _TIMER_DTFCFG_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */
+#define _TIMER_DTFCFG_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */
+#define TIMER_DTFCFG_DTDBGFEN_DEFAULT (_TIMER_DTFCFG_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_DTFCFG */
+#define TIMER_DTFCFG_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */
+#define _TIMER_DTFCFG_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */
+#define _TIMER_DTFCFG_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */
+#define _TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */
+#define TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT (_TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_DTFCFG */
+#define TIMER_DTFCFG_DTEM23FEN (0x1UL << 28) /**< DTI EM23 Fault Enable */
+#define _TIMER_DTFCFG_DTEM23FEN_SHIFT 28 /**< Shift value for TIMER_DTEM23FEN */
+#define _TIMER_DTFCFG_DTEM23FEN_MASK 0x10000000UL /**< Bit mask for TIMER_DTEM23FEN */
+#define _TIMER_DTFCFG_DTEM23FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */
+#define TIMER_DTFCFG_DTEM23FEN_DEFAULT (_TIMER_DTFCFG_DTEM23FEN_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_DTFCFG */
+
+/* Bit fields for TIMER DTCTRL */
+#define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */
+#define _TIMER_DTCTRL_MASK 0x00000003UL /**< Mask for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTCINV (0x1UL << 0) /**< DTI Complementary Output Invert. */
+#define _TIMER_DTCTRL_DTCINV_SHIFT 0 /**< Shift value for TIMER_DTCINV */
+#define _TIMER_DTCTRL_DTCINV_MASK 0x1UL /**< Bit mask for TIMER_DTCINV */
+#define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTIPOL (0x1UL << 1) /**< DTI Inactive Polarity */
+#define _TIMER_DTCTRL_DTIPOL_SHIFT 1 /**< Shift value for TIMER_DTIPOL */
+#define _TIMER_DTCTRL_DTIPOL_MASK 0x2UL /**< Bit mask for TIMER_DTIPOL */
+#define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
+#define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
+
+/* Bit fields for TIMER DTOGEN */
+#define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */
+#define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CCn Output Generation Enable */
+#define _TIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */
+#define _TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */
+#define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CCn Output Generation Enable */
+#define _TIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */
+#define _TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */
+#define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CCn Output Generation Enable */
+#define _TIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */
+#define _TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */
+#define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTIn Output Generation Enable */
+#define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */
+#define _TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */
+#define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTIn Output Generation Enable */
+#define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */
+#define _TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */
+#define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTIn Output Generation Enable */
+#define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */
+#define _TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */
+#define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
+#define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
+
+/* Bit fields for TIMER DTFAULT */
+#define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */
+#define _TIMER_DTFAULT_MASK 0x0000001FUL /**< Mask for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */
+#define _TIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */
+#define _TIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */
+#define _TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */
+#define _TIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */
+#define _TIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */
+#define _TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */
+#define _TIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */
+#define _TIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */
+#define _TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */
+#define _TIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */
+#define _TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */
+#define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTEM23F (0x1UL << 4) /**< DTI EM23 Entry Fault */
+#define _TIMER_DTFAULT_DTEM23F_SHIFT 4 /**< Shift value for TIMER_DTEM23F */
+#define _TIMER_DTFAULT_DTEM23F_MASK 0x10UL /**< Bit mask for TIMER_DTEM23F */
+#define _TIMER_DTFAULT_DTEM23F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */
+#define TIMER_DTFAULT_DTEM23F_DEFAULT (_TIMER_DTFAULT_DTEM23F_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
+
+/* Bit fields for TIMER DTFAULTC */
+#define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */
+#define _TIMER_DTFAULTC_MASK 0x0000001FUL /**< Mask for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */
+#define _TIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */
+#define _TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */
+#define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */
+#define _TIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */
+#define _TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */
+#define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */
+#define _TIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */
+#define _TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */
+#define _TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_DTLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */
+#define _TIMER_DTFAULTC_DTLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPFC */
+#define _TIMER_DTFAULTC_DTLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPFC */
+#define _TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_DTEM23FC (0x1UL << 4) /**< DTI EM23 Fault Clear */
+#define _TIMER_DTFAULTC_DTEM23FC_SHIFT 4 /**< Shift value for TIMER_DTEM23FC */
+#define _TIMER_DTFAULTC_DTEM23FC_MASK 0x10UL /**< Bit mask for TIMER_DTEM23FC */
+#define _TIMER_DTFAULTC_DTEM23FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */
+#define TIMER_DTFAULTC_DTEM23FC_DEFAULT (_TIMER_DTFAULTC_DTEM23FC_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
+
+/* Bit fields for TIMER DTLOCK */
+#define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */
+#define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */
+#define _TIMER_DTLOCK_DTILOCKKEY_SHIFT 0 /**< Shift value for TIMER_DTILOCKKEY */
+#define _TIMER_DTLOCK_DTILOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_DTILOCKKEY */
+#define _TIMER_DTLOCK_DTILOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */
+#define _TIMER_DTLOCK_DTILOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */
+#define TIMER_DTLOCK_DTILOCKKEY_DEFAULT (_TIMER_DTLOCK_DTILOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */
+#define TIMER_DTLOCK_DTILOCKKEY_UNLOCK (_TIMER_DTLOCK_DTILOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */
+
+/** @} End of group EFR32MG24_TIMER_BitFields */
+/** @} End of group EFR32MG24_TIMER */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_TIMER_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_ulfrco.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_ulfrco.h
new file mode 100644
index 00000000..f621de43
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_ulfrco.h
@@ -0,0 +1,147 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 ULFRCO register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_ULFRCO_H
+#define EFR32MG24_ULFRCO_H
+#define ULFRCO_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_ULFRCO ULFRCO
+ * @{
+ * @brief EFR32MG24 ULFRCO Register Declaration.
+ *****************************************************************************/
+
+/** ULFRCO Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IP version */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+ __IM uint32_t STATUS; /**< Status Register */
+ uint32_t RESERVED1[2U]; /**< Reserved for future use */
+ __IOM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ uint32_t RESERVED2[1017U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP version */
+ uint32_t RESERVED3[1U]; /**< Reserved for future use */
+ __IM uint32_t STATUS_SET; /**< Status Register */
+ uint32_t RESERVED4[2U]; /**< Reserved for future use */
+ __IOM uint32_t IF_SET; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
+ uint32_t RESERVED5[1017U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP version */
+ uint32_t RESERVED6[1U]; /**< Reserved for future use */
+ __IM uint32_t STATUS_CLR; /**< Status Register */
+ uint32_t RESERVED7[2U]; /**< Reserved for future use */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
+ uint32_t RESERVED8[1017U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP version */
+ uint32_t RESERVED9[1U]; /**< Reserved for future use */
+ __IM uint32_t STATUS_TGL; /**< Status Register */
+ uint32_t RESERVED10[2U]; /**< Reserved for future use */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
+} ULFRCO_TypeDef;
+/** @} End of group EFR32MG24_ULFRCO */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_ULFRCO
+ * @{
+ * @defgroup EFR32MG24_ULFRCO_BitFields ULFRCO Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for ULFRCO IPVERSION */
+#define _ULFRCO_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for ULFRCO_IPVERSION */
+#define _ULFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ULFRCO_IPVERSION */
+#define _ULFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ULFRCO_IPVERSION */
+#define _ULFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ULFRCO_IPVERSION */
+#define _ULFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for ULFRCO_IPVERSION */
+#define ULFRCO_IPVERSION_IPVERSION_DEFAULT (_ULFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IPVERSION */
+
+/* Bit fields for ULFRCO STATUS */
+#define _ULFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_STATUS */
+#define _ULFRCO_STATUS_MASK 0x00010001UL /**< Mask for ULFRCO_STATUS */
+#define ULFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */
+#define _ULFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */
+#define _ULFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */
+#define _ULFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */
+#define ULFRCO_STATUS_RDY_DEFAULT (_ULFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_STATUS */
+#define ULFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */
+#define _ULFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for ULFRCO_ENS */
+#define _ULFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for ULFRCO_ENS */
+#define _ULFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */
+#define ULFRCO_STATUS_ENS_DEFAULT (_ULFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for ULFRCO_STATUS */
+
+/* Bit fields for ULFRCO IF */
+#define _ULFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IF */
+#define _ULFRCO_IF_MASK 0x00000007UL /**< Mask for ULFRCO_IF */
+#define ULFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */
+#define _ULFRCO_IF_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */
+#define _ULFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */
+#define _ULFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */
+#define ULFRCO_IF_RDY_DEFAULT (_ULFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IF */
+#define ULFRCO_IF_POSEDGE (0x1UL << 1) /**< Positive Edge Interrupt Flag */
+#define _ULFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */
+#define _ULFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */
+#define _ULFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */
+#define ULFRCO_IF_POSEDGE_DEFAULT (_ULFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IF */
+#define ULFRCO_IF_NEGEDGE (0x1UL << 2) /**< Negative Edge Interrupt Flag */
+#define _ULFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */
+#define _ULFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */
+#define _ULFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */
+#define ULFRCO_IF_NEGEDGE_DEFAULT (_ULFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IF */
+
+/* Bit fields for ULFRCO IEN */
+#define _ULFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IEN */
+#define _ULFRCO_IEN_MASK 0x00000007UL /**< Mask for ULFRCO_IEN */
+#define ULFRCO_IEN_RDY (0x1UL << 0) /**< Enable Ready Interrupt */
+#define _ULFRCO_IEN_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */
+#define _ULFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */
+#define _ULFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */
+#define ULFRCO_IEN_RDY_DEFAULT (_ULFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IEN */
+#define ULFRCO_IEN_POSEDGE (0x1UL << 1) /**< Enable Positive Edge Interrupt */
+#define _ULFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */
+#define _ULFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */
+#define _ULFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */
+#define ULFRCO_IEN_POSEDGE_DEFAULT (_ULFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IEN */
+#define ULFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Enable Negative Edge Interrupt */
+#define _ULFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */
+#define _ULFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */
+#define _ULFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */
+#define ULFRCO_IEN_NEGEDGE_DEFAULT (_ULFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IEN */
+
+/** @} End of group EFR32MG24_ULFRCO_BitFields */
+/** @} End of group EFR32MG24_ULFRCO */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_ULFRCO_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_usart.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_usart.h
new file mode 100644
index 00000000..2d086abc
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_usart.h
@@ -0,0 +1,1431 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 USART register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_USART_H
+#define EFR32MG24_USART_H
+#define USART_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_USART USART
+ * @{
+ * @brief EFR32MG24 USART Register Declaration.
+ *****************************************************************************/
+
+/** USART Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IPVERSION */
+ __IOM uint32_t EN; /**< USART Enable */
+ __IOM uint32_t CTRL; /**< Control Register */
+ __IOM uint32_t FRAME; /**< USART Frame Format Register */
+ __IOM uint32_t TRIGCTRL; /**< USART Trigger Control register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IM uint32_t STATUS; /**< USART Status Register */
+ __IOM uint32_t CLKDIV; /**< Clock Control Register */
+ __IM uint32_t RXDATAX; /**< RX Buffer Data Extended Register */
+ __IM uint32_t RXDATA; /**< RX Buffer Data Register */
+ __IM uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */
+ __IM uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */
+ __IM uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */
+ __IM uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek R... */
+ __IOM uint32_t TXDATAX; /**< TX Buffer Data Extended Register */
+ __IOM uint32_t TXDATA; /**< TX Buffer Data Register */
+ __IOM uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */
+ __IOM uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */
+ __IOM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IOM uint32_t IRCTRL; /**< IrDA Control Register */
+ __IOM uint32_t I2SCTRL; /**< I2S Control Register */
+ __IOM uint32_t TIMING; /**< Timing Register */
+ __IOM uint32_t CTRLX; /**< Control Register Extended */
+ __IOM uint32_t TIMECMP0; /**< Timer Compare 0 */
+ __IOM uint32_t TIMECMP1; /**< Timer Compare 1 */
+ __IOM uint32_t TIMECMP2; /**< Timer Compare 2 */
+ uint32_t RESERVED0[997U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IPVERSION */
+ __IOM uint32_t EN_SET; /**< USART Enable */
+ __IOM uint32_t CTRL_SET; /**< Control Register */
+ __IOM uint32_t FRAME_SET; /**< USART Frame Format Register */
+ __IOM uint32_t TRIGCTRL_SET; /**< USART Trigger Control register */
+ __IOM uint32_t CMD_SET; /**< Command Register */
+ __IM uint32_t STATUS_SET; /**< USART Status Register */
+ __IOM uint32_t CLKDIV_SET; /**< Clock Control Register */
+ __IM uint32_t RXDATAX_SET; /**< RX Buffer Data Extended Register */
+ __IM uint32_t RXDATA_SET; /**< RX Buffer Data Register */
+ __IM uint32_t RXDOUBLEX_SET; /**< RX Buffer Double Data Extended Register */
+ __IM uint32_t RXDOUBLE_SET; /**< RX FIFO Double Data Register */
+ __IM uint32_t RXDATAXP_SET; /**< RX Buffer Data Extended Peek Register */
+ __IM uint32_t RXDOUBLEXP_SET; /**< RX Buffer Double Data Extended Peek R... */
+ __IOM uint32_t TXDATAX_SET; /**< TX Buffer Data Extended Register */
+ __IOM uint32_t TXDATA_SET; /**< TX Buffer Data Register */
+ __IOM uint32_t TXDOUBLEX_SET; /**< TX Buffer Double Data Extended Register */
+ __IOM uint32_t TXDOUBLE_SET; /**< TX Buffer Double Data Register */
+ __IOM uint32_t IF_SET; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
+ __IOM uint32_t IRCTRL_SET; /**< IrDA Control Register */
+ __IOM uint32_t I2SCTRL_SET; /**< I2S Control Register */
+ __IOM uint32_t TIMING_SET; /**< Timing Register */
+ __IOM uint32_t CTRLX_SET; /**< Control Register Extended */
+ __IOM uint32_t TIMECMP0_SET; /**< Timer Compare 0 */
+ __IOM uint32_t TIMECMP1_SET; /**< Timer Compare 1 */
+ __IOM uint32_t TIMECMP2_SET; /**< Timer Compare 2 */
+ uint32_t RESERVED1[997U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IPVERSION */
+ __IOM uint32_t EN_CLR; /**< USART Enable */
+ __IOM uint32_t CTRL_CLR; /**< Control Register */
+ __IOM uint32_t FRAME_CLR; /**< USART Frame Format Register */
+ __IOM uint32_t TRIGCTRL_CLR; /**< USART Trigger Control register */
+ __IOM uint32_t CMD_CLR; /**< Command Register */
+ __IM uint32_t STATUS_CLR; /**< USART Status Register */
+ __IOM uint32_t CLKDIV_CLR; /**< Clock Control Register */
+ __IM uint32_t RXDATAX_CLR; /**< RX Buffer Data Extended Register */
+ __IM uint32_t RXDATA_CLR; /**< RX Buffer Data Register */
+ __IM uint32_t RXDOUBLEX_CLR; /**< RX Buffer Double Data Extended Register */
+ __IM uint32_t RXDOUBLE_CLR; /**< RX FIFO Double Data Register */
+ __IM uint32_t RXDATAXP_CLR; /**< RX Buffer Data Extended Peek Register */
+ __IM uint32_t RXDOUBLEXP_CLR; /**< RX Buffer Double Data Extended Peek R... */
+ __IOM uint32_t TXDATAX_CLR; /**< TX Buffer Data Extended Register */
+ __IOM uint32_t TXDATA_CLR; /**< TX Buffer Data Register */
+ __IOM uint32_t TXDOUBLEX_CLR; /**< TX Buffer Double Data Extended Register */
+ __IOM uint32_t TXDOUBLE_CLR; /**< TX Buffer Double Data Register */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
+ __IOM uint32_t IRCTRL_CLR; /**< IrDA Control Register */
+ __IOM uint32_t I2SCTRL_CLR; /**< I2S Control Register */
+ __IOM uint32_t TIMING_CLR; /**< Timing Register */
+ __IOM uint32_t CTRLX_CLR; /**< Control Register Extended */
+ __IOM uint32_t TIMECMP0_CLR; /**< Timer Compare 0 */
+ __IOM uint32_t TIMECMP1_CLR; /**< Timer Compare 1 */
+ __IOM uint32_t TIMECMP2_CLR; /**< Timer Compare 2 */
+ uint32_t RESERVED2[997U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IPVERSION */
+ __IOM uint32_t EN_TGL; /**< USART Enable */
+ __IOM uint32_t CTRL_TGL; /**< Control Register */
+ __IOM uint32_t FRAME_TGL; /**< USART Frame Format Register */
+ __IOM uint32_t TRIGCTRL_TGL; /**< USART Trigger Control register */
+ __IOM uint32_t CMD_TGL; /**< Command Register */
+ __IM uint32_t STATUS_TGL; /**< USART Status Register */
+ __IOM uint32_t CLKDIV_TGL; /**< Clock Control Register */
+ __IM uint32_t RXDATAX_TGL; /**< RX Buffer Data Extended Register */
+ __IM uint32_t RXDATA_TGL; /**< RX Buffer Data Register */
+ __IM uint32_t RXDOUBLEX_TGL; /**< RX Buffer Double Data Extended Register */
+ __IM uint32_t RXDOUBLE_TGL; /**< RX FIFO Double Data Register */
+ __IM uint32_t RXDATAXP_TGL; /**< RX Buffer Data Extended Peek Register */
+ __IM uint32_t RXDOUBLEXP_TGL; /**< RX Buffer Double Data Extended Peek R... */
+ __IOM uint32_t TXDATAX_TGL; /**< TX Buffer Data Extended Register */
+ __IOM uint32_t TXDATA_TGL; /**< TX Buffer Data Register */
+ __IOM uint32_t TXDOUBLEX_TGL; /**< TX Buffer Double Data Extended Register */
+ __IOM uint32_t TXDOUBLE_TGL; /**< TX Buffer Double Data Register */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
+ __IOM uint32_t IRCTRL_TGL; /**< IrDA Control Register */
+ __IOM uint32_t I2SCTRL_TGL; /**< I2S Control Register */
+ __IOM uint32_t TIMING_TGL; /**< Timing Register */
+ __IOM uint32_t CTRLX_TGL; /**< Control Register Extended */
+ __IOM uint32_t TIMECMP0_TGL; /**< Timer Compare 0 */
+ __IOM uint32_t TIMECMP1_TGL; /**< Timer Compare 1 */
+ __IOM uint32_t TIMECMP2_TGL; /**< Timer Compare 2 */
+} USART_TypeDef;
+/** @} End of group EFR32MG24_USART */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_USART
+ * @{
+ * @defgroup EFR32MG24_USART_BitFields USART Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for USART IPVERSION */
+#define _USART_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for USART_IPVERSION */
+#define _USART_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for USART_IPVERSION */
+#define _USART_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for USART_IPVERSION */
+#define _USART_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for USART_IPVERSION */
+#define _USART_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IPVERSION */
+#define USART_IPVERSION_IPVERSION_DEFAULT (_USART_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IPVERSION */
+
+/* Bit fields for USART EN */
+#define _USART_EN_RESETVALUE 0x00000000UL /**< Default value for USART_EN */
+#define _USART_EN_MASK 0x00000001UL /**< Mask for USART_EN */
+#define USART_EN_EN (0x1UL << 0) /**< USART Enable */
+#define _USART_EN_EN_SHIFT 0 /**< Shift value for USART_EN */
+#define _USART_EN_EN_MASK 0x1UL /**< Bit mask for USART_EN */
+#define _USART_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_EN */
+#define USART_EN_EN_DEFAULT (_USART_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_EN */
+
+/* Bit fields for USART CTRL */
+#define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */
+#define _USART_CTRL_MASK 0xF3FFFF7FUL /**< Mask for USART_CTRL */
+#define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */
+#define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */
+#define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */
+#define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define _USART_CTRL_SYNC_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */
+#define _USART_CTRL_SYNC_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */
+#define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SYNC_DISABLE (_USART_CTRL_SYNC_DISABLE << 0) /**< Shifted mode DISABLE for USART_CTRL */
+#define USART_CTRL_SYNC_ENABLE (_USART_CTRL_SYNC_ENABLE << 0) /**< Shifted mode ENABLE for USART_CTRL */
+#define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */
+#define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */
+#define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */
+#define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define _USART_CTRL_LOOPBK_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */
+#define _USART_CTRL_LOOPBK_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */
+#define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_LOOPBK_DISABLE (_USART_CTRL_LOOPBK_DISABLE << 1) /**< Shifted mode DISABLE for USART_CTRL */
+#define USART_CTRL_LOOPBK_ENABLE (_USART_CTRL_LOOPBK_ENABLE << 1) /**< Shifted mode ENABLE for USART_CTRL */
+#define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */
+#define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */
+#define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */
+#define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define _USART_CTRL_CCEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */
+#define _USART_CTRL_CCEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */
+#define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_CCEN_DISABLE (_USART_CTRL_CCEN_DISABLE << 2) /**< Shifted mode DISABLE for USART_CTRL */
+#define USART_CTRL_CCEN_ENABLE (_USART_CTRL_CCEN_ENABLE << 2) /**< Shifted mode ENABLE for USART_CTRL */
+#define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */
+#define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */
+#define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */
+#define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define _USART_CTRL_MPM_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */
+#define _USART_CTRL_MPM_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */
+#define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_MPM_DISABLE (_USART_CTRL_MPM_DISABLE << 3) /**< Shifted mode DISABLE for USART_CTRL */
+#define USART_CTRL_MPM_ENABLE (_USART_CTRL_MPM_ENABLE << 3) /**< Shifted mode ENABLE for USART_CTRL */
+#define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */
+#define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */
+#define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */
+#define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */
+#define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */
+#define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */
+#define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */
+#define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */
+#define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */
+#define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */
+#define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */
+#define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */
+#define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */
+#define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */
+#define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */
+#define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */
+#define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */
+#define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */
+#define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */
+#define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */
+#define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */
+#define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */
+#define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */
+#define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */
+#define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */
+#define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */
+#define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */
+#define USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */
+#define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */
+#define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */
+#define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */
+#define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define _USART_CTRL_MSBF_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */
+#define _USART_CTRL_MSBF_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */
+#define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_MSBF_DISABLE (_USART_CTRL_MSBF_DISABLE << 10) /**< Shifted mode DISABLE for USART_CTRL */
+#define USART_CTRL_MSBF_ENABLE (_USART_CTRL_MSBF_ENABLE << 10) /**< Shifted mode ENABLE for USART_CTRL */
+#define USART_CTRL_CSMA (0x1UL << 11) /**< Action On Chip Select In Main Mode */
+#define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */
+#define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */
+#define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */
+#define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */
+#define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */
+#define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */
+#define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */
+#define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */
+#define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */
+#define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */
+#define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */
+#define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */
+#define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */
+#define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */
+#define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */
+#define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */
+#define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define _USART_CTRL_RXINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */
+#define _USART_CTRL_RXINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */
+#define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_RXINV_DISABLE (_USART_CTRL_RXINV_DISABLE << 13) /**< Shifted mode DISABLE for USART_CTRL */
+#define USART_CTRL_RXINV_ENABLE (_USART_CTRL_RXINV_ENABLE << 13) /**< Shifted mode ENABLE for USART_CTRL */
+#define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */
+#define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */
+#define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */
+#define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define _USART_CTRL_TXINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */
+#define _USART_CTRL_TXINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */
+#define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_TXINV_DISABLE (_USART_CTRL_TXINV_DISABLE << 14) /**< Shifted mode DISABLE for USART_CTRL */
+#define USART_CTRL_TXINV_ENABLE (_USART_CTRL_TXINV_ENABLE << 14) /**< Shifted mode ENABLE for USART_CTRL */
+#define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */
+#define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */
+#define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */
+#define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define _USART_CTRL_CSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */
+#define _USART_CTRL_CSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */
+#define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_CSINV_DISABLE (_USART_CTRL_CSINV_DISABLE << 15) /**< Shifted mode DISABLE for USART_CTRL */
+#define USART_CTRL_CSINV_ENABLE (_USART_CTRL_CSINV_ENABLE << 15) /**< Shifted mode ENABLE for USART_CTRL */
+#define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */
+#define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */
+#define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */
+#define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */
+#define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */
+#define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */
+#define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define _USART_CTRL_AUTOTRI_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */
+#define _USART_CTRL_AUTOTRI_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */
+#define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_AUTOTRI_DISABLE (_USART_CTRL_AUTOTRI_DISABLE << 17) /**< Shifted mode DISABLE for USART_CTRL */
+#define USART_CTRL_AUTOTRI_ENABLE (_USART_CTRL_AUTOTRI_ENABLE << 17) /**< Shifted mode ENABLE for USART_CTRL */
+#define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */
+#define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */
+#define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */
+#define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */
+#define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */
+#define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */
+#define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */
+#define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */
+#define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */
+#define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */
+#define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */
+#define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */
+#define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */
+#define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */
+#define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */
+#define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define _USART_CTRL_ERRSDMA_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */
+#define _USART_CTRL_ERRSDMA_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */
+#define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_ERRSDMA_DISABLE (_USART_CTRL_ERRSDMA_DISABLE << 22) /**< Shifted mode DISABLE for USART_CTRL */
+#define USART_CTRL_ERRSDMA_ENABLE (_USART_CTRL_ERRSDMA_ENABLE << 22) /**< Shifted mode ENABLE for USART_CTRL */
+#define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */
+#define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */
+#define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */
+#define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define _USART_CTRL_ERRSRX_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */
+#define _USART_CTRL_ERRSRX_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */
+#define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_ERRSRX_DISABLE (_USART_CTRL_ERRSRX_DISABLE << 23) /**< Shifted mode DISABLE for USART_CTRL */
+#define USART_CTRL_ERRSRX_ENABLE (_USART_CTRL_ERRSRX_ENABLE << 23) /**< Shifted mode ENABLE for USART_CTRL */
+#define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */
+#define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */
+#define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */
+#define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define _USART_CTRL_ERRSTX_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */
+#define _USART_CTRL_ERRSTX_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */
+#define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_ERRSTX_DISABLE (_USART_CTRL_ERRSTX_DISABLE << 24) /**< Shifted mode DISABLE for USART_CTRL */
+#define USART_CTRL_ERRSTX_ENABLE (_USART_CTRL_ERRSTX_ENABLE << 24) /**< Shifted mode ENABLE for USART_CTRL */
+#define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Secondary Setup Early */
+#define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */
+#define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */
+#define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */
+#define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */
+#define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */
+#define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define _USART_CTRL_BYTESWAP_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */
+#define _USART_CTRL_BYTESWAP_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */
+#define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_BYTESWAP_DISABLE (_USART_CTRL_BYTESWAP_DISABLE << 28) /**< Shifted mode DISABLE for USART_CTRL */
+#define USART_CTRL_BYTESWAP_ENABLE (_USART_CTRL_BYTESWAP_ENABLE << 28) /**< Shifted mode ENABLE for USART_CTRL */
+#define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */
+#define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */
+#define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */
+#define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */
+#define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */
+#define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */
+#define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Main Sample Delay */
+#define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */
+#define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */
+#define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
+#define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */
+
+/* Bit fields for USART FRAME */
+#define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */
+#define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */
+#define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */
+#define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */
+#define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */
+#define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */
+#define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */
+#define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */
+#define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */
+#define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */
+#define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */
+#define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */
+#define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */
+#define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */
+#define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */
+#define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */
+#define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */
+#define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */
+#define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */
+#define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */
+#define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */
+#define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */
+#define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */
+#define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */
+#define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */
+#define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */
+#define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */
+#define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */
+#define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */
+#define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */
+#define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */
+#define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */
+#define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */
+#define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */
+#define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */
+#define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */
+#define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */
+#define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */
+#define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */
+#define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */
+#define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */
+#define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */
+#define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */
+#define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */
+#define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */
+#define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */
+#define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */
+#define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */
+#define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */
+#define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */
+#define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */
+#define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */
+#define USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */
+#define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */
+
+/* Bit fields for USART TRIGCTRL */
+#define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */
+#define _USART_TRIGCTRL_MASK 0x00001FF0UL /**< Mask for USART_TRIGCTRL */
+#define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */
+#define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */
+#define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */
+#define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */
+#define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */
+#define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */
+#define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */
+#define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */
+#define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */
+#define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger after RX End of */
+#define _USART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */
+#define _USART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */
+#define _USART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TXARX0EN_DEFAULT (_USART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger after RX End of */
+#define _USART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */
+#define _USART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */
+#define _USART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TXARX1EN_DEFAULT (_USART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger after RX End of */
+#define _USART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */
+#define _USART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */
+#define _USART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_TXARX2EN_DEFAULT (_USART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger after TX end of f */
+#define _USART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */
+#define _USART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */
+#define _USART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_RXATX0EN_DEFAULT (_USART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger after TX end of f */
+#define _USART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */
+#define _USART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */
+#define _USART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_RXATX1EN_DEFAULT (_USART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger after TX end of f */
+#define _USART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */
+#define _USART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */
+#define _USART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
+#define USART_TRIGCTRL_RXATX2EN_DEFAULT (_USART_TRIGCTRL_RXATX2EN_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
+
+/* Bit fields for USART CMD */
+#define _USART_CMD_RESETVALUE 0x00000000UL /**< Default value for USART_CMD */
+#define _USART_CMD_MASK 0x00000FFFUL /**< Mask for USART_CMD */
+#define USART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */
+#define _USART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */
+#define _USART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */
+#define _USART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_RXEN_DEFAULT (_USART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */
+#define _USART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */
+#define _USART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */
+#define _USART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_RXDIS_DEFAULT (_USART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */
+#define _USART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */
+#define _USART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */
+#define _USART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_TXEN_DEFAULT (_USART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */
+#define _USART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */
+#define _USART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */
+#define _USART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_TXDIS_DEFAULT (_USART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_MASTEREN (0x1UL << 4) /**< Main Mode Enable */
+#define _USART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */
+#define _USART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */
+#define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_MASTEREN_DEFAULT (_USART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_MASTERDIS (0x1UL << 5) /**< Main Mode Disable */
+#define _USART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */
+#define _USART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */
+#define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_MASTERDIS_DEFAULT (_USART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */
+#define _USART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */
+#define _USART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */
+#define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_RXBLOCKEN_DEFAULT (_USART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */
+#define _USART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */
+#define _USART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */
+#define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_RXBLOCKDIS_DEFAULT (_USART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */
+#define _USART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */
+#define _USART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */
+#define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_TXTRIEN_DEFAULT (_USART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */
+#define _USART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */
+#define _USART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */
+#define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_TXTRIDIS_DEFAULT (_USART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */
+#define _USART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */
+#define _USART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */
+#define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_CLEARTX_DEFAULT (_USART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CMD */
+#define USART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */
+#define _USART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */
+#define _USART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */
+#define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
+#define USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CMD */
+
+/* Bit fields for USART STATUS */
+#define _USART_STATUS_RESETVALUE 0x00002040UL /**< Default value for USART_STATUS */
+#define _USART_STATUS_MASK 0x00037FFFUL /**< Mask for USART_STATUS */
+#define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */
+#define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */
+#define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */
+#define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */
+#define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */
+#define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */
+#define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Main Mode */
+#define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */
+#define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */
+#define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */
+#define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */
+#define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */
+#define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */
+#define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */
+#define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */
+#define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */
+#define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */
+#define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */
+#define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */
+#define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */
+#define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */
+#define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */
+#define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */
+#define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */
+#define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */
+#define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */
+#define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */
+#define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */
+#define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */
+#define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */
+#define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */
+#define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */
+#define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */
+#define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */
+#define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */
+#define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */
+#define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */
+#define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */
+#define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */
+#define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */
+#define _USART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
+#define _USART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
+#define _USART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXIDLE_DEFAULT (_USART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer restarted itself */
+#define _USART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */
+#define _USART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */
+#define _USART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TIMERRESTARTED_DEFAULT (_USART_STATUS_TIMERRESTARTED_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_STATUS */
+#define _USART_STATUS_TXBUFCNT_SHIFT 16 /**< Shift value for USART_TXBUFCNT */
+#define _USART_STATUS_TXBUFCNT_MASK 0x30000UL /**< Bit mask for USART_TXBUFCNT */
+#define _USART_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
+#define USART_STATUS_TXBUFCNT_DEFAULT (_USART_STATUS_TXBUFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_STATUS */
+
+/* Bit fields for USART CLKDIV */
+#define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */
+#define _USART_CLKDIV_MASK 0x807FFFF8UL /**< Mask for USART_CLKDIV */
+#define _USART_CLKDIV_DIV_SHIFT 3 /**< Shift value for USART_DIV */
+#define _USART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */
+#define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */
+#define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CLKDIV */
+#define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */
+#define _USART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */
+#define _USART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */
+#define _USART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */
+#define USART_CLKDIV_AUTOBAUDEN_DEFAULT (_USART_CLKDIV_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CLKDIV */
+
+/* Bit fields for USART RXDATAX */
+#define _USART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAX */
+#define _USART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAX */
+#define _USART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */
+#define _USART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */
+#define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */
+#define USART_RXDATAX_RXDATA_DEFAULT (_USART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */
+#define USART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */
+#define _USART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */
+#define _USART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */
+#define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */
+#define USART_RXDATAX_PERR_DEFAULT (_USART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAX */
+#define USART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */
+#define _USART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */
+#define _USART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */
+#define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */
+#define USART_RXDATAX_FERR_DEFAULT (_USART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAX */
+
+/* Bit fields for USART RXDATA */
+#define _USART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATA */
+#define _USART_RXDATA_MASK 0x000000FFUL /**< Mask for USART_RXDATA */
+#define _USART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */
+#define _USART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */
+#define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATA */
+#define USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATA */
+
+/* Bit fields for USART RXDOUBLEX */
+#define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */
+#define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */
+#define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */
+#define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */
+#define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
+#define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
+#define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */
+#define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */
+#define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */
+#define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
+#define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
+#define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */
+#define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */
+#define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */
+#define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
+#define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
+#define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */
+#define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */
+#define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
+#define USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
+#define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */
+#define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */
+#define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */
+#define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
+#define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
+#define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */
+#define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */
+#define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */
+#define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
+#define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
+
+/* Bit fields for USART RXDOUBLE */
+#define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */
+#define _USART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_RXDOUBLE */
+#define _USART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */
+#define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */
+#define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */
+#define USART_RXDOUBLE_RXDATA0_DEFAULT (_USART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */
+#define _USART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */
+#define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */
+#define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */
+#define USART_RXDOUBLE_RXDATA1_DEFAULT (_USART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */
+
+/* Bit fields for USART RXDATAXP */
+#define _USART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAXP */
+#define _USART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAXP */
+#define _USART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */
+#define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */
+#define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */
+#define USART_RXDATAXP_RXDATAP_DEFAULT (_USART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */
+#define USART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */
+#define _USART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */
+#define _USART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */
+#define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */
+#define USART_RXDATAXP_PERRP_DEFAULT (_USART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAXP */
+#define USART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */
+#define _USART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */
+#define _USART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */
+#define _USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */
+#define USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */
+
+/* Bit fields for USART RXDOUBLEXP */
+#define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */
+#define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */
+#define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */
+#define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */
+#define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
+#define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
+#define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */
+#define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */
+#define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */
+#define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
+#define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
+#define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */
+#define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */
+#define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */
+#define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
+#define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
+#define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */
+#define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */
+#define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
+#define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
+#define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */
+#define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */
+#define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */
+#define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
+#define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
+#define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */
+#define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */
+#define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */
+#define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
+#define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
+
+/* Bit fields for USART TXDATAX */
+#define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */
+#define _USART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for USART_TXDATAX */
+#define _USART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */
+#define _USART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */
+#define _USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_TXDATAX_DEFAULT (_USART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */
+#define _USART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */
+#define _USART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */
+#define _USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_UBRXAT_DEFAULT (_USART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */
+#define _USART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */
+#define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */
+#define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */
+#define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */
+#define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */
+#define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_TXBREAK_DEFAULT (_USART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */
+#define _USART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */
+#define _USART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */
+#define _USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_TXDISAT_DEFAULT (_USART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */
+#define _USART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */
+#define _USART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */
+#define _USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
+#define USART_TXDATAX_RXENAT_DEFAULT (_USART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDATAX */
+
+/* Bit fields for USART TXDATA */
+#define _USART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATA */
+#define _USART_TXDATA_MASK 0x000000FFUL /**< Mask for USART_TXDATA */
+#define _USART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */
+#define _USART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */
+#define _USART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATA */
+#define USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATA */
+
+/* Bit fields for USART TXDOUBLEX */
+#define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */
+#define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */
+#define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */
+#define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */
+#define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */
+#define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */
+#define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */
+#define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */
+#define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */
+#define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */
+#define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */
+#define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */
+#define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */
+#define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */
+#define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */
+#define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */
+#define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */
+#define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */
+#define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */
+#define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */
+#define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */
+#define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */
+#define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */
+#define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */
+#define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */
+#define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */
+#define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */
+#define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */
+#define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */
+#define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */
+#define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */
+#define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */
+#define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */
+#define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */
+#define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */
+#define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */
+#define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
+#define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
+
+/* Bit fields for USART TXDOUBLE */
+#define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */
+#define _USART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_TXDOUBLE */
+#define _USART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */
+#define _USART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */
+#define _USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */
+#define USART_TXDOUBLE_TXDATA0_DEFAULT (_USART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLE */
+#define _USART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */
+#define _USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */
+#define _USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */
+#define USART_TXDOUBLE_TXDATA1_DEFAULT (_USART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TXDOUBLE */
+
+/* Bit fields for USART IF */
+#define _USART_IF_RESETVALUE 0x00000002UL /**< Default value for USART_IF */
+#define _USART_IF_MASK 0x0001FFFFUL /**< Mask for USART_IF */
+#define USART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */
+#define _USART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */
+#define _USART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
+#define _USART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_TXC_DEFAULT (_USART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */
+#define _USART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */
+#define _USART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */
+#define _USART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_TXBL_DEFAULT (_USART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */
+#define _USART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */
+#define _USART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */
+#define _USART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_RXDATAV_DEFAULT (_USART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */
+#define _USART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
+#define _USART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
+#define _USART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_RXFULL_DEFAULT (_USART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */
+#define _USART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
+#define _USART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
+#define _USART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_RXOF_DEFAULT (_USART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */
+#define _USART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
+#define _USART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
+#define _USART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_RXUF_DEFAULT (_USART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */
+#define _USART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
+#define _USART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
+#define _USART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_TXOF_DEFAULT (_USART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */
+#define _USART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
+#define _USART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
+#define _USART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_TXUF_DEFAULT (_USART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */
+#define _USART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */
+#define _USART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
+#define _USART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_PERR_DEFAULT (_USART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */
+#define _USART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */
+#define _USART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
+#define _USART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_FERR_DEFAULT (_USART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */
+#define _USART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
+#define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
+#define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_SSM (0x1UL << 11) /**< Chip-Select In Main Mode Interrupt Flag */
+#define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */
+#define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
+#define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_SSM_DEFAULT (_USART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */
+#define _USART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */
+#define _USART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
+#define _USART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_CCF_DEFAULT (_USART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */
+#define _USART_IF_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
+#define _USART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
+#define _USART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_TXIDLE_DEFAULT (_USART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Flag */
+#define _USART_IF_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */
+#define _USART_IF_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */
+#define _USART_IF_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_TCMP0_DEFAULT (_USART_IF_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Flag */
+#define _USART_IF_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */
+#define _USART_IF_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */
+#define _USART_IF_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_TCMP1_DEFAULT (_USART_IF_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IF */
+#define USART_IF_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Flag */
+#define _USART_IF_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */
+#define _USART_IF_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */
+#define _USART_IF_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
+#define USART_IF_TCMP2_DEFAULT (_USART_IF_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IF */
+
+/* Bit fields for USART IEN */
+#define _USART_IEN_RESETVALUE 0x00000000UL /**< Default value for USART_IEN */
+#define _USART_IEN_MASK 0x0001FFFFUL /**< Mask for USART_IEN */
+#define USART_IEN_TXC (0x1UL << 0) /**< TX Complete Interrupt Enable */
+#define _USART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */
+#define _USART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
+#define _USART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_TXC_DEFAULT (_USART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Enable */
+#define _USART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */
+#define _USART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */
+#define _USART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_TXBL_DEFAULT (_USART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Enable */
+#define _USART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */
+#define _USART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */
+#define _USART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_RXDATAV_DEFAULT (_USART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Enable */
+#define _USART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
+#define _USART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
+#define _USART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_RXFULL_DEFAULT (_USART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Enable */
+#define _USART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
+#define _USART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
+#define _USART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_RXOF_DEFAULT (_USART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Enable */
+#define _USART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
+#define _USART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
+#define _USART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_RXUF_DEFAULT (_USART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Enable */
+#define _USART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
+#define _USART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
+#define _USART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_TXOF_DEFAULT (_USART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Enable */
+#define _USART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
+#define _USART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
+#define _USART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_TXUF_DEFAULT (_USART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_PERR (0x1UL << 8) /**< Parity Error Interrupt Enable */
+#define _USART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */
+#define _USART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
+#define _USART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_PERR_DEFAULT (_USART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_FERR (0x1UL << 9) /**< Framing Error Interrupt Enable */
+#define _USART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */
+#define _USART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
+#define _USART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_FERR_DEFAULT (_USART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */
+#define _USART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
+#define _USART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
+#define _USART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_MPAF_DEFAULT (_USART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_SSM (0x1UL << 11) /**< Chip-Select In Main Mode Interrupt Flag */
+#define _USART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */
+#define _USART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
+#define _USART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_SSM_DEFAULT (_USART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Enable */
+#define _USART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */
+#define _USART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
+#define _USART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_CCF_DEFAULT (_USART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Enable */
+#define _USART_IEN_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
+#define _USART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
+#define _USART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_TXIDLE_DEFAULT (_USART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Enable */
+#define _USART_IEN_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */
+#define _USART_IEN_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */
+#define _USART_IEN_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_TCMP0_DEFAULT (_USART_IEN_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Enable */
+#define _USART_IEN_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */
+#define _USART_IEN_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */
+#define _USART_IEN_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_TCMP1_DEFAULT (_USART_IEN_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IEN */
+#define USART_IEN_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Enable */
+#define _USART_IEN_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */
+#define _USART_IEN_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */
+#define _USART_IEN_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
+#define USART_IEN_TCMP2_DEFAULT (_USART_IEN_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IEN */
+
+/* Bit fields for USART IRCTRL */
+#define _USART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_IRCTRL */
+#define _USART_IRCTRL_MASK 0x0000008FUL /**< Mask for USART_IRCTRL */
+#define USART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */
+#define _USART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */
+#define _USART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */
+#define _USART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
+#define USART_IRCTRL_IREN_DEFAULT (_USART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IRCTRL */
+#define _USART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */
+#define _USART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */
+#define _USART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
+#define _USART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for USART_IRCTRL */
+#define _USART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for USART_IRCTRL */
+#define _USART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for USART_IRCTRL */
+#define _USART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for USART_IRCTRL */
+#define USART_IRCTRL_IRPW_DEFAULT (_USART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IRCTRL */
+#define USART_IRCTRL_IRPW_ONE (_USART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for USART_IRCTRL */
+#define USART_IRCTRL_IRPW_TWO (_USART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for USART_IRCTRL */
+#define USART_IRCTRL_IRPW_THREE (_USART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for USART_IRCTRL */
+#define USART_IRCTRL_IRPW_FOUR (_USART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for USART_IRCTRL */
+#define USART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */
+#define _USART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */
+#define _USART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */
+#define _USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
+#define _USART_IRCTRL_IRFILT_DISABLE 0x00000000UL /**< Mode DISABLE for USART_IRCTRL */
+#define _USART_IRCTRL_IRFILT_ENABLE 0x00000001UL /**< Mode ENABLE for USART_IRCTRL */
+#define USART_IRCTRL_IRFILT_DEFAULT (_USART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IRCTRL */
+#define USART_IRCTRL_IRFILT_DISABLE (_USART_IRCTRL_IRFILT_DISABLE << 3) /**< Shifted mode DISABLE for USART_IRCTRL */
+#define USART_IRCTRL_IRFILT_ENABLE (_USART_IRCTRL_IRFILT_ENABLE << 3) /**< Shifted mode ENABLE for USART_IRCTRL */
+
+/* Bit fields for USART I2SCTRL */
+#define _USART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_I2SCTRL */
+#define _USART_I2SCTRL_MASK 0x0000071FUL /**< Mask for USART_I2SCTRL */
+#define USART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */
+#define _USART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */
+#define _USART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */
+#define _USART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
+#define USART_I2SCTRL_EN_DEFAULT (_USART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_I2SCTRL */
+#define USART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */
+#define _USART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */
+#define _USART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */
+#define _USART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
+#define USART_I2SCTRL_MONO_DEFAULT (_USART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_I2SCTRL */
+#define USART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */
+#define _USART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */
+#define _USART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */
+#define _USART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
+#define _USART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for USART_I2SCTRL */
+#define _USART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for USART_I2SCTRL */
+#define USART_I2SCTRL_JUSTIFY_DEFAULT (_USART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_I2SCTRL */
+#define USART_I2SCTRL_JUSTIFY_LEFT (_USART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for USART_I2SCTRL */
+#define USART_I2SCTRL_JUSTIFY_RIGHT (_USART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for USART_I2SCTRL */
+#define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request For Left/Right Data */
+#define _USART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */
+#define _USART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */
+#define _USART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
+#define USART_I2SCTRL_DMASPLIT_DEFAULT (_USART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_I2SCTRL */
+#define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S data */
+#define _USART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */
+#define _USART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */
+#define _USART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
+#define USART_I2SCTRL_DELAY_DEFAULT (_USART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_I2SCTRL */
+#define _USART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */
+#define _USART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */
+#define _USART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
+#define _USART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for USART_I2SCTRL */
+#define _USART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for USART_I2SCTRL */
+#define _USART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for USART_I2SCTRL */
+#define _USART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for USART_I2SCTRL */
+#define _USART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for USART_I2SCTRL */
+#define _USART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for USART_I2SCTRL */
+#define _USART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for USART_I2SCTRL */
+#define _USART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for USART_I2SCTRL */
+#define USART_I2SCTRL_FORMAT_DEFAULT (_USART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_I2SCTRL */
+#define USART_I2SCTRL_FORMAT_W32D32 (_USART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for USART_I2SCTRL */
+#define USART_I2SCTRL_FORMAT_W32D24M (_USART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for USART_I2SCTRL */
+#define USART_I2SCTRL_FORMAT_W32D24 (_USART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for USART_I2SCTRL */
+#define USART_I2SCTRL_FORMAT_W32D16 (_USART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for USART_I2SCTRL */
+#define USART_I2SCTRL_FORMAT_W32D8 (_USART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for USART_I2SCTRL */
+#define USART_I2SCTRL_FORMAT_W16D16 (_USART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for USART_I2SCTRL */
+#define USART_I2SCTRL_FORMAT_W16D8 (_USART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for USART_I2SCTRL */
+#define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */
+
+/* Bit fields for USART TIMING */
+#define _USART_TIMING_RESETVALUE 0x00000000UL /**< Default value for USART_TIMING */
+#define _USART_TIMING_MASK 0x77770000UL /**< Mask for USART_TIMING */
+#define _USART_TIMING_TXDELAY_SHIFT 16 /**< Shift value for USART_TXDELAY */
+#define _USART_TIMING_TXDELAY_MASK 0x70000UL /**< Bit mask for USART_TXDELAY */
+#define _USART_TIMING_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */
+#define _USART_TIMING_TXDELAY_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMING */
+#define _USART_TIMING_TXDELAY_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */
+#define _USART_TIMING_TXDELAY_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */
+#define _USART_TIMING_TXDELAY_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */
+#define _USART_TIMING_TXDELAY_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */
+#define _USART_TIMING_TXDELAY_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */
+#define _USART_TIMING_TXDELAY_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */
+#define _USART_TIMING_TXDELAY_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */
+#define USART_TIMING_TXDELAY_DEFAULT (_USART_TIMING_TXDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMING */
+#define USART_TIMING_TXDELAY_DISABLE (_USART_TIMING_TXDELAY_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMING */
+#define USART_TIMING_TXDELAY_ONE (_USART_TIMING_TXDELAY_ONE << 16) /**< Shifted mode ONE for USART_TIMING */
+#define USART_TIMING_TXDELAY_TWO (_USART_TIMING_TXDELAY_TWO << 16) /**< Shifted mode TWO for USART_TIMING */
+#define USART_TIMING_TXDELAY_THREE (_USART_TIMING_TXDELAY_THREE << 16) /**< Shifted mode THREE for USART_TIMING */
+#define USART_TIMING_TXDELAY_SEVEN (_USART_TIMING_TXDELAY_SEVEN << 16) /**< Shifted mode SEVEN for USART_TIMING */
+#define USART_TIMING_TXDELAY_TCMP0 (_USART_TIMING_TXDELAY_TCMP0 << 16) /**< Shifted mode TCMP0 for USART_TIMING */
+#define USART_TIMING_TXDELAY_TCMP1 (_USART_TIMING_TXDELAY_TCMP1 << 16) /**< Shifted mode TCMP1 for USART_TIMING */
+#define USART_TIMING_TXDELAY_TCMP2 (_USART_TIMING_TXDELAY_TCMP2 << 16) /**< Shifted mode TCMP2 for USART_TIMING */
+#define _USART_TIMING_CSSETUP_SHIFT 20 /**< Shift value for USART_CSSETUP */
+#define _USART_TIMING_CSSETUP_MASK 0x700000UL /**< Bit mask for USART_CSSETUP */
+#define _USART_TIMING_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */
+#define _USART_TIMING_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */
+#define _USART_TIMING_CSSETUP_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */
+#define _USART_TIMING_CSSETUP_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */
+#define _USART_TIMING_CSSETUP_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */
+#define _USART_TIMING_CSSETUP_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */
+#define _USART_TIMING_CSSETUP_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */
+#define _USART_TIMING_CSSETUP_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */
+#define _USART_TIMING_CSSETUP_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */
+#define USART_TIMING_CSSETUP_DEFAULT (_USART_TIMING_CSSETUP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMING */
+#define USART_TIMING_CSSETUP_ZERO (_USART_TIMING_CSSETUP_ZERO << 20) /**< Shifted mode ZERO for USART_TIMING */
+#define USART_TIMING_CSSETUP_ONE (_USART_TIMING_CSSETUP_ONE << 20) /**< Shifted mode ONE for USART_TIMING */
+#define USART_TIMING_CSSETUP_TWO (_USART_TIMING_CSSETUP_TWO << 20) /**< Shifted mode TWO for USART_TIMING */
+#define USART_TIMING_CSSETUP_THREE (_USART_TIMING_CSSETUP_THREE << 20) /**< Shifted mode THREE for USART_TIMING */
+#define USART_TIMING_CSSETUP_SEVEN (_USART_TIMING_CSSETUP_SEVEN << 20) /**< Shifted mode SEVEN for USART_TIMING */
+#define USART_TIMING_CSSETUP_TCMP0 (_USART_TIMING_CSSETUP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMING */
+#define USART_TIMING_CSSETUP_TCMP1 (_USART_TIMING_CSSETUP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMING */
+#define USART_TIMING_CSSETUP_TCMP2 (_USART_TIMING_CSSETUP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMING */
+#define _USART_TIMING_ICS_SHIFT 24 /**< Shift value for USART_ICS */
+#define _USART_TIMING_ICS_MASK 0x7000000UL /**< Bit mask for USART_ICS */
+#define _USART_TIMING_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */
+#define _USART_TIMING_ICS_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */
+#define _USART_TIMING_ICS_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */
+#define _USART_TIMING_ICS_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */
+#define _USART_TIMING_ICS_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */
+#define _USART_TIMING_ICS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */
+#define _USART_TIMING_ICS_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */
+#define _USART_TIMING_ICS_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */
+#define _USART_TIMING_ICS_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */
+#define USART_TIMING_ICS_DEFAULT (_USART_TIMING_ICS_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMING */
+#define USART_TIMING_ICS_ZERO (_USART_TIMING_ICS_ZERO << 24) /**< Shifted mode ZERO for USART_TIMING */
+#define USART_TIMING_ICS_ONE (_USART_TIMING_ICS_ONE << 24) /**< Shifted mode ONE for USART_TIMING */
+#define USART_TIMING_ICS_TWO (_USART_TIMING_ICS_TWO << 24) /**< Shifted mode TWO for USART_TIMING */
+#define USART_TIMING_ICS_THREE (_USART_TIMING_ICS_THREE << 24) /**< Shifted mode THREE for USART_TIMING */
+#define USART_TIMING_ICS_SEVEN (_USART_TIMING_ICS_SEVEN << 24) /**< Shifted mode SEVEN for USART_TIMING */
+#define USART_TIMING_ICS_TCMP0 (_USART_TIMING_ICS_TCMP0 << 24) /**< Shifted mode TCMP0 for USART_TIMING */
+#define USART_TIMING_ICS_TCMP1 (_USART_TIMING_ICS_TCMP1 << 24) /**< Shifted mode TCMP1 for USART_TIMING */
+#define USART_TIMING_ICS_TCMP2 (_USART_TIMING_ICS_TCMP2 << 24) /**< Shifted mode TCMP2 for USART_TIMING */
+#define _USART_TIMING_CSHOLD_SHIFT 28 /**< Shift value for USART_CSHOLD */
+#define _USART_TIMING_CSHOLD_MASK 0x70000000UL /**< Bit mask for USART_CSHOLD */
+#define _USART_TIMING_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */
+#define _USART_TIMING_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */
+#define _USART_TIMING_CSHOLD_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */
+#define _USART_TIMING_CSHOLD_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */
+#define _USART_TIMING_CSHOLD_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */
+#define _USART_TIMING_CSHOLD_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */
+#define _USART_TIMING_CSHOLD_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */
+#define _USART_TIMING_CSHOLD_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */
+#define _USART_TIMING_CSHOLD_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */
+#define USART_TIMING_CSHOLD_DEFAULT (_USART_TIMING_CSHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TIMING */
+#define USART_TIMING_CSHOLD_ZERO (_USART_TIMING_CSHOLD_ZERO << 28) /**< Shifted mode ZERO for USART_TIMING */
+#define USART_TIMING_CSHOLD_ONE (_USART_TIMING_CSHOLD_ONE << 28) /**< Shifted mode ONE for USART_TIMING */
+#define USART_TIMING_CSHOLD_TWO (_USART_TIMING_CSHOLD_TWO << 28) /**< Shifted mode TWO for USART_TIMING */
+#define USART_TIMING_CSHOLD_THREE (_USART_TIMING_CSHOLD_THREE << 28) /**< Shifted mode THREE for USART_TIMING */
+#define USART_TIMING_CSHOLD_SEVEN (_USART_TIMING_CSHOLD_SEVEN << 28) /**< Shifted mode SEVEN for USART_TIMING */
+#define USART_TIMING_CSHOLD_TCMP0 (_USART_TIMING_CSHOLD_TCMP0 << 28) /**< Shifted mode TCMP0 for USART_TIMING */
+#define USART_TIMING_CSHOLD_TCMP1 (_USART_TIMING_CSHOLD_TCMP1 << 28) /**< Shifted mode TCMP1 for USART_TIMING */
+#define USART_TIMING_CSHOLD_TCMP2 (_USART_TIMING_CSHOLD_TCMP2 << 28) /**< Shifted mode TCMP2 for USART_TIMING */
+
+/* Bit fields for USART CTRLX */
+#define _USART_CTRLX_RESETVALUE 0x00000000UL /**< Default value for USART_CTRLX */
+#define _USART_CTRLX_MASK 0x8000808FUL /**< Mask for USART_CTRLX */
+#define USART_CTRLX_DBGHALT (0x1UL << 0) /**< Debug halt */
+#define _USART_CTRLX_DBGHALT_SHIFT 0 /**< Shift value for USART_DBGHALT */
+#define _USART_CTRLX_DBGHALT_MASK 0x1UL /**< Bit mask for USART_DBGHALT */
+#define _USART_CTRLX_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
+#define _USART_CTRLX_DBGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */
+#define _USART_CTRLX_DBGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */
+#define USART_CTRLX_DBGHALT_DEFAULT (_USART_CTRLX_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRLX */
+#define USART_CTRLX_DBGHALT_DISABLE (_USART_CTRLX_DBGHALT_DISABLE << 0) /**< Shifted mode DISABLE for USART_CTRLX */
+#define USART_CTRLX_DBGHALT_ENABLE (_USART_CTRLX_DBGHALT_ENABLE << 0) /**< Shifted mode ENABLE for USART_CTRLX */
+#define USART_CTRLX_CTSINV (0x1UL << 1) /**< CTS Pin Inversion */
+#define _USART_CTRLX_CTSINV_SHIFT 1 /**< Shift value for USART_CTSINV */
+#define _USART_CTRLX_CTSINV_MASK 0x2UL /**< Bit mask for USART_CTSINV */
+#define _USART_CTRLX_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
+#define _USART_CTRLX_CTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */
+#define _USART_CTRLX_CTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */
+#define USART_CTRLX_CTSINV_DEFAULT (_USART_CTRLX_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRLX */
+#define USART_CTRLX_CTSINV_DISABLE (_USART_CTRLX_CTSINV_DISABLE << 1) /**< Shifted mode DISABLE for USART_CTRLX */
+#define USART_CTRLX_CTSINV_ENABLE (_USART_CTRLX_CTSINV_ENABLE << 1) /**< Shifted mode ENABLE for USART_CTRLX */
+#define USART_CTRLX_CTSEN (0x1UL << 2) /**< CTS Function enabled */
+#define _USART_CTRLX_CTSEN_SHIFT 2 /**< Shift value for USART_CTSEN */
+#define _USART_CTRLX_CTSEN_MASK 0x4UL /**< Bit mask for USART_CTSEN */
+#define _USART_CTRLX_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
+#define _USART_CTRLX_CTSEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */
+#define _USART_CTRLX_CTSEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */
+#define USART_CTRLX_CTSEN_DEFAULT (_USART_CTRLX_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRLX */
+#define USART_CTRLX_CTSEN_DISABLE (_USART_CTRLX_CTSEN_DISABLE << 2) /**< Shifted mode DISABLE for USART_CTRLX */
+#define USART_CTRLX_CTSEN_ENABLE (_USART_CTRLX_CTSEN_ENABLE << 2) /**< Shifted mode ENABLE for USART_CTRLX */
+#define USART_CTRLX_RTSINV (0x1UL << 3) /**< RTS Pin Inversion */
+#define _USART_CTRLX_RTSINV_SHIFT 3 /**< Shift value for USART_RTSINV */
+#define _USART_CTRLX_RTSINV_MASK 0x8UL /**< Bit mask for USART_RTSINV */
+#define _USART_CTRLX_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
+#define _USART_CTRLX_RTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */
+#define _USART_CTRLX_RTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */
+#define USART_CTRLX_RTSINV_DEFAULT (_USART_CTRLX_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRLX */
+#define USART_CTRLX_RTSINV_DISABLE (_USART_CTRLX_RTSINV_DISABLE << 3) /**< Shifted mode DISABLE for USART_CTRLX */
+#define USART_CTRLX_RTSINV_ENABLE (_USART_CTRLX_RTSINV_ENABLE << 3) /**< Shifted mode ENABLE for USART_CTRLX */
+#define USART_CTRLX_RXPRSEN (0x1UL << 7) /**< PRS RX Enable */
+#define _USART_CTRLX_RXPRSEN_SHIFT 7 /**< Shift value for USART_RXPRSEN */
+#define _USART_CTRLX_RXPRSEN_MASK 0x80UL /**< Bit mask for USART_RXPRSEN */
+#define _USART_CTRLX_RXPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
+#define USART_CTRLX_RXPRSEN_DEFAULT (_USART_CTRLX_RXPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CTRLX */
+#define USART_CTRLX_CLKPRSEN (0x1UL << 15) /**< PRS CLK Enable */
+#define _USART_CTRLX_CLKPRSEN_SHIFT 15 /**< Shift value for USART_CLKPRSEN */
+#define _USART_CTRLX_CLKPRSEN_MASK 0x8000UL /**< Bit mask for USART_CLKPRSEN */
+#define _USART_CTRLX_CLKPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
+#define USART_CTRLX_CLKPRSEN_DEFAULT (_USART_CTRLX_CLKPRSEN_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRLX */
+
+/* Bit fields for USART TIMECMP0 */
+#define _USART_TIMECMP0_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP0 */
+#define _USART_TIMECMP0_MASK 0x017700FFUL /**< Mask for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */
+#define _USART_TIMECMP0_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */
+#define _USART_TIMECMP0_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */
+#define USART_TIMECMP0_TCMPVAL_DEFAULT (_USART_TIMECMP0_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */
+#define _USART_TIMECMP0_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */
+#define _USART_TIMECMP0_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTART_DEFAULT (_USART_TIMECMP0_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTART_DISABLE (_USART_TIMECMP0_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTART_TXEOF (_USART_TIMECMP0_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTART_TXC (_USART_TIMECMP0_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTART_RXACT (_USART_TIMECMP0_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTART_RXEOF (_USART_TIMECMP0_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */
+#define _USART_TIMECMP0_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */
+#define _USART_TIMECMP0_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTOP_TCMP0 0x00000000UL /**< Mode TCMP0 for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP0 */
+#define _USART_TIMECMP0_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTOP_DEFAULT (_USART_TIMECMP0_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTOP_TCMP0 (_USART_TIMECMP0_TSTOP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTOP_TXST (_USART_TIMECMP0_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTOP_RXACT (_USART_TIMECMP0_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP0 */
+#define USART_TIMECMP0_TSTOP_RXACTN (_USART_TIMECMP0_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP0 */
+#define USART_TIMECMP0_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP0 */
+#define _USART_TIMECMP0_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */
+#define _USART_TIMECMP0_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */
+#define _USART_TIMECMP0_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */
+#define _USART_TIMECMP0_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */
+#define _USART_TIMECMP0_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP0 */
+#define USART_TIMECMP0_RESTARTEN_DEFAULT (_USART_TIMECMP0_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP0 */
+#define USART_TIMECMP0_RESTARTEN_DISABLE (_USART_TIMECMP0_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP0 */
+#define USART_TIMECMP0_RESTARTEN_ENABLE (_USART_TIMECMP0_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP0 */
+
+/* Bit fields for USART TIMECMP1 */
+#define _USART_TIMECMP1_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP1 */
+#define _USART_TIMECMP1_MASK 0x017700FFUL /**< Mask for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */
+#define _USART_TIMECMP1_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */
+#define _USART_TIMECMP1_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */
+#define USART_TIMECMP1_TCMPVAL_DEFAULT (_USART_TIMECMP1_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */
+#define _USART_TIMECMP1_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */
+#define _USART_TIMECMP1_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTART_DEFAULT (_USART_TIMECMP1_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTART_DISABLE (_USART_TIMECMP1_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTART_TXEOF (_USART_TIMECMP1_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTART_TXC (_USART_TIMECMP1_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTART_RXACT (_USART_TIMECMP1_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTART_RXEOF (_USART_TIMECMP1_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */
+#define _USART_TIMECMP1_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */
+#define _USART_TIMECMP1_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTOP_TCMP1 0x00000000UL /**< Mode TCMP1 for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP1 */
+#define _USART_TIMECMP1_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTOP_DEFAULT (_USART_TIMECMP1_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTOP_TCMP1 (_USART_TIMECMP1_TSTOP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTOP_TXST (_USART_TIMECMP1_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTOP_RXACT (_USART_TIMECMP1_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP1 */
+#define USART_TIMECMP1_TSTOP_RXACTN (_USART_TIMECMP1_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP1 */
+#define USART_TIMECMP1_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP1 */
+#define _USART_TIMECMP1_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */
+#define _USART_TIMECMP1_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */
+#define _USART_TIMECMP1_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */
+#define _USART_TIMECMP1_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */
+#define _USART_TIMECMP1_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP1 */
+#define USART_TIMECMP1_RESTARTEN_DEFAULT (_USART_TIMECMP1_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP1 */
+#define USART_TIMECMP1_RESTARTEN_DISABLE (_USART_TIMECMP1_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP1 */
+#define USART_TIMECMP1_RESTARTEN_ENABLE (_USART_TIMECMP1_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP1 */
+
+/* Bit fields for USART TIMECMP2 */
+#define _USART_TIMECMP2_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP2 */
+#define _USART_TIMECMP2_MASK 0x017700FFUL /**< Mask for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */
+#define _USART_TIMECMP2_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */
+#define _USART_TIMECMP2_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */
+#define USART_TIMECMP2_TCMPVAL_DEFAULT (_USART_TIMECMP2_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */
+#define _USART_TIMECMP2_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */
+#define _USART_TIMECMP2_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTART_DEFAULT (_USART_TIMECMP2_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTART_DISABLE (_USART_TIMECMP2_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTART_TXEOF (_USART_TIMECMP2_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTART_TXC (_USART_TIMECMP2_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTART_RXACT (_USART_TIMECMP2_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTART_RXEOF (_USART_TIMECMP2_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */
+#define _USART_TIMECMP2_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */
+#define _USART_TIMECMP2_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTOP_TCMP2 0x00000000UL /**< Mode TCMP2 for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP2 */
+#define _USART_TIMECMP2_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTOP_DEFAULT (_USART_TIMECMP2_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTOP_TCMP2 (_USART_TIMECMP2_TSTOP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTOP_TXST (_USART_TIMECMP2_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTOP_RXACT (_USART_TIMECMP2_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP2 */
+#define USART_TIMECMP2_TSTOP_RXACTN (_USART_TIMECMP2_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP2 */
+#define USART_TIMECMP2_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP2 */
+#define _USART_TIMECMP2_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */
+#define _USART_TIMECMP2_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */
+#define _USART_TIMECMP2_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */
+#define _USART_TIMECMP2_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */
+#define _USART_TIMECMP2_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP2 */
+#define USART_TIMECMP2_RESTARTEN_DEFAULT (_USART_TIMECMP2_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP2 */
+#define USART_TIMECMP2_RESTARTEN_DISABLE (_USART_TIMECMP2_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP2 */
+#define USART_TIMECMP2_RESTARTEN_ENABLE (_USART_TIMECMP2_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP2 */
+
+/** @} End of group EFR32MG24_USART_BitFields */
+/** @} End of group EFR32MG24_USART */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_USART_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_vdac.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_vdac.h
new file mode 100644
index 00000000..a89a20fc
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_vdac.h
@@ -0,0 +1,757 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 VDAC register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_VDAC_H
+#define EFR32MG24_VDAC_H
+#define VDAC_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_VDAC VDAC
+ * @{
+ * @brief EFR32MG24 VDAC Register Declaration.
+ *****************************************************************************/
+
+/** VDAC Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IPVERSION */
+ __IOM uint32_t EN; /**< Module Enable */
+ __IOM uint32_t SWRST; /**< Software Reset Register */
+ __IOM uint32_t CFG; /**< Config Register */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IOM uint32_t CH0CFG; /**< Channel 0 Config Register */
+ __IOM uint32_t CH1CFG; /**< Channel 1 Config Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ __IOM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IOM uint32_t CH0F; /**< Channel 0 Data Write Fifo */
+ __IOM uint32_t CH1F; /**< Channel 1 Data Write Fifo */
+ __IOM uint32_t OUTCTRL; /**< DAC Output Control */
+ __IOM uint32_t OUTTIMERCFG; /**< DAC Out Timer Config Register */
+ uint32_t RESERVED0[50U]; /**< Reserved for future use */
+ uint32_t RESERVED1[1U]; /**< Reserved for future use */
+ uint32_t RESERVED2[63U]; /**< Reserved for future use */
+ uint32_t RESERVED3[1U]; /**< Reserved for future use */
+ uint32_t RESERVED4[895U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IPVERSION */
+ __IOM uint32_t EN_SET; /**< Module Enable */
+ __IOM uint32_t SWRST_SET; /**< Software Reset Register */
+ __IOM uint32_t CFG_SET; /**< Config Register */
+ __IM uint32_t STATUS_SET; /**< Status Register */
+ __IOM uint32_t CH0CFG_SET; /**< Channel 0 Config Register */
+ __IOM uint32_t CH1CFG_SET; /**< Channel 1 Config Register */
+ __IOM uint32_t CMD_SET; /**< Command Register */
+ __IOM uint32_t IF_SET; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
+ __IOM uint32_t CH0F_SET; /**< Channel 0 Data Write Fifo */
+ __IOM uint32_t CH1F_SET; /**< Channel 1 Data Write Fifo */
+ __IOM uint32_t OUTCTRL_SET; /**< DAC Output Control */
+ __IOM uint32_t OUTTIMERCFG_SET; /**< DAC Out Timer Config Register */
+ uint32_t RESERVED5[50U]; /**< Reserved for future use */
+ uint32_t RESERVED6[1U]; /**< Reserved for future use */
+ uint32_t RESERVED7[63U]; /**< Reserved for future use */
+ uint32_t RESERVED8[1U]; /**< Reserved for future use */
+ uint32_t RESERVED9[895U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IPVERSION */
+ __IOM uint32_t EN_CLR; /**< Module Enable */
+ __IOM uint32_t SWRST_CLR; /**< Software Reset Register */
+ __IOM uint32_t CFG_CLR; /**< Config Register */
+ __IM uint32_t STATUS_CLR; /**< Status Register */
+ __IOM uint32_t CH0CFG_CLR; /**< Channel 0 Config Register */
+ __IOM uint32_t CH1CFG_CLR; /**< Channel 1 Config Register */
+ __IOM uint32_t CMD_CLR; /**< Command Register */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
+ __IOM uint32_t CH0F_CLR; /**< Channel 0 Data Write Fifo */
+ __IOM uint32_t CH1F_CLR; /**< Channel 1 Data Write Fifo */
+ __IOM uint32_t OUTCTRL_CLR; /**< DAC Output Control */
+ __IOM uint32_t OUTTIMERCFG_CLR; /**< DAC Out Timer Config Register */
+ uint32_t RESERVED10[50U]; /**< Reserved for future use */
+ uint32_t RESERVED11[1U]; /**< Reserved for future use */
+ uint32_t RESERVED12[63U]; /**< Reserved for future use */
+ uint32_t RESERVED13[1U]; /**< Reserved for future use */
+ uint32_t RESERVED14[895U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IPVERSION */
+ __IOM uint32_t EN_TGL; /**< Module Enable */
+ __IOM uint32_t SWRST_TGL; /**< Software Reset Register */
+ __IOM uint32_t CFG_TGL; /**< Config Register */
+ __IM uint32_t STATUS_TGL; /**< Status Register */
+ __IOM uint32_t CH0CFG_TGL; /**< Channel 0 Config Register */
+ __IOM uint32_t CH1CFG_TGL; /**< Channel 1 Config Register */
+ __IOM uint32_t CMD_TGL; /**< Command Register */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
+ __IOM uint32_t CH0F_TGL; /**< Channel 0 Data Write Fifo */
+ __IOM uint32_t CH1F_TGL; /**< Channel 1 Data Write Fifo */
+ __IOM uint32_t OUTCTRL_TGL; /**< DAC Output Control */
+ __IOM uint32_t OUTTIMERCFG_TGL; /**< DAC Out Timer Config Register */
+ uint32_t RESERVED15[50U]; /**< Reserved for future use */
+ uint32_t RESERVED16[1U]; /**< Reserved for future use */
+ uint32_t RESERVED17[63U]; /**< Reserved for future use */
+ uint32_t RESERVED18[1U]; /**< Reserved for future use */
+} VDAC_TypeDef;
+/** @} End of group EFR32MG24_VDAC */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_VDAC
+ * @{
+ * @defgroup EFR32MG24_VDAC_BitFields VDAC Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for VDAC IPVERSION */
+#define _VDAC_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for VDAC_IPVERSION */
+#define _VDAC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for VDAC_IPVERSION */
+#define _VDAC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for VDAC_IPVERSION */
+#define _VDAC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for VDAC_IPVERSION */
+#define _VDAC_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for VDAC_IPVERSION */
+#define VDAC_IPVERSION_IPVERSION_DEFAULT (_VDAC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IPVERSION */
+
+/* Bit fields for VDAC EN */
+#define _VDAC_EN_RESETVALUE 0x00000000UL /**< Default value for VDAC_EN */
+#define _VDAC_EN_MASK 0x00000003UL /**< Mask for VDAC_EN */
+#define VDAC_EN_EN (0x1UL << 0) /**< VDAC Module Enable */
+#define _VDAC_EN_EN_SHIFT 0 /**< Shift value for VDAC_EN */
+#define _VDAC_EN_EN_MASK 0x1UL /**< Bit mask for VDAC_EN */
+#define _VDAC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_EN */
+#define _VDAC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for VDAC_EN */
+#define _VDAC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for VDAC_EN */
+#define VDAC_EN_EN_DEFAULT (_VDAC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_EN */
+#define VDAC_EN_EN_DISABLE (_VDAC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for VDAC_EN */
+#define VDAC_EN_EN_ENABLE (_VDAC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for VDAC_EN */
+#define VDAC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */
+#define _VDAC_EN_DISABLING_SHIFT 1 /**< Shift value for VDAC_DISABLING */
+#define _VDAC_EN_DISABLING_MASK 0x2UL /**< Bit mask for VDAC_DISABLING */
+#define _VDAC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_EN */
+#define VDAC_EN_DISABLING_DEFAULT (_VDAC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_EN */
+
+/* Bit fields for VDAC SWRST */
+#define _VDAC_SWRST_RESETVALUE 0x00000000UL /**< Default value for VDAC_SWRST */
+#define _VDAC_SWRST_MASK 0x00000003UL /**< Mask for VDAC_SWRST */
+#define VDAC_SWRST_SWRST (0x1UL << 0) /**< Software reset command */
+#define _VDAC_SWRST_SWRST_SHIFT 0 /**< Shift value for VDAC_SWRST */
+#define _VDAC_SWRST_SWRST_MASK 0x1UL /**< Bit mask for VDAC_SWRST */
+#define _VDAC_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_SWRST */
+#define VDAC_SWRST_SWRST_DEFAULT (_VDAC_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_SWRST */
+#define VDAC_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */
+#define _VDAC_SWRST_RESETTING_SHIFT 1 /**< Shift value for VDAC_RESETTING */
+#define _VDAC_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for VDAC_RESETTING */
+#define _VDAC_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_SWRST */
+#define VDAC_SWRST_RESETTING_DEFAULT (_VDAC_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_SWRST */
+
+/* Bit fields for VDAC CFG */
+#define _VDAC_CFG_RESETVALUE 0x20000000UL /**< Default value for VDAC_CFG */
+#define _VDAC_CFG_MASK 0x7F773FBFUL /**< Mask for VDAC_CFG */
+#define VDAC_CFG_DIFF (0x1UL << 0) /**< Differential Mode */
+#define _VDAC_CFG_DIFF_SHIFT 0 /**< Shift value for VDAC_DIFF */
+#define _VDAC_CFG_DIFF_MASK 0x1UL /**< Bit mask for VDAC_DIFF */
+#define _VDAC_CFG_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */
+#define _VDAC_CFG_DIFF_SINGLEENDED 0x00000000UL /**< Mode SINGLEENDED for VDAC_CFG */
+#define _VDAC_CFG_DIFF_DIFFERENTIAL 0x00000001UL /**< Mode DIFFERENTIAL for VDAC_CFG */
+#define VDAC_CFG_DIFF_DEFAULT (_VDAC_CFG_DIFF_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CFG */
+#define VDAC_CFG_DIFF_SINGLEENDED (_VDAC_CFG_DIFF_SINGLEENDED << 0) /**< Shifted mode SINGLEENDED for VDAC_CFG */
+#define VDAC_CFG_DIFF_DIFFERENTIAL (_VDAC_CFG_DIFF_DIFFERENTIAL << 0) /**< Shifted mode DIFFERENTIAL for VDAC_CFG */
+#define VDAC_CFG_SINEMODE (0x1UL << 1) /**< Sine Mode */
+#define _VDAC_CFG_SINEMODE_SHIFT 1 /**< Shift value for VDAC_SINEMODE */
+#define _VDAC_CFG_SINEMODE_MASK 0x2UL /**< Bit mask for VDAC_SINEMODE */
+#define _VDAC_CFG_SINEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */
+#define _VDAC_CFG_SINEMODE_DISSINEMODE 0x00000000UL /**< Mode DISSINEMODE for VDAC_CFG */
+#define _VDAC_CFG_SINEMODE_ENSINEMODE 0x00000001UL /**< Mode ENSINEMODE for VDAC_CFG */
+#define VDAC_CFG_SINEMODE_DEFAULT (_VDAC_CFG_SINEMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_CFG */
+#define VDAC_CFG_SINEMODE_DISSINEMODE (_VDAC_CFG_SINEMODE_DISSINEMODE << 1) /**< Shifted mode DISSINEMODE for VDAC_CFG */
+#define VDAC_CFG_SINEMODE_ENSINEMODE (_VDAC_CFG_SINEMODE_ENSINEMODE << 1) /**< Shifted mode ENSINEMODE for VDAC_CFG */
+#define VDAC_CFG_SINERESET (0x1UL << 2) /**< Sine Wave Reset When inactive */
+#define _VDAC_CFG_SINERESET_SHIFT 2 /**< Shift value for VDAC_SINERESET */
+#define _VDAC_CFG_SINERESET_MASK 0x4UL /**< Bit mask for VDAC_SINERESET */
+#define _VDAC_CFG_SINERESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */
+#define VDAC_CFG_SINERESET_DEFAULT (_VDAC_CFG_SINERESET_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CFG */
+#define VDAC_CFG_CH0PRESCRST (0x1UL << 3) /**< Channel 0 Start Reset Prescaler */
+#define _VDAC_CFG_CH0PRESCRST_SHIFT 3 /**< Shift value for VDAC_CH0PRESCRST */
+#define _VDAC_CFG_CH0PRESCRST_MASK 0x8UL /**< Bit mask for VDAC_CH0PRESCRST */
+#define _VDAC_CFG_CH0PRESCRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */
+#define _VDAC_CFG_CH0PRESCRST_NORESETPRESC 0x00000000UL /**< Mode NORESETPRESC for VDAC_CFG */
+#define _VDAC_CFG_CH0PRESCRST_RESETPRESC 0x00000001UL /**< Mode RESETPRESC for VDAC_CFG */
+#define VDAC_CFG_CH0PRESCRST_DEFAULT (_VDAC_CFG_CH0PRESCRST_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_CFG */
+#define VDAC_CFG_CH0PRESCRST_NORESETPRESC (_VDAC_CFG_CH0PRESCRST_NORESETPRESC << 3) /**< Shifted mode NORESETPRESC for VDAC_CFG */
+#define VDAC_CFG_CH0PRESCRST_RESETPRESC (_VDAC_CFG_CH0PRESCRST_RESETPRESC << 3) /**< Shifted mode RESETPRESC for VDAC_CFG */
+#define _VDAC_CFG_REFRSEL_SHIFT 4 /**< Shift value for VDAC_REFRSEL */
+#define _VDAC_CFG_REFRSEL_MASK 0x30UL /**< Bit mask for VDAC_REFRSEL */
+#define _VDAC_CFG_REFRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */
+#define _VDAC_CFG_REFRSEL_V125 0x00000000UL /**< Mode V125 for VDAC_CFG */
+#define _VDAC_CFG_REFRSEL_V25 0x00000001UL /**< Mode V25 for VDAC_CFG */
+#define _VDAC_CFG_REFRSEL_VDD 0x00000002UL /**< Mode VDD for VDAC_CFG */
+#define _VDAC_CFG_REFRSEL_EXT 0x00000003UL /**< Mode EXT for VDAC_CFG */
+#define VDAC_CFG_REFRSEL_DEFAULT (_VDAC_CFG_REFRSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CFG */
+#define VDAC_CFG_REFRSEL_V125 (_VDAC_CFG_REFRSEL_V125 << 4) /**< Shifted mode V125 for VDAC_CFG */
+#define VDAC_CFG_REFRSEL_V25 (_VDAC_CFG_REFRSEL_V25 << 4) /**< Shifted mode V25 for VDAC_CFG */
+#define VDAC_CFG_REFRSEL_VDD (_VDAC_CFG_REFRSEL_VDD << 4) /**< Shifted mode VDD for VDAC_CFG */
+#define VDAC_CFG_REFRSEL_EXT (_VDAC_CFG_REFRSEL_EXT << 4) /**< Shifted mode EXT for VDAC_CFG */
+#define _VDAC_CFG_PRESC_SHIFT 7 /**< Shift value for VDAC_PRESC */
+#define _VDAC_CFG_PRESC_MASK 0x3F80UL /**< Bit mask for VDAC_PRESC */
+#define _VDAC_CFG_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */
+#define VDAC_CFG_PRESC_DEFAULT (_VDAC_CFG_PRESC_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_CFG */
+#define _VDAC_CFG_TIMEROVRFLOWPERIOD_SHIFT 16 /**< Shift value for VDAC_TIMEROVRFLOWPERIOD */
+#define _VDAC_CFG_TIMEROVRFLOWPERIOD_MASK 0x70000UL /**< Bit mask for VDAC_TIMEROVRFLOWPERIOD */
+#define _VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */
+#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 0x00000000UL /**< Mode CYCLES2 for VDAC_CFG */
+#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 0x00000001UL /**< Mode CYCLES4 for VDAC_CFG */
+#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 0x00000002UL /**< Mode CYCLES8 for VDAC_CFG */
+#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 0x00000003UL /**< Mode CYCLES16 for VDAC_CFG */
+#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 0x00000004UL /**< Mode CYCLES32 for VDAC_CFG */
+#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 0x00000005UL /**< Mode CYCLES64 for VDAC_CFG */
+#define VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT (_VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CFG */
+#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 << 16) /**< Shifted mode CYCLES2 for VDAC_CFG */
+#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 << 16) /**< Shifted mode CYCLES4 for VDAC_CFG */
+#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 << 16) /**< Shifted mode CYCLES8 for VDAC_CFG */
+#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 << 16) /**< Shifted mode CYCLES16 for VDAC_CFG */
+#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 << 16) /**< Shifted mode CYCLES32 for VDAC_CFG */
+#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 << 16) /**< Shifted mode CYCLES64 for VDAC_CFG */
+#define _VDAC_CFG_REFRESHPERIOD_SHIFT 20 /**< Shift value for VDAC_REFRESHPERIOD */
+#define _VDAC_CFG_REFRESHPERIOD_MASK 0x700000UL /**< Bit mask for VDAC_REFRESHPERIOD */
+#define _VDAC_CFG_REFRESHPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */
+#define _VDAC_CFG_REFRESHPERIOD_CYCLES2 0x00000000UL /**< Mode CYCLES2 for VDAC_CFG */
+#define _VDAC_CFG_REFRESHPERIOD_CYCLES4 0x00000001UL /**< Mode CYCLES4 for VDAC_CFG */
+#define _VDAC_CFG_REFRESHPERIOD_CYCLES8 0x00000002UL /**< Mode CYCLES8 for VDAC_CFG */
+#define _VDAC_CFG_REFRESHPERIOD_CYCLES16 0x00000003UL /**< Mode CYCLES16 for VDAC_CFG */
+#define _VDAC_CFG_REFRESHPERIOD_CYCLES32 0x00000004UL /**< Mode CYCLES32 for VDAC_CFG */
+#define _VDAC_CFG_REFRESHPERIOD_CYCLES64 0x00000005UL /**< Mode CYCLES64 for VDAC_CFG */
+#define _VDAC_CFG_REFRESHPERIOD_CYCLES128 0x00000006UL /**< Mode CYCLES128 for VDAC_CFG */
+#define _VDAC_CFG_REFRESHPERIOD_CYCLES256 0x00000007UL /**< Mode CYCLES256 for VDAC_CFG */
+#define VDAC_CFG_REFRESHPERIOD_DEFAULT (_VDAC_CFG_REFRESHPERIOD_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_CFG */
+#define VDAC_CFG_REFRESHPERIOD_CYCLES2 (_VDAC_CFG_REFRESHPERIOD_CYCLES2 << 20) /**< Shifted mode CYCLES2 for VDAC_CFG */
+#define VDAC_CFG_REFRESHPERIOD_CYCLES4 (_VDAC_CFG_REFRESHPERIOD_CYCLES4 << 20) /**< Shifted mode CYCLES4 for VDAC_CFG */
+#define VDAC_CFG_REFRESHPERIOD_CYCLES8 (_VDAC_CFG_REFRESHPERIOD_CYCLES8 << 20) /**< Shifted mode CYCLES8 for VDAC_CFG */
+#define VDAC_CFG_REFRESHPERIOD_CYCLES16 (_VDAC_CFG_REFRESHPERIOD_CYCLES16 << 20) /**< Shifted mode CYCLES16 for VDAC_CFG */
+#define VDAC_CFG_REFRESHPERIOD_CYCLES32 (_VDAC_CFG_REFRESHPERIOD_CYCLES32 << 20) /**< Shifted mode CYCLES32 for VDAC_CFG */
+#define VDAC_CFG_REFRESHPERIOD_CYCLES64 (_VDAC_CFG_REFRESHPERIOD_CYCLES64 << 20) /**< Shifted mode CYCLES64 for VDAC_CFG */
+#define VDAC_CFG_REFRESHPERIOD_CYCLES128 (_VDAC_CFG_REFRESHPERIOD_CYCLES128 << 20) /**< Shifted mode CYCLES128 for VDAC_CFG */
+#define VDAC_CFG_REFRESHPERIOD_CYCLES256 (_VDAC_CFG_REFRESHPERIOD_CYCLES256 << 20) /**< Shifted mode CYCLES256 for VDAC_CFG */
+#define VDAC_CFG_BIASKEEPWARM (0x1UL << 24) /**< Bias Keepwarm Mode Enable */
+#define _VDAC_CFG_BIASKEEPWARM_SHIFT 24 /**< Shift value for VDAC_BIASKEEPWARM */
+#define _VDAC_CFG_BIASKEEPWARM_MASK 0x1000000UL /**< Bit mask for VDAC_BIASKEEPWARM */
+#define _VDAC_CFG_BIASKEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */
+#define VDAC_CFG_BIASKEEPWARM_DEFAULT (_VDAC_CFG_BIASKEEPWARM_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_CFG */
+#define VDAC_CFG_DMAWU (0x1UL << 25) /**< VDAC DMA Wakeup */
+#define _VDAC_CFG_DMAWU_SHIFT 25 /**< Shift value for VDAC_DMAWU */
+#define _VDAC_CFG_DMAWU_MASK 0x2000000UL /**< Bit mask for VDAC_DMAWU */
+#define _VDAC_CFG_DMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */
+#define VDAC_CFG_DMAWU_DEFAULT (_VDAC_CFG_DMAWU_DEFAULT << 25) /**< Shifted mode DEFAULT for VDAC_CFG */
+#define VDAC_CFG_ONDEMANDCLK (0x1UL << 26) /**< Always allow clk_dac */
+#define _VDAC_CFG_ONDEMANDCLK_SHIFT 26 /**< Shift value for VDAC_ONDEMANDCLK */
+#define _VDAC_CFG_ONDEMANDCLK_MASK 0x4000000UL /**< Bit mask for VDAC_ONDEMANDCLK */
+#define _VDAC_CFG_ONDEMANDCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */
+#define VDAC_CFG_ONDEMANDCLK_DEFAULT (_VDAC_CFG_ONDEMANDCLK_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_CFG */
+#define VDAC_CFG_DBGHALT (0x1UL << 27) /**< Debug Halt */
+#define _VDAC_CFG_DBGHALT_SHIFT 27 /**< Shift value for VDAC_DBGHALT */
+#define _VDAC_CFG_DBGHALT_MASK 0x8000000UL /**< Bit mask for VDAC_DBGHALT */
+#define _VDAC_CFG_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */
+#define _VDAC_CFG_DBGHALT_NORMAL 0x00000000UL /**< Mode NORMAL for VDAC_CFG */
+#define _VDAC_CFG_DBGHALT_HALT 0x00000001UL /**< Mode HALT for VDAC_CFG */
+#define VDAC_CFG_DBGHALT_DEFAULT (_VDAC_CFG_DBGHALT_DEFAULT << 27) /**< Shifted mode DEFAULT for VDAC_CFG */
+#define VDAC_CFG_DBGHALT_NORMAL (_VDAC_CFG_DBGHALT_NORMAL << 27) /**< Shifted mode NORMAL for VDAC_CFG */
+#define VDAC_CFG_DBGHALT_HALT (_VDAC_CFG_DBGHALT_HALT << 27) /**< Shifted mode HALT for VDAC_CFG */
+#define _VDAC_CFG_WARMUPTIME_SHIFT 28 /**< Shift value for VDAC_WARMUPTIME */
+#define _VDAC_CFG_WARMUPTIME_MASK 0x70000000UL /**< Bit mask for VDAC_WARMUPTIME */
+#define _VDAC_CFG_WARMUPTIME_DEFAULT 0x00000002UL /**< Mode DEFAULT for VDAC_CFG */
+#define VDAC_CFG_WARMUPTIME_DEFAULT (_VDAC_CFG_WARMUPTIME_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_CFG */
+
+/* Bit fields for VDAC STATUS */
+#define _VDAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for VDAC_STATUS */
+#define _VDAC_STATUS_MASK 0xFCDBF333UL /**< Mask for VDAC_STATUS */
+#define VDAC_STATUS_CH0ENS (0x1UL << 0) /**< Channel 0 Enabled Status */
+#define _VDAC_STATUS_CH0ENS_SHIFT 0 /**< Shift value for VDAC_CH0ENS */
+#define _VDAC_STATUS_CH0ENS_MASK 0x1UL /**< Bit mask for VDAC_CH0ENS */
+#define _VDAC_STATUS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_CH0ENS_DEFAULT (_VDAC_STATUS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_CH1ENS (0x1UL << 1) /**< Channel 1 Enabled Status */
+#define _VDAC_STATUS_CH1ENS_SHIFT 1 /**< Shift value for VDAC_CH1ENS */
+#define _VDAC_STATUS_CH1ENS_MASK 0x2UL /**< Bit mask for VDAC_CH1ENS */
+#define _VDAC_STATUS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_CH1ENS_DEFAULT (_VDAC_STATUS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_CH0WARM (0x1UL << 4) /**< Channel 0 Warmed Status */
+#define _VDAC_STATUS_CH0WARM_SHIFT 4 /**< Shift value for VDAC_CH0WARM */
+#define _VDAC_STATUS_CH0WARM_MASK 0x10UL /**< Bit mask for VDAC_CH0WARM */
+#define _VDAC_STATUS_CH0WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_CH0WARM_DEFAULT (_VDAC_STATUS_CH0WARM_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_CH1WARM (0x1UL << 5) /**< Channel 1 Warmed Status */
+#define _VDAC_STATUS_CH1WARM_SHIFT 5 /**< Shift value for VDAC_CH1WARM */
+#define _VDAC_STATUS_CH1WARM_MASK 0x20UL /**< Bit mask for VDAC_CH1WARM */
+#define _VDAC_STATUS_CH1WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_CH1WARM_DEFAULT (_VDAC_STATUS_CH1WARM_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_CH0FIFOFULL (0x1UL << 8) /**< Channel 0 FIFO Full Status */
+#define _VDAC_STATUS_CH0FIFOFULL_SHIFT 8 /**< Shift value for VDAC_CH0FIFOFULL */
+#define _VDAC_STATUS_CH0FIFOFULL_MASK 0x100UL /**< Bit mask for VDAC_CH0FIFOFULL */
+#define _VDAC_STATUS_CH0FIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_CH0FIFOFULL_DEFAULT (_VDAC_STATUS_CH0FIFOFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_CH1FIFOFULL (0x1UL << 9) /**< Channel 1 FIFO Full Status */
+#define _VDAC_STATUS_CH1FIFOFULL_SHIFT 9 /**< Shift value for VDAC_CH1FIFOFULL */
+#define _VDAC_STATUS_CH1FIFOFULL_MASK 0x200UL /**< Bit mask for VDAC_CH1FIFOFULL */
+#define _VDAC_STATUS_CH1FIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_CH1FIFOFULL_DEFAULT (_VDAC_STATUS_CH1FIFOFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_STATUS */
+#define _VDAC_STATUS_CH0FIFOCNT_SHIFT 12 /**< Shift value for VDAC_CH0FIFOCNT */
+#define _VDAC_STATUS_CH0FIFOCNT_MASK 0x7000UL /**< Bit mask for VDAC_CH0FIFOCNT */
+#define _VDAC_STATUS_CH0FIFOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_CH0FIFOCNT_DEFAULT (_VDAC_STATUS_CH0FIFOCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_STATUS */
+#define _VDAC_STATUS_CH1FIFOCNT_SHIFT 15 /**< Shift value for VDAC_CH1FIFOCNT */
+#define _VDAC_STATUS_CH1FIFOCNT_MASK 0x38000UL /**< Bit mask for VDAC_CH1FIFOCNT */
+#define _VDAC_STATUS_CH1FIFOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_CH1FIFOCNT_DEFAULT (_VDAC_STATUS_CH1FIFOCNT_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_CH0CURRENTSTATE (0x1UL << 19) /**< Channel 0 Current Status */
+#define _VDAC_STATUS_CH0CURRENTSTATE_SHIFT 19 /**< Shift value for VDAC_CH0CURRENTSTATE */
+#define _VDAC_STATUS_CH0CURRENTSTATE_MASK 0x80000UL /**< Bit mask for VDAC_CH0CURRENTSTATE */
+#define _VDAC_STATUS_CH0CURRENTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_CH0CURRENTSTATE_DEFAULT (_VDAC_STATUS_CH0CURRENTSTATE_DEFAULT << 19) /**< Shifted mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_CH1CURRENTSTATE (0x1UL << 20) /**< Channel 1 Current Status */
+#define _VDAC_STATUS_CH1CURRENTSTATE_SHIFT 20 /**< Shift value for VDAC_CH1CURRENTSTATE */
+#define _VDAC_STATUS_CH1CURRENTSTATE_MASK 0x100000UL /**< Bit mask for VDAC_CH1CURRENTSTATE */
+#define _VDAC_STATUS_CH1CURRENTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_CH1CURRENTSTATE_DEFAULT (_VDAC_STATUS_CH1CURRENTSTATE_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_CH0FIFOEMPTY (0x1UL << 22) /**< Channel 0 FIFO Empty Status */
+#define _VDAC_STATUS_CH0FIFOEMPTY_SHIFT 22 /**< Shift value for VDAC_CH0FIFOEMPTY */
+#define _VDAC_STATUS_CH0FIFOEMPTY_MASK 0x400000UL /**< Bit mask for VDAC_CH0FIFOEMPTY */
+#define _VDAC_STATUS_CH0FIFOEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_CH0FIFOEMPTY_DEFAULT (_VDAC_STATUS_CH0FIFOEMPTY_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_CH1FIFOEMPTY (0x1UL << 23) /**< Channel 1 FIFO Empty Status */
+#define _VDAC_STATUS_CH1FIFOEMPTY_SHIFT 23 /**< Shift value for VDAC_CH1FIFOEMPTY */
+#define _VDAC_STATUS_CH1FIFOEMPTY_MASK 0x800000UL /**< Bit mask for VDAC_CH1FIFOEMPTY */
+#define _VDAC_STATUS_CH1FIFOEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_CH1FIFOEMPTY_DEFAULT (_VDAC_STATUS_CH1FIFOEMPTY_DEFAULT << 23) /**< Shifted mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_CH0FIFOFLBUSY (0x1UL << 26) /**< CH0 WFIFO Flush Sync Busy */
+#define _VDAC_STATUS_CH0FIFOFLBUSY_SHIFT 26 /**< Shift value for VDAC_CH0FIFOFLBUSY */
+#define _VDAC_STATUS_CH0FIFOFLBUSY_MASK 0x4000000UL /**< Bit mask for VDAC_CH0FIFOFLBUSY */
+#define _VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT (_VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_CH1FIFOFLBUSY (0x1UL << 27) /**< CH1 WFIFO Flush Sync Busy */
+#define _VDAC_STATUS_CH1FIFOFLBUSY_SHIFT 27 /**< Shift value for VDAC_CH1FIFOFLBUSY */
+#define _VDAC_STATUS_CH1FIFOFLBUSY_MASK 0x8000000UL /**< Bit mask for VDAC_CH1FIFOFLBUSY */
+#define _VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT (_VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT << 27) /**< Shifted mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_ABUSINPUTCONFLICT (0x1UL << 28) /**< ABUS Input Conflict Status */
+#define _VDAC_STATUS_ABUSINPUTCONFLICT_SHIFT 28 /**< Shift value for VDAC_ABUSINPUTCONFLICT */
+#define _VDAC_STATUS_ABUSINPUTCONFLICT_MASK 0x10000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */
+#define _VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT (_VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_SINEACTIVE (0x1UL << 29) /**< Sine Wave Output Status on Channel */
+#define _VDAC_STATUS_SINEACTIVE_SHIFT 29 /**< Shift value for VDAC_SINEACTIVE */
+#define _VDAC_STATUS_SINEACTIVE_MASK 0x20000000UL /**< Bit mask for VDAC_SINEACTIVE */
+#define _VDAC_STATUS_SINEACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_SINEACTIVE_DEFAULT (_VDAC_STATUS_SINEACTIVE_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_ABUSALLOCERR (0x1UL << 30) /**< ABUS Allocation Error Status */
+#define _VDAC_STATUS_ABUSALLOCERR_SHIFT 30 /**< Shift value for VDAC_ABUSALLOCERR */
+#define _VDAC_STATUS_ABUSALLOCERR_MASK 0x40000000UL /**< Bit mask for VDAC_ABUSALLOCERR */
+#define _VDAC_STATUS_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_ABUSALLOCERR_DEFAULT (_VDAC_STATUS_ABUSALLOCERR_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_SYNCBUSY (0x1UL << 31) /**< Sync Busy Combined */
+#define _VDAC_STATUS_SYNCBUSY_SHIFT 31 /**< Shift value for VDAC_SYNCBUSY */
+#define _VDAC_STATUS_SYNCBUSY_MASK 0x80000000UL /**< Bit mask for VDAC_SYNCBUSY */
+#define _VDAC_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */
+#define VDAC_STATUS_SYNCBUSY_DEFAULT (_VDAC_STATUS_SYNCBUSY_DEFAULT << 31) /**< Shifted mode DEFAULT for VDAC_STATUS */
+
+/* Bit fields for VDAC CH0CFG */
+#define _VDAC_CH0CFG_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH0CFG */
+#define _VDAC_CH0CFG_MASK 0x00015B75UL /**< Mask for VDAC_CH0CFG */
+#define VDAC_CH0CFG_CONVMODE (0x1UL << 0) /**< Channel 0 Conversion Mode */
+#define _VDAC_CH0CFG_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */
+#define _VDAC_CH0CFG_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */
+#define _VDAC_CH0CFG_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */
+#define _VDAC_CH0CFG_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH0CFG */
+#define _VDAC_CH0CFG_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH0CFG */
+#define VDAC_CH0CFG_CONVMODE_DEFAULT (_VDAC_CH0CFG_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0CFG */
+#define VDAC_CH0CFG_CONVMODE_CONTINUOUS (_VDAC_CH0CFG_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH0CFG */
+#define VDAC_CH0CFG_CONVMODE_SAMPLEOFF (_VDAC_CH0CFG_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH0CFG */
+#define VDAC_CH0CFG_POWERMODE (0x1UL << 2) /**< Channel 0 Power Mode */
+#define _VDAC_CH0CFG_POWERMODE_SHIFT 2 /**< Shift value for VDAC_POWERMODE */
+#define _VDAC_CH0CFG_POWERMODE_MASK 0x4UL /**< Bit mask for VDAC_POWERMODE */
+#define _VDAC_CH0CFG_POWERMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */
+#define _VDAC_CH0CFG_POWERMODE_HIGHPOWER 0x00000000UL /**< Mode HIGHPOWER for VDAC_CH0CFG */
+#define _VDAC_CH0CFG_POWERMODE_LOWPOWER 0x00000001UL /**< Mode LOWPOWER for VDAC_CH0CFG */
+#define VDAC_CH0CFG_POWERMODE_DEFAULT (_VDAC_CH0CFG_POWERMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CH0CFG */
+#define VDAC_CH0CFG_POWERMODE_HIGHPOWER (_VDAC_CH0CFG_POWERMODE_HIGHPOWER << 2) /**< Shifted mode HIGHPOWER for VDAC_CH0CFG */
+#define VDAC_CH0CFG_POWERMODE_LOWPOWER (_VDAC_CH0CFG_POWERMODE_LOWPOWER << 2) /**< Shifted mode LOWPOWER for VDAC_CH0CFG */
+#define _VDAC_CH0CFG_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */
+#define _VDAC_CH0CFG_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */
+#define _VDAC_CH0CFG_TRIGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */
+#define _VDAC_CH0CFG_TRIGMODE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH0CFG */
+#define _VDAC_CH0CFG_TRIGMODE_SW 0x00000001UL /**< Mode SW for VDAC_CH0CFG */
+#define _VDAC_CH0CFG_TRIGMODE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH0CFG */
+#define _VDAC_CH0CFG_TRIGMODE_INTERNALTIMER 0x00000004UL /**< Mode INTERNALTIMER for VDAC_CH0CFG */
+#define _VDAC_CH0CFG_TRIGMODE_ASYNCPRS 0x00000005UL /**< Mode ASYNCPRS for VDAC_CH0CFG */
+#define VDAC_CH0CFG_TRIGMODE_DEFAULT (_VDAC_CH0CFG_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH0CFG */
+#define VDAC_CH0CFG_TRIGMODE_NONE (_VDAC_CH0CFG_TRIGMODE_NONE << 4) /**< Shifted mode NONE for VDAC_CH0CFG */
+#define VDAC_CH0CFG_TRIGMODE_SW (_VDAC_CH0CFG_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH0CFG */
+#define VDAC_CH0CFG_TRIGMODE_SYNCPRS (_VDAC_CH0CFG_TRIGMODE_SYNCPRS << 4) /**< Shifted mode SYNCPRS for VDAC_CH0CFG */
+#define VDAC_CH0CFG_TRIGMODE_INTERNALTIMER (_VDAC_CH0CFG_TRIGMODE_INTERNALTIMER << 4) /**< Shifted mode INTERNALTIMER for VDAC_CH0CFG */
+#define VDAC_CH0CFG_TRIGMODE_ASYNCPRS (_VDAC_CH0CFG_TRIGMODE_ASYNCPRS << 4) /**< Shifted mode ASYNCPRS for VDAC_CH0CFG */
+#define _VDAC_CH0CFG_REFRESHSOURCE_SHIFT 8 /**< Shift value for VDAC_REFRESHSOURCE */
+#define _VDAC_CH0CFG_REFRESHSOURCE_MASK 0x300UL /**< Bit mask for VDAC_REFRESHSOURCE */
+#define _VDAC_CH0CFG_REFRESHSOURCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */
+#define _VDAC_CH0CFG_REFRESHSOURCE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH0CFG */
+#define _VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER 0x00000001UL /**< Mode REFRESHTIMER for VDAC_CH0CFG */
+#define _VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH0CFG */
+#define _VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS 0x00000003UL /**< Mode ASYNCPRS for VDAC_CH0CFG */
+#define VDAC_CH0CFG_REFRESHSOURCE_DEFAULT (_VDAC_CH0CFG_REFRESHSOURCE_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH0CFG */
+#define VDAC_CH0CFG_REFRESHSOURCE_NONE (_VDAC_CH0CFG_REFRESHSOURCE_NONE << 8) /**< Shifted mode NONE for VDAC_CH0CFG */
+#define VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER (_VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER << 8) /**< Shifted mode REFRESHTIMER for VDAC_CH0CFG */
+#define VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS (_VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS << 8) /**< Shifted mode SYNCPRS for VDAC_CH0CFG */
+#define VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS (_VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS << 8) /**< Shifted mode ASYNCPRS for VDAC_CH0CFG */
+#define _VDAC_CH0CFG_FIFODVL_SHIFT 11 /**< Shift value for VDAC_FIFODVL */
+#define _VDAC_CH0CFG_FIFODVL_MASK 0x1800UL /**< Bit mask for VDAC_FIFODVL */
+#define _VDAC_CH0CFG_FIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */
+#define VDAC_CH0CFG_FIFODVL_DEFAULT (_VDAC_CH0CFG_FIFODVL_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CH0CFG */
+#define VDAC_CH0CFG_HIGHCAPLOADEN (0x1UL << 14) /**< Channel 0 High Cap Load Mode Enable */
+#define _VDAC_CH0CFG_HIGHCAPLOADEN_SHIFT 14 /**< Shift value for VDAC_HIGHCAPLOADEN */
+#define _VDAC_CH0CFG_HIGHCAPLOADEN_MASK 0x4000UL /**< Bit mask for VDAC_HIGHCAPLOADEN */
+#define _VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */
+#define VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT (_VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT << 14) /**< Shifted mode DEFAULT for VDAC_CH0CFG */
+#define VDAC_CH0CFG_KEEPWARM (0x1UL << 16) /**< Channel 0 Keepwarm Mode Enable */
+#define _VDAC_CH0CFG_KEEPWARM_SHIFT 16 /**< Shift value for VDAC_KEEPWARM */
+#define _VDAC_CH0CFG_KEEPWARM_MASK 0x10000UL /**< Bit mask for VDAC_KEEPWARM */
+#define _VDAC_CH0CFG_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */
+#define VDAC_CH0CFG_KEEPWARM_DEFAULT (_VDAC_CH0CFG_KEEPWARM_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CH0CFG */
+
+/* Bit fields for VDAC CH1CFG */
+#define _VDAC_CH1CFG_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH1CFG */
+#define _VDAC_CH1CFG_MASK 0x00015B75UL /**< Mask for VDAC_CH1CFG */
+#define VDAC_CH1CFG_CONVMODE (0x1UL << 0) /**< Channel 1 Conversion Mode */
+#define _VDAC_CH1CFG_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */
+#define _VDAC_CH1CFG_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */
+#define _VDAC_CH1CFG_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */
+#define _VDAC_CH1CFG_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH1CFG */
+#define _VDAC_CH1CFG_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH1CFG */
+#define VDAC_CH1CFG_CONVMODE_DEFAULT (_VDAC_CH1CFG_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1CFG */
+#define VDAC_CH1CFG_CONVMODE_CONTINUOUS (_VDAC_CH1CFG_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH1CFG */
+#define VDAC_CH1CFG_CONVMODE_SAMPLEOFF (_VDAC_CH1CFG_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH1CFG */
+#define VDAC_CH1CFG_POWERMODE (0x1UL << 2) /**< Channel 1 Power Mode */
+#define _VDAC_CH1CFG_POWERMODE_SHIFT 2 /**< Shift value for VDAC_POWERMODE */
+#define _VDAC_CH1CFG_POWERMODE_MASK 0x4UL /**< Bit mask for VDAC_POWERMODE */
+#define _VDAC_CH1CFG_POWERMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */
+#define _VDAC_CH1CFG_POWERMODE_HIGHPOWER 0x00000000UL /**< Mode HIGHPOWER for VDAC_CH1CFG */
+#define _VDAC_CH1CFG_POWERMODE_LOWPOWER 0x00000001UL /**< Mode LOWPOWER for VDAC_CH1CFG */
+#define VDAC_CH1CFG_POWERMODE_DEFAULT (_VDAC_CH1CFG_POWERMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CH1CFG */
+#define VDAC_CH1CFG_POWERMODE_HIGHPOWER (_VDAC_CH1CFG_POWERMODE_HIGHPOWER << 2) /**< Shifted mode HIGHPOWER for VDAC_CH1CFG */
+#define VDAC_CH1CFG_POWERMODE_LOWPOWER (_VDAC_CH1CFG_POWERMODE_LOWPOWER << 2) /**< Shifted mode LOWPOWER for VDAC_CH1CFG */
+#define _VDAC_CH1CFG_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */
+#define _VDAC_CH1CFG_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */
+#define _VDAC_CH1CFG_TRIGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */
+#define _VDAC_CH1CFG_TRIGMODE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH1CFG */
+#define _VDAC_CH1CFG_TRIGMODE_SW 0x00000001UL /**< Mode SW for VDAC_CH1CFG */
+#define _VDAC_CH1CFG_TRIGMODE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH1CFG */
+#define _VDAC_CH1CFG_TRIGMODE_INTERNALTIMER 0x00000004UL /**< Mode INTERNALTIMER for VDAC_CH1CFG */
+#define _VDAC_CH1CFG_TRIGMODE_ASYNCPRS 0x00000005UL /**< Mode ASYNCPRS for VDAC_CH1CFG */
+#define VDAC_CH1CFG_TRIGMODE_DEFAULT (_VDAC_CH1CFG_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH1CFG */
+#define VDAC_CH1CFG_TRIGMODE_NONE (_VDAC_CH1CFG_TRIGMODE_NONE << 4) /**< Shifted mode NONE for VDAC_CH1CFG */
+#define VDAC_CH1CFG_TRIGMODE_SW (_VDAC_CH1CFG_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH1CFG */
+#define VDAC_CH1CFG_TRIGMODE_SYNCPRS (_VDAC_CH1CFG_TRIGMODE_SYNCPRS << 4) /**< Shifted mode SYNCPRS for VDAC_CH1CFG */
+#define VDAC_CH1CFG_TRIGMODE_INTERNALTIMER (_VDAC_CH1CFG_TRIGMODE_INTERNALTIMER << 4) /**< Shifted mode INTERNALTIMER for VDAC_CH1CFG */
+#define VDAC_CH1CFG_TRIGMODE_ASYNCPRS (_VDAC_CH1CFG_TRIGMODE_ASYNCPRS << 4) /**< Shifted mode ASYNCPRS for VDAC_CH1CFG */
+#define _VDAC_CH1CFG_REFRESHSOURCE_SHIFT 8 /**< Shift value for VDAC_REFRESHSOURCE */
+#define _VDAC_CH1CFG_REFRESHSOURCE_MASK 0x300UL /**< Bit mask for VDAC_REFRESHSOURCE */
+#define _VDAC_CH1CFG_REFRESHSOURCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */
+#define _VDAC_CH1CFG_REFRESHSOURCE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH1CFG */
+#define _VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER 0x00000001UL /**< Mode REFRESHTIMER for VDAC_CH1CFG */
+#define _VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH1CFG */
+#define _VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS 0x00000003UL /**< Mode ASYNCPRS for VDAC_CH1CFG */
+#define VDAC_CH1CFG_REFRESHSOURCE_DEFAULT (_VDAC_CH1CFG_REFRESHSOURCE_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH1CFG */
+#define VDAC_CH1CFG_REFRESHSOURCE_NONE (_VDAC_CH1CFG_REFRESHSOURCE_NONE << 8) /**< Shifted mode NONE for VDAC_CH1CFG */
+#define VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER (_VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER << 8) /**< Shifted mode REFRESHTIMER for VDAC_CH1CFG */
+#define VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS (_VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS << 8) /**< Shifted mode SYNCPRS for VDAC_CH1CFG */
+#define VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS (_VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS << 8) /**< Shifted mode ASYNCPRS for VDAC_CH1CFG */
+#define _VDAC_CH1CFG_FIFODVL_SHIFT 11 /**< Shift value for VDAC_FIFODVL */
+#define _VDAC_CH1CFG_FIFODVL_MASK 0x1800UL /**< Bit mask for VDAC_FIFODVL */
+#define _VDAC_CH1CFG_FIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */
+#define VDAC_CH1CFG_FIFODVL_DEFAULT (_VDAC_CH1CFG_FIFODVL_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CH1CFG */
+#define VDAC_CH1CFG_HIGHCAPLOADEN (0x1UL << 14) /**< Channel 1 High Cap Load Mode Enable */
+#define _VDAC_CH1CFG_HIGHCAPLOADEN_SHIFT 14 /**< Shift value for VDAC_HIGHCAPLOADEN */
+#define _VDAC_CH1CFG_HIGHCAPLOADEN_MASK 0x4000UL /**< Bit mask for VDAC_HIGHCAPLOADEN */
+#define _VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */
+#define VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT (_VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT << 14) /**< Shifted mode DEFAULT for VDAC_CH1CFG */
+#define VDAC_CH1CFG_KEEPWARM (0x1UL << 16) /**< Channel 1 Keepwarm Mode Enable */
+#define _VDAC_CH1CFG_KEEPWARM_SHIFT 16 /**< Shift value for VDAC_KEEPWARM */
+#define _VDAC_CH1CFG_KEEPWARM_MASK 0x10000UL /**< Bit mask for VDAC_KEEPWARM */
+#define _VDAC_CH1CFG_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */
+#define VDAC_CH1CFG_KEEPWARM_DEFAULT (_VDAC_CH1CFG_KEEPWARM_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CH1CFG */
+
+/* Bit fields for VDAC CMD */
+#define _VDAC_CMD_RESETVALUE 0x00000000UL /**< Default value for VDAC_CMD */
+#define _VDAC_CMD_MASK 0x00000F33UL /**< Mask for VDAC_CMD */
+#define VDAC_CMD_CH0EN (0x1UL << 0) /**< DAC Channel 0 Enable */
+#define _VDAC_CMD_CH0EN_SHIFT 0 /**< Shift value for VDAC_CH0EN */
+#define _VDAC_CMD_CH0EN_MASK 0x1UL /**< Bit mask for VDAC_CH0EN */
+#define _VDAC_CMD_CH0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */
+#define VDAC_CMD_CH0EN_DEFAULT (_VDAC_CMD_CH0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CMD */
+#define VDAC_CMD_CH0DIS (0x1UL << 1) /**< DAC Channel 0 Disable */
+#define _VDAC_CMD_CH0DIS_SHIFT 1 /**< Shift value for VDAC_CH0DIS */
+#define _VDAC_CMD_CH0DIS_MASK 0x2UL /**< Bit mask for VDAC_CH0DIS */
+#define _VDAC_CMD_CH0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */
+#define VDAC_CMD_CH0DIS_DEFAULT (_VDAC_CMD_CH0DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_CMD */
+#define VDAC_CMD_CH1EN (0x1UL << 4) /**< DAC Channel 1 Enable */
+#define _VDAC_CMD_CH1EN_SHIFT 4 /**< Shift value for VDAC_CH1EN */
+#define _VDAC_CMD_CH1EN_MASK 0x10UL /**< Bit mask for VDAC_CH1EN */
+#define _VDAC_CMD_CH1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */
+#define VDAC_CMD_CH1EN_DEFAULT (_VDAC_CMD_CH1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CMD */
+#define VDAC_CMD_CH1DIS (0x1UL << 5) /**< DAC Channel 1 Disable */
+#define _VDAC_CMD_CH1DIS_SHIFT 5 /**< Shift value for VDAC_CH1DIS */
+#define _VDAC_CMD_CH1DIS_MASK 0x20UL /**< Bit mask for VDAC_CH1DIS */
+#define _VDAC_CMD_CH1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */
+#define VDAC_CMD_CH1DIS_DEFAULT (_VDAC_CMD_CH1DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_CMD */
+#define VDAC_CMD_CH0FIFOFLUSH (0x1UL << 8) /**< CH0 WFIFO Flush */
+#define _VDAC_CMD_CH0FIFOFLUSH_SHIFT 8 /**< Shift value for VDAC_CH0FIFOFLUSH */
+#define _VDAC_CMD_CH0FIFOFLUSH_MASK 0x100UL /**< Bit mask for VDAC_CH0FIFOFLUSH */
+#define _VDAC_CMD_CH0FIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */
+#define VDAC_CMD_CH0FIFOFLUSH_DEFAULT (_VDAC_CMD_CH0FIFOFLUSH_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CMD */
+#define VDAC_CMD_CH1FIFOFLUSH (0x1UL << 9) /**< CH1 WFIFO Flush */
+#define _VDAC_CMD_CH1FIFOFLUSH_SHIFT 9 /**< Shift value for VDAC_CH1FIFOFLUSH */
+#define _VDAC_CMD_CH1FIFOFLUSH_MASK 0x200UL /**< Bit mask for VDAC_CH1FIFOFLUSH */
+#define _VDAC_CMD_CH1FIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */
+#define VDAC_CMD_CH1FIFOFLUSH_DEFAULT (_VDAC_CMD_CH1FIFOFLUSH_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_CMD */
+#define VDAC_CMD_SINEMODESTART (0x1UL << 10) /**< Start Sine Wave Generation */
+#define _VDAC_CMD_SINEMODESTART_SHIFT 10 /**< Shift value for VDAC_SINEMODESTART */
+#define _VDAC_CMD_SINEMODESTART_MASK 0x400UL /**< Bit mask for VDAC_SINEMODESTART */
+#define _VDAC_CMD_SINEMODESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */
+#define VDAC_CMD_SINEMODESTART_DEFAULT (_VDAC_CMD_SINEMODESTART_DEFAULT << 10) /**< Shifted mode DEFAULT for VDAC_CMD */
+#define VDAC_CMD_SINEMODESTOP (0x1UL << 11) /**< Stop Sine Wave Generation */
+#define _VDAC_CMD_SINEMODESTOP_SHIFT 11 /**< Shift value for VDAC_SINEMODESTOP */
+#define _VDAC_CMD_SINEMODESTOP_MASK 0x800UL /**< Bit mask for VDAC_SINEMODESTOP */
+#define _VDAC_CMD_SINEMODESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */
+#define VDAC_CMD_SINEMODESTOP_DEFAULT (_VDAC_CMD_SINEMODESTOP_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CMD */
+
+/* Bit fields for VDAC IF */
+#define _VDAC_IF_RESETVALUE 0x00000000UL /**< Default value for VDAC_IF */
+#define _VDAC_IF_MASK 0x04340333UL /**< Mask for VDAC_IF */
+#define VDAC_IF_CH0CD (0x1UL << 0) /**< CH0 Conversion Done Interrupt Flag */
+#define _VDAC_IF_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */
+#define _VDAC_IF_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */
+#define _VDAC_IF_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
+#define VDAC_IF_CH0CD_DEFAULT (_VDAC_IF_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IF */
+#define VDAC_IF_CH1CD (0x1UL << 1) /**< CH1 Conversion Done Interrupt Flag */
+#define _VDAC_IF_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */
+#define _VDAC_IF_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */
+#define _VDAC_IF_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
+#define VDAC_IF_CH1CD_DEFAULT (_VDAC_IF_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IF */
+#define VDAC_IF_CH0OF (0x1UL << 4) /**< CH0 Data Overflow Interrupt Flag */
+#define _VDAC_IF_CH0OF_SHIFT 4 /**< Shift value for VDAC_CH0OF */
+#define _VDAC_IF_CH0OF_MASK 0x10UL /**< Bit mask for VDAC_CH0OF */
+#define _VDAC_IF_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
+#define VDAC_IF_CH0OF_DEFAULT (_VDAC_IF_CH0OF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IF */
+#define VDAC_IF_CH1OF (0x1UL << 5) /**< CH1 Data Overflow Interrupt Flag */
+#define _VDAC_IF_CH1OF_SHIFT 5 /**< Shift value for VDAC_CH1OF */
+#define _VDAC_IF_CH1OF_MASK 0x20UL /**< Bit mask for VDAC_CH1OF */
+#define _VDAC_IF_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
+#define VDAC_IF_CH1OF_DEFAULT (_VDAC_IF_CH1OF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IF */
+#define VDAC_IF_CH0UF (0x1UL << 8) /**< CH0 Data Underflow Interrupt Flag */
+#define _VDAC_IF_CH0UF_SHIFT 8 /**< Shift value for VDAC_CH0UF */
+#define _VDAC_IF_CH0UF_MASK 0x100UL /**< Bit mask for VDAC_CH0UF */
+#define _VDAC_IF_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
+#define VDAC_IF_CH0UF_DEFAULT (_VDAC_IF_CH0UF_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_IF */
+#define VDAC_IF_CH1UF (0x1UL << 9) /**< CH1 Data Underflow Interrupt Flag */
+#define _VDAC_IF_CH1UF_SHIFT 9 /**< Shift value for VDAC_CH1UF */
+#define _VDAC_IF_CH1UF_MASK 0x200UL /**< Bit mask for VDAC_CH1UF */
+#define _VDAC_IF_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
+#define VDAC_IF_CH1UF_DEFAULT (_VDAC_IF_CH1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_IF */
+#define VDAC_IF_ABUSALLOCERR (0x1UL << 18) /**< ABUS Port Allocation Error Flag */
+#define _VDAC_IF_ABUSALLOCERR_SHIFT 18 /**< Shift value for VDAC_ABUSALLOCERR */
+#define _VDAC_IF_ABUSALLOCERR_MASK 0x40000UL /**< Bit mask for VDAC_ABUSALLOCERR */
+#define _VDAC_IF_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
+#define VDAC_IF_ABUSALLOCERR_DEFAULT (_VDAC_IF_ABUSALLOCERR_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IF */
+#define VDAC_IF_CH0DVL (0x1UL << 20) /**< CH0 Data Valid Level Interrupt Flag */
+#define _VDAC_IF_CH0DVL_SHIFT 20 /**< Shift value for VDAC_CH0DVL */
+#define _VDAC_IF_CH0DVL_MASK 0x100000UL /**< Bit mask for VDAC_CH0DVL */
+#define _VDAC_IF_CH0DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
+#define VDAC_IF_CH0DVL_DEFAULT (_VDAC_IF_CH0DVL_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IF */
+#define VDAC_IF_CH1DVL (0x1UL << 21) /**< CH1 Data Valid Level Interrupt Flag */
+#define _VDAC_IF_CH1DVL_SHIFT 21 /**< Shift value for VDAC_CH1DVL */
+#define _VDAC_IF_CH1DVL_MASK 0x200000UL /**< Bit mask for VDAC_CH1DVL */
+#define _VDAC_IF_CH1DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
+#define VDAC_IF_CH1DVL_DEFAULT (_VDAC_IF_CH1DVL_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IF */
+#define VDAC_IF_ABUSINPUTCONFLICT (0x1UL << 26) /**< ABUS Input Conflict Error Flag */
+#define _VDAC_IF_ABUSINPUTCONFLICT_SHIFT 26 /**< Shift value for VDAC_ABUSINPUTCONFLICT */
+#define _VDAC_IF_ABUSINPUTCONFLICT_MASK 0x4000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */
+#define _VDAC_IF_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */
+#define VDAC_IF_ABUSINPUTCONFLICT_DEFAULT (_VDAC_IF_ABUSINPUTCONFLICT_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_IF */
+
+/* Bit fields for VDAC IEN */
+#define _VDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for VDAC_IEN */
+#define _VDAC_IEN_MASK 0x04340333UL /**< Mask for VDAC_IEN */
+#define VDAC_IEN_CH0CD (0x1UL << 0) /**< CH0 Conversion Done Interrupt Flag */
+#define _VDAC_IEN_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */
+#define _VDAC_IEN_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */
+#define _VDAC_IEN_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
+#define VDAC_IEN_CH0CD_DEFAULT (_VDAC_IEN_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IEN */
+#define VDAC_IEN_CH1CD (0x1UL << 1) /**< CH1 Conversion Done Interrupt Flag */
+#define _VDAC_IEN_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */
+#define _VDAC_IEN_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */
+#define _VDAC_IEN_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
+#define VDAC_IEN_CH1CD_DEFAULT (_VDAC_IEN_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IEN */
+#define VDAC_IEN_CH0OF (0x1UL << 4) /**< CH0 Data Overflow Interrupt Flag */
+#define _VDAC_IEN_CH0OF_SHIFT 4 /**< Shift value for VDAC_CH0OF */
+#define _VDAC_IEN_CH0OF_MASK 0x10UL /**< Bit mask for VDAC_CH0OF */
+#define _VDAC_IEN_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
+#define VDAC_IEN_CH0OF_DEFAULT (_VDAC_IEN_CH0OF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IEN */
+#define VDAC_IEN_CH1OF (0x1UL << 5) /**< CH1 Data Overflow Interrupt Flag */
+#define _VDAC_IEN_CH1OF_SHIFT 5 /**< Shift value for VDAC_CH1OF */
+#define _VDAC_IEN_CH1OF_MASK 0x20UL /**< Bit mask for VDAC_CH1OF */
+#define _VDAC_IEN_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
+#define VDAC_IEN_CH1OF_DEFAULT (_VDAC_IEN_CH1OF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IEN */
+#define VDAC_IEN_CH0UF (0x1UL << 8) /**< CH0 Data Underflow Interrupt Flag */
+#define _VDAC_IEN_CH0UF_SHIFT 8 /**< Shift value for VDAC_CH0UF */
+#define _VDAC_IEN_CH0UF_MASK 0x100UL /**< Bit mask for VDAC_CH0UF */
+#define _VDAC_IEN_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
+#define VDAC_IEN_CH0UF_DEFAULT (_VDAC_IEN_CH0UF_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_IEN */
+#define VDAC_IEN_CH1UF (0x1UL << 9) /**< CH1 Data Underflow Interrupt Flag */
+#define _VDAC_IEN_CH1UF_SHIFT 9 /**< Shift value for VDAC_CH1UF */
+#define _VDAC_IEN_CH1UF_MASK 0x200UL /**< Bit mask for VDAC_CH1UF */
+#define _VDAC_IEN_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
+#define VDAC_IEN_CH1UF_DEFAULT (_VDAC_IEN_CH1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_IEN */
+#define VDAC_IEN_ABUSALLOCERR (0x1UL << 18) /**< ABUS Allocation Error Interrupt Flag */
+#define _VDAC_IEN_ABUSALLOCERR_SHIFT 18 /**< Shift value for VDAC_ABUSALLOCERR */
+#define _VDAC_IEN_ABUSALLOCERR_MASK 0x40000UL /**< Bit mask for VDAC_ABUSALLOCERR */
+#define _VDAC_IEN_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
+#define VDAC_IEN_ABUSALLOCERR_DEFAULT (_VDAC_IEN_ABUSALLOCERR_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IEN */
+#define VDAC_IEN_CH0DVL (0x1UL << 20) /**< CH0 Data Valid Level Interrupt Flag */
+#define _VDAC_IEN_CH0DVL_SHIFT 20 /**< Shift value for VDAC_CH0DVL */
+#define _VDAC_IEN_CH0DVL_MASK 0x100000UL /**< Bit mask for VDAC_CH0DVL */
+#define _VDAC_IEN_CH0DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
+#define VDAC_IEN_CH0DVL_DEFAULT (_VDAC_IEN_CH0DVL_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IEN */
+#define VDAC_IEN_CH1DVL (0x1UL << 21) /**< CH1 Data Valid Level Interrupt Flag */
+#define _VDAC_IEN_CH1DVL_SHIFT 21 /**< Shift value for VDAC_CH1DVL */
+#define _VDAC_IEN_CH1DVL_MASK 0x200000UL /**< Bit mask for VDAC_CH1DVL */
+#define _VDAC_IEN_CH1DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
+#define VDAC_IEN_CH1DVL_DEFAULT (_VDAC_IEN_CH1DVL_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IEN */
+#define VDAC_IEN_ABUSINPUTCONFLICT (0x1UL << 26) /**< ABUS Input Conflict Interrupt Flag */
+#define _VDAC_IEN_ABUSINPUTCONFLICT_SHIFT 26 /**< Shift value for VDAC_ABUSINPUTCONFLICT */
+#define _VDAC_IEN_ABUSINPUTCONFLICT_MASK 0x4000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */
+#define _VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */
+#define VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT (_VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_IEN */
+
+/* Bit fields for VDAC CH0F */
+#define _VDAC_CH0F_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH0F */
+#define _VDAC_CH0F_MASK 0x00000FFFUL /**< Mask for VDAC_CH0F */
+#define _VDAC_CH0F_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */
+#define _VDAC_CH0F_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */
+#define _VDAC_CH0F_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0F */
+#define VDAC_CH0F_DATA_DEFAULT (_VDAC_CH0F_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0F */
+
+/* Bit fields for VDAC CH1F */
+#define _VDAC_CH1F_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH1F */
+#define _VDAC_CH1F_MASK 0x00000FFFUL /**< Mask for VDAC_CH1F */
+#define _VDAC_CH1F_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */
+#define _VDAC_CH1F_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */
+#define _VDAC_CH1F_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1F */
+#define VDAC_CH1F_DATA_DEFAULT (_VDAC_CH1F_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1F */
+
+/* Bit fields for VDAC OUTCTRL */
+#define _VDAC_OUTCTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_OUTCTRL */
+#define _VDAC_OUTCTRL_MASK 0x7FDFF333UL /**< Mask for VDAC_OUTCTRL */
+#define VDAC_OUTCTRL_MAINOUTENCH0 (0x1UL << 0) /**< CH0 Main Output Enable */
+#define _VDAC_OUTCTRL_MAINOUTENCH0_SHIFT 0 /**< Shift value for VDAC_MAINOUTENCH0 */
+#define _VDAC_OUTCTRL_MAINOUTENCH0_MASK 0x1UL /**< Bit mask for VDAC_MAINOUTENCH0 */
+#define _VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */
+#define VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT (_VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */
+#define VDAC_OUTCTRL_MAINOUTENCH1 (0x1UL << 1) /**< CH1 Main Output Enable */
+#define _VDAC_OUTCTRL_MAINOUTENCH1_SHIFT 1 /**< Shift value for VDAC_MAINOUTENCH1 */
+#define _VDAC_OUTCTRL_MAINOUTENCH1_MASK 0x2UL /**< Bit mask for VDAC_MAINOUTENCH1 */
+#define _VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */
+#define VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT (_VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */
+#define VDAC_OUTCTRL_AUXOUTENCH0 (0x1UL << 4) /**< CH0 Alternative Output Enable */
+#define _VDAC_OUTCTRL_AUXOUTENCH0_SHIFT 4 /**< Shift value for VDAC_AUXOUTENCH0 */
+#define _VDAC_OUTCTRL_AUXOUTENCH0_MASK 0x10UL /**< Bit mask for VDAC_AUXOUTENCH0 */
+#define _VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */
+#define VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT (_VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */
+#define VDAC_OUTCTRL_AUXOUTENCH1 (0x1UL << 5) /**< CH1 Alternative Output Enable */
+#define _VDAC_OUTCTRL_AUXOUTENCH1_SHIFT 5 /**< Shift value for VDAC_AUXOUTENCH1 */
+#define _VDAC_OUTCTRL_AUXOUTENCH1_MASK 0x20UL /**< Bit mask for VDAC_AUXOUTENCH1 */
+#define _VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */
+#define VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT (_VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */
+#define VDAC_OUTCTRL_SHORTCH0 (0x1UL << 8) /**< CH1 Main and Alternative Output Short */
+#define _VDAC_OUTCTRL_SHORTCH0_SHIFT 8 /**< Shift value for VDAC_SHORTCH0 */
+#define _VDAC_OUTCTRL_SHORTCH0_MASK 0x100UL /**< Bit mask for VDAC_SHORTCH0 */
+#define _VDAC_OUTCTRL_SHORTCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */
+#define VDAC_OUTCTRL_SHORTCH0_DEFAULT (_VDAC_OUTCTRL_SHORTCH0_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */
+#define VDAC_OUTCTRL_SHORTCH1 (0x1UL << 9) /**< CH0 Main and Alternative Output Short */
+#define _VDAC_OUTCTRL_SHORTCH1_SHIFT 9 /**< Shift value for VDAC_SHORTCH1 */
+#define _VDAC_OUTCTRL_SHORTCH1_MASK 0x200UL /**< Bit mask for VDAC_SHORTCH1 */
+#define _VDAC_OUTCTRL_SHORTCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */
+#define VDAC_OUTCTRL_SHORTCH1_DEFAULT (_VDAC_OUTCTRL_SHORTCH1_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */
+#define _VDAC_OUTCTRL_ABUSPORTSELCH0_SHIFT 12 /**< Shift value for VDAC_ABUSPORTSELCH0 */
+#define _VDAC_OUTCTRL_ABUSPORTSELCH0_MASK 0x7000UL /**< Bit mask for VDAC_ABUSPORTSELCH0 */
+#define _VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */
+#define _VDAC_OUTCTRL_ABUSPORTSELCH0_NONE 0x00000000UL /**< Mode NONE for VDAC_OUTCTRL */
+#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA 0x00000001UL /**< Mode PORTA for VDAC_OUTCTRL */
+#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB 0x00000002UL /**< Mode PORTB for VDAC_OUTCTRL */
+#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC 0x00000003UL /**< Mode PORTC for VDAC_OUTCTRL */
+#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD 0x00000004UL /**< Mode PORTD for VDAC_OUTCTRL */
+#define VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT (_VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */
+#define VDAC_OUTCTRL_ABUSPORTSELCH0_NONE (_VDAC_OUTCTRL_ABUSPORTSELCH0_NONE << 12) /**< Shifted mode NONE for VDAC_OUTCTRL */
+#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA << 12) /**< Shifted mode PORTA for VDAC_OUTCTRL */
+#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB << 12) /**< Shifted mode PORTB for VDAC_OUTCTRL */
+#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC << 12) /**< Shifted mode PORTC for VDAC_OUTCTRL */
+#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD << 12) /**< Shifted mode PORTD for VDAC_OUTCTRL */
+#define _VDAC_OUTCTRL_ABUSPINSELCH0_SHIFT 15 /**< Shift value for VDAC_ABUSPINSELCH0 */
+#define _VDAC_OUTCTRL_ABUSPINSELCH0_MASK 0x1F8000UL /**< Bit mask for VDAC_ABUSPINSELCH0 */
+#define _VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */
+#define VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT (_VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */
+#define _VDAC_OUTCTRL_ABUSPORTSELCH1_SHIFT 22 /**< Shift value for VDAC_ABUSPORTSELCH1 */
+#define _VDAC_OUTCTRL_ABUSPORTSELCH1_MASK 0x1C00000UL /**< Bit mask for VDAC_ABUSPORTSELCH1 */
+#define _VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */
+#define _VDAC_OUTCTRL_ABUSPORTSELCH1_NONE 0x00000000UL /**< Mode NONE for VDAC_OUTCTRL */
+#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA 0x00000001UL /**< Mode PORTA for VDAC_OUTCTRL */
+#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB 0x00000002UL /**< Mode PORTB for VDAC_OUTCTRL */
+#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC 0x00000003UL /**< Mode PORTC for VDAC_OUTCTRL */
+#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD 0x00000004UL /**< Mode PORTD for VDAC_OUTCTRL */
+#define VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT (_VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */
+#define VDAC_OUTCTRL_ABUSPORTSELCH1_NONE (_VDAC_OUTCTRL_ABUSPORTSELCH1_NONE << 22) /**< Shifted mode NONE for VDAC_OUTCTRL */
+#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA << 22) /**< Shifted mode PORTA for VDAC_OUTCTRL */
+#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB << 22) /**< Shifted mode PORTB for VDAC_OUTCTRL */
+#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC << 22) /**< Shifted mode PORTC for VDAC_OUTCTRL */
+#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD << 22) /**< Shifted mode PORTD for VDAC_OUTCTRL */
+#define _VDAC_OUTCTRL_ABUSPINSELCH1_SHIFT 25 /**< Shift value for VDAC_ABUSPINSELCH1 */
+#define _VDAC_OUTCTRL_ABUSPINSELCH1_MASK 0x7E000000UL /**< Bit mask for VDAC_ABUSPINSELCH1 */
+#define _VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */
+#define VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT (_VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT << 25) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */
+
+/* Bit fields for VDAC OUTTIMERCFG */
+#define _VDAC_OUTTIMERCFG_RESETVALUE 0x00000000UL /**< Default value for VDAC_OUTTIMERCFG */
+#define _VDAC_OUTTIMERCFG_MASK 0x01FF83FFUL /**< Mask for VDAC_OUTTIMERCFG */
+#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_SHIFT 0 /**< Shift value for VDAC_CH0OUTHOLDTIME */
+#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_MASK 0x3FFUL /**< Bit mask for VDAC_CH0OUTHOLDTIME */
+#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTTIMERCFG */
+#define VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT (_VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OUTTIMERCFG */
+#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_SHIFT 15 /**< Shift value for VDAC_CH1OUTHOLDTIME */
+#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_MASK 0x1FF8000UL /**< Bit mask for VDAC_CH1OUTHOLDTIME */
+#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTTIMERCFG */
+#define VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT (_VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_OUTTIMERCFG */
+
+/** @} End of group EFR32MG24_VDAC_BitFields */
+/** @} End of group EFR32MG24_VDAC */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_VDAC_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_wdog.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_wdog.h
new file mode 100644
index 00000000..60f9144c
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24_wdog.h
@@ -0,0 +1,375 @@
+/**************************************************************************//**
+ * @file
+ * @brief EFR32MG24 WDOG register and bit field definitions
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24_WDOG_H
+#define EFR32MG24_WDOG_H
+#define WDOG_HAS_SET_CLEAR
+
+/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
+ * @defgroup EFR32MG24_WDOG WDOG
+ * @{
+ * @brief EFR32MG24 WDOG Register Declaration.
+ *****************************************************************************/
+
+/** WDOG Register Declaration. */
+typedef struct {
+ __IM uint32_t IPVERSION; /**< IP Version Register */
+ __IOM uint32_t EN; /**< Enable Register */
+ __IOM uint32_t CFG; /**< Configuration Register */
+ __IOM uint32_t CMD; /**< Command Register */
+ uint32_t RESERVED0[1U]; /**< Reserved for future use */
+ __IM uint32_t STATUS; /**< Status Register */
+ __IOM uint32_t IF; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN; /**< Interrupt Enable Register */
+ __IOM uint32_t LOCK; /**< Lock Register */
+ __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
+ uint32_t RESERVED1[1014U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_SET; /**< IP Version Register */
+ __IOM uint32_t EN_SET; /**< Enable Register */
+ __IOM uint32_t CFG_SET; /**< Configuration Register */
+ __IOM uint32_t CMD_SET; /**< Command Register */
+ uint32_t RESERVED2[1U]; /**< Reserved for future use */
+ __IM uint32_t STATUS_SET; /**< Status Register */
+ __IOM uint32_t IF_SET; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
+ __IOM uint32_t LOCK_SET; /**< Lock Register */
+ __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */
+ uint32_t RESERVED3[1014U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_CLR; /**< IP Version Register */
+ __IOM uint32_t EN_CLR; /**< Enable Register */
+ __IOM uint32_t CFG_CLR; /**< Configuration Register */
+ __IOM uint32_t CMD_CLR; /**< Command Register */
+ uint32_t RESERVED4[1U]; /**< Reserved for future use */
+ __IM uint32_t STATUS_CLR; /**< Status Register */
+ __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
+ __IOM uint32_t LOCK_CLR; /**< Lock Register */
+ __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */
+ uint32_t RESERVED5[1014U]; /**< Reserved for future use */
+ __IM uint32_t IPVERSION_TGL; /**< IP Version Register */
+ __IOM uint32_t EN_TGL; /**< Enable Register */
+ __IOM uint32_t CFG_TGL; /**< Configuration Register */
+ __IOM uint32_t CMD_TGL; /**< Command Register */
+ uint32_t RESERVED6[1U]; /**< Reserved for future use */
+ __IM uint32_t STATUS_TGL; /**< Status Register */
+ __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
+ __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
+ __IOM uint32_t LOCK_TGL; /**< Lock Register */
+ __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */
+} WDOG_TypeDef;
+/** @} End of group EFR32MG24_WDOG */
+
+/**************************************************************************//**
+ * @addtogroup EFR32MG24_WDOG
+ * @{
+ * @defgroup EFR32MG24_WDOG_BitFields WDOG Bit Fields
+ * @{
+ *****************************************************************************/
+
+/* Bit fields for WDOG IPVERSION */
+#define _WDOG_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for WDOG_IPVERSION */
+#define _WDOG_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for WDOG_IPVERSION */
+#define _WDOG_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for WDOG_IPVERSION */
+#define _WDOG_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for WDOG_IPVERSION */
+#define _WDOG_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for WDOG_IPVERSION */
+#define WDOG_IPVERSION_IPVERSION_DEFAULT (_WDOG_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IPVERSION */
+
+/* Bit fields for WDOG EN */
+#define _WDOG_EN_RESETVALUE 0x00000000UL /**< Default value for WDOG_EN */
+#define _WDOG_EN_MASK 0x00000003UL /**< Mask for WDOG_EN */
+#define WDOG_EN_EN (0x1UL << 0) /**< Module Enable */
+#define _WDOG_EN_EN_SHIFT 0 /**< Shift value for WDOG_EN */
+#define _WDOG_EN_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */
+#define _WDOG_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_EN */
+#define WDOG_EN_EN_DEFAULT (_WDOG_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_EN */
+#define WDOG_EN_DISABLING (0x1UL << 1) /**< Disabling busy status */
+#define _WDOG_EN_DISABLING_SHIFT 1 /**< Shift value for WDOG_DISABLING */
+#define _WDOG_EN_DISABLING_MASK 0x2UL /**< Bit mask for WDOG_DISABLING */
+#define _WDOG_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_EN */
+#define WDOG_EN_DISABLING_DEFAULT (_WDOG_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_EN */
+
+/* Bit fields for WDOG CFG */
+#define _WDOG_CFG_RESETVALUE 0x000F0000UL /**< Default value for WDOG_CFG */
+#define _WDOG_CFG_MASK 0x730F073FUL /**< Mask for WDOG_CFG */
+#define WDOG_CFG_CLRSRC (0x1UL << 0) /**< WDOG Clear Source */
+#define _WDOG_CFG_CLRSRC_SHIFT 0 /**< Shift value for WDOG_CLRSRC */
+#define _WDOG_CFG_CLRSRC_MASK 0x1UL /**< Bit mask for WDOG_CLRSRC */
+#define _WDOG_CFG_CLRSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */
+#define _WDOG_CFG_CLRSRC_SW 0x00000000UL /**< Mode SW for WDOG_CFG */
+#define _WDOG_CFG_CLRSRC_PRSSRC0 0x00000001UL /**< Mode PRSSRC0 for WDOG_CFG */
+#define WDOG_CFG_CLRSRC_DEFAULT (_WDOG_CFG_CLRSRC_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CFG */
+#define WDOG_CFG_CLRSRC_SW (_WDOG_CFG_CLRSRC_SW << 0) /**< Shifted mode SW for WDOG_CFG */
+#define WDOG_CFG_CLRSRC_PRSSRC0 (_WDOG_CFG_CLRSRC_PRSSRC0 << 0) /**< Shifted mode PRSSRC0 for WDOG_CFG */
+#define WDOG_CFG_EM1RUN (0x1UL << 1) /**< EM1 Run */
+#define _WDOG_CFG_EM1RUN_SHIFT 1 /**< Shift value for WDOG_EM1RUN */
+#define _WDOG_CFG_EM1RUN_MASK 0x2UL /**< Bit mask for WDOG_EM1RUN */
+#define _WDOG_CFG_EM1RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */
+#define _WDOG_CFG_EM1RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */
+#define _WDOG_CFG_EM1RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */
+#define WDOG_CFG_EM1RUN_DEFAULT (_WDOG_CFG_EM1RUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CFG */
+#define WDOG_CFG_EM1RUN_DISABLE (_WDOG_CFG_EM1RUN_DISABLE << 1) /**< Shifted mode DISABLE for WDOG_CFG */
+#define WDOG_CFG_EM1RUN_ENABLE (_WDOG_CFG_EM1RUN_ENABLE << 1) /**< Shifted mode ENABLE for WDOG_CFG */
+#define WDOG_CFG_EM2RUN (0x1UL << 2) /**< EM2 Run */
+#define _WDOG_CFG_EM2RUN_SHIFT 2 /**< Shift value for WDOG_EM2RUN */
+#define _WDOG_CFG_EM2RUN_MASK 0x4UL /**< Bit mask for WDOG_EM2RUN */
+#define _WDOG_CFG_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */
+#define _WDOG_CFG_EM2RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */
+#define _WDOG_CFG_EM2RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */
+#define WDOG_CFG_EM2RUN_DEFAULT (_WDOG_CFG_EM2RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CFG */
+#define WDOG_CFG_EM2RUN_DISABLE (_WDOG_CFG_EM2RUN_DISABLE << 2) /**< Shifted mode DISABLE for WDOG_CFG */
+#define WDOG_CFG_EM2RUN_ENABLE (_WDOG_CFG_EM2RUN_ENABLE << 2) /**< Shifted mode ENABLE for WDOG_CFG */
+#define WDOG_CFG_EM3RUN (0x1UL << 3) /**< EM3 Run */
+#define _WDOG_CFG_EM3RUN_SHIFT 3 /**< Shift value for WDOG_EM3RUN */
+#define _WDOG_CFG_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */
+#define _WDOG_CFG_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */
+#define _WDOG_CFG_EM3RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */
+#define _WDOG_CFG_EM3RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */
+#define WDOG_CFG_EM3RUN_DEFAULT (_WDOG_CFG_EM3RUN_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CFG */
+#define WDOG_CFG_EM3RUN_DISABLE (_WDOG_CFG_EM3RUN_DISABLE << 3) /**< Shifted mode DISABLE for WDOG_CFG */
+#define WDOG_CFG_EM3RUN_ENABLE (_WDOG_CFG_EM3RUN_ENABLE << 3) /**< Shifted mode ENABLE for WDOG_CFG */
+#define WDOG_CFG_EM4BLOCK (0x1UL << 4) /**< EM4 Block */
+#define _WDOG_CFG_EM4BLOCK_SHIFT 4 /**< Shift value for WDOG_EM4BLOCK */
+#define _WDOG_CFG_EM4BLOCK_MASK 0x10UL /**< Bit mask for WDOG_EM4BLOCK */
+#define _WDOG_CFG_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */
+#define _WDOG_CFG_EM4BLOCK_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */
+#define _WDOG_CFG_EM4BLOCK_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */
+#define WDOG_CFG_EM4BLOCK_DEFAULT (_WDOG_CFG_EM4BLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CFG */
+#define WDOG_CFG_EM4BLOCK_DISABLE (_WDOG_CFG_EM4BLOCK_DISABLE << 4) /**< Shifted mode DISABLE for WDOG_CFG */
+#define WDOG_CFG_EM4BLOCK_ENABLE (_WDOG_CFG_EM4BLOCK_ENABLE << 4) /**< Shifted mode ENABLE for WDOG_CFG */
+#define WDOG_CFG_DEBUGRUN (0x1UL << 5) /**< Debug Mode Run */
+#define _WDOG_CFG_DEBUGRUN_SHIFT 5 /**< Shift value for WDOG_DEBUGRUN */
+#define _WDOG_CFG_DEBUGRUN_MASK 0x20UL /**< Bit mask for WDOG_DEBUGRUN */
+#define _WDOG_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */
+#define _WDOG_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */
+#define _WDOG_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */
+#define WDOG_CFG_DEBUGRUN_DEFAULT (_WDOG_CFG_DEBUGRUN_DEFAULT << 5) /**< Shifted mode DEFAULT for WDOG_CFG */
+#define WDOG_CFG_DEBUGRUN_DISABLE (_WDOG_CFG_DEBUGRUN_DISABLE << 5) /**< Shifted mode DISABLE for WDOG_CFG */
+#define WDOG_CFG_DEBUGRUN_ENABLE (_WDOG_CFG_DEBUGRUN_ENABLE << 5) /**< Shifted mode ENABLE for WDOG_CFG */
+#define WDOG_CFG_WDOGRSTDIS (0x1UL << 8) /**< WDOG Reset Disable */
+#define _WDOG_CFG_WDOGRSTDIS_SHIFT 8 /**< Shift value for WDOG_WDOGRSTDIS */
+#define _WDOG_CFG_WDOGRSTDIS_MASK 0x100UL /**< Bit mask for WDOG_WDOGRSTDIS */
+#define _WDOG_CFG_WDOGRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */
+#define _WDOG_CFG_WDOGRSTDIS_EN 0x00000000UL /**< Mode EN for WDOG_CFG */
+#define _WDOG_CFG_WDOGRSTDIS_DIS 0x00000001UL /**< Mode DIS for WDOG_CFG */
+#define WDOG_CFG_WDOGRSTDIS_DEFAULT (_WDOG_CFG_WDOGRSTDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CFG */
+#define WDOG_CFG_WDOGRSTDIS_EN (_WDOG_CFG_WDOGRSTDIS_EN << 8) /**< Shifted mode EN for WDOG_CFG */
+#define WDOG_CFG_WDOGRSTDIS_DIS (_WDOG_CFG_WDOGRSTDIS_DIS << 8) /**< Shifted mode DIS for WDOG_CFG */
+#define WDOG_CFG_PRS0MISSRSTEN (0x1UL << 9) /**< PRS Src0 Missing Event WDOG Reset */
+#define _WDOG_CFG_PRS0MISSRSTEN_SHIFT 9 /**< Shift value for WDOG_PRS0MISSRSTEN */
+#define _WDOG_CFG_PRS0MISSRSTEN_MASK 0x200UL /**< Bit mask for WDOG_PRS0MISSRSTEN */
+#define _WDOG_CFG_PRS0MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */
+#define WDOG_CFG_PRS0MISSRSTEN_DEFAULT (_WDOG_CFG_PRS0MISSRSTEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WDOG_CFG */
+#define WDOG_CFG_PRS1MISSRSTEN (0x1UL << 10) /**< PRS Src1 Missing Event WDOG Reset */
+#define _WDOG_CFG_PRS1MISSRSTEN_SHIFT 10 /**< Shift value for WDOG_PRS1MISSRSTEN */
+#define _WDOG_CFG_PRS1MISSRSTEN_MASK 0x400UL /**< Bit mask for WDOG_PRS1MISSRSTEN */
+#define _WDOG_CFG_PRS1MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */
+#define WDOG_CFG_PRS1MISSRSTEN_DEFAULT (_WDOG_CFG_PRS1MISSRSTEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WDOG_CFG */
+#define _WDOG_CFG_PERSEL_SHIFT 16 /**< Shift value for WDOG_PERSEL */
+#define _WDOG_CFG_PERSEL_MASK 0xF0000UL /**< Bit mask for WDOG_PERSEL */
+#define _WDOG_CFG_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CFG */
+#define _WDOG_CFG_PERSEL_SEL0 0x00000000UL /**< Mode SEL0 for WDOG_CFG */
+#define _WDOG_CFG_PERSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */
+#define _WDOG_CFG_PERSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */
+#define _WDOG_CFG_PERSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */
+#define _WDOG_CFG_PERSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */
+#define _WDOG_CFG_PERSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */
+#define _WDOG_CFG_PERSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */
+#define _WDOG_CFG_PERSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */
+#define _WDOG_CFG_PERSEL_SEL8 0x00000008UL /**< Mode SEL8 for WDOG_CFG */
+#define _WDOG_CFG_PERSEL_SEL9 0x00000009UL /**< Mode SEL9 for WDOG_CFG */
+#define _WDOG_CFG_PERSEL_SEL10 0x0000000AUL /**< Mode SEL10 for WDOG_CFG */
+#define _WDOG_CFG_PERSEL_SEL11 0x0000000BUL /**< Mode SEL11 for WDOG_CFG */
+#define _WDOG_CFG_PERSEL_SEL12 0x0000000CUL /**< Mode SEL12 for WDOG_CFG */
+#define _WDOG_CFG_PERSEL_SEL13 0x0000000DUL /**< Mode SEL13 for WDOG_CFG */
+#define _WDOG_CFG_PERSEL_SEL14 0x0000000EUL /**< Mode SEL14 for WDOG_CFG */
+#define _WDOG_CFG_PERSEL_SEL15 0x0000000FUL /**< Mode SEL15 for WDOG_CFG */
+#define WDOG_CFG_PERSEL_DEFAULT (_WDOG_CFG_PERSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WDOG_CFG */
+#define WDOG_CFG_PERSEL_SEL0 (_WDOG_CFG_PERSEL_SEL0 << 16) /**< Shifted mode SEL0 for WDOG_CFG */
+#define WDOG_CFG_PERSEL_SEL1 (_WDOG_CFG_PERSEL_SEL1 << 16) /**< Shifted mode SEL1 for WDOG_CFG */
+#define WDOG_CFG_PERSEL_SEL2 (_WDOG_CFG_PERSEL_SEL2 << 16) /**< Shifted mode SEL2 for WDOG_CFG */
+#define WDOG_CFG_PERSEL_SEL3 (_WDOG_CFG_PERSEL_SEL3 << 16) /**< Shifted mode SEL3 for WDOG_CFG */
+#define WDOG_CFG_PERSEL_SEL4 (_WDOG_CFG_PERSEL_SEL4 << 16) /**< Shifted mode SEL4 for WDOG_CFG */
+#define WDOG_CFG_PERSEL_SEL5 (_WDOG_CFG_PERSEL_SEL5 << 16) /**< Shifted mode SEL5 for WDOG_CFG */
+#define WDOG_CFG_PERSEL_SEL6 (_WDOG_CFG_PERSEL_SEL6 << 16) /**< Shifted mode SEL6 for WDOG_CFG */
+#define WDOG_CFG_PERSEL_SEL7 (_WDOG_CFG_PERSEL_SEL7 << 16) /**< Shifted mode SEL7 for WDOG_CFG */
+#define WDOG_CFG_PERSEL_SEL8 (_WDOG_CFG_PERSEL_SEL8 << 16) /**< Shifted mode SEL8 for WDOG_CFG */
+#define WDOG_CFG_PERSEL_SEL9 (_WDOG_CFG_PERSEL_SEL9 << 16) /**< Shifted mode SEL9 for WDOG_CFG */
+#define WDOG_CFG_PERSEL_SEL10 (_WDOG_CFG_PERSEL_SEL10 << 16) /**< Shifted mode SEL10 for WDOG_CFG */
+#define WDOG_CFG_PERSEL_SEL11 (_WDOG_CFG_PERSEL_SEL11 << 16) /**< Shifted mode SEL11 for WDOG_CFG */
+#define WDOG_CFG_PERSEL_SEL12 (_WDOG_CFG_PERSEL_SEL12 << 16) /**< Shifted mode SEL12 for WDOG_CFG */
+#define WDOG_CFG_PERSEL_SEL13 (_WDOG_CFG_PERSEL_SEL13 << 16) /**< Shifted mode SEL13 for WDOG_CFG */
+#define WDOG_CFG_PERSEL_SEL14 (_WDOG_CFG_PERSEL_SEL14 << 16) /**< Shifted mode SEL14 for WDOG_CFG */
+#define WDOG_CFG_PERSEL_SEL15 (_WDOG_CFG_PERSEL_SEL15 << 16) /**< Shifted mode SEL15 for WDOG_CFG */
+#define _WDOG_CFG_WARNSEL_SHIFT 24 /**< Shift value for WDOG_WARNSEL */
+#define _WDOG_CFG_WARNSEL_MASK 0x3000000UL /**< Bit mask for WDOG_WARNSEL */
+#define _WDOG_CFG_WARNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */
+#define _WDOG_CFG_WARNSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */
+#define _WDOG_CFG_WARNSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */
+#define _WDOG_CFG_WARNSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */
+#define _WDOG_CFG_WARNSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */
+#define WDOG_CFG_WARNSEL_DEFAULT (_WDOG_CFG_WARNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for WDOG_CFG */
+#define WDOG_CFG_WARNSEL_DIS (_WDOG_CFG_WARNSEL_DIS << 24) /**< Shifted mode DIS for WDOG_CFG */
+#define WDOG_CFG_WARNSEL_SEL1 (_WDOG_CFG_WARNSEL_SEL1 << 24) /**< Shifted mode SEL1 for WDOG_CFG */
+#define WDOG_CFG_WARNSEL_SEL2 (_WDOG_CFG_WARNSEL_SEL2 << 24) /**< Shifted mode SEL2 for WDOG_CFG */
+#define WDOG_CFG_WARNSEL_SEL3 (_WDOG_CFG_WARNSEL_SEL3 << 24) /**< Shifted mode SEL3 for WDOG_CFG */
+#define _WDOG_CFG_WINSEL_SHIFT 28 /**< Shift value for WDOG_WINSEL */
+#define _WDOG_CFG_WINSEL_MASK 0x70000000UL /**< Bit mask for WDOG_WINSEL */
+#define _WDOG_CFG_WINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */
+#define _WDOG_CFG_WINSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */
+#define _WDOG_CFG_WINSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */
+#define _WDOG_CFG_WINSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */
+#define _WDOG_CFG_WINSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */
+#define _WDOG_CFG_WINSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */
+#define _WDOG_CFG_WINSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */
+#define _WDOG_CFG_WINSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */
+#define _WDOG_CFG_WINSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */
+#define WDOG_CFG_WINSEL_DEFAULT (_WDOG_CFG_WINSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for WDOG_CFG */
+#define WDOG_CFG_WINSEL_DIS (_WDOG_CFG_WINSEL_DIS << 28) /**< Shifted mode DIS for WDOG_CFG */
+#define WDOG_CFG_WINSEL_SEL1 (_WDOG_CFG_WINSEL_SEL1 << 28) /**< Shifted mode SEL1 for WDOG_CFG */
+#define WDOG_CFG_WINSEL_SEL2 (_WDOG_CFG_WINSEL_SEL2 << 28) /**< Shifted mode SEL2 for WDOG_CFG */
+#define WDOG_CFG_WINSEL_SEL3 (_WDOG_CFG_WINSEL_SEL3 << 28) /**< Shifted mode SEL3 for WDOG_CFG */
+#define WDOG_CFG_WINSEL_SEL4 (_WDOG_CFG_WINSEL_SEL4 << 28) /**< Shifted mode SEL4 for WDOG_CFG */
+#define WDOG_CFG_WINSEL_SEL5 (_WDOG_CFG_WINSEL_SEL5 << 28) /**< Shifted mode SEL5 for WDOG_CFG */
+#define WDOG_CFG_WINSEL_SEL6 (_WDOG_CFG_WINSEL_SEL6 << 28) /**< Shifted mode SEL6 for WDOG_CFG */
+#define WDOG_CFG_WINSEL_SEL7 (_WDOG_CFG_WINSEL_SEL7 << 28) /**< Shifted mode SEL7 for WDOG_CFG */
+
+/* Bit fields for WDOG CMD */
+#define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */
+#define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */
+#define WDOG_CMD_CLEAR (0x1UL << 0) /**< WDOG Timer Clear */
+#define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */
+#define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */
+#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */
+#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */
+#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */
+#define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */
+#define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */
+#define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */
+
+/* Bit fields for WDOG STATUS */
+#define _WDOG_STATUS_RESETVALUE 0x00000000UL /**< Default value for WDOG_STATUS */
+#define _WDOG_STATUS_MASK 0x80000000UL /**< Mask for WDOG_STATUS */
+#define WDOG_STATUS_LOCK (0x1UL << 31) /**< WDOG Configuration Lock Status */
+#define _WDOG_STATUS_LOCK_SHIFT 31 /**< Shift value for WDOG_LOCK */
+#define _WDOG_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for WDOG_LOCK */
+#define _WDOG_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_STATUS */
+#define _WDOG_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WDOG_STATUS */
+#define _WDOG_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for WDOG_STATUS */
+#define WDOG_STATUS_LOCK_DEFAULT (_WDOG_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for WDOG_STATUS */
+#define WDOG_STATUS_LOCK_UNLOCKED (_WDOG_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for WDOG_STATUS */
+#define WDOG_STATUS_LOCK_LOCKED (_WDOG_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for WDOG_STATUS */
+
+/* Bit fields for WDOG IF */
+#define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */
+#define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */
+#define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */
+#define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */
+#define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */
+#define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
+#define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */
+#define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */
+#define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */
+#define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */
+#define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
+#define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */
+#define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */
+#define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */
+#define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */
+#define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
+#define WDOG_IF_WIN_DEFAULT (_WDOG_IF_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IF */
+#define WDOG_IF_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Flag */
+#define _WDOG_IF_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */
+#define _WDOG_IF_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */
+#define _WDOG_IF_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
+#define WDOG_IF_PEM0_DEFAULT (_WDOG_IF_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IF */
+#define WDOG_IF_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Flag */
+#define _WDOG_IF_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */
+#define _WDOG_IF_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */
+#define _WDOG_IF_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
+#define WDOG_IF_PEM1_DEFAULT (_WDOG_IF_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IF */
+
+/* Bit fields for WDOG IEN */
+#define _WDOG_IEN_RESETVALUE 0x00000000UL /**< Default value for WDOG_IEN */
+#define _WDOG_IEN_MASK 0x0000001FUL /**< Mask for WDOG_IEN */
+#define WDOG_IEN_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Enable */
+#define _WDOG_IEN_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */
+#define _WDOG_IEN_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */
+#define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
+#define WDOG_IEN_TOUT_DEFAULT (_WDOG_IEN_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IEN */
+#define WDOG_IEN_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Enable */
+#define _WDOG_IEN_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */
+#define _WDOG_IEN_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */
+#define _WDOG_IEN_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
+#define WDOG_IEN_WARN_DEFAULT (_WDOG_IEN_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IEN */
+#define WDOG_IEN_WIN (0x1UL << 2) /**< WDOG Window Interrupt Enable */
+#define _WDOG_IEN_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */
+#define _WDOG_IEN_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */
+#define _WDOG_IEN_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
+#define WDOG_IEN_WIN_DEFAULT (_WDOG_IEN_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IEN */
+#define WDOG_IEN_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Enable */
+#define _WDOG_IEN_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */
+#define _WDOG_IEN_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */
+#define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
+#define WDOG_IEN_PEM0_DEFAULT (_WDOG_IEN_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IEN */
+#define WDOG_IEN_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Enable */
+#define _WDOG_IEN_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */
+#define _WDOG_IEN_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */
+#define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
+#define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */
+
+/* Bit fields for WDOG LOCK */
+#define _WDOG_LOCK_RESETVALUE 0x0000ABE8UL /**< Default value for WDOG_LOCK */
+#define _WDOG_LOCK_MASK 0x0000FFFFUL /**< Mask for WDOG_LOCK */
+#define _WDOG_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for WDOG_LOCKKEY */
+#define _WDOG_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for WDOG_LOCKKEY */
+#define _WDOG_LOCK_LOCKKEY_DEFAULT 0x0000ABE8UL /**< Mode DEFAULT for WDOG_LOCK */
+#define _WDOG_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WDOG_LOCK */
+#define _WDOG_LOCK_LOCKKEY_UNLOCK 0x0000ABE8UL /**< Mode UNLOCK for WDOG_LOCK */
+#define WDOG_LOCK_LOCKKEY_DEFAULT (_WDOG_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_LOCK */
+#define WDOG_LOCK_LOCKKEY_LOCK (_WDOG_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WDOG_LOCK */
+#define WDOG_LOCK_LOCKKEY_UNLOCK (_WDOG_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WDOG_LOCK */
+
+/* Bit fields for WDOG SYNCBUSY */
+#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */
+#define _WDOG_SYNCBUSY_MASK 0x00000001UL /**< Mask for WDOG_SYNCBUSY */
+#define WDOG_SYNCBUSY_CMD (0x1UL << 0) /**< Sync Busy for Cmd Register */
+#define _WDOG_SYNCBUSY_CMD_SHIFT 0 /**< Shift value for WDOG_CMD */
+#define _WDOG_SYNCBUSY_CMD_MASK 0x1UL /**< Bit mask for WDOG_CMD */
+#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */
+#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
+
+/** @} End of group EFR32MG24_WDOG_BitFields */
+/** @} End of group EFR32MG24_WDOG */
+/** @} End of group Parts */
+
+#endif /* EFR32MG24_WDOG_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a010f1024im40.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a010f1024im40.h
new file mode 100644
index 00000000..7a95189c
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a010f1024im40.h
@@ -0,0 +1,1413 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24A010F1024IM40
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24A010F1024IM40_H
+#define EFR32MG24A010F1024IM40_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1024IM40 EFR32MG24A010F1024IM40
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1024IM40_Core EFR32MG24A010F1024IM40 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24A010F1024IM40_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24A010F1024IM40_Part EFR32MG24A010F1024IM40 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24A010F1024IM40)
+#define EFR32MG24A010F1024IM40 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24A010F1024IM40" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24A010F1024IM40 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24A010F1024IM40_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1024IM40_Peripheral_TypeDefs EFR32MG24A010F1024IM40 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24A010F1024IM40_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1024IM40_Peripheral_Base EFR32MG24A010F1024IM40 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24A010F1024IM40_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1024IM40_Peripheral_Declaration EFR32MG24A010F1024IM40 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24A010F1024IM40_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1024IM40_Peripheral_Parameters EFR32MG24A010F1024IM40 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24A010F1024IM40_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24A010F1024IM40 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a010f1024im48.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a010f1024im48.h
new file mode 100644
index 00000000..4c2de2b9
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a010f1024im48.h
@@ -0,0 +1,1419 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24A010F1024IM48
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24A010F1024IM48_H
+#define EFR32MG24A010F1024IM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1024IM48 EFR32MG24A010F1024IM48
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1024IM48_Core EFR32MG24A010F1024IM48 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24A010F1024IM48_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24A010F1024IM48_Part EFR32MG24A010F1024IM48 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24A010F1024IM48)
+#define EFR32MG24A010F1024IM48 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24A010F1024IM48" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24A010F1024IM48 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */
+#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */
+#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */
+#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */
+#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24A010F1024IM48_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1024IM48_Peripheral_TypeDefs EFR32MG24A010F1024IM48 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24A010F1024IM48_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1024IM48_Peripheral_Base EFR32MG24A010F1024IM48 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24A010F1024IM48_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1024IM48_Peripheral_Declaration EFR32MG24A010F1024IM48 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24A010F1024IM48_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1024IM48_Peripheral_Parameters EFR32MG24A010F1024IM48 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24A010F1024IM48_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24A010F1024IM48 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a010f1536gm40.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a010f1536gm40.h
new file mode 100644
index 00000000..eee9bdb7
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a010f1536gm40.h
@@ -0,0 +1,1413 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24A010F1536GM40
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24A010F1536GM40_H
+#define EFR32MG24A010F1536GM40_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1536GM40 EFR32MG24A010F1536GM40
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1536GM40_Core EFR32MG24A010F1536GM40 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24A010F1536GM40_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24A010F1536GM40_Part EFR32MG24A010F1536GM40 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24A010F1536GM40)
+#define EFR32MG24A010F1536GM40 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24A010F1536GM40" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24A010F1536GM40 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24A010F1536GM40_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1536GM40_Peripheral_TypeDefs EFR32MG24A010F1536GM40 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24A010F1536GM40_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1536GM40_Peripheral_Base EFR32MG24A010F1536GM40 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24A010F1536GM40_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1536GM40_Peripheral_Declaration EFR32MG24A010F1536GM40 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24A010F1536GM40_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1536GM40_Peripheral_Parameters EFR32MG24A010F1536GM40 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24A010F1536GM40_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24A010F1536GM40 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a010f1536gm48.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a010f1536gm48.h
new file mode 100644
index 00000000..c0393e76
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a010f1536gm48.h
@@ -0,0 +1,1419 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24A010F1536GM48
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24A010F1536GM48_H
+#define EFR32MG24A010F1536GM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1536GM48 EFR32MG24A010F1536GM48
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1536GM48_Core EFR32MG24A010F1536GM48 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24A010F1536GM48_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24A010F1536GM48_Part EFR32MG24A010F1536GM48 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24A010F1536GM48)
+#define EFR32MG24A010F1536GM48 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24A010F1536GM48" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24A010F1536GM48 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */
+#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */
+#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */
+#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */
+#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24A010F1536GM48_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1536GM48_Peripheral_TypeDefs EFR32MG24A010F1536GM48 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24A010F1536GM48_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1536GM48_Peripheral_Base EFR32MG24A010F1536GM48 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24A010F1536GM48_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1536GM48_Peripheral_Declaration EFR32MG24A010F1536GM48 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24A010F1536GM48_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1536GM48_Peripheral_Parameters EFR32MG24A010F1536GM48 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24A010F1536GM48_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24A010F1536GM48 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a010f1536im40.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a010f1536im40.h
new file mode 100644
index 00000000..9351eee9
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a010f1536im40.h
@@ -0,0 +1,1413 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24A010F1536IM40
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24A010F1536IM40_H
+#define EFR32MG24A010F1536IM40_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1536IM40 EFR32MG24A010F1536IM40
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1536IM40_Core EFR32MG24A010F1536IM40 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24A010F1536IM40_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24A010F1536IM40_Part EFR32MG24A010F1536IM40 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24A010F1536IM40)
+#define EFR32MG24A010F1536IM40 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24A010F1536IM40" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24A010F1536IM40 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00030000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24A010F1536IM40_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1536IM40_Peripheral_TypeDefs EFR32MG24A010F1536IM40 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24A010F1536IM40_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1536IM40_Peripheral_Base EFR32MG24A010F1536IM40 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24A010F1536IM40_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1536IM40_Peripheral_Declaration EFR32MG24A010F1536IM40 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24A010F1536IM40_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1536IM40_Peripheral_Parameters EFR32MG24A010F1536IM40 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24A010F1536IM40_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24A010F1536IM40 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a010f1536im48.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a010f1536im48.h
new file mode 100644
index 00000000..58e28801
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a010f1536im48.h
@@ -0,0 +1,1419 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24A010F1536IM48
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24A010F1536IM48_H
+#define EFR32MG24A010F1536IM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1536IM48 EFR32MG24A010F1536IM48
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1536IM48_Core EFR32MG24A010F1536IM48 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24A010F1536IM48_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24A010F1536IM48_Part EFR32MG24A010F1536IM48 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24A010F1536IM48)
+#define EFR32MG24A010F1536IM48 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24A010F1536IM48" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24A010F1536IM48 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00030000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */
+#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */
+#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */
+#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */
+#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24A010F1536IM48_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1536IM48_Peripheral_TypeDefs EFR32MG24A010F1536IM48 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24A010F1536IM48_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1536IM48_Peripheral_Base EFR32MG24A010F1536IM48 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24A010F1536IM48_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1536IM48_Peripheral_Declaration EFR32MG24A010F1536IM48 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24A010F1536IM48_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A010F1536IM48_Peripheral_Parameters EFR32MG24A010F1536IM48 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24A010F1536IM48_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24A010F1536IM48 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a020f1024im40.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a020f1024im40.h
new file mode 100644
index 00000000..213e9647
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a020f1024im40.h
@@ -0,0 +1,1411 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24A020F1024IM40
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24A020F1024IM40_H
+#define EFR32MG24A020F1024IM40_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1024IM40 EFR32MG24A020F1024IM40
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1024IM40_Core EFR32MG24A020F1024IM40 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24A020F1024IM40_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24A020F1024IM40_Part EFR32MG24A020F1024IM40 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24A020F1024IM40)
+#define EFR32MG24A020F1024IM40 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24A020F1024IM40" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24A020F1024IM40 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24A020F1024IM40_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1024IM40_Peripheral_TypeDefs EFR32MG24A020F1024IM40 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24A020F1024IM40_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1024IM40_Peripheral_Base EFR32MG24A020F1024IM40 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24A020F1024IM40_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1024IM40_Peripheral_Declaration EFR32MG24A020F1024IM40 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24A020F1024IM40_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1024IM40_Peripheral_Parameters EFR32MG24A020F1024IM40 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24A020F1024IM40_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24A020F1024IM40 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a020f1024im48.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a020f1024im48.h
new file mode 100644
index 00000000..24bbb546
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a020f1024im48.h
@@ -0,0 +1,1417 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24A020F1024IM48
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24A020F1024IM48_H
+#define EFR32MG24A020F1024IM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1024IM48 EFR32MG24A020F1024IM48
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1024IM48_Core EFR32MG24A020F1024IM48 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24A020F1024IM48_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24A020F1024IM48_Part EFR32MG24A020F1024IM48 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24A020F1024IM48)
+#define EFR32MG24A020F1024IM48 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24A020F1024IM48" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24A020F1024IM48 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */
+#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */
+#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */
+#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */
+#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24A020F1024IM48_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1024IM48_Peripheral_TypeDefs EFR32MG24A020F1024IM48 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24A020F1024IM48_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1024IM48_Peripheral_Base EFR32MG24A020F1024IM48 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24A020F1024IM48_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1024IM48_Peripheral_Declaration EFR32MG24A020F1024IM48 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24A020F1024IM48_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1024IM48_Peripheral_Parameters EFR32MG24A020F1024IM48 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24A020F1024IM48_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24A020F1024IM48 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a020f1536gm40.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a020f1536gm40.h
new file mode 100644
index 00000000..ef7ed223
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a020f1536gm40.h
@@ -0,0 +1,1411 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24A020F1536GM40
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24A020F1536GM40_H
+#define EFR32MG24A020F1536GM40_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1536GM40 EFR32MG24A020F1536GM40
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1536GM40_Core EFR32MG24A020F1536GM40 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24A020F1536GM40_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24A020F1536GM40_Part EFR32MG24A020F1536GM40 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24A020F1536GM40)
+#define EFR32MG24A020F1536GM40 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24A020F1536GM40" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24A020F1536GM40 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24A020F1536GM40_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1536GM40_Peripheral_TypeDefs EFR32MG24A020F1536GM40 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24A020F1536GM40_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1536GM40_Peripheral_Base EFR32MG24A020F1536GM40 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24A020F1536GM40_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1536GM40_Peripheral_Declaration EFR32MG24A020F1536GM40 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24A020F1536GM40_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1536GM40_Peripheral_Parameters EFR32MG24A020F1536GM40 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24A020F1536GM40_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24A020F1536GM40 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a020f1536gm48.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a020f1536gm48.h
new file mode 100644
index 00000000..6f7def9f
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a020f1536gm48.h
@@ -0,0 +1,1417 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24A020F1536GM48
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24A020F1536GM48_H
+#define EFR32MG24A020F1536GM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1536GM48 EFR32MG24A020F1536GM48
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1536GM48_Core EFR32MG24A020F1536GM48 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24A020F1536GM48_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24A020F1536GM48_Part EFR32MG24A020F1536GM48 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24A020F1536GM48)
+#define EFR32MG24A020F1536GM48 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24A020F1536GM48" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24A020F1536GM48 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */
+#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */
+#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */
+#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */
+#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24A020F1536GM48_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1536GM48_Peripheral_TypeDefs EFR32MG24A020F1536GM48 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24A020F1536GM48_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1536GM48_Peripheral_Base EFR32MG24A020F1536GM48 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24A020F1536GM48_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1536GM48_Peripheral_Declaration EFR32MG24A020F1536GM48 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24A020F1536GM48_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1536GM48_Peripheral_Parameters EFR32MG24A020F1536GM48 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24A020F1536GM48_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24A020F1536GM48 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a020f1536im40.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a020f1536im40.h
new file mode 100644
index 00000000..53ec4a6c
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a020f1536im40.h
@@ -0,0 +1,1411 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24A020F1536IM40
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24A020F1536IM40_H
+#define EFR32MG24A020F1536IM40_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1536IM40 EFR32MG24A020F1536IM40
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1536IM40_Core EFR32MG24A020F1536IM40 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24A020F1536IM40_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24A020F1536IM40_Part EFR32MG24A020F1536IM40 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24A020F1536IM40)
+#define EFR32MG24A020F1536IM40 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24A020F1536IM40" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24A020F1536IM40 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00030000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24A020F1536IM40_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1536IM40_Peripheral_TypeDefs EFR32MG24A020F1536IM40 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24A020F1536IM40_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1536IM40_Peripheral_Base EFR32MG24A020F1536IM40 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24A020F1536IM40_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1536IM40_Peripheral_Declaration EFR32MG24A020F1536IM40 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24A020F1536IM40_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1536IM40_Peripheral_Parameters EFR32MG24A020F1536IM40 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24A020F1536IM40_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24A020F1536IM40 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a020f1536im48.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a020f1536im48.h
new file mode 100644
index 00000000..74908e7f
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a020f1536im48.h
@@ -0,0 +1,1417 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24A020F1536IM48
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24A020F1536IM48_H
+#define EFR32MG24A020F1536IM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1536IM48 EFR32MG24A020F1536IM48
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1536IM48_Core EFR32MG24A020F1536IM48 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24A020F1536IM48_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24A020F1536IM48_Part EFR32MG24A020F1536IM48 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24A020F1536IM48)
+#define EFR32MG24A020F1536IM48 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24A020F1536IM48" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24A020F1536IM48 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00030000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */
+#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */
+#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */
+#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */
+#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24A020F1536IM48_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1536IM48_Peripheral_TypeDefs EFR32MG24A020F1536IM48 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24A020F1536IM48_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1536IM48_Peripheral_Base EFR32MG24A020F1536IM48 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24A020F1536IM48_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1536IM48_Peripheral_Declaration EFR32MG24A020F1536IM48 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24A020F1536IM48_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A020F1536IM48_Peripheral_Parameters EFR32MG24A020F1536IM48 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24A020F1536IM48_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24A020F1536IM48 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a021f1024im40.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a021f1024im40.h
new file mode 100644
index 00000000..8ca31095
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a021f1024im40.h
@@ -0,0 +1,1410 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24A021F1024IM40
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24A021F1024IM40_H
+#define EFR32MG24A021F1024IM40_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A021F1024IM40 EFR32MG24A021F1024IM40
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A021F1024IM40_Core EFR32MG24A021F1024IM40 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24A021F1024IM40_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24A021F1024IM40_Part EFR32MG24A021F1024IM40 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24A021F1024IM40)
+#define EFR32MG24A021F1024IM40 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24A021F1024IM40" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24A021F1024IM40 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 7U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x007FUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24A021F1024IM40_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A021F1024IM40_Peripheral_TypeDefs EFR32MG24A021F1024IM40 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24A021F1024IM40_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A021F1024IM40_Peripheral_Base EFR32MG24A021F1024IM40 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24A021F1024IM40_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A021F1024IM40_Peripheral_Declaration EFR32MG24A021F1024IM40 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24A021F1024IM40_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A021F1024IM40_Peripheral_Parameters EFR32MG24A021F1024IM40 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24A021F1024IM40_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24A021F1024IM40 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a110f1024im48.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a110f1024im48.h
new file mode 100644
index 00000000..a58c8f3d
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a110f1024im48.h
@@ -0,0 +1,1415 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24A110F1024IM48
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24A110F1024IM48_H
+#define EFR32MG24A110F1024IM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A110F1024IM48 EFR32MG24A110F1024IM48
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A110F1024IM48_Core EFR32MG24A110F1024IM48 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24A110F1024IM48_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24A110F1024IM48_Part EFR32MG24A110F1024IM48 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24A110F1024IM48)
+#define EFR32MG24A110F1024IM48 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24A110F1024IM48" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24A110F1024IM48 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 8U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x00FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 4U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x000FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */
+#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */
+#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24A110F1024IM48_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A110F1024IM48_Peripheral_TypeDefs EFR32MG24A110F1024IM48 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24A110F1024IM48_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A110F1024IM48_Peripheral_Base EFR32MG24A110F1024IM48 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24A110F1024IM48_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A110F1024IM48_Peripheral_Declaration EFR32MG24A110F1024IM48 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24A110F1024IM48_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A110F1024IM48_Peripheral_Parameters EFR32MG24A110F1024IM48 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24A110F1024IM48_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24A110F1024IM48 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a110f1536gm48.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a110f1536gm48.h
new file mode 100644
index 00000000..63d7653d
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a110f1536gm48.h
@@ -0,0 +1,1415 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24A110F1536GM48
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24A110F1536GM48_H
+#define EFR32MG24A110F1536GM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A110F1536GM48 EFR32MG24A110F1536GM48
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A110F1536GM48_Core EFR32MG24A110F1536GM48 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24A110F1536GM48_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24A110F1536GM48_Part EFR32MG24A110F1536GM48 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24A110F1536GM48)
+#define EFR32MG24A110F1536GM48 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24A110F1536GM48" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24A110F1536GM48 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 8U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x00FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 4U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x000FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */
+#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */
+#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24A110F1536GM48_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A110F1536GM48_Peripheral_TypeDefs EFR32MG24A110F1536GM48 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24A110F1536GM48_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A110F1536GM48_Peripheral_Base EFR32MG24A110F1536GM48 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24A110F1536GM48_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A110F1536GM48_Peripheral_Declaration EFR32MG24A110F1536GM48 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24A110F1536GM48_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A110F1536GM48_Peripheral_Parameters EFR32MG24A110F1536GM48 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24A110F1536GM48_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24A110F1536GM48 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a111f1536gm48.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a111f1536gm48.h
new file mode 100644
index 00000000..13439ce1
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a111f1536gm48.h
@@ -0,0 +1,1414 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24A111F1536GM48
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24A111F1536GM48_H
+#define EFR32MG24A111F1536GM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A111F1536GM48 EFR32MG24A111F1536GM48
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A111F1536GM48_Core EFR32MG24A111F1536GM48 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24A111F1536GM48_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24A111F1536GM48_Part EFR32MG24A111F1536GM48 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24A111F1536GM48)
+#define EFR32MG24A111F1536GM48 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24A111F1536GM48" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24A111F1536GM48 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 8U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x00FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 4U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x000FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 9U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x02FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */
+#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24A111F1536GM48_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A111F1536GM48_Peripheral_TypeDefs EFR32MG24A111F1536GM48 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24A111F1536GM48_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A111F1536GM48_Peripheral_Base EFR32MG24A111F1536GM48 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24A111F1536GM48_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A111F1536GM48_Peripheral_Declaration EFR32MG24A111F1536GM48 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24A111F1536GM48_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A111F1536GM48_Peripheral_Parameters EFR32MG24A111F1536GM48 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24A111F1536GM48_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24A111F1536GM48 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a120f1536gm48.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a120f1536gm48.h
new file mode 100644
index 00000000..f776a0f3
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a120f1536gm48.h
@@ -0,0 +1,1413 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24A120F1536GM48
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24A120F1536GM48_H
+#define EFR32MG24A120F1536GM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A120F1536GM48 EFR32MG24A120F1536GM48
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A120F1536GM48_Core EFR32MG24A120F1536GM48 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24A120F1536GM48_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24A120F1536GM48_Part EFR32MG24A120F1536GM48 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24A120F1536GM48)
+#define EFR32MG24A120F1536GM48 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24A120F1536GM48" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24A120F1536GM48 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 8U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x00FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 4U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x000FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */
+#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */
+#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24A120F1536GM48_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A120F1536GM48_Peripheral_TypeDefs EFR32MG24A120F1536GM48 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24A120F1536GM48_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A120F1536GM48_Peripheral_Base EFR32MG24A120F1536GM48 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24A120F1536GM48_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A120F1536GM48_Peripheral_Declaration EFR32MG24A120F1536GM48 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24A120F1536GM48_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A120F1536GM48_Peripheral_Parameters EFR32MG24A120F1536GM48 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24A120F1536GM48_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24A120F1536GM48 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a121f1536gm48.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a121f1536gm48.h
new file mode 100644
index 00000000..c42e3b93
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a121f1536gm48.h
@@ -0,0 +1,1412 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24A121F1536GM48
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24A121F1536GM48_H
+#define EFR32MG24A121F1536GM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A121F1536GM48 EFR32MG24A121F1536GM48
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A121F1536GM48_Core EFR32MG24A121F1536GM48 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24A121F1536GM48_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24A121F1536GM48_Part EFR32MG24A121F1536GM48 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24A121F1536GM48)
+#define EFR32MG24A121F1536GM48 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24A121F1536GM48" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24A121F1536GM48 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 8U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x00FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 4U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x000FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 9U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x02FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */
+#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24A121F1536GM48_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A121F1536GM48_Peripheral_TypeDefs EFR32MG24A121F1536GM48 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24A121F1536GM48_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A121F1536GM48_Peripheral_Base EFR32MG24A121F1536GM48 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24A121F1536GM48_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A121F1536GM48_Peripheral_Declaration EFR32MG24A121F1536GM48 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24A121F1536GM48_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A121F1536GM48_Peripheral_Parameters EFR32MG24A121F1536GM48 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24A121F1536GM48_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24A121F1536GM48 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a410f1536im40.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a410f1536im40.h
new file mode 100644
index 00000000..fe1815fb
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a410f1536im40.h
@@ -0,0 +1,1413 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24A410F1536IM40
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24A410F1536IM40_H
+#define EFR32MG24A410F1536IM40_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A410F1536IM40 EFR32MG24A410F1536IM40
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A410F1536IM40_Core EFR32MG24A410F1536IM40 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24A410F1536IM40_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24A410F1536IM40_Part EFR32MG24A410F1536IM40 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24A410F1536IM40)
+#define EFR32MG24A410F1536IM40 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24A410F1536IM40" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24A410F1536IM40 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24A410F1536IM40_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A410F1536IM40_Peripheral_TypeDefs EFR32MG24A410F1536IM40 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24A410F1536IM40_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A410F1536IM40_Peripheral_Base EFR32MG24A410F1536IM40 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24A410F1536IM40_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A410F1536IM40_Peripheral_Declaration EFR32MG24A410F1536IM40 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24A410F1536IM40_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A410F1536IM40_Peripheral_Parameters EFR32MG24A410F1536IM40 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24A410F1536IM40_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24A410F1536IM40 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a410f1536im48.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a410f1536im48.h
new file mode 100644
index 00000000..29cc7830
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a410f1536im48.h
@@ -0,0 +1,1419 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24A410F1536IM48
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24A410F1536IM48_H
+#define EFR32MG24A410F1536IM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A410F1536IM48 EFR32MG24A410F1536IM48
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A410F1536IM48_Core EFR32MG24A410F1536IM48 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24A410F1536IM48_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24A410F1536IM48_Part EFR32MG24A410F1536IM48 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24A410F1536IM48)
+#define EFR32MG24A410F1536IM48 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24A410F1536IM48" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24A410F1536IM48 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */
+#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */
+#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */
+#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */
+#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24A410F1536IM48_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A410F1536IM48_Peripheral_TypeDefs EFR32MG24A410F1536IM48 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24A410F1536IM48_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A410F1536IM48_Peripheral_Base EFR32MG24A410F1536IM48 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24A410F1536IM48_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A410F1536IM48_Peripheral_Declaration EFR32MG24A410F1536IM48 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24A410F1536IM48_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A410F1536IM48_Peripheral_Parameters EFR32MG24A410F1536IM48 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24A410F1536IM48_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24A410F1536IM48 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a420f1536im40.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a420f1536im40.h
new file mode 100644
index 00000000..07829ab4
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a420f1536im40.h
@@ -0,0 +1,1411 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24A420F1536IM40
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24A420F1536IM40_H
+#define EFR32MG24A420F1536IM40_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A420F1536IM40 EFR32MG24A420F1536IM40
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A420F1536IM40_Core EFR32MG24A420F1536IM40 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24A420F1536IM40_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24A420F1536IM40_Part EFR32MG24A420F1536IM40 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24A420F1536IM40)
+#define EFR32MG24A420F1536IM40 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24A420F1536IM40" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24A420F1536IM40 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24A420F1536IM40_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A420F1536IM40_Peripheral_TypeDefs EFR32MG24A420F1536IM40 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24A420F1536IM40_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A420F1536IM40_Peripheral_Base EFR32MG24A420F1536IM40 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24A420F1536IM40_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A420F1536IM40_Peripheral_Declaration EFR32MG24A420F1536IM40 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24A420F1536IM40_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A420F1536IM40_Peripheral_Parameters EFR32MG24A420F1536IM40 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24A420F1536IM40_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24A420F1536IM40 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a420f1536im48.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a420f1536im48.h
new file mode 100644
index 00000000..8da5eddc
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a420f1536im48.h
@@ -0,0 +1,1417 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24A420F1536IM48
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24A420F1536IM48_H
+#define EFR32MG24A420F1536IM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A420F1536IM48 EFR32MG24A420F1536IM48
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A420F1536IM48_Core EFR32MG24A420F1536IM48 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24A420F1536IM48_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24A420F1536IM48_Part EFR32MG24A420F1536IM48 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24A420F1536IM48)
+#define EFR32MG24A420F1536IM48 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24A420F1536IM48" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24A420F1536IM48 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */
+#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */
+#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */
+#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */
+#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24A420F1536IM48_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A420F1536IM48_Peripheral_TypeDefs EFR32MG24A420F1536IM48 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24A420F1536IM48_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A420F1536IM48_Peripheral_Base EFR32MG24A420F1536IM48 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24A420F1536IM48_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A420F1536IM48_Peripheral_Declaration EFR32MG24A420F1536IM48 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24A420F1536IM48_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A420F1536IM48_Peripheral_Parameters EFR32MG24A420F1536IM48 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24A420F1536IM48_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24A420F1536IM48 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a610f1536im40.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a610f1536im40.h
new file mode 100644
index 00000000..9ab8d9fc
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a610f1536im40.h
@@ -0,0 +1,1413 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24A610F1536IM40
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24A610F1536IM40_H
+#define EFR32MG24A610F1536IM40_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A610F1536IM40 EFR32MG24A610F1536IM40
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A610F1536IM40_Core EFR32MG24A610F1536IM40 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24A610F1536IM40_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24A610F1536IM40_Part EFR32MG24A610F1536IM40 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24A610F1536IM40)
+#define EFR32MG24A610F1536IM40 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24A610F1536IM40" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24A610F1536IM40 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24A610F1536IM40_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A610F1536IM40_Peripheral_TypeDefs EFR32MG24A610F1536IM40 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24A610F1536IM40_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A610F1536IM40_Peripheral_Base EFR32MG24A610F1536IM40 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24A610F1536IM40_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A610F1536IM40_Peripheral_Declaration EFR32MG24A610F1536IM40 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24A610F1536IM40_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A610F1536IM40_Peripheral_Parameters EFR32MG24A610F1536IM40 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24A610F1536IM40_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24A610F1536IM40 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a620f1536im40.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a620f1536im40.h
new file mode 100644
index 00000000..206479b7
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24a620f1536im40.h
@@ -0,0 +1,1411 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24A620F1536IM40
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24A620F1536IM40_H
+#define EFR32MG24A620F1536IM40_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A620F1536IM40 EFR32MG24A620F1536IM40
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A620F1536IM40_Core EFR32MG24A620F1536IM40 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24A620F1536IM40_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24A620F1536IM40_Part EFR32MG24A620F1536IM40 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24A620F1536IM40)
+#define EFR32MG24A620F1536IM40 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24A620F1536IM40" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24A620F1536IM40 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24A620F1536IM40_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A620F1536IM40_Peripheral_TypeDefs EFR32MG24A620F1536IM40 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24A620F1536IM40_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A620F1536IM40_Peripheral_Base EFR32MG24A620F1536IM40 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24A620F1536IM40_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A620F1536IM40_Peripheral_Declaration EFR32MG24A620F1536IM40 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24A620F1536IM40_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24A620F1536IM40_Peripheral_Parameters EFR32MG24A620F1536IM40 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24A620F1536IM40_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24A620F1536IM40 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b010f1024im48.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b010f1024im48.h
new file mode 100644
index 00000000..703a4cca
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b010f1024im48.h
@@ -0,0 +1,1419 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24B010F1024IM48
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24B010F1024IM48_H
+#define EFR32MG24B010F1024IM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B010F1024IM48 EFR32MG24B010F1024IM48
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B010F1024IM48_Core EFR32MG24B010F1024IM48 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24B010F1024IM48_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24B010F1024IM48_Part EFR32MG24B010F1024IM48 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24B010F1024IM48)
+#define EFR32MG24B010F1024IM48 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24B010F1024IM48" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24B010F1024IM48 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */
+#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */
+#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */
+#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */
+#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24B010F1024IM48_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B010F1024IM48_Peripheral_TypeDefs EFR32MG24B010F1024IM48 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24B010F1024IM48_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B010F1024IM48_Peripheral_Base EFR32MG24B010F1024IM48 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24B010F1024IM48_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B010F1024IM48_Peripheral_Declaration EFR32MG24B010F1024IM48 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24B010F1024IM48_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B010F1024IM48_Peripheral_Parameters EFR32MG24B010F1024IM48 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24B010F1024IM48_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24B010F1024IM48 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b010f1536im40.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b010f1536im40.h
new file mode 100644
index 00000000..084f34eb
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b010f1536im40.h
@@ -0,0 +1,1413 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24B010F1536IM40
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24B010F1536IM40_H
+#define EFR32MG24B010F1536IM40_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B010F1536IM40 EFR32MG24B010F1536IM40
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B010F1536IM40_Core EFR32MG24B010F1536IM40 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24B010F1536IM40_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24B010F1536IM40_Part EFR32MG24B010F1536IM40 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24B010F1536IM40)
+#define EFR32MG24B010F1536IM40 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24B010F1536IM40" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24B010F1536IM40 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24B010F1536IM40_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B010F1536IM40_Peripheral_TypeDefs EFR32MG24B010F1536IM40 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24B010F1536IM40_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B010F1536IM40_Peripheral_Base EFR32MG24B010F1536IM40 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24B010F1536IM40_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B010F1536IM40_Peripheral_Declaration EFR32MG24B010F1536IM40 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24B010F1536IM40_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B010F1536IM40_Peripheral_Parameters EFR32MG24B010F1536IM40 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24B010F1536IM40_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24B010F1536IM40 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b010f1536im48.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b010f1536im48.h
new file mode 100644
index 00000000..50338c9b
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b010f1536im48.h
@@ -0,0 +1,1419 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24B010F1536IM48
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24B010F1536IM48_H
+#define EFR32MG24B010F1536IM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B010F1536IM48 EFR32MG24B010F1536IM48
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B010F1536IM48_Core EFR32MG24B010F1536IM48 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24B010F1536IM48_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24B010F1536IM48_Part EFR32MG24B010F1536IM48 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24B010F1536IM48)
+#define EFR32MG24B010F1536IM48 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24B010F1536IM48" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24B010F1536IM48 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */
+#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */
+#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */
+#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */
+#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24B010F1536IM48_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B010F1536IM48_Peripheral_TypeDefs EFR32MG24B010F1536IM48 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24B010F1536IM48_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B010F1536IM48_Peripheral_Base EFR32MG24B010F1536IM48 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24B010F1536IM48_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B010F1536IM48_Peripheral_Declaration EFR32MG24B010F1536IM48 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24B010F1536IM48_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B010F1536IM48_Peripheral_Parameters EFR32MG24B010F1536IM48 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24B010F1536IM48_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24B010F1536IM48 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b020f1024im48.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b020f1024im48.h
new file mode 100644
index 00000000..d531fc04
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b020f1024im48.h
@@ -0,0 +1,1417 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24B020F1024IM48
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24B020F1024IM48_H
+#define EFR32MG24B020F1024IM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B020F1024IM48 EFR32MG24B020F1024IM48
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B020F1024IM48_Core EFR32MG24B020F1024IM48 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24B020F1024IM48_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24B020F1024IM48_Part EFR32MG24B020F1024IM48 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24B020F1024IM48)
+#define EFR32MG24B020F1024IM48 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24B020F1024IM48" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24B020F1024IM48 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */
+#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */
+#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */
+#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */
+#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24B020F1024IM48_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B020F1024IM48_Peripheral_TypeDefs EFR32MG24B020F1024IM48 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24B020F1024IM48_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B020F1024IM48_Peripheral_Base EFR32MG24B020F1024IM48 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24B020F1024IM48_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B020F1024IM48_Peripheral_Declaration EFR32MG24B020F1024IM48 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24B020F1024IM48_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B020F1024IM48_Peripheral_Parameters EFR32MG24B020F1024IM48 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24B020F1024IM48_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24B020F1024IM48 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b020f1536im40.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b020f1536im40.h
new file mode 100644
index 00000000..ba0056f3
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b020f1536im40.h
@@ -0,0 +1,1411 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24B020F1536IM40
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24B020F1536IM40_H
+#define EFR32MG24B020F1536IM40_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B020F1536IM40 EFR32MG24B020F1536IM40
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B020F1536IM40_Core EFR32MG24B020F1536IM40 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24B020F1536IM40_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24B020F1536IM40_Part EFR32MG24B020F1536IM40 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24B020F1536IM40)
+#define EFR32MG24B020F1536IM40 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24B020F1536IM40" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24B020F1536IM40 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24B020F1536IM40_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B020F1536IM40_Peripheral_TypeDefs EFR32MG24B020F1536IM40 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24B020F1536IM40_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B020F1536IM40_Peripheral_Base EFR32MG24B020F1536IM40 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24B020F1536IM40_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B020F1536IM40_Peripheral_Declaration EFR32MG24B020F1536IM40 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24B020F1536IM40_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B020F1536IM40_Peripheral_Parameters EFR32MG24B020F1536IM40 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24B020F1536IM40_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24B020F1536IM40 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b020f1536im48.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b020f1536im48.h
new file mode 100644
index 00000000..1c1077cd
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b020f1536im48.h
@@ -0,0 +1,1417 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24B020F1536IM48
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24B020F1536IM48_H
+#define EFR32MG24B020F1536IM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B020F1536IM48 EFR32MG24B020F1536IM48
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B020F1536IM48_Core EFR32MG24B020F1536IM48 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24B020F1536IM48_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24B020F1536IM48_Part EFR32MG24B020F1536IM48 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24B020F1536IM48)
+#define EFR32MG24B020F1536IM48 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24B020F1536IM48" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24B020F1536IM48 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */
+#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */
+#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */
+#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */
+#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24B020F1536IM48_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B020F1536IM48_Peripheral_TypeDefs EFR32MG24B020F1536IM48 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24B020F1536IM48_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B020F1536IM48_Peripheral_Base EFR32MG24B020F1536IM48 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24B020F1536IM48_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B020F1536IM48_Peripheral_Declaration EFR32MG24B020F1536IM48 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24B020F1536IM48_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B020F1536IM48_Peripheral_Parameters EFR32MG24B020F1536IM48 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24B020F1536IM48_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24B020F1536IM48 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b110f1536gm48.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b110f1536gm48.h
new file mode 100644
index 00000000..4ab03c39
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b110f1536gm48.h
@@ -0,0 +1,1415 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24B110F1536GM48
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24B110F1536GM48_H
+#define EFR32MG24B110F1536GM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B110F1536GM48 EFR32MG24B110F1536GM48
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B110F1536GM48_Core EFR32MG24B110F1536GM48 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24B110F1536GM48_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24B110F1536GM48_Part EFR32MG24B110F1536GM48 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24B110F1536GM48)
+#define EFR32MG24B110F1536GM48 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24B110F1536GM48" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24B110F1536GM48 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 8U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x00FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 4U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x000FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */
+#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */
+#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24B110F1536GM48_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B110F1536GM48_Peripheral_TypeDefs EFR32MG24B110F1536GM48 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24B110F1536GM48_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B110F1536GM48_Peripheral_Base EFR32MG24B110F1536GM48 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24B110F1536GM48_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B110F1536GM48_Peripheral_Declaration EFR32MG24B110F1536GM48 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24B110F1536GM48_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B110F1536GM48_Peripheral_Parameters EFR32MG24B110F1536GM48 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24B110F1536GM48_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24B110F1536GM48 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b110f1536im48.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b110f1536im48.h
new file mode 100644
index 00000000..f1399094
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b110f1536im48.h
@@ -0,0 +1,1415 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24B110F1536IM48
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24B110F1536IM48_H
+#define EFR32MG24B110F1536IM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B110F1536IM48 EFR32MG24B110F1536IM48
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B110F1536IM48_Core EFR32MG24B110F1536IM48 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24B110F1536IM48_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24B110F1536IM48_Part EFR32MG24B110F1536IM48 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24B110F1536IM48)
+#define EFR32MG24B110F1536IM48 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24B110F1536IM48" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24B110F1536IM48 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 8U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x00FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 4U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x000FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */
+#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */
+#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24B110F1536IM48_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B110F1536IM48_Peripheral_TypeDefs EFR32MG24B110F1536IM48 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24B110F1536IM48_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B110F1536IM48_Peripheral_Base EFR32MG24B110F1536IM48 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24B110F1536IM48_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B110F1536IM48_Peripheral_Declaration EFR32MG24B110F1536IM48 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24B110F1536IM48_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B110F1536IM48_Peripheral_Parameters EFR32MG24B110F1536IM48 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24B110F1536IM48_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24B110F1536IM48 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b120f1536im48.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b120f1536im48.h
new file mode 100644
index 00000000..d9a4e0c9
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b120f1536im48.h
@@ -0,0 +1,1413 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24B120F1536IM48
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24B120F1536IM48_H
+#define EFR32MG24B120F1536IM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B120F1536IM48 EFR32MG24B120F1536IM48
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B120F1536IM48_Core EFR32MG24B120F1536IM48 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24B120F1536IM48_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24B120F1536IM48_Part EFR32MG24B120F1536IM48 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24B120F1536IM48)
+#define EFR32MG24B120F1536IM48 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24B120F1536IM48" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24B120F1536IM48 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 8U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x00FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 4U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x000FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */
+#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */
+#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24B120F1536IM48_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B120F1536IM48_Peripheral_TypeDefs EFR32MG24B120F1536IM48 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24B120F1536IM48_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B120F1536IM48_Peripheral_Base EFR32MG24B120F1536IM48 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24B120F1536IM48_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B120F1536IM48_Peripheral_Declaration EFR32MG24B120F1536IM48 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24B120F1536IM48_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B120F1536IM48_Peripheral_Parameters EFR32MG24B120F1536IM48 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24B120F1536IM48_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24B120F1536IM48 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b210f1536im48.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b210f1536im48.h
new file mode 100644
index 00000000..8ce1cff3
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b210f1536im48.h
@@ -0,0 +1,1428 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24B210F1536IM48
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24B210F1536IM48_H
+#define EFR32MG24B210F1536IM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B210F1536IM48 EFR32MG24B210F1536IM48
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ MVP_IRQn = 15, /*!< 15 EFR32 MVP Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B210F1536IM48_Core EFR32MG24B210F1536IM48 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24B210F1536IM48_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24B210F1536IM48_Part EFR32MG24B210F1536IM48 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24B210F1536IM48)
+#define EFR32MG24B210F1536IM48 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24B210F1536IM48" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24B210F1536IM48 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */
+#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */
+#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */
+#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */
+#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define MVP_PRESENT /** MVP is available in this part */
+#define MVP_COUNT 1 /** 1 MVPs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24B210F1536IM48_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B210F1536IM48_Peripheral_TypeDefs EFR32MG24B210F1536IM48 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_mvp.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24B210F1536IM48_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B210F1536IM48_Peripheral_Base EFR32MG24B210F1536IM48 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define MVP_BASE (0x4D000000UL) /* MVP base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define MVP_NS_BASE (0x5D000000UL) /* MVP_NS base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24B210F1536IM48_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B210F1536IM48_Peripheral_Declaration EFR32MG24B210F1536IM48 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define MVP_S ((MVP_TypeDef *) MVP_BASE) /**< MVP_S base pointer */
+#define MVP ((MVP_TypeDef *) MVP_BASE) /**< MVP_S base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define MVP_NS ((MVP_TypeDef *) MVP_NS_BASE) /**< MVP_NS base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24B210F1536IM48_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B210F1536IM48_Peripheral_Parameters EFR32MG24B210F1536IM48 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24B210F1536IM48_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24B210F1536IM48 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b220f1536im48.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b220f1536im48.h
new file mode 100644
index 00000000..c4c1cacd
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b220f1536im48.h
@@ -0,0 +1,1426 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24B220F1536IM48
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24B220F1536IM48_H
+#define EFR32MG24B220F1536IM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B220F1536IM48 EFR32MG24B220F1536IM48
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ MVP_IRQn = 15, /*!< 15 EFR32 MVP Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B220F1536IM48_Core EFR32MG24B220F1536IM48 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24B220F1536IM48_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24B220F1536IM48_Part EFR32MG24B220F1536IM48 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24B220F1536IM48)
+#define EFR32MG24B220F1536IM48 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24B220F1536IM48" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24B220F1536IM48 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */
+#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */
+#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */
+#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */
+#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define MVP_PRESENT /** MVP is available in this part */
+#define MVP_COUNT 1 /** 1 MVPs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24B220F1536IM48_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B220F1536IM48_Peripheral_TypeDefs EFR32MG24B220F1536IM48 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_mvp.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24B220F1536IM48_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B220F1536IM48_Peripheral_Base EFR32MG24B220F1536IM48 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define MVP_BASE (0x4D000000UL) /* MVP base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define MVP_NS_BASE (0x5D000000UL) /* MVP_NS base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24B220F1536IM48_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B220F1536IM48_Peripheral_Declaration EFR32MG24B220F1536IM48 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define MVP_S ((MVP_TypeDef *) MVP_BASE) /**< MVP_S base pointer */
+#define MVP ((MVP_TypeDef *) MVP_BASE) /**< MVP_S base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define MVP_NS ((MVP_TypeDef *) MVP_NS_BASE) /**< MVP_NS base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24B220F1536IM48_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B220F1536IM48_Peripheral_Parameters EFR32MG24B220F1536IM48 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24B220F1536IM48_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24B220F1536IM48 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b310f1536im48.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b310f1536im48.h
new file mode 100644
index 00000000..9b3bf206
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b310f1536im48.h
@@ -0,0 +1,1424 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24B310F1536IM48
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24B310F1536IM48_H
+#define EFR32MG24B310F1536IM48_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B310F1536IM48 EFR32MG24B310F1536IM48
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ MVP_IRQn = 15, /*!< 15 EFR32 MVP Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B310F1536IM48_Core EFR32MG24B310F1536IM48 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24B310F1536IM48_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24B310F1536IM48_Part EFR32MG24B310F1536IM48 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24B310F1536IM48)
+#define EFR32MG24B310F1536IM48 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24B310F1536IM48" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24B310F1536IM48 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 8U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x00FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 4U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x000FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */
+#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */
+#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define MVP_PRESENT /** MVP is available in this part */
+#define MVP_COUNT 1 /** 1 MVPs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24B310F1536IM48_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B310F1536IM48_Peripheral_TypeDefs EFR32MG24B310F1536IM48 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_mvp.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24B310F1536IM48_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B310F1536IM48_Peripheral_Base EFR32MG24B310F1536IM48 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define MVP_BASE (0x4D000000UL) /* MVP base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define MVP_NS_BASE (0x5D000000UL) /* MVP_NS base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24B310F1536IM48_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B310F1536IM48_Peripheral_Declaration EFR32MG24B310F1536IM48 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define MVP_S ((MVP_TypeDef *) MVP_BASE) /**< MVP_S base pointer */
+#define MVP ((MVP_TypeDef *) MVP_BASE) /**< MVP_S base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define MVP_NS ((MVP_TypeDef *) MVP_NS_BASE) /**< MVP_NS base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24B310F1536IM48_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B310F1536IM48_Peripheral_Parameters EFR32MG24B310F1536IM48 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24B310F1536IM48_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24B310F1536IM48 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b610f1536im40.h b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b610f1536im40.h
new file mode 100644
index 00000000..c41b7c9f
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/efr32mg24b610f1536im40.h
@@ -0,0 +1,1413 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer Header File
+ * for EFR32MG24B610F1536IM40
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+#ifndef EFR32MG24B610F1536IM40_H
+#define EFR32MG24B610F1536IM40_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ *****************************************************************************/
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B610F1536IM40 EFR32MG24B610F1536IM40
+ * @{
+ *****************************************************************************/
+
+/** Interrupt Number Definition */
+typedef enum IRQn{
+ /****** Cortex-M Processor Exceptions Numbers ******************************************/
+ NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */
+
+ /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/
+
+ SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */
+ SMU_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_PRIVILEGED Interrupt */
+ SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */
+ EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */
+ TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */
+ TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */
+ TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */
+ TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */
+ TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */
+ USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */
+ USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */
+ EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */
+ EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */
+ EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */
+ EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */
+ ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */
+ BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */
+ LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */
+ SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */
+ MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */
+ LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */
+ LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */
+ LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */
+ ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */
+ GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */
+ GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */
+ I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */
+ I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */
+ EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */
+ AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */
+ BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */
+ FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */
+ FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */
+ MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */
+ PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */
+ RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */
+ RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */
+ HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */
+ SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */
+ ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */
+ ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */
+ WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */
+ WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */
+ HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */
+ HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */
+ HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */
+ CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */
+ AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */
+ IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */
+ MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */
+ DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */
+ EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */
+ DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */
+ PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */
+ SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */
+ SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */
+ SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */
+ SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */
+ KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */
+ KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */
+ M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */
+ M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */
+ FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */
+ SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */
+ SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */
+ SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */
+ SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */
+ SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */
+ KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */
+ RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */
+ RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */
+ VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */
+ VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */
+ AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */
+ AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */
+} IRQn_Type;
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B610F1536IM40_Core EFR32MG24B610F1536IM40 Core
+ * @{
+ * @brief Processor and Core Peripheral Section
+ *****************************************************************************/
+
+#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */
+#define __DSP_PRESENT 1U /**< Presence of DSP */
+#define __FPU_PRESENT 1U /**< Presence of FPU */
+#define __MPU_PRESENT 1U /**< Presence of MPU */
+#define __SAUREGION_PRESENT 1U /**< Presence of FPU */
+#define __TZ_PRESENT 1U /**< Presence of TrustZone */
+#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */
+#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */
+#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */
+
+/** @} End of group EFR32MG24B610F1536IM40_Core */
+
+/**************************************************************************//**
+* @defgroup EFR32MG24B610F1536IM40_Part EFR32MG24B610F1536IM40 Part
+* @{
+******************************************************************************/
+
+/** Part number */
+
+/* If part number is not defined as compiler option, define it */
+#if !defined(EFR32MG24B610F1536IM40)
+#define EFR32MG24B610F1536IM40 1 /**< FULL Part */
+#endif
+
+/** Configure part number */
+#define PART_NUMBER "EFR32MG24B610F1536IM40" /**< Part Number */
+
+/** Family / Line / Series / Config */
+#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */
+#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */
+#define _EFR_DEVICE 1 /** Product Line Identifier */
+#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */
+#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */
+#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */
+#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */
+#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */
+#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */
+#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */
+#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */
+#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */
+#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */
+#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */
+#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */
+#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */
+#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */
+
+/** Memory Base addresses and limits */
+#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */
+#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */
+#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */
+#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */
+#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */
+#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */
+#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */
+#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */
+#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */
+#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */
+#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */
+#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */
+#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */
+#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */
+#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */
+#define USERDATA_BITS (0xBUL) /** USERDATA used bits */
+#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */
+#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */
+#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */
+#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */
+#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */
+#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */
+#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */
+#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */
+#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */
+#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */
+#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */
+#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */
+#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */
+#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */
+#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */
+#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */
+#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */
+#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */
+#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */
+#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */
+#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */
+#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */
+#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */
+#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */
+#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */
+#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */
+#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */
+#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */
+#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */
+#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */
+#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */
+#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */
+#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */
+#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */
+#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */
+#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */
+
+/** Flash and SRAM limits for EFR32MG24B610F1536IM40 */
+#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */
+#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */
+#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */
+#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
+#define SRAM_SIZE (0x00028000UL) /**< Available SRAM Memory */
+#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */
+#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */
+
+/* GPIO Avalibility Info */
+#define GPIO_PA_INDEX 0U /**< Index of port PA */
+#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */
+#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */
+#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */
+#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */
+#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */
+#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */
+#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */
+#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */
+#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */
+#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */
+#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */
+#define GPIO_PB_INDEX 1U /**< Index of port PB */
+#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */
+#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */
+#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */
+#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */
+#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */
+#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */
+#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */
+#define GPIO_PC_INDEX 2U /**< Index of port PC */
+#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */
+#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */
+#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */
+#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */
+#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */
+#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */
+#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */
+#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */
+#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */
+#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */
+#define GPIO_PD_INDEX 3U /**< Index of port PD */
+#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */
+#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */
+#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */
+#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */
+#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */
+#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */
+
+/* Fixed Resource Locations */
+#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/
+#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/
+#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/
+#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/
+#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/
+#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/
+#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/
+#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/
+#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/
+#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/
+#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/
+#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/
+#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/
+#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/
+#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/
+#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/
+#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/
+#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/
+#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/
+#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/
+#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/
+#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/
+#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/
+#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/
+#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/
+#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/
+#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/
+#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/
+#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/
+#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/
+#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/
+#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/
+#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/
+#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/
+#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/
+#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/
+#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/
+#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/
+#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/
+#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/
+#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/
+#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/
+#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/
+#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/
+#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/
+#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/
+#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/
+#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/
+#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/
+#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/
+#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/
+#define MSC_TSW_FLASH_TM0_PORT GPIO_PD_INDEX /**< Port of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM0_PIN 0U /**< Pin of TSW_FLASH_TM0.*/
+#define MSC_TSW_FLASH_TM1_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM1_PIN 3U /**< Pin of TSW_FLASH_TM1.*/
+#define MSC_TSW_FLASH_TM2_PORT GPIO_PA_INDEX /**< Port of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM2_PIN 0U /**< Pin of TSW_FLASH_TM2.*/
+#define MSC_TSW_FLASH_TM3_PORT GPIO_PB_INDEX /**< Port of TSW_FLASH_TM3.*/
+#define MSC_TSW_FLASH_TM3_PIN 0U /**< Pin of TSW_FLASH_TM3.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/
+#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/
+
+/* Part number capabilities */
+#define ACMP_PRESENT /** ACMP is available in this part */
+#define ACMP_COUNT 2 /** 2 ACMPs available */
+#define AGC_PRESENT /** AGC is available in this part */
+#define AGC_COUNT 1 /** 1 AGCs available */
+#define AMUXCP_PRESENT /** AMUXCP is available in this part */
+#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */
+#define BUFC_PRESENT /** BUFC is available in this part */
+#define BUFC_COUNT 1 /** 1 BUFCs available */
+#define BURAM_PRESENT /** BURAM is available in this part */
+#define BURAM_COUNT 1 /** 1 BURAMs available */
+#define BURTC_PRESENT /** BURTC is available in this part */
+#define BURTC_COUNT 1 /** 1 BURTCs available */
+#define CMU_PRESENT /** CMU is available in this part */
+#define CMU_COUNT 1 /** 1 CMUs available */
+#define DCDC_PRESENT /** DCDC is available in this part */
+#define DCDC_COUNT 1 /** 1 DCDCs available */
+#define DMEM_PRESENT /** DMEM is available in this part */
+#define DMEM_COUNT 1 /** 1 DMEMs available */
+#define DPLL_PRESENT /** DPLL is available in this part */
+#define DPLL_COUNT 1 /** 1 DPLLs available */
+#define ECAIFADC_PRESENT /** ECAIFADC is available in this part */
+#define ECAIFADC_COUNT 1 /** 1 ECAIFADCs available */
+#define EMU_PRESENT /** EMU is available in this part */
+#define EMU_COUNT 1 /** 1 EMUs available */
+#define EUSART_PRESENT /** EUSART is available in this part */
+#define EUSART_COUNT 2 /** 2 EUSARTs available */
+#define FRC_PRESENT /** FRC is available in this part */
+#define FRC_COUNT 1 /** 1 FRCs available */
+#define FSRCO_PRESENT /** FSRCO is available in this part */
+#define FSRCO_COUNT 1 /** 1 FSRCOs available */
+#define GPCRC_PRESENT /** GPCRC is available in this part */
+#define GPCRC_COUNT 1 /** 1 GPCRCs available */
+#define GPIO_PRESENT /** GPIO is available in this part */
+#define GPIO_COUNT 1 /** 1 GPIOs available */
+#define HFRCO_PRESENT /** HFRCO is available in this part */
+#define HFRCO_COUNT 1 /** 1 HFRCOs available */
+#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */
+#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */
+#define HFXO_PRESENT /** HFXO is available in this part */
+#define HFXO_COUNT 1 /** 1 HFXOs available */
+#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */
+#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */
+#define I2C_PRESENT /** I2C is available in this part */
+#define I2C_COUNT 2 /** 2 I2Cs available */
+#define IADC_PRESENT /** IADC is available in this part */
+#define IADC_COUNT 1 /** 1 IADCs available */
+#define ICACHE_PRESENT /** ICACHE is available in this part */
+#define ICACHE_COUNT 1 /** 1 ICACHEs available */
+#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */
+#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */
+#define LDMA_PRESENT /** LDMA is available in this part */
+#define LDMA_COUNT 1 /** 1 LDMAs available */
+#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */
+#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */
+#define LETIMER_PRESENT /** LETIMER is available in this part */
+#define LETIMER_COUNT 1 /** 1 LETIMERs available */
+#define LFRCO_PRESENT /** LFRCO is available in this part */
+#define LFRCO_COUNT 1 /** 1 LFRCOs available */
+#define LFXO_PRESENT /** LFXO is available in this part */
+#define LFXO_COUNT 1 /** 1 LFXOs available */
+#define MODEM_PRESENT /** MODEM is available in this part */
+#define MODEM_COUNT 1 /** 1 MODEMs available */
+#define MSC_PRESENT /** MSC is available in this part */
+#define MSC_COUNT 1 /** 1 MSCs available */
+#define PCNT_PRESENT /** PCNT is available in this part */
+#define PCNT_COUNT 1 /** 1 PCNTs available */
+#define PROTIMER_PRESENT /** PROTIMER is available in this part */
+#define PROTIMER_COUNT 1 /** 1 PROTIMERs available */
+#define PRS_PRESENT /** PRS is available in this part */
+#define PRS_COUNT 1 /** 1 PRSs available */
+#define RAC_PRESENT /** RAC is available in this part */
+#define RAC_COUNT 1 /** 1 RACs available */
+#define RADIOAES_PRESENT /** RADIOAES is available in this part */
+#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */
+#define RFCRC_PRESENT /** RFCRC is available in this part */
+#define RFCRC_COUNT 1 /** 1 RFCRCs available */
+#define RFECA_PRESENT /** RFECA is available in this part */
+#define RFECA_COUNT 2 /** 2 RFECAs available */
+#define RFMAILBOX_PRESENT /** RFMAILBOX is available in this part */
+#define RFMAILBOX_COUNT 1 /** 1 RFMAILBOXs available */
+#define RFSCRATCHPAD_PRESENT /** RFSCRATCHPAD is available in this part */
+#define RFSCRATCHPAD_COUNT 1 /** 1 RFSCRATCHPADs available */
+#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */
+#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */
+#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */
+#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */
+#define SMU_PRESENT /** SMU is available in this part */
+#define SMU_COUNT 1 /** 1 SMUs available */
+#define SYNTH_PRESENT /** SYNTH is available in this part */
+#define SYNTH_COUNT 1 /** 1 SYNTHs available */
+#define SYSCFG_PRESENT /** SYSCFG is available in this part */
+#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */
+#define SYSRTC_PRESENT /** SYSRTC is available in this part */
+#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */
+#define TIMER_PRESENT /** TIMER is available in this part */
+#define TIMER_COUNT 5 /** 5 TIMERs available */
+#define ULFRCO_PRESENT /** ULFRCO is available in this part */
+#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */
+#define USART_PRESENT /** USART is available in this part */
+#define USART_COUNT 1 /** 1 USARTs available */
+#define VDAC_PRESENT /** VDAC is available in this part */
+#define VDAC_COUNT 2 /** 2 VDACs available */
+#define WDOG_PRESENT /** WDOG is available in this part */
+#define WDOG_COUNT 2 /** 2 WDOGs available */
+#define DEVINFO_PRESENT /** DEVINFO is available in this part */
+#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */
+
+/* Include standard ARM headers for the core */
+#include "core_cm33.h" /* Core Header File */
+#include "system_efr32mg24.h" /* System Header File */
+
+/** @} End of group EFR32MG24B610F1536IM40_Part */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B610F1536IM40_Peripheral_TypeDefs EFR32MG24B610F1536IM40 Peripheral TypeDefs
+ * @{
+ * @brief Device Specific Peripheral Register Structures
+ *****************************************************************************/
+#include "efr32mg24_scratchpad.h"
+#include "efr32mg24_emu.h"
+#include "efr32mg24_cmu.h"
+#include "efr32mg24_hfrco.h"
+#include "efr32mg24_fsrco.h"
+#include "efr32mg24_dpll.h"
+#include "efr32mg24_lfxo.h"
+#include "efr32mg24_lfrco.h"
+#include "efr32mg24_ulfrco.h"
+#include "efr32mg24_msc.h"
+#include "efr32mg24_icache.h"
+#include "efr32mg24_prs.h"
+#include "efr32mg24_gpio.h"
+#include "efr32mg24_ldma.h"
+#include "efr32mg24_ldmaxbar.h"
+#include "efr32mg24_timer.h"
+#include "efr32mg24_usart.h"
+#include "efr32mg24_burtc.h"
+#include "efr32mg24_i2c.h"
+#include "efr32mg24_syscfg.h"
+#include "efr32mg24_buram.h"
+#include "efr32mg24_gpcrc.h"
+#include "efr32mg24_dcdc.h"
+#include "efr32mg24_mailbox.h"
+#include "efr32mg24_eusart.h"
+#include "efr32mg24_sysrtc.h"
+#include "efr32mg24_keyscan.h"
+#include "efr32mg24_mpahbram.h"
+#include "efr32mg24_aes.h"
+#include "efr32mg24_smu.h"
+#include "efr32mg24_letimer.h"
+#include "efr32mg24_iadc.h"
+#include "efr32mg24_acmp.h"
+#include "efr32mg24_amuxcp.h"
+#include "efr32mg24_vdac.h"
+#include "efr32mg24_pcnt.h"
+#include "efr32mg24_hfxo.h"
+#include "efr32mg24_wdog.h"
+#include "efr32mg24_semailbox.h"
+#include "efr32mg24_frc.h"
+#include "efr32mg24_agc.h"
+#include "efr32mg24_rfcrc.h"
+#include "efr32mg24_modem.h"
+#include "efr32mg24_synth.h"
+#include "efr32mg24_protimer.h"
+#include "efr32mg24_rac.h"
+#include "efr32mg24_eca.h"
+#include "efr32mg24_ecaifadc.h"
+#include "efr32mg24_bufc.h"
+#include "efr32mg24_devinfo.h"
+
+/* Custom headers for LDMAXBAR and PRS mappings */
+#include "efr32mg24_prs_signals.h"
+#include "efr32mg24_dma_descriptor.h"
+#include "efr32mg24_ldmaxbar_defines.h"
+
+/** @} End of group EFR32MG24B610F1536IM40_Peripheral_TypeDefs */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B610F1536IM40_Peripheral_Base EFR32MG24B610F1536IM40 Peripheral Memory Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_BASE (0x40000000UL) /* SCRATCHPAD base address */
+#define EMU_BASE (0x40004000UL) /* EMU base address */
+#define CMU_BASE (0x40008000UL) /* CMU base address */
+#define HFRCO0_BASE (0x40010000UL) /* HFRCO0 base address */
+#define FSRCO_BASE (0x40018000UL) /* FSRCO base address */
+#define DPLL0_BASE (0x4001C000UL) /* DPLL0 base address */
+#define LFXO_BASE (0x40020000UL) /* LFXO base address */
+#define LFRCO_BASE (0x40024000UL) /* LFRCO base address */
+#define ULFRCO_BASE (0x40028000UL) /* ULFRCO base address */
+#define MSC_BASE (0x40030000UL) /* MSC base address */
+#define ICACHE0_BASE (0x40034000UL) /* ICACHE0 base address */
+#define PRS_BASE (0x40038000UL) /* PRS base address */
+#define GPIO_BASE (0x4003C000UL) /* GPIO base address */
+#define LDMA_BASE (0x40040000UL) /* LDMA base address */
+#define LDMAXBAR_BASE (0x40044000UL) /* LDMAXBAR base address */
+#define TIMER0_BASE (0x40048000UL) /* TIMER0 base address */
+#define TIMER1_BASE (0x4004C000UL) /* TIMER1 base address */
+#define TIMER2_BASE (0x40050000UL) /* TIMER2 base address */
+#define TIMER3_BASE (0x40054000UL) /* TIMER3 base address */
+#define TIMER4_BASE (0x40058000UL) /* TIMER4 base address */
+#define USART0_BASE (0x4005C000UL) /* USART0 base address */
+#define BURTC_BASE (0x40064000UL) /* BURTC base address */
+#define I2C1_BASE (0x40068000UL) /* I2C1 base address */
+#define SYSCFG_CFGNS_BASE (0x40078000UL) /* SYSCFG_CFGNS base address */
+#define SYSCFG_BASE (0x4007C000UL) /* SYSCFG base address */
+#define BURAM_BASE (0x40080000UL) /* BURAM base address */
+#define GPCRC_BASE (0x40088000UL) /* GPCRC base address */
+#define DCDC_BASE (0x40094000UL) /* DCDC base address */
+#define HOSTMAILBOX_BASE (0x40098000UL) /* HOSTMAILBOX base address */
+#define EUSART1_BASE (0x400A0000UL) /* EUSART1 base address */
+#define SYSRTC0_BASE (0x400A8000UL) /* SYSRTC0 base address */
+#define KEYSCAN_BASE (0x400B0000UL) /* KEYSCAN base address */
+#define DMEM_BASE (0x400B4000UL) /* DMEM base address */
+#define RADIOAES_BASE (0x44000000UL) /* RADIOAES base address */
+#define SMU_BASE (0x44008000UL) /* SMU base address */
+#define SMU_CFGNS_BASE (0x4400C000UL) /* SMU_CFGNS base address */
+#define LETIMER0_BASE (0x49000000UL) /* LETIMER0 base address */
+#define IADC0_BASE (0x49004000UL) /* IADC0 base address */
+#define ACMP0_BASE (0x49008000UL) /* ACMP0 base address */
+#define ACMP1_BASE (0x4900C000UL) /* ACMP1 base address */
+#define AMUXCP0_BASE (0x49020000UL) /* AMUXCP0 base address */
+#define VDAC0_BASE (0x49024000UL) /* VDAC0 base address */
+#define VDAC1_BASE (0x49028000UL) /* VDAC1 base address */
+#define PCNT0_BASE (0x49030000UL) /* PCNT0 base address */
+#define HFRCOEM23_BASE (0x4A000000UL) /* HFRCOEM23 base address */
+#define HFXO0_BASE (0x4A004000UL) /* HFXO0 base address */
+#define I2C0_BASE (0x4B000000UL) /* I2C0 base address */
+#define WDOG0_BASE (0x4B004000UL) /* WDOG0 base address */
+#define WDOG1_BASE (0x4B008000UL) /* WDOG1 base address */
+#define EUSART0_BASE (0x4B010000UL) /* EUSART0 base address */
+#define SEMAILBOX_HOST_BASE (0x4C000000UL) /* SEMAILBOX_HOST base address */
+#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */
+#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */
+#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */
+#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */
+#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */
+#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */
+#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */
+#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */
+#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */
+#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */
+#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */
+#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */
+#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */
+#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */
+#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */
+#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */
+#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */
+#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */
+#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */
+#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */
+#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */
+#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */
+#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */
+#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */
+#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */
+#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */
+#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */
+#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */
+#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */
+#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */
+#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */
+#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */
+#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */
+#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */
+#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */
+#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */
+#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */
+#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */
+#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */
+#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */
+#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */
+#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */
+#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */
+#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */
+#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */
+#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */
+#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */
+#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */
+#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */
+#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */
+#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */
+#define FRC_BASE (0xA8004000UL) /* FRC base address */
+#define AGC_BASE (0xA800C000UL) /* AGC base address */
+#define RFCRC_BASE (0xA8010000UL) /* RFCRC base address */
+#define MODEM_BASE (0xA8014000UL) /* MODEM base address */
+#define SYNTH_BASE (0xA8018000UL) /* SYNTH base address */
+#define PROTIMER_BASE (0xA801C000UL) /* PROTIMER base address */
+#define RAC_BASE (0xA8020000UL) /* RAC base address */
+#define RFSCRATCHPAD_BASE (0xA8024000UL) /* RFSCRATCHPAD base address */
+#define RFMAILBOX_BASE (0xA802C000UL) /* RFMAILBOX base address */
+#define RFECA0_BASE (0xA8030000UL) /* RFECA0 base address */
+#define RFECA1_BASE (0xA8034000UL) /* RFECA1 base address */
+#define ECAIFADC_BASE (0xA8038000UL) /* ECAIFADC base address */
+#define BUFC_BASE (0xAA000000UL) /* BUFC base address */
+#define FRC_NS_BASE (0xB8004000UL) /* FRC_NS base address */
+#define AGC_NS_BASE (0xB800C000UL) /* AGC_NS base address */
+#define RFCRC_NS_BASE (0xB8010000UL) /* RFCRC_NS base address */
+#define MODEM_NS_BASE (0xB8014000UL) /* MODEM_NS base address */
+#define SYNTH_NS_BASE (0xB8018000UL) /* SYNTH_NS base address */
+#define PROTIMER_NS_BASE (0xB801C000UL) /* PROTIMER_NS base address */
+#define RAC_NS_BASE (0xB8020000UL) /* RAC_NS base address */
+#define RFSCRATCHPAD_NS_BASE (0xB8024000UL) /* RFSCRATCHPAD_NS base address */
+#define RFMAILBOX_NS_BASE (0xB802C000UL) /* RFMAILBOX_NS base address */
+#define RFECA0_NS_BASE (0xB8030000UL) /* RFECA0_NS base address */
+#define RFECA1_NS_BASE (0xB8034000UL) /* RFECA1_NS base address */
+#define ECAIFADC_NS_BASE (0xB8038000UL) /* ECAIFADC_NS base address */
+#define BUFC_NS_BASE (0xBA000000UL) /* BUFC_NS base address */
+#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */
+/** @} End of group EFR32MG24B610F1536IM40_Peripheral_Base */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B610F1536IM40_Peripheral_Declaration EFR32MG24B610F1536IM40 Peripheral Declarations Map
+ * @{
+ *****************************************************************************/
+
+#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD_S base pointer */
+#define EMU_S ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU_S base pointer */
+#define CMU_S ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU_S base pointer */
+#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0_S base pointer */
+#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO_S base pointer */
+#define DPLL0_S ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0_S base pointer */
+#define LFXO_S ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO_S base pointer */
+#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO_S base pointer */
+#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO_S base pointer */
+#define MSC_S ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC_S base pointer */
+#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0_S base pointer */
+#define PRS_S ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS_S base pointer */
+#define GPIO_S ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO_S base pointer */
+#define LDMA_S ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA_S base pointer */
+#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR_S base pointer */
+#define TIMER0_S ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0_S base pointer */
+#define TIMER1_S ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1_S base pointer */
+#define TIMER2_S ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2_S base pointer */
+#define TIMER3_S ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3_S base pointer */
+#define TIMER4_S ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4_S base pointer */
+#define USART0_S ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0_S base pointer */
+#define BURTC_S ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC_S base pointer */
+#define I2C1_S ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1_S base pointer */
+#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */
+#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG_S base pointer */
+#define BURAM_S ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM_S base pointer */
+#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC_S base pointer */
+#define DCDC_S ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC_S base pointer */
+#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX_S base pointer */
+#define EUSART1_S ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1_S base pointer */
+#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0_S base pointer */
+#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN_S base pointer */
+#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM_S base pointer */
+#define RADIOAES_S ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES_S base pointer */
+#define SMU_S ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU_S base pointer */
+#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */
+#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0_S base pointer */
+#define IADC0_S ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0_S base pointer */
+#define ACMP0_S ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0_S base pointer */
+#define ACMP1_S ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1_S base pointer */
+#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0_S base pointer */
+#define VDAC0_S ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0_S base pointer */
+#define VDAC1_S ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1_S base pointer */
+#define PCNT0_S ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0_S base pointer */
+#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23_S base pointer */
+#define HFXO0_S ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0_S base pointer */
+#define I2C0_S ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0_S base pointer */
+#define WDOG0_S ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0_S base pointer */
+#define WDOG1_S ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1_S base pointer */
+#define EUSART0_S ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0_S base pointer */
+#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */
+#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */
+#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */
+#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */
+#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */
+#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */
+#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */
+#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */
+#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */
+#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */
+#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */
+#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */
+#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */
+#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */
+#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */
+#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */
+#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */
+#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */
+#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */
+#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */
+#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */
+#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */
+#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */
+#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */
+#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */
+#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */
+#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */
+#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */
+#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */
+#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */
+#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */
+#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */
+#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */
+#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */
+#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */
+#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */
+#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */
+#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */
+#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */
+#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */
+#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */
+#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */
+#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */
+#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */
+#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */
+#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */
+#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */
+#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */
+#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */
+#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */
+#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */
+#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */
+#define FRC_S ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define FRC ((FRC_TypeDef *) FRC_BASE) /**< FRC_S base pointer */
+#define AGC_S ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define AGC ((AGC_TypeDef *) AGC_BASE) /**< AGC_S base pointer */
+#define RFCRC_S ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define RFCRC ((RFCRC_TypeDef *) RFCRC_BASE) /**< RFCRC_S base pointer */
+#define MODEM_S ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define MODEM ((MODEM_TypeDef *) MODEM_BASE) /**< MODEM_S base pointer */
+#define SYNTH_S ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define SYNTH ((SYNTH_TypeDef *) SYNTH_BASE) /**< SYNTH_S base pointer */
+#define PROTIMER_S ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define PROTIMER ((PROTIMER_TypeDef *) PROTIMER_BASE) /**< PROTIMER_S base pointer */
+#define RAC_S ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RAC ((RAC_TypeDef *) RAC_BASE) /**< RAC_S base pointer */
+#define RFSCRATCHPAD_S ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFSCRATCHPAD ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_BASE) /**< RFSCRATCHPAD_S base pointer */
+#define RFMAILBOX_S ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFMAILBOX ((MAILBOX_TypeDef *) RFMAILBOX_BASE) /**< RFMAILBOX_S base pointer */
+#define RFECA0_S ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA0 ((ECA_TypeDef *) RFECA0_BASE) /**< RFECA0_S base pointer */
+#define RFECA1_S ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define RFECA1 ((ECA_TypeDef *) RFECA1_BASE) /**< RFECA1_S base pointer */
+#define ECAIFADC_S ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define ECAIFADC ((ECAIFADC_TypeDef *) ECAIFADC_BASE) /**< ECAIFADC_S base pointer */
+#define BUFC_S ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC_S base pointer */
+#define FRC_NS ((FRC_TypeDef *) FRC_NS_BASE) /**< FRC_NS base pointer */
+#define AGC_NS ((AGC_TypeDef *) AGC_NS_BASE) /**< AGC_NS base pointer */
+#define RFCRC_NS ((RFCRC_TypeDef *) RFCRC_NS_BASE) /**< RFCRC_NS base pointer */
+#define MODEM_NS ((MODEM_TypeDef *) MODEM_NS_BASE) /**< MODEM_NS base pointer */
+#define SYNTH_NS ((SYNTH_TypeDef *) SYNTH_NS_BASE) /**< SYNTH_NS base pointer */
+#define PROTIMER_NS ((PROTIMER_TypeDef *) PROTIMER_NS_BASE) /**< PROTIMER_NS base pointer */
+#define RAC_NS ((RAC_TypeDef *) RAC_NS_BASE) /**< RAC_NS base pointer */
+#define RFSCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) RFSCRATCHPAD_NS_BASE) /**< RFSCRATCHPAD_NS base pointer */
+#define RFMAILBOX_NS ((MAILBOX_TypeDef *) RFMAILBOX_NS_BASE) /**< RFMAILBOX_NS base pointer */
+#define RFECA0_NS ((ECA_TypeDef *) RFECA0_NS_BASE) /**< RFECA0_NS base pointer */
+#define RFECA1_NS ((ECA_TypeDef *) RFECA1_NS_BASE) /**< RFECA1_NS base pointer */
+#define ECAIFADC_NS ((ECAIFADC_TypeDef *) ECAIFADC_NS_BASE) /**< ECAIFADC_NS base pointer */
+#define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
+/** @} End of group EFR32MG24B610F1536IM40_Peripheral_Declaration */
+
+/**************************************************************************//**
+ * @defgroup EFR32MG24B610F1536IM40_Peripheral_Parameters EFR32MG24B610F1536IM40 Peripheral Parameters
+ * @{
+ * @brief Device peripheral parameter values
+ *****************************************************************************/
+
+/* Common peripheral register block offsets. */
+#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */
+#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */
+#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */
+#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */
+#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */
+#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */
+#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */
+#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */
+#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */
+#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */
+#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */
+#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */
+#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */
+#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */
+#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */
+#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */
+#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */
+#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */
+#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */
+#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */
+#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */
+#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */
+#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */
+#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */
+#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */
+#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */
+#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */
+#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */
+#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */
+#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */
+#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */
+#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */
+#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */
+#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */
+#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */
+#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */
+#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */
+#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */
+#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */
+#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */
+#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */
+#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */
+#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */
+#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */
+#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */
+#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */
+#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */
+#define LFXO_CTUNE 0x1UL /**> CTUNE Present */
+#define MSC_CDA_PRESENT 0x0UL /**> */
+#define MSC_FDIO_WIDTH 0x40UL /**> None */
+#define MSC_FLASHADDRBITS 0x15UL /**> None */
+#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */
+#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */
+#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */
+#define MSC_INFOADDRBITS 0xEUL /**> None */
+#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */
+#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */
+#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */
+#define MSC_REDUNDANCY 0x2UL /**> None */
+#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */
+#define MSC_UD_PRESENT 0x1UL /**> */
+#define MSC_YADDRBITS 0x6UL /**> */
+#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */
+#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */
+#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */
+#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */
+#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */
+#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */
+#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */
+#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */
+#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */
+#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */
+#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */
+#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */
+#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */
+#define ICACHE0_SET_BITS 0x7UL /**> Set bits */
+#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */
+#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */
+#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */
+#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */
+#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */
+#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */
+#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */
+#define PRS_ASYNC_CH_NUM 0x10UL /**> None */
+#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */
+#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */
+#define PRS_SYNC_CH_NUM 0x4UL /**> None */
+#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */
+#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */
+#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */
+#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */
+#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */
+#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */
+#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */
+#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */
+#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */
+#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */
+#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */
+#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */
+#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */
+#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */
+#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */
+#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */
+#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */
+#define GPIO_PORT_A_WL 0x8UL /**> New Param */
+#define GPIO_PORT_A_WU 0x2UL /**> New Param */
+#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */
+#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */
+#define GPIO_PORT_B_WL 0x6UL /**> New Param */
+#define GPIO_PORT_B_WU 0x0UL /**> New Param */
+#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */
+#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */
+#define GPIO_PORT_C_WL 0x8UL /**> New Param */
+#define GPIO_PORT_C_WU 0x2UL /**> New Param */
+#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */
+#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */
+#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */
+#define GPIO_PORT_D_WL 0x6UL /**> New Param */
+#define GPIO_PORT_D_WU 0x0UL /**> New Param */
+#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */
+#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */
+#define LDMA_CH_BITS 0x5UL /**> New Param */
+#define LDMA_CH_NUM 0x8UL /**> New Param */
+#define LDMA_FIFO_BITS 0x5UL /**> New Param */
+#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */
+#define LDMAXBAR_CH_BITS 0x5UL /**> None */
+#define LDMAXBAR_CH_NUM 0x8UL /**> None */
+#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */
+#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */
+#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER0_NO_DTI 0x0UL /**> */
+#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */
+#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER1_NO_DTI 0x0UL /**> */
+#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER2_NO_DTI 0x0UL /**> */
+#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER3_NO_DTI 0x0UL /**> */
+#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */
+#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */
+#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */
+#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */
+#define TIMER4_NO_DTI 0x0UL /**> */
+#define USART0_AUTOTX_REG 0x1UL /**> None */
+#define USART0_AUTOTX_REG_B 0x0UL /**> None */
+#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */
+#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */
+#define USART0_CLK_PRS 0x1UL /**> None */
+#define USART0_CLK_PRS_B 0x0UL /**> New Param */
+#define USART0_FLOW_CONTROL 0x1UL /**> None */
+#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */
+#define USART0_I2S 0x1UL /**> None */
+#define USART0_I2S_B 0x0UL /**> New Param */
+#define USART0_IRDA_AVAILABLE 0x1UL /**> None */
+#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_MVDIS_FUNC 0x1UL /**> None */
+#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */
+#define USART0_RX_PRS 0x1UL /**> None */
+#define USART0_RX_PRS_B 0x0UL /**> New Param */
+#define USART0_SC_AVAILABLE 0x1UL /**> None */
+#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_AVAILABLE 0x1UL /**> None */
+#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */
+#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */
+#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */
+#define USART0_TIMER 0x1UL /**> New Param */
+#define USART0_TIMER_B 0x0UL /**> New Param */
+#define BURTC_CNTWIDTH 0x20UL /**> None */
+#define BURTC_PRECNT_WIDTH 0xFUL /**> */
+#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */
+#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */
+#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */
+#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */
+#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */
+#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */
+#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */
+#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */
+#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */
+#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */
+#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */
+#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */
+#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */
+#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */
+#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */
+#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */
+#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */
+#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */
+#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */
+#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */
+#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */
+#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */
+#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */
+#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */
+#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */
+#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */
+#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */
+#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */
+#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */
+#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */
+#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */
+#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */
+#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */
+#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */
+#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */
+#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */
+#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */
+#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */
+#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */
+#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */
+#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */
+#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */
+#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */
+#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */
+#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */
+#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */
+#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */
+#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */
+#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */
+#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */
+#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */
+#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */
+#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */
+#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */
+#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */
+#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */
+#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */
+#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */
+#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */
+#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */
+#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */
+#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */
+#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */
+#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */
+#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */
+#define IADC0_ENTRIES 0x10UL /**> ENTRIES */
+#define ACMP0_DAC_INPUT 0x1UL /**> None */
+#define ACMP0_EXT_OVR_IF 0x1UL /**> None */
+#define ACMP1_DAC_INPUT 0x1UL /**> None */
+#define ACMP1_EXT_OVR_IF 0x1UL /**> None */
+#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */
+#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */
+#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */
+#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */
+#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */
+#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */
+#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */
+#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */
+#define PCNT0_PCNT_WIDTH 0x10UL /**> None */
+#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */
+#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */
+#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */
+#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */
+#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */
+#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */
+#define WDOG0_PCNUM 0x2UL /**> None */
+#define WDOG1_PCNUM 0x2UL /**> None */
+#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */
+#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */
+#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */
+#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */
+#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */
+#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */
+#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */
+#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */
+#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */
+#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */
+#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */
+#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */
+#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */
+#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */
+#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */
+#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */
+#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */
+#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */
+#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */
+#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */
+#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */
+#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */
+#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */
+#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */
+#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */
+#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */
+#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */
+#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */
+#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */
+#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */
+#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */
+#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */
+#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */
+#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */
+#define FRC_DEMOD_FILT_WIDTH 0x13UL /**> New Param */
+#define FRC_FCD_NUM 0x4UL /**> None */
+#define FRC_INTELEMENTS 0x10UL /**> None */
+#define FRC_RAMADDR_WIDTH 0x20UL /**> None */
+#define AGC_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define AGC_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_ADDR_WIDTH 0xAUL /**> New Param */
+#define MODEM_AMPLITUDE_WIDTH 0x14UL /**> New Param */
+#define MODEM_ANT_NUM 0x2UL /**> Antenna Number */
+#define MODEM_DEC0_SIZE 0xFUL /**> New Param */
+#define MODEM_DEMOD_RAM_WIDTH 0xEUL /**> New Param */
+#define MODEM_DEMOD_WIDTH 0x8UL /**> New Param */
+#define MODEM_INTERNAL_SIZE 0x13UL /**> New Param */
+#define MODEM_IN_SIZE 0x8UL /**> New Param */
+#define MODEM_LEADING_BITS_SIZE 0x4UL /**> New Param */
+#define MODEM_PHASE_SIZE 0x8UL /**> New Param */
+#define MODEM_POWER_WIDTH 0xCUL /**> New Param */
+#define MODEM_RAM_SIZE 0x100UL /**> New Param */
+#define MODEM_REMOVE_ANARAMP 0x1UL /**> New Param */
+#define MODEM_REMOVE_BCR 0x1UL /**> New Param */
+#define MODEM_REMOVE_COH_DEMOD 0x0UL /**> New Param */
+#define MODEM_REMOVE_DEMOD_FILTER 0x0UL /**> New Param */
+#define MODEM_REMOVE_HADM 0x0UL /**> New Param */
+#define MODEM_REMOVE_IQDSA 0x1UL /**> New Param */
+#define MODEM_REMOVE_LRBLE 0x0UL /**> New Param */
+#define MODEM_REMOVE_OOKSHAPING 0x1UL /**> New Param */
+#define MODEM_REMOVE_SI 0x0UL /**> New Param */
+#define MODEM_REMOVE_SRC2_NCO 0x0UL /**> New Param */
+#define MODEM_SYMBOL_WIDTH 0x4UL /**> New Param */
+#define SYNTH_CHPDACBITS 0x8UL /**> */
+#define SYNTH_DACDEMBITS 0x3UL /**> */
+#define SYNTH_MMDDENOMBITS 0x9UL /**> */
+#define SYNTH_MODEM_AFCADJ_WIDTH 0x13UL /**> */
+#define SYNTH_MOD_OUT_WIDTH 0x11UL /**> */
+#define SYNTH_ZERO_IF_RECEIVER 0x0UL /**> */
+#define PROTIMER_CC_NUM 0x8UL /**> None */
+#define PROTIMER_PRS_NUM 0xBUL /**> */
+#define RAC_DIAGABLK_WIDTH 0x7UL /**> None */
+#define RAC_DIAGATP_WIDTH 0x6UL /**> None */
+#define RAC_DPI_CHAN_COUNT 0x6UL /**> */
+#define RAC_PRESC_BITS 0x7UL /**> None */
+#define RAC_WAIT_BITS 0xAUL /**> None */
+#define RFMAILBOX_NUM_MSGPTRS 0x4UL /**> */
+#define RFECA0_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define RFECA1_BUF_NUM 0x2UL /**> Number of Memory Buffers */
+#define ECAIFADC_FIFO_SIZE 0x4UL /**> FIFO size */
+#define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */
+#define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */
+#define BUFC_NUMOFBUFS 0x4UL /**> New Param */
+#define BUFC_NUMOFINPUTS 0x1UL /**> New Param */
+
+/* Instance macros for ACMP */
+#define ACMP(n) (((n) == 0) ? ACMP0 \
+ : ((n) == 1) ? ACMP1 \
+ : 0x0UL)
+#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \
+ : ((ref) == ACMP1) ? 1 \
+ : -1)
+#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \
+ : ((n) == 1) ? ACMP1_DAC_INPUT \
+ : 0x0UL)
+#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \
+ : ((n) == 1) ? ACMP1_EXT_OVR_IF \
+ : 0x0UL)
+
+/* Instance macros for ECA */
+#define ECA(n) (((n) == 0) ? RFECA0 \
+ : ((n) == 1) ? RFECA1 \
+ : 0x0UL)
+#define ECA_NUM(ref) (((ref) == RFECA0) ? 0 \
+ : ((ref) == RFECA1) ? 1 \
+ : -1)
+#define ECA_BUF_NUM(n) (((n) == 0) ? RFECA0_BUF_NUM \
+ : ((n) == 1) ? RFECA1_BUF_NUM \
+ : 0x0UL)
+
+/* Instance macros for EUSART */
+#define EUSART(n) (((n) == 0) ? EUSART0 \
+ : ((n) == 1) ? EUSART1 \
+ : 0x0UL)
+#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \
+ : ((ref) == EUSART1) ? 1 \
+ : -1)
+#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_EM2_CAPABLE \
+ : 0x0UL)
+#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \
+ : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \
+ : 0x0UL)
+
+/* Instance macros for HFRCO */
+#define HFRCO(n) (((n) == 0) ? HFRCO0 \
+ : ((n) == 1) ? HFRCOEM23 \
+ : 0x0UL)
+#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \
+ : ((ref) == HFRCOEM23) ? 1 \
+ : -1)
+#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \
+ : 0x0UL)
+#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \
+ : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \
+ : 0x0UL)
+
+/* Instance macros for I2C */
+#define I2C(n) (((n) == 0) ? I2C0 \
+ : ((n) == 1) ? I2C1 \
+ : 0x0UL)
+#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \
+ : ((ref) == I2C1) ? 1 \
+ : -1)
+#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \
+ : ((n) == 1) ? I2C1_DELAY \
+ : 0x0UL)
+#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
+ : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
+ : 0x0UL)
+
+/* Instance macros for TIMER */
+#define TIMER(n) (((n) == 0) ? TIMER0 \
+ : ((n) == 1) ? TIMER1 \
+ : ((n) == 2) ? TIMER2 \
+ : ((n) == 3) ? TIMER3 \
+ : ((n) == 4) ? TIMER4 \
+ : 0x0UL)
+#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \
+ : ((ref) == TIMER1) ? 1 \
+ : ((ref) == TIMER2) ? 2 \
+ : ((ref) == TIMER3) ? 3 \
+ : ((ref) == TIMER4) ? 4 \
+ : -1)
+#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \
+ : ((n) == 1) ? TIMER1_CC_NUM \
+ : ((n) == 2) ? TIMER2_CC_NUM \
+ : ((n) == 3) ? TIMER3_CC_NUM \
+ : ((n) == 4) ? TIMER4_CC_NUM \
+ : 0x0UL)
+#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \
+ : ((n) == 1) ? TIMER1_CNTWIDTH \
+ : ((n) == 2) ? TIMER2_CNTWIDTH \
+ : ((n) == 3) ? TIMER3_CNTWIDTH \
+ : ((n) == 4) ? TIMER4_CNTWIDTH \
+ : 0x0UL)
+#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \
+ : ((n) == 1) ? TIMER1_DTI \
+ : ((n) == 2) ? TIMER2_DTI \
+ : ((n) == 3) ? TIMER3_DTI \
+ : ((n) == 4) ? TIMER4_DTI \
+ : 0x0UL)
+#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \
+ : ((n) == 1) ? TIMER1_DTI_CC_NUM \
+ : ((n) == 2) ? TIMER2_DTI_CC_NUM \
+ : ((n) == 3) ? TIMER3_DTI_CC_NUM \
+ : ((n) == 4) ? TIMER4_DTI_CC_NUM \
+ : 0x0UL)
+#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \
+ : ((n) == 1) ? TIMER1_NO_DTI \
+ : ((n) == 2) ? TIMER2_NO_DTI \
+ : ((n) == 3) ? TIMER3_NO_DTI \
+ : ((n) == 4) ? TIMER4_NO_DTI \
+ : 0x0UL)
+
+/* Instance macros for VDAC */
+#define VDAC(n) (((n) == 0) ? VDAC0 \
+ : ((n) == 1) ? VDAC1 \
+ : 0x0UL)
+#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \
+ : ((ref) == VDAC1) ? 1 \
+ : -1)
+#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \
+ : ((n) == 1) ? VDAC1_ALT_WIDTH \
+ : 0x0UL)
+#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \
+ : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \
+ : 0x0UL)
+#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \
+ : ((n) == 1) ? VDAC1_FIFO_DEPTH \
+ : 0x0UL)
+#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \
+ : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \
+ : 0x0UL)
+#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \
+ : ((n) == 1) ? VDAC1_RESOLUTION \
+ : 0x0UL)
+
+/* Instance macros for WDOG */
+#define WDOG(n) (((n) == 0) ? WDOG0 \
+ : ((n) == 1) ? WDOG1 \
+ : 0x0UL)
+#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \
+ : ((ref) == WDOG1) ? 1 \
+ : -1)
+#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \
+ : ((n) == 1) ? WDOG1_PCNUM \
+ : 0x0UL)
+
+/** @} End of group EFR32MG24B610F1536IM40_Peripheral_Parameters */
+
+/** @} End of group EFR32MG24B610F1536IM40 */
+/** @}} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/em_device.h b/mcu/efr/common/vendor/efr32mg24/Include/em_device.h
new file mode 100644
index 00000000..13e7a19e
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/em_device.h
@@ -0,0 +1,158 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories
+ * microcontroller devices
+ *
+ * This is a convenience header file for defining the part number on the
+ * build command line, instead of specifying the part specific header file.
+ *
+ * @verbatim
+ * Example: Add "-DEFM32G890F128" to your build options, to define part
+ * Add "#include "em_device.h" to your source files
+
+ *
+ * @endverbatim
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+
+#ifndef EM_DEVICE_H
+#define EM_DEVICE_H
+#if defined(EFR32MG24A010F1024IM40)
+#include "efr32mg24a010f1024im40.h"
+
+#elif defined(EFR32MG24A010F1024IM48)
+#include "efr32mg24a010f1024im48.h"
+
+#elif defined(EFR32MG24A010F1536GM40)
+#include "efr32mg24a010f1536gm40.h"
+
+#elif defined(EFR32MG24A010F1536GM48)
+#include "efr32mg24a010f1536gm48.h"
+
+#elif defined(EFR32MG24A010F1536IM40)
+#include "efr32mg24a010f1536im40.h"
+
+#elif defined(EFR32MG24A010F1536IM48)
+#include "efr32mg24a010f1536im48.h"
+
+#elif defined(EFR32MG24A020F1024IM40)
+#include "efr32mg24a020f1024im40.h"
+
+#elif defined(EFR32MG24A020F1024IM48)
+#include "efr32mg24a020f1024im48.h"
+
+#elif defined(EFR32MG24A020F1536GM40)
+#include "efr32mg24a020f1536gm40.h"
+
+#elif defined(EFR32MG24A020F1536GM48)
+#include "efr32mg24a020f1536gm48.h"
+
+#elif defined(EFR32MG24A020F1536IM40)
+#include "efr32mg24a020f1536im40.h"
+
+#elif defined(EFR32MG24A020F1536IM48)
+#include "efr32mg24a020f1536im48.h"
+
+#elif defined(EFR32MG24A021F1024IM40)
+#include "efr32mg24a021f1024im40.h"
+
+#elif defined(EFR32MG24A110F1024IM48)
+#include "efr32mg24a110f1024im48.h"
+
+#elif defined(EFR32MG24A110F1536GM48)
+#include "efr32mg24a110f1536gm48.h"
+
+#elif defined(EFR32MG24A111F1536GM48)
+#include "efr32mg24a111f1536gm48.h"
+
+#elif defined(EFR32MG24A120F1536GM48)
+#include "efr32mg24a120f1536gm48.h"
+
+#elif defined(EFR32MG24A121F1536GM48)
+#include "efr32mg24a121f1536gm48.h"
+
+#elif defined(EFR32MG24A410F1536IM40)
+#include "efr32mg24a410f1536im40.h"
+
+#elif defined(EFR32MG24A410F1536IM48)
+#include "efr32mg24a410f1536im48.h"
+
+#elif defined(EFR32MG24A420F1536IM40)
+#include "efr32mg24a420f1536im40.h"
+
+#elif defined(EFR32MG24A420F1536IM48)
+#include "efr32mg24a420f1536im48.h"
+
+#elif defined(EFR32MG24A610F1536IM40)
+#include "efr32mg24a610f1536im40.h"
+
+#elif defined(EFR32MG24A620F1536IM40)
+#include "efr32mg24a620f1536im40.h"
+
+#elif defined(EFR32MG24B010F1024IM48)
+#include "efr32mg24b010f1024im48.h"
+
+#elif defined(EFR32MG24B010F1536IM40)
+#include "efr32mg24b010f1536im40.h"
+
+#elif defined(EFR32MG24B010F1536IM48)
+#include "efr32mg24b010f1536im48.h"
+
+#elif defined(EFR32MG24B020F1024IM48)
+#include "efr32mg24b020f1024im48.h"
+
+#elif defined(EFR32MG24B020F1536IM40)
+#include "efr32mg24b020f1536im40.h"
+
+#elif defined(EFR32MG24B020F1536IM48)
+#include "efr32mg24b020f1536im48.h"
+
+#elif defined(EFR32MG24B110F1536GM48)
+#include "efr32mg24b110f1536gm48.h"
+
+#elif defined(EFR32MG24B110F1536IM48)
+#include "efr32mg24b110f1536im48.h"
+
+#elif defined(EFR32MG24B120F1536IM48)
+#include "efr32mg24b120f1536im48.h"
+
+#elif defined(EFR32MG24B210F1536IM48)
+#include "efr32mg24b210f1536im48.h"
+
+#elif defined(EFR32MG24B220F1536IM48)
+#include "efr32mg24b220f1536im48.h"
+
+#elif defined(EFR32MG24B310F1536IM48)
+#include "efr32mg24b310f1536im48.h"
+
+#elif defined(EFR32MG24B610F1536IM40)
+#include "efr32mg24b610f1536im40.h"
+
+#else
+#error "em_device.h: PART NUMBER undefined"
+#endif
+#endif /* EM_DEVICE_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Include/system_efr32mg24.h b/mcu/efr/common/vendor/efr32mg24/Include/system_efr32mg24.h
new file mode 100644
index 00000000..5834d8b7
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Include/system_efr32mg24.h
@@ -0,0 +1,233 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS system header file for EFR32MG24
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+
+#ifndef SYSTEM_EFR32MG24_H
+#define SYSTEM_EFR32MG24_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include
+
+/***************************************************************************//**
+ * @addtogroup Parts
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @addtogroup EFR32MG24 EFR32MG24
+ * @{
+ ******************************************************************************/
+
+/*******************************************************************************
+ ****************************** TYPEDEFS ***********************************
+ ******************************************************************************/
+
+/* Interrupt vectortable entry */
+typedef union {
+ void (*pFunc)(void);
+ void *topOfStack;
+} tVectorEntry;
+
+/*******************************************************************************
+ ************************** GLOBAL VARIABLES *******************************
+ ******************************************************************************/
+
+#if !defined(SYSTEM_NO_STATIC_MEMORY)
+extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */
+extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */
+#endif
+
+#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+#if defined(__ICCARM__) /* IAR requires the __vector_table symbol */
+#define __Vectors __vector_table
+#endif
+extern const tVectorEntry __Vectors[];
+#endif
+
+/*******************************************************************************
+ ***************************** PROTOTYPES **********************************
+ ******************************************************************************/
+
+void Reset_Handler(void); /**< Reset Handler */
+void NMI_Handler(void); /**< NMI Handler */
+void HardFault_Handler(void); /**< Hard Fault Handler */
+void MemManage_Handler(void); /**< MPU Fault Handler */
+void BusFault_Handler(void); /**< Bus Fault Handler */
+void UsageFault_Handler(void); /**< Usage Fault Handler */
+void SVC_Handler(void); /**< SVCall Handler */
+void DebugMon_Handler(void); /**< Debug Monitor Handler */
+void PendSV_Handler(void); /**< PendSV Handler */
+void SysTick_Handler(void); /**< SysTick Handler */
+
+/* Part Specific Interrupts */
+void SMU_SECURE_IRQHandler(void); /**< SMU_SECURE IRQ Handler */
+void SMU_PRIVILEGED_IRQHandler(void); /**< SMU_PRIVILEGED IRQ Handler */
+void SMU_NS_PRIVILEGED_IRQHandler(void); /**< SMU_NS_PRIVILEGED IRQ Handler */
+void EMU_IRQHandler(void); /**< EMU IRQ Handler */
+void TIMER0_IRQHandler(void); /**< TIMER0 IRQ Handler */
+void TIMER1_IRQHandler(void); /**< TIMER1 IRQ Handler */
+void TIMER2_IRQHandler(void); /**< TIMER2 IRQ Handler */
+void TIMER3_IRQHandler(void); /**< TIMER3 IRQ Handler */
+void TIMER4_IRQHandler(void); /**< TIMER4 IRQ Handler */
+void USART0_RX_IRQHandler(void); /**< USART0_RX IRQ Handler */
+void USART0_TX_IRQHandler(void); /**< USART0_TX IRQ Handler */
+void EUSART0_RX_IRQHandler(void); /**< EUSART0_RX IRQ Handler */
+void EUSART0_TX_IRQHandler(void); /**< EUSART0_TX IRQ Handler */
+void EUSART1_RX_IRQHandler(void); /**< EUSART1_RX IRQ Handler */
+void EUSART1_TX_IRQHandler(void); /**< EUSART1_TX IRQ Handler */
+void MVP_IRQHandler(void); /**< MVP IRQ Handler */
+void ICACHE0_IRQHandler(void); /**< ICACHE0 IRQ Handler */
+void BURTC_IRQHandler(void); /**< BURTC IRQ Handler */
+void LETIMER0_IRQHandler(void); /**< LETIMER0 IRQ Handler */
+void SYSCFG_IRQHandler(void); /**< SYSCFG IRQ Handler */
+void MPAHBRAM_IRQHandler(void); /**< MPAHBRAM IRQ Handler */
+void LDMA_IRQHandler(void); /**< LDMA IRQ Handler */
+void LFXO_IRQHandler(void); /**< LFXO IRQ Handler */
+void LFRCO_IRQHandler(void); /**< LFRCO IRQ Handler */
+void ULFRCO_IRQHandler(void); /**< ULFRCO IRQ Handler */
+void GPIO_ODD_IRQHandler(void); /**< GPIO_ODD IRQ Handler */
+void GPIO_EVEN_IRQHandler(void); /**< GPIO_EVEN IRQ Handler */
+void I2C0_IRQHandler(void); /**< I2C0 IRQ Handler */
+void I2C1_IRQHandler(void); /**< I2C1 IRQ Handler */
+void EMUDG_IRQHandler(void); /**< EMUDG IRQ Handler */
+void AGC_IRQHandler(void); /**< AGC IRQ Handler */
+void BUFC_IRQHandler(void); /**< BUFC IRQ Handler */
+void FRC_PRI_IRQHandler(void); /**< FRC_PRI IRQ Handler */
+void FRC_IRQHandler(void); /**< FRC IRQ Handler */
+void MODEM_IRQHandler(void); /**< MODEM IRQ Handler */
+void PROTIMER_IRQHandler(void); /**< PROTIMER IRQ Handler */
+void RAC_RSM_IRQHandler(void); /**< RAC_RSM IRQ Handler */
+void RAC_SEQ_IRQHandler(void); /**< RAC_SEQ IRQ Handler */
+void HOSTMAILBOX_IRQHandler(void); /**< HOSTMAILBOX IRQ Handler */
+void SYNTH_IRQHandler(void); /**< SYNTH IRQ Handler */
+void ACMP0_IRQHandler(void); /**< ACMP0 IRQ Handler */
+void ACMP1_IRQHandler(void); /**< ACMP1 IRQ Handler */
+void WDOG0_IRQHandler(void); /**< WDOG0 IRQ Handler */
+void WDOG1_IRQHandler(void); /**< WDOG1 IRQ Handler */
+void HFXO0_IRQHandler(void); /**< HFXO0 IRQ Handler */
+void HFRCO0_IRQHandler(void); /**< HFRCO0 IRQ Handler */
+void HFRCOEM23_IRQHandler(void); /**< HFRCOEM23 IRQ Handler */
+void CMU_IRQHandler(void); /**< CMU IRQ Handler */
+void AES_IRQHandler(void); /**< AES IRQ Handler */
+void IADC_IRQHandler(void); /**< IADC IRQ Handler */
+void MSC_IRQHandler(void); /**< MSC IRQ Handler */
+void DPLL0_IRQHandler(void); /**< DPLL0 IRQ Handler */
+void EMUEFP_IRQHandler(void); /**< EMUEFP IRQ Handler */
+void DCDC_IRQHandler(void); /**< DCDC IRQ Handler */
+void PCNT0_IRQHandler(void); /**< PCNT0 IRQ Handler */
+void SW0_IRQHandler(void); /**< SW0 IRQ Handler */
+void SW1_IRQHandler(void); /**< SW1 IRQ Handler */
+void SW2_IRQHandler(void); /**< SW2 IRQ Handler */
+void SW3_IRQHandler(void); /**< SW3 IRQ Handler */
+void KERNEL0_IRQHandler(void); /**< KERNEL0 IRQ Handler */
+void KERNEL1_IRQHandler(void); /**< KERNEL1 IRQ Handler */
+void M33CTI0_IRQHandler(void); /**< M33CTI0 IRQ Handler */
+void M33CTI1_IRQHandler(void); /**< M33CTI1 IRQ Handler */
+void FPUEXH_IRQHandler(void); /**< FPUEXH IRQ Handler */
+void SETAMPERHOST_IRQHandler(void); /**< SETAMPERHOST IRQ Handler */
+void SEMBRX_IRQHandler(void); /**< SEMBRX IRQ Handler */
+void SEMBTX_IRQHandler(void); /**< SEMBTX IRQ Handler */
+void SYSRTC_APP_IRQHandler(void); /**< SYSRTC_APP IRQ Handler */
+void SYSRTC_SEQ_IRQHandler(void); /**< SYSRTC_SEQ IRQ Handler */
+void KEYSCAN_IRQHandler(void); /**< KEYSCAN IRQ Handler */
+void RFECA0_IRQHandler(void); /**< RFECA0 IRQ Handler */
+void RFECA1_IRQHandler(void); /**< RFECA1 IRQ Handler */
+void VDAC0_IRQHandler(void); /**< VDAC0 IRQ Handler */
+void VDAC1_IRQHandler(void); /**< VDAC1 IRQ Handler */
+void AHB2AHB0_IRQHandler(void); /**< AHB2AHB0 IRQ Handler */
+void AHB2AHB1_IRQHandler(void); /**< AHB2AHB1 IRQ Handler */
+
+#if (__FPU_PRESENT == 1)
+void FPUEH_IRQHandler(void); /**< FPU IRQ Handler */
+#endif
+
+uint32_t SystemHCLKGet(void);
+
+/**************************************************************************//**
+ * @brief
+ * Update CMSIS SystemCoreClock variable.
+ *
+ * @details
+ * CMSIS defines a global variable SystemCoreClock that shall hold the
+ * core frequency in Hz. If the core frequency is dynamically changed, the
+ * variable must be kept updated in order to be CMSIS compliant.
+ *
+ * Notice that only if changing the core clock frequency through the EMLIB
+ * CMU API, this variable will be kept updated. This function is only
+ * provided for CMSIS compliance and if a user modifies the the core clock
+ * outside the EMLIB CMU API.
+ *****************************************************************************/
+static __INLINE uint32_t SystemCoreClockGet(void)
+{
+ return SystemHCLKGet();
+}
+
+/**************************************************************************//**
+ * @brief
+ * Update CMSIS SystemCoreClock variable.
+ *
+ * @details
+ * CMSIS defines a global variable SystemCoreClock that shall hold the
+ * core frequency in Hz. If the core frequency is dynamically changed, the
+ * variable must be kept updated in order to be CMSIS compliant.
+ *
+ * Notice that only if changing the core clock frequency through the EMLIB
+ * CMU API, this variable will be kept updated. This function is only
+ * provided for CMSIS compliance and if a user modifies the the core clock
+ * outside the EMLIB CMU API.
+ *****************************************************************************/
+static __INLINE void SystemCoreClockUpdate(void)
+{
+ SystemHCLKGet();
+}
+
+void SystemInit(void);
+uint32_t SystemHFRCODPLLClockGet(void);
+void SystemHFRCODPLLClockSet(uint32_t freq);
+uint32_t SystemSYSCLKGet(void);
+uint32_t SystemMaxCoreClockGet(void);
+uint32_t SystemFSRCOClockGet(void);
+uint32_t SystemHFXOClockGet(void);
+void SystemHFXOClockSet(uint32_t freq);
+uint32_t SystemCLKIN0Get(void);
+uint32_t SystemHFRCOEM23ClockGet(void);
+uint32_t SystemLFXOClockGet(void);
+void SystemLFXOClockSet(uint32_t freq);
+uint32_t SystemLFRCOClockGet(void);
+uint32_t SystemULFRCOClockGet(void);
+
+/** @} End of group */
+/** @} End of group Parts */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* SYSTEM_EFR32MG24_H */
diff --git a/mcu/efr/common/vendor/efr32mg24/Source/GCC/efr32mg24.ld b/mcu/efr/common/vendor/efr32mg24/Source/GCC/efr32mg24.ld
new file mode 100644
index 00000000..bd86f762
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Source/GCC/efr32mg24.ld
@@ -0,0 +1,229 @@
+/***************************************************************************//**
+ * @file
+ * Linker script for Silicon Labs EFR32MG24 devices
+ *******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1536K
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapBase
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.vectors))
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG (__data2_end__ - __data2_start__)
+ __copy_table_end__ = .;
+ } > FLASH
+ */
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (__bss2_start__)
+ LONG (__bss2_end__ - __bss2_start__)
+ __zero_table_end__ = .;
+ } > FLASH
+ */
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+ . = ALIGN (4);
+ PROVIDE (__ram_func_section_start = .);
+ *(.ram)
+ PROVIDE (__ram_func_section_end = .);
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __HeapBase = .;
+ __end__ = .;
+ end = __end__;
+ _end = __end__;
+ KEEP(*(.heap*))
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ KEEP(*(.stack*))
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+ /* Check if FLASH usage exceeds FLASH size */
+ /*ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), "FLASH memory overflowed !")*/
+}
\ No newline at end of file
diff --git a/mcu/efr/common/vendor/efr32mg24/Source/GCC/startup_efr32mg24.S b/mcu/efr/common/vendor/efr32mg24/Source/GCC/startup_efr32mg24.S
new file mode 100644
index 00000000..69d225c2
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Source/GCC/startup_efr32mg24.S
@@ -0,0 +1,413 @@
+/**************************************************************************//**
+ * @file
+ * @brief CMSIS Compatible EFR32MG24 startup file for GCC.
+ * Should be used with GCC 'GNU Tools ARM Embedded'
+ ******************************************************************************
+ * # License
+ *
+ * The licensor of this software is Silicon Laboratories Inc. Your use of this
+ * software is governed by the terms of Silicon Labs Master Software License
+ * Agreement (MSLA) available at
+ * www.silabs.com/about-us/legal/master-software-license-agreement. This
+ * software is Third Party Software licensed by Silicon Labs from a third party
+ * and is governed by the sections of the MSLA applicable to Third Party
+ * Software and the additional terms set forth below.
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ .syntax unified
+ .arch armv8-m.main
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x00000400
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x00000C00
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long Default_Handler /* Reserved */
+ .long Default_Handler /* Reserved */
+ .long Default_Handler /* Reserved */
+ .long Default_Handler /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long sl_app_properties /* Application properties */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long SMU_SECURE_IRQHandler /* 0 - SMU_SECURE */
+ .long SMU_PRIVILEGED_IRQHandler /* 1 - SMU_PRIVILEGED */
+ .long SMU_NS_PRIVILEGED_IRQHandler /* 2 - SMU_NS_PRIVILEGED */
+ .long EMU_IRQHandler /* 3 - EMU */
+ .long TIMER0_IRQHandler /* 4 - TIMER0 */
+ .long TIMER1_IRQHandler /* 5 - TIMER1 */
+ .long TIMER2_IRQHandler /* 6 - TIMER2 */
+ .long TIMER3_IRQHandler /* 7 - TIMER3 */
+ .long TIMER4_IRQHandler /* 8 - TIMER4 */
+ .long USART0_RX_IRQHandler /* 9 - USART0_RX */
+ .long USART0_TX_IRQHandler /* 10 - USART0_TX */
+ .long EUSART0_RX_IRQHandler /* 11 - EUSART0_RX */
+ .long EUSART0_TX_IRQHandler /* 12 - EUSART0_TX */
+ .long EUSART1_RX_IRQHandler /* 13 - EUSART1_RX */
+ .long EUSART1_TX_IRQHandler /* 14 - EUSART1_TX */
+ .long MVP_IRQHandler /* 15 - MVP */
+ .long ICACHE0_IRQHandler /* 16 - ICACHE0 */
+ .long BURTC_IRQHandler /* 17 - BURTC */
+ .long LETIMER0_IRQHandler /* 18 - LETIMER0 */
+ .long SYSCFG_IRQHandler /* 19 - SYSCFG */
+ .long MPAHBRAM_IRQHandler /* 20 - MPAHBRAM */
+ .long LDMA_IRQHandler /* 21 - LDMA */
+ .long LFXO_IRQHandler /* 22 - LFXO */
+ .long LFRCO_IRQHandler /* 23 - LFRCO */
+ .long ULFRCO_IRQHandler /* 24 - ULFRCO */
+ .long GPIO_ODD_IRQHandler /* 25 - GPIO_ODD */
+ .long GPIO_EVEN_IRQHandler /* 26 - GPIO_EVEN */
+ .long I2C0_IRQHandler /* 27 - I2C0 */
+ .long I2C1_IRQHandler /* 28 - I2C1 */
+ .long EMUDG_IRQHandler /* 29 - EMUDG */
+ .long AGC_IRQHandler /* 30 - AGC */
+ .long BUFC_IRQHandler /* 31 - BUFC */
+ .long FRC_PRI_IRQHandler /* 32 - FRC_PRI */
+ .long FRC_IRQHandler /* 33 - FRC */
+ .long MODEM_IRQHandler /* 34 - MODEM */
+ .long PROTIMER_IRQHandler /* 35 - PROTIMER */
+ .long RAC_RSM_IRQHandler /* 36 - RAC_RSM */
+ .long RAC_SEQ_IRQHandler /* 37 - RAC_SEQ */
+ .long HOSTMAILBOX_IRQHandler /* 38 - HOSTMAILBOX */
+ .long SYNTH_IRQHandler /* 39 - SYNTH */
+ .long ACMP0_IRQHandler /* 40 - ACMP0 */
+ .long ACMP1_IRQHandler /* 41 - ACMP1 */
+ .long WDOG0_IRQHandler /* 42 - WDOG0 */
+ .long WDOG1_IRQHandler /* 43 - WDOG1 */
+ .long HFXO0_IRQHandler /* 44 - HFXO0 */
+ .long HFRCO0_IRQHandler /* 45 - HFRCO0 */
+ .long HFRCOEM23_IRQHandler /* 46 - HFRCOEM23 */
+ .long CMU_IRQHandler /* 47 - CMU */
+ .long AES_IRQHandler /* 48 - AES */
+ .long IADC_IRQHandler /* 49 - IADC */
+ .long MSC_IRQHandler /* 50 - MSC */
+ .long DPLL0_IRQHandler /* 51 - DPLL0 */
+ .long EMUEFP_IRQHandler /* 52 - EMUEFP */
+ .long DCDC_IRQHandler /* 53 - DCDC */
+ .long PCNT0_IRQHandler /* 54 - PCNT0 */
+ .long SW0_IRQHandler /* 55 - SW0 */
+ .long SW1_IRQHandler /* 56 - SW1 */
+ .long SW2_IRQHandler /* 57 - SW2 */
+ .long SW3_IRQHandler /* 58 - SW3 */
+ .long KERNEL0_IRQHandler /* 59 - KERNEL0 */
+ .long KERNEL1_IRQHandler /* 60 - KERNEL1 */
+ .long M33CTI0_IRQHandler /* 61 - M33CTI0 */
+ .long M33CTI1_IRQHandler /* 62 - M33CTI1 */
+ .long FPUEXH_IRQHandler /* 63 - FPUEXH */
+ .long SETAMPERHOST_IRQHandler /* 64 - SETAMPERHOST */
+ .long SEMBRX_IRQHandler /* 65 - SEMBRX */
+ .long SEMBTX_IRQHandler /* 66 - SEMBTX */
+ .long SYSRTC_APP_IRQHandler /* 67 - SYSRTC_APP */
+ .long SYSRTC_SEQ_IRQHandler /* 68 - SYSRTC_SEQ */
+ .long KEYSCAN_IRQHandler /* 69 - KEYSCAN */
+ .long RFECA0_IRQHandler /* 70 - RFECA0 */
+ .long RFECA1_IRQHandler /* 71 - RFECA1 */
+ .long VDAC0_IRQHandler /* 72 - VDAC0 */
+ .long VDAC1_IRQHandler /* 73 - VDAC1 */
+ .long AHB2AHB0_IRQHandler /* 74 - AHB2AHB0 */
+ .long AHB2AHB1_IRQHandler /* 75 - AHB2AHB1 */
+
+ .size __Vectors, . - __Vectors
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+#ifndef __NO_SYSTEM_INIT
+ ldr r0, =SystemInit
+ blx r0
+#endif
+
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+#endif /* __STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __zero_table_start__ and __zero_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak Default_Handler
+ .type Default_Handler, %function
+ .weak sl_app_properties
+ .type sl_app_properties, %common
+Default_Handler:
+sl_app_properties: /* Provide a dummy value for the sl_app_properties symbol. */
+ b .
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers.
+ */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler MemManage_Handler
+ def_irq_handler BusFault_Handler
+ def_irq_handler UsageFault_Handler
+ def_irq_handler SVC_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+ def_irq_handler SMU_SECURE_IRQHandler
+ def_irq_handler SMU_PRIVILEGED_IRQHandler
+ def_irq_handler SMU_NS_PRIVILEGED_IRQHandler
+ def_irq_handler EMU_IRQHandler
+ def_irq_handler TIMER0_IRQHandler
+ def_irq_handler TIMER1_IRQHandler
+ def_irq_handler TIMER2_IRQHandler
+ def_irq_handler TIMER3_IRQHandler
+ def_irq_handler TIMER4_IRQHandler
+ def_irq_handler USART0_RX_IRQHandler
+ def_irq_handler USART0_TX_IRQHandler
+ def_irq_handler EUSART0_RX_IRQHandler
+ def_irq_handler EUSART0_TX_IRQHandler
+ def_irq_handler EUSART1_RX_IRQHandler
+ def_irq_handler EUSART1_TX_IRQHandler
+ def_irq_handler MVP_IRQHandler
+ def_irq_handler ICACHE0_IRQHandler
+ def_irq_handler BURTC_IRQHandler
+ def_irq_handler LETIMER0_IRQHandler
+ def_irq_handler SYSCFG_IRQHandler
+ def_irq_handler MPAHBRAM_IRQHandler
+ def_irq_handler LDMA_IRQHandler
+ def_irq_handler LFXO_IRQHandler
+ def_irq_handler LFRCO_IRQHandler
+ def_irq_handler ULFRCO_IRQHandler
+ def_irq_handler GPIO_ODD_IRQHandler
+ def_irq_handler GPIO_EVEN_IRQHandler
+ def_irq_handler I2C0_IRQHandler
+ def_irq_handler I2C1_IRQHandler
+ def_irq_handler EMUDG_IRQHandler
+ def_irq_handler AGC_IRQHandler
+ def_irq_handler BUFC_IRQHandler
+ def_irq_handler FRC_PRI_IRQHandler
+ def_irq_handler FRC_IRQHandler
+ def_irq_handler MODEM_IRQHandler
+ def_irq_handler PROTIMER_IRQHandler
+ def_irq_handler RAC_RSM_IRQHandler
+ def_irq_handler RAC_SEQ_IRQHandler
+ def_irq_handler HOSTMAILBOX_IRQHandler
+ def_irq_handler SYNTH_IRQHandler
+ def_irq_handler ACMP0_IRQHandler
+ def_irq_handler ACMP1_IRQHandler
+ def_irq_handler WDOG0_IRQHandler
+ def_irq_handler WDOG1_IRQHandler
+ def_irq_handler HFXO0_IRQHandler
+ def_irq_handler HFRCO0_IRQHandler
+ def_irq_handler HFRCOEM23_IRQHandler
+ def_irq_handler CMU_IRQHandler
+ def_irq_handler AES_IRQHandler
+ def_irq_handler IADC_IRQHandler
+ def_irq_handler MSC_IRQHandler
+ def_irq_handler DPLL0_IRQHandler
+ def_irq_handler EMUEFP_IRQHandler
+ def_irq_handler DCDC_IRQHandler
+ def_irq_handler PCNT0_IRQHandler
+ def_irq_handler SW0_IRQHandler
+ def_irq_handler SW1_IRQHandler
+ def_irq_handler SW2_IRQHandler
+ def_irq_handler SW3_IRQHandler
+ def_irq_handler KERNEL0_IRQHandler
+ def_irq_handler KERNEL1_IRQHandler
+ def_irq_handler M33CTI0_IRQHandler
+ def_irq_handler M33CTI1_IRQHandler
+ def_irq_handler FPUEXH_IRQHandler
+ def_irq_handler SETAMPERHOST_IRQHandler
+ def_irq_handler SEMBRX_IRQHandler
+ def_irq_handler SEMBTX_IRQHandler
+ def_irq_handler SYSRTC_APP_IRQHandler
+ def_irq_handler SYSRTC_SEQ_IRQHandler
+ def_irq_handler KEYSCAN_IRQHandler
+ def_irq_handler RFECA0_IRQHandler
+ def_irq_handler RFECA1_IRQHandler
+ def_irq_handler VDAC0_IRQHandler
+ def_irq_handler VDAC1_IRQHandler
+ def_irq_handler AHB2AHB0_IRQHandler
+ def_irq_handler AHB2AHB1_IRQHandler
+
+ .end
\ No newline at end of file
diff --git a/mcu/efr/common/vendor/efr32mg24/Source/GCC/startup_efr32mg24.c b/mcu/efr/common/vendor/efr32mg24/Source/GCC/startup_efr32mg24.c
new file mode 100644
index 00000000..651d6f38
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Source/GCC/startup_efr32mg24.c
@@ -0,0 +1,418 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Compatible EFR32MG24 startup file in C.
+ * Should be used with GCC 'GNU Tools ARM Embedded'.
+ *******************************************************************************
+ * # License
+ *
+ * The licensor of this software is Silicon Laboratories Inc. Your use of this
+ * software is governed by the terms of Silicon Labs Master Software License
+ * Agreement (MSLA) available at
+ * www.silabs.com/about-us/legal/master-software-license-agreement. This
+ * software is Third Party Software licensed by Silicon Labs from a third party
+ * and is governed by the sections of the MSLA applicable to Third Party
+ * Software and the additional terms set forth below.
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include
+#include "em_device.h"
+
+#ifdef BOOTLOADER_ENABLE
+#include "api/btl_interface.h"
+
+#endif
+
+/*----------------------------------------------------------------------------
+ * Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t __etext;
+extern uint32_t __data_start__;
+extern uint32_t __data_end__;
+extern uint32_t __copy_table_start__;
+extern uint32_t __copy_table_end__;
+extern uint32_t __zero_table_start__;
+extern uint32_t __zero_table_end__;
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+extern uint32_t __StackTop;
+
+#ifdef BOOTLOADER_ENABLE
+extern MainBootloaderTable_t mainStageTable;
+
+extern void SystemInit2(void);
+
+/*----------------------------------------------------------------------------
+ * Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void (*pFunc)(void);
+#endif
+
+/*----------------------------------------------------------------------------
+ * External References
+ *----------------------------------------------------------------------------*/
+#ifndef __START
+extern void _start(void) __attribute__((noreturn)); /* Pre Main (C library entry point) */
+#else
+extern int __START(void) __attribute__((noreturn)); /* main entry point */
+#endif
+
+#ifndef __NO_SYSTEM_INIT
+extern void SystemInit(void); /* CMSIS System Initialization */
+#endif
+
+/*----------------------------------------------------------------------------
+ * Internal References
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void); /* Default empty handler */
+void Reset_Handler(void); /* Reset Handler */
+
+/*----------------------------------------------------------------------------
+ * User Initial Stack & Heap
+ *----------------------------------------------------------------------------*/
+#ifndef __STACK_SIZE
+#define __STACK_SIZE 0x00000400
+#endif
+static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
+
+#ifndef __HEAP_SIZE
+#define __HEAP_SIZE 0x00000C00
+#endif
+#if __HEAP_SIZE > 0
+static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap")));
+#endif
+
+/*----------------------------------------------------------------------------
+ * Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Cortex-M Processor Exceptions */
+void NMI_Handler(void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler(void) __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler(void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler(void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler(void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler(void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler(void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler(void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler(void) __attribute__ ((weak, alias("Default_Handler")));
+/* Provide a dummy value for the sl_app_properties symbol. */
+void sl_app_properties(void); /* Prototype to please MISRA checkers. */
+void sl_app_properties(void) __attribute__ ((weak, alias("Default_Handler")));
+
+/* Part Specific Interrupts */
+void SMU_SECURE_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void SMU_PRIVILEGED_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void SMU_NS_PRIVILEGED_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void EMU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void TIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void TIMER1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void TIMER2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void TIMER3_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void TIMER4_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void USART0_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void USART0_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void EUSART0_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void EUSART0_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void EUSART1_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void EUSART1_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void MVP_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void ICACHE0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void BURTC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void LETIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void SYSCFG_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void MPAHBRAM_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void LDMA_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void LFXO_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void LFRCO_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void ULFRCO_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void GPIO_ODD_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void GPIO_EVEN_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void I2C0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void I2C1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void EMUDG_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void AGC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void BUFC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void FRC_PRI_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void FRC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void MODEM_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void PROTIMER_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void RAC_RSM_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void RAC_SEQ_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void HOSTMAILBOX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void SYNTH_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void ACMP0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void ACMP1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void WDOG0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void WDOG1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void HFXO0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void HFRCO0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void HFRCOEM23_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void CMU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void AES_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void IADC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void MSC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void DPLL0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void EMUEFP_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void DCDC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void PCNT0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void SW0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void SW1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void SW2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void SW3_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void KERNEL0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void KERNEL1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void M33CTI0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void M33CTI1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void FPUEXH_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void SETAMPERHOST_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void SEMBRX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void SEMBTX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void SYSRTC_APP_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void SYSRTC_SEQ_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void KEYSCAN_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void RFECA0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void RFECA1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void VDAC0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void VDAC1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void AHB2AHB0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+void AHB2AHB1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+ * Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+extern const tVectorEntry __Vectors[];
+const tVectorEntry __Vectors[] __attribute__ ((section(".vectors"))) = {
+ /* Cortex-M Exception Handlers */
+ { .topOfStack = &__StackTop }, /* Initial Stack Pointer */
+ { Reset_Handler }, /* Reset Handler */
+ { NMI_Handler }, /* NMI Handler */
+ { HardFault_Handler }, /* Hard Fault Handler */
+ { MemManage_Handler }, /* MPU Fault Handler */
+ { BusFault_Handler }, /* Bus Fault Handler */
+ { UsageFault_Handler }, /* Usage Fault Handler */
+ { Default_Handler }, /* Reserved */
+ { Default_Handler }, /* Reserved */
+ { Default_Handler }, /* Reserved */
+#ifdef BOOTLOADER_ENABLE
+ { (pFunc) & mainStageTable },
+#else
+ { Default_Handler }, /* Reserved */
+#endif
+ { SVC_Handler }, /* SVCall Handler */
+ { DebugMon_Handler }, /* Debug Monitor Handler */
+ { sl_app_properties }, /* Application properties */
+ { PendSV_Handler }, /* PendSV Handler */
+ { SysTick_Handler }, /* SysTick Handler */
+
+ /* External interrupts */
+ { SMU_SECURE_IRQHandler }, /* -16 = SMU_SECURE */
+ { SMU_PRIVILEGED_IRQHandler }, /* -15 = SMU_PRIVILEGED */
+ { SMU_NS_PRIVILEGED_IRQHandler }, /* -14 = SMU_NS_PRIVILEGED */
+ { EMU_IRQHandler }, /* -13 = EMU */
+ { TIMER0_IRQHandler }, /* -12 = TIMER0 */
+ { TIMER1_IRQHandler }, /* -11 = TIMER1 */
+ { TIMER2_IRQHandler }, /* -10 = TIMER2 */
+ { TIMER3_IRQHandler }, /* -9 = TIMER3 */
+ { TIMER4_IRQHandler }, /* -8 = TIMER4 */
+ { USART0_RX_IRQHandler }, /* -7 = USART0_RX */
+ { USART0_TX_IRQHandler }, /* -6 = USART0_TX */
+ { EUSART0_RX_IRQHandler }, /* -5 = EUSART0_RX */
+ { EUSART0_TX_IRQHandler }, /* -4 = EUSART0_TX */
+ { EUSART1_RX_IRQHandler }, /* -3 = EUSART1_RX */
+ { EUSART1_TX_IRQHandler }, /* -2 = EUSART1_TX */
+ { MVP_IRQHandler }, /* -1 = MVP */
+ { ICACHE0_IRQHandler }, /* 00 = ICACHE0 */
+ { BURTC_IRQHandler }, /* 01 = BURTC */
+ { LETIMER0_IRQHandler }, /* 02 = LETIMER0 */
+ { SYSCFG_IRQHandler }, /* 03 = SYSCFG */
+ { MPAHBRAM_IRQHandler }, /* 04 = MPAHBRAM */
+ { LDMA_IRQHandler }, /* 05 = LDMA */
+ { LFXO_IRQHandler }, /* 06 = LFXO */
+ { LFRCO_IRQHandler }, /* 07 = LFRCO */
+ { ULFRCO_IRQHandler }, /* 08 = ULFRCO */
+ { GPIO_ODD_IRQHandler }, /* 09 = GPIO_ODD */
+ { GPIO_EVEN_IRQHandler }, /* 10 = GPIO_EVEN */
+ { I2C0_IRQHandler }, /* 11 = I2C0 */
+ { I2C1_IRQHandler }, /* 12 = I2C1 */
+ { EMUDG_IRQHandler }, /* 13 = EMUDG */
+ { AGC_IRQHandler }, /* 14 = AGC */
+ { BUFC_IRQHandler }, /* 15 = BUFC */
+ { FRC_PRI_IRQHandler }, /* 16 = FRC_PRI */
+ { FRC_IRQHandler }, /* 17 = FRC */
+ { MODEM_IRQHandler }, /* 18 = MODEM */
+ { PROTIMER_IRQHandler }, /* 19 = PROTIMER */
+ { RAC_RSM_IRQHandler }, /* 20 = RAC_RSM */
+ { RAC_SEQ_IRQHandler }, /* 21 = RAC_SEQ */
+ { HOSTMAILBOX_IRQHandler }, /* 22 = HOSTMAILBOX */
+ { SYNTH_IRQHandler }, /* 23 = SYNTH */
+ { ACMP0_IRQHandler }, /* 24 = ACMP0 */
+ { ACMP1_IRQHandler }, /* 25 = ACMP1 */
+ { WDOG0_IRQHandler }, /* 26 = WDOG0 */
+ { WDOG1_IRQHandler }, /* 27 = WDOG1 */
+ { HFXO0_IRQHandler }, /* 28 = HFXO0 */
+ { HFRCO0_IRQHandler }, /* 29 = HFRCO0 */
+ { HFRCOEM23_IRQHandler }, /* 30 = HFRCOEM23 */
+ { CMU_IRQHandler }, /* 31 = CMU */
+ { AES_IRQHandler }, /* 32 = AES */
+ { IADC_IRQHandler }, /* 33 = IADC */
+ { MSC_IRQHandler }, /* 34 = MSC */
+ { DPLL0_IRQHandler }, /* 35 = DPLL0 */
+ { EMUEFP_IRQHandler }, /* 36 = EMUEFP */
+ { DCDC_IRQHandler }, /* 37 = DCDC */
+ { PCNT0_IRQHandler }, /* 38 = PCNT0 */
+ { SW0_IRQHandler }, /* 39 = SW0 */
+ { SW1_IRQHandler }, /* 40 = SW1 */
+ { SW2_IRQHandler }, /* 41 = SW2 */
+ { SW3_IRQHandler }, /* 42 = SW3 */
+ { KERNEL0_IRQHandler }, /* 43 = KERNEL0 */
+ { KERNEL1_IRQHandler }, /* 44 = KERNEL1 */
+ { M33CTI0_IRQHandler }, /* 45 = M33CTI0 */
+ { M33CTI1_IRQHandler }, /* 46 = M33CTI1 */
+ { FPUEXH_IRQHandler }, /* 47 = FPUEXH */
+ { SETAMPERHOST_IRQHandler }, /* 48 = SETAMPERHOST */
+ { SEMBRX_IRQHandler }, /* 49 = SEMBRX */
+ { SEMBTX_IRQHandler }, /* 50 = SEMBTX */
+ { SYSRTC_APP_IRQHandler }, /* 51 = SYSRTC_APP */
+ { SYSRTC_SEQ_IRQHandler }, /* 52 = SYSRTC_SEQ */
+ { KEYSCAN_IRQHandler }, /* 53 = KEYSCAN */
+ { RFECA0_IRQHandler }, /* 54 = RFECA0 */
+ { RFECA1_IRQHandler }, /* 55 = RFECA1 */
+ { VDAC0_IRQHandler }, /* 56 = VDAC0 */
+ { VDAC1_IRQHandler }, /* 57 = VDAC1 */
+ { AHB2AHB0_IRQHandler }, /* 58 = AHB2AHB0 */
+ { AHB2AHB1_IRQHandler }, /* 59 = AHB2AHB1 */
+};
+
+/*----------------------------------------------------------------------------
+ * Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+ uint32_t *pSrc, *pDest;
+ uint32_t *pTable __attribute__((unused));
+
+#ifndef __NO_SYSTEM_INIT
+ SystemInit();
+#endif
+
+#ifdef BOOTLOADER_ENABLE
+ SystemInit2();
+#endif
+
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ pTable = &__copy_table_start__;
+
+ for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
+ pSrc = (uint32_t *) *(pTable + 0);
+ pDest = (uint32_t *) *(pTable + 1);
+ for (; pDest < (uint32_t *) (*(pTable + 1) + *(pTable + 2)); ) {
+ *pDest++ = *pSrc++;
+ }
+ }
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ pSrc = &__etext;
+ pDest = &__data_start__;
+
+ for (; pDest < &__data_end__; ) {
+ *pDest++ = *pSrc++;
+ }
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ pTable = &__zero_table_start__;
+
+ for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
+ pDest = (uint32_t *) *(pTable + 0);
+ for (; pDest < (uint32_t *) (*(pTable + 0) + *(pTable + 1)); ) {
+ *pDest++ = 0UL;
+ }
+ }
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ pDest = &__bss_start__;
+
+ for (; pDest < &__bss_end__; ) {
+ *pDest++ = 0UL;
+ }
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __START
+#define __START _start
+#endif
+ __START();
+}
+
+/*----------------------------------------------------------------------------
+ * Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+ while (true) {
+ }
+}
diff --git a/mcu/efr/common/vendor/efr32mg24/Source/system_efr32mg24.c b/mcu/efr/common/vendor/efr32mg24/Source/system_efr32mg24.c
new file mode 100644
index 00000000..91428351
--- /dev/null
+++ b/mcu/efr/common/vendor/efr32mg24/Source/system_efr32mg24.c
@@ -0,0 +1,614 @@
+/***************************************************************************//**
+ * @file
+ * @brief CMSIS Cortex-M33 system support for EFR32MG24 devices.
+ ******************************************************************************
+ * # License
+ * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com
+ ******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *****************************************************************************/
+
+#include
+#include "em_device.h"
+
+/*******************************************************************************
+ ****************************** DEFINES ************************************
+ ******************************************************************************/
+
+/* System oscillator frequencies. These frequencies are normally constant */
+/* for a target, but they are made configurable in order to allow run-time */
+/* handling of different boards. The crystal oscillator clocks can be set */
+/* compile time to a non-default value by defining respective nFXO_FREQ */
+/* values according to board design. By defining the nFXO_FREQ to 0, */
+/* one indicates that the oscillator is not present, in order to save some */
+/* SW footprint. */
+
+#if !defined(FSRCO_FREQ)
+/* FSRCO frequency */
+#define FSRCO_FREQ (20000000UL)
+#endif
+
+#if !defined(HFXO_FREQ)
+/* HFXO frequency */
+#define HFXO_FREQ (39000000UL)
+#endif
+
+#if !defined(HFRCODPLL_STARTUP_FREQ)
+/* HFRCODPLL startup frequency */
+#define HFRCODPLL_STARTUP_FREQ (19000000UL)
+#endif
+
+#if !defined(HFRCODPLL_MAX_FREQ)
+/* Maximum HFRCODPLL frequency */
+#define HFRCODPLL_MAX_FREQ (80000000UL)
+#endif
+
+/* CLKIN0 input */
+#if !defined(CLKIN0_FREQ)
+#define CLKIN0_FREQ (0UL)
+#endif
+
+#if !defined(LFRCO_MAX_FREQ)
+/* LFRCO frequency, tuned to below frequency during manufacturing. */
+#define LFRCO_FREQ (32768UL)
+#endif
+
+#if !defined(ULFRCO_FREQ)
+/* ULFRCO frequency */
+#define ULFRCO_FREQ (1000UL)
+#endif
+
+#if !defined(LFXO_FREQ)
+/* LFXO frequency */
+#define LFXO_FREQ (LFRCO_FREQ)
+#endif
+
+/*******************************************************************************
+ ************************** LOCAL VARIABLES ********************************
+ ******************************************************************************/
+
+#if (HFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY)
+/* NOTE: Gecko bootloaders can't have static variable allocation. */
+/* System HFXO clock frequency */
+static uint32_t SystemHFXOClock = HFXO_FREQ;
+#endif
+
+#if (LFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY)
+/* System LFXO clock frequency */
+static uint32_t SystemLFXOClock = LFXO_FREQ;
+#endif
+
+#if !defined(SYSTEM_NO_STATIC_MEMORY)
+/* System HFRCODPLL clock frequency */
+static uint32_t SystemHFRCODPLLClock = HFRCODPLL_STARTUP_FREQ;
+#endif
+
+/*******************************************************************************
+ ************************** GLOBAL VARIABLES *******************************
+ ******************************************************************************/
+
+#if !defined(SYSTEM_NO_STATIC_MEMORY)
+
+/**
+ * @brief
+ * System System Clock Frequency (Core Clock).
+ *
+ * @details
+ * Required CMSIS global variable that must be kept up-to-date.
+ */
+uint32_t SystemCoreClock = HFRCODPLL_STARTUP_FREQ;
+
+#endif
+
+/*******************************************************************************
+ ************************** GLOBAL FUNCTIONS *******************************
+ ******************************************************************************/
+
+/**************************************************************************//**
+ * @brief
+ * Initialize the system.
+ *
+ * @details
+ * Do required generic HW system init.
+ *
+ * @note
+ * This function is invoked during system init, before the main() routine
+ * and any data has been initialized. For this reason, it cannot do any
+ * initialization of variables etc.
+ *****************************************************************************/
+void SystemInit(void)
+{
+#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined(UNALIGNED_SUPPORT_DISABLE)
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+#if (__FPU_PRESENT == 1)
+ SCB->CPACR |= ((3U << 10U * 2U) /* set CP10 Full Access */
+ | (3U << 11U * 2U)); /* set CP11 Full Access */
+#endif
+}
+
+/**************************************************************************//**
+ * @brief
+ * Get current HFRCODPLL frequency.
+ *
+ * @note
+ * This is a EFR32MG24 specific function, not part of the
+ * CMSIS definition.
+ *
+ * @return
+ * HFRCODPLL frequency in Hz.
+ *****************************************************************************/
+uint32_t SystemHFRCODPLLClockGet(void)
+{
+#if !defined(SYSTEM_NO_STATIC_MEMORY)
+ return SystemHFRCODPLLClock;
+#else
+ uint32_t ret = 0UL;
+
+ /* Get oscillator frequency band */
+ switch ((HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK)
+ >> _HFRCO_CAL_FREQRANGE_SHIFT) {
+ case 0:
+ switch (HFRCO0->CAL & _HFRCO_CAL_CLKDIV_MASK) {
+ case HFRCO_CAL_CLKDIV_DIV1:
+ ret = 4000000UL;
+ break;
+
+ case HFRCO_CAL_CLKDIV_DIV2:
+ ret = 2000000UL;
+ break;
+
+ case HFRCO_CAL_CLKDIV_DIV4:
+ ret = 1000000UL;
+ break;
+
+ default:
+ ret = 0UL;
+ break;
+ }
+ break;
+
+ case 3:
+ ret = 7000000UL;
+ break;
+
+ case 6:
+ ret = 13000000UL;
+ break;
+
+ case 7:
+ ret = 16000000UL;
+ break;
+
+ case 8:
+ ret = 19000000UL;
+ break;
+
+ case 10:
+ ret = 26000000UL;
+ break;
+
+ case 11:
+ ret = 32000000UL;
+ break;
+
+ case 12:
+ ret = 38000000UL;
+ break;
+
+ case 13:
+ ret = 48000000UL;
+ break;
+
+ case 14:
+ ret = 56000000UL;
+ break;
+
+ case 15:
+ ret = 64000000UL;
+ break;
+
+ case 16:
+ ret = 80000000UL;
+ break;
+
+ default:
+ break;
+ }
+ return ret;
+#endif
+}
+
+/**************************************************************************//**
+ * @brief
+ * Set HFRCODPLL frequency value.
+ *
+ * @note
+ * This is a EFR32MG24 specific function, not part of the
+ * CMSIS definition.
+ *
+ * @param[in] freq
+ * HFRCODPLL frequency in Hz.
+ *****************************************************************************/
+void SystemHFRCODPLLClockSet(uint32_t freq)
+{
+#if !defined(SYSTEM_NO_STATIC_MEMORY)
+ SystemHFRCODPLLClock = freq;
+#else
+ (void) freq; /* Unused parameter */
+#endif
+}
+
+/***************************************************************************//**
+ * @brief
+ * Get the current system clock frequency (SYSCLK).
+ *
+ * @details
+ * Calculate and get the current core clock frequency based on the current
+ * hardware configuration.
+ *
+ * @note
+ * This is an EFR32MG24 specific function, not part of the
+ * CMSIS definition.
+ *
+ * @return
+ * Current system clock (SYSCLK) frequency in Hz.
+ ******************************************************************************/
+uint32_t SystemSYSCLKGet(void)
+{
+ uint32_t ret = 0U;
+
+ /* Find clock source */
+ switch (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK) {
+ case _CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL:
+ ret = SystemHFRCODPLLClockGet();
+ break;
+
+#if (HFXO_FREQ > 0U)
+ case _CMU_SYSCLKCTRL_CLKSEL_HFXO:
+#if defined(SYSTEM_NO_STATIC_MEMORY)
+ ret = HFXO_FREQ;
+#else
+ ret = SystemHFXOClock;
+#endif
+ break;
+#endif
+
+#if (CLKIN0_FREQ > 0U)
+ case _CMU_SYSCLKCTRL_CLKSEL_CLKIN0:
+ ret = CLKIN0_FREQ;
+ break;
+#endif
+
+ case _CMU_SYSCLKCTRL_CLKSEL_FSRCO:
+ ret = FSRCO_FREQ;
+ break;
+
+ default:
+ /* Unknown clock source. */
+ while (1) {
+ }
+ }
+ return ret;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Get the current system core clock frequency (HCLK).
+ *
+ * @details
+ * Calculate and get the current core clock frequency based on the current
+ * configuration. Assuming that the SystemCoreClock global variable is
+ * maintained, the core clock frequency is stored in that variable as well.
+ * This function will however calculate the core clock based on actual HW
+ * configuration. It will also update the SystemCoreClock global variable.
+ *
+ * @note
+ * This is a EFR32MG24 specific function, not part of the
+ * CMSIS definition.
+ *
+ * @return
+ * The current core clock (HCLK) frequency in Hz.
+ ******************************************************************************/
+uint32_t SystemHCLKGet(void)
+{
+ uint32_t presc, ret;
+
+ ret = SystemSYSCLKGet();
+
+ presc = (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_HCLKPRESC_MASK)
+ >> _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT;
+
+ ret /= presc + 1U;
+
+#if !defined(SYSTEM_NO_STATIC_MEMORY)
+ /* Keep CMSIS system clock variable up-to-date */
+ SystemCoreClock = ret;
+#endif
+
+ return ret;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Get the maximum core clock frequency.
+ *
+ * @note
+ * This is a EFR32MG24 specific function, not part of the
+ * CMSIS definition.
+ *
+ * @return
+ * The maximum core clock frequency in Hz.
+ ******************************************************************************/
+uint32_t SystemMaxCoreClockGet(void)
+{
+ return(HFRCODPLL_MAX_FREQ > HFXO_FREQ \
+ ? HFRCODPLL_MAX_FREQ : HFXO_FREQ);
+}
+
+/**************************************************************************//**
+ * @brief
+ * Get high frequency crystal oscillator clock frequency for target system.
+ *
+ * @note
+ * This is a EFR32MG24 specific function, not part of the
+ * CMSIS definition.
+ *
+ * @return
+ * HFXO frequency in Hz. 0 if the external crystal oscillator is not present.
+ *****************************************************************************/
+uint32_t SystemHFXOClockGet(void)
+{
+ /* The external crystal oscillator is not present if HFXO_FREQ==0 */
+#if (HFXO_FREQ > 0U)
+#if defined(SYSTEM_NO_STATIC_MEMORY)
+ return HFXO_FREQ;
+#else
+ return SystemHFXOClock;
+#endif
+#else
+ return 0U;
+#endif
+}
+
+/**************************************************************************//**
+ * @brief
+ * Set high frequency crystal oscillator clock frequency for target system.
+ *
+ * @note
+ * This function is mainly provided for being able to handle target systems
+ * with different HF crystal oscillator frequencies run-time. If used, it
+ * should probably only be used once during system startup.
+ *
+ * @note
+ * This is a EFR32MG24 specific function, not part of the
+ * CMSIS definition.
+ *
+ * @param[in] freq
+ * HFXO frequency in Hz used for target.
+ *****************************************************************************/
+void SystemHFXOClockSet(uint32_t freq)
+{
+ /* External crystal oscillator present? */
+#if (HFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY)
+ SystemHFXOClock = freq;
+
+ /* Update core clock frequency if HFXO is used to clock core */
+ if ((CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK)
+ == _CMU_SYSCLKCTRL_CLKSEL_HFXO) {
+ /* This function will update the global variable */
+ SystemHCLKGet();
+ }
+#else
+ (void) freq; /* Unused parameter */
+#endif
+}
+
+/**************************************************************************//**
+ * @brief
+ * Get current CLKIN0 frequency.
+ *
+ * @note
+ * This is a EFR32MG24 specific function, not part of the
+ * CMSIS definition.
+ *
+ * @return
+ * CLKIN0 frequency in Hz.
+ *****************************************************************************/
+uint32_t SystemCLKIN0Get(void)
+{
+ return CLKIN0_FREQ;
+}
+
+/**************************************************************************//**
+ * @brief
+ * Get FSRCO frequency.
+ *
+ * @note
+ * This is a EFR32MG24 specific function, not part of the
+ * CMSIS definition.
+ *
+ * @return
+ * FSRCO frequency in Hz.
+ *****************************************************************************/
+uint32_t SystemFSRCOClockGet(void)
+{
+ return FSRCO_FREQ;
+}
+
+/**************************************************************************//**
+ * @brief
+ * Get current HFRCOEM23 frequency.
+ *
+ * @note
+ * This is a EFR32MG24 specific function, not part of the
+ * CMSIS definition.
+ *
+ * @return
+ * HFRCOEM23 frequency in Hz.
+ *****************************************************************************/
+uint32_t SystemHFRCOEM23ClockGet(void)
+{
+ uint32_t ret = 0UL;
+
+ /* Get oscillator frequency band */
+ switch ((HFRCOEM23->CAL & _HFRCO_CAL_FREQRANGE_MASK)
+ >> _HFRCO_CAL_FREQRANGE_SHIFT) {
+ case 0:
+ switch (HFRCOEM23->CAL & _HFRCO_CAL_CLKDIV_MASK) {
+ case HFRCO_CAL_CLKDIV_DIV1:
+ ret = 4000000UL;
+ break;
+
+ case HFRCO_CAL_CLKDIV_DIV2:
+ ret = 2000000UL;
+ break;
+
+ case HFRCO_CAL_CLKDIV_DIV4:
+ ret = 1000000UL;
+ break;
+
+ default:
+ ret = 0UL;
+ break;
+ }
+ break;
+
+ case 6:
+ ret = 13000000UL;
+ break;
+
+ case 7:
+ ret = 16000000UL;
+ break;
+
+ case 8:
+ ret = 19000000UL;
+ break;
+
+ case 10:
+ ret = 26000000UL;
+ break;
+
+ case 11:
+ ret = 32000000UL;
+ break;
+
+ case 12:
+ ret = 40000000UL;
+ break;
+
+ default:
+ break;
+ }
+ return ret;
+}
+
+/**************************************************************************//**
+ * @brief
+ * Get low frequency RC oscillator clock frequency for target system.
+ *
+ * @note
+ * This is a EFR32MG24 specific function, not part of the
+ * CMSIS definition.
+ *
+ * @return
+ * LFRCO frequency in Hz.
+ *****************************************************************************/
+uint32_t SystemLFRCOClockGet(void)
+{
+ return LFRCO_FREQ;
+}
+
+/**************************************************************************//**
+ * @brief
+ * Get ultra low frequency RC oscillator clock frequency for target system.
+ *
+ * @note
+ * This is a EFR32MG24 specific function, not part of the
+ * CMSIS definition.
+ *
+ * @return
+ * ULFRCO frequency in Hz.
+ *****************************************************************************/
+uint32_t SystemULFRCOClockGet(void)
+{
+ /* The ULFRCO frequency is not tuned, and can be very inaccurate */
+ return ULFRCO_FREQ;
+}
+
+/**************************************************************************//**
+ * @brief
+ * Get low frequency crystal oscillator clock frequency for target system.
+ *
+ * @note
+ * This is a EFR32MG24 specific function, not part of the
+ * CMSIS definition.
+ *
+ * @return
+ * LFXO frequency in Hz.
+ *****************************************************************************/
+uint32_t SystemLFXOClockGet(void)
+{
+ /* External crystal present? */
+#if (LFXO_FREQ > 0U)
+#if defined(SYSTEM_NO_STATIC_MEMORY)
+ return LFXO_FREQ;
+#else
+ return SystemLFXOClock;
+#endif
+#else
+ return 0U;
+#endif
+}
+
+/**************************************************************************//**
+ * @brief
+ * Set low frequency crystal oscillator clock frequency for target system.
+ *
+ * @note
+ * This function is mainly provided for being able to handle target systems
+ * with different HF crystal oscillator frequencies run-time. If used, it
+ * should probably only be used once during system startup.
+ *
+ * @note
+ * This is a EFR32MG24 specific function, not part of the
+ * CMSIS definition.
+ *
+ * @param[in] freq
+ * LFXO frequency in Hz used for target.
+ *****************************************************************************/
+void SystemLFXOClockSet(uint32_t freq)
+{
+ /* External crystal oscillator present? */
+#if (LFXO_FREQ > 0U) && !defined(SYSTEM_NO_STATIC_MEMORY)
+ SystemLFXOClock = freq;
+#else
+ (void) freq; /* Unused parameter */
+#endif
+}
diff --git a/mcu/efr/common/vendor/efr32fg13/efr32_gpio.h b/mcu/efr/common/vendor/efr32mg24/efr32_gpio.h
similarity index 81%
rename from mcu/efr/common/vendor/efr32fg13/efr32_gpio.h
rename to mcu/efr/common/vendor/efr32mg24/efr32_gpio.h
index e930caf1..0119932a 100644
--- a/mcu/efr/common/vendor/efr32fg13/efr32_gpio.h
+++ b/mcu/efr/common/vendor/efr32mg24/efr32_gpio.h
@@ -1,25 +1,18 @@
-#ifndef EFR32FG13_GPIO_H_
-#define EFR32FG13_GPIO_H_
+#ifndef EFR32_GPIO_H_
+#define EFR32_GPIO_H_
-#include "../../../efr32/vendor/em_device.h"
+#include "vendor/em_device.h"
/** GPIO ports identificator. */
typedef enum
{
- GPIOA = 0, /**< Port A */
- GPIOB = 1, /**< Port B */
- GPIOC = 2, /**< Port C */
- GPIOD = 3, /**< Port D */
- GPIOE = 4, /**< Port E */
- GPIOF = 5, /**< Port F */
- GPIOG = 6, /**< Port G */
- GPIOH = 7, /**< Port H */
- GPIOI = 8, /**< Port I */
- GPIOJ = 9, /**< Port J */
- GPIOK = 10 /**< Port K */
+ GPIOA = GPIO_PORTA, /**< Port A */
+ GPIOB = GPIO_PORTB, /**< Port B */
+ GPIOC = GPIO_PORTC, /**< Port C */
+ GPIOD = GPIO_PORTD, /**< Port D */
} hal_gpio_port_e;
-/** Pin mode. For more details on each mode, please refer to the EFR32XG13
+/** Pin mode. For more details on each mode, please refer to the EFM32
* reference manual. */
typedef enum
{
@@ -63,7 +56,7 @@ __STATIC_INLINE void hal_gpio_clear(hal_gpio_port_e port, uint32_t pin)
__STATIC_INLINE void hal_gpio_toggle(hal_gpio_port_e port, uint32_t pin)
{
- GPIO->P[port].DOUTTGL = 1 << pin;
+ GPIO->P_TGL[port].DOUT = 1 << pin;
}
__STATIC_INLINE void hal_gpio_set_mode(hal_gpio_port_e port,
@@ -83,4 +76,4 @@ __STATIC_INLINE void hal_gpio_set_mode(hal_gpio_port_e port,
}
}
-#endif /* EFR32FG13_GPIO_H_ */
+#endif /* EFR32_GPIO_H_ */
diff --git a/mcu/efr/common/vendor/em_chip.h b/mcu/efr/common/vendor/em_chip.h
index f233d6f7..a3a19737 100644
--- a/mcu/efr/common/vendor/em_chip.h
+++ b/mcu/efr/common/vendor/em_chip.h
@@ -1,40 +1,40 @@
/***************************************************************************//**
- * @file em_chip.h
- * @brief Chip Initialization API
- * @version 5.4.0
+ * @file
+ * @brief Chip Errata Workarounds
*******************************************************************************
* # License
- * Copyright 2017 Silicon Laboratories, Inc. www.silabs.com
+ * Copyright 2018 Silicon Laboratories Inc. www.silabs.com
*******************************************************************************
*
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
- * obligation to support this Software. Silicon Labs is providing the
- * Software "AS IS", with no express or implied warranties of any kind,
- * including, but not limited to, any implied warranties of merchantability
- * or fitness for any particular purpose or warranties against infringement
- * of any proprietary rights of a third party.
- *
- * Silicon Labs will not be liable for any consequential, incidental, or
- * special damages, or any other relief, or for any claim by any third party,
- * arising from your use of this Software.
- *
******************************************************************************/
#ifndef EM_CHIP_H
#define EM_CHIP_H
#include "em_device.h"
+#include "em_common.h"
#include "em_system.h"
+#include "em_gpio.h"
#include "em_bus.h"
#ifdef __cplusplus
@@ -42,39 +42,39 @@ extern "C" {
#endif
/***************************************************************************//**
- * @addtogroup emlib
- * @{
- ******************************************************************************/
-
-/***************************************************************************//**
- * @addtogroup CHIP
- * @brief Chip errata workarounds initialization API
+ * @addtogroup chip CHIP - Chip Errata Workarounds
+ * @brief Chip errata workaround APIs
* @details
- * API to initialize chip for errata workarounds.
+ * API to apply chip errata workarounds at initialization and reset.
* @{
******************************************************************************/
/**************************************************************************//**
* @brief
- * Chip initialization routine for revision errata workarounds. This function
- * must be called immediately in main().
+ * Chip initialization routine for revision errata workarounds.
*
* @note
* This function must be called immediately in main().
*
- * This init function will configure the device to a state where it is
- * as similar as later revisions as possible, to improve software compatibility
- * with newer parts. See the device specific errata for details.
+ * This initialization function configures the device to a state
+ * as similar to later revisions as possible to improve software compatibility
+ * with newer parts. See the device-specific errata for details.
*****************************************************************************/
__STATIC_INLINE void CHIP_Init(void)
{
+#if defined(MSC_CACHECMD_INVCACHE)
+ MSC->CACHECMD = MSC_CACHECMD_INVCACHE;
+#elif defined(MSC_CMD_INVCACHE)
+ MSC->CMD = MSC_CMD_INVCACHE;
+#endif
+
#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GECKO_FAMILY)
uint32_t rev;
SYSTEM_ChipRevision_TypeDef chipRev;
volatile uint32_t *reg;
rev = *(volatile uint32_t *)(0x0FE081FC);
- /* Engineering Sample calibration setup */
+ /* Engineering Sample calibration setup. */
if ((rev >> 24) == 0) {
reg = (volatile uint32_t *)0x400CA00C;
*reg &= ~(0x70UL);
@@ -87,7 +87,7 @@ __STATIC_INLINE void CHIP_Init(void)
/* DREG */
reg = (volatile uint32_t *)0x400C6020;
*reg &= ~(0x00001F80UL);
- /* Update CMU reset values */
+ /* Update CMU reset values. */
reg = (volatile uint32_t *)0x400C8040;
*reg = 0;
reg = (volatile uint32_t *)0x400C8044;
@@ -102,31 +102,31 @@ __STATIC_INLINE void CHIP_Init(void)
SYSTEM_ChipRevisionGet(&chipRev);
if (chipRev.major == 0x01) {
- /* Rev A errata handling for EM2/3. Must enable DMA clock in order for EM2/3 */
- /* to work. This will be fixed in later chip revisions, so only do for rev A. */
+ /* Rev A errata handling for EM2/3. Must enable DMA clock to get EM2/3 */
+ /* to work. This will be fixed in later chip revisions and is only needed for rev A. */
if (chipRev.minor == 00) {
reg = (volatile uint32_t *)0x400C8040;
*reg |= 0x2;
}
/* Rev A+B errata handling for I2C when using EM2/3. USART0 clock must be enabled */
- /* after waking up from EM2/EM3 in order for I2C to work. This will be fixed in */
- /* later chip revisions, so only do for rev A+B. */
+ /* after waking up from EM2/EM3 to get I2C to work. This will be fixed in */
+ /* later chip revisions and is only needed for rev A+B. */
if (chipRev.minor <= 0x01) {
reg = (volatile uint32_t *)0x400C8044;
*reg |= 0x1;
}
}
- /* Ensure correct ADC/DAC calibration value */
+ /* Ensure correct ADC/DAC calibration value. */
rev = *(volatile uint32_t *)0x0FE081F0;
if (rev < 0x4C8ABA00) {
uint32_t cal;
- /* Enable ADC/DAC clocks */
+ /* Enable ADC/DAC clocks. */
reg = (volatile uint32_t *)0x400C8044UL;
*reg |= (1 << 14 | 1 << 11);
- /* Retrive calibration values */
+ /* Retrive calibration values. */
cal = ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL)
>> 8) << 24;
@@ -139,16 +139,16 @@ __STATIC_INLINE void CHIP_Init(void)
cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x0000007FUL)
>> 0) << 0;
- /* ADC0->CAL = 1.25 reference */
+ /* ADC0->CAL = 1.25 reference. */
reg = (volatile uint32_t *)0x40002034UL;
*reg = cal;
- /* DAC0->CAL = 1.25 reference */
+ /* DAC0->CAL = 1.25 reference. */
reg = (volatile uint32_t *)(0x4000402CUL);
cal = *(volatile uint32_t *)0x0FE081C8UL;
*reg = cal;
- /* Turn off ADC/DAC clocks */
+ /* Turn off ADC/DAC clocks. */
reg = (volatile uint32_t *)0x400C8044UL;
*reg &= ~(1 << 14 | 1 << 11);
}
@@ -165,7 +165,9 @@ __STATIC_INLINE void CHIP_Init(void)
prodRev = SYSTEM_GetProdRev();
SYSTEM_ChipRevisionGet(&chipRev);
- if ((prodRev >= 16) && (chipRev.minor >= 3)) {
+ // All Giant and Leopard parts except Leopard Rev E
+ if ((prodRev >= 16) && (chipRev.minor >= 3)
+ && !((chipRev.major == 2) && (chipRev.minor == 4))) {
/* This fixes an issue with the LFXO on high temperatures. */
*(volatile uint32_t*)0x400C80C0 =
(*(volatile uint32_t*)0x400C80C0 & ~(1 << 6) ) | (1 << 4);
@@ -178,10 +180,10 @@ __STATIC_INLINE void CHIP_Init(void)
prodRev = SYSTEM_GetProdRev();
if (prodRev <= 129) {
- /* This fixes a mistaken internal connection between PC0 and PC4 */
- /* This disables an internal pulldown on PC4 */
+ /* This fixes a mistaken internal connection between PC0 and PC4. */
+ /* This disables an internal pull-down on PC4. */
*(volatile uint32_t*)(0x400C6018) = (1 << 26) | (5 << 0);
- /* This disables an internal LDO test signal driving PC4 */
+ /* This disables an internal LDO test signal driving PC4. */
*(volatile uint32_t*)(0x400C80E4) &= ~(1 << 24);
}
#endif
@@ -190,7 +192,7 @@ __STATIC_INLINE void CHIP_Init(void)
/****************************
* Fixes for errata GPIO_E201 (slewrate) and
- * HFXO high temperature oscillator startup robustness fix */
+ * HFXO high-temperature oscillator startup robustness fix. */
uint32_t port;
uint32_t clkEn;
@@ -207,13 +209,13 @@ __STATIC_INLINE void CHIP_Init(void)
/* This errata is fixed in hardware from PRODREV 0x8F. */
if (prodRev < 0x8F) {
- /* Fixes for errata GPIO_E201 (slewrate) */
+ /* Fixes for errata GPIO_E201 (slewrate). */
/* Save HFBUSCLK enable state and enable GPIO clock. */
clkEn = CMU->HFBUSCLKEN0;
CMU->HFBUSCLKEN0 = clkEn | CMU_HFBUSCLKEN0_GPIO;
- /* Update slewrate */
+ /* Update slewrate. */
for (port = 0; port <= GPIO_PORT_MAX; port++) {
GPIO->P[port].CTRL = setVal | resetVal;
}
@@ -224,7 +226,7 @@ __STATIC_INLINE void CHIP_Init(void)
/* This errata is fixed in hardware from PRODREV 0x90. */
if (prodRev < 0x90) {
- /* HFXO high temperature oscillator startup robustness fix */
+ /* HFXO high-temperature oscillator startup robustness fix. */
CMU->HFXOSTARTUPCTRL =
(CMU->HFXOSTARTUPCTRL & ~_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK)
| (0x20 << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT);
@@ -235,20 +237,18 @@ __STATIC_INLINE void CHIP_Init(void)
*(volatile uint32_t *)(EMU_BASE + 0x164) |= 0x4;
}
-#if defined(_EFR_DEVICE)
/****************************
- * Fix for errata DCDC_E206
+ * Fix for errata DCDC_E206.
* Disable bypass limit enabled temporarily in SystemInit() errata
* workaround. */
BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0);
#endif
-#endif
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
uint8_t prodRev = SYSTEM_GetProdRev();
- /* EM2 current fixes for early samples */
+ /* EM2 current fixes for early samples. */
if (prodRev == 0U) {
*(volatile uint32_t *)(EMU_BASE + 0x190UL) = 0x0000ADE8UL;
*(volatile uint32_t *)(EMU_BASE + 0x198UL) |= (0x1UL << 2);
@@ -258,37 +258,192 @@ __STATIC_INLINE void CHIP_Init(void)
*(volatile uint32_t *)(EMU_BASE + 0x164UL) |= (0x1UL << 13);
}
- /* Set optimal LFRCOCTRL VREFUPDATE and enable duty cycling of vref */
+ /* Set optimal LFRCOCTRL VREFUPDATE and enable duty cycling of VREF. */
CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~_CMU_LFRCOCTRL_VREFUPDATE_MASK)
| CMU_LFRCOCTRL_VREFUPDATE_64CYCLES
| CMU_LFRCOCTRL_ENVREF;
#endif
-#if defined(_EFR_DEVICE) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 84)
+#if defined(_SILICON_LABS_32B_SERIES_1) \
+ && defined(_EFR_DEVICE) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 84)
MSC->CTRL |= 0x1UL << 8;
#endif
- /* Set validated PLFRCO trims for production revision < 5. Overwriting registers
- for all production revisions is safe. */
-#if defined(_SILICON_LABS_32B_SERIES_1) && defined(_CMU_STATUS_PLFRCOENS_MASK)
- *(volatile uint32_t *)(CMU_BASE + 0x28C) = 0x258;
- *(volatile uint32_t *)(CMU_BASE + 0x290) = 0x55D4A;
- *(volatile uint32_t *)(CMU_BASE + 0x2FC) = 0x16E228;
- *(volatile uint32_t *)(CMU_BASE + 0x294) = 0x1E0;
+#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89)
+ SYSTEM_ChipRevision_TypeDef chipRev;
+ SYSTEM_ChipRevisionGet(&chipRev);
+
+ if ((chipRev.major > 1) || (chipRev.minor >= 3)) {
+ /* PLFRCO trim values */
+ *(volatile uint32_t *)(CMU_BASE + 0x28CUL) = 608;
+ *(volatile uint32_t *)(CMU_BASE + 0x290UL) = 356250;
+ *(volatile uint32_t *)(CMU_BASE + 0x2F0UL) = 0x04000118;
+ *(volatile uint32_t *)(CMU_BASE + 0x2F8UL) = 0x08328400;
+ }
#endif
-/* Charge redist setup (fixed value): LCD->DBGCTRL.CHGRDSTSTR = 1 (reset: 0) */
+/* Charge redist setup (fixed value): LCD->DBGCTRL.CHGRDSTSTR = 1 (reset: 0). */
#if defined(_LCD_DISPCTRL_CHGRDST_MASK)
+#if defined(_SILICON_LABS_32B_SERIES_1)
CMU->HFBUSCLKEN0 |= CMU_HFBUSCLKEN0_LE;
CMU->LFACLKEN0 |= CMU_LFACLKEN0_LCD;
*(volatile uint32_t *)(LCD_BASE + 0x034) |= (0x1UL << 12);
CMU->LFACLKEN0 &= ~CMU_LFACLKEN0_LCD;
CMU->HFBUSCLKEN0 &= ~CMU_HFBUSCLKEN0_LE;
#endif
+#endif
+
+#if defined(_SILICON_LABS_32B_SERIES_1) \
+ && !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) \
+ && !defined(ERRATA_FIX_EMU_E220_DECBOD_IGNORE)
+ /* First part of the EMU_E220 DECBOD Errata fix. DECBOD Reset can occur
+ * during voltage scaling after EM2/3 wakeup. Second part is in em_emu.c */
+ *(volatile uint32_t *)(EMU_BASE + 0x1A4) |= 0x1f << 10;
+#endif
+
+#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_200)
+ SYSTEM_ChipRevision_TypeDef chipRev;
+ SYSTEM_ChipRevisionGet(&chipRev);
+
+ if ((HFXO0->STATUS & HFXO_STATUS_ENS) == 0U) {
+ /* Change HFXO default peak detector settings. */
+ *(volatile uint32_t*)(HFXO0_BASE + 0x34U) =
+ (*(volatile uint32_t*)(HFXO0_BASE + 0x34U) & 0xFF8000FFU)
+ | 0x00178500U;
+ /* Change HFXO low power control settings. */
+ *(volatile uint32_t*)(HFXO0_BASE + 0x30U) =
+ (*(volatile uint32_t*)(HFXO0_BASE + 0x30U) & 0xFFFF0FFFU)
+ | 0x0000C000U;
+ /* Change default SQBUF bias current. */
+ *(volatile uint32_t*)(HFXO0_BASE + 0x30U) |= 0x700;
+ }
+
+ if (chipRev.major == 0x01 && chipRev.minor == 0x0) {
+ /* Trigger RAM read for each RAM instance */
+ volatile uint32_t *dmem = (volatile uint32_t *) DMEM_RAM0_RAM_MEM_BASE;
+ for (uint32_t i = 0U; i < DMEM_NUM_BANK; i++) {
+ // Force memory read
+ *dmem;
+ dmem += (DMEM_BANK0_SIZE / 4U);
+ }
+ }
+
+ /* Set TRACE clock to intended reset value. */
+ CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK)
+ | CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23;
+#endif
+
+#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205)
+ if (SYSTEM_GetProdRev() == 1) {
+ bool hfrcoClkIsOff = (CMU->CLKEN0 & CMU_CLKEN0_HFRCO0) == 0;
+ CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0;
+ /* Enable HFRCO CLKOUT0. */
+ *(volatile uint32_t*)(0x40012020UL) = 0x4UL;
+ if (hfrcoClkIsOff) {
+ CMU->CLKEN0_CLR = CMU_CLKEN0_HFRCO0;
+ }
+ }
+#endif
+
+/* PM-3503 */
+#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_210)
+ {
+ bool syscfgClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) == 0);
+ CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG;
+
+ bool dcdcClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_DCDC) == 0);
+ CMU->CLKEN0_SET = CMU_CLKEN0_DCDC;
+
+ bool dcdcIsLock = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK_LOCKED) != 0);
+ DCDC->LOCK = DCDC_LOCK_LOCKKEY_UNLOCKKEY;
+
+ while (DCDC->SYNCBUSY & DCDC_SYNCBUSY_CTRL) {
+ /* Wait for previous synchronization to finish */
+ }
+ DCDC->CTRL_CLR = DCDC_CTRL_MODE;
+ while ((DCDC->STATUS & DCDC_STATUS_BYPSW) == 0U) {
+ /* Wait for BYPASS switch enable. */
+ }
+
+ if ((SYSCFG->ROOTLOCKSTATUS & SYSCFG_ROOTLOCKSTATUS_REGLOCK) == 0) {
+ *(volatile uint32_t *)(DCDC_BASE + 0x205CUL) = (0x1UL << 18);
+ }
+
+ if (dcdcIsLock) {
+ DCDC->LOCK = ~DCDC_LOCK_LOCKKEY_UNLOCKKEY;
+ }
+ if (dcdcClkIsOff) {
+ CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC;
+ }
+ if (syscfgClkIsOff) {
+ CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG;
+ }
+ }
+#endif
+
+/* PM-5163 */
+#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_215) \
+ && defined(_SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT) \
+ && (_SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM == 20)
+ SYSTEM_ChipRevision_TypeDef chipRev;
+ SYSTEM_ChipRevisionGet(&chipRev);
+
+ if (chipRev.major == 0x01 && chipRev.minor == 0x00) {
+ bool hfxo0ClkIsOff = (CMU->CLKEN0 & CMU_CLKEN0_HFXO0) == 0;
+ CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0;
+
+ *(volatile uint32_t*)(HFXO0_BASE + 0x0034UL) =
+ (*(volatile uint32_t*)(HFXO0_BASE + 0x0034UL) & 0xE3FFFFFFUL)
+ | 0x0C000000UL;
+
+ if (hfxo0ClkIsOff) {
+ CMU->CLKEN0_CLR = CMU_CLKEN0_HFXO0;
+ }
+ }
+#endif
+}
+
+/**************************************************************************//**
+ * @brief
+ * Chip reset routine with errata workarounds.
+ *
+ * @note
+ * This function should be called to reset the chip. It does not return.
+ *
+ * This function applies any errata workarounds needed to cleanly reset the
+ * device and then performs a system reset. See the device-specific errata for
+ * details.
+ *****************************************************************************/
+__STATIC_INLINE void CHIP_Reset(void)
+{
+#if defined(_EFR_DEVICE) && defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
+ /****************************
+ * Workaround for errata DCDC_E206.
+ * Disable radio interference minimization features when resetting */
+
+ // Ensure access to EMU registers
+ EMU->LOCK = EMU_LOCK_LOCKKEY_UNLOCK;
+ EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_LOCK;
+
+ // No need to do anything if the DCDC is not powering DVDD
+ if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) == EMU_PWRCFG_PWRCFG_DCDCTODVDD) {
+ // Make sure radio cannot accidentally re-enable features
+ *(volatile uint32_t *)(0x40084040UL) = 0x1UL;
+
+ // If DCDC is in use, disable features
+ uint32_t dcdcMode = EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK;
+ if ((dcdcMode == EMU_DCDCCTRL_DCDCMODE_LOWNOISE)
+ || (dcdcMode == EMU_DCDCCTRL_DCDCMODE_LOWPOWER)) {
+ BUS_RegBitWrite((volatile uint32_t *)(0x400E3060UL), 28UL, 0);
+ BUS_RegBitWrite((volatile uint32_t *)(0x400E3074UL), 0, 0);
+ }
+ }
+#endif
+
+ NVIC_SystemReset();
}
-/** @} (end addtogroup CHIP) */
-/** @} (end addtogroup emlib) */
+/** @} (end addtogroup chip) */
#ifdef __cplusplus
}
diff --git a/mcu/efr/common/vendor/em_device.h b/mcu/efr/common/vendor/em_device.h
index b338d08e..bf76d3d2 100644
--- a/mcu/efr/common/vendor/em_device.h
+++ b/mcu/efr/common/vendor/em_device.h
@@ -7,11 +7,8 @@
#ifndef EM_DEVICE_H_
#define EM_DEVICE_H_
-#if defined(EFR32FG13)
-#include "efr32fg13/em_device_fg13.h"
-#define GPIO_PORT_MAX 5
-#elif defined(EFR32FG12)
-#include "efr32fg12/em_device_fg12.h"
+#if defined(EFR32FG12)
+#include "efr32fg12/Include/em_device.h"
#define GPIO_PORT_MAX 10
#elif defined(EFR32MG21)
#include "efr32mg21/Include/em_device.h"
@@ -22,6 +19,11 @@
#elif defined(EFR32FG23)
#include "efr32fg23/Include/em_device.h"
#define GPIO_PORT_MAX 3
+#define __SYSTEM_CLOCK (39000000UL)
+#elif defined(EFR32MG24)
+#include "efr32mg24/Include/em_device.h"
+#define GPIO_PORT_MAX 3
+#define __SYSTEM_CLOCK (39000000UL)
#else
#error "em_device.h: Unknown EFR32 PART"
#endif
diff --git a/mcu/efr/common/vendor/em_eusart.c b/mcu/efr/common/vendor/em_eusart.c
new file mode 100644
index 00000000..a7ed6b07
--- /dev/null
+++ b/mcu/efr/common/vendor/em_eusart.c
@@ -0,0 +1,1345 @@
+/***************************************************************************//**
+ * @file
+ * @brief Universal asynchronous receiver/transmitter (EUSART) peripheral API
+ *******************************************************************************
+ * # License
+ * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#include "em_eusart.h"
+#if defined(EUART_PRESENT) || defined(EUSART_PRESENT)
+#include "em_cmu.h"
+#include
+
+/*******************************************************************************
+ ********************************* DEFINES *********************************
+ ******************************************************************************/
+
+#if defined(EUART_PRESENT)
+ #define EUSART_REF_VALID(ref) ((ref) == EUART0)
+ #define EUSART_EM2_CAPABLE(ref) (true)
+ #define EUSART_RX_FIFO_SIZE 4u
+#elif defined(EUSART_PRESENT)
+ #define EUSART_REF_VALID(ref) (EUSART_NUM(ref) != -1)
+ #define EUSART_RX_FIFO_SIZE 16u
+#endif
+
+/*******************************************************************************
+ ************************** LOCAL VARIABLES ********************************
+ ******************************************************************************/
+#if defined(EUSART_DALICFG_DALIEN)
+static uint8_t dali_tx_nb_packets[EUSART_COUNT];
+static uint8_t dali_rx_nb_packets[EUSART_COUNT];
+#endif /* EUSART_DALICFG_DALIEN */
+
+/*******************************************************************************
+ ************************** LOCAL FUNCTIONS ********************************
+ ******************************************************************************/
+
+static CMU_Clock_TypeDef EUSART_ClockGet(EUSART_TypeDef *eusart);
+
+static void EUSART_AsyncInitCommon(EUSART_TypeDef *eusart,
+ const EUSART_UartInit_TypeDef *init,
+ const EUSART_IrDAInit_TypeDef *irdaInit,
+ const EUSART_DaliInit_TypeDef *daliInit);
+
+#if defined(EUSART_PRESENT)
+static void EUSART_SyncInitCommon(EUSART_TypeDef *eusart,
+ const EUSART_SpiInit_TypeDef *init);
+#endif
+
+/***************************************************************************//**
+ * Wait for ongoing sync of register(s) to the low-frequency domain to complete.
+ *
+ * @param eusart Pointer to the EUSART peripheral register block.
+ * @param mask A bitmask corresponding to SYNCBUSY register defined bits,
+ * indicating registers that must complete any ongoing
+ * synchronization.
+ ******************************************************************************/
+__STATIC_INLINE void eusart_sync(EUSART_TypeDef *eusart, uint32_t mask)
+{
+ // Wait for any pending previous write operation to have been completed
+ // in the low-frequency domain.
+ while ((eusart->SYNCBUSY & mask) != 0U) {
+ }
+}
+
+/***************************************************************************//**
+ * Calculate baudrate for a given reference frequency, clock division,
+ * and oversampling rate.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t EUSART_AsyncBaudrateCalc(uint32_t refFreq,
+ uint32_t clkdiv,
+ EUSART_OVS_TypeDef ovs);
+
+/***************************************************************************//**
+ * Execute the EUSART peripheral disabling sequence.
+ ******************************************************************************/
+__STATIC_INLINE void EUSART_Disable(EUSART_TypeDef *eusart);
+
+/*******************************************************************************
+ ************************** GLOBAL FUNCTIONS *******************************
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * Initializes the EUSART when used with the high frequency clock.
+ ******************************************************************************/
+void EUSART_UartInitHf(EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init)
+{
+ // Make sure the module exists on the selected chip.
+ EFM_ASSERT(EUSART_REF_VALID(eusart));
+ // Init structure must be provided.
+ EFM_ASSERT(init);
+
+ // Assert features specific to HF.
+ // The oversampling must not be disabled when using a high frequency clock.
+ EFM_ASSERT(init->oversampling != eusartOVS0);
+
+ // Uart mode only supports up to 9 databits frame.
+ EFM_ASSERT(init->databits <= eusartDataBits9);
+
+ // Initialize EUSART with common features to HF and LF.
+ EUSART_AsyncInitCommon(eusart, init, NULL, NULL);
+}
+
+/***************************************************************************//**
+ * Initializes the EUSART when used with the low frequency clock.
+ *
+ * @note (1) When EUSART oversampling is set to eusartOVS0 (Disable), the peripheral
+ * clock frequency must be at least three times higher than the
+ * chosen baud rate. In LF, max input clock is 32768 (LFXO or LFRCO),
+ * thus 32768 / 3 ~ 9600 baudrate.
+ ******************************************************************************/
+void EUSART_UartInitLf(EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init)
+{
+ // Make sure the module exists and is Low frequency capable.
+ EFM_ASSERT(EUSART_REF_VALID(eusart) && EUSART_EM2_CAPABLE(EUSART_NUM(eusart)));
+ // Init structure must be provided.
+ EFM_ASSERT(init);
+
+ // Assert features specific to LF.
+ // LFXO, LFRCO, ULFRCO can be a clock source in LF.
+#if defined(DEBUG_EFM) || defined(DEBUG_EFM_USER)
+ {
+ CMU_Select_TypeDef clock_source = (CMU_Select_TypeDef) NULL;
+#if defined(EUART_PRESENT)
+ if (eusart == EUART0) {
+ clock_source = CMU_ClockSelectGet(cmuClock_EUART0);
+ }
+#endif
+#if defined(EUSART_PRESENT) && defined(EUSART0)
+ if (eusart == EUSART0) {
+ clock_source = CMU_ClockSelectGet(cmuClock_EUSART0);
+ }
+#endif
+ EFM_ASSERT((clock_source == cmuSelect_LFRCO) || (clock_source == cmuSelect_ULFRCO) || (clock_source == cmuSelect_LFXO));
+ }
+#endif
+ // Uart mode only supports up to 9 databits frame.
+ EFM_ASSERT(init->databits <= eusartDataBits9);
+ // The oversampling must be disabled when using a low frequency clock.
+ EFM_ASSERT(init->oversampling == eusartOVS0);
+ // The Majority Vote must be disabled when using a low frequency clock.
+ EFM_ASSERT(init->majorityVote == eusartMajorityVoteDisable);
+ // Number of stop bits can only be 1 or 2 in LF.
+ EFM_ASSERT((init->stopbits == eusartStopbits1) || (init->stopbits == eusartStopbits2));
+ // In LF, max baudrate is 9600. See Note #1.
+ EFM_ASSERT(init->baudrate <= 9600 && init->baudrate != 0);
+
+ // Initialize EUSART with common features to HF and LF.
+ EUSART_AsyncInitCommon(eusart, init, NULL, NULL);
+}
+
+/***************************************************************************//**
+ * Initializes the EUSART when used in IrDA mode with the high or low
+ * frequency clock.
+ ******************************************************************************/
+void EUSART_IrDAInit(EUSART_TypeDef *eusart,
+ const EUSART_IrDAInit_TypeDef *irdaInit)
+{
+ // Make sure the module exists on the selected chip.
+ EFM_ASSERT(EUSART_REF_VALID(eusart));
+ // Init structure must be provided.
+ EFM_ASSERT(irdaInit);
+
+ if (irdaInit->irDALowFrequencyEnable) {
+ // Validate the low frequency capability of the EUSART instance.
+ EFM_ASSERT(EUSART_EM2_CAPABLE(EUSART_NUM(eusart)));
+ // The oversampling must be disabled when using a low frequency clock.
+ EFM_ASSERT(irdaInit->init.oversampling == eusartOVS0);
+ // Number of stop bits can only be 1 or 2 in LF.
+ EFM_ASSERT((irdaInit->init.stopbits == eusartStopbits1) || (irdaInit->init.stopbits == eusartStopbits2));
+ // In LF, max baudrate is 9600. See Note #1.
+ EFM_ASSERT(irdaInit->init.baudrate <= 9600);
+ EFM_ASSERT(irdaInit->init.enable == eusartEnableRx || irdaInit->init.enable == eusartDisable);
+ } else {
+ EFM_ASSERT(irdaInit->init.oversampling != eusartOVS0);
+ // In HF, 2.4 kbps <= baudrate <= 1.152 Mbps.
+ EFM_ASSERT(irdaInit->init.baudrate >= 2400 && irdaInit->init.baudrate <= 1152000);
+ }
+
+ // Initialize EUSART with common features to HF and LF.
+ EUSART_AsyncInitCommon(eusart, &irdaInit->init, irdaInit, NULL);
+}
+
+#if defined(EUSART_PRESENT)
+/***************************************************************************//**
+ * Initializes the EUSART when used in SPI mode.
+ ******************************************************************************/
+void EUSART_SpiInit(EUSART_TypeDef *eusart, EUSART_SpiInit_TypeDef const *init)
+{
+ // Make sure the module exists on the selected chip.
+ EFM_ASSERT(EUSART_REF_VALID(eusart));
+ // Init structure must be provided.
+ EFM_ASSERT(init);
+ if (init->master) {
+ EFM_ASSERT(init->bitRate <= 20000000);
+
+ if (init->advancedSettings) {
+ EFM_ASSERT(!(init->advancedSettings->prsClockEnable));
+ }
+ } else {
+ EFM_ASSERT(init->bitRate <= 10000000);
+
+ if (init->advancedSettings && init->advancedSettings->forceLoad) {
+ // If baud-rate is more than 5MHz, a value of 4 is recommended, any values
+ // smaller than that can be tried out but avoid using 0. If baud-rate is less than 5MHz,
+ // value of 5 is recommended, values higher than 5 can be used but it may make the load
+ // error easy to occur. The recommended values for frequency bands should be sufficient
+ // to work all the time.
+ EFM_ASSERT((init->bitRate >= 5000000 && init->advancedSettings->setupWindow <= 4)
+ || (init->bitRate < 5000000 && init->advancedSettings->setupWindow >= 5));
+ }
+ }
+
+ EUSART_SyncInitCommon(eusart, init);
+}
+
+#if defined(EUSART_DALICFG_DALIEN)
+/***************************************************************************//**
+ * Initializes the EUSART when used in DALI mode with the high or low
+ * frequency clock.
+ *
+ * @note (1) When EUSART oversampling is set to eusartOVS0 (Disable), the peripheral
+ * clock frequency must be at least three times higher than the
+ * chosen baud rate. In LF, max input clock is 32768 (LFXO or LFRCO),
+ * thus 32768 / 3 ~ 9600 baudrate.
+ ******************************************************************************/
+void EUSART_DaliInit(EUSART_TypeDef *eusart,
+ const EUSART_DaliInit_TypeDef *daliInit)
+{
+ // Make sure the module exists on the selected chip.
+ EFM_ASSERT(EUSART_REF_VALID(eusart));
+ // Init structure must be provided.
+ EFM_ASSERT(daliInit);
+
+ if (daliInit->init.loopbackEnable) {
+ // If LOOPBK in CFG0 is set to 1 in order to do loopback testing for DALI,
+ // then in this case DALIRXENDT should be set to 1 and DALIRXDATABITS should
+ // be set the same as DALITXDATABITS.
+ EFM_ASSERT( (daliInit->TXdatabits >> _EUSART_DALICFG_DALITXDATABITS_SHIFT)
+ == (daliInit->RXdatabits >> _EUSART_DALICFG_DALIRXDATABITS_SHIFT));
+ }
+
+ if (daliInit->daliLowFrequencyEnable) {
+ // Validate the low frequency capability of the EUSART instance.
+ EFM_ASSERT(EUSART_EM2_CAPABLE(EUSART_NUM(eusart)));
+ // The oversampling must be disabled when using a low frequency clock.
+ EFM_ASSERT(daliInit->init.oversampling == eusartOVS0);
+ // In LF, max baudrate is 9600. See Note #1.
+ // but manchester is running at 2x clock 9600 => 4800
+ EFM_ASSERT(daliInit->init.baudrate <= 4800);
+ } else {
+ EFM_ASSERT(daliInit->init.oversampling != eusartOVS0);
+ // In HF, 2.4 kbps <= baudrate <= 1.152 Mbps.
+ // but manchester is running at 2x clock so 2.4 kbps => 1.2 kbps
+ EFM_ASSERT(daliInit->init.baudrate >= 1200 && daliInit->init.baudrate <= 57600);
+ }
+
+ // Initialize EUSART with common features to HF and LF.
+ EUSART_AsyncInitCommon(eusart, &daliInit->init, NULL, daliInit);
+}
+#endif /* EUSART_DALICFG_DALIEN */
+#endif /* EUSART_PRESENT */
+
+/***************************************************************************//**
+ * Configure the EUSART to its reset state.
+ ******************************************************************************/
+void EUSART_Reset(EUSART_TypeDef *eusart)
+{
+ // 1. Properly disable the module
+ EUSART_Disable(eusart);
+
+#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \
+ || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \
+ || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5)
+ // Manual toggling tx_sclk_mst to synchronize handshake
+ // when switching from SPI master to other modes
+ // so module is disabling correctly.
+ uint32_t forcedClkCycle = 4u;
+
+ while (forcedClkCycle--) {
+ eusart->CFG2_SET = _EUSART_CFG2_CLKPHA_MASK;
+ eusart->CFG2_CLR = _EUSART_CFG2_CLKPHA_MASK;
+ }
+#endif
+ // All registers that end with CFG should be programmed before EUSART gets enabled (EUSARTn_EN is set).
+ // Set all configurable register to its reset value.
+ // Note: Program desired settings to all registers that have names ending with CFG in the following sequence:
+ // a. CFG2
+#if defined(EUSART_PRESENT)
+ eusart->CFG2 = _EUSART_CFG2_RESETVALUE;
+#endif
+ // b. CFG1
+ eusart->CFG1 = _EUSART_CFG1_RESETVALUE;
+ // c. CFG0
+ eusart->CFG0 = _EUSART_CFG0_RESETVALUE;
+ // d. FRAMECFG, DTXDATCFG, TIMINGCFG (Any sequence)
+ eusart->FRAMECFG = _EUSART_FRAMECFG_RESETVALUE;
+#if defined(EUSART_PRESENT)
+ eusart->DTXDATCFG = _EUSART_DTXDATCFG_RESETVALUE;
+#if defined(EUSART_DALICFG_DALIEN)
+ eusart->DALICFG = _EUSART_DALICFG_RESETVALUE;
+#endif /* EUSART_DALICFG_DALIEN */
+#endif /* EUSART_PRESENT */
+ eusart->TIMINGCFG = _EUSART_TIMINGCFG_RESETVALUE;
+ eusart->IRHFCFG = _EUSART_IRHFCFG_RESETVALUE;
+ eusart->IRLFCFG = _EUSART_IRLFCFG_RESETVALUE;
+ eusart->STARTFRAMECFG = _EUSART_STARTFRAMECFG_RESETVALUE;
+ eusart->SIGFRAMECFG = _EUSART_SIGFRAMECFG_RESETVALUE;
+ eusart->TRIGCTRL = _EUSART_TRIGCTRL_RESETVALUE;
+ eusart->IEN = _EUSART_IEN_RESETVALUE;
+ eusart->IF_CLR = _EUSART_IF_MASK;
+
+ // no need to sync while EN=0, multiple writes can be queued up,
+ // and the last one will synchronize once EN=1
+ eusart->CLKDIV = _EUSART_CLKDIV_RESETVALUE;
+}
+
+/***************************************************************************//**
+ * Enables/disables the EUSART receiver and/or transmitter.
+ ******************************************************************************/
+void EUSART_Enable(EUSART_TypeDef *eusart, EUSART_Enable_TypeDef enable)
+{
+ uint32_t tmp = 0;
+
+ // Make sure that the module exists on the selected chip.
+ EFM_ASSERT(EUSART_REF_VALID(eusart));
+
+ if (enable == eusartDisable) {
+ EUSART_Disable(eusart);
+ } else {
+ // Enable peripheral to configure Rx and Tx.
+ eusart->EN_SET = EUSART_EN_EN;
+
+ // Enable or disable Rx and/or Tx
+ tmp = (enable)
+ & (_EUSART_CMD_RXEN_MASK | _EUSART_CMD_TXEN_MASK
+ | _EUSART_CMD_RXDIS_MASK | _EUSART_CMD_TXDIS_MASK);
+
+ eusart_sync(eusart, _EUSART_SYNCBUSY_MASK);
+ eusart->CMD = tmp;
+ eusart_sync(eusart,
+ EUSART_SYNCBUSY_RXEN | EUSART_SYNCBUSY_TXEN
+ | EUSART_SYNCBUSY_RXDIS | EUSART_SYNCBUSY_TXDIS);
+
+ // Wait for the status register to be updated.
+ tmp = 0;
+ if (_EUSART_CMD_RXEN_MASK & enable) {
+ tmp |= EUSART_STATUS_RXENS;
+ }
+ if (_EUSART_CMD_TXEN_MASK & enable) {
+ tmp |= EUSART_STATUS_TXENS;
+ }
+ while ((eusart->STATUS & (_EUSART_STATUS_TXENS_MASK | _EUSART_STATUS_RXENS_MASK)) != tmp) {
+ }
+ }
+}
+
+/***************************************************************************//**
+ * Receives one 8 bit frame, (or part of 9 bit frame).
+ ******************************************************************************/
+uint8_t EUSART_Rx(EUSART_TypeDef *eusart)
+{
+ while (!(eusart->STATUS & EUSART_STATUS_RXFL)) {
+ } // Wait for incoming data.
+
+ return (uint8_t)eusart->RXDATA;
+}
+
+/***************************************************************************//**
+ * Receives one 8-9 bit frame with extended information.
+ ******************************************************************************/
+uint16_t EUSART_RxExt(EUSART_TypeDef *eusart)
+{
+ while (!(eusart->STATUS & EUSART_STATUS_RXFL)) {
+ } // Wait for incoming data.
+
+ return (uint16_t)eusart->RXDATA;
+}
+
+/***************************************************************************//**
+ * Transmits one frame.
+ ******************************************************************************/
+void EUSART_Tx(EUSART_TypeDef *eusart, uint8_t data)
+{
+ // Check that transmit FIFO is not full.
+ while (!(eusart->STATUS & EUSART_STATUS_TXFL)) {
+ }
+
+ eusart->TXDATA = (uint32_t)data;
+}
+
+/***************************************************************************//**
+ * Transmits one 8-9 bit frame with extended control.
+ ******************************************************************************/
+void EUSART_TxExt(EUSART_TypeDef *eusart, uint16_t data)
+{
+ // Check that transmit FIFO is not full.
+ while (!(eusart->STATUS & EUSART_STATUS_TXFL)) {
+ }
+
+ eusart->TXDATA = (uint32_t)data;
+}
+
+#if defined(EUSART_PRESENT)
+/***************************************************************************//**
+ * Transmits one 8-16 bit frame and return received data.
+ ******************************************************************************/
+uint16_t EUSART_Spi_TxRx(EUSART_TypeDef *eusart, uint16_t data)
+{
+ // Check that transmit FIFO is not full.
+ while (!(eusart->STATUS & EUSART_STATUS_TXFL)) {
+ }
+ eusart->TXDATA = (uint32_t)data;
+
+ // Wait for Rx data to be available.
+ while (!(eusart->STATUS & EUSART_STATUS_RXFL)) {
+ }
+ return (uint16_t)eusart->RXDATA;
+}
+
+#if defined(EUSART_DALICFG_DALIEN)
+/***************************************************************************//**
+ * Transmits one frame.
+ ******************************************************************************/
+void EUSART_Dali_Tx(EUSART_TypeDef *eusart, uint32_t data)
+{
+ uint32_t packet;
+
+ // Make sure the module exists on the selected chip.
+ EFM_ASSERT(EUSART_REF_VALID(eusart));
+
+ // Check that transmit FIFO is not full.
+ while (!(eusart->STATUS & EUSART_STATUS_TXFL)) {
+ }
+
+ for (uint8_t index = 0; index < dali_tx_nb_packets[EUSART_NUM(eusart)]; index++) {
+ // when DALICFG.DALIEN is set to 1, then all 16 bits [15:0] represent data
+ // First write to TXDATA register should contain 16 LSBs of the TX frame.
+ // Transmission will not start after this first write.
+ // Second write to TXDATA register should contain the remaining TX frame bits.
+ // This second write will result in start of transmission.
+ packet = (data >> (index * 16));
+ // To ensure compatibility with future devices, always write bits [31:16] to 0.
+ packet &= 0x0000FFFF;
+ eusart->TXDATA = packet;
+ }
+}
+
+/***************************************************************************//**
+ * Receive one frame.
+ ******************************************************************************/
+uint32_t EUSART_Dali_Rx(EUSART_TypeDef *eusart)
+{
+ uint32_t data = 0;
+
+ // Make sure the module exists on the selected chip.
+ EFM_ASSERT(EUSART_REF_VALID(eusart));
+
+ while (!(eusart->STATUS & EUSART_STATUS_RXFL)) {
+ } // Wait for incoming data.
+
+ for (uint8_t index = 0; index < dali_rx_nb_packets[EUSART_NUM(eusart)]; index++) {
+ // when DALICFG.DALIEN is set to 1, then all 16 bits [15:0] represent data
+ // When receiving a frame that has more than 16 databits,
+ // RXDATA register needs to be read twice:
+ // First read will provide 16 LSBs of the received frame.
+ // Second read will provide the remaining RX frame bits.
+ data |= ((eusart->RXDATA & _EUSART_RXDATA_RXDATA_MASK) << (index * 16));
+ }
+ return data;
+}
+
+#endif /* EUSART_DALICFG_DALIEN */
+#endif /* EUSART_PRESENT */
+
+/***************************************************************************//**
+ * Configures the baudrate (or as close as possible to a specified baudrate)
+ * depending on the current mode of the EU(S)ART peripheral.
+ *
+ * @note (1) When the oversampling is disabled, the peripheral clock frequency
+ * must be at least three times higher than the chosen baud rate.
+ ******************************************************************************/
+void EUSART_BaudrateSet(EUSART_TypeDef *eusart,
+ uint32_t refFreq,
+ uint32_t baudrate)
+{
+ uint32_t clkdiv;
+ uint8_t oversample = 0;
+
+ // Prevent dividing by 0.
+ EFM_ASSERT(baudrate);
+
+ // Make sure the module exists on the selected chip.
+ EFM_ASSERT(EUSART_REF_VALID(eusart));
+
+ // Get the current frequency.
+ if (!refFreq) {
+ refFreq = CMU_ClockFreqGet(EUSART_ClockGet(eusart));
+ }
+
+#if defined(EUSART_PRESENT)
+ // In synchronous mode (ex: SPI)
+ if (eusart->CFG0 & _EUSART_CFG0_SYNC_MASK ) {
+ EFM_ASSERT(baudrate <= refFreq);
+
+ EUSART_Enable_TypeDef txrxEnStatus = eusartDisable;
+ bool wasEnabled = (eusart->EN & _EUSART_EN_EN_MASK) == true;
+ clkdiv = refFreq / baudrate - 1UL;
+
+ // If the desired bit rate requires a divider larger than the Synchronous divider bitfield (CFG2_SDIV),
+ // the resulting spi master bus clock will be undefined because the result will be truncated.
+ EFM_ASSERT(clkdiv <= (_EUSART_CFG2_SDIV_MASK >> _EUSART_CFG2_SDIV_SHIFT));
+
+ if (wasEnabled) {
+ eusart_sync(eusart, _EUSART_SYNCBUSY_RXEN_MASK | _EUSART_SYNCBUSY_TXEN_MASK);
+
+ // Save the state of the reveiver and transmitter before disabling the peripheral.
+ if (eusart->STATUS & (_EUSART_STATUS_RXENS_MASK | _EUSART_STATUS_TXENS_MASK)) {
+ txrxEnStatus = eusartEnable;
+ } else if (eusart->STATUS & (_EUSART_STATUS_RXENS_MASK)) {
+ txrxEnStatus = eusartEnableRx;
+ } else if (eusart->STATUS & (_EUSART_STATUS_TXENS_MASK)) {
+ txrxEnStatus = eusartEnableTx;
+ } else {
+ EFM_ASSERT(false);
+ }
+
+ // Disable the eusart to be able to modify the CFG2 register.
+ EUSART_Disable(eusart);
+ }
+
+ // In Synchronous mode the clock divider that is managing the bitRate
+ // is located inside the sdiv bitfield of the CFG2 register instead of
+ // the CLKDIV register combined with the oversample setting for asynchronous mode.
+ eusart->CFG2 = (eusart->CFG2 & ~(_EUSART_CFG2_SDIV_MASK)) | ((clkdiv << _EUSART_CFG2_SDIV_SHIFT) & _EUSART_CFG2_SDIV_MASK);
+
+ if (wasEnabled) {
+ EUSART_Enable(eusart, txrxEnStatus);
+ }
+ } else // In asynchronous mode (ex: UART)
+#endif
+ {
+ // The peripheral must be enabled to configure the baud rate.
+ EFM_ASSERT(eusart->EN == EUSART_EN_EN);
+
+#if defined(EUSART_DALICFG_DALIEN)
+ if (eusart->DALICFG & EUSART_DALICFG_DALIEN) {
+ // adjust for manchester double-clocking scheme
+ baudrate *= 2;
+ }
+#endif
+
+ /*
+ * Use integer division to avoid forcing in float division
+ * utils, and yet keep rounding effect errors to a minimum.
+ *
+ * CLKDIV is given by:
+ *
+ * CLKDIV = 256 * (fUARTn/(oversample * br) - 1)
+ * or
+ * CLKDIV = (256 * fUARTn)/(oversample * br) - 256
+ *
+ * Since fUARTn may be derived from HFCORECLK, consider the overflow when
+ * using integer arithmetic.
+ *
+ * The basic problem with integer division in the above formula is that
+ * the dividend (256 * fUARTn) may become higher than the maximum 32 bit
+ * integer. Yet, the dividend should be evaluated first before dividing
+ * to get as small rounding effects as possible.
+ * Also, harsh restrictions on the maximum fUARTn value should not be made.
+ *
+ * Since the last 3 bits of CLKDIV are don't care, base the
+ * integer arithmetic on the below formula:
+ *
+ * CLKDIV/8 = ((32*fUARTn)/(br * Oversample)) - 32
+ *
+ * and calculate 1/8 of CLKDIV first. This allows for fUARTn
+ * up to 128 MHz without overflowing a 32 bit value.
+ */
+
+ // Map oversampling.
+ switch (eusart->CFG0 & _EUSART_CFG0_OVS_MASK) {
+ case eusartOVS16:
+ EFM_ASSERT(baudrate <= (refFreq / 16));
+ oversample = 16;
+ break;
+
+ case eusartOVS8:
+ EFM_ASSERT(baudrate <= (refFreq / 8));
+ oversample = 8;
+ break;
+
+ case eusartOVS6:
+ EFM_ASSERT(baudrate <= (refFreq / 6));
+ oversample = 6;
+ break;
+
+ case eusartOVS4:
+ EFM_ASSERT(baudrate <= (refFreq / 4));
+ oversample = 4;
+ break;
+
+ case eusartOVS0:
+ EFM_ASSERT(refFreq >= (3 * baudrate)); // See Note #1.
+ oversample = 1;
+ break;
+
+ default:
+ // Invalid input
+ EFM_ASSERT(0);
+ break;
+ }
+
+ if (oversample > 0U) {
+ // Calculate and set the CLKDIV with fractional bits.
+ clkdiv = (32 * refFreq) / (baudrate * oversample);
+ clkdiv -= 32;
+ clkdiv *= 8;
+
+ // Verify that the resulting clock divider is within limits.
+ EFM_ASSERT(clkdiv <= _EUSART_CLKDIV_MASK);
+
+ // If the EFM_ASSERT is not enabled, make sure not to write to reserved bits.
+ clkdiv &= _EUSART_CLKDIV_MASK;
+
+ eusart_sync(eusart, _EUSART_SYNCBUSY_DIV_MASK);
+ eusart->CLKDIV = clkdiv;
+ eusart_sync(eusart, _EUSART_SYNCBUSY_DIV_MASK);
+ }
+ }
+}
+
+/***************************************************************************//**
+ * Gets the current baudrate.
+ ******************************************************************************/
+uint32_t EUSART_BaudrateGet(EUSART_TypeDef *eusart)
+{
+ uint32_t freq;
+ uint32_t div = 1;
+ uint32_t br = 0;
+ EUSART_OVS_TypeDef ovs = eusartOVS0;
+
+ // Make sure the module exists on the selected chip.
+ EFM_ASSERT(EUSART_REF_VALID(eusart));
+
+ freq = CMU_ClockFreqGet(EUSART_ClockGet(eusart));
+
+#if defined(EUSART_PRESENT)
+ // In synchronous mode (ex: SPI)
+ if (eusart->CFG0 & _EUSART_CFG0_SYNC_MASK) {
+ div = (eusart->CFG2 & _EUSART_CFG2_SDIV_MASK) >> _EUSART_CFG2_SDIV_SHIFT;
+ br = freq / (div + 1);
+ }
+ // In asynchronous mode (ex: UART)
+ else
+#endif
+ {
+ div = eusart->CLKDIV;
+ ovs = (EUSART_OVS_TypeDef)(eusart->CFG0 & _EUSART_CFG0_OVS_MASK);
+ br = EUSART_AsyncBaudrateCalc(freq, div, ovs);
+
+#if defined(EUSART_DALICFG_DALIEN)
+ if (eusart->DALICFG & EUSART_DALICFG_DALIEN) {
+ // adjust for manchester double-clocking scheme
+ br /= 2;
+ }
+#endif
+ }
+
+ return br;
+}
+
+/***************************************************************************//**
+ * Enable/Disable reception operations until the configured start frame is
+ * received.
+ ******************************************************************************/
+void EUSART_RxBlock(EUSART_TypeDef *eusart, EUSART_BlockRx_TypeDef enable)
+{
+ uint32_t tmp;
+
+ // Make sure that the module exists on the selected chip.
+ EFM_ASSERT(EUSART_REF_VALID(eusart));
+
+ tmp = ((uint32_t)(enable));
+ tmp &= (_EUSART_CMD_RXBLOCKEN_MASK | _EUSART_CMD_RXBLOCKDIS_MASK);
+
+ eusart_sync(eusart, EUSART_SYNCBUSY_RXBLOCKEN | EUSART_SYNCBUSY_RXBLOCKDIS);
+ eusart->CMD_SET = tmp;
+ eusart_sync(eusart, EUSART_SYNCBUSY_RXBLOCKEN | EUSART_SYNCBUSY_RXBLOCKDIS);
+
+ tmp = 0u;
+ if ((_EUSART_CMD_RXBLOCKEN_MASK & enable) != 0u) {
+ tmp |= EUSART_STATUS_RXBLOCK;
+ }
+ while ((eusart->STATUS & _EUSART_STATUS_RXBLOCK_MASK) != tmp) {
+ } // Wait for the status register to be updated.
+}
+
+/***************************************************************************//**
+ * Enables/Disables the tristating of the transmitter output.
+ ******************************************************************************/
+void EUSART_TxTristateSet(EUSART_TypeDef *eusart,
+ EUSART_TristateTx_TypeDef enable)
+{
+ uint32_t tmp;
+
+ // Make sure that the module exists on the selected chip.
+ EFM_ASSERT(EUSART_REF_VALID(eusart));
+
+ tmp = ((uint32_t)(enable));
+ tmp &= (_EUSART_CMD_TXTRIEN_MASK | _EUSART_CMD_TXTRIDIS_MASK);
+
+ eusart_sync(eusart, EUSART_SYNCBUSY_TXTRIEN | EUSART_SYNCBUSY_TXTRIDIS);
+ eusart->CMD = tmp;
+ eusart_sync(eusart, EUSART_SYNCBUSY_TXTRIEN | EUSART_SYNCBUSY_TXTRIDIS);
+
+ tmp = 0u;
+ if ((_EUSART_CMD_TXTRIEN_MASK & enable) != 0u) {
+ tmp |= EUSART_STATUS_TXTRI;
+ }
+ while ((eusart->STATUS & _EUSART_STATUS_TXTRI_MASK) != tmp) {
+ } // Wait for the status register to be updated.
+}
+
+/***************************************************************************//**
+ * Initializes the automatic enabling of transmissions and/or reception using
+ * the PRS as a trigger.
+ ******************************************************************************/
+void EUSART_PrsTriggerEnable(EUSART_TypeDef *eusart,
+ const EUSART_PrsTriggerInit_TypeDef *init)
+{
+ uint32_t tmp;
+
+ // Make sure that the module exists on the selected chip.
+ EFM_ASSERT(EUSART_REF_VALID(eusart));
+
+ // The peripheral must be enabled to configure the PRS trigger.
+ EFM_ASSERT(eusart->EN == EUSART_EN_EN);
+
+#if defined(EUART_PRESENT)
+ PRS->CONSUMER_EUART0_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUART0_TRIGGER_MASK);
+#else
+
+#if defined(EUSART0)
+ if (eusart == EUSART0) {
+ PRS->CONSUMER_EUSART0_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUSART0_TRIGGER_MASK);
+ }
+#endif
+#if defined(EUSART1)
+ if (eusart == EUSART1) {
+ PRS->CONSUMER_EUSART1_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUSART1_TRIGGER_MASK);
+ }
+#endif
+#if defined(EUSART2)
+ if (eusart == EUSART2) {
+ PRS->CONSUMER_EUSART2_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUSART2_TRIGGER_MASK);
+ }
+#endif
+#if defined(EUSART3)
+ if (eusart == EUSART3) {
+ PRS->CONSUMER_EUSART3_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUSART3_TRIGGER_MASK);
+ }
+#endif
+#if defined(EUSART4)
+ if (eusart == EUSART4) {
+ PRS->CONSUMER_EUSART4_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUSART4_TRIGGER_MASK);
+ }
+#endif
+#endif
+
+ tmp = ((uint32_t)(init->prs_trigger_enable));
+ tmp &= (_EUSART_TRIGCTRL_RXTEN_MASK | _EUSART_TRIGCTRL_TXTEN_MASK);
+
+ eusart->TRIGCTRL_SET = tmp;
+ eusart_sync(eusart, EUSART_SYNCBUSY_RXTEN | EUSART_SYNCBUSY_TXTEN);
+
+ tmp = ~((uint32_t)(init->prs_trigger_enable));
+ tmp &= (_EUSART_TRIGCTRL_RXTEN_MASK | _EUSART_TRIGCTRL_TXTEN_MASK);
+ eusart->TRIGCTRL_CLR = tmp;
+ eusart_sync(eusart, EUSART_SYNCBUSY_RXTEN | EUSART_SYNCBUSY_TXTEN);
+}
+
+/*******************************************************************************
+ ************************** LOCAL FUNCTIONS ********************************
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * Gets the clock associated to the specified EUSART instance.
+ *
+ * @param eusart Pointer to the EUSART peripheral register block.
+ *
+ * @return Clock corresponding to the eusart.
+ ******************************************************************************/
+static CMU_Clock_TypeDef EUSART_ClockGet(EUSART_TypeDef *eusart)
+{
+ CMU_Clock_TypeDef clock;
+
+#if defined(EUART0)
+ if (eusart == EUART0) {
+ clock = cmuClock_EUART0;
+ }
+#endif
+#if defined(EUSART0)
+ if (eusart == EUSART0) {
+ clock = cmuClock_EUSART0;
+ }
+#endif
+#if defined(EUSART1)
+ else if (eusart == EUSART1) {
+ clock = cmuClock_EUSART1;
+ }
+#endif
+#if defined(EUSART2)
+ else if (eusart == EUSART2) {
+ clock = cmuClock_EUSART2;
+ }
+#endif
+#if defined(EUSART3)
+ else if (eusart == EUSART3) {
+ clock = cmuClock_EUSART3;
+ }
+#endif
+#if defined(EUSART4)
+ else if (eusart == EUSART4) {
+ clock = cmuClock_EUSART4;
+ }
+#endif
+ else {
+ EFM_ASSERT(0);
+ return (CMU_Clock_TypeDef)0u;
+ }
+ return clock;
+}
+
+/***************************************************************************//**
+ * Initializes the EUSART with asynchronous common settings to high
+ * and low frequency clock.
+ *
+ * @param eusart Pointer to the EUSART peripheral register block.
+ * @param init A pointer to the initialization structure.
+ * @param irdaInit Pointer to IrDA initialization structure.
+ ******************************************************************************/
+static void EUSART_AsyncInitCommon(EUSART_TypeDef *eusart,
+ const EUSART_UartInit_TypeDef *init,
+ const EUSART_IrDAInit_TypeDef *irdaInit,
+ const EUSART_DaliInit_TypeDef *daliInit)
+{
+ // LF register about to be modified requires sync busy check.
+ if (eusart->EN) {
+ eusart_sync(eusart, _EUSART_SYNCBUSY_MASK);
+ }
+ // Initialize EUSART registers to hardware reset state.
+ EUSART_Reset(eusart);
+
+ // Configure frame format
+ eusart->FRAMECFG = (eusart->FRAMECFG & ~(_EUSART_FRAMECFG_DATABITS_MASK
+ | _EUSART_FRAMECFG_STOPBITS_MASK
+ | _EUSART_FRAMECFG_PARITY_MASK))
+ | (uint32_t)(init->databits)
+ | (uint32_t)(init->parity)
+ | (uint32_t)(init->stopbits);
+
+ // Configure global configuration register 0.
+ eusart->CFG0 = (eusart->CFG0 & ~(_EUSART_CFG0_OVS_MASK
+ | _EUSART_CFG0_LOOPBK_MASK
+ | _EUSART_CFG0_MVDIS_MASK))
+ | (uint32_t)(init->oversampling)
+ | (uint32_t)(init->loopbackEnable)
+ | (uint32_t)(init->majorityVote);
+
+ if (init->baudrate == 0) {
+ eusart->CFG0 |= EUSART_CFG0_AUTOBAUDEN;
+ }
+
+ if (init->advancedSettings) {
+ eusart->CFG0 |= (uint32_t)init->advancedSettings->dmaHaltOnError << _EUSART_CFG0_ERRSDMA_SHIFT;
+ eusart->CFG0 |= (uint32_t)init->advancedSettings->txAutoTristate << _EUSART_CFG0_AUTOTRI_SHIFT;
+ eusart->CFG0 |= (uint32_t)init->advancedSettings->invertIO & (_EUSART_CFG0_RXINV_MASK | _EUSART_CFG0_TXINV_MASK);
+ eusart->CFG0 |= (uint32_t)init->advancedSettings->collisionDetectEnable << _EUSART_CFG0_CCEN_SHIFT;
+ eusart->CFG0 |= (uint32_t)init->advancedSettings->multiProcessorEnable << _EUSART_CFG0_MPM_SHIFT;
+ eusart->CFG0 |= (uint32_t)init->advancedSettings->multiProcessorAddressBitHigh << _EUSART_CFG0_MPAB_SHIFT;
+ eusart->CFG0 |= (uint32_t)init->advancedSettings->msbFirst << _EUSART_CFG0_MSBF_SHIFT;
+
+ // Configure global configuration register 1.
+ eusart->CFG1 = (uint32_t)init->advancedSettings->dmaWakeUpOnRx << _EUSART_CFG1_RXDMAWU_SHIFT
+ | (uint32_t)init->advancedSettings->dmaWakeUpOnTx << _EUSART_CFG1_TXDMAWU_SHIFT;
+
+ if (init->advancedSettings->hwFlowControl == eusartHwFlowControlCts
+ || init->advancedSettings->hwFlowControl == eusartHwFlowControlCtsAndRts) {
+ eusart->CFG1 |= EUSART_CFG1_CTSEN;
+ }
+ // Enable RTS route pin if necessary. CTS is an input so it is enabled by default.
+ if ((init->advancedSettings->hwFlowControl == eusartHwFlowControlRts)
+ || (init->advancedSettings->hwFlowControl == eusartHwFlowControlCtsAndRts)) {
+#if defined(EUART0)
+ GPIO->EUARTROUTE_SET->ROUTEEN = GPIO_EUART_ROUTEEN_RTSPEN;
+#elif defined(EUSART0)
+ GPIO->EUSARTROUTE_SET[EUSART_NUM(eusart)].ROUTEEN = GPIO_EUSART_ROUTEEN_RTSPEN;
+#endif
+ } else {
+#if defined(EUART0)
+ GPIO->EUARTROUTE_CLR->ROUTEEN = GPIO_EUART_ROUTEEN_RTSPEN;
+#elif defined(EUSART0)
+ GPIO->EUSARTROUTE_CLR[EUSART_NUM(eusart)].ROUTEEN = GPIO_EUSART_ROUTEEN_RTSPEN;
+#endif
+ }
+ eusart->STARTFRAMECFG_SET = (uint32_t)init->advancedSettings->startFrame;
+ if (init->advancedSettings->startFrame) {
+ eusart->CFG1 |= EUSART_CFG1_SFUBRX;
+ }
+ if (init->advancedSettings->prsRxEnable) {
+ eusart->CFG1 |= EUSART_CFG1_RXPRSEN;
+ // Configure PRS channel as input data line for EUSART.
+#if defined(EUART_PRESENT)
+ PRS->CONSUMER_EUART0_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUART0_RX_MASK);
+#elif defined(EUSART_PRESENT)
+
+ if (eusart == EUSART0) {
+ PRS->CONSUMER_EUSART0_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART0_RX_MASK);
+ }
+#if defined(EUSART1)
+ if (eusart == EUSART1) {
+ }
+ PRS->CONSUMER_EUSART1_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART1_RX_MASK);
+#endif
+#if defined(EUSART2)
+ if (eusart == EUSART2) {
+ PRS->CONSUMER_EUSART2_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART2_RX_MASK);
+ }
+#endif
+#if defined(EUSART3)
+ if (eusart == EUSART3) {
+ PRS->CONSUMER_EUSART3_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART3_RX_MASK);
+ }
+#endif
+#if defined(EUSART4)
+ if (eusart == EUSART4) {
+ PRS->CONSUMER_EUSART4_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART4_RX_MASK);
+ }
+#endif
+#endif
+ }
+ }
+
+ if (irdaInit) {
+ if (irdaInit->irDALowFrequencyEnable) {
+ eusart->IRLFCFG_SET = (uint32_t)(EUSART_IRLFCFG_IRLFEN);
+ } else {
+ // Configure IrDA HF configuration register.
+ eusart->IRHFCFG_SET = (eusart->IRHFCFG & ~(_EUSART_IRHFCFG_IRHFEN_MASK
+ | _EUSART_IRHFCFG_IRHFEN_MASK
+ | _EUSART_IRHFCFG_IRHFFILT_MASK))
+ | (uint32_t)(EUSART_IRHFCFG_IRHFEN)
+ | (uint32_t)(irdaInit->irDAPulseWidth)
+ | (uint32_t)(irdaInit->irDARxFilterEnable);
+ }
+ }
+
+#if defined(EUSART_DALICFG_DALIEN)
+ // DALI-specific configuration section
+ if (daliInit) {
+ if (init->loopbackEnable) {
+ // If LOOPBK in CFG0 is set to 1 in order to do loopback testing for DALI,
+ // then in this case DALIRXENDT should be set to 1.
+ eusart->DALICFG_SET = EUSART_DALICFG_DALIRXENDT;
+ }
+
+ // keep track of the number of 16-bits packet to send
+ if (daliInit->TXdatabits <= eusartDaliTxDataBits16) {
+ dali_tx_nb_packets[EUSART_NUM(eusart)] = 1;
+ } else {
+ dali_tx_nb_packets[EUSART_NUM(eusart)] = 2;
+ }
+
+ // keep track of the number of 16-bits packet to receive
+ if (daliInit->RXdatabits <= eusartDaliRxDataBits16) {
+ dali_rx_nb_packets[EUSART_NUM(eusart)] = 1;
+ } else {
+ dali_rx_nb_packets[EUSART_NUM(eusart)] = 2;
+ }
+
+ // Configure the numbers of bits per TX and RX frames
+ eusart->DALICFG = (eusart->DALICFG & ~(_EUSART_DALICFG_DALITXDATABITS_MASK
+ | _EUSART_DALICFG_DALIRXDATABITS_MASK))
+ | daliInit->TXdatabits
+ | daliInit->RXdatabits;
+ eusart->DALICFG_SET = EUSART_DALICFG_DALIEN;
+ }
+#else
+ (void)(daliInit);
+#endif /* EUSART_DALICFG_DALIEN */
+
+ // Enable EUSART IP.
+ EUSART_Enable(eusart, eusartEnable);
+
+ // Configure the baudrate if auto baud detection is not used.
+ if (init->baudrate) {
+ EUSART_BaudrateSet(eusart, init->refFreq, init->baudrate);
+ }
+
+ // Finally enable the Rx and/or Tx channel (as specified).
+ EUSART_Enable(eusart, init->enable);
+ while (~EUSART_StatusGet(eusart) & (_EUSART_STATUS_RXIDLE_MASK | _EUSART_STATUS_TXIDLE_MASK)) {
+ }
+}
+
+#if defined(EUSART_PRESENT)
+/***************************************************************************//**
+ * Initializes the EUSART with synchronous common settings to high
+ * and low frequency clock.
+ *
+ * @param eusart Pointer to the EUSART peripheral register block.
+ * @param init A pointer to the initialization structure.
+ ******************************************************************************/
+static void EUSART_SyncInitCommon(EUSART_TypeDef *eusart,
+ EUSART_SpiInit_TypeDef const *init)
+{
+ void* advancedSetting_ptr = (void*)init->advancedSettings; // Used to avoid GCC over optimization.
+
+ // LF register about to be modified requires sync busy check.
+ if (eusart->EN) {
+ eusart_sync(eusart, _EUSART_SYNCBUSY_MASK);
+ }
+
+ // Initialize EUSART registers to hardware reset state.
+ EUSART_Reset(eusart);
+
+ // Configure global configuration register 2.
+ eusart->CFG2 = (eusart->CFG2 & ~(_EUSART_CFG2_MASTER_MASK
+ | _EUSART_CFG2_CLKPOL_MASK
+ | _EUSART_CFG2_CLKPHA_MASK
+ | _EUSART_CFG2_FORCELOAD_MASK))
+ | (uint32_t)(init->master)
+ | (uint32_t)(init->clockMode)
+ | (uint32_t)(EUSART_CFG2_FORCELOAD); // Force load feature enabled by default.
+
+ if (advancedSetting_ptr) {
+ // Configure global configuration register 2.
+ eusart->CFG2 = (eusart->CFG2 & ~(_EUSART_CFG2_FORCELOAD_MASK
+ | _EUSART_CFG2_AUTOCS_MASK
+ | _EUSART_CFG2_AUTOTX_MASK
+ | _EUSART_CFG2_CSINV_MASK
+ | _EUSART_CFG2_CLKPRSEN_MASK))
+ | (uint32_t)(init->advancedSettings->forceLoad << _EUSART_CFG2_FORCELOAD_SHIFT)
+ | (uint32_t)(init->advancedSettings->autoCsEnable << _EUSART_CFG2_AUTOCS_SHIFT)
+ | (uint32_t)(init->advancedSettings->autoTxEnable << _EUSART_CFG2_AUTOTX_SHIFT)
+ | (uint32_t)(init->advancedSettings->csPolarity)
+ | (uint32_t)(init->advancedSettings->prsClockEnable << _EUSART_CFG2_CLKPRSEN_SHIFT);
+
+ // Only applicable to EM2 (low frequency) capable EUSART instances.
+ eusart->CFG1 = (eusart->CFG1 & ~(_EUSART_CFG1_RXFIW_MASK
+ | _EUSART_CFG1_TXFIW_MASK))
+ | (uint32_t)(init->advancedSettings->RxFifoWatermark)
+ | (uint32_t)(init->advancedSettings->TxFifoWatermark)
+ | (uint32_t)(init->advancedSettings->dmaWakeUpOnRx << _EUSART_CFG1_RXDMAWU_SHIFT)
+ | (uint32_t)(init->advancedSettings->prsRxEnable << _EUSART_CFG1_RXPRSEN_SHIFT);
+ }
+
+ eusart->CFG0 = (eusart->CFG0 & ~(_EUSART_CFG0_SYNC_MASK
+ | _EUSART_CFG0_LOOPBK_MASK))
+ | (uint32_t)(_EUSART_CFG0_SYNC_SYNC)
+ | (uint32_t)(init->loopbackEnable);
+
+ if (advancedSetting_ptr) {
+ eusart->CFG0 |= (uint32_t)init->advancedSettings->invertIO & (_EUSART_CFG0_RXINV_MASK | _EUSART_CFG0_TXINV_MASK);
+ eusart->CFG0 |= (uint32_t)init->advancedSettings->msbFirst << _EUSART_CFG0_MSBF_SHIFT;
+
+ // Configure global configurationTiming register.
+ eusart->TIMINGCFG = (eusart->TIMINGCFG & ~(_EUSART_TIMINGCFG_CSSETUP_MASK
+ | _EUSART_TIMINGCFG_CSHOLD_MASK
+ | _EUSART_TIMINGCFG_ICS_MASK
+ | _EUSART_TIMINGCFG_SETUPWINDOW_MASK))
+ | ((uint32_t)(init->advancedSettings->autoCsSetupTime << _EUSART_TIMINGCFG_CSSETUP_SHIFT)
+ & _EUSART_TIMINGCFG_CSSETUP_MASK)
+ | ((uint32_t)(init->advancedSettings->autoCsHoldTime << _EUSART_TIMINGCFG_CSHOLD_SHIFT)
+ & _EUSART_TIMINGCFG_CSHOLD_MASK)
+ | ((uint32_t)(init->advancedSettings->autoInterFrameTime << _EUSART_TIMINGCFG_ICS_SHIFT)
+ & _EUSART_TIMINGCFG_ICS_MASK)
+ | ((uint32_t)(init->advancedSettings->setupWindow << _EUSART_TIMINGCFG_SETUPWINDOW_SHIFT)
+ & _EUSART_TIMINGCFG_SETUPWINDOW_MASK)
+ ;
+ }
+
+ // Configure frame format
+ eusart->FRAMECFG = (eusart->FRAMECFG & ~(_EUSART_FRAMECFG_DATABITS_MASK))
+ | (uint32_t)(init->databits);
+
+ if (advancedSetting_ptr) {
+ eusart->DTXDATCFG = (init->advancedSettings->defaultTxData & _EUSART_DTXDATCFG_MASK);
+
+ if (init->advancedSettings->prsRxEnable) {
+ //Configure PRS channel as input data line for EUSART.
+ if (eusart == EUSART0) {
+ PRS->CONSUMER_EUSART0_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART0_RX_MASK);
+ }
+#if defined(EUSART1)
+ if (eusart == EUSART1) {
+ PRS->CONSUMER_EUSART1_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART1_RX_MASK);
+ }
+#endif
+#if defined(EUSART2)
+ if (eusart == EUSART2) {
+ PRS->CONSUMER_EUSART2_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART2_RX_MASK);
+ }
+#endif
+#if defined(EUSART3)
+ if (eusart == EUSART3) {
+ PRS->CONSUMER_EUSART3_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART3_RX_MASK);
+ }
+#endif
+#if defined(EUSART4)
+ if (eusart == EUSART4) {
+ PRS->CONSUMER_EUSART4_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART4_RX_MASK);
+ }
+#endif
+ }
+
+ if (init->advancedSettings->prsClockEnable) {
+ //Configure PRS channel as SCLK input for EUSART.
+ if (eusart == EUSART0) {
+ PRS->CONSUMER_EUSART0_CLK_SET = (init->advancedSettings->prsClockChannel & _PRS_CONSUMER_EUSART0_CLK_MASK);
+ }
+#if defined(EUSART1)
+ if (eusart == EUSART1) {
+ PRS->CONSUMER_EUSART1_CLK_SET = (init->advancedSettings->prsClockChannel & _PRS_CONSUMER_EUSART1_CLK_MASK);
+ }
+#endif
+#if defined(EUSART2)
+ if (eusart == EUSART2) {
+ PRS->CONSUMER_EUSART2_CLK_SET = (init->advancedSettings->prsClockChannel & _PRS_CONSUMER_EUSART2_CLK_MASK);
+ }
+#endif
+#if defined(EUSART3)
+ if (eusart == EUSART3) {
+ PRS->CONSUMER_EUSART3_CLK_SET = (init->advancedSettings->prsClockChannel & _PRS_CONSUMER_EUSART3_CLK_MASK);
+ }
+#endif
+#if defined(EUSART4)
+ if (eusart == EUSART4) {
+ PRS->CONSUMER_EUSART4_CLK_SET = (init->advancedSettings->prsClockChannel & _PRS_CONSUMER_EUSART4_CLK_MASK);
+ }
+#endif
+ }
+ }
+
+ // Set baudrate for synchronous operation mode.
+ EUSART_BaudrateSet(eusart, init->refFreq, init->bitRate);
+
+ // Enable EUSART IP.
+ EUSART_Enable(eusart, eusartEnable);
+
+ // Finally enable the Rx and/or Tx channel (as specified).
+ eusart_sync(eusart, _EUSART_SYNCBUSY_RXEN_MASK & _EUSART_SYNCBUSY_TXEN_MASK); // Wait for low frequency register synchronization.
+ eusart->CMD = (uint32_t)init->enable;
+ eusart_sync(eusart, _EUSART_SYNCBUSY_RXEN_MASK & _EUSART_SYNCBUSY_TXEN_MASK);
+ while (~EUSART_StatusGet(eusart) & (_EUSART_STATUS_RXIDLE_MASK | _EUSART_STATUS_TXIDLE_MASK)) {
+ }
+}
+#endif
+
+/***************************************************************************//**
+ * Calculate baudrate for a given reference frequency, clock division,
+ * and oversampling rate when the module is in UART mode.
+ *
+ * @param refFreq The EUSART reference clock frequency in Hz that will be used.
+ * @param clkdiv Clock division factor to be used.
+ * @param ovs Oversampling to be used.
+ *
+ * @return Computed baudrate from given settings.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t EUSART_AsyncBaudrateCalc(uint32_t refFreq,
+ uint32_t clkdiv,
+ EUSART_OVS_TypeDef ovs)
+{
+ uint32_t oversample;
+ uint64_t divisor;
+ uint64_t factor;
+ uint64_t remainder;
+ uint64_t quotient;
+ uint32_t br;
+
+ // Out of bound clkdiv.
+ EFM_ASSERT(clkdiv <= _EUSART_CLKDIV_MASK);
+
+ // Mask out unused bits
+ clkdiv &= _EUSART_CLKDIV_MASK;
+
+ /* Use integer division to avoid forcing in float division
+ * utils and yet keep rounding effect errors to a minimum.
+ *
+ * Baudrate in is given by:
+ *
+ * br = fUARTn/(oversample * (1 + (CLKDIV / 256)))
+ * or
+ * br = (256 * fUARTn)/(oversample * (256 + CLKDIV))
+ *
+ * 256 factor of the dividend is reduced with a
+ * (part of) oversample part of the divisor.
+ */
+
+ switch (ovs) {
+ case eusartOVS16:
+ oversample = 1;
+ factor = 256 / 16;
+ break;
+
+ case eusartOVS8:
+ oversample = 1;
+ factor = 256 / 8;
+ break;
+
+ case eusartOVS6:
+ oversample = 3;
+ factor = 256 / 2;
+ break;
+
+ case eusartOVS4:
+ oversample = 1;
+ factor = 256 / 4;
+ break;
+
+ case eusartOVS0:
+ oversample = 1;
+ factor = 256;
+ break;
+
+ default:
+ return 0u;
+ break;
+ }
+
+ /*
+ * The basic problem with integer division in the above formula is that
+ * the dividend (factor * fUARTn) may become larger than a 32 bit
+ * integer. Yet we want to evaluate the dividend first before dividing
+ * to get as small rounding effects as possible. Too harsh restrictions
+ * should not be made on the maximum fUARTn value either.
+ *
+ * For division a/b,
+ *
+ * a = qb + r
+ *
+ * where q is the quotient and r is the remainder, both integers.
+ *
+ * The original baudrate formula can be rewritten as
+ *
+ * br = xa / b = x(qb + r)/b = xq + xr/b
+ *
+ * where x is 'factor', a is 'refFreq' and b is 'divisor', referring to
+ * variable names.
+ */
+
+ /*
+ * The divisor will never exceed max 32 bit value since
+ * clkdiv <= _EUSART_CLKDIV_MASK (currently 0x7FFFF8)
+ * and 'oversample' has been reduced to <= 3.
+ */
+ divisor = (uint64_t)(oversample * (256 + clkdiv));
+
+ quotient = refFreq / divisor;
+ remainder = refFreq % divisor;
+
+ // The factor <= 128 and since divisor >= 256, the below cannot exceed the maximum
+ // 32 bit value. However, factor * remainder can become larger than 32-bit
+ // because of the size of _EUSART_CLKDIV_DIV_MASK on some families.
+ br = (uint32_t) (factor * quotient);
+
+ /*
+ * The factor <= 128 and remainder < (oversample*(256 + clkdiv)), which
+ * means dividend (factor * remainder) worst case is
+ * 128 * (3 * (256 + _EUSART_CLKDIV_MASK)) = 0xC001_7400.
+ */
+ br += (uint32_t) ((factor * remainder) / divisor);
+
+ return br;
+}
+
+/***************************************************************************//**
+ * Perform EUSART Module disablement - resetting all internal flops/FSM.
+ *
+ * @param eusart Pointer to the EUSART peripheral register block.
+ ******************************************************************************/
+__STATIC_INLINE void EUSART_Disable(EUSART_TypeDef *eusart)
+{
+ if (eusart->EN & _EUSART_EN_EN_MASK) {
+ // This step should be skipped especially in Synchronous Slave mode when
+ // external SCLK is not running and CS is active
+#if defined(EUSART_PRESENT)
+ if (!(eusart->CFG0 & _EUSART_CFG0_SYNC_MASK) || (eusart->CFG2 & _EUSART_CFG2_MASTER_MASK))
+#endif
+ {
+ // General Programming Guideline to properly disable the module:
+ // 1a. Disable TX and RX using TXDIS and RXDIS cmd
+ eusart->CMD = EUSART_CMD_TXDIS | EUSART_CMD_RXDIS;
+ // 1b. Poll for EUSARTn_SYNCBUSY.TXDIS and EUSARTn_SYNCBUSY.RXDIS to go low;
+ eusart_sync(eusart, (EUSART_SYNCBUSY_TXDIS | EUSART_SYNCBUSY_RXDIS));
+ // 1c. Wait for EUSARTn_STATUS.TXENS and EUSARTn_STATUS.RXENS to go low
+ while (eusart->STATUS & (_EUSART_STATUS_TXENS_MASK | _EUSART_STATUS_RXENS_MASK)) {
+ }
+ }
+#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2)
+ eusart->CLKDIV = eusart->CLKDIV;
+ eusart_sync(eusart, _EUSART_SYNCBUSY_DIV_MASK);
+
+ // Read data until FIFO is emptied
+ // but taking care not to underflow the receiver
+ while (eusart->STATUS & EUSART_STATUS_RXFL) {
+ eusart->RXDATA;
+ }
+#endif
+
+ eusart->EN_CLR = EUSART_EN_EN;
+
+#if defined(_EUSART_EN_DISABLING_MASK)
+ // 2. Polling for EUSARTn_EN.DISABLING = 0.
+ while (eusart->EN & _EUSART_EN_DISABLING_MASK) {
+ }
+#endif
+ }
+}
+
+#endif /* defined(EUART_PRESENT) || defined(EUSART_PRESENT) */
diff --git a/mcu/efr/common/vendor/em_eusart.h b/mcu/efr/common/vendor/em_eusart.h
new file mode 100644
index 00000000..afe84d97
--- /dev/null
+++ b/mcu/efr/common/vendor/em_eusart.h
@@ -0,0 +1,1160 @@
+/***************************************************************************//**
+ * @file
+ * @brief Universal asynchronous receiver/transmitter (EUSART) peripheral API
+ *******************************************************************************
+ * # License
+ * Copyright 2019 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef EM_EUSART_H
+#define EM_EUSART_H
+#include "em_device.h"
+#if defined(EUART_PRESENT) || defined(EUSART_PRESENT)
+#include "em_eusart_compat.h"
+#include
+
+/* *INDENT-OFF* */
+// *****************************************************************************
+/// @addtogroup eusart EUSART - Extended USART
+/// @brief Extended Universal Synchronous/Asynchronous Receiver/Transmitter
+///
+/// @li @ref eusart_intro
+/// @li @ref eusart_example
+/// @li @ref eusart_em2
+///
+///@n @section eusart_intro Introduction
+/// This module contains functions to control the Enhanced Universal Synchronous
+/// / Asynchronous Receiver / Transmitter controller(s) (EUSART) peripheral of Silicon
+/// Labs' 32-bit MCUs and SoCs. EUSART can be used as a UART and can,
+/// therefore, be connected to an external transceiver to communicate with
+/// another host using the serial link.
+///
+/// It supports full duplex asynchronous UART communication as well as RS-485,
+/// SPI, MicroWire, and 3-wire. It can also interface with ISO7816 Smart-Cards,
+/// and IrDA devices.
+///
+/// EUSART has a wide selection of operating modes, frame formats, and baud rates.
+/// All features are supported through the API of this module.
+///
+/// This module does not support DMA configuration. UARTDRV and SPIDRV drivers
+/// provide full support for DMA and more.
+///
+///@n @section eusart_example Example
+///
+/// EUSART Async TX example:
+/// @code{.c}
+/// {
+/// EUSART_UartInit_TypeDef init = EUSART_UART_INIT_DEFAULT_HF;
+///
+/// // Configure the clocks.
+/// CMU_ClockSelectSet(cmuClock_EUSART0CLK, cmuSelect_EM01GRPCCLK);
+/// CMU_ClockEnable(cmuClock_EUSART0CLK, true);
+/// // Initialize the EUSART
+/// EUSART_UartInitHf(EUSART0, &init);
+/// EUSART_Tx(EUSART0, data);
+/// }
+///
+/// @endcode
+///
+/// EUSART Sync SPI Transaction example:
+/// @code{.c}
+/// {
+/// EUSART_SpiInit_TypeDef init_master = EUSART_SPI_MASTER_INIT_DEFAULT_HF;
+///
+/// // Configure the clocks.
+/// CMU_ClockSelectSet(cmuClock_EM01GRPCCLK, cmuSelect_HFRCODPLL);
+/// CMU_ClockEnable(cmuClock_EUSART1, true);
+/// CMU_ClockEnable(cmuClock_GPIO, true);
+///
+/// //Configure the SPI ports
+/// GPIO_PinModeSet(sclk_port, sclk_pin, gpioModePushPull, 0);
+/// GPIO_PinModeSet(mosi_port, mosi_pin, gpioModePushPull, 0);
+/// GPIO_PinModeSet(mosi_port, miso_pin, gpioModeInput, 0);
+///
+/// // Connect EUSART to ports
+/// GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].TXROUTE = (mosi_port << _GPIO_EUSART_TXROUTE_PORT_SHIFT)
+/// | (mosi_pin << _GPIO_EUSART_TXROUTE_PIN_SHIFT);
+/// GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].RXROUTE = (miso_port << _GPIO_EUSART_RXROUTE_PORT_SHIFT)
+/// | (miso_pin << _GPIO_EUSART_RXROUTE_PIN_SHIFT);
+/// GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].SCLKROUTE = (sclk_port << _GPIO_EUSART_SCLKROUTE_PORT_SHIFT)
+/// | (sclk_pin << _GPIO_EUSART_SCLKROUTE_PIN_SHIFT);
+/// GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].ROUTEEN = GPIO_EUSART_ROUTEEN_TXPEN | GPIO_EUSART_ROUTEEN_SCLKPEN;
+///
+/// // Initialize the EUSART
+/// EUSART_SpiInit(EUSART1, &init_master);
+/// EUSART_Spi_TxRx(EUSART1, data);
+/// }
+///
+/// @endcode
+///@n @section eusart_em2 EM2 guidelines for non EM2-Capable instances
+///
+/// @note EUSART instances located in the PD1 power domain are non EM2-capable.
+/// The EUSART_EM2_CAPABLE() and EUSART_NOT_EM2_CAPABLE() macros can be used
+/// to determine whether or not a EUSART instance is EM2-Capable.
+///
+/// Follow theses steps when entering in EM2:
+/// -# Wait for the current transaction to complete with TXCIF interrupt
+/// -# Disable TX and RX using TXDIS and RXDIS cmd
+/// -# Poll for EUSARTn_SYNCBUSY.TXDIS and EUSARTn_SYNCBUSY.RXDIS to go low
+/// -# Wait for EUSARTn_STATUS.TXENS and EUSARTn_STATUS.RXENS to go low
+/// -# Disable SCLKPEN and CSPEN in GPIO if they were previously enabled
+/// -# Enter EM2
+///
+/// On wakeup from EM2, EUSART transmitter/receiver and relevant GPIO
+/// (SCLKPEN and CSPEN) must be re-enabled. For example:
+///
+/// @code{.c}
+/// {
+/// // Enable TX and RX
+/// EUSART_Enable(EUSART0, eusartEnable);
+/// BUS_RegMaskedWrite(&GPIO->EUSARTROUTE[EUSART_NUM(EUSART0)].ROUTEEN,
+/// _GPIO_EUSART_ROUTEEN_TXPEN_MASK | _GPIO_EUSART_ROUTEEN_SCLKPEN_MASK,
+/// GPIO_EUSART_ROUTEEN_TXPEN | GPIO_EUSART_ROUTEEN_SCLKPEN);
+/// }
+/// @endcode
+///
+/// @{
+// *****************************************************************************
+/* *INDENT-ON* */
+
+/*******************************************************************************
+ ******************************** ENUMS ************************************
+ ******************************************************************************/
+
+/// Enable selection.
+typedef enum {
+ /// Disable the peripheral.
+ eusartDisable = 0x0,
+
+ /// Enable receiver only, transmitter disabled.
+ eusartEnableRx = (EUSART_CMD_RXEN | EUSART_CMD_TXDIS),
+
+ /// Enable transmitter only, receiver disabled.
+ eusartEnableTx = (EUSART_CMD_TXEN | EUSART_CMD_RXDIS),
+
+ /// Enable both receiver and transmitter.
+ eusartEnable = (EUSART_CMD_RXEN | EUSART_CMD_TXEN)
+} EUSART_Enable_TypeDef;
+
+/// Data bit selection.
+typedef enum {
+ eusartDataBits7 = EUSART_FRAMECFG_DATABITS_SEVEN, ///< 7 data bits.
+ eusartDataBits8 = EUSART_FRAMECFG_DATABITS_EIGHT, ///< 8 data bits.
+ eusartDataBits9 = EUSART_FRAMECFG_DATABITS_NINE, ///< 9 data bits.
+#if defined(EUSART_PRESENT)
+ eusartDataBits10 = EUSART_FRAMECFG_DATABITS_TEN, ///< 10 data bits, SPI mode only.
+ eusartDataBits11 = EUSART_FRAMECFG_DATABITS_ELEVEN, ///< 11 data bits, SPI mode only.
+ eusartDataBits12 = EUSART_FRAMECFG_DATABITS_TWELVE, ///< 12 data bits, SPI mode only.
+ eusartDataBits13 = EUSART_FRAMECFG_DATABITS_THIRTEEN, ///< 13 data bits, SPI mode only.
+ eusartDataBits14 = EUSART_FRAMECFG_DATABITS_FOURTEEN, ///< 14 data bits, SPI mode only.
+ eusartDataBits15 = EUSART_FRAMECFG_DATABITS_FIFTEEN, ///< 15 data bits, SPI mode only.
+ eusartDataBits16 = EUSART_FRAMECFG_DATABITS_SIXTEEN, ///< 16 data bits, SPI mode only.
+#endif
+} EUSART_Databits_TypeDef;
+
+/// Parity selection.
+typedef enum {
+ eusartNoParity = EUSART_FRAMECFG_PARITY_NONE, ///< No parity.
+ eusartEvenParity = EUSART_FRAMECFG_PARITY_EVEN, ///< Even parity.
+ eusartOddParity = EUSART_FRAMECFG_PARITY_ODD ///< Odd parity.
+} EUSART_Parity_TypeDef;
+
+/// Stop bits selection.
+typedef enum {
+ eusartStopbits0p5 = EUSART_FRAMECFG_STOPBITS_HALF, ///< 0.5 stop bits.
+ eusartStopbits1p5 = EUSART_FRAMECFG_STOPBITS_ONEANDAHALF, ///< 1.5 stop bits.
+ eusartStopbits1 = EUSART_FRAMECFG_STOPBITS_ONE, ///< 1 stop bits.
+ eusartStopbits2 = EUSART_FRAMECFG_STOPBITS_TWO ///< 2 stop bits.
+} EUSART_Stopbits_TypeDef;
+
+/// Oversampling selection, used for asynchronous operation.
+typedef enum {
+ eusartOVS16 = EUSART_CFG0_OVS_X16, ///< 16x oversampling (normal).
+ eusartOVS8 = EUSART_CFG0_OVS_X8, ///< 8x oversampling.
+ eusartOVS6 = EUSART_CFG0_OVS_X6, ///< 6x oversampling.
+ eusartOVS4 = EUSART_CFG0_OVS_X4, ///< 4x oversampling.
+ eusartOVS0 = EUSART_CFG0_OVS_DISABLE ///< Oversampling disabled.
+} EUSART_OVS_TypeDef;
+
+/// HW flow control config.
+typedef enum {
+ eusartHwFlowControlNone = 0, ///< No HW Flow Control.
+ eusartHwFlowControlCts, ///< CTS HW Flow Control.
+ eusartHwFlowControlRts, ///< RTS HW Flow Control.
+ eusartHwFlowControlCtsAndRts ///< CTS and RTS HW Flow Control.
+} EUSART_HwFlowControl_TypeDef;
+
+/// Loopback enable.
+typedef enum {
+ eusartLoopbackEnable = EUSART_CFG0_LOOPBK, ///< Enable loopback.
+ eusartLoopbackDisable = _EUSART_CFG0_RESETVALUE ///< Disable loopback.
+} EUSART_LoopbackEnable_TypeDef;
+
+/// Majority vote enable.
+typedef enum {
+ eusartMajorityVoteEnable = EUSART_CFG0_MVDIS_DEFAULT, ///< Enable majority vote for 16x, 8x and 6x oversampling modes.
+ eusartMajorityVoteDisable = EUSART_CFG0_MVDIS ///< Disable majority vote for 16x, 8x and 6x oversampling modes.
+} EUSART_MajorityVote_TypeDef;
+
+/// Block reception enable.
+typedef enum {
+ eusartBlockRxEnable = EUSART_CMD_RXBLOCKEN, ///< Block reception enable, resulting in all incoming frames being discarded.
+ eusartBlockRxDisable = EUSART_CMD_RXBLOCKDIS ///< Block reception disable, resulting in all incoming frames being loaded into the RX FIFO.
+} EUSART_BlockRx_TypeDef;
+
+/// TX output tristate enable.
+typedef enum {
+ eusartTristateTxEnable = EUSART_CMD_TXTRIEN, ///< Tristates the transmitter output.
+ eusartTristateTxDisable = EUSART_CMD_TXTRIDIS ///< Disables tristating of the transmitter output.
+} EUSART_TristateTx_TypeDef;
+
+/// IrDA filter enable.
+typedef enum {
+ eusartIrDARxFilterEnable = EUSART_IRHFCFG_IRHFFILT_ENABLE, ///< Enable filter on demodulator.
+ eusartIrDARxFilterDisable = EUSART_IRHFCFG_IRHFFILT_DISABLE ///< Disable filter on demodulator.
+} EUSART_IrDARxFilterEnable_TypeDef;
+
+/// Pulse width selection for IrDA mode.
+typedef enum {
+ /// IrDA pulse width is 1/16 for OVS=X16 and 1/8 for OVS=X8
+ eusartIrDAPulseWidthOne = EUSART_IRHFCFG_IRHFPW_ONE,
+
+ /// IrDA pulse width is 2/16 for OVS=X16 and 2/8 for OVS=X8
+ eusartIrDAPulseWidthTwo = EUSART_IRHFCFG_IRHFPW_TWO,
+
+ /// IrDA pulse width is 3/16 for OVS=X16 and 3/8 for OVS=X8
+ eusartIrDAPulseWidthThree = EUSART_IRHFCFG_IRHFPW_THREE,
+
+ /// IrDA pulse width is 4/16 for OVS=X16 and 4/8 for OVS=X8
+ eusartIrDAPulseWidthFour = EUSART_IRHFCFG_IRHFPW_FOUR
+} EUSART_IrDAPulseWidth_Typedef;
+
+/// PRS trigger enable.
+typedef enum {
+ /// Disable trigger on both receiver and transmitter.
+ eusartPrsTriggerDisable = 0x0,
+
+ /// Enable receive trigger only, transmit disabled.
+ eusartPrsTriggerEnableRx = EUSART_TRIGCTRL_RXTEN,
+
+ /// Enable transmit trigger only, receive disabled.
+ eusartPrsTriggerEnableTx = EUSART_TRIGCTRL_TXTEN,
+
+ /// Enable trigger on both receive and transmit.
+ eusartPrsTriggerEnableRxTx = (EUSART_TRIGCTRL_RXTEN | EUSART_TRIGCTRL_TXTEN)
+} EUSART_PrsTriggerEnable_TypeDef;
+
+/// PRS Channel type.
+typedef uint8_t EUSART_PrsChannel_TypeDef;
+
+/// IO polarity selection.
+typedef enum {
+ /// Disable inversion on both RX and TX signals.
+ eusartInvertIODisable = (EUSART_CFG0_RXINV_DISABLE | EUSART_CFG0_TXINV_DISABLE),
+
+ /// Invert RX signal, before receiver.
+ eusartInvertRxEnable = EUSART_CFG0_RXINV_ENABLE,
+
+ /// Invert TX signal, after transmitter.
+ eusartInvertTxEnable = EUSART_CFG0_TXINV_ENABLE,
+
+ /// Enable trigger on both receive and transmit.
+ eusartInvertIOEnable = (EUSART_CFG0_RXINV_ENABLE | EUSART_CFG0_TXINV_ENABLE)
+} EUSART_InvertIO_TypeDef;
+
+#if defined(EUSART_PRESENT)
+/// Clock polarity/phase mode.
+typedef enum {
+ /// Clock idle low, sample on rising edge.
+ eusartClockMode0 = EUSART_CFG2_CLKPOL_IDLELOW | EUSART_CFG2_CLKPHA_SAMPLELEADING,
+
+ /// Clock idle low, sample on falling edge.
+ eusartClockMode1 = EUSART_CFG2_CLKPOL_IDLELOW | EUSART_CFG2_CLKPHA_SAMPLETRAILING,
+
+ /// Clock idle high, sample on falling edge.
+ eusartClockMode2 = EUSART_CFG2_CLKPOL_IDLEHIGH | EUSART_CFG2_CLKPHA_SAMPLELEADING,
+
+ /// Clock idle high, sample on rising edge.
+ eusartClockMode3 = EUSART_CFG2_CLKPOL_IDLEHIGH | EUSART_CFG2_CLKPHA_SAMPLETRAILING
+} EUSART_ClockMode_TypeDef;
+
+/// Chip select polarity.
+typedef enum {
+ /// Chip select active low.
+ eusartCsActiveLow = EUSART_CFG2_CSINV_AL,
+
+ /// Chip select active high.
+ eusartCsActiveHigh = EUSART_CFG2_CSINV_AH,
+} EUSART_CsPolarity_TypeDef;
+
+/// RX FIFO Interrupt ans Status Watermark.
+typedef enum {
+ eusartRxFiFoWatermark1Frame = EUSART_CFG1_RXFIW_ONEFRAME,
+ eusartRxFiFoWatermark2Frame = EUSART_CFG1_RXFIW_TWOFRAMES,
+ eusartRxFiFoWatermark3Frame = EUSART_CFG1_RXFIW_THREEFRAMES,
+ eusartRxFiFoWatermark4Frame = EUSART_CFG1_RXFIW_FOURFRAMES,
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 2)
+ eusartRxFiFoWatermark5Frame = EUSART_CFG1_RXFIW_FIVEFRAMES,
+ eusartRxFiFoWatermark6Frame = EUSART_CFG1_RXFIW_SIXFRAMES,
+ eusartRxFiFoWatermark7Frame = EUSART_CFG1_RXFIW_SEVENFRAMES,
+ eusartRxFiFoWatermark8Frame = EUSART_CFG1_RXFIW_EIGHTFRAMES,
+ eusartRxFiFoWatermark9Frame = EUSART_CFG1_RXFIW_NINEFRAMES,
+ eusartRxFiFoWatermark10Frame = EUSART_CFG1_RXFIW_TENFRAMES,
+ eusartRxFiFoWatermark11Frame = EUSART_CFG1_RXFIW_ELEVENFRAMES,
+ eusartRxFiFoWatermark12Frame = EUSART_CFG1_RXFIW_TWELVEFRAMES,
+ eusartRxFiFoWatermark13Frame = EUSART_CFG1_RXFIW_THIRTEENFRAMES,
+ eusartRxFiFoWatermark14Frame = EUSART_CFG1_RXFIW_FOURTEENFRAMES,
+ eusartRxFiFoWatermark15Frame = EUSART_CFG1_RXFIW_FIFTEENFRAMES,
+ eusartRxFiFoWatermark16Frame = EUSART_CFG1_RXFIW_SIXTEENFRAMES
+#endif
+} EUSART_RxFifoWatermark_TypeDef;
+
+/// TX FIFO Interrupt and Status Watermark.
+typedef enum {
+ eusartTxFiFoWatermark1Frame = EUSART_CFG1_TXFIW_ONEFRAME,
+ eusartTxFiFoWatermark2Frame = EUSART_CFG1_TXFIW_TWOFRAMES,
+ eusartTxFiFoWatermark3Frame = EUSART_CFG1_TXFIW_THREEFRAMES,
+ eusartTxFiFoWatermark4Frame = EUSART_CFG1_TXFIW_FOURFRAMES,
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 2)
+ eusartTxFiFoWatermark5Frame = EUSART_CFG1_TXFIW_FIVEFRAMES,
+ eusartTxFiFoWatermark6Frame = EUSART_CFG1_TXFIW_SIXFRAMES,
+ eusartTxFiFoWatermark7Frame = EUSART_CFG1_TXFIW_SEVENFRAMES,
+ eusartTxFiFoWatermark8Frame = EUSART_CFG1_TXFIW_EIGHTFRAMES,
+ eusartTxFiFoWatermark9Frame = EUSART_CFG1_TXFIW_NINEFRAMES,
+ eusartTxFiFoWatermark10Frame = EUSART_CFG1_TXFIW_TENFRAMES,
+ eusartTxFiFoWatermark11Frame = EUSART_CFG1_TXFIW_ELEVENFRAMES,
+ eusartTxFiFoWatermark12Frame = EUSART_CFG1_TXFIW_TWELVEFRAMES,
+ eusartTxFiFoWatermark13Frame = EUSART_CFG1_TXFIW_THIRTEENFRAMES,
+ eusartTxFiFoWatermark14Frame = EUSART_CFG1_TXFIW_FOURTEENFRAMES,
+ eusartTxFiFoWatermark15Frame = EUSART_CFG1_TXFIW_FIFTEENFRAMES,
+ eusartTxFiFoWatermark16Frame = EUSART_CFG1_TXFIW_SIXTEENFRAMES
+#endif
+} EUSART_TxFifoWatermark_TypeDef;
+
+#if defined(EUSART_DALICFG_DALIEN)
+/// DALI TX databits (8-32).
+typedef enum {
+ eusartDaliTxDataBits8 = EUSART_DALICFG_DALITXDATABITS_EIGHT, ///< Each frame contains 8 data bits.
+ eusartDaliTxDataBits9 = EUSART_DALICFG_DALITXDATABITS_NINE, ///< Each frame contains 9 data bits.
+ eusartDaliTxDataBits10 = EUSART_DALICFG_DALITXDATABITS_TEN, ///< Each frame contains 10 data bits.
+ eusartDaliTxDataBits11 = EUSART_DALICFG_DALITXDATABITS_ELEVEN, ///< Each frame contains 11 data bits.
+ eusartDaliTxDataBits12 = EUSART_DALICFG_DALITXDATABITS_TWELVE, ///< Each frame contains 12 data bits.
+ eusartDaliTxDataBits13 = EUSART_DALICFG_DALITXDATABITS_THIRTEEN, ///< Each frame contains 13 data bits.
+ eusartDaliTxDataBits14 = EUSART_DALICFG_DALITXDATABITS_FOURTEEN, ///< Each frame contains 14 data bits.
+ eusartDaliTxDataBits15 = EUSART_DALICFG_DALITXDATABITS_FIFTEEN, ///< Each frame contains 15 data bits.
+ eusartDaliTxDataBits16 = EUSART_DALICFG_DALITXDATABITS_SIXTEEN, ///< Each frame contains 16 data bits.
+ eusartDaliTxDataBits17 = EUSART_DALICFG_DALITXDATABITS_SEVENTEEN, ///< Each frame contains 17 data bits.
+ eusartDaliTxDataBits18 = EUSART_DALICFG_DALITXDATABITS_EIGHTEEN, ///< Each frame contains 18 data bits.
+ eusartDaliTxDataBits19 = EUSART_DALICFG_DALITXDATABITS_NINETEEN, ///< Each frame contains 19 data bits.
+ eusartDaliTxDataBits20 = EUSART_DALICFG_DALITXDATABITS_TWENTY, ///< Each frame contains 20 data bits.
+ eusartDaliTxDataBits21 = EUSART_DALICFG_DALITXDATABITS_TWENTYONE, ///< Each frame contains 21 data bits.
+ eusartDaliTxDataBits22 = EUSART_DALICFG_DALITXDATABITS_TWENTYTWO, ///< Each frame contains 22 data bits.
+ eusartDaliTxDataBits23 = EUSART_DALICFG_DALITXDATABITS_TWENTYEIGHT, ///< Each frame contains 23 data bits.
+ eusartDaliTxDataBits24 = EUSART_DALICFG_DALITXDATABITS_TWENTYFOUR, ///< Each frame contains 24 data bits.
+ eusartDaliTxDataBits25 = EUSART_DALICFG_DALITXDATABITS_TWENTYFIVE, ///< Each frame contains 25 data bits.
+ eusartDaliTxDataBits26 = EUSART_DALICFG_DALITXDATABITS_TWENTYSIX, ///< Each frame contains 26 data bits.
+ eusartDaliTxDataBits27 = EUSART_DALICFG_DALITXDATABITS_TWENTYSEVEN, ///< Each frame contains 27 data bits.
+ eusartDaliTxDataBits28 = EUSART_DALICFG_DALITXDATABITS_TWENTYEIGHT, ///< Each frame contains 28 data bits.
+ eusartDaliTxDataBits29 = EUSART_DALICFG_DALITXDATABITS_TWENTYNINE, ///< Each frame contains 29 data bits.
+ eusartDaliTxDataBits30 = EUSART_DALICFG_DALITXDATABITS_THIRTY, ///< Each frame contains 30 data bits.
+ eusartDaliTxDataBits31 = EUSART_DALICFG_DALITXDATABITS_THIRTYONE, ///< Each frame contains 31 data bits.
+ eusartDaliTxDataBits32 = EUSART_DALICFG_DALITXDATABITS_THIRTYTWO, ///< Each frame contains 32 data bits.
+} EUSART_DaliTxDatabits_TypeDef;
+
+/// DALI RX databits (8-32).
+typedef enum {
+ eusartDaliRxDataBits8 = EUSART_DALICFG_DALIRXDATABITS_EIGHT, ///< Each frame contains 8 data bits.
+ eusartDaliRxDataBits9 = EUSART_DALICFG_DALIRXDATABITS_NINE, ///< Each frame contains 9 data bits.
+ eusartDaliRxDataBits10 = EUSART_DALICFG_DALIRXDATABITS_TEN, ///< Each frame contains 10 data bits.
+ eusartDaliRxDataBits11 = EUSART_DALICFG_DALIRXDATABITS_ELEVEN, ///< Each frame contains 11 data bits.
+ eusartDaliRxDataBits12 = EUSART_DALICFG_DALIRXDATABITS_TWELVE, ///< Each frame contains 12 data bits.
+ eusartDaliRxDataBits13 = EUSART_DALICFG_DALIRXDATABITS_THIRTEEN, ///< Each frame contains 13 data bits.
+ eusartDaliRxDataBits14 = EUSART_DALICFG_DALIRXDATABITS_FOURTEEN, ///< Each frame contains 14 data bits.
+ eusartDaliRxDataBits15 = EUSART_DALICFG_DALIRXDATABITS_FIFTEEN, ///< Each frame contains 15 data bits.
+ eusartDaliRxDataBits16 = EUSART_DALICFG_DALIRXDATABITS_SIXTEEN, ///< Each frame contains 16 data bits.
+ eusartDaliRxDataBits17 = EUSART_DALICFG_DALIRXDATABITS_SEVENTEEN, ///< Each frame contains 17 data bits.
+ eusartDaliRxDataBits18 = EUSART_DALICFG_DALIRXDATABITS_EIGHTEEN, ///< Each frame contains 18 data bits.
+ eusartDaliRxDataBits19 = EUSART_DALICFG_DALIRXDATABITS_NINETEEN, ///< Each frame contains 19 data bits.
+ eusartDaliRxDataBits20 = EUSART_DALICFG_DALIRXDATABITS_TWENTY, ///< Each frame contains 20 data bits.
+ eusartDaliRxDataBits21 = EUSART_DALICFG_DALIRXDATABITS_TWENTYONE, ///< Each frame contains 21 data bits.
+ eusartDaliRxDataBits22 = EUSART_DALICFG_DALIRXDATABITS_TWENTYTWO, ///< Each frame contains 22 data bits.
+ eusartDaliRxDataBits23 = EUSART_DALICFG_DALIRXDATABITS_TWENTYEIGHT, ///< Each frame contains 23 data bits.
+ eusartDaliRxDataBits24 = EUSART_DALICFG_DALIRXDATABITS_TWENTYFOUR, ///< Each frame contains 24 data bits.
+ eusartDaliRxDataBits25 = EUSART_DALICFG_DALIRXDATABITS_TWENTYFIVE, ///< Each frame contains 25 data bits.
+ eusartDaliRxDataBits26 = EUSART_DALICFG_DALIRXDATABITS_TWENTYSIX, ///< Each frame contains 26 data bits.
+ eusartDaliRxDataBits27 = EUSART_DALICFG_DALIRXDATABITS_TWENTYSEVEN, ///< Each frame contains 27 data bits.
+ eusartDaliRxDataBits28 = EUSART_DALICFG_DALIRXDATABITS_TWENTYEIGHT, ///< Each frame contains 28 data bits.
+ eusartDaliRxDataBits29 = EUSART_DALICFG_DALIRXDATABITS_TWENTYNINE, ///< Each frame contains 29 data bits.
+ eusartDaliRxDataBits30 = EUSART_DALICFG_DALIRXDATABITS_THIRTY, ///< Each frame contains 30 data bits.
+ eusartDaliRxDataBits31 = EUSART_DALICFG_DALIRXDATABITS_THIRTYONE, ///< Each frame contains 31 data bits.
+ eusartDaliRxDataBits32 = EUSART_DALICFG_DALIRXDATABITS_THIRTYTWO, ///< Each frame contains 32 data bits.
+} EUSART_DaliRxDatabits_TypeDef;
+#endif /* EUSART_DALICFG_DALIEN */
+#endif /* EUSART_PRESENT */
+
+/*******************************************************************************
+ ******************************* STRUCTS ***********************************
+ ******************************************************************************/
+/// Advanced initialization structure.
+typedef struct {
+ /// Hardware flow control mode.
+ EUSART_HwFlowControl_TypeDef hwFlowControl;
+
+ /// Enable the collision Detection feature.
+ /// Internal (setting loopbackEnable) or external loopback must be done to use this feature.
+ bool collisionDetectEnable;
+
+ /// If true, data will be send with most significant bit first.
+ bool msbFirst;
+
+ /// Enable inversion of RX and/or TX signals.
+ EUSART_InvertIO_TypeDef invertIO;
+
+ /// Enable the automatic wake up from EM2 to EM1 for DMA RX operation.
+ bool dmaWakeUpOnRx;
+
+ /// Enable the automatic wake up from EM2 to EM1 for DMA TX operation.
+ bool dmaWakeUpOnTx;
+
+ /// Enable DMA requests blocking while framing or parity errors.
+ bool dmaHaltOnError;
+
+ /// Start frame that will enable RX operation. 0x00 Disable this feature.
+ uint8_t startFrame;
+
+ /// Enable automatic tristating of transmistter output when there is nothing to transmit.
+ bool txAutoTristate;
+
+ /// Enable EUSART capability to use a PRS channel as an input data line for the receiver.
+ /// The configured RX GPIO signal won't be routed to the EUSART receiver.
+ bool prsRxEnable;
+
+ /// PRS Channel used to transmit data from PRS to the EUSART.
+ EUSART_PrsChannel_TypeDef prsRxChannel;
+
+ /// Enable Multiprocessor mode. Address and data filtering using the 9th bit.
+ bool multiProcessorEnable;
+
+ /// Multiprocessor address bit value. If true, 9th bit of address frame must bit 1, 0 otherwise.
+ bool multiProcessorAddressBitHigh;
+} EUSART_AdvancedInit_TypeDef;
+
+/// Initialization structure.
+typedef struct {
+ /// Specifies whether TX and/or RX will be enabled when initialization completes.
+ EUSART_Enable_TypeDef enable;
+
+ /// EUSART reference clock assumed when configuring baud rate setup. Set
+ /// to 0 if using currently configured reference clock.
+ uint32_t refFreq;
+
+ /// Desired baud rate. If set to 0, Auto Baud feature is enabled and
+ /// the EUSART will wait for (0x55) frame to detect the Baudrate.
+ uint32_t baudrate;
+
+ /// Oversampling used.
+ EUSART_OVS_TypeDef oversampling;
+
+ /// Number of data bits in frame.
+ EUSART_Databits_TypeDef databits;
+
+ /// Parity mode to use.
+ EUSART_Parity_TypeDef parity;
+
+ /// Number of stop bits to use.
+ EUSART_Stopbits_TypeDef stopbits;
+
+ /// Majority Vote can be disabled for 16x, 8x and 6x oversampling modes.
+ EUSART_MajorityVote_TypeDef majorityVote;
+
+ /// Enable Loop Back configuration.
+ EUSART_LoopbackEnable_TypeDef loopbackEnable;
+
+ /// Advanced initialization structure pointer. It can be NULL.
+ EUSART_AdvancedInit_TypeDef *advancedSettings;
+} EUSART_UartInit_TypeDef;
+
+/// IrDA Initialization structure.
+typedef struct {
+ /// General EUSART initialization structure.
+ EUSART_UartInit_TypeDef init;
+
+ /// Enable the IrDA low frequency mode. Only RX operation are enabled.
+ bool irDALowFrequencyEnable;
+
+ /// Set to enable filter on IrDA demodulator.
+ EUSART_IrDARxFilterEnable_TypeDef irDARxFilterEnable;
+
+ /// Configure the pulse width generated by the IrDA modulator as a fraction
+ /// of the configured EUSART bit period.
+ EUSART_IrDAPulseWidth_Typedef irDAPulseWidth;
+} EUSART_IrDAInit_TypeDef;
+
+/// PRS Trigger initialization structure.
+typedef struct {
+ /// PRS to EUSART trigger mode.
+ EUSART_PrsTriggerEnable_TypeDef prs_trigger_enable;
+
+ /// PRS channel to be used to trigger auto transmission.
+ EUSART_PrsChannel_TypeDef prs_trigger_channel;
+} EUSART_PrsTriggerInit_TypeDef;
+
+#if defined(EUSART_PRESENT)
+/// SPI Advanced initialization structure.
+typedef struct {
+ /// Chip select polarity
+ EUSART_CsPolarity_TypeDef csPolarity;
+
+ /// Enable inversion of RX and/or TX signals.
+ EUSART_InvertIO_TypeDef invertIO;
+
+ /// Enable automatic chip select. CS is managed by the peripheral.
+ bool autoCsEnable;
+
+ /// If true, data will be send with most significant bit first.
+ bool msbFirst;
+
+ /// Auto CS setup time (before transmission) in baud cycles. Acceptable value ( 0 to 7 baud cycle).
+ uint8_t autoCsSetupTime;
+
+ /// Auto CS hold time (after transmission) in baud cycles. Acceptable value ( 0 to 7 baud cycle).
+ uint8_t autoCsHoldTime;
+
+ /// Inter-frame time in baud cycles. Acceptable value ( 0 to 7 baud cycle).
+ uint8_t autoInterFrameTime;
+
+ /// Enable AUTOTX mode. Transmits as long as the RX FIFO is not full.
+ /// Generates underflow interrupt if the TX FIFO is empty.
+ bool autoTxEnable;
+
+ /// Default transmitted data when the TXFIFO is empty.
+ uint16_t defaultTxData;
+
+ /// Enable the automatic wake up from EM2 to EM1 for DMA RX operation.
+ /// Only applicable to EM2 (low frequency) capable EUSART instances.
+ bool dmaWakeUpOnRx;
+
+ /// Enable EUSART capability to use a PRS channel as an input data line for the receiver.
+ /// The configured RX GPIO signal won't be routed to the EUSART receiver.
+ bool prsRxEnable;
+
+ /// PRS Channel used to transmit data from PRS to the EUSART.
+ EUSART_PrsChannel_TypeDef prsRxChannel;
+
+ /// Enable EUSART capability to use a PRS channel as an input SPI Clock.
+ /// Slave mode only.
+ bool prsClockEnable;
+
+ /// PRS Channel used to transmit SCLK from PRS to the EUSART.
+ EUSART_PrsChannel_TypeDef prsClockChannel;
+
+ /// Interrupt and status level of the Receive FIFO.
+ EUSART_RxFifoWatermark_TypeDef RxFifoWatermark;
+
+ /// Interrupt and status level of the Receive FIFO.
+ EUSART_TxFifoWatermark_TypeDef TxFifoWatermark;
+
+ /// Force load the first FIFO value.
+ bool forceLoad;
+
+ /// Setup window in bus clock cycles before the sampling edge of SCLK at word-boundary to avoid force load error.
+ uint8_t setupWindow;
+} EUSART_SpiAdvancedInit_TypeDef;
+
+/// SPI Initialization structure.
+typedef struct {
+ /// Specifies whether TX and/or RX will be enabled when initialization completes.
+ EUSART_Enable_TypeDef enable;
+
+ /// EUSART reference clock assumed when configuring baud rate setup. Set
+ /// to 0 if using currently configured reference clock.
+ uint32_t refFreq;
+
+ /// Desired bit rate in Hz.
+ /// Depending on EUSART instance clock, not all bitrates
+ /// are achievable as the divider is limited to 255.
+ uint32_t bitRate;
+
+ /// Number of data bits in frame.
+ EUSART_Databits_TypeDef databits;
+
+ /// Select to operate in master or slave mode.
+ bool master;
+
+ /// Clock polarity/phase mode.
+ EUSART_ClockMode_TypeDef clockMode;
+
+ /// Enable Loop Back configuration.
+ EUSART_LoopbackEnable_TypeDef loopbackEnable;
+
+ /// Advanced initialization structure pointer. It can be NULL.
+ EUSART_SpiAdvancedInit_TypeDef *advancedSettings;
+} EUSART_SpiInit_TypeDef;
+#endif /* EUSART_PRESENT */
+
+/// DALI Initialization structure.
+typedef struct {
+ /// General EUSART initialization structure.
+ EUSART_UartInit_TypeDef init;
+
+ /// Enable the DALI low frequency mode.
+ bool daliLowFrequencyEnable;
+
+#if defined(EUSART_DALICFG_DALIEN)
+ /// Number of TX data bits in frame.
+ EUSART_DaliTxDatabits_TypeDef TXdatabits;
+ /// Number of RX data bits in frame.
+ EUSART_DaliRxDatabits_TypeDef RXdatabits;
+#endif
+} EUSART_DaliInit_TypeDef;
+
+/// Default configuration for EUSART initialization structure in UART mode with high-frequency clock.
+#define EUSART_UART_INIT_DEFAULT_HF \
+ { \
+ eusartEnable, /* Enable RX/TX when initialization completed. */ \
+ 0, /* Use current configured reference clock for configuring baud rate.*/ \
+ 115200, /* 115200 bits/s. */ \
+ eusartOVS16, /* Oversampling x16. */ \
+ eusartDataBits8, /* 8 data bits. */ \
+ eusartNoParity, /* No parity. */ \
+ eusartStopbits1, /* 1 stop bit. */ \
+ eusartMajorityVoteEnable, /* Majority vote enabled. */ \
+ eusartLoopbackDisable, /* Loop back disabled. */ \
+ NULL, /* Default advanced settings. */ \
+ }
+
+/// Default start frame configuration, i.e. feature disabled.
+#define EUSART_DEFAULT_START_FRAME 0x00u
+
+/// Default configuration for EUSART advanced initialization structure.
+#define EUSART_ADVANCED_INIT_DEFAULT \
+ { \
+ eusartHwFlowControlNone, /* Flow control disabled. */ \
+ false, /* Collision detection disabled. */ \
+ false, /* Data is sent with the least significant bit first. */ \
+ eusartInvertIODisable, /* RX and TX signal active high. */ \
+ false, /* No DMA wake up on reception. */ \
+ false, /* No DMA wake up on transmission. */ \
+ false, /* Halt DMA on error disabled. */ \
+ EUSART_DEFAULT_START_FRAME, /* No start frame. */ \
+ false, /* TX auto tristate disabled. */ \
+ false, /* Do not use PRS signal as RX signal.*/ \
+ (EUSART_PrsChannel_TypeDef) 0u, /* EUSART RX connected to prs channel 0. */ \
+ false, /* Multiprocessor mode disabled. */ \
+ false, /* Multiprocessor address bit : 0.*/ \
+ }
+
+/// Default configuration for EUSART initialization structure in UART mode with low-frequency clock.
+#define EUSART_UART_INIT_DEFAULT_LF \
+ { \
+ eusartEnable, /* Enable RX/TX when initialization completed. */ \
+ 0, /* Use current configured reference clock for configuring baud rate.*/ \
+ 9600, /* 9600 bits/s. */ \
+ eusartOVS0, /* Oversampling disabled. */ \
+ eusartDataBits8, /* 8 data bits. */ \
+ eusartNoParity, /* No parity. */ \
+ eusartStopbits1, /* 1 stop bit. */ \
+ eusartMajorityVoteDisable, /* Majority vote enabled. */ \
+ eusartLoopbackDisable, /* Loop back disabled. */ \
+ NULL, /* Default advanced settings. */ \
+ }
+
+/// Default configuration for EUSART initialization structure in IrDA mode with high-frequency clock.
+#define EUSART_IRDA_INIT_DEFAULT_HF \
+ { \
+ EUSART_UART_INIT_DEFAULT_HF, /* Default high frequency configuration. */ \
+ false, /* Disable IrDA low frequency mode. */ \
+ eusartIrDARxFilterDisable, /* RX Filter disabled. */ \
+ eusartIrDAPulseWidthOne, /* Pulse width is set to 1/16. */ \
+ }
+
+/// Default configuration for EUSART initialization structure in IrDA mode with low-frequency clock.
+#define EUSART_IRDA_INIT_DEFAULT_LF \
+ { \
+ { \
+ eusartEnableRx, /* Enable RX when initialization completed (TX not allowed). */ \
+ 0, /* Use current configured reference clock for configuring baud rate.*/ \
+ 9600, /* 9600 bits/s. */ \
+ eusartOVS0, /* Oversampling disabled. */ \
+ eusartDataBits8, /* 8 data bits. */ \
+ eusartNoParity, /* No parity. */ \
+ eusartStopbits1, /* 1 stop bit. */ \
+ eusartMajorityVoteDisable, /* Majority vote enabled. */ \
+ eusartLoopbackDisable, /* Loop back disabled. */ \
+ NULL, /* Default advanced settings. */ \
+ }, \
+ true, /* Enable IrDA low frequency mode. */ \
+ eusartIrDARxFilterDisable, /* RX Filter disabled. */ \
+ eusartIrDAPulseWidthOne, /* Pulse width is set to 1. */ \
+ }
+
+#if defined(EUSART_PRESENT)
+/// Default advanced configuration for EUSART initialization structure in SPI mode with high-frequency clock.
+#define EUSART_SPI_ADVANCED_INIT_DEFAULT \
+ { \
+ eusartCsActiveLow, /* CS active low. */ \
+ eusartInvertIODisable, /* RX and TX signal active High. */ \
+ true, /* AutoCS enabled. */ \
+ false, /* Data is sent with the least significant bit first. */ \
+ 0u, /* CS setup time is 0 baud cycles */ \
+ 0u, /* CS hold time is 0 baud cycles */ \
+ 0u, /* Inter-frame time is 0 baud cycles */ \
+ false, /* AutoTX disabled. */ \
+ 0x0000, /* Default transmitted data is 0. */ \
+ false, /* No DMA wake up on reception. */ \
+ false, /* Do not use PRS signal as RX signal. */ \
+ (EUSART_PrsChannel_TypeDef) 0u, /* EUSART RX tied to prs channel 0. */ \
+ false, /* Do not use PRS signal as SCLK signal. */ \
+ (EUSART_PrsChannel_TypeDef) 1u, /* EUSART SCLCK tied to prs channel 1. */ \
+ eusartRxFiFoWatermark1Frame, /* RXFL status/IF set when RX FIFO has at least one frame in it */ \
+ eusartTxFiFoWatermark1Frame, /* TXFL status/IF set when TX FIFO has space for at least one more frame */ \
+ true, /* The first byte sent by the slave won't be the default value if a byte is made available \
+ after chip select is asserted. */ \
+ 0x04u, /* Setup window before the sampling edge of SCLK at word-boundary to avoid force load error. */ \
+ }
+
+/// Default configuration for EUSART initialization structure in SPI master mode with high-frequency clock.
+#define EUSART_SPI_MASTER_INIT_DEFAULT_HF \
+ { \
+ eusartEnable, /* Enable RX/TX when initialization completed. */ \
+ 0, /* Use current configured reference clock for configuring baud rate.*/ \
+ 10000000, /* 10 Mbits/s. */ \
+ eusartDataBits8, /* 8 data bits. */ \
+ true, /* Master mode enabled. */ \
+ eusartClockMode0, /* Clock idle low, sample on rising edge. */ \
+ eusartLoopbackDisable, /* Loop back disabled. */ \
+ NULL, /* Default advanced settings. */ \
+ }
+
+/// Default configuration for EUSART initialization structure in SPI slave mode with high-frequency clock.
+#define EUSART_SPI_SLAVE_INIT_DEFAULT_HF \
+ { \
+ eusartEnable, /* Enable RX/TX when initialization completed. */ \
+ 0, /* Use current configured reference clock for configuring baud rate.*/ \
+ 10000000, /* 10 Mbits/s. */ \
+ eusartDataBits8, /* 8 data bits. */ \
+ false, /* Master mode enabled. */ \
+ eusartClockMode0, /* Clock idle low, sample on rising edge. */ \
+ eusartLoopbackDisable, /* Loop back disabled. */ \
+ NULL, /* Default advanced settings. */ \
+ }
+
+#if defined(EUSART_DALICFG_DALIEN)
+/// Default configuration for EUSART initialization structure in DALI mode with high-frequency clock.
+/// Default configuration for EUSART advanced initialization structure.
+#define EUSART_ADVANCED_DALI_INIT_DEFAULT \
+ { \
+ eusartHwFlowControlNone, /* Flow control disabled. */ \
+ false, /* Collision detection disabled. */ \
+ true, /* Data is sent with the most significant bit first. */ \
+ eusartInvertIODisable, /* RX and TX signal active high. */ \
+ false, /* No DMA wake up on reception. */ \
+ false, /* No DMA wake up on transmission. */ \
+ false, /* Halt DMA on error disabled. */ \
+ EUSART_DEFAULT_START_FRAME, /* No start frame. */ \
+ false, /* TX auto tristate disabled. */ \
+ false, /* Do not use PRS signal as RX signal.*/ \
+ (EUSART_PrsChannel_TypeDef) 0u, /* EUSART RX connected to prs channel 0. */ \
+ false, /* Multiprocessor mode disabled. */ \
+ false, /* Multiprocessor address bit : 0.*/ \
+ }
+
+/// Default configuration for EUSART initialization structure in DALI mode with high-frequency clock.
+#define EUSART_UART_DALI_INIT_DEFAULT_HF \
+ { \
+ eusartEnable, /* Enable RX/TX when initialization completed. */ \
+ 0, /* Use current configured reference clock for configuring baud rate.*/ \
+ 1200, /* 1200 bits/s. */ \
+ eusartOVS16, /* Oversampling x16. */ \
+ eusartDataBits8, /* 8 data bits. */ \
+ eusartNoParity, /* No parity. */ \
+ eusartStopbits1, /* 1 stop bit. */ \
+ eusartMajorityVoteEnable, /* Majority vote enabled. */ \
+ eusartLoopbackDisable, /* Loop back disabled. */ \
+ NULL, /* Default advanced settings. */ \
+ }
+
+/// Default configuration for EUSART initialization structure in DALI mode with low-frequency clock.
+#define EUSART_UART_DALI_INIT_DEFAULT_LF \
+ { \
+ eusartEnable, /* Enable RX/TX when initialization completed. */ \
+ 0, /* Use current configured reference clock for configuring baud rate.*/ \
+ 1200, /* 1200 bits/s. */ \
+ eusartOVS0, /* Oversampling disabled. */ \
+ eusartDataBits8, /* 8 data bits. */ \
+ eusartNoParity, /* No parity. */ \
+ eusartStopbits1, /* 1 stop bit. */ \
+ eusartMajorityVoteDisable, /* Majority vote enabled. */ \
+ eusartLoopbackDisable, /* Loop back disabled. */ \
+ NULL, /* Default advanced settings. */ \
+ }
+
+/// Default configuration for EUSART initialization structure in DALI mode with high-frequency clock.
+#define EUSART_DALI_INIT_DEFAULT_HF \
+ { \
+ EUSART_UART_DALI_INIT_DEFAULT_HF, \
+ false, /* Disable DALI low frequency mode. */ \
+ eusartDaliTxDataBits16, /* TX 16 data bits. */ \
+ eusartDaliRxDataBits8, /* RX 8 data bits. */ \
+ } \
+
+/// Default configuration for EUSART initialization structure in DALI mode with low-frequency clock.
+#define EUSART_DALI_INIT_DEFAULT_LF \
+ { \
+ EUSART_UART_DALI_INIT_DEFAULT_LF, \
+ true, /* Enable DALI low frequency mode. */ \
+ eusartDaliTxDataBits16, /* TX 16 data bits. */ \
+ eusartDaliRxDataBits8, /* RX 8 data bits. */ \
+ } \
+
+#endif /* EUSART_DALICFG_DALIEN */
+#endif /* EUSART_PRESENT */
+
+/*******************************************************************************
+ ***************************** PROTOTYPES **********************************
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * Initialize EUSART when used in UART mode with the high frequency clock.
+ *
+ * @param eusart Pointer to the EUSART peripheral register block.
+ * @param init A pointer to the initialization structure.
+ ******************************************************************************/
+void EUSART_UartInitHf(EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init);
+
+/***************************************************************************//**
+ * Initialize EUSART when used in UART mode with the low frequency clock.
+ *
+ * @param eusart Pointer to the EUSART peripheral register block.
+ * @param init A pointer to the initialization structure.
+ ******************************************************************************/
+void EUSART_UartInitLf(EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init);
+
+/***************************************************************************//**
+ * Initialize EUSART when used in IrDA mode with the high or low
+ * frequency clock.
+ *
+ * @param eusart Pointer to the EUSART peripheral register block.
+ * @param irdaInit A pointer to the initialization structure.
+ ******************************************************************************/
+void EUSART_IrDAInit(EUSART_TypeDef *eusart,
+ const EUSART_IrDAInit_TypeDef *irdaInit);
+
+#if defined(EUSART_PRESENT)
+/***************************************************************************//**
+ * Initialize EUSART when used in SPI mode.
+ *
+ * @param eusart Pointer to the EUSART peripheral register block.
+ * @param init A pointer to the initialization structure.
+ ******************************************************************************/
+void EUSART_SpiInit(EUSART_TypeDef *eusart, const EUSART_SpiInit_TypeDef *init);
+
+#if defined(EUSART_DALICFG_DALIEN)
+/***************************************************************************//**
+ * Initialize EUSART when used in DALI mode with the high or low
+ * frequency clock.
+ *
+ * @param eusart Pointer to the EUSART peripheral register block.
+ * @param daliInit A pointer to the initialization structure.
+ ******************************************************************************/
+void EUSART_DaliInit(EUSART_TypeDef *eusart,
+ const EUSART_DaliInit_TypeDef *daliInit);
+
+#endif /* EUSART_DALICFG_DALIEN */
+#endif /* EUSART_PRESENT */
+
+/***************************************************************************//**
+ * Configure EUSART to its reset state.
+ *
+ * @param eusart Pointer to the EUSART peripheral register block.
+ ******************************************************************************/
+void EUSART_Reset(EUSART_TypeDef *eusart);
+
+/***************************************************************************//**
+ * Enable/disable EUSART receiver and/or transmitter.
+ *
+ * @param eusart Pointer to the EUSART peripheral register block.
+ * @param enable Select the status for the receiver and transmitter.
+ ******************************************************************************/
+void EUSART_Enable(EUSART_TypeDef *eusart, EUSART_Enable_TypeDef enable);
+
+/***************************************************************************//**
+ * Receive one 8 bit frame, (or part of 9 bit frame).
+ *
+ * @param eusart Pointer to the EUSART peripheral register block.
+ *
+ * @note This function is normally used to receive one frame when operating with
+ * frame length of 8 bits. See EUSART_RxExt() for reception of 9 bit frames.
+ * Notice that possible parity/stop bits are not considered a part of the
+ * specified frame bit length.
+ * @note This function will stall if buffer is empty until data is received.
+ *
+ * @return Data received.
+ ******************************************************************************/
+uint8_t EUSART_Rx(EUSART_TypeDef *eusart);
+
+/***************************************************************************//**
+ * Receive one 8-16 bit frame with extended information.
+ *
+ * @param eusart Pointer to the EUSART peripheral register block.
+ *
+ * @note This function is normally used to receive one frame and additional RX
+ * status information.
+ * @note This function will stall if buffer is empty until data is received.
+ *
+ * @return Data received and receive status.
+ ******************************************************************************/
+uint16_t EUSART_RxExt(EUSART_TypeDef *eusart);
+
+/***************************************************************************//**
+ * Transmit one frame.
+ *
+ * @param eusart Pointer to the EUSART peripheral register block.
+ * @param data Data to transmit.
+ *
+ * @note Depending on the frame length configuration, 8 (least significant) bits
+ * from @p data are transmitted. If the frame length is 9, 8 bits are
+ * transmitted from @p data. See EUSART_TxExt() for transmitting 9 bit frame
+ * with full control of all 9 bits.
+ * @note This function will stall if the 4 frame FIFO is full, until the buffer
+ * becomes available.
+ ******************************************************************************/
+void EUSART_Tx(EUSART_TypeDef *eusart, uint8_t data);
+
+/***************************************************************************//**
+ * Transmit one 8-9 bit frame with extended control.
+ *
+ * @param eusart Pointer to the EUSART peripheral register block.
+ * @param data Data to transmit.
+ *
+ * @note Possible parity/stop bits in asynchronous mode are not
+ * considered part of a specified frame bit length.
+ * @note This function will stall if buffer is full until the buffer becomes
+ * available.
+ ******************************************************************************/
+void EUSART_TxExt(EUSART_TypeDef *eusart, uint16_t data);
+
+#if defined(EUSART_PRESENT)
+/***************************************************************************//**
+ * Transmit one 8-16 bit frame and return received data.
+ *
+ * @param eusart Pointer to the EUSART peripheral register block.
+ * @param data Data to transmit.
+ *
+ * @return Data received and receive status.
+ *
+ * @note SPI master mode only.
+ * @note This function will stall if the TX buffer is full until the buffer becomes
+ * available.
+ ******************************************************************************/
+uint16_t EUSART_Spi_TxRx(EUSART_TypeDef *eusart, uint16_t data);
+
+#if defined(EUSART_DALICFG_DALIEN)
+/***************************************************************************//**
+ * Transmit one DALI frame.
+ *
+ * @param eusart Pointer to the EUSART peripheral register block.
+ * @param data Data to transmit.
+ *
+ * @note Depending on the TXdatabits configuration, N (least significant) bits
+ * from @p data are transmitted.
+ * @note This function will stall if the 16 frame FIFO is full, until the buffer
+ * becomes available.
+ ******************************************************************************/
+void EUSART_Dali_Tx(EUSART_TypeDef *eusart, uint32_t data);
+
+/***************************************************************************//**
+ * Receive one 8-32 bit DALI frame.
+ *
+ * @param eusart Pointer to the EUSART peripheral register block.
+ *
+ * @note This function is normally used to receive one DALI frame (RXdatabits).
+ * @note This function will stall if the 16 frame FIFO is empty until new
+ * data is received.
+ *
+ * @return Data received. Depending on the RXdatabits configuration, N
+ * (least significant) bits are returned.
+ ******************************************************************************/
+uint32_t EUSART_Dali_Rx(EUSART_TypeDef *eusart);
+#endif /* EUSART_DALICFG_DALIEN */
+#endif /* EUSART_PRESENT */
+
+/***************************************************************************//**
+ * Configure the baudrate (or as close as possible to a specified baudrate).
+ *
+ * @param eusart Pointer to the EUSART peripheral register block.
+ * @param refFreq The EUSART reference clock frequency in Hz that will be used.
+ * If set to 0, the currently configured peripheral clock is
+ * used.
+ * @param baudrate A baudrate to try to achieve.
+ ******************************************************************************/
+void EUSART_BaudrateSet(EUSART_TypeDef *eusart,
+ uint32_t refFreq,
+ uint32_t baudrate);
+
+/***************************************************************************//**
+ * Get the current baudrate.
+ *
+ * @param eusart Pointer to the EUSART peripheral register block.
+ *
+ * @return The current baudrate.
+ ******************************************************************************/
+uint32_t EUSART_BaudrateGet(EUSART_TypeDef *eusart);
+
+/***************************************************************************//**
+ * Enable/Disable reception operation until the configured start frame is
+ * received.
+ *
+ * @param eusart Pointer to the EUSART peripheral register block.
+ * @param enable Select the receiver blocking status.
+ ******************************************************************************/
+void EUSART_RxBlock(EUSART_TypeDef *eusart,
+ EUSART_BlockRx_TypeDef enable);
+
+/***************************************************************************//**
+ * Enable/Disable the tristating of the transmitter output.
+ *
+ * @param eusart Pointer to the EUSART peripheral register block.
+ * @param enable Select the transmitter tristate status.
+ ******************************************************************************/
+void EUSART_TxTristateSet(EUSART_TypeDef *eusart,
+ EUSART_TristateTx_TypeDef enable);
+
+/***************************************************************************//**
+ * Initialize the automatic enabling of transmissions and/or reception using
+ * the PRS as a trigger.
+ * @note
+ * Initialize EUSART with sl_eusart_initHf() or sl_eusart_initLf() before
+ * enabling the PRS trigger.
+ *
+ * @param eusart Pointer to the EUSART peripheral register block.
+ * @param init Pointer to the initialization structure.
+ ******************************************************************************/
+void EUSART_PrsTriggerEnable(EUSART_TypeDef *eusart,
+ const EUSART_PrsTriggerInit_TypeDef *init);
+
+/***************************************************************************//**
+ * Get EUSART STATUS register.
+ *
+ * @param eusart Pointer to the EUSART peripheral register block.
+ *
+ * @return STATUS register value.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t EUSART_StatusGet(EUSART_TypeDef *eusart)
+{
+ return eusart->STATUS;
+}
+
+/***************************************************************************//**
+ * Clear one or more pending EUSART interrupts.
+ *
+ * @param eusart Pointer to the EUSART peripheral register block.
+ *
+ * @param flags Pending EUSART interrupt source to clear. Use a bitwise logic OR
+ * combination of valid interrupt flags for EUSART module
+ * (EUSART_IF_nnn).
+ ******************************************************************************/
+__STATIC_INLINE void EUSART_IntClear(EUSART_TypeDef *eusart, uint32_t flags)
+{
+ eusart->IF_CLR = flags;
+}
+
+/***************************************************************************//**
+ * Disable one or more EUSART interrupts.
+ *
+ * @param eusart Pointer to the EUSART peripheral register block.
+ *
+ * @param flags Pending EUSART interrupt source to clear. Use a bitwise logic OR
+ * combination of valid interrupt flags for EUSART module
+ * (EUSART_IF_nnn).
+ ******************************************************************************/
+__STATIC_INLINE void EUSART_IntDisable(EUSART_TypeDef *eusart, uint32_t flags)
+{
+ eusart->IEN_CLR = flags;
+}
+
+/***************************************************************************//**
+ * Enable one or more EUSART interrupts.
+ *
+ * @param eusart Pointer to the EUSART peripheral register block.
+ *
+ * @param flags Pending EUSART interrupt source to clear. Use a bitwise logic OR
+ * combination of valid interrupt flags for EUSART module
+ * (EUSART_IF_nnn).
+ ******************************************************************************/
+__STATIC_INLINE void EUSART_IntEnable(EUSART_TypeDef *eusart, uint32_t flags)
+{
+ eusart->IEN_SET = flags;
+}
+
+/***************************************************************************//**
+ * Get pending EUSART interrupt flags.
+ *
+ * @param eusart Pointer to the EUSART peripheral register block.
+ *
+ * @return Pending EUSART interrupt sources.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t EUSART_IntGet(EUSART_TypeDef *eusart)
+{
+ return eusart->IF;
+}
+
+/***************************************************************************//**
+ * Get enabled and pending EUSART interrupt flags.
+ * Useful for handling more interrupt sources in the same interrupt handler.
+ *
+ * @param eusart Pointer to the EUSART peripheral register block.
+ *
+ * @return Pending and enabled EUSART interrupt sources.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t EUSART_IntGetEnabled(EUSART_TypeDef *eusart)
+{
+ uint32_t tmp;
+
+ /* Store EUSARTx->IEN in temporary variable in order to define explicit order
+ * of volatile accesses. */
+ tmp = eusart->IEN;
+
+ /* Bitwise AND of pending and enabled interrupts */
+ return eusart->IF & tmp;
+}
+
+/***************************************************************************//**
+ * Set one or more pending EUSART interrupts from SW.
+ *
+ * @param eusart Pointer to the EUSART peripheral register block.
+ *
+ * @param flags Interrupt source(s) to set to pending. Use a bitwise logic OR
+ * combination of valid interrupt flags for EUSART module
+ * (EUSART_IF_nnn).
+ ******************************************************************************/
+__STATIC_INLINE void EUSART_IntSet(EUSART_TypeDef *eusart, uint32_t flags)
+{
+ eusart->IF_SET = flags;
+}
+
+/** @} (end addtogroup eusart) */
+#endif /* defined(EUART_PRESENT) || defined(EUSART_PRESENT) */
+#endif /* EM_EUSART_H */
diff --git a/mcu/efr/common/vendor/em_eusart_compat.h b/mcu/efr/common/vendor/em_eusart_compat.h
new file mode 100644
index 00000000..50822e2e
--- /dev/null
+++ b/mcu/efr/common/vendor/em_eusart_compat.h
@@ -0,0 +1,218 @@
+/***************************************************************************//**
+ * @file
+ * @brief EUSART Compatibility Header
+ *******************************************************************************
+ * # License
+ * Copyright 2020 Silicon Laboratories Inc. www.silabs.com
+ *******************************************************************************
+ *
+ * SPDX-License-Identifier: Zlib
+ *
+ * The licensor of this software is Silicon Laboratories Inc.
+ *
+ * This software is provided 'as-is', without any express or implied
+ * warranty. In no event will the authors be held liable for any damages
+ * arising from the use of this software.
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software
+ * in a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ ******************************************************************************/
+
+#ifndef EM_EUSART_COMPAT_H
+#define EM_EUSART_COMPAT_H
+
+#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2)
+
+#define EUSART_IF_TXCIF EUSART_IF_TXC
+#define _EUSART_IF_TXCIF_SHIFT _EUSART_IF_TXC_SHIFT
+#define _EUSART_IF_TXCIF_MASK _EUSART_IF_TXC_MASK
+#define _EUSART_IF_TXCIF_DEFAULT _EUSART_IF_TXC_DEFAULT
+#define EUSART_IF_TXCIF_DEFAULT EUSART_IF_TXC_DEFAULT
+
+#define EUSART_IF_TXFLIF EUSART_IF_TXFL
+#define _EUSART_IF_TXFLIF_SHIFT _EUSART_IF_TXFL_SHIFT
+#define _EUSART_IF_TXFLIF_MASK _EUSART_IF_TXFL_MASK
+#define _EUSART_IF_TXFLIF_DEFAULT _EUSART_IF_TXFL_DEFAULT
+#define EUSART_IF_TXFLIF_DEFAULT EUSART_IF_TXFL_DEFAULT
+
+#define EUSART_IF_RXFLIF EUSART_IF_RXFL
+#define _EUSART_IF_RXFLIF_SHIFT _EUSART_IF_RXFL_SHIFT
+#define _EUSART_IF_RXFLIF_MASK _EUSART_IF_RXFL_MASK
+#define _EUSART_IF_RXFLIF_DEFAULT _EUSART_IF_RXFL_DEFAULT
+#define EUSART_IF_RXFLIF_DEFAULT EUSART_IF_RXFL_DEFAULT
+
+#define EUSART_IF_RXFULLIF EUSART_IF_RXFULL
+#define _EUSART_IF_RXFULLIF_SHIFT _EUSART_IF_RXFULL_SHIFT
+#define _EUSART_IF_RXFULLIF_MASK _EUSART_IF_RXFULL_MASK
+#define _EUSART_IF_RXFULLIF_DEFAULT _EUSART_IF_RXFULL_DEFAULT
+#define EUSART_IF_RXFULLIF_DEFAULT EUSART_IF_RXFULL_DEFAULT
+
+#define EUSART_IF_RXOFIF EUSART_IF_RXOF
+#define _EUSART_IF_RXOFIF_SHIFT _EUSART_IF_RXOF_SHIFT
+#define _EUSART_IF_RXOFIF_MASK _EUSART_IF_RXOF_MASK
+#define _EUSART_IF_RXOFIF_DEFAULT _EUSART_IF_RXOF_DEFAULT
+#define EUSART_IF_RXOFIF_DEFAULT EUSART_IF_RXOF_DEFAULT
+
+#define EUSART_IF_RXUFIF EUSART_IF_RXUF
+#define _EUSART_IF_RXUFIF_SHIFT _EUSART_IF_RXUF_SHIFT
+#define _EUSART_IF_RXUFIF_MASK _EUSART_IF_RXUF_MASK
+#define _EUSART_IF_RXUFIF_DEFAULT _EUSART_IF_RXUF_DEFAULT
+#define EUSART_IF_RXUFIF_DEFAULT EUSART_IF_RXUF_DEFAULT
+
+#define EUSART_IF_TXOFIF EUSART_IF_TXOF
+#define _EUSART_IF_TXOFIF_SHIFT _EUSART_IF_TXOF_SHIFT
+#define _EUSART_IF_TXOFIF_MASK _EUSART_IF_TXOF_MASK
+#define _EUSART_IF_TXOFIF_DEFAULT _EUSART_IF_TXOF_DEFAULT
+#define EUSART_IF_TXOFIF_DEFAULT EUSART_IF_TXOF_DEFAULT
+
+#define EUSART_IF_PERRIF EUSART_IF_PERR
+#define _EUSART_IF_PERRIF_SHIFT _EUSART_IF_PERR_SHIFT
+#define _EUSART_IF_PERRIF_MASK _EUSART_IF_PERR_MASK
+#define _EUSART_IF_PERRIF_DEFAULT _EUSART_IF_PERR_DEFAULT
+#define EUSART_IF_PERRIF_DEFAULT EUSART_IF_PERR_DEFAULT
+
+#define EUSART_IF_FERRIF EUSART_IF_FERR
+#define _EUSART_IF_FERRIF_SHIFT _EUSART_IF_FERR_SHIFT
+#define _EUSART_IF_FERRIF_MASK _EUSART_IF_FERR_MASK
+#define _EUSART_IF_FERRIF_DEFAULT _EUSART_IF_FERR_DEFAULT
+#define EUSART_IF_FERRIF_DEFAULT EUSART_IF_FERR_DEFAULT
+
+#define EUSART_IF_MPAFIF EUSART_IF_MPAF
+#define _EUSART_IF_MPAFIF_SHIFT _EUSART_IF_MPAF_SHIFT
+#define _EUSART_IF_MPAFIF_MASK _EUSART_IF_MPAF_MASK
+#define _EUSART_IF_MPAFIF_DEFAULT _EUSART_IF_MPAF_DEFAULT
+#define EUSART_IF_MPAFIF_DEFAULT EUSART_IF_MPAF_DEFAULT
+
+#define EUSART_IF_CCFIF EUSART_IF_CCF
+#define _EUSART_IF_CCFIF_SHIFT _EUSART_IF_CCF_SHIFT
+#define _EUSART_IF_CCFIF_MASK _EUSART_IF_CCF_MASK
+#define _EUSART_IF_CCFIF_DEFAULT _EUSART_IF_CCF_DEFAULT
+#define EUSART_IF_CCFIF_DEFAULT EUSART_IF_CCF_DEFAULT
+
+#define EUSART_IF_TXIDLEIF EUSART_IF_TXIDLE
+#define _EUSART_IF_TXIDLEIF_SHIFT _EUSART_IF_TXIDLE_SHIFT
+#define _EUSART_IF_TXIDLEIF_MASK _EUSART_IF_TXIDLE_MASK
+#define _EUSART_IF_TXIDLEIF_DEFAULT _EUSART_IF_TXIDLE_DEFAULT
+#define EUSART_IF_TXIDLEIF_DEFAULT EUSART_IF_TXIDLE_DEFAULT
+
+#define EUSART_IF_STARTFIF EUSART_IF_STARTF
+#define _EUSART_IF_STARTFIF_SHIFT _EUSART_IF_STARTF_SHIFT
+#define _EUSART_IF_STARTFIF_MASK _EUSART_IF_STARTF_MASK
+#define _EUSART_IF_STARTFIF_DEFAULT _EUSART_IF_STARTF_DEFAULT
+#define EUSART_IF_STARTFIF_DEFAULT EUSART_IF_STARTF_DEFAULT
+
+#define EUSART_IF_SIGFIF EUSART_IF_SIGF
+#define _EUSART_IF_SIGFIF_SHIFT _EUSART_IF_SIGF_SHIFT
+#define _EUSART_IF_SIGFIF_MASK _EUSART_IF_SIGF_MASK
+#define _EUSART_IF_SIGFIF_DEFAULT _EUSART_IF_SIGF_DEFAULT
+#define EUSART_IF_SIGFIF_DEFAULT EUSART_IF_SIGF_DEFAULT
+
+#define EUSART_IF_AUTOBAUDDONEIF EUSART_IF_AUTOBAUDDONE
+#define _EUSART_IF_AUTOBAUDDONEIF_SHIFT _EUSART_IF_AUTOBAUDDONE_SHIFT
+#define _EUSART_IF_AUTOBAUDDONEIF_MASK _EUSART_IF_AUTOBAUDDONE_MASK
+#define _EUSART_IF_AUTOBAUDDONEIF_DEFAULT _EUSART_IF_AUTOBAUDDONE_DEFAULT
+#define EUSART_IF_AUTOBAUDDONEIF_DEFAULT EUSART_IF_AUTOBAUDDONE_DEFAULT
+
+#define EUSART_IEN_TXCIEN EUSART_IEN_TXC
+#define _EUSART_IEN_TXCIEN_SHIFT _EUSART_IEN_TXC_SHIFT
+#define _EUSART_IEN_TXCIEN_MASK _EUSART_IEN_TXC_MASK
+#define _EUSART_IEN_TXCIEN_DEFAULT _EUSART_IEN_TXC_DEFAULT
+#define EUSART_IEN_TXCIEN_DEFAULT EUSART_IEN_TXC_DEFAULT
+
+#define EUSART_IEN_TXFLIEN EUSART_IEN_TXFL
+#define _EUSART_IEN_TXFLIEN_SHIFT _EUSART_IEN_TXFL_SHIFT
+#define _EUSART_IEN_TXFLIEN_MASK _EUSART_IEN_TXFL_MASK
+#define _EUSART_IEN_TXFLIEN_DEFAULT _EUSART_IEN_TXFL_DEFAULT
+#define EUSART_IEN_TXFLIEN_DEFAULT EUSART_IEN_TXFL_DEFAULT
+
+#define EUSART_IEN_RXFLIEN EUSART_IEN_RXFL
+#define _EUSART_IEN_RXFLIEN_SHIFT _EUSART_IEN_RXFL_SHIFT
+#define _EUSART_IEN_RXFLIEN_MASK _EUSART_IEN_RXFL_MASK
+#define _EUSART_IEN_RXFLIEN_DEFAULT _EUSART_IEN_RXFL_DEFAULT
+#define EUSART_IEN_RXFLIEN_DEFAULT EUSART_IEN_RXFL_DEFAULT
+
+#define EUSART_IEN_RXFULLIEN EUSART_IEN_RXFULL
+#define _EUSART_IEN_RXFULLIEN_SHIFT _EUSART_IEN_RXFULL_SHIFT
+#define _EUSART_IEN_RXFULLIEN_MASK _EUSART_IEN_RXFULL_MASK
+#define _EUSART_IEN_RXFULLIEN_DEFAULT _EUSART_IEN_RXFULL_DEFAULT
+#define EUSART_IEN_RXFULLIEN_DEFAULT EUSART_IEN_RXFULL_DEFAULT
+
+#define EUSART_IEN_RXOFIEN EUSART_IEN_RXOF
+#define _EUSART_IEN_RXOFIEN_SHIFT _EUSART_IEN_RXOF_SHIFT
+#define _EUSART_IEN_RXOFIEN_MASK _EUSART_IEN_RXOF_MASK
+#define _EUSART_IEN_RXOFIEN_DEFAULT _EUSART_IEN_RXOF_DEFAULT
+#define EUSART_IEN_RXOFIEN_DEFAULT EUSART_IEN_RXOF_DEFAULT
+
+#define EUSART_IEN_RXUFIEN EUSART_IEN_RXUF
+#define _EUSART_IEN_RXUFIEN_SHIFT _EUSART_IEN_RXUF_SHIFT
+#define _EUSART_IEN_RXUFIEN_MASK _EUSART_IEN_RXUF_MASK
+#define _EUSART_IEN_RXUFIEN_DEFAULT _EUSART_IEN_RXUF_DEFAULT
+#define EUSART_IEN_RXUFIEN_DEFAULT EUSART_IEN_RXUF_DEFAULT
+
+#define EUSART_IEN_TXOFIEN EUSART_IEN_TXOF
+#define _EUSART_IEN_TXOFIEN_SHIFT _EUSART_IEN_TXOF_SHIFT
+#define _EUSART_IEN_TXOFIEN_MASK _EUSART_IEN_TXOF_MASK
+#define _EUSART_IEN_TXOFIEN_DEFAULT _EUSART_IEN_TXOF_DEFAULT
+#define EUSART_IEN_TXOFIEN_DEFAULT EUSART_IEN_TXOF_DEFAULT
+
+#define EUSART_IEN_PERRIEN EUSART_IEN_PERR
+#define _EUSART_IEN_PERRIEN_SHIFT _EUSART_IEN_PERR_SHIFT
+#define _EUSART_IEN_PERRIEN_MASK _EUSART_IEN_PERR_MASK
+#define _EUSART_IEN_PERRIEN_DEFAULT _EUSART_IEN_PERR_DEFAULT
+#define EUSART_IEN_PERRIEN_DEFAULT EUSART_IEN_PERR_DEFAULT
+
+#define EUSART_IEN_FERRIEN EUSART_IEN_FERR
+#define _EUSART_IEN_FERRIEN_SHIFT _EUSART_IEN_FERR_SHIFT
+#define _EUSART_IEN_FERRIEN_MASK _EUSART_IEN_FERR_MASK
+#define _EUSART_IEN_FERRIEN_DEFAULT _EUSART_IEN_FERR_DEFAULT
+#define EUSART_IEN_FERRIEN_DEFAULT EUSART_IEN_FERR_DEFAULT
+
+#define EUSART_IEN_MPAFIEN EUSART_IEN_MPAF
+#define _EUSART_IEN_MPAFIEN_SHIFT _EUSART_IEN_MPAF_SHIFT
+#define _EUSART_IEN_MPAFIEN_MASK _EUSART_IEN_MPAF_MASK
+#define _EUSART_IEN_MPAFIEN_DEFAULT _EUSART_IEN_MPAF_DEFAULT
+#define EUSART_IEN_MPAFIEN_DEFAULT EUSART_IEN_MPAF_DEFAULT
+
+#define EUSART_IEN_CCFIEN EUSART_IEN_CCF
+#define _EUSART_IEN_CCFIEN_SHIFT _EUSART_IEN_CCF_SHIFT
+#define _EUSART_IEN_CCFIEN_MASK _EUSART_IEN_CCF_MASK
+#define _EUSART_IEN_CCFIEN_DEFAULT _EUSART_IEN_CCF_DEFAULT
+#define EUSART_IEN_CCFIEN_DEFAULT EUSART_IEN_CCF_DEFAULT
+
+#define EUSART_IEN_TXIDLEIEN EUSART_IEN_TXIDLE
+#define _EUSART_IEN_TXIDLEIEN_SHIFT _EUSART_IEN_TXIDLE_SHIFT
+#define _EUSART_IEN_TXIDLEIEN_MASK _EUSART_IEN_TXIDLE_MASK
+#define _EUSART_IEN_TXIDLEIEN_DEFAULT _EUSART_IEN_TXIDLE_DEFAULT
+#define EUSART_IEN_TXIDLEIEN_DEFAULT EUSART_IEN_TXIDLE_DEFAULT
+
+#define EUSART_IEN_STARTFIEN EUSART_IEN_STARTF
+#define _EUSART_IEN_STARTFIEN_SHIFT _EUSART_IEN_STARTF_SHIFT
+#define _EUSART_IEN_STARTFIEN_MASK _EUSART_IEN_STARTF_MASK
+#define _EUSART_IEN_STARTFIEN_DEFAULT _EUSART_IEN_STARTF_DEFAULT
+#define EUSART_IEN_STARTFIEN_DEFAULT EUSART_IEN_STARTF_DEFAULT
+
+#define EUSART_IEN_SIGFIEN EUSART_IEN_SIGF
+#define _EUSART_IEN_SIGFIEN_SHIFT _EUSART_IEN_SIGF_SHIFT
+#define _EUSART_IEN_SIGFIEN_MASK _EUSART_IEN_SIGF_MASK
+#define _EUSART_IEN_SIGFIEN_DEFAULT _EUSART_IEN_SIGF_DEFAULT
+#define EUSART_IEN_SIGFIEN_DEFAULT EUSART_IEN_SIGF_DEFAULT
+
+#define EUSART_IEN_AUTOBAUDDONEIEN EUSART_IEN_AUTOBAUDDONE
+#define _EUSART_IEN_AUTOBAUDDONEIEN_SHIFT _EUSART_IEN_AUTOBAUDDONE_SHIFT
+#define _EUSART_IEN_AUTOBAUDDONEIEN_MASK _EUSART_IEN_AUTOBAUDDONE_MASK
+#define _EUSART_IEN_AUTOBAUDDONEIEN_DEFAULT _EUSART_IEN_AUTOBAUDDONE_DEFAULT
+#define EUSART_IEN_AUTOBAUDDONEIEN_DEFAULT EUSART_IEN_AUTOBAUDDONE_DEFAULT
+
+#endif // _SILICON_LABS_32B_SERIES_2_CONFIG_2
+
+#endif
diff --git a/mcu/efr/common/vendor/rail_lib/chip/efr32/efr32xg2x/rail_chip_specific.h b/mcu/efr/common/vendor/rail_lib/chip/efr32/efr32xg2x/rail_chip_specific.h
index ee550214..526f02b9 100644
--- a/mcu/efr/common/vendor/rail_lib/chip/efr32/efr32xg2x/rail_chip_specific.h
+++ b/mcu/efr/common/vendor/rail_lib/chip/efr32/efr32xg2x/rail_chip_specific.h
@@ -30,129 +30,112 @@
******************************************************************************/
#ifndef __RAIL_CHIP_SPECIFIC_H_
+#if !defined(__RAIL_TYPES_H__) && !defined(DOXYGEN_SHOULD_SKIP_THIS)
+#warning rail_chip_specific.h should only be included by rail_types.h
+#include "rail_types.h" // Force rail_chip_specific.h only within rail_types.h
+#else // __RAIL_TYPES_H__
+/// Include guard
#define __RAIL_CHIP_SPECIFIC_H_
-// Include standard type headers to help define structures
-#include
-#include
-#include
-
-#include "em_gpio.h"
-
-#include "rail_types.h"
#include "rail_features.h"
#ifdef __cplusplus
extern "C" {
#endif
-// -----------------------------------------------------------------------------
-// Multiprotocol
-// -----------------------------------------------------------------------------
-
/**
- * @def TRANSITION_TIME_US
- * @brief Time it takes to take care of protocol switching.
+ * @addtogroup General_EFR32XG2 EFR32xG2
+ * @{
+ * @brief EFR32xG2-specific initialization data types
+ * @ingroup General
*/
-#define TRANSITION_TIME_US 510
/**
- * @def EFR32XG21_RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE
- * @brief The size in 32-bit words of RAIL_SchedulerStateBuffer_t to store
- * RAIL multiprotocol internal state.
+ * A placeholder for a chip-specific RAIL handle. Using NULL as a RAIL handle is
+ * not recommended. As a result, another value that can't be de-referenced is used.
+ *
+ * This generic handle can and should be used for RAIL APIs that are called
+ * prior to RAIL initialization.
*/
-#define EFR32XG21_RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE 26
+#define RAIL_EFR32_HANDLE ((RAIL_Handle_t)0xFFFFFFFFUL)
-/**
- * @def EFR32XG22_RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE
- * @brief The size in 32-bit words of RAIL_SchedulerStateBuffer_t to store
- * RAIL multiprotocol internal state.
- */
-#define EFR32XG22_RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE 26
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
/**
- * @def EFR32XG23_RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE
- * @brief The size in 32-bit words of RAIL_SchedulerStateBuffer_t to store
- * RAIL multiprotocol internal state.
+ * @def RAIL_EFR32XG21_STATE_BUFFER_BYTES
+ * @brief The EFR32XG21 series size needed for
+ * \ref RAIL_StateBufferEntry_t::bufferBytes.
*/
-#define EFR32XG23_RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE 25
-
-#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 1)
-#define RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE EFR32XG21_RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE
-#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 2)
-#define RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE EFR32XG22_RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE
-#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 3)
-#define RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE EFR32XG23_RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE
-#else
-#error "Unsupported platform!"
-#endif //_SILICON_LABS_32B_SERIES_2_CONFIG
+#define RAIL_EFR32XG21_STATE_BUFFER_BYTES 544
/**
- * @typedef RAIL_SchedulerStateBuffer_t
- * @brief A buffer used to store multiprotocol scheduler internal state.
- *
- * This buffer must be allocated in application global read-write memory
- * that persists for the duration of RAIL usage. It cannot be allocated
- * in read-only memory or on the call stack.
+ * @def RAIL_EFR32XG22_STATE_BUFFER_BYTES
+ * @brief The EFR32XG22 series size needed for
+ * \ref RAIL_StateBufferEntry_t::bufferBytes.
*/
-typedef uint32_t RAIL_SchedulerStateBuffer_t[RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE];
+#define RAIL_EFR32XG22_STATE_BUFFER_BYTES 568
/**
- * @struct RAILSched_Config_t
- * @brief A multiprotocol scheduler configuration and internal state.
- *
- * This buffer must be allocated in application global read-write memory
- * that persists for the duration of RAIL usage. It cannot be allocated
- * in read-only memory or on the call stack.
+ * @def RAIL_EFR32XG23_STATE_BUFFER_BYTES
+ * @brief The EFR32XG23 series size needed for
+ * \ref RAIL_StateBufferEntry_t::bufferBytes.
*/
-typedef struct RAILSched_Config {
- RAIL_SchedulerStateBuffer_t buffer; /**< An internal state buffer. */
-} RAILSched_Config_t;
+#define RAIL_EFR32XG23_STATE_BUFFER_BYTES 568
/**
- * @def EFR32XG21_RAIL_STATE_UINT32_BUFFER_SIZE
- * @brief The size, in 32-bit words, of RAIL_StateBuffer_t to store RAIL
- * internal state for the EFR32XG21 series.
+ * @def RAIL_EFR32XG24_STATE_BUFFER_BYTES
+ * @brief The EFR32XG24 series size needed for
+ * \ref RAIL_StateBufferEntry_t::bufferBytes.
*/
-#define EFR32XG21_RAIL_STATE_UINT32_BUFFER_SIZE 102
+#define RAIL_EFR32XG24_STATE_BUFFER_BYTES 560
/**
- * @def EFR32XG22_RAIL_STATE_UINT32_BUFFER_SIZE
- * @brief The size, in 32-bit words, of RAIL_StateBuffer_t to store RAIL
- * internal state for the EFR32XG22 series.
+ * @def RAIL_EFR32XG25_STATE_BUFFER_BYTES
+ * @brief The EFR32XG25 series size needed for
+ * \ref RAIL_StateBufferEntry_t::bufferBytes.
*/
-#define EFR32XG22_RAIL_STATE_UINT32_BUFFER_SIZE 104
+#define RAIL_EFR32XG25_STATE_BUFFER_BYTES 576
/**
- * @def EFR32XG23_RAIL_STATE_UINT32_BUFFER_SIZE
- * @brief The size, in 32-bit words, of RAIL_StateBuffer_t to store RAIL
- * internal state for the EFR32XG23 series.
+ * @def RAIL_STATE_BUFFER_BYTES
+ * @brief The size needed for \ref RAIL_StateBufferEntry_t::bufferBytes
+ * on this platform for this radio. This compile-time size may be slightly
+ * larger than what \ref RAIL_GetStateBufferSize() determines at run-time.
*/
-#define EFR32XG23_RAIL_STATE_UINT32_BUFFER_SIZE 82
-
#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 1)
-#define RAIL_STATE_UINT32_BUFFER_SIZE EFR32XG21_RAIL_STATE_UINT32_BUFFER_SIZE
+#define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG21_STATE_BUFFER_BYTES
#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 2)
-#define RAIL_STATE_UINT32_BUFFER_SIZE EFR32XG22_RAIL_STATE_UINT32_BUFFER_SIZE
+#define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG22_STATE_BUFFER_BYTES
#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 3)
-#define RAIL_STATE_UINT32_BUFFER_SIZE EFR32XG23_RAIL_STATE_UINT32_BUFFER_SIZE
+#define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG23_STATE_BUFFER_BYTES
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 4)
+#define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG24_STATE_BUFFER_BYTES
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 5)
+#define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG25_STATE_BUFFER_BYTES
#else
+#define RAIL_STATE_BUFFER_BYTES 0 // Sate Doxygen
#error "Unsupported platform!"
-#endif //_SILICON_LABS_32B_SERIES_2_CONFIG
+#endif
+
+#endif//DOXYGEN_SHOULD_SKIP_THIS
+
+/**
+ * @struct RAILSched_Config_t
+ * @brief Provided for backwards compatibility.
+ */
+typedef struct RAILSched_Config {
+ uint8_t buffer[1]; /**< Dummy buffer no longer used. */
+} RAILSched_Config_t;
/**
* @typedef RAIL_StateBuffer_t
- * @brief A buffer to store RAIL internal state.
+ * @brief Provided for backwards compatibility.
*/
-typedef uint32_t RAIL_StateBuffer_t[RAIL_STATE_UINT32_BUFFER_SIZE];
+typedef uint8_t RAIL_StateBuffer_t[1];
/**
* @struct RAIL_Config_t
- * @brief RAIL configuration and internal state structure.
- *
- * This structure must be allocated in application global read-write memory
- * that persists for the duration of RAIL usage. It cannot be allocated
- * in read-only memory or on the call stack.
+ * @brief RAIL configuration structure.
*/
typedef struct RAIL_Config {
/**
@@ -160,34 +143,84 @@ typedef struct RAIL_Config {
*
* @param[in] railHandle A handle for a RAIL instance.
* @param[in] events A bit mask of RAIL events.
- * @return void.
*
* See the \ref RAIL_Events_t documentation for the list of RAIL events.
*/
void (*eventsCallback)(RAIL_Handle_t railHandle, RAIL_Events_t events);
/**
- * Pointer to a structure to hold state information required by the \ref
- * Protocol_Specific APIs. If needed, this structure must be allocated in
- * global read-write memory and initialized to all zeros.
- *
- * Currently, this is only required when using the \ref BLE APIs and should be
- * set to point to a \ref RAIL_BLE_State_t structure. When using \ref
- * IEEE802_15_4 or \ref Z_Wave this should be set to NULL.
+ * Provided for backwards compatibility. Ignored.
*/
void *protocol;
/**
- * A pointer to a RAIL scheduler state object allocated in global read-write
- * memory and initialized to all zeros. When not using a multiprotocol
- * scheduler, it should be NULL.
+ * Provided for backwards compatibility. Ignored.
*/
RAILSched_Config_t *scheduler;
/**
- * A structure for RAIL to maintain its internal state, which must be
- * initialized to all zeros.
+ * Provided for backwards compatibility. Ignored.
*/
RAIL_StateBuffer_t buffer;
} RAIL_Config_t;
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+/**
+ * @enum RAIL_RadioStateEfr32_t
+ * @brief Radio state machine statuses.
+ */
+RAIL_ENUM(RAIL_RadioStateEfr32_t) {
+ RAIL_RAC_STATE_OFF, /**< Radio is off. */
+ RAIL_RAC_STATE_RXWARM, /**< Radio is enabling the receiver. */
+ RAIL_RAC_STATE_RXSEARCH, /**< Radio is listening for incoming frames. */
+ RAIL_RAC_STATE_RXFRAME, /**< Radio is receiving a frame. */
+ RAIL_RAC_STATE_RXPD, /**< Radio is powering down receiver and going to
+ OFF state. */
+ RAIL_RAC_STATE_RX2RX, /**< Radio is going back to receive mode after
+ receiving a frame. */
+ RAIL_RAC_STATE_RXOVERFLOW, /**< Received data was lost due to full receive
+ buffer. */
+ RAIL_RAC_STATE_RX2TX, /**< Radio is disabling receiver and enabling
+ transmitter. */
+ RAIL_RAC_STATE_TXWARM, /**< Radio is enabling transmitter. */
+ RAIL_RAC_STATE_TX, /**< Radio is transmitting data. */
+ RAIL_RAC_STATE_TXPD, /**< Radio is powering down transmitter and going
+ to OFF state. */
+ RAIL_RAC_STATE_TX2RX, /**< Radio is disabling transmitter and enabling
+ reception. */
+ RAIL_RAC_STATE_TX2TX, /**< Radio is preparing a transmission after the
+ previous transmission was ended. */
+ RAIL_RAC_STATE_SHUTDOWN, /**< Radio is powering down receiver and going to
+ OFF state. */
+#if _SILICON_LABS_32B_SERIES_2_CONFIG >= 2
+ RAIL_RAC_STATE_POR, /**< Radio power-on-reset state. */
+#endif
+ RAIL_RAC_STATE_NONE /**< Invalid Radio state, must be the last entry */
+};
+
+// Self-referencing defines minimize compiler complaints when using RAIL_ENUM
+#define RAIL_RAC_STATE_OFF ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_OFF)
+#define RAIL_RAC_STATE_RXWARM ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RXWARM)
+#define RAIL_RAC_STATE_RXSEARCH ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RXSEARCH)
+#define RAIL_RAC_STATE_RXFRAME ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RXFRAME)
+#define RAIL_RAC_STATE_RXPD ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RXPD)
+#define RAIL_RAC_STATE_RX2RX ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RX2RX)
+#define RAIL_RAC_STATE_RXOVERFLOW ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RXOVERFLOW)
+#define RAIL_RAC_STATE_RX2TX ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RX2TX)
+#define RAIL_RAC_STATE_TXWARM ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_TXWARM)
+#define RAIL_RAC_STATE_TX ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_TX)
+#define RAIL_RAC_STATE_TXPD ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_TXPD)
+#define RAIL_RAC_STATE_TX2RX ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_TX2RX)
+#define RAIL_RAC_STATE_TX2TX ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_TX2TX)
+#define RAIL_RAC_STATE_SHUTDOWN ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_SHUTDOWN)
+#if _SILICON_LABS_32B_SERIES_2_CONFIG >= 2
+#define RAIL_RAC_STATE_POR ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_POR)
+#endif
+#define RAIL_RAC_STATE_NONE ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_NONE)
+#endif//DOXYGEN_SHOULD_SKIP_THIS
+
+/** @} */ // end of group General_EFR32XG2
+
+// -----------------------------------------------------------------------------
+// Multiprotocol
+// -----------------------------------------------------------------------------
/**
* @addtogroup Multiprotocol_EFR32 EFR32
* @{
@@ -196,13 +229,76 @@ typedef struct RAIL_Config {
*/
/**
- * A placeholder for a chip-specific RAIL handle. Using NULL as a RAIL handle is
- * not recommended. As a result, another value that can't be de-referenced is used.
+ * @def TRANSITION_TIME_US
+ * @brief Time it takes to take care of protocol switching.
*/
-#define RAIL_EFR32_HANDLE ((RAIL_Handle_t)0xFFFFFFFFUL)
+#if _SILICON_LABS_32B_SERIES_2_CONFIG > 1
+// XG22 + devices
+#define TRANSITION_TIME_US 510
+#else
+// XG21
+#define TRANSITION_TIME_US 500
+#endif
/** @} */ // end of group Multiprotocol_EFR32
+// -----------------------------------------------------------------------------
+// Antenna Control
+// -----------------------------------------------------------------------------
+/**
+ * @addtogroup Antenna_Control_EFR32XG2X EFR32XG2X
+ * @{
+ * @brief EFR32 Antenna Control Functionality
+ * @ingroup Antenna_Control
+ *
+ * These enumerations and structures are used with RAIL Antenna Control API. EFR32 supports
+ * up to two antennas with configurable pin locations.
+ */
+
+/** Antenna path Selection enumeration. */
+RAIL_ENUM(RAIL_AntennaSel_t) {
+ /** Enum for antenna path 0. */
+ RAIL_ANTENNA_0 = 0,
+ /** Enum for antenna path 1. */
+ RAIL_ANTENNA_1 = 1,
+ /** Enum for antenna path auto. */
+ RAIL_ANTENNA_AUTO = 255,
+};
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+// Self-referencing defines minimize compiler complaints when using RAIL_ENUM
+#define RAIL_ANTENNA_0 ((RAIL_AntennaSel_t) RAIL_ANTENNA_0)
+#define RAIL_ANTENNA_1 ((RAIL_AntennaSel_t) RAIL_ANTENNA_1)
+#define RAIL_ANTENNA_AUTO ((RAIL_AntennaSel_t) RAIL_ANTENNA_AUTO)
+#endif//DOXYGEN_SHOULD_SKIP_THIS
+
+/**
+ * @struct RAIL_AntennaConfig_t
+ * @brief A configuration for antenna selection.
+ */
+typedef struct RAIL_AntennaConfig {
+ /** Antenna 0 Pin Enable */
+ bool ant0PinEn;
+ /** Antenna 1 Pin Enable */
+ bool ant1PinEn;
+ /** Antenna 0 internal RF Path to use */
+ RAIL_AntennaSel_t ant0Loc;
+ /** Map internal default path to ant0Loc */
+ #define defaultPath ant0Loc
+ /** Antenna 0 output GPIO port */
+ uint8_t ant0Port;
+ /** Antenna 0 output GPIO pin */
+ uint8_t ant0Pin;
+ /** Antenna 1 internal RF Path to use */
+ RAIL_AntennaSel_t ant1Loc;
+ /** Antenna 1 output GPIO port */
+ uint8_t ant1Port;
+ /** Antenna 1 output GPIO pin */
+ uint8_t ant1Pin;
+} RAIL_AntennaConfig_t;
+
+/** @} */ // end of group Antenna_Control_EFR32
+
// -----------------------------------------------------------------------------
// Calibration
// -----------------------------------------------------------------------------
@@ -232,7 +328,17 @@ typedef struct RAIL_Config {
/** EFR32-specific temperature calibration bit */
#define RAIL_CAL_TEMP_VCO (0x00000001U)
/** EFR32-specific IR calibration bit */
-#define RAIL_CAL_ONETIME_IRCAL (0x00010000U)
+#define RAIL_CAL_RX_IRCAL (0x00010000U)
+
+#if RAIL_SUPPORTS_OFDM_PA
+/** EFR32-specific Tx IR calibration bit */
+#define RAIL_CAL_OFDM_TX_IRCAL (0x00100000U)
+#else
+#define RAIL_CAL_OFDM_TX_IRCAL (0U)
+#endif // RAIL_SUPPORTS_OFDM_PA
+
+/** EFR32-specific IR calibration bit */
+#define RAIL_CAL_ONETIME_IRCAL (RAIL_CAL_RX_IRCAL | RAIL_CAL_OFDM_TX_IRCAL)
/** A mask to run temperature-dependent calibrations */
#define RAIL_CAL_TEMP (RAIL_CAL_TEMP_VCO)
@@ -249,6 +355,162 @@ typedef struct RAIL_Config {
/** An invalid calibration value */
#define RAIL_CAL_INVALID_VALUE (0xFFFFFFFFU)
+/**
+ * @def RAIL_RF_PATHS_2P4GIG
+ * @brief Indicates the number of 2.4 GHz RF Paths suppported
+ */
+#if _SILICON_LABS_32B_SERIES_2_CONFIG == 1 || _SILICON_LABS_32B_SERIES_2_CONFIG == 4
+#define RAIL_RF_PATHS_2P4GIG 2
+#elif _SILICON_LABS_32B_SERIES_2_CONFIG == 2
+#define RAIL_RF_PATHS_2P4GIG 1
+#else
+#define RAIL_RF_PATHS_2P4GIG 0
+#endif
+
+/**
+ * @def RAIL_RF_PATHS_SUBG
+ * @brief Indicates the number of sub-GHz RF Paths supported
+ */
+#if _SILICON_LABS_32B_SERIES_2_CONFIG == 3
+#define RAIL_RF_PATHS_SUBGIG 2
+#elif _SILICON_LABS_32B_SERIES_2_CONFIG == 5
+#define RAIL_RF_PATHS_SUBGIG 2
+#else
+#define RAIL_RF_PATHS_SUBGIG 0
+#endif
+
+/**
+ * @def RAIL_RF_PATHS
+ * @brief Indicates the number of RF Paths supported
+ */
+#define RAIL_RF_PATHS (RAIL_RF_PATHS_SUBGIG + RAIL_RF_PATHS_2P4GIG)
+
+/**
+ * @def RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS
+ * @brief Indicates this version of RAIL supports IR calibration on multiple RF paths
+ * Needed for backwards compatibility.
+ */
+#if RAIL_RF_PATHS > 1
+#define RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS 1
+#endif
+
+#if RAIL_SUPPORTS_OFDM_PA
+/**
+ * @typedef RAIL_TxIrCalValues_t
+ * @brief A Tx IR calibration value structure.
+ *
+ * This definition contains the set of persistent calibration values for
+ * OFDM on EFR32. You can set these beforehand and apply them at startup to save the
+ * time required to compute them. Any of these values may be set to
+ * RAIL_IRCAL_INVALID_VALUE to force the code to compute that calibration value.
+ */
+typedef struct RAIL_TxIrCalValues {
+ uint32_t dcOffsetIQ; // TXIRCAL result
+ uint32_t phiEpsilon; // TXIRCAL result
+} RAIL_TxIrCalValues_t;
+
+/**
+ * A define to set all RAIL_TxIrCalValues_t values to uninitialized.
+ *
+ * This define can be used when you have no data to pass to the calibration
+ * routines but wish to compute and save all possible calibrations.
+ */
+#define RAIL_IRCALVALUES_TX_UNINIT { \
+ RAIL_CAL_INVALID_VALUE, \
+ RAIL_CAL_INVALID_VALUE, \
+}
+
+/**
+ * @typedef RAIL_IrCalValues_t
+ * @brief An IR calibration value structure.
+ *
+ * This definition contains the set of persistent calibration values for
+ * EFR32. You can set these beforehand and apply them at startup to save the
+ * time required to compute them. Any of these values may be set to
+ * RAIL_IRCAL_INVALID_VALUE to force the code to compute that calibration value.
+ */
+typedef struct RAIL_IrCalValues {
+ uint32_t rxIrCalValues[RAIL_RF_PATHS]; /**< An Image Rejection (IR) calibration value */
+ RAIL_TxIrCalValues_t txIrCalValues; /**< An Image Rejection (IR) calibration value for OFDM Tx*/
+} RAIL_IrCalValues_t;
+
+/**
+ * A define allowing Rx calibration value access compatibility
+ * between series 1 and series 2.
+ */
+#define RAIL_IRCALVAL(irCalStruct, rfPath) \
+ ((irCalStruct).rxIrCalValues[(rfPath)])
+
+/**
+ * A define to set all RAIL_IrCalValues_t values to uninitialized.
+ *
+ * This define can be used when you have no data to pass to the calibration
+ * routines but wish to compute and save all possible calibrations.
+ */
+#if (RAIL_RF_PATHS == 2)
+#define RAIL_IRCALVALUES_UNINIT { \
+ { RAIL_CAL_INVALID_VALUE, RAIL_CAL_INVALID_VALUE }, \
+ RAIL_IRCALVALUES_TX_UNINIT, \
+}
+#elif (RAIL_RF_PATHS == 1)
+#define RAIL_IRCALVALUES_UNINIT { \
+ { RAIL_CAL_INVALID_VALUE }, \
+ RAIL_IRCALVALUES_TX_UNINIT, \
+}
+#else
+#error "This config is not valid, RAIL_RF_PATHS has to be either 1 or 2"
+#endif
+
+#else // RAIL_SUPPORTS_OFDM_PA
+/**
+ * @typedef RAIL_IrCalValues_t
+ * @brief An IR calibration value structure.
+ *
+ * This definition contains the set of persistent calibration values for
+ * EFR32. You can set these beforehand and apply them at startup to save the
+ * time required to compute them. Any of these values may be set to
+ * RAIL_IRCAL_INVALID_VALUE to force the code to compute that calibration value.
+ */
+typedef uint32_t RAIL_IrCalValues_t[RAIL_RF_PATHS];
+
+/**
+ * A define allowing Rx calibration value access compatibility
+ * between series 1 and series 2.
+ */
+#define RAIL_IRCALVAL(irCalStruct, rfPath) \
+ ((irCalStruct)[(rfPath)])
+
+/**
+ * A define to set all RAIL_IrCalValues_t values to uninitialized.
+ *
+ * This define can be used when you have no data to pass to the calibration
+ * routines but wish to compute and save all possible calibrations.
+ */
+#if (RAIL_RF_PATHS == 2)
+#define RAIL_IRCALVALUES_UNINIT { \
+ RAIL_CAL_INVALID_VALUE, \
+ RAIL_CAL_INVALID_VALUE, \
+}
+#elif (RAIL_RF_PATHS == 1)
+#define RAIL_IRCALVALUES_UNINIT { \
+ RAIL_CAL_INVALID_VALUE, \
+}
+#else
+#error "This config is not valid, RAIL_RF_PATHS has to be either 1 or 2"
+#endif
+
+#endif // RAIL_SUPPORTS_OFDM_PA
+
+/**
+ * @struct RAIL_ChannelConfigEntryAttr
+ * @brief A channel configuration entry attribute structure. Items listed
+ * are designed to be altered and updated during run-time.
+ */
+struct RAIL_ChannelConfigEntryAttr {
+ RAIL_IrCalValues_t calValues; /**< IR calibration attributes specific to
+ each channel configuration entry. */
+};
+
/**
* Applies a given image rejection calibration value.
*
@@ -264,10 +526,33 @@ typedef struct RAIL_Config {
* If multiple protocols are used, this function will return
* \ref RAIL_STATUS_INVALID_STATE if it is called and the given railHandle is
* not active. In that case, the caller must attempt to re-call this function later.
+ *
+ * @note: This function is deprecated. Please use RAIL_ApplyIrCalibrationAlt instead.
*/
RAIL_Status_t RAIL_ApplyIrCalibration(RAIL_Handle_t railHandle,
uint32_t imageRejection);
+/**
+ * Applies a given image rejection calibration value.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] imageRejection Pointer to the image rejection value to apply.
+ * @param[in] rfPath RF path to calibrate.
+ * @return A status code indicating success of the function call.
+ *
+ * Take an image rejection calibration value and apply it. This value should be
+ * determined from a previous run of \ref RAIL_CalibrateIrAlt on the same
+ * physical device with the same radio configuration. The imageRejection value
+ * will also be stored to the \ref RAIL_ChannelConfigEntry_t::attr, if possible.
+ *
+ * If multiple protocols are used, this function will return
+ * \ref RAIL_STATUS_INVALID_STATE if it is called and the given railHandle is
+ * not active. In that case, the caller must attempt to re-call this function later.
+ */
+RAIL_Status_t RAIL_ApplyIrCalibrationAlt(RAIL_Handle_t railHandle,
+ RAIL_IrCalValues_t *imageRejection,
+ RAIL_AntennaSel_t rfPath);
+
/**
* Runs the image rejection calibration.
*
@@ -286,10 +571,36 @@ RAIL_Status_t RAIL_ApplyIrCalibration(RAIL_Handle_t railHandle,
* If multiple protocols are used, this function will return
* \ref RAIL_STATUS_INVALID_STATE if it is called and the given railHandle is
* not active. In that case, the caller must attempt to re-call this function later.
+ *
+ * @note: This function is deprecated. Please use RAIL_CalibrateIrAlt instead.
*/
RAIL_Status_t RAIL_CalibrateIr(RAIL_Handle_t railHandle,
uint32_t *imageRejection);
+/**
+ * Runs the image rejection calibration.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[out] imageRejection Pointer to the image rejection result.
+ * @param[in] rfPath RF path to calibrate.
+ * @return A status code indicating success of the function call.
+ *
+ * Run the image rejection calibration and apply the resulting value. If the
+ * imageRejection parameter is not NULL, store the value at that
+ * location. The imageRejection value will also be stored to the
+ * \ref RAIL_ChannelConfigEntry_t::attr, if possible. This is a long-running
+ * calibration that adds significant code space when run and can be run with a
+ * separate firmware image on each device to save code space in the
+ * final image.
+ *
+ * If multiple protocols are used, this function will return
+ * \ref RAIL_STATUS_INVALID_STATE if it is called and the given railHandle is
+ * not active. In that case, the caller must attempt to re-call this function later.
+ */
+RAIL_Status_t RAIL_CalibrateIrAlt(RAIL_Handle_t railHandle,
+ RAIL_IrCalValues_t *imageRejection,
+ RAIL_AntennaSel_t rfPath);
+
/**
* Calibrates image rejection for IEEE 802.15.4 2.4 GHz
*
@@ -355,7 +666,7 @@ RAIL_Status_t RAIL_BLE_CalibrateIr(RAIL_Handle_t railHandle,
RAIL_Status_t RAIL_CalibrateTemp(RAIL_Handle_t railHandle);
/**
- * @struct RAIL_CalValues_t
+ * @typedef RAIL_CalValues_t
* @brief A calibration value structure.
*
* This structure contains the set of persistent calibration values for
@@ -363,9 +674,7 @@ RAIL_Status_t RAIL_CalibrateTemp(RAIL_Handle_t railHandle);
* time required to compute them. Any of these values may be set to
* RAIL_CAL_INVALID_VALUE to force the code to compute that calibration value.
*/
-typedef struct RAIL_CalValues {
- uint32_t imageRejection; /**< An Image Rejection (IR) calibration value */
-} RAIL_CalValues_t;
+typedef RAIL_IrCalValues_t RAIL_CalValues_t;
/**
* A define to set all RAIL_CalValues_t values to uninitialized.
@@ -373,9 +682,7 @@ typedef struct RAIL_CalValues {
* This define can be used when you have no data to pass to the calibration
* routines but wish to compute and save all possible calibrations.
*/
-#define RAIL_CALVALUES_UNINIT (RAIL_CalValues_t){ \
- RAIL_CAL_INVALID_VALUE, \
-}
+#define RAIL_CALVALUES_UNINIT RAIL_IRCALVALUES_UNINIT
/** @} */ // end of group Calibration_EFR32
@@ -413,11 +720,44 @@ typedef int16_t RAIL_FrequencyOffset_t;
#define RAIL_FREQUENCY_OFFSET_MIN ((RAIL_FrequencyOffset_t) -RAIL_FREQUENCY_OFFSET_MAX)
/**
- * Specifies an invalid frequency offset value. This will be returned if you
+ * Specify an invalid frequency offset value. This will be returned if you
* call \ref RAIL_GetRxFreqOffset() at an invalid time.
*/
#define RAIL_FREQUENCY_OFFSET_INVALID ((RAIL_FrequencyOffset_t) 0x8000)
+/**
+ * @struct RAIL_DirectModeConfig_t
+ * @brief Chip-specific type that allows the user to specify direct mode
+ * parameters using \ref RAIL_ConfigDirectMode().
+ */
+typedef struct RAIL_DirectModeConfig {
+ /** Enable synchronous RX DOUT using DCLK vs. asynchronous RX DOUT. */
+ bool syncRx;
+ /** Enable synchronous TX DIN using DCLK vs. asynchronous TX DIN. */
+ bool syncTx;
+
+ /** Only used with directRx */
+ /** Data output (DOUT) GPIO port */
+ uint8_t doutPort;
+ /** Data output (DOUT) GPIO pin */
+ uint8_t doutPin;
+
+ /** Only used in synchronous mode */
+ /** Data clock (DCLK) GPIO port. Only used in synchronous mode */
+ uint8_t dclkPort;
+ /** Data clock (DCLK) GPIO pin. Only used in synchronous mode */
+ uint8_t dclkPin;
+
+ /** Only used with directTx */
+ /** Data frame (DIN) GPIO port */
+ uint8_t dinPort;
+ /** Data frame (DIN) GPIO pin */
+ uint8_t dinPin;
+
+ /** Reserved for future use */
+ uint8_t reserved[3];
+} RAIL_DirectModeConfig_t;
+
/** @} */ // end of group Diagnostic_EFR32
// -----------------------------------------------------------------------------
@@ -455,10 +795,10 @@ typedef const uint32_t *RAIL_RadioConfig_t;
* Raw power levels used directly by the RAIL_Get/SetTxPower API where a higher
* numerical value corresponds to a higher output power. These are referred to
* as 'raw (values/units)'. On EFR32, they can range from one of \ref
- * RAIL_TX_POWER_LEVEL_LP_MIN, \ref RAIL_TX_POWER_LEVEL_HP_MIN, or
- * \ref RAIL_TX_POWER_LEVEL_SUBGIG_MIN to one of \ref
- * RAIL_TX_POWER_LEVEL_LP_MAX, \ref RAIL_TX_POWER_LEVEL_HP_MAX, and \ref
- * RAIL_TX_POWER_LEVEL_SUBGIG_MAX, respectively, depending on the selected \ref
+ * RAIL_TX_POWER_LEVEL_2P4_LP_MIN, \ref RAIL_TX_POWER_LEVEL_2P4_HP_MIN, or
+ * \ref RAIL_TX_POWER_LEVEL_SUBGIG_HP_MIN to one of \ref
+ * RAIL_TX_POWER_LEVEL_2P4_LP_MAX, \ref RAIL_TX_POWER_LEVEL_2P4_HP_MAX, and \ref
+ * RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX, respectively, depending on the selected \ref
* RAIL_TxPowerMode_t.
*/
typedef uint8_t RAIL_TxPowerLevel_t;
@@ -468,62 +808,182 @@ typedef uint8_t RAIL_TxPowerLevel_t;
* The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
* RAIL_TX_POWER_MODE_2P4_HP mode.
*/
-#define RAIL_TX_POWER_LEVEL_HP_MAX (180U)
+#define RAIL_TX_POWER_LEVEL_2P4_HP_MAX (180U)
/**
* The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
* RAIL_TX_POWER_MODE_2P4_HP mode.
*/
-#define RAIL_TX_POWER_LEVEL_HP_MIN (1U)
+#define RAIL_TX_POWER_LEVEL_2P4_HP_MIN (1U)
+/**
+ * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4_MP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_2P4_MP_MAX (90U)
/**
* The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
* RAIL_TX_POWER_MODE_2P4_MP mode.
*/
-#define RAIL_TX_POWER_LEVEL_MP_MAX (90U)
+#define RAIL_TX_POWER_LEVEL_2P4_MP_MIN (1U)
/**
* The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
* RAIL_TX_POWER_MODE_2P4_LP mode.
*/
-#define RAIL_TX_POWER_LEVEL_LP_MAX (64U)
+#define RAIL_TX_POWER_LEVEL_2P4_LP_MAX (64U)
/**
* The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
- * RAIL_TX_POWER_MODE_2P4_MP mode.
+ * RAIL_TX_POWER_MODE_2P4_LP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_2P4_LP_MIN (0U)
+#elif _SILICON_LABS_32B_SERIES_2_CONFIG == 4
+/**
+ * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4_HP mode.
+ * EFR32XG24: capable of 20dBm max output power has max powerlevel:180
+ * EFR32XG24: capable of 10dBm max output power has max powerlevel:90
*/
-#define RAIL_TX_POWER_LEVEL_MP_MIN (1U)
+#if defined (_SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT) \
+ && (_SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM > 10)
+#define RAIL_TX_POWER_LEVEL_2P4_HP_MAX (180U)
+#else
+#define RAIL_TX_POWER_LEVEL_2P4_HP_MAX (90U)
+#endif
/**
* The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4_HP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_2P4_HP_MIN (0U)
+/**
+ * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
* RAIL_TX_POWER_MODE_2P4_LP mode.
*/
-#define RAIL_TX_POWER_LEVEL_LP_MIN (1U)
-#else
+#define RAIL_TX_POWER_LEVEL_2P4_LP_MAX (15U)
+/**
+ * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4_LP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_2P4_LP_MIN (0U)
+#elif _SILICON_LABS_32B_SERIES_2_CONFIG == 2
/**
* The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
* RAIL_TX_POWER_MODE_2P4_HP mode.
*/
-#define RAIL_TX_POWER_LEVEL_HP_MAX (128U)
+#define RAIL_TX_POWER_LEVEL_2P4_HP_MAX (127U)
/**
* The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
* RAIL_TX_POWER_MODE_2P4_HP mode.
*/
-#define RAIL_TX_POWER_LEVEL_HP_MIN (0U)
+#define RAIL_TX_POWER_LEVEL_2P4_HP_MIN (0U)
/**
* The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
* RAIL_TX_POWER_MODE_2P4_LP mode.
*/
-#define RAIL_TX_POWER_LEVEL_LP_MAX (15U)
+#define RAIL_TX_POWER_LEVEL_2P4_LP_MAX (15U)
/**
* The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
* RAIL_TX_POWER_MODE_2P4_LP mode.
*/
-#define RAIL_TX_POWER_LEVEL_LP_MIN (0U)
-#endif
+#define RAIL_TX_POWER_LEVEL_2P4_LP_MIN (0U)
+#else //efr32xg23
+/**
+ * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4_HP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_2P4_HP_MAX (128U)
+/**
+ * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4_HP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_2P4_HP_MIN (0U)
+#endif //_SILICON_LABS_32B_SERIES_2_CONFIG
#if RAIL_FEAT_SUBGIG_RADIO
+#if _SILICON_LABS_32B_SERIES_2_CONFIG == 3
+#define RAIL_SUBGIG_MAX 240U
+#elif _SILICON_LABS_32B_SERIES_2_CONFIG == 5
+#define RAIL_SUBGIG_MAX 79U
+#endif
/**
* The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
* RAIL_TX_POWER_MODE_SUBGIG mode.
*/
-#define RAIL_TX_POWER_LEVEL_SUBGIG_MAX (248U)
+#define RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX (RAIL_SUBGIG_MAX)
+/**
+ * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_SUBGIG mode.
+ */
+#define RAIL_TX_POWER_LEVEL_SUBGIG_HP_MIN (1U)
+/**
+ * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_SUBGIG_MP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_SUBGIG_MP_MAX (RAIL_SUBGIG_MAX)
+/**
+ * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_SUBGIG_MP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_SUBGIG_MP_MIN (1U)
+/**
+ * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_SUBGIG_LP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_SUBGIG_LP_MAX (RAIL_SUBGIG_MAX)
+/**
+ * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_SUBGIG_LP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_SUBGIG_LP_MIN (1U)
+/**
+ * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_SUBGIG_LLP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_SUBGIG_LLP_MAX (RAIL_SUBGIG_MAX)
+/**
+ * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_SUBGIG_LLP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_SUBGIG_LLP_MIN (1U)
+#endif //RAIL_FEAT_SUBGIG_RADIO
+
+#if RAIL_SUPPORTS_OFDM_PA
+#if _SILICON_LABS_32B_SERIES_2_CONFIG == 5
+/**
+ * With RAIL_LIB-6495 the OFDM PA power output will not
+ * be modified at this time for gain control. Instead the PA will be kept at 191 slices
+ * active and TXFRONT_TXGAIN_GAINDIG will vary between 65-1020. The raw power level
+ * will be multiplied by 5 to get the GAINDIG value.
+ */
+#define RAIL_OFDM_PA_MAX 204U
+#define RAIL_OFDM_PA_MULT 5U
+#define RAIL_OFDM_PA_MIN 13U
#endif
+/**
+ * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_OFDM_PA mode.
+ */
+#define RAIL_TX_POWER_LEVEL_OFDM_PA_MAX (RAIL_OFDM_PA_MAX)
+/**
+ * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_OFDM_PA mode.
+ */
+#define RAIL_TX_POWER_LEVEL_OFDM_PA_MIN (RAIL_OFDM_PA_MIN)
+#endif //RAIL_SUPPORTS_OFDM_PA
+
+/** Backwards compatability define */
+#define RAIL_TX_POWER_LEVEL_HP_MAX RAIL_TX_POWER_LEVEL_2P4_HP_MAX
+/** Backwards compatability define */
+#define RAIL_TX_POWER_LEVEL_HP_MIN RAIL_TX_POWER_LEVEL_2P4_HP_MIN
+/** Backwards compatability define */
+#define RAIL_TX_POWER_LEVEL_MP_MAX RAIL_TX_POWER_LEVEL_2P4_MP_MAX
+/** Backwards compatability define */
+#define RAIL_TX_POWER_LEVEL_MP_MIN RAIL_TX_POWER_LEVEL_2P4_MP_MIN
+/** Backwards compatability define */
+#define RAIL_TX_POWER_LEVEL_LP_MAX RAIL_TX_POWER_LEVEL_2P4_LP_MAX
+/** Backwards compatability define */
+#define RAIL_TX_POWER_LEVEL_LP_MIN RAIL_TX_POWER_LEVEL_2P4_LP_MIN
+/** Backwards compatability define */
+#define RAIL_TX_POWER_LEVEL_SUBGIG_MAX RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX
+/** Backwards compatability define */
+#define RAIL_TX_POWER_LEVEL_SUBGIG_MIN RAIL_TX_POWER_LEVEL_SUBGIG_HP_MIN
/**
* Invalid RAIL_TxPowerLevel_t value returned when an error occurs
@@ -546,15 +1006,18 @@ typedef uint8_t RAIL_TxPowerLevel_t;
* characteristics of a given amplifier, see the data sheet.
*/
RAIL_ENUM(RAIL_TxPowerMode_t) {
+#if RAIL_FEAT_2G4_RADIO
/**
* High-power 2.4 GHz amplifier
* EFR32XG21: up to 20 dBm, raw values: 1-180
* EFR32XG22: up to 6 dBm, raw values: 1-128
+ * EFR32XG24: capable of 20dBm max output power supports powerlevel: 0-180
+ * EFR32XG24: capable of 10dBm max output power supports powerlevel: 0-90
*/
RAIL_TX_POWER_MODE_2P4GIG_HP,
/** Deprecated enum equivalent to \ref RAIL_TX_POWER_MODE_2P4GIG_HP */
RAIL_TX_POWER_MODE_2P4_HP = RAIL_TX_POWER_MODE_2P4GIG_HP,
-#if _SILICON_LABS_32B_SERIES_2_CONFIG != 2
+#if _SILICON_LABS_32B_SERIES_2_CONFIG == 1
/**
* Mid-power 2.4 GHz amplifier
* EFR32XG21: up to 10 dBm, raw values: 1-90
@@ -564,28 +1027,40 @@ RAIL_ENUM(RAIL_TxPowerMode_t) {
/** Deprecated enum equivalent to \ref RAIL_TX_POWER_MODE_2P4GIG_MP */
RAIL_TX_POWER_MODE_2P4_MP = RAIL_TX_POWER_MODE_2P4GIG_MP,
#endif
+#if _SILICON_LABS_32B_SERIES_2_CONFIG != 3
/**
* Low-power 2.4 GHz amplifier
* EFR32XG21: up to 0 dBm, raw values: 1-64
* EFR32XG22: up to 0 dBm, raw values: 1-16
+ * EFR32XG24: up to 0 dBm, raw values: 1-16
*/
RAIL_TX_POWER_MODE_2P4GIG_LP,
/** Deprecated enum equivalent to \ref RAIL_TX_POWER_MODE_2P4GIG_LP */
RAIL_TX_POWER_MODE_2P4_LP = RAIL_TX_POWER_MODE_2P4GIG_LP,
+#endif
/** Select the highest power PA available on the current chip. */
RAIL_TX_POWER_MODE_2P4GIG_HIGHEST,
/** Deprecated enum equivalent to \ref RAIL_TX_POWER_MODE_2P4GIG_HIGHEST */
RAIL_TX_POWER_MODE_2P4_HIGHEST = RAIL_TX_POWER_MODE_2P4GIG_HIGHEST,
+#endif
#if RAIL_FEAT_SUBGIG_RADIO
- /** High-power amplifier, up to 20 dBm, raw values: 0-180 */
+ /** High-power amplifier (Class D mode), up to 20 dBm, raw values: 0-180 */
RAIL_TX_POWER_MODE_SUBGIG_HP,
- /** Mid-power amplifier, up to 10 dBm, raw values: 0-90 */
+ /** Deprecated enum equivalent to \ref RAIL_TX_POWER_MODE_SUBGIG_HP */
+ RAIL_TX_POWER_MODE_SUBGIG = RAIL_TX_POWER_MODE_SUBGIG_HP,
+ /** Mid-power amplifier, greater than -10 dBm, raw values: 0-90 */
RAIL_TX_POWER_MODE_SUBGIG_MP,
- /** Low-power amplifier, up to 0 dBm, raw values: 1-7 */
+ /** Low-power amplifier, greater than -20 dBm, raw values: 1-7 */
RAIL_TX_POWER_MODE_SUBGIG_LP,
+ /** Low-Low-power amplifier, greater than -30 dBm, raw values: 1-7 */
+ RAIL_TX_POWER_MODE_SUBGIG_LLP,
/** Select the highest power PA available on the current chip. */
RAIL_TX_POWER_MODE_SUBGIG_HIGHEST,
-#endif
+#endif//RAIL_FEAT_SUBGIG_RADIO
+#if RAIL_SUPPORTS_OFDM_PA
+ /** OFDM PA, up to 17 dBm, raw values 0-191. */
+ RAIL_TX_POWER_MODE_OFDM_PA,
+#endif//RAIL_SUPPORTS_OFDM_PA
/** Invalid amplifier Selection */
RAIL_TX_POWER_MODE_NONE,
};
@@ -593,30 +1068,87 @@ RAIL_ENUM(RAIL_TxPowerMode_t) {
/**
* The number of PA's on this chip.
*/
-#if _SILICON_LABS_32B_SERIES_2_CONFIG == 2
+#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \
+ || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4))
#define RAIL_NUM_PA (2U)
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 3)
+#define RAIL_NUM_PA (4U)
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 5)
+#define RAIL_NUM_PA (6U)
#else
#define RAIL_NUM_PA (3U)
#endif
#ifndef DOXYGEN_SHOULD_SKIP_THIS
// Self-referencing defines minimize compiler complaints when using RAIL_ENUM
+#if RAIL_FEAT_2G4_RADIO
#define RAIL_TX_POWER_MODE_2P4GIG_HP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4GIG_HP)
#define RAIL_TX_POWER_MODE_2P4_HP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4_HP)
-#if _SILICON_LABS_32B_SERIES_2_CONFIG != 2
+#if _SILICON_LABS_32B_SERIES_2_CONFIG == 1
#define RAIL_TX_POWER_MODE_2P4GIG_MP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4GIG_MP)
#define RAIL_TX_POWER_MODE_2P4_MP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4_MP)
-#endif
+#endif //_SILICON_LABS_32B_SERIES_2_CONFIG == 1
+#if _SILICON_LABS_32B_SERIES_2_CONFIG != 3
#define RAIL_TX_POWER_MODE_2P4GIG_LP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4GIG_LP)
#define RAIL_TX_POWER_MODE_2P4_LP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4_LP)
+#endif //_SILICON_LABS_32B_SERIES_2_CONFIG != 3
#define RAIL_TX_POWER_MODE_2P4GIG_HIGHEST ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4GIG_HIGHEST)
#define RAIL_TX_POWER_MODE_2P4_HIGHEST ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4_HIGHEST)
+#endif //RAIL_FEAT_2G4_RADIO
#if RAIL_FEAT_SUBGIG_RADIO
+#define RAIL_TX_POWER_MODE_SUBGIG_HP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_HP)
+#define RAIL_TX_POWER_MODE_SUBGIG_MP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_MP)
+#define RAIL_TX_POWER_MODE_SUBGIG_LP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_LP)
+#define RAIL_TX_POWER_MODE_SUBGIG_LLP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_LLP)
#define RAIL_TX_POWER_MODE_SUBGIG ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG)
-#endif
+#define RAIL_TX_POWER_MODE_SUBGIG_HIGHEST ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_HIGHEST)
+#endif //RAIL_FEAT_SUBGIG_RADIO
+#if RAIL_SUPPORTS_OFDM_PA
+#define RAIL_TX_POWER_MODE_OFDM_PA ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_OFDM_PA)
+#define RAIL_TX_POWER_MODE_OFDM_PA_HIGHEST ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_OFDM_PA_HIGHEST)
+#endif //RAIL_SUPPORTS_OFDM_PA
#define RAIL_TX_POWER_MODE_NONE ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_NONE)
#endif//DOXYGEN_SHOULD_SKIP_THIS
+#if RAIL_FEAT_2G4_RADIO
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 1)
+#define RAIL_TX_POWER_MODE_NAMES_2P4GIG \
+ "RAIL_TX_POWER_MODE_2P4GIG_HP", \
+ "RAIL_TX_POWER_MODE_2P4GIG_MP", \
+ "RAIL_TX_POWER_MODE_2P4GIG_LP", \
+ "RAIL_TX_POWER_MODE_2P4GIG_HIGHEST",
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \
+ || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4)
+#define RAIL_TX_POWER_MODE_NAMES_2P4GIG \
+ "RAIL_TX_POWER_MODE_2P4GIG_HP", \
+ "RAIL_TX_POWER_MODE_2P4GIG_LP", \
+ "RAIL_TX_POWER_MODE_2P4GIG_HIGHEST",
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 3)
+#define RAIL_TX_POWER_MODE_NAMES_2P4GIG \
+ "RAIL_TX_POWER_MODE_2P4GIG_HP", \
+ "RAIL_TX_POWER_MODE_2P4GIG_HIGHEST",
+#endif
+#else
+#define RAIL_TX_POWER_MODE_NAMES_2P4GIG
+#endif //RAIL_FEAT_2G4_RADIO
+#if RAIL_FEAT_SUBGIG_RADIO
+#define RAIL_TX_POWER_MODE_NAMES_SUBGIG \
+ "RAIL_TX_POWER_MODE_SUBGIG_HP", \
+ "RAIL_TX_POWER_MODE_SUBGIG_MP", \
+ "RAIL_TX_POWER_MODE_SUBGIG_LP", \
+ "RAIL_TX_POWER_MODE_SUBGIG_LLP", \
+ "RAIL_TX_POWER_MODE_SUBGIG_HIGHEST",
+#else
+#define RAIL_TX_POWER_MODE_NAMES_SUBGIG
+#endif
+
+#if RAIL_SUPPORTS_OFDM_PA
+#define RAIL_TX_POWER_MODE_NAMES_OFDM_PA \
+ "RAIL_TX_POWER_MODE_OFDM_PA",
+#else
+#define RAIL_TX_POWER_MODE_NAMES_OFDM_PA
+#endif
+
/**
* @def RAIL_TX_POWER_MODE_NAMES
* @brief The names of the TX power modes
@@ -624,22 +1156,12 @@ RAIL_ENUM(RAIL_TxPowerMode_t) {
* A list of the names for the TX power modes on the EFR32 series 2 parts. This
* macro is useful for test applications and debugging output.
*/
-#if _SILICON_LABS_32B_SERIES_2_CONFIG == 2
-#define RAIL_TX_POWER_MODE_NAMES { \
- "RAIL_TX_POWER_MODE_2P4GIG_HP", \
- "RAIL_TX_POWER_MODE_2P4GIG_LP", \
- "RAIL_TX_POWER_MODE_2P4GIG_HIGHEST", \
- "RAIL_TX_POWER_MODE_NONE" \
+#define RAIL_TX_POWER_MODE_NAMES { \
+ RAIL_TX_POWER_MODE_NAMES_2P4GIG \
+ RAIL_TX_POWER_MODE_NAMES_SUBGIG \
+ RAIL_TX_POWER_MODE_NAMES_OFDM_PA \
+ "RAIL_TX_POWER_MODE_NONE" \
}
-#else
-#define RAIL_TX_POWER_MODE_NAMES { \
- "RAIL_TX_POWER_MODE_2P4GIG_HP", \
- "RAIL_TX_POWER_MODE_2P4GIG_MP", \
- "RAIL_TX_POWER_MODE_2P4GIG_LP", \
- "RAIL_TX_POWER_MODE_2P4GIG_HIGHEST", \
- "RAIL_TX_POWER_MODE_NONE" \
-}
-#endif
/**
* @struct RAIL_TxPowerConfig_t
@@ -725,80 +1247,110 @@ typedef struct RAIL_PtiConfig {
/** @} */ // end of group PTI_EFR32
+/******************************************************************************
+ * Calibration Structures
+ *****************************************************************************/
+/**
+ * @addtogroup Calibration
+ * @{
+ */
+
+/// Use this value with either TX or RX values in RAIL_SetPaCTune
+/// to use whatever value is already set and do no update. This
+/// value is provided to provide consistency across EFR32 chips,
+/// but technically speaking, all PA capacitance tuning values are
+/// invalid on EFR32XG21 parts, as RAIL_SetPaCTune is not supported
+/// on those parts.
+#define RAIL_PACTUNE_IGNORE (255U)
+
+/** @} */ // end of group Calibration
+
// -----------------------------------------------------------------------------
-// Antenna Control
+// Retiming
// -----------------------------------------------------------------------------
/**
- * @addtogroup Antenna_Control_EFR32XG2X EFR32XG2X
+ * @addtogroup Retiming_EFR32 Retiming
* @{
- * @brief EFR32 Antenna Control Functionality
- * @ingroup Antenna_Control
+ * @brief EFR32-specific retiming capability.
+ * @ingroup RAIL_API
*
- * These enumerations and structures are used with RAIL Antenna Control API. EFR32 supports
- * up to two antennas with configurable pin locations.
+ * The EFR product families have many digital and analog modules that can run
+ * in parallel with a radio. Such combinations can result in interference and
+ * degradation on the radio RX sensitivity. Retiming have the capability to
+ * modify the clocking of the digital modules to reduce such interference.
*/
-/** Antenna path Selection enumeration. */
-RAIL_ENUM(RAIL_AntennaSel_t) {
- /** Enum for antenna path 0. */
- RAIL_ANTENNA_0 = 0,
- /** Enum for antenna path 1. */
- RAIL_ANTENNA_1 = 1,
- /** Enum for antenna path auto. */
- RAIL_ANTENNA_AUTO = 255,
+/**
+ * @enum RAIL_RetimeOptions_t
+ * @brief Retiming options bit shifts.
+ */
+RAIL_ENUM(RAIL_RetimeOptions_t) {
+ /** Shift position of \ref RAIL_RETIME_OPTION_HFXO bit */
+ RAIL_RETIME_OPTION_HFXO_SHIFT = 0,
+ /** Shift position of \ref RAIL_RETIME_OPTION_HFRCO bit */
+ RAIL_RETIME_OPTION_HFRCO_SHIFT,
+ /** Shift position of \ref RAIL_RETIME_OPTION_DCDC bit */
+ RAIL_RETIME_OPTION_DCDC_SHIFT,
+ /** Shift position of \ref RAIL_RETIME_OPTION_LCD bit */
+ RAIL_RETIME_OPTION_LCD_SHIFT,
};
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-// Self-referencing defines minimize compiler complaints when using RAIL_ENUM
-#define RAIL_ANTENNA_0 ((RAIL_AntennaSel_t) RAIL_ANTENNA_0)
-#define RAIL_ANTENNA_1 ((RAIL_AntennaSel_t) RAIL_ANTENNA_1)
-#define RAIL_ANTENNA_AUTO ((RAIL_AntennaSel_t) RAIL_ANTENNA_AUTO)
-#endif//DOXYGEN_SHOULD_SKIP_THIS
+// RAIL_RetimeOptions_t bitmasks
+/**
+ * An option to configure HFXO retiming
+ */
+#define RAIL_RETIME_OPTION_HFXO \
+ (1U << RAIL_RETIME_OPTION_HFXO_SHIFT)
/**
- * @struct RAIL_AntennaConfig_t
- * @brief A configuration for antenna selection.
+ * An option to configure HFRCO retiming
*/
-typedef struct RAIL_AntennaConfig {
- /** Antenna 0 Pin Enable */
- bool ant0PinEn;
- /** Antenna 1 Pin Enable */
- bool ant1PinEn;
- /** Antenna 0 internal RF Path to use */
- RAIL_AntennaSel_t ant0Loc;
- /** Map internal default path to ant0Loc */
- #define defaultPath ant0Loc
- /** Antenna 0 output GPIO port */
- uint8_t ant0Port;
- /** Antenna 0 output GPIO pin */
- uint8_t ant0Pin;
- /** Antenna 1 internal RF Path to use */
- RAIL_AntennaSel_t ant1Loc;
- /** Antenna 1 output GPIO port */
- uint8_t ant1Port;
- /** Antenna 1 output GPIO pin */
- uint8_t ant1Pin;
-} RAIL_AntennaConfig_t;
+#define RAIL_RETIME_OPTION_HFRCO \
+ (1U << RAIL_RETIME_OPTION_HFRCO_SHIFT)
-/** @} */ // end of group Antenna_Control_EFR32
+/**
+ * An option to configure DCDC retiming
+ */
+#define RAIL_RETIME_OPTION_DCDC \
+ (1U << RAIL_RETIME_OPTION_DCDC_SHIFT)
-/******************************************************************************
- * Calibration Structures
- *****************************************************************************/
/**
- * @addtogroup Calibration
- * @{
+ * An option to configure LCD retiming
*/
+#define RAIL_RETIME_OPTION_LCD \
+ (1U << RAIL_RETIME_OPTION_LCD_SHIFT)
-/// Use this value with either TX or RX values in RAIL_SetPaCTune
-/// to use whatever value is already set and do no update. This
-/// value is provided to provide consistency across EFR32 chips,
-/// but technically speaking, all PA capacitance tuning values are
-/// invalid on EFR32XG21 parts, as RAIL_SetPaCTune is not supported
-/// on those parts.
-#define RAIL_PACTUNE_IGNORE (255U)
+/** A value representing no retiming options */
+#define RAIL_RETIME_OPTIONS_NONE 0x0U
-/** @} */ // end of group Calibration
+/** A value representing all retiming options */
+#define RAIL_RETIME_OPTIONS_ALL 0xFFU
+
+/**
+ * Configure retiming options.
+ *
+ * @param[in] railHandle A handle of RAIL instance.
+ * @param[in] mask A bitmask containing which options should be modified.
+ * @param[in] options A bitmask containing desired configuration settings.
+ * Bit positions for each option are found in the \ref RAIL_RetimeOptions_t.
+ * @return Status code indicating success of the function call.
+ */
+RAIL_Status_t RAIL_ConfigRetimeOptions(RAIL_Handle_t railHandle,
+ RAIL_RetimeOptions_t mask,
+ RAIL_RetimeOptions_t options);
+
+/**
+ * Gets currently configured retiming option.
+ *
+ * @param[in] railHandle A handle of RAIL instance.
+ * @param[out] pOptions A pointer to configured retiming options
+ bitmask indicating which are enabled.
+ * @return Status code indicating success of the function call.
+ */
+RAIL_Status_t RAIL_GetRetimeOptions(RAIL_Handle_t railHandle,
+ RAIL_RetimeOptions_t *pOptions);
+
+/** @} */ // end of group Retiming_EFR32
/******************************************************************************
* RX Channel Hopping
@@ -810,10 +1362,41 @@ typedef struct RAIL_AntennaConfig {
/// The static amount of memory needed per channel for channel
/// hopping, regardless of the size of radio configuration structures.
-#define RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL (23U)
+#define RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL (34U)
/** @} */ // end of group Rx_Channel_Hopping
+/**
+ * @addtogroup Sleep
+ * @{
+ */
+
+/// Default PRS channel to use when configuring sleep
+#define RAIL_TIMER_SYNC_PRS_CHANNEL_DEFAULT (7U)
+
+#if _SILICON_LABS_32B_SERIES_2_CONFIG == 2
+/// Default RTCC channel to use when configuring sleep
+#define RAIL_TIMER_SYNC_RTCC_CHANNEL_DEFAULT (1U)
+#else
+/// Default RTCC channel to use when configuring sleep
+#define RAIL_TIMER_SYNC_RTCC_CHANNEL_DEFAULT (0U)
+#endif
+
+/// Default timer synchronization configuration
+#define RAIL_TIMER_SYNC_DEFAULT { \
+ RAIL_TIMER_SYNC_PRS_CHANNEL_DEFAULT, \
+ RAIL_TIMER_SYNC_RTCC_CHANNEL_DEFAULT, \
+ RAIL_SLEEP_CONFIG_TIMERSYNC_ENABLED, \
+}
+
+/** @} */ // end of group Sleep
+
+/**
+ * @addtogroup Data_Management_EFR32XG2X EFR32XG2X
+ * @{
+ * @ingroup Data_Management
+ */
+
/// Fixed-width type indicating the needed alignment for RX and TX FIFOs. Note
/// that docs.silabs.com will incorrectly indicate that this is always a
/// uint8_t, but it does vary across RAIL platforms.
@@ -826,8 +1409,40 @@ typedef struct RAIL_AntennaConfig {
/// Alignment that is needed for the RX and TX FIFOs.
#define RAIL_FIFO_ALIGNMENT (sizeof(RAIL_FIFO_ALIGNMENT_TYPE))
+/** @} */ // end of group Data_Management_EFR32
+
+/**
+ * @addtogroup State_Transitions_EFR32XG2X
+ * @{
+ * @ingroup State_Transitions
+ */
+
+/**
+ * @def RAIL_MINIMUM_TRANSITION_US
+ * @brief The minimum value for a consistent RAIL transition
+ * @note Transitions may need to be slower than this when using longer
+ * \ref RAIL_TxPowerConfig_t::rampTime values
+ */
+#define RAIL_MINIMUM_TRANSITION_US (100U)
+
+/**
+ * @def RAIL_MAXIMUM_TRANSITION_US
+ * @brief The maximum value for a consistent RAIL transition
+ */
+#define RAIL_MAXIMUM_TRANSITION_US (1000000U)
+
+/**
+ * @typedef RAIL_TransitionTime_t
+ * @brief Suitable type for the supported transition time range.
+ */
+typedef uint32_t RAIL_TransitionTime_t;
+
+/** @} */ // end of group State_Transitions_EFR32
+
#ifdef __cplusplus
}
#endif
-#endif
+#endif //__RAIL_TYPES_H__
+
+#endif //__RAIL_CHIP_SPECIFIC_H_
diff --git a/mcu/efr/common/vendor/rail_lib/common/rail_features.h b/mcu/efr/common/vendor/rail_lib/common/rail_features.h
index a92100d9..336a2fef 100644
--- a/mcu/efr/common/vendor/rail_lib/common/rail_features.h
+++ b/mcu/efr/common/vendor/rail_lib/common/rail_features.h
@@ -28,6 +28,8 @@
* 3. This notice may not be removed or altered from any source distribution.
*
******************************************************************************/
+#include "em_device.h"
+#include "rail_types.h"
#ifndef __RAIL_FEATURES_H__
#define __RAIL_FEATURES_H__
@@ -36,9 +38,6 @@
extern "C" {
#endif
-#include "em_device.h"
-#include "rail_types.h"
-
/**
* @addtogroup RAIL_API RAIL API
* @{
@@ -128,10 +127,73 @@ bool RAIL_Supports2p4GHzBand(RAIL_Handle_t railHandle);
*/
bool RAIL_SupportsSubGHzBand(RAIL_Handle_t railHandle);
+/// Boolean to indicate whether the selected chip supports OFDM PA.
+/// See also runtime refinement \ref RAIL_SupportsOFDMPA().
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 5)
+#define RAIL_SUPPORTS_OFDM_PA 1
+#else
+#define RAIL_SUPPORTS_OFDM_PA 0
+#endif
+
+/**
+ * Indicate whether RAIL supports OFDM band operation on this chip.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return true if OFDM operation is supported; false otherwise.
+ *
+ * Runtime refinement of compile-time \ref RAIL_SUPPORTS_OFDM_PA.
+ */
+bool RAIL_SupportsOFDMPA(RAIL_Handle_t railHandle);
+
+/// Boolean to indicate whether the selected chip supports
+/// bit masked address filtering.
+/// See also runtime refinement \ref RAIL_SupportsAddrFilterAddressBitMask().
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2)
+#define RAIL_SUPPORTS_ADDR_FILTER_ADDRESS_BIT_MASK 1
+#else
+#define RAIL_SUPPORTS_ADDR_FILTER_ADDRESS_BIT_MASK 0
+#endif
+
+/**
+ * Indicate whether this chip supports bit masked address filtering
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return true if bit masked address filtering is supported; false otherwise.
+ *
+ * Runtime refinement of compile-time
+ * \ref RAIL_SUPPORTS_ADDR_FILTER_ADDRESS_BIT_MASK.
+ */
+bool RAIL_SupportsAddrFilterAddressBitMask(RAIL_Handle_t railHandle);
+
+/// Boolean to indicate whether the selected chip supports
+/// address filter mask information for incoming packets in
+/// \ref RAIL_RxPacketInfo_t::filterMask and
+/// \ref RAIL_IEEE802154_Address_t::filterMask.
+/// See also runtime refinement \ref RAIL_SupportsAddrFilterMask().
+#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1)
+#define RAIL_SUPPORTS_ADDR_FILTER_MASK 1
+#else
+#define RAIL_SUPPORTS_ADDR_FILTER_MASK 0
+#endif
+
+/**
+ * Indicate whether this chip supports address filter mask information
+ * for incoming packets in
+ * \ref RAIL_RxPacketInfo_t::filterMask and
+ * \ref RAIL_IEEE802154_Address_t::filterMask.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return true if address filter information is supported; false otherwise
+ * (in which case \ref RAIL_RxPacketInfo_t::filterMask value is undefined).
+ *
+ * Runtime refinement of compile-time \ref RAIL_SUPPORTS_ADDR_FILTER_MASK.
+ */
+bool RAIL_SupportsAddrFilterMask(RAIL_Handle_t railHandle);
+
/// Boolean to indicate whether the selected chip supports
/// alternate power settings for the Power Amplifier.
/// See also runtime refinement \ref RAIL_SupportsAlternateTxPower().
-#if (_SILICON_LABS_32B_SERIES_1_CONFIG > 1)
+#if (_SILICON_LABS_32B_SERIES_1_CONFIG > 1) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 3)
#define RAIL_SUPPORTS_ALTERNATE_TX_POWER 1
#else
#define RAIL_SUPPORTS_ALTERNATE_TX_POWER 0
@@ -152,7 +214,8 @@ bool RAIL_SupportsAlternateTxPower(RAIL_Handle_t railHandle);
/// Boolean to indicate whether the selected chip supports antenna diversity.
/// See also runtime refinement \ref RAIL_SupportsAntennaDiversity().
-#if ((_SILICON_LABS_32B_SERIES_1_CONFIG >= 2) || (_SILICON_LABS_32B_SERIES == 2))
+#if ((_SILICON_LABS_32B_SERIES_1_CONFIG >= 2) \
+ || (_SILICON_LABS_32B_SERIES == 2))
#define RAIL_SUPPORTS_ANTENNA_DIVERSITY 1
#else
#define RAIL_SUPPORTS_ANTENNA_DIVERSITY 0
@@ -214,9 +277,28 @@ bool RAIL_SupportsChannelHopping(RAIL_Handle_t railHandle);
*/
bool RAIL_SupportsDualSyncWords(RAIL_Handle_t railHandle);
+/// Boolean to indicate whether the selected chip supports automatic transitions
+/// from TX to TX.
+/// See also runtime refinement \ref RAIL_SupportsTxToTx().
+#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1)
+#define RAIL_SUPPORTS_TX_TO_TX 1
+#else
+#define RAIL_SUPPORTS_TX_TO_TX 0
+#endif
+
+/**
+ * Indicate whether this chip supports automatic TX to TX transitions.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return true if TX to TX transitions are supported; false otherwise.
+ *
+ * Runtime refinement of compile-time \ref RAIL_SUPPORTS_TX_TO_TX.
+ */
+bool RAIL_SupportsTxToTx(RAIL_Handle_t railHandle);
+
/// Boolean to indicate whether the selected chip supports thermistor measurements.
/// See also runtime refinement \ref RAIL_SupportsExternalThermistor().
-#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 2)
+#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 3))
#define RAIL_SUPPORTS_EXTERNAL_THERMISTOR 1
#else
#define RAIL_SUPPORTS_EXTERNAL_THERMISTOR 0
@@ -272,6 +354,26 @@ bool RAIL_SupportsPrecisionLFRCO(RAIL_Handle_t railHandle);
*/
bool RAIL_SupportsRadioEntropy(RAIL_Handle_t railHandle);
+/// Boolean to indicate whether the selected chip supports
+/// RFSENSE Energy Detection Mode.
+/// See also runtime refinement \ref RAIL_SupportsRfSenseEnergyDetection().
+#if ((_SILICON_LABS_32B_SERIES == 1) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 2))
+#define RAIL_SUPPORTS_RFSENSE_ENERGY_DETECTION 1
+#else
+#define RAIL_SUPPORTS_RFSENSE_ENERGY_DETECTION 0
+#endif
+
+/**
+ * Indicate whether RAIL supports RFSENSE Energy Detection Mode on this chip.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return true if RFSENSE Energy Detection Mode is supported; false otherwise.
+ *
+ * Runtime refinement of compile-time
+ * \ref RAIL_SUPPORTS_RFSENSE_ENERGY_DETECTION.
+ */
+bool RAIL_SupportsRfSenseEnergyDetection(RAIL_Handle_t railHandle);
+
/// Boolean to indicate whether the selected chip supports
/// RFSENSE Selective(OOK) Mode.
/// See also runtime refinement \ref RAIL_SupportsRfSenseSelectiveOok().
@@ -436,7 +538,7 @@ bool RAIL_BLE_Supports2Mbps(RAIL_Handle_t railHandle)
/// Antenna Switching needed for Angle-of-Arrival receives or
/// Angle-of-Departure transmits.
/// See also runtime refinement \ref RAIL_BLE_SupportsAntennaSwitching().
-#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 2)
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 2 || _SILICON_LABS_32B_SERIES_2_CONFIG == 4)
#define RAIL_BLE_SUPPORTS_ANTENNA_SWITCHING RAIL_SUPPORTS_PROTOCOL_BLE
#else
#define RAIL_BLE_SUPPORTS_ANTENNA_SWITCHING 0
@@ -457,10 +559,11 @@ bool RAIL_BLE_SupportsAntennaSwitching(RAIL_Handle_t railHandle);
/// See also runtime refinement \ref RAIL_BLE_SupportsCodedPhy().
#if ((_SILICON_LABS_32B_SERIES_1_CONFIG == 3) \
|| (_SILICON_LABS_32B_SERIES_2_CONFIG == 1) \
- || (_SILICON_LABS_32B_SERIES_2_CONFIG == 2))
+ || (_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \
+ || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4))
#define RAIL_BLE_SUPPORTS_CODED_PHY RAIL_SUPPORTS_PROTOCOL_BLE
#else
-#define RAIL_BLE_SUPPORTS_CODED_PHY 0
+#define RAIL_BLE_SUPPORTS_CODED_PHY 0
#endif
/// Backwards-compatible synonym of \ref RAIL_BLE_SUPPORTS_CODED_PHY.
#define RAIL_FEAT_BLE_CODED RAIL_BLE_SUPPORTS_CODED_PHY
@@ -475,11 +578,32 @@ bool RAIL_BLE_SupportsAntennaSwitching(RAIL_Handle_t railHandle);
*/
bool RAIL_BLE_SupportsCodedPhy(RAIL_Handle_t railHandle);
+/// Boolean to indicate whether the selected chip supports the BLE Simulscan PHY
+/// used for simultaneous BLE 1Mbps and Coded PHY reception.
+/// See also runtime refinement \ref RAIL_BLE_SupportsSimulscanPhy().
+#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \
+ || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4))
+#define RAIL_BLE_SUPPORTS_SIMULSCAN_PHY RAIL_SUPPORTS_PROTOCOL_BLE
+#else
+#define RAIL_BLE_SUPPORTS_SIMULSCAN_PHY 0
+#endif
+
+/**
+ * Indicate whether this chip supports BLE Simulscan PHY used for simultaneous
+ * BLE 1Mbps and Coded PHY reception.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return true if BLE Simulscan PHY is supported; false otherwise.
+ *
+ * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_SIMULSCAN_PHY.
+ */
+bool RAIL_BLE_SupportsSimulscanPhy(RAIL_Handle_t railHandle);
+
/// Boolean to indicate whether the selected chip supports BLE
/// CTE (Constant Tone Extension) needed for Angle-of-Arrival/Departure
/// transmits.
/// See also runtime refinement \ref RAIL_BLE_SupportsCte().
-#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 2)
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 2 || _SILICON_LABS_32B_SERIES_2_CONFIG == 4)
#define RAIL_BLE_SUPPORTS_CTE RAIL_SUPPORTS_PROTOCOL_BLE
#else
#define RAIL_BLE_SUPPORTS_CTE 0
@@ -518,7 +642,7 @@ bool RAIL_BLE_SupportsQuuppa(RAIL_Handle_t railHandle);
/// Boolean to indicate whether the selected chip supports BLE
/// IQ Sampling needed for Angle-of-Arrival/Departure receives.
/// See also runtime refinement \ref RAIL_BLE_SupportsIQSampling().
-#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 2)
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 2 || _SILICON_LABS_32B_SERIES_2_CONFIG == 4)
#define RAIL_BLE_SUPPORTS_IQ_SAMPLING RAIL_SUPPORTS_PROTOCOL_BLE
#else
#define RAIL_BLE_SUPPORTS_IQ_SAMPLING 0
@@ -535,13 +659,16 @@ bool RAIL_BLE_SupportsQuuppa(RAIL_Handle_t railHandle);
*/
bool RAIL_BLE_SupportsIQSampling(RAIL_Handle_t railHandle);
-/// Backwards-compatible synonym of \ref RAIL_BLE_SUPPORTS_ANTENNA_SWITCHING,
-/// or \ref RAIL_BLE_SUPPORTS_IQ_SAMPLING, or \ref RAIL_BLE_SUPPORTS_CTE.
-#define RAIL_FEAT_BLE_AOX_SUPPORTED \
+/// Boolean to indicate whether the selected chip supports some BLE AOX
+/// features.
+#define RAIL_BLE_SUPPORTS_AOX \
(RAIL_BLE_SUPPORTS_ANTENNA_SWITCHING \
|| RAIL_BLE_SUPPORTS_IQ_SAMPLING \
|| RAIL_BLE_SUPPORTS_CTE)
+/// Backwards-compatible synonym of \ref RAIL_BLE_SUPPORTS_AOX
+#define RAIL_FEAT_BLE_AOX_SUPPORTED RAIL_BLE_SUPPORTS_AOX
+
/// Boolean to indicate whether the selected chip supports BLE PHY switch to RX
/// functionality, which is used to switch BLE PHYs at a specific time
/// to receive auxiliary packets.
@@ -560,7 +687,7 @@ bool RAIL_BLE_SupportsIQSampling(RAIL_Handle_t railHandle);
* to receive auxiliary packets.
*
* @param[in] railHandle A RAIL instance handle.
- * @return true if BLE Phy switch to RX is supported; false otherwise.
+ * @return true if BLE PHY switch to RX is supported; false otherwise.
*
* Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_PHY_SWITCH_TO_RX.
*/
@@ -592,7 +719,7 @@ bool RAIL_SupportsProtocolIEEE802154(RAIL_Handle_t railHandle);
/// 802.15.4 Wi-Fi Coexistence PHY.
/// See also runtime refinement \ref RAIL_IEEE802154_SupportsCoexPhy().
#if (_SILICON_LABS_32B_SERIES_1_CONFIG > 1)
-#define RAIL_IEEE802154_SUPPORTS_COEX_PHY RAIL_SUPPORTS_PROTOCOL_IEEE802154
+#define RAIL_IEEE802154_SUPPORTS_COEX_PHY (RAIL_SUPPORTS_PROTOCOL_IEEE802154 && RAIL_SUPPORTS_2P4GHZ_BAND)
#else
#define RAIL_IEEE802154_SUPPORTS_COEX_PHY 0
#endif
@@ -609,6 +736,21 @@ bool RAIL_SupportsProtocolIEEE802154(RAIL_Handle_t railHandle);
*/
bool RAIL_IEEE802154_SupportsCoexPhy(RAIL_Handle_t railHandle);
+/// Boolean to indicate whether the selected chip supports a front end module.
+/// See also runtime refinement \ref RAIL_IEEE802154_SupportsFemPhy().
+#define RAIL_IEEE802154_SUPPORTS_FEM_PHY (RAIL_SUPPORTS_PROTOCOL_IEEE802154 && RAIL_SUPPORTS_2P4GHZ_BAND)
+
+/**
+ * Indicate whether this chip supports the IEEE 802.15.4
+ * front end module optimized PHY.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return true if a front end module is supported; false otherwise.
+ *
+ * Runtime refinement of compile-time \ref RAIL_IEEE802154_SUPPORTS_FEM_PHY.
+ */
+bool RAIL_IEEE802154_SupportsFemPhy(RAIL_Handle_t railHandle);
+
/// Boolean to indicate whether the selected chip supports
/// IEEE 802.15.4E-2012 feature subset needed for Zigbee R22 GB868.
/// See also runtime refinement \ref
@@ -713,11 +855,53 @@ bool RAIL_IEEE802154_SupportsEMultipurposeFrames(RAIL_Handle_t railHandle);
*/
bool RAIL_IEEE802154_SupportsGSubsetGB868(RAIL_Handle_t railHandle);
+/// Boolean to indicate whether the selected chip supports
+/// dynamic FEC
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1)
+#define RAIL_IEEE802154_SUPPORTS_G_DYNFEC \
+ RAIL_FEAT_IEEE802154_G_GB868_SUPPORTED // limit to SUBGHZ for now
+#else
+#define RAIL_IEEE802154_SUPPORTS_G_DYNFEC 0
+#endif
+
+/**
+ * Indicate whether this chip supports IEEE 802.15.4G dynamic FEC
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return true if dynamic FEC is supported; false otherwise.
+ *
+ * Runtime refinement of compile-time \ref
+ * RAIL_IEEE802154_SUPPORTS_G_DYNFEC.
+ */
+bool RAIL_IEEE802154_SupportsGDynFec(RAIL_Handle_t railHandle);
+
+/// Boolean to indicate whether the selected chip supports
+/// Wi-SUN mode switching
+/// See also runtime refinement \ref
+/// RAIL_IEEE802154_SupportsGModeSwitch().
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 5)
+#define RAIL_IEEE802154_SUPPORTS_G_MODESWITCH \
+ RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868 // limit to SUBGHZ for now
+#else
+#define RAIL_IEEE802154_SUPPORTS_G_MODESWITCH 0
+#endif
+
+/**
+ * Indicate whether this chip supports Wi-SUN mode switching
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return true if Wi-SUN mode switching is supported; false otherwise.
+ *
+ * Runtime refinement of compile-time \ref
+ * RAIL_IEEE802154_SUPPORTS_G_MODESWITCH.
+ */
+bool RAIL_IEEE802154_SupportsGModeSwitch(RAIL_Handle_t railHandle);
+
/// Boolean to indicate whether the selected chip supports
/// IEEE 802.15.4G-2012 reception and transmission of frames
/// with 4-byte CRC.
/// See also runtime refinement \ref RAIL_IEEE802154_SupportsG4ByteCrc().
-#if (_SILICON_LABS_32B_SERIES_1_CONFIG > 1)
+#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1)
#define RAIL_IEEE802154_SUPPORTS_G_4BYTE_CRC RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868
#else
#define RAIL_IEEE802154_SUPPORTS_G_4BYTE_CRC 0
@@ -742,7 +926,7 @@ bool RAIL_IEEE802154_SupportsG4ByteCrc(RAIL_Handle_t railHandle);
/// IEEE 802.15.4G-2012 reception of unwhitened frames.
/// See also runtime refinement \ref
/// RAIL_IEEE802154_SupportsGUnwhitenedRx().
-#if (_SILICON_LABS_32B_SERIES_1_CONFIG > 1)
+#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1)
#define RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_RX RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868
#else
#define RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_RX 0
@@ -769,7 +953,7 @@ bool RAIL_IEEE802154_SupportsGUnwhitenedRx(RAIL_Handle_t railHandle);
/// IEEE 802.15.4G-2012 transmission of unwhitened frames.
/// See also runtime refinement \ref
/// RAIL_IEEE802154_SupportsGUnwhitenedTx().
-#if (_SILICON_LABS_32B_SERIES_1_CONFIG > 1)
+#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1)
#define RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_TX RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868
#else
#define RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_TX 0
@@ -853,13 +1037,50 @@ bool RAIL_IEEE802154_SupportsCancelFramePendingLookup(RAIL_Handle_t railHandle);
*/
bool RAIL_IEEE802154_SupportsEarlyFramePendingLookup(RAIL_Handle_t railHandle);
+/// Boolean to indicate whether the selected chip supports dual PA configs for mode switch
+/// or concurrent mode.
+/// See also runtime refinement \ref RAIL_IEEE802154_SupportsDualPaConfig().
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 5)
+#define RAIL_IEEE802154_SUPPORTS_DUAL_PA_CONFIG 1
+#else
+#define RAIL_IEEE802154_SUPPORTS_DUAL_PA_CONFIG 0
+#endif
+
+/**
+ * Indicate whether RAIL supports dual PA mode on this chip.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return true if the dual PA mode is supported; false otherwise.
+ *
+ * Runtime refinement of compile-time \ref RAIL_IEEE802154_SUPPORTS_DUAL_PA_CONFIG.
+ */
+bool RAIL_IEEE802154_SupportsDualPaConfig(RAIL_Handle_t railHandle);
+
+/// Boolean to indicate whether the selected chip supports IEEE 802.15.4 PHY
+/// with custom settings
+#if ((_SILICON_LABS_32B_SERIES_1_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_1_CONFIG == 3))
+#define RAIL_IEEE802154_SUPPORTS_CUSTOM1_PHY (RAIL_SUPPORTS_PROTOCOL_IEEE802154 && RAIL_SUPPORTS_2P4GHZ_BAND)
+#else
+#define RAIL_IEEE802154_SUPPORTS_CUSTOM1_PHY 0
+#endif
+
+/**
+ * Indicate whether this chip supports the IEEE 802.15.4 PHY with custom settings.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return true if the 802.15.4 PHY with custom settings is supported; false otherwise.
+ *
+ * Runtime refinement of compile-time \ref RAIL_IEEE802154_SUPPORTS_CUSTOM1_PHY.
+ */
+bool RAIL_IEEE802154_SupportsCustom1Phy(RAIL_Handle_t railHandle);
+
// Z-Wave features
// Some features may not be available on all platforms
// due to radio hardware limitations.
/// Boolean to indicate whether the selected chip supports Z-Wave.
/// See also runtime refinement \ref RAIL_SupportsProtocolZWave().
-#if (_SILICON_LABS_32B_SERIES_1_CONFIG >= 3)
+#if (_SILICON_LABS_32B_SERIES_1_CONFIG >= 3) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 3)
#define RAIL_SUPPORTS_PROTOCOL_ZWAVE RAIL_SUPPORTS_SUBGHZ_BAND
#else
#define RAIL_SUPPORTS_PROTOCOL_ZWAVE 0
@@ -877,6 +1098,62 @@ bool RAIL_IEEE802154_SupportsEarlyFramePendingLookup(RAIL_Handle_t railHandle);
*/
bool RAIL_SupportsProtocolZWave(RAIL_Handle_t railHandle);
+/// Boolean to indicate whether the selected chip supports energy detect PHY.
+/// See also runtime refinement \ref RAIL_ZWAVE_SupportsEnergyDetectPhy().
+#if (_SILICON_LABS_32B_SERIES_1_CONFIG >= 3)
+#define RAIL_ZWAVE_SUPPORTS_ED_PHY RAIL_SUPPORTS_PROTOCOL_ZWAVE
+#else
+#define RAIL_ZWAVE_SUPPORTS_ED_PHY 0
+#endif
+
+/**
+ * Indicate whether this chip supports the Z-Wave energy detect PHY.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return true if the Z-Wave energy detect PHY is supported; false otherwise.
+ *
+ * Runtime refinement of compile-time \ref RAIL_ZWAVE_SUPPORTS_ED_PHY.
+ */
+bool RAIL_ZWAVE_SupportsEnergyDetectPhy(RAIL_Handle_t railHandle);
+
+/// Boolean to indicate whether the selected chip supports concurrent PHY.
+/// See also runtime refinement \ref RAIL_ZWAVE_SupportsConcPhy().
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 3)
+#define RAIL_ZWAVE_SUPPORTS_CONC_PHY RAIL_SUPPORTS_PROTOCOL_ZWAVE
+#else
+#define RAIL_ZWAVE_SUPPORTS_CONC_PHY 0
+#endif
+
+/**
+ * Indicate whether this chip supports the Z-Wave concurrent PHY.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return true if the Z-Wave concurrent PHY is supported; false otherwise.
+ *
+ * Runtime refinement of compile-time \ref RAIL_ZWAVE_SUPPORTS_CONC_PHY.
+ */
+bool RAIL_ZWAVE_SupportsConcPhy(RAIL_Handle_t railHandle);
+
+/// Boolean to indicate whether the selected chip supports SQ-based PHY.
+/// See also runtime refinement \ref RAIL_SupportsSQPhy().
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \
+ || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) \
+ || (_SILICON_LABS_32B_SERIES_2_CONFIG == 5)
+#define RAIL_SUPPORTS_SQ_PHY 1
+#else
+#define RAIL_SUPPORTS_SQ_PHY 0
+#endif
+
+/**
+ * Indicate whether this chip supports SQ-based PHY.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return true if the SQ-based PHY is supported; false otherwise.
+ *
+ * Runtime refinement of compile-time \ref RAIL_SUPPORTS_SQ_PHY.
+ */
+bool RAIL_SupportsSQPhy(RAIL_Handle_t railHandle);
+
/// Boolean to indicate whether the code supports Z-Wave
/// region information in PTI and
/// newer RAIL_ZWAVE_RegionConfig_t structure
@@ -899,6 +1176,97 @@ bool RAIL_SupportsProtocolZWave(RAIL_Handle_t railHandle);
*/
bool RAIL_ZWAVE_SupportsRegionPti(RAIL_Handle_t railHandle);
+/// Boolean to indicate whether the selected chip supports
+/// direct mode.
+/// See also runtime refinement \ref RAIL_SupportsDirectMode().
+#if ((_SILICON_LABS_32B_SERIES == 1) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 3))
+#define RAIL_SUPPORTS_DIRECT_MODE 1
+#else
+#define RAIL_SUPPORTS_DIRECT_MODE 0
+#endif
+
+/**
+ * Indicate whether this chip supports direct mode.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return true if direct mode is supported; false otherwise.
+ *
+ * Runtime refinement of compile-time \ref
+ * RAIL_SUPPORTS_DIRECT_MODE.
+ */
+bool RAIL_SupportsDirectMode(RAIL_Handle_t railHandle);
+
+/// Boolean to indicate whether the selected chip supports
+/// RX direct mode data to FIFO.
+/// See also runtime refinement \ref RAIL_SupportsRxDirectModeDataToFifo().
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 3)
+#define RAIL_SUPPORTS_RX_DIRECT_MODE_DATA_TO_FIFO 1
+#else
+#define RAIL_SUPPORTS_RX_DIRECT_MODE_DATA_TO_FIFO 0
+#endif
+
+/**
+ * Indicate whether this chip supports RX direct mode data to FIFO.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return true if direct mode data to FIFO is supported; false otherwise.
+ *
+ * Runtime refinement of compile-time \ref
+ * RAIL_SUPPORTS_RX_DIRECT_MODE_DATA_TO_FIFO.
+ */
+bool RAIL_SupportsRxDirectModeDataToFifo(RAIL_Handle_t railHandle);
+
+/// Boolean to indicate whether the selected chip supports
+/// MFM protocol.
+/// See also runtime refinement \ref RAIL_SupportsMfm().
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 3)
+#define RAIL_SUPPORTS_MFM 1
+#else
+#define RAIL_SUPPORTS_MFM 0
+#endif
+
+/**
+ * Indicate whether this chip supports MFM protocol.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return true if MFM protocol is supported; false otherwise.
+ *
+ * Runtime refinement of compile-time \ref RAIL_SUPPORTS_MFM.
+ */
+bool RAIL_SupportsMfm(RAIL_Handle_t railHandle);
+
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 4)
+/// Boolean to indicate whether the selected chip supports
+/// 802.15.4 signal detection
+ #define RAIL_IEEE802154_SUPPORTS_SIGNAL_IDENTIFIER (RAIL_SUPPORTS_PROTOCOL_IEEE802154)
+/// Boolean to indicate whether the selected chip supports
+/// BLE signal detection
+ #define RAIL_BLE_SUPPORTS_SIGNAL_IDENTIFIER (RAIL_SUPPORTS_PROTOCOL_BLE)
+#else
+/// Boolean to indicate whether the selected chip supports
+/// 802.15.4 signal detection
+ #define RAIL_IEEE802154_SUPPORTS_SIGNAL_IDENTIFIER 0
+/// Boolean to indicate whether the selected chip supports
+/// BLE signal detection
+ #define RAIL_BLE_SUPPORTS_SIGNAL_IDENTIFIER 0
+#endif
+
+/**
+ * Indicate whether this chip supports IEEE 802.15.4 signal identifier.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return true if signal identifier is supported; false otherwise.
+ */
+bool RAIL_IEEE802154_SupportsSignalIdentifier(RAIL_Handle_t railHandle);
+
+/**
+ * Indicate whether this chip supports BLE signal identifier.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return true if signal identifier is supported; false otherwise.
+ */
+bool RAIL_BLE_SupportsSignalIdentifier(RAIL_Handle_t railHandle);
+
/** @} */ // end of group Features
/** @} */ // end of group RAIL_API
diff --git a/mcu/efr/common/vendor/rail_lib/common/rail_types.h b/mcu/efr/common/vendor/rail_lib/common/rail_types.h
index 75f4e86d..59b433f0 100644
--- a/mcu/efr/common/vendor/rail_lib/common/rail_types.h
+++ b/mcu/efr/common/vendor/rail_lib/common/rail_types.h
@@ -92,7 +92,12 @@ typedef struct RAIL_Version {
/**
* @typedef RAIL_Handle_t
- * @brief A handle of a RAIL instance, as returned from RAIL_Init().
+ * @brief A generic handle to a particular radio (e.g. RAIL_EFR32_HANDLE),
+ * or a real handle of a RAIL instance, as returned from RAIL_Init().
+ *
+ * Generic handles should be used for certain RAIL APIs that are called
+ * prior to RAIL initialization. However, once RAIL has been initialized,
+ * the real handle returned by RAIL_Init() should be used instead.
*/
typedef void *RAIL_Handle_t;
@@ -111,6 +116,9 @@ RAIL_ENUM(RAIL_Status_t) {
RAIL_STATUS_INVALID_CALL, /**< RAIL function is called in an invalid order. */
RAIL_STATUS_SUSPENDED, /**< RAIL function did not finish in the allotted
time. */
+ RAIL_STATUS_SCHED_ERROR, /**< RAIL function could not be scheduled
+ by the Radio scheduler. Only issued when
+ using a Multiprotocol application. */
};
#ifndef DOXYGEN_SHOULD_SKIP_THIS
@@ -120,12 +128,13 @@ RAIL_ENUM(RAIL_Status_t) {
#define RAIL_STATUS_INVALID_STATE ((RAIL_Status_t) RAIL_STATUS_INVALID_STATE)
#define RAIL_STATUS_INVALID_CALL ((RAIL_Status_t) RAIL_STATUS_INVALID_CALL)
#define RAIL_STATUS_SUSPENDED ((RAIL_Status_t) RAIL_STATUS_SUSPENDED)
+#define RAIL_STATUS_SCHED_ERROR ((RAIL_Status_t) RAIL_STATUS_SCHED_ERROR)
#endif//DOXYGEN_SHOULD_SKIP_THIS
/**
* A pointer to init complete callback function
*
- * @param[in] railHandle A handle for RAIL instance.
+ * @param[in] railHandle The initialized RAIL instance handle.
*
*/
typedef void (*RAIL_InitCompleteCallbackPtr_t)(RAIL_Handle_t railHandle);
@@ -133,6 +142,20 @@ typedef void (*RAIL_InitCompleteCallbackPtr_t)(RAIL_Handle_t railHandle);
/** A value to signal that RAIL should not use DMA. */
#define RAIL_DMA_INVALID (0xFFU)
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+
+/**
+ * A linked list structure for RAIL state buffers which \ref RAIL_Init()
+ * utilizes for managing internal RAIL state.
+ */
+typedef struct RAIL_StateBufferEntry {
+ struct RAIL_StateBufferEntry *next; /**< pointer to next buffer in linked list */
+ uint32_t bufferBytes; /**< size of the buffer */
+ uint64_t *buffer; /**< pointer to the buffer in RAM */
+} RAIL_StateBufferEntry_t;
+
+#endif//DOXYGEN_SHOULD_SKIP_THIS
+
/** @} */ // end of group General
/******************************************************************************
@@ -149,6 +172,21 @@ typedef void (*RAIL_InitCompleteCallbackPtr_t)(RAIL_Handle_t railHandle);
*/
typedef uint32_t RAIL_Time_t;
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+/**
+ * @typedef RAIL_TimerTick_t
+ * @brief Internal RAIL hardware timer tick that drives the RAIL timebase.
+ *
+ * @note \ref RAIL_TimerTick_t does not use the full 32-bit range since we also
+ * account for fractional error drift on timebase overflow. This counts up
+ * to ~17 minutes before wrapping.
+ *
+ * @note \ref RAIL_TimerTicksToUs() can be used to convert the delta between
+ * two \ref RAIL_TimerTick_t values to microseconds.
+ */
+typedef uint32_t RAIL_TimerTick_t;
+#endif//DOXYGEN_SHOULD_SKIP_THIS
+
/**
* A pointer to the callback called when the RAIL timer expires.
*
@@ -319,7 +357,7 @@ typedef struct RAIL_PacketTimeStamp {
* field. This should account for all bytes sent over the air after
* the Preamble and Sync word(s) including CRC bytes.
*/
- uint32_t totalPacketBytes;
+ uint16_t totalPacketBytes;
/**
* A RAIL_PacketTimePosition_t value specifying the packet position
* to return in the packetTime field.
@@ -355,6 +393,9 @@ RAIL_ENUM(RAIL_SleepConfig_t) {
/**
* @struct RAIL_TimerSyncConfig_t
* @brief Channel values used to perform timer sync before and after sleep.
+ *
+ * The default value of this structure is provided in the
+ * \ref RAIL_TIMER_SYNC_DEFAULT macro.
*/
typedef struct RAIL_TimerSyncConfig {
/**
@@ -365,6 +406,10 @@ typedef struct RAIL_TimerSyncConfig {
* RTCC Channel used for timer sync operations
*/
uint8_t rtccChannel;
+ /**
+ * Whether to sync the timer before and after sleeping
+ */
+ RAIL_SleepConfig_t sleep;
} RAIL_TimerSyncConfig_t;
/** @} */ // end of group Sleep
@@ -409,86 +454,249 @@ typedef struct RAIL_SchedulerInfo {
RAIL_Time_t transactionTime;
} RAIL_SchedulerInfo_t;
+/** Radio Scheduler Status mask*/
+#define RAIL_SCHEDULER_STATUS_MASK 0x0FU
+/** Radio Scheduler Status shift*/
+#define RAIL_SCHEDULER_STATUS_SHIFT 0
+
+/** Radio Scheduler Task mask*/
+#define RAIL_SCHEDULER_TASK_MASK 0xF0U
+/** Radio Scheduler Task shift*/
+#define RAIL_SCHEDULER_TASK_SHIFT 4
/**
* @enum RAIL_SchedulerStatus_t
* @brief Multiprotocol scheduler status returned by RAIL_GetSchedulerStatus().
+ *
+ * \ref Multiprotocol scheduler status is a combination of the upper 4 bits which
+ * constitute the type of scheduler task and the lower 4 bits which constitute
+ * the type of scheduler error.
*/
RAIL_ENUM(RAIL_SchedulerStatus_t) {
+ /** Lower 4 bits of uint8_t capture the different Radio Scheduler errors */
/** Multiprotocol scheduler reports no error. */
- RAIL_SCHEDULER_STATUS_NO_ERROR,
+ RAIL_SCHEDULER_STATUS_NO_ERROR = (0U << RAIL_SCHEDULER_STATUS_SHIFT),
/**
* The scheduler is disabled or the requested scheduler operation is
* unsupported.
*/
- RAIL_SCHEDULER_STATUS_UNSUPPORTED,
+ RAIL_SCHEDULER_STATUS_UNSUPPORTED = (1U << RAIL_SCHEDULER_STATUS_SHIFT),
/**
- * The scheduled event was started but was interrupted by a higher-priority
+ * The scheduled task was started but was interrupted by a higher-priority
* event before it could be completed.
*/
- RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED,
- /**
- * This task could not be scheduled given its priority and the other tasks
- * running on the system.
- */
- RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL,
- /**
- * Calling the scheduled transmit function returned an error code. See
- * RAIL_StartScheduledTx() for more information about possible errors.
- */
- RAIL_SCHEDULER_STATUS_SCHEDULED_TX_FAIL,
- /**
- * Calling the start transmit function returned an error code. See
- * RAIL_StartTx() for more information about possible errors.
- */
- RAIL_SCHEDULER_STATUS_SINGLE_TX_FAIL,
+ RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED = (2U << RAIL_SCHEDULER_STATUS_SHIFT),
/**
- * Calling the CSMA transmit function returned an error code. See
- * RAIL_StartCcaCsmaTx() for more information about possible errors.
+ * Scheduled task could not be scheduled given its priority and the other
+ * tasks running on the system.
*/
- RAIL_SCHEDULER_STATUS_CCA_CSMA_TX_FAIL,
+ RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL = (3U << RAIL_SCHEDULER_STATUS_SHIFT),
/**
- * Calling the LBT transmit function returned an error code. See
- * RAIL_StartCcaLbtTx() for more information about possible errors.
+ * Calling the RAIL API associated with the Radio scheduler task returned
+ * an error code. See \ref RAIL_GetSchedulerStatus or \ref RAIL_GetSchedulerStatusAlt
+ * for more information about \ref RAIL_Status_t status.
*/
- RAIL_SCHEDULER_STATUS_CCA_LBT_TX_FAIL,
- /**
- * Calling the scheduled receive function returned an error code, which
- * means that the hardware was not set up in
- * time for this receive.
- */
- RAIL_SCHEDULER_STATUS_SCHEDULED_RX_FAIL,
- /**
- * Calling the stream transmit function returned an error code. See
- * RAIL_StartTxStream() for more information about possible errors.
- */
- RAIL_SCHEDULER_STATUS_TX_STREAM_FAIL,
- /**
- * RSSI averaging failed. If this scheduler status occurs,
- * RAIL_GetAverageRssi() will return \ref RAIL_RSSI_INVALID until
- * a RAIL_StartAverageRssi() completes successfully.
- */
- RAIL_SCHEDULER_STATUS_AVERAGE_RSSI_FAIL,
+ RAIL_SCHEDULER_STATUS_TASK_FAIL = (4U << RAIL_SCHEDULER_STATUS_SHIFT),
/**
* An internal error occurred in scheduler data structures, which should
* not happen and indicates a problem.
*/
- RAIL_SCHEDULER_STATUS_INTERNAL_ERROR,
+ RAIL_SCHEDULER_STATUS_INTERNAL_ERROR = (5U << RAIL_SCHEDULER_STATUS_SHIFT),
+
+ /** Upper 4 bits of uint8_t capture the different Radio Scheduler tasks */
+ RAIL_SCHEDULER_TASK_EMPTY = (0U << RAIL_SCHEDULER_TASK_SHIFT),
+ /** Radio scheduler calls \ref RAIL_ScheduleRx(). */
+ RAIL_SCHEDULER_TASK_SCHEDULED_RX = (1U << RAIL_SCHEDULER_TASK_SHIFT),
+ /** Radio scheduler calls \ref RAIL_StartScheduledTx(). */
+ RAIL_SCHEDULER_TASK_SCHEDULED_TX = (2U << RAIL_SCHEDULER_TASK_SHIFT),
+ /** Radio scheduler calls \ref RAIL_StartTx(). */
+ RAIL_SCHEDULER_TASK_SINGLE_TX = (3U << RAIL_SCHEDULER_TASK_SHIFT),
+ /** Radio scheduler calls \ref RAIL_StartCcaCsmaTx(). */
+ RAIL_SCHEDULER_TASK_SINGLE_CCA_CSMA_TX = (4U << RAIL_SCHEDULER_TASK_SHIFT),
+ /** Radio scheduler calls \ref RAIL_StartCcaLbtTx(). */
+ RAIL_SCHEDULER_TASK_SINGLE_CCA_LBT_TX = (5U << RAIL_SCHEDULER_TASK_SHIFT),
+ /** Radio scheduler calls \ref RAIL_StartScheduledCcaCsmaTx(). */
+ RAIL_SCHEDULER_TASK_SCHEDULED_CCA_CSMA_TX = (6U << RAIL_SCHEDULER_TASK_SHIFT),
+ /** Radio scheduler calls \ref RAIL_StartScheduledCcaLbtTx(). */
+ RAIL_SCHEDULER_TASK_SCHEDULED_CCA_LBT_TX = (7U << RAIL_SCHEDULER_TASK_SHIFT),
+ /** Radio scheduler calls \ref RAIL_StartTxStream(). */
+ RAIL_SCHEDULER_TASK_TX_STREAM = (8U << RAIL_SCHEDULER_TASK_SHIFT),
+ /** Radio scheduler calls \ref RAIL_StartAverageRssi(). */
+ RAIL_SCHEDULER_TASK_AVERAGE_RSSI = (9U << RAIL_SCHEDULER_TASK_SHIFT),
+
+ /** \ref RAIL_StartScheduledTx() returned error status. */
+ RAIL_SCHEDULER_STATUS_SCHEDULED_TX_FAIL = (RAIL_SCHEDULER_TASK_SCHEDULED_TX
+ | RAIL_SCHEDULER_STATUS_TASK_FAIL),
+ /** \ref RAIL_StartTx() returned error status. */
+ RAIL_SCHEDULER_STATUS_SINGLE_TX_FAIL = (RAIL_SCHEDULER_TASK_SINGLE_TX
+ | RAIL_SCHEDULER_STATUS_TASK_FAIL),
+ /** \ref RAIL_StartCcaCsmaTx() returned error status. */
+ RAIL_SCHEDULER_STATUS_CCA_CSMA_TX_FAIL = (RAIL_SCHEDULER_TASK_SINGLE_CCA_CSMA_TX
+ | RAIL_SCHEDULER_STATUS_TASK_FAIL),
+ /** \ref RAIL_StartCcaLbtTx() returned error status. */
+ RAIL_SCHEDULER_STATUS_CCA_LBT_TX_FAIL = (RAIL_SCHEDULER_TASK_SINGLE_CCA_LBT_TX
+ | RAIL_SCHEDULER_STATUS_TASK_FAIL),
+ /** \ref RAIL_ScheduleRx() returned error status. */
+ RAIL_SCHEDULER_STATUS_SCHEDULED_RX_FAIL = (RAIL_SCHEDULER_TASK_SCHEDULED_RX
+ | RAIL_SCHEDULER_STATUS_TASK_FAIL),
+ /** \ref RAIL_StartTxStream() returned error status. */
+ RAIL_SCHEDULER_STATUS_TX_STREAM_FAIL = (RAIL_SCHEDULER_TASK_TX_STREAM
+ | RAIL_SCHEDULER_STATUS_TASK_FAIL),
+ /** \ref RAIL_StartAverageRssi() returned error status. */
+ RAIL_SCHEDULER_STATUS_AVERAGE_RSSI_FAIL = (RAIL_SCHEDULER_TASK_AVERAGE_RSSI
+ | RAIL_SCHEDULER_STATUS_TASK_FAIL),
+
+ /** Multiprotocol scheduled receive function internal error. */
+ RAIL_SCHEDULER_SCHEDULED_RX_INTERNAL_ERROR = (RAIL_SCHEDULER_TASK_SCHEDULED_RX
+ | RAIL_SCHEDULER_STATUS_INTERNAL_ERROR),
+ /** Multiprotocol scheduled receive scheduling error. */
+ RAIL_SCHEDULER_SCHEDULED_RX_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_SCHEDULED_RX
+ | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL),
+ /** \ref RAIL_ScheduleRx() operation interrupted */
+ RAIL_SCHEDULER_SCHEDULED_RX_INTERRUPTED = (RAIL_SCHEDULER_TASK_SCHEDULED_RX
+ | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED),
+
+ /** Multiprotocol scheduled Tx internal error. */
+ RAIL_SCHEDULER_SCHEDULED_TX_INTERNAL_ERROR = (RAIL_SCHEDULER_TASK_SCHEDULED_TX
+ | RAIL_SCHEDULER_STATUS_INTERNAL_ERROR),
+ /** Multiprotocol scheduled Tx scheduling error. */
+ RAIL_SCHEDULER_SCHEDULED_TX_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_SCHEDULED_TX
+ | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL),
+ /** \ref RAIL_StartScheduledTx() operation interrupted */
+ RAIL_SCHEDULER_SCHEDULED_TX_INTERRUPTED = (RAIL_SCHEDULER_TASK_SCHEDULED_TX
+ | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED),
+
+ /** Multiprotocol instantaneous Tx internal error. */
+ RAIL_SCHEDULER_SINGLE_TX_INTERNAL_ERROR = (RAIL_SCHEDULER_TASK_SINGLE_TX
+ | RAIL_SCHEDULER_STATUS_INTERNAL_ERROR),
+ /** Multiprotocol instantaneous Tx scheduling error. */
+ RAIL_SCHEDULER_SINGLE_TX_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_SINGLE_TX
+ | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL),
+ /** \ref RAIL_StartTx() operation interrupted */
+ RAIL_SCHEDULER_SINGLE_TX_INTERRUPTED = (RAIL_SCHEDULER_TASK_SINGLE_TX
+ | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED),
+
+ /** Multiprotocol single CSMA transmit function internal error. */
+ RAIL_SCHEDULER_SINGLE_CCA_CSMA_TX_INTERNAL_ERROR = (RAIL_SCHEDULER_TASK_SINGLE_CCA_CSMA_TX
+ | RAIL_SCHEDULER_STATUS_INTERNAL_ERROR),
+ /** Multiprotocol single CSMA transmit scheduling error. */
+ RAIL_SCHEDULER_SINGLE_CCA_CSMA_TX_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_SINGLE_CCA_CSMA_TX
+ | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL),
+ /** \ref RAIL_StartCcaCsmaTx() operation interrupted */
+ RAIL_SCHEDULER_SINGLE_CCA_CSMA_TX_INTERRUPTED = (RAIL_SCHEDULER_TASK_SINGLE_CCA_CSMA_TX
+ | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED),
+
+ /** Multiprotocol single LBT transmit function internal error. */
+ RAIL_SCHEDULER_SINGLE_CCA_LBT_TX_INTERNAL_ERROR = (RAIL_SCHEDULER_TASK_SINGLE_CCA_LBT_TX
+ | RAIL_SCHEDULER_STATUS_INTERNAL_ERROR),
+ /** Multiprotocol single LBT transmit scheduling error. */
+ RAIL_SCHEDULER_SINGLE_CCA_LBT_TX_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_SINGLE_CCA_LBT_TX
+ | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL),
+ /** \ref RAIL_StartCcaLbtTx() operation interrupted */
+ RAIL_SCHEDULER_SINGLE_CCA_LBT_TX_INTERRUPTED = (RAIL_SCHEDULER_TASK_SINGLE_CCA_LBT_TX
+ | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED),
+
+ /** Multiprotocol scheduled CSMA transmit function internal error. */
+ RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_INTERNAL_ERROR = (RAIL_SCHEDULER_TASK_SCHEDULED_CCA_CSMA_TX
+ | RAIL_SCHEDULER_STATUS_INTERNAL_ERROR),
+ /** \ref RAIL_StartScheduledCcaCsmaTx() returned error status. */
+ RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_FAIL = (RAIL_SCHEDULER_TASK_SCHEDULED_CCA_CSMA_TX
+ | RAIL_SCHEDULER_STATUS_TASK_FAIL),
+ /** Multiprotocol scheduled CSMA transmit scheduling error. */
+ RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_SCHEDULED_CCA_CSMA_TX
+ | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL),
+ /** \ref RAIL_StartScheduledCcaCsmaTx() operation interrupted */
+ RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_INTERRUPTED = (RAIL_SCHEDULER_TASK_SCHEDULED_CCA_CSMA_TX
+ | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED),
+
+ /** Multiprotocol scheduled LBT transmit function internal error. */
+ RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_INTERNAL_ERROR = (RAIL_SCHEDULER_TASK_SCHEDULED_CCA_LBT_TX
+ | RAIL_SCHEDULER_STATUS_INTERNAL_ERROR),
+ /** \ref RAIL_StartScheduledCcaLbtTx() returned error status. */
+ RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_FAIL = (RAIL_SCHEDULER_TASK_SCHEDULED_CCA_LBT_TX
+ | RAIL_SCHEDULER_STATUS_TASK_FAIL),
+ /** Multiprotocol scheduled LBT transmit scheduling error. */
+ RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_SCHEDULED_CCA_LBT_TX
+ | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL),
+ /** \ref RAIL_StartScheduledCcaLbtTx() operation interrupted */
+ RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_INTERRUPTED = (RAIL_SCHEDULER_TASK_SCHEDULED_CCA_LBT_TX
+ | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED),
+
+ /** Multiprotocol stream transmit function internal error. */
+ RAIL_SCHEDULER_TX_STREAM_INTERNAL_ERROR = (RAIL_SCHEDULER_TASK_TX_STREAM
+ | RAIL_SCHEDULER_STATUS_INTERNAL_ERROR),
+ /** Multiprotocol stream transmit scheduling error. */
+ RAIL_SCHEDULER_TX_STREAM_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_TX_STREAM
+ | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL),
+ /** \ref RAIL_StartTxStream() operation interrupted */
+ RAIL_SCHEDULER_TX_STREAM_INTERRUPTED = (RAIL_SCHEDULER_TASK_TX_STREAM
+ | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED),
+
+ /** Multiprotocol RSSI averaging function internal error. */
+ RAIL_SCHEDULER_AVERAGE_RSSI_INTERNAL_ERROR = (RAIL_SCHEDULER_TASK_AVERAGE_RSSI
+ | RAIL_SCHEDULER_STATUS_INTERNAL_ERROR),
+ /** Multiprotocol RSSI average scheduling error. */
+ RAIL_SCHEDULER_AVERAGE_RSSI_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_AVERAGE_RSSI
+ | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL),
+ /** \ref RAIL_StartAverageRssi() operation interrupted */
+ RAIL_SCHEDULER_AVERAGE_RSSI_INTERRUPTED = (RAIL_SCHEDULER_TASK_AVERAGE_RSSI
+ | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED),
};
#ifndef DOXYGEN_SHOULD_SKIP_THIS
// Self-referencing defines minimize compiler complaints when using RAIL_ENUM
-#define RAIL_SCHEDULER_STATUS_NO_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_NO_ERROR)
-#define RAIL_SCHEDULER_STATUS_UNSUPPORTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_UNSUPPORTED)
-#define RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED)
-#define RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL)
-#define RAIL_SCHEDULER_STATUS_SCHEDULED_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_SCHEDULED_TX_FAIL)
-#define RAIL_SCHEDULER_STATUS_SINGLE_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_SINGLE_TX_FAIL)
-#define RAIL_SCHEDULER_STATUS_CCA_CSMA_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_CCA_CSMA_TX_FAIL)
-#define RAIL_SCHEDULER_STATUS_CCA_LBT_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_CCA_LBT_TX_FAIL)
-#define RAIL_SCHEDULER_STATUS_SCHEDULED_RX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_SCHEDULED_RX_FAIL)
-#define RAIL_SCHEDULER_STATUS_TX_STREAM_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_TX_STREAM_FAIL)
-#define RAIL_SCHEDULER_STATUS_AVERAGE_RSSI_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_AVERAGE_RSSI_FAIL)
-#define RAIL_SCHEDULER_STATUS_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_INTERNAL_ERROR)
+#define RAIL_SCHEDULER_STATUS_NO_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_NO_ERROR)
+#define RAIL_SCHEDULER_STATUS_UNSUPPORTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_UNSUPPORTED)
+#define RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED)
+#define RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL)
+#define RAIL_SCHEDULER_STATUS_SCHEDULED_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_SCHEDULED_TX_FAIL)
+#define RAIL_SCHEDULER_STATUS_SINGLE_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_SINGLE_TX_FAIL)
+#define RAIL_SCHEDULER_STATUS_CCA_CSMA_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_CCA_CSMA_TX_FAIL)
+#define RAIL_SCHEDULER_STATUS_CCA_LBT_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_CCA_LBT_TX_FAIL)
+#define RAIL_SCHEDULER_STATUS_SCHEDULED_RX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_SCHEDULED_RX_FAIL)
+#define RAIL_SCHEDULER_STATUS_TX_STREAM_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_TX_STREAM_FAIL)
+#define RAIL_SCHEDULER_STATUS_AVERAGE_RSSI_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_AVERAGE_RSSI_FAIL)
+#define RAIL_SCHEDULER_STATUS_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_INTERNAL_ERROR)
+
+#define RAIL_SCHEDULER_TASK_EMPTY ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_EMPTY)
+#define RAIL_SCHEDULER_TASK_SCHEDULED_RX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_SCHEDULED_RX)
+#define RAIL_SCHEDULER_TASK_SCHEDULED_TX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_TX)
+#define RAIL_SCHEDULER_TASK_SINGLE_TX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_SINGLE_TX)
+#define RAIL_SCHEDULER_TASK_SINGLE_CCA_CSMA_TX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_SINGLE_CCA_CSMA_TX)
+#define RAIL_SCHEDULER_TASK_SINGLE_CCA_LBT_TX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_SINGLE_CCA_LBT_TX)
+#define RAIL_SCHEDULER_TASK_SCHEDULED_CCA_CSMA_TX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_SCHEDULED_CCA_CSMA_TX)
+#define RAIL_SCHEDULER_TASK_SCHEDULED_CCA_LBT_TX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_SCHEDULED_CCA_LBT_TX)
+#define RAIL_SCHEDULER_TASK_TX_STREAM ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_TX_STREAM)
+#define RAIL_SCHEDULER_TASK_AVERAGE_RSSI ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_AVERAGE_RSSI)
+
+#define RAIL_SCHEDULER_SCHEDULED_RX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_RX_INTERNAL_ERROR)
+#define RAIL_SCHEDULER_SCHEDULED_RX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_RX_SCHEDULING_ERROR)
+#define RAIL_SCHEDULER_SCHEDULED_RX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_RX_INTERRUPTED)
+#define RAIL_SCHEDULER_SCHEDULED_TX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_TX_INTERNAL_ERROR)
+#define RAIL_SCHEDULER_SCHEDULED_TX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_TX_SCHEDULING_ERROR)
+#define RAIL_SCHEDULER_SCHEDULED_TX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_TX_INTERRUPTED)
+#define RAIL_SCHEDULER_SINGLE_TX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SINGLE_TX_INTERNAL_ERROR)
+#define RAIL_SCHEDULER_SINGLE_TX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SINGLE_TX_SCHEDULING_ERROR)
+#define RAIL_SCHEDULER_SINGLE_TX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SINGLE_TX_INTERRUPTED)
+#define RAIL_SCHEDULER_CCA_CSMA_TX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_CCA_CSMA_TX_INTERNAL_ERROR)
+#define RAIL_SCHEDULER_CCA_CSMA_TX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_CCA_CSMA_TX_SCHEDULING_ERROR)
+#define RAIL_SCHEDULER_CCA_CSMA_TX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_CCA_CSMA_TX_INTERRUPTED)
+#define RAIL_SCHEDULER_CCA_LBT_TX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_CCA_LBT_TX_INTERNAL_ERROR)
+#define RAIL_SCHEDULER_CCA_LBT_TX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_CCA_LBT_TX_SCHEDULING_ERROR)
+#define RAIL_SCHEDULER_CCA_LBT_TX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_CCA_LBT_TX_INTERRUPTED)
+#define RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_INTERNAL_ERROR)
+#define RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_FAIL)
+#define RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_SCHEDULING_ERROR)
+#define RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_INTERRUPTED)
+#define RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_INTERNAL_ERROR)
+#define RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_FAIL)
+#define RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_SCHEDULING_ERROR)
+#define RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_INTERRUPTED)
+#define RAIL_SCHEDULER_TX_STREAM_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TX_STREAM_INTERNAL_ERROR)
+#define RAIL_SCHEDULER_TX_STREAM_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TX_STREAM_SCHEDULING_ERROR)
+#define RAIL_SCHEDULER_TX_STREAM_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TX_STREAM_INTERRUPTED)
+#define RAIL_SCHEDULER_AVERAGE_RSSI_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_AVERAGE_RSSI_INTERNAL_ERROR)
+#define RAIL_SCHEDULER_AVERAGE_RSSI_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_AVERAGE_RSSI_SCHEDULING_ERROR)
+#define RAIL_SCHEDULER_AVERAGE_RSSI_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_AVERAGE_RSSI_INTERRUPTED)
#endif//DOXYGEN_SHOULD_SKIP_THIS
/**
@@ -575,11 +783,15 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) {
RAIL_EVENT_RX_DUTY_CYCLE_RX_END_SHIFT = RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE_SHIFT,
/** Shift position of \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND bit */
RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND_SHIFT,
- /** Shift position of \ref RAIL_EVENT_ZWAVE_BEAM bit */
- RAIL_EVENT_ZWAVE_BEAM_SHIFT = RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND_SHIFT,
-
+ /** Shift position of \ref RAIL_EVENT_ZWAVE_LR_ACK_REQUEST_COMMAND_SHIFT bit */
+ RAIL_EVENT_ZWAVE_LR_ACK_REQUEST_COMMAND_SHIFT = RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND_SHIFT,
// TX Event Bit Shifts
+ /** Shift position of \ref RAIL_EVENT_MFM_TX_BUFFER_DONE bit */
+ RAIL_EVENT_MFM_TX_BUFFER_DONE_SHIFT = RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_ZWAVE_BEAM bit */
+ RAIL_EVENT_ZWAVE_BEAM_SHIFT,
+
/** Shift position of \ref RAIL_EVENT_TX_FIFO_ALMOST_EMPTY bit */
RAIL_EVENT_TX_FIFO_ALMOST_EMPTY_SHIFT,
/** Shift position of \ref RAIL_EVENT_TX_PACKET_SENT bit */
@@ -624,6 +836,18 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) {
/** Shift position of \ref RAIL_EVENT_CAL_NEEDED bit */
RAIL_EVENT_CAL_NEEDED_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_RF_SENSED bit */
+ RAIL_EVENT_RF_SENSED_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_PA_PROTECTION bit */
+ RAIL_EVENT_PA_PROTECTION_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_SIGNAL_DETECTED bit */
+ RAIL_EVENT_SIGNAL_DETECTED_SHIFT,
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+ /** Shift position of \ref RAIL_EVENT_IEEE802154_MODESWITCH_START bit */
+ RAIL_EVENT_IEEE802154_MODESWITCH_START_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_IEEE802154_MODESWITCH_END bit */
+ RAIL_EVENT_IEEE802154_MODESWITCH_END_SHIFT,
+#endif//DOXYGEN_SHOULD_SKIP_THIS
};
// RAIL_Event_t bitmasks
@@ -725,7 +949,8 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) {
#define RAIL_EVENT_RX_FRAME_ERROR (1ULL << RAIL_EVENT_RX_FRAME_ERROR_SHIFT)
/**
- * Occurs coincident to a receive packet completion event in which the
+ * When using \ref RAIL_RxDataSource_t::RX_PACKET_DATA this event
+ * occurs coincident to a receive packet completion event in which the
* receive FIFO or any supplemental packet metadata FIFO (see \ref
* Data_Management) are full and further packet reception is jeopardized.
*
@@ -734,11 +959,18 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) {
* as possible. This event may may be posted multiple times with subsequent
* receive completion events if the FIFO(s) remain full, and should also
* occur coincident with \ref RAIL_EVENT_RX_FIFO_OVERFLOW.
+ *
+ * When not using \ref RAIL_RxDataSource_t::RX_PACKET_DATA this event
+ * is not tied to packet completion and will occur coincident with
+ * \ref RAIL_EVENT_RX_FIFO_OVERFLOW when the receive FIFO has filled and
+ * overflowed. The application should consume receive FIFO data via
+ * \ref RAIL_ReadRxFifo() as soon as possible to minimize lost raw data.
*/
#define RAIL_EVENT_RX_FIFO_FULL (1ULL << RAIL_EVENT_RX_FIFO_FULL_SHIFT)
/**
- * Occurs when a receive is aborted with \ref RAIL_RX_PACKET_ABORT_OVERFLOW
+ * When using \ref RAIL_RxDataSource_t::RX_PACKET_DATA this event
+ * occurs when a receive is aborted with \ref RAIL_RX_PACKET_ABORT_OVERFLOW
* due to overflowing the receive FIFO or any supplemental packet metadata
* FIFO (see \ref Data_Management).
*
@@ -746,6 +978,12 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) {
* the receive FIFO(s) have been fully processed (drained and released
* or reset). It is not guaranteed that a \ref RAIL_EVENT_RX_FIFO_FULL
* will precede this event, but both events should be coincident.
+ *
+ * When not using \ref RAIL_RxDataSource_t::RX_PACKET_DATA this event
+ * is not tied to packet completion and will occur coincident with
+ * \ref RAIL_EVENT_RX_FIFO_FULL when the receive FIFO has filled and
+ * overflowed. The application should consume receive FIFO data via
+ * \ref RAIL_ReadRxFifo() as soon as possible to minimize lost raw data.
*/
#define RAIL_EVENT_RX_FIFO_OVERFLOW (1ULL << RAIL_EVENT_RX_FIFO_OVERFLOW_SHIFT)
@@ -909,6 +1147,27 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) {
*/
#define RAIL_EVENT_ZWAVE_BEAM (1ULL << RAIL_EVENT_ZWAVE_BEAM_SHIFT)
+/**
+ * Indicate a MFM buffer has completely transmitted.
+ *
+ * This event only occurs if the RAIL MFM functionality is enabled
+ * and a MFM buffer has completely transmitted.
+ *
+ * Following this event, the application can update the MFM buffer
+ * that has transmitted to be used for the next transmission.
+ */
+#define RAIL_EVENT_MFM_TX_BUFFER_DONE (1ULL << RAIL_EVENT_MFM_TX_BUFFER_DONE_SHIFT)
+
+/**
+ * Indicate a request for populating Z-Wave LR ACK packet.
+ * This event only occurs if the RAIL Z-Wave functionality is enabled.
+ *
+ * Following this event, the application must call \ref RAIL_ZWAVE_SetLrAckData()
+ * to populate noise floor, TX power and receive rssi fields of the Z-Wave
+ * Long Range ACK packet.
+ */
+#define RAIL_EVENT_ZWAVE_LR_ACK_REQUEST_COMMAND (1ULL << RAIL_EVENT_ZWAVE_LR_ACK_REQUEST_COMMAND_SHIFT)
+
/**
* The mask representing all events that determine the end of a received
* packet.
@@ -972,7 +1231,7 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) {
* This can happen due to calling RAIL_Idle() or due to a scheduler
* preemption.
*
- * @note The TX FIFO is left in an indeterminate state and should be
+ * @note The Transmit FIFO is left in an indeterminate state and should be
* reset prior to reuse for sending a new packet. Contrast this
* with \ref RAIL_EVENT_TX_BLOCKED.
*/
@@ -991,9 +1250,9 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) {
* Occurs when a transmit is blocked from occurring because
* RAIL_EnableTxHoldOff() was called.
*
- * @note Since the transmit never started, the TX FIFO remains intact after
- * this event -- no packet data was consumed from it. Contrast this with
- * \ref RAIL_EVENT_TX_ABORTED.
+ * @note Since the transmit never started, the Transmit FIFO remains intact
+ * after this event -- no packet data was consumed from it. Contrast this
+ * with \ref RAIL_EVENT_TX_ABORTED.
*/
#define RAIL_EVENT_TX_BLOCKED (1ULL << RAIL_EVENT_TX_BLOCKED_SHIFT)
@@ -1012,6 +1271,10 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) {
* transmitted packet specifying an unintended length based on the current
* radio configuration or due to RAIL_WriteTxFifo() calls not keeping up with
* the transmit rate if the entire packet isn't loaded at once.
+ *
+ * @note The Transmit FIFO is left in an indeterminate state and should be
+ * reset prior to reuse for sending a new packet. Contrast this
+ * with \ref RAIL_EVENT_TX_BLOCKED.
*/
#define RAIL_EVENT_TX_UNDERFLOW (1ULL << RAIL_EVENT_TX_UNDERFLOW_SHIFT)
@@ -1043,8 +1306,8 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) {
* This event can only happen after calling RAIL_StartCcaCsmaTx() or
* RAIL_StartCcaLbtTx().
*
- * @note Since the transmit never started, the TX FIFO remains intact after
- * this event -- no packet data was consumed from it.
+ * @note Since the transmit never started, the Transmit FIFO remains intact
+ * after this event -- no packet data was consumed from it.
*/
#define RAIL_EVENT_TX_CHANNEL_BUSY (1ULL << RAIL_EVENT_TX_CHANNEL_BUSY_SHIFT)
@@ -1093,6 +1356,9 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) {
*
* This can occur if the radio is put to sleep and not woken up with enough time
* to configure the scheduled transmit event.
+ *
+ * @note Since the transmit never started, the Transmit FIFO remains intact
+ * after this event -- no packet data was consumed from it.
*/
#define RAIL_EVENT_TX_SCHEDULED_TX_MISSED (1ULL << RAIL_EVENT_TX_SCHEDULED_TX_MISSED_SHIFT)
@@ -1137,7 +1403,7 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) {
* This event will occur in dynamic multiprotocol scenarios each
* time a protocol is shutting down. When it does occur, it will be
* the only event passed to RAIL_Config_t::eventsCallback. Therefore,
- * in order to optimize protocol switch time, this event should be handled
+ * to optimize protocol switch time, this event should be handled
* among the first in that callback, and then the application can return
* immediately.
*
@@ -1166,7 +1432,7 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) {
* The exact status can be found with RAIL_GetSchedulerStatus().
* See \ref RAIL_SchedulerStatus_t for more details. When this event
* does occur, it will be the only event passed to RAIL_Config_t::eventsCallback.
- * Therefore in order to optimize protocol switch time, this event should
+ * Therefore, to optimize protocol switch time, this event should
* be handled among the first in that callback, and then the application
* can return immediately.
*
@@ -1188,6 +1454,45 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) {
*/
#define RAIL_EVENT_CAL_NEEDED (1ULL << RAIL_EVENT_CAL_NEEDED_SHIFT)
+/**
+ * Occurs when RF energy is sensed from the radio. This event can be used as
+ * an alternative to the callback passed as \ref RAIL_RfSense_CallbackPtr_t.
+ *
+ * Alternatively, the application can poll using \ref RAIL_IsRfSensed().
+ *
+ * @note This event will not occur when waking up from EM4. Prefer
+ * \ref RAIL_IsRfSensed() when waking from EM4.
+ */
+#define RAIL_EVENT_RF_SENSED (1ULL << RAIL_EVENT_RF_SENSED_SHIFT)
+
+/**
+ * Occurs when PA protection circuit kicks in.
+ */
+#define RAIL_EVENT_PA_PROTECTION (1ULL << RAIL_EVENT_PA_PROTECTION_SHIFT)
+
+/**
+ * Occurs after enabling the signal identifier using \ref RAIL_BLE_EnableSignalIdentifier
+ * or \ref RAIL_IEEE802154_EnableSignalIdentifier when a signal is detected.
+ * This is only used on platforms that support signal identifer, where
+ * RAIL_BLE_SUPPORTS_SIGNAL_IDENTIFIER or RAIL_IEEE802154_SUPPORTS_SIGNAL_IDENTIFIER
+ * is true.
+ */
+#define RAIL_EVENT_SIGNAL_DETECTED (1ULL << RAIL_EVENT_SIGNAL_DETECTED_SHIFT)
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+/**
+ * Occurs at the beginning of Wi-SUN's mode switch process, i.e. after the switch to
+ * the new channel has been performed. Applies to RX node that receives the mode switch packet.
+ */
+#define RAIL_EVENT_IEEE802154_MODESWITCH_START (1ULL << RAIL_EVENT_IEEE802154_MODESWITCH_START_SHIFT)
+
+/**
+ * Occurs at the end of the mode switch process, i.e. after the second switch back
+ * to the base channel has been performed. Applies to RX node that receives the mode switch packet.
+ */
+#define RAIL_EVENT_IEEE802154_MODESWITCH_END (1ULL << RAIL_EVENT_IEEE802154_MODESWITCH_END_SHIFT)
+#endif//DOXYGEN_SHOULD_SKIP_THIS
+
/** A value representing all possible events */
#define RAIL_EVENTS_ALL 0xFFFFFFFFFFFFFFFFULL
@@ -1214,7 +1519,7 @@ typedef int16_t RAIL_TxPower_t;
/** The maximum power in deci-dBm the curve supports */
#define RAIL_TX_POWER_CURVE_DEFAULT_MAX ((RAIL_TxPower_t)200)
-/** The increment step in deci-dBm for calculating powerlevel*/
+/** The increment step in deci-dBm for calculating power level*/
#define RAIL_TX_POWER_CURVE_DEFAULT_INCREMENT ((RAIL_TxPower_t)40)
/// mV are used for all TX power voltage values.
@@ -1287,10 +1592,33 @@ typedef struct RAIL_FrameType {
* @brief A channel configuration entry attribute structure. Items listed
* are designed to be altered and updated during run-time.
*/
-typedef struct RAIL_ChannelConfigEntryAttr {
- uint32_t calValues[1]; /**< Attributes specific to each channel configuration
- entry. */
-} RAIL_ChannelConfigEntryAttr_t;
+typedef struct RAIL_ChannelConfigEntryAttr RAIL_ChannelConfigEntryAttr_t;
+
+/**
+ * @enum RAIL_ChannelConfigEntryType_t
+ * @brief Define if the channel support using concurrent PHY during channel
+ * hopping. RAIL_RX_CHANNEL_HOPPING_MODE_CONC and RAIL_RX_CHANNEL_HOPPING_MODE_VT
+ * can only be used if the channel supports it.
+ */
+RAIL_ENUM(RAIL_ChannelConfigEntryType_t) {
+ RAIL_CH_TYPE_NORMAL, /**< Not a concurrent PHY. */
+ RAIL_CH_TYPE_CONC_BASE, /**< Base concurrent PHY. */
+ RAIL_CH_TYPE_CONC_VIRTUAL, /**< Virtual concurrent PHY. */
+};
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+// Self-referencing defines minimize compiler complaints when using RAIL_ENUM
+#define RAIL_CH_TYPE_NORMAL ((RAIL_ChannelConfigEntryType_t) RAIL_CH_TYPE_NORMAL)
+#define RAIL_CH_TYPE_CONC_BASE ((RAIL_ChannelConfigEntryType_t) RAIL_CH_TYPE_CONC_BASE)
+#define RAIL_CH_TYPE_CONC_VIRTUAL ((RAIL_ChannelConfigEntryType_t) RAIL_CH_TYPE_CONC_VIRTUAL)
+#endif//DOXYGEN_SHOULD_SKIP_THIS
+
+/**
+ * @def RADIO_CONFIG_ENABLE_CONC_PHY
+ * @brief Indicates this version of RAIL supports concurrent PHY information in
+ * radio configurator output. Needed for backwards compatibility.
+ */
+#define RADIO_CONFIG_ENABLE_CONC_PHY 1
/**
* @struct RAIL_ChannelConfigEntry_t
@@ -1319,6 +1647,8 @@ typedef struct RAIL_ChannelConfigEntry {
RAIL_ChannelConfigEntryAttr_t *attr; /**< A pointer to a structure containing
attributes specific to this
channel set. */
+ RAIL_ChannelConfigEntryType_t entryType; /**< Indicates channel config type. */
+ uint8_t reserved[3]; /**< to align to 32-bit boundary. */
} RAIL_ChannelConfigEntry_t;
/// @struct RAIL_ChannelConfig_t
@@ -1558,6 +1888,7 @@ typedef struct RAIL_ChannelMetadata {
*/
typedef void (*RAIL_RadioConfigChangedCallback_t)(RAIL_Handle_t railHandle,
const RAIL_ChannelConfigEntry_t *entry);
+
/** @} */ // end of group Radio_Configuration
/******************************************************************************
@@ -1579,6 +1910,8 @@ RAIL_ENUM(RAIL_PtiProtocol_t) {
RAIL_PTI_PROTOCOL_CONNECT = 4, /**< PTI output for the Connect protocol. */
RAIL_PTI_PROTOCOL_ZIGBEE = 5, /**< PTI output for the Zigbee protocol. */
RAIL_PTI_PROTOCOL_ZWAVE = 6, /**< PTI output for the Z-Wave protocol. */
+ RAIL_PTI_PROTOCOL_WISUN = 7, /**< PTI output for the Wi-SUN protocol. */
+ RAIL_PTI_PROTOCOL_802154 = 8, /**< PTI output for a custom protocol using a built-in 802.15.4 radio config. */
};
#ifndef DOXYGEN_SHOULD_SKIP_THIS
@@ -1589,6 +1922,7 @@ RAIL_ENUM(RAIL_PtiProtocol_t) {
#define RAIL_PTI_PROTOCOL_CONNECT ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_CONNECT)
#define RAIL_PTI_PROTOCOL_ZIGBEE ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_ZIGBEE)
#define RAIL_PTI_PROTOCOL_ZWAVE ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_ZWAVE)
+#define RAIL_PTI_PROTOCOL_802154 ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_802154)
#endif//DOXYGEN_SHOULD_SKIP_THIS
/** @} */ // end of group PTI
@@ -1607,16 +1941,30 @@ RAIL_ENUM(RAIL_PtiProtocol_t) {
*/
RAIL_ENUM(RAIL_TxDataSource_t) {
TX_PACKET_DATA, /**< Uses the frame hardware to packetize data. */
+ /** Uses the multi-level frequency modulation data.
+ * @note This is only supported on devices where \ref RAIL_SUPPORTS_MFM
+ * or \ref RAIL_SupportsMfm() are true.
+ * @note This feature cannot be used with built-in protocols (802.15.4, BLE,
+ * Z-Wave).
+ */
+ TX_MFM_DATA,
+ /** A count of the choices in this enumeration. */
+ RAIL_TX_DATA_SOURCE_COUNT // Must be last
};
#ifndef DOXYGEN_SHOULD_SKIP_THIS
// Self-referencing defines minimize compiler complaints when using RAIL_ENUM
-#define TX_PACKET_DATA ((RAIL_TxDataSource_t) TX_PACKET_DATA)
+#define TX_PACKET_DATA ((RAIL_TxDataSource_t) TX_PACKET_DATA)
+#define TX_MFM_DATA ((RAIL_TxDataSource_t) TX_MFM_DATA)
+#define RAIL_TX_DATA_SOURCE_COUNT ((RAIL_TxDataSource_t) RAIL_TX_DATA_SOURCE_COUNT)
#endif//DOXYGEN_SHOULD_SKIP_THIS
/**
* @enum RAIL_RxDataSource_t
* @brief Receive data sources supported by RAIL.
+ *
+ * @note Data sources other than \ref RX_PACKET_DATA require use of
+ * \ref RAIL_DataMethod_t::FIFO_MODE.
*/
RAIL_ENUM(RAIL_RxDataSource_t) {
RX_PACKET_DATA, /**< Uses the frame hardware to packetize data. */
@@ -1625,14 +1973,22 @@ RAIL_ENUM(RAIL_RxDataSource_t) {
demodulator. */
RX_IQDATA_FILTMSB, /**< Gets highest 16 bits of I/Q data provided to the
demodulator. */
+ RX_DIRECT_MODE_DATA, /**< Gets RX direct mode data output from the demodulator.
+ Only supported if
+ \ref RAIL_SUPPORTS_RX_DIRECT_MODE_DATA_TO_FIFO
+ is true. */
+ /** A count of the choices in this enumeration. */
+ RAIL_RX_DATA_SOURCE_COUNT // Must be last
};
#ifndef DOXYGEN_SHOULD_SKIP_THIS
// Self-referencing defines minimize compiler complaints when using RAIL_ENUM
-#define RX_PACKET_DATA ((RAIL_RxDataSource_t) RX_PACKET_DATA)
-#define RX_DEMOD_DATA ((RAIL_RxDataSource_t) RX_DEMOD_DATA)
-#define RX_IQDATA_FILTLSB ((RAIL_RxDataSource_t) RX_IQDATA_FILTLSB)
-#define RX_IQDATA_FILTMSB ((RAIL_RxDataSource_t) RX_IQDATA_FILTMSB)
+#define RX_PACKET_DATA ((RAIL_RxDataSource_t) RX_PACKET_DATA)
+#define RX_DEMOD_DATA ((RAIL_RxDataSource_t) RX_DEMOD_DATA)
+#define RX_IQDATA_FILTLSB ((RAIL_RxDataSource_t) RX_IQDATA_FILTLSB)
+#define RX_IQDATA_FILTMSB ((RAIL_RxDataSource_t) RX_IQDATA_FILTMSB)
+#define RX_DIRECT_MODE_DATA ((RAIL_RxDataSource_t) RX_DIRECT_MODE_DATA)
+#define RAIL_RX_DATA_SOURCE_COUNT ((RAIL_RxDataSource_t) RAIL_RX_DATA_SOURCE_COUNT)
#endif//DOXYGEN_SHOULD_SKIP_THIS
/**
@@ -1655,12 +2011,15 @@ RAIL_ENUM(RAIL_RxDataSource_t) {
RAIL_ENUM(RAIL_DataMethod_t) {
PACKET_MODE, /**< Packet-based data method. */
FIFO_MODE, /**< FIFO-based data method. */
+ /** A count of the choices in this enumeration. */
+ RAIL_DATA_METHOD_COUNT // Must be last
};
#ifndef DOXYGEN_SHOULD_SKIP_THIS
// Self-referencing defines minimize compiler complaints when using RAIL_ENUM
-#define PACKET_MODE ((RAIL_DataMethod_t) PACKET_MODE)
-#define FIFO_MODE ((RAIL_DataMethod_t) FIFO_MODE)
+#define PACKET_MODE ((RAIL_DataMethod_t) PACKET_MODE)
+#define FIFO_MODE ((RAIL_DataMethod_t) FIFO_MODE)
+#define RAIL_DATA_METHOD_COUNT ((RAIL_DataMethod_t) RAIL_DATA_METHOD_COUNT)
#endif//DOXYGEN_SHOULD_SKIP_THIS
/**
@@ -1738,49 +2097,68 @@ typedef struct RAIL_StateTransitions {
} RAIL_StateTransitions_t;
/**
- * @def RAIL_MINIMUM_TRANSITION_US
- * @brief The minimum value for a consistent RAIL transition
- * @note Transitions may need to be slower than this when using longer
- * \ref RAIL_TxPowerConfig_t::rampTime values
- */
-#define RAIL_MINIMUM_TRANSITION_US (100U)
-
-/**
- * @def RAIL_MAXIMUM_TRANSITION_US
- * @brief The maximum value for a consistent RAIL transition
- */
-#define RAIL_MAXIMUM_TRANSITION_US (13000U)
-
-/**
- * @struct RAIL_StateTiming_t
- * @brief A timing configuration structure for the RAIL State Machine.
- *
- * Configure the timings of the radio state transitions for common situations.
- * All of the listed timings are in us. Transitions from an active radio state
- * to idle are not configurable, and will always happen as fast as possible.
- * All timing values cannot exceed \ref RAIL_MAXIMUM_TRANSITION_US.
+ * @enum RAIL_RadioStateDetail_t
+ * @brief The detailed state of the radio.
*
- * For idleToRx, idleToTx, rxToTx, and txToRx, a value of 0 for the transition
- * time means that the specified transition should happen as fast as possible,
- * even if the timing cannot be as consistent. Otherwise, the timing value
- * cannot be below \ref RAIL_MINIMUM_TRANSITION_US.
+ * The three radio state bits \ref RAIL_RF_STATE_DETAIL_IDLE_STATE, \ref
+ * RAIL_RF_STATE_DETAIL_RX_STATE, and \ref RAIL_RF_STATE_DETAIL_TX_STATE
+ * comprise a set of mutually exclusive core radio states. Only one (or none)
+ * of these bits can be set at a time. Otherwise, the value is invalid.
*
- * For idleToTx and rxToTx, setting a longer \ref RAIL_TxPowerConfig_t::rampTime
- * may result in a larger minimum value.
+ * The precise meaning of each of these three core bits, when set, depends on
+ * the value of the two bits \ref RAIL_RF_STATE_DETAIL_TRANSITION and \ref
+ * RAIL_RF_STATE_DETAIL_ACTIVE. When \ref RAIL_RF_STATE_DETAIL_TRANSITION is
+ * set, the radio is transitioning into the core radio state corresponding
+ * to the set state bit. When it is clear, the radio is already in the core
+ * radio state that corresponds to the set state bit. When \ref
+ * RAIL_RF_STATE_DETAIL_ACTIVE is set, the radio is actively transmitting or
+ * receiving. When it is clear, the radio is not actively transmitting or receiving.
+ * This bit will always be clear when \ref RAIL_RF_STATE_DETAIL_IDLE_STATE is
+ * set, and will always be set when \ref RAIL_RF_STATE_DETAIL_TX_STATE is set.
+ * Otherwise, the value is invalid.
*
- * For rxSearchTimeout and txToRxSearchTimeout, there is no minimum value. A
- * value of 0 disables the feature, functioning as an infinite timeout.
- */
-typedef struct RAIL_StateTiming {
- uint16_t idleToRx; /**< Transition time from IDLE to RX. */
- uint16_t txToRx; /**< Transition time from TX to RX. */
- uint16_t idleToTx; /**< Transition time from IDLE to RX. */
- uint16_t rxToTx; /**< Transition time from RX to TX. */
- uint16_t rxSearchTimeout; /**< Length of time the radio will search for a
- packet when coming from idle. */
- uint16_t txToRxSearchTimeout; /**< Length of time the radio will search for a
- packet when coming from TX. */
-} RAIL_StateTiming_t;
+ * The bit \ref RAIL_RF_STATE_DETAIL_NO_FRAMES is set if the radio is currently
+ * operating with frame detection disabled, and clear otherwise. The bit \ref
+ * RAIL_RF_STATE_DETAIL_LBT_SHIFT is set if an LBT/CSMA operation
+ * (e.g., performing CCA) is currently ongoing, and clear otherwise.
+ */
+RAIL_ENUM(RAIL_RadioStateDetail_t) {
+ /** Shift position of \ref RAIL_RF_STATE_DETAIL_IDLE_STATE bit */
+ RAIL_RF_STATE_DETAIL_IDLE_STATE_SHIFT = 0u,
+ /** Shift position of \ref RAIL_RF_STATE_DETAIL_RX_STATE bit */
+ RAIL_RF_STATE_DETAIL_RX_STATE_SHIFT,
+ /** Shift position of \ref RAIL_RF_STATE_DETAIL_TX_STATE bit */
+ RAIL_RF_STATE_DETAIL_TX_STATE_SHIFT,
+ /** Shift position of \ref RAIL_RF_STATE_DETAIL_TRANSITION bit */
+ RAIL_RF_STATE_DETAIL_TRANSITION_SHIFT,
+ /** Shift position of \ref RAIL_RF_STATE_DETAIL_ACTIVE bit */
+ RAIL_RF_STATE_DETAIL_ACTIVE_SHIFT,
+ /** Shift position of \ref RAIL_RF_STATE_DETAIL_NO_FRAMES bit */
+ RAIL_RF_STATE_DETAIL_NO_FRAMES_SHIFT,
+ /** Shift position of \ref RAIL_RF_STATE_DETAIL_LBT bit */
+ RAIL_RF_STATE_DETAIL_LBT_SHIFT,
+};
+
+/** Radio is inactive. */
+#define RAIL_RF_STATE_DETAIL_INACTIVE (0U)
+/** Radio is in or headed to the idle state. */
+#define RAIL_RF_STATE_DETAIL_IDLE_STATE (1U << RAIL_RF_STATE_DETAIL_IDLE_STATE_SHIFT)
+/** Radio is in or headed to the receive state. */
+#define RAIL_RF_STATE_DETAIL_RX_STATE (1U << RAIL_RF_STATE_DETAIL_RX_STATE_SHIFT)
+/** Radio is in or headed to the transmit state. */
+#define RAIL_RF_STATE_DETAIL_TX_STATE (1U << RAIL_RF_STATE_DETAIL_TX_STATE_SHIFT)
+/** Radio is headed to the idle, receive, or transmit state. */
+#define RAIL_RF_STATE_DETAIL_TRANSITION (1U << RAIL_RF_STATE_DETAIL_TRANSITION_SHIFT)
+/** Radio is actively transmitting or receiving. */
+#define RAIL_RF_STATE_DETAIL_ACTIVE (1U << RAIL_RF_STATE_DETAIL_ACTIVE_SHIFT)
+/** Radio has frame detect disabled. */
+#define RAIL_RF_STATE_DETAIL_NO_FRAMES (1U << RAIL_RF_STATE_DETAIL_NO_FRAMES_SHIFT)
+/** LBT/CSMA operation is currently ongoing. */
+#define RAIL_RF_STATE_DETAIL_LBT (1U << RAIL_RF_STATE_DETAIL_LBT_SHIFT)
+/** Mask for core radio state bits. */
+#define RAIL_RF_STATE_DETAIL_CORE_STATE_MASK (RAIL_RF_STATE_DETAIL_IDLE_STATE \
+ | RAIL_RF_STATE_DETAIL_RX_STATE \
+ | RAIL_RF_STATE_DETAIL_TX_STATE)
/**
* @enum RAIL_IdleMode_t
@@ -1825,6 +2203,90 @@ RAIL_ENUM(RAIL_IdleMode_t) {
/** @} */ // end of group State_Transitions
+/******************************************************************************
+ * TX Channel Hopping
+ *****************************************************************************/
+/**
+ * @addtogroup Tx_Channel_Hopping TX Channel Hopping
+ * @{
+ */
+
+/**
+ * @struct RAIL_TxChannelHoppingConfigEntry_t
+ * @brief Structure that represents one of the channels that is part of a
+ * \ref RAIL_TxChannelHoppingConfig_t sequence of channels used in
+ * channel hopping.
+ */
+typedef struct RAIL_TxChannelHoppingConfigEntry {
+ /**
+ * The channel number to be used for this entry in the channel hopping
+ * sequence. If this is an invalid channel for the current PHY, the
+ * call to \ref RAIL_SetNextTxRepeat() will fail.
+ */
+ uint16_t channel;
+ /**
+ * Pad bytes reserved for future use and currently ignored.
+ */
+ uint8_t reserved[2];
+ /**
+ * Idle time in microseconds to wait before transmitting on the channel
+ * indicated by this entry.
+ */
+ uint32_t delay;
+} RAIL_TxChannelHoppingConfigEntry_t;
+
+/**
+ * @struct RAIL_TxChannelHoppingConfig_t
+ * @brief Wrapper struct that will contain the sequence of
+ * \ref RAIL_TxChannelHoppingConfigEntry_t that represents the channel
+ * sequence to use during TX Channel Hopping.
+ */
+typedef struct RAIL_TxChannelHoppingConfig {
+ /**
+ * Pointer to contiguous global read-write memory that will be used
+ * by RAIL to store channel hopping information throughout its operation.
+ * It need not be initialized and applications should never write
+ * data anywhere in this buffer.
+ *
+ * @note the size of this buffer must be at least as large as
+ * 3 + 30 * numberOfChannels, plus the sum of the sizes of the
+ * radioConfigDeltaAdd's of the required channels, plus the size of the
+ * radioConfigDeltaSubtract. In the case that one channel
+ * appears two or more times in your channel sequence
+ * (e.g., 1, 2, 3, 2), you must account for the radio configuration
+ * size that number of times (i.e., need to count channel 2's
+ * radio configuration size twice for the given example). The overall
+ * 3 words and 30 words per channel needed in this buffer are
+ * for internal use to the library.
+ */
+ uint32_t *buffer;
+ /**
+ * This parameter must be set to the length of the buffer array. This way,
+ * during configuration, the software can confirm it's writing within the
+ * range of the buffer. The configuration API will return an error
+ * if bufferLength is insufficient.
+ */
+ uint16_t bufferLength;
+ /**
+ * The number of channels in the channel hopping sequence, which is the
+ * number of elements in the array that entries points to.
+ */
+ uint8_t numberOfChannels;
+ /**
+ * Pad byte reserved for future use and currently ignored.
+ */
+ uint8_t reserved;
+ /**
+ * A pointer to the first element of an array of \ref
+ * RAIL_TxChannelHoppingConfigEntry_t that represents the channels
+ * used during channel hopping. The length of this array must be
+ * numberOfChannels.
+ */
+ RAIL_TxChannelHoppingConfigEntry_t *entries;
+} RAIL_TxChannelHoppingConfig_t;
+
+/** @} */ // end of group Tx_Channel_Hopping
+
/******************************************************************************
* TX/RX Configuration Structures
*****************************************************************************/
@@ -1874,6 +2336,8 @@ RAIL_ENUM_GENERIC(RAIL_TxOptions_t, uint32_t) {
RAIL_TX_OPTION_CCA_PEAK_RSSI_SHIFT,
/** Shift position of \ref RAIL_TX_OPTION_CCA_ONLY bit */
RAIL_TX_OPTION_CCA_ONLY_SHIFT,
+ /** Shift position of \ref RAIL_TX_OPTION_RESEND bit */
+ RAIL_TX_OPTION_RESEND_SHIFT,
/** A count of the choices in this enumeration. */
RAIL_TX_OPTIONS_COUNT // Must be last
};
@@ -1895,13 +2359,13 @@ RAIL_ENUM_GENERIC(RAIL_TxOptions_t, uint32_t) {
*/
#define RAIL_TX_OPTION_REMOVE_CRC (1UL << RAIL_TX_OPTION_REMOVE_CRC_SHIFT)
/**
- * An option to select which sync word to send (0 or 1). Note that this does
- * not set the actual sync words, it just picks which of the two will be
- * sent with the packet.
- * This setting is valid only if \ref RAIL_RX_OPTION_ENABLE_DUALSYNC is set.
- * Setting to 0 will transmit on SYNC1.
- * Setting to 1 will transmit on SYNC2 if \ref RAIL_RX_OPTION_ENABLE_DUALSYNC
- * is in effect.
+ * An option to select which sync word to send (0 or 1). This does not set the
+ * actual sync words, it just picks which of the two will be sent with the
+ * outgoing packet. Setting to 0 will transmit on SYNC1. Setting to 1 will
+ * transmit on SYNC2.
+ *
+ * @note There are a few special radio configurations (e.g. BLE Viterbi) that do
+ * not support transmitting different sync words.
*/
#define RAIL_TX_OPTION_SYNC_WORD_ID (1UL << RAIL_TX_OPTION_SYNC_WORD_ID_SHIFT)
/**
@@ -1958,6 +2422,23 @@ RAIL_ENUM_GENERIC(RAIL_TxOptions_t, uint32_t) {
*/
#define RAIL_TX_OPTION_CCA_ONLY (1UL << RAIL_TX_OPTION_CCA_ONLY_SHIFT)
+/**
+ * An option to resend packet at the beginning of the Transmit FIFO.
+ *
+ * The packet to be resent must have been previously provided by
+ * \ref RAIL_SetTxFifo() or \ref RAIL_WriteTxFifo() passing true for
+ * the latter's reset parameter. It works by setting the
+ * transmit FIFO's read offset to the beginning of the FIFO while
+ * leaving its write offset intact. For this to work,
+ * \ref RAIL_DataConfig_t::txMethod must be RAIL_DataMethod_t::PACKET_MODE
+ * (i.e., the packet can't exceed the Transmit FIFO's size), otherwise
+ * undefined behavior will result.
+ *
+ * This option can also be used with \ref RAIL_SetNextTxRepeat() to cause
+ * the repeated packet(s) to all be the same as the first.
+ */
+#define RAIL_TX_OPTION_RESEND (1UL << RAIL_TX_OPTION_RESEND_SHIFT)
+
/** A value representing all possible options. */
#define RAIL_TX_OPTIONS_ALL 0xFFFFFFFFUL
@@ -2118,6 +2599,17 @@ typedef struct RAIL_CsmaConfig {
/**
* The minimum (starting) exponent for CSMA random backoff (2^exp - 1).
* It can range from 0 to \ref RAIL_MAX_CSMA_EXPONENT.
+ *
+ * @warning On EFR32, due to a hardware limitation, this can only be 0
+ * if \ref csmaMaxBoExp is also 0 specifying a non-random fixed backoff.
+ * \ref RAIL_STATUS_INVALID_PARAMETER will result otherwise.
+ * If you really want CSMA's first iteration to have no backoff prior to
+ * CCA, with subsequent iterations having random backoff as the exponent
+ * is increased, you must do a fixed backoff of 0 operation first
+ * (\ref csmaMinBoExp = 0, \ref csmaMaxBoExp = 0, \ref ccaBackoff = 0,
+ * \ref csmaTries = 1), and if that fails (\ref RAIL_EVENT_TX_CHANNEL_BUSY),
+ * follow up with a random backoff operation starting at \ref csmaMinBoExp
+ * = 1 for the remaining iterations.
*/
uint8_t csmaMinBoExp;
/**
@@ -2325,6 +2817,101 @@ typedef struct RAIL_SyncWordConfig {
* @{
*/
+/**
+ * @addtogroup Address_Filtering
+ * @{
+ */
+
+/// A default address filtering match table for configurations that use only one
+/// address field. The truth table for address matching is shown below.
+///
+/// | | No Match | Address 0 | Address 1 | Address 2 | Address 3 |
+/// |----------------|----------|-----------|-----------|-----------|-----------|
+/// | __No Match__ | 0 | 1 | 1 | 1 | 1 |
+/// | __Address 0__ | 1 | 1 | 1 | 1 | 1 |
+/// | __Address 1__ | 1 | 1 | 1 | 1 | 1 |
+/// | __Address 2__ | 1 | 1 | 1 | 1 | 1 |
+/// | __Address 3__ | 1 | 1 | 1 | 1 | 1 |
+///
+#define ADDRCONFIG_MATCH_TABLE_SINGLE_FIELD (0x1FFFFFE)
+/// A default address filtering match table for configurations that use two
+/// address fields and want to match the same index in each. The truth
+/// table for address matching is shown below.
+///
+/// | | No Match | Address 0 | Address 1 | Address 2 | Address 3 |
+/// |----------------|----------|-----------|-----------|-----------|-----------|
+/// | __No Match__ | 0 | 0 | 0 | 0 | 0 |
+/// | __Address 0__ | 0 | 1 | 0 | 0 | 0 |
+/// | __Address 1__ | 0 | 0 | 1 | 0 | 0 |
+/// | __Address 2__ | 0 | 0 | 0 | 1 | 0 |
+/// | __Address 3__ | 0 | 0 | 0 | 0 | 1 |
+#define ADDRCONFIG_MATCH_TABLE_DOUBLE_FIELD (0x1041040)
+
+/// The maximum number of address fields that can be used by the address
+/// filtering logic.
+#define ADDRCONFIG_MAX_ADDRESS_FIELDS (2)
+
+/**
+ * @struct RAIL_AddrConfig_t
+ * @brief A structure to configure the address filtering functionality in RAIL.
+ */
+typedef struct RAIL_AddrConfig {
+ /**
+ * A list of the start offsets for each field.
+ *
+ * These offsets are specified relative to the previous field's end.
+ * For the first field, it is relative to either the beginning of the packet
+ * or the end of the frame type byte if frame type decoding is enabled. If a
+ * field is unused, it's offset should be set to 0.
+ */
+ uint8_t offsets[ADDRCONFIG_MAX_ADDRESS_FIELDS];
+
+ /**
+ * A list of the address field sizes.
+ *
+ * These sizes are specified in bytes from 0 to 8. If you choose a
+ * size of 0, this field is effectively disabled.
+ */
+ uint8_t sizes[ADDRCONFIG_MAX_ADDRESS_FIELDS];
+
+ /**
+ * The truth table to determine how the two fields combine to create a match.
+ *
+ * For detailed information about how this truth table is formed, see the
+ * detailed description of \ref Address_Filtering.
+ *
+ * For simple predefined configurations use the following defines.
+ * - ADDRCONFIG_MATCH_TABLE_SINGLE_FIELD
+ * - For filtering that only uses a single address field.
+ * - ADDRCONFIG_MATCH_TABLE_DOUBLE_FIELD for two field filtering where you
+ * - For filtering that uses two address fields in a configurations where
+ * you want the following logic `((Field0, Index0) && (Field1, Index0))
+ * || ((Field0, Index1) && (Field1, Index1)) || ...`
+ */
+ uint32_t matchTable;
+} RAIL_AddrConfig_t;
+
+/**
+ * @brief A bitmask representation of which 4 filters passed for each
+ * \ref ADDRCONFIG_MAX_ADDRESS_FIELDS when filtering has completed
+ * successfully.
+ *
+ * It's layout is:
+ * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
+ * |--------+--------+--------+--------+--------+--------+--------+--------|
+ * | Second Address Field Nibble | First Address Field Nibble |
+ * | Addr 3 | Addr 2 | Addr 1 | Addr 0 | Addr 3 | Addr 2 | Addr 1 | Addr 0 |
+ * | match | match | match | match | match | match | match | match |
+ * |--------+--------+--------+--------+--------+--------+--------+--------|
+ *
+ * @note This information is valid in \ref RAIL_IEEE802154_Address_t on all
+ * platforms, but is only valid in \ref RAIL_RxPacketInfo_t on platforms
+ * where \ref RAIL_SUPPORTS_ADDR_FILTER_MASK is true.
+ */
+typedef uint8_t RAIL_AddrFilterMask_t;
+
+/** @} */ // end of group Address_Filtering
+
/**
* @enum RAIL_RxOptions_t
* @brief Receive options, in reality a bitmask.
@@ -2378,7 +2965,7 @@ RAIL_ENUM_GENERIC(RAIL_RxOptions_t, uint32_t) {
* sync word(s) are received, but not what each of the sync words actually are.
* This feature may not be available on some combinations of chips, PHYs, and
* protocols. Use the compile time symbol RAIL_SUPPORTS_DUAL_SYNC_WORDS or
- * the runtume call RAIL_SupportsDualSyncWords() to check whether the
+ * the runtime call RAIL_SupportsDualSyncWords() to check whether the
* platform supports this feature. Also, DUALSYNC may be incompatible
* with certain radio configurations. In these cases, setting this bit will
* be ignored. See the data sheet or support team for more details.
@@ -2398,6 +2985,11 @@ RAIL_ENUM_GENERIC(RAIL_RxOptions_t, uint32_t) {
* \ref RAIL_RxPacketDetails_t details will not be available for received
* packets whose \ref RAIL_RxPacketStatus_t is among the RAIL_RX_PACKET_READY_
* set.
+ *
+ * @warning This option should be changed only when the radio is idle
+ * and the receive FIFO is empty or has been reset,
+ * otherwise \ref RAIL_GetRxPacketInfo() and \ref RAIL_GetRxPacketDetails()
+ * may think appended info is packet data or vice-versa.
*/
#define RAIL_RX_OPTION_REMOVE_APPENDED_INFO (1UL << RAIL_RX_OPTION_REMOVE_APPENDED_INFO_SHIFT)
@@ -2446,6 +3038,18 @@ RAIL_ENUM_GENERIC(RAIL_RxOptions_t, uint32_t) {
#define RAIL_RSSI_INVALID_DBM (-128)
/** The value returned by RAIL for an invalid RSSI: in quarter dBm. */
#define RAIL_RSSI_INVALID ((int16_t)(RAIL_RSSI_INVALID_DBM * 4))
+/** The lowest RSSI value returned by RAIL: in quarter dBm. */
+#define RAIL_RSSI_LOWEST ((int16_t)(RAIL_RSSI_INVALID + 1))
+/** The highest RSSI value returned by RAIL: in quarter dBm. */
+#define RAIL_RSSI_HIGHEST ((int16_t)((-RAIL_RSSI_INVALID_DBM - 1) * 4))
+
+/** Maximum absolute value for RSSI offset */
+#define RAIL_RSSI_OFFSET_MAX 35
+
+/** A sentinel value to indicate waiting for a valid RSSI without a timeout. */
+#define RAIL_GET_RSSI_WAIT_WITHOUT_TIMEOUT ((RAIL_Time_t)0xFFFFFFFFU)
+/** A sentinel value to indicate no waiting for a valid RSSI. */
+#define RAIL_GET_RSSI_NO_WAIT ((RAIL_Time_t)0U)
/**
* @struct RAIL_ScheduleRxConfig_t
@@ -2480,8 +3084,8 @@ typedef struct RAIL_ScheduleRxConfig {
* this API, if you specify a \ref RAIL_TIME_DELAY, it is relative to the
* start time if given and relative to now if none is specified. Also, using
* \ref RAIL_TIME_DISABLED means that this window will not end unless you
- * explicitly call RAIL_RfIdle() or add an end event through a future update
- * to this configuration.
+ * explicitly call \ref RAIL_Idle() or add an end event through a future
+ * update to this configuration.
*/
RAIL_TimeMode_t endMode;
/**
@@ -2666,6 +3270,13 @@ typedef struct RAIL_RxPacketInfo {
packet, if any; NULL otherwise. The
number of bytes in this portion is
packetBytes - firstPortionBytes. */
+ RAIL_AddrFilterMask_t filterMask; /**< A bitmask representing which address
+ filter(s) this packet has passed.
+ Will be 0 when not filtering or if
+ packet info is retrieved before
+ filtering has completed. It's
+ undefined on platforms lacking \ref
+ RAIL_SUPPORTS_ADDR_FILTER_MASK */
} RAIL_RxPacketInfo_t;
/**
@@ -2746,7 +3357,20 @@ typedef struct RAIL_RxPacketDetails {
* In configurations where the radio has the option of receiving a given
* packet in multiple ways, indicates which of the sub-PHY options
* was used to receive the packet. Most radio configurations do not have
- * this ability and the subPhy is set to 0.
+ * this ability and the subPhyId is set to 0.
+ *
+ * Currently, this field is used by the BLE Coded PHY, the BLE Simulscan PHY
+ * and the SUN OFDM PHYs.
+ * In BLE cases, a value of 0 marks a 500 kbps packet, a value of 1 marks a 125
+ * kbps packet, and a value of 2 marks a 1 Mbps packet.
+ * Also, see \ref RAIL_BLE_ConfigPhyCoded and \ref RAIL_BLE_ConfigPhySimulscan.
+ *
+ * In SUN OFDM cases, the value corresponds to the numerical value of the
+ * Modulation and Coding Scheme (MCS) level of the last received packet.
+ * The packet bitrate depends on the MCS value, as well as the OFDM option.
+ * Packets bitrates for SUN OFDM PHYs can be found in 802.15.4-2020 specification,
+ * chapter 20.3, table 20-10.
+ * Ex: Packet bitrate for OFDM option 1 MCS0 is 100kb/s and 2400kb/s for MCS6.
*
* It is always available.
*/
@@ -2771,82 +3395,6 @@ typedef struct RAIL_RxPacketDetails {
uint8_t channelHoppingChannelIndex;
} RAIL_RxPacketDetails_t;
-/**
- * @addtogroup Address_Filtering
- * @{
- */
-
-/// A default address filtering match table for configurations that use only one
-/// address field. The truth table for address matching is shown below.
-///
-/// | | No Match | Address 0 | Address 1 | Address 2 | Address 3 |
-/// |----------------|----------|-----------|-----------|-----------|-----------|
-/// | __No Match__ | 0 | 1 | 1 | 1 | 1 |
-/// | __Address 0__ | 1 | 1 | 1 | 1 | 1 |
-/// | __Address 1__ | 1 | 1 | 1 | 1 | 1 |
-/// | __Address 2__ | 1 | 1 | 1 | 1 | 1 |
-/// | __Address 3__ | 1 | 1 | 1 | 1 | 1 |
-///
-#define ADDRCONFIG_MATCH_TABLE_SINGLE_FIELD (0x1FFFFFE)
-/// A default address filtering match table for configurations that use two
-/// address fields and want to match the same index in each. The truth
-/// table for address matching is shown below.
-///
-/// | | No Match | Address 0 | Address 1 | Address 2 | Address 3 |
-/// |----------------|----------|-----------|-----------|-----------|-----------|
-/// | __No Match__ | 0 | 0 | 0 | 0 | 0 |
-/// | __Address 0__ | 0 | 1 | 0 | 0 | 0 |
-/// | __Address 1__ | 0 | 0 | 1 | 0 | 0 |
-/// | __Address 2__ | 0 | 0 | 0 | 1 | 0 |
-/// | __Address 3__ | 0 | 0 | 0 | 0 | 1 |
-#define ADDRCONFIG_MATCH_TABLE_DOUBLE_FIELD (0x1041040)
-
-/// The maximum number of address fields that can be used by the address
-/// filtering logic.
-#define ADDRCONFIG_MAX_ADDRESS_FIELDS (2)
-
-/**
- * @struct RAIL_AddrConfig_t
- * @brief A structure to configure the address filtering functionality in RAIL.
- */
-typedef struct RAIL_AddrConfig {
- /**
- * A list of the start offsets for each field.
- *
- * These offsets are specified relative to the previous field's end.
- * For the first field, it is relative to either the beginning of the packet
- * or the end of the frame type byte if frame type decoding is enabled. If a
- * field is unused, it's offset should be set to 0.
- */
- uint8_t offsets[ADDRCONFIG_MAX_ADDRESS_FIELDS];
-
- /**
- * A list of the address field sizes.
- *
- * These sizes are specified in bytes from 0 to 8. If you choose a
- * size of 0, this field is effectively disabled.
- */
- uint8_t sizes[ADDRCONFIG_MAX_ADDRESS_FIELDS];
-
- /**
- * The truth table to determine how the two fields combine to create a match.
- *
- * For detailed information about how this truth table is formed, see the
- * detailed description of \ref Address_Filtering.
- *
- * For simple predefined configurations use the following defines.
- * - ADDRCONFIG_MATCH_TABLE_SINGLE_FIELD
- * - For filtering that only uses a single address field.
- * - ADDRCONFIG_MATCH_TABLE_DOUBLE_FIELD for two field filtering where you
- * - For filtering that uses two address fields in a configurations where
- * you want the following logic `((Field0, Index0) && (Field1, Index0))
- * || ((Field0, Index1) && (Field1, Index1)) || ...`
- */
- uint32_t matchTable;
-} RAIL_AddrConfig_t;
-
-/** @} */ // end of group Address_Filtering
-
/** @} */ // end of group Receive
/**
@@ -2976,6 +3524,8 @@ typedef uint8_t (*RAIL_ConvertLqiCallback_t)(uint8_t lqi,
/**
* A pointer to an RF Sense callback function.
+ *
+ * Consider using the event \ref RAIL_EVENT_RF_SENSED as an alternative.
*/
typedef void (*RAIL_RfSense_CallbackPtr_t)(void);
@@ -3118,7 +3668,31 @@ RAIL_ENUM(RAIL_RxChannelHoppingMode_t) {
* \ref RAIL_RxChannelHoppingConfigEntry_t that uses this mode.
*/
RAIL_RX_CHANNEL_HOPPING_MODE_MULTI_SENSE,
-
+ /**
+ * Switch to the next channel based on the demodulation settings in the PHY
+ * config. This mode is PHY and chip dependent. The
+ * \ref RAIL_RxChannelHoppingConfigEntry_t::parameter is ignored, and should
+ * be set to 0 for future compatibility.
+ */
+ RAIL_RX_CHANNEL_HOPPING_MODE_SQ,
+ /**
+ * Marks that the channel is concurrent with another channel, and otherwise
+ * behaves identically to \ref RAIL_RX_CHANNEL_HOPPING_MODE_SQ.
+ */
+ RAIL_RX_CHANNEL_HOPPING_MODE_CONC,
+ /**
+ * Indicates that this channel is a virtual channel that is concurrently
+ * detected with the channel indicated by the
+ * \ref RAIL_RxChannelHoppingConfigEntry_t::parameter. Otherwise behaves
+ * identically to \ref RAIL_RX_CHANNEL_HOPPING_MODE_SQ.
+ */
+ RAIL_RX_CHANNEL_HOPPING_MODE_VT,
+ /**
+ * This is the transmit channel used for auto-ACK if the regular channel,
+ * specified in RAIL_RxChannelHoppingConfigEntry::parameter, is
+ * optimized for RX which may degrade some TX performance
+ */
+ RAIL_RX_CHANNEL_HOPPING_MODE_TX,
/**
* A count of the basic choices in this enumeration.
*/
@@ -3144,6 +3718,14 @@ RAIL_ENUM(RAIL_RxChannelHoppingMode_t) {
RAIL_RX_CHANNEL_HOPPING_MODE_RESERVED1_WITH_OPTIONS,
/** Variant of \ref RAIL_RX_CHANNEL_HOPPING_MODE_MULTI_SENSE with options. */
RAIL_RX_CHANNEL_HOPPING_MODE_MULTI_SENSE_WITH_OPTIONS,
+ /** Variant of \ref RAIL_RX_CHANNEL_HOPPING_MODE_SQ with options. */
+ RAIL_RX_CHANNEL_HOPPING_MODE_SQ_WITH_OPTIONS,
+ /** Variant of \ref RAIL_RX_CHANNEL_HOPPING_MODE_CONC with options. */
+ RAIL_RX_CHANNEL_HOPPING_MODE_CONC_WITH_OPTIONS,
+ /** Variant of \ref RAIL_RX_CHANNEL_HOPPING_MODE_VT with options. */
+ RAIL_RX_CHANNEL_HOPPING_MODE_VT_WITH_OPTIONS,
+ /** Variant of \ref RAIL_RX_CHANNEL_HOPPING_MODE_TX with options. */
+ RAIL_RX_CHANNEL_HOPPING_MODE_TX_WITH_OPTIONS,
};
#ifndef DOXYGEN_SHOULD_SKIP_THIS
@@ -3154,6 +3736,10 @@ RAIL_ENUM(RAIL_RxChannelHoppingMode_t) {
#define RAIL_RX_CHANNEL_HOPPING_MODE_PREAMBLE_SENSE ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_PREAMBLE_SENSE)
#define RAIL_RX_CHANNEL_HOPPING_MODE_RESERVED1 ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_RESERVED1)
#define RAIL_RX_CHANNEL_HOPPING_MODE_MULTI_SENSE ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_MULTI_SENSE)
+#define RAIL_RX_CHANNEL_HOPPING_MODE_SQ ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_SQ)
+#define RAIL_RX_CHANNEL_HOPPING_MODE_CONC ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_CONC)
+#define RAIL_RX_CHANNEL_HOPPING_MODE_VT ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_VT)
+#define RAIL_RX_CHANNEL_HOPPING_MODE_TX ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_TX)
#define RAIL_RX_CHANNEL_HOPPING_MODES_WITH_OPTIONS_BASE ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODES_WITH_OPTIONS_BASE)
#define RAIL_RX_CHANNEL_HOPPING_MODE_MANUAL_WITH_OPTIONS ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_MANUAL_WITH_OPTIONS)
#define RAIL_RX_CHANNEL_HOPPING_MODE_TIMEOUT_WITH_OPTIONS ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_TIMEOUT_WITH_OPTIONS)
@@ -3161,6 +3747,10 @@ RAIL_ENUM(RAIL_RxChannelHoppingMode_t) {
#define RAIL_RX_CHANNEL_HOPPING_MODE_PREAMBLE_SENSE_WITH_OPTIONS ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_PREAMBLE_SENSE_WITH_OPTIONS)
#define RAIL_RX_CHANNEL_HOPPING_MODE_RESERVED1_WITH_OPTIONS ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_RESERVED1_WITH_OPTIONS)
#define RAIL_RX_CHANNEL_HOPPING_MODE_MULTI_SENSE_WITH_OPTIONS ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_MULTI_SENSE_WITH_OPTIONS)
+#define RAIL_RX_CHANNEL_HOPPING_MODE_SQ_WITH_OPTIONS ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_SQ_WITH_OPTIONS)
+#define RAIL_RX_CHANNEL_HOPPING_MODE_CONC_WITH_OPTIONS ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_CONC_WITH_OPTIONS)
+#define RAIL_RX_CHANNEL_HOPPING_MODE_VT_WITH_OPTIONS ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_VT_WITH_OPTIONS)
+#define RAIL_RX_CHANNEL_HOPPING_MODE_TX_WITH_OPTIONS ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_TX_WITH_OPTIONS)
#endif//DOXYGEN_SHOULD_SKIP_THIS
/**
@@ -3171,8 +3761,7 @@ RAIL_ENUM(RAIL_RxChannelHoppingMode_t) {
/**
* @enum RAIL_RxChannelHoppingDelayMode_t
- * @brief Modes by which RAIL_RxChannelHoppingConfigEntry_t::delay
- * timing can be applied to the time gap between channels.
+ * @brief Deprecated enum. Set only to RAIL_RX_CHANNEL_DELAY_MODE_STATIC
*/
RAIL_ENUM(RAIL_RxChannelHoppingDelayMode_t) {
/**
@@ -3183,6 +3772,12 @@ RAIL_ENUM(RAIL_RxChannelHoppingDelayMode_t) {
RAIL_RX_CHANNEL_HOPPING_DELAY_MODE_STATIC,
};
+/**
+ * @typedef RAIL_RxChannelHoppingParameter_t
+ * @brief Rx channel hopping on-channel time
+ */
+typedef uint32_t RAIL_RxChannelHoppingParameter_t;
+
#ifndef DOXYGEN_SHOULD_SKIP_THIS
// Self-referencing defines minimize compiler complaints when using RAIL_ENUM
#define RAIL_RX_CHANNEL_HOPPING_DELAY_MODE_STATIC ((RAIL_RxChannelHoppingDelayMode_t) RAIL_RX_CHANNEL_HOPPING_DELAY_MODE_STATIC)
@@ -3200,6 +3795,8 @@ RAIL_ENUM(RAIL_RxChannelHoppingOptions_t) {
RAIL_RX_CHANNEL_HOPPING_OPTION_SKIP_DC_CAL_SHIFT,
/** Shift position of \ref RAIL_RX_CHANNEL_HOPPING_OPTION_RSSI_THRESHOLD bit */
RAIL_RX_CHANNEL_HOPPING_OPTION_RSSI_THRESHOLD_SHIFT,
+ /** Stop hopping on this hop. */
+ RAIL_RX_CHANNEL_HOPPING_OPTION_STOP_SHIFT,
/** A count of the choices in this enumeration. */
RAIL_RX_CHANNEL_HOPPING_OPTIONS_COUNT // Must be last
};
@@ -3235,6 +3832,11 @@ RAIL_ENUM(RAIL_RxChannelHoppingOptions_t) {
* specified and may cause a hop sooner than that mode otherwise would.
*/
#define RAIL_RX_CHANNEL_HOPPING_OPTION_RSSI_THRESHOLD (1U << RAIL_RX_CHANNEL_HOPPING_OPTION_RSSI_THRESHOLD_SHIFT)
+/**
+ * An option to stop the hopping sequence at this entry in the hop
+ * table.
+ */
+#define RAIL_RX_CHANNEL_HOPPING_OPTION_STOP (1U << RAIL_RX_CHANNEL_HOPPING_OPTION_STOP_SHIFT)
/// @struct RAIL_RxChannelHoppingConfigMultiMode_t
/// @brief Structure that parameterizes \ref
@@ -3273,7 +3875,7 @@ RAIL_ENUM(RAIL_RxChannelHoppingOptions_t) {
/// } else {
/// suspendRx(delay);
/// }
-/// onStartRx(); // resume receive after delay (on new channel if hoppping)
+/// onStartRx(); // resume receive after delay (on new channel if hopping)
/// }
///
/// void onStartRx(void) // called upon entry to receive
@@ -3380,10 +3982,10 @@ typedef struct RAIL_RxChannelHoppingConfigEntry {
/**
* The channel number to be used for this entry in the channel hopping
* sequence. If this is an invalid channel for the current phy, the
- * call to RAIL_ConfigRxChannelHopping will fail.
+ * call to \ref RAIL_ConfigRxChannelHopping() will fail.
*/
uint16_t channel;
- /** The mode by which RAIL determines when to hop to the next channel. */
+ /** Deprecated field. Set to RAIL_RX_CHANNEL_HOPPING_DELAY_MODE_STATIC. */
RAIL_RxChannelHoppingMode_t mode;
// Unnamed 'uint8_t reserved1[1]' pad byte field here.
/**
@@ -3391,7 +3993,7 @@ typedef struct RAIL_RxChannelHoppingConfigEntry {
* is used to parameterize that mode. See the comments on each value of
* \ref RAIL_RxChannelHoppingMode_t to learn what to specify here.
*/
- uint32_t parameter;
+ RAIL_RxChannelHoppingParameter_t parameter;
/**
* Idle time in microseconds to wait before hopping into the
* channel indicated by this entry.
@@ -3444,13 +4046,16 @@ typedef struct RAIL_RxChannelHoppingConfig {
*/
uint32_t *buffer;
/**
- * This parameter must be set to the length of the buffer array. This way,
- * during configuration, the software can confirm it's writing within the
- * range of the buffer. The configuration API will return an error
- * if bufferLength is insufficient.
+ * This parameter must be set to the length of the buffer array, in 32 bit
+ * words. This way, during configuration, the software can confirm it's
+ * writing within the range of the buffer. The configuration API will return
+ * an error if bufferLength is insufficient.
*/
uint16_t bufferLength;
- /** The number of channels that is in the channel hopping sequence. */
+ /**
+ * The number of channels in the channel hopping sequence, which is the
+ * number of elements in the array that entries points to.
+ */
uint8_t numberOfChannels;
/**
* A pointer to the first element of an array of \ref
@@ -3474,7 +4079,7 @@ typedef struct RAIL_RxDutyCycleConfig {
* \ref RAIL_RxChannelHoppingMode_t to learn what to specify here.
*/
// Unnamed 'uint8_t reserved[3]' pad byte field here.
- uint32_t parameter;
+ RAIL_RxChannelHoppingParameter_t parameter;
/**
* Idle time in microseconds to wait before re-entering RX.
*/
@@ -3507,7 +4112,7 @@ typedef struct RAIL_RxDutyCycleConfig {
/** @} */ // end of group Rx_Channel_Hopping
/******************************************************************************
- * Diagnositc Structures
+ * Diagnostic Structures
*****************************************************************************/
/**
* @addtogroup Diagnostic
@@ -3522,6 +4127,9 @@ RAIL_ENUM(RAIL_StreamMode_t) {
RAIL_STREAM_CARRIER_WAVE = 0, /**< An unmodulated carrier wave. */
RAIL_STREAM_PN9_STREAM = 1, /**< PN9 byte sequence. */
RAIL_STREAM_10_STREAM = 2, /**< 101010 sequence. */
+ RAIL_STREAM_CARRIER_WAVE_PHASENOISE = 3, /**< An unmodulated carrier wave with no change to PLL BW. For series-2, same as RAIL_STREAM_CARRIER_WAVE */
+ RAIL_STREAM_RAMP_STREAM = 4, /**< ramp sequence starting at a different offset for consecutive packets. Only available for some modulations. Fall back to RAIL_STREAM_PN9_STREAM if not available. */
+ RAIL_STREAM_CARRIER_WAVE_SHIFTED = 5, /**< An unmodulated carrier wave not centered on DC but shifted roughly by channel_bandwidth/6 allowing an easy check of the residual DC. Only available for OFDM PA. Fall back to RAIL_STREAM_CARRIER_WAVE_PHASENOISE if not available. */
RAIL_STREAM_MODES_COUNT /**< A count of the choices in this enumeration. Must be last. */
};
@@ -3530,6 +4138,10 @@ RAIL_ENUM(RAIL_StreamMode_t) {
#define RAIL_STREAM_CARRIER_WAVE ((RAIL_StreamMode_t) RAIL_STREAM_CARRIER_WAVE)
#define RAIL_STREAM_PN9_STREAM ((RAIL_StreamMode_t) RAIL_STREAM_PN9_STREAM)
#define RAIL_STREAM_10_STREAM ((RAIL_StreamMode_t) RAIL_STREAM_10_STREAM)
+#define RAIL_STREAM_CARRIER_WAVE_PHASENOISE ((RAIL_StreamMode_t) RAIL_STREAM_CARRIER_WAVE_PHASENOISE)
+#define RAIL_STREAM_RAMP_STREAM ((RAIL_StreamMode_t) RAIL_STREAM_RAMP_STREAM)
+#define RAIL_STREAM_CARRIER_WAVE_SHIFTED ((RAIL_StreamMode_t) RAIL_STREAM_CARRIER_WAVE_SHIFTED)
+
#define RAIL_STREAM_MODES_COUNT ((RAIL_StreamMode_t) RAIL_STREAM_MODES_COUNT)
#endif//DOXYGEN_SHOULD_SKIP_THIS
@@ -3586,14 +4198,6 @@ typedef struct RAIL_VerifyConfig {
RAIL_VerifyCallbackPtr_t cb;
} RAIL_VerifyConfig_t;
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-typedef struct RAIL_DirectModeConfig {
- bool enable; /**< Indicates whether to enable direct mode. */
-} RAIL_DirectModeConfig_t;
-
-#endif//DOXYGEN_SHOULD_SKIP_THIS
-
/** @} */ // end of group Diagnostic
#ifndef DOXYGEN_SHOULD_SKIP_THIS
@@ -3624,10 +4228,143 @@ typedef struct RAIL_DirectModeConfig {
#endif//DOXYGEN_SHOULD_SKIP_THIS
+/** @} */ // end of RAIL_API
+
+#ifdef __cplusplus
+}
+#endif
+
+// Include appropriate chip-specific types and APIs *after* common types, and
+// *before* types that require chip-specific abstractions.
+#include "rail_chip_specific.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @addtogroup RAIL_API
+ * @{
+ */
+
+/**
+ * @addtogroup State_Transitions
+ * @{
+ */
+
+/**
+ * @def RAIL_TRANSITION_TIME_KEEP
+ * @brief A value to use in \ref RAIL_StateTiming_t fields when
+ * calling \ref RAIL_SetStateTiming() to keep that timing
+ * parameter at it current setting.
+ */
+#define RAIL_TRANSITION_TIME_KEEP ((RAIL_TransitionTime_t) -1)
+
+/**
+ * @struct RAIL_StateTiming_t
+ * @brief A timing configuration structure for the RAIL State Machine.
+ *
+ * Configure the timings of the radio state transitions for common situations.
+ * All of the listed timings are in microseconds. Transitions from an active
+ * radio state to idle are not configurable, and will always happen as fast
+ * as possible.
+ * No timing value can exceed \ref RAIL_MAXIMUM_TRANSITION_US.
+ * Use \ref RAIL_TRANSITION_TIME_KEEP to keep an existing setting.
+ *
+ * For idleToRx, idleToTx, rxToTx, txToRx, and txToTx a value of 0 for the
+ * transition time means that the specified transition should happen as fast
+ * as possible, even if the timing cannot be as consistent. Otherwise, the
+ * timing value cannot be below \ref RAIL_MINIMUM_TRANSITION_US.
+ *
+ * For idleToTx, rxToTx, and txToTx setting a longer \ref
+ * RAIL_TxPowerConfig_t::rampTime may result in a larger minimum value.
+ *
+ * For rxSearchTimeout and txToRxSearchTimeout, there is no minimum value. A
+ * value of 0 disables the feature, functioning as an infinite timeout.
+ */
+typedef struct RAIL_StateTiming {
+ RAIL_TransitionTime_t idleToRx; /**< Transition time from IDLE to RX. */
+ RAIL_TransitionTime_t txToRx; /**< Transition time from TX to RX. */
+ RAIL_TransitionTime_t idleToTx; /**< Transition time from IDLE to RX. */
+ RAIL_TransitionTime_t rxToTx; /**< Transition time from RX packet to TX. */
+ RAIL_TransitionTime_t rxSearchTimeout; /**< Length of time the radio will search for a
+ packet when coming from idle or RX. */
+ RAIL_TransitionTime_t txToRxSearchTimeout; /**< Length of time the radio will search for a
+ packet when coming from TX. */
+ RAIL_TransitionTime_t txToTx; /**< Transition time from TX packet to TX. */
+} RAIL_StateTiming_t;
+
+/** @} */ // end of group State_Transitions
+
+/**
+ * @addtogroup Transmit
+ * @{
+ */
+
+/**
+ * @enum RAIL_TxRepeatOptions_t
+ * @brief Transmit repeat options, in reality a bitmask.
+ */
+RAIL_ENUM_GENERIC(RAIL_TxRepeatOptions_t, uint16_t) {
+ /** Shift position of \ref RAIL_TX_REPEAT_OPTION_HOP bit */
+ RAIL_TX_REPEAT_OPTION_HOP_SHIFT = 0,
+};
+
+/** A value representing no repeat options enabled. */
+#define RAIL_TX_REPEAT_OPTIONS_NONE 0U
+/** All repeat options disabled by default. */
+#define RAIL_TX_REPEAT_OPTIONS_DEFAULT RAIL_TX_REPEAT_OPTIONS_NONE
/**
- * @}
- * end of RAIL_API
+ * An option to configure whether or not to channel-hop before each
+ * repeated transmit.
*/
+#define RAIL_TX_REPEAT_OPTION_HOP (1U << RAIL_TX_REPEAT_OPTION_HOP_SHIFT)
+
+/// @struct RAIL_TxRepeatConfig_t
+/// @brief A configuration structure for repeated transmits
+///
+/// @note The PA will always be ramped down and up in between transmits so
+/// there will always be some minimum delay between transmits depending on the
+/// ramp time configuration.
+typedef struct RAIL_TxRepeatConfig {
+ /**
+ * The number of repeated transmits to run. A total of (iterations + 1)
+ * transmits will go on-air in the absence of errors.
+ */
+ uint16_t iterations;
+ /**
+ * Repeat option(s) to apply.
+ */
+ RAIL_TxRepeatOptions_t repeatOptions;
+ /**
+ * Per-repeat delay or hopping configuration, depending on repeatOptions.
+ */
+ union {
+ /**
+ * When \ref RAIL_TX_REPEAT_OPTION_HOP is not set, specifies
+ * the delay time between each repeated transmit. Specify \ref
+ * RAIL_TRANSITION_TIME_KEEP to use the current \ref
+ * RAIL_StateTiming_t::txToTx transition time setting.
+ */
+ RAIL_TransitionTime_t delay;
+ /**
+ * When \ref RAIL_TX_REPEAT_OPTION_HOP is set, this specifies
+ * the channel hopping configuration to use when hopping between
+ * repeated transmits. Per-hop delays are configured within each
+ * \ref RAIL_TxChannelHoppingConfigEntry_t::delay rather than
+ * this union's delay field.
+ */
+ RAIL_TxChannelHoppingConfig_t channelHopping;
+ } delayOrHop;
+} RAIL_TxRepeatConfig_t;
+
+/// RAIL_TxRepeatConfig_t::iterations initializer configuring infinite
+/// repeated transmissions.
+#define RAIL_TX_REPEAT_INFINITE_ITERATIONS (0xFFFFU)
+
+/** @} */ // end of group Transmit
+
+/** @} */ // end of RAIL_API
#ifdef __cplusplus
}
diff --git a/mcu/efr/efr32/config.mk b/mcu/efr/efr32/config.mk
index 1e1ce43c..a11b21a5 100644
--- a/mcu/efr/efr32/config.mk
+++ b/mcu/efr/efr32/config.mk
@@ -4,22 +4,25 @@ HAS_BOOTLOADER=yes
CFLAGS += -DEFR32_PLATFORM
ifeq ($(MCU)$(MCU_SUB)$(MCU_MEM_VAR),efr32xg12pxxxf1024)
+ EFR32_SERIES=1
# Hardware magic used for this architecture with 1024kB Flash, 128kB RAM
HW_MAGIC=05
HW_VARIANT_ID=05
CFLAGS += -DEFR32FG12 -DEFR32FG12P232F1024GL125
# Mcu instruction set
ARCH=armv7e-m
- HAL_SYSTEM_C := efr32fg12/system_efr32fg12p.c
+ HAL_SYSTEM_C := efr32fg12/Source/system_efr32fg12p.c
else ifeq ($(MCU)$(MCU_SUB)$(MCU_MEM_VAR),efr32xg12pxxxf512)
+ EFR32_SERIES=1
# Hardware magic used for this architecture with 512kB Flash, 64kB RAM
HW_MAGIC=07
HW_VARIANT_ID=07
CFLAGS += -DEFR32FG12 -DEFR32FG12P232F1024GL125
# Mcu instruction set
ARCH=armv7e-m
- HAL_SYSTEM_C := efr32fg12/system_efr32fg12p.c
+ HAL_SYSTEM_C := efr32fg12/Source/system_efr32fg12p.c
else ifeq ($(MCU)$(MCU_SUB),efr32xg21)
+ EFR32_SERIES=2
ifeq ($(radio),bgm210pa22jia)
HW_MAGIC=0C
HW_VARIANT_ID=0E
@@ -50,6 +53,7 @@ else ifeq ($(MCU)$(MCU_SUB),efr32xg21)
$(error "DCDC is not supported by efr32xg21")
endif
else ifeq ($(MCU)$(MCU_SUB)$(MCU_MEM_VAR),efr32xg22xxxxf512)
+ EFR32_SERIES=2
ifeq ($(radio),bgm220pc22hna)
HW_MAGIC=0D
HW_VARIANT_ID=0F
@@ -60,7 +64,7 @@ else ifeq ($(MCU)$(MCU_SUB)$(MCU_MEM_VAR),efr32xg22xxxxf512)
HW_MAGIC=0B
HW_VARIANT_ID=0B
endif
- CFLAGS += -DEFR32MG22 -DEFR32MG22C224F512IM32
+ CFLAGS += -DEFR32MG22 -DEFR32MG22C224F512IM40
CFLAGS += -DARM_MATH_ARMV8MML
CFLAGS += -mfloat-abi=hard -mfpu=fpv5-sp-d16
# Mcu instruction set
@@ -76,6 +80,7 @@ else ifeq ($(MCU)$(MCU_SUB)$(MCU_MEM_VAR),efr32xg22xxxxf512)
$(error "32kHz crystal must be installed on efr32xg22 board")
endif
else ifeq ($(MCU)$(MCU_SUB)$(MCU_MEM_VAR),efr32xg23xxxxf512)
+ EFR32_SERIES=2
HW_MAGIC=10
HW_VARIANT_ID=13
CFLAGS += -DEFR32FG23 -DEFR32FG23B020F512IM48
@@ -90,6 +95,33 @@ else ifeq ($(MCU)$(MCU_SUB)$(MCU_MEM_VAR),efr32xg23xxxxf512)
ifneq ($(board_hw_crystal_32k),no)
$(error "32kHz crystal not supported on efr32xg23 board")
endif
+else ifeq ($(MCU)$(MCU_SUB),efr32xg24)
+ EFR32_SERIES=2
+ # HWM_EFR32XG24 = 17, as hex string
+ HW_MAGIC=11
+
+ ifeq ($(MCU_MEM_VAR), xxxxf1536)
+ HW_VARIANT_ID=17
+ CFLAGS += -DEFR32MG24 -DEFR32MG24B210F1536IM48 ## xG24-EK2703A dev kit
+ else ifeq ($(MCU_MEM_VAR), xxxxf1024)
+ HW_VARIANT_ID=16
+ CFLAGS += -DEFR32MG24 -DEFR32MG24B010F1024IM48
+ else
+ $(error "Invalid xg24 memory variant $(MCU)$(MCU_SUB)$(MCU_MEM_VAR)!")
+ endif
+
+ CFLAGS += -DARM_MATH_ARMV8MML
+ CFLAGS += -mfloat-abi=hard -mfpu=fpv5-sp-d16
+ # Mcu instruction set
+ ARCH=armv8-m.main
+ # Libraries to be build for Cortex-M33
+ CM33 := yes
+ HAL_SYSTEM_C := efr32mg24/Source/system_efr32mg24.c
+ # Bootloader sanity check
+ ifneq ($(board_hw_dcdc),yes)
+ $(error "DCDC must be enabled on efr32xg24")
+ endif
+
else
$(error "Invalid MCU configuration $(MCU)$(MCU_SUB)$(MCU_MEM_VAR)!")
endif
diff --git a/mcu/efr/efr32/hal/board_usart.h b/mcu/efr/efr32/hal/board_usart.h
deleted file mode 100644
index f05fe479..00000000
--- a/mcu/efr/efr32/hal/board_usart.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* Copyright 2020 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-#ifndef BOARD_USART_H_
-#define BOARD_USART_H_
-
-// Map some registers constant to the USART selected
-#if defined(_SILICON_LABS_32B_SERIES_1)
-
-#if BOARD_USART_ID == 0
-#define BOARD_USART USART0
-#define BOARD_USART_CMU_BIT CMU_HFPERCLKEN0_USART0
-#define BOARD_UART_RX_IRQn USART0_RX_IRQn
-#define BOARD_UART_TX_IRQn USART0_TX_IRQn
-#define BOARD_UART_LDMA_RX ldmaPeripheralSignal_USART0_RXDATAV
-#define BOARD_UART_LDMA_TX ldmaPeripheralSignal_USART0_TXEMPTY
-#elif BOARD_USART_ID == 1
-#define BOARD_USART USART1
-#define BOARD_USART_CMU_BIT CMU_HFPERCLKEN0_USART1
-#define BOARD_UART_RX_IRQn USART1_RX_IRQn
-#define BOARD_UART_TX_IRQn USART1_TX_IRQn
-#define BOARD_UART_LDMA_RX ldmaPeripheralSignal_USART1_RXDATAV
-#define BOARD_UART_LDMA_TX ldmaPeripheralSignal_USART1_TXEMPTY
-#elif BOARD_USART_ID == 2
-#define BOARD_USART USART2
-#define BOARD_USART_CMU_BIT CMU_HFPERCLKEN0_USART2
-#define BOARD_UART_RX_IRQn USART2_RX_IRQn
-#define BOARD_UART_TX_IRQn USART2_TX_IRQn
-#define BOARD_UART_LDMA_RX ldmaPeripheralSignal_USART2_RXDATAV
-#define BOARD_UART_LDMA_TX ldmaPeripheralSignal_USART2_TXEMPTY
-#elif BOARD_USART_ID == 3
-#define BOARD_USART USART3
-#define BOARD_USART_CMU_BIT CMU_HFPERCLKEN0_USART3
-#define BOARD_UART_RX_IRQn USART3_RX_IRQn
-#define BOARD_UART_TX_IRQn USART3_TX_IRQn
-#define BOARD_UART_LDMA_RX ldmaPeripheralSignal_USART3_RXDATAV
-#define BOARD_UART_LDMA_TX ldmaPeripheralSignal_USART3_TXEMPTY
-#else // BOARD_USART_ID
-#error USART ID must be 0, 1, 2 or 3
-#endif // BOARD_USART_ID
-#define BOARD_USART_ROUTE BOARD_USART->ROUTELOC0 = BOARD_USART_ROUTELOC_RXLOC | \
- BOARD_USART_ROUTELOC_TXLOC
-#define BOARD_USART_PINS BOARD_USART->ROUTEPEN = USART_ROUTEPEN_RXPEN | \
- USART_ROUTEPEN_TXPEN
-#define BOARD_USART_CLR_IRQ_ALL BOARD_USART->IFC = _USART_IFC_MASK
-#define BOARD_USART_CLR_IRQ_RXFULL BOARD_USART->IFC = USART_IFC_RXFULL
-#define BOARD_USART_CLR_IRQ_TXC BOARD_USART->IFC = _USART_IFC_TXC_MASK
-#define BOARD_USART_CLR_IRQ_TCMP1 BOARD_USART->IFC = USART_IFC_TCMP1
-#define BOARD_USART_LDMA_CLR_IRQ LDMA->IFC
-#define BOARD_USART_LDMA_ENABLE // TODO: Change to LDMA_Init()
-#define BOARD_USART_LDMA_DISABLE // TODO: Change to LDMA_DeInit()
-#define BOARD_USART_ENABLE_USART_CLK CMU->HFPERCLKEN0 |= BOARD_USART_CMU_BIT
-#define BOARD_USART_DISABLE_USART_CLK CMU->HFPERCLKEN0 &= ~(BOARD_USART_CMU_BIT)
-#define BOARD_USART_ENABLE_LDMA_CLK CMU->HFBUSCLKEN0 |= CMU_HFBUSCLKEN0_LDMA
-#define BOARD_USART_DISABLE_LDMA_CLK CMU->HFBUSCLKEN0 &= ~(CMU_HFBUSCLKEN0_LDMA)
-#define BOARD_USART_ENABLE_GPIO_CLK CMU->HFBUSCLKEN0 |= CMU_HFBUSCLKEN0_GPIO
-#define BOARD_USART_DISABLE_GPIO_CLK CMU->HFBUSCLKEN0 &= ~(CMU_HFBUSCLKEN0_GPIO)
-
-#else // defined(_SILICON_LABS_32B_SERIES_1)
-
-#if BOARD_USART_ID == 0
-#define BOARD_USART USART0
-#define BOARD_USART_CMU_BIT CMU_CLKEN0_USART0
-#define BOARD_USARTINPUT PRS->CONSUMER_USART0_RX
-#define BOARD_USARTROUTE GPIO->USARTROUTE[0]
-#define BOARD_UART_RX_IRQn USART0_RX_IRQn
-#define BOARD_UART_TX_IRQn USART0_TX_IRQn
-#define BOARD_UART_LDMA_RX ldmaPeripheralSignal_USART0_RXDATAV
-#define BOARD_UART_LDMA_TX ldmaPeripheralSignal_USART0_TXEMPTY
-#elif BOARD_USART_ID == 1
-#define BOARD_USART USART1
-#define BOARD_USART_CMU_BIT CMU_CLKEN0_USART0
-#define BOARD_USARTINPUT PRS->CONSUMER_USART1_RX
-#define BOARD_USARTROUTE GPIO->USARTROUTE[1]
-#define BOARD_UART_RX_IRQn USART1_RX_IRQn
-#define BOARD_UART_TX_IRQn USART1_TX_IRQn
-#define BOARD_UART_LDMA_RX ldmaPeripheralSignal_USART1_RXDATAV
-#define BOARD_UART_LDMA_TX ldmaPeripheralSignal_USART1_TXEMPTY
-#else // BOARD_USART_ID
-#error USART ID must be 0 or 1
-#endif // BOARD_USART_ID
-#define BOARD_USART_ROUTE BOARD_USARTROUTE.RXROUTE = BOARD_USART_RX_PIN << _GPIO_USART_RXROUTE_PIN_SHIFT | \
- BOARD_USART_GPIO_PORT << _GPIO_USART_RXROUTE_PORT_SHIFT; \
- BOARD_USARTROUTE.TXROUTE = BOARD_USART_TX_PIN << _GPIO_USART_RXROUTE_PIN_SHIFT | \
- BOARD_USART_GPIO_PORT << _GPIO_USART_RXROUTE_PORT_SHIFT
-#define BOARD_USART_PINS BOARD_USARTROUTE.ROUTEEN = GPIO_USART_ROUTEEN_RXPEN | \
- GPIO_USART_ROUTEEN_TXPEN
-#define BOARD_USART_CLR_IRQ_ALL BOARD_USART->IF_CLR = _USART_IF_MASK
-#define BOARD_USART_CLR_IRQ_RXFULL BOARD_USART->IF_CLR = USART_IF_RXFULL
-#define BOARD_USART_CLR_IRQ_TXC BOARD_USART->IF_CLR = _USART_IF_TXC_MASK
-#define BOARD_USART_CLR_IRQ_TCMP1 BOARD_USART->IF_CLR = USART_IF_TCMP1
-#define BOARD_USART_LDMA_CLR_IRQ LDMA->IF_CLR
-#define BOARD_USART_LDMA_ENABLE LDMA->EN = LDMA_EN_EN // TODO: Change to LDMA_Init()
-#define BOARD_USART_LDMA_DISABLE LDMA->EN = 0 // TODO: Change to LDMA_DeInit()
-#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1)
-#define BOARD_USART_ENABLE_USART_CLK
-#define BOARD_USART_DISABLE_USART_CLK
-#define BOARD_USART_ENABLE_LDMA_CLK
-#define BOARD_USART_DISABLE_LDMA_CLK
-#define BOARD_USART_ENABLE_GPIO_CLK
-#define BOARD_USART_DISABLE_GPIO_CLK
-#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3)
-#define BOARD_USART_ENABLE_USART_CLK CMU->CLKEN0_SET = BOARD_USART_CMU_BIT
-#define BOARD_USART_DISABLE_USART_CLK CMU->CLKEN0_CLR = BOARD_USART_CMU_BIT
-#define BOARD_USART_ENABLE_LDMA_CLK CMU->CLKEN0_SET = CMU_CLKEN0_LDMA | CMU_CLKEN0_LDMAXBAR
-#define BOARD_USART_DISABLE_LDMA_CLK CMU->CLKEN0_CLR = CMU_CLKEN0_LDMA | CMU_CLKEN0_LDMAXBAR
-#define BOARD_USART_ENABLE_GPIO_CLK CMU->CLKEN0_SET = CMU_CLKEN0_GPIO | CMU_CLKEN0_PRS
-#define BOARD_USART_DISABLE_GPIO_CLK CMU->CLKEN0_CLR = CMU_CLKEN0_GPIO | CMU_CLKEN0_PRS
-#endif // defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1)
-
-#endif // defined(_SILICON_LABS_32B_SERIES_1)
-
-#endif // BOARD_USART_H_
diff --git a/mcu/efr/efr32/hal/button.c b/mcu/efr/efr32/hal/button.c
deleted file mode 100644
index e782edda..00000000
--- a/mcu/efr/efr32/hal/button.c
+++ /dev/null
@@ -1,334 +0,0 @@
-/* Copyright 2019 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-/*
- * \file button.c
- * \brief Board-specific button module for efr32
- */
-
-#include "button.h"
-#include "mcu.h"
-#include "board.h"
-#include "api.h"
-
-
-#ifdef BOARD_BUTTON_PIN_LIST
-
-/*
- * The selected board has buttons
- */
-
-#ifndef BOARD_DEBOUNCE_TIME_MS
-/** \brief Debounce time of button in ms. It can be overwritten from board.h */
-#define BOARD_DEBOUNCE_TIME_MS 100
-#endif
-
-#ifndef BOARD_BUTTON_ACTIVE_LOW
-/** \brief Is button active low. It can be overwritten from board.h */
-#define BOARD_BUTTON_ACTIVE_LOW true
-#endif
-
-#ifndef BOARD_BUTTON_INTERNAL_PULL
-/** \brief Does the driver needs to activate internal pull-up/down.
- * If true; pull-up (down) is enabled if BOARD_BUTTON_ACTIVE_LOW is
- * true (false). It can be overwritten from board.h
- */
-#define BOARD_BUTTON_INTERNAL_PULL true
-#endif
-
-#ifndef BOARD_BUTTON_USE_EVEN_INT
-/** \brief Use even (or odd) ext int. It can be overwritten from board.h */
-#define BOARD_BUTTON_USE_EVEN_INT true
-#endif
-
-/** \brief Each button use a GPIOTE channel Define first one */
-#define GPIOTE_START_CHANNEL 0
-
-/** \brief GPIO port and pin number */
-typedef struct
-{
- uint8_t ext_int;
- uint8_t port;
- uint8_t pin;
-} button_gpio_t;
-
-/** \brief Board-dependent Button number to pin mapping */
-static const button_gpio_t m_pin_map[] = BOARD_BUTTON_PIN_LIST;
-
-/** \brief Compute number of buttons on the board */
-#define BOARD_BUTTON_NUMBER (sizeof(m_pin_map) / sizeof(m_pin_map[0]))
-
-typedef struct
-{
- // Callback when button pressed
- on_button_event_cb on_pressed;
- // Callback when button released
- on_button_event_cb on_released;
- // Used for debounce
- app_lib_time_timestamp_hp_t last_button_event;
- // True if button GPIO is active low
- bool active_low;
-} button_internal_t;
-
-/** \brief Table to manage the button list */
-static button_internal_t m_button_conf[BOARD_BUTTON_NUMBER];
-
-static void button_interrupt_handler(void);
-
-static void button_enable_interrupt(uint8_t ext_int,
- uint8_t port,
- uint8_t pin,
- bool enable)
-{
- bool high_reg = ext_int >= 8;
- uint8_t shift = (ext_int & 7) * 4;
- uint32_t mask = ~((uint32_t)0xf << shift);
- uint32_t set = 0;
-
- // Select port
- set = enable ? (uint32_t)port << shift : 0;
- if (high_reg)
- {
-#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1)
- GPIO->EXTIPSELH = (GPIO->EXTIPSELH & mask) | set;
-#endif
- }
- else
- {
- GPIO->EXTIPSELL = (GPIO->EXTIPSELL & mask) | set;
- }
-
- // Select pin
- set = enable ? (uint32_t)(pin & 3) << shift : 0;
- if (high_reg)
- {
-#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1)
- GPIO->EXTIPINSELH = (GPIO->EXTIPINSELH & mask) | set;
-#endif
- }
- else
- {
- GPIO->EXTIPINSELL = (GPIO->EXTIPINSELL & mask) | set;
- }
-
- // Set rising and falling edge sensitivity
- shift = ext_int;
- mask = ~((uint32_t)1 << shift);
- set = enable ? (uint32_t)1 << shift : 0;
- GPIO->EXTIRISE = (GPIO->EXTIRISE & mask) | set;
- GPIO->EXTIFALL = (GPIO->EXTIFALL & mask) | set;
-
- //Clear external interrupt flag
-#if defined(_SILICON_LABS_32B_SERIES_1)
- GPIO->IFC = (uint32_t)1 << shift;
-#else
- GPIO->IF_CLR = (uint32_t)1 << shift;
-#endif
-
- // Enable or disable external interrupt
- GPIO->IEN = (GPIO->IEN & mask) | set;
-}
-
-void Button_init(void)
-{
- // Enable clocks
-#if defined(_SILICON_LABS_32B_SERIES_1)
- CMU->HFBUSCLKEN0 |= CMU_HFBUSCLKEN0_GPIO;
-#elif !defined (EFR32MG21)
- CMU->CLKEN0_SET = CMU_CLKEN0_GPIO;
-#endif
-
- // Get current timestamp
- app_lib_time_timestamp_hp_t now = lib_time->getTimestampHp();
-
- // Configure button GPIOs
- for (uint8_t i = 0; i < BOARD_BUTTON_NUMBER; i++)
- {
- // Set button configuration
- m_button_conf[i].on_pressed = NULL;
- m_button_conf[i].on_released = NULL;
- m_button_conf[i].last_button_event = now;
- m_button_conf[i].active_low = BOARD_BUTTON_ACTIVE_LOW;
-
- // Enable the Pull-Up/Down on Buttons.
- if (BOARD_BUTTON_INTERNAL_PULL)
- {
- // Set pin mode: input enabled with filter, DOUT sets pull dir.
- hal_gpio_set_mode(m_pin_map[i].port,
- m_pin_map[i].pin,
- GPIO_MODE_IN_PP);
-
- if (m_button_conf[i].active_low)
- {
- hal_gpio_set(m_pin_map[i].port, m_pin_map[i].pin);
- }
- else
- {
- hal_gpio_clear(m_pin_map[i].port, m_pin_map[i].pin);
- }
- }
- else
- {
- // Default config: Input No Pull, DOUT enables filter.
- hal_gpio_set_mode(m_pin_map[i].port,
- m_pin_map[i].pin,
- GPIO_MODE_IN_OD_NOPULL);
- hal_gpio_set(m_pin_map[i].port, m_pin_map[i].pin);
- }
- }
-
- // Enable even or odd external interrupts
- lib_system->enableAppIrq(
- false,
- BOARD_BUTTON_USE_EVEN_INT ? GPIO_EVEN_IRQn : GPIO_ODD_IRQn,
- APP_LIB_SYSTEM_IRQ_PRIO_LO,
- button_interrupt_handler);
-}
-
-button_res_e Button_getState(uint8_t button_id, bool * state_p)
-{
- if (button_id >= BOARD_BUTTON_NUMBER)
- {
- // Invalid button number
- return BUTTON_RES_INVALID_ID;
- }
-
- uint32_t b = hal_gpio_get(m_pin_map[button_id].port,
- m_pin_map[button_id].pin);
-
- if (m_button_conf[button_id].active_low)
- {
- b ^= 0x01;
- }
-
- *state_p = (b != 0);
-
- return BUTTON_RES_OK;
-}
-
-button_res_e Button_register_for_event(uint8_t button_id,
- button_event_e event,
- on_button_event_cb cb)
-{
- if ((button_id >= BOARD_BUTTON_NUMBER)
- || (event != BUTTON_PRESSED && event != BUTTON_RELEASED ))
- {
- // Invalid button number
- return BUTTON_RES_INVALID_ID;
- }
-
- Sys_enterCriticalSection();
-
- if (event == BUTTON_PRESSED)
- {
- m_button_conf[button_id].on_pressed = cb;
- }
- else
- {
- m_button_conf[button_id].on_released = cb;
- }
-
- // Enable interrupt if at least one event registered, disable otherwise
- button_enable_interrupt(m_pin_map[button_id].ext_int,
- m_pin_map[button_id].port,
- m_pin_map[button_id].pin,
- m_button_conf[button_id].on_pressed ||
- m_button_conf[button_id].on_released);
-
- Sys_exitCriticalSection();
-
- return BUTTON_RES_OK;
-}
-
-uint8_t Button_get_number(void)
-{
- return BOARD_BUTTON_NUMBER;
-}
-
-static void button_interrupt_handler(void)
-{
- app_lib_time_timestamp_hp_t now = lib_time->getTimestampHp();
-
- // Check all possible sources
- for (uint8_t i = 0; i < BOARD_BUTTON_NUMBER; i++)
- {
- // Read external interrupt flag
- if ((GPIO->IF & (((uint32_t)1) << m_pin_map[i].ext_int)) != 0)
- {
- if (lib_time->getTimeDiffUs(now, m_button_conf[i].last_button_event)
- > (BOARD_DEBOUNCE_TIME_MS * 1000))
- {
- // Button is pressed if gpio is in active state
- bool pressed = hal_gpio_get(m_pin_map[i].port,
- m_pin_map[i].pin);
- if (m_button_conf[i].active_low)
- {
- pressed = !pressed;
- }
- m_button_conf[i].last_button_event = now;
-
- if (m_button_conf[i].on_pressed && pressed)
- {
- m_button_conf[i].on_pressed(i, BUTTON_PRESSED);
- }
- else if (m_button_conf[i].on_released && !pressed)
- {
- m_button_conf[i].on_released(i, BUTTON_RELEASED);
- }
- }
-
- // Clear external interrupt flag
-#if defined(_SILICON_LABS_32B_SERIES_1)
- GPIO->IFC = (uint32_t)1 << m_pin_map[i].ext_int;
-#else
- GPIO->IF_CLR = (uint32_t)1 << m_pin_map[i].ext_int;
-#endif
- }
- }
-}
-
-#else // BOARD_BUTTON_PIN_LIST
-
-/*
- * The selected board has no buttons
- *
- * As some example apps support such boards but also provide extra features
- * when a board has buttons, the button driver has this dummy implementation
- * to simplify the build process.
- */
-
-void Button_init(void)
-{
- // Do nothing
-}
-
-button_res_e Button_getState(uint8_t button_id, bool * state_p)
-{
- (void) button_id;
- *state_p = false;
-
- // Invalid button number
- return BUTTON_RES_INVALID_ID;
-}
-
-uint8_t Button_get_number(void)
-{
- return 0;
-}
-
-button_res_e Button_register_for_event(uint8_t button_id,
- button_event_e event,
- on_button_event_cb cb)
-{
- (void) button_id;
- (void) event;
- (void) cb;
-
- // Invalid button number
- return BUTTON_RES_INVALID_ID;
-}
-
-#endif // BOARD_BUTTON_PIN_LIST
diff --git a/mcu/efr/efr32/hal/gpio.c b/mcu/efr/efr32/hal/gpio.c
new file mode 100644
index 00000000..1a544592
--- /dev/null
+++ b/mcu/efr/efr32/hal/gpio.c
@@ -0,0 +1,606 @@
+/* Copyright 2022 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+
+/**
+ * \file gpio.c
+ * \brief Board-specific GPIO functions for efr32.
+ * \attention Should be compatible with the gpio.h interface.
+ */
+
+#include "gpio.h"
+#include "mcu.h"
+#include "board.h"
+#include "api.h"
+#include "em_cmu.h"
+#include "em_gpio.h"
+
+/*
+ * If some GPIOs are mapped
+ *
+ * Note:
+ * If BOARD_GPIO_PIN_LIST is not defined,
+ * then the dummy functions defined in the gpio_weak.c file will be used instead
+ */
+#ifdef BOARD_GPIO_PIN_LIST
+
+/** \brief Interrupt identified as free (meaning it is available) */
+#define IT_FREE (0x1F) // must be greater than GPIO_EXTINTNO_MAX
+
+/** \brief GPIO external interrupt number */
+typedef uint8_t gpio_it_t;
+
+/** \brief GPIO direction */
+typedef enum
+{
+ /** input direction */
+ DIR_INPUT,
+ /** output direction */
+ DIR_OUTPUT
+} direction_e;
+
+/** \brief GPIO internal configuration */
+typedef struct
+{
+ /** GPIO direction (either input or output) */
+ direction_e direction : 1;
+ /** Callback called on GPIO events. Only used on input GPIO */
+ gpio_in_event_e event_cfg : 2;
+ /** GPIO interrupt number. Only used on input GPIO */
+ gpio_it_t it : 5; // bitsize = 5 to hold interrupt number (see GPIO_EXTINTNO_MAX) and IT_FREE value
+} gpio_cfg_t;
+
+/** \brief GPIO id to GPIO pin map (array index: GPIO id ; array value: GPIO port & pin) */
+static const struct
+{
+ gpio_port_t port;
+ gpio_pin_t pin;
+} m_id_to_pin_map[] = BOARD_GPIO_PIN_LIST;
+
+/** \brief Compute number of GPIOs that are mapped (= total number of used GPIOs) */
+#define BOARD_GPIO_NUMBER (sizeof(m_id_to_pin_map) / sizeof(m_id_to_pin_map[0]))
+
+/** \brief GPIO id to GPIO internal config map (array index: GPIO id ; array value: GPIO internal config) */
+static gpio_cfg_t m_id_to_cfg_map[BOARD_GPIO_NUMBER];
+
+/** \brief GPIO id to GPIO event callback map (array index: GPIO id ; array value: GPIO event callback) */
+static gpio_in_event_cb_f m_id_to_event_cb_map[BOARD_GPIO_NUMBER];
+
+/** \brief Has the library been initialized */
+static bool m_initialized = false;
+
+/**
+ * \brief Check if the pin numbers of the mapped GPIOs are valid (if they exist on the MCU)
+ * \return True if all the pin numbers are valid ; False otherwise
+ */
+static bool check_pins(void);
+
+/**
+ * \brief Configure mode (e.g.: pull-down) of input GPIO
+ * \param id
+ * Id of the GPIO
+ * \param[in] in_cfg
+ * GPIO input configuration
+ */
+static void input_set_cfg_mode(gpio_id_t id, const gpio_in_cfg_t *in_cfg);
+
+/**
+ * \brief Configure interrupt of input GPIO
+ * \param id
+ * Id of the GPIO
+ * \param[in] in_cfg
+ * GPIO input configuration
+ * \return Return code of operation
+ */
+static gpio_res_e input_set_cfg_irq(gpio_id_t id, const gpio_in_cfg_t *in_cfg);
+
+/** \brief Initialize GPIOs interrupts */
+static void input_init_irq(void);
+
+/**
+ * \brief Allocate a interrupt number to a GPIO
+ * \param id
+ * Id of the GPIO
+ * \param[out] it
+ * Returned interrupt number
+ * \return Return code of operation
+ */
+static gpio_res_e alloc_it(gpio_id_t id, gpio_it_t *it);
+
+/**
+ * \brief Free a interrupt number allocated to a GPIO
+ * \param id
+ * Id of the GPIO
+ * \param[out] it
+ * Freed interrupt number
+ * \return Return code of operation
+ */
+static void free_it(gpio_id_t id, gpio_it_t *it);
+
+/**
+ * \brief Check if the given interrupt number is already in use or if it is free
+ * \param it
+ * interrupt number to check
+ * \return True if the given interrupt number is free ; False otherwise (meaning it is already in use)
+ */
+static bool is_it_free(gpio_it_t it);
+
+/** \brief function called when a GPIO interrupt is raised. Used to generate the appropriate GPIO event */
+static void gpio_event_handle(void);
+
+/** \brief Enable GPIO clock */
+static inline void enable_gpio_clock(void)
+{
+#if (_SILICON_LABS_32B_SERIES == 1)
+ CMU->HFBUSCLKEN0 |= CMU_HFBUSCLKEN0_GPIO;
+#elif (_SILICON_LABS_32B_SERIES == 2) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 1)
+ CMU->CLKEN0_SET = CMU_CLKEN0_GPIO;
+#endif
+}
+
+gpio_res_e Gpio_init(void)
+{
+ gpio_id_t id;
+ const gpio_in_cfg_t in_cfg =
+ {
+ .event_cb = NULL,
+ .event_cfg = GPIO_IN_EVENT_NONE,
+ .in_mode_cfg = GPIO_IN_DISABLED
+ };
+
+ if (m_initialized)
+ {
+ /* return if GPIO initialization has already been performed */
+ return GPIO_RES_OK;
+ }
+ if (!check_pins())
+ {
+ return GPIO_RES_INVALID_PIN;
+ }
+
+ Sys_enterCriticalSection();
+
+ enable_gpio_clock();
+ /* Configure each mapped GPIOs to a default configuration */
+ for (id = 0; id < BOARD_GPIO_NUMBER; id++)
+ {
+ input_set_cfg_mode(id, &in_cfg);
+ /* set interrupt number as unused/free */
+ m_id_to_cfg_map[id].it = IT_FREE;
+ /* Store direction and part of configuration that is used internally */
+ m_id_to_event_cb_map[id] = in_cfg.event_cb;
+ m_id_to_cfg_map[id].direction = DIR_INPUT;
+ m_id_to_cfg_map[id].event_cfg = in_cfg.event_cfg;
+ }
+ input_init_irq();
+
+ Sys_exitCriticalSection();
+
+ m_initialized = true;
+
+ return GPIO_RES_OK;
+}
+
+gpio_res_e Gpio_inputSetCfg(gpio_id_t id, const gpio_in_cfg_t *in_cfg)
+{
+ gpio_res_e res;
+
+ if (!m_initialized)
+ {
+ return GPIO_RES_UNINITIALIZED;
+ }
+ if (id >= BOARD_GPIO_NUMBER || in_cfg == NULL)
+ {
+ return GPIO_RES_INVALID_PARAM;
+ }
+
+ Sys_enterCriticalSection();
+
+ input_set_cfg_mode(id, in_cfg);
+ res = input_set_cfg_irq(id, in_cfg);
+ if (res != GPIO_RES_OK)
+ {
+ Sys_exitCriticalSection();
+ return res;
+ }
+ /* Store direction and part of configuration that is used internally */
+ m_id_to_event_cb_map[id] = in_cfg->event_cb;
+ m_id_to_cfg_map[id].direction = DIR_INPUT;
+ m_id_to_cfg_map[id].event_cfg = in_cfg->event_cfg;
+
+ Sys_exitCriticalSection();
+
+ return GPIO_RES_OK;
+}
+
+gpio_res_e Gpio_inputRead(gpio_id_t id, gpio_level_e *level)
+{
+ gpio_port_t port;
+ gpio_pin_t pin;
+ bool read_val;
+
+ if (!m_initialized)
+ {
+ return GPIO_RES_UNINITIALIZED;
+ }
+ if (id >= BOARD_GPIO_NUMBER || level == NULL)
+ {
+ return GPIO_RES_INVALID_PARAM;
+ }
+ if (m_id_to_cfg_map[id].direction != DIR_INPUT)
+ {
+ return GPIO_RES_INVALID_DIRECTION;
+ }
+
+ Gpio_getPin(id, &port, &pin);
+ read_val = (GPIO_PinInGet(port, pin) != 0);
+ *level = read_val ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW;
+
+ return GPIO_RES_OK;
+}
+
+gpio_res_e Gpio_outputSetCfg(gpio_id_t id, const gpio_out_cfg_t *out_cfg)
+{
+ GPIO_Mode_TypeDef mode;
+ gpio_port_t port;
+ gpio_pin_t pin;
+
+ if (!m_initialized)
+ {
+ return GPIO_RES_UNINITIALIZED;
+ }
+ if (id >= BOARD_GPIO_NUMBER || out_cfg == NULL)
+ {
+ return GPIO_RES_INVALID_PARAM;
+ }
+
+ /*
+ * convert board independant operating mode enum,
+ * to board specific operating mode enum
+ */
+ switch (out_cfg->out_mode_cfg)
+ {
+ case GPIO_OUT_MODE_PUSH_PULL:
+ mode = gpioModePushPull;
+ break;
+ case GPIO_OUT_MODE_OPEN_DRAIN:
+ mode = gpioModeWiredAndFilter;
+ break;
+ case GPIO_OUT_MODE_OPEN_DRAIN_WITH_PULL_UP:
+ mode = gpioModeWiredAndPullUpFilter;
+ break;
+ default:
+ return GPIO_RES_INVALID_PARAM;
+ }
+
+ Sys_enterCriticalSection();
+
+ Gpio_getPin(id, &port, &pin);
+ GPIO_PinModeSet(port, pin, mode, (out_cfg->level_default != GPIO_LEVEL_LOW));
+ /* Store direction */
+ m_id_to_cfg_map[id].direction = DIR_OUTPUT;
+
+ Sys_exitCriticalSection();
+
+ return GPIO_RES_OK;
+}
+
+gpio_res_e Gpio_outputWrite(gpio_id_t id, gpio_level_e level)
+{
+ gpio_port_t port;
+ gpio_pin_t pin;
+
+ if (!m_initialized)
+ {
+ return GPIO_RES_UNINITIALIZED;
+ }
+ if (id >= BOARD_GPIO_NUMBER)
+ {
+ return GPIO_RES_INVALID_PARAM;
+ }
+ if (m_id_to_cfg_map[id].direction != DIR_OUTPUT)
+ {
+ return GPIO_RES_INVALID_DIRECTION;
+ }
+
+ Gpio_getPin(id, &port, &pin);
+ if (level == GPIO_LEVEL_HIGH)
+ {
+ GPIO_PinOutSet(port, pin);
+ }
+ else
+ {
+ GPIO_PinOutClear(port, pin);
+ }
+
+ return GPIO_RES_OK;
+}
+
+gpio_res_e Gpio_outputToggle(gpio_id_t id)
+{
+ gpio_port_t port;
+ gpio_pin_t pin;
+
+ if (!m_initialized)
+ {
+ return GPIO_RES_UNINITIALIZED;
+ }
+ if (id >= BOARD_GPIO_NUMBER)
+ {
+ return GPIO_RES_INVALID_PARAM;
+ }
+ if (m_id_to_cfg_map[id].direction != DIR_OUTPUT)
+ {
+ return GPIO_RES_INVALID_DIRECTION;
+ }
+
+ Gpio_getPin(id, &port, &pin);
+ GPIO_PinOutToggle(port, pin);
+
+ return GPIO_RES_OK;
+}
+
+gpio_res_e Gpio_outputRead(gpio_id_t id, gpio_level_e *level)
+{
+ gpio_port_t port;
+ gpio_pin_t pin;
+ bool read_val;
+
+ if (!m_initialized)
+ {
+ return GPIO_RES_UNINITIALIZED;
+ }
+ if (id >= BOARD_GPIO_NUMBER || level == NULL)
+ {
+ return GPIO_RES_INVALID_PARAM;
+ }
+ if (m_id_to_cfg_map[id].direction != DIR_OUTPUT)
+ {
+ return GPIO_RES_INVALID_DIRECTION;
+ }
+
+ Gpio_getPin(id, &port, &pin);
+ read_val = GPIO_PinOutGet(port, pin) != 0;
+ *level = read_val ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW;
+
+ return GPIO_RES_OK;
+}
+
+gpio_res_e Gpio_getPin(gpio_id_t id, gpio_port_t *port, gpio_pin_t *pin)
+{
+ if (id >= BOARD_GPIO_NUMBER)
+ {
+ return GPIO_RES_INVALID_PARAM;
+ }
+
+ if (port)
+ {
+ *port = m_id_to_pin_map[id].port;
+ }
+ if (pin)
+ {
+ *pin = m_id_to_pin_map[id].pin;
+ }
+
+ return GPIO_RES_OK;
+}
+
+uint8_t Gpio_getNumber(void)
+{
+ return BOARD_GPIO_NUMBER;
+}
+
+static bool check_pins(void)
+{
+ gpio_id_t id;
+ gpio_port_t port;
+ gpio_pin_t pin;
+
+ for (id = 0; id < BOARD_GPIO_NUMBER; id++)
+ {
+ Gpio_getPin(id, &port, &pin);
+ if (!GPIO_PORT_PIN_VALID(port, pin))
+ {
+ return false;
+ }
+ }
+ return true;
+}
+
+static void input_set_cfg_mode(gpio_id_t id, const gpio_in_cfg_t *in_cfg)
+{
+ gpio_port_t port;
+ gpio_pin_t pin;
+ GPIO_Mode_TypeDef efr_mode;
+ bool out;
+
+ /*
+ * convert board independant mode enum,
+ * to board specific mode enum
+ */
+ switch (in_cfg->in_mode_cfg)
+ {
+ case GPIO_IN_DISABLED:
+ efr_mode = gpioModeDisabled;
+ /* set "out" to 0 to disable pull-up */
+ out = false;
+ break;
+ case GPIO_IN_PULL_NONE:
+ efr_mode = gpioModeInput;
+ /* set "out" to 1 to enable filter */
+ out = true;
+ break;
+ case GPIO_IN_PULL_DOWN:
+ efr_mode = gpioModeInputPullFilter;
+ /* "out" determines pull direction (0 -> pull-down) */
+ out = false;
+ break;
+ case GPIO_IN_PULL_UP:
+ efr_mode = gpioModeInputPullFilter;
+ /* "out" determines pull direction (1 -> pull-up) */
+ out = true;
+ break;
+ }
+ Gpio_getPin(id, &port, &pin);
+ GPIO_PinModeSet(port, pin, efr_mode, out);
+}
+
+static gpio_res_e input_set_cfg_irq(gpio_id_t id, const gpio_in_cfg_t *in_cfg)
+{
+ gpio_port_t port;
+ gpio_pin_t pin;
+ gpio_it_t it;
+ gpio_res_e res;
+
+ /* if no event on this GPIO, ... */
+ if (in_cfg->event_cfg == GPIO_IN_EVENT_NONE)
+ {
+ /* ...then free/unalloc its interrupt number */
+ free_it(id, &it);
+ }
+ /* else if any event on this GPIO, ... */
+ else
+ {
+ /* ...then allocate an interrupt number to the GPIO */
+ res = alloc_it(id, &it);
+ if (res != GPIO_RES_OK)
+ {
+ return res;
+ }
+ }
+
+ /* update the interrupt registers, if got a valid interrupt number */
+ if (it != IT_FREE)
+ {
+ Gpio_getPin(id, &port, &pin);
+ GPIO_ExtIntConfig(port,
+ pin,
+ it,
+ IS_RISING_EDGE(in_cfg->event_cfg),
+ IS_FALLING_EDGE(in_cfg->event_cfg),
+ in_cfg->event_cfg != GPIO_IN_EVENT_NONE);
+ }
+ return GPIO_RES_OK;
+}
+
+static void input_init_irq(void)
+{
+ GPIO_IntDisable(_GPIO_IEN_MASK & 0x0000FFFF);
+ lib_system->enableAppIrq(true, GPIO_EVEN_IRQn, APP_LIB_SYSTEM_IRQ_PRIO_LO, gpio_event_handle);
+ lib_system->enableAppIrq(true, GPIO_ODD_IRQn, APP_LIB_SYSTEM_IRQ_PRIO_LO, gpio_event_handle);
+ lib_system->clearPendingFastAppIrq(GPIO_EVEN_IRQn);
+ lib_system->clearPendingFastAppIrq(GPIO_ODD_IRQn);
+}
+
+static gpio_res_e alloc_it(gpio_id_t id, gpio_it_t *it)
+{
+ gpio_pin_t pin;
+ gpio_it_t it_tmp, it_min, it_max;
+ bool it_found = false;
+
+ /*
+ * if an interrupt number was already allocated for this GPIO,
+ * then just return it.
+ */
+ it_tmp = m_id_to_cfg_map[id].it;
+ if (it_tmp != IT_FREE)
+ {
+ *it = it_tmp;
+ return GPIO_RES_OK;
+ }
+
+ /*
+ * Refer to chapter "Edge Interrupt Generation" in the MCU reference manual
+ * for an explanation about the interrupt number allocation mechanism
+ *
+ * Example:
+ * GPIO pin = Px5. in group Px[4:7] -> so one interrupt in the EXTI[4-7] interrupt group can be used.
+ */
+ Gpio_getPin(id, NULL, &pin);
+ it_min = SL_FLOOR(pin, 4);
+ it_max = SL_FLOOR(pin, 4) + 3;
+
+ /* Browse the interrupt group, and allocate the first interrupt that is free */
+ for (it_tmp = it_min; it_tmp <= it_max; it_tmp++)
+ {
+ if (is_it_free(it_tmp))
+ {
+ m_id_to_cfg_map[id].it = it_tmp;
+ *it = it_tmp;
+ it_found = true;
+ break;
+ }
+ }
+ return it_found ? GPIO_RES_OK : GPIO_RES_NO_FREE_IT;
+}
+
+static void free_it(gpio_id_t id, gpio_it_t *it)
+{
+ *it = m_id_to_cfg_map[id].it;
+ m_id_to_cfg_map[id].it = IT_FREE;
+}
+
+static bool is_it_free(gpio_it_t it)
+{
+ gpio_id_t id;
+
+ for (id = 0; id < BOARD_GPIO_NUMBER; id++)
+ {
+ if (m_id_to_cfg_map[id].it == it)
+ {
+ return false;
+ }
+ }
+ return true;
+}
+
+static void gpio_event_handle(void)
+{
+ gpio_id_t id;
+ gpio_it_t it;
+ bool it_raised;
+ gpio_level_e level;
+ gpio_in_event_cb_f event_cb;
+ gpio_in_event_e event_cfg;
+ gpio_in_event_e event;
+
+ /* for each GPIO */
+ for (id = 0; id < BOARD_GPIO_NUMBER; id++)
+ {
+ /* get the interrupt number of the GPIO */
+ it = m_id_to_cfg_map[id].it;
+ if (it == IT_FREE)
+ {
+ continue;
+ }
+
+ /* check if the GPIO interrupt flag is set */
+ it_raised = (GPIO_IntGet() & (((uint32_t) 1) << it)) != 0;
+ if (it_raised)
+ {
+ Gpio_inputRead(id, &level);
+ /* get stored/internal config */
+ event_cb = m_id_to_event_cb_map[id];
+ event_cfg = m_id_to_cfg_map[id].event_cfg;
+ /*
+ * Invoke user handler only if the pin level
+ * matches its polarity configuration.
+ */
+ if (event_cb &&
+ ((IS_RISING_EDGE(event_cfg) && IS_FALLING_EDGE(event_cfg)) ||
+ (level == GPIO_LEVEL_HIGH && IS_RISING_EDGE(event_cfg)) ||
+ (level == GPIO_LEVEL_LOW && IS_FALLING_EDGE(event_cfg))))
+ {
+ event = (level == GPIO_LEVEL_HIGH) ? GPIO_IN_EVENT_RISING_EDGE : GPIO_IN_EVENT_FALLING_EDGE;
+ event_cb(id, event);
+ }
+
+ /* clear the GPIO interrupt flag */
+ GPIO_IntClear((uint32_t) 1 << it);
+ }
+ }
+}
+
+#endif // BOARD_GPIO_PIN_LIST
diff --git a/mcu/efr/efr32/hal/i2c/i2c_common.h b/mcu/efr/efr32/hal/i2c/i2c_common.h
new file mode 100644
index 00000000..da4aaf62
--- /dev/null
+++ b/mcu/efr/efr32/hal/i2c/i2c_common.h
@@ -0,0 +1,46 @@
+/* Copyright 2023 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+#ifndef I2C_COMMON_H_
+#define I2C_COMMON_H_
+
+
+#define USE_I2C1
+
+/** Internal transfer description */
+typedef struct
+{
+ i2c_xfer_t * client_xfer; //< Transfer asked by client
+ i2c_on_transfer_done_cb_f cb; //< Callback to call at end of transfer
+ i2c_res_e res; //< Result of I2C transfer
+ uint8_t pos; //< Read or write position
+ bool free; //< False if transfer ongoing
+ bool write_done; //< Is write before read done
+ bool done; //< Is transfer done
+ bool mstop_detected; //< Is MSTOP interrupt detected
+} internal_xfer_desc;
+
+/** I2C state machine state */
+typedef enum
+{
+ I2C_SM_ST_UNINITIALIZED = 0,
+ I2C_SM_ST_IDLE,
+ I2C_SM_ST_START,
+ I2C_SM_ST_WRITE_ADDR,
+ I2C_SM_ST_WRITE_DATA,
+ I2C_SM_ST_READ,
+ I2C_SM_ST_STOP
+} i2c_sm_state_e;
+
+/** I2C state machine commands */
+typedef enum
+{
+ I2C_SM_CMD_ABORT = 0,
+ I2C_SM_CMD_START,
+ I2C_SM_CMD_NEXT
+} i2c_sm_command_e;
+
+
+#endif //I2C_COMMON_H_
\ No newline at end of file
diff --git a/mcu/efr/efr32/hal/i2c/i2c_series1.c b/mcu/efr/efr32/hal/i2c/i2c_series1.c
new file mode 100644
index 00000000..ac93dd07
--- /dev/null
+++ b/mcu/efr/efr32/hal/i2c/i2c_series1.c
@@ -0,0 +1,684 @@
+/* Copyright 2020 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+#include
+#include
+#include
+
+#include "board.h"
+#include "api.h"
+
+#include "mcu.h"
+#include "i2c.h"
+#include "i2c_common.h"
+
+#include "vendor/em_cmu.h" // For CMU_ClockFreqGet(), cmuClock_HFPER
+
+/** Declare the interrupt handler */
+void I2C_IRQHandler(void);
+
+#if defined(USE_I2C1)
+#define I2C_IRQn I2C1_IRQn
+#define I2C_DEV I2C1
+#define I2C_MODULE 1
+#define I2C_HFPERCLKEN0_BIT CMU_HFPERCLKEN0_I2C1
+
+#elif defined(USE_I2C0)
+#define I2C_IRQn I2C0_IRQn
+#define I2C_DEV I2C0
+#define I2C_MODULE 0
+#define I2C_HFPERCLKEN0_BIT CMU_HFPERCLKEN0_I2C0
+
+#else
+#error USE_I2C0 or USE_I2C1 must be defined
+#endif
+
+
+/**
+ * Time taken to transfer one bit on I2C with 50% margin. This value depends
+ * on the bus speed.
+ * This timeout is necessary because I2C peripheral doesn't generate any errors
+ * and hangs when the line is low (disconnected slave, no pull-up one the line).
+ * In asynchronous mode, use I2C_status to check if transfer is finished.
+ */
+static uint32_t m_i2c_bit_timeout_ns;
+
+/** Is I2C module initialized */
+static volatile i2c_sm_state_e m_state = I2C_SM_ST_UNINITIALIZED;
+
+/** Current tansfer ongoing. Only one transfer supported at a time */
+static volatile internal_xfer_desc m_current_xfer;
+
+
+/**
+ * \brief Configure I2C gpios
+ * \param pullup
+ * Activate internal EFR32 pullup on SDA and SCL
+ */
+static void configure_gpios(bool pullup)
+{
+ //Configure SCL GPIO
+ hal_gpio_set(BOARD_I2C_GPIO_PORT, BOARD_I2C_SCL_PIN);
+ hal_gpio_set_mode(BOARD_I2C_GPIO_PORT,
+ BOARD_I2C_SCL_PIN,
+ pullup ? GPIO_MODE_OUT_OD_PU :
+ GPIO_MODE_OUT_OD_NOPULL);
+
+ //Configure SDA GPIO
+ hal_gpio_set(BOARD_I2C_GPIO_PORT, BOARD_I2C_SDA_PIN);
+ hal_gpio_set_mode(BOARD_I2C_GPIO_PORT,
+ BOARD_I2C_SDA_PIN,
+ pullup ? GPIO_MODE_OUT_OD_PU :
+ GPIO_MODE_OUT_OD_NOPULL);
+
+ // Choose routing of SDA and SCL GPIO to the I2C peripheral
+ I2C_DEV->ROUTELOC0 = BOARD_I2C_ROUTELOC_SDALOC | BOARD_I2C_ROUTELOC_SCLLOC;
+
+ // Enable routing of SDA and SCL to the I2C peripheral
+ I2C_DEV->ROUTEPEN = I2C_ROUTEPEN_SDAPEN | I2C_ROUTEPEN_SCLPEN;
+}
+
+/**
+ * \brief Release I2C gpios (SDA and SCL)
+ */
+static void release_gpios(void)
+{
+ // Disable routing of SDA and SCL to the I2C peripheral
+ I2C_DEV->ROUTEPEN = _I2C_ROUTEPEN_RESETVALUE;
+ I2C_DEV->ROUTELOC0 = _I2C_ROUTELOC0_RESETVALUE;
+
+ // Restore SDA GPIO
+ hal_gpio_set_mode(BOARD_I2C_GPIO_PORT,
+ BOARD_I2C_SDA_PIN,
+ GPIO_MODE_DISABLED);
+ hal_gpio_clear(BOARD_I2C_GPIO_PORT, BOARD_I2C_SDA_PIN);
+
+ // Restore SCL GPIO
+ hal_gpio_set_mode(BOARD_I2C_GPIO_PORT,
+ BOARD_I2C_SCL_PIN,
+ GPIO_MODE_DISABLED);
+ hal_gpio_clear(BOARD_I2C_GPIO_PORT, BOARD_I2C_SCL_PIN);
+}
+
+/**
+ * \brief Enable or disable I2C peripheral clock
+ * \param enable
+ * True to enable clock, false to disable
+ */
+static void enable_clock(bool enable)
+{
+ if (enable)
+ {
+ // Turn on clock to the I2C peripheral for xg12/13
+ CMU->HFPERCLKEN0 |= I2C_HFPERCLKEN0_BIT;
+ }
+ else
+ {
+ // Turn off clock to the I2C peripheral for xg12/13
+ CMU->HFPERCLKEN0 &= ~I2C_HFPERCLKEN0_BIT;
+ }
+}
+
+/**
+ * \brief Enable or disable I2C peripheral interrupts
+ * \param enable
+ * True to enable NVIC IRQ for I2C, false to disable
+ * \param clear
+ * True to clear pending I2C peripheral interrupts, false to disable
+ * \note IRQ can only be enabled when clocks are enabled
+ */
+static void enable_interrupts(bool enable, bool clear)
+{
+ if (clear)
+ {
+ // Clear all I2C interrupt flags
+ // for xg12/13
+ I2C_DEV->IFC = _I2C_IFC_MASK;
+ }
+
+ if (enable)
+ {
+ // Enable START, RXDATAV, ACK, NACK and MSTOP interrupts
+ I2C_DEV->IEN = I2C_IEN_START | I2C_IEN_RXDATAV |
+ I2C_IEN_ACK | I2C_IEN_NACK | I2C_IEN_MSTOP;
+ }
+ else
+ {
+ // Disable all I2C interrupts
+ I2C_DEV->IEN = _I2C_IEN_RESETVALUE;
+ }
+}
+
+/**
+ * \brief Set the frequency of the I2C module
+ * \param freq
+ * Frequency requested in Hz
+ * \return True if successful set, false if not available
+ */
+static bool set_frequency(uint32_t f_scl)
+{
+ //Clock source for I2C interface
+ // Read HFPERCLK frequency
+ uint32_t f_i2cclk = CMU_ClockFreqGet(cmuClock_HFPER);
+
+ // Calculate required divisor
+ //
+ // div = (f_i2cclk / f_scl - 8) / (n_low + n_high) - 1
+ //
+ // , where
+ // f_i2cclk: I2C clock source frequency, in Hz
+ // f_scl: Desired SCL frequency, in Hz
+ // n_low: low period counter, 4 for standard clock
+ // n_high: high period counter, 4 for standard clock
+ if (f_scl == 0)
+ {
+ // DC SCL not supported
+ return false;
+ }
+ uint32_t div = f_i2cclk / f_scl;
+ if (div < (1 * 8 + 8))
+ {
+ // Requested SCL clock frequency too fast
+ return false;
+ }
+ div = (div - 8) / 8 - 1;
+ if (div > (_I2C_CLKDIV_DIV_MASK >> _I2C_CLKDIV_DIV_SHIFT))
+ {
+ // Requested SCL clock frequency too slow
+ return false;
+ }
+
+ // Set I2C SCL frequency
+ I2C_DEV->CLKDIV = div;
+
+ return true;
+}
+
+/**
+ * \brief I2C state machine, also called from interrupts
+ * \param state
+ * New state to enter
+ */
+static void i2c_state_machine(i2c_sm_command_e command)
+{
+ bool error = false;
+ bool call_cb = false;
+ i2c_xfer_t * client_xfer = m_current_xfer.client_xfer;
+ uint8_t dev_state;
+
+ // Turn on clock while in state machine
+ enable_clock(true);
+
+ dev_state = I2C_DEV->STATE & (_I2C_STATE_STATE_MASK |
+ _I2C_STATE_NACKED_MASK);
+
+ // Disable interrupts while in state machine
+ enable_interrupts(false, false);
+
+ if (command == I2C_SM_CMD_ABORT)
+ {
+ // Force transfer abort
+ error = true;
+ }
+ else if ((command == I2C_SM_CMD_START) &&
+ (m_state == I2C_SM_ST_IDLE) &&
+ (dev_state == I2C_STATE_STATE_IDLE))
+ {
+ // Start transfer, transmit START condition
+
+ // Update current state
+ m_state = I2C_SM_ST_START;
+
+ // Clear pending interrupts just in case
+ enable_interrupts(false, true);
+
+ // Transmit START condition
+ I2C_DEV->CMD = I2C_CMD_START;
+ }
+ else if ((command == I2C_SM_CMD_NEXT) &&
+ (m_state == I2C_SM_ST_START) &&
+ (dev_state == I2C_STATE_STATE_START))
+ {
+ // Transmit address and R/W bit, or STOP condition if nothing to do
+
+ uint8_t addr = client_xfer->address << 1;
+
+ if (!m_current_xfer.write_done && (client_xfer->write_size > 0))
+ {
+ // Update current state
+ m_state = I2C_SM_ST_WRITE_ADDR;
+
+ // Write address and R/W bit = 0 to transmit buffer, to transmit it
+ I2C_DEV->TXDATA = addr | 0x00;
+ }
+ else if (client_xfer->read_size > 0)
+ {
+ // Update current state
+ m_state = I2C_SM_ST_READ;
+
+ // Flush receive buffer and shift register
+ while (I2C_DEV->STATUS & I2C_STATUS_RXDATAV)
+ {
+ I2C_DEV->RXDATA;
+ }
+
+ // Write address and R/W bit = 1 to transmit buffer, to transmit it
+ I2C_DEV->TXDATA = addr | 0x01;
+ }
+ else
+ {
+ // Update current state
+ m_state = I2C_SM_ST_STOP;
+
+ // Nothing to transmit or receive, transmit a STOP condition
+ I2C_DEV->CMD = I2C_CMD_STOP;
+ }
+ }
+ else if ((command == I2C_SM_CMD_NEXT) && (m_state == I2C_SM_ST_WRITE_ADDR))
+ {
+ // Check address ACK, transmit first byte of data
+
+ if (dev_state == I2C_STATE_STATE_ADDR)
+ {
+ // Address transmitted, wait for ACK or NACK
+ }
+ else if (dev_state == (I2C_STATE_STATE_ADDRACK | I2C_STATE_NACKED))
+ {
+ // Address not ACKed
+ m_current_xfer.res = I2C_RES_ANACK;
+
+ // Update current state
+ m_state = I2C_SM_ST_STOP;
+
+ // Transmit STOP condition
+ I2C_DEV->CMD = I2C_CMD_STOP;
+ }
+ else if (dev_state == I2C_STATE_STATE_ADDRACK)
+ {
+ // Address ACKed, update current state
+ m_state = I2C_SM_ST_WRITE_DATA;
+
+ // Write first byte of data to transmit buffer
+ I2C_DEV->TXDATA = client_xfer->write_ptr[m_current_xfer.pos++];
+ }
+ else
+ {
+ // Invalid state
+ error = true;
+ }
+ }
+ else if ((command == I2C_SM_CMD_NEXT) && (m_state == I2C_SM_ST_WRITE_DATA))
+ {
+ // Check data ACK, transmit next byte of data
+
+ if (dev_state == I2C_STATE_STATE_DATA)
+ {
+ // Data transmitted, wait for ACK or NACK
+ }
+ else if (dev_state == (I2C_STATE_STATE_DATAACK | I2C_STATE_NACKED))
+ {
+ // Data not ACKed
+ m_current_xfer.res = I2C_RES_DNACK;
+
+ // Update current state
+ m_state = I2C_SM_ST_STOP;
+
+ // Transmit STOP condition
+ I2C_DEV->CMD = I2C_CMD_STOP;
+ }
+ else if (dev_state == I2C_STATE_STATE_DATAACK)
+ {
+ // Data ACKed
+ if (m_current_xfer.pos < client_xfer->write_size)
+ {
+ // Write next byte of data to transmit buffer
+ I2C_DEV->TXDATA = client_xfer->write_ptr[m_current_xfer.pos++];
+ }
+ else if (client_xfer->read_size > 0)
+ {
+ // Mark write done and reset read position
+ m_current_xfer.write_done = true;
+ m_current_xfer.pos = 0;
+
+ // Update current state
+ m_state = I2C_SM_ST_START;
+
+ // Some bytes to read, transmit repeated START condition
+ I2C_DEV->CMD = I2C_CMD_START;
+ }
+ else
+ {
+ // No more bytes to write or read
+ m_current_xfer.res = I2C_RES_OK;
+
+ // Update current state
+ m_state = I2C_SM_ST_STOP;
+
+ // Transmit STOP condition
+ I2C_DEV->CMD = I2C_CMD_STOP;
+ }
+ }
+ else
+ {
+ // Invalid state
+ error = true;
+ }
+ }
+ else if ((command == I2C_SM_CMD_NEXT) && (m_state == I2C_SM_ST_READ))
+ {
+ // Check address ACK or read data
+
+ if (dev_state == I2C_STATE_STATE_ADDR)
+ {
+ // Address transmitted, wait for ACK or NACK
+ }
+ else if (dev_state == (I2C_STATE_STATE_ADDRACK | I2C_STATE_NACKED))
+ {
+ // Address not ACKed
+ m_current_xfer.res = I2C_RES_ANACK;
+
+ // Update current state
+ m_state = I2C_SM_ST_STOP;
+
+ // Transmit STOP condition
+ I2C_DEV->CMD = I2C_CMD_STOP;
+ }
+ else if (dev_state == I2C_STATE_STATE_ADDRACK)
+ {
+ // Address ACKed, perform a dummy read to start reception
+ I2C_DEV->RXDATA;
+ }
+ else if (dev_state == I2C_STATE_STATE_DATA)
+ {
+ // Data received, transmit ACK or NACK
+ I2C_DEV->CMD = ((client_xfer->read_size - m_current_xfer.pos) > 1) ?
+ I2C_CMD_ACK : I2C_CMD_NACK;
+ }
+ else if (dev_state == I2C_STATE_STATE_DATAACK)
+ {
+ // Read received byte
+ client_xfer->read_ptr[m_current_xfer.pos++] = I2C_DEV->RXDATA;
+
+ // Data ACK or NACK sent
+ if (m_current_xfer.pos == client_xfer->read_size)
+ {
+ // Last byte received
+ m_current_xfer.res = I2C_RES_OK;
+
+ // Update current state
+ m_state = I2C_SM_ST_STOP;
+
+ // Transmit STOP condition
+ I2C_DEV->CMD = I2C_CMD_STOP;
+ }
+ }
+ else
+ {
+ // Invalid state
+ error = true;
+ }
+ }
+ else if ((command == I2C_SM_CMD_NEXT) && (m_state == I2C_SM_ST_STOP))
+ {
+ // STOP has been served. Or is it? What is the opinion of HW?
+ // Unfortunately cannot assume that dev_state would be IDLE when
+ // MSTOP interrupt is generated. It is still quite often DATAACK.
+ // No interrupts will occur after MSTOP, thus i2c bus would hang.
+ // To overcome this problem mstop_detected flag is passed from
+ // interrupt handler so that state machine can be set to IDLE
+ // state and complete transfer successfully.
+ if ((dev_state == I2C_STATE_STATE_IDLE) || (m_current_xfer.mstop_detected))
+ {
+ // I2C is idle again
+ m_state = I2C_SM_ST_IDLE;
+
+ // Call callback
+ call_cb = true;
+ }
+ else
+ {
+ // Invalid state
+ error = true;
+ }
+ }
+ else
+ {
+ // Invalid state, abort transfer
+ error = true;
+ }
+
+ if (error)
+ {
+ // I2C is idle again
+ m_state = I2C_SM_ST_IDLE;
+
+ if (!m_current_xfer.free)
+ {
+ // Error occurred, call callback with error code I2C_RES_BUS_HANG
+ m_current_xfer.res = I2C_RES_BUS_HANG;
+ call_cb = true;
+ }
+
+ // Something went wrong, abort transfer
+ I2C_DEV->CMD = I2C_CMD_ABORT;
+ }
+
+ if (call_cb && !m_current_xfer.free)
+ {
+ // Free the transfer before calling client callback, to chain requests
+ m_current_xfer.free = true;
+
+ // If not blocking transfer, call the client callback
+ // NOTE: This may set m_state != I2C_SM_ST_IDLE
+ if (m_current_xfer.cb != NULL)
+ {
+ m_current_xfer.cb(m_current_xfer.res, client_xfer);
+ }
+ else
+ {
+ // If blocking call, set the transfer completed flag
+ m_current_xfer.done = true;
+ }
+ }
+
+ if (m_state == I2C_SM_ST_IDLE)
+ {
+ // I2C is idle, so turn off clock to the I2C peripheral
+ enable_clock(false);
+ }
+ else
+ {
+ // I2C is running, enable interrupts and keep pending interrupt flags,
+ // as the I2C operation may have completed already when we get here
+ enable_interrupts(true, false);
+ }
+}
+
+i2c_res_e I2C_init(i2c_conf_t * conf_p)
+{
+ if (m_state != I2C_SM_ST_UNINITIALIZED)
+ {
+ return I2C_RES_ALREADY_INITIALIZED;
+ }
+
+ // Mark I2C driver as initialized
+ m_state = I2C_SM_ST_IDLE;
+
+ // Turn on clock to the I2C peripheral during configuration
+ enable_clock(true);
+
+ // Disable I2C peripheral interrupts, clear pending interrupt flags
+ enable_interrupts(false, true);
+
+ // Enable I2C IRQ
+ Sys_clearFastAppIrq(I2C_IRQn);
+ Sys_enableFastAppIrq(I2C_IRQn,
+ APP_LIB_SYSTEM_IRQ_PRIO_HI,
+ I2C_IRQHandler);
+
+ // Enable I2C peripheral: arbitration disabled, 4:4 clock periods
+ I2C_DEV->CTRL = I2C_CTRL_EN | I2C_CTRL_ARBDIS |
+ I2C_CTRL_CLHR_STANDARD | I2C_CTRL_TXBIL_EMPTY;
+
+ // Configure SCL frequency
+ if (!set_frequency(conf_p->clock))
+ {
+ // Invalid SCL frequency, return peripheral to the reset state
+ I2C_close();
+ return I2C_RES_INVALID_CONFIG;
+ }
+ // Issue an ABORT command to make sure the peripheral is in a known state
+ I2C_DEV->CMD = I2C_CMD_ABORT;
+
+ // Configure the GPIOs
+ configure_gpios(conf_p->pullup);
+
+ // Configuration done, turn off clock to the I2C peripheral
+ enable_clock(false);
+
+ /* Add 50% margin to timeout calculation */
+ m_i2c_bit_timeout_ns = 1500000000 / conf_p->clock;
+
+ m_current_xfer.free = true;
+
+ return I2C_RES_OK;
+}
+
+i2c_res_e I2C_close(void)
+{
+ if (m_state == I2C_SM_ST_UNINITIALIZED)
+ {
+ return I2C_RES_NOT_INITIALIZED;
+ }
+
+ m_state = I2C_SM_ST_UNINITIALIZED;
+
+ // Turn on clock to the I2C peripheral during configuration
+ enable_clock(true);
+
+ // Disable I2C peripheral interrupts, clear pending interrupt flags
+ enable_interrupts(false, true);
+
+ // Disable I2C IRQ
+ Sys_disableAppIrq(I2C_IRQn);
+
+ // Issue an ABORT command to make sure the peripheral is in a known state
+ I2C_DEV->CMD = I2C_CMD_ABORT;
+
+ // Set all gpios as default configuration
+ release_gpios();
+
+ // Disable I2C peripheral
+ I2C_DEV->CTRL = _I2C_CTRL_RESETVALUE;
+
+ // Configuration done, turn off clock to the I2C peripheral
+ enable_clock(false);
+
+ return I2C_RES_OK;
+}
+
+i2c_res_e I2C_transfer(i2c_xfer_t * xfer_p, i2c_on_transfer_done_cb_f cb)
+{
+ if (m_state == I2C_SM_ST_UNINITIALIZED)
+ {
+ return I2C_RES_NOT_INITIALIZED;
+ }
+
+ // Check if a transfer is already ongoing
+ if (!m_current_xfer.free)
+ {
+ return I2C_RES_BUSY;
+ }
+
+ // Check transfer
+ if (((xfer_p->read_ptr != NULL) && (xfer_p->read_size == 0)) ||
+ ((xfer_p->read_ptr == NULL) && (xfer_p->read_size != 0)) ||
+ ((xfer_p->write_ptr != NULL) && (xfer_p->write_size == 0)) ||
+ ((xfer_p->write_ptr == NULL) && (xfer_p->write_size != 0)))
+ {
+ return I2C_RES_INVALID_XFER;
+ }
+
+ // Setup the transfer
+ m_current_xfer.client_xfer = xfer_p;
+ m_current_xfer.cb = cb;
+ m_current_xfer.res = I2C_RES_OK;
+ m_current_xfer.pos = 0;
+ m_current_xfer.free = false;
+ m_current_xfer.write_done = false;
+ m_current_xfer.done = false;
+ m_current_xfer.mstop_detected = false;
+
+ // Start the transfer
+ i2c_state_machine(I2C_SM_CMD_START);
+
+ // Is it a blocking call
+ if (m_current_xfer.cb == NULL)
+ {
+ app_lib_time_timestamp_hp_t end;
+
+ /* Timeout calculation, (timeout is in us)/
+ * - Start Address R/W bit is 10bits
+ * - For each byte read or written add 1 ack bit so 9bits
+ */
+ uint32_t timeout = ((10 + xfer_p->read_size*9 + xfer_p->write_size*9) *
+ m_i2c_bit_timeout_ns) / 1000;
+
+ end = lib_time->addUsToHpTimestamp(lib_time->getTimestampHp(),
+ timeout);
+
+ // Active wait until end of transfer or timeout
+ while (!m_current_xfer.done &&
+ lib_time->isHpTimestampBefore(lib_time->getTimestampHp(),end) );
+
+ m_current_xfer.free = true;
+
+ if(!m_current_xfer.done)
+ {
+ return I2C_RES_BUS_HANG;
+ }
+ else
+ {
+ return m_current_xfer.res;
+ }
+ }
+
+ return I2C_RES_OK;
+}
+
+i2c_res_e I2C_status(void)
+{
+ if (m_state == I2C_SM_ST_UNINITIALIZED)
+ {
+ return I2C_RES_NOT_INITIALIZED;
+ }
+ else if (!m_current_xfer.free)
+ {
+ return I2C_RES_BUSY;
+ }
+ else
+ {
+ return I2C_RES_OK;
+ }
+}
+
+/**
+ * \brief Function to handle the I2C Interrupt.
+ */
+void __attribute__((__interrupt__)) I2C_IRQHandler(void)
+{
+ if (I2C_DEV->IF && _I2C_IF_MSTOP_MASK)
+ {
+ m_current_xfer.mstop_detected = true;
+ } else {
+ m_current_xfer.mstop_detected = false;
+ }
+
+ // Clear all I2C interrupt flags
+ I2C_DEV->IFC = _I2C_IFC_MASK;
+
+ // Run the I2C state machine
+ i2c_state_machine(I2C_SM_CMD_NEXT);
+}
\ No newline at end of file
diff --git a/mcu/efr/efr32/hal/i2c.c b/mcu/efr/efr32/hal/i2c/i2c_series2.c
similarity index 86%
rename from mcu/efr/efr32/hal/i2c.c
rename to mcu/efr/efr32/hal/i2c/i2c_series2.c
index 943aa5ef..8adee47a 100644
--- a/mcu/efr/efr32/hal/i2c.c
+++ b/mcu/efr/efr32/hal/i2c/i2c_series2.c
@@ -12,6 +12,7 @@
#include "mcu.h"
#include "i2c.h"
+#include "i2c_common.h"
#include "vendor/em_cmu.h" // For CMU_ClockFreqGet(), cmuClock_HFPER
@@ -22,57 +23,18 @@ void I2C_IRQHandler(void);
#define I2C_IRQn I2C1_IRQn
#define I2C_DEV I2C1
#define I2C_MODULE 1
-#ifdef _SILICON_LABS_32B_SERIES_2
#define I2C_CLKEN0_BIT CMU_CLKEN0_I2C1
-#elif defined _SILICON_LABS_32B_SERIES_1
-#define I2C_HFPERCLKEN0_BIT CMU_HFPERCLKEN0_I2C1
-#endif // _SILICON_LABS_32B_SERIES_2
+
#elif defined(USE_I2C0)
#define I2C_IRQn I2C0_IRQn
#define I2C_DEV I2C0
#define I2C_MODULE 0
-#ifdef _SILICON_LABS_32B_SERIES_2
#define I2C_CLKEN0_BIT CMU_CLKEN0_I2C0
-#elif defined _SILICON_LABS_32B_SERIES_1
-#define I2C_HFPERCLKEN0_BIT CMU_HFPERCLKEN0_I2C0
-#endif // _SILICON_LABS_32B_SERIES_2
+
#else
#error USE_I2C0 or USE_I2C1 must be defined
#endif
-/** Internal transfer description */
-typedef struct
-{
- i2c_xfer_t * client_xfer; //< Transfer asked by client
- i2c_on_transfer_done_cb_f cb; //< Callback to call at end of transfer
- i2c_res_e res; //< Result of I2C transfer
- uint8_t pos; //< Read or write position
- bool free; //< False if transfer ongoing
- bool write_done; //< Is write before read done
- bool done; //< Is transfer done
- bool mstop_detected; //< Is MSTOP interrupt detected
-} internal_xfer_desc;
-
-/** I2C state machine state */
-typedef enum
-{
- I2C_SM_ST_UNINITIALIZED = 0,
- I2C_SM_ST_IDLE,
- I2C_SM_ST_START,
- I2C_SM_ST_WRITE_ADDR,
- I2C_SM_ST_WRITE_DATA,
- I2C_SM_ST_READ,
- I2C_SM_ST_STOP
-} i2c_sm_state_e;
-
-/** I2C state machine commands */
-typedef enum
-{
- I2C_SM_CMD_ABORT = 0,
- I2C_SM_CMD_START,
- I2C_SM_CMD_NEXT
-} i2c_sm_command_e;
-
/**
* Time taken to transfer one bit on I2C with 50% margin. This value depends
* on the bus speed.
@@ -109,7 +71,6 @@ static void configure_gpios(bool pullup)
pullup ? GPIO_MODE_OUT_OD_PU :
GPIO_MODE_OUT_OD_NOPULL);
-#ifdef _SILICON_LABS_32B_SERIES_2
// Route GPIO pins to I2C module
GPIO->I2CROUTE[I2C_MODULE].SDAROUTE = (GPIO->I2CROUTE[I2C_MODULE].SDAROUTE & ~_GPIO_I2C_SDAROUTE_MASK)
| (BOARD_I2C_GPIO_PORT << _GPIO_I2C_SDAROUTE_PORT_SHIFT
@@ -118,13 +79,7 @@ static void configure_gpios(bool pullup)
| (BOARD_I2C_GPIO_PORT << _GPIO_I2C_SCLROUTE_PORT_SHIFT
| (BOARD_I2C_SCL_PIN << _GPIO_I2C_SCLROUTE_PIN_SHIFT));
GPIO->I2CROUTE[I2C_MODULE].ROUTEEN = GPIO_I2C_ROUTEEN_SDAPEN | GPIO_I2C_ROUTEEN_SCLPEN;
-#else
- // Choose routing of SDA and SCL GPIO to the I2C peripheral
- I2C_DEV->ROUTELOC0 = BOARD_I2C_ROUTELOC_SDALOC | BOARD_I2C_ROUTELOC_SCLLOC;
- // Enable routing of SDA and SCL to the I2C peripheral
- I2C_DEV->ROUTEPEN = I2C_ROUTEPEN_SDAPEN | I2C_ROUTEPEN_SCLPEN;
-#endif
}
/**
@@ -133,14 +88,9 @@ static void configure_gpios(bool pullup)
static void release_gpios(void)
{
// Disable routing of SDA and SCL to the I2C peripheral
-#ifdef _SILICON_LABS_32B_SERIES_2
GPIO->I2CROUTE[I2C_MODULE].SDAROUTE = _GPIO_I2C_SDAROUTE_RESETVALUE;
GPIO->I2CROUTE[I2C_MODULE].SCLROUTE = _GPIO_I2C_SCLROUTE_RESETVALUE;
GPIO->I2CROUTE[I2C_MODULE].ROUTEEN = _GPIO_LETIMER_ROUTEEN_RESETVALUE;
-#else
- I2C_DEV->ROUTEPEN = _I2C_ROUTEPEN_RESETVALUE;
- I2C_DEV->ROUTELOC0 = _I2C_ROUTELOC0_RESETVALUE;
-#endif
// Restore SDA GPIO
hal_gpio_set_mode(BOARD_I2C_GPIO_PORT,
@@ -160,29 +110,19 @@ static void release_gpios(void)
* \param enable
* True to enable clock, false to disable
*/
-static void enable_clock(bool enable)
+void enable_clock(bool enable)
{
if (enable)
{
-#ifdef _SILICON_LABS_32B_SERIES_2
// I2C clock source gating available for xg22 only
// Turn on clock to the I2C peripheral for xg22
CMU->CLKEN0 |= I2C_CLKEN0_BIT;
-#elif defined _SILICON_LABS_32B_SERIES_1
- // Turn on clock to the I2C peripheral for xg12/13
- CMU->HFPERCLKEN0 |= I2C_HFPERCLKEN0_BIT;
-#endif
}
else
{
-#ifdef _SILICON_LABS_32B_SERIES_2
// I2C clock source gating available for xg22 only
// Turn off clock to the I2C peripheral for xg22
CMU->CLKEN0 &= ~I2C_CLKEN0_BIT;
-#elif defined _SILICON_LABS_32B_SERIES_1
- // Turn off clock to the I2C peripheral for xg12/13
- CMU->HFPERCLKEN0 &= ~I2C_HFPERCLKEN0_BIT;
-#endif
}
}
@@ -194,18 +134,13 @@ static void enable_clock(bool enable)
* True to clear pending I2C peripheral interrupts, false to disable
* \note IRQ can only be enabled when clocks are enabled
*/
-static void enable_interrupts(bool enable, bool clear)
+void enable_interrupts(bool enable, bool clear)
{
if (clear)
{
// Clear all I2C interrupt flags
-#ifdef _SILICON_LABS_32B_SERIES_2
// For xg21/22
I2C_DEV->IF_CLR = _I2C_IF_MASK;
-#elif defined _SILICON_LABS_32B_SERIES_1
- // for xg12/13
- I2C_DEV->IFC = _I2C_IFC_MASK;
-#endif
}
if (enable)
@@ -230,16 +165,11 @@ static void enable_interrupts(bool enable, bool clear)
static bool set_frequency(uint32_t f_scl)
{
//Clock source for I2C interface
-#ifdef _SILICON_LABS_32B_SERIES_2
#ifdef USE_I2C0
uint32_t f_i2cclk = CMU_ClockFreqGet(cmuClock_LSPCLK);
#elif defined USE_I2C1
uint32_t f_i2cclk = CMU_ClockFreqGet(cmuClock_PCLK);
#endif
-#elif defined _SILICON_LABS_32B_SERIES_1
- // Read HFPERCLK frequency
- uint32_t f_i2cclk = CMU_ClockFreqGet(cmuClock_HFPER);
-#endif
// Calculate required divisor
//
@@ -597,14 +527,9 @@ i2c_res_e I2C_init(i2c_conf_t * conf_p)
I2C_IRQHandler);
// Enable I2C peripheral: arbitration disabled, 4:4 clock periods
-#ifdef _SILICON_LABS_32B_SERIES_2
I2C_DEV->CTRL_SET = I2C_CTRL_ARBDIS |
I2C_CTRL_CLHR_STANDARD | I2C_CTRL_TXBIL_EMPTY;
I2C_DEV->EN_SET = I2C_EN_EN;
-#else
- I2C_DEV->CTRL = I2C_CTRL_EN | I2C_CTRL_ARBDIS |
- I2C_CTRL_CLHR_STANDARD | I2C_CTRL_TXBIL_EMPTY;
-#endif
// Configure SCL frequency
if (!set_frequency(conf_p->clock))
@@ -655,9 +580,7 @@ i2c_res_e I2C_close(void)
release_gpios();
// Disable I2C peripheral
-#ifdef _SILICON_LABS_32B_SERIES_2
I2C_DEV->EN_CLR = I2C_EN_EN;
-#endif
I2C_DEV->CTRL = _I2C_CTRL_RESETVALUE;
// Configuration done, turn off clock to the I2C peripheral
@@ -764,13 +687,7 @@ void __attribute__((__interrupt__)) I2C_IRQHandler(void)
}
// Clear all I2C interrupt flags
-#ifdef _SILICON_LABS_32B_SERIES_2
- // For xg21/22
- I2C_DEV->IF_CLR = _I2C_IF_MASK;
-#else
- // for xg12/13
- I2C_DEV->IFC = _I2C_IFC_MASK;
-#endif
+ I2C_DEV->IF_CLR = _I2C_IF_MASK;
// Run the I2C state machine
i2c_state_machine(I2C_SM_CMD_NEXT);
diff --git a/mcu/efr/efr32/hal/led.c b/mcu/efr/efr32/hal/led.c
deleted file mode 100644
index 25cf978b..00000000
--- a/mcu/efr/efr32/hal/led.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/* Copyright 2019 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-/*
- * \file led.c
- * \brief Board-specific LED functions for efr32
- */
-
-#include "led.h"
-#include "mcu.h"
-#include "board.h"
-
-#ifdef BOARD_LED_PIN_LIST
-
-/*
- * The selected board has LEDs
- */
-
-#ifndef BOARD_LED_ACTIVE_LOW
-/** \brief Are LEDs active low. It can be overwritten from board.h */
-#define BOARD_LED_ACTIVE_LOW false
-#endif
-
-typedef struct
-{
- uint8_t port;
- uint8_t pin;
-} led_gpio_t;
-
-/** \brief Board-dependent LED number to pin mapping */
-static const led_gpio_t pin_map[] = BOARD_LED_PIN_LIST;
-
-/** \brief Compute number of leds on the board */
-#define NUMBER_OF_LEDS (sizeof(pin_map) / sizeof(pin_map[0]))
-
-static void led_configure(uint8_t led_id)
-{
- led_gpio_t led = pin_map[led_id];
- if (led.pin > 15 || led.port > GPIO_PORT_MAX)
- {
- return;
- }
-
-#if defined(_SILICON_LABS_32B_SERIES_1)
- /* Enable clocks */
- CMU->HFBUSCLKEN0 |= CMU_HFBUSCLKEN0_GPIO;
-#elif !defined (EFR32MG21)
- CMU->CLKEN0_SET = CMU_CLKEN0_GPIO;
-#endif
-
- /* Set pin mode */
- hal_gpio_set_mode(led.port,
- led.pin,
- GPIO_MODE_OUT_PP);
-
- /* Off by default */
-#if BOARD_LED_ACTIVE_LOW
- hal_gpio_set(led.port, led.pin);
-#else // BOARD_LED_ACTIVE_LOW
- hal_gpio_clear(led.port, led.pin);
-#endif // BOARD_LED_ACTIVE_LOW
-}
-
-void Led_init(void)
-{
- for (uint8_t i = 0; i < NUMBER_OF_LEDS; i++)
- {
- // Set up LED GPIO
- led_configure(i);
- }
-}
-
-bool Led_get(uint8_t led_id)
-{
- if (led_id >= NUMBER_OF_LEDS)
- {
- return LED_RES_INVALID_ID;
- }
- led_gpio_t led = pin_map[led_id];
- if (led.pin > 15 || led.port > GPIO_PORT_MAX)
- {
- return LED_RES_INVALID_ID;
- }
-
-#if BOARD_LED_ACTIVE_LOW
- return (hal_gpio_get(led.port, led.pin) == 0);
-#else //BOARD_LED_ACTIVE_HIGH
- return (hal_gpio_get(led.port, led.pin) != 0);
-#endif // BOARD_LED_ACTIVE_LOW
-}
-
-led_res_e Led_set(uint8_t led_id, bool state)
-{
- if (led_id >= NUMBER_OF_LEDS)
- {
- return LED_RES_INVALID_ID;
- }
-
- led_gpio_t led = pin_map[led_id];
- if (led.pin > 15 || led.port > GPIO_PORT_MAX)
- {
- return LED_RES_INVALID_ID;
- }
-
-#if BOARD_LED_ACTIVE_LOW
- if (state)
- {
- hal_gpio_clear(led.port, led.pin);
- }
- else
- {
- hal_gpio_set(led.port, led.pin);
- }
-#else // BOARD_LED_ACTIVE_LOW
- if (state)
- {
- hal_gpio_set(led.port, led.pin);
- }
- else
- {
- hal_gpio_clear(led.port, led.pin);
- }
-#endif // BOARD_LED_ACTIVE_LOW
-
- return LED_RES_OK;
-}
-
-led_res_e Led_toggle(uint8_t led_id)
-{
- if (led_id >= NUMBER_OF_LEDS)
- {
- return LED_RES_INVALID_ID;
- }
-
- led_gpio_t led = pin_map[led_id];
-
- if (led.pin > 15 || led.port > GPIO_PORT_MAX)
- {
- return LED_RES_INVALID_ID;
- }
-
- hal_gpio_toggle(led.port, led.pin);
-
- return LED_RES_OK;
-}
-
-uint8_t Led_getNumber(void)
-{
- return NUMBER_OF_LEDS;
-}
-
-#else // BOARD_LED_PIN_LIST
-
-/*
- * The selected board has no LEDs
- *
- * As some example apps support such boards but also provide extra status
- * information when a board has LEDs, the LED driver has this dummy
- * implementation to simplify the build process.
- */
-
-void Led_init(void)
-{
- // Do nothing
-}
-
-led_res_e Led_set(uint8_t led_id, bool state)
-{
- (void) led_id;
- (void) state;
-
- // Invalid LED number
- return LED_RES_INVALID_ID;
-}
-
-led_res_e Led_toggle(uint8_t led_id)
-{
- (void) led_id;
-
- // Invalid LED number
- return LED_RES_INVALID_ID;
-}
-
-uint8_t Led_getNumber(void)
-{
- return 0;
-}
-
-#endif // BOARD_LED_PIN_LIST
diff --git a/mcu/efr/efr32/hal/makefile b/mcu/efr/efr32/hal/makefile
index 0e9b585b..603399ad 100644
--- a/mcu/efr/efr32/hal/makefile
+++ b/mcu/efr/efr32/hal/makefile
@@ -1,62 +1,80 @@
EFR32_HAL_PREFIX := $(MCU_PREFIX)hal/
EFR32_VENDOR_PREFIX :=$(MCU_COMMON)/vendor/
-# Add include path for nrf52 specific HAL header files
+# Add include path for efr32 specific HAL header files
INCLUDES += -I$(EFR32_HAL_PREFIX)
+ifeq ($(HAL_GPIO), yes)
+SRCS += $(EFR32_HAL_PREFIX)gpio.c
+endif
+
ifeq ($(HAL_UART), yes)
+INCLUDES += -I$(EFR32_HAL_PREFIX)usart/series$(EFR32_SERIES)
ifeq ($(UART_USE_DMA), yes)
-SRCS += $(EFR32_HAL_PREFIX)usart_dma.c \
+SRCS += $(EFR32_HAL_PREFIX)usart/usart_dma.c \
$(EFR32_VENDOR_PREFIX)em_ldma.c \
- $(EFR32_VENDOR_PREFIX)em_core.c
-else
-SRCS += $(EFR32_HAL_PREFIX)usart.c
-endif
-SRCS += $(EFR32_VENDOR_PREFIX)em_usart.c \
- $(EFR32_VENDOR_PREFIX)$(HAL_SYSTEM_C)
-endif
+ $(EFR32_VENDOR_PREFIX)em_usart.c
+else # DMA
+ifeq ($(MCU_SUB), xg23)
+SRCS += $(EFR32_HAL_PREFIX)usart/eusart.c
+SRCS += $(EFR32_VENDOR_PREFIX)em_eusart.c
+else # xG23
+SRCS += $(EFR32_HAL_PREFIX)usart/usart.c
+SRCS += $(EFR32_VENDOR_PREFIX)em_usart.c
+endif # xG23
+endif # DMA
+SRCS += $(EFR32_VENDOR_PREFIX)$(HAL_SYSTEM_C)
+endif # UART
+
+
ifeq ($(HAL_I2C), yes)
-SRCS += $(EFR32_HAL_PREFIX)i2c.c \
- $(EFR32_VENDOR_PREFIX)$(HAL_SYSTEM_C)
+ifeq ($(MCU_SUB), xg12)
+SRCS += $(EFR32_HAL_PREFIX)i2c/i2c_series1.c
+else
+SRCS += $(EFR32_HAL_PREFIX)i2c/i2c_series2.c
endif
-
-ifeq ($(MCU_SUB), xg21)
-INCLUDES += -I$(EFR32_VENDOR_PREFIX)rail_lib/chip/efr32/efr32xg2x
-INCLUDES += -I$(EFR32_VENDOR_PREFIX)rail_lib/common
+SRCS += $(EFR32_VENDOR_PREFIX)$(HAL_SYSTEM_C)
endif
-ifeq ($(MCU_SUB), xg23)
+ifneq (,$(filter $(MCU_SUB), xg21 xg23 xg24 ))
INCLUDES += -I$(EFR32_VENDOR_PREFIX)rail_lib/chip/efr32/efr32xg2x
INCLUDES += -I$(EFR32_VENDOR_PREFIX)rail_lib/common
endif
-ifeq ($(HAL_BUTTON), yes)
-SRCS += $(EFR32_HAL_PREFIX)button.c
-endif
-
-ifeq ($(HAL_LED), yes)
-SRCS += $(EFR32_HAL_PREFIX)led.c
-endif
-ifeq ($(HAL_VOLTAGE), yes)
-ifneq (,$(filter $(MCU_SUB), xg21 xg22))
+ifeq ($(HAL_VOLTAGE), yes)
+ifeq ($(EFR32_SERIES), 2)
SRCS += $(EFR32_VENDOR_PREFIX)em_iadc.c \
$(EFR32_VENDOR_PREFIX)$(HAL_SYSTEM_C)
endif
-ifeq ($(MCU_SUB), xg22)
-SRCS += $(EFR32_VENDOR_PREFIX)em_core.c
-endif
-SRCS += $(EFR32_HAL_PREFIX)voltage.c
+SRCS += $(EFR32_HAL_PREFIX)voltage_series_$(EFR32_SERIES).c
endif
ifeq ($(HAL_PRS), yes)
SRCS += $(EFR32_VENDOR_PREFIX)em_prs.c
endif
-SRCS += $(EFR32_HAL_PREFIX)ds.c \
- $(EFR32_HAL_PREFIX)power.c \
+ifeq ($(HAL_SPI), yes)
+ifneq (,$(filter $(MCU_SUB), xg22 xg23 xg24 ))
+SRCS += $(EFR32_HAL_PREFIX)spi.c
+ifeq ($(MCU_SUB), xg23)
+SRCS += $(EFR32_VENDOR_PREFIX)em_usart.c \
+ $(EFR32_VENDOR_PREFIX)$(HAL_SYSTEM_C)
+else
+ifneq ($(HAL_UART), yes)
+SRCS += $(EFR32_VENDOR_PREFIX)em_usart.c \
+ $(EFR32_VENDOR_PREFIX)$(HAL_SYSTEM_C)
+endif
+endif
+else
+$(error Board $(target_board) doesn't support SPI (xg22, xg23, xg24 only))
+endif
+endif
+
+SRCS += $(EFR32_HAL_PREFIX)power.c \
$(EFR32_HAL_PREFIX)hal.c \
$(EFR32_VENDOR_PREFIX)em_emu.c\
$(EFR32_VENDOR_PREFIX)em_cmu.c \
+ $(EFR32_VENDOR_PREFIX)em_core.c \
$(EFR32_VENDOR_PREFIX)em_gpio.c
diff --git a/mcu/efr/efr32/hal/power.c b/mcu/efr/efr32/hal/power.c
index dcd08820..86eea656 100644
--- a/mcu/efr/efr32/hal/power.c
+++ b/mcu/efr/efr32/hal/power.c
@@ -26,7 +26,7 @@
* (Profiles over ~13.5dBm TX power need PA voltage 3V3, DCDC is not enough).
*/
-#if defined(_SILICON_LABS_32B_SERIES_1)
+#if (_SILICON_LABS_32B_SERIES == 1)
#define EMU_DCDCINIT \
{ \
emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \
@@ -40,7 +40,7 @@
160, /* Maximum reverse current of 160mA */ \
emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor */ \
}
-#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3)
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 3)
#define EMU_DCDCINIT \
{ \
emuDcdcMode_Regulation, /**< DCDC regulator on. */ \
@@ -51,6 +51,18 @@
emuDcdcPeakCurrent_Load36mA, /**< Default peak current in EM0/1. */ \
emuDcdcPeakCurrent_Load36mA /**< Default peak current in EM2/3. */ \
}
+#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 4 || _SILICON_LABS_32B_SERIES_2_CONFIG == 5)
+#define EMU_DCDCINIT \
+ { \
+ emuDcdcMode_Regulation, /**< DCDC regulator on. */ \
+ emuVreginCmpThreshold_2v3, /**< 2.3V VREGIN comparator threshold. */ \
+ emuDcdcTonMaxTimeout_1P19us, /**< Ton max is 1.19us. */ \
+ emuDcdcDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \
+ emuDcdcDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \
+ emuDcdcPeakCurrent_Load60mA, /**< Default peak current in EM0/1. */ \
+ emuDcdcPeakCurrent_Load36mA /**< Default peak current in EM2/3. */ \
+ }
+
#else //other _SILICON_LABS_32B_SERIES_2 device
#define EMU_DCDCINIT \
{ \
diff --git a/mcu/efr/efr32/hal/radio/radio_power_table_efr32xg12_19dBm.h b/mcu/efr/efr32/hal/radio/radio_power_table_efr32xg12_19dBm.h
index e7c9fbec..5b723cae 100644
--- a/mcu/efr/efr32/hal/radio/radio_power_table_efr32xg12_19dBm.h
+++ b/mcu/efr/efr32/hal/radio/radio_power_table_efr32xg12_19dBm.h
@@ -10,7 +10,7 @@
const app_lib_radio_cfg_power_t power_table_efr32xg12_19dBm =
{
.rx_current = 100, // 10 mA RX current
- .rx_gain_dbm = 0, // 0 dBm RX gain
+ .rx_gain_db = 0, // 0 dB RX gain
.power_count = 8, // 8 power levels
.powers =
{
diff --git a/mcu/efr/efr32/hal/radio/radio_power_table_efr32xg21_20dbm.h b/mcu/efr/efr32/hal/radio/radio_power_table_efr32xg21_20dbm.h
index 6bf85d68..d1bc6abb 100644
--- a/mcu/efr/efr32/hal/radio/radio_power_table_efr32xg21_20dbm.h
+++ b/mcu/efr/efr32/hal/radio/radio_power_table_efr32xg21_20dbm.h
@@ -6,8 +6,7 @@
#ifndef RADIO_POWER_TABLE_EFR32XG21_20DBM_H_
#define RADIO_POWER_TABLE_EFR32XG21_20DBM_H_
-#include "radio_config.h"
-#include "rail_chip_specific.h"
+#include "rail_types.h"
/**
* Power table for efr32xg21 +20dBm.
@@ -15,7 +14,7 @@
const app_lib_radio_cfg_power_t power_table_efr32xg21_20dBm =
{
.rx_current = 880, // 8.8 mA RX current
- .rx_gain_dbm = 0, // 0 dBm RX gain
+ .rx_gain_db = 0, // 0 dB RX gain
.power_count = 8, // 8 power levels
.powers =
{
diff --git a/mcu/efr/efr32/hal/radio/radio_power_table_efr32xg23_13dbm.h b/mcu/efr/efr32/hal/radio/radio_power_table_efr32xg23_13dbm.h
index f5edf889..012bfc5d 100644
--- a/mcu/efr/efr32/hal/radio/radio_power_table_efr32xg23_13dbm.h
+++ b/mcu/efr/efr32/hal/radio/radio_power_table_efr32xg23_13dbm.h
@@ -6,15 +6,13 @@
#ifndef RADIO_POWER_TABLE_EFR32XG23_13DBM_H_
#define RADIO_POWER_TABLE_EFR32XG23_13DBM_H_
-#include "rail_chip_specific.h"
-
/**
* Power table for efr32xg23 +13dBm.
* */
const app_lib_radio_cfg_power_t power_table_efr32xg23_13dBm =
{
.rx_current = 69, // 6.9 mA RX current
- .rx_gain_dbm = 0, // 0 dBm RX gain
+ .rx_gain_db = 0, // 0 dB RX gain
.power_count = 8, // 8 power levels
.powers =
{
diff --git a/mcu/efr/efr32/hal/radio/radio_power_table_efr32xg23_16dbm.h b/mcu/efr/efr32/hal/radio/radio_power_table_efr32xg23_16dbm.h
index 5b18b088..63d3a9fe 100644
--- a/mcu/efr/efr32/hal/radio/radio_power_table_efr32xg23_16dbm.h
+++ b/mcu/efr/efr32/hal/radio/radio_power_table_efr32xg23_16dbm.h
@@ -6,15 +6,13 @@
#ifndef RADIO_POWER_TABLE_EFR32XG23_16DBM_H_
#define RADIO_POWER_TABLE_EFR32XG23_16DBM_H_
-#include "rail_chip_specific.h"
-
/**
* Power table for efr32xg23 +16dBm.
* */
const app_lib_radio_cfg_power_t power_table_efr32xg23_16dBm =
{
.rx_current = 69, // 6.9 mA RX current
- .rx_gain_dbm = 0, // 0 dBm RX gain
+ .rx_gain_db = 0, // 0 dB RX gain
.power_count = 8, // 8 power levels
.powers =
{
diff --git a/mcu/efr/efr32/hal/radio/radio_power_table_efr32xg23_20dbm.h b/mcu/efr/efr32/hal/radio/radio_power_table_efr32xg23_20dbm.h
index bdd9304e..c672aec0 100644
--- a/mcu/efr/efr32/hal/radio/radio_power_table_efr32xg23_20dbm.h
+++ b/mcu/efr/efr32/hal/radio/radio_power_table_efr32xg23_20dbm.h
@@ -6,15 +6,13 @@
#ifndef RADIO_POWER_TABLE_EFR32XG23_20DBM_H_
#define RADIO_POWER_TABLE_EFR32XG23_20DBM_H_
-#include "rail_chip_specific.h"
-
/**
* Power table for efr32xg23 +20dBm.
* */
const app_lib_radio_cfg_power_t power_table_efr32xg23_20dBm =
{
.rx_current = 69, // 6.9 mA RX current
- .rx_gain_dbm = 0, // 0 dBm RX gain
+ .rx_gain_db = 0, // 0 dB RX gain
.power_count = 8, // 8 power levels
.powers =
{
diff --git a/mcu/efr/efr32/hal/radio/radio_power_table_efr32xg24_20dbm.h b/mcu/efr/efr32/hal/radio/radio_power_table_efr32xg24_20dbm.h
new file mode 100644
index 00000000..2b4abce8
--- /dev/null
+++ b/mcu/efr/efr32/hal/radio/radio_power_table_efr32xg24_20dbm.h
@@ -0,0 +1,59 @@
+/* Copyright 2023 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+#ifndef RADIO_POWER_TABLE_EFR32XG24_20DBM_H_
+#define RADIO_POWER_TABLE_EFR32XG24_20DBM_H_
+
+#include "rail_types.h"
+
+/**
+ * Power table for efr32xg24 +20dBm.
+ * */
+const app_lib_radio_cfg_power_t power_table_efr32xg24_20dBm =
+{
+ .rx_current = 880, // 8.8 mA RX current
+ .rx_gain_db = 0, // 0 dB RX gain
+ .power_count = 8, // 8 power levels
+ .powers =
+ {
+ //todo: Current consumption figures to be checked
+ { 1, -17, 1, 150 }, // -17.29 dBm, 15.00 mA
+ { 3, -10, 1, 170 }, // -9.60 dBm, 17.00 mA
+ { 5, -5, 1, 220 }, // -5.21 dBm, 22.00 mA
+ { 10, 0, 1, 300 }, // 0.35 dBm, 30.00 mA
+ { 18, 5, 1, 400 }, // 5.01 dBm, 40.00 mA
+ { 33, 10, 1, 600 }, // 9.92 dBm, 60.00 mA
+ { 63, 15, 1, 1000 }, // 14.99 dBm, 100.00 mA
+ { 160, 20, 1, 2000 }, // 19.98 dBm, 200.00 mA
+ },
+};
+
+#define RADIO_CUSTOM_PA_CONFIG
+
+#if defined RADIO_CUSTOM_PA_CONFIG
+// PA configuration for efr32xg24 +20dbm
+const RAIL_TxPowerConfig_t pa_config_efr32xg24_20dBm =
+ {
+ .mode = RAIL_TX_POWER_MODE_2P4GIG_HP,
+ .voltage = 3300,
+ .rampTime = 10,
+ };
+#endif
+
+#if defined RADIO_CUSTOM_POWER_TABLE_H
+__STATIC_INLINE const app_lib_radio_cfg_power_t * get_custom_power_table(void)
+{
+ return &power_table_efr32xg24_20dBm;
+}
+#endif
+
+#if defined RADIO_CUSTOM_PA_CONFIG
+__STATIC_INLINE const RAIL_TxPowerConfig_t * get_custom_pa_config(void)
+{
+ return &pa_config_efr32xg24_20dBm;
+}
+#endif
+
+#endif /* RADIO_POWER_TABLE_EFR32XG24_20DBM_H_ */
diff --git a/mcu/efr/efr32/hal/spi.c b/mcu/efr/efr32/hal/spi.c
new file mode 100644
index 00000000..155bdd3e
--- /dev/null
+++ b/mcu/efr/efr32/hal/spi.c
@@ -0,0 +1,394 @@
+/* Copyright 2022 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+#include
+#include
+#include
+
+#include "hal_api.h"
+#include "board.h"
+#include "api.h"
+#include "spi.h"
+
+#include "em_cmu.h"
+#include "em_gpio.h"
+#include "em_usart.h"
+
+// References:
+// [1] EFR32xG23 Wireless SoC Reference Manual
+// https://www.silabs.com/documents/public/reference-manuals/efr32xg23-rm.pdf
+
+#ifndef BOARD_SPI
+#error "Please define the required SPI definition in your board.h (BOARD_SPI,…)"
+#endif
+
+#define SPI_EXTFLASH_BAUDRATE 8000000
+
+// Dummy byte for SPI transfer
+#define DUMMY_BYTE 0xFF
+
+/** Internal transfer description */
+typedef struct
+{
+ spi_xfer_t * client_xfer; //< Transfer asked by client
+ spi_on_transfer_done_cb_f cb; //< Callback to call at end of transfer
+ bool free; //< False if transfer ongoing
+ volatile bool done; //< Is transfer done
+} internal_xfer_desc;
+
+/** Current tansfer ongoing. Only one transfer supported in this implementation */
+static internal_xfer_desc m_current_xfer;
+
+/** Is SPI module initialized */
+static bool m_spi_initialized = false;
+
+/***************************************************************************//**
+ * @brief Configure different SPI gpios (MOSI, MISO, SCLK and CS)
+ * @param[in] mode
+ * SPI chosen mode \ref spi_mode_e
+ ******************************************************************************/
+static void spidrv_configure_gpios(spi_mode_e mode)
+{
+ // Pin configuration: refer to doc [1] section 24.3.1 Pin Configuration
+ // Setup the MOSI pin (TX), PUSHPULL mode
+ hal_gpio_set_mode(BOARD_SPI_EXTFLASH_MOSI_PORT,
+ BOARD_SPI_EXTFLASH_MOSI_PIN,
+ GPIO_MODE_OUT_PP);
+ hal_gpio_clear(BOARD_SPI_EXTFLASH_MOSI_PORT, BOARD_SPI_EXTFLASH_MOSI_PIN);
+
+ // Setup the MISO pin (RX), INPUT mode
+ hal_gpio_set_mode(BOARD_SPI_EXTFLASH_MISO_PORT,
+ BOARD_SPI_EXTFLASH_MISO_PIN,
+ GPIO_MODE_IN_OD_NOPULL);
+ hal_gpio_clear(BOARD_SPI_EXTFLASH_MISO_PORT, BOARD_SPI_EXTFLASH_MISO_PIN);
+
+ // Setup the SCLK pin, PUSHPULL mode:
+ // - serial mode 0 and 1 => SCLK idle low
+ // - serial mode 2 and 3 => SCLK idle high)
+ hal_gpio_set_mode(BOARD_SPI_EXTFLASH_SCKL_PORT,
+ BOARD_SPI_EXTFLASH_SCKL_PIN,
+ GPIO_MODE_OUT_PP);
+ if (SPI_MODE_LOW_FIRST == mode || SPI_MODE_LOW_SECOND == mode)
+ {
+ hal_gpio_clear(BOARD_SPI_EXTFLASH_SCKL_PORT,
+ BOARD_SPI_EXTFLASH_SCKL_PIN);
+ }
+ else
+ {
+ hal_gpio_set(BOARD_SPI_EXTFLASH_SCKL_PORT,
+ BOARD_SPI_EXTFLASH_SCKL_PIN);
+ }
+}
+
+/***************************************************************************//**
+ * @brief Release different SPI GPIOs (MOSI, MISO, SCLK and CS)
+ ******************************************************************************/
+static void spidrv_release_gpios(void)
+{
+ hal_gpio_set_mode(BOARD_SPI_EXTFLASH_MOSI_PORT,
+ BOARD_SPI_EXTFLASH_MOSI_PIN,
+ GPIO_MODE_DISABLED);
+ hal_gpio_set_mode(BOARD_SPI_EXTFLASH_MISO_PORT,
+ BOARD_SPI_EXTFLASH_MISO_PIN,
+ GPIO_MODE_DISABLED);
+ hal_gpio_set_mode(BOARD_SPI_EXTFLASH_SCKL_PORT,
+ BOARD_SPI_EXTFLASH_SCKL_PIN,
+ GPIO_MODE_DISABLED);
+}
+
+/***************************************************************************//**
+ * @brief Convert configuration parameters
+ * @param[in] p_in
+ * SPI driver API configuration parameters \ref spi_conf_t
+ * @param[out] p_out
+ * EFR32 xG2x USART configuration parameters
+ * \ref USART_InitSync_TypeDef
+ * @return true if input parameters are valid, false otherwise
+ ******************************************************************************/
+static bool spidrv_convert_parameters(spi_conf_t * in_p,
+ USART_InitSync_TypeDef * out_p)
+{
+ switch (in_p->mode)
+ {
+ //< Low Polarity, First Clock edge
+ case SPI_MODE_LOW_FIRST:
+ out_p->clockMode = usartClockMode0;
+ break;
+ //< Low Polarity, Second Clock edge
+ case SPI_MODE_LOW_SECOND:
+ out_p->clockMode = usartClockMode1;
+ break;
+ //< High Polarity, First Clock edge
+ case SPI_MODE_HIGH_FIRST:
+ out_p->clockMode = usartClockMode2;
+ break;
+ //< High Polarity, Second Clock edge
+ case SPI_MODE_HIGH_SECOND:
+ out_p->clockMode = usartClockMode3;
+ break;
+ default:
+ return false;
+ }
+
+ switch (in_p->bit_order)
+ {
+ //< Most Significant Bit first
+ case SPI_ORDER_MSB:
+ out_p->msbf = true;
+ break;
+ //< Less Significant Bit first
+ case SPI_ORDER_LSB:
+ out_p->msbf = false;
+ break;
+ default:
+ return false;
+ }
+
+ if (! in_p->clock)
+ {
+ return false;
+ }
+ out_p->baudrate = in_p->clock;
+
+ return true;
+}
+
+/***************************************************************************//**
+ * @brief Enable USART clock
+ * @param[in] p_in
+ * SPI driver API configuration parameters \ref spi_conf_t
+ * @param[out] p_out
+ * EFR32 xG2x USART configuration parameters
+ * \ref USART_InitSync_TypeDef
+ * @return true if input parameters are valid, false otherwise
+ ******************************************************************************/
+static void enable_usart_clock(void)
+{
+ DS_Disable(DS_SOURCE_USART);
+ CMU->CLKEN0_SET = CMU_CLKEN0_USART0;
+}
+
+/***************************************************************************//**
+ * @brief Disable USART clock
+ * @param[in] p_in
+ * SPI driver API configuration parameters \ref spi_conf_t
+ * @param[out] p_out
+ * EFR32 xG2x USART configuration parameters
+ * \ref USART_InitSync_TypeDef
+ * @return true if input parameters are valid, false otherwise
+ ******************************************************************************/
+static void disable_usart_clock(void)
+{
+ CMU->CLKEN0_CLR = CMU_CLKEN0_USART0;
+ DS_Enable(DS_SOURCE_USART);
+}
+
+/***************************************************************************//**
+ * @brief
+ * Initialize SPI i.e. USART block for synchronous mode.
+ *
+ * @details
+ * This function will configure basic settings to operate in
+ * synchronous mode.
+ *
+ * @param[in] conf_p
+ * A pointer to the SPI configuration parameters \ref spi_conf_t
+ *
+ * @return
+ * \ref SPI_RES_OK if initialization is ok, an error code otherwise
+ * Refer to \ref spi_res_e for other result codes
+ ******************************************************************************/
+spi_res_e SPI_init(spi_conf_t * conf_p)
+{
+ if (m_spi_initialized)
+ {
+ return SPI_RES_ALREADY_INITIALIZED;
+ }
+
+ // Check and convert input parameters
+ USART_InitSync_TypeDef USART_init = USART_INITSYNC_DEFAULT;
+ USART_init.enable = usartDisable;
+ if (! conf_p || false == spidrv_convert_parameters(conf_p, &USART_init))
+ {
+ return SPI_RES_INVALID_CONFIG;
+ }
+
+ // Enable GPIO clock
+ CMU->CLKEN0_SET = CMU_CLKEN0_GPIO;
+
+ // Configure GPIO
+ spidrv_configure_gpios(conf_p->mode);
+
+ // Enable USART clock during the configuration
+ enable_usart_clock();
+
+ // Configure UART in sync mode
+ USART_InitSync(BOARD_SPI, &USART_init);
+
+ // Set UART routes
+ // Refer to doc [1], sections:
+ // - 24.6.192 GPIO_USART0_TXROUTE - TX Port/Pin Select
+ // - 24.6.190 GPIO_USART0_RXROUTE - RX Port/Pin Select
+ // - 24.6.191 GPIO_USART0_CLKROUTE - SCLK Port/Pin Select
+ BOARD_SPIROUTE.TXROUTE =
+ (BOARD_SPI_EXTFLASH_MOSI_PORT << _GPIO_USART_TXROUTE_PORT_SHIFT) |
+ (BOARD_SPI_EXTFLASH_MOSI_PIN << _GPIO_USART_TXROUTE_PIN_SHIFT);
+
+ BOARD_SPIROUTE.RXROUTE =
+ (BOARD_SPI_EXTFLASH_MISO_PORT << _GPIO_USART_RXROUTE_PORT_SHIFT) |
+ (BOARD_SPI_EXTFLASH_MISO_PIN << _GPIO_USART_RXROUTE_PIN_SHIFT);
+
+ BOARD_SPIROUTE.CLKROUTE =
+ (BOARD_SPI_EXTFLASH_SCKL_PORT << _GPIO_USART_CLKROUTE_PORT_SHIFT) |
+ (BOARD_SPI_EXTFLASH_SCKL_PIN << _GPIO_USART_CLKROUTE_PIN_SHIFT);
+
+ // Enable the routes
+ // Refer to doc [1] 24.6.186 GPIO_USART0_ROUTEEN - USART0 Pin Enable
+ BOARD_SPIROUTE.ROUTEEN = GPIO_USART_ROUTEEN_TXPEN |
+ GPIO_USART_ROUTEEN_RXPEN |
+ GPIO_USART_ROUTEEN_CLKPEN;
+
+
+ // Enable data transmission and reception
+ // Refer to doc [1] section 20.5.3 USART_CTRL - Control Register
+ BOARD_SPI->CMD = USART_CMD_RXEN | USART_CMD_TXEN;
+
+ // Configuration done: disable USART clock
+ disable_usart_clock();
+
+ // Initialize the transfer structure
+ memset(&m_current_xfer, 0x00, sizeof(m_current_xfer));
+ m_current_xfer.free = true;
+
+ m_spi_initialized = true;
+
+ return SPI_RES_OK;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Deinitialize SPI
+ *
+ * @return
+ * \ref SPI_RES_OK if initialization is ok, an error code otherwise
+ * Refer to \ref spi_res_e for other result codes
+ ******************************************************************************/
+ spi_res_e SPI_close(void)
+{
+ if (! m_spi_initialized)
+ {
+ return SPI_RES_NOT_INITIALIZED;
+ }
+
+ // Enable USART clock
+ enable_usart_clock();
+
+ // Reser USART registers to their default configuration
+ USART_Reset(BOARD_SPI);
+
+ // Disable USART clock
+ disable_usart_clock();
+
+ // Disable the routes
+ BOARD_SPIROUTE.RXROUTE = _GPIO_USART_RXROUTE_RESETVALUE;
+ BOARD_SPIROUTE.TXROUTE = _GPIO_USART_TXROUTE_RESETVALUE;
+ BOARD_SPIROUTE.CLKROUTE = _GPIO_USART_CLKROUTE_RESETVALUE;
+ BOARD_SPIROUTE.ROUTEEN = _GPIO_USART_ROUTEEN_RESETVALUE;
+
+ // Set all GPIOs as default configuration
+ spidrv_release_gpios();
+
+ m_spi_initialized = false;
+
+ return SPI_RES_OK;
+}
+
+/***************************************************************************//**
+ * @brief
+ * SPI_transfer
+ *
+ * @details
+ *
+ * @param[in] xfer_p
+ * A pointer to the structure describing a SPI transfer \ref spi_xfer_t
+ * @param[in] cb
+ * Callback to be called when the transfer is done
+ *
+ * @return
+ * \ref SPI_RES_OK if the transfer is ok, an error code otherwise
+ * Refer to \ref spi_res_e for other result codes
+ ******************************************************************************/
+spi_res_e SPI_transfer(spi_xfer_t * xfer_p,
+ spi_on_transfer_done_cb_f cb)
+{
+ uint32_t i;
+
+ if (! m_spi_initialized)
+ {
+ return SPI_RES_NOT_INITIALIZED;
+ }
+
+ // Check if a transfer is already ongoing
+ if (! m_current_xfer.free)
+ {
+ return SPI_RES_BUSY;
+ }
+
+ // Check transfer
+ if (((xfer_p->write_ptr != NULL) && (xfer_p->write_size == 0)) ||
+ ((xfer_p->write_ptr == NULL) && (xfer_p->write_size != 0)) ||
+ ((xfer_p->read_ptr != NULL) && (xfer_p->read_size == 0)) ||
+ ((xfer_p->read_ptr == NULL) && (xfer_p->read_size != 0)))
+ {
+ return SPI_RES_INVALID_XFER;
+ }
+
+ // We just support synchronous transfers
+ if (NULL != cb)
+ {
+ return SPI_RES_INVALID_XFER;
+ }
+
+ // Enable USART clock
+ enable_usart_clock();
+
+ // Setup the transfer
+ m_current_xfer.free = false;
+ m_current_xfer.client_xfer = xfer_p;
+ m_current_xfer.done = false;
+ m_current_xfer.cb = NULL;
+
+ // Send the command
+ for (i = 0; i < m_current_xfer.client_xfer->write_size; i++)
+ {
+ uint8_t rsp;
+ rsp = USART_SpiTransfer(BOARD_SPI,
+ m_current_xfer.client_xfer->write_ptr[i]);
+ if (i < m_current_xfer.client_xfer->read_size)
+ {
+ m_current_xfer.client_xfer->read_ptr[i] = rsp;
+ }
+ }
+
+ // Read the data if requested
+ if (m_current_xfer.client_xfer->read_size >
+ m_current_xfer.client_xfer->write_size)
+ {
+ for (i = m_current_xfer.client_xfer->write_size;
+ i < m_current_xfer.client_xfer->read_size; i++)
+ {
+ m_current_xfer.client_xfer->read_ptr[i] =
+ USART_SpiTransfer(BOARD_SPI, DUMMY_BYTE);
+ }
+ }
+
+ m_current_xfer.done = true;
+ m_current_xfer.free = true;
+
+ // Disable clocks
+ disable_usart_clock();
+
+ return SPI_RES_OK;
+}
diff --git a/mcu/efr/efr32/hal/usart/eusart.c b/mcu/efr/efr32/hal/usart/eusart.c
new file mode 100644
index 00000000..ba5e847a
--- /dev/null
+++ b/mcu/efr/efr32/hal/usart/eusart.c
@@ -0,0 +1,286 @@
+/* Copyright 2022 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+
+#include
+#include
+#include
+
+#include "hal_api.h"
+#include "board.h"
+#include "api.h"
+#include "gpio.h"
+#include "em_eusart.h"
+#include "em_cmu.h"
+
+#define BUFFER_SIZE 512u
+#include "ringbuffer.h"
+static volatile ringbuffer_t m_usart_tx_buffer;
+
+static volatile serial_rx_callback_f m_rx_callback;
+static volatile uint32_t m_enabled;
+static volatile bool m_tx_active;
+
+void __attribute__((__interrupt__)) EUSART_RX_IRQHandler(void);
+void __attribute__((__interrupt__)) EUSART_TX_IRQHandler(void);
+
+bool Usart_init(uint32_t baudrate, uart_flow_control_e flow_control)
+{
+ EUSART_UartInit_TypeDef EUSART_init = EUSART_UART_INIT_DEFAULT_HF;
+
+#ifdef BOARD_GPIO_ID_VCOM_ENABLE
+ const gpio_out_cfg_t usart_vcom_enable_cfg =
+ {
+ .out_mode_cfg = GPIO_OUT_MODE_PUSH_PULL,
+ .level_default = GPIO_LEVEL_HIGH
+ };
+
+ // Enable vcom
+ Gpio_outputSetCfg(BOARD_GPIO_ID_VCOM_ENABLE, &usart_vcom_enable_cfg);
+#endif
+
+ (void)flow_control;
+
+ // Module variables
+ Ringbuffer_reset(m_usart_tx_buffer);
+ m_rx_callback = NULL;
+ m_tx_active = false;
+ m_enabled = 0;
+
+ // Disable for RX
+ Sys_disableAppIrq(EUSART0_RX_IRQn);
+ Sys_clearFastAppIrq(EUSART0_RX_IRQn);
+ // Disable for TX
+ Sys_disableAppIrq(EUSART0_TX_IRQn);
+ Sys_clearFastAppIrq(EUSART0_TX_IRQn);
+
+ CMU_ClockEnable(cmuClock_EUSART0, true);
+
+ // EUSART0 clock is connected to the HFXO (through the EM01GRPCCLK clock group)
+ CMU_ClockSelectSet(cmuClock_EM01GRPCCLK, cmuSelect_HFXO);
+ CMU_ClockSelectSet(cmuClock_EUSART0, cmuSelect_EM01GRPCCLK);
+
+ // EUSART0 is using a high frequency clock (HFXO),
+ // so that it can support high baudrates (e.g. 115200 bauds)
+ EUSART_init.enable = eusartDisable;
+ EUSART_init.baudrate = baudrate;
+ EUSART_init.oversampling = EUSART_CFG0_OVS_X4;
+ EUSART_UartInitHf(EUSART0, &EUSART_init);
+
+ // Set UART TX GPIO
+ hal_gpio_set_mode(BOARD_USART_TX_PORT,
+ BOARD_USART_TX_PIN,
+ GPIO_MODE_DISABLED);
+ hal_gpio_clear(BOARD_USART_TX_PORT,
+ BOARD_USART_TX_PIN);
+ // Set UART RX GPIO
+ hal_gpio_set_mode(BOARD_USART_RX_PORT,
+ BOARD_USART_RX_PIN,
+ GPIO_MODE_DISABLED);
+ hal_gpio_clear(BOARD_USART_RX_PORT,
+ BOARD_USART_RX_PIN);
+
+
+ GPIO->EUSARTROUTE[0].ROUTEEN = GPIO_EUSART_ROUTEEN_TXPEN;
+ GPIO->EUSARTROUTE[0].TXROUTE = (BOARD_USART_TX_PORT << _GPIO_EUSART_TXROUTE_PORT_SHIFT) | (BOARD_USART_TX_PIN << _GPIO_EUSART_TXROUTE_PIN_SHIFT);
+ GPIO->EUSARTROUTE[0].RXROUTE = (BOARD_USART_RX_PORT << _GPIO_EUSART_RXROUTE_PORT_SHIFT) | (BOARD_USART_RX_PIN << _GPIO_EUSART_RXROUTE_PIN_SHIFT);
+
+ EUSART_IntDisable(EUSART0, _EUSART_IF_MASK);
+ EUSART_IntClear(EUSART0, _EUSART_IF_MASK);
+
+ // APP IRQ
+ Sys_clearFastAppIrq(EUSART0_TX_IRQn);
+ Sys_enableFastAppIrq(EUSART0_TX_IRQn,
+ APP_LIB_SYSTEM_IRQ_PRIO_HI,
+ EUSART_TX_IRQHandler);
+
+ EUSART_Enable(EUSART0, eusartEnableTx);
+
+ CMU_ClockEnable(cmuClock_EUSART0, false);
+
+ return true;
+}
+
+void Usart_setEnabled(bool enabled)
+{
+ Sys_enterCriticalSection();
+ if(enabled)
+ {
+ // Detect if someone is enabling UART but not disabling it ever
+ if(m_enabled == 0)
+ {
+ // Enable clock
+ CMU_ClockEnable(cmuClock_EUSART0, true);
+ // Disable deep sleep
+ DS_Disable(DS_SOURCE_USART);
+ // Set output
+ hal_gpio_set_mode(BOARD_USART_TX_PORT,
+ BOARD_USART_TX_PIN,
+ GPIO_MODE_OUT_PP);
+ }
+ m_enabled++;
+ }
+ else
+ {
+ if (m_enabled > 0)
+ {
+ m_enabled--;
+ }
+ if(m_enabled == 0)
+ {
+ // Set light pullup
+ hal_gpio_set_mode(BOARD_USART_TX_PORT,
+ BOARD_USART_TX_PIN,
+ GPIO_MODE_IN_PULL);
+ hal_gpio_set(BOARD_USART_TX_PORT,
+ BOARD_USART_TX_PIN);
+ // Enable deep sleep
+ DS_Enable(DS_SOURCE_USART);
+ // Disable clock
+ CMU_ClockEnable(cmuClock_EUSART0, false);
+ }
+ }
+ Sys_exitCriticalSection();
+}
+
+void Usart_receiverOn(void)
+{
+ EUSART_Enable(EUSART0, eusartEnable);
+}
+
+void Usart_receiverOff(void)
+{
+ EUSART_Enable(EUSART0, eusartEnableTx);
+}
+
+bool Usart_setFlowControl(uart_flow_control_e flow)
+{
+ (void)flow;
+ return false;
+}
+
+uint32_t Usart_sendBuffer(const void * buffer, uint32_t length)
+{
+ bool empty = false;
+ uint32_t size_in = length;
+ uint8_t * data_out = (uint8_t *)buffer;
+ Sys_enterCriticalSection();
+
+ // Return if the ring buffer cannot contain the bytes to be transmitted
+ if (Ringbuffer_free(m_usart_tx_buffer) < length)
+ {
+ size_in = 0;
+ }
+ else
+ {
+ empty = (Ringbuffer_usage(m_usart_tx_buffer) == 0);
+ while(length--)
+ {
+ Ringbuffer_getHeadByte(m_usart_tx_buffer) = *data_out++;
+ Ringbuffer_incrHead(m_usart_tx_buffer, 1);
+ }
+ if (empty)
+ {
+ Usart_setEnabled(true);
+ EUSART_IntEnable(EUSART0, EUSART_IF_TXC);
+ while ((EUSART_StatusGet(EUSART0) & EUSART_STATUS_TXFL) && (Ringbuffer_usage(m_usart_tx_buffer) != 0))
+ {
+ EUSART_Tx(EUSART0, Ringbuffer_getTailByte(m_usart_tx_buffer));
+ Ringbuffer_incrTail(m_usart_tx_buffer, 1);
+ }
+ m_tx_active = true;
+ }
+ }
+ Sys_exitCriticalSection();
+ return size_in;
+}
+
+void Usart_enableReceiver(serial_rx_callback_f rx_callback)
+{
+ Sys_enterCriticalSection();
+ // Set callback
+ m_rx_callback = rx_callback;
+ // Enable clock
+ CMU_ClockEnable(cmuClock_EUSART0, true);
+ if(rx_callback)
+ {
+ Sys_enableFastAppIrq(EUSART0_RX_IRQn,
+ APP_LIB_SYSTEM_IRQ_PRIO_HI,
+ EUSART_RX_IRQHandler);
+
+ EUSART_IntEnable(EUSART0, EUSART_IF_RXFL);
+
+ // Set light pull-up resistor
+ hal_gpio_set_mode(BOARD_USART_RX_PORT,
+ BOARD_USART_RX_PIN,
+ GPIO_MODE_IN_PULL);
+ hal_gpio_set(BOARD_USART_RX_PORT,
+ BOARD_USART_RX_PIN);
+ }
+ else
+ {
+ Sys_disableAppIrq(EUSART0_RX_IRQn);
+
+ EUSART_IntDisable(EUSART0, EUSART_IF_RXFL);
+
+ // Disable input & input pull-up resistor
+ hal_gpio_set_mode(BOARD_USART_RX_PORT,
+ BOARD_USART_RX_PIN,
+ GPIO_MODE_DISABLED);
+ hal_gpio_clear(BOARD_USART_RX_PORT,
+ BOARD_USART_RX_PIN);
+ }
+ EUSART_IntClear(EUSART0, EUSART_IF_RXFL);
+ CMU_ClockEnable(cmuClock_EUSART0, false);
+ Sys_clearFastAppIrq(EUSART0_RX_IRQn);
+ Sys_exitCriticalSection();
+}
+
+uint32_t Usart_getMTUSize(void)
+{
+ return BUFFER_SIZE;
+}
+
+void Usart_flush(void)
+{
+ volatile uint32_t timeout = 20000;
+ while(m_tx_active && timeout > 0)
+ {
+ timeout--;
+ }
+}
+
+void __attribute__((__interrupt__)) EUSART_RX_IRQHandler(void)
+{
+ // Data received
+ uint16_t ch = EUSART0->RXDATA;
+ // RXFULL must be explicitly cleared
+ EUSART_IntClear(EUSART0, EUSART_IF_RXFL);
+
+ if (m_rx_callback != NULL)
+ {
+ m_rx_callback((uint8_t *) &ch, 1);
+ }
+}
+
+void __attribute__((__interrupt__)) EUSART_TX_IRQHandler(void)
+{
+ EUSART_IntClear(EUSART0, EUSART_IF_TXC);
+
+ if (Ringbuffer_usage(m_usart_tx_buffer) == 0)
+ {
+ // when buffer becomes empty, reset indexes
+ EUSART_IntDisable(EUSART0, EUSART_IF_TXC);
+ Usart_setEnabled(false);
+ m_tx_active = false;
+ return;
+ }
+
+ while ((EUSART_StatusGet(EUSART0) & EUSART_STATUS_TXFL) && (Ringbuffer_usage(m_usart_tx_buffer) != 0))
+ {
+ EUSART_Tx(EUSART0, Ringbuffer_getTailByte(m_usart_tx_buffer));
+ Ringbuffer_incrTail(m_usart_tx_buffer, 1);
+ }
+}
diff --git a/mcu/efr/efr32/hal/usart/series1/board_usart.h b/mcu/efr/efr32/hal/usart/series1/board_usart.h
new file mode 100644
index 00000000..8ac495c9
--- /dev/null
+++ b/mcu/efr/efr32/hal/usart/series1/board_usart.h
@@ -0,0 +1,60 @@
+/* Copyright 2020 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+
+#ifndef BOARD_USART_H_
+#define BOARD_USART_H_
+
+// Map some registers constant to the USART selected
+#if BOARD_USART_ID == 0
+#define BOARD_USART USART0
+#define BOARD_USART_CMU_BIT CMU_HFPERCLKEN0_USART0
+#define BOARD_UART_RX_IRQn USART0_RX_IRQn
+#define BOARD_UART_TX_IRQn USART0_TX_IRQn
+#define BOARD_UART_LDMA_RX ldmaPeripheralSignal_USART0_RXDATAV
+#define BOARD_UART_LDMA_TX ldmaPeripheralSignal_USART0_TXEMPTY
+#elif BOARD_USART_ID == 1
+#define BOARD_USART USART1
+#define BOARD_USART_CMU_BIT CMU_HFPERCLKEN0_USART1
+#define BOARD_UART_RX_IRQn USART1_RX_IRQn
+#define BOARD_UART_TX_IRQn USART1_TX_IRQn
+#define BOARD_UART_LDMA_RX ldmaPeripheralSignal_USART1_RXDATAV
+#define BOARD_UART_LDMA_TX ldmaPeripheralSignal_USART1_TXEMPTY
+#elif BOARD_USART_ID == 2
+#define BOARD_USART USART2
+#define BOARD_USART_CMU_BIT CMU_HFPERCLKEN0_USART2
+#define BOARD_UART_RX_IRQn USART2_RX_IRQn
+#define BOARD_UART_TX_IRQn USART2_TX_IRQn
+#define BOARD_UART_LDMA_RX ldmaPeripheralSignal_USART2_RXDATAV
+#define BOARD_UART_LDMA_TX ldmaPeripheralSignal_USART2_TXEMPTY
+#elif BOARD_USART_ID == 3
+#define BOARD_USART USART3
+#define BOARD_USART_CMU_BIT CMU_HFPERCLKEN0_USART3
+#define BOARD_UART_RX_IRQn USART3_RX_IRQn
+#define BOARD_UART_TX_IRQn USART3_TX_IRQn
+#define BOARD_UART_LDMA_RX ldmaPeripheralSignal_USART3_RXDATAV
+#define BOARD_UART_LDMA_TX ldmaPeripheralSignal_USART3_TXEMPTY
+#else // BOARD_USART_ID
+#error USART ID must be 0, 1, 2 or 3
+#endif // BOARD_USART_ID
+#define BOARD_USART_ROUTE BOARD_USART->ROUTELOC0 = BOARD_USART_ROUTELOC_RXLOC | \
+ BOARD_USART_ROUTELOC_TXLOC
+#define BOARD_USART_PINS BOARD_USART->ROUTEPEN = USART_ROUTEPEN_RXPEN | \
+ USART_ROUTEPEN_TXPEN
+#define BOARD_USART_CLR_IRQ_ALL BOARD_USART->IFC = _USART_IFC_MASK
+#define BOARD_USART_CLR_IRQ_RXFULL BOARD_USART->IFC = USART_IFC_RXFULL
+#define BOARD_USART_CLR_IRQ_TXC BOARD_USART->IFC = _USART_IFC_TXC_MASK
+#define BOARD_USART_CLR_IRQ_TCMP1 BOARD_USART->IFC = USART_IFC_TCMP1
+#define BOARD_USART_LDMA_CLR_IRQ LDMA->IFC
+#define BOARD_USART_LDMA_ENABLE // TODO: Change to LDMA_Init()
+#define BOARD_USART_LDMA_DISABLE // TODO: Change to LDMA_DeInit()
+#define BOARD_USART_ENABLE_USART_CLK CMU->HFPERCLKEN0 |= BOARD_USART_CMU_BIT
+#define BOARD_USART_DISABLE_USART_CLK CMU->HFPERCLKEN0 &= ~(BOARD_USART_CMU_BIT)
+#define BOARD_USART_ENABLE_LDMA_CLK CMU->HFBUSCLKEN0 |= CMU_HFBUSCLKEN0_LDMA
+#define BOARD_USART_DISABLE_LDMA_CLK CMU->HFBUSCLKEN0 &= ~(CMU_HFBUSCLKEN0_LDMA)
+#define BOARD_USART_ENABLE_GPIO_CLK CMU->HFBUSCLKEN0 |= CMU_HFBUSCLKEN0_GPIO
+#define BOARD_USART_DISABLE_GPIO_CLK CMU->HFBUSCLKEN0 &= ~(CMU_HFBUSCLKEN0_GPIO)
+
+#endif // BOARD_USART_H_
diff --git a/mcu/efr/efr32/hal/usart/series2/board_usart.h b/mcu/efr/efr32/hal/usart/series2/board_usart.h
new file mode 100644
index 00000000..0aa36974
--- /dev/null
+++ b/mcu/efr/efr32/hal/usart/series2/board_usart.h
@@ -0,0 +1,61 @@
+/* Copyright 2020 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+
+#ifndef BOARD_USART_H_
+#define BOARD_USART_H_
+
+// Map some registers constant to the USART selected
+#if BOARD_USART_ID == 0
+#define BOARD_USART USART0
+#define BOARD_USART_CMU_BIT CMU_CLKEN0_USART0
+#define BOARD_USARTINPUT PRS->CONSUMER_USART0_RX
+#define BOARD_USARTROUTE GPIO->USARTROUTE[0]
+#define BOARD_UART_RX_IRQn USART0_RX_IRQn
+#define BOARD_UART_TX_IRQn USART0_TX_IRQn
+#define BOARD_UART_LDMA_RX ldmaPeripheralSignal_USART0_RXDATAV
+#define BOARD_UART_LDMA_TX ldmaPeripheralSignal_USART0_TXEMPTY
+#elif BOARD_USART_ID == 1
+#define BOARD_USART USART1
+#define BOARD_USART_CMU_BIT CMU_CLKEN0_USART1
+#define BOARD_USARTINPUT PRS->CONSUMER_USART1_RX
+#define BOARD_USARTROUTE GPIO->USARTROUTE[1]
+#define BOARD_UART_RX_IRQn USART1_RX_IRQn
+#define BOARD_UART_TX_IRQn USART1_TX_IRQn
+#define BOARD_UART_LDMA_RX ldmaPeripheralSignal_USART1_RXDATAV
+#define BOARD_UART_LDMA_TX ldmaPeripheralSignal_USART1_TXEMPTY
+#else // BOARD_USART_ID
+#error USART ID must be 0 or 1
+#endif // BOARD_USART_ID
+#define BOARD_USART_ROUTE BOARD_USARTROUTE.RXROUTE = BOARD_USART_RX_PIN << _GPIO_USART_RXROUTE_PIN_SHIFT | \
+ BOARD_USART_RX_PORT << _GPIO_USART_RXROUTE_PORT_SHIFT; \
+ BOARD_USARTROUTE.TXROUTE = BOARD_USART_TX_PIN << _GPIO_USART_RXROUTE_PIN_SHIFT | \
+ BOARD_USART_TX_PORT << _GPIO_USART_RXROUTE_PORT_SHIFT
+#define BOARD_USART_PINS BOARD_USARTROUTE.ROUTEEN = GPIO_USART_ROUTEEN_RXPEN | \
+ GPIO_USART_ROUTEEN_TXPEN
+#define BOARD_USART_CLR_IRQ_ALL BOARD_USART->IF_CLR = _USART_IF_MASK
+#define BOARD_USART_CLR_IRQ_RXFULL BOARD_USART->IF_CLR = USART_IF_RXFULL
+#define BOARD_USART_CLR_IRQ_TXC BOARD_USART->IF_CLR = _USART_IF_TXC_MASK
+#define BOARD_USART_CLR_IRQ_TCMP1 BOARD_USART->IF_CLR = USART_IF_TCMP1
+#define BOARD_USART_LDMA_CLR_IRQ LDMA->IF_CLR
+#define BOARD_USART_LDMA_ENABLE LDMA->EN = LDMA_EN_EN // TODO: Change to LDMA_Init()
+#define BOARD_USART_LDMA_DISABLE LDMA->EN = 0 // TODO: Change to LDMA_DeInit()
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 1)
+#define BOARD_USART_ENABLE_USART_CLK
+#define BOARD_USART_DISABLE_USART_CLK
+#define BOARD_USART_ENABLE_LDMA_CLK
+#define BOARD_USART_DISABLE_LDMA_CLK
+#define BOARD_USART_ENABLE_GPIO_CLK
+#define BOARD_USART_DISABLE_GPIO_CLK
+#else
+#define BOARD_USART_ENABLE_USART_CLK CMU->CLKEN0_SET = BOARD_USART_CMU_BIT
+#define BOARD_USART_DISABLE_USART_CLK CMU->CLKEN0_CLR = BOARD_USART_CMU_BIT
+#define BOARD_USART_ENABLE_LDMA_CLK CMU->CLKEN0_SET = CMU_CLKEN0_LDMA | CMU_CLKEN0_LDMAXBAR
+#define BOARD_USART_DISABLE_LDMA_CLK CMU->CLKEN0_CLR = CMU_CLKEN0_LDMA | CMU_CLKEN0_LDMAXBAR
+#define BOARD_USART_ENABLE_GPIO_CLK CMU->CLKEN0_SET = CMU_CLKEN0_GPIO | CMU_CLKEN0_PRS
+#define BOARD_USART_DISABLE_GPIO_CLK CMU->CLKEN0_CLR = CMU_CLKEN0_GPIO | CMU_CLKEN0_PRS
+#endif // (_SILICON_LABS_32B_SERIES_2_CONFIG == 1)
+
+#endif // BOARD_USART_H_
diff --git a/mcu/efr/efr32/hal/usart.c b/mcu/efr/efr32/hal/usart/usart.c
similarity index 88%
rename from mcu/efr/efr32/hal/usart.c
rename to mcu/efr/efr32/hal/usart/usart.c
index d3ab7504..f0e46719 100644
--- a/mcu/efr/efr32/hal/usart.c
+++ b/mcu/efr/efr32/hal/usart/usart.c
@@ -12,6 +12,7 @@
#include "board.h"
#include "board_usart.h"
#include "api.h"
+#include "gpio.h"
#include "em_cmu.h"
#include "em_gpio.h"
@@ -38,6 +39,14 @@ void __attribute__((__interrupt__)) USART_TX_IRQHandler(void);
bool Usart_init(uint32_t baudrate, uart_flow_control_e flow_control)
{
+#ifdef BOARD_GPIO_ID_VCOM_ENABLE
+ const gpio_out_cfg_t usart_vcom_enable_cfg =
+ {
+ .out_mode_cfg = GPIO_OUT_MODE_PUSH_PULL,
+ .level_default = GPIO_LEVEL_HIGH
+ };
+#endif
+
#ifdef BOARD_USART_FORCE_BAUDRATE
// Some hardware only support a given speed, so override the chosen baudrate
baudrate = BOARD_USART_FORCE_BAUDRATE;
@@ -47,33 +56,10 @@ bool Usart_init(uint32_t baudrate, uart_flow_control_e flow_control)
// Enable GPIO clock
BOARD_USART_ENABLE_GPIO_CLK;
-#ifdef BOARD_USART_VCOM_PORT
+#ifdef BOARD_GPIO_ID_VCOM_ENABLE
// Enable vcom
- hal_gpio_set_mode(BOARD_USART_VCOM_PORT,
- BOARD_USART_VCOM_PIN,
- GPIO_MODE_DISABLED);
- hal_gpio_clear(BOARD_USART_VCOM_PORT,
- BOARD_USART_VCOM_PIN);
- hal_gpio_set_mode(BOARD_USART_VCOM_PORT,
- BOARD_USART_VCOM_PIN,
- GPIO_MODE_OUT_PP);
- hal_gpio_set(BOARD_USART_VCOM_PORT,
- BOARD_USART_VCOM_PIN);
+ Gpio_outputSetCfg(BOARD_GPIO_ID_VCOM_ENABLE, &usart_vcom_enable_cfg);
#endif
-
- // uart_tx_pin
- hal_gpio_set_mode(BOARD_USART_GPIO_PORT,
- BOARD_USART_TX_PIN,
- GPIO_MODE_DISABLED);
- hal_gpio_clear(BOARD_USART_GPIO_PORT,
- BOARD_USART_TX_PIN);
- // uart_rx_pin
- hal_gpio_set_mode(BOARD_USART_GPIO_PORT,
- BOARD_USART_RX_PIN,
- GPIO_MODE_DISABLED);
- hal_gpio_clear(BOARD_USART_GPIO_PORT,
- BOARD_USART_RX_PIN);
-
// Module variables
Ringbuffer_reset(m_usart_tx_buffer);
m_rx_callback = NULL;
@@ -98,6 +84,19 @@ bool Usart_init(uint32_t baudrate, uart_flow_control_e flow_control)
USART_init.hwFlowControl = usartHwFlowControlNone;
USART_InitAsync(BOARD_USART, &USART_init);
+ // Set UART TX GPIO
+ hal_gpio_set_mode(BOARD_USART_TX_PORT,
+ BOARD_USART_TX_PIN,
+ GPIO_MODE_DISABLED);
+ hal_gpio_clear(BOARD_USART_TX_PORT,
+ BOARD_USART_TX_PIN);
+ // Set UART RX GPIO
+ hal_gpio_set_mode(BOARD_USART_RX_PORT,
+ BOARD_USART_RX_PIN,
+ GPIO_MODE_DISABLED);
+ hal_gpio_clear(BOARD_USART_RX_PORT,
+ BOARD_USART_RX_PIN);
+
// Set UART route
BOARD_USART_ROUTE;
@@ -136,7 +135,7 @@ void Usart_setEnabled(bool enabled)
// Disable deep sleep
DS_Disable(DS_SOURCE_USART);
// Set output
- hal_gpio_set_mode(BOARD_USART_GPIO_PORT,
+ hal_gpio_set_mode(BOARD_USART_TX_PORT,
BOARD_USART_TX_PIN,
GPIO_MODE_OUT_PP);
}
@@ -151,10 +150,10 @@ void Usart_setEnabled(bool enabled)
if(m_enabled == 0)
{
// Set light pullup
- hal_gpio_set_mode(BOARD_USART_GPIO_PORT,
+ hal_gpio_set_mode(BOARD_USART_TX_PORT,
BOARD_USART_TX_PIN,
GPIO_MODE_IN_PULL);
- hal_gpio_set(BOARD_USART_GPIO_PORT,
+ hal_gpio_set(BOARD_USART_TX_PORT,
BOARD_USART_TX_PIN);
// Enable deep sleep
DS_Enable(DS_SOURCE_USART);
@@ -225,22 +224,22 @@ void Usart_enableReceiver(serial_rx_callback_f rx_callback)
USART_RX_IRQHandler);
BUS_RegBitWrite(&(BOARD_USART->IEN), _USART_IEN_RXDATAV_SHIFT, 1);
// Set light pull-up resistor
- hal_gpio_set_mode(BOARD_USART_GPIO_PORT,
+ hal_gpio_set_mode(BOARD_USART_RX_PORT,
BOARD_USART_RX_PIN,
GPIO_MODE_IN_PULL);
- hal_gpio_set(BOARD_USART_GPIO_PORT,
+ hal_gpio_set(BOARD_USART_RX_PORT,
BOARD_USART_RX_PIN);
-
}
else
{
Sys_disableAppIrq(BOARD_UART_RX_IRQn);
BUS_RegBitWrite(&(BOARD_USART->IEN), _USART_IEN_RXDATAV_SHIFT, 0);
- hal_gpio_set_mode(BOARD_USART_GPIO_PORT,
+ // Disable input & input pull-up resistor
+ hal_gpio_set_mode(BOARD_USART_RX_PORT,
BOARD_USART_RX_PIN,
GPIO_MODE_DISABLED);
- // Disable pull-up for disabled GPIO:s
- hal_gpio_clear(BOARD_USART_GPIO_PORT,
+ // Disable pull-up for disabled GPIO
+ hal_gpio_clear(BOARD_USART_RX_PORT,
BOARD_USART_RX_PIN);
}
// Clear all interrupts
diff --git a/mcu/efr/efr32/hal/usart_dma.c b/mcu/efr/efr32/hal/usart/usart_dma.c
similarity index 94%
rename from mcu/efr/efr32/hal/usart_dma.c
rename to mcu/efr/efr32/hal/usart/usart_dma.c
index 357844d8..59ee224b 100644
--- a/mcu/efr/efr32/hal/usart_dma.c
+++ b/mcu/efr/efr32/hal/usart/usart_dma.c
@@ -11,6 +11,7 @@
#include "board.h"
#include "board_usart.h"
#include "api.h"
+#include "gpio.h"
#include "em_cmu.h"
#include "em_gpio.h"
@@ -66,6 +67,14 @@ static LDMA_Descriptor_t m_tx_dma_descriptor[3];
bool Usart_init(uint32_t baudrate, uart_flow_control_e flow_control)
{
+#ifdef BOARD_GPIO_ID_VCOM_ENABLE
+ const gpio_out_cfg_t usart_vcom_enable_cfg =
+ {
+ .out_mode_cfg = GPIO_OUT_MODE_PUSH_PULL,
+ .level_default = GPIO_LEVEL_HIGH
+ };
+#endif
+
#ifdef BOARD_USART_FORCE_BAUDRATE
// Some hardware only support a given speed, so override the chosen baudrate
baudrate = BOARD_USART_FORCE_BAUDRATE;
@@ -75,33 +84,11 @@ bool Usart_init(uint32_t baudrate, uart_flow_control_e flow_control)
// Enable GPIO clock
BOARD_USART_ENABLE_GPIO_CLK;
-#ifdef BOARD_USART_VCOM_PORT
+#ifdef BOARD_GPIO_ID_VCOM_ENABLE
// Enable vcom
- hal_gpio_set_mode(BOARD_USART_VCOM_PORT,
- BOARD_USART_VCOM_PIN,
- GPIO_MODE_DISABLED);
- hal_gpio_clear(BOARD_USART_VCOM_PORT,
- BOARD_USART_VCOM_PIN);
- hal_gpio_set_mode(BOARD_USART_VCOM_PORT,
- BOARD_USART_VCOM_PIN,
- GPIO_MODE_OUT_PP);
- hal_gpio_set(BOARD_USART_VCOM_PORT,
- BOARD_USART_VCOM_PIN);
+ Gpio_outputSetCfg(BOARD_GPIO_ID_VCOM_ENABLE, &usart_vcom_enable_cfg);
#endif
- // uart_tx_pin
- hal_gpio_set_mode(BOARD_USART_GPIO_PORT,
- BOARD_USART_TX_PIN,
- GPIO_MODE_DISABLED);
- hal_gpio_clear(BOARD_USART_GPIO_PORT,
- BOARD_USART_TX_PIN);
- // uart_rx_pin
- hal_gpio_set_mode(BOARD_USART_GPIO_PORT,
- BOARD_USART_RX_PIN,
- GPIO_MODE_DISABLED);
- hal_gpio_clear(BOARD_USART_GPIO_PORT,
- BOARD_USART_RX_PIN);
-
// Module variables
m_rx_callback = NULL;
m_enabled = 0;
@@ -122,6 +109,19 @@ bool Usart_init(uint32_t baudrate, uart_flow_control_e flow_control)
USART_init.hwFlowControl = usartHwFlowControlNone;
USART_InitAsync(BOARD_USART, &USART_init);
+ // Set UART TX GPIO
+ hal_gpio_set_mode(BOARD_USART_TX_PORT,
+ BOARD_USART_TX_PIN,
+ GPIO_MODE_DISABLED);
+ hal_gpio_clear(BOARD_USART_TX_PORT,
+ BOARD_USART_TX_PIN);
+ // Set UART RX GPIO
+ hal_gpio_set_mode(BOARD_USART_RX_PORT,
+ BOARD_USART_RX_PIN,
+ GPIO_MODE_DISABLED);
+ hal_gpio_clear(BOARD_USART_RX_PORT,
+ BOARD_USART_RX_PIN);
+
// Set UART route
BOARD_USART_ROUTE;
@@ -180,7 +180,7 @@ void Usart_setEnabled(bool enabled)
// Disable deep sleep
DS_Disable(DS_SOURCE_USART);
// Set output
- hal_gpio_set_mode(BOARD_USART_GPIO_PORT,
+ hal_gpio_set_mode(BOARD_USART_TX_PORT,
BOARD_USART_TX_PIN,
GPIO_MODE_OUT_PP);
}
@@ -197,10 +197,10 @@ void Usart_setEnabled(bool enabled)
wait_end_of_tx();
// Set light pullup
- hal_gpio_set_mode(BOARD_USART_GPIO_PORT,
+ hal_gpio_set_mode(BOARD_USART_TX_PORT,
BOARD_USART_TX_PIN,
GPIO_MODE_IN_PULL);
- hal_gpio_set(BOARD_USART_GPIO_PORT,
+ hal_gpio_set(BOARD_USART_TX_PORT,
BOARD_USART_TX_PIN);
// Enable deep sleep
DS_Enable(DS_SOURCE_USART);
@@ -243,7 +243,7 @@ void Usart_receiverOff(void)
{
Sys_enterCriticalSection();
-#if defined(EFR32MG22) || defined(EFR32FG23)
+#if (_SILICON_LABS_32B_SERIES == 2) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 1)
// Stop Current DMA transfer
if (CMU->CLKEN0 & CMU_CLKEN0_LDMA)
{
@@ -502,22 +502,21 @@ void Usart_enableReceiver(serial_rx_callback_f rx_callback)
BUS_RegBitWrite(&(BOARD_USART->IEN), _USART_IEN_TCMP1_SHIFT, 1);
// Set light pull-up resistor
- hal_gpio_set_mode(BOARD_USART_GPIO_PORT,
+ hal_gpio_set_mode(BOARD_USART_RX_PORT,
BOARD_USART_RX_PIN,
GPIO_MODE_IN_PULL);
- hal_gpio_set(BOARD_USART_GPIO_PORT,
+ hal_gpio_set(BOARD_USART_RX_PORT,
BOARD_USART_RX_PIN);
-
}
else
{
Sys_disableAppIrq(BOARD_UART_RX_IRQn);
BUS_RegBitWrite(&(BOARD_USART->IEN), _USART_IEN_TCMP1_SHIFT, 0);
- hal_gpio_set_mode(BOARD_USART_GPIO_PORT,
+ hal_gpio_set_mode(BOARD_USART_RX_PORT,
BOARD_USART_RX_PIN,
GPIO_MODE_DISABLED);
- // Disable pull-up for disabled GPIO:s
- hal_gpio_clear(BOARD_USART_GPIO_PORT,
+ // Disable pull-up for disabled GPIO
+ hal_gpio_clear(BOARD_USART_RX_PORT,
BOARD_USART_RX_PIN);
}
diff --git a/mcu/efr/efr32/hal/voltage.c b/mcu/efr/efr32/hal/voltage_series_1.c
similarity index 54%
rename from mcu/efr/efr32/hal/voltage.c
rename to mcu/efr/efr32/hal/voltage_series_1.c
index afd2fddd..b0266c85 100644
--- a/mcu/efr/efr32/hal/voltage.c
+++ b/mcu/efr/efr32/hal/voltage_series_1.c
@@ -7,17 +7,12 @@
#include
#include "hal_api.h"
#include "em_cmu.h"
-/* Include only for xg21/xg22. */
-#ifndef _SILICON_LABS_32B_SERIES_1
-#include "em_iadc.h"
-#endif
/**
* \brief ADC peripheral control function.
* \param state
* true = turn peripheral clocks on, false = clocks off
*/
-#if defined(_SILICON_LABS_32B_SERIES_1)
static void adcControl(bool state)
{
if(state)
@@ -29,19 +24,6 @@ static void adcControl(bool state)
CMU->HFPERCLKEN0 &= ~(CMU_HFPERCLKEN0_ADC0);
}
}
-#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1)
-static void adcControl(bool state)
-{
- (void)state;
-}
-#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2)
-static void adcControl(bool state)
-{
- CMU_ClockEnable(cmuClock_IADC0, state);
-}
-#else
-#error "Unsupported EFR32 Series & Config"
-#endif
/**
@@ -49,13 +31,13 @@ static void adcControl(bool state)
*/
#define V_MAX_ADC 4096u
-#if defined(_SILICON_LABS_32B_SERIES_1)
/**
* \brief VBGR reference voltage
*/
#define VBG_MILLIVOLTS 5000u
+
/**
* \brief Initialize voltage measurement
*/
@@ -64,6 +46,7 @@ void Mcu_voltageInit(void)
/* Do nothing */
}
+
/**
* \brief Get current MCU voltage (platform voltage).
*
@@ -142,79 +125,3 @@ uint16_t Mcu_voltageGet(void)
vbat = (vbat * VBG_MILLIVOLTS) / V_MAX_ADC;
return vbat;
}
-
-#else // defined(_SILICON_LABS_32B_SERIES_1)
-
-/**
- * \brief VBGR reference voltage, 4*1,2V
- */
-#define VBG_MILLIVOLTS 4800u
-
-
-
-#define ADC_PORT gpioPortC
-#define ADC_PIN 3
-
-#define PRS_CHANNEL 2
-
-#define clksrcadc 9600000 // The HFXO (EM01GRPACLK) is running at 38.4 MHz.
- // The HSCLKRATE is set to 3 (DIV4).
- // CLK_SRC_ADC is 9.6 MHz
-
-
-void Mcu_voltageInit(void)
-{
-}
-
-uint16_t Mcu_voltageGet(void)
-{
- uint32_t vbat;
- IADC_Result_t adcResult;
-
- // EM01 Peripheral Group A Clock to use HFXO as source.
- CMU_ClockSelectSet(cmuClock_EM01GRPACLK, cmuSelect_HFXO);
-
- // Configure IADC Clock to use EM01GRPACLK as source.
- adcControl(true);
- CMU_ClockSelectSet(cmuClock_IADCCLK, cmuSelect_EM01GRPACLK);
-
- IADC_Init_t init = IADC_INIT_DEFAULT;
- init.srcClkPrescale = IADC_calcSrcClkPrescale(IADC0, clksrcadc, 0);
-
- IADC_AllConfigs_t initAllConfigs = IADC_ALLCONFIGS_DEFAULT;
- // Use internal 1.2V Band Gap Reference (buffered).
- initAllConfigs.configs[0].reference = iadcCfgReferenceInt1V2;
- // Divides CLK_SRC_ADC by 24 ==> 400kHz.
- initAllConfigs.configs[0].adcClkPrescale = 23;
-
- // Initialize the IADC.
- IADC_init(IADC0, &init, &initAllConfigs);
-
- // Assign pin.
- IADC_SingleInput_t initSingleInput = IADC_SINGLEINPUT_DEFAULT;
- // Avdd is attenuated by a factor of 4.
- // This is compensated by setting VBGR 4 times the reference voltage.
- initSingleInput.posInput = iadcPosInputAvdd;
-
- // Initialize the Single conversion inputs.
- IADC_InitSingle_t initSingle = IADC_INITSINGLE_DEFAULT;
- initSingle.triggerSelect = iadcTriggerSelImmediate;
- initSingle.triggerAction = iadcTriggerActionOnce;
- initSingle.start = true;
- IADC_initSingle(IADC0, &initSingle, &initSingleInput);
-
- // Wait conversion to complete.
- while(!(IADC_getStatus(IADC0) & IADC_STATUS_SINGLEFIFODV));
-
- // Get value.
- adcResult = IADC_readSingleResult(IADC0);
-
- // Save power by switching off clocks from IADC0.
- adcControl(false);
-
- // Scale result.
- vbat = (adcResult.data * VBG_MILLIVOLTS) / V_MAX_ADC;
- return vbat;
-}
-
-#endif // defined(_SILICON_LABS_32B_SERIES_1)
diff --git a/mcu/efr/efr32/hal/voltage_series_2.c b/mcu/efr/efr32/hal/voltage_series_2.c
new file mode 100644
index 00000000..d2be5c34
--- /dev/null
+++ b/mcu/efr/efr32/hal/voltage_series_2.c
@@ -0,0 +1,104 @@
+/**
+ * Copyright 2021 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+#include
+#include "hal_api.h"
+#include "em_cmu.h"
+#include "em_iadc.h"
+
+
+/**
+ * \brief ADC max value + 1 = 12bit ADC conversion, 0xFFF + 1 = 4096u
+ */
+#define V_MAX_ADC 4096u
+
+
+/**
+ * \brief VBGR reference voltage, 4*1,2V
+ */
+#define VBG_MILLIVOLTS 4800u
+
+
+/* CMU clock is divided by 4 (HSCLKRATE is set to 3). */
+#define IADC_CMU_CLOCK_DIV 4UL
+
+/* The HFXO (EM01GRPACLK) is running at 38.4 MHz or 39 MHz.
+ The HSCLKRATE is set to 3 (DIV4).
+ IADC_CLK_SRC_ADC is 9.6 MHz or 9.75 MHz */
+#define IADC_CLK_SRC_ADC (__SYSTEM_CLOCK / IADC_CMU_CLOCK_DIV)
+
+
+/**
+ * \brief ADC peripheral control function.
+ * \param state
+ * true = turn peripheral clocks on, false = clocks off
+ */
+static void adcControl(bool state)
+{
+#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 1)
+ (void)state;
+#else
+ CMU_ClockEnable(cmuClock_IADC0, state);
+#endif
+}
+
+
+void Mcu_voltageInit(void)
+{
+ /* Do nothing */
+}
+
+
+uint16_t Mcu_voltageGet(void)
+{
+ uint32_t vbat;
+ IADC_Result_t adcResult;
+
+ // EM01 Peripheral Group A Clock to use HFXO as source.
+ CMU_ClockSelectSet(cmuClock_EM01GRPACLK, cmuSelect_HFXO);
+
+ // Configure IADC Clock to use EM01GRPACLK as source.
+ adcControl(true);
+ CMU_ClockSelectSet(cmuClock_IADCCLK, cmuSelect_EM01GRPACLK);
+
+ IADC_Init_t init = IADC_INIT_DEFAULT;
+ init.srcClkPrescale = IADC_calcSrcClkPrescale(IADC0, IADC_CLK_SRC_ADC, 0);
+
+ IADC_AllConfigs_t initAllConfigs = IADC_ALLCONFIGS_DEFAULT;
+ // Use internal 1.2V Band Gap Reference (buffered).
+ initAllConfigs.configs[0].reference = iadcCfgReferenceInt1V2;
+ // Divides CLK_SRC_ADC by 24 ==> 400 kHz or 406 kHz.
+ initAllConfigs.configs[0].adcClkPrescale = 23;
+
+ // Initialize the IADC.
+ IADC_init(IADC0, &init, &initAllConfigs);
+
+ // Assign pin.
+ IADC_SingleInput_t initSingleInput = IADC_SINGLEINPUT_DEFAULT;
+ // Avdd is attenuated by a factor of 4.
+ // This is compensated by setting VBGR 4 times the reference voltage.
+ initSingleInput.posInput = iadcPosInputAvdd;
+
+ // Initialize the Single conversion inputs.
+ IADC_InitSingle_t initSingle = IADC_INITSINGLE_DEFAULT;
+ initSingle.triggerSelect = iadcTriggerSelImmediate;
+ initSingle.triggerAction = iadcTriggerActionOnce;
+ initSingle.start = true;
+ IADC_initSingle(IADC0, &initSingle, &initSingleInput);
+
+ // Wait conversion to complete.
+ while(!(IADC_getStatus(IADC0) & IADC_STATUS_SINGLEFIFODV));
+
+ // Get value.
+ adcResult = IADC_readSingleResult(IADC0);
+
+ // Save power by switching off clocks from IADC0.
+ adcControl(false);
+
+ // Scale result.
+ vbat = (adcResult.data * VBG_MILLIVOLTS) / V_MAX_ADC;
+ return vbat;
+}
diff --git a/mcu/efr/efr32/ini_files/efr32xg12pxxxf1024_app.ini b/mcu/efr/efr32/ini_files/efr32xg12pxxxf1024_app.ini
index 919ba8e9..c596982c 100644
--- a/mcu/efr/efr32/ini_files/efr32xg12pxxxf1024_app.ini
+++ b/mcu/efr/efr32/ini_files/efr32xg12pxxxf1024_app.ini
@@ -19,7 +19,7 @@
; bit 0 : store version numbers in this area (must be 1 for application area and 0 for others
; except if you know what you are doing)
; bit 1 : memory area is located in external flash
-; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user
+; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user, 6:modemfw
[area:application]
id = APP_AREA_ID ; Area ID, different for each application
diff --git a/mcu/efr/efr32/ini_files/efr32xg12pxxxf1024_wp.ini b/mcu/efr/efr32/ini_files/efr32xg12pxxxf1024_wp.ini
index 47b63fa0..51e55551 100644
--- a/mcu/efr/efr32/ini_files/efr32xg12pxxxf1024_wp.ini
+++ b/mcu/efr/efr32/ini_files/efr32xg12pxxxf1024_wp.ini
@@ -22,7 +22,7 @@ eraseblock = 2048 ; Size of individually erasable block, in bytes: 2 kB
; Flags definition:
; bit 0 : store version numbers in this area
; bit 1 : memory area is located in external flash
-; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user
+; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user, 6:modemfw
[area:bootloader]
id = 0x10000105 ; Area ID: HWM_EFR32_SP_2 | 0x10000100
diff --git a/mcu/efr/efr32/ini_files/efr32xg12pxxxf512_app.ini b/mcu/efr/efr32/ini_files/efr32xg12pxxxf512_app.ini
index b3b4fd15..d083fe30 100644
--- a/mcu/efr/efr32/ini_files/efr32xg12pxxxf512_app.ini
+++ b/mcu/efr/efr32/ini_files/efr32xg12pxxxf512_app.ini
@@ -19,7 +19,7 @@
; bit 0 : store version numbers in this area (must be 1 for application area and 0 for others
; except if you know what you are doing)
; bit 1 : memory area is located in external flash
-; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user
+; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user, 6:modemfw
[area:application]
id = APP_AREA_ID ; Area ID, different for each application
diff --git a/mcu/efr/efr32/ini_files/efr32xg12pxxxf512_wp.ini b/mcu/efr/efr32/ini_files/efr32xg12pxxxf512_wp.ini
index d16523e2..101d1578 100644
--- a/mcu/efr/efr32/ini_files/efr32xg12pxxxf512_wp.ini
+++ b/mcu/efr/efr32/ini_files/efr32xg12pxxxf512_wp.ini
@@ -22,7 +22,7 @@ eraseblock = 2048 ; Size of individually erasable block, in bytes: 2 kB
; Flags definition:
; bit 0 : store version numbers in this area
; bit 1 : memory area is located in external flash
-; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user
+; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user, 6:modemfw
[area:bootloader]
id = 0x10000107 ; Area ID: HWM_EFR32_512K_SP_2 | 0x10000100
diff --git a/mcu/efr/efr32/ini_files/efr32xg21xxxxf1024_app.ini b/mcu/efr/efr32/ini_files/efr32xg21xxxxf1024_app.ini
index 4008b1c9..b14f3a68 100644
--- a/mcu/efr/efr32/ini_files/efr32xg21xxxxf1024_app.ini
+++ b/mcu/efr/efr32/ini_files/efr32xg21xxxxf1024_app.ini
@@ -19,7 +19,7 @@
; bit 0 : store version numbers in this area (must be 1 for application area and 0 for others
; except if you know what you are doing)
; bit 1 : memory area is located in external flash
-; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user
+; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user, 6:modemfw
[area:application]
id = APP_AREA_ID ; Area ID, different for each application
diff --git a/mcu/efr/efr32/ini_files/efr32xg21xxxxf1024_wp.ini b/mcu/efr/efr32/ini_files/efr32xg21xxxxf1024_wp.ini
index debea180..3f2761b9 100644
--- a/mcu/efr/efr32/ini_files/efr32xg21xxxxf1024_wp.ini
+++ b/mcu/efr/efr32/ini_files/efr32xg21xxxxf1024_wp.ini
@@ -22,7 +22,7 @@ eraseblock = 8192 ; Size of individually erasable block, in bytes: 8 kB
; Flags definition:
; bit 0 : store version numbers in this area
; bit 1 : memory area is located in external flash
-; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user
+; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user, 6:modemfw
[area:bootloader]
id = 0x1000010A ; Area ID: HW_VARIANT_ID=0A | 0x10000100
diff --git a/mcu/efr/efr32/ini_files/efr32xg21xxxxf512_app.ini b/mcu/efr/efr32/ini_files/efr32xg21xxxxf512_app.ini
index 6aa013fb..bc1a3696 100644
--- a/mcu/efr/efr32/ini_files/efr32xg21xxxxf512_app.ini
+++ b/mcu/efr/efr32/ini_files/efr32xg21xxxxf512_app.ini
@@ -19,7 +19,7 @@
; bit 0 : store version numbers in this area (must be 1 for application area and 0 for others
; except if you know what you are doing)
; bit 1 : memory area is located in external flash
-; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user
+; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user, 6:modemfw
[area:application]
id = APP_AREA_ID ; Area ID, different for each application
diff --git a/mcu/efr/efr32/ini_files/efr32xg21xxxxf512_wp.ini b/mcu/efr/efr32/ini_files/efr32xg21xxxxf512_wp.ini
index e7105dff..c36d6ad1 100644
--- a/mcu/efr/efr32/ini_files/efr32xg21xxxxf512_wp.ini
+++ b/mcu/efr/efr32/ini_files/efr32xg21xxxxf512_wp.ini
@@ -22,7 +22,7 @@ eraseblock = 8192 ; Size of individually erasable block, in bytes: 8 kB
; Flags definition:
; bit 0 : store version numbers in this area
; bit 1 : memory area is located in external flash
-; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user
+; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user, 6:modemfw
[area:bootloader]
id = 0x1000010C ; Area ID: HW_VARIANT_ID=0C | 0x10000100
diff --git a/mcu/efr/efr32/ini_files/efr32xg21xxxxf768_app.ini b/mcu/efr/efr32/ini_files/efr32xg21xxxxf768_app.ini
index f9e10e20..aace3349 100644
--- a/mcu/efr/efr32/ini_files/efr32xg21xxxxf768_app.ini
+++ b/mcu/efr/efr32/ini_files/efr32xg21xxxxf768_app.ini
@@ -19,7 +19,7 @@
; bit 0 : store version numbers in this area (must be 1 for application area and 0 for others
; except if you know what you are doing)
; bit 1 : memory area is located in external flash
-; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user
+; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user, 6:modemfw
[area:application]
id = APP_AREA_ID ; Area ID, different for each application
diff --git a/mcu/efr/efr32/ini_files/efr32xg21xxxxf768_wp.ini b/mcu/efr/efr32/ini_files/efr32xg21xxxxf768_wp.ini
index 2a775003..3a747e7b 100644
--- a/mcu/efr/efr32/ini_files/efr32xg21xxxxf768_wp.ini
+++ b/mcu/efr/efr32/ini_files/efr32xg21xxxxf768_wp.ini
@@ -22,7 +22,7 @@ eraseblock = 8192 ; Size of individually erasable block, in bytes: 8 kB
; Flags definition:
; bit 0 : store version numbers in this area
; bit 1 : memory area is located in external flash
-; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user
+; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user, 6:modemfw
[area:bootloader]
id = 0x1000010D ; Area ID: HW_VARIANT_ID=0D | 0x10000100
diff --git a/mcu/efr/efr32/ini_files/efr32xg22xxxxf512_app.ini b/mcu/efr/efr32/ini_files/efr32xg22xxxxf512_app.ini
index 1c6b2c3c..92bc74ff 100644
--- a/mcu/efr/efr32/ini_files/efr32xg22xxxxf512_app.ini
+++ b/mcu/efr/efr32/ini_files/efr32xg22xxxxf512_app.ini
@@ -19,7 +19,7 @@
; bit 0 : store version numbers in this area (must be 1 for application area and 0 for others
; except if you know what you are doing)
; bit 1 : memory area is located in external flash
-; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user
+; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user, 6:modemfw
[area:application]
id = APP_AREA_ID ; Area ID, different for each application
diff --git a/mcu/efr/efr32/ini_files/efr32xg22xxxxf512_wp.ini b/mcu/efr/efr32/ini_files/efr32xg22xxxxf512_wp.ini
index 0b2d7a48..9e4a7222 100644
--- a/mcu/efr/efr32/ini_files/efr32xg22xxxxf512_wp.ini
+++ b/mcu/efr/efr32/ini_files/efr32xg22xxxxf512_wp.ini
@@ -22,7 +22,7 @@ eraseblock = 8192 ; Size of individually erasable block, in bytes: 8 kB
; Flags definition:
; bit 0 : store version numbers in this area
; bit 1 : memory area is located in external flash
-; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user
+; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user, 6:modemfw
[area:bootloader]
id = 0x1000010B ; Area ID: HWM_EFR32XG22 | 0x10000100
diff --git a/mcu/efr/efr32/ini_files/efr32xg23xxxxf512_app.ini b/mcu/efr/efr32/ini_files/efr32xg23xxxxf512_app.ini
index 19cffad8..532e0a5c 100644
--- a/mcu/efr/efr32/ini_files/efr32xg23xxxxf512_app.ini
+++ b/mcu/efr/efr32/ini_files/efr32xg23xxxxf512_app.ini
@@ -19,7 +19,7 @@
; bit 0 : store version numbers in this area (must be 1 for application area and 0 for others
; except if you know what you are doing)
; bit 1 : memory area is located in external flash
-; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user
+; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user, 6:modemfw
[area:application]
id = APP_AREA_ID ; Area ID, different for each application
diff --git a/mcu/efr/efr32/ini_files/efr32xg23xxxxf512_wp.ini b/mcu/efr/efr32/ini_files/efr32xg23xxxxf512_wp.ini
index 73d78293..ad2f27d6 100644
--- a/mcu/efr/efr32/ini_files/efr32xg23xxxxf512_wp.ini
+++ b/mcu/efr/efr32/ini_files/efr32xg23xxxxf512_wp.ini
@@ -22,7 +22,7 @@ eraseblock = 8192 ; Size of individually erasable block, in bytes: 8 kB
; Flags definition:
; bit 0 : store version numbers in this area
; bit 1 : memory area is located in external flash
-; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user
+; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user, 6:modemfw
[area:bootloader]
id = 0x10000113 ; Area ID: HW_VARIANT_ID=13 | 0x10000100
diff --git a/mcu/efr/efr32/ini_files/efr32xg24xxxxf1024_app.ini b/mcu/efr/efr32/ini_files/efr32xg24xxxxf1024_app.ini
new file mode 100644
index 00000000..a049e6af
--- /dev/null
+++ b/mcu/efr/efr32/ini_files/efr32xg24xxxxf1024_app.ini
@@ -0,0 +1,34 @@
+; Custom Memory areas that can be defined
+;
+; On this platform you can use up to 752 kB of internal memory starting at address 0x44000
+;
+; If you support external memory, you can also define them here with the correct flag.
+;
+; There is room for 8 areas. Wirepas uses 3 of them so 5 other ones can be defined.
+;
+; By default, two areas are defined. One to store application and a smaller one to
+; store persistent application data.
+;
+; To override this file, please copy this file under your application folder and override the
+; INI_FILE_APP variable (from the application config.mk).
+;
+; If your application is supported by multiple platforms, do not forget to have a dedicated
+; file for each of them.
+;
+; Flags definition:
+; bit 0 : store version numbers in this area (must be 1 for application area and 0 for others
+; except if you know what you are doing)
+; bit 1 : memory area is located in external flash
+; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user, 6:modemfw
+
+[area:application]
+id = APP_AREA_ID ; Area ID, different for each application
+address = 0x08044000 ; Start address: right after firmware
+length = 737280 ; Length in bytes: 720 kB, shared with scratchpad
+flags = 0x00000009 ; Store version; internal flash; application
+
+[area:app_persistent]
+id = 0x8AE573BA ; Area ID, same for all apps/platform by default
+address = 0x080F8000 ; Start address: end of app_area - 16 kB
+length = 16384 ; Length in bytes: 16 kB
+flags = 0x00000014 ; internal flash, user
diff --git a/mcu/efr/efr32/ini_files/efr32xg24xxxxf1024_wp.ini b/mcu/efr/efr32/ini_files/efr32xg24xxxxf1024_wp.ini
new file mode 100644
index 00000000..e40128e6
--- /dev/null
+++ b/mcu/efr/efr32/ini_files/efr32xg24xxxxf1024_wp.ini
@@ -0,0 +1,44 @@
+; A configuration file for genscratchpad.py
+;
+; Comments begin with ";" and are ignored.
+;
+; SiLabs EFR32xG24xxxxF1024 with 1024 kB Flash and 128 kB of RAM
+
+; Flash memory information
+[flash]
+length = 1048576 ; Length of Flash in bytes: 1024 kB
+eraseblock = 8192 ; Size of individually erasable block, in bytes: 8 kB
+
+; Memory areas where the bootloader is allowed write
+;
+; The bootloader erases an area completely before writing to it, even if data
+; from scratchpad does not fill the area entirely. It is possible to define
+; overlapping areas, to update only the application code but not its data, for
+; example.
+;
+; There is room for 8 areas. Area IDs where the top
+; bit (bit 31) is zero are reserved for Wirepas use.
+;
+; Flags definition:
+; bit 0 : store version numbers in this area
+; bit 1 : memory area is located in external flash
+; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user, 6:modemfw
+
+[area:bootloader]
+id = 0x10000116 ; Area ID: HW_VARIANT_ID=0x16 | 0x10000100
+address = 0x08000000 ; Start address: beginning of Flash
+length = 32768 ; Length in bytes: 32 kB
+flags = 0x00000000 ; Don't store version; internal flash; bootloader
+settings = 0x00007C00 ; Offset of bootloader settings from addr. (areas, keys)
+
+[area:firmware]
+id = STACK_AREA_ID ; Area ID: HW_MAGIC | 0x00000100
+address = 0x08008000 ; Start address: right after bootloader
+length = 245760 ; Length in bytes: 240 kB
+flags = 0x00000005 ; Store version; internal flash; stack
+
+[area:persistent]
+id = 0x20000016 ; Area ID: HW_VARIANT_ID=0x16 | 0x20000000
+address = 0x080FC000 ; Start address: 16 kB before end of Flash
+length = 16384 ; Length in bytes: 16 kB
+flags = 0x0000000C ; Don't store version; internal flash; persistent
diff --git a/mcu/efr/efr32/ini_files/efr32xg24xxxxf1536_app.ini b/mcu/efr/efr32/ini_files/efr32xg24xxxxf1536_app.ini
new file mode 100644
index 00000000..098f116d
--- /dev/null
+++ b/mcu/efr/efr32/ini_files/efr32xg24xxxxf1536_app.ini
@@ -0,0 +1,34 @@
+; Custom Memory areas that can be defined
+;
+; On this platform you can use up to 1264 kB of internal memory starting at address 0x44000
+;
+; If you support external memory, you can also define them here with the correct flag.
+;
+; There is room for 8 areas. Wirepas uses 3 of them so 5 other ones can be defined.
+;
+; By default, two areas are defined. One to store application and a smaller one to
+; store persistent application data.
+;
+; To override this file, please copy this file under your application folder and override the
+; INI_FILE_APP variable (from the application config.mk).
+;
+; If your application is supported by multiple platforms, do not forget to have a dedicated
+; file for each of them.
+;
+; Flags definition:
+; bit 0 : store version numbers in this area (must be 1 for application area and 0 for others
+; except if you know what you are doing)
+; bit 1 : memory area is located in external flash
+; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user, 6:modemfw
+
+[area:application]
+id = APP_AREA_ID ; Area ID, different for each application
+address = 0x08044000 ; Start address: right after firmware
+length = 1261568 ; Length in bytes: 1232 kB, shared with scratchpad
+flags = 0x00000009 ; Store version; internal flash; application
+
+[area:app_persistent]
+id = 0x8AE573BA ; Area ID, same for all apps/platform by default
+address = 0x08178000 ; Start address: end of app_area - 16 kB
+length = 16384 ; Length in bytes: 16 kB
+flags = 0x00000014 ; internal flash, user
diff --git a/mcu/efr/efr32/ini_files/efr32xg24xxxxf1536_wp.ini b/mcu/efr/efr32/ini_files/efr32xg24xxxxf1536_wp.ini
new file mode 100644
index 00000000..b937c4cf
--- /dev/null
+++ b/mcu/efr/efr32/ini_files/efr32xg24xxxxf1536_wp.ini
@@ -0,0 +1,44 @@
+; A configuration file for genscratchpad.py
+;
+; Comments begin with ";" and are ignored.
+;
+; SiLabs EFR32xG24xxxxF1536 with 1536 kB Flash and 256 kB of RAM
+
+; Flash memory information
+[flash]
+length = 1572864 ; Length of Flash in bytes: 1536 kB
+eraseblock = 8192 ; Size of individually erasable block, in bytes: 8 kB
+
+; Memory areas where the bootloader is allowed write
+;
+; The bootloader erases an area completely before writing to it, even if data
+; from scratchpad does not fill the area entirely. It is possible to define
+; overlapping areas, to update only the application code but not its data, for
+; example.
+;
+; There is room for 8 areas. Area IDs where the top
+; bit (bit 31) is zero are reserved for Wirepas use.
+;
+; Flags definition:
+; bit 0 : store version numbers in this area
+; bit 1 : memory area is located in external flash
+; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user, 6:modemfw
+
+[area:bootloader]
+id = 0x10000117 ; Area ID: HW_VARIANT_ID=0x17 | 0x10000100
+address = 0x08000000 ; Start address: beginning of Flash
+length = 32768 ; Length in bytes: 32 kB
+flags = 0x00000000 ; Don't store version; internal flash; bootloader
+settings = 0x00007C00 ; Offset of bootloader settings from addr. (areas, keys)
+
+[area:firmware]
+id = STACK_AREA_ID ; Area ID: HW_MAGIC | 0x00000100
+address = 0x08008000 ; Start address: right after bootloader
+length = 245760 ; Length in bytes: 240 kB
+flags = 0x00000005 ; Store version; internal flash; stack
+
+[area:persistent]
+id = 0x20000017 ; Area ID: HW_VARIANT_ID=0x17 | 0x20000000
+address = 0x0817C000 ; Start address: 16 kB before end of Flash
+length = 16384 ; Length in bytes: 16 kB
+flags = 0x0000000C ; Don't store version; internal flash; persistent
diff --git a/mcu/efr/efr32/linker/gcc_app_efr32xg24xxxxf1024_128.ld b/mcu/efr/efr32/linker/gcc_app_efr32xg24xxxxf1024_128.ld
new file mode 100644
index 00000000..d8761a6d
--- /dev/null
+++ b/mcu/efr/efr32/linker/gcc_app_efr32xg24xxxxf1024_128.ld
@@ -0,0 +1,112 @@
+/* Copyright 2023 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+
+SEARCH_DIR(.)
+
+/* Flash is 1024 kB and RAM is 128 kB
+ * - 256 kB of Flash is reserved by default for the application. But it is
+ * not a hard limit and could be increased. As application and scratchpad area
+ * are shared by default, if the application is too big, OTAP may be affected.
+ * Please see the Wirepas documentation about OTAP for more details
+ * - 72 kB (minus 8 bytes) of RAM can be used by the app
+ */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08044000, LENGTH = 256K /* See above note before changing length */
+ RAM (rwx) : ORIGIN = 0x2000D000, LENGTH = 72K - 8
+ INVALID (rwx) : ORIGIN = 0xFFFFFFFF, LENGTH = 0 /* Sanity check */
+}
+
+SECTIONS
+{
+ .text :
+ {
+ __text_start__ = .;
+ KEEP(*(.entrypoint))
+ KEEP(*(.app_header))
+ *(.text.*)
+ *(.text)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.vfp11_veneer)
+ *(.v4_bx)
+ *(.rodata.*)
+ *(.rodata)
+ *(.rodata1)
+ . = ALIGN(8);
+ __text_end__ = .;
+ } >FLASH
+
+ __data_src_start__ = .;
+
+ .rtt (NOLOAD):
+ {
+ /* Force placing _SEGGER_RTT control block here, if RTT tracing is on */
+ *(.rtt_cb_section)
+ . = ALIGN(8);
+ } >RAM
+
+ .data :
+ {
+ __data_start__ = .;
+ *(.ramtext)
+ *(.data.*)
+ *(.data)
+ *(.data1)
+ . = ALIGN(8);
+ __data_end__ = .;
+ } >RAM AT >FLASH
+
+ __rom_end__ = __data_src_start__ + SIZEOF(.data);
+
+ /* Total size includes persistent data, when implemented */
+ __total_size_bytes__ = __rom_end__ - __text_start__;
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss.*)
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(8);
+ __bss_end__ = .;
+ } >RAM
+
+ /* Symbols for the RAM */
+ __ram_start__ = ORIGIN(RAM);
+ __ram_end__ = ORIGIN(RAM) + LENGTH(RAM);
+
+ .invalid :
+ {
+ *(.init)
+ *(.fini)
+ *(.preinit_array)
+ *(.init_array)
+ *(.fini_array)
+ *(.ctors)
+ *(.dtors)
+ *(.jcr)
+ *(.eh_frame)
+ *(.eh_frame_hdr)
+ *(.heap*)
+ *(.tbss)
+ *(.tdata)
+ *(.tdata1)
+ *(.got)
+ *(.got.plt)
+ *(.igot.plt)
+ *(.iplt)
+ *(.rel.dyn)
+ *(.rel.iplt)
+ } >INVALID /* Linking fails if any of these sections have contents. */
+
+ /* C++ exception unwinding information is silently discarded. */
+ /DISCARD/ :
+ {
+ *(.ARM.extab)
+ *(.ARM.exidx)
+ }
+}
diff --git a/mcu/efr/efr32/linker/gcc_app_efr32xg24xxxxf1536_196.ld b/mcu/efr/efr32/linker/gcc_app_efr32xg24xxxxf1536_196.ld
new file mode 100644
index 00000000..593a1dd2
--- /dev/null
+++ b/mcu/efr/efr32/linker/gcc_app_efr32xg24xxxxf1536_196.ld
@@ -0,0 +1,112 @@
+/* Copyright 2022 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+
+SEARCH_DIR(.)
+
+/* Flash is 1536 kB and RAM is 196 kB
+ * - 256 kB of Flash is reserved by default for the application. But it is
+ * not a hard limit and could be increased. As application and scratchpad area
+ * are shared by default, if the application is too big, OTAP may be affected.
+ * Please see the Wirepas documentation about OTAP for more details
+ * - 140 kB (minus 8 bytes) of RAM can be used by the app
+ */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08044000, LENGTH = 256K /* See above note before changing length */
+ RAM (rwx) : ORIGIN = 0x2000D000, LENGTH = 140K - 8
+ INVALID (rwx) : ORIGIN = 0xFFFFFFFF, LENGTH = 0 /* Sanity check */
+}
+
+SECTIONS
+{
+ .text :
+ {
+ __text_start__ = .;
+ KEEP(*(.entrypoint))
+ KEEP(*(.app_header))
+ *(.text.*)
+ *(.text)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.vfp11_veneer)
+ *(.v4_bx)
+ *(.rodata.*)
+ *(.rodata)
+ *(.rodata1)
+ . = ALIGN(8);
+ __text_end__ = .;
+ } >FLASH
+
+ __data_src_start__ = .;
+
+ .rtt (NOLOAD):
+ {
+ /* Force placing _SEGGER_RTT control block here, if RTT tracing is on */
+ *(.rtt_cb_section)
+ . = ALIGN(8);
+ } >RAM
+
+ .data :
+ {
+ __data_start__ = .;
+ *(.ramtext)
+ *(.data.*)
+ *(.data)
+ *(.data1)
+ . = ALIGN(8);
+ __data_end__ = .;
+ } >RAM AT >FLASH
+
+ __rom_end__ = __data_src_start__ + SIZEOF(.data);
+
+ /* Total size includes persistent data, when implemented */
+ __total_size_bytes__ = __rom_end__ - __text_start__;
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss.*)
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(8);
+ __bss_end__ = .;
+ } >RAM
+
+ /* Symbols for the RAM */
+ __ram_start__ = ORIGIN(RAM);
+ __ram_end__ = ORIGIN(RAM) + LENGTH(RAM);
+
+ .invalid :
+ {
+ *(.init)
+ *(.fini)
+ *(.preinit_array)
+ *(.init_array)
+ *(.fini_array)
+ *(.ctors)
+ *(.dtors)
+ *(.jcr)
+ *(.eh_frame)
+ *(.eh_frame_hdr)
+ *(.heap*)
+ *(.tbss)
+ *(.tdata)
+ *(.tdata1)
+ *(.got)
+ *(.got.plt)
+ *(.igot.plt)
+ *(.iplt)
+ *(.rel.dyn)
+ *(.rel.iplt)
+ } >INVALID /* Linking fails if any of these sections have contents. */
+
+ /* C++ exception unwinding information is silently discarded. */
+ /DISCARD/ :
+ {
+ *(.ARM.extab)
+ *(.ARM.exidx)
+ }
+}
diff --git a/mcu/efr/efr32/linker/gcc_app_efr32xg24xxxxf1536_256.ld b/mcu/efr/efr32/linker/gcc_app_efr32xg24xxxxf1536_256.ld
new file mode 100644
index 00000000..68e11979
--- /dev/null
+++ b/mcu/efr/efr32/linker/gcc_app_efr32xg24xxxxf1536_256.ld
@@ -0,0 +1,112 @@
+/* Copyright 2022 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+
+SEARCH_DIR(.)
+
+/* Flash is 1536 kB and RAM is 256 kB
+ * - 40 kB of Flash is reserved by default for the application. But it is
+ * not a hard limit and could be increased. As application and scratchpad area
+ * are shared by default, if the application is too big, OTAP may be affected.
+ * Please see the Wirepas documentation about OTAP for more details
+ * - 155 kB (minus 8 bytes) of RAM can be used by the app
+ */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08044000, LENGTH = 256K /* See above note before changing length */
+ RAM (rwx) : ORIGIN = 0x2000D000, LENGTH = 155K - 8
+ INVALID (rwx) : ORIGIN = 0xFFFFFFFF, LENGTH = 0 /* Sanity check */
+}
+
+SECTIONS
+{
+ .text :
+ {
+ __text_start__ = .;
+ KEEP(*(.entrypoint))
+ KEEP(*(.app_header))
+ *(.text.*)
+ *(.text)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.vfp11_veneer)
+ *(.v4_bx)
+ *(.rodata.*)
+ *(.rodata)
+ *(.rodata1)
+ . = ALIGN(8);
+ __text_end__ = .;
+ } >FLASH
+
+ __data_src_start__ = .;
+
+ .rtt (NOLOAD):
+ {
+ /* Force placing _SEGGER_RTT control block here, if RTT tracing is on */
+ *(.rtt_cb_section)
+ . = ALIGN(8);
+ } >RAM
+
+ .data :
+ {
+ __data_start__ = .;
+ *(.ramtext)
+ *(.data.*)
+ *(.data)
+ *(.data1)
+ . = ALIGN(8);
+ __data_end__ = .;
+ } >RAM AT >FLASH
+
+ __rom_end__ = __data_src_start__ + SIZEOF(.data);
+
+ /* Total size includes persistent data, when implemented */
+ __total_size_bytes__ = __rom_end__ - __text_start__;
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss.*)
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(8);
+ __bss_end__ = .;
+ } >RAM
+
+ /* Symbols for the RAM */
+ __ram_start__ = ORIGIN(RAM);
+ __ram_end__ = ORIGIN(RAM) + LENGTH(RAM);
+
+ .invalid :
+ {
+ *(.init)
+ *(.fini)
+ *(.preinit_array)
+ *(.init_array)
+ *(.fini_array)
+ *(.ctors)
+ *(.dtors)
+ *(.jcr)
+ *(.eh_frame)
+ *(.eh_frame_hdr)
+ *(.heap*)
+ *(.tbss)
+ *(.tdata)
+ *(.tdata1)
+ *(.got)
+ *(.got.plt)
+ *(.igot.plt)
+ *(.iplt)
+ *(.rel.dyn)
+ *(.rel.iplt)
+ } >INVALID /* Linking fails if any of these sections have contents. */
+
+ /* C++ exception unwinding information is silently discarded. */
+ /DISCARD/ :
+ {
+ *(.ARM.extab)
+ *(.ARM.exidx)
+ }
+}
diff --git a/mcu/efr/efr32/linker/gcc_bl_efr32xg12pxxxf1024.ld b/mcu/efr/efr32/linker/gcc_bl_efr32xg12pxxxf1024.ld
index 01497a6b..788fae75 100644
--- a/mcu/efr/efr32/linker/gcc_bl_efr32xg12pxxxf1024.ld
+++ b/mcu/efr/efr32/linker/gcc_bl_efr32xg12pxxxf1024.ld
@@ -63,6 +63,7 @@ SECTIONS
*scratchpad.*o*(.data* .data)
*internal_flash*.*o*(.data* .data)
*external_flash*.*o*(.data* .data)
+ *debug_flow*.*o*(.data* .data)
/* Customer specific external flash driver must be located in
* board/board_name/bootloader folder.
*/
@@ -79,6 +80,7 @@ SECTIONS
*scratchpad.*o*(.bss.* .bss)
*internal_flash*.*o*(.bss* .bss)
*external_flash*.*o*(.bss* .bss)
+ *debug_flow*.*o*(.bss* .bss)
/* Customer specific external flash driver must be located in
* board/board_name/bootloader folder
*/
diff --git a/mcu/efr/efr32/linker/gcc_bl_efr32xg12pxxxf512.ld b/mcu/efr/efr32/linker/gcc_bl_efr32xg12pxxxf512.ld
index 423cffb3..28d9a6f0 100644
--- a/mcu/efr/efr32/linker/gcc_bl_efr32xg12pxxxf512.ld
+++ b/mcu/efr/efr32/linker/gcc_bl_efr32xg12pxxxf512.ld
@@ -63,6 +63,7 @@ SECTIONS
*scratchpad.*o*(.data* .data)
*internal_flash*.*o*(.data* .data)
*external_flash*.*o*(.data* .data)
+ *debug_flow*.*o*(.data* .data)
/* Customer specific external flash driver must be located in
* board/board_name/bootloader folder.
*/
@@ -79,6 +80,7 @@ SECTIONS
*scratchpad.*o*(.bss.* .bss)
*internal_flash*.*o*(.bss* .bss)
*external_flash*.*o*(.bss* .bss)
+ *debug_flow*.*o*(.bss* .bss)
/* Customer specific external flash driver must be located in
* board/board_name/bootloader folder
*/
diff --git a/mcu/efr/efr32/linker/gcc_bl_efr32xg21xxxxf1024.ld b/mcu/efr/efr32/linker/gcc_bl_efr32xg21xxxxf1024.ld
index fb7c6709..166c6c08 100644
--- a/mcu/efr/efr32/linker/gcc_bl_efr32xg21xxxxf1024.ld
+++ b/mcu/efr/efr32/linker/gcc_bl_efr32xg21xxxxf1024.ld
@@ -62,6 +62,7 @@ SECTIONS
*scratchpad.*o*(.data* .data)
*internal_flash*.*o*(.data* .data)
*external_flash*.*o*(.data* .data)
+ *debug_flow*.*o*(.data* .data)
/* Customer specific external flash driver must be located in
* board/board_name/bootloader folder.
*/
@@ -78,6 +79,7 @@ SECTIONS
*scratchpad.*o*(.bss.* .bss)
*internal_flash*.*o*(.bss* .bss)
*external_flash*.*o*(.bss* .bss)
+ *debug_flow*.*o*(.bss* .bss)
/* Customer specific external flash driver must be located in
* board/board_name/bootloader folder
*/
diff --git a/mcu/efr/efr32/linker/gcc_bl_efr32xg21xxxxf512.ld b/mcu/efr/efr32/linker/gcc_bl_efr32xg21xxxxf512.ld
index 98da469e..f88b234a 100644
--- a/mcu/efr/efr32/linker/gcc_bl_efr32xg21xxxxf512.ld
+++ b/mcu/efr/efr32/linker/gcc_bl_efr32xg21xxxxf512.ld
@@ -62,6 +62,7 @@ SECTIONS
*scratchpad.*o*(.data* .data)
*internal_flash*.*o*(.data* .data)
*external_flash*.*o*(.data* .data)
+ *debug_flow*.*o*(.data* .data)
/* Customer specific external flash driver must be located in
* board/board_name/bootloader folder.
*/
@@ -78,6 +79,7 @@ SECTIONS
*scratchpad.*o*(.bss.* .bss)
*internal_flash*.*o*(.bss* .bss)
*external_flash*.*o*(.bss* .bss)
+ *debug_flow*.*o*(.bss* .bss)
/* Customer specific external flash driver must be located in
* board/board_name/bootloader folder
*/
diff --git a/mcu/efr/efr32/linker/gcc_bl_efr32xg21xxxxf768.ld b/mcu/efr/efr32/linker/gcc_bl_efr32xg21xxxxf768.ld
index 764afca1..be50c214 100644
--- a/mcu/efr/efr32/linker/gcc_bl_efr32xg21xxxxf768.ld
+++ b/mcu/efr/efr32/linker/gcc_bl_efr32xg21xxxxf768.ld
@@ -62,6 +62,7 @@ SECTIONS
*scratchpad.*o*(.data* .data)
*internal_flash*.*o*(.data* .data)
*external_flash*.*o*(.data* .data)
+ *debug_flow*.*o*(.data* .data)
/* Customer specific external flash driver must be located in
* board/board_name/bootloader folder.
*/
@@ -78,6 +79,7 @@ SECTIONS
*scratchpad.*o*(.bss.* .bss)
*internal_flash*.*o*(.bss* .bss)
*external_flash*.*o*(.bss* .bss)
+ *debug_flow*.*o*(.bss* .bss)
/* Customer specific external flash driver must be located in
* board/board_name/bootloader folder
*/
diff --git a/mcu/efr/efr32/linker/gcc_bl_efr32xg22xxxxf512.ld b/mcu/efr/efr32/linker/gcc_bl_efr32xg22xxxxf512.ld
index c3c49595..89435aa5 100644
--- a/mcu/efr/efr32/linker/gcc_bl_efr32xg22xxxxf512.ld
+++ b/mcu/efr/efr32/linker/gcc_bl_efr32xg22xxxxf512.ld
@@ -22,8 +22,8 @@ MEMORY
{
BOOTLOADER (rx) : ORIGIN = 0x00000000, LENGTH = 16K - 1K
BLCONFIG (rx) : ORIGIN = 0x00000000 + 15K, LENGTH = 1K
- BL_STATIC (rwx) : ORIGIN = 0x20000000 + 24, LENGTH = 512 - 24
- RAM (rwx) : ORIGIN = 0x20000000 + 512, LENGTH = 32K - 512
+ BL_STATIC (rwx) : ORIGIN = 0x20000000 + 24, LENGTH = 1K - 24
+ RAM (rwx) : ORIGIN = 0x20000000 + 1K, LENGTH = 32K - 1K
INVALID (rwx) : ORIGIN = 0xFFFFFFFF, LENGTH = 0
}
@@ -62,6 +62,7 @@ SECTIONS
*scratchpad.*o*(.data* .data)
*internal_flash*.*o*(.data* .data)
*external_flash*.*o*(.data* .data)
+ *debug_flow*.*o*(.data* .data)
/* Customer specific external flash driver must be located in
* board/board_name/bootloader folder.
*/
@@ -78,6 +79,7 @@ SECTIONS
*scratchpad.*o*(.bss.* .bss)
*internal_flash*.*o*(.bss* .bss)
*external_flash*.*o*(.bss* .bss)
+ *debug_flow*.*o*(.bss* .bss)
/* Customer specific external flash driver must be located in
* board/board_name/bootloader folder
*/
diff --git a/mcu/efr/efr32/linker/gcc_bl_efr32xg23xxxxf512.ld b/mcu/efr/efr32/linker/gcc_bl_efr32xg23xxxxf512.ld
index 969b3af2..18820e6a 100644
--- a/mcu/efr/efr32/linker/gcc_bl_efr32xg23xxxxf512.ld
+++ b/mcu/efr/efr32/linker/gcc_bl_efr32xg23xxxxf512.ld
@@ -62,6 +62,7 @@ SECTIONS
*scratchpad.*o*(.data* .data)
*internal_flash*.*o*(.data* .data)
*external_flash*.*o*(.data* .data)
+ *debug_flow*.*o*(.data* .data)
/* Customer specific external flash driver must be located in
* board/board_name/bootloader folder.
*/
@@ -78,6 +79,7 @@ SECTIONS
*scratchpad.*o*(.bss.* .bss)
*internal_flash*.*o*(.bss* .bss)
*external_flash*.*o*(.bss* .bss)
+ *debug_flow*.*o*(.bss* .bss)
/* Customer specific external flash driver must be located in
* board/board_name/bootloader folder
*/
diff --git a/mcu/efr/efr32/linker/gcc_bl_efr32xg24xxxxf1024_128.ld b/mcu/efr/efr32/linker/gcc_bl_efr32xg24xxxxf1024_128.ld
new file mode 100644
index 00000000..16f9791d
--- /dev/null
+++ b/mcu/efr/efr32/linker/gcc_bl_efr32xg24xxxxf1024_128.ld
@@ -0,0 +1,169 @@
+/* Copyright 2023 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+
+/* Linker script for Wirepas Connectivity bootloader on EFR32xG24xxxxF1024
+ *
+ * This file is for the 1024 kB FLASH, 128 kB RAM variant
+ *
+ * Flash is split into
+ * - Bootloader executable code (BOOTLOADER)
+ * - Bootloader config: memory areas, auth. and encryption keys (BLCONFIG)
+ * - Executable code (FLASH)
+ *
+ * Dedicated 32 kB bootloader Flash area is not used.
+ */
+
+SEARCH_DIR(.)
+
+MEMORY
+{
+ BOOTLOADER (rx) : ORIGIN = 0x08000000, LENGTH = 32K - 1K
+ BLCONFIG (rx) : ORIGIN = 0x08000000 + 31K, LENGTH = 1K
+ BL_STATIC (rwx) : ORIGIN = 0x20000000 + 24, LENGTH = 1024
+ RAM (rwx) : ORIGIN = 0x20001500, LENGTH = 128K - 0x1500
+ INVALID (rwx) : ORIGIN = 0xFFFFFFFF, LENGTH = 0
+}
+
+ENTRY(__startup__)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.Vectors))
+ __bl_version__ = .;
+ KEEP(*(.BootloaderVersion))
+ *(.romtext)
+ *(.text.*)
+ *(.text)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.vfp11_veneer)
+ *(.v4_bx)
+ *(.rodata.*)
+ *(.rodata)
+ *(.rodata1)
+ *(.crc_lut)
+ . = ALIGN(8);
+ } >BOOTLOADER
+
+ __etext = .;
+ __data_src_start__ = .;
+
+ .datastatic :
+ {
+ __datastatic_start__ = .;
+ /* ramtext is needed by the internal flash driver */
+ *(.ramtext)
+ *memoryarea.*o*(.data* .data)
+ *scratchpad.*o*(.data* .data)
+ *internal_flash*.*o*(.data* .data)
+ *external_flash*.*o*(.data* .data)
+ *debug_flow*.*o*(.data* .data)
+ /* Customer specific external flash driver must be located in
+ * board/board_name/bootloader folder.
+ */
+ *board/*/bootloader/*.*o*(.data* .data)
+ *bootloader/bl_hardware*.*o*(.data* .data)
+ . = ALIGN(8);
+ __datastatic_end__ = .;
+ } >BL_STATIC AT >BOOTLOADER
+
+ .bssstatic :
+ {
+ __bssstatic_start__ = .;
+ *memoryarea.*o*(.bss.* .bss)
+ *scratchpad.*o*(.bss.* .bss)
+ *internal_flash*.*o*(.bss* .bss)
+ *external_flash*.*o*(.bss* .bss)
+ *debug_flow*.*o*(.bss* .bss)
+ /* Customer specific external flash driver must be located in
+ * board/board_name/bootloader folder
+ */
+ *board/*/bootloader/*.*o*(.bss* .bss)
+ *bootloader/bl_hardware*.*o*(.bss* .bss)
+ /* COMMON symbols here as well */
+ *(COMMON)
+ . = ALIGN(8);
+ __bssstatic_end__ = .;
+ } >BL_STATIC
+
+ .data :
+ {
+ __data_start__ = .;
+ *(.data.*)
+ *(.data)
+ *(.data1)
+ . = ALIGN(8);
+ __data_end__ = .;
+ } >RAM AT >BOOTLOADER
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss.*)
+ *(.bss)
+ . = ALIGN(8);
+ __bss_end__ = .;
+ } >RAM
+
+ .blconfig :
+ {
+ /* Bootloader configuration (memory areas, keys) */
+ __blconfig_start__ = .;
+ . += LENGTH(BLCONFIG);
+ __blconfig_end__ = .;
+ } >BLCONFIG
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __stack_top__ = ORIGIN(RAM) + LENGTH(RAM);
+
+ /* dummy definition to meet the linker dependency in SystemInit() */
+ /* Warning: do not use this to anything! */
+ __Vectors = 0;
+
+ .invalid :
+ {
+ *(.init)
+ *(.fini)
+ *(.preinit_array)
+ *(.init_array)
+ *(.fini_array)
+ *(.ctors)
+ *(.dtors)
+ *(.jcr)
+ *(.eh_frame)
+ *(.eh_frame_hdr)
+ *(.heap*)
+ *(.tbss)
+ *(.tdata)
+ *(.tdata1)
+ *(.got)
+ *(.got.plt)
+ *(.igot.plt)
+ *(.iplt)
+ *(.rel.dyn)
+ *(.rel.iplt)
+ } >INVALID /* Linking fails if any of these sections have contents. */
+
+ /* C++ exception unwinding information is silently discarded. */
+ /DISCARD/ :
+ {
+ *(.ARM.extab)
+ *(.ARM.extab.*)
+ *(.ARM.exidx)
+ *(.ARM.exidx.*)
+ }
+}
diff --git a/mcu/efr/efr32/linker/gcc_bl_efr32xg24xxxxf1536_196.ld b/mcu/efr/efr32/linker/gcc_bl_efr32xg24xxxxf1536_196.ld
new file mode 100644
index 00000000..72748073
--- /dev/null
+++ b/mcu/efr/efr32/linker/gcc_bl_efr32xg24xxxxf1536_196.ld
@@ -0,0 +1,169 @@
+/* Copyright 2023 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+
+/* Linker script for Wirepas Connectivity bootloader on EFR32xG25xxxxF1536
+ *
+ * This file is for the 1536 kB FLASH, 196 kB RAM variant
+ *
+ * Flash is split into
+ * - Bootloader executable code (BOOTLOADER)
+ * - Bootloader config: memory areas, auth. and encryption keys (BLCONFIG)
+ * - Executable code (FLASH)
+ *
+ * Dedicated 32 kB bootloader Flash area is not used.
+ */
+
+SEARCH_DIR(.)
+
+MEMORY
+{
+ BOOTLOADER (rx) : ORIGIN = 0x08000000, LENGTH = 32K - 1K
+ BLCONFIG (rx) : ORIGIN = 0x08000000 + 31K, LENGTH = 1K
+ BL_STATIC (rwx) : ORIGIN = 0x20000000 + 24, LENGTH = 1024
+ RAM (rwx) : ORIGIN = 0x20001500, LENGTH = 196K - 0x1500
+ INVALID (rwx) : ORIGIN = 0xFFFFFFFF, LENGTH = 0
+}
+
+ENTRY(__startup__)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.Vectors))
+ __bl_version__ = .;
+ KEEP(*(.BootloaderVersion))
+ *(.romtext)
+ *(.text.*)
+ *(.text)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.vfp11_veneer)
+ *(.v4_bx)
+ *(.rodata.*)
+ *(.rodata)
+ *(.rodata1)
+ *(.crc_lut)
+ . = ALIGN(8);
+ } >BOOTLOADER
+
+ __etext = .;
+ __data_src_start__ = .;
+
+ .datastatic :
+ {
+ __datastatic_start__ = .;
+ /* ramtext is needed by the internal flash driver */
+ *(.ramtext)
+ *memoryarea.*o*(.data* .data)
+ *scratchpad.*o*(.data* .data)
+ *internal_flash*.*o*(.data* .data)
+ *external_flash*.*o*(.data* .data)
+ *debug_flow*.*o*(.data* .data)
+ /* Customer specific external flash driver must be located in
+ * board/board_name/bootloader folder.
+ */
+ *board/*/bootloader/*.*o*(.data* .data)
+ *bootloader/bl_hardware*.*o*(.data* .data)
+ . = ALIGN(8);
+ __datastatic_end__ = .;
+ } >BL_STATIC AT >BOOTLOADER
+
+ .bssstatic :
+ {
+ __bssstatic_start__ = .;
+ *memoryarea.*o*(.bss.* .bss)
+ *scratchpad.*o*(.bss.* .bss)
+ *internal_flash*.*o*(.bss* .bss)
+ *external_flash*.*o*(.bss* .bss)
+ *debug_flow*.*o*(.bss* .bss)
+ /* Customer specific external flash driver must be located in
+ * board/board_name/bootloader folder
+ */
+ *board/*/bootloader/*.*o*(.bss* .bss)
+ *bootloader/bl_hardware*.*o*(.bss* .bss)
+ /* COMMON symbols here as well */
+ *(COMMON)
+ . = ALIGN(8);
+ __bssstatic_end__ = .;
+ } >BL_STATIC
+
+ .data :
+ {
+ __data_start__ = .;
+ *(.data.*)
+ *(.data)
+ *(.data1)
+ . = ALIGN(8);
+ __data_end__ = .;
+ } >RAM AT >BOOTLOADER
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss.*)
+ *(.bss)
+ . = ALIGN(8);
+ __bss_end__ = .;
+ } >RAM
+
+ .blconfig :
+ {
+ /* Bootloader configuration (memory areas, keys) */
+ __blconfig_start__ = .;
+ . += LENGTH(BLCONFIG);
+ __blconfig_end__ = .;
+ } >BLCONFIG
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __stack_top__ = ORIGIN(RAM) + LENGTH(RAM);
+
+ /* dummy definition to meet the linker dependency in SystemInit() */
+ /* Warning: do not use this to anything! */
+ __Vectors = 0;
+
+ .invalid :
+ {
+ *(.init)
+ *(.fini)
+ *(.preinit_array)
+ *(.init_array)
+ *(.fini_array)
+ *(.ctors)
+ *(.dtors)
+ *(.jcr)
+ *(.eh_frame)
+ *(.eh_frame_hdr)
+ *(.heap*)
+ *(.tbss)
+ *(.tdata)
+ *(.tdata1)
+ *(.got)
+ *(.got.plt)
+ *(.igot.plt)
+ *(.iplt)
+ *(.rel.dyn)
+ *(.rel.iplt)
+ } >INVALID /* Linking fails if any of these sections have contents. */
+
+ /* C++ exception unwinding information is silently discarded. */
+ /DISCARD/ :
+ {
+ *(.ARM.extab)
+ *(.ARM.extab.*)
+ *(.ARM.exidx)
+ *(.ARM.exidx.*)
+ }
+}
diff --git a/mcu/efr/efr32/linker/gcc_bl_efr32xg24xxxxf1536_256.ld b/mcu/efr/efr32/linker/gcc_bl_efr32xg24xxxxf1536_256.ld
new file mode 100644
index 00000000..5c92bf89
--- /dev/null
+++ b/mcu/efr/efr32/linker/gcc_bl_efr32xg24xxxxf1536_256.ld
@@ -0,0 +1,169 @@
+/* Copyright 2023 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+
+/* Linker script for Wirepas Connectivity bootloader on EFR32xG25xxxxF1536
+ *
+ * This file is for the 1536 kB FLASH, 256 kB RAM variant
+ *
+ * Flash is split into
+ * - Bootloader executable code (BOOTLOADER)
+ * - Bootloader config: memory areas, auth. and encryption keys (BLCONFIG)
+ * - Executable code (FLASH)
+ *
+ * Dedicated 32 kB bootloader Flash area is not used.
+ */
+
+SEARCH_DIR(.)
+
+MEMORY
+{
+ BOOTLOADER (rx) : ORIGIN = 0x08000000, LENGTH = 32K - 1K
+ BLCONFIG (rx) : ORIGIN = 0x08000000 + 31K, LENGTH = 1K
+ BL_STATIC (rwx) : ORIGIN = 0x20000000 + 24, LENGTH = 1024
+ RAM (rwx) : ORIGIN = 0x20001500, LENGTH = 256K - 0x1500
+ INVALID (rwx) : ORIGIN = 0xFFFFFFFF, LENGTH = 0
+}
+
+ENTRY(__startup__)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.Vectors))
+ __bl_version__ = .;
+ KEEP(*(.BootloaderVersion))
+ *(.romtext)
+ *(.text.*)
+ *(.text)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.vfp11_veneer)
+ *(.v4_bx)
+ *(.rodata.*)
+ *(.rodata)
+ *(.rodata1)
+ *(.crc_lut)
+ . = ALIGN(8);
+ } >BOOTLOADER
+
+ __etext = .;
+ __data_src_start__ = .;
+
+ .datastatic :
+ {
+ __datastatic_start__ = .;
+ /* ramtext is needed by the internal flash driver */
+ *(.ramtext)
+ *memoryarea.*o*(.data* .data)
+ *scratchpad.*o*(.data* .data)
+ *internal_flash*.*o*(.data* .data)
+ *external_flash*.*o*(.data* .data)
+ *debug_flow*.*o*(.data* .data)
+ /* Customer specific external flash driver must be located in
+ * board/board_name/bootloader folder.
+ */
+ *board/*/bootloader/*.*o*(.data* .data)
+ *bootloader/bl_hardware*.*o*(.data* .data)
+ . = ALIGN(8);
+ __datastatic_end__ = .;
+ } >BL_STATIC AT >BOOTLOADER
+
+ .bssstatic :
+ {
+ __bssstatic_start__ = .;
+ *memoryarea.*o*(.bss.* .bss)
+ *scratchpad.*o*(.bss.* .bss)
+ *internal_flash*.*o*(.bss* .bss)
+ *external_flash*.*o*(.bss* .bss)
+ *debug_flow*.*o*(.bss* .bss)
+ /* Customer specific external flash driver must be located in
+ * board/board_name/bootloader folder
+ */
+ *board/*/bootloader/*.*o*(.bss* .bss)
+ *bootloader/bl_hardware*.*o*(.bss* .bss)
+ /* COMMON symbols here as well */
+ *(COMMON)
+ . = ALIGN(8);
+ __bssstatic_end__ = .;
+ } >BL_STATIC
+
+ .data :
+ {
+ __data_start__ = .;
+ *(.data.*)
+ *(.data)
+ *(.data1)
+ . = ALIGN(8);
+ __data_end__ = .;
+ } >RAM AT >BOOTLOADER
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss.*)
+ *(.bss)
+ . = ALIGN(8);
+ __bss_end__ = .;
+ } >RAM
+
+ .blconfig :
+ {
+ /* Bootloader configuration (memory areas, keys) */
+ __blconfig_start__ = .;
+ . += LENGTH(BLCONFIG);
+ __blconfig_end__ = .;
+ } >BLCONFIG
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __stack_top__ = ORIGIN(RAM) + LENGTH(RAM);
+
+ /* dummy definition to meet the linker dependency in SystemInit() */
+ /* Warning: do not use this to anything! */
+ __Vectors = 0;
+
+ .invalid :
+ {
+ *(.init)
+ *(.fini)
+ *(.preinit_array)
+ *(.init_array)
+ *(.fini_array)
+ *(.ctors)
+ *(.dtors)
+ *(.jcr)
+ *(.eh_frame)
+ *(.eh_frame_hdr)
+ *(.heap*)
+ *(.tbss)
+ *(.tdata)
+ *(.tdata1)
+ *(.got)
+ *(.got.plt)
+ *(.igot.plt)
+ *(.iplt)
+ *(.rel.dyn)
+ *(.rel.iplt)
+ } >INVALID /* Linking fails if any of these sections have contents. */
+
+ /* C++ exception unwinding information is silently discarded. */
+ /DISCARD/ :
+ {
+ *(.ARM.extab)
+ *(.ARM.extab.*)
+ *(.ARM.exidx)
+ *(.ARM.exidx.*)
+ }
+}
diff --git a/mcu/efr/makefile b/mcu/efr/makefile
index ede33893..bad3418f 100644
--- a/mcu/efr/makefile
+++ b/mcu/efr/makefile
@@ -1,5 +1,5 @@
MCU_PREFIX := $(MCU_PATH)$(MCU_FAMILY)/$(MCU)/
-MCU_CONFIG := $(MCU_PREFIX)/config.mk
+MCU_CONFIG := $(MCU_PREFIX)config.mk
MCU_COMMON := $(MCU_PATH)$(MCU_FAMILY)/common
# Add include path for nrfx vendor files
diff --git a/mcu/hal_api/button.h b/mcu/hal_api/button/button.h
similarity index 88%
rename from mcu/hal_api/button.h
rename to mcu/hal_api/button/button.h
index 33ea6e9e..7dc73028 100644
--- a/mcu/hal_api/button.h
+++ b/mcu/hal_api/button/button.h
@@ -8,6 +8,10 @@
* \file button.h
* \brief Board-independent button functions
*/
+
+#ifndef BUTTON_H_
+#define BUTTON_H_
+
#include
#include
@@ -28,6 +32,10 @@ typedef enum
BUTTON_RES_OK = 0,
/** Button id is invalid */
BUTTON_RES_INVALID_ID = 1,
+ /** Function parameter is invalid */
+ BUTTON_RES_INVALID_PARAM = 2,
+ /** Button initialization has not been performed */
+ BUTTON_RES_UNINITIALIZED = 3
} button_res_e;
/**
@@ -75,3 +83,5 @@ button_res_e Button_getState(uint8_t button_id,
* \brief Get number of buttons
*/
uint8_t Button_get_number(void);
+
+#endif /* BUTTON_H_ */
diff --git a/mcu/hal_api/ds.h b/mcu/hal_api/ds.h
index 310d276d..f0c94201 100644
--- a/mcu/hal_api/ds.h
+++ b/mcu/hal_api/ds.h
@@ -24,8 +24,7 @@ void DS_Disable(uint32_t source);
// Bitmasks for deep sleep disable bits
#define DS_SOURCE_USART 0x00000001
-#define DS_SOURCE_USART_POWER 0x00000002
-#define DS_SOURCE_DEBUG 0x00000004
-#define DS_SOURCE_INIT 0x00000008
+#define DS_SOURCE_DEBUG 0x00000002
+#define DS_SOURCE_INIT 0x00000004
#endif /* SOURCE_WAPS_APP_DRIVERS_DS_H_ */
diff --git a/mcu/hal_api/gpio/gpio.h b/mcu/hal_api/gpio/gpio.h
new file mode 100644
index 00000000..6d9f7aee
--- /dev/null
+++ b/mcu/hal_api/gpio/gpio.h
@@ -0,0 +1,237 @@
+/* Copyright 2022 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+
+/**
+ * \file gpio.h
+ * \brief Board-independent GPIO functions.
+ */
+
+#ifndef GPIO_H_
+#define GPIO_H_
+
+#include
+
+/** \brief GPIO identification number */
+typedef uint8_t gpio_id_t;
+
+/** \brief GPIO port number */
+typedef uint8_t gpio_port_t;
+
+/** \brief GPIO pin number */
+typedef uint8_t gpio_pin_t;
+
+/** \brief List of return code */
+typedef enum
+{
+ /** Operation is successful */
+ GPIO_RES_OK = 0,
+ /** GPIO iniatialization has not been performed */
+ GPIO_RES_UNINITIALIZED = 1,
+ /** GPIO HAL is not implemented. Weak definitions are used instead */
+ GPIO_RES_NOT_IMPLEMENTED = 2,
+ /** Invalid parameter(s) */
+ GPIO_RES_INVALID_PARAM = 3,
+ /** Invalid pin number */
+ GPIO_RES_INVALID_PIN = 4,
+ /** Invalid GPIO direction */
+ GPIO_RES_INVALID_DIRECTION = 5,
+ /** No free external interrupt: all of them are already in use. Note: Only used on SiLabs/EFR32 boards */
+ GPIO_RES_NO_FREE_IT = 6
+} gpio_res_e;
+
+/** \brief GPIO logical level */
+typedef enum
+{
+ /** The GPIO is low */
+ GPIO_LEVEL_LOW,
+ /** The GPIO is high */
+ GPIO_LEVEL_HIGH
+} gpio_level_e;
+
+/**
+ * \brief GPIO pull configuration
+ * \note Used for input GPIOs
+ */
+typedef enum
+{
+ /** input disabled */
+ GPIO_IN_DISABLED,
+ /** No pull (floating if no external pull-up or pull-down) */
+ GPIO_IN_PULL_NONE,
+ /** Pull-down */
+ GPIO_IN_PULL_DOWN,
+ /** Pull-up */
+ GPIO_IN_PULL_UP
+} gpio_in_mode_cfg_e;
+
+/**
+ * \brief GPIO operating mode configuration
+ * \note Used for output GPIOs
+ */
+typedef enum
+{
+ /** Push-pull */
+ GPIO_OUT_MODE_PUSH_PULL,
+ /** Open-drain */
+ GPIO_OUT_MODE_OPEN_DRAIN,
+ /** Open-drain with pull-up */
+ GPIO_OUT_MODE_OPEN_DRAIN_WITH_PULL_UP
+} gpio_out_mode_cfg_e;
+
+/**
+ * \brief GPIO event.
+ * \note Used for input GPIOs
+ */
+typedef enum
+{
+ /** No event */
+ GPIO_IN_EVENT_NONE = 0,
+ /** Rising edge event */
+ GPIO_IN_EVENT_RISING_EDGE = 1U << 0U,
+ /** Falling edge event */
+ GPIO_IN_EVENT_FALLING_EDGE = 1U << 1U,
+} gpio_in_event_e;
+
+/** \brief Check if event has its rising edge bit set */
+#define IS_RISING_EDGE(event) ((event & GPIO_IN_EVENT_RISING_EDGE) == GPIO_IN_EVENT_RISING_EDGE)
+/** \brief Check if event has its falling edge bit set */
+#define IS_FALLING_EDGE(event) ((event & GPIO_IN_EVENT_FALLING_EDGE) == GPIO_IN_EVENT_FALLING_EDGE)
+
+/**
+ * \brief Callback structure for a GPIO event
+ * \param id
+ * Id of the GPIO which raised the event
+ * \param event
+ * Event raised
+ */
+typedef void (*gpio_in_event_cb_f)(gpio_id_t id, gpio_in_event_e event);
+
+/** \brief GPIO input configuration */
+typedef struct
+{
+ /** Callback called on GPIO events */
+ gpio_in_event_cb_f event_cb;
+ /**
+ * Event configuration.
+ * Use | (OR) operator to detect both rising and falling edges.
+ * e.g.: .event_cfg = (GPIO_IN_EVENT_RISING_EDGE | GPIO_IN_EVENT_FALLING_EDGE)
+ */
+ gpio_in_event_e event_cfg : 2;
+ /** Pull configuration (e.g.: Pull-down) */
+ gpio_in_mode_cfg_e in_mode_cfg : 2;
+} gpio_in_cfg_t;
+
+/** \brief GPIO output configuration */
+typedef struct
+{
+ /** Operating mode configuration (e.g.: Push-pull) */
+ gpio_out_mode_cfg_e out_mode_cfg : 2;
+ /** GPIO default logical level (e.g.: Low) */
+ gpio_level_e level_default : 1;
+} gpio_out_cfg_t;
+
+/**
+ * \brief Initialize GPIO module
+ *
+ * Example on use:
+ * @code
+ * void App_init(const app_global_functions_t * functions)
+ * {
+ * ...
+ * // Set up GPIOs first
+ * Gpio_init();
+ * ...
+ * Gpio_inputSetCfg(GPIO_INPUT_ID, &in_cfg);
+ * ...
+ * Gpio_outputSetCfg(GPIO_OUTPUT_ID, &out_cfg);
+ * ...
+ * }
+ * @endcode
+ */
+gpio_res_e Gpio_init(void);
+
+/**
+ * \brief Configure a GPIO as an input GPIO
+ * \param id
+ * Id of the GPIO
+ * \param[in] in_cfg
+ * GPIO input configuration
+ * \return Return code of operation
+ */
+gpio_res_e Gpio_inputSetCfg(gpio_id_t id, const gpio_in_cfg_t *in_cfg);
+
+/**
+ * \brief Read the GPIO input level
+ * \note The GPIO should be configured as an input GPIO
+ * \param id
+ * Id of the GPIO
+ * \param[out] level
+ * Returned GPIO level (low or high)
+ * \return Return code of operation
+ */
+gpio_res_e Gpio_inputRead(gpio_id_t id, gpio_level_e *level);
+
+/**
+ * \brief Configure a GPIO as an output GPIO
+ * \param id
+ * Id of the GPIO
+ * \param[in] out_cfg
+ * GPIO output configuration
+ * \return Return code of operation
+ */
+gpio_res_e Gpio_outputSetCfg(gpio_id_t id, const gpio_out_cfg_t *out_cfg);
+
+/**
+ * \brief Write GPIO output level
+ * \note The GPIO should be configured as an output GPIO
+ * \param id
+ * Id of the GPIO
+ * \param level
+ * GPIO level (low or high) to write
+ * \return Return code of operation
+ */
+gpio_res_e Gpio_outputWrite(gpio_id_t id, gpio_level_e level);
+
+/**
+ * \brief Toggle GPIO output level
+ * \note The GPIO should be configured as an output GPIO
+ * \param id
+ * Id of the GPIO
+ * \return Return code of operation
+ */
+gpio_res_e Gpio_outputToggle(gpio_id_t id);
+
+/**
+ * \brief Read the GPIO output level
+ * \note The GPIO should be configured as an output GPIO
+ * \param id
+ * Id of the GPIO
+ * \param[out] level
+ * Returned GPIO level (low or high)
+ * \return Return code of operation
+ */
+gpio_res_e Gpio_outputRead(gpio_id_t id, gpio_level_e *level);
+
+/**
+ * \brief Get the GPIO port and pin numbers of the given GPIO id
+ * \param id
+ * Id of the GPIO
+ * \param[out] port
+ * Returned GPIO port number
+ * \param[out] pin
+ * Returned GPIO pin number
+ *
+ * \return Return code of operation
+ */
+gpio_res_e Gpio_getPin(gpio_id_t id, gpio_port_t *port, gpio_pin_t *pin);
+
+/**
+ * \brief Get the number of GPIOs
+ * \return Number of GPIOs
+ */
+uint8_t Gpio_getNumber(void);
+
+#endif /* GPIO_H_ */
diff --git a/mcu/hal_api/hal_init.c b/mcu/hal_api/hal_init.c
new file mode 100644
index 00000000..5714987a
--- /dev/null
+++ b/mcu/hal_api/hal_init.c
@@ -0,0 +1,37 @@
+/* Copyright 2021 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+#include "hal_init.h"
+
+// HAL drivers are considered in use if their associated interface (.h)
+// file is in the include list. It could be done with a dedicated C flag
+// but it would have the same effect
+
+#if __has_include("gpio.h")
+#include "gpio.h"
+#endif
+
+#if __has_include("button.h")
+#include "button.h"
+#endif
+
+#if __has_include("led.h")
+#include "led.h"
+#endif
+
+void Hal_init(void)
+{
+#if __has_include("gpio.h")
+ Gpio_init();
+#endif
+
+#if __has_include("button.h")
+ Button_init();
+#endif
+
+#if __has_include("led.h")
+ Led_init();
+#endif
+}
diff --git a/mcu/hal_api/hal_init.h b/mcu/hal_api/hal_init.h
new file mode 100644
index 00000000..25b38798
--- /dev/null
+++ b/mcu/hal_api/hal_init.h
@@ -0,0 +1,15 @@
+/* Copyright 2022 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+
+#ifndef HAL_INIT_H_
+#define HAL_INIT_H_
+
+/**
+ * \brief HAL drivers initialization
+ */
+void Hal_init(void);
+
+#endif /* HAL_INIT_H_ */
diff --git a/mcu/hal_api/led.h b/mcu/hal_api/led/led.h
similarity index 92%
rename from mcu/hal_api/led.h
rename to mcu/hal_api/led/led.h
index cdfce138..b5714039 100644
--- a/mcu/hal_api/led.h
+++ b/mcu/hal_api/led/led.h
@@ -8,6 +8,10 @@
* \file led.h
* \brief Board-independent LED functions
*/
+
+#ifndef LED_H_
+#define LED_H_
+
#include
#include
@@ -20,6 +24,8 @@ typedef enum
LED_RES_OK = 0,
/** Led id is invalid */
LED_RES_INVALID_ID = 1,
+ /** LED iniatialization has not been performed */
+ LED_RES_UNINITIALIZED = 2
} led_res_e;
/**
@@ -87,3 +93,5 @@ led_res_e Led_toggle(uint8_t led_id);
* \return The number of leds available
*/
uint8_t Led_getNumber(void);
+
+#endif /* LED_H_ */
diff --git a/mcu/hal_api/makefile b/mcu/hal_api/makefile
index 2ef6c81d..c3639dcb 100644
--- a/mcu/hal_api/makefile
+++ b/mcu/hal_api/makefile
@@ -1,6 +1,18 @@
-CFLAGS += -I$(HAL_API_PATH)
+INCLUDES += -I$(HAL_API_PATH)
+
+SRCS += $(HAL_API_PATH)hal_init.c
# include drivers
-#MCU_PREFIX := $(MCU_PATH)$(MCU_FAMILY)/$(MCU)/
-#include $(MCU_PREFIX)hal/makefile
-include $(MCU_PATH)$(MCU_FAMILY)/makefile
\ No newline at end of file
+include $(MCU_PATH)$(MCU_FAMILY)/makefile
+
+ifeq ($(HAL_BUTTON), yes)
+INCLUDES += -I$(HAL_API_PATH)button
+endif
+
+ifeq ($(HAL_LED), yes)
+INCLUDES += -I$(HAL_API_PATH)led
+endif
+
+ifeq ($(HAL_GPIO), yes)
+INCLUDES += -I$(HAL_API_PATH)gpio
+endif
diff --git a/mcu/hal_api/spi.h b/mcu/hal_api/spi.h
index ef505bb2..6e7c1b8f 100644
--- a/mcu/hal_api/spi.h
+++ b/mcu/hal_api/spi.h
@@ -42,9 +42,9 @@ typedef struct
typedef struct
{
uint8_t * write_ptr; //< Pointer to bytes to write (Must be NULL for pure read)
- uint8_t write_size; //< Number of bytes to write (Must be 0 for pure read)
+ size_t write_size; //< Number of bytes to write (Must be 0 for pure read)
uint8_t * read_ptr; //< Pointer to store bytes to read (Must be NULL for pure write)
- uint8_t read_size; //< Number of bytes to read (Must be 0 for pure write)
+ size_t read_size; //< Number of bytes to read (Must be 0 for pure write)
uint32_t custom; //< Custom param (can be used to implement state machine)
} spi_xfer_t;
diff --git a/mcu/nrf/common/hal/button.c b/mcu/nrf/common/hal/button.c
deleted file mode 100644
index ef2ec5d9..00000000
--- a/mcu/nrf/common/hal/button.c
+++ /dev/null
@@ -1,380 +0,0 @@
-/* Copyright 2018 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-/*
- * \file button.c
- * \brief Board-specific button module for nrf52
- */
-
-#include "button.h"
-#include "mcu.h"
-#include "board.h"
-#include "api.h"
-
-
-#ifdef BOARD_BUTTON_PIN_LIST
-
-/*
- * The selected board has buttons
- */
-
-#ifndef BOARD_DEBOUNCE_TIME_MS
-/** \brief Debounce time of button in ms. It can be overwritten from board.h */
-#define BOARD_DEBOUNCE_TIME_MS 100
-#endif
-
-#ifndef BOARD_BUTTON_ACTIVE_LOW
-/** \brief Is button active low. It can be overwritten from board.h */
-#define BOARD_BUTTON_ACTIVE_LOW true
-#endif
-
-#ifndef BOARD_BUTTON_INTERNAL_PULL
-/** \brief Does the driver needs to activate internal pull-up/down.
- * If true; pull-up (down) is enabled if BOARD_BUTTON_ACTIVE_LOW is
- * true (false). It can be overwritten from board.h
- */
-#define BOARD_BUTTON_INTERNAL_PULL true
-#endif
-
-/** \brief Each button use a GPIOTE channel Define first one */
-#define GPIOTE_START_CHANNEL 0
-
-/** \brief Board-dependent Button number to pin mapping */
-static const uint8_t pin_map[] = BOARD_BUTTON_PIN_LIST;
-
-/** \brief Compute number of button on the board */
-#define BOARD_BUTTON_NUMBER (sizeof(pin_map) / sizeof(pin_map[0]))
-
-static void gpiote_interrupt_handler(void);
-
-typedef enum
-{
- NO_INTERRUPT,
- ON_PRESSED_ONLY,
- ON_RELEASED_ONLY,
- ON_PRESSED_AND_RELEASED
-} button_interrupt_type_e;
-
-typedef struct
-{
- // Callback when button pressed
- on_button_event_cb on_pressed;
- // Callback when button released
- on_button_event_cb on_released;
- // Used for debounce
- app_lib_time_timestamp_hp_t last_button_event;
- uint8_t gpio;
- uint8_t channel;
- bool active_low;
-} button_internal_t;
-
-/** \brief Table to manage the button list */
-static button_internal_t m_button_conf[BOARD_BUTTON_NUMBER];
-
-/* Button events and sense truth table
- *
- * Type : interrupt type see button_interrupt_type_e
- * N:No_it, P:pressed_only, R:released_only, PR:pressed&released
- * act_low: Button is active low
- * Pin: IO state (Low or High)
- * Sense: Value to configure in sense register
- *
- * Type | act_low | Pin | Sense
- * N | X | X | Disabled
- *
- * P | Y | X | Low
- * P | N | X | High
- *
- * R | Y | X | High
- * R | N | X | Low
- *
- * PR | X | H | Low
- * PR | X | L | Low
- *
- */
-static void button_enable_interrupt(uint8_t button_id,
- button_interrupt_type_e type)
-{
- bool is_sense_low = false;
-
- switch(type)
- {
- case NO_INTERRUPT:
- {
- //Disable SENSE
- NRF_GPIO->PIN_CNF[m_button_conf[button_id].gpio] = 0;
- NRF_GPIO->LATCH = 1 << m_button_conf[button_id].gpio;
-
- // Check if port IRQ must be masked
- for (uint8_t i = 0; i < BOARD_BUTTON_NUMBER; i++)
- {
- if (m_button_conf[i].on_pressed ||
- m_button_conf[i].on_released)
- {
- // At least one line still enabled
- return;
- }
- }
- NRF_GPIOTE->INTENCLR = GPIOTE_INTENCLR_PORT_Msk;
- return;
- }
- case ON_PRESSED_ONLY:
- {
- is_sense_low = m_button_conf[button_id].active_low;
- break;
- }
- case ON_RELEASED_ONLY:
- {
- is_sense_low = !m_button_conf[button_id].active_low;
- break;
- }
- case ON_PRESSED_AND_RELEASED:
- {
- is_sense_low =
- nrf_gpio_pin_read(m_button_conf[button_id].gpio) == 0 ?
- false : true;
- break;
- }
- }
-
- // Configure interrupt (type != NO_INTERRUPT)
-
- //Disable IRQ
- NRF_GPIO->PIN_CNF[m_button_conf[button_id].gpio] &=
- ~(GPIO_PIN_CNF_SENSE_Msk);
-
- if(is_sense_low)
- {
- NRF_GPIO->PIN_CNF[m_button_conf[button_id].gpio] |=
- (GPIO_PIN_CNF_SENSE_Low << GPIO_PIN_CNF_SENSE_Pos);
- }
- else
- {
- NRF_GPIO->PIN_CNF[m_button_conf[button_id].gpio] |=
- (GPIO_PIN_CNF_SENSE_High << GPIO_PIN_CNF_SENSE_Pos);
- }
- // Clear the line before enabling IRQ
- NRF_GPIO->LATCH = 1 << m_button_conf[button_id].gpio;
- NRF_GPIOTE->INTENSET = GPIOTE_INTENSET_PORT_Msk;
-}
-
-void Button_init(void)
-{
- app_lib_time_timestamp_hp_t now = lib_time->getTimestampHp();
-
- for (uint8_t i = 0; i < BOARD_BUTTON_NUMBER; i ++)
- {
- m_button_conf[i].gpio = pin_map[i];
- m_button_conf[i].channel = GPIOTE_START_CHANNEL + i;
- m_button_conf[i].on_pressed = NULL;
- m_button_conf[i].on_released = NULL;
- m_button_conf[i].last_button_event = now;
- m_button_conf[i].active_low = BOARD_BUTTON_ACTIVE_LOW;
-
- // Enable the Pull-Up/Down on Buttons (Input; Pull; SENSE:Disabled)
- if (BOARD_BUTTON_INTERNAL_PULL)
- {
- uint32_t pull;
-
- if (BOARD_BUTTON_ACTIVE_LOW)
- {
- pull = (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos);
- }
- else
- {
- pull = (GPIO_PIN_CNF_PULL_Pulldown << GPIO_PIN_CNF_PULL_Pos);
- }
- NRF_GPIO->PIN_CNF[m_button_conf[i].gpio] = pull;
- }
- else
- {
- // Default config (Input; No Pull; SENSE:Disabled).
- NRF_GPIO->PIN_CNF[m_button_conf[i].gpio] = 0;
- }
- }
-
- NRF_GPIOTE->INTENCLR = GPIOTE_INTENCLR_PORT_Msk;
- NRF_GPIOTE->EVENTS_PORT = 0;
-
- // Enable interrupt
- lib_system->clearPendingFastAppIrq(GPIOTE_IRQn);
- lib_system->enableAppIrq(true,
- GPIOTE_IRQn,
- APP_LIB_SYSTEM_IRQ_PRIO_LO,
- gpiote_interrupt_handler);
-}
-
-button_res_e Button_getState(uint8_t button_id, bool * state_p)
-{
- if (button_id >= BOARD_BUTTON_NUMBER)
- {
- // Invalid button number, just answer not pressed
- return BUTTON_RES_INVALID_ID;
- }
-
- *state_p = ((nrf_gpio_pin_read(m_button_conf[button_id].gpio) != 0)
- != m_button_conf[button_id].active_low);
-
- return BUTTON_RES_OK;
-}
-
-button_res_e Button_register_for_event(uint8_t button_id,
- button_event_e event,
- on_button_event_cb cb)
-{
- button_interrupt_type_e type;
-
- if ((button_id >= BOARD_BUTTON_NUMBER)
- || (event != BUTTON_PRESSED && event != BUTTON_RELEASED ))
- {
- // Invalid button number
- return BUTTON_RES_INVALID_ID;
- }
-
- Sys_enterCriticalSection();
-
- if (event == BUTTON_PRESSED)
- {
- m_button_conf[button_id].on_pressed = cb;
- }
- else
- {
- m_button_conf[button_id].on_released = cb;
- }
-
- if (m_button_conf[button_id].on_pressed &&
- m_button_conf[button_id].on_released)
- {
- type = ON_PRESSED_AND_RELEASED;
- }
- else if (m_button_conf[button_id].on_pressed)
- {
- type = ON_PRESSED_ONLY;
- }
- else if (m_button_conf[button_id].on_released)
- {
- type = ON_RELEASED_ONLY;
- }
- else
- {
- type = NO_INTERRUPT;
- }
-
- button_enable_interrupt(button_id, type);
-
- Sys_exitCriticalSection();
-
- return BUTTON_RES_OK;
-}
-
-uint8_t Button_get_number(void)
-{
- return BOARD_BUTTON_NUMBER;
-}
-
-static void gpiote_interrupt_handler(void)
-{
- app_lib_time_timestamp_hp_t now = lib_time->getTimestampHp();
-
- if (NRF_GPIOTE->EVENTS_PORT == 0)
- {
- return;
- }
-
- NRF_GPIOTE->EVENTS_PORT = 0;
- // read any event from peripheral to flush the write buffer:
- EVENT_READBACK = NRF_GPIOTE->EVENTS_PORT;
-
- // Check all possible sources
- for (uint8_t i = 0; i < BOARD_BUTTON_NUMBER; i ++)
- {
- uint8_t pin = m_button_conf[i].gpio;
- if (NRF_GPIO->LATCH & (1 << pin))
- {
- if (lib_time->getTimeDiffUs(now,
- m_button_conf[i].last_button_event)
- > (BOARD_DEBOUNCE_TIME_MS * 1000))
- {
- bool pressed;
- Button_getState(i, &pressed);
- m_button_conf[i].last_button_event = now;
-
- if (m_button_conf[i].on_pressed && pressed)
- {
- // Call callback
- m_button_conf[i].on_pressed(i, BUTTON_PRESSED);
- }
- else if (m_button_conf[i].on_released && !pressed)
- {
- //Call callback
- m_button_conf[i].on_released(i, BUTTON_RELEASED);
- }
-
- // Change SENSE polarity
- if (m_button_conf[i].on_pressed &&
- m_button_conf[i].on_released)
- {
- NRF_GPIO->PIN_CNF[pin] &= ~(GPIO_PIN_CNF_SENSE_Msk);
- if (nrf_gpio_pin_read(pin) == 0)
- {
- NRF_GPIO->PIN_CNF[pin] |=
- (GPIO_PIN_CNF_SENSE_High << GPIO_PIN_CNF_SENSE_Pos);
- }
- else
- {
- NRF_GPIO->PIN_CNF[pin] |=
- (GPIO_PIN_CNF_SENSE_Low << GPIO_PIN_CNF_SENSE_Pos);
- }
- }
- }
- // Clear the line
- NRF_GPIO->LATCH = 1 << pin;
- }
- }
-}
-
-#else // BOARD_BUTTON_PIN_LIST
-
-/*
- * The selected board has no buttons
- *
- * As some example apps support such boards but also provide extra features
- * when a board has buttons, the button driver has this dummy implementation
- * to simplify the build process.
- */
-
-void Button_init(void)
-{
- // Do nothing
-}
-
-button_res_e Button_getState(uint8_t button_id, bool * state_p)
-{
- (void) button_id;
- *state_p = false;
-
- // Invalid button number
- return BUTTON_RES_INVALID_ID;
-}
-
-uint8_t Button_get_number(void)
-{
- return 0;
-}
-
-button_res_e Button_register_for_event(uint8_t button_id,
- button_event_e event,
- on_button_event_cb cb)
-{
- (void) button_id;
- (void) event;
- (void) cb;
-
- // Invalid button number
- return BUTTON_RES_INVALID_ID;
-}
-
-#endif // BOARD_BUTTON_PIN_LIST
diff --git a/mcu/nrf/common/hal/ds.c b/mcu/nrf/common/hal/ds.c
deleted file mode 100644
index 4c69e44e..00000000
--- a/mcu/nrf/common/hal/ds.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/* Copyright 2017 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-
-#include
-#include "ds.h"
-#include "api.h"
-
-// Bitmask holding different sleep control bits
-static volatile uint32_t m_sleep_mask = 0;
-
-void DS_Init(void)
-{
- m_sleep_mask = 0;
-}
-
-void DS_Enable(uint32_t source)
-{
- // Atomic operation
- Sys_enterCriticalSection();
- // Clear bit
- m_sleep_mask &= ~source;
- // If mask is clear, enable deep sleep
- if(m_sleep_mask == 0)
- {
- // Enable deep sleep
- Sys_disableDs(false);
- }
- Sys_exitCriticalSection();
-}
-
-void DS_Disable(uint32_t source)
-{
- // Atomic operation
- Sys_enterCriticalSection();
- // Some sources are declared NIL on this platform
- if(source == DS_SOURCE_USART_POWER)
- {
- // Usart power-up procedure does not need ds disable as the system
- // is very fast to wake up from deep sleep
- goto exit_no_change;
- }
- // Set bit
- m_sleep_mask |= source;
- // Disable deep sleep
- Sys_disableDs(true);
-exit_no_change:
- Sys_exitCriticalSection();
-}
diff --git a/mcu/nrf/common/hal/gpio.c b/mcu/nrf/common/hal/gpio.c
new file mode 100644
index 00000000..51d60ab0
--- /dev/null
+++ b/mcu/nrf/common/hal/gpio.c
@@ -0,0 +1,522 @@
+/* Copyright 2022 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+
+/**
+ * \file gpio.c
+ * \brief Board-specific GPIO functions for nrf52.
+ * \attention Should be compatible with the gpio.h interface.
+ */
+
+#include "gpio.h"
+#include "mcu.h"
+#include "board.h"
+#include "api.h"
+
+/*
+ * If some GPIOs are mapped
+ *
+ * Note:
+ * If BOARD_GPIO_PIN_LIST is not defined,
+ * then the dummy functions defined in the gpio_weak.c file will be used instead
+ */
+#ifdef BOARD_GPIO_PIN_LIST
+
+/** \brief GPIO direction */
+typedef enum
+{
+ /** input direction */
+ DIR_INPUT,
+ /** output direction */
+ DIR_OUTPUT
+} direction_e;
+
+/** \brief GPIO internal configuration */
+typedef struct
+{
+ /** GPIO direction (either input or output) */
+ direction_e direction : 1;
+ /** Callback called on GPIO events */
+ gpio_in_event_e event_cfg : 2;
+} gpio_cfg_intern_t;
+
+/** \brief GPIO id to GPIO pin map (array index: GPIO id ; array value: GPIO pin) */
+static const gpio_pin_t m_id_to_pin_map[] = BOARD_GPIO_PIN_LIST;
+
+/** \brief Compute number of GPIOs that are mapped (= total number of used GPIOs) */
+#define BOARD_GPIO_NUMBER (sizeof(m_id_to_pin_map) / sizeof(m_id_to_pin_map[0]))
+
+/** \brief GPIO id to GPIO internal config map (array index: GPIO id ; array value: GPIO internal config) */
+static gpio_cfg_intern_t m_id_to_cfg_map[BOARD_GPIO_NUMBER];
+
+/** \brief GPIO id to GPIO event callback map (array index: GPIO id ; array value: GPIO event callback) */
+static gpio_in_event_cb_f m_id_to_event_cb_map[BOARD_GPIO_NUMBER];
+
+/** \brief Has the library been initialized */
+static bool m_initialized = false;
+
+/**
+ * \brief Check if the pin numbers of the mapped GPIOs are valid (if they exist on the MCU)
+ * \return True if all the pin numbers are valid ; False otherwise
+ */
+static bool check_pins(void);
+
+/**
+ * \brief Configure mode (e.g.: pull-down) of input GPIO
+ * \param id
+ * Id of the GPIO
+ * \param[in] in_cfg
+ * GPIO input configuration
+ */
+static void input_set_cfg_mode(gpio_id_t id, const gpio_in_cfg_t *in_cfg);
+
+/**
+ * \brief Configure interrupt of input GPIO
+ * \param id
+ * Id of the GPIO
+ * \param[in] in_cfg
+ * GPIO input configuration
+ */
+static void input_set_cfg_irq(gpio_id_t id, const gpio_in_cfg_t *in_cfg);
+
+/** \brief Initialize GPIOs interrupts */
+static void input_init_irq(void);
+
+/**
+ * \brief Check if any of the GPIO "SENSE" is enabled
+ * \return True if any of the GPIO "SENSE" is enabled ; False otherwise
+ */
+static bool any_sense_enabled(void);
+
+/** \brief function called when a GPIO interrupt is raised. Used to generate the appropriate GPIO event */
+static void gpio_event_handle(void);
+
+gpio_res_e Gpio_init(void)
+{
+ gpio_id_t id;
+ const gpio_in_cfg_t in_cfg =
+ {
+ .event_cb = NULL,
+ .event_cfg = GPIO_IN_EVENT_NONE,
+ .in_mode_cfg = GPIO_IN_DISABLED
+ };
+
+ if (m_initialized)
+ {
+ /* return if GPIO initialization has already been performed */
+ return GPIO_RES_OK;
+ }
+ if (!check_pins())
+ {
+ return GPIO_RES_INVALID_PIN;
+ }
+
+ Sys_enterCriticalSection();
+
+ /* Configure each mapped GPIOs to a default configuration */
+ for (id = 0; id < BOARD_GPIO_NUMBER; id++)
+ {
+ input_set_cfg_mode(id, &in_cfg);
+ input_set_cfg_irq(id, &in_cfg);
+ /* Store direction and part of configuration that is used internally */
+ m_id_to_event_cb_map[id] = in_cfg.event_cb;
+ m_id_to_cfg_map[id].direction = DIR_INPUT;
+ m_id_to_cfg_map[id].event_cfg = in_cfg.event_cfg;
+ }
+ input_init_irq();
+
+ Sys_exitCriticalSection();
+
+ m_initialized = true;
+
+ return GPIO_RES_OK;
+}
+
+gpio_res_e Gpio_inputSetCfg(gpio_id_t id, const gpio_in_cfg_t *in_cfg)
+{
+ if (!m_initialized)
+ {
+ return GPIO_RES_UNINITIALIZED;
+ }
+ if (id >= BOARD_GPIO_NUMBER || in_cfg == NULL)
+ {
+ return GPIO_RES_INVALID_PARAM;
+ }
+
+ Sys_enterCriticalSection();
+
+ input_set_cfg_mode(id, in_cfg);
+ input_set_cfg_irq(id, in_cfg);
+ /* Store direction and part of configuration that is used internally */
+ m_id_to_event_cb_map[id] = in_cfg->event_cb;
+ m_id_to_cfg_map[id].direction = DIR_INPUT;
+ m_id_to_cfg_map[id].event_cfg = in_cfg->event_cfg;
+
+ Sys_exitCriticalSection();
+
+ return GPIO_RES_OK;
+}
+
+gpio_res_e Gpio_inputRead(gpio_id_t id, gpio_level_e *level)
+{
+ gpio_pin_t pin;
+ bool read_val;
+
+ if (!m_initialized)
+ {
+ return GPIO_RES_UNINITIALIZED;
+ }
+ if (id >= BOARD_GPIO_NUMBER || level == NULL)
+ {
+ return GPIO_RES_INVALID_PARAM;
+ }
+ if (m_id_to_cfg_map[id].direction != DIR_INPUT)
+ {
+ return GPIO_RES_INVALID_DIRECTION;
+ }
+
+ Gpio_getPin(id, NULL, &pin);
+ read_val = (nrf_gpio_pin_read(pin) != 0);
+ *level = read_val ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW;
+
+ return GPIO_RES_OK;
+}
+
+gpio_res_e Gpio_outputSetCfg(gpio_id_t id, const gpio_out_cfg_t *out_cfg)
+{
+ nrf_gpio_pin_pull_t pull;
+ nrf_gpio_pin_drive_t drive;
+ gpio_pin_t pin;
+
+ if (!m_initialized)
+ {
+ return GPIO_RES_UNINITIALIZED;
+ }
+ if (id >= BOARD_GPIO_NUMBER || out_cfg == NULL)
+ {
+ return GPIO_RES_INVALID_PARAM;
+ }
+
+ /*
+ * convert board independant operating mode enum,
+ * to board specific operating mode enum
+ */
+ switch (out_cfg->out_mode_cfg)
+ {
+ case GPIO_OUT_MODE_PUSH_PULL:
+ drive = NRF_GPIO_PIN_S0S1;
+ pull = NRF_GPIO_PIN_NOPULL;
+ break;
+ case GPIO_OUT_MODE_OPEN_DRAIN:
+ drive = NRF_GPIO_PIN_S0D1;
+ pull = NRF_GPIO_PIN_NOPULL;
+ break;
+ case GPIO_OUT_MODE_OPEN_DRAIN_WITH_PULL_UP:
+ drive = NRF_GPIO_PIN_S0D1;
+ pull = NRF_GPIO_PIN_PULLUP;
+ break;
+ default:
+ return GPIO_RES_INVALID_PARAM;
+ }
+
+ Sys_enterCriticalSection();
+
+ Gpio_getPin(id, NULL, &pin);
+ nrf_gpio_cfg(pin,
+ NRF_GPIO_PIN_DIR_OUTPUT,
+ NRF_GPIO_PIN_INPUT_DISCONNECT,
+ pull,
+ drive,
+ NRF_GPIO_PIN_NOSENSE);
+ /* Set pin default state */
+ nrf_gpio_pin_write(pin, (out_cfg->level_default != GPIO_LEVEL_LOW));
+ /* Store direction */
+ m_id_to_cfg_map[id].direction = DIR_OUTPUT;
+
+ Sys_exitCriticalSection();
+
+ return GPIO_RES_OK;
+}
+
+gpio_res_e Gpio_outputWrite(gpio_id_t id, gpio_level_e level)
+{
+ gpio_pin_t pin;
+ bool write_val;
+
+ if (!m_initialized)
+ {
+ return GPIO_RES_UNINITIALIZED;
+ }
+ if (id >= BOARD_GPIO_NUMBER)
+ {
+ return GPIO_RES_INVALID_PARAM;
+ }
+ if (m_id_to_cfg_map[id].direction != DIR_OUTPUT)
+ {
+ return GPIO_RES_INVALID_DIRECTION;
+ }
+
+ Gpio_getPin(id, NULL, &pin);
+ write_val = (level != GPIO_LEVEL_LOW);
+ nrf_gpio_pin_write(pin, write_val);
+
+ return GPIO_RES_OK;
+}
+
+gpio_res_e Gpio_outputToggle(gpio_id_t id)
+{
+ gpio_pin_t pin;
+
+ if (!m_initialized)
+ {
+ return GPIO_RES_UNINITIALIZED;
+ }
+ if (id >= BOARD_GPIO_NUMBER)
+ {
+ return GPIO_RES_INVALID_PARAM;
+ }
+ if (m_id_to_cfg_map[id].direction != DIR_OUTPUT)
+ {
+ return GPIO_RES_INVALID_DIRECTION;
+ }
+
+ Gpio_getPin(id, NULL, &pin);
+ nrf_gpio_pin_toggle(pin);
+
+ return GPIO_RES_OK;
+}
+
+gpio_res_e Gpio_outputRead(gpio_id_t id, gpio_level_e *level)
+{
+ gpio_pin_t pin;
+ bool read_val;
+
+ if (!m_initialized)
+ {
+ return GPIO_RES_UNINITIALIZED;
+ }
+ if (id >= BOARD_GPIO_NUMBER || level == NULL)
+ {
+ return GPIO_RES_INVALID_PARAM;
+ }
+ if (m_id_to_cfg_map[id].direction != DIR_OUTPUT)
+ {
+ return GPIO_RES_INVALID_DIRECTION;
+ }
+
+ Gpio_getPin(id, NULL, &pin);
+ read_val = nrf_gpio_pin_out_read(pin) != 0;
+ *level = read_val ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW;
+
+ return GPIO_RES_OK;
+}
+
+gpio_res_e Gpio_getPin(gpio_id_t id, gpio_port_t *port, gpio_pin_t *pin)
+{
+ if (id >= BOARD_GPIO_NUMBER)
+ {
+ return GPIO_RES_INVALID_PARAM;
+ }
+
+ if (port)
+ {
+ /*
+ * With NRF chips, all the information is stored in pin.
+ * Thus port is always set to 0 and it can be ignored.
+ */
+ *port = 0;
+ }
+ if (pin)
+ {
+ *pin = m_id_to_pin_map[id];
+ }
+
+ return GPIO_RES_OK;
+}
+
+uint8_t Gpio_getNumber(void)
+{
+ return BOARD_GPIO_NUMBER;
+}
+
+static bool check_pins(void)
+{
+ gpio_id_t id;
+ gpio_pin_t pin;
+
+ for (id = 0; id < BOARD_GPIO_NUMBER; id++)
+ {
+ Gpio_getPin(id, NULL, &pin);
+ if (!nrf_gpio_pin_present_check(pin))
+ {
+ return false;
+ }
+ }
+ return true;
+}
+
+static void input_set_cfg_mode(gpio_id_t id, const gpio_in_cfg_t *in_cfg)
+{
+ gpio_pin_t pin;
+ nrf_gpio_pin_pull_t nrf_pin_pull;
+ nrf_gpio_pin_input_t nrf_connect;
+
+ /*
+ * convert board independant mode enum,
+ * to board specific pull enum
+ */
+ switch (in_cfg->in_mode_cfg)
+ {
+ case GPIO_IN_DISABLED:
+ nrf_pin_pull = NRF_GPIO_PIN_NOPULL;
+ nrf_connect = NRF_GPIO_PIN_INPUT_DISCONNECT;
+ break;
+ case GPIO_IN_PULL_NONE:
+ nrf_pin_pull = NRF_GPIO_PIN_NOPULL;
+ nrf_connect = NRF_GPIO_PIN_INPUT_CONNECT;
+ break;
+ case GPIO_IN_PULL_DOWN:
+ nrf_pin_pull = NRF_GPIO_PIN_PULLDOWN;
+ nrf_connect = NRF_GPIO_PIN_INPUT_CONNECT;
+ break;
+ case GPIO_IN_PULL_UP:
+ nrf_pin_pull = NRF_GPIO_PIN_PULLUP;
+ nrf_connect = NRF_GPIO_PIN_INPUT_CONNECT;
+ break;
+ }
+ Gpio_getPin(id, NULL, &pin);
+
+ nrf_gpio_cfg(pin,
+ NRF_GPIO_PIN_DIR_INPUT,
+ nrf_connect,
+ nrf_pin_pull,
+ NRF_GPIO_PIN_S0S1,
+ NRF_GPIO_PIN_NOSENSE);
+}
+
+static void input_set_cfg_irq(gpio_id_t id, const gpio_in_cfg_t *in_cfg)
+{
+ gpio_pin_t pin;
+ nrf_gpio_pin_sense_t sense;
+
+ Gpio_getPin(id, NULL, &pin);
+
+ /* if no event on this GPIO, ... */
+ if (in_cfg->event_cfg == GPIO_IN_EVENT_NONE)
+ {
+ /* ...then disable its sense feature */
+ nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE);
+ nrf_gpio_pin_latch_clear(pin);
+
+ /* if not a single GPIO uses its sense feature, ... */
+ if(!any_sense_enabled())
+ {
+ /* ...then disable the port interrupt (since it is no longer used by any GPIO) */
+ nrf_gpiote_int_disable(NRF_GPIOTE, GPIOTE_INTENCLR_PORT_Msk);
+ }
+ }
+ /* if event on this GPIO (rising edge, falling edge, or both),... */
+ else
+ {
+ /* ...then read the current pin state and set for next sense to oposit */
+ sense = (nrf_gpio_pin_read(pin)) ? NRF_GPIO_PIN_SENSE_LOW : NRF_GPIO_PIN_SENSE_HIGH;
+ nrf_gpio_cfg_sense_set(pin, sense);
+ nrf_gpio_pin_latch_clear(pin);
+ nrf_gpiote_int_enable(NRF_GPIOTE, GPIOTE_INTENCLR_PORT_Msk);
+ }
+}
+
+static void input_init_irq(void)
+{
+ nrf_gpiote_event_clear(NRF_GPIOTE, NRF_GPIOTE_EVENT_PORT);
+ nrf_gpiote_int_disable(NRF_GPIOTE, GPIOTE_INTENCLR_PORT_Msk);
+ lib_system->enableAppIrq(true,
+ GPIOTE_IRQn,
+ APP_LIB_SYSTEM_IRQ_PRIO_LO,
+ gpio_event_handle);
+ lib_system->clearPendingFastAppIrq(GPIOTE_IRQn);
+}
+
+static bool any_sense_enabled(void)
+{
+ gpio_id_t id;
+ gpio_pin_t pin;
+ nrf_gpio_pin_sense_t sense;
+
+ for (id = 0; id < BOARD_GPIO_NUMBER; id++)
+ {
+ Gpio_getPin(id, NULL, &pin);
+ sense = nrf_gpio_pin_sense_get(pin);
+ if (sense != NRF_GPIO_PIN_NOSENSE)
+ {
+ return true;
+ }
+ }
+ return false;
+}
+
+static void gpio_event_handle(void)
+{
+ gpio_id_t id;
+ gpio_pin_t pin;
+ gpio_in_event_cb_f event_cb;
+ gpio_in_event_e event_cfg;
+ nrf_gpio_pin_sense_t sense;
+ gpio_in_event_e event;
+
+ /* leave if the port interrupt flag is not set (should not happen) */
+ if (!nrf_gpiote_event_check(NRF_GPIOTE, NRF_GPIOTE_EVENT_PORT))
+ {
+ return;
+ }
+
+ /* clear the port interrupt */
+ nrf_gpiote_event_clear(NRF_GPIOTE, NRF_GPIOTE_EVENT_PORT);
+
+ /* for each GPIO */
+ for (id = 0; id < BOARD_GPIO_NUMBER; id++)
+ {
+ Gpio_getPin(id, NULL, &pin);
+ /* check if the GPIO latch (= GPIO interrupt flag) is set */
+ if (nrf_gpio_pin_latch_get(pin) != 0)
+ {
+ /* get stored/internal config */
+ event_cb = m_id_to_event_cb_map[id];
+ event_cfg = m_id_to_cfg_map[id].event_cfg;
+
+ sense = nrf_gpio_pin_sense_get(pin);
+ /*
+ * Invoke user handler only if the sensed pin level
+ * matches its polarity configuration.
+ */
+ if (event_cb &&
+ ((IS_RISING_EDGE(event_cfg) && IS_FALLING_EDGE(event_cfg)) ||
+ (sense == NRF_GPIO_PIN_SENSE_HIGH && IS_RISING_EDGE(event_cfg)) ||
+ (sense == NRF_GPIO_PIN_SENSE_LOW && IS_FALLING_EDGE(event_cfg))))
+ {
+ event = (sense == NRF_GPIO_PIN_SENSE_HIGH) ? GPIO_IN_EVENT_RISING_EDGE : GPIO_IN_EVENT_FALLING_EDGE;
+ event_cb(id, event);
+ }
+
+ /*
+ * Reconfigure sense to the opposite level, so the internal PINx.DETECT signal
+ * can be deasserted. Therefore PORT event generated again,
+ * unless some other PINx.DETECT signal is still active.
+ */
+ sense = (sense == NRF_GPIO_PIN_SENSE_HIGH) ? NRF_GPIO_PIN_SENSE_LOW : NRF_GPIO_PIN_SENSE_HIGH;
+ nrf_gpio_cfg_sense_set(pin, sense);
+
+ /*
+ * Try to clear LATCH bit corresponding to currently processed pin.
+ * This may not succeed if the pin's state changed during the interrupt processing
+ * and now it matches the new sense configuration. In such case,
+ * the pin will be processed again in another iteration of the outer loop.
+ */
+ nrf_gpio_pin_latch_clear(pin);
+ }
+ }
+}
+
+#endif // BOARD_GPIO_PIN_LIST
diff --git a/mcu/nrf/common/hal/led.c b/mcu/nrf/common/hal/led.c
deleted file mode 100644
index 0ee11ac6..00000000
--- a/mcu/nrf/common/hal/led.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/* Copyright 2018 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-/*
- * \file led.c
- * \brief Board-specific LED functions for nrf52
- */
-
-#include "led.h"
-#include "mcu.h"
-#include "board.h"
-
-#ifdef BOARD_LED_PIN_LIST
-
-/*
- * The selected board has LEDs
- */
-
-#ifndef BOARD_LED_ACTIVE_LOW
-/** \brief Are LEDs active low. It can be overwritten from board.h */
-#define BOARD_LED_ACTIVE_LOW true
-#endif
-
-/** \brief Board-dependent LED number to pin mapping */
-static const uint8_t pin_map[] = BOARD_LED_PIN_LIST;
-
-/** \brief Compute number of leds on the board */
-#define NUMBER_OF_LEDS (sizeof(pin_map) / sizeof(pin_map[0]))
-
-static void led_configure(uint_fast8_t led_num)
-{
- uint_fast8_t pin_num = pin_map[led_num];
-
- nrf_gpio_cfg_output(pin_num);
-
- // Off by default
-#if BOARD_LED_ACTIVE_LOW
- nrf_gpio_pin_set(pin_num);
-#else // BOARD_LED_ACTIVE_LOW
- nrf_gpio_pin_clear(pin_num);
-#endif // BOARD_LED_ACTIVE_LOW
-}
-
-void Led_init(void)
-{
- for (uint8_t i = 0; i < NUMBER_OF_LEDS; i++)
- {
- // Set up LED GPIO
- led_configure(i);
- }
-}
-
-bool Led_get(uint8_t led_id)
-{
- if (led_id >= (sizeof(pin_map) / sizeof(pin_map[0])))
- {
- return LED_RES_INVALID_ID;
- }
- uint_fast8_t pin_num = pin_map[led_id];
-#if BOARD_LED_ACTIVE_LOW
- return (nrf_gpio_pin_out_read(pin_num) == 0);
-#else //BOARD_LED_ACTIVE_HIGH
- return (nrf_gpio_pin_out_read(pin_num) != 0);
-#endif // BOARD_LED_ACTIVE_LOW
-}
-
-led_res_e Led_set(uint8_t led_id, bool state)
-{
- if (led_id >= (sizeof(pin_map) / sizeof(pin_map[0])))
- {
- return LED_RES_INVALID_ID;
- }
-
- uint_fast8_t pin_num = pin_map[led_id];
-
-#if BOARD_LED_ACTIVE_LOW
- if (state)
- {
- nrf_gpio_pin_clear(pin_num);
- }
- else
- {
- nrf_gpio_pin_set(pin_num);
- }
-#else // BOARD_LED_ACTIVE_LOW
- if (state)
- {
- nrf_gpio_pin_set(pin_num);
- }
- else
- {
- nrf_gpio_pin_clear(pin_num);
- }
-#endif // BOARD_LED_ACTIVE_LOW
-
- return LED_RES_OK;
-}
-
-led_res_e Led_toggle(uint8_t led_id)
-{
- if (led_id >= (sizeof(pin_map) / sizeof(pin_map[0])))
- {
- return LED_RES_INVALID_ID;
- }
-
- uint_fast8_t pin_num = pin_map[led_id];
-
- nrf_gpio_pin_toggle(pin_num);
-
- return LED_RES_OK;
-}
-
-uint8_t Led_getNumber(void)
-{
- return NUMBER_OF_LEDS;
-}
-
-#else // BOARD_LED_PIN_LIST
-
-/*
- * The selected board has no LEDs
- *
- * As some example apps support such boards but also provide extra status
- * information when a board has LEDs, the LED driver has this dummy
- * implementation to simplify the build process.
- */
-
-void Led_init(void)
-{
- // Do nothing
-}
-
-led_res_e Led_set(uint8_t led_id, bool state)
-{
- (void) led_id;
- (void) state;
-
- // Invalid LED number
- return LED_RES_INVALID_ID;
-}
-
-led_res_e Led_toggle(uint8_t led_id)
-{
- (void) led_id;
-
- // Invalid LED number
- return LED_RES_INVALID_ID;
-}
-
-uint8_t Led_getNumber(void)
-{
- return 0;
-}
-
-#endif // BOARD_LED_PIN_LIST
diff --git a/mcu/nrf/common/hal/spi.c b/mcu/nrf/common/hal/spi.c
index d8a22c14..805efd2b 100644
--- a/mcu/nrf/common/hal/spi.c
+++ b/mcu/nrf/common/hal/spi.c
@@ -26,8 +26,20 @@ void __attribute__((__interrupt__)) SPI_IRQHandler(void);
#elif defined(USE_SPI2)
#define SPI_IRQn SPIM2_SPIS2_SPI2_IRQn
#define SPI_DEV NRF_SPIM2
+#elif defined(USE_SPI3)
+#if MCU_SUB == 832
+#error SPI3 is not available on nrf52832
+#endif
+#define SPI_IRQn SPIM3_IRQn
+#define SPI_DEV NRF_SPIM3
#else
-#error USE_SPI0 or USE_SPI1 or USE_SPI2 must be defined
+#error You must specify either USE_SPI0, USE_SPI1, USE_SPI2 or USE_SPI3 (nrf52833 and nrf52840 only) in your board.h
+#endif
+
+#if MCU_SUB == 832
+#define MAX_XFER_SIZE UINT8_MAX
+#else
+#define MAX_XFER_SIZE UINT16_MAX
#endif
/** Is SPI module initialized */
@@ -295,6 +307,13 @@ spi_res_e SPI_transfer(spi_xfer_t * xfer_p,
return SPI_RES_INVALID_XFER;
}
+ // Check transfer size
+ if ((xfer_p->write_size > MAX_XFER_SIZE) || (xfer_p->read_size > MAX_XFER_SIZE))
+ {
+ return SPI_RES_INVALID_XFER;
+ }
+
+
// Enable SPIM module
SPI_DEV->ENABLE =
(SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos);
diff --git a/mcu/nrf/common/mcu.h b/mcu/nrf/common/mcu.h
index b0e5e760..272a2944 100644
--- a/mcu/nrf/common/mcu.h
+++ b/mcu/nrf/common/mcu.h
@@ -21,8 +21,15 @@
#define GPIOTE_IRQn GPIOTE0_IRQn
#define UART0_IRQn UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQn
/** Define the last IRQ number in the interrupt vector */
+#elif MCU_SUB == 61
+#define NRF9120_XXAA
+/** Define NRF_GPIO and GPIOTE_IRQn for nrf9160. */
+#define NRF_GPIO NRF_P0
+#define GPIOTE_IRQn GPIOTE0_IRQn
+#define UART0_IRQn UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQn
+/** Define the last IRQ number in the interrupt vector */
#else
-#error SUB_MCU Must be 832 or 840 or 60
+#error SUB_MCU Must be 832 or 840 or 60 or 61
#endif
#include "nrfx.h"
diff --git a/mcu/nrf/common/vendor/drivers/nrfx_common.h b/mcu/nrf/common/vendor/drivers/nrfx_common.h
index b6d86ca3..70f9d466 100644
--- a/mcu/nrf/common/vendor/drivers/nrfx_common.h
+++ b/mcu/nrf/common/vendor/drivers/nrfx_common.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA
+ * Copyright (c) 2017 - 2023, Nordic Semiconductor ASA
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -37,14 +37,29 @@
#include
#include
#include
+#include
#include
+#include "nrfx_utils.h"
#include
+#include "nrfx_ext.h"
#ifdef __cplusplus
extern "C" {
#endif
+#if defined(__CORTEX_M) || defined(__NRFX_DOXYGEN__)
+#define ISA_ARM 1
+#elif defined(__VPR_REV)
+#define ISA_RISCV 1
+#else
+#define ISA_UNKNOWN 1
+#endif
+
+#if defined(ISA_RISCV)
+#define __STATIC_INLINE static inline
+#endif
+
#ifndef NRFX_STATIC_INLINE
#ifdef NRFX_DECLARE_ONLY
#define NRFX_STATIC_INLINE
@@ -53,6 +68,8 @@ extern "C" {
#endif
#endif // NRFX_STATIC_INLINE
+#define NRFY_STATIC_INLINE __STATIC_INLINE
+
#ifndef NRF_STATIC_INLINE
#ifdef NRF_DECLARE_ONLY
#define NRF_STATIC_INLINE
@@ -78,7 +95,55 @@ extern "C" {
* such warnings only in places where this macro is used for evaluation, not in
* the whole analyzed code.
*/
-#define NRFX_CHECK(module_enabled) (module_enabled)
+#define NRFX_CHECK(module_enabled) (module_enabled)
+
+/**
+ * @brief Macro for checking if the configured API version is greater than or equal
+ * to the specified API version.
+ *
+ * @note API version to be used is configured using following symbols:
+ * - @ref NRFX_CONFIG_API_VER_MAJOR
+ * - @ref NRFX_CONFIG_API_VER_MINOR
+ * - @ref NRFX_CONFIG_API_VER_MICRO
+ *
+ * @param[in] major Major API version.
+ * @param[in] minor Minor API version.
+ * @param[in] micro Micro API version.
+ *
+ * @retval true Configured API version is greater than or equal to the specified API version.
+ * @retval false Configured API version is smaller than the specified API version.
+ */
+#define NRFX_API_VER_AT_LEAST(major, minor, micro) \
+ ((NRFX_CONFIG_API_VER_MAJOR >= (major)) && \
+ (NRFX_CONFIG_API_VER_MINOR >= (minor)) && \
+ (NRFX_CONFIG_API_VER_MICRO >= (micro)))
+
+/**
+ * @brief Macro for creating unsigned integer with bit position @p x set.
+ *
+ * @param[in] x Bit position to be set.
+ *
+ * @return Unsigned integer with requested bit position set.
+ */
+#define NRFX_BIT(x) (1UL << (x))
+
+/**
+ * @brief Macro for returning bit mask or 0 if @p x is 0.
+ *
+ * @param[in] x Bit mask size. Bit mask has bits 0 through x-1 (inclusive) set.
+ *
+ * @return Bit mask.
+ */
+#define NRFX_BIT_MASK(x) (((x) == 32) ? UINT32_MAX : ((1UL << x) - 1))
+
+/**
+ * @brief Macro for returning size in bits for given size in bytes.
+ *
+ * @param[in] x Size in bytes.
+ *
+ * @return Size in bits.
+ */
+#define NRFX_BIT_SIZE(x) ((x) << 3)
/**
* @brief Macro for concatenating two tokens in macro expansion.
@@ -95,10 +160,10 @@ extern "C" {
*
* @sa NRFX_CONCAT_3
*/
-#define NRFX_CONCAT_2(p1, p2) NRFX_CONCAT_2_(p1, p2)
+#define NRFX_CONCAT_2(p1, p2) NRFX_CONCAT_2_(p1, p2)
/** @brief Internal macro used by @ref NRFX_CONCAT_2 to perform the expansion in two steps. */
-#define NRFX_CONCAT_2_(p1, p2) p1 ## p2
+#define NRFX_CONCAT_2_(p1, p2) p1 ## p2
/**
* @brief Macro for concatenating three tokens in macro expansion.
@@ -116,10 +181,229 @@ extern "C" {
*
* @sa NRFX_CONCAT_2
*/
-#define NRFX_CONCAT_3(p1, p2, p3) NRFX_CONCAT_3_(p1, p2, p3)
+#define NRFX_CONCAT_3(p1, p2, p3) NRFX_CONCAT_3_(p1, p2, p3)
/** @brief Internal macro used by @ref NRFX_CONCAT_3 to perform the expansion in two steps. */
-#define NRFX_CONCAT_3_(p1, p2, p3) p1 ## p2 ## p3
+#define NRFX_CONCAT_3_(p1, p2, p3) p1 ## p2 ## p3
+
+/**
+ * @brief Macro for computing the absolute value of an integer number.
+ *
+ * @param[in] a Input value.
+ *
+ * @return Absolute value.
+ */
+#define NRFX_ABS(a) ((a) < (0) ? -(a) : (a))
+
+/**
+ * @brief Macro for checking whether any of the instance of the specified peripheral supports a given feature.
+ *
+ * Macro checks flags set in \_peripherals.h file.
+ *
+ * Macro supports check on instances with following names:
+ * - \0 - \255 - e.g. SPIM0, SPIM255
+ * - \00 - \099 - e.g. SPIM00, SPIM099
+ * - \000 - \009 - e.g. SPIM000, SPIM009
+ *
+ * @param[in] periph_name Peripheral name, e.g. SPIM.
+ * @param[in] feature_name Feature flag name suffix following an instance name, e.g.
+ * _FEATURE_HARDWARE_CSN_PRESENT.
+ *
+ * @retval 1 At least one instance on current device supports a given feature.
+ * @retval 0 None of peripheral instances supports a given feature.
+ */
+#define NRFX_FEATURE_PRESENT(periph_name, feature_name) \
+ NRFX_COND_CODE_0(NRFX_CONCAT(0, \
+ _NRFX_FEATURE_PRESENT(periph_name, feature_name, 256), \
+ _NRFX_FEATURE_PRESENT(NRFX_CONCAT(periph_name, 0), feature_name, 100), \
+ _NRFX_FEATURE_PRESENT(NRFX_CONCAT(periph_name, 00), feature_name, 10) \
+ ), \
+ (0), (1))
+
+/**
+ * @brief Macro for resolving provided user macro for enabled instances of a driver.
+ *
+ * Macro checks if driver instances are enabled for all potential instaces of a
+ * peripheral. It takes peripheral name and checks whether NRFX_\\_ENABLED
+ * is set to 1 and if yes then provided macro is evaluated for given instance.
+ *
+ * Macro supports check on instances with following names:
+ * - \0 - \255 - e.g. SPIM0, SPIM255
+ * - \00 - \099 - e.g. SPIM00, SPIM099
+ * - \000 - \009 - e.g. SPIM000, SPIM009
+ *
+ * @param[in] periph_name Peripheral name, e.g. SPIM.
+ * @param[in] macro Macro which is resolved if driver instance is enabled. Macro has following
+ * arguments: macro(periph_name, prefix, i, ...).
+ * @param[in] sep Separator added between all evaluations, in parentheses.
+ * @param[in] off_code Code injected for disabled instances, in parentheses.
+ */
+#define NRFX_FOREACH_ENABLED(periph_name, macro, sep, off_code, ...) \
+ NRFX_LISTIFY(256, _NRFX_EVAL_IF_ENABLED, sep, \
+ off_code, periph_name, , macro, __VA_ARGS__) NRFX_DEBRACKET sep \
+ NRFX_LISTIFY(100, _NRFX_EVAL_IF_ENABLED, sep, \
+ off_code, periph_name, 0, macro, __VA_ARGS__) NRFX_DEBRACKET sep \
+ NRFX_LISTIFY(10, _NRFX_EVAL_IF_ENABLED, sep, \
+ off_code, periph_name, 00, macro, __VA_ARGS__)
+
+/**
+ * @brief Macro for resolving provided user macro for present instances of a peripheral.
+ *
+ * Macro checks if peripheral instances are present by checking if there is
+ * \\_PRESENT define set to 1.
+ *
+ * Macro supports check on instances with following names:
+ * - \0 - \255 - e.g. SPIM0, SPIM255
+ * - \00 - \099 - e.g. SPIM00, SPIM099
+ * - \000 - \009 - e.g. SPIM000, SPIM009
+ * - \ - e.g. SPIM
+ *
+ * @param[in] periph_name Peripheral name, e.g. SPIM.
+ * @param[in] macro Macro which is resolved if peripheral instance is present.
+ * Macro has following arguments: macro(periph_name, prefix, i, ...).
+ * @param[in] sep Separator added between all evaluations, in parentheses.
+ * @param[in] off_code Code injected for disabled instances, in parentheses.
+ */
+#define NRFX_FOREACH_PRESENT(periph_name, macro, sep, off_code, ...) \
+ NRFX_LISTIFY(256, _NRFX_EVAL_IF_PRESENT, sep, \
+ off_code, periph_name, , macro, __VA_ARGS__) NRFX_DEBRACKET sep \
+ NRFX_LISTIFY(100, _NRFX_EVAL_IF_PRESENT, sep, \
+ off_code, periph_name, 0, macro, __VA_ARGS__) NRFX_DEBRACKET sep \
+ NRFX_LISTIFY(10, _NRFX_EVAL_IF_PRESENT, sep, \
+ off_code, periph_name, 00, macro, __VA_ARGS__) NRFX_DEBRACKET sep \
+ _NRFX_EVAL_IF_PRESENT(, off_code, periph_name, , macro, __VA_ARGS__)
+
+/**
+ * @brief Macro for resolving provided user macro on concatenated peripheral name
+ * and instance index.
+ *
+ * Execute provided macro with single argument
+ * that is the concatenation of @p periph_name, @p prefix and @p i.
+ *
+ * @param[in] i Instance index.
+ * @param[in] periph_name Peripheral name, e.g. SPIM.
+ * @param[in] prefix Prefix added before instance index, e.g. some device has
+ * instances named like SPIM00. First 0 is passed here as prefix.
+ * @param[in] macro Macro which is executed.
+ * @param[in] ... Variable length arguments passed to the @p macro. Macro has following
+ * arguments: macro(instance, ...).
+ */
+#define NRFX_INSTANCE_CONCAT(periph_name, prefix, i, macro, ...) \
+ macro(NRFX_CONCAT(periph_name, prefix, i), __VA_ARGS__)
+
+/**
+ * @brief Macro for creating a content for enum which is listing enabled driver instances.
+ *
+ * It creates comma separated list of entries like NRFX_\_INST_IDX,
+ * e.g. (NRFX_SPIM0_INST_IDX) for all enabled instances (NRFX_\_ENABLED
+ * is set to 1). It should be called within enum declaration. Created enum is used
+ * by the driver to index all enabled instances of the driver.
+ *
+ * @param[in] periph_name Peripheral name (e.g. SPIM).
+ */
+#define NRFX_INSTANCE_ENUM_LIST(periph_name) \
+ NRFX_FOREACH_ENABLED(periph_name, _NRFX_INST_ENUM, (), ())
+
+/**
+ * @brief Macro for creating an interrupt handler for all enabled driver instances.
+ *
+ * Macro creates a set of functions which calls generic @p irq_handler function with two parameters:
+ * - peripheral instance register pointer
+ * - pointer to a control block structure associated with the given instance
+ *
+ * Generic interrupt handler function with above mentioned parameters named @p irq_handler
+ * must be implemented in the driver.
+ *
+ * @note Handlers are using enum which should be generated using @ref NRFX_INSTANCE_ENUM_LIST.
+ *
+ * @param[in] periph_name Peripheral name, e.g. SPIM.
+ * @param[in] periph_name_small Peripheral name written with small letters, e.g. spim.
+ */
+#define NRFX_INSTANCE_IRQ_HANDLERS(periph_name, periph_name_small) \
+ NRFX_FOREACH_ENABLED(periph_name, _NRFX_IRQ_HANDLER, (), (), periph_name_small)
+
+/**
+ * @brief Macro for creating an interrupt handler for all enabled driver instances
+ * with the specified extra parameter.
+ *
+ * Macro creates set of function which calls generic @p irq_handler function with three parameters:
+ * - peripheral instance register pointer
+ * - pointer to a control block structure associated with the given instance
+ * - provided @p ext_macro called with peripheral name suffix (e.g. 01 for TIMER01)
+ *
+ * Generic interrupt handler function with above mentioned parameters named @p irq_handler
+ * must be implemented in the driver.
+ *
+ * @note Handlers are using enum which should be generated using @ref NRFX_INSTANCE_ENUM_LIST.
+ *
+ * @param[in] periph_name Peripheral name, e.g. SPIM.
+ * @param[in] periph_name_small Peripheral name written with small letters, e.g. rtc.
+ * @param[in] ext_macro External macro to be executed for each instance.
+ */
+#define NRFX_INSTANCE_IRQ_HANDLERS_EXT(periph_name, periph_name_small, ext_macro) \
+ NRFX_FOREACH_ENABLED(periph_name, _NRFX_IRQ_HANDLER_EXT, (), (), periph_name_small, ext_macro)
+
+/**
+ * @brief Macro for declaring an interrupt handler for all enabled driver instances.
+ *
+ * Macro creates set of function declarations. It is intended to be used in the driver header.
+ *
+ * @param[in] periph_name Peripheral name, e.g. SPIM.
+ * @param[in] periph_name_small Peripheral name written with small letters, e.g. spim.
+ */
+#define NRFX_INSTANCE_IRQ_HANDLERS_DECLARE(periph_name, periph_name_small) \
+ NRFX_FOREACH_ENABLED(periph_name, _NRFX_IRQ_HANDLER_DECLARE, (), (), periph_name_small)
+
+/**
+ * @brief Macro for generating comma-separated list of interrupt handlers for all
+ * enabled driver instances.
+ *
+ * Interrupt handlers are generated using @ref NRFX_INSTANCE_IRQ_HANDLERS.
+ * It is intended to be used to create a list which is used for passing an interrupt
+ * handler function to the PRS driver.
+ *
+ * @param[in] periph_name Peripheral name, e.g. SPIM.
+ * @param[in] periph_name_small Peripheral name written with small letters, e.g. spim.
+ */
+#define NRFX_INSTANCE_IRQ_HANDLERS_LIST(periph_name, periph_name_small) \
+ NRFX_FOREACH_ENABLED(periph_name, _NRFX_IRQ_HANDLER_LIST, (), (), periph_name_small)
+
+/**
+ * @brief Macro for checking if given peripheral instance is present on the target.
+ *
+ * Macro utilizes the fact that for each existing instance a define is created which points to
+ * the memory mapped register set casted to a register set structure. It is wrapped in parenthesis
+ * and existance of parethesis wrapping is used to determine if instance exists. It if does not
+ * exist then token (e.g. NRF_SPIM10) is undefined so it does not have parenthesis wrapping.
+ *
+ * Since macro returns literal 1 it can be used by other macros.
+ *
+ * @param[in] _inst Instance, .e.g SPIM10.
+ *
+ * @retval 1 If instance is present.
+ * @retval 0 If instance is not present.
+ */
+#define NRFX_INSTANCE_PRESENT(_inst) NRFX_ARG_HAS_PARENTHESIS(NRFX_CONCAT(NRF_, _inst))
+
+/**
+ * @brief Macro for getting the smaller value between two arguments.
+ *
+ * @param[in] a First argument.
+ * @param[in] b Second argument.
+ *
+ * @return Smaller value between two arguments.
+ */
+#define NRFX_MIN(a, b) ((a) < (b) ? (a) : (b))
+
+/**
+ * @brief Macro for getting the larger value between two arguments.
+ *
+ * @param[in] a First argument.
+ * @param[in] b Second argument.
+ *
+ * @return Larger value between two arguments.
+ */
+#define NRFX_MAX(a, b) ((a) > (b) ? (a) : (b))
/**
* @brief Macro for performing rounded integer division (as opposed to
@@ -130,7 +414,8 @@ extern "C" {
*
* @return Rounded (integer) result of dividing @c a by @c b.
*/
-#define NRFX_ROUNDED_DIV(a, b) (((a) + ((b) / 2)) / (b))
+#define NRFX_ROUNDED_DIV(a, b) \
+ ((((a) < 0) ^ ((b) < 0)) ? (((a) - (b) / 2) / (b)) : (((a) + (b) / 2) / (b)))
/**
* @brief Macro for performing integer division, making sure the result is rounded up.
@@ -143,7 +428,7 @@ extern "C" {
*
* @return Integer result of dividing @c a by @c b, rounded up.
*/
-#define NRFX_CEIL_DIV(a, b) ((((a) - 1) / (b)) + 1)
+#define NRFX_CEIL_DIV(a, b) ((((a) - 1) / (b)) + 1)
/**
* @brief Macro for getting the number of elements in an array.
@@ -163,9 +448,30 @@ extern "C" {
*
* @return Member offset in bytes.
*/
-#define NRFX_OFFSETOF(type, member) ((size_t)&(((type *)0)->member))
+#define NRFX_OFFSETOF(type, member) ((size_t) & (((type *)0)->member))
-/**@brief Macro for checking if given lengths of EasyDMA transfers do not exceed
+/**
+ * @brief Macro for checking whether given number is power of 2.
+ *
+ * @param[in] val Tested value.
+ *
+ * @retval true The value is power of 2.
+ * @retval false The value is not power of 2.
+ */
+#define NRFX_IS_POWER_OF_TWO(val) (((val) != 0) && ((val) & ((val) - 1)) == 0)
+
+/**
+ * @brief Macro for checking whether a given number is even.
+ *
+ * @param[in] val Tested value.
+ *
+ * @retval true The value is even.
+ * @retval false The value is odd.
+ */
+#define NRFX_IS_EVEN(val) (((val) % 2) == 0)
+
+/**
+ * @brief Macro for checking if given lengths of EasyDMA transfers do not exceed
* the limit of the specified peripheral.
*
* @param[in] peripheral Peripheral to check the lengths against.
@@ -213,7 +519,7 @@ do { \
*
* @return ID number associated with the specified peripheral.
*/
-#define NRFX_PERIPHERAL_ID_GET(base_addr) (uint8_t)((uint32_t)(base_addr) >> 12)
+#define NRFX_PERIPHERAL_ID_GET(base_addr) (uint16_t)(((uint32_t)(base_addr) >> 12) & 0x000001FF)
/**
* @brief Macro for getting the interrupt number assigned to a specific
@@ -227,7 +533,25 @@ do { \
*
* @return Interrupt number associated with the specified peripheral.
*/
-#define NRFX_IRQ_NUMBER_GET(base_addr) NRFX_PERIPHERAL_ID_GET(base_addr)
+#define NRFX_IRQ_NUMBER_GET(base_addr) NRFX_PERIPHERAL_ID_GET(base_addr)
+
+/**
+ * @brief Macro for converting frequency in kHz to Hz.
+ *
+ * @param[in] freq Frequency value in kHz.
+ *
+ * @return Number of Hz in @p freq kHz.
+ */
+#define NRFX_KHZ_TO_HZ(freq) ((freq) * 1000)
+
+/**
+ * @brief Macro for converting frequency in MHz to Hz.
+ *
+ * @param[in] freq Frequency value in MHz.
+ *
+ * @return Number of Hz in @p freq MHz.
+ */
+#define NRFX_MHZ_TO_HZ(freq) ((freq) * 1000 * 1000)
/** @brief IRQ handler type. */
typedef void (* nrfx_irq_handler_t)(void);
@@ -240,7 +564,6 @@ typedef enum
NRFX_DRV_STATE_POWERED_ON, ///< Initialized and powered on.
} nrfx_drv_state_t;
-
/**
* @brief Function for checking if an object is placed in the Data RAM region.
*
@@ -310,7 +633,6 @@ NRF_STATIC_INLINE uint32_t nrfx_bitpos_to_event(uint32_t bit);
*/
NRF_STATIC_INLINE uint32_t nrfx_event_to_bitpos(uint32_t event);
-
#ifndef NRF_DECLARE_ONLY
NRF_STATIC_INLINE bool nrfx_is_in_ram(void const * p_object)
diff --git a/mcu/nrf/common/vendor/drivers/nrfx_errors.h b/mcu/nrf/common/vendor/drivers/nrfx_errors.h
index 26f3f4a2..d5c791cd 100644
--- a/mcu/nrf/common/vendor/drivers/nrfx_errors.h
+++ b/mcu/nrf/common/vendor/drivers/nrfx_errors.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA
+ * Copyright (c) 2017 - 2023, Nordic Semiconductor ASA
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
diff --git a/mcu/nrf/common/vendor/drivers/nrfx_ext.h b/mcu/nrf/common/vendor/drivers/nrfx_ext.h
new file mode 100644
index 00000000..fc02a442
--- /dev/null
+++ b/mcu/nrf/common/vendor/drivers/nrfx_ext.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2022 - 2023, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRFX_EXT_H__
+#define NRFX_EXT_H__
+
+#endif // NRFX_EXT_H__
diff --git a/mcu/nrf/common/vendor/drivers/nrfx_utils.h b/mcu/nrf/common/vendor/drivers/nrfx_utils.h
new file mode 100644
index 00000000..a5e1cc91
--- /dev/null
+++ b/mcu/nrf/common/vendor/drivers/nrfx_utils.h
@@ -0,0 +1,348 @@
+/*
+ * Copyright (c) 2022 - 2023, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRFX_UTILS_H__
+#define NRFX_UTILS_H__
+
+#include "nrfx_utils_internal.h"
+
+/**
+ * @defgroup nrfx_utils Preprocessor utility macros
+ * @{
+ * @ingroup nrfx
+ * @brief Preprocessor utility macros.
+ */
+
+/**
+ * @brief Macro for inserting code depending on whether @p _flag exists and expands to 1 or not.
+ *
+ * To prevent the preprocessor from treating commas as argument
+ * separators, the @p _if_1_code and @p _else_code expressions must be
+ * inside brackets/parentheses: (). These are stripped away
+ * during macro expansion.
+ *
+ * Example:
+ *
+ * NRFX_COND_CODE_1(CONFIG_FLAG, (uint32_t x;), (there_is_no_flag();))
+ *
+ * If @p CONFIG_FLAG is defined to 1, this expands to:
+ *
+ * uint32_t x;
+ *
+ * It expands to there_is_no_flag(); otherwise.
+ *
+ * This could be used as an alternative to:
+ *
+ * #if defined(CONFIG_FLAG) && (CONFIG_FLAG == 1)
+ * #define MAYBE_DECLARE(x) uint32_t x
+ * #else
+ * #define MAYBE_DECLARE(x) there_is_no_flag()
+ * #endif
+ *
+ * MAYBE_DECLARE(x);
+ *
+ * However, the advantage of COND_CODE_1() is that code is resolved in
+ * place where it is used, while the @p \#if method defines @p
+ * MAYBE_DECLARE on two lines and requires it to be invoked again on a
+ * separate line. This makes COND_CODE_1() more concise and also
+ * sometimes more useful when used within another macro's expansion.
+ *
+ * @note @p _flag can be the result of preprocessor expansion,
+ * however @p _if_1_code is only expanded if @p _flag expands
+ * to the integer literal 1. Integer expressions that evaluate
+ * to 1, e.g. after doing some arithmetic, will not work.
+ *
+ * @param[in] _flag Evaluated flag
+ * @param[in] _if_1_code Result if @p _flag expands to 1; must be in parentheses
+ * @param[in] _else_code Result otherwise; must be in parentheses
+ */
+#define NRFX_COND_CODE_1(_flag, _if_1_code, _else_code) \
+ _NRFX_COND_CODE_1(_flag, _if_1_code, _else_code)
+
+/**
+ * @brief Macro for inserting code depending on whether @p _flag exists and expands to 0 or not.
+ *
+ * This is like @ref NRFX_COND_CODE_1(), except that it tests whether @p _flag
+ * expands to the integer literal 0. It expands to @p _if_0_code if
+ * so, and @p _else_code otherwise; both of these must be enclosed in
+ * parentheses.
+ *
+ * @param[in] _flag Evaluated flag
+ * @param[in] _if_0_code Result if @p _flag expands to 0; must be in parentheses
+ * @param[in] _else_code Result otherwise; must be in parentheses
+ */
+#define NRFX_COND_CODE_0(_flag, _if_0_code, _else_code) \
+ _NRFX_COND_CODE_0(_flag, _if_0_code, _else_code)
+
+/**
+ * @brief Macro for checking for macro definition in compiler-visible expressions
+ *
+ * It has the effect of taking a macro value that may be defined to "1"
+ * or may not be defined at all and turning it into a literal
+ * expression that can be handled by the C compiler instead of just
+ * the preprocessor.
+ *
+ * That is, it works similarly to \#if defined(CONFIG_FOO)
+ * except that its expansion is a C expression. Thus, much \#ifdef
+ * usage can be replaced with equivalents like:
+ *
+ * if (IS_ENABLED(CONFIG_FOO)) {
+ * do_something_with_foo
+ * }
+ *
+ * This is cleaner since the compiler can generate errors and warnings
+ * for @p do_something_with_foo even when @p CONFIG_FOO is undefined.
+ *
+ * @param[in] config_macro Macro to check
+ *
+ * @return 1 if @p config_macro is defined to 1, 0 otherwise (including
+ * if @p config_macro is not defined)
+ */
+#define NRFX_IS_ENABLED(config_macro) _NRFX_IS_ENABLED1(config_macro)
+
+/**
+ * @brief Macro for generating a sequence of code with configurable separator.
+ *
+ * Example:
+ *
+ * #define FOO(i, _) MY_PWM ## i
+ * { NRFX_LISTIFY(PWM_COUNT, FOO, (,)) }
+ *
+ * The above two lines expand to:
+ *
+ * { MY_PWM0 , MY_PWM1 }
+ *
+ * @param[in] LEN The length of the sequence. Must be an integer literal less
+ * than 255.
+ * @param[in] F A macro function that accepts at least two arguments:
+ * F(i, ...). @p F is called repeatedly in the expansion.
+ * Its first argument @p i is the index in the sequence, and
+ * the variable list of arguments passed to LISTIFY are passed
+ * through to @p F.
+ * @param[in] sep Separator (e.g. comma or semicolon). Must be in parentheses;
+ * this is required to enable providing a comma as separator.
+ *
+ * @note Calling NRFX_LISTIFY with undefined arguments has undefined behavior.
+ */
+#define NRFX_LISTIFY(LEN, F, sep, ...) \
+ NRFX_CONCAT_2(_NRFX_LISTIFY_, LEN)(F, sep, __VA_ARGS__)
+
+/**
+ * @brief Macro for checking if input argument is empty.
+ *
+ * Empty means that nothing is provided or provided value is resolved to nothing
+ * (e.g. empty define).
+ *
+ * Macro idea is taken from P99 which is under Apache 2.0 license and described by
+ * Jens Gustedt https://gustedt.wordpress.com/2010/06/08/detect-empty-macro-arguments/
+ *
+ * @param arg Argument.
+ *
+ * @retval 1 if argument is empty.
+ * @retval 0 if argument is not empty.
+ */
+#define NRFX_IS_EMPTY(arg) _NRFX_IS_EMPTY(arg)
+
+/**
+ * @brief Macro for calculating number of arguments in the variable arguments list minus one.
+ *
+ * @param[in] ... List of arguments
+ *
+ * @return Number of variadic arguments in the argument list, minus one
+ */
+#define NRFX_NUM_VA_ARGS_LESS_1(...) \
+ _NRFX_NUM_VA_ARGS_LESS_1_IMPL(__VA_ARGS__, 63, 62, 61, \
+ 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
+ 50, 49, 48, 47, 46, 45, 44, 43, 42, 41, \
+ 40, 39, 38, 37, 36, 35, 34, 33, 32, 31, \
+ 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, \
+ 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, \
+ 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, ~)
+
+/**
+ * @brief Macro for concatenating multiple arguments.
+ *
+ * Support up to 8 arguments.
+ *
+ * @param[in] ... Arguments to concatenate.
+ */
+#define NRFX_CONCAT(...) \
+ NRFX_CONCAT_2(_NRFX_CONCAT_, NRFX_NUM_VA_ARGS_LESS_1(__VA_ARGS__))(__VA_ARGS__)
+
+/**
+ * @brief Macro for checking if argument starts with opening round bracket and contains matching
+ * closing bracket (parenthesis).
+ *
+ * @param[in] x Input argument.
+ *
+ * @retval 1 If input argument starts with opening bracket and contains closing bracket.
+ * @retval 0 If input argument does not match above mentioned condition.
+ */
+#define NRFX_ARG_HAS_PARENTHESIS(x) _NRFX_GET_ARG3(_NRFX_EVAL(_NRFX_ARG_HAS_PARENTHESIS x, 1, 0))
+
+/**
+ * @brief Macro for calling a macro @p F on each provided argument with a given
+ * separator between each call.
+ *
+ * Example:
+ *
+ * #define F(x) int a##x
+ * NRFX_FOR_EACH(F, (;), 4, 5, 6);
+ *
+ * This expands to:
+ *
+ * int a4;
+ * int a5;
+ * int a6;
+ *
+ * @param F Macro to invoke
+ * @param sep Separator (e.g. comma or semicolon). Must be in parentheses;
+ * this is required to enable providing a comma as a separator.
+ * @param ... Variable argument list. The macro @p F is invoked as
+ * F(element) for each element in the list.
+ */
+#define NRFX_FOR_EACH(F, sep, ...) \
+ _NRFX_FOR_EACH(F, sep, NRFX_REVERSE_ARGS(__VA_ARGS__))
+
+/**
+ * @brief Call macro @p F on each provided argument, with the argument's index
+ * as an additional parameter.
+ *
+ * This is like @ref NRFX_FOR_EACH(), except @p F should be a macro which takes two
+ * arguments: F(index, variable_arg).
+ *
+ * Example:
+ *
+ * #define F(idx, x) int a##idx = x
+ * NRFX_FOR_EACH_IDX(F, (;), 4, 5, 6);
+ *
+ * This expands to:
+ *
+ * int a0 = 4;
+ * int a1 = 5;
+ * int a2 = 6;
+ *
+ * @param F Macro to invoke
+ * @param sep Separator (e.g. comma or semicolon). Must be in parentheses;
+ * this is required to enable providing a comma as a separator.
+ * @param ... Variable argument list. The macro @p F is invoked as
+ * F(index, element) for each element in the list.
+ */
+#define NRFX_FOR_EACH_IDX(F, sep, ...) \
+ _NRFX_FOR_EACH_IDX(F, sep, NRFX_REVERSE_ARGS(__VA_ARGS__))
+
+/**
+ * @brief Macro for calling macro @p F on each provided argument, with an additional fixed
+ * argument as a parameter.
+ *
+ * This is like @ref NRFX_FOR_EACH(), except @p F should be a macro which takes two
+ * arguments: F(variable_arg, fixed_arg).
+ *
+ * Example:
+ *
+ * static void func(int val, void *dev);
+ * NRFX_FOR_EACH_FIXED_ARG(func, (;), dev, 4, 5, 6);
+ *
+ * This expands to:
+ *
+ * func(4, dev);
+ * func(5, dev);
+ * func(6, dev);
+ *
+ * @param F Macro to invoke
+ * @param sep Separator (e.g. comma or semicolon). Must be in parentheses;
+ * this is required to enable providing a comma as a separator.
+ * @param fixed_arg Fixed argument passed to @p F as the second macro parameter.
+ * @param ... Variable argument list. The macro @p F is invoked as
+ * F(element, fixed_arg) for each element in the list.
+ */
+#define NRFX_FOR_EACH_FIXED_ARG(F, sep, fixed_arg, ...) \
+ _NRFX_FOR_EACH_FIXED_ARG(F, sep, fixed_arg, NRFX_REVERSE_ARGS(__VA_ARGS__))
+
+/**
+ * @brief Macro from calling macro @p F for each variable argument with an index and fixed
+ * argument
+ *
+ * This is like the combination of @ref NRFX_FOR_EACH_IDX() with @ref NRFX_FOR_EACH_FIXED_ARG().
+ *
+ * Example:
+ *
+ * #define F(idx, x, fixed_arg) int fixed_arg##idx = x
+ * NRFX_FOR_EACH_IDX_FIXED_ARG(F, (;), a, 4, 5, 6);
+ *
+ * This expands to:
+ *
+ * int a0 = 4;
+ * int a1 = 5;
+ * int a2 = 6;
+ *
+ * @param F Macro to invoke
+ * @param sep Separator (e.g. comma or semicolon). Must be in parentheses;
+ * This is required to enable providing a comma as a separator.
+ * @param fixed_arg Fixed argument passed to @p F as the third macro parameter.
+ * @param ... Variable list of arguments. The macro @p F is invoked as
+ * F(index, element, fixed_arg) for each element in
+ * the list.
+ */
+#define NRFX_FOR_EACH_IDX_FIXED_ARG(F, sep, fixed_arg, ...) \
+ _NRFX_FOR_EACH_IDX_FIXED_ARG(F, sep, fixed_arg, NRFX_REVERSE_ARGS(__VA_ARGS__))
+
+/**
+ * @brief Macro for reversing arguments order.
+ *
+ * @param ... Variable argument list.
+ *
+ * @return Input arguments in reversed order.
+ */
+#define NRFX_REVERSE_ARGS(...) \
+ _NRFX_FOR_EACH_ENGINE(_NRFX_FOR_EACH_EXEC, (,), NRFX_EVAL, _, __VA_ARGS__)
+
+
+/**
+ * @brief Macro for getting the highest value from input arguments.
+ *
+ * It is similar to @ref NRFX_MAX but accepts a variable number of arguments.
+ *
+ * @note Input arguments must be numeric variables.
+ *
+ * @param ... Variable argument list.
+ *
+ * @return Highest value from the input list.
+ */
+#define NRFX_MAX_N(...) \
+ NRFX_EVAL(NRFX_FOR_EACH(_NRFX_MAX_P1, (), __VA_ARGS__) 0 \
+ NRFX_FOR_EACH(_NRFX_MAX_P2, (), __VA_ARGS__))
+
+/** @} */
+
+#endif /* NRFX_UTILS_H__ */
diff --git a/mcu/nrf/common/vendor/drivers/nrfx_utils_internal.h b/mcu/nrf/common/vendor/drivers/nrfx_utils_internal.h
new file mode 100644
index 00000000..4c742b9b
--- /dev/null
+++ b/mcu/nrf/common/vendor/drivers/nrfx_utils_internal.h
@@ -0,0 +1,1730 @@
+/*
+ * Copyright (c) 2022 - 2023, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRFX_UTILS_INTERNAL_H__
+#define NRFX_UTILS_INTERNAL_H__
+
+/* NRFX_IS_ENABLED() helpers */
+
+/* This is called from NRFX_IS_ENABLED(), and sticks on a "_XXXX" prefix,
+ * it will now be "_XXXX1" if config_macro is "1", or just "_XXXX" if it's
+ * undefined.
+ * ENABLED: NRFX_IS_ENABLED2(_XXXX1)
+ * DISABLED NRFX_IS_ENABLED2(_XXXX)
+ */
+#define _NRFX_IS_ENABLED1(config_macro) _NRFX_IS_ENABLED2(_XXXX##config_macro)
+
+/* Here's the core trick, we map "_XXXX1" to "_YYYY," (i.e. a string
+ * with a trailing comma), so it has the effect of making this a
+ * two-argument tuple to the preprocessor only in the case where the
+ * value is defined to "1"
+ * ENABLED: _YYYY, <--- note comma!
+ * DISABLED: _XXXX
+ */
+#define _XXXX1 _YYYY,
+
+/* Then we append an extra argument to fool the gcc preprocessor into
+ * accepting it as a varargs macro.
+ * arg1 arg2 arg3
+ * ENABLED: NRFX_IS_ENABLED3(_YYYY, 1, 0)
+ * DISABLED NRFX_IS_ENABLED3(_XXXX 1, 0)
+ */
+#define _NRFX_IS_ENABLED2(one_or_two_args) _NRFX_IS_ENABLED3(one_or_two_args 1, 0)
+
+/* And our second argument is thus now cooked to be 1 in the case
+ * where the value is defined to 1, and 0 if not:
+ */
+#define _NRFX_IS_ENABLED3(ignore_this, val, ...) val
+
+/* Used internally by NRFX_COND_CODE_1 and NRFX_COND_CODE_0. */
+#define _NRFX_COND_CODE_1(_flag, _if_1_code, _else_code) \
+ _NRFX_COND_CODE1(_XXXX##_flag, _if_1_code, _else_code)
+
+#define _NRFX_COND_CODE_0(_flag, _if_0_code, _else_code) \
+ _NRFX_COND_CODE1(_ZZZZ##_flag, _if_0_code, _else_code)
+
+#define _ZZZZ0 _YYYY,
+
+#define _NRFX_COND_CODE1(one_or_two_args, _if_code, _else_code) \
+ NRFX_GET_ARG2_DEBRACKET(one_or_two_args _if_code, _else_code)
+
+#define NRFX_GET_ARG2_DEBRACKET(ignore_this, val, ...) NRFX_DEBRACKET val
+
+#define NRFX_DEBRACKET(...) __VA_ARGS__
+
+#define NRFX_EVAL(...) __VA_ARGS__
+
+#define NRFX_EMPTY()
+
+/* Helper macros used for @ref NRFX_MAX_N. */
+#define _NRFX_MAX_P1(x) NRFX_MAX NRFX_EMPTY() ((x),
+#define _NRFX_MAX_P2(x) )
+
+/* Implementation details for NRFX_NUM_VA_ARGS_LESS_1 */
+#define _NRFX_NUM_VA_ARGS_LESS_1_IMPL(\
+ _ignored,\
+ _0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10,\
+ _11, _12, _13, _14, _15, _16, _17, _18, _19, _20,\
+ _21, _22, _23, _24, _25, _26, _27, _28, _29, _30,\
+ _31, _32, _33, _34, _35, _36, _37, _38, _39, _40,\
+ _41, _42, _43, _44, _45, _46, _47, _48, _49, _50,\
+ _51, _52, _53, _54, _55, _56, _57, _58, _59, _60,\
+ _61, _62, N, ...) N
+
+/* Intermediate macros needed for @ref NRFX_FEATURE_PRESENT. */
+#define NRFX_INSTANCE_FEATURE_PRESENT(i, _instance_name, _feature_name) \
+ NRFX_COND_CODE_1(NRFX_CONCAT_3(_instance_name, i, _feature_name), (1), ())
+
+#define _NRFX_FEATURE_PRESENT(_instance_name, _feature_name, _rpt) \
+ NRFX_LISTIFY(_rpt, NRFX_INSTANCE_FEATURE_PRESENT, (), _instance_name, _feature_name)
+
+
+/** Used by @ref NRFX_FOREACH_ENABLED. Execute provided macro if driver instance is enabled.
+ *
+ * @param[in] i Instance index.
+ * @param[in] off_code Code which is pasted when given driver instance is disabled.
+ * Must be given in parentheses.
+ * @param[in] periph_name Peripheral name, e.g. SPIM.
+ * @param[in] prefix Prefix added before instance index, e.g. some device has
+ * instances named like SPIM00. First 0 is passed here as prefix.
+ * @param[in] macro Macro which is executed.
+ * @param[in] ... Variable length arguments passed to the @p macro. Macro has following
+ * arguments: macro(periph_name, prefix, i, ...).
+ */
+#define _NRFX_EVAL_IF_ENABLED(i, off_code, periph_name, prefix, macro, ...) \
+ NRFX_COND_CODE_1(NRFX_CONCAT(NRFX_, periph_name, prefix, i, _ENABLED), \
+ (macro(periph_name, prefix, i, __VA_ARGS__)), \
+ off_code)
+
+/** Used by @ref NRFX_FOREACH_PRESENT. Execute provided macro if instance is present.
+ *
+ * Presence is determined by existing of token NRF_\ defined with wrapped
+ * in parenthesis value (see @ref NRFX_INSTANCE_PRESENT), where is the concatenation
+ * of @p periph_name, @p prefix and @p i.
+ *
+ * @param[in] i Instance index.
+ * @param[in] off_code Code which is pasted when given driver instance is disabled.
+ * Must be given in parentheses.
+ * @param[in] periph_name Peripheral name, e.g. SPIM.
+ * @param[in] prefix Prefix added before instance index, e.g. some device has
+ * instances named like SPIM00. First 0 is passed here as prefix.
+ * @param[in] macro Macro which is executed.
+ * @param[in] ... Variable length arguments passed to the @p macro. Macro has following
+ * arguments: macro(periph_name, prefix, i, ...).
+ */
+#define _NRFX_EVAL_IF_PRESENT(i, off_code, periph_name, prefix, macro, ...) \
+ NRFX_COND_CODE_1(NRFX_INSTANCE_PRESENT(NRFX_CONCAT(periph_name, prefix, i)), \
+ (macro(periph_name, prefix, i, __VA_ARGS__)), \
+ off_code)
+
+/* Macro used for enabled driver instances enum generation. */
+#define _NRFX_INST_ENUM(periph_name, prefix, i, _) \
+ NRFX_CONCAT(NRFX_, periph_name, prefix, i, _INST_IDX),
+
+/* Macro used for generation of irq handlers.
+ *
+ * Macro is using enum created by _NRFX_INSG_ENUM macro.
+ *
+ * @param[in] periph_name Peripheral name, e.g. SPIM.
+ * @param[in] prefix Prefix appended to the index.
+ * @param[in] i Index.
+ * @param[in] periph_name_small Peripheral name in small letters, e.g. spim.
+ */
+#define _NRFX_IRQ_HANDLER(periph_name, prefix, i, periph_name_small) \
+void NRFX_CONCAT(nrfx_, periph_name_small, _, prefix, i, _irq_handler)(void) \
+{ \
+ irq_handler(NRFX_CONCAT(NRF_, periph_name, prefix, i), \
+ &m_cb[NRFX_CONCAT(NRFX_, periph_name, prefix, i, _INST_IDX)]); \
+}
+
+/* Macro used for generation of irq handlers with addtional parameter.
+ *
+ * Additional parameter passed to the interrupt handler is a value returned by
+ * @p ext_macro. One of the use cases is a peripheral with variable number of
+ * channels (e.g. RTC or TIMER).
+ *
+ * Macro is using enum created by _NRFX_INSG_ENUM macro.
+ *
+ * @param[in] periph_name Peripheral name, e.g. SPIM.
+ * @param[in] prefix Prefix appended to the index.
+ * @param[in] i Index.
+ * @param[in] periph_name_small Peripheral name in small letters, e.g. spim.
+ * @param[in] ext_macro Macro called as third parameter of the handler.
+ */
+#define _NRFX_IRQ_HANDLER_EXT(periph_name, prefix, i, periph_name_small, ext_macro) \
+void NRFX_CONCAT(nrfx_, periph_name_small, _, prefix, i, _irq_handler)(void) \
+{ \
+ irq_handler(NRFX_CONCAT(NRF_, periph_name, prefix, i), \
+ &m_cb[NRFX_CONCAT(NRFX_, periph_name, prefix, i, _INST_IDX)], \
+ ext_macro(NRFX_CONCAT(prefix, i))); \
+}
+
+#define _NRFX_IRQ_HANDLER_LIST(periph_name, prefix, i, periph_name_small) \
+ NRFX_CONCAT(nrfx_, periph_name_small, _, prefix, i, _irq_handler),
+
+#define _NRFX_IRQ_HANDLER_DECLARE(periph_name, prefix, i, periph_name_small) \
+ void NRFX_CONCAT(nrfx_, periph_name_small, _, prefix, i, _irq_handler)(void);
+
+/* Macro for getting third argument from the set of input arguments. */
+#define __NRFX_GET_ARG3(arg1, arg2, arg3, ...) arg3
+#define _NRFX_GET_ARG3(...) __NRFX_GET_ARG3(__VA_ARGS__)
+
+/* Macro for triggering argument evaluation. */
+#define _NRFX_EVAL(...) __VA_ARGS__
+
+/* Macro used for a trick which detects if input argument is wrapped in parenthesis.
+ *
+ * Macro that has parenthesis will expand to additional comma (additional argument)
+ * and that is used to return 0 or 1.
+ */
+#define _NRFX_ARG_HAS_PARENTHESIS(...) ,
+
+#define _NRFX_ARG16(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, _15, ...) _15
+
+/* Returns 1 if there is a comma in the arguments (if there is more than one argument) */
+#define _NRFX_HAS_COMMA(...) \
+ _NRFX_ARG16(__VA_ARGS__, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0)
+
+/* Internal macro used for @ref NRFX_IS_EMPTY */
+#define _NRFX_IS_EMPTY2(_0, _1, _2, _3) \
+ _NRFX_HAS_COMMA(NRFX_CONCAT(_NRFX_IS_EMPTY_CASE_, _0, _1, _2, _3))
+
+#define _NRFX_IS_EMPTY_CASE_0001 ,
+
+/* Internal macro used for @ref NRFX_IS_EMPTY */
+#define _NRFX_IS_EMPTY(...) \
+ _NRFX_IS_EMPTY2( \
+ /* test if there is just one argument, eventually an empty one */ \
+ _NRFX_HAS_COMMA(__VA_ARGS__), \
+ /* test if _TRIGGER_PARENTHESIS_ together with the argument adds a comma */ \
+ _NRFX_HAS_COMMA(_NRFX_ARG_HAS_PARENTHESIS __VA_ARGS__), \
+ /* test if the argument together with a parenthesis adds a comma */ \
+ _NRFX_HAS_COMMA(__VA_ARGS__ (/*empty*/)), \
+ /* test if placing it between _TRIGGER_PARENTHESIS_ and the parenthesis adds a comma */ \
+ _NRFX_HAS_COMMA(_NRFX_ARG_HAS_PARENTHESIS __VA_ARGS__ (/*empty*/)) \
+ )
+
+/**
+ * @brief Macro for generating else if statement code blocks that assignes token \\\\
+ * to the variable \ if \ points to the instance NRF_\\\.
+ *
+ * @param[in] periph_name Peripheral name, e.g. SPIM.
+ * @param[in] prefix Prefix appended to the index.
+ * @param[in] i Index.
+ * @param[in] var Variable.
+ * @param[in] suffix Suffix following an instance name, e.g. _CH_NUM.
+ * @param[in] p_reg Specific peripheral instance register pointer.
+ */
+#define NRF_INTERNAL_ELSE_IF_EXTRACT_1(periph_name, prefix, i, var, suffix, p_reg) \
+ else if (p_reg == NRFX_CONCAT(NRF_, periph_name, prefix, i)) \
+ { \
+ var = NRFX_CONCAT(periph_name, prefix, i, suffix); \
+ }
+
+/**
+ * Macro used with @p NRFX_FOREACH_PRESENT for generating comma separated
+ * \\\_CH_NUM tokens.
+ */
+#define NRFX_INTERNAL_CHAN_NUM(periph_name, prefix, i, _) \
+ NRFX_CONCAT(periph_name, prefix, i, _CH_NUM),
+
+/* Internal macros for @ref NRFX_FOR_EACH_IDX_FIXED_ARG */
+#define _NRFX_FOR_EACH_IDX_FIXED_ARG_EXEC(idx, x, fixed_arg0, fixed_arg1) \
+ fixed_arg0(idx, x, fixed_arg1)
+
+#define _NRFX_FOR_EACH_IDX_FIXED_ARG(F, sep, fixed_arg, ...) \
+ _NRFX_FOR_EACH_ENGINE(_NRFX_FOR_EACH_IDX_FIXED_ARG_EXEC, sep, \
+ F, fixed_arg, __VA_ARGS__)
+
+/* Internal macros for @ref NRFX_FOR_EACH_FIXED_ARG */
+#define _NRFX_FOR_EACH_FIXED_ARG_EXEC(idx, x, fixed_arg0, fixed_arg1) \
+ fixed_arg0(x, fixed_arg1)
+
+#define _NRFX_FOR_EACH_FIXED_ARG(F, sep, fixed_arg, ...) \
+ _NRFX_FOR_EACH_ENGINE(_NRFX_FOR_EACH_FIXED_ARG_EXEC, sep, \
+ F, fixed_arg, __VA_ARGS__)
+
+/* Internal macros for @ref NRFX_FOR_EACH_IDX */
+#define _NRFX_FOR_EACH_IDX_EXEC(idx, x, fixed_arg0, fixed_arg1) \
+ fixed_arg0(idx, x)
+
+#define _NRFX_FOR_EACH_IDX(F, sep, ...) \
+ _NRFX_FOR_EACH_ENGINE(_NRFX_FOR_EACH_IDX_EXEC, sep, F, _, __VA_ARGS__)
+
+/* Internal macros for @ref NRFX_FOR_EACH */
+#define _NRFX_FOR_EACH(F, sep, ...) \
+ _NRFX_FOR_EACH_ENGINE(_NRFX_FOR_EACH_EXEC, sep, F, _, __VA_ARGS__)
+
+#define _NRFX_FOR_EACH_EXEC(idx, x, fixed_arg0, fixed_arg1) \
+ fixed_arg0(x)
+
+#define _NRFX_FOR_EACH_ENGINE(x, sep, fixed_arg0, fixed_arg1, ...) \
+ _NRFX_FOR_LOOP_GET_ARG(__VA_ARGS__, \
+ _NRFX_FOR_LOOP_64, \
+ _NRFX_FOR_LOOP_63, \
+ _NRFX_FOR_LOOP_62, \
+ _NRFX_FOR_LOOP_61, \
+ _NRFX_FOR_LOOP_60, \
+ _NRFX_FOR_LOOP_59, \
+ _NRFX_FOR_LOOP_58, \
+ _NRFX_FOR_LOOP_57, \
+ _NRFX_FOR_LOOP_56, \
+ _NRFX_FOR_LOOP_55, \
+ _NRFX_FOR_LOOP_54, \
+ _NRFX_FOR_LOOP_53, \
+ _NRFX_FOR_LOOP_52, \
+ _NRFX_FOR_LOOP_51, \
+ _NRFX_FOR_LOOP_50, \
+ _NRFX_FOR_LOOP_49, \
+ _NRFX_FOR_LOOP_48, \
+ _NRFX_FOR_LOOP_47, \
+ _NRFX_FOR_LOOP_46, \
+ _NRFX_FOR_LOOP_45, \
+ _NRFX_FOR_LOOP_44, \
+ _NRFX_FOR_LOOP_43, \
+ _NRFX_FOR_LOOP_42, \
+ _NRFX_FOR_LOOP_41, \
+ _NRFX_FOR_LOOP_40, \
+ _NRFX_FOR_LOOP_39, \
+ _NRFX_FOR_LOOP_38, \
+ _NRFX_FOR_LOOP_37, \
+ _NRFX_FOR_LOOP_36, \
+ _NRFX_FOR_LOOP_35, \
+ _NRFX_FOR_LOOP_34, \
+ _NRFX_FOR_LOOP_33, \
+ _NRFX_FOR_LOOP_32, \
+ _NRFX_FOR_LOOP_31, \
+ _NRFX_FOR_LOOP_30, \
+ _NRFX_FOR_LOOP_29, \
+ _NRFX_FOR_LOOP_28, \
+ _NRFX_FOR_LOOP_27, \
+ _NRFX_FOR_LOOP_26, \
+ _NRFX_FOR_LOOP_25, \
+ _NRFX_FOR_LOOP_24, \
+ _NRFX_FOR_LOOP_23, \
+ _NRFX_FOR_LOOP_22, \
+ _NRFX_FOR_LOOP_21, \
+ _NRFX_FOR_LOOP_20, \
+ _NRFX_FOR_LOOP_19, \
+ _NRFX_FOR_LOOP_18, \
+ _NRFX_FOR_LOOP_17, \
+ _NRFX_FOR_LOOP_16, \
+ _NRFX_FOR_LOOP_15, \
+ _NRFX_FOR_LOOP_14, \
+ _NRFX_FOR_LOOP_13, \
+ _NRFX_FOR_LOOP_12, \
+ _NRFX_FOR_LOOP_11, \
+ _NRFX_FOR_LOOP_10, \
+ _NRFX_FOR_LOOP_9, \
+ _NRFX_FOR_LOOP_8, \
+ _NRFX_FOR_LOOP_7, \
+ _NRFX_FOR_LOOP_6, \
+ _NRFX_FOR_LOOP_5, \
+ _NRFX_FOR_LOOP_4, \
+ _NRFX_FOR_LOOP_3, \
+ _NRFX_FOR_LOOP_2, \
+ _NRFX_FOR_LOOP_1, \
+ _NRFX_FOR_LOOP_0)(x, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__)
+
+/* Partial macros for @ref NRFX_CONCAT */
+#define _NRFX_CONCAT_0(arg, ...) arg
+
+#define _NRFX_CONCAT_1(arg, ...) NRFX_CONCAT_2(arg, _NRFX_CONCAT_0(__VA_ARGS__))
+
+#define _NRFX_CONCAT_2(arg, ...) NRFX_CONCAT_2(arg, _NRFX_CONCAT_1(__VA_ARGS__))
+
+#define _NRFX_CONCAT_3(arg, ...) NRFX_CONCAT_2(arg, _NRFX_CONCAT_2(__VA_ARGS__))
+
+#define _NRFX_CONCAT_4(arg, ...) NRFX_CONCAT_2(arg, _NRFX_CONCAT_3(__VA_ARGS__))
+
+#define _NRFX_CONCAT_5(arg, ...) NRFX_CONCAT_2(arg, _NRFX_CONCAT_4(__VA_ARGS__))
+
+#define _NRFX_CONCAT_6(arg, ...) NRFX_CONCAT_2(arg, _NRFX_CONCAT_5(__VA_ARGS__))
+
+#define _NRFX_CONCAT_7(arg, ...) NRFX_CONCAT_2(arg, _NRFX_CONCAT_6(__VA_ARGS__))
+
+/* Set of UTIL_LISTIFY particles */
+#define _NRFX_LISTIFY_0(F, sep, ...)
+
+#define _NRFX_LISTIFY_1(F, sep, ...) \
+ F(0, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_2(F, sep, ...) \
+ _NRFX_LISTIFY_1(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(1, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_3(F, sep, ...) \
+ _NRFX_LISTIFY_2(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(2, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_4(F, sep, ...) \
+ _NRFX_LISTIFY_3(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(3, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_5(F, sep, ...) \
+ _NRFX_LISTIFY_4(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(4, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_6(F, sep, ...) \
+ _NRFX_LISTIFY_5(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(5, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_7(F, sep, ...) \
+ _NRFX_LISTIFY_6(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(6, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_8(F, sep, ...) \
+ _NRFX_LISTIFY_7(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(7, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_9(F, sep, ...) \
+ _NRFX_LISTIFY_8(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(8, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_10(F, sep, ...) \
+ _NRFX_LISTIFY_9(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(9, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_11(F, sep, ...) \
+ _NRFX_LISTIFY_10(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(10, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_12(F, sep, ...) \
+ _NRFX_LISTIFY_11(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(11, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_13(F, sep, ...) \
+ _NRFX_LISTIFY_12(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(12, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_14(F, sep, ...) \
+ _NRFX_LISTIFY_13(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(13, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_15(F, sep, ...) \
+ _NRFX_LISTIFY_14(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(14, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_16(F, sep, ...) \
+ _NRFX_LISTIFY_15(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(15, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_17(F, sep, ...) \
+ _NRFX_LISTIFY_16(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(16, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_18(F, sep, ...) \
+ _NRFX_LISTIFY_17(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(17, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_19(F, sep, ...) \
+ _NRFX_LISTIFY_18(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(18, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_20(F, sep, ...) \
+ _NRFX_LISTIFY_19(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(19, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_21(F, sep, ...) \
+ _NRFX_LISTIFY_20(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(20, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_22(F, sep, ...) \
+ _NRFX_LISTIFY_21(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(21, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_23(F, sep, ...) \
+ _NRFX_LISTIFY_22(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(22, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_24(F, sep, ...) \
+ _NRFX_LISTIFY_23(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(23, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_25(F, sep, ...) \
+ _NRFX_LISTIFY_24(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(24, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_26(F, sep, ...) \
+ _NRFX_LISTIFY_25(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(25, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_27(F, sep, ...) \
+ _NRFX_LISTIFY_26(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(26, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_28(F, sep, ...) \
+ _NRFX_LISTIFY_27(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(27, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_29(F, sep, ...) \
+ _NRFX_LISTIFY_28(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(28, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_30(F, sep, ...) \
+ _NRFX_LISTIFY_29(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(29, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_31(F, sep, ...) \
+ _NRFX_LISTIFY_30(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(30, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_32(F, sep, ...) \
+ _NRFX_LISTIFY_31(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(31, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_33(F, sep, ...) \
+ _NRFX_LISTIFY_32(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(32, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_34(F, sep, ...) \
+ _NRFX_LISTIFY_33(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(33, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_35(F, sep, ...) \
+ _NRFX_LISTIFY_34(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(34, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_36(F, sep, ...) \
+ _NRFX_LISTIFY_35(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(35, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_37(F, sep, ...) \
+ _NRFX_LISTIFY_36(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(36, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_38(F, sep, ...) \
+ _NRFX_LISTIFY_37(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(37, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_39(F, sep, ...) \
+ _NRFX_LISTIFY_38(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(38, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_40(F, sep, ...) \
+ _NRFX_LISTIFY_39(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(39, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_41(F, sep, ...) \
+ _NRFX_LISTIFY_40(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(40, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_42(F, sep, ...) \
+ _NRFX_LISTIFY_41(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(41, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_43(F, sep, ...) \
+ _NRFX_LISTIFY_42(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(42, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_44(F, sep, ...) \
+ _NRFX_LISTIFY_43(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(43, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_45(F, sep, ...) \
+ _NRFX_LISTIFY_44(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(44, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_46(F, sep, ...) \
+ _NRFX_LISTIFY_45(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(45, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_47(F, sep, ...) \
+ _NRFX_LISTIFY_46(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(46, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_48(F, sep, ...) \
+ _NRFX_LISTIFY_47(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(47, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_49(F, sep, ...) \
+ _NRFX_LISTIFY_48(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(48, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_50(F, sep, ...) \
+ _NRFX_LISTIFY_49(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(49, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_51(F, sep, ...) \
+ _NRFX_LISTIFY_50(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(50, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_52(F, sep, ...) \
+ _NRFX_LISTIFY_51(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(51, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_53(F, sep, ...) \
+ _NRFX_LISTIFY_52(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(52, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_54(F, sep, ...) \
+ _NRFX_LISTIFY_53(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(53, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_55(F, sep, ...) \
+ _NRFX_LISTIFY_54(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(54, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_56(F, sep, ...) \
+ _NRFX_LISTIFY_55(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(55, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_57(F, sep, ...) \
+ _NRFX_LISTIFY_56(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(56, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_58(F, sep, ...) \
+ _NRFX_LISTIFY_57(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(57, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_59(F, sep, ...) \
+ _NRFX_LISTIFY_58(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(58, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_60(F, sep, ...) \
+ _NRFX_LISTIFY_59(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(59, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_61(F, sep, ...) \
+ _NRFX_LISTIFY_60(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(60, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_62(F, sep, ...) \
+ _NRFX_LISTIFY_61(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(61, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_63(F, sep, ...) \
+ _NRFX_LISTIFY_62(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(62, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_64(F, sep, ...) \
+ _NRFX_LISTIFY_63(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(63, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_65(F, sep, ...) \
+ _NRFX_LISTIFY_64(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(64, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_66(F, sep, ...) \
+ _NRFX_LISTIFY_65(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(65, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_67(F, sep, ...) \
+ _NRFX_LISTIFY_66(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(66, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_68(F, sep, ...) \
+ _NRFX_LISTIFY_67(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(67, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_69(F, sep, ...) \
+ _NRFX_LISTIFY_68(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(68, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_70(F, sep, ...) \
+ _NRFX_LISTIFY_69(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(69, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_71(F, sep, ...) \
+ _NRFX_LISTIFY_70(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(70, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_72(F, sep, ...) \
+ _NRFX_LISTIFY_71(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(71, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_73(F, sep, ...) \
+ _NRFX_LISTIFY_72(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(72, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_74(F, sep, ...) \
+ _NRFX_LISTIFY_73(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(73, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_75(F, sep, ...) \
+ _NRFX_LISTIFY_74(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(74, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_76(F, sep, ...) \
+ _NRFX_LISTIFY_75(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(75, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_77(F, sep, ...) \
+ _NRFX_LISTIFY_76(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(76, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_78(F, sep, ...) \
+ _NRFX_LISTIFY_77(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(77, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_79(F, sep, ...) \
+ _NRFX_LISTIFY_78(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(78, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_80(F, sep, ...) \
+ _NRFX_LISTIFY_79(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(79, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_81(F, sep, ...) \
+ _NRFX_LISTIFY_80(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(80, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_82(F, sep, ...) \
+ _NRFX_LISTIFY_81(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(81, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_83(F, sep, ...) \
+ _NRFX_LISTIFY_82(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(82, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_84(F, sep, ...) \
+ _NRFX_LISTIFY_83(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(83, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_85(F, sep, ...) \
+ _NRFX_LISTIFY_84(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(84, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_86(F, sep, ...) \
+ _NRFX_LISTIFY_85(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(85, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_87(F, sep, ...) \
+ _NRFX_LISTIFY_86(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(86, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_88(F, sep, ...) \
+ _NRFX_LISTIFY_87(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(87, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_89(F, sep, ...) \
+ _NRFX_LISTIFY_88(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(88, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_90(F, sep, ...) \
+ _NRFX_LISTIFY_89(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(89, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_91(F, sep, ...) \
+ _NRFX_LISTIFY_90(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(90, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_92(F, sep, ...) \
+ _NRFX_LISTIFY_91(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(91, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_93(F, sep, ...) \
+ _NRFX_LISTIFY_92(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(92, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_94(F, sep, ...) \
+ _NRFX_LISTIFY_93(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(93, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_95(F, sep, ...) \
+ _NRFX_LISTIFY_94(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(94, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_96(F, sep, ...) \
+ _NRFX_LISTIFY_95(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(95, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_97(F, sep, ...) \
+ _NRFX_LISTIFY_96(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(96, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_98(F, sep, ...) \
+ _NRFX_LISTIFY_97(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(97, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_99(F, sep, ...) \
+ _NRFX_LISTIFY_98(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(98, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_100(F, sep, ...) \
+ _NRFX_LISTIFY_99(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(99, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_101(F, sep, ...) \
+ _NRFX_LISTIFY_100(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(100, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_102(F, sep, ...) \
+ _NRFX_LISTIFY_101(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(101, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_103(F, sep, ...) \
+ _NRFX_LISTIFY_102(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(102, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_104(F, sep, ...) \
+ _NRFX_LISTIFY_103(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(103, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_105(F, sep, ...) \
+ _NRFX_LISTIFY_104(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(104, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_106(F, sep, ...) \
+ _NRFX_LISTIFY_105(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(105, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_107(F, sep, ...) \
+ _NRFX_LISTIFY_106(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(106, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_108(F, sep, ...) \
+ _NRFX_LISTIFY_107(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(107, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_109(F, sep, ...) \
+ _NRFX_LISTIFY_108(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(108, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_110(F, sep, ...) \
+ _NRFX_LISTIFY_109(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(109, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_111(F, sep, ...) \
+ _NRFX_LISTIFY_110(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(110, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_112(F, sep, ...) \
+ _NRFX_LISTIFY_111(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(111, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_113(F, sep, ...) \
+ _NRFX_LISTIFY_112(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(112, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_114(F, sep, ...) \
+ _NRFX_LISTIFY_113(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(113, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_115(F, sep, ...) \
+ _NRFX_LISTIFY_114(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(114, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_116(F, sep, ...) \
+ _NRFX_LISTIFY_115(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(115, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_117(F, sep, ...) \
+ _NRFX_LISTIFY_116(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(116, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_118(F, sep, ...) \
+ _NRFX_LISTIFY_117(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(117, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_119(F, sep, ...) \
+ _NRFX_LISTIFY_118(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(118, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_120(F, sep, ...) \
+ _NRFX_LISTIFY_119(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(119, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_121(F, sep, ...) \
+ _NRFX_LISTIFY_120(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(120, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_122(F, sep, ...) \
+ _NRFX_LISTIFY_121(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(121, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_123(F, sep, ...) \
+ _NRFX_LISTIFY_122(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(122, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_124(F, sep, ...) \
+ _NRFX_LISTIFY_123(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(123, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_125(F, sep, ...) \
+ _NRFX_LISTIFY_124(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(124, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_126(F, sep, ...) \
+ _NRFX_LISTIFY_125(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(125, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_127(F, sep, ...) \
+ _NRFX_LISTIFY_126(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(126, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_128(F, sep, ...) \
+ _NRFX_LISTIFY_127(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(127, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_129(F, sep, ...) \
+ _NRFX_LISTIFY_128(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(128, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_130(F, sep, ...) \
+ _NRFX_LISTIFY_129(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(129, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_131(F, sep, ...) \
+ _NRFX_LISTIFY_130(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(130, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_132(F, sep, ...) \
+ _NRFX_LISTIFY_131(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(131, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_133(F, sep, ...) \
+ _NRFX_LISTIFY_132(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(132, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_134(F, sep, ...) \
+ _NRFX_LISTIFY_133(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(133, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_135(F, sep, ...) \
+ _NRFX_LISTIFY_134(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(134, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_136(F, sep, ...) \
+ _NRFX_LISTIFY_135(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(135, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_137(F, sep, ...) \
+ _NRFX_LISTIFY_136(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(136, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_138(F, sep, ...) \
+ _NRFX_LISTIFY_137(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(137, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_139(F, sep, ...) \
+ _NRFX_LISTIFY_138(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(138, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_140(F, sep, ...) \
+ _NRFX_LISTIFY_139(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(139, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_141(F, sep, ...) \
+ _NRFX_LISTIFY_140(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(140, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_142(F, sep, ...) \
+ _NRFX_LISTIFY_141(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(141, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_143(F, sep, ...) \
+ _NRFX_LISTIFY_142(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(142, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_144(F, sep, ...) \
+ _NRFX_LISTIFY_143(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(143, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_145(F, sep, ...) \
+ _NRFX_LISTIFY_144(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(144, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_146(F, sep, ...) \
+ _NRFX_LISTIFY_145(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(145, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_147(F, sep, ...) \
+ _NRFX_LISTIFY_146(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(146, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_148(F, sep, ...) \
+ _NRFX_LISTIFY_147(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(147, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_149(F, sep, ...) \
+ _NRFX_LISTIFY_148(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(148, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_150(F, sep, ...) \
+ _NRFX_LISTIFY_149(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(149, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_151(F, sep, ...) \
+ _NRFX_LISTIFY_150(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(150, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_152(F, sep, ...) \
+ _NRFX_LISTIFY_151(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(151, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_153(F, sep, ...) \
+ _NRFX_LISTIFY_152(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(152, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_154(F, sep, ...) \
+ _NRFX_LISTIFY_153(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(153, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_155(F, sep, ...) \
+ _NRFX_LISTIFY_154(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(154, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_156(F, sep, ...) \
+ _NRFX_LISTIFY_155(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(155, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_157(F, sep, ...) \
+ _NRFX_LISTIFY_156(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(156, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_158(F, sep, ...) \
+ _NRFX_LISTIFY_157(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(157, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_159(F, sep, ...) \
+ _NRFX_LISTIFY_158(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(158, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_160(F, sep, ...) \
+ _NRFX_LISTIFY_159(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(159, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_161(F, sep, ...) \
+ _NRFX_LISTIFY_160(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(160, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_162(F, sep, ...) \
+ _NRFX_LISTIFY_161(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(161, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_163(F, sep, ...) \
+ _NRFX_LISTIFY_162(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(162, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_164(F, sep, ...) \
+ _NRFX_LISTIFY_163(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(163, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_165(F, sep, ...) \
+ _NRFX_LISTIFY_164(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(164, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_166(F, sep, ...) \
+ _NRFX_LISTIFY_165(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(165, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_167(F, sep, ...) \
+ _NRFX_LISTIFY_166(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(166, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_168(F, sep, ...) \
+ _NRFX_LISTIFY_167(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(167, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_169(F, sep, ...) \
+ _NRFX_LISTIFY_168(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(168, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_170(F, sep, ...) \
+ _NRFX_LISTIFY_169(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(169, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_171(F, sep, ...) \
+ _NRFX_LISTIFY_170(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(170, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_172(F, sep, ...) \
+ _NRFX_LISTIFY_171(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(171, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_173(F, sep, ...) \
+ _NRFX_LISTIFY_172(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(172, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_174(F, sep, ...) \
+ _NRFX_LISTIFY_173(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(173, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_175(F, sep, ...) \
+ _NRFX_LISTIFY_174(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(174, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_176(F, sep, ...) \
+ _NRFX_LISTIFY_175(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(175, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_177(F, sep, ...) \
+ _NRFX_LISTIFY_176(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(176, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_178(F, sep, ...) \
+ _NRFX_LISTIFY_177(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(177, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_179(F, sep, ...) \
+ _NRFX_LISTIFY_178(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(178, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_180(F, sep, ...) \
+ _NRFX_LISTIFY_179(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(179, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_181(F, sep, ...) \
+ _NRFX_LISTIFY_180(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(180, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_182(F, sep, ...) \
+ _NRFX_LISTIFY_181(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(181, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_183(F, sep, ...) \
+ _NRFX_LISTIFY_182(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(182, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_184(F, sep, ...) \
+ _NRFX_LISTIFY_183(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(183, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_185(F, sep, ...) \
+ _NRFX_LISTIFY_184(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(184, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_186(F, sep, ...) \
+ _NRFX_LISTIFY_185(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(185, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_187(F, sep, ...) \
+ _NRFX_LISTIFY_186(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(186, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_188(F, sep, ...) \
+ _NRFX_LISTIFY_187(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(187, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_189(F, sep, ...) \
+ _NRFX_LISTIFY_188(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(188, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_190(F, sep, ...) \
+ _NRFX_LISTIFY_189(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(189, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_191(F, sep, ...) \
+ _NRFX_LISTIFY_190(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(190, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_192(F, sep, ...) \
+ _NRFX_LISTIFY_191(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(191, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_193(F, sep, ...) \
+ _NRFX_LISTIFY_192(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(192, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_194(F, sep, ...) \
+ _NRFX_LISTIFY_193(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(193, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_195(F, sep, ...) \
+ _NRFX_LISTIFY_194(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(194, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_196(F, sep, ...) \
+ _NRFX_LISTIFY_195(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(195, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_197(F, sep, ...) \
+ _NRFX_LISTIFY_196(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(196, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_198(F, sep, ...) \
+ _NRFX_LISTIFY_197(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(197, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_199(F, sep, ...) \
+ _NRFX_LISTIFY_198(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(198, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_200(F, sep, ...) \
+ _NRFX_LISTIFY_199(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(199, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_201(F, sep, ...) \
+ _NRFX_LISTIFY_200(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(200, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_202(F, sep, ...) \
+ _NRFX_LISTIFY_201(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(201, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_203(F, sep, ...) \
+ _NRFX_LISTIFY_202(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(202, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_204(F, sep, ...) \
+ _NRFX_LISTIFY_203(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(203, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_205(F, sep, ...) \
+ _NRFX_LISTIFY_204(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(204, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_206(F, sep, ...) \
+ _NRFX_LISTIFY_205(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(205, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_207(F, sep, ...) \
+ _NRFX_LISTIFY_206(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(206, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_208(F, sep, ...) \
+ _NRFX_LISTIFY_207(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(207, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_209(F, sep, ...) \
+ _NRFX_LISTIFY_208(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(208, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_210(F, sep, ...) \
+ _NRFX_LISTIFY_209(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(209, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_211(F, sep, ...) \
+ _NRFX_LISTIFY_210(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(210, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_212(F, sep, ...) \
+ _NRFX_LISTIFY_211(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(211, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_213(F, sep, ...) \
+ _NRFX_LISTIFY_212(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(212, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_214(F, sep, ...) \
+ _NRFX_LISTIFY_213(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(213, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_215(F, sep, ...) \
+ _NRFX_LISTIFY_214(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(214, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_216(F, sep, ...) \
+ _NRFX_LISTIFY_215(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(215, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_217(F, sep, ...) \
+ _NRFX_LISTIFY_216(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(216, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_218(F, sep, ...) \
+ _NRFX_LISTIFY_217(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(217, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_219(F, sep, ...) \
+ _NRFX_LISTIFY_218(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(218, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_220(F, sep, ...) \
+ _NRFX_LISTIFY_219(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(219, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_221(F, sep, ...) \
+ _NRFX_LISTIFY_220(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(220, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_222(F, sep, ...) \
+ _NRFX_LISTIFY_221(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(221, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_223(F, sep, ...) \
+ _NRFX_LISTIFY_222(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(222, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_224(F, sep, ...) \
+ _NRFX_LISTIFY_223(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(223, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_225(F, sep, ...) \
+ _NRFX_LISTIFY_224(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(224, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_226(F, sep, ...) \
+ _NRFX_LISTIFY_225(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(225, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_227(F, sep, ...) \
+ _NRFX_LISTIFY_226(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(226, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_228(F, sep, ...) \
+ _NRFX_LISTIFY_227(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(227, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_229(F, sep, ...) \
+ _NRFX_LISTIFY_228(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(228, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_230(F, sep, ...) \
+ _NRFX_LISTIFY_229(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(229, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_231(F, sep, ...) \
+ _NRFX_LISTIFY_230(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(230, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_232(F, sep, ...) \
+ _NRFX_LISTIFY_231(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(231, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_233(F, sep, ...) \
+ _NRFX_LISTIFY_232(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(232, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_234(F, sep, ...) \
+ _NRFX_LISTIFY_233(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(233, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_235(F, sep, ...) \
+ _NRFX_LISTIFY_234(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(234, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_236(F, sep, ...) \
+ _NRFX_LISTIFY_235(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(235, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_237(F, sep, ...) \
+ _NRFX_LISTIFY_236(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(236, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_238(F, sep, ...) \
+ _NRFX_LISTIFY_237(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(237, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_239(F, sep, ...) \
+ _NRFX_LISTIFY_238(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(238, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_240(F, sep, ...) \
+ _NRFX_LISTIFY_239(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(239, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_241(F, sep, ...) \
+ _NRFX_LISTIFY_240(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(240, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_242(F, sep, ...) \
+ _NRFX_LISTIFY_241(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(241, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_243(F, sep, ...) \
+ _NRFX_LISTIFY_242(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(242, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_244(F, sep, ...) \
+ _NRFX_LISTIFY_243(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(243, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_245(F, sep, ...) \
+ _NRFX_LISTIFY_244(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(244, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_246(F, sep, ...) \
+ _NRFX_LISTIFY_245(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(245, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_247(F, sep, ...) \
+ _NRFX_LISTIFY_246(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(246, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_248(F, sep, ...) \
+ _NRFX_LISTIFY_247(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(247, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_249(F, sep, ...) \
+ _NRFX_LISTIFY_248(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(248, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_250(F, sep, ...) \
+ _NRFX_LISTIFY_249(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(249, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_251(F, sep, ...) \
+ _NRFX_LISTIFY_250(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(250, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_252(F, sep, ...) \
+ _NRFX_LISTIFY_251(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(251, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_253(F, sep, ...) \
+ _NRFX_LISTIFY_252(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(252, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_254(F, sep, ...) \
+ _NRFX_LISTIFY_253(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(253, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_255(F, sep, ...) \
+ _NRFX_LISTIFY_254(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(254, __VA_ARGS__)
+
+#define _NRFX_LISTIFY_256(F, sep, ...) \
+ _NRFX_LISTIFY_255(F, sep, __VA_ARGS__) NRFX_DEBRACKET sep \
+ F(255, __VA_ARGS__)
+
+#define _NRFX_FOR_LOOP_GET_ARG(_1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, \
+ _12, _13, _14, _15, _16, _17, _18, _19, _20, \
+ _21, _22, _23, _24, _25, _26, _27, _28, _29, \
+ _30, _31, _32, _33, _34, _35, _36, _37, _38, \
+ _39, _40, _41, _42, _43, _44, _45, _46, _47, \
+ _48, _49, _50, _51, _52, _53, _54, _55, _56, \
+ _57, _58, _59, _60, _61, _62, _63, _64, N, ...) N
+
+#define _NRFX_FOR_LOOP_0(call, sep, fixed_arg0, fixed_arg1, ...)
+
+#define _NRFX_FOR_LOOP_1(call, sep, fixed_arg0, fixed_arg1, x) \
+ call(0, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_2(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_1(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(1, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_3(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_2(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(2, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_4(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_3(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(3, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_5(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_4(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(4, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_6(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_5(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(5, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_7(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_6(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(6, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_8(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_7(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(7, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_9(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_8(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(8, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_10(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_9(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(9, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_11(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_10(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(10, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_12(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_11(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(11, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_13(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_12(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(12, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_14(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_13(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(13, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_15(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_14(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(14, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_16(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_15(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(15, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_17(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_16(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(16, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_18(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_17(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(17, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_19(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_18(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(18, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_20(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_19(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(19, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_21(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_20(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(20, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_22(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_21(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(21, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_23(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_22(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(22, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_24(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_23(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(23, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_25(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_24(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(24, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_26(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_25(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(25, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_27(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_26(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(26, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_28(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_27(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(27, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_29(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_28(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(28, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_30(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_29(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(29, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_31(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_30(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(30, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_32(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_31(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(31, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_33(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_32(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(32, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_34(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_33(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(33, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_35(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_34(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(34, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_36(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_35(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(35, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_37(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_36(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(36, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_38(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_37(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(37, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_39(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_38(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(38, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_40(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_39(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(39, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_41(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_40(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(40, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_42(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_41(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(41, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_43(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_42(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(42, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_44(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_43(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(43, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_45(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_44(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(44, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_46(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_45(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(45, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_47(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_46(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(46, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_48(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_47(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(47, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_49(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_48(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(48, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_50(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_49(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(49, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_51(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_50(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(50, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_52(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_51(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(51, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_53(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_52(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(52, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_54(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_53(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(53, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_55(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_54(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(54, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_56(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_55(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(55, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_57(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_56(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(56, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_58(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_57(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(57, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_59(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_58(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(58, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_60(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_59(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(59, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_61(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_60(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(60, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_62(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_61(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(61, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_63(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_62(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(62, x, fixed_arg0, fixed_arg1)
+
+#define _NRFX_FOR_LOOP_64(call, sep, fixed_arg0, fixed_arg1, x, ...) \
+ _NRFX_FOR_LOOP_63(call, sep, fixed_arg0, fixed_arg1, ##__VA_ARGS__) \
+ NRFX_DEBRACKET sep \
+ call(63, x, fixed_arg0, fixed_arg1)
+
+#endif /* NRFX_UTILS_INTERNAL_H__ */
diff --git a/mcu/nrf/common/vendor/get_vendor_files.py b/mcu/nrf/common/vendor/get_vendor_files.py
index bc6ae7cf..8e049894 100644
--- a/mcu/nrf/common/vendor/get_vendor_files.py
+++ b/mcu/nrf/common/vendor/get_vendor_files.py
@@ -1,8 +1,9 @@
#!/usr/bin/env python3
# -*- coding: utf-8 -*-
+import os
import wget
-url='https://raw.githubusercontent.com/NordicSemiconductor/nrfx/v2.5.0/'
+url='https://raw.githubusercontent.com/NordicSemiconductor/nrfx/v3.0.0/'
files = [
{"input": "nrfx.h", "output": "."},
@@ -13,8 +14,12 @@
{"input": "hal/nrf_uarte.h", "output": "hal"},
{"input": "hal/nrf_common.h", "output": "hal"},
{"input": "hal/nrf_timer.h", "output": "hal"},
+ {"input": "haly/nrfy_common.h", "output": "haly"},
{"input": "drivers/nrfx_common.h", "output": "drivers"},
{"input": "drivers/nrfx_errors.h", "output": "drivers"},
+ {"input": "drivers/nrfx_utils.h", "output": "drivers"},
+ {"input": "drivers/nrfx_utils_internal.h", "output": "drivers"},
+ {"input": "drivers/nrfx_ext.h", "output": "drivers"},
{"input": "mdk/nrf52.h", "output": 'mdk'},
{"input": "mdk/nrf52_bitfields.h", "output": 'mdk'},
{"input": "mdk/nrf51_to_nrf52.h", "output": 'mdk'},
@@ -33,17 +38,23 @@
{"input": "mdk/nrf52833_peripherals.h", "output": 'mdk'},
{"input": "mdk/nrf52840_peripherals.h", "output": 'mdk'},
{"input": "mdk/nrf9160_bitfields.h", "output": "mdk"},
+ {"input": "mdk/nrf9120_bitfields.h", "output": "mdk"},
{"input": "mdk/nrf9160.h", "output": "mdk"},
+ {"input": "mdk/nrf9120.h", "output": "mdk"},
{"input": "mdk/system_nrf9160.h", "output": "mdk"},
+ {"input": "mdk/system_nrf9120.h", "output": "mdk"},
{"input": "mdk/system_nrf.h", "output": "mdk"},
{"input": "mdk/compiler_abstraction.h", "output": "mdk"},
{"input": "mdk/nrf9160_peripherals.h", "output": "mdk"},
+ {"input": "mdk/nrf9120_peripherals.h", "output": "mdk"},
{"input": "mdk/nrf9160_name_change.h", "output": "mdk"},
+ {"input": "mdk/nrf91_name_change.h", "output": "mdk"},
{"input": "templates/nrfx_config.h", "output": "templates"},
+ {"input": "templates/nrfx_config_common.h", "output": "templates"},
{"input": "templates/nrfx_config_nrf52832.h", "output": "templates"},
{"input": "templates/nrfx_config_nrf52833.h", "output": 'templates'},
{"input": "templates/nrfx_config_nrf52840.h", "output": "templates"},
- {"input": "templates/nrfx_config_nrf9160.h", "output": "templates"},
+ {"input": "templates/nrfx_config_nrf91.h", "output": "templates"},
{"input": "templates/nrfx_glue.h", "output": "templates"},
]
@@ -51,6 +62,9 @@
src = url+file['input']
dest = file['output']
print('\nLoading:{}, to location:{}\n'.format(src, dest))
+ dst_filename = dest+'/'+os.path.basename(src)
+ if os.path.exists(dst_filename):
+ os.remove(dst_filename)
filename = wget.download (url=src, out=dest)
print ("\n**ALL DONE**\n")
diff --git a/mcu/nrf/common/vendor/get_vendor_files.sh b/mcu/nrf/common/vendor/get_vendor_files.sh
old mode 100644
new mode 100755
diff --git a/mcu/nrf/common/vendor/hal/nrf_common.h b/mcu/nrf/common/vendor/hal/nrf_common.h
index 7f0dd3d7..b3eecf58 100644
--- a/mcu/nrf/common/vendor/hal/nrf_common.h
+++ b/mcu/nrf/common/vendor/hal/nrf_common.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020 - 2021, Nordic Semiconductor ASA
+ * Copyright (c) 2020 - 2023, Nordic Semiconductor ASA
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -42,6 +42,70 @@ extern "C" {
#define NRFX_EVENT_READBACK_ENABLED 1
#endif
+#ifndef NRFX_CONFIG_API_VER_MAJOR
+#define NRFX_CONFIG_API_VER_MAJOR 3
+#endif
+
+#ifndef NRFX_CONFIG_API_VER_MINOR
+#define NRFX_CONFIG_API_VER_MINOR 0
+#endif
+
+#ifndef NRFX_CONFIG_API_VER_MICRO
+#define NRFX_CONFIG_API_VER_MICRO 0
+#endif
+
+#if defined(ISA_RISCV)
+#define RISCV_FENCE(p, s) __asm__ __volatile__ ("fence " #p "," #s : : : "memory")
+#endif
+
+#ifndef NRF_SUBSCRIBE_PUBLISH_ENABLE
+#define NRF_SUBSCRIBE_PUBLISH_ENABLE (0x01UL << 31UL)
+#endif
+
+#if defined(NRFX_CLZ)
+#define NRF_CLZ(value) NRFX_CLZ(value)
+#elif defined(ISA_ARM)
+#define NRF_CLZ(value) __CLZ(value)
+#else
+#define NRF_CLZ(value) __builtin_clz(value)
+#endif
+
+#if defined(NRFX_CTZ)
+#define NRF_CTZ(value) NRFX_CTZ(value)
+#elif defined(ISA_ARM)
+#define NRF_CTZ(value) __CLZ(__RBIT(value))
+#else
+#define NRF_CTZ(value) __builtin_ctz(value)
+#endif
+
+/** @brief Macro for extracting relative pin number from the absolute pin number. */
+#define NRF_PIN_NUMBER_TO_PIN(pin) ((pin) & 0x1F)
+
+/** @brief Macro for extracting port number from the absolute pin number. */
+#define NRF_PIN_NUMBER_TO_PORT(pin) ((pin) >> 5)
+
+/** @brief Macro for extracting absolute pin number from the relative pin and port numbers. */
+#define NRF_PIN_PORT_TO_PIN_NUMBER(pin, port) (((pin) & 0x1F) | ((port) << 5))
+
+/**
+ * @brief Function for checking if an object is accesible by EasyDMA of given peripheral instance.
+ *
+ * Peripherals that use EasyDMA require buffers to be placed in certain memory regions.
+ *
+ * @param[in] p_reg Peripheral base pointer.
+ * @param[in] p_object Pointer to an object whose location is to be checked.
+ *
+ * @retval true The pointed object is located in the memory region accessible by EasyDMA.
+ * @retval false The pointed object is not located in the memory region accessible by EasyDMA.
+ */
+NRF_STATIC_INLINE bool nrf_dma_accessible_check(void const * p_reg, void const * p_object);
+
+NRF_STATIC_INLINE void nrf_barrier_w(void);
+
+NRF_STATIC_INLINE void nrf_barrier_r(void);
+
+NRF_STATIC_INLINE void nrf_barrier_rw(void);
+
#ifndef NRF_DECLARE_ONLY
NRF_STATIC_INLINE void nrf_event_readback(void * p_event_reg)
@@ -53,6 +117,93 @@ NRF_STATIC_INLINE void nrf_event_readback(void * p_event_reg)
#endif
}
+NRF_STATIC_INLINE void nrf_barrier_w(void)
+{
+#if defined(ISA_RISCV)
+ RISCV_FENCE(ow, ow);
+#endif
+}
+
+NRF_STATIC_INLINE void nrf_barrier_r(void)
+{
+#if defined(ISA_RISCV)
+ RISCV_FENCE(ir, ir);
+#endif
+}
+
+NRF_STATIC_INLINE void nrf_barrier_rw(void)
+{
+#if defined(ISA_RISCV)
+ RISCV_FENCE(iorw, iorw);
+#endif
+}
+
+#if defined(ADDRESS_DOMAIN_Msk)
+NRF_STATIC_INLINE uint8_t nrf_address_domain_get(uint32_t addr)
+{
+ return (uint8_t)((addr & ADDRESS_DOMAIN_Msk) >> ADDRESS_DOMAIN_Pos);
+}
+#endif
+
+#if defined(ADDRESS_REGION_Msk)
+NRF_STATIC_INLINE nrf_region_t nrf_address_region_get(uint32_t addr)
+{
+ return (nrf_region_t)((addr & ADDRESS_REGION_Msk) >> ADDRESS_REGION_Pos);
+}
+#endif
+
+#if defined(ADDRESS_SECURITY_Msk)
+NRF_STATIC_INLINE bool nrf_address_security_get(uint32_t addr)
+{
+ return ((addr & ADDRESS_SECURITY_Msk) >> ADDRESS_SECURITY_Pos);
+}
+#endif
+
+#if defined(ADDRESS_BUS_Msk)
+NRF_STATIC_INLINE uint8_t nrf_address_bus_get(uint32_t addr, size_t size)
+{
+ return (uint8_t)((addr & ADDRESS_BUS_Msk & ~(size - 1)) >> ADDRESS_BUS_Pos);
+}
+#endif
+
+#if defined(ADDRESS_BRIDGE_GROUP_Msk)
+NRF_STATIC_INLINE uint8_t nrf_address_bridge_group_get(uint32_t addr)
+{
+ return (uint8_t)((addr & ADDRESS_BRIDGE_GROUP_Msk) >> ADDRESS_BRIDGE_GROUP_Pos);
+}
+#endif
+
+#if defined(ADDRESS_DOMAIN_SPEED_Msk)
+NRF_STATIC_INLINE nrf_domain_speed_t nrf_address_domain_speed_get(uint32_t addr)
+{
+ return (nrf_domain_speed_t)((addr & ADDRESS_DOMAIN_SPEED_Msk) >> ADDRESS_DOMAIN_SPEED_Pos);
+}
+#endif
+
+#if defined(ADDRESS_SLAVE_Msk)
+NRF_STATIC_INLINE uint8_t nrf_address_slave_get(uint32_t addr)
+{
+ return (uint8_t)((addr & ADDRESS_SLAVE_Msk) >> ADDRESS_SLAVE_Pos);
+}
+#endif
+
+#if defined(ADDRESS_PERIPHID_Msk)
+NRF_STATIC_INLINE uint16_t nrf_address_periphid_get(uint32_t addr)
+{
+ return (uint16_t)((addr & ADDRESS_PERIPHID_Msk) >> ADDRESS_PERIPHID_Pos);
+}
+#endif
+
+NRF_STATIC_INLINE bool nrf_dma_accessible_check(void const * p_reg, void const * p_object)
+{
+#if defined(NRF_DMA_ACCESS_EXT)
+ NRF_DMA_ACCESS_EXT
+#else
+ (void)p_reg;
+ return ((((uint32_t)p_object) & 0xE0000000u) == 0x20000000u);
+#endif
+}
+
#endif // NRF_DECLARE_ONLY
#ifdef __cplusplus
diff --git a/mcu/nrf/common/vendor/hal/nrf_gpio.h b/mcu/nrf/common/vendor/hal/nrf_gpio.h
index 0364b6da..8506c737 100644
--- a/mcu/nrf/common/vendor/hal/nrf_gpio.h
+++ b/mcu/nrf/common/vendor/hal/nrf_gpio.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -50,14 +50,56 @@ extern "C" {
#elif (GPIO_COUNT == 2)
#define NUMBER_OF_PINS (P0_PIN_NUM + P1_PIN_NUM)
#define GPIO_REG_LIST {NRF_P0, NRF_P1}
-#else
+#endif
+
+#if !defined(GPIO_REG_LIST)
#error "Not supported."
#endif
+#if defined(GPIO_PIN_CNF_DRIVE0_Msk)
+#define GPIO_PIN_CNF_DRIVE1_OFFSET (GPIO_PIN_CNF_DRIVE1_Pos - GPIO_PIN_CNF_DRIVE0_Pos)
+#endif
+
#if defined(NRF52820_XXAA)
#include
#endif
+/*
+ * Macro for generating case code blocks that return token NRF_
+ * for case value equal to .
+ *
+ * Used by NRF_INTERNAL_GPIO_PORT_EXTRACT.
+ */
+#define NRF_INTERNAL_GPIO_PORT_EXTRACT_1(periph_name, prefix, i, port) \
+ case i: \
+ port = NRFX_CONCAT(NRF_, periph_name, prefix, i); \
+ break;
+
+/*
+ * Macro for generating case code blocks for switch statement used in function nrf_gpio_pin_port_decode.
+ * It allows extracting the port number relative to the decoded pin.
+ */
+#define NRF_INTERNAL_GPIO_PORT_EXTRACT(port) \
+ NRFX_FOREACH_PRESENT(P, NRF_INTERNAL_GPIO_PORT_EXTRACT_1, (), (), port)
+
+/*
+ * Macro for generating case code blocks that set mask to _FEATURE_PINS_PRESENT
+ * for case value equal to .
+ *
+ * Used by NRF_INTERNAL_GPIO_PORT_MASK_SET.
+ */
+#define NRF_INTERNAL_GPIO_PORT_MASK_SET_1(periph_name, prefix, i, mask) \
+ case i: \
+ mask = NRFX_CONCAT(periph_name, prefix, i, _FEATURE_PINS_PRESENT); \
+ break;
+
+/*
+ * Macro for generating case code blocks for switch statement used in function nrf_gpio_pin_present_check.
+ * It allows setting the mask to a value associated with the specific port.
+ */
+#define NRF_INTERNAL_GPIO_PORT_MASK_SET(mask) \
+ NRFX_FOREACH_PRESENT(P, NRF_INTERNAL_GPIO_PORT_MASK_SET_1, (), (), mask)
+
/**
* @defgroup nrf_gpio_hal GPIO HAL
* @{
@@ -70,9 +112,61 @@ extern "C" {
#define NRF_GPIO_LATCH_PRESENT
#endif
-/** @brief Macro for mapping port and pin numbers to values understandable for nrf_gpio functions. */
-#define NRF_GPIO_PIN_MAP(port, pin) (((port) << 5) | ((pin) & 0x1F))
+#if defined(GPIO_PIN_CNF_MCUSEL_Msk) || defined(GPIO_PIN_CNF_CTRLSEL_Msk) \
+ || defined(__NRFX_DOXYGEN__)
+/** @brief Presence of MCU/Subsystem control selection. */
+#define NRF_GPIO_HAS_SEL 1
+#else
+#define NRF_GPIO_HAS_SEL 0
+#endif
+#if defined(GPIO_PIN_CNF_CTRLSEL_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Presence of MCU/Subsystem control selection for multiple peripherals. */
+#define NRF_GPIO_HAS_MULTIPERIPH_SEL 1
+#else
+#define NRF_GPIO_HAS_MULTIPERIPH_SEL 0
+#endif
+
+#if defined(GPIO_PIN_CNF_CLOCKPIN_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Presence of clock pin enable. */
+#define NRF_GPIO_HAS_CLOCKPIN 1
+#else
+#define NRF_GPIO_HAS_CLOCKPIN 0
+#endif
+
+#if defined(GPIO_PORTCNF_DRIVECTRL_IMPEDANCE50_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Presence of drive control for impedance. */
+#define NRF_GPIO_HAS_PORT_IMPEDANCE 1
+#else
+#define NRF_GPIO_HAS_PORT_IMPEDANCE 0
+#endif
+
+#if defined(GPIO_RETAIN_APPLICAION_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Presence of register retention. */
+#define NRF_GPIO_HAS_RETENTION 1
+#else
+#define NRF_GPIO_HAS_RETENTION 0
+#endif
+
+#if defined(GPIO_DETECTMODE_DETECTMODE_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Presence of detect mode. */
+#define NRF_GPIO_HAS_DETECT_MODE 1
+#else
+#define NRF_GPIO_HAS_DETECT_MODE 0
+#endif
+
+/** @brief Macro for mapping port and pin numbers to values understandable for nrf_gpio functions. */
+#define NRF_GPIO_PIN_MAP(port, pin) NRF_PIN_PORT_TO_PIN_NUMBER(pin, port)
+
+#if NRF_GPIO_HAS_PORT_IMPEDANCE
+/** @brief Mask of all impedances. */
+#define NRF_GPIO_PORT_IMPEDANCE_ALL_MASK (GPIO_PORTCNF_DRIVECTRL_IMPEDANCE50_Msk | \
+ GPIO_PORTCNF_DRIVECTRL_IMPEDANCE100_Msk | \
+ GPIO_PORTCNF_DRIVECTRL_IMPEDANCE200_Msk | \
+ GPIO_PORTCNF_DRIVECTRL_IMPEDANCE400_Msk | \
+ GPIO_PORTCNF_DRIVECTRL_IMPEDANCE800_Msk | \
+ GPIO_PORTCNF_DRIVECTRL_IMPEDANCE1600_Msk)
+#endif
/** @brief Pin direction definitions. */
typedef enum
@@ -102,6 +196,7 @@ typedef enum
/** @brief Enumerator used for selecting output drive mode. */
typedef enum
{
+#if defined(GPIO_PIN_CNF_DRIVE_Msk) || defined(__NRFX_DOXYGEN__)
NRF_GPIO_PIN_S0S1 = GPIO_PIN_CNF_DRIVE_S0S1, ///< Standard '0', standard '1'.
NRF_GPIO_PIN_H0S1 = GPIO_PIN_CNF_DRIVE_H0S1, ///< High drive '0', standard '1'.
NRF_GPIO_PIN_S0H1 = GPIO_PIN_CNF_DRIVE_S0H1, ///< Standard '0', high drive '1'.
@@ -131,6 +226,38 @@ typedef enum
#if defined(GPIO_PIN_CNF_DRIVE_E0D1) || defined(__NRFX_DOXYGEN__)
NRF_GPIO_PIN_E0D1 = GPIO_PIN_CNF_DRIVE_E0D1, ///< Extra high drive '0', disconnect '1'.
#endif
+#else
+ NRF_GPIO_PIN_S0S1 = GPIO_PIN_CNF_DRIVE0_S0 |
+ (GPIO_PIN_CNF_DRIVE1_S1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
+ NRF_GPIO_PIN_H0S1 = GPIO_PIN_CNF_DRIVE0_H0 |
+ (GPIO_PIN_CNF_DRIVE1_S1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
+ NRF_GPIO_PIN_S0H1 = GPIO_PIN_CNF_DRIVE0_S0 |
+ (GPIO_PIN_CNF_DRIVE1_H1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
+ NRF_GPIO_PIN_H0H1 = GPIO_PIN_CNF_DRIVE0_H0 |
+ (GPIO_PIN_CNF_DRIVE1_H1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
+ NRF_GPIO_PIN_D0S1 = GPIO_PIN_CNF_DRIVE0_D0 |
+ (GPIO_PIN_CNF_DRIVE1_S1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
+ NRF_GPIO_PIN_D0H1 = GPIO_PIN_CNF_DRIVE0_D0 |
+ (GPIO_PIN_CNF_DRIVE1_H1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
+ NRF_GPIO_PIN_S0D1 = GPIO_PIN_CNF_DRIVE0_S0 |
+ (GPIO_PIN_CNF_DRIVE1_D1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
+ NRF_GPIO_PIN_H0D1 = GPIO_PIN_CNF_DRIVE0_H0 |
+ (GPIO_PIN_CNF_DRIVE1_D1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
+ NRF_GPIO_PIN_E0S1 = GPIO_PIN_CNF_DRIVE0_E0 |
+ (GPIO_PIN_CNF_DRIVE1_S1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
+ NRF_GPIO_PIN_S0E1 = GPIO_PIN_CNF_DRIVE0_S0 |
+ (GPIO_PIN_CNF_DRIVE1_E1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
+ NRF_GPIO_PIN_E0E1 = GPIO_PIN_CNF_DRIVE0_E0 |
+ (GPIO_PIN_CNF_DRIVE1_E1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
+ NRF_GPIO_PIN_E0H1 = GPIO_PIN_CNF_DRIVE0_E0 |
+ (GPIO_PIN_CNF_DRIVE1_H1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
+ NRF_GPIO_PIN_H0E1 = GPIO_PIN_CNF_DRIVE0_H0 |
+ (GPIO_PIN_CNF_DRIVE1_E1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
+ NRF_GPIO_PIN_D0E1 = GPIO_PIN_CNF_DRIVE0_D0 |
+ (GPIO_PIN_CNF_DRIVE1_E1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
+ NRF_GPIO_PIN_E0D1 = GPIO_PIN_CNF_DRIVE0_E0 |
+ (GPIO_PIN_CNF_DRIVE1_D1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
+#endif // defined(GPIO_PIN_CNF_DRIVE_Msk) || defined(__NRFX_DOXYGEN__)
} nrf_gpio_pin_drive_t;
/** @brief Enumerator used for selecting the pin to sense high or low level on the pin input. */
@@ -141,15 +268,41 @@ typedef enum
NRF_GPIO_PIN_SENSE_HIGH = GPIO_PIN_CNF_SENSE_High, ///< Pin sense high level.
} nrf_gpio_pin_sense_t;
-#if defined(GPIO_PIN_CNF_MCUSEL_Msk) || defined(__NRFX_DOXYGEN__)
+#if NRF_GPIO_HAS_SEL
/** @brief Enumerator used for selecting the MCU/Subsystem to control the specified pin. */
typedef enum
{
- NRF_GPIO_PIN_MCUSEL_APP = GPIO_PIN_CNF_MCUSEL_AppMCU, ///< Pin controlled by Application MCU.
- NRF_GPIO_PIN_MCUSEL_NETWORK = GPIO_PIN_CNF_MCUSEL_NetworkMCU, ///< Pin controlled by Network MCU.
- NRF_GPIO_PIN_MCUSEL_PERIPHERAL = GPIO_PIN_CNF_MCUSEL_Peripheral, ///< Pin controlled by dedicated peripheral.
- NRF_GPIO_PIN_MCUSEL_TND = GPIO_PIN_CNF_MCUSEL_TND, ///< Pin controlled by Trace and Debug Subsystem.
-} nrf_gpio_pin_mcusel_t;
+#if defined(GPIO_PIN_CNF_MCUSEL_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_GPIO_PIN_SEL_APP = GPIO_PIN_CNF_MCUSEL_AppMCU, ///< Pin controlled by Application MCU.
+ NRF_GPIO_PIN_SEL_NETWORK = GPIO_PIN_CNF_MCUSEL_NetworkMCU, ///< Pin controlled by Network MCU.
+ NRF_GPIO_PIN_SEL_PERIPHERAL = GPIO_PIN_CNF_MCUSEL_Peripheral, ///< Pin controlled by dedicated peripheral.
+ NRF_GPIO_PIN_SEL_TND = GPIO_PIN_CNF_MCUSEL_TND, ///< Pin controlled by Trace and Debug Subsystem.
+#endif
+#if defined(NRF_GPIO_PIN_SEL_EXT)
+ NRF_GPIO_PIN_SEL_EXT
+#endif
+} nrf_gpio_pin_sel_t;
+#endif // NRF_GPIO_HAS_SEL
+
+#if NRF_GPIO_HAS_PORT_IMPEDANCE
+/** @brief Port impedance enable mask. */
+typedef enum
+{
+ NRF_GPIO_PORT_IMPEDANCE_50_MASK = GPIO_PORTCNF_DRIVECTRL_IMPEDANCE50_Msk, //< Enable 50 Ohm impedance.
+ NRF_GPIO_PORT_IMPEDANCE_100_MASK = GPIO_PORTCNF_DRIVECTRL_IMPEDANCE100_Msk, //< Enable 100 Ohm impedance.
+ NRF_GPIO_PORT_IMPEDANCE_200_MASK = GPIO_PORTCNF_DRIVECTRL_IMPEDANCE200_Msk, //< Enable 200 Ohm impedance.
+ NRF_GPIO_PORT_IMPEDANCE_400_MASK = GPIO_PORTCNF_DRIVECTRL_IMPEDANCE400_Msk, //< Enable 400 Ohm impedance.
+ NRF_GPIO_PORT_IMPEDANCE_800_MASK = GPIO_PORTCNF_DRIVECTRL_IMPEDANCE800_Msk, //< Enable 800 Ohm impedance.
+ NRF_GPIO_PORT_IMPEDANCE_1600_MASK = GPIO_PORTCNF_DRIVECTRL_IMPEDANCE1600_Msk, //< Enable 1600 Ohm impedance.
+} nrf_gpio_port_impedance_mask_t;
+#endif
+
+#if NRF_GPIO_HAS_RETENTION
+/** @brief Retention enable mask. */
+typedef enum
+{
+ NRF_GPIO_RETAIN_EXT ///< Reserved. For internal use only.
+} nrf_gpio_retain_mask_t;
#endif
/**
@@ -200,6 +353,27 @@ NRF_STATIC_INLINE void nrf_gpio_cfg(
nrf_gpio_pin_drive_t drive,
nrf_gpio_pin_sense_t sense);
+/**
+ * @brief Function for reconfiguring pin.
+ *
+ * @note This function selectively updates fields in PIN_CNF register. Reconfiguration
+ * is performed in single register write. Fields for which new configuration is
+ * not provided remain unchanged.
+ *
+ * @param pin_number Specifies the pin number.
+ * @param p_dir Pin direction. If NULL, previous setting remains.
+ * @param p_input Connect or disconnect the input buffer. If NULL, previous setting remains.
+ * @param p_pull Pull configuration. If NULL, previous setting remains.
+ * @param p_drive Drive configuration. If NULL, previous setting remains.
+ * @param p_sense Pin sensing mechanism. If NULL, previous setting remains.
+ */
+NRF_STATIC_INLINE void nrf_gpio_reconfigure(uint32_t pin_number,
+ const nrf_gpio_pin_dir_t * p_dir,
+ const nrf_gpio_pin_input_t * p_input,
+ const nrf_gpio_pin_pull_t * p_pull,
+ const nrf_gpio_pin_drive_t * p_drive,
+ const nrf_gpio_pin_sense_t * p_sense);
+
/**
* @brief Function for configuring the given GPIO pin number as output, hiding inner details.
* This function can be used to configure a pin as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
@@ -379,6 +553,8 @@ NRF_STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32
/**
* @brief Function for writing the direction configuration of the GPIO pins in the given port.
*
+ * @warning This register is retained when retention is enabled.
+ *
* @param p_reg Pointer to the structure of registers of the peripheral.
* @param dir_mask Mask that specifies the direction of pins. Bit set means that the given pin is configured as output.
*/
@@ -387,6 +563,8 @@ NRF_STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t d
/**
* @brief Function for reading the direction configuration of a GPIO port.
*
+ * @warning This register is retained when retention is enabled.
+ *
* @param p_reg Pointer to the structure of registers of the peripheral.
*
* @return Pin configuration of the current direction settings. Bit set means that the given pin is configured as output.
@@ -405,6 +583,8 @@ NRF_STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg);
/**
* @brief Function for reading the output signals of the GPIO pins on the given port.
*
+ * @warning This register is retained when retention is enabled.
+ *
* @param p_reg Pointer to the peripheral registers structure.
*
* @return Port output values.
@@ -414,6 +594,8 @@ NRF_STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg);
/**
* @brief Function for writing the GPIO pins output on a given port.
*
+ * @warning This register is retained when retention is enabled.
+ *
* @param p_reg Pointer to the structure of registers of the peripheral.
* @param value Output port mask.
*/
@@ -446,10 +628,79 @@ NRF_STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port,
uint32_t length,
uint32_t * p_masks);
+#if NRF_GPIO_HAS_PORT_IMPEDANCE
+/**
+ * @brief Function for setting the impedance matching of the pins on the given port.
+ *
+ * @note Each bit sets certain impedance and have them in parallel when more than one bit is set.
+ * High impedance is set for the pin when all bits are disabled.
+ * When all bits are enabled, the resulting impedance is about 25 Ohm.
+ *
+ * @warning This register is retained when retention is enabled.
+ *
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ * @param mask Mask of impedances to be set, created using @ref nrf_gpio_port_impedance_mask_t.
+ */
+NRF_STATIC_INLINE void nrf_gpio_port_impedance_set(NRF_GPIO_Type * p_reg, uint32_t mask);
+
+/**
+ * @brief Function for geting the impedance matching of the pins on the given port.
+ *
+ * @warning This register is retained when retention is enabled.
+ *
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return Mask of impedances set, created using @ref nrf_gpio_port_impedance_mask_t.
+ */
+NRF_STATIC_INLINE uint32_t nrf_gpio_port_impedance_get(NRF_GPIO_Type const * p_reg);
+#endif
+
+#if NRF_GPIO_HAS_RETENTION
+/**
+ * @brief Function for setting the retention of the registers.
+ *
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ * @param mask Mask of retention domains to be enabled, created using @ref nrf_gpio_retain_mask_t.
+ */
+NRF_STATIC_INLINE void nrf_gpio_port_retain_set(NRF_GPIO_Type * p_reg, uint32_t mask);
+
+/**
+ * @brief Function for geting the retention setting of the registers.
+ *
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return Mask of retention domains set, created using @ref nrf_gpio_retain_mask_t.
+ */
+NRF_STATIC_INLINE uint32_t nrf_gpio_port_retain_get(NRF_GPIO_Type const * p_reg);
+#endif
+
+#if NRF_GPIO_HAS_DETECT_MODE
+/**
+ * @brief Function for setting the latched detect behaviour.
+ *
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ * @param enable True if the latched LDETECT behaviour is to be used, false if DETECT is to be
+ * directly connected to PIN DETECT signals.
+ */
+NRF_STATIC_INLINE void nrf_gpio_port_detect_latch_set(NRF_GPIO_Type * p_reg, bool enable);
+
+/**
+ * @brief Function for checking the latched detect behaviour.
+ *
+ * @param p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @retval true Latched LDETECT behaviour is used.
+ * @retval false DETECT is directly connected to PIN DETECT signals.
+ */
+NRF_STATIC_INLINE bool nrf_gpio_port_detect_latch_check(NRF_GPIO_Type const * p_reg);
+#endif
+
#if defined(NRF_GPIO_LATCH_PRESENT)
/**
* @brief Function for reading latch state of multiple consecutive ports.
*
+ * @warning This register is retained when retention is enabled.
+ *
* @param start_port Index of the first port to read.
* @param length Number of ports to read.
* @param p_masks Pointer to output array where latch states will be stored.
@@ -461,6 +712,8 @@ NRF_STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port,
/**
* @brief Function for reading and immediate clearing latch state of multiple consecutive ports.
*
+ * @warning This register is retained when retention is enabled.
+ *
* @param start_port Index of the first port to read and clear.
* @param length Number of ports to read and clear.
* @param p_masks Pointer to output array where latch states will be stored.
@@ -472,6 +725,8 @@ NRF_STATIC_INLINE void nrf_gpio_latches_read_and_clear(uint32_t start_port,
/**
* @brief Function for reading latch state of single pin.
*
+ * @warning This register is retained when retention is enabled.
+ *
* @param pin_number Pin number.
*
* @return 0 if latch is not set. Positive value otherwise.
@@ -481,19 +736,47 @@ NRF_STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number);
/**
* @brief Function for clearing latch state of a single pin.
*
+ * @warning This register is retained when retention is enabled.
+ *
* @param pin_number Pin number.
*/
NRF_STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number);
#endif // defined(NRF_GPIO_LATCH_PRESENT)
-#if defined(GPIO_PIN_CNF_MCUSEL_Msk) || defined(__NRFX_DOXYGEN__)
+#if NRF_GPIO_HAS_SEL
/**
- * @brief Function for selecting the MCU to control a GPIO pin.
+ * @brief Function for selecting the MCU or Subsystem to control a GPIO pin.
+ *
+ * @warning This register is retained when retention is enabled.
*
* @param pin_number Pin_number.
- * @param mcu MCU to control the pin.
+ * @param ctrl MCU/Subsystem to control the pin.
*/
-NRF_STATIC_INLINE void nrf_gpio_pin_mcu_select(uint32_t pin_number, nrf_gpio_pin_mcusel_t mcu);
+NRF_STATIC_INLINE void nrf_gpio_pin_control_select(uint32_t pin_number, nrf_gpio_pin_sel_t ctrl);
+#endif
+
+#if NRF_GPIO_HAS_CLOCKPIN
+/**
+ * @brief Function for setting whether the clock should be enabled for the specified GPIO pin.
+ *
+ * @warning This register is retained when retention is enabled.
+ *
+ * @param[in] pin_number Pin number.
+ * @param[in] enable True if clock is to be enabled, false otherwise.
+ */
+NRF_STATIC_INLINE void nrf_gpio_pin_clock_set(uint32_t pin_number, bool enable);
+
+/**
+ * @brief Function for getting the clock enable setting for the specified GPIO pin.
+ *
+ * @warning This register is retained when retention is enabled.
+ *
+ * @param[in] pin_number Pin number.
+ *
+ * @retval true Clock is enabled.
+ * @retval false Clock is disabled.
+ */
+NRF_STATIC_INLINE bool nrf_gpio_pin_clock_check(uint32_t pin_number);
#endif
/**
@@ -531,19 +814,16 @@ NRF_STATIC_INLINE NRF_GPIO_Type * nrf_gpio_pin_port_decode(uint32_t * p_pin)
{
NRFX_ASSERT(nrf_gpio_pin_present_check(*p_pin));
+ NRF_GPIO_Type * p_port = NULL;
+
switch (nrf_gpio_pin_port_number_extract(p_pin))
{
+ NRF_INTERNAL_GPIO_PORT_EXTRACT(p_port);
+
default:
NRFX_ASSERT(0);
-#if defined(P0_FEATURE_PINS_PRESENT)
- /* FALLTHROUGH */
- case 0: return NRF_P0;
-#endif
-#if defined(P1_FEATURE_PINS_PRESENT)
- /* FALLTHROUGH */
- case 1: return NRF_P1;
-#endif
}
+ return p_port;
}
@@ -576,22 +856,67 @@ NRF_STATIC_INLINE void nrf_gpio_cfg(
nrf_gpio_pin_sense_t sense)
{
NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
+ uint32_t cnf = reg->PIN_CNF[pin_number];
-#if defined(GPIO_PIN_CNF_MCUSEL_Msk)
- /* Preserve MCUSEL setting. */
- uint32_t cnf = reg->PIN_CNF[pin_number] & GPIO_PIN_CNF_MCUSEL_Msk;
+ uint32_t to_update = GPIO_PIN_CNF_DIR_Msk |
+ GPIO_PIN_CNF_INPUT_Msk |
+ GPIO_PIN_CNF_PULL_Msk |
+#if defined(GPIO_PIN_CNF_DRIVE_Msk)
+ GPIO_PIN_CNF_DRIVE_Msk |
+#else
+ GPIO_PIN_CNF_DRIVE0_Msk |
+ GPIO_PIN_CNF_DRIVE1_Msk |
+#endif
+ GPIO_PIN_CNF_SENSE_Msk;
+
+ /* Clear fields that will be updated. */
+ cnf &= ~to_update;
+ cnf |= ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos) |
+ ((uint32_t)input << GPIO_PIN_CNF_INPUT_Pos) |
+ ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos) |
+#if defined(GPIO_PIN_CNF_DRIVE_Pos)
+ ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) |
#else
- uint32_t cnf = 0;
+ ((uint32_t)drive << GPIO_PIN_CNF_DRIVE0_Pos) |
#endif
- cnf |= ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos) |
- ((uint32_t)input << GPIO_PIN_CNF_INPUT_Pos) |
- ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos) |
- ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) |
((uint32_t)sense << GPIO_PIN_CNF_SENSE_Pos);
reg->PIN_CNF[pin_number] = cnf;
}
+NRF_STATIC_INLINE void nrf_gpio_reconfigure(uint32_t pin_number,
+ const nrf_gpio_pin_dir_t * p_dir,
+ const nrf_gpio_pin_input_t * p_input,
+ const nrf_gpio_pin_pull_t * p_pull,
+ const nrf_gpio_pin_drive_t * p_drive,
+ const nrf_gpio_pin_sense_t * p_sense)
+{
+ NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
+ uint32_t cnf = reg->PIN_CNF[pin_number];
+ uint32_t to_update = (p_dir ? GPIO_PIN_CNF_DIR_Msk : 0) |
+ (p_input ? GPIO_PIN_CNF_INPUT_Msk : 0) |
+ (p_pull ? GPIO_PIN_CNF_PULL_Msk : 0) |
+#if defined(GPIO_PIN_CNF_DRIVE_Msk)
+ (p_drive ? GPIO_PIN_CNF_DRIVE_Msk : 0) |
+#else
+ (p_drive ? (GPIO_PIN_CNF_DRIVE0_Msk | GPIO_PIN_CNF_DRIVE1_Msk) : 0) |
+#endif
+ (p_sense ? GPIO_PIN_CNF_SENSE_Msk : 0);
+
+ /* Clear fields that will be updated. */
+ cnf &= ~to_update;
+ cnf |= ((uint32_t)(p_dir ? *p_dir : 0) << GPIO_PIN_CNF_DIR_Pos) |
+ ((uint32_t)(p_input ? *p_input : 0) << GPIO_PIN_CNF_INPUT_Pos) |
+ ((uint32_t)(p_pull ? *p_pull : 0) << GPIO_PIN_CNF_PULL_Pos) |
+#if defined(GPIO_PIN_CNF_DRIVE_Pos)
+ ((uint32_t)(p_drive ? *p_drive : 0) << GPIO_PIN_CNF_DRIVE_Pos) |
+#else
+ ((uint32_t)(p_drive ? *p_drive : 0) << GPIO_PIN_CNF_DRIVE0_Pos) |
+#endif
+ ((uint32_t)(p_sense ? *p_sense : 0)<< GPIO_PIN_CNF_SENSE_Pos);
+
+ reg->PIN_CNF[pin_number] = cnf;
+}
NRF_STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number)
{
@@ -631,19 +956,17 @@ NRF_STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number)
NRF_STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number)
{
- NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
- uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk;
+ nrf_gpio_pin_input_t input = NRF_GPIO_PIN_INPUT_CONNECT;
- reg->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos);
+ nrf_gpio_reconfigure(pin_number, NULL, &input, NULL, NULL, NULL);
}
NRF_STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number)
{
- NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
- uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk;
+ nrf_gpio_pin_input_t input = NRF_GPIO_PIN_INPUT_DISCONNECT;
- reg->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos);
+ nrf_gpio_reconfigure(pin_number, NULL, &input, NULL, NULL, NULL);
}
@@ -664,13 +987,9 @@ NRF_STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number,
NRF_STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number,
nrf_gpio_pin_sense_t sense_config)
{
- NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
- uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_SENSE_Msk;
-
- reg->PIN_CNF[pin_number] = cnf | (sense_config << GPIO_PIN_CNF_SENSE_Pos);
+ nrf_gpio_reconfigure(pin_number, NULL, NULL, NULL, NULL, &sense_config);
}
-
NRF_STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction)
{
if (direction == NRF_GPIO_PIN_DIR_INPUT)
@@ -850,6 +1169,43 @@ NRF_STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port,
}
}
+#if NRF_GPIO_HAS_PORT_IMPEDANCE
+NRF_STATIC_INLINE void nrf_gpio_port_impedance_set(NRF_GPIO_Type * p_reg, uint32_t mask)
+{
+ p_reg->PORTCNF.DRIVECTRL = ((p_reg->PORTCNF.DRIVECTRL & ~NRF_GPIO_PORT_IMPEDANCE_ALL_MASK) |
+ (mask & NRF_GPIO_PORT_IMPEDANCE_ALL_MASK));
+}
+
+NRF_STATIC_INLINE uint32_t nrf_gpio_port_impedance_get(NRF_GPIO_Type const * p_reg)
+{
+ return p_reg->PORTCNF.DRIVECTRL & NRF_GPIO_PORT_IMPEDANCE_ALL_MASK;
+}
+#endif
+
+#if NRF_GPIO_HAS_RETENTION
+NRF_STATIC_INLINE void nrf_gpio_port_retain_set(NRF_GPIO_Type * p_reg, uint32_t mask)
+{
+ p_reg->RETAIN = mask;
+}
+
+NRF_STATIC_INLINE uint32_t nrf_gpio_port_retain_get(NRF_GPIO_Type const * p_reg)
+{
+ return p_reg->RETAIN;
+}
+#endif
+
+#if NRF_GPIO_HAS_DETECT_MODE
+NRF_STATIC_INLINE void nrf_gpio_port_detect_latch_set(NRF_GPIO_Type * p_reg, bool enable)
+{
+ p_reg->DETECTMODE = (enable ? GPIO_DETECTMODE_DETECTMODE_LDETECT :
+ GPIO_DETECTMODE_DETECTMODE_Default);
+}
+
+NRF_STATIC_INLINE bool nrf_gpio_port_detect_latch_check(NRF_GPIO_Type const * p_reg)
+{
+ return (p_reg->DETECTMODE == GPIO_DETECTMODE_DETECTMODE_LDETECT);
+}
+#endif
#if defined(NRF_GPIO_LATCH_PRESENT)
NRF_STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port,
@@ -900,12 +1256,36 @@ NRF_STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number)
}
#endif // defined(NRF_GPIO_LATCH_PRESENT)
-#if defined(GPIO_PIN_CNF_MCUSEL_Msk)
-NRF_STATIC_INLINE void nrf_gpio_pin_mcu_select(uint32_t pin_number, nrf_gpio_pin_mcusel_t mcu)
+#if NRF_GPIO_HAS_SEL
+NRF_STATIC_INLINE void nrf_gpio_pin_control_select(uint32_t pin_number, nrf_gpio_pin_sel_t ctrl)
{
NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
+#if defined(GPIO_PIN_CNF_MCUSEL_Msk)
uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_MCUSEL_Msk;
- reg->PIN_CNF[pin_number] = cnf | (mcu << GPIO_PIN_CNF_MCUSEL_Pos);
+ reg->PIN_CNF[pin_number] = cnf | (ctrl << GPIO_PIN_CNF_MCUSEL_Pos);
+#else
+ uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_CTRLSEL_Msk;
+ reg->PIN_CNF[pin_number] = cnf | (ctrl << GPIO_PIN_CNF_CTRLSEL_Pos);
+#endif
+}
+#endif // NRF_GPIO_HAS_SEL
+
+#if NRF_GPIO_HAS_CLOCKPIN
+NRF_STATIC_INLINE void nrf_gpio_pin_clock_set(uint32_t pin_number, bool enable)
+{
+ NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
+
+ reg->PIN_CNF[pin_number] = ((reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_CLOCKPIN_Msk) |
+ ((enable ? GPIO_PIN_CNF_CLOCKPIN_Enabled :
+ GPIO_PIN_CNF_CLOCKPIN_Disabled) << GPIO_PIN_CNF_CLOCKPIN_Pos));
+}
+
+NRF_STATIC_INLINE bool nrf_gpio_pin_clock_check(uint32_t pin_number)
+{
+ NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
+
+ return (((reg->PIN_CNF[pin_number] & GPIO_PIN_CNF_CLOCKPIN_Msk) >> GPIO_PIN_CNF_CLOCKPIN_Pos)
+ == GPIO_PIN_CNF_CLOCKPIN_Enabled);
}
#endif
@@ -916,28 +1296,25 @@ NRF_STATIC_INLINE bool nrf_gpio_pin_present_check(uint32_t pin_number)
switch (port)
{
+ NRF_INTERNAL_GPIO_PORT_MASK_SET(mask);
+
+ default:
+ NRFX_ASSERT(0);
+ }
+
#ifdef P0_FEATURE_PINS_PRESENT
- case 0:
- mask = P0_FEATURE_PINS_PRESENT;
#if defined(NRF52820_XXAA) && defined(DEVELOP_IN_NRF52833)
- /* Allow use of the following additional GPIOs that are connected to LEDs and buttons
- * on the nRF52833 DK:
- * - P0.11 - Button 1
- * - P0.12 - Button 2
- * - P0.13 - LED 1
- * - P0.24 - Button 3
- * - P0.25 - Button 4
- */
- mask |= 0x03003800;
+ /* Allow use of the following additional GPIOs that are connected to LEDs and buttons
+ * on the nRF52833 DK:
+ * - P0.11 - Button 1
+ * - P0.12 - Button 2
+ * - P0.13 - LED 1
+ * - P0.24 - Button 3
+ * - P0.25 - Button 4
+ */
+ mask |= 0x03003800;
#endif // defined(NRF52820_XXAA) && defined(DEVELOP_IN_NRF52833)
- break;
#endif
-#ifdef P1_FEATURE_PINS_PRESENT
- case 1:
- mask = P1_FEATURE_PINS_PRESENT;
- break;
-#endif
- }
pin_number &= 0x1F;
@@ -947,9 +1324,9 @@ NRF_STATIC_INLINE bool nrf_gpio_pin_present_check(uint32_t pin_number)
NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin)
{
uint32_t pin_number = *p_pin;
- *p_pin = pin_number & 0x1F;
+ *p_pin = NRF_PIN_NUMBER_TO_PIN(pin_number);
- return pin_number >> 5;
+ return NRF_PIN_NUMBER_TO_PORT(pin_number);
}
#endif // NRF_DECLARE_ONLY
diff --git a/mcu/nrf/common/vendor/hal/nrf_gpiote.h b/mcu/nrf/common/vendor/hal/nrf_gpiote.h
index 6a58ac2e..4195be92 100644
--- a/mcu/nrf/common/vendor/hal/nrf_gpiote.h
+++ b/mcu/nrf/common/vendor/hal/nrf_gpiote.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -40,6 +40,9 @@
extern "C" {
#endif
+/* Internal macro used for NRF_GPIOTE_INT_IN_MASK. */
+#define NRF_GPIOTE_INT_IN(idx, _) NRFX_CONCAT(NRF_GPIOTE_INT_IN, idx, _MASK)
+
/**
* @defgroup nrf_gpiote_hal GPIOTE HAL
* @{
@@ -61,107 +64,134 @@ extern "C" {
#define NRF_GPIOTE_HAS_LATENCY 0
#endif
- /** @brief Polarity for the GPIOTE channel. */
+#if !defined(NRF_GPIOTE_IRQ_GROUP) || defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating which interrupt group to use. Empty if there are no groups. */
+#define NRF_GPIOTE_IRQ_GROUP
+#endif
+
+#if defined(GPIOTE_INTENSET0_PORT0SECURE_Msk)
+#if defined(NRF_TRUSTZONE_NONSECURE) || defined(ISA_RISCV)
+#define NRF_GPIOTE_SECURE_SUFFIX NONSECURE
+#else
+#define NRF_GPIOTE_SECURE_SUFFIX SECURE
+#endif
+#else
+/** @brief Symbol indicating a TrustZone suffix added to the register name. */
+#define NRF_GPIOTE_SECURE_SUFFIX
+#endif
+
+#if defined(NRF_GPIOTE_PORT_ID)
+#define NRF_GPIOTE_EVENTS_PORT_REG EVENTS_PORT[NRF_GPIOTE_PORT_ID].NRF_GPIOTE_SECURE_SUFFIX
+
+#define NRF_GPIOTE_INT_PORT_MASK_NAME \
+ NRFX_CONCAT(GPIOTE_INTENSET, \
+ NRF_GPIOTE_IRQ_GROUP, \
+ _PORT, \
+ NRF_GPIOTE_PORT_ID, \
+ NRF_GPIOTE_SECURE_SUFFIX, \
+ _Msk)
+#else
+/** @brief Symbol indicating a name of PORT event register to be used. */
+#define NRF_GPIOTE_EVENTS_PORT_REG EVENTS_PORT
+
+/** @brief Symbol specifying interrupt bitmask associated with the PORT event. */
+#define NRF_GPIOTE_INT_PORT_MASK_NAME GPIOTE_INTENSET_PORT_Msk
+#endif
+
+/** @brief Polarity for the GPIOTE channel. */
typedef enum
{
- NRF_GPIOTE_POLARITY_LOTOHI = GPIOTE_CONFIG_POLARITY_LoToHi, /**< Low to high. */
- NRF_GPIOTE_POLARITY_HITOLO = GPIOTE_CONFIG_POLARITY_HiToLo, /**< High to low. */
- NRF_GPIOTE_POLARITY_TOGGLE = GPIOTE_CONFIG_POLARITY_Toggle, /**< Toggle. */
+ NRF_GPIOTE_POLARITY_NONE = GPIOTE_CONFIG_POLARITY_None, ///< None.
+ NRF_GPIOTE_POLARITY_LOTOHI = GPIOTE_CONFIG_POLARITY_LoToHi, ///< Low to high.
+ NRF_GPIOTE_POLARITY_HITOLO = GPIOTE_CONFIG_POLARITY_HiToLo, ///< High to low.
+ NRF_GPIOTE_POLARITY_TOGGLE = GPIOTE_CONFIG_POLARITY_Toggle, ///< Toggle.
} nrf_gpiote_polarity_t;
/** @brief Initial output value for the GPIOTE channel. */
typedef enum
{
- NRF_GPIOTE_INITIAL_VALUE_LOW = GPIOTE_CONFIG_OUTINIT_Low, /**< Low to high. */
- NRF_GPIOTE_INITIAL_VALUE_HIGH = GPIOTE_CONFIG_OUTINIT_High, /**< High to low. */
+ NRF_GPIOTE_INITIAL_VALUE_LOW = GPIOTE_CONFIG_OUTINIT_Low, ///< Low to high.
+ NRF_GPIOTE_INITIAL_VALUE_HIGH = GPIOTE_CONFIG_OUTINIT_High, ///< High to low.
} nrf_gpiote_outinit_t;
#if NRF_GPIOTE_HAS_LATENCY
/** @brief Latency setting. */
typedef enum
{
- NRF_GPIOTE_LATENCY_LOWPOWER = GPIOTE_LATENCY_LATENCY_LowPower, /**< Low Power. */
- NRF_GPIOTE_LATENCY_LOWLATENCY = GPIOTE_LATENCY_LATENCY_LowLatency, /**< Low Latency. */
+ NRF_GPIOTE_LATENCY_LOWPOWER = GPIOTE_LATENCY_LATENCY_LowPower, ///< Low Power.
+ NRF_GPIOTE_LATENCY_LOWLATENCY = GPIOTE_LATENCY_LATENCY_LowLatency, ///< Low Latency.
} nrf_gpiote_latency_t;
#endif
/** @brief GPIOTE tasks. */
typedef enum
{
- NRF_GPIOTE_TASK_OUT_0 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[0]), /**< Out task 0. */
- NRF_GPIOTE_TASK_OUT_1 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[1]), /**< Out task 1. */
- NRF_GPIOTE_TASK_OUT_2 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[2]), /**< Out task 2. */
- NRF_GPIOTE_TASK_OUT_3 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[3]), /**< Out task 3. */
+ NRF_GPIOTE_TASK_OUT_0 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[0]), ///< Out task 0.
+ NRF_GPIOTE_TASK_OUT_1 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[1]), ///< Out task 1.
+ NRF_GPIOTE_TASK_OUT_2 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[2]), ///< Out task 2.
+ NRF_GPIOTE_TASK_OUT_3 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[3]), ///< Out task 3.
#if (GPIOTE_CH_NUM > 4) || defined(__NRFX_DOXYGEN__)
- NRF_GPIOTE_TASK_OUT_4 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[4]), /**< Out task 4. */
- NRF_GPIOTE_TASK_OUT_5 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[5]), /**< Out task 5. */
- NRF_GPIOTE_TASK_OUT_6 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[6]), /**< Out task 6. */
- NRF_GPIOTE_TASK_OUT_7 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[7]), /**< Out task 7. */
+ NRF_GPIOTE_TASK_OUT_4 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[4]), ///< Out task 4.
+ NRF_GPIOTE_TASK_OUT_5 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[5]), ///< Out task 5.
+ NRF_GPIOTE_TASK_OUT_6 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[6]), ///< Out task 6.
+ NRF_GPIOTE_TASK_OUT_7 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[7]), ///< Out task 7.
#endif
#if defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__NRFX_DOXYGEN__)
- NRF_GPIOTE_TASK_SET_0 = offsetof(NRF_GPIOTE_Type, TASKS_SET[0]), /**< Set task 0. */
- NRF_GPIOTE_TASK_SET_1 = offsetof(NRF_GPIOTE_Type, TASKS_SET[1]), /**< Set task 1. */
- NRF_GPIOTE_TASK_SET_2 = offsetof(NRF_GPIOTE_Type, TASKS_SET[2]), /**< Set task 2. */
- NRF_GPIOTE_TASK_SET_3 = offsetof(NRF_GPIOTE_Type, TASKS_SET[3]), /**< Set task 3. */
- NRF_GPIOTE_TASK_SET_4 = offsetof(NRF_GPIOTE_Type, TASKS_SET[4]), /**< Set task 4. */
- NRF_GPIOTE_TASK_SET_5 = offsetof(NRF_GPIOTE_Type, TASKS_SET[5]), /**< Set task 5. */
- NRF_GPIOTE_TASK_SET_6 = offsetof(NRF_GPIOTE_Type, TASKS_SET[6]), /**< Set task 6. */
- NRF_GPIOTE_TASK_SET_7 = offsetof(NRF_GPIOTE_Type, TASKS_SET[7]), /**< Set task 7. */
+ NRF_GPIOTE_TASK_SET_0 = offsetof(NRF_GPIOTE_Type, TASKS_SET[0]), ///< Set task 0.
+ NRF_GPIOTE_TASK_SET_1 = offsetof(NRF_GPIOTE_Type, TASKS_SET[1]), ///< Set task 1.
+ NRF_GPIOTE_TASK_SET_2 = offsetof(NRF_GPIOTE_Type, TASKS_SET[2]), ///< Set task 2.
+ NRF_GPIOTE_TASK_SET_3 = offsetof(NRF_GPIOTE_Type, TASKS_SET[3]), ///< Set task 3.
+ NRF_GPIOTE_TASK_SET_4 = offsetof(NRF_GPIOTE_Type, TASKS_SET[4]), ///< Set task 4.
+ NRF_GPIOTE_TASK_SET_5 = offsetof(NRF_GPIOTE_Type, TASKS_SET[5]), ///< Set task 5.
+ NRF_GPIOTE_TASK_SET_6 = offsetof(NRF_GPIOTE_Type, TASKS_SET[6]), ///< Set task 6.
+ NRF_GPIOTE_TASK_SET_7 = offsetof(NRF_GPIOTE_Type, TASKS_SET[7]), ///< Set task 7.
#endif
#if defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__NRFX_DOXYGEN__)
- NRF_GPIOTE_TASK_CLR_0 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[0]), /**< Clear task 0. */
- NRF_GPIOTE_TASK_CLR_1 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[1]), /**< Clear task 1. */
- NRF_GPIOTE_TASK_CLR_2 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[2]), /**< Clear task 2. */
- NRF_GPIOTE_TASK_CLR_3 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[3]), /**< Clear task 3. */
- NRF_GPIOTE_TASK_CLR_4 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[4]), /**< Clear task 4. */
- NRF_GPIOTE_TASK_CLR_5 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[5]), /**< Clear task 5. */
- NRF_GPIOTE_TASK_CLR_6 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[6]), /**< Clear task 6. */
- NRF_GPIOTE_TASK_CLR_7 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[7]), /**< Clear task 7. */
+ NRF_GPIOTE_TASK_CLR_0 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[0]), ///< Clear task 0.
+ NRF_GPIOTE_TASK_CLR_1 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[1]), ///< Clear task 1.
+ NRF_GPIOTE_TASK_CLR_2 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[2]), ///< Clear task 2.
+ NRF_GPIOTE_TASK_CLR_3 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[3]), ///< Clear task 3.
+ NRF_GPIOTE_TASK_CLR_4 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[4]), ///< Clear task 4.
+ NRF_GPIOTE_TASK_CLR_5 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[5]), ///< Clear task 5.
+ NRF_GPIOTE_TASK_CLR_6 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[6]), ///< Clear task 6.
+ NRF_GPIOTE_TASK_CLR_7 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[7]), ///< Clear task 7.
#endif
} nrf_gpiote_task_t;
/** @brief GPIOTE events. */
typedef enum
{
- NRF_GPIOTE_EVENT_IN_0 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[0]), /**< In event 0. */
- NRF_GPIOTE_EVENT_IN_1 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[1]), /**< In event 1. */
- NRF_GPIOTE_EVENT_IN_2 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[2]), /**< In event 2. */
- NRF_GPIOTE_EVENT_IN_3 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[3]), /**< In event 3. */
+ NRF_GPIOTE_EVENT_IN_0 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[0]), ///< In event 0.
+ NRF_GPIOTE_EVENT_IN_1 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[1]), ///< In event 1.
+ NRF_GPIOTE_EVENT_IN_2 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[2]), ///< In event 2.
+ NRF_GPIOTE_EVENT_IN_3 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[3]), ///< In event 3.
#if (GPIOTE_CH_NUM > 4) || defined(__NRFX_DOXYGEN__)
- NRF_GPIOTE_EVENT_IN_4 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[4]), /**< In event 4. */
- NRF_GPIOTE_EVENT_IN_5 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[5]), /**< In event 5. */
- NRF_GPIOTE_EVENT_IN_6 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[6]), /**< In event 6. */
- NRF_GPIOTE_EVENT_IN_7 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[7]), /**< In event 7. */
+ NRF_GPIOTE_EVENT_IN_4 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[4]), ///< In event 4.
+ NRF_GPIOTE_EVENT_IN_5 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[5]), ///< In event 5.
+ NRF_GPIOTE_EVENT_IN_6 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[6]), ///< In event 6.
+ NRF_GPIOTE_EVENT_IN_7 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[7]), ///< In event 7.
#endif
- NRF_GPIOTE_EVENT_PORT = offsetof(NRF_GPIOTE_Type, EVENTS_PORT), /**< Port event. */
+ NRF_GPIOTE_EVENT_PORT = offsetof(NRF_GPIOTE_Type, NRF_GPIOTE_EVENTS_PORT_REG), ///< Port event.
} nrf_gpiote_event_t;
/** @brief GPIOTE interrupts. */
typedef enum
{
- NRF_GPIOTE_INT_IN0_MASK = GPIOTE_INTENSET_IN0_Msk, /**< GPIOTE interrupt from IN0. */
- NRF_GPIOTE_INT_IN1_MASK = GPIOTE_INTENSET_IN1_Msk, /**< GPIOTE interrupt from IN1. */
- NRF_GPIOTE_INT_IN2_MASK = GPIOTE_INTENSET_IN2_Msk, /**< GPIOTE interrupt from IN2. */
- NRF_GPIOTE_INT_IN3_MASK = GPIOTE_INTENSET_IN3_Msk, /**< GPIOTE interrupt from IN3. */
+ NRF_GPIOTE_INT_IN0_MASK = NRFX_CONCAT(GPIOTE_INTENSET, NRF_GPIOTE_IRQ_GROUP, _IN0_Msk), ///< GPIOTE interrupt from IN0.
+ NRF_GPIOTE_INT_IN1_MASK = NRFX_CONCAT(GPIOTE_INTENSET, NRF_GPIOTE_IRQ_GROUP, _IN1_Msk), ///< GPIOTE interrupt from IN1.
+ NRF_GPIOTE_INT_IN2_MASK = NRFX_CONCAT(GPIOTE_INTENSET, NRF_GPIOTE_IRQ_GROUP, _IN2_Msk), ///< GPIOTE interrupt from IN2.
+ NRF_GPIOTE_INT_IN3_MASK = NRFX_CONCAT(GPIOTE_INTENSET, NRF_GPIOTE_IRQ_GROUP, _IN3_Msk), ///< GPIOTE interrupt from IN3.
#if (GPIOTE_CH_NUM > 4) || defined(__NRFX_DOXYGEN__)
- NRF_GPIOTE_INT_IN4_MASK = GPIOTE_INTENSET_IN4_Msk, /**< GPIOTE interrupt from IN4. */
- NRF_GPIOTE_INT_IN5_MASK = GPIOTE_INTENSET_IN5_Msk, /**< GPIOTE interrupt from IN5. */
- NRF_GPIOTE_INT_IN6_MASK = GPIOTE_INTENSET_IN6_Msk, /**< GPIOTE interrupt from IN6. */
- NRF_GPIOTE_INT_IN7_MASK = GPIOTE_INTENSET_IN7_Msk, /**< GPIOTE interrupt from IN7. */
+ NRF_GPIOTE_INT_IN4_MASK = NRFX_CONCAT(GPIOTE_INTENSET, NRF_GPIOTE_IRQ_GROUP, _IN4_Msk), ///< GPIOTE interrupt from IN4.
+ NRF_GPIOTE_INT_IN5_MASK = NRFX_CONCAT(GPIOTE_INTENSET, NRF_GPIOTE_IRQ_GROUP, _IN5_Msk), ///< GPIOTE interrupt from IN5.
+ NRF_GPIOTE_INT_IN6_MASK = NRFX_CONCAT(GPIOTE_INTENSET, NRF_GPIOTE_IRQ_GROUP, _IN6_Msk), ///< GPIOTE interrupt from IN6.
+ NRF_GPIOTE_INT_IN7_MASK = NRFX_CONCAT(GPIOTE_INTENSET, NRF_GPIOTE_IRQ_GROUP, _IN7_Msk), ///< GPIOTE interrupt from IN7.
#endif
- NRF_GPIOTE_INT_PORT_MASK = (int)GPIOTE_INTENSET_PORT_Msk, /**< GPIOTE interrupt from PORT event. */
+ NRF_GPIOTE_INT_PORT_MASK = (int)NRF_GPIOTE_INT_PORT_MASK_NAME ///< GPIOTE interrupt from PORT event.
} nrf_gpiote_int_t;
-#if (GPIOTE_CH_NUM == 4) || defined(__NRFX_DOXYGEN__)
-/** @brief Mask holding positions of available GPIOTE input interrupts. */
-#define NRF_GPIOTE_INT_IN_MASK (NRF_GPIOTE_INT_IN0_MASK | NRF_GPIOTE_INT_IN1_MASK |\
- NRF_GPIOTE_INT_IN2_MASK | NRF_GPIOTE_INT_IN3_MASK)
-#else
-#define NRF_GPIOTE_INT_IN_MASK (NRF_GPIOTE_INT_IN0_MASK | NRF_GPIOTE_INT_IN1_MASK |\
- NRF_GPIOTE_INT_IN2_MASK | NRF_GPIOTE_INT_IN3_MASK |\
- NRF_GPIOTE_INT_IN4_MASK | NRF_GPIOTE_INT_IN5_MASK |\
- NRF_GPIOTE_INT_IN6_MASK | NRF_GPIOTE_INT_IN7_MASK)
-#endif
+/** @brief Symbol specifying bitmask collecting all IN events interrupts. */
+#define NRF_GPIOTE_INT_IN_MASK (NRFX_LISTIFY(GPIOTE_CH_NUM, NRF_GPIOTE_INT_IN, (|), _))
/**
* @brief Function for activating the specified GPIOTE task.
@@ -386,7 +416,8 @@ NRF_STATIC_INLINE void nrf_gpiote_task_force(NRF_GPIOTE_Type * p_reg,
*/
NRF_STATIC_INLINE void nrf_gpiote_te_default(NRF_GPIOTE_Type * p_reg, uint32_t idx);
-/**@brief Function for checking if particular Task-Event is enabled.
+/**
+ * @brief Function for checking if particular Task-Event is enabled.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] idx Task-Event index.
@@ -492,17 +523,17 @@ NRF_STATIC_INLINE uint32_t nrf_gpiote_event_address_get(NRF_GPIOTE_Type const *
NRF_STATIC_INLINE void nrf_gpiote_int_enable(NRF_GPIOTE_Type * p_reg, uint32_t mask)
{
- p_reg->INTENSET = mask;
+ p_reg->NRFX_CONCAT_2(INTENSET, NRF_GPIOTE_IRQ_GROUP) = mask;
}
NRF_STATIC_INLINE void nrf_gpiote_int_disable(NRF_GPIOTE_Type * p_reg, uint32_t mask)
{
- p_reg->INTENCLR = mask;
+ p_reg->NRFX_CONCAT_2(INTENCLR, NRF_GPIOTE_IRQ_GROUP) = mask;
}
NRF_STATIC_INLINE uint32_t nrf_gpiote_int_enable_check(NRF_GPIOTE_Type const * p_reg, uint32_t mask)
{
- return p_reg->INTENSET & mask;
+ return p_reg->NRFX_CONCAT_2(INTENSET, NRF_GPIOTE_IRQ_GROUP) & mask;
}
#if defined(DPPI_PRESENT)
@@ -511,7 +542,7 @@ NRF_STATIC_INLINE void nrf_gpiote_subscribe_set(NRF_GPIOTE_Type * p_reg,
uint8_t channel)
{
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
- ((uint32_t)channel | GPIOTE_SUBSCRIBE_OUT_EN_Msk);
+ ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
}
NRF_STATIC_INLINE void nrf_gpiote_subscribe_clear(NRF_GPIOTE_Type * p_reg, nrf_gpiote_task_t task)
@@ -524,7 +555,7 @@ NRF_STATIC_INLINE void nrf_gpiote_publish_set(NRF_GPIOTE_Type * p_reg,
uint8_t channel)
{
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
- ((uint32_t)channel | GPIOTE_PUBLISH_IN_EN_Msk);
+ ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
}
NRF_STATIC_INLINE void nrf_gpiote_publish_clear(NRF_GPIOTE_Type * p_reg, nrf_gpiote_event_t event)
@@ -540,7 +571,7 @@ NRF_STATIC_INLINE void nrf_gpiote_event_enable(NRF_GPIOTE_Type * p_reg, uint32_t
NRF_STATIC_INLINE void nrf_gpiote_event_disable(NRF_GPIOTE_Type * p_reg, uint32_t idx)
{
- p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Event;
+ p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk;
}
NRF_STATIC_INLINE void nrf_gpiote_event_configure(NRF_GPIOTE_Type * p_reg,
@@ -585,7 +616,7 @@ NRF_STATIC_INLINE void nrf_gpiote_task_enable(NRF_GPIOTE_Type * p_reg, uint32_t
NRF_STATIC_INLINE void nrf_gpiote_task_disable(NRF_GPIOTE_Type * p_reg, uint32_t idx)
{
- p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Task;
+ p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk;
}
NRF_STATIC_INLINE void nrf_gpiote_task_configure(NRF_GPIOTE_Type * p_reg,
@@ -614,6 +645,9 @@ NRF_STATIC_INLINE void nrf_gpiote_task_force(NRF_GPIOTE_Type * p_reg,
NRF_STATIC_INLINE void nrf_gpiote_te_default(NRF_GPIOTE_Type * p_reg, uint32_t idx)
{
p_reg->CONFIG[idx] = 0;
+#if !defined(NRF51_SERIES) && !defined(NRF52_SERIES)
+ p_reg->CONFIG[idx] = 0;
+#endif
}
NRF_STATIC_INLINE bool nrf_gpiote_te_is_enabled(NRF_GPIOTE_Type const * p_reg, uint32_t idx)
diff --git a/mcu/nrf/common/vendor/hal/nrf_timer.h b/mcu/nrf/common/vendor/hal/nrf_timer.h
index 64da71c5..10b77832 100644
--- a/mcu/nrf/common/vendor/hal/nrf_timer.h
+++ b/mcu/nrf/common/vendor/hal/nrf_timer.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014 - 2021, Nordic Semiconductor ASA
+ * Copyright (c) 2014 - 2023, Nordic Semiconductor ASA
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -47,6 +47,71 @@ extern "C" {
* @brief Hardware access layer for managing the TIMER peripheral.
*/
+/**
+ * @brief Macro getting pointer to the structure of registers of the TIMER peripheral.
+ *
+ * @param[in] idx TIMER instance index.
+ *
+ * @return Pointer to the structure of registers of the TIMER peripheral.
+ */
+#define NRF_TIMER_INST_GET(idx) NRFX_CONCAT_2(NRF_TIMER, idx)
+
+#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether timer has capture/compare channel 4. */
+#define NRF_TIMER_HAS_CC4 1
+#else
+#define NRF_TIMER_HAS_CC4 0
+#endif
+
+#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether timer has capture/compare channel 5. */
+#define NRF_TIMER_HAS_CC5 1
+#else
+#define NRF_TIMER_HAS_CC5 0
+#endif
+
+#if defined(TIMER_INTENSET_COMPARE6_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether timer has capture/compare channel 6. */
+#define NRF_TIMER_HAS_CC6 1
+#else
+#define NRF_TIMER_HAS_CC6 0
+#endif
+
+#if defined(TIMER_INTENSET_COMPARE7_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether timer has capture/compare channel 7. */
+#define NRF_TIMER_HAS_CC7 1
+#else
+#define NRF_TIMER_HAS_CC7 0
+#endif
+
+#if defined(TIMER_MODE_MODE_LowPowerCounter) || defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether timer supports low power mode. */
+#define NRF_TIMER_HAS_LOW_POWER_MODE 1
+#else
+#define NRF_TIMER_HAS_LOW_POWER_MODE 0
+#endif
+
+#if defined(TIMER_ONESHOTEN_ONESHOTEN_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether timer supports one-shot operation. */
+#define NRF_TIMER_HAS_ONE_SHOT 1
+#else
+#define NRF_TIMER_HAS_ONE_SHOT 0
+#endif
+
+/** @brief Base frequency value 320 MHz for TIMER. */
+#define NRF_TIMER_BASE_FREQUENCY_320MHZ (NRFX_MHZ_TO_HZ(320UL))
+/** @brief Base frequency value 64 MHz for TIMER. */
+#define NRF_TIMER_BASE_FREQUENCY_64MHZ (NRFX_MHZ_TO_HZ(64UL))
+/** @brief Base frequency value 32 MHz for TIMER. */
+#define NRF_TIMER_BASE_FREQUENCY_32MHZ (NRFX_MHZ_TO_HZ(32UL))
+/** @brief Base frequency value 16 MHz for TIMER. */
+#define NRF_TIMER_BASE_FREQUENCY_16MHZ (NRFX_MHZ_TO_HZ(16UL))
+
+#if !defined(NRF_TIMER_PRESCALER_MAX)
+/** @brief Maximum value of PRESCALER register. */
+#define NRF_TIMER_PRESCALER_MAX 9
+#endif
+
/**
* @brief Macro for getting the maximum bit resolution of the specified timer instance.
*
@@ -87,36 +152,102 @@ extern "C" {
* @retval true Timer instance supports the specified bit width resolution value.
* @retval false Timer instance does not support the specified bit width resolution value.
*/
-#if (TIMER_COUNT == 3) || defined(__NRFX_DOXYGEN__)
- #define NRF_TIMER_IS_BIT_WIDTH_VALID(p_reg, bit_width) ( \
- ((p_reg == NRF_TIMER0) && TIMER_BIT_WIDTH_MAX(0, bit_width)) \
- || ((p_reg == NRF_TIMER1) && TIMER_BIT_WIDTH_MAX(1, bit_width)) \
- || ((p_reg == NRF_TIMER2) && TIMER_BIT_WIDTH_MAX(2, bit_width)))
-#elif (TIMER_COUNT == 4)
- #define NRF_TIMER_IS_BIT_WIDTH_VALID(p_reg, bit_width) ( \
- ((p_reg == NRF_TIMER0) && TIMER_BIT_WIDTH_MAX(0, bit_width)) \
- || ((p_reg == NRF_TIMER1) && TIMER_BIT_WIDTH_MAX(1, bit_width)) \
- || ((p_reg == NRF_TIMER2) && TIMER_BIT_WIDTH_MAX(2, bit_width)) \
- || ((p_reg == NRF_TIMER3) && TIMER_BIT_WIDTH_MAX(3, bit_width)))
-#elif (TIMER_COUNT == 5)
- #define NRF_TIMER_IS_BIT_WIDTH_VALID(p_reg, bit_width) ( \
- ((p_reg == NRF_TIMER0) && TIMER_BIT_WIDTH_MAX(0, bit_width)) \
- || ((p_reg == NRF_TIMER1) && TIMER_BIT_WIDTH_MAX(1, bit_width)) \
- || ((p_reg == NRF_TIMER2) && TIMER_BIT_WIDTH_MAX(2, bit_width)) \
- || ((p_reg == NRF_TIMER3) && TIMER_BIT_WIDTH_MAX(3, bit_width)) \
- || ((p_reg == NRF_TIMER4) && TIMER_BIT_WIDTH_MAX(4, bit_width)))
-#else
- #error "Not supported timer count"
+#if !defined(NRF_TIMER_IS_BIT_WIDTH_VALID)
+ #if (TIMER_COUNT == 3) || defined(__NRFX_DOXYGEN__)
+ #define NRF_TIMER_IS_BIT_WIDTH_VALID(p_reg, bit_width) ( \
+ ((p_reg == NRF_TIMER0) && TIMER_BIT_WIDTH_MAX(0, bit_width)) \
+ || ((p_reg == NRF_TIMER1) && TIMER_BIT_WIDTH_MAX(1, bit_width)) \
+ || ((p_reg == NRF_TIMER2) && TIMER_BIT_WIDTH_MAX(2, bit_width)))
+ #elif (TIMER_COUNT == 4)
+ #define NRF_TIMER_IS_BIT_WIDTH_VALID(p_reg, bit_width) ( \
+ ((p_reg == NRF_TIMER0) && TIMER_BIT_WIDTH_MAX(0, bit_width)) \
+ || ((p_reg == NRF_TIMER1) && TIMER_BIT_WIDTH_MAX(1, bit_width)) \
+ || ((p_reg == NRF_TIMER2) && TIMER_BIT_WIDTH_MAX(2, bit_width)) \
+ || ((p_reg == NRF_TIMER3) && TIMER_BIT_WIDTH_MAX(3, bit_width)))
+ #elif (TIMER_COUNT == 5)
+ #define NRF_TIMER_IS_BIT_WIDTH_VALID(p_reg, bit_width) ( \
+ ((p_reg == NRF_TIMER0) && TIMER_BIT_WIDTH_MAX(0, bit_width)) \
+ || ((p_reg == NRF_TIMER1) && TIMER_BIT_WIDTH_MAX(1, bit_width)) \
+ || ((p_reg == NRF_TIMER2) && TIMER_BIT_WIDTH_MAX(2, bit_width)) \
+ || ((p_reg == NRF_TIMER3) && TIMER_BIT_WIDTH_MAX(3, bit_width)) \
+ || ((p_reg == NRF_TIMER4) && TIMER_BIT_WIDTH_MAX(4, bit_width)))
+ #else
+ #error "Not supported timer count"
+ #endif
+#endif
+
+#if !defined(NRF_TIMER_IS_320MHZ_TIMER)
+/** @brief Macro for checking whether the base frequency for the specified timer is 320 MHz. */
+#define NRF_TIMER_IS_320MHZ_TIMER(p_reg) false
+#endif
+
+#if !defined(NRF_TIMER_IS_64MHZ_TIMER)
+/** @brief Macro for checking whether the base frequency for the specified timer is 64 MHz. */
+#define NRF_TIMER_IS_64MHZ_TIMER(p_reg) false
+#endif
+
+#if !defined(NRF_TIMER_IS_32MHZ_TIMER)
+/** @brief Macro for checking whether the base frequency for the specified timer is 32 MHz. */
+#define NRF_TIMER_IS_32MHZ_TIMER(p_reg) false
#endif
+#if !defined(NRF_TIMER_IS_16MHZ_TIMER)
+/** @brief Macro for checking whether the base frequency for the specified timer is 16 MHz. */
+#define NRF_TIMER_IS_16MHZ_TIMER(p_reg) true
+#endif
+
+/**
+ * @brief Macro for getting base frequency value in Hz for the specified timer.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ */
+#define NRF_TIMER_BASE_FREQUENCY_GET(p_reg) \
+ ((NRF_TIMER_IS_320MHZ_TIMER(p_reg)) ? (NRF_TIMER_BASE_FREQUENCY_320MHZ): \
+ ((NRF_TIMER_IS_64MHZ_TIMER(p_reg)) ? (NRF_TIMER_BASE_FREQUENCY_64MHZ): \
+ ((NRF_TIMER_IS_16MHZ_TIMER(p_reg)) ? (NRF_TIMER_BASE_FREQUENCY_16MHZ) : \
+ (NRF_TIMER_BASE_FREQUENCY_32MHZ))))
+
+/**
+ * @brief Macro for computing prescaler value for given base frequency and desired frequency.
+ *
+ * @warning Not every combination of base frequency and desired frequency is supported.
+ *
+ * @param[in] base_freq Base clock frequency for timer in Hz.
+ * @param[in] frequency Desired frequency value in Hz.
+ */
+#define NRF_TIMER_PRESCALER_CALCULATE(base_freq, frequency) \
+ NRF_CTZ((uint32_t)(base_freq) / (uint32_t)(frequency))
+
+/**
+ * @brief Macro for checking whether specified frequency can be achived for given timer instance.
+ *
+ * @note Macro is using compile time assertion.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] frequency Desired frequency value in Hz.
+ */
+#define NRF_TIMER_FREQUENCY_STATIC_CHECK(p_reg, frequency) \
+ NRFX_STATIC_ASSERT( \
+ (NRF_TIMER_BASE_FREQUENCY_GET(p_reg) == frequency) || \
+ ((NRF_TIMER_BASE_FREQUENCY_GET(p_reg) % frequency == 0) && \
+ NRFX_IS_POWER_OF_TWO(NRF_TIMER_BASE_FREQUENCY_GET(p_reg) / (uint32_t)frequency) && \
+ ((NRF_TIMER_BASE_FREQUENCY_GET(p_reg) / frequency) <= (1 << NRF_TIMER_PRESCALER_MAX))), \
+ "Specified frequency can not be achived with given TIMER instance.")
+
/**
* @brief Macro for getting the number of capture/compare channels available
* in a given timer instance.
*
* @param[in] id Index of the specified timer instance.
*/
-#define NRF_TIMER_CC_CHANNEL_COUNT(id) NRFX_CONCAT_3(TIMER, id, _CC_NUM)
+#define NRF_TIMER_CC_CHANNEL_COUNT(id) NRFX_CONCAT_3(TIMER, id, _CC_NUM)
+/** @brief Symbol specifying maximum number of available compare channels. */
+#define NRF_TIMER_CC_COUNT_MAX NRFX_ARRAY_SIZE(((NRF_TIMER_Type*)0)->EVENTS_COMPARE)
+
+/** @brief Symbol for creating the interrupt bitmask for all compare channels. */
+#define NRF_TIMER_ALL_CHANNELS_INT_MASK \
+ ((uint32_t)((1 << NRF_TIMER_CC_COUNT_MAX) - 1) << TIMER_INTENSET_COMPARE0_Pos)
/** @brief Timer tasks. */
typedef enum
@@ -130,16 +261,16 @@ typedef enum
NRF_TIMER_TASK_CAPTURE1 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[1]), ///< Task for capturing the timer value on channel 1.
NRF_TIMER_TASK_CAPTURE2 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[2]), ///< Task for capturing the timer value on channel 2.
NRF_TIMER_TASK_CAPTURE3 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[3]), ///< Task for capturing the timer value on channel 3.
-#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__)
+#if NRF_TIMER_HAS_CC4
NRF_TIMER_TASK_CAPTURE4 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[4]), ///< Task for capturing the timer value on channel 4.
#endif
-#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__)
+#if NRF_TIMER_HAS_CC5
NRF_TIMER_TASK_CAPTURE5 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[5]), ///< Task for capturing the timer value on channel 5.
#endif
-#if defined(TIMER_INTENSET_COMPARE6_Msk) || defined(__NRFX_DOXYGEN__)
+#if NRF_TIMER_HAS_CC6
NRF_TIMER_TASK_CAPTURE6 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[6]), ///< Task for capturing the timer value on channel 6.
#endif
-#if defined(TIMER_INTENSET_COMPARE7_Msk) || defined(__NRFX_DOXYGEN__)
+#if NRF_TIMER_HAS_CC7
NRF_TIMER_TASK_CAPTURE7 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[7]), ///< Task for capturing the timer value on channel 7.
#endif
} nrf_timer_task_t;
@@ -151,16 +282,16 @@ typedef enum
NRF_TIMER_EVENT_COMPARE1 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[1]), ///< Event from compare channel 1.
NRF_TIMER_EVENT_COMPARE2 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[2]), ///< Event from compare channel 2.
NRF_TIMER_EVENT_COMPARE3 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[3]), ///< Event from compare channel 3.
-#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__)
+#if NRF_TIMER_HAS_CC4
NRF_TIMER_EVENT_COMPARE4 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[4]), ///< Event from compare channel 4.
#endif
-#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__)
+#if NRF_TIMER_HAS_CC5
NRF_TIMER_EVENT_COMPARE5 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[5]), ///< Event from compare channel 5.
#endif
-#if defined(TIMER_INTENSET_COMPARE6_Msk) || defined(__NRFX_DOXYGEN__)
+#if NRF_TIMER_HAS_CC6
NRF_TIMER_EVENT_COMPARE6 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[6]), ///< Event from compare channel 6.
#endif
-#if defined(TIMER_INTENSET_COMPARE7_Msk) || defined(__NRFX_DOXYGEN__)
+#if NRF_TIMER_HAS_CC7
NRF_TIMER_EVENT_COMPARE7 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[7]), ///< Event from compare channel 7.
#endif
} nrf_timer_event_t;
@@ -172,22 +303,34 @@ typedef enum
NRF_TIMER_SHORT_COMPARE1_STOP_MASK = TIMER_SHORTS_COMPARE1_STOP_Msk, ///< Shortcut for stopping the timer based on compare 1.
NRF_TIMER_SHORT_COMPARE2_STOP_MASK = TIMER_SHORTS_COMPARE2_STOP_Msk, ///< Shortcut for stopping the timer based on compare 2.
NRF_TIMER_SHORT_COMPARE3_STOP_MASK = TIMER_SHORTS_COMPARE3_STOP_Msk, ///< Shortcut for stopping the timer based on compare 3.
-#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__)
+#if NRF_TIMER_HAS_CC4
NRF_TIMER_SHORT_COMPARE4_STOP_MASK = TIMER_SHORTS_COMPARE4_STOP_Msk, ///< Shortcut for stopping the timer based on compare 4.
#endif
-#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__)
+#if NRF_TIMER_HAS_CC5
NRF_TIMER_SHORT_COMPARE5_STOP_MASK = TIMER_SHORTS_COMPARE5_STOP_Msk, ///< Shortcut for stopping the timer based on compare 5.
+#endif
+#if NRF_TIMER_HAS_CC6
+ NRF_TIMER_SHORT_COMPARE6_STOP_MASK = TIMER_SHORTS_COMPARE6_STOP_Msk, ///< Shortcut for stopping the timer based on compare 6.
+#endif
+#if NRF_TIMER_HAS_CC7
+ NRF_TIMER_SHORT_COMPARE7_STOP_MASK = TIMER_SHORTS_COMPARE7_STOP_Msk, ///< Shortcut for stopping the timer based on compare 7.
#endif
NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK = TIMER_SHORTS_COMPARE0_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 0.
NRF_TIMER_SHORT_COMPARE1_CLEAR_MASK = TIMER_SHORTS_COMPARE1_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 1.
NRF_TIMER_SHORT_COMPARE2_CLEAR_MASK = TIMER_SHORTS_COMPARE2_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 2.
NRF_TIMER_SHORT_COMPARE3_CLEAR_MASK = TIMER_SHORTS_COMPARE3_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 3.
-#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__)
+#if NRF_TIMER_HAS_CC4
NRF_TIMER_SHORT_COMPARE4_CLEAR_MASK = TIMER_SHORTS_COMPARE4_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 4.
#endif
-#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__)
+#if NRF_TIMER_HAS_CC5
NRF_TIMER_SHORT_COMPARE5_CLEAR_MASK = TIMER_SHORTS_COMPARE5_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 5.
#endif
+#if NRF_TIMER_HAS_CC6
+ NRF_TIMER_SHORT_COMPARE6_CLEAR_MASK = TIMER_SHORTS_COMPARE6_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 6.
+#endif
+#if NRF_TIMER_HAS_CC7
+ NRF_TIMER_SHORT_COMPARE7_CLEAR_MASK = TIMER_SHORTS_COMPARE7_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 7.
+#endif
} nrf_timer_short_mask_t;
/** @brief Timer modes. */
@@ -195,7 +338,7 @@ typedef enum
{
NRF_TIMER_MODE_TIMER = TIMER_MODE_MODE_Timer, ///< Timer mode: timer.
NRF_TIMER_MODE_COUNTER = TIMER_MODE_MODE_Counter, ///< Timer mode: counter.
-#if defined(TIMER_MODE_MODE_LowPowerCounter) || defined(__NRFX_DOXYGEN__)
+#if NRF_TIMER_HAS_LOW_POWER_MODE
NRF_TIMER_MODE_LOW_POWER_COUNTER = TIMER_MODE_MODE_LowPowerCounter, ///< Timer mode: low-power counter.
#endif
} nrf_timer_mode_t;
@@ -231,12 +374,18 @@ typedef enum
NRF_TIMER_CC_CHANNEL1, ///< Timer capture/compare channel 1.
NRF_TIMER_CC_CHANNEL2, ///< Timer capture/compare channel 2.
NRF_TIMER_CC_CHANNEL3, ///< Timer capture/compare channel 3.
-#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__)
+#if NRF_TIMER_HAS_CC4
NRF_TIMER_CC_CHANNEL4, ///< Timer capture/compare channel 4.
#endif
-#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__)
+#if NRF_TIMER_HAS_CC5
NRF_TIMER_CC_CHANNEL5, ///< Timer capture/compare channel 5.
#endif
+#if NRF_TIMER_HAS_CC6
+ NRF_TIMER_CC_CHANNEL6, ///< Timer capture/compare channel 6.
+#endif
+#if NRF_TIMER_HAS_CC7
+ NRF_TIMER_CC_CHANNEL7, ///< Timer capture/compare channel 7.
+#endif
} nrf_timer_cc_channel_t;
/** @brief Timer interrupts. */
@@ -246,15 +395,40 @@ typedef enum
NRF_TIMER_INT_COMPARE1_MASK = TIMER_INTENSET_COMPARE1_Msk, ///< Timer interrupt from compare event on channel 1.
NRF_TIMER_INT_COMPARE2_MASK = TIMER_INTENSET_COMPARE2_Msk, ///< Timer interrupt from compare event on channel 2.
NRF_TIMER_INT_COMPARE3_MASK = TIMER_INTENSET_COMPARE3_Msk, ///< Timer interrupt from compare event on channel 3.
-#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__)
+#if NRF_TIMER_HAS_CC4
NRF_TIMER_INT_COMPARE4_MASK = TIMER_INTENSET_COMPARE4_Msk, ///< Timer interrupt from compare event on channel 4.
#endif
-#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__)
+#if NRF_TIMER_HAS_CC5
NRF_TIMER_INT_COMPARE5_MASK = TIMER_INTENSET_COMPARE5_Msk, ///< Timer interrupt from compare event on channel 5.
#endif
+#if NRF_TIMER_HAS_CC6
+ NRF_TIMER_INT_COMPARE6_MASK = TIMER_INTENSET_COMPARE6_Msk, ///< Timer interrupt from compare event on channel 6.
+#endif
+#if NRF_TIMER_HAS_CC7
+ NRF_TIMER_INT_COMPARE7_MASK = TIMER_INTENSET_COMPARE7_Msk, ///< Timer interrupt from compare event on channel 7.
+#endif
} nrf_timer_int_mask_t;
+/**
+ * @brief Function for setting the prescaler factor.
+ *
+ * @note Prescaler value is expressed as \f$ 2^{prescaler\_factor} \f$.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] prescaler_factor Prescaler factor.
+ */
+NRF_STATIC_INLINE void nrf_timer_prescaler_set(NRF_TIMER_Type * p_reg, uint32_t prescaler_factor);
+
+/**
+ * @brief Function for retrieving the prescaler factor.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return Prescaler factor.
+ */
+NRF_STATIC_INLINE uint32_t nrf_timer_prescaler_get(NRF_TIMER_Type const * p_reg);
+
/**
* @brief Function for activating the specified timer task.
*
@@ -334,6 +508,24 @@ NRF_STATIC_INLINE void nrf_timer_shorts_disable(NRF_TIMER_Type * p_reg,
NRF_STATIC_INLINE void nrf_timer_shorts_set(NRF_TIMER_Type * p_reg,
uint32_t mask);
+/**
+ * @brief Function for getting COMPARE_CLEAR short mask for the specified channel.
+ *
+ * @param[in] channel Channel.
+ *
+ * @return Short mask.
+ */
+NRF_STATIC_INLINE nrf_timer_short_mask_t nrf_timer_short_compare_clear_get(uint8_t channel);
+
+/**
+ * @brief Function for getting COMPARE_STOP short mask for the specified channel.
+ *
+ * @param[in] channel Channel.
+ *
+ * @return Short mask.
+ */
+NRF_STATIC_INLINE nrf_timer_short_mask_t nrf_timer_short_compare_stop_get(uint8_t channel);
+
/**
* @brief Function for enabling the specified interrupts.
*
@@ -444,24 +636,6 @@ NRF_STATIC_INLINE void nrf_timer_bit_width_set(NRF_TIMER_Type * p_reg,
*/
NRF_STATIC_INLINE nrf_timer_bit_width_t nrf_timer_bit_width_get(NRF_TIMER_Type const * p_reg);
-/**
- * @brief Function for setting the timer frequency.
- *
- * @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] frequency Timer frequency.
- */
-NRF_STATIC_INLINE void nrf_timer_frequency_set(NRF_TIMER_Type * p_reg,
- nrf_timer_frequency_t frequency);
-
-/**
- * @brief Function for retrieving the timer frequency.
- *
- * @param[in] p_reg Pointer to the structure of registers of the peripheral.
- *
- * @return Timer frequency.
- */
-NRF_STATIC_INLINE nrf_timer_frequency_t nrf_timer_frequency_get(NRF_TIMER_Type const * p_reg);
-
/**
* @brief Function for setting the capture/compare register for the specified channel.
*
@@ -491,7 +665,7 @@ NRF_STATIC_INLINE uint32_t nrf_timer_cc_get(NRF_TIMER_Type const * p_reg,
*
* @return Capture task.
*/
-NRF_STATIC_INLINE nrf_timer_task_t nrf_timer_capture_task_get(uint32_t channel);
+NRF_STATIC_INLINE nrf_timer_task_t nrf_timer_capture_task_get(uint8_t channel);
/**
* @brief Function for getting the specified timer compare event.
@@ -500,7 +674,7 @@ NRF_STATIC_INLINE nrf_timer_task_t nrf_timer_capture_task_get(uint32_t channel);
*
* @return Compare event.
*/
-NRF_STATIC_INLINE nrf_timer_event_t nrf_timer_compare_event_get(uint32_t channel);
+NRF_STATIC_INLINE nrf_timer_event_t nrf_timer_compare_event_get(uint8_t channel);
/**
* @brief Function for getting the specified timer compare interrupt.
@@ -509,7 +683,7 @@ NRF_STATIC_INLINE nrf_timer_event_t nrf_timer_compare_event_get(uint32_t channel
*
* @return Compare interrupt.
*/
-NRF_STATIC_INLINE nrf_timer_int_mask_t nrf_timer_compare_int_get(uint32_t channel);
+NRF_STATIC_INLINE nrf_timer_int_mask_t nrf_timer_compare_int_get(uint8_t channel);
/**
* @brief Function for calculating the number of timer ticks for a given time
@@ -535,7 +709,7 @@ NRF_STATIC_INLINE uint32_t nrf_timer_us_to_ticks(uint32_t time_us,
NRF_STATIC_INLINE uint32_t nrf_timer_ms_to_ticks(uint32_t time_ms,
nrf_timer_frequency_t frequency);
-#if defined(TIMER_ONESHOTEN_ONESHOTEN_Msk) || defined(__NRFX_DOXYGEN__)
+#if NRF_TIMER_HAS_ONE_SHOT
/**
* @brief Function for enabling one-shot operation for the specified capture/compare channel.
*
@@ -554,7 +728,7 @@ NRF_STATIC_INLINE void nrf_timer_one_shot_enable(NRF_TIMER_Type * p_reg,
NRF_STATIC_INLINE void nrf_timer_one_shot_disable(NRF_TIMER_Type * p_reg,
nrf_timer_cc_channel_t cc_channel);
-#endif // defined(TIMER_ONESHOTEN_ONESHOTEN_Msk) || defined(__NRFX_DOXYGEN__)
+#endif // NRF_TIMER_HAS_ONE_SHOT
#ifndef NRF_DECLARE_ONLY
@@ -607,6 +781,16 @@ NRF_STATIC_INLINE void nrf_timer_shorts_set(NRF_TIMER_Type * p_reg,
p_reg->SHORTS = mask;
}
+NRF_STATIC_INLINE nrf_timer_short_mask_t nrf_timer_short_compare_clear_get(uint8_t channel)
+{
+ return (nrf_timer_short_mask_t)((uint32_t)NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK << channel);
+}
+
+NRF_STATIC_INLINE nrf_timer_short_mask_t nrf_timer_short_compare_stop_get(uint8_t channel)
+{
+ return (nrf_timer_short_mask_t)((uint32_t)NRF_TIMER_SHORT_COMPARE0_STOP_MASK << channel);
+}
+
NRF_STATIC_INLINE void nrf_timer_int_enable(NRF_TIMER_Type * p_reg,
uint32_t mask)
{
@@ -630,7 +814,7 @@ NRF_STATIC_INLINE void nrf_timer_subscribe_set(NRF_TIMER_Type * p_reg,
uint8_t channel)
{
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
- ((uint32_t)channel | TIMER_SUBSCRIBE_START_EN_Msk);
+ ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
}
NRF_STATIC_INLINE void nrf_timer_subscribe_clear(NRF_TIMER_Type * p_reg,
@@ -644,7 +828,7 @@ NRF_STATIC_INLINE void nrf_timer_publish_set(NRF_TIMER_Type * p_reg,
uint8_t channel)
{
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
- ((uint32_t)channel | TIMER_PUBLISH_COMPARE_EN_Msk);
+ ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
}
NRF_STATIC_INLINE void nrf_timer_publish_clear(NRF_TIMER_Type * p_reg,
@@ -679,17 +863,15 @@ NRF_STATIC_INLINE nrf_timer_bit_width_t nrf_timer_bit_width_get(NRF_TIMER_Type c
return (nrf_timer_bit_width_t)(p_reg->BITMODE);
}
-NRF_STATIC_INLINE void nrf_timer_frequency_set(NRF_TIMER_Type * p_reg,
- nrf_timer_frequency_t frequency)
+NRF_STATIC_INLINE void nrf_timer_prescaler_set(NRF_TIMER_Type * p_reg, uint32_t prescaler_factor)
{
- p_reg->PRESCALER = (p_reg->PRESCALER & ~TIMER_PRESCALER_PRESCALER_Msk) |
- ((frequency << TIMER_PRESCALER_PRESCALER_Pos) &
- TIMER_PRESCALER_PRESCALER_Msk);
+ NRFX_ASSERT(prescaler_factor <= NRF_TIMER_PRESCALER_MAX);
+ p_reg->PRESCALER = prescaler_factor;
}
-NRF_STATIC_INLINE nrf_timer_frequency_t nrf_timer_frequency_get(NRF_TIMER_Type const * p_reg)
+NRF_STATIC_INLINE uint32_t nrf_timer_prescaler_get(NRF_TIMER_Type const * p_reg)
{
- return (nrf_timer_frequency_t)(p_reg->PRESCALER);
+ return p_reg->PRESCALER;
}
NRF_STATIC_INLINE void nrf_timer_cc_set(NRF_TIMER_Type * p_reg,
@@ -705,17 +887,17 @@ NRF_STATIC_INLINE uint32_t nrf_timer_cc_get(NRF_TIMER_Type const * p_reg,
return (uint32_t)p_reg->CC[cc_channel];
}
-NRF_STATIC_INLINE nrf_timer_task_t nrf_timer_capture_task_get(uint32_t channel)
+NRF_STATIC_INLINE nrf_timer_task_t nrf_timer_capture_task_get(uint8_t channel)
{
return (nrf_timer_task_t)NRFX_OFFSETOF(NRF_TIMER_Type, TASKS_CAPTURE[channel]);
}
-NRF_STATIC_INLINE nrf_timer_event_t nrf_timer_compare_event_get(uint32_t channel)
+NRF_STATIC_INLINE nrf_timer_event_t nrf_timer_compare_event_get(uint8_t channel)
{
return (nrf_timer_event_t)NRFX_OFFSETOF(NRF_TIMER_Type, EVENTS_COMPARE[channel]);
}
-NRF_STATIC_INLINE nrf_timer_int_mask_t nrf_timer_compare_int_get(uint32_t channel)
+NRF_STATIC_INLINE nrf_timer_int_mask_t nrf_timer_compare_int_get(uint8_t channel)
{
return (nrf_timer_int_mask_t)
((uint32_t)NRF_TIMER_INT_COMPARE0_MASK << channel);
@@ -743,7 +925,7 @@ NRF_STATIC_INLINE uint32_t nrf_timer_ms_to_ticks(uint32_t time_ms,
return (uint32_t)ticks;
}
-#if defined(TIMER_ONESHOTEN_ONESHOTEN_Msk)
+#if NRF_TIMER_HAS_ONE_SHOT
NRF_STATIC_INLINE void nrf_timer_one_shot_enable(NRF_TIMER_Type * p_reg,
nrf_timer_cc_channel_t cc_channel)
{
@@ -755,7 +937,7 @@ NRF_STATIC_INLINE void nrf_timer_one_shot_disable(NRF_TIMER_Type * p_reg,
{
p_reg->ONESHOTEN[cc_channel] = 0;
}
-#endif // defined(TIMER_ONESHOTEN_ONESHOTEN_Msk)
+#endif // NRF_TIMER_HAS_ONE_SHOT
#endif // NRF_DECLARE_ONLY
diff --git a/mcu/nrf/common/vendor/hal/nrf_uarte.h b/mcu/nrf/common/vendor/hal/nrf_uarte.h
index 33714431..1aecb3a2 100644
--- a/mcu/nrf/common/vendor/hal/nrf_uarte.h
+++ b/mcu/nrf/common/vendor/hal/nrf_uarte.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA
+ * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -49,30 +49,68 @@ extern "C" {
* @brief Hardware access layer for managing the UARTE peripheral.
*/
+/**
+ * @brief Macro getting pointer to the structure of registers of the UARTE peripheral.
+ *
+ * @param[in] idx UARTE instance index.
+ *
+ * @return Pointer to the structure of registers of the UARTE peripheral.
+ */
+#define NRF_UARTE_INST_GET(idx) NRFX_CONCAT_2(NRF_UARTE, idx)
+
+#if defined(UARTE_DMA_RX_PTR_PTR_Msk) || defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether dedicated DMA register is present. */
+#define NRF_UARTE_HAS_DMA_REG 1
+#else
+#define NRF_UARTE_HAS_DMA_REG 0
+#endif
+
+#if (defined(UARTE_TASKS_DMA_RX_START_START_Msk) && defined(UARTE_EVENTS_DMA_RX_END_END_Msk)) || \
+ defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether UARTE DMA tasks and events are present. */
+#define NRF_UARTE_HAS_DMA_TASKS_EVENTS 1
+#else
+#define NRF_UARTE_HAS_DMA_TASKS_EVENTS 0
+#endif
+
/** @brief UARTE tasks. */
typedef enum
{
- NRF_UARTE_TASK_STARTRX = offsetof(NRF_UARTE_Type, TASKS_STARTRX), ///< Start UART receiver.
- NRF_UARTE_TASK_STOPRX = offsetof(NRF_UARTE_Type, TASKS_STOPRX), ///< Stop UART receiver.
- NRF_UARTE_TASK_STARTTX = offsetof(NRF_UARTE_Type, TASKS_STARTTX), ///< Start UART transmitter.
- NRF_UARTE_TASK_STOPTX = offsetof(NRF_UARTE_Type, TASKS_STOPTX), ///< Stop UART transmitter.
- NRF_UARTE_TASK_FLUSHRX = offsetof(NRF_UARTE_Type, TASKS_FLUSHRX) ///< Flush RX FIFO in RX buffer.
+#if NRF_UARTE_HAS_DMA_TASKS_EVENTS
+ NRF_UARTE_TASK_STARTRX = offsetof(NRF_UARTE_Type, TASKS_DMA.RX.START), ///< Start UART receiver.
+ NRF_UARTE_TASK_STOPRX = offsetof(NRF_UARTE_Type, TASKS_DMA.RX.STOP), ///< Stop UART receiver.
+ NRF_UARTE_TASK_STARTTX = offsetof(NRF_UARTE_Type, TASKS_DMA.TX.START), ///< Start UART transmitter.
+ NRF_UARTE_TASK_STOPTX = offsetof(NRF_UARTE_Type, TASKS_DMA.TX.STOP), ///< Stop UART transmitter.
+#else
+ NRF_UARTE_TASK_STARTRX = offsetof(NRF_UARTE_Type, TASKS_STARTRX), ///< Start UART receiver.
+ NRF_UARTE_TASK_STOPRX = offsetof(NRF_UARTE_Type, TASKS_STOPRX), ///< Stop UART receiver.
+ NRF_UARTE_TASK_STARTTX = offsetof(NRF_UARTE_Type, TASKS_STARTTX), ///< Start UART transmitter.
+ NRF_UARTE_TASK_STOPTX = offsetof(NRF_UARTE_Type, TASKS_STOPTX), ///< Stop UART transmitter.
+#endif
+ NRF_UARTE_TASK_FLUSHRX = offsetof(NRF_UARTE_Type, TASKS_FLUSHRX) ///< Flush RX FIFO in RX buffer.
} nrf_uarte_task_t;
/** @brief UARTE events. */
typedef enum
{
- NRF_UARTE_EVENT_CTS = offsetof(NRF_UARTE_Type, EVENTS_CTS), ///< CTS is activated.
- NRF_UARTE_EVENT_NCTS = offsetof(NRF_UARTE_Type, EVENTS_NCTS), ///< CTS is deactivated.
- NRF_UARTE_EVENT_RXDRDY = offsetof(NRF_UARTE_Type, EVENTS_RXDRDY), ///< Data received in RXD (but potentially not yet transferred to Data RAM).
- NRF_UARTE_EVENT_ENDRX = offsetof(NRF_UARTE_Type, EVENTS_ENDRX), ///< Receive buffer is filled up.
- NRF_UARTE_EVENT_TXDRDY = offsetof(NRF_UARTE_Type, EVENTS_TXDRDY), ///< Data sent from TXD.
- NRF_UARTE_EVENT_ENDTX = offsetof(NRF_UARTE_Type, EVENTS_ENDTX), ///< Last TX byte transmitted.
- NRF_UARTE_EVENT_ERROR = offsetof(NRF_UARTE_Type, EVENTS_ERROR), ///< Error detected.
- NRF_UARTE_EVENT_RXTO = offsetof(NRF_UARTE_Type, EVENTS_RXTO), ///< Receiver timeout.
- NRF_UARTE_EVENT_RXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_RXSTARTED), ///< Receiver has started.
- NRF_UARTE_EVENT_TXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_TXSTARTED), ///< Transmitter has started.
- NRF_UARTE_EVENT_TXSTOPPED = offsetof(NRF_UARTE_Type, EVENTS_TXSTOPPED) ///< Transmitted stopped.
+ NRF_UARTE_EVENT_CTS = offsetof(NRF_UARTE_Type, EVENTS_CTS), ///< CTS is activated.
+ NRF_UARTE_EVENT_NCTS = offsetof(NRF_UARTE_Type, EVENTS_NCTS), ///< CTS is deactivated.
+ NRF_UARTE_EVENT_RXDRDY = offsetof(NRF_UARTE_Type, EVENTS_RXDRDY), ///< Data received in RXD (but potentially not yet transferred to Data RAM).
+ NRF_UARTE_EVENT_TXDRDY = offsetof(NRF_UARTE_Type, EVENTS_TXDRDY), ///< Data sent from TXD.
+ NRF_UARTE_EVENT_ERROR = offsetof(NRF_UARTE_Type, EVENTS_ERROR), ///< Error detected.
+ NRF_UARTE_EVENT_RXTO = offsetof(NRF_UARTE_Type, EVENTS_RXTO), ///< Receiver timeout.
+ NRF_UARTE_EVENT_TXSTOPPED = offsetof(NRF_UARTE_Type, EVENTS_TXSTOPPED), ///< Transmitted stopped.
+#if NRF_UARTE_HAS_DMA_TASKS_EVENTS
+ NRF_UARTE_EVENT_ENDRX = offsetof(NRF_UARTE_Type, EVENTS_DMA.RX.END), ///< Receive buffer is filled up.
+ NRF_UARTE_EVENT_ENDTX = offsetof(NRF_UARTE_Type, EVENTS_DMA.TX.END), ///< Last TX byte transmitted.
+ NRF_UARTE_EVENT_RXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_DMA.RX.READY), ///< Receiver has started.
+ NRF_UARTE_EVENT_TXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_DMA.TX.READY), ///< Transmitter has started.
+#else
+ NRF_UARTE_EVENT_ENDRX = offsetof(NRF_UARTE_Type, EVENTS_ENDRX), ///< Receive buffer is filled up.
+ NRF_UARTE_EVENT_ENDTX = offsetof(NRF_UARTE_Type, EVENTS_ENDTX), ///< Last TX byte transmitted.
+ NRF_UARTE_EVENT_RXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_RXSTARTED), ///< Receiver has started.
+ NRF_UARTE_EVENT_TXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_TXSTARTED), ///< Transmitter has started.
+#endif
} nrf_uarte_event_t;
/** @brief Types of UARTE shortcuts. */
@@ -86,17 +124,24 @@ typedef enum
/** @brief UARTE interrupts. */
typedef enum
{
- NRF_UARTE_INT_CTS_MASK = UARTE_INTENSET_CTS_Msk, ///< Interrupt on CTS event.
- NRF_UARTE_INT_NCTS_MASK = UARTE_INTENSET_NCTS_Msk, ///< Interrupt on NCTS event.
- NRF_UARTE_INT_RXDRDY_MASK = UARTE_INTENSET_RXDRDY_Msk, ///< Interrupt on RXDRDY event.
- NRF_UARTE_INT_ENDRX_MASK = UARTE_INTENSET_ENDRX_Msk, ///< Interrupt on ENDRX event.
- NRF_UARTE_INT_TXDRDY_MASK = UARTE_INTENSET_TXDRDY_Msk, ///< Interrupt on TXDRDY event.
- NRF_UARTE_INT_ENDTX_MASK = UARTE_INTENSET_ENDTX_Msk, ///< Interrupt on ENDTX event.
- NRF_UARTE_INT_ERROR_MASK = UARTE_INTENSET_ERROR_Msk, ///< Interrupt on ERROR event.
- NRF_UARTE_INT_RXTO_MASK = UARTE_INTENSET_RXTO_Msk, ///< Interrupt on RXTO event.
- NRF_UARTE_INT_RXSTARTED_MASK = UARTE_INTENSET_RXSTARTED_Msk, ///< Interrupt on RXSTARTED event.
- NRF_UARTE_INT_TXSTARTED_MASK = UARTE_INTENSET_TXSTARTED_Msk, ///< Interrupt on TXSTARTED event.
- NRF_UARTE_INT_TXSTOPPED_MASK = UARTE_INTENSET_TXSTOPPED_Msk ///< Interrupt on TXSTOPPED event.
+ NRF_UARTE_INT_CTS_MASK = UARTE_INTENSET_CTS_Msk, ///< Interrupt on CTS event.
+ NRF_UARTE_INT_NCTS_MASK = UARTE_INTENSET_NCTS_Msk, ///< Interrupt on NCTS event.
+ NRF_UARTE_INT_RXDRDY_MASK = UARTE_INTENSET_RXDRDY_Msk, ///< Interrupt on RXDRDY event.
+ NRF_UARTE_INT_TXDRDY_MASK = UARTE_INTENSET_TXDRDY_Msk, ///< Interrupt on TXDRDY event.
+ NRF_UARTE_INT_ERROR_MASK = UARTE_INTENSET_ERROR_Msk, ///< Interrupt on ERROR event.
+ NRF_UARTE_INT_RXTO_MASK = UARTE_INTENSET_RXTO_Msk, ///< Interrupt on RXTO event.
+ NRF_UARTE_INT_TXSTOPPED_MASK = UARTE_INTENSET_TXSTOPPED_Msk, ///< Interrupt on TXSTOPPED event.
+#if NRF_UARTE_HAS_DMA_TASKS_EVENTS
+ NRF_UARTE_INT_ENDRX_MASK = UARTE_INTENSET_DMARXEND_Msk, ///< Interrupt on ENDRX event.
+ NRF_UARTE_INT_ENDTX_MASK = UARTE_INTENSET_DMATXEND_Msk, ///< Interrupt on ENDTX event.
+ NRF_UARTE_INT_RXSTARTED_MASK = UARTE_INTENSET_DMARXREADY_Msk, ///< Interrupt on RXSTARTED event.
+ NRF_UARTE_INT_TXSTARTED_MASK = UARTE_INTENSET_DMATXREADY_Msk, ///< Interrupt on TXSTARTED event.
+#else
+ NRF_UARTE_INT_ENDRX_MASK = UARTE_INTENSET_ENDRX_Msk, ///< Interrupt on ENDRX event.
+ NRF_UARTE_INT_ENDTX_MASK = UARTE_INTENSET_ENDTX_Msk, ///< Interrupt on ENDTX event.
+ NRF_UARTE_INT_RXSTARTED_MASK = UARTE_INTENSET_RXSTARTED_Msk, ///< Interrupt on RXSTARTED event.
+ NRF_UARTE_INT_TXSTARTED_MASK = UARTE_INTENSET_TXSTARTED_Msk, ///< Interrupt on TXSTARTED event.
+#endif
} nrf_uarte_int_mask_t;
/** @brief Baudrates supported by UARTE. */
@@ -517,7 +562,7 @@ NRF_STATIC_INLINE void nrf_uarte_subscribe_set(NRF_UARTE_Type * p_reg,
uint8_t channel)
{
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
- ((uint32_t)channel | UARTE_SUBSCRIBE_STARTRX_EN_Msk);
+ ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
}
NRF_STATIC_INLINE void nrf_uarte_subscribe_clear(NRF_UARTE_Type * p_reg,
@@ -531,7 +576,7 @@ NRF_STATIC_INLINE void nrf_uarte_publish_set(NRF_UARTE_Type * p_reg,
uint8_t channel)
{
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
- ((uint32_t)channel | UARTE_PUBLISH_CTS_EN_Msk);
+ ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
}
NRF_STATIC_INLINE void nrf_uarte_publish_clear(NRF_UARTE_Type * p_reg,
@@ -637,26 +682,44 @@ NRF_STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
uint8_t const * p_buffer,
size_t length)
{
+#if NRF_UARTE_HAS_DMA_REG
+ p_reg->DMA.TX.PTR = (uint32_t)p_buffer;
+ p_reg->DMA.TX.MAXCNT = length;
+#else
p_reg->TXD.PTR = (uint32_t)p_buffer;
p_reg->TXD.MAXCNT = length;
+#endif
}
NRF_STATIC_INLINE uint32_t nrf_uarte_tx_amount_get(NRF_UARTE_Type const * p_reg)
{
+#if NRF_UARTE_HAS_DMA_REG
+ return p_reg->DMA.TX.AMOUNT;
+#else
return p_reg->TXD.AMOUNT;
+#endif
}
NRF_STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
uint8_t * p_buffer,
size_t length)
{
+#if NRF_UARTE_HAS_DMA_REG
+ p_reg->DMA.RX.PTR = (uint32_t)p_buffer;
+ p_reg->DMA.RX.MAXCNT = length;
+#else
p_reg->RXD.PTR = (uint32_t)p_buffer;
p_reg->RXD.MAXCNT = length;
+#endif
}
NRF_STATIC_INLINE uint32_t nrf_uarte_rx_amount_get(NRF_UARTE_Type const * p_reg)
{
+#if NRF_UARTE_HAS_DMA_REG
+ return p_reg->DMA.RX.AMOUNT;
+#else
return p_reg->RXD.AMOUNT;
+#endif
}
#endif // NRF_DECLARE_ONLY
diff --git a/mcu/nrf/common/vendor/haly/nrfy_common.h b/mcu/nrf/common/vendor/haly/nrfy_common.h
new file mode 100644
index 00000000..203502f1
--- /dev/null
+++ b/mcu/nrf/common/vendor/haly/nrfy_common.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2021 - 2023, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRFY_COMMON_H__
+#define NRFY_COMMON_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup nrfy_common Common nrfy module
+ * @{
+ * @ingroup nrfx
+ * @brief Common nrfy module.
+ */
+
+/**
+ * @brief Macro for calculating interrupt bit position associated with the specified event.
+ *
+ * @param[in] event Event.
+ *
+ * @return Interrupt bit position.
+ */
+#define NRFY_EVENT_TO_INT_BITPOS(event) ((((uint32_t)event) - 0x100) >> 2)
+
+/**
+ * @brief Macro for calculating interrupt bitmask associated with the specified event.
+ *
+ * @param[in] event Event.
+ *
+ * @return Interrupt bitmask.
+ */
+#define NRFY_EVENT_TO_INT_BITMASK(event) (1 << NRFY_EVENT_TO_INT_BITPOS(event))
+
+/** @sa NRFX_IRQ_PRIORITY_SET */
+#define NRFY_IRQ_PRIORITY_SET(irq_number, priority) NRFX_IRQ_PRIORITY_SET(irq_number, priority)
+
+/** @sa NRFX_IRQ_ENABLE */
+#define NRFY_IRQ_ENABLE(irq_number) NRFX_IRQ_ENABLE(irq_number)
+
+/** @sa NRFX_IRQ_IS_ENABLED */
+#define NRFY_IRQ_IS_ENABLED(irq_number) NRFX_IRQ_IS_ENABLED(irq_number)
+
+/** @sa NRFX_IRQ_DISABLE */
+#define NRFY_IRQ_DISABLE(irq_number) NRFX_IRQ_DISABLE(irq_number)
+
+/** @sa NRFX_IRQ_PENDING_SET */
+#define NRFY_IRQ_PENDING_SET(irq_number) NRFX_IRQ_PENDING_SET(irq_number)
+
+/** @sa NRFX_IRQ_PENDING_CLEAR */
+#define NRFY_IRQ_PENDING_CLEAR(irq_number) NRFX_IRQ_PENDING_CLEAR(irq_number)
+
+/** @sa NRFX_IRQ_IS_PENDING */
+#define NRFY_IRQ_IS_PENDING(irq_number) NRFX_IRQ_IS_PENDING(irq_number)
+
+/** @sa NRFX_CRITICAL_SECTION_ENTER */
+#define NRFY_CRITICAL_SECTION_ENTER() NRFX_CRITICAL_SECTION_ENTER()
+
+/** @sa NRFX_CRITICAL_SECTION_EXIT */
+#define NRFY_CRITICAL_SECTION_EXIT() NRFX_CRITICAL_SECTION_EXIT()
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRFY_COMMON_H__
diff --git a/mcu/nrf/common/vendor/mdk/compiler_abstraction.h b/mcu/nrf/common/vendor/mdk/compiler_abstraction.h
index b687bfab..628faf50 100644
--- a/mcu/nrf/common/vendor/mdk/compiler_abstraction.h
+++ b/mcu/nrf/common/vendor/mdk/compiler_abstraction.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
+Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
@@ -57,7 +57,7 @@ POSSIBILITY OF SUCH DAMAGE.
#ifndef __WEAK
#define __WEAK __weak
#endif
-
+
#ifndef __ALIGN
#define __ALIGN(n) __align(n)
#endif
@@ -70,8 +70,48 @@ POSSIBILITY OF SUCH DAMAGE.
#define __UNUSED __attribute__((unused))
#endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+
+ #ifndef __HANDLER
+ #define __HANDLER(handler)
+ #endif
+
#define GET_SP() __current_sp()
+ #ifndef __DEPRECATED
+ #define __DEPRECATED(msg) __attribute__((deprecated(msg)))
+ #endif
+
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __declspec(noreturn)
+ #endif
+
+ #ifndef __RESET_HANDLER_ATTRIBUTE
+ #define __RESET_HANDLER_ATTRIBUTE __NO_RETURN
+ #endif
+
+ #ifndef __START
+ #define __START __main
+ #endif
+
+ #ifndef __VECTOR_TABLE
+ #define __VECTOR_TABLE __Vectors
+ #endif
+
+ #ifndef __VECTOR_TABLE_ATTRIBUTE
+ #define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
+ #endif
+
+ #ifndef __STACK_ATTRIBUTES
+ #define __STACK_ATTRIBUTES(align)
+ #endif
+
+ #ifndef __HEAP_ATTRIBUTES
+ #define __HEAP_ATTRIBUTES(align)
+ #endif
+
#ifndef NRF_STATIC_ASSERT
#define NRF_STATIC_ASSERT(cond, msg) \
;enum { NRF_STRING_CONCATENATE(static_assert_on_line_, __LINE__) = 1 / (!!(cond)) }
@@ -103,8 +143,48 @@ POSSIBILITY OF SUCH DAMAGE.
#define __UNUSED __attribute__((unused))
#endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+
+ #ifndef __HANDLER
+ #define __HANDLER(handler) __WEAK __attribute__((alias(handler)))
+ #endif
+
#define GET_SP() __current_sp()
+ #ifndef __DEPRECATED
+ #define __DEPRECATED(msg) __attribute__((deprecated(msg)))
+ #endif
+
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+ #endif
+
+ #ifndef __RESET_HANDLER_ATTRIBUTE
+ #define __RESET_HANDLER_ATTRIBUTE __NO_RETURN
+ #endif
+
+ #ifndef __START
+ #define __START __main
+ #endif
+
+ #ifndef __VECTOR_TABLE
+ #define __VECTOR_TABLE __Vectors
+ #endif
+
+ #ifndef __VECTOR_TABLE_ATTRIBUTE
+ #define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
+ #endif
+
+ #ifndef __STACK_ATTRIBUTES
+ #define __STACK_ATTRIBUTES(align) __attribute__ ((aligned(1 << align), used, section(".stack")));
+ #endif
+
+ #ifndef __HEAP_ATTRIBUTES
+ #define __HEAP_ATTRIBUTES(align) __attribute__ ((aligned(1 << align), used, section(".heap")));
+ #endif
+
#ifndef NRF_STATIC_ASSERT
#ifdef __cplusplus
#ifndef _Static_assert
@@ -130,7 +210,7 @@ POSSIBILITY OF SUCH DAMAGE.
#if (__VER__ >= 8000000)
#ifndef __ALIGN
- #define __ALIGN(n) __attribute__((aligned(x)))
+ #define __ALIGN(n) __attribute__((aligned(n)))
#endif
#ifndef __PACKED
@@ -150,9 +230,49 @@ POSSIBILITY OF SUCH DAMAGE.
#ifndef __UNUSED
#define __UNUSED
#endif
+
+ #ifndef __USED
+ #define __USED __root
+ #endif
+
+ #ifndef __HANDLER
+ #define __HANDLER(handler) __WEAK __attribute__((alias(handler)))
+ #endif
#define GET_SP() __get_SP()
+ #ifndef __DEPRECATED
+ #define __DEPRECATED(msg) __attribute__((deprecated(msg)))
+ #endif
+
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+ #endif
+
+ #ifndef __RESET_HANDLER_ATTRIBUTE
+ #define __RESET_HANDLER_ATTRIBUTE __NO_RETURN
+ #endif
+
+ #ifndef __START
+ #define __START __iar_program_start
+ #endif
+
+ #ifndef __VECTOR_TABLE
+ #define __VECTOR_TABLE __vector_table
+ #endif
+
+ #ifndef __VECTOR_TABLE_ATTRIBUTE
+ #define __VECTOR_TABLE_ATTRIBUTE @".intvec"
+ #endif
+
+ #ifndef __STACK_ATTRIBUTES
+ #define __STACK_ATTRIBUTES(align) __attribute__ ((aligned(1 << align), used, section(".stack")));
+ #endif
+
+ #ifndef __HEAP_ATTRIBUTES
+ #define __HEAP_ATTRIBUTES(align) __attribute__ ((aligned(1 << align), used, section(".heap")));
+ #endif
+
#ifndef NRF_STATIC_ASSERT
#define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg)
#endif
@@ -166,6 +286,10 @@ POSSIBILITY OF SUCH DAMAGE.
#ifndef __INLINE
#define __INLINE inline
#endif
+
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
+ #endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
@@ -183,8 +307,48 @@ POSSIBILITY OF SUCH DAMAGE.
#define __UNUSED __attribute__((unused))
#endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+
+ #ifndef __HANDLER
+ #define __HANDLER(handler) __WEAK __attribute__((alias(handler)))
+ #endif
+
#define GET_SP() gcc_current_sp()
+ #ifndef __DEPRECATED
+ #define __DEPRECATED(msg) __attribute__((deprecated(msg)))
+ #endif
+
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+ #endif
+
+ #ifndef __RESET_HANDLER_ATTRIBUTE
+ #define __RESET_HANDLER_ATTRIBUTE __NO_RETURN __attribute__((section(".startup")))
+ #endif
+
+ #ifndef __START
+ #define __START _start
+ #endif
+
+ #ifndef __VECTOR_TABLE
+ #define __VECTOR_TABLE __Vectors
+ #endif
+
+ #ifndef __VECTOR_TABLE_ATTRIBUTE
+ #define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".isr_vector")))
+ #endif
+
+ #ifndef __STACK_ATTRIBUTES
+ #define __STACK_ATTRIBUTES(align) __attribute__ ((aligned(1 << align), used, section(".stack")));
+ #endif
+
+ #ifndef __HEAP_ATTRIBUTES
+ #define __HEAP_ATTRIBUTES(align) __attribute__ ((aligned(1 << align), used, section(".heap")));
+ #endif
+
static inline unsigned int gcc_current_sp(void)
{
unsigned int stack_pointer = 0;
@@ -228,8 +392,48 @@ POSSIBILITY OF SUCH DAMAGE.
#define __UNUSED __attribute__((unused))
#endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+
+ #ifndef __HANDLER
+ #define __HANDLER(handler) __WEAK __attribute__((alias(handler)))
+ #endif
+
#define GET_SP() __get_MSP()
+ #ifndef __DEPRECATED
+ #define __DEPRECATED(msg)
+ #endif
+
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+ #endif
+
+ #ifndef __RESET_HANDLER_ATTRIBUTE
+ #define __RESET_HANDLER_ATTRIBUTE __NO_RETURN __attribute__((section(".startup")))
+ #endif
+
+ #ifndef __START
+ #define __START _start
+ #endif
+
+ #ifndef __VECTOR_TABLE
+ #define __VECTOR_TABLE __Vectors
+ #endif
+
+ #ifndef __VECTOR_TABLE_ATTRIBUTE
+ #define __VECTOR_TABLE_ATTRIBUTE
+ #endif
+
+ #ifndef __STACK_ATTRIBUTES
+ #define __STACK_ATTRIBUTES(align)
+ #endif
+
+ #ifndef __HEAP_ATTRIBUTES
+ #define __HEAP_ATTRIBUTES(align)
+ #endif
+
#ifndef NRF_STATIC_ASSERT
#define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg)
#endif
diff --git a/mcu/nrf/common/vendor/mdk/nrf.h b/mcu/nrf/common/vendor/mdk/nrf.h
index 8a122273..a1174ca0 100644
--- a/mcu/nrf/common/vendor/mdk/nrf.h
+++ b/mcu/nrf/common/vendor/mdk/nrf.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
+Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
@@ -37,8 +37,8 @@ POSSIBILITY OF SUCH DAMAGE.
/* MDK version */
#define MDK_MAJOR_VERSION 8
-#define MDK_MINOR_VERSION 40
-#define MDK_MICRO_VERSION 2
+#define MDK_MINOR_VERSION 53
+#define MDK_MICRO_VERSION 1
/* Define coprocessor domains */
@@ -113,7 +113,7 @@ POSSIBILITY OF SUCH DAMAGE.
#endif
/* Define NRF91_SERIES for common use in nRF91 series devices. */
-#if defined (NRF9160_XXAA)
+#if defined (NRF9160_XXAA) || defined (NRF9120_XXAA)
#ifndef NRF91_SERIES
#define NRF91_SERIES
#endif
@@ -170,6 +170,12 @@ POSSIBILITY OF SUCH DAMAGE.
#include "nrf5340_application.h"
#include "nrf5340_application_bitfields.h"
#include "nrf5340_application_name_change.h"
+
+ /* Address of locations in RAM that will be used to store a NS-accessible version of FICR */
+ #if !defined(NRF_FICR_NS)
+ #define NRF_FICR_NS_BASE 0x2007F000
+ #define NRF_FICR_NS ((NRF_FICR_Type*) NRF_FICR_NS_BASE)
+ #endif
#elif defined (NRF_NETWORK)
#include "nrf5340_network.h"
#include "nrf5340_network_bitfields.h"
@@ -179,7 +185,24 @@ POSSIBILITY OF SUCH DAMAGE.
#elif defined (NRF9160_XXAA)
#include "nrf9160.h"
#include "nrf9160_bitfields.h"
- #include "nrf9160_name_change.h"
+ #include "nrf91_name_change.h"
+
+ /* Address of locations in RAM that will be used to store a NS-accessible version of FICR */
+ #if !defined(NRF_FICR_NS)
+ #define NRF_FICR_NS_BASE 0x2003E000
+ #define NRF_FICR_NS ((NRF_FICR_Type*) NRF_FICR_NS_BASE)
+ #endif
+
+#elif defined (NRF9120_XXAA)
+ #include "nrf9120.h"
+ #include "nrf9120_bitfields.h"
+ #include "nrf91_name_change.h"
+
+ /* Address of locations in RAM that will be used to store a NS-accessible version of FICR */
+ #if !defined(NRF_FICR_NS)
+ #define NRF_FICR_NS_BASE 0x2003E000
+ #define NRF_FICR_NS ((NRF_FICR_Type*) NRF_FICR_NS_BASE)
+ #endif
#else
#error "Device must be defined. See nrf.h."
diff --git a/mcu/nrf/common/vendor/mdk/nrf51_to_nrf52.h b/mcu/nrf/common/vendor/mdk/nrf51_to_nrf52.h
index 77a7588e..e17b8d72 100644
--- a/mcu/nrf/common/vendor/mdk/nrf51_to_nrf52.h
+++ b/mcu/nrf/common/vendor/mdk/nrf51_to_nrf52.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
+Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
diff --git a/mcu/nrf/common/vendor/mdk/nrf51_to_nrf52840.h b/mcu/nrf/common/vendor/mdk/nrf51_to_nrf52840.h
index c991d665..f6033f57 100644
--- a/mcu/nrf/common/vendor/mdk/nrf51_to_nrf52840.h
+++ b/mcu/nrf/common/vendor/mdk/nrf51_to_nrf52840.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
+Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
diff --git a/mcu/nrf/common/vendor/mdk/nrf52.h b/mcu/nrf/common/vendor/mdk/nrf52.h
index 6aab0ea8..86c53791 100644
--- a/mcu/nrf/common/vendor/mdk/nrf52.h
+++ b/mcu/nrf/common/vendor/mdk/nrf52.h
@@ -1,41 +1,41 @@
/*
- * Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
- * contributors may be used to endorse or promote products derived from this
- * software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
+
+SPDX-License-Identifier: BSD-3-Clause
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from this
+ software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
*
* @file nrf52.h
* @brief CMSIS HeaderFile
* @version 1
- * @date 29. April 2021
- * @note Generated by SVDConv V3.3.35 on Thursday, 29.04.2021 12:43:45
+ * @date 04. April 2023
+ * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:33
* from File 'nrf52.svd',
- * last modified on Thursday, 29.04.2021 10:43:40
+ * last modified on Tuesday, 04.04.2023 09:57:13
*/
@@ -130,6 +130,7 @@ typedef enum {
/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */
#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
+#define __INTERRUPTS_MAX 112 /*!< Top interrupt number */
#define __DSP_PRESENT 1 /*!< DSP present or not */
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
@@ -199,8 +200,7 @@ typedef struct {
__IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */
__IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */
__IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */
- __IOM uint32_t UNUSED0[3]; /*!< (@ 0x00000014) Description collection[0]: Unspecified */
-} FICR_INFO_Type; /*!< Size = 32 (0x20) */
+} FICR_INFO_Type; /*!< Size = 20 (0x14) */
/**
@@ -250,10 +250,9 @@ typedef struct {
* @brief POWER_RAM [RAM] (Unspecified)
*/
typedef struct {
- __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster[0]: RAM0 power control register */
- __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster[0]: RAM0 power control set
- register */
- __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster[0]: RAM0 power control clear
+ __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAMn power control register */
+ __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power control set register */
+ __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power control clear
register */
__IM uint32_t RESERVED;
} POWER_RAM_Type; /*!< Size = 16 (0x10) */
@@ -290,6 +289,16 @@ typedef struct {
} UARTE_TXD_Type; /*!< Size = 12 (0xc) */
+/**
+ * @brief SPI_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */
+ __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI */
+ __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO */
+} SPI_PSEL_Type; /*!< Size = 12 (0xc) */
+
+
/**
* @brief SPIM_PSEL [PSEL] (Unspecified)
*/
@@ -413,16 +422,6 @@ typedef struct {
} TWIS_TXD_Type; /*!< Size = 12 (0xc) */
-/**
- * @brief SPI_PSEL [PSEL] (Unspecified)
- */
-typedef struct {
- __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */
- __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI */
- __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO */
-} SPI_PSEL_Type; /*!< Size = 12 (0xc) */
-
-
/**
* @brief NFCT_FRAMESTATUS [FRAMESTATUS] (Unspecified)
*/
@@ -450,13 +449,13 @@ typedef struct {
/**
- * @brief SAADC_EVENTS_CH [EVENTS_CH] (Unspecified)
+ * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.)
*/
typedef struct {
- __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster[0]: Last results is equal
- or above CH[0].LIMIT.HIGH */
- __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster[0]: Last results is equal
- or below CH[0].LIMIT.LOW */
+ __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last results is equal or
+ above CH[n].LIMIT.HIGH */
+ __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last results is equal or
+ below CH[n].LIMIT.LOW */
} SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */
@@ -464,13 +463,13 @@ typedef struct {
* @brief SAADC_CH [CH] (Unspecified)
*/
typedef struct {
- __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster[0]: Input positive pin selection
- for CH[0] */
- __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster[0]: Input negative pin selection
- for CH[0] */
- __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster[0]: Input configuration for
- CH[0] */
- __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster[0]: High/low limits for event
+ __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster: Input positive pin selection
+ for CH[n] */
+ __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster: Input negative pin selection
+ for CH[n] */
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input configuration for
+ CH[n] */
+ __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster: High/low limits for event
monitoring a channel */
} SAADC_CH_Type; /*!< Size = 16 (0x10) */
@@ -500,15 +499,14 @@ typedef struct {
* @brief PWM_SEQ [SEQ] (Unspecified)
*/
typedef struct {
- __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[0]: Beginning address in
- Data RAM of this sequence */
- __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster[0]: Amount of values (duty
- cycles) in this sequence */
- __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster[0]: Amount of additional
- PWM periods between samples loaded into
- compare register */
- __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster[0]: Time added after the
- sequence */
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning address in Data
+ RAM of this sequence */
+ __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster: Amount of values (duty cycles)
+ in this sequence */
+ __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster: Amount of additional PWM
+ periods between samples loaded into compare
+ register */
+ __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster: Time added after the sequence */
__IM uint32_t RESERVED[4];
} PWM_SEQ_Type; /*!< Size = 32 (0x20) */
@@ -517,8 +515,8 @@ typedef struct {
* @brief PWM_PSEL [PSEL] (Unspecified)
*/
typedef struct {
- __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection[0]: Output pin select
- for PWM channel 0 */
+ __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection: Output pin select for
+ PWM channel n */
} PWM_PSEL_Type; /*!< Size = 16 (0x10) */
@@ -546,10 +544,8 @@ typedef struct {
* @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks)
*/
typedef struct {
- __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster[0]: Enable channel group
- 0 */
- __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster[0]: Disable channel group
- 0 */
+ __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */
+ __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */
} PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */
@@ -557,8 +553,8 @@ typedef struct {
* @brief PPI_CH [CH] (PPI Channel)
*/
typedef struct {
- __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster[0]: Channel 0 event end-point */
- __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster[0]: Channel 0 task end-point */
+ __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event end-point */
+ __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task end-point */
} PPI_CH_Type; /*!< Size = 8 (0x8) */
@@ -566,29 +562,29 @@ typedef struct {
* @brief PPI_FORK [FORK] (Fork)
*/
typedef struct {
- __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster[0]: Channel 0 task end-point */
+ __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task end-point */
} PPI_FORK_Type; /*!< Size = 4 (0x4) */
/**
- * @brief MWU_EVENTS_REGION [EVENTS_REGION] (Unspecified)
+ * @brief MWU_EVENTS_REGION [EVENTS_REGION] (Peripheral events.)
*/
typedef struct {
- __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[0]: Write access to region
- 0 detected */
- __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[0]: Read access to region
- 0 detected */
+ __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster: Write access to region n
+ detected */
+ __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster: Read access to region n
+ detected */
} MWU_EVENTS_REGION_Type; /*!< Size = 8 (0x8) */
/**
- * @brief MWU_EVENTS_PREGION [EVENTS_PREGION] (Unspecified)
+ * @brief MWU_EVENTS_PREGION [EVENTS_PREGION] (Peripheral events.)
*/
typedef struct {
- __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[0]: Write access to peripheral
- region 0 detected */
- __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[0]: Read access to peripheral
- region 0 detected */
+ __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster: Write access to peripheral
+ region n detected */
+ __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster: Read access to peripheral
+ region n detected */
} MWU_EVENTS_PREGION_Type; /*!< Size = 8 (0x8) */
@@ -596,12 +592,12 @@ typedef struct {
* @brief MWU_PERREGION [PERREGION] (Unspecified)
*/
typedef struct {
- __IOM uint32_t SUBSTATWA; /*!< (@ 0x00000000) Description cluster[0]: Source of event/interrupt
- in region 0, write access detected while
+ __IOM uint32_t SUBSTATWA; /*!< (@ 0x00000000) Description cluster: Source of event/interrupt
+ in region n, write access detected while
corresponding subregion was enabled for
watching */
- __IOM uint32_t SUBSTATRA; /*!< (@ 0x00000004) Description cluster[0]: Source of event/interrupt
- in region 0, read access detected while
+ __IOM uint32_t SUBSTATRA; /*!< (@ 0x00000004) Description cluster: Source of event/interrupt
+ in region n, read access detected while
corresponding subregion was enabled for
watching */
} MWU_PERREGION_Type; /*!< Size = 8 (0x8) */
@@ -611,10 +607,9 @@ typedef struct {
* @brief MWU_REGION [REGION] (Unspecified)
*/
typedef struct {
- __IOM uint32_t START; /*!< (@ 0x00000000) Description cluster[0]: Start address for region
- 0 */
- __IOM uint32_t END; /*!< (@ 0x00000004) Description cluster[0]: End address of region
- 0 */
+ __IOM uint32_t START; /*!< (@ 0x00000000) Description cluster: Start address for region
+ n */
+ __IOM uint32_t END; /*!< (@ 0x00000004) Description cluster: End address of region n */
__IM uint32_t RESERVED[2];
} MWU_REGION_Type; /*!< Size = 16 (0x10) */
@@ -623,10 +618,9 @@ typedef struct {
* @brief MWU_PREGION [PREGION] (Unspecified)
*/
typedef struct {
- __IM uint32_t START; /*!< (@ 0x00000000) Description cluster[0]: Reserved for future use */
- __IM uint32_t END; /*!< (@ 0x00000004) Description cluster[0]: Reserved for future use */
- __IOM uint32_t SUBS; /*!< (@ 0x00000008) Description cluster[0]: Subregions of region
- 0 */
+ __IM uint32_t START; /*!< (@ 0x00000000) Description cluster: Reserved for future use */
+ __IM uint32_t END; /*!< (@ 0x00000004) Description cluster: Reserved for future use */
+ __IOM uint32_t SUBS; /*!< (@ 0x00000008) Description cluster: Subregions of region n */
__IM uint32_t RESERVED;
} MWU_PREGION_Type; /*!< Size = 16 (0x10) */
@@ -712,17 +706,16 @@ typedef struct { /*!< (@ 0x10000000) FICR Structu
__IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */
__IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */
__IM uint32_t RESERVED1[18];
- __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection[0]: Device identifier */
+ __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection: Device identifier */
__IM uint32_t RESERVED2[6];
- __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection[0]: Encryption Root, word
- 0 */
- __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection[0]: Identity Root, word
- 0 */
+ __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection: Encryption Root, word
+ n */
+ __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection: Identity Root, word n */
__IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */
- __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection[0]: Device address 0 */
+ __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection: Device address n */
__IM uint32_t RESERVED3[21];
__IOM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */
- __IM uint32_t RESERVED4[185];
+ __IM uint32_t RESERVED4[188];
__IOM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization
coefficients */
__IM uint32_t RESERVED5[2];
@@ -741,18 +734,14 @@ typedef struct { /*!< (@ 0x10000000) FICR Structu
*/
typedef struct { /*!< (@ 0x10001000) UICR Structure */
- __IOM uint32_t UNUSED0; /*!< (@ 0x00000000) Unspecified */
- __IOM uint32_t UNUSED1; /*!< (@ 0x00000004) Unspecified */
- __IOM uint32_t UNUSED2; /*!< (@ 0x00000008) Unspecified */
- __IM uint32_t RESERVED;
- __IOM uint32_t UNUSED3; /*!< (@ 0x00000010) Unspecified */
- __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Description collection[0]: Reserved for Nordic
- firmware design */
- __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection[0]: Reserved for Nordic
- hardware design */
- __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection[0]: Reserved for customer */
+ __IM uint32_t RESERVED[5];
+ __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Description collection: Reserved for Nordic firmware
+ design */
+ __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection: Reserved for Nordic hardware
+ design */
+ __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection: Reserved for customer */
__IM uint32_t RESERVED1[64];
- __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection[0]: Mapping of the nRESET
+ __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection: Mapping of the nRESET
function (see POWER chapter for details) */
__IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */
__IOM uint32_t NFCPINS; /*!< (@ 0x0000020C) Setting of pins dedicated to NFC functionality:
@@ -796,13 +785,59 @@ typedef struct { /*!< (@ 0x40000000) BPROT Struct
__IOM uint32_t CONFIG1; /*!< (@ 0x00000604) Block protect configuration register 1 */
__IOM uint32_t DISABLEINDEBUG; /*!< (@ 0x00000608) Disable protection mechanism in debug interface
mode */
- __IOM uint32_t UNUSED0; /*!< (@ 0x0000060C) Unspecified */
+ __IM uint32_t RESERVED1;
__IOM uint32_t CONFIG2; /*!< (@ 0x00000610) Block protect configuration register 2 */
__IOM uint32_t CONFIG3; /*!< (@ 0x00000614) Block protect configuration register 3 */
} NRF_BPROT_Type; /*!< Size = 1560 (0x618) */
+/* =========================================================================================================================== */
+/* ================ CLOCK ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Clock control (CLOCK)
+ */
+
+typedef struct { /*!< (@ 0x40000000) CLOCK Structure */
+ __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK crystal oscillator */
+ __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK crystal oscillator */
+ __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source */
+ __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */
+ __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC oscillator */
+ __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */
+ __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */
+ __IM uint32_t RESERVED[57];
+ __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started */
+ __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFCLK RC oscillator complete event */
+ __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */
+ __IM uint32_t RESERVED2[124];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED3[63];
+ __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been
+ triggered */
+ __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */
+ __IM uint32_t RESERVED4;
+ __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been
+ triggered */
+ __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */
+ __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART
+ task was triggered */
+ __IM uint32_t RESERVED5[62];
+ __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */
+ __IM uint32_t RESERVED6[7];
+ __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */
+ __IM uint32_t RESERVED7[8];
+ __IOM uint32_t TRACECONFIG; /*!< (@ 0x0000055C) Clocking options for the Trace Port debug interface */
+} NRF_CLOCK_Type; /*!< Size = 1376 (0x560) */
+
+
+
/* =========================================================================================================================== */
/* ================ POWER ================ */
/* =========================================================================================================================== */
@@ -849,48 +884,32 @@ typedef struct { /*!< (@ 0x40000000) POWER Struct
/* =========================================================================================================================== */
-/* ================ CLOCK ================ */
+/* ================ P0 ================ */
/* =========================================================================================================================== */
/**
- * @brief Clock control (CLOCK)
+ * @brief GPIO Port 1 (P0)
*/
-typedef struct { /*!< (@ 0x40000000) CLOCK Structure */
- __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK crystal oscillator */
- __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK crystal oscillator */
- __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source */
- __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */
- __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC oscillator */
- __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */
- __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */
- __IM uint32_t RESERVED[57];
- __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started */
- __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */
- __IM uint32_t RESERVED1;
- __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFCLK RC oscillator complete event */
- __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */
- __IM uint32_t RESERVED2[124];
- __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
- __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
- __IM uint32_t RESERVED3[63];
- __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been
- triggered */
- __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */
- __IM uint32_t RESERVED4;
- __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been
- triggered */
- __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */
- __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART
- task was triggered */
- __IM uint32_t RESERVED5[62];
- __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */
- __IM uint32_t RESERVED6[7];
- __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */
- __IM uint32_t RESERVED7[8];
- __IOM uint32_t TRACECONFIG; /*!< (@ 0x0000055C) Clocking options for the Trace Port debug interface */
-} NRF_CLOCK_Type; /*!< Size = 1376 (0x560) */
+typedef struct { /*!< (@ 0x50000000) P0 Structure */
+ __IM uint32_t RESERVED[321];
+ __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */
+ __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */
+ __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */
+ __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */
+ __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */
+ __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */
+ __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */
+ __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that
+ have met the criteria set in the PIN_CNF[n].SENSE
+ registers */
+ __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour
+ and LDETECT mode */
+ __IM uint32_t RESERVED1[118];
+ __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection: Configuration of GPIO
+ pins */
+} NRF_GPIO_Type; /*!< Size = 1920 (0x780) */
@@ -931,7 +950,7 @@ typedef struct { /*!< (@ 0x40001000) RADIO Struct
__IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */
__IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */
__IM uint32_t RESERVED3[50];
- __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED4[64];
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
@@ -957,28 +976,78 @@ typedef struct { /*!< (@ 0x40001000) RADIO Struct
__IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */
__IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */
__IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */
- __IOM uint32_t UNUSED0; /*!< (@ 0x00000540) Unspecified */
+ __IM uint32_t RESERVED8;
__IOM uint32_t TIFS; /*!< (@ 0x00000544) Inter Frame Spacing in us */
__IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */
- __IM uint32_t RESERVED8;
+ __IM uint32_t RESERVED9;
__IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */
__IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */
- __IM uint32_t RESERVED9[2];
+ __IM uint32_t RESERVED10[2];
__IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */
- __IM uint32_t RESERVED10[39];
- __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection[0]: Device address base
- segment 0 */
- __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection[0]: Device address prefix
- 0 */
+ __IM uint32_t RESERVED11[39];
+ __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection: Device address base segment
+ n */
+ __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection: Device address prefix
+ n */
__IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */
- __IM uint32_t RESERVED11[3];
+ __IM uint32_t RESERVED12[3];
__IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */
- __IM uint32_t RESERVED12[618];
+ __IM uint32_t RESERVED13[618];
__IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */
} NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */
+/* =========================================================================================================================== */
+/* ================ UART0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Universal Asynchronous Receiver/Transmitter (UART0)
+ */
+
+typedef struct { /*!< (@ 0x40002000) UART0 Structure */
+ __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */
+ __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */
+ __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */
+ __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */
+ __IM uint32_t RESERVED[3];
+ __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */
+ __IM uint32_t RESERVED1[56];
+ __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */
+ __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */
+ __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */
+ __IM uint32_t RESERVED2[4];
+ __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */
+ __IM uint32_t RESERVED3;
+ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */
+ __IM uint32_t RESERVED4[7];
+ __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */
+ __IM uint32_t RESERVED5[46];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED6[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED7[93];
+ __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */
+ __IM uint32_t RESERVED8[31];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */
+ __IM uint32_t RESERVED9;
+ __IOM uint32_t PSELRTS; /*!< (@ 0x00000508) Pin select for RTS */
+ __IOM uint32_t PSELTXD; /*!< (@ 0x0000050C) Pin select for TXD */
+ __IOM uint32_t PSELCTS; /*!< (@ 0x00000510) Pin select for CTS */
+ __IOM uint32_t PSELRXD; /*!< (@ 0x00000514) Pin select for RXD */
+ __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */
+ __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */
+ __IM uint32_t RESERVED10;
+ __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate */
+ __IM uint32_t RESERVED11[17];
+ __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */
+} NRF_UART_Type; /*!< Size = 1392 (0x570) */
+
+
+
/* =========================================================================================================================== */
/* ================ UARTE0 ================ */
/* =========================================================================================================================== */
@@ -1014,7 +1083,7 @@ typedef struct { /*!< (@ 0x40002000) UARTE0 Struc
__IM uint32_t RESERVED6;
__IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */
__IM uint32_t RESERVED7[41];
- __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED8[63];
__IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
@@ -1039,52 +1108,32 @@ typedef struct { /*!< (@ 0x40002000) UARTE0 Struc
/* =========================================================================================================================== */
-/* ================ UART0 ================ */
+/* ================ SPI0 ================ */
/* =========================================================================================================================== */
/**
- * @brief Universal Asynchronous Receiver/Transmitter (UART0)
+ * @brief Serial Peripheral Interface 0 (SPI0)
*/
-typedef struct { /*!< (@ 0x40002000) UART0 Structure */
- __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */
- __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */
- __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */
- __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */
- __IM uint32_t RESERVED[3];
- __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */
- __IM uint32_t RESERVED1[56];
- __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */
- __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */
- __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */
- __IM uint32_t RESERVED2[4];
- __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */
- __IM uint32_t RESERVED3;
- __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */
- __IM uint32_t RESERVED4[7];
- __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */
- __IM uint32_t RESERVED5[46];
- __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
- __IM uint32_t RESERVED6[64];
+typedef struct { /*!< (@ 0x40003000) SPI0 Structure */
+ __IM uint32_t RESERVED[66];
+ __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */
+ __IM uint32_t RESERVED1[126];
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
- __IM uint32_t RESERVED7[93];
- __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */
- __IM uint32_t RESERVED8[31];
- __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */
- __IM uint32_t RESERVED9;
- __IOM uint32_t PSELRTS; /*!< (@ 0x00000508) Pin select for RTS */
- __IOM uint32_t PSELTXD; /*!< (@ 0x0000050C) Pin select for TXD */
- __IOM uint32_t PSELCTS; /*!< (@ 0x00000510) Pin select for CTS */
- __IOM uint32_t PSELRXD; /*!< (@ 0x00000514) Pin select for RXD */
+ __IM uint32_t RESERVED2[125];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */
+ __IM uint32_t RESERVED3;
+ __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
+ __IM uint32_t RESERVED4;
__IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */
- __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */
- __IM uint32_t RESERVED10;
- __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate */
- __IM uint32_t RESERVED11[17];
- __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */
-} NRF_UART_Type; /*!< Size = 1392 (0x570) */
+ __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency */
+ __IM uint32_t RESERVED6[11];
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */
+} NRF_SPI_Type; /*!< Size = 1368 (0x558) */
@@ -1115,7 +1164,7 @@ typedef struct { /*!< (@ 0x40003000) SPIM0 Struct
__IM uint32_t RESERVED6[10];
__IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */
__IM uint32_t RESERVED7[44];
- __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED8[64];
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
@@ -1158,7 +1207,7 @@ typedef struct { /*!< (@ 0x40003000) SPIS0 Struct
__IM uint32_t RESERVED3[5];
__IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */
__IM uint32_t RESERVED4[53];
- __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED5[64];
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
@@ -1185,6 +1234,59 @@ typedef struct { /*!< (@ 0x40003000) SPIS0 Struct
+/* =========================================================================================================================== */
+/* ================ TWI0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief I2C compatible Two-Wire Interface 0 (TWI0)
+ */
+
+typedef struct { /*!< (@ 0x40003000) TWI0 Structure */
+ __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */
+ __IM uint32_t RESERVED;
+ __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */
+ __IM uint32_t RESERVED1[2];
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */
+ __IM uint32_t RESERVED2;
+ __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */
+ __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */
+ __IM uint32_t RESERVED3[56];
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */
+ __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */
+ __IM uint32_t RESERVED4[4];
+ __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */
+ __IM uint32_t RESERVED6[4];
+ __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte
+ that is sent or received */
+ __IM uint32_t RESERVED7[3];
+ __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */
+ __IM uint32_t RESERVED8[45];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED9[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED10[110];
+ __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */
+ __IM uint32_t RESERVED11[14];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */
+ __IM uint32_t RESERVED12;
+ __IOM uint32_t PSELSCL; /*!< (@ 0x00000508) Pin select for SCL */
+ __IOM uint32_t PSELSDA; /*!< (@ 0x0000050C) Pin select for SDA */
+ __IM uint32_t RESERVED13[2];
+ __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */
+ __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */
+ __IM uint32_t RESERVED14;
+ __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency */
+ __IM uint32_t RESERVED15[24];
+ __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */
+} NRF_TWI_Type; /*!< Size = 1420 (0x58c) */
+
+
+
/* =========================================================================================================================== */
/* ================ TWIM0 ================ */
/* =========================================================================================================================== */
@@ -1219,7 +1321,7 @@ typedef struct { /*!< (@ 0x40003000) TWIM0 Struct
__IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last
byte */
__IM uint32_t RESERVED7[39];
- __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED8[63];
__IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
@@ -1247,139 +1349,55 @@ typedef struct { /*!< (@ 0x40003000) TWIM0 Struct
/**
- * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0)
- */
-
-typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */
- __IM uint32_t RESERVED[5];
- __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */
- __IM uint32_t RESERVED1;
- __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */
- __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */
- __IM uint32_t RESERVED2[3];
- __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */
- __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */
- __IM uint32_t RESERVED3[51];
- __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */
- __IM uint32_t RESERVED4[7];
- __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */
- __IM uint32_t RESERVED5[9];
- __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */
- __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */
- __IM uint32_t RESERVED6[4];
- __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */
- __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */
- __IM uint32_t RESERVED7[37];
- __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
- __IM uint32_t RESERVED8[63];
- __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
- __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
- __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
- __IM uint32_t RESERVED9[113];
- __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */
- __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had
- a match */
- __IM uint32_t RESERVED10[10];
- __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */
- __IM uint32_t RESERVED11;
- __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
- __IM uint32_t RESERVED12[9];
- __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */
- __IM uint32_t RESERVED13;
- __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */
- __IM uint32_t RESERVED14[14];
- __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection[0]: TWI slave address
- 0 */
- __IM uint32_t RESERVED15;
- __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match
- mechanism */
- __IM uint32_t RESERVED16[10];
- __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case
- of an over-read of the transmit buffer. */
-} NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */
-
-
-
-/* =========================================================================================================================== */
-/* ================ SPI0 ================ */
-/* =========================================================================================================================== */
-
-
-/**
- * @brief Serial Peripheral Interface 0 (SPI0)
- */
-
-typedef struct { /*!< (@ 0x40003000) SPI0 Structure */
- __IM uint32_t RESERVED[66];
- __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */
- __IM uint32_t RESERVED1[126];
- __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
- __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
- __IM uint32_t RESERVED2[125];
- __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */
- __IM uint32_t RESERVED3;
- __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
- __IM uint32_t RESERVED4;
- __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */
- __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */
- __IM uint32_t RESERVED5;
- __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency */
- __IM uint32_t RESERVED6[11];
- __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */
-} NRF_SPI_Type; /*!< Size = 1368 (0x558) */
-
-
-
-/* =========================================================================================================================== */
-/* ================ TWI0 ================ */
-/* =========================================================================================================================== */
-
-
-/**
- * @brief I2C compatible Two-Wire Interface 0 (TWI0)
+ * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0)
*/
-typedef struct { /*!< (@ 0x40003000) TWI0 Structure */
- __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */
- __IM uint32_t RESERVED;
- __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */
- __IM uint32_t RESERVED1[2];
+typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */
+ __IM uint32_t RESERVED[5];
__OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */
- __IM uint32_t RESERVED2;
+ __IM uint32_t RESERVED1;
__OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */
__OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */
- __IM uint32_t RESERVED3[56];
+ __IM uint32_t RESERVED2[3];
+ __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */
+ __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */
+ __IM uint32_t RESERVED3[51];
__IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */
- __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */
- __IM uint32_t RESERVED4[4];
- __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */
- __IM uint32_t RESERVED5;
+ __IM uint32_t RESERVED4[7];
__IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */
+ __IM uint32_t RESERVED5[9];
+ __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */
+ __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */
__IM uint32_t RESERVED6[4];
- __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte
- that is sent or received */
- __IM uint32_t RESERVED7[3];
- __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */
- __IM uint32_t RESERVED8[45];
- __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
- __IM uint32_t RESERVED9[64];
+ __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */
+ __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */
+ __IM uint32_t RESERVED7[37];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED8[63];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
- __IM uint32_t RESERVED10[110];
- __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */
- __IM uint32_t RESERVED11[14];
- __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */
- __IM uint32_t RESERVED12;
- __IOM uint32_t PSELSCL; /*!< (@ 0x00000508) Pin select for SCL */
- __IOM uint32_t PSELSDA; /*!< (@ 0x0000050C) Pin select for SDA */
- __IM uint32_t RESERVED13[2];
- __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */
- __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */
- __IM uint32_t RESERVED14;
- __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency */
- __IM uint32_t RESERVED15[24];
- __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */
-} NRF_TWI_Type; /*!< Size = 1420 (0x58c) */
+ __IM uint32_t RESERVED9[113];
+ __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */
+ __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had
+ a match */
+ __IM uint32_t RESERVED10[10];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */
+ __IM uint32_t RESERVED11;
+ __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
+ __IM uint32_t RESERVED12[9];
+ __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */
+ __IM uint32_t RESERVED13;
+ __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */
+ __IM uint32_t RESERVED14[14];
+ __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */
+ __IM uint32_t RESERVED15;
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match
+ mechanism */
+ __IM uint32_t RESERVED16[10];
+ __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case
+ of an over-read of the transmit buffer. */
+} NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */
@@ -1436,7 +1454,7 @@ typedef struct { /*!< (@ 0x40005000) NFCT Structu
__IOM uint32_t EVENTS_SELECTED; /*!< (@ 0x0000014C) NFC Auto collision resolution successfully completed */
__IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames. */
__IM uint32_t RESERVED6[43];
- __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED7[63];
__IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
@@ -1480,20 +1498,20 @@ typedef struct { /*!< (@ 0x40005000) NFCT Structu
*/
typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */
- __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection[0]: Task for writing to
- pin specified in CONFIG[0].PSEL. Action
- on pin is configured in CONFIG[0].POLARITY. */
+ __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin
+ specified in CONFIG[n].PSEL. Action on pin
+ is configured in CONFIG[n].POLARITY. */
__IM uint32_t RESERVED[4];
- __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection[0]: Task for writing to
- pin specified in CONFIG[0].PSEL. Action
- on pin is to set it high. */
+ __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin
+ specified in CONFIG[n].PSEL. Action on pin
+ is to set it high. */
__IM uint32_t RESERVED1[4];
- __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection[0]: Task for writing to
- pin specified in CONFIG[0].PSEL. Action
- on pin is to set it low. */
+ __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin
+ specified in CONFIG[n].PSEL. Action on pin
+ is to set it low. */
__IM uint32_t RESERVED2[32];
- __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection[0]: Event generated from
- pin specified in CONFIG[0].PSEL */
+ __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from
+ pin specified in CONFIG[n].PSEL */
__IM uint32_t RESERVED3[23];
__IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins
with SENSE mechanism enabled */
@@ -1501,9 +1519,8 @@ typedef struct { /*!< (@ 0x40006000) GPIOTE Struc
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
__IM uint32_t RESERVED5[129];
- __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection[0]: Configuration for
- OUT[n], SET[n] and CLR[n] tasks and IN[n]
- event */
+ __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n],
+ SET[n] and CLR[n] tasks and IN[n] event */
} NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */
@@ -1534,7 +1551,7 @@ typedef struct { /*!< (@ 0x40007000) SAADC Struct
__IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */
__IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */
__IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */
- __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Unspecified */
+ __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */
__IM uint32_t RESERVED1[106];
__IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
@@ -1575,13 +1592,13 @@ typedef struct { /*!< (@ 0x40008000) TIMER0 Struc
__OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */
__OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */
__IM uint32_t RESERVED[11];
- __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection[0]: Capture Timer value
- to CC[0] register */
+ __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to
+ CC[n] register */
__IM uint32_t RESERVED1[58];
- __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection[0]: Compare event on CC[0]
+ __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n]
match */
__IM uint32_t RESERVED2[42];
- __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED3[64];
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
@@ -1591,8 +1608,8 @@ typedef struct { /*!< (@ 0x40008000) TIMER0 Struc
__IM uint32_t RESERVED5;
__IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */
__IM uint32_t RESERVED6[11];
- __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection[0]: Capture/Compare register
- 0 */
+ __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register
+ n */
} NRF_TIMER_Type; /*!< Size = 1368 (0x558) */
@@ -1615,7 +1632,7 @@ typedef struct { /*!< (@ 0x4000B000) RTC0 Structu
__IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */
__IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */
__IM uint32_t RESERVED1[14];
- __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection[0]: Compare event on CC[0]
+ __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n]
match */
__IM uint32_t RESERVED2[109];
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
@@ -1629,7 +1646,7 @@ typedef struct { /*!< (@ 0x4000B000) RTC0 Structu
__IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu
t be written when RTC is stopped */
__IM uint32_t RESERVED5[13];
- __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection[0]: Compare register 0 */
+ __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */
} NRF_RTC_Type; /*!< Size = 1360 (0x550) */
@@ -1693,7 +1710,7 @@ typedef struct { /*!< (@ 0x4000D000) RNG Structur
__IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number
written to the VALUE register */
__IM uint32_t RESERVED1[63];
- __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED2[64];
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
@@ -1729,6 +1746,40 @@ typedef struct { /*!< (@ 0x4000E000) ECB Structur
+/* =========================================================================================================================== */
+/* ================ AAR ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Accelerated Address Resolver (AAR)
+ */
+
+typedef struct { /*!< (@ 0x4000F000) AAR Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified
+ in the IRK data structure */
+ __IM uint32_t RESERVED;
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */
+ __IM uint32_t RESERVED1[61];
+ __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */
+ __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */
+ __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */
+ __IM uint32_t RESERVED2[126];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED3[61];
+ __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */
+ __IM uint32_t RESERVED4[63];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */
+ __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */
+ __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */
+ __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */
+} NRF_AAR_Type; /*!< Size = 1304 (0x518) */
+
+
+
/* =========================================================================================================================== */
/* ================ CCM ================ */
/* =========================================================================================================================== */
@@ -1749,7 +1800,7 @@ typedef struct { /*!< (@ 0x4000F000) CCM Structur
__IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */
__IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) CCM error event */
__IM uint32_t RESERVED1[61];
- __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED2[64];
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
@@ -1767,40 +1818,6 @@ typedef struct { /*!< (@ 0x4000F000) CCM Structur
-/* =========================================================================================================================== */
-/* ================ AAR ================ */
-/* =========================================================================================================================== */
-
-
-/**
- * @brief Accelerated Address Resolver (AAR)
- */
-
-typedef struct { /*!< (@ 0x4000F000) AAR Structure */
- __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified
- in the IRK data structure */
- __IM uint32_t RESERVED;
- __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */
- __IM uint32_t RESERVED1[61];
- __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */
- __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */
- __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */
- __IM uint32_t RESERVED2[126];
- __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
- __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
- __IM uint32_t RESERVED3[61];
- __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */
- __IM uint32_t RESERVED4[63];
- __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */
- __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */
- __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */
- __IM uint32_t RESERVED5;
- __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */
- __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */
-} NRF_AAR_Type; /*!< Size = 1304 (0x518) */
-
-
-
/* =========================================================================================================================== */
/* ================ WDT ================ */
/* =========================================================================================================================== */
@@ -1825,7 +1842,7 @@ typedef struct { /*!< (@ 0x40010000) WDT Structur
__IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */
__IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */
__IM uint32_t RESERVED4[60];
- __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection[0]: Reload request 0 */
+ __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */
} NRF_WDT_Type; /*!< Size = 1568 (0x620) */
@@ -1853,7 +1870,7 @@ typedef struct { /*!< (@ 0x40012000) QDEC Structu
__IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */
__IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */
__IM uint32_t RESERVED1[59];
- __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED2[64];
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
@@ -1898,7 +1915,7 @@ typedef struct { /*!< (@ 0x40013000) COMP Structu
__IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */
__IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */
__IM uint32_t RESERVED1[60];
- __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED2[63];
__IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
@@ -1938,7 +1955,7 @@ typedef struct { /*!< (@ 0x40013000) LPCOMP Struc
__IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */
__IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */
__IM uint32_t RESERVED1[60];
- __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED2[64];
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
@@ -1957,21 +1974,6 @@ typedef struct { /*!< (@ 0x40013000) LPCOMP Struc
-/* =========================================================================================================================== */
-/* ================ SWI0 ================ */
-/* =========================================================================================================================== */
-
-
-/**
- * @brief Software interrupt 0 (SWI0)
- */
-
-typedef struct { /*!< (@ 0x40014000) SWI0 Structure */
- __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */
-} NRF_SWI_Type; /*!< Size = 4 (0x4) */
-
-
-
/* =========================================================================================================================== */
/* ================ EGU0 ================ */
/* =========================================================================================================================== */
@@ -1982,11 +1984,11 @@ typedef struct { /*!< (@ 0x40014000) SWI0 Structu
*/
typedef struct { /*!< (@ 0x40014000) EGU0 Structure */
- __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection[0]: Trigger 0 for triggering
- the corresponding TRIGGERED[0] event */
+ __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering
+ the corresponding TRIGGERED[n] event */
__IM uint32_t RESERVED[48];
- __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection[0]: Event number 0 generated
- by triggering the corresponding TRIGGER[0]
+ __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated
+ by triggering the corresponding TRIGGER[n]
task */
__IM uint32_t RESERVED1[112];
__IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
@@ -1996,6 +1998,21 @@ typedef struct { /*!< (@ 0x40014000) EGU0 Structu
+/* =========================================================================================================================== */
+/* ================ SWI0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Software interrupt 0 (SWI0)
+ */
+
+typedef struct { /*!< (@ 0x40014000) SWI0 Structure */
+ __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */
+} NRF_SWI_Type; /*!< Size = 4 (0x4) */
+
+
+
/* =========================================================================================================================== */
/* ================ PWM0 ================ */
/* =========================================================================================================================== */
@@ -2010,10 +2027,10 @@ typedef struct { /*!< (@ 0x4001C000) PWM0 Structu
__OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at
the end of current PWM period, and stops
sequence playback */
- __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection[0]: Loads the first PWM
- value on all enabled channels from sequence
- 0, and starts playing that sequence at the
- rate defined in SEQ[0]REFRESH and/or DECODER.MODE.
+ __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection: Loads the first PWM value
+ on all enabled channels from sequence n,
+ and starts playing that sequence at the
+ rate defined in SEQ[n]REFRESH and/or DECODER.MODE.
Causes PWM generation to start it was not
running. */
__OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on
@@ -2023,16 +2040,16 @@ typedef struct { /*!< (@ 0x4001C000) PWM0 Structu
__IM uint32_t RESERVED1[60];
__IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses
are no longer generated */
- __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection[0]: First PWM period started
- on sequence 0 */
- __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection[0]: Emitted at end of
- every sequence 0, when last value from RAM
- has been applied to wave counter */
+ __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection: First PWM period started
+ on sequence n */
+ __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection: Emitted at end of every
+ sequence n, when last value from RAM has
+ been applied to wave counter */
__IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */
__IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount
of times defined in LOOP.CNT */
__IM uint32_t RESERVED2[56];
- __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED3[63];
__IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
@@ -2134,7 +2151,7 @@ typedef struct { /*!< (@ 0x4001E000) NVMC Structu
*/
typedef struct { /*!< (@ 0x4001F000) PPI Structure */
- __IOM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */
+ __OM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */
__IM uint32_t RESERVED[308];
__IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */
__IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */
@@ -2142,7 +2159,7 @@ typedef struct { /*!< (@ 0x4001F000) PPI Structur
__IM uint32_t RESERVED1;
__IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */
__IM uint32_t RESERVED2[148];
- __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection[0]: Channel group 0 */
+ __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n */
__IM uint32_t RESERVED3[62];
__IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */
} NRF_PPI_Type; /*!< Size = 2448 (0x990) */
@@ -2160,17 +2177,17 @@ typedef struct { /*!< (@ 0x4001F000) PPI Structur
typedef struct { /*!< (@ 0x40020000) MWU Structure */
__IM uint32_t RESERVED[64];
- __IOM MWU_EVENTS_REGION_Type EVENTS_REGION[4];/*!< (@ 0x00000100) Unspecified */
+ __IOM MWU_EVENTS_REGION_Type EVENTS_REGION[4];/*!< (@ 0x00000100) Peripheral events. */
__IM uint32_t RESERVED1[16];
- __IOM MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];/*!< (@ 0x00000160) Unspecified */
+ __IOM MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];/*!< (@ 0x00000160) Peripheral events. */
__IM uint32_t RESERVED2[100];
__IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
__IM uint32_t RESERVED3[5];
- __IOM uint32_t NMIEN; /*!< (@ 0x00000320) Enable or disable non-maskable interrupt */
- __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable non-maskable interrupt */
- __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable non-maskable interrupt */
+ __IOM uint32_t NMIEN; /*!< (@ 0x00000320) Enable or disable interrupt */
+ __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable interrupt */
+ __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable interrupt */
__IM uint32_t RESERVED4[53];
__IOM MWU_PERREGION_Type PERREGION[2]; /*!< (@ 0x00000400) Unspecified */
__IM uint32_t RESERVED5[64];
@@ -2246,36 +2263,6 @@ typedef struct { /*!< (@ 0x40026000) FPU Structur
} NRF_FPU_Type; /*!< Size = 4 (0x4) */
-
-/* =========================================================================================================================== */
-/* ================ P0 ================ */
-/* =========================================================================================================================== */
-
-
-/**
- * @brief GPIO Port 1 (P0)
- */
-
-typedef struct { /*!< (@ 0x50000000) P0 Structure */
- __IM uint32_t RESERVED[321];
- __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */
- __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */
- __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */
- __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */
- __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */
- __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */
- __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */
- __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that
- have met the criteria set in the PIN_CNF[n].SENSE
- registers */
- __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour
- and LDETECT mode */
- __IM uint32_t RESERVED1[118];
- __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection[0]: Configuration of GPIO
- pins */
-} NRF_GPIO_Type; /*!< Size = 1920 (0x780) */
-
-
/** @} */ /* End of group Device_Peripheral_peripherals */
@@ -2292,23 +2279,24 @@ typedef struct { /*!< (@ 0x50000000) P0 Structure
#define NRF_UICR_BASE 0x10001000UL
#define NRF_APPROTECT_BASE 0x40000000UL
#define NRF_BPROT_BASE 0x40000000UL
-#define NRF_POWER_BASE 0x40000000UL
#define NRF_CLOCK_BASE 0x40000000UL
+#define NRF_POWER_BASE 0x40000000UL
+#define NRF_P0_BASE 0x50000000UL
#define NRF_RADIO_BASE 0x40001000UL
-#define NRF_UARTE0_BASE 0x40002000UL
#define NRF_UART0_BASE 0x40002000UL
+#define NRF_UARTE0_BASE 0x40002000UL
+#define NRF_SPI0_BASE 0x40003000UL
#define NRF_SPIM0_BASE 0x40003000UL
#define NRF_SPIS0_BASE 0x40003000UL
+#define NRF_TWI0_BASE 0x40003000UL
#define NRF_TWIM0_BASE 0x40003000UL
#define NRF_TWIS0_BASE 0x40003000UL
-#define NRF_SPI0_BASE 0x40003000UL
-#define NRF_TWI0_BASE 0x40003000UL
+#define NRF_SPI1_BASE 0x40004000UL
#define NRF_SPIM1_BASE 0x40004000UL
#define NRF_SPIS1_BASE 0x40004000UL
+#define NRF_TWI1_BASE 0x40004000UL
#define NRF_TWIM1_BASE 0x40004000UL
#define NRF_TWIS1_BASE 0x40004000UL
-#define NRF_SPI1_BASE 0x40004000UL
-#define NRF_TWI1_BASE 0x40004000UL
#define NRF_NFCT_BASE 0x40005000UL
#define NRF_GPIOTE_BASE 0x40006000UL
#define NRF_SAADC_BASE 0x40007000UL
@@ -2319,25 +2307,25 @@ typedef struct { /*!< (@ 0x50000000) P0 Structure
#define NRF_TEMP_BASE 0x4000C000UL
#define NRF_RNG_BASE 0x4000D000UL
#define NRF_ECB_BASE 0x4000E000UL
-#define NRF_CCM_BASE 0x4000F000UL
#define NRF_AAR_BASE 0x4000F000UL
+#define NRF_CCM_BASE 0x4000F000UL
#define NRF_WDT_BASE 0x40010000UL
#define NRF_RTC1_BASE 0x40011000UL
#define NRF_QDEC_BASE 0x40012000UL
#define NRF_COMP_BASE 0x40013000UL
#define NRF_LPCOMP_BASE 0x40013000UL
-#define NRF_SWI0_BASE 0x40014000UL
#define NRF_EGU0_BASE 0x40014000UL
-#define NRF_SWI1_BASE 0x40015000UL
+#define NRF_SWI0_BASE 0x40014000UL
#define NRF_EGU1_BASE 0x40015000UL
-#define NRF_SWI2_BASE 0x40016000UL
+#define NRF_SWI1_BASE 0x40015000UL
#define NRF_EGU2_BASE 0x40016000UL
-#define NRF_SWI3_BASE 0x40017000UL
+#define NRF_SWI2_BASE 0x40016000UL
#define NRF_EGU3_BASE 0x40017000UL
-#define NRF_SWI4_BASE 0x40018000UL
+#define NRF_SWI3_BASE 0x40017000UL
#define NRF_EGU4_BASE 0x40018000UL
-#define NRF_SWI5_BASE 0x40019000UL
+#define NRF_SWI4_BASE 0x40018000UL
#define NRF_EGU5_BASE 0x40019000UL
+#define NRF_SWI5_BASE 0x40019000UL
#define NRF_TIMER3_BASE 0x4001A000UL
#define NRF_TIMER4_BASE 0x4001B000UL
#define NRF_PWM0_BASE 0x4001C000UL
@@ -2347,13 +2335,12 @@ typedef struct { /*!< (@ 0x50000000) P0 Structure
#define NRF_MWU_BASE 0x40020000UL
#define NRF_PWM1_BASE 0x40021000UL
#define NRF_PWM2_BASE 0x40022000UL
+#define NRF_SPI2_BASE 0x40023000UL
#define NRF_SPIM2_BASE 0x40023000UL
#define NRF_SPIS2_BASE 0x40023000UL
-#define NRF_SPI2_BASE 0x40023000UL
#define NRF_RTC2_BASE 0x40024000UL
#define NRF_I2S_BASE 0x40025000UL
#define NRF_FPU_BASE 0x40026000UL
-#define NRF_P0_BASE 0x50000000UL
/** @} */ /* End of group Device_Peripheral_peripheralAddr */
@@ -2371,23 +2358,24 @@ typedef struct { /*!< (@ 0x50000000) P0 Structure
#define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE)
#define NRF_APPROTECT ((NRF_APPROTECT_Type*) NRF_APPROTECT_BASE)
#define NRF_BPROT ((NRF_BPROT_Type*) NRF_BPROT_BASE)
-#define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE)
#define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE)
+#define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE)
+#define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE)
#define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE)
-#define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE)
#define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE)
+#define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE)
+#define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE)
#define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE)
#define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE)
+#define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE)
#define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE)
#define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE)
-#define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE)
-#define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE)
+#define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE)
#define NRF_SPIM1 ((NRF_SPIM_Type*) NRF_SPIM1_BASE)
#define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE)
+#define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE)
#define NRF_TWIM1 ((NRF_TWIM_Type*) NRF_TWIM1_BASE)
#define NRF_TWIS1 ((NRF_TWIS_Type*) NRF_TWIS1_BASE)
-#define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE)
-#define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE)
#define NRF_NFCT ((NRF_NFCT_Type*) NRF_NFCT_BASE)
#define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE)
#define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE)
@@ -2398,25 +2386,25 @@ typedef struct { /*!< (@ 0x50000000) P0 Structure
#define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE)
#define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE)
#define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE)
-#define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE)
#define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE)
+#define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE)
#define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE)
#define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE)
#define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE)
#define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE)
#define NRF_LPCOMP ((NRF_LPCOMP_Type*) NRF_LPCOMP_BASE)
-#define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE)
#define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE)
-#define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE)
+#define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE)
#define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE)
-#define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE)
+#define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE)
#define NRF_EGU2 ((NRF_EGU_Type*) NRF_EGU2_BASE)
-#define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE)
+#define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE)
#define NRF_EGU3 ((NRF_EGU_Type*) NRF_EGU3_BASE)
-#define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE)
+#define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE)
#define NRF_EGU4 ((NRF_EGU_Type*) NRF_EGU4_BASE)
-#define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE)
+#define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE)
#define NRF_EGU5 ((NRF_EGU_Type*) NRF_EGU5_BASE)
+#define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE)
#define NRF_TIMER3 ((NRF_TIMER_Type*) NRF_TIMER3_BASE)
#define NRF_TIMER4 ((NRF_TIMER_Type*) NRF_TIMER4_BASE)
#define NRF_PWM0 ((NRF_PWM_Type*) NRF_PWM0_BASE)
@@ -2426,13 +2414,12 @@ typedef struct { /*!< (@ 0x50000000) P0 Structure
#define NRF_MWU ((NRF_MWU_Type*) NRF_MWU_BASE)
#define NRF_PWM1 ((NRF_PWM_Type*) NRF_PWM1_BASE)
#define NRF_PWM2 ((NRF_PWM_Type*) NRF_PWM2_BASE)
+#define NRF_SPI2 ((NRF_SPI_Type*) NRF_SPI2_BASE)
#define NRF_SPIM2 ((NRF_SPIM_Type*) NRF_SPIM2_BASE)
#define NRF_SPIS2 ((NRF_SPIS_Type*) NRF_SPIS2_BASE)
-#define NRF_SPI2 ((NRF_SPI_Type*) NRF_SPI2_BASE)
#define NRF_RTC2 ((NRF_RTC_Type*) NRF_RTC2_BASE)
#define NRF_I2S ((NRF_I2S_Type*) NRF_I2S_BASE)
#define NRF_FPU ((NRF_FPU_Type*) NRF_FPU_BASE)
-#define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE)
/** @} */ /* End of group Device_Peripheral_declaration */
diff --git a/mcu/nrf/common/vendor/mdk/nrf52832_peripherals.h b/mcu/nrf/common/vendor/mdk/nrf52832_peripherals.h
index bada5f2c..72798878 100644
--- a/mcu/nrf/common/vendor/mdk/nrf52832_peripherals.h
+++ b/mcu/nrf/common/vendor/mdk/nrf52832_peripherals.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
+Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
diff --git a/mcu/nrf/common/vendor/mdk/nrf52833.h b/mcu/nrf/common/vendor/mdk/nrf52833.h
index dad362e2..f9c0bcf6 100644
--- a/mcu/nrf/common/vendor/mdk/nrf52833.h
+++ b/mcu/nrf/common/vendor/mdk/nrf52833.h
@@ -1,41 +1,41 @@
/*
- * Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
- * contributors may be used to endorse or promote products derived from this
- * software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.\n
+\n
+SPDX-License-Identifier: BSD-3-Clause\n
+\n
+Redistribution and use in source and binary forms, with or without\n
+modification, are permitted provided that the following conditions are met:\n
+\n
+1. Redistributions of source code must retain the above copyright notice, this\n
+ list of conditions and the following disclaimer.\n
+\n
+2. Redistributions in binary form must reproduce the above copyright\n
+ notice, this list of conditions and the following disclaimer in the\n
+ documentation and/or other materials provided with the distribution.\n
+\n
+3. Neither the name of Nordic Semiconductor ASA nor the names of its\n
+ contributors may be used to endorse or promote products derived from this\n
+ software without specific prior written permission.\n
+\n
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n
+IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n
+ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n
+POSSIBILITY OF SUCH DAMAGE.\n
*
* @file nrf52833.h
* @brief CMSIS HeaderFile
* @version 1
- * @date 29. April 2021
- * @note Generated by SVDConv V3.3.35 on Thursday, 29.04.2021 12:43:46
+ * @date 04. April 2023
+ * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:35
* from File 'nrf52833.svd',
- * last modified on Thursday, 29.04.2021 10:43:41
+ * last modified on Tuesday, 04.04.2023 09:57:14
*/
@@ -134,6 +134,7 @@ typedef enum {
/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */
#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
+#define __INTERRUPTS_MAX 112 /*!< Top interrupt number */
#define __DSP_PRESENT 1 /*!< DSP present or not */
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
@@ -605,8 +606,8 @@ typedef struct {
__IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Start address of region
to protect. The start address must be word-aligned. */
__IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Size of region to protect
- counting from address ACL[n].ADDR. Write
- '0' as no effect. */
+ counting from address ACL[n].ADDR. Writing
+ a '0' has no effect. */
__IOM uint32_t PERM; /*!< (@ 0x00000008) Description cluster: Access permissions for region
n as defined by start address ACL[n].ADDR
and size ACL[n].SIZE */
@@ -1995,7 +1996,7 @@ typedef struct { /*!< (@ 0x4000F000) AAR Structur
/**
- * @brief AES CCM Mode Encryption (CCM)
+ * @brief AES CCM mode encryption (CCM)
*/
typedef struct { /*!< (@ 0x4000F000) CCM Structure */
@@ -2021,15 +2022,16 @@ typedef struct { /*!< (@ 0x4000F000) CCM Structur
__IM uint32_t RESERVED4[63];
__IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */
__IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */
- __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and
- NONCE vector */
+ __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding the AES key
+ and the NONCE vector */
__IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */
__IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */
__IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */
__IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of keystream generated when MODE.LENGTH
- = Extended. */
+ = Extended */
__IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */
-} NRF_CCM_Type; /*!< Size = 1312 (0x520) */
+ __IOM uint32_t HEADERMASK; /*!< (@ 0x00000520) Header (S0) mask. */
+} NRF_CCM_Type; /*!< Size = 1316 (0x524) */
diff --git a/mcu/nrf/common/vendor/mdk/nrf52833_bitfields.h b/mcu/nrf/common/vendor/mdk/nrf52833_bitfields.h
index 372472b2..707a3598 100644
--- a/mcu/nrf/common/vendor/mdk/nrf52833_bitfields.h
+++ b/mcu/nrf/common/vendor/mdk/nrf52833_bitfields.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
+Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
@@ -187,7 +187,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define ACL_ACL_ADDR_ADDR_Msk (0xFFFFFFFFUL << ACL_ACL_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */
/* Register: ACL_ACL_SIZE */
-/* Description: Description cluster: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. */
+/* Description: Description cluster: Size of region to protect counting from address ACL[n].ADDR. Writing a '0' has no effect. */
/* Bits 31..0 : Size of flash region n in bytes. Must be a multiple of the flash page size. */
#define ACL_ACL_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
@@ -196,17 +196,17 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: ACL_ACL_PERM */
/* Description: Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE */
-/* Bit 2 : Configure read permissions for region n. Write '0' has no effect. */
+/* Bit 2 : Configure read permissions for region n. Writing a '0' has no effect. */
#define ACL_ACL_PERM_READ_Pos (2UL) /*!< Position of READ field. */
#define ACL_ACL_PERM_READ_Msk (0x1UL << ACL_ACL_PERM_READ_Pos) /*!< Bit mask of READ field. */
-#define ACL_ACL_PERM_READ_Enable (0UL) /*!< Allow read instructions to region n */
-#define ACL_ACL_PERM_READ_Disable (1UL) /*!< Block read instructions to region n */
+#define ACL_ACL_PERM_READ_Enable (0UL) /*!< Allow read instructions to region n. */
+#define ACL_ACL_PERM_READ_Disable (1UL) /*!< Block read instructions to region n. */
-/* Bit 1 : Configure write and erase permissions for region n. Write '0' has no effect. */
+/* Bit 1 : Configure write and erase permissions for region n. Writing a '0' has no effect. */
#define ACL_ACL_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */
#define ACL_ACL_PERM_WRITE_Msk (0x1UL << ACL_ACL_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */
-#define ACL_ACL_PERM_WRITE_Enable (0UL) /*!< Allow write and erase instructions to region n */
-#define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region n */
+#define ACL_ACL_PERM_WRITE_Enable (0UL) /*!< Allow write and erase instructions to region n. */
+#define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region n. */
/* Peripheral: APPROTECT */
@@ -230,7 +230,7 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: CCM */
-/* Description: AES CCM Mode Encryption */
+/* Description: AES CCM mode encryption */
/* Register: CCM_TASKS_KSGEN */
/* Description: Start generation of keystream. This operation will stop by itself when completed. */
@@ -380,19 +380,19 @@ POSSIBILITY OF SUCH DAMAGE.
#define CCM_MODE_DATARATE_Msk (0x3UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */
#define CCM_MODE_DATARATE_1Mbit (0UL) /*!< 1 Mbps */
#define CCM_MODE_DATARATE_2Mbit (1UL) /*!< 2 Mbps */
-#define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 Kbps */
-#define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 Kbps */
+#define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 kbps */
+#define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 kbps */
-/* Bit 0 : The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. */
+/* Bit 0 : The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered. */
#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
#define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */
#define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */
/* Register: CCM_CNFPTR */
-/* Description: Pointer to data structure holding AES key and NONCE vector */
+/* Description: Pointer to data structure holding the AES key and the NONCE vector */
-/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */
+/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see table CCM data structure overview) */
#define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */
#define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */
@@ -419,22 +419,29 @@ POSSIBILITY OF SUCH DAMAGE.
#define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
/* Register: CCM_MAXPACKETSIZE */
-/* Description: Length of keystream generated when MODE.LENGTH = Extended. */
+/* Description: Length of keystream generated when MODE.LENGTH = Extended */
-/* Bits 7..0 : Length of keystream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. */
+/* Bits 7..0 : Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted. */
#define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */
#define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */
/* Register: CCM_RATEOVERRIDE */
/* Description: Data rate override setting. */
-/* Bits 1..0 : Data rate override setting. */
+/* Bits 1..0 : Data rate override setting */
#define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL) /*!< Position of RATEOVERRIDE field. */
#define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x3UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field. */
#define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0UL) /*!< 1 Mbps */
#define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (1UL) /*!< 2 Mbps */
-#define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 Kbps */
-#define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 Kbps */
+#define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 kbps */
+#define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 kbps */
+
+/* Register: CCM_HEADERMASK */
+/* Description: Header (S0) mask. */
+
+/* Bits 7..0 : Header (S0) mask */
+#define CCM_HEADERMASK_HEADERMASK_Pos (0UL) /*!< Position of HEADERMASK field. */
+#define CCM_HEADERMASK_HEADERMASK_Msk (0xFFUL << CCM_HEADERMASK_HEADERMASK_Pos) /*!< Bit mask of HEADERMASK field. */
/* Peripheral: CLOCK */
@@ -1551,6 +1558,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define FICR_INFO_VARIANT_VARIANT_AAA1 (0x41414131UL) /*!< AAA1 */
#define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */
#define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */
+#define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */
#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
/* Register: FICR_INFO_PACKAGE */
diff --git a/mcu/nrf/common/vendor/mdk/nrf52833_peripherals.h b/mcu/nrf/common/vendor/mdk/nrf52833_peripherals.h
index c0629c3a..e7afce42 100644
--- a/mcu/nrf/common/vendor/mdk/nrf52833_peripherals.h
+++ b/mcu/nrf/common/vendor/mdk/nrf52833_peripherals.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
+Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
diff --git a/mcu/nrf/common/vendor/mdk/nrf52840.h b/mcu/nrf/common/vendor/mdk/nrf52840.h
index 141e4369..ca458c0a 100644
--- a/mcu/nrf/common/vendor/mdk/nrf52840.h
+++ b/mcu/nrf/common/vendor/mdk/nrf52840.h
@@ -1,41 +1,41 @@
/*
- * Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
- * contributors may be used to endorse or promote products derived from this
- * software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.\n
+\n
+SPDX-License-Identifier: BSD-3-Clause\n
+\n
+Redistribution and use in source and binary forms, with or without\n
+modification, are permitted provided that the following conditions are met:\n
+\n
+1. Redistributions of source code must retain the above copyright notice, this\n
+ list of conditions and the following disclaimer.\n
+\n
+2. Redistributions in binary form must reproduce the above copyright\n
+ notice, this list of conditions and the following disclaimer in the\n
+ documentation and/or other materials provided with the distribution.\n
+\n
+3. Neither the name of Nordic Semiconductor ASA nor the names of its\n
+ contributors may be used to endorse or promote products derived from this\n
+ software without specific prior written permission.\n
+\n
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n
+IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n
+ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n
+POSSIBILITY OF SUCH DAMAGE.\n
*
* @file nrf52840.h
* @brief CMSIS HeaderFile
* @version 1
- * @date 29. April 2021
- * @note Generated by SVDConv V3.3.35 on Thursday, 29.04.2021 12:43:48
+ * @date 04. April 2023
+ * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:37
* from File 'nrf52840.svd',
- * last modified on Thursday, 29.04.2021 10:43:41
+ * last modified on Tuesday, 04.04.2023 09:57:14
*/
@@ -136,6 +136,7 @@ typedef enum {
/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */
#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
+#define __INTERRUPTS_MAX 112 /*!< Top interrupt number */
#define __DSP_PRESENT 1 /*!< DSP present or not */
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
@@ -603,8 +604,8 @@ typedef struct {
__IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Start address of region
to protect. The start address must be word-aligned. */
__IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Size of region to protect
- counting from address ACL[n].ADDR. Write
- '0' as no effect. */
+ counting from address ACL[n].ADDR. Writing
+ a '0' has no effect. */
__IOM uint32_t PERM; /*!< (@ 0x00000008) Description cluster: Access permissions for region
n as defined by start address ACL[n].ADDR
and size ACL[n].SIZE */
@@ -2017,7 +2018,7 @@ typedef struct { /*!< (@ 0x4000F000) AAR Structur
/**
- * @brief AES CCM Mode Encryption (CCM)
+ * @brief AES CCM mode encryption (CCM)
*/
typedef struct { /*!< (@ 0x4000F000) CCM Structure */
@@ -2043,13 +2044,13 @@ typedef struct { /*!< (@ 0x4000F000) CCM Structur
__IM uint32_t RESERVED4[63];
__IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */
__IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */
- __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and
- NONCE vector */
+ __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding the AES key
+ and the NONCE vector */
__IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */
__IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */
__IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */
__IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of keystream generated when MODE.LENGTH
- = Extended. */
+ = Extended */
__IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */
} NRF_CCM_Type; /*!< Size = 1312 (0x520) */
diff --git a/mcu/nrf/common/vendor/mdk/nrf52840_bitfields.h b/mcu/nrf/common/vendor/mdk/nrf52840_bitfields.h
index 2e8b24ac..fec204b4 100644
--- a/mcu/nrf/common/vendor/mdk/nrf52840_bitfields.h
+++ b/mcu/nrf/common/vendor/mdk/nrf52840_bitfields.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
+Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
@@ -187,7 +187,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define ACL_ACL_ADDR_ADDR_Msk (0xFFFFFFFFUL << ACL_ACL_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */
/* Register: ACL_ACL_SIZE */
-/* Description: Description cluster: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. */
+/* Description: Description cluster: Size of region to protect counting from address ACL[n].ADDR. Writing a '0' has no effect. */
/* Bits 31..0 : Size of flash region n in bytes. Must be a multiple of the flash page size. */
#define ACL_ACL_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
@@ -196,17 +196,17 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: ACL_ACL_PERM */
/* Description: Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE */
-/* Bit 2 : Configure read permissions for region n. Write '0' has no effect. */
+/* Bit 2 : Configure read permissions for region n. Writing a '0' has no effect. */
#define ACL_ACL_PERM_READ_Pos (2UL) /*!< Position of READ field. */
#define ACL_ACL_PERM_READ_Msk (0x1UL << ACL_ACL_PERM_READ_Pos) /*!< Bit mask of READ field. */
-#define ACL_ACL_PERM_READ_Enable (0UL) /*!< Allow read instructions to region n */
-#define ACL_ACL_PERM_READ_Disable (1UL) /*!< Block read instructions to region n */
+#define ACL_ACL_PERM_READ_Enable (0UL) /*!< Allow read instructions to region n. */
+#define ACL_ACL_PERM_READ_Disable (1UL) /*!< Block read instructions to region n. */
-/* Bit 1 : Configure write and erase permissions for region n. Write '0' has no effect. */
+/* Bit 1 : Configure write and erase permissions for region n. Writing a '0' has no effect. */
#define ACL_ACL_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */
#define ACL_ACL_PERM_WRITE_Msk (0x1UL << ACL_ACL_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */
-#define ACL_ACL_PERM_WRITE_Enable (0UL) /*!< Allow write and erase instructions to region n */
-#define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region n */
+#define ACL_ACL_PERM_WRITE_Enable (0UL) /*!< Allow write and erase instructions to region n. */
+#define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region n. */
/* Peripheral: APPROTECT */
@@ -230,7 +230,7 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: CCM */
-/* Description: AES CCM Mode Encryption */
+/* Description: AES CCM mode encryption */
/* Register: CCM_TASKS_KSGEN */
/* Description: Start generation of keystream. This operation will stop by itself when completed. */
@@ -380,19 +380,19 @@ POSSIBILITY OF SUCH DAMAGE.
#define CCM_MODE_DATARATE_Msk (0x3UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */
#define CCM_MODE_DATARATE_1Mbit (0UL) /*!< 1 Mbps */
#define CCM_MODE_DATARATE_2Mbit (1UL) /*!< 2 Mbps */
-#define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 Kbps */
-#define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 Kbps */
+#define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 kbps */
+#define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 kbps */
-/* Bit 0 : The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. */
+/* Bit 0 : The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered. */
#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
#define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */
#define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */
/* Register: CCM_CNFPTR */
-/* Description: Pointer to data structure holding AES key and NONCE vector */
+/* Description: Pointer to data structure holding the AES key and the NONCE vector */
-/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */
+/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see table CCM data structure overview) */
#define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */
#define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */
@@ -419,22 +419,22 @@ POSSIBILITY OF SUCH DAMAGE.
#define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
/* Register: CCM_MAXPACKETSIZE */
-/* Description: Length of keystream generated when MODE.LENGTH = Extended. */
+/* Description: Length of keystream generated when MODE.LENGTH = Extended */
-/* Bits 7..0 : Length of keystream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. */
+/* Bits 7..0 : Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted. */
#define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */
#define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */
/* Register: CCM_RATEOVERRIDE */
/* Description: Data rate override setting. */
-/* Bits 1..0 : Data rate override setting. */
+/* Bits 1..0 : Data rate override setting */
#define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL) /*!< Position of RATEOVERRIDE field. */
#define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x3UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field. */
#define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0UL) /*!< 1 Mbps */
#define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (1UL) /*!< 2 Mbps */
-#define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 Kbps */
-#define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 Kbps */
+#define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 kbps */
+#define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 kbps */
/* Peripheral: CC_HOST_RGF */
@@ -1642,6 +1642,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define FICR_INFO_VARIANT_VARIANT_AAD1 (0x41414431UL) /*!< AAD1 */
#define FICR_INFO_VARIANT_VARIANT_AADA (0x41414441UL) /*!< AADA */
#define FICR_INFO_VARIANT_VARIANT_AAEA (0x41414541UL) /*!< AAEA */
+#define FICR_INFO_VARIANT_VARIANT_AAF0 (0x41414630UL) /*!< AAF0 */
+#define FICR_INFO_VARIANT_VARIANT_AAFA (0x41414641UL) /*!< AAFA */
#define FICR_INFO_VARIANT_VARIANT_BAAA (0x42414141UL) /*!< BAAA */
#define FICR_INFO_VARIANT_VARIANT_CAAA (0x43414141UL) /*!< CAAA */
#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
@@ -1652,6 +1654,7 @@ POSSIBILITY OF SUCH DAMAGE.
/* Bits 31..0 : Package option */
#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
+#define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 6x6 48-pin QFN */
#define FICR_INFO_PACKAGE_PACKAGE_QI (0x2004UL) /*!< QIxx - 7x7 73-pin aQFN */
#define FICR_INFO_PACKAGE_PACKAGE_CK (0x2005UL) /*!< CKxx - 3.544 x 3.607 WLCSP */
#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
@@ -1662,11 +1665,11 @@ POSSIBILITY OF SUCH DAMAGE.
/* Bits 31..0 : RAM variant */
#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
-#define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */
-#define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */
-#define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */
-#define FICR_INFO_RAM_RAM_K128 (0x80UL) /*!< 128 kByte RAM */
-#define FICR_INFO_RAM_RAM_K256 (0x100UL) /*!< 256 kByte RAM */
+#define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kB RAM */
+#define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kB RAM */
+#define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kB RAM */
+#define FICR_INFO_RAM_RAM_K128 (0x80UL) /*!< 128 kB RAM */
+#define FICR_INFO_RAM_RAM_K256 (0x100UL) /*!< 256 kB RAM */
#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
/* Register: FICR_INFO_FLASH */
@@ -1675,11 +1678,11 @@ POSSIBILITY OF SUCH DAMAGE.
/* Bits 31..0 : Flash variant */
#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
-#define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */
-#define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */
-#define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */
-#define FICR_INFO_FLASH_FLASH_K1024 (0x400UL) /*!< 1 MByte FLASH */
-#define FICR_INFO_FLASH_FLASH_K2048 (0x800UL) /*!< 2 MByte FLASH */
+#define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kB FLASH */
+#define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kB FLASH */
+#define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kB FLASH */
+#define FICR_INFO_FLASH_FLASH_K1024 (0x400UL) /*!< 1 MB FLASH */
+#define FICR_INFO_FLASH_FLASH_K2048 (0x800UL) /*!< 2 MB FLASH */
#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
/* Register: FICR_PRODTEST */
diff --git a/mcu/nrf/common/vendor/mdk/nrf52840_peripherals.h b/mcu/nrf/common/vendor/mdk/nrf52840_peripherals.h
index 1c9140e7..e56e7bc1 100644
--- a/mcu/nrf/common/vendor/mdk/nrf52840_peripherals.h
+++ b/mcu/nrf/common/vendor/mdk/nrf52840_peripherals.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
+Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
diff --git a/mcu/nrf/common/vendor/mdk/nrf52_bitfields.h b/mcu/nrf/common/vendor/mdk/nrf52_bitfields.h
index 220ada67..33fc6cec 100644
--- a/mcu/nrf/common/vendor/mdk/nrf52_bitfields.h
+++ b/mcu/nrf/common/vendor/mdk/nrf52_bitfields.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
+Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
@@ -40,24 +40,67 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: AAR */
/* Description: Accelerated Address Resolver */
+/* Register: AAR_TASKS_START */
+/* Description: Start resolving addresses based on IRKs specified in the IRK data structure */
+
+/* Bit 0 : Start resolving addresses based on IRKs specified in the IRK data structure */
+#define AAR_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define AAR_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: AAR_TASKS_STOP */
+/* Description: Stop resolving addresses */
+
+/* Bit 0 : Stop resolving addresses */
+#define AAR_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define AAR_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: AAR_EVENTS_END */
+/* Description: Address resolution procedure complete */
+
+/* Bit 0 : Address resolution procedure complete */
+#define AAR_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
+#define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
+#define AAR_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
+#define AAR_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
+
+/* Register: AAR_EVENTS_RESOLVED */
+/* Description: Address resolved */
+
+/* Bit 0 : Address resolved */
+#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos (0UL) /*!< Position of EVENTS_RESOLVED field. */
+#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of EVENTS_RESOLVED field. */
+#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_NotGenerated (0UL) /*!< Event not generated */
+#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Generated (1UL) /*!< Event generated */
+
+/* Register: AAR_EVENTS_NOTRESOLVED */
+/* Description: Address not resolved */
+
+/* Bit 0 : Address not resolved */
+#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos (0UL) /*!< Position of EVENTS_NOTRESOLVED field. */
+#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask of EVENTS_NOTRESOLVED field. */
+#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_NotGenerated (0UL) /*!< Event not generated */
+#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Generated (1UL) /*!< Event generated */
+
/* Register: AAR_INTENSET */
/* Description: Enable interrupt */
-/* Bit 2 : Write '1' to Enable interrupt for NOTRESOLVED event */
+/* Bit 2 : Write '1' to enable interrupt for event NOTRESOLVED */
#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */
-/* Bit 1 : Write '1' to Enable interrupt for RESOLVED event */
+/* Bit 1 : Write '1' to enable interrupt for event RESOLVED */
#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */
-/* Bit 0 : Write '1' to Enable interrupt for END event */
+/* Bit 0 : Write '1' to enable interrupt for event END */
#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
#define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
@@ -67,21 +110,21 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: AAR_INTENCLR */
/* Description: Disable interrupt */
-/* Bit 2 : Write '1' to Disable interrupt for NOTRESOLVED event */
+/* Bit 2 : Write '1' to disable interrupt for event NOTRESOLVED */
#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */
-/* Bit 1 : Write '1' to Disable interrupt for RESOLVED event */
+/* Bit 1 : Write '1' to disable interrupt for event RESOLVED */
#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */
-/* Bit 0 : Write '1' to Disable interrupt for END event */
+/* Bit 0 : Write '1' to disable interrupt for event END */
#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
#define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
@@ -949,10 +992,61 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: CCM */
/* Description: AES CCM Mode Encryption */
+/* Register: CCM_TASKS_KSGEN */
+/* Description: Start generation of key-stream. This operation will stop by itself when completed. */
+
+/* Bit 0 : Start generation of key-stream. This operation will stop by itself when completed. */
+#define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */
+#define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */
+#define CCM_TASKS_KSGEN_TASKS_KSGEN_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CCM_TASKS_CRYPT */
+/* Description: Start encryption/decryption. This operation will stop by itself when completed. */
+
+/* Bit 0 : Start encryption/decryption. This operation will stop by itself when completed. */
+#define CCM_TASKS_CRYPT_TASKS_CRYPT_Pos (0UL) /*!< Position of TASKS_CRYPT field. */
+#define CCM_TASKS_CRYPT_TASKS_CRYPT_Msk (0x1UL << CCM_TASKS_CRYPT_TASKS_CRYPT_Pos) /*!< Bit mask of TASKS_CRYPT field. */
+#define CCM_TASKS_CRYPT_TASKS_CRYPT_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CCM_TASKS_STOP */
+/* Description: Stop encryption/decryption */
+
+/* Bit 0 : Stop encryption/decryption */
+#define CCM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define CCM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CCM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define CCM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CCM_EVENTS_ENDKSGEN */
+/* Description: Key-stream generation complete */
+
+/* Bit 0 : Key-stream generation complete */
+#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */
+#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */
+#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_NotGenerated (0UL) /*!< Event not generated */
+#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Generated (1UL) /*!< Event generated */
+
+/* Register: CCM_EVENTS_ENDCRYPT */
+/* Description: Encrypt/decrypt complete */
+
+/* Bit 0 : Encrypt/decrypt complete */
+#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos (0UL) /*!< Position of EVENTS_ENDCRYPT field. */
+#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Msk (0x1UL << CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos) /*!< Bit mask of EVENTS_ENDCRYPT field. */
+#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_NotGenerated (0UL) /*!< Event not generated */
+#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Generated (1UL) /*!< Event generated */
+
+/* Register: CCM_EVENTS_ERROR */
+/* Description: CCM error event */
+
+/* Bit 0 : CCM error event */
+#define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
+#define CCM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << CCM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
+#define CCM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
+#define CCM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
+
/* Register: CCM_SHORTS */
-/* Description: Shortcut register */
+/* Description: Shortcuts between local events and tasks */
-/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task */
+/* Bit 0 : Shortcut between event ENDKSGEN and task CRYPT */
#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */
@@ -961,21 +1055,21 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: CCM_INTENSET */
/* Description: Enable interrupt */
-/* Bit 2 : Write '1' to Enable interrupt for ERROR event */
+/* Bit 2 : Write '1' to enable interrupt for event ERROR */
#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */
-/* Bit 1 : Write '1' to Enable interrupt for ENDCRYPT event */
+/* Bit 1 : Write '1' to enable interrupt for event ENDCRYPT */
#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */
-/* Bit 0 : Write '1' to Enable interrupt for ENDKSGEN event */
+/* Bit 0 : Write '1' to enable interrupt for event ENDKSGEN */
#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
@@ -985,21 +1079,21 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: CCM_INTENCLR */
/* Description: Disable interrupt */
-/* Bit 2 : Write '1' to Disable interrupt for ERROR event */
+/* Bit 2 : Write '1' to disable interrupt for event ERROR */
#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
-/* Bit 1 : Write '1' to Disable interrupt for ENDCRYPT event */
+/* Bit 1 : Write '1' to disable interrupt for event ENDCRYPT */
#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */
-/* Bit 0 : Write '1' to Disable interrupt for ENDKSGEN event */
+/* Bit 0 : Write '1' to disable interrupt for event ENDKSGEN */
#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
@@ -1069,7 +1163,8 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: CCM_SCRATCHPTR */
/* Description: Pointer to data area used for temporary storage */
-/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. */
+/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation,
+ MIC generation and encryption/decryption. */
#define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
#define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
@@ -1077,31 +1172,123 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: CLOCK */
/* Description: Clock control */
+/* Register: CLOCK_TASKS_HFCLKSTART */
+/* Description: Start HFCLK crystal oscillator */
+
+/* Bit 0 : Start HFCLK crystal oscillator */
+#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */
+#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */
+#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CLOCK_TASKS_HFCLKSTOP */
+/* Description: Stop HFCLK crystal oscillator */
+
+/* Bit 0 : Stop HFCLK crystal oscillator */
+#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */
+#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */
+#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CLOCK_TASKS_LFCLKSTART */
+/* Description: Start LFCLK source */
+
+/* Bit 0 : Start LFCLK source */
+#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */
+#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */
+#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CLOCK_TASKS_LFCLKSTOP */
+/* Description: Stop LFCLK source */
+
+/* Bit 0 : Stop LFCLK source */
+#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */
+#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */
+#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CLOCK_TASKS_CAL */
+/* Description: Start calibration of LFRC oscillator */
+
+/* Bit 0 : Start calibration of LFRC oscillator */
+#define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL) /*!< Position of TASKS_CAL field. */
+#define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos) /*!< Bit mask of TASKS_CAL field. */
+#define CLOCK_TASKS_CAL_TASKS_CAL_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CLOCK_TASKS_CTSTART */
+/* Description: Start calibration timer */
+
+/* Bit 0 : Start calibration timer */
+#define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos (0UL) /*!< Position of TASKS_CTSTART field. */
+#define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Msk (0x1UL << CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos) /*!< Bit mask of TASKS_CTSTART field. */
+#define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CLOCK_TASKS_CTSTOP */
+/* Description: Stop calibration timer */
+
+/* Bit 0 : Stop calibration timer */
+#define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos (0UL) /*!< Position of TASKS_CTSTOP field. */
+#define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Msk (0x1UL << CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos) /*!< Bit mask of TASKS_CTSTOP field. */
+#define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CLOCK_EVENTS_HFCLKSTARTED */
+/* Description: HFCLK oscillator started */
+
+/* Bit 0 : HFCLK oscillator started */
+#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */
+#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */
+#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: CLOCK_EVENTS_LFCLKSTARTED */
+/* Description: LFCLK started */
+
+/* Bit 0 : LFCLK started */
+#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */
+#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */
+#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: CLOCK_EVENTS_DONE */
+/* Description: Calibration of LFCLK RC oscillator complete event */
+
+/* Bit 0 : Calibration of LFCLK RC oscillator complete event */
+#define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */
+#define CLOCK_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CLOCK_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */
+#define CLOCK_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */
+#define CLOCK_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */
+
+/* Register: CLOCK_EVENTS_CTTO */
+/* Description: Calibration timer timeout */
+
+/* Bit 0 : Calibration timer timeout */
+#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos (0UL) /*!< Position of EVENTS_CTTO field. */
+#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Msk (0x1UL << CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos) /*!< Bit mask of EVENTS_CTTO field. */
+#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_NotGenerated (0UL) /*!< Event not generated */
+#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Generated (1UL) /*!< Event generated */
+
/* Register: CLOCK_INTENSET */
/* Description: Enable interrupt */
-/* Bit 4 : Write '1' to Enable interrupt for CTTO event */
+/* Bit 4 : Write '1' to enable interrupt for event CTTO */
#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */
#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */
#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */
-/* Bit 3 : Write '1' to Enable interrupt for DONE event */
+/* Bit 3 : Write '1' to enable interrupt for event DONE */
#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */
-/* Bit 1 : Write '1' to Enable interrupt for LFCLKSTARTED event */
+/* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */
#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
-/* Bit 0 : Write '1' to Enable interrupt for HFCLKSTARTED event */
+/* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */
#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
@@ -1111,28 +1298,28 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: CLOCK_INTENCLR */
/* Description: Disable interrupt */
-/* Bit 4 : Write '1' to Disable interrupt for CTTO event */
+/* Bit 4 : Write '1' to disable interrupt for event CTTO */
#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */
#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */
#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */
-/* Bit 3 : Write '1' to Disable interrupt for DONE event */
+/* Bit 3 : Write '1' to disable interrupt for event DONE */
#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */
-/* Bit 1 : Write '1' to Disable interrupt for LFCLKSTARTED event */
+/* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */
#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
-/* Bit 0 : Write '1' to Disable interrupt for HFCLKSTARTED event */
+/* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */
#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
@@ -1249,34 +1436,94 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: COMP */
/* Description: Comparator */
+/* Register: COMP_TASKS_START */
+/* Description: Start comparator */
+
+/* Bit 0 : Start comparator */
+#define COMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define COMP_TASKS_START_TASKS_START_Msk (0x1UL << COMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define COMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: COMP_TASKS_STOP */
+/* Description: Stop comparator */
+
+/* Bit 0 : Stop comparator */
+#define COMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define COMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << COMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define COMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: COMP_TASKS_SAMPLE */
+/* Description: Sample comparator value */
+
+/* Bit 0 : Sample comparator value */
+#define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
+#define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
+#define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: COMP_EVENTS_READY */
+/* Description: COMP is ready and output is valid */
+
+/* Bit 0 : COMP is ready and output is valid */
+#define COMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
+#define COMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << COMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
+#define COMP_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
+#define COMP_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
+
+/* Register: COMP_EVENTS_DOWN */
+/* Description: Downward crossing */
+
+/* Bit 0 : Downward crossing */
+#define COMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */
+#define COMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << COMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */
+#define COMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0UL) /*!< Event not generated */
+#define COMP_EVENTS_DOWN_EVENTS_DOWN_Generated (1UL) /*!< Event generated */
+
+/* Register: COMP_EVENTS_UP */
+/* Description: Upward crossing */
+
+/* Bit 0 : Upward crossing */
+#define COMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */
+#define COMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << COMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */
+#define COMP_EVENTS_UP_EVENTS_UP_NotGenerated (0UL) /*!< Event not generated */
+#define COMP_EVENTS_UP_EVENTS_UP_Generated (1UL) /*!< Event generated */
+
+/* Register: COMP_EVENTS_CROSS */
+/* Description: Downward or upward crossing */
+
+/* Bit 0 : Downward or upward crossing */
+#define COMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */
+#define COMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << COMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */
+#define COMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0UL) /*!< Event not generated */
+#define COMP_EVENTS_CROSS_EVENTS_CROSS_Generated (1UL) /*!< Event generated */
+
/* Register: COMP_SHORTS */
-/* Description: Shortcut register */
+/* Description: Shortcuts between local events and tasks */
-/* Bit 4 : Shortcut between CROSS event and STOP task */
+/* Bit 4 : Shortcut between event CROSS and task STOP */
#define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
#define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
#define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
#define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 3 : Shortcut between UP event and STOP task */
+/* Bit 3 : Shortcut between event UP and task STOP */
#define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
#define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
#define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
#define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 2 : Shortcut between DOWN event and STOP task */
+/* Bit 2 : Shortcut between event DOWN and task STOP */
#define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
#define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
#define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
#define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 1 : Shortcut between READY event and STOP task */
+/* Bit 1 : Shortcut between event READY and task STOP */
#define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
#define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
#define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
#define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 0 : Shortcut between READY event and SAMPLE task */
+/* Bit 0 : Shortcut between event READY and task SAMPLE */
#define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
#define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
#define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
@@ -1285,25 +1532,25 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: COMP_INTEN */
/* Description: Enable or disable interrupt */
-/* Bit 3 : Enable or disable interrupt for CROSS event */
+/* Bit 3 : Enable or disable interrupt for event CROSS */
#define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */
#define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */
#define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */
#define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */
-/* Bit 2 : Enable or disable interrupt for UP event */
+/* Bit 2 : Enable or disable interrupt for event UP */
#define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */
#define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */
#define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */
#define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */
-/* Bit 1 : Enable or disable interrupt for DOWN event */
+/* Bit 1 : Enable or disable interrupt for event DOWN */
#define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */
#define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */
#define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */
#define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */
-/* Bit 0 : Enable or disable interrupt for READY event */
+/* Bit 0 : Enable or disable interrupt for event READY */
#define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
#define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */
#define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */
@@ -1312,28 +1559,28 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: COMP_INTENSET */
/* Description: Enable interrupt */
-/* Bit 3 : Write '1' to Enable interrupt for CROSS event */
+/* Bit 3 : Write '1' to enable interrupt for event CROSS */
#define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
#define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
#define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
#define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
#define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
-/* Bit 2 : Write '1' to Enable interrupt for UP event */
+/* Bit 2 : Write '1' to enable interrupt for event UP */
#define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
#define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
#define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
#define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
#define COMP_INTENSET_UP_Set (1UL) /*!< Enable */
-/* Bit 1 : Write '1' to Enable interrupt for DOWN event */
+/* Bit 1 : Write '1' to enable interrupt for event DOWN */
#define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
#define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
#define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
#define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
#define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
-/* Bit 0 : Write '1' to Enable interrupt for READY event */
+/* Bit 0 : Write '1' to enable interrupt for event READY */
#define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
#define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
#define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
@@ -1343,28 +1590,28 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: COMP_INTENCLR */
/* Description: Disable interrupt */
-/* Bit 3 : Write '1' to Disable interrupt for CROSS event */
+/* Bit 3 : Write '1' to disable interrupt for event CROSS */
#define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
#define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
#define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
#define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
#define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
-/* Bit 2 : Write '1' to Disable interrupt for UP event */
+/* Bit 2 : Write '1' to disable interrupt for event UP */
#define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
#define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
#define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
#define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
#define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
-/* Bit 1 : Write '1' to Disable interrupt for DOWN event */
+/* Bit 1 : Write '1' to disable interrupt for event DOWN */
#define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
#define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
#define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
#define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
#define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
-/* Bit 0 : Write '1' to Disable interrupt for READY event */
+/* Bit 0 : Write '1' to disable interrupt for event READY */
#define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
#define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
#define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
@@ -1482,17 +1729,51 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: ECB */
/* Description: AES ECB Mode Encryption */
+/* Register: ECB_TASKS_STARTECB */
+/* Description: Start ECB block encrypt */
+
+/* Bit 0 : Start ECB block encrypt */
+#define ECB_TASKS_STARTECB_TASKS_STARTECB_Pos (0UL) /*!< Position of TASKS_STARTECB field. */
+#define ECB_TASKS_STARTECB_TASKS_STARTECB_Msk (0x1UL << ECB_TASKS_STARTECB_TASKS_STARTECB_Pos) /*!< Bit mask of TASKS_STARTECB field. */
+#define ECB_TASKS_STARTECB_TASKS_STARTECB_Trigger (1UL) /*!< Trigger task */
+
+/* Register: ECB_TASKS_STOPECB */
+/* Description: Abort a possible executing ECB operation */
+
+/* Bit 0 : Abort a possible executing ECB operation */
+#define ECB_TASKS_STOPECB_TASKS_STOPECB_Pos (0UL) /*!< Position of TASKS_STOPECB field. */
+#define ECB_TASKS_STOPECB_TASKS_STOPECB_Msk (0x1UL << ECB_TASKS_STOPECB_TASKS_STOPECB_Pos) /*!< Bit mask of TASKS_STOPECB field. */
+#define ECB_TASKS_STOPECB_TASKS_STOPECB_Trigger (1UL) /*!< Trigger task */
+
+/* Register: ECB_EVENTS_ENDECB */
+/* Description: ECB block encrypt complete */
+
+/* Bit 0 : ECB block encrypt complete */
+#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos (0UL) /*!< Position of EVENTS_ENDECB field. */
+#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Msk (0x1UL << ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos) /*!< Bit mask of EVENTS_ENDECB field. */
+#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_NotGenerated (0UL) /*!< Event not generated */
+#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Generated (1UL) /*!< Event generated */
+
+/* Register: ECB_EVENTS_ERRORECB */
+/* Description: ECB block encrypt aborted because of a STOPECB task or due to an error */
+
+/* Bit 0 : ECB block encrypt aborted because of a STOPECB task or due to an error */
+#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos (0UL) /*!< Position of EVENTS_ERRORECB field. */
+#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Msk (0x1UL << ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos) /*!< Bit mask of EVENTS_ERRORECB field. */
+#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_NotGenerated (0UL) /*!< Event not generated */
+#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Generated (1UL) /*!< Event generated */
+
/* Register: ECB_INTENSET */
/* Description: Enable interrupt */
-/* Bit 1 : Write '1' to Enable interrupt for ERRORECB event */
+/* Bit 1 : Write '1' to enable interrupt for event ERRORECB */
#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */
-/* Bit 0 : Write '1' to Enable interrupt for ENDECB event */
+/* Bit 0 : Write '1' to enable interrupt for event ENDECB */
#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */
@@ -1502,14 +1783,14 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: ECB_INTENCLR */
/* Description: Disable interrupt */
-/* Bit 1 : Write '1' to Disable interrupt for ERRORECB event */
+/* Bit 1 : Write '1' to disable interrupt for event ERRORECB */
#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */
-/* Bit 0 : Write '1' to Disable interrupt for ENDECB event */
+/* Bit 0 : Write '1' to disable interrupt for event ENDECB */
#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */
@@ -1527,100 +1808,117 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: EGU */
/* Description: Event Generator Unit 0 */
+/* Register: EGU_TASKS_TRIGGER */
+/* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */
+
+/* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */
+#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */
+#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */
+#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL) /*!< Trigger task */
+
+/* Register: EGU_EVENTS_TRIGGERED */
+/* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */
+
+/* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */
+#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */
+#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */
+#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0UL) /*!< Event not generated */
+#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL) /*!< Event generated */
+
/* Register: EGU_INTEN */
/* Description: Enable or disable interrupt */
-/* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */
+/* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */
#define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
#define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
#define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
-/* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */
+/* Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */
#define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
#define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
#define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
-/* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */
+/* Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */
#define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
#define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
#define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
-/* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */
+/* Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */
#define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
#define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
#define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
-/* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */
+/* Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */
#define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
#define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
#define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
-/* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */
+/* Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */
#define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
#define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
#define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
-/* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */
+/* Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */
#define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
#define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
#define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
-/* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */
+/* Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */
#define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
#define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
#define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
-/* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */
+/* Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */
#define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
#define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
#define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
-/* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */
+/* Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */
#define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
#define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
#define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
-/* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */
+/* Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */
#define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
#define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
#define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
-/* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */
+/* Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */
#define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
#define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
#define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
-/* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */
+/* Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */
#define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
#define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
#define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
-/* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */
+/* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */
#define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
#define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
#define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
-/* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */
+/* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */
#define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
#define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
#define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
-/* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */
+/* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */
#define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
#define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
#define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
@@ -1629,112 +1927,112 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: EGU_INTENSET */
/* Description: Enable interrupt */
-/* Bit 15 : Write '1' to Enable interrupt for TRIGGERED[15] event */
+/* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */
#define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
#define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
#define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
-/* Bit 14 : Write '1' to Enable interrupt for TRIGGERED[14] event */
+/* Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */
#define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
#define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
#define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
-/* Bit 13 : Write '1' to Enable interrupt for TRIGGERED[13] event */
+/* Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */
#define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
#define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
#define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
-/* Bit 12 : Write '1' to Enable interrupt for TRIGGERED[12] event */
+/* Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */
#define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
#define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
#define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
-/* Bit 11 : Write '1' to Enable interrupt for TRIGGERED[11] event */
+/* Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */
#define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
#define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
#define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
-/* Bit 10 : Write '1' to Enable interrupt for TRIGGERED[10] event */
+/* Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */
#define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
#define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
#define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
-/* Bit 9 : Write '1' to Enable interrupt for TRIGGERED[9] event */
+/* Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */
#define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
#define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
#define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
-/* Bit 8 : Write '1' to Enable interrupt for TRIGGERED[8] event */
+/* Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */
#define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
#define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
#define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
-/* Bit 7 : Write '1' to Enable interrupt for TRIGGERED[7] event */
+/* Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */
#define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
#define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
#define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
-/* Bit 6 : Write '1' to Enable interrupt for TRIGGERED[6] event */
+/* Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */
#define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
#define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
#define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
-/* Bit 5 : Write '1' to Enable interrupt for TRIGGERED[5] event */
+/* Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */
#define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
#define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
#define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
-/* Bit 4 : Write '1' to Enable interrupt for TRIGGERED[4] event */
+/* Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */
#define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
#define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
#define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
-/* Bit 3 : Write '1' to Enable interrupt for TRIGGERED[3] event */
+/* Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */
#define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
#define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
#define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
-/* Bit 2 : Write '1' to Enable interrupt for TRIGGERED[2] event */
+/* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */
#define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
#define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
#define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
-/* Bit 1 : Write '1' to Enable interrupt for TRIGGERED[1] event */
+/* Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */
#define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
#define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
#define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
-/* Bit 0 : Write '1' to Enable interrupt for TRIGGERED[0] event */
+/* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */
#define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
#define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
#define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
@@ -1744,112 +2042,112 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: EGU_INTENCLR */
/* Description: Disable interrupt */
-/* Bit 15 : Write '1' to Disable interrupt for TRIGGERED[15] event */
+/* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */
#define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
#define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
#define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
-/* Bit 14 : Write '1' to Disable interrupt for TRIGGERED[14] event */
+/* Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */
#define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
#define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
#define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
-/* Bit 13 : Write '1' to Disable interrupt for TRIGGERED[13] event */
+/* Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */
#define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
#define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
#define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
-/* Bit 12 : Write '1' to Disable interrupt for TRIGGERED[12] event */
+/* Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */
#define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
#define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
#define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
-/* Bit 11 : Write '1' to Disable interrupt for TRIGGERED[11] event */
+/* Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */
#define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
#define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
#define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
-/* Bit 10 : Write '1' to Disable interrupt for TRIGGERED[10] event */
+/* Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */
#define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
#define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
#define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
-/* Bit 9 : Write '1' to Disable interrupt for TRIGGERED[9] event */
+/* Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */
#define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
#define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
#define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
-/* Bit 8 : Write '1' to Disable interrupt for TRIGGERED[8] event */
+/* Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */
#define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
#define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
#define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
-/* Bit 7 : Write '1' to Disable interrupt for TRIGGERED[7] event */
+/* Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */
#define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
#define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
#define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
-/* Bit 6 : Write '1' to Disable interrupt for TRIGGERED[6] event */
+/* Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */
#define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
#define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
#define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
-/* Bit 5 : Write '1' to Disable interrupt for TRIGGERED[5] event */
+/* Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */
#define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
#define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
#define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
-/* Bit 4 : Write '1' to Disable interrupt for TRIGGERED[4] event */
+/* Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */
#define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
#define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
#define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
-/* Bit 3 : Write '1' to Disable interrupt for TRIGGERED[3] event */
+/* Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */
#define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
#define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
#define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
-/* Bit 2 : Write '1' to Disable interrupt for TRIGGERED[2] event */
+/* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */
#define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
#define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
#define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
-/* Bit 1 : Write '1' to Disable interrupt for TRIGGERED[1] event */
+/* Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */
#define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
#define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
#define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
-/* Bit 0 : Write '1' to Disable interrupt for TRIGGERED[0] event */
+/* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */
#define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
#define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
#define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
@@ -1875,21 +2173,21 @@ POSSIBILITY OF SUCH DAMAGE.
#define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */
/* Register: FICR_DEVICEID */
-/* Description: Description collection[0]: Device identifier */
+/* Description: Description collection: Device identifier */
/* Bits 31..0 : 64 bit unique device identifier */
#define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */
#define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */
/* Register: FICR_ER */
-/* Description: Description collection[0]: Encryption Root, word 0 */
+/* Description: Description collection: Encryption Root, word n */
/* Bits 31..0 : Encryption Root, word n */
#define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */
#define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */
/* Register: FICR_IR */
-/* Description: Description collection[0]: Identity Root, word 0 */
+/* Description: Description collection: Identity Root, word n */
/* Bits 31..0 : Identity Root, word n */
#define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */
@@ -1905,7 +2203,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */
/* Register: FICR_DEVICEADDR */
-/* Description: Description collection[0]: Device address 0 */
+/* Description: Description collection: Device address n */
/* Bits 31..0 : 48 bit device address */
#define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */
@@ -1927,11 +2225,17 @@ POSSIBILITY OF SUCH DAMAGE.
#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
#define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */
-#define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */
+#define FICR_INFO_VARIANT_VARIANT_AAAC (0x41414143UL) /*!< AAAC */
#define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */
#define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */
#define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */
#define FICR_INFO_VARIANT_VARIANT_AAE0 (0x41414530UL) /*!< AAE0 */
+#define FICR_INFO_VARIANT_VARIANT_AAG0 (0x41414730UL) /*!< AAG0 */
+#define FICR_INFO_VARIANT_VARIANT_AAGB (0x41414742UL) /*!< AAGB */
+#define FICR_INFO_VARIANT_VARIANT_ABB0 (0x41424230UL) /*!< ABB0 */
+#define FICR_INFO_VARIANT_VARIANT_ABE0 (0x41424530UL) /*!< ABE0 */
+#define FICR_INFO_VARIANT_VARIANT_ABG0 (0x41424730UL) /*!< ABG0 */
+#define FICR_INFO_VARIANT_VARIANT_ABGB (0x41424742UL) /*!< ABGB */
#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
/* Register: FICR_INFO_PACKAGE */
@@ -2167,66 +2471,108 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: GPIOTE */
/* Description: GPIO Tasks and Events */
+/* Register: GPIOTE_TASKS_OUT */
+/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
+
+/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
+#define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */
+#define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */
+#define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (1UL) /*!< Trigger task */
+
+/* Register: GPIOTE_TASKS_SET */
+/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
+
+/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
+#define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */
+#define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */
+#define GPIOTE_TASKS_SET_TASKS_SET_Trigger (1UL) /*!< Trigger task */
+
+/* Register: GPIOTE_TASKS_CLR */
+/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
+
+/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
+#define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */
+#define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */
+#define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (1UL) /*!< Trigger task */
+
+/* Register: GPIOTE_EVENTS_IN */
+/* Description: Description collection: Event generated from pin specified in CONFIG[n].PSEL */
+
+/* Bit 0 : Event generated from pin specified in CONFIG[n].PSEL */
+#define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */
+#define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */
+#define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0UL) /*!< Event not generated */
+#define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (1UL) /*!< Event generated */
+
+/* Register: GPIOTE_EVENTS_PORT */
+/* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */
+
+/* Bit 0 : Event generated from multiple input GPIO pins with SENSE mechanism enabled */
+#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */
+#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */
+#define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0UL) /*!< Event not generated */
+#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (1UL) /*!< Event generated */
+
/* Register: GPIOTE_INTENSET */
/* Description: Enable interrupt */
-/* Bit 31 : Write '1' to Enable interrupt for PORT event */
+/* Bit 31 : Write '1' to enable interrupt for event PORT */
#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
-/* Bit 7 : Write '1' to Enable interrupt for IN[7] event */
+/* Bit 7 : Write '1' to enable interrupt for event IN[7] */
#define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */
#define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */
#define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
-/* Bit 6 : Write '1' to Enable interrupt for IN[6] event */
+/* Bit 6 : Write '1' to enable interrupt for event IN[6] */
#define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */
#define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */
#define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
-/* Bit 5 : Write '1' to Enable interrupt for IN[5] event */
+/* Bit 5 : Write '1' to enable interrupt for event IN[5] */
#define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */
#define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */
#define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
-/* Bit 4 : Write '1' to Enable interrupt for IN[4] event */
+/* Bit 4 : Write '1' to enable interrupt for event IN[4] */
#define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */
#define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */
#define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
-/* Bit 3 : Write '1' to Enable interrupt for IN[3] event */
+/* Bit 3 : Write '1' to enable interrupt for event IN[3] */
#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
-/* Bit 2 : Write '1' to Enable interrupt for IN[2] event */
+/* Bit 2 : Write '1' to enable interrupt for event IN[2] */
#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
-/* Bit 1 : Write '1' to Enable interrupt for IN[1] event */
+/* Bit 1 : Write '1' to enable interrupt for event IN[1] */
#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
-/* Bit 0 : Write '1' to Enable interrupt for IN[0] event */
+/* Bit 0 : Write '1' to enable interrupt for event IN[0] */
#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
@@ -2236,63 +2582,63 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: GPIOTE_INTENCLR */
/* Description: Disable interrupt */
-/* Bit 31 : Write '1' to Disable interrupt for PORT event */
+/* Bit 31 : Write '1' to disable interrupt for event PORT */
#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
-/* Bit 7 : Write '1' to Disable interrupt for IN[7] event */
+/* Bit 7 : Write '1' to disable interrupt for event IN[7] */
#define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */
#define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */
#define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
-/* Bit 6 : Write '1' to Disable interrupt for IN[6] event */
+/* Bit 6 : Write '1' to disable interrupt for event IN[6] */
#define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */
#define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */
#define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
-/* Bit 5 : Write '1' to Disable interrupt for IN[5] event */
+/* Bit 5 : Write '1' to disable interrupt for event IN[5] */
#define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */
#define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */
#define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
-/* Bit 4 : Write '1' to Disable interrupt for IN[4] event */
+/* Bit 4 : Write '1' to disable interrupt for event IN[4] */
#define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */
#define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */
#define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
-/* Bit 3 : Write '1' to Disable interrupt for IN[3] event */
+/* Bit 3 : Write '1' to disable interrupt for event IN[3] */
#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
-/* Bit 2 : Write '1' to Disable interrupt for IN[2] event */
+/* Bit 2 : Write '1' to disable interrupt for event IN[2] */
#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
-/* Bit 1 : Write '1' to Disable interrupt for IN[1] event */
+/* Bit 1 : Write '1' to disable interrupt for event IN[1] */
#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
-/* Bit 0 : Write '1' to Disable interrupt for IN[0] event */
+/* Bit 0 : Write '1' to disable interrupt for event IN[0] */
#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
@@ -2300,7 +2646,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
/* Register: GPIOTE_CONFIG */
-/* Description: Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */
+/* Description: Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */
/* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
@@ -2331,22 +2677,69 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: I2S */
/* Description: Inter-IC Sound */
+/* Register: I2S_TASKS_START */
+/* Description: Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */
+
+/* Bit 0 : Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */
+#define I2S_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define I2S_TASKS_START_TASKS_START_Msk (0x1UL << I2S_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define I2S_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: I2S_TASKS_STOP */
+/* Description: Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the {event:STOPPED} event to be generated. */
+
+/* Bit 0 : Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the {event:STOPPED} event to be generated. */
+#define I2S_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define I2S_TASKS_STOP_TASKS_STOP_Msk (0x1UL << I2S_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define I2S_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: I2S_EVENTS_RXPTRUPD */
+/* Description: The RXD.PTR register has been copied to internal double-buffers.
+ When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */
+
+/* Bit 0 : The RXD.PTR register has been copied to internal double-buffers.
+ When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */
+#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos (0UL) /*!< Position of EVENTS_RXPTRUPD field. */
+#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Msk (0x1UL << I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos) /*!< Bit mask of EVENTS_RXPTRUPD field. */
+#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_NotGenerated (0UL) /*!< Event not generated */
+#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Generated (1UL) /*!< Event generated */
+
+/* Register: I2S_EVENTS_STOPPED */
+/* Description: I2S transfer stopped. */
+
+/* Bit 0 : I2S transfer stopped. */
+#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
+#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
+#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: I2S_EVENTS_TXPTRUPD */
+/* Description: The TDX.PTR register has been copied to internal double-buffers.
+ When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */
+
+/* Bit 0 : The TDX.PTR register has been copied to internal double-buffers.
+ When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */
+#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos (0UL) /*!< Position of EVENTS_TXPTRUPD field. */
+#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Msk (0x1UL << I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos) /*!< Bit mask of EVENTS_TXPTRUPD field. */
+#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_NotGenerated (0UL) /*!< Event not generated */
+#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Generated (1UL) /*!< Event generated */
+
/* Register: I2S_INTEN */
/* Description: Enable or disable interrupt */
-/* Bit 5 : Enable or disable interrupt for TXPTRUPD event */
+/* Bit 5 : Enable or disable interrupt for event TXPTRUPD */
#define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
#define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
#define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */
#define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */
-/* Bit 2 : Enable or disable interrupt for STOPPED event */
+/* Bit 2 : Enable or disable interrupt for event STOPPED */
#define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
#define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
#define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
-/* Bit 1 : Enable or disable interrupt for RXPTRUPD event */
+/* Bit 1 : Enable or disable interrupt for event RXPTRUPD */
#define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
#define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
#define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */
@@ -2355,21 +2748,21 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: I2S_INTENSET */
/* Description: Enable interrupt */
-/* Bit 5 : Write '1' to Enable interrupt for TXPTRUPD event */
+/* Bit 5 : Write '1' to enable interrupt for event TXPTRUPD */
#define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
#define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
#define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
#define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
#define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */
-/* Bit 2 : Write '1' to Enable interrupt for STOPPED event */
+/* Bit 2 : Write '1' to enable interrupt for event STOPPED */
#define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
#define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */
-/* Bit 1 : Write '1' to Enable interrupt for RXPTRUPD event */
+/* Bit 1 : Write '1' to enable interrupt for event RXPTRUPD */
#define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
#define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
#define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
@@ -2379,21 +2772,21 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: I2S_INTENCLR */
/* Description: Disable interrupt */
-/* Bit 5 : Write '1' to Disable interrupt for TXPTRUPD event */
+/* Bit 5 : Write '1' to disable interrupt for event TXPTRUPD */
#define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
#define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
#define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
#define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
#define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */
-/* Bit 2 : Write '1' to Disable interrupt for STOPPED event */
+/* Bit 2 : Write '1' to disable interrupt for event STOPPED */
#define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
#define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
-/* Bit 1 : Write '1' to Disable interrupt for RXPTRUPD event */
+/* Bit 1 : Write '1' to disable interrupt for event RXPTRUPD */
#define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
#define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
#define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
@@ -2614,34 +3007,94 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: LPCOMP */
/* Description: Low Power Comparator */
+/* Register: LPCOMP_TASKS_START */
+/* Description: Start comparator */
+
+/* Bit 0 : Start comparator */
+#define LPCOMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define LPCOMP_TASKS_START_TASKS_START_Msk (0x1UL << LPCOMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define LPCOMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: LPCOMP_TASKS_STOP */
+/* Description: Stop comparator */
+
+/* Bit 0 : Stop comparator */
+#define LPCOMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define LPCOMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << LPCOMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define LPCOMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: LPCOMP_TASKS_SAMPLE */
+/* Description: Sample comparator value */
+
+/* Bit 0 : Sample comparator value */
+#define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
+#define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
+#define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: LPCOMP_EVENTS_READY */
+/* Description: LPCOMP is ready and output is valid */
+
+/* Bit 0 : LPCOMP is ready and output is valid */
+#define LPCOMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
+#define LPCOMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << LPCOMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
+#define LPCOMP_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
+#define LPCOMP_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
+
+/* Register: LPCOMP_EVENTS_DOWN */
+/* Description: Downward crossing */
+
+/* Bit 0 : Downward crossing */
+#define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */
+#define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */
+#define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0UL) /*!< Event not generated */
+#define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Generated (1UL) /*!< Event generated */
+
+/* Register: LPCOMP_EVENTS_UP */
+/* Description: Upward crossing */
+
+/* Bit 0 : Upward crossing */
+#define LPCOMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */
+#define LPCOMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << LPCOMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */
+#define LPCOMP_EVENTS_UP_EVENTS_UP_NotGenerated (0UL) /*!< Event not generated */
+#define LPCOMP_EVENTS_UP_EVENTS_UP_Generated (1UL) /*!< Event generated */
+
+/* Register: LPCOMP_EVENTS_CROSS */
+/* Description: Downward or upward crossing */
+
+/* Bit 0 : Downward or upward crossing */
+#define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */
+#define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */
+#define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0UL) /*!< Event not generated */
+#define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Generated (1UL) /*!< Event generated */
+
/* Register: LPCOMP_SHORTS */
-/* Description: Shortcut register */
+/* Description: Shortcuts between local events and tasks */
-/* Bit 4 : Shortcut between CROSS event and STOP task */
+/* Bit 4 : Shortcut between event CROSS and task STOP */
#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 3 : Shortcut between UP event and STOP task */
+/* Bit 3 : Shortcut between event UP and task STOP */
#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 2 : Shortcut between DOWN event and STOP task */
+/* Bit 2 : Shortcut between event DOWN and task STOP */
#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 1 : Shortcut between READY event and STOP task */
+/* Bit 1 : Shortcut between event READY and task STOP */
#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 0 : Shortcut between READY event and SAMPLE task */
+/* Bit 0 : Shortcut between event READY and task SAMPLE */
#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
@@ -2650,28 +3103,28 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: LPCOMP_INTENSET */
/* Description: Enable interrupt */
-/* Bit 3 : Write '1' to Enable interrupt for CROSS event */
+/* Bit 3 : Write '1' to enable interrupt for event CROSS */
#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
-/* Bit 2 : Write '1' to Enable interrupt for UP event */
+/* Bit 2 : Write '1' to enable interrupt for event UP */
#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */
-/* Bit 1 : Write '1' to Enable interrupt for DOWN event */
+/* Bit 1 : Write '1' to enable interrupt for event DOWN */
#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
-/* Bit 0 : Write '1' to Enable interrupt for READY event */
+/* Bit 0 : Write '1' to enable interrupt for event READY */
#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
@@ -2681,28 +3134,28 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: LPCOMP_INTENCLR */
/* Description: Disable interrupt */
-/* Bit 3 : Write '1' to Disable interrupt for CROSS event */
+/* Bit 3 : Write '1' to disable interrupt for event CROSS */
#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
-/* Bit 2 : Write '1' to Disable interrupt for UP event */
+/* Bit 2 : Write '1' to disable interrupt for event UP */
#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
-/* Bit 1 : Write '1' to Disable interrupt for DOWN event */
+/* Bit 1 : Write '1' to disable interrupt for event DOWN */
#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
-/* Bit 0 : Write '1' to Disable interrupt for READY event */
+/* Bit 0 : Write '1' to disable interrupt for event READY */
#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
@@ -2797,76 +3250,112 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: MWU */
/* Description: Memory Watch Unit */
+/* Register: MWU_EVENTS_REGION_WA */
+/* Description: Description cluster: Write access to region n detected */
+
+/* Bit 0 : Write access to region n detected */
+#define MWU_EVENTS_REGION_WA_WA_Pos (0UL) /*!< Position of WA field. */
+#define MWU_EVENTS_REGION_WA_WA_Msk (0x1UL << MWU_EVENTS_REGION_WA_WA_Pos) /*!< Bit mask of WA field. */
+#define MWU_EVENTS_REGION_WA_WA_NotGenerated (0UL) /*!< Event not generated */
+#define MWU_EVENTS_REGION_WA_WA_Generated (1UL) /*!< Event generated */
+
+/* Register: MWU_EVENTS_REGION_RA */
+/* Description: Description cluster: Read access to region n detected */
+
+/* Bit 0 : Read access to region n detected */
+#define MWU_EVENTS_REGION_RA_RA_Pos (0UL) /*!< Position of RA field. */
+#define MWU_EVENTS_REGION_RA_RA_Msk (0x1UL << MWU_EVENTS_REGION_RA_RA_Pos) /*!< Bit mask of RA field. */
+#define MWU_EVENTS_REGION_RA_RA_NotGenerated (0UL) /*!< Event not generated */
+#define MWU_EVENTS_REGION_RA_RA_Generated (1UL) /*!< Event generated */
+
+/* Register: MWU_EVENTS_PREGION_WA */
+/* Description: Description cluster: Write access to peripheral region n detected */
+
+/* Bit 0 : Write access to peripheral region n detected */
+#define MWU_EVENTS_PREGION_WA_WA_Pos (0UL) /*!< Position of WA field. */
+#define MWU_EVENTS_PREGION_WA_WA_Msk (0x1UL << MWU_EVENTS_PREGION_WA_WA_Pos) /*!< Bit mask of WA field. */
+#define MWU_EVENTS_PREGION_WA_WA_NotGenerated (0UL) /*!< Event not generated */
+#define MWU_EVENTS_PREGION_WA_WA_Generated (1UL) /*!< Event generated */
+
+/* Register: MWU_EVENTS_PREGION_RA */
+/* Description: Description cluster: Read access to peripheral region n detected */
+
+/* Bit 0 : Read access to peripheral region n detected */
+#define MWU_EVENTS_PREGION_RA_RA_Pos (0UL) /*!< Position of RA field. */
+#define MWU_EVENTS_PREGION_RA_RA_Msk (0x1UL << MWU_EVENTS_PREGION_RA_RA_Pos) /*!< Bit mask of RA field. */
+#define MWU_EVENTS_PREGION_RA_RA_NotGenerated (0UL) /*!< Event not generated */
+#define MWU_EVENTS_PREGION_RA_RA_Generated (1UL) /*!< Event generated */
+
/* Register: MWU_INTEN */
/* Description: Enable or disable interrupt */
-/* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */
+/* Bit 27 : Enable or disable interrupt for event PREGION1RA */
#define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
#define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
#define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */
-/* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */
+/* Bit 26 : Enable or disable interrupt for event PREGION1WA */
#define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
#define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
#define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */
-/* Bit 25 : Enable or disable interrupt for PREGION[0].RA event */
+/* Bit 25 : Enable or disable interrupt for event PREGION0RA */
#define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
#define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
#define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */
-/* Bit 24 : Enable or disable interrupt for PREGION[0].WA event */
+/* Bit 24 : Enable or disable interrupt for event PREGION0WA */
#define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
#define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
#define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */
-/* Bit 7 : Enable or disable interrupt for REGION[3].RA event */
+/* Bit 7 : Enable or disable interrupt for event REGION3RA */
#define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
#define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
#define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */
-/* Bit 6 : Enable or disable interrupt for REGION[3].WA event */
+/* Bit 6 : Enable or disable interrupt for event REGION3WA */
#define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
#define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
#define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */
-/* Bit 5 : Enable or disable interrupt for REGION[2].RA event */
+/* Bit 5 : Enable or disable interrupt for event REGION2RA */
#define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
#define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
#define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */
-/* Bit 4 : Enable or disable interrupt for REGION[2].WA event */
+/* Bit 4 : Enable or disable interrupt for event REGION2WA */
#define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
#define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
#define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */
-/* Bit 3 : Enable or disable interrupt for REGION[1].RA event */
+/* Bit 3 : Enable or disable interrupt for event REGION1RA */
#define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
#define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
#define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */
-/* Bit 2 : Enable or disable interrupt for REGION[1].WA event */
+/* Bit 2 : Enable or disable interrupt for event REGION1WA */
#define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
#define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
#define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */
-/* Bit 1 : Enable or disable interrupt for REGION[0].RA event */
+/* Bit 1 : Enable or disable interrupt for event REGION0RA */
#define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
#define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
#define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */
#define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */
-/* Bit 0 : Enable or disable interrupt for REGION[0].WA event */
+/* Bit 0 : Enable or disable interrupt for event REGION0WA */
#define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
#define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
#define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */
@@ -2875,84 +3364,84 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: MWU_INTENSET */
/* Description: Enable interrupt */
-/* Bit 27 : Write '1' to Enable interrupt for PREGION[1].RA event */
+/* Bit 27 : Write '1' to enable interrupt for event PREGION1RA */
#define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
#define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
#define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */
-/* Bit 26 : Write '1' to Enable interrupt for PREGION[1].WA event */
+/* Bit 26 : Write '1' to enable interrupt for event PREGION1WA */
#define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
#define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
#define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */
-/* Bit 25 : Write '1' to Enable interrupt for PREGION[0].RA event */
+/* Bit 25 : Write '1' to enable interrupt for event PREGION0RA */
#define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
#define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
#define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */
-/* Bit 24 : Write '1' to Enable interrupt for PREGION[0].WA event */
+/* Bit 24 : Write '1' to enable interrupt for event PREGION0WA */
#define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
#define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
#define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */
-/* Bit 7 : Write '1' to Enable interrupt for REGION[3].RA event */
+/* Bit 7 : Write '1' to enable interrupt for event REGION3RA */
#define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
#define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
#define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */
-/* Bit 6 : Write '1' to Enable interrupt for REGION[3].WA event */
+/* Bit 6 : Write '1' to enable interrupt for event REGION3WA */
#define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
#define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
#define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */
-/* Bit 5 : Write '1' to Enable interrupt for REGION[2].RA event */
+/* Bit 5 : Write '1' to enable interrupt for event REGION2RA */
#define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
#define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
#define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */
-/* Bit 4 : Write '1' to Enable interrupt for REGION[2].WA event */
+/* Bit 4 : Write '1' to enable interrupt for event REGION2WA */
#define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
#define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
#define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */
-/* Bit 3 : Write '1' to Enable interrupt for REGION[1].RA event */
+/* Bit 3 : Write '1' to enable interrupt for event REGION1RA */
#define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
#define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
#define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */
-/* Bit 2 : Write '1' to Enable interrupt for REGION[1].WA event */
+/* Bit 2 : Write '1' to enable interrupt for event REGION1WA */
#define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
#define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
#define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */
-/* Bit 1 : Write '1' to Enable interrupt for REGION[0].RA event */
+/* Bit 1 : Write '1' to enable interrupt for event REGION0RA */
#define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
#define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
#define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */
-/* Bit 0 : Write '1' to Enable interrupt for REGION[0].WA event */
+/* Bit 0 : Write '1' to enable interrupt for event REGION0WA */
#define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
#define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
#define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
@@ -2962,84 +3451,84 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: MWU_INTENCLR */
/* Description: Disable interrupt */
-/* Bit 27 : Write '1' to Disable interrupt for PREGION[1].RA event */
+/* Bit 27 : Write '1' to disable interrupt for event PREGION1RA */
#define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
#define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
#define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
-/* Bit 26 : Write '1' to Disable interrupt for PREGION[1].WA event */
+/* Bit 26 : Write '1' to disable interrupt for event PREGION1WA */
#define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
#define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
#define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
-/* Bit 25 : Write '1' to Disable interrupt for PREGION[0].RA event */
+/* Bit 25 : Write '1' to disable interrupt for event PREGION0RA */
#define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
#define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
#define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
-/* Bit 24 : Write '1' to Disable interrupt for PREGION[0].WA event */
+/* Bit 24 : Write '1' to disable interrupt for event PREGION0WA */
#define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
#define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
#define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
-/* Bit 7 : Write '1' to Disable interrupt for REGION[3].RA event */
+/* Bit 7 : Write '1' to disable interrupt for event REGION3RA */
#define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
#define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
#define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */
-/* Bit 6 : Write '1' to Disable interrupt for REGION[3].WA event */
+/* Bit 6 : Write '1' to disable interrupt for event REGION3WA */
#define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
#define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
#define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */
-/* Bit 5 : Write '1' to Disable interrupt for REGION[2].RA event */
+/* Bit 5 : Write '1' to disable interrupt for event REGION2RA */
#define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
#define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
#define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */
-/* Bit 4 : Write '1' to Disable interrupt for REGION[2].WA event */
+/* Bit 4 : Write '1' to disable interrupt for event REGION2WA */
#define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
#define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
#define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */
-/* Bit 3 : Write '1' to Disable interrupt for REGION[1].RA event */
+/* Bit 3 : Write '1' to disable interrupt for event REGION1RA */
#define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
#define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
#define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */
-/* Bit 2 : Write '1' to Disable interrupt for REGION[1].WA event */
+/* Bit 2 : Write '1' to disable interrupt for event REGION1WA */
#define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
#define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
#define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */
-/* Bit 1 : Write '1' to Disable interrupt for REGION[0].RA event */
+/* Bit 1 : Write '1' to disable interrupt for event REGION0RA */
#define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
#define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
#define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */
-/* Bit 0 : Write '1' to Disable interrupt for REGION[0].WA event */
+/* Bit 0 : Write '1' to disable interrupt for event REGION0WA */
#define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
#define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
#define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
@@ -3047,161 +3536,161 @@ POSSIBILITY OF SUCH DAMAGE.
#define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */
/* Register: MWU_NMIEN */
-/* Description: Enable or disable non-maskable interrupt */
+/* Description: Enable or disable interrupt */
-/* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */
+/* Bit 27 : Enable or disable interrupt for event PREGION1RA */
#define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
#define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
#define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */
-/* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */
+/* Bit 26 : Enable or disable interrupt for event PREGION1WA */
#define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
#define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
#define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */
-/* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */
+/* Bit 25 : Enable or disable interrupt for event PREGION0RA */
#define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
#define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
#define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */
-/* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */
+/* Bit 24 : Enable or disable interrupt for event PREGION0WA */
#define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
#define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
#define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */
-/* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */
+/* Bit 7 : Enable or disable interrupt for event REGION3RA */
#define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
#define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
#define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */
-/* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */
+/* Bit 6 : Enable or disable interrupt for event REGION3WA */
#define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
#define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
#define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */
-/* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */
+/* Bit 5 : Enable or disable interrupt for event REGION2RA */
#define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
#define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
#define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */
-/* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */
+/* Bit 4 : Enable or disable interrupt for event REGION2WA */
#define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
#define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
#define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */
-/* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */
+/* Bit 3 : Enable or disable interrupt for event REGION1RA */
#define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
#define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
#define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */
-/* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */
+/* Bit 2 : Enable or disable interrupt for event REGION1WA */
#define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
#define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
#define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */
-/* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */
+/* Bit 1 : Enable or disable interrupt for event REGION0RA */
#define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
#define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
#define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */
-/* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */
+/* Bit 0 : Enable or disable interrupt for event REGION0WA */
#define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
#define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
#define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */
#define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */
/* Register: MWU_NMIENSET */
-/* Description: Enable non-maskable interrupt */
+/* Description: Enable interrupt */
-/* Bit 27 : Write '1' to Enable non-maskable interrupt for PREGION[1].RA event */
+/* Bit 27 : Write '1' to enable interrupt for event PREGION1RA */
#define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
#define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
#define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */
-/* Bit 26 : Write '1' to Enable non-maskable interrupt for PREGION[1].WA event */
+/* Bit 26 : Write '1' to enable interrupt for event PREGION1WA */
#define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
#define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
#define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */
-/* Bit 25 : Write '1' to Enable non-maskable interrupt for PREGION[0].RA event */
+/* Bit 25 : Write '1' to enable interrupt for event PREGION0RA */
#define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
#define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
#define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */
-/* Bit 24 : Write '1' to Enable non-maskable interrupt for PREGION[0].WA event */
+/* Bit 24 : Write '1' to enable interrupt for event PREGION0WA */
#define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
#define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
#define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */
-/* Bit 7 : Write '1' to Enable non-maskable interrupt for REGION[3].RA event */
+/* Bit 7 : Write '1' to enable interrupt for event REGION3RA */
#define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
#define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
#define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */
-/* Bit 6 : Write '1' to Enable non-maskable interrupt for REGION[3].WA event */
+/* Bit 6 : Write '1' to enable interrupt for event REGION3WA */
#define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
#define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
#define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */
-/* Bit 5 : Write '1' to Enable non-maskable interrupt for REGION[2].RA event */
+/* Bit 5 : Write '1' to enable interrupt for event REGION2RA */
#define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
#define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
#define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */
-/* Bit 4 : Write '1' to Enable non-maskable interrupt for REGION[2].WA event */
+/* Bit 4 : Write '1' to enable interrupt for event REGION2WA */
#define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
#define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
#define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */
-/* Bit 3 : Write '1' to Enable non-maskable interrupt for REGION[1].RA event */
+/* Bit 3 : Write '1' to enable interrupt for event REGION1RA */
#define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
#define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
#define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */
-/* Bit 2 : Write '1' to Enable non-maskable interrupt for REGION[1].WA event */
+/* Bit 2 : Write '1' to enable interrupt for event REGION1WA */
#define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
#define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
#define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */
-/* Bit 1 : Write '1' to Enable non-maskable interrupt for REGION[0].RA event */
+/* Bit 1 : Write '1' to enable interrupt for event REGION0RA */
#define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
#define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
#define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */
-/* Bit 0 : Write '1' to Enable non-maskable interrupt for REGION[0].WA event */
+/* Bit 0 : Write '1' to enable interrupt for event REGION0WA */
#define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
#define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
#define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
@@ -3209,86 +3698,86 @@ POSSIBILITY OF SUCH DAMAGE.
#define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */
/* Register: MWU_NMIENCLR */
-/* Description: Disable non-maskable interrupt */
+/* Description: Disable interrupt */
-/* Bit 27 : Write '1' to Disable non-maskable interrupt for PREGION[1].RA event */
+/* Bit 27 : Write '1' to disable interrupt for event PREGION1RA */
#define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
#define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
#define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
-/* Bit 26 : Write '1' to Disable non-maskable interrupt for PREGION[1].WA event */
+/* Bit 26 : Write '1' to disable interrupt for event PREGION1WA */
#define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
#define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
#define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
-/* Bit 25 : Write '1' to Disable non-maskable interrupt for PREGION[0].RA event */
+/* Bit 25 : Write '1' to disable interrupt for event PREGION0RA */
#define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
#define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
#define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
-/* Bit 24 : Write '1' to Disable non-maskable interrupt for PREGION[0].WA event */
+/* Bit 24 : Write '1' to disable interrupt for event PREGION0WA */
#define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
#define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
#define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
-/* Bit 7 : Write '1' to Disable non-maskable interrupt for REGION[3].RA event */
+/* Bit 7 : Write '1' to disable interrupt for event REGION3RA */
#define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
#define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
#define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */
-/* Bit 6 : Write '1' to Disable non-maskable interrupt for REGION[3].WA event */
+/* Bit 6 : Write '1' to disable interrupt for event REGION3WA */
#define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
#define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
#define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */
-/* Bit 5 : Write '1' to Disable non-maskable interrupt for REGION[2].RA event */
+/* Bit 5 : Write '1' to disable interrupt for event REGION2RA */
#define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
#define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
#define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */
-/* Bit 4 : Write '1' to Disable non-maskable interrupt for REGION[2].WA event */
+/* Bit 4 : Write '1' to disable interrupt for event REGION2WA */
#define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
#define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
#define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */
-/* Bit 3 : Write '1' to Disable non-maskable interrupt for REGION[1].RA event */
+/* Bit 3 : Write '1' to disable interrupt for event REGION1RA */
#define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
#define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
#define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */
-/* Bit 2 : Write '1' to Disable non-maskable interrupt for REGION[1].WA event */
+/* Bit 2 : Write '1' to disable interrupt for event REGION1WA */
#define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
#define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
#define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */
-/* Bit 1 : Write '1' to Disable non-maskable interrupt for REGION[0].RA event */
+/* Bit 1 : Write '1' to disable interrupt for event REGION0RA */
#define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
#define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
#define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
#define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
#define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */
-/* Bit 0 : Write '1' to Disable non-maskable interrupt for REGION[0].WA event */
+/* Bit 0 : Write '1' to disable interrupt for event REGION0WA */
#define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
#define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
#define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
@@ -3296,390 +3785,390 @@ POSSIBILITY OF SUCH DAMAGE.
#define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */
/* Register: MWU_PERREGION_SUBSTATWA */
-/* Description: Description cluster[0]: Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for watching */
+/* Description: Description cluster: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching */
-/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
+/* Bit 31 : Subregion 31 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */
#define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */
#define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion */
-/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
+/* Bit 30 : Subregion 30 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */
#define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */
#define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion */
-/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
+/* Bit 29 : Subregion 29 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */
#define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */
#define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion */
-/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
+/* Bit 28 : Subregion 28 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */
#define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */
#define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion */
-/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
+/* Bit 27 : Subregion 27 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */
#define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */
#define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion */
-/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
+/* Bit 26 : Subregion 26 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */
#define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */
#define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion */
-/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
+/* Bit 25 : Subregion 25 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */
#define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */
#define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion */
-/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
+/* Bit 24 : Subregion 24 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */
#define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */
#define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion */
-/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
+/* Bit 23 : Subregion 23 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */
#define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */
#define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion */
-/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
+/* Bit 22 : Subregion 22 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */
#define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */
#define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion */
-/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
+/* Bit 21 : Subregion 21 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */
#define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */
#define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion */
-/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
+/* Bit 20 : Subregion 20 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */
#define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */
#define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion */
-/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
+/* Bit 19 : Subregion 19 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */
#define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */
#define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion */
-/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
+/* Bit 18 : Subregion 18 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */
#define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */
#define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion */
-/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
+/* Bit 17 : Subregion 17 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */
#define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */
#define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion */
-/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
+/* Bit 16 : Subregion 16 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */
#define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */
#define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion */
-/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
+/* Bit 15 : Subregion 15 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */
#define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */
#define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion */
-/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
+/* Bit 14 : Subregion 14 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */
#define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */
#define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion */
-/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
+/* Bit 13 : Subregion 13 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */
#define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */
#define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion */
-/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
+/* Bit 12 : Subregion 12 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */
#define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */
#define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion */
-/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
+/* Bit 11 : Subregion 11 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */
#define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */
#define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion */
-/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
+/* Bit 10 : Subregion 10 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */
#define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */
#define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion */
-/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
+/* Bit 9 : Subregion 9 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */
#define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */
#define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */
-/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
+/* Bit 8 : Subregion 8 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */
#define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */
#define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */
-/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
+/* Bit 7 : Subregion 7 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */
#define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */
#define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */
-/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
+/* Bit 6 : Subregion 6 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */
#define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */
#define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */
-/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
+/* Bit 5 : Subregion 5 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */
#define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */
#define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */
-/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
+/* Bit 4 : Subregion 4 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */
#define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */
#define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */
-/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
+/* Bit 3 : Subregion 3 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */
#define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */
#define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */
-/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
+/* Bit 2 : Subregion 2 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */
#define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */
#define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */
-/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
+/* Bit 1 : Subregion 1 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */
#define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */
#define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */
-/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
+/* Bit 0 : Subregion 0 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */
#define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */
#define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion */
#define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */
/* Register: MWU_PERREGION_SUBSTATRA */
-/* Description: Description cluster[0]: Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for watching */
+/* Description: Description cluster: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching */
-/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
+/* Bit 31 : Subregion 31 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */
#define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */
#define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */
-/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
+/* Bit 30 : Subregion 30 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */
#define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */
#define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */
-/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
+/* Bit 29 : Subregion 29 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */
#define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */
#define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */
-/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
+/* Bit 28 : Subregion 28 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */
#define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */
#define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */
-/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
+/* Bit 27 : Subregion 27 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */
#define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */
#define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */
-/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
+/* Bit 26 : Subregion 26 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */
#define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */
#define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */
-/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
+/* Bit 25 : Subregion 25 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */
#define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */
#define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */
-/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
+/* Bit 24 : Subregion 24 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */
#define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */
#define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */
-/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
+/* Bit 23 : Subregion 23 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */
#define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */
#define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */
-/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
+/* Bit 22 : Subregion 22 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */
#define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */
#define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */
-/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
+/* Bit 21 : Subregion 21 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */
#define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */
#define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */
-/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
+/* Bit 20 : Subregion 20 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */
#define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */
#define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */
-/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
+/* Bit 19 : Subregion 19 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */
#define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */
#define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */
-/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
+/* Bit 18 : Subregion 18 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */
#define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */
#define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */
-/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
+/* Bit 17 : Subregion 17 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */
#define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */
#define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */
-/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
+/* Bit 16 : Subregion 16 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */
#define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */
#define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */
-/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
+/* Bit 15 : Subregion 15 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */
#define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */
#define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */
-/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
+/* Bit 14 : Subregion 14 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */
#define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */
#define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */
-/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
+/* Bit 13 : Subregion 13 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */
#define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */
#define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */
-/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
+/* Bit 12 : Subregion 12 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */
#define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */
#define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */
-/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
+/* Bit 11 : Subregion 11 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */
#define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */
#define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */
-/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
+/* Bit 10 : Subregion 10 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */
#define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */
#define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */
-/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
+/* Bit 9 : Subregion 9 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */
#define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */
#define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */
-/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
+/* Bit 8 : Subregion 8 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */
#define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */
#define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */
-/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
+/* Bit 7 : Subregion 7 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */
#define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */
#define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */
-/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
+/* Bit 6 : Subregion 6 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */
#define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */
#define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */
-/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
+/* Bit 5 : Subregion 5 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */
#define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */
#define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */
-/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
+/* Bit 4 : Subregion 4 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */
#define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */
#define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */
-/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
+/* Bit 3 : Subregion 3 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */
#define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */
#define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */
-/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
+/* Bit 2 : Subregion 2 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */
#define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */
#define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */
-/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
+/* Bit 1 : Subregion 1 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */
#define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */
#define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */
#define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */
-/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
+/* Bit 0 : Subregion 0 in region n (write '1' to clear) */
#define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */
#define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */
#define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */
@@ -3935,35 +4424,35 @@ POSSIBILITY OF SUCH DAMAGE.
#define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */
/* Register: MWU_REGION_START */
-/* Description: Description cluster[0]: Start address for region 0 */
+/* Description: Description cluster: Start address for region n */
/* Bits 31..0 : Start address for region */
#define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */
#define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */
/* Register: MWU_REGION_END */
-/* Description: Description cluster[0]: End address of region 0 */
+/* Description: Description cluster: End address of region n */
/* Bits 31..0 : End address of region. */
#define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */
#define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */
/* Register: MWU_PREGION_START */
-/* Description: Description cluster[0]: Reserved for future use */
+/* Description: Description cluster: Reserved for future use */
/* Bits 31..0 : Reserved for future use */
#define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */
#define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */
/* Register: MWU_PREGION_END */
-/* Description: Description cluster[0]: Reserved for future use */
+/* Description: Description cluster: Reserved for future use */
/* Bits 31..0 : Reserved for future use */
#define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */
#define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */
/* Register: MWU_PREGION_SUBS */
-/* Description: Description cluster[0]: Subregions of region 0 */
+/* Description: Description cluster: Subregions of region n */
/* Bit 31 : Include or exclude subregion 31 in region */
#define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */
@@ -4161,16 +4650,207 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: NFCT */
/* Description: NFC-A compatible radio */
+/* Register: NFCT_TASKS_ACTIVATE */
+/* Description: Activate NFC peripheral for incoming and outgoing frames, change state to activated */
+
+/* Bit 0 : Activate NFC peripheral for incoming and outgoing frames, change state to activated */
+#define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos (0UL) /*!< Position of TASKS_ACTIVATE field. */
+#define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Msk (0x1UL << NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos) /*!< Bit mask of TASKS_ACTIVATE field. */
+#define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: NFCT_TASKS_DISABLE */
+/* Description: Disable NFC peripheral */
+
+/* Bit 0 : Disable NFC peripheral */
+#define NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */
+#define NFCT_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */
+#define NFCT_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: NFCT_TASKS_SENSE */
+/* Description: Enable NFC sense field mode, change state to sense mode */
+
+/* Bit 0 : Enable NFC sense field mode, change state to sense mode */
+#define NFCT_TASKS_SENSE_TASKS_SENSE_Pos (0UL) /*!< Position of TASKS_SENSE field. */
+#define NFCT_TASKS_SENSE_TASKS_SENSE_Msk (0x1UL << NFCT_TASKS_SENSE_TASKS_SENSE_Pos) /*!< Bit mask of TASKS_SENSE field. */
+#define NFCT_TASKS_SENSE_TASKS_SENSE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: NFCT_TASKS_STARTTX */
+/* Description: Start transmission of a outgoing frame, change state to transmit */
+
+/* Bit 0 : Start transmission of a outgoing frame, change state to transmit */
+#define NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
+#define NFCT_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
+#define NFCT_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: NFCT_TASKS_ENABLERXDATA */
+/* Description: Initializes the EasyDMA for receive. */
+
+/* Bit 0 : Initializes the EasyDMA for receive. */
+#define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos (0UL) /*!< Position of TASKS_ENABLERXDATA field. */
+#define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Msk (0x1UL << NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos) /*!< Bit mask of TASKS_ENABLERXDATA field. */
+#define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Trigger (1UL) /*!< Trigger task */
+
+/* Register: NFCT_TASKS_GOIDLE */
+/* Description: Force state machine to IDLE state */
+
+/* Bit 0 : Force state machine to IDLE state */
+#define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos (0UL) /*!< Position of TASKS_GOIDLE field. */
+#define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Msk (0x1UL << NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos) /*!< Bit mask of TASKS_GOIDLE field. */
+#define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: NFCT_TASKS_GOSLEEP */
+/* Description: Force state machine to SLEEP_A state */
+
+/* Bit 0 : Force state machine to SLEEP_A state */
+#define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos (0UL) /*!< Position of TASKS_GOSLEEP field. */
+#define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Msk (0x1UL << NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos) /*!< Bit mask of TASKS_GOSLEEP field. */
+#define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: NFCT_EVENTS_READY */
+/* Description: The NFC peripheral is ready to receive and send frames */
+
+/* Bit 0 : The NFC peripheral is ready to receive and send frames */
+#define NFCT_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
+#define NFCT_EVENTS_READY_EVENTS_READY_Msk (0x1UL << NFCT_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
+#define NFCT_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
+#define NFCT_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
+
+/* Register: NFCT_EVENTS_FIELDDETECTED */
+/* Description: Remote NFC field detected */
+
+/* Bit 0 : Remote NFC field detected */
+#define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos (0UL) /*!< Position of EVENTS_FIELDDETECTED field. */
+#define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Msk (0x1UL << NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos) /*!< Bit mask of EVENTS_FIELDDETECTED field. */
+#define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_NotGenerated (0UL) /*!< Event not generated */
+#define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Generated (1UL) /*!< Event generated */
+
+/* Register: NFCT_EVENTS_FIELDLOST */
+/* Description: Remote NFC field lost */
+
+/* Bit 0 : Remote NFC field lost */
+#define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos (0UL) /*!< Position of EVENTS_FIELDLOST field. */
+#define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Msk (0x1UL << NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos) /*!< Bit mask of EVENTS_FIELDLOST field. */
+#define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_NotGenerated (0UL) /*!< Event not generated */
+#define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Generated (1UL) /*!< Event generated */
+
+/* Register: NFCT_EVENTS_TXFRAMESTART */
+/* Description: Marks the start of the first symbol of a transmitted frame */
+
+/* Bit 0 : Marks the start of the first symbol of a transmitted frame */
+#define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_TXFRAMESTART field. */
+#define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos) /*!< Bit mask of EVENTS_TXFRAMESTART field. */
+#define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_NotGenerated (0UL) /*!< Event not generated */
+#define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Generated (1UL) /*!< Event generated */
+
+/* Register: NFCT_EVENTS_TXFRAMEEND */
+/* Description: Marks the end of the last transmitted on-air symbol of a frame */
+
+/* Bit 0 : Marks the end of the last transmitted on-air symbol of a frame */
+#define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_TXFRAMEEND field. */
+#define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos) /*!< Bit mask of EVENTS_TXFRAMEEND field. */
+#define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_NotGenerated (0UL) /*!< Event not generated */
+#define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Generated (1UL) /*!< Event generated */
+
+/* Register: NFCT_EVENTS_RXFRAMESTART */
+/* Description: Marks the end of the first symbol of a received frame */
+
+/* Bit 0 : Marks the end of the first symbol of a received frame */
+#define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_RXFRAMESTART field. */
+#define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos) /*!< Bit mask of EVENTS_RXFRAMESTART field. */
+#define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_NotGenerated (0UL) /*!< Event not generated */
+#define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Generated (1UL) /*!< Event generated */
+
+/* Register: NFCT_EVENTS_RXFRAMEEND */
+/* Description: Received data have been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer */
+
+/* Bit 0 : Received data have been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer */
+#define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_RXFRAMEEND field. */
+#define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos) /*!< Bit mask of EVENTS_RXFRAMEEND field. */
+#define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_NotGenerated (0UL) /*!< Event not generated */
+#define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Generated (1UL) /*!< Event generated */
+
+/* Register: NFCT_EVENTS_ERROR */
+/* Description: NFC error reported. The ERRORSTATUS register contains details on the source of the error. */
+
+/* Bit 0 : NFC error reported. The ERRORSTATUS register contains details on the source of the error. */
+#define NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
+#define NFCT_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
+#define NFCT_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
+#define NFCT_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
+
+/* Register: NFCT_EVENTS_RXERROR */
+/* Description: NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. */
+
+/* Bit 0 : NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. */
+#define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos (0UL) /*!< Position of EVENTS_RXERROR field. */
+#define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Msk (0x1UL << NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos) /*!< Bit mask of EVENTS_RXERROR field. */
+#define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_NotGenerated (0UL) /*!< Event not generated */
+#define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Generated (1UL) /*!< Event generated */
+
+/* Register: NFCT_EVENTS_ENDRX */
+/* Description: RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */
+
+/* Bit 0 : RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */
+#define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
+#define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
+#define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
+#define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
+
+/* Register: NFCT_EVENTS_ENDTX */
+/* Description: Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */
+
+/* Bit 0 : Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */
+#define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
+#define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
+#define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
+#define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
+
+/* Register: NFCT_EVENTS_AUTOCOLRESSTARTED */
+/* Description: Auto collision resolution process has started */
+
+/* Bit 0 : Auto collision resolution process has started */
+#define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos (0UL) /*!< Position of EVENTS_AUTOCOLRESSTARTED field. */
+#define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of EVENTS_AUTOCOLRESSTARTED field. */
+#define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: NFCT_EVENTS_COLLISION */
+/* Description: NFC Auto collision resolution error reported. */
+
+/* Bit 0 : NFC Auto collision resolution error reported. */
+#define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos (0UL) /*!< Position of EVENTS_COLLISION field. */
+#define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Msk (0x1UL << NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos) /*!< Bit mask of EVENTS_COLLISION field. */
+#define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_NotGenerated (0UL) /*!< Event not generated */
+#define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Generated (1UL) /*!< Event generated */
+
+/* Register: NFCT_EVENTS_SELECTED */
+/* Description: NFC Auto collision resolution successfully completed */
+
+/* Bit 0 : NFC Auto collision resolution successfully completed */
+#define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos (0UL) /*!< Position of EVENTS_SELECTED field. */
+#define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Msk (0x1UL << NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos) /*!< Bit mask of EVENTS_SELECTED field. */
+#define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_NotGenerated (0UL) /*!< Event not generated */
+#define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Generated (1UL) /*!< Event generated */
+
+/* Register: NFCT_EVENTS_STARTED */
+/* Description: EasyDMA is ready to receive or send frames. */
+
+/* Bit 0 : EasyDMA is ready to receive or send frames. */
+#define NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
+#define NFCT_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
+#define NFCT_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
+#define NFCT_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
+
/* Register: NFCT_SHORTS */
-/* Description: Shortcut register */
+/* Description: Shortcuts between local events and tasks */
-/* Bit 1 : Shortcut between FIELDLOST event and SENSE task */
+/* Bit 1 : Shortcut between event FIELDLOST and task SENSE */
#define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */
#define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */
#define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */
#define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 0 : Shortcut between FIELDDETECTED event and ACTIVATE task */
+/* Bit 0 : Shortcut between event FIELDDETECTED and task ACTIVATE */
#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */
#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */
#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */
@@ -4179,91 +4859,91 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: NFCT_INTEN */
/* Description: Enable or disable interrupt */
-/* Bit 20 : Enable or disable interrupt for STARTED event */
+/* Bit 20 : Enable or disable interrupt for event STARTED */
#define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */
#define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */
-/* Bit 19 : Enable or disable interrupt for SELECTED event */
+/* Bit 19 : Enable or disable interrupt for event SELECTED */
#define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
#define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
#define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */
-/* Bit 18 : Enable or disable interrupt for COLLISION event */
+/* Bit 18 : Enable or disable interrupt for event COLLISION */
#define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
#define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
#define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */
-/* Bit 14 : Enable or disable interrupt for AUTOCOLRESSTARTED event */
+/* Bit 14 : Enable or disable interrupt for event AUTOCOLRESSTARTED */
#define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
#define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
#define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */
-/* Bit 12 : Enable or disable interrupt for ENDTX event */
+/* Bit 12 : Enable or disable interrupt for event ENDTX */
#define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
#define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
-/* Bit 11 : Enable or disable interrupt for ENDRX event */
+/* Bit 11 : Enable or disable interrupt for event ENDRX */
#define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
#define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
-/* Bit 10 : Enable or disable interrupt for RXERROR event */
+/* Bit 10 : Enable or disable interrupt for event RXERROR */
#define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
#define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
#define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */
-/* Bit 7 : Enable or disable interrupt for ERROR event */
+/* Bit 7 : Enable or disable interrupt for event ERROR */
#define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */
#define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */
-/* Bit 6 : Enable or disable interrupt for RXFRAMEEND event */
+/* Bit 6 : Enable or disable interrupt for event RXFRAMEEND */
#define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
#define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
#define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */
-/* Bit 5 : Enable or disable interrupt for RXFRAMESTART event */
+/* Bit 5 : Enable or disable interrupt for event RXFRAMESTART */
#define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
#define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
#define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */
-/* Bit 4 : Enable or disable interrupt for TXFRAMEEND event */
+/* Bit 4 : Enable or disable interrupt for event TXFRAMEEND */
#define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
#define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
#define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */
-/* Bit 3 : Enable or disable interrupt for TXFRAMESTART event */
+/* Bit 3 : Enable or disable interrupt for event TXFRAMESTART */
#define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
#define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
#define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */
-/* Bit 2 : Enable or disable interrupt for FIELDLOST event */
+/* Bit 2 : Enable or disable interrupt for event FIELDLOST */
#define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
#define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
#define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */
-/* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */
+/* Bit 1 : Enable or disable interrupt for event FIELDDETECTED */
#define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
#define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
#define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */
#define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */
-/* Bit 0 : Enable or disable interrupt for READY event */
+/* Bit 0 : Enable or disable interrupt for event READY */
#define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
#define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */
#define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */
@@ -4272,105 +4952,105 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: NFCT_INTENSET */
/* Description: Enable interrupt */
-/* Bit 20 : Write '1' to Enable interrupt for STARTED event */
+/* Bit 20 : Write '1' to enable interrupt for event STARTED */
#define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */
#define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */
-/* Bit 19 : Write '1' to Enable interrupt for SELECTED event */
+/* Bit 19 : Write '1' to enable interrupt for event SELECTED */
#define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
#define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
#define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */
-/* Bit 18 : Write '1' to Enable interrupt for COLLISION event */
+/* Bit 18 : Write '1' to enable interrupt for event COLLISION */
#define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
#define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
#define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */
-/* Bit 14 : Write '1' to Enable interrupt for AUTOCOLRESSTARTED event */
+/* Bit 14 : Write '1' to enable interrupt for event AUTOCOLRESSTARTED */
#define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
#define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
#define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */
-/* Bit 12 : Write '1' to Enable interrupt for ENDTX event */
+/* Bit 12 : Write '1' to enable interrupt for event ENDTX */
#define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
#define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */
-/* Bit 11 : Write '1' to Enable interrupt for ENDRX event */
+/* Bit 11 : Write '1' to enable interrupt for event ENDRX */
#define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
#define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */
-/* Bit 10 : Write '1' to Enable interrupt for RXERROR event */
+/* Bit 10 : Write '1' to enable interrupt for event RXERROR */
#define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
#define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
#define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */
-/* Bit 7 : Write '1' to Enable interrupt for ERROR event */
+/* Bit 7 : Write '1' to enable interrupt for event ERROR */
#define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */
#define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */
-/* Bit 6 : Write '1' to Enable interrupt for RXFRAMEEND event */
+/* Bit 6 : Write '1' to enable interrupt for event RXFRAMEEND */
#define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
#define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
#define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */
-/* Bit 5 : Write '1' to Enable interrupt for RXFRAMESTART event */
+/* Bit 5 : Write '1' to enable interrupt for event RXFRAMESTART */
#define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
#define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
#define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */
-/* Bit 4 : Write '1' to Enable interrupt for TXFRAMEEND event */
+/* Bit 4 : Write '1' to enable interrupt for event TXFRAMEEND */
#define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
#define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
#define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */
-/* Bit 3 : Write '1' to Enable interrupt for TXFRAMESTART event */
+/* Bit 3 : Write '1' to enable interrupt for event TXFRAMESTART */
#define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
#define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
#define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */
-/* Bit 2 : Write '1' to Enable interrupt for FIELDLOST event */
+/* Bit 2 : Write '1' to enable interrupt for event FIELDLOST */
#define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
#define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
#define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */
-/* Bit 1 : Write '1' to Enable interrupt for FIELDDETECTED event */
+/* Bit 1 : Write '1' to enable interrupt for event FIELDDETECTED */
#define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
#define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
#define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */
-/* Bit 0 : Write '1' to Enable interrupt for READY event */
+/* Bit 0 : Write '1' to enable interrupt for event READY */
#define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
#define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
#define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
@@ -4380,105 +5060,105 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: NFCT_INTENCLR */
/* Description: Disable interrupt */
-/* Bit 20 : Write '1' to Disable interrupt for STARTED event */
+/* Bit 20 : Write '1' to disable interrupt for event STARTED */
#define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */
#define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
-/* Bit 19 : Write '1' to Disable interrupt for SELECTED event */
+/* Bit 19 : Write '1' to disable interrupt for event SELECTED */
#define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
#define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
#define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */
-/* Bit 18 : Write '1' to Disable interrupt for COLLISION event */
+/* Bit 18 : Write '1' to disable interrupt for event COLLISION */
#define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
#define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
#define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */
-/* Bit 14 : Write '1' to Disable interrupt for AUTOCOLRESSTARTED event */
+/* Bit 14 : Write '1' to disable interrupt for event AUTOCOLRESSTARTED */
#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */
-/* Bit 12 : Write '1' to Disable interrupt for ENDTX event */
+/* Bit 12 : Write '1' to disable interrupt for event ENDTX */
#define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
#define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
-/* Bit 11 : Write '1' to Disable interrupt for ENDRX event */
+/* Bit 11 : Write '1' to disable interrupt for event ENDRX */
#define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
#define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
-/* Bit 10 : Write '1' to Disable interrupt for RXERROR event */
+/* Bit 10 : Write '1' to disable interrupt for event RXERROR */
#define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
#define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
#define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */
-/* Bit 7 : Write '1' to Disable interrupt for ERROR event */
+/* Bit 7 : Write '1' to disable interrupt for event ERROR */
#define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */
#define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
-/* Bit 6 : Write '1' to Disable interrupt for RXFRAMEEND event */
+/* Bit 6 : Write '1' to disable interrupt for event RXFRAMEEND */
#define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
#define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
#define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */
-/* Bit 5 : Write '1' to Disable interrupt for RXFRAMESTART event */
+/* Bit 5 : Write '1' to disable interrupt for event RXFRAMESTART */
#define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
#define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
#define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */
-/* Bit 4 : Write '1' to Disable interrupt for TXFRAMEEND event */
+/* Bit 4 : Write '1' to disable interrupt for event TXFRAMEEND */
#define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
#define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
#define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */
-/* Bit 3 : Write '1' to Disable interrupt for TXFRAMESTART event */
+/* Bit 3 : Write '1' to disable interrupt for event TXFRAMESTART */
#define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
#define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
#define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */
-/* Bit 2 : Write '1' to Disable interrupt for FIELDLOST event */
+/* Bit 2 : Write '1' to disable interrupt for event FIELDLOST */
#define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
#define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
#define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */
-/* Bit 1 : Write '1' to Disable interrupt for FIELDDETECTED event */
+/* Bit 1 : Write '1' to disable interrupt for event FIELDDETECTED */
#define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
#define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
#define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */
-/* Bit 0 : Write '1' to Disable interrupt for READY event */
+/* Bit 0 : Write '1' to disable interrupt for event READY */
#define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
#define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
#define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
@@ -4789,7 +5469,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */
/* Register: NVMC_ERASEPCR1 */
-/* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
+/* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
/* Bits 31..0 : Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
#define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */
@@ -4805,7 +5485,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */
/* Register: NVMC_ERASEPCR0 */
-/* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
+/* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
/* Bits 31..0 : Register for starting erase of a page in Code area. Equivalent to ERASEPAGE. */
#define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */
@@ -6551,7 +7231,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */
/* Register: GPIO_PIN_CNF */
-/* Description: Description collection[0]: Configuration of GPIO pins */
+/* Description: Description collection: Configuration of GPIO pins */
/* Bits 17..16 : Pin sensing mechanism */
#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
@@ -6595,22 +7275,65 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: PDM */
/* Description: Pulse Density Modulation (Digital Microphone) Interface */
+/* Register: PDM_TASKS_START */
+/* Description: Starts continuous PDM transfer */
+
+/* Bit 0 : Starts continuous PDM transfer */
+#define PDM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define PDM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: PDM_TASKS_STOP */
+/* Description: Stops PDM transfer */
+
+/* Bit 0 : Stops PDM transfer */
+#define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define PDM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: PDM_EVENTS_STARTED */
+/* Description: PDM transfer has started */
+
+/* Bit 0 : PDM transfer has started */
+#define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
+#define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
+#define PDM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
+#define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: PDM_EVENTS_STOPPED */
+/* Description: PDM transfer has finished */
+
+/* Bit 0 : PDM transfer has finished */
+#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
+#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
+#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: PDM_EVENTS_END */
+/* Description: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */
+
+/* Bit 0 : The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */
+#define PDM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
+#define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
+#define PDM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
+#define PDM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
+
/* Register: PDM_INTEN */
/* Description: Enable or disable interrupt */
-/* Bit 2 : Enable or disable interrupt for END event */
+/* Bit 2 : Enable or disable interrupt for event END */
#define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */
#define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */
#define PDM_INTEN_END_Disabled (0UL) /*!< Disable */
#define PDM_INTEN_END_Enabled (1UL) /*!< Enable */
-/* Bit 1 : Enable or disable interrupt for STOPPED event */
+/* Bit 1 : Enable or disable interrupt for event STOPPED */
#define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
#define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
-/* Bit 0 : Enable or disable interrupt for STARTED event */
+/* Bit 0 : Enable or disable interrupt for event STARTED */
#define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
#define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */
@@ -6619,21 +7342,21 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: PDM_INTENSET */
/* Description: Enable interrupt */
-/* Bit 2 : Write '1' to Enable interrupt for END event */
+/* Bit 2 : Write '1' to enable interrupt for event END */
#define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */
#define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */
#define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
#define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
#define PDM_INTENSET_END_Set (1UL) /*!< Enable */
-/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+/* Bit 1 : Write '1' to enable interrupt for event STOPPED */
#define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
-/* Bit 0 : Write '1' to Enable interrupt for STARTED event */
+/* Bit 0 : Write '1' to enable interrupt for event STARTED */
#define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
#define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
@@ -6643,21 +7366,21 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: PDM_INTENCLR */
/* Description: Disable interrupt */
-/* Bit 2 : Write '1' to Disable interrupt for END event */
+/* Bit 2 : Write '1' to disable interrupt for event END */
#define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */
#define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
#define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
#define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
#define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */
-/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+/* Bit 1 : Write '1' to disable interrupt for event STOPPED */
#define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
-/* Bit 0 : Write '1' to Disable interrupt for STARTED event */
+/* Bit 0 : Write '1' to disable interrupt for event STARTED */
#define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
#define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
@@ -6762,24 +7485,67 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: POWER */
/* Description: Power control */
+/* Register: POWER_TASKS_CONSTLAT */
+/* Description: Enable constant latency mode */
+
+/* Bit 0 : Enable constant latency mode */
+#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */
+#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */
+#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */
+
+/* Register: POWER_TASKS_LOWPWR */
+/* Description: Enable low power mode (variable latency) */
+
+/* Bit 0 : Enable low power mode (variable latency) */
+#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */
+#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */
+#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */
+
+/* Register: POWER_EVENTS_POFWARN */
+/* Description: Power failure warning */
+
+/* Bit 0 : Power failure warning */
+#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */
+#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */
+#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0UL) /*!< Event not generated */
+#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (1UL) /*!< Event generated */
+
+/* Register: POWER_EVENTS_SLEEPENTER */
+/* Description: CPU entered WFI/WFE sleep */
+
+/* Bit 0 : CPU entered WFI/WFE sleep */
+#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */
+#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */
+#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0UL) /*!< Event not generated */
+#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (1UL) /*!< Event generated */
+
+/* Register: POWER_EVENTS_SLEEPEXIT */
+/* Description: CPU exited WFI/WFE sleep */
+
+/* Bit 0 : CPU exited WFI/WFE sleep */
+#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */
+#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */
+#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0UL) /*!< Event not generated */
+#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (1UL) /*!< Event generated */
+
/* Register: POWER_INTENSET */
/* Description: Enable interrupt */
-/* Bit 6 : Write '1' to Enable interrupt for SLEEPEXIT event */
+/* Bit 6 : Write '1' to enable interrupt for event SLEEPEXIT */
#define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
#define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
#define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
#define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
#define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
-/* Bit 5 : Write '1' to Enable interrupt for SLEEPENTER event */
+/* Bit 5 : Write '1' to enable interrupt for event SLEEPENTER */
#define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
#define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
#define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
#define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
#define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
-/* Bit 2 : Write '1' to Enable interrupt for POFWARN event */
+/* Bit 2 : Write '1' to enable interrupt for event POFWARN */
#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
@@ -6789,21 +7555,21 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: POWER_INTENCLR */
/* Description: Disable interrupt */
-/* Bit 6 : Write '1' to Disable interrupt for SLEEPEXIT event */
+/* Bit 6 : Write '1' to disable interrupt for event SLEEPEXIT */
#define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
#define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
#define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
#define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
#define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
-/* Bit 5 : Write '1' to Disable interrupt for SLEEPENTER event */
+/* Bit 5 : Write '1' to disable interrupt for event SLEEPENTER */
#define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
#define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
#define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
#define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
#define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
-/* Bit 2 : Write '1' to Disable interrupt for POFWARN event */
+/* Bit 2 : Write '1' to disable interrupt for event POFWARN */
#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
@@ -6862,7 +7628,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */
/* Register: POWER_RAMSTATUS */
-/* Description: Deprecated register - RAM status register */
+/* Description: Deprecated register - RAM status register */
/* Bit 3 : RAM block 3 is on or off/powering up */
#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
@@ -6936,7 +7702,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
/* Register: POWER_RAMON */
-/* Description: Deprecated register - RAM on/off register (this register is retained) */
+/* Description: Deprecated register - RAM on/off register (this register is retained) */
/* Bit 17 : Keep retention on RAM block 1 when RAM block is switched off */
#define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */
@@ -6963,7 +7729,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< On */
/* Register: POWER_RAMONB */
-/* Description: Deprecated register - RAM on/off register (this register is retained) */
+/* Description: Deprecated register - RAM on/off register (this register is retained) */
/* Bit 17 : Keep retention on RAM block 3 when RAM block is switched off */
#define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */
@@ -6999,7 +7765,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */
/* Register: POWER_RAM_POWER */
-/* Description: Description cluster[0]: RAM0 power control register */
+/* Description: Description cluster: RAMn power control register */
/* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */
#define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
@@ -7026,7 +7792,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */
/* Register: POWER_RAM_POWERSET */
-/* Description: Description cluster[0]: RAM0 power control set register */
+/* Description: Description cluster: RAMn power control set register */
/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
#define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
@@ -7038,18 +7804,18 @@ POSSIBILITY OF SUCH DAMAGE.
#define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
#define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */
-/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */
+/* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */
#define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
#define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
#define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */
-/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */
+/* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */
#define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
#define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
#define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */
/* Register: POWER_RAM_POWERCLR */
-/* Description: Description cluster[0]: RAM0 power control clear register */
+/* Description: Description cluster: RAMn power control clear register */
/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
#define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
@@ -7061,12 +7827,12 @@ POSSIBILITY OF SUCH DAMAGE.
#define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
#define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */
-/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */
+/* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */
#define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
#define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
#define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */
-/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */
+/* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */
#define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
#define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
#define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */
@@ -7075,6 +7841,22 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: PPI */
/* Description: Programmable Peripheral Interconnect */
+/* Register: PPI_TASKS_CHG_EN */
+/* Description: Description cluster: Enable channel group n */
+
+/* Bit 0 : Enable channel group n */
+#define PPI_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */
+#define PPI_TASKS_CHG_EN_EN_Msk (0x1UL << PPI_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */
+#define PPI_TASKS_CHG_EN_EN_Trigger (1UL) /*!< Trigger task */
+
+/* Register: PPI_TASKS_CHG_DIS */
+/* Description: Description cluster: Disable channel group n */
+
+/* Bit 0 : Disable channel group n */
+#define PPI_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */
+#define PPI_TASKS_CHG_DIS_DIS_Msk (0x1UL << PPI_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */
+#define PPI_TASKS_CHG_DIS_DIS_Trigger (1UL) /*!< Trigger task */
+
/* Register: PPI_CHEN */
/* Description: Channel enable register */
@@ -7725,21 +8507,21 @@ POSSIBILITY OF SUCH DAMAGE.
#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
/* Register: PPI_CH_EEP */
-/* Description: Description cluster[0]: Channel 0 event end-point */
+/* Description: Description cluster: Channel n event end-point */
/* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */
#define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */
#define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */
/* Register: PPI_CH_TEP */
-/* Description: Description cluster[0]: Channel 0 task end-point */
+/* Description: Description cluster: Channel n task end-point */
/* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */
#define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
#define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
/* Register: PPI_CHG */
-/* Description: Description collection[0]: Channel group 0 */
+/* Description: Description collection: Channel group n */
/* Bit 31 : Include or exclude channel 31 */
#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
@@ -7934,7 +8716,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define PPI_CHG_CH0_Included (1UL) /*!< Include */
/* Register: PPI_FORK_TEP */
-/* Description: Description cluster[0]: Channel 0 task end-point */
+/* Description: Description cluster: Channel n task end-point */
/* Bits 31..0 : Pointer to task register */
#define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
@@ -7944,34 +8726,103 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: PWM */
/* Description: Pulse Width Modulation Unit 0 */
+/* Register: PWM_TASKS_STOP */
+/* Description: Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */
+
+/* Bit 0 : Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */
+#define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define PWM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: PWM_TASKS_SEQSTART */
+/* Description: Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running. */
+
+/* Bit 0 : Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running. */
+#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos (0UL) /*!< Position of TASKS_SEQSTART field. */
+#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Msk (0x1UL << PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos) /*!< Bit mask of TASKS_SEQSTART field. */
+#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Trigger (1UL) /*!< Trigger task */
+
+/* Register: PWM_TASKS_NEXTSTEP */
+/* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start it was not running. */
+
+/* Bit 0 : Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start it was not running. */
+#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL) /*!< Position of TASKS_NEXTSTEP field. */
+#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos) /*!< Bit mask of TASKS_NEXTSTEP field. */
+#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: PWM_EVENTS_STOPPED */
+/* Description: Response to STOP task, emitted when PWM pulses are no longer generated */
+
+/* Bit 0 : Response to STOP task, emitted when PWM pulses are no longer generated */
+#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
+#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
+#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: PWM_EVENTS_SEQSTARTED */
+/* Description: Description collection: First PWM period started on sequence n */
+
+/* Bit 0 : First PWM period started on sequence n */
+#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field. */
+#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of EVENTS_SEQSTARTED field. */
+#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: PWM_EVENTS_SEQEND */
+/* Description: Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */
+
+/* Bit 0 : Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */
+#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL) /*!< Position of EVENTS_SEQEND field. */
+#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos) /*!< Bit mask of EVENTS_SEQEND field. */
+#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_NotGenerated (0UL) /*!< Event not generated */
+#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (1UL) /*!< Event generated */
+
+/* Register: PWM_EVENTS_PWMPERIODEND */
+/* Description: Emitted at the end of each PWM period */
+
+/* Bit 0 : Emitted at the end of each PWM period */
+#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field. */
+#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit mask of EVENTS_PWMPERIODEND field. */
+#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0UL) /*!< Event not generated */
+#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (1UL) /*!< Event generated */
+
+/* Register: PWM_EVENTS_LOOPSDONE */
+/* Description: Concatenated sequences have been played the amount of times defined in LOOP.CNT */
+
+/* Bit 0 : Concatenated sequences have been played the amount of times defined in LOOP.CNT */
+#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL) /*!< Position of EVENTS_LOOPSDONE field. */
+#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos) /*!< Bit mask of EVENTS_LOOPSDONE field. */
+#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_NotGenerated (0UL) /*!< Event not generated */
+#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (1UL) /*!< Event generated */
+
/* Register: PWM_SHORTS */
-/* Description: Shortcut register */
+/* Description: Shortcuts between local events and tasks */
-/* Bit 4 : Shortcut between LOOPSDONE event and STOP task */
+/* Bit 4 : Shortcut between event LOOPSDONE and task STOP */
#define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */
#define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */
#define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */
#define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 3 : Shortcut between LOOPSDONE event and SEQSTART[1] task */
+/* Bit 3 : Shortcut between event LOOPSDONE and task SEQSTART[1] */
#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */
#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */
#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */
#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */
+/* Bit 2 : Shortcut between event LOOPSDONE and task SEQSTART[0] */
#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */
#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */
#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */
#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 1 : Shortcut between SEQEND[1] event and STOP task */
+/* Bit 1 : Shortcut between event SEQEND[1] and task STOP */
#define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */
#define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */
#define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */
#define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 0 : Shortcut between SEQEND[0] event and STOP task */
+/* Bit 0 : Shortcut between event SEQEND[0] and task STOP */
#define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */
#define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */
#define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */
@@ -7980,43 +8831,43 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: PWM_INTEN */
/* Description: Enable or disable interrupt */
-/* Bit 7 : Enable or disable interrupt for LOOPSDONE event */
+/* Bit 7 : Enable or disable interrupt for event LOOPSDONE */
#define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
#define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
#define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */
#define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */
-/* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */
+/* Bit 6 : Enable or disable interrupt for event PWMPERIODEND */
#define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
#define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
#define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */
#define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */
-/* Bit 5 : Enable or disable interrupt for SEQEND[1] event */
+/* Bit 5 : Enable or disable interrupt for event SEQEND[1] */
#define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
#define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
#define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */
#define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */
-/* Bit 4 : Enable or disable interrupt for SEQEND[0] event */
+/* Bit 4 : Enable or disable interrupt for event SEQEND[0] */
#define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
#define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
#define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */
#define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */
-/* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */
+/* Bit 3 : Enable or disable interrupt for event SEQSTARTED[1] */
#define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
#define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
#define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */
#define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */
-/* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */
+/* Bit 2 : Enable or disable interrupt for event SEQSTARTED[0] */
#define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
#define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
#define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */
#define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */
-/* Bit 1 : Enable or disable interrupt for STOPPED event */
+/* Bit 1 : Enable or disable interrupt for event STOPPED */
#define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
@@ -8025,49 +8876,49 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: PWM_INTENSET */
/* Description: Enable interrupt */
-/* Bit 7 : Write '1' to Enable interrupt for LOOPSDONE event */
+/* Bit 7 : Write '1' to enable interrupt for event LOOPSDONE */
#define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
#define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
#define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */
-/* Bit 6 : Write '1' to Enable interrupt for PWMPERIODEND event */
+/* Bit 6 : Write '1' to enable interrupt for event PWMPERIODEND */
#define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
#define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
#define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */
-/* Bit 5 : Write '1' to Enable interrupt for SEQEND[1] event */
+/* Bit 5 : Write '1' to enable interrupt for event SEQEND[1] */
#define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
#define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
#define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */
-/* Bit 4 : Write '1' to Enable interrupt for SEQEND[0] event */
+/* Bit 4 : Write '1' to enable interrupt for event SEQEND[0] */
#define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
#define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
#define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */
-/* Bit 3 : Write '1' to Enable interrupt for SEQSTARTED[1] event */
+/* Bit 3 : Write '1' to enable interrupt for event SEQSTARTED[1] */
#define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
#define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
#define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */
-/* Bit 2 : Write '1' to Enable interrupt for SEQSTARTED[0] event */
+/* Bit 2 : Write '1' to enable interrupt for event SEQSTARTED[0] */
#define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
#define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
#define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */
-/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+/* Bit 1 : Write '1' to enable interrupt for event STOPPED */
#define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
@@ -8077,49 +8928,49 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: PWM_INTENCLR */
/* Description: Disable interrupt */
-/* Bit 7 : Write '1' to Disable interrupt for LOOPSDONE event */
+/* Bit 7 : Write '1' to disable interrupt for event LOOPSDONE */
#define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
#define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
#define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */
-/* Bit 6 : Write '1' to Disable interrupt for PWMPERIODEND event */
+/* Bit 6 : Write '1' to disable interrupt for event PWMPERIODEND */
#define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
#define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
#define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */
-/* Bit 5 : Write '1' to Disable interrupt for SEQEND[1] event */
+/* Bit 5 : Write '1' to disable interrupt for event SEQEND[1] */
#define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
#define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
#define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */
-/* Bit 4 : Write '1' to Disable interrupt for SEQEND[0] event */
+/* Bit 4 : Write '1' to disable interrupt for event SEQEND[0] */
#define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
#define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
#define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */
-/* Bit 3 : Write '1' to Disable interrupt for SEQSTARTED[1] event */
+/* Bit 3 : Write '1' to disable interrupt for event SEQSTARTED[1] */
#define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
#define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
#define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */
-/* Bit 2 : Write '1' to Disable interrupt for SEQSTARTED[0] event */
+/* Bit 2 : Write '1' to disable interrupt for event SEQSTARTED[0] */
#define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
#define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
#define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
#define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
#define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */
-/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+/* Bit 1 : Write '1' to disable interrupt for event STOPPED */
#define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
@@ -8192,14 +9043,14 @@ POSSIBILITY OF SUCH DAMAGE.
#define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */
/* Register: PWM_SEQ_PTR */
-/* Description: Description cluster[0]: Beginning address in Data RAM of this sequence */
+/* Description: Description cluster: Beginning address in Data RAM of this sequence */
/* Bits 31..0 : Beginning address in Data RAM of this sequence */
#define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
/* Register: PWM_SEQ_CNT */
-/* Description: Description cluster[0]: Amount of values (duty cycles) in this sequence */
+/* Description: Description cluster: Amount of values (duty cycles) in this sequence */
/* Bits 14..0 : Amount of values (duty cycles) in this sequence */
#define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
@@ -8207,7 +9058,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */
/* Register: PWM_SEQ_REFRESH */
-/* Description: Description cluster[0]: Amount of additional PWM periods between samples loaded into compare register */
+/* Description: Description cluster: Amount of additional PWM periods between samples loaded into compare register */
/* Bits 23..0 : Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */
#define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */
@@ -8215,14 +9066,14 @@ POSSIBILITY OF SUCH DAMAGE.
#define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */
/* Register: PWM_SEQ_ENDDELAY */
-/* Description: Description cluster[0]: Time added after the sequence */
+/* Description: Description cluster: Time added after the sequence */
/* Bits 23..0 : Time added after the sequence in PWM periods */
#define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */
#define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */
/* Register: PWM_PSEL_OUT */
-/* Description: Description collection[0]: Output pin select for PWM channel 0 */
+/* Description: Description collection: Output pin select for PWM channel n */
/* Bit 31 : Connection */
#define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
@@ -8238,46 +9089,131 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: QDEC */
/* Description: Quadrature Decoder */
+/* Register: QDEC_TASKS_START */
+/* Description: Task starting the quadrature decoder */
+
+/* Bit 0 : Task starting the quadrature decoder */
+#define QDEC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define QDEC_TASKS_START_TASKS_START_Msk (0x1UL << QDEC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define QDEC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: QDEC_TASKS_STOP */
+/* Description: Task stopping the quadrature decoder */
+
+/* Bit 0 : Task stopping the quadrature decoder */
+#define QDEC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define QDEC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << QDEC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define QDEC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: QDEC_TASKS_READCLRACC */
+/* Description: Read and clear ACC and ACCDBL */
+
+/* Bit 0 : Read and clear ACC and ACCDBL */
+#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos (0UL) /*!< Position of TASKS_READCLRACC field. */
+#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Msk (0x1UL << QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos) /*!< Bit mask of TASKS_READCLRACC field. */
+#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Trigger (1UL) /*!< Trigger task */
+
+/* Register: QDEC_TASKS_RDCLRACC */
+/* Description: Read and clear ACC */
+
+/* Bit 0 : Read and clear ACC */
+#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos (0UL) /*!< Position of TASKS_RDCLRACC field. */
+#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Msk (0x1UL << QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos) /*!< Bit mask of TASKS_RDCLRACC field. */
+#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Trigger (1UL) /*!< Trigger task */
+
+/* Register: QDEC_TASKS_RDCLRDBL */
+/* Description: Read and clear ACCDBL */
+
+/* Bit 0 : Read and clear ACCDBL */
+#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos (0UL) /*!< Position of TASKS_RDCLRDBL field. */
+#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Msk (0x1UL << QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos) /*!< Bit mask of TASKS_RDCLRDBL field. */
+#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Trigger (1UL) /*!< Trigger task */
+
+/* Register: QDEC_EVENTS_SAMPLERDY */
+/* Description: Event being generated for every new sample value written to the SAMPLE register */
+
+/* Bit 0 : Event being generated for every new sample value written to the SAMPLE register */
+#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos (0UL) /*!< Position of EVENTS_SAMPLERDY field. */
+#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Msk (0x1UL << QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos) /*!< Bit mask of EVENTS_SAMPLERDY field. */
+#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_NotGenerated (0UL) /*!< Event not generated */
+#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Generated (1UL) /*!< Event generated */
+
+/* Register: QDEC_EVENTS_REPORTRDY */
+/* Description: Non-null report ready */
+
+/* Bit 0 : Non-null report ready */
+#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos (0UL) /*!< Position of EVENTS_REPORTRDY field. */
+#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Msk (0x1UL << QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos) /*!< Bit mask of EVENTS_REPORTRDY field. */
+#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_NotGenerated (0UL) /*!< Event not generated */
+#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Generated (1UL) /*!< Event generated */
+
+/* Register: QDEC_EVENTS_ACCOF */
+/* Description: ACC or ACCDBL register overflow */
+
+/* Bit 0 : ACC or ACCDBL register overflow */
+#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos (0UL) /*!< Position of EVENTS_ACCOF field. */
+#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Msk (0x1UL << QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos) /*!< Bit mask of EVENTS_ACCOF field. */
+#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_NotGenerated (0UL) /*!< Event not generated */
+#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Generated (1UL) /*!< Event generated */
+
+/* Register: QDEC_EVENTS_DBLRDY */
+/* Description: Double displacement(s) detected */
+
+/* Bit 0 : Double displacement(s) detected */
+#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos (0UL) /*!< Position of EVENTS_DBLRDY field. */
+#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Msk (0x1UL << QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos) /*!< Bit mask of EVENTS_DBLRDY field. */
+#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_NotGenerated (0UL) /*!< Event not generated */
+#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Generated (1UL) /*!< Event generated */
+
+/* Register: QDEC_EVENTS_STOPPED */
+/* Description: QDEC has been stopped */
+
+/* Bit 0 : QDEC has been stopped */
+#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
+#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
+#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
+
/* Register: QDEC_SHORTS */
-/* Description: Shortcut register */
+/* Description: Shortcuts between local events and tasks */
-/* Bit 6 : Shortcut between SAMPLERDY event and READCLRACC task */
+/* Bit 6 : Shortcut between event SAMPLERDY and task READCLRACC */
#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */
#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */
#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 5 : Shortcut between DBLRDY event and STOP task */
+/* Bit 5 : Shortcut between event DBLRDY and task STOP */
#define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */
#define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */
#define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
#define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 4 : Shortcut between DBLRDY event and RDCLRDBL task */
+/* Bit 4 : Shortcut between event DBLRDY and task RDCLRDBL */
#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */
#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */
#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */
#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 3 : Shortcut between REPORTRDY event and STOP task */
+/* Bit 3 : Shortcut between event REPORTRDY and task STOP */
#define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */
#define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */
#define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
#define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */
+/* Bit 2 : Shortcut between event REPORTRDY and task RDCLRACC */
#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */
#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */
#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */
#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 1 : Shortcut between SAMPLERDY event and STOP task */
+/* Bit 1 : Shortcut between event SAMPLERDY and task STOP */
#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */
#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task */
+/* Bit 0 : Shortcut between event REPORTRDY and task READCLRACC */
#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
@@ -8286,35 +9222,35 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: QDEC_INTENSET */
/* Description: Enable interrupt */
-/* Bit 4 : Write '1' to Enable interrupt for STOPPED event */
+/* Bit 4 : Write '1' to enable interrupt for event STOPPED */
#define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
#define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
-/* Bit 3 : Write '1' to Enable interrupt for DBLRDY event */
+/* Bit 3 : Write '1' to enable interrupt for event DBLRDY */
#define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
#define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
#define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
#define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
#define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */
-/* Bit 2 : Write '1' to Enable interrupt for ACCOF event */
+/* Bit 2 : Write '1' to enable interrupt for event ACCOF */
#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */
#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */
#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */
-/* Bit 1 : Write '1' to Enable interrupt for REPORTRDY event */
+/* Bit 1 : Write '1' to enable interrupt for event REPORTRDY */
#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */
-/* Bit 0 : Write '1' to Enable interrupt for SAMPLERDY event */
+/* Bit 0 : Write '1' to enable interrupt for event SAMPLERDY */
#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
@@ -8324,35 +9260,35 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: QDEC_INTENCLR */
/* Description: Disable interrupt */
-/* Bit 4 : Write '1' to Disable interrupt for STOPPED event */
+/* Bit 4 : Write '1' to disable interrupt for event STOPPED */
#define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
#define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
-/* Bit 3 : Write '1' to Disable interrupt for DBLRDY event */
+/* Bit 3 : Write '1' to disable interrupt for event DBLRDY */
#define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
#define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
#define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
#define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
#define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */
-/* Bit 2 : Write '1' to Disable interrupt for ACCOF event */
+/* Bit 2 : Write '1' to disable interrupt for event ACCOF */
#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */
#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */
#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */
-/* Bit 1 : Write '1' to Disable interrupt for REPORTRDY event */
+/* Bit 1 : Write '1' to disable interrupt for event REPORTRDY */
#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */
-/* Bit 0 : Write '1' to Disable interrupt for SAMPLERDY event */
+/* Bit 0 : Write '1' to disable interrupt for event SAMPLERDY */
#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
@@ -8505,52 +9441,223 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: RADIO */
/* Description: 2.4 GHz Radio */
+/* Register: RADIO_TASKS_TXEN */
+/* Description: Enable RADIO in TX mode */
+
+/* Bit 0 : Enable RADIO in TX mode */
+#define RADIO_TASKS_TXEN_TASKS_TXEN_Pos (0UL) /*!< Position of TASKS_TXEN field. */
+#define RADIO_TASKS_TXEN_TASKS_TXEN_Msk (0x1UL << RADIO_TASKS_TXEN_TASKS_TXEN_Pos) /*!< Bit mask of TASKS_TXEN field. */
+#define RADIO_TASKS_TXEN_TASKS_TXEN_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RADIO_TASKS_RXEN */
+/* Description: Enable RADIO in RX mode */
+
+/* Bit 0 : Enable RADIO in RX mode */
+#define RADIO_TASKS_RXEN_TASKS_RXEN_Pos (0UL) /*!< Position of TASKS_RXEN field. */
+#define RADIO_TASKS_RXEN_TASKS_RXEN_Msk (0x1UL << RADIO_TASKS_RXEN_TASKS_RXEN_Pos) /*!< Bit mask of TASKS_RXEN field. */
+#define RADIO_TASKS_RXEN_TASKS_RXEN_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RADIO_TASKS_START */
+/* Description: Start RADIO */
+
+/* Bit 0 : Start RADIO */
+#define RADIO_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define RADIO_TASKS_START_TASKS_START_Msk (0x1UL << RADIO_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define RADIO_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RADIO_TASKS_STOP */
+/* Description: Stop RADIO */
+
+/* Bit 0 : Stop RADIO */
+#define RADIO_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define RADIO_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RADIO_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define RADIO_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RADIO_TASKS_DISABLE */
+/* Description: Disable RADIO */
+
+/* Bit 0 : Disable RADIO */
+#define RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */
+#define RADIO_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */
+#define RADIO_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RADIO_TASKS_RSSISTART */
+/* Description: Start the RSSI and take one single sample of the receive signal strength. */
+
+/* Bit 0 : Start the RSSI and take one single sample of the receive signal strength. */
+#define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos (0UL) /*!< Position of TASKS_RSSISTART field. */
+#define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Msk (0x1UL << RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos) /*!< Bit mask of TASKS_RSSISTART field. */
+#define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RADIO_TASKS_RSSISTOP */
+/* Description: Stop the RSSI measurement */
+
+/* Bit 0 : Stop the RSSI measurement */
+#define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos (0UL) /*!< Position of TASKS_RSSISTOP field. */
+#define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Msk (0x1UL << RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos) /*!< Bit mask of TASKS_RSSISTOP field. */
+#define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RADIO_TASKS_BCSTART */
+/* Description: Start the bit counter */
+
+/* Bit 0 : Start the bit counter */
+#define RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos (0UL) /*!< Position of TASKS_BCSTART field. */
+#define RADIO_TASKS_BCSTART_TASKS_BCSTART_Msk (0x1UL << RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos) /*!< Bit mask of TASKS_BCSTART field. */
+#define RADIO_TASKS_BCSTART_TASKS_BCSTART_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RADIO_TASKS_BCSTOP */
+/* Description: Stop the bit counter */
+
+/* Bit 0 : Stop the bit counter */
+#define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos (0UL) /*!< Position of TASKS_BCSTOP field. */
+#define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Msk (0x1UL << RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos) /*!< Bit mask of TASKS_BCSTOP field. */
+#define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RADIO_EVENTS_READY */
+/* Description: RADIO has ramped up and is ready to be started */
+
+/* Bit 0 : RADIO has ramped up and is ready to be started */
+#define RADIO_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
+#define RADIO_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RADIO_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
+#define RADIO_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_ADDRESS */
+/* Description: Address sent or received */
+
+/* Bit 0 : Address sent or received */
+#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos (0UL) /*!< Position of EVENTS_ADDRESS field. */
+#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Msk (0x1UL << RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos) /*!< Bit mask of EVENTS_ADDRESS field. */
+#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_PAYLOAD */
+/* Description: Packet payload sent or received */
+
+/* Bit 0 : Packet payload sent or received */
+#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos (0UL) /*!< Position of EVENTS_PAYLOAD field. */
+#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Msk (0x1UL << RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos) /*!< Bit mask of EVENTS_PAYLOAD field. */
+#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_END */
+/* Description: Packet sent or received */
+
+/* Bit 0 : Packet sent or received */
+#define RADIO_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
+#define RADIO_EVENTS_END_EVENTS_END_Msk (0x1UL << RADIO_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
+#define RADIO_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_DISABLED */
+/* Description: RADIO has been disabled */
+
+/* Bit 0 : RADIO has been disabled */
+#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos (0UL) /*!< Position of EVENTS_DISABLED field. */
+#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Msk (0x1UL << RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos) /*!< Bit mask of EVENTS_DISABLED field. */
+#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_DEVMATCH */
+/* Description: A device address match occurred on the last received packet */
+
+/* Bit 0 : A device address match occurred on the last received packet */
+#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos (0UL) /*!< Position of EVENTS_DEVMATCH field. */
+#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Msk (0x1UL << RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos) /*!< Bit mask of EVENTS_DEVMATCH field. */
+#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_DEVMISS */
+/* Description: No device address match occurred on the last received packet */
+
+/* Bit 0 : No device address match occurred on the last received packet */
+#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos (0UL) /*!< Position of EVENTS_DEVMISS field. */
+#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Msk (0x1UL << RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos) /*!< Bit mask of EVENTS_DEVMISS field. */
+#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_RSSIEND */
+/* Description: Sampling of receive signal strength complete. */
+
+/* Bit 0 : Sampling of receive signal strength complete. */
+#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos (0UL) /*!< Position of EVENTS_RSSIEND field. */
+#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Msk (0x1UL << RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos) /*!< Bit mask of EVENTS_RSSIEND field. */
+#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_BCMATCH */
+/* Description: Bit counter reached bit count value. */
+
+/* Bit 0 : Bit counter reached bit count value. */
+#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos (0UL) /*!< Position of EVENTS_BCMATCH field. */
+#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Msk (0x1UL << RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos) /*!< Bit mask of EVENTS_BCMATCH field. */
+#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_CRCOK */
+/* Description: Packet received with CRC ok */
+
+/* Bit 0 : Packet received with CRC ok */
+#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos (0UL) /*!< Position of EVENTS_CRCOK field. */
+#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Msk (0x1UL << RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos) /*!< Bit mask of EVENTS_CRCOK field. */
+#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Generated (1UL) /*!< Event generated */
+
+/* Register: RADIO_EVENTS_CRCERROR */
+/* Description: Packet received with CRC error */
+
+/* Bit 0 : Packet received with CRC error */
+#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos (0UL) /*!< Position of EVENTS_CRCERROR field. */
+#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Msk (0x1UL << RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos) /*!< Bit mask of EVENTS_CRCERROR field. */
+#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_NotGenerated (0UL) /*!< Event not generated */
+#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Generated (1UL) /*!< Event generated */
+
/* Register: RADIO_SHORTS */
-/* Description: Shortcut register */
+/* Description: Shortcuts between local events and tasks */
-/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */
+/* Bit 8 : Shortcut between event DISABLED and task RSSISTOP */
#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */
#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 6 : Shortcut between ADDRESS event and BCSTART task */
+/* Bit 6 : Shortcut between event ADDRESS and task BCSTART */
#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */
#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 5 : Shortcut between END event and START task */
+/* Bit 5 : Shortcut between event END and task START */
#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task */
+/* Bit 4 : Shortcut between event ADDRESS and task RSSISTART */
#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */
#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 3 : Shortcut between DISABLED event and RXEN task */
+/* Bit 3 : Shortcut between event DISABLED and task RXEN */
#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */
#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 2 : Shortcut between DISABLED event and TXEN task */
+/* Bit 2 : Shortcut between event DISABLED and task TXEN */
#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */
#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 1 : Shortcut between END event and DISABLE task */
+/* Bit 1 : Shortcut between event END and task DISABLE */
#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */
#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 0 : Shortcut between READY event and START task */
+/* Bit 0 : Shortcut between event READY and task START */
#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */
@@ -8559,77 +9666,77 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: RADIO_INTENSET */
/* Description: Enable interrupt */
-/* Bit 13 : Write '1' to Enable interrupt for CRCERROR event */
+/* Bit 13 : Write '1' to enable interrupt for event CRCERROR */
#define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
#define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
#define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */
-/* Bit 12 : Write '1' to Enable interrupt for CRCOK event */
+/* Bit 12 : Write '1' to enable interrupt for event CRCOK */
#define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
#define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
#define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */
-/* Bit 10 : Write '1' to Enable interrupt for BCMATCH event */
+/* Bit 10 : Write '1' to enable interrupt for event BCMATCH */
#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */
-/* Bit 7 : Write '1' to Enable interrupt for RSSIEND event */
+/* Bit 7 : Write '1' to enable interrupt for event RSSIEND */
#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */
-/* Bit 6 : Write '1' to Enable interrupt for DEVMISS event */
+/* Bit 6 : Write '1' to enable interrupt for event DEVMISS */
#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */
-/* Bit 5 : Write '1' to Enable interrupt for DEVMATCH event */
+/* Bit 5 : Write '1' to enable interrupt for event DEVMATCH */
#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */
-/* Bit 4 : Write '1' to Enable interrupt for DISABLED event */
+/* Bit 4 : Write '1' to enable interrupt for event DISABLED */
#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */
-/* Bit 3 : Write '1' to Enable interrupt for END event */
+/* Bit 3 : Write '1' to enable interrupt for event END */
#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
#define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_END_Set (1UL) /*!< Enable */
-/* Bit 2 : Write '1' to Enable interrupt for PAYLOAD event */
+/* Bit 2 : Write '1' to enable interrupt for event PAYLOAD */
#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */
-/* Bit 1 : Write '1' to Enable interrupt for ADDRESS event */
+/* Bit 1 : Write '1' to enable interrupt for event ADDRESS */
#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */
-/* Bit 0 : Write '1' to Enable interrupt for READY event */
+/* Bit 0 : Write '1' to enable interrupt for event READY */
#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
@@ -8639,77 +9746,77 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: RADIO_INTENCLR */
/* Description: Disable interrupt */
-/* Bit 13 : Write '1' to Disable interrupt for CRCERROR event */
+/* Bit 13 : Write '1' to disable interrupt for event CRCERROR */
#define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
#define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
#define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */
-/* Bit 12 : Write '1' to Disable interrupt for CRCOK event */
+/* Bit 12 : Write '1' to disable interrupt for event CRCOK */
#define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
#define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
#define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */
-/* Bit 10 : Write '1' to Disable interrupt for BCMATCH event */
+/* Bit 10 : Write '1' to disable interrupt for event BCMATCH */
#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */
-/* Bit 7 : Write '1' to Disable interrupt for RSSIEND event */
+/* Bit 7 : Write '1' to disable interrupt for event RSSIEND */
#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */
-/* Bit 6 : Write '1' to Disable interrupt for DEVMISS event */
+/* Bit 6 : Write '1' to disable interrupt for event DEVMISS */
#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */
-/* Bit 5 : Write '1' to Disable interrupt for DEVMATCH event */
+/* Bit 5 : Write '1' to disable interrupt for event DEVMATCH */
#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */
-/* Bit 4 : Write '1' to Disable interrupt for DISABLED event */
+/* Bit 4 : Write '1' to disable interrupt for event DISABLED */
#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */
-/* Bit 3 : Write '1' to Disable interrupt for END event */
+/* Bit 3 : Write '1' to disable interrupt for event END */
#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */
-/* Bit 2 : Write '1' to Disable interrupt for PAYLOAD event */
+/* Bit 2 : Write '1' to disable interrupt for event PAYLOAD */
#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */
-/* Bit 1 : Write '1' to Disable interrupt for ADDRESS event */
+/* Bit 1 : Write '1' to disable interrupt for event ADDRESS */
#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */
-/* Bit 0 : Write '1' to Disable interrupt for READY event */
+/* Bit 0 : Write '1' to disable interrupt for event READY */
#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
@@ -9035,16 +10142,16 @@ POSSIBILITY OF SUCH DAMAGE.
#define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */
/* Register: RADIO_DAB */
-/* Description: Description collection[0]: Device address base segment 0 */
+/* Description: Description collection: Device address base segment n */
-/* Bits 31..0 : Device address base segment 0 */
+/* Bits 31..0 : Device address base segment n */
#define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */
#define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */
/* Register: RADIO_DAP */
-/* Description: Description collection[0]: Device address prefix 0 */
+/* Description: Description collection: Device address prefix n */
-/* Bits 15..0 : Device address prefix 0 */
+/* Bits 15..0 : Device address prefix n */
#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
@@ -9160,10 +10267,35 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: RNG */
/* Description: Random Number Generator */
+/* Register: RNG_TASKS_START */
+/* Description: Task starting the random number generator */
+
+/* Bit 0 : Task starting the random number generator */
+#define RNG_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define RNG_TASKS_START_TASKS_START_Msk (0x1UL << RNG_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define RNG_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RNG_TASKS_STOP */
+/* Description: Task stopping the random number generator */
+
+/* Bit 0 : Task stopping the random number generator */
+#define RNG_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define RNG_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RNG_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define RNG_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RNG_EVENTS_VALRDY */
+/* Description: Event being generated for every new random number written to the VALUE register */
+
+/* Bit 0 : Event being generated for every new random number written to the VALUE register */
+#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos (0UL) /*!< Position of EVENTS_VALRDY field. */
+#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Msk (0x1UL << RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos) /*!< Bit mask of EVENTS_VALRDY field. */
+#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_NotGenerated (0UL) /*!< Event not generated */
+#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Generated (1UL) /*!< Event generated */
+
/* Register: RNG_SHORTS */
-/* Description: Shortcut register */
+/* Description: Shortcuts between local events and tasks */
-/* Bit 0 : Shortcut between VALRDY event and STOP task */
+/* Bit 0 : Shortcut between event VALRDY and task STOP */
#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
@@ -9172,7 +10304,7 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: RNG_INTENSET */
/* Description: Enable interrupt */
-/* Bit 0 : Write '1' to Enable interrupt for VALRDY event */
+/* Bit 0 : Write '1' to enable interrupt for event VALRDY */
#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */
@@ -9182,7 +10314,7 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: RNG_INTENCLR */
/* Description: Disable interrupt */
-/* Bit 0 : Write '1' to Disable interrupt for VALRDY event */
+/* Bit 0 : Write '1' to disable interrupt for event VALRDY */
#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */
@@ -9209,45 +10341,104 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: RTC */
/* Description: Real time counter 0 */
+/* Register: RTC_TASKS_START */
+/* Description: Start RTC COUNTER */
+
+/* Bit 0 : Start RTC COUNTER */
+#define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define RTC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RTC_TASKS_STOP */
+/* Description: Stop RTC COUNTER */
+
+/* Bit 0 : Stop RTC COUNTER */
+#define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RTC_TASKS_CLEAR */
+/* Description: Clear RTC COUNTER */
+
+/* Bit 0 : Clear RTC COUNTER */
+#define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
+#define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
+#define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RTC_TASKS_TRIGOVRFLW */
+/* Description: Set COUNTER to 0xFFFFF0 */
+
+/* Bit 0 : Set COUNTER to 0xFFFFF0 */
+#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */
+#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */
+#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RTC_EVENTS_TICK */
+/* Description: Event on COUNTER increment */
+
+/* Bit 0 : Event on COUNTER increment */
+#define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */
+#define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */
+#define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0UL) /*!< Event not generated */
+#define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL) /*!< Event generated */
+
+/* Register: RTC_EVENTS_OVRFLW */
+/* Description: Event on COUNTER overflow */
+
+/* Bit 0 : Event on COUNTER overflow */
+#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */
+#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */
+#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0UL) /*!< Event not generated */
+#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL) /*!< Event generated */
+
+/* Register: RTC_EVENTS_COMPARE */
+/* Description: Description collection: Compare event on CC[n] match */
+
+/* Bit 0 : Compare event on CC[n] match */
+#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
+#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
+#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */
+#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */
+
/* Register: RTC_INTENSET */
/* Description: Enable interrupt */
-/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
+/* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
-/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
+/* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
-/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
+/* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
-/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
+/* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
-/* Bit 1 : Write '1' to Enable interrupt for OVRFLW event */
+/* Bit 1 : Write '1' to enable interrupt for event OVRFLW */
#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
-/* Bit 0 : Write '1' to Enable interrupt for TICK event */
+/* Bit 0 : Write '1' to enable interrupt for event TICK */
#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
@@ -9257,42 +10448,42 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: RTC_INTENCLR */
/* Description: Disable interrupt */
-/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
+/* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
-/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
+/* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
-/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
+/* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
-/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
+/* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
-/* Bit 1 : Write '1' to Disable interrupt for OVRFLW event */
+/* Bit 1 : Write '1' to disable interrupt for event OVRFLW */
#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
-/* Bit 0 : Write '1' to Disable interrupt for TICK event */
+/* Bit 0 : Write '1' to disable interrupt for event TICK */
#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
@@ -9302,37 +10493,37 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: RTC_EVTEN */
/* Description: Enable or disable event routing */
-/* Bit 19 : Enable or disable event routing for COMPARE[3] event */
+/* Bit 19 : Enable or disable event routing for event COMPARE[3] */
#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */
-/* Bit 18 : Enable or disable event routing for COMPARE[2] event */
+/* Bit 18 : Enable or disable event routing for event COMPARE[2] */
#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */
#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */
-/* Bit 17 : Enable or disable event routing for COMPARE[1] event */
+/* Bit 17 : Enable or disable event routing for event COMPARE[1] */
#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */
#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */
-/* Bit 16 : Enable or disable event routing for COMPARE[0] event */
+/* Bit 16 : Enable or disable event routing for event COMPARE[0] */
#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */
-/* Bit 1 : Enable or disable event routing for OVRFLW event */
+/* Bit 1 : Enable or disable event routing for event OVRFLW */
#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */
-/* Bit 0 : Enable or disable event routing for TICK event */
+/* Bit 0 : Enable or disable event routing for event TICK */
#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
@@ -9341,42 +10532,42 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: RTC_EVTENSET */
/* Description: Enable event routing */
-/* Bit 19 : Write '1' to Enable event routing for COMPARE[3] event */
+/* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */
#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
-/* Bit 18 : Write '1' to Enable event routing for COMPARE[2] event */
+/* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */
#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
-/* Bit 17 : Write '1' to Enable event routing for COMPARE[1] event */
+/* Bit 17 : Write '1' to enable event routing for event COMPARE[1] */
#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
-/* Bit 16 : Write '1' to Enable event routing for COMPARE[0] event */
+/* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */
#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
-/* Bit 1 : Write '1' to Enable event routing for OVRFLW event */
+/* Bit 1 : Write '1' to enable event routing for event OVRFLW */
#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
-/* Bit 0 : Write '1' to Enable event routing for TICK event */
+/* Bit 0 : Write '1' to enable event routing for event TICK */
#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
@@ -9386,42 +10577,42 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: RTC_EVTENCLR */
/* Description: Disable event routing */
-/* Bit 19 : Write '1' to Disable event routing for COMPARE[3] event */
+/* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */
#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
-/* Bit 18 : Write '1' to Disable event routing for COMPARE[2] event */
+/* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */
#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
-/* Bit 17 : Write '1' to Disable event routing for COMPARE[1] event */
+/* Bit 17 : Write '1' to disable event routing for event COMPARE[1] */
#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
-/* Bit 16 : Write '1' to Disable event routing for COMPARE[0] event */
+/* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */
#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
-/* Bit 1 : Write '1' to Disable event routing for OVRFLW event */
+/* Bit 1 : Write '1' to disable event routing for event OVRFLW */
#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
-/* Bit 0 : Write '1' to Disable event routing for TICK event */
+/* Bit 0 : Write '1' to disable event routing for event TICK */
#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
@@ -9443,7 +10634,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
/* Register: RTC_CC */
-/* Description: Description collection[0]: Compare register 0 */
+/* Description: Description collection: Compare register n */
/* Bits 23..0 : Compare value */
#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
@@ -9453,136 +10644,240 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: SAADC */
/* Description: Analog to Digital Converter */
+/* Register: SAADC_TASKS_START */
+/* Description: Start the ADC and prepare the result buffer in RAM */
+
+/* Bit 0 : Start the ADC and prepare the result buffer in RAM */
+#define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define SAADC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SAADC_TASKS_SAMPLE */
+/* Description: Take one ADC sample, if scan is enabled all channels are sampled */
+
+/* Bit 0 : Take one ADC sample, if scan is enabled all channels are sampled */
+#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
+#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
+#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SAADC_TASKS_STOP */
+/* Description: Stop the ADC and terminate any on-going conversion */
+
+/* Bit 0 : Stop the ADC and terminate any on-going conversion */
+#define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define SAADC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SAADC_TASKS_CALIBRATEOFFSET */
+/* Description: Starts offset auto-calibration */
+
+/* Bit 0 : Starts offset auto-calibration */
+#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field. */
+#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) /*!< Bit mask of TASKS_CALIBRATEOFFSET field. */
+#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SAADC_EVENTS_STARTED */
+/* Description: The ADC has started */
+
+/* Bit 0 : The ADC has started */
+#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
+#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
+#define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: SAADC_EVENTS_END */
+/* Description: The ADC has filled up the Result buffer */
+
+/* Bit 0 : The ADC has filled up the Result buffer */
+#define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
+#define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
+#define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
+
+/* Register: SAADC_EVENTS_DONE */
+/* Description: A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */
+
+/* Bit 0 : A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */
+#define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */
+#define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */
+#define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */
+
+/* Register: SAADC_EVENTS_RESULTDONE */
+/* Description: A result is ready to get transferred to RAM. */
+
+/* Bit 0 : A result is ready to get transferred to RAM. */
+#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */
+#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask of EVENTS_RESULTDONE field. */
+#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (1UL) /*!< Event generated */
+
+/* Register: SAADC_EVENTS_CALIBRATEDONE */
+/* Description: Calibration is complete */
+
+/* Bit 0 : Calibration is complete */
+#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field. */
+#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) /*!< Bit mask of EVENTS_CALIBRATEDONE field. */
+#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (1UL) /*!< Event generated */
+
+/* Register: SAADC_EVENTS_STOPPED */
+/* Description: The ADC has stopped */
+
+/* Bit 0 : The ADC has stopped */
+#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
+#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
+#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: SAADC_EVENTS_CH_LIMITH */
+/* Description: Description cluster: Last results is equal or above CH[n].LIMIT.HIGH */
+
+/* Bit 0 : Last results is equal or above CH[n].LIMIT.HIGH */
+#define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */
+#define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */
+#define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (1UL) /*!< Event generated */
+
+/* Register: SAADC_EVENTS_CH_LIMITL */
+/* Description: Description cluster: Last results is equal or below CH[n].LIMIT.LOW */
+
+/* Bit 0 : Last results is equal or below CH[n].LIMIT.LOW */
+#define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */
+#define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field. */
+#define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (1UL) /*!< Event generated */
+
/* Register: SAADC_INTEN */
/* Description: Enable or disable interrupt */
-/* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */
+/* Bit 21 : Enable or disable interrupt for event CH7LIMITL */
#define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
#define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
#define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */
-/* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */
+/* Bit 20 : Enable or disable interrupt for event CH7LIMITH */
#define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
#define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
#define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */
-/* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */
+/* Bit 19 : Enable or disable interrupt for event CH6LIMITL */
#define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
#define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
#define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */
-/* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */
+/* Bit 18 : Enable or disable interrupt for event CH6LIMITH */
#define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
#define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
#define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */
-/* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */
+/* Bit 17 : Enable or disable interrupt for event CH5LIMITL */
#define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
#define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
#define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */
-/* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */
+/* Bit 16 : Enable or disable interrupt for event CH5LIMITH */
#define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
#define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
#define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */
-/* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */
+/* Bit 15 : Enable or disable interrupt for event CH4LIMITL */
#define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
#define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
#define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */
-/* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */
+/* Bit 14 : Enable or disable interrupt for event CH4LIMITH */
#define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
#define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
#define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */
-/* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */
+/* Bit 13 : Enable or disable interrupt for event CH3LIMITL */
#define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
#define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
#define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */
-/* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */
+/* Bit 12 : Enable or disable interrupt for event CH3LIMITH */
#define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
#define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
#define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */
-/* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */
+/* Bit 11 : Enable or disable interrupt for event CH2LIMITL */
#define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
#define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
#define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */
-/* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */
+/* Bit 10 : Enable or disable interrupt for event CH2LIMITH */
#define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
#define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
#define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */
-/* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */
+/* Bit 9 : Enable or disable interrupt for event CH1LIMITL */
#define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
#define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
#define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */
-/* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */
+/* Bit 8 : Enable or disable interrupt for event CH1LIMITH */
#define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
#define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
#define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */
-/* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */
+/* Bit 7 : Enable or disable interrupt for event CH0LIMITL */
#define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
#define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
#define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */
-/* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */
+/* Bit 6 : Enable or disable interrupt for event CH0LIMITH */
#define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
#define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
#define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */
-/* Bit 5 : Enable or disable interrupt for STOPPED event */
+/* Bit 5 : Enable or disable interrupt for event STOPPED */
#define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
#define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
-/* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */
+/* Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */
#define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
#define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
#define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */
-/* Bit 3 : Enable or disable interrupt for RESULTDONE event */
+/* Bit 3 : Enable or disable interrupt for event RESULTDONE */
#define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
#define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
#define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */
-/* Bit 2 : Enable or disable interrupt for DONE event */
+/* Bit 2 : Enable or disable interrupt for event DONE */
#define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */
#define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */
#define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */
-/* Bit 1 : Enable or disable interrupt for END event */
+/* Bit 1 : Enable or disable interrupt for event END */
#define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */
#define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */
#define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */
#define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */
-/* Bit 0 : Enable or disable interrupt for STARTED event */
+/* Bit 0 : Enable or disable interrupt for event STARTED */
#define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
#define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */
@@ -9591,154 +10886,154 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: SAADC_INTENSET */
/* Description: Enable interrupt */
-/* Bit 21 : Write '1' to Enable interrupt for CH[7].LIMITL event */
+/* Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */
#define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
#define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
#define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */
-/* Bit 20 : Write '1' to Enable interrupt for CH[7].LIMITH event */
+/* Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */
#define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
#define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
#define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */
-/* Bit 19 : Write '1' to Enable interrupt for CH[6].LIMITL event */
+/* Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */
#define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
#define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
#define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */
-/* Bit 18 : Write '1' to Enable interrupt for CH[6].LIMITH event */
+/* Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */
#define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
#define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
#define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */
-/* Bit 17 : Write '1' to Enable interrupt for CH[5].LIMITL event */
+/* Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */
#define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
#define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
#define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */
-/* Bit 16 : Write '1' to Enable interrupt for CH[5].LIMITH event */
+/* Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */
#define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
#define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
#define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */
-/* Bit 15 : Write '1' to Enable interrupt for CH[4].LIMITL event */
+/* Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */
#define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
#define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
#define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */
-/* Bit 14 : Write '1' to Enable interrupt for CH[4].LIMITH event */
+/* Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */
#define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
#define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
#define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */
-/* Bit 13 : Write '1' to Enable interrupt for CH[3].LIMITL event */
+/* Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */
#define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
#define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
#define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */
-/* Bit 12 : Write '1' to Enable interrupt for CH[3].LIMITH event */
+/* Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */
#define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
#define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
#define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */
-/* Bit 11 : Write '1' to Enable interrupt for CH[2].LIMITL event */
+/* Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */
#define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
#define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
#define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */
-/* Bit 10 : Write '1' to Enable interrupt for CH[2].LIMITH event */
+/* Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */
#define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
#define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
#define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */
-/* Bit 9 : Write '1' to Enable interrupt for CH[1].LIMITL event */
+/* Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */
#define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
#define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
#define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */
-/* Bit 8 : Write '1' to Enable interrupt for CH[1].LIMITH event */
+/* Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */
#define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
#define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
#define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */
-/* Bit 7 : Write '1' to Enable interrupt for CH[0].LIMITL event */
+/* Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */
#define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
#define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
#define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */
-/* Bit 6 : Write '1' to Enable interrupt for CH[0].LIMITH event */
+/* Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */
#define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
#define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
#define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */
-/* Bit 5 : Write '1' to Enable interrupt for STOPPED event */
+/* Bit 5 : Write '1' to enable interrupt for event STOPPED */
#define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
#define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
-/* Bit 4 : Write '1' to Enable interrupt for CALIBRATEDONE event */
+/* Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */
#define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
#define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
#define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */
-/* Bit 3 : Write '1' to Enable interrupt for RESULTDONE event */
+/* Bit 3 : Write '1' to enable interrupt for event RESULTDONE */
#define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
#define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
#define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */
-/* Bit 2 : Write '1' to Enable interrupt for DONE event */
+/* Bit 2 : Write '1' to enable interrupt for event DONE */
#define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */
#define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
#define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */
-/* Bit 1 : Write '1' to Enable interrupt for END event */
+/* Bit 1 : Write '1' to enable interrupt for event END */
#define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */
#define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
#define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_END_Set (1UL) /*!< Enable */
-/* Bit 0 : Write '1' to Enable interrupt for STARTED event */
+/* Bit 0 : Write '1' to enable interrupt for event STARTED */
#define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
#define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
@@ -9748,154 +11043,154 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: SAADC_INTENCLR */
/* Description: Disable interrupt */
-/* Bit 21 : Write '1' to Disable interrupt for CH[7].LIMITL event */
+/* Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */
#define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
#define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
#define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */
-/* Bit 20 : Write '1' to Disable interrupt for CH[7].LIMITH event */
+/* Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */
#define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
#define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
#define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */
-/* Bit 19 : Write '1' to Disable interrupt for CH[6].LIMITL event */
+/* Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */
#define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
#define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
#define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */
-/* Bit 18 : Write '1' to Disable interrupt for CH[6].LIMITH event */
+/* Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */
#define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
#define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
#define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */
-/* Bit 17 : Write '1' to Disable interrupt for CH[5].LIMITL event */
+/* Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */
#define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
#define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
#define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */
-/* Bit 16 : Write '1' to Disable interrupt for CH[5].LIMITH event */
+/* Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */
#define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
#define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
#define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */
-/* Bit 15 : Write '1' to Disable interrupt for CH[4].LIMITL event */
+/* Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */
#define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
#define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
#define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */
-/* Bit 14 : Write '1' to Disable interrupt for CH[4].LIMITH event */
+/* Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */
#define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
#define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
#define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */
-/* Bit 13 : Write '1' to Disable interrupt for CH[3].LIMITL event */
+/* Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */
#define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
#define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
#define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */
-/* Bit 12 : Write '1' to Disable interrupt for CH[3].LIMITH event */
+/* Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */
#define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
#define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
#define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */
-/* Bit 11 : Write '1' to Disable interrupt for CH[2].LIMITL event */
+/* Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */
#define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
#define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
#define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */
-/* Bit 10 : Write '1' to Disable interrupt for CH[2].LIMITH event */
+/* Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */
#define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
#define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
#define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */
-/* Bit 9 : Write '1' to Disable interrupt for CH[1].LIMITL event */
+/* Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */
#define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
#define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
#define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */
-/* Bit 8 : Write '1' to Disable interrupt for CH[1].LIMITH event */
+/* Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */
#define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
#define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
#define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */
-/* Bit 7 : Write '1' to Disable interrupt for CH[0].LIMITL event */
+/* Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */
#define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
#define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
#define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */
-/* Bit 6 : Write '1' to Disable interrupt for CH[0].LIMITH event */
+/* Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */
#define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
#define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
#define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */
-/* Bit 5 : Write '1' to Disable interrupt for STOPPED event */
+/* Bit 5 : Write '1' to disable interrupt for event STOPPED */
#define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
#define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
-/* Bit 4 : Write '1' to Disable interrupt for CALIBRATEDONE event */
+/* Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */
#define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
#define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
#define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */
-/* Bit 3 : Write '1' to Disable interrupt for RESULTDONE event */
+/* Bit 3 : Write '1' to disable interrupt for event RESULTDONE */
#define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
#define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
#define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */
-/* Bit 2 : Write '1' to Disable interrupt for DONE event */
+/* Bit 2 : Write '1' to disable interrupt for event DONE */
#define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */
#define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
#define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */
-/* Bit 1 : Write '1' to Disable interrupt for END event */
+/* Bit 1 : Write '1' to disable interrupt for event END */
#define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
#define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
#define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */
-/* Bit 0 : Write '1' to Disable interrupt for STARTED event */
+/* Bit 0 : Write '1' to disable interrupt for event STARTED */
#define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
#define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
@@ -9921,7 +11216,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */
/* Register: SAADC_CH_PSELP */
-/* Description: Description cluster[0]: Input positive pin selection for CH[0] */
+/* Description: Description cluster: Input positive pin selection for CH[n] */
/* Bits 4..0 : Analog positive input channel */
#define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */
@@ -9938,7 +11233,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */
/* Register: SAADC_CH_PSELN */
-/* Description: Description cluster[0]: Input negative pin selection for CH[0] */
+/* Description: Description cluster: Input negative pin selection for CH[n] */
/* Bits 4..0 : Analog negative input, enables differential channel */
#define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */
@@ -9955,7 +11250,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */
/* Register: SAADC_CH_CONFIG */
-/* Description: Description cluster[0]: Input configuration for CH[0] */
+/* Description: Description cluster: Input configuration for CH[n] */
/* Bit 24 : Enable burst mode */
#define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */
@@ -10014,7 +11309,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */
/* Register: SAADC_CH_LIMIT */
-/* Description: Description cluster[0]: High/low limits for event monitoring a channel */
+/* Description: Description cluster: High/low limits for event monitoring a channel */
/* Bits 31..16 : High level limit */
#define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */
@@ -10089,10 +11384,19 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: SPI */
/* Description: Serial Peripheral Interface 0 */
+/* Register: SPI_EVENTS_READY */
+/* Description: TXD byte sent and RXD byte received */
+
+/* Bit 0 : TXD byte sent and RXD byte received */
+#define SPI_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
+#define SPI_EVENTS_READY_EVENTS_READY_Msk (0x1UL << SPI_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
+#define SPI_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
+#define SPI_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
+
/* Register: SPI_INTENSET */
/* Description: Enable interrupt */
-/* Bit 2 : Write '1' to Enable interrupt for READY event */
+/* Bit 2 : Write '1' to enable interrupt for event READY */
#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
#define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
@@ -10102,7 +11406,7 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: SPI_INTENCLR */
/* Description: Disable interrupt */
-/* Bit 2 : Write '1' to Disable interrupt for READY event */
+/* Bit 2 : Write '1' to disable interrupt for event READY */
#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
@@ -10195,10 +11499,87 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: SPIM */
/* Description: Serial Peripheral Interface Master with EasyDMA 0 */
+/* Register: SPIM_TASKS_START */
+/* Description: Start SPI transaction */
+
+/* Bit 0 : Start SPI transaction */
+#define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define SPIM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SPIM_TASKS_STOP */
+/* Description: Stop SPI transaction */
+
+/* Bit 0 : Stop SPI transaction */
+#define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define SPIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SPIM_TASKS_SUSPEND */
+/* Description: Suspend SPI transaction */
+
+/* Bit 0 : Suspend SPI transaction */
+#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
+#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
+#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SPIM_TASKS_RESUME */
+/* Description: Resume SPI transaction */
+
+/* Bit 0 : Resume SPI transaction */
+#define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
+#define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
+#define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SPIM_EVENTS_STOPPED */
+/* Description: SPI transaction has stopped */
+
+/* Bit 0 : SPI transaction has stopped */
+#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
+#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
+#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: SPIM_EVENTS_ENDRX */
+/* Description: End of RXD buffer reached */
+
+/* Bit 0 : End of RXD buffer reached */
+#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
+#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
+#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
+#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
+
+/* Register: SPIM_EVENTS_END */
+/* Description: End of RXD buffer and TXD buffer reached */
+
+/* Bit 0 : End of RXD buffer and TXD buffer reached */
+#define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
+#define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
+#define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
+#define SPIM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
+
+/* Register: SPIM_EVENTS_ENDTX */
+/* Description: End of TXD buffer reached */
+
+/* Bit 0 : End of TXD buffer reached */
+#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
+#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
+#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
+#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
+
+/* Register: SPIM_EVENTS_STARTED */
+/* Description: Transaction started */
+
+/* Bit 0 : Transaction started */
+#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
+#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
+#define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
+#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
+
/* Register: SPIM_SHORTS */
-/* Description: Shortcut register */
+/* Description: Shortcuts between local events and tasks */
-/* Bit 17 : Shortcut between END event and START task */
+/* Bit 17 : Shortcut between event END and task START */
#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
@@ -10207,35 +11588,35 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: SPIM_INTENSET */
/* Description: Enable interrupt */
-/* Bit 19 : Write '1' to Enable interrupt for STARTED event */
+/* Bit 19 : Write '1' to enable interrupt for event STARTED */
#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
-/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
+/* Bit 8 : Write '1' to enable interrupt for event ENDTX */
#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
-/* Bit 6 : Write '1' to Enable interrupt for END event */
+/* Bit 6 : Write '1' to enable interrupt for event END */
#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
#define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
#define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
#define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
-/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
+/* Bit 4 : Write '1' to enable interrupt for event ENDRX */
#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
-/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+/* Bit 1 : Write '1' to enable interrupt for event STOPPED */
#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
@@ -10245,35 +11626,35 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: SPIM_INTENCLR */
/* Description: Disable interrupt */
-/* Bit 19 : Write '1' to Disable interrupt for STARTED event */
+/* Bit 19 : Write '1' to disable interrupt for event STARTED */
#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
-/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
+/* Bit 8 : Write '1' to disable interrupt for event ENDTX */
#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
-/* Bit 6 : Write '1' to Disable interrupt for END event */
+/* Bit 6 : Write '1' to disable interrupt for event END */
#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
-/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
+/* Bit 4 : Write '1' to disable interrupt for event ENDRX */
#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
-/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+/* Bit 1 : Write '1' to disable interrupt for event STOPPED */
#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
@@ -10434,10 +11815,53 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: SPIS */
/* Description: SPI Slave 0 */
+/* Register: SPIS_TASKS_ACQUIRE */
+/* Description: Acquire SPI semaphore */
+
+/* Bit 0 : Acquire SPI semaphore */
+#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */
+#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */
+#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SPIS_TASKS_RELEASE */
+/* Description: Release SPI semaphore, enabling the SPI slave to acquire it */
+
+/* Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */
+#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */
+#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */
+#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SPIS_EVENTS_END */
+/* Description: Granted transaction completed */
+
+/* Bit 0 : Granted transaction completed */
+#define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
+#define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
+#define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
+#define SPIS_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
+
+/* Register: SPIS_EVENTS_ENDRX */
+/* Description: End of RXD buffer reached */
+
+/* Bit 0 : End of RXD buffer reached */
+#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
+#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
+#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
+#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
+
+/* Register: SPIS_EVENTS_ACQUIRED */
+/* Description: Semaphore acquired */
+
+/* Bit 0 : Semaphore acquired */
+#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */
+#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */
+#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0UL) /*!< Event not generated */
+#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (1UL) /*!< Event generated */
+
/* Register: SPIS_SHORTS */
-/* Description: Shortcut register */
+/* Description: Shortcuts between local events and tasks */
-/* Bit 2 : Shortcut between END event and ACQUIRE task */
+/* Bit 2 : Shortcut between event END and task ACQUIRE */
#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */
@@ -10446,21 +11870,21 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: SPIS_INTENSET */
/* Description: Enable interrupt */
-/* Bit 10 : Write '1' to Enable interrupt for ACQUIRED event */
+/* Bit 10 : Write '1' to enable interrupt for event ACQUIRED */
#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
-/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
+/* Bit 4 : Write '1' to enable interrupt for event ENDRX */
#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */
-/* Bit 1 : Write '1' to Enable interrupt for END event */
+/* Bit 1 : Write '1' to enable interrupt for event END */
#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
#define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
@@ -10470,21 +11894,21 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: SPIS_INTENCLR */
/* Description: Disable interrupt */
-/* Bit 10 : Write '1' to Disable interrupt for ACQUIRED event */
+/* Bit 10 : Write '1' to disable interrupt for event ACQUIRED */
#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
-/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
+/* Bit 4 : Write '1' to disable interrupt for event ENDRX */
#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
-/* Bit 1 : Write '1' to Disable interrupt for END event */
+/* Bit 1 : Write '1' to disable interrupt for event END */
#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
@@ -10661,10 +12085,35 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: TEMP */
/* Description: Temperature Sensor */
+/* Register: TEMP_TASKS_START */
+/* Description: Start temperature measurement */
+
+/* Bit 0 : Start temperature measurement */
+#define TEMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define TEMP_TASKS_START_TASKS_START_Msk (0x1UL << TEMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define TEMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TEMP_TASKS_STOP */
+/* Description: Stop temperature measurement */
+
+/* Bit 0 : Stop temperature measurement */
+#define TEMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define TEMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TEMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define TEMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TEMP_EVENTS_DATARDY */
+/* Description: Temperature measurement complete, data ready */
+
+/* Bit 0 : Temperature measurement complete, data ready */
+#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos (0UL) /*!< Position of EVENTS_DATARDY field. */
+#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Msk (0x1UL << TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos) /*!< Bit mask of EVENTS_DATARDY field. */
+#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_NotGenerated (0UL) /*!< Event not generated */
+#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Generated (1UL) /*!< Event generated */
+
/* Register: TEMP_INTENSET */
/* Description: Enable interrupt */
-/* Bit 0 : Write '1' to Enable interrupt for DATARDY event */
+/* Bit 0 : Write '1' to enable interrupt for event DATARDY */
#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */
@@ -10674,7 +12123,7 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: TEMP_INTENCLR */
/* Description: Disable interrupt */
-/* Bit 0 : Write '1' to Disable interrupt for DATARDY event */
+/* Bit 0 : Write '1' to disable interrupt for event DATARDY */
#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */
@@ -10811,76 +12260,133 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: TIMER */
/* Description: Timer/Counter 0 */
+/* Register: TIMER_TASKS_START */
+/* Description: Start Timer */
+
+/* Bit 0 : Start Timer */
+#define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define TIMER_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TIMER_TASKS_STOP */
+/* Description: Stop Timer */
+
+/* Bit 0 : Stop Timer */
+#define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TIMER_TASKS_COUNT */
+/* Description: Increment Timer (Counter mode only) */
+
+/* Bit 0 : Increment Timer (Counter mode only) */
+#define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */
+#define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */
+#define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TIMER_TASKS_CLEAR */
+/* Description: Clear time */
+
+/* Bit 0 : Clear time */
+#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
+#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
+#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TIMER_TASKS_SHUTDOWN */
+/* Description: Deprecated register - Shut down timer */
+
+/* Bit 0 : Deprecated field - Shut down timer */
+#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */
+#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */
+#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TIMER_TASKS_CAPTURE */
+/* Description: Description collection: Capture Timer value to CC[n] register */
+
+/* Bit 0 : Capture Timer value to CC[n] register */
+#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */
+#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */
+#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TIMER_EVENTS_COMPARE */
+/* Description: Description collection: Compare event on CC[n] match */
+
+/* Bit 0 : Compare event on CC[n] match */
+#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
+#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
+#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */
+#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */
+
/* Register: TIMER_SHORTS */
-/* Description: Shortcut register */
+/* Description: Shortcuts between local events and tasks */
-/* Bit 13 : Shortcut between COMPARE[5] event and STOP task */
+/* Bit 13 : Shortcut between event COMPARE[5] and task STOP */
#define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */
#define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */
#define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 12 : Shortcut between COMPARE[4] event and STOP task */
+/* Bit 12 : Shortcut between event COMPARE[4] and task STOP */
#define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */
#define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */
#define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 11 : Shortcut between COMPARE[3] event and STOP task */
+/* Bit 11 : Shortcut between event COMPARE[3] and task STOP */
#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 10 : Shortcut between COMPARE[2] event and STOP task */
+/* Bit 10 : Shortcut between event COMPARE[2] and task STOP */
#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 9 : Shortcut between COMPARE[1] event and STOP task */
+/* Bit 9 : Shortcut between event COMPARE[1] and task STOP */
#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 8 : Shortcut between COMPARE[0] event and STOP task */
+/* Bit 8 : Shortcut between event COMPARE[0] and task STOP */
#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 5 : Shortcut between COMPARE[5] event and CLEAR task */
+/* Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */
#define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */
#define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */
#define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 4 : Shortcut between COMPARE[4] event and CLEAR task */
+/* Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */
#define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */
#define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */
#define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 3 : Shortcut between COMPARE[3] event and CLEAR task */
+/* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */
#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */
+/* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */
#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 1 : Shortcut between COMPARE[1] event and CLEAR task */
+/* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */
#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 0 : Shortcut between COMPARE[0] event and CLEAR task */
+/* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */
#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
@@ -10889,42 +12395,42 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: TIMER_INTENSET */
/* Description: Enable interrupt */
-/* Bit 21 : Write '1' to Enable interrupt for COMPARE[5] event */
+/* Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */
#define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
#define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
#define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
-/* Bit 20 : Write '1' to Enable interrupt for COMPARE[4] event */
+/* Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */
#define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
#define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
#define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
-/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
+/* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
-/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
+/* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
-/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
+/* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
-/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
+/* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
@@ -10934,42 +12440,42 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: TIMER_INTENCLR */
/* Description: Disable interrupt */
-/* Bit 21 : Write '1' to Disable interrupt for COMPARE[5] event */
+/* Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */
#define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
#define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
#define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
-/* Bit 20 : Write '1' to Disable interrupt for COMPARE[4] event */
+/* Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */
#define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
#define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
#define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
-/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
+/* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
-/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
+/* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
-/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
+/* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
-/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
+/* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
@@ -11005,7 +12511,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
/* Register: TIMER_CC */
-/* Description: Description collection[0]: Capture/Compare register 0 */
+/* Description: Description collection: Capture/Compare register n */
/* Bits 31..0 : Capture/Compare value */
#define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */
@@ -11015,16 +12521,110 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: TWI */
/* Description: I2C compatible Two-Wire Interface 0 */
+/* Register: TWI_TASKS_STARTRX */
+/* Description: Start TWI receive sequence */
+
+/* Bit 0 : Start TWI receive sequence */
+#define TWI_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
+#define TWI_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWI_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
+#define TWI_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWI_TASKS_STARTTX */
+/* Description: Start TWI transmit sequence */
+
+/* Bit 0 : Start TWI transmit sequence */
+#define TWI_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
+#define TWI_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWI_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
+#define TWI_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWI_TASKS_STOP */
+/* Description: Stop TWI transaction */
+
+/* Bit 0 : Stop TWI transaction */
+#define TWI_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define TWI_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWI_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define TWI_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWI_TASKS_SUSPEND */
+/* Description: Suspend TWI transaction */
+
+/* Bit 0 : Suspend TWI transaction */
+#define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
+#define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
+#define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWI_TASKS_RESUME */
+/* Description: Resume TWI transaction */
+
+/* Bit 0 : Resume TWI transaction */
+#define TWI_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
+#define TWI_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWI_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
+#define TWI_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWI_EVENTS_STOPPED */
+/* Description: TWI stopped */
+
+/* Bit 0 : TWI stopped */
+#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
+#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
+#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWI_EVENTS_RXDREADY */
+/* Description: TWI RXD byte received */
+
+/* Bit 0 : TWI RXD byte received */
+#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos (0UL) /*!< Position of EVENTS_RXDREADY field. */
+#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Msk (0x1UL << TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos) /*!< Bit mask of EVENTS_RXDREADY field. */
+#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_NotGenerated (0UL) /*!< Event not generated */
+#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Generated (1UL) /*!< Event generated */
+
+/* Register: TWI_EVENTS_TXDSENT */
+/* Description: TWI TXD byte sent */
+
+/* Bit 0 : TWI TXD byte sent */
+#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos (0UL) /*!< Position of EVENTS_TXDSENT field. */
+#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Msk (0x1UL << TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos) /*!< Bit mask of EVENTS_TXDSENT field. */
+#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_NotGenerated (0UL) /*!< Event not generated */
+#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Generated (1UL) /*!< Event generated */
+
+/* Register: TWI_EVENTS_ERROR */
+/* Description: TWI error */
+
+/* Bit 0 : TWI error */
+#define TWI_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
+#define TWI_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWI_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
+#define TWI_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
+#define TWI_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
+
+/* Register: TWI_EVENTS_BB */
+/* Description: TWI byte boundary, generated before each byte that is sent or received */
+
+/* Bit 0 : TWI byte boundary, generated before each byte that is sent or received */
+#define TWI_EVENTS_BB_EVENTS_BB_Pos (0UL) /*!< Position of EVENTS_BB field. */
+#define TWI_EVENTS_BB_EVENTS_BB_Msk (0x1UL << TWI_EVENTS_BB_EVENTS_BB_Pos) /*!< Bit mask of EVENTS_BB field. */
+#define TWI_EVENTS_BB_EVENTS_BB_NotGenerated (0UL) /*!< Event not generated */
+#define TWI_EVENTS_BB_EVENTS_BB_Generated (1UL) /*!< Event generated */
+
+/* Register: TWI_EVENTS_SUSPENDED */
+/* Description: TWI entered the suspended state */
+
+/* Bit 0 : TWI entered the suspended state */
+#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */
+#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */
+#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */
+#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */
+
/* Register: TWI_SHORTS */
-/* Description: Shortcut register */
+/* Description: Shortcuts between local events and tasks */
-/* Bit 1 : Shortcut between BB event and STOP task */
+/* Bit 1 : Shortcut between event BB and task STOP */
#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */
#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 0 : Shortcut between BB event and SUSPEND task */
+/* Bit 0 : Shortcut between event BB and task SUSPEND */
#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
@@ -11033,42 +12633,42 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: TWI_INTENSET */
/* Description: Enable interrupt */
-/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
+/* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */
#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
-/* Bit 14 : Write '1' to Enable interrupt for BB event */
+/* Bit 14 : Write '1' to enable interrupt for event BB */
#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
#define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENSET_BB_Set (1UL) /*!< Enable */
-/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
+/* Bit 9 : Write '1' to enable interrupt for event ERROR */
#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */
-/* Bit 7 : Write '1' to Enable interrupt for TXDSENT event */
+/* Bit 7 : Write '1' to enable interrupt for event TXDSENT */
#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */
-/* Bit 2 : Write '1' to Enable interrupt for RXDREADY event */
+/* Bit 2 : Write '1' to enable interrupt for event RXDREADY */
#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */
-/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+/* Bit 1 : Write '1' to enable interrupt for event STOPPED */
#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
@@ -11078,42 +12678,42 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: TWI_INTENCLR */
/* Description: Disable interrupt */
-/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
+/* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */
#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
-/* Bit 14 : Write '1' to Disable interrupt for BB event */
+/* Bit 14 : Write '1' to disable interrupt for event BB */
#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */
-/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
+/* Bit 9 : Write '1' to disable interrupt for event ERROR */
#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
-/* Bit 7 : Write '1' to Disable interrupt for TXDSENT event */
+/* Bit 7 : Write '1' to disable interrupt for event TXDSENT */
#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */
-/* Bit 2 : Write '1' to Disable interrupt for RXDREADY event */
+/* Bit 2 : Write '1' to disable interrupt for event RXDREADY */
#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */
-/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+/* Bit 1 : Write '1' to disable interrupt for event STOPPED */
#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
@@ -11204,34 +12804,137 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: TWIM */
/* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */
+/* Register: TWIM_TASKS_STARTRX */
+/* Description: Start TWI receive sequence */
+
+/* Bit 0 : Start TWI receive sequence */
+#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
+#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
+#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIM_TASKS_STARTTX */
+/* Description: Start TWI transmit sequence */
+
+/* Bit 0 : Start TWI transmit sequence */
+#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
+#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
+#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIM_TASKS_STOP */
+/* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */
+
+/* Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */
+#define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define TWIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIM_TASKS_SUSPEND */
+/* Description: Suspend TWI transaction */
+
+/* Bit 0 : Suspend TWI transaction */
+#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
+#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
+#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIM_TASKS_RESUME */
+/* Description: Resume TWI transaction */
+
+/* Bit 0 : Resume TWI transaction */
+#define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
+#define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
+#define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIM_EVENTS_STOPPED */
+/* Description: TWI stopped */
+
+/* Bit 0 : TWI stopped */
+#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
+#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
+#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIM_EVENTS_ERROR */
+/* Description: TWI error */
+
+/* Bit 0 : TWI error */
+#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
+#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
+#define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
+#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIM_EVENTS_SUSPENDED */
+/* Description: Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */
+
+/* Bit 0 : Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */
+#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */
+#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */
+#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */
+#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIM_EVENTS_RXSTARTED */
+/* Description: Receive sequence started */
+
+/* Bit 0 : Receive sequence started */
+#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
+#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
+#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIM_EVENTS_TXSTARTED */
+/* Description: Transmit sequence started */
+
+/* Bit 0 : Transmit sequence started */
+#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
+#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
+#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIM_EVENTS_LASTRX */
+/* Description: Byte boundary, starting to receive the last byte */
+
+/* Bit 0 : Byte boundary, starting to receive the last byte */
+#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */
+#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */
+#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0UL) /*!< Event not generated */
+#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIM_EVENTS_LASTTX */
+/* Description: Byte boundary, starting to transmit the last byte */
+
+/* Bit 0 : Byte boundary, starting to transmit the last byte */
+#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */
+#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */
+#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0UL) /*!< Event not generated */
+#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (1UL) /*!< Event generated */
+
/* Register: TWIM_SHORTS */
-/* Description: Shortcut register */
+/* Description: Shortcuts between local events and tasks */
-/* Bit 12 : Shortcut between LASTRX event and STOP task */
+/* Bit 12 : Shortcut between event LASTRX and task STOP */
#define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */
#define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */
#define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */
#define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 10 : Shortcut between LASTRX event and STARTTX task */
+/* Bit 10 : Shortcut between event LASTRX and task STARTTX */
#define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */
#define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */
#define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */
#define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 9 : Shortcut between LASTTX event and STOP task */
+/* Bit 9 : Shortcut between event LASTTX and task STOP */
#define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */
#define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */
#define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */
#define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 8 : Shortcut between LASTTX event and SUSPEND task */
+/* Bit 8 : Shortcut between event LASTTX and task SUSPEND */
#define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */
#define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */
#define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
#define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 7 : Shortcut between LASTTX event and STARTRX task */
+/* Bit 7 : Shortcut between event LASTTX and task STARTRX */
#define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */
#define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */
#define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
@@ -11240,43 +12943,43 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: TWIM_INTEN */
/* Description: Enable or disable interrupt */
-/* Bit 24 : Enable or disable interrupt for LASTTX event */
+/* Bit 24 : Enable or disable interrupt for event LASTTX */
#define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
#define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
#define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */
#define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
-/* Bit 23 : Enable or disable interrupt for LASTRX event */
+/* Bit 23 : Enable or disable interrupt for event LASTRX */
#define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
#define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
#define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */
#define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
-/* Bit 20 : Enable or disable interrupt for TXSTARTED event */
+/* Bit 20 : Enable or disable interrupt for event TXSTARTED */
#define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
#define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
-/* Bit 19 : Enable or disable interrupt for RXSTARTED event */
+/* Bit 19 : Enable or disable interrupt for event RXSTARTED */
#define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
#define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
-/* Bit 18 : Enable or disable interrupt for SUSPENDED event */
+/* Bit 18 : Enable or disable interrupt for event SUSPENDED */
#define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
#define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
#define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */
#define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */
-/* Bit 9 : Enable or disable interrupt for ERROR event */
+/* Bit 9 : Enable or disable interrupt for event ERROR */
#define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */
#define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
-/* Bit 1 : Enable or disable interrupt for STOPPED event */
+/* Bit 1 : Enable or disable interrupt for event STOPPED */
#define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
@@ -11285,49 +12988,49 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: TWIM_INTENSET */
/* Description: Enable interrupt */
-/* Bit 24 : Write '1' to Enable interrupt for LASTTX event */
+/* Bit 24 : Write '1' to enable interrupt for event LASTTX */
#define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
#define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
#define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
-/* Bit 23 : Write '1' to Enable interrupt for LASTRX event */
+/* Bit 23 : Write '1' to enable interrupt for event LASTRX */
#define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
#define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
#define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
-/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
+/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
#define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
-/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
+/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
#define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
-/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
+/* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */
#define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
#define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
#define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
-/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
+/* Bit 9 : Write '1' to enable interrupt for event ERROR */
#define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
-/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+/* Bit 1 : Write '1' to enable interrupt for event STOPPED */
#define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
@@ -11337,49 +13040,49 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: TWIM_INTENCLR */
/* Description: Disable interrupt */
-/* Bit 24 : Write '1' to Disable interrupt for LASTTX event */
+/* Bit 24 : Write '1' to disable interrupt for event LASTTX */
#define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
#define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
#define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
-/* Bit 23 : Write '1' to Disable interrupt for LASTRX event */
+/* Bit 23 : Write '1' to disable interrupt for event LASTRX */
#define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
#define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
#define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
-/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
+/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
#define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
-/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
+/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
#define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
-/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
+/* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */
#define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
#define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
#define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
-/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
+/* Bit 9 : Write '1' to disable interrupt for event ERROR */
#define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
-/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+/* Bit 1 : Write '1' to disable interrupt for event STOPPED */
#define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
@@ -11523,16 +13226,110 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: TWIS */
/* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */
+/* Register: TWIS_TASKS_STOP */
+/* Description: Stop TWI transaction */
+
+/* Bit 0 : Stop TWI transaction */
+#define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define TWIS_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIS_TASKS_SUSPEND */
+/* Description: Suspend TWI transaction */
+
+/* Bit 0 : Suspend TWI transaction */
+#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
+#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
+#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIS_TASKS_RESUME */
+/* Description: Resume TWI transaction */
+
+/* Bit 0 : Resume TWI transaction */
+#define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
+#define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
+#define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIS_TASKS_PREPARERX */
+/* Description: Prepare the TWI slave to respond to a write command */
+
+/* Bit 0 : Prepare the TWI slave to respond to a write command */
+#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */
+#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */
+#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIS_TASKS_PREPARETX */
+/* Description: Prepare the TWI slave to respond to a read command */
+
+/* Bit 0 : Prepare the TWI slave to respond to a read command */
+#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */
+#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */
+#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIS_EVENTS_STOPPED */
+/* Description: TWI stopped */
+
+/* Bit 0 : TWI stopped */
+#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
+#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
+#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIS_EVENTS_ERROR */
+/* Description: TWI error */
+
+/* Bit 0 : TWI error */
+#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
+#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
+#define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
+#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIS_EVENTS_RXSTARTED */
+/* Description: Receive sequence started */
+
+/* Bit 0 : Receive sequence started */
+#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
+#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
+#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIS_EVENTS_TXSTARTED */
+/* Description: Transmit sequence started */
+
+/* Bit 0 : Transmit sequence started */
+#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
+#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
+#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIS_EVENTS_WRITE */
+/* Description: Write command received */
+
+/* Bit 0 : Write command received */
+#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */
+#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */
+#define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0UL) /*!< Event not generated */
+#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIS_EVENTS_READ */
+/* Description: Read command received */
+
+/* Bit 0 : Read command received */
+#define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */
+#define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */
+#define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0UL) /*!< Event not generated */
+#define TWIS_EVENTS_READ_EVENTS_READ_Generated (1UL) /*!< Event generated */
+
/* Register: TWIS_SHORTS */
-/* Description: Shortcut register */
+/* Description: Shortcuts between local events and tasks */
-/* Bit 14 : Shortcut between READ event and SUSPEND task */
+/* Bit 14 : Shortcut between event READ and task SUSPEND */
#define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */
#define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */
#define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
#define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 13 : Shortcut between WRITE event and SUSPEND task */
+/* Bit 13 : Shortcut between event WRITE and task SUSPEND */
#define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */
#define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */
#define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
@@ -11541,37 +13338,37 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: TWIS_INTEN */
/* Description: Enable or disable interrupt */
-/* Bit 26 : Enable or disable interrupt for READ event */
+/* Bit 26 : Enable or disable interrupt for event READ */
#define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
#define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
#define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */
#define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
-/* Bit 25 : Enable or disable interrupt for WRITE event */
+/* Bit 25 : Enable or disable interrupt for event WRITE */
#define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
#define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
#define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */
#define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
-/* Bit 20 : Enable or disable interrupt for TXSTARTED event */
+/* Bit 20 : Enable or disable interrupt for event TXSTARTED */
#define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
#define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
-/* Bit 19 : Enable or disable interrupt for RXSTARTED event */
+/* Bit 19 : Enable or disable interrupt for event RXSTARTED */
#define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
#define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
-/* Bit 9 : Enable or disable interrupt for ERROR event */
+/* Bit 9 : Enable or disable interrupt for event ERROR */
#define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */
#define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
-/* Bit 1 : Enable or disable interrupt for STOPPED event */
+/* Bit 1 : Enable or disable interrupt for event STOPPED */
#define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
@@ -11580,42 +13377,42 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: TWIS_INTENSET */
/* Description: Enable interrupt */
-/* Bit 26 : Write '1' to Enable interrupt for READ event */
+/* Bit 26 : Write '1' to enable interrupt for event READ */
#define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
#define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
#define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
-/* Bit 25 : Write '1' to Enable interrupt for WRITE event */
+/* Bit 25 : Write '1' to enable interrupt for event WRITE */
#define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
#define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
#define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
-/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
+/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
#define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
-/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
+/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
#define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
-/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
+/* Bit 9 : Write '1' to enable interrupt for event ERROR */
#define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
-/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+/* Bit 1 : Write '1' to enable interrupt for event STOPPED */
#define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
@@ -11625,42 +13422,42 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: TWIS_INTENCLR */
/* Description: Disable interrupt */
-/* Bit 26 : Write '1' to Disable interrupt for READ event */
+/* Bit 26 : Write '1' to disable interrupt for event READ */
#define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
#define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
#define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
-/* Bit 25 : Write '1' to Disable interrupt for WRITE event */
+/* Bit 25 : Write '1' to disable interrupt for event WRITE */
#define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
#define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
#define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
-/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
+/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
#define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
-/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
+/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
#define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
-/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
+/* Bit 9 : Write '1' to disable interrupt for event ERROR */
#define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
-/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+/* Bit 1 : Write '1' to disable interrupt for event STOPPED */
#define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
@@ -11773,7 +13570,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Register: TWIS_ADDRESS */
-/* Description: Description collection[0]: TWI slave address 0 */
+/* Description: Description collection: TWI slave address n */
/* Bits 6..0 : TWI slave address */
#define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
@@ -11805,16 +13602,110 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: UART */
/* Description: Universal Asynchronous Receiver/Transmitter */
+/* Register: UART_TASKS_STARTRX */
+/* Description: Start UART receiver */
+
+/* Bit 0 : Start UART receiver */
+#define UART_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
+#define UART_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UART_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
+#define UART_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UART_TASKS_STOPRX */
+/* Description: Stop UART receiver */
+
+/* Bit 0 : Stop UART receiver */
+#define UART_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */
+#define UART_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UART_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */
+#define UART_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UART_TASKS_STARTTX */
+/* Description: Start UART transmitter */
+
+/* Bit 0 : Start UART transmitter */
+#define UART_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
+#define UART_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UART_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
+#define UART_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UART_TASKS_STOPTX */
+/* Description: Stop UART transmitter */
+
+/* Bit 0 : Stop UART transmitter */
+#define UART_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */
+#define UART_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UART_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */
+#define UART_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UART_TASKS_SUSPEND */
+/* Description: Suspend UART */
+
+/* Bit 0 : Suspend UART */
+#define UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
+#define UART_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
+#define UART_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UART_EVENTS_CTS */
+/* Description: CTS is activated (set low). Clear To Send. */
+
+/* Bit 0 : CTS is activated (set low). Clear To Send. */
+#define UART_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */
+#define UART_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UART_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */
+#define UART_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */
+#define UART_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */
+
+/* Register: UART_EVENTS_NCTS */
+/* Description: CTS is deactivated (set high). Not Clear To Send. */
+
+/* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */
+#define UART_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */
+#define UART_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UART_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */
+#define UART_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */
+#define UART_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */
+
+/* Register: UART_EVENTS_RXDRDY */
+/* Description: Data received in RXD */
+
+/* Bit 0 : Data received in RXD */
+#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */
+#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */
+#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */
+#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */
+
+/* Register: UART_EVENTS_TXDRDY */
+/* Description: Data sent from TXD */
+
+/* Bit 0 : Data sent from TXD */
+#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */
+#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */
+#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */
+#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */
+
+/* Register: UART_EVENTS_ERROR */
+/* Description: Error detected */
+
+/* Bit 0 : Error detected */
+#define UART_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
+#define UART_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UART_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
+#define UART_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
+#define UART_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
+
+/* Register: UART_EVENTS_RXTO */
+/* Description: Receiver timeout */
+
+/* Bit 0 : Receiver timeout */
+#define UART_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */
+#define UART_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UART_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */
+#define UART_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */
+#define UART_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */
+
/* Register: UART_SHORTS */
-/* Description: Shortcut register */
+/* Description: Shortcuts between local events and tasks */
-/* Bit 4 : Shortcut between NCTS event and STOPRX task */
+/* Bit 4 : Shortcut between event NCTS and task STOPRX */
#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */
#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 3 : Shortcut between CTS event and STARTRX task */
+/* Bit 3 : Shortcut between event CTS and task STARTRX */
#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */
@@ -11823,42 +13714,42 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: UART_INTENSET */
/* Description: Enable interrupt */
-/* Bit 17 : Write '1' to Enable interrupt for RXTO event */
+/* Bit 17 : Write '1' to enable interrupt for event RXTO */
#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */
-/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
+/* Bit 9 : Write '1' to enable interrupt for event ERROR */
#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */
-/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */
+/* Bit 7 : Write '1' to enable interrupt for event TXDRDY */
#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
-/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */
+/* Bit 2 : Write '1' to enable interrupt for event RXDRDY */
#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
-/* Bit 1 : Write '1' to Enable interrupt for NCTS event */
+/* Bit 1 : Write '1' to enable interrupt for event NCTS */
#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */
-/* Bit 0 : Write '1' to Enable interrupt for CTS event */
+/* Bit 0 : Write '1' to enable interrupt for event CTS */
#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
#define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
@@ -11868,42 +13759,42 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: UART_INTENCLR */
/* Description: Disable interrupt */
-/* Bit 17 : Write '1' to Disable interrupt for RXTO event */
+/* Bit 17 : Write '1' to disable interrupt for event RXTO */
#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
-/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
+/* Bit 9 : Write '1' to disable interrupt for event ERROR */
#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
-/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */
+/* Bit 7 : Write '1' to disable interrupt for event TXDRDY */
#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
-/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */
+/* Bit 2 : Write '1' to disable interrupt for event RXDRDY */
#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
-/* Bit 1 : Write '1' to Disable interrupt for NCTS event */
+/* Bit 1 : Write '1' to disable interrupt for event NCTS */
#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
-/* Bit 0 : Write '1' to Disable interrupt for CTS event */
+/* Bit 0 : Write '1' to disable interrupt for event CTS */
#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
@@ -12036,16 +13927,155 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: UARTE */
/* Description: UART with EasyDMA */
+/* Register: UARTE_TASKS_STARTRX */
+/* Description: Start UART receiver */
+
+/* Bit 0 : Start UART receiver */
+#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
+#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
+#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UARTE_TASKS_STOPRX */
+/* Description: Stop UART receiver */
+
+/* Bit 0 : Stop UART receiver */
+#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */
+#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */
+#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UARTE_TASKS_STARTTX */
+/* Description: Start UART transmitter */
+
+/* Bit 0 : Start UART transmitter */
+#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
+#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
+#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UARTE_TASKS_STOPTX */
+/* Description: Stop UART transmitter */
+
+/* Bit 0 : Stop UART transmitter */
+#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */
+#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */
+#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UARTE_TASKS_FLUSHRX */
+/* Description: Flush RX FIFO into RX buffer */
+
+/* Bit 0 : Flush RX FIFO into RX buffer */
+#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */
+#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */
+#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UARTE_EVENTS_CTS */
+/* Description: CTS is activated (set low). Clear To Send. */
+
+/* Bit 0 : CTS is activated (set low). Clear To Send. */
+#define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */
+#define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */
+#define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_NCTS */
+/* Description: CTS is deactivated (set high). Not Clear To Send. */
+
+/* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */
+#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */
+#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */
+#define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_RXDRDY */
+/* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */
+
+/* Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */
+#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */
+#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */
+#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_ENDRX */
+/* Description: Receive buffer is filled up */
+
+/* Bit 0 : Receive buffer is filled up */
+#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
+#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
+#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_TXDRDY */
+/* Description: Data sent from TXD */
+
+/* Bit 0 : Data sent from TXD */
+#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */
+#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */
+#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_ENDTX */
+/* Description: Last TX byte transmitted */
+
+/* Bit 0 : Last TX byte transmitted */
+#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
+#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
+#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_ERROR */
+/* Description: Error detected */
+
+/* Bit 0 : Error detected */
+#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
+#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
+#define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_RXTO */
+/* Description: Receiver timeout */
+
+/* Bit 0 : Receiver timeout */
+#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */
+#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */
+#define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_RXSTARTED */
+/* Description: UART receiver has started */
+
+/* Bit 0 : UART receiver has started */
+#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
+#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
+#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_TXSTARTED */
+/* Description: UART transmitter has started */
+
+/* Bit 0 : UART transmitter has started */
+#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
+#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
+#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_TXSTOPPED */
+/* Description: Transmitter stopped */
+
+/* Bit 0 : Transmitter stopped */
+#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */
+#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */
+#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (1UL) /*!< Event generated */
+
/* Register: UARTE_SHORTS */
-/* Description: Shortcut register */
+/* Description: Shortcuts between local events and tasks */
-/* Bit 6 : Shortcut between ENDRX event and STOPRX task */
+/* Bit 6 : Shortcut between event ENDRX and task STOPRX */
#define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */
#define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */
#define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */
#define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
-/* Bit 5 : Shortcut between ENDRX event and STARTRX task */
+/* Bit 5 : Shortcut between event ENDRX and task STARTRX */
#define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */
#define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */
#define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
@@ -12054,67 +14084,67 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: UARTE_INTEN */
/* Description: Enable or disable interrupt */
-/* Bit 22 : Enable or disable interrupt for TXSTOPPED event */
+/* Bit 22 : Enable or disable interrupt for event TXSTOPPED */
#define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
#define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
#define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */
#define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
-/* Bit 20 : Enable or disable interrupt for TXSTARTED event */
+/* Bit 20 : Enable or disable interrupt for event TXSTARTED */
#define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
#define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
-/* Bit 19 : Enable or disable interrupt for RXSTARTED event */
+/* Bit 19 : Enable or disable interrupt for event RXSTARTED */
#define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
#define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
-/* Bit 17 : Enable or disable interrupt for RXTO event */
+/* Bit 17 : Enable or disable interrupt for event RXTO */
#define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */
#define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */
#define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */
#define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
-/* Bit 9 : Enable or disable interrupt for ERROR event */
+/* Bit 9 : Enable or disable interrupt for event ERROR */
#define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */
#define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
-/* Bit 8 : Enable or disable interrupt for ENDTX event */
+/* Bit 8 : Enable or disable interrupt for event ENDTX */
#define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
#define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
#define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
-/* Bit 7 : Enable or disable interrupt for TXDRDY event */
+/* Bit 7 : Enable or disable interrupt for event TXDRDY */
#define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
#define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
#define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */
#define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */
-/* Bit 4 : Enable or disable interrupt for ENDRX event */
+/* Bit 4 : Enable or disable interrupt for event ENDRX */
#define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
#define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
-/* Bit 2 : Enable or disable interrupt for RXDRDY event */
+/* Bit 2 : Enable or disable interrupt for event RXDRDY */
#define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
#define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
#define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */
#define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */
-/* Bit 1 : Enable or disable interrupt for NCTS event */
+/* Bit 1 : Enable or disable interrupt for event NCTS */
#define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */
#define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */
#define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */
#define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
-/* Bit 0 : Enable or disable interrupt for CTS event */
+/* Bit 0 : Enable or disable interrupt for event CTS */
#define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */
#define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */
#define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */
@@ -12123,77 +14153,77 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: UARTE_INTENSET */
/* Description: Enable interrupt */
-/* Bit 22 : Write '1' to Enable interrupt for TXSTOPPED event */
+/* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */
#define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
#define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
#define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
-/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
+/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
#define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
-/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
+/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
#define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
-/* Bit 17 : Write '1' to Enable interrupt for RXTO event */
+/* Bit 17 : Write '1' to enable interrupt for event RXTO */
#define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
#define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
#define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
-/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
+/* Bit 9 : Write '1' to enable interrupt for event ERROR */
#define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
-/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
+/* Bit 8 : Write '1' to enable interrupt for event ENDTX */
#define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
#define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
-/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */
+/* Bit 7 : Write '1' to enable interrupt for event TXDRDY */
#define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
#define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
#define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
-/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
+/* Bit 4 : Write '1' to enable interrupt for event ENDRX */
#define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
-/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */
+/* Bit 2 : Write '1' to enable interrupt for event RXDRDY */
#define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
#define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
#define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
-/* Bit 1 : Write '1' to Enable interrupt for NCTS event */
+/* Bit 1 : Write '1' to enable interrupt for event NCTS */
#define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
#define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
#define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
-/* Bit 0 : Write '1' to Enable interrupt for CTS event */
+/* Bit 0 : Write '1' to enable interrupt for event CTS */
#define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
#define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
#define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
@@ -12203,77 +14233,77 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: UARTE_INTENCLR */
/* Description: Disable interrupt */
-/* Bit 22 : Write '1' to Disable interrupt for TXSTOPPED event */
+/* Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */
#define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
#define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
#define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
-/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
+/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
#define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
-/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
+/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
#define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
-/* Bit 17 : Write '1' to Disable interrupt for RXTO event */
+/* Bit 17 : Write '1' to disable interrupt for event RXTO */
#define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
#define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
#define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
-/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
+/* Bit 9 : Write '1' to disable interrupt for event ERROR */
#define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
-/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
+/* Bit 8 : Write '1' to disable interrupt for event ENDTX */
#define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
#define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
-/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */
+/* Bit 7 : Write '1' to disable interrupt for event TXDRDY */
#define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
#define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
#define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
-/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
+/* Bit 4 : Write '1' to disable interrupt for event ENDRX */
#define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
-/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */
+/* Bit 2 : Write '1' to disable interrupt for event RXDRDY */
#define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
#define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
#define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
-/* Bit 1 : Write '1' to Disable interrupt for NCTS event */
+/* Bit 1 : Write '1' to disable interrupt for event NCTS */
#define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
#define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
#define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
-/* Bit 0 : Write '1' to Disable interrupt for CTS event */
+/* Bit 0 : Write '1' to disable interrupt for event CTS */
#define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
#define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
#define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
@@ -12455,28 +14485,28 @@ POSSIBILITY OF SUCH DAMAGE.
/* Description: User Information Configuration Registers */
/* Register: UICR_NRFFW */
-/* Description: Description collection[0]: Reserved for Nordic firmware design */
+/* Description: Description collection: Reserved for Nordic firmware design */
/* Bits 31..0 : Reserved for Nordic firmware design */
#define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */
#define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */
/* Register: UICR_NRFHW */
-/* Description: Description collection[0]: Reserved for Nordic hardware design */
+/* Description: Description collection: Reserved for Nordic hardware design */
/* Bits 31..0 : Reserved for Nordic hardware design */
#define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */
#define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */
/* Register: UICR_CUSTOMER */
-/* Description: Description collection[0]: Reserved for customer */
+/* Description: Description collection: Reserved for customer */
/* Bits 31..0 : Reserved for customer */
#define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */
#define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */
/* Register: UICR_PSELRESET */
-/* Description: Description collection[0]: Mapping of the nRESET function (see POWER chapter for details) */
+/* Description: Description collection: Mapping of the nRESET function (see POWER chapter for details) */
/* Bit 31 : Connection */
#define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
@@ -12511,10 +14541,27 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: WDT */
/* Description: Watchdog Timer */
+/* Register: WDT_TASKS_START */
+/* Description: Start the watchdog */
+
+/* Bit 0 : Start the watchdog */
+#define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define WDT_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: WDT_EVENTS_TIMEOUT */
+/* Description: Watchdog timeout */
+
+/* Bit 0 : Watchdog timeout */
+#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */
+#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */
+#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0UL) /*!< Event not generated */
+#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (1UL) /*!< Event generated */
+
/* Register: WDT_INTENSET */
/* Description: Enable interrupt */
-/* Bit 0 : Write '1' to Enable interrupt for TIMEOUT event */
+/* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */
#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
@@ -12524,7 +14571,7 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: WDT_INTENCLR */
/* Description: Disable interrupt */
-/* Bit 0 : Write '1' to Disable interrupt for TIMEOUT event */
+/* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */
#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
@@ -12665,7 +14712,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */
/* Register: WDT_RR */
-/* Description: Description collection[0]: Reload request 0 */
+/* Description: Description collection: Reload request n */
/* Bits 31..0 : Reload request register */
#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
diff --git a/mcu/nrf/common/vendor/mdk/nrf52_name_change.h b/mcu/nrf/common/vendor/mdk/nrf52_name_change.h
index 6b1d6664..a2253df9 100644
--- a/mcu/nrf/common/vendor/mdk/nrf52_name_change.h
+++ b/mcu/nrf/common/vendor/mdk/nrf52_name_change.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
+Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
diff --git a/mcu/nrf/common/vendor/mdk/nrf52_to_nrf52833.h b/mcu/nrf/common/vendor/mdk/nrf52_to_nrf52833.h
index 15944c34..8efadc60 100644
--- a/mcu/nrf/common/vendor/mdk/nrf52_to_nrf52833.h
+++ b/mcu/nrf/common/vendor/mdk/nrf52_to_nrf52833.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
+Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
diff --git a/mcu/nrf/common/vendor/mdk/nrf52_to_nrf52840.h b/mcu/nrf/common/vendor/mdk/nrf52_to_nrf52840.h
index 01bf9e53..e26e601b 100644
--- a/mcu/nrf/common/vendor/mdk/nrf52_to_nrf52840.h
+++ b/mcu/nrf/common/vendor/mdk/nrf52_to_nrf52840.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
+Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
diff --git a/mcu/nrf/common/vendor/mdk/nrf9120.h b/mcu/nrf/common/vendor/mdk/nrf9120.h
new file mode 100644
index 00000000..6a62070a
--- /dev/null
+++ b/mcu/nrf/common/vendor/mdk/nrf9120.h
@@ -0,0 +1,2335 @@
+/*
+Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
+
+SPDX-License-Identifier: BSD-3-Clause
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from this
+ software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+ *
+ * @file nrf9120.h
+ * @brief CMSIS HeaderFile
+ * @version 1
+ * @date 04. April 2023
+ * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:51
+ * from File 'nrf9120.svd',
+ * last modified on Tuesday, 04.04.2023 09:57:14
+ */
+
+
+
+/** @addtogroup Nordic Semiconductor
+ * @{
+ */
+
+
+/** @addtogroup nrf9120
+ * @{
+ */
+
+
+#ifndef NRF9120_H
+#define NRF9120_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+
+
+/* =========================================================================================================================== */
+/* ================ Interrupt Number Definition ================ */
+/* =========================================================================================================================== */
+
+typedef enum {
+/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */
+ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
+ and No Match */
+ BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
+ related Fault */
+ UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */
+ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
+ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< -1 System Tick Timer */
+/* ========================================== nrf9120 Specific Interrupt Numbers =========================================== */
+ SPU_IRQn = 3, /*!< 3 SPU */
+ CLOCK_POWER_IRQn = 5, /*!< 5 CLOCK_POWER */
+ SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn= 8, /*!< 8 SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 */
+ SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQn= 9, /*!< 9 SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 */
+ SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQn= 10, /*!< 10 SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 */
+ SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQn= 11, /*!< 11 SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 */
+ GPIOTE0_IRQn = 13, /*!< 13 GPIOTE0 */
+ SAADC_IRQn = 14, /*!< 14 SAADC */
+ TIMER0_IRQn = 15, /*!< 15 TIMER0 */
+ TIMER1_IRQn = 16, /*!< 16 TIMER1 */
+ TIMER2_IRQn = 17, /*!< 17 TIMER2 */
+ RTC0_IRQn = 20, /*!< 20 RTC0 */
+ RTC1_IRQn = 21, /*!< 21 RTC1 */
+ WDT_IRQn = 24, /*!< 24 WDT */
+ EGU0_IRQn = 27, /*!< 27 EGU0 */
+ EGU1_IRQn = 28, /*!< 28 EGU1 */
+ EGU2_IRQn = 29, /*!< 29 EGU2 */
+ EGU3_IRQn = 30, /*!< 30 EGU3 */
+ EGU4_IRQn = 31, /*!< 31 EGU4 */
+ EGU5_IRQn = 32, /*!< 32 EGU5 */
+ PWM0_IRQn = 33, /*!< 33 PWM0 */
+ PWM1_IRQn = 34, /*!< 34 PWM1 */
+ PWM2_IRQn = 35, /*!< 35 PWM2 */
+ PWM3_IRQn = 36, /*!< 36 PWM3 */
+ PDM_IRQn = 38, /*!< 38 PDM */
+ I2S_IRQn = 40, /*!< 40 I2S */
+ IPC_IRQn = 42, /*!< 42 IPC */
+ FPU_IRQn = 44, /*!< 44 FPU */
+ GPIOTE1_IRQn = 49, /*!< 49 GPIOTE1 */
+ KMU_IRQn = 57, /*!< 57 KMU */
+ CRYPTOCELL_IRQn = 64 /*!< 64 CRYPTOCELL */
+} IRQn_Type;
+
+
+
+/* =========================================================================================================================== */
+/* ================ Processor and Core Peripheral Section ================ */
+/* =========================================================================================================================== */
+
+/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */
+#define __CM33_REV 0x0004U /*!< CM33 Core Revision */
+#define __INTERRUPTS_MAX 240 /*!< Top interrupt number */
+#define __DSP_PRESENT 1 /*!< DSP present or not */
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
+#define __MPU_PRESENT 1 /*!< MPU present */
+#define __FPU_PRESENT 1 /*!< FPU present */
+#define __FPU_DP 0 /*!< Double Precision FPU */
+#define __SAUREGION_PRESENT 0 /*!< SAU region present */
+
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */
+#include "system_nrf9120.h" /*!< nrf9120 System */
+
+#ifndef __IM /*!< Fallback for older CMSIS versions */
+ #define __IM __I
+#endif
+#ifndef __OM /*!< Fallback for older CMSIS versions */
+ #define __OM __O
+#endif
+#ifndef __IOM /*!< Fallback for older CMSIS versions */
+ #define __IOM __IO
+#endif
+
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Cluster Section ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_clusters
+ * @{
+ */
+
+
+/**
+ * @brief FICR_SIPINFO [SIPINFO] (SIP-specific device info)
+ */
+typedef struct {
+ __IM uint32_t PARTNO; /*!< (@ 0x00000000) SIP part number */
+ __IM uint8_t HWREVISION[4]; /*!< (@ 0x00000004) Description collection: SIP hardware revision,
+ encoded in ASCII, ex B0A or B1A */
+ __IM uint8_t VARIANT[4]; /*!< (@ 0x00000008) Description collection: SIP VARIANT, encoded
+ in ASCII, ex SIAA, SIBA or SICA */
+} FICR_SIPINFO_Type; /*!< Size = 12 (0xc) */
+
+
+/**
+ * @brief FICR_INFO [INFO] (Device info)
+ */
+typedef struct {
+ __IM uint32_t RESERVED;
+ __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000004) Description collection: Device identifier */
+ __IM uint32_t PART; /*!< (@ 0x0000000C) Part code */
+ __IM uint32_t VARIANT; /*!< (@ 0x00000010) Part Variant, Hardware version and Production
+ configuration */
+ __IM uint32_t PACKAGE; /*!< (@ 0x00000014) Package option */
+ __IM uint32_t RAM; /*!< (@ 0x00000018) RAM variant */
+ __IM uint32_t FLASH; /*!< (@ 0x0000001C) Flash variant */
+ __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000020) Code memory page size */
+ __IM uint32_t CODESIZE; /*!< (@ 0x00000024) Code memory size */
+ __IM uint32_t DEVICETYPE; /*!< (@ 0x00000028) Device type */
+} FICR_INFO_Type; /*!< Size = 44 (0x2c) */
+
+
+/**
+ * @brief FICR_TRIMCNF [TRIMCNF] (Unspecified)
+ */
+typedef struct {
+ __IM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Address */
+ __IM uint32_t DATA; /*!< (@ 0x00000004) Description cluster: Data */
+} FICR_TRIMCNF_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief FICR_TRNG90B [TRNG90B] (NIST800-90B RNG calibration data)
+ */
+typedef struct {
+ __IM uint32_t BYTES; /*!< (@ 0x00000000) Amount of bytes for the required entropy bits */
+ __IM uint32_t RCCUTOFF; /*!< (@ 0x00000004) Repetition counter cutoff */
+ __IM uint32_t APCUTOFF; /*!< (@ 0x00000008) Adaptive proportion cutoff */
+ __IM uint32_t STARTUP; /*!< (@ 0x0000000C) Amount of bytes for the startup tests */
+ __IM uint32_t ROSC1; /*!< (@ 0x00000010) Sample count for ring oscillator 1 */
+ __IM uint32_t ROSC2; /*!< (@ 0x00000014) Sample count for ring oscillator 2 */
+ __IM uint32_t ROSC3; /*!< (@ 0x00000018) Sample count for ring oscillator 3 */
+ __IM uint32_t ROSC4; /*!< (@ 0x0000001C) Sample count for ring oscillator 4 */
+} FICR_TRNG90B_Type; /*!< Size = 32 (0x20) */
+
+
+/**
+ * @brief UICR_KEYSLOT_CONFIG [CONFIG] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t DEST; /*!< (@ 0x00000000) Description cluster: Destination address where
+ content of the key value registers (KEYSLOT.KEYn.VALUE[0-3
+ ) will be pushed by KMU. Note that this
+ address must match that of a peripherals
+ APB mapped write-only key registers, else
+ the KMU can push this key value into an
+ address range which the CPU can potentially
+ read. */
+ __IOM uint32_t PERM; /*!< (@ 0x00000004) Description cluster: Define permissions for the
+ key slot. Bits 0-15 and 16-31 can only be
+ written when equal to 0xFFFF. */
+} UICR_KEYSLOT_CONFIG_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief UICR_KEYSLOT_KEY [KEY] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t VALUE[4]; /*!< (@ 0x00000000) Description collection: Define bits [31+o*32:0+o*32]
+ of value assigned to KMU key slot. */
+} UICR_KEYSLOT_KEY_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief UICR_KEYSLOT [KEYSLOT] (Unspecified)
+ */
+typedef struct {
+ __IOM UICR_KEYSLOT_CONFIG_Type CONFIG[128]; /*!< (@ 0x00000000) Unspecified */
+ __IOM UICR_KEYSLOT_KEY_Type KEY[128]; /*!< (@ 0x00000400) Unspecified */
+} UICR_KEYSLOT_Type; /*!< Size = 3072 (0xc00) */
+
+
+/**
+ * @brief TAD_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t TRACECLK; /*!< (@ 0x00000000) Pin configuration for TRACECLK */
+ __IOM uint32_t TRACEDATA0; /*!< (@ 0x00000004) Pin configuration for TRACEDATA[0] */
+ __IOM uint32_t TRACEDATA1; /*!< (@ 0x00000008) Pin configuration for TRACEDATA[1] */
+ __IOM uint32_t TRACEDATA2; /*!< (@ 0x0000000C) Pin configuration for TRACEDATA[2] */
+ __IOM uint32_t TRACEDATA3; /*!< (@ 0x00000010) Pin configuration for TRACEDATA[3] */
+} TAD_PSEL_Type; /*!< Size = 20 (0x14) */
+
+
+/**
+ * @brief SPU_EXTDOMAIN [EXTDOMAIN] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access for bus access generated
+ from the external domain n List capabilities
+ of the external domain n */
+} SPU_EXTDOMAIN_Type; /*!< Size = 4 (0x4) */
+
+
+/**
+ * @brief SPU_DPPI [DPPI] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Select between secure and
+ non-secure attribute for the DPPI channels. */
+ __IOM uint32_t LOCK; /*!< (@ 0x00000004) Description cluster: Prevent further modification
+ of the corresponding PERM register */
+} SPU_DPPI_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief SPU_GPIOPORT [GPIOPORT] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Select between secure and
+ non-secure attribute for pins 0 to 31 of
+ port n. */
+ __IOM uint32_t LOCK; /*!< (@ 0x00000004) Description cluster: Prevent further modification
+ of the corresponding PERM register */
+} SPU_GPIOPORT_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief SPU_FLASHNSC [FLASHNSC] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t REGION; /*!< (@ 0x00000000) Description cluster: Define which flash region
+ can contain the non-secure callable (NSC)
+ region n */
+ __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Define the size of the non-secure
+ callable (NSC) region n */
+} SPU_FLASHNSC_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief SPU_RAMNSC [RAMNSC] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t REGION; /*!< (@ 0x00000000) Description cluster: Define which RAM region
+ can contain the non-secure callable (NSC)
+ region n */
+ __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Define the size of the non-secure
+ callable (NSC) region n */
+} SPU_RAMNSC_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief SPU_FLASHREGION [FLASHREGION] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access permissions for flash
+ region n */
+} SPU_FLASHREGION_Type; /*!< Size = 4 (0x4) */
+
+
+/**
+ * @brief SPU_RAMREGION [RAMREGION] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access permissions for RAM
+ region n */
+} SPU_RAMREGION_Type; /*!< Size = 4 (0x4) */
+
+
+/**
+ * @brief SPU_PERIPHID [PERIPHID] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: List capabilities and access
+ permissions for the peripheral with ID n */
+} SPU_PERIPHID_Type; /*!< Size = 4 (0x4) */
+
+
+/**
+ * @brief POWER_LTEMODEM [LTEMODEM] (LTE Modem)
+ */
+typedef struct {
+ __IOM uint32_t STARTN; /*!< (@ 0x00000000) Start LTE modem */
+ __IOM uint32_t FORCEOFF; /*!< (@ 0x00000004) Force off LTE modem */
+} POWER_LTEMODEM_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief CTRLAPPERI_MAILBOX [MAILBOX] (Unspecified)
+ */
+typedef struct {
+ __IM uint32_t RXDATA; /*!< (@ 0x00000000) Data sent from the debugger to the CPU. */
+ __IM uint32_t RXSTATUS; /*!< (@ 0x00000004) This register shows a status that indicates if
+ data sent from the debugger to the CPU has
+ been read. */
+ __IM uint32_t RESERVED[30];
+ __IOM uint32_t TXDATA; /*!< (@ 0x00000080) Data sent from the CPU to the debugger. */
+ __IM uint32_t TXSTATUS; /*!< (@ 0x00000084) This register shows a status that indicates if
+ the data sent from the CPU to the debugger
+ has been read. */
+} CTRLAPPERI_MAILBOX_Type; /*!< Size = 136 (0x88) */
+
+
+/**
+ * @brief CTRLAPPERI_ERASEPROTECT [ERASEPROTECT] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t LOCK; /*!< (@ 0x00000000) This register locks the ERASEPROTECT.DISABLE
+ register from being written until next reset. */
+ __IOM uint32_t DISABLE; /*!< (@ 0x00000004) This register disables the ERASEPROTECT register
+ and performs an ERASEALL operation. */
+} CTRLAPPERI_ERASEPROTECT_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief SPIM_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */
+ __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */
+ __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */
+} SPIM_PSEL_Type; /*!< Size = 12 (0xc) */
+
+
+/**
+ * @brief SPIM_RXD [RXD] (RXD EasyDMA channel)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} SPIM_RXD_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief SPIM_TXD [TXD] (TXD EasyDMA channel)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} SPIM_TXD_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief SPIS_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */
+ __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */
+ __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */
+ __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */
+} SPIS_PSEL_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief SPIS_RXD [RXD] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} SPIS_RXD_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief SPIS_TXD [TXD] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} SPIS_TXD_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief TWIM_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */
+ __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */
+} TWIM_PSEL_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief TWIM_RXD [RXD] (RXD EasyDMA channel)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} TWIM_RXD_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief TWIM_TXD [TXD] (TXD EasyDMA channel)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} TWIM_TXD_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief TWIS_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */
+ __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */
+} TWIS_PSEL_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief TWIS_RXD [RXD] (RXD EasyDMA channel)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} TWIS_RXD_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief TWIS_TXD [TXD] (TXD EasyDMA channel)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} TWIS_TXD_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief UARTE_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */
+ __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */
+ __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */
+ __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */
+} UARTE_PSEL_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief UARTE_RXD [RXD] (RXD EasyDMA channel)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+} UARTE_RXD_Type; /*!< Size = 12 (0xc) */
+
+
+/**
+ * @brief UARTE_TXD [TXD] (TXD EasyDMA channel)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+} UARTE_TXD_Type; /*!< Size = 12 (0xc) */
+
+
+/**
+ * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.)
+ */
+typedef struct {
+ __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last results is equal or
+ above CH[n].LIMIT.HIGH */
+ __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last results is equal or
+ below CH[n].LIMIT.LOW */
+} SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief SAADC_PUBLISH_CH [PUBLISH_CH] (Publish configuration for events)
+ */
+typedef struct {
+ __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Publish configuration for
+ event CH[n].LIMITH */
+ __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Publish configuration for
+ event CH[n].LIMITL */
+} SAADC_PUBLISH_CH_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief SAADC_CH [CH] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster: Input positive pin selection
+ for CH[n] */
+ __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster: Input negative pin selection
+ for CH[n] */
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input configuration for
+ CH[n] */
+ __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster: High/low limits for event
+ monitoring a channel */
+} SAADC_CH_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of buffer words transferred since last
+ START */
+} SAADC_RESULT_Type; /*!< Size = 12 (0xc) */
+
+
+/**
+ * @brief DPPIC_TASKS_CHG [TASKS_CHG] (Channel group tasks)
+ */
+typedef struct {
+ __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */
+ __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */
+} DPPIC_TASKS_CHG_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief DPPIC_SUBSCRIBE_CHG [SUBSCRIBE_CHG] (Subscribe configuration for tasks)
+ */
+typedef struct {
+ __IOM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Subscribe configuration
+ for task CHG[n].EN */
+ __IOM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Subscribe configuration
+ for task CHG[n].DIS */
+} DPPIC_SUBSCRIBE_CHG_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief PWM_SEQ [SEQ] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning address in RAM
+ of this sequence */
+ __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster: Number of values (duty cycles)
+ in this sequence */
+ __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster: Number of additional PWM
+ periods between samples loaded into compare
+ register */
+ __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster: Time added after the sequence */
+ __IM uint32_t RESERVED[4];
+} PWM_SEQ_Type; /*!< Size = 32 (0x20) */
+
+
+/**
+ * @brief PWM_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection: Output pin select for
+ PWM channel n */
+} PWM_PSEL_Type; /*!< Size = 16 (0x10) */
+
+
+/**
+ * @brief PDM_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */
+ __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */
+} PDM_PSEL_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief PDM_SAMPLE [SAMPLE] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with
+ EasyDMA */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA
+ mode */
+} PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief I2S_CONFIG [CONFIG] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode. */
+ __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable. */
+ __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable. */
+ __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable. */
+ __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) Master clock generator frequency. */
+ __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio. */
+ __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width. */
+ __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame. */
+ __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format. */
+ __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels. */
+} I2S_CONFIG_Type; /*!< Size = 40 (0x28) */
+
+
+/**
+ * @brief I2S_RXD [RXD] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */
+} I2S_RXD_Type; /*!< Size = 4 (0x4) */
+
+
+/**
+ * @brief I2S_TXD [TXD] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address. */
+} I2S_TXD_Type; /*!< Size = 4 (0x4) */
+
+
+/**
+ * @brief I2S_RXTXD [RXTXD] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers. */
+} I2S_RXTXD_Type; /*!< Size = 4 (0x4) */
+
+
+/**
+ * @brief I2S_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal. */
+ __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal. */
+ __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal. */
+ __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal. */
+ __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal. */
+} I2S_PSEL_Type; /*!< Size = 20 (0x14) */
+
+
+/**
+ * @brief APPROTECT_SECUREAPPROTECT [SECUREAPPROTECT] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t DISABLE; /*!< (@ 0x00000000) Software disable SECUREAPPROTECT mechanism */
+ __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000004) Software force SECUREAPPROTECT mechanism */
+} APPROTECT_SECUREAPPROTECT_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief APPROTECT_APPROTECT [APPROTECT] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t DISABLE; /*!< (@ 0x00000000) Software disable APPROTECT mechanism */
+ __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000004) Software force APPROTECT mechanism */
+} APPROTECT_APPROTECT_Type; /*!< Size = 8 (0x8) */
+
+
+/**
+ * @brief VMC_RAM [RAM] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAMn power control register */
+ __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power control set register */
+ __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power control clear
+ register */
+ __IM uint32_t RESERVED;
+} VMC_RAM_Type; /*!< Size = 16 (0x10) */
+
+
+/** @} */ /* End of group Device_Peripheral_clusters */
+
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Peripheral Section ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_peripherals
+ * @{
+ */
+
+
+
+/* =========================================================================================================================== */
+/* ================ FICR_S ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Factory Information Configuration Registers (FICR_S)
+ */
+
+typedef struct { /*!< (@ 0x00FF0000) FICR_S Structure */
+ __IM uint32_t RESERVED[80];
+ __IOM FICR_SIPINFO_Type SIPINFO; /*!< (@ 0x00000140) SIP-specific device info */
+ __IM uint32_t RESERVED1[45];
+ __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000200) Device info */
+ __IM uint32_t RESERVED2[53];
+ __IOM FICR_TRIMCNF_Type TRIMCNF[256]; /*!< (@ 0x00000300) Unspecified */
+ __IM uint32_t RESERVED3[64];
+ __IOM FICR_TRNG90B_Type TRNG90B; /*!< (@ 0x00000C00) NIST800-90B RNG calibration data */
+} NRF_FICR_Type; /*!< Size = 3104 (0xc20) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ UICR_S ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief User information configuration registers User information configuration registers (UICR_S)
+ */
+
+typedef struct { /*!< (@ 0x00FF8000) UICR_S Structure */
+ __IOM uint32_t APPROTECT; /*!< (@ 0x00000000) Access port protection */
+ __IM uint32_t RESERVED[4];
+ __IOM uint32_t XOSC32M; /*!< (@ 0x00000014) Oscillator control */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t HFXOSRC; /*!< (@ 0x0000001C) HFXO clock source selection */
+ __IOM uint32_t HFXOCNT; /*!< (@ 0x00000020) HFXO startup counter */
+ __IOM uint32_t APPNVMCPOFGUARD; /*!< (@ 0x00000024) Enable blocking NVM WRITE and aborting NVM ERASE
+ for Application NVM in POFWARN condition
+ . */
+ __IOM uint32_t PMICCONF; /*!< (@ 0x00000028) Polarity of PMIC polarity configuration signals. */
+ __IOM uint32_t SECUREAPPROTECT; /*!< (@ 0x0000002C) Secure access port protection */
+ __IOM uint32_t ERASEPROTECT; /*!< (@ 0x00000030) Erase protection */
+ __IM uint32_t RESERVED2[53];
+ __IOM uint32_t OTP[190]; /*!< (@ 0x00000108) Description collection: One time programmable
+ memory */
+ __IOM UICR_KEYSLOT_Type KEYSLOT; /*!< (@ 0x00000400) Unspecified */
+} NRF_UICR_Type; /*!< Size = 4096 (0x1000) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TAD_S ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Trace and debug control (TAD_S)
+ */
+
+typedef struct { /*!< (@ 0xE0080000) TAD_S Structure */
+ __OM uint32_t TASKS_CLOCKSTART; /*!< (@ 0x00000000) Start all trace and debug clocks. */
+ __OM uint32_t TASKS_CLOCKSTOP; /*!< (@ 0x00000004) Stop all trace and debug clocks. */
+ __IM uint32_t RESERVED[318];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable debug domain and aquire selected GPIOs */
+ __IOM TAD_PSEL_Type PSEL; /*!< (@ 0x00000504) Unspecified */
+ __IOM uint32_t TRACEPORTSPEED; /*!< (@ 0x00000518) Clocking options for the Trace Port debug interface
+ Reset behavior is the same as debug components */
+} NRF_TAD_Type; /*!< Size = 1308 (0x51c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SPU_S ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief System protection unit (SPU_S)
+ */
+
+typedef struct { /*!< (@ 0x50003000) SPU_S Structure */
+ __IM uint32_t RESERVED[64];
+ __IOM uint32_t EVENTS_RAMACCERR; /*!< (@ 0x00000100) A security violation has been detected for the
+ RAM memory space */
+ __IOM uint32_t EVENTS_FLASHACCERR; /*!< (@ 0x00000104) A security violation has been detected for the
+ flash memory space */
+ __IOM uint32_t EVENTS_PERIPHACCERR; /*!< (@ 0x00000108) A security violation has been detected on one
+ or several peripherals */
+ __IM uint32_t RESERVED1[29];
+ __IOM uint32_t PUBLISH_RAMACCERR; /*!< (@ 0x00000180) Publish configuration for event RAMACCERR */
+ __IOM uint32_t PUBLISH_FLASHACCERR; /*!< (@ 0x00000184) Publish configuration for event FLASHACCERR */
+ __IOM uint32_t PUBLISH_PERIPHACCERR; /*!< (@ 0x00000188) Publish configuration for event PERIPHACCERR */
+ __IM uint32_t RESERVED2[93];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED3[61];
+ __IM uint32_t CAP; /*!< (@ 0x00000400) Show implemented features for the current device */
+ __IM uint32_t RESERVED4[15];
+ __IOM SPU_EXTDOMAIN_Type EXTDOMAIN[1]; /*!< (@ 0x00000440) Unspecified */
+ __IM uint32_t RESERVED5[15];
+ __IOM SPU_DPPI_Type DPPI[1]; /*!< (@ 0x00000480) Unspecified */
+ __IM uint32_t RESERVED6[14];
+ __IOM SPU_GPIOPORT_Type GPIOPORT[1]; /*!< (@ 0x000004C0) Unspecified */
+ __IM uint32_t RESERVED7[14];
+ __IOM SPU_FLASHNSC_Type FLASHNSC[2]; /*!< (@ 0x00000500) Unspecified */
+ __IM uint32_t RESERVED8[12];
+ __IOM SPU_RAMNSC_Type RAMNSC[2]; /*!< (@ 0x00000540) Unspecified */
+ __IM uint32_t RESERVED9[44];
+ __IOM SPU_FLASHREGION_Type FLASHREGION[32]; /*!< (@ 0x00000600) Unspecified */
+ __IM uint32_t RESERVED10[32];
+ __IOM SPU_RAMREGION_Type RAMREGION[32]; /*!< (@ 0x00000700) Unspecified */
+ __IM uint32_t RESERVED11[32];
+ __IOM SPU_PERIPHID_Type PERIPHID[67]; /*!< (@ 0x00000800) Unspecified */
+} NRF_SPU_Type; /*!< Size = 2316 (0x90c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ REGULATORS_NS ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Voltage regulators control 0 (REGULATORS_NS)
+ */
+
+typedef struct { /*!< (@ 0x40004000) REGULATORS_NS Structure */
+ __IM uint32_t RESERVED[320];
+ __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */
+ __IM uint32_t RESERVED1[4];
+ __IOM uint32_t EXTPOFCON; /*!< (@ 0x00000514) External power failure warning configuration */
+ __IM uint32_t RESERVED2[24];
+ __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC mode of the main voltage regulator. */
+} NRF_REGULATORS_Type; /*!< Size = 1404 (0x57c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CLOCK_NS ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Clock management 0 (CLOCK_NS)
+ */
+
+typedef struct { /*!< (@ 0x40005000) CLOCK_NS Structure */
+ __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK source */
+ __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK source */
+ __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source */
+ __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */
+ __IM uint32_t RESERVED[28];
+ __IOM uint32_t SUBSCRIBE_HFCLKSTART; /*!< (@ 0x00000080) Subscribe configuration for task HFCLKSTART */
+ __IOM uint32_t SUBSCRIBE_HFCLKSTOP; /*!< (@ 0x00000084) Subscribe configuration for task HFCLKSTOP */
+ __IOM uint32_t SUBSCRIBE_LFCLKSTART; /*!< (@ 0x00000088) Subscribe configuration for task LFCLKSTART */
+ __IOM uint32_t SUBSCRIBE_LFCLKSTOP; /*!< (@ 0x0000008C) Subscribe configuration for task LFCLKSTOP */
+ __IM uint32_t RESERVED1[28];
+ __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started */
+ __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */
+ __IM uint32_t RESERVED2[30];
+ __IOM uint32_t PUBLISH_HFCLKSTARTED; /*!< (@ 0x00000180) Publish configuration for event HFCLKSTARTED */
+ __IOM uint32_t PUBLISH_LFCLKSTARTED; /*!< (@ 0x00000184) Publish configuration for event LFCLKSTARTED */
+ __IM uint32_t RESERVED3[94];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */
+ __IM uint32_t RESERVED4[62];
+ __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been
+ triggered */
+ __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) The register shows if HFXO has been requested
+ by triggering HFCLKSTART task and if it
+ has been started (STATE) */
+ __IM uint32_t RESERVED5;
+ __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been
+ triggered */
+ __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) The register shows which LFCLK source has been
+ requested (SRC) when triggering LFCLKSTART
+ task and if the source has been started
+ (STATE) */
+ __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set after LFCLKSTART
+ task has been triggered */
+ __IM uint32_t RESERVED6[62];
+ __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK. LFCLKSTART task starts
+ starts a clock source selected with this
+ register. */
+} NRF_CLOCK_Type; /*!< Size = 1308 (0x51c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ POWER_NS ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Power control 0 (POWER_NS)
+ */
+
+typedef struct { /*!< (@ 0x40005000) POWER_NS Structure */
+ __IM uint32_t RESERVED[28];
+ __OM uint32_t TASKS_PWMREQSTART; /*!< (@ 0x00000070) Request forcing PWM mode in external DC/DC voltage
+ regulator. (Drives FPWM_DCDC pin high or
+ low depending on a setting in UICR). */
+ __OM uint32_t TASKS_PWMREQSTOP; /*!< (@ 0x00000074) Stop requesting forcing PWM mode in external
+ DC/DC voltage regulator */
+ __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode. */
+ __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */
+ __IM uint32_t RESERVED1[28];
+ __IOM uint32_t SUBSCRIBE_PWMREQSTART; /*!< (@ 0x000000F0) Subscribe configuration for task PWMREQSTART */
+ __IOM uint32_t SUBSCRIBE_PWMREQSTOP; /*!< (@ 0x000000F4) Subscribe configuration for task PWMREQSTOP */
+ __IOM uint32_t SUBSCRIBE_CONSTLAT; /*!< (@ 0x000000F8) Subscribe configuration for task CONSTLAT */
+ __IOM uint32_t SUBSCRIBE_LOWPWR; /*!< (@ 0x000000FC) Subscribe configuration for task LOWPWR */
+ __IM uint32_t RESERVED2[2];
+ __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */
+ __IM uint32_t RESERVED3[2];
+ __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */
+ __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */
+ __IM uint32_t RESERVED4[27];
+ __IOM uint32_t PUBLISH_POFWARN; /*!< (@ 0x00000188) Publish configuration for event POFWARN */
+ __IM uint32_t RESERVED5[2];
+ __IOM uint32_t PUBLISH_SLEEPENTER; /*!< (@ 0x00000194) Publish configuration for event SLEEPENTER */
+ __IOM uint32_t PUBLISH_SLEEPEXIT; /*!< (@ 0x00000198) Publish configuration for event SLEEPEXIT */
+ __IM uint32_t RESERVED6[89];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED7[61];
+ __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */
+ __IM uint32_t RESERVED8[15];
+ __IM uint32_t POWERSTATUS; /*!< (@ 0x00000440) Modem domain power status */
+ __IM uint32_t RESERVED9[54];
+ __IOM uint32_t GPREGRET[2]; /*!< (@ 0x0000051C) Description collection: General purpose retention
+ register */
+ __IM uint32_t RESERVED10[59];
+ __IOM POWER_LTEMODEM_Type LTEMODEM; /*!< (@ 0x00000610) LTE Modem */
+} NRF_POWER_Type; /*!< Size = 1560 (0x618) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CTRL_AP_PERI_S ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Control access port (CTRL_AP_PERI_S)
+ */
+
+typedef struct { /*!< (@ 0x50006000) CTRL_AP_PERI_S Structure */
+ __IM uint32_t RESERVED[256];
+ __IOM CTRLAPPERI_MAILBOX_Type MAILBOX; /*!< (@ 0x00000400) Unspecified */
+ __IM uint32_t RESERVED1[30];
+ __IOM CTRLAPPERI_ERASEPROTECT_Type ERASEPROTECT;/*!< (@ 0x00000500) Unspecified */
+} NRF_CTRLAPPERI_Type; /*!< Size = 1288 (0x508) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SPIM0_NS ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0_NS)
+ */
+
+typedef struct { /*!< (@ 0x40008000) SPIM0_NS Structure */
+ __IM uint32_t RESERVED[4];
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */
+ __IM uint32_t RESERVED1;
+ __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */
+ __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */
+ __IM uint32_t RESERVED2[27];
+ __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000090) Subscribe configuration for task START */
+ __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */
+ __IM uint32_t RESERVED3;
+ __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */
+ __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */
+ __IM uint32_t RESERVED4[24];
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */
+ __IM uint32_t RESERVED5[2];
+ __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */
+ __IM uint32_t RESERVED6;
+ __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */
+ __IM uint32_t RESERVED7;
+ __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */
+ __IM uint32_t RESERVED8[10];
+ __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */
+ __IM uint32_t RESERVED9[13];
+ __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */
+ __IM uint32_t RESERVED10[2];
+ __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */
+ __IM uint32_t RESERVED11;
+ __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000198) Publish configuration for event END */
+ __IM uint32_t RESERVED12;
+ __IOM uint32_t PUBLISH_ENDTX; /*!< (@ 0x000001A0) Publish configuration for event ENDTX */
+ __IM uint32_t RESERVED13[10];
+ __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x000001CC) Publish configuration for event STARTED */
+ __IM uint32_t RESERVED14[12];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED15[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED16[125];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */
+ __IM uint32_t RESERVED17;
+ __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
+ __IM uint32_t RESERVED18[4];
+ __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK
+ source selected. */
+ __IM uint32_t RESERVED19[3];
+ __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */
+ __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */
+ __IM uint32_t RESERVED20[26];
+ __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character clocked out in
+ case an over-read of the TXD buffer. */
+} NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SPIS0_NS ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief SPI Slave 0 (SPIS0_NS)
+ */
+
+typedef struct { /*!< (@ 0x40008000) SPIS0_NS Structure */
+ __IM uint32_t RESERVED[9];
+ __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */
+ __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave
+ to acquire it */
+ __IM uint32_t RESERVED1[30];
+ __IOM uint32_t SUBSCRIBE_ACQUIRE; /*!< (@ 0x000000A4) Subscribe configuration for task ACQUIRE */
+ __IOM uint32_t SUBSCRIBE_RELEASE; /*!< (@ 0x000000A8) Subscribe configuration for task RELEASE */
+ __IM uint32_t RESERVED2[22];
+ __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */
+ __IM uint32_t RESERVED3[2];
+ __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */
+ __IM uint32_t RESERVED4[5];
+ __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */
+ __IM uint32_t RESERVED5[22];
+ __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */
+ __IM uint32_t RESERVED6[2];
+ __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */
+ __IM uint32_t RESERVED7[5];
+ __IOM uint32_t PUBLISH_ACQUIRED; /*!< (@ 0x000001A8) Publish configuration for event ACQUIRED */
+ __IM uint32_t RESERVED8[21];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED9[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED10[61];
+ __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */
+ __IM uint32_t RESERVED11[15];
+ __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */
+ __IM uint32_t RESERVED12[47];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */
+ __IM uint32_t RESERVED13;
+ __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
+ __IM uint32_t RESERVED14[7];
+ __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */
+ __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */
+ __IM uint32_t RESERVED15;
+ __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case
+ of an ignored transaction. */
+ __IM uint32_t RESERVED16[24];
+ __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */
+} NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TWIM0_NS ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0_NS)
+ */
+
+typedef struct { /*!< (@ 0x40008000) TWIM0_NS Structure */
+ __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */
+ __IM uint32_t RESERVED;
+ __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */
+ __IM uint32_t RESERVED1[2];
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the
+ TWI master is not suspended. */
+ __IM uint32_t RESERVED2;
+ __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */
+ __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */
+ __IM uint32_t RESERVED3[23];
+ __IOM uint32_t SUBSCRIBE_STARTRX; /*!< (@ 0x00000080) Subscribe configuration for task STARTRX */
+ __IM uint32_t RESERVED4;
+ __IOM uint32_t SUBSCRIBE_STARTTX; /*!< (@ 0x00000088) Subscribe configuration for task STARTTX */
+ __IM uint32_t RESERVED5[2];
+ __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */
+ __IM uint32_t RESERVED6;
+ __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */
+ __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */
+ __IM uint32_t RESERVED7[24];
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */
+ __IM uint32_t RESERVED8[7];
+ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */
+ __IM uint32_t RESERVED9[8];
+ __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) SUSPEND task has been issued, TWI traffic is
+ now suspended. */
+ __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */
+ __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */
+ __IM uint32_t RESERVED10[2];
+ __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */
+ __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last
+ byte */
+ __IM uint32_t RESERVED11[8];
+ __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */
+ __IM uint32_t RESERVED12[7];
+ __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */
+ __IM uint32_t RESERVED13[8];
+ __IOM uint32_t PUBLISH_SUSPENDED; /*!< (@ 0x000001C8) Publish configuration for event SUSPENDED */
+ __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */
+ __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */
+ __IM uint32_t RESERVED14[2];
+ __IOM uint32_t PUBLISH_LASTRX; /*!< (@ 0x000001DC) Publish configuration for event LASTRX */
+ __IOM uint32_t PUBLISH_LASTTX; /*!< (@ 0x000001E0) Publish configuration for event LASTTX */
+ __IM uint32_t RESERVED15[7];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED16[63];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED17[110];
+ __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */
+ __IM uint32_t RESERVED18[14];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */
+ __IM uint32_t RESERVED19;
+ __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
+ __IM uint32_t RESERVED20[5];
+ __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK
+ source selected. */
+ __IM uint32_t RESERVED21[3];
+ __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */
+ __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */
+ __IM uint32_t RESERVED22[13];
+ __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */
+} NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TWIS0_NS ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0_NS)
+ */
+
+typedef struct { /*!< (@ 0x40008000) TWIS0_NS Structure */
+ __IM uint32_t RESERVED[5];
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */
+ __IM uint32_t RESERVED1;
+ __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */
+ __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */
+ __IM uint32_t RESERVED2[3];
+ __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */
+ __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */
+ __IM uint32_t RESERVED3[23];
+ __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */
+ __IM uint32_t RESERVED4;
+ __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */
+ __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */
+ __IM uint32_t RESERVED5[3];
+ __IOM uint32_t SUBSCRIBE_PREPARERX; /*!< (@ 0x000000B0) Subscribe configuration for task PREPARERX */
+ __IOM uint32_t SUBSCRIBE_PREPARETX; /*!< (@ 0x000000B4) Subscribe configuration for task PREPARETX */
+ __IM uint32_t RESERVED6[19];
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */
+ __IM uint32_t RESERVED7[7];
+ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */
+ __IM uint32_t RESERVED8[9];
+ __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */
+ __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */
+ __IM uint32_t RESERVED9[4];
+ __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */
+ __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */
+ __IM uint32_t RESERVED10[6];
+ __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */
+ __IM uint32_t RESERVED11[7];
+ __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */
+ __IM uint32_t RESERVED12[9];
+ __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */
+ __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */
+ __IM uint32_t RESERVED13[4];
+ __IOM uint32_t PUBLISH_WRITE; /*!< (@ 0x000001E4) Publish configuration for event WRITE */
+ __IOM uint32_t PUBLISH_READ; /*!< (@ 0x000001E8) Publish configuration for event READ */
+ __IM uint32_t RESERVED14[5];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED15[63];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED16[113];
+ __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */
+ __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had
+ a match */
+ __IM uint32_t RESERVED17[10];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */
+ __IM uint32_t RESERVED18;
+ __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
+ __IM uint32_t RESERVED19[9];
+ __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */
+ __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */
+ __IM uint32_t RESERVED20[13];
+ __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */
+ __IM uint32_t RESERVED21;
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match
+ mechanism */
+ __IM uint32_t RESERVED22[10];
+ __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case
+ of an over-read of the transmit buffer. */
+} NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ UARTE0_NS ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief UART with EasyDMA 0 (UARTE0_NS)
+ */
+
+typedef struct { /*!< (@ 0x40008000) UARTE0_NS Structure */
+ __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */
+ __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */
+ __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */
+ __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */
+ __IM uint32_t RESERVED[7];
+ __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */
+ __IM uint32_t RESERVED1[20];
+ __IOM uint32_t SUBSCRIBE_STARTRX; /*!< (@ 0x00000080) Subscribe configuration for task STARTRX */
+ __IOM uint32_t SUBSCRIBE_STOPRX; /*!< (@ 0x00000084) Subscribe configuration for task STOPRX */
+ __IOM uint32_t SUBSCRIBE_STARTTX; /*!< (@ 0x00000088) Subscribe configuration for task STARTTX */
+ __IOM uint32_t SUBSCRIBE_STOPTX; /*!< (@ 0x0000008C) Subscribe configuration for task STOPTX */
+ __IM uint32_t RESERVED2[7];
+ __IOM uint32_t SUBSCRIBE_FLUSHRX; /*!< (@ 0x000000AC) Subscribe configuration for task FLUSHRX */
+ __IM uint32_t RESERVED3[20];
+ __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */
+ __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */
+ __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet
+ transferred to Data RAM) */
+ __IM uint32_t RESERVED4;
+ __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */
+ __IM uint32_t RESERVED5[2];
+ __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */
+ __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */
+ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */
+ __IM uint32_t RESERVED6[7];
+ __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */
+ __IM uint32_t RESERVED7;
+ __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */
+ __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */
+ __IM uint32_t RESERVED8;
+ __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */
+ __IM uint32_t RESERVED9[9];
+ __IOM uint32_t PUBLISH_CTS; /*!< (@ 0x00000180) Publish configuration for event CTS */
+ __IOM uint32_t PUBLISH_NCTS; /*!< (@ 0x00000184) Publish configuration for event NCTS */
+ __IOM uint32_t PUBLISH_RXDRDY; /*!< (@ 0x00000188) Publish configuration for event RXDRDY */
+ __IM uint32_t RESERVED10;
+ __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */
+ __IM uint32_t RESERVED11[2];
+ __IOM uint32_t PUBLISH_TXDRDY; /*!< (@ 0x0000019C) Publish configuration for event TXDRDY */
+ __IOM uint32_t PUBLISH_ENDTX; /*!< (@ 0x000001A0) Publish configuration for event ENDTX */
+ __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */
+ __IM uint32_t RESERVED12[7];
+ __IOM uint32_t PUBLISH_RXTO; /*!< (@ 0x000001C4) Publish configuration for event RXTO */
+ __IM uint32_t RESERVED13;
+ __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */
+ __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */
+ __IM uint32_t RESERVED14;
+ __IOM uint32_t PUBLISH_TXSTOPPED; /*!< (@ 0x000001D8) Publish configuration for event TXSTOPPED */
+ __IM uint32_t RESERVED15[9];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED16[63];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED17[93];
+ __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source This register is read/write one
+ to clear. */
+ __IM uint32_t RESERVED18[31];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */
+ __IM uint32_t RESERVED19;
+ __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
+ __IM uint32_t RESERVED20[3];
+ __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source
+ selected. */
+ __IM uint32_t RESERVED21[3];
+ __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */
+ __IM uint32_t RESERVED22;
+ __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */
+ __IM uint32_t RESERVED23[7];
+ __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */
+} NRF_UARTE_Type; /*!< Size = 1392 (0x570) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOTE0_S ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief GPIO Tasks and Events 0 (GPIOTE0_S)
+ */
+
+typedef struct { /*!< (@ 0x5000D000) GPIOTE0_S Structure */
+ __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin
+ specified in CONFIG[n].PSEL. Action on pin
+ is configured in CONFIG[n].POLARITY. */
+ __IM uint32_t RESERVED[4];
+ __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin
+ specified in CONFIG[n].PSEL. Action on pin
+ is to set it high. */
+ __IM uint32_t RESERVED1[4];
+ __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin
+ specified in CONFIG[n].PSEL. Action on pin
+ is to set it low. */
+ __IOM uint32_t SUBSCRIBE_OUT[8]; /*!< (@ 0x00000080) Description collection: Subscribe configuration
+ for task OUT[n] */
+ __IM uint32_t RESERVED2[4];
+ __IOM uint32_t SUBSCRIBE_SET[8]; /*!< (@ 0x000000B0) Description collection: Subscribe configuration
+ for task SET[n] */
+ __IM uint32_t RESERVED3[4];
+ __IOM uint32_t SUBSCRIBE_CLR[8]; /*!< (@ 0x000000E0) Description collection: Subscribe configuration
+ for task CLR[n] */
+ __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from
+ pin specified in CONFIG[n].PSEL */
+ __IM uint32_t RESERVED4[23];
+ __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins
+ with SENSE mechanism enabled */
+ __IOM uint32_t PUBLISH_IN[8]; /*!< (@ 0x00000180) Description collection: Publish configuration
+ for event IN[n] */
+ __IM uint32_t RESERVED5[23];
+ __IOM uint32_t PUBLISH_PORT; /*!< (@ 0x000001FC) Publish configuration for event PORT */
+ __IM uint32_t RESERVED6[65];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED7[129];
+ __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n],
+ SET[n], and CLR[n] tasks and IN[n] event */
+} NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SAADC_NS ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Analog to Digital Converter 0 (SAADC_NS)
+ */
+
+typedef struct { /*!< (@ 0x4000E000) SAADC_NS Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in
+ RAM */
+ __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels
+ are sampled */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion */
+ __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */
+ __IM uint32_t RESERVED[28];
+ __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */
+ __IOM uint32_t SUBSCRIBE_SAMPLE; /*!< (@ 0x00000084) Subscribe configuration for task SAMPLE */
+ __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000088) Subscribe configuration for task STOP */
+ __IOM uint32_t SUBSCRIBE_CALIBRATEOFFSET; /*!< (@ 0x0000008C) Subscribe configuration for task CALIBRATEOFFSET */
+ __IM uint32_t RESERVED1[28];
+ __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The ADC has started */
+ __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The ADC has filled up the Result buffer */
+ __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending
+ on the mode, multiple conversions might
+ be needed for a result to be transferred
+ to RAM. */
+ __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */
+ __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */
+ __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */
+ __IM uint32_t RESERVED2[10];
+ __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x00000180) Publish configuration for event STARTED */
+ __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */
+ __IOM uint32_t PUBLISH_DONE; /*!< (@ 0x00000188) Publish configuration for event DONE */
+ __IOM uint32_t PUBLISH_RESULTDONE; /*!< (@ 0x0000018C) Publish configuration for event RESULTDONE */
+ __IOM uint32_t PUBLISH_CALIBRATEDONE; /*!< (@ 0x00000190) Publish configuration for event CALIBRATEDONE */
+ __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000194) Publish configuration for event STOPPED */
+ __IOM SAADC_PUBLISH_CH_Type PUBLISH_CH[8]; /*!< (@ 0x00000198) Publish configuration for events */
+ __IM uint32_t RESERVED3[74];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED4[61];
+ __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */
+ __IM uint32_t RESERVED5[63];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */
+ __IM uint32_t RESERVED6[3];
+ __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */
+ __IM uint32_t RESERVED7[24];
+ __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */
+ __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should
+ not be combined with SCAN. The RESOLUTION
+ is applied before averaging, thus for high
+ OVERSAMPLE a higher RESOLUTION should be
+ used. */
+ __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */
+ __IM uint32_t RESERVED8[12];
+ __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */
+} NRF_SAADC_Type; /*!< Size = 1592 (0x638) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TIMER0_NS ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Timer/Counter 0 (TIMER0_NS)
+ */
+
+typedef struct { /*!< (@ 0x4000F000) TIMER0_NS Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */
+ __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */
+ __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */
+ __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */
+ __IM uint32_t RESERVED[11];
+ __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to
+ CC[n] register */
+ __IM uint32_t RESERVED1[10];
+ __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */
+ __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */
+ __IOM uint32_t SUBSCRIBE_COUNT; /*!< (@ 0x00000088) Subscribe configuration for task COUNT */
+ __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x0000008C) Subscribe configuration for task CLEAR */
+ __IOM uint32_t SUBSCRIBE_SHUTDOWN; /*!< (@ 0x00000090) Deprecated register - Subscribe configuration
+ for task SHUTDOWN */
+ __IM uint32_t RESERVED2[11];
+ __IOM uint32_t SUBSCRIBE_CAPTURE[6]; /*!< (@ 0x000000C0) Description collection: Subscribe configuration
+ for task CAPTURE[n] */
+ __IM uint32_t RESERVED3[26];
+ __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n]
+ match */
+ __IM uint32_t RESERVED4[26];
+ __IOM uint32_t PUBLISH_COMPARE[6]; /*!< (@ 0x000001C0) Description collection: Publish configuration
+ for event COMPARE[n] */
+ __IM uint32_t RESERVED5[10];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED6[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED7[126];
+ __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */
+ __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */
+ __IM uint32_t RESERVED8;
+ __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */
+ __IOM uint32_t ONESHOTEN[6]; /*!< (@ 0x00000514) Description collection: Enable one-shot operation
+ for Capture/Compare channel n */
+ __IM uint32_t RESERVED9[5];
+ __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register
+ n */
+} NRF_TIMER_Type; /*!< Size = 1368 (0x558) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ RTC0_NS ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Real-time counter 0 (RTC0_NS)
+ */
+
+typedef struct { /*!< (@ 0x40014000) RTC0_NS Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC counter */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC counter */
+ __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC counter */
+ __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set counter to 0xFFFFF0 */
+ __IM uint32_t RESERVED[28];
+ __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */
+ __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */
+ __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x00000088) Subscribe configuration for task CLEAR */
+ __IOM uint32_t SUBSCRIBE_TRIGOVRFLW; /*!< (@ 0x0000008C) Subscribe configuration for task TRIGOVRFLW */
+ __IM uint32_t RESERVED1[28];
+ __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on counter increment */
+ __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on counter overflow */
+ __IM uint32_t RESERVED2[14];
+ __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n]
+ match */
+ __IM uint32_t RESERVED3[12];
+ __IOM uint32_t PUBLISH_TICK; /*!< (@ 0x00000180) Publish configuration for event TICK */
+ __IOM uint32_t PUBLISH_OVRFLW; /*!< (@ 0x00000184) Publish configuration for event OVRFLW */
+ __IM uint32_t RESERVED4[14];
+ __IOM uint32_t PUBLISH_COMPARE[4]; /*!< (@ 0x000001C0) Description collection: Publish configuration
+ for event COMPARE[n] */
+ __IM uint32_t RESERVED5[77];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED6[13];
+ __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */
+ __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */
+ __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */
+ __IM uint32_t RESERVED7[110];
+ __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current counter value */
+ __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12-bit prescaler for counter frequency (32768/(PRESCALER+1)).
+ Must be written when RTC is stopped. */
+ __IM uint32_t RESERVED8[13];
+ __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */
+} NRF_RTC_Type; /*!< Size = 1360 (0x550) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DPPIC_NS ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Distributed programmable peripheral interconnect controller 0 (DPPIC_NS)
+ */
+
+typedef struct { /*!< (@ 0x40017000) DPPIC_NS Structure */
+ __OM DPPIC_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */
+ __IM uint32_t RESERVED[20];
+ __IOM DPPIC_SUBSCRIBE_CHG_Type SUBSCRIBE_CHG[6];/*!< (@ 0x00000080) Subscribe configuration for tasks */
+ __IM uint32_t RESERVED1[276];
+ __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */
+ __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */
+ __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */
+ __IM uint32_t RESERVED2[189];
+ __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n Note:
+ Writes to this register are ignored if either
+ SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS
+ is enabled */
+} NRF_DPPIC_Type; /*!< Size = 2072 (0x818) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ WDT_NS ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Watchdog Timer 0 (WDT_NS)
+ */
+
+typedef struct { /*!< (@ 0x40018000) WDT_NS Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */
+ __IM uint32_t RESERVED[31];
+ __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */
+ __IM uint32_t RESERVED1[31];
+ __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */
+ __IM uint32_t RESERVED2[31];
+ __IOM uint32_t PUBLISH_TIMEOUT; /*!< (@ 0x00000180) Publish configuration for event TIMEOUT */
+ __IM uint32_t RESERVED3[96];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED4[61];
+ __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */
+ __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */
+ __IM uint32_t RESERVED5[63];
+ __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */
+ __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */
+ __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */
+ __IM uint32_t RESERVED6[60];
+ __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */
+} NRF_WDT_Type; /*!< Size = 1568 (0x620) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ EGU0_NS ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Event generator unit 0 (EGU0_NS)
+ */
+
+typedef struct { /*!< (@ 0x4001B000) EGU0_NS Structure */
+ __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering
+ the corresponding TRIGGERED[n] event */
+ __IM uint32_t RESERVED[16];
+ __IOM uint32_t SUBSCRIBE_TRIGGER[16]; /*!< (@ 0x00000080) Description collection: Subscribe configuration
+ for task TRIGGER[n] */
+ __IM uint32_t RESERVED1[16];
+ __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated
+ by triggering the corresponding TRIGGER[n]
+ task */
+ __IM uint32_t RESERVED2[16];
+ __IOM uint32_t PUBLISH_TRIGGERED[16]; /*!< (@ 0x00000180) Description collection: Publish configuration
+ for event TRIGGERED[n] */
+ __IM uint32_t RESERVED3[80];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+} NRF_EGU_Type; /*!< Size = 780 (0x30c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ PWM0_NS ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Pulse width modulation unit 0 (PWM0_NS)
+ */
+
+typedef struct { /*!< (@ 0x40021000) PWM0_NS Structure */
+ __IM uint32_t RESERVED;
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at
+ the end of current PWM period, and stops
+ sequence playback */
+ __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection: Loads the first PWM value
+ on all enabled channels from sequence n,
+ and starts playing that sequence at the
+ rate defined in SEQ[n]REFRESH and/or DECODER.MODE.
+ Causes PWM generation to start if not running. */
+ __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on
+ all enabled channels if DECODER.MODE=NextStep.
+ Does not cause PWM generation to start if
+ not running. */
+ __IM uint32_t RESERVED1[28];
+ __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */
+ __IOM uint32_t SUBSCRIBE_SEQSTART[2]; /*!< (@ 0x00000088) Description collection: Subscribe configuration
+ for task SEQSTART[n] */
+ __IOM uint32_t SUBSCRIBE_NEXTSTEP; /*!< (@ 0x00000090) Subscribe configuration for task NEXTSTEP */
+ __IM uint32_t RESERVED2[28];
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses
+ are no longer generated */
+ __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection: First PWM period started
+ on sequence n */
+ __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection: Emitted at end of every
+ sequence n, when last value from RAM has
+ been applied to wave counter */
+ __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */
+ __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount
+ of times defined in LOOP.CNT */
+ __IM uint32_t RESERVED3[25];
+ __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */
+ __IOM uint32_t PUBLISH_SEQSTARTED[2]; /*!< (@ 0x00000188) Description collection: Publish configuration
+ for event SEQSTARTED[n] */
+ __IOM uint32_t PUBLISH_SEQEND[2]; /*!< (@ 0x00000190) Description collection: Publish configuration
+ for event SEQEND[n] */
+ __IOM uint32_t PUBLISH_PWMPERIODEND; /*!< (@ 0x00000198) Publish configuration for event PWMPERIODEND */
+ __IOM uint32_t PUBLISH_LOOPSDONE; /*!< (@ 0x0000019C) Publish configuration for event LOOPSDONE */
+ __IM uint32_t RESERVED4[24];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED5[63];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED6[125];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */
+ __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */
+ __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter
+ counts */
+ __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */
+ __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */
+ __IOM uint32_t LOOP; /*!< (@ 0x00000514) Number of playbacks of a loop */
+ __IM uint32_t RESERVED7[2];
+ __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */
+ __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */
+} NRF_PWM_Type; /*!< Size = 1392 (0x570) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ PDM_NS ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Pulse Density Modulation (Digital Microphone) Interface 0 (PDM_NS)
+ */
+
+typedef struct { /*!< (@ 0x40026000) PDM_NS Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */
+ __IM uint32_t RESERVED[30];
+ __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */
+ __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */
+ __IM uint32_t RESERVED1[30];
+ __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */
+ __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified
+ by SAMPLE.MAXCNT (or the last sample after
+ a STOP task has been received) to Data RAM */
+ __IM uint32_t RESERVED2[29];
+ __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x00000180) Publish configuration for event STARTED */
+ __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */
+ __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000188) Publish configuration for event END */
+ __IM uint32_t RESERVED3[93];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED4[125];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */
+ __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */
+ __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones'
+ signals */
+ __IM uint32_t RESERVED5[3];
+ __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */
+ __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */
+ __IOM uint32_t RATIO; /*!< (@ 0x00000520) Selects the ratio between PDM_CLK and output
+ sample rate. Change PDMCLKCTRL accordingly. */
+ __IM uint32_t RESERVED6[7];
+ __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */
+ __IM uint32_t RESERVED7[6];
+ __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */
+} NRF_PDM_Type; /*!< Size = 1384 (0x568) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ I2S_NS ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Inter-IC Sound 0 (I2S_NS)
+ */
+
+typedef struct { /*!< (@ 0x40028000) I2S_NS Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK
+ generator when this is enabled. */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator.
+ Triggering this task will cause the STOPPED
+ event to be generated. */
+ __IM uint32_t RESERVED[30];
+ __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */
+ __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */
+ __IM uint32_t RESERVED1[31];
+ __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal
+ double-buffers. When the I2S module is started
+ and RX is enabled, this event will be generated
+ for every RXTXD.MAXCNT words that are received
+ on the SDIN pin. */
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */
+ __IM uint32_t RESERVED2[2];
+ __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal
+ double-buffers. When the I2S module is started
+ and TX is enabled, this event will be generated
+ for every RXTXD.MAXCNT words that are sent
+ on the SDOUT pin. */
+ __IM uint32_t RESERVED3[27];
+ __IOM uint32_t PUBLISH_RXPTRUPD; /*!< (@ 0x00000184) Publish configuration for event RXPTRUPD */
+ __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000188) Publish configuration for event STOPPED */
+ __IM uint32_t RESERVED4[2];
+ __IOM uint32_t PUBLISH_TXPTRUPD; /*!< (@ 0x00000194) Publish configuration for event TXPTRUPD */
+ __IM uint32_t RESERVED5[90];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED6[125];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module. */
+ __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */
+ __IM uint32_t RESERVED7[3];
+ __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */
+ __IM uint32_t RESERVED8;
+ __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */
+ __IM uint32_t RESERVED9[3];
+ __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */
+ __IM uint32_t RESERVED10[3];
+ __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */
+} NRF_I2S_Type; /*!< Size = 1396 (0x574) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ IPC_NS ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Interprocessor communication 0 (IPC_NS)
+ */
+
+typedef struct { /*!< (@ 0x4002A000) IPC_NS Structure */
+ __OM uint32_t TASKS_SEND[8]; /*!< (@ 0x00000000) Description collection: Trigger events on IPC
+ channel enabled in SEND_CNF[n] */
+ __IM uint32_t RESERVED[24];
+ __IOM uint32_t SUBSCRIBE_SEND[8]; /*!< (@ 0x00000080) Description collection: Subscribe configuration
+ for task SEND[n] */
+ __IM uint32_t RESERVED1[24];
+ __IOM uint32_t EVENTS_RECEIVE[8]; /*!< (@ 0x00000100) Description collection: Event received on one
+ or more of the enabled IPC channels in RECEIVE_CNF[n] */
+ __IM uint32_t RESERVED2[24];
+ __IOM uint32_t PUBLISH_RECEIVE[8]; /*!< (@ 0x00000180) Description collection: Publish configuration
+ for event RECEIVE[n] */
+ __IM uint32_t RESERVED3[88];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */
+ __IM uint32_t RESERVED4[128];
+ __IOM uint32_t SEND_CNF[8]; /*!< (@ 0x00000510) Description collection: Send event configuration
+ for TASKS_SEND[n] */
+ __IM uint32_t RESERVED5[24];
+ __IOM uint32_t RECEIVE_CNF[8]; /*!< (@ 0x00000590) Description collection: Receive event configuration
+ for EVENTS_RECEIVE[n] */
+ __IM uint32_t RESERVED6[24];
+ __IOM uint32_t GPMEM[4]; /*!< (@ 0x00000610) Description collection: General purpose memory */
+} NRF_IPC_Type; /*!< Size = 1568 (0x620) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ FPU_NS ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief FPU 0 (FPU_NS)
+ */
+
+typedef struct { /*!< (@ 0x4002C000) FPU_NS Structure */
+ __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */
+} NRF_FPU_Type; /*!< Size = 4 (0x4) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ APPROTECT_NS ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Access Port Protection 0 (APPROTECT_NS)
+ */
+
+typedef struct { /*!< (@ 0x40039000) APPROTECT_NS Structure */
+ __IM uint32_t RESERVED[896];
+ __IOM APPROTECT_SECUREAPPROTECT_Type SECUREAPPROTECT;/*!< (@ 0x00000E00) Unspecified */
+ __IM uint32_t RESERVED1[2];
+ __IOM APPROTECT_APPROTECT_Type APPROTECT; /*!< (@ 0x00000E10) Unspecified */
+} NRF_APPROTECT_Type; /*!< Size = 3608 (0xe18) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ KMU_NS ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Key management unit 0 (KMU_NS)
+ */
+
+typedef struct { /*!< (@ 0x40039000) KMU_NS Structure */
+ __OM uint32_t TASKS_PUSH_KEYSLOT; /*!< (@ 0x00000000) Push a key slot over secure APB */
+ __IM uint32_t RESERVED[63];
+ __IOM uint32_t EVENTS_KEYSLOT_PUSHED; /*!< (@ 0x00000100) Key slot successfully pushed over secure APB */
+ __IOM uint32_t EVENTS_KEYSLOT_REVOKED; /*!< (@ 0x00000104) Key slot has been revoked and cannot be tasked
+ for selection */
+ __IOM uint32_t EVENTS_KEYSLOT_ERROR; /*!< (@ 0x00000108) No key slot selected, no destination address
+ defined, or error during push operation */
+ __IM uint32_t RESERVED1[125];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */
+ __IM uint32_t RESERVED2[63];
+ __IM uint32_t STATUS; /*!< (@ 0x0000040C) Status bits for KMU operation */
+ __IM uint32_t RESERVED3[60];
+ __IOM uint32_t SELECTKEYSLOT; /*!< (@ 0x00000500) Select key slot to be read over AHB or pushed
+ over secure APB when TASKS_PUSH_KEYSLOT
+ is started */
+} NRF_KMU_Type; /*!< Size = 1284 (0x504) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ NVMC_NS ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Non-volatile memory controller 0 (NVMC_NS)
+ */
+
+typedef struct { /*!< (@ 0x40039000) NVMC_NS Structure */
+ __IM uint32_t RESERVED[256];
+ __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */
+ __IM uint32_t RESERVED1;
+ __IM uint32_t READYNEXT; /*!< (@ 0x00000408) Ready flag */
+ __IM uint32_t RESERVED2[62];
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */
+ __IM uint32_t RESERVED3;
+ __OM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */
+ __IM uint32_t RESERVED4[3];
+ __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */
+ __IM uint32_t RESERVED5[8];
+ __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-code cache configuration register */
+ __IM uint32_t RESERVED6;
+ __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-code cache hit counter */
+ __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-code cache miss counter */
+ __IM uint32_t RESERVED7[13];
+ __IOM uint32_t CONFIGNS; /*!< (@ 0x00000584) Unspecified */
+ __OM uint32_t WRITEUICRNS; /*!< (@ 0x00000588) Non-secure APPROTECT enable register */
+} NRF_NVMC_Type; /*!< Size = 1420 (0x58c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ VMC_NS ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Volatile Memory controller 0 (VMC_NS)
+ */
+
+typedef struct { /*!< (@ 0x4003A000) VMC_NS Structure */
+ __IM uint32_t RESERVED[384];
+ __IOM VMC_RAM_Type RAM[8]; /*!< (@ 0x00000600) Unspecified */
+} NRF_VMC_Type; /*!< Size = 1664 (0x680) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CC_HOST_RGF_S ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CRYPTOCELL HOST_RGF interface (CC_HOST_RGF_S)
+ */
+
+typedef struct { /*!< (@ 0x50840000) CC_HOST_RGF_S Structure */
+ __IM uint32_t RESERVED[1678];
+ __IOM uint32_t HOST_CRYPTOKEY_SEL; /*!< (@ 0x00001A38) AES hardware key select */
+ __IM uint32_t RESERVED1[4];
+ __IOM uint32_t HOST_IOT_KPRTL_LOCK; /*!< (@ 0x00001A4C) This write-once register is the K_PRTL lock register.
+ When this register is set, K_PRTL cannot
+ be used and a zeroed key will be used instead.
+ The value of this register is saved in the
+ CRYPTOCELL AO power domain. */
+ __IOM uint32_t HOST_IOT_KDR0; /*!< (@ 0x00001A50) This register holds bits 31:0 of K_DR. The value
+ of this register is saved in the CRYPTOCELL
+ AO power domain. Reading from this address
+ returns the K_DR valid status indicating
+ if K_DR is successfully retained. */
+ __OM uint32_t HOST_IOT_KDR1; /*!< (@ 0x00001A54) This register holds bits 63:32 of K_DR. The value
+ of this register is saved in the CRYPTOCELL
+ AO power domain. */
+ __OM uint32_t HOST_IOT_KDR2; /*!< (@ 0x00001A58) This register holds bits 95:64 of K_DR. The value
+ of this register is saved in the CRYPTOCELL
+ AO power domain. */
+ __OM uint32_t HOST_IOT_KDR3; /*!< (@ 0x00001A5C) This register holds bits 127:96 of K_DR. The
+ value of this register is saved in the CRYPTOCELL
+ AO power domain. */
+ __IOM uint32_t HOST_IOT_LCS; /*!< (@ 0x00001A60) Controls lifecycle state (LCS) for CRYPTOCELL
+ subsystem */
+} NRF_CC_HOST_RGF_Type; /*!< Size = 6756 (0x1a64) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CRYPTOCELL_S ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief ARM TrustZone CryptoCell register interface (CRYPTOCELL_S)
+ */
+
+typedef struct { /*!< (@ 0x50840000) CRYPTOCELL_S Structure */
+ __IM uint32_t RESERVED[320];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable CRYPTOCELL subsystem */
+} NRF_CRYPTOCELL_Type; /*!< Size = 1284 (0x504) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ P0_NS ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief GPIO Port 0 (P0_NS)
+ */
+
+typedef struct { /*!< (@ 0x40842500) P0_NS Structure */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t OUT; /*!< (@ 0x00000004) Write GPIO port */
+ __IOM uint32_t OUTSET; /*!< (@ 0x00000008) Set individual bits in GPIO port */
+ __IOM uint32_t OUTCLR; /*!< (@ 0x0000000C) Clear individual bits in GPIO port */
+ __IM uint32_t IN; /*!< (@ 0x00000010) Read GPIO port */
+ __IOM uint32_t DIR; /*!< (@ 0x00000014) Direction of GPIO pins */
+ __IOM uint32_t DIRSET; /*!< (@ 0x00000018) DIR set register */
+ __IOM uint32_t DIRCLR; /*!< (@ 0x0000001C) DIR clear register */
+ __IOM uint32_t LATCH; /*!< (@ 0x00000020) Latch register indicating what GPIO pins that
+ have met the criteria set in the PIN_CNF[n].SENSE
+ registers */
+ __IOM uint32_t DETECTMODE; /*!< (@ 0x00000024) Select between default DETECT signal behavior
+ and LDETECT mode (For non-secure pin only) */
+ __IOM uint32_t DETECTMODE_SEC; /*!< (@ 0x00000028) Select between default DETECT signal behavior
+ and LDETECT mode (For secure pin only) */
+ __IM uint32_t RESERVED1[117];
+ __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000200) Description collection: Configuration of GPIO
+ pins */
+} NRF_GPIO_Type; /*!< Size = 640 (0x280) */
+
+
+/** @} */ /* End of group Device_Peripheral_peripherals */
+
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Peripheral Address Map ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_peripheralAddr
+ * @{
+ */
+
+#define NRF_FICR_S_BASE 0x00FF0000UL
+#define NRF_UICR_S_BASE 0x00FF8000UL
+#define NRF_TAD_S_BASE 0xE0080000UL
+#define NRF_SPU_S_BASE 0x50003000UL
+#define NRF_REGULATORS_NS_BASE 0x40004000UL
+#define NRF_REGULATORS_S_BASE 0x50004000UL
+#define NRF_CLOCK_NS_BASE 0x40005000UL
+#define NRF_POWER_NS_BASE 0x40005000UL
+#define NRF_CLOCK_S_BASE 0x50005000UL
+#define NRF_POWER_S_BASE 0x50005000UL
+#define NRF_CTRL_AP_PERI_S_BASE 0x50006000UL
+#define NRF_SPIM0_NS_BASE 0x40008000UL
+#define NRF_SPIS0_NS_BASE 0x40008000UL
+#define NRF_TWIM0_NS_BASE 0x40008000UL
+#define NRF_TWIS0_NS_BASE 0x40008000UL
+#define NRF_UARTE0_NS_BASE 0x40008000UL
+#define NRF_SPIM0_S_BASE 0x50008000UL
+#define NRF_SPIS0_S_BASE 0x50008000UL
+#define NRF_TWIM0_S_BASE 0x50008000UL
+#define NRF_TWIS0_S_BASE 0x50008000UL
+#define NRF_UARTE0_S_BASE 0x50008000UL
+#define NRF_SPIM1_NS_BASE 0x40009000UL
+#define NRF_SPIS1_NS_BASE 0x40009000UL
+#define NRF_TWIM1_NS_BASE 0x40009000UL
+#define NRF_TWIS1_NS_BASE 0x40009000UL
+#define NRF_UARTE1_NS_BASE 0x40009000UL
+#define NRF_SPIM1_S_BASE 0x50009000UL
+#define NRF_SPIS1_S_BASE 0x50009000UL
+#define NRF_TWIM1_S_BASE 0x50009000UL
+#define NRF_TWIS1_S_BASE 0x50009000UL
+#define NRF_UARTE1_S_BASE 0x50009000UL
+#define NRF_SPIM2_NS_BASE 0x4000A000UL
+#define NRF_SPIS2_NS_BASE 0x4000A000UL
+#define NRF_TWIM2_NS_BASE 0x4000A000UL
+#define NRF_TWIS2_NS_BASE 0x4000A000UL
+#define NRF_UARTE2_NS_BASE 0x4000A000UL
+#define NRF_SPIM2_S_BASE 0x5000A000UL
+#define NRF_SPIS2_S_BASE 0x5000A000UL
+#define NRF_TWIM2_S_BASE 0x5000A000UL
+#define NRF_TWIS2_S_BASE 0x5000A000UL
+#define NRF_UARTE2_S_BASE 0x5000A000UL
+#define NRF_SPIM3_NS_BASE 0x4000B000UL
+#define NRF_SPIS3_NS_BASE 0x4000B000UL
+#define NRF_TWIM3_NS_BASE 0x4000B000UL
+#define NRF_TWIS3_NS_BASE 0x4000B000UL
+#define NRF_UARTE3_NS_BASE 0x4000B000UL
+#define NRF_SPIM3_S_BASE 0x5000B000UL
+#define NRF_SPIS3_S_BASE 0x5000B000UL
+#define NRF_TWIM3_S_BASE 0x5000B000UL
+#define NRF_TWIS3_S_BASE 0x5000B000UL
+#define NRF_UARTE3_S_BASE 0x5000B000UL
+#define NRF_GPIOTE0_S_BASE 0x5000D000UL
+#define NRF_SAADC_NS_BASE 0x4000E000UL
+#define NRF_SAADC_S_BASE 0x5000E000UL
+#define NRF_TIMER0_NS_BASE 0x4000F000UL
+#define NRF_TIMER0_S_BASE 0x5000F000UL
+#define NRF_TIMER1_NS_BASE 0x40010000UL
+#define NRF_TIMER1_S_BASE 0x50010000UL
+#define NRF_TIMER2_NS_BASE 0x40011000UL
+#define NRF_TIMER2_S_BASE 0x50011000UL
+#define NRF_RTC0_NS_BASE 0x40014000UL
+#define NRF_RTC0_S_BASE 0x50014000UL
+#define NRF_RTC1_NS_BASE 0x40015000UL
+#define NRF_RTC1_S_BASE 0x50015000UL
+#define NRF_DPPIC_NS_BASE 0x40017000UL
+#define NRF_DPPIC_S_BASE 0x50017000UL
+#define NRF_WDT_NS_BASE 0x40018000UL
+#define NRF_WDT_S_BASE 0x50018000UL
+#define NRF_EGU0_NS_BASE 0x4001B000UL
+#define NRF_EGU0_S_BASE 0x5001B000UL
+#define NRF_EGU1_NS_BASE 0x4001C000UL
+#define NRF_EGU1_S_BASE 0x5001C000UL
+#define NRF_EGU2_NS_BASE 0x4001D000UL
+#define NRF_EGU2_S_BASE 0x5001D000UL
+#define NRF_EGU3_NS_BASE 0x4001E000UL
+#define NRF_EGU3_S_BASE 0x5001E000UL
+#define NRF_EGU4_NS_BASE 0x4001F000UL
+#define NRF_EGU4_S_BASE 0x5001F000UL
+#define NRF_EGU5_NS_BASE 0x40020000UL
+#define NRF_EGU5_S_BASE 0x50020000UL
+#define NRF_PWM0_NS_BASE 0x40021000UL
+#define NRF_PWM0_S_BASE 0x50021000UL
+#define NRF_PWM1_NS_BASE 0x40022000UL
+#define NRF_PWM1_S_BASE 0x50022000UL
+#define NRF_PWM2_NS_BASE 0x40023000UL
+#define NRF_PWM2_S_BASE 0x50023000UL
+#define NRF_PWM3_NS_BASE 0x40024000UL
+#define NRF_PWM3_S_BASE 0x50024000UL
+#define NRF_PDM_NS_BASE 0x40026000UL
+#define NRF_PDM_S_BASE 0x50026000UL
+#define NRF_I2S_NS_BASE 0x40028000UL
+#define NRF_I2S_S_BASE 0x50028000UL
+#define NRF_IPC_NS_BASE 0x4002A000UL
+#define NRF_IPC_S_BASE 0x5002A000UL
+#define NRF_FPU_NS_BASE 0x4002C000UL
+#define NRF_FPU_S_BASE 0x5002C000UL
+#define NRF_GPIOTE1_NS_BASE 0x40031000UL
+#define NRF_APPROTECT_NS_BASE 0x40039000UL
+#define NRF_KMU_NS_BASE 0x40039000UL
+#define NRF_NVMC_NS_BASE 0x40039000UL
+#define NRF_APPROTECT_S_BASE 0x50039000UL
+#define NRF_KMU_S_BASE 0x50039000UL
+#define NRF_NVMC_S_BASE 0x50039000UL
+#define NRF_VMC_NS_BASE 0x4003A000UL
+#define NRF_VMC_S_BASE 0x5003A000UL
+#define NRF_CC_HOST_RGF_S_BASE 0x50840000UL
+#define NRF_CRYPTOCELL_S_BASE 0x50840000UL
+#define NRF_P0_NS_BASE 0x40842500UL
+#define NRF_P0_S_BASE 0x50842500UL
+
+/** @} */ /* End of group Device_Peripheral_peripheralAddr */
+
+
+/* =========================================================================================================================== */
+/* ================ Peripheral declaration ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_declaration
+ * @{
+ */
+
+#define NRF_FICR_S ((NRF_FICR_Type*) NRF_FICR_S_BASE)
+#define NRF_UICR_S ((NRF_UICR_Type*) NRF_UICR_S_BASE)
+#define NRF_TAD_S ((NRF_TAD_Type*) NRF_TAD_S_BASE)
+#define NRF_SPU_S ((NRF_SPU_Type*) NRF_SPU_S_BASE)
+#define NRF_REGULATORS_NS ((NRF_REGULATORS_Type*) NRF_REGULATORS_NS_BASE)
+#define NRF_REGULATORS_S ((NRF_REGULATORS_Type*) NRF_REGULATORS_S_BASE)
+#define NRF_CLOCK_NS ((NRF_CLOCK_Type*) NRF_CLOCK_NS_BASE)
+#define NRF_POWER_NS ((NRF_POWER_Type*) NRF_POWER_NS_BASE)
+#define NRF_CLOCK_S ((NRF_CLOCK_Type*) NRF_CLOCK_S_BASE)
+#define NRF_POWER_S ((NRF_POWER_Type*) NRF_POWER_S_BASE)
+#define NRF_CTRL_AP_PERI_S ((NRF_CTRLAPPERI_Type*) NRF_CTRL_AP_PERI_S_BASE)
+#define NRF_SPIM0_NS ((NRF_SPIM_Type*) NRF_SPIM0_NS_BASE)
+#define NRF_SPIS0_NS ((NRF_SPIS_Type*) NRF_SPIS0_NS_BASE)
+#define NRF_TWIM0_NS ((NRF_TWIM_Type*) NRF_TWIM0_NS_BASE)
+#define NRF_TWIS0_NS ((NRF_TWIS_Type*) NRF_TWIS0_NS_BASE)
+#define NRF_UARTE0_NS ((NRF_UARTE_Type*) NRF_UARTE0_NS_BASE)
+#define NRF_SPIM0_S ((NRF_SPIM_Type*) NRF_SPIM0_S_BASE)
+#define NRF_SPIS0_S ((NRF_SPIS_Type*) NRF_SPIS0_S_BASE)
+#define NRF_TWIM0_S ((NRF_TWIM_Type*) NRF_TWIM0_S_BASE)
+#define NRF_TWIS0_S ((NRF_TWIS_Type*) NRF_TWIS0_S_BASE)
+#define NRF_UARTE0_S ((NRF_UARTE_Type*) NRF_UARTE0_S_BASE)
+#define NRF_SPIM1_NS ((NRF_SPIM_Type*) NRF_SPIM1_NS_BASE)
+#define NRF_SPIS1_NS ((NRF_SPIS_Type*) NRF_SPIS1_NS_BASE)
+#define NRF_TWIM1_NS ((NRF_TWIM_Type*) NRF_TWIM1_NS_BASE)
+#define NRF_TWIS1_NS ((NRF_TWIS_Type*) NRF_TWIS1_NS_BASE)
+#define NRF_UARTE1_NS ((NRF_UARTE_Type*) NRF_UARTE1_NS_BASE)
+#define NRF_SPIM1_S ((NRF_SPIM_Type*) NRF_SPIM1_S_BASE)
+#define NRF_SPIS1_S ((NRF_SPIS_Type*) NRF_SPIS1_S_BASE)
+#define NRF_TWIM1_S ((NRF_TWIM_Type*) NRF_TWIM1_S_BASE)
+#define NRF_TWIS1_S ((NRF_TWIS_Type*) NRF_TWIS1_S_BASE)
+#define NRF_UARTE1_S ((NRF_UARTE_Type*) NRF_UARTE1_S_BASE)
+#define NRF_SPIM2_NS ((NRF_SPIM_Type*) NRF_SPIM2_NS_BASE)
+#define NRF_SPIS2_NS ((NRF_SPIS_Type*) NRF_SPIS2_NS_BASE)
+#define NRF_TWIM2_NS ((NRF_TWIM_Type*) NRF_TWIM2_NS_BASE)
+#define NRF_TWIS2_NS ((NRF_TWIS_Type*) NRF_TWIS2_NS_BASE)
+#define NRF_UARTE2_NS ((NRF_UARTE_Type*) NRF_UARTE2_NS_BASE)
+#define NRF_SPIM2_S ((NRF_SPIM_Type*) NRF_SPIM2_S_BASE)
+#define NRF_SPIS2_S ((NRF_SPIS_Type*) NRF_SPIS2_S_BASE)
+#define NRF_TWIM2_S ((NRF_TWIM_Type*) NRF_TWIM2_S_BASE)
+#define NRF_TWIS2_S ((NRF_TWIS_Type*) NRF_TWIS2_S_BASE)
+#define NRF_UARTE2_S ((NRF_UARTE_Type*) NRF_UARTE2_S_BASE)
+#define NRF_SPIM3_NS ((NRF_SPIM_Type*) NRF_SPIM3_NS_BASE)
+#define NRF_SPIS3_NS ((NRF_SPIS_Type*) NRF_SPIS3_NS_BASE)
+#define NRF_TWIM3_NS ((NRF_TWIM_Type*) NRF_TWIM3_NS_BASE)
+#define NRF_TWIS3_NS ((NRF_TWIS_Type*) NRF_TWIS3_NS_BASE)
+#define NRF_UARTE3_NS ((NRF_UARTE_Type*) NRF_UARTE3_NS_BASE)
+#define NRF_SPIM3_S ((NRF_SPIM_Type*) NRF_SPIM3_S_BASE)
+#define NRF_SPIS3_S ((NRF_SPIS_Type*) NRF_SPIS3_S_BASE)
+#define NRF_TWIM3_S ((NRF_TWIM_Type*) NRF_TWIM3_S_BASE)
+#define NRF_TWIS3_S ((NRF_TWIS_Type*) NRF_TWIS3_S_BASE)
+#define NRF_UARTE3_S ((NRF_UARTE_Type*) NRF_UARTE3_S_BASE)
+#define NRF_GPIOTE0_S ((NRF_GPIOTE_Type*) NRF_GPIOTE0_S_BASE)
+#define NRF_SAADC_NS ((NRF_SAADC_Type*) NRF_SAADC_NS_BASE)
+#define NRF_SAADC_S ((NRF_SAADC_Type*) NRF_SAADC_S_BASE)
+#define NRF_TIMER0_NS ((NRF_TIMER_Type*) NRF_TIMER0_NS_BASE)
+#define NRF_TIMER0_S ((NRF_TIMER_Type*) NRF_TIMER0_S_BASE)
+#define NRF_TIMER1_NS ((NRF_TIMER_Type*) NRF_TIMER1_NS_BASE)
+#define NRF_TIMER1_S ((NRF_TIMER_Type*) NRF_TIMER1_S_BASE)
+#define NRF_TIMER2_NS ((NRF_TIMER_Type*) NRF_TIMER2_NS_BASE)
+#define NRF_TIMER2_S ((NRF_TIMER_Type*) NRF_TIMER2_S_BASE)
+#define NRF_RTC0_NS ((NRF_RTC_Type*) NRF_RTC0_NS_BASE)
+#define NRF_RTC0_S ((NRF_RTC_Type*) NRF_RTC0_S_BASE)
+#define NRF_RTC1_NS ((NRF_RTC_Type*) NRF_RTC1_NS_BASE)
+#define NRF_RTC1_S ((NRF_RTC_Type*) NRF_RTC1_S_BASE)
+#define NRF_DPPIC_NS ((NRF_DPPIC_Type*) NRF_DPPIC_NS_BASE)
+#define NRF_DPPIC_S ((NRF_DPPIC_Type*) NRF_DPPIC_S_BASE)
+#define NRF_WDT_NS ((NRF_WDT_Type*) NRF_WDT_NS_BASE)
+#define NRF_WDT_S ((NRF_WDT_Type*) NRF_WDT_S_BASE)
+#define NRF_EGU0_NS ((NRF_EGU_Type*) NRF_EGU0_NS_BASE)
+#define NRF_EGU0_S ((NRF_EGU_Type*) NRF_EGU0_S_BASE)
+#define NRF_EGU1_NS ((NRF_EGU_Type*) NRF_EGU1_NS_BASE)
+#define NRF_EGU1_S ((NRF_EGU_Type*) NRF_EGU1_S_BASE)
+#define NRF_EGU2_NS ((NRF_EGU_Type*) NRF_EGU2_NS_BASE)
+#define NRF_EGU2_S ((NRF_EGU_Type*) NRF_EGU2_S_BASE)
+#define NRF_EGU3_NS ((NRF_EGU_Type*) NRF_EGU3_NS_BASE)
+#define NRF_EGU3_S ((NRF_EGU_Type*) NRF_EGU3_S_BASE)
+#define NRF_EGU4_NS ((NRF_EGU_Type*) NRF_EGU4_NS_BASE)
+#define NRF_EGU4_S ((NRF_EGU_Type*) NRF_EGU4_S_BASE)
+#define NRF_EGU5_NS ((NRF_EGU_Type*) NRF_EGU5_NS_BASE)
+#define NRF_EGU5_S ((NRF_EGU_Type*) NRF_EGU5_S_BASE)
+#define NRF_PWM0_NS ((NRF_PWM_Type*) NRF_PWM0_NS_BASE)
+#define NRF_PWM0_S ((NRF_PWM_Type*) NRF_PWM0_S_BASE)
+#define NRF_PWM1_NS ((NRF_PWM_Type*) NRF_PWM1_NS_BASE)
+#define NRF_PWM1_S ((NRF_PWM_Type*) NRF_PWM1_S_BASE)
+#define NRF_PWM2_NS ((NRF_PWM_Type*) NRF_PWM2_NS_BASE)
+#define NRF_PWM2_S ((NRF_PWM_Type*) NRF_PWM2_S_BASE)
+#define NRF_PWM3_NS ((NRF_PWM_Type*) NRF_PWM3_NS_BASE)
+#define NRF_PWM3_S ((NRF_PWM_Type*) NRF_PWM3_S_BASE)
+#define NRF_PDM_NS ((NRF_PDM_Type*) NRF_PDM_NS_BASE)
+#define NRF_PDM_S ((NRF_PDM_Type*) NRF_PDM_S_BASE)
+#define NRF_I2S_NS ((NRF_I2S_Type*) NRF_I2S_NS_BASE)
+#define NRF_I2S_S ((NRF_I2S_Type*) NRF_I2S_S_BASE)
+#define NRF_IPC_NS ((NRF_IPC_Type*) NRF_IPC_NS_BASE)
+#define NRF_IPC_S ((NRF_IPC_Type*) NRF_IPC_S_BASE)
+#define NRF_FPU_NS ((NRF_FPU_Type*) NRF_FPU_NS_BASE)
+#define NRF_FPU_S ((NRF_FPU_Type*) NRF_FPU_S_BASE)
+#define NRF_GPIOTE1_NS ((NRF_GPIOTE_Type*) NRF_GPIOTE1_NS_BASE)
+#define NRF_APPROTECT_NS ((NRF_APPROTECT_Type*) NRF_APPROTECT_NS_BASE)
+#define NRF_KMU_NS ((NRF_KMU_Type*) NRF_KMU_NS_BASE)
+#define NRF_NVMC_NS ((NRF_NVMC_Type*) NRF_NVMC_NS_BASE)
+#define NRF_APPROTECT_S ((NRF_APPROTECT_Type*) NRF_APPROTECT_S_BASE)
+#define NRF_KMU_S ((NRF_KMU_Type*) NRF_KMU_S_BASE)
+#define NRF_NVMC_S ((NRF_NVMC_Type*) NRF_NVMC_S_BASE)
+#define NRF_VMC_NS ((NRF_VMC_Type*) NRF_VMC_NS_BASE)
+#define NRF_VMC_S ((NRF_VMC_Type*) NRF_VMC_S_BASE)
+#define NRF_CC_HOST_RGF_S ((NRF_CC_HOST_RGF_Type*) NRF_CC_HOST_RGF_S_BASE)
+#define NRF_CRYPTOCELL_S ((NRF_CRYPTOCELL_Type*) NRF_CRYPTOCELL_S_BASE)
+#define NRF_P0_NS ((NRF_GPIO_Type*) NRF_P0_NS_BASE)
+#define NRF_P0_S ((NRF_GPIO_Type*) NRF_P0_S_BASE)
+
+/** @} */ /* End of group Device_Peripheral_declaration */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NRF9120_H */
+
+
+/** @} */ /* End of group nrf9120 */
+
+/** @} */ /* End of group Nordic Semiconductor */
diff --git a/mcu/nrf/common/vendor/mdk/nrf9120_bitfields.h b/mcu/nrf/common/vendor/mdk/nrf9120_bitfields.h
new file mode 100644
index 00000000..2a1b529f
--- /dev/null
+++ b/mcu/nrf/common/vendor/mdk/nrf9120_bitfields.h
@@ -0,0 +1,11195 @@
+/*
+
+Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
+
+SPDX-License-Identifier: BSD-3-Clause
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from this
+ software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef __NRF9120_BITS_H
+#define __NRF9120_BITS_H
+
+/*lint ++flb "Enter library region" */
+
+/* Peripheral: APPROTECT */
+/* Description: Access Port Protection 0 */
+
+/* Register: APPROTECT_SECUREAPPROTECT_DISABLE */
+/* Description: Software disable SECUREAPPROTECT mechanism */
+
+/* Bits 7..0 : Software disable SECUREAPPROTECT mechanism */
+#define APPROTECT_SECUREAPPROTECT_DISABLE_DISABLE_Pos (0UL) /*!< Position of DISABLE field. */
+#define APPROTECT_SECUREAPPROTECT_DISABLE_DISABLE_Msk (0xFFUL << APPROTECT_SECUREAPPROTECT_DISABLE_DISABLE_Pos) /*!< Bit mask of DISABLE field. */
+#define APPROTECT_SECUREAPPROTECT_DISABLE_DISABLE_SwUnprotected (0x5AUL) /*!< Software disable SECUREAPPROTECT mechanism */
+
+/* Register: APPROTECT_SECUREAPPROTECT_FORCEPROTECT */
+/* Description: Software force SECUREAPPROTECT mechanism */
+
+/* Bit 9 : Write 0x1 to force enable SECUREAPPROTECT mechanism, which will remain set until the next reset */
+#define APPROTECT_SECUREAPPROTECT_FORCEPROTECT_FORCEPROTECT_Pos (9UL) /*!< Position of FORCEPROTECT field. */
+#define APPROTECT_SECUREAPPROTECT_FORCEPROTECT_FORCEPROTECT_Msk (0x1UL << APPROTECT_SECUREAPPROTECT_FORCEPROTECT_FORCEPROTECT_Pos) /*!< Bit mask of FORCEPROTECT field. */
+#define APPROTECT_SECUREAPPROTECT_FORCEPROTECT_FORCEPROTECT_Force (0x1UL) /*!< Software force enable SECUREAPPROTECT mechanism */
+
+/* Register: APPROTECT_APPROTECT_DISABLE */
+/* Description: Software disable APPROTECT mechanism */
+
+/* Bits 7..0 : Software disable APPROTECT mechanism */
+#define APPROTECT_APPROTECT_DISABLE_DISABLE_Pos (0UL) /*!< Position of DISABLE field. */
+#define APPROTECT_APPROTECT_DISABLE_DISABLE_Msk (0xFFUL << APPROTECT_APPROTECT_DISABLE_DISABLE_Pos) /*!< Bit mask of DISABLE field. */
+#define APPROTECT_APPROTECT_DISABLE_DISABLE_SwUnprotected (0x5AUL) /*!< Software disable APPROTECT mechanism */
+
+/* Register: APPROTECT_APPROTECT_FORCEPROTECT */
+/* Description: Software force APPROTECT mechanism */
+
+/* Bit 9 : Write 0x1 to force enable APPROTECT mechanism, which will remain set until the next reset */
+#define APPROTECT_APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos (9UL) /*!< Position of FORCEPROTECT field. */
+#define APPROTECT_APPROTECT_FORCEPROTECT_FORCEPROTECT_Msk (0x1UL << APPROTECT_APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos) /*!< Bit mask of FORCEPROTECT field. */
+#define APPROTECT_APPROTECT_FORCEPROTECT_FORCEPROTECT_Force (0x1UL) /*!< Software force enable APPROTECT mechanism */
+
+
+/* Peripheral: CC_HOST_RGF */
+/* Description: CRYPTOCELL HOST_RGF interface */
+
+/* Register: CC_HOST_RGF_HOST_CRYPTOKEY_SEL */
+/* Description: AES hardware key select */
+
+/* Bits 1..0 : Select the source of the HW key that is used by the AES engine */
+#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Pos (0UL) /*!< Position of HOST_CRYPTOKEY_SEL field. */
+#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Msk (0x3UL << CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Pos) /*!< Bit mask of HOST_CRYPTOKEY_SEL field. */
+#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_DR (0UL) /*!< Use device root key K_DR from CRYPTOCELL AO power domain */
+#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_PRTL (1UL) /*!< Use hard-coded RTL key K_PRTL */
+#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Session (2UL) /*!< Use provided session key */
+
+/* Register: CC_HOST_RGF_HOST_IOT_KPRTL_LOCK */
+/* Description: This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */
+
+/* Bit 0 : This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */
+#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos (0UL) /*!< Position of HOST_IOT_KPRTL_LOCK field. */
+#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos) /*!< Bit mask of HOST_IOT_KPRTL_LOCK field. */
+#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Disabled (0UL) /*!< K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL */
+#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Enabled (1UL) /*!< K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead. */
+
+/* Register: CC_HOST_RGF_HOST_IOT_KDR0 */
+/* Description: This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. */
+
+/* Bits 31..0 : Write: K_DR bits 31:0. Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain. Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain. */
+#define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos (0UL) /*!< Position of HOST_IOT_KDR0 field. */
+#define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos) /*!< Bit mask of HOST_IOT_KDR0 field. */
+
+/* Register: CC_HOST_RGF_HOST_IOT_KDR1 */
+/* Description: This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */
+
+/* Bits 31..0 : K_DR bits 63:32 */
+#define CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Pos (0UL) /*!< Position of HOST_IOT_KDR1 field. */
+#define CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Pos) /*!< Bit mask of HOST_IOT_KDR1 field. */
+
+/* Register: CC_HOST_RGF_HOST_IOT_KDR2 */
+/* Description: This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */
+
+/* Bits 31..0 : K_DR bits 95:64 */
+#define CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Pos (0UL) /*!< Position of HOST_IOT_KDR2 field. */
+#define CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Pos) /*!< Bit mask of HOST_IOT_KDR2 field. */
+
+/* Register: CC_HOST_RGF_HOST_IOT_KDR3 */
+/* Description: This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */
+
+/* Bits 31..0 : K_DR bits 127:96 */
+#define CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Pos (0UL) /*!< Position of HOST_IOT_KDR3 field. */
+#define CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Pos) /*!< Bit mask of HOST_IOT_KDR3 field. */
+
+/* Register: CC_HOST_RGF_HOST_IOT_LCS */
+/* Description: Controls lifecycle state (LCS) for CRYPTOCELL subsystem */
+
+/* Bit 8 : Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset. */
+#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos (8UL) /*!< Position of LCS_IS_VALID field. */
+#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos) /*!< Bit mask of LCS_IS_VALID field. */
+#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Invalid (0UL) /*!< Valid LCS not yet retained in the CRYPTOCELL AO power domain */
+#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Valid (1UL) /*!< Valid LCS successfully retained in the CRYPTOCELL AO power domain */
+
+/* Bits 2..0 : Lifecycle state value. This field is write-once per reset. */
+#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos (0UL) /*!< Position of LCS field. */
+#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Msk (0x7UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos) /*!< Bit mask of LCS field. */
+#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Debug (0UL) /*!< CC310 operates in debug mode */
+#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Secure (2UL) /*!< CC310 operates in secure mode */
+
+
+/* Peripheral: CLOCK */
+/* Description: Clock management 0 */
+
+/* Register: CLOCK_TASKS_HFCLKSTART */
+/* Description: Start HFCLK source */
+
+/* Bit 0 : Start HFCLK source */
+#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */
+#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */
+#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CLOCK_TASKS_HFCLKSTOP */
+/* Description: Stop HFCLK source */
+
+/* Bit 0 : Stop HFCLK source */
+#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */
+#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */
+#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CLOCK_TASKS_LFCLKSTART */
+/* Description: Start LFCLK source */
+
+/* Bit 0 : Start LFCLK source */
+#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */
+#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */
+#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CLOCK_TASKS_LFCLKSTOP */
+/* Description: Stop LFCLK source */
+
+/* Bit 0 : Stop LFCLK source */
+#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */
+#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */
+#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: CLOCK_SUBSCRIBE_HFCLKSTART */
+/* Description: Subscribe configuration for task HFCLKSTART */
+
+/* Bit 31 : */
+#define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos (31UL) /*!< Position of EN field. */
+#define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos) /*!< Bit mask of EN field. */
+#define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Disabled (0UL) /*!< Disable subscription */
+#define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task HFCLKSTART will subscribe to */
+#define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: CLOCK_SUBSCRIBE_HFCLKSTOP */
+/* Description: Subscribe configuration for task HFCLKSTOP */
+
+/* Bit 31 : */
+#define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos (31UL) /*!< Position of EN field. */
+#define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos) /*!< Bit mask of EN field. */
+#define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Disabled (0UL) /*!< Disable subscription */
+#define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task HFCLKSTOP will subscribe to */
+#define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: CLOCK_SUBSCRIBE_LFCLKSTART */
+/* Description: Subscribe configuration for task LFCLKSTART */
+
+/* Bit 31 : */
+#define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos (31UL) /*!< Position of EN field. */
+#define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos) /*!< Bit mask of EN field. */
+#define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Disabled (0UL) /*!< Disable subscription */
+#define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task LFCLKSTART will subscribe to */
+#define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: CLOCK_SUBSCRIBE_LFCLKSTOP */
+/* Description: Subscribe configuration for task LFCLKSTOP */
+
+/* Bit 31 : */
+#define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos (31UL) /*!< Position of EN field. */
+#define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos) /*!< Bit mask of EN field. */
+#define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Disabled (0UL) /*!< Disable subscription */
+#define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task LFCLKSTOP will subscribe to */
+#define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: CLOCK_EVENTS_HFCLKSTARTED */
+/* Description: HFCLK oscillator started */
+
+/* Bit 0 : HFCLK oscillator started */
+#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */
+#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */
+#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: CLOCK_EVENTS_LFCLKSTARTED */
+/* Description: LFCLK started */
+
+/* Bit 0 : LFCLK started */
+#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */
+#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */
+#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: CLOCK_PUBLISH_HFCLKSTARTED */
+/* Description: Publish configuration for event HFCLKSTARTED */
+
+/* Bit 31 : */
+#define CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
+#define CLOCK_PUBLISH_HFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos) /*!< Bit mask of EN field. */
+#define CLOCK_PUBLISH_HFCLKSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
+#define CLOCK_PUBLISH_HFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event HFCLKSTARTED will publish to */
+#define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: CLOCK_PUBLISH_LFCLKSTARTED */
+/* Description: Publish configuration for event LFCLKSTARTED */
+
+/* Bit 31 : */
+#define CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
+#define CLOCK_PUBLISH_LFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos) /*!< Bit mask of EN field. */
+#define CLOCK_PUBLISH_LFCLKSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
+#define CLOCK_PUBLISH_LFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event LFCLKSTARTED will publish to */
+#define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: CLOCK_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 1 : Enable or disable interrupt for event LFCLKSTARTED */
+#define CLOCK_INTEN_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
+#define CLOCK_INTEN_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
+#define CLOCK_INTEN_LFCLKSTARTED_Disabled (0UL) /*!< Disable */
+#define CLOCK_INTEN_LFCLKSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for event HFCLKSTARTED */
+#define CLOCK_INTEN_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
+#define CLOCK_INTEN_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
+#define CLOCK_INTEN_HFCLKSTARTED_Disabled (0UL) /*!< Disable */
+#define CLOCK_INTEN_HFCLKSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Register: CLOCK_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */
+#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */
+#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
+
+/* Register: CLOCK_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
+
+/* Register: CLOCK_INTPEND */
+/* Description: Pending interrupts */
+
+/* Bit 1 : Read pending status of interrupt for event LFCLKSTARTED */
+#define CLOCK_INTPEND_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
+#define CLOCK_INTPEND_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
+#define CLOCK_INTPEND_LFCLKSTARTED_NotPending (0UL) /*!< Read: Not pending */
+#define CLOCK_INTPEND_LFCLKSTARTED_Pending (1UL) /*!< Read: Pending */
+
+/* Bit 0 : Read pending status of interrupt for event HFCLKSTARTED */
+#define CLOCK_INTPEND_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
+#define CLOCK_INTPEND_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
+#define CLOCK_INTPEND_HFCLKSTARTED_NotPending (0UL) /*!< Read: Not pending */
+#define CLOCK_INTPEND_HFCLKSTARTED_Pending (1UL) /*!< Read: Pending */
+
+/* Register: CLOCK_HFCLKRUN */
+/* Description: Status indicating that HFCLKSTART task has been triggered */
+
+/* Bit 0 : HFCLKSTART task triggered or not */
+#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
+#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
+
+/* Register: CLOCK_HFCLKSTAT */
+/* Description: The register shows if HFXO has been requested by triggering HFCLKSTART task and if it has been started (STATE) */
+
+/* Bit 16 : HFCLK state */
+#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
+#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
+#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFXO has not been started or HFCLKSTOP task has been triggered */
+#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFXO has been started (HFCLKSTARTED event has been generated) */
+
+/* Bit 0 : Active clock source */
+#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_HFCLKSTAT_SRC_HFINT (0UL) /*!< HFINT - 64 MHz on-chip oscillator */
+#define CLOCK_HFCLKSTAT_SRC_HFXO (1UL) /*!< HFXO - 64 MHz clock derived from external 32 MHz crystal oscillator */
+
+/* Register: CLOCK_LFCLKRUN */
+/* Description: Status indicating that LFCLKSTART task has been triggered */
+
+/* Bit 0 : LFCLKSTART task triggered or not */
+#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
+#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
+
+/* Register: CLOCK_LFCLKSTAT */
+/* Description: The register shows which LFCLK source has been requested (SRC) when triggering LFCLKSTART task and if the source has been started (STATE) */
+
+/* Bit 16 : LFCLK state */
+#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
+#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
+#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< Requested LFCLK source has not been started or LFCLKSTOP task has been triggered */
+#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< Requested LFCLK source has been started (LFCLKSTARTED event has been generated) */
+
+/* Bits 1..0 : Active clock source */
+#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSTAT_SRC_RFU (0UL) /*!< Reserved for future use */
+#define CLOCK_LFCLKSTAT_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */
+#define CLOCK_LFCLKSTAT_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */
+
+/* Register: CLOCK_LFCLKSRCCOPY */
+/* Description: Copy of LFCLKSRC register, set after LFCLKSTART task has been triggered */
+
+/* Bits 1..0 : Clock source */
+#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSRCCOPY_SRC_RFU (0UL) /*!< Reserved for future use */
+#define CLOCK_LFCLKSRCCOPY_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */
+#define CLOCK_LFCLKSRCCOPY_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */
+
+/* Register: CLOCK_LFCLKSRC */
+/* Description: Clock source for the LFCLK. LFCLKSTART task starts starts a clock source selected with this register. */
+
+/* Bits 1..0 : Clock source */
+#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSRC_SRC_RFU (0UL) /*!< Reserved for future use (equals selecting LFRC) */
+#define CLOCK_LFCLKSRC_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */
+#define CLOCK_LFCLKSRC_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */
+
+
+/* Peripheral: CRYPTOCELL */
+/* Description: ARM TrustZone CryptoCell register interface */
+
+/* Register: CRYPTOCELL_ENABLE */
+/* Description: Enable CRYPTOCELL subsystem */
+
+/* Bit 0 : Enable or disable the CRYPTOCELL subsystem */
+#define CRYPTOCELL_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define CRYPTOCELL_ENABLE_ENABLE_Msk (0x1UL << CRYPTOCELL_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define CRYPTOCELL_ENABLE_ENABLE_Disabled (0UL) /*!< CRYPTOCELL subsystem disabled */
+#define CRYPTOCELL_ENABLE_ENABLE_Enabled (1UL) /*!< CRYPTOCELL subsystem enabled. */
+
+
+/* Peripheral: CTRLAPPERI */
+/* Description: Control access port */
+
+/* Register: CTRLAPPERI_MAILBOX_RXDATA */
+/* Description: Data sent from the debugger to the CPU. */
+
+/* Bits 31..0 : Data received from debugger */
+#define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos (0UL) /*!< Position of RXDATA field. */
+#define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos) /*!< Bit mask of RXDATA field. */
+
+/* Register: CTRLAPPERI_MAILBOX_RXSTATUS */
+/* Description: This register shows a status that indicates if data sent from the debugger to the CPU has been read. */
+
+/* Bit 0 : Status of data in register RXDATA */
+#define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos (0UL) /*!< Position of RXSTATUS field. */
+#define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos) /*!< Bit mask of RXSTATUS field. */
+#define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_NoDataPending (0UL) /*!< No data pending in register RXDATA */
+#define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_DataPending (1UL) /*!< Data pending in register RXDATA */
+
+/* Register: CTRLAPPERI_MAILBOX_TXDATA */
+/* Description: Data sent from the CPU to the debugger. */
+
+/* Bits 31..0 : Data sent to debugger */
+#define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos (0UL) /*!< Position of TXDATA field. */
+#define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos) /*!< Bit mask of TXDATA field. */
+
+/* Register: CTRLAPPERI_MAILBOX_TXSTATUS */
+/* Description: This register shows a status that indicates if the data sent from the CPU to the debugger has been read. */
+
+/* Bit 0 : Status of data in register TXDATA */
+#define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos (0UL) /*!< Position of TXSTATUS field. */
+#define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos) /*!< Bit mask of TXSTATUS field. */
+#define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_NoDataPending (0UL) /*!< No data pending in register TXDATA */
+#define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_DataPending (1UL) /*!< Data pending in register TXDATA */
+
+/* Register: CTRLAPPERI_ERASEPROTECT_LOCK */
+/* Description: This register locks the ERASEPROTECT.DISABLE register from being written until next reset. */
+
+/* Bit 0 : Lock ERASEPROTECT.DISABLE register from being written until next reset */
+#define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */
+#define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Msk (0x1UL << CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */
+#define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Unlocked (0UL) /*!< Register ERASEPROTECT.DISABLE is writeable */
+#define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Locked (1UL) /*!< Register ERASEPROTECT.DISABLE is read-only */
+
+/* Register: CTRLAPPERI_ERASEPROTECT_DISABLE */
+/* Description: This register disables the ERASEPROTECT register and performs an ERASEALL operation. */
+
+/* Bits 31..0 : The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. */
+#define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos (0UL) /*!< Position of KEY field. */
+#define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos) /*!< Bit mask of KEY field. */
+
+
+/* Peripheral: DPPIC */
+/* Description: Distributed programmable peripheral interconnect controller 0 */
+
+/* Register: DPPIC_TASKS_CHG_EN */
+/* Description: Description cluster: Enable channel group n */
+
+/* Bit 0 : Enable channel group n */
+#define DPPIC_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */
+#define DPPIC_TASKS_CHG_EN_EN_Msk (0x1UL << DPPIC_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */
+#define DPPIC_TASKS_CHG_EN_EN_Trigger (1UL) /*!< Trigger task */
+
+/* Register: DPPIC_TASKS_CHG_DIS */
+/* Description: Description cluster: Disable channel group n */
+
+/* Bit 0 : Disable channel group n */
+#define DPPIC_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */
+#define DPPIC_TASKS_CHG_DIS_DIS_Msk (0x1UL << DPPIC_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */
+#define DPPIC_TASKS_CHG_DIS_DIS_Trigger (1UL) /*!< Trigger task */
+
+/* Register: DPPIC_SUBSCRIBE_CHG_EN */
+/* Description: Description cluster: Subscribe configuration for task CHG[n].EN */
+
+/* Bit 31 : */
+#define DPPIC_SUBSCRIBE_CHG_EN_EN_Pos (31UL) /*!< Position of EN field. */
+#define DPPIC_SUBSCRIBE_CHG_EN_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */
+#define DPPIC_SUBSCRIBE_CHG_EN_EN_Disabled (0UL) /*!< Disable subscription */
+#define DPPIC_SUBSCRIBE_CHG_EN_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task CHG[n].EN will subscribe to */
+#define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: DPPIC_SUBSCRIBE_CHG_DIS */
+/* Description: Description cluster: Subscribe configuration for task CHG[n].DIS */
+
+/* Bit 31 : */
+#define DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos (31UL) /*!< Position of EN field. */
+#define DPPIC_SUBSCRIBE_CHG_DIS_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos) /*!< Bit mask of EN field. */
+#define DPPIC_SUBSCRIBE_CHG_DIS_EN_Disabled (0UL) /*!< Disable subscription */
+#define DPPIC_SUBSCRIBE_CHG_DIS_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task CHG[n].DIS will subscribe to */
+#define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: DPPIC_CHEN */
+/* Description: Channel enable register */
+
+/* Bit 15 : Enable or disable channel 15 */
+#define DPPIC_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define DPPIC_CHEN_CH15_Msk (0x1UL << DPPIC_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define DPPIC_CHEN_CH15_Disabled (0UL) /*!< Disable channel */
+#define DPPIC_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 14 : Enable or disable channel 14 */
+#define DPPIC_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define DPPIC_CHEN_CH14_Msk (0x1UL << DPPIC_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define DPPIC_CHEN_CH14_Disabled (0UL) /*!< Disable channel */
+#define DPPIC_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 13 : Enable or disable channel 13 */
+#define DPPIC_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define DPPIC_CHEN_CH13_Msk (0x1UL << DPPIC_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define DPPIC_CHEN_CH13_Disabled (0UL) /*!< Disable channel */
+#define DPPIC_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 12 : Enable or disable channel 12 */
+#define DPPIC_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define DPPIC_CHEN_CH12_Msk (0x1UL << DPPIC_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define DPPIC_CHEN_CH12_Disabled (0UL) /*!< Disable channel */
+#define DPPIC_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 11 : Enable or disable channel 11 */
+#define DPPIC_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define DPPIC_CHEN_CH11_Msk (0x1UL << DPPIC_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define DPPIC_CHEN_CH11_Disabled (0UL) /*!< Disable channel */
+#define DPPIC_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 10 : Enable or disable channel 10 */
+#define DPPIC_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define DPPIC_CHEN_CH10_Msk (0x1UL << DPPIC_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define DPPIC_CHEN_CH10_Disabled (0UL) /*!< Disable channel */
+#define DPPIC_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 9 : Enable or disable channel 9 */
+#define DPPIC_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define DPPIC_CHEN_CH9_Msk (0x1UL << DPPIC_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define DPPIC_CHEN_CH9_Disabled (0UL) /*!< Disable channel */
+#define DPPIC_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 8 : Enable or disable channel 8 */
+#define DPPIC_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define DPPIC_CHEN_CH8_Msk (0x1UL << DPPIC_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define DPPIC_CHEN_CH8_Disabled (0UL) /*!< Disable channel */
+#define DPPIC_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 7 : Enable or disable channel 7 */
+#define DPPIC_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define DPPIC_CHEN_CH7_Msk (0x1UL << DPPIC_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define DPPIC_CHEN_CH7_Disabled (0UL) /*!< Disable channel */
+#define DPPIC_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 6 : Enable or disable channel 6 */
+#define DPPIC_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define DPPIC_CHEN_CH6_Msk (0x1UL << DPPIC_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define DPPIC_CHEN_CH6_Disabled (0UL) /*!< Disable channel */
+#define DPPIC_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 5 : Enable or disable channel 5 */
+#define DPPIC_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define DPPIC_CHEN_CH5_Msk (0x1UL << DPPIC_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define DPPIC_CHEN_CH5_Disabled (0UL) /*!< Disable channel */
+#define DPPIC_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 4 : Enable or disable channel 4 */
+#define DPPIC_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define DPPIC_CHEN_CH4_Msk (0x1UL << DPPIC_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define DPPIC_CHEN_CH4_Disabled (0UL) /*!< Disable channel */
+#define DPPIC_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 3 : Enable or disable channel 3 */
+#define DPPIC_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define DPPIC_CHEN_CH3_Msk (0x1UL << DPPIC_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define DPPIC_CHEN_CH3_Disabled (0UL) /*!< Disable channel */
+#define DPPIC_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 2 : Enable or disable channel 2 */
+#define DPPIC_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define DPPIC_CHEN_CH2_Msk (0x1UL << DPPIC_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define DPPIC_CHEN_CH2_Disabled (0UL) /*!< Disable channel */
+#define DPPIC_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 1 : Enable or disable channel 1 */
+#define DPPIC_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define DPPIC_CHEN_CH1_Msk (0x1UL << DPPIC_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define DPPIC_CHEN_CH1_Disabled (0UL) /*!< Disable channel */
+#define DPPIC_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 0 : Enable or disable channel 0 */
+#define DPPIC_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define DPPIC_CHEN_CH0_Msk (0x1UL << DPPIC_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define DPPIC_CHEN_CH0_Disabled (0UL) /*!< Disable channel */
+#define DPPIC_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
+
+/* Register: DPPIC_CHENSET */
+/* Description: Channel enable set register */
+
+/* Bit 15 : Channel 15 enable set register. Writing 0 has no effect. */
+#define DPPIC_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define DPPIC_CHENSET_CH15_Msk (0x1UL << DPPIC_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define DPPIC_CHENSET_CH15_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH15_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 14 : Channel 14 enable set register. Writing 0 has no effect. */
+#define DPPIC_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define DPPIC_CHENSET_CH14_Msk (0x1UL << DPPIC_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define DPPIC_CHENSET_CH14_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH14_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 13 : Channel 13 enable set register. Writing 0 has no effect. */
+#define DPPIC_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define DPPIC_CHENSET_CH13_Msk (0x1UL << DPPIC_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define DPPIC_CHENSET_CH13_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH13_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 12 : Channel 12 enable set register. Writing 0 has no effect. */
+#define DPPIC_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define DPPIC_CHENSET_CH12_Msk (0x1UL << DPPIC_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define DPPIC_CHENSET_CH12_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH12_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 11 : Channel 11 enable set register. Writing 0 has no effect. */
+#define DPPIC_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define DPPIC_CHENSET_CH11_Msk (0x1UL << DPPIC_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define DPPIC_CHENSET_CH11_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH11_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 10 : Channel 10 enable set register. Writing 0 has no effect. */
+#define DPPIC_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define DPPIC_CHENSET_CH10_Msk (0x1UL << DPPIC_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define DPPIC_CHENSET_CH10_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH10_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 9 : Channel 9 enable set register. Writing 0 has no effect. */
+#define DPPIC_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define DPPIC_CHENSET_CH9_Msk (0x1UL << DPPIC_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define DPPIC_CHENSET_CH9_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH9_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 8 : Channel 8 enable set register. Writing 0 has no effect. */
+#define DPPIC_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define DPPIC_CHENSET_CH8_Msk (0x1UL << DPPIC_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define DPPIC_CHENSET_CH8_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH8_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 7 : Channel 7 enable set register. Writing 0 has no effect. */
+#define DPPIC_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define DPPIC_CHENSET_CH7_Msk (0x1UL << DPPIC_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define DPPIC_CHENSET_CH7_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH7_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 6 : Channel 6 enable set register. Writing 0 has no effect. */
+#define DPPIC_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define DPPIC_CHENSET_CH6_Msk (0x1UL << DPPIC_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define DPPIC_CHENSET_CH6_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH6_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 5 : Channel 5 enable set register. Writing 0 has no effect. */
+#define DPPIC_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define DPPIC_CHENSET_CH5_Msk (0x1UL << DPPIC_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define DPPIC_CHENSET_CH5_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH5_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 4 : Channel 4 enable set register. Writing 0 has no effect. */
+#define DPPIC_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define DPPIC_CHENSET_CH4_Msk (0x1UL << DPPIC_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define DPPIC_CHENSET_CH4_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH4_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 3 : Channel 3 enable set register. Writing 0 has no effect. */
+#define DPPIC_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define DPPIC_CHENSET_CH3_Msk (0x1UL << DPPIC_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define DPPIC_CHENSET_CH3_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH3_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 2 : Channel 2 enable set register. Writing 0 has no effect. */
+#define DPPIC_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define DPPIC_CHENSET_CH2_Msk (0x1UL << DPPIC_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define DPPIC_CHENSET_CH2_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH2_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 1 : Channel 1 enable set register. Writing 0 has no effect. */
+#define DPPIC_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define DPPIC_CHENSET_CH1_Msk (0x1UL << DPPIC_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define DPPIC_CHENSET_CH1_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH1_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 0 : Channel 0 enable set register. Writing 0 has no effect. */
+#define DPPIC_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define DPPIC_CHENSET_CH0_Msk (0x1UL << DPPIC_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define DPPIC_CHENSET_CH0_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH0_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
+
+/* Register: DPPIC_CHENCLR */
+/* Description: Channel enable clear register */
+
+/* Bit 15 : Channel 15 enable clear register. Writing 0 has no effect. */
+#define DPPIC_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define DPPIC_CHENCLR_CH15_Msk (0x1UL << DPPIC_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define DPPIC_CHENCLR_CH15_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH15_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH15_Clear (1UL) /*!< Write: Disable channel */
+
+/* Bit 14 : Channel 14 enable clear register. Writing 0 has no effect. */
+#define DPPIC_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define DPPIC_CHENCLR_CH14_Msk (0x1UL << DPPIC_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define DPPIC_CHENCLR_CH14_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH14_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH14_Clear (1UL) /*!< Write: Disable channel */
+
+/* Bit 13 : Channel 13 enable clear register. Writing 0 has no effect. */
+#define DPPIC_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define DPPIC_CHENCLR_CH13_Msk (0x1UL << DPPIC_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define DPPIC_CHENCLR_CH13_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH13_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH13_Clear (1UL) /*!< Write: Disable channel */
+
+/* Bit 12 : Channel 12 enable clear register. Writing 0 has no effect. */
+#define DPPIC_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define DPPIC_CHENCLR_CH12_Msk (0x1UL << DPPIC_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define DPPIC_CHENCLR_CH12_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH12_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH12_Clear (1UL) /*!< Write: Disable channel */
+
+/* Bit 11 : Channel 11 enable clear register. Writing 0 has no effect. */
+#define DPPIC_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define DPPIC_CHENCLR_CH11_Msk (0x1UL << DPPIC_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define DPPIC_CHENCLR_CH11_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH11_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH11_Clear (1UL) /*!< Write: Disable channel */
+
+/* Bit 10 : Channel 10 enable clear register. Writing 0 has no effect. */
+#define DPPIC_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define DPPIC_CHENCLR_CH10_Msk (0x1UL << DPPIC_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define DPPIC_CHENCLR_CH10_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH10_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH10_Clear (1UL) /*!< Write: Disable channel */
+
+/* Bit 9 : Channel 9 enable clear register. Writing 0 has no effect. */
+#define DPPIC_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define DPPIC_CHENCLR_CH9_Msk (0x1UL << DPPIC_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define DPPIC_CHENCLR_CH9_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH9_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH9_Clear (1UL) /*!< Write: Disable channel */
+
+/* Bit 8 : Channel 8 enable clear register. Writing 0 has no effect. */
+#define DPPIC_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define DPPIC_CHENCLR_CH8_Msk (0x1UL << DPPIC_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define DPPIC_CHENCLR_CH8_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH8_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH8_Clear (1UL) /*!< Write: Disable channel */
+
+/* Bit 7 : Channel 7 enable clear register. Writing 0 has no effect. */
+#define DPPIC_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define DPPIC_CHENCLR_CH7_Msk (0x1UL << DPPIC_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define DPPIC_CHENCLR_CH7_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH7_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH7_Clear (1UL) /*!< Write: Disable channel */
+
+/* Bit 6 : Channel 6 enable clear register. Writing 0 has no effect. */
+#define DPPIC_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define DPPIC_CHENCLR_CH6_Msk (0x1UL << DPPIC_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define DPPIC_CHENCLR_CH6_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH6_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH6_Clear (1UL) /*!< Write: Disable channel */
+
+/* Bit 5 : Channel 5 enable clear register. Writing 0 has no effect. */
+#define DPPIC_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define DPPIC_CHENCLR_CH5_Msk (0x1UL << DPPIC_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define DPPIC_CHENCLR_CH5_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH5_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH5_Clear (1UL) /*!< Write: Disable channel */
+
+/* Bit 4 : Channel 4 enable clear register. Writing 0 has no effect. */
+#define DPPIC_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define DPPIC_CHENCLR_CH4_Msk (0x1UL << DPPIC_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define DPPIC_CHENCLR_CH4_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH4_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH4_Clear (1UL) /*!< Write: Disable channel */
+
+/* Bit 3 : Channel 3 enable clear register. Writing 0 has no effect. */
+#define DPPIC_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define DPPIC_CHENCLR_CH3_Msk (0x1UL << DPPIC_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define DPPIC_CHENCLR_CH3_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH3_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH3_Clear (1UL) /*!< Write: Disable channel */
+
+/* Bit 2 : Channel 2 enable clear register. Writing 0 has no effect. */
+#define DPPIC_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define DPPIC_CHENCLR_CH2_Msk (0x1UL << DPPIC_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define DPPIC_CHENCLR_CH2_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH2_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH2_Clear (1UL) /*!< Write: Disable channel */
+
+/* Bit 1 : Channel 1 enable clear register. Writing 0 has no effect. */
+#define DPPIC_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define DPPIC_CHENCLR_CH1_Msk (0x1UL << DPPIC_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define DPPIC_CHENCLR_CH1_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH1_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH1_Clear (1UL) /*!< Write: Disable channel */
+
+/* Bit 0 : Channel 0 enable clear register. Writing 0 has no effect. */
+#define DPPIC_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define DPPIC_CHENCLR_CH0_Msk (0x1UL << DPPIC_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define DPPIC_CHENCLR_CH0_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH0_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH0_Clear (1UL) /*!< Write: Disable channel */
+
+/* Register: DPPIC_CHG */
+/* Description: Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled */
+
+/* Bit 15 : Include or exclude channel 15 */
+#define DPPIC_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define DPPIC_CHG_CH15_Msk (0x1UL << DPPIC_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define DPPIC_CHG_CH15_Excluded (0UL) /*!< Exclude */
+#define DPPIC_CHG_CH15_Included (1UL) /*!< Include */
+
+/* Bit 14 : Include or exclude channel 14 */
+#define DPPIC_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define DPPIC_CHG_CH14_Msk (0x1UL << DPPIC_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define DPPIC_CHG_CH14_Excluded (0UL) /*!< Exclude */
+#define DPPIC_CHG_CH14_Included (1UL) /*!< Include */
+
+/* Bit 13 : Include or exclude channel 13 */
+#define DPPIC_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define DPPIC_CHG_CH13_Msk (0x1UL << DPPIC_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define DPPIC_CHG_CH13_Excluded (0UL) /*!< Exclude */
+#define DPPIC_CHG_CH13_Included (1UL) /*!< Include */
+
+/* Bit 12 : Include or exclude channel 12 */
+#define DPPIC_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define DPPIC_CHG_CH12_Msk (0x1UL << DPPIC_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define DPPIC_CHG_CH12_Excluded (0UL) /*!< Exclude */
+#define DPPIC_CHG_CH12_Included (1UL) /*!< Include */
+
+/* Bit 11 : Include or exclude channel 11 */
+#define DPPIC_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define DPPIC_CHG_CH11_Msk (0x1UL << DPPIC_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define DPPIC_CHG_CH11_Excluded (0UL) /*!< Exclude */
+#define DPPIC_CHG_CH11_Included (1UL) /*!< Include */
+
+/* Bit 10 : Include or exclude channel 10 */
+#define DPPIC_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define DPPIC_CHG_CH10_Msk (0x1UL << DPPIC_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define DPPIC_CHG_CH10_Excluded (0UL) /*!< Exclude */
+#define DPPIC_CHG_CH10_Included (1UL) /*!< Include */
+
+/* Bit 9 : Include or exclude channel 9 */
+#define DPPIC_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define DPPIC_CHG_CH9_Msk (0x1UL << DPPIC_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define DPPIC_CHG_CH9_Excluded (0UL) /*!< Exclude */
+#define DPPIC_CHG_CH9_Included (1UL) /*!< Include */
+
+/* Bit 8 : Include or exclude channel 8 */
+#define DPPIC_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define DPPIC_CHG_CH8_Msk (0x1UL << DPPIC_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define DPPIC_CHG_CH8_Excluded (0UL) /*!< Exclude */
+#define DPPIC_CHG_CH8_Included (1UL) /*!< Include */
+
+/* Bit 7 : Include or exclude channel 7 */
+#define DPPIC_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define DPPIC_CHG_CH7_Msk (0x1UL << DPPIC_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define DPPIC_CHG_CH7_Excluded (0UL) /*!< Exclude */
+#define DPPIC_CHG_CH7_Included (1UL) /*!< Include */
+
+/* Bit 6 : Include or exclude channel 6 */
+#define DPPIC_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define DPPIC_CHG_CH6_Msk (0x1UL << DPPIC_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define DPPIC_CHG_CH6_Excluded (0UL) /*!< Exclude */
+#define DPPIC_CHG_CH6_Included (1UL) /*!< Include */
+
+/* Bit 5 : Include or exclude channel 5 */
+#define DPPIC_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define DPPIC_CHG_CH5_Msk (0x1UL << DPPIC_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define DPPIC_CHG_CH5_Excluded (0UL) /*!< Exclude */
+#define DPPIC_CHG_CH5_Included (1UL) /*!< Include */
+
+/* Bit 4 : Include or exclude channel 4 */
+#define DPPIC_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define DPPIC_CHG_CH4_Msk (0x1UL << DPPIC_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define DPPIC_CHG_CH4_Excluded (0UL) /*!< Exclude */
+#define DPPIC_CHG_CH4_Included (1UL) /*!< Include */
+
+/* Bit 3 : Include or exclude channel 3 */
+#define DPPIC_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define DPPIC_CHG_CH3_Msk (0x1UL << DPPIC_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define DPPIC_CHG_CH3_Excluded (0UL) /*!< Exclude */
+#define DPPIC_CHG_CH3_Included (1UL) /*!< Include */
+
+/* Bit 2 : Include or exclude channel 2 */
+#define DPPIC_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define DPPIC_CHG_CH2_Msk (0x1UL << DPPIC_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define DPPIC_CHG_CH2_Excluded (0UL) /*!< Exclude */
+#define DPPIC_CHG_CH2_Included (1UL) /*!< Include */
+
+/* Bit 1 : Include or exclude channel 1 */
+#define DPPIC_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define DPPIC_CHG_CH1_Msk (0x1UL << DPPIC_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define DPPIC_CHG_CH1_Excluded (0UL) /*!< Exclude */
+#define DPPIC_CHG_CH1_Included (1UL) /*!< Include */
+
+/* Bit 0 : Include or exclude channel 0 */
+#define DPPIC_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define DPPIC_CHG_CH0_Msk (0x1UL << DPPIC_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define DPPIC_CHG_CH0_Excluded (0UL) /*!< Exclude */
+#define DPPIC_CHG_CH0_Included (1UL) /*!< Include */
+
+
+/* Peripheral: EGU */
+/* Description: Event generator unit 0 */
+
+/* Register: EGU_TASKS_TRIGGER */
+/* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */
+
+/* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */
+#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */
+#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */
+#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL) /*!< Trigger task */
+
+/* Register: EGU_SUBSCRIBE_TRIGGER */
+/* Description: Description collection: Subscribe configuration for task TRIGGER[n] */
+
+/* Bit 31 : */
+#define EGU_SUBSCRIBE_TRIGGER_EN_Pos (31UL) /*!< Position of EN field. */
+#define EGU_SUBSCRIBE_TRIGGER_EN_Msk (0x1UL << EGU_SUBSCRIBE_TRIGGER_EN_Pos) /*!< Bit mask of EN field. */
+#define EGU_SUBSCRIBE_TRIGGER_EN_Disabled (0UL) /*!< Disable subscription */
+#define EGU_SUBSCRIBE_TRIGGER_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task TRIGGER[n] will subscribe to */
+#define EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define EGU_SUBSCRIBE_TRIGGER_CHIDX_Msk (0xFFUL << EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: EGU_EVENTS_TRIGGERED */
+/* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */
+
+/* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */
+#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */
+#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */
+#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0UL) /*!< Event not generated */
+#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL) /*!< Event generated */
+
+/* Register: EGU_PUBLISH_TRIGGERED */
+/* Description: Description collection: Publish configuration for event TRIGGERED[n] */
+
+/* Bit 31 : */
+#define EGU_PUBLISH_TRIGGERED_EN_Pos (31UL) /*!< Position of EN field. */
+#define EGU_PUBLISH_TRIGGERED_EN_Msk (0x1UL << EGU_PUBLISH_TRIGGERED_EN_Pos) /*!< Bit mask of EN field. */
+#define EGU_PUBLISH_TRIGGERED_EN_Disabled (0UL) /*!< Disable publishing */
+#define EGU_PUBLISH_TRIGGERED_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event TRIGGERED[n] will publish to */
+#define EGU_PUBLISH_TRIGGERED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define EGU_PUBLISH_TRIGGERED_CHIDX_Msk (0xFFUL << EGU_PUBLISH_TRIGGERED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: EGU_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */
+#define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
+#define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
+#define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
+
+/* Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */
+#define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
+#define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
+#define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
+
+/* Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */
+#define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
+#define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
+#define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
+
+/* Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */
+#define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
+#define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
+#define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
+
+/* Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */
+#define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
+#define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
+#define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
+
+/* Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */
+#define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
+#define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
+#define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */
+#define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
+#define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
+#define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
+
+/* Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */
+#define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
+#define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
+#define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */
+#define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
+#define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
+#define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */
+#define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
+#define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
+#define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */
+#define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
+#define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
+#define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */
+#define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
+#define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
+#define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */
+#define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
+#define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
+#define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */
+#define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
+#define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
+#define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */
+#define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
+#define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
+#define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */
+#define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
+#define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
+#define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
+
+/* Register: EGU_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */
+#define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
+#define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
+#define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */
+#define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
+#define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
+#define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
+
+/* Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */
+#define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
+#define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
+#define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */
+#define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
+#define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
+#define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
+
+/* Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */
+#define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
+#define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
+#define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */
+#define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
+#define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
+#define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */
+#define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
+#define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
+#define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */
+#define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
+#define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
+#define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */
+#define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
+#define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
+#define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */
+#define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
+#define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
+#define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */
+#define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
+#define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
+#define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */
+#define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
+#define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
+#define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */
+#define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
+#define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
+#define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */
+#define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
+#define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
+#define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */
+#define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
+#define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
+#define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */
+#define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
+#define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
+#define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
+
+/* Register: EGU_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */
+#define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
+#define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
+#define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */
+#define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
+#define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
+#define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
+
+/* Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */
+#define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
+#define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
+#define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */
+#define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
+#define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
+#define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
+
+/* Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */
+#define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
+#define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
+#define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */
+#define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
+#define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
+#define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */
+#define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
+#define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
+#define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */
+#define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
+#define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
+#define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */
+#define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
+#define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
+#define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */
+#define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
+#define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
+#define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */
+#define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
+#define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
+#define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */
+#define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
+#define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
+#define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */
+#define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
+#define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
+#define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */
+#define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
+#define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
+#define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */
+#define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
+#define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
+#define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */
+#define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
+#define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
+#define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
+
+
+/* Peripheral: FICR */
+/* Description: Factory Information Configuration Registers */
+
+/* Register: FICR_SIPINFO_PARTNO */
+/* Description: SIP part number */
+
+/* Bits 31..0 : */
+#define FICR_SIPINFO_PARTNO_PARTNO_Pos (0UL) /*!< Position of PARTNO field. */
+#define FICR_SIPINFO_PARTNO_PARTNO_Msk (0xFFFFFFFFUL << FICR_SIPINFO_PARTNO_PARTNO_Pos) /*!< Bit mask of PARTNO field. */
+#define FICR_SIPINFO_PARTNO_PARTNO_9160 (0x00009160UL) /*!< Device is an nRF9160 sip */
+
+/* Register: FICR_SIPINFO_HWREVISION */
+/* Description: Description collection: SIP hardware revision, encoded in ASCII, ex B0A or B1A */
+
+/* Bits 7..0 : */
+#define FICR_SIPINFO_HWREVISION_HWREVISION_Pos (0UL) /*!< Position of HWREVISION field. */
+#define FICR_SIPINFO_HWREVISION_HWREVISION_Msk (0xFFUL << FICR_SIPINFO_HWREVISION_HWREVISION_Pos) /*!< Bit mask of HWREVISION field. */
+
+/* Register: FICR_SIPINFO_VARIANT */
+/* Description: Description collection: SIP VARIANT, encoded in ASCII, ex SIAA, SIBA or SICA */
+
+/* Bits 7..0 : */
+#define FICR_SIPINFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
+#define FICR_SIPINFO_VARIANT_VARIANT_Msk (0xFFUL << FICR_SIPINFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
+
+/* Register: FICR_INFO_DEVICEID */
+/* Description: Description collection: Device identifier */
+
+/* Bits 31..0 : 64 bit unique device identifier */
+#define FICR_INFO_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */
+#define FICR_INFO_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */
+
+/* Register: FICR_INFO_PART */
+/* Description: Part code */
+
+/* Bits 31..0 : Part code */
+#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
+#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
+#define FICR_INFO_PART_PART_N9120 (0x9120UL) /*!< nRF9120 */
+#define FICR_INFO_PART_PART_N9160 (0x9160UL) /*!< nRF9160 */
+
+/* Register: FICR_INFO_VARIANT */
+/* Description: Part Variant, Hardware version and Production configuration */
+
+/* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */
+#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
+#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
+#define FICR_INFO_VARIANT_VARIANT_AAA0 (0x41414130UL) /*!< AAA0 */
+#define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */
+#define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */
+#define FICR_INFO_VARIANT_VARIANT_AAC0 (0x41414330UL) /*!< AAC0 */
+
+/* Register: FICR_INFO_PACKAGE */
+/* Description: Package option */
+
+/* Bits 31..0 : Package option */
+#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
+#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
+#define FICR_INFO_PACKAGE_PACKAGE_CF (0x2002UL) /*!< CFxx - 236 ball wlCSP */
+
+/* Register: FICR_INFO_RAM */
+/* Description: RAM variant */
+
+/* Bits 31..0 : RAM variant */
+#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
+#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
+#define FICR_INFO_RAM_RAM_K256 (0x100UL) /*!< 256 kByte RAM */
+#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_FLASH */
+/* Description: Flash variant */
+
+/* Bits 31..0 : Flash variant */
+#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
+#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
+#define FICR_INFO_FLASH_FLASH_K1024 (0x400UL) /*!< 1 MByte FLASH */
+
+/* Register: FICR_INFO_CODEPAGESIZE */
+/* Description: Code memory page size */
+
+/* Bits 31..0 : Code memory page size */
+#define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */
+#define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */
+#define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_K4096 (0x1000UL) /*!< 4 kByte */
+
+/* Register: FICR_INFO_CODESIZE */
+/* Description: Code memory size */
+
+/* Bits 31..0 : Code memory size in number of pages Total code space is: CODEPAGESIZE * CODESIZE */
+#define FICR_INFO_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */
+#define FICR_INFO_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */
+#define FICR_INFO_CODESIZE_CODESIZE_P256 (256UL) /*!< 256 pages */
+
+/* Register: FICR_INFO_DEVICETYPE */
+/* Description: Device type */
+
+/* Bits 31..0 : Device type */
+#define FICR_INFO_DEVICETYPE_DEVICETYPE_Pos (0UL) /*!< Position of DEVICETYPE field. */
+#define FICR_INFO_DEVICETYPE_DEVICETYPE_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICETYPE_DEVICETYPE_Pos) /*!< Bit mask of DEVICETYPE field. */
+#define FICR_INFO_DEVICETYPE_DEVICETYPE_Die (0x0000000UL) /*!< Device is an physical DIE */
+#define FICR_INFO_DEVICETYPE_DEVICETYPE_FPGA (0xFFFFFFFFUL) /*!< Device is an FPGA */
+
+/* Register: FICR_TRIMCNF_ADDR */
+/* Description: Description cluster: Address */
+
+/* Bits 31..0 : Address */
+#define FICR_TRIMCNF_ADDR_Address_Pos (0UL) /*!< Position of Address field. */
+#define FICR_TRIMCNF_ADDR_Address_Msk (0xFFFFFFFFUL << FICR_TRIMCNF_ADDR_Address_Pos) /*!< Bit mask of Address field. */
+
+/* Register: FICR_TRIMCNF_DATA */
+/* Description: Description cluster: Data */
+
+/* Bits 31..0 : Data */
+#define FICR_TRIMCNF_DATA_Data_Pos (0UL) /*!< Position of Data field. */
+#define FICR_TRIMCNF_DATA_Data_Msk (0xFFFFFFFFUL << FICR_TRIMCNF_DATA_Data_Pos) /*!< Bit mask of Data field. */
+
+/* Register: FICR_TRNG90B_BYTES */
+/* Description: Amount of bytes for the required entropy bits */
+
+/* Bits 31..0 : Amount of bytes for the required entropy bits */
+#define FICR_TRNG90B_BYTES_BYTES_Pos (0UL) /*!< Position of BYTES field. */
+#define FICR_TRNG90B_BYTES_BYTES_Msk (0xFFFFFFFFUL << FICR_TRNG90B_BYTES_BYTES_Pos) /*!< Bit mask of BYTES field. */
+
+/* Register: FICR_TRNG90B_RCCUTOFF */
+/* Description: Repetition counter cutoff */
+
+/* Bits 31..0 : Repetition counter cutoff */
+#define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos (0UL) /*!< Position of RCCUTOFF field. */
+#define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos) /*!< Bit mask of RCCUTOFF field. */
+
+/* Register: FICR_TRNG90B_APCUTOFF */
+/* Description: Adaptive proportion cutoff */
+
+/* Bits 31..0 : Adaptive proportion cutoff */
+#define FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos (0UL) /*!< Position of APCUTOFF field. */
+#define FICR_TRNG90B_APCUTOFF_APCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos) /*!< Bit mask of APCUTOFF field. */
+
+/* Register: FICR_TRNG90B_STARTUP */
+/* Description: Amount of bytes for the startup tests */
+
+/* Bits 31..0 : Amount of bytes for the startup tests */
+#define FICR_TRNG90B_STARTUP_STARTUP_Pos (0UL) /*!< Position of STARTUP field. */
+#define FICR_TRNG90B_STARTUP_STARTUP_Msk (0xFFFFFFFFUL << FICR_TRNG90B_STARTUP_STARTUP_Pos) /*!< Bit mask of STARTUP field. */
+
+/* Register: FICR_TRNG90B_ROSC1 */
+/* Description: Sample count for ring oscillator 1 */
+
+/* Bits 31..0 : Sample count for ring oscillator 1 */
+#define FICR_TRNG90B_ROSC1_ROSC1_Pos (0UL) /*!< Position of ROSC1 field. */
+#define FICR_TRNG90B_ROSC1_ROSC1_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC1_ROSC1_Pos) /*!< Bit mask of ROSC1 field. */
+
+/* Register: FICR_TRNG90B_ROSC2 */
+/* Description: Sample count for ring oscillator 2 */
+
+/* Bits 31..0 : Sample count for ring oscillator 2 */
+#define FICR_TRNG90B_ROSC2_ROSC2_Pos (0UL) /*!< Position of ROSC2 field. */
+#define FICR_TRNG90B_ROSC2_ROSC2_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC2_ROSC2_Pos) /*!< Bit mask of ROSC2 field. */
+
+/* Register: FICR_TRNG90B_ROSC3 */
+/* Description: Sample count for ring oscillator 3 */
+
+/* Bits 31..0 : Sample count for ring oscillator 3 */
+#define FICR_TRNG90B_ROSC3_ROSC3_Pos (0UL) /*!< Position of ROSC3 field. */
+#define FICR_TRNG90B_ROSC3_ROSC3_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC3_ROSC3_Pos) /*!< Bit mask of ROSC3 field. */
+
+/* Register: FICR_TRNG90B_ROSC4 */
+/* Description: Sample count for ring oscillator 4 */
+
+/* Bits 31..0 : Sample count for ring oscillator 4 */
+#define FICR_TRNG90B_ROSC4_ROSC4_Pos (0UL) /*!< Position of ROSC4 field. */
+#define FICR_TRNG90B_ROSC4_ROSC4_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC4_ROSC4_Pos) /*!< Bit mask of ROSC4 field. */
+
+
+/* Peripheral: GPIOTE */
+/* Description: GPIO Tasks and Events 0 */
+
+/* Register: GPIOTE_TASKS_OUT */
+/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
+
+/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
+#define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */
+#define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */
+#define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (1UL) /*!< Trigger task */
+
+/* Register: GPIOTE_TASKS_SET */
+/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
+
+/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
+#define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */
+#define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */
+#define GPIOTE_TASKS_SET_TASKS_SET_Trigger (1UL) /*!< Trigger task */
+
+/* Register: GPIOTE_TASKS_CLR */
+/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
+
+/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
+#define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */
+#define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */
+#define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (1UL) /*!< Trigger task */
+
+/* Register: GPIOTE_SUBSCRIBE_OUT */
+/* Description: Description collection: Subscribe configuration for task OUT[n] */
+
+/* Bit 31 : */
+#define GPIOTE_SUBSCRIBE_OUT_EN_Pos (31UL) /*!< Position of EN field. */
+#define GPIOTE_SUBSCRIBE_OUT_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_OUT_EN_Pos) /*!< Bit mask of EN field. */
+#define GPIOTE_SUBSCRIBE_OUT_EN_Disabled (0UL) /*!< Disable subscription */
+#define GPIOTE_SUBSCRIBE_OUT_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task OUT[n] will subscribe to */
+#define GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define GPIOTE_SUBSCRIBE_OUT_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: GPIOTE_SUBSCRIBE_SET */
+/* Description: Description collection: Subscribe configuration for task SET[n] */
+
+/* Bit 31 : */
+#define GPIOTE_SUBSCRIBE_SET_EN_Pos (31UL) /*!< Position of EN field. */
+#define GPIOTE_SUBSCRIBE_SET_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_SET_EN_Pos) /*!< Bit mask of EN field. */
+#define GPIOTE_SUBSCRIBE_SET_EN_Disabled (0UL) /*!< Disable subscription */
+#define GPIOTE_SUBSCRIBE_SET_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task SET[n] will subscribe to */
+#define GPIOTE_SUBSCRIBE_SET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define GPIOTE_SUBSCRIBE_SET_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_SET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: GPIOTE_SUBSCRIBE_CLR */
+/* Description: Description collection: Subscribe configuration for task CLR[n] */
+
+/* Bit 31 : */
+#define GPIOTE_SUBSCRIBE_CLR_EN_Pos (31UL) /*!< Position of EN field. */
+#define GPIOTE_SUBSCRIBE_CLR_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_CLR_EN_Pos) /*!< Bit mask of EN field. */
+#define GPIOTE_SUBSCRIBE_CLR_EN_Disabled (0UL) /*!< Disable subscription */
+#define GPIOTE_SUBSCRIBE_CLR_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task CLR[n] will subscribe to */
+#define GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define GPIOTE_SUBSCRIBE_CLR_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: GPIOTE_EVENTS_IN */
+/* Description: Description collection: Event generated from pin specified in CONFIG[n].PSEL */
+
+/* Bit 0 : Event generated from pin specified in CONFIG[n].PSEL */
+#define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */
+#define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */
+#define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0UL) /*!< Event not generated */
+#define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (1UL) /*!< Event generated */
+
+/* Register: GPIOTE_EVENTS_PORT */
+/* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */
+
+/* Bit 0 : Event generated from multiple input GPIO pins with SENSE mechanism enabled */
+#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */
+#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */
+#define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0UL) /*!< Event not generated */
+#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (1UL) /*!< Event generated */
+
+/* Register: GPIOTE_PUBLISH_IN */
+/* Description: Description collection: Publish configuration for event IN[n] */
+
+/* Bit 31 : */
+#define GPIOTE_PUBLISH_IN_EN_Pos (31UL) /*!< Position of EN field. */
+#define GPIOTE_PUBLISH_IN_EN_Msk (0x1UL << GPIOTE_PUBLISH_IN_EN_Pos) /*!< Bit mask of EN field. */
+#define GPIOTE_PUBLISH_IN_EN_Disabled (0UL) /*!< Disable publishing */
+#define GPIOTE_PUBLISH_IN_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event IN[n] will publish to */
+#define GPIOTE_PUBLISH_IN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define GPIOTE_PUBLISH_IN_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_IN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: GPIOTE_PUBLISH_PORT */
+/* Description: Publish configuration for event PORT */
+
+/* Bit 31 : */
+#define GPIOTE_PUBLISH_PORT_EN_Pos (31UL) /*!< Position of EN field. */
+#define GPIOTE_PUBLISH_PORT_EN_Msk (0x1UL << GPIOTE_PUBLISH_PORT_EN_Pos) /*!< Bit mask of EN field. */
+#define GPIOTE_PUBLISH_PORT_EN_Disabled (0UL) /*!< Disable publishing */
+#define GPIOTE_PUBLISH_PORT_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event PORT will publish to */
+#define GPIOTE_PUBLISH_PORT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define GPIOTE_PUBLISH_PORT_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_PORT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: GPIOTE_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 31 : Write '1' to enable interrupt for event PORT */
+#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
+#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
+#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to enable interrupt for event IN[7] */
+#define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */
+#define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */
+#define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to enable interrupt for event IN[6] */
+#define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */
+#define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */
+#define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to enable interrupt for event IN[5] */
+#define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */
+#define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */
+#define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to enable interrupt for event IN[4] */
+#define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */
+#define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */
+#define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to enable interrupt for event IN[3] */
+#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
+#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
+#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event IN[2] */
+#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
+#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
+#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event IN[1] */
+#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
+#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
+#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event IN[0] */
+#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
+#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
+#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
+
+/* Register: GPIOTE_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 31 : Write '1' to disable interrupt for event PORT */
+#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
+#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
+#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to disable interrupt for event IN[7] */
+#define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */
+#define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */
+#define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to disable interrupt for event IN[6] */
+#define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */
+#define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */
+#define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to disable interrupt for event IN[5] */
+#define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */
+#define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */
+#define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to disable interrupt for event IN[4] */
+#define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */
+#define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */
+#define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to disable interrupt for event IN[3] */
+#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
+#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
+#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event IN[2] */
+#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
+#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
+#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event IN[1] */
+#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
+#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
+#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event IN[0] */
+#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
+#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
+#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
+
+/* Register: GPIOTE_CONFIG */
+/* Description: Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event */
+
+/* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
+#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
+#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
+#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */
+#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */
+
+/* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */
+#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
+#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
+#define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */
+#define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */
+#define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */
+#define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */
+
+/* Bits 12..8 : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event */
+#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
+#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
+
+/* Bits 1..0 : Mode */
+#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
+#define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */
+#define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */
+#define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */
+
+
+/* Peripheral: I2S */
+/* Description: Inter-IC Sound 0 */
+
+/* Register: I2S_TASKS_START */
+/* Description: Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */
+
+/* Bit 0 : Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */
+#define I2S_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define I2S_TASKS_START_TASKS_START_Msk (0x1UL << I2S_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define I2S_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: I2S_TASKS_STOP */
+/* Description: Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */
+
+/* Bit 0 : Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */
+#define I2S_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define I2S_TASKS_STOP_TASKS_STOP_Msk (0x1UL << I2S_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define I2S_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: I2S_SUBSCRIBE_START */
+/* Description: Subscribe configuration for task START */
+
+/* Bit 31 : */
+#define I2S_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
+#define I2S_SUBSCRIBE_START_EN_Msk (0x1UL << I2S_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
+#define I2S_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
+#define I2S_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task START will subscribe to */
+#define I2S_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define I2S_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << I2S_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: I2S_SUBSCRIBE_STOP */
+/* Description: Subscribe configuration for task STOP */
+
+/* Bit 31 : */
+#define I2S_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
+#define I2S_SUBSCRIBE_STOP_EN_Msk (0x1UL << I2S_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
+#define I2S_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
+#define I2S_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
+#define I2S_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define I2S_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << I2S_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: I2S_EVENTS_RXPTRUPD */
+/* Description: The RXD.PTR register has been copied to internal double-buffers.
+ When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */
+
+/* Bit 0 : The RXD.PTR register has been copied to internal double-buffers.
+ When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */
+#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos (0UL) /*!< Position of EVENTS_RXPTRUPD field. */
+#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Msk (0x1UL << I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos) /*!< Bit mask of EVENTS_RXPTRUPD field. */
+#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_NotGenerated (0UL) /*!< Event not generated */
+#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Generated (1UL) /*!< Event generated */
+
+/* Register: I2S_EVENTS_STOPPED */
+/* Description: I2S transfer stopped. */
+
+/* Bit 0 : I2S transfer stopped. */
+#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
+#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
+#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: I2S_EVENTS_TXPTRUPD */
+/* Description: The TDX.PTR register has been copied to internal double-buffers.
+ When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */
+
+/* Bit 0 : The TDX.PTR register has been copied to internal double-buffers.
+ When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */
+#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos (0UL) /*!< Position of EVENTS_TXPTRUPD field. */
+#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Msk (0x1UL << I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos) /*!< Bit mask of EVENTS_TXPTRUPD field. */
+#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_NotGenerated (0UL) /*!< Event not generated */
+#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Generated (1UL) /*!< Event generated */
+
+/* Register: I2S_PUBLISH_RXPTRUPD */
+/* Description: Publish configuration for event RXPTRUPD */
+
+/* Bit 31 : */
+#define I2S_PUBLISH_RXPTRUPD_EN_Pos (31UL) /*!< Position of EN field. */
+#define I2S_PUBLISH_RXPTRUPD_EN_Msk (0x1UL << I2S_PUBLISH_RXPTRUPD_EN_Pos) /*!< Bit mask of EN field. */
+#define I2S_PUBLISH_RXPTRUPD_EN_Disabled (0UL) /*!< Disable publishing */
+#define I2S_PUBLISH_RXPTRUPD_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event RXPTRUPD will publish to */
+#define I2S_PUBLISH_RXPTRUPD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define I2S_PUBLISH_RXPTRUPD_CHIDX_Msk (0xFFUL << I2S_PUBLISH_RXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: I2S_PUBLISH_STOPPED */
+/* Description: Publish configuration for event STOPPED */
+
+/* Bit 31 : */
+#define I2S_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
+#define I2S_PUBLISH_STOPPED_EN_Msk (0x1UL << I2S_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
+#define I2S_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
+#define I2S_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event STOPPED will publish to */
+#define I2S_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define I2S_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << I2S_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: I2S_PUBLISH_TXPTRUPD */
+/* Description: Publish configuration for event TXPTRUPD */
+
+/* Bit 31 : */
+#define I2S_PUBLISH_TXPTRUPD_EN_Pos (31UL) /*!< Position of EN field. */
+#define I2S_PUBLISH_TXPTRUPD_EN_Msk (0x1UL << I2S_PUBLISH_TXPTRUPD_EN_Pos) /*!< Bit mask of EN field. */
+#define I2S_PUBLISH_TXPTRUPD_EN_Disabled (0UL) /*!< Disable publishing */
+#define I2S_PUBLISH_TXPTRUPD_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event TXPTRUPD will publish to */
+#define I2S_PUBLISH_TXPTRUPD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define I2S_PUBLISH_TXPTRUPD_CHIDX_Msk (0xFFUL << I2S_PUBLISH_TXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: I2S_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 5 : Enable or disable interrupt for event TXPTRUPD */
+#define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
+#define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
+#define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */
+#define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for event STOPPED */
+#define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
+#define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for event RXPTRUPD */
+#define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
+#define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
+#define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */
+#define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */
+
+/* Register: I2S_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 5 : Write '1' to enable interrupt for event TXPTRUPD */
+#define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
+#define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
+#define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event STOPPED */
+#define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
+#define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event RXPTRUPD */
+#define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
+#define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
+#define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */
+
+/* Register: I2S_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 5 : Write '1' to disable interrupt for event TXPTRUPD */
+#define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
+#define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
+#define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event STOPPED */
+#define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
+#define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event RXPTRUPD */
+#define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
+#define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
+#define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */
+
+/* Register: I2S_ENABLE */
+/* Description: Enable I2S module. */
+
+/* Bit 0 : Enable I2S module. */
+#define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: I2S_CONFIG_MODE */
+/* Description: I2S mode. */
+
+/* Bit 0 : I2S mode. */
+#define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */
+#define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */
+
+/* Register: I2S_CONFIG_RXEN */
+/* Description: Reception (RX) enable. */
+
+/* Bit 0 : Reception (RX) enable. */
+#define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */
+#define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */
+#define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */
+#define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */
+
+/* Register: I2S_CONFIG_TXEN */
+/* Description: Transmission (TX) enable. */
+
+/* Bit 0 : Transmission (TX) enable. */
+#define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */
+#define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */
+#define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */
+#define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */
+
+/* Register: I2S_CONFIG_MCKEN */
+/* Description: Master clock generator enable. */
+
+/* Bit 0 : Master clock generator enable. */
+#define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */
+#define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */
+#define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */
+#define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */
+
+/* Register: I2S_CONFIG_MCKFREQ */
+/* Description: Master clock generator frequency. */
+
+/* Bits 31..0 : Master clock generator frequency. */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */
+
+/* Register: I2S_CONFIG_RATIO */
+/* Description: MCK / LRCK ratio. */
+
+/* Bits 3..0 : MCK / LRCK ratio. */
+#define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
+#define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
+#define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */
+#define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */
+#define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */
+#define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */
+#define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */
+#define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */
+#define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */
+#define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */
+#define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */
+
+/* Register: I2S_CONFIG_SWIDTH */
+/* Description: Sample width. */
+
+/* Bits 1..0 : Sample width. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */
+
+/* Register: I2S_CONFIG_ALIGN */
+/* Description: Alignment of sample within a frame. */
+
+/* Bit 0 : Alignment of sample within a frame. */
+#define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */
+#define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */
+#define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */
+#define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */
+
+/* Register: I2S_CONFIG_FORMAT */
+/* Description: Frame format. */
+
+/* Bit 0 : Frame format. */
+#define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */
+#define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */
+#define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */
+#define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */
+
+/* Register: I2S_CONFIG_CHANNELS */
+/* Description: Enable channels. */
+
+/* Bits 1..0 : Enable channels. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */
+
+/* Register: I2S_RXD_PTR */
+/* Description: Receive buffer RAM start address. */
+
+/* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */
+#define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: I2S_TXD_PTR */
+/* Description: Transmit buffer RAM start address. */
+
+/* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */
+#define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: I2S_RXTXD_MAXCNT */
+/* Description: Size of RXD and TXD buffers. */
+
+/* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */
+#define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: I2S_PSEL_MCK */
+/* Description: Pin select for MCK signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: I2S_PSEL_SCK */
+/* Description: Pin select for SCK signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: I2S_PSEL_LRCK */
+/* Description: Pin select for LRCK signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: I2S_PSEL_SDIN */
+/* Description: Pin select for SDIN signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: I2S_PSEL_SDOUT */
+/* Description: Pin select for SDOUT signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */
+
+
+/* Peripheral: IPC */
+/* Description: Interprocessor communication 0 */
+
+/* Register: IPC_TASKS_SEND */
+/* Description: Description collection: Trigger events on IPC channel enabled in SEND_CNF[n] */
+
+/* Bit 0 : Trigger events on IPC channel enabled in SEND_CNF[n] */
+#define IPC_TASKS_SEND_TASKS_SEND_Pos (0UL) /*!< Position of TASKS_SEND field. */
+#define IPC_TASKS_SEND_TASKS_SEND_Msk (0x1UL << IPC_TASKS_SEND_TASKS_SEND_Pos) /*!< Bit mask of TASKS_SEND field. */
+#define IPC_TASKS_SEND_TASKS_SEND_Trigger (1UL) /*!< Trigger task */
+
+/* Register: IPC_SUBSCRIBE_SEND */
+/* Description: Description collection: Subscribe configuration for task SEND[n] */
+
+/* Bit 31 : */
+#define IPC_SUBSCRIBE_SEND_EN_Pos (31UL) /*!< Position of EN field. */
+#define IPC_SUBSCRIBE_SEND_EN_Msk (0x1UL << IPC_SUBSCRIBE_SEND_EN_Pos) /*!< Bit mask of EN field. */
+#define IPC_SUBSCRIBE_SEND_EN_Disabled (0UL) /*!< Disable subscription */
+#define IPC_SUBSCRIBE_SEND_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task SEND[n] will subscribe to */
+#define IPC_SUBSCRIBE_SEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define IPC_SUBSCRIBE_SEND_CHIDX_Msk (0xFFUL << IPC_SUBSCRIBE_SEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: IPC_EVENTS_RECEIVE */
+/* Description: Description collection: Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] */
+
+/* Bit 0 : Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] */
+#define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos (0UL) /*!< Position of EVENTS_RECEIVE field. */
+#define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Msk (0x1UL << IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos) /*!< Bit mask of EVENTS_RECEIVE field. */
+#define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_NotGenerated (0UL) /*!< Event not generated */
+#define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Generated (1UL) /*!< Event generated */
+
+/* Register: IPC_PUBLISH_RECEIVE */
+/* Description: Description collection: Publish configuration for event RECEIVE[n] */
+
+/* Bit 31 : */
+#define IPC_PUBLISH_RECEIVE_EN_Pos (31UL) /*!< Position of EN field. */
+#define IPC_PUBLISH_RECEIVE_EN_Msk (0x1UL << IPC_PUBLISH_RECEIVE_EN_Pos) /*!< Bit mask of EN field. */
+#define IPC_PUBLISH_RECEIVE_EN_Disabled (0UL) /*!< Disable publishing */
+#define IPC_PUBLISH_RECEIVE_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event RECEIVE[n] will publish to */
+#define IPC_PUBLISH_RECEIVE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define IPC_PUBLISH_RECEIVE_CHIDX_Msk (0xFFUL << IPC_PUBLISH_RECEIVE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: IPC_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 7 : Enable or disable interrupt for event RECEIVE[7] */
+#define IPC_INTEN_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */
+#define IPC_INTEN_RECEIVE7_Msk (0x1UL << IPC_INTEN_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */
+#define IPC_INTEN_RECEIVE7_Disabled (0UL) /*!< Disable */
+#define IPC_INTEN_RECEIVE7_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for event RECEIVE[6] */
+#define IPC_INTEN_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */
+#define IPC_INTEN_RECEIVE6_Msk (0x1UL << IPC_INTEN_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */
+#define IPC_INTEN_RECEIVE6_Disabled (0UL) /*!< Disable */
+#define IPC_INTEN_RECEIVE6_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for event RECEIVE[5] */
+#define IPC_INTEN_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */
+#define IPC_INTEN_RECEIVE5_Msk (0x1UL << IPC_INTEN_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */
+#define IPC_INTEN_RECEIVE5_Disabled (0UL) /*!< Disable */
+#define IPC_INTEN_RECEIVE5_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for event RECEIVE[4] */
+#define IPC_INTEN_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */
+#define IPC_INTEN_RECEIVE4_Msk (0x1UL << IPC_INTEN_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */
+#define IPC_INTEN_RECEIVE4_Disabled (0UL) /*!< Disable */
+#define IPC_INTEN_RECEIVE4_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for event RECEIVE[3] */
+#define IPC_INTEN_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */
+#define IPC_INTEN_RECEIVE3_Msk (0x1UL << IPC_INTEN_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */
+#define IPC_INTEN_RECEIVE3_Disabled (0UL) /*!< Disable */
+#define IPC_INTEN_RECEIVE3_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for event RECEIVE[2] */
+#define IPC_INTEN_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
+#define IPC_INTEN_RECEIVE2_Msk (0x1UL << IPC_INTEN_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */
+#define IPC_INTEN_RECEIVE2_Disabled (0UL) /*!< Disable */
+#define IPC_INTEN_RECEIVE2_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for event RECEIVE[1] */
+#define IPC_INTEN_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
+#define IPC_INTEN_RECEIVE1_Msk (0x1UL << IPC_INTEN_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */
+#define IPC_INTEN_RECEIVE1_Disabled (0UL) /*!< Disable */
+#define IPC_INTEN_RECEIVE1_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for event RECEIVE[0] */
+#define IPC_INTEN_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */
+#define IPC_INTEN_RECEIVE0_Msk (0x1UL << IPC_INTEN_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */
+#define IPC_INTEN_RECEIVE0_Disabled (0UL) /*!< Disable */
+#define IPC_INTEN_RECEIVE0_Enabled (1UL) /*!< Enable */
+
+/* Register: IPC_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 7 : Write '1' to enable interrupt for event RECEIVE[7] */
+#define IPC_INTENSET_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */
+#define IPC_INTENSET_RECEIVE7_Msk (0x1UL << IPC_INTENSET_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */
+#define IPC_INTENSET_RECEIVE7_Disabled (0UL) /*!< Read: Disabled */
+#define IPC_INTENSET_RECEIVE7_Enabled (1UL) /*!< Read: Enabled */
+#define IPC_INTENSET_RECEIVE7_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to enable interrupt for event RECEIVE[6] */
+#define IPC_INTENSET_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */
+#define IPC_INTENSET_RECEIVE6_Msk (0x1UL << IPC_INTENSET_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */
+#define IPC_INTENSET_RECEIVE6_Disabled (0UL) /*!< Read: Disabled */
+#define IPC_INTENSET_RECEIVE6_Enabled (1UL) /*!< Read: Enabled */
+#define IPC_INTENSET_RECEIVE6_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to enable interrupt for event RECEIVE[5] */
+#define IPC_INTENSET_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */
+#define IPC_INTENSET_RECEIVE5_Msk (0x1UL << IPC_INTENSET_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */
+#define IPC_INTENSET_RECEIVE5_Disabled (0UL) /*!< Read: Disabled */
+#define IPC_INTENSET_RECEIVE5_Enabled (1UL) /*!< Read: Enabled */
+#define IPC_INTENSET_RECEIVE5_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to enable interrupt for event RECEIVE[4] */
+#define IPC_INTENSET_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */
+#define IPC_INTENSET_RECEIVE4_Msk (0x1UL << IPC_INTENSET_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */
+#define IPC_INTENSET_RECEIVE4_Disabled (0UL) /*!< Read: Disabled */
+#define IPC_INTENSET_RECEIVE4_Enabled (1UL) /*!< Read: Enabled */
+#define IPC_INTENSET_RECEIVE4_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to enable interrupt for event RECEIVE[3] */
+#define IPC_INTENSET_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */
+#define IPC_INTENSET_RECEIVE3_Msk (0x1UL << IPC_INTENSET_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */
+#define IPC_INTENSET_RECEIVE3_Disabled (0UL) /*!< Read: Disabled */
+#define IPC_INTENSET_RECEIVE3_Enabled (1UL) /*!< Read: Enabled */
+#define IPC_INTENSET_RECEIVE3_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event RECEIVE[2] */
+#define IPC_INTENSET_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
+#define IPC_INTENSET_RECEIVE2_Msk (0x1UL << IPC_INTENSET_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */
+#define IPC_INTENSET_RECEIVE2_Disabled (0UL) /*!< Read: Disabled */
+#define IPC_INTENSET_RECEIVE2_Enabled (1UL) /*!< Read: Enabled */
+#define IPC_INTENSET_RECEIVE2_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event RECEIVE[1] */
+#define IPC_INTENSET_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
+#define IPC_INTENSET_RECEIVE1_Msk (0x1UL << IPC_INTENSET_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */
+#define IPC_INTENSET_RECEIVE1_Disabled (0UL) /*!< Read: Disabled */
+#define IPC_INTENSET_RECEIVE1_Enabled (1UL) /*!< Read: Enabled */
+#define IPC_INTENSET_RECEIVE1_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event RECEIVE[0] */
+#define IPC_INTENSET_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */
+#define IPC_INTENSET_RECEIVE0_Msk (0x1UL << IPC_INTENSET_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */
+#define IPC_INTENSET_RECEIVE0_Disabled (0UL) /*!< Read: Disabled */
+#define IPC_INTENSET_RECEIVE0_Enabled (1UL) /*!< Read: Enabled */
+#define IPC_INTENSET_RECEIVE0_Set (1UL) /*!< Enable */
+
+/* Register: IPC_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 7 : Write '1' to disable interrupt for event RECEIVE[7] */
+#define IPC_INTENCLR_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */
+#define IPC_INTENCLR_RECEIVE7_Msk (0x1UL << IPC_INTENCLR_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */
+#define IPC_INTENCLR_RECEIVE7_Disabled (0UL) /*!< Read: Disabled */
+#define IPC_INTENCLR_RECEIVE7_Enabled (1UL) /*!< Read: Enabled */
+#define IPC_INTENCLR_RECEIVE7_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to disable interrupt for event RECEIVE[6] */
+#define IPC_INTENCLR_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */
+#define IPC_INTENCLR_RECEIVE6_Msk (0x1UL << IPC_INTENCLR_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */
+#define IPC_INTENCLR_RECEIVE6_Disabled (0UL) /*!< Read: Disabled */
+#define IPC_INTENCLR_RECEIVE6_Enabled (1UL) /*!< Read: Enabled */
+#define IPC_INTENCLR_RECEIVE6_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to disable interrupt for event RECEIVE[5] */
+#define IPC_INTENCLR_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */
+#define IPC_INTENCLR_RECEIVE5_Msk (0x1UL << IPC_INTENCLR_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */
+#define IPC_INTENCLR_RECEIVE5_Disabled (0UL) /*!< Read: Disabled */
+#define IPC_INTENCLR_RECEIVE5_Enabled (1UL) /*!< Read: Enabled */
+#define IPC_INTENCLR_RECEIVE5_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to disable interrupt for event RECEIVE[4] */
+#define IPC_INTENCLR_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */
+#define IPC_INTENCLR_RECEIVE4_Msk (0x1UL << IPC_INTENCLR_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */
+#define IPC_INTENCLR_RECEIVE4_Disabled (0UL) /*!< Read: Disabled */
+#define IPC_INTENCLR_RECEIVE4_Enabled (1UL) /*!< Read: Enabled */
+#define IPC_INTENCLR_RECEIVE4_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to disable interrupt for event RECEIVE[3] */
+#define IPC_INTENCLR_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */
+#define IPC_INTENCLR_RECEIVE3_Msk (0x1UL << IPC_INTENCLR_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */
+#define IPC_INTENCLR_RECEIVE3_Disabled (0UL) /*!< Read: Disabled */
+#define IPC_INTENCLR_RECEIVE3_Enabled (1UL) /*!< Read: Enabled */
+#define IPC_INTENCLR_RECEIVE3_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event RECEIVE[2] */
+#define IPC_INTENCLR_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
+#define IPC_INTENCLR_RECEIVE2_Msk (0x1UL << IPC_INTENCLR_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */
+#define IPC_INTENCLR_RECEIVE2_Disabled (0UL) /*!< Read: Disabled */
+#define IPC_INTENCLR_RECEIVE2_Enabled (1UL) /*!< Read: Enabled */
+#define IPC_INTENCLR_RECEIVE2_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event RECEIVE[1] */
+#define IPC_INTENCLR_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
+#define IPC_INTENCLR_RECEIVE1_Msk (0x1UL << IPC_INTENCLR_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */
+#define IPC_INTENCLR_RECEIVE1_Disabled (0UL) /*!< Read: Disabled */
+#define IPC_INTENCLR_RECEIVE1_Enabled (1UL) /*!< Read: Enabled */
+#define IPC_INTENCLR_RECEIVE1_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event RECEIVE[0] */
+#define IPC_INTENCLR_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */
+#define IPC_INTENCLR_RECEIVE0_Msk (0x1UL << IPC_INTENCLR_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */
+#define IPC_INTENCLR_RECEIVE0_Disabled (0UL) /*!< Read: Disabled */
+#define IPC_INTENCLR_RECEIVE0_Enabled (1UL) /*!< Read: Enabled */
+#define IPC_INTENCLR_RECEIVE0_Clear (1UL) /*!< Disable */
+
+/* Register: IPC_INTPEND */
+/* Description: Pending interrupts */
+
+/* Bit 7 : Read pending status of interrupt for event RECEIVE[7] */
+#define IPC_INTPEND_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */
+#define IPC_INTPEND_RECEIVE7_Msk (0x1UL << IPC_INTPEND_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */
+#define IPC_INTPEND_RECEIVE7_NotPending (0UL) /*!< Read: Not pending */
+#define IPC_INTPEND_RECEIVE7_Pending (1UL) /*!< Read: Pending */
+
+/* Bit 6 : Read pending status of interrupt for event RECEIVE[6] */
+#define IPC_INTPEND_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */
+#define IPC_INTPEND_RECEIVE6_Msk (0x1UL << IPC_INTPEND_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */
+#define IPC_INTPEND_RECEIVE6_NotPending (0UL) /*!< Read: Not pending */
+#define IPC_INTPEND_RECEIVE6_Pending (1UL) /*!< Read: Pending */
+
+/* Bit 5 : Read pending status of interrupt for event RECEIVE[5] */
+#define IPC_INTPEND_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */
+#define IPC_INTPEND_RECEIVE5_Msk (0x1UL << IPC_INTPEND_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */
+#define IPC_INTPEND_RECEIVE5_NotPending (0UL) /*!< Read: Not pending */
+#define IPC_INTPEND_RECEIVE5_Pending (1UL) /*!< Read: Pending */
+
+/* Bit 4 : Read pending status of interrupt for event RECEIVE[4] */
+#define IPC_INTPEND_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */
+#define IPC_INTPEND_RECEIVE4_Msk (0x1UL << IPC_INTPEND_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */
+#define IPC_INTPEND_RECEIVE4_NotPending (0UL) /*!< Read: Not pending */
+#define IPC_INTPEND_RECEIVE4_Pending (1UL) /*!< Read: Pending */
+
+/* Bit 3 : Read pending status of interrupt for event RECEIVE[3] */
+#define IPC_INTPEND_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */
+#define IPC_INTPEND_RECEIVE3_Msk (0x1UL << IPC_INTPEND_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */
+#define IPC_INTPEND_RECEIVE3_NotPending (0UL) /*!< Read: Not pending */
+#define IPC_INTPEND_RECEIVE3_Pending (1UL) /*!< Read: Pending */
+
+/* Bit 2 : Read pending status of interrupt for event RECEIVE[2] */
+#define IPC_INTPEND_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
+#define IPC_INTPEND_RECEIVE2_Msk (0x1UL << IPC_INTPEND_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */
+#define IPC_INTPEND_RECEIVE2_NotPending (0UL) /*!< Read: Not pending */
+#define IPC_INTPEND_RECEIVE2_Pending (1UL) /*!< Read: Pending */
+
+/* Bit 1 : Read pending status of interrupt for event RECEIVE[1] */
+#define IPC_INTPEND_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
+#define IPC_INTPEND_RECEIVE1_Msk (0x1UL << IPC_INTPEND_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */
+#define IPC_INTPEND_RECEIVE1_NotPending (0UL) /*!< Read: Not pending */
+#define IPC_INTPEND_RECEIVE1_Pending (1UL) /*!< Read: Pending */
+
+/* Bit 0 : Read pending status of interrupt for event RECEIVE[0] */
+#define IPC_INTPEND_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */
+#define IPC_INTPEND_RECEIVE0_Msk (0x1UL << IPC_INTPEND_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */
+#define IPC_INTPEND_RECEIVE0_NotPending (0UL) /*!< Read: Not pending */
+#define IPC_INTPEND_RECEIVE0_Pending (1UL) /*!< Read: Pending */
+
+/* Register: IPC_SEND_CNF */
+/* Description: Description collection: Send event configuration for TASKS_SEND[n] */
+
+/* Bit 7 : Enable broadcasting on IPC channel 7 */
+#define IPC_SEND_CNF_CHEN7_Pos (7UL) /*!< Position of CHEN7 field. */
+#define IPC_SEND_CNF_CHEN7_Msk (0x1UL << IPC_SEND_CNF_CHEN7_Pos) /*!< Bit mask of CHEN7 field. */
+#define IPC_SEND_CNF_CHEN7_Disable (0UL) /*!< Disable broadcast */
+#define IPC_SEND_CNF_CHEN7_Enable (1UL) /*!< Enable broadcast */
+
+/* Bit 6 : Enable broadcasting on IPC channel 6 */
+#define IPC_SEND_CNF_CHEN6_Pos (6UL) /*!< Position of CHEN6 field. */
+#define IPC_SEND_CNF_CHEN6_Msk (0x1UL << IPC_SEND_CNF_CHEN6_Pos) /*!< Bit mask of CHEN6 field. */
+#define IPC_SEND_CNF_CHEN6_Disable (0UL) /*!< Disable broadcast */
+#define IPC_SEND_CNF_CHEN6_Enable (1UL) /*!< Enable broadcast */
+
+/* Bit 5 : Enable broadcasting on IPC channel 5 */
+#define IPC_SEND_CNF_CHEN5_Pos (5UL) /*!< Position of CHEN5 field. */
+#define IPC_SEND_CNF_CHEN5_Msk (0x1UL << IPC_SEND_CNF_CHEN5_Pos) /*!< Bit mask of CHEN5 field. */
+#define IPC_SEND_CNF_CHEN5_Disable (0UL) /*!< Disable broadcast */
+#define IPC_SEND_CNF_CHEN5_Enable (1UL) /*!< Enable broadcast */
+
+/* Bit 4 : Enable broadcasting on IPC channel 4 */
+#define IPC_SEND_CNF_CHEN4_Pos (4UL) /*!< Position of CHEN4 field. */
+#define IPC_SEND_CNF_CHEN4_Msk (0x1UL << IPC_SEND_CNF_CHEN4_Pos) /*!< Bit mask of CHEN4 field. */
+#define IPC_SEND_CNF_CHEN4_Disable (0UL) /*!< Disable broadcast */
+#define IPC_SEND_CNF_CHEN4_Enable (1UL) /*!< Enable broadcast */
+
+/* Bit 3 : Enable broadcasting on IPC channel 3 */
+#define IPC_SEND_CNF_CHEN3_Pos (3UL) /*!< Position of CHEN3 field. */
+#define IPC_SEND_CNF_CHEN3_Msk (0x1UL << IPC_SEND_CNF_CHEN3_Pos) /*!< Bit mask of CHEN3 field. */
+#define IPC_SEND_CNF_CHEN3_Disable (0UL) /*!< Disable broadcast */
+#define IPC_SEND_CNF_CHEN3_Enable (1UL) /*!< Enable broadcast */
+
+/* Bit 2 : Enable broadcasting on IPC channel 2 */
+#define IPC_SEND_CNF_CHEN2_Pos (2UL) /*!< Position of CHEN2 field. */
+#define IPC_SEND_CNF_CHEN2_Msk (0x1UL << IPC_SEND_CNF_CHEN2_Pos) /*!< Bit mask of CHEN2 field. */
+#define IPC_SEND_CNF_CHEN2_Disable (0UL) /*!< Disable broadcast */
+#define IPC_SEND_CNF_CHEN2_Enable (1UL) /*!< Enable broadcast */
+
+/* Bit 1 : Enable broadcasting on IPC channel 1 */
+#define IPC_SEND_CNF_CHEN1_Pos (1UL) /*!< Position of CHEN1 field. */
+#define IPC_SEND_CNF_CHEN1_Msk (0x1UL << IPC_SEND_CNF_CHEN1_Pos) /*!< Bit mask of CHEN1 field. */
+#define IPC_SEND_CNF_CHEN1_Disable (0UL) /*!< Disable broadcast */
+#define IPC_SEND_CNF_CHEN1_Enable (1UL) /*!< Enable broadcast */
+
+/* Bit 0 : Enable broadcasting on IPC channel 0 */
+#define IPC_SEND_CNF_CHEN0_Pos (0UL) /*!< Position of CHEN0 field. */
+#define IPC_SEND_CNF_CHEN0_Msk (0x1UL << IPC_SEND_CNF_CHEN0_Pos) /*!< Bit mask of CHEN0 field. */
+#define IPC_SEND_CNF_CHEN0_Disable (0UL) /*!< Disable broadcast */
+#define IPC_SEND_CNF_CHEN0_Enable (1UL) /*!< Enable broadcast */
+
+/* Register: IPC_RECEIVE_CNF */
+/* Description: Description collection: Receive event configuration for EVENTS_RECEIVE[n] */
+
+/* Bit 7 : Enable subscription to IPC channel 7 */
+#define IPC_RECEIVE_CNF_CHEN7_Pos (7UL) /*!< Position of CHEN7 field. */
+#define IPC_RECEIVE_CNF_CHEN7_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN7_Pos) /*!< Bit mask of CHEN7 field. */
+#define IPC_RECEIVE_CNF_CHEN7_Disable (0UL) /*!< Disable events */
+#define IPC_RECEIVE_CNF_CHEN7_Enable (1UL) /*!< Enable events */
+
+/* Bit 6 : Enable subscription to IPC channel 6 */
+#define IPC_RECEIVE_CNF_CHEN6_Pos (6UL) /*!< Position of CHEN6 field. */
+#define IPC_RECEIVE_CNF_CHEN6_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN6_Pos) /*!< Bit mask of CHEN6 field. */
+#define IPC_RECEIVE_CNF_CHEN6_Disable (0UL) /*!< Disable events */
+#define IPC_RECEIVE_CNF_CHEN6_Enable (1UL) /*!< Enable events */
+
+/* Bit 5 : Enable subscription to IPC channel 5 */
+#define IPC_RECEIVE_CNF_CHEN5_Pos (5UL) /*!< Position of CHEN5 field. */
+#define IPC_RECEIVE_CNF_CHEN5_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN5_Pos) /*!< Bit mask of CHEN5 field. */
+#define IPC_RECEIVE_CNF_CHEN5_Disable (0UL) /*!< Disable events */
+#define IPC_RECEIVE_CNF_CHEN5_Enable (1UL) /*!< Enable events */
+
+/* Bit 4 : Enable subscription to IPC channel 4 */
+#define IPC_RECEIVE_CNF_CHEN4_Pos (4UL) /*!< Position of CHEN4 field. */
+#define IPC_RECEIVE_CNF_CHEN4_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN4_Pos) /*!< Bit mask of CHEN4 field. */
+#define IPC_RECEIVE_CNF_CHEN4_Disable (0UL) /*!< Disable events */
+#define IPC_RECEIVE_CNF_CHEN4_Enable (1UL) /*!< Enable events */
+
+/* Bit 3 : Enable subscription to IPC channel 3 */
+#define IPC_RECEIVE_CNF_CHEN3_Pos (3UL) /*!< Position of CHEN3 field. */
+#define IPC_RECEIVE_CNF_CHEN3_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN3_Pos) /*!< Bit mask of CHEN3 field. */
+#define IPC_RECEIVE_CNF_CHEN3_Disable (0UL) /*!< Disable events */
+#define IPC_RECEIVE_CNF_CHEN3_Enable (1UL) /*!< Enable events */
+
+/* Bit 2 : Enable subscription to IPC channel 2 */
+#define IPC_RECEIVE_CNF_CHEN2_Pos (2UL) /*!< Position of CHEN2 field. */
+#define IPC_RECEIVE_CNF_CHEN2_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN2_Pos) /*!< Bit mask of CHEN2 field. */
+#define IPC_RECEIVE_CNF_CHEN2_Disable (0UL) /*!< Disable events */
+#define IPC_RECEIVE_CNF_CHEN2_Enable (1UL) /*!< Enable events */
+
+/* Bit 1 : Enable subscription to IPC channel 1 */
+#define IPC_RECEIVE_CNF_CHEN1_Pos (1UL) /*!< Position of CHEN1 field. */
+#define IPC_RECEIVE_CNF_CHEN1_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN1_Pos) /*!< Bit mask of CHEN1 field. */
+#define IPC_RECEIVE_CNF_CHEN1_Disable (0UL) /*!< Disable events */
+#define IPC_RECEIVE_CNF_CHEN1_Enable (1UL) /*!< Enable events */
+
+/* Bit 0 : Enable subscription to IPC channel 0 */
+#define IPC_RECEIVE_CNF_CHEN0_Pos (0UL) /*!< Position of CHEN0 field. */
+#define IPC_RECEIVE_CNF_CHEN0_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN0_Pos) /*!< Bit mask of CHEN0 field. */
+#define IPC_RECEIVE_CNF_CHEN0_Disable (0UL) /*!< Disable events */
+#define IPC_RECEIVE_CNF_CHEN0_Enable (1UL) /*!< Enable events */
+
+/* Register: IPC_GPMEM */
+/* Description: Description collection: General purpose memory */
+
+/* Bits 31..0 : General purpose memory */
+#define IPC_GPMEM_GPMEM_Pos (0UL) /*!< Position of GPMEM field. */
+#define IPC_GPMEM_GPMEM_Msk (0xFFFFFFFFUL << IPC_GPMEM_GPMEM_Pos) /*!< Bit mask of GPMEM field. */
+
+
+/* Peripheral: KMU */
+/* Description: Key management unit 0 */
+
+/* Register: KMU_TASKS_PUSH_KEYSLOT */
+/* Description: Push a key slot over secure APB */
+
+/* Bit 0 : Push a key slot over secure APB */
+#define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Pos (0UL) /*!< Position of TASKS_PUSH_KEYSLOT field. */
+#define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Msk (0x1UL << KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Pos) /*!< Bit mask of TASKS_PUSH_KEYSLOT field. */
+#define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Trigger (1UL) /*!< Trigger task */
+
+/* Register: KMU_EVENTS_KEYSLOT_PUSHED */
+/* Description: Key slot successfully pushed over secure APB */
+
+/* Bit 0 : Key slot successfully pushed over secure APB */
+#define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_PUSHED field. */
+#define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Msk (0x1UL << KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Pos) /*!< Bit mask of EVENTS_KEYSLOT_PUSHED field. */
+#define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_NotGenerated (0UL) /*!< Event not generated */
+#define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Generated (1UL) /*!< Event generated */
+
+/* Register: KMU_EVENTS_KEYSLOT_REVOKED */
+/* Description: Key slot has been revoked and cannot be tasked for selection */
+
+/* Bit 0 : Key slot has been revoked and cannot be tasked for selection */
+#define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_REVOKED field. */
+#define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Msk (0x1UL << KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Pos) /*!< Bit mask of EVENTS_KEYSLOT_REVOKED field. */
+#define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_NotGenerated (0UL) /*!< Event not generated */
+#define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Generated (1UL) /*!< Event generated */
+
+/* Register: KMU_EVENTS_KEYSLOT_ERROR */
+/* Description: No key slot selected, no destination address defined, or error during push operation */
+
+/* Bit 0 : No key slot selected, no destination address defined, or error during push operation */
+#define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_ERROR field. */
+#define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Msk (0x1UL << KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Pos) /*!< Bit mask of EVENTS_KEYSLOT_ERROR field. */
+#define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_NotGenerated (0UL) /*!< Event not generated */
+#define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Generated (1UL) /*!< Event generated */
+
+/* Register: KMU_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 2 : Enable or disable interrupt for event KEYSLOT_ERROR */
+#define KMU_INTEN_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */
+#define KMU_INTEN_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTEN_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */
+#define KMU_INTEN_KEYSLOT_ERROR_Disabled (0UL) /*!< Disable */
+#define KMU_INTEN_KEYSLOT_ERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for event KEYSLOT_REVOKED */
+#define KMU_INTEN_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */
+#define KMU_INTEN_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTEN_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */
+#define KMU_INTEN_KEYSLOT_REVOKED_Disabled (0UL) /*!< Disable */
+#define KMU_INTEN_KEYSLOT_REVOKED_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for event KEYSLOT_PUSHED */
+#define KMU_INTEN_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */
+#define KMU_INTEN_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTEN_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */
+#define KMU_INTEN_KEYSLOT_PUSHED_Disabled (0UL) /*!< Disable */
+#define KMU_INTEN_KEYSLOT_PUSHED_Enabled (1UL) /*!< Enable */
+
+/* Register: KMU_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 2 : Write '1' to enable interrupt for event KEYSLOT_ERROR */
+#define KMU_INTENSET_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */
+#define KMU_INTENSET_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTENSET_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */
+#define KMU_INTENSET_KEYSLOT_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define KMU_INTENSET_KEYSLOT_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define KMU_INTENSET_KEYSLOT_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event KEYSLOT_REVOKED */
+#define KMU_INTENSET_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */
+#define KMU_INTENSET_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTENSET_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */
+#define KMU_INTENSET_KEYSLOT_REVOKED_Disabled (0UL) /*!< Read: Disabled */
+#define KMU_INTENSET_KEYSLOT_REVOKED_Enabled (1UL) /*!< Read: Enabled */
+#define KMU_INTENSET_KEYSLOT_REVOKED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event KEYSLOT_PUSHED */
+#define KMU_INTENSET_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */
+#define KMU_INTENSET_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTENSET_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */
+#define KMU_INTENSET_KEYSLOT_PUSHED_Disabled (0UL) /*!< Read: Disabled */
+#define KMU_INTENSET_KEYSLOT_PUSHED_Enabled (1UL) /*!< Read: Enabled */
+#define KMU_INTENSET_KEYSLOT_PUSHED_Set (1UL) /*!< Enable */
+
+/* Register: KMU_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 2 : Write '1' to disable interrupt for event KEYSLOT_ERROR */
+#define KMU_INTENCLR_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */
+#define KMU_INTENCLR_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */
+#define KMU_INTENCLR_KEYSLOT_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define KMU_INTENCLR_KEYSLOT_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define KMU_INTENCLR_KEYSLOT_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event KEYSLOT_REVOKED */
+#define KMU_INTENCLR_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */
+#define KMU_INTENCLR_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */
+#define KMU_INTENCLR_KEYSLOT_REVOKED_Disabled (0UL) /*!< Read: Disabled */
+#define KMU_INTENCLR_KEYSLOT_REVOKED_Enabled (1UL) /*!< Read: Enabled */
+#define KMU_INTENCLR_KEYSLOT_REVOKED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event KEYSLOT_PUSHED */
+#define KMU_INTENCLR_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */
+#define KMU_INTENCLR_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */
+#define KMU_INTENCLR_KEYSLOT_PUSHED_Disabled (0UL) /*!< Read: Disabled */
+#define KMU_INTENCLR_KEYSLOT_PUSHED_Enabled (1UL) /*!< Read: Enabled */
+#define KMU_INTENCLR_KEYSLOT_PUSHED_Clear (1UL) /*!< Disable */
+
+/* Register: KMU_INTPEND */
+/* Description: Pending interrupts */
+
+/* Bit 2 : Read pending status of interrupt for event KEYSLOT_ERROR */
+#define KMU_INTPEND_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */
+#define KMU_INTPEND_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTPEND_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */
+#define KMU_INTPEND_KEYSLOT_ERROR_NotPending (0UL) /*!< Read: Not pending */
+#define KMU_INTPEND_KEYSLOT_ERROR_Pending (1UL) /*!< Read: Pending */
+
+/* Bit 1 : Read pending status of interrupt for event KEYSLOT_REVOKED */
+#define KMU_INTPEND_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */
+#define KMU_INTPEND_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTPEND_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */
+#define KMU_INTPEND_KEYSLOT_REVOKED_NotPending (0UL) /*!< Read: Not pending */
+#define KMU_INTPEND_KEYSLOT_REVOKED_Pending (1UL) /*!< Read: Pending */
+
+/* Bit 0 : Read pending status of interrupt for event KEYSLOT_PUSHED */
+#define KMU_INTPEND_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */
+#define KMU_INTPEND_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTPEND_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */
+#define KMU_INTPEND_KEYSLOT_PUSHED_NotPending (0UL) /*!< Read: Not pending */
+#define KMU_INTPEND_KEYSLOT_PUSHED_Pending (1UL) /*!< Read: Pending */
+
+/* Register: KMU_STATUS */
+/* Description: Status bits for KMU operation */
+
+/* Bit 1 : Violation status */
+#define KMU_STATUS_BLOCKED_Pos (1UL) /*!< Position of BLOCKED field. */
+#define KMU_STATUS_BLOCKED_Msk (0x1UL << KMU_STATUS_BLOCKED_Pos) /*!< Bit mask of BLOCKED field. */
+#define KMU_STATUS_BLOCKED_Disabled (0UL) /*!< No access violation detected */
+#define KMU_STATUS_BLOCKED_Enabled (1UL) /*!< Access violation detected and blocked */
+
+/* Bit 0 : Key slot ID successfully selected by the KMU */
+#define KMU_STATUS_SELECTED_Pos (0UL) /*!< Position of SELECTED field. */
+#define KMU_STATUS_SELECTED_Msk (0x1UL << KMU_STATUS_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
+#define KMU_STATUS_SELECTED_Disabled (0UL) /*!< No key slot ID selected by KMU */
+#define KMU_STATUS_SELECTED_Enabled (1UL) /*!< Key slot ID successfully selected by KMU */
+
+/* Register: KMU_SELECTKEYSLOT */
+/* Description: Select key slot to be read over AHB or pushed over secure APB when TASKS_PUSH_KEYSLOT is started */
+
+/* Bits 7..0 : Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started. NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use. NOTE: Index N in UICR->KEYSLOT.KEY[N] and UICR->KEYSLOT.CONFIG[N] corresponds to KMU key slot ID=N+1. */
+#define KMU_SELECTKEYSLOT_ID_Pos (0UL) /*!< Position of ID field. */
+#define KMU_SELECTKEYSLOT_ID_Msk (0xFFUL << KMU_SELECTKEYSLOT_ID_Pos) /*!< Bit mask of ID field. */
+
+
+/* Peripheral: NVMC */
+/* Description: Non-volatile memory controller 0 */
+
+/* Register: NVMC_READY */
+/* Description: Ready flag */
+
+/* Bit 0 : NVMC is ready or busy */
+#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
+#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
+#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */
+#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */
+
+/* Register: NVMC_READYNEXT */
+/* Description: Ready flag */
+
+/* Bit 0 : NVMC can accept a new write operation */
+#define NVMC_READYNEXT_READYNEXT_Pos (0UL) /*!< Position of READYNEXT field. */
+#define NVMC_READYNEXT_READYNEXT_Msk (0x1UL << NVMC_READYNEXT_READYNEXT_Pos) /*!< Bit mask of READYNEXT field. */
+#define NVMC_READYNEXT_READYNEXT_Busy (0UL) /*!< NVMC cannot accept any write operation */
+#define NVMC_READYNEXT_READYNEXT_Ready (1UL) /*!< NVMC is ready */
+
+/* Register: NVMC_CONFIG */
+/* Description: Configuration register */
+
+/* Bits 2..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */
+#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
+#define NVMC_CONFIG_WEN_Msk (0x7UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
+#define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
+#define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */
+#define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
+#define NVMC_CONFIG_WEN_PEen (4UL) /*!< Partial erase enabled */
+
+/* Register: NVMC_ERASEALL */
+/* Description: Register for erasing all non-volatile user memory */
+
+/* Bit 0 : Erase all non-volatile memory including UICR registers. Note that erasing must be enabled by setting CONFIG.WEN = Een before the non-volatile memory can be erased. */
+#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
+#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
+#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */
+#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */
+
+/* Register: NVMC_ERASEPAGEPARTIALCFG */
+/* Description: Register for partial erase configuration */
+
+/* Bits 6..0 : Duration of the partial erase in milliseconds */
+#define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL) /*!< Position of DURATION field. */
+#define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */
+
+/* Register: NVMC_ICACHECNF */
+/* Description: I-code cache configuration register */
+
+/* Bit 8 : Cache profiling enable */
+#define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */
+#define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */
+#define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */
+#define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */
+
+/* Bit 0 : Cache enable */
+#define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */
+#define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */
+#define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */
+#define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */
+
+/* Register: NVMC_IHIT */
+/* Description: I-code cache hit counter */
+
+/* Bits 31..0 : Number of cache hits Write zero to clear */
+#define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */
+#define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */
+
+/* Register: NVMC_IMISS */
+/* Description: I-code cache miss counter */
+
+/* Bits 31..0 : Number of cache misses Write zero to clear */
+#define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */
+#define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */
+
+/* Register: NVMC_CONFIGNS */
+/* Description: Unspecified */
+
+/* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */
+#define NVMC_CONFIGNS_WEN_Pos (0UL) /*!< Position of WEN field. */
+#define NVMC_CONFIGNS_WEN_Msk (0x3UL << NVMC_CONFIGNS_WEN_Pos) /*!< Bit mask of WEN field. */
+#define NVMC_CONFIGNS_WEN_Ren (0UL) /*!< Read only access */
+#define NVMC_CONFIGNS_WEN_Wen (1UL) /*!< Write enabled */
+#define NVMC_CONFIGNS_WEN_Een (2UL) /*!< Erase enabled */
+
+/* Register: NVMC_WRITEUICRNS */
+/* Description: Non-secure APPROTECT enable register */
+
+/* Bits 31..4 : Key to write in order to validate the write operation */
+#define NVMC_WRITEUICRNS_KEY_Pos (4UL) /*!< Position of KEY field. */
+#define NVMC_WRITEUICRNS_KEY_Msk (0xFFFFFFFUL << NVMC_WRITEUICRNS_KEY_Pos) /*!< Bit mask of KEY field. */
+#define NVMC_WRITEUICRNS_KEY_Keyvalid (0xAFBE5A7UL) /*!< Key value */
+
+/* Bit 0 : Allow non-secure code to set APPROTECT */
+#define NVMC_WRITEUICRNS_SET_Pos (0UL) /*!< Position of SET field. */
+#define NVMC_WRITEUICRNS_SET_Msk (0x1UL << NVMC_WRITEUICRNS_SET_Pos) /*!< Bit mask of SET field. */
+#define NVMC_WRITEUICRNS_SET_Set (1UL) /*!< Set value */
+
+
+/* Peripheral: GPIO */
+/* Description: GPIO Port 0 */
+
+/* Register: GPIO_OUT */
+/* Description: Write GPIO port */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */
+
+/* Register: GPIO_OUTSET */
+/* Description: Set individual bits in GPIO port */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Register: GPIO_OUTCLR */
+/* Description: Clear individual bits in GPIO port */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Register: GPIO_IN */
+/* Description: Read GPIO port */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */
+
+/* Register: GPIO_DIR */
+/* Description: Direction of GPIO pins */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */
+
+/* Register: GPIO_DIRSET */
+/* Description: DIR set register */
+
+/* Bit 31 : Set as output pin 31 */
+#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 30 : Set as output pin 30 */
+#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 29 : Set as output pin 29 */
+#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 28 : Set as output pin 28 */
+#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 27 : Set as output pin 27 */
+#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 26 : Set as output pin 26 */
+#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 25 : Set as output pin 25 */
+#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 24 : Set as output pin 24 */
+#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 23 : Set as output pin 23 */
+#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 22 : Set as output pin 22 */
+#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 21 : Set as output pin 21 */
+#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 20 : Set as output pin 20 */
+#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 19 : Set as output pin 19 */
+#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 18 : Set as output pin 18 */
+#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 17 : Set as output pin 17 */
+#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 16 : Set as output pin 16 */
+#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 15 : Set as output pin 15 */
+#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 14 : Set as output pin 14 */
+#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 13 : Set as output pin 13 */
+#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 12 : Set as output pin 12 */
+#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 11 : Set as output pin 11 */
+#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 10 : Set as output pin 10 */
+#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 9 : Set as output pin 9 */
+#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 8 : Set as output pin 8 */
+#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 7 : Set as output pin 7 */
+#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 6 : Set as output pin 6 */
+#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 5 : Set as output pin 5 */
+#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 4 : Set as output pin 4 */
+#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 3 : Set as output pin 3 */
+#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 2 : Set as output pin 2 */
+#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 1 : Set as output pin 1 */
+#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 0 : Set as output pin 0 */
+#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Register: GPIO_DIRCLR */
+/* Description: DIR clear register */
+
+/* Bit 31 : Set as input pin 31 */
+#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 30 : Set as input pin 30 */
+#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 29 : Set as input pin 29 */
+#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 28 : Set as input pin 28 */
+#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 27 : Set as input pin 27 */
+#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 26 : Set as input pin 26 */
+#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 25 : Set as input pin 25 */
+#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 24 : Set as input pin 24 */
+#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 23 : Set as input pin 23 */
+#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 22 : Set as input pin 22 */
+#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 21 : Set as input pin 21 */
+#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 20 : Set as input pin 20 */
+#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 19 : Set as input pin 19 */
+#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 18 : Set as input pin 18 */
+#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 17 : Set as input pin 17 */
+#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 16 : Set as input pin 16 */
+#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 15 : Set as input pin 15 */
+#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 14 : Set as input pin 14 */
+#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 13 : Set as input pin 13 */
+#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 12 : Set as input pin 12 */
+#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 11 : Set as input pin 11 */
+#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 10 : Set as input pin 10 */
+#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 9 : Set as input pin 9 */
+#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 8 : Set as input pin 8 */
+#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 7 : Set as input pin 7 */
+#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 6 : Set as input pin 6 */
+#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 5 : Set as input pin 5 */
+#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 4 : Set as input pin 4 */
+#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 3 : Set as input pin 3 */
+#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 2 : Set as input pin 2 */
+#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 1 : Set as input pin 1 */
+#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 0 : Set as input pin 0 */
+#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Register: GPIO_LATCH */
+/* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */
+
+/* Bit 31 : Status on whether PIN[31] has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 30 : Status on whether PIN[30] has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 29 : Status on whether PIN[29] has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 28 : Status on whether PIN[28] has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 27 : Status on whether PIN[27] has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 26 : Status on whether PIN[26] has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 25 : Status on whether PIN[25] has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 24 : Status on whether PIN[24] has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 23 : Status on whether PIN[23] has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 22 : Status on whether PIN[22] has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 21 : Status on whether PIN[21] has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 20 : Status on whether PIN[20] has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 19 : Status on whether PIN[19] has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 18 : Status on whether PIN[18] has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 17 : Status on whether PIN[17] has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 16 : Status on whether PIN[16] has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 15 : Status on whether PIN[15] has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 14 : Status on whether PIN[14] has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 13 : Status on whether PIN[13] has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 12 : Status on whether PIN[12] has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 11 : Status on whether PIN[11] has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 10 : Status on whether PIN[10] has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 9 : Status on whether PIN[9] has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 8 : Status on whether PIN[8] has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 7 : Status on whether PIN[7] has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 6 : Status on whether PIN[6] has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 5 : Status on whether PIN[5] has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 4 : Status on whether PIN[4] has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 3 : Status on whether PIN[3] has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 2 : Status on whether PIN[2] has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 1 : Status on whether PIN[1] has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 0 : Status on whether PIN[0] has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */
+
+/* Register: GPIO_DETECTMODE */
+/* Description: Select between default DETECT signal behavior and LDETECT mode (For non-secure pin only) */
+
+/* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */
+#define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
+#define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
+#define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
+#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behavior */
+
+/* Register: GPIO_DETECTMODE_SEC */
+/* Description: Select between default DETECT signal behavior and LDETECT mode (For secure pin only) */
+
+/* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */
+#define GPIO_DETECTMODE_SEC_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
+#define GPIO_DETECTMODE_SEC_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_SEC_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
+#define GPIO_DETECTMODE_SEC_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
+#define GPIO_DETECTMODE_SEC_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behavior */
+
+/* Register: GPIO_PIN_CNF */
+/* Description: Description collection: Configuration of GPIO pins */
+
+/* Bits 17..16 : Pin sensing mechanism */
+#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
+#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
+#define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
+#define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
+#define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */
+
+/* Bits 10..8 : Drive configuration */
+#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
+#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
+#define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */
+#define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
+#define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
+#define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
+#define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0', standard '1' (normally used for wired-or connections) */
+#define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */
+#define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0', disconnect '1' (normally used for wired-and connections) */
+#define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */
+
+/* Bits 3..2 : Pull configuration */
+#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
+#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
+#define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */
+#define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */
+#define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */
+
+/* Bit 1 : Connect or disconnect input buffer */
+#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
+#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
+#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */
+#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */
+
+/* Bit 0 : Pin direction. Same physical register as DIR register */
+#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
+#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
+#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */
+#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */
+
+
+/* Peripheral: PDM */
+/* Description: Pulse Density Modulation (Digital Microphone) Interface 0 */
+
+/* Register: PDM_TASKS_START */
+/* Description: Starts continuous PDM transfer */
+
+/* Bit 0 : Starts continuous PDM transfer */
+#define PDM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define PDM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: PDM_TASKS_STOP */
+/* Description: Stops PDM transfer */
+
+/* Bit 0 : Stops PDM transfer */
+#define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define PDM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: PDM_SUBSCRIBE_START */
+/* Description: Subscribe configuration for task START */
+
+/* Bit 31 : */
+#define PDM_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
+#define PDM_SUBSCRIBE_START_EN_Msk (0x1UL << PDM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
+#define PDM_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
+#define PDM_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task START will subscribe to */
+#define PDM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define PDM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << PDM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: PDM_SUBSCRIBE_STOP */
+/* Description: Subscribe configuration for task STOP */
+
+/* Bit 31 : */
+#define PDM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
+#define PDM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PDM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
+#define PDM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
+#define PDM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
+#define PDM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define PDM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << PDM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: PDM_EVENTS_STARTED */
+/* Description: PDM transfer has started */
+
+/* Bit 0 : PDM transfer has started */
+#define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
+#define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
+#define PDM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
+#define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: PDM_EVENTS_STOPPED */
+/* Description: PDM transfer has finished */
+
+/* Bit 0 : PDM transfer has finished */
+#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
+#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
+#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: PDM_EVENTS_END */
+/* Description: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */
+
+/* Bit 0 : The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */
+#define PDM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
+#define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
+#define PDM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
+#define PDM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
+
+/* Register: PDM_PUBLISH_STARTED */
+/* Description: Publish configuration for event STARTED */
+
+/* Bit 31 : */
+#define PDM_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */
+#define PDM_PUBLISH_STARTED_EN_Msk (0x1UL << PDM_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */
+#define PDM_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */
+#define PDM_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event STARTED will publish to */
+#define PDM_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define PDM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << PDM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: PDM_PUBLISH_STOPPED */
+/* Description: Publish configuration for event STOPPED */
+
+/* Bit 31 : */
+#define PDM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
+#define PDM_PUBLISH_STOPPED_EN_Msk (0x1UL << PDM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
+#define PDM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
+#define PDM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event STOPPED will publish to */
+#define PDM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define PDM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << PDM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: PDM_PUBLISH_END */
+/* Description: Publish configuration for event END */
+
+/* Bit 31 : */
+#define PDM_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */
+#define PDM_PUBLISH_END_EN_Msk (0x1UL << PDM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */
+#define PDM_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */
+#define PDM_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event END will publish to */
+#define PDM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define PDM_PUBLISH_END_CHIDX_Msk (0xFFUL << PDM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: PDM_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 2 : Enable or disable interrupt for event END */
+#define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */
+#define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */
+#define PDM_INTEN_END_Disabled (0UL) /*!< Disable */
+#define PDM_INTEN_END_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for event STOPPED */
+#define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for event STARTED */
+#define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */
+#define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */
+
+/* Register: PDM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 2 : Write '1' to enable interrupt for event END */
+#define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */
+#define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event STOPPED */
+#define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event STARTED */
+#define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Register: PDM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 2 : Write '1' to disable interrupt for event END */
+#define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */
+#define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event STOPPED */
+#define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event STARTED */
+#define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Register: PDM_ENABLE */
+/* Description: PDM module enable register */
+
+/* Bit 0 : Enable or disable PDM module */
+#define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: PDM_PDMCLKCTRL */
+/* Description: PDM clock generator control */
+
+/* Bits 31..0 : PDM_CLK frequency configuration. */
+#define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */
+#define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */
+#define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */
+#define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. */
+#define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */
+#define PDM_PDMCLKCTRL_FREQ_1231K (0x09800000UL) /*!< PDM_CLK = 32 MHz / 26 = 1.231 MHz */
+#define PDM_PDMCLKCTRL_FREQ_1280K (0x0A000000UL) /*!< PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. */
+#define PDM_PDMCLKCTRL_FREQ_1333K (0x0A800000UL) /*!< PDM_CLK = 32 MHz / 24 = 1.333 MHz */
+
+/* Register: PDM_MODE */
+/* Description: Defines the routing of the connected PDM microphones' signals */
+
+/* Bit 1 : Defines on which PDM_CLK edge left (or mono) is sampled */
+#define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */
+#define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */
+#define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */
+#define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */
+
+/* Bit 0 : Mono or stereo operation */
+#define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */
+#define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */
+#define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] */
+#define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] */
+
+/* Register: PDM_GAINL */
+/* Description: Left output gain adjustment */
+
+/* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust */
+#define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */
+#define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */
+#define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */
+#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */
+#define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */
+
+/* Register: PDM_GAINR */
+/* Description: Right output gain adjustment */
+
+/* Bits 6..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */
+#define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */
+#define PDM_GAINR_GAINR_Msk (0x7FUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */
+#define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */
+#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */
+#define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */
+
+/* Register: PDM_RATIO */
+/* Description: Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. */
+
+/* Bit 0 : Selects the ratio between PDM_CLK and output sample rate */
+#define PDM_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
+#define PDM_RATIO_RATIO_Msk (0x1UL << PDM_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
+#define PDM_RATIO_RATIO_Ratio64 (0UL) /*!< Ratio of 64 */
+#define PDM_RATIO_RATIO_Ratio80 (1UL) /*!< Ratio of 80 */
+
+/* Register: PDM_PSEL_CLK */
+/* Description: Pin number configuration for PDM CLK signal */
+
+/* Bit 31 : Connection */
+#define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */
+#define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: PDM_PSEL_DIN */
+/* Description: Pin number configuration for PDM DIN signal */
+
+/* Bit 31 : Connection */
+#define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */
+#define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: PDM_SAMPLE_PTR */
+/* Description: RAM address pointer to write samples to with EasyDMA */
+
+/* Bits 31..0 : Address to write PDM samples to over DMA */
+#define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */
+#define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */
+
+/* Register: PDM_SAMPLE_MAXCNT */
+/* Description: Number of samples to allocate memory for in EasyDMA mode */
+
+/* Bits 14..0 : Length of DMA RAM allocation in number of samples */
+#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */
+#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */
+
+
+/* Peripheral: POWER */
+/* Description: Power control 0 */
+
+/* Register: POWER_TASKS_PWMREQSTART */
+/* Description: Request forcing PWM mode in external DC/DC voltage regulator. (Drives FPWM_DCDC pin high or low depending on a setting in UICR). */
+
+/* Bit 0 : Request forcing PWM mode in external DC/DC voltage regulator. (Drives FPWM_DCDC pin high or low depending on a setting in UICR). */
+#define POWER_TASKS_PWMREQSTART_TASKS_PWMREQSTART_Pos (0UL) /*!< Position of TASKS_PWMREQSTART field. */
+#define POWER_TASKS_PWMREQSTART_TASKS_PWMREQSTART_Msk (0x1UL << POWER_TASKS_PWMREQSTART_TASKS_PWMREQSTART_Pos) /*!< Bit mask of TASKS_PWMREQSTART field. */
+#define POWER_TASKS_PWMREQSTART_TASKS_PWMREQSTART_Trigger (1UL) /*!< Trigger task */
+
+/* Register: POWER_TASKS_PWMREQSTOP */
+/* Description: Stop requesting forcing PWM mode in external DC/DC voltage regulator */
+
+/* Bit 0 : Stop requesting forcing PWM mode in external DC/DC voltage regulator */
+#define POWER_TASKS_PWMREQSTOP_TASKS_PWMREQSTOP_Pos (0UL) /*!< Position of TASKS_PWMREQSTOP field. */
+#define POWER_TASKS_PWMREQSTOP_TASKS_PWMREQSTOP_Msk (0x1UL << POWER_TASKS_PWMREQSTOP_TASKS_PWMREQSTOP_Pos) /*!< Bit mask of TASKS_PWMREQSTOP field. */
+#define POWER_TASKS_PWMREQSTOP_TASKS_PWMREQSTOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: POWER_TASKS_CONSTLAT */
+/* Description: Enable constant latency mode. */
+
+/* Bit 0 : Enable constant latency mode. */
+#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */
+#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */
+#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */
+
+/* Register: POWER_TASKS_LOWPWR */
+/* Description: Enable low power mode (variable latency) */
+
+/* Bit 0 : Enable low power mode (variable latency) */
+#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */
+#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */
+#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */
+
+/* Register: POWER_SUBSCRIBE_PWMREQSTART */
+/* Description: Subscribe configuration for task PWMREQSTART */
+
+/* Bit 31 : */
+#define POWER_SUBSCRIBE_PWMREQSTART_EN_Pos (31UL) /*!< Position of EN field. */
+#define POWER_SUBSCRIBE_PWMREQSTART_EN_Msk (0x1UL << POWER_SUBSCRIBE_PWMREQSTART_EN_Pos) /*!< Bit mask of EN field. */
+#define POWER_SUBSCRIBE_PWMREQSTART_EN_Disabled (0UL) /*!< Disable subscription */
+#define POWER_SUBSCRIBE_PWMREQSTART_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task PWMREQSTART will subscribe to */
+#define POWER_SUBSCRIBE_PWMREQSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define POWER_SUBSCRIBE_PWMREQSTART_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_PWMREQSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: POWER_SUBSCRIBE_PWMREQSTOP */
+/* Description: Subscribe configuration for task PWMREQSTOP */
+
+/* Bit 31 : */
+#define POWER_SUBSCRIBE_PWMREQSTOP_EN_Pos (31UL) /*!< Position of EN field. */
+#define POWER_SUBSCRIBE_PWMREQSTOP_EN_Msk (0x1UL << POWER_SUBSCRIBE_PWMREQSTOP_EN_Pos) /*!< Bit mask of EN field. */
+#define POWER_SUBSCRIBE_PWMREQSTOP_EN_Disabled (0UL) /*!< Disable subscription */
+#define POWER_SUBSCRIBE_PWMREQSTOP_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task PWMREQSTOP will subscribe to */
+#define POWER_SUBSCRIBE_PWMREQSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define POWER_SUBSCRIBE_PWMREQSTOP_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_PWMREQSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: POWER_SUBSCRIBE_CONSTLAT */
+/* Description: Subscribe configuration for task CONSTLAT */
+
+/* Bit 31 : */
+#define POWER_SUBSCRIBE_CONSTLAT_EN_Pos (31UL) /*!< Position of EN field. */
+#define POWER_SUBSCRIBE_CONSTLAT_EN_Msk (0x1UL << POWER_SUBSCRIBE_CONSTLAT_EN_Pos) /*!< Bit mask of EN field. */
+#define POWER_SUBSCRIBE_CONSTLAT_EN_Disabled (0UL) /*!< Disable subscription */
+#define POWER_SUBSCRIBE_CONSTLAT_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task CONSTLAT will subscribe to */
+#define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: POWER_SUBSCRIBE_LOWPWR */
+/* Description: Subscribe configuration for task LOWPWR */
+
+/* Bit 31 : */
+#define POWER_SUBSCRIBE_LOWPWR_EN_Pos (31UL) /*!< Position of EN field. */
+#define POWER_SUBSCRIBE_LOWPWR_EN_Msk (0x1UL << POWER_SUBSCRIBE_LOWPWR_EN_Pos) /*!< Bit mask of EN field. */
+#define POWER_SUBSCRIBE_LOWPWR_EN_Disabled (0UL) /*!< Disable subscription */
+#define POWER_SUBSCRIBE_LOWPWR_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task LOWPWR will subscribe to */
+#define POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define POWER_SUBSCRIBE_LOWPWR_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: POWER_EVENTS_POFWARN */
+/* Description: Power failure warning */
+
+/* Bit 0 : Power failure warning */
+#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */
+#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */
+#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0UL) /*!< Event not generated */
+#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (1UL) /*!< Event generated */
+
+/* Register: POWER_EVENTS_SLEEPENTER */
+/* Description: CPU entered WFI/WFE sleep */
+
+/* Bit 0 : CPU entered WFI/WFE sleep */
+#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */
+#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */
+#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0UL) /*!< Event not generated */
+#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (1UL) /*!< Event generated */
+
+/* Register: POWER_EVENTS_SLEEPEXIT */
+/* Description: CPU exited WFI/WFE sleep */
+
+/* Bit 0 : CPU exited WFI/WFE sleep */
+#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */
+#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */
+#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0UL) /*!< Event not generated */
+#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (1UL) /*!< Event generated */
+
+/* Register: POWER_PUBLISH_POFWARN */
+/* Description: Publish configuration for event POFWARN */
+
+/* Bit 31 : */
+#define POWER_PUBLISH_POFWARN_EN_Pos (31UL) /*!< Position of EN field. */
+#define POWER_PUBLISH_POFWARN_EN_Msk (0x1UL << POWER_PUBLISH_POFWARN_EN_Pos) /*!< Bit mask of EN field. */
+#define POWER_PUBLISH_POFWARN_EN_Disabled (0UL) /*!< Disable publishing */
+#define POWER_PUBLISH_POFWARN_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event POFWARN will publish to */
+#define POWER_PUBLISH_POFWARN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define POWER_PUBLISH_POFWARN_CHIDX_Msk (0xFFUL << POWER_PUBLISH_POFWARN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: POWER_PUBLISH_SLEEPENTER */
+/* Description: Publish configuration for event SLEEPENTER */
+
+/* Bit 31 : */
+#define POWER_PUBLISH_SLEEPENTER_EN_Pos (31UL) /*!< Position of EN field. */
+#define POWER_PUBLISH_SLEEPENTER_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPENTER_EN_Pos) /*!< Bit mask of EN field. */
+#define POWER_PUBLISH_SLEEPENTER_EN_Disabled (0UL) /*!< Disable publishing */
+#define POWER_PUBLISH_SLEEPENTER_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event SLEEPENTER will publish to */
+#define POWER_PUBLISH_SLEEPENTER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define POWER_PUBLISH_SLEEPENTER_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPENTER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: POWER_PUBLISH_SLEEPEXIT */
+/* Description: Publish configuration for event SLEEPEXIT */
+
+/* Bit 31 : */
+#define POWER_PUBLISH_SLEEPEXIT_EN_Pos (31UL) /*!< Position of EN field. */
+#define POWER_PUBLISH_SLEEPEXIT_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPEXIT_EN_Pos) /*!< Bit mask of EN field. */
+#define POWER_PUBLISH_SLEEPEXIT_EN_Disabled (0UL) /*!< Disable publishing */
+#define POWER_PUBLISH_SLEEPEXIT_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event SLEEPEXIT will publish to */
+#define POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define POWER_PUBLISH_SLEEPEXIT_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: POWER_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 6 : Enable or disable interrupt for event SLEEPEXIT */
+#define POWER_INTEN_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
+#define POWER_INTEN_SLEEPEXIT_Msk (0x1UL << POWER_INTEN_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
+#define POWER_INTEN_SLEEPEXIT_Disabled (0UL) /*!< Disable */
+#define POWER_INTEN_SLEEPEXIT_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for event SLEEPENTER */
+#define POWER_INTEN_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
+#define POWER_INTEN_SLEEPENTER_Msk (0x1UL << POWER_INTEN_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
+#define POWER_INTEN_SLEEPENTER_Disabled (0UL) /*!< Disable */
+#define POWER_INTEN_SLEEPENTER_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for event POFWARN */
+#define POWER_INTEN_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
+#define POWER_INTEN_POFWARN_Msk (0x1UL << POWER_INTEN_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
+#define POWER_INTEN_POFWARN_Disabled (0UL) /*!< Disable */
+#define POWER_INTEN_POFWARN_Enabled (1UL) /*!< Enable */
+
+/* Register: POWER_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 6 : Write '1' to enable interrupt for event SLEEPEXIT */
+#define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
+#define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
+#define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to enable interrupt for event SLEEPENTER */
+#define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
+#define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
+#define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event POFWARN */
+#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
+#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
+#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
+
+/* Register: POWER_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 6 : Write '1' to disable interrupt for event SLEEPEXIT */
+#define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
+#define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
+#define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to disable interrupt for event SLEEPENTER */
+#define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
+#define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
+#define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event POFWARN */
+#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
+#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
+#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
+
+/* Register: POWER_RESETREAS */
+/* Description: Reset reason */
+
+/* Bit 18 : Reset triggered through CTRL-AP */
+#define POWER_RESETREAS_CTRLAP_Pos (18UL) /*!< Position of CTRLAP field. */
+#define POWER_RESETREAS_CTRLAP_Msk (0x1UL << POWER_RESETREAS_CTRLAP_Pos) /*!< Bit mask of CTRLAP field. */
+#define POWER_RESETREAS_CTRLAP_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_CTRLAP_Detected (1UL) /*!< Detected */
+
+/* Bit 17 : Reset from CPU lock-up detected */
+#define POWER_RESETREAS_LOCKUP_Pos (17UL) /*!< Position of LOCKUP field. */
+#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
+#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */
+
+/* Bit 16 : Reset from AIRCR.SYSRESETREQ detected */
+#define POWER_RESETREAS_SREQ_Pos (16UL) /*!< Position of SREQ field. */
+#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
+#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */
+
+/* Bit 4 : Reset due to wakeup from System OFF mode, when wakeup is triggered by entering debug interface mode */
+#define POWER_RESETREAS_DIF_Pos (4UL) /*!< Position of DIF field. */
+#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
+#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */
+
+/* Bit 2 : Reset due to wakeup from System OFF mode, when wakeup is triggered by DETECT signal from GPIO */
+#define POWER_RESETREAS_OFF_Pos (2UL) /*!< Position of OFF field. */
+#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
+#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */
+
+/* Bit 1 : Reset from global watchdog detected */
+#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
+#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
+#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */
+
+/* Bit 0 : Reset from pin reset detected */
+#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
+#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
+#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */
+
+/* Register: POWER_POWERSTATUS */
+/* Description: Modem domain power status */
+
+/* Bit 0 : LTE modem domain status */
+#define POWER_POWERSTATUS_LTEMODEM_Pos (0UL) /*!< Position of LTEMODEM field. */
+#define POWER_POWERSTATUS_LTEMODEM_Msk (0x1UL << POWER_POWERSTATUS_LTEMODEM_Pos) /*!< Bit mask of LTEMODEM field. */
+#define POWER_POWERSTATUS_LTEMODEM_OFF (0UL) /*!< LTE modem domain is powered off */
+#define POWER_POWERSTATUS_LTEMODEM_ON (1UL) /*!< LTE modem domain is powered on */
+
+/* Register: POWER_GPREGRET */
+/* Description: Description collection: General purpose retention register */
+
+/* Bits 7..0 : General purpose retention register */
+#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
+#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
+
+/* Register: POWER_LTEMODEM_STARTN */
+/* Description: Start LTE modem */
+
+/* Bit 0 : Start LTE modem */
+#define POWER_LTEMODEM_STARTN_STARTN_Pos (0UL) /*!< Position of STARTN field. */
+#define POWER_LTEMODEM_STARTN_STARTN_Msk (0x1UL << POWER_LTEMODEM_STARTN_STARTN_Pos) /*!< Bit mask of STARTN field. */
+#define POWER_LTEMODEM_STARTN_STARTN_Start (0UL) /*!< Start LTE modem */
+#define POWER_LTEMODEM_STARTN_STARTN_Hold (1UL) /*!< Hold LTE modem disabled */
+
+/* Register: POWER_LTEMODEM_FORCEOFF */
+/* Description: Force off LTE modem */
+
+/* Bit 0 : Force off LTE modem */
+#define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */
+#define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Msk (0x1UL << POWER_LTEMODEM_FORCEOFF_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */
+#define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Release (0UL) /*!< Release force off */
+#define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Hold (1UL) /*!< Hold force off active */
+
+
+/* Peripheral: PWM */
+/* Description: Pulse width modulation unit 0 */
+
+/* Register: PWM_TASKS_STOP */
+/* Description: Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */
+
+/* Bit 0 : Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */
+#define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define PWM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: PWM_TASKS_SEQSTART */
+/* Description: Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */
+
+/* Bit 0 : Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */
+#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos (0UL) /*!< Position of TASKS_SEQSTART field. */
+#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Msk (0x1UL << PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos) /*!< Bit mask of TASKS_SEQSTART field. */
+#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Trigger (1UL) /*!< Trigger task */
+
+/* Register: PWM_TASKS_NEXTSTEP */
+/* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */
+
+/* Bit 0 : Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */
+#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL) /*!< Position of TASKS_NEXTSTEP field. */
+#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos) /*!< Bit mask of TASKS_NEXTSTEP field. */
+#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: PWM_SUBSCRIBE_STOP */
+/* Description: Subscribe configuration for task STOP */
+
+/* Bit 31 : */
+#define PWM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
+#define PWM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PWM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
+#define PWM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
+#define PWM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
+#define PWM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define PWM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: PWM_SUBSCRIBE_SEQSTART */
+/* Description: Description collection: Subscribe configuration for task SEQSTART[n] */
+
+/* Bit 31 : */
+#define PWM_SUBSCRIBE_SEQSTART_EN_Pos (31UL) /*!< Position of EN field. */
+#define PWM_SUBSCRIBE_SEQSTART_EN_Msk (0x1UL << PWM_SUBSCRIBE_SEQSTART_EN_Pos) /*!< Bit mask of EN field. */
+#define PWM_SUBSCRIBE_SEQSTART_EN_Disabled (0UL) /*!< Disable subscription */
+#define PWM_SUBSCRIBE_SEQSTART_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task SEQSTART[n] will subscribe to */
+#define PWM_SUBSCRIBE_SEQSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define PWM_SUBSCRIBE_SEQSTART_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_SEQSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: PWM_SUBSCRIBE_NEXTSTEP */
+/* Description: Subscribe configuration for task NEXTSTEP */
+
+/* Bit 31 : */
+#define PWM_SUBSCRIBE_NEXTSTEP_EN_Pos (31UL) /*!< Position of EN field. */
+#define PWM_SUBSCRIBE_NEXTSTEP_EN_Msk (0x1UL << PWM_SUBSCRIBE_NEXTSTEP_EN_Pos) /*!< Bit mask of EN field. */
+#define PWM_SUBSCRIBE_NEXTSTEP_EN_Disabled (0UL) /*!< Disable subscription */
+#define PWM_SUBSCRIBE_NEXTSTEP_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task NEXTSTEP will subscribe to */
+#define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: PWM_EVENTS_STOPPED */
+/* Description: Response to STOP task, emitted when PWM pulses are no longer generated */
+
+/* Bit 0 : Response to STOP task, emitted when PWM pulses are no longer generated */
+#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
+#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
+#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: PWM_EVENTS_SEQSTARTED */
+/* Description: Description collection: First PWM period started on sequence n */
+
+/* Bit 0 : First PWM period started on sequence n */
+#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field. */
+#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of EVENTS_SEQSTARTED field. */
+#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: PWM_EVENTS_SEQEND */
+/* Description: Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */
+
+/* Bit 0 : Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */
+#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL) /*!< Position of EVENTS_SEQEND field. */
+#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos) /*!< Bit mask of EVENTS_SEQEND field. */
+#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_NotGenerated (0UL) /*!< Event not generated */
+#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (1UL) /*!< Event generated */
+
+/* Register: PWM_EVENTS_PWMPERIODEND */
+/* Description: Emitted at the end of each PWM period */
+
+/* Bit 0 : Emitted at the end of each PWM period */
+#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field. */
+#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit mask of EVENTS_PWMPERIODEND field. */
+#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0UL) /*!< Event not generated */
+#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (1UL) /*!< Event generated */
+
+/* Register: PWM_EVENTS_LOOPSDONE */
+/* Description: Concatenated sequences have been played the amount of times defined in LOOP.CNT */
+
+/* Bit 0 : Concatenated sequences have been played the amount of times defined in LOOP.CNT */
+#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL) /*!< Position of EVENTS_LOOPSDONE field. */
+#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos) /*!< Bit mask of EVENTS_LOOPSDONE field. */
+#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_NotGenerated (0UL) /*!< Event not generated */
+#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (1UL) /*!< Event generated */
+
+/* Register: PWM_PUBLISH_STOPPED */
+/* Description: Publish configuration for event STOPPED */
+
+/* Bit 31 : */
+#define PWM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
+#define PWM_PUBLISH_STOPPED_EN_Msk (0x1UL << PWM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
+#define PWM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
+#define PWM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event STOPPED will publish to */
+#define PWM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define PWM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << PWM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: PWM_PUBLISH_SEQSTARTED */
+/* Description: Description collection: Publish configuration for event SEQSTARTED[n] */
+
+/* Bit 31 : */
+#define PWM_PUBLISH_SEQSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
+#define PWM_PUBLISH_SEQSTARTED_EN_Msk (0x1UL << PWM_PUBLISH_SEQSTARTED_EN_Pos) /*!< Bit mask of EN field. */
+#define PWM_PUBLISH_SEQSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
+#define PWM_PUBLISH_SEQSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event SEQSTARTED[n] will publish to */
+#define PWM_PUBLISH_SEQSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define PWM_PUBLISH_SEQSTARTED_CHIDX_Msk (0xFFUL << PWM_PUBLISH_SEQSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: PWM_PUBLISH_SEQEND */
+/* Description: Description collection: Publish configuration for event SEQEND[n] */
+
+/* Bit 31 : */
+#define PWM_PUBLISH_SEQEND_EN_Pos (31UL) /*!< Position of EN field. */
+#define PWM_PUBLISH_SEQEND_EN_Msk (0x1UL << PWM_PUBLISH_SEQEND_EN_Pos) /*!< Bit mask of EN field. */
+#define PWM_PUBLISH_SEQEND_EN_Disabled (0UL) /*!< Disable publishing */
+#define PWM_PUBLISH_SEQEND_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event SEQEND[n] will publish to */
+#define PWM_PUBLISH_SEQEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define PWM_PUBLISH_SEQEND_CHIDX_Msk (0xFFUL << PWM_PUBLISH_SEQEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: PWM_PUBLISH_PWMPERIODEND */
+/* Description: Publish configuration for event PWMPERIODEND */
+
+/* Bit 31 : */
+#define PWM_PUBLISH_PWMPERIODEND_EN_Pos (31UL) /*!< Position of EN field. */
+#define PWM_PUBLISH_PWMPERIODEND_EN_Msk (0x1UL << PWM_PUBLISH_PWMPERIODEND_EN_Pos) /*!< Bit mask of EN field. */
+#define PWM_PUBLISH_PWMPERIODEND_EN_Disabled (0UL) /*!< Disable publishing */
+#define PWM_PUBLISH_PWMPERIODEND_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event PWMPERIODEND will publish to */
+#define PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define PWM_PUBLISH_PWMPERIODEND_CHIDX_Msk (0xFFUL << PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: PWM_PUBLISH_LOOPSDONE */
+/* Description: Publish configuration for event LOOPSDONE */
+
+/* Bit 31 : */
+#define PWM_PUBLISH_LOOPSDONE_EN_Pos (31UL) /*!< Position of EN field. */
+#define PWM_PUBLISH_LOOPSDONE_EN_Msk (0x1UL << PWM_PUBLISH_LOOPSDONE_EN_Pos) /*!< Bit mask of EN field. */
+#define PWM_PUBLISH_LOOPSDONE_EN_Disabled (0UL) /*!< Disable publishing */
+#define PWM_PUBLISH_LOOPSDONE_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event LOOPSDONE will publish to */
+#define PWM_PUBLISH_LOOPSDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define PWM_PUBLISH_LOOPSDONE_CHIDX_Msk (0xFFUL << PWM_PUBLISH_LOOPSDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: PWM_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 4 : Shortcut between event LOOPSDONE and task STOP */
+#define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */
+#define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */
+#define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between event LOOPSDONE and task SEQSTART[1] */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between event LOOPSDONE and task SEQSTART[0] */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between event SEQEND[1] and task STOP */
+#define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */
+#define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */
+#define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between event SEQEND[0] and task STOP */
+#define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */
+#define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */
+#define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: PWM_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 7 : Enable or disable interrupt for event LOOPSDONE */
+#define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
+#define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
+#define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for event PWMPERIODEND */
+#define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
+#define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
+#define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for event SEQEND[1] */
+#define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
+#define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
+#define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for event SEQEND[0] */
+#define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
+#define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
+#define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for event SEQSTARTED[1] */
+#define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
+#define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
+#define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for event SEQSTARTED[0] */
+#define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
+#define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
+#define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for event STOPPED */
+#define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Register: PWM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 7 : Write '1' to enable interrupt for event LOOPSDONE */
+#define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
+#define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
+#define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to enable interrupt for event PWMPERIODEND */
+#define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
+#define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
+#define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to enable interrupt for event SEQEND[1] */
+#define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
+#define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
+#define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to enable interrupt for event SEQEND[0] */
+#define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
+#define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
+#define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to enable interrupt for event SEQSTARTED[1] */
+#define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
+#define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
+#define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event SEQSTARTED[0] */
+#define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
+#define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
+#define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event STOPPED */
+#define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: PWM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 7 : Write '1' to disable interrupt for event LOOPSDONE */
+#define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
+#define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
+#define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to disable interrupt for event PWMPERIODEND */
+#define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
+#define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
+#define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to disable interrupt for event SEQEND[1] */
+#define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
+#define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
+#define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to disable interrupt for event SEQEND[0] */
+#define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
+#define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
+#define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to disable interrupt for event SEQSTARTED[1] */
+#define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
+#define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
+#define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event SEQSTARTED[0] */
+#define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
+#define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
+#define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event STOPPED */
+#define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: PWM_ENABLE */
+/* Description: PWM module enable register */
+
+/* Bit 0 : Enable or disable PWM module */
+#define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */
+#define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: PWM_MODE */
+/* Description: Selects operating mode of the wave counter */
+
+/* Bit 0 : Selects up mode or up-and-down mode for the counter */
+#define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */
+#define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */
+#define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter, edge-aligned PWM duty cycle */
+#define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter, center-aligned PWM duty cycle */
+
+/* Register: PWM_COUNTERTOP */
+/* Description: Value up to which the pulse generator counter counts */
+
+/* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. */
+#define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */
+#define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */
+
+/* Register: PWM_PRESCALER */
+/* Description: Configuration for PWM_CLK */
+
+/* Bits 2..0 : Prescaler of PWM_CLK */
+#define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
+#define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+#define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16 MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 (8 MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 (4 MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 (2 MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 (1 MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by 32 (500 kHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by 64 (250 kHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 (125 kHz) */
+
+/* Register: PWM_DECODER */
+/* Description: Configuration of the decoder */
+
+/* Bit 8 : Selects source for advancing the active sequence */
+#define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */
+#define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */
+#define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */
+#define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */
+
+/* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */
+#define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */
+#define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */
+#define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
+#define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */
+#define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */
+#define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */
+
+/* Register: PWM_LOOP */
+/* Description: Number of playbacks of a loop */
+
+/* Bits 15..0 : Number of playbacks of pattern cycles */
+#define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */
+#define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */
+
+/* Register: PWM_SEQ_PTR */
+/* Description: Description cluster: Beginning address in RAM of this sequence */
+
+/* Bits 31..0 : Beginning address in RAM of this sequence */
+#define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: PWM_SEQ_CNT */
+/* Description: Description cluster: Number of values (duty cycles) in this sequence */
+
+/* Bits 14..0 : Number of values (duty cycles) in this sequence */
+#define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
+#define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */
+
+/* Register: PWM_SEQ_REFRESH */
+/* Description: Description cluster: Number of additional PWM periods between samples loaded into compare register */
+
+/* Bits 23..0 : Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */
+#define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */
+#define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */
+
+/* Register: PWM_SEQ_ENDDELAY */
+/* Description: Description cluster: Time added after the sequence */
+
+/* Bits 23..0 : Time added after the sequence in PWM periods */
+#define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */
+
+/* Register: PWM_PSEL_OUT */
+/* Description: Description collection: Output pin select for PWM channel n */
+
+/* Bit 31 : Connection */
+#define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */
+#define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */
+
+
+/* Peripheral: REGULATORS */
+/* Description: Voltage regulators control 0 */
+
+/* Register: REGULATORS_SYSTEMOFF */
+/* Description: System OFF register */
+
+/* Bit 0 : Enable System OFF mode */
+#define REGULATORS_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
+#define REGULATORS_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << REGULATORS_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
+#define REGULATORS_SYSTEMOFF_SYSTEMOFF_Enable (1UL) /*!< Enable System OFF mode */
+
+/* Register: REGULATORS_EXTPOFCON */
+/* Description: External power failure warning configuration */
+
+/* Bit 0 : Enable or disable external power failure warning */
+#define REGULATORS_EXTPOFCON_POF_Pos (0UL) /*!< Position of POF field. */
+#define REGULATORS_EXTPOFCON_POF_Msk (0x1UL << REGULATORS_EXTPOFCON_POF_Pos) /*!< Bit mask of POF field. */
+#define REGULATORS_EXTPOFCON_POF_Disabled (0UL) /*!< Disable */
+#define REGULATORS_EXTPOFCON_POF_Enabled (1UL) /*!< Enable */
+
+/* Register: REGULATORS_DCDCEN */
+/* Description: Enable DC/DC mode of the main voltage regulator. */
+
+/* Bit 0 : Enable DC/DC converter */
+#define REGULATORS_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
+#define REGULATORS_DCDCEN_DCDCEN_Msk (0x1UL << REGULATORS_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
+#define REGULATORS_DCDCEN_DCDCEN_Disabled (0UL) /*!< DC/DC mode is disabled */
+#define REGULATORS_DCDCEN_DCDCEN_Enabled (1UL) /*!< DC/DC mode is enabled */
+
+
+/* Peripheral: RTC */
+/* Description: Real-time counter 0 */
+
+/* Register: RTC_TASKS_START */
+/* Description: Start RTC counter */
+
+/* Bit 0 : Start RTC counter */
+#define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define RTC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RTC_TASKS_STOP */
+/* Description: Stop RTC counter */
+
+/* Bit 0 : Stop RTC counter */
+#define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RTC_TASKS_CLEAR */
+/* Description: Clear RTC counter */
+
+/* Bit 0 : Clear RTC counter */
+#define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
+#define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
+#define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RTC_TASKS_TRIGOVRFLW */
+/* Description: Set counter to 0xFFFFF0 */
+
+/* Bit 0 : Set counter to 0xFFFFF0 */
+#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */
+#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */
+#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL) /*!< Trigger task */
+
+/* Register: RTC_SUBSCRIBE_START */
+/* Description: Subscribe configuration for task START */
+
+/* Bit 31 : */
+#define RTC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
+#define RTC_SUBSCRIBE_START_EN_Msk (0x1UL << RTC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
+#define RTC_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
+#define RTC_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task START will subscribe to */
+#define RTC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define RTC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: RTC_SUBSCRIBE_STOP */
+/* Description: Subscribe configuration for task STOP */
+
+/* Bit 31 : */
+#define RTC_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
+#define RTC_SUBSCRIBE_STOP_EN_Msk (0x1UL << RTC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
+#define RTC_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
+#define RTC_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
+#define RTC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define RTC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: RTC_SUBSCRIBE_CLEAR */
+/* Description: Subscribe configuration for task CLEAR */
+
+/* Bit 31 : */
+#define RTC_SUBSCRIBE_CLEAR_EN_Pos (31UL) /*!< Position of EN field. */
+#define RTC_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << RTC_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field. */
+#define RTC_SUBSCRIBE_CLEAR_EN_Disabled (0UL) /*!< Disable subscription */
+#define RTC_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */
+#define RTC_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define RTC_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: RTC_SUBSCRIBE_TRIGOVRFLW */
+/* Description: Subscribe configuration for task TRIGOVRFLW */
+
+/* Bit 31 : */
+#define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos (31UL) /*!< Position of EN field. */
+#define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Msk (0x1UL << RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos) /*!< Bit mask of EN field. */
+#define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Disabled (0UL) /*!< Disable subscription */
+#define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task TRIGOVRFLW will subscribe to */
+#define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: RTC_EVENTS_TICK */
+/* Description: Event on counter increment */
+
+/* Bit 0 : Event on counter increment */
+#define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */
+#define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */
+#define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0UL) /*!< Event not generated */
+#define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL) /*!< Event generated */
+
+/* Register: RTC_EVENTS_OVRFLW */
+/* Description: Event on counter overflow */
+
+/* Bit 0 : Event on counter overflow */
+#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */
+#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */
+#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0UL) /*!< Event not generated */
+#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL) /*!< Event generated */
+
+/* Register: RTC_EVENTS_COMPARE */
+/* Description: Description collection: Compare event on CC[n] match */
+
+/* Bit 0 : Compare event on CC[n] match */
+#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
+#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
+#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */
+#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */
+
+/* Register: RTC_PUBLISH_TICK */
+/* Description: Publish configuration for event TICK */
+
+/* Bit 31 : */
+#define RTC_PUBLISH_TICK_EN_Pos (31UL) /*!< Position of EN field. */
+#define RTC_PUBLISH_TICK_EN_Msk (0x1UL << RTC_PUBLISH_TICK_EN_Pos) /*!< Bit mask of EN field. */
+#define RTC_PUBLISH_TICK_EN_Disabled (0UL) /*!< Disable publishing */
+#define RTC_PUBLISH_TICK_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event TICK will publish to */
+#define RTC_PUBLISH_TICK_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define RTC_PUBLISH_TICK_CHIDX_Msk (0xFFUL << RTC_PUBLISH_TICK_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: RTC_PUBLISH_OVRFLW */
+/* Description: Publish configuration for event OVRFLW */
+
+/* Bit 31 : */
+#define RTC_PUBLISH_OVRFLW_EN_Pos (31UL) /*!< Position of EN field. */
+#define RTC_PUBLISH_OVRFLW_EN_Msk (0x1UL << RTC_PUBLISH_OVRFLW_EN_Pos) /*!< Bit mask of EN field. */
+#define RTC_PUBLISH_OVRFLW_EN_Disabled (0UL) /*!< Disable publishing */
+#define RTC_PUBLISH_OVRFLW_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event OVRFLW will publish to */
+#define RTC_PUBLISH_OVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define RTC_PUBLISH_OVRFLW_CHIDX_Msk (0xFFUL << RTC_PUBLISH_OVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: RTC_PUBLISH_COMPARE */
+/* Description: Description collection: Publish configuration for event COMPARE[n] */
+
+/* Bit 31 : */
+#define RTC_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */
+#define RTC_PUBLISH_COMPARE_EN_Msk (0x1UL << RTC_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */
+#define RTC_PUBLISH_COMPARE_EN_Disabled (0UL) /*!< Disable publishing */
+#define RTC_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to */
+#define RTC_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define RTC_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << RTC_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: RTC_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
+#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
+#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
+#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
+#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event OVRFLW */
+#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event TICK */
+#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
+
+/* Register: RTC_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
+#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
+#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
+#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
+#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event OVRFLW */
+#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event TICK */
+#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
+
+/* Register: RTC_EVTEN */
+/* Description: Enable or disable event routing */
+
+/* Bit 19 : Enable or disable event routing for event COMPARE[3] */
+#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */
+
+/* Bit 18 : Enable or disable event routing for event COMPARE[2] */
+#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */
+
+/* Bit 17 : Enable or disable event routing for event COMPARE[1] */
+#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */
+
+/* Bit 16 : Enable or disable event routing for event COMPARE[0] */
+#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable event routing for event OVRFLW */
+#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable event routing for event TICK */
+#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */
+
+/* Register: RTC_EVTENSET */
+/* Description: Enable event routing */
+
+/* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */
+#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */
+#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to enable event routing for event COMPARE[1] */
+#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */
+#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable event routing for event OVRFLW */
+#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable event routing for event TICK */
+#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
+
+/* Register: RTC_EVTENCLR */
+/* Description: Disable event routing */
+
+/* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */
+#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */
+#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to disable event routing for event COMPARE[1] */
+#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */
+#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable event routing for event OVRFLW */
+#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable event routing for event TICK */
+#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
+
+/* Register: RTC_COUNTER */
+/* Description: Current counter value */
+
+/* Bits 23..0 : Counter value */
+#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
+#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
+
+/* Register: RTC_PRESCALER */
+/* Description: 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. */
+
+/* Bits 11..0 : Prescaler value */
+#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
+#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+
+/* Register: RTC_CC */
+/* Description: Description collection: Compare register n */
+
+/* Bits 23..0 : Compare value */
+#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
+#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
+
+
+/* Peripheral: SAADC */
+/* Description: Analog to Digital Converter 0 */
+
+/* Register: SAADC_TASKS_START */
+/* Description: Start the ADC and prepare the result buffer in RAM */
+
+/* Bit 0 : Start the ADC and prepare the result buffer in RAM */
+#define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define SAADC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SAADC_TASKS_SAMPLE */
+/* Description: Take one ADC sample, if scan is enabled all channels are sampled */
+
+/* Bit 0 : Take one ADC sample, if scan is enabled all channels are sampled */
+#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
+#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
+#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SAADC_TASKS_STOP */
+/* Description: Stop the ADC and terminate any on-going conversion */
+
+/* Bit 0 : Stop the ADC and terminate any on-going conversion */
+#define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define SAADC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SAADC_TASKS_CALIBRATEOFFSET */
+/* Description: Starts offset auto-calibration */
+
+/* Bit 0 : Starts offset auto-calibration */
+#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field. */
+#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) /*!< Bit mask of TASKS_CALIBRATEOFFSET field. */
+#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SAADC_SUBSCRIBE_START */
+/* Description: Subscribe configuration for task START */
+
+/* Bit 31 : */
+#define SAADC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
+#define SAADC_SUBSCRIBE_START_EN_Msk (0x1UL << SAADC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
+#define SAADC_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
+#define SAADC_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task START will subscribe to */
+#define SAADC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define SAADC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: SAADC_SUBSCRIBE_SAMPLE */
+/* Description: Subscribe configuration for task SAMPLE */
+
+/* Bit 31 : */
+#define SAADC_SUBSCRIBE_SAMPLE_EN_Pos (31UL) /*!< Position of EN field. */
+#define SAADC_SUBSCRIBE_SAMPLE_EN_Msk (0x1UL << SAADC_SUBSCRIBE_SAMPLE_EN_Pos) /*!< Bit mask of EN field. */
+#define SAADC_SUBSCRIBE_SAMPLE_EN_Disabled (0UL) /*!< Disable subscription */
+#define SAADC_SUBSCRIBE_SAMPLE_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task SAMPLE will subscribe to */
+#define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: SAADC_SUBSCRIBE_STOP */
+/* Description: Subscribe configuration for task STOP */
+
+/* Bit 31 : */
+#define SAADC_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
+#define SAADC_SUBSCRIBE_STOP_EN_Msk (0x1UL << SAADC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
+#define SAADC_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
+#define SAADC_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
+#define SAADC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define SAADC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: SAADC_SUBSCRIBE_CALIBRATEOFFSET */
+/* Description: Subscribe configuration for task CALIBRATEOFFSET */
+
+/* Bit 31 : */
+#define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos (31UL) /*!< Position of EN field. */
+#define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Msk (0x1UL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos) /*!< Bit mask of EN field. */
+#define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Disabled (0UL) /*!< Disable subscription */
+#define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task CALIBRATEOFFSET will subscribe to */
+#define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: SAADC_EVENTS_STARTED */
+/* Description: The ADC has started */
+
+/* Bit 0 : The ADC has started */
+#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
+#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
+#define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: SAADC_EVENTS_END */
+/* Description: The ADC has filled up the Result buffer */
+
+/* Bit 0 : The ADC has filled up the Result buffer */
+#define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
+#define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
+#define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
+
+/* Register: SAADC_EVENTS_DONE */
+/* Description: A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */
+
+/* Bit 0 : A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */
+#define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */
+#define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */
+#define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */
+
+/* Register: SAADC_EVENTS_RESULTDONE */
+/* Description: A result is ready to get transferred to RAM. */
+
+/* Bit 0 : A result is ready to get transferred to RAM. */
+#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */
+#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask of EVENTS_RESULTDONE field. */
+#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (1UL) /*!< Event generated */
+
+/* Register: SAADC_EVENTS_CALIBRATEDONE */
+/* Description: Calibration is complete */
+
+/* Bit 0 : Calibration is complete */
+#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field. */
+#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) /*!< Bit mask of EVENTS_CALIBRATEDONE field. */
+#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (1UL) /*!< Event generated */
+
+/* Register: SAADC_EVENTS_STOPPED */
+/* Description: The ADC has stopped */
+
+/* Bit 0 : The ADC has stopped */
+#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
+#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
+#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: SAADC_EVENTS_CH_LIMITH */
+/* Description: Description cluster: Last results is equal or above CH[n].LIMIT.HIGH */
+
+/* Bit 0 : Last results is equal or above CH[n].LIMIT.HIGH */
+#define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */
+#define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */
+#define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (1UL) /*!< Event generated */
+
+/* Register: SAADC_EVENTS_CH_LIMITL */
+/* Description: Description cluster: Last results is equal or below CH[n].LIMIT.LOW */
+
+/* Bit 0 : Last results is equal or below CH[n].LIMIT.LOW */
+#define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */
+#define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field. */
+#define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0UL) /*!< Event not generated */
+#define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (1UL) /*!< Event generated */
+
+/* Register: SAADC_PUBLISH_STARTED */
+/* Description: Publish configuration for event STARTED */
+
+/* Bit 31 : */
+#define SAADC_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */
+#define SAADC_PUBLISH_STARTED_EN_Msk (0x1UL << SAADC_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */
+#define SAADC_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */
+#define SAADC_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event STARTED will publish to */
+#define SAADC_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define SAADC_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: SAADC_PUBLISH_END */
+/* Description: Publish configuration for event END */
+
+/* Bit 31 : */
+#define SAADC_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */
+#define SAADC_PUBLISH_END_EN_Msk (0x1UL << SAADC_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */
+#define SAADC_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */
+#define SAADC_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event END will publish to */
+#define SAADC_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define SAADC_PUBLISH_END_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: SAADC_PUBLISH_DONE */
+/* Description: Publish configuration for event DONE */
+
+/* Bit 31 : */
+#define SAADC_PUBLISH_DONE_EN_Pos (31UL) /*!< Position of EN field. */
+#define SAADC_PUBLISH_DONE_EN_Msk (0x1UL << SAADC_PUBLISH_DONE_EN_Pos) /*!< Bit mask of EN field. */
+#define SAADC_PUBLISH_DONE_EN_Disabled (0UL) /*!< Disable publishing */
+#define SAADC_PUBLISH_DONE_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event DONE will publish to */
+#define SAADC_PUBLISH_DONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define SAADC_PUBLISH_DONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_DONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: SAADC_PUBLISH_RESULTDONE */
+/* Description: Publish configuration for event RESULTDONE */
+
+/* Bit 31 : */
+#define SAADC_PUBLISH_RESULTDONE_EN_Pos (31UL) /*!< Position of EN field. */
+#define SAADC_PUBLISH_RESULTDONE_EN_Msk (0x1UL << SAADC_PUBLISH_RESULTDONE_EN_Pos) /*!< Bit mask of EN field. */
+#define SAADC_PUBLISH_RESULTDONE_EN_Disabled (0UL) /*!< Disable publishing */
+#define SAADC_PUBLISH_RESULTDONE_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event RESULTDONE will publish to */
+#define SAADC_PUBLISH_RESULTDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define SAADC_PUBLISH_RESULTDONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_RESULTDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: SAADC_PUBLISH_CALIBRATEDONE */
+/* Description: Publish configuration for event CALIBRATEDONE */
+
+/* Bit 31 : */
+#define SAADC_PUBLISH_CALIBRATEDONE_EN_Pos (31UL) /*!< Position of EN field. */
+#define SAADC_PUBLISH_CALIBRATEDONE_EN_Msk (0x1UL << SAADC_PUBLISH_CALIBRATEDONE_EN_Pos) /*!< Bit mask of EN field. */
+#define SAADC_PUBLISH_CALIBRATEDONE_EN_Disabled (0UL) /*!< Disable publishing */
+#define SAADC_PUBLISH_CALIBRATEDONE_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event CALIBRATEDONE will publish to */
+#define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: SAADC_PUBLISH_STOPPED */
+/* Description: Publish configuration for event STOPPED */
+
+/* Bit 31 : */
+#define SAADC_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
+#define SAADC_PUBLISH_STOPPED_EN_Msk (0x1UL << SAADC_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
+#define SAADC_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
+#define SAADC_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event STOPPED will publish to */
+#define SAADC_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define SAADC_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: SAADC_PUBLISH_CH_LIMITH */
+/* Description: Description cluster: Publish configuration for event CH[n].LIMITH */
+
+/* Bit 31 : */
+#define SAADC_PUBLISH_CH_LIMITH_EN_Pos (31UL) /*!< Position of EN field. */
+#define SAADC_PUBLISH_CH_LIMITH_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITH_EN_Pos) /*!< Bit mask of EN field. */
+#define SAADC_PUBLISH_CH_LIMITH_EN_Disabled (0UL) /*!< Disable publishing */
+#define SAADC_PUBLISH_CH_LIMITH_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event CH[n].LIMITH will publish to */
+#define SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define SAADC_PUBLISH_CH_LIMITH_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: SAADC_PUBLISH_CH_LIMITL */
+/* Description: Description cluster: Publish configuration for event CH[n].LIMITL */
+
+/* Bit 31 : */
+#define SAADC_PUBLISH_CH_LIMITL_EN_Pos (31UL) /*!< Position of EN field. */
+#define SAADC_PUBLISH_CH_LIMITL_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITL_EN_Pos) /*!< Bit mask of EN field. */
+#define SAADC_PUBLISH_CH_LIMITL_EN_Disabled (0UL) /*!< Disable publishing */
+#define SAADC_PUBLISH_CH_LIMITL_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event CH[n].LIMITL will publish to */
+#define SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define SAADC_PUBLISH_CH_LIMITL_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: SAADC_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 21 : Enable or disable interrupt for event CH7LIMITL */
+#define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
+#define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
+#define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for event CH7LIMITH */
+#define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
+#define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
+#define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for event CH6LIMITL */
+#define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
+#define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
+#define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 18 : Enable or disable interrupt for event CH6LIMITH */
+#define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
+#define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
+#define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 17 : Enable or disable interrupt for event CH5LIMITL */
+#define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
+#define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
+#define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 16 : Enable or disable interrupt for event CH5LIMITH */
+#define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
+#define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
+#define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 15 : Enable or disable interrupt for event CH4LIMITL */
+#define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
+#define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
+#define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 14 : Enable or disable interrupt for event CH4LIMITH */
+#define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
+#define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
+#define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 13 : Enable or disable interrupt for event CH3LIMITL */
+#define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
+#define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
+#define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 12 : Enable or disable interrupt for event CH3LIMITH */
+#define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
+#define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
+#define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 11 : Enable or disable interrupt for event CH2LIMITL */
+#define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
+#define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
+#define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 10 : Enable or disable interrupt for event CH2LIMITH */
+#define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
+#define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
+#define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for event CH1LIMITL */
+#define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
+#define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
+#define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 8 : Enable or disable interrupt for event CH1LIMITH */
+#define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
+#define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
+#define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for event CH0LIMITL */
+#define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
+#define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
+#define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for event CH0LIMITH */
+#define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
+#define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
+#define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for event STOPPED */
+#define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
+#define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */
+#define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
+#define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
+#define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for event RESULTDONE */
+#define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
+#define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
+#define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for event DONE */
+#define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */
+#define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */
+#define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for event END */
+#define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */
+#define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */
+#define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for event STARTED */
+#define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */
+
+/* Register: SAADC_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */
+#define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
+#define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
+#define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */
+#define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
+#define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
+#define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */
+#define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
+#define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
+#define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */
+#define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
+#define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
+#define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */
+#define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
+#define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
+#define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */
+#define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
+#define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
+#define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */
+#define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
+#define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
+#define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */
+#define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
+#define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
+#define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */
+#define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
+#define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
+#define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */
+#define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
+#define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
+#define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */
+#define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
+#define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
+#define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */
+#define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
+#define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
+#define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */
+#define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
+#define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
+#define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */
+#define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
+#define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
+#define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */
+#define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
+#define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
+#define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */
+#define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
+#define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
+#define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to enable interrupt for event STOPPED */
+#define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
+#define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */
+#define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
+#define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
+#define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to enable interrupt for event RESULTDONE */
+#define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
+#define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
+#define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event DONE */
+#define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */
+#define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
+#define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event END */
+#define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */
+#define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event STARTED */
+#define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Register: SAADC_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */
+#define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
+#define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
+#define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */
+#define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
+#define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
+#define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */
+#define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
+#define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
+#define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */
+#define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
+#define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
+#define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */
+#define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
+#define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
+#define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */
+#define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
+#define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
+#define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */
+#define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
+#define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
+#define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */
+#define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
+#define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
+#define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */
+#define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
+#define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
+#define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */
+#define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
+#define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
+#define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */
+#define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
+#define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
+#define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */
+#define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
+#define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
+#define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */
+#define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
+#define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
+#define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */
+#define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
+#define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
+#define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */
+#define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
+#define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
+#define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */
+#define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
+#define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
+#define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to disable interrupt for event STOPPED */
+#define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
+#define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */
+#define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
+#define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
+#define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to disable interrupt for event RESULTDONE */
+#define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
+#define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
+#define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event DONE */
+#define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */
+#define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
+#define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event END */
+#define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
+#define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event STARTED */
+#define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Register: SAADC_STATUS */
+/* Description: Status */
+
+/* Bit 0 : Status */
+#define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */
+#define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Single conversion in progress. */
+
+/* Register: SAADC_ENABLE */
+/* Description: Enable or disable ADC */
+
+/* Bit 0 : Enable or disable ADC */
+#define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */
+#define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */
+
+/* Register: SAADC_CH_PSELP */
+/* Description: Description cluster: Input positive pin selection for CH[n] */
+
+/* Bits 4..0 : Analog positive input channel */
+#define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */
+#define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */
+#define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */
+#define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */
+#define SAADC_CH_PSELP_PSELP_VDDGPIO (9UL) /*!< VDD_GPIO */
+
+/* Register: SAADC_CH_PSELN */
+/* Description: Description cluster: Input negative pin selection for CH[n] */
+
+/* Bits 4..0 : Analog negative input, enables differential channel */
+#define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */
+#define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */
+#define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */
+#define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */
+#define SAADC_CH_PSELN_PSELN_VDD_GPIO (9UL) /*!< VDD_GPIO */
+
+/* Register: SAADC_CH_CONFIG */
+/* Description: Description cluster: Input configuration for CH[n] */
+
+/* Bit 24 : Enable burst mode */
+#define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */
+#define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */
+#define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */
+#define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */
+
+/* Bit 20 : Enable differential mode */
+#define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */
+#define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
+#define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */
+#define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */
+
+/* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */
+#define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */
+#define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */
+#define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */
+#define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */
+#define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */
+#define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */
+#define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */
+#define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */
+
+/* Bit 12 : Reference control */
+#define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */
+#define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
+#define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */
+#define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD_GPIO/4 as reference */
+
+/* Bits 10..8 : Gain control */
+#define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */
+#define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */
+#define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */
+#define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */
+#define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */
+#define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */
+
+/* Bits 5..4 : Negative channel resistor control */
+#define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */
+#define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */
+#define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */
+#define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */
+#define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD_GPIO */
+#define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD_GPIO/2 */
+
+/* Bits 1..0 : Positive channel resistor control */
+#define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */
+#define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */
+#define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */
+#define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */
+#define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD_GPIO */
+#define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD_GPIO/2 */
+
+/* Register: SAADC_CH_LIMIT */
+/* Description: Description cluster: High/low limits for event monitoring a channel */
+
+/* Bits 31..16 : High level limit */
+#define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */
+#define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */
+
+/* Bits 15..0 : Low level limit */
+#define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */
+#define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */
+
+/* Register: SAADC_RESOLUTION */
+/* Description: Resolution configuration */
+
+/* Bits 2..0 : Set the resolution */
+#define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */
+#define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */
+#define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */
+#define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */
+#define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */
+#define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */
+
+/* Register: SAADC_OVERSAMPLE */
+/* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */
+
+/* Bits 3..0 : Oversample control */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */
+
+/* Register: SAADC_SAMPLERATE */
+/* Description: Controls normal or continuous sample rate */
+
+/* Bit 12 : Select mode for sample rate control */
+#define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */
+#define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */
+#define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */
+
+/* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */
+#define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */
+#define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */
+
+/* Register: SAADC_RESULT_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SAADC_RESULT_MAXCNT */
+/* Description: Maximum number of buffer words to transfer */
+
+/* Bits 14..0 : Maximum number of buffer words to transfer */
+#define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SAADC_RESULT_AMOUNT */
+/* Description: Number of buffer words transferred since last START */
+
+/* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */
+#define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+
+/* Peripheral: SPIM */
+/* Description: Serial Peripheral Interface Master with EasyDMA 0 */
+
+/* Register: SPIM_TASKS_START */
+/* Description: Start SPI transaction */
+
+/* Bit 0 : Start SPI transaction */
+#define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define SPIM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SPIM_TASKS_STOP */
+/* Description: Stop SPI transaction */
+
+/* Bit 0 : Stop SPI transaction */
+#define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define SPIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SPIM_TASKS_SUSPEND */
+/* Description: Suspend SPI transaction */
+
+/* Bit 0 : Suspend SPI transaction */
+#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
+#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
+#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SPIM_TASKS_RESUME */
+/* Description: Resume SPI transaction */
+
+/* Bit 0 : Resume SPI transaction */
+#define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
+#define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
+#define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SPIM_SUBSCRIBE_START */
+/* Description: Subscribe configuration for task START */
+
+/* Bit 31 : */
+#define SPIM_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
+#define SPIM_SUBSCRIBE_START_EN_Msk (0x1UL << SPIM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
+#define SPIM_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
+#define SPIM_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task START will subscribe to */
+#define SPIM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define SPIM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: SPIM_SUBSCRIBE_STOP */
+/* Description: Subscribe configuration for task STOP */
+
+/* Bit 31 : */
+#define SPIM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
+#define SPIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << SPIM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
+#define SPIM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
+#define SPIM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
+#define SPIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define SPIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: SPIM_SUBSCRIBE_SUSPEND */
+/* Description: Subscribe configuration for task SUSPEND */
+
+/* Bit 31 : */
+#define SPIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */
+#define SPIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << SPIM_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */
+#define SPIM_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */
+#define SPIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */
+#define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: SPIM_SUBSCRIBE_RESUME */
+/* Description: Subscribe configuration for task RESUME */
+
+/* Bit 31 : */
+#define SPIM_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */
+#define SPIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << SPIM_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */
+#define SPIM_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */
+#define SPIM_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task RESUME will subscribe to */
+#define SPIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define SPIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: SPIM_EVENTS_STOPPED */
+/* Description: SPI transaction has stopped */
+
+/* Bit 0 : SPI transaction has stopped */
+#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
+#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
+#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: SPIM_EVENTS_ENDRX */
+/* Description: End of RXD buffer reached */
+
+/* Bit 0 : End of RXD buffer reached */
+#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
+#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
+#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
+#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
+
+/* Register: SPIM_EVENTS_END */
+/* Description: End of RXD buffer and TXD buffer reached */
+
+/* Bit 0 : End of RXD buffer and TXD buffer reached */
+#define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
+#define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
+#define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
+#define SPIM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
+
+/* Register: SPIM_EVENTS_ENDTX */
+/* Description: End of TXD buffer reached */
+
+/* Bit 0 : End of TXD buffer reached */
+#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
+#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
+#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
+#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
+
+/* Register: SPIM_EVENTS_STARTED */
+/* Description: Transaction started */
+
+/* Bit 0 : Transaction started */
+#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
+#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
+#define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
+#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: SPIM_PUBLISH_STOPPED */
+/* Description: Publish configuration for event STOPPED */
+
+/* Bit 31 : */
+#define SPIM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
+#define SPIM_PUBLISH_STOPPED_EN_Msk (0x1UL << SPIM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
+#define SPIM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
+#define SPIM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event STOPPED will publish to */
+#define SPIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define SPIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: SPIM_PUBLISH_ENDRX */
+/* Description: Publish configuration for event ENDRX */
+
+/* Bit 31 : */
+#define SPIM_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */
+#define SPIM_PUBLISH_ENDRX_EN_Msk (0x1UL << SPIM_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */
+#define SPIM_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */
+#define SPIM_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event ENDRX will publish to */
+#define SPIM_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define SPIM_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: SPIM_PUBLISH_END */
+/* Description: Publish configuration for event END */
+
+/* Bit 31 : */
+#define SPIM_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */
+#define SPIM_PUBLISH_END_EN_Msk (0x1UL << SPIM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */
+#define SPIM_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */
+#define SPIM_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event END will publish to */
+#define SPIM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define SPIM_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: SPIM_PUBLISH_ENDTX */
+/* Description: Publish configuration for event ENDTX */
+
+/* Bit 31 : */
+#define SPIM_PUBLISH_ENDTX_EN_Pos (31UL) /*!< Position of EN field. */
+#define SPIM_PUBLISH_ENDTX_EN_Msk (0x1UL << SPIM_PUBLISH_ENDTX_EN_Pos) /*!< Bit mask of EN field. */
+#define SPIM_PUBLISH_ENDTX_EN_Disabled (0UL) /*!< Disable publishing */
+#define SPIM_PUBLISH_ENDTX_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event ENDTX will publish to */
+#define SPIM_PUBLISH_ENDTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define SPIM_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: SPIM_PUBLISH_STARTED */
+/* Description: Publish configuration for event STARTED */
+
+/* Bit 31 : */
+#define SPIM_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */
+#define SPIM_PUBLISH_STARTED_EN_Msk (0x1UL << SPIM_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */
+#define SPIM_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */
+#define SPIM_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event STARTED will publish to */
+#define SPIM_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define SPIM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: SPIM_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 17 : Shortcut between event END and task START */
+#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
+#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
+#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
+#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: SPIM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 19 : Write '1' to enable interrupt for event STARTED */
+#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
+#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to enable interrupt for event ENDTX */
+#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to enable interrupt for event END */
+#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
+#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to enable interrupt for event ENDRX */
+#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event STOPPED */
+#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: SPIM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 19 : Write '1' to disable interrupt for event STARTED */
+#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
+#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to disable interrupt for event ENDTX */
+#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to disable interrupt for event END */
+#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
+#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to disable interrupt for event ENDRX */
+#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event STOPPED */
+#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: SPIM_ENABLE */
+/* Description: Enable SPIM */
+
+/* Bits 3..0 : Enable or disable SPIM */
+#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */
+#define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */
+
+/* Register: SPIM_PSEL_SCK */
+/* Description: Pin select for SCK */
+
+/* Bit 31 : Connection */
+#define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIM_PSEL_MOSI */
+/* Description: Pin select for MOSI signal */
+
+/* Bit 31 : Connection */
+#define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIM_PSEL_MISO */
+/* Description: Pin select for MISO signal */
+
+/* Bit 31 : Connection */
+#define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIM_FREQUENCY */
+/* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
+
+/* Bits 31..0 : SPI master data rate */
+#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
+#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
+#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
+#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
+#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
+#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
+#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
+
+/* Register: SPIM_RXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIM_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 12..0 : Maximum number of bytes in receive buffer */
+#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIM_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 12..0 : Number of bytes transferred in the last transaction */
+#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIM_RXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 1..0 : List type */
+#define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define SPIM_RXD_LIST_LIST_Msk (0x3UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: SPIM_TXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIM_TXD_MAXCNT */
+/* Description: Maximum number of bytes in transmit buffer */
+
+/* Bits 12..0 : Maximum number of bytes in transmit buffer */
+#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIM_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 12..0 : Number of bytes transferred in the last transaction */
+#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIM_TXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 1..0 : List type */
+#define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define SPIM_TXD_LIST_LIST_Msk (0x3UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: SPIM_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 2 : Serial clock (SCK) polarity */
+#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
+#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
+
+/* Bit 1 : Serial clock (SCK) phase */
+#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
+#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
+
+/* Bit 0 : Bit order */
+#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
+#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
+
+/* Register: SPIM_ORC */
+/* Description: Over-read character. Character clocked out in case an over-read of the TXD buffer. */
+
+/* Bits 7..0 : Over-read character. Character clocked out in case an over-read of the TXD buffer. */
+#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
+#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
+
+
+/* Peripheral: SPIS */
+/* Description: SPI Slave 0 */
+
+/* Register: SPIS_TASKS_ACQUIRE */
+/* Description: Acquire SPI semaphore */
+
+/* Bit 0 : Acquire SPI semaphore */
+#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */
+#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */
+#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SPIS_TASKS_RELEASE */
+/* Description: Release SPI semaphore, enabling the SPI slave to acquire it */
+
+/* Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */
+#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */
+#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */
+#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: SPIS_SUBSCRIBE_ACQUIRE */
+/* Description: Subscribe configuration for task ACQUIRE */
+
+/* Bit 31 : */
+#define SPIS_SUBSCRIBE_ACQUIRE_EN_Pos (31UL) /*!< Position of EN field. */
+#define SPIS_SUBSCRIBE_ACQUIRE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_ACQUIRE_EN_Pos) /*!< Bit mask of EN field. */
+#define SPIS_SUBSCRIBE_ACQUIRE_EN_Disabled (0UL) /*!< Disable subscription */
+#define SPIS_SUBSCRIBE_ACQUIRE_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task ACQUIRE will subscribe to */
+#define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: SPIS_SUBSCRIBE_RELEASE */
+/* Description: Subscribe configuration for task RELEASE */
+
+/* Bit 31 : */
+#define SPIS_SUBSCRIBE_RELEASE_EN_Pos (31UL) /*!< Position of EN field. */
+#define SPIS_SUBSCRIBE_RELEASE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_RELEASE_EN_Pos) /*!< Bit mask of EN field. */
+#define SPIS_SUBSCRIBE_RELEASE_EN_Disabled (0UL) /*!< Disable subscription */
+#define SPIS_SUBSCRIBE_RELEASE_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task RELEASE will subscribe to */
+#define SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define SPIS_SUBSCRIBE_RELEASE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: SPIS_EVENTS_END */
+/* Description: Granted transaction completed */
+
+/* Bit 0 : Granted transaction completed */
+#define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
+#define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
+#define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
+#define SPIS_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
+
+/* Register: SPIS_EVENTS_ENDRX */
+/* Description: End of RXD buffer reached */
+
+/* Bit 0 : End of RXD buffer reached */
+#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
+#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
+#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
+#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
+
+/* Register: SPIS_EVENTS_ACQUIRED */
+/* Description: Semaphore acquired */
+
+/* Bit 0 : Semaphore acquired */
+#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */
+#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */
+#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0UL) /*!< Event not generated */
+#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (1UL) /*!< Event generated */
+
+/* Register: SPIS_PUBLISH_END */
+/* Description: Publish configuration for event END */
+
+/* Bit 31 : */
+#define SPIS_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */
+#define SPIS_PUBLISH_END_EN_Msk (0x1UL << SPIS_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */
+#define SPIS_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */
+#define SPIS_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event END will publish to */
+#define SPIS_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define SPIS_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: SPIS_PUBLISH_ENDRX */
+/* Description: Publish configuration for event ENDRX */
+
+/* Bit 31 : */
+#define SPIS_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */
+#define SPIS_PUBLISH_ENDRX_EN_Msk (0x1UL << SPIS_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */
+#define SPIS_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */
+#define SPIS_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event ENDRX will publish to */
+#define SPIS_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define SPIS_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: SPIS_PUBLISH_ACQUIRED */
+/* Description: Publish configuration for event ACQUIRED */
+
+/* Bit 31 : */
+#define SPIS_PUBLISH_ACQUIRED_EN_Pos (31UL) /*!< Position of EN field. */
+#define SPIS_PUBLISH_ACQUIRED_EN_Msk (0x1UL << SPIS_PUBLISH_ACQUIRED_EN_Pos) /*!< Bit mask of EN field. */
+#define SPIS_PUBLISH_ACQUIRED_EN_Disabled (0UL) /*!< Disable publishing */
+#define SPIS_PUBLISH_ACQUIRED_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event ACQUIRED will publish to */
+#define SPIS_PUBLISH_ACQUIRED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define SPIS_PUBLISH_ACQUIRED_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ACQUIRED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: SPIS_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 2 : Shortcut between event END and task ACQUIRE */
+#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
+#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
+#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */
+#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: SPIS_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 10 : Write '1' to enable interrupt for event ACQUIRED */
+#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
+#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
+#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to enable interrupt for event ENDRX */
+#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event END */
+#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
+#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Register: SPIS_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 10 : Write '1' to disable interrupt for event ACQUIRED */
+#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
+#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
+#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to disable interrupt for event ENDRX */
+#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event END */
+#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
+#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Register: SPIS_SEMSTAT */
+/* Description: Semaphore status register */
+
+/* Bits 1..0 : Semaphore status */
+#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
+#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
+#define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */
+#define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */
+#define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */
+#define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */
+
+/* Register: SPIS_STATUS */
+/* Description: Status from last transaction */
+
+/* Bit 1 : RX buffer overflow detected, and prevented */
+#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
+#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
+#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */
+#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */
+#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */
+
+/* Bit 0 : TX buffer over-read detected, and prevented */
+#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
+#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
+#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */
+#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */
+#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */
+
+/* Register: SPIS_ENABLE */
+/* Description: Enable SPI slave */
+
+/* Bits 3..0 : Enable or disable SPI slave */
+#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */
+#define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
+
+/* Register: SPIS_PSEL_SCK */
+/* Description: Pin select for SCK */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_PSEL_MISO */
+/* Description: Pin select for MISO signal */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_PSEL_MOSI */
+/* Description: Pin select for MOSI signal */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_PSEL_CSN */
+/* Description: Pin select for CSN signal */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_RXD_PTR */
+/* Description: RXD data pointer */
+
+/* Bits 31..0 : RXD data pointer */
+#define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIS_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 12..0 : Maximum number of bytes in receive buffer */
+#define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIS_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIS_RXD_AMOUNT */
+/* Description: Number of bytes received in last granted transaction */
+
+/* Bits 12..0 : Number of bytes received in the last granted transaction */
+#define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIS_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIS_RXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 1..0 : List type */
+#define SPIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define SPIS_RXD_LIST_LIST_Msk (0x3UL << SPIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define SPIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define SPIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: SPIS_TXD_PTR */
+/* Description: TXD data pointer */
+
+/* Bits 31..0 : TXD data pointer */
+#define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIS_TXD_MAXCNT */
+/* Description: Maximum number of bytes in transmit buffer */
+
+/* Bits 12..0 : Maximum number of bytes in transmit buffer */
+#define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIS_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIS_TXD_AMOUNT */
+/* Description: Number of bytes transmitted in last granted transaction */
+
+/* Bits 12..0 : Number of bytes transmitted in last granted transaction */
+#define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIS_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIS_TXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 1..0 : List type */
+#define SPIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define SPIS_TXD_LIST_LIST_Msk (0x3UL << SPIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define SPIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define SPIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: SPIS_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 2 : Serial clock (SCK) polarity */
+#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
+#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
+
+/* Bit 1 : Serial clock (SCK) phase */
+#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
+#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
+
+/* Bit 0 : Bit order */
+#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
+#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
+
+/* Register: SPIS_DEF */
+/* Description: Default character. Character clocked out in case of an ignored transaction. */
+
+/* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */
+#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
+#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
+
+/* Register: SPIS_ORC */
+/* Description: Over-read character */
+
+/* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */
+#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
+#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
+
+
+/* Peripheral: SPU */
+/* Description: System protection unit */
+
+/* Register: SPU_EVENTS_RAMACCERR */
+/* Description: A security violation has been detected for the RAM memory space */
+
+/* Bit 0 : A security violation has been detected for the RAM memory space */
+#define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Pos (0UL) /*!< Position of EVENTS_RAMACCERR field. */
+#define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Msk (0x1UL << SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Pos) /*!< Bit mask of EVENTS_RAMACCERR field. */
+#define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_NotGenerated (0UL) /*!< Event not generated */
+#define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Generated (1UL) /*!< Event generated */
+
+/* Register: SPU_EVENTS_FLASHACCERR */
+/* Description: A security violation has been detected for the flash memory space */
+
+/* Bit 0 : A security violation has been detected for the flash memory space */
+#define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Pos (0UL) /*!< Position of EVENTS_FLASHACCERR field. */
+#define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Msk (0x1UL << SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Pos) /*!< Bit mask of EVENTS_FLASHACCERR field. */
+#define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_NotGenerated (0UL) /*!< Event not generated */
+#define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Generated (1UL) /*!< Event generated */
+
+/* Register: SPU_EVENTS_PERIPHACCERR */
+/* Description: A security violation has been detected on one or several peripherals */
+
+/* Bit 0 : A security violation has been detected on one or several peripherals */
+#define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos (0UL) /*!< Position of EVENTS_PERIPHACCERR field. */
+#define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Msk (0x1UL << SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos) /*!< Bit mask of EVENTS_PERIPHACCERR field. */
+#define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_NotGenerated (0UL) /*!< Event not generated */
+#define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Generated (1UL) /*!< Event generated */
+
+/* Register: SPU_PUBLISH_RAMACCERR */
+/* Description: Publish configuration for event RAMACCERR */
+
+/* Bit 31 : */
+#define SPU_PUBLISH_RAMACCERR_EN_Pos (31UL) /*!< Position of EN field. */
+#define SPU_PUBLISH_RAMACCERR_EN_Msk (0x1UL << SPU_PUBLISH_RAMACCERR_EN_Pos) /*!< Bit mask of EN field. */
+#define SPU_PUBLISH_RAMACCERR_EN_Disabled (0UL) /*!< Disable publishing */
+#define SPU_PUBLISH_RAMACCERR_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event RAMACCERR will publish to */
+#define SPU_PUBLISH_RAMACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define SPU_PUBLISH_RAMACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_RAMACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: SPU_PUBLISH_FLASHACCERR */
+/* Description: Publish configuration for event FLASHACCERR */
+
+/* Bit 31 : */
+#define SPU_PUBLISH_FLASHACCERR_EN_Pos (31UL) /*!< Position of EN field. */
+#define SPU_PUBLISH_FLASHACCERR_EN_Msk (0x1UL << SPU_PUBLISH_FLASHACCERR_EN_Pos) /*!< Bit mask of EN field. */
+#define SPU_PUBLISH_FLASHACCERR_EN_Disabled (0UL) /*!< Disable publishing */
+#define SPU_PUBLISH_FLASHACCERR_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event FLASHACCERR will publish to */
+#define SPU_PUBLISH_FLASHACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define SPU_PUBLISH_FLASHACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_FLASHACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: SPU_PUBLISH_PERIPHACCERR */
+/* Description: Publish configuration for event PERIPHACCERR */
+
+/* Bit 31 : */
+#define SPU_PUBLISH_PERIPHACCERR_EN_Pos (31UL) /*!< Position of EN field. */
+#define SPU_PUBLISH_PERIPHACCERR_EN_Msk (0x1UL << SPU_PUBLISH_PERIPHACCERR_EN_Pos) /*!< Bit mask of EN field. */
+#define SPU_PUBLISH_PERIPHACCERR_EN_Disabled (0UL) /*!< Disable publishing */
+#define SPU_PUBLISH_PERIPHACCERR_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event PERIPHACCERR will publish to */
+#define SPU_PUBLISH_PERIPHACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define SPU_PUBLISH_PERIPHACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_PERIPHACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: SPU_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 2 : Enable or disable interrupt for event PERIPHACCERR */
+#define SPU_INTEN_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */
+#define SPU_INTEN_PERIPHACCERR_Msk (0x1UL << SPU_INTEN_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */
+#define SPU_INTEN_PERIPHACCERR_Disabled (0UL) /*!< Disable */
+#define SPU_INTEN_PERIPHACCERR_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for event FLASHACCERR */
+#define SPU_INTEN_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */
+#define SPU_INTEN_FLASHACCERR_Msk (0x1UL << SPU_INTEN_FLASHACCERR_Pos) /*!< Bit mask of FLASHACCERR field. */
+#define SPU_INTEN_FLASHACCERR_Disabled (0UL) /*!< Disable */
+#define SPU_INTEN_FLASHACCERR_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for event RAMACCERR */
+#define SPU_INTEN_RAMACCERR_Pos (0UL) /*!< Position of RAMACCERR field. */
+#define SPU_INTEN_RAMACCERR_Msk (0x1UL << SPU_INTEN_RAMACCERR_Pos) /*!< Bit mask of RAMACCERR field. */
+#define SPU_INTEN_RAMACCERR_Disabled (0UL) /*!< Disable */
+#define SPU_INTEN_RAMACCERR_Enabled (1UL) /*!< Enable */
+
+/* Register: SPU_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 2 : Write '1' to enable interrupt for event PERIPHACCERR */
+#define SPU_INTENSET_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */
+#define SPU_INTENSET_PERIPHACCERR_Msk (0x1UL << SPU_INTENSET_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */
+#define SPU_INTENSET_PERIPHACCERR_Disabled (0UL) /*!< Read: Disabled */
+#define SPU_INTENSET_PERIPHACCERR_Enabled (1UL) /*!< Read: Enabled */
+#define SPU_INTENSET_PERIPHACCERR_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event FLASHACCERR */
+#define SPU_INTENSET_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */
+#define SPU_INTENSET_FLASHACCERR_Msk (0x1UL << SPU_INTENSET_FLASHACCERR_Pos) /*!< Bit mask of FLASHACCERR field. */
+#define SPU_INTENSET_FLASHACCERR_Disabled (0UL) /*!< Read: Disabled */
+#define SPU_INTENSET_FLASHACCERR_Enabled (1UL) /*!< Read: Enabled */
+#define SPU_INTENSET_FLASHACCERR_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event RAMACCERR */
+#define SPU_INTENSET_RAMACCERR_Pos (0UL) /*!< Position of RAMACCERR field. */
+#define SPU_INTENSET_RAMACCERR_Msk (0x1UL << SPU_INTENSET_RAMACCERR_Pos) /*!< Bit mask of RAMACCERR field. */
+#define SPU_INTENSET_RAMACCERR_Disabled (0UL) /*!< Read: Disabled */
+#define SPU_INTENSET_RAMACCERR_Enabled (1UL) /*!< Read: Enabled */
+#define SPU_INTENSET_RAMACCERR_Set (1UL) /*!< Enable */
+
+/* Register: SPU_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 2 : Write '1' to disable interrupt for event PERIPHACCERR */
+#define SPU_INTENCLR_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */
+#define SPU_INTENCLR_PERIPHACCERR_Msk (0x1UL << SPU_INTENCLR_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */
+#define SPU_INTENCLR_PERIPHACCERR_Disabled (0UL) /*!< Read: Disabled */
+#define SPU_INTENCLR_PERIPHACCERR_Enabled (1UL) /*!< Read: Enabled */
+#define SPU_INTENCLR_PERIPHACCERR_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event FLASHACCERR */
+#define SPU_INTENCLR_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */
+#define SPU_INTENCLR_FLASHACCERR_Msk (0x1UL << SPU_INTENCLR_FLASHACCERR_Pos) /*!< Bit mask of FLASHACCERR field. */
+#define SPU_INTENCLR_FLASHACCERR_Disabled (0UL) /*!< Read: Disabled */
+#define SPU_INTENCLR_FLASHACCERR_Enabled (1UL) /*!< Read: Enabled */
+#define SPU_INTENCLR_FLASHACCERR_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event RAMACCERR */
+#define SPU_INTENCLR_RAMACCERR_Pos (0UL) /*!< Position of RAMACCERR field. */
+#define SPU_INTENCLR_RAMACCERR_Msk (0x1UL << SPU_INTENCLR_RAMACCERR_Pos) /*!< Bit mask of RAMACCERR field. */
+#define SPU_INTENCLR_RAMACCERR_Disabled (0UL) /*!< Read: Disabled */
+#define SPU_INTENCLR_RAMACCERR_Enabled (1UL) /*!< Read: Enabled */
+#define SPU_INTENCLR_RAMACCERR_Clear (1UL) /*!< Disable */
+
+/* Register: SPU_CAP */
+/* Description: Show implemented features for the current device */
+
+/* Bit 0 : Show ARM TrustZone status */
+#define SPU_CAP_TZM_Pos (0UL) /*!< Position of TZM field. */
+#define SPU_CAP_TZM_Msk (0x1UL << SPU_CAP_TZM_Pos) /*!< Bit mask of TZM field. */
+#define SPU_CAP_TZM_NotAvailable (0UL) /*!< ARM TrustZone support not available */
+#define SPU_CAP_TZM_Enabled (1UL) /*!< ARM TrustZone support is available */
+
+/* Register: SPU_EXTDOMAIN_PERM */
+/* Description: Description cluster: Access for bus access generated from the external domain n List capabilities of the external domain n */
+
+/* Bit 8 : */
+#define SPU_EXTDOMAIN_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */
+#define SPU_EXTDOMAIN_PERM_LOCK_Msk (0x1UL << SPU_EXTDOMAIN_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */
+#define SPU_EXTDOMAIN_PERM_LOCK_Unlocked (0UL) /*!< This register can be updated */
+#define SPU_EXTDOMAIN_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
+
+/* Bit 4 : Peripheral security mapping */
+#define SPU_EXTDOMAIN_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */
+#define SPU_EXTDOMAIN_PERM_SECATTR_Msk (0x1UL << SPU_EXTDOMAIN_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */
+#define SPU_EXTDOMAIN_PERM_SECATTR_NonSecure (0UL) /*!< Bus accesses from this domain have the non-secure attribute set */
+#define SPU_EXTDOMAIN_PERM_SECATTR_Secure (1UL) /*!< Bus accesses from this domain have secure attribute set */
+
+/* Bits 1..0 : Define configuration capabilities for TrustZone Cortex-M secure attribute */
+#define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Pos (0UL) /*!< Position of SECUREMAPPING field. */
+#define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Msk (0x3UL << SPU_EXTDOMAIN_PERM_SECUREMAPPING_Pos) /*!< Bit mask of SECUREMAPPING field. */
+#define SPU_EXTDOMAIN_PERM_SECUREMAPPING_NonSecure (0UL) /*!< The bus access from this external domain always have the non-secure attribute set */
+#define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Secure (1UL) /*!< The bus access from this external domain always have the secure attribute set */
+#define SPU_EXTDOMAIN_PERM_SECUREMAPPING_UserSelectable (2UL) /*!< Non-secure or secure attribute for bus access from this domain is defined by the EXTDOMAIN[n].PERM register */
+
+/* Register: SPU_DPPI_PERM */
+/* Description: Description cluster: Select between secure and non-secure attribute for the DPPI channels. */
+
+/* Bit 15 : Select secure attribute. */
+#define SPU_DPPI_PERM_CHANNEL15_Pos (15UL) /*!< Position of CHANNEL15 field. */
+#define SPU_DPPI_PERM_CHANNEL15_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL15_Pos) /*!< Bit mask of CHANNEL15 field. */
+#define SPU_DPPI_PERM_CHANNEL15_NonSecure (0UL) /*!< Channel15 has its non-secure attribute set */
+#define SPU_DPPI_PERM_CHANNEL15_Secure (1UL) /*!< Channel15 has its secure attribute set */
+
+/* Bit 14 : Select secure attribute. */
+#define SPU_DPPI_PERM_CHANNEL14_Pos (14UL) /*!< Position of CHANNEL14 field. */
+#define SPU_DPPI_PERM_CHANNEL14_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL14_Pos) /*!< Bit mask of CHANNEL14 field. */
+#define SPU_DPPI_PERM_CHANNEL14_NonSecure (0UL) /*!< Channel14 has its non-secure attribute set */
+#define SPU_DPPI_PERM_CHANNEL14_Secure (1UL) /*!< Channel14 has its secure attribute set */
+
+/* Bit 13 : Select secure attribute. */
+#define SPU_DPPI_PERM_CHANNEL13_Pos (13UL) /*!< Position of CHANNEL13 field. */
+#define SPU_DPPI_PERM_CHANNEL13_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL13_Pos) /*!< Bit mask of CHANNEL13 field. */
+#define SPU_DPPI_PERM_CHANNEL13_NonSecure (0UL) /*!< Channel13 has its non-secure attribute set */
+#define SPU_DPPI_PERM_CHANNEL13_Secure (1UL) /*!< Channel13 has its secure attribute set */
+
+/* Bit 12 : Select secure attribute. */
+#define SPU_DPPI_PERM_CHANNEL12_Pos (12UL) /*!< Position of CHANNEL12 field. */
+#define SPU_DPPI_PERM_CHANNEL12_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL12_Pos) /*!< Bit mask of CHANNEL12 field. */
+#define SPU_DPPI_PERM_CHANNEL12_NonSecure (0UL) /*!< Channel12 has its non-secure attribute set */
+#define SPU_DPPI_PERM_CHANNEL12_Secure (1UL) /*!< Channel12 has its secure attribute set */
+
+/* Bit 11 : Select secure attribute. */
+#define SPU_DPPI_PERM_CHANNEL11_Pos (11UL) /*!< Position of CHANNEL11 field. */
+#define SPU_DPPI_PERM_CHANNEL11_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL11_Pos) /*!< Bit mask of CHANNEL11 field. */
+#define SPU_DPPI_PERM_CHANNEL11_NonSecure (0UL) /*!< Channel11 has its non-secure attribute set */
+#define SPU_DPPI_PERM_CHANNEL11_Secure (1UL) /*!< Channel11 has its secure attribute set */
+
+/* Bit 10 : Select secure attribute. */
+#define SPU_DPPI_PERM_CHANNEL10_Pos (10UL) /*!< Position of CHANNEL10 field. */
+#define SPU_DPPI_PERM_CHANNEL10_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL10_Pos) /*!< Bit mask of CHANNEL10 field. */
+#define SPU_DPPI_PERM_CHANNEL10_NonSecure (0UL) /*!< Channel10 has its non-secure attribute set */
+#define SPU_DPPI_PERM_CHANNEL10_Secure (1UL) /*!< Channel10 has its secure attribute set */
+
+/* Bit 9 : Select secure attribute. */
+#define SPU_DPPI_PERM_CHANNEL9_Pos (9UL) /*!< Position of CHANNEL9 field. */
+#define SPU_DPPI_PERM_CHANNEL9_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL9_Pos) /*!< Bit mask of CHANNEL9 field. */
+#define SPU_DPPI_PERM_CHANNEL9_NonSecure (0UL) /*!< Channel9 has its non-secure attribute set */
+#define SPU_DPPI_PERM_CHANNEL9_Secure (1UL) /*!< Channel9 has its secure attribute set */
+
+/* Bit 8 : Select secure attribute. */
+#define SPU_DPPI_PERM_CHANNEL8_Pos (8UL) /*!< Position of CHANNEL8 field. */
+#define SPU_DPPI_PERM_CHANNEL8_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL8_Pos) /*!< Bit mask of CHANNEL8 field. */
+#define SPU_DPPI_PERM_CHANNEL8_NonSecure (0UL) /*!< Channel8 has its non-secure attribute set */
+#define SPU_DPPI_PERM_CHANNEL8_Secure (1UL) /*!< Channel8 has its secure attribute set */
+
+/* Bit 7 : Select secure attribute. */
+#define SPU_DPPI_PERM_CHANNEL7_Pos (7UL) /*!< Position of CHANNEL7 field. */
+#define SPU_DPPI_PERM_CHANNEL7_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL7_Pos) /*!< Bit mask of CHANNEL7 field. */
+#define SPU_DPPI_PERM_CHANNEL7_NonSecure (0UL) /*!< Channel7 has its non-secure attribute set */
+#define SPU_DPPI_PERM_CHANNEL7_Secure (1UL) /*!< Channel7 has its secure attribute set */
+
+/* Bit 6 : Select secure attribute. */
+#define SPU_DPPI_PERM_CHANNEL6_Pos (6UL) /*!< Position of CHANNEL6 field. */
+#define SPU_DPPI_PERM_CHANNEL6_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL6_Pos) /*!< Bit mask of CHANNEL6 field. */
+#define SPU_DPPI_PERM_CHANNEL6_NonSecure (0UL) /*!< Channel6 has its non-secure attribute set */
+#define SPU_DPPI_PERM_CHANNEL6_Secure (1UL) /*!< Channel6 has its secure attribute set */
+
+/* Bit 5 : Select secure attribute. */
+#define SPU_DPPI_PERM_CHANNEL5_Pos (5UL) /*!< Position of CHANNEL5 field. */
+#define SPU_DPPI_PERM_CHANNEL5_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL5_Pos) /*!< Bit mask of CHANNEL5 field. */
+#define SPU_DPPI_PERM_CHANNEL5_NonSecure (0UL) /*!< Channel5 has its non-secure attribute set */
+#define SPU_DPPI_PERM_CHANNEL5_Secure (1UL) /*!< Channel5 has its secure attribute set */
+
+/* Bit 4 : Select secure attribute. */
+#define SPU_DPPI_PERM_CHANNEL4_Pos (4UL) /*!< Position of CHANNEL4 field. */
+#define SPU_DPPI_PERM_CHANNEL4_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL4_Pos) /*!< Bit mask of CHANNEL4 field. */
+#define SPU_DPPI_PERM_CHANNEL4_NonSecure (0UL) /*!< Channel4 has its non-secure attribute set */
+#define SPU_DPPI_PERM_CHANNEL4_Secure (1UL) /*!< Channel4 has its secure attribute set */
+
+/* Bit 3 : Select secure attribute. */
+#define SPU_DPPI_PERM_CHANNEL3_Pos (3UL) /*!< Position of CHANNEL3 field. */
+#define SPU_DPPI_PERM_CHANNEL3_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL3_Pos) /*!< Bit mask of CHANNEL3 field. */
+#define SPU_DPPI_PERM_CHANNEL3_NonSecure (0UL) /*!< Channel3 has its non-secure attribute set */
+#define SPU_DPPI_PERM_CHANNEL3_Secure (1UL) /*!< Channel3 has its secure attribute set */
+
+/* Bit 2 : Select secure attribute. */
+#define SPU_DPPI_PERM_CHANNEL2_Pos (2UL) /*!< Position of CHANNEL2 field. */
+#define SPU_DPPI_PERM_CHANNEL2_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL2_Pos) /*!< Bit mask of CHANNEL2 field. */
+#define SPU_DPPI_PERM_CHANNEL2_NonSecure (0UL) /*!< Channel2 has its non-secure attribute set */
+#define SPU_DPPI_PERM_CHANNEL2_Secure (1UL) /*!< Channel2 has its secure attribute set */
+
+/* Bit 1 : Select secure attribute. */
+#define SPU_DPPI_PERM_CHANNEL1_Pos (1UL) /*!< Position of CHANNEL1 field. */
+#define SPU_DPPI_PERM_CHANNEL1_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL1_Pos) /*!< Bit mask of CHANNEL1 field. */
+#define SPU_DPPI_PERM_CHANNEL1_NonSecure (0UL) /*!< Channel1 has its non-secure attribute set */
+#define SPU_DPPI_PERM_CHANNEL1_Secure (1UL) /*!< Channel1 has its secure attribute set */
+
+/* Bit 0 : Select secure attribute. */
+#define SPU_DPPI_PERM_CHANNEL0_Pos (0UL) /*!< Position of CHANNEL0 field. */
+#define SPU_DPPI_PERM_CHANNEL0_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL0_Pos) /*!< Bit mask of CHANNEL0 field. */
+#define SPU_DPPI_PERM_CHANNEL0_NonSecure (0UL) /*!< Channel0 has its non-secure attribute set */
+#define SPU_DPPI_PERM_CHANNEL0_Secure (1UL) /*!< Channel0 has its secure attribute set */
+
+/* Register: SPU_DPPI_LOCK */
+/* Description: Description cluster: Prevent further modification of the corresponding PERM register */
+
+/* Bit 0 : */
+#define SPU_DPPI_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */
+#define SPU_DPPI_LOCK_LOCK_Msk (0x1UL << SPU_DPPI_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */
+#define SPU_DPPI_LOCK_LOCK_Unlocked (0UL) /*!< DPPI[n].PERM register content can be changed */
+#define SPU_DPPI_LOCK_LOCK_Locked (1UL) /*!< DPPI[n].PERM register can't be changed until next reset */
+
+/* Register: SPU_GPIOPORT_PERM */
+/* Description: Description cluster: Select between secure and non-secure attribute for pins 0 to 31 of port n. */
+
+/* Bit 31 : Select secure attribute attribute for PIN 31. */
+#define SPU_GPIOPORT_PERM_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define SPU_GPIOPORT_PERM_PIN31_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define SPU_GPIOPORT_PERM_PIN31_NonSecure (0UL) /*!< Pin 31 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN31_Secure (1UL) /*!< Pin 31 has its secure attribute set */
+
+/* Bit 30 : Select secure attribute attribute for PIN 30. */
+#define SPU_GPIOPORT_PERM_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define SPU_GPIOPORT_PERM_PIN30_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define SPU_GPIOPORT_PERM_PIN30_NonSecure (0UL) /*!< Pin 30 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN30_Secure (1UL) /*!< Pin 30 has its secure attribute set */
+
+/* Bit 29 : Select secure attribute attribute for PIN 29. */
+#define SPU_GPIOPORT_PERM_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define SPU_GPIOPORT_PERM_PIN29_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define SPU_GPIOPORT_PERM_PIN29_NonSecure (0UL) /*!< Pin 29 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN29_Secure (1UL) /*!< Pin 29 has its secure attribute set */
+
+/* Bit 28 : Select secure attribute attribute for PIN 28. */
+#define SPU_GPIOPORT_PERM_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define SPU_GPIOPORT_PERM_PIN28_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define SPU_GPIOPORT_PERM_PIN28_NonSecure (0UL) /*!< Pin 28 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN28_Secure (1UL) /*!< Pin 28 has its secure attribute set */
+
+/* Bit 27 : Select secure attribute attribute for PIN 27. */
+#define SPU_GPIOPORT_PERM_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define SPU_GPIOPORT_PERM_PIN27_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define SPU_GPIOPORT_PERM_PIN27_NonSecure (0UL) /*!< Pin 27 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN27_Secure (1UL) /*!< Pin 27 has its secure attribute set */
+
+/* Bit 26 : Select secure attribute attribute for PIN 26. */
+#define SPU_GPIOPORT_PERM_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define SPU_GPIOPORT_PERM_PIN26_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define SPU_GPIOPORT_PERM_PIN26_NonSecure (0UL) /*!< Pin 26 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN26_Secure (1UL) /*!< Pin 26 has its secure attribute set */
+
+/* Bit 25 : Select secure attribute attribute for PIN 25. */
+#define SPU_GPIOPORT_PERM_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define SPU_GPIOPORT_PERM_PIN25_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define SPU_GPIOPORT_PERM_PIN25_NonSecure (0UL) /*!< Pin 25 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN25_Secure (1UL) /*!< Pin 25 has its secure attribute set */
+
+/* Bit 24 : Select secure attribute attribute for PIN 24. */
+#define SPU_GPIOPORT_PERM_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define SPU_GPIOPORT_PERM_PIN24_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define SPU_GPIOPORT_PERM_PIN24_NonSecure (0UL) /*!< Pin 24 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN24_Secure (1UL) /*!< Pin 24 has its secure attribute set */
+
+/* Bit 23 : Select secure attribute attribute for PIN 23. */
+#define SPU_GPIOPORT_PERM_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define SPU_GPIOPORT_PERM_PIN23_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define SPU_GPIOPORT_PERM_PIN23_NonSecure (0UL) /*!< Pin 23 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN23_Secure (1UL) /*!< Pin 23 has its secure attribute set */
+
+/* Bit 22 : Select secure attribute attribute for PIN 22. */
+#define SPU_GPIOPORT_PERM_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define SPU_GPIOPORT_PERM_PIN22_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define SPU_GPIOPORT_PERM_PIN22_NonSecure (0UL) /*!< Pin 22 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN22_Secure (1UL) /*!< Pin 22 has its secure attribute set */
+
+/* Bit 21 : Select secure attribute attribute for PIN 21. */
+#define SPU_GPIOPORT_PERM_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define SPU_GPIOPORT_PERM_PIN21_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define SPU_GPIOPORT_PERM_PIN21_NonSecure (0UL) /*!< Pin 21 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN21_Secure (1UL) /*!< Pin 21 has its secure attribute set */
+
+/* Bit 20 : Select secure attribute attribute for PIN 20. */
+#define SPU_GPIOPORT_PERM_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define SPU_GPIOPORT_PERM_PIN20_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define SPU_GPIOPORT_PERM_PIN20_NonSecure (0UL) /*!< Pin 20 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN20_Secure (1UL) /*!< Pin 20 has its secure attribute set */
+
+/* Bit 19 : Select secure attribute attribute for PIN 19. */
+#define SPU_GPIOPORT_PERM_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define SPU_GPIOPORT_PERM_PIN19_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define SPU_GPIOPORT_PERM_PIN19_NonSecure (0UL) /*!< Pin 19 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN19_Secure (1UL) /*!< Pin 19 has its secure attribute set */
+
+/* Bit 18 : Select secure attribute attribute for PIN 18. */
+#define SPU_GPIOPORT_PERM_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define SPU_GPIOPORT_PERM_PIN18_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define SPU_GPIOPORT_PERM_PIN18_NonSecure (0UL) /*!< Pin 18 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN18_Secure (1UL) /*!< Pin 18 has its secure attribute set */
+
+/* Bit 17 : Select secure attribute attribute for PIN 17. */
+#define SPU_GPIOPORT_PERM_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define SPU_GPIOPORT_PERM_PIN17_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define SPU_GPIOPORT_PERM_PIN17_NonSecure (0UL) /*!< Pin 17 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN17_Secure (1UL) /*!< Pin 17 has its secure attribute set */
+
+/* Bit 16 : Select secure attribute attribute for PIN 16. */
+#define SPU_GPIOPORT_PERM_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define SPU_GPIOPORT_PERM_PIN16_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define SPU_GPIOPORT_PERM_PIN16_NonSecure (0UL) /*!< Pin 16 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN16_Secure (1UL) /*!< Pin 16 has its secure attribute set */
+
+/* Bit 15 : Select secure attribute attribute for PIN 15. */
+#define SPU_GPIOPORT_PERM_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define SPU_GPIOPORT_PERM_PIN15_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define SPU_GPIOPORT_PERM_PIN15_NonSecure (0UL) /*!< Pin 15 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN15_Secure (1UL) /*!< Pin 15 has its secure attribute set */
+
+/* Bit 14 : Select secure attribute attribute for PIN 14. */
+#define SPU_GPIOPORT_PERM_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define SPU_GPIOPORT_PERM_PIN14_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define SPU_GPIOPORT_PERM_PIN14_NonSecure (0UL) /*!< Pin 14 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN14_Secure (1UL) /*!< Pin 14 has its secure attribute set */
+
+/* Bit 13 : Select secure attribute attribute for PIN 13. */
+#define SPU_GPIOPORT_PERM_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define SPU_GPIOPORT_PERM_PIN13_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define SPU_GPIOPORT_PERM_PIN13_NonSecure (0UL) /*!< Pin 13 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN13_Secure (1UL) /*!< Pin 13 has its secure attribute set */
+
+/* Bit 12 : Select secure attribute attribute for PIN 12. */
+#define SPU_GPIOPORT_PERM_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define SPU_GPIOPORT_PERM_PIN12_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define SPU_GPIOPORT_PERM_PIN12_NonSecure (0UL) /*!< Pin 12 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN12_Secure (1UL) /*!< Pin 12 has its secure attribute set */
+
+/* Bit 11 : Select secure attribute attribute for PIN 11. */
+#define SPU_GPIOPORT_PERM_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define SPU_GPIOPORT_PERM_PIN11_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define SPU_GPIOPORT_PERM_PIN11_NonSecure (0UL) /*!< Pin 11 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN11_Secure (1UL) /*!< Pin 11 has its secure attribute set */
+
+/* Bit 10 : Select secure attribute attribute for PIN 10. */
+#define SPU_GPIOPORT_PERM_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define SPU_GPIOPORT_PERM_PIN10_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define SPU_GPIOPORT_PERM_PIN10_NonSecure (0UL) /*!< Pin 10 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN10_Secure (1UL) /*!< Pin 10 has its secure attribute set */
+
+/* Bit 9 : Select secure attribute attribute for PIN 9. */
+#define SPU_GPIOPORT_PERM_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define SPU_GPIOPORT_PERM_PIN9_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define SPU_GPIOPORT_PERM_PIN9_NonSecure (0UL) /*!< Pin 9 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN9_Secure (1UL) /*!< Pin 9 has its secure attribute set */
+
+/* Bit 8 : Select secure attribute attribute for PIN 8. */
+#define SPU_GPIOPORT_PERM_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define SPU_GPIOPORT_PERM_PIN8_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define SPU_GPIOPORT_PERM_PIN8_NonSecure (0UL) /*!< Pin 8 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN8_Secure (1UL) /*!< Pin 8 has its secure attribute set */
+
+/* Bit 7 : Select secure attribute attribute for PIN 7. */
+#define SPU_GPIOPORT_PERM_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define SPU_GPIOPORT_PERM_PIN7_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define SPU_GPIOPORT_PERM_PIN7_NonSecure (0UL) /*!< Pin 7 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN7_Secure (1UL) /*!< Pin 7 has its secure attribute set */
+
+/* Bit 6 : Select secure attribute attribute for PIN 6. */
+#define SPU_GPIOPORT_PERM_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define SPU_GPIOPORT_PERM_PIN6_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define SPU_GPIOPORT_PERM_PIN6_NonSecure (0UL) /*!< Pin 6 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN6_Secure (1UL) /*!< Pin 6 has its secure attribute set */
+
+/* Bit 5 : Select secure attribute attribute for PIN 5. */
+#define SPU_GPIOPORT_PERM_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define SPU_GPIOPORT_PERM_PIN5_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define SPU_GPIOPORT_PERM_PIN5_NonSecure (0UL) /*!< Pin 5 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN5_Secure (1UL) /*!< Pin 5 has its secure attribute set */
+
+/* Bit 4 : Select secure attribute attribute for PIN 4. */
+#define SPU_GPIOPORT_PERM_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define SPU_GPIOPORT_PERM_PIN4_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define SPU_GPIOPORT_PERM_PIN4_NonSecure (0UL) /*!< Pin 4 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN4_Secure (1UL) /*!< Pin 4 has its secure attribute set */
+
+/* Bit 3 : Select secure attribute attribute for PIN 3. */
+#define SPU_GPIOPORT_PERM_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define SPU_GPIOPORT_PERM_PIN3_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define SPU_GPIOPORT_PERM_PIN3_NonSecure (0UL) /*!< Pin 3 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN3_Secure (1UL) /*!< Pin 3 has its secure attribute set */
+
+/* Bit 2 : Select secure attribute attribute for PIN 2. */
+#define SPU_GPIOPORT_PERM_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define SPU_GPIOPORT_PERM_PIN2_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define SPU_GPIOPORT_PERM_PIN2_NonSecure (0UL) /*!< Pin 2 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN2_Secure (1UL) /*!< Pin 2 has its secure attribute set */
+
+/* Bit 1 : Select secure attribute attribute for PIN 1. */
+#define SPU_GPIOPORT_PERM_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define SPU_GPIOPORT_PERM_PIN1_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define SPU_GPIOPORT_PERM_PIN1_NonSecure (0UL) /*!< Pin 1 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN1_Secure (1UL) /*!< Pin 1 has its secure attribute set */
+
+/* Bit 0 : Select secure attribute attribute for PIN 0. */
+#define SPU_GPIOPORT_PERM_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define SPU_GPIOPORT_PERM_PIN0_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define SPU_GPIOPORT_PERM_PIN0_NonSecure (0UL) /*!< Pin 0 has its non-secure attribute set */
+#define SPU_GPIOPORT_PERM_PIN0_Secure (1UL) /*!< Pin 0 has its secure attribute set */
+
+/* Register: SPU_GPIOPORT_LOCK */
+/* Description: Description cluster: Prevent further modification of the corresponding PERM register */
+
+/* Bit 0 : */
+#define SPU_GPIOPORT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */
+#define SPU_GPIOPORT_LOCK_LOCK_Msk (0x1UL << SPU_GPIOPORT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */
+#define SPU_GPIOPORT_LOCK_LOCK_Unlocked (0UL) /*!< GPIOPORT[n].PERM register content can be changed */
+#define SPU_GPIOPORT_LOCK_LOCK_Locked (1UL) /*!< GPIOPORT[n].PERM register can't be changed until next reset */
+
+/* Register: SPU_FLASHNSC_REGION */
+/* Description: Description cluster: Define which flash region can contain the non-secure callable (NSC) region n */
+
+/* Bit 8 : */
+#define SPU_FLASHNSC_REGION_LOCK_Pos (8UL) /*!< Position of LOCK field. */
+#define SPU_FLASHNSC_REGION_LOCK_Msk (0x1UL << SPU_FLASHNSC_REGION_LOCK_Pos) /*!< Bit mask of LOCK field. */
+#define SPU_FLASHNSC_REGION_LOCK_Unlocked (0UL) /*!< This register can be updated */
+#define SPU_FLASHNSC_REGION_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
+
+/* Bits 4..0 : Region number */
+#define SPU_FLASHNSC_REGION_REGION_Pos (0UL) /*!< Position of REGION field. */
+#define SPU_FLASHNSC_REGION_REGION_Msk (0x1FUL << SPU_FLASHNSC_REGION_REGION_Pos) /*!< Bit mask of REGION field. */
+
+/* Register: SPU_FLASHNSC_SIZE */
+/* Description: Description cluster: Define the size of the non-secure callable (NSC) region n */
+
+/* Bit 8 : */
+#define SPU_FLASHNSC_SIZE_LOCK_Pos (8UL) /*!< Position of LOCK field. */
+#define SPU_FLASHNSC_SIZE_LOCK_Msk (0x1UL << SPU_FLASHNSC_SIZE_LOCK_Pos) /*!< Bit mask of LOCK field. */
+#define SPU_FLASHNSC_SIZE_LOCK_Unlocked (0UL) /*!< This register can be updated */
+#define SPU_FLASHNSC_SIZE_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
+
+/* Bits 3..0 : Size of the non-secure callable (NSC) region n */
+#define SPU_FLASHNSC_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
+#define SPU_FLASHNSC_SIZE_SIZE_Msk (0xFUL << SPU_FLASHNSC_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */
+#define SPU_FLASHNSC_SIZE_SIZE_Disabled (0UL) /*!< The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. */
+#define SPU_FLASHNSC_SIZE_SIZE_32 (1UL) /*!< The region n is defined as non-secure callable with a 32-byte size */
+#define SPU_FLASHNSC_SIZE_SIZE_64 (2UL) /*!< The region n is defined as non-secure callable with a 64-byte size */
+#define SPU_FLASHNSC_SIZE_SIZE_128 (3UL) /*!< The region n is defined as non-secure callable with a 128-byte size */
+#define SPU_FLASHNSC_SIZE_SIZE_256 (4UL) /*!< The region n is defined as non-secure callable with a 256-byte size */
+#define SPU_FLASHNSC_SIZE_SIZE_512 (5UL) /*!< The region n is defined as non-secure callable with a 512-byte size */
+#define SPU_FLASHNSC_SIZE_SIZE_1024 (6UL) /*!< The region n is defined as non-secure callable with a 1024-byte size */
+#define SPU_FLASHNSC_SIZE_SIZE_2048 (7UL) /*!< The region n is defined as non-secure callable with a 2048-byte size */
+#define SPU_FLASHNSC_SIZE_SIZE_4096 (8UL) /*!< The region n is defined as non-secure callable with a 4096-byte size */
+
+/* Register: SPU_RAMNSC_REGION */
+/* Description: Description cluster: Define which RAM region can contain the non-secure callable (NSC) region n */
+
+/* Bit 8 : */
+#define SPU_RAMNSC_REGION_LOCK_Pos (8UL) /*!< Position of LOCK field. */
+#define SPU_RAMNSC_REGION_LOCK_Msk (0x1UL << SPU_RAMNSC_REGION_LOCK_Pos) /*!< Bit mask of LOCK field. */
+#define SPU_RAMNSC_REGION_LOCK_Unlocked (0UL) /*!< This register can be updated */
+#define SPU_RAMNSC_REGION_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
+
+/* Bits 4..0 : Region number */
+#define SPU_RAMNSC_REGION_REGION_Pos (0UL) /*!< Position of REGION field. */
+#define SPU_RAMNSC_REGION_REGION_Msk (0x1FUL << SPU_RAMNSC_REGION_REGION_Pos) /*!< Bit mask of REGION field. */
+
+/* Register: SPU_RAMNSC_SIZE */
+/* Description: Description cluster: Define the size of the non-secure callable (NSC) region n */
+
+/* Bit 8 : */
+#define SPU_RAMNSC_SIZE_LOCK_Pos (8UL) /*!< Position of LOCK field. */
+#define SPU_RAMNSC_SIZE_LOCK_Msk (0x1UL << SPU_RAMNSC_SIZE_LOCK_Pos) /*!< Bit mask of LOCK field. */
+#define SPU_RAMNSC_SIZE_LOCK_Unlocked (0UL) /*!< This register can be updated */
+#define SPU_RAMNSC_SIZE_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
+
+/* Bits 3..0 : Size of the non-secure callable (NSC) region n */
+#define SPU_RAMNSC_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
+#define SPU_RAMNSC_SIZE_SIZE_Msk (0xFUL << SPU_RAMNSC_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */
+#define SPU_RAMNSC_SIZE_SIZE_Disabled (0UL) /*!< The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. */
+#define SPU_RAMNSC_SIZE_SIZE_32 (1UL) /*!< The region n is defined as non-secure callable with a 32-byte size */
+#define SPU_RAMNSC_SIZE_SIZE_64 (2UL) /*!< The region n is defined as non-secure callable with a 64-byte size */
+#define SPU_RAMNSC_SIZE_SIZE_128 (3UL) /*!< The region n is defined as non-secure callable with a 128-byte size */
+#define SPU_RAMNSC_SIZE_SIZE_256 (4UL) /*!< The region n is defined as non-secure callable with a 256-byte size */
+#define SPU_RAMNSC_SIZE_SIZE_512 (5UL) /*!< The region n is defined as non-secure callable with a 512-byte size */
+#define SPU_RAMNSC_SIZE_SIZE_1024 (6UL) /*!< The region n is defined as non-secure callable with a 1024-byte size */
+#define SPU_RAMNSC_SIZE_SIZE_2048 (7UL) /*!< The region n is defined as non-secure callable with a 2048-byte size */
+#define SPU_RAMNSC_SIZE_SIZE_4096 (8UL) /*!< The region n is defined as non-secure callable with a 4096-byte size */
+
+/* Register: SPU_FLASHREGION_PERM */
+/* Description: Description cluster: Access permissions for flash region n */
+
+/* Bit 8 : */
+#define SPU_FLASHREGION_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */
+#define SPU_FLASHREGION_PERM_LOCK_Msk (0x1UL << SPU_FLASHREGION_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */
+#define SPU_FLASHREGION_PERM_LOCK_Unlocked (0UL) /*!< This register can be updated */
+#define SPU_FLASHREGION_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
+
+/* Bit 4 : Security attribute for flash region n */
+#define SPU_FLASHREGION_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */
+#define SPU_FLASHREGION_PERM_SECATTR_Msk (0x1UL << SPU_FLASHREGION_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */
+#define SPU_FLASHREGION_PERM_SECATTR_Non_Secure (0UL) /*!< Flash region n security attribute is non-secure */
+#define SPU_FLASHREGION_PERM_SECATTR_Secure (1UL) /*!< Flash region n security attribute is secure */
+
+/* Bit 2 : Configure read permissions for flash region n */
+#define SPU_FLASHREGION_PERM_READ_Pos (2UL) /*!< Position of READ field. */
+#define SPU_FLASHREGION_PERM_READ_Msk (0x1UL << SPU_FLASHREGION_PERM_READ_Pos) /*!< Bit mask of READ field. */
+#define SPU_FLASHREGION_PERM_READ_Disable (0UL) /*!< Block read operation from flash region n */
+#define SPU_FLASHREGION_PERM_READ_Enable (1UL) /*!< Allow read operation from flash region n */
+
+/* Bit 1 : Configure write permission for flash region n */
+#define SPU_FLASHREGION_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */
+#define SPU_FLASHREGION_PERM_WRITE_Msk (0x1UL << SPU_FLASHREGION_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */
+#define SPU_FLASHREGION_PERM_WRITE_Disable (0UL) /*!< Block write operation to region n */
+#define SPU_FLASHREGION_PERM_WRITE_Enable (1UL) /*!< Allow write operation to region n */
+
+/* Bit 0 : Configure instruction fetch permissions from flash region n */
+#define SPU_FLASHREGION_PERM_EXECUTE_Pos (0UL) /*!< Position of EXECUTE field. */
+#define SPU_FLASHREGION_PERM_EXECUTE_Msk (0x1UL << SPU_FLASHREGION_PERM_EXECUTE_Pos) /*!< Bit mask of EXECUTE field. */
+#define SPU_FLASHREGION_PERM_EXECUTE_Disable (0UL) /*!< Block instruction fetches from flash region n */
+#define SPU_FLASHREGION_PERM_EXECUTE_Enable (1UL) /*!< Allow instruction fetches from flash region n */
+
+/* Register: SPU_RAMREGION_PERM */
+/* Description: Description cluster: Access permissions for RAM region n */
+
+/* Bit 8 : */
+#define SPU_RAMREGION_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */
+#define SPU_RAMREGION_PERM_LOCK_Msk (0x1UL << SPU_RAMREGION_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */
+#define SPU_RAMREGION_PERM_LOCK_Unlocked (0UL) /*!< This register can be updated */
+#define SPU_RAMREGION_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
+
+/* Bit 4 : Security attribute for RAM region n */
+#define SPU_RAMREGION_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */
+#define SPU_RAMREGION_PERM_SECATTR_Msk (0x1UL << SPU_RAMREGION_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */
+#define SPU_RAMREGION_PERM_SECATTR_Non_Secure (0UL) /*!< RAM region n security attribute is non-secure */
+#define SPU_RAMREGION_PERM_SECATTR_Secure (1UL) /*!< RAM region n security attribute is secure */
+
+/* Bit 2 : Configure read permissions for RAM region n */
+#define SPU_RAMREGION_PERM_READ_Pos (2UL) /*!< Position of READ field. */
+#define SPU_RAMREGION_PERM_READ_Msk (0x1UL << SPU_RAMREGION_PERM_READ_Pos) /*!< Bit mask of READ field. */
+#define SPU_RAMREGION_PERM_READ_Disable (0UL) /*!< Block read operation from RAM region n */
+#define SPU_RAMREGION_PERM_READ_Enable (1UL) /*!< Allow read operation from RAM region n */
+
+/* Bit 1 : Configure write permission for RAM region n */
+#define SPU_RAMREGION_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */
+#define SPU_RAMREGION_PERM_WRITE_Msk (0x1UL << SPU_RAMREGION_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */
+#define SPU_RAMREGION_PERM_WRITE_Disable (0UL) /*!< Block write operation to RAM region n */
+#define SPU_RAMREGION_PERM_WRITE_Enable (1UL) /*!< Allow write operation to RAM region n */
+
+/* Bit 0 : Configure instruction fetch permissions from RAM region n */
+#define SPU_RAMREGION_PERM_EXECUTE_Pos (0UL) /*!< Position of EXECUTE field. */
+#define SPU_RAMREGION_PERM_EXECUTE_Msk (0x1UL << SPU_RAMREGION_PERM_EXECUTE_Pos) /*!< Bit mask of EXECUTE field. */
+#define SPU_RAMREGION_PERM_EXECUTE_Disable (0UL) /*!< Block instruction fetches from RAM region n */
+#define SPU_RAMREGION_PERM_EXECUTE_Enable (1UL) /*!< Allow instruction fetches from RAM region n */
+
+/* Register: SPU_PERIPHID_PERM */
+/* Description: Description cluster: List capabilities and access permissions for the peripheral with ID n */
+
+/* Bit 31 : Indicate if a peripheral is present with ID n */
+#define SPU_PERIPHID_PERM_PRESENT_Pos (31UL) /*!< Position of PRESENT field. */
+#define SPU_PERIPHID_PERM_PRESENT_Msk (0x1UL << SPU_PERIPHID_PERM_PRESENT_Pos) /*!< Bit mask of PRESENT field. */
+#define SPU_PERIPHID_PERM_PRESENT_NotPresent (0UL) /*!< Peripheral is not present */
+#define SPU_PERIPHID_PERM_PRESENT_IsPresent (1UL) /*!< Peripheral is present */
+
+/* Bit 8 : */
+#define SPU_PERIPHID_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */
+#define SPU_PERIPHID_PERM_LOCK_Msk (0x1UL << SPU_PERIPHID_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */
+#define SPU_PERIPHID_PERM_LOCK_Unlocked (0UL) /*!< This register can be updated */
+#define SPU_PERIPHID_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
+
+/* Bit 5 : Security attribution for the DMA transfer */
+#define SPU_PERIPHID_PERM_DMASEC_Pos (5UL) /*!< Position of DMASEC field. */
+#define SPU_PERIPHID_PERM_DMASEC_Msk (0x1UL << SPU_PERIPHID_PERM_DMASEC_Pos) /*!< Bit mask of DMASEC field. */
+#define SPU_PERIPHID_PERM_DMASEC_NonSecure (0UL) /*!< DMA transfers initiated by this peripheral have the non-secure attribute set */
+#define SPU_PERIPHID_PERM_DMASEC_Secure (1UL) /*!< DMA transfers initiated by this peripheral have the secure attribute set */
+
+/* Bit 4 : Peripheral security mapping */
+#define SPU_PERIPHID_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */
+#define SPU_PERIPHID_PERM_SECATTR_Msk (0x1UL << SPU_PERIPHID_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */
+#define SPU_PERIPHID_PERM_SECATTR_NonSecure (0UL) /*!< If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure peripheral address space. If SECUREMAPPING == Split: Peripheral is mapped in non-secure and secure peripheral address space. */
+#define SPU_PERIPHID_PERM_SECATTR_Secure (1UL) /*!< Peripheral is mapped in secure peripheral address space */
+
+/* Bits 3..2 : Indicate if the peripheral has DMA capabilities and if DMA transfer can be assigned to a different security attribute than the peripheral itself */
+#define SPU_PERIPHID_PERM_DMA_Pos (2UL) /*!< Position of DMA field. */
+#define SPU_PERIPHID_PERM_DMA_Msk (0x3UL << SPU_PERIPHID_PERM_DMA_Pos) /*!< Bit mask of DMA field. */
+#define SPU_PERIPHID_PERM_DMA_NoDMA (0UL) /*!< Peripheral has no DMA capability */
+#define SPU_PERIPHID_PERM_DMA_NoSeparateAttribute (1UL) /*!< Peripheral has DMA and DMA transfers always have the same security attribute as assigned to the peripheral */
+#define SPU_PERIPHID_PERM_DMA_SeparateAttribute (2UL) /*!< Peripheral has DMA and DMA transfers can have a different security attribute than the one assigned to the peripheral */
+
+/* Bits 1..0 : Define configuration capabilities for TrustZone Cortex-M secure attribute */
+#define SPU_PERIPHID_PERM_SECUREMAPPING_Pos (0UL) /*!< Position of SECUREMAPPING field. */
+#define SPU_PERIPHID_PERM_SECUREMAPPING_Msk (0x3UL << SPU_PERIPHID_PERM_SECUREMAPPING_Pos) /*!< Bit mask of SECUREMAPPING field. */
+#define SPU_PERIPHID_PERM_SECUREMAPPING_NonSecure (0UL) /*!< This peripheral is always accessible as a non-secure peripheral */
+#define SPU_PERIPHID_PERM_SECUREMAPPING_Secure (1UL) /*!< This peripheral is always accessible as a secure peripheral */
+#define SPU_PERIPHID_PERM_SECUREMAPPING_UserSelectable (2UL) /*!< Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register */
+#define SPU_PERIPHID_PERM_SECUREMAPPING_Split (3UL) /*!< This peripheral implements the split security mechanism. Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register. */
+
+
+/* Peripheral: TAD */
+/* Description: Trace and debug control */
+
+/* Register: TAD_TASKS_CLOCKSTART */
+/* Description: Start all trace and debug clocks. */
+
+/* Bit 0 : Start all trace and debug clocks. */
+#define TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Pos (0UL) /*!< Position of TASKS_CLOCKSTART field. */
+#define TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Msk (0x1UL << TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Pos) /*!< Bit mask of TASKS_CLOCKSTART field. */
+#define TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TAD_TASKS_CLOCKSTOP */
+/* Description: Stop all trace and debug clocks. */
+
+/* Bit 0 : Stop all trace and debug clocks. */
+#define TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Pos (0UL) /*!< Position of TASKS_CLOCKSTOP field. */
+#define TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Msk (0x1UL << TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Pos) /*!< Bit mask of TASKS_CLOCKSTOP field. */
+#define TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TAD_ENABLE */
+/* Description: Enable debug domain and aquire selected GPIOs */
+
+/* Bit 0 : */
+#define TAD_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define TAD_ENABLE_ENABLE_Msk (0x1UL << TAD_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define TAD_ENABLE_ENABLE_DISABLED (0UL) /*!< Disable debug domain and release selected GPIOs */
+#define TAD_ENABLE_ENABLE_ENABLED (1UL) /*!< Enable debug domain and aquire selected GPIOs */
+
+/* Register: TAD_PSEL_TRACECLK */
+/* Description: Pin configuration for TRACECLK */
+
+/* Bit 31 : Connection */
+#define TAD_PSEL_TRACECLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TAD_PSEL_TRACECLK_CONNECT_Msk (0x1UL << TAD_PSEL_TRACECLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TAD_PSEL_TRACECLK_CONNECT_Connected (0UL) /*!< Connect */
+#define TAD_PSEL_TRACECLK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define TAD_PSEL_TRACECLK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TAD_PSEL_TRACECLK_PIN_Msk (0x1FUL << TAD_PSEL_TRACECLK_PIN_Pos) /*!< Bit mask of PIN field. */
+#define TAD_PSEL_TRACECLK_PIN_Traceclk (21UL) /*!< TRACECLK pin */
+
+/* Register: TAD_PSEL_TRACEDATA0 */
+/* Description: Pin configuration for TRACEDATA[0] */
+
+/* Bit 31 : Connection */
+#define TAD_PSEL_TRACEDATA0_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TAD_PSEL_TRACEDATA0_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA0_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TAD_PSEL_TRACEDATA0_CONNECT_Connected (0UL) /*!< Connect */
+#define TAD_PSEL_TRACEDATA0_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define TAD_PSEL_TRACEDATA0_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TAD_PSEL_TRACEDATA0_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA0_PIN_Pos) /*!< Bit mask of PIN field. */
+#define TAD_PSEL_TRACEDATA0_PIN_Tracedata0 (22UL) /*!< TRACEDATA0 pin */
+
+/* Register: TAD_PSEL_TRACEDATA1 */
+/* Description: Pin configuration for TRACEDATA[1] */
+
+/* Bit 31 : Connection */
+#define TAD_PSEL_TRACEDATA1_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TAD_PSEL_TRACEDATA1_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA1_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TAD_PSEL_TRACEDATA1_CONNECT_Connected (0UL) /*!< Connect */
+#define TAD_PSEL_TRACEDATA1_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define TAD_PSEL_TRACEDATA1_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TAD_PSEL_TRACEDATA1_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA1_PIN_Pos) /*!< Bit mask of PIN field. */
+#define TAD_PSEL_TRACEDATA1_PIN_Tracedata1 (23UL) /*!< TRACEDATA1 pin */
+
+/* Register: TAD_PSEL_TRACEDATA2 */
+/* Description: Pin configuration for TRACEDATA[2] */
+
+/* Bit 31 : Connection */
+#define TAD_PSEL_TRACEDATA2_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TAD_PSEL_TRACEDATA2_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA2_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TAD_PSEL_TRACEDATA2_CONNECT_Connected (0UL) /*!< Connect */
+#define TAD_PSEL_TRACEDATA2_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define TAD_PSEL_TRACEDATA2_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TAD_PSEL_TRACEDATA2_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA2_PIN_Pos) /*!< Bit mask of PIN field. */
+#define TAD_PSEL_TRACEDATA2_PIN_Tracedata2 (24UL) /*!< TRACEDATA2 pin */
+
+/* Register: TAD_PSEL_TRACEDATA3 */
+/* Description: Pin configuration for TRACEDATA[3] */
+
+/* Bit 31 : Connection */
+#define TAD_PSEL_TRACEDATA3_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TAD_PSEL_TRACEDATA3_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA3_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TAD_PSEL_TRACEDATA3_CONNECT_Connected (0UL) /*!< Connect */
+#define TAD_PSEL_TRACEDATA3_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define TAD_PSEL_TRACEDATA3_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TAD_PSEL_TRACEDATA3_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA3_PIN_Pos) /*!< Bit mask of PIN field. */
+#define TAD_PSEL_TRACEDATA3_PIN_Tracedata3 (25UL) /*!< TRACEDATA3 pin */
+
+/* Register: TAD_TRACEPORTSPEED */
+/* Description: Clocking options for the Trace Port debug interface Reset behavior is the same as debug components */
+
+/* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock. */
+#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */
+#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Msk (0x3UL << TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */
+#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz (0UL) /*!< Trace Port clock is: 32MHz */
+#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_16MHz (1UL) /*!< Trace Port clock is: 16MHz */
+#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_8MHz (2UL) /*!< Trace Port clock is: 8MHz */
+#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_4MHz (3UL) /*!< Trace Port clock is: 4MHz */
+
+
+/* Peripheral: TIMER */
+/* Description: Timer/Counter 0 */
+
+/* Register: TIMER_TASKS_START */
+/* Description: Start Timer */
+
+/* Bit 0 : Start Timer */
+#define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define TIMER_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TIMER_TASKS_STOP */
+/* Description: Stop Timer */
+
+/* Bit 0 : Stop Timer */
+#define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TIMER_TASKS_COUNT */
+/* Description: Increment Timer (Counter mode only) */
+
+/* Bit 0 : Increment Timer (Counter mode only) */
+#define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */
+#define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */
+#define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TIMER_TASKS_CLEAR */
+/* Description: Clear time */
+
+/* Bit 0 : Clear time */
+#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
+#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
+#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TIMER_TASKS_SHUTDOWN */
+/* Description: Deprecated register - Shut down timer */
+
+/* Bit 0 : Deprecated field - Shut down timer */
+#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */
+#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */
+#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TIMER_TASKS_CAPTURE */
+/* Description: Description collection: Capture Timer value to CC[n] register */
+
+/* Bit 0 : Capture Timer value to CC[n] register */
+#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */
+#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */
+#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TIMER_SUBSCRIBE_START */
+/* Description: Subscribe configuration for task START */
+
+/* Bit 31 : */
+#define TIMER_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
+#define TIMER_SUBSCRIBE_START_EN_Msk (0x1UL << TIMER_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
+#define TIMER_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
+#define TIMER_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task START will subscribe to */
+#define TIMER_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define TIMER_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: TIMER_SUBSCRIBE_STOP */
+/* Description: Subscribe configuration for task STOP */
+
+/* Bit 31 : */
+#define TIMER_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
+#define TIMER_SUBSCRIBE_STOP_EN_Msk (0x1UL << TIMER_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
+#define TIMER_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
+#define TIMER_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
+#define TIMER_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define TIMER_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: TIMER_SUBSCRIBE_COUNT */
+/* Description: Subscribe configuration for task COUNT */
+
+/* Bit 31 : */
+#define TIMER_SUBSCRIBE_COUNT_EN_Pos (31UL) /*!< Position of EN field. */
+#define TIMER_SUBSCRIBE_COUNT_EN_Msk (0x1UL << TIMER_SUBSCRIBE_COUNT_EN_Pos) /*!< Bit mask of EN field. */
+#define TIMER_SUBSCRIBE_COUNT_EN_Disabled (0UL) /*!< Disable subscription */
+#define TIMER_SUBSCRIBE_COUNT_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task COUNT will subscribe to */
+#define TIMER_SUBSCRIBE_COUNT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define TIMER_SUBSCRIBE_COUNT_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_COUNT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: TIMER_SUBSCRIBE_CLEAR */
+/* Description: Subscribe configuration for task CLEAR */
+
+/* Bit 31 : */
+#define TIMER_SUBSCRIBE_CLEAR_EN_Pos (31UL) /*!< Position of EN field. */
+#define TIMER_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field. */
+#define TIMER_SUBSCRIBE_CLEAR_EN_Disabled (0UL) /*!< Disable subscription */
+#define TIMER_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */
+#define TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define TIMER_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: TIMER_SUBSCRIBE_SHUTDOWN */
+/* Description: Deprecated register - Subscribe configuration for task SHUTDOWN */
+
+/* Bit 31 : */
+#define TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos (31UL) /*!< Position of EN field. */
+#define TIMER_SUBSCRIBE_SHUTDOWN_EN_Msk (0x1UL << TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos) /*!< Bit mask of EN field. */
+#define TIMER_SUBSCRIBE_SHUTDOWN_EN_Disabled (0UL) /*!< Disable subscription */
+#define TIMER_SUBSCRIBE_SHUTDOWN_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task SHUTDOWN will subscribe to */
+#define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: TIMER_SUBSCRIBE_CAPTURE */
+/* Description: Description collection: Subscribe configuration for task CAPTURE[n] */
+
+/* Bit 31 : */
+#define TIMER_SUBSCRIBE_CAPTURE_EN_Pos (31UL) /*!< Position of EN field. */
+#define TIMER_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CAPTURE_EN_Pos) /*!< Bit mask of EN field. */
+#define TIMER_SUBSCRIBE_CAPTURE_EN_Disabled (0UL) /*!< Disable subscription */
+#define TIMER_SUBSCRIBE_CAPTURE_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task CAPTURE[n] will subscribe to */
+#define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: TIMER_EVENTS_COMPARE */
+/* Description: Description collection: Compare event on CC[n] match */
+
+/* Bit 0 : Compare event on CC[n] match */
+#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
+#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
+#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */
+#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */
+
+/* Register: TIMER_PUBLISH_COMPARE */
+/* Description: Description collection: Publish configuration for event COMPARE[n] */
+
+/* Bit 31 : */
+#define TIMER_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */
+#define TIMER_PUBLISH_COMPARE_EN_Msk (0x1UL << TIMER_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */
+#define TIMER_PUBLISH_COMPARE_EN_Disabled (0UL) /*!< Disable publishing */
+#define TIMER_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to */
+#define TIMER_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define TIMER_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << TIMER_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: TIMER_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 13 : Shortcut between event COMPARE[5] and task STOP */
+#define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */
+#define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */
+#define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 12 : Shortcut between event COMPARE[4] and task STOP */
+#define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */
+#define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */
+#define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 11 : Shortcut between event COMPARE[3] and task STOP */
+#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
+#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
+#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 10 : Shortcut between event COMPARE[2] and task STOP */
+#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
+#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
+#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 9 : Shortcut between event COMPARE[1] and task STOP */
+#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
+#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
+#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 8 : Shortcut between event COMPARE[0] and task STOP */
+#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
+#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
+#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: TIMER_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */
+#define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
+#define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
+#define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */
+#define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
+#define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
+#define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
+#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
+#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
+#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
+#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
+
+/* Register: TIMER_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */
+#define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
+#define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
+#define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */
+#define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
+#define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
+#define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
+#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
+#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
+#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
+#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
+
+/* Register: TIMER_MODE */
+/* Description: Timer mode selection */
+
+/* Bits 1..0 : Timer mode */
+#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */
+#define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator - Select Counter mode */
+#define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */
+
+/* Register: TIMER_BITMODE */
+/* Description: Configure the number of bits used by the TIMER */
+
+/* Bits 1..0 : Timer bit width */
+#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
+#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
+#define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */
+#define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */
+#define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */
+#define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */
+
+/* Register: TIMER_PRESCALER */
+/* Description: Timer prescaler register */
+
+/* Bits 3..0 : Prescaler value */
+#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
+#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+
+/* Register: TIMER_ONESHOTEN */
+/* Description: Description collection: Enable one-shot operation for Capture/Compare channel n */
+
+/* Bit 0 : Enable one-shot operation */
+#define TIMER_ONESHOTEN_ONESHOTEN_Pos (0UL) /*!< Position of ONESHOTEN field. */
+#define TIMER_ONESHOTEN_ONESHOTEN_Msk (0x1UL << TIMER_ONESHOTEN_ONESHOTEN_Pos) /*!< Bit mask of ONESHOTEN field. */
+#define TIMER_ONESHOTEN_ONESHOTEN_Disable (0UL) /*!< Disable one-shot operation */
+#define TIMER_ONESHOTEN_ONESHOTEN_Enable (1UL) /*!< Enable one-shot operation */
+
+/* Register: TIMER_CC */
+/* Description: Description collection: Capture/Compare register n */
+
+/* Bits 31..0 : Capture/Compare value */
+#define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */
+#define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */
+
+
+/* Peripheral: TWIM */
+/* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */
+
+/* Register: TWIM_TASKS_STARTRX */
+/* Description: Start TWI receive sequence */
+
+/* Bit 0 : Start TWI receive sequence */
+#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
+#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
+#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIM_TASKS_STARTTX */
+/* Description: Start TWI transmit sequence */
+
+/* Bit 0 : Start TWI transmit sequence */
+#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
+#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
+#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIM_TASKS_STOP */
+/* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */
+
+/* Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */
+#define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define TWIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIM_TASKS_SUSPEND */
+/* Description: Suspend TWI transaction */
+
+/* Bit 0 : Suspend TWI transaction */
+#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
+#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
+#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIM_TASKS_RESUME */
+/* Description: Resume TWI transaction */
+
+/* Bit 0 : Resume TWI transaction */
+#define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
+#define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
+#define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIM_SUBSCRIBE_STARTRX */
+/* Description: Subscribe configuration for task STARTRX */
+
+/* Bit 31 : */
+#define TWIM_SUBSCRIBE_STARTRX_EN_Pos (31UL) /*!< Position of EN field. */
+#define TWIM_SUBSCRIBE_STARTRX_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STARTRX_EN_Pos) /*!< Bit mask of EN field. */
+#define TWIM_SUBSCRIBE_STARTRX_EN_Disabled (0UL) /*!< Disable subscription */
+#define TWIM_SUBSCRIBE_STARTRX_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task STARTRX will subscribe to */
+#define TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define TWIM_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: TWIM_SUBSCRIBE_STARTTX */
+/* Description: Subscribe configuration for task STARTTX */
+
+/* Bit 31 : */
+#define TWIM_SUBSCRIBE_STARTTX_EN_Pos (31UL) /*!< Position of EN field. */
+#define TWIM_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STARTTX_EN_Pos) /*!< Bit mask of EN field. */
+#define TWIM_SUBSCRIBE_STARTTX_EN_Disabled (0UL) /*!< Disable subscription */
+#define TWIM_SUBSCRIBE_STARTTX_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task STARTTX will subscribe to */
+#define TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define TWIM_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: TWIM_SUBSCRIBE_STOP */
+/* Description: Subscribe configuration for task STOP */
+
+/* Bit 31 : */
+#define TWIM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
+#define TWIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
+#define TWIM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
+#define TWIM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
+#define TWIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define TWIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: TWIM_SUBSCRIBE_SUSPEND */
+/* Description: Subscribe configuration for task SUSPEND */
+
+/* Bit 31 : */
+#define TWIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */
+#define TWIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIM_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */
+#define TWIM_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */
+#define TWIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */
+#define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: TWIM_SUBSCRIBE_RESUME */
+/* Description: Subscribe configuration for task RESUME */
+
+/* Bit 31 : */
+#define TWIM_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */
+#define TWIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIM_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */
+#define TWIM_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */
+#define TWIM_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task RESUME will subscribe to */
+#define TWIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define TWIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: TWIM_EVENTS_STOPPED */
+/* Description: TWI stopped */
+
+/* Bit 0 : TWI stopped */
+#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
+#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
+#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIM_EVENTS_ERROR */
+/* Description: TWI error */
+
+/* Bit 0 : TWI error */
+#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
+#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
+#define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
+#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIM_EVENTS_SUSPENDED */
+/* Description: SUSPEND task has been issued, TWI traffic is now suspended. */
+
+/* Bit 0 : SUSPEND task has been issued, TWI traffic is now suspended. */
+#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */
+#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */
+#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */
+#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIM_EVENTS_RXSTARTED */
+/* Description: Receive sequence started */
+
+/* Bit 0 : Receive sequence started */
+#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
+#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
+#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIM_EVENTS_TXSTARTED */
+/* Description: Transmit sequence started */
+
+/* Bit 0 : Transmit sequence started */
+#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
+#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
+#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIM_EVENTS_LASTRX */
+/* Description: Byte boundary, starting to receive the last byte */
+
+/* Bit 0 : Byte boundary, starting to receive the last byte */
+#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */
+#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */
+#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0UL) /*!< Event not generated */
+#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIM_EVENTS_LASTTX */
+/* Description: Byte boundary, starting to transmit the last byte */
+
+/* Bit 0 : Byte boundary, starting to transmit the last byte */
+#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */
+#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */
+#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0UL) /*!< Event not generated */
+#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIM_PUBLISH_STOPPED */
+/* Description: Publish configuration for event STOPPED */
+
+/* Bit 31 : */
+#define TWIM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
+#define TWIM_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
+#define TWIM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
+#define TWIM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event STOPPED will publish to */
+#define TWIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define TWIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: TWIM_PUBLISH_ERROR */
+/* Description: Publish configuration for event ERROR */
+
+/* Bit 31 : */
+#define TWIM_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */
+#define TWIM_PUBLISH_ERROR_EN_Msk (0x1UL << TWIM_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */
+#define TWIM_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */
+#define TWIM_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event ERROR will publish to */
+#define TWIM_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define TWIM_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: TWIM_PUBLISH_SUSPENDED */
+/* Description: Publish configuration for event SUSPENDED */
+
+/* Bit 31 : */
+#define TWIM_PUBLISH_SUSPENDED_EN_Pos (31UL) /*!< Position of EN field. */
+#define TWIM_PUBLISH_SUSPENDED_EN_Msk (0x1UL << TWIM_PUBLISH_SUSPENDED_EN_Pos) /*!< Bit mask of EN field. */
+#define TWIM_PUBLISH_SUSPENDED_EN_Disabled (0UL) /*!< Disable publishing */
+#define TWIM_PUBLISH_SUSPENDED_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event SUSPENDED will publish to */
+#define TWIM_PUBLISH_SUSPENDED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define TWIM_PUBLISH_SUSPENDED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_SUSPENDED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: TWIM_PUBLISH_RXSTARTED */
+/* Description: Publish configuration for event RXSTARTED */
+
+/* Bit 31 : */
+#define TWIM_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
+#define TWIM_PUBLISH_RXSTARTED_EN_Msk (0x1UL << TWIM_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
+#define TWIM_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
+#define TWIM_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event RXSTARTED will publish to */
+#define TWIM_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define TWIM_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: TWIM_PUBLISH_TXSTARTED */
+/* Description: Publish configuration for event TXSTARTED */
+
+/* Bit 31 : */
+#define TWIM_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
+#define TWIM_PUBLISH_TXSTARTED_EN_Msk (0x1UL << TWIM_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
+#define TWIM_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
+#define TWIM_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event TXSTARTED will publish to */
+#define TWIM_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define TWIM_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: TWIM_PUBLISH_LASTRX */
+/* Description: Publish configuration for event LASTRX */
+
+/* Bit 31 : */
+#define TWIM_PUBLISH_LASTRX_EN_Pos (31UL) /*!< Position of EN field. */
+#define TWIM_PUBLISH_LASTRX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTRX_EN_Pos) /*!< Bit mask of EN field. */
+#define TWIM_PUBLISH_LASTRX_EN_Disabled (0UL) /*!< Disable publishing */
+#define TWIM_PUBLISH_LASTRX_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event LASTRX will publish to */
+#define TWIM_PUBLISH_LASTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define TWIM_PUBLISH_LASTRX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: TWIM_PUBLISH_LASTTX */
+/* Description: Publish configuration for event LASTTX */
+
+/* Bit 31 : */
+#define TWIM_PUBLISH_LASTTX_EN_Pos (31UL) /*!< Position of EN field. */
+#define TWIM_PUBLISH_LASTTX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTTX_EN_Pos) /*!< Bit mask of EN field. */
+#define TWIM_PUBLISH_LASTTX_EN_Disabled (0UL) /*!< Disable publishing */
+#define TWIM_PUBLISH_LASTTX_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event LASTTX will publish to */
+#define TWIM_PUBLISH_LASTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define TWIM_PUBLISH_LASTTX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: TWIM_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 12 : Shortcut between event LASTRX and task STOP */
+#define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */
+#define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */
+#define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 10 : Shortcut between event LASTRX and task STARTTX */
+#define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */
+#define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */
+#define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 9 : Shortcut between event LASTTX and task STOP */
+#define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */
+#define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */
+#define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 8 : Shortcut between event LASTTX and task SUSPEND */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 7 : Shortcut between event LASTTX and task STARTRX */
+#define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */
+#define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */
+#define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: TWIM_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 24 : Enable or disable interrupt for event LASTTX */
+#define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
+#define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
+#define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
+
+/* Bit 23 : Enable or disable interrupt for event LASTRX */
+#define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
+#define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
+#define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for event TXSTARTED */
+#define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for event RXSTARTED */
+#define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 18 : Enable or disable interrupt for event SUSPENDED */
+#define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for event ERROR */
+#define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for event STOPPED */
+#define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Register: TWIM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 24 : Write '1' to enable interrupt for event LASTTX */
+#define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
+#define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
+#define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
+
+/* Bit 23 : Write '1' to enable interrupt for event LASTRX */
+#define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
+#define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
+#define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
+#define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
+#define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */
+#define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to enable interrupt for event ERROR */
+#define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event STOPPED */
+#define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: TWIM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 24 : Write '1' to disable interrupt for event LASTTX */
+#define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
+#define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
+#define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
+
+/* Bit 23 : Write '1' to disable interrupt for event LASTRX */
+#define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
+#define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
+#define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
+#define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
+#define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */
+#define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to disable interrupt for event ERROR */
+#define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event STOPPED */
+#define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: TWIM_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
+#define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
+#define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
+#define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
+#define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
+
+/* Bit 1 : NACK received after sending the address (write '1' to clear) */
+#define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
+#define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
+#define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */
+#define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */
+
+/* Bit 0 : Overrun error */
+#define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */
+#define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */
+
+/* Register: TWIM_ENABLE */
+/* Description: Enable TWIM */
+
+/* Bits 3..0 : Enable or disable TWIM */
+#define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */
+#define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */
+
+/* Register: TWIM_PSEL_SCL */
+/* Description: Pin select for SCL signal */
+
+/* Bit 31 : Connection */
+#define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIM_PSEL_SDA */
+/* Description: Pin select for SDA signal */
+
+/* Bit 31 : Connection */
+#define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIM_FREQUENCY */
+/* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */
+
+/* Bits 31..0 : TWI master clock frequency */
+#define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
+#define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
+#define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */
+
+/* Register: TWIM_RXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIM_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 12..0 : Maximum number of bytes in receive buffer */
+#define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIM_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIM_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 12..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
+#define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIM_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIM_RXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 1..0 : List type */
+#define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define TWIM_RXD_LIST_LIST_Msk (0x3UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: TWIM_TXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIM_TXD_MAXCNT */
+/* Description: Maximum number of bytes in transmit buffer */
+
+/* Bits 12..0 : Maximum number of bytes in transmit buffer */
+#define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIM_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIM_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 12..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
+#define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIM_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIM_TXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 1..0 : List type */
+#define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define TWIM_TXD_LIST_LIST_Msk (0x3UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: TWIM_ADDRESS */
+/* Description: Address used in the TWI transfer */
+
+/* Bits 6..0 : Address used in the TWI transfer */
+#define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
+#define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+
+
+/* Peripheral: TWIS */
+/* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */
+
+/* Register: TWIS_TASKS_STOP */
+/* Description: Stop TWI transaction */
+
+/* Bit 0 : Stop TWI transaction */
+#define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
+#define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
+#define TWIS_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIS_TASKS_SUSPEND */
+/* Description: Suspend TWI transaction */
+
+/* Bit 0 : Suspend TWI transaction */
+#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
+#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
+#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIS_TASKS_RESUME */
+/* Description: Resume TWI transaction */
+
+/* Bit 0 : Resume TWI transaction */
+#define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
+#define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
+#define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIS_TASKS_PREPARERX */
+/* Description: Prepare the TWI slave to respond to a write command */
+
+/* Bit 0 : Prepare the TWI slave to respond to a write command */
+#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */
+#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */
+#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIS_TASKS_PREPARETX */
+/* Description: Prepare the TWI slave to respond to a read command */
+
+/* Bit 0 : Prepare the TWI slave to respond to a read command */
+#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */
+#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */
+#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: TWIS_SUBSCRIBE_STOP */
+/* Description: Subscribe configuration for task STOP */
+
+/* Bit 31 : */
+#define TWIS_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
+#define TWIS_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIS_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
+#define TWIS_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
+#define TWIS_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
+#define TWIS_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define TWIS_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: TWIS_SUBSCRIBE_SUSPEND */
+/* Description: Subscribe configuration for task SUSPEND */
+
+/* Bit 31 : */
+#define TWIS_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */
+#define TWIS_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIS_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */
+#define TWIS_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */
+#define TWIS_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */
+#define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: TWIS_SUBSCRIBE_RESUME */
+/* Description: Subscribe configuration for task RESUME */
+
+/* Bit 31 : */
+#define TWIS_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */
+#define TWIS_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIS_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */
+#define TWIS_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */
+#define TWIS_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task RESUME will subscribe to */
+#define TWIS_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define TWIS_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: TWIS_SUBSCRIBE_PREPARERX */
+/* Description: Subscribe configuration for task PREPARERX */
+
+/* Bit 31 : */
+#define TWIS_SUBSCRIBE_PREPARERX_EN_Pos (31UL) /*!< Position of EN field. */
+#define TWIS_SUBSCRIBE_PREPARERX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARERX_EN_Pos) /*!< Bit mask of EN field. */
+#define TWIS_SUBSCRIBE_PREPARERX_EN_Disabled (0UL) /*!< Disable subscription */
+#define TWIS_SUBSCRIBE_PREPARERX_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task PREPARERX will subscribe to */
+#define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: TWIS_SUBSCRIBE_PREPARETX */
+/* Description: Subscribe configuration for task PREPARETX */
+
+/* Bit 31 : */
+#define TWIS_SUBSCRIBE_PREPARETX_EN_Pos (31UL) /*!< Position of EN field. */
+#define TWIS_SUBSCRIBE_PREPARETX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARETX_EN_Pos) /*!< Bit mask of EN field. */
+#define TWIS_SUBSCRIBE_PREPARETX_EN_Disabled (0UL) /*!< Disable subscription */
+#define TWIS_SUBSCRIBE_PREPARETX_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task PREPARETX will subscribe to */
+#define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: TWIS_EVENTS_STOPPED */
+/* Description: TWI stopped */
+
+/* Bit 0 : TWI stopped */
+#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
+#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
+#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIS_EVENTS_ERROR */
+/* Description: TWI error */
+
+/* Bit 0 : TWI error */
+#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
+#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
+#define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
+#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIS_EVENTS_RXSTARTED */
+/* Description: Receive sequence started */
+
+/* Bit 0 : Receive sequence started */
+#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
+#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
+#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIS_EVENTS_TXSTARTED */
+/* Description: Transmit sequence started */
+
+/* Bit 0 : Transmit sequence started */
+#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
+#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
+#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIS_EVENTS_WRITE */
+/* Description: Write command received */
+
+/* Bit 0 : Write command received */
+#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */
+#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */
+#define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0UL) /*!< Event not generated */
+#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIS_EVENTS_READ */
+/* Description: Read command received */
+
+/* Bit 0 : Read command received */
+#define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */
+#define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */
+#define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0UL) /*!< Event not generated */
+#define TWIS_EVENTS_READ_EVENTS_READ_Generated (1UL) /*!< Event generated */
+
+/* Register: TWIS_PUBLISH_STOPPED */
+/* Description: Publish configuration for event STOPPED */
+
+/* Bit 31 : */
+#define TWIS_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
+#define TWIS_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIS_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
+#define TWIS_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
+#define TWIS_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event STOPPED will publish to */
+#define TWIS_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define TWIS_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: TWIS_PUBLISH_ERROR */
+/* Description: Publish configuration for event ERROR */
+
+/* Bit 31 : */
+#define TWIS_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */
+#define TWIS_PUBLISH_ERROR_EN_Msk (0x1UL << TWIS_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */
+#define TWIS_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */
+#define TWIS_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event ERROR will publish to */
+#define TWIS_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define TWIS_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: TWIS_PUBLISH_RXSTARTED */
+/* Description: Publish configuration for event RXSTARTED */
+
+/* Bit 31 : */
+#define TWIS_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
+#define TWIS_PUBLISH_RXSTARTED_EN_Msk (0x1UL << TWIS_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
+#define TWIS_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
+#define TWIS_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event RXSTARTED will publish to */
+#define TWIS_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define TWIS_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: TWIS_PUBLISH_TXSTARTED */
+/* Description: Publish configuration for event TXSTARTED */
+
+/* Bit 31 : */
+#define TWIS_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
+#define TWIS_PUBLISH_TXSTARTED_EN_Msk (0x1UL << TWIS_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
+#define TWIS_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
+#define TWIS_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event TXSTARTED will publish to */
+#define TWIS_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define TWIS_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: TWIS_PUBLISH_WRITE */
+/* Description: Publish configuration for event WRITE */
+
+/* Bit 31 : */
+#define TWIS_PUBLISH_WRITE_EN_Pos (31UL) /*!< Position of EN field. */
+#define TWIS_PUBLISH_WRITE_EN_Msk (0x1UL << TWIS_PUBLISH_WRITE_EN_Pos) /*!< Bit mask of EN field. */
+#define TWIS_PUBLISH_WRITE_EN_Disabled (0UL) /*!< Disable publishing */
+#define TWIS_PUBLISH_WRITE_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event WRITE will publish to */
+#define TWIS_PUBLISH_WRITE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define TWIS_PUBLISH_WRITE_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_WRITE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: TWIS_PUBLISH_READ */
+/* Description: Publish configuration for event READ */
+
+/* Bit 31 : */
+#define TWIS_PUBLISH_READ_EN_Pos (31UL) /*!< Position of EN field. */
+#define TWIS_PUBLISH_READ_EN_Msk (0x1UL << TWIS_PUBLISH_READ_EN_Pos) /*!< Bit mask of EN field. */
+#define TWIS_PUBLISH_READ_EN_Disabled (0UL) /*!< Disable publishing */
+#define TWIS_PUBLISH_READ_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event READ will publish to */
+#define TWIS_PUBLISH_READ_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define TWIS_PUBLISH_READ_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_READ_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: TWIS_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 14 : Shortcut between event READ and task SUSPEND */
+#define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */
+#define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */
+#define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 13 : Shortcut between event WRITE and task SUSPEND */
+#define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */
+#define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */
+#define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: TWIS_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 26 : Enable or disable interrupt for event READ */
+#define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
+#define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
+#define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
+
+/* Bit 25 : Enable or disable interrupt for event WRITE */
+#define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
+#define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
+#define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for event TXSTARTED */
+#define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for event RXSTARTED */
+#define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for event ERROR */
+#define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for event STOPPED */
+#define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Register: TWIS_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 26 : Write '1' to enable interrupt for event READ */
+#define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
+#define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
+#define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
+
+/* Bit 25 : Write '1' to enable interrupt for event WRITE */
+#define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
+#define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
+#define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
+#define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
+#define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to enable interrupt for event ERROR */
+#define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event STOPPED */
+#define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: TWIS_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 26 : Write '1' to disable interrupt for event READ */
+#define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
+#define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
+#define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
+
+/* Bit 25 : Write '1' to disable interrupt for event WRITE */
+#define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
+#define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
+#define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
+#define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
+#define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to disable interrupt for event ERROR */
+#define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event STOPPED */
+#define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: TWIS_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 3 : TX buffer over-read detected, and prevented */
+#define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */
+#define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
+#define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */
+#define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */
+
+/* Bit 2 : NACK sent after receiving a data byte */
+#define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
+#define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
+#define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
+#define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
+
+/* Bit 0 : RX buffer overflow detected, and prevented */
+#define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */
+#define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
+#define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */
+#define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */
+
+/* Register: TWIS_MATCH */
+/* Description: Status register indicating which address had a match */
+
+/* Bit 0 : Indication of which address in {ADDRESS} that matched the incoming address */
+#define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */
+#define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */
+
+/* Register: TWIS_ENABLE */
+/* Description: Enable TWIS */
+
+/* Bits 3..0 : Enable or disable TWIS */
+#define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */
+#define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */
+
+/* Register: TWIS_PSEL_SCL */
+/* Description: Pin select for SCL signal */
+
+/* Bit 31 : Connection */
+#define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIS_PSEL_SDA */
+/* Description: Pin select for SDA signal */
+
+/* Bit 31 : Connection */
+#define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIS_RXD_PTR */
+/* Description: RXD Data pointer */
+
+/* Bits 31..0 : RXD Data pointer */
+#define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIS_RXD_MAXCNT */
+/* Description: Maximum number of bytes in RXD buffer */
+
+/* Bits 12..0 : Maximum number of bytes in RXD buffer */
+#define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIS_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIS_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last RXD transaction */
+
+/* Bits 12..0 : Number of bytes transferred in the last RXD transaction */
+#define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIS_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIS_RXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 1..0 : List type */
+#define TWIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define TWIS_RXD_LIST_LIST_Msk (0x3UL << TWIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define TWIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define TWIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: TWIS_TXD_PTR */
+/* Description: TXD Data pointer */
+
+/* Bits 31..0 : TXD Data pointer */
+#define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIS_TXD_MAXCNT */
+/* Description: Maximum number of bytes in TXD buffer */
+
+/* Bits 12..0 : Maximum number of bytes in TXD buffer */
+#define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIS_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIS_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last TXD transaction */
+
+/* Bits 12..0 : Number of bytes transferred in the last TXD transaction */
+#define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIS_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIS_TXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 1..0 : List type */
+#define TWIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define TWIS_TXD_LIST_LIST_Msk (0x3UL << TWIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define TWIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define TWIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: TWIS_ADDRESS */
+/* Description: Description collection: TWI slave address n */
+
+/* Bits 6..0 : TWI slave address */
+#define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
+#define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+
+/* Register: TWIS_CONFIG */
+/* Description: Configuration register for the address match mechanism */
+
+/* Bit 1 : Enable or disable address matching on ADDRESS[1] */
+#define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */
+#define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */
+#define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */
+#define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */
+
+/* Bit 0 : Enable or disable address matching on ADDRESS[0] */
+#define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */
+#define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */
+#define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */
+#define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */
+
+/* Register: TWIS_ORC */
+/* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */
+
+/* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */
+#define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
+#define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
+
+
+/* Peripheral: UARTE */
+/* Description: UART with EasyDMA 0 */
+
+/* Register: UARTE_TASKS_STARTRX */
+/* Description: Start UART receiver */
+
+/* Bit 0 : Start UART receiver */
+#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
+#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
+#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UARTE_TASKS_STOPRX */
+/* Description: Stop UART receiver */
+
+/* Bit 0 : Stop UART receiver */
+#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */
+#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */
+#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UARTE_TASKS_STARTTX */
+/* Description: Start UART transmitter */
+
+/* Bit 0 : Start UART transmitter */
+#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
+#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
+#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UARTE_TASKS_STOPTX */
+/* Description: Stop UART transmitter */
+
+/* Bit 0 : Stop UART transmitter */
+#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */
+#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */
+#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UARTE_TASKS_FLUSHRX */
+/* Description: Flush RX FIFO into RX buffer */
+
+/* Bit 0 : Flush RX FIFO into RX buffer */
+#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */
+#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */
+#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (1UL) /*!< Trigger task */
+
+/* Register: UARTE_SUBSCRIBE_STARTRX */
+/* Description: Subscribe configuration for task STARTRX */
+
+/* Bit 31 : */
+#define UARTE_SUBSCRIBE_STARTRX_EN_Pos (31UL) /*!< Position of EN field. */
+#define UARTE_SUBSCRIBE_STARTRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STARTRX_EN_Pos) /*!< Bit mask of EN field. */
+#define UARTE_SUBSCRIBE_STARTRX_EN_Disabled (0UL) /*!< Disable subscription */
+#define UARTE_SUBSCRIBE_STARTRX_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task STARTRX will subscribe to */
+#define UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define UARTE_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: UARTE_SUBSCRIBE_STOPRX */
+/* Description: Subscribe configuration for task STOPRX */
+
+/* Bit 31 : */
+#define UARTE_SUBSCRIBE_STOPRX_EN_Pos (31UL) /*!< Position of EN field. */
+#define UARTE_SUBSCRIBE_STOPRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STOPRX_EN_Pos) /*!< Bit mask of EN field. */
+#define UARTE_SUBSCRIBE_STOPRX_EN_Disabled (0UL) /*!< Disable subscription */
+#define UARTE_SUBSCRIBE_STOPRX_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task STOPRX will subscribe to */
+#define UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define UARTE_SUBSCRIBE_STOPRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: UARTE_SUBSCRIBE_STARTTX */
+/* Description: Subscribe configuration for task STARTTX */
+
+/* Bit 31 : */
+#define UARTE_SUBSCRIBE_STARTTX_EN_Pos (31UL) /*!< Position of EN field. */
+#define UARTE_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STARTTX_EN_Pos) /*!< Bit mask of EN field. */
+#define UARTE_SUBSCRIBE_STARTTX_EN_Disabled (0UL) /*!< Disable subscription */
+#define UARTE_SUBSCRIBE_STARTTX_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task STARTTX will subscribe to */
+#define UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define UARTE_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: UARTE_SUBSCRIBE_STOPTX */
+/* Description: Subscribe configuration for task STOPTX */
+
+/* Bit 31 : */
+#define UARTE_SUBSCRIBE_STOPTX_EN_Pos (31UL) /*!< Position of EN field. */
+#define UARTE_SUBSCRIBE_STOPTX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STOPTX_EN_Pos) /*!< Bit mask of EN field. */
+#define UARTE_SUBSCRIBE_STOPTX_EN_Disabled (0UL) /*!< Disable subscription */
+#define UARTE_SUBSCRIBE_STOPTX_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task STOPTX will subscribe to */
+#define UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define UARTE_SUBSCRIBE_STOPTX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: UARTE_SUBSCRIBE_FLUSHRX */
+/* Description: Subscribe configuration for task FLUSHRX */
+
+/* Bit 31 : */
+#define UARTE_SUBSCRIBE_FLUSHRX_EN_Pos (31UL) /*!< Position of EN field. */
+#define UARTE_SUBSCRIBE_FLUSHRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_FLUSHRX_EN_Pos) /*!< Bit mask of EN field. */
+#define UARTE_SUBSCRIBE_FLUSHRX_EN_Disabled (0UL) /*!< Disable subscription */
+#define UARTE_SUBSCRIBE_FLUSHRX_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task FLUSHRX will subscribe to */
+#define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: UARTE_EVENTS_CTS */
+/* Description: CTS is activated (set low). Clear To Send. */
+
+/* Bit 0 : CTS is activated (set low). Clear To Send. */
+#define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */
+#define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */
+#define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_NCTS */
+/* Description: CTS is deactivated (set high). Not Clear To Send. */
+
+/* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */
+#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */
+#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */
+#define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_RXDRDY */
+/* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */
+
+/* Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */
+#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */
+#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */
+#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_ENDRX */
+/* Description: Receive buffer is filled up */
+
+/* Bit 0 : Receive buffer is filled up */
+#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
+#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
+#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_TXDRDY */
+/* Description: Data sent from TXD */
+
+/* Bit 0 : Data sent from TXD */
+#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */
+#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */
+#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_ENDTX */
+/* Description: Last TX byte transmitted */
+
+/* Bit 0 : Last TX byte transmitted */
+#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
+#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
+#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_ERROR */
+/* Description: Error detected */
+
+/* Bit 0 : Error detected */
+#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
+#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
+#define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_RXTO */
+/* Description: Receiver timeout */
+
+/* Bit 0 : Receiver timeout */
+#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */
+#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */
+#define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_RXSTARTED */
+/* Description: UART receiver has started */
+
+/* Bit 0 : UART receiver has started */
+#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
+#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
+#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_TXSTARTED */
+/* Description: UART transmitter has started */
+
+/* Bit 0 : UART transmitter has started */
+#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
+#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
+#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_EVENTS_TXSTOPPED */
+/* Description: Transmitter stopped */
+
+/* Bit 0 : Transmitter stopped */
+#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */
+#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */
+#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0UL) /*!< Event not generated */
+#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (1UL) /*!< Event generated */
+
+/* Register: UARTE_PUBLISH_CTS */
+/* Description: Publish configuration for event CTS */
+
+/* Bit 31 : */
+#define UARTE_PUBLISH_CTS_EN_Pos (31UL) /*!< Position of EN field. */
+#define UARTE_PUBLISH_CTS_EN_Msk (0x1UL << UARTE_PUBLISH_CTS_EN_Pos) /*!< Bit mask of EN field. */
+#define UARTE_PUBLISH_CTS_EN_Disabled (0UL) /*!< Disable publishing */
+#define UARTE_PUBLISH_CTS_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event CTS will publish to */
+#define UARTE_PUBLISH_CTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define UARTE_PUBLISH_CTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_CTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: UARTE_PUBLISH_NCTS */
+/* Description: Publish configuration for event NCTS */
+
+/* Bit 31 : */
+#define UARTE_PUBLISH_NCTS_EN_Pos (31UL) /*!< Position of EN field. */
+#define UARTE_PUBLISH_NCTS_EN_Msk (0x1UL << UARTE_PUBLISH_NCTS_EN_Pos) /*!< Bit mask of EN field. */
+#define UARTE_PUBLISH_NCTS_EN_Disabled (0UL) /*!< Disable publishing */
+#define UARTE_PUBLISH_NCTS_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event NCTS will publish to */
+#define UARTE_PUBLISH_NCTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define UARTE_PUBLISH_NCTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_NCTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: UARTE_PUBLISH_RXDRDY */
+/* Description: Publish configuration for event RXDRDY */
+
+/* Bit 31 : */
+#define UARTE_PUBLISH_RXDRDY_EN_Pos (31UL) /*!< Position of EN field. */
+#define UARTE_PUBLISH_RXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_RXDRDY_EN_Pos) /*!< Bit mask of EN field. */
+#define UARTE_PUBLISH_RXDRDY_EN_Disabled (0UL) /*!< Disable publishing */
+#define UARTE_PUBLISH_RXDRDY_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event RXDRDY will publish to */
+#define UARTE_PUBLISH_RXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define UARTE_PUBLISH_RXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: UARTE_PUBLISH_ENDRX */
+/* Description: Publish configuration for event ENDRX */
+
+/* Bit 31 : */
+#define UARTE_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */
+#define UARTE_PUBLISH_ENDRX_EN_Msk (0x1UL << UARTE_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */
+#define UARTE_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */
+#define UARTE_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event ENDRX will publish to */
+#define UARTE_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define UARTE_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: UARTE_PUBLISH_TXDRDY */
+/* Description: Publish configuration for event TXDRDY */
+
+/* Bit 31 : */
+#define UARTE_PUBLISH_TXDRDY_EN_Pos (31UL) /*!< Position of EN field. */
+#define UARTE_PUBLISH_TXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_TXDRDY_EN_Pos) /*!< Bit mask of EN field. */
+#define UARTE_PUBLISH_TXDRDY_EN_Disabled (0UL) /*!< Disable publishing */
+#define UARTE_PUBLISH_TXDRDY_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event TXDRDY will publish to */
+#define UARTE_PUBLISH_TXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define UARTE_PUBLISH_TXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: UARTE_PUBLISH_ENDTX */
+/* Description: Publish configuration for event ENDTX */
+
+/* Bit 31 : */
+#define UARTE_PUBLISH_ENDTX_EN_Pos (31UL) /*!< Position of EN field. */
+#define UARTE_PUBLISH_ENDTX_EN_Msk (0x1UL << UARTE_PUBLISH_ENDTX_EN_Pos) /*!< Bit mask of EN field. */
+#define UARTE_PUBLISH_ENDTX_EN_Disabled (0UL) /*!< Disable publishing */
+#define UARTE_PUBLISH_ENDTX_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event ENDTX will publish to */
+#define UARTE_PUBLISH_ENDTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define UARTE_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: UARTE_PUBLISH_ERROR */
+/* Description: Publish configuration for event ERROR */
+
+/* Bit 31 : */
+#define UARTE_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */
+#define UARTE_PUBLISH_ERROR_EN_Msk (0x1UL << UARTE_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */
+#define UARTE_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */
+#define UARTE_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event ERROR will publish to */
+#define UARTE_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define UARTE_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: UARTE_PUBLISH_RXTO */
+/* Description: Publish configuration for event RXTO */
+
+/* Bit 31 : */
+#define UARTE_PUBLISH_RXTO_EN_Pos (31UL) /*!< Position of EN field. */
+#define UARTE_PUBLISH_RXTO_EN_Msk (0x1UL << UARTE_PUBLISH_RXTO_EN_Pos) /*!< Bit mask of EN field. */
+#define UARTE_PUBLISH_RXTO_EN_Disabled (0UL) /*!< Disable publishing */
+#define UARTE_PUBLISH_RXTO_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event RXTO will publish to */
+#define UARTE_PUBLISH_RXTO_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define UARTE_PUBLISH_RXTO_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXTO_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: UARTE_PUBLISH_RXSTARTED */
+/* Description: Publish configuration for event RXSTARTED */
+
+/* Bit 31 : */
+#define UARTE_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
+#define UARTE_PUBLISH_RXSTARTED_EN_Msk (0x1UL << UARTE_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
+#define UARTE_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
+#define UARTE_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event RXSTARTED will publish to */
+#define UARTE_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define UARTE_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: UARTE_PUBLISH_TXSTARTED */
+/* Description: Publish configuration for event TXSTARTED */
+
+/* Bit 31 : */
+#define UARTE_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
+#define UARTE_PUBLISH_TXSTARTED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
+#define UARTE_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
+#define UARTE_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event TXSTARTED will publish to */
+#define UARTE_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define UARTE_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: UARTE_PUBLISH_TXSTOPPED */
+/* Description: Publish configuration for event TXSTOPPED */
+
+/* Bit 31 : */
+#define UARTE_PUBLISH_TXSTOPPED_EN_Pos (31UL) /*!< Position of EN field. */
+#define UARTE_PUBLISH_TXSTOPPED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTOPPED_EN_Pos) /*!< Bit mask of EN field. */
+#define UARTE_PUBLISH_TXSTOPPED_EN_Disabled (0UL) /*!< Disable publishing */
+#define UARTE_PUBLISH_TXSTOPPED_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event TXSTOPPED will publish to */
+#define UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define UARTE_PUBLISH_TXSTOPPED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: UARTE_SHORTS */
+/* Description: Shortcuts between local events and tasks */
+
+/* Bit 6 : Shortcut between event ENDRX and task STOPRX */
+#define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */
+#define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */
+#define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */
+#define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 5 : Shortcut between event ENDRX and task STARTRX */
+#define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */
+#define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */
+#define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
+#define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: UARTE_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 22 : Enable or disable interrupt for event TXSTOPPED */
+#define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
+#define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
+#define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for event TXSTARTED */
+#define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for event RXSTARTED */
+#define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 17 : Enable or disable interrupt for event RXTO */
+#define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for event ERROR */
+#define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 8 : Enable or disable interrupt for event ENDTX */
+#define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for event TXDRDY */
+#define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for event ENDRX */
+#define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for event RXDRDY */
+#define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for event NCTS */
+#define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for event CTS */
+#define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */
+
+/* Register: UARTE_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */
+#define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
+#define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
+#define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
+#define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
+#define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to enable interrupt for event RXTO */
+#define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to enable interrupt for event ERROR */
+#define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to enable interrupt for event ENDTX */
+#define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to enable interrupt for event TXDRDY */
+#define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to enable interrupt for event ENDRX */
+#define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to enable interrupt for event RXDRDY */
+#define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to enable interrupt for event NCTS */
+#define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to enable interrupt for event CTS */
+#define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
+
+/* Register: UARTE_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */
+#define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
+#define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
+#define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
+#define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
+#define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to disable interrupt for event RXTO */
+#define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to disable interrupt for event ERROR */
+#define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to disable interrupt for event ENDTX */
+#define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to disable interrupt for event TXDRDY */
+#define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to disable interrupt for event ENDRX */
+#define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to disable interrupt for event RXDRDY */
+#define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to disable interrupt for event NCTS */
+#define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to disable interrupt for event CTS */
+#define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
+
+/* Register: UARTE_ERRORSRC */
+/* Description: Error source This register is read/write one to clear. */
+
+/* Bit 3 : Break condition */
+#define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
+#define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
+#define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
+
+/* Bit 2 : Framing error occurred */
+#define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
+#define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
+#define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
+
+/* Bit 1 : Parity error */
+#define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
+
+/* Bit 0 : Overrun error */
+#define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
+
+/* Register: UARTE_ENABLE */
+/* Description: Enable UART */
+
+/* Bits 3..0 : Enable or disable UARTE */
+#define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */
+#define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */
+
+/* Register: UARTE_PSEL_RTS */
+/* Description: Pin select for RTS signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_PSEL_TXD */
+/* Description: Pin select for TXD signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_PSEL_CTS */
+/* Description: Pin select for CTS signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_PSEL_RXD */
+/* Description: Pin select for RXD signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_BAUDRATE */
+/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
+
+/* Bits 31..0 : Baud rate */
+#define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
+#define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
+#define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
+#define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
+#define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud */
+
+/* Register: UARTE_RXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: UARTE_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 12..0 : Maximum number of bytes in receive buffer */
+#define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define UARTE_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: UARTE_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 12..0 : Number of bytes transferred in the last transaction */
+#define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define UARTE_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: UARTE_TXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: UARTE_TXD_MAXCNT */
+/* Description: Maximum number of bytes in transmit buffer */
+
+/* Bits 12..0 : Maximum number of bytes in transmit buffer */
+#define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define UARTE_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: UARTE_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 12..0 : Number of bytes transferred in the last transaction */
+#define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define UARTE_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: UARTE_CONFIG */
+/* Description: Configuration of parity and hardware flow control */
+
+/* Bit 4 : Stop bits */
+#define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */
+#define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */
+#define UARTE_CONFIG_STOP_One (0UL) /*!< One stop bit */
+#define UARTE_CONFIG_STOP_Two (1UL) /*!< Two stop bits */
+
+/* Bits 3..1 : Parity */
+#define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
+#define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include even parity bit */
+
+/* Bit 0 : Hardware flow control */
+#define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
+#define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
+#define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
+#define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
+
+
+/* Peripheral: UICR */
+/* Description: User information configuration registers User information configuration registers */
+
+/* Register: UICR_APPROTECT */
+/* Description: Access port protection */
+
+/* Bits 31..0 : Blocks debugger read/write access to all CPU registers and
+ memory mapped addresses */
+#define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
+#define UICR_APPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
+#define UICR_APPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */
+#define UICR_APPROTECT_PALL_HwUnprotected (0x50FA50FAUL) /*!< HwUnprotected */
+
+/* Register: UICR_XOSC32M */
+/* Description: Oscillator control */
+
+/* Bits 5..0 : Pierce current DAC control signals */
+#define UICR_XOSC32M_CTRL_Pos (0UL) /*!< Position of CTRL field. */
+#define UICR_XOSC32M_CTRL_Msk (0x3FUL << UICR_XOSC32M_CTRL_Pos) /*!< Bit mask of CTRL field. */
+
+/* Register: UICR_HFXOSRC */
+/* Description: HFXO clock source selection */
+
+/* Bit 0 : HFXO clock source selection */
+#define UICR_HFXOSRC_HFXOSRC_Pos (0UL) /*!< Position of HFXOSRC field. */
+#define UICR_HFXOSRC_HFXOSRC_Msk (0x1UL << UICR_HFXOSRC_HFXOSRC_Pos) /*!< Bit mask of HFXOSRC field. */
+#define UICR_HFXOSRC_HFXOSRC_TCXO (0UL) /*!< 32 MHz temperature compensated crystal oscillator (TCXO) */
+#define UICR_HFXOSRC_HFXOSRC_XTAL (1UL) /*!< 32 MHz crystal oscillator */
+
+/* Register: UICR_HFXOCNT */
+/* Description: HFXO startup counter */
+
+/* Bits 7..0 : HFXO startup counter. Total debounce time = HFXOCNT*64 us + 0.5 us */
+#define UICR_HFXOCNT_HFXOCNT_Pos (0UL) /*!< Position of HFXOCNT field. */
+#define UICR_HFXOCNT_HFXOCNT_Msk (0xFFUL << UICR_HFXOCNT_HFXOCNT_Pos) /*!< Bit mask of HFXOCNT field. */
+#define UICR_HFXOCNT_HFXOCNT_MinDebounceTime (0UL) /*!< Min debounce time = (0*64 us + 0.5 us) */
+#define UICR_HFXOCNT_HFXOCNT_MaxDebounceTime (255UL) /*!< Max debounce time = (255*64 us + 0.5 us) */
+
+/* Register: UICR_APPNVMCPOFGUARD */
+/* Description: Enable blocking NVM WRITE and aborting NVM ERASE for Application NVM in POFWARN condition . */
+
+/* Bit 0 : Enable blocking NVM WRITE and aborting NVM ERASE in POFWARN condition */
+#define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Pos (0UL) /*!< Position of NVMCPOFGUARDEN field. */
+#define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Msk (0x1UL << UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Pos) /*!< Bit mask of NVMCPOFGUARDEN field. */
+#define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Disabled (0UL) /*!< NVM WRITE and NVM ERASE are not blocked in POFWARN condition */
+#define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Enabled (1UL) /*!< NVM WRITE and NVM ERASE are blocked in POFWARN condition */
+
+/* Register: UICR_PMICCONF */
+/* Description: Polarity of PMIC polarity configuration signals. */
+
+/* Bit 0 : Polarity of PMIC_FPWM signal. */
+#define UICR_PMICCONF_PMICFPWMPOL_Pos (0UL) /*!< Position of PMICFPWMPOL field. */
+#define UICR_PMICCONF_PMICFPWMPOL_Msk (0x1UL << UICR_PMICCONF_PMICFPWMPOL_Pos) /*!< Bit mask of PMICFPWMPOL field. */
+#define UICR_PMICCONF_PMICFPWMPOL_ActiveLow (0UL) /*!< PMIC_FPWM output signal is active-low */
+#define UICR_PMICCONF_PMICFPWMPOL_ActiveHigh (1UL) /*!< PMIC_FPWM output signal is active-high */
+
+/* Register: UICR_SECUREAPPROTECT */
+/* Description: Secure access port protection */
+
+/* Bits 31..0 : Blocks debugger read/write access to all secure CPU registers and secure
+ memory mapped addresses */
+#define UICR_SECUREAPPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
+#define UICR_SECUREAPPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_SECUREAPPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
+#define UICR_SECUREAPPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */
+#define UICR_SECUREAPPROTECT_PALL_HwUnprotected (0x50FA50FAUL) /*!< HwUnprotected */
+
+/* Register: UICR_ERASEPROTECT */
+/* Description: Erase protection */
+
+/* Bits 31..0 : Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality */
+#define UICR_ERASEPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
+#define UICR_ERASEPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_ERASEPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
+#define UICR_ERASEPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */
+#define UICR_ERASEPROTECT_PALL_Unprotected (0xFFFFFFFFUL) /*!< Unprotected */
+
+/* Register: UICR_OTP */
+/* Description: Description collection: One time programmable memory */
+
+/* Bits 31..16 : Upper half word */
+#define UICR_OTP_UPPER_Pos (16UL) /*!< Position of UPPER field. */
+#define UICR_OTP_UPPER_Msk (0xFFFFUL << UICR_OTP_UPPER_Pos) /*!< Bit mask of UPPER field. */
+
+/* Bits 15..0 : Lower half word */
+#define UICR_OTP_LOWER_Pos (0UL) /*!< Position of LOWER field. */
+#define UICR_OTP_LOWER_Msk (0xFFFFUL << UICR_OTP_LOWER_Pos) /*!< Bit mask of LOWER field. */
+
+/* Register: UICR_KEYSLOT_CONFIG_DEST */
+/* Description: Description cluster: Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE[0-3])
+ will be pushed by KMU. Note that this address must match that of a peripherals
+ APB mapped write-only key registers, else the KMU can push this key value into
+ an address range which the CPU can potentially read. */
+
+/* Bits 31..0 : Secure APB destination address */
+#define UICR_KEYSLOT_CONFIG_DEST_DEST_Pos (0UL) /*!< Position of DEST field. */
+#define UICR_KEYSLOT_CONFIG_DEST_DEST_Msk (0xFFFFFFFFUL << UICR_KEYSLOT_CONFIG_DEST_DEST_Pos) /*!< Bit mask of DEST field. */
+
+/* Register: UICR_KEYSLOT_CONFIG_PERM */
+/* Description: Description cluster: Define permissions for the key slot. Bits 0-15 and 16-31 can only be written when equal to 0xFFFF. */
+
+/* Bit 16 : Revocation state for the key slot */
+#define UICR_KEYSLOT_CONFIG_PERM_STATE_Pos (16UL) /*!< Position of STATE field. */
+#define UICR_KEYSLOT_CONFIG_PERM_STATE_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_STATE_Pos) /*!< Bit mask of STATE field. */
+#define UICR_KEYSLOT_CONFIG_PERM_STATE_Revoked (0UL) /*!< Key value registers can no longer be read or pushed */
+#define UICR_KEYSLOT_CONFIG_PERM_STATE_Active (1UL) /*!< Key value registers are readable (if enabled) and can be pushed (if enabled) */
+
+/* Bit 2 : Push permission for key slot */
+#define UICR_KEYSLOT_CONFIG_PERM_PUSH_Pos (2UL) /*!< Position of PUSH field. */
+#define UICR_KEYSLOT_CONFIG_PERM_PUSH_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_PUSH_Pos) /*!< Bit mask of PUSH field. */
+#define UICR_KEYSLOT_CONFIG_PERM_PUSH_Disabled (0UL) /*!< Disable pushing of key value registers over secure APB, but can be read if field READ is Enabled */
+#define UICR_KEYSLOT_CONFIG_PERM_PUSH_Enabled (1UL) /*!< Enable pushing of key value registers over secure APB. Register KEYSLOT.CONFIGn.DEST must contain a valid destination address! */
+
+/* Bit 1 : Read permission for key slot */
+#define UICR_KEYSLOT_CONFIG_PERM_READ_Pos (1UL) /*!< Position of READ field. */
+#define UICR_KEYSLOT_CONFIG_PERM_READ_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_READ_Pos) /*!< Bit mask of READ field. */
+#define UICR_KEYSLOT_CONFIG_PERM_READ_Disabled (0UL) /*!< Disable read from key value registers */
+#define UICR_KEYSLOT_CONFIG_PERM_READ_Enabled (1UL) /*!< Enable read from key value registers */
+
+/* Bit 0 : Write permission for key slot */
+#define UICR_KEYSLOT_CONFIG_PERM_WRITE_Pos (0UL) /*!< Position of WRITE field. */
+#define UICR_KEYSLOT_CONFIG_PERM_WRITE_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */
+#define UICR_KEYSLOT_CONFIG_PERM_WRITE_Disabled (0UL) /*!< Disable write to the key value registers */
+#define UICR_KEYSLOT_CONFIG_PERM_WRITE_Enabled (1UL) /*!< Enable write to the key value registers */
+
+/* Register: UICR_KEYSLOT_KEY_VALUE */
+/* Description: Description collection: Define bits [31+o*32:0+o*32] of value assigned to KMU key slot. */
+
+/* Bits 31..0 : Define bits [31+o*32:0+o*32] of value assigned to KMU key slot */
+#define UICR_KEYSLOT_KEY_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
+#define UICR_KEYSLOT_KEY_VALUE_VALUE_Msk (0xFFFFFFFFUL << UICR_KEYSLOT_KEY_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
+
+
+/* Peripheral: VMC */
+/* Description: Volatile Memory controller 0 */
+
+/* Register: VMC_RAM_POWER */
+/* Description: Description cluster: RAMn power control register */
+
+/* Bit 19 : Keep retention on RAM section S3 of RAM n when RAM section is switched off */
+#define VMC_RAM_POWER_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
+#define VMC_RAM_POWER_S3RETENTION_Msk (0x1UL << VMC_RAM_POWER_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
+#define VMC_RAM_POWER_S3RETENTION_Off (0UL) /*!< Off */
+#define VMC_RAM_POWER_S3RETENTION_On (1UL) /*!< On */
+
+/* Bit 18 : Keep retention on RAM section S2 of RAM n when RAM section is switched off */
+#define VMC_RAM_POWER_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
+#define VMC_RAM_POWER_S2RETENTION_Msk (0x1UL << VMC_RAM_POWER_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
+#define VMC_RAM_POWER_S2RETENTION_Off (0UL) /*!< Off */
+#define VMC_RAM_POWER_S2RETENTION_On (1UL) /*!< On */
+
+/* Bit 17 : Keep retention on RAM section S1 of RAM n when RAM section is switched off */
+#define VMC_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
+#define VMC_RAM_POWER_S1RETENTION_Msk (0x1UL << VMC_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
+#define VMC_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */
+#define VMC_RAM_POWER_S1RETENTION_On (1UL) /*!< On */
+
+/* Bit 16 : Keep retention on RAM section S0 of RAM n when RAM section is switched off */
+#define VMC_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
+#define VMC_RAM_POWER_S0RETENTION_Msk (0x1UL << VMC_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
+#define VMC_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */
+#define VMC_RAM_POWER_S0RETENTION_On (1UL) /*!< On */
+
+/* Bit 3 : Keep RAM section S3 of RAM n on or off in System ON mode */
+#define VMC_RAM_POWER_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
+#define VMC_RAM_POWER_S3POWER_Msk (0x1UL << VMC_RAM_POWER_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
+#define VMC_RAM_POWER_S3POWER_Off (0UL) /*!< Off */
+#define VMC_RAM_POWER_S3POWER_On (1UL) /*!< On */
+
+/* Bit 2 : Keep RAM section S2 of RAM n on or off in System ON mode */
+#define VMC_RAM_POWER_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
+#define VMC_RAM_POWER_S2POWER_Msk (0x1UL << VMC_RAM_POWER_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
+#define VMC_RAM_POWER_S2POWER_Off (0UL) /*!< Off */
+#define VMC_RAM_POWER_S2POWER_On (1UL) /*!< On */
+
+/* Bit 1 : Keep RAM section S1 of RAM n on or off in System ON mode */
+#define VMC_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
+#define VMC_RAM_POWER_S1POWER_Msk (0x1UL << VMC_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
+#define VMC_RAM_POWER_S1POWER_Off (0UL) /*!< Off */
+#define VMC_RAM_POWER_S1POWER_On (1UL) /*!< On */
+
+/* Bit 0 : Keep RAM section S0 of RAM n on or off in System ON mode */
+#define VMC_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
+#define VMC_RAM_POWER_S0POWER_Msk (0x1UL << VMC_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
+#define VMC_RAM_POWER_S0POWER_Off (0UL) /*!< Off */
+#define VMC_RAM_POWER_S0POWER_On (1UL) /*!< On */
+
+/* Register: VMC_RAM_POWERSET */
+/* Description: Description cluster: RAMn power control set register */
+
+/* Bit 19 : Keep retention on RAM section S3 of RAM n when RAM section is switched off */
+#define VMC_RAM_POWERSET_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
+#define VMC_RAM_POWERSET_S3RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
+#define VMC_RAM_POWERSET_S3RETENTION_On (1UL) /*!< On */
+
+/* Bit 18 : Keep retention on RAM section S2 of RAM n when RAM section is switched off */
+#define VMC_RAM_POWERSET_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
+#define VMC_RAM_POWERSET_S2RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
+#define VMC_RAM_POWERSET_S2RETENTION_On (1UL) /*!< On */
+
+/* Bit 17 : Keep retention on RAM section S1 of RAM n when RAM section is switched off */
+#define VMC_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
+#define VMC_RAM_POWERSET_S1RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
+#define VMC_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */
+
+/* Bit 16 : Keep retention on RAM section S0 of RAM n when RAM section is switched off */
+#define VMC_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
+#define VMC_RAM_POWERSET_S0RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
+#define VMC_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */
+
+/* Bit 3 : Keep RAM section S3 of RAM n on or off in System ON mode */
+#define VMC_RAM_POWERSET_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
+#define VMC_RAM_POWERSET_S3POWER_Msk (0x1UL << VMC_RAM_POWERSET_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
+#define VMC_RAM_POWERSET_S3POWER_On (1UL) /*!< On */
+
+/* Bit 2 : Keep RAM section S2 of RAM n on or off in System ON mode */
+#define VMC_RAM_POWERSET_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
+#define VMC_RAM_POWERSET_S2POWER_Msk (0x1UL << VMC_RAM_POWERSET_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
+#define VMC_RAM_POWERSET_S2POWER_On (1UL) /*!< On */
+
+/* Bit 1 : Keep RAM section S1 of RAM n on or off in System ON mode */
+#define VMC_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
+#define VMC_RAM_POWERSET_S1POWER_Msk (0x1UL << VMC_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
+#define VMC_RAM_POWERSET_S1POWER_On (1UL) /*!< On */
+
+/* Bit 0 : Keep RAM section S0 of RAM n on or off in System ON mode */
+#define VMC_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
+#define VMC_RAM_POWERSET_S0POWER_Msk (0x1UL << VMC_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
+#define VMC_RAM_POWERSET_S0POWER_On (1UL) /*!< On */
+
+/* Register: VMC_RAM_POWERCLR */
+/* Description: Description cluster: RAMn power control clear register */
+
+/* Bit 19 : Keep retention on RAM section S3 of RAM n when RAM section is switched off */
+#define VMC_RAM_POWERCLR_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
+#define VMC_RAM_POWERCLR_S3RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
+#define VMC_RAM_POWERCLR_S3RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 18 : Keep retention on RAM section S2 of RAM n when RAM section is switched off */
+#define VMC_RAM_POWERCLR_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
+#define VMC_RAM_POWERCLR_S2RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
+#define VMC_RAM_POWERCLR_S2RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 17 : Keep retention on RAM section S1 of RAM n when RAM section is switched off */
+#define VMC_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
+#define VMC_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
+#define VMC_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 16 : Keep retention on RAM section S0 of RAM n when RAM section is switched off */
+#define VMC_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
+#define VMC_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
+#define VMC_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 3 : Keep RAM section S3 of RAM n on or off in System ON mode */
+#define VMC_RAM_POWERCLR_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
+#define VMC_RAM_POWERCLR_S3POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
+#define VMC_RAM_POWERCLR_S3POWER_Off (1UL) /*!< Off */
+
+/* Bit 2 : Keep RAM section S2 of RAM n on or off in System ON mode */
+#define VMC_RAM_POWERCLR_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
+#define VMC_RAM_POWERCLR_S2POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
+#define VMC_RAM_POWERCLR_S2POWER_Off (1UL) /*!< Off */
+
+/* Bit 1 : Keep RAM section S1 of RAM n on or off in System ON mode */
+#define VMC_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
+#define VMC_RAM_POWERCLR_S1POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
+#define VMC_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */
+
+/* Bit 0 : Keep RAM section S0 of RAM n on or off in System ON mode */
+#define VMC_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
+#define VMC_RAM_POWERCLR_S0POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
+#define VMC_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */
+
+
+/* Peripheral: WDT */
+/* Description: Watchdog Timer 0 */
+
+/* Register: WDT_TASKS_START */
+/* Description: Start the watchdog */
+
+/* Bit 0 : Start the watchdog */
+#define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
+#define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
+#define WDT_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
+
+/* Register: WDT_SUBSCRIBE_START */
+/* Description: Subscribe configuration for task START */
+
+/* Bit 31 : */
+#define WDT_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
+#define WDT_SUBSCRIBE_START_EN_Msk (0x1UL << WDT_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
+#define WDT_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
+#define WDT_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
+
+/* Bits 7..0 : DPPI channel that task START will subscribe to */
+#define WDT_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define WDT_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << WDT_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: WDT_EVENTS_TIMEOUT */
+/* Description: Watchdog timeout */
+
+/* Bit 0 : Watchdog timeout */
+#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */
+#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */
+#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0UL) /*!< Event not generated */
+#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (1UL) /*!< Event generated */
+
+/* Register: WDT_PUBLISH_TIMEOUT */
+/* Description: Publish configuration for event TIMEOUT */
+
+/* Bit 31 : */
+#define WDT_PUBLISH_TIMEOUT_EN_Pos (31UL) /*!< Position of EN field. */
+#define WDT_PUBLISH_TIMEOUT_EN_Msk (0x1UL << WDT_PUBLISH_TIMEOUT_EN_Pos) /*!< Bit mask of EN field. */
+#define WDT_PUBLISH_TIMEOUT_EN_Disabled (0UL) /*!< Disable publishing */
+#define WDT_PUBLISH_TIMEOUT_EN_Enabled (1UL) /*!< Enable publishing */
+
+/* Bits 7..0 : DPPI channel that event TIMEOUT will publish to */
+#define WDT_PUBLISH_TIMEOUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
+#define WDT_PUBLISH_TIMEOUT_CHIDX_Msk (0xFFUL << WDT_PUBLISH_TIMEOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+
+/* Register: WDT_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */
+#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
+#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
+#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
+#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
+#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */
+
+/* Register: WDT_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */
+#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
+#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
+#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
+#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
+#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
+
+/* Register: WDT_RUNSTATUS */
+/* Description: Run status */
+
+/* Bit 0 : Indicates whether or not the watchdog is running */
+#define WDT_RUNSTATUS_RUNSTATUSWDT_Pos (0UL) /*!< Position of RUNSTATUSWDT field. */
+#define WDT_RUNSTATUS_RUNSTATUSWDT_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUSWDT_Pos) /*!< Bit mask of RUNSTATUSWDT field. */
+#define WDT_RUNSTATUS_RUNSTATUSWDT_NotRunning (0UL) /*!< Watchdog not running */
+#define WDT_RUNSTATUS_RUNSTATUSWDT_Running (1UL) /*!< Watchdog is running */
+
+/* Register: WDT_REQSTATUS */
+/* Description: Request status */
+
+/* Bit 7 : Request status for RR[7] register */
+#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
+#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
+#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */
+
+/* Bit 6 : Request status for RR[6] register */
+#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
+#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
+#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */
+
+/* Bit 5 : Request status for RR[5] register */
+#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
+#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
+#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */
+
+/* Bit 4 : Request status for RR[4] register */
+#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
+#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
+#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */
+
+/* Bit 3 : Request status for RR[3] register */
+#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
+#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
+#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */
+
+/* Bit 2 : Request status for RR[2] register */
+#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
+#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
+#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */
+
+/* Bit 1 : Request status for RR[1] register */
+#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
+#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
+#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */
+
+/* Bit 0 : Request status for RR[0] register */
+#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
+#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
+#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */
+
+/* Register: WDT_CRV */
+/* Description: Counter reload value */
+
+/* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */
+#define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */
+#define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */
+
+/* Register: WDT_RREN */
+/* Description: Enable register for reload request registers */
+
+/* Bit 7 : Enable or disable RR[7] register */
+#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
+#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
+#define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */
+#define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */
+
+/* Bit 6 : Enable or disable RR[6] register */
+#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
+#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
+#define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */
+#define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */
+
+/* Bit 5 : Enable or disable RR[5] register */
+#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
+#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
+#define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */
+#define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */
+
+/* Bit 4 : Enable or disable RR[4] register */
+#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
+#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
+#define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */
+#define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */
+
+/* Bit 3 : Enable or disable RR[3] register */
+#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
+#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
+#define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */
+#define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */
+
+/* Bit 2 : Enable or disable RR[2] register */
+#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
+#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
+#define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
+#define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */
+
+/* Bit 1 : Enable or disable RR[1] register */
+#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
+#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
+#define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */
+#define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */
+
+/* Bit 0 : Enable or disable RR[0] register */
+#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
+#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
+#define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */
+#define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */
+
+/* Register: WDT_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */
+#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
+#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
+#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */
+#define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */
+
+/* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */
+#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
+#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
+#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */
+#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */
+
+/* Register: WDT_RR */
+/* Description: Description collection: Reload request n */
+
+/* Bits 31..0 : Reload request register */
+#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
+#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
+#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */
+
+
+/*lint --flb "Leave library region" */
+#endif
diff --git a/mcu/nrf/common/vendor/mdk/nrf9120_peripherals.h b/mcu/nrf/common/vendor/mdk/nrf9120_peripherals.h
new file mode 100644
index 00000000..c343842b
--- /dev/null
+++ b/mcu/nrf/common/vendor/mdk/nrf9120_peripherals.h
@@ -0,0 +1,232 @@
+/*
+
+Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
+
+SPDX-License-Identifier: BSD-3-Clause
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from this
+ software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef _NRF9120_PERIPHERALS_H
+#define _NRF9120_PERIPHERALS_H
+
+/* UICR */
+#define UICR_KEYSLOT_COUNT 128
+
+/* Clock Peripheral */
+#define CLOCK_PRESENT
+#define CLOCK_COUNT 1
+
+/* Power Peripheral */
+#define POWER_PRESENT
+#define POWER_COUNT 1
+
+/* Non-Volatile Memory Controller */
+#define NVMC_PRESENT
+#define NVMC_COUNT 1
+
+#define NVMC_FEATURE_CACHE_PRESENT
+
+/* Memory Protection Unit */
+#define MPU_REGION_NUM 16
+
+/* GPIO */
+#define GPIO_PRESENT
+#define GPIO_COUNT 1
+
+#define P0_PIN_NUM 32
+
+#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
+
+/* Distributed Peripheral to Peripheral Interconnect */
+#define DPPIC_PRESENT
+#define DPPIC_COUNT 1
+
+#define DPPIC_CH_NUM 16
+#define DPPIC_GROUP_NUM 6
+
+/* Event Generator Unit */
+#define EGU_PRESENT
+#define EGU_COUNT 6
+
+#define EGU0_CH_NUM 16
+#define EGU1_CH_NUM 16
+#define EGU2_CH_NUM 16
+#define EGU3_CH_NUM 16
+#define EGU4_CH_NUM 16
+#define EGU5_CH_NUM 16
+
+/* Timer/Counter */
+#define TIMER_PRESENT
+#define TIMER_COUNT 3
+
+#define TIMER0_MAX_SIZE 32
+#define TIMER1_MAX_SIZE 32
+#define TIMER2_MAX_SIZE 32
+
+
+#define TIMER0_CC_NUM 6
+#define TIMER1_CC_NUM 6
+#define TIMER2_CC_NUM 6
+
+/* Real Time Counter */
+#define RTC_PRESENT
+#define RTC_COUNT 2
+
+#define RTC0_CC_NUM 4
+#define RTC1_CC_NUM 4
+
+/* Watchdog Timer */
+#define WDT_PRESENT
+#define WDT_COUNT 1
+
+/* Serial Peripheral Interface Master with DMA */
+#define SPIM_PRESENT
+#define SPIM_COUNT 4
+
+#define SPIM0_MAX_DATARATE 8
+#define SPIM1_MAX_DATARATE 8
+#define SPIM2_MAX_DATARATE 8
+#define SPIM3_MAX_DATARATE 8
+
+#define SPIM0_EASYDMA_MAXCNT_SIZE 13
+#define SPIM1_EASYDMA_MAXCNT_SIZE 13
+#define SPIM2_EASYDMA_MAXCNT_SIZE 13
+#define SPIM3_EASYDMA_MAXCNT_SIZE 13
+
+/* Serial Peripheral Interface Slave with DMA*/
+#define SPIS_PRESENT
+#define SPIS_COUNT 4
+
+#define SPIS0_EASYDMA_MAXCNT_SIZE 13
+#define SPIS1_EASYDMA_MAXCNT_SIZE 13
+#define SPIS2_EASYDMA_MAXCNT_SIZE 13
+#define SPIS3_EASYDMA_MAXCNT_SIZE 13
+
+/* Two Wire Interface Master with DMA */
+#define TWIM_PRESENT
+#define TWIM_COUNT 4
+
+#define TWIM0_EASYDMA_MAXCNT_SIZE 13
+#define TWIM1_EASYDMA_MAXCNT_SIZE 13
+#define TWIM2_EASYDMA_MAXCNT_SIZE 13
+#define TWIM3_EASYDMA_MAXCNT_SIZE 13
+
+/* Two Wire Interface Slave with DMA */
+#define TWIS_PRESENT
+#define TWIS_COUNT 4
+
+#define TWIS0_EASYDMA_MAXCNT_SIZE 13
+#define TWIS1_EASYDMA_MAXCNT_SIZE 13
+#define TWIS2_EASYDMA_MAXCNT_SIZE 13
+#define TWIS3_EASYDMA_MAXCNT_SIZE 13
+
+/* Universal Asynchronous Receiver-Transmitter with DMA */
+#define UARTE_PRESENT
+#define UARTE_COUNT 4
+
+#define UARTE0_EASYDMA_MAXCNT_SIZE 13
+#define UARTE1_EASYDMA_MAXCNT_SIZE 13
+#define UARTE2_EASYDMA_MAXCNT_SIZE 13
+#define UARTE3_EASYDMA_MAXCNT_SIZE 13
+
+/* Successive Approximation Analog to Digital Converter */
+#define SAADC_PRESENT
+#define SAADC_COUNT 1
+
+#define SAADC_CH_NUM 8
+#define SAADC_EASYDMA_MAXCNT_SIZE 15
+
+/* GPIO Tasks and Events */
+#define GPIOTE_PRESENT
+#define GPIOTE_COUNT 2
+
+#define GPIOTE_CH_NUM 8
+
+#define GPIOTE_FEATURE_SET_PRESENT
+#define GPIOTE_FEATURE_CLR_PRESENT
+
+/* Pulse Width Modulator */
+#define PWM_PRESENT
+#define PWM_COUNT 4
+
+#define PWM_CH_NUM 4
+
+#define PWM_EASYDMA_MAXCNT_SIZE 15
+
+/* Pulse Density Modulator */
+#define PDM_PRESENT
+#define PDM_COUNT 1
+
+#define PDM_EASYDMA_MAXCNT_SIZE 15
+
+/* Inter-IC Sound Interface */
+#define I2S_PRESENT
+#define I2S_COUNT 1
+
+#define I2S_EASYDMA_MAXCNT_SIZE 14
+
+/* Inter Processor Communication */
+#define IPC_PRESENT
+#define IPC_COUNT 1
+
+#define IPC_CH_NUM 8
+#define IPC_CONF_NUM 8
+#define IPC_GPMEM_NUM 4
+
+/* FPU */
+#define FPU_PRESENT
+#define FPU_COUNT 1
+
+/* SPU */
+#define SPU_PRESENT
+#define SPU_COUNT 1
+
+#define SPU_RAMREGION_SIZE 0x2000ul
+
+/* CRYPTOCELL */
+#define CRYPTOCELL_PRESENT
+#define CRYPTOCELL_COUNT 1
+
+/* KMU */
+#define KMU_PRESENT
+#define KMU_COUNT 1
+
+#define KMU_KEYSLOT_PRESENT
+
+/* MAGPIO */
+#define MAGPIO_PRESENT
+#define MAGPIO_COUNT 1
+#define MAGPIO_PIN_NUM 3
+
+/* REGULATORS */
+#define REGULATORS_PRESENT
+#define REGULATORS_COUNT 1
+
+
+#endif // _NRF9120_PERIPHERALS_H
diff --git a/mcu/nrf/common/vendor/mdk/nrf9160.h b/mcu/nrf/common/vendor/mdk/nrf9160.h
index 333bc313..0670ad89 100644
--- a/mcu/nrf/common/vendor/mdk/nrf9160.h
+++ b/mcu/nrf/common/vendor/mdk/nrf9160.h
@@ -1,41 +1,41 @@
/*
- * Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
- * contributors may be used to endorse or promote products derived from this
- * software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
+
+SPDX-License-Identifier: BSD-3-Clause
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from this
+ software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
*
* @file nrf9160.h
* @brief CMSIS HeaderFile
* @version 1
- * @date 29. April 2021
- * @note Generated by SVDConv V3.3.35 on Thursday, 29.04.2021 12:43:58
+ * @date 04. April 2023
+ * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:56
* from File 'nrf9160.svd',
- * last modified on Thursday, 29.04.2021 10:43:41
+ * last modified on Tuesday, 04.04.2023 09:57:14
*/
@@ -86,10 +86,10 @@ typedef enum {
/* ========================================== nrf9160 Specific Interrupt Numbers =========================================== */
SPU_IRQn = 3, /*!< 3 SPU */
CLOCK_POWER_IRQn = 5, /*!< 5 CLOCK_POWER */
- UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQn= 8, /*!< 8 UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 */
- UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQn= 9, /*!< 9 UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 */
- UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQn= 10, /*!< 10 UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 */
- UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQn= 11, /*!< 11 UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 */
+ SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn= 8, /*!< 8 SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 */
+ SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQn= 9, /*!< 9 SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 */
+ SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQn= 10, /*!< 10 SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 */
+ SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQn= 11, /*!< 11 SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 */
GPIOTE0_IRQn = 13, /*!< 13 GPIOTE0 */
SAADC_IRQn = 14, /*!< 14 SAADC */
TIMER0_IRQn = 15, /*!< 15 TIMER0 */
@@ -125,6 +125,7 @@ typedef enum {
/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */
#define __CM33_REV 0x0004U /*!< CM33 Core Revision */
+#define __INTERRUPTS_MAX 240 /*!< Top interrupt number */
#define __DSP_PRESENT 1 /*!< DSP present or not */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
@@ -161,6 +162,18 @@ typedef enum {
*/
+/**
+ * @brief FICR_SIPINFO [SIPINFO] (SIP-specific device info)
+ */
+typedef struct {
+ __IM uint32_t PARTNO; /*!< (@ 0x00000000) SIP part number */
+ __IM uint8_t HWREVISION[4]; /*!< (@ 0x00000004) Description collection: SIP hardware revision,
+ encoded in ASCII, ex B0A or B1A */
+ __IM uint8_t VARIANT[4]; /*!< (@ 0x00000008) Description collection: SIP VARIANT, encoded
+ in ASCII, ex SIAA, SIBA or SICA */
+} FICR_SIPINFO_Type; /*!< Size = 12 (0xc) */
+
+
/**
* @brief FICR_INFO [INFO] (Device info)
*/
@@ -210,11 +223,11 @@ typedef struct {
__IOM uint32_t DEST; /*!< (@ 0x00000000) Description cluster: Destination address where
content of the key value registers (KEYSLOT.KEYn.VALUE[0-3
) will be pushed by KMU. Note that this
- address MUST match that of a peripherals
+ address must match that of a peripherals
APB mapped write-only key registers, else
the KMU can push this key value into an
address range which the CPU can potentially
- read! */
+ read. */
__IOM uint32_t PERM; /*!< (@ 0x00000004) Description cluster: Define permissions for the
key slot. Bits 0-15 and 16-31 can only be
written when equal to 0xFFFF. */
@@ -243,11 +256,11 @@ typedef struct {
* @brief TAD_PSEL [PSEL] (Unspecified)
*/
typedef struct {
- __IOM uint32_t TRACECLK; /*!< (@ 0x00000000) Pin number configuration for TRACECLK */
- __IOM uint32_t TRACEDATA0; /*!< (@ 0x00000004) Pin number configuration for TRACEDATA[0] */
- __IOM uint32_t TRACEDATA1; /*!< (@ 0x00000008) Pin number configuration for TRACEDATA[1] */
- __IOM uint32_t TRACEDATA2; /*!< (@ 0x0000000C) Pin number configuration for TRACEDATA[2] */
- __IOM uint32_t TRACEDATA3; /*!< (@ 0x00000010) Pin number configuration for TRACEDATA[3] */
+ __IOM uint32_t TRACECLK; /*!< (@ 0x00000000) Pin configuration for TRACECLK */
+ __IOM uint32_t TRACEDATA0; /*!< (@ 0x00000004) Pin configuration for TRACEDATA[0] */
+ __IOM uint32_t TRACEDATA1; /*!< (@ 0x00000008) Pin configuration for TRACEDATA[1] */
+ __IOM uint32_t TRACEDATA2; /*!< (@ 0x0000000C) Pin configuration for TRACEDATA[2] */
+ __IOM uint32_t TRACEDATA3; /*!< (@ 0x00000010) Pin configuration for TRACEDATA[3] */
} TAD_PSEL_Type; /*!< Size = 20 (0x14) */
@@ -335,17 +348,28 @@ typedef struct {
} SPU_PERIPHID_Type; /*!< Size = 4 (0x4) */
+/**
+ * @brief POWER_LTEMODEM [LTEMODEM] (LTE Modem)
+ */
+typedef struct {
+ __IOM uint32_t STARTN; /*!< (@ 0x00000000) Start LTE modem */
+ __IOM uint32_t FORCEOFF; /*!< (@ 0x00000004) Force off LTE modem */
+} POWER_LTEMODEM_Type; /*!< Size = 8 (0x8) */
+
+
/**
* @brief CTRLAPPERI_MAILBOX [MAILBOX] (Unspecified)
*/
typedef struct {
- __IM uint32_t RXDATA; /*!< (@ 0x00000000) Data sent from the debugger to the CPU */
- __IM uint32_t RXSTATUS; /*!< (@ 0x00000004) Status to indicate if data sent from the debugger
- to the CPU has been read */
+ __IM uint32_t RXDATA; /*!< (@ 0x00000000) Data sent from the debugger to the CPU. */
+ __IM uint32_t RXSTATUS; /*!< (@ 0x00000004) This register shows a status that indicates if
+ data sent from the debugger to the CPU has
+ been read. */
__IM uint32_t RESERVED[30];
- __IOM uint32_t TXDATA; /*!< (@ 0x00000080) Data sent from the CPU to the debugger */
- __IM uint32_t TXSTATUS; /*!< (@ 0x00000084) Status to indicate if data sent from the CPU
- to the debugger has been read */
+ __IOM uint32_t TXDATA; /*!< (@ 0x00000080) Data sent from the CPU to the debugger. */
+ __IM uint32_t TXSTATUS; /*!< (@ 0x00000084) This register shows a status that indicates if
+ the data sent from the CPU to the debugger
+ has been read. */
} CTRLAPPERI_MAILBOX_Type; /*!< Size = 136 (0x88) */
@@ -353,9 +377,10 @@ typedef struct {
* @brief CTRLAPPERI_ERASEPROTECT [ERASEPROTECT] (Unspecified)
*/
typedef struct {
- __IOM uint32_t LOCK; /*!< (@ 0x00000000) Lock register ERASEPROTECT.DISABLE from being
- written until next reset */
- __IOM uint32_t DISABLE; /*!< (@ 0x00000004) Disable ERASEPROTECT and perform ERASEALL */
+ __IOM uint32_t LOCK; /*!< (@ 0x00000000) This register locks the ERASEPROTECT.DISABLE
+ register from being written until next reset. */
+ __IOM uint32_t DISABLE; /*!< (@ 0x00000004) This register disables the ERASEPROTECT register
+ and performs an ERASEALL operation. */
} CTRLAPPERI_ERASEPROTECT_Type; /*!< Size = 8 (0x8) */
@@ -719,11 +744,13 @@ typedef struct {
*/
typedef struct { /*!< (@ 0x00FF0000) FICR_S Structure */
- __IM uint32_t RESERVED[128];
+ __IM uint32_t RESERVED[80];
+ __IOM FICR_SIPINFO_Type SIPINFO; /*!< (@ 0x00000140) SIP-specific device info */
+ __IM uint32_t RESERVED1[45];
__IOM FICR_INFO_Type INFO; /*!< (@ 0x00000200) Device info */
- __IM uint32_t RESERVED1[53];
+ __IM uint32_t RESERVED2[53];
__IOM FICR_TRIMCNF_Type TRIMCNF[256]; /*!< (@ 0x00000300) Unspecified */
- __IM uint32_t RESERVED2[64];
+ __IM uint32_t RESERVED3[64];
__IOM FICR_TRNG90B_Type TRNG90B; /*!< (@ 0x00000C00) NIST800-90B RNG calibration data */
} NRF_FICR_Type; /*!< Size = 3104 (0xc20) */
@@ -745,7 +772,10 @@ typedef struct { /*!< (@ 0x00FF8000) UICR_S Struc
__IM uint32_t RESERVED1;
__IOM uint32_t HFXOSRC; /*!< (@ 0x0000001C) HFXO clock source selection */
__IOM uint32_t HFXOCNT; /*!< (@ 0x00000020) HFXO startup counter */
- __IM uint32_t RESERVED2[2];
+ __IOM uint32_t APPNVMCPOFGUARD; /*!< (@ 0x00000024) Enable blocking NVM WRITE and aborting NVM ERASE
+ for Application NVM in POFWARN condition
+ . */
+ __IM uint32_t RESERVED2;
__IOM uint32_t SECUREAPPROTECT; /*!< (@ 0x0000002C) Secure access port protection */
__IOM uint32_t ERASEPROTECT; /*!< (@ 0x00000030) Erase protection */
__IM uint32_t RESERVED3[53];
@@ -766,12 +796,13 @@ typedef struct { /*!< (@ 0x00FF8000) UICR_S Struc
*/
typedef struct { /*!< (@ 0xE0080000) TAD_S Structure */
- __OM uint32_t CLOCKSTART; /*!< (@ 0x00000000) Start all trace and debug clocks. */
- __OM uint32_t CLOCKSTOP; /*!< (@ 0x00000004) Stop all trace and debug clocks. */
+ __OM uint32_t TASKS_CLOCKSTART; /*!< (@ 0x00000000) Start all trace and debug clocks. */
+ __OM uint32_t TASKS_CLOCKSTOP; /*!< (@ 0x00000004) Stop all trace and debug clocks. */
__IM uint32_t RESERVED[318];
__IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable debug domain and aquire selected GPIOs */
__IOM TAD_PSEL_Type PSEL; /*!< (@ 0x00000504) Unspecified */
- __IOM uint32_t TRACEPORTSPEED; /*!< (@ 0x00000518) Clocking options for the Trace Port debug interface */
+ __IOM uint32_t TRACEPORTSPEED; /*!< (@ 0x00000518) Clocking options for the Trace Port debug interface
+ Reset behavior is the same as debug components */
} NRF_TAD_Type; /*!< Size = 1308 (0x51c) */
@@ -835,7 +866,9 @@ typedef struct { /*!< (@ 0x50003000) SPU_S Struct
typedef struct { /*!< (@ 0x40004000) REGULATORS_NS Structure */
__IM uint32_t RESERVED[320];
__OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */
- __IM uint32_t RESERVED1[29];
+ __IM uint32_t RESERVED1[4];
+ __IOM uint32_t EXTPOFCON; /*!< (@ 0x00000514) External power failure warning configuration */
+ __IM uint32_t RESERVED2[24];
__IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC mode of the main voltage regulator. */
} NRF_REGULATORS_Type; /*!< Size = 1404 (0x57c) */
@@ -931,7 +964,9 @@ typedef struct { /*!< (@ 0x40005000) POWER_NS Str
__IM uint32_t RESERVED9[54];
__IOM uint32_t GPREGRET[2]; /*!< (@ 0x0000051C) Description collection: General purpose retention
register */
-} NRF_POWER_Type; /*!< Size = 1316 (0x524) */
+ __IM uint32_t RESERVED10[59];
+ __IOM POWER_LTEMODEM_Type LTEMODEM; /*!< (@ 0x00000610) LTE Modem */
+} NRF_POWER_Type; /*!< Size = 1560 (0x618) */
@@ -1289,8 +1324,8 @@ typedef struct { /*!< (@ 0x40008000) UARTE0_NS St
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
__IM uint32_t RESERVED17[93];
- __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source Note : this register is read / write
- one to clear. */
+ __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source This register is read/write one
+ to clear. */
__IM uint32_t RESERVED18[31];
__IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */
__IM uint32_t RESERVED19;
@@ -1351,7 +1386,7 @@ typedef struct { /*!< (@ 0x5000D000) GPIOTE0_S St
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
__IM uint32_t RESERVED7[129];
__IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n],
- SET[n] and CLR[n] tasks and IN[n] event */
+ SET[n], and CLR[n] tasks and IN[n] event */
} NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */
@@ -1527,7 +1562,7 @@ typedef struct { /*!< (@ 0x40014000) RTC0_NS Stru
/**
- * @brief Distributed Programmable Peripheral Interconnect Controller 0 (DPPIC_NS)
+ * @brief Distributed programmable peripheral interconnect controller 0 (DPPIC_NS)
*/
typedef struct { /*!< (@ 0x40017000) DPPIC_NS Structure */
@@ -1540,8 +1575,9 @@ typedef struct { /*!< (@ 0x40017000) DPPIC_NS Str
__IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */
__IM uint32_t RESERVED2[189];
__IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n Note:
- Writes to this register is ignored if either
- SUBSCRIBE_CHG[n].EN/DIS are enabled. */
+ Writes to this register are ignored if either
+ SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS
+ is enabled */
} NRF_DPPIC_Type; /*!< Size = 2072 (0x818) */
@@ -1785,18 +1821,18 @@ typedef struct { /*!< (@ 0x40028000) I2S_NS Struc
/**
- * @brief Inter Processor Communication 0 (IPC_NS)
+ * @brief Interprocessor communication 0 (IPC_NS)
*/
typedef struct { /*!< (@ 0x4002A000) IPC_NS Structure */
- __OM uint32_t TASKS_SEND[8]; /*!< (@ 0x00000000) Description collection: Trigger events on channel
- enabled in SEND_CNF[n]. */
+ __OM uint32_t TASKS_SEND[8]; /*!< (@ 0x00000000) Description collection: Trigger events on IPC
+ channel enabled in SEND_CNF[n] */
__IM uint32_t RESERVED[24];
__IOM uint32_t SUBSCRIBE_SEND[8]; /*!< (@ 0x00000080) Description collection: Subscribe configuration
for task SEND[n] */
__IM uint32_t RESERVED1[24];
__IOM uint32_t EVENTS_RECEIVE[8]; /*!< (@ 0x00000100) Description collection: Event received on one
- or more of the enabled channels in RECEIVE_CNF[n]. */
+ or more of the enabled IPC channels in RECEIVE_CNF[n] */
__IM uint32_t RESERVED2[24];
__IOM uint32_t PUBLISH_RECEIVE[8]; /*!< (@ 0x00000180) Description collection: Publish configuration
for event RECEIVE[n] */
@@ -1807,12 +1843,12 @@ typedef struct { /*!< (@ 0x4002A000) IPC_NS Struc
__IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */
__IM uint32_t RESERVED4[128];
__IOM uint32_t SEND_CNF[8]; /*!< (@ 0x00000510) Description collection: Send event configuration
- for TASKS_SEND[n]. */
+ for TASKS_SEND[n] */
__IM uint32_t RESERVED5[24];
__IOM uint32_t RECEIVE_CNF[8]; /*!< (@ 0x00000590) Description collection: Receive event configuration
- for EVENTS_RECEIVE[n]. */
+ for EVENTS_RECEIVE[n] */
__IM uint32_t RESERVED6[24];
- __IOM uint32_t GPMEM[4]; /*!< (@ 0x00000610) Description collection: General purpose memory. */
+ __IOM uint32_t GPMEM[4]; /*!< (@ 0x00000610) Description collection: General purpose memory */
} NRF_IPC_Type; /*!< Size = 1568 (0x620) */
diff --git a/mcu/nrf/common/vendor/mdk/nrf9160_bitfields.h b/mcu/nrf/common/vendor/mdk/nrf9160_bitfields.h
index 83e7cc23..22abc215 100644
--- a/mcu/nrf/common/vendor/mdk/nrf9160_bitfields.h
+++ b/mcu/nrf/common/vendor/mdk/nrf9160_bitfields.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
+Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
@@ -147,9 +147,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Disabled (0UL) /*!< Disable subscription */
#define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task HFCLKSTART will subscribe to */
+/* Bits 7..0 : DPPI channel that task HFCLKSTART will subscribe to */
#define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Msk (0xFUL << CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: CLOCK_SUBSCRIBE_HFCLKSTOP */
/* Description: Subscribe configuration for task HFCLKSTOP */
@@ -160,9 +160,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Disabled (0UL) /*!< Disable subscription */
#define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task HFCLKSTOP will subscribe to */
+/* Bits 7..0 : DPPI channel that task HFCLKSTOP will subscribe to */
#define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Msk (0xFUL << CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: CLOCK_SUBSCRIBE_LFCLKSTART */
/* Description: Subscribe configuration for task LFCLKSTART */
@@ -173,9 +173,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Disabled (0UL) /*!< Disable subscription */
#define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task LFCLKSTART will subscribe to */
+/* Bits 7..0 : DPPI channel that task LFCLKSTART will subscribe to */
#define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Msk (0xFUL << CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: CLOCK_SUBSCRIBE_LFCLKSTOP */
/* Description: Subscribe configuration for task LFCLKSTOP */
@@ -186,9 +186,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Disabled (0UL) /*!< Disable subscription */
#define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task LFCLKSTOP will subscribe to */
+/* Bits 7..0 : DPPI channel that task LFCLKSTOP will subscribe to */
#define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Msk (0xFUL << CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: CLOCK_EVENTS_HFCLKSTARTED */
/* Description: HFCLK oscillator started */
@@ -217,9 +217,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define CLOCK_PUBLISH_HFCLKSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
#define CLOCK_PUBLISH_HFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event HFCLKSTARTED will publish to. */
+/* Bits 7..0 : DPPI channel that event HFCLKSTARTED will publish to */
#define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Msk (0xFUL << CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: CLOCK_PUBLISH_LFCLKSTARTED */
/* Description: Publish configuration for event LFCLKSTARTED */
@@ -230,9 +230,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define CLOCK_PUBLISH_LFCLKSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
#define CLOCK_PUBLISH_LFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event LFCLKSTARTED will publish to. */
+/* Bits 7..0 : DPPI channel that event LFCLKSTARTED will publish to */
#define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Msk (0xFUL << CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: CLOCK_INTEN */
/* Description: Enable or disable interrupt */
@@ -319,6 +319,7 @@ POSSIBILITY OF SUCH DAMAGE.
/* Bit 0 : Active clock source */
#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_HFCLKSTAT_SRC_HFINT (0UL) /*!< HFINT - 64 MHz on-chip oscillator */
#define CLOCK_HFCLKSTAT_SRC_HFXO (1UL) /*!< HFXO - 64 MHz clock derived from external 32 MHz crystal oscillator */
/* Register: CLOCK_LFCLKRUN */
@@ -384,14 +385,14 @@ POSSIBILITY OF SUCH DAMAGE.
/* Description: Control access port */
/* Register: CTRLAPPERI_MAILBOX_RXDATA */
-/* Description: Data sent from the debugger to the CPU */
+/* Description: Data sent from the debugger to the CPU. */
/* Bits 31..0 : Data received from debugger */
#define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos (0UL) /*!< Position of RXDATA field. */
#define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos) /*!< Bit mask of RXDATA field. */
/* Register: CTRLAPPERI_MAILBOX_RXSTATUS */
-/* Description: Status to indicate if data sent from the debugger to the CPU has been read */
+/* Description: This register shows a status that indicates if data sent from the debugger to the CPU has been read. */
/* Bit 0 : Status of data in register RXDATA */
#define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos (0UL) /*!< Position of RXSTATUS field. */
@@ -400,14 +401,14 @@ POSSIBILITY OF SUCH DAMAGE.
#define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_DataPending (1UL) /*!< Data pending in register RXDATA */
/* Register: CTRLAPPERI_MAILBOX_TXDATA */
-/* Description: Data sent from the CPU to the debugger */
+/* Description: Data sent from the CPU to the debugger. */
/* Bits 31..0 : Data sent to debugger */
#define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos (0UL) /*!< Position of TXDATA field. */
#define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos) /*!< Bit mask of TXDATA field. */
/* Register: CTRLAPPERI_MAILBOX_TXSTATUS */
-/* Description: Status to indicate if data sent from the CPU to the debugger has been read */
+/* Description: This register shows a status that indicates if the data sent from the CPU to the debugger has been read. */
/* Bit 0 : Status of data in register TXDATA */
#define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos (0UL) /*!< Position of TXSTATUS field. */
@@ -416,24 +417,24 @@ POSSIBILITY OF SUCH DAMAGE.
#define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_DataPending (1UL) /*!< Data pending in register TXDATA */
/* Register: CTRLAPPERI_ERASEPROTECT_LOCK */
-/* Description: Lock register ERASEPROTECT.DISABLE from being written until next reset */
+/* Description: This register locks the ERASEPROTECT.DISABLE register from being written until next reset. */
-/* Bit 0 : Lock register ERASEPROTECT.DISABLE from being written until next reset */
+/* Bit 0 : Lock ERASEPROTECT.DISABLE register from being written until next reset */
#define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */
#define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Msk (0x1UL << CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */
#define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Unlocked (0UL) /*!< Register ERASEPROTECT.DISABLE is writeable */
#define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Locked (1UL) /*!< Register ERASEPROTECT.DISABLE is read-only */
/* Register: CTRLAPPERI_ERASEPROTECT_DISABLE */
-/* Description: Disable ERASEPROTECT and perform ERASEALL */
+/* Description: This register disables the ERASEPROTECT register and performs an ERASEALL operation. */
-/* Bits 31..0 : The ERASEALL sequence will be initiated if value of KEY fields are non-zero and KEY fields match on both CPU and debugger side */
+/* Bits 31..0 : The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. */
#define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos (0UL) /*!< Position of KEY field. */
#define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos) /*!< Bit mask of KEY field. */
/* Peripheral: DPPIC */
-/* Description: Distributed Programmable Peripheral Interconnect Controller 0 */
+/* Description: Distributed programmable peripheral interconnect controller 0 */
/* Register: DPPIC_TASKS_CHG_EN */
/* Description: Description cluster: Enable channel group n */
@@ -460,9 +461,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define DPPIC_SUBSCRIBE_CHG_EN_EN_Disabled (0UL) /*!< Disable subscription */
#define DPPIC_SUBSCRIBE_CHG_EN_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task CHG[n].EN will subscribe to */
+/* Bits 7..0 : DPPI channel that task CHG[n].EN will subscribe to */
#define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Msk (0xFUL << DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: DPPIC_SUBSCRIBE_CHG_DIS */
/* Description: Description cluster: Subscribe configuration for task CHG[n].DIS */
@@ -473,9 +474,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define DPPIC_SUBSCRIBE_CHG_DIS_EN_Disabled (0UL) /*!< Disable subscription */
#define DPPIC_SUBSCRIBE_CHG_DIS_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task CHG[n].DIS will subscribe to */
+/* Bits 7..0 : DPPI channel that task CHG[n].DIS will subscribe to */
#define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Msk (0xFUL << DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: DPPIC_CHEN */
/* Description: Channel enable register */
@@ -579,235 +580,235 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: DPPIC_CHENSET */
/* Description: Channel enable set register */
-/* Bit 15 : Channel 15 enable set register. Writing '0' has no effect */
+/* Bit 15 : Channel 15 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
#define DPPIC_CHENSET_CH15_Msk (0x1UL << DPPIC_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
-#define DPPIC_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
+#define DPPIC_CHENSET_CH15_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH15_Enabled (1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
-/* Bit 14 : Channel 14 enable set register. Writing '0' has no effect */
+/* Bit 14 : Channel 14 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
#define DPPIC_CHENSET_CH14_Msk (0x1UL << DPPIC_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
-#define DPPIC_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
+#define DPPIC_CHENSET_CH14_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH14_Enabled (1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
-/* Bit 13 : Channel 13 enable set register. Writing '0' has no effect */
+/* Bit 13 : Channel 13 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
#define DPPIC_CHENSET_CH13_Msk (0x1UL << DPPIC_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
-#define DPPIC_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
+#define DPPIC_CHENSET_CH13_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH13_Enabled (1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
-/* Bit 12 : Channel 12 enable set register. Writing '0' has no effect */
+/* Bit 12 : Channel 12 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
#define DPPIC_CHENSET_CH12_Msk (0x1UL << DPPIC_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
-#define DPPIC_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
+#define DPPIC_CHENSET_CH12_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH12_Enabled (1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
-/* Bit 11 : Channel 11 enable set register. Writing '0' has no effect */
+/* Bit 11 : Channel 11 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
#define DPPIC_CHENSET_CH11_Msk (0x1UL << DPPIC_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
-#define DPPIC_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
+#define DPPIC_CHENSET_CH11_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH11_Enabled (1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
-/* Bit 10 : Channel 10 enable set register. Writing '0' has no effect */
+/* Bit 10 : Channel 10 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
#define DPPIC_CHENSET_CH10_Msk (0x1UL << DPPIC_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
-#define DPPIC_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
+#define DPPIC_CHENSET_CH10_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH10_Enabled (1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
-/* Bit 9 : Channel 9 enable set register. Writing '0' has no effect */
+/* Bit 9 : Channel 9 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
#define DPPIC_CHENSET_CH9_Msk (0x1UL << DPPIC_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
-#define DPPIC_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
+#define DPPIC_CHENSET_CH9_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH9_Enabled (1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
-/* Bit 8 : Channel 8 enable set register. Writing '0' has no effect */
+/* Bit 8 : Channel 8 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
#define DPPIC_CHENSET_CH8_Msk (0x1UL << DPPIC_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
-#define DPPIC_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
+#define DPPIC_CHENSET_CH8_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH8_Enabled (1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
-/* Bit 7 : Channel 7 enable set register. Writing '0' has no effect */
+/* Bit 7 : Channel 7 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
#define DPPIC_CHENSET_CH7_Msk (0x1UL << DPPIC_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
-#define DPPIC_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
+#define DPPIC_CHENSET_CH7_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH7_Enabled (1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
-/* Bit 6 : Channel 6 enable set register. Writing '0' has no effect */
+/* Bit 6 : Channel 6 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
#define DPPIC_CHENSET_CH6_Msk (0x1UL << DPPIC_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
-#define DPPIC_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
+#define DPPIC_CHENSET_CH6_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH6_Enabled (1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
-/* Bit 5 : Channel 5 enable set register. Writing '0' has no effect */
+/* Bit 5 : Channel 5 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
#define DPPIC_CHENSET_CH5_Msk (0x1UL << DPPIC_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
-#define DPPIC_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
+#define DPPIC_CHENSET_CH5_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH5_Enabled (1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
-/* Bit 4 : Channel 4 enable set register. Writing '0' has no effect */
+/* Bit 4 : Channel 4 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
#define DPPIC_CHENSET_CH4_Msk (0x1UL << DPPIC_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
-#define DPPIC_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
+#define DPPIC_CHENSET_CH4_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH4_Enabled (1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
-/* Bit 3 : Channel 3 enable set register. Writing '0' has no effect */
+/* Bit 3 : Channel 3 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
#define DPPIC_CHENSET_CH3_Msk (0x1UL << DPPIC_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
-#define DPPIC_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
+#define DPPIC_CHENSET_CH3_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH3_Enabled (1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
-/* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */
+/* Bit 2 : Channel 2 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
#define DPPIC_CHENSET_CH2_Msk (0x1UL << DPPIC_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
-#define DPPIC_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
+#define DPPIC_CHENSET_CH2_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH2_Enabled (1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
-/* Bit 1 : Channel 1 enable set register. Writing '0' has no effect */
+/* Bit 1 : Channel 1 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
#define DPPIC_CHENSET_CH1_Msk (0x1UL << DPPIC_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
-#define DPPIC_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
+#define DPPIC_CHENSET_CH1_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH1_Enabled (1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
-/* Bit 0 : Channel 0 enable set register. Writing '0' has no effect */
+/* Bit 0 : Channel 0 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
#define DPPIC_CHENSET_CH0_Msk (0x1UL << DPPIC_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
-#define DPPIC_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
+#define DPPIC_CHENSET_CH0_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENSET_CH0_Enabled (1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
/* Register: DPPIC_CHENCLR */
/* Description: Channel enable clear register */
-/* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect */
+/* Bit 15 : Channel 15 enable clear register. Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
#define DPPIC_CHENCLR_CH15_Msk (0x1UL << DPPIC_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
-#define DPPIC_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
-#define DPPIC_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
+#define DPPIC_CHENCLR_CH15_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH15_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH15_Clear (1UL) /*!< Write: Disable channel */
-/* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect */
+/* Bit 14 : Channel 14 enable clear register. Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
#define DPPIC_CHENCLR_CH14_Msk (0x1UL << DPPIC_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
-#define DPPIC_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
-#define DPPIC_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
+#define DPPIC_CHENCLR_CH14_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH14_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH14_Clear (1UL) /*!< Write: Disable channel */
-/* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect */
+/* Bit 13 : Channel 13 enable clear register. Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
#define DPPIC_CHENCLR_CH13_Msk (0x1UL << DPPIC_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
-#define DPPIC_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
-#define DPPIC_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
+#define DPPIC_CHENCLR_CH13_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH13_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH13_Clear (1UL) /*!< Write: Disable channel */
-/* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect */
+/* Bit 12 : Channel 12 enable clear register. Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
#define DPPIC_CHENCLR_CH12_Msk (0x1UL << DPPIC_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
-#define DPPIC_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
-#define DPPIC_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
+#define DPPIC_CHENCLR_CH12_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH12_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH12_Clear (1UL) /*!< Write: Disable channel */
-/* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect */
+/* Bit 11 : Channel 11 enable clear register. Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
#define DPPIC_CHENCLR_CH11_Msk (0x1UL << DPPIC_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
-#define DPPIC_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
-#define DPPIC_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
+#define DPPIC_CHENCLR_CH11_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH11_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH11_Clear (1UL) /*!< Write: Disable channel */
-/* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect */
+/* Bit 10 : Channel 10 enable clear register. Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
#define DPPIC_CHENCLR_CH10_Msk (0x1UL << DPPIC_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
-#define DPPIC_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
-#define DPPIC_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
+#define DPPIC_CHENCLR_CH10_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH10_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH10_Clear (1UL) /*!< Write: Disable channel */
-/* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect */
+/* Bit 9 : Channel 9 enable clear register. Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
#define DPPIC_CHENCLR_CH9_Msk (0x1UL << DPPIC_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
-#define DPPIC_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
-#define DPPIC_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
+#define DPPIC_CHENCLR_CH9_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH9_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH9_Clear (1UL) /*!< Write: Disable channel */
-/* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect */
+/* Bit 8 : Channel 8 enable clear register. Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
#define DPPIC_CHENCLR_CH8_Msk (0x1UL << DPPIC_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
-#define DPPIC_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
-#define DPPIC_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
+#define DPPIC_CHENCLR_CH8_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH8_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH8_Clear (1UL) /*!< Write: Disable channel */
-/* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect */
+/* Bit 7 : Channel 7 enable clear register. Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
#define DPPIC_CHENCLR_CH7_Msk (0x1UL << DPPIC_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
-#define DPPIC_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
-#define DPPIC_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
+#define DPPIC_CHENCLR_CH7_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH7_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH7_Clear (1UL) /*!< Write: Disable channel */
-/* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect */
+/* Bit 6 : Channel 6 enable clear register. Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
#define DPPIC_CHENCLR_CH6_Msk (0x1UL << DPPIC_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
-#define DPPIC_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
-#define DPPIC_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */
+#define DPPIC_CHENCLR_CH6_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH6_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH6_Clear (1UL) /*!< Write: Disable channel */
-/* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect */
+/* Bit 5 : Channel 5 enable clear register. Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
#define DPPIC_CHENCLR_CH5_Msk (0x1UL << DPPIC_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
-#define DPPIC_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
-#define DPPIC_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */
+#define DPPIC_CHENCLR_CH5_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH5_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH5_Clear (1UL) /*!< Write: Disable channel */
-/* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect */
+/* Bit 4 : Channel 4 enable clear register. Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
#define DPPIC_CHENCLR_CH4_Msk (0x1UL << DPPIC_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
-#define DPPIC_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
-#define DPPIC_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */
+#define DPPIC_CHENCLR_CH4_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH4_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH4_Clear (1UL) /*!< Write: Disable channel */
-/* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect */
+/* Bit 3 : Channel 3 enable clear register. Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
#define DPPIC_CHENCLR_CH3_Msk (0x1UL << DPPIC_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
-#define DPPIC_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
-#define DPPIC_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */
+#define DPPIC_CHENCLR_CH3_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH3_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH3_Clear (1UL) /*!< Write: Disable channel */
-/* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect */
+/* Bit 2 : Channel 2 enable clear register. Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
#define DPPIC_CHENCLR_CH2_Msk (0x1UL << DPPIC_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
-#define DPPIC_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
-#define DPPIC_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */
+#define DPPIC_CHENCLR_CH2_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH2_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH2_Clear (1UL) /*!< Write: Disable channel */
-/* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect */
+/* Bit 1 : Channel 1 enable clear register. Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
#define DPPIC_CHENCLR_CH1_Msk (0x1UL << DPPIC_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
-#define DPPIC_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
-#define DPPIC_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */
+#define DPPIC_CHENCLR_CH1_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH1_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH1_Clear (1UL) /*!< Write: Disable channel */
-/* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect */
+/* Bit 0 : Channel 0 enable clear register. Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
#define DPPIC_CHENCLR_CH0_Msk (0x1UL << DPPIC_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
-#define DPPIC_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */
-#define DPPIC_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
-#define DPPIC_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
+#define DPPIC_CHENCLR_CH0_Disabled (0UL) /*!< Read: Channel disabled */
+#define DPPIC_CHENCLR_CH0_Enabled (1UL) /*!< Read: Channel enabled */
+#define DPPIC_CHENCLR_CH0_Clear (1UL) /*!< Write: Disable channel */
/* Register: DPPIC_CHG */
-/* Description: Description collection: Channel group n Note: Writes to this register is ignored if either SUBSCRIBE_CHG[n].EN/DIS are enabled. */
+/* Description: Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled */
/* Bit 15 : Include or exclude channel 15 */
#define DPPIC_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
@@ -926,9 +927,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define EGU_SUBSCRIBE_TRIGGER_EN_Disabled (0UL) /*!< Disable subscription */
#define EGU_SUBSCRIBE_TRIGGER_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task TRIGGER[n] will subscribe to */
+/* Bits 7..0 : DPPI channel that task TRIGGER[n] will subscribe to */
#define EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define EGU_SUBSCRIBE_TRIGGER_CHIDX_Msk (0xFUL << EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define EGU_SUBSCRIBE_TRIGGER_CHIDX_Msk (0xFFUL << EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: EGU_EVENTS_TRIGGERED */
/* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */
@@ -948,9 +949,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define EGU_PUBLISH_TRIGGERED_EN_Disabled (0UL) /*!< Disable publishing */
#define EGU_PUBLISH_TRIGGERED_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event TRIGGERED[n] will publish to. */
+/* Bits 7..0 : DPPI channel that event TRIGGERED[n] will publish to */
#define EGU_PUBLISH_TRIGGERED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define EGU_PUBLISH_TRIGGERED_CHIDX_Msk (0xFUL << EGU_PUBLISH_TRIGGERED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define EGU_PUBLISH_TRIGGERED_CHIDX_Msk (0xFFUL << EGU_PUBLISH_TRIGGERED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: EGU_INTEN */
/* Description: Enable or disable interrupt */
@@ -1285,6 +1286,28 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: FICR */
/* Description: Factory Information Configuration Registers */
+/* Register: FICR_SIPINFO_PARTNO */
+/* Description: SIP part number */
+
+/* Bits 31..0 : */
+#define FICR_SIPINFO_PARTNO_PARTNO_Pos (0UL) /*!< Position of PARTNO field. */
+#define FICR_SIPINFO_PARTNO_PARTNO_Msk (0xFFFFFFFFUL << FICR_SIPINFO_PARTNO_PARTNO_Pos) /*!< Bit mask of PARTNO field. */
+#define FICR_SIPINFO_PARTNO_PARTNO_9160 (0x00009160UL) /*!< Device is an nRF9160 sip */
+
+/* Register: FICR_SIPINFO_HWREVISION */
+/* Description: Description collection: SIP hardware revision, encoded in ASCII, ex B0A or B1A */
+
+/* Bits 7..0 : */
+#define FICR_SIPINFO_HWREVISION_HWREVISION_Pos (0UL) /*!< Position of HWREVISION field. */
+#define FICR_SIPINFO_HWREVISION_HWREVISION_Msk (0xFFUL << FICR_SIPINFO_HWREVISION_HWREVISION_Pos) /*!< Bit mask of HWREVISION field. */
+
+/* Register: FICR_SIPINFO_VARIANT */
+/* Description: Description collection: SIP VARIANT, encoded in ASCII, ex SIAA, SIBA or SICA */
+
+/* Bits 7..0 : */
+#define FICR_SIPINFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
+#define FICR_SIPINFO_VARIANT_VARIANT_Msk (0xFFUL << FICR_SIPINFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
+
/* Register: FICR_INFO_DEVICEID */
/* Description: Description collection: Device identifier */
@@ -1298,6 +1321,7 @@ POSSIBILITY OF SUCH DAMAGE.
/* Bits 31..0 : Part code */
#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
+#define FICR_INFO_PART_PART_N9120 (0x9120UL) /*!< nRF9120 */
#define FICR_INFO_PART_PART_N9160 (0x9160UL) /*!< nRF9160 */
/* Register: FICR_INFO_VARIANT */
@@ -1308,6 +1332,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
#define FICR_INFO_VARIANT_VARIANT_AAA0 (0x41414130UL) /*!< AAA0 */
#define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */
+#define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */
+#define FICR_INFO_VARIANT_VARIANT_AAC0 (0x41414330UL) /*!< AAC0 */
/* Register: FICR_INFO_PACKAGE */
/* Description: Package option */
@@ -1315,7 +1341,7 @@ POSSIBILITY OF SUCH DAMAGE.
/* Bits 31..0 : Package option */
#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
-#define FICR_INFO_PACKAGE_PACKAGE_CC (0x2000UL) /*!< CCxx - 236 ball wlCSP */
+#define FICR_INFO_PACKAGE_PACKAGE_CF (0x2002UL) /*!< CFxx - 236 ball wlCSP */
/* Register: FICR_INFO_RAM */
/* Description: RAM variant */
@@ -1340,13 +1366,15 @@ POSSIBILITY OF SUCH DAMAGE.
/* Bits 31..0 : Code memory page size */
#define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */
#define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */
+#define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_K4096 (0x1000UL) /*!< 4 kByte */
/* Register: FICR_INFO_CODESIZE */
/* Description: Code memory size */
-/* Bits 31..0 : Code memory size in number of pages */
+/* Bits 31..0 : Code memory size in number of pages Total code space is: CODEPAGESIZE * CODESIZE */
#define FICR_INFO_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */
#define FICR_INFO_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */
+#define FICR_INFO_CODESIZE_CODESIZE_P256 (256UL) /*!< 256 pages */
/* Register: FICR_INFO_DEVICETYPE */
/* Description: Device type */
@@ -1464,9 +1492,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define GPIOTE_SUBSCRIBE_OUT_EN_Disabled (0UL) /*!< Disable subscription */
#define GPIOTE_SUBSCRIBE_OUT_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task OUT[n] will subscribe to */
+/* Bits 7..0 : DPPI channel that task OUT[n] will subscribe to */
#define GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define GPIOTE_SUBSCRIBE_OUT_CHIDX_Msk (0xFUL << GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define GPIOTE_SUBSCRIBE_OUT_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: GPIOTE_SUBSCRIBE_SET */
/* Description: Description collection: Subscribe configuration for task SET[n] */
@@ -1477,9 +1505,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define GPIOTE_SUBSCRIBE_SET_EN_Disabled (0UL) /*!< Disable subscription */
#define GPIOTE_SUBSCRIBE_SET_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task SET[n] will subscribe to */
+/* Bits 7..0 : DPPI channel that task SET[n] will subscribe to */
#define GPIOTE_SUBSCRIBE_SET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define GPIOTE_SUBSCRIBE_SET_CHIDX_Msk (0xFUL << GPIOTE_SUBSCRIBE_SET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define GPIOTE_SUBSCRIBE_SET_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_SET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: GPIOTE_SUBSCRIBE_CLR */
/* Description: Description collection: Subscribe configuration for task CLR[n] */
@@ -1490,9 +1518,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define GPIOTE_SUBSCRIBE_CLR_EN_Disabled (0UL) /*!< Disable subscription */
#define GPIOTE_SUBSCRIBE_CLR_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task CLR[n] will subscribe to */
+/* Bits 7..0 : DPPI channel that task CLR[n] will subscribe to */
#define GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define GPIOTE_SUBSCRIBE_CLR_CHIDX_Msk (0xFUL << GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define GPIOTE_SUBSCRIBE_CLR_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: GPIOTE_EVENTS_IN */
/* Description: Description collection: Event generated from pin specified in CONFIG[n].PSEL */
@@ -1521,9 +1549,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define GPIOTE_PUBLISH_IN_EN_Disabled (0UL) /*!< Disable publishing */
#define GPIOTE_PUBLISH_IN_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event IN[n] will publish to. */
+/* Bits 7..0 : DPPI channel that event IN[n] will publish to */
#define GPIOTE_PUBLISH_IN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define GPIOTE_PUBLISH_IN_CHIDX_Msk (0xFUL << GPIOTE_PUBLISH_IN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define GPIOTE_PUBLISH_IN_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_IN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: GPIOTE_PUBLISH_PORT */
/* Description: Publish configuration for event PORT */
@@ -1534,9 +1562,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define GPIOTE_PUBLISH_PORT_EN_Disabled (0UL) /*!< Disable publishing */
#define GPIOTE_PUBLISH_PORT_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event PORT will publish to. */
+/* Bits 7..0 : DPPI channel that event PORT will publish to */
#define GPIOTE_PUBLISH_PORT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define GPIOTE_PUBLISH_PORT_CHIDX_Msk (0xFUL << GPIOTE_PUBLISH_PORT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define GPIOTE_PUBLISH_PORT_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_PORT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: GPIOTE_INTENSET */
/* Description: Enable interrupt */
@@ -1671,7 +1699,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
/* Register: GPIOTE_CONFIG */
-/* Description: Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */
+/* Description: Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event */
/* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
@@ -1687,7 +1715,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */
#define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */
-/* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */
+/* Bits 12..8 : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event */
#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
@@ -1727,9 +1755,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define I2S_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
#define I2S_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task START will subscribe to */
+/* Bits 7..0 : DPPI channel that task START will subscribe to */
#define I2S_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define I2S_SUBSCRIBE_START_CHIDX_Msk (0xFUL << I2S_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define I2S_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << I2S_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: I2S_SUBSCRIBE_STOP */
/* Description: Subscribe configuration for task STOP */
@@ -1740,9 +1768,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define I2S_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
#define I2S_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task STOP will subscribe to */
+/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
#define I2S_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define I2S_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << I2S_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define I2S_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << I2S_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: I2S_EVENTS_RXPTRUPD */
/* Description: The RXD.PTR register has been copied to internal double-buffers.
@@ -1784,9 +1812,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define I2S_PUBLISH_RXPTRUPD_EN_Disabled (0UL) /*!< Disable publishing */
#define I2S_PUBLISH_RXPTRUPD_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event RXPTRUPD will publish to. */
+/* Bits 7..0 : DPPI channel that event RXPTRUPD will publish to */
#define I2S_PUBLISH_RXPTRUPD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define I2S_PUBLISH_RXPTRUPD_CHIDX_Msk (0xFUL << I2S_PUBLISH_RXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define I2S_PUBLISH_RXPTRUPD_CHIDX_Msk (0xFFUL << I2S_PUBLISH_RXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: I2S_PUBLISH_STOPPED */
/* Description: Publish configuration for event STOPPED */
@@ -1797,9 +1825,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define I2S_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
#define I2S_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event STOPPED will publish to. */
+/* Bits 7..0 : DPPI channel that event STOPPED will publish to */
#define I2S_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define I2S_PUBLISH_STOPPED_CHIDX_Msk (0xFUL << I2S_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define I2S_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << I2S_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: I2S_PUBLISH_TXPTRUPD */
/* Description: Publish configuration for event TXPTRUPD */
@@ -1810,9 +1838,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define I2S_PUBLISH_TXPTRUPD_EN_Disabled (0UL) /*!< Disable publishing */
#define I2S_PUBLISH_TXPTRUPD_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event TXPTRUPD will publish to. */
+/* Bits 7..0 : DPPI channel that event TXPTRUPD will publish to */
#define I2S_PUBLISH_TXPTRUPD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define I2S_PUBLISH_TXPTRUPD_CHIDX_Msk (0xFUL << I2S_PUBLISH_TXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define I2S_PUBLISH_TXPTRUPD_CHIDX_Msk (0xFFUL << I2S_PUBLISH_TXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: I2S_INTEN */
/* Description: Enable or disable interrupt */
@@ -2090,12 +2118,12 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: IPC */
-/* Description: Inter Processor Communication 0 */
+/* Description: Interprocessor communication 0 */
/* Register: IPC_TASKS_SEND */
-/* Description: Description collection: Trigger events on channel enabled in SEND_CNF[n]. */
+/* Description: Description collection: Trigger events on IPC channel enabled in SEND_CNF[n] */
-/* Bit 0 : Trigger events on channel enabled in SEND_CNF[n]. */
+/* Bit 0 : Trigger events on IPC channel enabled in SEND_CNF[n] */
#define IPC_TASKS_SEND_TASKS_SEND_Pos (0UL) /*!< Position of TASKS_SEND field. */
#define IPC_TASKS_SEND_TASKS_SEND_Msk (0x1UL << IPC_TASKS_SEND_TASKS_SEND_Pos) /*!< Bit mask of TASKS_SEND field. */
#define IPC_TASKS_SEND_TASKS_SEND_Trigger (1UL) /*!< Trigger task */
@@ -2109,14 +2137,14 @@ POSSIBILITY OF SUCH DAMAGE.
#define IPC_SUBSCRIBE_SEND_EN_Disabled (0UL) /*!< Disable subscription */
#define IPC_SUBSCRIBE_SEND_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task SEND[n] will subscribe to */
+/* Bits 7..0 : DPPI channel that task SEND[n] will subscribe to */
#define IPC_SUBSCRIBE_SEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define IPC_SUBSCRIBE_SEND_CHIDX_Msk (0xFUL << IPC_SUBSCRIBE_SEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define IPC_SUBSCRIBE_SEND_CHIDX_Msk (0xFFUL << IPC_SUBSCRIBE_SEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: IPC_EVENTS_RECEIVE */
-/* Description: Description collection: Event received on one or more of the enabled channels in RECEIVE_CNF[n]. */
+/* Description: Description collection: Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] */
-/* Bit 0 : Event received on one or more of the enabled channels in RECEIVE_CNF[n]. */
+/* Bit 0 : Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] */
#define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos (0UL) /*!< Position of EVENTS_RECEIVE field. */
#define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Msk (0x1UL << IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos) /*!< Bit mask of EVENTS_RECEIVE field. */
#define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_NotGenerated (0UL) /*!< Event not generated */
@@ -2131,9 +2159,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define IPC_PUBLISH_RECEIVE_EN_Disabled (0UL) /*!< Disable publishing */
#define IPC_PUBLISH_RECEIVE_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event RECEIVE[n] will publish to. */
+/* Bits 7..0 : DPPI channel that event RECEIVE[n] will publish to */
#define IPC_PUBLISH_RECEIVE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define IPC_PUBLISH_RECEIVE_CHIDX_Msk (0xFUL << IPC_PUBLISH_RECEIVE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define IPC_PUBLISH_RECEIVE_CHIDX_Msk (0xFFUL << IPC_PUBLISH_RECEIVE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: IPC_INTEN */
/* Description: Enable or disable interrupt */
@@ -2356,109 +2384,109 @@ POSSIBILITY OF SUCH DAMAGE.
#define IPC_INTPEND_RECEIVE0_Pending (1UL) /*!< Read: Pending */
/* Register: IPC_SEND_CNF */
-/* Description: Description collection: Send event configuration for TASKS_SEND[n]. */
+/* Description: Description collection: Send event configuration for TASKS_SEND[n] */
-/* Bit 7 : Enable broadcasting on channel 7. */
+/* Bit 7 : Enable broadcasting on IPC channel 7 */
#define IPC_SEND_CNF_CHEN7_Pos (7UL) /*!< Position of CHEN7 field. */
#define IPC_SEND_CNF_CHEN7_Msk (0x1UL << IPC_SEND_CNF_CHEN7_Pos) /*!< Bit mask of CHEN7 field. */
-#define IPC_SEND_CNF_CHEN7_Disable (0UL) /*!< Disable broadcast. */
-#define IPC_SEND_CNF_CHEN7_Enable (1UL) /*!< Enable broadcast. */
+#define IPC_SEND_CNF_CHEN7_Disable (0UL) /*!< Disable broadcast */
+#define IPC_SEND_CNF_CHEN7_Enable (1UL) /*!< Enable broadcast */
-/* Bit 6 : Enable broadcasting on channel 6. */
+/* Bit 6 : Enable broadcasting on IPC channel 6 */
#define IPC_SEND_CNF_CHEN6_Pos (6UL) /*!< Position of CHEN6 field. */
#define IPC_SEND_CNF_CHEN6_Msk (0x1UL << IPC_SEND_CNF_CHEN6_Pos) /*!< Bit mask of CHEN6 field. */
-#define IPC_SEND_CNF_CHEN6_Disable (0UL) /*!< Disable broadcast. */
-#define IPC_SEND_CNF_CHEN6_Enable (1UL) /*!< Enable broadcast. */
+#define IPC_SEND_CNF_CHEN6_Disable (0UL) /*!< Disable broadcast */
+#define IPC_SEND_CNF_CHEN6_Enable (1UL) /*!< Enable broadcast */
-/* Bit 5 : Enable broadcasting on channel 5. */
+/* Bit 5 : Enable broadcasting on IPC channel 5 */
#define IPC_SEND_CNF_CHEN5_Pos (5UL) /*!< Position of CHEN5 field. */
#define IPC_SEND_CNF_CHEN5_Msk (0x1UL << IPC_SEND_CNF_CHEN5_Pos) /*!< Bit mask of CHEN5 field. */
-#define IPC_SEND_CNF_CHEN5_Disable (0UL) /*!< Disable broadcast. */
-#define IPC_SEND_CNF_CHEN5_Enable (1UL) /*!< Enable broadcast. */
+#define IPC_SEND_CNF_CHEN5_Disable (0UL) /*!< Disable broadcast */
+#define IPC_SEND_CNF_CHEN5_Enable (1UL) /*!< Enable broadcast */
-/* Bit 4 : Enable broadcasting on channel 4. */
+/* Bit 4 : Enable broadcasting on IPC channel 4 */
#define IPC_SEND_CNF_CHEN4_Pos (4UL) /*!< Position of CHEN4 field. */
#define IPC_SEND_CNF_CHEN4_Msk (0x1UL << IPC_SEND_CNF_CHEN4_Pos) /*!< Bit mask of CHEN4 field. */
-#define IPC_SEND_CNF_CHEN4_Disable (0UL) /*!< Disable broadcast. */
-#define IPC_SEND_CNF_CHEN4_Enable (1UL) /*!< Enable broadcast. */
+#define IPC_SEND_CNF_CHEN4_Disable (0UL) /*!< Disable broadcast */
+#define IPC_SEND_CNF_CHEN4_Enable (1UL) /*!< Enable broadcast */
-/* Bit 3 : Enable broadcasting on channel 3. */
+/* Bit 3 : Enable broadcasting on IPC channel 3 */
#define IPC_SEND_CNF_CHEN3_Pos (3UL) /*!< Position of CHEN3 field. */
#define IPC_SEND_CNF_CHEN3_Msk (0x1UL << IPC_SEND_CNF_CHEN3_Pos) /*!< Bit mask of CHEN3 field. */
-#define IPC_SEND_CNF_CHEN3_Disable (0UL) /*!< Disable broadcast. */
-#define IPC_SEND_CNF_CHEN3_Enable (1UL) /*!< Enable broadcast. */
+#define IPC_SEND_CNF_CHEN3_Disable (0UL) /*!< Disable broadcast */
+#define IPC_SEND_CNF_CHEN3_Enable (1UL) /*!< Enable broadcast */
-/* Bit 2 : Enable broadcasting on channel 2. */
+/* Bit 2 : Enable broadcasting on IPC channel 2 */
#define IPC_SEND_CNF_CHEN2_Pos (2UL) /*!< Position of CHEN2 field. */
#define IPC_SEND_CNF_CHEN2_Msk (0x1UL << IPC_SEND_CNF_CHEN2_Pos) /*!< Bit mask of CHEN2 field. */
-#define IPC_SEND_CNF_CHEN2_Disable (0UL) /*!< Disable broadcast. */
-#define IPC_SEND_CNF_CHEN2_Enable (1UL) /*!< Enable broadcast. */
+#define IPC_SEND_CNF_CHEN2_Disable (0UL) /*!< Disable broadcast */
+#define IPC_SEND_CNF_CHEN2_Enable (1UL) /*!< Enable broadcast */
-/* Bit 1 : Enable broadcasting on channel 1. */
+/* Bit 1 : Enable broadcasting on IPC channel 1 */
#define IPC_SEND_CNF_CHEN1_Pos (1UL) /*!< Position of CHEN1 field. */
#define IPC_SEND_CNF_CHEN1_Msk (0x1UL << IPC_SEND_CNF_CHEN1_Pos) /*!< Bit mask of CHEN1 field. */
-#define IPC_SEND_CNF_CHEN1_Disable (0UL) /*!< Disable broadcast. */
-#define IPC_SEND_CNF_CHEN1_Enable (1UL) /*!< Enable broadcast. */
+#define IPC_SEND_CNF_CHEN1_Disable (0UL) /*!< Disable broadcast */
+#define IPC_SEND_CNF_CHEN1_Enable (1UL) /*!< Enable broadcast */
-/* Bit 0 : Enable broadcasting on channel 0. */
+/* Bit 0 : Enable broadcasting on IPC channel 0 */
#define IPC_SEND_CNF_CHEN0_Pos (0UL) /*!< Position of CHEN0 field. */
#define IPC_SEND_CNF_CHEN0_Msk (0x1UL << IPC_SEND_CNF_CHEN0_Pos) /*!< Bit mask of CHEN0 field. */
-#define IPC_SEND_CNF_CHEN0_Disable (0UL) /*!< Disable broadcast. */
-#define IPC_SEND_CNF_CHEN0_Enable (1UL) /*!< Enable broadcast. */
+#define IPC_SEND_CNF_CHEN0_Disable (0UL) /*!< Disable broadcast */
+#define IPC_SEND_CNF_CHEN0_Enable (1UL) /*!< Enable broadcast */
/* Register: IPC_RECEIVE_CNF */
-/* Description: Description collection: Receive event configuration for EVENTS_RECEIVE[n]. */
+/* Description: Description collection: Receive event configuration for EVENTS_RECEIVE[n] */
-/* Bit 7 : Enable subscription to channel 7. */
+/* Bit 7 : Enable subscription to IPC channel 7 */
#define IPC_RECEIVE_CNF_CHEN7_Pos (7UL) /*!< Position of CHEN7 field. */
#define IPC_RECEIVE_CNF_CHEN7_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN7_Pos) /*!< Bit mask of CHEN7 field. */
-#define IPC_RECEIVE_CNF_CHEN7_Disable (0UL) /*!< Disable events. */
-#define IPC_RECEIVE_CNF_CHEN7_Enable (1UL) /*!< Enable events. */
+#define IPC_RECEIVE_CNF_CHEN7_Disable (0UL) /*!< Disable events */
+#define IPC_RECEIVE_CNF_CHEN7_Enable (1UL) /*!< Enable events */
-/* Bit 6 : Enable subscription to channel 6. */
+/* Bit 6 : Enable subscription to IPC channel 6 */
#define IPC_RECEIVE_CNF_CHEN6_Pos (6UL) /*!< Position of CHEN6 field. */
#define IPC_RECEIVE_CNF_CHEN6_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN6_Pos) /*!< Bit mask of CHEN6 field. */
-#define IPC_RECEIVE_CNF_CHEN6_Disable (0UL) /*!< Disable events. */
-#define IPC_RECEIVE_CNF_CHEN6_Enable (1UL) /*!< Enable events. */
+#define IPC_RECEIVE_CNF_CHEN6_Disable (0UL) /*!< Disable events */
+#define IPC_RECEIVE_CNF_CHEN6_Enable (1UL) /*!< Enable events */
-/* Bit 5 : Enable subscription to channel 5. */
+/* Bit 5 : Enable subscription to IPC channel 5 */
#define IPC_RECEIVE_CNF_CHEN5_Pos (5UL) /*!< Position of CHEN5 field. */
#define IPC_RECEIVE_CNF_CHEN5_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN5_Pos) /*!< Bit mask of CHEN5 field. */
-#define IPC_RECEIVE_CNF_CHEN5_Disable (0UL) /*!< Disable events. */
-#define IPC_RECEIVE_CNF_CHEN5_Enable (1UL) /*!< Enable events. */
+#define IPC_RECEIVE_CNF_CHEN5_Disable (0UL) /*!< Disable events */
+#define IPC_RECEIVE_CNF_CHEN5_Enable (1UL) /*!< Enable events */
-/* Bit 4 : Enable subscription to channel 4. */
+/* Bit 4 : Enable subscription to IPC channel 4 */
#define IPC_RECEIVE_CNF_CHEN4_Pos (4UL) /*!< Position of CHEN4 field. */
#define IPC_RECEIVE_CNF_CHEN4_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN4_Pos) /*!< Bit mask of CHEN4 field. */
-#define IPC_RECEIVE_CNF_CHEN4_Disable (0UL) /*!< Disable events. */
-#define IPC_RECEIVE_CNF_CHEN4_Enable (1UL) /*!< Enable events. */
+#define IPC_RECEIVE_CNF_CHEN4_Disable (0UL) /*!< Disable events */
+#define IPC_RECEIVE_CNF_CHEN4_Enable (1UL) /*!< Enable events */
-/* Bit 3 : Enable subscription to channel 3. */
+/* Bit 3 : Enable subscription to IPC channel 3 */
#define IPC_RECEIVE_CNF_CHEN3_Pos (3UL) /*!< Position of CHEN3 field. */
#define IPC_RECEIVE_CNF_CHEN3_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN3_Pos) /*!< Bit mask of CHEN3 field. */
-#define IPC_RECEIVE_CNF_CHEN3_Disable (0UL) /*!< Disable events. */
-#define IPC_RECEIVE_CNF_CHEN3_Enable (1UL) /*!< Enable events. */
+#define IPC_RECEIVE_CNF_CHEN3_Disable (0UL) /*!< Disable events */
+#define IPC_RECEIVE_CNF_CHEN3_Enable (1UL) /*!< Enable events */
-/* Bit 2 : Enable subscription to channel 2. */
+/* Bit 2 : Enable subscription to IPC channel 2 */
#define IPC_RECEIVE_CNF_CHEN2_Pos (2UL) /*!< Position of CHEN2 field. */
#define IPC_RECEIVE_CNF_CHEN2_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN2_Pos) /*!< Bit mask of CHEN2 field. */
-#define IPC_RECEIVE_CNF_CHEN2_Disable (0UL) /*!< Disable events. */
-#define IPC_RECEIVE_CNF_CHEN2_Enable (1UL) /*!< Enable events. */
+#define IPC_RECEIVE_CNF_CHEN2_Disable (0UL) /*!< Disable events */
+#define IPC_RECEIVE_CNF_CHEN2_Enable (1UL) /*!< Enable events */
-/* Bit 1 : Enable subscription to channel 1. */
+/* Bit 1 : Enable subscription to IPC channel 1 */
#define IPC_RECEIVE_CNF_CHEN1_Pos (1UL) /*!< Position of CHEN1 field. */
#define IPC_RECEIVE_CNF_CHEN1_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN1_Pos) /*!< Bit mask of CHEN1 field. */
-#define IPC_RECEIVE_CNF_CHEN1_Disable (0UL) /*!< Disable events. */
-#define IPC_RECEIVE_CNF_CHEN1_Enable (1UL) /*!< Enable events. */
+#define IPC_RECEIVE_CNF_CHEN1_Disable (0UL) /*!< Disable events */
+#define IPC_RECEIVE_CNF_CHEN1_Enable (1UL) /*!< Enable events */
-/* Bit 0 : Enable subscription to channel 0. */
+/* Bit 0 : Enable subscription to IPC channel 0 */
#define IPC_RECEIVE_CNF_CHEN0_Pos (0UL) /*!< Position of CHEN0 field. */
#define IPC_RECEIVE_CNF_CHEN0_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN0_Pos) /*!< Bit mask of CHEN0 field. */
-#define IPC_RECEIVE_CNF_CHEN0_Disable (0UL) /*!< Disable events. */
-#define IPC_RECEIVE_CNF_CHEN0_Enable (1UL) /*!< Enable events. */
+#define IPC_RECEIVE_CNF_CHEN0_Disable (0UL) /*!< Disable events */
+#define IPC_RECEIVE_CNF_CHEN0_Enable (1UL) /*!< Enable events */
/* Register: IPC_GPMEM */
-/* Description: Description collection: General purpose memory. */
+/* Description: Description collection: General purpose memory */
/* Bits 31..0 : General purpose memory */
#define IPC_GPMEM_GPMEM_Pos (0UL) /*!< Position of GPMEM field. */
@@ -2611,7 +2639,7 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: KMU_SELECTKEYSLOT */
/* Description: Select key slot to be read over AHB or pushed over secure APB when TASKS_PUSH_KEYSLOT is started */
-/* Bits 7..0 : Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use NOTE: Index N in UICR->KEYSLOT.KEY[N] and UICR->KEYSLOT.CONFIG[N] corresponds to KMU key slot ID=N+1 */
+/* Bits 7..0 : Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started. NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use. NOTE: Index N in UICR->KEYSLOT.KEY[N] and UICR->KEYSLOT.CONFIG[N] corresponds to KMU key slot ID=N+1. */
#define KMU_SELECTKEYSLOT_ID_Pos (0UL) /*!< Position of ID field. */
#define KMU_SELECTKEYSLOT_ID_Msk (0xFFUL << KMU_SELECTKEYSLOT_ID_Pos) /*!< Bit mask of ID field. */
@@ -4216,193 +4244,193 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: GPIO_LATCH */
/* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */
-/* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */
+/* Bit 31 : Status on whether PIN[31] has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */
-/* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */
+/* Bit 30 : Status on whether PIN[30] has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */
-/* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */
+/* Bit 29 : Status on whether PIN[29] has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */
-/* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */
+/* Bit 28 : Status on whether PIN[28] has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */
-/* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */
+/* Bit 27 : Status on whether PIN[27] has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */
-/* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */
+/* Bit 26 : Status on whether PIN[26] has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */
-/* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */
+/* Bit 25 : Status on whether PIN[25] has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */
-/* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */
+/* Bit 24 : Status on whether PIN[24] has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */
-/* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */
+/* Bit 23 : Status on whether PIN[23] has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */
-/* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */
+/* Bit 22 : Status on whether PIN[22] has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */
-/* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */
+/* Bit 21 : Status on whether PIN[21] has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */
-/* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */
+/* Bit 20 : Status on whether PIN[20] has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */
-/* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */
+/* Bit 19 : Status on whether PIN[19] has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */
-/* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */
+/* Bit 18 : Status on whether PIN[18] has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */
-/* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */
+/* Bit 17 : Status on whether PIN[17] has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */
-/* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */
+/* Bit 16 : Status on whether PIN[16] has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */
-/* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */
+/* Bit 15 : Status on whether PIN[15] has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */
-/* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */
+/* Bit 14 : Status on whether PIN[14] has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */
-/* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */
+/* Bit 13 : Status on whether PIN[13] has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */
-/* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */
+/* Bit 12 : Status on whether PIN[12] has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */
-/* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */
+/* Bit 11 : Status on whether PIN[11] has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */
-/* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */
+/* Bit 10 : Status on whether PIN[10] has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */
-/* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */
+/* Bit 9 : Status on whether PIN[9] has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */
-/* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */
+/* Bit 8 : Status on whether PIN[8] has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */
-/* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */
+/* Bit 7 : Status on whether PIN[7] has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */
-/* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */
+/* Bit 6 : Status on whether PIN[6] has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */
-/* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */
+/* Bit 5 : Status on whether PIN[5] has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */
-/* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */
+/* Bit 4 : Status on whether PIN[4] has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */
-/* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */
+/* Bit 3 : Status on whether PIN[3] has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */
-/* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */
+/* Bit 2 : Status on whether PIN[2] has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */
-/* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */
+/* Bit 1 : Status on whether PIN[1] has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */
-/* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */
+/* Bit 0 : Status on whether PIN[0] has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */
@@ -4496,9 +4524,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define PDM_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
#define PDM_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task START will subscribe to */
+/* Bits 7..0 : DPPI channel that task START will subscribe to */
#define PDM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define PDM_SUBSCRIBE_START_CHIDX_Msk (0xFUL << PDM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define PDM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << PDM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: PDM_SUBSCRIBE_STOP */
/* Description: Subscribe configuration for task STOP */
@@ -4509,9 +4537,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define PDM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
#define PDM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task STOP will subscribe to */
+/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
#define PDM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define PDM_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << PDM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define PDM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << PDM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: PDM_EVENTS_STARTED */
/* Description: PDM transfer has started */
@@ -4549,9 +4577,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define PDM_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */
#define PDM_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event STARTED will publish to. */
+/* Bits 7..0 : DPPI channel that event STARTED will publish to */
#define PDM_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define PDM_PUBLISH_STARTED_CHIDX_Msk (0xFUL << PDM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define PDM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << PDM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: PDM_PUBLISH_STOPPED */
/* Description: Publish configuration for event STOPPED */
@@ -4562,9 +4590,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define PDM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
#define PDM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event STOPPED will publish to. */
+/* Bits 7..0 : DPPI channel that event STOPPED will publish to */
#define PDM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define PDM_PUBLISH_STOPPED_CHIDX_Msk (0xFUL << PDM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define PDM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << PDM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: PDM_PUBLISH_END */
/* Description: Publish configuration for event END */
@@ -4575,9 +4603,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define PDM_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */
#define PDM_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event END will publish to. */
+/* Bits 7..0 : DPPI channel that event END will publish to */
#define PDM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define PDM_PUBLISH_END_CHIDX_Msk (0xFUL << PDM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define PDM_PUBLISH_END_CHIDX_Msk (0xFFUL << PDM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: PDM_INTEN */
/* Description: Enable or disable interrupt */
@@ -4660,7 +4688,7 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: PDM_PDMCLKCTRL */
/* Description: PDM clock generator control */
-/* Bits 31..0 : PDM_CLK frequency */
+/* Bits 31..0 : PDM_CLK frequency configuration. */
#define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */
#define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */
#define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */
@@ -4673,7 +4701,7 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: PDM_MODE */
/* Description: Defines the routing of the connected PDM microphones' signals */
-/* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */
+/* Bit 1 : Defines on which PDM_CLK edge left (or mono) is sampled */
#define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */
#define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */
#define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */
@@ -4682,8 +4710,8 @@ POSSIBILITY OF SUCH DAMAGE.
/* Bit 0 : Mono or stereo operation */
#define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */
#define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */
-#define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */
-#define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */
+#define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] */
+#define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] */
/* Register: PDM_GAINL */
/* Description: Left output gain adjustment */
@@ -4691,9 +4719,9 @@ POSSIBILITY OF SUCH DAMAGE.
/* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust */
#define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */
#define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */
-#define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
-#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment */
-#define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
+#define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */
+#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */
+#define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */
/* Register: PDM_GAINR */
/* Description: Right output gain adjustment */
@@ -4701,9 +4729,9 @@ POSSIBILITY OF SUCH DAMAGE.
/* Bits 6..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */
#define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */
#define PDM_GAINR_GAINR_Msk (0x7FUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */
-#define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
-#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment */
-#define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
+#define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */
+#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */
+#define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */
/* Register: PDM_RATIO */
/* Description: Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. */
@@ -4783,9 +4811,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define POWER_SUBSCRIBE_CONSTLAT_EN_Disabled (0UL) /*!< Disable subscription */
#define POWER_SUBSCRIBE_CONSTLAT_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task CONSTLAT will subscribe to */
+/* Bits 7..0 : DPPI channel that task CONSTLAT will subscribe to */
#define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Msk (0xFUL << POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: POWER_SUBSCRIBE_LOWPWR */
/* Description: Subscribe configuration for task LOWPWR */
@@ -4796,9 +4824,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define POWER_SUBSCRIBE_LOWPWR_EN_Disabled (0UL) /*!< Disable subscription */
#define POWER_SUBSCRIBE_LOWPWR_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task LOWPWR will subscribe to */
+/* Bits 7..0 : DPPI channel that task LOWPWR will subscribe to */
#define POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define POWER_SUBSCRIBE_LOWPWR_CHIDX_Msk (0xFUL << POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define POWER_SUBSCRIBE_LOWPWR_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: POWER_EVENTS_POFWARN */
/* Description: Power failure warning */
@@ -4836,9 +4864,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define POWER_PUBLISH_POFWARN_EN_Disabled (0UL) /*!< Disable publishing */
#define POWER_PUBLISH_POFWARN_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event POFWARN will publish to. */
+/* Bits 7..0 : DPPI channel that event POFWARN will publish to */
#define POWER_PUBLISH_POFWARN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define POWER_PUBLISH_POFWARN_CHIDX_Msk (0xFUL << POWER_PUBLISH_POFWARN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define POWER_PUBLISH_POFWARN_CHIDX_Msk (0xFFUL << POWER_PUBLISH_POFWARN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: POWER_PUBLISH_SLEEPENTER */
/* Description: Publish configuration for event SLEEPENTER */
@@ -4849,9 +4877,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define POWER_PUBLISH_SLEEPENTER_EN_Disabled (0UL) /*!< Disable publishing */
#define POWER_PUBLISH_SLEEPENTER_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event SLEEPENTER will publish to. */
+/* Bits 7..0 : DPPI channel that event SLEEPENTER will publish to */
#define POWER_PUBLISH_SLEEPENTER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define POWER_PUBLISH_SLEEPENTER_CHIDX_Msk (0xFUL << POWER_PUBLISH_SLEEPENTER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define POWER_PUBLISH_SLEEPENTER_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPENTER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: POWER_PUBLISH_SLEEPEXIT */
/* Description: Publish configuration for event SLEEPEXIT */
@@ -4862,9 +4890,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define POWER_PUBLISH_SLEEPEXIT_EN_Disabled (0UL) /*!< Disable publishing */
#define POWER_PUBLISH_SLEEPEXIT_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event SLEEPEXIT will publish to. */
+/* Bits 7..0 : DPPI channel that event SLEEPEXIT will publish to */
#define POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define POWER_PUBLISH_SLEEPEXIT_CHIDX_Msk (0xFUL << POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define POWER_PUBLISH_SLEEPEXIT_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: POWER_INTEN */
/* Description: Enable or disable interrupt */
@@ -4996,6 +5024,24 @@ POSSIBILITY OF SUCH DAMAGE.
#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
+/* Register: POWER_LTEMODEM_STARTN */
+/* Description: Start LTE modem */
+
+/* Bit 0 : Start LTE modem */
+#define POWER_LTEMODEM_STARTN_STARTN_Pos (0UL) /*!< Position of STARTN field. */
+#define POWER_LTEMODEM_STARTN_STARTN_Msk (0x1UL << POWER_LTEMODEM_STARTN_STARTN_Pos) /*!< Bit mask of STARTN field. */
+#define POWER_LTEMODEM_STARTN_STARTN_Start (0UL) /*!< Start LTE modem */
+#define POWER_LTEMODEM_STARTN_STARTN_Hold (1UL) /*!< Hold LTE modem disabled */
+
+/* Register: POWER_LTEMODEM_FORCEOFF */
+/* Description: Force off LTE modem */
+
+/* Bit 0 : Force off LTE modem */
+#define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */
+#define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Msk (0x1UL << POWER_LTEMODEM_FORCEOFF_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */
+#define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Release (0UL) /*!< Release force off */
+#define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Hold (1UL) /*!< Hold force off active */
+
/* Peripheral: PWM */
/* Description: Pulse width modulation unit 0 */
@@ -5033,9 +5079,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define PWM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
#define PWM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task STOP will subscribe to */
+/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
#define PWM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define PWM_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << PWM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define PWM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: PWM_SUBSCRIBE_SEQSTART */
/* Description: Description collection: Subscribe configuration for task SEQSTART[n] */
@@ -5046,9 +5092,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define PWM_SUBSCRIBE_SEQSTART_EN_Disabled (0UL) /*!< Disable subscription */
#define PWM_SUBSCRIBE_SEQSTART_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task SEQSTART[n] will subscribe to */
+/* Bits 7..0 : DPPI channel that task SEQSTART[n] will subscribe to */
#define PWM_SUBSCRIBE_SEQSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define PWM_SUBSCRIBE_SEQSTART_CHIDX_Msk (0xFUL << PWM_SUBSCRIBE_SEQSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define PWM_SUBSCRIBE_SEQSTART_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_SEQSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: PWM_SUBSCRIBE_NEXTSTEP */
/* Description: Subscribe configuration for task NEXTSTEP */
@@ -5059,9 +5105,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define PWM_SUBSCRIBE_NEXTSTEP_EN_Disabled (0UL) /*!< Disable subscription */
#define PWM_SUBSCRIBE_NEXTSTEP_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task NEXTSTEP will subscribe to */
+/* Bits 7..0 : DPPI channel that task NEXTSTEP will subscribe to */
#define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Msk (0xFUL << PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: PWM_EVENTS_STOPPED */
/* Description: Response to STOP task, emitted when PWM pulses are no longer generated */
@@ -5117,9 +5163,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define PWM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
#define PWM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event STOPPED will publish to. */
+/* Bits 7..0 : DPPI channel that event STOPPED will publish to */
#define PWM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define PWM_PUBLISH_STOPPED_CHIDX_Msk (0xFUL << PWM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define PWM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << PWM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: PWM_PUBLISH_SEQSTARTED */
/* Description: Description collection: Publish configuration for event SEQSTARTED[n] */
@@ -5130,9 +5176,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define PWM_PUBLISH_SEQSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
#define PWM_PUBLISH_SEQSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event SEQSTARTED[n] will publish to. */
+/* Bits 7..0 : DPPI channel that event SEQSTARTED[n] will publish to */
#define PWM_PUBLISH_SEQSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define PWM_PUBLISH_SEQSTARTED_CHIDX_Msk (0xFUL << PWM_PUBLISH_SEQSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define PWM_PUBLISH_SEQSTARTED_CHIDX_Msk (0xFFUL << PWM_PUBLISH_SEQSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: PWM_PUBLISH_SEQEND */
/* Description: Description collection: Publish configuration for event SEQEND[n] */
@@ -5143,9 +5189,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define PWM_PUBLISH_SEQEND_EN_Disabled (0UL) /*!< Disable publishing */
#define PWM_PUBLISH_SEQEND_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event SEQEND[n] will publish to. */
+/* Bits 7..0 : DPPI channel that event SEQEND[n] will publish to */
#define PWM_PUBLISH_SEQEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define PWM_PUBLISH_SEQEND_CHIDX_Msk (0xFUL << PWM_PUBLISH_SEQEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define PWM_PUBLISH_SEQEND_CHIDX_Msk (0xFFUL << PWM_PUBLISH_SEQEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: PWM_PUBLISH_PWMPERIODEND */
/* Description: Publish configuration for event PWMPERIODEND */
@@ -5156,9 +5202,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define PWM_PUBLISH_PWMPERIODEND_EN_Disabled (0UL) /*!< Disable publishing */
#define PWM_PUBLISH_PWMPERIODEND_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event PWMPERIODEND will publish to. */
+/* Bits 7..0 : DPPI channel that event PWMPERIODEND will publish to */
#define PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define PWM_PUBLISH_PWMPERIODEND_CHIDX_Msk (0xFUL << PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define PWM_PUBLISH_PWMPERIODEND_CHIDX_Msk (0xFFUL << PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: PWM_PUBLISH_LOOPSDONE */
/* Description: Publish configuration for event LOOPSDONE */
@@ -5169,9 +5215,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define PWM_PUBLISH_LOOPSDONE_EN_Disabled (0UL) /*!< Disable publishing */
#define PWM_PUBLISH_LOOPSDONE_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event LOOPSDONE will publish to. */
+/* Bits 7..0 : DPPI channel that event LOOPSDONE will publish to */
#define PWM_PUBLISH_LOOPSDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define PWM_PUBLISH_LOOPSDONE_CHIDX_Msk (0xFUL << PWM_PUBLISH_LOOPSDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define PWM_PUBLISH_LOOPSDONE_CHIDX_Msk (0xFFUL << PWM_PUBLISH_LOOPSDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: PWM_SHORTS */
/* Description: Shortcuts between local events and tasks */
@@ -5475,6 +5521,15 @@ POSSIBILITY OF SUCH DAMAGE.
#define REGULATORS_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << REGULATORS_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
#define REGULATORS_SYSTEMOFF_SYSTEMOFF_Enable (1UL) /*!< Enable System OFF mode */
+/* Register: REGULATORS_EXTPOFCON */
+/* Description: External power failure warning configuration */
+
+/* Bit 0 : Enable or disable external power failure warning */
+#define REGULATORS_EXTPOFCON_POF_Pos (0UL) /*!< Position of POF field. */
+#define REGULATORS_EXTPOFCON_POF_Msk (0x1UL << REGULATORS_EXTPOFCON_POF_Pos) /*!< Bit mask of POF field. */
+#define REGULATORS_EXTPOFCON_POF_Disabled (0UL) /*!< Disable */
+#define REGULATORS_EXTPOFCON_POF_Enabled (1UL) /*!< Enable */
+
/* Register: REGULATORS_DCDCEN */
/* Description: Enable DC/DC mode of the main voltage regulator. */
@@ -5529,9 +5584,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define RTC_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
#define RTC_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task START will subscribe to */
+/* Bits 7..0 : DPPI channel that task START will subscribe to */
#define RTC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define RTC_SUBSCRIBE_START_CHIDX_Msk (0xFUL << RTC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define RTC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: RTC_SUBSCRIBE_STOP */
/* Description: Subscribe configuration for task STOP */
@@ -5542,9 +5597,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define RTC_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
#define RTC_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task STOP will subscribe to */
+/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
#define RTC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define RTC_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << RTC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define RTC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: RTC_SUBSCRIBE_CLEAR */
/* Description: Subscribe configuration for task CLEAR */
@@ -5555,9 +5610,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define RTC_SUBSCRIBE_CLEAR_EN_Disabled (0UL) /*!< Disable subscription */
#define RTC_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task CLEAR will subscribe to */
+/* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */
#define RTC_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define RTC_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFUL << RTC_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define RTC_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: RTC_SUBSCRIBE_TRIGOVRFLW */
/* Description: Subscribe configuration for task TRIGOVRFLW */
@@ -5568,9 +5623,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Disabled (0UL) /*!< Disable subscription */
#define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task TRIGOVRFLW will subscribe to */
+/* Bits 7..0 : DPPI channel that task TRIGOVRFLW will subscribe to */
#define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Msk (0xFUL << RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: RTC_EVENTS_TICK */
/* Description: Event on counter increment */
@@ -5608,9 +5663,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define RTC_PUBLISH_TICK_EN_Disabled (0UL) /*!< Disable publishing */
#define RTC_PUBLISH_TICK_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event TICK will publish to. */
+/* Bits 7..0 : DPPI channel that event TICK will publish to */
#define RTC_PUBLISH_TICK_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define RTC_PUBLISH_TICK_CHIDX_Msk (0xFUL << RTC_PUBLISH_TICK_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define RTC_PUBLISH_TICK_CHIDX_Msk (0xFFUL << RTC_PUBLISH_TICK_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: RTC_PUBLISH_OVRFLW */
/* Description: Publish configuration for event OVRFLW */
@@ -5621,9 +5676,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define RTC_PUBLISH_OVRFLW_EN_Disabled (0UL) /*!< Disable publishing */
#define RTC_PUBLISH_OVRFLW_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event OVRFLW will publish to. */
+/* Bits 7..0 : DPPI channel that event OVRFLW will publish to */
#define RTC_PUBLISH_OVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define RTC_PUBLISH_OVRFLW_CHIDX_Msk (0xFUL << RTC_PUBLISH_OVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define RTC_PUBLISH_OVRFLW_CHIDX_Msk (0xFFUL << RTC_PUBLISH_OVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: RTC_PUBLISH_COMPARE */
/* Description: Description collection: Publish configuration for event COMPARE[n] */
@@ -5634,9 +5689,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define RTC_PUBLISH_COMPARE_EN_Disabled (0UL) /*!< Disable publishing */
#define RTC_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event COMPARE[n] will publish to. */
+/* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to */
#define RTC_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define RTC_PUBLISH_COMPARE_CHIDX_Msk (0xFUL << RTC_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define RTC_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << RTC_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: RTC_INTENSET */
/* Description: Enable interrupt */
@@ -5735,37 +5790,37 @@ POSSIBILITY OF SUCH DAMAGE.
#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
-#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */
/* Bit 18 : Enable or disable event routing for event COMPARE[2] */
#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */
-#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */
/* Bit 17 : Enable or disable event routing for event COMPARE[1] */
#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */
-#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */
/* Bit 16 : Enable or disable event routing for event COMPARE[0] */
#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
-#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */
/* Bit 1 : Enable or disable event routing for event OVRFLW */
#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
-#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Disable */
+#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */
/* Bit 0 : Enable or disable event routing for event TICK */
#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
-#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Disable */
+#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */
/* Register: RTC_EVTENSET */
/* Description: Enable event routing */
@@ -5923,9 +5978,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define SAADC_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
#define SAADC_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task START will subscribe to */
+/* Bits 7..0 : DPPI channel that task START will subscribe to */
#define SAADC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define SAADC_SUBSCRIBE_START_CHIDX_Msk (0xFUL << SAADC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define SAADC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: SAADC_SUBSCRIBE_SAMPLE */
/* Description: Subscribe configuration for task SAMPLE */
@@ -5936,9 +5991,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define SAADC_SUBSCRIBE_SAMPLE_EN_Disabled (0UL) /*!< Disable subscription */
#define SAADC_SUBSCRIBE_SAMPLE_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task SAMPLE will subscribe to */
+/* Bits 7..0 : DPPI channel that task SAMPLE will subscribe to */
#define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFUL << SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: SAADC_SUBSCRIBE_STOP */
/* Description: Subscribe configuration for task STOP */
@@ -5949,9 +6004,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define SAADC_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
#define SAADC_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task STOP will subscribe to */
+/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
#define SAADC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define SAADC_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << SAADC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define SAADC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: SAADC_SUBSCRIBE_CALIBRATEOFFSET */
/* Description: Subscribe configuration for task CALIBRATEOFFSET */
@@ -5962,9 +6017,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Disabled (0UL) /*!< Disable subscription */
#define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task CALIBRATEOFFSET will subscribe to */
+/* Bits 7..0 : DPPI channel that task CALIBRATEOFFSET will subscribe to */
#define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Msk (0xFUL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: SAADC_EVENTS_STARTED */
/* Description: The ADC has started */
@@ -6047,9 +6102,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define SAADC_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */
#define SAADC_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event STARTED will publish to. */
+/* Bits 7..0 : DPPI channel that event STARTED will publish to */
#define SAADC_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define SAADC_PUBLISH_STARTED_CHIDX_Msk (0xFUL << SAADC_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define SAADC_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: SAADC_PUBLISH_END */
/* Description: Publish configuration for event END */
@@ -6060,9 +6115,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define SAADC_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */
#define SAADC_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event END will publish to. */
+/* Bits 7..0 : DPPI channel that event END will publish to */
#define SAADC_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define SAADC_PUBLISH_END_CHIDX_Msk (0xFUL << SAADC_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define SAADC_PUBLISH_END_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: SAADC_PUBLISH_DONE */
/* Description: Publish configuration for event DONE */
@@ -6073,9 +6128,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define SAADC_PUBLISH_DONE_EN_Disabled (0UL) /*!< Disable publishing */
#define SAADC_PUBLISH_DONE_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event DONE will publish to. */
+/* Bits 7..0 : DPPI channel that event DONE will publish to */
#define SAADC_PUBLISH_DONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define SAADC_PUBLISH_DONE_CHIDX_Msk (0xFUL << SAADC_PUBLISH_DONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define SAADC_PUBLISH_DONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_DONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: SAADC_PUBLISH_RESULTDONE */
/* Description: Publish configuration for event RESULTDONE */
@@ -6086,9 +6141,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define SAADC_PUBLISH_RESULTDONE_EN_Disabled (0UL) /*!< Disable publishing */
#define SAADC_PUBLISH_RESULTDONE_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event RESULTDONE will publish to. */
+/* Bits 7..0 : DPPI channel that event RESULTDONE will publish to */
#define SAADC_PUBLISH_RESULTDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define SAADC_PUBLISH_RESULTDONE_CHIDX_Msk (0xFUL << SAADC_PUBLISH_RESULTDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define SAADC_PUBLISH_RESULTDONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_RESULTDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: SAADC_PUBLISH_CALIBRATEDONE */
/* Description: Publish configuration for event CALIBRATEDONE */
@@ -6099,9 +6154,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define SAADC_PUBLISH_CALIBRATEDONE_EN_Disabled (0UL) /*!< Disable publishing */
#define SAADC_PUBLISH_CALIBRATEDONE_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event CALIBRATEDONE will publish to. */
+/* Bits 7..0 : DPPI channel that event CALIBRATEDONE will publish to */
#define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Msk (0xFUL << SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: SAADC_PUBLISH_STOPPED */
/* Description: Publish configuration for event STOPPED */
@@ -6112,9 +6167,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define SAADC_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
#define SAADC_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event STOPPED will publish to. */
+/* Bits 7..0 : DPPI channel that event STOPPED will publish to */
#define SAADC_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define SAADC_PUBLISH_STOPPED_CHIDX_Msk (0xFUL << SAADC_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define SAADC_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: SAADC_PUBLISH_CH_LIMITH */
/* Description: Description cluster: Publish configuration for event CH[n].LIMITH */
@@ -6125,9 +6180,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define SAADC_PUBLISH_CH_LIMITH_EN_Disabled (0UL) /*!< Disable publishing */
#define SAADC_PUBLISH_CH_LIMITH_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event CH[n].LIMITH will publish to. */
+/* Bits 7..0 : DPPI channel that event CH[n].LIMITH will publish to */
#define SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define SAADC_PUBLISH_CH_LIMITH_CHIDX_Msk (0xFUL << SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define SAADC_PUBLISH_CH_LIMITH_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: SAADC_PUBLISH_CH_LIMITL */
/* Description: Description cluster: Publish configuration for event CH[n].LIMITL */
@@ -6138,9 +6193,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define SAADC_PUBLISH_CH_LIMITL_EN_Disabled (0UL) /*!< Disable publishing */
#define SAADC_PUBLISH_CH_LIMITL_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event CH[n].LIMITL will publish to. */
+/* Bits 7..0 : DPPI channel that event CH[n].LIMITL will publish to */
#define SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define SAADC_PUBLISH_CH_LIMITL_CHIDX_Msk (0xFUL << SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define SAADC_PUBLISH_CH_LIMITL_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: SAADC_INTEN */
/* Description: Enable or disable interrupt */
@@ -6819,9 +6874,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPIM_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
#define SPIM_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task START will subscribe to */
+/* Bits 7..0 : DPPI channel that task START will subscribe to */
#define SPIM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define SPIM_SUBSCRIBE_START_CHIDX_Msk (0xFUL << SPIM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define SPIM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: SPIM_SUBSCRIBE_STOP */
/* Description: Subscribe configuration for task STOP */
@@ -6832,9 +6887,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPIM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
#define SPIM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task STOP will subscribe to */
+/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
#define SPIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define SPIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << SPIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define SPIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: SPIM_SUBSCRIBE_SUSPEND */
/* Description: Subscribe configuration for task SUSPEND */
@@ -6845,9 +6900,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPIM_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */
#define SPIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task SUSPEND will subscribe to */
+/* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */
#define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFUL << SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: SPIM_SUBSCRIBE_RESUME */
/* Description: Subscribe configuration for task RESUME */
@@ -6858,9 +6913,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPIM_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */
#define SPIM_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task RESUME will subscribe to */
+/* Bits 7..0 : DPPI channel that task RESUME will subscribe to */
#define SPIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define SPIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFUL << SPIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define SPIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: SPIM_EVENTS_STOPPED */
/* Description: SPI transaction has stopped */
@@ -6916,9 +6971,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPIM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
#define SPIM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event STOPPED will publish to. */
+/* Bits 7..0 : DPPI channel that event STOPPED will publish to */
#define SPIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define SPIM_PUBLISH_STOPPED_CHIDX_Msk (0xFUL << SPIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define SPIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: SPIM_PUBLISH_ENDRX */
/* Description: Publish configuration for event ENDRX */
@@ -6929,9 +6984,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPIM_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */
#define SPIM_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event ENDRX will publish to. */
+/* Bits 7..0 : DPPI channel that event ENDRX will publish to */
#define SPIM_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define SPIM_PUBLISH_ENDRX_CHIDX_Msk (0xFUL << SPIM_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define SPIM_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: SPIM_PUBLISH_END */
/* Description: Publish configuration for event END */
@@ -6942,9 +6997,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPIM_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */
#define SPIM_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event END will publish to. */
+/* Bits 7..0 : DPPI channel that event END will publish to */
#define SPIM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define SPIM_PUBLISH_END_CHIDX_Msk (0xFUL << SPIM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define SPIM_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: SPIM_PUBLISH_ENDTX */
/* Description: Publish configuration for event ENDTX */
@@ -6955,9 +7010,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPIM_PUBLISH_ENDTX_EN_Disabled (0UL) /*!< Disable publishing */
#define SPIM_PUBLISH_ENDTX_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event ENDTX will publish to. */
+/* Bits 7..0 : DPPI channel that event ENDTX will publish to */
#define SPIM_PUBLISH_ENDTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define SPIM_PUBLISH_ENDTX_CHIDX_Msk (0xFUL << SPIM_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define SPIM_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: SPIM_PUBLISH_STARTED */
/* Description: Publish configuration for event STARTED */
@@ -6968,9 +7023,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPIM_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */
#define SPIM_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event STARTED will publish to. */
+/* Bits 7..0 : DPPI channel that event STARTED will publish to */
#define SPIM_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define SPIM_PUBLISH_STARTED_CHIDX_Msk (0xFUL << SPIM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define SPIM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: SPIM_SHORTS */
/* Description: Shortcuts between local events and tasks */
@@ -7236,9 +7291,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPIS_SUBSCRIBE_ACQUIRE_EN_Disabled (0UL) /*!< Disable subscription */
#define SPIS_SUBSCRIBE_ACQUIRE_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task ACQUIRE will subscribe to */
+/* Bits 7..0 : DPPI channel that task ACQUIRE will subscribe to */
#define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Msk (0xFUL << SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: SPIS_SUBSCRIBE_RELEASE */
/* Description: Subscribe configuration for task RELEASE */
@@ -7249,9 +7304,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPIS_SUBSCRIBE_RELEASE_EN_Disabled (0UL) /*!< Disable subscription */
#define SPIS_SUBSCRIBE_RELEASE_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task RELEASE will subscribe to */
+/* Bits 7..0 : DPPI channel that task RELEASE will subscribe to */
#define SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define SPIS_SUBSCRIBE_RELEASE_CHIDX_Msk (0xFUL << SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define SPIS_SUBSCRIBE_RELEASE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: SPIS_EVENTS_END */
/* Description: Granted transaction completed */
@@ -7289,9 +7344,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPIS_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */
#define SPIS_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event END will publish to. */
+/* Bits 7..0 : DPPI channel that event END will publish to */
#define SPIS_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define SPIS_PUBLISH_END_CHIDX_Msk (0xFUL << SPIS_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define SPIS_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: SPIS_PUBLISH_ENDRX */
/* Description: Publish configuration for event ENDRX */
@@ -7302,9 +7357,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPIS_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */
#define SPIS_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event ENDRX will publish to. */
+/* Bits 7..0 : DPPI channel that event ENDRX will publish to */
#define SPIS_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define SPIS_PUBLISH_ENDRX_CHIDX_Msk (0xFUL << SPIS_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define SPIS_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: SPIS_PUBLISH_ACQUIRED */
/* Description: Publish configuration for event ACQUIRED */
@@ -7315,9 +7370,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPIS_PUBLISH_ACQUIRED_EN_Disabled (0UL) /*!< Disable publishing */
#define SPIS_PUBLISH_ACQUIRED_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event ACQUIRED will publish to. */
+/* Bits 7..0 : DPPI channel that event ACQUIRED will publish to */
#define SPIS_PUBLISH_ACQUIRED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define SPIS_PUBLISH_ACQUIRED_CHIDX_Msk (0xFUL << SPIS_PUBLISH_ACQUIRED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define SPIS_PUBLISH_ACQUIRED_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ACQUIRED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: SPIS_SHORTS */
/* Description: Shortcuts between local events and tasks */
@@ -7600,9 +7655,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPU_PUBLISH_RAMACCERR_EN_Disabled (0UL) /*!< Disable publishing */
#define SPU_PUBLISH_RAMACCERR_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event RAMACCERR will publish to. */
+/* Bits 7..0 : DPPI channel that event RAMACCERR will publish to */
#define SPU_PUBLISH_RAMACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define SPU_PUBLISH_RAMACCERR_CHIDX_Msk (0xFUL << SPU_PUBLISH_RAMACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define SPU_PUBLISH_RAMACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_RAMACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: SPU_PUBLISH_FLASHACCERR */
/* Description: Publish configuration for event FLASHACCERR */
@@ -7613,9 +7668,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPU_PUBLISH_FLASHACCERR_EN_Disabled (0UL) /*!< Disable publishing */
#define SPU_PUBLISH_FLASHACCERR_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event FLASHACCERR will publish to. */
+/* Bits 7..0 : DPPI channel that event FLASHACCERR will publish to */
#define SPU_PUBLISH_FLASHACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define SPU_PUBLISH_FLASHACCERR_CHIDX_Msk (0xFUL << SPU_PUBLISH_FLASHACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define SPU_PUBLISH_FLASHACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_FLASHACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: SPU_PUBLISH_PERIPHACCERR */
/* Description: Publish configuration for event PERIPHACCERR */
@@ -7626,9 +7681,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPU_PUBLISH_PERIPHACCERR_EN_Disabled (0UL) /*!< Disable publishing */
#define SPU_PUBLISH_PERIPHACCERR_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event PERIPHACCERR will publish to. */
+/* Bits 7..0 : DPPI channel that event PERIPHACCERR will publish to */
#define SPU_PUBLISH_PERIPHACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define SPU_PUBLISH_PERIPHACCERR_CHIDX_Msk (0xFUL << SPU_PUBLISH_PERIPHACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define SPU_PUBLISH_PERIPHACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_PERIPHACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: SPU_INTEN */
/* Description: Enable or disable interrupt */
@@ -7723,7 +7778,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPU_EXTDOMAIN_PERM_SECATTR_NonSecure (0UL) /*!< Bus accesses from this domain have the non-secure attribute set */
#define SPU_EXTDOMAIN_PERM_SECATTR_Secure (1UL) /*!< Bus accesses from this domain have secure attribute set */
-/* Bits 1..0 : Define configuration capabilities for TrustZone Cortex-M secure attribute */
+/* Bits 1..0 : Define configuration capabilities for TrustZone Cortex-M secure attribute */
#define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Pos (0UL) /*!< Position of SECUREMAPPING field. */
#define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Msk (0x3UL << SPU_EXTDOMAIN_PERM_SECUREMAPPING_Pos) /*!< Bit mask of SECUREMAPPING field. */
#define SPU_EXTDOMAIN_PERM_SECUREMAPPING_NonSecure (0UL) /*!< The bus access from this external domain always have the non-secure attribute set */
@@ -8086,9 +8141,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPU_RAMNSC_REGION_LOCK_Unlocked (0UL) /*!< This register can be updated */
#define SPU_RAMNSC_REGION_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
-/* Bits 3..0 : Region number */
+/* Bits 4..0 : Region number */
#define SPU_RAMNSC_REGION_REGION_Pos (0UL) /*!< Position of REGION field. */
-#define SPU_RAMNSC_REGION_REGION_Msk (0xFUL << SPU_RAMNSC_REGION_REGION_Pos) /*!< Bit mask of REGION field. */
+#define SPU_RAMNSC_REGION_REGION_Msk (0x1FUL << SPU_RAMNSC_REGION_REGION_Pos) /*!< Bit mask of REGION field. */
/* Register: SPU_RAMNSC_SIZE */
/* Description: Description cluster: Define the size of the non-secure callable (NSC) region n */
@@ -8224,21 +8279,21 @@ POSSIBILITY OF SUCH DAMAGE.
/* Peripheral: TAD */
/* Description: Trace and debug control */
-/* Register: TAD_CLOCKSTART */
+/* Register: TAD_TASKS_CLOCKSTART */
/* Description: Start all trace and debug clocks. */
-/* Bit 0 : */
-#define TAD_CLOCKSTART_START_Pos (0UL) /*!< Position of START field. */
-#define TAD_CLOCKSTART_START_Msk (0x1UL << TAD_CLOCKSTART_START_Pos) /*!< Bit mask of START field. */
-#define TAD_CLOCKSTART_START_Start (1UL) /*!< Start all trace and debug clocks. */
+/* Bit 0 : Start all trace and debug clocks. */
+#define TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Pos (0UL) /*!< Position of TASKS_CLOCKSTART field. */
+#define TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Msk (0x1UL << TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Pos) /*!< Bit mask of TASKS_CLOCKSTART field. */
+#define TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Trigger (1UL) /*!< Trigger task */
-/* Register: TAD_CLOCKSTOP */
+/* Register: TAD_TASKS_CLOCKSTOP */
/* Description: Stop all trace and debug clocks. */
-/* Bit 0 : */
-#define TAD_CLOCKSTOP_STOP_Pos (0UL) /*!< Position of STOP field. */
-#define TAD_CLOCKSTOP_STOP_Msk (0x1UL << TAD_CLOCKSTOP_STOP_Pos) /*!< Bit mask of STOP field. */
-#define TAD_CLOCKSTOP_STOP_Stop (1UL) /*!< Stop all trace and debug clocks. */
+/* Bit 0 : Stop all trace and debug clocks. */
+#define TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Pos (0UL) /*!< Position of TASKS_CLOCKSTOP field. */
+#define TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Msk (0x1UL << TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Pos) /*!< Bit mask of TASKS_CLOCKSTOP field. */
+#define TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Trigger (1UL) /*!< Trigger task */
/* Register: TAD_ENABLE */
/* Description: Enable debug domain and aquire selected GPIOs */
@@ -8250,7 +8305,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define TAD_ENABLE_ENABLE_ENABLED (1UL) /*!< Enable debug domain and aquire selected GPIOs */
/* Register: TAD_PSEL_TRACECLK */
-/* Description: Pin number configuration for TRACECLK */
+/* Description: Pin configuration for TRACECLK */
/* Bit 31 : Connection */
#define TAD_PSEL_TRACECLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
@@ -8261,9 +8316,10 @@ POSSIBILITY OF SUCH DAMAGE.
/* Bits 4..0 : Pin number */
#define TAD_PSEL_TRACECLK_PIN_Pos (0UL) /*!< Position of PIN field. */
#define TAD_PSEL_TRACECLK_PIN_Msk (0x1FUL << TAD_PSEL_TRACECLK_PIN_Pos) /*!< Bit mask of PIN field. */
+#define TAD_PSEL_TRACECLK_PIN_Traceclk (21UL) /*!< TRACECLK pin */
/* Register: TAD_PSEL_TRACEDATA0 */
-/* Description: Pin number configuration for TRACEDATA[0] */
+/* Description: Pin configuration for TRACEDATA[0] */
/* Bit 31 : Connection */
#define TAD_PSEL_TRACEDATA0_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
@@ -8274,9 +8330,10 @@ POSSIBILITY OF SUCH DAMAGE.
/* Bits 4..0 : Pin number */
#define TAD_PSEL_TRACEDATA0_PIN_Pos (0UL) /*!< Position of PIN field. */
#define TAD_PSEL_TRACEDATA0_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA0_PIN_Pos) /*!< Bit mask of PIN field. */
+#define TAD_PSEL_TRACEDATA0_PIN_Tracedata0 (22UL) /*!< TRACEDATA0 pin */
/* Register: TAD_PSEL_TRACEDATA1 */
-/* Description: Pin number configuration for TRACEDATA[1] */
+/* Description: Pin configuration for TRACEDATA[1] */
/* Bit 31 : Connection */
#define TAD_PSEL_TRACEDATA1_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
@@ -8287,9 +8344,10 @@ POSSIBILITY OF SUCH DAMAGE.
/* Bits 4..0 : Pin number */
#define TAD_PSEL_TRACEDATA1_PIN_Pos (0UL) /*!< Position of PIN field. */
#define TAD_PSEL_TRACEDATA1_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA1_PIN_Pos) /*!< Bit mask of PIN field. */
+#define TAD_PSEL_TRACEDATA1_PIN_Tracedata1 (23UL) /*!< TRACEDATA1 pin */
/* Register: TAD_PSEL_TRACEDATA2 */
-/* Description: Pin number configuration for TRACEDATA[2] */
+/* Description: Pin configuration for TRACEDATA[2] */
/* Bit 31 : Connection */
#define TAD_PSEL_TRACEDATA2_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
@@ -8300,9 +8358,10 @@ POSSIBILITY OF SUCH DAMAGE.
/* Bits 4..0 : Pin number */
#define TAD_PSEL_TRACEDATA2_PIN_Pos (0UL) /*!< Position of PIN field. */
#define TAD_PSEL_TRACEDATA2_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA2_PIN_Pos) /*!< Bit mask of PIN field. */
+#define TAD_PSEL_TRACEDATA2_PIN_Tracedata2 (24UL) /*!< TRACEDATA2 pin */
/* Register: TAD_PSEL_TRACEDATA3 */
-/* Description: Pin number configuration for TRACEDATA[3] */
+/* Description: Pin configuration for TRACEDATA[3] */
/* Bit 31 : Connection */
#define TAD_PSEL_TRACEDATA3_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
@@ -8313,17 +8372,18 @@ POSSIBILITY OF SUCH DAMAGE.
/* Bits 4..0 : Pin number */
#define TAD_PSEL_TRACEDATA3_PIN_Pos (0UL) /*!< Position of PIN field. */
#define TAD_PSEL_TRACEDATA3_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA3_PIN_Pos) /*!< Bit mask of PIN field. */
+#define TAD_PSEL_TRACEDATA3_PIN_Tracedata3 (25UL) /*!< TRACEDATA3 pin */
/* Register: TAD_TRACEPORTSPEED */
-/* Description: Clocking options for the Trace Port debug interface */
+/* Description: Clocking options for the Trace Port debug interface Reset behavior is the same as debug components */
-/* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. */
+/* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock. */
#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */
#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Msk (0x3UL << TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */
-#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz Trace Port clock (TRACECLK = 16 MHz) */
-#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz Trace Port clock (TRACECLK = 8 MHz) */
-#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz Trace Port clock (TRACECLK = 4 MHz) */
-#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz Trace Port clock (TRACECLK = 2 MHz) */
+#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz (0UL) /*!< Trace Port clock is: 32MHz */
+#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_16MHz (1UL) /*!< Trace Port clock is: 16MHz */
+#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_8MHz (2UL) /*!< Trace Port clock is: 8MHz */
+#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_4MHz (3UL) /*!< Trace Port clock is: 4MHz */
/* Peripheral: TIMER */
@@ -8386,9 +8446,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define TIMER_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
#define TIMER_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task START will subscribe to */
+/* Bits 7..0 : DPPI channel that task START will subscribe to */
#define TIMER_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define TIMER_SUBSCRIBE_START_CHIDX_Msk (0xFUL << TIMER_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define TIMER_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: TIMER_SUBSCRIBE_STOP */
/* Description: Subscribe configuration for task STOP */
@@ -8399,9 +8459,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define TIMER_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
#define TIMER_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task STOP will subscribe to */
+/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
#define TIMER_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define TIMER_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << TIMER_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define TIMER_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: TIMER_SUBSCRIBE_COUNT */
/* Description: Subscribe configuration for task COUNT */
@@ -8412,9 +8472,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define TIMER_SUBSCRIBE_COUNT_EN_Disabled (0UL) /*!< Disable subscription */
#define TIMER_SUBSCRIBE_COUNT_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task COUNT will subscribe to */
+/* Bits 7..0 : DPPI channel that task COUNT will subscribe to */
#define TIMER_SUBSCRIBE_COUNT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define TIMER_SUBSCRIBE_COUNT_CHIDX_Msk (0xFUL << TIMER_SUBSCRIBE_COUNT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define TIMER_SUBSCRIBE_COUNT_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_COUNT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: TIMER_SUBSCRIBE_CLEAR */
/* Description: Subscribe configuration for task CLEAR */
@@ -8425,9 +8485,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define TIMER_SUBSCRIBE_CLEAR_EN_Disabled (0UL) /*!< Disable subscription */
#define TIMER_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task CLEAR will subscribe to */
+/* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */
#define TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define TIMER_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFUL << TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define TIMER_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: TIMER_SUBSCRIBE_SHUTDOWN */
/* Description: Deprecated register - Subscribe configuration for task SHUTDOWN */
@@ -8438,9 +8498,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define TIMER_SUBSCRIBE_SHUTDOWN_EN_Disabled (0UL) /*!< Disable subscription */
#define TIMER_SUBSCRIBE_SHUTDOWN_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task SHUTDOWN will subscribe to */
+/* Bits 7..0 : DPPI channel that task SHUTDOWN will subscribe to */
#define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Msk (0xFUL << TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: TIMER_SUBSCRIBE_CAPTURE */
/* Description: Description collection: Subscribe configuration for task CAPTURE[n] */
@@ -8451,9 +8511,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define TIMER_SUBSCRIBE_CAPTURE_EN_Disabled (0UL) /*!< Disable subscription */
#define TIMER_SUBSCRIBE_CAPTURE_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task CAPTURE[n] will subscribe to */
+/* Bits 7..0 : DPPI channel that task CAPTURE[n] will subscribe to */
#define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFUL << TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: TIMER_EVENTS_COMPARE */
/* Description: Description collection: Compare event on CC[n] match */
@@ -8473,9 +8533,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define TIMER_PUBLISH_COMPARE_EN_Disabled (0UL) /*!< Disable publishing */
#define TIMER_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event COMPARE[n] will publish to. */
+/* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to */
#define TIMER_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define TIMER_PUBLISH_COMPARE_CHIDX_Msk (0xFUL << TIMER_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define TIMER_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << TIMER_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: TIMER_SHORTS */
/* Description: Shortcuts between local events and tasks */
@@ -8739,9 +8799,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define TWIM_SUBSCRIBE_STARTRX_EN_Disabled (0UL) /*!< Disable subscription */
#define TWIM_SUBSCRIBE_STARTRX_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task STARTRX will subscribe to */
+/* Bits 7..0 : DPPI channel that task STARTRX will subscribe to */
#define TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define TWIM_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFUL << TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define TWIM_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: TWIM_SUBSCRIBE_STARTTX */
/* Description: Subscribe configuration for task STARTTX */
@@ -8752,9 +8812,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define TWIM_SUBSCRIBE_STARTTX_EN_Disabled (0UL) /*!< Disable subscription */
#define TWIM_SUBSCRIBE_STARTTX_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task STARTTX will subscribe to */
+/* Bits 7..0 : DPPI channel that task STARTTX will subscribe to */
#define TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define TWIM_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFUL << TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define TWIM_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: TWIM_SUBSCRIBE_STOP */
/* Description: Subscribe configuration for task STOP */
@@ -8765,9 +8825,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define TWIM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
#define TWIM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task STOP will subscribe to */
+/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
#define TWIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define TWIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << TWIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define TWIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: TWIM_SUBSCRIBE_SUSPEND */
/* Description: Subscribe configuration for task SUSPEND */
@@ -8778,9 +8838,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define TWIM_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */
#define TWIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task SUSPEND will subscribe to */
+/* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */
#define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFUL << TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: TWIM_SUBSCRIBE_RESUME */
/* Description: Subscribe configuration for task RESUME */
@@ -8791,9 +8851,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define TWIM_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */
#define TWIM_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task RESUME will subscribe to */
+/* Bits 7..0 : DPPI channel that task RESUME will subscribe to */
#define TWIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define TWIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFUL << TWIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define TWIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: TWIM_EVENTS_STOPPED */
/* Description: TWI stopped */
@@ -8867,9 +8927,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define TWIM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
#define TWIM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event STOPPED will publish to. */
+/* Bits 7..0 : DPPI channel that event STOPPED will publish to */
#define TWIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define TWIM_PUBLISH_STOPPED_CHIDX_Msk (0xFUL << TWIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define TWIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: TWIM_PUBLISH_ERROR */
/* Description: Publish configuration for event ERROR */
@@ -8880,9 +8940,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define TWIM_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */
#define TWIM_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event ERROR will publish to. */
+/* Bits 7..0 : DPPI channel that event ERROR will publish to */
#define TWIM_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define TWIM_PUBLISH_ERROR_CHIDX_Msk (0xFUL << TWIM_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define TWIM_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: TWIM_PUBLISH_SUSPENDED */
/* Description: Publish configuration for event SUSPENDED */
@@ -8893,9 +8953,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define TWIM_PUBLISH_SUSPENDED_EN_Disabled (0UL) /*!< Disable publishing */
#define TWIM_PUBLISH_SUSPENDED_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event SUSPENDED will publish to. */
+/* Bits 7..0 : DPPI channel that event SUSPENDED will publish to */
#define TWIM_PUBLISH_SUSPENDED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define TWIM_PUBLISH_SUSPENDED_CHIDX_Msk (0xFUL << TWIM_PUBLISH_SUSPENDED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define TWIM_PUBLISH_SUSPENDED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_SUSPENDED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: TWIM_PUBLISH_RXSTARTED */
/* Description: Publish configuration for event RXSTARTED */
@@ -8906,9 +8966,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define TWIM_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
#define TWIM_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event RXSTARTED will publish to. */
+/* Bits 7..0 : DPPI channel that event RXSTARTED will publish to */
#define TWIM_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define TWIM_PUBLISH_RXSTARTED_CHIDX_Msk (0xFUL << TWIM_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define TWIM_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: TWIM_PUBLISH_TXSTARTED */
/* Description: Publish configuration for event TXSTARTED */
@@ -8919,9 +8979,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define TWIM_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
#define TWIM_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event TXSTARTED will publish to. */
+/* Bits 7..0 : DPPI channel that event TXSTARTED will publish to */
#define TWIM_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define TWIM_PUBLISH_TXSTARTED_CHIDX_Msk (0xFUL << TWIM_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define TWIM_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: TWIM_PUBLISH_LASTRX */
/* Description: Publish configuration for event LASTRX */
@@ -8932,9 +8992,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define TWIM_PUBLISH_LASTRX_EN_Disabled (0UL) /*!< Disable publishing */
#define TWIM_PUBLISH_LASTRX_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event LASTRX will publish to. */
+/* Bits 7..0 : DPPI channel that event LASTRX will publish to */
#define TWIM_PUBLISH_LASTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define TWIM_PUBLISH_LASTRX_CHIDX_Msk (0xFUL << TWIM_PUBLISH_LASTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define TWIM_PUBLISH_LASTRX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: TWIM_PUBLISH_LASTTX */
/* Description: Publish configuration for event LASTTX */
@@ -8945,9 +9005,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define TWIM_PUBLISH_LASTTX_EN_Disabled (0UL) /*!< Disable publishing */
#define TWIM_PUBLISH_LASTTX_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event LASTTX will publish to. */
+/* Bits 7..0 : DPPI channel that event LASTTX will publish to */
#define TWIM_PUBLISH_LASTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define TWIM_PUBLISH_LASTTX_CHIDX_Msk (0xFUL << TWIM_PUBLISH_LASTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define TWIM_PUBLISH_LASTTX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: TWIM_SHORTS */
/* Description: Shortcuts between local events and tasks */
@@ -9323,9 +9383,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define TWIS_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
#define TWIS_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task STOP will subscribe to */
+/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
#define TWIS_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define TWIS_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << TWIS_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define TWIS_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: TWIS_SUBSCRIBE_SUSPEND */
/* Description: Subscribe configuration for task SUSPEND */
@@ -9336,9 +9396,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define TWIS_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */
#define TWIS_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task SUSPEND will subscribe to */
+/* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */
#define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFUL << TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: TWIS_SUBSCRIBE_RESUME */
/* Description: Subscribe configuration for task RESUME */
@@ -9349,9 +9409,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define TWIS_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */
#define TWIS_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task RESUME will subscribe to */
+/* Bits 7..0 : DPPI channel that task RESUME will subscribe to */
#define TWIS_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define TWIS_SUBSCRIBE_RESUME_CHIDX_Msk (0xFUL << TWIS_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define TWIS_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: TWIS_SUBSCRIBE_PREPARERX */
/* Description: Subscribe configuration for task PREPARERX */
@@ -9362,9 +9422,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define TWIS_SUBSCRIBE_PREPARERX_EN_Disabled (0UL) /*!< Disable subscription */
#define TWIS_SUBSCRIBE_PREPARERX_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task PREPARERX will subscribe to */
+/* Bits 7..0 : DPPI channel that task PREPARERX will subscribe to */
#define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Msk (0xFUL << TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: TWIS_SUBSCRIBE_PREPARETX */
/* Description: Subscribe configuration for task PREPARETX */
@@ -9375,9 +9435,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define TWIS_SUBSCRIBE_PREPARETX_EN_Disabled (0UL) /*!< Disable subscription */
#define TWIS_SUBSCRIBE_PREPARETX_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task PREPARETX will subscribe to */
+/* Bits 7..0 : DPPI channel that task PREPARETX will subscribe to */
#define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Msk (0xFUL << TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: TWIS_EVENTS_STOPPED */
/* Description: TWI stopped */
@@ -9442,9 +9502,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define TWIS_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
#define TWIS_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event STOPPED will publish to. */
+/* Bits 7..0 : DPPI channel that event STOPPED will publish to */
#define TWIS_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define TWIS_PUBLISH_STOPPED_CHIDX_Msk (0xFUL << TWIS_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define TWIS_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: TWIS_PUBLISH_ERROR */
/* Description: Publish configuration for event ERROR */
@@ -9455,9 +9515,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define TWIS_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */
#define TWIS_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event ERROR will publish to. */
+/* Bits 7..0 : DPPI channel that event ERROR will publish to */
#define TWIS_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define TWIS_PUBLISH_ERROR_CHIDX_Msk (0xFUL << TWIS_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define TWIS_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: TWIS_PUBLISH_RXSTARTED */
/* Description: Publish configuration for event RXSTARTED */
@@ -9468,9 +9528,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define TWIS_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
#define TWIS_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event RXSTARTED will publish to. */
+/* Bits 7..0 : DPPI channel that event RXSTARTED will publish to */
#define TWIS_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define TWIS_PUBLISH_RXSTARTED_CHIDX_Msk (0xFUL << TWIS_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define TWIS_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: TWIS_PUBLISH_TXSTARTED */
/* Description: Publish configuration for event TXSTARTED */
@@ -9481,9 +9541,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define TWIS_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
#define TWIS_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event TXSTARTED will publish to. */
+/* Bits 7..0 : DPPI channel that event TXSTARTED will publish to */
#define TWIS_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define TWIS_PUBLISH_TXSTARTED_CHIDX_Msk (0xFUL << TWIS_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define TWIS_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: TWIS_PUBLISH_WRITE */
/* Description: Publish configuration for event WRITE */
@@ -9494,9 +9554,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define TWIS_PUBLISH_WRITE_EN_Disabled (0UL) /*!< Disable publishing */
#define TWIS_PUBLISH_WRITE_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event WRITE will publish to. */
+/* Bits 7..0 : DPPI channel that event WRITE will publish to */
#define TWIS_PUBLISH_WRITE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define TWIS_PUBLISH_WRITE_CHIDX_Msk (0xFUL << TWIS_PUBLISH_WRITE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define TWIS_PUBLISH_WRITE_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_WRITE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: TWIS_PUBLISH_READ */
/* Description: Publish configuration for event READ */
@@ -9507,9 +9567,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define TWIS_PUBLISH_READ_EN_Disabled (0UL) /*!< Disable publishing */
#define TWIS_PUBLISH_READ_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event READ will publish to. */
+/* Bits 7..0 : DPPI channel that event READ will publish to */
#define TWIS_PUBLISH_READ_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define TWIS_PUBLISH_READ_CHIDX_Msk (0xFUL << TWIS_PUBLISH_READ_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define TWIS_PUBLISH_READ_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_READ_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: TWIS_SHORTS */
/* Description: Shortcuts between local events and tasks */
@@ -9679,7 +9739,7 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: TWIS_MATCH */
/* Description: Status register indicating which address had a match */
-/* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */
+/* Bit 0 : Indication of which address in {ADDRESS} that matched the incoming address */
#define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */
#define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */
@@ -9860,9 +9920,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE_SUBSCRIBE_STARTRX_EN_Disabled (0UL) /*!< Disable subscription */
#define UARTE_SUBSCRIBE_STARTRX_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task STARTRX will subscribe to */
+/* Bits 7..0 : DPPI channel that task STARTRX will subscribe to */
#define UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define UARTE_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFUL << UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define UARTE_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: UARTE_SUBSCRIBE_STOPRX */
/* Description: Subscribe configuration for task STOPRX */
@@ -9873,9 +9933,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE_SUBSCRIBE_STOPRX_EN_Disabled (0UL) /*!< Disable subscription */
#define UARTE_SUBSCRIBE_STOPRX_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task STOPRX will subscribe to */
+/* Bits 7..0 : DPPI channel that task STOPRX will subscribe to */
#define UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define UARTE_SUBSCRIBE_STOPRX_CHIDX_Msk (0xFUL << UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define UARTE_SUBSCRIBE_STOPRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: UARTE_SUBSCRIBE_STARTTX */
/* Description: Subscribe configuration for task STARTTX */
@@ -9886,9 +9946,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE_SUBSCRIBE_STARTTX_EN_Disabled (0UL) /*!< Disable subscription */
#define UARTE_SUBSCRIBE_STARTTX_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task STARTTX will subscribe to */
+/* Bits 7..0 : DPPI channel that task STARTTX will subscribe to */
#define UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define UARTE_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFUL << UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define UARTE_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: UARTE_SUBSCRIBE_STOPTX */
/* Description: Subscribe configuration for task STOPTX */
@@ -9899,9 +9959,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE_SUBSCRIBE_STOPTX_EN_Disabled (0UL) /*!< Disable subscription */
#define UARTE_SUBSCRIBE_STOPTX_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task STOPTX will subscribe to */
+/* Bits 7..0 : DPPI channel that task STOPTX will subscribe to */
#define UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define UARTE_SUBSCRIBE_STOPTX_CHIDX_Msk (0xFUL << UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define UARTE_SUBSCRIBE_STOPTX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: UARTE_SUBSCRIBE_FLUSHRX */
/* Description: Subscribe configuration for task FLUSHRX */
@@ -9912,9 +9972,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE_SUBSCRIBE_FLUSHRX_EN_Disabled (0UL) /*!< Disable subscription */
#define UARTE_SUBSCRIBE_FLUSHRX_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task FLUSHRX will subscribe to */
+/* Bits 7..0 : DPPI channel that task FLUSHRX will subscribe to */
#define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Msk (0xFUL << UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: UARTE_EVENTS_CTS */
/* Description: CTS is activated (set low). Clear To Send. */
@@ -10024,9 +10084,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE_PUBLISH_CTS_EN_Disabled (0UL) /*!< Disable publishing */
#define UARTE_PUBLISH_CTS_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event CTS will publish to. */
+/* Bits 7..0 : DPPI channel that event CTS will publish to */
#define UARTE_PUBLISH_CTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define UARTE_PUBLISH_CTS_CHIDX_Msk (0xFUL << UARTE_PUBLISH_CTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define UARTE_PUBLISH_CTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_CTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: UARTE_PUBLISH_NCTS */
/* Description: Publish configuration for event NCTS */
@@ -10037,9 +10097,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE_PUBLISH_NCTS_EN_Disabled (0UL) /*!< Disable publishing */
#define UARTE_PUBLISH_NCTS_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event NCTS will publish to. */
+/* Bits 7..0 : DPPI channel that event NCTS will publish to */
#define UARTE_PUBLISH_NCTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define UARTE_PUBLISH_NCTS_CHIDX_Msk (0xFUL << UARTE_PUBLISH_NCTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define UARTE_PUBLISH_NCTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_NCTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: UARTE_PUBLISH_RXDRDY */
/* Description: Publish configuration for event RXDRDY */
@@ -10050,9 +10110,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE_PUBLISH_RXDRDY_EN_Disabled (0UL) /*!< Disable publishing */
#define UARTE_PUBLISH_RXDRDY_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event RXDRDY will publish to. */
+/* Bits 7..0 : DPPI channel that event RXDRDY will publish to */
#define UARTE_PUBLISH_RXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define UARTE_PUBLISH_RXDRDY_CHIDX_Msk (0xFUL << UARTE_PUBLISH_RXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define UARTE_PUBLISH_RXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: UARTE_PUBLISH_ENDRX */
/* Description: Publish configuration for event ENDRX */
@@ -10063,9 +10123,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */
#define UARTE_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event ENDRX will publish to. */
+/* Bits 7..0 : DPPI channel that event ENDRX will publish to */
#define UARTE_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define UARTE_PUBLISH_ENDRX_CHIDX_Msk (0xFUL << UARTE_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define UARTE_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: UARTE_PUBLISH_TXDRDY */
/* Description: Publish configuration for event TXDRDY */
@@ -10076,9 +10136,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE_PUBLISH_TXDRDY_EN_Disabled (0UL) /*!< Disable publishing */
#define UARTE_PUBLISH_TXDRDY_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event TXDRDY will publish to. */
+/* Bits 7..0 : DPPI channel that event TXDRDY will publish to */
#define UARTE_PUBLISH_TXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define UARTE_PUBLISH_TXDRDY_CHIDX_Msk (0xFUL << UARTE_PUBLISH_TXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define UARTE_PUBLISH_TXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: UARTE_PUBLISH_ENDTX */
/* Description: Publish configuration for event ENDTX */
@@ -10089,9 +10149,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE_PUBLISH_ENDTX_EN_Disabled (0UL) /*!< Disable publishing */
#define UARTE_PUBLISH_ENDTX_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event ENDTX will publish to. */
+/* Bits 7..0 : DPPI channel that event ENDTX will publish to */
#define UARTE_PUBLISH_ENDTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define UARTE_PUBLISH_ENDTX_CHIDX_Msk (0xFUL << UARTE_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define UARTE_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: UARTE_PUBLISH_ERROR */
/* Description: Publish configuration for event ERROR */
@@ -10102,9 +10162,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */
#define UARTE_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event ERROR will publish to. */
+/* Bits 7..0 : DPPI channel that event ERROR will publish to */
#define UARTE_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define UARTE_PUBLISH_ERROR_CHIDX_Msk (0xFUL << UARTE_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define UARTE_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: UARTE_PUBLISH_RXTO */
/* Description: Publish configuration for event RXTO */
@@ -10115,9 +10175,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE_PUBLISH_RXTO_EN_Disabled (0UL) /*!< Disable publishing */
#define UARTE_PUBLISH_RXTO_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event RXTO will publish to. */
+/* Bits 7..0 : DPPI channel that event RXTO will publish to */
#define UARTE_PUBLISH_RXTO_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define UARTE_PUBLISH_RXTO_CHIDX_Msk (0xFUL << UARTE_PUBLISH_RXTO_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define UARTE_PUBLISH_RXTO_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXTO_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: UARTE_PUBLISH_RXSTARTED */
/* Description: Publish configuration for event RXSTARTED */
@@ -10128,9 +10188,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
#define UARTE_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event RXSTARTED will publish to. */
+/* Bits 7..0 : DPPI channel that event RXSTARTED will publish to */
#define UARTE_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define UARTE_PUBLISH_RXSTARTED_CHIDX_Msk (0xFUL << UARTE_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define UARTE_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: UARTE_PUBLISH_TXSTARTED */
/* Description: Publish configuration for event TXSTARTED */
@@ -10141,9 +10201,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
#define UARTE_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event TXSTARTED will publish to. */
+/* Bits 7..0 : DPPI channel that event TXSTARTED will publish to */
#define UARTE_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define UARTE_PUBLISH_TXSTARTED_CHIDX_Msk (0xFUL << UARTE_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define UARTE_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: UARTE_PUBLISH_TXSTOPPED */
/* Description: Publish configuration for event TXSTOPPED */
@@ -10154,9 +10214,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE_PUBLISH_TXSTOPPED_EN_Disabled (0UL) /*!< Disable publishing */
#define UARTE_PUBLISH_TXSTOPPED_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event TXSTOPPED will publish to. */
+/* Bits 7..0 : DPPI channel that event TXSTOPPED will publish to */
#define UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define UARTE_PUBLISH_TXSTOPPED_CHIDX_Msk (0xFUL << UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define UARTE_PUBLISH_TXSTOPPED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: UARTE_SHORTS */
/* Description: Shortcuts between local events and tasks */
@@ -10403,7 +10463,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
/* Register: UARTE_ERRORSRC */
-/* Description: Error source Note : this register is read / write one to clear. */
+/* Description: Error source This register is read/write one to clear. */
/* Bit 3 : Break condition */
#define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
@@ -10513,7 +10573,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
#define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */
#define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */
-#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
+#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud */
/* Register: UARTE_RXD_PTR */
/* Description: Data pointer */
@@ -10617,6 +10677,15 @@ POSSIBILITY OF SUCH DAMAGE.
#define UICR_HFXOCNT_HFXOCNT_MinDebounceTime (0UL) /*!< Min debounce time = (0*64 us + 0.5 us) */
#define UICR_HFXOCNT_HFXOCNT_MaxDebounceTime (255UL) /*!< Max debounce time = (255*64 us + 0.5 us) */
+/* Register: UICR_APPNVMCPOFGUARD */
+/* Description: Enable blocking NVM WRITE and aborting NVM ERASE for Application NVM in POFWARN condition . */
+
+/* Bit 0 : Enable blocking NVM WRITE and aborting NVM ERASE in POFWARN condition */
+#define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Pos (0UL) /*!< Position of NVMCPOFGUARDEN field. */
+#define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Msk (0x1UL << UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Pos) /*!< Bit mask of NVMCPOFGUARDEN field. */
+#define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Disabled (0UL) /*!< NVM WRITE and NVM ERASE are not blocked in POFWARN condition */
+#define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Enabled (1UL) /*!< NVM WRITE and NVM ERASE are blocked in POFWARN condition */
+
/* Register: UICR_SECUREAPPROTECT */
/* Description: Secure access port protection */
@@ -10649,9 +10718,9 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: UICR_KEYSLOT_CONFIG_DEST */
/* Description: Description cluster: Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE[0-3])
- will be pushed by KMU. Note that this address MUST match that of a peripherals
+ will be pushed by KMU. Note that this address must match that of a peripherals
APB mapped write-only key registers, else the KMU can push this key value into
- an address range which the CPU can potentially read! */
+ an address range which the CPU can potentially read. */
/* Bits 31..0 : Secure APB destination address */
#define UICR_KEYSLOT_CONFIG_DEST_DEST_Pos (0UL) /*!< Position of DEST field. */
@@ -10853,9 +10922,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define WDT_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
#define WDT_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
-/* Bits 3..0 : Channel that task START will subscribe to */
+/* Bits 7..0 : DPPI channel that task START will subscribe to */
#define WDT_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define WDT_SUBSCRIBE_START_CHIDX_Msk (0xFUL << WDT_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define WDT_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << WDT_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: WDT_EVENTS_TIMEOUT */
/* Description: Watchdog timeout */
@@ -10875,9 +10944,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define WDT_PUBLISH_TIMEOUT_EN_Disabled (0UL) /*!< Disable publishing */
#define WDT_PUBLISH_TIMEOUT_EN_Enabled (1UL) /*!< Enable publishing */
-/* Bits 3..0 : Channel that event TIMEOUT will publish to. */
+/* Bits 7..0 : DPPI channel that event TIMEOUT will publish to */
#define WDT_PUBLISH_TIMEOUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
-#define WDT_PUBLISH_TIMEOUT_CHIDX_Msk (0xFUL << WDT_PUBLISH_TIMEOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
+#define WDT_PUBLISH_TIMEOUT_CHIDX_Msk (0xFFUL << WDT_PUBLISH_TIMEOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
/* Register: WDT_INTENSET */
/* Description: Enable interrupt */
diff --git a/mcu/nrf/common/vendor/mdk/nrf9160_name_change.h b/mcu/nrf/common/vendor/mdk/nrf9160_name_change.h
index e3b4dbb7..2c24f1ba 100644
--- a/mcu/nrf/common/vendor/mdk/nrf9160_name_change.h
+++ b/mcu/nrf/common/vendor/mdk/nrf9160_name_change.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
+Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
@@ -35,24 +35,6 @@ POSSIBILITY OF SUCH DAMAGE.
#ifndef NRF9160_NAME_CHANGE_H
#define NRF9160_NAME_CHANGE_H
-/*lint ++flb "Enter library region */
-
-/* This file is given to prevent your SW from not compiling with the updates made to nrf9160.h and
- * nrf9160_bitfields.h. The macros defined in this file were available previously. Do not use these
- * macros on purpose. Use the ones defined in nrf9160.h and nrf9160_bitfields.h instead.
- */
-
- /* SAADC enums */
- /* Changes to enum names in SAADC */
- #define SAADC_CH_PSELP_PSELP_VDD SAADC_CH_PSELP_PSELP_VDDGPIO
- #define SAADC_CH_PSELP_PSELN_VDD SAADC_CH_PSELP_PSELN_VDDGPIO
-
- /* CTRLAP PERI Fields */
- #define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Pos CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos
- #define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Msk CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Msk
- #define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Unlocked CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Unlocked
- #define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Locked CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Locked
-
- /*lint --flb "Leave library region" */
+#include nrf91_name_change.h
#endif /* NRF9160_NAME_CHANGE_H */
diff --git a/mcu/nrf/common/vendor/mdk/nrf9160_peripherals.h b/mcu/nrf/common/vendor/mdk/nrf9160_peripherals.h
index 18fcd0a7..01095e38 100644
--- a/mcu/nrf/common/vendor/mdk/nrf9160_peripherals.h
+++ b/mcu/nrf/common/vendor/mdk/nrf9160_peripherals.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
+Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
@@ -52,6 +52,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define NVMC_FEATURE_CACHE_PRESENT
+/* Memory Protection Unit */
+#define MPU_REGION_NUM 16
+
/* GPIO */
#define GPIO_PRESENT
#define GPIO_COUNT 1
@@ -61,11 +64,11 @@ POSSIBILITY OF SUCH DAMAGE.
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
/* Distributed Peripheral to Peripheral Interconnect */
-#define DPPI_PRESENT
-#define DPPI_COUNT 1
+#define DPPIC_PRESENT
+#define DPPIC_COUNT 1
-#define DPPI_CH_NUM 16
-#define DPPI_GROUP_NUM 6
+#define DPPIC_CH_NUM 16
+#define DPPIC_GROUP_NUM 6
/* Event Generator Unit */
#define EGU_PRESENT
@@ -111,46 +114,46 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPIM2_MAX_DATARATE 8
#define SPIM3_MAX_DATARATE 8
-#define SPIM0_EASYDMA_MAXCNT_SIZE 12
-#define SPIM1_EASYDMA_MAXCNT_SIZE 12
-#define SPIM2_EASYDMA_MAXCNT_SIZE 12
-#define SPIM3_EASYDMA_MAXCNT_SIZE 12
+#define SPIM0_EASYDMA_MAXCNT_SIZE 13
+#define SPIM1_EASYDMA_MAXCNT_SIZE 13
+#define SPIM2_EASYDMA_MAXCNT_SIZE 13
+#define SPIM3_EASYDMA_MAXCNT_SIZE 13
/* Serial Peripheral Interface Slave with DMA*/
#define SPIS_PRESENT
#define SPIS_COUNT 4
-#define SPIS0_EASYDMA_MAXCNT_SIZE 12
-#define SPIS1_EASYDMA_MAXCNT_SIZE 12
-#define SPIS2_EASYDMA_MAXCNT_SIZE 12
-#define SPIS3_EASYDMA_MAXCNT_SIZE 12
+#define SPIS0_EASYDMA_MAXCNT_SIZE 13
+#define SPIS1_EASYDMA_MAXCNT_SIZE 13
+#define SPIS2_EASYDMA_MAXCNT_SIZE 13
+#define SPIS3_EASYDMA_MAXCNT_SIZE 13
/* Two Wire Interface Master with DMA */
#define TWIM_PRESENT
#define TWIM_COUNT 4
-#define TWIM0_EASYDMA_MAXCNT_SIZE 12
-#define TWIM1_EASYDMA_MAXCNT_SIZE 12
-#define TWIM2_EASYDMA_MAXCNT_SIZE 12
-#define TWIM3_EASYDMA_MAXCNT_SIZE 12
+#define TWIM0_EASYDMA_MAXCNT_SIZE 13
+#define TWIM1_EASYDMA_MAXCNT_SIZE 13
+#define TWIM2_EASYDMA_MAXCNT_SIZE 13
+#define TWIM3_EASYDMA_MAXCNT_SIZE 13
/* Two Wire Interface Slave with DMA */
#define TWIS_PRESENT
#define TWIS_COUNT 4
-#define TWIS0_EASYDMA_MAXCNT_SIZE 12
-#define TWIS1_EASYDMA_MAXCNT_SIZE 12
-#define TWIS2_EASYDMA_MAXCNT_SIZE 12
-#define TWIS3_EASYDMA_MAXCNT_SIZE 12
+#define TWIS0_EASYDMA_MAXCNT_SIZE 13
+#define TWIS1_EASYDMA_MAXCNT_SIZE 13
+#define TWIS2_EASYDMA_MAXCNT_SIZE 13
+#define TWIS3_EASYDMA_MAXCNT_SIZE 13
/* Universal Asynchronous Receiver-Transmitter with DMA */
#define UARTE_PRESENT
#define UARTE_COUNT 4
-#define UARTE0_EASYDMA_MAXCNT_SIZE 12
-#define UARTE1_EASYDMA_MAXCNT_SIZE 12
-#define UARTE2_EASYDMA_MAXCNT_SIZE 12
-#define UARTE3_EASYDMA_MAXCNT_SIZE 12
+#define UARTE0_EASYDMA_MAXCNT_SIZE 13
+#define UARTE1_EASYDMA_MAXCNT_SIZE 13
+#define UARTE2_EASYDMA_MAXCNT_SIZE 13
+#define UARTE3_EASYDMA_MAXCNT_SIZE 13
/* Successive Approximation Analog to Digital Converter */
#define SAADC_PRESENT
@@ -204,6 +207,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPU_PRESENT
#define SPU_COUNT 1
+#define SPU_RAMREGION_SIZE 0x2000ul
+
/* CRYPTOCELL */
#define CRYPTOCELL_PRESENT
#define CRYPTOCELL_COUNT 1
diff --git a/mcu/nrf/common/vendor/mdk/nrf91_name_change.h b/mcu/nrf/common/vendor/mdk/nrf91_name_change.h
new file mode 100644
index 00000000..eabe14fd
--- /dev/null
+++ b/mcu/nrf/common/vendor/mdk/nrf91_name_change.h
@@ -0,0 +1,85 @@
+/*
+
+Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
+
+SPDX-License-Identifier: BSD-3-Clause
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from this
+ software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef NRF91_NAME_CHANGE_H
+#define NRF91_NAME_CHANGE_H
+
+/*lint ++flb "Enter library region */
+
+/* This file is given to prevent your SW from not compiling with the updates made to nrf91-series
+ * headerfiles, like nrf9160.h and nrf9160_bitfields.h. The macros defined in this file were available
+ * previously. Do not use these macros on purpose. Use the ones defined in the respective nrf91-series
+ * header files.
+ */
+
+/* SAADC enums */
+/* Changes to enum names in SAADC */
+#define SAADC_CH_PSELP_PSELP_VDD SAADC_CH_PSELP_PSELP_VDDGPIO
+#define SAADC_CH_PSELP_PSELN_VDD SAADC_CH_PSELP_PSELN_VDDGPIO
+
+/* CTRLAP PERI Fields */
+#define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Pos CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos
+#define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Msk CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Msk
+#define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Unlocked CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Unlocked
+#define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Locked CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Locked
+
+ /* DPPI */
+ #define DPPI_PRESENT DPPIC_PRESENT
+ #define DPPI_COUNT DPPIC_COUNT
+ #define DPPI_CH_NUM DPPIC_CH_NUM
+ #define DPPI_GROUP_NUM DPPIC_GROUP_NUM
+
+
+/* The serial box interrupt ISRs were renamed. Adding old names as macros. */
+#define UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler
+#define UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn
+#define UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler
+#define UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQn
+#define UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler
+#define UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQn SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQn
+#define UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHanlder SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler
+#define UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQn SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQn
+
+/* TAD */
+
+#define TAD_CLOCKSTART_START_Pos TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Pos
+#define TAD_CLOCKSTART_START_Msk TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Msk
+#define TAD_CLOCKSTART_START_Start TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Trigger
+#define TAD_CLOCKSTOP_STOP_Pos TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Pos
+#define TAD_CLOCKSTOP_STOP_Msk TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Msk
+#define TAD_CLOCKSTOP_STOP_Stop TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Trigger
+
+/*lint --flb "Leave library region" */
+
+#endif /* NRF91_NAME_CHANGE_H */
diff --git a/mcu/nrf/common/vendor/mdk/nrf_peripherals.h b/mcu/nrf/common/vendor/mdk/nrf_peripherals.h
index 3f982920..750ab015 100644
--- a/mcu/nrf/common/vendor/mdk/nrf_peripherals.h
+++ b/mcu/nrf/common/vendor/mdk/nrf_peripherals.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
+Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
SPDX-License-Identifier: BSD-3-Clause
@@ -60,11 +60,13 @@ POSSIBILITY OF SUCH DAMAGE.
#elif defined (NRF5340_XXAA_NETWORK)
#include "nrf5340_network_peripherals.h"
+#elif defined(NRF9120_XXAA)
+ #include "nrf9120_peripherals.h"
#elif defined(NRF9160_XXAA)
#include "nrf9160_peripherals.h"
#else
- #error "Device must be defined. See nrf.h."
+ #error "Device must be defined. See nrf_peripherals.h."
#endif
/*lint --flb "Leave library region" */
diff --git a/mcu/nrf/common/vendor/mdk/system_nrf.h b/mcu/nrf/common/vendor/mdk/system_nrf.h
index bbc17985..8e16aaf7 100644
--- a/mcu/nrf/common/vendor/mdk/system_nrf.h
+++ b/mcu/nrf/common/vendor/mdk/system_nrf.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2009-2021 ARM Limited. All rights reserved.
+Copyright (c) 2009-2023 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
@@ -22,35 +22,33 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA.
#ifndef SYSTEM_NRF_H
#define SYSTEM_NRF_H
-
+#ifndef __ASSEMBLY__
#ifdef __cplusplus
extern "C" {
#endif
#include
+/**
+ \brief Exception / Interrupt Handler Function Prototype
+*/
+typedef void(*VECTOR_TABLE_Type)(void);
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+/**
+ \brief System Clock Frequency (Core Clock)
+*/
+extern uint32_t SystemCoreClock;
/**
- * Initialize the system
- *
- * @param none
- * @return none
- *
- * @brief Setup the microcontroller system.
- * Initialize the System and update the SystemCoreClock variable.
+ \brief Setup the microcontroller system.
+ Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
+
/**
- * Update SystemCoreClock variable
- *
- * @param none
- * @return none
- *
- * @brief Updates the SystemCoreClock with current core Clock
- * retrieved from cpu registers.
+ \brief Update SystemCoreClock variable.
+ Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
@@ -58,4 +56,5 @@ extern void SystemCoreClockUpdate (void);
}
#endif
+#endif /* __ASSEMBLY__ */
#endif /* SYSTEM_NRF_H */
diff --git a/mcu/nrf/common/vendor/mdk/system_nrf52.h b/mcu/nrf/common/vendor/mdk/system_nrf52.h
index bd3919cb..c24ae901 100644
--- a/mcu/nrf/common/vendor/mdk/system_nrf52.h
+++ b/mcu/nrf/common/vendor/mdk/system_nrf52.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2009-2021 ARM Limited. All rights reserved.
+Copyright (c) 2009-2023 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
@@ -22,40 +22,40 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA.
#ifndef SYSTEM_NRF52_H
#define SYSTEM_NRF52_H
-
+#ifndef __ASSEMBLY__
#ifdef __cplusplus
extern "C" {
#endif
#include
+/**
+ \brief Exception / Interrupt Handler Function Prototype
+*/
+typedef void(*VECTOR_TABLE_Type)(void);
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+/**
+ \brief System Clock Frequency (Core Clock)
+*/
+extern uint32_t SystemCoreClock;
/**
- * Initialize the system
- *
- * @param none
- * @return none
- *
- * @brief Setup the microcontroller system.
- * Initialize the System and update the SystemCoreClock variable.
+ \brief Setup the microcontroller system.
+ Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
+
/**
- * Update SystemCoreClock variable
- *
- * @param none
- * @return none
- *
- * @brief Updates the SystemCoreClock with current core Clock
- * retrieved from cpu registers.
+ \brief Update SystemCoreClock variable.
+ Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
+
#ifdef __cplusplus
}
#endif
+#endif /* __ASSEMBLY__ */
#endif /* SYSTEM_NRF52_H */
diff --git a/mcu/nrf/common/vendor/mdk/system_nrf52833.h b/mcu/nrf/common/vendor/mdk/system_nrf52833.h
index 342967a8..90388110 100644
--- a/mcu/nrf/common/vendor/mdk/system_nrf52833.h
+++ b/mcu/nrf/common/vendor/mdk/system_nrf52833.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2009-2021 ARM Limited. All rights reserved.
+Copyright (c) 2009-2023 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
@@ -22,40 +22,40 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA.
#ifndef SYSTEM_NRF52833_H
#define SYSTEM_NRF52833_H
-
+#ifndef __ASSEMBLY__
#ifdef __cplusplus
extern "C" {
#endif
#include
+/**
+ \brief Exception / Interrupt Handler Function Prototype
+*/
+typedef void(*VECTOR_TABLE_Type)(void);
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+/**
+ \brief System Clock Frequency (Core Clock)
+*/
+extern uint32_t SystemCoreClock;
/**
- * Initialize the system
- *
- * @param none
- * @return none
- *
- * @brief Setup the microcontroller system.
- * Initialize the System and update the SystemCoreClock variable.
+ \brief Setup the microcontroller system.
+ Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
+
/**
- * Update SystemCoreClock variable
- *
- * @param none
- * @return none
- *
- * @brief Updates the SystemCoreClock with current core Clock
- * retrieved from cpu registers.
+ \brief Update SystemCoreClock variable.
+ Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
+
#ifdef __cplusplus
}
#endif
+#endif /* __ASSEMBLY__ */
#endif /* SYSTEM_NRF52833_H */
diff --git a/mcu/nrf/common/vendor/mdk/system_nrf52840.h b/mcu/nrf/common/vendor/mdk/system_nrf52840.h
index 3df49a46..2b4d4fd0 100644
--- a/mcu/nrf/common/vendor/mdk/system_nrf52840.h
+++ b/mcu/nrf/common/vendor/mdk/system_nrf52840.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2009-2021 ARM Limited. All rights reserved.
+Copyright (c) 2009-2023 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
@@ -22,40 +22,40 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA.
#ifndef SYSTEM_NRF52840_H
#define SYSTEM_NRF52840_H
-
+#ifndef __ASSEMBLY__
#ifdef __cplusplus
extern "C" {
#endif
#include
+/**
+ \brief Exception / Interrupt Handler Function Prototype
+*/
+typedef void(*VECTOR_TABLE_Type)(void);
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+/**
+ \brief System Clock Frequency (Core Clock)
+*/
+extern uint32_t SystemCoreClock;
/**
- * Initialize the system
- *
- * @param none
- * @return none
- *
- * @brief Setup the microcontroller system.
- * Initialize the System and update the SystemCoreClock variable.
+ \brief Setup the microcontroller system.
+ Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
+
/**
- * Update SystemCoreClock variable
- *
- * @param none
- * @return none
- *
- * @brief Updates the SystemCoreClock with current core Clock
- * retrieved from cpu registers.
+ \brief Update SystemCoreClock variable.
+ Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
+
#ifdef __cplusplus
}
#endif
+#endif /* __ASSEMBLY__ */
#endif /* SYSTEM_NRF52840_H */
diff --git a/mcu/nrf/common/vendor/mdk/system_nrf9120.h b/mcu/nrf/common/vendor/mdk/system_nrf9120.h
new file mode 100644
index 00000000..3951be9e
--- /dev/null
+++ b/mcu/nrf/common/vendor/mdk/system_nrf9120.h
@@ -0,0 +1,61 @@
+/*
+
+Copyright (c) 2009-2023 ARM Limited. All rights reserved.
+
+ SPDX-License-Identifier: Apache-2.0
+
+Licensed under the Apache License, Version 2.0 (the License); you may
+not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an AS IS BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+NOTICE: This file has been modified by Nordic Semiconductor ASA.
+
+*/
+
+#ifndef SYSTEM_NRF9120_H
+#define SYSTEM_NRF9120_H
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include
+
+/**
+ \brief Exception / Interrupt Handler Function Prototype
+*/
+typedef void(*VECTOR_TABLE_Type)(void);
+
+/**
+ \brief System Clock Frequency (Core Clock)
+*/
+extern uint32_t SystemCoreClock;
+
+/**
+ \brief Setup the microcontroller system.
+ Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+ \brief Update SystemCoreClock variable.
+ Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* SYSTEM_NRF9120_H */
diff --git a/mcu/nrf/common/vendor/mdk/system_nrf9160.h b/mcu/nrf/common/vendor/mdk/system_nrf9160.h
index 1afad061..ac562026 100644
--- a/mcu/nrf/common/vendor/mdk/system_nrf9160.h
+++ b/mcu/nrf/common/vendor/mdk/system_nrf9160.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2009-2021 ARM Limited. All rights reserved.
+Copyright (c) 2009-2023 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
@@ -22,40 +22,40 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA.
#ifndef SYSTEM_NRF9160_H
#define SYSTEM_NRF9160_H
-
+#ifndef __ASSEMBLY__
#ifdef __cplusplus
extern "C" {
#endif
#include
+/**
+ \brief Exception / Interrupt Handler Function Prototype
+*/
+typedef void(*VECTOR_TABLE_Type)(void);
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+/**
+ \brief System Clock Frequency (Core Clock)
+*/
+extern uint32_t SystemCoreClock;
/**
- * Initialize the system
- *
- * @param none
- * @return none
- *
- * @brief Setup the microcontroller system.
- * Initialize the System and update the SystemCoreClock variable.
+ \brief Setup the microcontroller system.
+ Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
+
/**
- * Update SystemCoreClock variable
- *
- * @param none
- * @return none
- *
- * @brief Updates the SystemCoreClock with current core Clock
- * retrieved from cpu registers.
+ \brief Update SystemCoreClock variable.
+ Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
+
#ifdef __cplusplus
}
#endif
+#endif /* __ASSEMBLY__ */
#endif /* SYSTEM_NRF9160_H */
diff --git a/mcu/nrf/common/vendor/nrfx.h b/mcu/nrf/common/vendor/nrfx.h
index e5bda376..87ee6963 100644
--- a/mcu/nrf/common/vendor/nrfx.h
+++ b/mcu/nrf/common/vendor/nrfx.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA
+ * Copyright (c) 2017 - 2023, Nordic Semiconductor ASA
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -38,6 +38,7 @@
#include
#include
#include
+#include
#include
#endif // NRFX_H__
diff --git a/mcu/nrf/common/vendor/templates/nrfx_config.h b/mcu/nrf/common/vendor/templates/nrfx_config.h
index dccf675d..5b88e68b 100644
--- a/mcu/nrf/common/vendor/templates/nrfx_config.h
+++ b/mcu/nrf/common/vendor/templates/nrfx_config.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA
+ * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -34,6 +34,7 @@
#ifndef NRFX_CONFIG_H__
#define NRFX_CONFIG_H__
+#include
#if defined(NRF51)
#include
#elif defined(NRF52805_XXAA)
@@ -54,10 +55,10 @@
#include
#elif defined(NRF5340_XXAA_NETWORK)
#include
-#elif defined(NRF9160_XXAA)
- #include
+#elif defined(NRF9120_XXAA) || defined(NRF9160_XXAA)
+ #include
#else
- #error "Unknown device."
+ #include "nrfx_config_ext.h"
#endif
#endif // NRFX_CONFIG_H__
diff --git a/mcu/nrf/common/vendor/templates/nrfx_config_common.h b/mcu/nrf/common/vendor/templates/nrfx_config_common.h
new file mode 100644
index 00000000..beca3298
--- /dev/null
+++ b/mcu/nrf/common/vendor/templates/nrfx_config_common.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2022 - 2023, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRFX_CONFIG_COMMON_H__
+#define NRFX_CONFIG_COMMON_H__
+
+#ifndef NRFX_CONFIG_H__
+#error "This file should not be included directly. Include nrfx_config.h instead."
+#endif
+
+/** @brief Symbol specifying major version of the nrfx API to be used. */
+#ifndef NRFX_CONFIG_API_VER_MAJOR
+#define NRFX_CONFIG_API_VER_MAJOR 3
+#endif
+
+/** @brief Symbol specifying minor version of the nrfx API to be used. */
+#ifndef NRFX_CONFIG_API_VER_MINOR
+#define NRFX_CONFIG_API_VER_MINOR 0
+#endif
+
+/** @brief Symbol specifying micro version of the nrfx API to be used. */
+#ifndef NRFX_CONFIG_API_VER_MICRO
+#define NRFX_CONFIG_API_VER_MICRO 0
+#endif
+
+#endif /* NRFX_CONFIG_COMMON_H__ */
diff --git a/mcu/nrf/common/vendor/templates/nrfx_config_nrf52832.h b/mcu/nrf/common/vendor/templates/nrfx_config_nrf52832.h
index 2ebe2f51..f9fb9eed 100644
--- a/mcu/nrf/common/vendor/templates/nrfx_config_nrf52832.h
+++ b/mcu/nrf/common/vendor/templates/nrfx_config_nrf52832.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA
+ * Copyright (c) 2017 - 2023, Nordic Semiconductor ASA
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -38,2224 +38,1590 @@
#error "This file should not be included directly. Include nrfx_config.h instead."
#endif
-// <<< Use Configuration Wizard in Context Menu >>>\n
-// nRF_Drivers
+/**
+ * @brief NRFX_DEFAULT_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_DEFAULT_IRQ_PRIORITY
+#define NRFX_DEFAULT_IRQ_PRIORITY 7
+#endif
-// NRFX_CLOCK_ENABLED - nrfx_clock - CLOCK peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_CLOCK_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_CLOCK_ENABLED
#define NRFX_CLOCK_ENABLED 0
#endif
-// NRFX_CLOCK_CONFIG_LF_SRC - LF Clock Source
-
-// <0=> RC
-// <1=> XTAL
-// <2=> Synth
-// <131073=> External Low Swing
-// <196609=> External Full Swing
+/**
+ * @brief NRFX_CLOCK_CONFIG_LF_SRC
+ *
+ * Integer value.
+ * Supported values:
+ * - RC = 0
+ * - XTAL = 1
+ * - Synth = 2
+ * - External Low Swing = 131073
+ * - External Full Swing = 196609
+ */
#ifndef NRFX_CLOCK_CONFIG_LF_SRC
#define NRFX_CLOCK_CONFIG_LF_SRC 1
#endif
-// NRFX_CLOCK_CONFIG_LF_CAL_ENABLED - Enables LF Clock Calibration Support
-
+/**
+ * @brief NRFX_CLOCK_CONFIG_LF_CAL_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_CLOCK_CONFIG_LF_CAL_ENABLED
#define NRFX_CLOCK_CONFIG_LF_CAL_ENABLED 0
#endif
-// NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED - Enables two-stage LFXO start procedure
-
-// If set to a non-zero value, LFRC will be started before LFXO and corresponding
-// event will be generated. It means that CPU will be woken up when LFRC
-// oscillator starts, but user callback will be invoked only after LFXO
-// finally starts.
+/**
+ * @brief NRFX_CLOCK_CONFIG_CT_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_CLOCK_CONFIG_CT_ENABLED
+#define NRFX_CLOCK_CONFIG_CT_ENABLED 1
+#endif
+/**
+ * @brief NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED
#define NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED 0
#endif
-// NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_CLOCK_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_CLOCK_CONFIG_LOG_ENABLED
#define NRFX_CLOCK_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_CLOCK_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_CLOCK_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_CLOCK_CONFIG_LOG_LEVEL
#define NRFX_CLOCK_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_CLOCK_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_CLOCK_CONFIG_INFO_COLOR
-#define NRFX_CLOCK_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_CLOCK_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_CLOCK_CONFIG_DEBUG_COLOR
-#define NRFX_CLOCK_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_COMP_ENABLED - nrfx_comp - COMP peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_COMP_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_COMP_ENABLED
#define NRFX_COMP_ENABLED 0
#endif
-// NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_COMP_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_COMP_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_COMP_CONFIG_LOG_ENABLED
#define NRFX_COMP_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_COMP_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_COMP_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_COMP_CONFIG_LOG_LEVEL
#define NRFX_COMP_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_COMP_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_COMP_CONFIG_INFO_COLOR
-#define NRFX_COMP_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_COMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_COMP_CONFIG_DEBUG_COLOR
-#define NRFX_COMP_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_EGU_ENABLED - nrfx_egu - EGU peripheral driver.
-//==========================================================
+/**
+ * @brief NRFX_EGU_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_EGU_ENABLED
#define NRFX_EGU_ENABLED 0
#endif
-// NRFX_EGU0_ENABLED - Enable EGU0 instance.
+/**
+ * @brief NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+/**
+ * @brief NRFX_EGU0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_EGU0_ENABLED
#define NRFX_EGU0_ENABLED 0
#endif
-// NRFX_EGU1_ENABLED - Enable EGU1 instance.
-
+/**
+ * @brief NRFX_EGU1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_EGU1_ENABLED
#define NRFX_EGU1_ENABLED 0
#endif
-// NRFX_EGU2_ENABLED - Enable EGU2 instance.
-
+/**
+ * @brief NRFX_EGU2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_EGU2_ENABLED
#define NRFX_EGU2_ENABLED 0
#endif
-// NRFX_EGU3_ENABLED - Enable EGU3 instance.
-
+/**
+ * @brief NRFX_EGU3_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_EGU3_ENABLED
#define NRFX_EGU3_ENABLED 0
#endif
-// NRFX_EGU4_ENABLED - Enable EGU4 instance.
-
+/**
+ * @brief NRFX_EGU4_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_EGU4_ENABLED
#define NRFX_EGU4_ENABLED 0
#endif
-// NRFX_EGU5_ENABLED - Enable EGU5 instance.
-
+/**
+ * @brief NRFX_EGU5_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_EGU5_ENABLED
#define NRFX_EGU5_ENABLED 0
#endif
-// NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority.
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-//
-
-// NRFX_GPIOTE_ENABLED - nrfx_gpiote - GPIOTE peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_GPIOTE_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_GPIOTE_ENABLED
#define NRFX_GPIOTE_ENABLED 0
#endif
-// NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins
-#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS
-#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1
-#endif
-
-// NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
+/**
+ * @brief NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS
+ *
+ * Integer value. Minimum: 0 Maximum: 15
+ */
+#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS
+#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 2
#endif
-// NRFX_GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_GPIOTE_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED
#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_GPIOTE_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_GPIOTE_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL
#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_GPIOTE_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_GPIOTE_CONFIG_INFO_COLOR
-#define NRFX_GPIOTE_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_GPIOTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_GPIOTE_CONFIG_DEBUG_COLOR
-#define NRFX_GPIOTE_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_I2S_ENABLED - nrfx_i2s - I2S peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_I2S_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_I2S_ENABLED
#define NRFX_I2S_ENABLED 0
#endif
-// NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_I2S_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_I2S_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_I2S_CONFIG_LOG_ENABLED
#define NRFX_I2S_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_I2S_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_I2S_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_I2S_CONFIG_LOG_LEVEL
#define NRFX_I2S_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_I2S_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_I2S_CONFIG_INFO_COLOR
-#define NRFX_I2S_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_I2S_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_I2S_CONFIG_DEBUG_COLOR
-#define NRFX_I2S_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_LPCOMP_ENABLED - nrfx_lpcomp - LPCOMP peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_LPCOMP_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_LPCOMP_ENABLED
#define NRFX_LPCOMP_ENABLED 0
#endif
-// NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_LPCOMP_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_LPCOMP_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED
#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_LPCOMP_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_LPCOMP_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL
#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_LPCOMP_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_LPCOMP_CONFIG_INFO_COLOR
-#define NRFX_LPCOMP_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_LPCOMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_LPCOMP_CONFIG_DEBUG_COLOR
-#define NRFX_LPCOMP_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_NFCT_ENABLED - nrfx_nfct - NFCT peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_NFCT_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_NFCT_ENABLED
#define NRFX_NFCT_ENABLED 0
#endif
-// NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
+/**
+ * @brief NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID - Timer instance used for workarounds in the driver.
-
-// <0=> 0
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-
+/**
+ * @brief NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID - Timer instance used for workarounds in the driver.
+ *
+ * Integer value. Minimum: 0 Maximum: 5
+ */
#ifndef NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID
#define NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID 4
#endif
-// NRFX_NFCT_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_NFCT_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_NFCT_CONFIG_LOG_ENABLED
#define NRFX_NFCT_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_NFCT_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_NFCT_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_NFCT_CONFIG_LOG_LEVEL
#define NRFX_NFCT_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_NFCT_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_NFCT_CONFIG_INFO_COLOR
-#define NRFX_NFCT_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_NFCT_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_NFCT_CONFIG_DEBUG_COLOR
-#define NRFX_NFCT_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_NVMC_ENABLED - nrfx_nvmc - NVMC peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_NVMC_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_NVMC_ENABLED
#define NRFX_NVMC_ENABLED 0
#endif
-//
-
-// NRFX_PDM_ENABLED - nrfx_pdm - PDM peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_PDM_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PDM_ENABLED
#define NRFX_PDM_ENABLED 0
#endif
-// NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_PDM_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_PDM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PDM_CONFIG_LOG_ENABLED
#define NRFX_PDM_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_PDM_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_PDM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_PDM_CONFIG_LOG_LEVEL
#define NRFX_PDM_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_PDM_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_PDM_CONFIG_INFO_COLOR
-#define NRFX_PDM_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_PDM_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_PDM_CONFIG_DEBUG_COLOR
-#define NRFX_PDM_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_POWER_ENABLED - nrfx_power - POWER peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_POWER_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_POWER_ENABLED
#define NRFX_POWER_ENABLED 0
#endif
-// NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
+/**
+ * @brief NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-//
-
-// NRFX_PPI_ENABLED - nrfx_ppi - PPI peripheral allocator
-//==========================================================
+/**
+ * @brief NRFX_PPI_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PPI_ENABLED
#define NRFX_PPI_ENABLED 0
#endif
-// NRFX_PPI_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+
+/**
+ * @brief NRFX_PPI_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PPI_CONFIG_LOG_ENABLED
#define NRFX_PPI_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_PPI_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_PPI_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_PPI_CONFIG_LOG_LEVEL
#define NRFX_PPI_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_PPI_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_PPI_CONFIG_INFO_COLOR
-#define NRFX_PPI_CONFIG_INFO_COLOR 0
+/**
+ * @brief NRFX_PRS_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_PRS_ENABLED
+#define NRFX_PRS_ENABLED 0
#endif
-// NRFX_PPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_PPI_CONFIG_DEBUG_COLOR
-#define NRFX_PPI_CONFIG_DEBUG_COLOR 0
+/**
+ * @brief NRFX_PRS_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_PRS_CONFIG_LOG_ENABLED
+#define NRFX_PRS_CONFIG_LOG_ENABLED 0
#endif
-//
-
-//
-
-// NRFX_PRS_ENABLED - nrfx_prs - Peripheral Resource Sharing module
-//==========================================================
-#ifndef NRFX_PRS_ENABLED
-#define NRFX_PRS_ENABLED 0
+/**
+ * @brief NRFX_PRS_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_PRS_CONFIG_LOG_LEVEL
+#define NRFX_PRS_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_PRS_BOX_0_ENABLED - Enables box 0 in the module.
-
+/**
+ * @brief NRFX_PRS_BOX_0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PRS_BOX_0_ENABLED
#define NRFX_PRS_BOX_0_ENABLED 0
#endif
-// NRFX_PRS_BOX_1_ENABLED - Enables box 1 in the module.
-
-
+/**
+ * @brief NRFX_PRS_BOX_1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PRS_BOX_1_ENABLED
#define NRFX_PRS_BOX_1_ENABLED 0
#endif
-// NRFX_PRS_BOX_2_ENABLED - Enables box 2 in the module.
-
-
+/**
+ * @brief NRFX_PRS_BOX_2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PRS_BOX_2_ENABLED
#define NRFX_PRS_BOX_2_ENABLED 0
#endif
-// NRFX_PRS_BOX_3_ENABLED - Enables box 3 in the module.
-
-
+/**
+ * @brief NRFX_PRS_BOX_3_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PRS_BOX_3_ENABLED
#define NRFX_PRS_BOX_3_ENABLED 0
#endif
-// NRFX_PRS_BOX_4_ENABLED - Enables box 4 in the module.
-
-
+/**
+ * @brief NRFX_PRS_BOX_4_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PRS_BOX_4_ENABLED
#define NRFX_PRS_BOX_4_ENABLED 0
#endif
-// NRFX_PRS_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_PRS_CONFIG_LOG_ENABLED
-#define NRFX_PRS_CONFIG_LOG_ENABLED 0
+/**
+ * @brief NRFX_PWM_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_PWM_ENABLED
+#define NRFX_PWM_ENABLED 0
#endif
-// NRFX_PRS_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-#ifndef NRFX_PRS_CONFIG_LOG_LEVEL
-#define NRFX_PRS_CONFIG_LOG_LEVEL 3
+/**
+ * @brief NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_PRS_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_PRS_CONFIG_INFO_COLOR
-#define NRFX_PRS_CONFIG_INFO_COLOR 0
+/**
+ * @brief NRFX_PWM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_PWM_CONFIG_LOG_ENABLED
+#define NRFX_PWM_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_PRS_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_PRS_CONFIG_DEBUG_COLOR
-#define NRFX_PRS_CONFIG_DEBUG_COLOR 0
+/**
+ * @brief NRFX_PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED - Enables nRF52 Anomaly 109 workaround for PWM.
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED
+#define NRFX_PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED 0
#endif
-//
-
-//
-
-// NRFX_PWM_ENABLED - nrfx_pwm - PWM peripheral driver
-//==========================================================
-#ifndef NRFX_PWM_ENABLED
-#define NRFX_PWM_ENABLED 0
+/**
+ * @brief NRFX_PWM_NRF52_ANOMALY_109_EGU_INSTANCE - EGU instance used by the nRF52 Anomaly 109 workaround for PWM.
+ *
+ * Integer value.
+ * Supported values:
+ * - EGU0 = 0
+ * - EGU1 = 1
+ * - EGU2 = 2
+ * - EGU3 = 3
+ * - EGU4 = 4
+ * - EGU5 = 5
+ */
+#ifndef NRFX_PWM_NRF52_ANOMALY_109_EGU_INSTANCE
+#define NRFX_PWM_NRF52_ANOMALY_109_EGU_INSTANCE 5
#endif
-// NRFX_PWM0_ENABLED - Enable PWM0 instance
+/**
+ * @brief NRFX_PWM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_PWM_CONFIG_LOG_LEVEL
+#define NRFX_PWM_CONFIG_LOG_LEVEL 3
+#endif
+/**
+ * @brief NRFX_PWM0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PWM0_ENABLED
#define NRFX_PWM0_ENABLED 0
#endif
-// NRFX_PWM1_ENABLED - Enable PWM1 instance
-
+/**
+ * @brief NRFX_PWM1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PWM1_ENABLED
#define NRFX_PWM1_ENABLED 0
#endif
-// NRFX_PWM2_ENABLED - Enable PWM2 instance
-
+/**
+ * @brief NRFX_PWM2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PWM2_ENABLED
#define NRFX_PWM2_ENABLED 0
#endif
-// NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-// NRFX_PWM_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_PWM_CONFIG_LOG_ENABLED
-#define NRFX_PWM_CONFIG_LOG_ENABLED 0
-#endif
-// NRFX_PWM_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef NRFX_PWM_CONFIG_LOG_LEVEL
-#define NRFX_PWM_CONFIG_LOG_LEVEL 3
-#endif
-
-// NRFX_PWM_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_PWM_CONFIG_INFO_COLOR
-#define NRFX_PWM_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_PWM_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_PWM_CONFIG_DEBUG_COLOR
-#define NRFX_PWM_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-// NRFX_PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED - Enables nRF52 Anomaly 109 workaround for PWM.
-
-// The workaround uses interrupts to wake up the CPU and ensure
-// it is active when PWM is about to start a DMA transfer. For
-// initial transfer, done when a playback is started via PPI,
-// a specific EGU instance is used to generate the interrupt.
-// During the playback, the PWM interrupt triggered on SEQEND
-// event of a preceding sequence is used to protect the transfer
-// done for the next sequence to be played.
-//==========================================================
-#ifndef NRFX_PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED
-#define NRFX_PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED 0
-#endif
-// NRFX_PWM_NRF52_ANOMALY_109_EGU_INSTANCE - EGU instance used by the nRF52 Anomaly 109 workaround for PWM.
-
-// <0=> EGU0
-// <1=> EGU1
-// <2=> EGU2
-// <3=> EGU3
-// <4=> EGU4
-// <5=> EGU5
-
-#ifndef NRFX_PWM_NRF52_ANOMALY_109_EGU_INSTANCE
-#define NRFX_PWM_NRF52_ANOMALY_109_EGU_INSTANCE 5
-#endif
-
-//
-
-//
-
-// NRFX_QDEC_ENABLED - nrfx_qdec - QDEC peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_QDEC_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_QDEC_ENABLED
#define NRFX_QDEC_ENABLED 0
#endif
-// NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_QDEC_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_QDEC_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED
#define NRFX_QDEC_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_QDEC_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_QDEC_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL
#define NRFX_QDEC_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_QDEC_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_QDEC_CONFIG_INFO_COLOR
-#define NRFX_QDEC_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_QDEC_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_QDEC_CONFIG_DEBUG_COLOR
-#define NRFX_QDEC_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_RNG_ENABLED - nrfx_rng - RNG peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_RNG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_RNG_ENABLED
#define NRFX_RNG_ENABLED 0
#endif
-// NRFX_RNG_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_RNG_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_RNG_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_RNG_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_RNG_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_RNG_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_RNG_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_RNG_CONFIG_LOG_ENABLED
#define NRFX_RNG_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_RNG_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_RNG_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_RNG_CONFIG_LOG_LEVEL
#define NRFX_RNG_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_RNG_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_RNG_CONFIG_INFO_COLOR
-#define NRFX_RNG_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_RNG_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_RNG_CONFIG_DEBUG_COLOR
-#define NRFX_RNG_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_RTC_ENABLED - nrfx_rtc - RTC peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_RTC_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_RTC_ENABLED
#define NRFX_RTC_ENABLED 0
#endif
-// NRFX_RTC0_ENABLED - Enable RTC0 instance
-
-#ifndef NRFX_RTC0_ENABLED
-#define NRFX_RTC0_ENABLED 0
-#endif
-
-// NRFX_RTC1_ENABLED - Enable RTC1 instance
-
-#ifndef NRFX_RTC1_ENABLED
-#define NRFX_RTC1_ENABLED 0
-#endif
-
-// NRFX_RTC2_ENABLED - Enable RTC2 instance
-
-#ifndef NRFX_RTC2_ENABLED
-#define NRFX_RTC2_ENABLED 0
-#endif
-
-// NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
+/**
+ * @brief NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_RTC_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_RTC_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_RTC_CONFIG_LOG_ENABLED
#define NRFX_RTC_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_RTC_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_RTC_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_RTC_CONFIG_LOG_LEVEL
#define NRFX_RTC_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_RTC_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_RTC_CONFIG_INFO_COLOR
-#define NRFX_RTC_CONFIG_INFO_COLOR 0
+/**
+ * @brief NRFX_RTC0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_RTC0_ENABLED
+#define NRFX_RTC0_ENABLED 0
#endif
-// NRFX_RTC_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_RTC_CONFIG_DEBUG_COLOR
-#define NRFX_RTC_CONFIG_DEBUG_COLOR 0
+/**
+ * @brief NRFX_RTC1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_RTC1_ENABLED
+#define NRFX_RTC1_ENABLED 0
#endif
-//
-
-//
+/**
+ * @brief NRFX_RTC2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_RTC2_ENABLED
+#define NRFX_RTC2_ENABLED 0
+#endif
-// NRFX_SAADC_ENABLED - nrfx_saadc - SAADC peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_SAADC_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_SAADC_ENABLED
#define NRFX_SAADC_ENABLED 0
#endif
-// NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_SAADC_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_SAADC_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED
#define NRFX_SAADC_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_SAADC_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_SAADC_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL
#define NRFX_SAADC_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_SAADC_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_SAADC_CONFIG_INFO_COLOR
-#define NRFX_SAADC_CONFIG_INFO_COLOR 0
+/**
+ * @brief NRFX_SPI_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPI_ENABLED
+#define NRFX_SPI_ENABLED 0
#endif
-// NRFX_SAADC_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_SAADC_CONFIG_DEBUG_COLOR
-#define NRFX_SAADC_CONFIG_DEBUG_COLOR 0
+/**
+ * @brief NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-//
-
-//
-
-// NRFX_SPIM_ENABLED - nrfx_spim - SPIM peripheral driver
-//==========================================================
-#ifndef NRFX_SPIM_ENABLED
-#define NRFX_SPIM_ENABLED 0
+/**
+ * @brief NRFX_SPI_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPI_CONFIG_LOG_ENABLED
+#define NRFX_SPI_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_SPIM0_ENABLED - Enable SPIM0 instance
-
-#ifndef NRFX_SPIM0_ENABLED
-#define NRFX_SPIM0_ENABLED 0
+/**
+ * @brief NRFX_SPI_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_SPI_CONFIG_LOG_LEVEL
+#define NRFX_SPI_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_SPIM1_ENABLED - Enable SPIM1 instance
-
-
-#ifndef NRFX_SPIM1_ENABLED
-#define NRFX_SPIM1_ENABLED 0
+/**
+ * @brief NRFX_SPI0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPI0_ENABLED
+#define NRFX_SPI0_ENABLED 0
#endif
-// NRFX_SPIM2_ENABLED - Enable SPIM2 instance
-
-
-#ifndef NRFX_SPIM2_ENABLED
-#define NRFX_SPIM2_ENABLED 0
+/**
+ * @brief NRFX_SPI1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPI1_ENABLED
+#define NRFX_SPI1_ENABLED 0
#endif
-// NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
+/**
+ * @brief NRFX_SPI2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPI2_ENABLED
+#define NRFX_SPI2_ENABLED 0
+#endif
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
+/**
+ * @brief NRFX_SPIM_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIM_ENABLED
+#define NRFX_SPIM_ENABLED 0
+#endif
+/**
+ * @brief NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_SPIM_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_SPIM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED
#define NRFX_SPIM_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_SPIM_CONFIG_LOG_LEVEL - Default Severity level
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED - Enables nRF52 Anomaly 109 workaround for SPIM.
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED
+#define NRFX_SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED 0
+#endif
+/**
+ * @brief NRFX_SPIM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL
#define NRFX_SPIM_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_SPIM_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_SPIM_CONFIG_INFO_COLOR
-#define NRFX_SPIM_CONFIG_INFO_COLOR 0
+/**
+ * @brief NRFX_SPIM0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIM0_ENABLED
+#define NRFX_SPIM0_ENABLED 0
#endif
-// NRFX_SPIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_SPIM_CONFIG_DEBUG_COLOR
-#define NRFX_SPIM_CONFIG_DEBUG_COLOR 0
+/**
+ * @brief NRFX_SPIM1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIM1_ENABLED
+#define NRFX_SPIM1_ENABLED 0
#endif
-//
-
-// NRFX_SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED - Enables nRF52 anomaly 109 workaround for SPIM.
+/**
+ * @brief NRFX_SPIM2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIM2_ENABLED
+#define NRFX_SPIM2_ENABLED 0
+#endif
-
-// The workaround uses interrupts to wake up the CPU by catching
-// a start event of zero-length transmission to start the clock. This
-// ensures that the DMA transfer will be executed without issues and
-// that the proper transfer will be started. See more in the Errata
-// document or Anomaly 109 Addendum located at
-// https://infocenter.nordicsemi.com/
-
-#ifndef NRFX_SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED
-#define NRFX_SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED 0
-#endif
-
-//
-
-// NRFX_SPIS_ENABLED - nrfx_spis - SPIS peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_SPIS_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_SPIS_ENABLED
#define NRFX_SPIS_ENABLED 0
#endif
-// NRFX_SPIS0_ENABLED - Enable SPIS0 instance
-
-
-#ifndef NRFX_SPIS0_ENABLED
-#define NRFX_SPIS0_ENABLED 0
-#endif
-
-// NRFX_SPIS1_ENABLED - Enable SPIS1 instance
-
-
-#ifndef NRFX_SPIS1_ENABLED
-#define NRFX_SPIS1_ENABLED 0
-#endif
-
-// NRFX_SPIS2_ENABLED - Enable SPIS2 instance
-
-
-#ifndef NRFX_SPIS2_ENABLED
-#define NRFX_SPIS2_ENABLED 0
-#endif
-
-// NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
+/**
+ * @brief NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_SPIS_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_SPIS_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED
#define NRFX_SPIS_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_SPIS_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL
-#define NRFX_SPIS_CONFIG_LOG_LEVEL 3
-#endif
-
-// NRFX_SPIS_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_SPIS_CONFIG_INFO_COLOR
-#define NRFX_SPIS_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_SPIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_SPIS_CONFIG_DEBUG_COLOR
-#define NRFX_SPIS_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-// NRFX_SPIS_NRF52_ANOMALY_109_WORKAROUND_ENABLED - Enables nRF52 Anomaly 109 workaround for SPIS.
-
-
-// The workaround uses a GPIOTE channel to generate interrupts
-// on falling edges detected on the CSN line. This will make
-// the CPU active for the moment when SPIS starts DMA transfers,
-// and this way the transfers will be protected.
-// This workaround uses GPIOTE driver, so this driver must be
-// enabled as well.
+/**
+ * @brief NRFX_SPIS_NRF52_ANOMALY_109_WORKAROUND_ENABLED - Enables nRF52 Anomaly 109 workaround for SPIS.
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_SPIS_NRF52_ANOMALY_109_WORKAROUND_ENABLED
#define NRFX_SPIS_NRF52_ANOMALY_109_WORKAROUND_ENABLED 0
#endif
-//
-
-// NRFX_SPI_ENABLED - nrfx_spi - SPI peripheral driver
-//==========================================================
-#ifndef NRFX_SPI_ENABLED
-#define NRFX_SPI_ENABLED 0
+/**
+ * @brief NRFX_SPIS_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL
+#define NRFX_SPIS_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_SPI0_ENABLED - Enable SPI0 instance
-
-#ifndef NRFX_SPI0_ENABLED
-#define NRFX_SPI0_ENABLED 0
+/**
+ * @brief NRFX_SPIS0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIS0_ENABLED
+#define NRFX_SPIS0_ENABLED 0
#endif
-// NRFX_SPI1_ENABLED - Enable SPI1 instance
-
-
-#ifndef NRFX_SPI1_ENABLED
-#define NRFX_SPI1_ENABLED 0
+/**
+ * @brief NRFX_SPIS1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIS1_ENABLED
+#define NRFX_SPIS1_ENABLED 0
#endif
-// NRFX_SPI2_ENABLED - Enable SPI2 instance
-
-
-#ifndef NRFX_SPI2_ENABLED
-#define NRFX_SPI2_ENABLED 0
+/**
+ * @brief NRFX_SPIS2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIS2_ENABLED
+#define NRFX_SPIS2_ENABLED 0
#endif
-// NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY 7
+/**
+ * @brief NRFX_SYSTICK_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SYSTICK_ENABLED
+#define NRFX_SYSTICK_ENABLED 0
#endif
-// NRFX_SPI_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_SPI_CONFIG_LOG_ENABLED
-#define NRFX_SPI_CONFIG_LOG_ENABLED 0
+/**
+ * @brief NRFX_TEMP_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TEMP_ENABLED
+#define NRFX_TEMP_ENABLED 0
#endif
-// NRFX_SPI_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-#ifndef NRFX_SPI_CONFIG_LOG_LEVEL
-#define NRFX_SPI_CONFIG_LOG_LEVEL 3
+/**
+ * @brief NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_SPI_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_SPI_CONFIG_INFO_COLOR
-#define NRFX_SPI_CONFIG_INFO_COLOR 0
+/**
+ * @brief NRFX_TEMP_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TEMP_CONFIG_LOG_ENABLED
+#define NRFX_TEMP_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_SPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_SPI_CONFIG_DEBUG_COLOR
-#define NRFX_SPI_CONFIG_DEBUG_COLOR 0
+/**
+ * @brief NRFX_TEMP_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_TEMP_CONFIG_LOG_LEVEL
+#define NRFX_TEMP_CONFIG_LOG_LEVEL 3
#endif
-//
-
-//
-
-// NRFX_SYSTICK_ENABLED - nrfx_systick - ARM(R) SysTick driver
-
-
-#ifndef NRFX_SYSTICK_ENABLED
-#define NRFX_SYSTICK_ENABLED 0
+/**
+ * @brief NRFX_TIMER_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TIMER_ENABLED
+#define NRFX_TIMER_ENABLED 0
#endif
-// NRFX_TEMP_ENABLED - nrfx_temp - TEMP peripheral driver
-//==========================================================
-#ifndef NRFX_TEMP_ENABLED
-#define NRFX_TEMP_ENABLED 0
+/**
+ * @brief NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY 7
+/**
+ * @brief NRFX_TIMER_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED
+#define NRFX_TIMER_CONFIG_LOG_ENABLED 0
#endif
-//
-
-// NRFX_TIMER_ENABLED - nrfx_timer - TIMER periperal driver
-//==========================================================
-#ifndef NRFX_TIMER_ENABLED
-#define NRFX_TIMER_ENABLED 0
+/**
+ * @brief NRFX_TIMER_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL
+#define NRFX_TIMER_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_TIMER0_ENABLED - Enable TIMER0 instance
-
+/**
+ * @brief NRFX_TIMER0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_TIMER0_ENABLED
#define NRFX_TIMER0_ENABLED 0
#endif
-// NRFX_TIMER1_ENABLED - Enable TIMER1 instance
-
+/**
+ * @brief NRFX_TIMER1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_TIMER1_ENABLED
#define NRFX_TIMER1_ENABLED 0
#endif
-// NRFX_TIMER2_ENABLED - Enable TIMER2 instance
-
+/**
+ * @brief NRFX_TIMER2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_TIMER2_ENABLED
#define NRFX_TIMER2_ENABLED 0
#endif
-// NRFX_TIMER3_ENABLED - Enable TIMER3 instance
-
+/**
+ * @brief NRFX_TIMER3_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_TIMER3_ENABLED
#define NRFX_TIMER3_ENABLED 0
#endif
-// NRFX_TIMER4_ENABLED - Enable TIMER4 instance
-
+/**
+ * @brief NRFX_TIMER4_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_TIMER4_ENABLED
#define NRFX_TIMER4_ENABLED 0
#endif
-// NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 7
+/**
+ * @brief NRFX_TWI_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWI_ENABLED
+#define NRFX_TWI_ENABLED 0
#endif
-// NRFX_TIMER_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED
-#define NRFX_TIMER_CONFIG_LOG_ENABLED 0
+/**
+ * @brief NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_TIMER_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL
-#define NRFX_TIMER_CONFIG_LOG_LEVEL 3
+/**
+ * @brief NRFX_TWI_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWI_CONFIG_LOG_ENABLED
+#define NRFX_TWI_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_TIMER_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_TIMER_CONFIG_INFO_COLOR
-#define NRFX_TIMER_CONFIG_INFO_COLOR 0
+/**
+ * @brief NRFX_TWI_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_TWI_CONFIG_LOG_LEVEL
+#define NRFX_TWI_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_TIMER_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_TIMER_CONFIG_DEBUG_COLOR
-#define NRFX_TIMER_CONFIG_DEBUG_COLOR 0
+/**
+ * @brief NRFX_TWI0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWI0_ENABLED
+#define NRFX_TWI0_ENABLED 0
#endif
-//
-
-//
+/**
+ * @brief NRFX_TWI1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWI1_ENABLED
+#define NRFX_TWI1_ENABLED 0
+#endif
-// NRFX_TWIM_ENABLED - nrfx_twim - TWIM peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_TWIM_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_TWIM_ENABLED
#define NRFX_TWIM_ENABLED 0
#endif
-// NRFX_TWIM0_ENABLED - Enable TWIM0 instance
-
-#ifndef NRFX_TWIM0_ENABLED
-#define NRFX_TWIM0_ENABLED 0
-#endif
-
-// NRFX_TWIM1_ENABLED - Enable TWIM1 instance
-
-#ifndef NRFX_TWIM1_ENABLED
-#define NRFX_TWIM1_ENABLED 0
-#endif
-
-// NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_TWIM_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_TWIM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED
#define NRFX_TWIM_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_TWIM_CONFIG_LOG_LEVEL - Default Severity level
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED - Enables nRF52 Anomaly 109 workaround for TWIM.
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED
+#define NRFX_TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED 0
+#endif
+/**
+ * @brief NRFX_TWIM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL
#define NRFX_TWIM_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_TWIM_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_TWIM_CONFIG_INFO_COLOR
-#define NRFX_TWIM_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_TWIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_TWIM_CONFIG_DEBUG_COLOR
-#define NRFX_TWIM_CONFIG_DEBUG_COLOR 0
+/**
+ * @brief NRFX_TWIM0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWIM0_ENABLED
+#define NRFX_TWIM0_ENABLED 0
#endif
-//
-
-// NRFX_TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED - Enables nRF52 anomaly 109 workaround for TWIM.
-
-
-// The workaround uses interrupts to wake up the CPU by catching
-// the start event of zero-frequency transmission, clear the
-// peripheral, set desired frequency, start the peripheral, and
-// the proper transmission. See more in the Errata document or
-// Anomaly 109 Addendum located at https://infocenter.nordicsemi.com/
-
-#ifndef NRFX_TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED
-#define NRFX_TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED 0
+/**
+ * @brief NRFX_TWIM1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWIM1_ENABLED
+#define NRFX_TWIM1_ENABLED 0
#endif
-//
-
-// NRFX_TWIS_ENABLED - nrfx_twis - TWIS peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_TWIS_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_TWIS_ENABLED
#define NRFX_TWIS_ENABLED 0
#endif
-// NRFX_TWIS0_ENABLED - Enable TWIS0 instance
-
-#ifndef NRFX_TWIS0_ENABLED
-#define NRFX_TWIS0_ENABLED 0
+/**
+ * @brief NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_TWIS1_ENABLED - Enable TWIS1 instance
-
-#ifndef NRFX_TWIS1_ENABLED
-#define NRFX_TWIS1_ENABLED 0
+/**
+ * @brief NRFX_TWIS_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED
+#define NRFX_TWIS_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance would be initialized only once
-
-// Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code.
-
+/**
+ * @brief NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance would be initialized only once.
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY
#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
#endif
-// NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode
-
-// Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources.
-
+/**
+ * @brief NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode.
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_TWIS_NO_SYNC_MODE
#define NRFX_TWIS_NO_SYNC_MODE 0
#endif
-// NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-// NRFX_TWIS_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED
-#define NRFX_TWIS_CONFIG_LOG_ENABLED 0
-#endif
-// NRFX_TWIS_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
+/**
+ * @brief NRFX_TWIS_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL
#define NRFX_TWIS_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_TWIS_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_TWIS_CONFIG_INFO_COLOR
-#define NRFX_TWIS_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_TWIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_TWIS_CONFIG_DEBUG_COLOR
-#define NRFX_TWIS_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_TWI_ENABLED - nrfx_twi - TWI peripheral driver
-//==========================================================
-#ifndef NRFX_TWI_ENABLED
-#define NRFX_TWI_ENABLED 0
-#endif
-
-// NRFX_TWI0_ENABLED - Enable TWI0 instance
-
-#ifndef NRFX_TWI0_ENABLED
-#define NRFX_TWI0_ENABLED 0
+/**
+ * @brief NRFX_TWIS0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWIS0_ENABLED
+#define NRFX_TWIS0_ENABLED 0
#endif
-// NRFX_TWI1_ENABLED - Enable TWI1 instance
-
-#ifndef NRFX_TWI1_ENABLED
-#define NRFX_TWI1_ENABLED 0
+/**
+ * @brief NRFX_TWIS1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWIS1_ENABLED
+#define NRFX_TWIS1_ENABLED 0
#endif
-// NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY 7
+/**
+ * @brief NRFX_UART_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_UART_ENABLED
+#define NRFX_UART_ENABLED 0
#endif
-// NRFX_TWI_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_TWI_CONFIG_LOG_ENABLED
-#define NRFX_TWI_CONFIG_LOG_ENABLED 0
+/**
+ * @brief NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_TWI_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-#ifndef NRFX_TWI_CONFIG_LOG_LEVEL
-#define NRFX_TWI_CONFIG_LOG_LEVEL 3
+/**
+ * @brief NRFX_UART_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_UART_CONFIG_LOG_ENABLED
+#define NRFX_UART_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_TWI_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_TWI_CONFIG_INFO_COLOR
-#define NRFX_TWI_CONFIG_INFO_COLOR 0
+/**
+ * @brief NRFX_UART_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_UART_CONFIG_LOG_LEVEL
+#define NRFX_UART_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_TWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_TWI_CONFIG_DEBUG_COLOR
-#define NRFX_TWI_CONFIG_DEBUG_COLOR 0
+/**
+ * @brief NRFX_UART0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_UART0_ENABLED
+#define NRFX_UART0_ENABLED 0
#endif
-//
-
-//
-
-// NRFX_UARTE_ENABLED - nrfx_uarte - UARTE peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_UARTE_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_UARTE_ENABLED
#define NRFX_UARTE_ENABLED 0
#endif
-// NRFX_UARTE0_ENABLED - Enable UARTE0 instance
-
-#ifndef NRFX_UARTE0_ENABLED
-#define NRFX_UARTE0_ENABLED 0
-#endif
-
-// NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_UARTE_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_UARTE_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED
#define NRFX_UARTE_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_UARTE_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_UARTE_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL
#define NRFX_UARTE_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_UARTE_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_UARTE_CONFIG_INFO_COLOR
-#define NRFX_UARTE_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_UARTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_UARTE_CONFIG_DEBUG_COLOR
-#define NRFX_UARTE_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_UART_ENABLED - nrfx_uart - UART peripheral driver
-//==========================================================
-#ifndef NRFX_UART_ENABLED
-#define NRFX_UART_ENABLED 0
-#endif
-
-// NRFX_UART0_ENABLED - Enable UART0 instance
-
-#ifndef NRFX_UART0_ENABLED
-#define NRFX_UART0_ENABLED 0
-#endif
-
-// NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-// NRFX_UART_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_UART_CONFIG_LOG_ENABLED
-#define NRFX_UART_CONFIG_LOG_ENABLED 0
-#endif
-// NRFX_UART_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef NRFX_UART_CONFIG_LOG_LEVEL
-#define NRFX_UART_CONFIG_LOG_LEVEL 3
-#endif
-
-// NRFX_UART_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_UART_CONFIG_INFO_COLOR
-#define NRFX_UART_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_UART_CONFIG_DEBUG_COLOR
-#define NRFX_UART_CONFIG_DEBUG_COLOR 0
+/**
+ * @brief NRFX_UARTE0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_UARTE0_ENABLED
+#define NRFX_UARTE0_ENABLED 0
#endif
-//
-
-//
-
-// NRFX_WDT_ENABLED - nrfx_wdt - WDT peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_WDT_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_WDT_ENABLED
#define NRFX_WDT_ENABLED 0
#endif
-// NRFX_WDT0_ENABLED - Enable WDT0 instance
-
-#ifndef NRFX_WDT0_ENABLED
-#define NRFX_WDT0_ENABLED 0
+/**
+ * @brief NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver
-
-// <0=> Include WDT IRQ handling
-// <1=> Remove WDT IRQ handling
-
+/**
+ * @brief NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_WDT_CONFIG_NO_IRQ
#define NRFX_WDT_CONFIG_NO_IRQ 0
#endif
-// NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-// NRFX_WDT_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_WDT_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_WDT_CONFIG_LOG_ENABLED
#define NRFX_WDT_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_WDT_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_WDT_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_WDT_CONFIG_LOG_LEVEL
#define NRFX_WDT_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_WDT_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_WDT_CONFIG_INFO_COLOR
-#define NRFX_WDT_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_WDT_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_WDT_CONFIG_DEBUG_COLOR
-#define NRFX_WDT_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-//
-
#endif // NRFX_CONFIG_NRF52832_H__
diff --git a/mcu/nrf/common/vendor/templates/nrfx_config_nrf52833.h b/mcu/nrf/common/vendor/templates/nrfx_config_nrf52833.h
index 1b65157e..83c5d7b3 100644
--- a/mcu/nrf/common/vendor/templates/nrfx_config_nrf52833.h
+++ b/mcu/nrf/common/vendor/templates/nrfx_config_nrf52833.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA
+ * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -38,2276 +38,1625 @@
#error "This file should not be included directly. Include nrfx_config.h instead."
#endif
-// <<< Use Configuration Wizard in Context Menu >>>\n
-// nRF_Drivers
+/**
+ * @brief NRFX_DEFAULT_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_DEFAULT_IRQ_PRIORITY
+#define NRFX_DEFAULT_IRQ_PRIORITY 7
+#endif
-// NRFX_CLOCK_ENABLED - nrfx_clock - CLOCK peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_CLOCK_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_CLOCK_ENABLED
#define NRFX_CLOCK_ENABLED 0
#endif
-// NRFX_CLOCK_CONFIG_LF_SRC - LF Clock Source
-
-// <0=> RC
-// <1=> XTAL
-// <2=> Synth
-// <131073=> External Low Swing
-// <196609=> External Full Swing
+/**
+ * @brief NRFX_CLOCK_CONFIG_LF_SRC
+ *
+ * Integer value.
+ * Supported values:
+ * - RC = 0
+ * - XTAL = 1
+ * - Synth = 2
+ * - External Low Swing = 131073
+ * - External Full Swing = 196609
+ */
#ifndef NRFX_CLOCK_CONFIG_LF_SRC
#define NRFX_CLOCK_CONFIG_LF_SRC 1
#endif
-// NRFX_CLOCK_CONFIG_LF_CAL_ENABLED - Enables LF Clock Calibration Support
-
+/**
+ * @brief NRFX_CLOCK_CONFIG_LF_CAL_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_CLOCK_CONFIG_LF_CAL_ENABLED
#define NRFX_CLOCK_CONFIG_LF_CAL_ENABLED 0
#endif
-// NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED - Enables two-stage LFXO start procedure
-
-// If set to a non-zero value, LFRC will be started before LFXO and corresponding
-// event will be generated. It means that CPU will be woken up when LFRC
-// oscillator starts, but user callback will be invoked only after LFXO
-// finally starts.
+/**
+ * @brief NRFX_CLOCK_CONFIG_CT_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_CLOCK_CONFIG_CT_ENABLED
+#define NRFX_CLOCK_CONFIG_CT_ENABLED 1
+#endif
+/**
+ * @brief NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED
#define NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED 0
#endif
-// NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_CLOCK_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_CLOCK_CONFIG_LOG_ENABLED
#define NRFX_CLOCK_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_CLOCK_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_CLOCK_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_CLOCK_CONFIG_LOG_LEVEL
#define NRFX_CLOCK_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_CLOCK_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_CLOCK_CONFIG_INFO_COLOR
-#define NRFX_CLOCK_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_CLOCK_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_CLOCK_CONFIG_DEBUG_COLOR
-#define NRFX_CLOCK_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_COMP_ENABLED - nrfx_comp - COMP peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_COMP_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_COMP_ENABLED
#define NRFX_COMP_ENABLED 0
#endif
-// NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_COMP_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_COMP_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_COMP_CONFIG_LOG_ENABLED
#define NRFX_COMP_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_COMP_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_COMP_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_COMP_CONFIG_LOG_LEVEL
#define NRFX_COMP_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_COMP_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_COMP_CONFIG_INFO_COLOR
-#define NRFX_COMP_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_COMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_COMP_CONFIG_DEBUG_COLOR
-#define NRFX_COMP_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_EGU_ENABLED - nrfx_egu - EGU peripheral driver.
-//==========================================================
+/**
+ * @brief NRFX_EGU_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_EGU_ENABLED
#define NRFX_EGU_ENABLED 0
#endif
-// NRFX_EGU0_ENABLED - Enable EGU0 instance.
+/**
+ * @brief NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+/**
+ * @brief NRFX_EGU0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_EGU0_ENABLED
#define NRFX_EGU0_ENABLED 0
#endif
-// NRFX_EGU1_ENABLED - Enable EGU1 instance.
-
+/**
+ * @brief NRFX_EGU1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_EGU1_ENABLED
#define NRFX_EGU1_ENABLED 0
#endif
-// NRFX_EGU2_ENABLED - Enable EGU2 instance.
-
+/**
+ * @brief NRFX_EGU2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_EGU2_ENABLED
#define NRFX_EGU2_ENABLED 0
#endif
-// NRFX_EGU3_ENABLED - Enable EGU3 instance.
-
+/**
+ * @brief NRFX_EGU3_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_EGU3_ENABLED
#define NRFX_EGU3_ENABLED 0
#endif
-// NRFX_EGU4_ENABLED - Enable EGU4 instance.
-
+/**
+ * @brief NRFX_EGU4_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_EGU4_ENABLED
#define NRFX_EGU4_ENABLED 0
#endif
-// NRFX_EGU5_ENABLED - Enable EGU5 instance.
-
+/**
+ * @brief NRFX_EGU5_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_EGU5_ENABLED
#define NRFX_EGU5_ENABLED 0
#endif
-// NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority.
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-//
-
-// NRFX_GPIOTE_ENABLED - nrfx_gpiote - GPIOTE peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_GPIOTE_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_GPIOTE_ENABLED
#define NRFX_GPIOTE_ENABLED 0
#endif
-// NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins
-#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS
-#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1
-#endif
-
-// NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
+/**
+ * @brief NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS
+ *
+ * Integer value. Minimum: 0 Maximum: 15
+ */
+#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS
+#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 2
#endif
-// NRFX_GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_GPIOTE_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED
#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_GPIOTE_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_GPIOTE_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL
#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_GPIOTE_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_GPIOTE_CONFIG_INFO_COLOR
-#define NRFX_GPIOTE_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_GPIOTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_GPIOTE_CONFIG_DEBUG_COLOR
-#define NRFX_GPIOTE_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_I2S_ENABLED - nrfx_i2s - I2S peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_I2S_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_I2S_ENABLED
#define NRFX_I2S_ENABLED 0
#endif
-// NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_I2S_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_I2S_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_I2S_CONFIG_LOG_ENABLED
#define NRFX_I2S_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_I2S_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_I2S_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_I2S_CONFIG_LOG_LEVEL
#define NRFX_I2S_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_I2S_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_I2S_CONFIG_INFO_COLOR
-#define NRFX_I2S_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_I2S_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_I2S_CONFIG_DEBUG_COLOR
-#define NRFX_I2S_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_LPCOMP_ENABLED - nrfx_lpcomp - LPCOMP peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_LPCOMP_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_LPCOMP_ENABLED
#define NRFX_LPCOMP_ENABLED 0
#endif
-// NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_LPCOMP_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_LPCOMP_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED
#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_LPCOMP_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_LPCOMP_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL
#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_LPCOMP_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_LPCOMP_CONFIG_INFO_COLOR
-#define NRFX_LPCOMP_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_LPCOMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_LPCOMP_CONFIG_DEBUG_COLOR
-#define NRFX_LPCOMP_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_NFCT_ENABLED - nrfx_nfct - NFCT peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_NFCT_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_NFCT_ENABLED
#define NRFX_NFCT_ENABLED 0
#endif
-// NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
+/**
+ * @brief NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID - Timer instance used for workarounds in the driver.
-
-// <0=> 0
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-
+/**
+ * @brief NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID - Timer instance used for workarounds in the driver.
+ *
+ * Integer value. Minimum: 0 Maximum: 5
+ */
#ifndef NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID
#define NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID 4
#endif
-// NRFX_NFCT_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_NFCT_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_NFCT_CONFIG_LOG_ENABLED
#define NRFX_NFCT_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_NFCT_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_NFCT_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_NFCT_CONFIG_LOG_LEVEL
#define NRFX_NFCT_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_NFCT_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_NFCT_CONFIG_INFO_COLOR
-#define NRFX_NFCT_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_NFCT_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_NFCT_CONFIG_DEBUG_COLOR
-#define NRFX_NFCT_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_NVMC_ENABLED - nrfx_nvmc - NVMC peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_NVMC_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_NVMC_ENABLED
#define NRFX_NVMC_ENABLED 0
#endif
-//
-
-// NRFX_PDM_ENABLED - nrfx_pdm - PDM peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_PDM_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PDM_ENABLED
#define NRFX_PDM_ENABLED 0
#endif
-// NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_PDM_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_PDM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PDM_CONFIG_LOG_ENABLED
#define NRFX_PDM_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_PDM_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_PDM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_PDM_CONFIG_LOG_LEVEL
#define NRFX_PDM_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_PDM_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_PDM_CONFIG_INFO_COLOR
-#define NRFX_PDM_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_PDM_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_PDM_CONFIG_DEBUG_COLOR
-#define NRFX_PDM_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_POWER_ENABLED - nrfx_power - POWER peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_POWER_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_POWER_ENABLED
#define NRFX_POWER_ENABLED 0
#endif
-// NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
+/**
+ * @brief NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-//
-
-// NRFX_PPI_ENABLED - nrfx_ppi - PPI peripheral allocator
-//==========================================================
+/**
+ * @brief NRFX_PPI_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PPI_ENABLED
#define NRFX_PPI_ENABLED 0
#endif
-// NRFX_PPI_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+
+/**
+ * @brief NRFX_PPI_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PPI_CONFIG_LOG_ENABLED
#define NRFX_PPI_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_PPI_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_PPI_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_PPI_CONFIG_LOG_LEVEL
#define NRFX_PPI_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_PPI_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_PPI_CONFIG_INFO_COLOR
-#define NRFX_PPI_CONFIG_INFO_COLOR 0
+/**
+ * @brief NRFX_PRS_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_PRS_ENABLED
+#define NRFX_PRS_ENABLED 0
#endif
-// NRFX_PPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_PPI_CONFIG_DEBUG_COLOR
-#define NRFX_PPI_CONFIG_DEBUG_COLOR 0
+/**
+ * @brief NRFX_PRS_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_PRS_CONFIG_LOG_ENABLED
+#define NRFX_PRS_CONFIG_LOG_ENABLED 0
#endif
-//
-
-//
-
-// NRFX_PRS_ENABLED - nrfx_prs - Peripheral Resource Sharing module
-//==========================================================
-#ifndef NRFX_PRS_ENABLED
-#define NRFX_PRS_ENABLED 0
+/**
+ * @brief NRFX_PRS_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_PRS_CONFIG_LOG_LEVEL
+#define NRFX_PRS_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_PRS_BOX_0_ENABLED - Enables box 0 in the module.
-
+/**
+ * @brief NRFX_PRS_BOX_0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PRS_BOX_0_ENABLED
#define NRFX_PRS_BOX_0_ENABLED 0
#endif
-// NRFX_PRS_BOX_1_ENABLED - Enables box 1 in the module.
-
-
+/**
+ * @brief NRFX_PRS_BOX_1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PRS_BOX_1_ENABLED
#define NRFX_PRS_BOX_1_ENABLED 0
#endif
-// NRFX_PRS_BOX_2_ENABLED - Enables box 2 in the module.
-
-
+/**
+ * @brief NRFX_PRS_BOX_2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PRS_BOX_2_ENABLED
#define NRFX_PRS_BOX_2_ENABLED 0
#endif
-// NRFX_PRS_BOX_3_ENABLED - Enables box 3 in the module.
-
-
+/**
+ * @brief NRFX_PRS_BOX_3_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PRS_BOX_3_ENABLED
#define NRFX_PRS_BOX_3_ENABLED 0
#endif
-// NRFX_PRS_BOX_4_ENABLED - Enables box 4 in the module.
-
-
+/**
+ * @brief NRFX_PRS_BOX_4_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PRS_BOX_4_ENABLED
#define NRFX_PRS_BOX_4_ENABLED 0
#endif
-// NRFX_PRS_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_PRS_CONFIG_LOG_ENABLED
-#define NRFX_PRS_CONFIG_LOG_ENABLED 0
-#endif
-// NRFX_PRS_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef NRFX_PRS_CONFIG_LOG_LEVEL
-#define NRFX_PRS_CONFIG_LOG_LEVEL 3
+/**
+ * @brief NRFX_PWM_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_PWM_ENABLED
+#define NRFX_PWM_ENABLED 0
#endif
-// NRFX_PRS_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_PRS_CONFIG_INFO_COLOR
-#define NRFX_PRS_CONFIG_INFO_COLOR 0
+/**
+ * @brief NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_PRS_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_PRS_CONFIG_DEBUG_COLOR
-#define NRFX_PRS_CONFIG_DEBUG_COLOR 0
+/**
+ * @brief NRFX_PWM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_PWM_CONFIG_LOG_ENABLED
+#define NRFX_PWM_CONFIG_LOG_ENABLED 0
#endif
-//
-
-//
-
-// NRFX_PWM_ENABLED - nrfx_pwm - PWM peripheral driver
-//==========================================================
-#ifndef NRFX_PWM_ENABLED
-#define NRFX_PWM_ENABLED 0
+/**
+ * @brief NRFX_PWM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_PWM_CONFIG_LOG_LEVEL
+#define NRFX_PWM_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_PWM0_ENABLED - Enable PWM0 instance
-
+/**
+ * @brief NRFX_PWM0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PWM0_ENABLED
#define NRFX_PWM0_ENABLED 0
#endif
-// NRFX_PWM1_ENABLED - Enable PWM1 instance
-
+/**
+ * @brief NRFX_PWM1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PWM1_ENABLED
#define NRFX_PWM1_ENABLED 0
#endif
-// NRFX_PWM2_ENABLED - Enable PWM2 instance
-
+/**
+ * @brief NRFX_PWM2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PWM2_ENABLED
#define NRFX_PWM2_ENABLED 0
#endif
-// NRFX_PWM3_ENABLED - Enable PWM3 instance
-
+/**
+ * @brief NRFX_PWM3_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PWM3_ENABLED
#define NRFX_PWM3_ENABLED 0
#endif
-// NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-// NRFX_PWM_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_PWM_CONFIG_LOG_ENABLED
-#define NRFX_PWM_CONFIG_LOG_ENABLED 0
-#endif
-// NRFX_PWM_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef NRFX_PWM_CONFIG_LOG_LEVEL
-#define NRFX_PWM_CONFIG_LOG_LEVEL 3
-#endif
-
-// NRFX_PWM_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_PWM_CONFIG_INFO_COLOR
-#define NRFX_PWM_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_PWM_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_PWM_CONFIG_DEBUG_COLOR
-#define NRFX_PWM_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_QDEC_ENABLED - nrfx_qdec - QDEC peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_QDEC_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_QDEC_ENABLED
#define NRFX_QDEC_ENABLED 0
#endif
-// NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_QDEC_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_QDEC_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED
#define NRFX_QDEC_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_QDEC_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_QDEC_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL
#define NRFX_QDEC_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_QDEC_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_QDEC_CONFIG_INFO_COLOR
-#define NRFX_QDEC_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_QDEC_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_QDEC_CONFIG_DEBUG_COLOR
-#define NRFX_QDEC_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_RNG_ENABLED - nrfx_rng - RNG peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_RNG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_RNG_ENABLED
#define NRFX_RNG_ENABLED 0
#endif
-// NRFX_RNG_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_RNG_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_RNG_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_RNG_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_RNG_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_RNG_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_RNG_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_RNG_CONFIG_LOG_ENABLED
#define NRFX_RNG_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_RNG_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_RNG_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_RNG_CONFIG_LOG_LEVEL
#define NRFX_RNG_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_RNG_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_RNG_CONFIG_INFO_COLOR
-#define NRFX_RNG_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_RNG_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_RNG_CONFIG_DEBUG_COLOR
-#define NRFX_RNG_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_RTC_ENABLED - nrfx_rtc - RTC peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_RTC_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_RTC_ENABLED
#define NRFX_RTC_ENABLED 0
#endif
-// NRFX_RTC0_ENABLED - Enable RTC0 instance
-
-#ifndef NRFX_RTC0_ENABLED
-#define NRFX_RTC0_ENABLED 0
-#endif
-
-// NRFX_RTC1_ENABLED - Enable RTC1 instance
-
-#ifndef NRFX_RTC1_ENABLED
-#define NRFX_RTC1_ENABLED 0
-#endif
-
-// NRFX_RTC2_ENABLED - Enable RTC2 instance
-
-#ifndef NRFX_RTC2_ENABLED
-#define NRFX_RTC2_ENABLED 0
-#endif
-
-// NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
+/**
+ * @brief NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_RTC_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_RTC_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_RTC_CONFIG_LOG_ENABLED
#define NRFX_RTC_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_RTC_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_RTC_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_RTC_CONFIG_LOG_LEVEL
#define NRFX_RTC_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_RTC_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_RTC_CONFIG_INFO_COLOR
-#define NRFX_RTC_CONFIG_INFO_COLOR 0
+/**
+ * @brief NRFX_RTC0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_RTC0_ENABLED
+#define NRFX_RTC0_ENABLED 0
#endif
-// NRFX_RTC_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_RTC_CONFIG_DEBUG_COLOR
-#define NRFX_RTC_CONFIG_DEBUG_COLOR 0
+/**
+ * @brief NRFX_RTC1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_RTC1_ENABLED
+#define NRFX_RTC1_ENABLED 0
#endif
-//
-
-//
+/**
+ * @brief NRFX_RTC2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_RTC2_ENABLED
+#define NRFX_RTC2_ENABLED 0
+#endif
-// NRFX_SAADC_ENABLED - nrfx_saadc - SAADC peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_SAADC_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_SAADC_ENABLED
#define NRFX_SAADC_ENABLED 0
#endif
-// NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_SAADC_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_SAADC_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED
#define NRFX_SAADC_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_SAADC_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_SAADC_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL
#define NRFX_SAADC_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_SAADC_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_SAADC_CONFIG_INFO_COLOR
-#define NRFX_SAADC_CONFIG_INFO_COLOR 0
+/**
+ * @brief NRFX_SPI_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPI_ENABLED
+#define NRFX_SPI_ENABLED 0
#endif
-// NRFX_SAADC_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_SAADC_CONFIG_DEBUG_COLOR
-#define NRFX_SAADC_CONFIG_DEBUG_COLOR 0
+/**
+ * @brief NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-//
-
-//
-
-// NRFX_SPIM_ENABLED - nrfx_spim - SPIM peripheral driver
-//==========================================================
-#ifndef NRFX_SPIM_ENABLED
-#define NRFX_SPIM_ENABLED 0
+/**
+ * @brief NRFX_SPI_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPI_CONFIG_LOG_ENABLED
+#define NRFX_SPI_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_SPIM0_ENABLED - Enable SPIM0 instance
-
-#ifndef NRFX_SPIM0_ENABLED
-#define NRFX_SPIM0_ENABLED 0
+/**
+ * @brief NRFX_SPI_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_SPI_CONFIG_LOG_LEVEL
+#define NRFX_SPI_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_SPIM1_ENABLED - Enable SPIM1 instance
-
-
-#ifndef NRFX_SPIM1_ENABLED
-#define NRFX_SPIM1_ENABLED 0
+/**
+ * @brief NRFX_SPI0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPI0_ENABLED
+#define NRFX_SPI0_ENABLED 0
#endif
-// NRFX_SPIM2_ENABLED - Enable SPIM2 instance
-
-
-#ifndef NRFX_SPIM2_ENABLED
-#define NRFX_SPIM2_ENABLED 0
+/**
+ * @brief NRFX_SPI1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPI1_ENABLED
+#define NRFX_SPI1_ENABLED 0
#endif
-// NRFX_SPIM3_ENABLED - Enable SPIM3 instance
-
-
-#ifndef NRFX_SPIM3_ENABLED
-#define NRFX_SPIM3_ENABLED 0
+/**
+ * @brief NRFX_SPI2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPI2_ENABLED
+#define NRFX_SPI2_ENABLED 0
#endif
-// NRFX_SPIM_EXTENDED_ENABLED - Enable extended SPIM features
-
-
-#ifndef NRFX_SPIM_EXTENDED_ENABLED
-#define NRFX_SPIM_EXTENDED_ENABLED 0
+/**
+ * @brief NRFX_SPIM_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIM_ENABLED
+#define NRFX_SPIM_ENABLED 0
#endif
-// NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_SPIM_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_SPIM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED
#define NRFX_SPIM_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_SPIM_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_SPIM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL
#define NRFX_SPIM_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_SPIM_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_SPIM_CONFIG_INFO_COLOR
-#define NRFX_SPIM_CONFIG_INFO_COLOR 0
+/**
+ * @brief NRFX_SPIM0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIM0_ENABLED
+#define NRFX_SPIM0_ENABLED 0
#endif
-// NRFX_SPIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_SPIM_CONFIG_DEBUG_COLOR
-#define NRFX_SPIM_CONFIG_DEBUG_COLOR 0
+/**
+ * @brief NRFX_SPIM1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIM1_ENABLED
+#define NRFX_SPIM1_ENABLED 0
#endif
-//
+/**
+ * @brief NRFX_SPIM2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIM2_ENABLED
+#define NRFX_SPIM2_ENABLED 0
+#endif
-//
+/**
+ * @brief NRFX_SPIM3_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIM3_ENABLED
+#define NRFX_SPIM3_ENABLED 0
+#endif
-// NRFX_SPIS_ENABLED - nrfx_spis - SPIS peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_SPIS_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_SPIS_ENABLED
#define NRFX_SPIS_ENABLED 0
#endif
-// NRFX_SPIS0_ENABLED - Enable SPIS0 instance
-
-#ifndef NRFX_SPIS0_ENABLED
-#define NRFX_SPIS0_ENABLED 0
+/**
+ * @brief NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_SPIS1_ENABLED - Enable SPIS1 instance
-
-
-#ifndef NRFX_SPIS1_ENABLED
-#define NRFX_SPIS1_ENABLED 0
-#endif
-
-// NRFX_SPIS2_ENABLED - Enable SPIS2 instance
-
-
-#ifndef NRFX_SPIS2_ENABLED
-#define NRFX_SPIS2_ENABLED 0
-#endif
-
-// NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-// NRFX_SPIS_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_SPIS_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED
#define NRFX_SPIS_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_SPIS_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_SPIS_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL
#define NRFX_SPIS_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_SPIS_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_SPIS_CONFIG_INFO_COLOR
-#define NRFX_SPIS_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_SPIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_SPIS_CONFIG_DEBUG_COLOR
-#define NRFX_SPIS_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_SPI_ENABLED - nrfx_spi - SPI peripheral driver
-//==========================================================
-#ifndef NRFX_SPI_ENABLED
-#define NRFX_SPI_ENABLED 0
-#endif
-// NRFX_SPI0_ENABLED - Enable SPI0 instance
-
-
-#ifndef NRFX_SPI0_ENABLED
-#define NRFX_SPI0_ENABLED 0
+/**
+ * @brief NRFX_SPIS0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIS0_ENABLED
+#define NRFX_SPIS0_ENABLED 0
#endif
-// NRFX_SPI1_ENABLED - Enable SPI1 instance
-
-
-#ifndef NRFX_SPI1_ENABLED
-#define NRFX_SPI1_ENABLED 0
+/**
+ * @brief NRFX_SPIS1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIS1_ENABLED
+#define NRFX_SPIS1_ENABLED 0
#endif
-// NRFX_SPI2_ENABLED - Enable SPI2 instance
-
-
-#ifndef NRFX_SPI2_ENABLED
-#define NRFX_SPI2_ENABLED 0
+/**
+ * @brief NRFX_SPIS2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIS2_ENABLED
+#define NRFX_SPIS2_ENABLED 0
#endif
-// NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY 7
+/**
+ * @brief NRFX_SYSTICK_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SYSTICK_ENABLED
+#define NRFX_SYSTICK_ENABLED 0
#endif
-// NRFX_SPI_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_SPI_CONFIG_LOG_ENABLED
-#define NRFX_SPI_CONFIG_LOG_ENABLED 0
+/**
+ * @brief NRFX_TEMP_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TEMP_ENABLED
+#define NRFX_TEMP_ENABLED 0
#endif
-// NRFX_SPI_CONFIG_LOG_LEVEL - Default Severity level
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef NRFX_SPI_CONFIG_LOG_LEVEL
-#define NRFX_SPI_CONFIG_LOG_LEVEL 3
+/**
+ * @brief NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_SPI_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_SPI_CONFIG_INFO_COLOR
-#define NRFX_SPI_CONFIG_INFO_COLOR 0
+/**
+ * @brief NRFX_TEMP_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TEMP_CONFIG_LOG_ENABLED
+#define NRFX_TEMP_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_SPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_SPI_CONFIG_DEBUG_COLOR
-#define NRFX_SPI_CONFIG_DEBUG_COLOR 0
+/**
+ * @brief NRFX_TEMP_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_TEMP_CONFIG_LOG_LEVEL
+#define NRFX_TEMP_CONFIG_LOG_LEVEL 3
#endif
-//
-
-//
-
-// NRFX_SYSTICK_ENABLED - nrfx_systick - ARM(R) SysTick driver
-
-
-#ifndef NRFX_SYSTICK_ENABLED
-#define NRFX_SYSTICK_ENABLED 0
+/**
+ * @brief NRFX_TIMER_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TIMER_ENABLED
+#define NRFX_TIMER_ENABLED 0
#endif
-// NRFX_TEMP_ENABLED - nrfx_temp - TEMP peripheral driver
-//==========================================================
-#ifndef NRFX_TEMP_ENABLED
-#define NRFX_TEMP_ENABLED 0
+/**
+ * @brief NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY 7
+/**
+ * @brief NRFX_TIMER_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED
+#define NRFX_TIMER_CONFIG_LOG_ENABLED 0
#endif
-//
-
-// NRFX_TIMER_ENABLED - nrfx_timer - TIMER periperal driver
-//==========================================================
-#ifndef NRFX_TIMER_ENABLED
-#define NRFX_TIMER_ENABLED 0
+/**
+ * @brief NRFX_TIMER_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL
+#define NRFX_TIMER_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_TIMER0_ENABLED - Enable TIMER0 instance
-
+/**
+ * @brief NRFX_TIMER0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_TIMER0_ENABLED
#define NRFX_TIMER0_ENABLED 0
#endif
-// NRFX_TIMER1_ENABLED - Enable TIMER1 instance
-
+/**
+ * @brief NRFX_TIMER1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_TIMER1_ENABLED
#define NRFX_TIMER1_ENABLED 0
#endif
-// NRFX_TIMER2_ENABLED - Enable TIMER2 instance
-
+/**
+ * @brief NRFX_TIMER2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_TIMER2_ENABLED
#define NRFX_TIMER2_ENABLED 0
#endif
-// NRFX_TIMER3_ENABLED - Enable TIMER3 instance
-
+/**
+ * @brief NRFX_TIMER3_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_TIMER3_ENABLED
#define NRFX_TIMER3_ENABLED 0
#endif
-// NRFX_TIMER4_ENABLED - Enable TIMER4 instance
-
+/**
+ * @brief NRFX_TIMER4_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_TIMER4_ENABLED
#define NRFX_TIMER4_ENABLED 0
#endif
-// NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 7
+/**
+ * @brief NRFX_TWI_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWI_ENABLED
+#define NRFX_TWI_ENABLED 0
#endif
-// NRFX_TIMER_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED
-#define NRFX_TIMER_CONFIG_LOG_ENABLED 0
+/**
+ * @brief NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_TIMER_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL
-#define NRFX_TIMER_CONFIG_LOG_LEVEL 3
+/**
+ * @brief NRFX_TWI_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWI_CONFIG_LOG_ENABLED
+#define NRFX_TWI_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_TIMER_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_TIMER_CONFIG_INFO_COLOR
-#define NRFX_TIMER_CONFIG_INFO_COLOR 0
+/**
+ * @brief NRFX_TWI_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_TWI_CONFIG_LOG_LEVEL
+#define NRFX_TWI_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_TIMER_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_TIMER_CONFIG_DEBUG_COLOR
-#define NRFX_TIMER_CONFIG_DEBUG_COLOR 0
+/**
+ * @brief NRFX_TWI0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWI0_ENABLED
+#define NRFX_TWI0_ENABLED 0
#endif
-//
-
-//
+/**
+ * @brief NRFX_TWI1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWI1_ENABLED
+#define NRFX_TWI1_ENABLED 0
+#endif
-// NRFX_TWIM_ENABLED - nrfx_twim - TWIM peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_TWIM_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_TWIM_ENABLED
#define NRFX_TWIM_ENABLED 0
#endif
-// NRFX_TWIM0_ENABLED - Enable TWIM0 instance
-
-#ifndef NRFX_TWIM0_ENABLED
-#define NRFX_TWIM0_ENABLED 0
-#endif
-
-// NRFX_TWIM1_ENABLED - Enable TWIM1 instance
-
-#ifndef NRFX_TWIM1_ENABLED
-#define NRFX_TWIM1_ENABLED 0
-#endif
-
-// NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_TWIM_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_TWIM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED
#define NRFX_TWIM_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_TWIM_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_TWIM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL
#define NRFX_TWIM_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_TWIM_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_TWIM_CONFIG_INFO_COLOR
-#define NRFX_TWIM_CONFIG_INFO_COLOR 0
+/**
+ * @brief NRFX_TWIM0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWIM0_ENABLED
+#define NRFX_TWIM0_ENABLED 0
#endif
-// NRFX_TWIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_TWIM_CONFIG_DEBUG_COLOR
-#define NRFX_TWIM_CONFIG_DEBUG_COLOR 0
+/**
+ * @brief NRFX_TWIM1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWIM1_ENABLED
+#define NRFX_TWIM1_ENABLED 0
#endif
-//
-
-//
-
-// NRFX_TWIS_ENABLED - nrfx_twis - TWIS peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_TWIS_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_TWIS_ENABLED
#define NRFX_TWIS_ENABLED 0
#endif
-// NRFX_TWIS0_ENABLED - Enable TWIS0 instance
-
-#ifndef NRFX_TWIS0_ENABLED
-#define NRFX_TWIS0_ENABLED 0
+/**
+ * @brief NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_TWIS1_ENABLED - Enable TWIS1 instance
-
-#ifndef NRFX_TWIS1_ENABLED
-#define NRFX_TWIS1_ENABLED 0
+/**
+ * @brief NRFX_TWIS_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED
+#define NRFX_TWIS_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance would be initialized only once
-
-// Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code.
-
+/**
+ * @brief NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance would be initialized only once.
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY
#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
#endif
-// NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode
-
-// Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources.
-
+/**
+ * @brief NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode.
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_TWIS_NO_SYNC_MODE
#define NRFX_TWIS_NO_SYNC_MODE 0
#endif
-// NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-// NRFX_TWIS_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED
-#define NRFX_TWIS_CONFIG_LOG_ENABLED 0
-#endif
-// NRFX_TWIS_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
+/**
+ * @brief NRFX_TWIS_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL
#define NRFX_TWIS_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_TWIS_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_TWIS_CONFIG_INFO_COLOR
-#define NRFX_TWIS_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_TWIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_TWIS_CONFIG_DEBUG_COLOR
-#define NRFX_TWIS_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_TWI_ENABLED - nrfx_twi - TWI peripheral driver
-//==========================================================
-#ifndef NRFX_TWI_ENABLED
-#define NRFX_TWI_ENABLED 0
-#endif
-
-// NRFX_TWI0_ENABLED - Enable TWI0 instance
-
-#ifndef NRFX_TWI0_ENABLED
-#define NRFX_TWI0_ENABLED 0
+/**
+ * @brief NRFX_TWIS0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWIS0_ENABLED
+#define NRFX_TWIS0_ENABLED 0
#endif
-// NRFX_TWI1_ENABLED - Enable TWI1 instance
-
-#ifndef NRFX_TWI1_ENABLED
-#define NRFX_TWI1_ENABLED 0
+/**
+ * @brief NRFX_TWIS1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWIS1_ENABLED
+#define NRFX_TWIS1_ENABLED 0
#endif
-// NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY 7
+/**
+ * @brief NRFX_UART_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_UART_ENABLED
+#define NRFX_UART_ENABLED 0
#endif
-// NRFX_TWI_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_TWI_CONFIG_LOG_ENABLED
-#define NRFX_TWI_CONFIG_LOG_ENABLED 0
+/**
+ * @brief NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_TWI_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-#ifndef NRFX_TWI_CONFIG_LOG_LEVEL
-#define NRFX_TWI_CONFIG_LOG_LEVEL 3
+/**
+ * @brief NRFX_UART_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_UART_CONFIG_LOG_ENABLED
+#define NRFX_UART_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_TWI_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_TWI_CONFIG_INFO_COLOR
-#define NRFX_TWI_CONFIG_INFO_COLOR 0
+/**
+ * @brief NRFX_UART_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_UART_CONFIG_LOG_LEVEL
+#define NRFX_UART_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_TWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_TWI_CONFIG_DEBUG_COLOR
-#define NRFX_TWI_CONFIG_DEBUG_COLOR 0
+/**
+ * @brief NRFX_UART0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_UART0_ENABLED
+#define NRFX_UART0_ENABLED 0
#endif
-//
-
-//
-
-// NRFX_UARTE_ENABLED - nrfx_uarte - UARTE peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_UARTE_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_UARTE_ENABLED
#define NRFX_UARTE_ENABLED 0
#endif
-// NRFX_UARTE0_ENABLED - Enable UARTE0 instance
-
-#ifndef NRFX_UARTE0_ENABLED
-#define NRFX_UARTE0_ENABLED 0
-#endif
-
-// NRFX_UARTE1_ENABLED - Enable UARTE1 instance
-
-#ifndef NRFX_UARTE1_ENABLED
-#define NRFX_UARTE1_ENABLED 0
-#endif
-
-// NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_UARTE_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_UARTE_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED
#define NRFX_UARTE_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_UARTE_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_UARTE_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL
#define NRFX_UARTE_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_UARTE_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_UARTE_CONFIG_INFO_COLOR
-#define NRFX_UARTE_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_UARTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_UARTE_CONFIG_DEBUG_COLOR
-#define NRFX_UARTE_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_UART_ENABLED - nrfx_uart - UART peripheral driver
-//==========================================================
-#ifndef NRFX_UART_ENABLED
-#define NRFX_UART_ENABLED 0
-#endif
-
-// NRFX_UART0_ENABLED - Enable UART0 instance
-
-#ifndef NRFX_UART0_ENABLED
-#define NRFX_UART0_ENABLED 0
-#endif
-
-// NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-// NRFX_UART_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_UART_CONFIG_LOG_ENABLED
-#define NRFX_UART_CONFIG_LOG_ENABLED 0
-#endif
-// NRFX_UART_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef NRFX_UART_CONFIG_LOG_LEVEL
-#define NRFX_UART_CONFIG_LOG_LEVEL 3
-#endif
-
-// NRFX_UART_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_UART_CONFIG_INFO_COLOR
-#define NRFX_UART_CONFIG_INFO_COLOR 0
+/**
+ * @brief NRFX_UARTE0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_UARTE0_ENABLED
+#define NRFX_UARTE0_ENABLED 0
#endif
-// NRFX_UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_UART_CONFIG_DEBUG_COLOR
-#define NRFX_UART_CONFIG_DEBUG_COLOR 0
+/**
+ * @brief NRFX_UARTE1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_UARTE1_ENABLED
+#define NRFX_UARTE1_ENABLED 0
#endif
-//
-
-//
-
-// NRFX_USBD_ENABLED - nrfx_usbd - USBD peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_USBD_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_USBD_ENABLED
#define NRFX_USBD_ENABLED 0
#endif
-// NRFX_USBD_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
+/**
+ * @brief NRFX_USBD_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_USBD_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_USBD_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_USBD_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// USBD_CONFIG_DMASCHEDULER_ISO_BOOST - Give priority to isochronous transfers
-
-// This option gives priority to isochronous transfers.
-// Enabling it assures that isochronous transfers are always processed,
-// even if multiple other transfers are pending.
-// Isochronous endpoints are prioritized before the usbd_dma_scheduler_algorithm
-// function is called, so the option is independent of the algorithm chosen.
-
+/**
+ * @brief NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST - Give priority to isochronous transfers
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST
#define NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST 1
#endif
-// USBD_CONFIG_ISO_IN_ZLP - Respond to an IN token on ISO IN endpoint with ZLP when no data is ready
-
-
-// If set, ISO IN endpoint will respond to an IN token with ZLP when no data is ready to be sent.
-// Else, there will be no response.
-
+/**
+ * @brief NRFX_USBD_CONFIG_ISO_IN_ZLP - Respond to an IN token on ISO IN endpoint with ZLP when no data is ready.
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_USBD_CONFIG_ISO_IN_ZLP
#define NRFX_USBD_CONFIG_ISO_IN_ZLP 0
#endif
-// NRFX_USBD_CONFIG_LOG_ENABLED - Enable logging in the module
-//==========================================================
+/**
+ * @brief NRFX_USBD_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_USBD_CONFIG_LOG_ENABLED
#define NRFX_USBD_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_USBD_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_USBD_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_USBD_CONFIG_LOG_LEVEL
#define NRFX_USBD_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_USBD_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_USBD_CONFIG_INFO_COLOR
-#define NRFX_USBD_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_USBD_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_USBD_CONFIG_DEBUG_COLOR
-#define NRFX_USBD_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_WDT_ENABLED - nrfx_wdt - WDT peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_WDT_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_WDT_ENABLED
#define NRFX_WDT_ENABLED 0
#endif
-// NRFX_WDT0_ENABLED - Enable WDT0 instance
-
-#ifndef NRFX_WDT0_ENABLED
-#define NRFX_WDT0_ENABLED 0
+/**
+ * @brief NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver
-
-// <0=> Include WDT IRQ handling
-// <1=> Remove WDT IRQ handling
-
+/**
+ * @brief NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_WDT_CONFIG_NO_IRQ
#define NRFX_WDT_CONFIG_NO_IRQ 0
#endif
-// NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-// NRFX_WDT_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_WDT_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_WDT_CONFIG_LOG_ENABLED
#define NRFX_WDT_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_WDT_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_WDT_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_WDT_CONFIG_LOG_LEVEL
#define NRFX_WDT_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_WDT_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_WDT_CONFIG_INFO_COLOR
-#define NRFX_WDT_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_WDT_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_WDT_CONFIG_DEBUG_COLOR
-#define NRFX_WDT_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-//
-
#endif // NRFX_CONFIG_NRF52833_H__
diff --git a/mcu/nrf/common/vendor/templates/nrfx_config_nrf52840.h b/mcu/nrf/common/vendor/templates/nrfx_config_nrf52840.h
index 682aead8..09c06af5 100644
--- a/mcu/nrf/common/vendor/templates/nrfx_config_nrf52840.h
+++ b/mcu/nrf/common/vendor/templates/nrfx_config_nrf52840.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA
+ * Copyright (c) 2017 - 2023, Nordic Semiconductor ASA
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -38,2309 +38,1652 @@
#error "This file should not be included directly. Include nrfx_config.h instead."
#endif
-// <<< Use Configuration Wizard in Context Menu >>>\n
-// nRF_Drivers
+/**
+ * @brief NRFX_DEFAULT_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_DEFAULT_IRQ_PRIORITY
+#define NRFX_DEFAULT_IRQ_PRIORITY 7
+#endif
-// NRFX_CLOCK_ENABLED - nrfx_clock - CLOCK peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_CLOCK_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_CLOCK_ENABLED
#define NRFX_CLOCK_ENABLED 0
#endif
-// NRFX_CLOCK_CONFIG_LF_SRC - LF Clock Source
-
-// <0=> RC
-// <1=> XTAL
-// <2=> Synth
-// <131073=> External Low Swing
-// <196609=> External Full Swing
+/**
+ * @brief NRFX_CLOCK_CONFIG_LF_SRC
+ *
+ * Integer value.
+ * Supported values:
+ * - RC = 0
+ * - XTAL = 1
+ * - Synth = 2
+ * - External Low Swing = 131073
+ * - External Full Swing = 196609
+ */
#ifndef NRFX_CLOCK_CONFIG_LF_SRC
#define NRFX_CLOCK_CONFIG_LF_SRC 1
#endif
-// NRFX_CLOCK_CONFIG_LF_CAL_ENABLED - Enables LF Clock Calibration Support
-
+/**
+ * @brief NRFX_CLOCK_CONFIG_LF_CAL_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_CLOCK_CONFIG_LF_CAL_ENABLED
#define NRFX_CLOCK_CONFIG_LF_CAL_ENABLED 0
#endif
-// NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED - Enables two-stage LFXO start procedure
-
-// If set to a non-zero value, LFRC will be started before LFXO and corresponding
-// event will be generated. It means that CPU will be woken up when LFRC
-// oscillator starts, but user callback will be invoked only after LFXO
-// finally starts.
+/**
+ * @brief NRFX_CLOCK_CONFIG_CT_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_CLOCK_CONFIG_CT_ENABLED
+#define NRFX_CLOCK_CONFIG_CT_ENABLED 1
+#endif
+/**
+ * @brief NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED
#define NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED 0
#endif
-// NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_CLOCK_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_CLOCK_CONFIG_LOG_ENABLED
#define NRFX_CLOCK_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_CLOCK_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_CLOCK_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_CLOCK_CONFIG_LOG_LEVEL
#define NRFX_CLOCK_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_CLOCK_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_CLOCK_CONFIG_INFO_COLOR
-#define NRFX_CLOCK_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_CLOCK_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_CLOCK_CONFIG_DEBUG_COLOR
-#define NRFX_CLOCK_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_COMP_ENABLED - nrfx_comp - COMP peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_COMP_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_COMP_ENABLED
#define NRFX_COMP_ENABLED 0
#endif
-// NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_COMP_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_COMP_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_COMP_CONFIG_LOG_ENABLED
#define NRFX_COMP_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_COMP_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_COMP_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_COMP_CONFIG_LOG_LEVEL
#define NRFX_COMP_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_COMP_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_COMP_CONFIG_INFO_COLOR
-#define NRFX_COMP_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_COMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_COMP_CONFIG_DEBUG_COLOR
-#define NRFX_COMP_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_EGU_ENABLED - nrfx_egu - EGU peripheral driver.
-//==========================================================
+/**
+ * @brief NRFX_EGU_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_EGU_ENABLED
#define NRFX_EGU_ENABLED 0
#endif
-// NRFX_EGU0_ENABLED - Enable EGU0 instance.
+/**
+ * @brief NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+/**
+ * @brief NRFX_EGU0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_EGU0_ENABLED
#define NRFX_EGU0_ENABLED 0
#endif
-// NRFX_EGU1_ENABLED - Enable EGU1 instance.
-
+/**
+ * @brief NRFX_EGU1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_EGU1_ENABLED
#define NRFX_EGU1_ENABLED 0
#endif
-// NRFX_EGU2_ENABLED - Enable EGU2 instance.
-
+/**
+ * @brief NRFX_EGU2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_EGU2_ENABLED
#define NRFX_EGU2_ENABLED 0
#endif
-// NRFX_EGU3_ENABLED - Enable EGU3 instance.
-
+/**
+ * @brief NRFX_EGU3_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_EGU3_ENABLED
#define NRFX_EGU3_ENABLED 0
#endif
-// NRFX_EGU4_ENABLED - Enable EGU4 instance.
-
+/**
+ * @brief NRFX_EGU4_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_EGU4_ENABLED
#define NRFX_EGU4_ENABLED 0
#endif
-// NRFX_EGU5_ENABLED - Enable EGU5 instance.
-
+/**
+ * @brief NRFX_EGU5_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_EGU5_ENABLED
#define NRFX_EGU5_ENABLED 0
#endif
-// NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority.
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-//
-
-// NRFX_GPIOTE_ENABLED - nrfx_gpiote - GPIOTE peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_GPIOTE_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_GPIOTE_ENABLED
#define NRFX_GPIOTE_ENABLED 0
#endif
-// NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins
-#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS
-#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1
-#endif
-
-// NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
+/**
+ * @brief NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS
+ *
+ * Integer value. Minimum: 0 Maximum: 15
+ */
+#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS
+#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 2
#endif
-// NRFX_GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_GPIOTE_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED
#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_GPIOTE_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_GPIOTE_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL
#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_GPIOTE_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_GPIOTE_CONFIG_INFO_COLOR
-#define NRFX_GPIOTE_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_GPIOTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_GPIOTE_CONFIG_DEBUG_COLOR
-#define NRFX_GPIOTE_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_I2S_ENABLED - nrfx_i2s - I2S peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_I2S_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_I2S_ENABLED
#define NRFX_I2S_ENABLED 0
#endif
-// NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_I2S_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_I2S_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_I2S_CONFIG_LOG_ENABLED
#define NRFX_I2S_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_I2S_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_I2S_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_I2S_CONFIG_LOG_LEVEL
#define NRFX_I2S_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_I2S_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_I2S_CONFIG_INFO_COLOR
-#define NRFX_I2S_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_I2S_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_I2S_CONFIG_DEBUG_COLOR
-#define NRFX_I2S_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_LPCOMP_ENABLED - nrfx_lpcomp - LPCOMP peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_LPCOMP_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_LPCOMP_ENABLED
#define NRFX_LPCOMP_ENABLED 0
#endif
-// NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_LPCOMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_LPCOMP_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_LPCOMP_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED
#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_LPCOMP_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_LPCOMP_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL
#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_LPCOMP_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_LPCOMP_CONFIG_INFO_COLOR
-#define NRFX_LPCOMP_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_LPCOMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_LPCOMP_CONFIG_DEBUG_COLOR
-#define NRFX_LPCOMP_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_NFCT_ENABLED - nrfx_nfct - NFCT peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_NFCT_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_NFCT_ENABLED
#define NRFX_NFCT_ENABLED 0
#endif
-// NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
+/**
+ * @brief NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID - Timer instance used for workarounds in the driver.
-
-// <0=> 0
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-
+/**
+ * @brief NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID - Timer instance used for workarounds in the driver.
+ *
+ * Integer value. Minimum: 0 Maximum: 5
+ */
#ifndef NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID
#define NRFX_NFCT_CONFIG_TIMER_INSTANCE_ID 4
#endif
-// NRFX_NFCT_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_NFCT_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_NFCT_CONFIG_LOG_ENABLED
#define NRFX_NFCT_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_NFCT_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_NFCT_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_NFCT_CONFIG_LOG_LEVEL
#define NRFX_NFCT_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_NFCT_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_NFCT_CONFIG_INFO_COLOR
-#define NRFX_NFCT_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_NFCT_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_NFCT_CONFIG_DEBUG_COLOR
-#define NRFX_NFCT_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_NVMC_ENABLED - nrfx_nvmc - NVMC peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_NVMC_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_NVMC_ENABLED
#define NRFX_NVMC_ENABLED 0
#endif
-//
-
-// NRFX_PDM_ENABLED - nrfx_pdm - PDM peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_PDM_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PDM_ENABLED
#define NRFX_PDM_ENABLED 0
#endif
-// NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_PDM_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_PDM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PDM_CONFIG_LOG_ENABLED
#define NRFX_PDM_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_PDM_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_PDM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_PDM_CONFIG_LOG_LEVEL
#define NRFX_PDM_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_PDM_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_PDM_CONFIG_INFO_COLOR
-#define NRFX_PDM_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_PDM_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_PDM_CONFIG_DEBUG_COLOR
-#define NRFX_PDM_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_POWER_ENABLED - nrfx_power - POWER peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_POWER_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_POWER_ENABLED
#define NRFX_POWER_ENABLED 0
#endif
-// NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
+/**
+ * @brief NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-//
-
-// NRFX_PPI_ENABLED - nrfx_ppi - PPI peripheral allocator
-//==========================================================
+/**
+ * @brief NRFX_PPI_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PPI_ENABLED
#define NRFX_PPI_ENABLED 0
#endif
-// NRFX_PPI_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+
+/**
+ * @brief NRFX_PPI_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PPI_CONFIG_LOG_ENABLED
#define NRFX_PPI_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_PPI_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_PPI_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_PPI_CONFIG_LOG_LEVEL
#define NRFX_PPI_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_PPI_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_PPI_CONFIG_INFO_COLOR
-#define NRFX_PPI_CONFIG_INFO_COLOR 0
+/**
+ * @brief NRFX_PRS_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_PRS_ENABLED
+#define NRFX_PRS_ENABLED 0
#endif
-// NRFX_PPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_PPI_CONFIG_DEBUG_COLOR
-#define NRFX_PPI_CONFIG_DEBUG_COLOR 0
+/**
+ * @brief NRFX_PRS_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_PRS_CONFIG_LOG_ENABLED
+#define NRFX_PRS_CONFIG_LOG_ENABLED 0
#endif
-//
-
-//
-
-// NRFX_PRS_ENABLED - nrfx_prs - Peripheral Resource Sharing module
-//==========================================================
-#ifndef NRFX_PRS_ENABLED
-#define NRFX_PRS_ENABLED 0
+/**
+ * @brief NRFX_PRS_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_PRS_CONFIG_LOG_LEVEL
+#define NRFX_PRS_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_PRS_BOX_0_ENABLED - Enables box 0 in the module.
-
+/**
+ * @brief NRFX_PRS_BOX_0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PRS_BOX_0_ENABLED
#define NRFX_PRS_BOX_0_ENABLED 0
#endif
-// NRFX_PRS_BOX_1_ENABLED - Enables box 1 in the module.
-
-
+/**
+ * @brief NRFX_PRS_BOX_1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PRS_BOX_1_ENABLED
#define NRFX_PRS_BOX_1_ENABLED 0
#endif
-// NRFX_PRS_BOX_2_ENABLED - Enables box 2 in the module.
-
-
+/**
+ * @brief NRFX_PRS_BOX_2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PRS_BOX_2_ENABLED
#define NRFX_PRS_BOX_2_ENABLED 0
#endif
-// NRFX_PRS_BOX_3_ENABLED - Enables box 3 in the module.
-
-
+/**
+ * @brief NRFX_PRS_BOX_3_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PRS_BOX_3_ENABLED
#define NRFX_PRS_BOX_3_ENABLED 0
#endif
-// NRFX_PRS_BOX_4_ENABLED - Enables box 4 in the module.
-
-
+/**
+ * @brief NRFX_PRS_BOX_4_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PRS_BOX_4_ENABLED
#define NRFX_PRS_BOX_4_ENABLED 0
#endif
-// NRFX_PRS_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_PRS_CONFIG_LOG_ENABLED
-#define NRFX_PRS_CONFIG_LOG_ENABLED 0
-#endif
-// NRFX_PRS_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef NRFX_PRS_CONFIG_LOG_LEVEL
-#define NRFX_PRS_CONFIG_LOG_LEVEL 3
+/**
+ * @brief NRFX_PWM_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_PWM_ENABLED
+#define NRFX_PWM_ENABLED 0
#endif
-// NRFX_PRS_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_PRS_CONFIG_INFO_COLOR
-#define NRFX_PRS_CONFIG_INFO_COLOR 0
+/**
+ * @brief NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_PRS_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_PRS_CONFIG_DEBUG_COLOR
-#define NRFX_PRS_CONFIG_DEBUG_COLOR 0
+/**
+ * @brief NRFX_PWM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_PWM_CONFIG_LOG_ENABLED
+#define NRFX_PWM_CONFIG_LOG_ENABLED 0
#endif
-//
-
-//
-
-// NRFX_PWM_ENABLED - nrfx_pwm - PWM peripheral driver
-//==========================================================
-#ifndef NRFX_PWM_ENABLED
-#define NRFX_PWM_ENABLED 0
+/**
+ * @brief NRFX_PWM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_PWM_CONFIG_LOG_LEVEL
+#define NRFX_PWM_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_PWM0_ENABLED - Enable PWM0 instance
-
+/**
+ * @brief NRFX_PWM0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PWM0_ENABLED
#define NRFX_PWM0_ENABLED 0
#endif
-// NRFX_PWM1_ENABLED - Enable PWM1 instance
-
+/**
+ * @brief NRFX_PWM1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PWM1_ENABLED
#define NRFX_PWM1_ENABLED 0
#endif
-// NRFX_PWM2_ENABLED - Enable PWM2 instance
-
+/**
+ * @brief NRFX_PWM2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PWM2_ENABLED
#define NRFX_PWM2_ENABLED 0
#endif
-// NRFX_PWM3_ENABLED - Enable PWM3 instance
-
+/**
+ * @brief NRFX_PWM3_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_PWM3_ENABLED
#define NRFX_PWM3_ENABLED 0
#endif
-// NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-// NRFX_PWM_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_PWM_CONFIG_LOG_ENABLED
-#define NRFX_PWM_CONFIG_LOG_ENABLED 0
-#endif
-// NRFX_PWM_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef NRFX_PWM_CONFIG_LOG_LEVEL
-#define NRFX_PWM_CONFIG_LOG_LEVEL 3
-#endif
-
-// NRFX_PWM_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_PWM_CONFIG_INFO_COLOR
-#define NRFX_PWM_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_PWM_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_PWM_CONFIG_DEBUG_COLOR
-#define NRFX_PWM_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_QDEC_ENABLED - nrfx_qdec - QDEC peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_QDEC_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_QDEC_ENABLED
#define NRFX_QDEC_ENABLED 0
#endif
-// NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_QDEC_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_QDEC_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED
#define NRFX_QDEC_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_QDEC_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_QDEC_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL
#define NRFX_QDEC_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_QDEC_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_QDEC_CONFIG_INFO_COLOR
-#define NRFX_QDEC_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_QDEC_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_QDEC_CONFIG_DEBUG_COLOR
-#define NRFX_QDEC_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_QSPI_ENABLED - nrfx_qspi - QSPI peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_QSPI_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_QSPI_ENABLED
#define NRFX_QSPI_ENABLED 0
#endif
-// NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-//
-
-// NRFX_RNG_ENABLED - nrfx_rng - RNG peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_RNG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_RNG_ENABLED
#define NRFX_RNG_ENABLED 0
#endif
-// NRFX_RNG_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_RNG_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_RNG_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_RNG_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_RNG_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_RNG_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_RNG_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_RNG_CONFIG_LOG_ENABLED
#define NRFX_RNG_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_RNG_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_RNG_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_RNG_CONFIG_LOG_LEVEL
#define NRFX_RNG_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_RNG_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_RNG_CONFIG_INFO_COLOR
-#define NRFX_RNG_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_RNG_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_RNG_CONFIG_DEBUG_COLOR
-#define NRFX_RNG_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_RTC_ENABLED - nrfx_rtc - RTC peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_RTC_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_RTC_ENABLED
#define NRFX_RTC_ENABLED 0
#endif
-// NRFX_RTC0_ENABLED - Enable RTC0 instance
-
-#ifndef NRFX_RTC0_ENABLED
-#define NRFX_RTC0_ENABLED 0
-#endif
-
-// NRFX_RTC1_ENABLED - Enable RTC1 instance
-
-#ifndef NRFX_RTC1_ENABLED
-#define NRFX_RTC1_ENABLED 0
-#endif
-
-// NRFX_RTC2_ENABLED - Enable RTC2 instance
-
-#ifndef NRFX_RTC2_ENABLED
-#define NRFX_RTC2_ENABLED 0
-#endif
-
-// NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
+/**
+ * @brief NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_RTC_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_RTC_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_RTC_CONFIG_LOG_ENABLED
#define NRFX_RTC_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_RTC_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_RTC_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_RTC_CONFIG_LOG_LEVEL
#define NRFX_RTC_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_RTC_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_RTC_CONFIG_INFO_COLOR
-#define NRFX_RTC_CONFIG_INFO_COLOR 0
+/**
+ * @brief NRFX_RTC0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_RTC0_ENABLED
+#define NRFX_RTC0_ENABLED 0
#endif
-// NRFX_RTC_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_RTC_CONFIG_DEBUG_COLOR
-#define NRFX_RTC_CONFIG_DEBUG_COLOR 0
+/**
+ * @brief NRFX_RTC1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_RTC1_ENABLED
+#define NRFX_RTC1_ENABLED 0
#endif
-//
-
-//
+/**
+ * @brief NRFX_RTC2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_RTC2_ENABLED
+#define NRFX_RTC2_ENABLED 0
+#endif
-// NRFX_SAADC_ENABLED - nrfx_saadc - SAADC peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_SAADC_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_SAADC_ENABLED
#define NRFX_SAADC_ENABLED 0
#endif
-// NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_SAADC_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_SAADC_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED
#define NRFX_SAADC_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_SAADC_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_SAADC_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL
#define NRFX_SAADC_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_SAADC_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
+/**
+ * @brief NRFX_SPI_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPI_ENABLED
+#define NRFX_SPI_ENABLED 0
+#endif
-#ifndef NRFX_SAADC_CONFIG_INFO_COLOR
-#define NRFX_SAADC_CONFIG_INFO_COLOR 0
+/**
+ * @brief NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_SAADC_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
+/**
+ * @brief NRFX_SPI_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPI_CONFIG_LOG_ENABLED
+#define NRFX_SPI_CONFIG_LOG_ENABLED 0
+#endif
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
+/**
+ * @brief NRFX_SPI_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_SPI_CONFIG_LOG_LEVEL
+#define NRFX_SPI_CONFIG_LOG_LEVEL 3
+#endif
-#ifndef NRFX_SAADC_CONFIG_DEBUG_COLOR
-#define NRFX_SAADC_CONFIG_DEBUG_COLOR 0
+/**
+ * @brief NRFX_SPI0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPI0_ENABLED
+#define NRFX_SPI0_ENABLED 0
#endif
-//
+/**
+ * @brief NRFX_SPI1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPI1_ENABLED
+#define NRFX_SPI1_ENABLED 0
+#endif
-//
+/**
+ * @brief NRFX_SPI2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPI2_ENABLED
+#define NRFX_SPI2_ENABLED 0
+#endif
-// NRFX_SPIM_ENABLED - nrfx_spim - SPIM peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_SPIM_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_SPIM_ENABLED
#define NRFX_SPIM_ENABLED 0
#endif
-// NRFX_SPIM0_ENABLED - Enable SPIM0 instance
+/**
+ * @brief NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
-#ifndef NRFX_SPIM0_ENABLED
-#define NRFX_SPIM0_ENABLED 0
+/**
+ * @brief NRFX_SPIM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED
+#define NRFX_SPIM_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL
+#define NRFX_SPIM_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_SPIM1_ENABLED - Enable SPIM1 instance
+/**
+ * @brief NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED
+#define NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED 0
+#endif
+/**
+ * @brief NRFX_SPIM0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIM0_ENABLED
+#define NRFX_SPIM0_ENABLED 0
+#endif
+/**
+ * @brief NRFX_SPIM1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_SPIM1_ENABLED
#define NRFX_SPIM1_ENABLED 0
#endif
-// NRFX_SPIM2_ENABLED - Enable SPIM2 instance
-
-
+/**
+ * @brief NRFX_SPIM2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_SPIM2_ENABLED
#define NRFX_SPIM2_ENABLED 0
#endif
-// NRFX_SPIM3_ENABLED - Enable SPIM3 instance
-
-
+/**
+ * @brief NRFX_SPIM3_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_SPIM3_ENABLED
#define NRFX_SPIM3_ENABLED 0
#endif
-// NRFX_SPIM_EXTENDED_ENABLED - Enable extended SPIM features
-
-
-#ifndef NRFX_SPIM_EXTENDED_ENABLED
-#define NRFX_SPIM_EXTENDED_ENABLED 0
+/**
+ * @brief NRFX_SPIS_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIS_ENABLED
+#define NRFX_SPIS_ENABLED 0
#endif
-// NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
+/**
+ * @brief NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
-#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY 7
+/**
+ * @brief NRFX_SPIS_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED
+#define NRFX_SPIS_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_SPIM_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED
-#define NRFX_SPIM_CONFIG_LOG_ENABLED 0
-#endif
-// NRFX_SPIM_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL
-#define NRFX_SPIM_CONFIG_LOG_LEVEL 3
-#endif
-
-// NRFX_SPIM_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_SPIM_CONFIG_INFO_COLOR
-#define NRFX_SPIM_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_SPIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_SPIM_CONFIG_DEBUG_COLOR
-#define NRFX_SPIM_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-// NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED - Enables nRF52840 anomaly 198 workaround for SPIM3.
-
-
-// See more in the Errata document located at
-// https://infocenter.nordicsemi.com/
-
-#ifndef NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED
-#define NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED 0
-#endif
-
-//
-
-// NRFX_SPIS_ENABLED - nrfx_spis - SPIS peripheral driver
-//==========================================================
-#ifndef NRFX_SPIS_ENABLED
-#define NRFX_SPIS_ENABLED 0
+/**
+ * @brief NRFX_SPIS_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL
+#define NRFX_SPIS_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_SPIS0_ENABLED - Enable SPIS0 instance
-
+/**
+ * @brief NRFX_SPIS0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_SPIS0_ENABLED
#define NRFX_SPIS0_ENABLED 0
#endif
-// NRFX_SPIS1_ENABLED - Enable SPIS1 instance
-
-
+/**
+ * @brief NRFX_SPIS1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_SPIS1_ENABLED
#define NRFX_SPIS1_ENABLED 0
#endif
-// NRFX_SPIS2_ENABLED - Enable SPIS2 instance
-
-
+/**
+ * @brief NRFX_SPIS2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_SPIS2_ENABLED
#define NRFX_SPIS2_ENABLED 0
#endif
-// NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-// NRFX_SPIS_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED
-#define NRFX_SPIS_CONFIG_LOG_ENABLED 0
-#endif
-// NRFX_SPIS_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL
-#define NRFX_SPIS_CONFIG_LOG_LEVEL 3
-#endif
-
-// NRFX_SPIS_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_SPIS_CONFIG_INFO_COLOR
-#define NRFX_SPIS_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_SPIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_SPIS_CONFIG_DEBUG_COLOR
-#define NRFX_SPIS_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_SPI_ENABLED - nrfx_spi - SPI peripheral driver
-//==========================================================
-#ifndef NRFX_SPI_ENABLED
-#define NRFX_SPI_ENABLED 0
-#endif
-// NRFX_SPI0_ENABLED - Enable SPI0 instance
-
-
-#ifndef NRFX_SPI0_ENABLED
-#define NRFX_SPI0_ENABLED 0
-#endif
-
-// NRFX_SPI1_ENABLED - Enable SPI1 instance
-
-
-#ifndef NRFX_SPI1_ENABLED
-#define NRFX_SPI1_ENABLED 0
-#endif
-
-// NRFX_SPI2_ENABLED - Enable SPI2 instance
-
-
-#ifndef NRFX_SPI2_ENABLED
-#define NRFX_SPI2_ENABLED 0
-#endif
-
-// NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY 7
+/**
+ * @brief NRFX_SYSTICK_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SYSTICK_ENABLED
+#define NRFX_SYSTICK_ENABLED 0
#endif
-// NRFX_SPI_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_SPI_CONFIG_LOG_ENABLED
-#define NRFX_SPI_CONFIG_LOG_ENABLED 0
+/**
+ * @brief NRFX_TEMP_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TEMP_ENABLED
+#define NRFX_TEMP_ENABLED 0
#endif
-// NRFX_SPI_CONFIG_LOG_LEVEL - Default Severity level
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef NRFX_SPI_CONFIG_LOG_LEVEL
-#define NRFX_SPI_CONFIG_LOG_LEVEL 3
+/**
+ * @brief NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_SPI_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_SPI_CONFIG_INFO_COLOR
-#define NRFX_SPI_CONFIG_INFO_COLOR 0
+/**
+ * @brief NRFX_TEMP_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TEMP_CONFIG_LOG_ENABLED
+#define NRFX_TEMP_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_SPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_SPI_CONFIG_DEBUG_COLOR
-#define NRFX_SPI_CONFIG_DEBUG_COLOR 0
+/**
+ * @brief NRFX_TEMP_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_TEMP_CONFIG_LOG_LEVEL
+#define NRFX_TEMP_CONFIG_LOG_LEVEL 3
#endif
-//
-
-//
-
-// NRFX_SYSTICK_ENABLED - nrfx_systick - ARM(R) SysTick driver
-
-
-#ifndef NRFX_SYSTICK_ENABLED
-#define NRFX_SYSTICK_ENABLED 0
+/**
+ * @brief NRFX_TIMER_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TIMER_ENABLED
+#define NRFX_TIMER_ENABLED 0
#endif
-// NRFX_TEMP_ENABLED - nrfx_temp - TEMP peripheral driver
-//==========================================================
-#ifndef NRFX_TEMP_ENABLED
-#define NRFX_TEMP_ENABLED 0
+/**
+ * @brief NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY 7
+/**
+ * @brief NRFX_TIMER_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED
+#define NRFX_TIMER_CONFIG_LOG_ENABLED 0
#endif
-//
-
-// NRFX_TIMER_ENABLED - nrfx_timer - TIMER periperal driver
-//==========================================================
-#ifndef NRFX_TIMER_ENABLED
-#define NRFX_TIMER_ENABLED 0
+/**
+ * @brief NRFX_TIMER_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL
+#define NRFX_TIMER_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_TIMER0_ENABLED - Enable TIMER0 instance
-
+/**
+ * @brief NRFX_TIMER0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_TIMER0_ENABLED
#define NRFX_TIMER0_ENABLED 0
#endif
-// NRFX_TIMER1_ENABLED - Enable TIMER1 instance
-
+/**
+ * @brief NRFX_TIMER1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_TIMER1_ENABLED
#define NRFX_TIMER1_ENABLED 0
#endif
-// NRFX_TIMER2_ENABLED - Enable TIMER2 instance
-
+/**
+ * @brief NRFX_TIMER2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_TIMER2_ENABLED
#define NRFX_TIMER2_ENABLED 0
#endif
-// NRFX_TIMER3_ENABLED - Enable TIMER3 instance
-
+/**
+ * @brief NRFX_TIMER3_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_TIMER3_ENABLED
#define NRFX_TIMER3_ENABLED 0
#endif
-// NRFX_TIMER4_ENABLED - Enable TIMER4 instance
-
+/**
+ * @brief NRFX_TIMER4_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_TIMER4_ENABLED
#define NRFX_TIMER4_ENABLED 0
#endif
-// NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 7
+/**
+ * @brief NRFX_TWI_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWI_ENABLED
+#define NRFX_TWI_ENABLED 0
#endif
-// NRFX_TIMER_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED
-#define NRFX_TIMER_CONFIG_LOG_ENABLED 0
+/**
+ * @brief NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_TIMER_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL
-#define NRFX_TIMER_CONFIG_LOG_LEVEL 3
+/**
+ * @brief NRFX_TWI_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWI_CONFIG_LOG_ENABLED
+#define NRFX_TWI_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_TIMER_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_TIMER_CONFIG_INFO_COLOR
-#define NRFX_TIMER_CONFIG_INFO_COLOR 0
+/**
+ * @brief NRFX_TWI_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_TWI_CONFIG_LOG_LEVEL
+#define NRFX_TWI_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_TIMER_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_TIMER_CONFIG_DEBUG_COLOR
-#define NRFX_TIMER_CONFIG_DEBUG_COLOR 0
+/**
+ * @brief NRFX_TWI0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWI0_ENABLED
+#define NRFX_TWI0_ENABLED 0
#endif
-//
-
-//
+/**
+ * @brief NRFX_TWI1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWI1_ENABLED
+#define NRFX_TWI1_ENABLED 0
+#endif
-// NRFX_TWIM_ENABLED - nrfx_twim - TWIM peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_TWIM_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_TWIM_ENABLED
#define NRFX_TWIM_ENABLED 0
#endif
-// NRFX_TWIM0_ENABLED - Enable TWIM0 instance
-
-#ifndef NRFX_TWIM0_ENABLED
-#define NRFX_TWIM0_ENABLED 0
-#endif
-
-// NRFX_TWIM1_ENABLED - Enable TWIM1 instance
-
-#ifndef NRFX_TWIM1_ENABLED
-#define NRFX_TWIM1_ENABLED 0
-#endif
-
-// NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_TWIM_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_TWIM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED
#define NRFX_TWIM_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_TWIM_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_TWIM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL
#define NRFX_TWIM_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_TWIM_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_TWIM_CONFIG_INFO_COLOR
-#define NRFX_TWIM_CONFIG_INFO_COLOR 0
+/**
+ * @brief NRFX_TWIM0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWIM0_ENABLED
+#define NRFX_TWIM0_ENABLED 0
#endif
-// NRFX_TWIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_TWIM_CONFIG_DEBUG_COLOR
-#define NRFX_TWIM_CONFIG_DEBUG_COLOR 0
+/**
+ * @brief NRFX_TWIM1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWIM1_ENABLED
+#define NRFX_TWIM1_ENABLED 0
#endif
-//
-
-//
-
-// NRFX_TWIS_ENABLED - nrfx_twis - TWIS peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_TWIS_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_TWIS_ENABLED
#define NRFX_TWIS_ENABLED 0
#endif
-// NRFX_TWIS0_ENABLED - Enable TWIS0 instance
-
-#ifndef NRFX_TWIS0_ENABLED
-#define NRFX_TWIS0_ENABLED 0
+/**
+ * @brief NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_TWIS1_ENABLED - Enable TWIS1 instance
-
-#ifndef NRFX_TWIS1_ENABLED
-#define NRFX_TWIS1_ENABLED 0
+/**
+ * @brief NRFX_TWIS_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED
+#define NRFX_TWIS_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance would be initialized only once
-
-// Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code.
-
+/**
+ * @brief NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance would be initialized only once.
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY
#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
#endif
-// NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode
-
-// Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources.
-
+/**
+ * @brief NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode.
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_TWIS_NO_SYNC_MODE
#define NRFX_TWIS_NO_SYNC_MODE 0
#endif
-// NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-// NRFX_TWIS_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED
-#define NRFX_TWIS_CONFIG_LOG_ENABLED 0
-#endif
-// NRFX_TWIS_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
+/**
+ * @brief NRFX_TWIS_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL
#define NRFX_TWIS_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_TWIS_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_TWIS_CONFIG_INFO_COLOR
-#define NRFX_TWIS_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_TWIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_TWIS_CONFIG_DEBUG_COLOR
-#define NRFX_TWIS_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_TWI_ENABLED - nrfx_twi - TWI peripheral driver
-//==========================================================
-#ifndef NRFX_TWI_ENABLED
-#define NRFX_TWI_ENABLED 0
-#endif
-
-// NRFX_TWI0_ENABLED - Enable TWI0 instance
-
-#ifndef NRFX_TWI0_ENABLED
-#define NRFX_TWI0_ENABLED 0
+/**
+ * @brief NRFX_TWIS0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWIS0_ENABLED
+#define NRFX_TWIS0_ENABLED 0
#endif
-// NRFX_TWI1_ENABLED - Enable TWI1 instance
-
-#ifndef NRFX_TWI1_ENABLED
-#define NRFX_TWI1_ENABLED 0
+/**
+ * @brief NRFX_TWIS1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWIS1_ENABLED
+#define NRFX_TWIS1_ENABLED 0
#endif
-// NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY 7
+/**
+ * @brief NRFX_UART_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_UART_ENABLED
+#define NRFX_UART_ENABLED 0
#endif
-// NRFX_TWI_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_TWI_CONFIG_LOG_ENABLED
-#define NRFX_TWI_CONFIG_LOG_ENABLED 0
+/**
+ * @brief NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_TWI_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-#ifndef NRFX_TWI_CONFIG_LOG_LEVEL
-#define NRFX_TWI_CONFIG_LOG_LEVEL 3
+/**
+ * @brief NRFX_UART_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_UART_CONFIG_LOG_ENABLED
+#define NRFX_UART_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_TWI_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_TWI_CONFIG_INFO_COLOR
-#define NRFX_TWI_CONFIG_INFO_COLOR 0
+/**
+ * @brief NRFX_UART_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_UART_CONFIG_LOG_LEVEL
+#define NRFX_UART_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_TWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_TWI_CONFIG_DEBUG_COLOR
-#define NRFX_TWI_CONFIG_DEBUG_COLOR 0
+/**
+ * @brief NRFX_UART0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_UART0_ENABLED
+#define NRFX_UART0_ENABLED 0
#endif
-//
-
-//
-
-// NRFX_UARTE_ENABLED - nrfx_uarte - UARTE peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_UARTE_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_UARTE_ENABLED
#define NRFX_UARTE_ENABLED 0
#endif
-// NRFX_UARTE0_ENABLED - Enable UARTE0 instance
-
-#ifndef NRFX_UARTE0_ENABLED
-#define NRFX_UARTE0_ENABLED 0
-#endif
-
-// NRFX_UARTE1_ENABLED - Enable UARTE1 instance
-
-#ifndef NRFX_UARTE1_ENABLED
-#define NRFX_UARTE1_ENABLED 0
-#endif
-
-// NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
+/**
+ * @brief NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_UARTE_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_UARTE_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED
#define NRFX_UARTE_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_UARTE_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_UARTE_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL
#define NRFX_UARTE_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_UARTE_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_UARTE_CONFIG_INFO_COLOR
-#define NRFX_UARTE_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_UARTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_UARTE_CONFIG_DEBUG_COLOR
-#define NRFX_UARTE_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_UART_ENABLED - nrfx_uart - UART peripheral driver
-//==========================================================
-#ifndef NRFX_UART_ENABLED
-#define NRFX_UART_ENABLED 0
-#endif
-
-// NRFX_UART0_ENABLED - Enable UART0 instance
-
-#ifndef NRFX_UART0_ENABLED
-#define NRFX_UART0_ENABLED 0
-#endif
-
-// NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-// NRFX_UART_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_UART_CONFIG_LOG_ENABLED
-#define NRFX_UART_CONFIG_LOG_ENABLED 0
-#endif
-// NRFX_UART_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef NRFX_UART_CONFIG_LOG_LEVEL
-#define NRFX_UART_CONFIG_LOG_LEVEL 3
-#endif
-
-// NRFX_UART_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_UART_CONFIG_INFO_COLOR
-#define NRFX_UART_CONFIG_INFO_COLOR 0
+/**
+ * @brief NRFX_UARTE0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_UARTE0_ENABLED
+#define NRFX_UARTE0_ENABLED 0
#endif
-// NRFX_UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_UART_CONFIG_DEBUG_COLOR
-#define NRFX_UART_CONFIG_DEBUG_COLOR 0
+/**
+ * @brief NRFX_UARTE1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_UARTE1_ENABLED
+#define NRFX_UARTE1_ENABLED 0
#endif
-//
-
-//
-
-// NRFX_USBD_ENABLED - nrfx_usbd - USBD peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_USBD_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_USBD_ENABLED
#define NRFX_USBD_ENABLED 0
#endif
-// NRFX_USBD_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
+/**
+ * @brief NRFX_USBD_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
#ifndef NRFX_USBD_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_USBD_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_USBD_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// USBD_CONFIG_DMASCHEDULER_ISO_BOOST - Give priority to isochronous transfers
-
-// This option gives priority to isochronous transfers.
-// Enabling it assures that isochronous transfers are always processed,
-// even if multiple other transfers are pending.
-// Isochronous endpoints are prioritized before the usbd_dma_scheduler_algorithm
-// function is called, so the option is independent of the algorithm chosen.
-
+/**
+ * @brief NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST - Give priority to isochronous transfers
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST
#define NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST 1
#endif
-// USBD_CONFIG_ISO_IN_ZLP - Respond to an IN token on ISO IN endpoint with ZLP when no data is ready
-
-
-// If set, ISO IN endpoint will respond to an IN token with ZLP when no data is ready to be sent.
-// Else, there will be no response.
-
+/**
+ * @brief NRFX_USBD_CONFIG_ISO_IN_ZLP - Respond to an IN token on ISO IN endpoint with ZLP when no data is ready.
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_USBD_CONFIG_ISO_IN_ZLP
#define NRFX_USBD_CONFIG_ISO_IN_ZLP 0
#endif
-// NRFX_USBD_CONFIG_LOG_ENABLED - Enable logging in the module
-//==========================================================
+/**
+ * @brief NRFX_USBD_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_USBD_CONFIG_LOG_ENABLED
#define NRFX_USBD_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_USBD_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_USBD_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_USBD_CONFIG_LOG_LEVEL
#define NRFX_USBD_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_USBD_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_USBD_CONFIG_INFO_COLOR
-#define NRFX_USBD_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_USBD_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_USBD_CONFIG_DEBUG_COLOR
-#define NRFX_USBD_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_WDT_ENABLED - nrfx_wdt - WDT peripheral driver
-//==========================================================
+/**
+ * @brief NRFX_WDT_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_WDT_ENABLED
#define NRFX_WDT_ENABLED 0
#endif
-// NRFX_WDT0_ENABLED - Enable WDT0 instance
-
-#ifndef NRFX_WDT0_ENABLED
-#define NRFX_WDT0_ENABLED 0
+/**
+ * @brief NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
#endif
-// NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver
-
-// <0=> Include WDT IRQ handling
-// <1=> Remove WDT IRQ handling
-
+/**
+ * @brief NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_WDT_CONFIG_NO_IRQ
#define NRFX_WDT_CONFIG_NO_IRQ 0
#endif
-// NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-// NRFX_WDT_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
+/**
+ * @brief NRFX_WDT_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
#ifndef NRFX_WDT_CONFIG_LOG_ENABLED
#define NRFX_WDT_CONFIG_LOG_ENABLED 0
#endif
-// NRFX_WDT_CONFIG_LOG_LEVEL - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
+/**
+ * @brief NRFX_WDT_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
#ifndef NRFX_WDT_CONFIG_LOG_LEVEL
#define NRFX_WDT_CONFIG_LOG_LEVEL 3
#endif
-// NRFX_WDT_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_WDT_CONFIG_INFO_COLOR
-#define NRFX_WDT_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_WDT_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_WDT_CONFIG_DEBUG_COLOR
-#define NRFX_WDT_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-//
-
#endif // NRFX_CONFIG_NRF52840_H__
diff --git a/mcu/nrf/common/vendor/templates/nrfx_config_nrf91.h b/mcu/nrf/common/vendor/templates/nrfx_config_nrf91.h
new file mode 100644
index 00000000..2a218291
--- /dev/null
+++ b/mcu/nrf/common/vendor/templates/nrfx_config_nrf91.h
@@ -0,0 +1,1260 @@
+/*
+ * Copyright (c) 2018 - 2023, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRFX_CONFIG_NRF91_H__
+#define NRFX_CONFIG_NRF91_H__
+
+#ifndef NRFX_CONFIG_H__
+#error "This file should not be included directly. Include nrfx_config.h instead."
+#endif
+
+/*
+ * The MDK provides macros for accessing the peripheral register structures
+ * by using their secure and non-secure address mappings (with the names
+ * containing the suffix _S or _NS, respectively). Because the nrfx drivers
+ * use the macros without any suffixes, you must translate the names.
+ * The following section provides configuration for the name translation.
+ * It must be modified to reflect the actual configuration set in NRF_SPU.
+ */
+#define NRF_CLOCK NRF_CLOCK_S
+#define NRF_DPPIC NRF_DPPIC_S
+#define NRF_EGU0 NRF_EGU0_S
+#define NRF_EGU1 NRF_EGU1_S
+#define NRF_EGU2 NRF_EGU2_S
+#define NRF_EGU3 NRF_EGU3_S
+#define NRF_EGU4 NRF_EGU4_S
+#define NRF_EGU5 NRF_EGU5_S
+#define NRF_FPU NRF_FPU_S
+#define NRF_I2S NRF_I2S_S
+#define NRF_IPC NRF_IPC_S
+#define NRF_KMU NRF_KMU_S
+#define NRF_NVMC NRF_NVMC_S
+#define NRF_P0 NRF_P0_S
+#define NRF_PDM NRF_PDM_S
+#define NRF_POWER NRF_POWER_S
+#define NRF_PWM0 NRF_PWM0_S
+#define NRF_PWM1 NRF_PWM1_S
+#define NRF_PWM2 NRF_PWM2_S
+#define NRF_PWM3 NRF_PWM3_S
+#define NRF_REGULATORS NRF_REGULATORS_S
+#define NRF_RTC0 NRF_RTC0_S
+#define NRF_RTC1 NRF_RTC1_S
+#define NRF_SAADC NRF_SAADC_S
+#define NRF_SPIM0 NRF_SPIM0_S
+#define NRF_SPIM1 NRF_SPIM1_S
+#define NRF_SPIM2 NRF_SPIM2_S
+#define NRF_SPIM3 NRF_SPIM3_S
+#define NRF_SPIS0 NRF_SPIS0_S
+#define NRF_SPIS1 NRF_SPIS1_S
+#define NRF_SPIS2 NRF_SPIS2_S
+#define NRF_SPIS3 NRF_SPIS3_S
+#define NRF_TIMER0 NRF_TIMER0_S
+#define NRF_TIMER1 NRF_TIMER1_S
+#define NRF_TIMER2 NRF_TIMER2_S
+#define NRF_TWIM0 NRF_TWIM0_S
+#define NRF_TWIM1 NRF_TWIM1_S
+#define NRF_TWIM2 NRF_TWIM2_S
+#define NRF_TWIM3 NRF_TWIM3_S
+#define NRF_TWIS0 NRF_TWIS0_S
+#define NRF_TWIS1 NRF_TWIS1_S
+#define NRF_TWIS2 NRF_TWIS2_S
+#define NRF_TWIS3 NRF_TWIS3_S
+#define NRF_UARTE0 NRF_UARTE0_S
+#define NRF_UARTE1 NRF_UARTE1_S
+#define NRF_UARTE2 NRF_UARTE2_S
+#define NRF_UARTE3 NRF_UARTE3_S
+#define NRF_VMC NRF_VMC_S
+#define NRF_WDT NRF_WDT_S
+
+/*
+ * The following section provides the name translation for peripherals with
+ * only one type of access available. For these peripherals, you cannot choose
+ * between secure and non-secure mapping.
+ */
+#if defined(NRF_TRUSTZONE_NONSECURE)
+#define NRF_GPIOTE1 NRF_GPIOTE1_NS
+#else
+#define NRF_CC_HOST_RGF NRF_CC_HOST_RGF_S
+#define NRF_CRYPTOCELL NRF_CRYPTOCELL_S
+#define NRF_CTRL_AP_PERI NRF_CTRL_AP_PERI_S
+#define NRF_FICR NRF_FICR_S
+#define NRF_GPIOTE0 NRF_GPIOTE0_S
+#define NRF_SPU NRF_SPU_S
+#define NRF_TAD NRF_TAD_S
+#define NRF_UICR NRF_UICR_S
+#endif
+
+/* Fixups for the GPIOTE driver. */
+#if defined(NRF_TRUSTZONE_NONSECURE)
+#define NRF_GPIOTE NRF_GPIOTE1
+#define GPIOTE_IRQHandler GPIOTE1_IRQHandler
+#else
+#define NRF_GPIOTE NRF_GPIOTE0
+#define GPIOTE_IRQHandler GPIOTE0_IRQHandler
+#endif
+
+/**
+ * @brief NRFX_DEFAULT_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_DEFAULT_IRQ_PRIORITY
+#define NRFX_DEFAULT_IRQ_PRIORITY 7
+#endif
+
+/**
+ * @brief NRFX_CLOCK_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_CLOCK_ENABLED
+#define NRFX_CLOCK_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_CLOCK_CONFIG_LF_SRC
+ *
+ * Integer value.
+ * Supported values:
+ * - RC = 1
+ * - XTAL = 2
+ */
+#ifndef NRFX_CLOCK_CONFIG_LF_SRC
+#define NRFX_CLOCK_CONFIG_LF_SRC 2
+#endif
+
+/**
+ * @brief NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED
+#define NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_CLOCK_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_CLOCK_CONFIG_LOG_ENABLED
+#define NRFX_CLOCK_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_CLOCK_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_CLOCK_CONFIG_LOG_LEVEL
+#define NRFX_CLOCK_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_DPPI_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_DPPI_ENABLED
+#define NRFX_DPPI_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_DPPI_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_DPPI_CONFIG_LOG_ENABLED
+#define NRFX_DPPI_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_DPPI_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_DPPI_CONFIG_LOG_LEVEL
+#define NRFX_DPPI_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_EGU_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_EGU_ENABLED
+#define NRFX_EGU_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_EGU0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_EGU0_ENABLED
+#define NRFX_EGU0_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_EGU1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_EGU1_ENABLED
+#define NRFX_EGU1_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_EGU2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_EGU2_ENABLED
+#define NRFX_EGU2_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_EGU3_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_EGU3_ENABLED
+#define NRFX_EGU3_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_EGU4_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_EGU4_ENABLED
+#define NRFX_EGU4_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_EGU5_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_EGU5_ENABLED
+#define NRFX_EGU5_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_GPIOTE_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_GPIOTE_ENABLED
+#define NRFX_GPIOTE_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY 3
+#endif
+
+/**
+ * @brief NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS
+ *
+ * Integer value. Minimum: 0 Maximum: 15
+ */
+#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS
+#define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS 2
+#endif
+
+/**
+ * @brief NRFX_GPIOTE_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED
+#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_GPIOTE_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL
+#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_I2S_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_I2S_ENABLED
+#define NRFX_I2S_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_I2S_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_I2S_CONFIG_LOG_ENABLED
+#define NRFX_I2S_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_I2S_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_I2S_CONFIG_LOG_LEVEL
+#define NRFX_I2S_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_IPC_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_IPC_ENABLED
+#define NRFX_IPC_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_NVMC_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_NVMC_ENABLED
+#define NRFX_NVMC_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PDM_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_PDM_ENABLED
+#define NRFX_PDM_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_PDM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_PDM_CONFIG_LOG_ENABLED
+#define NRFX_PDM_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PDM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_PDM_CONFIG_LOG_LEVEL
+#define NRFX_PDM_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_POWER_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_POWER_ENABLED
+#define NRFX_POWER_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_PRS_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_PRS_ENABLED
+#define NRFX_PRS_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_PRS_CONFIG_LOG_ENABLED
+#define NRFX_PRS_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_PRS_CONFIG_LOG_LEVEL
+#define NRFX_PRS_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_0_ENABLED
+#define NRFX_PRS_BOX_0_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_1_ENABLED
+#define NRFX_PRS_BOX_1_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_2_ENABLED
+#define NRFX_PRS_BOX_2_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PRS_BOX_3_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_PRS_BOX_3_ENABLED
+#define NRFX_PRS_BOX_3_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_PWM_ENABLED
+#define NRFX_PWM_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_PWM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_PWM_CONFIG_LOG_ENABLED
+#define NRFX_PWM_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_PWM_CONFIG_LOG_LEVEL
+#define NRFX_PWM_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_PWM0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_PWM0_ENABLED
+#define NRFX_PWM0_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_PWM1_ENABLED
+#define NRFX_PWM1_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_PWM2_ENABLED
+#define NRFX_PWM2_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_PWM3_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_PWM3_ENABLED
+#define NRFX_PWM3_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_RTC_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_RTC_ENABLED
+#define NRFX_RTC_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_RTC_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_RTC_CONFIG_LOG_ENABLED
+#define NRFX_RTC_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_RTC_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_RTC_CONFIG_LOG_LEVEL
+#define NRFX_RTC_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_RTC0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_RTC0_ENABLED
+#define NRFX_RTC0_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_RTC1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_RTC1_ENABLED
+#define NRFX_RTC1_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SAADC_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SAADC_ENABLED
+#define NRFX_SAADC_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_SAADC_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED
+#define NRFX_SAADC_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SAADC_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL
+#define NRFX_SAADC_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_SPIM_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIM_ENABLED
+#define NRFX_SPIM_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_SPIM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED
+#define NRFX_SPIM_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL
+#define NRFX_SPIM_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_SPIM0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIM0_ENABLED
+#define NRFX_SPIM0_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIM1_ENABLED
+#define NRFX_SPIM1_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIM2_ENABLED
+#define NRFX_SPIM2_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIM3_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIM3_ENABLED
+#define NRFX_SPIM3_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIS_ENABLED
+#define NRFX_SPIS_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_SPIS_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED
+#define NRFX_SPIS_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL
+#define NRFX_SPIS_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_SPIS0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIS0_ENABLED
+#define NRFX_SPIS0_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIS1_ENABLED
+#define NRFX_SPIS1_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIS2_ENABLED
+#define NRFX_SPIS2_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SPIS3_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SPIS3_ENABLED
+#define NRFX_SPIS3_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_SYSTICK_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_SYSTICK_ENABLED
+#define NRFX_SYSTICK_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TIMER_ENABLED
+#define NRFX_TIMER_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_TIMER_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED
+#define NRFX_TIMER_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL
+#define NRFX_TIMER_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_TIMER0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TIMER0_ENABLED
+#define NRFX_TIMER0_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TIMER1_ENABLED
+#define NRFX_TIMER1_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TIMER2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TIMER2_ENABLED
+#define NRFX_TIMER2_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWIM_ENABLED
+#define NRFX_TWIM_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_TWIM_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED
+#define NRFX_TWIM_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL
+#define NRFX_TWIM_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_TWIM0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWIM0_ENABLED
+#define NRFX_TWIM0_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWIM1_ENABLED
+#define NRFX_TWIM1_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWIM2_ENABLED
+#define NRFX_TWIM2_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIM3_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWIM3_ENABLED
+#define NRFX_TWIM3_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWIS_ENABLED
+#define NRFX_TWIS_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_TWIS_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED
+#define NRFX_TWIS_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance would be initialized only once.
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY
+#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
+#endif
+
+/**
+ * @brief NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode.
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWIS_NO_SYNC_MODE
+#define NRFX_TWIS_NO_SYNC_MODE 0
+#endif
+
+/**
+ * @brief NRFX_TWIS_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL
+#define NRFX_TWIS_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_TWIS0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWIS0_ENABLED
+#define NRFX_TWIS0_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWIS1_ENABLED
+#define NRFX_TWIS1_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWIS2_ENABLED
+#define NRFX_TWIS2_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_TWIS3_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_TWIS3_ENABLED
+#define NRFX_TWIS3_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_UARTE_ENABLED
+#define NRFX_UARTE_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_UARTE_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED
+#define NRFX_UARTE_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL
+#define NRFX_UARTE_CONFIG_LOG_LEVEL 3
+#endif
+
+/**
+ * @brief NRFX_UARTE0_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_UARTE0_ENABLED
+#define NRFX_UARTE0_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE1_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_UARTE1_ENABLED
+#define NRFX_UARTE1_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE2_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_UARTE2_ENABLED
+#define NRFX_UARTE2_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_UARTE3_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_UARTE3_ENABLED
+#define NRFX_UARTE3_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_WDT_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_WDT_ENABLED
+#define NRFX_WDT_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY
+ *
+ * Integer value. Minimum: 0 Maximum: 7
+ */
+#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_WDT_CONFIG_NO_IRQ
+#define NRFX_WDT_CONFIG_NO_IRQ 0
+#endif
+
+/**
+ * @brief NRFX_WDT_CONFIG_LOG_ENABLED
+ *
+ * Boolean. Accepted values 0 and 1.
+ */
+#ifndef NRFX_WDT_CONFIG_LOG_ENABLED
+#define NRFX_WDT_CONFIG_LOG_ENABLED 0
+#endif
+
+/**
+ * @brief NRFX_WDT_CONFIG_LOG_LEVEL
+ *
+ * Integer value.
+ * Supported values:
+ * - Off = 0
+ * - Error = 1
+ * - Warning = 2
+ * - Info = 3
+ * - Debug = 4
+ */
+#ifndef NRFX_WDT_CONFIG_LOG_LEVEL
+#define NRFX_WDT_CONFIG_LOG_LEVEL 3
+#endif
+
+#endif // NRFX_CONFIG_NRF91_H__
diff --git a/mcu/nrf/common/vendor/templates/nrfx_config_nrf9160.h b/mcu/nrf/common/vendor/templates/nrfx_config_nrf9160.h
deleted file mode 100644
index 64b7cbc4..00000000
--- a/mcu/nrf/common/vendor/templates/nrfx_config_nrf9160.h
+++ /dev/null
@@ -1,1656 +0,0 @@
-/*
- * Copyright (c) 2018 - 2021, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from this
- * software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef NRFX_CONFIG_NRF9160_H__
-#define NRFX_CONFIG_NRF9160_H__
-
-#ifndef NRFX_CONFIG_H__
-#error "This file should not be included directly. Include nrfx_config.h instead."
-#endif
-
-/*
- * The MDK provides macros for accessing the peripheral register structures
- * by using their secure and non-secure address mappings (with the names
- * containing the suffix _S or _NS, respectively). Because the nrfx drivers
- * use the macros without any suffixes, you must translate the names.
- * The following section provides configuration for the name translation.
- * It must be modified to reflect the actual configuration set in NRF_SPU.
- */
-#define NRF_CLOCK NRF_CLOCK_S
-#define NRF_DPPIC NRF_DPPIC_S
-#define NRF_EGU0 NRF_EGU0_S
-#define NRF_EGU1 NRF_EGU1_S
-#define NRF_EGU2 NRF_EGU2_S
-#define NRF_EGU3 NRF_EGU3_S
-#define NRF_EGU4 NRF_EGU4_S
-#define NRF_EGU5 NRF_EGU5_S
-#define NRF_FPU NRF_FPU_S
-#define NRF_I2S NRF_I2S_S
-#define NRF_IPC NRF_IPC_S
-#define NRF_KMU NRF_KMU_S
-#define NRF_NVMC NRF_NVMC_S
-#define NRF_P0 NRF_P0_S
-#define NRF_PDM NRF_PDM_S
-#define NRF_POWER NRF_POWER_S
-#define NRF_PWM0 NRF_PWM0_S
-#define NRF_PWM1 NRF_PWM1_S
-#define NRF_PWM2 NRF_PWM2_S
-#define NRF_PWM3 NRF_PWM3_S
-#define NRF_REGULATORS NRF_REGULATORS_S
-#define NRF_RTC0 NRF_RTC0_S
-#define NRF_RTC1 NRF_RTC1_S
-#define NRF_SAADC NRF_SAADC_S
-#define NRF_SPIM0 NRF_SPIM0_S
-#define NRF_SPIM1 NRF_SPIM1_S
-#define NRF_SPIM2 NRF_SPIM2_S
-#define NRF_SPIM3 NRF_SPIM3_S
-#define NRF_SPIS0 NRF_SPIS0_S
-#define NRF_SPIS1 NRF_SPIS1_S
-#define NRF_SPIS2 NRF_SPIS2_S
-#define NRF_SPIS3 NRF_SPIS3_S
-#define NRF_TIMER0 NRF_TIMER0_S
-#define NRF_TIMER1 NRF_TIMER1_S
-#define NRF_TIMER2 NRF_TIMER2_S
-#define NRF_TWIM0 NRF_TWIM0_S
-#define NRF_TWIM1 NRF_TWIM1_S
-#define NRF_TWIM2 NRF_TWIM2_S
-#define NRF_TWIM3 NRF_TWIM3_S
-#define NRF_TWIS0 NRF_TWIS0_S
-#define NRF_TWIS1 NRF_TWIS1_S
-#define NRF_TWIS2 NRF_TWIS2_S
-#define NRF_TWIS3 NRF_TWIS3_S
-#define NRF_UARTE0 NRF_UARTE0_S
-#define NRF_UARTE1 NRF_UARTE1_S
-#define NRF_UARTE2 NRF_UARTE2_S
-#define NRF_UARTE3 NRF_UARTE3_S
-#define NRF_VMC NRF_VMC_S
-#define NRF_WDT NRF_WDT_S
-
-/*
- * The following section provides the name translation for peripherals with
- * only one type of access available. For these peripherals, you cannot choose
- * between secure and non-secure mapping.
- */
-#if defined(NRF_TRUSTZONE_NONSECURE)
-#define NRF_GPIOTE1 NRF_GPIOTE1_NS
-#else
-#define NRF_CC_HOST_RGF NRF_CC_HOST_RGF_S
-#define NRF_CRYPTOCELL NRF_CRYPTOCELL_S
-#define NRF_CTRL_AP_PERI NRF_CTRL_AP_PERI_S
-#define NRF_FICR NRF_FICR_S
-#define NRF_GPIOTE0 NRF_GPIOTE0_S
-#define NRF_SPU NRF_SPU_S
-#define NRF_TAD NRF_TAD_S
-#define NRF_UICR NRF_UICR_S
-#endif
-
-/* Fixups for the GPIOTE driver. */
-#if defined(NRF_TRUSTZONE_NONSECURE)
-#define NRF_GPIOTE NRF_GPIOTE1
-#define GPIOTE_IRQHandler GPIOTE1_IRQHandler
-#else
-#define NRF_GPIOTE NRF_GPIOTE0
-#define GPIOTE_IRQHandler GPIOTE0_IRQHandler
-#endif
-
-// <<< Use Configuration Wizard in Context Menu >>>\n
-
-// nRF_Drivers
-
-// NRFX_CLOCK_ENABLED - nrfx_clock - CLOCK peripheral driver.
-//==========================================================
-#ifndef NRFX_CLOCK_ENABLED
-#define NRFX_CLOCK_ENABLED 0
-#endif
-// NRFX_CLOCK_CONFIG_LF_SRC - LF clock source.
-
-// <1=> RC
-// <2=> XTAL
-
-#ifndef NRFX_CLOCK_CONFIG_LF_SRC
-#define NRFX_CLOCK_CONFIG_LF_SRC 2
-#endif
-
-// NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED - Enables two-stage LFXO start procedure
-
-// If set to a non-zero value, LFRC will be started before LFXO and corresponding
-// event will be generated. It means that CPU will be woken up when LFRC
-// oscillator starts, but user callback will be invoked only after LFXO
-// finally starts.
-
-#ifndef NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED
-#define NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED 0
-#endif
-
-// NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority.
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-// NRFX_CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_CLOCK_CONFIG_LOG_ENABLED
-#define NRFX_CLOCK_CONFIG_LOG_ENABLED 0
-#endif
-// NRFX_CLOCK_CONFIG_LOG_LEVEL - Default severity level.
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef NRFX_CLOCK_CONFIG_LOG_LEVEL
-#define NRFX_CLOCK_CONFIG_LOG_LEVEL 3
-#endif
-
-// NRFX_CLOCK_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_CLOCK_CONFIG_INFO_COLOR
-#define NRFX_CLOCK_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_CLOCK_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_CLOCK_CONFIG_DEBUG_COLOR
-#define NRFX_CLOCK_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_DPPI_ENABLED - nrfx_dppi - DPPI allocator.
-//==========================================================
-#ifndef NRFX_DPPI_ENABLED
-#define NRFX_DPPI_ENABLED 0
-#endif
-// NRFX_DPPI_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_DPPI_CONFIG_LOG_ENABLED
-#define NRFX_DPPI_CONFIG_LOG_ENABLED 0
-#endif
-// NRFX_DPPI_CONFIG_LOG_LEVEL - Default severity level.
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef NRFX_DPPI_CONFIG_LOG_LEVEL
-#define NRFX_DPPI_CONFIG_LOG_LEVEL 3
-#endif
-
-// NRFX_DPPI_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_DPPI_CONFIG_INFO_COLOR
-#define NRFX_DPPI_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_DPPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_DPPI_CONFIG_DEBUG_COLOR
-#define NRFX_DPPI_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_EGU_ENABLED - nrfx_egu - EGU peripheral driver.
-//==========================================================
-#ifndef NRFX_EGU_ENABLED
-#define NRFX_EGU_ENABLED 0
-#endif
-
-// NRFX_EGU0_ENABLED - Enable EGU0 instance.
-
-#ifndef NRFX_EGU0_ENABLED
-#define NRFX_EGU0_ENABLED 0
-#endif
-
-// NRFX_EGU1_ENABLED - Enable EGU1 instance.
-
-#ifndef NRFX_EGU1_ENABLED
-#define NRFX_EGU1_ENABLED 0
-#endif
-
-// NRFX_EGU2_ENABLED - Enable EGU2 instance.
-
-#ifndef NRFX_EGU2_ENABLED
-#define NRFX_EGU2_ENABLED 0
-#endif
-
-// NRFX_EGU3_ENABLED - Enable EGU3 instance.
-
-#ifndef NRFX_EGU3_ENABLED
-#define NRFX_EGU3_ENABLED 0
-#endif
-
-// NRFX_EGU4_ENABLED - Enable EGU4 instance.
-
-#ifndef NRFX_EGU4_ENABLED
-#define NRFX_EGU4_ENABLED 0
-#endif
-
-// NRFX_EGU5_ENABLED - Enable EGU5 instance.
-
-#ifndef NRFX_EGU5_ENABLED
-#define NRFX_EGU5_ENABLED 0
-#endif
-
-// NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority.
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-//
-
-// NRFX_GPIOTE_ENABLED - nrfx_gpiote - GPIOTE peripheral driver.
-//==========================================================
-#ifndef NRFX_GPIOTE_ENABLED
-#define NRFX_GPIOTE_ENABLED 0
-#endif
-// NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins.
-#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS
-#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1
-#endif
-
-// NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority.
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-// NRFX_GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED
-#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0
-#endif
-// NRFX_GPIOTE_CONFIG_LOG_LEVEL - Default severity level.
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL
-#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3
-#endif
-
-// NRFX_GPIOTE_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_GPIOTE_CONFIG_INFO_COLOR
-#define NRFX_GPIOTE_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_GPIOTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_GPIOTE_CONFIG_DEBUG_COLOR
-#define NRFX_GPIOTE_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_I2S_ENABLED - nrfx_i2s - I2S peripheral driver.
-//==========================================================
-#ifndef NRFX_I2S_ENABLED
-#define NRFX_I2S_ENABLED 0
-#endif
-
-// NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority.
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_I2S_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-// NRFX_I2S_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_I2S_CONFIG_LOG_ENABLED
-#define NRFX_I2S_CONFIG_LOG_ENABLED 0
-#endif
-// NRFX_I2S_CONFIG_LOG_LEVEL - Default severity level.
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef NRFX_I2S_CONFIG_LOG_LEVEL
-#define NRFX_I2S_CONFIG_LOG_LEVEL 3
-#endif
-
-// NRFX_I2S_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_I2S_CONFIG_INFO_COLOR
-#define NRFX_I2S_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_I2S_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_I2S_CONFIG_DEBUG_COLOR
-#define NRFX_I2S_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_IPC_ENABLED - nrfx_ipc - IPC peripheral driver
-//==========================================================
-#ifndef NRFX_IPC_ENABLED
-#define NRFX_IPC_ENABLED 0
-#endif
-
-//
-
-// NRFX_NVMC_ENABLED - nrfx_nvmc - NVMC peripheral driver
-//==========================================================
-#ifndef NRFX_NVMC_ENABLED
-#define NRFX_NVMC_ENABLED 0
-#endif
-
-//
-
-// NRFX_PDM_ENABLED - nrfx_pdm - PDM peripheral driver.
-//==========================================================
-#ifndef NRFX_PDM_ENABLED
-#define NRFX_PDM_ENABLED 0
-#endif
-
-// NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority.
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_PDM_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-// NRFX_PDM_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_PDM_CONFIG_LOG_ENABLED
-#define NRFX_PDM_CONFIG_LOG_ENABLED 0
-#endif
-// NRFX_PDM_CONFIG_LOG_LEVEL - Default severity level.
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef NRFX_PDM_CONFIG_LOG_LEVEL
-#define NRFX_PDM_CONFIG_LOG_LEVEL 3
-#endif
-
-// NRFX_PDM_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_PDM_CONFIG_INFO_COLOR
-#define NRFX_PDM_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_PDM_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_PDM_CONFIG_DEBUG_COLOR
-#define NRFX_PDM_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_POWER_ENABLED - nrfx_power - POWER peripheral driver.
-//==========================================================
-#ifndef NRFX_POWER_ENABLED
-#define NRFX_POWER_ENABLED 0
-#endif
-// NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority.
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-//
-
-// NRFX_PRS_ENABLED - nrfx_prs - Peripheral Resource Sharing (PRS) module.
-//==========================================================
-#ifndef NRFX_PRS_ENABLED
-#define NRFX_PRS_ENABLED 0
-#endif
-// NRFX_PRS_BOX_0_ENABLED - Enables box 0 in the module.
-
-
-#ifndef NRFX_PRS_BOX_0_ENABLED
-#define NRFX_PRS_BOX_0_ENABLED 0
-#endif
-
-// NRFX_PRS_BOX_1_ENABLED - Enables box 1 in the module.
-
-
-#ifndef NRFX_PRS_BOX_1_ENABLED
-#define NRFX_PRS_BOX_1_ENABLED 0
-#endif
-
-// NRFX_PRS_BOX_2_ENABLED - Enables box 2 in the module.
-
-
-#ifndef NRFX_PRS_BOX_2_ENABLED
-#define NRFX_PRS_BOX_2_ENABLED 0
-#endif
-
-// NRFX_PRS_BOX_3_ENABLED - Enables box 3 in the module.
-
-
-#ifndef NRFX_PRS_BOX_3_ENABLED
-#define NRFX_PRS_BOX_3_ENABLED 0
-#endif
-
-// NRFX_PRS_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_PRS_CONFIG_LOG_ENABLED
-#define NRFX_PRS_CONFIG_LOG_ENABLED 0
-#endif
-// NRFX_PRS_CONFIG_LOG_LEVEL - Default severity level.
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef NRFX_PRS_CONFIG_LOG_LEVEL
-#define NRFX_PRS_CONFIG_LOG_LEVEL 3
-#endif
-
-// NRFX_PRS_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_PRS_CONFIG_INFO_COLOR
-#define NRFX_PRS_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_PRS_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_PRS_CONFIG_DEBUG_COLOR
-#define NRFX_PRS_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_PWM_ENABLED - nrfx_pwm - PWM peripheral driver.
-//==========================================================
-#ifndef NRFX_PWM_ENABLED
-#define NRFX_PWM_ENABLED 0
-#endif
-// NRFX_PWM0_ENABLED - Enables PWM0 instance.
-
-
-#ifndef NRFX_PWM0_ENABLED
-#define NRFX_PWM0_ENABLED 0
-#endif
-
-// NRFX_PWM1_ENABLED - Enables PWM1 instance.
-
-
-#ifndef NRFX_PWM1_ENABLED
-#define NRFX_PWM1_ENABLED 0
-#endif
-
-// NRFX_PWM2_ENABLED - Enables PWM2 instance.
-
-
-#ifndef NRFX_PWM2_ENABLED
-#define NRFX_PWM2_ENABLED 0
-#endif
-
-// NRFX_PWM3_ENABLED - Enables PWM3 instance.
-
-
-#ifndef NRFX_PWM3_ENABLED
-#define NRFX_PWM3_ENABLED 0
-#endif
-
-// NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority.
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-// NRFX_PWM_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_PWM_CONFIG_LOG_ENABLED
-#define NRFX_PWM_CONFIG_LOG_ENABLED 0
-#endif
-// NRFX_PWM_CONFIG_LOG_LEVEL - Default severity level.
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef NRFX_PWM_CONFIG_LOG_LEVEL
-#define NRFX_PWM_CONFIG_LOG_LEVEL 3
-#endif
-
-// NRFX_PWM_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_PWM_CONFIG_INFO_COLOR
-#define NRFX_PWM_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_PWM_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_PWM_CONFIG_DEBUG_COLOR
-#define NRFX_PWM_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_RTC_ENABLED - nrfx_rtc - RTC peripheral driver.
-//==========================================================
-#ifndef NRFX_RTC_ENABLED
-#define NRFX_RTC_ENABLED 0
-#endif
-// NRFX_RTC0_ENABLED - Enables RTC0 instance.
-
-
-#ifndef NRFX_RTC0_ENABLED
-#define NRFX_RTC0_ENABLED 0
-#endif
-
-// NRFX_RTC1_ENABLED - Enables RTC1 instance.
-
-
-#ifndef NRFX_RTC1_ENABLED
-#define NRFX_RTC1_ENABLED 0
-#endif
-
-// NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority.
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-// NRFX_RTC_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_RTC_CONFIG_LOG_ENABLED
-#define NRFX_RTC_CONFIG_LOG_ENABLED 0
-#endif
-// NRFX_RTC_CONFIG_LOG_LEVEL - Default severity level.
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef NRFX_RTC_CONFIG_LOG_LEVEL
-#define NRFX_RTC_CONFIG_LOG_LEVEL 3
-#endif
-
-// NRFX_RTC_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_RTC_CONFIG_INFO_COLOR
-#define NRFX_RTC_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_RTC_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_RTC_CONFIG_DEBUG_COLOR
-#define NRFX_RTC_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_SAADC_ENABLED - nrfx_saadc - SAADC peripheral driver.
-//==========================================================
-#ifndef NRFX_SAADC_ENABLED
-#define NRFX_SAADC_ENABLED 0
-#endif
-
-// NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority.
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-// NRFX_SAADC_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED
-#define NRFX_SAADC_CONFIG_LOG_ENABLED 0
-#endif
-// NRFX_SAADC_CONFIG_LOG_LEVEL - Default severity level.
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL
-#define NRFX_SAADC_CONFIG_LOG_LEVEL 3
-#endif
-
-// NRFX_SAADC_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_SAADC_CONFIG_INFO_COLOR
-#define NRFX_SAADC_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_SAADC_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_SAADC_CONFIG_DEBUG_COLOR
-#define NRFX_SAADC_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_SPIM_ENABLED - nrfx_spim - SPIM peripheral driver.
-//==========================================================
-#ifndef NRFX_SPIM_ENABLED
-#define NRFX_SPIM_ENABLED 0
-#endif
-// NRFX_SPIM0_ENABLED - Enables SPIM0 instance.
-
-
-#ifndef NRFX_SPIM0_ENABLED
-#define NRFX_SPIM0_ENABLED 0
-#endif
-
-// NRFX_SPIM1_ENABLED - Enables SPIM1 instance.
-
-
-#ifndef NRFX_SPIM1_ENABLED
-#define NRFX_SPIM1_ENABLED 0
-#endif
-
-// NRFX_SPIM2_ENABLED - Enables SPIM2 instance.
-
-
-#ifndef NRFX_SPIM2_ENABLED
-#define NRFX_SPIM2_ENABLED 0
-#endif
-
-// NRFX_SPIM3_ENABLED - Enables SPIM3 instance.
-
-
-#ifndef NRFX_SPIM3_ENABLED
-#define NRFX_SPIM3_ENABLED 0
-#endif
-
-// NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority.
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-// NRFX_SPIM_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED
-#define NRFX_SPIM_CONFIG_LOG_ENABLED 0
-#endif
-// NRFX_SPIM_CONFIG_LOG_LEVEL - Default severity level.
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL
-#define NRFX_SPIM_CONFIG_LOG_LEVEL 3
-#endif
-
-// NRFX_SPIM_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_SPIM_CONFIG_INFO_COLOR
-#define NRFX_SPIM_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_SPIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_SPIM_CONFIG_DEBUG_COLOR
-#define NRFX_SPIM_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_SPIS_ENABLED - nrfx_spis - SPIS peripheral driver.
-//==========================================================
-#ifndef NRFX_SPIS_ENABLED
-#define NRFX_SPIS_ENABLED 0
-#endif
-// NRFX_SPIS0_ENABLED - Enables SPIS0 instance.
-
-
-#ifndef NRFX_SPIS0_ENABLED
-#define NRFX_SPIS0_ENABLED 0
-#endif
-
-// NRFX_SPIS1_ENABLED - Enables SPIS1 instance.
-
-
-#ifndef NRFX_SPIS1_ENABLED
-#define NRFX_SPIS1_ENABLED 0
-#endif
-
-// NRFX_SPIS2_ENABLED - Enables SPIS2 instance.
-
-
-#ifndef NRFX_SPIS2_ENABLED
-#define NRFX_SPIS2_ENABLED 0
-#endif
-
-// NRFX_SPIS3_ENABLED - Enables SPIS3 instance.
-
-
-#ifndef NRFX_SPIS3_ENABLED
-#define NRFX_SPIS3_ENABLED 0
-#endif
-
-// NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority.
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-// NRFX_SPIS_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED
-#define NRFX_SPIS_CONFIG_LOG_ENABLED 0
-#endif
-// NRFX_SPIS_CONFIG_LOG_LEVEL - Default severity level.
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL
-#define NRFX_SPIS_CONFIG_LOG_LEVEL 3
-#endif
-
-// NRFX_SPIS_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_SPIS_CONFIG_INFO_COLOR
-#define NRFX_SPIS_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_SPIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_SPIS_CONFIG_DEBUG_COLOR
-#define NRFX_SPIS_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_SYSTICK_ENABLED - nrfx_systick - ARM(R) SysTick driver.
-
-
-#ifndef NRFX_SYSTICK_ENABLED
-#define NRFX_SYSTICK_ENABLED 0
-#endif
-
-// NRFX_TIMER_ENABLED - nrfx_timer - TIMER periperal driver.
-//==========================================================
-#ifndef NRFX_TIMER_ENABLED
-#define NRFX_TIMER_ENABLED 0
-#endif
-
-// NRFX_TIMER0_ENABLED - Enables TIMER0 instance.
-
-#ifndef NRFX_TIMER0_ENABLED
-#define NRFX_TIMER0_ENABLED 0
-#endif
-
-// NRFX_TIMER1_ENABLED - Enables TIMER1 instance.
-
-#ifndef NRFX_TIMER1_ENABLED
-#define NRFX_TIMER1_ENABLED 0
-#endif
-
-// NRFX_TIMER2_ENABLED - Enables TIMER2 instance.
-
-#ifndef NRFX_TIMER2_ENABLED
-#define NRFX_TIMER2_ENABLED 0
-#endif
-
-// NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority.
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-// NRFX_TIMER_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED
-#define NRFX_TIMER_CONFIG_LOG_ENABLED 0
-#endif
-// NRFX_TIMER_CONFIG_LOG_LEVEL - Default severity level.
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL
-#define NRFX_TIMER_CONFIG_LOG_LEVEL 3
-#endif
-
-// NRFX_TIMER_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_TIMER_CONFIG_INFO_COLOR
-#define NRFX_TIMER_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_TIMER_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_TIMER_CONFIG_DEBUG_COLOR
-#define NRFX_TIMER_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_TWIM_ENABLED - nrfx_twim - TWIM peripheral driver.
-//==========================================================
-#ifndef NRFX_TWIM_ENABLED
-#define NRFX_TWIM_ENABLED 0
-#endif
-// NRFX_TWIM0_ENABLED - Enables TWIM0 instance.
-
-
-#ifndef NRFX_TWIM0_ENABLED
-#define NRFX_TWIM0_ENABLED 0
-#endif
-
-// NRFX_TWIM1_ENABLED - Enables TWIM1 instance.
-
-
-#ifndef NRFX_TWIM1_ENABLED
-#define NRFX_TWIM1_ENABLED 0
-#endif
-
-// NRFX_TWIM2_ENABLED - Enables TWIM2 instance.
-
-
-#ifndef NRFX_TWIM2_ENABLED
-#define NRFX_TWIM2_ENABLED 0
-#endif
-
-// NRFX_TWIM3_ENABLED - Enables TWIM3 instance.
-
-
-#ifndef NRFX_TWIM3_ENABLED
-#define NRFX_TWIM3_ENABLED 0
-#endif
-
-// NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority.
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-// NRFX_TWIM_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED
-#define NRFX_TWIM_CONFIG_LOG_ENABLED 0
-#endif
-// NRFX_TWIM_CONFIG_LOG_LEVEL - Default severity level.
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL
-#define NRFX_TWIM_CONFIG_LOG_LEVEL 3
-#endif
-
-// NRFX_TWIM_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_TWIM_CONFIG_INFO_COLOR
-#define NRFX_TWIM_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_TWIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_TWIM_CONFIG_DEBUG_COLOR
-#define NRFX_TWIM_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_TWIS_ENABLED - nrfx_twis - TWIS peripheral driver.
-//==========================================================
-#ifndef NRFX_TWIS_ENABLED
-#define NRFX_TWIS_ENABLED 0
-#endif
-// NRFX_TWIS0_ENABLED - Enables TWIS0 instance.
-
-
-#ifndef NRFX_TWIS0_ENABLED
-#define NRFX_TWIS0_ENABLED 0
-#endif
-
-// NRFX_TWIS1_ENABLED - Enables TWIS1 instance.
-
-
-#ifndef NRFX_TWIS1_ENABLED
-#define NRFX_TWIS1_ENABLED 0
-#endif
-
-// NRFX_TWIS2_ENABLED - Enables TWIS2 instance.
-
-
-#ifndef NRFX_TWIS2_ENABLED
-#define NRFX_TWIS2_ENABLED 0
-#endif
-
-// NRFX_TWIS3_ENABLED - Enables TWIS3 instance.
-
-
-#ifndef NRFX_TWIS3_ENABLED
-#define NRFX_TWIS3_ENABLED 0
-#endif
-
-// NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assumes that any instance would be initialized only once.
-
-
-// Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code.
-
-#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY
-#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
-#endif
-
-// NRFX_TWIS_NO_SYNC_MODE - Removes support for synchronous mode.
-
-// Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources.
-
-#ifndef NRFX_TWIS_NO_SYNC_MODE
-#define NRFX_TWIS_NO_SYNC_MODE 0
-#endif
-
-// NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority.
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-// NRFX_TWIS_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED
-#define NRFX_TWIS_CONFIG_LOG_ENABLED 0
-#endif
-// NRFX_TWIS_CONFIG_LOG_LEVEL - Default severity level.
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL
-#define NRFX_TWIS_CONFIG_LOG_LEVEL 3
-#endif
-
-// NRFX_TWIS_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_TWIS_CONFIG_INFO_COLOR
-#define NRFX_TWIS_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_TWIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_TWIS_CONFIG_DEBUG_COLOR
-#define NRFX_TWIS_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_UARTE_ENABLED - nrfx_uarte - UARTE peripheral driver.
-//==========================================================
-#ifndef NRFX_UARTE_ENABLED
-#define NRFX_UARTE_ENABLED 0
-#endif
-// NRFX_UARTE0_ENABLED - Enables UARTE0 instances
-#ifndef NRFX_UARTE0_ENABLED
-#define NRFX_UARTE0_ENABLED 0
-#endif
-
-// NRFX_UARTE1_ENABLED - Enables UARTE1 instance.
-#ifndef NRFX_UARTE1_ENABLED
-#define NRFX_UARTE1_ENABLED 0
-#endif
-
-// NRFX_UARTE2_ENABLED - Enables UARTE2 instance.
-#ifndef NRFX_UARTE2_ENABLED
-#define NRFX_UARTE2_ENABLED 0
-#endif
-
-// NRFX_UARTE3_ENABLED - Enables UARTE3 instance.
-#ifndef NRFX_UARTE3_ENABLED
-#define NRFX_UARTE3_ENABLED 0
-#endif
-
-// NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority.
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-// NRFX_UARTE_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED
-#define NRFX_UARTE_CONFIG_LOG_ENABLED 0
-#endif
-// NRFX_UARTE_CONFIG_LOG_LEVEL - Default severity level.
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL
-#define NRFX_UARTE_CONFIG_LOG_LEVEL 3
-#endif
-
-// NRFX_UARTE_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_UARTE_CONFIG_INFO_COLOR
-#define NRFX_UARTE_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_UARTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_UARTE_CONFIG_DEBUG_COLOR
-#define NRFX_UARTE_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-// NRFX_WDT_ENABLED - nrfx_wdt - WDT peripheral driver.
-//==========================================================
-#ifndef NRFX_WDT_ENABLED
-#define NRFX_WDT_ENABLED 0
-#endif
-// NRFX_WDT0_ENABLED - Enable WDT0 instance.
-
-
-#ifndef NRFX_WDT0_ENABLED
-#define NRFX_WDT0_ENABLED 0
-#endif
-
-// NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver.
-
-// <0=> Include WDT IRQ handling
-// <1=> Remove WDT IRQ handling
-
-#ifndef NRFX_WDT_CONFIG_NO_IRQ
-#define NRFX_WDT_CONFIG_NO_IRQ 0
-#endif
-
-// NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority.
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-// NRFX_WDT_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_WDT_CONFIG_LOG_ENABLED
-#define NRFX_WDT_CONFIG_LOG_ENABLED 0
-#endif
-// NRFX_WDT_CONFIG_LOG_LEVEL - Default severity level.
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef NRFX_WDT_CONFIG_LOG_LEVEL
-#define NRFX_WDT_CONFIG_LOG_LEVEL 3
-#endif
-
-// NRFX_WDT_CONFIG_INFO_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_WDT_CONFIG_INFO_COLOR
-#define NRFX_WDT_CONFIG_INFO_COLOR 0
-#endif
-
-// NRFX_WDT_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRFX_WDT_CONFIG_DEBUG_COLOR
-#define NRFX_WDT_CONFIG_DEBUG_COLOR 0
-#endif
-
-//
-
-//
-
-//
-
-#endif // NRFX_CONFIG_NRF9160_H__
diff --git a/mcu/nrf/common/vendor/templates/nrfx_glue.h b/mcu/nrf/common/vendor/templates/nrfx_glue.h
index 57f46ecb..973d2c06 100644
--- a/mcu/nrf/common/vendor/templates/nrfx_glue.h
+++ b/mcu/nrf/common/vendor/templates/nrfx_glue.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA
+ * Copyright (c) 2017 - 2023, Nordic Semiconductor ASA
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -221,6 +221,40 @@ extern "C" {
*/
#define NRFX_ATOMIC_FETCH_SUB(p_data, value)
+/**
+ * @brief Macro for running compare and swap on an atomic object.
+ *
+ * Value is updated to the new value only if it previously equaled old value.
+ *
+ * @param[in,out] p_data Atomic memory pointer.
+ * @param[in] old_value Expected old value.
+ * @param[in] new_value New value.
+ *
+ * @retval true If value was updated.
+ * @retval false If value was not updated because location was not equal to @p old_value.
+ */
+#define NRFX_ATOMIC_CAS(p_data, old_value, new_value)
+
+/**
+ * @brief Macro for counting leading zeros.
+ *
+ * @param[in] value A word value.
+ *
+ * @return Number of leading 0-bits in @p value, starting at the most significant bit position.
+ * If x is 0, the result is undefined.
+ */
+#define NRFX_CLZ(value)
+
+/**
+ * @brief Macro for counting trailing zeros.
+ *
+ * @param[in] value A word value.
+ *
+ * @return Number of trailing 0-bits in @p value, starting at the least significant bit position.
+ * If x is 0, the result is undefined.
+ */
+#define NRFX_CTZ(value)
+
//------------------------------------------------------------------------------
/**
@@ -242,6 +276,33 @@ extern "C" {
//------------------------------------------------------------------------------
+/**
+ * @brief Macro for writing back cache lines associated with the specified buffer.
+ *
+ * @param[in] p_buffer Pointer to the buffer.
+ * @param[in] size Size of the buffer.
+ */
+#define NRFY_CACHE_WB(p_buffer, size)
+
+/**
+ * @brief Macro for invalidating cache lines associated with the specified buffer.
+ *
+ * @param[in] p_buffer Pointer to the buffer.
+ * @param[in] size Size of the buffer.
+ */
+#define NRFY_CACHE_INV(p_buffer, size)
+
+/**
+ * @brief Macro for writing back and invalidating cache lines associated with
+ * the specified buffer.
+ *
+ * @param[in] p_buffer Pointer to the buffer.
+ * @param[in] size Size of the buffer.
+ */
+#define NRFY_CACHE_WBINV(p_buffer, size)
+
+//------------------------------------------------------------------------------
+
/** @brief Bitmask that defines DPPI channels that are reserved for use outside of the nrfx library. */
#define NRFX_DPPI_CHANNELS_USED 0
diff --git a/mcu/nrf/makefile b/mcu/nrf/makefile
index 8fb83080..354418b1 100644
--- a/mcu/nrf/makefile
+++ b/mcu/nrf/makefile
@@ -19,16 +19,12 @@ INCLUDES += -I$(MCU_PATH)$(MCU_FAMILY)/common/
-include $(MCU_PREFIX)hal/makefile
# Build common HAL drivers for nrf-family
-ifeq ($(HAL_SPI), yes)
-SRCS += $(NRF_FAMILY_HAL_PREFIX)spi.c
-endif
-
-ifeq ($(HAL_BUTTON), yes)
-SRCS += $(NRF_FAMILY_HAL_PREFIX)button.c
+ifeq ($(HAL_GPIO), yes)
+SRCS += $(NRF_FAMILY_HAL_PREFIX)gpio.c
endif
-ifeq ($(HAL_LED), yes)
-SRCS += $(NRF_FAMILY_HAL_PREFIX)led.c
+ifeq ($(HAL_SPI), yes)
+SRCS += $(NRF_FAMILY_HAL_PREFIX)spi.c
endif
ifeq ($(HAL_PERSISTENT_MEMORY), yes)
@@ -38,5 +34,4 @@ endif
ifeq ($(HAL_HW_DELAY), yes)
SRCS += $(NRF_FAMILY_HAL_PREFIX)hw_delay.c
endif
-SRCS += $(NRF_FAMILY_HAL_PREFIX)ds.c \
- $(NRF_FAMILY_HAL_PREFIX)hal.c
\ No newline at end of file
+SRCS += $(NRF_FAMILY_HAL_PREFIX)hal.c
diff --git a/mcu/nrf/nrf52/hal/radio/radio_power_table_nrf52840_4dBm.h b/mcu/nrf/nrf52/hal/radio/radio_power_table_nrf52840_4dBm.h
index 58f221ac..32250f9d 100644
--- a/mcu/nrf/nrf52/hal/radio/radio_power_table_nrf52840_4dBm.h
+++ b/mcu/nrf/nrf52/hal/radio/radio_power_table_nrf52840_4dBm.h
@@ -13,7 +13,7 @@
const app_lib_radio_cfg_power_t power_table_nrf52840_4dBm =
{
.rx_current = 46, // 4.6 mA RX current
- .rx_gain_dbm = 0, // 0 dBm RX gain
+ .rx_gain_db = 0, // 0 dB RX gain
.power_count = 8, // 8 power levels
.powers =
{
diff --git a/mcu/nrf/nrf52/hal/usart.c b/mcu/nrf/nrf52/hal/usart.c
index 5a3234e5..a891f3fd 100644
--- a/mcu/nrf/nrf52/hal/usart.c
+++ b/mcu/nrf/nrf52/hal/usart.c
@@ -43,13 +43,6 @@ void __attribute__((__interrupt__)) UART0_IRQHandler(void);
bool Usart_init(uint32_t baudrate, uart_flow_control_e flow_control)
{
bool ret;
- //uart_tx_pin
- nrf_gpio_cfg_default(BOARD_USART_TX_PIN);
- nrf_gpio_pin_set(BOARD_USART_TX_PIN);
-
- //uart_rx_pin
- nrf_gpio_cfg_default(BOARD_USART_RX_PIN);
- nrf_gpio_pin_set(BOARD_USART_RX_PIN);
/* Module variables */
m_enabled = false;
@@ -58,6 +51,11 @@ bool Usart_init(uint32_t baudrate, uart_flow_control_e flow_control)
m_tx_active = false;
/* GPIO init */
+ nrf_gpio_cfg_default(BOARD_USART_TX_PIN);
+ nrf_gpio_pin_set(BOARD_USART_TX_PIN);
+ nrf_gpio_cfg_default(BOARD_USART_RX_PIN);
+ nrf_gpio_pin_set(BOARD_USART_RX_PIN);
+
NRF_UART0->PSELTXD = BOARD_USART_TX_PIN;
NRF_UART0->PSELRXD = BOARD_USART_RX_PIN;
NRF_UART0->TASKS_STOPTX = 1;
@@ -324,9 +322,8 @@ static void set_flow_control(bool hw)
/* No parity, no HW flow control */
NRF_UART0->CONFIG = 0;
- // Deactivate HAL_USART_CTS_PIN
+ // Deactivate CTS & RTS pins
nrf_gpio_cfg_default(BOARD_USART_CTS_PIN);
- // Deactivate HAL_USART_RTS_PIN
nrf_gpio_cfg_default(BOARD_USART_RTS_PIN);
}
}
diff --git a/mcu/nrf/nrf52/hal/usart_dma.c b/mcu/nrf/nrf52/hal/usart_dma.c
index 18222387..ca821ad0 100644
--- a/mcu/nrf/nrf52/hal/usart_dma.c
+++ b/mcu/nrf/nrf52/hal/usart_dma.c
@@ -68,13 +68,6 @@ void __attribute__((__interrupt__)) TIMER1_IRQHandler(void);
bool Usart_init(uint32_t baudrate, uart_flow_control_e flow_control)
{
bool ret;
- //uart_tx_pin
- nrf_gpio_cfg_default(BOARD_USART_TX_PIN);
- nrf_gpio_pin_set(BOARD_USART_TX_PIN);
-
- //uart_rx_pin
- nrf_gpio_cfg_default(BOARD_USART_RX_PIN);
- nrf_gpio_pin_set(BOARD_USART_RX_PIN);
/* Module variables */
m_enabled = 0;
@@ -82,6 +75,11 @@ bool Usart_init(uint32_t baudrate, uart_flow_control_e flow_control)
m_rx_callback = NULL;
/* GPIO init */
+ nrf_gpio_cfg_default(BOARD_USART_TX_PIN);
+ nrf_gpio_pin_set(BOARD_USART_TX_PIN);
+ nrf_gpio_cfg_default(BOARD_USART_RX_PIN);
+ nrf_gpio_pin_set(BOARD_USART_RX_PIN);
+
NRF_UARTE0->PSEL.TXD = BOARD_USART_TX_PIN;
NRF_UARTE0->PSEL.RXD = BOARD_USART_RX_PIN;
NRF_UARTE0->TASKS_STOPTX = 1;
@@ -92,11 +90,9 @@ bool Usart_init(uint32_t baudrate, uart_flow_control_e flow_control)
//uart_cts_pin
nrf_gpio_cfg_default(BOARD_USART_CTS_PIN);
nrf_gpio_pin_set(BOARD_USART_CTS_PIN);
-
//uart_rts_pin
nrf_gpio_cfg_default(BOARD_USART_RTS_PIN);
nrf_gpio_pin_set(BOARD_USART_RTS_PIN);
-
/* Set flow control */
set_flow_control(flow_control == UART_FLOW_CONTROL_HW);
#endif
@@ -281,7 +277,6 @@ void Usart_enableReceiver(serial_rx_callback_f rx_callback)
m_rx_callback = rx_callback;
if (m_rx_callback)
{
- /* Enable interrupt */
// Enable RX input
nrf_gpio_cfg(BOARD_USART_RX_PIN,
NRF_GPIO_PIN_DIR_INPUT,
@@ -289,12 +284,9 @@ void Usart_enableReceiver(serial_rx_callback_f rx_callback)
NRF_GPIO_PIN_NOPULL,
NRF_GPIO_PIN_S0S1,
NRF_GPIO_PIN_SENSE_LOW);
-
-
}
else
{
- /* Disable interrupt */
// Disable RX input: note autopowering uart will not work either
nrf_gpio_cfg_default(BOARD_USART_RX_PIN);
}
@@ -435,9 +427,8 @@ static void set_flow_control(bool hw)
/* No parity, no HW flow control */
NRF_UARTE0->CONFIG = 0;
- // Deactivate HAL_USART_CTS_PIN
+ // Deactivate CTS & RTS pins
nrf_gpio_cfg_default(BOARD_USART_CTS_PIN);
- // Deactivate HAL_USART_RTS_PIN
nrf_gpio_cfg_default(BOARD_USART_RTS_PIN);
}
}
diff --git a/mcu/nrf/nrf52/ini_files/nrf52832_app.ini b/mcu/nrf/nrf52/ini_files/nrf52832_app.ini
index dc0e9fd4..ac8cea65 100644
--- a/mcu/nrf/nrf52/ini_files/nrf52832_app.ini
+++ b/mcu/nrf/nrf52/ini_files/nrf52832_app.ini
@@ -19,7 +19,7 @@
; bit 0 : store version numbers in this area (must be 1 for application area and 0 for others
; except if you know what you are doing)
; bit 1 : memory area is located in external flash
-; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user
+; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user, 6:modemfw
[area:application]
id = APP_AREA_ID ; Area ID, different for each application
diff --git a/mcu/nrf/nrf52/ini_files/nrf52832_wp.ini b/mcu/nrf/nrf52/ini_files/nrf52832_wp.ini
index 679b3ae3..281ba951 100644
--- a/mcu/nrf/nrf52/ini_files/nrf52832_wp.ini
+++ b/mcu/nrf/nrf52/ini_files/nrf52832_wp.ini
@@ -22,7 +22,7 @@ eraseblock = 4096 ; Size of individually erasable block, in bytes: 4 kB
; Flags definition:
; bit 0 : store version numbers in this area
; bit 1 : memory area is located in external flash
-; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user
+; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user, 6:modemfw
[area:bootloader]
id = 0x10000103 ; Area ID: HWM_NRF52832_SP_2 | 0x10000100
diff --git a/mcu/nrf/nrf52/ini_files/nrf52833_app.ini b/mcu/nrf/nrf52/ini_files/nrf52833_app.ini
index dc0e9fd4..ac8cea65 100644
--- a/mcu/nrf/nrf52/ini_files/nrf52833_app.ini
+++ b/mcu/nrf/nrf52/ini_files/nrf52833_app.ini
@@ -19,7 +19,7 @@
; bit 0 : store version numbers in this area (must be 1 for application area and 0 for others
; except if you know what you are doing)
; bit 1 : memory area is located in external flash
-; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user
+; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user, 6:modemfw
[area:application]
id = APP_AREA_ID ; Area ID, different for each application
diff --git a/mcu/nrf/nrf52/ini_files/nrf52833_wp.ini b/mcu/nrf/nrf52/ini_files/nrf52833_wp.ini
index d4821d96..d6803af5 100644
--- a/mcu/nrf/nrf52/ini_files/nrf52833_wp.ini
+++ b/mcu/nrf/nrf52/ini_files/nrf52833_wp.ini
@@ -22,7 +22,7 @@ eraseblock = 4096 ; Size of individually erasable block, in bytes: 4 kB
; Flags definition:
; bit 0 : store version numbers in this area
; bit 1 : memory area is located in external flash
-; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user
+; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user, 6:modemfw
[area:bootloader]
id = 0x10000109 ; Area ID: HWM_NRF52833 | 0x10000100
diff --git a/mcu/nrf/nrf52/ini_files/nrf52840_app.ini b/mcu/nrf/nrf52/ini_files/nrf52840_app.ini
index 62b28680..a810bf7b 100644
--- a/mcu/nrf/nrf52/ini_files/nrf52840_app.ini
+++ b/mcu/nrf/nrf52/ini_files/nrf52840_app.ini
@@ -19,7 +19,7 @@
; bit 0 : store version numbers in this area (must be 1 for application area and 0 for others
; except if you know what you are doing)
; bit 1 : memory area is located in external flash
-; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user
+; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user, 6:modemfw
[area:application]
id = APP_AREA_ID ; Area ID, different for each application
diff --git a/mcu/nrf/nrf52/ini_files/nrf52840_wp.ini b/mcu/nrf/nrf52/ini_files/nrf52840_wp.ini
index 003bb7a9..9bbe8b31 100644
--- a/mcu/nrf/nrf52/ini_files/nrf52840_wp.ini
+++ b/mcu/nrf/nrf52/ini_files/nrf52840_wp.ini
@@ -22,7 +22,7 @@ eraseblock = 4096 ; Size of individually erasable block, in bytes: 4 kB
; Flags definition:
; bit 0 : store version numbers in this area
; bit 1 : memory area is located in external flash
-; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user
+; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user, 6:modemfw
[area:bootloader]
id = 0x10000106 ; Area ID: HWM_NRF52840 | 0x10000100
diff --git a/mcu/nrf/nrf52/linker/gcc_bl_nrf52832.ld b/mcu/nrf/nrf52/linker/gcc_bl_nrf52832.ld
index dccac852..3c4934a2 100644
--- a/mcu/nrf/nrf52/linker/gcc_bl_nrf52832.ld
+++ b/mcu/nrf/nrf52/linker/gcc_bl_nrf52832.ld
@@ -58,6 +58,7 @@ SECTIONS
*scratchpad.*o*(.data* .data)
*internal_flash*.*o*(.data* .data)
*external_flash*.*o*(.data* .data)
+ *debug_flow*.*o*(.data* .data)
/* Customer specific external flash driver must be located in
* board/board_name/bootloader folder.
*/
@@ -73,6 +74,7 @@ SECTIONS
*scratchpad.*o*(.bss.* .bss)
*internal_flash*.*o*(.bss* .bss)
*external_flash*.*o*(.bss* .bss)
+ *debug_flow*.*o*(.bss* .bss)
/* Customer specific external flash driver must be located in
* board/board_name/bootloader folder
*/
diff --git a/mcu/nrf/nrf52/linker/gcc_bl_nrf52833.ld b/mcu/nrf/nrf52/linker/gcc_bl_nrf52833.ld
index fadf3002..a473bc26 100644
--- a/mcu/nrf/nrf52/linker/gcc_bl_nrf52833.ld
+++ b/mcu/nrf/nrf52/linker/gcc_bl_nrf52833.ld
@@ -58,6 +58,7 @@ SECTIONS
*scratchpad.*o*(.data* .data)
*internal_flash*.*o*(.data* .data)
*external_flash*.*o*(.data* .data)
+ *debug_flow*.*o*(.data* .data)
/* Customer specific external flash driver must be located in
* board/board_name/bootloader folder.
*/
@@ -73,6 +74,7 @@ SECTIONS
*scratchpad.*o*(.bss.* .bss)
*internal_flash*.*o*(.bss* .bss)
*external_flash*.*o*(.bss* .bss)
+ *debug_flow*.*o*(.bss* .bss)
/* Customer specific external flash driver must be located in
* board/board_name/bootloader folder
*/
diff --git a/mcu/nrf/nrf52/linker/gcc_bl_nrf52840.ld b/mcu/nrf/nrf52/linker/gcc_bl_nrf52840.ld
index d51e2885..641bbab9 100644
--- a/mcu/nrf/nrf52/linker/gcc_bl_nrf52840.ld
+++ b/mcu/nrf/nrf52/linker/gcc_bl_nrf52840.ld
@@ -58,6 +58,7 @@ SECTIONS
*scratchpad.*o*(.data* .data)
*internal_flash*.*o*(.data* .data)
*external_flash*.*o*(.data* .data)
+ *debug_flow*.*o*(.data* .data)
/* Customer specific external flash driver must be located in
* board/board_name/bootloader folder.
*/
@@ -73,6 +74,7 @@ SECTIONS
*scratchpad.*o*(.bss.* .bss)
*internal_flash*.*o*(.bss* .bss)
*external_flash*.*o*(.bss* .bss)
+ *debug_flow*.*o*(.bss* .bss)
/* Customer specific external flash driver must be located in
* board/board_name/bootloader folder
*/
diff --git a/mcu/nrf/nrf91/config.mk b/mcu/nrf/nrf91/config.mk
index 8e3de50a..15b7d29a 100644
--- a/mcu/nrf/nrf91/config.mk
+++ b/mcu/nrf/nrf91/config.mk
@@ -12,12 +12,18 @@ mac_profile?=dect_nr_19_ghz
radio?=none
ifeq ($(MCU_SUB),60)
# Hardware magic used for this architecture
- HW_MAGIC=12
+ HW_MAGIC=0F
HW_VARIANT_ID=12
+else ifeq ($(MCU_SUB),61)
+ # Hardware magic used for this architecture
+ HW_MAGIC=12
+ HW_VARIANT_ID=18
else
- $(error "Invalid MCU_SUB for nrf91! $(MCU_SUB) only 60 supported")
+ $(error "Invalid MCU_SUB for nrf91! $(MCU_SUB) only 60 and 61 supported")
endif
+modemfw_area_id=0x000004$(HW_MAGIC)
+modemfw_name=firmware.update.image.cbor
# Add custom flags
# Remove the -Wunused-parameter flag added by -Wextra as some cortex M4 header do not respect it
CFLAGS += -Wno-unused-parameter
diff --git a/mcu/nrf/nrf91/hal/usart_dma.c b/mcu/nrf/nrf91/hal/usart_dma.c
index b993ec03..d03c1790 100644
--- a/mcu/nrf/nrf91/hal/usart_dma.c
+++ b/mcu/nrf/nrf91/hal/usart_dma.c
@@ -68,13 +68,6 @@ void __attribute__((__interrupt__)) TIMER1_IRQHandler(void);
bool Usart_init(uint32_t baudrate, uart_flow_control_e flow_control)
{
bool ret;
- //uart_tx_pin
- nrf_gpio_cfg_default(BOARD_USART_TX_PIN);
- nrf_gpio_pin_set(BOARD_USART_TX_PIN);
-
- //uart_rx_pin
- nrf_gpio_cfg_default(BOARD_USART_RX_PIN);
- nrf_gpio_pin_set(BOARD_USART_RX_PIN);
/* Module variables */
m_enabled = 0;
@@ -82,6 +75,11 @@ bool Usart_init(uint32_t baudrate, uart_flow_control_e flow_control)
m_rx_callback = NULL;
/* GPIO init */
+ nrf_gpio_cfg_default(BOARD_USART_TX_PIN);
+ nrf_gpio_pin_set(BOARD_USART_TX_PIN);
+ nrf_gpio_cfg_default(BOARD_USART_RX_PIN);
+ nrf_gpio_pin_set(BOARD_USART_RX_PIN);
+
NRF_UARTE0->PSEL.TXD = BOARD_USART_TX_PIN;
NRF_UARTE0->PSEL.RXD = BOARD_USART_RX_PIN;
NRF_UARTE0->TASKS_STOPTX = 1;
@@ -89,14 +87,10 @@ bool Usart_init(uint32_t baudrate, uart_flow_control_e flow_control)
NRF_UARTE0->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
#if defined(BOARD_USART_CTS_PIN) && defined (BOARD_USART_RTS_PIN)
- //uart_cts_pin
nrf_gpio_cfg_default(BOARD_USART_CTS_PIN);
nrf_gpio_pin_set(BOARD_USART_CTS_PIN);
-
- //uart_rts_pin
nrf_gpio_cfg_default(BOARD_USART_RTS_PIN);
nrf_gpio_pin_set(BOARD_USART_RTS_PIN);
-
/* Set flow control */
set_flow_control(flow_control == UART_FLOW_CONTROL_HW);
#endif
@@ -281,7 +275,6 @@ void Usart_enableReceiver(serial_rx_callback_f rx_callback)
m_rx_callback = rx_callback;
if (m_rx_callback)
{
- /* Enable interrupt */
// Enable RX input
nrf_gpio_cfg(BOARD_USART_RX_PIN,
NRF_GPIO_PIN_DIR_INPUT,
@@ -289,12 +282,9 @@ void Usart_enableReceiver(serial_rx_callback_f rx_callback)
NRF_GPIO_PIN_NOPULL,
NRF_GPIO_PIN_S0S1,
NRF_GPIO_PIN_SENSE_LOW);
-
-
}
else
{
- /* Disable interrupt */
// Disable RX input: note autopowering uart will not work either
nrf_gpio_cfg_default(BOARD_USART_RX_PIN);
}
@@ -435,9 +425,8 @@ static void set_flow_control(bool hw)
/* No parity, no HW flow control */
NRF_UARTE0->CONFIG = 0;
- // Deactivate HAL_USART_CTS_PIN
+ // Deactivate CTS & RTS pins
nrf_gpio_cfg_default(BOARD_USART_CTS_PIN);
- // Deactivate HAL_USART_RTS_PIN
nrf_gpio_cfg_default(BOARD_USART_RTS_PIN);
}
}
diff --git a/mcu/nrf/nrf91/ini_files/nrf9160_app.ini b/mcu/nrf/nrf91/ini_files/nrf9160_app.ini
index bff4b093..341adac3 100644
--- a/mcu/nrf/nrf91/ini_files/nrf9160_app.ini
+++ b/mcu/nrf/nrf91/ini_files/nrf9160_app.ini
@@ -19,7 +19,7 @@
; bit 0 : store version numbers in this area (must be 1 for application area and 0 for others
; except if you know what you are doing)
; bit 1 : memory area is located in external flash
-; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user
+; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user, 6:modemfw
[area:application]
id = APP_AREA_ID ; Area ID, different for each application
diff --git a/mcu/nrf/nrf91/ini_files/nrf9160_wp.ini b/mcu/nrf/nrf91/ini_files/nrf9160_wp.ini
index 5e95639c..6f1ce1fe 100644
--- a/mcu/nrf/nrf91/ini_files/nrf9160_wp.ini
+++ b/mcu/nrf/nrf91/ini_files/nrf9160_wp.ini
@@ -22,23 +22,35 @@ eraseblock = 4096 ; Size of individually erasable block, in bytes: 4 kB
; Flags definition:
; bit 0 : store version numbers in this area
; bit 1 : memory area is located in external flash
-; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user
+; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user, 6:modemfw
[area:bootloader]
-id = 0x1000010F ; Area ID: HWM_NRF9160 | 0x10000100
+id = 0x10000112 ; Area ID: HW_VARIANT_ID=0x12 | 0x10000100
address = 0x00000000 ; Start address: beginning of Flash
length = 32768 ; Length in bytes: 32 kB
flags = 0x00000000 ; Don't store version; internal flash; bootloader
settings = 0x00007c00 ; Offset of bootloader settings from addr. (areas, keys)
[area:firmware]
-id = STACK_AREA_ID ; Area ID: HWM_NRF9160 | 0x00000100
+id = STACK_AREA_ID ; Area ID: HW_MAGIC=0x0f | 0x00000100
address = 0x00008000 ; Start address: right after bootloader
length = 245760 ; Length in bytes: 240 kB
flags = 0x00000005 ; Store version; internal flash; stack
[area:persistent]
-id = 0x2000000F ; Area ID: HWM_NRF9160 | 0x20000000
+id = 0x20000012 ; Area ID: HW_VARIANT_ID=0x12 | 0x20000000
address = 0x000fe000 ; Start address: 8 kB before end of Flash
length = 8192 ; Length in bytes: 8 kB
flags = 0x0000000C ; Don't store version; internal flash; persistent
+
+[area:scratchpad]
+id = 0x00000212 ; Area ID: HW_VARIANT_ID=0x12 | 0x00000200
+address = 0x00000000 ; Start address: at the start of ext flash
+length = 2097152 ; Length in bytes: 2 MB
+flags = 0x00000012 ; Don't store version; external flash; scratchpad
+
+[area:modemfw]
+id = 0x0000040F ; Area ID: HW_VARIANT_ID=0x0F | 0x00000400
+address = 0xFFFFFFFF ; Start address: N/A
+length = 0 ; Length in bytes: 0 MB
+flags = 0x0000001A ; Don't store version; modemfw
diff --git a/mcu/nrf/nrf91/ini_files/nrf9161_app.ini b/mcu/nrf/nrf91/ini_files/nrf9161_app.ini
new file mode 100644
index 00000000..341adac3
--- /dev/null
+++ b/mcu/nrf/nrf91/ini_files/nrf9161_app.ini
@@ -0,0 +1,35 @@
+; Custom Memory areas that can be defined
+;
+; On this platform you can use up to 760 kB of internal memory starting at address 0x40000
+;
+; If you support external memory, you can also define them here with the correct flag.
+;
+; There is room for 8 areas. Wirepas uses 3 of them so 5 other ones can be defined.
+;
+; By default, two areas are defined. One to store application and a smaller one to
+; store persistent application data.
+;
+; To override this file, please copy this file under your application folder and override the
+; INI_FILE_APP variable (from the application config.mk).
+;
+; If your application is supported by multiple platforms, do not forget to have a dedicated
+; file for each of them.
+;
+; Flags definition:
+; bit 0 : store version numbers in this area (must be 1 for application area and 0 for others
+; except if you know what you are doing)
+; bit 1 : memory area is located in external flash
+; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user, 6:modemfw
+
+[area:application]
+id = APP_AREA_ID ; Area ID, different for each application
+address = 0x00044000 ; Start address: right after firmware
+length = 745472 ; Length in bytes: 728 kB, shared with scratchpad
+flags = 0x00000009 ; Store version; internal flash; application
+
+[area:app_persistent]
+id = 0x8AE573BA ; Area ID, same for all apps/platform by default
+address = 0x000FA000 ; Start address: end of app_area - 16 kB
+length = 16384 ; Length in bytes: 16 kB
+flags = 0x00000014 ; internal flash, user
+
diff --git a/mcu/nrf/nrf91/ini_files/nrf9161_platform.ini b/mcu/nrf/nrf91/ini_files/nrf9161_platform.ini
new file mode 100644
index 00000000..aea1f79c
--- /dev/null
+++ b/mcu/nrf/nrf91/ini_files/nrf9161_platform.ini
@@ -0,0 +1,9 @@
+; Platform configuration for genscratchpad.py
+;
+; Comments begin with ";" and are ignored.
+;
+; Nordic Semiconductor nRF9160 with AES crypto library
+
+;
+[platform]
+aes_little_endian = False ; AES CTR endianess
\ No newline at end of file
diff --git a/mcu/nrf/nrf91/ini_files/nrf9161_wp.ini b/mcu/nrf/nrf91/ini_files/nrf9161_wp.ini
new file mode 100644
index 00000000..82c0a90c
--- /dev/null
+++ b/mcu/nrf/nrf91/ini_files/nrf9161_wp.ini
@@ -0,0 +1,56 @@
+; A configuration file for genscratchpad.py
+;
+; Comments begin with ";" and are ignored.
+;
+; Nordic Semiconductor nRF9160 with 1024 kB Flash
+
+; Flash memory information
+[flash]
+length = 1048576 ; Length of Flash in bytes: 1024 kB
+eraseblock = 4096 ; Size of individually erasable block, in bytes: 4 kB
+
+; Memory areas where the bootloader is allowed write
+;
+; The bootloader erases an area completely before writing to it, even if data
+; from scratchpad does not fill the area entirely. It is possible to define
+; overlapping areas, to update only the application code but not its data, for
+; example.
+;
+; There is room for 8 areas. Area IDs where the top
+; bit (bit 31) is zero are reserved for Wirepas use.
+;
+; Flags definition:
+; bit 0 : store version numbers in this area
+; bit 1 : memory area is located in external flash
+; bits 2,3,4 : area type, 0:bootloader, 1:stack, 2:application, 3:persistent, 4:scratchpad, 5:user, 6:modemfw
+
+[area:bootloader]
+id = 0x10000117 ; Area ID: HW_VARIANT_ID=0x17 | 0x10000100
+address = 0x00000000 ; Start address: beginning of Flash
+length = 32768 ; Length in bytes: 32 kB
+flags = 0x00000000 ; Don't store version; internal flash; bootloader
+settings = 0x00007c00 ; Offset of bootloader settings from addr. (areas, keys)
+
+[area:firmware]
+id = STACK_AREA_ID ; Area ID: HW_MAGIC=0x12 | 0x00000100
+address = 0x00008000 ; Start address: right after bootloader
+length = 245760 ; Length in bytes: 240 kB
+flags = 0x00000005 ; Store version; internal flash; stack
+
+[area:persistent]
+id = 0x20000017 ; Area ID: HW_VARIANT_ID=0x17 | 0x20000000
+address = 0x000fe000 ; Start address: 8 kB before end of Flash
+length = 8192 ; Length in bytes: 8 kB
+flags = 0x0000000C ; Don't store version; internal flash; persistent
+
+[area:scratchpad]
+id = 0x00000217 ; Area ID: HW_VARIANT_ID=0x17 | 0x00000200
+address = 0x00000000 ; Start address: at the start of ext flash
+length = 2097152 ; Length in bytes: 2 MB
+flags = 0x00000012 ; Don't store version; external flash; scratchpad
+
+[area:modemfw]
+id = 0x00000412 ; Area ID: HW_MAGIC_ID=0x12 | 0x00000400
+address = 0xFFFFFFFF ; Start address: N/A
+length = 0 ; Length in bytes: 0 MB
+flags = 0x0000001A ; Don't store version; modemfw
diff --git a/mcu/nrf/nrf91/linker/gcc_app_nrf9161.ld b/mcu/nrf/nrf91/linker/gcc_app_nrf9161.ld
new file mode 100644
index 00000000..edf242d6
--- /dev/null
+++ b/mcu/nrf/nrf91/linker/gcc_app_nrf9161.ld
@@ -0,0 +1,109 @@
+/* Copyright 2021 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+
+SEARCH_DIR(.)
+
+/* Flash is 1024 kB and RAM is 256 kB
+ * - 256 kB of Flash can be used by the app
+ * - 188 kB (minus 8 bytes) of RAM can be used by the app
+ */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00044000, LENGTH = 256K
+ RAM (rwx) : ORIGIN = 0x20018400, LENGTH = 155K - 8
+ INVALID (rwx) : ORIGIN = 0xFFFFFFFF, LENGTH = 0 /* Sanity check */
+}
+
+SECTIONS
+{
+ .text :
+ {
+ __text_start__ = .;
+ KEEP(*(.entrypoint))
+ KEEP(*(.app_header))
+ *(.text.*)
+ *(.text)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.vfp11_veneer)
+ *(.v4_bx)
+ *(.rodata.*)
+ *(.rodata)
+ *(.rodata1)
+ . = ALIGN(8);
+ __text_end__ = .;
+ } >FLASH
+
+ __data_src_start__ = .;
+
+ .rtt (NOLOAD):
+ {
+ /* Force placing _SEGGER_RTT control block here, if RTT tracing is on */
+ *(.rtt_cb_section)
+ . = ALIGN(8);
+ } >RAM
+
+ .data :
+ {
+ __data_start__ = .;
+ *(.ramtext)
+ *(.data.*)
+ *(.data)
+ *(.data1)
+ . = ALIGN(8);
+ __data_end__ = .;
+ } >RAM AT >FLASH
+
+ __rom_end__ = __data_src_start__ + SIZEOF(.data);
+
+ /* Total size includes persistent data, when implemented */
+ __total_size_bytes__ = __rom_end__ - __text_start__;
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss.*)
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(8);
+ __bss_end__ = .;
+ } >RAM
+
+ /* Symbols for the RAM */
+ __ram_start__ = ORIGIN(RAM);
+ __ram_end__ = ORIGIN(RAM) + LENGTH(RAM);
+
+.invalid :
+ {
+ *(.init)
+ *(.fini)
+ *(.preinit_array)
+ *(.init_array)
+ *(.fini_array)
+ *(.ctors)
+ *(.dtors)
+ *(.jcr)
+ *(.eh_frame)
+ *(.eh_frame_hdr)
+ *(.heap*)
+ *(.tbss)
+ *(.tdata)
+ *(.tdata1)
+ *(.got)
+ *(.got.plt)
+ *(.igot.plt)
+ *(.iplt)
+ *(.rel.dyn)
+ *(.rel.iplt)
+ } >INVALID /* Linking fails if any of these sections have contents. */
+
+ /* C++ exception unwinding information is silently discarded. */
+ /DISCARD/ :
+ {
+ *(.ARM.extab)
+ *(.ARM.exidx)
+ }
+}
diff --git a/mcu/nrf/nrf91/linker/gcc_bl_nrf9160.ld b/mcu/nrf/nrf91/linker/gcc_bl_nrf9160.ld
index 245321c3..beb63fd3 100644
--- a/mcu/nrf/nrf91/linker/gcc_bl_nrf9160.ld
+++ b/mcu/nrf/nrf91/linker/gcc_bl_nrf9160.ld
@@ -58,6 +58,7 @@ SECTIONS
*scratchpad.*o*(.data* .data)
*internal_flash*.*o*(.data* .data)
*external_flash*.*o*(.data* .data)
+ *debug_flow*.*o*(.data* .data)
/* Customer specific external flash driver must be located in
* board/board_name/bootloader folder.
*/
@@ -73,6 +74,7 @@ SECTIONS
*scratchpad.*o*(.bss.* .bss)
*internal_flash*.*o*(.bss* .bss)
*external_flash*.*o*(.bss* .bss)
+ *debug_flow*.*o*(.bss* .bss)
/* Customer specific external flash driver must be located in
* board/board_name/bootloader folder
*/
diff --git a/mcu/nrf/nrf91/linker/gcc_bl_nrf9161.ld b/mcu/nrf/nrf91/linker/gcc_bl_nrf9161.ld
new file mode 100644
index 00000000..beb63fd3
--- /dev/null
+++ b/mcu/nrf/nrf91/linker/gcc_bl_nrf9161.ld
@@ -0,0 +1,159 @@
+/* Copyright 2021 Wirepas Ltd. All Rights Reserved.
+ *
+ * See file LICENSE.txt for full license details.
+ *
+ */
+
+/* Linker script for Wirepas Connectivity bootloader on nRF9160
+ *
+ * This file is for the 1024 kB FLASH, 256 kB RAM variant
+ *
+ * Flash is 1024 kB, which is split into
+ * - Bootloader executable code (BOOTLOADER)
+ * - Bootloader config: memory areas, auth. and encryption keys (BLCONFIG)
+ *
+ */
+
+SEARCH_DIR(.)
+
+MEMORY
+{
+ BOOTLOADER (rx) : ORIGIN = 0x00000000, LENGTH = 32K - 1K
+ BLCONFIG (rx) : ORIGIN = 0x00000000 + 31K, LENGTH = 1K
+ BL_STATIC (rwx) : ORIGIN = 0x20000000, LENGTH = 1k
+ RAM (rwx) : ORIGIN = 0x20000000 + 1k, LENGTH = 255K - 24
+ INVALID (rwx) : ORIGIN = 0xFFFFFFFF, LENGTH = 0
+}
+
+ENTRY(__startup__)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.Vectors))
+ __bl_version__ = .;
+ KEEP(*(.BootloaderVersion))
+ *(.romtext)
+ *(.text.*)
+ *(.text)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.vfp11_veneer)
+ *(.v4_bx)
+ *(.rodata.*)
+ *(.rodata)
+ *(.rodata1)
+ *(.crc_lut)
+ . = ALIGN(8);
+ } >BOOTLOADER
+
+ __etext = .;
+ __data_src_start__ = .;
+
+ .datastatic :
+ {
+ __datastatic_start__ = .;
+ *memoryarea.*o*(.data* .data)
+ *scratchpad.*o*(.data* .data)
+ *internal_flash*.*o*(.data* .data)
+ *external_flash*.*o*(.data* .data)
+ *debug_flow*.*o*(.data* .data)
+ /* Customer specific external flash driver must be located in
+ * board/board_name/bootloader folder.
+ */
+ *board/*/bootloader/*.*o*(.data* .data)
+ . = ALIGN(8);
+ __datastatic_end__ = .;
+ } >BL_STATIC AT >BOOTLOADER
+
+ .bssstatic :
+ {
+ __bssstatic_start__ = .;
+ *memoryarea.*o*(.bss.* .bss)
+ *scratchpad.*o*(.bss.* .bss)
+ *internal_flash*.*o*(.bss* .bss)
+ *external_flash*.*o*(.bss* .bss)
+ *debug_flow*.*o*(.bss* .bss)
+ /* Customer specific external flash driver must be located in
+ * board/board_name/bootloader folder
+ */
+ *board/*/bootloader/*.*o*(.bss* .bss)
+ /* COMMON symbols here as well */
+ *(COMMON)
+ . = ALIGN(8);
+ __bssstatic_end__ = .;
+ } >BL_STATIC
+
+ .data :
+ {
+ __data_start__ = .;
+ *(.ramtext)
+ *(.data.*)
+ *(.data)
+ . = ALIGN(8);
+ __data_end__ = .;
+ } >RAM AT >BOOTLOADER
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss.*)
+ *(.bss)
+ . = ALIGN(8);
+ __bss_end__ = .;
+ } >RAM
+
+ .blconfig :
+ {
+ /* Bootloader configuration (memory areas, keys) */
+ __blconfig_start__ = .;
+ . += LENGTH(BLCONFIG);
+ __blconfig_end__ = .;
+ } >BLCONFIG
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __stack_top__ = ORIGIN(RAM) + LENGTH(RAM);
+
+ .invalid :
+ {
+ *(.init)
+ *(.fini)
+ *(.preinit_array)
+ *(.init_array)
+ *(.fini_array)
+ *(.ctors)
+ *(.dtors)
+ *(.jcr)
+ *(.eh_frame)
+ *(.eh_frame_hdr)
+ *(.heap*)
+ *(.tbss)
+ *(.tdata)
+ *(.tdata1)
+ *(.got)
+ *(.got.plt)
+ *(.igot.plt)
+ *(.iplt)
+ *(.rel.dyn)
+ *(.rel.iplt)
+ } >INVALID /* Linking fails if any of these sections have contents. */
+
+ /* C++ exception unwinding information is silently discarded. */
+ /DISCARD/ :
+ {
+ *(.ARM.extab)
+ *(.ARM.extab.*)
+ *(.ARM.exidx)
+ *(.ARM.exidx.*)
+ }
+}
diff --git a/source/example_apps/battery_voltage_read_app/app.c b/source/example_apps/battery_voltage_read_app/app.c
index 920810cc..cb33776f 100644
--- a/source/example_apps/battery_voltage_read_app/app.c
+++ b/source/example_apps/battery_voltage_read_app/app.c
@@ -131,7 +131,6 @@ static app_lib_data_send_res_e send_voltage_to_wnt(void)
.bytes = &m_tx_buf[0],
.num_bytes = cbor_encoder_get_buffer_size(&m_encoder, &m_tx_buf[0]),
.dest_address = APP_ADDR_ANYSINK,
- .delay = 0,
.tracking_id = APP_LIB_DATA_NO_TRACKING_ID,
.qos = APP_LIB_DATA_QOS_NORMAL,
.flags = APP_LIB_DATA_SEND_FLAG_NONE,
diff --git a/source/example_apps/battery_voltage_read_app/config.mk b/source/example_apps/battery_voltage_read_app/config.mk
index c4167c5a..87385228 100644
--- a/source/example_apps/battery_voltage_read_app/config.mk
+++ b/source/example_apps/battery_voltage_read_app/config.mk
@@ -1,5 +1,5 @@
# Boards compatible with this app
-TARGET_BOARDS := pca10056 pca10100 pca10040 ruuvitag silabs_brd4254a tbsense2 silabs_brd4253a silabs_brd4180b silabs_brd4184a silabs_brd4181b
+TARGET_BOARDS := silabs_brd2703a silabs_brd2601b silabs_brd4187c
#
# Network default settings configuration
#
diff --git a/source/example_apps/ble_scanner/app.c b/source/example_apps/ble_scanner/app.c
deleted file mode 100644
index 625021bb..00000000
--- a/source/example_apps/ble_scanner/app.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/* Copyright 2021 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-/*
- * \file app.c
- * \brief This file is an example for beacon scanner feature
- *
- */
-
-#include "api.h"
-#include "node_configuration.h"
-#include "ble_scanner.h"
-#include "shared_data.h"
-#include "stack_state.h"
-#include "led.h"
-#ifdef DUALMCU_INTERFACE
-#include "dualmcu_lib.h"
-#endif
-
-#include
-#include
-#include
-
-#define DEBUG_LOG_MODULE_NAME "BLE SCANNER"
-#define DEBUG_LOG_MAX_LEVEL LVL_INFO
-#include "debug_log.h"
-
-#define BLE_SCANNER_CONFIG_REQ_EP 13
-#define BLE_SCANNER_CONFIG_REPLY_EP 14
-
-#define BLE_SCANNER_DATA_EP 18
-
-/** Cmd accepted for this app */
-typedef enum
-{
- SCANNER_CMD_DISABLE = 0, //< Disable scanner
- SCANNER_CMD_ENABLE = 1, //< Enable scanner always
- SCANNER_CMD_ENABLE_PERIODIC = 2 //< Enable scanner periodicaly
-} scanner_cmd_e;
-
-typedef struct __attribute__ ((__packed__))
-{
- uint8_t channel; // Same as Ble_scanner_channel_e
-} enable_payload_t;
-
-typedef struct __attribute__ ((__packed__))
-{
- uint16_t period_s;
- uint16_t scan_length_s;
- uint8_t channel; // Same as Ble_scanner_channel_e
-} enable_periodic_payload_t;
-
-/** Application message format */
-typedef struct __attribute__((packed))
-{
- uint32_t id;
- uint8_t cmd_id;
- union
- {
- enable_payload_t enable;
- enable_periodic_payload_t enable_periodic;
- } payload;
-} cmd_t;
-
-/** Response format */
-typedef struct __attribute__((packed))
-{
- uint32_t id;
- uint8_t res;
-} response_t;
-
-static bool ble_scanner_filter(const app_lib_beacon_rx_received_t * packet)
-{
- const uint8_t pattern_enocean[] = {0x4C, 0x2E, 0x00, 0x00, 0x15};
-
- // Filter enocean switches as an example
- return packet->length > 5 &&
- !memcmp(pattern_enocean, packet->payload, sizeof(pattern_enocean));
-}
-
-static app_lib_data_receive_res_e ble_scanner_configuration_cb(
- const shared_data_item_t * item,
- const app_lib_data_received_t * data)
-{
- Ble_scanner_res_e res;
- cmd_t * cmd_p;
- response_t response;
- Ble_scanner_scanning_config_t conf;
-
- LOG(LVL_INFO, "Message received on config EP");
-
- if (data->num_bytes < 5)
- {
- // Too short to contain id + cmd
- return APP_LIB_DATA_RECEIVE_RES_NOT_FOR_APP;
- }
-
- cmd_p = (cmd_t *) data->bytes;
-
- switch (cmd_p->cmd_id)
- {
- case SCANNER_CMD_DISABLE:
- res = Ble_scanner_stop();
- break;
- case SCANNER_CMD_ENABLE:
- conf.type = BLE_SCANNER_SCANNING_TYPE_ALWAYS;
- conf.channel = cmd_p->payload.enable.channel;
-
- // This is a start command
- res = Ble_scanner_start(&conf);
- LOG(LVL_INFO, "Enable always = %d (channel=%d)",
- res,
- conf.channel);
- break;
- case SCANNER_CMD_ENABLE_PERIODIC:
- conf.type = BLE_SCANNER_SCANNING_TYPE_PERIODIC;
- conf.period_s = cmd_p->payload.enable_periodic.period_s;
- conf.scan_length_s = cmd_p->payload.enable_periodic.scan_length_s;
- conf.channel = cmd_p->payload.enable_periodic.channel;
-
- // This is a start command
- res = Ble_scanner_start(&conf);
- LOG(LVL_INFO, "Enable periodic = %d (%ds every %ds on channel=%d))",
- res,
- conf.scan_length_s,
- conf.period_s,
- conf.channel);
- break;
- default:
- LOG(LVL_DEBUG, "Wrong cmd format");
- return APP_LIB_DATA_RECEIVE_RES_NOT_FOR_APP;
- }
-
- response.id = cmd_p->id;
- response.res = res;
-
- // Send reply
- app_lib_data_to_send_t reply = {
- .bytes = (uint8_t *) &response,
- .num_bytes = sizeof(response),
- .dest_address = APP_ADDR_ANYSINK,
- .qos = APP_LIB_DATA_QOS_NORMAL,
- .src_endpoint = BLE_SCANNER_CONFIG_REPLY_EP,
- .dest_endpoint = BLE_SCANNER_CONFIG_REPLY_EP
- };
-
- // Answer backend with same endpoint
- Shared_Data_sendData(&reply,NULL);
-
- return APP_LIB_DATA_RECEIVE_RES_HANDLED;
-}
-
-/** Filter to receive cmd messages */
-static shared_data_item_t ble_scanner_control =
-{
- .cb = ble_scanner_configuration_cb,
- .filter =
- {
- .mode = SHARED_DATA_NET_MODE_ALL,
- .src_endpoint = BLE_SCANNER_CONFIG_REQ_EP,
- .dest_endpoint = BLE_SCANNER_CONFIG_REQ_EP,
- .multicast_cb = NULL
- }
-};
-
-volatile uint32_t tempo = 0;
-static size_t on_beacon_received(Ble_scanner_beacon_t beacons[],
- size_t beacons_available)
-{
- Led_toggle(0);
-
- // Handle the beacon one by one
- // No packing yet: could be stored in temporary buffer until a
- // full packet is ready
- app_lib_data_to_send_t data = {
- .bytes = (uint8_t *) beacons,
- .num_bytes = sizeof(Ble_scanner_beacon_t) - BLE_SCANNER_MAX_BEACON_SIZE + beacons[0].length,
- .dest_address = APP_ADDR_ANYSINK,
- .qos = APP_LIB_DATA_QOS_NORMAL,
- .src_endpoint = BLE_SCANNER_DATA_EP,
- .dest_endpoint = BLE_SCANNER_DATA_EP
- };
-
- // This is just a demo code so if packet is not transmitted,
- // it is lost
- Shared_Data_sendData(&data,NULL);
-
- return 1;
-}
-
-
-void App_init(const app_global_functions_t * functions)
-{
-#ifdef DUALMCU_INTERFACE
- Dualmcu_lib_init(1000000, false);
-#else
- // Enable log as dualmcu is not enabled
- LOG_INIT();
- // Configure node
- // Basic configuration of the node with a unique node address
- if (configureNodeFromBuildParameters() != APP_RES_OK)
- {
- // Could not configure the node
- // It should not happen except if one of the config value is invalid
- return;
- }
- // Start the stack
- Stack_State_startStack();
-#endif
-
- LOG(LVL_INFO, "Starting BLE Scanner app");
- Led_init();
-
- Ble_scanner_init(ble_scanner_filter, on_beacon_received);
-
- // Register data filter to control the configuration remotely
- Shared_Data_addDataReceivedCb(&ble_scanner_control);
-}
diff --git a/source/example_apps/ble_scanner/backend_scripts/beacon_scanner_config.py b/source/example_apps/ble_scanner/backend_scripts/beacon_scanner_config.py
deleted file mode 100644
index 773d9879..00000000
--- a/source/example_apps/ble_scanner/backend_scripts/beacon_scanner_config.py
+++ /dev/null
@@ -1,81 +0,0 @@
-# Copyright 2021 Wirepas Ltd. All Rights Reserved.
-#
-# See file LICENSE.txt for full license details.
-#
-import argparse
-from wirepas_mqtt_library import WirepasNetworkInterface
-import wirepas_mesh_messaging as wmm
-from struct import pack
-import random
-
-import logging
-
-if __name__ == "__main__":
- parser = argparse.ArgumentParser(fromfile_prefix_chars='@')
- parser.add_argument('--host',
- help="MQTT broker address")
- parser.add_argument('--port', default=8883,
- type=int,
- help="MQTT broker port")
- parser.add_argument('--username', default='mqttmasteruser',
- help="MQTT broker username")
- parser.add_argument('--password',
- help="MQTT broker password")
- parser.add_argument('--insecure',
- dest='insecure',
- action='store_true',
- help="MQTT use unsecured connection")
-
- parser.add_argument('--gateway',
- help="From which gateway to send config",
- required=True)
- parser.add_argument('--sink',
- help="From which sink to send config",
- required=True)
- parser.add_argument('--node',
- help="To which node to send the config",
- required=True)
-
- parser.add_argument("cmd", choices=["disable",
- "enable",
- "periodic"])
- # Param in case of periodic
- parser.add_argument('--period',
- help="How often in s to scan",
- default="360")
- parser.add_argument('--scan_len',
- help="How long to scan for beacons",
- default="60")
-
- args = parser.parse_args()
-
- logging.basicConfig(format='%(levelname)s %(asctime)s %(message)s', level=logging.INFO)
-
- wni = WirepasNetworkInterface(args.host,
- args.port,
- args.username,
- args.password,
- insecure=args.insecure)
-
- try:
- id = random.randint(0, 256) # It could be any 32 bits
- if args.cmd == "disable":
- payload = pack('
-
-#define DEBUG_LOG_MODULE_NAME "BLE_SCANNER_LIB"
-#define DEBUG_LOG_MAX_LEVEL LVL_INFO
-#include "debug_log.h"
-
-/* Is module initialized */
-static bool m_initialized = false;
-
-/* Max number of eeacons to store */
-#define BLE_SCAN_QUEUE_SIZE 16
-
-/* Intermediate buffer to store beacons between radio and task */
-Ble_scanner_beacon_t m_ble_data[BLE_SCAN_QUEUE_SIZE];
-
-/* FIFO management*/
-static uint8_t m_insert_index = 0;
-static uint8_t m_free_rooms = BLE_SCAN_QUEUE_SIZE;
-
-/* Module caller callbacks*/
-static ble_scanner_filter_cb m_app_beacon_filter = NULL;
-static ble_scanner_beacon_received_cb m_beacon_received_cb = NULL;
-
-/* Current config set by caller */
-static Ble_scanner_scanning_config_t m_current_config;
-
-static app_lib_beacon_rx_channels_mask_e get_beacon_rx_channel(Ble_scanner_channel_e channel)
-{
- switch(channel)
- {
- case BLE_SCANNER_CHANNEL_37:
- return APP_LIB_BEACON_RX_CHANNEL_37;
- case BLE_SCANNER_CHANNEL_38:
- return APP_LIB_BEACON_RX_CHANNEL_38;
- case BLE_SCANNER_CHANNEL_39:
- return APP_LIB_BEACON_RX_CHANNEL_39;
- case BLE_SCANNER_CHANNEL_ANY:
- default:
- return APP_LIB_BEACON_RX_CHANNEL_ALL;
- }
-}
-
-static uint32_t process_ble_beacon(void)
-{
- uint8_t index;
- uint8_t beacons_available = 0;
- size_t beacons_to_handle, beacons_handled = 0;
-
- beacons_available = BLE_SCAN_QUEUE_SIZE - m_free_rooms;
- if (beacons_available == 0)
- {
- return APP_SCHEDULER_STOP_TASK;
- }
-
- // Determine start index
- // Protect reading to have m_free_rooms and m_insert_index coherent
- lib_system->enterCriticalSection();
- index = (m_insert_index + m_free_rooms) % BLE_SCAN_QUEUE_SIZE;
- lib_system->exitCriticalSection();
-
- // Notify callback of beacon available
- // To avoid copies, only send beacons that are
- // contiguous in memory
- if (index + beacons_available < BLE_SCAN_QUEUE_SIZE)
- {
- beacons_to_handle = beacons_available;
- }
- else
- {
- beacons_to_handle = BLE_SCAN_QUEUE_SIZE - index;
- }
-
- beacons_handled = m_beacon_received_cb(&m_ble_data[index], beacons_to_handle);
-
- // Protect update to m_free_rooms to avoid races with IRQ as addition is not atomic
- lib_system->enterCriticalSection();
- m_free_rooms += beacons_handled;
- lib_system->exitCriticalSection();
-
- // Shedule task again in case there was still something in queue
- return APP_SCHEDULER_SCHEDULE_ASAP;
-}
-
-static uint32_t toggle_scanner_mode(void)
-{
- // Toogle beacon scanner depending on config and current state
- if (lib_beacon_rx->isScannerStarted())
- {
- if (lib_beacon_rx->stopScanner() != APP_RES_OK)
- {
- // Cannot stop, try again in 1s
- return 1000;
- }
- LOG(LVL_DEBUG, "Scanner stopped");
- return (m_current_config.period_s - m_current_config.scan_length_s) * 1000;
- }
- else
- {
- if (lib_beacon_rx->startScanner(get_beacon_rx_channel(m_current_config.channel)) != APP_RES_OK)
- {
- // Cannot start, try again in 1s
- return 1000;
- }
-
- LOG(LVL_DEBUG, "Scanner started");
- return m_current_config.scan_length_s * 1000;
- }
-}
-
-static void BLEdataReceivedCb(const app_lib_beacon_rx_received_t * packet)
-{
- if (m_app_beacon_filter != NULL && !m_app_beacon_filter(packet))
- {
- /* Packet is filtered by app filtering */
- return;
- }
-
- /* Not filtered out, insert it in the FIFO */
- /* Overriding older entry if needed */
- m_ble_data[m_insert_index].length = packet->length;
- m_ble_data[m_insert_index].type = packet->type;
- m_ble_data[m_insert_index].rssi = packet->rssi;
-
- memcpy(m_ble_data[m_insert_index].data,
- packet->payload,
- packet->length);
-
- m_insert_index = (m_insert_index + 1) % BLE_SCAN_QUEUE_SIZE;
- if (m_free_rooms > 0)
- {
- m_free_rooms--;
- }
-
- App_Scheduler_addTask_execTime(process_ble_beacon,
- APP_SCHEDULER_SCHEDULE_ASAP,
- 500);
-
-}
-
-Ble_scanner_res_e Ble_scanner_init(ble_scanner_filter_cb beacon_filter_cb,
- ble_scanner_beacon_received_cb beacon_received_cb)
-{
- lib_beacon_rx->setBeaconReceivedCb(BLEdataReceivedCb);
- m_app_beacon_filter = beacon_filter_cb;
- m_beacon_received_cb = beacon_received_cb;
-
- m_insert_index = 0;
- m_free_rooms = BLE_SCAN_QUEUE_SIZE;
-
- m_initialized = true;
- return BLE_SCANNER_RES_SUCCESS;
-}
-
-Ble_scanner_res_e Ble_scanner_start(Ble_scanner_scanning_config_t * config)
-{
- if (!m_initialized)
- {
- return BLE_SCANNER_RES_UNINTIALLIZED;
- }
-
- // Check config is valid
- if (config->type == BLE_SCANNER_SCANNING_TYPE_PERIODIC)
- {
- // Check that interval is correct
- if (config->scan_length_s > config->period_s)
- {
- return BLE_SCANNER_RES_INVALID_PARAM;
- }
-
- if (App_Scheduler_addTask_execTime(toggle_scanner_mode,
- APP_SCHEDULER_SCHEDULE_ASAP,
- 100) != APP_SCHEDULER_RES_OK)
- {
- LOG(LVL_ERROR, "Cannot add task to toggle scanner");
- return BLE_SCANNER_RES_INTERNAL_ERROR;
- }
-
- // Save new config
- m_current_config = *config;
-
- // Disable scanner to start
- lib_beacon_rx->stopScanner();
- }
- else
- {
- // Stop task an scanner in case it was already in periodic mode
- App_Scheduler_cancelTask(toggle_scanner_mode);
- lib_beacon_rx->stopScanner();
-
- app_res_e res = lib_beacon_rx->startScanner(get_beacon_rx_channel(m_current_config.channel));
- LOG(LVL_INFO, "Starting scanner %d", res);
- if (res != APP_RES_OK)
- {
- LOG(LVL_ERROR, "Cannot start scanner");
- return BLE_SCANNER_RES_INTERNAL_ERROR;
- }
- }
-
- return BLE_SCANNER_RES_SUCCESS;
-}
-
-Ble_scanner_res_e Ble_scanner_stop()
-{
- if (!m_initialized)
- {
- return BLE_SCANNER_RES_UNINTIALLIZED;
- }
-
- // Cancel task in case it was active
- App_Scheduler_cancelTask(toggle_scanner_mode);
- // Do it in whatever state we were
- lib_beacon_rx->stopScanner();
-
- // Clean our buffer
- m_insert_index = 0;
- m_free_rooms = BLE_SCAN_QUEUE_SIZE;
-
- return BLE_SCANNER_RES_SUCCESS;
-}
-
diff --git a/source/example_apps/ble_scanner/ble_scanner.h b/source/example_apps/ble_scanner/ble_scanner.h
deleted file mode 100644
index 57a8958c..00000000
--- a/source/example_apps/ble_scanner/ble_scanner.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* Copyright 2021 Wirepas Ltd. All Rights Reserved.
- *
- * See file LICENSE.txt for full license details.
- *
- */
-
-/**
- * @file ble_scanner.h
- *
- * Bleutooth Low Energy beacons scanner library.
- */
-
-#ifndef _BLE_SCANNER_H_
-#define _BLE_SCANNER_H_
-
-/** BLE advertising PDU has a maximum length of 37 bytes */
-#define BLE_SCANNER_MAX_BEACON_SIZE 37
-
-typedef enum {
- BLE_SCANNER_RES_SUCCESS = 0, /**< Operation is a success. */
- BLE_SCANNER_RES_UNINTIALLIZED = 1,
- BLE_SCANNER_RES_WRONG_STATE = 2,
- BLE_SCANNER_RES_INVALID_PARAM = 3,
- BLE_SCANNER_RES_INTERNAL_ERROR = 4,
-} Ble_scanner_res_e;
-
-/**
- * BLE beacon received data Data
- */
-typedef struct {
- uint8_t type;
- int8_t rssi;
- uint8_t length;
- uint8_t data[BLE_SCANNER_MAX_BEACON_SIZE];
-} Ble_scanner_beacon_t;
-
-typedef enum {
- BLE_SCANNER_SCANNING_TYPE_ALWAYS = 0,
- BLE_SCANNER_SCANNING_TYPE_PERIODIC = 1
-} Ble_scanner_scanning_type_e;
-
-typedef enum {
- /** Use any advertising channel */
- BLE_SCANNER_CHANNEL_ANY = 0,
- /** Use advertising channel 37 */
- BLE_SCANNER_CHANNEL_37 = 1,
- /** Use advertising channel 38 */
- BLE_SCANNER_CHANNEL_38 = 2,
- /** Use advertising channel 39 */
- BLE_SCANNER_CHANNEL_39 = 3,
- /** Use all advertising channels */
-} Ble_scanner_channel_e;
-
-/**
- * \brief Callback to filter ble beacons received
- * \param packet
- * packet received on radio level
- * \return True to keep it, False to discard
- * \note Called from Radio IRQ context so execution must be short
- */
-typedef bool (*ble_scanner_filter_cb)(const app_lib_beacon_rx_received_t * packet);
-
-/**
- * \brief Callback to be notified when ble beacons are available
- * matching the filter
- * \param beacons
- * Beacons to handle
- * \param beacons_available
- * Number of beacons to handle
- * \return Number of beacons handled from the table (from the start)
- * Unhandled beacons will be offered again to app later (immediatelly)
- * \note Called from task context so execution can be longer (up to 500us)
- */
-typedef size_t (*ble_scanner_beacon_received_cb)(Ble_scanner_beacon_t beacons[],
- size_t beacons_available);
-
-/**
- * @brief Structure to hold a scanning config
- */
-typedef struct
-{
- Ble_scanner_scanning_type_e type; //< Type of scanning
- uint16_t period_s; //< Scanning period in s, only needed if type is periodic
- uint16_t scan_length_s; //< Lenght of a scan in s, only needed if type is periodic, must be < period_s
- Ble_scanner_channel_e channel; //< Channel(s) to use for scanning
-} Ble_scanner_scanning_config_t;
-
-/**
- * \brief Initialize the ble scanner module
- * \param beacon_filter_cb
- * Filter to be used to select the beacons to keep. It is called from
- * ISR and execution must be really short.
- * \param beacon_received_cb
- * Callback called for every beacon that match the filter. It is called
- * asynchronously and execution time can be up to 5OOus
- * \return Result code of the operation
- */
-Ble_scanner_res_e Ble_scanner_init(ble_scanner_filter_cb beacon_filter_cb,
- ble_scanner_beacon_received_cb beacon_received_cb);
-
-
-/**
- * \brief Start the beacon scanner with the specified config
- * \param config
- * The config to use for ble scanning
- * \return Result code of the operation
- */
-Ble_scanner_res_e Ble_scanner_start(Ble_scanner_scanning_config_t * config);
-
-/**
- * \brief Stop the beacon scanner
- * \return Result code of the operation
- */
-Ble_scanner_res_e Ble_scanner_stop();
-
-#endif //_BLE_SCANNER_H_
\ No newline at end of file
diff --git a/source/example_apps/ble_scanner/config.mk b/source/example_apps/ble_scanner/config.mk
deleted file mode 100644
index c677f3c6..00000000
--- a/source/example_apps/ble_scanner/config.mk
+++ /dev/null
@@ -1,27 +0,0 @@
-# Boards compatible with this app
-TARGET_BOARDS := silabs_brd4254a pca10056 promistel_rpi_hat pca10100 ublox_b204 tbsense2 pca10040
-#
-# Network default settings configuration
-#
-
-# If this section is removed, node has to be configured in
-# a different way
-default_network_address ?= 0xefd4a2
-default_network_channel ?= 2
-# !HIGHLY RECOMMENDED! : To enable security keys please un-comment the lines below and fill with a
-# randomly generated authentication & encryption keys (exactly 16 bytes)
-#default_network_cipher_key ?= 0x??,0x??,0x??,0x??,0x??,0x??,0x??,0x??,0x??,0x??,0x??,0x??,0x??,0x??,0x??,0x??
-#default_network_authen_key ?= 0x??,0x??,0x??,0x??,0x??,0x??,0x??,0x??,0x??,0x??,0x??,0x??,0x??,0x??,0x??,0x??
-
-#
-# App specific configuration
-#
-
-# Define a specific application area_id
-app_specific_area_id=0x5bde2a
-
-# App version
-app_major=2
-app_minor=0
-app_maintenance=0
-app_development=0
diff --git a/source/example_apps/ble_scanner/config_dualmcu.mk b/source/example_apps/ble_scanner/config_dualmcu.mk
deleted file mode 100644
index a0e87fe7..00000000
--- a/source/example_apps/ble_scanner/config_dualmcu.mk
+++ /dev/null
@@ -1,8 +0,0 @@
-# Boards compatible with this app
-TARGET_BOARDS := silabs_brd4254a pca10056 promistel_rpi_hat pca10100 ublox_b204 tbsense2 pca10040
-include $(APP_SRCS_PATH)/config.mk
-
-# Target board must be redefined even if same as included base config
-
-# In this alternate config, include dualmcu interface
-dualmcu_interface=yes
diff --git a/source/example_apps/ble_scanner/makefile b/source/example_apps/ble_scanner/makefile
deleted file mode 100644
index 3cb299cd..00000000
--- a/source/example_apps/ble_scanner/makefile
+++ /dev/null
@@ -1,23 +0,0 @@
-# Adding ble scanner module
-SRCS += $(SRCS_PATH)ble_scanner.c
-INCLUDES += -I$(SRCS_PATH)
-
-# Two tasks are needed for the scanner part
-APP_SCHEDULER=yes
-APP_SCHEDULER_TASKS=2
-
-SHARED_DATA=yes
-STACK_STATE_LIB=yes
-
-HAL_LED=yes
-
-ifeq ($(dualmcu_interface), yes)
-# Enable dualmcu with UART and
-# and dma to support high baudrate
-HAL_UART=yes
-UART_USE_DMA=yes
-DUALMCU_LIB=yes
-CFLAGS += -DDUALMCU_INTERFACE
-else
-APP_PRINTING=yes
-endif
diff --git a/source/example_apps/control_node/app.c b/source/example_apps/control_node/app.c
index 5db179b0..feddeaad 100644
--- a/source/example_apps/control_node/app.c
+++ b/source/example_apps/control_node/app.c
@@ -22,7 +22,11 @@
#include "common.h"
#define DEBUG_LOG_MODULE_NAME "NODE APP"
+#ifdef DEBUG_LOG_MAX_LEVEL_APP
+#define DEBUG_LOG_MAX_LEVEL DEBUG_LOG_MAX_LEVEL_APP
+#else
#define DEBUG_LOG_MAX_LEVEL LVL_INFO
+#endif
#include "debug_log.h"
/** \brief This structure defines the application configuration parameters. */
@@ -79,7 +83,6 @@ static void switch_event(uint8_t button_id, button_event_e event)
{
.bytes = (const uint8_t *)&pkt,
.num_bytes = sizeof(control_app_switch_t),
- .delay = 0,
.tracking_id = APP_LIB_DATA_NO_TRACKING_ID,
.qos = APP_LIB_DATA_QOS_NORMAL,
.flags = APP_LIB_DATA_SEND_FLAG_NONE,
@@ -186,8 +189,6 @@ void App_init(const app_global_functions_t * functions)
return;
}
- Button_init();
-
app_res = lib_settings->setNodeRole(APP_LIB_SETTINGS_ROLE_ADVERTISER);
if (app_res != APP_RES_OK)
{
diff --git a/source/example_apps/control_node/config.mk b/source/example_apps/control_node/config.mk
index 36a2889e..b5ec5f4a 100644
--- a/source/example_apps/control_node/config.mk
+++ b/source/example_apps/control_node/config.mk
@@ -1,5 +1,5 @@
# Boards compatible with this app
-TARGET_BOARDS := silabs_brd4254a efr32_template pca10059 silabs_brd4180b pca10056 nrf52_template silabs_brd4184a silabs_brd4181b promistel_rpi_hat pca10100 ublox_b204 tbsense2 pca10112 pca10040 bgm220-ek4314a wuerth_261101102 silabs_brd4210a mdbt50q_rx nrf52832_mdk_v2 ruuvitag pan1780 silabs_brd4312a silabs_brd4253a
+TARGET_BOARDS := silabs_brd2703a silabs_brd2601b silabs_brd4187c
#
# Network default settings configuration
#
diff --git a/source/example_apps/control_router/app.c b/source/example_apps/control_router/app.c
index 1eed4b6d..f139f18c 100644
--- a/source/example_apps/control_router/app.c
+++ b/source/example_apps/control_router/app.c
@@ -22,7 +22,11 @@
#include "../control_node/common.h"
#define DEBUG_LOG_MODULE_NAME "ROUT APP"
+#ifdef DEBUG_LOG_MAX_LEVEL_APP
+#define DEBUG_LOG_MAX_LEVEL DEBUG_LOG_MAX_LEVEL_APP
+#else
#define DEBUG_LOG_MAX_LEVEL LVL_INFO
+#endif
#include "debug_log.h"
/** Control router type for shared appconfig. */
@@ -118,8 +122,6 @@ static app_lib_data_receive_res_e received_switch_cb(
{
.bytes = (const uint8_t *)&swtch_fwd,
.num_bytes = sizeof(control_app_switch_fwd_t),
- /* Propagate the travel time of the packet. */
- .delay = data->delay,
.tracking_id = APP_LIB_DATA_NO_TRACKING_ID,
.qos = APP_LIB_DATA_QOS_NORMAL,
/* This packet will only be received by CSMA nodes. */
@@ -275,8 +277,6 @@ void App_init(const app_global_functions_t * functions)
return;
}
- Led_init();
-
ctrl_ret = Control_Router_init(&conf);
if (ctrl_ret != CONTROL_RET_OK)
{
diff --git a/source/example_apps/control_router/config.mk b/source/example_apps/control_router/config.mk
index 5ee4ef48..40ded62f 100644
--- a/source/example_apps/control_router/config.mk
+++ b/source/example_apps/control_router/config.mk
@@ -1,5 +1,5 @@
# Boards compatible with this app
-TARGET_BOARDS := silabs_brd4254a efr32_template pca10059 silabs_brd4180b pca10056 nrf52_template silabs_brd4184a silabs_brd4181b promistel_rpi_hat pca10100 ublox_b204 tbsense2 pca10112 pca10040 bgm220-ek4314a wuerth_261101102 silabs_brd4210a mdbt50q_rx nrf52832_mdk_v2 ruuvitag pan1780 silabs_brd4312a silabs_brd4253a
+TARGET_BOARDS := silabs_brd2703a silabs_brd2601b silabs_brd4187c
#
# Network default settings configuration
#
@@ -20,6 +20,7 @@ default_network_channel ?= 3
# Define a specific application area_id
app_specific_area_id=0x8030B3
+
# App version
app_major=$(sdk_major)
app_minor=$(sdk_minor)
diff --git a/source/example_apps/control_router/makefile b/source/example_apps/control_router/makefile
index 8f91ae9d..5ed3d2f8 100644
--- a/source/example_apps/control_router/makefile
+++ b/source/example_apps/control_router/makefile
@@ -1,6 +1,7 @@
# Enable shared data library (needed by control library)
SHARED_DATA=yes
+
# Enable Control library (for router)
CONTROL_ROUTER=yes
diff --git a/source/example_apps/custom_app/app.c b/source/example_apps/custom_app/app.c
index dc8c2b4f..fe900829 100644
--- a/source/example_apps/custom_app/app.c
+++ b/source/example_apps/custom_app/app.c
@@ -60,7 +60,6 @@ static uint32_t send_data_task(void)
data_to_send.src_endpoint = DATA_EP;
data_to_send.dest_endpoint = DATA_EP;
data_to_send.qos = APP_LIB_DATA_QOS_HIGH;
- data_to_send.delay = 0;
data_to_send.flags = APP_LIB_DATA_SEND_FLAG_NONE;
data_to_send.tracking_id = APP_LIB_DATA_NO_TRACKING_ID;
diff --git a/source/example_apps/custom_app/config.mk b/source/example_apps/custom_app/config.mk
index 136bcc01..5abeb689 100644
--- a/source/example_apps/custom_app/config.mk
+++ b/source/example_apps/custom_app/config.mk
@@ -1,5 +1,5 @@
# Boards compatible with this app
-TARGET_BOARDS := silabs_brd4254a efr32_template pca10059 silabs_brd4180b pca10056 nrf52_template silabs_brd4184a silabs_brd4181b promistel_rpi_hat pca10100 ublox_b204 tbsense2 pca10112 pca10040 bgm220-ek4314a wuerth_261101102 silabs_brd4210a mdbt50q_rx nrf52832_mdk_v2 ruuvitag pan1780 silabs_brd4312a silabs_brd4253a
+TARGET_BOARDS := silabs_brd2703a silabs_brd2601b silabs_brd4187c
#
# Network default settings configuration
#
diff --git a/source/example_apps/evaluation_app/Readme.md b/source/example_apps/evaluation_app/Readme.md
deleted file mode 100644
index b21ace4b..00000000
--- a/source/example_apps/evaluation_app/Readme.md
+++ /dev/null
@@ -1,209 +0,0 @@
-# Evaluation application
-
-## Application scope
-
-This application is an evaluation application (i.e some sort of hello world)
-allowing to discover Wirepas Massive network capabilities. It embeds some use cases
-to generate and process messages from a node it is running on.
-
-This application provides to a node the following capabilities:
-* Send messages to a sink
- - a periodic message is sent at a configurable interval
- - a message is sent when a node's button is pressed
-
-* Receive messages from a sink
- - to control a node's LEDs state (i.e switch ON or OFF)
- - to change the period of the periodic message
-
-* Execute some requests coming from a sink
- - to return a node's LED state (i.e is the LED ON or OFF ?)
- - to return the message travel time from sink to node
-
-The python script found in the **backend_scripts** folder allows a user to interact
-with the nodes running the app using the **wirepas-gateway-API** if the nodes are part of a
-Wirepas Massive Network connected to a Wirepas gateway. In this configuration, a remote communication
-channel can be established via MQTT protocol as commands (described above) sent by the user are published
-on dedicated MQTT topics from which gateway can read and parse to send them to the Wirepas Massive network. By
-subscribing to dedicated topics the user can also get messages (from the set listed above) coming from nodes
-running the Evaluation application. See Readme.md file provided with the script to get more information about
-its usage and how communication via wirepas-gateway-API is handled.
-
-## Application API
-
-From a communication point, to send and receive data this application:
-* supports both unicast & broadcast addressing mode
- meaning it will only process messages intended for the node it is running on
- or intended to all the nodes within the network
-
-* integrates the endpoint functionnality of Wirepas which corresponds to
- an application channel (E.g. if node has multiple sensors it could use
- different endpoint to send/receive each sensor’s data).
- In this software, all messages have a dedicated source and destination
- endpoint fixed to the value 1
-
-* receives and generates internal Wirepas Massive network packet format with a specific
- payload format (\\) for each
- messages. See the "Message description" section to get all message' data format.
-
-* supports the configuration of one application parameter via the "Application data configuration" (app config)
-feature of Wirepas Massive stack
- meaning it can receive network wide persistent message
-
-### Messages description
-This section covers the description of the evaluation application supported
-messages (sent or received) which are :
-* a periodic message with a configurable interval
-* a set periodic message period
-* a button was pressed
-* a LED set state
-* a LED get state request
-* a LED get state response
-* a message travel time from sink to node calculation request (echo request)
-* a travel time response (echo response)
-
-All these message's data formats are explained in the following sections.
-The general format is \\ and all
-fields are expressed in little-endian format.
-
-#### Periodic message
-This message format is :
-\\\.
-
-The table given below presents the field byte size and meaning:
-
-| FIELD | SIZE | DESCRIPTION |
-| :---: |:---: | :---: |
-| Message ID | 1 | Message identifier. Decimal Value is 0 |
-| Counter value | 4 | Running counter value (starting from 0 with an increment step of 1) |
-| Data pattern | 8 | Fixed binary pattern: “0x0A 0x0B 0x0B 0x0A 0x0A 0x0C 0x0D 0x0C” |
-
-#### Set periodic message period
-This message format is :
-\\.
-
-The table given below presents the field bytes size and meaning:
-
-| FIELD | SIZE | DESCRIPTION |
-| :---: |:---: | :---: |
-| Message ID | 1 | Message identifier. Decimal Value is 128 |
-| New period value | 4 | Interval value expressed in milliseconds (2000-1200000, default 10000) |
-
-#### Set measurement rate via "app config" (network wide persistent message)
-This message format follows the rules of all messages delivered with Shared_AppConfig, described in the file shared_appconfig.md located in libraries\shared_appconfig folder.
-\\\\\
-The table given below presents the field byte size and meaning:
-
-| FIELD | SIZE | DESCRIPTION |
-| :---: |:---: | :---: |
-| AppConfig Header | 2 | App config header on 2 bytes, fixed pattern : "0xF6 0x7E" |
-| TLV entries Nb | 1 | Number of TLV (Type/ Length/ Value) entries contained in the message. In basic case, this is equal to 1 (One entry for the measurement period)|
-| Type | 1 | Message type. To set the mesurement rate, the type to set is "0xC3"|
-| Length | 1 | Length of the value on 1 byte. For the measurment rate, the length is 4.
-| Value | 1 | Value of the measurement rate in seconds.
-
-
-#### Button pressed notification message
-This message format is :
-\\